diff --git a/.github/workflows/bsp_buildings.yml b/.github/workflows/bsp_buildings.yml index 95f5edd46cb..cce98770fef 100644 --- a/.github/workflows/bsp_buildings.yml +++ b/.github/workflows/bsp_buildings.yml @@ -326,6 +326,17 @@ jobs: - "bluetrum/ab32vg1-ab-prougen" - "bouffalo_lab/bl60x" - "bouffalo_lab/bl70x" + - RTT_BSP: "hpmicro" + RTT_TOOL_CHAIN: "RISC-V-GCC-RV32" + SUB_RTT_BSP: + - "hpmicro/hpm6750evkmini" + - "hpmicro/hpm6750evk" + - "hpmicro/hpm6750evk2" + - "hpmicro/hpm6300evk" + - "hpmicro/hpm6200evk" + - "hpmicro/hpm5300evk" + - "hpmicro/hpm5301evklite" + - "hpmicro/hpm6800evk" - RTT_BSP: "llvm-arm" RTT_TOOL_CHAIN: "llvm-arm" SUB_RTT_BSP: @@ -406,6 +417,14 @@ jobs: /opt/riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-gcc --version echo "RTT_EXEC_PATH=/opt/riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14/bin" >> $GITHUB_ENV + - name: Install riscv32-unknown-elf Toolchains + if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'RISC-V-GCC-RV32' && success() }} + run: | + wget -q https://github.com/hpmicro/riscv-gnu-toolchain/releases/download/2022.05.15/riscv32-unknown-elf-newlib-multilib_2022.05.15_linux.tar.gz + sudo tar zxf riscv32-unknown-elf-newlib-multilib_2022.05.15_linux.tar.gz -C /opt + /opt/riscv32-unknown-elf-newlib-multilib/bin/riscv32-unknown-elf-gcc --version + echo "RTT_EXEC_PATH=/opt/riscv32-unknown-elf-newlib-multilib/bin/" >> $GITHUB_ENV + - name: Install Riscv-none-embed ToolChains if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-riscv-none-embed' && success() }} run: | diff --git a/bsp/hpmicro/.ignore_format.yml b/bsp/hpmicro/.ignore_format.yml index cad99bf4706..65bf18b330a 100644 --- a/bsp/hpmicro/.ignore_format.yml +++ b/bsp/hpmicro/.ignore_format.yml @@ -8,4 +8,7 @@ dir_path: - hpm6750evk/startup - hpm6750evk2/startup - hpm6750evkmini/startup + - hpm5300evk/startup + - hpm5301evklite/startup + - hpm6800evk/startup - libraries/hpm_sdk diff --git a/bsp/hpmicro/hpm5300evk/.config b/bsp/hpmicro/hpm5300evk/.config new file mode 100644 index 00000000000..1bd33fdf9b3 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/.config @@ -0,0 +1,1061 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=1024 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024 + +# +# kservice optimization +# +# CONFIG_RT_USING_TINY_FFS is not set + +# +# klibc optimization +# +# CONFIG_RT_KLIBC_USING_STDLIB is not set +# CONFIG_RT_KLIBC_USING_TINY_SIZE is not set +# CONFIG_RT_KLIBC_USING_PRINTF_LONGLONG is not set +# CONFIG_RT_USING_DEBUG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +# CONFIG_RT_USING_SCHED_THREAD_CTX is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x50200 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# CONFIG_RT_USING_CACHE is not set +# CONFIG_RT_USING_HW_ATOMIC is not set +# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_USING_HW_THREAD_SELF is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +CONFIG_RT_USING_LEGACY=y +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_USING_SERIAL_V1 is not set +CONFIG_RT_USING_SERIAL_V2=y +# CONFIG_RT_SERIAL_USING_DMA is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set + +# +# peripheral libraries and drivers +# + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ESP_IDF is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set + +# +# Uncategorized +# + +# +# Hardware Drivers Config +# +CONFIG_SOC_HPM5000=y + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +CONFIG_BSP_UART0_RX_BUFSIZE=128 +CONFIG_BSP_UART0_TX_BUFSIZE=0 +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART7 is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_GPTMR is not set +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_XPI_FLASH is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_USB is not set +# CONFIG_BSP_USING_EWDG is not set +# CONFIG_BSP_USING_MCAN is not set +# CONFIG_BSP_USING_ADC is not set diff --git a/bsp/hpmicro/hpm5300evk/Kconfig b/bsp/hpmicro/hpm5300evk/Kconfig new file mode 100644 index 00000000000..79b160b8567 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/Kconfig @@ -0,0 +1,21 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" diff --git a/bsp/hpmicro/hpm5300evk/README.md b/bsp/hpmicro/hpm5300evk/README.md new file mode 100644 index 00000000000..4e6ad210a66 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/README.md @@ -0,0 +1,113 @@ +# HPMicro HPM5300EVK BSP(Board Support Package) Introduction + +[中文页](README_zh.md) | + +## Introduction + +This document provides brief introduction of the BSP (board support package) for the HPM5300EVK development board. + +The document consists of the following parts: + +- HPM5300EVK Board Resources Introduction +- Quickly Getting Started +- Refreences + +By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources. + +## Board Resources Introduction + +HPM5300EVK is a development board based on the RISC-V core launched by HPMicro, with rich on-board resources and on-chip resources for motor control, etc. +![board](figures/board.png) + + +## Peripheral Condition + +Each peripheral supporting condition for this BSP is as follows: + + +| **On-board Peripherals** | **Support** | **Note** | +| ------------------------ | ----------- | ------------------------------------- | +| USB | √ | | +| QSPI Flash | √ | | +| GPIO | √ | | +| SPI | √ | | +| I2C | √ | | +| CAN | √ | | +| On-Board Debugger | √ | ft2232 | + + +## Execution Instruction + +### Quickly Getting Started + +The BSP support being build via the 'scons' command, below is the steps of compiling the example via the 'scons' command + +#### Parpare Environment +- Step 1: Prepare [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool) +- Step 2: Prepare [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) + - Download the package and extract it into a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain` +- Step 3: Set environment variable `RTT_RISCV_TOOLCHAIN` to `\bin` + - For example: `C:\DevTools\riscv32-gnu-toolchain\bin` +- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip) + - Download and extract it to specified directory, for example: `C:\DevTools\openocd-hpmicro` + - Add `OpenOCD` environment variable `OPENOCD_HPMICRO` to `\bin` + - For example: `C:\DevTools\openocd-hpmicro\bin` + +#### Configure and Build project + +Open RT-Thread ENV command-line, and change directory to this BSP directory, then users can: + +- Configure the project via `menuconfig` in `RT-Thread ENV` +- Build the project using `scons -jN`, `N` equals to the number of CPU cores +- Clean the project using `scons -c` + +#### Hardware Connection + +- Switch BOOT pin to 2'b00 +- Connect the `PWR_DEBUG` port to PC via TYPE-C cable + + +#### Dowload / Debug + +- Users can download the project via the below command: + ```console + %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm5300.cfg -f boards\debug_scripts\boards\hpm5300evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + ``` + +- Users can debug the project via the below command: + + - Connect debugger via `OpenOCD`: + +```console +%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm5300.cfg -f boards\debug_scripts\boards\hpm5300evk.cfg +``` + - Start Debugger via `GDB`: + +```console +%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf +``` + - In the `gdb shell`, type the following commands: + +```console +load +c +``` + +### **Running Results** + +Once the project is successfully downloaded, the system runs automatically. The LED on the board will flash periodically. + +Connect the serial port of the board to the PC, communicate with it via a serial terminal tool(115200-8-1-N). Reset the board and the startup information of RT-Thread will be observed: + +``` + \ | / +- RT - Thread Operating System + / | \ 5.1.0 build Aug 16 2023 18:18:18 + 2006 - 2024 Copyright by RT-Thread team +``` + +## **References** + +- [RT-Thread Documnent Center](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README) +- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md) +- [HPM5300EVK RT-Thread BSP Package](https://github.com/hpmicro/rtt-bsp-hpm5300evk) \ No newline at end of file diff --git a/bsp/hpmicro/hpm5300evk/README_zh.md b/bsp/hpmicro/hpm5300evk/README_zh.md new file mode 100644 index 00000000000..9b7086ddc10 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/README_zh.md @@ -0,0 +1,112 @@ +# 先楫 HPM5300EVK BSP(板级支持包)说明 + +[English](README.md) | + +## 简介 + +本文档为 HPM5300EVK 的 BSP (板级支持包) 说明。 + +本文包含如下部分: + +- HPM5300EVK 板级资源介绍 +- 快速上手指南 +- 参考链接 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 板级资源介绍 + + HPM5300EVK 是由先楫半导体推出的一款基于RISCV内核的开发板，带有丰富的片上资源和板上资源，可用于电机控制等应用。 + +开发板外观如下图所示： + +![board](figures/board.png) + + +## 板载外设 + +本 BSP 目前对外设的支持情况如下: + + +| **板载外设** | **支持情况** | **备注** | +| ------------------------ | ----------- | ------------------------------------- | +| USB | √ | | +| QSPI Flash | √ | | +| GPIO | √ | | +| SPI | √ | | +| I2C | √ | | +| CAN | √ | | +| 板载调试器 | √ | ft2232 | + + +## 使用说明 + +### 快速开始 + +本BSP支持通过`scons`命令来完成编译，在开始之前，需要先准备好开发所需的环境。 + +#### 准备环境 +- 步骤 1: 准备 [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool) +- 步骤 2: 准备 [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) + - 下载并解压到指定的目录，如: `C:\DevTools\riscv32-gnu-toolchain` +- 步骤 3: 设置环境变量： `RTT_RISCV_TOOLCHAIN` 为 `\bin`， 如: `C:\DevTools\riscv32-gnu-toolchain\bin` +- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip) + - 下载并解压到指定目录，如: `C:\DevTools\openocd-hpmicro` + - 将 `OPENOCD_HPMICRO`环境变量设置为 `\bin`，如： `C:\DevTools\openocd-hpmicro\bin` + +#### 配置和构建工程 + +通过 RT-Thread ENV 命令行切换目录到当前BSP所在目录后，用户可以: + +- 通过 `menuconfig` 命令 配置RT-Thread BSP的功能 +- 通过 `scons -jN` 命令完成构建, 其中`N` 最大值可以指定为CP拥有的物理内核数 +- 通过 `scons -c` 命令清除构建 + +#### 硬件连接 + +- 将BOOT 引脚拨到2'b00 +- 通过 TYPE-C线将板上的 `PWR_DEBUG` 连接到电脑 + +#### 下载 和 调试 + +- 通过如下命令完成下载: + ```console + %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\cmsis_dap.cfg -f boards\debug_scripts\soc\hpm5300.cfg -f boards\debug_scripts\boards\hpm5300evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + ``` + +- 通过如下命令实现调试: + + - 通过 `OpenOCD` 来连接开发板: +```console +%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm5300.cfg -f boards\debug_scripts\boards\hpm5300evk.cfg +``` + - 通过 `GDB` 实现调试: +```console +%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf +``` + + - 在`GDB Shell`中使用如下命令来加载和运行: + +```console +load +c +``` + +### **运行结果** + +一旦成功下载，程序会自动运行并打印如下结果，板载LED灯会周期性闪烁。 + +配置好串口终端(串口配置为115200, 8-N-1),按复位键后，串口终端会打印如下日志： + +``` + \ | / +- RT - Thread Operating System + / | \ 5.1.0 build Aug 16 2023 18:18:18 + 2006 - 2023 Copyright by RT-Thread team +``` + +## **参考链接** + +- [RT-Thread 文档中心](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README) +- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md) +- [HPM5300EVK RT-Thread BSP 包](https://github.com/hpmicro/rtt-bsp-hpm5300evk) \ No newline at end of file diff --git a/bsp/hpmicro/hpm5300evk/SConscript b/bsp/hpmicro/hpm5300evk/SConscript new file mode 100644 index 00000000000..014c428d0a3 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/SConscript @@ -0,0 +1,17 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +ASFLAGS = ' -I' + cwd + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/hpmicro/hpm5300evk/SConstruct b/bsp/hpmicro/hpm5300evk/SConstruct new file mode 100644 index 00000000000..3dadc575c01 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/SConstruct @@ -0,0 +1,75 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../../rt-thread') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +AddOption('--run', + dest = 'run', + type='string', + nargs=1, + action = 'store', + default = "", + help = 'Upload or debug application using openocd') + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(os.path.join(SDK_ROOT, 'libraries')): + libraries_path_prefix = os.path.join(SDK_ROOT, 'libraries') +else: + libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries') + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + + +GDB = rtconfig.GDB + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +hpm_library = 'hpm_sdk' +rtconfig.BSP_LIBRARY_TYPE = hpm_library + +# include soc +objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.CHIP_NAME, 'SConscript'))) + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript'))) + +# include components +objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript'))) + + +# includes rtt drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/hpmicro/hpm5300evk/applications/SConscript b/bsp/hpmicro/hpm5300evk/applications/SConscript new file mode 100644 index 00000000000..a65aa4d8553 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/applications/SConscript @@ -0,0 +1,14 @@ +import rtconfig + +from building import * + +cwd = GetCurrentDir() + +src = Glob('*.c') + +CPPDEFINES=[] +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm5300evk/applications/main.c b/bsp/hpmicro/hpm5300evk/applications/main.c new file mode 100644 index 00000000000..0bbf6370382 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/applications/main.c @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2021 hpmicro + * + * Change Logs: + * Date Author Notes + * 2021-08-13 Fan YANG first version + * + */ + +#include +#include +#include "rtt_board.h" +#include + +void thread_entry(void *arg); + + +int main(void) +{ + static uint32_t led_thread_arg = 0; + rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10); + rt_thread_startup(led_thread); + + return 0; +} + + +void thread_entry(void *arg) +{ + rt_pin_mode(APP_LED0_PIN_NUM, PIN_MODE_OUTPUT); + + while(1){ + rt_pin_write(APP_LED0_PIN_NUM, APP_LED_ON); + rt_thread_mdelay(500); + rt_pin_write(APP_LED0_PIN_NUM, APP_LED_OFF); + rt_thread_mdelay(500); + } +} diff --git a/bsp/hpmicro/hpm5300evk/board/Kconfig b/bsp/hpmicro/hpm5300evk/board/Kconfig new file mode 100644 index 00000000000..20bc12d04ba --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/Kconfig @@ -0,0 +1,236 @@ +menu "Hardware Drivers Config" + +config SOC_HPM5000 + bool + select SOC_SERIES_HPM5300 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN if BSP_USING_GPIO + default n + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + + if BSP_USING_UART + menuconfig BSP_USING_UART0 + bool "Enable UART0 (Debugger)" + default y + if BSP_USING_UART0 + config BSP_UART0_RX_USING_DMA + bool "Enable UART0 RX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + config BSP_UART0_TX_USING_DMA + bool "Enable UART0 TX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + config BSP_UART0_RX_BUFSIZE + int "Set UART0 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART0_TX_BUFSIZE + int "Set UART0 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + menuconfig BSP_USING_UART2 + bool "Enable UART2" + default y + if BSP_USING_UART2 + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default y + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + config BSP_UART2_RX_BUFSIZE + int "Set UART2 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART2_TX_BUFSIZE + int "Set UART2 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + menuconfig BSP_USING_UART7 + bool "Enable UART7" + default n + if BSP_USING_UART7 + config BSP_UART7_RX_USING_DMA + bool "Enable UART7 RX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + config BSP_UART7_TX_USING_DMA + bool "Enable UART7 TX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + config BSP_UART7_RX_BUFSIZE + int "Set UART7 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART7_TX_BUFSIZE + int "Set UART7 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI" + default n + select RT_USING_SPI if BSP_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1" + default y + if BSP_USING_SPI1 + config BSP_SPI1_USING_DMA + bool "Enable SPI1 DMA" + default n + endif + config BSP_USING_SPI2 + bool "Enable SPI2" + default n + if BSP_USING_SPI2 + config BSP_SPI2_USING_DMA + bool "Enable SPI2 DMA" + default n + endif + config BSP_USING_SPI3 + bool "Enable SPI3" + default n + if BSP_USING_SPI3 + config BSP_SPI3_USING_DMA + bool "Enable SPI3 DMA" + default n + endif + endif + + menuconfig BSP_USING_GPTMR + bool "Enable GPTMR" + default n + select RT_USING_HWTIMER if BSP_USING_GPTMR + if BSP_USING_GPTMR + config BSP_USING_GPTMR1 + bool "Enable GPTMR1" + default n + config BSP_USING_GPTMR2 + bool "Enable GPTMR2" + default n + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C" + default n + if BSP_USING_I2C + config BSP_USING_I2C0 + bool "Enable I2C0" + default y + if BSP_USING_I2C0 + config BSP_I2C0_USING_DMA + bool "Enable I2C0 DMA" + default n + endif + + config BSP_USING_I2C3 + bool "Enable I2C3" + default n + if BSP_USING_I2C3 + config BSP_I2C3_USING_DMA + bool "Enable I2C3 DMA" + default n + endif + endif + + menuconfig BSP_USING_XPI_FLASH + bool "Enable XPI FLASH" + default n + select RT_USING_FAL if BSP_USING_XPI_FLASH + + menuconfig BSP_USING_PWM + bool "Enable PWM" + default n + + menuconfig BSP_USING_USB + bool "Enable USB" + default n + if BSP_USING_USB + config BSP_USING_USB_DEVICE + bool "Enable USB Device" + default n + config BSP_USING_USB_HOST + bool "Enable USB HOST" + select RT_USING_CACHE + default n + endif + + menuconfig BSP_USING_EWDG + bool "Enable EWDG" + default n + select RT_USING_WDT if BSP_USING_EWDG + if BSP_USING_EWDG + config BSP_USING_EWDG0 + bool "Enable EWDG0" + default n + config BSP_USING_EWDG1 + bool "Enable EWDG1" + default n + endif + + menuconfig BSP_USING_MCAN + bool "Enable MCAN" + default n + select RT_USING_CAN if BSP_USING_MCAN + if BSP_USING_MCAN + config BSP_USING_MCAN0 + bool "Enable MCAN0" + default n + config BSP_USING_MCAN1 + bool "Enable MCAN1" + default n + config BSP_USING_MCAN2 + bool "Enable MCAN2" + default n + config BSP_USING_MCAN3 + bool "Enable MCAN3" + default n + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC if BSP_USING_ADC + if BSP_USING_ADC + menuconfig BSP_USING_ADC16 + bool "Enable ADC16" + default y + if BSP_USING_ADC16 + config BSP_USING_ADC0 + bool "Enable ADC0" + default y + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + config BSP_USING_ADC2 + bool "Enable ADC2" + default n + endif + endif +endmenu + +endmenu diff --git a/bsp/hpmicro/hpm5300evk/board/SConscript b/bsp/hpmicro/hpm5300evk/board/SConscript new file mode 100644 index 00000000000..dcd1e3543fd --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/SConscript @@ -0,0 +1,18 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers +src = Split(""" + board.c + rtt_board.c + pinmux.c + fal_flash_port.c +""") + +CPPPATH = [cwd] +CPPDEFINES=['D25', 'HPM5361'] + +group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm5300evk/board/board.c b/bsp/hpmicro/hpm5300evk/board/board.c new file mode 100644 index 00000000000..ce3f1ee0cee --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/board.c @@ -0,0 +1,662 @@ +/* + * Copyright (c) 2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "board.h" +#include "hpm_uart_drv.h" +#include "hpm_gptmr_drv.h" +#include "hpm_gpio_drv.h" +#include "hpm_usb_drv.h" +#include "hpm_clock_drv.h" +#include "hpm_pllctlv2_drv.h" +#include "hpm_i2c_drv.h" +#include "hpm_pcfg_drv.h" + +static board_timer_cb timer_cb; + +/** + * @brief FLASH configuration option definitions: + * option[0]: + * [31:16] 0xfcf9 - FLASH configuration option tag + * [15:4] 0 - Reserved + * [3:0] option words (exclude option[0]) + * option[1]: + * [31:28] Flash probe type + * 0 - SFDP SDR / 1 - SFDP DDR + * 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) + * 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V + * 6 - OctaBus DDR (SPI -> OPI DDR) + * 8 - Xccela DDR (SPI -> OPI DDR) + * 10 - EcoXiP DDR (SPI -> OPI DDR) + * [27:24] Command Pads after Power-on Reset + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [23:20] Command Pads after Configuring FLASH + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) + * 0 - Not needed + * 1 - QE bit is at bit 6 in Status Register 1 + * 2 - QE bit is at bit1 in Status Register 2 + * 3 - QE bit is at bit7 in Status Register 2 + * 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 + * [15:8] Dummy cycles + * 0 - Auto-probed / detected / default value + * Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet + * [7:4] Misc. + * 0 - Not used + * 1 - SPI mode + * 2 - Internal loopback + * 3 - External DQS + * [3:0] Frequency option + * 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz + * + * option[2] (Effective only if the bit[3:0] in option[0] > 1) + * [31:20] Reserved + * [19:16] IO voltage + * 0 - 3V / 1 - 1.8V + * [15:12] Pin group + * 0 - 1st group / 1 - 2nd group + * [11:8] Connection selection + * 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) + * [7:0] Drive Strength + * 0 - Default value + * option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports + * JESD216) + * [31:16] reserved + * [15:12] Sector Erase Command Option, not required here + * [11:8] Sector Size Option, not required here + * [7:0] Flash Size Option + * 0 - 4MB / 1 - 8MB / 2 - 16MB + */ +#if defined(FLASH_XIP) && FLASH_XIP +__attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90002, 0x00000006, 0x1000, 0x0}; +#endif + +#if defined(FLASH_UF2) && FLASH_UF2 +ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; +#endif + +void board_init_console(void) +{ +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART + console_config_t cfg; + + /* uart needs to configure pin function before enabling clock, otherwise the level change of + * uart rx pin when configuring pin function will cause a wrong data to be received. + * And a uart rx dma request will be generated by default uart fifo dma trigger level. + */ + init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE); + + /* Configure the UART clock to 24MHz */ + clock_set_source_divider(BOARD_CONSOLE_UART_CLK_NAME, clk_src_osc24m, 1U); + clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0); + + cfg.type = BOARD_CONSOLE_TYPE; + cfg.base = (uint32_t)BOARD_CONSOLE_UART_BASE; + cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_UART_CLK_NAME); + cfg.baudrate = BOARD_CONSOLE_UART_BAUDRATE; + + if (status_success != console_init(&cfg)) { + /* failed to initialize debug console */ + while (1) { + } + } +#else + while (1) + ; +#endif +#endif +} + +void board_print_banner(void) +{ + const uint8_t banner[] = "\n" +"----------------------------------------------------------------------\n" +"$$\\ $$\\ $$$$$$$\\ $$\\ $$\\ $$\\\n" +"$$ | $$ |$$ __$$\\ $$$\\ $$$ |\\__|\n" +"$$ | $$ |$$ | $$ |$$$$\\ $$$$ |$$\\ $$$$$$$\\ $$$$$$\\ $$$$$$\\\n" +"$$$$$$$$ |$$$$$$$ |$$\\$$\\$$ $$ |$$ |$$ _____|$$ __$$\\ $$ __$$\\\n" +"$$ __$$ |$$ ____/ $$ \\$$$ $$ |$$ |$$ / $$ | \\__|$$ / $$ |\n" +"$$ | $$ |$$ | $$ |\\$ /$$ |$$ |$$ | $$ | $$ | $$ |\n" +"$$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\n" +"\\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n" +"----------------------------------------------------------------------\n"; +#ifdef SDK_VERSION_STRING + printf("hpm_sdk: %s\n", SDK_VERSION_STRING); +#endif + printf("%s", banner); +} + +void board_print_clock_freq(void) +{ + printf("==============================\n"); + printf(" %s clock summary\n", BOARD_NAME); + printf("==============================\n"); + printf("cpu0:\t\t %luHz\n", clock_get_frequency(clock_cpu0)); + printf("ahb:\t\t %luHz\n", clock_get_frequency(clock_ahb)); + printf("mchtmr0:\t %luHz\n", clock_get_frequency(clock_mchtmr0)); + printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0)); + printf("==============================\n"); +} + +void board_init(void) +{ + init_xtal_pins(); + init_py_pins_as_pgpio(); + board_init_usb_dp_dm_pins(); + + board_init_clock(); + board_init_console(); + board_init_pmp(); +#if BOARD_SHOW_CLOCK + board_print_clock_freq(); +#endif +#if BOARD_SHOW_BANNER + board_print_banner(); +#endif +} + +void board_init_usb_dp_dm_pins(void) +{ + /* Disconnect usb dp/dm pins pull down 45ohm resistance */ + + while (sysctl_resource_any_is_busy(HPM_SYSCTL)) { + ; + } + if (pllctlv2_xtal_is_stable(HPM_PLLCTLV2) && pllctlv2_xtal_is_enabled(HPM_PLLCTLV2)) { + if (clock_check_in_group(clock_usb0, 0)) { + usb_phy_disable_dp_dm_pulldown(HPM_USB0); + } else { + clock_add_to_group(clock_usb0, 0); + usb_phy_disable_dp_dm_pulldown(HPM_USB0); + clock_remove_from_group(clock_usb0, 0); + } + } else { + uint8_t tmp; + tmp = sysctl_resource_target_get_mode(HPM_SYSCTL, sysctl_resource_xtal); + sysctl_resource_target_set_mode(HPM_SYSCTL, sysctl_resource_xtal, 0x03); + clock_add_to_group(clock_usb0, 0); + usb_phy_disable_dp_dm_pulldown(HPM_USB0); + clock_remove_from_group(clock_usb0, 0); + while (sysctl_resource_target_is_busy(HPM_SYSCTL, sysctl_resource_usb0)) { + ; + } + sysctl_resource_target_set_mode(HPM_SYSCTL, sysctl_resource_xtal, tmp); + } +} + +void board_init_clock(void) +{ + uint32_t cpu0_freq = clock_get_frequency(clock_cpu0); + + if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) { + /* Configure the External OSC ramp-up time: ~9ms */ + pllctlv2_xtal_set_rampup_time(HPM_PLLCTLV2, 32UL * 1000UL * 9U); + + /* Select clock setting preset1 */ + sysctl_clock_set_preset(HPM_SYSCTL, 2); + } + + /* group0[0] */ + clock_add_to_group(clock_cpu0, 0); + clock_add_to_group(clock_ahb, 0); + clock_add_to_group(clock_lmm0, 0); + clock_add_to_group(clock_mchtmr0, 0); + clock_add_to_group(clock_rom, 0); + clock_add_to_group(clock_can0, 0); + clock_add_to_group(clock_can1, 0); + clock_add_to_group(clock_can2, 0); + clock_add_to_group(clock_can3, 0); + clock_add_to_group(clock_ptpc, 0); + clock_add_to_group(clock_gptmr0, 0); + clock_add_to_group(clock_gptmr1, 0); + clock_add_to_group(clock_gptmr2, 0); + clock_add_to_group(clock_gptmr3, 0); + clock_add_to_group(clock_i2c0, 0); + clock_add_to_group(clock_i2c1, 0); + clock_add_to_group(clock_i2c2, 0); + clock_add_to_group(clock_i2c3, 0); + clock_add_to_group(clock_spi0, 0); + clock_add_to_group(clock_spi1, 0); + clock_add_to_group(clock_spi2, 0); + clock_add_to_group(clock_spi3, 0); + clock_add_to_group(clock_uart0, 0); + clock_add_to_group(clock_uart1, 0); + clock_add_to_group(clock_uart2, 0); + clock_add_to_group(clock_uart3, 0); + clock_add_to_group(clock_uart4, 0); + clock_add_to_group(clock_uart5, 0); + clock_add_to_group(clock_uart6, 0); + /* group0[1] */ + clock_add_to_group(clock_uart7, 0); + clock_add_to_group(clock_watchdog0, 0); + clock_add_to_group(clock_watchdog1, 0); + clock_add_to_group(clock_mbx0, 0); + clock_add_to_group(clock_tsns, 0); + clock_add_to_group(clock_crc0, 0); + clock_add_to_group(clock_adc0, 0); + clock_add_to_group(clock_adc1, 0); + clock_add_to_group(clock_dac0, 0); + clock_add_to_group(clock_dac1, 0); + clock_add_to_group(clock_acmp, 0); + clock_add_to_group(clock_opa0, 0); + clock_add_to_group(clock_opa1, 0); + clock_add_to_group(clock_mot0, 0); + clock_add_to_group(clock_rng, 0); + clock_add_to_group(clock_sdp, 0); + clock_add_to_group(clock_kman, 0); + clock_add_to_group(clock_gpio, 0); + clock_add_to_group(clock_hdma, 0); + clock_add_to_group(clock_xpi0, 0); + clock_add_to_group(clock_usb0, 0); + + /* Connect Group0 to CPU0 */ + clock_connect_group_to_cpu(0, 0); + + /* Bump up DCDC voltage to 1175mv */ + pcfg_dcdc_set_voltage(HPM_PCFG, 1175); + + /* Configure CPU to 480MHz, AXI/AHB to 160MHz */ + sysctl_config_cpu0_domain_clock(HPM_SYSCTL, clock_source_pll0_clk0, 2, 3); + /* Configure PLL0 Post Divider */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 0, 0); /* PLL0CLK0: 960MHz */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 1, 3); /* PLL0CLK1: 600MHz */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 2, 7); /* PLL0CLK2: 400MHz */ + /* Configure PLL0 Frequency to 960MHz */ + pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 0, 960000000); + + clock_update_core_clock(); + + /* Configure mchtmr to 24MHz */ + clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1); +} + +void board_delay_us(uint32_t us) +{ + clock_cpu_delay_us(us); +} + +void board_delay_ms(uint32_t ms) +{ + clock_cpu_delay_ms(ms); +} + +void board_timer_isr(void) +{ + if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) { + gptmr_clear_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH)); + timer_cb(); + } +} +SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr); + +void board_timer_create(uint32_t ms, board_timer_cb cb) +{ + uint32_t gptmr_freq; + gptmr_channel_config_t config; + + timer_cb = cb; + gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config); + + clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0); + gptmr_freq = clock_get_frequency(BOARD_CALLBACK_TIMER_CLK_NAME); + + config.reload = gptmr_freq / 1000 * ms; + gptmr_channel_config(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH, &config, false); + gptmr_enable_irq(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_IRQ_MASK(BOARD_CALLBACK_TIMER_CH)); + intc_m_enable_irq_with_priority(BOARD_CALLBACK_TIMER_IRQ, 1); + + gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH); +} + +void board_init_gpio_pins(void) +{ + init_gpio_pins(); + gpio_set_pin_input(BOARD_APP_GPIO_CTRL, BOARD_APP_GPIO_INDEX, BOARD_APP_GPIO_PIN); +} + +void board_init_led_pins(void) +{ + init_led_pins_as_gpio(); + gpio_set_pin_output_with_initial(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, board_get_led_gpio_off_level()); +} + +void board_init_usb_pins(void) +{ + init_usb_pins(); + usb_hcd_set_power_ctrl_polarity(BOARD_USB, true); + /* Wait USB_PWR pin control vbus power stable. Time depend on decoupling capacitor, you can decrease or increase this time */ + board_delay_ms(100); + + /* As QFN32, QFN48 and LQFP64 has no vbus pin, so should be call usb_phy_using_internal_vbus() API to use internal vbus. */ + /* usb_phy_using_internal_vbus(BOARD_USB); */ +} + +void board_led_write(uint8_t state) +{ + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state); +} + +void board_led_toggle(void) +{ + gpio_toggle_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN); +} + +void board_init_uart(UART_Type *ptr) +{ + /* configure uart's pin before opening uart's clock */ + init_uart_pins(ptr); + board_init_uart_clock(ptr); +} + +void board_ungate_mchtmr_at_lp_mode(void) +{ + /* Keep cpu clock on wfi, so that mchtmr irq can still work after wfi */ + sysctl_set_cpu_lp_mode(HPM_SYSCTL, BOARD_RUNNING_CORE, cpu_lp_mode_ungate_cpu_clock); +} + +uint32_t board_init_spi_clock(SPI_Type *ptr) +{ + if (ptr == HPM_SPI1) { + clock_add_to_group(clock_spi1, 0); + return clock_get_frequency(clock_spi1); + } + return 0; +} + +void board_init_spi_pins(SPI_Type *ptr) +{ + init_spi_pins(ptr); +} + +void board_write_spi_cs(uint32_t pin, uint8_t state) +{ + gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state); +} + +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + init_spi_pins_with_gpio_as_cs(ptr); + gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN), + GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL); +} + +void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level) +{ + (void) usb_index; + (void) level; +} + +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) +{ + uint32_t freq = 0; + + if (ptr == HPM_ADC0) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll0_clk2, 2U); + } + + freq = clock_get_frequency(clock_adc0); + } else if (ptr == HPM_ADC1) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc1, clk_adc_src_ana1); + clock_set_source_divider(clock_ana1, clk_src_pll0_clk2, 2U); + } + + freq = clock_get_frequency(clock_adc1); + } + + return freq; +} + +void board_init_adc16_pins(void) +{ + init_adc_pins(); +} + +uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb) +{ + uint32_t freq = 0; + + if (ptr == HPM_DAC0) { + if (clk_src_ahb == true) { + /* Configure the DAC clock to 180MHz */ + clock_set_dac_source(clock_dac0, clk_dac_src_ahb0); + } else { + /* Configure the DAC clock to 166MHz */ + clock_set_dac_source(clock_dac0, clk_dac_src_ana2); + clock_set_source_divider(clock_ana2, clk_src_pll0_clk1, 2); + } + + freq = clock_get_frequency(clock_dac0); + } else if (ptr == HPM_DAC1) { + if (clk_src_ahb == true) { + /* Configure the DAC clock to 180MHz */ + clock_set_dac_source(clock_dac1, clk_dac_src_ahb0); + } else { + /* Configure the DAC clock to 166MHz */ + clock_set_dac_source(clock_dac1, clk_dac_src_ana3); + clock_set_source_divider(clock_ana3, clk_src_pll0_clk1, 2); + } + + freq = clock_get_frequency(clock_dac1); + } + + return freq; +} + +void board_init_can(MCAN_Type *ptr) +{ + init_can_pins(ptr); +} + +uint32_t board_init_can_clock(MCAN_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_MCAN0) { + clock_add_to_group(clock_can0, 0); + clock_set_source_divider(clock_can0, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can0); + } + if (ptr == HPM_MCAN1) { + clock_add_to_group(clock_can1, 0); + clock_set_source_divider(clock_can1, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can1); + } + if (ptr == HPM_MCAN2) { + clock_add_to_group(clock_can2, 0); + clock_set_source_divider(clock_can2, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can2); + } + if (ptr == HPM_MCAN3) { + clock_add_to_group(clock_can3, 0); + clock_set_source_divider(clock_can3, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can3); + } + return freq; +} + +uint32_t board_init_pwm_clock(PWM_Type *ptr) +{ + uint32_t freq = 0; + (void) ptr; + + clock_add_to_group(clock_mot0, 0); + freq = clock_get_frequency(clock_mot0); + + return freq; +} + +void board_init_rgb_pwm_pins(void) +{ + init_led_pins_as_pwm(); +} + +void board_disable_output_rgb_led(uint8_t color) +{ + (void) color; +} + +void board_enable_output_rgb_led(uint8_t color) +{ + (void) color; +} + +void board_init_dac_pins(DAC_Type *ptr) +{ + init_dac_pins(ptr); +} + +uint8_t board_get_led_pwm_off_level(void) +{ + return BOARD_LED_OFF_LEVEL; +} + +uint8_t board_get_led_gpio_off_level(void) +{ + return BOARD_LED_OFF_LEVEL; +} + +void board_init_pmp(void) +{ +} + +uint32_t board_init_uart_clock(UART_Type *ptr) +{ + uint32_t freq = 0U; + if (ptr == HPM_UART0) { + clock_set_source_divider(clock_uart0, clk_src_osc24m, 1); + clock_add_to_group(clock_uart0, 0); + freq = clock_get_frequency(clock_uart0); + } else if (ptr == HPM_UART1) { + clock_set_source_divider(clock_uart1, clk_src_osc24m, 1); + clock_add_to_group(clock_uart1, 0); + freq = clock_get_frequency(clock_uart1); + } else if (ptr == HPM_UART2) { + clock_set_source_divider(clock_uart2, clk_src_pll0_clk2, 8); + clock_add_to_group(clock_uart2, 0); + freq = clock_get_frequency(clock_uart2); + } else if (ptr == HPM_UART3) { + clock_set_source_divider(clock_uart3, clk_src_pll0_clk2, 8); + clock_add_to_group(clock_uart3, 0); + freq = clock_get_frequency(clock_uart3); + } else if (ptr == HPM_UART7) { + clock_set_source_divider(clock_uart7, clk_src_pll0_clk2, 6); /* 80MHz */ + clock_add_to_group(clock_uart7, 0); + freq = clock_get_frequency(clock_uart7); + } + return freq; +} + +void board_init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx) +{ + init_sei_pins(ptr, sei_ctrl_idx); +} + +void board_i2c_bus_clear(I2C_Type *ptr) +{ + if (i2c_get_line_scl_status(ptr) == false) { + printf("CLK is low, please power cycle the board\n"); + while (1) { + } + } + if (i2c_get_line_sda_status(ptr) == false) { + printf("SDA is low, try to issue I2C bus clear\n"); + } else { + printf("I2C bus is ready\n"); + return; + } + i2s_gen_reset_signal(ptr, 9); + board_delay_ms(100); + printf("I2C bus is cleared\n"); +} + +void board_init_i2c(I2C_Type *ptr) +{ + i2c_config_t config; + hpm_stat_t stat; + uint32_t freq; + if (ptr == NULL) { + return; + } + init_i2c_pins(ptr); + board_i2c_bus_clear(ptr); + + clock_add_to_group(clock_i2c0, 0); + clock_add_to_group(clock_i2c1, 0); + clock_add_to_group(clock_i2c2, 0); + clock_add_to_group(clock_i2c3, 0); + /* Configure the I2C clock to 24MHz */ + clock_set_source_divider(BOARD_APP_I2C_CLK_NAME, clk_src_osc24m, 1U); + + config.i2c_mode = i2c_mode_normal; + config.is_10bit_addressing = false; + freq = clock_get_frequency(BOARD_APP_I2C_CLK_NAME); + stat = i2c_init_master(ptr, freq, &config); + if (stat != status_success) { + printf("failed to initialize i2c 0x%x\n", (uint32_t) ptr); + while (1) { + } + } + +} + +void board_init_adc_qeiv2_pins(void) +{ + init_adc_qeiv2_pins(); +} + +void board_lin_transceiver_control(bool enable) +{ + init_lin_transceiver_ctrl_pin(); + if (enable) { + gpio_set_pin_output_with_initial(BOARD_12V_EN_GPIO_CTRL, BOARD_12V_EN_GPIO_INDEX, BOARD_12V_EN_GPIO_PIN, 1); /* enable 12v output */ + gpio_set_pin_output_with_initial(BOARD_LIN_TRANSCEIVER_GPIO_CTRL, BOARD_LIN_TRANSCEIVER_GPIO_INDEX, BOARD_LIN_TRANSCEIVER_GPIO_PIN, 1); /* disable transceiver sleep */ + } else { + gpio_set_pin_output_with_initial(BOARD_12V_EN_GPIO_CTRL, BOARD_12V_EN_GPIO_INDEX, BOARD_12V_EN_GPIO_PIN, 0); /* disable 12v output */ + gpio_set_pin_output_with_initial(BOARD_LIN_TRANSCEIVER_GPIO_CTRL, BOARD_LIN_TRANSCEIVER_GPIO_INDEX, BOARD_LIN_TRANSCEIVER_GPIO_PIN, 0); /* enable transceiver sleep */ + } +} + +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) +{ + uint32_t freq = 0; + clock_name_t gptmr_clock =0; + uint32_t HPM_GPTMR = (uint32_t)ptr; + bool gptmr_valid = true; + + switch(HPM_GPTMR){ + case HPM_GPTMR0_BASE: + gptmr_clock = clock_gptmr0; + break; + case HPM_GPTMR1_BASE: + gptmr_clock = clock_gptmr1; + break; + case HPM_GPTMR2_BASE: + gptmr_clock = clock_gptmr2; + break; + case HPM_GPTMR3_BASE: + gptmr_clock = clock_gptmr3; + break; + default: + gptmr_valid = false; + } + if(gptmr_valid) + { + clock_add_to_group(gptmr_clock, 0); + clock_set_source_divider(gptmr_clock, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(gptmr_clock); + } + return freq; +} diff --git a/bsp/hpmicro/hpm5300evk/board/board.h b/bsp/hpmicro/hpm5300evk/board/board.h new file mode 100644 index 00000000000..ab2718b88e4 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/board.h @@ -0,0 +1,385 @@ +/* + * Copyright (c) 2023-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_BOARD_H +#define _HPM_BOARD_H +#include +#include +#include "hpm_common.h" +#include "hpm_clock_drv.h" +#include "hpm_soc.h" +#include "hpm_soc_feature.h" +#include "pinmux.h" +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#include "hpm_debug_console.h" +#endif + +#define BOARD_NAME "hpm5300evk" +#define BOARD_UF2_SIGNATURE (0x0A4D5048UL) + +/* ACMP desction */ +#define BOARD_ACMP HPM_ACMP +#define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 +#define BOARD_ACMP_IRQ IRQn_ACMP_1 +#define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ +#define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_4 /* align with used pin */ + +/* dma section */ +#define BOARD_APP_HDMA HPM_HDMA +#define BOARD_APP_HDMA_IRQ IRQn_HDMA +#define BOARD_APP_DMAMUX HPM_DMAMUX +#define TEST_DMA_CONTROLLER HPM_HDMA +#define TEST_DMA_IRQ IRQn_HDMA + +#ifndef BOARD_RUNNING_CORE +#define BOARD_RUNNING_CORE HPM_CORE0 +#endif + +/* uart section */ +#ifndef BOARD_APP_UART_BASE +#define BOARD_APP_UART_BASE HPM_UART2 +#define BOARD_APP_UART_IRQ IRQn_UART2 +#define BOARD_APP_UART_BAUDRATE (115200UL) +#define BOARD_APP_UART_CLK_NAME clock_uart2 +#define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART2_RX +#define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART2_TX +#endif + +/* uart lin sample section */ +#define BOARD_UART_LIN HPM_UART3 +#define BOARD_UART_LIN_IRQ IRQn_UART3 +#define BOARD_UART_LIN_CLK_NAME clock_uart3 +#define BOARD_UART_LIN_TX_PORT GPIO_DI_GPIOA +#define BOARD_UART_LIN_TX_PIN (15U) /* PA15 should align with used pin in pinmux configuration */ + + +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#ifndef BOARD_CONSOLE_TYPE +#define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART +#endif + +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART +#ifndef BOARD_CONSOLE_UART_BASE +#define BOARD_CONSOLE_UART_BASE HPM_UART0 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART0 +#define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX +#define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX +#endif +#define BOARD_CONSOLE_UART_BAUDRATE (115200UL) +#endif +#endif + +/* usb cdc acm uart section */ +#define BOARD_USB_CDC_ACM_UART BOARD_APP_UART_BASE +#define BOARD_USB_CDC_ACM_UART_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_USB_CDC_ACM_UART_TX_DMA_SRC BOARD_APP_UART_TX_DMA_REQ +#define BOARD_USB_CDC_ACM_UART_RX_DMA_SRC BOARD_APP_UART_RX_DMA_REQ + +/* rtthread-nano finsh section */ +#define BOARD_RT_CONSOLE_BASE BOARD_CONSOLE_UART_BASE + +/* modbus sample section */ +#define BOARD_MODBUS_UART_BASE BOARD_APP_UART_BASE +#define BOARD_MODBUS_UART_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_MODBUS_UART_RX_DMA_REQ BOARD_APP_UART_RX_DMA_REQ +#define BOARD_MODBUS_UART_TX_DMA_REQ BOARD_APP_UART_TX_DMA_REQ + +/* nor flash section */ +#define BOARD_FLASH_BASE_ADDRESS (0x80000000UL) /* Check */ +#define BOARD_FLASH_SIZE (SIZE_1MB) + +/* i2c section */ +#define BOARD_APP_I2C_BASE HPM_I2C0 +#define BOARD_APP_I2C_IRQ IRQn_I2C0 +#define BOARD_APP_I2C_CLK_NAME clock_i2c0 +#define BOARD_APP_I2C_DMA HPM_HDMA +#define BOARD_APP_I2C_DMAMUX HPM_DMAMUX +#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0 + +/* gptmr section */ +#define BOARD_GPTMR HPM_GPTMR0 +#define BOARD_GPTMR_IRQ IRQn_GPTMR0 +#define BOARD_GPTMR_CHANNEL 0 +#define BOARD_GPTMR_DMA_SRC HPM_DMA_SRC_GPTMR0_0 +#define BOARD_GPTMR_CLK_NAME clock_gptmr0 +#define BOARD_GPTMR_PWM HPM_GPTMR0 +#define BOARD_GPTMR_PWM_CHANNEL 0 +#define BOARD_GPTMR_PWM_DMA_SRC HPM_DMA_SRC_GPTMR0_0 +#define BOARD_GPTMR_PWM_CLK_NAME clock_gptmr0 +#define BOARD_GPTMR_PWM_IRQ IRQn_GPTMR0 +#define BOARD_GPTMR_PWM_SYNC HPM_GPTMR0 +#define BOARD_GPTMR_PWM_SYNC_CHANNEL 1 +#define BOARD_GPTMR_PWM_SYNC_CLK_NAME clock_gptmr0 + +/* User LED */ +#define BOARD_LED_GPIO_CTRL HPM_GPIO0 +#define BOARD_LED_GPIO_INDEX GPIO_DI_GPIOA +#define BOARD_LED_GPIO_PIN 23 + +#define BOARD_LED_OFF_LEVEL 1 +#define BOARD_LED_ON_LEVEL 0 + +/* 12V Power Enable for lin transceiver */ +#define BOARD_SUPPORT_LIN_TRANSCEIVER_CONTROL 1 +#define BOARD_12V_EN_GPIO_CTRL HPM_GPIO0 +#define BOARD_12V_EN_GPIO_INDEX GPIO_DI_GPIOA +#define BOARD_12V_EN_GPIO_PIN 24 +#define BOARD_LIN_TRANSCEIVER_GPIO_CTRL HPM_GPIO0 +#define BOARD_LIN_TRANSCEIVER_GPIO_INDEX GPIO_DI_GPIOA +#define BOARD_LIN_TRANSCEIVER_GPIO_PIN 13 + + +/* gpiom section */ +#define BOARD_APP_GPIOM_BASE HPM_GPIOM +#define BOARD_APP_GPIOM_USING_CTRL HPM_FGPIO +#define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast + +/* User button */ +#define BOARD_APP_GPIO_CTRL HPM_GPIO0 +#define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOA +#define BOARD_APP_GPIO_PIN 9 +#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_A + +/* spi section */ +#define BOARD_APP_SPI_BASE HPM_SPI1 +#define BOARD_APP_SPI_CLK_NAME clock_spi1 +#define BOARD_APP_SPI_IRQ IRQn_SPI1 +#define BOARD_APP_SPI_SCLK_FREQ (20000000UL) +#define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U) +#define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U) +#define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI1_RX +#define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI1_TX +#define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 +#define BOARD_SPI_CS_PIN IOC_PAD_PA26 +#define BOARD_SPI_CS_ACTIVE_LEVEL (0U) + +/* ADC section */ +#define BOARD_APP_ADC16_NAME "ADC0" +#define BOARD_APP_ADC16_BASE HPM_ADC0 +#define BOARD_APP_ADC16_IRQn IRQn_ADC0 +#define BOARD_APP_ADC16_CH_1 (13U) +#define BOARD_APP_ADC16_CLK_NAME (clock_adc0) + +#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI +#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A + +#define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A + +/* DAC section */ +#define BOARD_DAC_BASE HPM_DAC0 +#define BOARD_DAC_IRQn IRQn_DAC0 +#define BOARD_APP_DAC_CLOCK_NAME clock_dac0 + +/* Flash section */ +#define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) +#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90002U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000006U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) + +/* SDXC section */ +#define BOARD_APP_SDCARD_SDXC_BASE (HPM_SDXC0) +#define BOARD_APP_SDCARD_SUPPORT_1V8 (0) + +/* MCAN section */ +#define BOARD_APP_CAN_BASE HPM_MCAN3 +#define BOARD_APP_CAN_IRQn IRQn_MCAN3 + +/* CALLBACK TIMER section */ +#define BOARD_CALLBACK_TIMER (HPM_GPTMR3) +#define BOARD_CALLBACK_TIMER_CH 1 +#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR3 +#define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr3) + +/* APP PWM */ +#define BOARD_APP_PWM HPM_PWM0 +#define BOARD_APP_PWM_CLOCK_NAME clock_mot0 +#define BOARD_APP_PWM_OUT1 2 +#define BOARD_APP_PWM_OUT2 3 +#define BOARD_APP_TRGM HPM_TRGM0 +#define BOARD_APP_PWM_IRQ IRQn_PWM0 +#define BOARD_APP_TRGM_PWM_OUTPUT TRGM_TRGOCFG_PWM0_SYNCI + +/*BLDC pwm*/ +/*PWM define*/ +#define BOARD_BLDCPWM HPM_PWM0 +#define BOARD_BLDC_UH_PWM_OUTPIN (6U) +#define BOARD_BLDC_UL_PWM_OUTPIN (7U) +#define BOARD_BLDC_VH_PWM_OUTPIN (4U) +#define BOARD_BLDC_VL_PWM_OUTPIN (5U) +#define BOARD_BLDC_WH_PWM_OUTPIN (2U) +#define BOARD_BLDC_WL_PWM_OUTPIN (3U) +#define BOARD_BLDCPWM_TRGM HPM_TRGM0 +#define BOARD_BLDCAPP_PWM_IRQ IRQn_PWM0 +#define BOARD_BLDCPWM_CMP_INDEX_0 (0U) +#define BOARD_BLDCPWM_CMP_INDEX_1 (1U) +#define BOARD_BLDCPWM_CMP_INDEX_2 (2U) +#define BOARD_BLDCPWM_CMP_INDEX_3 (3U) +#define BOARD_BLDCPWM_CMP_INDEX_4 (4U) +#define BOARD_BLDCPWM_CMP_INDEX_5 (5U) +#define BOARD_BLDCPWM_CMP_INDEX_6 (6U) +#define BOARD_BLDCPWM_CMP_INDEX_7 (7U) +#define BOARD_BLDCPWM_CMP_TRIG_CMP (20U) + +/*HALL define*/ + +/*RDC*/ +#define BOARD_RDC_TRGM HPM_TRGM0 +#define BOARD_RDC_TRGIGMUX_IN_NUM HPM_TRGM0_INPUT_SRC_RDC_TRGO_0 +#define BOARD_RDC_TRG_NUM TRGM_TRGOCFG_MOT_GPIO0 +#define BOARD_RDC_TRG_ADC_NUM TRGM_TRGOCFG_ADCX_PTRGI0A +#define BOARD_RDC_ADC_I_BASE HPM_ADC0 +#define BOARD_RDC_ADC_Q_BASE HPM_ADC1 +#define BOARD_RDC_ADC_I_CHN (5U) +#define BOARD_RDC_ADC_Q_CHN (6U) +#define BOARD_RDC_ADC_IRQn IRQn_ADC0 +#define BOARD_RDC_ADC_TRIG_FLAG adc16_event_trig_complete +#define BOARD_RDC_ADC_TRG ADC16_CONFIG_TRG0A + +/*QEI*/ +#define BOARD_BLDC_QEI_TRGM HPM_TRGM0 +#define BOARD_BLDC_QEIV2_BASE HPM_QEI1 +#define BOARD_BLDC_QEIV2_IRQ IRQn_QEI1 +#define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV (16U) +#define BOARD_BLDC_QEI_CLOCK_SOURCE clock_mot0 +#define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV (4000U) +#define BOARD_BLDC_QEI_ADC_MATRIX_ADC0 trgm_adc_matrix_output_to_qei1_adc0 +#define BOARD_BLDC_QEI_ADC_MATRIX_ADC1 trgm_adc_matrix_output_to_qei1_adc1 + +/*Timer define*/ +#define BOARD_BLDC_TMR_1MS HPM_GPTMR2 +#define BOARD_BLDC_TMR_CH 0 +#define BOARD_BLDC_TMR_CMP 0 +#define BOARD_BLDC_TMR_IRQ IRQn_GPTMR2 +#define BOARD_BLDC_TMR_RELOAD (100000U) + +/*adc*/ +#define BOARD_BLDC_ADC_MODULE (ADCX_MODULE_ADC16) +#define BOARD_BLDC_ADC_U_BASE HPM_ADC0 +#define BOARD_BLDC_ADC_V_BASE HPM_ADC1 +#define BOARD_BLDC_ADC_W_BASE HPM_ADC1 +#define BOARD_BLDC_ADC_TRIG_FLAG adc16_event_trig_complete + +#define BOARD_BLDC_ADC_CH_U (5U) +#define BOARD_BLDC_ADC_CH_V (6U) +#define BOARD_BLDC_ADC_CH_W (4U) +#define BOARD_BLDC_ADC_IRQn IRQn_ADC0 +#define BOARD_BLDC_ADC_PMT_DMA_SIZE_IN_4BYTES (ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES) +#define BOARD_BLDC_ADC_TRG ADC16_CONFIG_TRG0A +#define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) +#define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U) +#define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A + +#define BOARD_PLB_COUNTER HPM_PLB +#define BOARD_PLB_PWM_BASE HPM_PWM0 +#define BOARD_PLB_PWM_CLOCK_NAME clock_mot0 +#define BOARD_PLB_TRGM HPM_TRGM0 +#define BOARD_PLB_PWM_TRG (HPM_TRGM0_INPUT_SRC_PWM0_CH8REF) +#define BOARD_PLB_IN_PWM_TRG_NUM (TRGM_TRGOCFG_PLB_IN_00) +#define BOARD_PLB_IN_PWM_PULSE_TRG_NUM (TRGM_TRGOCFG_PLB_IN_02) +#define BOARD_PLB_OUT_TRG (HPM_TRGM0_INPUT_SRC_PLB_OUT00) +#define BOARD_PLB_IO_TRG_NUM (TRGM_TRGOCFG_MOT_GPIO2) +#define BOARD_PLB_IO_TRG_SHIFT (2) +#define BOARD_PLB_PWM_CMP (8U) +#define BOARD_PLB_PWM_CHN (8U) +#define BOARD_PLB_CHN plb_chn0 + +/* QEO */ +#define BOARD_QEO HPM_QEO0 +#define BOARD_QEO_TRGM_POS trgm_pos_matrix_output_to_qeo0 + +/* moto */ +#define BOARD_MOTOR_CLK_NAME clock_mot0 + +/* SEI */ +#define BOARD_SEI HPM_SEI +#define BOARD_SEI_CTRL SEI_CTRL_1 +#define BOARD_SEI_IRQn IRQn_SEI1 + +/* USB */ +#define BOARD_USB HPM_USB0 + +/* OPAMP */ +#define BOARD_APP_OPAMP HPM_OPAMP0 + +#ifndef BOARD_SHOW_CLOCK +#define BOARD_SHOW_CLOCK 1 +#endif +#ifndef BOARD_SHOW_BANNER +#define BOARD_SHOW_BANNER 1 +#endif + +/* FreeRTOS Definitions */ +#define BOARD_FREERTOS_TIMER HPM_GPTMR2 +#define BOARD_FREERTOS_TIMER_CHANNEL 1 +#define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR2 +#define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr2 + +/* Threadx Definitions */ +#define BOARD_THREADX_TIMER HPM_GPTMR2 +#define BOARD_THREADX_TIMER_CHANNEL 1 +#define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR2 +#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr2 +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +typedef void (*board_timer_cb)(void); + +void board_init(void); +void board_init_console(void); +void board_init_gpio_pins(void); +void board_init_led_pins(void); +void board_init_usb_pins(void); +void board_led_write(uint8_t state); +void board_led_toggle(void); +void board_init_uart(UART_Type *ptr); +uint32_t board_init_spi_clock(SPI_Type *ptr); +void board_init_spi_pins(SPI_Type *ptr); +void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb); +void board_init_adc16_pins(void); +uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb); +void board_init_can(MCAN_Type *ptr); +uint32_t board_init_can_clock(MCAN_Type *ptr); +void board_init_rgb_pwm_pins(void); +void board_disable_output_rgb_led(uint8_t color); +void board_enable_output_rgb_led(uint8_t color); +void board_init_dac_pins(DAC_Type *ptr); +void board_write_spi_cs(uint32_t pin, uint8_t state); +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); + +void board_init_usb_dp_dm_pins(void); +void board_init_clock(void); +void board_delay_us(uint32_t us); +void board_delay_ms(uint32_t ms); +void board_timer_create(uint32_t ms, board_timer_cb cb); +void board_ungate_mchtmr_at_lp_mode(void); + +uint8_t board_get_led_gpio_off_level(void); +uint8_t board_get_led_pwm_off_level(void); + +void board_init_pmp(void); + +uint32_t board_init_uart_clock(UART_Type *ptr); +void board_init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx); + +void board_init_i2c(I2C_Type *ptr); + +void board_init_adc_qeiv2_pins(void); + +void board_lin_transceiver_control(bool enable); +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); +uint32_t board_init_pwm_clock(PWM_Type *ptr); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _HPM_BOARD_H */ diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/boards/hpm5300evk.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/boards/hpm5300evk.cfg new file mode 100644 index 00000000000..7d495f5b380 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/boards/hpm5300evk.cfg @@ -0,0 +1,79 @@ +# Copyright (c) 2023 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# openocd flash driver argument: +# - option0: +# [31:28] Flash probe type +# 0 - SFDP SDR / 1 - SFDP DDR +# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) +# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V +# 6 - OctaBus DDR (SPI -> OPI DDR) +# 8 - Xccela DDR (SPI -> OPI DDR) +# 10 - EcoXiP DDR (SPI -> OPI DDR) +# [27:24] Command Pads after Power-on Reset +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [23:20] Command Pads after Configuring FLASH +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) +# 0 - Not needed +# 1 - QE bit is at bit 6 in Status Register 1 +# 2 - QE bit is at bit1 in Status Register 2 +# 3 - QE bit is at bit7 in Status Register 2 +# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 +# [15:8] Dummy cycles +# 0 - Auto-probed / detected / default value +# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet +# [7:4] Misc. +# 0 - Not used +# 1 - SPI mode +# 2 - Internal loopback +# 3 - External DQS +# [3:0] Frequency option +# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz +# - option1: +# [31:20] Reserved +# [19:16] IO voltage +# 0 - 3V / 1 - 1.8V +# [15:12] Pin group +# 0 - 1st group / 1 - 2nd group +# [11:8] Connection selection +# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) +# [7:0] Drive Strength +# 0 - Default value + +# xpi0 configs +# - flash driver: hpm_xpi +# - flash ctrl index: 0xF3000000 +# - base address: 0x80000000 +# - flash size: 0x2000000 +# - flash option0: 0x7 +flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x6 0x1000 + +proc init_clock {} { + $::_TARGET0 riscv dmi_write 0x39 0xF4002000 + $::_TARGET0 riscv dmi_write 0x3C 0x1 + + $::_TARGET0 riscv dmi_write 0x39 0xF4002000 + $::_TARGET0 riscv dmi_write 0x3C 0x2 + + $::_TARGET0 riscv dmi_write 0x39 0xF4000800 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000810 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000820 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000830 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + echo "clocks has been enabled!" +} + +$_TARGET0 configure -event reset-init { + init_clock +} + +$_TARGET0 configure -event gdb-attach { + reset halt +} diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg new file mode 100644 index 00000000000..0aa1eed3dad --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg @@ -0,0 +1,11 @@ +# Copyright (c) 2021 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 8000 +adapter srst delay 500 + +source [find interface/cmsis-dap.cfg] + +transport select jtag +reset_config srst_only diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/ft2232.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/ft2232.cfg new file mode 100644 index 00000000000..782edbcf509 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/ft2232.cfg @@ -0,0 +1,15 @@ +# Copyright (c) 2021 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +reset_config trst_and_srst +adapter srst delay 50 + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0208 0x020b +ftdi_layout_signal nTRST -data 0x0200 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0100 -noe 0x0800 + diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/ft232.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/ft232.cfg new file mode 100644 index 00000000000..e2c01a2d788 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/ft232.cfg @@ -0,0 +1,14 @@ +# Copyright (c) 2021 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +reset_config trst_and_srst +adapter srst delay 50 + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6014 + +ftdi_layout_init 0x0018 0x001b +ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/jlink.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/jlink.cfg new file mode 100644 index 00000000000..5d565c0ecc3 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/jlink.cfg @@ -0,0 +1,11 @@ +# Copyright (c) 2021 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 + +source [find interface/jlink.cfg] + +transport select jtag +reset_config srst_only diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg new file mode 100644 index 00000000000..a9421a83877 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg @@ -0,0 +1,14 @@ +# Copyright (c) 2021 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 +reset_config srst_only + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x010b +ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm5300.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm5300.cfg new file mode 100644 index 00000000000..c57a36d0174 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm5300.cfg @@ -0,0 +1,13 @@ +# Copyright (c) 2021 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +set _CHIP hpm5301 +set _CPUTAPID 0x1000563D +jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID + +set _TARGET0 $_CHIP.cpu0 +target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0 + +$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 + +targets $_TARGET0 diff --git a/bsp/hpmicro/hpm5300evk/board/fal_cfg.h b/bsp/hpmicro/hpm5300evk/board/fal_cfg.h new file mode 100644 index 00000000000..40d0330d450 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/fal_cfg.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + +#ifdef RT_USING_FAL +#define NOR_FLASH_DEV_NAME "norflash0" +#define NOR_FLASH_MEM_BASE 0x80000000UL +#define NOR_FLASH_SIZE_IN_BYTES 0x1000000UL + +/* ===================== Flash device Configuration ========================= */ +extern const struct fal_flash_dev stm32f2_onchip_flash; +extern struct fal_flash_dev nor_flash0; + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &nor_flash0, \ +} +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG +/* partition table */ +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WORD, "app", NOR_FLASH_DEV_NAME, 0, 256*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME, 256*1024, 256*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "download", NOR_FLASH_DEV_NAME, 512*1024, 256*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "flashdb", NOR_FLASH_DEV_NAME, 768*1024, 256*1024, 0}, \ +} +#endif /* FAL_PART_HAS_TABLE_CFG */ +#endif /* RT_USING_FAL */ + +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/hpmicro/hpm5300evk/board/fal_flash_port.c b/bsp/hpmicro/hpm5300evk/board/fal_flash_port.c new file mode 100644 index 00000000000..1ed9fdffd69 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/fal_flash_port.c @@ -0,0 +1,254 @@ +/* + * Copyright (c) 2022-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2022-03-09 hpmicro First implementation + * 2022-08-01 hpmicro Fixed random crashing during kvdb_init + * 2022-08-03 hpmicro Improved erase speed + * 2023-01-31 hpmicro Fix random crashing issue if the global interrupt is always enabled + * + */ +#include +#include +#ifdef RT_USING_FAL +#include "fal.h" +#include "hpm_romapi.h" +#include "board.h" +#include "hpm_l1c_drv.h" + + +#define FAL_ENTER_CRITICAL() do {\ + disable_global_irq(CSR_MSTATUS_MIE_MASK);\ + }while(0) + +#define FAL_EXIT_CRITICAL() do {\ + enable_global_irq(CSR_MSTATUS_MIE_MASK);\ + }while(0) + +#define FAL_RAMFUNC __attribute__((section(".isr_vector"))) + + +/*************************************************************************************************** + * FAL Porting Guide + * + * 1. Most FLASH devices do not support RWW (Read-while-Write), the codes to access the FLASH + * must be placed at RAM or ROM code + * 2. During FLASH erase/program, it is recommended to disable the interrupt, or place the + * interrupt related codes to RAM + * + ***************************************************************************************************/ + +static int init(void); +static int read(long offset, uint8_t *buf, size_t size); +static int write(long offset, const uint8_t *buf, size_t size); +static int erase(long offset, size_t size); + +static xpi_nor_config_t s_flashcfg; + +/** + * @brief FAL Flash device context + */ +struct fal_flash_dev nor_flash0 = + { + .name = NOR_FLASH_DEV_NAME, + /* If porting this code to the device with FLASH connected to XPI1, the address must be changed to 0x90000000 */ + .addr = NOR_FLASH_MEM_BASE, + .len = 8 * 1024 * 1024, + .blk_size = 4096, + .ops = { .init = init, .read = read, .write = write, .erase = erase }, + .write_gran = 1 + }; + +/** + * @brief FAL initialization + * This function probes the FLASH using the ROM API + */ +FAL_RAMFUNC static int init(void) +{ + int ret = RT_EOK; + xpi_nor_config_option_t cfg_option; + cfg_option.header.U = BOARD_APP_XPI_NOR_CFG_OPT_HDR; + cfg_option.option0.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT0; + cfg_option.option1.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT1; + + FAL_ENTER_CRITICAL(); + hpm_stat_t status = rom_xpi_nor_auto_config(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, &cfg_option); + FAL_EXIT_CRITICAL(); + if (status != status_success) + { + ret = -RT_ERROR; + } + else + { + s_flashcfg.device_info.clk_freq_for_non_read_cmd = 0U; + /* update the flash chip information */ + uint32_t sector_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, §or_size); + uint32_t flash_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_total_size, &flash_size); + nor_flash0.blk_size = sector_size; + nor_flash0.len = flash_size; + } + + return ret; +} + +/** + * @brief FAL read function + * Read data from FLASH + * @param offset FLASH offset + * @param buf Buffer to hold data read by this API + * @param size Size of data to be read + * @return actual read bytes + */ +FAL_RAMFUNC static int read(long offset, uint8_t *buf, size_t size) +{ + uint32_t flash_addr = nor_flash0.addr + offset; + uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN(flash_addr); + uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP(flash_addr + size); + uint32_t aligned_size = aligned_end - aligned_start; + rt_base_t level = rt_hw_interrupt_disable(); + l1c_dc_invalidate(aligned_start, aligned_size); + rt_hw_interrupt_enable(level); + + (void) rt_memcpy(buf, (void*) flash_addr, size); + + return size; +} + +/** + * @brief Write unaligned data to the page + * @param offset FLASH offset + * @param buf Data buffer + * @param size Size of data to be written + * @return actual size of written data or error code + */ +FAL_RAMFUNC static int write_unaligned_page_data(long offset, const uint32_t *buf, size_t size) +{ + hpm_stat_t status; + + FAL_ENTER_CRITICAL(); + status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, buf, offset, size); + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + return -RT_ERROR; + rt_kprintf("write failed, status=%d\n", status); + } + + return size; +} + +/** + * @brief FAL write function + * Write data to specified FLASH address + * @param offset FLASH offset + * @param buf Data buffer + * @param size Size of data to be written + * @return actual size of written data or error code + */ +FAL_RAMFUNC static int write(long offset, const uint8_t *buf, size_t size) +{ + uint32_t *src = NULL; + uint32_t buf_32[64]; + uint32_t write_size; + size_t remaining_size = size; + int ret = (int)size; + + uint32_t page_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_page_size, &page_size); + uint32_t offset_in_page = offset % page_size; + if (offset_in_page != 0) + { + uint32_t write_size_in_page = page_size - offset_in_page; + uint32_t write_page_size = MIN(write_size_in_page, size); + (void) rt_memcpy(buf_32, buf, write_page_size); + write_size = write_unaligned_page_data(offset, buf_32, write_page_size); + if (write_size < 0) + { + ret = -RT_ERROR; + goto write_quit; + } + + remaining_size -= write_page_size; + offset += write_page_size; + buf += write_page_size; + } + + while (remaining_size > 0) + { + write_size = MIN(remaining_size, sizeof(buf_32)); + rt_memcpy(buf_32, buf, write_size); + src = &buf_32[0]; + + FAL_ENTER_CRITICAL(); + hpm_stat_t status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, src, + offset, write_size); + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + ret = -RT_ERROR; + rt_kprintf("write failed, status=%d\n", status); + break; + } + + remaining_size -= write_size; + buf += write_size; + offset += write_size; + } + +write_quit: + return ret; +} + +/** + * @brief FAL erase function + * Erase specified FLASH region + * @param offset the start FLASH address to be erased + * @param size size of the region to be erased + * @ret RT_EOK Erase operation is successful + * @retval -RT_ERROR Erase operation failed + */ +FAL_RAMFUNC static int erase(long offset, size_t size) +{ + uint32_t aligned_size = (size + nor_flash0.blk_size - 1U) & ~(nor_flash0.blk_size - 1U); + hpm_stat_t status; + int ret = (int)size; + + uint32_t block_size; + uint32_t sector_size; + (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, §or_size); + (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_block_size, &block_size); + uint32_t erase_unit; + while (aligned_size > 0) + { + FAL_ENTER_CRITICAL(); + if ((offset % block_size == 0) && (aligned_size >= block_size)) + { + erase_unit = block_size; + status = rom_xpi_nor_erase_block(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset); + } + else + { + erase_unit = sector_size; + status = rom_xpi_nor_erase_sector(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset); + } + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + ret = -RT_ERROR; + break; + } + offset += erase_unit; + aligned_size -= erase_unit; + } + + return ret; +} +#endif /* RT_USING_FAL */ diff --git a/bsp/hpmicro/hpm5300evk/board/linker_scripts/flash_rtt.ld b/bsp/hpmicro/hpm5300evk/board/linker_scripts/flash_rtt.ld new file mode 100644 index 00000000000..7f3af8a529c --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/linker_scripts/flash_rtt.ld @@ -0,0 +1,288 @@ +/* + * Copyright 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 1M; + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 32K; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K + AHB_SRAM (w) : ORIGIN = 0xf0400000, LENGTH = 32K +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .fast : AT(etext + __data_end__ - __tdata_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + + /* RT-Thread Core Start */ + KEEP(*context_gcc.o(.text* .rodata*)) + KEEP(*port*.o (.text .text* .rodata .rodata*)) + KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) + KEEP(*trap_common.o (.text .text* .rodata .rodata*)) + KEEP(*irq.o (.text .text* .rodata .rodata*)) + KEEP(*clock.o (.text .text* .rodata .rodata*)) + KEEP(*kservice.o (.text .text* .rodata .rodata*)) + KEEP(*scheduler.o (.text .text* .rodata .rodata*)) + KEEP(*trap*.o (.text .text* .rodata .rodata*)) + KEEP(*idle.o (.text .text* .rodata .rodata*)) + KEEP(*ipc.o (.text .text* .rodata .rodata*)) + KEEP(*thread.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*timer.o (.text .text* .rodata .rodata*)) + KEEP(*mem.o (.text .text* .rodata .rodata*)) + KEEP(*mempool.o (.text .text* .rodata .rodata*)) + /* RT-Thread Core End */ + + . = ALIGN(8); + __ramfunc_end__ = .; + } > ILM + + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + /* Note: the .tbss and .tdata section should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > DLM + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > DLM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + + .heap(NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE( __rt_rvstack = . ); + } > DLM + + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > DLM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > DLM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + /* __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + __share_mem_start__ = ORIGIN(SHARE_RAM); + __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); */ + +} diff --git a/bsp/hpmicro/hpm5300evk/board/linker_scripts/ram_rtt.ld b/bsp/hpmicro/hpm5300evk/board/linker_scripts/ram_rtt.ld new file mode 100644 index 00000000000..196cbe56efe --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/linker_scripts/ram_rtt.ld @@ -0,0 +1,244 @@ +/* + * Copyright 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x2000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x8000; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 0x8000; + +MEMORY +{ + ILM (wx) : ORIGIN = 0, LENGTH = 128K + DLM (w) : ORIGIN = 0x80000, LENGTH = 128K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x98000, LENGTH = NONCACHEABLE_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > ILM + + .vectors : { + . = ALIGN(8); + KEEP(*(.isr_vector)) + KEEP(*(.vector_table)) + . = ALIGN(8); + } > ILM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > ILM + + .text : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + *(FalPartTable) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + } > ILM + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > DLM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + + .fast : AT(etext + __data_end__ - __tdata_start__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > DLM + + .rel : { + KEEP(*(.rel*)) + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + /* Note: .tbss and .tdata should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > DLM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE (__rt_rvstack = .); + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + + } > DLM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); +} diff --git a/bsp/hpmicro/hpm5300evk/board/pinmux.c b/bsp/hpmicro/hpm5300evk/board/pinmux.c new file mode 100644 index 00000000000..2f17df67529 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/pinmux.c @@ -0,0 +1,325 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* + * Note: + * PY and PZ IOs: if any SOC pin function needs to be routed to these IOs, + * besides of IOC, PIOC/BIOC needs to be configured SOC_GPIO_X_xx, so that + * expected SoC function can be enabled on these IOs. + * + */ +#include "board.h" +#include "pinmux.h" + +void init_xtal_pins(void) +{ + /* Package QFN32 should be set PA30 and PA31 pins as analog type to enable xtal. */ + /* + * HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + * HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + */ +} + +void init_py_pins_as_pgpio(void) +{ + /* Set PY00-PY05 default function to PGPIO */ + HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_PGPIO_Y_00; + HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_PGPIO_Y_01; + HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = PIOC_PY02_FUNC_CTL_PGPIO_Y_02; + HPM_PIOC->PAD[IOC_PAD_PY03].FUNC_CTL = PIOC_PY03_FUNC_CTL_PGPIO_Y_03; + HPM_PIOC->PAD[IOC_PAD_PY04].FUNC_CTL = PIOC_PY04_FUNC_CTL_PGPIO_Y_04; + HPM_PIOC->PAD[IOC_PAD_PY05].FUNC_CTL = PIOC_PY05_FUNC_CTL_PGPIO_Y_05; +} + +void init_uart_pins(UART_Type *ptr) +{ + if (ptr == HPM_UART0) { + HPM_IOC->PAD[IOC_PAD_PA00].FUNC_CTL = IOC_PA00_FUNC_CTL_UART0_TXD; + HPM_IOC->PAD[IOC_PAD_PA01].FUNC_CTL = IOC_PA01_FUNC_CTL_UART0_RXD; + } else if (ptr == HPM_UART2) { + HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_UART2_TXD; + HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_UART2_RXD; + HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_UART2_DE; + } else if (ptr == HPM_UART3) { + /* using for uart_lin function */ + HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_UART3_RXD; + HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_UART3_TXD; + } else if (ptr == HPM_UART7) { + /* using for uart_lin function */ + HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_UART7_TXD; + HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_UART7_RXD; + } else { + ; + } +} + +void init_lin_transceiver_ctrl_pin(void) +{ + /* PA24 is used to control the 12V power supply of the LIN transceiver */ + HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PA24_FUNC_CTL_GPIO_A_24; + /* PA13 is used to control the LIN transceiver not to enter sleep mode */ + HPM_IOC->PAD[IOC_PAD_PA13].FUNC_CTL = IOC_PA13_FUNC_CTL_GPIO_A_13; +} + +/* for uart_lin case, need to configure pin as gpio to sent break signal */ +void init_uart_pin_as_gpio(UART_Type *ptr) +{ + /* pull-up */ + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + + if (ptr == HPM_UART3) { + HPM_IOC->PAD[IOC_PAD_PA14].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PA15].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_GPIO_A_14; + HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_GPIO_A_15; + } +} + +void init_i2c_pins(I2C_Type *ptr) +{ + if (ptr == HPM_I2C0) { + HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_I2C0_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_I2C0_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PB02].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PB03].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + } else if (ptr == HPM_I2C1) { + HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_I2C1_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_I2C1_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PB06].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PB07].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + } else { + ; + } +} + +void init_gpio_pins(void) +{ + /* configure pad setting: pull enable and pull up, schmitt trigger enable */ + /* enable schmitt trigger to eliminate jitter of pin used as button */ + + /* Button */ + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_SET(1); + HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_GPIO_A_09; + HPM_IOC->PAD[IOC_PAD_PA09].PAD_CTL = pad_ctl; +} + +void init_spi_pins(SPI_Type *ptr) +{ + if (ptr == HPM_SPI1) { + HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_SPI1_CS_1; + HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_SPI1_CS_0; + HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_SPI1_MISO; + HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_SPI1_MOSI; + } +} + +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + if (ptr == HPM_SPI1) { + HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_GPIO_A_25; + HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_GPIO_A_26; + HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_SPI1_MISO; + HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_SPI1_MOSI; + } +} + + +void init_gptmr_pins(GPTMR_Type *ptr) +{ + if (ptr == HPM_GPTMR0) { + HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_GPTMR0_CAPT_0; + HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_GPTMR0_COMP_0; + HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_GPTMR0_COMP_1; + } +} + +void init_hall_trgm_pins(void) +{ + init_qeiv2_uvw_pins(HPM_QEI1); +} + +void init_qei_trgm_pins(void) +{ + init_qeiv2_ab_pins(HPM_QEI1); +} + +void init_butn_pins(void) +{ + /* configure pad setting: pull enable and pull up, schmitt trigger enable */ + /* enable schmitt trigger to eliminate jitter of pin used as button */ + + /* Button */ + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_SET(1); + HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_GPIO_A_09; + HPM_IOC->PAD[IOC_PAD_PA09].PAD_CTL = pad_ctl; +} + +void init_acmp_pins(void) +{ + /* configure to ACMP_COMP_1(ALT16) function */ + HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_ACMP_COMP_1; + /* configure to CMP1_INN4 function */ + HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_pwm_pins(PWM_Type *ptr) +{ + if (ptr == HPM_PWM0) { + HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_PWM0_P_2; + HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_PWM0_P_3; + HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_PWM0_P_4; + HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_PWM0_P_5; + HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_PWM0_P_6; + HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_PWM0_P_7; + } +} + +void init_adc_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC0.13 */ +} + +void init_adc_bldc_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IU: ADC0.5 /ADC1.5 */ + HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IV: ADC0.6 /ADC1.6 */ +} + +void init_adc_qeiv2_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IW: ADC0.4 /ADC1.4 */ + HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IU: ADC0.5 /ADC1.5 */ +} + +void init_usb_pins(void) +{ + /* Package QFN48 and LQFP64 should be set PA24 and PA25 pins as analog type to enable USB_P and USB_N. */ + /* + * HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + * HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + */ + + /* Package QFN32 should be set PA26 and PA27 pins as analog type to enable USB_P and USB_N. */ + /* + * HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + * HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + */ + + /* USB0_ID */ + HPM_IOC->PAD[IOC_PAD_PY00].FUNC_CTL = IOC_PY00_FUNC_CTL_USB0_ID; + /* USB0_OC */ + HPM_IOC->PAD[IOC_PAD_PY01].FUNC_CTL = IOC_PY01_FUNC_CTL_USB0_OC; + /* USB0_PWR */ + HPM_IOC->PAD[IOC_PAD_PY02].FUNC_CTL = IOC_PY02_FUNC_CTL_USB0_PWR; + + /* PY port IO needs to configure PIOC as well */ + HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_SOC_GPIO_Y_00; + HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_SOC_GPIO_Y_01; + HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = PIOC_PY02_FUNC_CTL_SOC_GPIO_Y_02; +} + +void init_can_pins(MCAN_Type *ptr) +{ + if (ptr == HPM_MCAN3) { + HPM_IOC->PAD[IOC_PAD_PY04].FUNC_CTL = IOC_PY04_FUNC_CTL_MCAN3_RXD; + HPM_IOC->PAD[IOC_PAD_PY05].FUNC_CTL = IOC_PY05_FUNC_CTL_MCAN3_TXD; + /* PY port IO needs to configure PIOC as well */ + HPM_PIOC->PAD[IOC_PAD_PY04].FUNC_CTL = PIOC_PY04_FUNC_CTL_SOC_GPIO_Y_04; + HPM_PIOC->PAD[IOC_PAD_PY05].FUNC_CTL = PIOC_PY05_FUNC_CTL_SOC_GPIO_Y_05; + } +} + +void init_led_pins_as_gpio(void) +{ + HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_GPIO_A_23; +} + +void init_led_pins_as_pwm(void) +{ + HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_TRGM0_P_03; +} + +void init_dac_pins(DAC_Type *ptr) +{ + if (ptr == HPM_DAC0) { + HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* DAC0.OUT */ + } else if (ptr == HPM_DAC1) { + HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* DAC1.OUT */ + } +} + +void init_plb_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_TRGM0_P_02; +} + +void init_qeo_pins(QEO_Type *ptr) +{ + if (ptr == HPM_QEO0) { + HPM_IOC->PAD[IOC_PAD_PA20].FUNC_CTL = IOC_PA20_FUNC_CTL_QEO0_A; + HPM_IOC->PAD[IOC_PAD_PA21].FUNC_CTL = IOC_PA21_FUNC_CTL_QEO0_B; + HPM_IOC->PAD[IOC_PAD_PA22].FUNC_CTL = IOC_PA22_FUNC_CTL_QEO0_Z; + } +} + +void init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx) +{ + if (ptr == HPM_SEI) { + if (sei_ctrl_idx == SEI_CTRL_1) { + HPM_IOC->PAD[IOC_PAD_PA16].FUNC_CTL = IOC_PA16_FUNC_CTL_SEI1_DE; + HPM_IOC->PAD[IOC_PAD_PA17].FUNC_CTL = IOC_PA17_FUNC_CTL_SEI1_CK; + HPM_IOC->PAD[IOC_PAD_PA18].FUNC_CTL = IOC_PA18_FUNC_CTL_SEI1_TX; + HPM_IOC->PAD[IOC_PAD_PA19].FUNC_CTL = IOC_PA19_FUNC_CTL_SEI1_RX; + } + } +} + +void init_rdc_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_RDC0_EXC_P; + HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + +/*The GPIO is designed for debug */ +#ifdef RDC_SAMPLE_TEST_GPIO_OUTPUT + HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_TRGM0_P_00; +#endif +} + +void init_qeiv2_uvw_pins(QEIV2_Type *ptr) +{ + if (ptr == HPM_QEI1) { + HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_QEI1_A; + HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_QEI1_B; + HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = IOC_PA12_FUNC_CTL_QEI1_Z; + } +} + +void init_qeiv2_ab_pins(QEIV2_Type *ptr) +{ + if (ptr == HPM_QEI1) { + HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_QEI1_A; + HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_QEI1_B; + } +} + +void init_qeiv2_abz_pins(QEIV2_Type *ptr) +{ + if (ptr == HPM_QEI1) { + HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_QEI1_A; + HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_QEI1_B; + HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = IOC_PA12_FUNC_CTL_QEI1_Z; + } +} + +void init_opamp_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} diff --git a/bsp/hpmicro/hpm5300evk/board/pinmux.h b/bsp/hpmicro/hpm5300evk/board/pinmux.h new file mode 100644 index 00000000000..1ff17798655 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/pinmux.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PINMUX_H +#define HPM_PINMUX_H + +#ifdef __cplusplus +extern "C" { +#endif +void init_xtal_pins(void); +void init_py_pins_as_pgpio(void); +void init_uart_pins(UART_Type *ptr); +void init_uart_pin_as_gpio(UART_Type *ptr); +void init_i2c_pins(I2C_Type *ptr); +void init_gpio_pins(void); +void init_spi_pins(SPI_Type *ptr); +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); +void init_gptmr_pins(GPTMR_Type *ptr); +void init_hall_trgm_pins(void); +void init_qei_trgm_pins(void); +void init_butn_pins(void); +void init_acmp_pins(void); +void init_pwm_pins(PWM_Type *ptr); +void init_adc_pins(void); +void init_adc_bldc_pins(void); +void init_adc_qeiv2_pins(void); +void init_usb_pins(void); +void init_can_pins(MCAN_Type *ptr); +void init_dac_pins(DAC_Type *ptr); +void init_led_pins_as_gpio(void); +void init_led_pins_as_pwm(void); +void init_plb_pins(void); +void init_qeo_pins(QEO_Type *ptr); +void init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx); +void init_rdc_pin(void); +void init_qeiv2_uvw_pins(QEIV2_Type *ptr); +void init_qeiv2_ab_pins(QEIV2_Type *ptr); +void init_qeiv2_abz_pins(QEIV2_Type *ptr); +void init_opamp_pins(void); +void init_lin_transceiver_ctrl_pin(void); +#ifdef __cplusplus +} +#endif +#endif /* HPM_PINMUX_H */ diff --git a/bsp/hpmicro/hpm5300evk/board/rtt_board.c b/bsp/hpmicro/hpm5300evk/board/rtt_board.c new file mode 100644 index 00000000000..407d5ac9ecd --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/rtt_board.c @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2023-2024 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "board.h" +#include "rtt_board.h" +#include "hpm_uart_drv.h" +#include "hpm_gpio_drv.h" +#include "hpm_pmp_drv.h" +#include "assert.h" +#include "hpm_clock_drv.h" +#include "hpm_sysctl_drv.h" +#include +#include +#include "hpm_dma_mgr.h" +#include "hpm_mchtmr_drv.h" + +extern int rt_hw_uart_init(void); +void os_tick_config(void); +void rtt_board_init(void); + +void rt_hw_board_init(void) +{ + rtt_board_init(); + + /* Call the RT-Thread Component Board Initialization */ + rt_components_board_init(); +} + +void os_tick_config(void) +{ + sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1); + sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0); + mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND); + enable_mchtmr_irq(); +} + +void rtt_board_init(void) +{ + board_init_clock(); + board_init_console(); + board_init_pmp(); + + dma_mgr_init(); + + /* initialize memory system */ + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); + + /* Configure the OS Tick */ + os_tick_config(); + + /* Configure the USB pins*/ + board_init_usb_pins(); + + /* Initialize the UART driver first, because later driver initialization may require the rt_kprintf */ + rt_hw_uart_init(); + + /* Set console device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +} + +void app_init_led_pins(void) +{ + gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN); + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, BOARD_LED_OFF_LEVEL); +} + +void app_led_write(uint32_t index, bool state) +{ + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state); +} + +void BOARD_LED_write(uint32_t index, bool state) +{ + switch (index) + { + case 0: + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state); + break; + default: + /* Suppress the toolchain warnings */ + break; + } +} + +void rt_hw_console_output(const char *str) +{ + while (*str != '\0') + { + uart_send_byte(BOARD_APP_UART_BASE, *str++); + } +} + +void app_init_usb_pins(void) +{ + board_init_usb_pins(); +} + +ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) +{ + HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND; + + rt_tick_increase(); +} + +void rt_hw_cpu_reset(void) +{ + HPM_PPOR->RESET_ENABLE = (1UL << 31); + + HPM_PPOR->SOFTWARE_RESET = 1000U; + while(1) { + + } +} + +MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board); diff --git a/bsp/hpmicro/hpm5300evk/board/rtt_board.h b/bsp/hpmicro/hpm5300evk/board/rtt_board.h new file mode 100644 index 00000000000..78b51752c62 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/rtt_board.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _RTT_BOARD_H +#define _RTT_BOARD_H +#include "hpm_common.h" +#include "hpm_soc.h" +#include + +/* gpio section */ +#define APP_LED0_PIN_NUM GET_PIN(A, 23) +#define APP_LED_ON (1) +#define APP_LED_OFF (0) + +/* mchtimer section */ +#define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL) + +/* CAN section */ +#define BOARD_CAN_NAME "can0" +#define BOARD_CAN_HWFILTER_INDEX (0U) + +/* UART section */ +#define BOARD_UART_NAME "uart2" +#define BOARD_UART_RX_BUFFER_SIZE BSP_UART2_RX_BUFSIZE + +/* PWM section */ +#define BOARD_PWM_NAME "pwm0" +#define BOARD_PWM_CHANNEL (6) + +#define IRQn_PendSV IRQn_DEBUG0 + +/*************************************************************** + * + * RT-Thread related definitions + * + **************************************************************/ +extern unsigned int __heap_start__; +extern unsigned int __heap_end__; + +#define RT_HW_HEAP_BEGIN ((void*)&__heap_start__) +#define RT_HW_HEAP_END ((void*)&__heap_end__) + + +typedef struct { + uint16_t vdd; + uint8_t bus_width; + uint8_t drive_strength; +}sdxc_io_cfg_t; + +void app_init_led_pins(void); +void app_led_write(uint32_t index, bool state); +void app_init_usb_pins(void); + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + + + + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _RTT_BOARD_H */ diff --git a/bsp/hpmicro/hpm5300evk/figures/board.png b/bsp/hpmicro/hpm5300evk/figures/board.png new file mode 100644 index 00000000000..35c083c1208 Binary files /dev/null and b/bsp/hpmicro/hpm5300evk/figures/board.png differ diff --git a/bsp/hpmicro/hpm5300evk/rtconfig.h b/bsp/hpmicro/hpm5300evk/rtconfig.h new file mode 100644 index 00000000000..3d78319912e --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/rtconfig.h @@ -0,0 +1,254 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 1024 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 1024 + +/* kservice optimization */ + + +/* klibc optimization */ + + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x50200 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_LEGACY +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V2 +#define RT_USING_PIN + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + + +/* Memory protection */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* CYW43012 WiFi */ + + +/* BL808 WiFi */ + + +/* CYW43439 WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + +/* sensors drivers */ + + +/* touch drivers */ + + +/* Kendryte SDK */ + + +/* AI packages */ + + +/* Signal Processing and Control Algorithm Packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Arduino libraries */ + + +/* Projects and Demos */ + + +/* Sensors */ + + +/* Display */ + + +/* Timing */ + + +/* Data Processing */ + + +/* Data Storage */ + +/* Communication */ + + +/* Device Control */ + + +/* Other */ + + +/* Signal IO */ + + +/* Uncategorized */ + +/* Hardware Drivers Config */ + +#define SOC_HPM5000 + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART0 +#define BSP_UART0_RX_BUFSIZE 128 +#define BSP_UART0_TX_BUFSIZE 0 + +#endif diff --git a/bsp/hpmicro/hpm5300evk/rtconfig.py b/bsp/hpmicro/hpm5300evk/rtconfig.py new file mode 100644 index 00000000000..b1f8c645ec4 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/rtconfig.py @@ -0,0 +1,109 @@ +# Copyright 2021-2023 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +import os +import sys + +# toolchains options +ARCH='risc-v' +CPU='hpmicro' +CHIP_NAME='HPM5361' + +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +# Fallback toolchain info +FALLBACK_TOOLCHAIN_VENDOR='RISC-V' +FALLBACK_TOOLCHAIN_PKG='RISC-V-GCC-RV32' +FALLBACK_TOOLCHAIN_VER='2022-04-12' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +RTT_EXEC_PATH = os.getenv('RTT_EXEC_PATH') +if RTT_EXEC_PATH != None: + folders = RTT_EXEC_PATH.split(os.sep) + # If the `RT-Thread Env` is from the RT-Thread Studio, generate the RTT_EXEC_PATH using `FALLBACK_TOOLCHAIN_INFO` + if 'arm_gcc' in folders and 'platform' in folders: + RTT_EXEC_PATH = '' + for path in folders: + if path != 'platform': + RTT_EXEC_PATH = RTT_EXEC_PATH + path + os.sep + else: + break + RTT_EXEC_PATH = os.path.join(RTT_EXEC_PATH, 'repo', 'Extract', 'ToolChain_Support_Packages', FALLBACK_TOOLCHAIN_VENDOR, FALLBACK_TOOLCHAIN_PKG, FALLBACK_TOOLCHAIN_VER, 'bin') + # Override the 'RTT_RISCV_TOOLCHAIN' only if the `RT-Thread ENV` is from the RT-Thread Studio + if 'platform' in folders: + os.environ['RTT_RISCV_TOOLCHAIN'] = RTT_EXEC_PATH + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler path, for example, GNU RISC-V toolchain, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + if os.getenv('RTT_RISCV_TOOLCHAIN'): + EXEC_PATH = os.getenv('RTT_RISCV_TOOLCHAIN') + else: + EXEC_PATH = r'/opt/riscv-gnu-gcc/bin' +else: + print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL) + +BUILD = 'flash_debug' + +if PLATFORM == 'gcc': + PREFIX = 'riscv32-unknown-elf-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + GDB = PREFIX + 'gdb' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + ARCH_ABI = ' -mcmodel=medlow ' + DEVICE = ARCH_ABI + ' -DUSE_NONVECTOR_MODE=1 ' + ' -ffunction-sections -fdata-sections -fno-common ' + CFLAGS = DEVICE + AFLAGS = CFLAGS + LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections ' + + CPATH = '' + LPATH = '' + + if BUILD == 'ram_debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + LFLAGS += ' -O0' + LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + elif BUILD == 'ram_release': + CFLAGS += ' -O2' + LFLAGS += ' -O2' + LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + elif BUILD == 'flash_debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + LFLAGS += ' -O0' + CFLAGS += ' -DFLASH_XIP=1' + LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + elif BUILD == 'flash_release': + CFLAGS += ' -O2' + LFLAGS += ' -O2' + CFLAGS += ' -DFLASH_XIP=1' + LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + else: + CFLAGS += ' -O2' + LFLAGS += ' -O2' + LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + LFLAGS += ' -T ' + LINKER_FILE + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + + # module setting + CXXFLAGS = CFLAGS + ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' + CFLAGS = CFLAGS + ' -std=gnu11' \ No newline at end of file diff --git a/bsp/hpmicro/hpm5300evk/startup/HPM5361/SConscript b/bsp/hpmicro/hpm5300evk/startup/HPM5361/SConscript new file mode 100644 index 00000000000..7ade8d38e43 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/startup/HPM5361/SConscript @@ -0,0 +1,19 @@ +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() + +# add the startup files + +src = Glob('*.c') + +if rtconfig.PLATFORM == 'gcc': + src += [os.path.join('toolchains', 'gcc', 'start.S')] + src += [os.path.join('toolchains', 'gcc', 'port_gcc.S')] + +CPPPATH = [cwd] +CPPDEFINES=['D25', rtconfig.CHIP_NAME] + +group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm5300evk/startup/HPM5361/startup.c b/bsp/hpmicro/hpm5300evk/startup/HPM5361/startup.c new file mode 100644 index 00000000000..b0bab335d52 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/startup/HPM5361/startup.c @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * + */ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" +#include + +void system_init(void); + +extern int entry(void); + +extern void __libc_init_array(void); +extern void __libc_fini_array(void); + +void system_init(void) +{ + disable_global_irq(CSR_MSTATUS_MIE_MASK); + disable_irq_from_intc(); + enable_irq_from_intc(); + enable_global_irq(CSR_MSTATUS_MIE_MASK); +#ifndef CONFIG_NOT_ENABLE_ICACHE + l1c_ic_enable(); +#endif +#ifndef CONFIG_NOT_ENABLE_DCACHE + l1c_dc_enable(); +#endif +} + +__attribute__((weak)) void c_startup(void) +{ + uint32_t i, size; +#ifdef FLASH_XIP + extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; + size = __vector_ram_end__ - __vector_ram_start__; + for (i = 0; i < size; i++) { + *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); + } +#endif + + extern uint8_t __etext[]; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __tbss_start__[], __tbss_end__[]; + extern uint8_t __tdata_start__[], __tdata_end__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + + /* tbss section */ + size = __tbss_end__ - __tbss_start__; + for (i = 0; i < size; i++) { + *(__tbss_start__ + i) = 0; + } + + /* bss section */ + size = __bss_end__ - __bss_start__; + for (i = 0; i < size; i++) { + *(__bss_start__ + i) = 0; + } + + /* noncacheable bss section */ + size = __noncacheable_bss_end__ - __noncacheable_bss_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_bss_start__ + i) = 0; + } + + /* tdata section LMA: etext */ + size = __tdata_end__ - __tdata_start__; + for (i = 0; i < size; i++) { + *(__tdata_start__ + i) = *(__etext + i); + } + + /* data section LMA: etext */ + size = __data_end__ - __data_start__; + for (i = 0; i < size; i++) { + *(__data_start__ + i) = *(__etext + (__tdata_end__ - __tdata_start__) + i); + } + + /* ramfunc section LMA: etext + data length */ + size = __ramfunc_end__ - __ramfunc_start__; + for (i = 0; i < size; i++) { + *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + i); + } + + /* noncacheable init section LMA: etext + data length + ramfunc length */ + size = __noncacheable_init_end__ - __noncacheable_init_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); + } +} + +__attribute__((weak)) int main(void) +{ + while(1); +} + +void reset_handler(void) +{ + /** + * Disable preemptive interrupt + */ + HPM_PLIC->FEATURE = 0; + /* + * Initialize LMA/VMA sections. + * Relocation for any sections that need to be copied from LMA to VMA. + */ + c_startup(); + + /* Call platform specific hardware initialization */ + system_init(); + + /* Do global constructors */ + __libc_init_array(); + + + + /* Entry function */ + entry(); +} + + +__attribute__((weak)) void _init() +{ +} diff --git a/bsp/hpmicro/hpm5300evk/startup/HPM5361/toolchains/gcc/port_gcc.S b/bsp/hpmicro/hpm5300evk/startup/HPM5361/toolchains/gcc/port_gcc.S new file mode 100644 index 00000000000..2708b48e455 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/startup/HPM5361/toolchains/gcc/port_gcc.S @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "cpuport.h" + + .globl rt_hw_do_after_save_above + .type rt_hw_do_after_save_above,@function +rt_hw_do_after_save_above: + addi sp, sp, -4 + STORE ra, 0 * REGBYTES(sp) + + csrr t1, mcause + andi t1, t1, 0x3FF + /* get ISR */ + la t2, trap_entry + jalr t2 + + LOAD ra, 0 * REGBYTES(sp) + addi sp, sp, 4 + ret diff --git a/bsp/hpmicro/hpm5300evk/startup/HPM5361/toolchains/gcc/start.S b/bsp/hpmicro/hpm5300evk/startup/HPM5361/toolchains/gcc/start.S new file mode 100644 index 00000000000..76463936442 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/startup/HPM5361/toolchains/gcc/start.S @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + #include + #include "hpm_csr_regs.h" + .section .start, "ax" + + .global _start + .type _start,@function + +_start: + /* Initialize global pointer */ + .option push + .option norelax + la gp, __global_pointer$ + la tp, __thread_pointer + .option pop + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + /* Initialize stack pointer */ + la t0, _stack + mv sp, t0 + +#ifdef __nds_execit + /* Initialize EXEC.IT table */ + la t0, _ITB_BASE_ + csrw uitb, t0 +#endif + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + /* Disable Vector mode */ + csrci CSR_MMISC_CTL, 2 + /* Initialize trap_entry base */ + la t0, SW_handler + csrw mtvec, t0 + + + /* System reset handler */ + call reset_handler + + /* Infinite loop, if returned accidently */ +1: j 1b + + .weak nmi_handler +nmi_handler: +1: j 1b + + .global default_irq_handler + .weak default_irq_handler + .align 2 +default_irq_handler: +1: j 1b + + .macro IRQ_HANDLER irq + .weak default_isr_\irq + .set default_isr_\irq, default_irq_handler + .long default_isr_\irq + .endm + +#include "vectors.S" diff --git a/bsp/hpmicro/hpm5300evk/startup/HPM5361/toolchains/gcc/vectors.S b/bsp/hpmicro/hpm5300evk/startup/HPM5361/toolchains/gcc/vectors.S new file mode 100644 index 00000000000..5703e223309 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/startup/HPM5361/toolchains/gcc/vectors.S @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +.section .vector_table, "a" +.global __vector_table +.align 9 + +__vector_table: + .weak default_isr_trap + .set default_isr_trap, SW_handler + .long default_isr_trap + IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_HANDLER 5 /* GPIO0_X IRQ handler */ + IRQ_HANDLER 6 /* GPIO0_Y IRQ handler */ + IRQ_HANDLER 7 /* GPIO0_Z IRQ handler */ + IRQ_HANDLER 8 /* GPIO1_A IRQ handler */ + IRQ_HANDLER 9 /* GPIO1_B IRQ handler */ + IRQ_HANDLER 10 /* GPIO1_C IRQ handler */ + IRQ_HANDLER 11 /* GPIO1_D IRQ handler */ + IRQ_HANDLER 12 /* GPIO1_X IRQ handler */ + IRQ_HANDLER 13 /* GPIO1_Y IRQ handler */ + IRQ_HANDLER 14 /* GPIO1_Z IRQ handler */ + IRQ_HANDLER 15 /* ADC0 IRQ handler */ + IRQ_HANDLER 16 /* ADC1 IRQ handler */ + IRQ_HANDLER 17 /* ADC2 IRQ handler */ + IRQ_HANDLER 18 /* SDFM IRQ handler */ + IRQ_HANDLER 19 /* DAC0 IRQ handler */ + IRQ_HANDLER 20 /* DAC1 IRQ handler */ + IRQ_HANDLER 21 /* ACMP[0] IRQ handler */ + IRQ_HANDLER 22 /* ACMP[1] IRQ handler */ + IRQ_HANDLER 23 /* ACMP[2] IRQ handler */ + IRQ_HANDLER 24 /* ACMP[3] IRQ handler */ + IRQ_HANDLER 25 /* SPI0 IRQ handler */ + IRQ_HANDLER 26 /* SPI1 IRQ handler */ + IRQ_HANDLER 27 /* SPI2 IRQ handler */ + IRQ_HANDLER 28 /* SPI3 IRQ handler */ + IRQ_HANDLER 29 /* UART0 IRQ handler */ + IRQ_HANDLER 30 /* UART1 IRQ handler */ + IRQ_HANDLER 31 /* UART2 IRQ handler */ + IRQ_HANDLER 32 /* UART3 IRQ handler */ + IRQ_HANDLER 33 /* UART4 IRQ handler */ + IRQ_HANDLER 34 /* UART5 IRQ handler */ + IRQ_HANDLER 35 /* UART6 IRQ handler */ + IRQ_HANDLER 36 /* UART7 IRQ handler */ + IRQ_HANDLER 37 /* CAN0 IRQ handler */ + IRQ_HANDLER 38 /* CAN1 IRQ handler */ + IRQ_HANDLER 39 /* CAN2 IRQ handler */ + IRQ_HANDLER 40 /* CAN3 IRQ handler */ + IRQ_HANDLER 41 /* PTPC IRQ handler */ + IRQ_HANDLER 42 /* WDG0 IRQ handler */ + IRQ_HANDLER 43 /* WDG1 IRQ handler */ + IRQ_HANDLER 44 /* TSNS IRQ handler */ + IRQ_HANDLER 45 /* MBX0A IRQ handler */ + IRQ_HANDLER 46 /* MBX0B IRQ handler */ + IRQ_HANDLER 47 /* MBX1A IRQ handler */ + IRQ_HANDLER 48 /* MBX1B IRQ handler */ + IRQ_HANDLER 49 /* GPTMR0 IRQ handler */ + IRQ_HANDLER 50 /* GPTMR1 IRQ handler */ + IRQ_HANDLER 51 /* GPTMR2 IRQ handler */ + IRQ_HANDLER 52 /* GPTMR3 IRQ handler */ + IRQ_HANDLER 53 /* I2C0 IRQ handler */ + IRQ_HANDLER 54 /* I2C1 IRQ handler */ + IRQ_HANDLER 55 /* I2C2 IRQ handler */ + IRQ_HANDLER 56 /* I2C3 IRQ handler */ + IRQ_HANDLER 57 /* PWM0 IRQ handler */ + IRQ_HANDLER 58 /* HALL0 IRQ handler */ + IRQ_HANDLER 59 /* QEI0 IRQ handler */ + IRQ_HANDLER 60 /* PWM1 IRQ handler */ + IRQ_HANDLER 61 /* HALL1 IRQ handler */ + IRQ_HANDLER 62 /* QEI1 IRQ handler */ + IRQ_HANDLER 63 /* PWM2 IRQ handler */ + IRQ_HANDLER 64 /* HALL2 IRQ handler */ + IRQ_HANDLER 65 /* QEI2 IRQ handler */ + IRQ_HANDLER 66 /* PWM3 IRQ handler */ + IRQ_HANDLER 67 /* HALL3 IRQ handler */ + IRQ_HANDLER 68 /* QEI3 IRQ handler */ + IRQ_HANDLER 69 /* SDP IRQ handler */ + IRQ_HANDLER 70 /* XPI0 IRQ handler */ + IRQ_HANDLER 71 /* XDMA IRQ handler */ + IRQ_HANDLER 72 /* HDMA IRQ handler */ + IRQ_HANDLER 73 /* RNG IRQ handler */ + IRQ_HANDLER 74 /* USB0 IRQ handler */ + IRQ_HANDLER 75 /* PSEC IRQ handler */ + IRQ_HANDLER 76 /* PGPIO IRQ handler */ + IRQ_HANDLER 77 /* PWDG IRQ handler */ + IRQ_HANDLER 78 /* PTMR IRQ handler */ + IRQ_HANDLER 79 /* PUART IRQ handler */ + IRQ_HANDLER 80 /* FUSE IRQ handler */ + IRQ_HANDLER 81 /* SECMON IRQ handler */ + IRQ_HANDLER 82 /* RTC IRQ handler */ + IRQ_HANDLER 83 /* BUTN IRQ handler */ + IRQ_HANDLER 84 /* BGPIO IRQ handler */ + IRQ_HANDLER 85 /* BVIO IRQ handler */ + IRQ_HANDLER 86 /* BROWNOUT IRQ handler */ + IRQ_HANDLER 87 /* SYSCTL IRQ handler */ + IRQ_HANDLER 88 /* DEBUG[0] IRQ handler */ + IRQ_HANDLER 89 /* DEBUG[1] IRQ handler */ + IRQ_HANDLER 90 /* LIN0 IRQ handler */ + IRQ_HANDLER 91 /* LIN1 IRQ handler */ + IRQ_HANDLER 92 /* LIN2 IRQ handler */ + IRQ_HANDLER 93 /* LIN3 IRQ handler */ + diff --git a/bsp/hpmicro/hpm5300evk/startup/HPM5361/trap.c b/bsp/hpmicro/hpm5300evk/startup/HPM5361/trap.c new file mode 100644 index 00000000000..b87eaee5244 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/startup/HPM5361/trap.c @@ -0,0 +1,304 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_common.h" +#include "hpm_soc.h" +#include +#include "rt_hw_stack_frame.h" + +#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) //!< Instruction Address misaligned +#define MCAUSE_INSTR_ACCESS_FAULT (1U) //!< Instruction access fault +#define MCAUSE_ILLEGAL_INSTR (2U) //!< Illegal instruction +#define MCAUSE_BREAKPOINT (3U) //!< Breakpoint +#define MCAUSE_LOAD_ADDR_MISALIGNED (4U) //!< Load address misaligned +#define MCAUSE_LOAD_ACCESS_FAULT (5U) //!< Load access fault +#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U) //!< Store/AMO address misaligned +#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U) //!< Store/AMO access fault +#define MCAUSE_ECALL_FROM_USER_MODE (8U) //!< Environment call from User mode +#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U) //!< Environment call from Supervisor mode +#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U) //!< Environment call from machine mode +#define MCAUSE_INSTR_PAGE_FAULT (12U) //!< Instruction page fault +#define MCAUSE_LOAD_PAGE_FAULT (13) //!< Load page fault +#define MCAUSE_STORE_AMO_PAGE_FAULT (15U) //!< Store/AMO page fault + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#ifdef DEBUG +#define RT_EXCEPTION_TRACE rt_kprintf +#else +#define RT_EXCEPTION_TRACE(...) +#endif + +typedef void (*isr_func_t)(void); + +static volatile rt_hw_stack_frame_t *s_stack_frame; + +__attribute((weak)) void mchtmr_isr(void) +{ +} + +__attribute__((weak)) void mswi_isr(void) +{ +} + +__attribute__((weak)) void syscall_handler(uint32_t n, uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3) +{ +} + +void rt_show_stack_frame(void) +{ + RT_EXCEPTION_TRACE("Stack frame:\r\n----------------------------------------\r\n"); + RT_EXCEPTION_TRACE("ra : 0x%08x\r\n", s_stack_frame->ra); + RT_EXCEPTION_TRACE("mstatus : 0x%08x\r\n", read_csr(0x300));//mstatus + RT_EXCEPTION_TRACE("t0 : 0x%08x\r\n", s_stack_frame->t0); + RT_EXCEPTION_TRACE("t1 : 0x%08x\r\n", s_stack_frame->t1); + RT_EXCEPTION_TRACE("t2 : 0x%08x\r\n", s_stack_frame->t2); + RT_EXCEPTION_TRACE("a0 : 0x%08x\r\n", s_stack_frame->a0); + RT_EXCEPTION_TRACE("a1 : 0x%08x\r\n", s_stack_frame->a1); + RT_EXCEPTION_TRACE("a2 : 0x%08x\r\n", s_stack_frame->a2); + RT_EXCEPTION_TRACE("a3 : 0x%08x\r\n", s_stack_frame->a3); + RT_EXCEPTION_TRACE("a4 : 0x%08x\r\n", s_stack_frame->a4); + RT_EXCEPTION_TRACE("a5 : 0x%08x\r\n", s_stack_frame->a5); +#ifndef __riscv_32e + RT_EXCEPTION_TRACE("a6 : 0x%08x\r\n", s_stack_frame->a6); + RT_EXCEPTION_TRACE("a7 : 0x%08x\r\n", s_stack_frame->a7); + RT_EXCEPTION_TRACE("t3 : 0x%08x\r\n", s_stack_frame->t3); + RT_EXCEPTION_TRACE("t4 : 0x%08x\r\n", s_stack_frame->t4); + RT_EXCEPTION_TRACE("t5 : 0x%08x\r\n", s_stack_frame->t5); + RT_EXCEPTION_TRACE("t6 : 0x%08x\r\n", s_stack_frame->t6); +#endif +} + +uint32_t exception_handler(uint32_t cause, uint32_t epc) +{ + /* Unhandled Trap */ + uint32_t mdcause = read_csr(CSR_MDCAUSE); + uint32_t mtval = read_csr(CSR_MTVAL); + rt_uint32_t mscratch = read_csr(0x340); + + s_stack_frame = (rt_hw_stack_frame_t *)mscratch; + rt_show_stack_frame(); + + switch (cause) + { + case MCAUSE_INSTR_ADDR_MISALIGNED: + RT_EXCEPTION_TRACE("exception: instruction address was mis-aligned, mtval=0x%08x\n", mtval); + break; + case MCAUSE_INSTR_ACCESS_FAULT: + RT_EXCEPTION_TRACE("exception: instruction access fault happened, mtval=0x%08x, epc=0x%08x\n", mtval, epc); + switch (mdcause & 0x07) + { + case 1: + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); + break; + case 4: + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); + break; + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_ILLEGAL_INSTR: + RT_EXCEPTION_TRACE("exception: illegal instruction was met, mtval=0x%08x\n", mtval); + switch (mdcause & 0x07) + { + case 0: + RT_EXCEPTION_TRACE("mdcause: the actual faulting instruction is stored in the mtval CSR\r\n"); + break; + case 1: + RT_EXCEPTION_TRACE("mdcause: FP disabled exception \r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: ACE disabled exception \r\n"); + break; + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_BREAKPOINT: + RT_EXCEPTION_TRACE("exception: breakpoint was hit, mtval=0x%08x\n", mtval); + break; + case MCAUSE_LOAD_ADDR_MISALIGNED: + RT_EXCEPTION_TRACE("exception: load address was mis-aligned, mtval=0x%08x\n", mtval); + break; + case MCAUSE_LOAD_ACCESS_FAULT: + RT_EXCEPTION_TRACE("exception: load access fault happened, epc=%08x, mdcause=0x%x\n", epc, mdcause); + switch (mdcause & 0x07) + { + case 1: + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); + break; + case 4: + RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n"); + break; + case 5: + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); + break; + case 6: + RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n"); + break; + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_STORE_AMO_ADDR_MISALIGNED: + RT_EXCEPTION_TRACE("exception: store amo address was misaligned, epc=%08x\n", epc); + break; + case MCAUSE_STORE_AMO_ACCESS_FAULT: + RT_EXCEPTION_TRACE("exception: store amo access fault happened, epc=%08x\n", epc); + switch (mdcause & 0x07) + { + case 1: + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); + break; + case 4: + RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n"); + break; + case 5: + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); + break; + case 6: + RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n"); + break; + case 7: + RT_EXCEPTION_TRACE("mdcause: PMA NAMO exception \r\n"); + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + default: + RT_EXCEPTION_TRACE("Unknown exception happened, cause=%d\n", cause); + break; + } + + rt_kprintf("cause=0x%08x, epc=0x%08x, ra=0x%08x\n", cause, epc, s_stack_frame->ra); + while(1) { + } +} + +void trap_entry(void); + +void trap_entry(void) +{ + uint32_t mcause = read_csr(CSR_MCAUSE); + uint32_t mepc = read_csr(CSR_MEPC); + uint32_t mstatus = read_csr(CSR_MSTATUS); + +#if SUPPORT_PFT_ARCH + uint32_t mxstatus = read_csr(CSR_MXSTATUS); +#endif +#ifdef __riscv_dsp + int ucode = read_csr(CSR_UCODE); +#endif +#ifdef __riscv_flen + int fcsr = read_fcsr(); +#endif + + /* clobbers list for ecall */ +#ifdef __riscv_32e + __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3"); +#else + __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3"); +#endif + + /* Do your trap handling */ + uint32_t cause_type = mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK; + uint32_t irq_index; + if (mcause & CSR_MCAUSE_INTERRUPT_MASK) + { + switch (cause_type) + { + /* Machine timer interrupt */ + case IRQ_M_TIMER: + mchtmr_isr(); + break; + /* Machine EXT interrupt */ + case IRQ_M_EXT: + /* Claim interrupt */ + irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); + /* Execute EXT interrupt handler */ + if (irq_index > 0) + { + ((isr_func_t) __vector_table[irq_index])(); + /* Complete interrupt */ + __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index); + } + break; + /* Machine SWI interrupt */ + case IRQ_M_SOFT: + mswi_isr(); + intc_m_complete_swi(); + break; + } + } + else if (cause_type == MCAUSE_ECALL_FROM_MACHINE_MODE) + { + /* Machine Syscal call */ + __asm volatile( + "mv a4, a3\n" + "mv a3, a2\n" + "mv a2, a1\n" + "mv a1, a0\n" +#ifdef __riscv_32e + "mv a0, t0\n" +#else + "mv a0, a7\n" +#endif + "call syscall_handler\n" + : : : "a4" + ); + mepc += 4; + } + else + { + mepc = exception_handler(mcause, mepc); + } + + /* Restore CSR */ + write_csr(CSR_MSTATUS, mstatus); + write_csr(CSR_MEPC, mepc); +#if SUPPORT_PFT_ARCH + write_csr(CSR_MXSTATUS, mxstatus); +#endif +#ifdef __riscv_dsp + write_csr(CSR_UCODE, ucode); +#endif +#ifdef __riscv_flen + write_fcsr(fcsr); +#endif +} diff --git a/bsp/hpmicro/hpm5300evk/startup/SConscript b/bsp/hpmicro/hpm5300evk/startup/SConscript new file mode 100644 index 00000000000..de51a7c0d63 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/startup/SConscript @@ -0,0 +1,13 @@ +# for module compiling +import os +Import('rtconfig') +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] + +objs = objs + SConscript(os.path.join(cwd, rtconfig.CHIP_NAME, 'SConscript')) +ASFLAGS = ' -I' + cwd + +Return('objs') \ No newline at end of file diff --git a/bsp/hpmicro/hpm5301evklite/.config b/bsp/hpmicro/hpm5301evklite/.config new file mode 100644 index 00000000000..99bc81c3e3f --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/.config @@ -0,0 +1,1059 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=1024 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024 + +# +# kservice optimization +# +# CONFIG_RT_USING_TINY_FFS is not set + +# +# klibc optimization +# +# CONFIG_RT_KLIBC_USING_STDLIB is not set +# CONFIG_RT_KLIBC_USING_TINY_SIZE is not set +# CONFIG_RT_KLIBC_USING_PRINTF_LONGLONG is not set +# CONFIG_RT_USING_DEBUG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +# CONFIG_RT_USING_SCHED_THREAD_CTX is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x50200 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# CONFIG_RT_USING_CACHE is not set +# CONFIG_RT_USING_HW_ATOMIC is not set +# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_USING_HW_THREAD_SELF is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +CONFIG_RT_USING_LEGACY=y +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_USING_SERIAL_V1 is not set +CONFIG_RT_USING_SERIAL_V2=y +# CONFIG_RT_SERIAL_USING_DMA is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set + +# +# peripheral libraries and drivers +# + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ESP_IDF is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set + +# +# Uncategorized +# + +# +# Hardware Drivers Config +# +CONFIG_SOC_HPM5000=y + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +CONFIG_BSP_UART0_RX_BUFSIZE=128 +CONFIG_BSP_UART0_TX_BUFSIZE=0 +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART6 is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_GPTMR is not set +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_XPI_FLASH is not set +# CONFIG_BSP_USING_USB is not set +# CONFIG_BSP_USING_EWDG is not set +# CONFIG_BSP_USING_ADC is not set diff --git a/bsp/hpmicro/hpm5301evklite/Kconfig b/bsp/hpmicro/hpm5301evklite/Kconfig new file mode 100644 index 00000000000..79b160b8567 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/Kconfig @@ -0,0 +1,21 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" diff --git a/bsp/hpmicro/hpm5301evklite/README.md b/bsp/hpmicro/hpm5301evklite/README.md new file mode 100644 index 00000000000..ba4ad0b50fb --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/README.md @@ -0,0 +1,112 @@ +# HPMicro HPM5301EVKLITE BSP(Board Support Package) Introduction + +[中文页](README_zh.md) | + +## Introduction + +This document provides brief introduction of the BSP (board support package) for the HPM5301EVKLITE development board. + +The document consists of the following parts: + +- HPM5301EVKLITE Board Resources Introduction +- Quickly Getting Started +- Refreences + +By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources. + +## Board Resources Introduction + +HPM5301EVKLITE is a development board based on the RISC-V core launched by HPMicro, with rich on-board resources and on-chip resources for motor control, etc. +![board](figures/board.png) + + +## Peripheral Condition + +Each peripheral supporting condition for this BSP is as follows: + + +| **On-board Peripherals** | **Support** | **Note** | +| ------------------------ | ----------- | ------------------------------------- | +| USB | √ | | +| QSPI Flash | √ | | +| GPIO | √ | | +| SPI | √ | | +| I2C | √ | | +| On-Board Debugger | x | 20-PIN Standard JTAG Port | + + +## Execution Instruction + +### Quickly Getting Started + +The BSP support being build via the 'scons' command, below is the steps of compiling the example via the 'scons' command + +#### Parpare Environment +- Step 1: Prepare [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool) +- Step 2: Prepare [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) + - Download the package and extract it into a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain` +- Step 3: Set environment variable `RTT_RISCV_TOOLCHAIN` to `\bin` + - For example: `C:\DevTools\riscv32-gnu-toolchain\bin` +- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip) + - Download and extract it to specified directory, for example: `C:\DevTools\openocd-hpmicro` + - Add `OpenOCD` environment variable `OPENOCD_HPMICRO` to `\bin` + - For example: `C:\DevTools\openocd-hpmicro\bin` + +#### Configure and Build project + +Open RT-Thread ENV command-line, and change directory to this BSP directory, then users can: + +- Configure the project via `menuconfig` in `RT-Thread ENV` +- Build the project using `scons -jN`, `N` equals to the number of CPU cores +- Clean the project using `scons -c` + +#### Hardware Connection + +- Switch BOOT pin to 2'b00 +- Connect the `PWR_DEBUG` port to PC via TYPE-C cable + + +#### Dowload / Debug + +- Users can download the project via the below command: + ```console + %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\cmsis_dap.cfg -f boards\debug_scripts\soc\hpm5300.cfg -f boards\debug_scripts\boards\hpm5301evklite.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + ``` + +- Users can debug the project via the below command: + + - Connect debugger via `OpenOCD`: + +```console +%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\cmsis_dap.cfg -f boards\debug_scripts\soc\hpm5300.cfg -f boards\debug_scripts\boards\hpm5301evklite.cfg +``` + - Start Debugger via `GDB`: + +```console +%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf +``` + - In the `gdb shell`, type the following commands: + +```console +load +c +``` + +### **Running Results** + +Once the project is successfully downloaded, the system runs automatically. The LED on the board will flash periodically. + +Connect the serial port of the board to the PC, communicate with it via a serial terminal tool(115200-8-1-N). Reset the board and the startup information of RT-Thread will be observed: + +``` + \ | / +- RT - Thread Operating System + / | \ 5.1.0 build Aug 16 2023 18:18:18 + 2006 - 2024 Copyright by RT-Thread team +``` + +## **References** + +- [RT-Thread Documnent Center](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README) +- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md) +- [HPM5301EVKLITE RT-Thread BSP Package](https://github.com/hpmicro/rtt-bsp-hpm5301evklite) \ No newline at end of file diff --git a/bsp/hpmicro/hpm5301evklite/README_zh.md b/bsp/hpmicro/hpm5301evklite/README_zh.md new file mode 100644 index 00000000000..905d1649081 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/README_zh.md @@ -0,0 +1,111 @@ +# 先楫 HPM5301EVKLITE BSP(板级支持包)说明 + +[English](README.md) | + +## 简介 + +本文档为 HPM5301EVKLITE 的 BSP (板级支持包) 说明。 + +本文包含如下部分: + +- HPM5301EVKLITE 板级资源介绍 +- 快速上手指南 +- 参考链接 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 板级资源介绍 + + HPM5301EVKLITE 是由先楫半导体推出的一款基于RISCV内核的开发板，带有丰富的片上资源和板上资源，可用于电机控制等应用。 + +开发板外观如下图所示： + +![board](figures/board.png) + + +## 板载外设 + +本 BSP 目前对外设的支持情况如下: + + +| **板载外设** | **支持情况** | **备注** | +| ------------------------ | ----------- | ------------------------------------- | +| USB | √ | | +| QSPI Flash | √ | | +| GPIO | √ | | +| SPI | √ | | +| I2C | √ | | +| 板载调试器 | x | 20-PIN标准JTAG调试接口 | + + +## 使用说明 + +### 快速开始 + +本BSP支持通过`scons`命令来完成编译，在开始之前，需要先准备好开发所需的环境。 + +#### 准备环境 +- 步骤 1: 准备 [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool) +- 步骤 2: 准备 [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) + - 下载并解压到指定的目录，如: `C:\DevTools\riscv32-gnu-toolchain` +- 步骤 3: 设置环境变量： `RTT_RISCV_TOOLCHAIN` 为 `\bin`， 如: `C:\DevTools\riscv32-gnu-toolchain\bin` +- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip) + - 下载并解压到指定目录，如: `C:\DevTools\openocd-hpmicro` + - 将 `OPENOCD_HPMICRO`环境变量设置为 `\bin`，如： `C:\DevTools\openocd-hpmicro\bin` + +#### 配置和构建工程 + +通过 RT-Thread ENV 命令行切换目录到当前BSP所在目录后，用户可以: + +- 通过 `menuconfig` 命令 配置RT-Thread BSP的功能 +- 通过 `scons -jN` 命令完成构建, 其中`N` 最大值可以指定为CP拥有的物理内核数 +- 通过 `scons -c` 命令清除构建 + +#### 硬件连接 + +- 将BOOT 引脚拨到2'b00 +- 通过 TYPE-C线将板上的 `PWR_DEBUG` 连接到电脑 + +#### 下载 和 调试 + +- 通过如下命令完成下载: + ```console + %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\cmsis_dap.cfg -f boards\debug_scripts\soc\hpm5300.cfg -f boards\debug_scripts\boards\hpm5301evklite.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + ``` + +- 通过如下命令实现调试: + + - 通过 `OpenOCD` 来连接开发板: +```console +%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\cmsis_dap.cfg -f boards\debug_scripts\soc\hpm5300.cfg -f boards\debug_scripts\boards\hpm5301evklite.cfg +``` + - 通过 `GDB` 实现调试: +```console +%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf +``` + + - 在`GDB Shell`中使用如下命令来加载和运行: + +```console +load +c +``` + +### **运行结果** + +一旦成功下载，程序会自动运行并打印如下结果，板载LED灯会周期性闪烁。 + +配置好串口终端(串口配置为115200, 8-N-1),按复位键后，串口终端会打印如下日志： + +``` + \ | / +- RT - Thread Operating System + / | \ 5.1.0 build Aug 16 2023 18:18:18 + 2006 - 2023 Copyright by RT-Thread team +``` + +## **参考链接** + +- [RT-Thread 文档中心](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README) +- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md) +- [HPM5301EVKLITE RT-Thread BSP 包](https://github.com/hpmicro/rtt-bsp-hpm5301evklite) \ No newline at end of file diff --git a/bsp/hpmicro/hpm5301evklite/SConscript b/bsp/hpmicro/hpm5301evklite/SConscript new file mode 100644 index 00000000000..014c428d0a3 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/SConscript @@ -0,0 +1,17 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +ASFLAGS = ' -I' + cwd + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/hpmicro/hpm5301evklite/SConstruct b/bsp/hpmicro/hpm5301evklite/SConstruct new file mode 100644 index 00000000000..3dadc575c01 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/SConstruct @@ -0,0 +1,75 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../../rt-thread') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +AddOption('--run', + dest = 'run', + type='string', + nargs=1, + action = 'store', + default = "", + help = 'Upload or debug application using openocd') + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(os.path.join(SDK_ROOT, 'libraries')): + libraries_path_prefix = os.path.join(SDK_ROOT, 'libraries') +else: + libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries') + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + + +GDB = rtconfig.GDB + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +hpm_library = 'hpm_sdk' +rtconfig.BSP_LIBRARY_TYPE = hpm_library + +# include soc +objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.CHIP_NAME, 'SConscript'))) + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript'))) + +# include components +objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript'))) + + +# includes rtt drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/hpmicro/hpm5301evklite/applications/SConscript b/bsp/hpmicro/hpm5301evklite/applications/SConscript new file mode 100644 index 00000000000..a65aa4d8553 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/applications/SConscript @@ -0,0 +1,14 @@ +import rtconfig + +from building import * + +cwd = GetCurrentDir() + +src = Glob('*.c') + +CPPDEFINES=[] +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm5301evklite/applications/main.c b/bsp/hpmicro/hpm5301evklite/applications/main.c new file mode 100644 index 00000000000..0bbf6370382 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/applications/main.c @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2021 hpmicro + * + * Change Logs: + * Date Author Notes + * 2021-08-13 Fan YANG first version + * + */ + +#include +#include +#include "rtt_board.h" +#include + +void thread_entry(void *arg); + + +int main(void) +{ + static uint32_t led_thread_arg = 0; + rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10); + rt_thread_startup(led_thread); + + return 0; +} + + +void thread_entry(void *arg) +{ + rt_pin_mode(APP_LED0_PIN_NUM, PIN_MODE_OUTPUT); + + while(1){ + rt_pin_write(APP_LED0_PIN_NUM, APP_LED_ON); + rt_thread_mdelay(500); + rt_pin_write(APP_LED0_PIN_NUM, APP_LED_OFF); + rt_thread_mdelay(500); + } +} diff --git a/bsp/hpmicro/hpm5301evklite/board/Kconfig b/bsp/hpmicro/hpm5301evklite/board/Kconfig new file mode 100644 index 00000000000..2950dc6e485 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/board/Kconfig @@ -0,0 +1,189 @@ +menu "Hardware Drivers Config" + +config SOC_HPM5000 + bool + select SOC_SERIES_HPM5300 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN if BSP_USING_GPIO + default n + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + + if BSP_USING_UART + menuconfig BSP_USING_UART0 + bool "Enable UART0 (Debugger)" + default y + if BSP_USING_UART0 + config BSP_UART0_RX_USING_DMA + bool "Enable UART0 RX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + config BSP_UART0_TX_USING_DMA + bool "Enable UART0 TX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + config BSP_UART0_RX_BUFSIZE + int "Set UART0 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART0_TX_BUFSIZE + int "Set UART0 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + menuconfig BSP_USING_UART2 + bool "Enable UART2" + default y + if BSP_USING_UART2 + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default y + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + config BSP_UART2_RX_BUFSIZE + int "Set UART2 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART2_TX_BUFSIZE + int "Set UART2 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + menuconfig BSP_USING_UART6 + bool "Enable UART6" + default n + if BSP_USING_UART6 + config BSP_UART6_RX_USING_DMA + bool "Enable UART6 RX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + config BSP_UART6_TX_USING_DMA + bool "Enable UART6 TX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + config BSP_UART6_RX_BUFSIZE + int "Set UART6 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART6_TX_BUFSIZE + int "Set UART6 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI" + default n + select RT_USING_SPI if BSP_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1" + default y + config BSP_USING_SPI2 + bool "Enable SPI2" + default n + config BSP_USING_SPI3 + bool "Enable SPI3" + default n + endif + + menuconfig BSP_USING_GPTMR + bool "Enable GPTMR" + default n + select RT_USING_HWTIMER if BSP_USING_GPTMR + if BSP_USING_GPTMR + config BSP_USING_GPTMR1 + bool "Enable GPTMR1" + default n + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C" + default n + if BSP_USING_I2C + config BSP_USING_I2C0 + bool "Enable I2C0" + default y + if BSP_USING_I2C0 + config BSP_I2C0_USING_DMA + bool "Enable I2C0 DMA" + default n + endif + + config BSP_USING_I2C3 + bool "Enable I2C3" + default n + if BSP_USING_I2C3 + config BSP_I2C3_USING_DMA + bool "Enable I2C3 DMA" + default n + endif + endif + + menuconfig BSP_USING_XPI_FLASH + bool "Enable XPI FLASH" + default n + select RT_USING_FAL if BSP_USING_XPI_FLASH + + menuconfig BSP_USING_USB + bool "Enable USB" + default n + if BSP_USING_USB + config BSP_USING_USB_DEVICE + bool "Enable USB Device" + default n + config BSP_USING_USB_HOST + bool "Enable USB HOST" + select RT_USING_CACHE + default n + endif + + menuconfig BSP_USING_EWDG + bool "Enable EWDG" + default n + select RT_USING_WDT if BSP_USING_EWDG + if BSP_USING_EWDG + config BSP_USING_EWDG0 + bool "Enable EWDG0" + default n + config BSP_USING_EWDG1 + bool "Enable EWDG1" + default n + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC if BSP_USING_ADC + if BSP_USING_ADC + menuconfig BSP_USING_ADC16 + bool "Enable ADC16" + default y + if BSP_USING_ADC16 + config BSP_USING_ADC0 + bool "Enable ADC0" + default y + endif + endif +endmenu + +endmenu diff --git a/bsp/hpmicro/hpm5301evklite/board/SConscript b/bsp/hpmicro/hpm5301evklite/board/SConscript new file mode 100644 index 00000000000..dcd1e3543fd --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/board/SConscript @@ -0,0 +1,18 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers +src = Split(""" + board.c + rtt_board.c + pinmux.c + fal_flash_port.c +""") + +CPPPATH = [cwd] +CPPDEFINES=['D25', 'HPM5361'] + +group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm5301evklite/board/board.c b/bsp/hpmicro/hpm5301evklite/board/board.c new file mode 100644 index 00000000000..5c966c01141 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/board/board.c @@ -0,0 +1,490 @@ +/* + * Copyright (c) 2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "board.h" +#include "hpm_uart_drv.h" +#include "hpm_gptmr_drv.h" +#include "hpm_gpio_drv.h" +#include "hpm_usb_drv.h" +#include "hpm_clock_drv.h" +#include "hpm_pllctlv2_drv.h" +#include "hpm_i2c_drv.h" +#include "hpm_pcfg_drv.h" + +static board_timer_cb timer_cb; + +/** + * @brief FLASH configuration option definitions: + * option[0]: + * [31:16] 0xfcf9 - FLASH configuration option tag + * [15:4] 0 - Reserved + * [3:0] option words (exclude option[0]) + * option[1]: + * [31:28] Flash probe type + * 0 - SFDP SDR / 1 - SFDP DDR + * 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) + * 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V + * 6 - OctaBus DDR (SPI -> OPI DDR) + * 8 - Xccela DDR (SPI -> OPI DDR) + * 10 - EcoXiP DDR (SPI -> OPI DDR) + * [27:24] Command Pads after Power-on Reset + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [23:20] Command Pads after Configuring FLASH + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) + * 0 - Not needed + * 1 - QE bit is at bit 6 in Status Register 1 + * 2 - QE bit is at bit1 in Status Register 2 + * 3 - QE bit is at bit7 in Status Register 2 + * 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 + * [15:8] Dummy cycles + * 0 - Auto-probed / detected / default value + * Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet + * [7:4] Misc. + * 0 - Not used + * 1 - SPI mode + * 2 - Internal loopback + * 3 - External DQS + * [3:0] Frequency option + * 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz + * + * option[2] (Effective only if the bit[3:0] in option[0] > 1) + * [31:20] Reserved + * [19:16] IO voltage + * 0 - 3V / 1 - 1.8V + * [15:12] Pin group + * 0 - 1st group / 1 - 2nd group + * [11:8] Connection selection + * 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) + * [7:0] Drive Strength + * 0 - Default value + * option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports + * JESD216) + * [31:16] reserved + * [15:12] Sector Erase Command Option, not required here + * [11:8] Sector Size Option, not required here + * [7:0] Flash Size Option + * 0 - 4MB / 1 - 8MB / 2 - 16MB + */ +#if defined(FLASH_XIP) && FLASH_XIP +__attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90002, 0x00000006, 0x1000, 0x0}; +#endif + +#if defined(FLASH_UF2) && FLASH_UF2 +ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; +#endif + +void board_init_console(void) +{ +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART + console_config_t cfg; + + /* uart needs to configure pin function before enabling clock, otherwise the level change of + * uart rx pin when configuring pin function will cause a wrong data to be received. + * And a uart rx dma request will be generated by default uart fifo dma trigger level. + */ + init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE); + + /* Configure the UART clock to 24MHz */ + clock_set_source_divider(BOARD_CONSOLE_UART_CLK_NAME, clk_src_osc24m, 1U); + clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0); + + cfg.type = BOARD_CONSOLE_TYPE; + cfg.base = (uint32_t)BOARD_CONSOLE_UART_BASE; + cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_UART_CLK_NAME); + cfg.baudrate = BOARD_CONSOLE_UART_BAUDRATE; + + if (status_success != console_init(&cfg)) { + /* failed to initialize debug console */ + while (1) { + } + } +#else + while (1) + ; +#endif +#endif +} + +void board_print_banner(void) +{ + const uint8_t banner[] = "\n" +"----------------------------------------------------------------------\n" +"$$\\ $$\\ $$$$$$$\\ $$\\ $$\\ $$\\\n" +"$$ | $$ |$$ __$$\\ $$$\\ $$$ |\\__|\n" +"$$ | $$ |$$ | $$ |$$$$\\ $$$$ |$$\\ $$$$$$$\\ $$$$$$\\ $$$$$$\\\n" +"$$$$$$$$ |$$$$$$$ |$$\\$$\\$$ $$ |$$ |$$ _____|$$ __$$\\ $$ __$$\\\n" +"$$ __$$ |$$ ____/ $$ \\$$$ $$ |$$ |$$ / $$ | \\__|$$ / $$ |\n" +"$$ | $$ |$$ | $$ |\\$ /$$ |$$ |$$ | $$ | $$ | $$ |\n" +"$$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\n" +"\\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n" +"----------------------------------------------------------------------\n"; +#ifdef SDK_VERSION_STRING + printf("hpm_sdk: %s\n", SDK_VERSION_STRING); +#endif + printf("%s", banner); +} + +void board_print_clock_freq(void) +{ + printf("==============================\n"); + printf(" %s clock summary\n", BOARD_NAME); + printf("==============================\n"); + printf("cpu0:\t\t %luHz\n", clock_get_frequency(clock_cpu0)); + printf("ahb:\t\t %luHz\n", clock_get_frequency(clock_ahb)); + printf("mchtmr0:\t %luHz\n", clock_get_frequency(clock_mchtmr0)); + printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0)); + printf("==============================\n"); +} + +void board_init(void) +{ + init_xtal_pins(); + init_py_pins_as_pgpio(); + board_init_usb_dp_dm_pins(); + + board_init_clock(); + board_init_console(); + board_init_pmp(); +#if BOARD_SHOW_CLOCK + board_print_clock_freq(); +#endif +#if BOARD_SHOW_BANNER + board_print_banner(); +#endif +} + +void board_init_usb_dp_dm_pins(void) +{ + /* Disconnect usb dp/dm pins pull down 45ohm resistance */ + + while (sysctl_resource_any_is_busy(HPM_SYSCTL)) { + ; + } + if (pllctlv2_xtal_is_stable(HPM_PLLCTLV2) && pllctlv2_xtal_is_enabled(HPM_PLLCTLV2)) { + if (clock_check_in_group(clock_usb0, 0)) { + usb_phy_disable_dp_dm_pulldown(HPM_USB0); + } else { + clock_add_to_group(clock_usb0, 0); + usb_phy_disable_dp_dm_pulldown(HPM_USB0); + clock_remove_from_group(clock_usb0, 0); + } + } else { + uint8_t tmp; + tmp = sysctl_resource_target_get_mode(HPM_SYSCTL, sysctl_resource_xtal); + sysctl_resource_target_set_mode(HPM_SYSCTL, sysctl_resource_xtal, 0x03); + clock_add_to_group(clock_usb0, 0); + usb_phy_disable_dp_dm_pulldown(HPM_USB0); + clock_remove_from_group(clock_usb0, 0); + while (sysctl_resource_target_is_busy(HPM_SYSCTL, sysctl_resource_usb0)) { + ; + } + sysctl_resource_target_set_mode(HPM_SYSCTL, sysctl_resource_xtal, tmp); + } +} + +void board_init_clock(void) +{ + uint32_t cpu0_freq = clock_get_frequency(clock_cpu0); + + if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) { + /* Configure the External OSC ramp-up time: ~9ms */ + pllctlv2_xtal_set_rampup_time(HPM_PLLCTLV2, 32UL * 1000UL * 9U); + + /* Select clock setting preset1 */ + sysctl_clock_set_preset(HPM_SYSCTL, 2); + } + + /* group0[0] */ + clock_add_to_group(clock_cpu0, 0); + clock_add_to_group(clock_ahb, 0); + clock_add_to_group(clock_lmm0, 0); + clock_add_to_group(clock_mchtmr0, 0); + clock_add_to_group(clock_rom, 0); + clock_add_to_group(clock_gptmr0, 0); + clock_add_to_group(clock_gptmr1, 0); + clock_add_to_group(clock_i2c2, 0); + clock_add_to_group(clock_spi1, 0); + clock_add_to_group(clock_uart0, 0); + clock_add_to_group(clock_uart3, 0); + + clock_add_to_group(clock_watchdog0, 0); + clock_add_to_group(clock_watchdog1, 0); + clock_add_to_group(clock_mbx0, 0); + clock_add_to_group(clock_tsns, 0); + clock_add_to_group(clock_crc0, 0); + clock_add_to_group(clock_adc0, 0); + clock_add_to_group(clock_acmp, 0); + clock_add_to_group(clock_kman, 0); + clock_add_to_group(clock_gpio, 0); + clock_add_to_group(clock_hdma, 0); + clock_add_to_group(clock_xpi0, 0); + clock_add_to_group(clock_usb0, 0); + + /* Connect Group0 to CPU0 */ + clock_connect_group_to_cpu(0, 0); + + /* Bump up DCDC voltage to 1175mv */ + pcfg_dcdc_set_voltage(HPM_PCFG, 1175); + + /* Configure CPU to 360MHz, AXI/AHB to 120MHz */ + sysctl_config_cpu0_domain_clock(HPM_SYSCTL, clock_source_pll0_clk0, 2, 3); + /* Configure PLL0 Post Divider */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 0, 0); /* PLL0CLK0: 720MHz */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 1, 3); /* PLL0CLK1: 450MHz */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 2, 7); /* PLL0CLK2: 300MHz */ + /* Configure PLL0 Frequency to 720MHz */ + pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 0, 720000000); + + clock_update_core_clock(); + + /* Configure mchtmr to 24MHz */ + clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1); +} + +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) +{ + uint32_t freq = 0; + clock_name_t gptmr_clock =0; + uint32_t HPM_GPTMR = (uint32_t)ptr; + bool gptmr_valid = true; + + switch(HPM_GPTMR){ + case HPM_GPTMR0_BASE: + gptmr_clock = clock_gptmr0; + break; + case HPM_GPTMR1_BASE: + gptmr_clock = clock_gptmr1; + break; + default: + gptmr_valid = false; + } + if(gptmr_valid) + { + clock_add_to_group(gptmr_clock, 0); + clock_set_source_divider(gptmr_clock, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(gptmr_clock); + } + return freq; +} + +void board_delay_us(uint32_t us) +{ + clock_cpu_delay_us(us); +} + +void board_delay_ms(uint32_t ms) +{ + clock_cpu_delay_ms(ms); +} + +void board_timer_create(uint32_t ms, board_timer_cb cb) +{ + uint32_t gptmr_freq; + gptmr_channel_config_t config; + + timer_cb = cb; + gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config); + + clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0); + gptmr_freq = clock_get_frequency(BOARD_CALLBACK_TIMER_CLK_NAME); + + config.reload = gptmr_freq / 1000 * ms; + gptmr_channel_config(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH, &config, false); + gptmr_enable_irq(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_IRQ_MASK(BOARD_CALLBACK_TIMER_CH)); + intc_m_enable_irq_with_priority(BOARD_CALLBACK_TIMER_IRQ, 1); + + gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH); +} + +void board_init_gpio_pins(void) +{ + init_gpio_pins(); + gpio_set_pin_input(BOARD_APP_GPIO_CTRL, BOARD_APP_GPIO_INDEX, BOARD_APP_GPIO_PIN); +} + +void board_init_led_pins(void) +{ + init_led_pins_as_gpio(); + gpio_set_pin_output_with_initial(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, board_get_led_gpio_off_level()); +} + +void board_init_usb_pins(void) +{ + init_usb_pins(); + usb_hcd_set_power_ctrl_polarity(BOARD_USB, true); + /* Wait USB_PWR pin control vbus power stable. Time depend on decoupling capacitor, you can decrease or increase this time */ + board_delay_ms(100); + + /* As QFN32, QFN48 and LQFP64 has no vbus pin, so should be call usb_phy_using_internal_vbus() API to use internal vbus. */ + usb_phy_using_internal_vbus(BOARD_USB); +} + +void board_led_write(uint8_t state) +{ + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state); +} + +void board_led_toggle(void) +{ + gpio_toggle_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN); +} + +void board_init_uart(UART_Type *ptr) +{ + /* configure uart's pin before opening uart's clock */ + init_uart_pins(ptr); + board_init_uart_clock(ptr); +} + +void board_ungate_mchtmr_at_lp_mode(void) +{ + /* Keep cpu clock on wfi, so that mchtmr irq can still work after wfi */ + sysctl_set_cpu_lp_mode(HPM_SYSCTL, BOARD_RUNNING_CORE, cpu_lp_mode_ungate_cpu_clock); +} + +uint32_t board_init_spi_clock(SPI_Type *ptr) +{ + if (ptr == HPM_SPI1) { + clock_add_to_group(clock_spi1, 0); + return clock_get_frequency(clock_spi1); + } + return 0; +} + +void board_init_spi_pins(SPI_Type *ptr) +{ + init_spi_pins(ptr); +} + +void board_write_spi_cs(uint32_t pin, uint8_t state) +{ + gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state); +} + +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + init_spi_pins_with_gpio_as_cs(ptr); + gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN), + GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL); +} + +void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level) +{ + (void) usb_index; + (void) level; +} + +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) +{ + uint32_t freq = 0; + + if (ptr == HPM_ADC0) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll0_clk2, 2U); + } + + freq = clock_get_frequency(clock_adc0); + } + + return freq; +} + +void board_init_adc16_pins(void) +{ + init_adc_pins(); +} + +void board_disable_output_rgb_led(uint8_t color) +{ + (void) color; +} + +void board_enable_output_rgb_led(uint8_t color) +{ + (void) color; +} + +uint8_t board_get_led_gpio_off_level(void) +{ + return BOARD_LED_OFF_LEVEL; +} + +void board_init_pmp(void) +{ +} + +uint32_t board_init_uart_clock(UART_Type *ptr) +{ + uint32_t freq = 0U; + if (ptr == HPM_UART0) { + clock_set_source_divider(clock_uart0, clk_src_osc24m, 1); + clock_add_to_group(clock_uart0, 0); + freq = clock_get_frequency(clock_uart0); + } else if (ptr == HPM_UART2) { + clock_set_source_divider(clock_uart2, clk_src_pll0_clk2, 6); + clock_add_to_group(clock_uart2, 0); + freq = clock_get_frequency(clock_uart2); + } else if (ptr == HPM_UART3) { + clock_set_source_divider(clock_uart3, clk_src_pll0_clk2, 6); /* 50MHz */ + clock_add_to_group(clock_uart3, 0); + freq = clock_get_frequency(clock_uart3); + } + + return freq; +} + +void board_i2c_bus_clear(I2C_Type *ptr) +{ + if (i2c_get_line_scl_status(ptr) == false) { + printf("CLK is low, please power cycle the board\n"); + while (1) { + } + } + if (i2c_get_line_sda_status(ptr) == false) { + printf("SDA is low, try to issue I2C bus clear\n"); + } else { + printf("I2C bus is ready\n"); + return; + } + i2s_gen_reset_signal(ptr, 9); + board_delay_ms(100); + printf("I2C bus is cleared\n"); +} + +void board_init_i2c(I2C_Type *ptr) +{ + i2c_config_t config; + hpm_stat_t stat; + uint32_t freq; + if (ptr == NULL) { + return; + } + init_i2c_pins(ptr); + board_i2c_bus_clear(ptr); + + clock_add_to_group(clock_i2c2, 0); + /* Configure the I2C clock to 24MHz */ + clock_set_source_divider(BOARD_APP_I2C_CLK_NAME, clk_src_osc24m, 1U); + + config.i2c_mode = i2c_mode_normal; + config.is_10bit_addressing = false; + freq = clock_get_frequency(BOARD_APP_I2C_CLK_NAME); + stat = i2c_init_master(ptr, freq, &config); + if (stat != status_success) { + printf("failed to initialize i2c 0x%x\n", (uint32_t) ptr); + while (1) { + } + } + +} + diff --git a/bsp/hpmicro/hpm5301evklite/board/board.h b/bsp/hpmicro/hpm5301evklite/board/board.h new file mode 100644 index 00000000000..1c4793fbc6b --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/board/board.h @@ -0,0 +1,270 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_BOARD_H +#define _HPM_BOARD_H +#include +#include +#include "hpm_common.h" +#include "hpm_clock_drv.h" +#include "hpm_soc.h" +#include "hpm_soc_feature.h" +#include "pinmux.h" +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#include "hpm_debug_console.h" +#endif + +#define BOARD_NAME "hpm5301evklite" +#define BOARD_UF2_SIGNATURE (0x0A4D5048UL) + +/* ACMP desction */ +#define BOARD_ACMP HPM_ACMP +#define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 +#define BOARD_ACMP_IRQ IRQn_ACMP_1 +#define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ +#define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_4 /* align with used pin */ + +/* dma section */ +#define BOARD_APP_HDMA HPM_HDMA +#define BOARD_APP_HDMA_IRQ IRQn_HDMA +#define BOARD_APP_DMAMUX HPM_DMAMUX +#define TEST_DMA_CONTROLLER HPM_HDMA +#define TEST_DMA_IRQ IRQn_HDMA + +#ifndef BOARD_RUNNING_CORE +#define BOARD_RUNNING_CORE HPM_CORE0 +#endif + +#ifndef BOARD_APP_UART_BASE +#define BOARD_APP_UART_BASE HPM_UART3 +#define BOARD_APP_UART_IRQ IRQn_UART3 +#define BOARD_APP_UART_BAUDRATE (115200UL) +#define BOARD_APP_UART_CLK_NAME clock_uart3 +#define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART3_RX +#define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART3_TX +#endif + +/* uart lin sample section */ +#define BOARD_UART_LIN BOARD_APP_UART_BASE +#define BOARD_UART_LIN_IRQ BOARD_APP_UART_IRQ +#define BOARD_UART_LIN_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_UART_LIN_TX_PORT GPIO_DI_GPIOB +#define BOARD_UART_LIN_TX_PIN (15U) /* PB15 should align with used pin in pinmux configuration */ + + +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#ifndef BOARD_CONSOLE_TYPE +#define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART +#endif + +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART +#ifndef BOARD_CONSOLE_UART_BASE +#define BOARD_CONSOLE_UART_BASE HPM_UART0 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART0 +#define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX +#define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX +#endif +#define BOARD_CONSOLE_UART_BAUDRATE (115200UL) +#endif +#endif + +/* usb cdc acm uart section */ +#define BOARD_USB_CDC_ACM_UART BOARD_APP_UART_BASE +#define BOARD_USB_CDC_ACM_UART_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_USB_CDC_ACM_UART_TX_DMA_SRC BOARD_APP_UART_TX_DMA_REQ +#define BOARD_USB_CDC_ACM_UART_RX_DMA_SRC BOARD_APP_UART_RX_DMA_REQ + +/* rtthread-nano finsh section */ +#define BOARD_RT_CONSOLE_BASE BOARD_CONSOLE_UART_BASE + +/* modbus sample section */ +#define BOARD_MODBUS_UART_BASE BOARD_APP_UART_BASE +#define BOARD_MODBUS_UART_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_MODBUS_UART_RX_DMA_REQ BOARD_APP_UART_RX_DMA_REQ +#define BOARD_MODBUS_UART_TX_DMA_REQ BOARD_APP_UART_TX_DMA_REQ + +/* nor flash section */ +#define BOARD_FLASH_BASE_ADDRESS (0x80000000UL) /* Check */ +#define BOARD_FLASH_SIZE (SIZE_1MB) + +/* i2c section */ +#define BOARD_APP_I2C_BASE HPM_I2C2 +#define BOARD_APP_I2C_IRQ IRQn_I2C2 +#define BOARD_APP_I2C_CLK_NAME clock_i2c2 +#define BOARD_APP_I2C_DMA HPM_HDMA +#define BOARD_APP_I2C_DMAMUX HPM_DMAMUX +#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C2 + +/* gptmr section */ +#define BOARD_GPTMR HPM_GPTMR0 +#define BOARD_GPTMR_IRQ IRQn_GPTMR0 +#define BOARD_GPTMR_CHANNEL 0 +#define BOARD_GPTMR_DMA_SRC HPM_DMA_SRC_GPTMR0_0 +#define BOARD_GPTMR_CLK_NAME clock_gptmr0 +#define BOARD_GPTMR_PWM HPM_GPTMR0 +#define BOARD_GPTMR_PWM_CHANNEL 0 +#define BOARD_GPTMR_PWM_DMA_SRC HPM_DMA_SRC_GPTMR0_0 +#define BOARD_GPTMR_PWM_CLK_NAME clock_gptmr0 +#define BOARD_GPTMR_PWM_IRQ IRQn_GPTMR0 +#define BOARD_GPTMR_PWM_SYNC HPM_GPTMR0 +#define BOARD_GPTMR_PWM_SYNC_CHANNEL 1 +#define BOARD_GPTMR_PWM_SYNC_CLK_NAME clock_gptmr0 + +/* User LED */ +#define BOARD_LED_GPIO_CTRL HPM_GPIO0 +#define BOARD_LED_GPIO_INDEX GPIO_DI_GPIOA +#define BOARD_LED_GPIO_PIN 10 + +#define BOARD_LED_OFF_LEVEL 1 +#define BOARD_LED_ON_LEVEL 0 + +/* 12V Power Enable*/ +#define BOARD_12V_EN_GPIO_CTRL HPM_GPIO0 +#define BOARD_12V_EN_GPIO_INDEX GPIO_DI_GPIOA +#define BOARD_12V_EN_GPIO_PIN 24 + +/* gpiom section */ +#define BOARD_APP_GPIOM_BASE HPM_GPIOM +#define BOARD_APP_GPIOM_USING_CTRL HPM_FGPIO +#define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast + +/* GPIO read value macro,spec for sample cherryusb on board hpm5301evklite*/ +#define BOARD_BUTTON_PRESSED_VALUE 1 + +/* tinyuf2 button on hpm5301evklite*/ +#define BOARD_BUTTON_TINYUF2_PIN 9 + +/* User button */ +#define BOARD_APP_GPIO_CTRL HPM_GPIO0 +#define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOA +#define BOARD_APP_GPIO_PIN 3 +#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_A + +/* spi section */ +#define BOARD_APP_SPI_BASE HPM_SPI1 +#define BOARD_APP_SPI_CLK_NAME clock_spi1 +#define BOARD_APP_SPI_IRQ IRQn_SPI1 +#define BOARD_APP_SPI_SCLK_FREQ (20000000UL) +#define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U) +#define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U) +#define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI1_RX +#define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI1_TX +#define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 +#define BOARD_SPI_CS_PIN IOC_PAD_PA26 +#define BOARD_SPI_CS_ACTIVE_LEVEL (0U) + +/* ADC section */ +#define BOARD_APP_ADC16_NAME "ADC0" +#define BOARD_APP_ADC16_BASE HPM_ADC0 +#define BOARD_APP_ADC16_IRQn IRQn_ADC0 +#define BOARD_APP_ADC16_CH_1 (11U) +#define BOARD_APP_ADC16_CLK_NAME (clock_adc0) + +#define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A + +/* Flash section */ +#define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) +#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90002U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000006U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) + +/* CALLBACK TIMER section */ +#define BOARD_CALLBACK_TIMER (HPM_GPTMR1) +#define BOARD_CALLBACK_TIMER_CH 0 +#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR1 +#define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr1) + +/*Timer define*/ +#define BOARD_BLDC_TMR_1MS HPM_GPTMR2 +#define BOARD_BLDC_TMR_CH 0 +#define BOARD_BLDC_TMR_CMP 0 +#define BOARD_BLDC_TMR_IRQ IRQn_GPTMR2 +#define BOARD_BLDC_TMR_RELOAD (100000U) + +/*adc*/ +#define BOARD_BLDC_ADC_MODULE (ADCX_MODULE_ADC16) +#define BOARD_BLDC_ADC_U_BASE HPM_ADC0 +#define BOARD_BLDC_ADC_V_BASE HPM_ADC1 +#define BOARD_BLDC_ADC_W_BASE HPM_ADC1 +#define BOARD_BLDC_ADC_TRIG_FLAG adc16_event_trig_complete + +#define BOARD_BLDC_ADC_CH_U (5U) +#define BOARD_BLDC_ADC_CH_V (6U) +#define BOARD_BLDC_ADC_CH_W (4U) +#define BOARD_BLDC_ADC_IRQn IRQn_ADC0 +#define BOARD_BLDC_ADC_PMT_DMA_SIZE_IN_4BYTES (ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES) +#define BOARD_BLDC_ADC_TRG ADC16_CONFIG_TRG0A +#define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) +#define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U) +#define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A + +/* USB */ +#define BOARD_USB HPM_USB0 + +#ifndef BOARD_SHOW_CLOCK +#define BOARD_SHOW_CLOCK 1 +#endif +#ifndef BOARD_SHOW_BANNER +#define BOARD_SHOW_BANNER 1 +#endif + +/* FreeRTOS Definitions */ +#define BOARD_FREERTOS_TIMER HPM_GPTMR0 +#define BOARD_FREERTOS_TIMER_CHANNEL 1 +#define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR0 +#define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr0 + +/* Threadx Definitions */ +#define BOARD_THREADX_TIMER HPM_GPTMR0 +#define BOARD_THREADX_TIMER_CHANNEL 1 +#define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR0 +#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr0 +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +typedef void (*board_timer_cb)(void); + +void board_init_console(void); +void board_init_gpio_pins(void); +void board_init_led_pins(void); +void board_init_usb_pins(void); +void board_led_write(uint8_t state); +void board_led_toggle(void); +void board_init_uart(UART_Type *ptr); +uint32_t board_init_spi_clock(SPI_Type *ptr); +void board_init_spi_pins(SPI_Type *ptr); +void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb); +void board_init_adc16_pins(void); +void board_disable_output_rgb_led(uint8_t color); +void board_enable_output_rgb_led(uint8_t color); +void board_write_spi_cs(uint32_t pin, uint8_t state); +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); + +void board_init(void); +void board_init_usb_dp_dm_pins(void); +void board_init_clock(void); +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); +void board_delay_us(uint32_t us); +void board_delay_ms(uint32_t ms); +void board_timer_create(uint32_t ms, board_timer_cb cb); +void board_ungate_mchtmr_at_lp_mode(void); + +uint8_t board_get_led_gpio_off_level(void); + +void board_init_pmp(void); + +uint32_t board_init_uart_clock(UART_Type *ptr); + +void board_init_i2c(I2C_Type *ptr); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _HPM_BOARD_H */ diff --git a/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/boards/hpm5301evklite.cfg b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/boards/hpm5301evklite.cfg new file mode 100644 index 00000000000..7d495f5b380 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/boards/hpm5301evklite.cfg @@ -0,0 +1,79 @@ +# Copyright (c) 2023 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# openocd flash driver argument: +# - option0: +# [31:28] Flash probe type +# 0 - SFDP SDR / 1 - SFDP DDR +# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) +# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V +# 6 - OctaBus DDR (SPI -> OPI DDR) +# 8 - Xccela DDR (SPI -> OPI DDR) +# 10 - EcoXiP DDR (SPI -> OPI DDR) +# [27:24] Command Pads after Power-on Reset +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [23:20] Command Pads after Configuring FLASH +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) +# 0 - Not needed +# 1 - QE bit is at bit 6 in Status Register 1 +# 2 - QE bit is at bit1 in Status Register 2 +# 3 - QE bit is at bit7 in Status Register 2 +# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 +# [15:8] Dummy cycles +# 0 - Auto-probed / detected / default value +# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet +# [7:4] Misc. +# 0 - Not used +# 1 - SPI mode +# 2 - Internal loopback +# 3 - External DQS +# [3:0] Frequency option +# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz +# - option1: +# [31:20] Reserved +# [19:16] IO voltage +# 0 - 3V / 1 - 1.8V +# [15:12] Pin group +# 0 - 1st group / 1 - 2nd group +# [11:8] Connection selection +# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) +# [7:0] Drive Strength +# 0 - Default value + +# xpi0 configs +# - flash driver: hpm_xpi +# - flash ctrl index: 0xF3000000 +# - base address: 0x80000000 +# - flash size: 0x2000000 +# - flash option0: 0x7 +flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x6 0x1000 + +proc init_clock {} { + $::_TARGET0 riscv dmi_write 0x39 0xF4002000 + $::_TARGET0 riscv dmi_write 0x3C 0x1 + + $::_TARGET0 riscv dmi_write 0x39 0xF4002000 + $::_TARGET0 riscv dmi_write 0x3C 0x2 + + $::_TARGET0 riscv dmi_write 0x39 0xF4000800 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000810 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000820 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000830 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + echo "clocks has been enabled!" +} + +$_TARGET0 configure -event reset-init { + init_clock +} + +$_TARGET0 configure -event gdb-attach { + reset halt +} diff --git a/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/probes/cmsis_dap.cfg b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/probes/cmsis_dap.cfg new file mode 100644 index 00000000000..0aa1eed3dad --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/probes/cmsis_dap.cfg @@ -0,0 +1,11 @@ +# Copyright (c) 2021 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 8000 +adapter srst delay 500 + +source [find interface/cmsis-dap.cfg] + +transport select jtag +reset_config srst_only diff --git a/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/probes/ft2232.cfg b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/probes/ft2232.cfg new file mode 100644 index 00000000000..782edbcf509 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/probes/ft2232.cfg @@ -0,0 +1,15 @@ +# Copyright (c) 2021 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +reset_config trst_and_srst +adapter srst delay 50 + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0208 0x020b +ftdi_layout_signal nTRST -data 0x0200 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0100 -noe 0x0800 + diff --git a/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/probes/ft232.cfg b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/probes/ft232.cfg new file mode 100644 index 00000000000..e2c01a2d788 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/probes/ft232.cfg @@ -0,0 +1,14 @@ +# Copyright (c) 2021 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +reset_config trst_and_srst +adapter srst delay 50 + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6014 + +ftdi_layout_init 0x0018 0x001b +ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/probes/jlink.cfg b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/probes/jlink.cfg new file mode 100644 index 00000000000..5d565c0ecc3 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/probes/jlink.cfg @@ -0,0 +1,11 @@ +# Copyright (c) 2021 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 + +source [find interface/jlink.cfg] + +transport select jtag +reset_config srst_only diff --git a/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/probes/nds_aice_micro.cfg b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/probes/nds_aice_micro.cfg new file mode 100644 index 00000000000..a9421a83877 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/probes/nds_aice_micro.cfg @@ -0,0 +1,14 @@ +# Copyright (c) 2021 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 +reset_config srst_only + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x010b +ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm5300.cfg b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm5300.cfg new file mode 100644 index 00000000000..c57a36d0174 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm5300.cfg @@ -0,0 +1,13 @@ +# Copyright (c) 2021 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +set _CHIP hpm5301 +set _CPUTAPID 0x1000563D +jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID + +set _TARGET0 $_CHIP.cpu0 +target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0 + +$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 + +targets $_TARGET0 diff --git a/bsp/hpmicro/hpm5301evklite/board/fal_cfg.h b/bsp/hpmicro/hpm5301evklite/board/fal_cfg.h new file mode 100644 index 00000000000..40d0330d450 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/board/fal_cfg.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + +#ifdef RT_USING_FAL +#define NOR_FLASH_DEV_NAME "norflash0" +#define NOR_FLASH_MEM_BASE 0x80000000UL +#define NOR_FLASH_SIZE_IN_BYTES 0x1000000UL + +/* ===================== Flash device Configuration ========================= */ +extern const struct fal_flash_dev stm32f2_onchip_flash; +extern struct fal_flash_dev nor_flash0; + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &nor_flash0, \ +} +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG +/* partition table */ +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WORD, "app", NOR_FLASH_DEV_NAME, 0, 256*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME, 256*1024, 256*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "download", NOR_FLASH_DEV_NAME, 512*1024, 256*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "flashdb", NOR_FLASH_DEV_NAME, 768*1024, 256*1024, 0}, \ +} +#endif /* FAL_PART_HAS_TABLE_CFG */ +#endif /* RT_USING_FAL */ + +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/hpmicro/hpm5301evklite/board/fal_flash_port.c b/bsp/hpmicro/hpm5301evklite/board/fal_flash_port.c new file mode 100644 index 00000000000..1ed9fdffd69 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/board/fal_flash_port.c @@ -0,0 +1,254 @@ +/* + * Copyright (c) 2022-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2022-03-09 hpmicro First implementation + * 2022-08-01 hpmicro Fixed random crashing during kvdb_init + * 2022-08-03 hpmicro Improved erase speed + * 2023-01-31 hpmicro Fix random crashing issue if the global interrupt is always enabled + * + */ +#include +#include +#ifdef RT_USING_FAL +#include "fal.h" +#include "hpm_romapi.h" +#include "board.h" +#include "hpm_l1c_drv.h" + + +#define FAL_ENTER_CRITICAL() do {\ + disable_global_irq(CSR_MSTATUS_MIE_MASK);\ + }while(0) + +#define FAL_EXIT_CRITICAL() do {\ + enable_global_irq(CSR_MSTATUS_MIE_MASK);\ + }while(0) + +#define FAL_RAMFUNC __attribute__((section(".isr_vector"))) + + +/*************************************************************************************************** + * FAL Porting Guide + * + * 1. Most FLASH devices do not support RWW (Read-while-Write), the codes to access the FLASH + * must be placed at RAM or ROM code + * 2. During FLASH erase/program, it is recommended to disable the interrupt, or place the + * interrupt related codes to RAM + * + ***************************************************************************************************/ + +static int init(void); +static int read(long offset, uint8_t *buf, size_t size); +static int write(long offset, const uint8_t *buf, size_t size); +static int erase(long offset, size_t size); + +static xpi_nor_config_t s_flashcfg; + +/** + * @brief FAL Flash device context + */ +struct fal_flash_dev nor_flash0 = + { + .name = NOR_FLASH_DEV_NAME, + /* If porting this code to the device with FLASH connected to XPI1, the address must be changed to 0x90000000 */ + .addr = NOR_FLASH_MEM_BASE, + .len = 8 * 1024 * 1024, + .blk_size = 4096, + .ops = { .init = init, .read = read, .write = write, .erase = erase }, + .write_gran = 1 + }; + +/** + * @brief FAL initialization + * This function probes the FLASH using the ROM API + */ +FAL_RAMFUNC static int init(void) +{ + int ret = RT_EOK; + xpi_nor_config_option_t cfg_option; + cfg_option.header.U = BOARD_APP_XPI_NOR_CFG_OPT_HDR; + cfg_option.option0.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT0; + cfg_option.option1.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT1; + + FAL_ENTER_CRITICAL(); + hpm_stat_t status = rom_xpi_nor_auto_config(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, &cfg_option); + FAL_EXIT_CRITICAL(); + if (status != status_success) + { + ret = -RT_ERROR; + } + else + { + s_flashcfg.device_info.clk_freq_for_non_read_cmd = 0U; + /* update the flash chip information */ + uint32_t sector_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, §or_size); + uint32_t flash_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_total_size, &flash_size); + nor_flash0.blk_size = sector_size; + nor_flash0.len = flash_size; + } + + return ret; +} + +/** + * @brief FAL read function + * Read data from FLASH + * @param offset FLASH offset + * @param buf Buffer to hold data read by this API + * @param size Size of data to be read + * @return actual read bytes + */ +FAL_RAMFUNC static int read(long offset, uint8_t *buf, size_t size) +{ + uint32_t flash_addr = nor_flash0.addr + offset; + uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN(flash_addr); + uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP(flash_addr + size); + uint32_t aligned_size = aligned_end - aligned_start; + rt_base_t level = rt_hw_interrupt_disable(); + l1c_dc_invalidate(aligned_start, aligned_size); + rt_hw_interrupt_enable(level); + + (void) rt_memcpy(buf, (void*) flash_addr, size); + + return size; +} + +/** + * @brief Write unaligned data to the page + * @param offset FLASH offset + * @param buf Data buffer + * @param size Size of data to be written + * @return actual size of written data or error code + */ +FAL_RAMFUNC static int write_unaligned_page_data(long offset, const uint32_t *buf, size_t size) +{ + hpm_stat_t status; + + FAL_ENTER_CRITICAL(); + status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, buf, offset, size); + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + return -RT_ERROR; + rt_kprintf("write failed, status=%d\n", status); + } + + return size; +} + +/** + * @brief FAL write function + * Write data to specified FLASH address + * @param offset FLASH offset + * @param buf Data buffer + * @param size Size of data to be written + * @return actual size of written data or error code + */ +FAL_RAMFUNC static int write(long offset, const uint8_t *buf, size_t size) +{ + uint32_t *src = NULL; + uint32_t buf_32[64]; + uint32_t write_size; + size_t remaining_size = size; + int ret = (int)size; + + uint32_t page_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_page_size, &page_size); + uint32_t offset_in_page = offset % page_size; + if (offset_in_page != 0) + { + uint32_t write_size_in_page = page_size - offset_in_page; + uint32_t write_page_size = MIN(write_size_in_page, size); + (void) rt_memcpy(buf_32, buf, write_page_size); + write_size = write_unaligned_page_data(offset, buf_32, write_page_size); + if (write_size < 0) + { + ret = -RT_ERROR; + goto write_quit; + } + + remaining_size -= write_page_size; + offset += write_page_size; + buf += write_page_size; + } + + while (remaining_size > 0) + { + write_size = MIN(remaining_size, sizeof(buf_32)); + rt_memcpy(buf_32, buf, write_size); + src = &buf_32[0]; + + FAL_ENTER_CRITICAL(); + hpm_stat_t status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, src, + offset, write_size); + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + ret = -RT_ERROR; + rt_kprintf("write failed, status=%d\n", status); + break; + } + + remaining_size -= write_size; + buf += write_size; + offset += write_size; + } + +write_quit: + return ret; +} + +/** + * @brief FAL erase function + * Erase specified FLASH region + * @param offset the start FLASH address to be erased + * @param size size of the region to be erased + * @ret RT_EOK Erase operation is successful + * @retval -RT_ERROR Erase operation failed + */ +FAL_RAMFUNC static int erase(long offset, size_t size) +{ + uint32_t aligned_size = (size + nor_flash0.blk_size - 1U) & ~(nor_flash0.blk_size - 1U); + hpm_stat_t status; + int ret = (int)size; + + uint32_t block_size; + uint32_t sector_size; + (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, §or_size); + (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_block_size, &block_size); + uint32_t erase_unit; + while (aligned_size > 0) + { + FAL_ENTER_CRITICAL(); + if ((offset % block_size == 0) && (aligned_size >= block_size)) + { + erase_unit = block_size; + status = rom_xpi_nor_erase_block(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset); + } + else + { + erase_unit = sector_size; + status = rom_xpi_nor_erase_sector(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset); + } + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + ret = -RT_ERROR; + break; + } + offset += erase_unit; + aligned_size -= erase_unit; + } + + return ret; +} +#endif /* RT_USING_FAL */ diff --git a/bsp/hpmicro/hpm5301evklite/board/linker_scripts/flash_rtt.ld b/bsp/hpmicro/hpm5301evklite/board/linker_scripts/flash_rtt.ld new file mode 100644 index 00000000000..7f3af8a529c --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/board/linker_scripts/flash_rtt.ld @@ -0,0 +1,288 @@ +/* + * Copyright 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 1M; + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 32K; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K + AHB_SRAM (w) : ORIGIN = 0xf0400000, LENGTH = 32K +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .fast : AT(etext + __data_end__ - __tdata_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + + /* RT-Thread Core Start */ + KEEP(*context_gcc.o(.text* .rodata*)) + KEEP(*port*.o (.text .text* .rodata .rodata*)) + KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) + KEEP(*trap_common.o (.text .text* .rodata .rodata*)) + KEEP(*irq.o (.text .text* .rodata .rodata*)) + KEEP(*clock.o (.text .text* .rodata .rodata*)) + KEEP(*kservice.o (.text .text* .rodata .rodata*)) + KEEP(*scheduler.o (.text .text* .rodata .rodata*)) + KEEP(*trap*.o (.text .text* .rodata .rodata*)) + KEEP(*idle.o (.text .text* .rodata .rodata*)) + KEEP(*ipc.o (.text .text* .rodata .rodata*)) + KEEP(*thread.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*timer.o (.text .text* .rodata .rodata*)) + KEEP(*mem.o (.text .text* .rodata .rodata*)) + KEEP(*mempool.o (.text .text* .rodata .rodata*)) + /* RT-Thread Core End */ + + . = ALIGN(8); + __ramfunc_end__ = .; + } > ILM + + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + /* Note: the .tbss and .tdata section should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > DLM + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > DLM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + + .heap(NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE( __rt_rvstack = . ); + } > DLM + + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > DLM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > DLM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + /* __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + __share_mem_start__ = ORIGIN(SHARE_RAM); + __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); */ + +} diff --git a/bsp/hpmicro/hpm5301evklite/board/linker_scripts/ram_rtt.ld b/bsp/hpmicro/hpm5301evklite/board/linker_scripts/ram_rtt.ld new file mode 100644 index 00000000000..196cbe56efe --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/board/linker_scripts/ram_rtt.ld @@ -0,0 +1,244 @@ +/* + * Copyright 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x2000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x8000; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 0x8000; + +MEMORY +{ + ILM (wx) : ORIGIN = 0, LENGTH = 128K + DLM (w) : ORIGIN = 0x80000, LENGTH = 128K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x98000, LENGTH = NONCACHEABLE_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > ILM + + .vectors : { + . = ALIGN(8); + KEEP(*(.isr_vector)) + KEEP(*(.vector_table)) + . = ALIGN(8); + } > ILM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > ILM + + .text : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + *(FalPartTable) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + } > ILM + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > DLM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + + .fast : AT(etext + __data_end__ - __tdata_start__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > DLM + + .rel : { + KEEP(*(.rel*)) + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + /* Note: .tbss and .tdata should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > DLM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE (__rt_rvstack = .); + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + + } > DLM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); +} diff --git a/bsp/hpmicro/hpm5301evklite/board/pinmux.c b/bsp/hpmicro/hpm5301evklite/board/pinmux.c new file mode 100644 index 00000000000..bc17b8750de --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/board/pinmux.c @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* + * Note: + * PY and PZ IOs: if any SOC pin function needs to be routed to these IOs, + * besides of IOC, PIOC/BIOC needs to be configured SOC_GPIO_X_xx, so that + * expected SoC function can be enabled on these IOs. + * + */ +#include "board.h" +#include "pinmux.h" + +void init_xtal_pins(void) +{ + /* Package QFN32 should be set PA30 and PA31 pins as analog type to enable xtal. */ + /* + * HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + * HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + */ +} + +void init_py_pins_as_pgpio(void) +{ + /* Set PY00-PY05 default function to PGPIO */ + HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_PGPIO_Y_00; + HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_PGPIO_Y_01; + HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = PIOC_PY02_FUNC_CTL_PGPIO_Y_02; + HPM_PIOC->PAD[IOC_PAD_PY03].FUNC_CTL = PIOC_PY03_FUNC_CTL_PGPIO_Y_03; + HPM_PIOC->PAD[IOC_PAD_PY04].FUNC_CTL = PIOC_PY04_FUNC_CTL_PGPIO_Y_04; + HPM_PIOC->PAD[IOC_PAD_PY05].FUNC_CTL = PIOC_PY05_FUNC_CTL_PGPIO_Y_05; +} + +void init_uart_pins(UART_Type *ptr) +{ + if (ptr == HPM_UART0) { + HPM_IOC->PAD[IOC_PAD_PA00].FUNC_CTL = IOC_PA00_FUNC_CTL_UART0_TXD; + HPM_IOC->PAD[IOC_PAD_PA01].FUNC_CTL = IOC_PA01_FUNC_CTL_UART0_RXD; + } else if (ptr == HPM_UART2) { + HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_UART2_TXD; + HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_UART2_RXD; + HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_UART2_DE; + } else if (ptr == HPM_UART3) { + HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_UART3_TXD; + HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PB14_FUNC_CTL_UART3_RXD; + } else { + ; + } +} + +/* for uart_lin case, need to configure pin as gpio to sent break signal */ +void init_uart_pin_as_gpio(UART_Type *ptr) +{ + /* pull-up */ + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + + if (ptr == HPM_UART3) { + HPM_IOC->PAD[IOC_PAD_PB15].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PB14].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_GPIO_B_15; + HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PB14_FUNC_CTL_GPIO_B_14; + } +} + +void init_i2c_pins(I2C_Type *ptr) +{ + if (ptr == HPM_I2C2) { + HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_I2C2_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_I2C2_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PB08].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PB09].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + } else { + ; + } +} + +void init_gpio_pins(void) +{ + /* configure pad setting: pull enable and pull down, schmitt trigger enable */ + /* enable schmitt trigger to eliminate jitter of pin used as button */ + + /* Button */ + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(0) | IOC_PAD_PAD_CTL_HYS_SET(1); + HPM_IOC->PAD[IOC_PAD_PA03].FUNC_CTL = IOC_PA03_FUNC_CTL_GPIO_A_03; + HPM_IOC->PAD[IOC_PAD_PA03].PAD_CTL = pad_ctl; +} + +void init_spi_pins(SPI_Type *ptr) +{ + if (ptr == HPM_SPI1) { + HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_SPI1_CS_0; + HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_SPI1_MISO; + HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_SPI1_MOSI; + } +} + +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + if (ptr == HPM_SPI1) { + HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_GPIO_A_26; + HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_SPI1_MISO; + HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_SPI1_MOSI; + } +} + + +void init_gptmr_pins(GPTMR_Type *ptr) +{ + (void) ptr; +} + +void init_butn_pins(void) +{ + /* configure pad setting: pull enable and pull up, schmitt trigger enable */ + /* enable schmitt trigger to eliminate jitter of pin used as button */ + + /* Button */ + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_SET(1); + HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_GPIO_A_09; + HPM_IOC->PAD[IOC_PAD_PA09].PAD_CTL = pad_ctl; +} + +void init_acmp_pins(void) +{ + /* configure to ACMP_COMP_1(ALT16) function */ + HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_ACMP_COMP_1; + /* configure to CMP1_INN4 function */ + HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_adc_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_A: ADC0.11/ADC1.11 */ + HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_B: ADC0.1 /ADC1.1 */ + HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_C: ADC0.2 /ADC1.2 */ + HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_D: ADC0.3 /ADC1.3 */ + HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IW: ADC0.4 /ADC1.4 */ + HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IU: ADC0.5 /ADC1.5 */ + HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IV: ADC0.6 /ADC1.6 */ + HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* Board ID: ADC0.7 /ADC1.7 */ +} + +void init_adc_bldc_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IU: ADC0.5 /ADC1.5 */ + HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IV: ADC0.6 /ADC1.6 */ +} + +void init_usb_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + + /* USB0_ID */ + HPM_IOC->PAD[IOC_PAD_PY00].FUNC_CTL = IOC_PY00_FUNC_CTL_USB0_ID; + /* USB0_OC */ + HPM_IOC->PAD[IOC_PAD_PY01].FUNC_CTL = IOC_PY01_FUNC_CTL_USB0_OC; + /* USB0_PWR */ + HPM_IOC->PAD[IOC_PAD_PY02].FUNC_CTL = IOC_PY02_FUNC_CTL_USB0_PWR; + + /* PY port IO needs to configure PIOC as well */ + HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_SOC_GPIO_Y_00; + HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_SOC_GPIO_Y_01; + HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = PIOC_PY02_FUNC_CTL_SOC_GPIO_Y_02; +} + +void init_led_pins_as_gpio(void) +{ + HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_GPIO_A_10; +} + diff --git a/bsp/hpmicro/hpm5301evklite/board/pinmux.h b/bsp/hpmicro/hpm5301evklite/board/pinmux.h new file mode 100644 index 00000000000..4e5f2e53040 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/board/pinmux.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PINMUX_H +#define HPM_PINMUX_H + +#ifdef __cplusplus +extern "C" { +#endif +void init_xtal_pins(void); +void init_py_pins_as_pgpio(void); +void init_uart_pins(UART_Type *ptr); +void init_i2c_pins(I2C_Type *ptr); +void init_gpio_pins(void); +void init_spi_pins(SPI_Type *ptr); +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); +void init_gptmr_pins(GPTMR_Type *ptr); +void init_butn_pins(void); +void init_acmp_pins(void); +void init_adc_pins(void); +void init_adc_bldc_pins(void); +void init_usb_pins(void); +void init_led_pins_as_gpio(void); +#ifdef __cplusplus +} +#endif +#endif /* HPM_PINMUX_H */ diff --git a/bsp/hpmicro/hpm5301evklite/board/rtt_board.c b/bsp/hpmicro/hpm5301evklite/board/rtt_board.c new file mode 100644 index 00000000000..1ac0279b9e7 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/board/rtt_board.c @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2023-2024 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "board.h" +#include "rtt_board.h" +#include "hpm_uart_drv.h" +#include "hpm_gpio_drv.h" +#include "hpm_pmp_drv.h" +#include "assert.h" +#include "hpm_clock_drv.h" +#include "hpm_sysctl_drv.h" +#include +#include +#include "hpm_dma_mgr.h" +#include "hpm_mchtmr_drv.h" + +extern int rt_hw_uart_init(void); +void os_tick_config(void); +void rtt_board_init(void); + +void rt_hw_board_init(void) +{ + rtt_board_init(); + + /* Call the RT-Thread Component Board Initialization */ + rt_components_board_init(); +} + +void os_tick_config(void) +{ + sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1); + sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0); + mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND); + enable_mchtmr_irq(); +} + +void rtt_board_init(void) +{ + board_init_clock(); + board_init_console(); + board_init_pmp(); + + dma_mgr_init(); + + /* initialize memory system */ + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); + + /* Configure the OS Tick */ + os_tick_config(); + + /* Configure the USB pins*/ + board_init_usb_pins(); + + /* Initialize the UART driver first, because later driver initialization may require the rt_kprintf */ + rt_hw_uart_init(); + + /* Set console device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +} + +void app_init_led_pins(void) +{ + gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN); + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, BOARD_LED_OFF_LEVEL); +} + +void app_led_write(uint32_t index, bool state) +{ + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state); +} + + +void BOARD_LED_write(uint32_t index, bool state) +{ + switch (index) + { + case 0: + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state); + break; + default: + /* Suppress the toolchain warnings */ + break; + } +} + +void rt_hw_console_output(const char *str) +{ + while (*str != '\0') + { + uart_send_byte(BOARD_APP_UART_BASE, *str++); + } +} + +void app_init_usb_pins(void) +{ + board_init_usb_pins(); +} + +ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) +{ + HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND; + + rt_tick_increase(); +} + +void rt_hw_cpu_reset(void) +{ + HPM_PPOR->RESET_ENABLE = (1UL << 31); + + HPM_PPOR->SOFTWARE_RESET = 1000U; + while(1) { + + } +} + +MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board); diff --git a/bsp/hpmicro/hpm5301evklite/board/rtt_board.h b/bsp/hpmicro/hpm5301evklite/board/rtt_board.h new file mode 100644 index 00000000000..9bb7db4b652 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/board/rtt_board.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _RTT_BOARD_H +#define _RTT_BOARD_H +#include "hpm_common.h" +#include "hpm_soc.h" +#include + +/* gpio section */ +#define APP_LED0_PIN_NUM GET_PIN(A, 10) +#define APP_LED_ON (1) +#define APP_LED_OFF (0) + + + +/* mchtimer section */ +#define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL) + +/* CAN section */ +#define BOARD_CAN_NAME "can0" +#define BOARD_CAN_HWFILTER_INDEX (0U) + +/* UART section */ +#define BOARD_UART_NAME "uart2" +#define BOARD_UART_RX_BUFFER_SIZE BSP_UART2_RX_BUFSIZE + +#define IRQn_PendSV IRQn_DEBUG0 + +/*************************************************************** + * + * RT-Thread related definitions + * + **************************************************************/ +extern unsigned int __heap_start__; +extern unsigned int __heap_end__; + +#define RT_HW_HEAP_BEGIN ((void*)&__heap_start__) +#define RT_HW_HEAP_END ((void*)&__heap_end__) + + +typedef struct { + uint16_t vdd; + uint8_t bus_width; + uint8_t drive_strength; +}sdxc_io_cfg_t; + +void app_init_led_pins(void); +void app_led_write(uint32_t index, bool state); +void app_init_usb_pins(void); + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + + + + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _RTT_BOARD_H */ diff --git a/bsp/hpmicro/hpm5301evklite/figures/board.png b/bsp/hpmicro/hpm5301evklite/figures/board.png new file mode 100644 index 00000000000..f893cf6b115 Binary files /dev/null and b/bsp/hpmicro/hpm5301evklite/figures/board.png differ diff --git a/bsp/hpmicro/hpm5301evklite/rtconfig.h b/bsp/hpmicro/hpm5301evklite/rtconfig.h new file mode 100644 index 00000000000..3d78319912e --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/rtconfig.h @@ -0,0 +1,254 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 1024 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 1024 + +/* kservice optimization */ + + +/* klibc optimization */ + + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x50200 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_LEGACY +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V2 +#define RT_USING_PIN + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + + +/* Memory protection */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* CYW43012 WiFi */ + + +/* BL808 WiFi */ + + +/* CYW43439 WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + +/* sensors drivers */ + + +/* touch drivers */ + + +/* Kendryte SDK */ + + +/* AI packages */ + + +/* Signal Processing and Control Algorithm Packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Arduino libraries */ + + +/* Projects and Demos */ + + +/* Sensors */ + + +/* Display */ + + +/* Timing */ + + +/* Data Processing */ + + +/* Data Storage */ + +/* Communication */ + + +/* Device Control */ + + +/* Other */ + + +/* Signal IO */ + + +/* Uncategorized */ + +/* Hardware Drivers Config */ + +#define SOC_HPM5000 + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART0 +#define BSP_UART0_RX_BUFSIZE 128 +#define BSP_UART0_TX_BUFSIZE 0 + +#endif diff --git a/bsp/hpmicro/hpm5301evklite/rtconfig.py b/bsp/hpmicro/hpm5301evklite/rtconfig.py new file mode 100644 index 00000000000..229741746af --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/rtconfig.py @@ -0,0 +1,109 @@ +# Copyright 2021-2023 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +import os +import sys + +# toolchains options +ARCH='risc-v' +CPU='hpmicro' +CHIP_NAME='HPM5301' + +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +# Fallback toolchain info +FALLBACK_TOOLCHAIN_VENDOR='RISC-V' +FALLBACK_TOOLCHAIN_PKG='RISC-V-GCC-RV32' +FALLBACK_TOOLCHAIN_VER='2022-04-12' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +RTT_EXEC_PATH = os.getenv('RTT_EXEC_PATH') +if RTT_EXEC_PATH != None: + folders = RTT_EXEC_PATH.split(os.sep) + # If the `RT-Thread Env` is from the RT-Thread Studio, generate the RTT_EXEC_PATH using `FALLBACK_TOOLCHAIN_INFO` + if 'arm_gcc' in folders and 'platform' in folders: + RTT_EXEC_PATH = '' + for path in folders: + if path != 'platform': + RTT_EXEC_PATH = RTT_EXEC_PATH + path + os.sep + else: + break + RTT_EXEC_PATH = os.path.join(RTT_EXEC_PATH, 'repo', 'Extract', 'ToolChain_Support_Packages', FALLBACK_TOOLCHAIN_VENDOR, FALLBACK_TOOLCHAIN_PKG, FALLBACK_TOOLCHAIN_VER, 'bin') + # Override the 'RTT_RISCV_TOOLCHAIN' only if the `RT-Thread ENV` is from the RT-Thread Studio + if 'platform' in folders: + os.environ['RTT_RISCV_TOOLCHAIN'] = RTT_EXEC_PATH + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler path, for example, GNU RISC-V toolchain, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + if os.getenv('RTT_RISCV_TOOLCHAIN'): + EXEC_PATH = os.getenv('RTT_RISCV_TOOLCHAIN') + else: + EXEC_PATH = r'/opt/riscv-gnu-gcc/bin' +else: + print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL) + +BUILD = 'flash_debug' + +if PLATFORM == 'gcc': + PREFIX = 'riscv32-unknown-elf-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + GDB = PREFIX + 'gdb' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + ARCH_ABI = ' -mcmodel=medlow ' + DEVICE = ARCH_ABI + ' -DUSE_NONVECTOR_MODE=1 ' + ' -ffunction-sections -fdata-sections -fno-common ' + CFLAGS = DEVICE + AFLAGS = CFLAGS + LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections ' + + CPATH = '' + LPATH = '' + + if BUILD == 'ram_debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + LFLAGS += ' -O0' + LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + elif BUILD == 'ram_release': + CFLAGS += ' -O2' + LFLAGS += ' -O2' + LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + elif BUILD == 'flash_debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + LFLAGS += ' -O0' + CFLAGS += ' -DFLASH_XIP=1' + LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + elif BUILD == 'flash_release': + CFLAGS += ' -O2' + LFLAGS += ' -O2' + CFLAGS += ' -DFLASH_XIP=1' + LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + else: + CFLAGS += ' -O2' + LFLAGS += ' -O2' + LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + LFLAGS += ' -T ' + LINKER_FILE + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + + # module setting + CXXFLAGS = CFLAGS + ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' + CFLAGS = CFLAGS + ' -std=gnu11' \ No newline at end of file diff --git a/bsp/hpmicro/hpm5301evklite/startup/HPM5301/SConscript b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/SConscript new file mode 100644 index 00000000000..3e8dd931d38 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/SConscript @@ -0,0 +1,22 @@ +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() + +# add the startup files + +src = Split(''' + startup.c + trap.c +''') + +if rtconfig.PLATFORM == 'gcc': + src += [os.path.join('toolchains', 'gcc', 'start.S')] + src += [os.path.join('toolchains', 'gcc', 'port_gcc.S')] + +CPPPATH = [cwd] +CPPDEFINES=['D45', rtconfig.CHIP_NAME] + +group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm5301evklite/startup/HPM5301/startup.c b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/startup.c new file mode 100644 index 00000000000..b0bab335d52 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/startup.c @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * + */ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" +#include + +void system_init(void); + +extern int entry(void); + +extern void __libc_init_array(void); +extern void __libc_fini_array(void); + +void system_init(void) +{ + disable_global_irq(CSR_MSTATUS_MIE_MASK); + disable_irq_from_intc(); + enable_irq_from_intc(); + enable_global_irq(CSR_MSTATUS_MIE_MASK); +#ifndef CONFIG_NOT_ENABLE_ICACHE + l1c_ic_enable(); +#endif +#ifndef CONFIG_NOT_ENABLE_DCACHE + l1c_dc_enable(); +#endif +} + +__attribute__((weak)) void c_startup(void) +{ + uint32_t i, size; +#ifdef FLASH_XIP + extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; + size = __vector_ram_end__ - __vector_ram_start__; + for (i = 0; i < size; i++) { + *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); + } +#endif + + extern uint8_t __etext[]; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __tbss_start__[], __tbss_end__[]; + extern uint8_t __tdata_start__[], __tdata_end__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + + /* tbss section */ + size = __tbss_end__ - __tbss_start__; + for (i = 0; i < size; i++) { + *(__tbss_start__ + i) = 0; + } + + /* bss section */ + size = __bss_end__ - __bss_start__; + for (i = 0; i < size; i++) { + *(__bss_start__ + i) = 0; + } + + /* noncacheable bss section */ + size = __noncacheable_bss_end__ - __noncacheable_bss_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_bss_start__ + i) = 0; + } + + /* tdata section LMA: etext */ + size = __tdata_end__ - __tdata_start__; + for (i = 0; i < size; i++) { + *(__tdata_start__ + i) = *(__etext + i); + } + + /* data section LMA: etext */ + size = __data_end__ - __data_start__; + for (i = 0; i < size; i++) { + *(__data_start__ + i) = *(__etext + (__tdata_end__ - __tdata_start__) + i); + } + + /* ramfunc section LMA: etext + data length */ + size = __ramfunc_end__ - __ramfunc_start__; + for (i = 0; i < size; i++) { + *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + i); + } + + /* noncacheable init section LMA: etext + data length + ramfunc length */ + size = __noncacheable_init_end__ - __noncacheable_init_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); + } +} + +__attribute__((weak)) int main(void) +{ + while(1); +} + +void reset_handler(void) +{ + /** + * Disable preemptive interrupt + */ + HPM_PLIC->FEATURE = 0; + /* + * Initialize LMA/VMA sections. + * Relocation for any sections that need to be copied from LMA to VMA. + */ + c_startup(); + + /* Call platform specific hardware initialization */ + system_init(); + + /* Do global constructors */ + __libc_init_array(); + + + + /* Entry function */ + entry(); +} + + +__attribute__((weak)) void _init() +{ +} diff --git a/bsp/hpmicro/hpm5301evklite/startup/HPM5301/toolchains/gcc/port_gcc.S b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/toolchains/gcc/port_gcc.S new file mode 100644 index 00000000000..2708b48e455 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/toolchains/gcc/port_gcc.S @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "cpuport.h" + + .globl rt_hw_do_after_save_above + .type rt_hw_do_after_save_above,@function +rt_hw_do_after_save_above: + addi sp, sp, -4 + STORE ra, 0 * REGBYTES(sp) + + csrr t1, mcause + andi t1, t1, 0x3FF + /* get ISR */ + la t2, trap_entry + jalr t2 + + LOAD ra, 0 * REGBYTES(sp) + addi sp, sp, 4 + ret diff --git a/bsp/hpmicro/hpm5301evklite/startup/HPM5301/toolchains/gcc/start.S b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/toolchains/gcc/start.S new file mode 100644 index 00000000000..76463936442 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/toolchains/gcc/start.S @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + #include + #include "hpm_csr_regs.h" + .section .start, "ax" + + .global _start + .type _start,@function + +_start: + /* Initialize global pointer */ + .option push + .option norelax + la gp, __global_pointer$ + la tp, __thread_pointer + .option pop + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + /* Initialize stack pointer */ + la t0, _stack + mv sp, t0 + +#ifdef __nds_execit + /* Initialize EXEC.IT table */ + la t0, _ITB_BASE_ + csrw uitb, t0 +#endif + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + /* Disable Vector mode */ + csrci CSR_MMISC_CTL, 2 + /* Initialize trap_entry base */ + la t0, SW_handler + csrw mtvec, t0 + + + /* System reset handler */ + call reset_handler + + /* Infinite loop, if returned accidently */ +1: j 1b + + .weak nmi_handler +nmi_handler: +1: j 1b + + .global default_irq_handler + .weak default_irq_handler + .align 2 +default_irq_handler: +1: j 1b + + .macro IRQ_HANDLER irq + .weak default_isr_\irq + .set default_isr_\irq, default_irq_handler + .long default_isr_\irq + .endm + +#include "vectors.S" diff --git a/bsp/hpmicro/hpm5301evklite/startup/HPM5301/toolchains/gcc/vectors.S b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/toolchains/gcc/vectors.S new file mode 100644 index 00000000000..8f10ab7bddf --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/toolchains/gcc/vectors.S @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +.section .vector_table, "a" +.global __vector_table +.align 9 + +__vector_table: + .weak default_isr_trap + .set default_isr_trap, SW_handler + .long default_isr_trap + IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_HANDLER 5 /* GPIO0_X IRQ handler */ + IRQ_HANDLER 6 /* GPIO0_Y IRQ handler */ + IRQ_HANDLER 7 /* GPIO0_Z IRQ handler */ + IRQ_HANDLER 8 /* ADC0 IRQ handler */ + IRQ_HANDLER 9 /* ADC1 IRQ handler */ + IRQ_HANDLER 10 /* ADC2 IRQ handler */ + IRQ_HANDLER 11 /* DAC IRQ handler */ + IRQ_HANDLER 12 /* ACMP[0] IRQ handler */ + IRQ_HANDLER 13 /* ACMP[1] IRQ handler */ + IRQ_HANDLER 14 /* SPI0 IRQ handler */ + IRQ_HANDLER 15 /* SPI1 IRQ handler */ + IRQ_HANDLER 16 /* SPI2 IRQ handler */ + IRQ_HANDLER 17 /* SPI3 IRQ handler */ + IRQ_HANDLER 18 /* UART0 IRQ handler */ + IRQ_HANDLER 19 /* UART1 IRQ handler */ + IRQ_HANDLER 20 /* UART2 IRQ handler */ + IRQ_HANDLER 21 /* UART3 IRQ handler */ + IRQ_HANDLER 22 /* UART4 IRQ handler */ + IRQ_HANDLER 23 /* UART5 IRQ handler */ + IRQ_HANDLER 24 /* UART6 IRQ handler */ + IRQ_HANDLER 25 /* UART7 IRQ handler */ + IRQ_HANDLER 26 /* CAN0 IRQ handler */ + IRQ_HANDLER 27 /* CAN1 IRQ handler */ + IRQ_HANDLER 28 /* PTPC IRQ handler */ + IRQ_HANDLER 29 /* WDG0 IRQ handler */ + IRQ_HANDLER 30 /* WDG1 IRQ handler */ + IRQ_HANDLER 31 /* TSNS IRQ handler */ + IRQ_HANDLER 32 /* MBX0A IRQ handler */ + IRQ_HANDLER 33 /* MBX0B IRQ handler */ + IRQ_HANDLER 34 /* GPTMR0 IRQ handler */ + IRQ_HANDLER 35 /* GPTMR1 IRQ handler */ + IRQ_HANDLER 36 /* GPTMR2 IRQ handler */ + IRQ_HANDLER 37 /* GPTMR3 IRQ handler */ + IRQ_HANDLER 38 /* I2C0 IRQ handler */ + IRQ_HANDLER 39 /* I2C1 IRQ handler */ + IRQ_HANDLER 40 /* I2C2 IRQ handler */ + IRQ_HANDLER 41 /* I2C3 IRQ handler */ + IRQ_HANDLER 42 /* PWM0 IRQ handler */ + IRQ_HANDLER 43 /* HALL0 IRQ handler */ + IRQ_HANDLER 44 /* QEI0 IRQ handler */ + IRQ_HANDLER 45 /* PWM1 IRQ handler */ + IRQ_HANDLER 46 /* HALL1 IRQ handler */ + IRQ_HANDLER 47 /* QEI1 IRQ handler */ + IRQ_HANDLER 48 /* SDP IRQ handler */ + IRQ_HANDLER 49 /* XPI0 IRQ handler */ + IRQ_HANDLER 50 /* XPI1 IRQ handler */ + IRQ_HANDLER 51 /* XDMA IRQ handler */ + IRQ_HANDLER 52 /* HDMA IRQ handler */ + IRQ_HANDLER 53 /* DRAM IRQ handler */ + IRQ_HANDLER 54 /* RNG IRQ handler */ + IRQ_HANDLER 55 /* I2S0 IRQ handler */ + IRQ_HANDLER 56 /* I2S1 IRQ handler */ + IRQ_HANDLER 57 /* DAO IRQ handler */ + IRQ_HANDLER 58 /* PDM IRQ handler */ + IRQ_HANDLER 59 /* FFA IRQ handler */ + IRQ_HANDLER 60 /* NTMR0 IRQ handler */ + IRQ_HANDLER 61 /* USB0 IRQ handler */ + IRQ_HANDLER 62 /* ENET0 IRQ handler */ + IRQ_HANDLER 63 /* SDXC0 IRQ handler */ + IRQ_HANDLER 64 /* PSEC IRQ handler */ + IRQ_HANDLER 65 /* PGPIO IRQ handler */ + IRQ_HANDLER 66 /* PWDG IRQ handler */ + IRQ_HANDLER 67 /* PTMR IRQ handler */ + IRQ_HANDLER 68 /* PUART IRQ handler */ + IRQ_HANDLER 69 /* FUSE IRQ handler */ + IRQ_HANDLER 70 /* SECMON IRQ handler */ + IRQ_HANDLER 71 /* RTC IRQ handler */ + IRQ_HANDLER 72 /* BUTN IRQ handler */ + IRQ_HANDLER 73 /* BGPIO IRQ handler */ + IRQ_HANDLER 74 /* BVIO IRQ handler */ + IRQ_HANDLER 75 /* BROWNOUT IRQ handler */ + IRQ_HANDLER 76 /* SYSCTL IRQ handler */ + IRQ_HANDLER 77 /* DEBUG[0] IRQ handler */ + IRQ_HANDLER 78 /* DEBUG[1] IRQ handler */ diff --git a/bsp/hpmicro/hpm5301evklite/startup/HPM5301/trap.c b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/trap.c new file mode 100644 index 00000000000..b87eaee5244 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/trap.c @@ -0,0 +1,304 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_common.h" +#include "hpm_soc.h" +#include +#include "rt_hw_stack_frame.h" + +#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) //!< Instruction Address misaligned +#define MCAUSE_INSTR_ACCESS_FAULT (1U) //!< Instruction access fault +#define MCAUSE_ILLEGAL_INSTR (2U) //!< Illegal instruction +#define MCAUSE_BREAKPOINT (3U) //!< Breakpoint +#define MCAUSE_LOAD_ADDR_MISALIGNED (4U) //!< Load address misaligned +#define MCAUSE_LOAD_ACCESS_FAULT (5U) //!< Load access fault +#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U) //!< Store/AMO address misaligned +#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U) //!< Store/AMO access fault +#define MCAUSE_ECALL_FROM_USER_MODE (8U) //!< Environment call from User mode +#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U) //!< Environment call from Supervisor mode +#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U) //!< Environment call from machine mode +#define MCAUSE_INSTR_PAGE_FAULT (12U) //!< Instruction page fault +#define MCAUSE_LOAD_PAGE_FAULT (13) //!< Load page fault +#define MCAUSE_STORE_AMO_PAGE_FAULT (15U) //!< Store/AMO page fault + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#ifdef DEBUG +#define RT_EXCEPTION_TRACE rt_kprintf +#else +#define RT_EXCEPTION_TRACE(...) +#endif + +typedef void (*isr_func_t)(void); + +static volatile rt_hw_stack_frame_t *s_stack_frame; + +__attribute((weak)) void mchtmr_isr(void) +{ +} + +__attribute__((weak)) void mswi_isr(void) +{ +} + +__attribute__((weak)) void syscall_handler(uint32_t n, uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3) +{ +} + +void rt_show_stack_frame(void) +{ + RT_EXCEPTION_TRACE("Stack frame:\r\n----------------------------------------\r\n"); + RT_EXCEPTION_TRACE("ra : 0x%08x\r\n", s_stack_frame->ra); + RT_EXCEPTION_TRACE("mstatus : 0x%08x\r\n", read_csr(0x300));//mstatus + RT_EXCEPTION_TRACE("t0 : 0x%08x\r\n", s_stack_frame->t0); + RT_EXCEPTION_TRACE("t1 : 0x%08x\r\n", s_stack_frame->t1); + RT_EXCEPTION_TRACE("t2 : 0x%08x\r\n", s_stack_frame->t2); + RT_EXCEPTION_TRACE("a0 : 0x%08x\r\n", s_stack_frame->a0); + RT_EXCEPTION_TRACE("a1 : 0x%08x\r\n", s_stack_frame->a1); + RT_EXCEPTION_TRACE("a2 : 0x%08x\r\n", s_stack_frame->a2); + RT_EXCEPTION_TRACE("a3 : 0x%08x\r\n", s_stack_frame->a3); + RT_EXCEPTION_TRACE("a4 : 0x%08x\r\n", s_stack_frame->a4); + RT_EXCEPTION_TRACE("a5 : 0x%08x\r\n", s_stack_frame->a5); +#ifndef __riscv_32e + RT_EXCEPTION_TRACE("a6 : 0x%08x\r\n", s_stack_frame->a6); + RT_EXCEPTION_TRACE("a7 : 0x%08x\r\n", s_stack_frame->a7); + RT_EXCEPTION_TRACE("t3 : 0x%08x\r\n", s_stack_frame->t3); + RT_EXCEPTION_TRACE("t4 : 0x%08x\r\n", s_stack_frame->t4); + RT_EXCEPTION_TRACE("t5 : 0x%08x\r\n", s_stack_frame->t5); + RT_EXCEPTION_TRACE("t6 : 0x%08x\r\n", s_stack_frame->t6); +#endif +} + +uint32_t exception_handler(uint32_t cause, uint32_t epc) +{ + /* Unhandled Trap */ + uint32_t mdcause = read_csr(CSR_MDCAUSE); + uint32_t mtval = read_csr(CSR_MTVAL); + rt_uint32_t mscratch = read_csr(0x340); + + s_stack_frame = (rt_hw_stack_frame_t *)mscratch; + rt_show_stack_frame(); + + switch (cause) + { + case MCAUSE_INSTR_ADDR_MISALIGNED: + RT_EXCEPTION_TRACE("exception: instruction address was mis-aligned, mtval=0x%08x\n", mtval); + break; + case MCAUSE_INSTR_ACCESS_FAULT: + RT_EXCEPTION_TRACE("exception: instruction access fault happened, mtval=0x%08x, epc=0x%08x\n", mtval, epc); + switch (mdcause & 0x07) + { + case 1: + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); + break; + case 4: + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); + break; + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_ILLEGAL_INSTR: + RT_EXCEPTION_TRACE("exception: illegal instruction was met, mtval=0x%08x\n", mtval); + switch (mdcause & 0x07) + { + case 0: + RT_EXCEPTION_TRACE("mdcause: the actual faulting instruction is stored in the mtval CSR\r\n"); + break; + case 1: + RT_EXCEPTION_TRACE("mdcause: FP disabled exception \r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: ACE disabled exception \r\n"); + break; + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_BREAKPOINT: + RT_EXCEPTION_TRACE("exception: breakpoint was hit, mtval=0x%08x\n", mtval); + break; + case MCAUSE_LOAD_ADDR_MISALIGNED: + RT_EXCEPTION_TRACE("exception: load address was mis-aligned, mtval=0x%08x\n", mtval); + break; + case MCAUSE_LOAD_ACCESS_FAULT: + RT_EXCEPTION_TRACE("exception: load access fault happened, epc=%08x, mdcause=0x%x\n", epc, mdcause); + switch (mdcause & 0x07) + { + case 1: + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); + break; + case 4: + RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n"); + break; + case 5: + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); + break; + case 6: + RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n"); + break; + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_STORE_AMO_ADDR_MISALIGNED: + RT_EXCEPTION_TRACE("exception: store amo address was misaligned, epc=%08x\n", epc); + break; + case MCAUSE_STORE_AMO_ACCESS_FAULT: + RT_EXCEPTION_TRACE("exception: store amo access fault happened, epc=%08x\n", epc); + switch (mdcause & 0x07) + { + case 1: + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); + break; + case 4: + RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n"); + break; + case 5: + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); + break; + case 6: + RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n"); + break; + case 7: + RT_EXCEPTION_TRACE("mdcause: PMA NAMO exception \r\n"); + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + default: + RT_EXCEPTION_TRACE("Unknown exception happened, cause=%d\n", cause); + break; + } + + rt_kprintf("cause=0x%08x, epc=0x%08x, ra=0x%08x\n", cause, epc, s_stack_frame->ra); + while(1) { + } +} + +void trap_entry(void); + +void trap_entry(void) +{ + uint32_t mcause = read_csr(CSR_MCAUSE); + uint32_t mepc = read_csr(CSR_MEPC); + uint32_t mstatus = read_csr(CSR_MSTATUS); + +#if SUPPORT_PFT_ARCH + uint32_t mxstatus = read_csr(CSR_MXSTATUS); +#endif +#ifdef __riscv_dsp + int ucode = read_csr(CSR_UCODE); +#endif +#ifdef __riscv_flen + int fcsr = read_fcsr(); +#endif + + /* clobbers list for ecall */ +#ifdef __riscv_32e + __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3"); +#else + __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3"); +#endif + + /* Do your trap handling */ + uint32_t cause_type = mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK; + uint32_t irq_index; + if (mcause & CSR_MCAUSE_INTERRUPT_MASK) + { + switch (cause_type) + { + /* Machine timer interrupt */ + case IRQ_M_TIMER: + mchtmr_isr(); + break; + /* Machine EXT interrupt */ + case IRQ_M_EXT: + /* Claim interrupt */ + irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); + /* Execute EXT interrupt handler */ + if (irq_index > 0) + { + ((isr_func_t) __vector_table[irq_index])(); + /* Complete interrupt */ + __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index); + } + break; + /* Machine SWI interrupt */ + case IRQ_M_SOFT: + mswi_isr(); + intc_m_complete_swi(); + break; + } + } + else if (cause_type == MCAUSE_ECALL_FROM_MACHINE_MODE) + { + /* Machine Syscal call */ + __asm volatile( + "mv a4, a3\n" + "mv a3, a2\n" + "mv a2, a1\n" + "mv a1, a0\n" +#ifdef __riscv_32e + "mv a0, t0\n" +#else + "mv a0, a7\n" +#endif + "call syscall_handler\n" + : : : "a4" + ); + mepc += 4; + } + else + { + mepc = exception_handler(mcause, mepc); + } + + /* Restore CSR */ + write_csr(CSR_MSTATUS, mstatus); + write_csr(CSR_MEPC, mepc); +#if SUPPORT_PFT_ARCH + write_csr(CSR_MXSTATUS, mxstatus); +#endif +#ifdef __riscv_dsp + write_csr(CSR_UCODE, ucode); +#endif +#ifdef __riscv_flen + write_fcsr(fcsr); +#endif +} diff --git a/bsp/hpmicro/hpm5301evklite/startup/SConscript b/bsp/hpmicro/hpm5301evklite/startup/SConscript new file mode 100644 index 00000000000..de51a7c0d63 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/startup/SConscript @@ -0,0 +1,13 @@ +# for module compiling +import os +Import('rtconfig') +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] + +objs = objs + SConscript(os.path.join(cwd, rtconfig.CHIP_NAME, 'SConscript')) +ASFLAGS = ' -I' + cwd + +Return('objs') \ No newline at end of file diff --git a/bsp/hpmicro/hpm6200evk/README.md b/bsp/hpmicro/hpm6200evk/README.md index c4940261611..fe1b40a1a5c 100644 --- a/bsp/hpmicro/hpm6200evk/README.md +++ b/bsp/hpmicro/hpm6200evk/README.md @@ -49,7 +49,7 @@ The BSP support being build via the 'scons' command, below is the steps of compi - Download the package and extract it into a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain` - Step 3: Set environment variable `RTT_RISCV_TOOLCHAIN` to `\bin` - For example: `C:\DevTools\riscv32-gnu-toolchain\bin` -- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip) +- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip) - Download and extract it to specified directory, for example: `C:\DevTools\openocd-hpmicro` - Add `OpenOCD` environment variable `OPENOCD_HPMICRO` to `\bin` - For example: `C:\DevTools\openocd-hpmicro\bin` diff --git a/bsp/hpmicro/hpm6200evk/README_zh.md b/bsp/hpmicro/hpm6200evk/README_zh.md index 95ad6a5a941..d1fc210afd9 100644 --- a/bsp/hpmicro/hpm6200evk/README_zh.md +++ b/bsp/hpmicro/hpm6200evk/README_zh.md @@ -53,7 +53,7 @@ - 步骤 2: 准备 [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) - 下载并解压到指定的目录，如: `C:\DevTools\riscv32-gnu-toolchain` - 步骤 3: 设置环境变量： `RTT_RISCV_TOOLCHAIN` 为 `\bin`， 如: `C:\DevTools\riscv32-gnu-toolchain\bin` -- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip) +- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip) - 下载并解压到指定目录，如: `C:\DevTools\openocd-hpmicro` - 将 `OPENOCD_HPMICRO`环境变量设置为 `\bin`，如： `C:\DevTools\openocd-hpmicro\bin` diff --git a/bsp/hpmicro/hpm6200evk/board/Kconfig b/bsp/hpmicro/hpm6200evk/board/Kconfig index 5f352d3fba0..6ce12455b88 100644 --- a/bsp/hpmicro/hpm6200evk/board/Kconfig +++ b/bsp/hpmicro/hpm6200evk/board/Kconfig @@ -27,75 +27,45 @@ menu "On-chip Peripheral Drivers" bool "Enable UART0 RX DMA" depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA default n - config BSP_UART0_TX_USING_DMA bool "Enable UART0 TX DMA" depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA default n - - config BSP_UART0_RX_DMA_CHANNEL - int "Set UART0 RX DMA CHANNEL" - range 0 7 - depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA - default 0 - - config BSP_UART0_TX_DMA_CHANNEL - int "Set UART0 TX DMA CHANNEL" - range 0 7 - depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA - default 1 - config BSP_UART0_RX_BUFSIZE int "Set UART0 RX buffer size" range 64 65535 depends on RT_USING_SERIAL_V2 default 128 - config BSP_UART0_TX_BUFSIZE int "Set UART0 TX buffer size" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 endif - menuconfig BSP_USING_UART2 + menuconfig BSP_USING_UART2 bool "Enable UART2" - default n + default y if BSP_USING_UART2 config BSP_UART2_RX_USING_DMA bool "Enable UART2 RX DMA" depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA - default n - + default y config BSP_UART2_TX_USING_DMA bool "Enable UART2 TX DMA" - depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA - default n - - config BSP_UART2_RX_DMA_CHANNEL - int "Set UART2 RX DMA CHANNEL" - range 0 7 depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA - default 0 - - config BSP_UART2_TX_DMA_CHANNEL - int "Set UART2 TX DMA CHANNEL" - range 0 7 - depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA - default 1 - + default n config BSP_UART2_RX_BUFSIZE int "Set UART2 RX buffer size" range 64 65535 depends on RT_USING_SERIAL_V2 default 1024 - config BSP_UART2_TX_BUFSIZE int "Set UART2 TX buffer size" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 endif - menuconfig BSP_USING_UART6 + menuconfig BSP_USING_UART6 bool "Enable UART6" default n if BSP_USING_UART6 @@ -103,30 +73,15 @@ menu "On-chip Peripheral Drivers" bool "Enable UART6 RX DMA" depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA default n - config BSP_UART6_TX_USING_DMA bool "Enable UART6 TX DMA" depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA default n - - config BSP_UART6_RX_DMA_CHANNEL - int "Set UART6 RX DMA CHANNEL" - range 0 7 - depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA - default 0 - - config BSP_UART6_TX_DMA_CHANNEL - int "Set UART6 TX DMA CHANNEL" - range 0 7 - depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA - default 1 - config BSP_UART6_RX_BUFSIZE int "Set UART6 RX buffer size" range 64 65535 depends on RT_USING_SERIAL_V2 default 1024 - config BSP_UART6_TX_BUFSIZE int "Set UART6 TX buffer size" range 0 65535 @@ -144,32 +99,34 @@ menu "On-chip Peripheral Drivers" if BSP_USING_SPI config BSP_USING_SPI1 bool "Enable SPI1" - default y + default y + if BSP_USING_SPI1 + config BSP_SPI1_USING_DMA + bool "Enable SPI1 DMA" + default n + endif config BSP_USING_SPI2 bool "Enable SPI2" + default n + if BSP_USING_SPI2 + config BSP_SPI2_USING_DMA + bool "Enable SPI2 DMA" default n + endif config BSP_USING_SPI3 bool "Enable SPI3" + default n + if BSP_USING_SPI3 + config BSP_SPI3_USING_DMA + bool "Enable SPI3 DMA" default n + endif endif menuconfig BSP_USING_RTC bool "Enable RTC" default n - menuconfig BSP_USING_ETH - bool "Enable Ethernet" - default n - - select RT_USING_ETH - if BSP_USING_ETH - choice - prompt "ETH" - config BSP_USING_ETH0 - bool "Enable ETH0" - endchoice - endif - menuconfig BSP_USING_SDXC bool "Enable SDXC" default n @@ -177,96 +134,104 @@ menu "On-chip Peripheral Drivers" if BSP_USING_SDXC config BSP_USING_SDXC0 bool "Enable SDXC0" - default n + default n endif menuconfig BSP_USING_GPTMR - bool "Enable GPTMR" - default n - select RT_USING_HWTIMER if BSP_USING_GPTMR - if BSP_USING_GPTMR - config BSP_USING_GPTMR0 - bool "Enable GPTMR0" - default n - config BSP_USING_GPTMR1 - bool "Enable GPTMR1" - default n - config BSP_USING_GPTMR2 - bool "Enable GPTMR2" - default n + bool "Enable GPTMR" + default n + select RT_USING_HWTIMER if BSP_USING_GPTMR + if BSP_USING_GPTMR + config BSP_USING_GPTMR1 + bool "Enable GPTMR1" + default n + config BSP_USING_GPTMR2 + bool "Enable GPTMR2" + default n endif + menuconfig BSP_USING_I2C bool "Enable I2C" default n if BSP_USING_I2C config BSP_USING_I2C0 bool "Enable I2C0" - default y - + default y + if BSP_USING_I2C0 + config BSP_I2C0_USING_DMA + bool "Enable I2C0 DMA" + default n + endif config BSP_USING_I2C3 bool "Enable I2C3" + default n + if BSP_USING_I2C3 + config BSP_I2C3_USING_DMA + bool "Enable I2C3 DMA" default n + endif endif menuconfig BSP_USING_XPI_FLASH - bool "Enable XPI FLASH" - default n - select PKG_USING_FAL if BSP_USING_XPI_FLASH + bool "Enable XPI FLASH" + default n + select RT_USING_FAL if BSP_USING_XPI_FLASH menuconfig BSP_USING_PWM bool "Enable PWM" - default n + default n menuconfig BSP_USING_USB bool "Enable USB" default n if BSP_USING_USB - config BSP_USING_USB_DEVICE + config BSP_USING_USB_DEVICE bool "Enable USB Device" - default n + default n config BSP_USING_USB_HOST bool "Enable USB HOST" - default n + select RT_USING_CACHE + default n endif - menuconfig BSP_USING_WDG - bool "Enable Watchdog" - default n - select RT_USING_WDT if BSP_USING_WDG - if BSP_USING_WDG - config BSP_USING_WDG0 - bool "Enable WDG0" - default n - config BSP_USING_WDG1 - bool "Enable WDG1" - default n - endif + menuconfig BSP_USING_WDG + bool "Enable Watchdog" + default n + select RT_USING_WDT if BSP_USING_WDG + if BSP_USING_WDG + config BSP_USING_WDG0 + bool "Enable WDG0" + default n + config BSP_USING_WDG1 + bool "Enable WDG1" + default n + endif - menuconfig BSP_USING_MCAN - bool "Enable MCAN" - default n - select RT_USING_CAN if BSP_USING_MCAN - if BSP_USING_MCAN - config BSP_USING_MCAN0 - bool "Enable MCAN0" - default n - config BSP_USING_MCAN1 - bool "Enable MCAN1" - default n + menuconfig BSP_USING_MCAN + bool "Enable MCAN" + default n + select RT_USING_CAN if BSP_USING_MCAN + if BSP_USING_MCAN + config BSP_USING_MCAN0 + bool "Enable MCAN0" + default n + config BSP_USING_MCAN1 + bool "Enable MCAN1" + default n config BSP_USING_MCAN2 - bool "Enable MCAN2" - default n - config BSP_USING_MCAN3 - bool "Enable MCAN3" - default n - endif + bool "Enable MCAN2" + default n + config BSP_USING_MCAN3 + bool "Enable MCAN3" + default n + endif - menuconfig BSP_USING_ADC - bool "Enable ADC" - default n - select RT_USING_ADC if BSP_USING_ADC - if BSP_USING_ADC + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC if BSP_USING_ADC + if BSP_USING_ADC menuconfig BSP_USING_ADC16 bool "Enable ADC16" default y @@ -284,6 +249,36 @@ menu "On-chip Peripheral Drivers" endif endmenu +menu "Segger SystemView Config" + config BSP_USING_SYSTEMVIEW + select RT_USING_SYSTEMVIEW + select RT_USING_LEGACY + bool "Enable Segger SystemView" + default n + if BSP_USING_SYSTEMVIEW + menuconfig BSP_SYSTEMVIEW_RTT_SECTION + bool "enable SystemView RTT section" + default y + if BSP_SYSTEMVIEW_RTT_SECTION + config SEGGER_RTT_SECTION + string "segger rtt section" + default ".noncacheable.bss" + config SEGGER_RTT_BUFFER_SECTION + string "segger rtt buffer section" + default ".noncacheable.bss" + config SEGGER_SYSVIEW_SECTION + string "segger sysview section" + default ".noncacheable.bss" + endif + source "$RTT_DIR/../libraries/misc/systemview/Kconfig" + endif +endmenu + +menu "Hpmicro Interrupt Config" + config HPM_USING_VECTOR_PREEMPTED_MODE + bool "Enable Vector and Preempted Mode" + default n +endmenu endmenu diff --git a/bsp/hpmicro/hpm6200evk/board/board.c b/bsp/hpmicro/hpm6200evk/board/board.c index 2fe5ce3f98a..6a9d4b3cf3f 100644 --- a/bsp/hpmicro/hpm6200evk/board/board.c +++ b/bsp/hpmicro/hpm6200evk/board/board.c @@ -94,16 +94,16 @@ void board_init_console(void) /* uart needs to configure pin function before enabling clock, otherwise the level change of uart rx pin when configuring pin function will cause a wrong data to be received. And a uart rx dma request will be generated by default uart fifo dma trigger level. */ - init_uart_pins((UART_Type *) BOARD_CONSOLE_BASE); + init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE); /* Configure the UART clock to 24MHz */ - clock_set_source_divider(BOARD_CONSOLE_CLK_NAME, clk_src_osc24m, 1U); - clock_add_to_group(BOARD_CONSOLE_CLK_NAME, 0); + clock_set_source_divider(BOARD_CONSOLE_UART_CLK_NAME, clk_src_osc24m, 1U); + clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0); cfg.type = BOARD_CONSOLE_TYPE; - cfg.base = (uint32_t)BOARD_CONSOLE_BASE; - cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_CLK_NAME); - cfg.baudrate = BOARD_CONSOLE_BAUDRATE; + cfg.base = (uint32_t)BOARD_CONSOLE_UART_BASE; + cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_UART_CLK_NAME); + cfg.baudrate = BOARD_CONSOLE_UART_BAUDRATE; if (status_success != console_init(&cfg)) { /* failed to initialize debug console */ @@ -122,13 +122,13 @@ void board_print_clock_freq(void) printf("==============================\n"); printf(" %s clock summary\n", BOARD_NAME); printf("==============================\n"); - printf("cpu0:\t\t %dHz\n", clock_get_frequency(clock_cpu0)); + printf("cpu0:\t\t %luHz\n", clock_get_frequency(clock_cpu0)); printf("cpu1:\t\t %luHz\n", clock_get_frequency(clock_cpu1)); - printf("axi:\t\t %dHz\n", clock_get_frequency(clock_axi)); - printf("ahb:\t\t %dHz\n", clock_get_frequency(clock_ahb)); - printf("mchtmr0:\t %dHz\n", clock_get_frequency(clock_mchtmr0)); + printf("axi:\t\t %luHz\n", clock_get_frequency(clock_axi)); + printf("ahb:\t\t %luHz\n", clock_get_frequency(clock_ahb)); + printf("mchtmr0:\t %luHz\n", clock_get_frequency(clock_mchtmr0)); printf("mchtmr1:\t %luHz\n", clock_get_frequency(clock_mchtmr1)); - printf("xpi0:\t\t %dHz\n", clock_get_frequency(clock_xpi0)); + printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0)); printf("==============================\n"); } @@ -187,31 +187,20 @@ void board_init(void) #endif } -void board_delay_us(uint32_t us) +void board_init_core1(void) { - static uint32_t gptmr_freq; - gptmr_channel_config_t config; - - if (init_delay_flag == false) { - init_delay_flag = true; - clock_add_to_group(BOARD_DELAY_TIMER_CLK_NAME, 0); - gptmr_freq = clock_get_frequency(BOARD_DELAY_TIMER_CLK_NAME); - gptmr_channel_get_default_config(BOARD_DELAY_TIMER, &config); - gptmr_channel_config(BOARD_DELAY_TIMER, BOARD_DELAY_TIMER_CH, &config, false); - } + board_init_console(); + board_init_pmp(); +} - gptmr_channel_config_update_reload(BOARD_DELAY_TIMER, BOARD_DELAY_TIMER_CH, gptmr_freq / 1000000 * us); - gptmr_start_counter(BOARD_DELAY_TIMER, BOARD_DELAY_TIMER_CH); - while (!gptmr_check_status(BOARD_DELAY_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_DELAY_TIMER_CH))) { - __asm("nop"); - } - gptmr_stop_counter(BOARD_DELAY_TIMER, BOARD_DELAY_TIMER_CH); - gptmr_clear_status(BOARD_DELAY_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_DELAY_TIMER_CH)); +void board_delay_us(uint32_t us) +{ + clock_cpu_delay_us(us); } void board_delay_ms(uint32_t ms) { - board_delay_us(1000 * ms); + clock_cpu_delay_ms(ms); } void board_timer_isr(void) @@ -245,10 +234,62 @@ void board_timer_create(uint32_t ms, board_timer_cb cb) void board_i2c_bus_clear(I2C_Type *ptr) { init_i2c_pins_as_gpio(ptr); + if (ptr == BOARD_APP_I2C_BASE) { + gpio_set_pin_input(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SDA_GPIO_INDEX, BOARD_I2C_SDA_GPIO_PIN); + gpio_set_pin_input(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN); + if (!gpio_read_pin(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN)) { + printf("CLK is low, please power cycle the board\n"); + while (1) { + } + } + if (!gpio_read_pin(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SDA_GPIO_INDEX, BOARD_I2C_SDA_GPIO_PIN)) { + printf("SDA is low, try to issue I2C bus clear\n"); + } else { + printf("I2C bus is ready\n"); + return; + } + + gpio_set_pin_output(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN); + while (1) { + for (uint32_t i = 0; i < 9; i++) { + gpio_write_pin(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN, 1); + board_delay_ms(10); + gpio_write_pin(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN, 0); + board_delay_ms(10); + } + board_delay_ms(100); + } + printf("I2C bus is cleared\n"); + } } void board_init_i2c(I2C_Type *ptr) { + i2c_config_t config; + hpm_stat_t stat; + uint32_t freq; + if (ptr == NULL) { + return; + } + + board_i2c_bus_clear(ptr); + init_i2c_pins(ptr); + clock_add_to_group(clock_i2c0, 0); + clock_add_to_group(clock_i2c1, 0); + clock_add_to_group(clock_i2c2, 0); + clock_add_to_group(clock_i2c3, 0); + /* Configure the I2C clock to 24MHz */ + clock_set_source_divider(BOARD_APP_I2C_CLK_NAME, clk_src_osc24m, 1U); + + config.i2c_mode = i2c_mode_normal; + config.is_10bit_addressing = false; + freq = clock_get_frequency(BOARD_APP_I2C_CLK_NAME); + stat = i2c_init_master(ptr, freq, &config); + if (stat != status_success) { + printf("failed to initialize i2c 0x%x\n", (uint32_t) ptr); + while (1) { + } + } } uint32_t board_init_spi_clock(SPI_Type *ptr) @@ -275,6 +316,11 @@ uint32_t board_init_spi_clock(SPI_Type *ptr) return 0; } +void board_init_lin_pins(LIN_Type *ptr) +{ + init_lin_pins(ptr); +} + uint32_t board_init_lin_clock(LIN_Type *ptr) { if (ptr == HPM_LIN0) { @@ -368,6 +414,8 @@ uint8_t board_get_usb_id_status(void) void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level) { + (void) usb_index; + (void) level; } void board_init_pmp(void) @@ -499,20 +547,17 @@ void board_init_clock(void) /* Bump up DCDC voltage to 1275mv */ pcfg_dcdc_set_voltage(HPM_PCFG, 1275); - /* Configure CPU to 600MHz, AXI/AHB to 200MHz */ - sysctl_config_cpu0_domain_clock(HPM_SYSCTL, clk_src_pll1_clk0, 1, 3, 3); /* Connect CAN2/CAN3 to pll0clk0*/ clock_set_source_divider(clock_can2, clk_src_pll0_clk0, 1); clock_set_source_divider(clock_can3, clk_src_pll0_clk0, 1); + /* Configure CPU to 600MHz, AXI/AHB to 200MHz */ + sysctl_config_cpu0_domain_clock(HPM_SYSCTL, clock_source_pll1_clk0, 1, 3, 3); /* Configure PLL1_CLK0 Post Divider to 1 */ pllctlv2_set_postdiv(HPM_PLLCTLV2, 1, 0, 0); pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 1, 600000000); clock_update_core_clock(); - /* Configure AHB to 200MHz */ - clock_set_source_divider(clock_ahb, clk_src_pll1_clk1, 2); - /* Configure mchtmr to 24MHz */ clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1); clock_set_source_divider(clock_mchtmr1, clk_src_osc24m, 1); @@ -545,6 +590,7 @@ uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) else { /* Invalid instance */ } + return freq; } uint32_t board_init_adc12_clock(ADC16_Type *ptr) @@ -577,9 +623,46 @@ uint32_t board_init_adc12_clock(ADC16_Type *ptr) return freq; } -uint32_t board_init_adc16_clock(ADC16_Type *ptr) +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) { - return 0; + uint32_t freq = 0; + + if (ptr == HPM_ADC0) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll0_clk0, 2U); + } + + freq = clock_get_frequency(clock_adc0); + } else if (ptr == HPM_ADC1) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc1, clk_adc_src_ana1); + clock_set_source_divider(clock_ana1, clk_src_pll0_clk0, 2U); + } + + freq = clock_get_frequency(clock_adc1); + } else if (ptr == HPM_ADC2) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc2, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc2, clk_adc_src_ana2); + clock_set_source_divider(clock_ana2, clk_src_pll0_clk0, 2U); + } + + freq = clock_get_frequency(clock_adc2); + } + + return freq; } uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb) @@ -588,7 +671,7 @@ uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb) if (ptr == HPM_DAC0) { if (clk_src_ahb == true) { - /* Configure the DAC clock to 133MHz */ + /* Configure the DAC clock to 200MHz */ clock_set_dac_source(clock_dac0, clk_dac_src_ahb0); } else { /* Configure the DAC clock to 166MHz */ @@ -597,6 +680,17 @@ uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb) } freq = clock_get_frequency(clock_dac0); + } else if (ptr == HPM_DAC1) { + if (clk_src_ahb == true) { + /* Configure the DAC clock to 200MHz */ + clock_set_dac_source(clock_dac1, clk_dac_src_ahb0); + } else { + /* Configure the DAC clock to 166MHz */ + clock_set_dac_source(clock_dac1, clk_dac_src_ana4); + clock_set_source_divider(clock_ana4, clk_src_pll0_clk1, 2); + } + + freq = clock_get_frequency(clock_dac1); } return freq; @@ -708,3 +802,24 @@ uint32_t board_init_uart_clock(UART_Type *ptr) } return freq; } + +uint32_t board_init_pwm_clock(PWM_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_PWM0) { + clock_add_to_group(clock_mot0, 0); + freq = clock_get_frequency(clock_mot0); + } else if (ptr == HPM_PWM1) { + clock_add_to_group(clock_mot1, 0); + freq = clock_get_frequency(clock_mot1); + } else if (ptr == HPM_PWM2) { + clock_add_to_group(clock_mot2, 0); + freq = clock_get_frequency(clock_mot2); + } else if (ptr == HPM_PWM3) { + clock_add_to_group(clock_mot3, 0); + freq = clock_get_frequency(clock_mot3); + } else { + + } + return freq; +} diff --git a/bsp/hpmicro/hpm6200evk/board/board.h b/bsp/hpmicro/hpm6200evk/board/board.h index 173be58bcdf..ac74d1ca1d4 100644 --- a/bsp/hpmicro/hpm6200evk/board/board.h +++ b/bsp/hpmicro/hpm6200evk/board/board.h @@ -17,128 +17,156 @@ #include "hpm_debug_console.h" #endif -#define BOARD_NAME "hpm6200evk" +#define BOARD_NAME "hpm6200evk" #define BOARD_UF2_SIGNATURE (0x0A4D5048UL) #define SEC_CORE_IMG_START CORE1_ILM_LOCAL_BASE /* dma section */ -#define BOARD_APP_XDMA HPM_XDMA -#define BOARD_APP_HDMA HPM_HDMA +#define BOARD_APP_XDMA HPM_XDMA +#define BOARD_APP_HDMA HPM_HDMA #define BOARD_APP_XDMA_IRQ IRQn_XDMA #define BOARD_APP_HDMA_IRQ IRQn_HDMA -#define BOARD_APP_DMAMUX HPM_DMAMUX +#define BOARD_APP_DMAMUX HPM_DMAMUX -/* uart section */ #ifndef BOARD_RUNNING_CORE #define BOARD_RUNNING_CORE HPM_CORE0 #endif + +/* uart section */ #ifndef BOARD_APP_UART_BASE -#define BOARD_APP_UART_BASE HPM_UART0 -#define BOARD_APP_UART_IRQ IRQn_UART0 -#else -#ifndef BOARD_APP_UART_IRQ -#warning no IRQ specified for applicaiton uart -#endif +#define BOARD_APP_UART_BASE HPM_UART2 +#define BOARD_APP_UART_IRQ IRQn_UART2 +#define BOARD_APP_UART_BAUDRATE (115200UL) +#define BOARD_APP_UART_CLK_NAME clock_uart2 +#define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART2_RX +#define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART2_TX #endif -#define BOARD_APP_UART_BAUDRATE (115200UL) -#define BOARD_APP_UART_CLK_NAME clock_uart0 -#define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX -#define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX +/* uart lin sample section */ +#define BOARD_UART_LIN BOARD_APP_UART_BASE +#define BOARD_UART_LIN_IRQ BOARD_APP_UART_IRQ +#define BOARD_UART_LIN_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_UART_LIN_TX_PORT GPIO_DI_GPIOC +#define BOARD_UART_LIN_TX_PIN (26U) /* PC26 should align with used pin in pinmux configuration */ + +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE #ifndef BOARD_CONSOLE_TYPE #define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART #endif #if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART -#ifndef BOARD_CONSOLE_BASE +#ifndef BOARD_CONSOLE_UART_BASE #if BOARD_RUNNING_CORE == HPM_CORE0 -#define BOARD_CONSOLE_BASE HPM_UART0 -#define BOARD_CONSOLE_CLK_NAME clock_uart0 +#define BOARD_CONSOLE_UART_BASE HPM_UART0 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART0 +#define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX +#define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX #else -#define BOARD_CONSOLE_BASE HPM_UART2 -#define BOARD_CONSOLE_CLK_NAME clock_uart2 +#define BOARD_CONSOLE_UART_BASE HPM_UART2 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart2 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART2 +#define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART2_TX +#define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART2_RX #endif #endif -#define BOARD_CONSOLE_BAUDRATE (115200UL) +#define BOARD_CONSOLE_UART_BAUDRATE (115200UL) #endif +#endif + +/* uart microros sample section */ +#define BOARD_MICROROS_UART_BASE BOARD_APP_UART_BASE +#define BOARD_MICROROS_UART_IRQ BOARD_APP_UART_IRQ +#define BOARD_MICROROS_UART_CLK_NAME BOARD_APP_UART_CLK_NAME -#define BOARD_FREEMASTER_UART_BASE HPM_UART0 -#define BOARD_FREEMASTER_UART_IRQ IRQn_UART0 -#define BOARD_FREEMASTER_UART_CLK_NAME clock_uart0 +/* rtthread-nano finsh section */ +#define BOARD_RT_CONSOLE_BASE BOARD_CONSOLE_UART_BASE + +/* usb cdc acm uart section */ +#define BOARD_USB_CDC_ACM_UART BOARD_APP_UART_BASE +#define BOARD_USB_CDC_ACM_UART_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_USB_CDC_ACM_UART_TX_DMA_SRC BOARD_APP_UART_TX_DMA_REQ +#define BOARD_USB_CDC_ACM_UART_RX_DMA_SRC BOARD_APP_UART_RX_DMA_REQ + +/* modbus sample section */ +#define BOARD_MODBUS_UART_BASE BOARD_APP_UART_BASE +#define BOARD_MODBUS_UART_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_MODBUS_UART_RX_DMA_REQ BOARD_APP_UART_RX_DMA_REQ +#define BOARD_MODBUS_UART_TX_DMA_REQ BOARD_APP_UART_TX_DMA_REQ /* sdm section */ -#define BOARD_SDM HPM_SDM -#define BOARD_SDM_IRQ IRQn_SDFM -#define BOARD_SDM_CHANNEL 3 -#define BOARD_SDM_TRGM HPM_TRGM3 -#define BOARD_SDM_TRGM_GPTMR HPM_GPTMR3 -#define BOARD_SDM_TRGM_GPTMR_CH 2 -#define BOARD_SDM_TRGM_INPUT_SRC HPM_TRGM3_INPUT_SRC_GPTMR3_OUT2 -#define BOARD_SDM_TRGM_OUTPUT_DST HPM_TRGM3_OUTPUT_SRC_SDFM_TRG15 +#define BOARD_SDM HPM_SDM +#define BOARD_SDM_IRQ IRQn_SDFM +#define BOARD_SDM_CHANNEL 3 +#define BOARD_SDM_TRGM HPM_TRGM3 +#define BOARD_SDM_TRGM_GPTMR HPM_GPTMR3 +#define BOARD_SDM_TRGM_GPTMR_CH 2 +#define BOARD_SDM_TRGM_INPUT_SRC HPM_TRGM3_INPUT_SRC_GPTMR3_OUT2 +#define BOARD_SDM_TRGM_OUTPUT_DST HPM_TRGM3_OUTPUT_SRC_SDFM_TRG15 /* lin section */ -#define BOARD_LIN HPM_LIN0 -#define BOARD_LIN_CLK_NAME clock_lin0 -#define BOARD_LIN_IRQ IRQn_LIN0 -#define BOARD_LIN_BAUDRATE (19200U) +#define BOARD_LIN HPM_LIN0 +#define BOARD_LIN_CLK_NAME clock_lin0 +#define BOARD_LIN_IRQ IRQn_LIN0 +#define BOARD_LIN_BAUDRATE (19200U) /* nor flash section */ #define BOARD_FLASH_BASE_ADDRESS (0x80000000UL) -#define BOARD_FLASH_SIZE (16 * SIZE_1MB) +#define BOARD_FLASH_SIZE (16 * SIZE_1MB) /* i2c section */ -#define BOARD_APP_I2C_BASE HPM_I2C0 -#define BOARD_APP_I2C_IRQ IRQn_I2C0 -#define BOARD_APP_I2C_CLK_NAME clock_i2c0 -#define BOARD_APP_I2C_DMA HPM_HDMA -#define BOARD_APP_I2C_DMAMUX HPM_DMAMUX -#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0 -#define BOARD_APP_I2C_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 +#define BOARD_APP_I2C_BASE HPM_I2C3 +#define BOARD_APP_I2C_IRQ IRQn_I2C3 +#define BOARD_APP_I2C_CLK_NAME clock_i2c3 +#define BOARD_APP_I2C_DMA HPM_HDMA +#define BOARD_APP_I2C_DMAMUX HPM_DMAMUX +#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C3 +#define BOARD_APP_I2C_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 +#define BOARD_I2C_GPIO_CTRL HPM_GPIO0 +#define BOARD_I2C_SCL_GPIO_INDEX GPIO_DO_GPIOB +#define BOARD_I2C_SCL_GPIO_PIN 20 +#define BOARD_I2C_SDA_GPIO_INDEX GPIO_DO_GPIOB +#define BOARD_I2C_SDA_GPIO_PIN 21 /* ACMP desction */ -#define BOARD_ACMP HPM_ACMP -#define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 -#define BOARD_ACMP_IRQ IRQn_ACMP_1 -#define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ +#define BOARD_ACMP HPM_ACMP +#define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 +#define BOARD_ACMP_IRQ IRQn_ACMP_1 +#define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ #define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_5 /* align with used pin */ /* dma section */ -#define BOARD_APP_XDMA HPM_XDMA -#define BOARD_APP_HDMA HPM_HDMA +#define BOARD_APP_XDMA HPM_XDMA +#define BOARD_APP_HDMA HPM_HDMA #define BOARD_APP_XDMA_IRQ IRQn_XDMA #define BOARD_APP_HDMA_IRQ IRQn_HDMA -#define BOARD_APP_DMAMUX HPM_DMAMUX +#define BOARD_APP_DMAMUX HPM_DMAMUX /* gptmr section */ -#define BOARD_GPTMR HPM_GPTMR2 -#define BOARD_GPTMR_IRQ IRQn_GPTMR2 -#define BOARD_GPTMR_CHANNEL 0 -#define BOARD_GPTMR_PWM HPM_GPTMR2 -#define BOARD_GPTMR_PWM_CHANNEL 0 -#define BOARD_GPTMR_CLK_NAME clock_gptmr2 - - -#define BOARD_LED_GPIO_CTRL BOARD_G_GPIO_CTRL -#define BOARD_LED_GPIO_INDEX BOARD_G_GPIO_INDEX -#define BOARD_LED_GPIO_PIN BOARD_G_GPIO_PIN - -#define BOARD_LED_OFF_LEVEL 0 -#define BOARD_LED_ON_LEVEL !BOARD_LED_OFF_LEVEL -#define BOARD_LED_TOGGLE_RGB 1 - -#define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOZ -#define BOARD_APP_GPIO_PIN 2 +#define BOARD_GPTMR HPM_GPTMR1 +#define BOARD_GPTMR_IRQ IRQn_GPTMR1 +#define BOARD_GPTMR_CHANNEL 0 +#define BOARD_GPTMR_DMA_SRC HPM_DMA_SRC_GPTMR1_0 +#define BOARD_GPTMR_CLK_NAME clock_gptmr1 +#define BOARD_GPTMR_PWM HPM_GPTMR1 +#define BOARD_GPTMR_PWM_CHANNEL 0 +#define BOARD_GPTMR_PWM_DMA_SRC HPM_DMA_SRC_GPTMR1_0 +#define BOARD_GPTMR_PWM_CLK_NAME clock_gptmr1 +#define BOARD_GPTMR_PWM_IRQ IRQn_GPTMR1 +#define BOARD_GPTMR_PWM_SYNC HPM_GPTMR1 +#define BOARD_GPTMR_PWM_SYNC_CHANNEL 1 +#define BOARD_GPTMR_PWM_SYNC_CLK_NAME clock_gptmr1 /* pinmux section */ #define USING_GPIO0_FOR_GPIOZ #ifndef USING_GPIO0_FOR_GPIOZ #define BOARD_APP_GPIO_CTRL HPM_BGPIO -#define BOARD_APP_GPIO_IRQ IRQn_BGPIO +#define BOARD_APP_GPIO_IRQ IRQn_BGPIO #else #define BOARD_APP_GPIO_CTRL HPM_GPIO0 -#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_Z +#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_Z #endif /* gpiom section */ @@ -153,54 +181,52 @@ #define BOARD_APP_SPI_SCLK_FREQ (20000000UL) #define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U) #define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U) -#define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI1_RX -#define BOARD_APP_SPI_RX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 -#define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI1_TX -#define BOARD_APP_SPI_TX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX1 -#define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 -#define BOARD_SPI_CS_PIN IOC_PAD_PB02 -#define BOARD_SPI_CS_ACTIVE_LEVEL (0U) +#define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI1_RX +#define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI1_TX +#define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 +#define BOARD_SPI_CS_PIN IOC_PAD_PB02 +#define BOARD_SPI_CS_ACTIVE_LEVEL (0U) /* Flash section */ -#define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) -#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90001U) -#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000005U) -#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) +#define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) +#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90001U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000005U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) /* ADC section */ -#define BOARD_APP_ADC16_NAME "ADC0" -#define BOARD_APP_ADC16_BASE HPM_ADC0 -#define BOARD_APP_ADC16_IRQn IRQn_ADC0 -#define BOARD_APP_ADC16_CH_1 (1U) -#define BOARD_APP_ADC_SEQ_DMA_SIZE_IN_4BYTES (1024U) -#define BOARD_APP_ADC_PMT_DMA_SIZE_IN_4BYTES (192U) -#define BOARD_APP_ADC_PREEMPT_TRIG_LEN (1U) -#define BOARD_APP_ADC_SINGLE_CONV_CNT (6) -#define BOARD_APP_ADC_TRIG_PWMT0 HPM_PWM0 -#define BOARD_APP_ADC_TRIG_PWMT1 HPM_PWM1 -#define BOARD_APP_ADC_TRIG_TRGM0 HPM_TRGM0 -#define BOARD_APP_ADC_TRIG_TRGM1 HPM_TRGM1 -#define BOARD_APP_ADC_TRIG_PWM_SYNC HPM_SYNT +#define BOARD_APP_ADC16_NAME "ADC0" +#define BOARD_APP_ADC16_BASE HPM_ADC0 +#define BOARD_APP_ADC16_IRQn IRQn_ADC0 +#define BOARD_APP_ADC16_CH_1 (8U) +#define BOARD_APP_ADC16_CLK_NAME (clock_adc0) + +#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI +#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A + +#define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A /* DAC section */ -#define BOARD_DAC_BASE HPM_DAC0 -#define BOARD_DAC_IRQn IRQn_DAC0 -#define BOARD_DAC_CLOCK_NAME clock_dac0 +#define BOARD_DAC_BASE HPM_DAC0 +#define BOARD_DAC_IRQn IRQn_DAC0 +#define BOARD_APP_DAC_CLOCK_NAME clock_dac0 /* CAN section */ -#define BOARD_APP_CAN_BASE HPM_MCAN0 -#define BOARD_APP_CAN_IRQn IRQn_CAN0 +#define BOARD_APP_CAN_BASE HPM_MCAN0 +#define BOARD_APP_CAN_IRQn IRQn_MCAN0 /* * timer for board delay */ -#define BOARD_DELAY_TIMER (HPM_GPTMR3) -#define BOARD_DELAY_TIMER_CH 0 +#define BOARD_DELAY_TIMER (HPM_GPTMR3) +#define BOARD_DELAY_TIMER_CH 0 #define BOARD_DELAY_TIMER_CLK_NAME (clock_gptmr3) -#define BOARD_CALLBACK_TIMER (HPM_GPTMR3) -#define BOARD_CALLBACK_TIMER_CH 1 -#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR3 +#define BOARD_CALLBACK_TIMER (HPM_GPTMR3) +#define BOARD_CALLBACK_TIMER_CH 1 +#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR3 #define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr3) /* USB section */ @@ -211,138 +237,254 @@ /*BLDC pwm*/ /*PWM define*/ -#define BOARD_BLDCPWM HPM_PWM0 -#define BOARD_BLDC_UH_PWM_OUTPIN (0U) -#define BOARD_BLDC_UL_PWM_OUTPIN (1U) -#define BOARD_BLDC_VH_PWM_OUTPIN (2U) -#define BOARD_BLDC_VL_PWM_OUTPIN (3U) -#define BOARD_BLDC_WH_PWM_OUTPIN (4U) -#define BOARD_BLDC_WL_PWM_OUTPIN (5U) -#define BOARD_BLDCPWM_TRGM HPM_TRGM0 -#define BOARD_BLDCAPP_PWM_IRQ IRQn_PWM0 -#define BOARD_BLDCPWM_CMP_INDEX_0 (0U) -#define BOARD_BLDCPWM_CMP_INDEX_1 (1U) -#define BOARD_BLDCPWM_CMP_INDEX_2 (2U) -#define BOARD_BLDCPWM_CMP_INDEX_3 (3U) -#define BOARD_BLDCPWM_CMP_INDEX_4 (4U) -#define BOARD_BLDCPWM_CMP_INDEX_5 (5U) -#define BOARD_BLDCPWM_CMP_TRIG_CMP (15U) +#define BOARD_BLDCPWM HPM_PWM0 +#define BOARD_BLDC_UH_PWM_OUTPIN (0U) +#define BOARD_BLDC_UL_PWM_OUTPIN (1U) +#define BOARD_BLDC_VH_PWM_OUTPIN (2U) +#define BOARD_BLDC_VL_PWM_OUTPIN (3U) +#define BOARD_BLDC_WH_PWM_OUTPIN (4U) +#define BOARD_BLDC_WL_PWM_OUTPIN (5U) +#define BOARD_BLDCPWM_TRGM HPM_TRGM0 +#define BOARD_BLDCAPP_PWM_IRQ IRQn_PWM0 +#define BOARD_BLDCPWM_CMP_INDEX_0 (0U) +#define BOARD_BLDCPWM_CMP_INDEX_1 (1U) +#define BOARD_BLDCPWM_CMP_INDEX_2 (2U) +#define BOARD_BLDCPWM_CMP_INDEX_3 (3U) +#define BOARD_BLDCPWM_CMP_INDEX_4 (4U) +#define BOARD_BLDCPWM_CMP_INDEX_5 (5U) +#define BOARD_BLDCPWM_CMP_INDEX_6 (6U) +#define BOARD_BLDCPWM_CMP_INDEX_7 (7U) +#define BOARD_BLDCPWM_CMP_TRIG_CMP (15U) /*HALL define*/ -#define BOARD_BLDC_HALL_BASE HPM_HALL0 -#define BOARD_BLDC_HALL_TRGM HPM_TRGM0 -#define BOARD_BLDC_HALL_IRQ IRQn_HALL0 -#define BOARD_BLDC_HALL_TRGM_HALL_U_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P8 -#define BOARD_BLDC_HALL_TRGM_HALL_V_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P7 -#define BOARD_BLDC_HALL_TRGM_HALL_W_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P6 -#define BOARD_BLDC_HALL_MOTOR_PHASE_COUNT_PER_REV (1000U) - - +#define BOARD_BLDC_HALL_BASE HPM_HALL0 +#define BOARD_BLDC_HALL_TRGM HPM_TRGM0 +#define BOARD_BLDC_HALL_IRQ IRQn_HALL0 +#define BOARD_BLDC_HALL_TRGM_HALL_U_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P8 +#define BOARD_BLDC_HALL_TRGM_HALL_V_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P7 +#define BOARD_BLDC_HALL_TRGM_HALL_W_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P6 +#define BOARD_BLDC_HALL_MOTOR_PHASE_COUNT_PER_REV (1000U) /*QEI*/ -#define BOARD_BLDC_QEI_BASE HPM_QEI0 -#define BOARD_BLDC_QEI_IRQ IRQn_QEI0 -#define BOARD_BLDC_QEI_TRGM HPM_TRGM0 -#define BOARD_BLDC_QEI_TRGM_QEI_A_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P6 -#define BOARD_BLDC_QEI_TRGM_QEI_B_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P7 -#define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV (16U) -#define BOARD_BLDC_QEI_CLOCK_SOURCE clock_mot0 -#define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV (4000U) +#define BOARD_BLDC_QEI_BASE HPM_QEI0 +#define BOARD_BLDC_QEI_IRQ IRQn_QEI0 +#define BOARD_BLDC_QEI_TRGM HPM_TRGM0 +#define BOARD_BLDC_QEI_TRGM_QEI_A_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P6 +#define BOARD_BLDC_QEI_TRGM_QEI_B_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P7 +#define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV (16U) +#define BOARD_BLDC_QEI_CLOCK_SOURCE clock_mot0 +#define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV (4000U) /*Timer define*/ -#define BOARD_BLDC_TMR_1MS HPM_GPTMR2 -#define BOARD_BLDC_TMR_CH 0 -#define BOARD_BLDC_TMR_CMP 0 -#define BOARD_BLDC_TMR_IRQ IRQn_GPTMR2 -#define BOARD_BLDC_TMR_RELOAD (100000U) +#define BOARD_BLDC_TMR_1MS HPM_GPTMR2 +#define BOARD_BLDC_TMR_CH 0 +#define BOARD_BLDC_TMR_CMP 0 +#define BOARD_BLDC_TMR_IRQ IRQn_GPTMR2 +#define BOARD_BLDC_TMR_RELOAD (100000U) /*adc*/ -#define BOARD_BLDC_ADC_MODULE ADCX_MODULE_ADC16 -#define BOARD_BLDC_ADC_U_BASE HPM_ADC0 -#define BOARD_BLDC_ADC_V_BASE HPM_ADC1 -#define BOARD_BLDC_ADC_W_BASE HPM_ADC2 -#define BOARD_BLDC_ADC_TRIG_FLAG adc16_event_trig_complete - -#define BOARD_BLDC_ADC_CH_U (11U) -#define BOARD_BLDC_ADC_CH_V (9U) -#define BOARD_BLDC_ADC_CH_W (4U) -#define BOARD_BLDC_ADC_IRQn IRQn_ADC0 -#define BOARD_BLDC_ADC_SEQ_DMA_SIZE_IN_4BYTES (40U) +#define BOARD_BLDC_ADC_MODULE ADCX_MODULE_ADC16 +#define BOARD_BLDC_ADC_U_BASE HPM_ADC0 +#define BOARD_BLDC_ADC_V_BASE HPM_ADC1 +#define BOARD_BLDC_ADC_W_BASE HPM_ADC2 +#define BOARD_BLDC_ADC_TRIG_FLAG adc16_event_trig_complete + +#define BOARD_BLDC_ADC_CH_U (11U) +#define BOARD_BLDC_ADC_CH_V (9U) +#define BOARD_BLDC_ADC_CH_W (4U) +#define BOARD_BLDC_ADC_IRQn IRQn_ADC0 +#define BOARD_BLDC_ADC_PMT_DMA_SIZE_IN_4BYTES (ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES) #define BOARD_BLDC_ADC_TRG ADC16_CONFIG_TRG0A -#define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) -#define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U) -#define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM0_INPUT_SRC_PWM0_CH8REF -#define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A +#define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) +#define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U) +#define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A /*PLA*/ -#define BOARD_PLA_COUNTER HPM_PLA0 -#define BOARD_PLA_PWM_BASE HPM_PWM0 +#define BOARD_PLA_COUNTER HPM_PLA0 +#define BOARD_PLA_PWM_BASE HPM_PWM0 #define BOARD_PLA_PWM_CLOCK_NAME clock_mot0 -#define BOARD_PLA_TRGM HPM_TRGM0 -#define BOARD_PLA_PWM_TRG (HPM_TRGM0_INPUT_SRC_PWM0_CH8REF) -#define BOARD_PLA_IN_TRG_NUM (TRGM_TRGOCFG_PLA_IN0) -#define BOARD_PLA_OUT_TRG (HPM_TRGM0_INPUT_SRC_PLA0_OUT0) -#define BOARD_PLA_IO_TRG_NUM (TRGM_TRGOCFG_TRGM_OUT5) -#define BOARD_PLA_PWM_CMP (8U) -#define BOARD_PLA_PWM_CHN (8U) +#define BOARD_PLA_TRGM HPM_TRGM0 +#define BOARD_PLA_PWM_TRG (HPM_TRGM0_INPUT_SRC_PWM0_CH8REF) +#define BOARD_PLA_IN_TRG_NUM (TRGM_TRGOCFG_PLA_IN0) +#define BOARD_PLA_OUT_TRG (HPM_TRGM0_INPUT_SRC_PLA0_OUT0) +#define BOARD_PLA_IO_TRG_NUM (TRGM_TRGOCFG_TRGM_OUT5) +#define BOARD_PLA_PWM_CMP (8U) +#define BOARD_PLA_PWM_CHN (8U) /* APP PWM */ -#define BOARD_APP_PWM HPM_PWM0 -#define BOARD_APP_PWM_CLOCK_NAME clock_mot0 -#define BOARD_APP_PWM_OUT1 0 -#define BOARD_APP_PWM_OUT2 1 -#define BOARD_APP_TRGM HPM_TRGM0 -#define BOARD_APP_PWM_IRQ IRQn_PWM0 +#define BOARD_APP_PWM HPM_PWM0 +#define BOARD_APP_PWM_CLOCK_NAME clock_mot0 +#define BOARD_APP_PWM_OUT1 0 +#define BOARD_APP_PWM_OUT2 1 +#define BOARD_APP_TRGM HPM_TRGM0 +#define BOARD_APP_PWM_IRQ IRQn_PWM0 +#define BOARD_APP_TRGM_PWM_OUTPUT TRGM_TRGOCFG_PWM_SYNCI /* APP HRPWM */ -#define BOARD_APP_HRPWM HPM_PWM1 +#define BOARD_APP_HRPWM HPM_PWM1 #define BOARD_APP_HRPWM_CLOCK_NAME clock_mot1 -#define BOARD_APP_HRPWM_OUT1 0 -#define BOARD_APP_HRPWM_OUT2 2 -#define BOARD_APP_HRPWM_TRGM HPM_TRGM1 +#define BOARD_APP_HRPWM_OUT1 0 +#define BOARD_APP_HRPWM_OUT2 2 +#define BOARD_APP_HRPWM_TRGM HPM_TRGM1 #define BOARD_CPU_FREQ (480000000UL) /* LED */ -#define BOARD_R_GPIO_CTRL HPM_GPIO0 +#define BOARD_R_GPIO_CTRL HPM_GPIO0 #define BOARD_R_GPIO_INDEX GPIO_DI_GPIOA -#define BOARD_R_GPIO_PIN 27 -#define BOARD_G_GPIO_CTRL HPM_GPIO0 +#define BOARD_R_GPIO_PIN 27 +#define BOARD_G_GPIO_CTRL HPM_GPIO0 #define BOARD_G_GPIO_INDEX GPIO_DI_GPIOB -#define BOARD_G_GPIO_PIN 1 -#define BOARD_B_GPIO_CTRL HPM_GPIO0 +#define BOARD_G_GPIO_PIN 1 +#define BOARD_B_GPIO_CTRL HPM_GPIO0 #define BOARD_B_GPIO_INDEX GPIO_DI_GPIOB -#define BOARD_B_GPIO_PIN 19 +#define BOARD_B_GPIO_PIN 19 + +#define BOARD_LED_GPIO_CTRL BOARD_G_GPIO_CTRL +#define BOARD_LED_GPIO_INDEX BOARD_G_GPIO_INDEX +#define BOARD_LED_GPIO_PIN BOARD_G_GPIO_PIN + +#define BOARD_LED_OFF_LEVEL 0 +#define BOARD_LED_ON_LEVEL !BOARD_LED_OFF_LEVEL +#define BOARD_LED_TOGGLE_RGB 1 + +/* Key Section */ +#define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOZ +#define BOARD_APP_GPIO_PIN 2 /* RGB LED Section */ -#define BOARD_RED_PWM_IRQ IRQn_PWM3 -#define BOARD_RED_PWM HPM_PWM3 -#define BOARD_RED_PWM_OUT 7 -#define BOARD_RED_PWM_CMP 8 +#define BOARD_RED_PWM_IRQ IRQn_PWM3 +#define BOARD_RED_PWM HPM_PWM3 +#define BOARD_RED_PWM_OUT 7 +#define BOARD_RED_PWM_CMP 8 #define BOARD_RED_PWM_CMP_INITIAL_ZERO true -#define BOARD_RED_PWM_CLOCK_NAME clock_mot3 +#define BOARD_RED_PWM_CLOCK_NAME clock_mot3 -#define BOARD_GREEN_PWM_IRQ IRQn_PWM1 -#define BOARD_GREEN_PWM HPM_PWM1 -#define BOARD_GREEN_PWM_OUT 1 -#define BOARD_GREEN_PWM_CMP 8 +#define BOARD_GREEN_PWM_IRQ IRQn_PWM1 +#define BOARD_GREEN_PWM HPM_PWM1 +#define BOARD_GREEN_PWM_OUT 1 +#define BOARD_GREEN_PWM_CMP 8 #define BOARD_GREEN_PWM_CMP_INITIAL_ZERO true -#define BOARD_GREEN_PWM_CLOCK_NAME clock_mot1 +#define BOARD_GREEN_PWM_CLOCK_NAME clock_mot1 -#define BOARD_BLUE_PWM_IRQ IRQn_PWM0 -#define BOARD_BLUE_PWM HPM_PWM0 -#define BOARD_BLUE_PWM_OUT 7 -#define BOARD_BLUE_PWM_CMP 8 +#define BOARD_BLUE_PWM_IRQ IRQn_PWM0 +#define BOARD_BLUE_PWM HPM_PWM0 +#define BOARD_BLUE_PWM_OUT 7 +#define BOARD_BLUE_PWM_CMP 8 #define BOARD_BLUE_PWM_CMP_INITIAL_ZERO true -#define BOARD_BLUE_PWM_CLOCK_NAME clock_mot0 +#define BOARD_BLUE_PWM_CLOCK_NAME clock_mot0 -#define BOARD_RGB_RED 0 +#define BOARD_RGB_RED 0 #define BOARD_RGB_GREEN (BOARD_RGB_RED + 1) #define BOARD_RGB_BLUE (BOARD_RGB_RED + 2) +/* PLA TAMAGAWA*/ + +#define PLA_TMGW_SPI HPM_SPI2 +#define PLA_TMGW_SPI_DMA BOARD_APP_HDMA +#define PLA_TMGW_SPI_DMAMUX BOARD_APP_DMAMUX +#define PLA_TMGW_SPI_RX_DMA_REQ HPM_DMA_SRC_SPI2_RX +#define PLA_TMGW_SPI_TX_DMA_REQ HPM_DMA_SRC_SPI2_TX +#define PLA_TMGW_SPI_RX_DMA_CH 0 +#define PLA_TMGW_SPI_TX_DMA_CH 1 +#define PLA_TMGW_SPI_RX_DMAMUX_CH DMA_SOC_CHN_TO_DMAMUX_CHN(PLA_TMGW_SPI_DMA, PLA_TMGW_SPI_RX_DMA_CH) +#define PLA_TMGW_SPI_TX_DMAMUX_CH DMA_SOC_CHN_TO_DMAMUX_CHN(PLA_TMGW_SPI_DMA, PLA_TMGW_SPI_TX_DMA_CH) + +#define PLA_TMGW_SPI_CS_GPIO_CTRL HPM_GPIO0 +#define PLA_TMGW_SPI_CS_GPIO_INDEX GPIO_DI_GPIOB +#define PLA_TMGW_SPI_CS_GPIO_PIN 30 + +#define PLA_TMGW_DATA_DIR_GPIO_CTRL HPM_GPIO0 +#define PLA_TMGW_DATA_DIR_GPIO_INDEX GPIO_DI_GPIOB +#define PLA_TMGW_DATA_DIR_GPIO_PIN 21 + +#define PLA_TMGW_POWER_GPIO_CTRL HPM_GPIO0 +#define PLA_TMGW_POWER_GPIO_INDEX GPIO_DI_GPIOB +#define PLA_TMGW_POWER_GPIO_PIN 31 + +#define PLA_TMGW_SPI_485_DIR_TRG (HPM_TRGM0_INPUT_SRC_PLA0_OUT1) +#define PLA_TMGW_SPI_485_DIR_TRGNUM (TRGM_TRGOCFG_TRGM_OUT1) +#define PLA_TMGW_SPI_MOSI_DATA_TRG (HPM_TRGM0_INPUT_SRC_TRGM0_P3) +#define PLA_TMGW_SPI_MOSI_DATA_TRGNUM (TRGM_TRGOCFG_PLA_IN3) + +#define PLA_TMGW_SPI_CS_TRG (TEST_MOTOR_PWM_TRG_PLA_TRG) +#define PLA_TMGW_SPI_CS_TRGNUM (TRGM_TRGOCFG_TRGM_OUT0) + +#define PLA_TMGW_COUNTER HPM_PLA0 +#define PLA_TMGW_PWM_BASE HPM_PWM3 +#define PLA_TMGW_PWM_CLOCK_NAME clock_mot3 +#define PLA_TMGW_TRGM_CLK_IN_TRG (HPM_TRGM0_INPUT_SRC_TRGM3_OUTX0) +#define PLA_TMGW_TRGM_CLK_To_PLA_TRGNUM (TRGM_TRGOCFG_PLA_IN0) +#define PLA_TMGW_TRGM (HPM_TRGM0) +#define PLA_TMGW_CLK_TRGM (HPM_TRGM3) +#define PLA_TMGW_CLK_PWM_TRG (HPM_TRGM3_INPUT_SRC_PWM3_CH15REF) +#define PLA_TMGW_CLK_TRG_NUM (TRGM_TRGOCFG_TRGM_OUTX0) +#define PLA_TMGW_OUT_TRG (HPM_TRGM0_INPUT_SRC_PLA0_OUT0) +#define PLA_TMGW_IO_TRG_NUM (TRGM_TRGOCFG_TRGM_OUT5) +#define PLA_TMGW_PWM_CMP (15U) +#define PLA_TMGW_PWM_CHN (15U) +#define PLA_TMGW_PWM_SYNCI_TRG (HPM_TRGM0_INPUT_SRC_PLA0_OUT2) +#define PLA_TMGW_PWM_SYNCI_TRGNUM (TRGM_TRGOCFG_TRGM_OUTX0) +#define PLA_TMGW_PWM_SYNCI_IN_TRG (HPM_TRGM3_INPUT_SRC_TRGM0_OUTX0) +#define PLA_TMGW_PWM_SYNCI_IN_TRGNUM (TRGM_TRGOCFG_PWM_SYNCI) + +#define PLA_TMGW_HALL_TIME_TRG (HPM_TRGM0_INPUT_SRC_PLA0_OUT2) + +#define PLA_TMGW_IN_MOTOR_TRG_NUM (TRGM_TRGOCFG_PLA_IN2) + +#define PLA_TMGW_QEI_BASE HPM_QEI0 +#define PLA_TMGW_QEI_TRGM HPM_TRGM0 +#define PLA_TMGW_QEI_TRGM_QEI_A_SRC HPM_TRGM0_INPUT_SRC_PLA0_OUT0 +#define PLA_TMGW_QEI_IRQ IRQn_QEI0 +#define PLA_TMGW_QEI_MOTOR_PHASE_COUNT_MAX (0xffffff) + +#define PLA_TMGW_QEI_TRGM_QEI_TRG0 HPM_TRGM0_INPUT_SRC_QEI0_TRGO +#define PLA_TMGW_QEI_TRGM_QEI_PLA_IN TRGM_TRGOCFG_PLA_IN1 + +#define PLA_TMGW_QEI_DMA BOARD_APP_HDMA +#define PLA_TMGW_QEI_DMAMUX BOARD_APP_DMAMUX +#define PLA_TMGW_QEI_DMAREQ HPM_DMA_SRC_MOT0_0 +#define PLA_TMGW_QEI_DMACH (2UL) +#define PLA_TMGW_QEI_DMAMUX_CH DMA_SOC_CHN_TO_DMAMUX_CHN(PLA_TMGW_QEI_DMA, PLA_TMGW_QEI_DMACH) + +#define PLA_TMGW_HALL_BASE HPM_HALL0 +#define PLA_TMGW_HALL_TRGM HPM_TRGM0 +#define PLA_TMGW_HALL_DMA BOARD_APP_HDMA +#define PLA_TMGW_HALL_DMAMUX BOARD_APP_DMAMUX +#define PLA_TMGW_HALL_DMA_CH (3U) +#define PLA_TMGW_HALL_DMAMUX_CH DMA_SOC_CHN_TO_DMAMUX_CHN(PLA_TMGW_HALL_DMA, PLA_TMGW_HALL_DMA_CH) +#define PLA_TMGW_HALL_TRAN_SIZE (4U) /* four world */ +#define PLA_TMGW_HALL_DMA_REQ HPM_DMA_SRC_MOT0_1 + +#define PLA_TMGW_DMA_LINK_NUM (25U) +#define PLA_TMGW_DMA_LINK_TRGM HPM_TRGM0 +#define PLA_TMGW_DMA_LINK_DMA BOARD_APP_HDMA +#define PLA_TMGW_DMA_LINK_DMAMUX BOARD_APP_DMAMUX +#define PLA_TMGW_DMA_LINK_DMA_CH (4U) +#define PLA_TMGW_DMA_LINK_DMAMUX_CH DMA_SOC_CHN_TO_DMAMUX_CHN(PLA_TMGW_DMA_LINK_DMA, PLA_TMGW_DMA_LINK_DMA_CH) +#define PLA_TMGW_DMA_LINK_TRAN_SIZE (4U) +#define PLA_TMGW_DMA_LINK_DMA_REQ HPM_DMA_SRC_MOT0_2 +#define PLA_TMGW_DMA_LINK_TRGM_INPUT HPM_TRGM0_INPUT_SRC_PLA0_OUT6 + +/** + * @brief Get adc phase current + * + */ +#define BOARD_BLDC_ADC_PHASE_CH_U (3U) +#define BOARD_BLDC_ADC_PHASE_CH_V (4U) +#define BOARD_BLDC_ADC_PHASE_CH_W (2U) +#define BOARD_BLDC_ADC_PHASE_U_BASE HPM_ADC0 +#define BOARD_BLDC_ADC_PHASE_V_BASE HPM_ADC0 +#define BOARD_BLDC_ADC_PHASE_W_BASE HPM_ADC0 +#define BOARD_BLDC_ADC_PHASE_TRG ADC16_CONFIG_TRG0A +#define BOARD_BLDC_ADC_PHASE_PREEMPT_TRIG_LEN (3) +#define BOARD_BLDC_ADC_PHASE_IRQn IRQn_ADC0 +#define BOARD_BLDC_ADC_PHASE_TRIG_FLAG adc16_event_trig_complete + #ifndef BOARD_SHOW_CLOCK #define BOARD_SHOW_CLOCK 1 #endif @@ -350,6 +492,21 @@ #define BOARD_SHOW_BANNER 1 #endif +/* FreeRTOS Definitions */ +#define BOARD_FREERTOS_TIMER HPM_GPTMR1 +#define BOARD_FREERTOS_TIMER_CHANNEL 1 +#define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR1 +#define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr1 + +/* Threadx Definitions */ +#define BOARD_THREADX_TIMER HPM_GPTMR1 +#define BOARD_THREADX_TIMER_CHANNEL 1 +#define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR1 +#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr1 +/* Tamper Section */ +#define BOARD_TAMP_ACTIVE_CH 4 +#define BOARD_TAMP_LOW_LEVEL_CH 6 + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ @@ -359,6 +516,8 @@ typedef void (*board_timer_cb)(void); void board_init(void); void board_init_console(void); +void board_init_core1(void); + void board_init_uart(UART_Type *ptr); void board_init_i2c(I2C_Type *ptr); @@ -385,9 +544,10 @@ uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); uint32_t board_init_spi_clock(SPI_Type *ptr); +void board_init_lin_pins(LIN_Type *ptr); uint32_t board_init_lin_clock(LIN_Type *ptr); -uint32_t board_init_adc16_clock(ADC16_Type *ptr); +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb); uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb); @@ -401,7 +561,6 @@ void board_init_usb_pins(void); void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); uint8_t board_get_usb_id_status(void); - /* * @brief Initialize PMP and PMA for but not limited to the following purposes: * -- non-cacheable memory initialization @@ -417,6 +576,8 @@ void board_ungate_mchtmr_at_lp_mode(void); /* Initialize the UART clock */ uint32_t board_init_uart_clock(UART_Type *ptr); +uint32_t board_init_pwm_clock(PWM_Type *ptr); + #if defined(__cplusplus) } #endif /* __cplusplus */ diff --git a/bsp/hpmicro/hpm6200evk/board/linker_scripts/flash_rtt.ld b/bsp/hpmicro/hpm6200evk/board/linker_scripts/flash_rtt.ld index 2ab3b52bac0..2689df6217b 100644 --- a/bsp/hpmicro/hpm6200evk/board/linker_scripts/flash_rtt.ld +++ b/bsp/hpmicro/hpm6200evk/board/linker_scripts/flash_rtt.ld @@ -135,6 +135,12 @@ SECTIONS /* RT-Thread related sections - end */ + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + } > XPI0 .rel : { diff --git a/bsp/hpmicro/hpm6200evk/board/linker_scripts/ram_rtt.ld b/bsp/hpmicro/hpm6200evk/board/linker_scripts/ram_rtt.ld index 07055ad4622..67adc0489b7 100644 --- a/bsp/hpmicro/hpm6200evk/board/linker_scripts/ram_rtt.ld +++ b/bsp/hpmicro/hpm6200evk/board/linker_scripts/ram_rtt.ld @@ -85,6 +85,12 @@ SECTIONS /* RT-Thread related sections - end */ + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); diff --git a/bsp/hpmicro/hpm6200evk/board/pinmux.c b/bsp/hpmicro/hpm6200evk/board/pinmux.c index 3a6337faec0..13e02932d82 100644 --- a/bsp/hpmicro/hpm6200evk/board/pinmux.c +++ b/bsp/hpmicro/hpm6200evk/board/pinmux.c @@ -20,8 +20,8 @@ void init_uart_pins(UART_Type *ptr) HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART0_RXD; HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART0_TXD; /* PY port IO needs to configure PIOC */ - HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_SOC_GPIO_Y_07; - HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_SOC_GPIO_Y_06; + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = PIOC_PY07_FUNC_CTL_SOC_GPIO_Y_07; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = PIOC_PY06_FUNC_CTL_SOC_GPIO_Y_06; } else if (ptr == HPM_UART1) { HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_UART1_TXD; HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_UART1_RXD; @@ -29,11 +29,22 @@ void init_uart_pins(UART_Type *ptr) HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_UART2_TXD; HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_UART2_RXD; } else if (ptr == HPM_PUART) { - HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART_RXD; - HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART_TXD; - } else if (ptr == HPM_UART6) { - HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_UART6_RXD; - HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_UART6_TXD; + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = PIOC_PY07_FUNC_CTL_UART_RXD; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = PIOC_PY06_FUNC_CTL_UART_TXD; + } +} + +/* for uart_lin case, need to configure pin as gpio to sent break signal */ +void init_uart_pin_as_gpio(UART_Type *ptr) +{ + /* pull-up */ + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + + if (ptr == HPM_UART2) { + HPM_IOC->PAD[IOC_PAD_PC26].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PC27].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_GPIO_C_26; + HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_GPIO_C_27; } } @@ -43,6 +54,10 @@ void init_i2c_pins_as_gpio(I2C_Type *ptr) /* I2C0 */ HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_GPIO_B_22; HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PB23_FUNC_CTL_GPIO_B_23; + } else if (ptr == HPM_I2C3) { + /* I2C3 */ + HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_GPIO_B_20; + HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_GPIO_B_21; } else { while (1) { } @@ -59,12 +74,12 @@ void init_i2c_pins(I2C_Type *ptr) HPM_IOC->PAD[IOC_PAD_PB22].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); HPM_IOC->PAD[IOC_PAD_PB23].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); } else if (ptr == HPM_I2C3) { - HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_I2C3_SCL + HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_I2C3_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; - HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_I2C3_SDA + HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_I2C3_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; - HPM_IOC->PAD[IOC_PAD_PC11].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); - HPM_IOC->PAD[IOC_PAD_PC12].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PB20].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PB21].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); } else { while (1) { } @@ -89,7 +104,7 @@ void init_gpio_pins(void) HPM_IOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_GPIO_Z_02; HPM_IOC->PAD[IOC_PAD_PZ02].PAD_CTL = pad_ctl; /* PZ port IO needs to configure BIOC as well */ - HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_SOC_GPIO_Z_02; + HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = BIOC_PZ02_FUNC_CTL_SOC_GPIO_Z_02; #endif } @@ -125,14 +140,17 @@ void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) void init_pins(void) { - init_uart_pins(BOARD_CONSOLE_BASE); +#ifdef BOARD_CONSOLE_UART_BASE + init_uart_pins(BOARD_CONSOLE_UART_BASE); +#endif } void init_gptmr_pins(GPTMR_Type *ptr) { - if (ptr == HPM_GPTMR2) { - HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_GPTMR2_CAPT_0; - HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_GPTMR2_COMP_0; + if (ptr == HPM_GPTMR1) { + HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_GPTMR1_CAPT_0; + HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_GPTMR1_COMP_0; + HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_GPTMR1_COMP_1; } } @@ -185,10 +203,8 @@ void init_hrpwm_pins(PWM_Type *ptr) void init_adc_pins(void) { - HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_BUS:ADC0.INA1 */ - HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IW: ADC0.INA12/ADC1.INA8/ADC2.INA4 */ - HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IV: ADC0.INA13/ADC1.INA9/ADC2.INA5 */ - HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IU: ADC0.INA11/ADC1.INA7.ADC2.INA3 */ + /* ADC0.INA8 */ + HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; } void init_adc_bldc_pins(void) @@ -207,26 +223,13 @@ void init_usb_pins(void) void init_can_pins(MCAN_Type *ptr) { if (ptr == HPM_MCAN0) { - HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_CAN0_STBY | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; - HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_CAN0_TXD | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; - HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_CAN0_RXD | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_MCAN0_STBY | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_MCAN0_TXD | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_MCAN0_RXD | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; - HPM_IOC->PAD[IOC_PAD_PB19].PAD_CTL = 0x10; - HPM_IOC->PAD[IOC_PAD_PB20].PAD_CTL = 0x810; - HPM_IOC->PAD[IOC_PAD_PB21].PAD_CTL = 0x810; - } - if (ptr == HPM_MCAN3) { - HPM_IOC->PAD[IOC_PAD_PZ05].FUNC_CTL = IOC_PZ05_FUNC_CTL_CAN3_RXD | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; - HPM_IOC->PAD[IOC_PAD_PZ04].FUNC_CTL = IOC_PZ04_FUNC_CTL_CAN3_TXD | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; - HPM_IOC->PAD[IOC_PAD_PZ03].FUNC_CTL = IOC_PZ03_FUNC_CTL_CAN3_STBY | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; - - HPM_IOC->PAD[IOC_PAD_PZ03].PAD_CTL = 0x10; - HPM_IOC->PAD[IOC_PAD_PZ04].PAD_CTL = 0x810; - HPM_IOC->PAD[IOC_PAD_PZ05].PAD_CTL = 0x810; - /* PZ port IO needs to configure BIOC as well */ - HPM_BIOC->PAD[IOC_PAD_PZ03].FUNC_CTL = IOC_PZ03_FUNC_CTL_SOC_GPIO_Z_03; - HPM_BIOC->PAD[IOC_PAD_PZ04].FUNC_CTL = IOC_PZ04_FUNC_CTL_SOC_GPIO_Z_04; - HPM_BIOC->PAD[IOC_PAD_PZ05].FUNC_CTL = IOC_PZ05_FUNC_CTL_SOC_GPIO_Z_05; + HPM_IOC->PAD[IOC_PAD_PB19].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); + HPM_IOC->PAD[IOC_PAD_PB20].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); + HPM_IOC->PAD[IOC_PAD_PB21].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); } } @@ -262,6 +265,19 @@ void init_pla_pins(void) HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PB25_FUNC_CTL_TRGM0_P_05; } +void init_pla_tamagawa_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PB30_FUNC_CTL_GPIO_B_30; + HPM_IOC->PAD[IOC_PAD_PB31].FUNC_CTL = IOC_PB31_FUNC_CTL_GPIO_B_31; + HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_TRGM0_P_01; + HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_TRGM0_P_02; + HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PB23_FUNC_CTL_TRGM0_P_03; + HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PC22_FUNC_CTL_SPI2_CSN; + HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_SPI2_MOSI; + HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_SPI2_MISO; + HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_SPI2_SCLK; +} + void init_lin_pins(LIN_Type *ptr) { /** enable open drain and pull up */ @@ -282,6 +298,13 @@ void init_lin_pins(LIN_Type *ptr) } } +void init_motor_over_zero_sensorless_adc_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + void init_led_pins_as_pwm(void) { /* Blue */ @@ -291,3 +314,13 @@ void init_led_pins_as_pwm(void) /* Red */ HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_PWM3_P_07; } + +void init_tamper_pins(void) +{ + HPM_BIOC->PAD[IOC_PAD_PZ04].FUNC_CTL = BIOC_PZ04_FUNC_CTL_BATT_TAMPER_04 | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_BIOC->PAD[IOC_PAD_PZ05].FUNC_CTL = BIOC_PZ05_FUNC_CTL_BATT_TAMPER_05; + HPM_BIOC->PAD[IOC_PAD_PZ06].FUNC_CTL = BIOC_PZ06_FUNC_CTL_BATT_TAMPER_06; + + HPM_BIOC->PAD[IOC_PAD_PZ04].PAD_CTL &= ~IOC_PAD_PAD_CTL_OD_MASK; + HPM_BIOC->PAD[IOC_PAD_PZ05].PAD_CTL &= ~IOC_PAD_PAD_CTL_OD_MASK; +} diff --git a/bsp/hpmicro/hpm6200evk/board/pinmux.h b/bsp/hpmicro/hpm6200evk/board/pinmux.h index bd75fed4274..12686d8d7e2 100644 --- a/bsp/hpmicro/hpm6200evk/board/pinmux.h +++ b/bsp/hpmicro/hpm6200evk/board/pinmux.h @@ -12,6 +12,7 @@ extern "C" { #endif void init_uart_pins(UART_Type *ptr); +void init_uart_pin_as_gpio(UART_Type *ptr); void init_i2c_pins(I2C_Type *ptr); void init_gpio_pins(void); void init_spi_pins(SPI_Type *ptr); @@ -37,6 +38,10 @@ void init_trgmux_pins(uint32_t pin); void init_pla_pins(void); void init_lin_pins(LIN_Type *ptr); void init_sdm_pins(void); +void init_pla_tamagawa_pins(void); +void init_motor_over_zero_sensorless_adc_pins(void); +void init_tamper_pins(void); + #ifdef __cplusplus } #endif diff --git a/bsp/hpmicro/hpm6200evk/board/rtt_board.c b/bsp/hpmicro/hpm6200evk/board/rtt_board.c index d4d344287a7..3d7a94356e7 100644 --- a/bsp/hpmicro/hpm6200evk/board/rtt_board.c +++ b/bsp/hpmicro/hpm6200evk/board/rtt_board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * SPDX-License-Identifier: BSD-3-Clause * */ @@ -8,18 +8,34 @@ #include "rtt_board.h" #include "hpm_uart_drv.h" #include "hpm_gpio_drv.h" -#include "hpm_mchtmr_drv.h" #include "hpm_pmp_drv.h" #include "assert.h" #include "hpm_clock_drv.h" #include "hpm_sysctl_drv.h" #include #include -#include "hpm_dma_manager.h" +#include "hpm_dma_mgr.h" +#include "hpm_mchtmr_drv.h" +extern int rt_hw_uart_init(void); void os_tick_config(void); +void rtt_board_init(void); -extern int rt_hw_uart_init(void); +void rt_hw_board_init(void) +{ + rtt_board_init(); + + /* Call the RT-Thread Component Board Initialization */ + rt_components_board_init(); +} + +void os_tick_config(void) +{ + sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1); + sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0); + mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND); + enable_mchtmr_irq(); +} void rtt_board_init(void) { @@ -27,7 +43,7 @@ void rtt_board_init(void) board_init_console(); board_init_pmp(); - dma_manager_init(); + dma_mgr_init(); /* initialize memory system */ rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); @@ -67,24 +83,6 @@ void BOARD_LED_write(uint32_t index, bool state) } } -void os_tick_config(void) -{ - sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1); - sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0); - - mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND); - - enable_mchtmr_irq(); -} - -void rt_hw_board_init(void) -{ - rtt_board_init(); - - /* Call the RT-Thread Component Board Initialization */ - rt_components_board_init(); -} - void rt_hw_console_output(const char *str) { while (*str != '\0') @@ -93,18 +91,16 @@ void rt_hw_console_output(const char *str) } } +void app_init_usb_pins(void) +{ + board_init_usb_pins(); +} + ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) { HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND; - rt_interrupt_enter(); rt_tick_increase(); - rt_interrupt_leave(); -} - -void rt_hw_us_delay(rt_uint32_t us) -{ - clock_cpu_delay_us(us); } void rt_hw_cpu_reset(void) diff --git a/bsp/hpmicro/hpm6200evk/board/rtt_board.h b/bsp/hpmicro/hpm6200evk/board/rtt_board.h index f0dc3974cee..e21cb87f520 100644 --- a/bsp/hpmicro/hpm6200evk/board/rtt_board.h +++ b/bsp/hpmicro/hpm6200evk/board/rtt_board.h @@ -23,6 +23,17 @@ /* CAN section */ #define BOARD_CAN_NAME "can0" +#define BOARD_CAN_HWFILTER_INDEX (0U) + +/* UART section */ +#define BOARD_UART_NAME "uart2" +#define BOARD_UART_RX_BUFFER_SIZE BSP_UART2_RX_BUFSIZE + +/* PWM section */ +#define BOARD_PWM_NAME "pwm0" +#define BOARD_PWM_CHANNEL (0) + +#define IRQn_PendSV IRQn_DEBUG_0 /*************************************************************** * @@ -44,7 +55,7 @@ typedef struct { void app_init_led_pins(void); void app_led_write(uint32_t index, bool state); - +void app_init_usb_pins(void); #if defined(__cplusplus) extern "C" { diff --git a/bsp/hpmicro/hpm6200evk/rtconfig.py b/bsp/hpmicro/hpm6200evk/rtconfig.py index 098ea53e716..5b91dfe7b37 100644 --- a/bsp/hpmicro/hpm6200evk/rtconfig.py +++ b/bsp/hpmicro/hpm6200evk/rtconfig.py @@ -81,8 +81,8 @@ LFLAGS += ' -O0' LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' elif BUILD == 'ram_release': - CFLAGS += ' -O2 -Os' - LFLAGS += ' -O2 -Os' + CFLAGS += ' -O2' + LFLAGS += ' -O2' LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' elif BUILD == 'flash_debug': CFLAGS += ' -gdwarf-2' @@ -92,13 +92,13 @@ CFLAGS += ' -DFLASH_XIP=1' LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' elif BUILD == 'flash_release': - CFLAGS += ' -O2 -Os' - LFLAGS += ' -O2 -Os' + CFLAGS += ' -O2' + LFLAGS += ' -O2' CFLAGS += ' -DFLASH_XIP=1' LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' else: - CFLAGS += ' -O2 -Os' - LFLAGS += ' -O2 -Os' + CFLAGS += ' -O2' + LFLAGS += ' -O2' LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' LFLAGS += ' -T ' + LINKER_FILE diff --git a/bsp/hpmicro/hpm6300evk/README.md b/bsp/hpmicro/hpm6300evk/README.md index e7825a96ca4..75dea3f4af8 100644 --- a/bsp/hpmicro/hpm6300evk/README.md +++ b/bsp/hpmicro/hpm6300evk/README.md @@ -51,7 +51,7 @@ The BSP support being build via the 'scons' command, below is the steps of compi - Download the package and extract it into a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain` - Step 3: Set environment variable `RTT_RISCV_TOOLCHAIN` to `\bin` - For example: `C:\DevTools\riscv32-gnu-toolchain\bin` -- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip) +- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip) - Download and extract it to specified directory, for example: `C:\DevTools\openocd-hpmicro` - Add `OpenOCD` environment variable `OPENOCD_HPMICRO` to `\bin` - For example: `C:\DevTools\openocd-hpmicro\bin` diff --git a/bsp/hpmicro/hpm6300evk/README_zh.md b/bsp/hpmicro/hpm6300evk/README_zh.md index 04083bd12f4..884e84a9486 100644 --- a/bsp/hpmicro/hpm6300evk/README_zh.md +++ b/bsp/hpmicro/hpm6300evk/README_zh.md @@ -53,7 +53,7 @@ - 步骤 2: 准备 [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) - 下载并解压到指定的目录，如: `C:\DevTools\riscv32-gnu-toolchain` - 步骤 3: 设置环境变量： `RTT_RISCV_TOOLCHAIN` 为 `\bin`， 如: `C:\DevTools\riscv32-gnu-toolchain\bin` -- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip) +- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip) - 下载并解压到指定目录，如: `C:\DevTools\openocd-hpmicro` - 将 `OPENOCD_HPMICRO`环境变量设置为 `\bin`，如： `C:\DevTools\openocd-hpmicro\bin` diff --git a/bsp/hpmicro/hpm6300evk/board/Kconfig b/bsp/hpmicro/hpm6300evk/board/Kconfig index 210f94058f7..526c2b01e83 100644 --- a/bsp/hpmicro/hpm6300evk/board/Kconfig +++ b/bsp/hpmicro/hpm6300evk/board/Kconfig @@ -7,6 +7,10 @@ config SOC_HPM6000 select RT_USING_USER_MAIN default y +config BSP_USING_ENET_PHY_RTL8201 + bool + default n + menu "On-chip Peripheral Drivers" config BSP_USING_GPIO bool "Enable GPIO" @@ -27,68 +31,38 @@ menu "On-chip Peripheral Drivers" bool "Enable UART0 RX DMA" depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA default n - config BSP_UART0_TX_USING_DMA bool "Enable UART0 TX DMA" depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA default n - - config BSP_UART0_RX_DMA_CHANNEL - int "Set UART0 RX DMA CHANNEL" - range 0 7 - depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA - default 0 - - config BSP_UART0_TX_DMA_CHANNEL - int "Set UART0 TX DMA CHANNEL" - range 0 7 - depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA - default 1 - config BSP_UART0_RX_BUFSIZE int "Set UART0 RX buffer size" range 64 65535 depends on RT_USING_SERIAL_V2 default 128 - config BSP_UART0_TX_BUFSIZE int "Set UART0 TX buffer size" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 endif - menuconfig BSP_USING_UART2 + menuconfig BSP_USING_UART2 bool "Enable UART2" - default n + default y if BSP_USING_UART2 config BSP_UART2_RX_USING_DMA bool "Enable UART2 RX DMA" depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA default n - config BSP_UART2_TX_USING_DMA bool "Enable UART2 TX DMA" - depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA - default n - - config BSP_UART2_RX_DMA_CHANNEL - int "Set UART2 RX DMA CHANNEL" - range 0 7 depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA - default 0 - - config BSP_UART2_TX_DMA_CHANNEL - int "Set UART2 TX DMA CHANNEL" - range 0 7 - depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA - default 1 - + default n config BSP_UART2_RX_BUFSIZE int "Set UART2 RX buffer size" range 64 65535 depends on RT_USING_SERIAL_V2 default 128 - config BSP_UART2_TX_BUFSIZE int "Set UART2 TX buffer size" range 0 65535 @@ -106,13 +80,28 @@ menu "On-chip Peripheral Drivers" if BSP_USING_SPI config BSP_USING_SPI1 bool "Enable SPI1" + default y + if BSP_USING_SPI1 + config BSP_SPI1_USING_DMA + bool "Enable SPI1 DMA" default n + endif config BSP_USING_SPI2 bool "Enable SPI2" + default n + if BSP_USING_SPI2 + config BSP_SPI2_USING_DMA + bool "Enable SPI2 DMA" default n + endif config BSP_USING_SPI3 bool "Enable SPI3" + default n + if BSP_USING_SPI3 + config BSP_SPI3_USING_DMA + bool "Enable SPI3 DMA" default n + endif endif menuconfig BSP_USING_RTC @@ -122,14 +111,14 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_ETH bool "Enable Ethernet" default n - select RT_USING_ETH if BSP_USING_ETH - choice - prompt "ETH" - config BSP_USING_ETH0 - bool "Enable ETH0" - endchoice + choice + prompt "ETH" + config BSP_USING_ETH0 + bool "Enable ETH0" + select BSP_USING_ENET_PHY_RTL8201 + endchoice endif menuconfig BSP_USING_SDXC @@ -139,101 +128,130 @@ menu "On-chip Peripheral Drivers" if BSP_USING_SDXC config BSP_USING_SDXC0 bool "Enable SDXC0" - default n + default n + if BSP_USING_SDXC0 + choice + prompt "Select BUS_WIDTH" + default BSP_SDXC0_BUS_WIDTH_4BIT + config BSP_SDXC0_BUS_WIDTH_1BIT + bool "1-bit" + config BSP_SDXC0_BUS_WIDTH_4BIT + bool "4-bit" + endchoice + choice + prompt "Select Voltage" + default BSP_SDXC0_VOLTAGE_3V3 + config BSP_SDXC0_VOLTAGE_3V3 + bool "3.3V" + endchoice + config BSP_SDXC0_PWR_PIN + default "None" + string "PWR pin name" + endif endif menuconfig BSP_USING_GPTMR - bool "Enable GPTMR" - default n - select RT_USING_HWTIMER if BSP_USING_GPTMR - if BSP_USING_GPTMR - config BSP_USING_GPTMR0 - bool "Enable GPTMR0" - default n - config BSP_USING_GPTMR1 - bool "Enable GPTMR1" - default n - config BSP_USING_GPTMR2 - bool "Enable GPTMR2" - default n - config BSP_USING_GPTMR3 - bool "Enable GPTMR3" - default n + bool "Enable GPTMR" + default n + select RT_USING_HWTIMER if BSP_USING_GPTMR + if BSP_USING_GPTMR + config BSP_USING_GPTMR1 + bool "Enable GPTMR1" + default n + config BSP_USING_GPTMR2 + bool "Enable GPTMR2" + default n + config BSP_USING_GPTMR3 + bool "Enable GPTMR3" + default n endif + menuconfig BSP_USING_I2C bool "Enable I2C" default n if BSP_USING_I2C config BSP_USING_I2C0 bool "Enable I2C0" - default y + default y + if BSP_USING_I2C0 + config BSP_I2C0_USING_DMA + bool "Enable I2C0 DMA" + default n + endif config BSP_USING_I2C3 bool "Enable I2C3" + default n + if BSP_USING_I2C3 + config BSP_I2C3_USING_DMA + bool "Enable I2C3 DMA" default n + endif endif menuconfig BSP_USING_FEMC bool "Enable DRAM" default y + menuconfig INIT_EXT_RAM_FOR_DATA bool "INIT_EXT_RAM_FOR_DATA" default y menuconfig BSP_USING_XPI_FLASH - bool "Enable XPI FLASH" - default n - select PKG_USING_FAL if BSP_USING_XPI_FLASH + bool "Enable XPI FLASH" + default n + select RT_USING_FAL if BSP_USING_XPI_FLASH menuconfig BSP_USING_PWM bool "Enable PWM" - default n + default n menuconfig BSP_USING_USB bool "Enable USB" default n if BSP_USING_USB - config BSP_USING_USB_DEVICE + config BSP_USING_USB_DEVICE bool "Enable USB Device" - default n + default n config BSP_USING_USB_HOST bool "Enable USB HOST" - default n + select RT_USING_CACHE + default n endif - menuconfig BSP_USING_WDG - bool "Enable Watchdog" - default n - select RT_USING_WDT if BSP_USING_WDG - if BSP_USING_WDG - config BSP_USING_WDG0 - bool "Enable WDG0" - default n - config BSP_USING_WDG1 - bool "Enable WDG1" - default n - endif + menuconfig BSP_USING_WDG + bool "Enable Watchdog" + default n + select RT_USING_WDT if BSP_USING_WDG + if BSP_USING_WDG + config BSP_USING_WDG0 + bool "Enable WDG0" + default n + config BSP_USING_WDG1 + bool "Enable WDG1" + default n + endif - menuconfig BSP_USING_CAN - bool "Enable CAN" - default n - select RT_USING_CAN if BSP_USING_CAN - if BSP_USING_CAN - config BSP_USING_CAN0 - bool "Enable CAN0" - default n - config BSP_USING_CAN1 - bool "Enable CAN1" - default n - endif + menuconfig BSP_USING_CAN + bool "Enable CAN" + default n + select RT_USING_CAN if BSP_USING_CAN + if BSP_USING_CAN + config BSP_USING_CAN0 + bool "Enable CAN0" + default n + config BSP_USING_CAN1 + bool "Enable CAN1" + default n + endif - menuconfig BSP_USING_ADC - bool "Enable ADC" - default n - select RT_USING_ADC if BSP_USING_ADC - if BSP_USING_ADC + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC if BSP_USING_ADC + if BSP_USING_ADC menuconfig BSP_USING_ADC16 bool "Enable ADC16" default y @@ -251,6 +269,36 @@ menu "On-chip Peripheral Drivers" endif endmenu +menu "Segger SystemView Config" + config BSP_USING_SYSTEMVIEW + select RT_USING_SYSTEMVIEW + select RT_USING_LEGACY + bool "Enable Segger SystemView" + default n + + if BSP_USING_SYSTEMVIEW + menuconfig BSP_SYSTEMVIEW_RTT_SECTION + bool "enable SystemView RTT section" + default y + if BSP_SYSTEMVIEW_RTT_SECTION + config SEGGER_RTT_SECTION + string "segger rtt section" + default ".noncacheable.bss" + config SEGGER_RTT_BUFFER_SECTION + string "segger rtt buffer section" + default ".noncacheable.bss" + config SEGGER_SYSVIEW_SECTION + string "segger sysview section" + default ".noncacheable.bss" + endif + source "$RTT_DIR/../libraries/misc/systemview/Kconfig" + endif +endmenu +menu "Hpmicro Interrupt Config" + config HPM_USING_VECTOR_PREEMPTED_MODE + bool "Enable Vector and Preempted Mode" + default n +endmenu endmenu diff --git a/bsp/hpmicro/hpm6300evk/board/SConscript b/bsp/hpmicro/hpm6300evk/board/SConscript index 3f0a00f1963..b4fccd1c8d7 100644 --- a/bsp/hpmicro/hpm6300evk/board/SConscript +++ b/bsp/hpmicro/hpm6300evk/board/SConscript @@ -8,7 +8,6 @@ src = Split(""" rtt_board.c pinmux.c fal_flash_port.c - eth_phy_port.c """) CPPPATH = [cwd] diff --git a/bsp/hpmicro/hpm6300evk/board/board.c b/bsp/hpmicro/hpm6300evk/board/board.c index f176e26b88f..90055b093dd 100644 --- a/bsp/hpmicro/hpm6300evk/board/board.c +++ b/bsp/hpmicro/hpm6300evk/board/board.c @@ -91,18 +91,23 @@ ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATU void board_init_console(void) { -#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#if CONSOLE_TYPE_UART == BOARD_CONSOLE_TYPE console_config_t cfg; + /* uart needs to configure pin function before enabling clock, otherwise the level change of + uart rx pin when configuring pin function will cause a wrong data to be received. + And a uart rx dma request will be generated by default uart fifo dma trigger level. */ + init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE); + /* Configure the UART clock to 24MHz */ - clock_set_source_divider(BOARD_CONSOLE_CLK_NAME, clk_src_osc24m, 1U); + clock_set_source_divider(BOARD_CONSOLE_UART_CLK_NAME, clk_src_osc24m, 1U); + clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0); cfg.type = BOARD_CONSOLE_TYPE; - cfg.base = (uint32_t) BOARD_CONSOLE_BASE; - cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_CLK_NAME); - cfg.baudrate = BOARD_CONSOLE_BAUDRATE; - - init_uart_pins((UART_Type *) cfg.base); + cfg.base = (uint32_t) BOARD_CONSOLE_UART_BASE; + cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_UART_CLK_NAME); + cfg.baudrate = BOARD_CONSOLE_UART_BAUDRATE; if (status_success != console_init(&cfg)) { /* failed to initialize debug console */ @@ -110,7 +115,9 @@ void board_init_console(void) } } #else - while(1); + while (1) { + } +#endif #endif } @@ -131,12 +138,9 @@ void board_print_clock_freq(void) void board_init_uart(UART_Type *ptr) { + /* configure uart's pin before opening uart's clock */ init_uart_pins(ptr); -} - -void board_init_ahb(void) -{ - clock_set_source_divider(clock_ahb, clk_src_pll1_clk1, 2);/*200m hz*/ + board_init_uart_clock(ptr); } void board_print_banner(void) @@ -152,6 +156,9 @@ void board_print_banner(void) $$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\n\ \\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n\ ----------------------------------------------------------------------\n"}; +#ifdef SDK_VERSION_STRING + printf("hpm_sdk: %s\n", SDK_VERSION_STRING); +#endif printf("%s", banner); } @@ -167,7 +174,6 @@ void board_init(void) board_init_clock(); board_init_console(); board_init_pmp(); - board_init_ahb(); #if BOARD_SHOW_CLOCK board_print_clock_freq(); #endif @@ -231,10 +237,62 @@ void board_timer_create(uint32_t ms, board_timer_cb cb) void board_i2c_bus_clear(I2C_Type *ptr) { init_i2c_pins_as_gpio(ptr); + if (ptr == BOARD_APP_I2C_BASE) { + gpio_set_pin_input(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SDA_GPIO_INDEX, BOARD_I2C_SDA_GPIO_PIN); + gpio_set_pin_input(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN); + if (!gpio_read_pin(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN)) { + printf("CLK is low, please power cycle the board\n"); + while (1) { + } + } + if (!gpio_read_pin(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SDA_GPIO_INDEX, BOARD_I2C_SDA_GPIO_PIN)) { + printf("SDA is low, try to issue I2C bus clear\n"); + } else { + printf("I2C bus is ready\n"); + return; + } + + gpio_set_pin_output(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN); + while (1) { + for (uint32_t i = 0; i < 9; i++) { + gpio_write_pin(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN, 1); + board_delay_ms(10); + gpio_write_pin(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN, 0); + board_delay_ms(10); + } + board_delay_ms(100); + } + printf("I2C bus is cleared\n"); + } } void board_init_i2c(I2C_Type *ptr) { + i2c_config_t config; + hpm_stat_t stat; + uint32_t freq; + if (ptr == NULL) { + return; + } + + board_i2c_bus_clear(ptr); + init_i2c_pins(ptr); + clock_add_to_group(clock_i2c0, 0); + clock_add_to_group(clock_i2c1, 0); + clock_add_to_group(clock_i2c2, 0); + clock_add_to_group(clock_i2c3, 0); + /* Configure the I2C clock to 24MHz */ + clock_set_source_divider(BOARD_APP_I2C_CLK_NAME, clk_src_osc24m, 1U); + + config.i2c_mode = i2c_mode_normal; + config.is_10bit_addressing = false; + freq = clock_get_frequency(BOARD_APP_I2C_CLK_NAME); + stat = i2c_init_master(ptr, freq, &config); + if (stat != status_success) { + printf("failed to initialize i2c 0x%x\n", (uint32_t) ptr); + while (1) { + } + } } uint32_t board_init_spi_clock(SPI_Type *ptr) @@ -242,7 +300,7 @@ uint32_t board_init_spi_clock(SPI_Type *ptr) if (ptr == HPM_SPI3) { /* SPI3 clock configure */ clock_add_to_group(clock_spi3, 0); - clock_set_source_divider(clock_spi3, clk_src_osc24m, 1U); + clock_set_source_divider(clock_spi3, clk_src_pll0_clk0, 5U); /* 80MHz */ return clock_get_frequency(clock_spi3); } @@ -259,10 +317,27 @@ void board_init_spi_pins(SPI_Type *ptr) init_spi_pins(ptr); } +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + init_spi_pins_with_gpio_as_cs(ptr); + gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN), + GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL); +} + +void board_write_spi_cs(uint32_t pin, uint8_t state) +{ + gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state); +} + +uint8_t board_get_led_gpio_off_level(void) +{ + return BOARD_LED_OFF_LEVEL; +} + void board_init_led_pins(void) { init_led_pins(); - gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN); + gpio_set_pin_output_with_initial(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, board_get_led_gpio_off_level()); } void board_led_toggle(void) @@ -291,6 +366,8 @@ uint8_t board_get_usb_id_status(void) void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level) { + (void) usb_index; + (void) level; } void board_init_pmp(void) @@ -328,7 +405,6 @@ void board_init_pmp(void) void board_init_clock(void) { uint32_t cpu0_freq = clock_get_frequency(clock_cpu0); - hpm_core_clock = cpu0_freq; if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) { /* Configure the External OSC ramp-up time: ~9ms */ pllctlv2_xtal_set_rampup_time(HPM_PLLCTLV2, 32UL * 1000UL * 9U); @@ -336,7 +412,10 @@ void board_init_clock(void) /* Select clock setting preset1 */ sysctl_clock_set_preset(HPM_SYSCTL, 2); } + + /* Add most Clocks to group 0 */ + /* not open uart clock in this API, uart should configure pin function before opening clock */ clock_add_to_group(clock_cpu0, 0); clock_add_to_group(clock_ahbp, 0); clock_add_to_group(clock_axic, 0); @@ -397,52 +476,17 @@ void board_init_clock(void) /* Connect Group0 to CPU0 */ clock_connect_group_to_cpu(0, 0); - /* - * Configure CPU0 to 480MHz - * - * NOTE: The PLL2 is disabled by default, and it will be enabled automatically if - * it is required by any nodes. - * Here the PLl2 clock is enabled after switching CPU clock source to it - */ - clock_set_source_divider(clock_cpu0, clk_src_pll1_clk0, 1); + + /* Configure CPU to 480MHz, AXI/AHB to 160MHz */ + sysctl_config_cpu0_domain_clock(HPM_SYSCTL, clock_source_pll1_clk0, 1, 3, 3); /* Configure PLL1_CLK0 Post Divider to 1.2 */ pllctlv2_set_postdiv(HPM_PLLCTLV2, 1, 0, 1); - /* Configure PLL1 clock frequencey to 576MHz, the PLL1_CLK0 frequency =- 576MHz / 1.2 = 480MHz */ + /* Configure PLL1 clock frequencey to 576MHz, the PLL1_CLK0 frequency = 576MHz / 1.2 = 480MHz */ pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 1, 576000000); - clock_update_core_clock(); - clock_set_source_divider(clock_aud1, clk_src_pll2_clk0, 46); /* config clock_aud1 for 44100*n sample rate */ -} - -uint32_t board_init_adc16_clock(ADC16_Type *ptr) -{ - uint32_t freq = 0; - switch ((uint32_t) ptr) { - case HPM_ADC0_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc0, clk_adc_src_ana); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); - freq = clock_get_frequency(clock_adc0); - break; - case HPM_ADC1_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc1, clk_adc_src_ana); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); - freq = clock_get_frequency(clock_adc1); - break; - case HPM_ADC2_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc2, clk_adc_src_ana); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); - freq = clock_get_frequency(clock_adc2); - break; - default: - /* Invalid ADC instance */ - break; - } - - return freq; + /* Configure mchtmr to 24MHz */ + clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1); } uint32_t board_init_dao_clock(void) @@ -455,11 +499,63 @@ uint32_t board_init_pdm_clock(void) return clock_get_frequency(clock_pdm); } +hpm_stat_t board_set_audio_pll_clock(uint32_t freq) +{ + return pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 2, freq); /* pll2clk */ +} + uint32_t board_init_i2s_clock(I2S_Type *ptr) { + (void) ptr; return 0; } +void board_init_adc16_pins(void) +{ + init_adc_pins(); +} + +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) +{ + uint32_t freq = 0; + + if (ptr == HPM_ADC0) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@160MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll0_clk1 divided by 2 (@166MHz by default) */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll0_clk1, 2U); + } + + freq = clock_get_frequency(clock_adc0); + } else if (ptr == HPM_ADC1) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@160MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@166MHz by default) */ + clock_set_adc_source(clock_adc1, clk_adc_src_ana1); + clock_set_source_divider(clock_ana1, clk_src_pll0_clk1, 2U); + } + + freq = clock_get_frequency(clock_adc1); + } else if (ptr == HPM_ADC2) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@160MHz by default)*/ + clock_set_adc_source(clock_adc2, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@166MHz by default) */ + clock_set_adc_source(clock_adc2, clk_adc_src_ana2); + clock_set_source_divider(clock_ana2, clk_src_pll0_clk1, 2U); + } + + freq = clock_get_frequency(clock_adc2); + } + + return freq; +} uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb) { @@ -468,10 +564,10 @@ uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb) if (ptr == HPM_DAC) { if (clk_src_ahb == true) { /* Configure the DAC clock to 160MHz */ - clock_set_dac_source(clock_dac0, clk_dac_src_ahb); + clock_set_dac_source(clock_dac0, clk_dac_src_ahb0); } else { /* Configure the DAC clock to 166MHz */ - clock_set_dac_source(clock_dac0, clk_dac_src_ana); + clock_set_dac_source(clock_dac0, clk_dac_src_ana3); clock_set_source_divider(clock_ana3, clk_src_pll0_clk1, 2); } @@ -530,6 +626,12 @@ uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) else { /* Invalid instance */ } + return freq; +} + +void board_sd_power_switch(SDXC_Type *ptr, bool on_off) +{ + /* This feature is not supported */ } /* @@ -575,19 +677,14 @@ void _init_ext_ram(void) sdram_config.refresh_count = BOARD_SDRAM_REFRESH_COUNT; sdram_config.refresh_in_ms = BOARD_SDRAM_REFRESH_IN_MS; sdram_config.data_width_in_byte = BOARD_SDRAM_DATA_WIDTH_IN_BYTE; + sdram_config.delay_cell_disable = false; sdram_config.delay_cell_value = 29; femc_config_sdram(HPM_FEMC, femc_clk_in_hz, &sdram_config); } -void board_init_sd_pins(SDXC_Type *ptr) -{ - init_sdxc_pins(ptr, false); - init_sdxc_card_detection_pin(ptr); -} - -uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq) +uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inverse) { uint32_t actual_freq = 0; do { @@ -595,6 +692,7 @@ uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq) break; } clock_name_t sdxc_clk = clock_sdxc0; + sdxc_enable_inverse_clock(ptr, false); sdxc_enable_sd_clock(ptr, false); /* Configure the SDXC Frequency to 200MHz */ clock_set_source_divider(sdxc_clk, clk_src_pll0_clk0, 2); @@ -605,11 +703,11 @@ uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq) sdxc_set_clock_divider(ptr, 600); } /* configure the clock to 24MHz for the SDR12/Default speed */ - else if (freq <= 25000000UL) { + else if (freq <= 26000000UL) { sdxc_set_clock_divider(ptr, 8); } /* Configure the clock to 50MHz for the SDR25/High speed/50MHz DDR/50MHz SDR */ - else if (freq <= 50000000UL) { + else if (freq <= 52000000UL) { sdxc_set_clock_divider(ptr, 4); } /* Configure the clock to 100MHz for the SDR50 */ @@ -624,6 +722,9 @@ uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq) else { sdxc_set_clock_divider(ptr, 8); } + if (need_inverse) { + sdxc_enable_inverse_clock(ptr, true); + } sdxc_enable_sd_clock(ptr, true); actual_freq = clock_get_frequency(sdxc_clk) / sdxc_get_clock_divider(ptr); } while (false); @@ -633,11 +734,7 @@ uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq) void board_sd_switch_pins_to_1v8(SDXC_Type *ptr) { - /* This feature is not supported */ -} - -void board_sd_power_switch(SDXC_Type *ptr, bool on_off) -{ + (void) ptr; /* This feature is not supported */ } @@ -661,14 +758,19 @@ hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr) hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) { - if (internal == false) { - return status_success; - } - /* Configure Enet clock to output reference clock */ if (ptr == HPM_ENET0) { - /* make sure pll0_clk2 output clock at 250MHz then set 50MHz for enet0 */ - clock_set_source_divider(clock_eth0, clk_src_pll0_clk2, 5); + if (internal) { + /* set pll output frequency at 1GHz */ + if (pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, PLLCTLV2_PLL_PLL2, 1000000000UL) == status_success) { + /* set pll2_clk1 output frequence at 250MHz from PLL2 divided by 4 (1 + 15 / 5) */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, PLLCTLV2_PLL_PLL2, 1, 15); + /* set eth clock frequency at 50MHz for enet0 */ + clock_set_source_divider(clock_eth0, clk_src_pll2_clk1, 5); + } else { + return status_fail; + } + } } else { return status_invalid_argument; } @@ -678,11 +780,6 @@ hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) return status_success; } -void board_init_adc16_pins(void) -{ - init_adc_pins(); -} - hpm_stat_t board_init_enet_pins(ENET_Type *ptr) { init_enet_pins(ptr); @@ -692,6 +789,7 @@ hpm_stat_t board_init_enet_pins(ENET_Type *ptr) hpm_stat_t board_reset_enet_phy(ENET_Type *ptr) { + (void) ptr; return status_success; } @@ -721,12 +819,20 @@ uint32_t board_init_uart_clock(UART_Type *ptr) return freq; } -uint8_t board_enet_get_dma_pbl(ENET_Type *ptr) +uint32_t board_init_pwm_clock(PWM_Type *ptr) { + uint32_t freq = 0; + (void) ptr; + return freq; +} + +uint8_t board_get_enet_dma_pbl(ENET_Type *ptr) +{ + (void) ptr; return enet_pbl_16; } -hpm_stat_t board_enet_enable_irq(ENET_Type *ptr) +hpm_stat_t board_enable_enet_irq(ENET_Type *ptr) { if (ptr == HPM_ENET0) { intc_m_enable_irq(IRQn_ENET0); @@ -737,7 +843,7 @@ hpm_stat_t board_enet_enable_irq(ENET_Type *ptr) return status_success; } -hpm_stat_t board_enet_disable_irq(ENET_Type *ptr) +hpm_stat_t board_disable_enet_irq(ENET_Type *ptr) { if (ptr == HPM_ENET0) { intc_m_disable_irq(IRQn_ENET0); @@ -747,3 +853,9 @@ hpm_stat_t board_enet_disable_irq(ENET_Type *ptr) return status_success; } + +void board_init_enet_pps_pins(ENET_Type *ptr) +{ + (void) ptr; + init_enet_pps_pins(); +} diff --git a/bsp/hpmicro/hpm6300evk/board/board.h b/bsp/hpmicro/hpm6300evk/board/board.h index 7410b1b2b11..63b9d826370 100644 --- a/bsp/hpmicro/hpm6300evk/board/board.h +++ b/bsp/hpmicro/hpm6300evk/board/board.h @@ -13,125 +13,172 @@ #include "hpm_soc.h" #include "hpm_soc_feature.h" #include "pinmux.h" +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#include "hpm_debug_console.h" +#endif -#define BOARD_NAME "hpm6300evk" +#define BOARD_NAME "hpm6300evk" #define BOARD_UF2_SIGNATURE (0x0A4D5048UL) /* dma section */ -#define BOARD_APP_XDMA HPM_XDMA -#define BOARD_APP_HDMA HPM_HDMA +#define BOARD_APP_XDMA HPM_XDMA +#define BOARD_APP_HDMA HPM_HDMA #define BOARD_APP_XDMA_IRQ IRQn_XDMA #define BOARD_APP_HDMA_IRQ IRQn_HDMA -#define BOARD_APP_DMAMUX HPM_DMAMUX +#define BOARD_APP_DMAMUX HPM_DMAMUX -/* uart section */ #ifndef BOARD_RUNNING_CORE #define BOARD_RUNNING_CORE HPM_CORE0 #endif + +/* uart section */ #ifndef BOARD_APP_UART_BASE -#define BOARD_APP_UART_BASE HPM_UART0 -#define BOARD_APP_UART_IRQ IRQn_UART0 -#else -#ifndef BOARD_APP_UART_IRQ -#warning no IRQ specified for applicaiton uart -#endif +#define BOARD_APP_UART_BASE HPM_UART2 +#define BOARD_APP_UART_IRQ IRQn_UART2 +#define BOARD_APP_UART_BAUDRATE (115200UL) +#define BOARD_APP_UART_CLK_NAME clock_uart2 +#define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART2_RX +#define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART2_TX #endif -#define BOARD_APP_UART_BAUDRATE (115200UL) -#define BOARD_APP_UART_CLK_NAME clock_uart0 - +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE #ifndef BOARD_CONSOLE_TYPE #define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART #endif -#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART -#ifndef BOARD_CONSOLE_BASE +#if CONSOLE_TYPE_UART == BOARD_CONSOLE_TYPE +#ifndef BOARD_CONSOLE_UART_BASE #if BOARD_RUNNING_CORE == HPM_CORE0 -#define BOARD_CONSOLE_BASE HPM_UART0 -#define BOARD_CONSOLE_CLK_NAME clock_uart0 +#define BOARD_CONSOLE_UART_BASE HPM_UART0 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART0 +#define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX +#define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX #else -#define BOARD_CONSOLE_BASE HPM_UART13 -#define BOARD_CONSOLE_CLK_NAME clock_uart13 +#define BOARD_CONSOLE_UART_BASE HPM_UART13 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart13 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART13 +#define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART13_TX +#define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART13_RX #endif #endif -#define BOARD_CONSOLE_BAUDRATE (115200UL) +#define BOARD_CONSOLE_UART_BAUDRATE (115200UL) +#endif #endif - -#define BOARD_FREEMASTER_UART_BASE HPM_UART0 -#define BOARD_FREEMASTER_UART_IRQ IRQn_UART0 -#define BOARD_FREEMASTER_UART_CLK_NAME clock_uart0 /* uart rx idle demo section */ -#define BOARD_UART_IDLE HPM_UART2 -#define BOARD_UART_IDLE_DMA_SRC HPM_DMA_SRC_UART2_RX - -#define BOARD_UART_IDLE_TRGM HPM_TRGM1 -#define BOARD_UART_IDLE_TRGM_PIN IOC_PAD_PA24 -#define BOARD_UART_IDLE_TRGM_INPUT_SRC HPM_TRGM1_INPUT_SRC_TRGM1_P4 -#define BOARD_UART_IDLE_TRGM_OUTPUT_GPTMR_IN HPM_TRGM1_OUTPUT_SRC_GPTMR2_IN2 +#define BOARD_UART_IDLE BOARD_APP_UART_BASE +#define BOARD_UART_IDLE_IRQ BOARD_APP_UART_IRQ +#define BOARD_UART_IDLE_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_UART_IDLE_TX_DMA_SRC BOARD_APP_UART_TX_DMA_REQ +#define BOARD_UART_IDLE_DMA_SRC BOARD_APP_UART_RX_DMA_REQ + +#define BOARD_UART_IDLE_TRGM HPM_TRGM1 +#define BOARD_UART_IDLE_TRGM_PIN IOC_PAD_PA24 +#define BOARD_UART_IDLE_TRGM_INPUT_SRC HPM_TRGM1_INPUT_SRC_TRGM1_P4 +#define BOARD_UART_IDLE_TRGM_OUTPUT_GPTMR_IN HPM_TRGM1_OUTPUT_SRC_GPTMR2_IN2 #define BOARD_UART_IDLE_TRGM_OUTPUT_GPTMR_SYNCI HPM_TRGM1_OUTPUT_SRC_GPTMR2_SYNCI -#define BOARD_UART_IDLE_GPTMR HPM_GPTMR2 +#define BOARD_UART_IDLE_GPTMR HPM_GPTMR2 #define BOARD_UART_IDLE_GPTMR_CLK_NAME clock_gptmr2 -#define BOARD_UART_IDLE_GPTMR_IRQ IRQn_GPTMR2 -#define BOARD_UART_IDLE_GPTMR_CMP_CH 0 -#define BOARD_UART_IDLE_GPTMR_CAP_CH 2 +#define BOARD_UART_IDLE_GPTMR_IRQ IRQn_GPTMR2 +#define BOARD_UART_IDLE_GPTMR_CMP_CH 0 +#define BOARD_UART_IDLE_GPTMR_CAP_CH 2 + +/* uart lin sample section */ +#define BOARD_UART_LIN BOARD_APP_UART_BASE +#define BOARD_UART_LIN_IRQ BOARD_APP_UART_IRQ +#define BOARD_UART_LIN_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_UART_LIN_TX_PORT GPIO_DI_GPIOC +#define BOARD_UART_LIN_TX_PIN (26U) /* PC26 should align with used pin in pinmux configuration */ + +/* uart microros sample section */ +#define BOARD_MICROROS_UART_BASE BOARD_APP_UART_BASE +#define BOARD_MICROROS_UART_IRQ BOARD_APP_UART_IRQ +#define BOARD_MICROROS_UART_CLK_NAME BOARD_APP_UART_CLK_NAME + +/* rtthread-nano finsh section */ +#define BOARD_RT_CONSOLE_BASE BOARD_CONSOLE_UART_BASE + +/* usb cdc acm uart section */ +#define BOARD_USB_CDC_ACM_UART BOARD_APP_UART_BASE +#define BOARD_USB_CDC_ACM_UART_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_USB_CDC_ACM_UART_TX_DMA_SRC BOARD_APP_UART_TX_DMA_REQ +#define BOARD_USB_CDC_ACM_UART_RX_DMA_SRC BOARD_APP_UART_RX_DMA_REQ + +/* modbus sample section */ +#define BOARD_MODBUS_UART_BASE BOARD_APP_UART_BASE +#define BOARD_MODBUS_UART_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_MODBUS_UART_RX_DMA_REQ BOARD_APP_UART_RX_DMA_REQ +#define BOARD_MODBUS_UART_TX_DMA_REQ BOARD_APP_UART_TX_DMA_REQ /* sdram section */ -#define BOARD_SDRAM_ADDRESS (0x40000000UL) -#define BOARD_SDRAM_SIZE (32*SIZE_1MB) -#define BOARD_SDRAM_CS FEMC_SDRAM_CS0 -#define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_16_BITS -#define BOARD_SDRAM_REFRESH_COUNT (8192UL) -#define BOARD_SDRAM_REFRESH_IN_MS (64UL) +#define BOARD_SDRAM_ADDRESS (0x40000000UL) +#define BOARD_SDRAM_SIZE (32 * SIZE_1MB) +#define BOARD_SDRAM_CS FEMC_SDRAM_CS0 +#define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_16_BITS +#define BOARD_SDRAM_REFRESH_COUNT (8192UL) +#define BOARD_SDRAM_REFRESH_IN_MS (64UL) #define BOARD_SDRAM_DATA_WIDTH_IN_BYTE (4UL) - /* nor flash section */ #define BOARD_FLASH_BASE_ADDRESS (0x80000000UL) -#define BOARD_FLASH_SIZE (16 * SIZE_1MB) +#define BOARD_FLASH_SIZE (16 * SIZE_1MB) /* i2c section */ -#define BOARD_APP_I2C_BASE HPM_I2C0 -#define BOARD_APP_I2C_CLK_NAME clock_i2c0 -#define BOARD_APP_I2C_DMA HPM_HDMA -#define BOARD_APP_I2C_DMAMUX HPM_DMAMUX -#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0 -#define BOARD_APP_I2C_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 +#define BOARD_APP_I2C_BASE HPM_I2C0 +#define BOARD_APP_I2C_IRQ IRQn_I2C0 +#define BOARD_APP_I2C_CLK_NAME clock_i2c0 +#define BOARD_APP_I2C_DMA HPM_HDMA +#define BOARD_APP_I2C_DMAMUX HPM_DMAMUX +#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0 +#define BOARD_I2C_GPIO_CTRL HPM_GPIO0 +#define BOARD_I2C_SCL_GPIO_INDEX GPIO_DO_GPIOC +#define BOARD_I2C_SCL_GPIO_PIN 13 +#define BOARD_I2C_SDA_GPIO_INDEX GPIO_DO_GPIOC +#define BOARD_I2C_SDA_GPIO_PIN 14 /* ACMP desction */ -#define BOARD_ACMP HPM_ACMP -#define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 -#define BOARD_ACMP_IRQ IRQn_ACMP_1 -#define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ +#define BOARD_ACMP HPM_ACMP +#define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 +#define BOARD_ACMP_IRQ IRQn_ACMP_1 +#define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ #define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_5 /* align with used pin */ /* dma section */ -#define BOARD_APP_XDMA HPM_XDMA -#define BOARD_APP_HDMA HPM_HDMA +#define BOARD_APP_XDMA HPM_XDMA +#define BOARD_APP_HDMA HPM_HDMA #define BOARD_APP_XDMA_IRQ IRQn_XDMA #define BOARD_APP_HDMA_IRQ IRQn_HDMA -#define BOARD_APP_DMAMUX HPM_DMAMUX +#define BOARD_APP_DMAMUX HPM_DMAMUX /* gptmr section */ -#define BOARD_GPTMR HPM_GPTMR2 -#define BOARD_GPTMR_IRQ IRQn_GPTMR2 -#define BOARD_GPTMR_CHANNEL 0 -#define BOARD_GPTMR_PWM HPM_GPTMR2 -#define BOARD_GPTMR_PWM_CHANNEL 0 +#define BOARD_GPTMR HPM_GPTMR2 +#define BOARD_GPTMR_IRQ IRQn_GPTMR2 +#define BOARD_GPTMR_CHANNEL 0 +#define BOARD_GPTMR_DMA_SRC HPM_DMA_SRC_GPTMR2_0 +#define BOARD_GPTMR_CLK_NAME clock_gptmr2 +#define BOARD_GPTMR_PWM HPM_GPTMR2 +#define BOARD_GPTMR_PWM_DMA_SRC HPM_DMA_SRC_GPTMR2_0 +#define BOARD_GPTMR_PWM_CHANNEL 0 +#define BOARD_GPTMR_PWM_CLK_NAME clock_gptmr2 +#define BOARD_GPTMR_PWM_IRQ IRQn_GPTMR2 +#define BOARD_GPTMR_PWM_SYNC HPM_GPTMR2 +#define BOARD_GPTMR_PWM_SYNC_CHANNEL 1 +#define BOARD_GPTMR_PWM_SYNC_CLK_NAME clock_gptmr2 /* gpio section */ #define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOZ -#define BOARD_APP_GPIO_PIN 2 +#define BOARD_APP_GPIO_PIN 2 /* pinmux section */ #define USING_GPIO0_FOR_GPIOZ #ifndef USING_GPIO0_FOR_GPIOZ #define BOARD_APP_GPIO_CTRL HPM_BGPIO -#define BOARD_APP_GPIO_IRQ IRQn_BGPIO +#define BOARD_APP_GPIO_IRQ IRQn_BGPIO #else #define BOARD_APP_GPIO_CTRL HPM_GPIO0 -#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_Z +#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_Z #endif /* gpiom section */ @@ -140,41 +187,49 @@ #define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast /* spi section */ -#define BOARD_APP_SPI_BASE HPM_SPI3 -#define BOARD_APP_SPI_CLK_SRC_FREQ (24000000UL) -#define BOARD_APP_SPI_SCLK_FREQ (1562500UL) +#define BOARD_APP_SPI_BASE HPM_SPI3 +#define BOARD_APP_SPI_CLK_NAME clock_spi3 +#define BOARD_APP_SPI_IRQ IRQn_SPI3 +#define BOARD_APP_SPI_SCLK_FREQ (20000000UL) #define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U) #define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U) -#define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI3_RX -#define BOARD_APP_SPI_RX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 -#define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI3_TX -#define BOARD_APP_SPI_TX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX1 - +#define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI3_RX +#define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI3_TX +#define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 +#define BOARD_SPI_CS_PIN IOC_PAD_PC18 +#define BOARD_SPI_CS_ACTIVE_LEVEL (0U) /* Flash section */ -#define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) -#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90001U) -#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000007U) -#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) +#define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) +#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90001U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000005U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) /* i2s section */ -#define BOARD_APP_I2S_BASE HPM_I2S0 +#define BOARD_APP_I2S_BASE HPM_I2S0 #define BOARD_APP_I2S_DATA_LINE (2U) -#define BOARD_APP_I2S_CLK_NAME clock_i2s0 +#define BOARD_APP_I2S_CLK_NAME clock_i2s0 +#define BOARD_APP_AUDIO_CLK_SRC clock_source_pll2_clk0 +#define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll2clk0 /* enet section */ -#define BOARD_ENET_RMII HPM_ENET0 +#define BOARD_ENET_PPS HPM_ENET0 +#define BOARD_ENET_PPS_IDX enet_pps_0 +#define BOARD_ENET_PPS_PTP_CLOCK clock_ptp0 + +#define BOARD_ENET_RMII HPM_ENET0 #define BOARD_ENET_RMII_RST_GPIO #define BOARD_ENET_RMII_RST_GPIO_INDEX #define BOARD_ENET_RMII_RST_GPIO_PIN -#define BOARD_ENET_RMII HPM_ENET0 -#define BOARD_ENET_RMII_INT_REF_CLK (1U) -#define BOARD_ENET_RMII_PTP_CLOCK (clock_ptp0) +#define BOARD_ENET_RMII HPM_ENET0 +#define BOARD_ENET_RMII_INT_REF_CLK (1U) +#define BOARD_ENET_RMII_PTP_CLOCK (clock_ptp0) +#define BOARD_ENET_RMII_PPS0_PINOUT (1) + #define BOARD_ENET0_INF (0U) /* 0: RMII, 1: RGMII */ -#define BOARD_ENET0_INT_REF_CLK (0U) +#define BOARD_ENET0_INT_REF_CLK (1U) #define BOARD_ENET0_PHY_RST_TIME (30) - #if BOARD_ENET0_INF #define BOARD_ENET0_TX_DLY (0U) #define BOARD_ENET0_RX_DLY (0U) @@ -186,46 +241,52 @@ /* ADC section */ -#define BOARD_APP_ADC16_NAME "ADC0" -#define BOARD_APP_ADC16_BASE HPM_ADC0 -#define BOARD_APP_ADC16_IRQn IRQn_ADC0 -#define BOARD_APP_ADC16_CH (13U) -#define BOARD_APP_ADC_SEQ_DMA_SIZE_IN_4BYTES (1024U) -#define BOARD_APP_ADC_PMT_DMA_SIZE_IN_4BYTES (192U) -#define BOARD_APP_ADC_PREEMPT_TRIG_LEN (1U) -#define BOARD_APP_ADC_SINGLE_CONV_CNT (6) -#define BOARD_APP_ADC_TRIG_PWMT0 HPM_PWM0 -#define BOARD_APP_ADC_TRIG_PWMT1 HPM_PWM1 -#define BOARD_APP_ADC_TRIG_TRGM0 HPM_TRGM0 -#define BOARD_APP_ADC_TRIG_TRGM1 HPM_TRGM1 -#define BOARD_APP_ADC_TRIG_PWM_SYNC HPM_SYNT +#define BOARD_APP_ADC16_NAME "ADC0" +#define BOARD_APP_ADC16_BASE HPM_ADC0 +#define BOARD_APP_ADC16_IRQn IRQn_ADC0 +#define BOARD_APP_ADC16_CH_1 (6U) +#define BOARD_APP_ADC16_CLK_NAME (clock_adc0) + +#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI +#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A + +#define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A /* DAC section */ -#define BOARD_DAC_BASE HPM_DAC -#define BOARD_DAC_IRQn IRQn_DAC -#define BOARD_DAC_CLOCK_NAME clock_dac0 +#define BOARD_DAC_BASE HPM_DAC +#define BOARD_DAC_IRQn IRQn_DAC +#define BOARD_APP_DAC_CLOCK_NAME clock_dac0 /* CAN section */ -#define BOARD_APP_CAN_BASE HPM_CAN1 -#define BOARD_APP_CAN_IRQn IRQn_CAN1 +#define BOARD_APP_CAN_BASE HPM_CAN1 +#define BOARD_APP_CAN_IRQn IRQn_CAN1 /* * timer for board delay */ -#define BOARD_DELAY_TIMER (HPM_GPTMR3) -#define BOARD_DELAY_TIMER_CH 0 +#define BOARD_DELAY_TIMER (HPM_GPTMR3) +#define BOARD_DELAY_TIMER_CH 0 #define BOARD_DELAY_TIMER_CLK_NAME (clock_gptmr3) -#define BOARD_CALLBACK_TIMER (HPM_GPTMR3) -#define BOARD_CALLBACK_TIMER_CH 1 -#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR3 +#define BOARD_CALLBACK_TIMER (HPM_GPTMR3) +#define BOARD_CALLBACK_TIMER_CH 1 +#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR3 #define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr3) /* SDXC section */ -#define BOARD_APP_SDCARD_SDXC_BASE (HPM_SDXC0) -#define BOARD_APP_SDCARD_CDN_GPIO_CTRL (HPM_GPIO0) -#define BOARD_APP_SDCARD_CDN_GPIO_PIN (15UL) -#define BOARD_APP_SDCARD_SUPPORT_1V8 (0) +#define BOARD_APP_SDCARD_SDXC_BASE (HPM_SDXC0) +#define BOARD_APP_SDCARD_SUPPORT_3V3 (1) +#define BOARD_APP_SDCARD_SUPPORT_1V8 (0) +#define BOARD_APP_SDCARD_SUPPORT_4BIT (1) +#define BOARD_APP_SDCARD_SUPPORT_CARD_DETECTION (1) +#define BOARD_APP_EMMC_SDXC_BASE (HPM_SDXC0) +#define BOARD_APP_EMMC_SUPPORT_3V3 (1) +#define BOARD_APP_EMMC_SUPPORT_1V8 (0) +#define BOARD_APP_EMMC_SUPPORT_4BIT (1) +#define BOARD_APP_EMMC_HOST_USING_IRQ (0) /* USB section */ #define BOARD_USB0_ID_PORT (HPM_GPIO0) @@ -235,86 +296,89 @@ /*BLDC pwm*/ /*PWM define*/ -#define BOARD_BLDCPWM HPM_PWM0 -#define BOARD_BLDC_UH_PWM_OUTPIN (0U) -#define BOARD_BLDC_UL_PWM_OUTPIN (1U) -#define BOARD_BLDC_VH_PWM_OUTPIN (2U) -#define BOARD_BLDC_VL_PWM_OUTPIN (3U) -#define BOARD_BLDC_WH_PWM_OUTPIN (4U) -#define BOARD_BLDC_WL_PWM_OUTPIN (5U) -#define BOARD_BLDCPWM_TRGM HPM_TRGM0 -#define BOARD_BLDCAPP_PWM_IRQ IRQn_PWM0 -#define BOARD_BLDCPWM_CMP_INDEX_0 (0U) -#define BOARD_BLDCPWM_CMP_INDEX_1 (1U) -#define BOARD_BLDCPWM_CMP_INDEX_2 (2U) -#define BOARD_BLDCPWM_CMP_INDEX_3 (3U) -#define BOARD_BLDCPWM_CMP_INDEX_4 (4U) -#define BOARD_BLDCPWM_CMP_INDEX_5 (5U) +#define BOARD_BLDCPWM HPM_PWM0 +#define BOARD_BLDC_UH_PWM_OUTPIN (0U) +#define BOARD_BLDC_UL_PWM_OUTPIN (1U) +#define BOARD_BLDC_VH_PWM_OUTPIN (2U) +#define BOARD_BLDC_VL_PWM_OUTPIN (3U) +#define BOARD_BLDC_WH_PWM_OUTPIN (4U) +#define BOARD_BLDC_WL_PWM_OUTPIN (5U) +#define BOARD_BLDCPWM_TRGM HPM_TRGM0 +#define BOARD_BLDCAPP_PWM_IRQ IRQn_PWM0 +#define BOARD_BLDCPWM_CMP_INDEX_0 (0U) +#define BOARD_BLDCPWM_CMP_INDEX_1 (1U) +#define BOARD_BLDCPWM_CMP_INDEX_2 (2U) +#define BOARD_BLDCPWM_CMP_INDEX_3 (3U) +#define BOARD_BLDCPWM_CMP_INDEX_4 (4U) +#define BOARD_BLDCPWM_CMP_INDEX_5 (5U) +#define BOARD_BLDCPWM_CMP_INDEX_6 (6U) +#define BOARD_BLDCPWM_CMP_INDEX_7 (7U) +#define BOARD_BLDCPWM_CMP_TRIG_CMP (20U) /*HALL define*/ -#define BOARD_BLDC_HALL_BASE HPM_HALL0 -#define BOARD_BLDC_HALL_TRGM HPM_TRGM0 -#define BOARD_BLDC_HALL_IRQ IRQn_HALL0 -#define BOARD_BLDC_HALL_TRGM_HALL_U_SRC HPM_TRGM0_INPUT_SRC_TRGM0_IN8 -#define BOARD_BLDC_HALL_TRGM_HALL_V_SRC HPM_TRGM0_INPUT_SRC_TRGM0_IN7 -#define BOARD_BLDC_HALL_TRGM_HALL_W_SRC HPM_TRGM0_INPUT_SRC_TRGM0_IN6 -#define BOARD_BLDC_HALL_MOTOR_PHASE_COUNT_PER_REV (1000U) - - +#define BOARD_BLDC_HALL_BASE HPM_HALL0 +#define BOARD_BLDC_HALL_TRGM HPM_TRGM0 +#define BOARD_BLDC_HALL_IRQ IRQn_HALL0 +#define BOARD_BLDC_HALL_TRGM_HALL_U_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P8 +#define BOARD_BLDC_HALL_TRGM_HALL_V_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P7 +#define BOARD_BLDC_HALL_TRGM_HALL_W_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P6 +#define BOARD_BLDC_HALL_MOTOR_PHASE_COUNT_PER_REV (1000U) /*QEI*/ -#define BOARD_BLDC_QEI_BASE HPM_QEI0 -#define BOARD_BLDC_QEI_IRQ IRQn_QEI0 -#define BOARD_BLDC_QEI_TRGM HPM_TRGM0 -#define BOARD_BLDC_QEI_TRGM_QEI_A_SRC HPM_TRGM0_INPUT_SRC_TRGM0_IN9 -#define BOARD_BLDC_QEI_TRGM_QEI_B_SRC HPM_TRGM0_INPUT_SRC_TRGM0_IN10 -#define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV (16U) -#define BOARD_BLDC_QEI_CLOCK_SOURCE clock_mot0 -#define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV (4000U) +#define BOARD_BLDC_QEI_BASE HPM_QEI0 +#define BOARD_BLDC_QEI_IRQ IRQn_QEI0 +#define BOARD_BLDC_QEI_TRGM HPM_TRGM0 +#define BOARD_BLDC_QEI_TRGM_QEI_A_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P9 +#define BOARD_BLDC_QEI_TRGM_QEI_B_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P10 +#define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV (16U) +#define BOARD_BLDC_QEI_CLOCK_SOURCE clock_mot0 +#define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV (4000U) /*Timer define*/ -#define BOARD_BLDC_TMR_1MS HPM_GPTMR2 -#define BOARD_BLDC_TMR_CH 0 -#define BOARD_BLDC_TMR_CMP 0 -#define BOARD_BLDC_TMR_IRQ IRQn_GPTMR2 -#define BOARD_BLDC_TMR_RELOAD (100000U) +#define BOARD_BLDC_TMR_1MS HPM_GPTMR2 +#define BOARD_BLDC_TMR_CH 0 +#define BOARD_BLDC_TMR_CMP 0 +#define BOARD_BLDC_TMR_IRQ IRQn_GPTMR2 +#define BOARD_BLDC_TMR_RELOAD (100000U) /*adc*/ -#define BOARD_BLDC_ADC_MODULE ADCX_MODULE_ADC16 -#define BOARD_BLDC_ADC_U_BASE HPM_ADC1 -#define BOARD_BLDC_ADC_V_BASE HPM_ADC0 -#define BOARD_BLDC_ADC_W_BASE HPM_ADC2 -#define BOARD_BLDC_ADC_TRIG_FLAG adc16_event_trig_complete - -#define BOARD_BLDC_ADC_CH_U (14U) -#define BOARD_BLDC_ADC_CH_V (12U) -#define BOARD_BLDC_ADC_CH_W (5U) -#define BOARD_BLDC_ADC_IRQn IRQn_ADC1 -#define BOARD_BLDC_ADC_SEQ_DMA_SIZE_IN_4BYTES (40U) +#define BOARD_BLDC_ADC_MODULE ADCX_MODULE_ADC16 +#define BOARD_BLDC_ADC_U_BASE HPM_ADC1 +#define BOARD_BLDC_ADC_V_BASE HPM_ADC0 +#define BOARD_BLDC_ADC_W_BASE HPM_ADC2 +#define BOARD_BLDC_ADC_TRIG_FLAG adc16_event_trig_complete + +#define BOARD_BLDC_ADC_CH_U (7U) +#define BOARD_BLDC_ADC_CH_V (12U) +#define BOARD_BLDC_ADC_CH_W (5U) +#define BOARD_BLDC_ADC_IRQn IRQn_ADC1 +#define BOARD_BLDC_ADC_PMT_DMA_SIZE_IN_4BYTES (ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES) #define BOARD_BLDC_ADC_TRG ADC16_CONFIG_TRG0A -#define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) -#define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U) -#define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM0_INPUT_SRC_PWM0_CH8REF -#define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A +#define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) +#define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U) +#define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A /* APP PWM */ -#define BOARD_APP_PWM HPM_PWM0 -#define BOARD_APP_PWM_CLOCK_NAME clock_mot0 -#define BOARD_APP_PWM_OUT1 0 -#define BOARD_APP_PWM_OUT2 1 -#define BOARD_APP_TRGM HPM_TRGM0 +#define BOARD_APP_PWM HPM_PWM0 +#define BOARD_APP_PWM_CLOCK_NAME clock_mot0 +#define BOARD_APP_PWM_OUT1 0 +#define BOARD_APP_PWM_OUT2 1 +#define BOARD_APP_TRGM HPM_TRGM0 +#define BOARD_APP_PWM_IRQ IRQn_PWM0 +#define BOARD_APP_TRGM_PWM_OUTPUT TRGM_TRGOCFG_PWM_SYNCI #define BOARD_CPU_FREQ (480000000UL) /* LED */ -#define BOARD_LED_GPIO_CTRL HPM_GPIO0 +#define BOARD_LED_GPIO_CTRL HPM_GPIO0 #define BOARD_LED_GPIO_INDEX GPIO_DI_GPIOA -#define BOARD_LED_GPIO_PIN 7 -#define BOARD_LED_OFF_LEVEL 1 -#define BOARD_LED_ON_LEVEL 0 +#define BOARD_LED_GPIO_PIN 7 +#define BOARD_LED_OFF_LEVEL 1 +#define BOARD_LED_ON_LEVEL 0 #ifndef BOARD_SHOW_CLOCK #define BOARD_SHOW_CLOCK 1 @@ -323,6 +387,21 @@ #define BOARD_SHOW_BANNER 1 #endif +/* FreeRTOS Definitions */ +#define BOARD_FREERTOS_TIMER HPM_GPTMR1 +#define BOARD_FREERTOS_TIMER_CHANNEL 1 +#define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR1 +#define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr1 + +/* Threadx Definitions */ +#define BOARD_THREADX_TIMER HPM_GPTMR1 +#define BOARD_THREADX_TIMER_CHANNEL 1 +#define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR1 +#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr1 +/* Tamper Section */ +#define BOARD_TAMP_NO_LEVEL_PINS +#define BOARD_TAMP_ACTIVE_CH 6 + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ @@ -342,6 +421,8 @@ uint32_t board_init_femc_clock(void); void board_init_sdram_pins(void); void board_init_gpio_pins(void); void board_init_spi_pins(SPI_Type *ptr); +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); +void board_write_spi_cs(uint32_t pin, uint8_t state); void board_init_led_pins(void); void board_led_write(uint8_t state); @@ -352,7 +433,7 @@ void board_init_clock(void); uint32_t board_init_spi_clock(SPI_Type *ptr); -uint32_t board_init_adc16_clock(ADC16_Type *ptr); +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb); uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb); @@ -366,23 +447,22 @@ uint32_t board_init_i2s_clock(I2S_Type *ptr); uint32_t board_init_pdm_clock(void); uint32_t board_init_dao_clock(void); -void board_init_sd_pins(SDXC_Type *ptr); -uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq); +uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inverse); void board_sd_switch_pins_to_1v8(SDXC_Type *ptr); bool board_sd_detect_card(SDXC_Type *ptr); -void board_sd_power_switch(SDXC_Type *ptr, bool on_off); void board_init_usb_pins(void); void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); uint8_t board_get_usb_id_status(void); -uint8_t board_enet_get_dma_pbl(ENET_Type *ptr); +void board_init_enet_pps_pins(ENET_Type *ptr); +uint8_t board_get_enet_dma_pbl(ENET_Type *ptr); hpm_stat_t board_reset_enet_phy(ENET_Type *ptr); hpm_stat_t board_init_enet_pins(ENET_Type *ptr); hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal); hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr); -hpm_stat_t board_enet_enable_irq(ENET_Type *ptr); -hpm_stat_t board_enet_disable_irq(ENET_Type *ptr); +hpm_stat_t board_enable_enet_irq(ENET_Type *ptr); +hpm_stat_t board_disable_enet_irq(ENET_Type *ptr); /* * @brief Initialize PMP and PMA for but not limited to the following purposes: * -- non-cacheable memory initialization @@ -398,6 +478,14 @@ void board_ungate_mchtmr_at_lp_mode(void); /* Initialize the UART clock */ uint32_t board_init_uart_clock(UART_Type *ptr); +uint32_t board_init_pwm_clock(PWM_Type *ptr); + +/* + * Get GPIO pin level of onboard LED + */ +uint8_t board_get_led_gpio_off_level(void); + +void board_sd_power_switch(SDXC_Type *ptr, bool on_off); #if defined(__cplusplus) } #endif /* __cplusplus */ diff --git a/bsp/hpmicro/hpm6300evk/board/fal_cfg.h b/bsp/hpmicro/hpm6300evk/board/fal_cfg.h index e5121f56d36..323244ac49b 100644 --- a/bsp/hpmicro/hpm6300evk/board/fal_cfg.h +++ b/bsp/hpmicro/hpm6300evk/board/fal_cfg.h @@ -27,6 +27,13 @@ extern struct fal_flash_dev nor_flash0; /* ====================== Partition Configuration ========================== */ #ifdef FAL_PART_HAS_TABLE_CFG /* partition table */ +#ifdef CONFIG_WEBNET_FAL_FS +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WORD, "app", NOR_FLASH_DEV_NAME, 0, 6*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "fs", NOR_FLASH_DEV_NAME, 6*1024*1024, 10*1024*1024, 0}, \ +} +#else #define FAL_PART_TABLE \ { \ {FAL_PART_MAGIC_WORD, "app", NOR_FLASH_DEV_NAME, 0, 4*1024*1024, 0}, \ @@ -34,6 +41,7 @@ extern struct fal_flash_dev nor_flash0; {FAL_PART_MAGIC_WORD, "download", NOR_FLASH_DEV_NAME, 7*1024*1024, 8*1024*1024, 0}, \ {FAL_PART_MAGIC_WORD, "flashdb", NOR_FLASH_DEV_NAME, 15*1024*1024, 1*1024*1024, 0}, \ } +#endif #endif /* FAL_PART_HAS_TABLE_CFG */ #endif /* RT_USING_FAL */ diff --git a/bsp/hpmicro/hpm6300evk/board/linker_scripts/flash_rtt.ld b/bsp/hpmicro/hpm6300evk/board/linker_scripts/flash_rtt.ld index 4b534d16aca..0dcd2dc040f 100644 --- a/bsp/hpmicro/hpm6300evk/board/linker_scripts/flash_rtt.ld +++ b/bsp/hpmicro/hpm6300evk/board/linker_scripts/flash_rtt.ld @@ -141,6 +141,12 @@ SECTIONS /* RT-Thread related sections - end */ + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + } > XPI0 .rel : { diff --git a/bsp/hpmicro/hpm6300evk/board/linker_scripts/flash_rtt_enet.ld b/bsp/hpmicro/hpm6300evk/board/linker_scripts/flash_rtt_enet.ld new file mode 100644 index 00000000000..41339193998 --- /dev/null +++ b/bsp/hpmicro/hpm6300evk/board/linker_scripts/flash_rtt_enet.ld @@ -0,0 +1,330 @@ +/* + * Copyright 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 128K; +FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 128K; +SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE + ILM (wx) : ORIGIN = 0, LENGTH = 128K + DLM (w) : ORIGIN = 0x80000, LENGTH = 128K + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 384K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x10E0000, LENGTH = NONCACHEABLE_SIZE + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + + . = ALIGN(8); + __vector_ram_end__ = .; + } > AXI_SRAM + + .fast : AT(etext + __data_end__ - __tdata_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + + /* RT-Thread Core Start */ + KEEP(*context_gcc.o(.text* .rodata*)) + KEEP(*port*.o (.text .text* .rodata .rodata*)) + KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) + KEEP(*trap_common.o (.text .text* .rodata .rodata*)) + KEEP(*irq.o (.text .text* .rodata .rodata*)) + KEEP(*clock.o (.text .text* .rodata .rodata*)) + KEEP(*kservice.o (.text .text* .rodata .rodata*)) + KEEP(*scheduler*.o (.text .text* .rodata .rodata*)) + KEEP(*trap*.o (.text .text* .rodata .rodata*)) + KEEP(*idle.o (.text .text* .rodata .rodata*)) + KEEP(*ipc.o (.text .text* .rodata .rodata*)) + KEEP(*slab.o (.text .text* .rodata .rodata*)) + KEEP(*thread.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*timer.o (.text .text* .rodata .rodata*)) + KEEP(*mem.o (.text .text* .rodata .rodata*)) + KEEP(*memheap.o (.text .text* .rodata .rodata*)) + KEEP(*mempool.o (.text .text* .rodata .rodata*)) + /* RT-Thread Core End */ + + /* HPMicro Driver Wrapper */ + KEEP(*drv_*.o (.text .text* .rodata .rodata*)) + KEEP(*api_lib*.o (.text .text* .rodata .rodata*)) + KEEP(*api_msg*.o (.text .text* .rodata .rodata*)) + KEEP(*if_api*.o (.text .text* .rodata .rodata*)) + KEEP(*netbuf*.o (.text .text* .rodata .rodata*)) + KEEP(*netdb*.o (.text .text* .rodata .rodata*)) + KEEP(*netifapi*.o (.text .text* .rodata .rodata*)) + KEEP(*sockets*.o (.text .text* .rodata .rodata*)) + KEEP(*tcpip*.o (.text .text* .rodata .rodata*)) + KEEP(*inet_chksum*.o (.text .text* .rodata .rodata*)) + KEEP(*ip*.o (.text .text* .rodata .rodata*)) + KEEP(*memp*.o (.text .text* .rodata .rodata*)) + KEEP(*netif*.o (.text .text* .rodata .rodata*)) + KEEP(*pbuf*.o (.text .text* .rodata .rodata*)) + KEEP(*tcp_in*.o (.text .text* .rodata .rodata*)) + KEEP(*tcp_out*.o (.text .text* .rodata .rodata*)) + KEEP(*tcp*.o (.text .text* .rodata .rodata*)) + KEEP(*ethernet*.o (.text .text* .rodata .rodata*)) + KEEP(*ethernetif*.o (.text .text* .rodata .rodata*)) + + . = ALIGN(8); + __ramfunc_end__ = .; + } > AXI_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + /* Note: the .tbss and .tdata section should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > AXI_SRAM + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > AXI_SRAM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + + .heap(NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE( __rt_rvstack = . ); + } > AXI_SRAM + + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + + .sdram (NOLOAD) : { + . = ALIGN(8); + __sdram_start__ = .; + . += SDRAM_SIZE; + __sdram_end__ = .; + } > SDRAM +} diff --git a/bsp/hpmicro/hpm6300evk/board/linker_scripts/flash_sdram_rtt.ld b/bsp/hpmicro/hpm6300evk/board/linker_scripts/flash_sdram_rtt.ld index d2cfd45a7b4..4197cc4fe10 100644 --- a/bsp/hpmicro/hpm6300evk/board/linker_scripts/flash_sdram_rtt.ld +++ b/bsp/hpmicro/hpm6300evk/board/linker_scripts/flash_sdram_rtt.ld @@ -141,6 +141,12 @@ SECTIONS /* RT-Thread related sections - end */ + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + } > XPI0 .rel : { diff --git a/bsp/hpmicro/hpm6300evk/board/linker_scripts/ram_rtt.ld b/bsp/hpmicro/hpm6300evk/board/linker_scripts/ram_rtt.ld index da0acc5499c..af3b9df8d72 100644 --- a/bsp/hpmicro/hpm6300evk/board/linker_scripts/ram_rtt.ld +++ b/bsp/hpmicro/hpm6300evk/board/linker_scripts/ram_rtt.ld @@ -87,6 +87,12 @@ SECTIONS /* RT-Thread related sections - end */ + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); @@ -225,10 +231,6 @@ SECTIONS KEEP(*(.backup_sram)) } > APB_SRAM - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - .stack(NOLOAD) : { . = ALIGN(8); __stack_base__ = .; diff --git a/bsp/hpmicro/hpm6300evk/board/linker_scripts/ram_sdram_rtt.ld b/bsp/hpmicro/hpm6300evk/board/linker_scripts/ram_sdram_rtt.ld index 90a92d556cc..3c584f46e16 100644 --- a/bsp/hpmicro/hpm6300evk/board/linker_scripts/ram_sdram_rtt.ld +++ b/bsp/hpmicro/hpm6300evk/board/linker_scripts/ram_sdram_rtt.ld @@ -87,6 +87,12 @@ SECTIONS /* RT-Thread related sections - end */ + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); @@ -225,10 +231,6 @@ SECTIONS KEEP(*(.backup_sram)) } > APB_SRAM - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - .stack(NOLOAD) : { . = ALIGN(8); __stack_base__ = .; diff --git a/bsp/hpmicro/hpm6300evk/board/pinmux.c b/bsp/hpmicro/hpm6300evk/board/pinmux.c index 1f1f8d772d0..86d4008e184 100644 --- a/bsp/hpmicro/hpm6300evk/board/pinmux.c +++ b/bsp/hpmicro/hpm6300evk/board/pinmux.c @@ -20,8 +20,8 @@ void init_uart_pins(UART_Type *ptr) HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART0_RXD; HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART0_TXD; /* PY port IO needs to configure PIOC */ - HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_SOC_PY_07; - HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_SOC_PY_06; + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = PIOC_PY07_FUNC_CTL_SOC_PY_07; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = PIOC_PY06_FUNC_CTL_SOC_PY_06; } else if (ptr == HPM_UART1) { HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_UART1_TXD; HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_UART1_RXD; @@ -29,8 +29,20 @@ void init_uart_pins(UART_Type *ptr) HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_UART2_TXD; HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_UART2_RXD; } else if (ptr == HPM_PUART) { - HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_PUART_RXD; - HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_PUART_TXD; + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = PIOC_PY07_FUNC_CTL_PUART_RXD; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = PIOC_PY06_FUNC_CTL_PUART_TXD; + } +} + +void init_uart_pin_as_gpio(UART_Type *ptr) +{ + if (ptr == HPM_UART2) { + /* pull-up */ + HPM_IOC->PAD[IOC_PAD_PC26].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PC27].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + + HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_GPIO_C_26; + HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_GPIO_C_27; } } @@ -113,6 +125,43 @@ void init_sdram_pins(void) HPM_IOC->PAD[IOC_PAD_PB31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); } +void init_sram_pins(void) +{ + /* Non-MUX */ /* MUX */ + HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A0 */ /* A16 */ + HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A1 */ /* A17 */ + HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A2 */ /* A18 */ + HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A3 */ /* A19 */ + HPM_IOC->PAD[IOC_PAD_PB31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A4 */ /* A20 */ + HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A5 */ /* A21 */ + HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A6 */ /* A22 */ + HPM_IOC->PAD[IOC_PAD_PB28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A7 */ /* A23 */ + + HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D0 */ /* AD0 */ + HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D1 */ /* AD1 */ + HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D2 */ /* AD2 */ + HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D3 */ /* AD3 */ + HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D4 */ /* AD4 */ + HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D5 */ /* AD5 */ + HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D6 */ /* AD6 */ + HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D7 */ /* AD7 */ + HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D8 */ /* AD8 */ + HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D9 */ /* AD9 */ + HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D10 */ /* AD10 */ + HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D11 */ /* AD11 */ + HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D12 */ /* AD12 */ + HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D13 */ /* AD13 */ + HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D14 */ /* AD14 */ + HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D15 */ /* AD15 */ + + HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #CE */ + HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #OE */ + HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #WE */ + HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #UB */ + HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #LB */ + HPM_IOC->PAD[IOC_PAD_PB16].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #ADV */ +} + void init_gpio_pins(void) { /* configure pad setting: pull enable and pull up, schmitt trigger enable */ @@ -124,7 +173,7 @@ void init_gpio_pins(void) HPM_IOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_GPIO_Z_02; HPM_IOC->PAD[IOC_PAD_PZ02].PAD_CTL = pad_ctl; /* PZ port IO needs to configure BIOC as well */ - HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_SOC_PZ_02; + HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = BIOC_PZ02_FUNC_CTL_SOC_PZ_02; #endif } @@ -138,9 +187,21 @@ void init_spi_pins(SPI_Type *ptr) } } +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + if (ptr == HPM_SPI3) { + HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PC18_FUNC_CTL_GPIO_C_18; + HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_SPI3_MOSI; + HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_SPI3_MISO; + HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PC20_FUNC_CTL_SPI3_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + } +} + void init_pins(void) { - init_uart_pins(BOARD_CONSOLE_BASE); +#ifdef BOARD_CONSOLE_UART_BASE + init_uart_pins(BOARD_CONSOLE_UART_BASE); +#endif init_sdram_pins(); } @@ -149,6 +210,7 @@ void init_gptmr_pins(GPTMR_Type *ptr) if (ptr == HPM_GPTMR2) { HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_GPTMR2_CAPT_0; HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_GPTMR2_COMP_0; + HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PC09_FUNC_CTL_GPTMR2_COMP_1; } } @@ -167,8 +229,8 @@ void init_qei_trgm_pins(void) void init_butn_pins(void) { - // HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_PBUTN; - // HPM_BIOC->PAD[IOC_PAD_PZ03].FUNC_CTL = IOC_PZ03_FUNC_CTL_WBUTN; + /* HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = BIOC_PZ02_FUNC_CTL_PBUTN; */ + /* HPM_BIOC->PAD[IOC_PAD_PZ03].FUNC_CTL = BIOC_PZ03_FUNC_CTL_WBUTN; */ } void init_acmp_pins(void) @@ -211,7 +273,7 @@ void init_pwm_pins(PWM_Type *ptr) void init_adc_pins(void) { - HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; @@ -236,54 +298,65 @@ void init_can_pins(CAN_Type *ptr) HPM_IOC->PAD[IOC_PAD_PZ04].FUNC_CTL = IOC_PZ04_FUNC_CTL_CAN1_TXD; HPM_IOC->PAD[IOC_PAD_PZ05].FUNC_CTL = IOC_PZ05_FUNC_CTL_CAN1_RXD; /* PZ port IO needs to configure BIOC as well */ - HPM_BIOC->PAD[IOC_PAD_PZ04].FUNC_CTL = IOC_PZ04_FUNC_CTL_SOC_PZ_04; - HPM_BIOC->PAD[IOC_PAD_PZ05].FUNC_CTL = IOC_PZ05_FUNC_CTL_SOC_PZ_05; + HPM_BIOC->PAD[IOC_PAD_PZ04].FUNC_CTL = BIOC_PZ04_FUNC_CTL_SOC_PZ_04; + HPM_BIOC->PAD[IOC_PAD_PZ05].FUNC_CTL = BIOC_PZ05_FUNC_CTL_SOC_PZ_05; } } -void init_sdxc_power_pin(SDXC_Type *ptr) +void init_sdxc_cmd_pin(SDXC_Type *ptr, bool open_drain, bool is_1v8) { - -} - -void init_sdxc_vsel_pin(SDXC_Type *ptr) -{ - + (void) is_1v8; + if (ptr == HPM_SDXC0) { + uint32_t cmd_func_ctl = IOC_PA10_FUNC_CTL_SDC0_CMD | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + uint32_t cmd_pad_ctl = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + if (open_drain) { + cmd_pad_ctl |= IOC_PAD_PAD_CTL_OD_MASK; + } + /* SDXC0.CMD */ + HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = cmd_func_ctl; + HPM_IOC->PAD[IOC_PAD_PA10].PAD_CTL = cmd_pad_ctl; + } } -void init_sdxc_card_detection_pin(SDXC_Type *ptr) +void init_sdxc_cd_pin(SDXC_Type *ptr, bool as_gpio) { - /* SDXC0.CD */ - HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); - HPM_IOC->PAD[IOC_PAD_PA14].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + if (ptr == HPM_SDXC0) { + uint32_t cd_func_alt = as_gpio ? IOC_PA14_FUNC_CTL_GPIO_A_14 : IOC_PA14_FUNC_CTL_SDC0_CDN; + uint32_t cd_pad_ctl = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + /* SDXC0.CD */ + HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = cd_func_alt; + HPM_IOC->PAD[IOC_PAD_PA14].PAD_CTL = cd_pad_ctl; + } } -void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8) +void init_sdxc_clk_data_pins(SDXC_Type *ptr, uint32_t width, bool is_1v8) { - uint32_t func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); - uint32_t clk_pad_ctl = IOC_PAD_PAD_CTL_DS_SET(7); - uint32_t pad_ctl = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); - - /* SDXC0.CLK */ - HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = func_ctl; - HPM_IOC->PAD[IOC_PAD_PA11].PAD_CTL = clk_pad_ctl; - - /* SDXC0.CMD */ - HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = func_ctl; - HPM_IOC->PAD[IOC_PAD_PA10].PAD_CTL = pad_ctl; - - /* SDXC0.DATA0 */ - HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = func_ctl; - HPM_IOC->PAD[IOC_PAD_PA12].PAD_CTL = pad_ctl; - /* SDXC0.DATA1 */ - HPM_IOC->PAD[IOC_PAD_PA13].FUNC_CTL = func_ctl; - HPM_IOC->PAD[IOC_PAD_PA13].PAD_CTL = pad_ctl; - /* SDXC0.DATA2 */ - HPM_IOC->PAD[IOC_PAD_PA08].FUNC_CTL = func_ctl; - HPM_IOC->PAD[IOC_PAD_PA08].PAD_CTL = pad_ctl; - /* SDXC0.DATA3 */ - HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = func_ctl; - HPM_IOC->PAD[IOC_PAD_PA09].PAD_CTL = pad_ctl; + (void) is_1v8; + if (ptr == HPM_SDXC0) { + uint32_t func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + uint32_t clk_pad_ctl = IOC_PAD_PAD_CTL_DS_SET(7); + uint32_t pad_ctl = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + + /* SDXC0.CLK */ + HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PA11].PAD_CTL = clk_pad_ctl; + + /* SDXC0.DATA0 */ + HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PA12].PAD_CTL = pad_ctl; + + if (width == 4) { + /* SDXC0.DATA1 */ + HPM_IOC->PAD[IOC_PAD_PA13].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PA13].PAD_CTL = pad_ctl; + /* SDXC0.DATA2 */ + HPM_IOC->PAD[IOC_PAD_PA08].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PA08].PAD_CTL = pad_ctl; + /* SDXC0.DATA3 */ + HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PA09].PAD_CTL = pad_ctl; + } + } } void init_clk_obs_pins(void) @@ -312,3 +385,15 @@ void init_trgmux_pins(uint32_t pin) /* all trgmux pin ALT_SELECT fixed to 16*/ HPM_IOC->PAD[pin].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16); } + +void init_enet_pps_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_ETH0_EVTO_0; + HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PC20_FUNC_CTL_ETH0_EVTO_1; +} + +void init_tamper_pins(void) +{ + HPM_BIOC->PAD[IOC_PAD_PZ06].FUNC_CTL = BIOC_PZ06_FUNC_CTL_TAMP_06 | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_BIOC->PAD[IOC_PAD_PZ07].FUNC_CTL = BIOC_PZ07_FUNC_CTL_TAMP_07; +} diff --git a/bsp/hpmicro/hpm6300evk/board/pinmux.h b/bsp/hpmicro/hpm6300evk/board/pinmux.h index 5dd98741cf6..1f4061bd92b 100644 --- a/bsp/hpmicro/hpm6300evk/board/pinmux.h +++ b/bsp/hpmicro/hpm6300evk/board/pinmux.h @@ -12,10 +12,13 @@ extern "C" { #endif void init_uart_pins(UART_Type *ptr); +void init_uart_pin_as_gpio(UART_Type *ptr); void init_i2c_pins(I2C_Type *ptr); void init_sdram_pins(void); +void init_sram_pins(void); void init_gpio_pins(void); void init_spi_pins(SPI_Type *ptr); +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); void init_pins(void); void init_gptmr_pins(GPTMR_Type *ptr); void init_hall_trgm_pins(void); @@ -24,19 +27,21 @@ void init_butn_pins(void); void init_acmp_pins(void); void init_enet_pins(ENET_Type *ptr); void init_pwm_pins(PWM_Type *ptr); +void init_sdxc_cmd_pin(SDXC_Type *ptr, bool open_drain, bool is_1v8); +void init_sdxc_cd_pin(SDXC_Type *ptr, bool as_gpio); +void init_sdxc_clk_data_pins(SDXC_Type *ptr, uint32_t width, bool is_1v8); void init_adc_pins(void); void init_dac_pins(DAC_Type *ptr); void init_usb_pins(void); void init_can_pins(CAN_Type *ptr); -void init_sdxc_power_pin(SDXC_Type *ptr); -void init_sdxc_vsel_pin(SDXC_Type *ptr); -void init_sdxc_card_detection_pin(SDXC_Type *ptr); -void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8); void init_adc_bldc_pins(void); void init_rgb_pwm_pins(void); void init_i2c_pins_as_gpio(I2C_Type *ptr); void init_led_pins(void); void init_trgmux_pins(uint32_t pin); +void init_enet_pps_pins(void); +void init_tamper_pins(void); + #ifdef __cplusplus } #endif diff --git a/bsp/hpmicro/hpm6300evk/board/rtt_board.c b/bsp/hpmicro/hpm6300evk/board/rtt_board.c index b28ce90a065..3d7a94356e7 100644 --- a/bsp/hpmicro/hpm6300evk/board/rtt_board.c +++ b/bsp/hpmicro/hpm6300evk/board/rtt_board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2024 HPMicro * SPDX-License-Identifier: BSD-3-Clause * */ @@ -8,18 +8,34 @@ #include "rtt_board.h" #include "hpm_uart_drv.h" #include "hpm_gpio_drv.h" -#include "hpm_mchtmr_drv.h" #include "hpm_pmp_drv.h" #include "assert.h" #include "hpm_clock_drv.h" #include "hpm_sysctl_drv.h" #include #include -#include "hpm_dma_manager.h" +#include "hpm_dma_mgr.h" +#include "hpm_mchtmr_drv.h" +extern int rt_hw_uart_init(void); void os_tick_config(void); +void rtt_board_init(void); -extern int rt_hw_uart_init(void); +void rt_hw_board_init(void) +{ + rtt_board_init(); + + /* Call the RT-Thread Component Board Initialization */ + rt_components_board_init(); +} + +void os_tick_config(void) +{ + sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1); + sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0); + mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND); + enable_mchtmr_irq(); +} void rtt_board_init(void) { @@ -27,7 +43,7 @@ void rtt_board_init(void) board_init_console(); board_init_pmp(); - dma_manager_init(); + dma_mgr_init(); /* initialize memory system */ rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); @@ -67,24 +83,6 @@ void BOARD_LED_write(uint32_t index, bool state) } } -void os_tick_config(void) -{ - sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1); - sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0); - - mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND); - - enable_mchtmr_irq(); -} - -void rt_hw_board_init(void) -{ - rtt_board_init(); - - /* Call the RT-Thread Component Board Initialization */ - rt_components_board_init(); -} - void rt_hw_console_output(const char *str) { while (*str != '\0') @@ -93,18 +91,16 @@ void rt_hw_console_output(const char *str) } } +void app_init_usb_pins(void) +{ + board_init_usb_pins(); +} + ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) { HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND; - rt_interrupt_enter(); rt_tick_increase(); - rt_interrupt_leave(); -} - -void rt_hw_us_delay(rt_uint32_t us) -{ - clock_cpu_delay_us(us); } void rt_hw_cpu_reset(void) diff --git a/bsp/hpmicro/hpm6300evk/board/rtt_board.h b/bsp/hpmicro/hpm6300evk/board/rtt_board.h index c86742e8336..16f539bc628 100644 --- a/bsp/hpmicro/hpm6300evk/board/rtt_board.h +++ b/bsp/hpmicro/hpm6300evk/board/rtt_board.h @@ -23,6 +23,15 @@ /* CAN section */ #define BOARD_CAN_NAME "can0" +#define BOARD_CAN_HWFILTER_INDEX (0U) + +/* UART section */ +#define BOARD_UART_NAME "uart2" +#define BOARD_UART_RX_BUFFER_SIZE BSP_UART2_RX_BUFSIZE + +#define BOARD_SD_NAME "sd0" + +#define IRQn_PendSV IRQn_DEBUG_0 /*************************************************************** * @@ -44,7 +53,7 @@ typedef struct { void app_init_led_pins(void); void app_led_write(uint32_t index, bool state); - +void app_init_usb_pins(void); #if defined(__cplusplus) extern "C" { diff --git a/bsp/hpmicro/hpm6300evk/rtconfig.py b/bsp/hpmicro/hpm6300evk/rtconfig.py index 45a1fbff7a7..2173a8fb05f 100644 --- a/bsp/hpmicro/hpm6300evk/rtconfig.py +++ b/bsp/hpmicro/hpm6300evk/rtconfig.py @@ -81,8 +81,8 @@ LFLAGS += ' -O0' LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' elif BUILD == 'ram_release': - CFLAGS += ' -O2 -Os' - LFLAGS += ' -O2 -Os' + CFLAGS += ' -O2' + LFLAGS += ' -O2' LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' elif BUILD == 'flash_debug': CFLAGS += ' -gdwarf-2' @@ -92,13 +92,13 @@ CFLAGS += ' -DFLASH_XIP=1' LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' elif BUILD == 'flash_release': - CFLAGS += ' -O2 -Os' - LFLAGS += ' -O2 -Os' + CFLAGS += ' -O2' + LFLAGS += ' -O2' CFLAGS += ' -DFLASH_XIP=1' LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' else: - CFLAGS += ' -O2 -Os' - LFLAGS += ' -O2 -Os' + CFLAGS += ' -O2' + LFLAGS += ' -O2' LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' LFLAGS += ' -T ' + LINKER_FILE diff --git a/bsp/hpmicro/hpm6300evk/startup/HPM6360/toolchains/gcc/start.S b/bsp/hpmicro/hpm6300evk/startup/HPM6360/toolchains/gcc/start.S index 6c8798ab1a1..fdc2052aa31 100644 --- a/bsp/hpmicro/hpm6300evk/startup/HPM6360/toolchains/gcc/start.S +++ b/bsp/hpmicro/hpm6300evk/startup/HPM6360/toolchains/gcc/start.S @@ -19,6 +19,15 @@ _start: la tp, __thread_pointer .option pop +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + #ifdef INIT_EXT_RAM_FOR_DATA la t0, _stack_in_dlm mv sp, t0 diff --git a/bsp/hpmicro/hpm6750evk/README.md b/bsp/hpmicro/hpm6750evk/README.md index c5d789a8a61..e0b34306cff 100644 --- a/bsp/hpmicro/hpm6750evk/README.md +++ b/bsp/hpmicro/hpm6750evk/README.md @@ -51,7 +51,7 @@ The BSP support being build via the 'scons' command, below is the steps of compi - Download the package and extract it into a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain` - Step 3: Set environment variable `RTT_RISCV_TOOLCHAIN` to `\bin` - For example: `C:\DevTools\riscv32-gnu-toolchain\bin` -- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip) +- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip) - Download and extract it to specified directory, for example: `C:\DevTools\openocd-hpmicro` - Add `OpenOCD` environment variable `OPENOCD_HPMICRO` to `\bin` - For example: `C:\DevTools\openocd-hpmicro\bin` diff --git a/bsp/hpmicro/hpm6750evk/README_zh.md b/bsp/hpmicro/hpm6750evk/README_zh.md index f58ebf295ac..9d8effddaf7 100644 --- a/bsp/hpmicro/hpm6750evk/README_zh.md +++ b/bsp/hpmicro/hpm6750evk/README_zh.md @@ -53,7 +53,7 @@ HPM6750EVK 是由先楫半导体推出的一款基于RISCV内核的开发板， - 步骤 2: 准备 [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) - 下载并解压到指定的目录，如: `C:\DevTools\riscv32-gnu-toolchain` - 步骤 3: 设置环境变量： `RTT_RISCV_TOOLCHAIN` 为 `\bin`， 如: `C:\DevTools\riscv32-gnu-toolchain\bin` -- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip) +- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip) - 下载并解压到指定目录，如: `C:\DevTools\openocd-hpmicro` - 将 `OPENOCD_HPMICRO`环境变量设置为 `\bin`，如： `C:\DevTools\openocd-hpmicro\bin` diff --git a/bsp/hpmicro/hpm6750evk/board/Kconfig b/bsp/hpmicro/hpm6750evk/board/Kconfig index 651d2de16a9..32738cf5d9a 100644 --- a/bsp/hpmicro/hpm6750evk/board/Kconfig +++ b/bsp/hpmicro/hpm6750evk/board/Kconfig @@ -7,6 +7,14 @@ config SOC_HPM6000 select RT_USING_USER_MAIN default y +config BSP_USING_ENET_PHY_DP83867 + bool + default n + +config BSP_USING_ENET_PHY_DP83848 + bool + default n + menu "On-chip Peripheral Drivers" config BSP_USING_GPIO bool "Enable GPIO" @@ -27,37 +35,22 @@ menu "On-chip Peripheral Drivers" bool "Enable UART0 RX DMA" depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA default n - config BSP_UART0_TX_USING_DMA bool "Enable UART0 TX DMA" depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA default n - - config BSP_UART0_RX_DMA_CHANNEL - int "Set UART0 RX DMA CHANNEL" - range 0 7 - depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA - default 0 - - config BSP_UART0_TX_DMA_CHANNEL - int "Set UART0 TX DMA CHANNEL" - range 0 7 - depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA - default 1 - config BSP_UART0_RX_BUFSIZE int "Set UART0 RX buffer size" range 64 65535 depends on RT_USING_SERIAL_V2 default 128 - config BSP_UART0_TX_BUFSIZE int "Set UART0 TX buffer size" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 endif - menuconfig BSP_USING_UART6 + menuconfig BSP_USING_UART6 bool "Enable UART6" default n if BSP_USING_UART6 @@ -70,70 +63,41 @@ menu "On-chip Peripheral Drivers" bool "Enable UART6 TX DMA" depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA default n - - config BSP_UART6_RX_DMA_CHANNEL - int "Set UART6 RX DMA CHANNEL" - range 0 7 - depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA - default 0 - - config BSP_UART6_TX_DMA_CHANNEL - int "Set UART6 TX DMA CHANNEL" - range 0 7 - depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA - default 1 - config BSP_UART6_RX_BUFSIZE int "Set UART6 RX buffer size" range 64 65535 depends on RT_USING_SERIAL_V2 default 128 - config BSP_UART6_TX_BUFSIZE int "Set UART6 TX buffer size" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 endif - menuconfig BSP_USING_UART13 + menuconfig BSP_USING_UART13 bool "Enable UART13" - default n + default y if BSP_USING_UART13 config BSP_UART13_RX_USING_DMA bool "Enable UART13 RX DMA" depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA default n - config BSP_UART13_TX_USING_DMA bool "Enable UART13 TX DMA" depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA default n - - config BSP_UART13_RX_DMA_CHANNEL - int "Set UART13 RX DMA CHANNEL" - range 0 7 - depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA - default 0 - - config BSP_UART13_TX_DMA_CHANNEL - int "Set UART13 TX DMA CHANNEL" - range 0 7 - depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA - default 1 - config BSP_UART13_RX_BUFSIZE int "Set UART13 RX buffer size" range 64 65535 depends on RT_USING_SERIAL_V2 default 128 - config BSP_UART13_TX_BUFSIZE int "Set UART13 TX buffer size" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 endif - menuconfig BSP_USING_UART14 + menuconfig BSP_USING_UART14 bool "Enable UART14" default n if BSP_USING_UART14 @@ -141,30 +105,15 @@ menu "On-chip Peripheral Drivers" bool "Enable UART14 RX DMA" depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA default n - config BSP_UART14_TX_USING_DMA bool "Enable UART14 TX DMA" depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA default n - - config BSP_UART14_RX_DMA_CHANNEL - int "Set UART14 RX DMA CHANNEL" - range 0 7 - depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA - default 0 - - config BSP_UART14_TX_DMA_CHANNEL - int "Set UART14 TX DMA CHANNEL" - range 0 7 - depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA - default 1 - config BSP_UART14_RX_BUFSIZE int "Set UART14 RX buffer size" range 64 65535 depends on RT_USING_SERIAL_V2 default 128 - config BSP_UART14_TX_BUFSIZE int "Set UART14 TX buffer size" range 0 65535 @@ -182,13 +131,28 @@ menu "On-chip Peripheral Drivers" if BSP_USING_SPI config BSP_USING_SPI1 bool "Enable SPI1" - default y + default y + if BSP_USING_SPI1 + config BSP_SPI1_USING_DMA + bool "Enable SPI1 DMA" + default n + endif config BSP_USING_SPI2 bool "Enable SPI2" + default n + if BSP_USING_SPI2 + config BSP_SPI2_USING_DMA + bool "Enable SPI2 DMA" default n + endif config BSP_USING_SPI3 bool "Enable SPI3" + default n + if BSP_USING_SPI3 + config BSP_SPI3_USING_DMA + bool "Enable SPI3 DMA" default n + endif endif menuconfig BSP_USING_RTC @@ -201,14 +165,15 @@ menu "On-chip Peripheral Drivers" select RT_USING_ETH if BSP_USING_ETH - choice - prompt "ETH" - config BSP_USING_ETH0 - bool "Enable ETH0" - - config BSP_USING_ETH1 - bool "Enable ETH1" - endchoice + config BSP_USING_ETH0 + bool "Enable ETH0" + default y + select BSP_USING_ENET_PHY_DP83867 + + config BSP_USING_ETH1 + bool "Enable ETH1" + default n + select BSP_USING_ENET_PHY_DP83848 endif menuconfig BSP_USING_SDXC @@ -218,11 +183,65 @@ menu "On-chip Peripheral Drivers" if BSP_USING_SDXC config BSP_USING_SDXC0 bool "Enable SDXC0" - default n + default n + if BSP_USING_SDXC0 + choice + prompt "Select BUS_WIDTH" + default BSP_SDXC0_BUS_WIDTH_8BIT + config BSP_SDXC0_BUS_WIDTH_1BIT + bool "1-bit" + config BSP_SDXC0_BUS_WIDTH_4BIT + bool "4-bit" + config BSP_SDXC0_BUS_WIDTH_8BIT + bool "8-bit" + endchoice + choice + prompt "Select Voltage" + default BSP_SDXC0_VOLTAGE_3V3 + config BSP_SDXC0_VOLTAGE_3V3 + bool "3.3V" + config BSP_SDXC0_VOLTAGE_1V8 + bool "1.8V" + config BSP_SDXC0_VOLTAGE_DUAL + bool "Dual voltage 3.3V / 1.8V" + endchoice + config BSP_SDXC0_VSEL_PIN + default "None" + string "VSEL pin name" + config BSP_SDXC0_PWR_PIN + default "None" + string "PWR pin name" + endif config BSP_USING_SDXC1 bool "Enable SDXC1" - default y + default n + if BSP_USING_SDXC1 + choice + prompt "Select BUS_WIDTH" + default BSP_SDXC1_BUS_WIDTH_4BIT + config BSP_SDXC1_BUS_WIDTH_1BIT + bool "1-bit" + config BSP_SDXC1_BUS_WIDTH_4BIT + bool "4-bit" + endchoice + choice + prompt "Select Voltage" + default BSP_SDXC1_VOLTAGE_3V3 + config BSP_SDXC1_VOLTAGE_3V3 + bool "3.3V" + config BSP_SDXC1_VOLTAGE_1V8 + bool "1.8V" + config BSP_SDXC1_VOLTAGE_DUAL + bool "Dual voltage 3.3V / 1.8V" + endchoice + config BSP_SDXC1_VSEL_PIN + default "None" + string "VSEL pin name" + config BSP_SDXC1_PWR_PIN + default "None" + string "PWR pin name" + endif endif menuconfig BSP_USING_TOUCH @@ -231,16 +250,21 @@ menu "On-chip Peripheral Drivers" if BSP_USING_TOUCH config BSP_USING_TOUCH_GT911 bool "Enable GT911" - default y + default y config BSP_USING_TOUCH_FT5406 bool "Enable FT5406" - default n + default n endif menuconfig BSP_USING_LCD bool "Enable LCD" default n + if BSP_USING_LCD + config BSP_USING_LCD_ISR + bool "Enable LCD interrupt" + default n + endif menuconfig BSP_USING_LVGL bool "Enable LVGL" @@ -287,7 +311,12 @@ menu "On-chip Peripheral Drivers" if BSP_USING_I2C config BSP_USING_I2C0 bool "Enable I2C0" - default y + default y + endif + if BSP_USING_I2C0 + config BSP_I2C0_USING_DMA + bool "Enable I2C0 DMA" + default n endif menuconfig BSP_USING_FEMC @@ -300,12 +329,12 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_XPI_FLASH bool "Enable XPI FLASH" - default n - select PKG_USING_FAL if BSP_USING_XPI_FLASH + default n + select RT_USING_FAL if BSP_USING_XPI_FLASH menuconfig BSP_USING_PWM bool "Enable PWM" - default n + default n menuconfig BSP_USING_DAO bool "Enable Audio DAO play" @@ -324,7 +353,10 @@ menu "On-chip Peripheral Drivers" if BSP_USING_I2S config BSP_USING_I2S0 bool "Enable I2S0" - default y + default y + config BSP_USING_AUDIO_CODEC_SGTL5000 + bool "Enable audio codec on board" + default y endif menuconfig BSP_USING_USB @@ -333,14 +365,15 @@ menu "On-chip Peripheral Drivers" if BSP_USING_USB config BSP_USING_USB_DEVICE bool "Enable USB Device" - default n + default n config BSP_USING_USB_HOST bool "Enable USB Host" - default n + select RT_USING_CACHE + default n endif - menuconfig BSP_USING_WDG + menuconfig BSP_USING_WDG bool "Enable Watchdog" default n select RT_USING_WDT if BSP_USING_WDG @@ -359,7 +392,7 @@ menu "On-chip Peripheral Drivers" default n endif - menuconfig BSP_USING_CAN + menuconfig BSP_USING_CAN bool "Enable CAN" default n select RT_USING_CAN if BSP_USING_CAN @@ -376,7 +409,7 @@ menu "On-chip Peripheral Drivers" config BSP_USING_CAN3 bool "Enable CAN3" default n - endif + endif menuconfig BSP_USING_ADC bool "Enable ADC" @@ -384,8 +417,8 @@ menu "On-chip Peripheral Drivers" select RT_USING_ADC if BSP_USING_ADC if BSP_USING_ADC menuconfig BSP_USING_ADC12 - bool "Enable ADC12" - default n + bool "Enable ADC12" + default n if BSP_USING_ADC12 config BSP_USING_ADC0 bool "Enable ADC0" @@ -398,8 +431,8 @@ menu "On-chip Peripheral Drivers" default n endif menuconfig BSP_USING_ADC16 - bool "Enable ADC16" - default n + bool "Enable ADC16" + default n if BSP_USING_ADC16 config BSP_USING_ADC3 bool "Enable ADC3" @@ -407,8 +440,78 @@ menu "On-chip Peripheral Drivers" endif endif + menuconfig BSP_USING_CAMERA + bool "Enable camera" + default n + if BSP_USING_CAMERA + config BSP_USING_CAMERA_MT9M114 + bool "Enable mt9m114" + default y + + config BSP_USING_CAMERA_OV5640 + bool "Enable ov5640" + default n + + config BSP_USING_CAMERA_OV7725 + bool "Enable ov7725" + default n + endif + + menuconfig BSP_USING_JPEG + bool "Enable JPEG Driver" + default n + + menuconfig BSP_USING_CAM + bool "Enable CAM Driver" + default n + + menuconfig BSP_USING_PANEL + bool "Enable panel" + default n + if BSP_USING_PANEL + config BSP_USEING_PANEL_RGB_TM070RDH13 + bool "Enable RGB TM070RDH13" + default y + endif + + menuconfig BSP_USING_RTT_LCD_DRIVER + bool "Enable RTT LCD Driver" + select BSP_USING_LCD + default n + + endmenu +menu "Segger SystemView Config" + config BSP_USING_SYSTEMVIEW + select RT_USING_SYSTEMVIEW + select RT_USING_LEGACY + bool "Enable Segger SystemView" + default n + + if BSP_USING_SYSTEMVIEW + menuconfig BSP_SYSTEMVIEW_RTT_SECTION + bool "enable SystemView RTT section" + default y + if BSP_SYSTEMVIEW_RTT_SECTION + config SEGGER_RTT_SECTION + string "segger rtt section" + default ".noncacheable.bss" + config SEGGER_RTT_BUFFER_SECTION + string "segger rtt buffer section" + default ".noncacheable.bss" + config SEGGER_SYSVIEW_SECTION + string "segger sysview section" + default ".noncacheable.bss" + endif + source "$RTT_DIR/../libraries/misc/systemview/Kconfig" + endif +endmenu +menu "Hpmicro Interrupt Config" + config HPM_USING_VECTOR_PREEMPTED_MODE + bool "Enable Vector and Preempted Mode" + default n +endmenu endmenu diff --git a/bsp/hpmicro/hpm6750evk/board/SConscript b/bsp/hpmicro/hpm6750evk/board/SConscript index b0557f0945c..2124e479bc9 100644 --- a/bsp/hpmicro/hpm6750evk/board/SConscript +++ b/bsp/hpmicro/hpm6750evk/board/SConscript @@ -7,7 +7,6 @@ src = Split(""" board.c rtt_board.c pinmux.c - eth_phy_port.c fal_flash_port.c hpm_sgtl5000.c """) diff --git a/bsp/hpmicro/hpm6750evk/board/board.c b/bsp/hpmicro/hpm6750evk/board/board.c index 1a670403466..8ca397f413c 100644 --- a/bsp/hpmicro/hpm6750evk/board/board.c +++ b/bsp/hpmicro/hpm6750evk/board/board.c @@ -25,6 +25,7 @@ #include "hpm_pcfg_drv.h" static board_timer_cb timer_cb; +static bool invert_led_level; /** * @brief FLASH configuration option definitions: @@ -80,7 +81,7 @@ static board_timer_cb timer_cb; * 0 - 4MB / 1 - 8MB / 2 - 16MB */ #if defined(FLASH_XIP) && FLASH_XIP -__attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90001, 0x00000007, 0x0, 0x0}; +__attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90001, 0x00000007, 0x1000, 0x0}; #endif #if defined(FLASH_UF2) && FLASH_UF2 @@ -89,18 +90,23 @@ ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATU void board_init_console(void) { +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE #if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART console_config_t cfg; + /* uart needs to configure pin function before enabling clock, otherwise the level change of + uart rx pin when configuring pin function will cause a wrong data to be received. + And a uart rx dma request will be generated by default uart fifo dma trigger level. */ + init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE); + /* Configure the UART clock to 24MHz */ - clock_set_source_divider(BOARD_CONSOLE_CLK_NAME, clk_src_osc24m, 1U); + clock_set_source_divider(BOARD_CONSOLE_UART_CLK_NAME, clk_src_osc24m, 1U); + clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0); cfg.type = BOARD_CONSOLE_TYPE; - cfg.base = (uint32_t) BOARD_CONSOLE_BASE; - cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_CLK_NAME); - cfg.baudrate = BOARD_CONSOLE_BAUDRATE; - - init_uart_pins((UART_Type *) cfg.base); + cfg.base = (uint32_t) BOARD_CONSOLE_UART_BASE; + cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_UART_CLK_NAME); + cfg.baudrate = BOARD_CONSOLE_UART_BAUDRATE; if (status_success != console_init(&cfg)) { /* failed to initialize debug console */ @@ -108,7 +114,9 @@ void board_init_console(void) } } #else - while(1); + while (1) { + } +#endif #endif } @@ -138,6 +146,7 @@ void board_print_clock_freq(void) void board_init_uart(UART_Type *ptr) { + /* configure uart's pin before opening uart's clock */ init_uart_pins(ptr); board_init_uart_clock(ptr); } @@ -160,11 +169,17 @@ void board_print_banner(void) $$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\n\ \\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n\ ----------------------------------------------------------------------\n"}; +#ifdef SDK_VERSION_STRING + printf("hpm_sdk: %s\n", SDK_VERSION_STRING); +#endif printf("%s", banner); } static void board_turnoff_rgb_led(void) { + uint8_t p11_stat; + uint8_t p12_stat; + uint8_t p13_stat; uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_GPIO_B_11; HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12; @@ -173,6 +188,23 @@ static void board_turnoff_rgb_led(void) HPM_IOC->PAD[IOC_PAD_PB11].PAD_CTL = pad_ctl; HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = pad_ctl; HPM_IOC->PAD[IOC_PAD_PB13].PAD_CTL = pad_ctl; + + p11_stat = gpio_read_pin(BOARD_G_GPIO_CTRL, GPIO_DI_GPIOB, 11); + p12_stat = gpio_read_pin(BOARD_G_GPIO_CTRL, GPIO_DI_GPIOB, 12); + p13_stat = gpio_read_pin(BOARD_G_GPIO_CTRL, GPIO_DI_GPIOB, 13); + + invert_led_level = false; + /* + * check led gpio level + */ + if ((p11_stat & p12_stat & p13_stat) == 0) { + /* Rev B */ + invert_led_level = true; + pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(0); + HPM_IOC->PAD[IOC_PAD_PB11].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PB13].PAD_CTL = pad_ctl; + } } void board_ungate_mchtmr_at_lp_mode(void) @@ -196,6 +228,12 @@ void board_init(void) #endif } +void board_init_core1(void) +{ + board_init_console(); + board_init_pmp(); +} + void board_init_sdram_pins(void) { init_sdram_pins(); @@ -209,60 +247,107 @@ uint32_t board_init_femc_clock(void) return clock_get_frequency(clock_femc); } -void board_power_cycle_lcd(void) -{ - /* turn off backlight */ - gpio_set_pin_output(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN); - gpio_write_pin(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN, 0); +uint32_t board_lcdc_clock_init(clock_name_t clock_name, uint32_t pixel_clk_khz); - board_delay_ms(150); - /* power recycle */ - gpio_set_pin_output(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN); - gpio_write_pin(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN, 0); - board_delay_ms(150); - gpio_write_pin(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN, 1); - board_delay_ms(150); +#if defined(CONFIG_PANEL_RGB_TM070RDH13) && CONFIG_PANEL_RGB_TM070RDH13 - /* turn on backlight */ - gpio_write_pin(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN, 1); +static void set_reset_pin_level_tm070rdh13(uint8_t level) +{ + gpio_write_pin(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN, level); +} +static void set_backlight_tm070rdh13(uint16_t percent) +{ + gpio_write_pin(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN, percent > 0 ? 1 : 0); } -void board_init_lcd(void) +void board_init_lcd_rgb_tm070rdh13(void) { - board_init_lcd_clock(); init_lcd_pins(BOARD_LCD_BASE); - board_power_cycle_lcd(); + gpio_set_pin_output(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN); + gpio_set_pin_output(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN); + + hpm_panel_hw_interface_t hw_if = {0}; + hpm_panel_t *panel = hpm_panel_find_device_default(); + const hpm_panel_timing_t *timing = hpm_panel_get_timing(panel); + uint32_t lcdc_pixel_clk_khz = board_lcdc_clock_init(clock_display, timing->pixel_clock_khz); + hw_if.set_reset_pin_level = set_reset_pin_level_tm070rdh13; + hw_if.set_backlight = set_backlight_tm070rdh13; + hw_if.lcdc_pixel_clk_khz = lcdc_pixel_clk_khz; + hpm_panel_register_interface(panel, &hw_if); + + printf("name: %s, lcdc_clk: %ukhz\n", + hpm_panel_get_name(panel), + lcdc_pixel_clk_khz); + + hpm_panel_reset(panel); + hpm_panel_init(panel); + hpm_panel_power_on(panel); } -void board_panel_para_to_lcdc(lcdc_config_t *config) +#endif + +#ifdef CONFIG_HPM_PANEL + +uint32_t board_lcdc_clock_init(clock_name_t clock_name, uint32_t pixel_clk_khz) { - const uint16_t panel_timing_para[] = BOARD_PANEL_TIMING_PARA; + clock_add_to_group(clock_name, 0); - config->resolution_x = BOARD_LCD_WIDTH; - config->resolution_y = BOARD_LCD_HEIGHT; + uint32_t freq_khz = clock_get_frequency(clk_pll4clk0) / 1000; + uint32_t div = (freq_khz + pixel_clk_khz / 2) / pixel_clk_khz; + clock_set_source_divider(clock_name, clk_src_pll4_clk0, div); + return clock_get_frequency(clock_name) / 1000; +} - config->hsync.pulse_width = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HSPW_INDEX]; - config->hsync.back_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HBP_INDEX]; - config->hsync.front_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HFP_INDEX]; +void board_lcd_backlight(bool is_on) +{ + hpm_panel_t *panel = hpm_panel_find_device_default(); + hpm_panel_set_backlight(panel, is_on == true ? 100 : 0); +} - config->vsync.pulse_width = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VSPW_INDEX]; - config->vsync.back_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VBP_INDEX]; - config->vsync.front_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VFP_INDEX]; +void board_init_lcd(void) +{ +#ifdef CONFIG_PANEL_RGB_TM070RDH13 + board_init_lcd_rgb_tm070rdh13(); +#endif +} - config->control.invert_hsync = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HSSP_INDEX]; - config->control.invert_vsync = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VSSP_INDEX]; - config->control.invert_href = panel_timing_para[BOARD_PANEL_TIMEING_PARA_DESP_INDEX]; - config->control.invert_pixel_data = panel_timing_para[BOARD_PANEL_TIMEING_PARA_PDSP_INDEX]; - config->control.invert_pixel_clock = panel_timing_para[BOARD_PANEL_TIMEING_PARA_PCSP_INDEX]; +void board_panel_para_to_lcdc(lcdc_config_t *config) +{ + const hpm_panel_timing_t *timing; + hpm_panel_t *panel = hpm_panel_find_device_default(); + + timing = hpm_panel_get_timing(panel); + config->resolution_x = timing->hactive; + config->resolution_y = timing->vactive; + + config->hsync.pulse_width = timing->hsync_len; + config->hsync.back_porch_pulse = timing->hback_porch; + config->hsync.front_porch_pulse = timing->hfront_porch; + + config->vsync.pulse_width = timing->vsync_len; + config->vsync.back_porch_pulse = timing->vback_porch; + config->vsync.front_porch_pulse = timing->vfront_porch; + + config->control.invert_hsync = timing->hsync_pol; + config->control.invert_vsync = timing->vsync_pol; + config->control.invert_href = timing->de_pol; + config->control.invert_pixel_data = timing->pixel_data_pol; + config->control.invert_pixel_clock = timing->pixel_clk_pol; } +#endif void board_delay_ms(uint32_t ms) { clock_cpu_delay_ms(ms); } +void board_delay_us(uint32_t us) +{ + clock_cpu_delay_us(us); +} + void board_timer_isr(void) { if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) { @@ -299,7 +384,8 @@ void board_i2c_bus_clear(I2C_Type *ptr) gpio_set_pin_input(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN); if (!gpio_read_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN)) { printf("CLK is low, please power cycle the board\n"); - while (1) {} + while (1) { + } } if (!gpio_read_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_SDA_GPIO_INDEX, BOARD_CAP_I2C_SDA_GPIO_PIN)) { printf("SDA is low, try to issue I2C bus clear\n"); @@ -344,13 +430,14 @@ void board_init_i2c(I2C_Type *ptr) stat = i2c_init_master(BOARD_CAP_I2C_BASE, freq, &config); if (stat != status_success) { printf("failed to initialize i2c 0x%x\n", (uint32_t)BOARD_CAP_I2C_BASE); - while (1) {} + while (1) { + } } } uint32_t board_init_uart_clock(UART_Type *ptr) { - uint32_t freq = 0; + uint32_t freq = 0U; clock_name_t clock_name = clock_uart0; bool need_init_clock = true; if (ptr == HPM_UART0) { @@ -404,7 +491,7 @@ uint32_t board_init_spi_clock(SPI_Type *ptr) if (ptr == HPM_SPI2) { /* SPI2 clock configure */ clock_add_to_group(clock_spi2, 0); - clock_set_source_divider(clock_spi2, clk_src_osc24m, 1U); + clock_set_source_divider(clock_spi2, clk_src_pll1_clk1, 5U); /* 80MHz */ return clock_get_frequency(clock_spi2); } @@ -428,7 +515,12 @@ void board_init_cap_touch(void) void board_init_gpio_pins(void) { - init_gpio_pins(); + uint8_t led_pin_pull_selsect; + HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12; + HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + + led_pin_pull_selsect = gpio_read_pin(BOARD_G_GPIO_CTRL, GPIO_DI_GPIOB, 12); + init_gpio_pins(led_pin_pull_selsect); } void board_init_spi_pins(SPI_Type *ptr) @@ -436,19 +528,50 @@ void board_init_spi_pins(SPI_Type *ptr) init_spi_pins(ptr); } +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + init_spi_pins_with_gpio_as_cs(ptr); + gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN), + GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL); +} + +void board_write_spi_cs(uint32_t pin, uint8_t state) +{ + gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state); +} + +uint8_t board_get_led_pwm_off_level(void) +{ + if (invert_led_level) { + return BOARD_LED_ON_LEVEL; + } else { + return BOARD_LED_OFF_LEVEL; + } +} + +uint8_t board_get_led_gpio_off_level(void) +{ + if (invert_led_level) { + return BOARD_LED_ON_LEVEL; + } else { + return BOARD_LED_OFF_LEVEL; + } +} + void board_init_led_pins(void) { + board_turnoff_rgb_led(); init_led_pins_as_gpio(); - gpio_set_pin_output_with_initial(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_OFF_LEVEL); - gpio_set_pin_output_with_initial(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_OFF_LEVEL); - gpio_set_pin_output_with_initial(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_OFF_LEVEL); + gpio_set_pin_output_with_initial(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, board_get_led_gpio_off_level()); + gpio_set_pin_output_with_initial(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, board_get_led_gpio_off_level()); + gpio_set_pin_output_with_initial(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, board_get_led_gpio_off_level()); } void board_led_toggle(void) { #ifdef BOARD_LED_TOGGLE_RGB static uint8_t i; - gpio_write_port(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, (7 & ~(1 << i)) << BOARD_R_GPIO_PIN); + gpio_write_port(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, invert_led_level ? ((1 << i) << BOARD_R_GPIO_PIN) : ((7 & ~(1 << i)) << BOARD_R_GPIO_PIN)); i++; i = i % 3; #else @@ -490,38 +613,41 @@ void board_init_usb_pins(void) void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level) { + (void) usb_index; + (void) level; } void board_init_pmp(void) { + uint32_t start_addr; + uint32_t end_addr; + uint32_t length; + pmp_entry_t pmp_entry[16]; + uint8_t index = 0; + + /* Init noncachable memory */ extern uint32_t __noncacheable_start__[]; extern uint32_t __noncacheable_end__[]; - - uint32_t start_addr = (uint32_t) __noncacheable_start__; - uint32_t end_addr = (uint32_t) __noncacheable_end__; - uint32_t length = end_addr - start_addr; - - if (length == 0) { - return; + start_addr = (uint32_t) __noncacheable_start__; + end_addr = (uint32_t) __noncacheable_end__; + length = end_addr - start_addr; + if (length > 0) { + /* Ensure the address and the length are power of 2 aligned */ + assert((length & (length - 1U)) == 0U); + assert((start_addr & (length - 1U)) == 0U); + pmp_entry[index].pmp_addr = PMP_NAPOT_ADDR(start_addr, length); + pmp_entry[index].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK); + pmp_entry[index].pma_addr = PMA_NAPOT_ADDR(start_addr, length); + pmp_entry[index].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN); + index++; } - /* Ensure the address and the length are power of 2 aligned */ - assert((length & (length - 1U)) == 0U); - assert((start_addr & (length - 1U)) == 0U); - - pmp_entry_t pmp_entry[1]; - pmp_entry[0].pmp_addr = PMP_NAPOT_ADDR(start_addr, length); - pmp_entry[0].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK); - pmp_entry[0].pma_addr = PMA_NAPOT_ADDR(start_addr, length); - pmp_entry[0].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN); - - pmp_config(&pmp_entry[0], ARRAY_SIZE(pmp_entry)); + pmp_config(&pmp_entry[0], index); } void board_init_clock(void) { uint32_t cpu0_freq = clock_get_frequency(clock_cpu0); - hpm_core_clock = cpu0_freq; if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) { /* Configure the External OSC ramp-up time: ~9ms */ pllctl_xtal_set_rampup_time(HPM_PLLCTL, 32UL * 1000UL * 9U); @@ -531,6 +657,7 @@ void board_init_clock(void) } /* Add most Clocks to group 0 */ + /* not open uart clock in this API, uart should configure pin function before opening clock */ clock_add_to_group(clock_cpu0, 0); clock_add_to_group(clock_mchtmr0, 0); clock_add_to_group(clock_axi0, 0); @@ -548,7 +675,6 @@ void board_init_clock(void) clock_add_to_group(clock_gptmr5, 0); clock_add_to_group(clock_gptmr6, 0); clock_add_to_group(clock_gptmr7, 0); - clock_add_to_group(clock_uart0, 0); clock_add_to_group(clock_i2c0, 0); clock_add_to_group(clock_i2c1, 0); clock_add_to_group(clock_i2c2, 0); @@ -616,19 +742,21 @@ void board_init_clock(void) /* Bump up DCDC voltage to 1200mv */ pcfg_dcdc_set_voltage(HPM_PCFG, 1200); + pcfg_dcdc_switch_to_dcm_mode(HPM_PCFG); if (status_success != pllctl_init_int_pll_with_freq(HPM_PLLCTL, 0, BOARD_CPU_FREQ)) { - printf("Failed to set pll0_clk0 to %ldHz\n", BOARD_CPU_FREQ); + printf("Failed to set pll0_clk0 to %luHz\n", BOARD_CPU_FREQ); while (1) { } } clock_set_source_divider(clock_cpu0, clk_src_pll0_clk0, 1); clock_set_source_divider(clock_cpu1, clk_src_pll0_clk0, 1); - /* Connect Group1 to CPU1 */ - clock_connect_group_to_cpu(1, 1); + clock_update_core_clock(); - clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 54); /* config clock_aud1 for 44100*n sample rate */ + clock_set_source_divider(clock_ahb, clk_src_pll1_clk1, 2); /*200m hz*/ + clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1); + clock_set_source_divider(clock_mchtmr1, clk_src_osc24m, 1); } uint32_t board_init_cam_clock(CAM_Type *ptr) @@ -652,48 +780,18 @@ uint32_t board_init_lcd_clock(void) { uint32_t freq; clock_add_to_group(clock_display, 0); - /* Configure LCDC clock to 29.7MHz */ - clock_set_source_divider(clock_display, clock_source_pll4_clk0, 20U); + /* Configure LCDC clock to 59.4MHz */ + clock_set_source_divider(clock_display, (clk_src_t) clock_source_pll4_clk0, 10U); freq = clock_get_frequency(clock_display); return freq; } -uint32_t board_init_adc12_clock(ADC12_Type *ptr) -{ - uint32_t freq = 0; - switch ((uint32_t) ptr) { - case HPM_ADC0_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc0, clk_adc_src_ana0); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); - freq = clock_get_frequency(clock_adc0); - break; - case HPM_ADC1_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc1, clk_adc_src_ana0); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); - freq = clock_get_frequency(clock_adc1); - break; - case HPM_ADC2_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc2, clk_adc_src_ana0); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); - freq = clock_get_frequency(clock_adc2); - break; - default: - /* Invalid ADC instance */ - break; - } - - return freq; -} - uint32_t board_init_dao_clock(void) { clock_add_to_group(clock_dao, 0); - sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); - sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud0_clk); + sysctl_config_clock(HPM_SYSCTL, clock_node_aud1, clock_source_pll3_clk0, 25); + sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud1_clk); return clock_get_frequency(clock_dao); } @@ -708,26 +806,134 @@ uint32_t board_init_pdm_clock(void) return clock_get_frequency(clock_pdm); } +hpm_stat_t board_set_audio_pll_clock(uint32_t freq) +{ + return pllctl_init_frac_pll_with_freq(HPM_PLLCTL, 3, freq); /* pll3clk */ +} + +void board_init_i2s_pins(I2S_Type *ptr) +{ + init_i2s_pins(ptr); +} + uint32_t board_init_i2s_clock(I2S_Type *ptr) { + uint32_t freq = 0; + if (ptr == HPM_I2S0) { clock_add_to_group(clock_i2s0, 0); sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk); - return clock_get_frequency(clock_i2s0); + freq = clock_get_frequency(clock_i2s0); + } else if (ptr == HPM_I2S1) { + clock_add_to_group(clock_i2s1, 0); + + sysctl_config_clock(HPM_SYSCTL, clock_node_aud1, clock_source_pll3_clk0, 25); + sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud1_clk); + + freq = clock_get_frequency(clock_i2s1); + } else { + ; } - return 0; + + return freq; } -uint32_t board_init_adc16_clock(ADC16_Type *ptr) +/* adjust I2S source clock base on sample rate */ +uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate) { uint32_t freq = 0; + + if (ptr == HPM_I2S0) { + clock_add_to_group(clock_i2s0, 0); + if ((sample_rate % 22050) == 0) { + clock_set_source_divider(clock_aud0, clk_src_pll3_clk0, 54); /* config clock_aud1 for 22050*n sample rate */ + } else { + clock_set_source_divider(clock_aud0, clk_src_pll3_clk0, 25); /* config clock_aud0 for 8000*n sample rate */ + } + clock_set_i2s_source(clock_i2s0, clk_i2s_src_aud0); + freq = clock_get_frequency(clock_i2s0); + } else if (ptr == HPM_I2S1) { + clock_add_to_group(clock_i2s1, 0); + if ((sample_rate % 22050) == 0) { + clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 54); /* config clock_aud1 for 22050*n sample rate */ + } else { + clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 25); /* config clock_aud0 for 8000*n sample rate */ + } + clock_set_i2s_source(clock_i2s1, clk_i2s_src_aud1); + freq = clock_get_frequency(clock_i2s1); + } else { + ; + } + + return freq; +} + +void board_init_adc12_pins(void) +{ + init_adc12_pins(); +} + +void board_init_adc16_pins(void) +{ + init_adc16_pins(); +} + +uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb) +{ + uint32_t freq = 0; + + if (ptr == HPM_ADC0) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + } + freq = clock_get_frequency(clock_adc0); + } else if (ptr == HPM_ADC1) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc1, clk_adc_src_ana1); + clock_set_source_divider(clock_ana1, clk_src_pll1_clk1, 2U); + } + freq = clock_get_frequency(clock_adc1); + } else if (ptr == HPM_ADC2) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc2, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc2, clk_adc_src_ana2); + clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U); + } + freq = clock_get_frequency(clock_adc2); + } + + return freq; +} + +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) +{ + uint32_t freq = 0; + if (ptr == HPM_ADC3) { - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc3, clk_adc_src_ana1); - clock_set_source_divider(clock_ana1, clk_src_pll1_clk1, 2U); + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc3, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc3, clk_adc_src_ana2); + clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U); + } + freq = clock_get_frequency(clock_adc3); } @@ -764,6 +970,27 @@ uint32_t board_init_can_clock(CAN_Type *ptr) return freq; } +uint32_t board_init_pwm_clock(PWM_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_PWM0) { + clock_add_to_group(clock_mot0, 0); + freq = clock_get_frequency(clock_mot0); + } else if (ptr == HPM_PWM1) { + clock_add_to_group(clock_mot1, 0); + freq = clock_get_frequency(clock_mot1); + } else if (ptr == HPM_PWM2) { + clock_add_to_group(clock_mot2, 0); + freq = clock_get_frequency(clock_mot2); + } else if (ptr == HPM_PWM3) { + clock_add_to_group(clock_mot3, 0); + freq = clock_get_frequency(clock_mot3); + } else { + + } + return freq; +} + uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) { uint32_t freq = 0; @@ -811,6 +1038,7 @@ uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) else { /* Invalid instance */ } + return freq; } @@ -828,7 +1056,6 @@ void _init_ext_ram(void) femc_sdram_config_t sdram_config = {0}; femc_default_config(HPM_FEMC, &config); - config.dqs = FEMC_DQS_INTERNAL; femc_init(HPM_FEMC, &config); sdram_config.bank_num = FEMC_SDRAM_BANK_NUM_4; @@ -858,25 +1085,20 @@ void _init_ext_ram(void) sdram_config.refresh_count = BOARD_SDRAM_REFRESH_COUNT; sdram_config.refresh_in_ms = BOARD_SDRAM_REFRESH_IN_MS; sdram_config.data_width_in_byte = BOARD_SDRAM_DATA_WIDTH_IN_BYTE; - sdram_config.delay_cell_value = 29; + sdram_config.delay_cell_disable = true; + sdram_config.delay_cell_value = 0; femc_config_sdram(HPM_FEMC, femc_clk_in_hz, &sdram_config); } -void board_init_sd_pins(SDXC_Type *ptr) -{ - init_sdxc_pins(ptr, false); - init_sdxc_card_detection_pin(ptr); -} - void board_sd_power_switch(SDXC_Type *ptr, bool on_off) { /* This feature is not supported on current board */ } -uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq) +uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inverse) { uint32_t actual_freq = 0; do { @@ -891,11 +1113,11 @@ uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq) clock_set_source_divider(sdxc_clk, clk_src_osc24m, 63); } /* configure the clock to 24MHz for the SDR12/Default speed */ - else if (freq <= 25000000UL) { + else if (freq <= 26000000UL) { clock_set_source_divider(sdxc_clk, clk_src_osc24m, 1); } /* Configure the clock to 50MHz for the SDR25/High speed/50MHz DDR/50MHz SDR */ - else if (freq <= 50000000UL) { + else if (freq <= 52000000UL) { clock_set_source_divider(sdxc_clk, clk_src_pll1_clk1, 8); } /* Configure the clock to 100MHz for the SDR50 */ @@ -910,7 +1132,9 @@ uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq) else { clock_set_source_divider(sdxc_clk, clk_src_osc24m, 1); } - sdxc_enable_inverse_clock(ptr, true); + if (need_inverse) { + sdxc_enable_inverse_clock(ptr, true); + } sdxc_enable_sd_clock(ptr, true); actual_freq = clock_get_frequency(sdxc_clk); } while (false); @@ -918,16 +1142,6 @@ uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq) return actual_freq; } -void board_sd_switch_pins_to_1v8(SDXC_Type *ptr) -{ - /* This feature is not supported */ -} - -bool board_sd_detect_card(SDXC_Type *ptr) -{ - return ((BOARD_APP_SDCARD_CDN_GPIO_CTRL->DI[GPIO_DI_GPIOD].VALUE & (1UL << BOARD_APP_SDCARD_CDN_GPIO_PIN)) == 0U); -} - static void set_rgb_output_off(PWM_Type *ptr, uint8_t pin, uint8_t cmp_index) { pwm_cmp_config_t cmp_config = {0}; @@ -1035,30 +1249,35 @@ hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr) hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) { - if (internal == false) { - return status_success; - } /* Configure Enet clock to output reference clock */ - if (ptr == HPM_ENET0) { - /* make sure pll2_clk1 output clock at 250MHz then set 50MHz for enet0 */ - clock_set_source_divider(clock_eth0, clk_src_pll2_clk1, 5); - } else if (ptr == HPM_ENET1) { - /* make sure pll2_clk1 output clock at 250MHz then set 50MHz for enet1 */ - clock_set_source_divider(clock_eth1, clk_src_pll2_clk1, 5); /* set 50MHz for enet1 */ + if (ptr == HPM_ENET1) { + if (internal) { + /* set pll output frequency at 1GHz */ + if (pllctl_init_int_pll_with_freq(HPM_PLLCTL, PLLCTL_PLL_PLL2, 1000000000UL) == status_success) { + /* set pll2_clk1 output frequence at 250MHz from PLL2 divided by 4 */ + pllctl_set_div(HPM_PLLCTL, PLLCTL_PLL_PLL2, 1, 4); + /* set eth clock frequency at 50MHz for enet0 */ + clock_set_source_divider(ptr == HPM_ENET0 ? clock_eth0 : clock_eth1, clk_src_pll2_clk1, 5); + } else { + return status_fail; + } + } } else { return status_invalid_argument; } + + enet_rmii_enable_clock(ptr, internal); + return status_success; } -void board_init_adc12_pins(void) +hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr) { - init_adc12_pins(); -} + if (ptr == HPM_ENET0) { + return enet_rgmii_set_clock_delay(ptr, BOARD_ENET_RGMII_TX_DLY, BOARD_ENET_RGMII_RX_DLY); + } -void board_init_adc16_pins(void) -{ - init_adc16_pins(); + return status_invalid_argument; } hpm_stat_t board_init_enet_pins(ENET_Type *ptr) @@ -1066,9 +1285,9 @@ hpm_stat_t board_init_enet_pins(ENET_Type *ptr) init_enet_pins(ptr); if (ptr == HPM_ENET0) { - gpio_set_pin_output_with_initial(BOARD_ENET0_RST_GPIO, BOARD_ENET0_RST_GPIO_INDEX, BOARD_ENET0_RST_GPIO_PIN, 0); - } else if (ptr == HPM_ENET1) { - gpio_set_pin_output_with_initial(BOARD_ENET1_RST_GPIO, BOARD_ENET1_RST_GPIO_INDEX, BOARD_ENET1_RST_GPIO_PIN, 0); + gpio_set_pin_output_with_initial(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 0); + } else if (ptr == HPM_ENET1) { + gpio_set_pin_output_with_initial(BOARD_ENET_RMII_RST_GPIO, BOARD_ENET_RMII_RST_GPIO_INDEX, BOARD_ENET_RMII_RST_GPIO_PIN, 0); } else { return status_invalid_argument; } @@ -1079,13 +1298,13 @@ hpm_stat_t board_init_enet_pins(ENET_Type *ptr) hpm_stat_t board_reset_enet_phy(ENET_Type *ptr) { if (ptr == HPM_ENET0) { - gpio_write_pin(BOARD_ENET0_RST_GPIO, BOARD_ENET0_RST_GPIO_INDEX, BOARD_ENET0_RST_GPIO_PIN, 0); - board_delay_ms(BOARD_ENET0_PHY_RST_TIME); - gpio_write_pin(BOARD_ENET0_RST_GPIO, BOARD_ENET0_RST_GPIO_INDEX, BOARD_ENET0_RST_GPIO_PIN, 1); + gpio_write_pin(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 0); + board_delay_ms(1); + gpio_write_pin(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 1); } else if (ptr == HPM_ENET1) { - gpio_write_pin(BOARD_ENET1_RST_GPIO, BOARD_ENET1_RST_GPIO_INDEX, BOARD_ENET1_RST_GPIO_PIN, 0); - board_delay_ms(BOARD_ENET1_PHY_RST_TIME); - gpio_write_pin(BOARD_ENET1_RST_GPIO, BOARD_ENET1_RST_GPIO_INDEX, BOARD_ENET1_RST_GPIO_PIN, 1); + gpio_write_pin(BOARD_ENET_RMII_RST_GPIO, BOARD_ENET_RMII_RST_GPIO_INDEX, BOARD_ENET_RMII_RST_GPIO_PIN, 0); + board_delay_ms(1); + gpio_write_pin(BOARD_ENET_RMII_RST_GPIO, BOARD_ENET_RMII_RST_GPIO_INDEX, BOARD_ENET_RMII_RST_GPIO_PIN, 1); } else { return status_invalid_argument; } @@ -1093,7 +1312,134 @@ hpm_stat_t board_reset_enet_phy(ENET_Type *ptr) return status_success; } -uint8_t board_enet_get_dma_pbl(ENET_Type *ptr) +uint8_t board_get_enet_dma_pbl(ENET_Type *ptr) { + (void) ptr; return enet_pbl_32; } + +hpm_stat_t board_enable_enet_irq(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + intc_m_enable_irq(IRQn_ENET0); + } else if (ptr == HPM_ENET1) { + intc_m_enable_irq(IRQn_ENET1); + } else { + return status_invalid_argument; + } + + return status_success; +} + +hpm_stat_t board_disable_enet_irq(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + intc_m_disable_irq(IRQn_ENET0); + } else if (ptr == HPM_ENET1) { + intc_m_disable_irq(IRQn_ENET1); + } else { + return status_invalid_argument; + } + + return status_success; +} + +void board_init_enet_pps_pins(ENET_Type *ptr) +{ + (void) ptr; + init_enet_pps_pins(); +} + +#if defined(ENET_MULTIPLE_PORT) && ENET_MULTIPLE_PORT + +hpm_stat_t board_init_multiple_enet_pins(void) +{ + board_init_enet_pins(HPM_ENET0); + board_init_enet_pins(HPM_ENET1); + + return status_success; +} + +hpm_stat_t board_init_multiple_enet_clock(void) +{ + /* Set RGMII clock delay */ + board_init_enet_rgmii_clock_delay(HPM_ENET0); + + /* Set RMII reference clock */ + board_init_enet_rmii_reference_clock(HPM_ENET1, BOARD_ENET_RMII_INT_REF_CLK); + printf("Enet1 Reference Clock: %s\n", BOARD_ENET_RMII_INT_REF_CLK ? "Internal Clock" : "External Clock"); + + return status_success; +} + +hpm_stat_t board_reset_multiple_enet_phy(void) +{ + board_reset_enet_phy(HPM_ENET0); + board_reset_enet_phy(HPM_ENET1); + + return status_success; +} + +hpm_stat_t board_init_enet_phy(ENET_Type *ptr) +{ + dp83867_config_t phy_config0; + dp83848_config_t phy_config1; + + if (ptr == HPM_ENET0) { + dp83867_reset(HPM_ENET0); + #if defined(__DISABLE_AUTO_NEGO) && __DISABLE_AUTO_NEGO + dp83867_set_mdi_crossover_mode(HPM_ENET0, enet_phy_mdi_crossover_manual_mdix); + #endif + dp83867_basic_mode_default_config(HPM_ENET0, &phy_config0); + if (dp83867_basic_mode_init(HPM_ENET0, &phy_config0) == true) { + return status_success; + } else { + printf("Enet0 phy init failed!\n"); + return status_fail; + } + } else if (ptr == HPM_ENET1) { + dp83848_reset(HPM_ENET1); + dp83848_basic_mode_default_config(HPM_ENET1, &phy_config1); + if (dp83848_basic_mode_init(HPM_ENET1, &phy_config1) == true) { + return status_success; + } else { + printf("Enet1 phy init failed!\n"); + return status_fail; + } + } else { + return status_invalid_argument; + } +} + +ENET_Type *board_get_enet_base(uint8_t idx) +{ + if (idx == 0) { + return HPM_ENET0; + } else { + return HPM_ENET1; + } +} + +uint8_t board_get_enet_phy_itf(uint8_t idx) +{ + if (idx == 0) { + return BOARD_ENET_RGMII_PHY_ITF; + } else { + return BOARD_ENET_RMII_PHY_ITF; + } +} + +void board_get_enet_phy_status(uint8_t idx, void *status) +{ + if (idx == 0) { + dp83867_get_phy_status(HPM_ENET0, status); + } else { + dp83848_get_phy_status(HPM_ENET1, status); + } +} +#endif + +void board_init_dao_pins(void) +{ + init_dao_pins(); +} diff --git a/bsp/hpmicro/hpm6750evk/board/board.h b/bsp/hpmicro/hpm6750evk/board/board.h index 9827edf1553..35afc0bbec4 100644 --- a/bsp/hpmicro/hpm6750evk/board/board.h +++ b/bsp/hpmicro/hpm6750evk/board/board.h @@ -14,168 +14,218 @@ #include "hpm_soc_feature.h" #include "pinmux.h" #include "hpm_lcdc_drv.h" +#include "hpm_trgm_drv.h" +#ifdef CONFIG_HPM_PANEL +#include "hpm_panel.h" +#endif +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#include "hpm_debug_console.h" +#endif -#define BOARD_NAME "hpm6750evk" +#define BOARD_NAME "hpm6750evk" #define BOARD_UF2_SIGNATURE (0x0A4D5048UL) -/* uart section */ +#define SEC_CORE_IMG_START ILM_LOCAL_BASE + #ifndef BOARD_RUNNING_CORE #define BOARD_RUNNING_CORE HPM_CORE0 #endif + +/* uart section */ #ifndef BOARD_APP_UART_BASE -#define BOARD_APP_UART_BASE HPM_UART0 -#define BOARD_APP_UART_IRQ IRQn_UART0 -#else -#ifndef BOARD_APP_UART_IRQ -#warning no IRQ specified for applicaiton uart -#endif +#define BOARD_APP_UART_BASE HPM_UART13 +#define BOARD_APP_UART_IRQ IRQn_UART13 +#define BOARD_APP_UART_BAUDRATE (115200UL) +#define BOARD_APP_UART_CLK_NAME clock_uart13 +#define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART13_RX +#define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART13_TX #endif /* uart rx idle demo section */ -#define BOARD_UART_IDLE HPM_UART13 -#define BOARD_UART_IDLE_DMA_SRC HPM_DMA_SRC_UART13_RX - -#define BOARD_UART_IDLE_TRGM HPM_TRGM2 -#define BOARD_UART_IDLE_TRGM_PIN IOC_PAD_PD19 -#define BOARD_UART_IDLE_TRGM_INPUT_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P9 -#define BOARD_UART_IDLE_TRGM_OUTPUT_GPTMR_IN HPM_TRGM2_OUTPUT_SRC_GPTMR4_IN2 +#define BOARD_UART_IDLE BOARD_APP_UART_BASE +#define BOARD_UART_IDLE_IRQ BOARD_APP_UART_IRQ +#define BOARD_UART_IDLE_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_UART_IDLE_TX_DMA_SRC BOARD_APP_UART_TX_DMA_REQ +#define BOARD_UART_IDLE_DMA_SRC BOARD_APP_UART_RX_DMA_REQ + +#define BOARD_UART_IDLE_TRGM HPM_TRGM2 +#define BOARD_UART_IDLE_TRGM_PIN IOC_PAD_PD19 +#define BOARD_UART_IDLE_TRGM_INPUT_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P9 +#define BOARD_UART_IDLE_TRGM_OUTPUT_GPTMR_IN HPM_TRGM2_OUTPUT_SRC_GPTMR4_IN2 #define BOARD_UART_IDLE_TRGM_OUTPUT_GPTMR_SYNCI HPM_TRGM2_OUTPUT_SRC_GPTMR4_SYNCI -#define BOARD_UART_IDLE_GPTMR HPM_GPTMR4 +#define BOARD_UART_IDLE_GPTMR HPM_GPTMR4 #define BOARD_UART_IDLE_GPTMR_CLK_NAME clock_gptmr4 -#define BOARD_UART_IDLE_GPTMR_IRQ IRQn_GPTMR4 -#define BOARD_UART_IDLE_GPTMR_CMP_CH 0 -#define BOARD_UART_IDLE_GPTMR_CAP_CH 2 - -#define BOARD_APP_UART_BAUDRATE (115200UL) -#define BOARD_APP_UART_CLK_NAME clock_uart0 - +#define BOARD_UART_IDLE_GPTMR_IRQ IRQn_GPTMR4 +#define BOARD_UART_IDLE_GPTMR_CMP_CH 0 +#define BOARD_UART_IDLE_GPTMR_CAP_CH 2 + +/* uart microros sample section */ +#define BOARD_MICROROS_UART_BASE BOARD_APP_UART_BASE +#define BOARD_MICROROS_UART_IRQ BOARD_APP_UART_IRQ +#define BOARD_MICROROS_UART_CLK_NAME BOARD_APP_UART_CLK_NAME + +/* rtthread-nano finsh section */ +#define BOARD_RT_CONSOLE_BASE BOARD_CONSOLE_UART_BASE + +/* usb cdc acm uart section */ +#define BOARD_USB_CDC_ACM_UART BOARD_APP_UART_BASE +#define BOARD_USB_CDC_ACM_UART_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_USB_CDC_ACM_UART_TX_DMA_SRC BOARD_APP_UART_TX_DMA_REQ +#define BOARD_USB_CDC_ACM_UART_RX_DMA_SRC BOARD_APP_UART_RX_DMA_REQ + +/* modbus sample section */ +#define BOARD_MODBUS_UART_BASE BOARD_APP_UART_BASE +#define BOARD_MODBUS_UART_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_MODBUS_UART_RX_DMA_REQ BOARD_APP_UART_RX_DMA_REQ +#define BOARD_MODBUS_UART_TX_DMA_REQ BOARD_APP_UART_TX_DMA_REQ + +/* uart lin sample section */ +#define BOARD_UART_LIN BOARD_APP_UART_BASE +#define BOARD_UART_LIN_IRQ BOARD_APP_UART_IRQ +#define BOARD_UART_LIN_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_UART_LIN_TX_PORT GPIO_DI_GPIOZ +#define BOARD_UART_LIN_TX_PIN (9U) /* PZ09 should align with used pin in pinmux configuration */ + +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE #ifndef BOARD_CONSOLE_TYPE #define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART #endif #if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART -#ifndef BOARD_CONSOLE_BASE +#ifndef BOARD_CONSOLE_UART_BASE #if BOARD_RUNNING_CORE == HPM_CORE0 -#define BOARD_CONSOLE_BASE HPM_UART0 -#define BOARD_CONSOLE_CLK_NAME clock_uart0 +#define BOARD_CONSOLE_UART_BASE HPM_UART0 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART0 +#define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX +#define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX #else -#define BOARD_CONSOLE_BASE HPM_UART13 -#define BOARD_CONSOLE_CLK_NAME clock_uart13 +#define BOARD_CONSOLE_UART_BASE HPM_UART13 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart13 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART13 +#define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART13_TX +#define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART13_RX #endif #endif -#define BOARD_CONSOLE_BAUDRATE (115200UL) +#define BOARD_CONSOLE_UART_BAUDRATE (115200UL) +#endif #endif - - -#define BOARD_FREEMASTER_UART_BASE HPM_UART0 -#define BOARD_FREEMASTER_UART_IRQ IRQn_UART0 -#define BOARD_FREEMASTER_UART_CLK_NAME clock_uart0 /* sdram section */ -#define BOARD_SDRAM_ADDRESS (0x40000000UL) -#define BOARD_SDRAM_SIZE (32*SIZE_1MB) -#define BOARD_SDRAM_CS FEMC_SDRAM_CS0 -#define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_32_BITS -#define BOARD_SDRAM_REFRESH_COUNT (8192UL) -#define BOARD_SDRAM_REFRESH_IN_MS (64UL) +#define BOARD_SDRAM_ADDRESS (0x40000000UL) +#define BOARD_SDRAM_SIZE (32 * SIZE_1MB) +#define BOARD_SDRAM_CS FEMC_SDRAM_CS0 +#define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_32_BITS +#define BOARD_SDRAM_REFRESH_COUNT (8192UL) +#define BOARD_SDRAM_REFRESH_IN_MS (64UL) #define BOARD_SDRAM_DATA_WIDTH_IN_BYTE (4UL) #define BOARD_FLASH_BASE_ADDRESS (0x80000000UL) -#define BOARD_FLASH_SIZE (16 << 20) +#define BOARD_FLASH_SIZE (16 << 20) + +#define BOARD_FEMC_DQS_FLOATING 1 /* lcd section */ -#define BOARD_LCD_BASE HPM_LCDC -#define BOARD_LCD_IRQ IRQn_LCDC_D0 -#define BOARD_LCD_POWER_GPIO_BASE HPM_GPIO0 -#define BOARD_LCD_POWER_GPIO_INDEX GPIO_DO_GPIOB -#define BOARD_LCD_POWER_GPIO_PIN 16 -#define BOARD_LCD_BACKLIGHT_GPIO_BASE HPM_GPIO0 +#define BOARD_LCD_BASE HPM_LCDC +#define BOARD_LCD_IRQ IRQn_LCDC_D0 +#define BOARD_LCD_POWER_GPIO_BASE HPM_GPIO0 +#define BOARD_LCD_POWER_GPIO_INDEX GPIO_DO_GPIOB +#define BOARD_LCD_POWER_GPIO_PIN 16 +#define BOARD_LCD_BACKLIGHT_GPIO_BASE HPM_GPIO0 #define BOARD_LCD_BACKLIGHT_GPIO_INDEX GPIO_DO_GPIOB -#define BOARD_LCD_BACKLIGHT_GPIO_PIN 10 +#define BOARD_LCD_BACKLIGHT_GPIO_PIN 10 /* i2c section */ -#define BOARD_APP_I2C_BASE HPM_I2C0 +#define BOARD_APP_I2C_BASE HPM_I2C0 +#define BOARD_APP_I2C_IRQ IRQn_I2C0 #define BOARD_APP_I2C_CLK_NAME clock_i2c0 -#define BOARD_APP_I2C_DMA HPM_HDMA -#define BOARD_APP_I2C_DMAMUX HPM_DMAMUX -#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0 -#define BOARD_APP_I2C_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 +#define BOARD_APP_I2C_DMA HPM_HDMA +#define BOARD_APP_I2C_DMAMUX HPM_DMAMUX +#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0 -#define BOARD_CAM_I2C_BASE HPM_I2C0 +#define BOARD_CAM_I2C_BASE HPM_I2C0 #define BOARD_CAM_I2C_CLK_NAME clock_i2c0 #define BOARD_SUPPORT_CAM_RESET -#define BOARD_CAM_RST_GPIO_CTRL HPM_GPIO0 +#define BOARD_CAM_RST_GPIO_CTRL HPM_GPIO0 #define BOARD_CAM_RST_GPIO_INDEX GPIO_DI_GPIOY -#define BOARD_CAM_RST_GPIO_PIN 5 - -#define BOARD_CAP_I2C_BASE (HPM_I2C0) -#define BOARD_CAP_I2C_CLK_NAME clock_i2c0 -#define BOARD_CAP_RST_GPIO (HPM_GPIO0) -#define BOARD_CAP_RST_GPIO_INDEX (GPIO_DI_GPIOB) -#define BOARD_CAP_RST_GPIO_PIN (9) -#define BOARD_CAP_RST_GPIO_IRQ (IRQn_GPIO0_B) -#define BOARD_CAP_INTR_GPIO (HPM_GPIO0) -#define BOARD_CAP_INTR_GPIO_INDEX (GPIO_DI_GPIOB) -#define BOARD_CAP_INTR_GPIO_PIN (8) -#define BOARD_CAP_INTR_GPIO_IRQ (IRQn_GPIO0_B) +#define BOARD_CAM_RST_GPIO_PIN 5 + +#define BOARD_CAP_I2C_BASE (HPM_I2C0) +#define BOARD_CAP_I2C_CLK_NAME clock_i2c0 +#define BOARD_CAP_RST_GPIO (HPM_GPIO0) +#define BOARD_CAP_RST_GPIO_INDEX (GPIO_DI_GPIOB) +#define BOARD_CAP_RST_GPIO_PIN (9) +#define BOARD_CAP_RST_GPIO_IRQ (IRQn_GPIO0_B) +#define BOARD_CAP_INTR_GPIO (HPM_GPIO0) +#define BOARD_CAP_INTR_GPIO_INDEX (GPIO_DI_GPIOB) +#define BOARD_CAP_INTR_GPIO_PIN (8) +#define BOARD_CAP_INTR_GPIO_IRQ (IRQn_GPIO0_B) #define BOARD_CAP_I2C_SDA_GPIO_INDEX (GPIO_DI_GPIOZ) -#define BOARD_CAP_I2C_SDA_GPIO_PIN (10) +#define BOARD_CAP_I2C_SDA_GPIO_PIN (10) #define BOARD_CAP_I2C_CLK_GPIO_INDEX (GPIO_DI_GPIOZ) -#define BOARD_CAP_I2C_CLK_GPIO_PIN (11) +#define BOARD_CAP_I2C_CLK_GPIO_PIN (11) /* ACMP desction */ -#define BOARD_ACMP HPM_ACMP -#define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 -#define BOARD_ACMP_IRQ IRQn_ACMP_1 -#define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ +#define BOARD_ACMP HPM_ACMP +#define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 +#define BOARD_ACMP_IRQ IRQn_ACMP_1 +#define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ #define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_6 /* align with used pin */ /* dma section */ -#define BOARD_APP_XDMA HPM_XDMA -#define BOARD_APP_HDMA HPM_HDMA +#define BOARD_APP_XDMA HPM_XDMA +#define BOARD_APP_HDMA HPM_HDMA #define BOARD_APP_XDMA_IRQ IRQn_XDMA #define BOARD_APP_HDMA_IRQ IRQn_HDMA -#define BOARD_APP_DMAMUX HPM_DMAMUX +#define BOARD_APP_DMAMUX HPM_DMAMUX /* gptmr section */ -#define BOARD_GPTMR HPM_GPTMR4 -#define BOARD_GPTMR_IRQ IRQn_GPTMR4 -#define BOARD_GPTMR_CHANNEL 1 -#define BOARD_GPTMR_PWM HPM_GPTMR3 -#define BOARD_GPTMR_PWM_CHANNEL 1 +#define BOARD_GPTMR HPM_GPTMR4 +#define BOARD_GPTMR_IRQ IRQn_GPTMR4 +#define BOARD_GPTMR_CHANNEL 1 +#define BOARD_GPTMR_DMA_SRC HPM_DMA_SRC_GPTMR4_1 +#define BOARD_GPTMR_CLK_NAME clock_gptmr4 +#define BOARD_GPTMR_PWM HPM_GPTMR5 +#define BOARD_GPTMR_PWM_DMA_SRC HPM_DMA_SRC_GPTMR5_2 +#define BOARD_GPTMR_PWM_CHANNEL 2 +#define BOARD_GPTMR_PWM_CLK_NAME clock_gptmr5 +#define BOARD_GPTMR_PWM_IRQ IRQn_GPTMR5 +#define BOARD_GPTMR_PWM_SYNC HPM_GPTMR5 +#define BOARD_GPTMR_PWM_SYNC_CHANNEL 3 +#define BOARD_GPTMR_PWM_SYNC_CLK_NAME clock_gptmr5 /* gpio section */ -#define BOARD_R_GPIO_CTRL HPM_GPIO0 +#define BOARD_R_GPIO_CTRL HPM_GPIO0 #define BOARD_R_GPIO_INDEX GPIO_DI_GPIOB -#define BOARD_R_GPIO_PIN 11 -#define BOARD_G_GPIO_CTRL HPM_GPIO0 +#define BOARD_R_GPIO_PIN 11 +#define BOARD_G_GPIO_CTRL HPM_GPIO0 #define BOARD_G_GPIO_INDEX GPIO_DI_GPIOB -#define BOARD_G_GPIO_PIN 12 -#define BOARD_B_GPIO_CTRL HPM_GPIO0 +#define BOARD_G_GPIO_PIN 12 +#define BOARD_B_GPIO_CTRL HPM_GPIO0 #define BOARD_B_GPIO_INDEX GPIO_DI_GPIOB -#define BOARD_B_GPIO_PIN 13 +#define BOARD_B_GPIO_PIN 13 #define BOARD_LED_GPIO_CTRL HPM_GPIO0 #define BOARD_LED_GPIO_INDEX GPIO_DI_GPIOB -#define BOARD_LED_GPIO_PIN 12 -#define BOARD_LED_OFF_LEVEL 1 -#define BOARD_LED_ON_LEVEL 0 +#define BOARD_LED_GPIO_PIN 12 +#define BOARD_LED_OFF_LEVEL 1 +#define BOARD_LED_ON_LEVEL 0 #define BOARD_LED_TOGGLE_RGB 1 #define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOZ -#define BOARD_APP_GPIO_PIN 2 +#define BOARD_APP_GPIO_PIN 2 /* pinmux section */ #define USING_GPIO0_FOR_GPIOZ #ifndef USING_GPIO0_FOR_GPIOZ #define BOARD_APP_GPIO_CTRL HPM_BGPIO -#define BOARD_APP_GPIO_IRQ IRQn_BGPIO +#define BOARD_APP_GPIO_IRQ IRQn_BGPIO #else #define BOARD_APP_GPIO_CTRL HPM_GPIO0 -#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_Z +#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_Z #endif /* gpiom section */ @@ -184,89 +234,72 @@ #define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast /* spi section */ -#define BOARD_APP_SPI_BASE HPM_SPI2 -#define BOARD_APP_SPI_CLK_SRC_FREQ (24000000UL) -#define BOARD_APP_SPI_SCLK_FREQ (1562500UL) +#define BOARD_APP_SPI_BASE HPM_SPI2 +#define BOARD_APP_SPI_CLK_NAME clock_spi2 +#define BOARD_APP_SPI_IRQ IRQn_SPI2 +#define BOARD_APP_SPI_SCLK_FREQ (20000000UL) #define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U) #define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U) -#define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI2_RX -#define BOARD_APP_SPI_RX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 -#define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI2_TX -#define BOARD_APP_SPI_TX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX1 - +#define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI2_RX +#define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI2_TX +#define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 +#define BOARD_SPI_CS_PIN IOC_PAD_PE31 +#define BOARD_SPI_CS_ACTIVE_LEVEL (0U) /* Flash section */ -#define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) -#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90001U) -#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000005U) -#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) +#define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) +#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90001U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000005U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) /* lcd section */ -/* - * BOARD_PANEL_TIMING_PARA {HSPW, HBP, HFP, VSPW, VBP, VFP, HSSP, VSSP, DESP, PDSP, PCSP} - * - * HSPW: Horizontal Synchronization Pulse width - * HBP: Horizontal Back Porch - * HFP: Horizontal Front Porch - * VSPW: Vertical Synchronization Pulse width - * VBP: Vertical Back Porch - * VFP: Vertical Front Porch - * HSSP: Horizontal Synchronization Signal Polarity, 0: High Active, 1: Low Active - * VSSP: Vertical Synchronization Signal Polarity, 0: High Active, 1: Low Active - * DESP: Data Enable Signal Polarity, 0: High Active, 1: Low Active - * PDSP: Pixel Data Signal Polarity, 0: High Active, 1: Low Active - * PCSP: Pixel Clock Signal Polarity, 0: High Active, 1: Low Active - */ -#define BOARD_PANEL_TIMEING_PARA_HSPW_INDEX 0 -#define BOARD_PANEL_TIMEING_PARA_HBP_INDEX 1 -#define BOARD_PANEL_TIMEING_PARA_HFP_INDEX 2 -#define BOARD_PANEL_TIMEING_PARA_VSPW_INDEX 3 -#define BOARD_PANEL_TIMEING_PARA_VBP_INDEX 4 -#define BOARD_PANEL_TIMEING_PARA_VFP_INDEX 5 -#define BOARD_PANEL_TIMEING_PARA_HSSP_INDEX 6 -#define BOARD_PANEL_TIMEING_PARA_VSSP_INDEX 7 -#define BOARD_PANEL_TIMEING_PARA_DESP_INDEX 8 -#define BOARD_PANEL_TIMEING_PARA_PDSP_INDEX 9 -#define BOARD_PANEL_TIMEING_PARA_PCSP_INDEX 10 - -#if defined(PANEL_TM070RDH13) - #ifndef BOARD_LCD_WIDTH -#define BOARD_LCD_WIDTH 800 +#define BOARD_LCD_WIDTH PANEL_SIZE_WIDTH #endif #ifndef BOARD_LCD_HEIGHT -#define BOARD_LCD_HEIGHT 480 -#endif -#ifndef BOARD_PANEL_TIMING_PARA -#define BOARD_PANEL_TIMING_PARA {10, 46, 50, 3, 23, 10, 0, 0, 0, 0, 0} -#endif - -#else - -#ifndef BOARD_LCD_WIDTH -#define BOARD_LCD_WIDTH 800 -#endif -#ifndef BOARD_LCD_HEIGHT -#define BOARD_LCD_HEIGHT 480 -#endif -#ifndef BOARD_PANEL_TIMING_PARA -#define BOARD_PANEL_TIMING_PARA {10, 46, 50, 3, 23, 10, 0, 0, 0, 0, 0} -#endif - +#define BOARD_LCD_HEIGHT PANEL_SIZE_HEIGHT #endif /* pdma section */ #define BOARD_PDMA_BASE HPM_PDMA /* i2s section */ -#define BOARD_APP_I2S_BASE HPM_I2S0 -#define BOARD_APP_I2S_DATA_LINE (2U) -#define BOARD_APP_I2S_CLK_NAME clock_i2s0 -#define BOARD_APP_AUDIO_CLK_SRC clock_source_pll3_clk0 -#define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll3clk0 +#define BOARD_APP_I2S_BASE HPM_I2S0 +#define BOARD_APP_I2S_DATA_LINE (2U) +#define BOARD_APP_I2S_CLK_NAME clock_i2s0 +#define BOARD_APP_I2S_TX_DMA_REQ HPM_DMA_SRC_I2S0_TX +#define BOARD_APP_I2S_IRQ IRQn_I2S0 +#define BOARD_APP_AUDIO_CLK_SRC clock_source_pll3_clk0 +#define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll3clk0 +#define BOARD_PDM_SINGLE_CHANNEL_MASK (1U) +#define BOARD_PDM_DUAL_CHANNEL_MASK (0x11U) /* enet section */ +#define BOARD_ENET_COUNT (2U) +#define BOARD_ENET_PPS HPM_ENET0 +#define BOARD_ENET_PPS_IDX enet_pps_0 +#define BOARD_ENET_PPS_PTP_CLOCK clock_ptp0 + +#define BOARD_ENET_RGMII_PHY_ITF enet_inf_rgmii +#define BOARD_ENET_RGMII_RST_GPIO HPM_GPIO0 +#define BOARD_ENET_RGMII_RST_GPIO_INDEX GPIO_DO_GPIOF +#define BOARD_ENET_RGMII_RST_GPIO_PIN (0U) +#define BOARD_ENET_RGMII HPM_ENET0 +#define BOARD_ENET_RGMII_TX_DLY (0U) +#define BOARD_ENET_RGMII_RX_DLY (23U) +#define BOARD_ENET_RGMII_PTP_CLOCK clock_ptp0 +#define BOARD_ENET_RGMII_PPS0_PINOUT (1) + +#define BOARD_ENET_RMII_PHY_ITF enet_inf_rmii +#define BOARD_ENET_RMII_RST_GPIO HPM_GPIO0 +#define BOARD_ENET_RMII_RST_GPIO_INDEX GPIO_DO_GPIOE +#define BOARD_ENET_RMII_RST_GPIO_PIN (26U) +#define BOARD_ENET_RMII HPM_ENET1 +#define BOARD_ENET_RMII_INT_REF_CLK (1U) +#define BOARD_ENET_RMII_PTP_CLOCK clock_ptp1 +#define BOARD_ENET_RMII_PPS0_PINOUT (0) + #define BOARD_ENET0_RST_GPIO HPM_GPIO0 #define BOARD_ENET0_RST_GPIO_INDEX GPIO_DO_GPIOF #define BOARD_ENET0_RST_GPIO_PIN (0U) @@ -299,48 +332,69 @@ #endif /* ADC section */ -#define BOARD_APP_ADC12_NAME "ADC0" -#define BOARD_APP_ADC12_BASE HPM_ADC0 -#define BOARD_APP_ADC12_IRQn IRQn_ADC0 -#define BOARD_APP_ADC12_CH (11U) - -#define BOARD_APP_ADC16_NAME "ADC3" -#define BOARD_APP_ADC16_BASE HPM_ADC3 -#define BOARD_APP_ADC16_IRQn IRQn_ADC3 -#define BOARD_APP_ADC16_CH (2U) - -#define BOARD_APP_ADC_SEQ_DMA_SIZE_IN_4BYTES (1024U) -#define BOARD_APP_ADC_PMT_DMA_SIZE_IN_4BYTES (192U) -#define BOARD_APP_ADC_PREEMPT_TRIG_LEN (1U) -#define BOARD_APP_ADC_SINGLE_CONV_CNT (6) -#define BOARD_APP_ADC_TRIG_PWMT0 HPM_PWM0 -#define BOARD_APP_ADC_TRIG_PWMT1 HPM_PWM1 -#define BOARD_APP_ADC_TRIG_TRGM0 HPM_TRGM0 -#define BOARD_APP_ADC_TRIG_TRGM1 HPM_TRGM1 -#define BOARD_APP_ADC_TRIG_PWM_SYNC HPM_SYNT +#define BOARD_APP_ADC12_NAME "ADC0" +#define BOARD_APP_ADC12_BASE HPM_ADC0 +#define BOARD_APP_ADC12_IRQn IRQn_ADC0 +#define BOARD_APP_ADC12_CH_1 (11U) +#define BOARD_APP_ADC12_CLK_NAME (clock_adc0) + +#define BOARD_APP_ADC16_NAME "ADC3" +#define BOARD_APP_ADC16_BASE HPM_ADC3 +#define BOARD_APP_ADC16_IRQn IRQn_ADC3 +#define BOARD_APP_ADC16_CH_1 (2U) +#define BOARD_APP_ADC16_CLK_NAME (clock_adc3) + +#define BOARD_APP_ADC12_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC12_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC12_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_APP_ADC12_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI +#define BOARD_APP_ADC12_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A + +#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC3_STRGI +#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A + +#define BOARD_APP_ADC12_PMT_TRIG_CH ADC12_CONFIG_TRG0A +#define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A /* CAN section */ -#define BOARD_APP_CAN_BASE HPM_CAN0 -#define BOARD_APP_CAN_IRQn IRQn_CAN0 - +#define BOARD_APP_CAN_BASE HPM_CAN0 +#define BOARD_APP_CAN_IRQn IRQn_CAN0 /* * timer for board delay */ -#define BOARD_DELAY_TIMER (HPM_GPTMR7) -#define BOARD_DELAY_TIMER_CH 0 +#define BOARD_DELAY_TIMER (HPM_GPTMR7) +#define BOARD_DELAY_TIMER_CH 0 #define BOARD_DELAY_TIMER_CLK_NAME (clock_gptmr7) -#define BOARD_CALLBACK_TIMER (HPM_GPTMR7) -#define BOARD_CALLBACK_TIMER_CH 1 -#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR7 +#define BOARD_CALLBACK_TIMER (HPM_GPTMR7) +#define BOARD_CALLBACK_TIMER_CH 1 +#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR7 #define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr7) /* SDXC section */ -#define BOARD_APP_SDCARD_SDXC_BASE (HPM_SDXC1) -#define BOARD_APP_SDCARD_CDN_GPIO_CTRL (HPM_GPIO0) -#define BOARD_APP_SDCARD_CDN_GPIO_PIN (15UL) -#define BOARD_APP_SDCARD_SUPPORT_1V8 (0) +#define BOARD_APP_SDCARD_SDXC_BASE (HPM_SDXC1) +#define BOARD_APP_SDCARD_SUPPORT_3V3 (1) +#define BOARD_APP_SDCARD_SUPPORT_1V8 (0) +#define BOARD_APP_SDCARD_SUPPORT_4BIT (1) +#define BOARD_APP_SDCARD_SUPPORT_CARD_DETECTION (1) +#define BOARD_APP_SDCARD_SUPPORT_POWER_SWITCH (0) +#define BOARD_APP_SDCARD_SUPPORT_VOLTAGE_SWITCH (0) +#define BOARD_APP_SDCARD_SUPPORT_CARD_DETECTION (1) +#define BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO (1) +#if defined(BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO) && (BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO == 1) +#define BOARD_APP_SDCARD_CARD_DETECTION_PIN IOC_PAD_PD15 +#define BOARD_APP_SDCARD_CARD_DETECTION_PIN_POL 1 /* PIN value 0 means card is inserted */ +#endif + +#define BOARD_APP_EMMC_SDXC_BASE (HPM_SDXC1) +#define BOARD_APP_EMMC_SUPPORT_3V3 (1) +#define BOARD_APP_EMMC_SUPPORT_1V8 (0) +#define BOARD_APP_EMMC_SUPPORT_4BIT (1) +#define BOARD_APP_EMMC_HOST_USING_IRQ (0) /* USB section */ #define BOARD_USB0_ID_PORT (HPM_GPIO0) @@ -362,113 +416,115 @@ /*BLDC pwm*/ /*PWM define*/ -#define BOARD_BLDCPWM HPM_PWM2 -#define BOARD_BLDC_UH_PWM_OUTPIN (0U) -#define BOARD_BLDC_UL_PWM_OUTPIN (1U) -#define BOARD_BLDC_VH_PWM_OUTPIN (2U) -#define BOARD_BLDC_VL_PWM_OUTPIN (3U) -#define BOARD_BLDC_WH_PWM_OUTPIN (4U) -#define BOARD_BLDC_WL_PWM_OUTPIN (5U) -#define BOARD_BLDCPWM_TRGM HPM_TRGM2 -#define BOARD_BLDCAPP_PWM_IRQ IRQn_PWM2 -#define BOARD_BLDCPWM_CMP_INDEX_0 (0U) -#define BOARD_BLDCPWM_CMP_INDEX_1 (1U) -#define BOARD_BLDCPWM_CMP_INDEX_2 (2U) -#define BOARD_BLDCPWM_CMP_INDEX_3 (3U) -#define BOARD_BLDCPWM_CMP_INDEX_4 (4U) -#define BOARD_BLDCPWM_CMP_INDEX_5 (5U) +#define BOARD_BLDCPWM HPM_PWM2 +#define BOARD_BLDC_UH_PWM_OUTPIN (0U) +#define BOARD_BLDC_UL_PWM_OUTPIN (1U) +#define BOARD_BLDC_VH_PWM_OUTPIN (2U) +#define BOARD_BLDC_VL_PWM_OUTPIN (3U) +#define BOARD_BLDC_WH_PWM_OUTPIN (4U) +#define BOARD_BLDC_WL_PWM_OUTPIN (5U) +#define BOARD_BLDCPWM_TRGM HPM_TRGM2 +#define BOARD_BLDCAPP_PWM_IRQ IRQn_PWM2 +#define BOARD_BLDCPWM_CMP_INDEX_0 (0U) +#define BOARD_BLDCPWM_CMP_INDEX_1 (1U) +#define BOARD_BLDCPWM_CMP_INDEX_2 (2U) +#define BOARD_BLDCPWM_CMP_INDEX_3 (3U) +#define BOARD_BLDCPWM_CMP_INDEX_4 (4U) +#define BOARD_BLDCPWM_CMP_INDEX_5 (5U) +#define BOARD_BLDCPWM_CMP_INDEX_6 (6U) +#define BOARD_BLDCPWM_CMP_INDEX_7 (7U) +#define BOARD_BLDCPWM_CMP_TRIG_CMP (20U) /*HALL define*/ -#define BOARD_BLDC_HALL_BASE HPM_HALL2 -#define BOARD_BLDC_HALL_TRGM HPM_TRGM2 -#define BOARD_BLDC_HALL_IRQ IRQn_HALL2 -#define BOARD_BLDC_HALL_TRGM_HALL_U_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P6 -#define BOARD_BLDC_HALL_TRGM_HALL_V_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P7 -#define BOARD_BLDC_HALL_TRGM_HALL_W_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P8 -#define BOARD_BLDC_HALL_MOTOR_PHASE_COUNT_PER_REV (1000U) - - +#define BOARD_BLDC_HALL_BASE HPM_HALL2 +#define BOARD_BLDC_HALL_TRGM HPM_TRGM2 +#define BOARD_BLDC_HALL_IRQ IRQn_HALL2 +#define BOARD_BLDC_HALL_TRGM_HALL_U_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P6 +#define BOARD_BLDC_HALL_TRGM_HALL_V_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P7 +#define BOARD_BLDC_HALL_TRGM_HALL_W_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P8 +#define BOARD_BLDC_HALL_MOTOR_PHASE_COUNT_PER_REV (1000U) /*QEI*/ -#define BOARD_BLDC_QEI_BASE HPM_QEI2 -#define BOARD_BLDC_QEI_IRQ IRQn_QEI2 -#define BOARD_BLDC_QEI_TRGM HPM_TRGM2 -#define BOARD_BLDC_QEI_TRGM_QEI_A_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P9 -#define BOARD_BLDC_QEI_TRGM_QEI_B_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P10 -#define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV (16U) -#define BOARD_BLDC_QEI_CLOCK_SOURCE clock_mot2 -#define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV (4000U) +#define BOARD_BLDC_QEI_BASE HPM_QEI2 +#define BOARD_BLDC_QEI_IRQ IRQn_QEI2 +#define BOARD_BLDC_QEI_TRGM HPM_TRGM2 +#define BOARD_BLDC_QEI_TRGM_QEI_A_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P9 +#define BOARD_BLDC_QEI_TRGM_QEI_B_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P10 +#define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV (16U) +#define BOARD_BLDC_QEI_CLOCK_SOURCE clock_mot2 +#define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV (4000U) /*Timer define*/ -#define BOARD_TMR_1MS HPM_GPTMR2 -#define BOARD_TMR_1MS_CH 0 -#define BOARD_TMR_1MS_CMP 0 -#define BOARD_TMR_1MS_IRQ IRQn_GPTMR2 -#define BOARD_TMR_1MS_RELOAD (100000U) +#define BOARD_TMR_1MS HPM_GPTMR2 +#define BOARD_TMR_1MS_CH 0 +#define BOARD_TMR_1MS_CMP 0 +#define BOARD_TMR_1MS_IRQ IRQn_GPTMR2 +#define BOARD_TMR_1MS_RELOAD (100000U) -#define BOARD_BLDC_TMR_1MS BOARD_TMR_1MS -#define BOARD_BLDC_TMR_CH BOARD_TMR_1MS_CH -#define BOARD_BLDC_TMR_CMP BOARD_TMR_1MS_CMP -#define BOARD_BLDC_TMR_IRQ BOARD_TMR_1MS_IRQ -#define BOARD_BLDC_TMR_RELOAD BOARD_TMR_1MS_RELOAD -#define BOARD_BLDC_ADC_TRG ADC12_CONFIG_TRG2A +#define BOARD_BLDC_TMR_1MS BOARD_TMR_1MS +#define BOARD_BLDC_TMR_CH BOARD_TMR_1MS_CH +#define BOARD_BLDC_TMR_CMP BOARD_TMR_1MS_CMP +#define BOARD_BLDC_TMR_IRQ BOARD_TMR_1MS_IRQ +#define BOARD_BLDC_TMR_RELOAD BOARD_TMR_1MS_RELOAD /*adc*/ -#define BOARD_BLDC_ADC_MODULE ADCX_MODULE_ADC12 -#define BOARD_BLDC_ADC_U_BASE HPM_ADC0 -#define BOARD_BLDC_ADC_V_BASE HPM_ADC1 -#define BOARD_BLDC_ADC_W_BASE HPM_ADC2 -#define BOARD_BLDC_ADC_TRIG_FLAG adc12_event_trig_complete - -#define BOARD_BLDC_ADC_CH_U (7U) -#define BOARD_BLDC_ADC_CH_V (10U) -#define BOARD_BLDC_ADC_CH_W (11U) -#define BOARD_BLDC_ADC_IRQn IRQn_ADC0 -#define BOARD_BLDC_ADC_SEQ_DMA_SIZE_IN_4BYTES (40U) +#define BOARD_BLDC_ADC_MODULE ADCX_MODULE_ADC12 +#define BOARD_BLDC_ADC_U_BASE HPM_ADC0 +#define BOARD_BLDC_ADC_V_BASE HPM_ADC1 +#define BOARD_BLDC_ADC_W_BASE HPM_ADC2 +#define BOARD_BLDC_ADC_TRIG_FLAG adc12_event_trig_complete + +#define BOARD_BLDC_ADC_CH_U (7U) +#define BOARD_BLDC_ADC_CH_V (10U) +#define BOARD_BLDC_ADC_CH_W (11U) +#define BOARD_BLDC_ADC_IRQn IRQn_ADC0 +#define BOARD_BLDC_ADC_PMT_DMA_SIZE_IN_4BYTES (ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES) #define BOARD_BLDC_ADC_TRG ADC12_CONFIG_TRG2A -#define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) -#define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U) -#define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM2_INPUT_SRC_PWM2_CH8REF -#define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A -#define BOARD_BLDC_ADC_IRQn IRQn_ADC0 +#define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) +#define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U) +#define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM2_INPUT_SRC_PWM2_CH8REF +#define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A +#define BOARD_BLDC_ADC_IRQn IRQn_ADC0 /* APP PWM */ -#define BOARD_APP_PWM HPM_PWM2 -#define BOARD_APP_PWM_CLOCK_NAME clock_mot2 -#define BOARD_APP_PWM_OUT1 0 -#define BOARD_APP_PWM_OUT2 1 -#define BOARD_APP_TRGM HPM_TRGM2 +#define BOARD_APP_PWM HPM_PWM2 +#define BOARD_APP_PWM_CLOCK_NAME clock_mot2 +#define BOARD_APP_PWM_OUT1 0 +#define BOARD_APP_PWM_OUT2 1 +#define BOARD_APP_TRGM HPM_TRGM2 +#define BOARD_APP_PWM_IRQ IRQn_PWM2 +#define BOARD_APP_TRGM_PWM_OUTPUT TRGM_TRGOCFG_PWM_SYNCI /* RGB LED Section */ -#define BOARD_RED_PWM_IRQ IRQn_PWM1 -#define BOARD_RED_PWM HPM_PWM1 -#define BOARD_RED_PWM_OUT 8 -#define BOARD_RED_PWM_CMP 8 +#define BOARD_RED_PWM_IRQ IRQn_PWM1 +#define BOARD_RED_PWM HPM_PWM1 +#define BOARD_RED_PWM_OUT 8 +#define BOARD_RED_PWM_CMP 8 #define BOARD_RED_PWM_CMP_INITIAL_ZERO true -#define BOARD_RED_PWM_CLOCK_NAME clock_mot1 +#define BOARD_RED_PWM_CLOCK_NAME clock_mot1 -#define BOARD_GREEN_PWM_IRQ IRQn_PWM0 -#define BOARD_GREEN_PWM HPM_PWM0 -#define BOARD_GREEN_PWM_OUT 8 -#define BOARD_GREEN_PWM_CMP 8 +#define BOARD_GREEN_PWM_IRQ IRQn_PWM0 +#define BOARD_GREEN_PWM HPM_PWM0 +#define BOARD_GREEN_PWM_OUT 8 +#define BOARD_GREEN_PWM_CMP 8 #define BOARD_GREEN_PWM_CMP_INITIAL_ZERO true -#define BOARD_GREEN_PWM_CLOCK_NAME clock_mot0 +#define BOARD_GREEN_PWM_CLOCK_NAME clock_mot0 -#define BOARD_BLUE_PWM_IRQ IRQn_PWM1 -#define BOARD_BLUE_PWM HPM_PWM1 -#define BOARD_BLUE_PWM_OUT 9 -#define BOARD_BLUE_PWM_CMP 9 +#define BOARD_BLUE_PWM_IRQ IRQn_PWM1 +#define BOARD_BLUE_PWM HPM_PWM1 +#define BOARD_BLUE_PWM_OUT 9 +#define BOARD_BLUE_PWM_CMP 9 #define BOARD_BLUE_PWM_CMP_INITIAL_ZERO true -#define BOARD_BLUE_PWM_CLOCK_NAME clock_mot1 +#define BOARD_BLUE_PWM_CLOCK_NAME clock_mot1 -#define BOARD_RGB_RED 0 +#define BOARD_RGB_RED 0 #define BOARD_RGB_GREEN (BOARD_RGB_RED + 1) #define BOARD_RGB_BLUE (BOARD_RGB_RED + 2) -#define BOARD_CPU_FREQ (816000000UL) +#define BOARD_CPU_FREQ (648000000UL) #define BOARD_APP_DISPLAY_CLOCK clock_display @@ -479,6 +535,21 @@ #define BOARD_SHOW_BANNER 1 #endif +/* FreeRTOS Definitions */ +#define BOARD_FREERTOS_TIMER HPM_GPTMR4 +#define BOARD_FREERTOS_TIMER_CHANNEL 1 +#define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR4 +#define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr4 + +/* Threadx Definitions */ +#define BOARD_THREADX_TIMER HPM_GPTMR4 +#define BOARD_THREADX_TIMER_CHANNEL 1 +#define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR4 +#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr4 +/* Tamper Section */ +#define BOARD_TAMP_ACTIVE_CH 8 +#define BOARD_TAMP_LOW_LEVEL_CH 10 + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ @@ -488,9 +559,12 @@ typedef void (*board_timer_cb)(void); void board_init(void); void board_init_console(void); +void board_init_core1(void); + void board_init_uart(UART_Type *ptr); void board_init_i2c(I2C_Type *ptr); void board_init_lcd(void); +void board_lcd_backlight(bool is_on); void board_panel_para_to_lcdc(lcdc_config_t *config); void board_init_can(CAN_Type *ptr); @@ -499,6 +573,8 @@ uint32_t board_init_femc_clock(void); void board_init_sdram_pins(void); void board_init_gpio_pins(void); void board_init_spi_pins(SPI_Type *ptr); +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); +void board_write_spi_cs(uint32_t pin, uint8_t state); void board_init_led_pins(void); /* cap touch */ @@ -526,21 +602,26 @@ uint32_t board_init_lcd_clock(void); uint32_t board_init_spi_clock(SPI_Type *ptr); -uint32_t board_init_adc12_clock(ADC12_Type *ptr); +uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb); -uint32_t board_init_adc16_clock(ADC16_Type *ptr); +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb); uint32_t board_init_can_clock(CAN_Type *ptr); + +uint32_t board_init_pwm_clock(PWM_Type *ptr); + uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); +hpm_stat_t board_set_audio_pll_clock(uint32_t freq); + +void board_init_i2s_pins(I2S_Type *ptr); uint32_t board_init_i2s_clock(I2S_Type *ptr); +uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate); uint32_t board_init_pdm_clock(void); uint32_t board_init_dao_clock(void); -void board_init_sd_pins(SDXC_Type *ptr); -uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq); -void board_sd_switch_pins_to_1v8(SDXC_Type *ptr); -bool board_sd_detect_card(SDXC_Type *ptr); -void board_sd_power_switch(SDXC_Type *ptr, bool on_off); +uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inverse); + +void board_init_dao_pins(void); void board_init_adc12_pins(void); void board_init_adc16_pins(void); @@ -548,13 +629,25 @@ void board_init_adc16_pins(void); void board_init_usb_pins(void); void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); -uint8_t board_enet_get_dma_pbl(ENET_Type *ptr); -hpm_stat_t board_init_enet_pins(ENET_Type *ptr); +void board_init_enet_pps_pins(ENET_Type *ptr); +uint8_t board_get_enet_dma_pbl(ENET_Type *ptr); hpm_stat_t board_reset_enet_phy(ENET_Type *ptr); hpm_stat_t board_init_enet_pins(ENET_Type *ptr); hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal); - +hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr); hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr); +hpm_stat_t board_enable_enet_irq(ENET_Type *ptr); +hpm_stat_t board_disable_enet_irq(ENET_Type *ptr); + +#if defined(ENET_MULTIPLE_PORT) && ENET_MULTIPLE_PORT +hpm_stat_t board_init_multiple_enet_pins(void); +hpm_stat_t board_init_multiple_enet_clock(void); +hpm_stat_t board_reset_multiple_enet_phy(void); +hpm_stat_t board_init_enet_phy(ENET_Type *ptr); +ENET_Type *board_get_enet_base(uint8_t idx); +uint8_t board_get_enet_phy_itf(uint8_t idx); +void board_get_enet_phy_status(uint8_t idx, void *status); +#endif /* * @brief Initialize PMP and PMA for but not limited to the following purposes: @@ -563,6 +656,7 @@ hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr); void board_init_pmp(void); void board_delay_ms(uint32_t ms); +void board_delay_us(uint32_t us); void board_timer_create(uint32_t ms, board_timer_cb cb); @@ -575,6 +669,19 @@ void board_disable_output_rgb_led(uint8_t color); */ void board_ungate_mchtmr_at_lp_mode(void); +/* + * Get PWM output level of onboard LED + */ +uint8_t board_get_led_pwm_off_level(void); + +/* + * Get GPIO pin level of onboard LED + */ +uint8_t board_get_led_gpio_off_level(void); + +void board_init_trgm0_p6_pin(void); + +void board_sd_power_switch(SDXC_Type *ptr, bool on_off); #if defined(__cplusplus) } diff --git a/bsp/hpmicro/hpm6750evk/board/eth_phy_port.c b/bsp/hpmicro/hpm6750evk/board/eth_phy_port.c deleted file mode 100644 index 6df7441742e..00000000000 --- a/bsp/hpmicro/hpm6750evk/board/eth_phy_port.c +++ /dev/null @@ -1,320 +0,0 @@ -/* - * Copyright (c) 2022 hpmicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - * Change Logs: - * Date Author Notes - * 2022-01-11 hpmicro First version - */ - -#include "rtthread.h" - -#ifdef RT_USING_PHY -#include -#include -#include "hpm_enet_drv.h" -#include "eth_phy_port.h" -#include "hpm_soc.h" -#include "netif/ethernetif.h" -#include "board.h" - -typedef struct -{ - char *mdio_name; - ENET_Type *instance; - struct eth_device *eth_dev; - phy_device_t *phy_dev; - struct rt_mdio_bus *mdio_bus; -} eth_phy_handle_t; - -typedef struct -{ - uint8_t phy_handle_cnt; - eth_phy_handle_t **phy_handle; -} eth_phy_monitor_handle_t; - -#ifdef BSP_USING_ETH0 -extern struct eth_device eth0_dev; -static struct rt_mdio_bus mdio0_bus; -static phy_device_t phy0_dev; -static uint8_t phy0_reg_list[]= {PHY0_REG_LIST}; - -static eth_phy_handle_t eth0_phy_handle = -{ - .instance = HPM_ENET0, - .eth_dev = ð0_dev, - .phy_dev = &phy0_dev, - .mdio_name = "MDIO0", - .mdio_bus = &mdio0_bus, -}; -#endif - -#ifdef BSP_USING_ETH1 -extern struct eth_device eth1_dev; -static struct rt_mdio_bus mdio1_bus; -static phy_device_t phy1_dev; -static uint8_t phy1_reg_list[]= {PHY1_REG_LIST}; - -static eth_phy_handle_t eth1_phy_handle = -{ - .instance = HPM_ENET1, - .eth_dev = ð1_dev, - .phy_dev = &phy1_dev, - .mdio_name = "MDIO1", - .mdio_bus = &mdio1_bus, -}; -#endif - -static eth_phy_handle_t *s_gphys[] = -{ -#ifdef BSP_USING_ETH0 -ð0_phy_handle, -#endif - -#ifdef BSP_USING_ETH1 -ð1_phy_handle -#endif -}; - -static uint8_t *s_gphy_reg_list[] = -{ -#ifdef BSP_USING_ETH0 -phy0_reg_list, -#endif - -#ifdef BSP_USING_ETH1 -phy1_reg_list, -#endif -}; - -eth_phy_monitor_handle_t phy_monitor_handle = -{ - .phy_handle_cnt = ARRAY_SIZE(s_gphys), - .phy_handle = s_gphys -}; - -static struct rt_phy_ops phy_ops; - -static rt_phy_status phy_init(void *object, rt_uint32_t phy_addr, rt_uint32_t src_clock_hz) -{ - return PHY_STATUS_OK; -} - -static rt_size_t phy_read(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size) -{ - *(uint16_t *)data = enet_read_phy(((struct rt_mdio_bus *)bus)->hw_obj, addr, reg); - - return size; -} - -static rt_size_t phy_write(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size) -{ - enet_write_phy(((struct rt_mdio_bus *)bus)->hw_obj, addr, reg, *(uint16_t *)data); - - return size; -} - -static rt_phy_status phy_get_link_status(rt_phy_t *phy, rt_bool_t *status) -{ - uint16_t reg_status; - - reg_status = enet_read_phy(phy->bus->hw_obj, phy->addr, phy->reg_list[PHY_BASIC_STATUS_REG_IDX]); - - #if PHY_AUTO_NEGO - reg_status &= PHY_AUTONEGO_COMPLETE_MASK | PHY_LINKED_STATUS_MASK; - *status = reg_status ? RT_TRUE : RT_FALSE; - - #else - reg_status &= PHY_LINKED_STATUS_MASK; - *status = reg_status ? RT_TRUE : RT_FALSE; - #endif - - return PHY_STATUS_OK; -} - -static rt_phy_status phy_get_link_speed_duplex(rt_phy_t *phy, rt_uint32_t *speed, rt_uint32_t *duplex) -{ - uint16_t reg_status; - - reg_status = enet_read_phy(phy->bus->hw_obj, phy->addr, phy->reg_list[PHY_STATUS_REG_IDX]); -#if RGMII - if (PHY_STATUS_SPEED_1000M(reg_status)) - { - *speed = PHY_SPEED_1000M; - } - else if (PHY_STATUS_SPEED_100M(reg_status)) - { - *speed = PHY_SPEED_100M; - } - else - { - *speed = PHY_SPEED_10M; - } -#else - if (PHY_STATUS_SPEED_10M(reg_status)) - { - *speed = PHY_SPEED_10M; - } - else - { - *speed = PHY_SPEED_100M; - } -#endif - *duplex = PHY_STATUS_FULL_DUPLEX(reg_status) ? PHY_FULL_DUPLEX: PHY_HALF_DUPLEX; - - return PHY_STATUS_OK; -} - -static void phy_poll_status(void *parameter) -{ - int ret; - phy_info_t phy_info; - rt_bool_t status; - rt_device_t dev; - rt_phy_msg_t msg; - rt_uint32_t speed, duplex; - phy_device_t *phy_dev; - struct eth_device* eth_dev; - char const *ps[] = {"10Mbps", "100Mbps", "1000Mbps"}; - enet_line_speed_t line_speed[] = {enet_line_speed_10mbps, enet_line_speed_100mbps, enet_line_speed_1000mbps}; - - eth_phy_monitor_handle_t *phy_monitor_handle = (eth_phy_monitor_handle_t *)parameter; - - for (uint32_t i = 0; i < phy_monitor_handle->phy_handle_cnt; i++) - { - eth_dev = phy_monitor_handle->phy_handle[i]->eth_dev; - phy_dev = phy_monitor_handle->phy_handle[i]->phy_dev; - - phy_dev->phy.ops->get_link_status(&phy_dev->phy, &status); - - if (status) - { - phy_dev->phy.ops->get_link_speed_duplex(&phy_dev->phy, &phy_info.phy_speed, &phy_info.phy_duplex); - - ret = memcmp(&phy_dev->phy_info, &phy_info, sizeof(phy_info_t)); - if (ret != 0) - { - memcpy(&phy_dev->phy_info, &phy_info, sizeof(phy_info_t)); - } - } - - if (phy_dev->phy_link != status) - { - phy_dev->phy_link = status ? PHY_LINK_UP : PHY_LINK_DOWN; - eth_device_linkchange(eth_dev, status); - LOG_I("PHY Status: %s", status ? "Link up" : "Link down\n"); - if (status == PHY_LINK_UP) - { - LOG_I("PHY Speed: %s", ps[phy_dev->phy_info.phy_speed]); - LOG_I("PHY Duplex: %s\n", phy_dev->phy_info.phy_duplex & PHY_FULL_DUPLEX ? "full duplex" : "half duplex"); - enet_set_line_speed(phy_monitor_handle->phy_handle[i]->instance, line_speed[phy_dev->phy_info.phy_speed]); - enet_set_duplex_mode(phy_monitor_handle->phy_handle[i]->instance, phy_dev->phy_info.phy_duplex); - } - } - } -} - -static void phy_detection(void *parameter) -{ - uint8_t detected_count = 0; - struct rt_phy_msg msg = {0, 0}; - phy_device_t *phy_dev = (phy_device_t *)parameter; - rt_uint32_t i; - - msg.reg = phy_dev->phy.reg_list[PHY_ID1_REG_IDX]; - phy_dev->phy.ops->init(phy_dev->phy.bus->hw_obj, phy_dev->phy.addr, PHY_MDIO_CSR_CLK_FREQ); - - while(phy_dev->phy.addr == 0xffff) - { - /* Search a PHY */ - for (i = 0; i <= 0x1f; i++) - { - ((rt_phy_t *)(phy_dev->phy.parent.user_data))->addr = i; - phy_dev->phy.parent.read(&(phy_dev->phy.parent), 0, &msg, 1); - - if (msg.value == PHY_ID1) - { - phy_dev->phy.addr = i; - LOG_D("Found a PHY device[address:0x%02x].\n", phy_dev->phy.addr); - return; - } - } - - phy_dev->phy.addr = 0xffff; - detected_count++; - rt_thread_mdelay(1000); - - if (detected_count > 3) - { - LOG_E("No any PHY device is detected! Please check your hardware!\n"); - return; - } - } -} - -static void phy_monitor_thread_entry(void *args) -{ - rt_timer_t phy_status_timer; - - eth_phy_monitor_handle_t *phy_monitor_handle = (eth_phy_monitor_handle_t *)args; - - for (uint32_t i = 0; i < phy_monitor_handle->phy_handle_cnt; i++) - { - LOG_D("Detect a PHY%d\n", i); - phy_detection(phy_monitor_handle->phy_handle[i]->phy_dev); - } - - phy_status_timer = rt_timer_create("PHY_Monitor", phy_poll_status, phy_monitor_handle, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC | RT_TIMER_FLAG_SOFT_TIMER); - - if (!phy_status_timer || rt_timer_start(phy_status_timer) != RT_EOK) - { - LOG_E("Failed to start link change detection timer\n"); - } -} - -int phy_device_register(void) -{ - rt_err_t err = RT_ERROR; - rt_thread_t thread_phy_monitor; - - /* Set ops for PHY */ - phy_ops.init = phy_init; - phy_ops.get_link_status = phy_get_link_status; - phy_ops.get_link_speed_duplex = phy_get_link_speed_duplex; - - for (uint32_t i = 0; i < ARRAY_SIZE(s_gphys); i++) - { - /* Set PHY address */ - s_gphys[i]->phy_dev->phy.addr = 0xffff; - - /* Set MIDO bus */ - s_gphys[i]->mdio_bus->hw_obj = s_gphys[i]->instance; - s_gphys[i]->mdio_bus->name = s_gphys[i]->mdio_name; - s_gphys[i]->mdio_bus->ops->read = phy_read; - s_gphys[i]->mdio_bus->ops->write = phy_write; - s_gphys[i]->phy_dev->phy.bus = s_gphys[i]->mdio_bus; - s_gphys[i]->phy_dev->phy.ops = &phy_ops; - - /* Set PHY register list */ - s_gphys[i]->phy_dev->phy.reg_list = s_gphy_reg_list[i]; - - rt_hw_phy_register(&s_gphys[i]->phy_dev->phy, PHY_NAME); - } - - /* Start PHY monitor */ - thread_phy_monitor = rt_thread_create("PHY Monitor", phy_monitor_thread_entry, &phy_monitor_handle, 1024, RT_THREAD_PRIORITY_MAX - 2, 2); - - if (thread_phy_monitor != RT_NULL) - { - rt_thread_startup(thread_phy_monitor); - } - else - { - err = RT_ERROR; - } - - return err; -} -INIT_PREV_EXPORT(phy_device_register); -#endif /* RT_USING_PHY */ diff --git a/bsp/hpmicro/hpm6750evk/board/eth_phy_port.h b/bsp/hpmicro/hpm6750evk/board/eth_phy_port.h deleted file mode 100644 index 86329526601..00000000000 --- a/bsp/hpmicro/hpm6750evk/board/eth_phy_port.h +++ /dev/null @@ -1,158 +0,0 @@ -/* - * Copyright (c) 2021 hpmicro - * - * SPDX-License-Identifier: BSD-3-Clause - * -*/ - -#ifndef ETH_PHY_PORT_H -#define ETH_PHY_PORT_H - -#include "hpm_ioc_regs.h" -#include - -#ifndef PHY_AUTO_NEGO -#define PHY_AUTO_NEGO (1U) -#endif - -#ifndef PHY_MDIO_CSR_CLK_FREQ -#define PHY_MDIO_CSR_CLK_FREQ (200000000U) -#endif - -enum phy_link_status -{ - PHY_LINK_DOWN = 0U, - PHY_LINK_UP -}; - -typedef struct { - rt_uint32_t phy_speed; - rt_uint32_t phy_duplex; -} phy_info_t; - -typedef struct { - rt_uint32_t phy_link; - rt_phy_t phy; - phy_info_t phy_info; -} phy_device_t; - -#ifdef BSP_USING_ETH0 - - #define RGMII (1U) - - /* DP83867 name and ID */ - #define PHY_NAME ("DP83867") - #define PHY_ID1 (0x2000U) - #define PHY_ID2 (0x28U) - - /* PHY_DP83867 basic control register */ - #define PHY_BASIC_CONTROL_REG (0x00U) - #define PHY_RESET_MASK (1U << 15) - #define PHY_AUTO_NEGOTIATION_MASK (1U << 12) - - /* PHY_DP83867 basic status register */ - #define PHY_BASIC_STATUS_REG (0x01U) - #define PHY_LINKED_STATUS_MASK (1U << 2) - #define PHY_AUTONEGO_COMPLETE_MASK (1U << 5) - - /* PHY_DP83867 ID one register */ - #define PHY_ID1_REG (0x02U) - - /* PHY_DP83867 ID two register */ - #define PHY_ID2_REG (0x03U) - - /* PHY_DP83867 auto-negotiate advertise register */ - #define PHY_AUTONEG_ADVERTISE_REG (0x04U) - - /* PHY_DP83867 status register */ - #define PHY_STATUS_REG (0x11U) - #define PHY_100M_MASK (1UL << 14) - #define PHY_1000M_MASK (1UL << 15) - #define PHY_FULL_DUPLEX_MASK (1UL << 13) - #define PHY_STATUS_SPEED_100M(SR) ((SR) & PHY_100M_MASK) - #define PHY_STATUS_SPEED_1000M(SR) ((SR) & PHY_1000M_MASK) - #define PHY_STATUS_FULL_DUPLEX(SR) ((SR) & PHY_FULL_DUPLEX_MASK) - #define PHY_SPEED_SEL_SHIFT (14U) - /* PHY_DP83867 interrupt control register */ - #define PHY_INTERTUPT_CTRL_REG (0x12U) - - /* PHY_DP83867 interrupt status register */ - #define PHY_INTERRUPT_STATUS_REG (0x13U) - - /* PHY register index */ - typedef enum { - PHY_BASIC_CONTROL_REG_IDX = 0, - PHY_BASIC_STATUS_REG_IDX, - PHY_ID1_REG_IDX, - PHY_ID2_REG_IDX, - PHY_AUTONEG_ADVERTISE_REG_IDX, - PHY_STATUS_REG_IDX, - PHY_INTERRUPT_FLAG_REG_IDX, - PHY_INTERRUPT_MASK_REG_IDX - } phy_reg_idx_t; - - /* ETH0 PHY register list */ - #define PHY0_REG_LIST PHY_BASIC_CONTROL_REG,\ - PHY_BASIC_STATUS_REG,\ - PHY_ID1_REG,\ - PHY_ID2_REG,\ - PHY_AUTONEG_ADVERTISE_REG,\ - PHY_STATUS_REG,\ - PHY_INTERTUPT_CTRL_REG,\ - PHY_INTERRUPT_STATUS_REG - -#else - #define RMII (1U) - - /* DP83848 name and ID */ - #define PHY_NAME ("DP83848") - #define PHY_ID1 (0x2000U) - #define PHY_ID2 (0x17U) - - /* DP83848 basic control register */ - #define PHY_BASIC_CONTROL_REG (0x00U) - #define PHY_RESET_MASK (1U << 15) - #define PHY_AUTO_NEGOTIATION_MASK (1U << 12) - - /* DP83848 basic status register */ - #define PHY_BASIC_STATUS_REG (0x01U) - #define PHY_LINKED_STATUS_MASK (1U << 2) - #define PHY_AUTONEGO_COMPLETE_MASK (1U << 5) - - /* DP83848 ID one register */ - #define PHY_ID1_REG (0x02U) - - /* DP83848 ID two register */ - #define PHY_ID2_REG (0x03U) - - /* DP83848 auto-negotiate advertise register */ - #define PHY_AUTONEG_ADVERTISE_REG (0x04U) - - /* DP83848 status register */ - #define PHY_STATUS_REG (0x10U) - #define PHY_10M_MASK (1UL << 1) - #define PHY_FULL_DUPLEX_MASK (1UL << 2) - #define PHY_STATUS_SPEED_10M(SR) ((SR) & PHY_10M_MASK) - #define PHY_STATUS_FULL_DUPLEX(SR) ((SR) & PHY_FULL_DUPLEX_MASK) - - /* PHY register index */ - typedef enum { - PHY_BASIC_CONTROL_REG_IDX = 0, - PHY_BASIC_STATUS_REG_IDX, - PHY_ID1_REG_IDX, - PHY_ID2_REG_IDX, - PHY_AUTONEG_ADVERTISE_REG_IDX, - PHY_STATUS_REG_IDX, - } phy_reg_idx_t; - - /* ETH0 PHY register list */ - #define PHY1_REG_LIST PHY_BASIC_CONTROL_REG,\ - PHY_BASIC_STATUS_REG,\ - PHY_ID1_REG,\ - PHY_ID2_REG,\ - PHY_AUTONEG_ADVERTISE_REG,\ - PHY_STATUS_REG - -#endif -#endif - diff --git a/bsp/hpmicro/hpm6750evk/board/fal_cfg.h b/bsp/hpmicro/hpm6750evk/board/fal_cfg.h index b315dd87c38..3533c1fbb2c 100644 --- a/bsp/hpmicro/hpm6750evk/board/fal_cfg.h +++ b/bsp/hpmicro/hpm6750evk/board/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023 HPMicro + * Copyright (c) 2022 hpmicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -28,6 +28,13 @@ extern struct fal_flash_dev nor_flash0; /* ====================== Partition Configuration ========================== */ #ifdef FAL_PART_HAS_TABLE_CFG /* partition table */ +#ifdef CONFIG_WEBNET_FAL_FS +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WORD, "app", NOR_FLASH_DEV_NAME, 0, 6*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "fs", NOR_FLASH_DEV_NAME, 6*1024*1024, 10*1024*1024, 0}, \ +} +#else #define FAL_PART_TABLE \ { \ {FAL_PART_MAGIC_WORD, "app", NOR_FLASH_DEV_NAME, 0, 4*1024*1024, 0}, \ @@ -35,6 +42,7 @@ extern struct fal_flash_dev nor_flash0; {FAL_PART_MAGIC_WORD, "download", NOR_FLASH_DEV_NAME, 7*1024*1024, 8*1024*1024, 0}, \ {FAL_PART_MAGIC_WORD, "flashdb", NOR_FLASH_DEV_NAME, 15*1024*1024, 1*1024*1024, 0}, \ } +#endif #endif /* FAL_PART_HAS_TABLE_CFG */ #endif /* RT_USING_FAL */ diff --git a/bsp/hpmicro/hpm6750evk/board/fal_flash_port.c b/bsp/hpmicro/hpm6750evk/board/fal_flash_port.c index 12d5b3daa4d..57418e35514 100644 --- a/bsp/hpmicro/hpm6750evk/board/fal_flash_port.c +++ b/bsp/hpmicro/hpm6750evk/board/fal_flash_port.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023 HPMicro + * Copyright (c) 2022 hpmicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/hpm6750evk/board/hpm_sgtl5000.c b/bsp/hpmicro/hpm6750evk/board/hpm_sgtl5000.c index ebe335a2354..0be4618a24f 100644 --- a/bsp/hpmicro/hpm6750evk/board/hpm_sgtl5000.c +++ b/bsp/hpmicro/hpm6750evk/board/hpm_sgtl5000.c @@ -10,21 +10,9 @@ #include #include "hpm_sgtl5000.h" -/******************************************************************************* - * Definitations - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ +#ifndef HPM_SGTL5000_MCLK_TOLERANCE +#define HPM_SGTL5000_MCLK_TOLERANCE (4U) +#endif hpm_stat_t sgtl_init(sgtl_context_t *context, sgtl_config_t *config) { @@ -56,7 +44,7 @@ hpm_stat_t sgtl_init(sgtl_context_t *context, sgtl_config_t *config) /* Volume and Mute Control Configure HP_OUT left and right volume to minimum, unmute. HP_OUT and ramp the volume up to desired volume.*/ - if (sgtl_write_reg(context, CHIP_ANA_HP_CTRL, 0x1818U) != status_success) + if (sgtl_write_reg(context, CHIP_ANA_HP_CTRL, 0x0C0CU) != status_success) { return status_fail; } @@ -470,11 +458,20 @@ hpm_stat_t sgtl_set_mute(sgtl_context_t *context, sgtl_module_t module, bool mut return stat; } +static bool sgtl_check_clock_tolerance(uint32_t source, uint32_t target) +{ + uint32_t delta = (source >= target) ? (source - target) : (target - source); + if (delta * 100 <= HPM_SGTL5000_MCLK_TOLERANCE * target) { + return true; + } + return false; +} + hpm_stat_t sgtl_config_data_format(sgtl_context_t *context, uint32_t mclk, uint32_t sample_rate, uint32_t bits) { uint16_t val = 0; uint16_t regVal = 0; - uint16_t mul_clk = 0U; + uint32_t mul_div = 0U; uint32_t sysFs = 0U; hpm_stat_t stat = status_success; @@ -574,21 +571,18 @@ hpm_stat_t sgtl_config_data_format(sgtl_context_t *context, uint32_t mclk, uint3 return status_fail; } - /* While as slave, Fs is input */ - if ((regVal & SGTL5000_I2S_MS_GET_MASK) == 0U) - { - sysFs = sample_rate; - } - mul_clk = (uint16_t)(mclk / sysFs); - /* Configure the mul_clk. Sgtl-5000 only support 256, 384 and 512 oversample rate */ - if ((mul_clk / 128U - 2U) > 2U) - { + mul_div = mclk / sysFs; + + if (sgtl_check_clock_tolerance(mul_div, 256)) { + mul_div = 256; + } else if (sgtl_check_clock_tolerance(mul_div, 384)) { + mul_div = 384; + } else if (sgtl_check_clock_tolerance(mul_div, 512)) { + mul_div = 512; + } else { return status_invalid_argument; } - else - { - val |= (mul_clk / 128U - 2U); - } + val |= (mul_div / 128U - 2U); if (sgtl_write_reg(context, CHIP_CLK_CTRL, val) != status_success) { diff --git a/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt.ld b/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt.ld index 0d29b2257e5..5317b8a6f80 100644 --- a/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt.ld +++ b/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt.ld @@ -141,6 +141,12 @@ SECTIONS /* RT-Thread related sections - end */ + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + } > XPI0 .rel : { diff --git a/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt_enet.ld b/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt_enet.ld index e98a75c1219..f1d2bf25ac5 100644 --- a/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt_enet.ld +++ b/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt_enet.ld @@ -72,14 +72,16 @@ SECTIONS KEEP(*irq.o (.text .text* .rodata .rodata*)) KEEP(*clock.o (.text .text* .rodata .rodata*)) KEEP(*kservice.o (.text .text* .rodata .rodata*)) - KEEP(*scheduler.o (.text .text* .rodata .rodata*)) + KEEP(*scheduler*.o (.text .text* .rodata .rodata*)) KEEP(*trap*.o (.text .text* .rodata .rodata*)) KEEP(*idle.o (.text .text* .rodata .rodata*)) KEEP(*ipc.o (.text .text* .rodata .rodata*)) + KEEP(*slab.o (.text .text* .rodata .rodata*)) KEEP(*thread.o (.text .text* .rodata .rodata*)) KEEP(*object.o (.text .text* .rodata .rodata*)) KEEP(*timer.o (.text .text* .rodata .rodata*)) KEEP(*mem.o (.text .text* .rodata .rodata*)) + KEEP(*memheap.o (.text .text* .rodata .rodata*)) KEEP(*mempool.o (.text .text* .rodata .rodata*)) /* RT-Thread Core End */ @@ -163,6 +165,12 @@ SECTIONS /* RT-Thread related sections - end */ + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + } > XPI0 .rel : { diff --git a/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_sdram_rtt.ld b/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_sdram_rtt.ld index ed0fce209d0..218084bf969 100644 --- a/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_sdram_rtt.ld +++ b/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_sdram_rtt.ld @@ -141,6 +141,12 @@ SECTIONS /* RT-Thread related sections - end */ + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + } > XPI0 .rel : { diff --git a/bsp/hpmicro/hpm6750evk/board/linker_scripts/ram_rtt.ld b/bsp/hpmicro/hpm6750evk/board/linker_scripts/ram_rtt.ld index c3c0f2cf4ef..97483a9e302 100644 --- a/bsp/hpmicro/hpm6750evk/board/linker_scripts/ram_rtt.ld +++ b/bsp/hpmicro/hpm6750evk/board/linker_scripts/ram_rtt.ld @@ -87,6 +87,12 @@ SECTIONS /* RT-Thread related sections - end */ + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); @@ -225,10 +231,6 @@ SECTIONS KEEP(*(.backup_sram)) } > APB_SRAM - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - .stack(NOLOAD) : { . = ALIGN(8); __stack_base__ = .; diff --git a/bsp/hpmicro/hpm6750evk/board/linker_scripts/ram_sdram_rtt.ld b/bsp/hpmicro/hpm6750evk/board/linker_scripts/ram_sdram_rtt.ld index dedb377ad31..cd15d78304c 100644 --- a/bsp/hpmicro/hpm6750evk/board/linker_scripts/ram_sdram_rtt.ld +++ b/bsp/hpmicro/hpm6750evk/board/linker_scripts/ram_sdram_rtt.ld @@ -87,6 +87,12 @@ SECTIONS /* RT-Thread related sections - end */ + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); @@ -225,10 +231,6 @@ SECTIONS KEEP(*(.backup_sram)) } > APB_SRAM - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - .stack(NOLOAD) : { . = ALIGN(8); __stack_base__ = .; diff --git a/bsp/hpmicro/hpm6750evk/board/pinmux.c b/bsp/hpmicro/hpm6750evk/board/pinmux.c index 67ff6a39b3e..8056ca54327 100644 --- a/bsp/hpmicro/hpm6750evk/board/pinmux.c +++ b/bsp/hpmicro/hpm6750evk/board/pinmux.c @@ -21,8 +21,8 @@ void init_uart_pins(UART_Type *ptr) HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART0_RXD; HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART0_TXD; /* PY port IO needs to configure PIOC as well */ - HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_SOC_PY_07; - HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_SOC_PY_06; + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = PIOC_PY07_FUNC_CTL_SOC_PY_07; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = PIOC_PY06_FUNC_CTL_SOC_PY_06; } else if (ptr == HPM_UART2) { HPM_IOC->PAD[IOC_PAD_PE16].FUNC_CTL = IOC_PE16_FUNC_CTL_UART2_TXD; HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PE21_FUNC_CTL_UART2_RXD; @@ -30,13 +30,34 @@ void init_uart_pins(UART_Type *ptr) HPM_IOC->PAD[IOC_PAD_PZ08].FUNC_CTL = IOC_PZ08_FUNC_CTL_UART13_RXD; HPM_IOC->PAD[IOC_PAD_PZ09].FUNC_CTL = IOC_PZ09_FUNC_CTL_UART13_TXD; /* PZ port IO needs to configure BIOC as well */ - HPM_BIOC->PAD[IOC_PAD_PZ08].FUNC_CTL = IOC_PZ08_FUNC_CTL_SOC_PZ_08; - HPM_BIOC->PAD[IOC_PAD_PZ09].FUNC_CTL = IOC_PZ09_FUNC_CTL_SOC_PZ_09; + HPM_BIOC->PAD[IOC_PAD_PZ08].FUNC_CTL = BIOC_PZ08_FUNC_CTL_SOC_PZ_08; + HPM_BIOC->PAD[IOC_PAD_PZ09].FUNC_CTL = BIOC_PZ09_FUNC_CTL_SOC_PZ_09; + } else if (ptr == HPM_PUART) { + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = PIOC_PY07_FUNC_CTL_PUART_RXD; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = PIOC_PY06_FUNC_CTL_PUART_TXD; + } +} + +void init_uart_pin_as_gpio(UART_Type *ptr) +{ + if (ptr == HPM_UART13) { + /* pull-up */ + HPM_IOC->PAD[IOC_PAD_PZ08].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PZ09].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + + /* PZ port IO needs to configure BIOC as well */ + HPM_IOC->PAD[IOC_PAD_PZ08].FUNC_CTL = IOC_PZ08_FUNC_CTL_GPIO_Z_08; + HPM_BIOC->PAD[IOC_PAD_PZ08].FUNC_CTL = BIOC_PZ08_FUNC_CTL_SOC_PZ_08; + + /* PZ port IO needs to configure BIOC as well */ + HPM_IOC->PAD[IOC_PAD_PZ09].FUNC_CTL = IOC_PZ09_FUNC_CTL_GPIO_Z_09; + HPM_BIOC->PAD[IOC_PAD_PZ09].FUNC_CTL = BIOC_PZ09_FUNC_CTL_SOC_PZ_09; } } void init_lcd_pins(LCDC_Type *ptr) { + (void) ptr; HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_DIS0_R_0; HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_DIS0_R_1; HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PB00_FUNC_CTL_DIS0_R_2; @@ -185,16 +206,69 @@ void init_sdram_pins(void) HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); } -void init_gpio_pins(void) +void init_sram_pins(void) +{ + /* Non-MUX */ /* MUX */ + HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A0 */ /* A16 */ + HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A1 */ /* A17 */ + HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A2 */ /* A18 */ + HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A3 */ /* A19 */ + HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A4 */ /* A20 */ + HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A5 */ /* A21 */ + HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A6 */ /* A22 */ + HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A7 */ /* A23 */ + HPM_IOC->PAD[IOC_PAD_PC01].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A8 */ + HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A9 */ + HPM_IOC->PAD[IOC_PAD_PB31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A10 */ + HPM_IOC->PAD[IOC_PAD_PB28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A11 */ + HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A12 */ + HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A13 */ + HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A14 */ + HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A15 */ + HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A16 */ + HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A17 */ + HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A18 */ + HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A19 */ + HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A20 */ + HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A21 */ + HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A22 */ + HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A23 */ + + HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D0 */ /* AD0 */ + HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D1 */ /* AD1 */ + HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D2 */ /* AD2 */ + HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D3 */ /* AD3 */ + HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D4 */ /* AD4 */ + HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D5 */ /* AD5 */ + HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D6 */ /* AD6 */ + HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D7 */ /* AD7 */ + HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D8 */ /* AD8 */ + HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D9 */ /* AD9 */ + HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D10 */ /* AD10 */ + HPM_IOC->PAD[IOC_PAD_PD06].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D11 */ /* AD11 */ + HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D12 */ /* AD12 */ + HPM_IOC->PAD[IOC_PAD_PD09].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D13 */ /* AD13 */ + HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D14 */ /* AD14 */ + HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D15 */ /* AD15 */ + + HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #CE */ + HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #OE */ + HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #WE */ + HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #UB */ + HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #LB */ + HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #ADV */ +} + +void init_gpio_pins(uint8_t led_pull_select) { - uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12; - HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(led_pull_select); #ifdef USING_GPIO0_FOR_GPIOZ HPM_IOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_GPIO_Z_02; - HPM_IOC->PAD[IOC_PAD_PZ02].PAD_CTL = pad_ctl; - HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_SOC_PZ_02; + HPM_IOC->PAD[IOC_PAD_PZ02].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + /* PZ port IO needs to configure BIOC as well */ + HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = BIOC_PZ02_FUNC_CTL_SOC_PZ_02; #endif } @@ -208,9 +282,21 @@ void init_spi_pins(SPI_Type *ptr) } } +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + if (ptr == HPM_SPI2) { + HPM_IOC->PAD[IOC_PAD_PE31].FUNC_CTL = IOC_PE31_FUNC_CTL_GPIO_E_31; + HPM_IOC->PAD[IOC_PAD_PE30].FUNC_CTL = IOC_PE30_FUNC_CTL_SPI2_MOSI; + HPM_IOC->PAD[IOC_PAD_PE28].FUNC_CTL = IOC_PE28_FUNC_CTL_SPI2_MISO; + HPM_IOC->PAD[IOC_PAD_PE27].FUNC_CTL = IOC_PE27_FUNC_CTL_SPI2_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + } +} + void init_pins(void) { - init_uart_pins(BOARD_CONSOLE_BASE); +#ifdef BOARD_CONSOLE_UART_BASE + init_uart_pins(BOARD_CONSOLE_UART_BASE); +#endif init_sdram_pins(); } @@ -224,6 +310,27 @@ void init_gptmr_pins(GPTMR_Type *ptr) /* TMR4 capture 1 */ HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PE25_FUNC_CTL_GPTMR4_CAPT_1; } + if (ptr == HPM_GPTMR5) { + /* TMR5 capture 2 */ + HPM_IOC->PAD[IOC_PAD_PD24].FUNC_CTL = IOC_PD24_FUNC_CTL_TRGM2_P_10; + trgm_enable_io_output(HPM_TRGM2, 1 << 10); + + /* TMR5 capture 3 */ + HPM_IOC->PAD[IOC_PAD_PD23].FUNC_CTL = IOC_PD23_FUNC_CTL_TRGM2_P_11; + trgm_enable_io_output(HPM_TRGM2, 1 << 11); + + trgm_output_t trgm2IoConfig0; + trgm2IoConfig0.invert = 0; + trgm2IoConfig0.type = trgm_output_same_as_input; + trgm2IoConfig0.input = HPM_TRGM2_INPUT_SRC_GPTMR5_OUT2; + trgm_output_config(HPM_TRGM2, HPM_TRGM2_OUTPUT_SRC_TRGM2_P10, &trgm2IoConfig0); + + trgm_output_t trgm2IoConfig1; + trgm2IoConfig1.invert = 0; + trgm2IoConfig1.type = trgm_output_same_as_input; + trgm2IoConfig1.input = HPM_TRGM2_INPUT_SRC_GPTMR5_OUT3; + trgm_output_config(HPM_TRGM2, HPM_TRGM2_OUTPUT_SRC_TRGM2_P11, &trgm2IoConfig1); + } } void init_hall_trgm_pins(void) @@ -255,8 +362,8 @@ void init_dao_pins(void) HPM_IOC->PAD[IOC_PAD_PY08].FUNC_CTL = IOC_PY08_FUNC_CTL_DAOR_P; HPM_IOC->PAD[IOC_PAD_PY09].FUNC_CTL = IOC_PY09_FUNC_CTL_DAOR_N; /* PY port IO needs to configure PIOC */ - HPM_PIOC->PAD[IOC_PAD_PY08].FUNC_CTL = IOC_PY08_FUNC_CTL_SOC_PY_08; - HPM_PIOC->PAD[IOC_PAD_PY09].FUNC_CTL = IOC_PY09_FUNC_CTL_SOC_PY_09; + HPM_PIOC->PAD[IOC_PAD_PY08].FUNC_CTL = PIOC_PY08_FUNC_CTL_SOC_PY_08; + HPM_PIOC->PAD[IOC_PAD_PY09].FUNC_CTL = PIOC_PY09_FUNC_CTL_SOC_PY_09; } void init_pdm_pins(void) @@ -264,14 +371,14 @@ void init_pdm_pins(void) HPM_IOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_PDM0_CLK; HPM_IOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_PDM0_D_0; /* PY port IO needs to configure PIOC */ - HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_SOC_PY_10; - HPM_PIOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_SOC_PY_11; + HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = PIOC_PY10_FUNC_CTL_SOC_PY_10; + HPM_PIOC->PAD[IOC_PAD_PY11].FUNC_CTL = PIOC_PY11_FUNC_CTL_SOC_PY_11; } void init_vad_pins(void) { - HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_VAD_CLK; - HPM_PIOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_VAD_DAT; + HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = PIOC_PY10_FUNC_CTL_VAD_CLK; + HPM_PIOC->PAD[IOC_PAD_PY11].FUNC_CTL = PIOC_PY11_FUNC_CTL_VAD_DAT; } void init_cam_pins(void) @@ -279,7 +386,7 @@ void init_cam_pins(void) /* configure rst pin function */ HPM_IOC->PAD[IOC_PAD_PY05].FUNC_CTL = IOC_PY05_FUNC_CTL_GPIO_Y_05; /* PY port IO needs to configure PIOC */ - HPM_PIOC->PAD[IOC_PAD_PY05].FUNC_CTL = IOC_PY05_FUNC_CTL_SOC_PY_05; + HPM_PIOC->PAD[IOC_PAD_PY05].FUNC_CTL = PIOC_PY05_FUNC_CTL_SOC_PY_05; HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_CAM0_XCLK; HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_CAM0_PIXCLK; @@ -297,10 +404,10 @@ void init_cam_pins(void) void init_butn_pins(void) { - HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_PBUTN; - HPM_BIOC->PAD[IOC_PAD_PZ03].FUNC_CTL = IOC_PZ03_FUNC_CTL_WBUTN; - HPM_BIOC->PAD[IOC_PAD_PZ04].FUNC_CTL = IOC_PZ04_FUNC_CTL_PLED; - HPM_BIOC->PAD[IOC_PAD_PZ05].FUNC_CTL = IOC_PZ05_FUNC_CTL_WLED; + HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = BIOC_PZ02_FUNC_CTL_PBUTN; + HPM_BIOC->PAD[IOC_PAD_PZ03].FUNC_CTL = BIOC_PZ03_FUNC_CTL_WBUTN; + HPM_BIOC->PAD[IOC_PAD_PZ04].FUNC_CTL = BIOC_PZ04_FUNC_CTL_PLED; + HPM_BIOC->PAD[IOC_PAD_PZ05].FUNC_CTL = BIOC_PZ05_FUNC_CTL_WLED; } void init_acmp_pins(void) @@ -417,59 +524,61 @@ void init_can_pins(CAN_Type *ptr) } } -void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8) +void init_sdxc_cmd_pin(SDXC_Type *ptr, bool open_drain, bool is_1v8) { uint32_t cmd_func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); - uint32_t func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17); - uint32_t pad_ctl = IOC_PAD_PAD_CTL_MS_SET(use_1v8) | IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_PE_SET(1) | - IOC_PAD_PAD_CTL_PS_SET(1); - - if (ptr == HPM_SDXC0) { - } else if (ptr == HPM_SDXC1) { - /* CLK */ - HPM_IOC->PAD[IOC_PAD_PD22].FUNC_CTL = func_ctl; - HPM_IOC->PAD[IOC_PAD_PD22].PAD_CTL = pad_ctl; + uint32_t cmd_pad_ctl = IOC_PAD_PAD_CTL_MS_SET(is_1v8) | IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | + IOC_PAD_PAD_CTL_PS_SET(1); + if (open_drain) { + cmd_pad_ctl |= IOC_PAD_PAD_CTL_OD_MASK; + } - /* CMD */ + if (ptr == HPM_SDXC1) { + /* SDXC1.CMD */ HPM_IOC->PAD[IOC_PAD_PD21].FUNC_CTL = cmd_func_ctl; - HPM_IOC->PAD[IOC_PAD_PD21].PAD_CTL = pad_ctl; - - /* DATA0 */ - HPM_IOC->PAD[IOC_PAD_PD18].FUNC_CTL = func_ctl; - HPM_IOC->PAD[IOC_PAD_PD18].PAD_CTL = pad_ctl; - /* DATA1 */ - HPM_IOC->PAD[IOC_PAD_PD17].FUNC_CTL = func_ctl; - HPM_IOC->PAD[IOC_PAD_PD17].PAD_CTL = pad_ctl; - /* DATA2 */ - HPM_IOC->PAD[IOC_PAD_PD27].FUNC_CTL = func_ctl; - HPM_IOC->PAD[IOC_PAD_PD27].PAD_CTL = pad_ctl; - /* DATA3 */ - HPM_IOC->PAD[IOC_PAD_PD26].FUNC_CTL = func_ctl; - HPM_IOC->PAD[IOC_PAD_PD26].PAD_CTL = pad_ctl; - - /* CDN */ - HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = IOC_PD15_FUNC_CTL_GPIO_D_15; - HPM_IOC->PAD[IOC_PAD_PD15].PAD_CTL = pad_ctl; - HPM_GPIO0->OE[GPIO_OE_GPIOD].CLEAR = 1UL << BOARD_APP_SDCARD_CDN_GPIO_PIN; + HPM_IOC->PAD[IOC_PAD_PD21].PAD_CTL = cmd_pad_ctl; } } -void init_sdxc_power_pin(SDXC_Type *ptr) +void init_sdxc_cd_pin(SDXC_Type *ptr, bool as_gpio) { - /* Not supported by current board */ -} -void init_sdxc_vsel_pin(SDXC_Type *ptr) -{ - /* Not suppored by current board */ + uint32_t cd_pad_ctl = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + if (ptr == HPM_SDXC1) { + if (as_gpio) { + /* SDXC1.CDN */ + uint32_t cd_func_alt = IOC_PD15_FUNC_CTL_GPIO_D_15; + HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = cd_func_alt; + HPM_IOC->PAD[IOC_PAD_PD15].PAD_CTL = cd_pad_ctl; + } + } } -void init_sdxc_card_detection_pin(SDXC_Type *ptr) +void init_sdxc_clk_data_pins(SDXC_Type *ptr, uint32_t width, bool is_1v8) { - /* CDN */ - HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = IOC_PD15_FUNC_CTL_GPIO_D_15; - HPM_IOC->PAD[IOC_PAD_PD15].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_PE_SET(1) | + uint32_t func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17); + uint32_t pad_ctl = IOC_PAD_PAD_CTL_MS_SET(is_1v8) | IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); - HPM_GPIO0->OE[GPIO_OE_GPIOD].CLEAR = 1UL << BOARD_APP_SDCARD_CDN_GPIO_PIN; + + if (ptr == HPM_SDXC1) { + /* SDXC1.CLK */ + HPM_IOC->PAD[IOC_PAD_PD22].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD22].PAD_CTL = pad_ctl; + + /* SDXC1.DATA0 */ + HPM_IOC->PAD[IOC_PAD_PD18].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD18].PAD_CTL = pad_ctl; + if ((width == 4)) { + /* SDXC1.DATA1 */ + HPM_IOC->PAD[IOC_PAD_PD17].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD17].PAD_CTL = pad_ctl; + /* SDXC1.DATA2 */ + HPM_IOC->PAD[IOC_PAD_PD27].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD27].PAD_CTL = pad_ctl; + /* SDXC1.DATA3 */ + HPM_IOC->PAD[IOC_PAD_PD26].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD26].PAD_CTL = pad_ctl; + } + } } void init_clk_obs_pins(void) @@ -489,12 +598,19 @@ void init_rgb_pwm_pins(void) void init_led_pins_as_gpio(void) { - uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); - HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_GPIO_B_11; - HPM_IOC->PAD[IOC_PAD_PB11].PAD_CTL = pad_ctl; HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12; - HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = pad_ctl; HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_GPIO_B_13; - HPM_IOC->PAD[IOC_PAD_PB13].PAD_CTL = pad_ctl; +} + +void init_enet_pps_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PF05].FUNC_CTL = IOC_PF05_FUNC_CTL_ETH0_EVTO_0; +} + +void init_tamper_pins(void) +{ + HPM_BIOC->PAD[IOC_PAD_PZ08].FUNC_CTL = BIOC_PZ08_FUNC_CTL_TAMP_08 | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_BIOC->PAD[IOC_PAD_PZ09].FUNC_CTL = BIOC_PZ09_FUNC_CTL_TAMP_09; + HPM_BIOC->PAD[IOC_PAD_PZ10].FUNC_CTL = BIOC_PZ10_FUNC_CTL_TAMP_10; } diff --git a/bsp/hpmicro/hpm6750evk/board/pinmux.h b/bsp/hpmicro/hpm6750evk/board/pinmux.h index 52c97a9b9a4..f90130b2910 100644 --- a/bsp/hpmicro/hpm6750evk/board/pinmux.h +++ b/bsp/hpmicro/hpm6750evk/board/pinmux.h @@ -12,12 +12,15 @@ extern "C" { #endif void init_uart_pins(UART_Type *ptr); +void init_uart_pin_as_gpio(UART_Type *ptr); void init_lcd_pins(LCDC_Type *ptr); void init_i2c_pins(I2C_Type *ptr); void init_cap_pins(void); void init_sdram_pins(void); -void init_gpio_pins(void); +void init_sram_pins(void); +void init_gpio_pins(uint8_t pin_stat); void init_spi_pins(SPI_Type *ptr); +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); void init_pins(void); void init_gptmr_pins(GPTMR_Type *ptr); void init_hall_trgm_pins(void); @@ -35,15 +38,21 @@ void init_adc12_pins(void); void init_adc16_pins(void); void init_usb_pins(void); void init_can_pins(CAN_Type *ptr); -void init_sdxc_power_pin(SDXC_Type *ptr); -void init_sdxc_vsel_pin(SDXC_Type *ptr); -void init_sdxc_card_detection_pin(SDXC_Type *ptr); -void init_sdxc_pins(SDXC_Type * ptr, bool use_1v8); +void init_sdxc_cmd_pin(SDXC_Type *ptr, bool open_drain, bool is_1v8); +void init_sdxc_cd_pin(SDXC_Type *ptr, bool as_gpio); +void init_sdxc_clk_data_pins(SDXC_Type *ptr, uint32_t width, bool is_1v8); +void init_sdxc_pwr_pin(SDXC_Type *ptr, bool as_gpio); +void init_adc12_pins(void); +void init_adc16_pins(void); +void init_usb_pins(void); +void init_can_pins(CAN_Type *ptr); void init_adc_bldc_pins(void); void init_rgb_pwm_pins(void); void init_i2c_pins_as_gpio(I2C_Type *ptr); void init_led_pins_as_gpio(void); void init_trgmux_pins(uint32_t pin); +void init_enet_pps_pins(void); +void init_tamper_pins(void); #ifdef __cplusplus } diff --git a/bsp/hpmicro/hpm6750evk/board/rtt_board.c b/bsp/hpmicro/hpm6750evk/board/rtt_board.c index 2fa9cf7aab8..42f3e9a8b7c 100644 --- a/bsp/hpmicro/hpm6750evk/board/rtt_board.c +++ b/bsp/hpmicro/hpm6750evk/board/rtt_board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * SPDX-License-Identifier: BSD-3-Clause * */ @@ -8,18 +8,34 @@ #include "rtt_board.h" #include "hpm_uart_drv.h" #include "hpm_gpio_drv.h" -#include "hpm_mchtmr_drv.h" #include "hpm_pmp_drv.h" #include "assert.h" #include "hpm_clock_drv.h" #include "hpm_sysctl_drv.h" #include #include -#include "hpm_dma_manager.h" +#include "hpm_dma_mgr.h" +#include "hpm_mchtmr_drv.h" +extern int rt_hw_uart_init(void); void os_tick_config(void); +void rtt_board_init(void); -extern int rt_hw_uart_init(void); +void rt_hw_board_init(void) +{ + rtt_board_init(); + + /* Call the RT-Thread Component Board Initialization */ + rt_components_board_init(); +} + +void os_tick_config(void) +{ + sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1); + sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0); + mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND); + enable_mchtmr_irq(); +} void rtt_board_init(void) { @@ -27,7 +43,7 @@ void rtt_board_init(void) board_init_console(); board_init_pmp(); - dma_manager_init(); + dma_mgr_init(); /* initialize memory system */ rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); @@ -72,24 +88,6 @@ void app_led_write(uint32_t index, bool state) } } -void os_tick_config(void) -{ - sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1); - sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0); - - mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND); - - enable_mchtmr_irq(); -} - -void rt_hw_board_init(void) -{ - rtt_board_init(); - - /* Call the RT-Thread Component Board Initialization */ - rt_components_board_init(); -} - void rt_hw_console_output(const char *str) { while (*str != '\0') @@ -98,18 +96,16 @@ void rt_hw_console_output(const char *str) } } +void app_init_usb_pins(void) +{ + board_init_usb_pins(); +} + ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) { HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND; - rt_interrupt_enter(); rt_tick_increase(); - rt_interrupt_leave(); -} - -void rt_hw_us_delay(rt_uint32_t us) -{ - clock_cpu_delay_us(us); } void rt_hw_cpu_reset(void) diff --git a/bsp/hpmicro/hpm6750evk/board/rtt_board.h b/bsp/hpmicro/hpm6750evk/board/rtt_board.h index de60e7f9f89..67fa97bd9c9 100644 --- a/bsp/hpmicro/hpm6750evk/board/rtt_board.h +++ b/bsp/hpmicro/hpm6750evk/board/rtt_board.h @@ -38,6 +38,25 @@ /* CAN section */ #define BOARD_CAN_NAME "can0" +#define BOARD_CAN_HWFILTER_INDEX (0U) + +/* UART section */ +#define BOARD_UART_NAME "uart13" +#define BOARD_UART_RX_BUFFER_SIZE BSP_UART13_RX_BUFSIZE + +/* eeprom section */ +#define BOARD_EEPROM_I2C_NAME "i2c0" + +#define BOARD_SD_NAME "sd1" +/* audio section */ +#define BOARD_AUDIO_CODEC_I2C_NAME "i2c0" +#define BOARD_AUDIO_CODEC_I2S_NAME "i2s0" + +/* PWM section */ +#define BOARD_PWM_NAME "pwm2" +#define BOARD_PWM_CHANNEL (0) + +#define IRQn_PendSV IRQn_DEBUG_0 /*************************************************************** * @@ -65,7 +84,7 @@ extern "C" { void app_init_led_pins(void); void app_led_write(uint32_t index, bool state); - +void app_init_usb_pins(void); #if defined(__cplusplus) diff --git a/bsp/hpmicro/hpm6750evk/rtconfig.py b/bsp/hpmicro/hpm6750evk/rtconfig.py index f199f0f3653..d0781627b3f 100644 --- a/bsp/hpmicro/hpm6750evk/rtconfig.py +++ b/bsp/hpmicro/hpm6750evk/rtconfig.py @@ -81,8 +81,8 @@ LFLAGS += ' -O0' LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' elif BUILD == 'ram_release': - CFLAGS += ' -O2 -Os' - LFLAGS += ' -O2 -Os' + CFLAGS += ' -O2' + LFLAGS += ' -O2' LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' elif BUILD == 'flash_debug': CFLAGS += ' -gdwarf-2' @@ -92,13 +92,13 @@ CFLAGS += ' -DFLASH_XIP=1' LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' elif BUILD == 'flash_release': - CFLAGS += ' -O2 -Os' - LFLAGS += ' -O2 -Os' + CFLAGS += ' -O2' + LFLAGS += ' -O2' CFLAGS += ' -DFLASH_XIP=1' LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' else: - CFLAGS += ' -O2 -Os' - LFLAGS += ' -O2 -Os' + CFLAGS += ' -O2' + LFLAGS += ' -O2' LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' LFLAGS += ' -T ' + LINKER_FILE diff --git a/bsp/hpmicro/hpm6750evk/startup/HPM6750/toolchains/gcc/start.S b/bsp/hpmicro/hpm6750evk/startup/HPM6750/toolchains/gcc/start.S index 5c47c92afe7..238e05b43bb 100644 --- a/bsp/hpmicro/hpm6750evk/startup/HPM6750/toolchains/gcc/start.S +++ b/bsp/hpmicro/hpm6750evk/startup/HPM6750/toolchains/gcc/start.S @@ -25,6 +25,15 @@ _start: ori t1, t1, 0x80 sw t1, 0(t0) +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + #ifdef INIT_EXT_RAM_FOR_DATA la t0, _stack_in_dlm mv sp, t0 diff --git a/bsp/hpmicro/hpm6750evk2/README.md b/bsp/hpmicro/hpm6750evk2/README.md index 5f0624b48c7..dd06637e341 100644 --- a/bsp/hpmicro/hpm6750evk2/README.md +++ b/bsp/hpmicro/hpm6750evk2/README.md @@ -51,7 +51,7 @@ The BSP support being build via the 'scons' command, below is the steps of compi - Download the package and extract it into a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain` - Step 3: Set environment variable `RTT_RISCV_TOOLCHAIN` to `\bin` - For example: `C:\DevTools\riscv32-gnu-toolchain\bin` -- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip) +- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip) - Download and extract it to specified directory, for example: `C:\DevTools\openocd-hpmicro` - Add `OpenOCD` environment variable `OPENOCD_HPMICRO` to `\bin` - For example: `C:\DevTools\openocd-hpmicro\bin` diff --git a/bsp/hpmicro/hpm6750evk2/README_zh.md b/bsp/hpmicro/hpm6750evk2/README_zh.md index 35e712a6302..ab908fe462e 100644 --- a/bsp/hpmicro/hpm6750evk2/README_zh.md +++ b/bsp/hpmicro/hpm6750evk2/README_zh.md @@ -53,7 +53,7 @@ HPM6750EVK2 是由先楫半导体推出的一款基于RISCV内核的开发板， - 步骤 2: 准备 [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) - 下载并解压到指定的目录，如: `C:\DevTools\riscv32-gnu-toolchain` - 步骤 3: 设置环境变量： `RTT_RISCV_TOOLCHAIN` 为 `\bin`， 如: `C:\DevTools\riscv32-gnu-toolchain\bin` -- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip) +- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip) - 下载并解压到指定目录，如: `C:\DevTools\openocd-hpmicro` - 将 `OPENOCD_HPMICRO`环境变量设置为 `\bin`，如： `C:\DevTools\openocd-hpmicro\bin` diff --git a/bsp/hpmicro/hpm6750evk2/board/Kconfig b/bsp/hpmicro/hpm6750evk2/board/Kconfig index 676f155d77f..bb866694cac 100644 --- a/bsp/hpmicro/hpm6750evk2/board/Kconfig +++ b/bsp/hpmicro/hpm6750evk2/board/Kconfig @@ -7,6 +7,10 @@ config SOC_HPM6000 select RT_USING_USER_MAIN default y +config BSP_USING_ENET_PHY_RTL8211 + bool + default n + config BSP_USING_ENET_PHY_RTL8201 bool default n @@ -21,7 +25,6 @@ menu "On-chip Peripheral Drivers" bool "Enable UART" default y select RT_USING_SERIAL - if BSP_USING_UART menuconfig BSP_USING_UART0 bool "Enable UART0 (Debugger)" @@ -31,37 +34,22 @@ menu "On-chip Peripheral Drivers" bool "Enable UART0 RX DMA" depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA default n - config BSP_UART0_TX_USING_DMA bool "Enable UART0 TX DMA" depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA default n - - config BSP_UART0_RX_DMA_CHANNEL - int "Set UART0 RX DMA CHANNEL" - range 0 7 - depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA - default 0 - - config BSP_UART0_TX_DMA_CHANNEL - int "Set UART0 TX DMA CHANNEL" - range 0 7 - depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA - default 1 - config BSP_UART0_RX_BUFSIZE int "Set UART0 RX buffer size" range 64 65535 depends on RT_USING_SERIAL_V2 default 128 - config BSP_UART0_TX_BUFSIZE int "Set UART0 TX buffer size" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 endif - menuconfig BSP_USING_UART6 + menuconfig BSP_USING_UART6 bool "Enable UART6" default n if BSP_USING_UART6 @@ -69,75 +57,45 @@ menu "On-chip Peripheral Drivers" bool "Enable UART6 RX DMA" depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA default n - config BSP_UART6_TX_USING_DMA bool "Enable UART6 TX DMA" depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA default n - - config BSP_UART6_RX_DMA_CHANNEL - int "Set UART6 RX DMA CHANNEL" - range 0 7 - depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA - default 0 - - config BSP_UART6_TX_DMA_CHANNEL - int "Set UART6 TX DMA CHANNEL" - range 0 7 - depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA - default 1 - config BSP_UART6_RX_BUFSIZE int "Set UART6 RX buffer size" range 64 65535 depends on RT_USING_SERIAL_V2 default 128 - config BSP_UART6_TX_BUFSIZE int "Set UART6 TX buffer size" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 endif - menuconfig BSP_USING_UART13 + menuconfig BSP_USING_UART13 bool "Enable UART13" - default n + default y if BSP_USING_UART13 config BSP_UART13_RX_USING_DMA bool "Enable UART13 RX DMA" depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA default n - config BSP_UART13_TX_USING_DMA bool "Enable UART13 TX DMA" depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA default n - - config BSP_UART13_RX_DMA_CHANNEL - int "Set UART13 RX DMA CHANNEL" - range 0 7 - depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA - default 0 - - config BSP_UART13_TX_DMA_CHANNEL - int "Set UART13 TX DMA CHANNEL" - range 0 7 - depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA - default 1 - config BSP_UART13_RX_BUFSIZE int "Set UART13 RX buffer size" range 64 65535 depends on RT_USING_SERIAL_V2 default 128 - config BSP_UART13_TX_BUFSIZE int "Set UART13 TX buffer size" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 endif - menuconfig BSP_USING_UART14 + menuconfig BSP_USING_UART14 bool "Enable UART14" default n if BSP_USING_UART14 @@ -145,30 +103,15 @@ menu "On-chip Peripheral Drivers" bool "Enable UART14 RX DMA" depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA default n - config BSP_UART14_TX_USING_DMA bool "Enable UART14 TX DMA" depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA default n - - config BSP_UART14_RX_DMA_CHANNEL - int "Set UART14 RX DMA CHANNEL" - range 0 7 - depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA - default 0 - - config BSP_UART14_TX_DMA_CHANNEL - int "Set UART14 TX DMA CHANNEL" - range 0 7 - depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA - default 1 - config BSP_UART14_RX_BUFSIZE int "Set UART14 RX buffer size" range 64 65535 depends on RT_USING_SERIAL_V2 default 128 - config BSP_UART14_TX_BUFSIZE int "Set UART14 TX buffer size" range 0 65535 @@ -178,7 +121,6 @@ menu "On-chip Peripheral Drivers" endif - menuconfig BSP_USING_SPI bool "Enable SPI" default n @@ -186,13 +128,28 @@ menu "On-chip Peripheral Drivers" if BSP_USING_SPI config BSP_USING_SPI1 bool "Enable SPI1" - default y + default y + if BSP_USING_SPI1 + config BSP_SPI1_USING_DMA + bool "Enable SPI1 DMA" + default n + endif config BSP_USING_SPI2 bool "Enable SPI2" + default n + if BSP_USING_SPI2 + config BSP_SPI2_USING_DMA + bool "Enable SPI2 DMA" default n + endif config BSP_USING_SPI3 bool "Enable SPI3" + default n + if BSP_USING_SPI3 + config BSP_SPI3_USING_DMA + bool "Enable SPI3 DMA" default n + endif endif menuconfig BSP_USING_RTC @@ -204,18 +161,16 @@ menu "On-chip Peripheral Drivers" default n select RT_USING_ETH - if BSP_USING_ETH - choice - prompt "ETH" - default BSP_USING_ETH1 - + if BSP_USING_ETH config BSP_USING_ETH0 bool "Enable ETH0" + default y + select BSP_USING_ENET_PHY_RTL8211 config BSP_USING_ETH1 bool "Enable ETH1" - select BSP_USING_ENET_PHY_RTL8201 - endchoice + default n + select BSP_USING_ENET_PHY_RTL8201 endif menuconfig BSP_USING_SDXC @@ -225,11 +180,65 @@ menu "On-chip Peripheral Drivers" if BSP_USING_SDXC config BSP_USING_SDXC0 bool "Enable SDXC0" - default n + default n + if BSP_USING_SDXC0 + choice + prompt "Select BUS_WIDTH" + default BSP_SDXC0_BUS_WIDTH_8BIT + config BSP_SDXC0_BUS_WIDTH_1BIT + bool "1-bit" + config BSP_SDXC0_BUS_WIDTH_4BIT + bool "4-bit" + config BSP_SDXC0_BUS_WIDTH_8BIT + bool "8-bit" + endchoice + choice + prompt "Select Voltage" + default BSP_SDXC0_VOLTAGE_3V3 + config BSP_SDXC0_VOLTAGE_3V3 + bool "3.3V" + config BSP_SDXC0_VOLTAGE_1V8 + bool "1.8V" + config BSP_SDXC0_VOLTAGE_DUAL + bool "Dual voltage 3.3V / 1.8V" + endchoice + config BSP_SDXC0_VSEL_PIN + default "None" + string "VSEL pin name" + config BSP_SDXC0_PWR_PIN + default "None" + string "PWR pin name" + endif config BSP_USING_SDXC1 bool "Enable SDXC1" - default y + default n + if BSP_USING_SDXC1 + choice + prompt "Select BUS_WIDTH" + default BSP_SDXC1_BUS_WIDTH_4BIT + config BSP_SDXC1_BUS_WIDTH_1BIT + bool "1-bit" + config BSP_SDXC1_BUS_WIDTH_4BIT + bool "4-bit" + endchoice + choice + prompt "Select Voltage" + default BSP_SDXC1_VOLTAGE_3V3 + config BSP_SDXC1_VOLTAGE_3V3 + bool "3.3V" + config BSP_SDXC1_VOLTAGE_1V8 + bool "1.8V" + config BSP_SDXC1_VOLTAGE_DUAL + bool "Dual voltage 3.3V / 1.8V" + endchoice + config BSP_SDXC1_VSEL_PIN + default "None" + string "VSEL pin name" + config BSP_SDXC1_PWR_PIN + default "PC20" + string "PWR pin name" + endif endif menuconfig BSP_USING_TOUCH @@ -238,16 +247,21 @@ menu "On-chip Peripheral Drivers" if BSP_USING_TOUCH config BSP_USING_TOUCH_GT911 bool "Enable GT911" - default y + default y config BSP_USING_TOUCH_FT5406 bool "Enable FT5406" - default n + default n endif menuconfig BSP_USING_LCD bool "Enable LCD" default n + if BSP_USING_LCD + config BSP_USING_LCD_ISR + bool "Enable LCD interrupt" + default n + endif menuconfig BSP_USING_LVGL bool "Enable LVGL" @@ -260,31 +274,31 @@ menu "On-chip Peripheral Drivers" default n menuconfig BSP_USING_GPTMR - bool "Enable GPTMR" - default n - select RT_USING_HWTIMER if BSP_USING_GPTMR - if BSP_USING_GPTMR - config BSP_USING_GPTMR1 - bool "Enable GPTMR1" - default n - config BSP_USING_GPTMR2 - bool "Enable GPTMR2" - default n - config BSP_USING_GPTMR3 - bool "Enable GPTMR3" - default n - config BSP_USING_GPTMR4 - bool "Enable GPTMR4" - default n - config BSP_USING_GPTMR5 - bool "Enable GPTMR5" - default n - config BSP_USING_GPTMR6 - bool "Enable GPTMR6" - default n - config BSP_USING_GPTMR7 - bool "Enable GPTMR7" - default n + bool "Enable GPTMR" + default n + select RT_USING_HWTIMER if BSP_USING_GPTMR + if BSP_USING_GPTMR + config BSP_USING_GPTMR1 + bool "Enable GPTMR1" + default n + config BSP_USING_GPTMR2 + bool "Enable GPTMR2" + default n + config BSP_USING_GPTMR3 + bool "Enable GPTMR3" + default n + config BSP_USING_GPTMR4 + bool "Enable GPTMR4" + default n + config BSP_USING_GPTMR5 + bool "Enable GPTMR5" + default n + config BSP_USING_GPTMR6 + bool "Enable GPTMR6" + default n + config BSP_USING_GPTMR7 + bool "Enable GPTMR7" + default n endif menuconfig BSP_USING_I2C @@ -294,7 +308,12 @@ menu "On-chip Peripheral Drivers" if BSP_USING_I2C config BSP_USING_I2C0 bool "Enable I2C0" - default y + default y + endif + if BSP_USING_I2C0 + config BSP_I2C0_USING_DMA + bool "Enable I2C0 DMA" + default n endif menuconfig BSP_USING_FEMC @@ -307,12 +326,12 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_XPI_FLASH bool "Enable XPI FLASH" - default n - select PKG_USING_FAL if BSP_USING_XPI_FLASH + default n + select RT_USING_FAL if BSP_USING_XPI_FLASH menuconfig BSP_USING_PWM bool "Enable PWM" - default n + default n menuconfig BSP_USING_DAO bool "Enable Audio DAO play" @@ -331,89 +350,162 @@ menu "On-chip Peripheral Drivers" if BSP_USING_I2S config BSP_USING_I2S0 bool "Enable I2S0" - default y + default y + config BSP_USING_AUDIO_CODEC_WM8960 + bool "Enable audio codec on board" + default y endif menuconfig BSP_USING_USB bool "Enable USB" default n if BSP_USING_USB - config BSP_USING_USB_DEVICE + config BSP_USING_USB_DEVICE bool "Enable USB Device" - default n + default n config BSP_USING_USB_HOST bool "Enable USB Host" - default n + select RT_USING_CACHE + default n endif - menuconfig BSP_USING_WDG - bool "Enable Watchdog" - default n - select RT_USING_WDT if BSP_USING_WDG - if BSP_USING_WDG - config BSP_USING_WDG0 - bool "Enable WDG0" - default n - config BSP_USING_WDG1 - bool "Enable WDG1" - default n - config BSP_USING_WDG2 - bool "Enable WDG2" - default n - config BSP_USING_WDG3 - bool "Enable WDG3" - default n - endif + menuconfig BSP_USING_WDG + bool "Enable Watchdog" + default n + select RT_USING_WDT if BSP_USING_WDG + if BSP_USING_WDG + config BSP_USING_WDG0 + bool "Enable WDG0" + default n + config BSP_USING_WDG1 + bool "Enable WDG1" + default n + config BSP_USING_WDG2 + bool "Enable WDG2" + default n + config BSP_USING_WDG3 + bool "Enable WDG3" + default n + endif + + menuconfig BSP_USING_CAN + bool "Enable CAN" + default n + select RT_USING_CAN if BSP_USING_CAN + if BSP_USING_CAN + config BSP_USING_CAN0 + bool "Enable CAN0" + default n + config BSP_USING_CAN1 + bool "Enable CAN1" + default n + config BSP_USING_CAN2 + bool "Enable CAN2" + default n + config BSP_USING_CAN3 + bool "Enable CAN3" + default n + endif - menuconfig BSP_USING_CAN - bool "Enable CAN" - default n - select RT_USING_CAN if BSP_USING_CAN - if BSP_USING_CAN - config BSP_USING_CAN0 - bool "Enable CAN0" - default n - config BSP_USING_CAN1 - bool "Enable CAN1" - default n - config BSP_USING_CAN2 - bool "Enable CAN2" - default n - config BSP_USING_CAN3 - bool "Enable CAN3" - default n - endif menuconfig BSP_USING_ADC - bool "Enable ADC" - default n - select RT_USING_ADC if BSP_USING_ADC - if BSP_USING_ADC - menuconfig BSP_USING_ADC12 - bool "Enable ADC12" - default n - if BSP_USING_ADC12 - config BSP_USING_ADC0 - bool "Enable ADC0" - default n - config BSP_USING_ADC1 - bool "Enable ADC1" - default n - config BSP_USING_ADC2 - bool "Enable ADC2" - default n - endif + bool "Enable ADC" + default n + select RT_USING_ADC if BSP_USING_ADC + if BSP_USING_ADC + menuconfig BSP_USING_ADC12 + bool "Enable ADC12" + default n + if BSP_USING_ADC12 + config BSP_USING_ADC0 + bool "Enable ADC0" + default n + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + config BSP_USING_ADC2 + bool "Enable ADC2" + default n + endif menuconfig BSP_USING_ADC16 - bool "Enable ADC16" - default n + bool "Enable ADC16" + default n if BSP_USING_ADC16 config BSP_USING_ADC3 bool "Enable ADC3" default n endif endif + + menuconfig BSP_USING_CAMERA + bool "Enable camera" + default n + if BSP_USING_CAMERA + config BSP_USING_CAMERA_MT9M114 + bool "Enable mt9m114" + default y + + config BSP_USING_CAMERA_OV5640 + bool "Enable ov5640" + default n + + config BSP_USING_CAMERA_OV7725 + bool "Enable ov7725" + default n + endif + + menuconfig BSP_USING_JPEG + bool "Enable JPEG Driver" + default n + + menuconfig BSP_USING_CAM + bool "Enable CAM Driver" + default n + + menuconfig BSP_USING_PANEL + bool "Enable panel" + default n + if BSP_USING_PANEL + config BSP_USEING_PANEL_RGB_TM070RDH13 + bool "Enable RGB TM070RDH13" + default y + endif + menuconfig BSP_USING_RTT_LCD_DRIVER + bool "Enable RTT LCD Driver" + select BSP_USING_LCD + default n endmenu +menu "Segger SystemView Config" + config BSP_USING_SYSTEMVIEW + select RT_USING_SYSTEMVIEW + select RT_USING_LEGACY + bool "Enable Segger SystemView" + default n + if BSP_USING_SYSTEMVIEW + menuconfig BSP_SYSTEMVIEW_RTT_SECTION + bool "enable SystemView RTT section" + default y + if BSP_SYSTEMVIEW_RTT_SECTION + config SEGGER_RTT_SECTION + string "segger rtt section" + default ".noncacheable.bss" + config SEGGER_RTT_BUFFER_SECTION + string "segger rtt buffer section" + default ".noncacheable.bss" + config SEGGER_SYSVIEW_SECTION + string "segger sysview section" + default ".noncacheable.bss" + endif + source "$RTT_DIR/../libraries/misc/systemview/Kconfig" + endif +endmenu + +menu "Hpmicro Interrupt Config" + config HPM_USING_VECTOR_PREEMPTED_MODE + bool "Enable Vector and Preempted Mode" + default n +endmenu endmenu diff --git a/bsp/hpmicro/hpm6750evk2/board/SConscript b/bsp/hpmicro/hpm6750evk2/board/SConscript index 22253773860..2639fc87bb5 100644 --- a/bsp/hpmicro/hpm6750evk2/board/SConscript +++ b/bsp/hpmicro/hpm6750evk2/board/SConscript @@ -7,7 +7,6 @@ src = Split(""" board.c rtt_board.c pinmux.c - eth_phy_port.c fal_flash_port.c hpm_wm8960.c """) diff --git a/bsp/hpmicro/hpm6750evk2/board/board.c b/bsp/hpmicro/hpm6750evk2/board/board.c index 624bcbcd138..6034c7ae748 100644 --- a/bsp/hpmicro/hpm6750evk2/board/board.c +++ b/bsp/hpmicro/hpm6750evk2/board/board.c @@ -89,18 +89,23 @@ ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATU void board_init_console(void) { +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE #if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART console_config_t cfg; + /* uart needs to configure pin function before enabling clock, otherwise the level change of + uart rx pin when configuring pin function will cause a wrong data to be received. + And a uart rx dma request will be generated by default uart fifo dma trigger level. */ + init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE); + /* Configure the UART clock to 24MHz */ - clock_set_source_divider(BOARD_CONSOLE_CLK_NAME, clk_src_osc24m, 1U); + clock_set_source_divider(BOARD_CONSOLE_UART_CLK_NAME, clk_src_osc24m, 1U); + clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0); cfg.type = BOARD_CONSOLE_TYPE; - cfg.base = (uint32_t) BOARD_CONSOLE_BASE; - cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_CLK_NAME); - cfg.baudrate = BOARD_CONSOLE_BAUDRATE; - - init_uart_pins((UART_Type *) cfg.base); + cfg.base = (uint32_t) BOARD_CONSOLE_UART_BASE; + cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_UART_CLK_NAME); + cfg.baudrate = BOARD_CONSOLE_UART_BAUDRATE; if (status_success != console_init(&cfg)) { /* failed to initialize debug console */ @@ -108,7 +113,9 @@ void board_init_console(void) } } #else - while(1); + while (1) { + } +#endif #endif } @@ -138,6 +145,7 @@ void board_print_clock_freq(void) void board_init_uart(UART_Type *ptr) { + /* configure uart's pin before opening uart's clock */ init_uart_pins(ptr); board_init_uart_clock(ptr); } @@ -160,12 +168,15 @@ void board_print_banner(void) $$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\n\ \\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n\ ----------------------------------------------------------------------\n"}; +#ifdef SDK_VERSION_STRING + printf("hpm_sdk: %s\n", SDK_VERSION_STRING); +#endif printf("%s", banner); } static void board_turnoff_rgb_led(void) { - uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PE_SET(BOARD_LED_OFF_LEVEL); HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_GPIO_B_11; HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12; HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_GPIO_B_13; @@ -196,6 +207,12 @@ void board_init(void) #endif } +void board_init_core1(void) +{ + board_init_console(); + board_init_pmp(); +} + void board_init_sdram_pins(void) { init_sdram_pins(); @@ -209,62 +226,111 @@ uint32_t board_init_femc_clock(void) return clock_get_frequency(clock_femc); } -void board_power_cycle_lcd(void) +uint32_t board_lcdc_clock_init(clock_name_t clock_name, uint32_t pixel_clk_khz); + +#if defined(CONFIG_PANEL_RGB_TM070RDH13) && CONFIG_PANEL_RGB_TM070RDH13 + +static void set_reset_pin_level_tm070rdh13(uint8_t level) { - /* turn off backlight */ - gpio_set_pin_output(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN); - gpio_write_pin(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN, 0); + gpio_write_pin(BOARD_LCD_RESET_GPIO_BASE, BOARD_LCD_RESET_GPIO_INDEX, BOARD_LCD_RESET_GPIO_PIN, level); +} + +static void set_backlight_tm070rdh13(uint16_t percent) +{ + gpio_write_pin(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN, percent > 0 ? 1 : 0); +} + +void board_init_lcd_rgb_tm070rdh13(void) +{ + init_lcd_pins(BOARD_LCD_BASE); gpio_set_pin_output(BOARD_LCD_POWER_EN_GPIO_BASE, BOARD_LCD_POWER_EN_GPIO_INDEX, BOARD_LCD_POWER_EN_GPIO_PIN); gpio_write_pin(BOARD_LCD_POWER_EN_GPIO_BASE, BOARD_LCD_POWER_EN_GPIO_INDEX, BOARD_LCD_POWER_EN_GPIO_PIN, 0); gpio_write_pin(BOARD_LCD_POWER_EN_GPIO_BASE, BOARD_LCD_POWER_EN_GPIO_INDEX, BOARD_LCD_POWER_EN_GPIO_PIN, 1); - board_delay_ms(150); - /* power recycle */ + + gpio_set_pin_output(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN); gpio_set_pin_output(BOARD_LCD_RESET_GPIO_BASE, BOARD_LCD_RESET_GPIO_INDEX, BOARD_LCD_RESET_GPIO_PIN); - gpio_write_pin(BOARD_LCD_RESET_GPIO_BASE, BOARD_LCD_RESET_GPIO_INDEX, BOARD_LCD_RESET_GPIO_PIN, 0); - board_delay_ms(150); - gpio_write_pin(BOARD_LCD_RESET_GPIO_BASE, BOARD_LCD_RESET_GPIO_INDEX, BOARD_LCD_RESET_GPIO_PIN, 1); - board_delay_ms(150); - /* turn on backlight */ - gpio_write_pin(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN, 1); + hpm_panel_hw_interface_t hw_if = {0}; + hpm_panel_t *panel = hpm_panel_find_device_default(); + const hpm_panel_timing_t *timing = hpm_panel_get_timing(panel); + uint32_t lcdc_pixel_clk_khz = board_lcdc_clock_init(clock_display, timing->pixel_clock_khz); + hw_if.set_reset_pin_level = set_reset_pin_level_tm070rdh13; + hw_if.set_backlight = set_backlight_tm070rdh13; + hw_if.lcdc_pixel_clk_khz = lcdc_pixel_clk_khz; + hpm_panel_register_interface(panel, &hw_if); + + printf("name: %s, lcdc_clk: %ukhz\n", + hpm_panel_get_name(panel), + lcdc_pixel_clk_khz); + + hpm_panel_reset(panel); + hpm_panel_init(panel); + hpm_panel_power_on(panel); } -void board_init_lcd(void) -{ - board_init_lcd_clock(); - init_lcd_pins(BOARD_LCD_BASE); +#endif - board_power_cycle_lcd(); -} +#ifdef CONFIG_HPM_PANEL -void board_panel_para_to_lcdc(lcdc_config_t *config) +uint32_t board_lcdc_clock_init(clock_name_t clock_name, uint32_t pixel_clk_khz) { - const uint16_t panel_timing_para[] = BOARD_PANEL_TIMING_PARA; + clock_add_to_group(clock_name, 0); - config->resolution_x = BOARD_LCD_WIDTH; - config->resolution_y = BOARD_LCD_HEIGHT; + uint32_t freq_khz = clock_get_frequency(clk_pll4clk0) / 1000; + uint32_t div = (freq_khz + pixel_clk_khz / 2) / pixel_clk_khz; + clock_set_source_divider(clock_name, clk_src_pll4_clk0, div); + return clock_get_frequency(clock_name) / 1000; +} - config->hsync.pulse_width = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HSPW_INDEX]; - config->hsync.back_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HBP_INDEX]; - config->hsync.front_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HFP_INDEX]; +void board_lcd_backlight(bool is_on) +{ + hpm_panel_t *panel = hpm_panel_find_device_default(); + hpm_panel_set_backlight(panel, is_on == true ? 100 : 0); +} - config->vsync.pulse_width = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VSPW_INDEX]; - config->vsync.back_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VBP_INDEX]; - config->vsync.front_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VFP_INDEX]; +void board_init_lcd(void) +{ +#ifdef CONFIG_PANEL_RGB_TM070RDH13 + board_init_lcd_rgb_tm070rdh13(); +#endif +} - config->control.invert_hsync = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HSSP_INDEX]; - config->control.invert_vsync = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VSSP_INDEX]; - config->control.invert_href = panel_timing_para[BOARD_PANEL_TIMEING_PARA_DESP_INDEX]; - config->control.invert_pixel_data = panel_timing_para[BOARD_PANEL_TIMEING_PARA_PDSP_INDEX]; - config->control.invert_pixel_clock = panel_timing_para[BOARD_PANEL_TIMEING_PARA_PCSP_INDEX]; +void board_panel_para_to_lcdc(lcdc_config_t *config) +{ + const hpm_panel_timing_t *timing; + hpm_panel_t *panel = hpm_panel_find_device_default(); + + timing = hpm_panel_get_timing(panel); + config->resolution_x = timing->hactive; + config->resolution_y = timing->vactive; + + config->hsync.pulse_width = timing->hsync_len; + config->hsync.back_porch_pulse = timing->hback_porch; + config->hsync.front_porch_pulse = timing->hfront_porch; + + config->vsync.pulse_width = timing->vsync_len; + config->vsync.back_porch_pulse = timing->vback_porch; + config->vsync.front_porch_pulse = timing->vfront_porch; + + config->control.invert_hsync = timing->hsync_pol; + config->control.invert_vsync = timing->vsync_pol; + config->control.invert_href = timing->de_pol; + config->control.invert_pixel_data = timing->pixel_data_pol; + config->control.invert_pixel_clock = timing->pixel_clk_pol; } +#endif void board_delay_ms(uint32_t ms) { clock_cpu_delay_ms(ms); } +void board_delay_us(uint32_t us) +{ + clock_cpu_delay_us(us); +} + void board_timer_isr(void) { if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) { @@ -301,7 +367,8 @@ void board_i2c_bus_clear(I2C_Type *ptr) gpio_set_pin_input(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN); if (!gpio_read_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN)) { printf("CLK is low, please power cycle the board\n"); - while (1) {} + while (1) { + } } if (!gpio_read_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_SDA_GPIO_INDEX, BOARD_CAP_I2C_SDA_GPIO_PIN)) { printf("SDA is low, try to issue I2C bus clear\n"); @@ -346,7 +413,8 @@ void board_init_i2c(I2C_Type *ptr) stat = i2c_init_master(BOARD_CAP_I2C_BASE, freq, &config); if (stat != status_success) { printf("failed to initialize i2c 0x%x\n", (uint32_t)BOARD_CAP_I2C_BASE); - while (1) {} + while (1) { + } } } @@ -406,7 +474,7 @@ uint32_t board_init_spi_clock(SPI_Type *ptr) if (ptr == HPM_SPI2) { /* SPI2 clock configure */ clock_add_to_group(clock_spi2, 0); - clock_set_source_divider(clock_spi2, clk_src_osc24m, 1U); + clock_set_source_divider(clock_spi2, clk_src_pll1_clk1, 5U); /* 80MHz */ return clock_get_frequency(clock_spi2); } @@ -439,19 +507,42 @@ void board_init_spi_pins(SPI_Type *ptr) init_spi_pins(ptr); } +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + init_spi_pins_with_gpio_as_cs(ptr); + gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN), + GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL); +} + +void board_write_spi_cs(uint32_t pin, uint8_t state) +{ + gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state); +} + +uint8_t board_get_led_pwm_off_level(void) +{ + return BOARD_LED_OFF_LEVEL; +} + +uint8_t board_get_led_gpio_off_level(void) +{ + return BOARD_LED_OFF_LEVEL; +} + void board_init_led_pins(void) { + board_turnoff_rgb_led(); init_led_pins_as_gpio(); - gpio_set_pin_output_with_initial(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_OFF_LEVEL); - gpio_set_pin_output_with_initial(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_OFF_LEVEL); - gpio_set_pin_output_with_initial(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_OFF_LEVEL); + gpio_set_pin_output_with_initial(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, board_get_led_gpio_off_level()); + gpio_set_pin_output_with_initial(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, board_get_led_gpio_off_level()); + gpio_set_pin_output_with_initial(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, board_get_led_gpio_off_level()); } void board_led_toggle(void) { #ifdef BOARD_LED_TOGGLE_RGB static uint8_t i; - gpio_write_port(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, (7 & ~(1 << i)) << BOARD_R_GPIO_PIN); + gpio_write_port(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, (7 & (1 << i)) << BOARD_R_GPIO_PIN); i++; i = i % 3; #else @@ -493,38 +584,41 @@ void board_init_usb_pins(void) void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level) { + (void) usb_index; + (void) level; } void board_init_pmp(void) { + uint32_t start_addr; + uint32_t end_addr; + uint32_t length; + pmp_entry_t pmp_entry[16]; + uint8_t index = 0; + + /* Init noncachable memory */ extern uint32_t __noncacheable_start__[]; extern uint32_t __noncacheable_end__[]; - - uint32_t start_addr = (uint32_t) __noncacheable_start__; - uint32_t end_addr = (uint32_t) __noncacheable_end__; - uint32_t length = end_addr - start_addr; - - if (length == 0) { - return; + start_addr = (uint32_t) __noncacheable_start__; + end_addr = (uint32_t) __noncacheable_end__; + length = end_addr - start_addr; + if (length > 0) { + /* Ensure the address and the length are power of 2 aligned */ + assert((length & (length - 1U)) == 0U); + assert((start_addr & (length - 1U)) == 0U); + pmp_entry[index].pmp_addr = PMP_NAPOT_ADDR(start_addr, length); + pmp_entry[index].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK); + pmp_entry[index].pma_addr = PMA_NAPOT_ADDR(start_addr, length); + pmp_entry[index].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN); + index++; } - /* Ensure the address and the length are power of 2 aligned */ - assert((length & (length - 1U)) == 0U); - assert((start_addr & (length - 1U)) == 0U); - - pmp_entry_t pmp_entry[1]; - pmp_entry[0].pmp_addr = PMP_NAPOT_ADDR(start_addr, length); - pmp_entry[0].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK); - pmp_entry[0].pma_addr = PMA_NAPOT_ADDR(start_addr, length); - pmp_entry[0].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN); - - pmp_config(&pmp_entry[0], ARRAY_SIZE(pmp_entry)); + pmp_config(&pmp_entry[0], index); } void board_init_clock(void) { uint32_t cpu0_freq = clock_get_frequency(clock_cpu0); - hpm_core_clock = cpu0_freq; if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) { /* Configure the External OSC ramp-up time: ~9ms */ pllctl_xtal_set_rampup_time(HPM_PLLCTL, 32UL * 1000UL * 9U); @@ -534,6 +628,7 @@ void board_init_clock(void) } /* Add most Clocks to group 0 */ + /* not open uart clock in this API, uart should configure pin function before opening clock */ clock_add_to_group(clock_cpu0, 0); clock_add_to_group(clock_mchtmr0, 0); clock_add_to_group(clock_axi0, 0); @@ -618,19 +713,21 @@ void board_init_clock(void) /* Bump up DCDC voltage to 1200mv */ pcfg_dcdc_set_voltage(HPM_PCFG, 1200); + pcfg_dcdc_switch_to_dcm_mode(HPM_PCFG); if (status_success != pllctl_init_int_pll_with_freq(HPM_PLLCTL, 0, BOARD_CPU_FREQ)) { - printf("Failed to set pll0_clk0 to %ldHz\n", BOARD_CPU_FREQ); + printf("Failed to set pll0_clk0 to %luHz\n", BOARD_CPU_FREQ); while (1) { } } clock_set_source_divider(clock_cpu0, clk_src_pll0_clk0, 1); clock_set_source_divider(clock_cpu1, clk_src_pll0_clk0, 1); - /* Connect Group1 to CPU1 */ - clock_connect_group_to_cpu(1, 1); + clock_update_core_clock(); - clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 54); /* config clock_aud1 for 44100*n sample rate */ + clock_set_source_divider(clock_ahb, clk_src_pll1_clk1, 2); /*200m hz*/ + clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1); + clock_set_source_divider(clock_mchtmr1, clk_src_osc24m, 1); } uint32_t board_init_cam_clock(CAM_Type *ptr) @@ -654,48 +751,18 @@ uint32_t board_init_lcd_clock(void) { uint32_t freq; clock_add_to_group(clock_display, 0); - /* Configure LCDC clock to 29.7MHz */ - clock_set_source_divider(clock_display, clock_source_pll4_clk0, 10U); + /* Configure LCDC clock to 59.4MHz */ + clock_set_source_divider(clock_display, clk_src_pll4_clk0, 10U); freq = clock_get_frequency(clock_display); return freq; } -uint32_t board_init_adc12_clock(ADC12_Type *ptr) -{ - uint32_t freq = 0; - switch ((uint32_t) ptr) { - case HPM_ADC0_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc0, clk_adc_src_ana0); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); - freq = clock_get_frequency(clock_adc0); - break; - case HPM_ADC1_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc1, clk_adc_src_ana0); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); - freq = clock_get_frequency(clock_adc1); - break; - case HPM_ADC2_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc2, clk_adc_src_ana0); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); - freq = clock_get_frequency(clock_adc2); - break; - default: - /* Invalid ADC instance */ - break; - } - - return freq; -} - uint32_t board_init_dao_clock(void) { clock_add_to_group(clock_dao, 0); - sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); - sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud0_clk); + sysctl_config_clock(HPM_SYSCTL, clock_node_aud1, clock_source_pll3_clk0, 25); + sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud1_clk); return clock_get_frequency(clock_dao); } @@ -710,26 +777,134 @@ uint32_t board_init_pdm_clock(void) return clock_get_frequency(clock_pdm); } +hpm_stat_t board_set_audio_pll_clock(uint32_t freq) +{ + return pllctl_init_frac_pll_with_freq(HPM_PLLCTL, 3, freq); /* pll3clk */ +} + +void board_init_i2s_pins(I2S_Type *ptr) +{ + init_i2s_pins(ptr); +} + uint32_t board_init_i2s_clock(I2S_Type *ptr) { + uint32_t freq = 0; + if (ptr == HPM_I2S0) { clock_add_to_group(clock_i2s0, 0); sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk); - return clock_get_frequency(clock_i2s0); + freq = clock_get_frequency(clock_i2s0); + } else if (ptr == HPM_I2S1) { + clock_add_to_group(clock_i2s1, 0); + + sysctl_config_clock(HPM_SYSCTL, clock_node_aud1, clock_source_pll3_clk0, 25); + sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud1_clk); + + freq = clock_get_frequency(clock_i2s1); + } else { + ; } - return 0; + + return freq; +} + +/* adjust I2S source clock base on sample rate */ +uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate) +{ + uint32_t freq = 0; + + if (ptr == HPM_I2S0) { + clock_add_to_group(clock_i2s0, 0); + if ((sample_rate % 22050) == 0) { + clock_set_source_divider(clock_aud0, clk_src_pll3_clk0, 54); /* config clock_aud1 for 22050*n sample rate */ + } else { + clock_set_source_divider(clock_aud0, clk_src_pll3_clk0, 25); /* config clock_aud0 for 8000*n sample rate */ + } + clock_set_i2s_source(clock_i2s0, clk_i2s_src_aud0); + freq = clock_get_frequency(clock_i2s0); + } else if (ptr == HPM_I2S1) { + clock_add_to_group(clock_i2s1, 0); + if ((sample_rate % 22050) == 0) { + clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 54); /* config clock_aud1 for 22050*n sample rate */ + } else { + clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 25); /* config clock_aud0 for 8000*n sample rate */ + } + clock_set_i2s_source(clock_i2s1, clk_i2s_src_aud1); + freq = clock_get_frequency(clock_i2s1); + } else { + ; + } + + return freq; +} + +void board_init_adc12_pins(void) +{ + init_adc12_pins(); +} + +void board_init_adc16_pins(void) +{ + init_adc16_pins(); +} + +uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb) +{ + uint32_t freq = 0; + + if (ptr == HPM_ADC0) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + } + freq = clock_get_frequency(clock_adc0); + } else if (ptr == HPM_ADC1) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc1, clk_adc_src_ana1); + clock_set_source_divider(clock_ana1, clk_src_pll1_clk1, 2U); + } + freq = clock_get_frequency(clock_adc1); + } else if (ptr == HPM_ADC2) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc2, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc2, clk_adc_src_ana2); + clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U); + } + freq = clock_get_frequency(clock_adc2); + } + + return freq; } -uint32_t board_init_adc16_clock(ADC16_Type *ptr) +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) { uint32_t freq = 0; + if (ptr == HPM_ADC3) { - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc3, clk_adc_src_ana1); - clock_set_source_divider(clock_ana1, clk_src_pll1_clk1, 2U); + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc3, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc3, clk_adc_src_ana2); + clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U); + } + freq = clock_get_frequency(clock_adc3); } @@ -813,6 +988,7 @@ uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) else { /* Invalid instance */ } + return freq; } @@ -830,7 +1006,6 @@ void _init_ext_ram(void) femc_sdram_config_t sdram_config = {0}; femc_default_config(HPM_FEMC, &config); - config.dqs = FEMC_DQS_INTERNAL; femc_init(HPM_FEMC, &config); sdram_config.bank_num = FEMC_SDRAM_BANK_NUM_4; @@ -860,32 +1035,25 @@ void _init_ext_ram(void) sdram_config.refresh_count = BOARD_SDRAM_REFRESH_COUNT; sdram_config.refresh_in_ms = BOARD_SDRAM_REFRESH_IN_MS; sdram_config.data_width_in_byte = BOARD_SDRAM_DATA_WIDTH_IN_BYTE; - sdram_config.delay_cell_value = 29; + sdram_config.delay_cell_disable = true; + sdram_config.delay_cell_value = 0; femc_config_sdram(HPM_FEMC, femc_clk_in_hz, &sdram_config); } - -void board_init_sd_pins(SDXC_Type *ptr) -{ - init_sdxc_pins(ptr, false); - init_sdxc_card_detection_pin(ptr); -} - void board_sd_power_switch(SDXC_Type *ptr, bool on_off) { - if (ptr == HPM_SDXC1) { - init_sdxc_power_pin(ptr); + if (ptr == BOARD_APP_SDCARD_SDXC_BASE) { + init_sdxc_pwr_pin(ptr, true); gpio_set_pin_output_with_initial(BOARD_APP_SDCARD_POWER_EN_GPIO_BASE, BOARD_APP_SDCARD_POWER_EN_GPIO_INDEX, BOARD_APP_SDCARD_POWER_EN_GPIO_PIN, on_off); } } - -uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq) +uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inverse) { uint32_t actual_freq = 0; do { - if (ptr != HPM_SDXC1) { + if (ptr != BOARD_APP_SDCARD_SDXC_BASE) { break; } clock_name_t sdxc_clk = (ptr == HPM_SDXC0) ? clock_sdxc0 : clock_sdxc1; @@ -896,11 +1064,11 @@ uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq) clock_set_source_divider(sdxc_clk, clk_src_osc24m, 63); } /* configure the clock to 24MHz for the SDR12/Default speed */ - else if (freq <= 25000000UL) { + else if (freq <= 26000000UL) { clock_set_source_divider(sdxc_clk, clk_src_osc24m, 1); } /* Configure the clock to 50MHz for the SDR25/High speed/50MHz DDR/50MHz SDR */ - else if (freq <= 50000000UL) { + else if (freq <= 52000000UL) { clock_set_source_divider(sdxc_clk, clk_src_pll1_clk1, 8); } /* Configure the clock to 100MHz for the SDR50 */ @@ -915,7 +1083,9 @@ uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq) else { clock_set_source_divider(sdxc_clk, clk_src_osc24m, 1); } - sdxc_enable_inverse_clock(ptr, true); + if (need_inverse) { + sdxc_enable_inverse_clock(ptr, true); + } sdxc_enable_sd_clock(ptr, true); actual_freq = clock_get_frequency(sdxc_clk); } while (false); @@ -1043,30 +1213,35 @@ hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr) hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) { - if (internal == false) { - return status_success; - } /* Configure Enet clock to output reference clock */ - if (ptr == HPM_ENET0) { - /* make sure pll2_clk1 output clock at 250MHz then set 50MHz for enet0 */ - clock_set_source_divider(clock_eth0, clk_src_pll2_clk1, 5); - } else if (ptr == HPM_ENET1) { - /* make sure pll2_clk1 output clock at 250MHz then set 50MHz for enet1 */ - clock_set_source_divider(clock_eth1, clk_src_pll2_clk1, 5); /* set 50MHz for enet1 */ + if (ptr == HPM_ENET1) { + if (internal) { + /* set pll output frequency at 1GHz */ + if (pllctl_init_int_pll_with_freq(HPM_PLLCTL, PLLCTL_PLL_PLL2, 1000000000UL) == status_success) { + /* set pll2_clk1 output frequence at 250MHz from PLL2 divided by 4 */ + pllctl_set_div(HPM_PLLCTL, PLLCTL_PLL_PLL2, 1, 4); + /* set eth clock frequency at 50MHz for enet0 */ + clock_set_source_divider(ptr == HPM_ENET0 ? clock_eth0 : clock_eth1, clk_src_pll2_clk1, 5); + } else { + return status_fail; + } + } } else { return status_invalid_argument; } + + enet_rmii_enable_clock(ptr, internal); + return status_success; } -void board_init_adc12_pins(void) +hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr) { - init_adc12_pins(); -} + if (ptr == HPM_ENET0) { + return enet_rgmii_set_clock_delay(ptr, BOARD_ENET_RGMII_TX_DLY, BOARD_ENET_RGMII_RX_DLY); + } -void board_init_adc16_pins(void) -{ - init_adc16_pins(); + return status_invalid_argument; } hpm_stat_t board_init_enet_pins(ENET_Type *ptr) @@ -1074,9 +1249,9 @@ hpm_stat_t board_init_enet_pins(ENET_Type *ptr) init_enet_pins(ptr); if (ptr == HPM_ENET0) { - gpio_set_pin_output_with_initial(BOARD_ENET0_RST_GPIO, BOARD_ENET0_RST_GPIO_INDEX, BOARD_ENET0_RST_GPIO_PIN, 0); - } else if (ptr == HPM_ENET1) { - gpio_set_pin_output_with_initial(BOARD_ENET1_RST_GPIO, BOARD_ENET1_RST_GPIO_INDEX, BOARD_ENET1_RST_GPIO_PIN, 0); + gpio_set_pin_output_with_initial(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 0); + } else if (ptr == HPM_ENET1) { + gpio_set_pin_output_with_initial(BOARD_ENET_RMII_RST_GPIO, BOARD_ENET_RMII_RST_GPIO_INDEX, BOARD_ENET_RMII_RST_GPIO_PIN, 0); } else { return status_invalid_argument; } @@ -1087,13 +1262,13 @@ hpm_stat_t board_init_enet_pins(ENET_Type *ptr) hpm_stat_t board_reset_enet_phy(ENET_Type *ptr) { if (ptr == HPM_ENET0) { - gpio_write_pin(BOARD_ENET0_RST_GPIO, BOARD_ENET0_RST_GPIO_INDEX, BOARD_ENET0_RST_GPIO_PIN, 0); - board_delay_ms(BOARD_ENET0_PHY_RST_TIME); - gpio_write_pin(BOARD_ENET0_RST_GPIO, BOARD_ENET0_RST_GPIO_INDEX, BOARD_ENET0_RST_GPIO_PIN, 1); + gpio_write_pin(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 0); + board_delay_ms(1); + gpio_write_pin(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 1); } else if (ptr == HPM_ENET1) { - gpio_write_pin(BOARD_ENET1_RST_GPIO, BOARD_ENET1_RST_GPIO_INDEX, BOARD_ENET1_RST_GPIO_PIN, 0); - board_delay_ms(BOARD_ENET1_PHY_RST_TIME); - gpio_write_pin(BOARD_ENET1_RST_GPIO, BOARD_ENET1_RST_GPIO_INDEX, BOARD_ENET1_RST_GPIO_PIN, 1); + gpio_write_pin(BOARD_ENET_RMII_RST_GPIO, BOARD_ENET_RMII_RST_GPIO_INDEX, BOARD_ENET_RMII_RST_GPIO_PIN, 0); + board_delay_ms(1); + gpio_write_pin(BOARD_ENET_RMII_RST_GPIO, BOARD_ENET_RMII_RST_GPIO_INDEX, BOARD_ENET_RMII_RST_GPIO_PIN, 1); } else { return status_invalid_argument; } @@ -1101,7 +1276,131 @@ hpm_stat_t board_reset_enet_phy(ENET_Type *ptr) return status_success; } -uint8_t board_enet_get_dma_pbl(ENET_Type *ptr) +uint8_t board_get_enet_dma_pbl(ENET_Type *ptr) { + (void) ptr; return enet_pbl_32; } + +hpm_stat_t board_enable_enet_irq(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + intc_m_enable_irq(IRQn_ENET0); + } else if (ptr == HPM_ENET1) { + intc_m_enable_irq(IRQn_ENET1); + } else { + return status_invalid_argument; + } + + return status_success; +} + +hpm_stat_t board_disable_enet_irq(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + intc_m_disable_irq(IRQn_ENET0); + } else if (ptr == HPM_ENET1) { + intc_m_disable_irq(IRQn_ENET1); + } else { + return status_invalid_argument; + } + + return status_success; +} + +void board_init_enet_pps_pins(ENET_Type *ptr) +{ + (void) ptr; + init_enet_pps_pins(); +} + +#if defined(ENET_MULTIPLE_PORT) && ENET_MULTIPLE_PORT + +hpm_stat_t board_init_multiple_enet_pins(void) +{ + board_init_enet_pins(HPM_ENET0); + board_init_enet_pins(HPM_ENET1); + + return status_success; +} + +hpm_stat_t board_init_multiple_enet_clock(void) +{ + /* Set RGMII clock delay */ + board_init_enet_rgmii_clock_delay(HPM_ENET0); + + /* Set RMII reference clock */ + board_init_enet_rmii_reference_clock(HPM_ENET1, BOARD_ENET_RMII_INT_REF_CLK); + printf("Enet1 Reference Clock: %s\n", BOARD_ENET_RMII_INT_REF_CLK ? "Internal Clock" : "External Clock"); + + return status_success; +} + +hpm_stat_t board_reset_multiple_enet_phy(void) +{ + board_reset_enet_phy(HPM_ENET0); + board_reset_enet_phy(HPM_ENET1); + + return status_success; +} + +hpm_stat_t board_init_enet_phy(ENET_Type *ptr) +{ + rtl8211_config_t phy_config0; + rtl8201_config_t phy_config1; + + if (ptr == HPM_ENET0) { + rtl8211_reset(ptr); + rtl8211_basic_mode_default_config(HPM_ENET0, &phy_config0); + if (rtl8211_basic_mode_init(HPM_ENET0, &phy_config0) == true) { + return status_success; + } else { + printf("Enet0 phy init failed!\n"); + return status_fail; + } + } else if (ptr == HPM_ENET1) { + rtl8201_reset(HPM_ENET1); + rtl8201_basic_mode_default_config(HPM_ENET1, &phy_config1); + if (rtl8201_basic_mode_init(HPM_ENET1, &phy_config1) == true) { + return status_success; + } else { + printf("Enet1 phy init failed!\n"); + return status_fail; + } + } else { + return status_invalid_argument; + } +} + +ENET_Type *board_get_enet_base(uint8_t idx) +{ + if (idx == 0) { + return HPM_ENET0; + } else { + return HPM_ENET1; + } +} + +uint8_t board_get_enet_phy_itf(uint8_t idx) +{ + if (idx == 0) { + return BOARD_ENET_RGMII_PHY_ITF; + } else { + return BOARD_ENET_RMII_PHY_ITF; + } +} + +void board_get_enet_phy_status(uint8_t idx, void *status) +{ + if (idx == 0) { + rtl8211_get_phy_status(HPM_ENET0, status); + } else { + rtl8201_get_phy_status(HPM_ENET1, status); + } +} +#endif + +void board_init_dao_pins(void) +{ + init_dao_pins(); +} diff --git a/bsp/hpmicro/hpm6750evk2/board/board.h b/bsp/hpmicro/hpm6750evk2/board/board.h index 1c282cd89e4..7d6487312e7 100644 --- a/bsp/hpmicro/hpm6750evk2/board/board.h +++ b/bsp/hpmicro/hpm6750evk2/board/board.h @@ -14,171 +14,221 @@ #include "hpm_soc_feature.h" #include "pinmux.h" #include "hpm_lcdc_drv.h" +#include "hpm_trgm_drv.h" +#ifdef CONFIG_HPM_PANEL +#include "hpm_panel.h" +#endif +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#include "hpm_debug_console.h" +#endif -#define BOARD_NAME "hpm6750evk" +#define BOARD_NAME "hpm6750evk2" #define BOARD_UF2_SIGNATURE (0x0A4D5048UL) -/* uart section */ +#define SEC_CORE_IMG_START ILM_LOCAL_BASE + #ifndef BOARD_RUNNING_CORE #define BOARD_RUNNING_CORE HPM_CORE0 #endif + +/* uart section */ #ifndef BOARD_APP_UART_BASE -#define BOARD_APP_UART_BASE HPM_UART0 -#define BOARD_APP_UART_IRQ IRQn_UART0 -#else -#ifndef BOARD_APP_UART_IRQ -#warning no IRQ specified for applicaiton uart -#endif +#define BOARD_APP_UART_BASE HPM_UART13 +#define BOARD_APP_UART_IRQ IRQn_UART13 +#define BOARD_APP_UART_BAUDRATE (115200UL) +#define BOARD_APP_UART_CLK_NAME clock_uart13 +#define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART13_RX +#define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART13_TX #endif /* uart rx idle demo section */ -#define BOARD_UART_IDLE HPM_UART13 -#define BOARD_UART_IDLE_DMA_SRC HPM_DMA_SRC_UART13_RX - -#define BOARD_UART_IDLE_TRGM HPM_TRGM2 -#define BOARD_UART_IDLE_TRGM_PIN IOC_PAD_PD19 -#define BOARD_UART_IDLE_TRGM_INPUT_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P9 -#define BOARD_UART_IDLE_TRGM_OUTPUT_GPTMR_IN HPM_TRGM2_OUTPUT_SRC_GPTMR4_IN2 +#define BOARD_UART_IDLE BOARD_APP_UART_BASE +#define BOARD_UART_IDLE_IRQ BOARD_APP_UART_IRQ +#define BOARD_UART_IDLE_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_UART_IDLE_TX_DMA_SRC BOARD_APP_UART_TX_DMA_REQ +#define BOARD_UART_IDLE_DMA_SRC BOARD_APP_UART_RX_DMA_REQ + +#define BOARD_UART_IDLE_TRGM HPM_TRGM2 +#define BOARD_UART_IDLE_TRGM_PIN IOC_PAD_PD19 +#define BOARD_UART_IDLE_TRGM_INPUT_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P9 +#define BOARD_UART_IDLE_TRGM_OUTPUT_GPTMR_IN HPM_TRGM2_OUTPUT_SRC_GPTMR4_IN2 #define BOARD_UART_IDLE_TRGM_OUTPUT_GPTMR_SYNCI HPM_TRGM2_OUTPUT_SRC_GPTMR4_SYNCI -#define BOARD_UART_IDLE_GPTMR HPM_GPTMR4 +#define BOARD_UART_IDLE_GPTMR HPM_GPTMR4 #define BOARD_UART_IDLE_GPTMR_CLK_NAME clock_gptmr4 -#define BOARD_UART_IDLE_GPTMR_IRQ IRQn_GPTMR4 -#define BOARD_UART_IDLE_GPTMR_CMP_CH 0 -#define BOARD_UART_IDLE_GPTMR_CAP_CH 2 - -#define BOARD_APP_UART_BAUDRATE (115200UL) -#define BOARD_APP_UART_CLK_NAME clock_uart0 - +#define BOARD_UART_IDLE_GPTMR_IRQ IRQn_GPTMR4 +#define BOARD_UART_IDLE_GPTMR_CMP_CH 0 +#define BOARD_UART_IDLE_GPTMR_CAP_CH 2 + +/* uart microros sample section */ +#define BOARD_MICROROS_UART_BASE BOARD_APP_UART_BASE +#define BOARD_MICROROS_UART_IRQ BOARD_APP_UART_IRQ +#define BOARD_MICROROS_UART_CLK_NAME BOARD_APP_UART_CLK_NAME + +/* rtthread-nano finsh section */ +#define BOARD_RT_CONSOLE_BASE BOARD_CONSOLE_UART_BASE + +/* usb cdc acm uart section */ +#define BOARD_USB_CDC_ACM_UART BOARD_APP_UART_BASE +#define BOARD_USB_CDC_ACM_UART_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_USB_CDC_ACM_UART_TX_DMA_SRC BOARD_APP_UART_TX_DMA_REQ +#define BOARD_USB_CDC_ACM_UART_RX_DMA_SRC BOARD_APP_UART_RX_DMA_REQ + +/* modbus sample section */ +#define BOARD_MODBUS_UART_BASE BOARD_APP_UART_BASE +#define BOARD_MODBUS_UART_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_MODBUS_UART_RX_DMA_REQ BOARD_APP_UART_RX_DMA_REQ +#define BOARD_MODBUS_UART_TX_DMA_REQ BOARD_APP_UART_TX_DMA_REQ + +/* uart lin sample section */ +#define BOARD_UART_LIN BOARD_APP_UART_BASE +#define BOARD_UART_LIN_IRQ BOARD_APP_UART_IRQ +#define BOARD_UART_LIN_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_UART_LIN_TX_PORT GPIO_DI_GPIOZ +#define BOARD_UART_LIN_TX_PIN (9U) /* PZ09 should align with used pin in pinmux configuration */ + +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE #ifndef BOARD_CONSOLE_TYPE #define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART #endif #if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART -#ifndef BOARD_CONSOLE_BASE +#ifndef BOARD_CONSOLE_UART_BASE #if BOARD_RUNNING_CORE == HPM_CORE0 -#define BOARD_CONSOLE_BASE HPM_UART0 -#define BOARD_CONSOLE_CLK_NAME clock_uart0 +#define BOARD_CONSOLE_UART_BASE HPM_UART0 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART0 +#define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX +#define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX #else -#define BOARD_CONSOLE_BASE HPM_UART13 -#define BOARD_CONSOLE_CLK_NAME clock_uart13 +#define BOARD_CONSOLE_UART_BASE HPM_UART13 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart13 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART13 +#define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART13_TX +#define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART13_RX #endif #endif -#define BOARD_CONSOLE_BAUDRATE (115200UL) +#define BOARD_CONSOLE_UART_BAUDRATE (115200UL) +#endif #endif - - -#define BOARD_FREEMASTER_UART_BASE HPM_UART0 -#define BOARD_FREEMASTER_UART_IRQ IRQn_UART0 -#define BOARD_FREEMASTER_UART_CLK_NAME clock_uart0 /* sdram section */ -#define BOARD_SDRAM_ADDRESS (0x40000000UL) -#define BOARD_SDRAM_SIZE (32*SIZE_1MB) -#define BOARD_SDRAM_CS FEMC_SDRAM_CS0 -#define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_32_BITS -#define BOARD_SDRAM_REFRESH_COUNT (8192UL) -#define BOARD_SDRAM_REFRESH_IN_MS (64UL) +#define BOARD_SDRAM_ADDRESS (0x40000000UL) +#define BOARD_SDRAM_SIZE (32 * SIZE_1MB) +#define BOARD_SDRAM_CS FEMC_SDRAM_CS0 +#define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_32_BITS +#define BOARD_SDRAM_REFRESH_COUNT (8192UL) +#define BOARD_SDRAM_REFRESH_IN_MS (64UL) #define BOARD_SDRAM_DATA_WIDTH_IN_BYTE (4UL) #define BOARD_FLASH_BASE_ADDRESS (0x80000000UL) -#define BOARD_FLASH_SIZE (16 << 20) +#define BOARD_FLASH_SIZE (16 << 20) + +#define BOARD_FEMC_DQS_FLOATING 1 /* lcd section */ -#define BOARD_LCD_BASE HPM_LCDC -#define BOARD_LCD_IRQ IRQn_LCDC_D0 -#define BOARD_LCD_RESET_GPIO_BASE HPM_GPIO0 -#define BOARD_LCD_RESET_GPIO_INDEX GPIO_DO_GPIOB -#define BOARD_LCD_RESET_GPIO_PIN 16 -#define BOARD_LCD_BACKLIGHT_GPIO_BASE HPM_GPIO0 +#define BOARD_LCD_BASE HPM_LCDC +#define BOARD_LCD_IRQ IRQn_LCDC_D0 +#define BOARD_LCD_RESET_GPIO_BASE HPM_GPIO0 +#define BOARD_LCD_RESET_GPIO_INDEX GPIO_DO_GPIOB +#define BOARD_LCD_RESET_GPIO_PIN 16 +#define BOARD_LCD_BACKLIGHT_GPIO_BASE HPM_GPIO0 #define BOARD_LCD_BACKLIGHT_GPIO_INDEX GPIO_DO_GPIOB -#define BOARD_LCD_BACKLIGHT_GPIO_PIN 10 -#define BOARD_LCD_POWER_EN_GPIO_BASE HPM_GPIO0 -#define BOARD_LCD_POWER_EN_GPIO_INDEX GPIO_DO_GPIOZ -#define BOARD_LCD_POWER_EN_GPIO_PIN 00 +#define BOARD_LCD_BACKLIGHT_GPIO_PIN 10 +#define BOARD_LCD_POWER_EN_GPIO_BASE HPM_GPIO0 +#define BOARD_LCD_POWER_EN_GPIO_INDEX GPIO_DO_GPIOZ +#define BOARD_LCD_POWER_EN_GPIO_PIN 00 /* i2c section */ -#define BOARD_APP_I2C_BASE HPM_I2C0 +#define BOARD_APP_I2C_BASE HPM_I2C0 +#define BOARD_APP_I2C_IRQ IRQn_I2C0 #define BOARD_APP_I2C_CLK_NAME clock_i2c0 -#define BOARD_APP_I2C_DMA HPM_HDMA -#define BOARD_APP_I2C_DMAMUX HPM_DMAMUX -#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0 -#define BOARD_APP_I2C_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 +#define BOARD_APP_I2C_DMA HPM_HDMA +#define BOARD_APP_I2C_DMAMUX HPM_DMAMUX +#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0 -#define BOARD_CAM_I2C_BASE HPM_I2C0 +#define BOARD_CAM_I2C_BASE HPM_I2C0 #define BOARD_CAM_I2C_CLK_NAME clock_i2c0 #define BOARD_SUPPORT_CAM_RESET -#define BOARD_CAM_RST_GPIO_CTRL HPM_GPIO0 +#define BOARD_CAM_RST_GPIO_CTRL HPM_GPIO0 #define BOARD_CAM_RST_GPIO_INDEX GPIO_DI_GPIOY -#define BOARD_CAM_RST_GPIO_PIN 5 - -#define BOARD_CAP_I2C_BASE (HPM_I2C0) -#define BOARD_CAP_I2C_CLK_NAME clock_i2c0 -#define BOARD_CAP_RST_GPIO (HPM_GPIO0) -#define BOARD_CAP_RST_GPIO_INDEX (GPIO_DI_GPIOB) -#define BOARD_CAP_RST_GPIO_PIN (9) -#define BOARD_CAP_RST_GPIO_IRQ (IRQn_GPIO0_B) -#define BOARD_CAP_INTR_GPIO (HPM_GPIO0) -#define BOARD_CAP_INTR_GPIO_INDEX (GPIO_DI_GPIOB) -#define BOARD_CAP_INTR_GPIO_PIN (8) -#define BOARD_CAP_INTR_GPIO_IRQ (IRQn_GPIO0_B) +#define BOARD_CAM_RST_GPIO_PIN 5 + +#define BOARD_CAP_I2C_BASE (HPM_I2C0) +#define BOARD_CAP_I2C_CLK_NAME clock_i2c0 +#define BOARD_CAP_RST_GPIO (HPM_GPIO0) +#define BOARD_CAP_RST_GPIO_INDEX (GPIO_DI_GPIOB) +#define BOARD_CAP_RST_GPIO_PIN (9) +#define BOARD_CAP_RST_GPIO_IRQ (IRQn_GPIO0_B) +#define BOARD_CAP_INTR_GPIO (HPM_GPIO0) +#define BOARD_CAP_INTR_GPIO_INDEX (GPIO_DI_GPIOB) +#define BOARD_CAP_INTR_GPIO_PIN (8) +#define BOARD_CAP_INTR_GPIO_IRQ (IRQn_GPIO0_B) #define BOARD_CAP_I2C_SDA_GPIO_INDEX (GPIO_DI_GPIOZ) -#define BOARD_CAP_I2C_SDA_GPIO_PIN (10) +#define BOARD_CAP_I2C_SDA_GPIO_PIN (10) #define BOARD_CAP_I2C_CLK_GPIO_INDEX (GPIO_DI_GPIOZ) -#define BOARD_CAP_I2C_CLK_GPIO_PIN (11) +#define BOARD_CAP_I2C_CLK_GPIO_PIN (11) /* ACMP desction */ -#define BOARD_ACMP HPM_ACMP -#define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 -#define BOARD_ACMP_IRQ IRQn_ACMP_1 -#define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ +#define BOARD_ACMP HPM_ACMP +#define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 +#define BOARD_ACMP_IRQ IRQn_ACMP_1 +#define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ #define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_6 /* align with used pin */ /* dma section */ -#define BOARD_APP_XDMA HPM_XDMA -#define BOARD_APP_HDMA HPM_HDMA +#define BOARD_APP_XDMA HPM_XDMA +#define BOARD_APP_HDMA HPM_HDMA #define BOARD_APP_XDMA_IRQ IRQn_XDMA #define BOARD_APP_HDMA_IRQ IRQn_HDMA -#define BOARD_APP_DMAMUX HPM_DMAMUX +#define BOARD_APP_DMAMUX HPM_DMAMUX /* gptmr section */ -#define BOARD_GPTMR HPM_GPTMR4 -#define BOARD_GPTMR_IRQ IRQn_GPTMR4 -#define BOARD_GPTMR_CHANNEL 1 -#define BOARD_GPTMR_PWM HPM_GPTMR3 -#define BOARD_GPTMR_PWM_CHANNEL 1 +#define BOARD_GPTMR HPM_GPTMR4 +#define BOARD_GPTMR_IRQ IRQn_GPTMR4 +#define BOARD_GPTMR_CHANNEL 1 +#define BOARD_GPTMR_DMA_SRC HPM_DMA_SRC_GPTMR4_1 +#define BOARD_GPTMR_CLK_NAME clock_gptmr4 +#define BOARD_GPTMR_PWM HPM_GPTMR5 +#define BOARD_GPTMR_PWM_DMA_SRC HPM_DMA_SRC_GPTMR5_2 +#define BOARD_GPTMR_PWM_CHANNEL 2 +#define BOARD_GPTMR_PWM_CLK_NAME clock_gptmr5 +#define BOARD_GPTMR_PWM_IRQ IRQn_GPTMR5 +#define BOARD_GPTMR_PWM_SYNC HPM_GPTMR5 +#define BOARD_GPTMR_PWM_SYNC_CHANNEL 3 +#define BOARD_GPTMR_PWM_SYNC_CLK_NAME clock_gptmr5 /* gpio section */ -#define BOARD_R_GPIO_CTRL HPM_GPIO0 +#define BOARD_R_GPIO_CTRL HPM_GPIO0 #define BOARD_R_GPIO_INDEX GPIO_DI_GPIOB -#define BOARD_R_GPIO_PIN 11 -#define BOARD_G_GPIO_CTRL HPM_GPIO0 +#define BOARD_R_GPIO_PIN 11 +#define BOARD_G_GPIO_CTRL HPM_GPIO0 #define BOARD_G_GPIO_INDEX GPIO_DI_GPIOB -#define BOARD_G_GPIO_PIN 12 -#define BOARD_B_GPIO_CTRL HPM_GPIO0 +#define BOARD_G_GPIO_PIN 12 +#define BOARD_B_GPIO_CTRL HPM_GPIO0 #define BOARD_B_GPIO_INDEX GPIO_DI_GPIOB -#define BOARD_B_GPIO_PIN 13 +#define BOARD_B_GPIO_PIN 13 #define BOARD_LED_GPIO_CTRL HPM_GPIO0 #define BOARD_LED_GPIO_INDEX GPIO_DI_GPIOB -#define BOARD_LED_GPIO_PIN 12 -#define BOARD_LED_OFF_LEVEL 1 -#define BOARD_LED_ON_LEVEL 0 +#define BOARD_LED_GPIO_PIN 12 +#define BOARD_LED_OFF_LEVEL 0 +#define BOARD_LED_ON_LEVEL 1 #define BOARD_LED_TOGGLE_RGB 1 #define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOZ -#define BOARD_APP_GPIO_PIN 2 +#define BOARD_APP_GPIO_PIN 2 /* pinmux section */ #define USING_GPIO0_FOR_GPIOZ #ifndef USING_GPIO0_FOR_GPIOZ #define BOARD_APP_GPIO_CTRL HPM_BGPIO -#define BOARD_APP_GPIO_IRQ IRQn_BGPIO +#define BOARD_APP_GPIO_IRQ IRQn_BGPIO #else #define BOARD_APP_GPIO_CTRL HPM_GPIO0 -#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_Z +#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_Z #endif /* gpiom section */ @@ -187,92 +237,72 @@ #define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast /* spi section */ -#define BOARD_APP_SPI_BASE HPM_SPI2 -#define BOARD_APP_SPI_CLK_SRC_FREQ (24000000UL) -#define BOARD_APP_SPI_SCLK_FREQ (1562500UL) +#define BOARD_APP_SPI_BASE HPM_SPI2 +#define BOARD_APP_SPI_CLK_NAME clock_spi2 +#define BOARD_APP_SPI_IRQ IRQn_SPI2 +#define BOARD_APP_SPI_SCLK_FREQ (20000000UL) #define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U) #define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U) -#define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI2_RX -#define BOARD_APP_SPI_RX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 -#define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI2_TX -#define BOARD_APP_SPI_TX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX1 - +#define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI2_RX +#define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI2_TX +#define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 +#define BOARD_SPI_CS_PIN IOC_PAD_PE31 +#define BOARD_SPI_CS_ACTIVE_LEVEL (0U) /* Flash section */ -#define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) -#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90001U) -#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000005U) -#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) +#define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) +#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90001U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000005U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) /* lcd section */ -/* - * BOARD_PANEL_TIMING_PARA {HSPW, HBP, HFP, VSPW, VBP, VFP, HSSP, VSSP, DESP, PDSP, PCSP} - * - * HSPW: Horizontal Synchronization Pulse width - * HBP: Horizontal Back Porch - * HFP: Horizontal Front Porch - * VSPW: Vertical Synchronization Pulse width - * VBP: Vertical Back Porch - * VFP: Vertical Front Porch - * HSSP: Horizontal Synchronization Signal Polarity, 0: High Active, 1: Low Active - * VSSP: Vertical Synchronization Signal Polarity, 0: High Active, 1: Low Active - * DESP: Data Enable Signal Polarity, 0: High Active, 1: Low Active - * PDSP: Pixel Data Signal Polarity, 0: High Active, 1: Low Active - * PCSP: Pixel Clock Signal Polarity, 0: High Active, 1: Low Active - */ -#define BOARD_PANEL_TIMEING_PARA_HSPW_INDEX 0 -#define BOARD_PANEL_TIMEING_PARA_HBP_INDEX 1 -#define BOARD_PANEL_TIMEING_PARA_HFP_INDEX 2 -#define BOARD_PANEL_TIMEING_PARA_VSPW_INDEX 3 -#define BOARD_PANEL_TIMEING_PARA_VBP_INDEX 4 -#define BOARD_PANEL_TIMEING_PARA_VFP_INDEX 5 -#define BOARD_PANEL_TIMEING_PARA_HSSP_INDEX 6 -#define BOARD_PANEL_TIMEING_PARA_VSSP_INDEX 7 -#define BOARD_PANEL_TIMEING_PARA_DESP_INDEX 8 -#define BOARD_PANEL_TIMEING_PARA_PDSP_INDEX 9 -#define BOARD_PANEL_TIMEING_PARA_PCSP_INDEX 10 - -#if defined(PANEL_TM070RDH13) - #ifndef BOARD_LCD_WIDTH -#define BOARD_LCD_WIDTH 800 +#define BOARD_LCD_WIDTH PANEL_SIZE_WIDTH #endif #ifndef BOARD_LCD_HEIGHT -#define BOARD_LCD_HEIGHT 480 -#endif -#ifndef BOARD_PANEL_TIMING_PARA -#define BOARD_PANEL_TIMING_PARA {10, 46, 50, 3, 23, 10, 0, 0, 0, 0, 0} -#endif - -#else - -#ifndef BOARD_LCD_WIDTH -#define BOARD_LCD_WIDTH 800 -#endif -#ifndef BOARD_LCD_HEIGHT -#define BOARD_LCD_HEIGHT 480 -#endif -#ifndef BOARD_PANEL_TIMING_PARA -#define BOARD_PANEL_TIMING_PARA {10, 46, 50, 3, 23, 10, 0, 0, 0, 0, 0} -#endif - +#define BOARD_LCD_HEIGHT PANEL_SIZE_HEIGHT #endif /* pdma section */ #define BOARD_PDMA_BASE HPM_PDMA /* i2s section */ -#define BOARD_APP_I2S_BASE HPM_I2S0 -#define BOARD_APP_I2S_DATA_LINE (2U) -#define BOARD_APP_I2S_CLK_NAME clock_i2s0 -#define BOARD_APP_AUDIO_CLK_SRC clock_source_pll3_clk0 -#define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll3clk0 +#define BOARD_APP_I2S_BASE HPM_I2S0 +#define BOARD_APP_I2S_DATA_LINE (2U) +#define BOARD_APP_I2S_CLK_NAME clock_i2s0 +#define BOARD_APP_I2S_TX_DMA_REQ HPM_DMA_SRC_I2S0_TX +#define BOARD_APP_I2S_IRQ IRQn_I2S0 +#define BOARD_APP_AUDIO_CLK_SRC clock_source_pll3_clk0 +#define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll3clk0 +#define BOARD_PDM_SINGLE_CHANNEL_MASK (1U) +#define BOARD_PDM_DUAL_CHANNEL_MASK (0x11U) /* enet section */ -#define BOARD_ENET0_RST_GPIO HPM_GPIO0 -#define BOARD_ENET0_RST_GPIO_INDEX GPIO_DO_GPIOF -#define BOARD_ENET0_RST_GPIO_PIN (0U) +#define BOARD_ENET_COUNT (2U) +#define BOARD_ENET_PPS HPM_ENET0 +#define BOARD_ENET_PPS_IDX enet_pps_0 +#define BOARD_ENET_PPS_PTP_CLOCK clock_ptp0 + +#define BOARD_ENET_RGMII_PHY_ITF enet_inf_rgmii +#define BOARD_ENET_RGMII_RST_GPIO HPM_GPIO0 +#define BOARD_ENET_RGMII_RST_GPIO_INDEX GPIO_DO_GPIOF +#define BOARD_ENET_RGMII_RST_GPIO_PIN (0U) +#define BOARD_ENET_RGMII HPM_ENET0 +#define BOARD_ENET_RGMII_TX_DLY (0U) +#define BOARD_ENET_RGMII_RX_DLY (7U) +#define BOARD_ENET_RGMII_PTP_CLOCK (clock_ptp0) +#define BOARD_ENET_RGMII_PPS0_PINOUT (1) + +#define BOARD_ENET_RMII_PHY_ITF enet_inf_rmii +#define BOARD_ENET_RMII_RST_GPIO HPM_GPIO0 +#define BOARD_ENET_RMII_RST_GPIO_INDEX GPIO_DO_GPIOE +#define BOARD_ENET_RMII_RST_GPIO_PIN (26U) +#define BOARD_ENET_RMII HPM_ENET1 +#define BOARD_ENET_RMII_INT_REF_CLK (1U) +#define BOARD_ENET_RMII_PTP_CLOCK (clock_ptp1) +#define BOARD_ENET_RMII_PPS0_PINOUT (0) + #define BOARD_ENET0_INF (1U) /* 0: RMII, 1: RGMII */ #define BOARD_ENET0_INT_REF_CLK (0U) #define BOARD_ENET0_PHY_RST_TIME (30) @@ -301,57 +331,88 @@ #define BOARD_ENET1_PTP_CLOCK (clock_ptp1) #endif + /* ADC section */ -#define BOARD_APP_ADC12_NAME "ADC0" -#define BOARD_APP_ADC12_BASE HPM_ADC0 -#define BOARD_APP_ADC12_IRQn IRQn_ADC0 -#define BOARD_APP_ADC12_CH (11U) - -#define BOARD_APP_ADC16_NAME "ADC3" -#define BOARD_APP_ADC16_BASE HPM_ADC3 -#define BOARD_APP_ADC16_IRQn IRQn_ADC3 -#define BOARD_APP_ADC16_CH (2U) - -#define BOARD_APP_ADC_SEQ_DMA_SIZE_IN_4BYTES (1024U) -#define BOARD_APP_ADC_PMT_DMA_SIZE_IN_4BYTES (192U) -#define BOARD_APP_ADC_PREEMPT_TRIG_LEN (1U) -#define BOARD_APP_ADC_SINGLE_CONV_CNT (6) -#define BOARD_APP_ADC_TRIG_PWMT0 HPM_PWM0 -#define BOARD_APP_ADC_TRIG_PWMT1 HPM_PWM1 -#define BOARD_APP_ADC_TRIG_TRGM0 HPM_TRGM0 -#define BOARD_APP_ADC_TRIG_TRGM1 HPM_TRGM1 -#define BOARD_APP_ADC_TRIG_PWM_SYNC HPM_SYNT +#define BOARD_APP_ADC12_NAME "ADC0" +#define BOARD_APP_ADC12_BASE HPM_ADC0 +#define BOARD_APP_ADC12_IRQn IRQn_ADC0 +#define BOARD_APP_ADC12_CH_1 (11U) +#define BOARD_APP_ADC12_CLK_NAME (clock_adc0) + +#define BOARD_APP_ADC16_NAME "ADC3" +#define BOARD_APP_ADC16_BASE HPM_ADC3 +#define BOARD_APP_ADC16_IRQn IRQn_ADC3 +#define BOARD_APP_ADC16_CH_1 (2U) +#define BOARD_APP_ADC16_CLK_NAME (clock_adc3) + +#define BOARD_APP_ADC12_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC12_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC12_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_APP_ADC12_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI +#define BOARD_APP_ADC12_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A + +#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC3_STRGI +#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A + +#define BOARD_APP_ADC12_PMT_TRIG_CH ADC12_CONFIG_TRG0A +#define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A /* CAN section */ -#define BOARD_APP_CAN_BASE HPM_CAN0 -#define BOARD_APP_CAN_IRQn IRQn_CAN0 - +#define BOARD_APP_CAN_BASE HPM_CAN0 +#define BOARD_APP_CAN_IRQn IRQn_CAN0 /* * timer for board delay */ -#define BOARD_DELAY_TIMER (HPM_GPTMR7) -#define BOARD_DELAY_TIMER_CH 0 +#define BOARD_DELAY_TIMER (HPM_GPTMR7) +#define BOARD_DELAY_TIMER_CH 0 #define BOARD_DELAY_TIMER_CLK_NAME (clock_gptmr7) -#define BOARD_CALLBACK_TIMER (HPM_GPTMR7) -#define BOARD_CALLBACK_TIMER_CH 1 -#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR7 +#define BOARD_CALLBACK_TIMER (HPM_GPTMR7) +#define BOARD_CALLBACK_TIMER_CH 1 +#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR7 #define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr7) /* SDXC section */ -#define BOARD_APP_SDCARD_SDXC_BASE (HPM_SDXC1) -#define BOARD_APP_SDCARD_SUPPORT_1V8 (0) -#define BOARD_APP_SDCARD_SUPPORT_CARD_DETECTION (1) -#define BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO (1) -#if BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO +#define BOARD_APP_SDCARD_SDXC_BASE (HPM_SDXC1) +#define BOARD_APP_SDCARD_SUPPORT_3V3 (1) +#define BOARD_APP_SDCARD_SUPPORT_1V8 (0) +#define BOARD_APP_SDCARD_SUPPORT_4BIT (1) +#define BOARD_APP_SDCARD_SUPPORT_CARD_DETECTION (1) +#define BOARD_APP_SDCARD_SUPPORT_POWER_SWITCH (1) +#define BOARD_APP_SDCARD_POWER_SWITCH_USING_GPIO (1) +#define BOARD_APP_SDCARD_SUPPORT_VOLTAGE_SWITCH (0) +#define BOARD_APP_SDCARD_SUPPORT_CARD_DETECTION (1) +#define BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO (1) +#if defined(BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO) && (BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO == 1) +#define BOARD_APP_SDCARD_CARD_DETECTION_PIN IOC_PAD_PD15 +#define BOARD_APP_SDCARD_CARD_DETECTION_PIN_POL 1 /* PIN value 0 means card is inserted */ #define BOARD_APP_SDCARD_CARD_DETECTION_GPIO HPM_GPIO0 #define BOARD_APP_SDCARD_CARD_DETECTION_GPIO_INDEX GPIO_DI_GPIOD #define BOARD_APP_SDCARD_CARD_DETECTION_PIN_INDEX 15 #endif +#if defined(BOARD_APP_SDCARD_POWER_SWITCH_USING_GPIO) && (BOARD_APP_SDCARD_POWER_SWITCH_USING_GPIO == 1) #define BOARD_APP_SDCARD_POWER_EN_GPIO_BASE HPM_GPIO0 #define BOARD_APP_SDCARD_POWER_EN_GPIO_INDEX GPIO_DO_GPIOC #define BOARD_APP_SDCARD_POWER_EN_GPIO_PIN 20 +#define BOARD_APP_SDCARD_POWER_SWITCH_PIN IOC_PAD_PC20 +#define BOARD_APP_SDCARD_POWER_SWITCH_PIN_POL 0 /* PIN value 1 means power is supplied */ +#endif + +#define BOARD_APP_EMMC_SDXC_BASE (HPM_SDXC1) +#define BOARD_APP_EMMC_SUPPORT_3V3 (1) +#define BOARD_APP_EMMC_SUPPORT_1V8 (0) +#define BOARD_APP_EMMC_SUPPORT_4BIT (1) +#define BOARD_APP_EMMC_SUPPORT_POWER_SWITCH (1) +#define BOARD_APP_EMMC_POWER_SWITCH_USING_GPIO (1) +#define BOARD_APP_EMMC_HOST_USING_IRQ (0) +#if defined(BOARD_APP_EMMC_POWER_SWITCH_USING_GPIO) && (BOARD_APP_EMMC_POWER_SWITCH_USING_GPIO == 1) +#define BOARD_APP_EMMC_POWER_SWITCH_PIN IOC_PAD_PC20 +#define BOARD_APP_EMMC_POWER_SWITCH_PIN_POL 0 /* PIN value 1 means power is supplied */ +#endif /* USB section */ #define BOARD_USB0_ID_PORT (HPM_GPIO0) @@ -373,113 +434,119 @@ /*BLDC pwm*/ /*PWM define*/ -#define BOARD_BLDCPWM HPM_PWM2 -#define BOARD_BLDC_UH_PWM_OUTPIN (0U) -#define BOARD_BLDC_UL_PWM_OUTPIN (1U) -#define BOARD_BLDC_VH_PWM_OUTPIN (2U) -#define BOARD_BLDC_VL_PWM_OUTPIN (3U) -#define BOARD_BLDC_WH_PWM_OUTPIN (4U) -#define BOARD_BLDC_WL_PWM_OUTPIN (5U) -#define BOARD_BLDCPWM_TRGM HPM_TRGM2 -#define BOARD_BLDCAPP_PWM_IRQ IRQn_PWM2 -#define BOARD_BLDCPWM_CMP_INDEX_0 (0U) -#define BOARD_BLDCPWM_CMP_INDEX_1 (1U) -#define BOARD_BLDCPWM_CMP_INDEX_2 (2U) -#define BOARD_BLDCPWM_CMP_INDEX_3 (3U) -#define BOARD_BLDCPWM_CMP_INDEX_4 (4U) -#define BOARD_BLDCPWM_CMP_INDEX_5 (5U) +#define BOARD_BLDCPWM HPM_PWM2 +#define BOARD_BLDC_UH_PWM_OUTPIN (0U) +#define BOARD_BLDC_UL_PWM_OUTPIN (1U) +#define BOARD_BLDC_VH_PWM_OUTPIN (2U) +#define BOARD_BLDC_VL_PWM_OUTPIN (3U) +#define BOARD_BLDC_WH_PWM_OUTPIN (4U) +#define BOARD_BLDC_WL_PWM_OUTPIN (5U) +#define BOARD_BLDCPWM_TRGM HPM_TRGM2 +#define BOARD_BLDCAPP_PWM_IRQ IRQn_PWM2 +#define BOARD_BLDCPWM_CMP_INDEX_0 (0U) +#define BOARD_BLDCPWM_CMP_INDEX_1 (1U) +#define BOARD_BLDCPWM_CMP_INDEX_2 (2U) +#define BOARD_BLDCPWM_CMP_INDEX_3 (3U) +#define BOARD_BLDCPWM_CMP_INDEX_4 (4U) +#define BOARD_BLDCPWM_CMP_INDEX_5 (5U) +#define BOARD_BLDCPWM_CMP_INDEX_6 (6U) +#define BOARD_BLDCPWM_CMP_INDEX_7 (7U) +#define BOARD_BLDCPWM_CMP_TRIG_CMP (20U) /*HALL define*/ -#define BOARD_BLDC_HALL_BASE HPM_HALL2 -#define BOARD_BLDC_HALL_TRGM HPM_TRGM2 -#define BOARD_BLDC_HALL_IRQ IRQn_HALL2 -#define BOARD_BLDC_HALL_TRGM_HALL_U_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P6 -#define BOARD_BLDC_HALL_TRGM_HALL_V_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P7 -#define BOARD_BLDC_HALL_TRGM_HALL_W_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P8 -#define BOARD_BLDC_HALL_MOTOR_PHASE_COUNT_PER_REV (1000U) - - +#define BOARD_BLDC_HALL_BASE HPM_HALL2 +#define BOARD_BLDC_HALL_TRGM HPM_TRGM2 +#define BOARD_BLDC_HALL_IRQ IRQn_HALL2 +#define BOARD_BLDC_HALL_TRGM_HALL_U_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P6 +#define BOARD_BLDC_HALL_TRGM_HALL_V_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P7 +#define BOARD_BLDC_HALL_TRGM_HALL_W_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P8 +#define BOARD_BLDC_HALL_MOTOR_PHASE_COUNT_PER_REV (1000U) /*QEI*/ -#define BOARD_BLDC_QEI_BASE HPM_QEI2 -#define BOARD_BLDC_QEI_IRQ IRQn_QEI2 -#define BOARD_BLDC_QEI_TRGM HPM_TRGM2 -#define BOARD_BLDC_QEI_TRGM_QEI_A_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P9 -#define BOARD_BLDC_QEI_TRGM_QEI_B_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P10 -#define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV (16U) -#define BOARD_BLDC_QEI_CLOCK_SOURCE clock_mot2 -#define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV (4000U) +#define BOARD_BLDC_QEI_BASE HPM_QEI2 +#define BOARD_BLDC_QEI_IRQ IRQn_QEI2 +#define BOARD_BLDC_QEI_TRGM HPM_TRGM2 +#define BOARD_BLDC_QEI_TRGM_QEI_A_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P9 +#define BOARD_BLDC_QEI_TRGM_QEI_B_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P10 +#define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV (16U) +#define BOARD_BLDC_QEI_CLOCK_SOURCE clock_mot2 +#define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV (4000U) + +/*HFI define*/ +#define MOTOR0_HFI_SPD (0.5) +#define MOTOR0_HFI_KP (40) /*Timer define*/ -#define BOARD_TMR_1MS HPM_GPTMR2 -#define BOARD_TMR_1MS_CH 0 -#define BOARD_TMR_1MS_CMP 0 -#define BOARD_TMR_1MS_IRQ IRQn_GPTMR2 -#define BOARD_TMR_1MS_RELOAD (100000U) +#define BOARD_TMR_1MS HPM_GPTMR2 +#define BOARD_TMR_1MS_CH 0 +#define BOARD_TMR_1MS_CMP 0 +#define BOARD_TMR_1MS_IRQ IRQn_GPTMR2 +#define BOARD_TMR_1MS_RELOAD (100000U) -#define BOARD_BLDC_TMR_1MS BOARD_TMR_1MS -#define BOARD_BLDC_TMR_CH BOARD_TMR_1MS_CH -#define BOARD_BLDC_TMR_CMP BOARD_TMR_1MS_CMP -#define BOARD_BLDC_TMR_IRQ BOARD_TMR_1MS_IRQ -#define BOARD_BLDC_TMR_RELOAD BOARD_TMR_1MS_RELOAD -#define BOARD_BLDC_ADC_TRG ADC12_CONFIG_TRG2A +#define BOARD_BLDC_TMR_1MS BOARD_TMR_1MS +#define BOARD_BLDC_TMR_CH BOARD_TMR_1MS_CH +#define BOARD_BLDC_TMR_CMP BOARD_TMR_1MS_CMP +#define BOARD_BLDC_TMR_IRQ BOARD_TMR_1MS_IRQ +#define BOARD_BLDC_TMR_RELOAD BOARD_TMR_1MS_RELOAD /*adc*/ -#define BOARD_BLDC_ADC_MODULE ADCX_MODULE_ADC12 -#define BOARD_BLDC_ADC_U_BASE HPM_ADC0 -#define BOARD_BLDC_ADC_V_BASE HPM_ADC1 -#define BOARD_BLDC_ADC_W_BASE HPM_ADC2 -#define BOARD_BLDC_ADC_TRIG_FLAG adc12_event_trig_complete - -#define BOARD_BLDC_ADC_CH_U (7U) -#define BOARD_BLDC_ADC_CH_V (10U) -#define BOARD_BLDC_ADC_CH_W (11U) -#define BOARD_BLDC_ADC_IRQn IRQn_ADC0 -#define BOARD_BLDC_ADC_SEQ_DMA_SIZE_IN_4BYTES (40U) +#define BOARD_BLDC_ADC_MODULE ADCX_MODULE_ADC12 +#define BOARD_BLDC_ADC_U_BASE HPM_ADC0 +#define BOARD_BLDC_ADC_V_BASE HPM_ADC1 +#define BOARD_BLDC_ADC_W_BASE HPM_ADC2 +#define BOARD_BLDC_ADC_TRIG_FLAG adc12_event_trig_complete + +#define BOARD_BLDC_ADC_CH_U (7U) +#define BOARD_BLDC_ADC_CH_V (10U) +#define BOARD_BLDC_ADC_CH_W (11U) +#define BOARD_BLDC_ADC_IRQn IRQn_ADC0 +#define BOARD_BLDC_ADC_PMT_DMA_SIZE_IN_4BYTES (ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES) #define BOARD_BLDC_ADC_TRG ADC12_CONFIG_TRG2A -#define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) -#define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U) -#define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM2_INPUT_SRC_PWM2_CH8REF -#define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A -#define BOARD_BLDC_ADC_IRQn IRQn_ADC0 +#define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) +#define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U) +#define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM2_INPUT_SRC_PWM2_CH8REF +#define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A +#define BOARD_BLDC_ADC_IRQn IRQn_ADC0 /* APP PWM */ -#define BOARD_APP_PWM HPM_PWM2 -#define BOARD_APP_PWM_CLOCK_NAME clock_mot2 -#define BOARD_APP_PWM_OUT1 0 -#define BOARD_APP_PWM_OUT2 1 -#define BOARD_APP_TRGM HPM_TRGM2 +#define BOARD_APP_PWM HPM_PWM2 +#define BOARD_APP_PWM_CLOCK_NAME clock_mot2 +#define BOARD_APP_PWM_OUT1 0 +#define BOARD_APP_PWM_OUT2 1 +#define BOARD_APP_TRGM HPM_TRGM2 +#define BOARD_APP_PWM_IRQ IRQn_PWM2 +#define BOARD_APP_TRGM_PWM_OUTPUT TRGM_TRGOCFG_PWM_SYNCI /* RGB LED Section */ -#define BOARD_RED_PWM_IRQ IRQn_PWM1 -#define BOARD_RED_PWM HPM_PWM1 -#define BOARD_RED_PWM_OUT 8 -#define BOARD_RED_PWM_CMP 8 +#define BOARD_RED_PWM_IRQ IRQn_PWM1 +#define BOARD_RED_PWM HPM_PWM1 +#define BOARD_RED_PWM_OUT 8 +#define BOARD_RED_PWM_CMP 8 #define BOARD_RED_PWM_CMP_INITIAL_ZERO true -#define BOARD_RED_PWM_CLOCK_NAME clock_mot1 +#define BOARD_RED_PWM_CLOCK_NAME clock_mot1 -#define BOARD_GREEN_PWM_IRQ IRQn_PWM0 -#define BOARD_GREEN_PWM HPM_PWM0 -#define BOARD_GREEN_PWM_OUT 8 -#define BOARD_GREEN_PWM_CMP 8 +#define BOARD_GREEN_PWM_IRQ IRQn_PWM0 +#define BOARD_GREEN_PWM HPM_PWM0 +#define BOARD_GREEN_PWM_OUT 8 +#define BOARD_GREEN_PWM_CMP 8 #define BOARD_GREEN_PWM_CMP_INITIAL_ZERO true -#define BOARD_GREEN_PWM_CLOCK_NAME clock_mot0 +#define BOARD_GREEN_PWM_CLOCK_NAME clock_mot0 -#define BOARD_BLUE_PWM_IRQ IRQn_PWM1 -#define BOARD_BLUE_PWM HPM_PWM1 -#define BOARD_BLUE_PWM_OUT 9 -#define BOARD_BLUE_PWM_CMP 9 +#define BOARD_BLUE_PWM_IRQ IRQn_PWM1 +#define BOARD_BLUE_PWM HPM_PWM1 +#define BOARD_BLUE_PWM_OUT 9 +#define BOARD_BLUE_PWM_CMP 9 #define BOARD_BLUE_PWM_CMP_INITIAL_ZERO true -#define BOARD_BLUE_PWM_CLOCK_NAME clock_mot1 +#define BOARD_BLUE_PWM_CLOCK_NAME clock_mot1 -#define BOARD_RGB_RED 0 +#define BOARD_RGB_RED 0 #define BOARD_RGB_GREEN (BOARD_RGB_RED + 1) #define BOARD_RGB_BLUE (BOARD_RGB_RED + 2) -#define BOARD_CPU_FREQ (816000000UL) +#define BOARD_CPU_FREQ (648000000UL) #define BOARD_APP_DISPLAY_CLOCK clock_display @@ -490,6 +557,22 @@ #define BOARD_SHOW_BANNER 1 #endif +/* FreeRTOS Definitions */ +#define BOARD_FREERTOS_TIMER HPM_GPTMR6 +#define BOARD_FREERTOS_TIMER_CHANNEL 1 +#define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR6 +#define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr6 + +/* Threadx Definitions */ +#define BOARD_THREADX_TIMER HPM_GPTMR6 +#define BOARD_THREADX_TIMER_CHANNEL 1 +#define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR6 +#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr6 + +/* Tamper Section */ +#define BOARD_TAMP_ACTIVE_CH 8 +#define BOARD_TAMP_LOW_LEVEL_CH 10 + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ @@ -499,9 +582,12 @@ typedef void (*board_timer_cb)(void); void board_init(void); void board_init_console(void); +void board_init_core1(void); + void board_init_uart(UART_Type *ptr); void board_init_i2c(I2C_Type *ptr); void board_init_lcd(void); +void board_lcd_backlight(bool is_on); void board_panel_para_to_lcdc(lcdc_config_t *config); void board_init_can(CAN_Type *ptr); @@ -510,6 +596,8 @@ uint32_t board_init_femc_clock(void); void board_init_sdram_pins(void); void board_init_gpio_pins(void); void board_init_spi_pins(SPI_Type *ptr); +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); +void board_write_spi_cs(uint32_t pin, uint8_t state); void board_init_led_pins(void); /* cap touch */ @@ -522,7 +610,6 @@ void board_fpga_power_enable(void); void board_init_cam_pins(void); void board_write_cam_rst(uint8_t state); - /* Initialize SoC overall clocks */ void board_init_clock(void); @@ -537,35 +624,52 @@ uint32_t board_init_lcd_clock(void); uint32_t board_init_spi_clock(SPI_Type *ptr); -uint32_t board_init_adc12_clock(ADC12_Type *ptr); +uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb); -uint32_t board_init_adc16_clock(ADC16_Type *ptr); +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb); uint32_t board_init_can_clock(CAN_Type *ptr); uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); +hpm_stat_t board_set_audio_pll_clock(uint32_t freq); + +void board_init_i2s_pins(I2S_Type *ptr); uint32_t board_init_i2s_clock(I2S_Type *ptr); +uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate); uint32_t board_init_pdm_clock(void); uint32_t board_init_dao_clock(void); -void board_init_sd_pins(SDXC_Type *ptr); -uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq); +uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inverse); void board_sd_switch_pins_to_1v8(SDXC_Type *ptr); void board_sd_power_switch(SDXC_Type *ptr, bool on_off); bool board_sd_detect_card(SDXC_Type *ptr); +void board_init_dao_pins(void); + void board_init_adc12_pins(void); void board_init_adc16_pins(void); void board_init_usb_pins(void); void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); -uint8_t board_enet_get_dma_pbl(ENET_Type *ptr); -hpm_stat_t board_init_enet_pins(ENET_Type *ptr); +void board_init_enet_pps_pins(ENET_Type *ptr); +uint8_t board_get_enet_dma_pbl(ENET_Type *ptr); hpm_stat_t board_reset_enet_phy(ENET_Type *ptr); hpm_stat_t board_init_enet_pins(ENET_Type *ptr); hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal); - +hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr); hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr); +hpm_stat_t board_enable_enet_irq(ENET_Type *ptr); +hpm_stat_t board_disable_enet_irq(ENET_Type *ptr); + +#if defined(ENET_MULTIPLE_PORT) && ENET_MULTIPLE_PORT +hpm_stat_t board_init_multiple_enet_pins(void); +hpm_stat_t board_init_multiple_enet_clock(void); +hpm_stat_t board_reset_multiple_enet_phy(void); +hpm_stat_t board_init_enet_phy(ENET_Type *ptr); +ENET_Type *board_get_enet_base(uint8_t idx); +uint8_t board_get_enet_phy_itf(uint8_t idx); +void board_get_enet_phy_status(uint8_t idx, void *status); +#endif /* * @brief Initialize PMP and PMA for but not limited to the following purposes: @@ -574,6 +678,7 @@ hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr); void board_init_pmp(void); void board_delay_ms(uint32_t ms); +void board_delay_us(uint32_t us); void board_timer_create(uint32_t ms, board_timer_cb cb); @@ -586,6 +691,15 @@ void board_disable_output_rgb_led(uint8_t color); */ void board_ungate_mchtmr_at_lp_mode(void); +/* + * Get PWM output level of onboard LED + */ +uint8_t board_get_led_pwm_off_level(void); + +/* + * Get GPIO pin level of onboard LED + */ +uint8_t board_get_led_gpio_off_level(void); #if defined(__cplusplus) } diff --git a/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/boards/hpm6750evk.cfg b/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/boards/hpm6750evk.cfg deleted file mode 100644 index 9f15d4c2ec1..00000000000 --- a/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/boards/hpm6750evk.cfg +++ /dev/null @@ -1,345 +0,0 @@ -# Copyright 2021 hpmicro -# SPDX-License-Identifier: BSD-3-Clause - -# openocd flash driver argument: -# - option0: -# [31:28] Flash probe type -# 0 - SFDP SDR / 1 - SFDP DDR -# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) -# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V -# 6 - OctaBus DDR (SPI -> OPI DDR) -# 8 - Xccela DDR (SPI -> OPI DDR) -# 10 - EcoXiP DDR (SPI -> OPI DDR) -# [27:24] Command Pads after Power-on Reset -# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI -# [23:20] Command Pads after Configuring FLASH -# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI -# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) -# 0 - Not needed -# 1 - QE bit is at bit 6 in Status Register 1 -# 2 - QE bit is at bit1 in Status Register 2 -# 3 - QE bit is at bit7 in Status Register 2 -# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 -# [15:8] Dummy cycles -# 0 - Auto-probed / detected / default value -# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet -# [7:4] Misc. -# 0 - Not used -# 1 - SPI mode -# 2 - Internal loopback -# 3 - External DQS -# [3:0] Frequency option -# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz -# - option1: -# [31:20] Reserved -# [19:16] IO voltage -# 0 - 3V / 1 - 1.8V -# [15:12] Pin group -# 0 - 1st group / 1 - 2nd group -# [11:8] Connection selection -# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) -# [7:0] Drive Strength -# 0 - Default value - -# xpi0 configs -# - flash driver: hpm_xpi -# - flash ctrl index: 0xF3040000 -# - base address: 0x80000000 -# - flash size: 0x2000000 -# - flash option0: 0x7 -flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3040000 0x7 - -proc init_clock {} { - $::_TARGET0 riscv dmi_write 0x39 0xF4002000 - $::_TARGET0 riscv dmi_write 0x3C 0x1 - - $::_TARGET0 riscv dmi_write 0x39 0xF4002000 - $::_TARGET0 riscv dmi_write 0x3C 0x2 - - $::_TARGET0 riscv dmi_write 0x39 0xF4000800 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000810 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000820 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000830 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - echo "clocks has been enabled!" -} - -proc init_sdram { } { -# configure dram frequency -# 133Mhz pll1_clk0: 266Mhz divide by 2 - #$::_TARGET0 riscv dmi_write 0x39 0xF4001820 - $::_TARGET0 riscv dmi_write 0x3C 0x201 -# 166Mhz pll2_clk0: 333Mhz divide by 2 - $::_TARGET0 riscv dmi_write 0x39 0xF4001820 - $::_TARGET0 riscv dmi_write 0x3C 0x401 - # PC01 - $::_TARGET0 riscv dmi_write 0x39 0xF4040208 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC00 - $::_TARGET0 riscv dmi_write 0x39 0xF4040200 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PB31 - $::_TARGET0 riscv dmi_write 0x39 0xF40401F8 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PB30 - $::_TARGET0 riscv dmi_write 0x39 0xF40401F0 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PB29 - $::_TARGET0 riscv dmi_write 0x39 0xF40401E8 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PB28 - $::_TARGET0 riscv dmi_write 0x39 0xF40401E0 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PB27 - $::_TARGET0 riscv dmi_write 0x39 0xF40401D8 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PB26 - $::_TARGET0 riscv dmi_write 0x39 0xF40401D0 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PB25 - $::_TARGET0 riscv dmi_write 0x39 0xF40401C8 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PB24 - $::_TARGET0 riscv dmi_write 0x39 0xF40401C0 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PB23 - $::_TARGET0 riscv dmi_write 0x39 0xF40401B8 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PB22 - $::_TARGET0 riscv dmi_write 0x39 0xF40401B0 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PB21 - $::_TARGET0 riscv dmi_write 0x39 0xF40401A8 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PB20 - $::_TARGET0 riscv dmi_write 0x39 0xF40401A0 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PB19 - $::_TARGET0 riscv dmi_write 0x39 0xF4040198 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PB18 - $::_TARGET0 riscv dmi_write 0x39 0xF4040190 - $::_TARGET0 riscv dmi_write 0x3C 0xC - - # PD13 - $::_TARGET0 riscv dmi_write 0x39 0xF4040368 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD12 - $::_TARGET0 riscv dmi_write 0x39 0xF4040360 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD10 - $::_TARGET0 riscv dmi_write 0x39 0xF4040350 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD09 - $::_TARGET0 riscv dmi_write 0x39 0xF4040348 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD08 - $::_TARGET0 riscv dmi_write 0x39 0xF4040340 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD07 - $::_TARGET0 riscv dmi_write 0x39 0xF4040338 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD06 - $::_TARGET0 riscv dmi_write 0x39 0xF4040330 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD05 - $::_TARGET0 riscv dmi_write 0x39 0xF4040328 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD04 - $::_TARGET0 riscv dmi_write 0x39 0xF4040320 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD03 - $::_TARGET0 riscv dmi_write 0x39 0xF4040318 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD02 - $::_TARGET0 riscv dmi_write 0x39 0xF4040310 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD01 - $::_TARGET0 riscv dmi_write 0x39 0xF4040308 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD00 - $::_TARGET0 riscv dmi_write 0x39 0xF4040300 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC29 - $::_TARGET0 riscv dmi_write 0x39 0xF40402E8 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC28 - $::_TARGET0 riscv dmi_write 0x39 0xF40402E0 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC27 - $::_TARGET0 riscv dmi_write 0x39 0xF40402D8 - $::_TARGET0 riscv dmi_write 0x3C 0xC - - # PC22 - $::_TARGET0 riscv dmi_write 0x39 0xF40402B0 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC21 - $::_TARGET0 riscv dmi_write 0x39 0xF40402A8 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC17 - $::_TARGET0 riscv dmi_write 0x39 0xF4040288 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC15 - $::_TARGET0 riscv dmi_write 0x39 0xF4040278 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC12 - $::_TARGET0 riscv dmi_write 0x39 0xF4040260 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC11 - $::_TARGET0 riscv dmi_write 0x39 0xF4040258 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC10 - $::_TARGET0 riscv dmi_write 0x39 0xF4040250 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC09 - $::_TARGET0 riscv dmi_write 0x39 0xF4040248 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC08 - $::_TARGET0 riscv dmi_write 0x39 0xF4040240 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC07 - $::_TARGET0 riscv dmi_write 0x39 0xF4040238 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC06 - $::_TARGET0 riscv dmi_write 0x39 0xF4040230 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC05 - $::_TARGET0 riscv dmi_write 0x39 0xF4040228 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC04 - $::_TARGET0 riscv dmi_write 0x39 0xF4040220 - $::_TARGET0 riscv dmi_write 0x3C 0xC - - # PC14 - $::_TARGET0 riscv dmi_write 0x39 0xF4040270 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC13 - $::_TARGET0 riscv dmi_write 0x39 0xF4040268 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC16 - # $::_TARGET0 riscv dmi_write 0x39 0xF4040280 - $::_TARGET0 riscv dmi_write 0x3C 0x1000C - # PC26 - $::_TARGET0 riscv dmi_write 0x39 0xF40402D0 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC25 - $::_TARGET0 riscv dmi_write 0x39 0xF40402C8 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC19 - $::_TARGET0 riscv dmi_write 0x39 0xF4040298 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC18 - $::_TARGET0 riscv dmi_write 0x39 0xF4040290 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC23 - $::_TARGET0 riscv dmi_write 0x39 0xF40402B8 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC24 - $::_TARGET0 riscv dmi_write 0x39 0xF40402C0 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC30 - $::_TARGET0 riscv dmi_write 0x39 0xF40402F0 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC31 - $::_TARGET0 riscv dmi_write 0x39 0xF40402F8 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC02 - $::_TARGET0 riscv dmi_write 0x39 0xF4040210 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC03 - $::_TARGET0 riscv dmi_write 0x39 0xF4040218 - $::_TARGET0 riscv dmi_write 0x3C 0xC - - # dramc configuration - $::_TARGET0 riscv dmi_write 0x39 0xF3050000 - $::_TARGET0 riscv dmi_write 0x3C 0x1 - sleep 10 - $::_TARGET0 riscv dmi_write 0x39 0xF3050000 - $::_TARGET0 riscv dmi_write 0x3C 0x2 - $::_TARGET0 riscv dmi_write 0x39 0xF3050008 - $::_TARGET0 riscv dmi_write 0x3C 0x30524 - $::_TARGET0 riscv dmi_write 0x39 0xF305000C - $::_TARGET0 riscv dmi_write 0x3C 0x6030524 - $::_TARGET0 riscv dmi_write 0x39 0xF3050000 - $::_TARGET0 riscv dmi_write 0x3C 0x10000000 - - $::_TARGET0 riscv dmi_write 0x39 0xF3050010 - $::_TARGET0 riscv dmi_write 0x3C 0x4000001b - $::_TARGET0 riscv dmi_write 0x39 0xF3050014 - $::_TARGET0 riscv dmi_write 0x3C 0 - $::_TARGET0 riscv dmi_write 0x39 0xF3050040 - $::_TARGET0 riscv dmi_write 0x3C 0xf32 - - # 133Mhz configuration - #$::_TARGET0 riscv dmi_write 0x39 0xF3050044 - $::_TARGET0 riscv dmi_write 0x3C 0x884e22 - # 166Mhz configuration - $::_TARGET0 riscv dmi_write 0x39 0xF3050044 - $::_TARGET0 riscv dmi_write 0x3C 0x884e33 - - $::_TARGET0 riscv dmi_write 0x39 0xF3050048 - $::_TARGET0 riscv dmi_write 0x3C 0x1020d0d - $::_TARGET0 riscv dmi_write 0x39 0xF3050048 - $::_TARGET0 riscv dmi_write 0x3C 0x1020d0d - $::_TARGET0 riscv dmi_write 0x39 0xF305004C - $::_TARGET0 riscv dmi_write 0x3C 0x2020300 - - # config delay cell - $::_TARGET0 riscv dmi_write 0x39 0xF3050150 - $::_TARGET0 riscv dmi_write 0x3C 0x3b - $::_TARGET0 riscv dmi_write 0x39 0xF3050150 - $::_TARGET0 riscv dmi_write 0x3C 0x203b - - $::_TARGET0 riscv dmi_write 0x39 0xF3050094 - $::_TARGET0 riscv dmi_write 0x3C 0 - $::_TARGET0 riscv dmi_write 0x39 0xF3050098 - $::_TARGET0 riscv dmi_write 0x3C 0 - - # precharge all - $::_TARGET0 riscv dmi_write 0x39 0xF3050090 - $::_TARGET0 riscv dmi_write 0x3C 0x40000000 - $::_TARGET0 riscv dmi_write 0x39 0xF305009C - $::_TARGET0 riscv dmi_write 0x3C 0xA55A000F - sleep 500 - $::_TARGET0 riscv dmi_write 0x39 0xF305003C - $::_TARGET0 riscv dmi_write 0x3C 0x3 - # auto refresh - $::_TARGET0 riscv dmi_write 0x39 0xF305009C - $::_TARGET0 riscv dmi_write 0x3C 0xA55A000C - sleep 500 - $::_TARGET0 riscv dmi_write 0x39 0xF305003C - $::_TARGET0 riscv dmi_write 0x3C 0x3 - $::_TARGET0 riscv dmi_write 0x39 0xF305009C - $::_TARGET0 riscv dmi_write 0x3C 0xA55A000C - sleep 500 - $::_TARGET0 riscv dmi_write 0x39 0xF305003C - $::_TARGET0 riscv dmi_write 0x3C 0x3 - - # set mode - $::_TARGET0 riscv dmi_write 0x39 0xF30500A0 - $::_TARGET0 riscv dmi_write 0x3C 0x33 - $::_TARGET0 riscv dmi_write 0x39 0xF305009C - $::_TARGET0 riscv dmi_write 0x3C 0xA55A000A - sleep 500 - $::_TARGET0 riscv dmi_write 0x39 0xF305003C - $::_TARGET0 riscv dmi_write 0x3C 0x3 - - $::_TARGET0 riscv dmi_write 0x39 0xF305004C - $::_TARGET0 riscv dmi_write 0x3C 0x2020301 - echo "SDRAM has been initialized" -} - -$_TARGET0 configure -event reset-init { - init_clock - init_sdram -} - -$_TARGET0 configure -event gdb-attach { - reset halt -} diff --git a/bsp/hpmicro/hpm6750evk2/board/eth_phy_port.h b/bsp/hpmicro/hpm6750evk2/board/eth_phy_port.h deleted file mode 100644 index cde420add9f..00000000000 --- a/bsp/hpmicro/hpm6750evk2/board/eth_phy_port.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - * Copyright (c) 2023 hpmicro - * - * SPDX-License-Identifier: BSD-3-Clause - * -*/ - -#ifndef ETH_PHY_PORT_H -#define ETH_PHY_PORT_H - -#include "hpm_ioc_regs.h" -#include - -#ifndef PHY_AUTO_NEGO -#define PHY_AUTO_NEGO (1U) -#endif - -#ifndef PHY_MDIO_CSR_CLK_FREQ -#define PHY_MDIO_CSR_CLK_FREQ (200000000U) -#endif - -enum phy_link_status -{ - PHY_LINK_DOWN = 0U, - PHY_LINK_UP -}; - -typedef struct { - rt_uint32_t phy_speed; - rt_uint32_t phy_duplex; -} phy_info_t; - -typedef struct { - rt_uint32_t phy_link; - rt_phy_t phy; - phy_info_t phy_info; -} phy_device_t; - -#ifdef BSP_USING_ETH0 - - #define RGMII (1U) - - /* RTL8211 name and ID */ - #define PHY_NAME ("RTL8211") - #define PHY_ID1 (0x001CU) - #define PHY_ID2 (0x32U) - - /* PHY_RTL8211 basic control register */ - #define PHY_BASIC_CONTROL_REG (0x00U) - #define PHY_RESET_MASK (1U << 15) - #define PHY_AUTO_NEGOTIATION_MASK (1U << 12) - - /* PHY_RTL8211 basic status register */ - #define PHY_BASIC_STATUS_REG (0x01U) - #define PHY_LINKED_STATUS_MASK (1U << 2) - #define PHY_AUTONEGO_COMPLETE_MASK (1U << 5) - - /* PHY_RTL8211 ID one register */ - #define PHY_ID1_REG (0x02U) - - /* PHY_RTL8211 ID two register */ - #define PHY_ID2_REG (0x03U) - - /* PHY_RTL8211 auto-negotiate advertise register */ - #define PHY_AUTONEG_ADVERTISE_REG (0x04U) - - /* PHY_RTL8211 status register */ - #define PHY_STATUS_REG (0x11U) - #define PHY_100M_MASK (1UL << 14) - #define PHY_1000M_MASK (1UL << 15) - #define PHY_FULL_DUPLEX_MASK (1UL << 13) - #define PHY_STATUS_SPEED_100M(SR) ((SR) & PHY_100M_MASK) - #define PHY_STATUS_SPEED_1000M(SR) ((SR) & PHY_1000M_MASK) - #define PHY_STATUS_FULL_DUPLEX(SR) ((SR) & PHY_FULL_DUPLEX_MASK) - #define PHY_SPEED_SEL_SHIFT (14U) - /* PHY_RTL8211 interrupt control register */ - #define PHY_INTERTUPT_CTRL_REG (0x12U) - - /* PHY_RTL8211 interrupt status register */ - #define PHY_INTERRUPT_STATUS_REG (0x13U) - - /* PHY register index */ - typedef enum { - PHY_BASIC_CONTROL_REG_IDX = 0, - PHY_BASIC_STATUS_REG_IDX, - PHY_ID1_REG_IDX, - PHY_ID2_REG_IDX, - PHY_AUTONEG_ADVERTISE_REG_IDX, - PHY_STATUS_REG_IDX, - PHY_INTERRUPT_FLAG_REG_IDX, - PHY_INTERRUPT_MASK_REG_IDX - } phy_reg_idx_t; - - /* ETH0 PHY register list */ - #define PHY0_REG_LIST PHY_BASIC_CONTROL_REG,\ - PHY_BASIC_STATUS_REG,\ - PHY_ID1_REG,\ - PHY_ID2_REG,\ - PHY_AUTONEG_ADVERTISE_REG,\ - PHY_STATUS_REG,\ - PHY_INTERTUPT_CTRL_REG,\ - PHY_INTERRUPT_STATUS_REG - -#else - #include "hpm_rtl8201.h" - - #define RMII (1U) - - /* RTL8201 name and ID */ - #define PHY_NAME ("RTL8201") - #define PHY_ID1 (0x001CU) - #define PHY_ID2 (0x32U) - - /* RTL8201 basic control register */ - #define PHY_BASIC_CONTROL_REG (0x00U) - #define PHY_RESET_MASK (1U << 15) - #define PHY_AUTO_NEGOTIATION_MASK (1U << 12) - - /* RTL8201 basic status register */ - #define PHY_BASIC_STATUS_REG (0x01U) - #define PHY_LINKED_STATUS_MASK (1U << 2) - #define PHY_AUTONEGO_COMPLETE_MASK (1U << 5) - - /* RTL8201 ID one register */ - #define PHY_ID1_REG (0x02U) - - /* RTL8201 ID two register */ - #define PHY_ID2_REG (0x03U) - - /* RTL8201 auto-negotiate advertise register */ - #define PHY_AUTONEG_ADVERTISE_REG (0x04U) - - /* RTL8201 status register */ - #define PHY_STATUS_REG (0x00U) - #define PHY_100M_MASK (1UL << 13) - #define PHY_FULL_DUPLEX_MASK (1UL << 8) - #define PHY_STATUS_SPEED_100M(SR) ((SR) & PHY_100M_MASK) - #define PHY_STATUS_FULL_DUPLEX(SR) ((SR) & PHY_FULL_DUPLEX_MASK) - - /* RTL8201 mode setting register */ - #define PHY_RMSR_P7 (0x10) - #define PHY_RMSR_P7_RG_RMII_CLKDIR_MASK (0x1000U) - - /* RTL8201 page select register */ - #define PHY_PAGESEL (0x1f) - - /* PHY register index */ - typedef enum { - PHY_BASIC_CONTROL_REG_IDX = 0, - PHY_BASIC_STATUS_REG_IDX, - PHY_ID1_REG_IDX, - PHY_ID2_REG_IDX, - PHY_AUTONEG_ADVERTISE_REG_IDX, - PHY_STATUS_REG_IDX, - PHY_RMSR_P7_IDX, - PHY_PAGE_SEL_IDX - } phy_reg_idx_t; - - /* ETH0 PHY register list */ - #define PHY1_REG_LIST PHY_BASIC_CONTROL_REG,\ - PHY_BASIC_STATUS_REG,\ - PHY_ID1_REG,\ - PHY_ID2_REG,\ - PHY_AUTONEG_ADVERTISE_REG,\ - PHY_STATUS_REG,\ - PHY_RMSR_P7_IDX,\ - PHY_PAGE_SEL_IDX - -#endif -#endif diff --git a/bsp/hpmicro/hpm6750evk2/board/fal_cfg.h b/bsp/hpmicro/hpm6750evk2/board/fal_cfg.h index b315dd87c38..3533c1fbb2c 100644 --- a/bsp/hpmicro/hpm6750evk2/board/fal_cfg.h +++ b/bsp/hpmicro/hpm6750evk2/board/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023 HPMicro + * Copyright (c) 2022 hpmicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -28,6 +28,13 @@ extern struct fal_flash_dev nor_flash0; /* ====================== Partition Configuration ========================== */ #ifdef FAL_PART_HAS_TABLE_CFG /* partition table */ +#ifdef CONFIG_WEBNET_FAL_FS +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WORD, "app", NOR_FLASH_DEV_NAME, 0, 6*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "fs", NOR_FLASH_DEV_NAME, 6*1024*1024, 10*1024*1024, 0}, \ +} +#else #define FAL_PART_TABLE \ { \ {FAL_PART_MAGIC_WORD, "app", NOR_FLASH_DEV_NAME, 0, 4*1024*1024, 0}, \ @@ -35,6 +42,7 @@ extern struct fal_flash_dev nor_flash0; {FAL_PART_MAGIC_WORD, "download", NOR_FLASH_DEV_NAME, 7*1024*1024, 8*1024*1024, 0}, \ {FAL_PART_MAGIC_WORD, "flashdb", NOR_FLASH_DEV_NAME, 15*1024*1024, 1*1024*1024, 0}, \ } +#endif #endif /* FAL_PART_HAS_TABLE_CFG */ #endif /* RT_USING_FAL */ diff --git a/bsp/hpmicro/hpm6750evk2/board/fal_flash_port.c b/bsp/hpmicro/hpm6750evk2/board/fal_flash_port.c index 5f21019b862..6960ab7f675 100644 --- a/bsp/hpmicro/hpm6750evk2/board/fal_flash_port.c +++ b/bsp/hpmicro/hpm6750evk2/board/fal_flash_port.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023 HPMicro + * Copyright (c) 2022 hpmicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/hpm6750evk2/board/hpm_wm8960.c b/bsp/hpmicro/hpm6750evk2/board/hpm_wm8960.c index 30e262cf65d..bbb1b25beb4 100644 --- a/bsp/hpmicro/hpm6750evk2/board/hpm_wm8960.c +++ b/bsp/hpmicro/hpm6750evk2/board/hpm_wm8960.c @@ -10,6 +10,10 @@ #include #include "hpm_wm8960.h" +#ifndef HPM_WM8960_MCLK_TOLERANCE +#define HPM_WM8960_MCLK_TOLERANCE (4U) +#endif + /* wm8960 register default value */ static const uint16_t wm8960_default_reg_val[WM8960_REG_NUM] = { 0x0097, 0x0097, 0x0000, 0x0000, 0x0000, 0x0008, 0x0000, 0x000a, 0x01c0, 0x0000, 0x00ff, 0x00ff, 0x0000, 0x0000, @@ -49,6 +53,9 @@ hpm_stat_t wm8960_init(wm8960_control_t *control, wm8960_config_t *config) /* set wm8960 as slave */ HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_MS_MASK, WM8960_IFACE1_MS_SET(0))); + /* invert LRCLK */ + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_LRP_MASK, WM8960_IFACE1_LRP_SET(1))); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ADDCTL1, 0xC0)); HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ADDCTL4, 0x40)); @@ -398,28 +405,39 @@ hpm_stat_t wm8960_set_volume(wm8960_control_t *control, wm8960_module_t module, return stat; } +static bool wm8960_check_clock_tolerance(uint32_t source, uint32_t target) +{ + uint32_t delta = (source >= target) ? (source - target) : (target - source); + if (delta * 100 <= HPM_WM8960_MCLK_TOLERANCE * target) { + return true; + } + return false; +} + hpm_stat_t wm8960_set_data_format(wm8960_control_t *control, uint32_t sysclk, uint32_t sample_rate, uint32_t bits) { hpm_stat_t stat = status_success; - uint32_t divider = 0; - uint16_t val = 0; + uint16_t val = 0; + uint32_t ratio[7] = {256, 256 * 1.5, 256 * 2, 256 * 3, 256 * 4, 256 * 5.5, 256 * 6}; + bool clock_meet_requirement = false; - /* Compute sample rate divider and SYSCLK Pre-divider, dac and adc are the same sample rate */ - divider = sysclk / sample_rate; + if (sysclk / sample_rate > 256 * 6) { + sysclk = sysclk / 2; + val = WM8960_CLOCK1_SYSCLKDIV_SET(2U); /* SYSCLK Pre-divider */ + } - if (divider >= 512) { - divider = divider / 2; /* SYSCLK Pre-divider */ - val |= WM8960_CLOCK1_SYSCLKDIV_SET(2U); + for (uint8_t i = 0; i < 7; i++) { + if (wm8960_check_clock_tolerance(sysclk, sample_rate * ratio[i])) { + val |= ((i << WM8960_CLOCK1_ADCDIV_SHIFT) | (i << WM8960_CLOCK1_DACDIV_SHIFT)); + clock_meet_requirement = true; + break; + } } - if (divider < 256U) { + if (!clock_meet_requirement) { return status_invalid_argument; - } else if (divider == 256U) { - HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_CLOCK1, 0x1FEU, val)); - } else { - val |= (((divider / 256U) << WM8960_CLOCK1_ADCDIV_SHIFT) | ((divider / 256U) << WM8960_CLOCK1_DACDIV_SHIFT)); - HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_CLOCK1, 0x1FEU, val)); } + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_CLOCK1, 0x1FEU, val)); /* set sample bit */ switch (bits) { diff --git a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_rtt.ld b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_rtt.ld index c993127eb1d..a95394ba713 100644 --- a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_rtt.ld +++ b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_rtt.ld @@ -147,6 +147,12 @@ SECTIONS /* RT-Thread related sections - end */ + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + } > XPI0 .rel : { diff --git a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_rtt_enet.ld b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_rtt_enet.ld index e98a75c1219..f1d2bf25ac5 100644 --- a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_rtt_enet.ld +++ b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_rtt_enet.ld @@ -72,14 +72,16 @@ SECTIONS KEEP(*irq.o (.text .text* .rodata .rodata*)) KEEP(*clock.o (.text .text* .rodata .rodata*)) KEEP(*kservice.o (.text .text* .rodata .rodata*)) - KEEP(*scheduler.o (.text .text* .rodata .rodata*)) + KEEP(*scheduler*.o (.text .text* .rodata .rodata*)) KEEP(*trap*.o (.text .text* .rodata .rodata*)) KEEP(*idle.o (.text .text* .rodata .rodata*)) KEEP(*ipc.o (.text .text* .rodata .rodata*)) + KEEP(*slab.o (.text .text* .rodata .rodata*)) KEEP(*thread.o (.text .text* .rodata .rodata*)) KEEP(*object.o (.text .text* .rodata .rodata*)) KEEP(*timer.o (.text .text* .rodata .rodata*)) KEEP(*mem.o (.text .text* .rodata .rodata*)) + KEEP(*memheap.o (.text .text* .rodata .rodata*)) KEEP(*mempool.o (.text .text* .rodata .rodata*)) /* RT-Thread Core End */ @@ -163,6 +165,12 @@ SECTIONS /* RT-Thread related sections - end */ + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + } > XPI0 .rel : { diff --git a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_sdram_rtt.ld b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_sdram_rtt.ld index ed0fce209d0..9ac0b042499 100644 --- a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_sdram_rtt.ld +++ b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_sdram_rtt.ld @@ -141,6 +141,13 @@ SECTIONS /* RT-Thread related sections - end */ + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + } > XPI0 .rel : { diff --git a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/ram_rtt.ld b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/ram_rtt.ld index c3c0f2cf4ef..7d022d2db74 100644 --- a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/ram_rtt.ld +++ b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/ram_rtt.ld @@ -87,6 +87,13 @@ SECTIONS /* RT-Thread related sections - end */ + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); @@ -225,10 +232,6 @@ SECTIONS KEEP(*(.backup_sram)) } > APB_SRAM - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - .stack(NOLOAD) : { . = ALIGN(8); __stack_base__ = .; diff --git a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/ram_sdram_rtt.ld b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/ram_sdram_rtt.ld index dedb377ad31..0458805797b 100644 --- a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/ram_sdram_rtt.ld +++ b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/ram_sdram_rtt.ld @@ -87,6 +87,13 @@ SECTIONS /* RT-Thread related sections - end */ + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); @@ -225,10 +232,6 @@ SECTIONS KEEP(*(.backup_sram)) } > APB_SRAM - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - .stack(NOLOAD) : { . = ALIGN(8); __stack_base__ = .; diff --git a/bsp/hpmicro/hpm6750evk2/board/pinmux.c b/bsp/hpmicro/hpm6750evk2/board/pinmux.c index c008f1dcd0f..a918344b2b7 100644 --- a/bsp/hpmicro/hpm6750evk2/board/pinmux.c +++ b/bsp/hpmicro/hpm6750evk2/board/pinmux.c @@ -21,8 +21,8 @@ void init_uart_pins(UART_Type *ptr) HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART0_RXD; HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART0_TXD; /* PY port IO needs to configure PIOC as well */ - HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_SOC_PY_07; - HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_SOC_PY_06; + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = PIOC_PY07_FUNC_CTL_SOC_PY_07; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = PIOC_PY06_FUNC_CTL_SOC_PY_06; } else if (ptr == HPM_UART2) { HPM_IOC->PAD[IOC_PAD_PE16].FUNC_CTL = IOC_PE16_FUNC_CTL_UART2_TXD; HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PE21_FUNC_CTL_UART2_RXD; @@ -30,13 +30,35 @@ void init_uart_pins(UART_Type *ptr) HPM_IOC->PAD[IOC_PAD_PZ08].FUNC_CTL = IOC_PZ08_FUNC_CTL_UART13_RXD; HPM_IOC->PAD[IOC_PAD_PZ09].FUNC_CTL = IOC_PZ09_FUNC_CTL_UART13_TXD; /* PZ port IO needs to configure BIOC as well */ - HPM_BIOC->PAD[IOC_PAD_PZ08].FUNC_CTL = IOC_PZ08_FUNC_CTL_SOC_PZ_08; - HPM_BIOC->PAD[IOC_PAD_PZ09].FUNC_CTL = IOC_PZ09_FUNC_CTL_SOC_PZ_09; + HPM_BIOC->PAD[IOC_PAD_PZ08].FUNC_CTL = BIOC_PZ08_FUNC_CTL_SOC_PZ_08; + HPM_BIOC->PAD[IOC_PAD_PZ09].FUNC_CTL = BIOC_PZ09_FUNC_CTL_SOC_PZ_09; + } else if (ptr == HPM_PUART) { + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = PIOC_PY07_FUNC_CTL_PUART_RXD; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = PIOC_PY06_FUNC_CTL_PUART_TXD; + } +} + +void init_uart_pin_as_gpio(UART_Type *ptr) +{ + if (ptr == HPM_UART13) { + /* pull-up */ + HPM_IOC->PAD[IOC_PAD_PZ08].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PZ09].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + + /* PZ port IO needs to configure BIOC as well */ + HPM_IOC->PAD[IOC_PAD_PZ08].FUNC_CTL = IOC_PZ08_FUNC_CTL_GPIO_Z_08; + HPM_BIOC->PAD[IOC_PAD_PZ08].FUNC_CTL = BIOC_PZ08_FUNC_CTL_SOC_PZ_08; + + /* PZ port IO needs to configure BIOC as well */ + HPM_IOC->PAD[IOC_PAD_PZ09].FUNC_CTL = IOC_PZ09_FUNC_CTL_GPIO_Z_09; + HPM_BIOC->PAD[IOC_PAD_PZ09].FUNC_CTL = BIOC_PZ09_FUNC_CTL_SOC_PZ_09; } } void init_lcd_pins(LCDC_Type *ptr) { + (void) ptr; + HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_DIS0_R_0; HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_DIS0_R_1; HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PB00_FUNC_CTL_DIS0_R_2; @@ -70,6 +92,10 @@ void init_lcd_pins(LCDC_Type *ptr) HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_GPIO_B_10; /* RST */ HPM_IOC->PAD[IOC_PAD_PB16].FUNC_CTL = IOC_PB16_FUNC_CTL_GPIO_B_16; + + HPM_IOC->PAD[IOC_PAD_PZ00].FUNC_CTL = IOC_PZ00_FUNC_CTL_GPIO_Z_00; + HPM_IOC->PAD[IOC_PAD_PZ00].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); + HPM_BIOC->PAD[IOC_PAD_PZ00].FUNC_CTL = BIOC_PZ00_FUNC_CTL_SOC_PZ_00; } void init_cap_pins(void) @@ -185,16 +211,69 @@ void init_sdram_pins(void) HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); } +void init_sram_pins(void) +{ + /* Non-MUX */ /* MUX */ + HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A0 */ /* A16 */ + HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A1 */ /* A17 */ + HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A2 */ /* A18 */ + HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A3 */ /* A19 */ + HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A4 */ /* A20 */ + HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A5 */ /* A21 */ + HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A6 */ /* A22 */ + HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A7 */ /* A23 */ + HPM_IOC->PAD[IOC_PAD_PC01].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A8 */ + HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A9 */ + HPM_IOC->PAD[IOC_PAD_PB31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A10 */ + HPM_IOC->PAD[IOC_PAD_PB28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A11 */ + HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A12 */ + HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A13 */ + HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A14 */ + HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A15 */ + HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A16 */ + HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A17 */ + HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A18 */ + HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A19 */ + HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A20 */ + HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A21 */ + HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A22 */ + HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A23 */ + + HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D0 */ /* AD0 */ + HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D1 */ /* AD1 */ + HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D2 */ /* AD2 */ + HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D3 */ /* AD3 */ + HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D4 */ /* AD4 */ + HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D5 */ /* AD5 */ + HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D6 */ /* AD6 */ + HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D7 */ /* AD7 */ + HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D8 */ /* AD8 */ + HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D9 */ /* AD9 */ + HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D10 */ /* AD10 */ + HPM_IOC->PAD[IOC_PAD_PD06].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D11 */ /* AD11 */ + HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D12 */ /* AD12 */ + HPM_IOC->PAD[IOC_PAD_PD09].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D13 */ /* AD13 */ + HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D14 */ /* AD14 */ + HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D15 */ /* AD15 */ + + HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #CE */ + HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #OE */ + HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #WE */ + HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #UB */ + HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #LB */ + HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #ADV */ +} + void init_gpio_pins(void) { - uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12; - HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(0); #ifdef USING_GPIO0_FOR_GPIOZ HPM_IOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_GPIO_Z_02; - HPM_IOC->PAD[IOC_PAD_PZ02].PAD_CTL = pad_ctl; - HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_SOC_PZ_02; + HPM_IOC->PAD[IOC_PAD_PZ02].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + /* PZ port IO needs to configure BIOC as well */ + HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = BIOC_PZ02_FUNC_CTL_SOC_PZ_02; #endif } @@ -208,9 +287,21 @@ void init_spi_pins(SPI_Type *ptr) } } +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + if (ptr == HPM_SPI2) { + HPM_IOC->PAD[IOC_PAD_PE31].FUNC_CTL = IOC_PE31_FUNC_CTL_GPIO_E_31; + HPM_IOC->PAD[IOC_PAD_PE30].FUNC_CTL = IOC_PE30_FUNC_CTL_SPI2_MOSI; + HPM_IOC->PAD[IOC_PAD_PE28].FUNC_CTL = IOC_PE28_FUNC_CTL_SPI2_MISO; + HPM_IOC->PAD[IOC_PAD_PE27].FUNC_CTL = IOC_PE27_FUNC_CTL_SPI2_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + } +} + void init_pins(void) { - init_uart_pins(BOARD_CONSOLE_BASE); +#ifdef BOARD_CONSOLE_UART_BASE + init_uart_pins(BOARD_CONSOLE_UART_BASE); +#endif init_sdram_pins(); } @@ -224,6 +315,27 @@ void init_gptmr_pins(GPTMR_Type *ptr) /* TMR4 capture 1 */ HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PE25_FUNC_CTL_GPTMR4_CAPT_1; } + if (ptr == HPM_GPTMR5) { + /* TMR5 compare 2 */ + HPM_IOC->PAD[IOC_PAD_PD24].FUNC_CTL = IOC_PD24_FUNC_CTL_TRGM2_P_10; + trgm_enable_io_output(HPM_TRGM2, 1 << 10); + + /* TMR5 compare 3 */ + HPM_IOC->PAD[IOC_PAD_PD23].FUNC_CTL = IOC_PD23_FUNC_CTL_TRGM2_P_11; + trgm_enable_io_output(HPM_TRGM2, 1 << 11); + + trgm_output_t trgm2IoConfig0; + trgm2IoConfig0.invert = 0; + trgm2IoConfig0.type = trgm_output_same_as_input; + trgm2IoConfig0.input = HPM_TRGM2_INPUT_SRC_GPTMR5_OUT2; + trgm_output_config(HPM_TRGM2, HPM_TRGM2_OUTPUT_SRC_TRGM2_P10, &trgm2IoConfig0); + + trgm_output_t trgm2IoConfig1; + trgm2IoConfig1.invert = 0; + trgm2IoConfig1.type = trgm_output_same_as_input; + trgm2IoConfig1.input = HPM_TRGM2_INPUT_SRC_GPTMR5_OUT3; + trgm_output_config(HPM_TRGM2, HPM_TRGM2_OUTPUT_SRC_TRGM2_P11, &trgm2IoConfig1); + } } void init_hall_trgm_pins(void) @@ -255,8 +367,8 @@ void init_dao_pins(void) HPM_IOC->PAD[IOC_PAD_PY08].FUNC_CTL = IOC_PY08_FUNC_CTL_DAOR_P; HPM_IOC->PAD[IOC_PAD_PY09].FUNC_CTL = IOC_PY09_FUNC_CTL_DAOR_N; /* PY port IO needs to configure PIOC */ - HPM_PIOC->PAD[IOC_PAD_PY08].FUNC_CTL = IOC_PY08_FUNC_CTL_SOC_PY_08; - HPM_PIOC->PAD[IOC_PAD_PY09].FUNC_CTL = IOC_PY09_FUNC_CTL_SOC_PY_09; + HPM_PIOC->PAD[IOC_PAD_PY08].FUNC_CTL = PIOC_PY08_FUNC_CTL_SOC_PY_08; + HPM_PIOC->PAD[IOC_PAD_PY09].FUNC_CTL = PIOC_PY09_FUNC_CTL_SOC_PY_09; } void init_pdm_pins(void) @@ -264,14 +376,14 @@ void init_pdm_pins(void) HPM_IOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_PDM0_CLK; HPM_IOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_PDM0_D_0; /* PY port IO needs to configure PIOC */ - HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_SOC_PY_10; - HPM_PIOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_SOC_PY_11; + HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = PIOC_PY10_FUNC_CTL_SOC_PY_10; + HPM_PIOC->PAD[IOC_PAD_PY11].FUNC_CTL = PIOC_PY11_FUNC_CTL_SOC_PY_11; } void init_vad_pins(void) { - HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_VAD_CLK; - HPM_PIOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_VAD_DAT; + HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = PIOC_PY10_FUNC_CTL_VAD_CLK; + HPM_PIOC->PAD[IOC_PAD_PY11].FUNC_CTL = PIOC_PY11_FUNC_CTL_VAD_DAT; } void init_cam_pins(void) @@ -279,7 +391,7 @@ void init_cam_pins(void) /* configure rst pin function */ HPM_IOC->PAD[IOC_PAD_PY05].FUNC_CTL = IOC_PY05_FUNC_CTL_GPIO_Y_05; /* PY port IO needs to configure PIOC */ - HPM_PIOC->PAD[IOC_PAD_PY05].FUNC_CTL = IOC_PY05_FUNC_CTL_SOC_PY_05; + HPM_PIOC->PAD[IOC_PAD_PY05].FUNC_CTL = PIOC_PY05_FUNC_CTL_SOC_PY_05; HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_CAM0_XCLK; HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_CAM0_PIXCLK; @@ -297,10 +409,10 @@ void init_cam_pins(void) void init_butn_pins(void) { - HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_PBUTN; - HPM_BIOC->PAD[IOC_PAD_PZ03].FUNC_CTL = IOC_PZ03_FUNC_CTL_WBUTN; - HPM_BIOC->PAD[IOC_PAD_PZ04].FUNC_CTL = IOC_PZ04_FUNC_CTL_PLED; - HPM_BIOC->PAD[IOC_PAD_PZ05].FUNC_CTL = IOC_PZ05_FUNC_CTL_WLED; + HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = BIOC_PZ02_FUNC_CTL_PBUTN; + HPM_BIOC->PAD[IOC_PAD_PZ03].FUNC_CTL = BIOC_PZ03_FUNC_CTL_WBUTN; + HPM_BIOC->PAD[IOC_PAD_PZ04].FUNC_CTL = BIOC_PZ04_FUNC_CTL_PLED; + HPM_BIOC->PAD[IOC_PAD_PZ05].FUNC_CTL = BIOC_PZ05_FUNC_CTL_WLED; } void init_acmp_pins(void) @@ -417,57 +529,74 @@ void init_can_pins(CAN_Type *ptr) } } -void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8) +void init_sdxc_cmd_pin(SDXC_Type *ptr, bool open_drain, bool is_1v8) { uint32_t cmd_func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); - uint32_t func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17); - uint32_t pad_ctl = IOC_PAD_PAD_CTL_MS_SET(use_1v8) | IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_PE_SET(1) | - IOC_PAD_PAD_CTL_PS_SET(1); - - if (ptr == HPM_SDXC0) { - } else if (ptr == HPM_SDXC1) { - /* CLK */ - HPM_IOC->PAD[IOC_PAD_PD22].FUNC_CTL = func_ctl; - HPM_IOC->PAD[IOC_PAD_PD22].PAD_CTL = pad_ctl; + uint32_t cmd_pad_ctl = IOC_PAD_PAD_CTL_MS_SET(is_1v8) | IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | + IOC_PAD_PAD_CTL_PS_SET(1); + if (open_drain) { + cmd_pad_ctl |= IOC_PAD_PAD_CTL_OD_MASK; + } - /* CMD */ + if (ptr == HPM_SDXC1) { + /* SDXC1.CMD */ HPM_IOC->PAD[IOC_PAD_PD21].FUNC_CTL = cmd_func_ctl; - HPM_IOC->PAD[IOC_PAD_PD21].PAD_CTL = pad_ctl; - - /* DATA0 */ - HPM_IOC->PAD[IOC_PAD_PD18].FUNC_CTL = func_ctl; - HPM_IOC->PAD[IOC_PAD_PD18].PAD_CTL = pad_ctl; - /* DATA1 */ - HPM_IOC->PAD[IOC_PAD_PD17].FUNC_CTL = func_ctl; - HPM_IOC->PAD[IOC_PAD_PD17].PAD_CTL = pad_ctl; - /* DATA2 */ - HPM_IOC->PAD[IOC_PAD_PD27].FUNC_CTL = func_ctl; - HPM_IOC->PAD[IOC_PAD_PD27].PAD_CTL = pad_ctl; - /* DATA3 */ - HPM_IOC->PAD[IOC_PAD_PD26].FUNC_CTL = func_ctl; - HPM_IOC->PAD[IOC_PAD_PD26].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PD21].PAD_CTL = cmd_pad_ctl; } } -void init_sdxc_power_pin(SDXC_Type *ptr) +void init_sdxc_cd_pin(SDXC_Type *ptr, bool as_gpio) { - /* Power */ - HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PC20_FUNC_CTL_GPIO_C_20; - HPM_IOC->PAD[IOC_PAD_PC20].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + uint32_t cd_pad_ctl = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + if (ptr == HPM_SDXC1) { + if (as_gpio) { + /* SDXC1.CDN */ + uint32_t cd_func_alt = IOC_PD15_FUNC_CTL_GPIO_D_15; + HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = cd_func_alt; + HPM_IOC->PAD[IOC_PAD_PD15].PAD_CTL = cd_pad_ctl; + } + } } -void init_sdxc_vsel_pin(SDXC_Type *ptr) +void init_sdxc_clk_data_pins(SDXC_Type *ptr, uint32_t width, bool is_1v8) { + uint32_t func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17); + uint32_t pad_ctl = IOC_PAD_PAD_CTL_MS_SET(is_1v8) | IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | + IOC_PAD_PAD_CTL_PS_SET(1); + + if (ptr == HPM_SDXC1) { + /* SDXC1.CLK */ + HPM_IOC->PAD[IOC_PAD_PD22].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD22].PAD_CTL = pad_ctl; + /* SDXC1.DATA0 */ + HPM_IOC->PAD[IOC_PAD_PD18].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD18].PAD_CTL = pad_ctl; + if ((width == 4)) { + /* SDXC1.DATA1 */ + HPM_IOC->PAD[IOC_PAD_PD17].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD17].PAD_CTL = pad_ctl; + /* SDXC1.DATA2 */ + HPM_IOC->PAD[IOC_PAD_PD27].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD27].PAD_CTL = pad_ctl; + /* SDXC1.DATA3 */ + HPM_IOC->PAD[IOC_PAD_PD26].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD26].PAD_CTL = pad_ctl; + } + } } -void init_sdxc_card_detection_pin(SDXC_Type *ptr) +void init_sdxc_pwr_pin(SDXC_Type *ptr, bool as_gpio) { - /* CDN */ - HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = IOC_PD15_FUNC_CTL_GPIO_D_15; - HPM_IOC->PAD[IOC_PAD_PD15].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_PE_SET(1) | - IOC_PAD_PAD_CTL_PS_SET(1); - HPM_GPIO0->OE[GPIO_OE_GPIOD].CLEAR = 1UL << BOARD_APP_SDCARD_CARD_DETECTION_PIN_INDEX; + if (ptr == HPM_SDXC1) { + if (as_gpio) { + /* SD_PWR */ + HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PC20_FUNC_CTL_GPIO_C_20; + HPM_IOC->PAD[IOC_PAD_PC20].PAD_CTL = + IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_DS_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_GPIO0->OE[GPIO_OE_GPIOC].SET = 1UL << 20; + } + } } void init_clk_obs_pins(void) @@ -487,12 +616,19 @@ void init_rgb_pwm_pins(void) void init_led_pins_as_gpio(void) { - uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); - HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_GPIO_B_11; - HPM_IOC->PAD[IOC_PAD_PB11].PAD_CTL = pad_ctl; HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12; - HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = pad_ctl; HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_GPIO_B_13; - HPM_IOC->PAD[IOC_PAD_PB13].PAD_CTL = pad_ctl; +} + +void init_enet_pps_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PF05].FUNC_CTL = IOC_PF05_FUNC_CTL_ETH0_EVTO_0; +} + +void init_tamper_pins(void) +{ + HPM_BIOC->PAD[IOC_PAD_PZ08].FUNC_CTL = BIOC_PZ08_FUNC_CTL_TAMP_08 | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_BIOC->PAD[IOC_PAD_PZ09].FUNC_CTL = BIOC_PZ09_FUNC_CTL_TAMP_09; + HPM_BIOC->PAD[IOC_PAD_PZ10].FUNC_CTL = BIOC_PZ10_FUNC_CTL_TAMP_10; } diff --git a/bsp/hpmicro/hpm6750evk2/board/pinmux.h b/bsp/hpmicro/hpm6750evk2/board/pinmux.h index 52c97a9b9a4..7b850152b53 100644 --- a/bsp/hpmicro/hpm6750evk2/board/pinmux.h +++ b/bsp/hpmicro/hpm6750evk2/board/pinmux.h @@ -12,12 +12,15 @@ extern "C" { #endif void init_uart_pins(UART_Type *ptr); +void init_uart_pin_as_gpio(UART_Type *ptr); void init_lcd_pins(LCDC_Type *ptr); void init_i2c_pins(I2C_Type *ptr); void init_cap_pins(void); void init_sdram_pins(void); +void init_sram_pins(void); void init_gpio_pins(void); void init_spi_pins(SPI_Type *ptr); +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); void init_pins(void); void init_gptmr_pins(GPTMR_Type *ptr); void init_hall_trgm_pins(void); @@ -31,19 +34,21 @@ void init_butn_pins(void); void init_acmp_pins(void); void init_enet_pins(ENET_Type *ptr); void init_pwm_pins(PWM_Type *ptr); +void init_sdxc_cmd_pin(SDXC_Type *ptr, bool open_drain, bool is_1v8); +void init_sdxc_cd_pin(SDXC_Type *ptr, bool as_gpio); +void init_sdxc_clk_data_pins(SDXC_Type *ptr, uint32_t width, bool is_1v8); +void init_sdxc_pwr_pin(SDXC_Type *ptr, bool as_gpio); void init_adc12_pins(void); void init_adc16_pins(void); void init_usb_pins(void); void init_can_pins(CAN_Type *ptr); -void init_sdxc_power_pin(SDXC_Type *ptr); -void init_sdxc_vsel_pin(SDXC_Type *ptr); -void init_sdxc_card_detection_pin(SDXC_Type *ptr); -void init_sdxc_pins(SDXC_Type * ptr, bool use_1v8); void init_adc_bldc_pins(void); void init_rgb_pwm_pins(void); void init_i2c_pins_as_gpio(I2C_Type *ptr); void init_led_pins_as_gpio(void); void init_trgmux_pins(uint32_t pin); +void init_enet_pps_pins(void); +void init_tamper_pins(void); #ifdef __cplusplus } diff --git a/bsp/hpmicro/hpm6750evk2/board/rtt_board.c b/bsp/hpmicro/hpm6750evk2/board/rtt_board.c index 0fef780fd36..293167c529c 100644 --- a/bsp/hpmicro/hpm6750evk2/board/rtt_board.c +++ b/bsp/hpmicro/hpm6750evk2/board/rtt_board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * SPDX-License-Identifier: BSD-3-Clause * */ @@ -8,18 +8,34 @@ #include "rtt_board.h" #include "hpm_uart_drv.h" #include "hpm_gpio_drv.h" -#include "hpm_mchtmr_drv.h" #include "hpm_pmp_drv.h" #include "assert.h" #include "hpm_clock_drv.h" #include "hpm_sysctl_drv.h" #include #include -#include "hpm_dma_manager.h" +#include "hpm_dma_mgr.h" +#include "hpm_mchtmr_drv.h" +extern int rt_hw_uart_init(void); void os_tick_config(void); +void rtt_board_init(void); -extern int rt_hw_uart_init(void); +void rt_hw_board_init(void) +{ + rtt_board_init(); + + /* Call the RT-Thread Component Board Initialization */ + rt_components_board_init(); +} + +void os_tick_config(void) +{ + sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1); + sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0); + mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND); + enable_mchtmr_irq(); +} void rtt_board_init(void) { @@ -27,7 +43,7 @@ void rtt_board_init(void) board_init_console(); board_init_pmp(); - dma_manager_init(); + dma_mgr_init(); /* initialize memory system */ rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); @@ -72,24 +88,6 @@ void app_led_write(uint32_t index, bool state) } } -void os_tick_config(void) -{ - sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1); - sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0); - - mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND); - - enable_mchtmr_irq(); -} - -void rt_hw_board_init(void) -{ - rtt_board_init(); - - /* Call the RT-Thread Component Board Initialization */ - rt_components_board_init(); -} - void rt_hw_console_output(const char *str) { while (*str != '\0') @@ -98,18 +96,16 @@ void rt_hw_console_output(const char *str) } } +void app_init_usb_pins(void) +{ + board_init_usb_pins(); +} + ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) { HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND; - rt_interrupt_enter(); rt_tick_increase(); - rt_interrupt_leave(); -} - -void rt_hw_us_delay(rt_uint32_t us) -{ - clock_cpu_delay_us(us); } void rt_hw_cpu_reset(void) diff --git a/bsp/hpmicro/hpm6750evk2/board/rtt_board.h b/bsp/hpmicro/hpm6750evk2/board/rtt_board.h index 8a05e027d01..fbe587f3af6 100644 --- a/bsp/hpmicro/hpm6750evk2/board/rtt_board.h +++ b/bsp/hpmicro/hpm6750evk2/board/rtt_board.h @@ -38,6 +38,21 @@ /* CAN section */ #define BOARD_CAN_NAME "can0" +#define BOARD_CAN_HWFILTER_INDEX (0U) + +/* UART section */ +#define BOARD_UART_NAME "uart13" +#define BOARD_UART_RX_BUFFER_SIZE BSP_UART13_RX_BUFSIZE + +/* eeprom section */ +#define BOARD_EEPROM_I2C_NAME "i2c0" + +#define BOARD_SD_NAME "sd1" +/* audio section */ +#define BOARD_AUDIO_CODEC_I2C_NAME "i2c0" +#define BOARD_AUDIO_CODEC_I2S_NAME "i2s0" + +#define IRQn_PendSV IRQn_DEBUG_0 /*************************************************************** * @@ -65,7 +80,7 @@ extern "C" { void app_init_led_pins(void); void app_led_write(uint32_t index, bool state); - +void app_init_usb_pins(void); #if defined(__cplusplus) diff --git a/bsp/hpmicro/hpm6750evk2/rtconfig.py b/bsp/hpmicro/hpm6750evk2/rtconfig.py index f199f0f3653..d0781627b3f 100644 --- a/bsp/hpmicro/hpm6750evk2/rtconfig.py +++ b/bsp/hpmicro/hpm6750evk2/rtconfig.py @@ -81,8 +81,8 @@ LFLAGS += ' -O0' LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' elif BUILD == 'ram_release': - CFLAGS += ' -O2 -Os' - LFLAGS += ' -O2 -Os' + CFLAGS += ' -O2' + LFLAGS += ' -O2' LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' elif BUILD == 'flash_debug': CFLAGS += ' -gdwarf-2' @@ -92,13 +92,13 @@ CFLAGS += ' -DFLASH_XIP=1' LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' elif BUILD == 'flash_release': - CFLAGS += ' -O2 -Os' - LFLAGS += ' -O2 -Os' + CFLAGS += ' -O2' + LFLAGS += ' -O2' CFLAGS += ' -DFLASH_XIP=1' LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' else: - CFLAGS += ' -O2 -Os' - LFLAGS += ' -O2 -Os' + CFLAGS += ' -O2' + LFLAGS += ' -O2' LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' LFLAGS += ' -T ' + LINKER_FILE diff --git a/bsp/hpmicro/hpm6750evk2/startup/HPM6750/toolchains/gcc/start.S b/bsp/hpmicro/hpm6750evk2/startup/HPM6750/toolchains/gcc/start.S index 5c47c92afe7..238e05b43bb 100644 --- a/bsp/hpmicro/hpm6750evk2/startup/HPM6750/toolchains/gcc/start.S +++ b/bsp/hpmicro/hpm6750evk2/startup/HPM6750/toolchains/gcc/start.S @@ -25,6 +25,15 @@ _start: ori t1, t1, 0x80 sw t1, 0(t0) +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + #ifdef INIT_EXT_RAM_FOR_DATA la t0, _stack_in_dlm mv sp, t0 diff --git a/bsp/hpmicro/hpm6750evkmini/.config b/bsp/hpmicro/hpm6750evkmini/.config index 2b5e222d9b9..1d3c2343092 100644 --- a/bsp/hpmicro/hpm6750evkmini/.config +++ b/bsp/hpmicro/hpm6750evkmini/.config @@ -24,18 +24,22 @@ CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=512 +CONFIG_IDLE_THREAD_STACK_SIZE=1024 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 -CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024 # # kservice optimization # -# CONFIG_RT_KSERVICE_USING_STDLIB is not set -# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set # CONFIG_RT_USING_TINY_FFS is not set -# CONFIG_RT_KPRINTF_USING_LONGLONG is not set + +# +# klibc optimization +# +# CONFIG_RT_KLIBC_USING_STDLIB is not set +# CONFIG_RT_KLIBC_USING_TINY_SIZE is not set +# CONFIG_RT_KLIBC_USING_PRINTF_LONGLONG is not set # CONFIG_RT_USING_DEBUG is not set # @@ -72,7 +76,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -CONFIG_RT_VER_NUM=0x50100 +CONFIG_RT_VER_NUM=0x50200 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # CONFIG_RT_USING_CACHE is not set @@ -80,6 +84,7 @@ CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_USING_HW_THREAD_SELF is not set # # RT-Thread Components @@ -137,9 +142,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set -CONFIG_RT_USING_RTC=y -# CONFIG_RT_USING_ALARM is not set -# CONFIG_RT_USING_SOFT_RTC is not set +# CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set # CONFIG_RT_USING_SPI is not set # CONFIG_RT_USING_WDT is not set @@ -492,9 +495,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CMSIS: ARM Cortex-M Microcontroller Software Interface Standard # # CONFIG_PKG_USING_CMSIS_5 is not set -# CONFIG_PKG_USING_CMSIS_CORE is not set -# CONFIG_PKG_USING_CMSIS_DSP is not set -# CONFIG_PKG_USING_CMSIS_NN is not set # CONFIG_PKG_USING_CMSIS_RTOS1 is not set # CONFIG_PKG_USING_CMSIS_RTOS2 is not set @@ -559,29 +559,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # peripheral libraries and drivers # -# -# HAL & SDK Drivers -# - -# -# STM32 HAL & SDK Drivers -# -# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set -# CONFIG_PKG_USING_STM32WB55_SDK is not set -# CONFIG_PKG_USING_STM32_SDIO is not set -# CONFIG_PKG_USING_BLUETRUM_SDK is not set -# CONFIG_PKG_USING_EMBARC_BSP is not set -# CONFIG_PKG_USING_ESP_IDF is not set - -# -# Kendryte SDK -# -# CONFIG_PKG_USING_K210_SDK is not set -# CONFIG_PKG_USING_KENDRYTE_SDK is not set -# CONFIG_PKG_USING_NRF5X_SDK is not set -# CONFIG_PKG_USING_NRFX is not set -# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set - # # sensors drivers # @@ -663,8 +640,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_FT6236 is not set # CONFIG_PKG_USING_XPT2046_TOUCH is not set # CONFIG_PKG_USING_CST816X is not set -# CONFIG_PKG_USING_CST812T is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ESP_IDF is not set # CONFIG_PKG_USING_BUTTON is not set # CONFIG_PKG_USING_PCF8574 is not set # CONFIG_PKG_USING_SX12XX is not set @@ -672,6 +650,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_LEDBLINK is not set # CONFIG_PKG_USING_LITTLED is not set # CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set # CONFIG_PKG_USING_MULTI_INFRARED is not set # CONFIG_PKG_USING_AGILE_BUTTON is not set @@ -686,6 +672,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_AS608 is not set # CONFIG_PKG_USING_RC522 is not set # CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set # CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set # CONFIG_PKG_USING_MULTI_RTIMER is not set # CONFIG_PKG_USING_MAX7219 is not set @@ -708,6 +695,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_VIRTUAL_SENSOR is not set # CONFIG_PKG_USING_VDEVICE is not set # CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set # CONFIG_PKG_USING_RDA58XX is not set # CONFIG_PKG_USING_LIBNFC is not set # CONFIG_PKG_USING_MFOC is not set @@ -717,6 +705,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ROSSERIAL is not set # CONFIG_PKG_USING_MICRO_ROS is not set # CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set # CONFIG_PKG_USING_MISAKA_AT24CXX is not set # CONFIG_PKG_USING_MISAKA_RGB_BLING is not set # CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set @@ -724,6 +713,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_MB85RS16 is not set # CONFIG_PKG_USING_RFM300 is not set # CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set # CONFIG_PKG_USING_LRF_NV7LIDAR is not set # CONFIG_PKG_USING_AIP650 is not set # CONFIG_PKG_USING_FINGERPRINT is not set @@ -734,7 +724,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_X9555 is not set # CONFIG_PKG_USING_SYSTEM_RUN_LED is not set # CONFIG_PKG_USING_BT_MX01 is not set -# CONFIG_PKG_USING_RGPOWER is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # @@ -1051,6 +1040,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # Hardware Drivers Config # CONFIG_SOC_HPM6000=y +# CONFIG_BSP_USING_ENET_PHY_LAN8720 is not set # # On-chip Peripheral Drivers @@ -1084,3 +1074,8 @@ CONFIG_INIT_EXT_RAM_FOR_DATA=y # CONFIG_BSP_USING_WDG is not set # CONFIG_BSP_USING_CAN is not set # CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_CAMERA is not set +# CONFIG_BSP_USING_JPEG is not set +# CONFIG_BSP_USING_CAM is not set +# CONFIG_BSP_USING_PANEL is not set +# CONFIG_BSP_USING_RTT_LCD_DRIVER is not set diff --git a/bsp/hpmicro/hpm6750evkmini/README.md b/bsp/hpmicro/hpm6750evkmini/README.md index aab8844e17a..00cfb6542ac 100644 --- a/bsp/hpmicro/hpm6750evkmini/README.md +++ b/bsp/hpmicro/hpm6750evkmini/README.md @@ -51,7 +51,7 @@ The BSP support being build via the 'scons' command, below is the steps of compi - Download the package and extract it into a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain` - Step 3: Set environment variable `RTT_RISCV_TOOLCHAIN` to `\bin` - For example: `C:\DevTools\riscv32-gnu-toolchain\bin` -- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip) +- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip) - Download and extract it to specified directory, for example: `C:\DevTools\openocd-hpmicro` - Add `OpenOCD` environment variable `OPENOCD_HPMICRO` to `\bin` - For example: `C:\DevTools\openocd-hpmicro\bin` diff --git a/bsp/hpmicro/hpm6750evkmini/README_zh.md b/bsp/hpmicro/hpm6750evkmini/README_zh.md index 7f4b7b28047..00b4c9bb141 100644 --- a/bsp/hpmicro/hpm6750evkmini/README_zh.md +++ b/bsp/hpmicro/hpm6750evkmini/README_zh.md @@ -53,7 +53,7 @@ HPM6750EVKMINI 是由先楫半导体推出的一款基于RISCV内核的开发板 - 步骤 2: 准备 [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) - 下载并解压到指定的目录，如: `C:\DevTools\riscv32-gnu-toolchain` - 步骤 3: 设置环境变量： `RTT_RISCV_TOOLCHAIN` 为 `\bin`， 如: `C:\DevTools\riscv32-gnu-toolchain\bin` -- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip) +- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip) - 下载并解压到指定目录，如: `C:\DevTools\openocd-hpmicro` - 将 `OPENOCD_HPMICRO`环境变量设置为 `\bin`，如： `C:\DevTools\openocd-hpmicro\bin` diff --git a/bsp/hpmicro/hpm6750evkmini/applications/main.c b/bsp/hpmicro/hpm6750evkmini/applications/main.c index a82b3f2cfdd..a5a7f07c737 100644 --- a/bsp/hpmicro/hpm6750evkmini/applications/main.c +++ b/bsp/hpmicro/hpm6750evkmini/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2024 HPMicro * * Change Logs: * Date Author Notes @@ -15,7 +15,6 @@ void thread_entry(void *arg); int main(void) { - app_init_led_pins(); static uint32_t led_thread_arg = 0; diff --git a/bsp/hpmicro/hpm6750evkmini/board/Kconfig b/bsp/hpmicro/hpm6750evkmini/board/Kconfig index bf463b7e2c1..31468bd6da1 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/Kconfig +++ b/bsp/hpmicro/hpm6750evkmini/board/Kconfig @@ -7,6 +7,10 @@ config SOC_HPM6000 select RT_USING_USER_MAIN default y +config BSP_USING_ENET_PHY_LAN8720 + bool + default n + menu "On-chip Peripheral Drivers" config BSP_USING_GPIO bool "Enable GPIO" @@ -38,25 +42,22 @@ menu "On-chip Peripheral Drivers" bool "Enable UART0 RX DMA" depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA default n - config BSP_UART0_TX_USING_DMA bool "Enable UART0 TX DMA" depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA default n - config BSP_UART0_RX_BUFSIZE int "Set UART0 RX buffer size" range 64 65535 depends on RT_USING_SERIAL_V2 default 128 - config BSP_UART0_TX_BUFSIZE int "Set UART0 TX buffer size" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 endif - menuconfig BSP_USING_UART6 + menuconfig BSP_USING_UART6 bool "Enable UART6" default n if BSP_USING_UART6 @@ -64,51 +65,45 @@ menu "On-chip Peripheral Drivers" bool "Enable UART6 RX DMA" depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA default n - config BSP_UART6_TX_USING_DMA bool "Enable UART6 TX DMA" depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA default n - config BSP_UART6_RX_BUFSIZE int "Set UART6 RX buffer size" range 64 65535 depends on RT_USING_SERIAL_V2 default 128 - config BSP_UART6_TX_BUFSIZE int "Set UART6 TX buffer size" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 endif - menuconfig BSP_USING_UART13 + menuconfig BSP_USING_UART13 bool "Enable UART13" - default n + default y if BSP_USING_UART13 config BSP_UART13_RX_USING_DMA bool "Enable UART13 RX DMA" depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA default n - config BSP_UART13_TX_USING_DMA bool "Enable UART13 TX DMA" depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA default n - config BSP_UART13_RX_BUFSIZE int "Set UART13 RX buffer size" range 64 65535 depends on RT_USING_SERIAL_V2 default 128 - config BSP_UART13_TX_BUFSIZE int "Set UART13 TX buffer size" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 endif - menuconfig BSP_USING_UART14 + menuconfig BSP_USING_UART14 bool "Enable UART14" default n if BSP_USING_UART14 @@ -116,18 +111,15 @@ menu "On-chip Peripheral Drivers" bool "Enable UART14 RX DMA" depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA default n - config BSP_UART14_TX_USING_DMA bool "Enable UART14 TX DMA" depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA default n - config BSP_UART14_RX_BUFSIZE int "Set UART14 RX buffer size" range 64 65535 depends on RT_USING_SERIAL_V2 default 128 - config BSP_UART14_TX_BUFSIZE int "Set UART14 TX buffer size" range 0 65535 @@ -145,13 +137,28 @@ menu "On-chip Peripheral Drivers" if BSP_USING_SPI config BSP_USING_SPI1 bool "Enable SPI1" - default y + default y + if BSP_USING_SPI1 + config BSP_SPI1_USING_DMA + bool "Enable SPI1 DMA" + default n + endif config BSP_USING_SPI2 bool "Enable SPI2" + default n + if BSP_USING_SPI2 + config BSP_SPI2_USING_DMA + bool "Enable SPI2 DMA" default n + endif config BSP_USING_SPI3 bool "Enable SPI3" + default n + if BSP_USING_SPI3 + config BSP_SPI3_USING_DMA + bool "Enable SPI3 DMA" default n + endif endif menuconfig BSP_USING_RTC @@ -165,7 +172,8 @@ menu "On-chip Peripheral Drivers" if BSP_USING_ETH config BSP_USING_ETH1 bool "Enable ETH1" - default n + default n + select BSP_USING_ENET_PHY_LAN8720 endif menuconfig BSP_USING_SDXC @@ -175,11 +183,65 @@ menu "On-chip Peripheral Drivers" if BSP_USING_SDXC config BSP_USING_SDXC0 bool "Enable SDXC0" - default n + default n + if BSP_USING_SDXC0 + choice + prompt "Select BUS_WIDTH" + default BSP_SDXC0_BUS_WIDTH_8BIT + config BSP_SDXC0_BUS_WIDTH_1BIT + bool "1-bit" + config BSP_SDXC0_BUS_WIDTH_4BIT + bool "4-bit" + config BSP_SDXC0_BUS_WIDTH_8BIT + bool "8-bit" + endchoice + choice + prompt "Select Voltage" + default BSP_SDXC0_VOLTAGE_1V8 + config BSP_SDXC0_VOLTAGE_3V3 + bool "3.3V" + config BSP_SDXC0_VOLTAGE_1V8 + bool "1.8V" + config BSP_SDXC0_VOLTAGE_DUAL + bool "Dual voltage 3.3V / 1.8V" + endchoice + config BSP_SDXC0_VSEL_PIN + default "None" + string "VSEL pin name" + config BSP_SDXC0_PWR_PIN + default "None" + string "PWR pin name" + endif config BSP_USING_SDXC1 bool "Enable SDXC1" - default y + default n + if BSP_USING_SDXC1 + choice + prompt "Select BUS_WIDTH" + default BSP_SDXC1_BUS_WIDTH_4BIT + config BSP_SDXC1_BUS_WIDTH_1BIT + bool "1-bit" + config BSP_SDXC1_BUS_WIDTH_4BIT + bool "4-bit" + endchoice + choice + prompt "Select Voltage" + default BSP_SDXC1_VOLTAGE_3V3 + config BSP_SDXC1_VOLTAGE_3V3 + bool "3.3V" + config BSP_SDXC1_VOLTAGE_1V8 + bool "1.8V" + config BSP_SDXC1_VOLTAGE_DUAL + bool "Dual voltage 3.3V / 1.8V" + endchoice + config BSP_SDXC1_VSEL_PIN + default "PD29" + string "VSEL pin name" + config BSP_SDXC1_PWR_PIN + default "None" + string "PWR pin name" + endif endif menuconfig BSP_USING_TOUCH @@ -188,16 +250,21 @@ menu "On-chip Peripheral Drivers" if BSP_USING_TOUCH config BSP_USING_TOUCH_GT911 bool "Enable GT911" - default y + default y config BSP_USING_TOUCH_FT5406 bool "Enable FT5406" - default n + default n endif menuconfig BSP_USING_LCD bool "Enable LCD" default n + if BSP_USING_LCD + config BSP_USING_LCD_ISR + bool "Enable LCD interrupt" + default n + endif menuconfig BSP_USING_LVGL bool "Enable LVGL" @@ -236,17 +303,31 @@ menu "On-chip Peripheral Drivers" bool "Enable GPTMR7" default n endif + menuconfig BSP_USING_I2C bool "Enable I2C" default n if BSP_USING_I2C config BSP_USING_I2C0 bool "Enable I2C0" - default y + default y + + if BSP_USING_I2C0 + config BSP_I2C0_USING_DMA + bool "Enable I2C0 DMA" + default n + endif config BSP_USING_I2C3 bool "Enable I2C3" + default n + + if BSP_USING_I2C3 + config BSP_I2C3_USING_DMA + bool "Enable I2C3 DMA" default n + endif + endif menuconfig BSP_USING_FEMC @@ -259,12 +340,12 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_XPI_FLASH bool "Enable XPI FLASH" - default n + default n select RT_USING_FAL if BSP_USING_XPI_FLASH menuconfig BSP_USING_PWM bool "Enable PWM" - default n + default n menuconfig BSP_USING_DAO bool "Enable Audio DAO play" @@ -283,7 +364,7 @@ menu "On-chip Peripheral Drivers" if BSP_USING_I2S config BSP_USING_I2S0 bool "Enable I2S0" - default y + default y endif menuconfig BSP_USING_USB @@ -292,14 +373,15 @@ menu "On-chip Peripheral Drivers" if BSP_USING_USB config BSP_USING_USB_DEVICE bool "Enable USB Device" - default n + default n config BSP_USING_USB_HOST bool "Enable USB HOST" - default n + select RT_USING_CACHE + default n endif - menuconfig BSP_USING_WDG + menuconfig BSP_USING_WDG bool "Enable Watchdog" default n select RT_USING_WDT if BSP_USING_WDG @@ -318,7 +400,7 @@ menu "On-chip Peripheral Drivers" default n endif - menuconfig BSP_USING_CAN + menuconfig BSP_USING_CAN bool "Enable CAN" default n select RT_USING_CAN if BSP_USING_CAN @@ -337,36 +419,74 @@ menu "On-chip Peripheral Drivers" default n endif - menuconfig BSP_USING_ADC - bool "Enable ADC" + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC if BSP_USING_ADC + if BSP_USING_ADC + menuconfig BSP_USING_ADC12 + bool "Enable ADC12" + default n + if BSP_USING_ADC12 + config BSP_USING_ADC0 + bool "Enable ADC0" + default n + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + config BSP_USING_ADC2 + bool "Enable ADC2" + default n + endif + menuconfig BSP_USING_ADC16 + bool "Enable ADC16" + default n + if BSP_USING_ADC16 + config BSP_USING_ADC3 + bool "Enable ADC3" + default n + endif + endif + + menuconfig BSP_USING_CAMERA + bool "Enable camera" default n - select RT_USING_ADC if BSP_USING_ADC - if BSP_USING_ADC - menuconfig BSP_USING_ADC12 - bool "Enable ADC12" - default n - if BSP_USING_ADC12 - config BSP_USING_ADC0 - bool "Enable ADC0" - default n - config BSP_USING_ADC1 - bool "Enable ADC1" + if BSP_USING_CAMERA + config BSP_USING_CAMERA_MT9M114 + bool "Enable mt9m114" + default y + + config BSP_USING_CAMERA_OV5640 + bool "Enable ov5640" default n - config BSP_USING_ADC2 - bool "Enable ADC2" + + config BSP_USING_CAMERA_OV7725 + bool "Enable ov7725" default n - endif - menuconfig BSP_USING_ADC16 - bool "Enable ADC16" - default n - if BSP_USING_ADC16 - config BSP_USING_ADC3 - bool "Enable ADC3" - default n - endif + endif + + menuconfig BSP_USING_JPEG + bool "Enable JPEG Driver" + default n + + menuconfig BSP_USING_CAM + bool "Enable CAM Driver" + default n + + menuconfig BSP_USING_PANEL + bool "Enable panel" + default n + if BSP_USING_PANEL + config BSP_USEING_PANEL_RGB_TM070RDH13 + bool "Enable RGB TM070RDH13" + default y endif -endmenu + menuconfig BSP_USING_RTT_LCD_DRIVER + bool "Enable RTT LCD Driver" + select BSP_USING_LCD + default n +endmenu endmenu diff --git a/bsp/hpmicro/hpm6750evkmini/board/SConscript b/bsp/hpmicro/hpm6750evkmini/board/SConscript index 6245c5f443b..8e2285e89fc 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/SConscript +++ b/bsp/hpmicro/hpm6750evkmini/board/SConscript @@ -8,7 +8,6 @@ src = Split(""" rtt_board.c pinmux.c rw007_port.c - eth_phy_port.c fal_flash_port.c """) diff --git a/bsp/hpmicro/hpm6750evkmini/board/board.c b/bsp/hpmicro/hpm6750evkmini/board/board.c index de9188fdf06..57123938541 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/board.c +++ b/bsp/hpmicro/hpm6750evkmini/board/board.c @@ -20,9 +20,13 @@ #include "hpm_sdxc_drv.h" #include "hpm_sdxc_soc_drv.h" #include "hpm_pllctl_drv.h" +#include "hpm_pwm_drv.h" #include "hpm_pcfg_drv.h" +#include "hpm_enet_drv.h" + static board_timer_cb timer_cb; +static bool invert_led_level; /** * @brief FLASH configuration option definitions: @@ -81,24 +85,39 @@ static board_timer_cb timer_cb; __attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90001, 0x00000007, 0x0, 0x0}; #endif +#if defined(FLASH_UF2) && FLASH_UF2 +ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; +#endif + void board_init_console(void) { +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE #if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART console_config_t cfg; + /* uart needs to configure pin function before enabling clock, otherwise the level change of + uart rx pin when configuring pin function will cause a wrong data to be received. + And a uart rx dma request will be generated by default uart fifo dma trigger level. */ + init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE); + /* Configure the UART clock to 24MHz */ - clock_set_source_divider(BOARD_CONSOLE_CLK_NAME, clk_src_osc24m, 1U); + clock_set_source_divider(BOARD_CONSOLE_UART_CLK_NAME, clk_src_osc24m, 1U); + clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0); cfg.type = BOARD_CONSOLE_TYPE; - cfg.base = (uint32_t) BOARD_CONSOLE_BASE; - cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_CLK_NAME); - cfg.baudrate = BOARD_CONSOLE_BAUDRATE; + cfg.base = (uint32_t) BOARD_CONSOLE_UART_BASE; + cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_UART_CLK_NAME); + cfg.baudrate = BOARD_CONSOLE_UART_BAUDRATE; - init_uart_pins((UART_Type *) cfg.base); - - console_init(&cfg); + if (status_success != console_init(&cfg)) { + /* failed to initialize debug console */ + while (1) { + } + } #else - while(1); + while (1) { + } +#endif #endif } @@ -150,11 +169,17 @@ void board_print_banner(void) $$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\n\ \\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n\ ----------------------------------------------------------------------\n"}; +#ifdef SDK_VERSION_STRING + printf("hpm_sdk: %s\n", SDK_VERSION_STRING); +#endif printf("%s", banner); } static void board_turnoff_rgb_led(void) { + uint8_t port_pin18_status; + uint8_t port_pin19_status; + uint8_t port_pin20_status; uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_GPIO_B_18; HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_GPIO_B_19; @@ -163,6 +188,47 @@ static void board_turnoff_rgb_led(void) HPM_IOC->PAD[IOC_PAD_PB18].PAD_CTL = pad_ctl; HPM_IOC->PAD[IOC_PAD_PB19].PAD_CTL = pad_ctl; HPM_IOC->PAD[IOC_PAD_PB20].PAD_CTL = pad_ctl; + + port_pin18_status = gpio_read_pin(BOARD_G_GPIO_CTRL, GPIO_DI_GPIOB, 18); + port_pin19_status = gpio_read_pin(BOARD_G_GPIO_CTRL, GPIO_DI_GPIOB, 19); + port_pin20_status = gpio_read_pin(BOARD_G_GPIO_CTRL, GPIO_DI_GPIOB, 20); + invert_led_level = false; +/** + * hpm board evkmini Rev. B led light modification, resulting in two versions of rgb led processing different + * + */ + if ((port_pin18_status & port_pin19_status & port_pin20_status) == 0) { + /* Mini Rev B */ + invert_led_level = true; + pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(0); + HPM_IOC->PAD[IOC_PAD_PB18].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PB19].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PB20].PAD_CTL = pad_ctl; + } +} + +uint8_t board_get_led_pwm_off_level(void) +{ + if (invert_led_level) { + return BOARD_LED_ON_LEVEL; + } else { + return BOARD_LED_OFF_LEVEL; + } +} + +uint8_t board_get_led_gpio_off_level(void) +{ + if (invert_led_level) { + return BOARD_LED_ON_LEVEL; + } else { + return BOARD_LED_OFF_LEVEL; + } +} + +void board_ungate_mchtmr_at_lp_mode(void) +{ + /* Keep cpu clock on wfi, so that mchtmr irq can still work after wfi */ + sysctl_set_cpu_lp_mode(HPM_SYSCTL, BOARD_RUNNING_CORE, cpu_lp_mode_ungate_cpu_clock); } void board_init(void) @@ -180,6 +246,12 @@ void board_init(void) #endif } +void board_init_core1(void) +{ + board_init_console(); + board_init_pmp(); +} + void board_init_sdram_pins(void) { init_sdram_pins(); @@ -191,59 +263,107 @@ uint32_t board_init_femc_clock(void) return clock_get_frequency(clock_femc); } -void board_power_cycle_lcd(void) -{ - /* turn off backlight */ - gpio_set_pin_output(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN); - gpio_write_pin(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN, 0); +uint32_t board_lcdc_clock_init(clock_name_t clock_name, uint32_t pixel_clk_khz); - board_delay_ms(150); - /* power recycle */ - gpio_set_pin_output(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN); - gpio_write_pin(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN, 0); - board_delay_ms(20); - gpio_write_pin(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN, 1); - board_delay_ms(150); +#if defined(CONFIG_PANEL_RGB_TM070RDH13) && CONFIG_PANEL_RGB_TM070RDH13 - /* turn on backlight */ - gpio_write_pin(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN, 1); +static void set_reset_pin_level_tm070rdh13(uint8_t level) +{ + gpio_write_pin(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN, level); +} +static void set_backlight_tm070rdh13(uint16_t percent) +{ + gpio_write_pin(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN, percent > 0 ? 1 : 0); } -void board_init_lcd(void) +void board_init_lcd_rgb_tm070rdh13(void) { - board_init_lcd_clock(); init_lcd_pins(BOARD_LCD_BASE); - board_power_cycle_lcd(); + + gpio_set_pin_output(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN); + gpio_set_pin_output(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN); + + hpm_panel_hw_interface_t hw_if = {0}; + hpm_panel_t *panel = hpm_panel_find_device_default(); + const hpm_panel_timing_t *timing = hpm_panel_get_timing(panel); + uint32_t lcdc_pixel_clk_khz = board_lcdc_clock_init(clock_display, timing->pixel_clock_khz); + hw_if.set_reset_pin_level = set_reset_pin_level_tm070rdh13; + hw_if.set_backlight = set_backlight_tm070rdh13; + hw_if.lcdc_pixel_clk_khz = lcdc_pixel_clk_khz; + hpm_panel_register_interface(panel, &hw_if); + + printf("name: %s, lcdc_clk: %ukhz\n", + hpm_panel_get_name(panel), + lcdc_pixel_clk_khz); + + hpm_panel_reset(panel); + hpm_panel_init(panel); + hpm_panel_power_on(panel); } -void board_panel_para_to_lcdc(lcdc_config_t *config) +#endif + +#ifdef CONFIG_HPM_PANEL + +uint32_t board_lcdc_clock_init(clock_name_t clock_name, uint32_t pixel_clk_khz) { - const uint16_t panel_timing_para[] = BOARD_PANEL_TIMING_PARA; + clock_add_to_group(clock_name, 0); - config->resolution_x = BOARD_LCD_WIDTH; - config->resolution_y = BOARD_LCD_HEIGHT; + uint32_t freq_khz = clock_get_frequency(clk_pll4clk0) / 1000; + uint32_t div = (freq_khz + pixel_clk_khz / 2) / pixel_clk_khz; + clock_set_source_divider(clock_name, clk_src_pll4_clk0, div); + return clock_get_frequency(clock_name) / 1000; +} - config->hsync.pulse_width = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HSPW_INDEX]; - config->hsync.back_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HBP_INDEX]; - config->hsync.front_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HFP_INDEX]; +void board_lcd_backlight(bool is_on) +{ + hpm_panel_t *panel = hpm_panel_find_device_default(); + hpm_panel_set_backlight(panel, is_on == true ? 100 : 0); +} - config->vsync.pulse_width = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VSPW_INDEX]; - config->vsync.back_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VBP_INDEX]; - config->vsync.front_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VFP_INDEX]; +void board_init_lcd(void) +{ +#ifdef CONFIG_PANEL_RGB_TM070RDH13 + board_init_lcd_rgb_tm070rdh13(); +#endif +} - config->control.invert_hsync = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HSSP_INDEX]; - config->control.invert_vsync = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VSSP_INDEX]; - config->control.invert_href = panel_timing_para[BOARD_PANEL_TIMEING_PARA_DESP_INDEX]; - config->control.invert_pixel_data = panel_timing_para[BOARD_PANEL_TIMEING_PARA_PDSP_INDEX]; - config->control.invert_pixel_clock = panel_timing_para[BOARD_PANEL_TIMEING_PARA_PCSP_INDEX]; +void board_panel_para_to_lcdc(lcdc_config_t *config) +{ + const hpm_panel_timing_t *timing; + hpm_panel_t *panel = hpm_panel_find_device_default(); + + timing = hpm_panel_get_timing(panel); + config->resolution_x = timing->hactive; + config->resolution_y = timing->vactive; + + config->hsync.pulse_width = timing->hsync_len; + config->hsync.back_porch_pulse = timing->hback_porch; + config->hsync.front_porch_pulse = timing->hfront_porch; + + config->vsync.pulse_width = timing->vsync_len; + config->vsync.back_porch_pulse = timing->vback_porch; + config->vsync.front_porch_pulse = timing->vfront_porch; + + config->control.invert_hsync = timing->hsync_pol; + config->control.invert_vsync = timing->vsync_pol; + config->control.invert_href = timing->de_pol; + config->control.invert_pixel_data = timing->pixel_data_pol; + config->control.invert_pixel_clock = timing->pixel_clk_pol; } +#endif void board_delay_ms(uint32_t ms) { clock_cpu_delay_ms(ms); } +void board_delay_us(uint32_t us) +{ + clock_cpu_delay_us(us); +} + void board_timer_isr(void) { if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) { @@ -253,12 +373,12 @@ void board_timer_isr(void) } SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr); -void board_timer_create(uint32_t ms, void *cb) +void board_timer_create(uint32_t ms, board_timer_cb cb) { uint32_t gptmr_freq; gptmr_channel_config_t config; - timer_cb = (board_timer_cb)cb; + timer_cb = cb; gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config); clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0); @@ -280,7 +400,8 @@ void board_i2c_bus_clear(I2C_Type *ptr) gpio_set_pin_input(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN); if (!gpio_read_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN)) { printf("CLK is low, please power cycle the board\n"); - while (1) {} + while (1) { + } } if (!gpio_read_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_SDA_GPIO_INDEX, BOARD_CAP_I2C_SDA_GPIO_PIN)) { printf("SDA is low, try to issue I2C bus clear\n"); @@ -324,8 +445,9 @@ void board_init_i2c(I2C_Type *ptr) freq = clock_get_frequency(BOARD_CAP_I2C_CLK_NAME); stat = i2c_init_master(BOARD_CAP_I2C_BASE, freq, &config); if (stat != status_success) { - printf("failed to initialize i2c 0x%lx\n", BOARD_CAP_I2C_BASE); - while (1) {} + printf("failed to initialize i2c 0x%x\n", (uint32_t) BOARD_CAP_I2C_BASE); + while (1) { + } } } @@ -444,25 +566,44 @@ void board_init_spi_pins(SPI_Type *ptr) init_spi_pins(ptr); } +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + init_spi_pins_with_gpio_as_cs(ptr); + gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN), + GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL); +} + +void board_write_spi_cs(uint32_t pin, uint8_t state) +{ + gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state); +} + void board_init_led_pins(void) { + board_turnoff_rgb_led(); init_led_pins_as_gpio(); - gpio_set_pin_output_with_initial(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_OFF_LEVEL); - gpio_set_pin_output_with_initial(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_OFF_LEVEL); - gpio_set_pin_output_with_initial(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_OFF_LEVEL); + gpio_set_pin_output_with_initial(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, board_get_led_gpio_off_level()); + gpio_set_pin_output_with_initial(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, board_get_led_gpio_off_level()); + gpio_set_pin_output_with_initial(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, board_get_led_gpio_off_level()); } void board_led_toggle(void) { static uint8_t i; - gpio_write_port(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, (7 & ~(1 << i)) << BOARD_G_GPIO_PIN); + if (!invert_led_level) { + /* hpm6750 Mini Rev A led configure*/ + gpio_write_port(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, (7 & ~(1 << i)) << BOARD_G_GPIO_PIN); + } else { + /* hpm6750 Mini Rev B led configure*/ + gpio_write_port(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, ((1 << i)) << BOARD_G_GPIO_PIN); + } i++; i = i % 3; } -void board_led_write(bool state) +void board_led_write(uint8_t state) { - gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state ? BOARD_LED_ON_LEVEL : BOARD_LED_OFF_LEVEL); + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state); } void board_init_cam_pins(void) @@ -472,56 +613,63 @@ void board_init_cam_pins(void) void board_init_usb_pins(void) { - /* set pull-up for USBx OC pins */ + /* set pull-up for USBx OC pin and ID pin */ init_usb_pins(HPM_USB0); - /* configure USBx OC Flag pins as input function */ + /* configure USBx ID pin as input function */ + gpio_set_pin_input(BOARD_USB0_ID_PORT, BOARD_USB0_ID_GPIO_INDEX, BOARD_USB0_ID_GPIO_PIN); + + /* configure USBx OC Flag pin as input function */ gpio_set_pin_input(BOARD_USB0_OC_PORT, BOARD_USB0_OC_GPIO_INDEX, BOARD_USB0_OC_GPIO_PIN); } void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level) { + (void) usb_index; + (void) level; } void board_init_pmp(void) { + uint32_t start_addr; + uint32_t end_addr; + uint32_t length; + pmp_entry_t pmp_entry[16]; + uint8_t index = 0; + + /* Init noncachable memory */ extern uint32_t __noncacheable_start__[]; extern uint32_t __noncacheable_end__[]; - - uint32_t start_addr = (uint32_t) __noncacheable_start__; - uint32_t end_addr = (uint32_t) __noncacheable_end__; - uint32_t length = end_addr - start_addr; - - if (length == 0) { - return; + start_addr = (uint32_t) __noncacheable_start__; + end_addr = (uint32_t) __noncacheable_end__; + length = end_addr - start_addr; + if (length > 0) { + /* Ensure the address and the length are power of 2 aligned */ + assert((length & (length - 1U)) == 0U); + assert((start_addr & (length - 1U)) == 0U); + pmp_entry[index].pmp_addr = PMP_NAPOT_ADDR(start_addr, length); + pmp_entry[index].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK); + pmp_entry[index].pma_addr = PMA_NAPOT_ADDR(start_addr, length); + pmp_entry[index].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN); + index++; } - /* Ensure the address and the length are power of 2 aligned */ - assert((length & (length - 1U)) == 0U); - assert((start_addr & (length - 1U)) == 0U); - - pmp_entry_t pmp_entry[1]; - pmp_entry[0].pmp_addr = PMP_NAPOT_ADDR(start_addr, length); - pmp_entry[0].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK); - pmp_entry[0].pma_addr = PMA_NAPOT_ADDR(start_addr, length); - pmp_entry[0].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN); - - pmp_config(&pmp_entry[0], ARRAY_SIZE(pmp_entry)); + pmp_config(&pmp_entry[0], index); } void board_init_clock(void) { uint32_t cpu0_freq = clock_get_frequency(clock_cpu0); - hpm_core_clock = cpu0_freq; if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) { /* Configure the External OSC ramp-up time: ~9ms */ - HPM_PLLCTL->XTAL = PLLCTL_XTAL_RAMP_TIME_SET(32UL * 1000UL * 9U); + pllctl_xtal_set_rampup_time(HPM_PLLCTL, 32UL * 1000UL * 9U); /* Select clock setting preset1 */ sysctl_clock_set_preset(HPM_SYSCTL, sysctl_preset_1); } /* Add most Clocks to group 0 */ + /* not open uart clock in this API, uart should configure pin function before opening clock */ clock_add_to_group(clock_cpu0, 0); clock_add_to_group(clock_mchtmr0, 0); clock_add_to_group(clock_axi0, 0); @@ -584,6 +732,7 @@ void board_init_clock(void) clock_add_to_group(clock_msyn, 0); clock_add_to_group(clock_lmm0, 0); clock_add_to_group(clock_lmm1, 0); + clock_add_to_group(clock_pdm, 0); clock_add_to_group(clock_adc0, 0); clock_add_to_group(clock_adc1, 0); @@ -594,7 +743,6 @@ void board_init_clock(void) clock_add_to_group(clock_i2s1, 0); clock_add_to_group(clock_i2s2, 0); clock_add_to_group(clock_i2s3, 0); - /* Connect Group0 to CPU0 */ clock_connect_group_to_cpu(0, 0); @@ -606,16 +754,21 @@ void board_init_clock(void) /* Bump up DCDC voltage to 1200mv */ pcfg_dcdc_set_voltage(HPM_PCFG, 1200); + pcfg_dcdc_switch_to_dcm_mode(HPM_PCFG); if (status_success != pllctl_init_int_pll_with_freq(HPM_PLLCTL, 0, BOARD_CPU_FREQ)) { printf("Failed to set pll0_clk0 to %luHz\n", BOARD_CPU_FREQ); - while(1); + while (1) { + } } clock_set_source_divider(clock_cpu0, clk_src_pll0_clk0, 1); clock_set_source_divider(clock_cpu1, clk_src_pll0_clk0, 1); - /* Connect Group1 to CPU1 */ - clock_connect_group_to_cpu(1, 1); + clock_update_core_clock(); + + clock_set_source_divider(clock_ahb, clk_src_pll1_clk1, 2); /*200m hz*/ + clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1); + clock_set_source_divider(clock_mchtmr1, clk_src_osc24m, 1); } uint32_t board_init_cam_clock(CAM_Type *ptr) @@ -640,47 +793,17 @@ uint32_t board_init_lcd_clock(void) uint32_t freq; clock_add_to_group(clock_display, 0); /* Configure LCDC clock to 29.7MHz */ - clock_set_source_divider(clock_display, clock_source_pll4_clk0, 20U); + clock_set_source_divider(clock_display, clk_src_pll4_clk0, 20U); freq = clock_get_frequency(clock_display); return freq; } -uint32_t board_init_adc12_clock(ADC12_Type *ptr) -{ - uint32_t freq = 0; - switch ((uint32_t) ptr) { - case HPM_ADC0_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc0, clk_adc_src_ana0); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); - freq = clock_get_frequency(clock_adc0); - break; - case HPM_ADC1_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc1, clk_adc_src_ana0); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); - freq = clock_get_frequency(clock_adc1); - break; - case HPM_ADC2_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc2, clk_adc_src_ana0); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); - freq = clock_get_frequency(clock_adc2); - break; - default: - /* Invalid ADC instance */ - break; - } - - return freq; -} - uint32_t board_init_dao_clock(void) { clock_add_to_group(clock_dao, 0); - sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); - sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud0_clk); + sysctl_config_clock(HPM_SYSCTL, clock_node_aud1, clock_source_pll3_clk0, 25); + sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud1_clk); return clock_get_frequency(clock_dao); } @@ -695,27 +818,134 @@ uint32_t board_init_pdm_clock(void) return clock_get_frequency(clock_pdm); } +hpm_stat_t board_set_audio_pll_clock(uint32_t freq) +{ + return pllctl_init_frac_pll_with_freq(HPM_PLLCTL, 3, freq); /* pll3clk */ +} + +void board_init_i2s_pins(I2S_Type *ptr) +{ + init_i2s_pins(ptr); +} + uint32_t board_init_i2s_clock(I2S_Type *ptr) { + uint32_t freq = 0; + if (ptr == HPM_I2S0) { clock_add_to_group(clock_i2s0, 0); sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk); - return clock_get_frequency(clock_i2s0); + freq = clock_get_frequency(clock_i2s0); + } else if (ptr == HPM_I2S1) { + clock_add_to_group(clock_i2s1, 0); + + sysctl_config_clock(HPM_SYSCTL, clock_node_aud1, clock_source_pll3_clk0, 25); + sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud1_clk); + + freq = clock_get_frequency(clock_i2s1); + } else { + ; + } + + return freq; +} + +/* adjust I2S source clock base on sample rate */ +uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate) +{ + uint32_t freq = 0; + + if (ptr == HPM_I2S0) { + clock_add_to_group(clock_i2s0, 0); + if ((sample_rate % 22050) == 0) { + clock_set_source_divider(clock_aud0, clk_src_pll3_clk0, 54); /* config clock_aud1 for 22050*n sample rate */ + } else { + clock_set_source_divider(clock_aud0, clk_src_pll3_clk0, 25); /* config clock_aud0 for 8000*n sample rate */ + } + clock_set_i2s_source(clock_i2s0, clk_i2s_src_aud0); + freq = clock_get_frequency(clock_i2s0); + } else if (ptr == HPM_I2S1) { + clock_add_to_group(clock_i2s1, 0); + if ((sample_rate % 22050) == 0) { + clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 54); /* config clock_aud1 for 22050*n sample rate */ + } else { + clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 25); /* config clock_aud0 for 8000*n sample rate */ + } + clock_set_i2s_source(clock_i2s1, clk_i2s_src_aud1); + freq = clock_get_frequency(clock_i2s1); } else { - return 0; + ; + } + + return freq; +} + +void board_init_adc12_pins(void) +{ + init_adc12_pins(); +} + +void board_init_adc16_pins(void) +{ + init_adc16_pins(); +} + +uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb) +{ + uint32_t freq = 0; + + if (ptr == HPM_ADC0) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + } + freq = clock_get_frequency(clock_adc0); + } else if (ptr == HPM_ADC1) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc1, clk_adc_src_ana1); + clock_set_source_divider(clock_ana1, clk_src_pll1_clk1, 2U); + } + freq = clock_get_frequency(clock_adc1); + } else if (ptr == HPM_ADC2) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc2, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc2, clk_adc_src_ana2); + clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U); + } + freq = clock_get_frequency(clock_adc2); } + + return freq; } -uint32_t board_init_adc16_clock(ADC16_Type *ptr) +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) { uint32_t freq = 0; + if (ptr == HPM_ADC3) { - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc3, clk_adc_src_ana1); - clock_set_source_divider(clock_ana1, clk_src_pll1_clk1, 2U); + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc3, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc3, clk_adc_src_ana2); + clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U); + } + freq = clock_get_frequency(clock_adc3); } @@ -752,6 +982,27 @@ uint32_t board_init_can_clock(CAN_Type *ptr) return freq; } +uint32_t board_init_pwm_clock(PWM_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_PWM0) { + clock_add_to_group(clock_mot0, 0); + freq = clock_get_frequency(clock_mot0); + } else if (ptr == HPM_PWM1) { + clock_add_to_group(clock_mot1, 0); + freq = clock_get_frequency(clock_mot1); + } else if (ptr == HPM_PWM2) { + clock_add_to_group(clock_mot2, 0); + freq = clock_get_frequency(clock_mot2); + } else if (ptr == HPM_PWM3) { + clock_add_to_group(clock_mot3, 0); + freq = clock_get_frequency(clock_mot3); + } else { + + } + return freq; +} + uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) { uint32_t freq = 0; @@ -799,6 +1050,7 @@ uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) else { /* Invalid instance */ } + return freq; } /* @@ -815,7 +1067,6 @@ void _init_ext_ram(void) femc_sdram_config_t sdram_config = {0}; femc_default_config(HPM_FEMC, &config); - config.dqs = FEMC_DQS_INTERNAL; femc_init(HPM_FEMC, &config); sdram_config.bank_num = FEMC_SDRAM_BANK_NUM_4; @@ -845,43 +1096,19 @@ void _init_ext_ram(void) sdram_config.refresh_count = BOARD_SDRAM_REFRESH_COUNT; sdram_config.refresh_in_ms = BOARD_SDRAM_REFRESH_IN_MS; sdram_config.data_width_in_byte = BOARD_SDRAM_DATA_WIDTH_IN_BYTE; - sdram_config.delay_cell_value = 29; + sdram_config.delay_cell_disable = true; + sdram_config.delay_cell_value = 0; femc_config_sdram(HPM_FEMC, femc_clk_in_hz, &sdram_config); } -void board_init_sd_pins(SDXC_Type *ptr) -{ - if (ptr == HPM_SDXC1) { - init_sdxc_pins(ptr, false); - init_sdxc_card_detection_pin(ptr); - init_sdxc_vsel_pin(ptr); - } else { - while (1) { - - } - } -} void board_sd_power_switch(SDXC_Type *ptr, bool on_off) { /* This feature is not supported by current board*/ } -void board_sd_switch_pins_to_1v8(SDXC_Type *ptr) -{ - sdxc_switch_to_1v8_signal(ptr, true); - init_sdxc_pins(ptr, true); -} - -bool board_sd_detect_card(SDXC_Type *ptr) -{ - return sdxc_is_card_inserted(ptr); -} - - - -uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq) +uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inverse) { uint32_t actual_freq = 0; do { @@ -896,26 +1123,28 @@ uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq) clock_set_source_divider(sdxc_clk, clk_src_osc24m, 63); } /* configure the clock to 24MHz for the SDR12/Default speed */ - else if (freq <= 25000000UL) { + else if (freq <= 26000000UL) { clock_set_source_divider(sdxc_clk, clk_src_osc24m, 1); } /* Configure the clock to 50MHz for the SDR25/High speed/50MHz DDR/50MHz SDR */ - else if (freq <= 50000000UL) { + else if (freq <= 52000000UL) { clock_set_source_divider(sdxc_clk, clk_src_pll1_clk1, 8); } /* Configure the clock to 100MHz for the SDR50 */ else if (freq <= 100000000UL) { clock_set_source_divider(sdxc_clk, clk_src_pll1_clk1, 4); } - /* Configure the clock to 166MHz for SDR104/HS200/HS400 */ + /* Configure the clock to 133MHz for SDR104/HS200/HS400 */ else if (freq <= 208000000UL) { - clock_set_source_divider(sdxc_clk, clk_src_pll2_clk0, 2); + clock_set_source_divider(sdxc_clk, clk_src_pll1_clk1, 3); } /* For other unsupported clock ranges, configure the clock to 24MHz */ else { clock_set_source_divider(sdxc_clk, clk_src_osc24m, 1); } - sdxc_enable_inverse_clock(ptr, true); + if (need_inverse) { + sdxc_enable_inverse_clock(ptr, true); + } sdxc_enable_sd_clock(ptr, true); actual_freq = clock_get_frequency(sdxc_clk); } while (false); @@ -923,14 +1152,90 @@ uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq) return actual_freq; } + +static void set_rgb_output_off(PWM_Type *ptr, uint8_t pin, uint8_t cmp_index) +{ + pwm_cmp_config_t cmp_config = {0}; + pwm_output_channel_t ch_config = {0}; + + pwm_stop_counter(ptr); + pwm_get_default_cmp_config(ptr, &cmp_config); + pwm_get_default_output_channel_config(ptr, &ch_config); + + pwm_set_reload(ptr, 0, 0xF); + pwm_set_start_count(ptr, 0, 0); + + cmp_config.mode = pwm_cmp_mode_output_compare; + cmp_config.cmp = 0x10; + cmp_config.update_trigger = pwm_shadow_register_update_on_modify; + pwm_config_cmp(ptr, cmp_index, &cmp_config); + + ch_config.cmp_start_index = cmp_index; + ch_config.cmp_end_index = cmp_index; + ch_config.invert_output = !board_get_led_pwm_off_level(); + + pwm_config_output_channel(ptr, pin, &ch_config); +} + +void board_init_rgb_pwm_pins(void) +{ + board_turnoff_rgb_led(); + + set_rgb_output_off(BOARD_RED_PWM, BOARD_RED_PWM_OUT, BOARD_RED_PWM_CMP); + set_rgb_output_off(BOARD_GREEN_PWM, BOARD_GREEN_PWM_OUT, BOARD_GREEN_PWM_CMP); + set_rgb_output_off(BOARD_BLUE_PWM, BOARD_BLUE_PWM_OUT, BOARD_BLUE_PWM_CMP); + + init_led_pins_as_pwm(); +} + +void board_disable_output_rgb_led(uint8_t color) +{ + switch (color) { + case BOARD_RGB_RED: + pwm_disable_output(BOARD_RED_PWM, BOARD_RED_PWM_OUT); + break; + case BOARD_RGB_GREEN: + pwm_disable_output(BOARD_GREEN_PWM, BOARD_GREEN_PWM_OUT); + break; + case BOARD_RGB_BLUE: + pwm_disable_output(BOARD_BLUE_PWM, BOARD_BLUE_PWM_OUT); + break; + default: + while (1) { + ; + } + } +} + +void board_enable_output_rgb_led(uint8_t color) +{ + switch (color) { + case BOARD_RGB_RED: + pwm_enable_output(BOARD_RED_PWM, BOARD_RED_PWM_OUT); + break; + case BOARD_RGB_GREEN: + pwm_enable_output(BOARD_GREEN_PWM, BOARD_GREEN_PWM_OUT); + break; + case BOARD_RGB_BLUE: + pwm_enable_output(BOARD_BLUE_PWM, BOARD_BLUE_PWM_OUT); + break; + default: + while (1) { + ; + } + } +} + +void board_init_beep_pwm_pins(void) +{ + init_beep_pwm_pins(); +} + hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr) { - /* set clock source */ if (ptr == HPM_ENET0) { - /* make sure pll0_clk0 output clock at 400MHz to get a clock at 100MHz for the enet0 ptp function */ clock_set_source_divider(clock_ptp0, clk_src_pll1_clk1, 4); /* 100MHz */ } else if (ptr == HPM_ENET1) { - /* make sure pll0_clk0 output clock at 400MHz to get a clock at 100MHz for the enet1 ptp function */ clock_set_source_divider(clock_ptp1, clk_src_pll1_clk1, 4); /* 100MHz */ } else { return status_invalid_argument; @@ -941,31 +1246,26 @@ hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr) hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) { - if (internal == false) { - return status_success; - } - /* Configure Enet clock to output reference clock */ - if (ptr == HPM_ENET0) { - /* make sure pll2_clk1 output clock at 250MHz then set 50MHz for enet0 */ - clock_set_source_divider(clock_eth0, clk_src_pll2_clk1, 5); - } else if (ptr == HPM_ENET1) { - /* make sure pll2_clk1 output clock at 250MHz then set 50MHz for enet1 */ - clock_set_source_divider(clock_eth1, clk_src_pll2_clk1, 5); /* set 50MHz for enet1 */ + if (ptr == HPM_ENET0 || ptr == HPM_ENET1) { + if (internal) { + /* set pll output frequency at 1GHz */ + if (pllctl_init_int_pll_with_freq(HPM_PLLCTL, PLLCTL_PLL_PLL2, 1000000000UL) == status_success) { + /* set pll2_clk1 output frequence at 250MHz from PLL2 divided by 4 */ + pllctl_set_div(HPM_PLLCTL, PLLCTL_PLL_PLL2, 1, 4); + /* set eth clock frequency at 50MHz for enet0 */ + clock_set_source_divider(ptr == HPM_ENET0 ? clock_eth0 : clock_eth1, clk_src_pll2_clk1, 5); + } else { + return status_fail; + } + } } else { return status_invalid_argument; } - return status_success; -} -void board_init_rgb_pwm_pins(void) -{ - init_led_pins_as_pwm(); -} + enet_rmii_enable_clock(ptr, internal); -void board_init_beep_pwm_pins(void) -{ - init_beep_pwm_pins(); + return status_success; } hpm_stat_t board_init_enet_pins(ENET_Type *ptr) @@ -973,7 +1273,7 @@ hpm_stat_t board_init_enet_pins(ENET_Type *ptr) init_enet_pins(ptr); if (ptr == HPM_ENET1) { - gpio_set_pin_output_with_initial(BOARD_ENET1_RST_GPIO, BOARD_ENET1_RST_GPIO_INDEX, BOARD_ENET1_RST_GPIO_PIN, 0); + gpio_set_pin_output_with_initial(BOARD_ENET_RMII_RST_GPIO, BOARD_ENET_RMII_RST_GPIO_INDEX, BOARD_ENET_RMII_RST_GPIO_PIN, 0); } else { return status_invalid_argument; } @@ -984,9 +1284,9 @@ hpm_stat_t board_init_enet_pins(ENET_Type *ptr) hpm_stat_t board_reset_enet_phy(ENET_Type *ptr) { if (ptr == HPM_ENET1) { - gpio_write_pin(BOARD_ENET1_RST_GPIO, BOARD_ENET1_RST_GPIO_INDEX, BOARD_ENET1_RST_GPIO_PIN, 0); - board_delay_ms(BOARD_ENET1_PHY_RST_TIME); - gpio_write_pin(BOARD_ENET1_RST_GPIO, BOARD_ENET1_RST_GPIO_INDEX, BOARD_ENET1_RST_GPIO_PIN, 1); + gpio_write_pin(BOARD_ENET_RMII_RST_GPIO, BOARD_ENET_RMII_RST_GPIO_INDEX, BOARD_ENET_RMII_RST_GPIO_PIN, 0); + board_delay_ms(1); + gpio_write_pin(BOARD_ENET_RMII_RST_GPIO, BOARD_ENET_RMII_RST_GPIO_INDEX, BOARD_ENET_RMII_RST_GPIO_PIN, 1); } else { return status_invalid_argument; } @@ -994,7 +1294,31 @@ hpm_stat_t board_reset_enet_phy(ENET_Type *ptr) return status_success; } -uint8_t board_enet_get_dma_pbl(ENET_Type *ptr) +uint8_t board_get_enet_dma_pbl(ENET_Type *ptr) { + (void) ptr; return enet_pbl_32; } + +hpm_stat_t board_enable_enet_irq(ENET_Type *ptr) +{ + (void) ptr; + return status_success; +} + +hpm_stat_t board_disable_enet_irq(ENET_Type *ptr) +{ + (void) ptr; + return status_success; +} + +void board_init_enet_pps_pins(ENET_Type *ptr) +{ + (void) ptr; + init_enet_pps_pins(); +} + +void board_init_dao_pins(void) +{ + init_dao_pins(); +} diff --git a/bsp/hpmicro/hpm6750evkmini/board/board.h b/bsp/hpmicro/hpm6750evkmini/board/board.h index 57820cb8bb4..c86e7704341 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/board.h +++ b/bsp/hpmicro/hpm6750evkmini/board/board.h @@ -12,166 +12,215 @@ #include "hpm_soc.h" #include "hpm_soc_feature.h" #include "hpm_clock_drv.h" -#include "hpm_enet_drv.h" -#include "hpm_otp_drv.h" -#include "hpm_lcdc_drv.h" #include "pinmux.h" +#include "hpm_lcdc_drv.h" +#ifdef CONFIG_HPM_PANEL +#include "hpm_panel.h" +#endif +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#include "hpm_debug_console.h" +#endif -#define BOARD_NAME "hpm6750evkmini" +#define BOARD_NAME "hpm6750evkmini" +#define BOARD_UF2_SIGNATURE (0x0A4D5048UL) + +#define SEC_CORE_IMG_START ILM_LOCAL_BASE -/* uart section */ #ifndef BOARD_RUNNING_CORE #define BOARD_RUNNING_CORE HPM_CORE0 #endif + +/* uart section */ #ifndef BOARD_APP_UART_BASE -#define BOARD_APP_UART_BASE HPM_UART0 -#define BOARD_APP_UART_IRQ IRQn_UART0 -#else -#ifndef BOARD_APP_UART_IRQ -#warning no IRQ specified for applicaiton uart +#define BOARD_APP_UART_BASE HPM_UART13 +#define BOARD_APP_UART_IRQ IRQn_UART13 +#define BOARD_APP_UART_BAUDRATE (115200UL) +#define BOARD_APP_UART_CLK_NAME clock_uart13 +#define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART13_RX +#define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART13_TX #endif -#endif - -#define BOARD_APP_UART_BAUDRATE (115200UL) -#define BOARD_APP_UART_CLK_NAME clock_uart0 +/* uart rx idle demo section */ +#define BOARD_UART_IDLE BOARD_APP_UART_BASE +#define BOARD_UART_IDLE_IRQ BOARD_APP_UART_IRQ +#define BOARD_UART_IDLE_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_UART_IDLE_TX_DMA_SRC BOARD_APP_UART_TX_DMA_REQ +#define BOARD_UART_IDLE_DMA_SRC BOARD_APP_UART_RX_DMA_REQ + +#define BOARD_UART_IDLE_TRGM HPM_TRGM2 +#define BOARD_UART_IDLE_TRGM_PIN IOC_PAD_PD19 +#define BOARD_UART_IDLE_TRGM_INPUT_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P9 +#define BOARD_UART_IDLE_TRGM_OUTPUT_GPTMR_IN HPM_TRGM2_OUTPUT_SRC_GPTMR4_IN2 +#define BOARD_UART_IDLE_TRGM_OUTPUT_GPTMR_SYNCI HPM_TRGM2_OUTPUT_SRC_GPTMR4_SYNCI + +#define BOARD_UART_IDLE_GPTMR HPM_GPTMR4 +#define BOARD_UART_IDLE_GPTMR_CLK_NAME clock_gptmr4 +#define BOARD_UART_IDLE_GPTMR_IRQ IRQn_GPTMR4 +#define BOARD_UART_IDLE_GPTMR_CMP_CH 0 +#define BOARD_UART_IDLE_GPTMR_CAP_CH 2 + +/* uart microros sample section */ +#define BOARD_MICROROS_UART_BASE BOARD_APP_UART_BASE +#define BOARD_MICROROS_UART_IRQ BOARD_APP_UART_IRQ +#define BOARD_MICROROS_UART_CLK_NAME BOARD_APP_UART_CLK_NAME + +/* rtthread-nano finsh section */ +#define BOARD_RT_CONSOLE_BASE BOARD_CONSOLE_UART_BASE + +/* usb cdc acm uart section */ +#define BOARD_USB_CDC_ACM_UART BOARD_APP_UART_BASE +#define BOARD_USB_CDC_ACM_UART_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_USB_CDC_ACM_UART_TX_DMA_SRC BOARD_APP_UART_TX_DMA_REQ +#define BOARD_USB_CDC_ACM_UART_RX_DMA_SRC BOARD_APP_UART_RX_DMA_REQ + +/* modbus sample section */ +#define BOARD_MODBUS_UART_BASE BOARD_APP_UART_BASE +#define BOARD_MODBUS_UART_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_MODBUS_UART_RX_DMA_REQ BOARD_APP_UART_RX_DMA_REQ +#define BOARD_MODBUS_UART_TX_DMA_REQ BOARD_APP_UART_TX_DMA_REQ + +/* uart lin sample section */ +#define BOARD_UART_LIN BOARD_APP_UART_BASE +#define BOARD_UART_LIN_IRQ BOARD_APP_UART_IRQ +#define BOARD_UART_LIN_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_UART_LIN_TX_PORT GPIO_DI_GPIOZ +#define BOARD_UART_LIN_TX_PIN (9U) /* PC03 should align with used pin in pinmux configuration */ + +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE #ifndef BOARD_CONSOLE_TYPE #define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART #endif #if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART -#define BOARD_CONSOLE_BASE HPM_UART0 -#define BOARD_CONSOLE_CLK_NAME clock_uart0 -#define BOARD_CONSOLE_BAUDRATE (115200UL) +#ifndef BOARD_CONSOLE_UART_BASE +#if BOARD_RUNNING_CORE == HPM_CORE0 +#define BOARD_CONSOLE_UART_BASE HPM_UART0 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART0 +#define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX +#define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX +#else +#define BOARD_CONSOLE_UART_BASE HPM_UART13 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart13 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART13 +#define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART13_TX +#define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART13_RX #endif - -#define BOARD_FREEMASTER_UART_BASE HPM_UART0 -#define BOARD_FREEMASTER_UART_IRQ IRQn_UART0 -#define BOARD_FREEMASTER_UART_CLK_NAME clock_uart0 - -/* sdram section */ -#define BOARD_SDRAM_ADDRESS (0x40000000UL) -#define BOARD_SDRAM_SIZE (16*SIZE_1MB) -#define BOARD_SDRAM_CS FEMC_SDRAM_CS0 -#define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_16_BITS -#define BOARD_SDRAM_REFRESH_COUNT (4096UL) -#define BOARD_SDRAM_REFRESH_IN_MS (64UL) -#define BOARD_SDRAM_DATA_WIDTH_IN_BYTE (2UL) - -/* lcd section */ -/* - * BOARD_PANEL_TIMING_PARA {HSPW, HBP, HFP, VSPW, VBP, VFP, HSSP, VSSP, DESP, PDSP, PCSP} - * - * HSPW: Horizontal Synchronization Pulse width - * HBP: Horizontal Back Porch - * HFP: Horizontal Front Porch - * VSPW: Vertical Synchronization Pulse width - * VBP: Vertical Back Porch - * VFP: Vertical Front Porch - * HSSP: Horizontal Synchronization Signal Polarity, 0: High Active, 1: Low Active - * VSSP: Vertical Synchronization Signal Polarity, 0: High Active, 1: Low Active - * DESP: Data Enable Signal Polarity, 0: High Active, 1: Low Active - * PDSP: Pixel Data Signal Polarity, 0: High Active, 1: Low Active - * PCSP: Pixel Clock Signal Polarity, 0: High Active, 1: Low Active - */ -#define BOARD_PANEL_TIMEING_PARA_HSPW_INDEX 0 -#define BOARD_PANEL_TIMEING_PARA_HBP_INDEX 1 -#define BOARD_PANEL_TIMEING_PARA_HFP_INDEX 2 -#define BOARD_PANEL_TIMEING_PARA_VSPW_INDEX 3 -#define BOARD_PANEL_TIMEING_PARA_VBP_INDEX 4 -#define BOARD_PANEL_TIMEING_PARA_VFP_INDEX 5 -#define BOARD_PANEL_TIMEING_PARA_HSSP_INDEX 6 -#define BOARD_PANEL_TIMEING_PARA_VSSP_INDEX 7 -#define BOARD_PANEL_TIMEING_PARA_DESP_INDEX 8 -#define BOARD_PANEL_TIMEING_PARA_PDSP_INDEX 9 -#define BOARD_PANEL_TIMEING_PARA_PCSP_INDEX 10 - -#if defined(PANEL_TM070RDH13) - -#ifndef BOARD_LCD_WIDTH -#define BOARD_LCD_WIDTH 800 #endif -#ifndef BOARD_LCD_HEIGHT -#define BOARD_LCD_HEIGHT 480 +#define BOARD_CONSOLE_UART_BAUDRATE (115200UL) #endif -#ifndef BOARD_PANEL_TIMING_PARA -#define BOARD_PANEL_TIMING_PARA {10, 46, 50, 3, 23, 10, 0, 0, 0, 0, 0} #endif -#else +/* sdram section */ +#define BOARD_SDRAM_ADDRESS (0x40000000UL) +#define BOARD_SDRAM_SIZE (16 * SIZE_1MB) +#define BOARD_SDRAM_CS FEMC_SDRAM_CS0 +#define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_16_BITS +#define BOARD_SDRAM_REFRESH_COUNT (4096UL) +#define BOARD_SDRAM_REFRESH_IN_MS (64UL) +#define BOARD_SDRAM_DATA_WIDTH_IN_BYTE (2UL) -#ifndef BOARD_LCD_WIDTH -#define BOARD_LCD_WIDTH 800 -#endif -#ifndef BOARD_LCD_HEIGHT -#define BOARD_LCD_HEIGHT 480 -#endif -#ifndef BOARD_PANEL_TIMING_PARA -#define BOARD_PANEL_TIMING_PARA {10, 46, 50, 3, 23, 10, 0, 0, 0, 0, 0} -#endif +#define BOARD_FEMC_DQS_FLOATING 1 -#endif +/* lcd section */ +#define BOARD_LCD_BASE HPM_LCDC +#define BOARD_LCD_IRQ IRQn_LCDC_D0 +#define BOARD_LCD_POWER_GPIO_BASE HPM_GPIO0 +#define BOARD_LCD_POWER_GPIO_INDEX GPIO_DO_GPIOB +#define BOARD_LCD_POWER_GPIO_PIN 12 +#define BOARD_LCD_BACKLIGHT_GPIO_BASE HPM_GPIO0 +#define BOARD_LCD_BACKLIGHT_GPIO_INDEX GPIO_DO_GPIOB +#define BOARD_LCD_BACKLIGHT_GPIO_PIN 23 /* i2c section */ -#define BOARD_APP_I2C_BASE HPM_I2C0 -#define BOARD_APP_I2C_IRQ IRQn_I2C0 +#define BOARD_APP_I2C_BASE HPM_I2C0 +#define BOARD_APP_I2C_IRQ IRQn_I2C0 +#define BOARD_APP_I2C_IRQ IRQn_I2C0 #define BOARD_APP_I2C_CLK_NAME clock_i2c0 +#define BOARD_APP_I2C_DMA HPM_HDMA +#define BOARD_APP_I2C_DMAMUX HPM_DMAMUX +#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0 -#define BOARD_APP_I2C_SLAVE_BASE HPM_I2C3 -#define BOARD_APP_I2C_SLAVE_IRQ IRQn_I2C3 -#define BOARD_APP_I2C_SLAVE_CLK_NAME clock_i2c3 - -#define BOARD_CAM_I2C_BASE HPM_I2C0 +#define BOARD_CAM_I2C_BASE HPM_I2C0 #define BOARD_CAM_I2C_CLK_NAME clock_i2c0 -#define BOARD_CAP_I2C_BASE (HPM_I2C0) -#define BOARD_CAP_I2C_CLK_NAME clock_i2c0 -#define BOARD_CAP_RST_GPIO (HPM_GPIO0) -#define BOARD_CAP_RST_GPIO_INDEX (GPIO_DI_GPIOB) -#define BOARD_CAP_RST_GPIO_PIN (9) -#define BOARD_CAP_RST_GPIO_IRQ (IRQn_GPIO0_B) -#define BOARD_CAP_INTR_GPIO (HPM_GPIO0) -#define BOARD_CAP_INTR_GPIO_INDEX (GPIO_DI_GPIOB) -#define BOARD_CAP_INTR_GPIO_PIN (8) -#define BOARD_CAP_INTR_GPIO_IRQ (IRQn_GPIO0_B) +#define BOARD_CAP_I2C_BASE (HPM_I2C0) +#define BOARD_CAP_I2C_CLK_NAME clock_i2c0 +#define BOARD_CAP_RST_GPIO (HPM_GPIO0) +#define BOARD_CAP_RST_GPIO_INDEX (GPIO_DI_GPIOB) +#define BOARD_CAP_RST_GPIO_PIN (9) +#define BOARD_CAP_RST_GPIO_IRQ (IRQn_GPIO0_B) +#define BOARD_CAP_INTR_GPIO (HPM_GPIO0) +#define BOARD_CAP_INTR_GPIO_INDEX (GPIO_DI_GPIOB) +#define BOARD_CAP_INTR_GPIO_PIN (8) +#define BOARD_CAP_INTR_GPIO_IRQ (IRQn_GPIO0_B) #define BOARD_CAP_I2C_SDA_GPIO_INDEX (GPIO_DI_GPIOB) -#define BOARD_CAP_I2C_SDA_GPIO_PIN (10) +#define BOARD_CAP_I2C_SDA_GPIO_PIN (10) #define BOARD_CAP_I2C_CLK_GPIO_INDEX (GPIO_DI_GPIOB) -#define BOARD_CAP_I2C_CLK_GPIO_PIN (11) +#define BOARD_CAP_I2C_CLK_GPIO_PIN (11) + +/* ACMP desction */ +#define BOARD_ACMP HPM_ACMP +#define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 +#define BOARD_ACMP_IRQ IRQn_ACMP_1 +#define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ +#define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_6 /* align with used pin */ /* dma section */ +#define BOARD_APP_XDMA HPM_XDMA +#define BOARD_APP_HDMA HPM_HDMA #define BOARD_APP_XDMA_IRQ IRQn_XDMA #define BOARD_APP_HDMA_IRQ IRQn_HDMA +#define BOARD_APP_DMAMUX HPM_DMAMUX + +/* gptmr section */ +#define BOARD_GPTMR HPM_GPTMR5 +#define BOARD_GPTMR_IRQ IRQn_GPTMR5 +#define BOARD_GPTMR_CHANNEL 1 +#define BOARD_GPTMR_DMA_SRC HPM_DMA_SRC_GPTMR5_1 +#define BOARD_GPTMR_CLK_NAME clock_gptmr5 +#define BOARD_GPTMR_PWM HPM_GPTMR5 +#define BOARD_GPTMR_PWM_DMA_SRC HPM_DMA_SRC_GPTMR5_1 +#define BOARD_GPTMR_PWM_CHANNEL 1 +#define BOARD_GPTMR_PWM_CLK_NAME clock_gptmr5 +#define BOARD_GPTMR_PWM_IRQ IRQn_GPTMR5 +#define BOARD_GPTMR_PWM_SYNC HPM_GPTMR5 +#define BOARD_GPTMR_PWM_SYNC_CHANNEL 0 +#define BOARD_GPTMR_PWM_SYNC_CLK_NAME clock_gptmr5 /* gpio section */ -#define BOARD_R_GPIO_CTRL HPM_GPIO0 +#define BOARD_R_GPIO_CTRL HPM_GPIO0 #define BOARD_R_GPIO_INDEX GPIO_DI_GPIOB -#define BOARD_R_GPIO_PIN 19 -#define BOARD_G_GPIO_CTRL HPM_GPIO0 +#define BOARD_R_GPIO_PIN 19 +#define BOARD_G_GPIO_CTRL HPM_GPIO0 #define BOARD_G_GPIO_INDEX GPIO_DI_GPIOB -#define BOARD_G_GPIO_PIN 18 -#define BOARD_B_GPIO_CTRL HPM_GPIO0 +#define BOARD_G_GPIO_PIN 18 +#define BOARD_B_GPIO_CTRL HPM_GPIO0 #define BOARD_B_GPIO_INDEX GPIO_DI_GPIOB -#define BOARD_B_GPIO_PIN 20 +#define BOARD_B_GPIO_PIN 20 -#define BOARD_LED_GPIO_CTRL BOARD_G_GPIO_CTRL +#define BOARD_LED_GPIO_CTRL BOARD_G_GPIO_CTRL #define BOARD_LED_GPIO_INDEX BOARD_G_GPIO_INDEX -#define BOARD_LED_GPIO_PIN BOARD_G_GPIO_PIN +#define BOARD_LED_GPIO_PIN BOARD_G_GPIO_PIN +/* + *led Internal pull-up and pull-down resistance direction + *The configurations of Rev-A / B boards are different + */ #define BOARD_LED_OFF_LEVEL 1 -#define BOARD_LED_ON_LEVEL 0 +#define BOARD_LED_ON_LEVEL 0 #define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOZ -#define BOARD_APP_GPIO_PIN 2 +#define BOARD_APP_GPIO_PIN 2 /* pinmux section */ #define USING_GPIO0_FOR_GPIOZ #ifndef USING_GPIO0_FOR_GPIOZ #define BOARD_APP_GPIO_CTRL HPM_BGPIO -#define BOARD_APP_GPIO_IRQ IRQn_BGPIO +#define BOARD_APP_GPIO_IRQ IRQn_BGPIO #else #define BOARD_APP_GPIO_CTRL HPM_GPIO0 -#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_Z +#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_Z #endif /* gpiom section */ @@ -180,42 +229,61 @@ #define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast /* spi section */ -#define BOARD_APP_SPI_BASE HPM_SPI2 -#define BOARD_APP_SPI_CLK_SRC_FREQ (24000000UL) -#define BOARD_APP_SPI_SCLK_FREQ (1562500UL) +#define BOARD_APP_SPI_BASE HPM_SPI2 +#define BOARD_APP_SPI_CLK_NAME clock_spi2 +#define BOARD_APP_SPI_IRQ IRQn_SPI2 +#define BOARD_APP_SPI_SCLK_FREQ (20000000UL) #define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U) #define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U) +#define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI2_RX +#define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI2_TX +#define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 +#define BOARD_SPI_CS_PIN IOC_PAD_PB24 +#define BOARD_SPI_CS_ACTIVE_LEVEL (0U) /* Flash section */ -#define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) -#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90001U) -#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000007U) -#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00000000U) +#define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) +#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90001U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000007U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00000000U) + +#define BOARD_FLASH_BASE_ADDRESS (0x80000000UL) +#define BOARD_FLASH_SIZE (8 << 20) /* lcd section */ -#define BOARD_LCD_BASE HPM_LCDC -#define BOARD_LCD_IRQ IRQn_LCDC_D0 -#define BOARD_LCD_POWER_GPIO_BASE HPM_GPIO0 -#define BOARD_LCD_POWER_GPIO_INDEX GPIO_DO_GPIOB -#define BOARD_LCD_POWER_GPIO_PIN 12 -#define BOARD_LCD_BACKLIGHT_GPIO_BASE HPM_GPIO0 -#define BOARD_LCD_BACKLIGHT_GPIO_INDEX GPIO_DO_GPIOB -#define BOARD_LCD_BACKLIGHT_GPIO_PIN 23 #ifndef BOARD_LCD_WIDTH -#define BOARD_LCD_WIDTH (800) +#define BOARD_LCD_WIDTH PANEL_SIZE_WIDTH #endif #ifndef BOARD_LCD_HEIGHT -#define BOARD_LCD_HEIGHT (480) +#define BOARD_LCD_HEIGHT PANEL_SIZE_HEIGHT #endif /* pdma section */ #define BOARD_PDMA_BASE HPM_PDMA +/* i2s section */ +#define BOARD_APP_I2S_CLK_NAME clock_i2s1 +#define BOARD_APP_AUDIO_CLK_SRC clock_source_pll3_clk0 +#define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll3clk0 +#define BOARD_PDM_SINGLE_CHANNEL_MASK (1U) +#define BOARD_PDM_DUAL_CHANNEL_MASK (0x11U) + /* enet section */ -#define BOARD_ENET0_RST_GPIO -#define BOARD_ENET0_RST_GPIO_INDEX -#define BOARD_ENET0_RST_GPIO_PIN +#define BOARD_ENET_PPS HPM_ENET0 +#define BOARD_ENET_PPS_IDX enet_pps_0 +#define BOARD_ENET_PPS_PTP_CLOCK clock_ptp0 + +#define BOARD_ENET_RMII_RST_GPIO HPM_GPIO0 +#define BOARD_ENET_RMII_RST_GPIO_INDEX GPIO_DO_GPIOD +#define BOARD_ENET_RMII_RST_GPIO_PIN (15U) +#define BOARD_ENET_RMII HPM_ENET1 +#define BOARD_ENET_RMII_INT_REF_CLK (0U) +#define BOARD_ENET_RMII_PTP_CLOCK clock_ptp1 + +#define BOARD_ENET1_RST_GPIO HPM_GPIO0 +#define BOARD_ENET1_RST_GPIO_INDEX GPIO_DO_GPIOE +#define BOARD_ENET1_RST_GPIO_PIN (26U) #define BOARD_ENET0_INF (0U) /* 0: RMII, 1: RGMII */ #define BOARD_ENET0_INT_REF_CLK (0U) @@ -230,11 +298,6 @@ #define BOARD_ENET0_PTP_CLOCK (clock_ptp0) #endif - -#define BOARD_ENET1_RST_GPIO HPM_GPIO0 -#define BOARD_ENET1_RST_GPIO_INDEX GPIO_DO_GPIOD -#define BOARD_ENET1_RST_GPIO_PIN (15U) - #define BOARD_ENET1_INF (0U) /* 0: RMII, 1: RGMII */ #define BOARD_ENET1_INT_REF_CLK (0U) #define BOARD_ENET1_PHY_RST_TIME (30) @@ -248,83 +311,215 @@ #define BOARD_ENET1_PTP_CLOCK (clock_ptp1) #endif -/* adc section */ -#define BOARD_APP_ADC12_BASE HPM_ADC0 -#define BOARD_APP_ADC16_BASE HPM_ADC3 -#define BOARD_APP_ADC12_IRQn IRQn_ADC0 -#define BOARD_APP_ADC16_IRQn IRQn_ADC3 -#define BOARD_APP_ADC_CH (0U) -#define BOARD_APP_ADC_SEQ_DMA_SIZE_IN_4BYTES (1024U) -#define BOARD_APP_ADC_PREEMPT_DMA_SIZE_IN_4BYTES (192U) -#define BOARD_APP_ADC_PREEMPT_TRIG_LEN (1U) -#define BOARD_APP_ADC_SINGLE_CONV_CNT (6) -#define BOARD_APP_ADC_TRIG_PWMT0 HPM_PWM0 -#define BOARD_APP_ADC_TRIG_PWMT1 HPM_PWM1 -#define BOARD_APP_ADC_TRIG_TRGM0 HPM_TRGM0 -#define BOARD_APP_ADC_TRIG_TRGM1 HPM_TRGM1 -#define BOARD_APP_ADC_TRIG_PWM_SYNC HPM_SYNT + + +/* ADC section */ +#define BOARD_APP_ADC12_NAME "ADC0" +#define BOARD_APP_ADC12_BASE HPM_ADC0 +#define BOARD_APP_ADC12_IRQn IRQn_ADC0 +#define BOARD_APP_ADC12_CH_1 (14U) +#define BOARD_APP_ADC12_CLK_NAME (clock_adc0) + +#define BOARD_APP_ADC16_NAME "ADC3" +#define BOARD_APP_ADC16_IRQn IRQn_ADC3 +#define BOARD_APP_ADC16_BASE HPM_ADC3 +#define BOARD_APP_ADC16_CH_1 (2U) +#define BOARD_APP_ADC16_CLK_NAME (clock_adc3) + +#define BOARD_APP_ADC12_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC12_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC12_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_APP_ADC12_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI +#define BOARD_APP_ADC12_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A + +#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC3_STRGI +#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A + +#define BOARD_APP_ADC12_PMT_TRIG_CH ADC12_CONFIG_TRG0A +#define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A + +/* CAN section */ +#define BOARD_APP_CAN_BASE HPM_CAN1 +#define BOARD_APP_CAN_IRQn IRQn_CAN1 /* * timer for board delay */ -#define BOARD_DELAY_TIMER (HPM_GPTMR0) -#define BOARD_DELAY_TIMER_CH 0 -#define BOARD_DELAY_TIMER_CLK_NAME (clock_gptmr0) - -#define BOARD_CALLBACK_TIMER (HPM_GPTMR0) -#define BOARD_CALLBACK_TIMER_CH 1 -#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR0 -#define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr0) +#define BOARD_DELAY_TIMER (HPM_GPTMR7) +#define BOARD_DELAY_TIMER_CH 0 +#define BOARD_DELAY_TIMER_CLK_NAME (clock_gptmr7) + +#define BOARD_CALLBACK_TIMER (HPM_GPTMR7) +#define BOARD_CALLBACK_TIMER_CH 1 +#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR7 +#define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr7) + +/* timer for 1ms*/ +#define BOARD_TMR_1MS HPM_GPTMR2 +#define BOARD_TMR_1MS_CH 0 +#define BOARD_TMR_1MS_CMP 0 +#define BOARD_TMR_1MS_IRQ IRQn_GPTMR2 +#define BOARD_TMR_1MS_RELOAD (100000U) /* SDXC section */ -#define BOARD_APP_SDCARD_SDXC_BASE (HPM_SDXC1) -#define BOARD_APP_SDCARD_SUPPORT_1V8 (0) +#define BOARD_APP_SDCARD_SDXC_BASE (HPM_SDXC1) +#define BOARD_APP_SDCARD_SUPPORT_3V3 (1) +#define BOARD_APP_SDCARD_SUPPORT_1V8 (1) +#define BOARD_APP_SDCARD_SUPPORT_4BIT (1) +#define BOARD_APP_SDCARD_SUPPORT_CARD_DETECTION (1) +#define BOARD_APP_SDCARD_SUPPORT_POWER_SWITCH (0) +#define BOARD_APP_SDCARD_SUPPORT_VOLTAGE_SWITCH (1) +#define BOARD_APP_SDCARD_SUPPORT_CARD_DETECTION (1) +#define BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO (0) +#if defined(BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO) && (BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO == 1) +#define BOARD_APP_SDCARD_CARD_DETECTION_GPIO NULL +#define BOARD_APP_SDCARD_CARD_DETECTION_GPIO_INDEX 0 +#define BOARD_APP_SDCARD_CARD_DETECTION_PIN_INDEX 0 +#endif + +#define BOARD_APP_EMMC_SDXC_BASE (HPM_SDXC1) +#define BOARD_APP_EMMC_SUPPORT_3V3 (1) +#define BOARD_APP_EMMC_SUPPORT_1V8 (0) +#define BOARD_APP_EMMC_SUPPORT_4BIT (1) +#define BOARD_APP_EMMC_SUPPORT_8BIT (0) +#define BOARD_APP_EMMC_SUPPORT_VOLTAGE_SWITCH (0) +/* For eMMC device, it is recommended to use GPIO to switch voltage directly */ +#define BOARD_APP_EMMC_VOLTAGE_SWITCH_USING_GPIO (1) +#if defined(BOARD_APP_EMMC_VOLTAGE_SWITCH_USING_GPIO) && (BOARD_APP_EMMC_VOLTAGE_SWITCH_USING_GPIO == 1) +#define BOARD_APP_EMMC_VSEL_PIN IOC_PAD_PD29 +#endif /* USB section */ -#define BOARD_USB0_VBUS_PORT (HPM_GPIO0) -#define BOARD_USB0_VBUS_GPIO_INDEX (GPIO_DO_GPIOF) -#define BOARD_USB0_VBUS_GPIO_PIN (9) +#define BOARD_USB0_ID_PORT (HPM_GPIO0) +#define BOARD_USB0_ID_GPIO_INDEX (GPIO_DO_GPIOF) +#define BOARD_USB0_ID_GPIO_PIN (10) -#define BOARD_USB0_OC_PORT (HPM_GPIO0) -#define BOARD_USB0_OC_GPIO_INDEX (GPIO_DI_GPIOF) -#define BOARD_USB0_OC_GPIO_PIN (8) +#define BOARD_USB0_OC_PORT (HPM_GPIO0) +#define BOARD_USB0_OC_GPIO_INDEX (GPIO_DI_GPIOF) +#define BOARD_USB0_OC_GPIO_PIN (8) /* APP PWM */ -#define BOARD_APP_PWM HPM_PWM0 -#define BOARD_APP_PWM_CLOCK_NAME clock_mot0 -#define BOARD_APP_PWM_OUT1 4 -#define BOARD_APP_PWM_OUT2 5 -#define BOARD_APP_TRGM HPM_TRGM0 +#define BOARD_APP_PWM HPM_PWM0 +#define BOARD_APP_PWM_CLOCK_NAME clock_mot0 +#define BOARD_APP_PWM_OUT1 4 +#define BOARD_APP_PWM_OUT2 5 +#define BOARD_APP_TRGM HPM_TRGM0 +#define BOARD_APP_PWM_IRQ IRQn_PWM0 +#define BOARD_APP_TRGM_PWM_OUTPUT TRGM_TRGOCFG_PWM_SYNCI /* RGB LED Section */ -#define BOARD_RED_PWM_IRQ IRQn_PWM1 -#define BOARD_RED_PWM HPM_PWM1 -#define BOARD_RED_PWM_OUT 0 -#define BOARD_RED_PWM_CMP 0 +#define BOARD_RED_PWM_IRQ IRQn_PWM1 +#define BOARD_RED_PWM HPM_PWM1 +#define BOARD_RED_PWM_OUT 0 +#define BOARD_RED_PWM_CMP 0 #define BOARD_RED_PWM_CMP_INITIAL_ZERO true -#define BOARD_RED_PWM_CLOCK_NAME clock_mot1 +#define BOARD_RED_PWM_CLOCK_NAME clock_mot1 -#define BOARD_GREEN_PWM_IRQ IRQn_PWM1 -#define BOARD_GREEN_PWM HPM_PWM1 -#define BOARD_GREEN_PWM_OUT 1 -#define BOARD_GREEN_PWM_CMP 1 +#define BOARD_GREEN_PWM_IRQ IRQn_PWM1 +#define BOARD_GREEN_PWM HPM_PWM1 +#define BOARD_GREEN_PWM_OUT 1 +#define BOARD_GREEN_PWM_CMP 1 #define BOARD_GREEN_PWM_CMP_INITIAL_ZERO true -#define BOARD_GREEN_PWM_CLOCK_NAME clock_mot1 +#define BOARD_GREEN_PWM_CLOCK_NAME clock_mot1 -#define BOARD_BLUE_PWM_IRQ IRQn_PWM0 -#define BOARD_BLUE_PWM HPM_PWM0 -#define BOARD_BLUE_PWM_OUT 7 -#define BOARD_BLUE_PWM_CMP 0 +#define BOARD_BLUE_PWM_IRQ IRQn_PWM0 +#define BOARD_BLUE_PWM HPM_PWM0 +#define BOARD_BLUE_PWM_OUT 7 +#define BOARD_BLUE_PWM_CMP 7 #define BOARD_BLUE_PWM_CMP_INITIAL_ZERO true -#define BOARD_BLUE_PWM_CLOCK_NAME clock_mot0 +#define BOARD_BLUE_PWM_CLOCK_NAME clock_mot0 +#define BOARD_RGB_RED 0 +#define BOARD_RGB_GREEN (BOARD_RGB_RED + 1) +#define BOARD_RGB_BLUE (BOARD_RGB_RED + 2) /* Beep Section */ -#define BOARD_BEEP_PWM HPM_PWM3 -#define BOARD_BEEP_PWM_OUT 4 +#define BOARD_BEEP_PWM HPM_PWM3 +#define BOARD_BEEP_PWM_OUT 4 #define BOARD_BEEP_PWM_CLOCK_NAME clock_mot3 -#define BOARD_CPU_FREQ (816000000UL) +/*BLDC pwm*/ + +/*PWM define*/ +#define BOARD_BLDCPWM HPM_PWM1 +#define BOARD_BLDC_UH_PWM_OUTPIN (2U) +#define BOARD_BLDC_UL_PWM_OUTPIN (3U) +#define BOARD_BLDC_VH_PWM_OUTPIN (4U) +#define BOARD_BLDC_VL_PWM_OUTPIN (5U) +#define BOARD_BLDC_WH_PWM_OUTPIN (6U) +#define BOARD_BLDC_WL_PWM_OUTPIN (7U) +#define BOARD_BLDCPWM_TRGM HPM_TRGM1 +#define BOARD_BLDCAPP_PWM_IRQ IRQn_PWM1 +#define BOARD_BLDCPWM_CMP_INDEX_0 (0U) +#define BOARD_BLDCPWM_CMP_INDEX_1 (1U) +#define BOARD_BLDCPWM_CMP_INDEX_2 (2U) +#define BOARD_BLDCPWM_CMP_INDEX_3 (3U) +#define BOARD_BLDCPWM_CMP_INDEX_4 (4U) +#define BOARD_BLDCPWM_CMP_INDEX_5 (5U) +#define BOARD_BLDCPWM_CMP_INDEX_6 (6U) +#define BOARD_BLDCPWM_CMP_INDEX_7 (7U) +#define BOARD_BLDCPWM_CMP_TRIG_CMP (20U) + +/*HALL define*/ + +#define BOARD_BLDC_HALL_BASE HPM_HALL2 +#define BOARD_BLDC_HALL_TRGM HPM_TRGM2 +#define BOARD_BLDC_HALL_IRQ IRQn_HALL2 +#define BOARD_BLDC_HALL_TRGM_HALL_U_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P9 +#define BOARD_BLDC_HALL_TRGM_HALL_V_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P10 +#define BOARD_BLDC_HALL_TRGM_HALL_W_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P11 +#define BOARD_BLDC_HALL_MOTOR_PHASE_COUNT_PER_REV (1000U) + +/*QEI*/ + +#define BOARD_BLDC_QEI_BASE HPM_QEI2 +#define BOARD_BLDC_QEI_IRQ IRQn_QEI2 +#define BOARD_BLDC_QEI_TRGM HPM_TRGM2 +#define BOARD_BLDC_QEI_TRGM_QEI_A_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P6 +#define BOARD_BLDC_QEI_TRGM_QEI_B_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P7 +#define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV (16U) +#define BOARD_BLDC_QEI_CLOCK_SOURCE clock_mot2 +#define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV (4000U) + +/*Timer define*/ + +#define BOARD_TMR_1MS HPM_GPTMR2 +#define BOARD_TMR_1MS_CH 0 +#define BOARD_TMR_1MS_CMP 0 +#define BOARD_TMR_1MS_IRQ IRQn_GPTMR2 +#define BOARD_TMR_1MS_RELOAD (100000U) + +#define BOARD_BLDC_TMR_1MS BOARD_TMR_1MS +#define BOARD_BLDC_TMR_CH BOARD_TMR_1MS_CH +#define BOARD_BLDC_TMR_CMP BOARD_TMR_1MS_CMP +#define BOARD_BLDC_TMR_IRQ BOARD_TMR_1MS_IRQ +#define BOARD_BLDC_TMR_RELOAD BOARD_TMR_1MS_RELOAD + +/*adc*/ +#define BOARD_BLDC_ADC_MODULE ADCX_MODULE_ADC12 +#define BOARD_BLDC_ADC_U_BASE HPM_ADC0 +#define BOARD_BLDC_ADC_V_BASE HPM_ADC1 +#define BOARD_BLDC_ADC_W_BASE HPM_ADC2 +#define BOARD_BLDC_ADC_TRIG_FLAG adc12_event_trig_complete + +#define BOARD_BLDC_ADC_CH_U (1U) +#define BOARD_BLDC_ADC_CH_V (2U) +#define BOARD_BLDC_ADC_CH_W (3U) +#define BOARD_BLDC_ADC_IRQn IRQn_ADC0 +#define BOARD_BLDC_ADC_PMT_DMA_SIZE_IN_4BYTES (ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES) +#define BOARD_BLDC_ADC_TRG ADC12_CONFIG_TRG1A +#define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) +#define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U) +#define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM1_INPUT_SRC_PWM1_CH8REF +#define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A +#define BOARD_BLDC_ADC_IRQn IRQn_ADC0 + +#define BOARD_CPU_FREQ (648000000UL) + +#define BOARD_APP_DISPLAY_CLOCK clock_display #ifndef BOARD_SHOW_CLOCK #define BOARD_SHOW_CLOCK 1 @@ -333,10 +528,25 @@ #define BOARD_SHOW_BANNER 1 #endif +/* FreeRTOS Definitions */ +#define BOARD_FREERTOS_TIMER HPM_GPTMR4 +#define BOARD_FREERTOS_TIMER_CHANNEL 1 +#define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR4 +#define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr4 + +/* Threadx Definitions */ +#define BOARD_THREADX_TIMER HPM_GPTMR4 +#define BOARD_THREADX_TIMER_CHANNEL 1 +#define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR4 +#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr4 #ifndef BOARD_RUNNING_CORE #define BOARD_RUNNING_CORE 0 #endif +/* Tamper Section */ +#define BOARD_TAMP_ACTIVE_CH 8 +#define BOARD_TAMP_LOW_LEVEL_CH 10 + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ @@ -346,11 +556,13 @@ typedef void (*board_timer_cb)(void); void board_init(void); void board_init_console(void); +void board_init_core1(void); + void board_init_uart(UART_Type *ptr); void board_init_i2c(I2C_Type *ptr); void board_init_lcd(void); +void board_lcd_backlight(bool is_on); void board_panel_para_to_lcdc(lcdc_config_t *config); - void board_init_can(CAN_Type *ptr); uint32_t board_init_femc_clock(void); @@ -358,21 +570,25 @@ uint32_t board_init_femc_clock(void); void board_init_sdram_pins(void); void board_init_gpio_pins(void); void board_init_spi_pins(SPI_Type *ptr); +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); +void board_write_spi_cs(uint32_t pin, uint8_t state); void board_init_led_pins(void); /* cap touch */ void board_init_cap_touch(void); -void board_led_write(bool state); +void board_led_write(uint8_t state); void board_led_toggle(void); void board_fpga_power_enable(void); void board_init_cam_pins(void); - /* Initialize SoC overall clocks */ void board_init_clock(void); +/* Initialize the UART clock */ +uint32_t board_init_uart_clock(UART_Type *ptr); + /* Initialize the CAM(camera) dot clock */ uint32_t board_init_cam_clock(CAM_Type *ptr); @@ -383,27 +599,47 @@ uint32_t board_init_uart_clock(UART_Type *ptr); uint32_t board_init_spi_clock(SPI_Type *ptr); -uint32_t board_init_adc12_clock(ADC12_Type *ptr); +uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb); -uint32_t board_init_adc16_clock(ADC16_Type *ptr); +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb); uint32_t board_init_can_clock(CAN_Type *ptr); +uint32_t board_init_pwm_clock(PWM_Type *ptr); + +hpm_stat_t board_set_audio_pll_clock(uint32_t freq); + +void board_init_i2s_pins(I2S_Type *ptr); uint32_t board_init_i2s_clock(I2S_Type *ptr); +uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate); uint32_t board_init_pdm_clock(void); uint32_t board_init_dao_clock(void); +uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate); uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); - void board_init_sd_pins(SDXC_Type *ptr); -uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq); + +uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inverse); void board_sd_switch_pins_to_1v8(SDXC_Type *ptr); -void board_sd_power_switch(SDXC_Type *ptr, bool on_off); bool board_sd_detect_card(SDXC_Type *ptr); +void board_init_dao_pins(void); + +void board_init_adc12_pins(void); +void board_init_adc16_pins(void); + void board_init_usb_pins(void); void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); +void board_init_enet_pps_pins(ENET_Type *ptr); +uint8_t board_get_enet_dma_pbl(ENET_Type *ptr); +hpm_stat_t board_reset_enet_phy(ENET_Type *ptr); +hpm_stat_t board_init_enet_pins(ENET_Type *ptr); +hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal); +hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr); +hpm_stat_t board_enable_enet_irq(ENET_Type *ptr); +hpm_stat_t board_disable_enet_irq(ENET_Type *ptr); + /* * @brief Initialize PMP and PMA for but not limited to the following purposes: * -- non-cacheable memory initialization @@ -411,17 +647,31 @@ void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); void board_init_pmp(void); void board_delay_ms(uint32_t ms); +void board_delay_us(uint32_t us); void board_init_beep_pwm_pins(void); void board_init_rgb_pwm_pins(void); -void board_timer_create(uint32_t ms, void *cb); +void board_timer_create(uint32_t ms, board_timer_cb cb); +void board_enable_output_rgb_led(uint8_t color); +void board_disable_output_rgb_led(uint8_t color); -hpm_stat_t board_init_enet_pins(ENET_Type *ptr); -hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal); -hpm_stat_t board_reset_enet_phy(ENET_Type *ptr); -uint8_t board_enet_get_dma_pbl(ENET_Type *ptr); -hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr); +/* + * Keep mchtmr clock on low power mode + */ +void board_ungate_mchtmr_at_lp_mode(void); + +/* + * Get PWM output level of onboard LED + */ +uint8_t board_get_led_pwm_off_level(void); + +/* + * Get GPIO pin level of onboard LED + */ +uint8_t board_get_led_gpio_off_level(void); + +void board_sd_power_switch(SDXC_Type *ptr, bool on_off); #if defined(__cplusplus) } diff --git a/bsp/hpmicro/hpm6750evkmini/board/eth_phy_port.c b/bsp/hpmicro/hpm6750evkmini/board/eth_phy_port.c deleted file mode 100644 index ee4efc0bd9a..00000000000 --- a/bsp/hpmicro/hpm6750evkmini/board/eth_phy_port.c +++ /dev/null @@ -1,299 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - * Change Logs: - * Date Author Notes - * 2022-01-11 hpmicro First version - */ - -#include "rtthread.h" - -#ifdef RT_USING_PHY -#include -#include -#include "hpm_enet_drv.h" -#include "eth_phy_port.h" -#include "hpm_soc.h" -#include "netif/ethernetif.h" -#include "board.h" - -typedef struct -{ - char *mdio_name; - ENET_Type *instance; - struct eth_device *eth_dev; - phy_device_t *phy_dev; - struct rt_mdio_bus *mdio_bus; -} eth_phy_handle_t; - -typedef struct -{ - uint8_t phy_handle_cnt; - eth_phy_handle_t **phy_handle; -} eth_phy_monitor_handle_t; - -#ifdef BSP_USING_ETH0 -extern struct eth_device eth0_dev; -static struct rt_mdio_bus mdio0_bus; -static phy_device_t phy0_dev; -static uint8_t phy0_reg_list[]= {PHY0_REG_LIST}; - -static eth_phy_handle_t eth0_phy_handle = -{ - .instance = HPM_ENET0, - .eth_dev = ð0_dev, - .phy_dev = &phy0_dev, - .mdio_name = "MDIO0", - .mdio_bus = &mdio0_bus, -}; -#endif - -#ifdef BSP_USING_ETH1 -extern struct eth_device eth1_dev; -static struct rt_mdio_bus mdio1_bus; -static phy_device_t phy1_dev; -static uint8_t phy1_reg_list[]= {PHY1_REG_LIST}; - -static eth_phy_handle_t eth1_phy_handle = -{ - .instance = HPM_ENET1, - .eth_dev = ð1_dev, - .phy_dev = &phy1_dev, - .mdio_name = "MDIO1", - .mdio_bus = &mdio1_bus, -}; -#endif - -static eth_phy_handle_t *s_gphys[] = -{ -#ifdef BSP_USING_ETH0 -ð0_phy_handle, -#endif - -#ifdef BSP_USING_ETH1 -ð1_phy_handle -#endif -}; - -static uint8_t *s_gphy_reg_list[] = -{ -#ifdef BSP_USING_ETH0 -phy0_reg_list, -#endif - -#ifdef BSP_USING_ETH1 -phy1_reg_list, -#endif -}; - -eth_phy_monitor_handle_t phy_monitor_handle = -{ - .phy_handle_cnt = ARRAY_SIZE(s_gphys), - .phy_handle = s_gphys -}; - -static struct rt_phy_ops phy_ops; - -static rt_phy_status phy_init(void *object, rt_uint32_t phy_addr, rt_uint32_t src_clock_hz) -{ - return PHY_STATUS_OK; -} - -static rt_size_t phy_read(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size) -{ - *(uint16_t *)data = enet_read_phy(((struct rt_mdio_bus *)bus)->hw_obj, addr, reg); - - return size; -} - -static rt_size_t phy_write(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size) -{ - enet_write_phy(((struct rt_mdio_bus *)bus)->hw_obj, addr, reg, *(uint16_t *)data); - - return size; -} - -static rt_phy_status phy_get_link_status(rt_phy_t *phy, rt_bool_t *status) -{ - uint16_t reg_status; - - reg_status = enet_read_phy(phy->bus->hw_obj, phy->addr, phy->reg_list[PHY_BASIC_STATUS_REG_IDX]); - - #if PHY_AUTO_NEGO - reg_status &= PHY_AUTONEGO_COMPLETE_MASK | PHY_LINKED_STATUS_MASK; - *status = reg_status ? RT_TRUE : RT_FALSE; - - #else - reg_status &= PHY_LINKED_STATUS_MASK; - *status = reg_status ? RT_TRUE : RT_FALSE; - #endif - - return PHY_STATUS_OK; -} - -static rt_phy_status phy_get_link_speed_duplex(rt_phy_t *phy, rt_uint32_t *speed, rt_uint32_t *duplex) -{ - uint16_t reg_status; - - reg_status = enet_read_phy(phy->bus->hw_obj, phy->addr, phy->reg_list[PHY_STATUS_REG_IDX]); - - *speed = PHY_STATUS_SPEED_100M(reg_status) ? PHY_SPEED_100M : PHY_SPEED_10M; - *duplex = PHY_STATUS_FULL_DUPLEX(reg_status) ? PHY_FULL_DUPLEX: PHY_HALF_DUPLEX; - - return PHY_STATUS_OK; -} - -static void phy_poll_status(void *parameter) -{ - int ret; - phy_info_t phy_info; - rt_bool_t status; - rt_device_t dev; - rt_phy_msg_t msg; - rt_uint32_t speed, duplex; - phy_device_t *phy_dev; - struct eth_device* eth_dev; - char const *ps[] = {"10Mbps", "100Mbps", "1000Mbps"}; - enet_line_speed_t line_speed[] = {enet_line_speed_10mbps, enet_line_speed_100mbps, enet_line_speed_1000mbps}; - - eth_phy_monitor_handle_t *phy_monitor_handle = (eth_phy_monitor_handle_t *)parameter; - - for (uint32_t i = 0; i < phy_monitor_handle->phy_handle_cnt; i++) - { - eth_dev = phy_monitor_handle->phy_handle[i]->eth_dev; - phy_dev = phy_monitor_handle->phy_handle[i]->phy_dev; - - phy_dev->phy.ops->get_link_status(&phy_dev->phy, &status); - - if (status) - { - phy_dev->phy.ops->get_link_speed_duplex(&phy_dev->phy, &phy_info.phy_speed, &phy_info.phy_duplex); - - ret = memcmp(&phy_dev->phy_info, &phy_info, sizeof(phy_info_t)); - if (ret != 0) - { - memcpy(&phy_dev->phy_info, &phy_info, sizeof(phy_info_t)); - } - } - - if (phy_dev->phy_link != status) - { - phy_dev->phy_link = status ? PHY_LINK_UP : PHY_LINK_DOWN; - eth_device_linkchange(eth_dev, status); - LOG_I("PHY Status: %s", status ? "Link up" : "Link down\n"); - if (status == PHY_LINK_UP) - { - LOG_I("PHY Speed: %s", ps[phy_dev->phy_info.phy_speed]); - LOG_I("PHY Duplex: %s\n", phy_dev->phy_info.phy_duplex & PHY_FULL_DUPLEX ? "full duplex" : "half duplex"); - enet_set_line_speed(phy_monitor_handle->phy_handle[i]->instance, line_speed[phy_dev->phy_info.phy_speed]); - enet_set_duplex_mode(phy_monitor_handle->phy_handle[i]->instance, phy_dev->phy_info.phy_duplex); - } - } - } -} - -static void phy_detection(void *parameter) -{ - uint8_t detected_count = 0; - struct rt_phy_msg msg = {0, 0}; - phy_device_t *phy_dev = (phy_device_t *)parameter; - rt_uint32_t i; - - msg.reg = phy_dev->phy.reg_list[PHY_ID1_REG_IDX]; - phy_dev->phy.ops->init(phy_dev->phy.bus->hw_obj, phy_dev->phy.addr, PHY_MDIO_CSR_CLK_FREQ); - - while(phy_dev->phy.addr == 0xffff) - { - /* Search a PHY */ - for (i = 0; i <= 0x1f; i++) - { - ((rt_phy_t *)(phy_dev->phy.parent.user_data))->addr = i; - phy_dev->phy.parent.read(&(phy_dev->phy.parent), 0, &msg, 1); - - if (msg.value == PHY_ID1) - { - phy_dev->phy.addr = i; - LOG_D("Found a PHY device[address:0x%02x].\n", phy_dev->phy.addr); - return; - } - } - - phy_dev->phy.addr = 0xffff; - detected_count++; - rt_thread_mdelay(1000); - - if (detected_count > 3) - { - LOG_E("No any PHY device is detected! Please check your hardware!\n"); - return; - } - } -} - -static void phy_monitor_thread_entry(void *args) -{ - rt_timer_t phy_status_timer; - - eth_phy_monitor_handle_t *phy_monitor_handle = (eth_phy_monitor_handle_t *)args; - - for (uint32_t i = 0; i < phy_monitor_handle->phy_handle_cnt; i++) - { - LOG_D("Detect a PHY%d\n", i); - phy_detection(phy_monitor_handle->phy_handle[i]->phy_dev); - } - - phy_status_timer = rt_timer_create("PHY_Monitor", phy_poll_status, phy_monitor_handle, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC | RT_TIMER_FLAG_SOFT_TIMER); - - if (!phy_status_timer || rt_timer_start(phy_status_timer) != RT_EOK) - { - LOG_E("Failed to start link change detection timer\n"); - } -} - -int phy_device_register(void) -{ - rt_err_t err = -RT_ERROR; - rt_thread_t thread_phy_monitor; - - /* Set ops for PHY */ - phy_ops.init = phy_init; - phy_ops.get_link_status = phy_get_link_status; - phy_ops.get_link_speed_duplex = phy_get_link_speed_duplex; - - for (uint32_t i = 0; i < ARRAY_SIZE(s_gphys); i++) - { - /* Set PHY address */ - s_gphys[i]->phy_dev->phy.addr = 0xffff; - - /* Set MIDO bus */ - s_gphys[i]->mdio_bus->hw_obj = s_gphys[i]->instance; - s_gphys[i]->mdio_bus->name = s_gphys[i]->mdio_name; - s_gphys[i]->mdio_bus->ops->read = phy_read; - s_gphys[i]->mdio_bus->ops->write = phy_write; - s_gphys[i]->phy_dev->phy.bus = s_gphys[i]->mdio_bus; - s_gphys[i]->phy_dev->phy.ops = &phy_ops; - - /* Set PHY register list */ - s_gphys[i]->phy_dev->phy.reg_list = s_gphy_reg_list[i]; - - rt_hw_phy_register(&s_gphys[i]->phy_dev->phy, PHY_NAME); - } - - /* Start PHY monitor */ - thread_phy_monitor = rt_thread_create("PHY Monitor", phy_monitor_thread_entry, &phy_monitor_handle, 1024, RT_THREAD_PRIORITY_MAX - 2, 2); - - if (thread_phy_monitor != RT_NULL) - { - rt_thread_startup(thread_phy_monitor); - } - else - { - err = -RT_ERROR; - } - - return err; -} -INIT_PREV_EXPORT(phy_device_register); -#endif /* RT_USING_PHY */ diff --git a/bsp/hpmicro/hpm6750evkmini/board/eth_phy_port.h b/bsp/hpmicro/hpm6750evkmini/board/eth_phy_port.h deleted file mode 100644 index 1aab1b3c578..00000000000 --- a/bsp/hpmicro/hpm6750evkmini/board/eth_phy_port.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef ETH_PHY_PORT_H -#define ETH_PHY_PORT_H - -#include "hpm_ioc_regs.h" -#include - -#ifndef PHY_AUTO_NEGO -#define PHY_AUTO_NEGO (1U) -#endif - -#ifndef PHY_MDIO_CSR_CLK_FREQ -#define PHY_MDIO_CSR_CLK_FREQ (200000000U) -#endif - -enum phy_link_status -{ - PHY_LINK_DOWN = 0U, - PHY_LINK_UP -}; - -typedef struct { - rt_uint32_t phy_speed; - rt_uint32_t phy_duplex; -} phy_info_t; - -typedef struct { - rt_uint32_t phy_link; - rt_phy_t phy; - phy_info_t phy_info; -} phy_device_t; - -/** @note PHY: LAN8720A */ - -#define PHY_NAME ("LAN8720A") -#define PHY_ID1 (7U) - -/* The PHY basic control register */ -#define PHY_BASIC_CONTROL_REG (0x00U) -#define PHY_RESET_MASK (1U << 15) -#define PHY_AUTO_NEGOTIATION_MASK (1U << 12) - -/* The PHY basic status register */ -#define PHY_BASIC_STATUS_REG (0x01U) -#define PHY_LINKED_STATUS_MASK (1U << 2) -#define PHY_AUTONEGO_COMPLETE_MASK (1U << 5) - -/* The PHY ID one register */ -#define PHY_ID1_REG (0x02U) - -/* The PHY ID two register */ -#define PHY_ID2_REG (0x03U) - -/* The PHY auto-negotiate advertise register */ -#define PHY_AUTONEG_ADVERTISE_REG (0x04U) - -/* The PHY SPECIAL MODES REGISTER */ -#define PHY_SPECIAL_MODES_REG (0x12U) - -/* The PHY interrupt source flag register. */ -#define PHY_INTERRUPT_FLAG_REG (0x1dU) - -/* The PHY interrupt mask register. */ -#define PHY_INTERRUPT_MASK_REG (0x1eU) -#define PHY_LINK_DOWN_MASK (1 << 4) -#define PHY_AUTO_NEGO_COMPLETE_MASK (1 << 6) - -/* The PHY status register. */ -#define PHY_STATUS_REG (0x1fU) -#define PHY_10M_MASK (1 << 2) -#define PHY_100M_MASK (1 << 3) -#define PHY_FULL_DUPLEX_MASK (1 << 4) -#define PHY_STATUS_SPEED_10M(SR) ((SR) & PHY_10M_MASK) -#define PHY_STATUS_SPEED_100M(SR) ((SR) & PHY_100M_MASK) -#define PHY_STATUS_FULL_DUPLEX(SR) ((SR) & PHY_FULL_DUPLEX_MASK) - -/* PHY0 register list */ -#define PHY0_REG_LIST PHY_BASIC_CONTROL_REG,\ - PHY_BASIC_STATUS_REG,\ - PHY_ID1_REG,\ - PHY_ID2_REG,\ - PHY_SPECIAL_MODES_REG,\ - PHY_INTERRUPT_FLAG_REG,\ - PHY_INTERRUPT_MASK_REG,\ - PHY_STATUS_REG - -/* PHY0 register index */ -#define PHY0_BASIC_STATUS_REG_IDX (1U) -#define PHY0_ID1_REG_IDX (2U) -#define PHY0_STATUS_REG_IDX (7U) - -/* PHY1 register list */ -#define PHY1_REG_LIST PHY_BASIC_CONTROL_REG,\ - PHY_BASIC_STATUS_REG,\ - PHY_ID1_REG,\ - PHY_ID2_REG,\ - PHY_SPECIAL_MODES_REG,\ - PHY_INTERRUPT_FLAG_REG,\ - PHY_INTERRUPT_MASK_REG,\ - PHY_STATUS_REG - -/* PHY1 register index */ -#define PHY_BASIC_STATUS_REG_IDX (1U) -#define PHY_ID1_REG_IDX (2U) -#define PHY_STATUS_REG_IDX (7U) - -#endif diff --git a/bsp/hpmicro/hpm6750evkmini/board/fal_cfg.h b/bsp/hpmicro/hpm6750evkmini/board/fal_cfg.h index 781dbe865d5..91f2d61bdab 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/fal_cfg.h +++ b/bsp/hpmicro/hpm6750evkmini/board/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023 HPMicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_rtt.ld b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_rtt.ld index c8b1045f8bd..6cd03eb349e 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_rtt.ld +++ b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_rtt.ld @@ -141,6 +141,12 @@ SECTIONS /* RT-Thread related sections - end */ + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + } > XPI0 .rel : { @@ -298,7 +304,6 @@ SECTIONS .sdram (NOLOAD) : { . = ALIGN(8); __sdram_start__ = .; - . += SDRAM_SIZE; __sdram_end__ = .; } > SDRAM } diff --git a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_rtt_enet.ld b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_rtt_enet.ld new file mode 100644 index 00000000000..705d3d328a2 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_rtt_enet.ld @@ -0,0 +1,330 @@ +/* + * Copyright 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K; +FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 256K; +SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 16M; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE + ILM (wx) : ORIGIN = 0, LENGTH = 256K + DLM (w) : ORIGIN = 0x80000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1280K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x11C0000, LENGTH = NONCACHEABLE_SIZE + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + + . = ALIGN(8); + __vector_ram_end__ = .; + } > AXI_SRAM + + .fast : AT(etext + __data_end__ - __tdata_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + + /* RT-Thread Core Start */ + KEEP(*context_gcc.o(.text* .rodata*)) + KEEP(*port*.o (.text .text* .rodata .rodata*)) + KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) + KEEP(*trap_common.o (.text .text* .rodata .rodata*)) + KEEP(*irq.o (.text .text* .rodata .rodata*)) + KEEP(*clock.o (.text .text* .rodata .rodata*)) + KEEP(*kservice.o (.text .text* .rodata .rodata*)) + KEEP(*scheduler*.o (.text .text* .rodata .rodata*)) + KEEP(*trap*.o (.text .text* .rodata .rodata*)) + KEEP(*idle.o (.text .text* .rodata .rodata*)) + KEEP(*ipc.o (.text .text* .rodata .rodata*)) + KEEP(*slab.o (.text .text* .rodata .rodata*)) + KEEP(*thread.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*timer.o (.text .text* .rodata .rodata*)) + KEEP(*mem.o (.text .text* .rodata .rodata*)) + KEEP(*memheap.o (.text .text* .rodata .rodata*)) + KEEP(*mempool.o (.text .text* .rodata .rodata*)) + /* RT-Thread Core End */ + + /* HPMicro Driver Wrapper */ + KEEP(*drv_*.o (.text .text* .rodata .rodata*)) + KEEP(*api_lib*.o (.text .text* .rodata .rodata*)) + KEEP(*api_msg*.o (.text .text* .rodata .rodata*)) + KEEP(*if_api*.o (.text .text* .rodata .rodata*)) + KEEP(*netbuf*.o (.text .text* .rodata .rodata*)) + KEEP(*netdb*.o (.text .text* .rodata .rodata*)) + KEEP(*netifapi*.o (.text .text* .rodata .rodata*)) + KEEP(*sockets*.o (.text .text* .rodata .rodata*)) + KEEP(*tcpip*.o (.text .text* .rodata .rodata*)) + KEEP(*inet_chksum*.o (.text .text* .rodata .rodata*)) + KEEP(*ip*.o (.text .text* .rodata .rodata*)) + KEEP(*memp*.o (.text .text* .rodata .rodata*)) + KEEP(*netif*.o (.text .text* .rodata .rodata*)) + KEEP(*pbuf*.o (.text .text* .rodata .rodata*)) + KEEP(*tcp_in*.o (.text .text* .rodata .rodata*)) + KEEP(*tcp_out*.o (.text .text* .rodata .rodata*)) + KEEP(*tcp*.o (.text .text* .rodata .rodata*)) + KEEP(*ethernet*.o (.text .text* .rodata .rodata*)) + KEEP(*ethernetif*.o (.text .text* .rodata .rodata*)) + + . = ALIGN(8); + __ramfunc_end__ = .; + } > AXI_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + /* Note: the .tbss and .tdata section should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > AXI_SRAM + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > AXI_SRAM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + + .heap(NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE( __rt_rvstack = . ); + } > AXI_SRAM + + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + + .sdram (NOLOAD) : { + . = ALIGN(8); + __sdram_start__ = .; + . += SDRAM_SIZE; + __sdram_end__ = .; + } > SDRAM +} diff --git a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_sdram_rtt.ld b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_sdram_rtt.ld index c967b2fcf5e..9e97c660112 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_sdram_rtt.ld +++ b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_sdram_rtt.ld @@ -141,6 +141,12 @@ SECTIONS /* RT-Thread related sections - end */ + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + } > XPI0 .rel : { diff --git a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/ram_rtt.ld b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/ram_rtt.ld index 0d071418144..731fbafe63d 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/ram_rtt.ld +++ b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/ram_rtt.ld @@ -87,6 +87,12 @@ SECTIONS /* RT-Thread related sections - end */ + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); @@ -225,10 +231,6 @@ SECTIONS KEEP(*(.backup_sram)) } > APB_SRAM - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - .stack(NOLOAD) : { . = ALIGN(8); __stack_base__ = .; diff --git a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/ram_sdram_rtt.ld b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/ram_sdram_rtt.ld index 34d67d45233..1e7c3e6fcd3 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/ram_sdram_rtt.ld +++ b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/ram_sdram_rtt.ld @@ -87,6 +87,12 @@ SECTIONS /* RT-Thread related sections - end */ + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); diff --git a/bsp/hpmicro/hpm6750evkmini/board/pinmux.c b/bsp/hpmicro/hpm6750evkmini/board/pinmux.c index abe1e4603be..33d93cd5dd2 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/pinmux.c +++ b/bsp/hpmicro/hpm6750evkmini/board/pinmux.c @@ -20,26 +20,61 @@ void init_uart_pins(UART_Type *ptr) if (ptr == HPM_UART0) { HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART0_RXD; HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART0_TXD; - HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY06_FUNC_CTL_SOC_PY_06; - HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY07_FUNC_CTL_SOC_PY_07; + /* PY port IO needs to configure PIOC as well */ + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = PIOC_PY07_FUNC_CTL_SOC_PY_07; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = PIOC_PY06_FUNC_CTL_SOC_PY_06; } else if (ptr == HPM_UART6) { HPM_IOC->PAD[IOC_PAD_PE27].FUNC_CTL = IOC_PE27_FUNC_CTL_UART6_RXD; HPM_IOC->PAD[IOC_PAD_PE28].FUNC_CTL = IOC_PE28_FUNC_CTL_UART6_TXD; + } else if (ptr == HPM_UART7) { + HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PC02_FUNC_CTL_UART7_RXD; + HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PC03_FUNC_CTL_UART7_TXD; } else if (ptr == HPM_UART13) { HPM_IOC->PAD[IOC_PAD_PZ08].FUNC_CTL = IOC_PZ08_FUNC_CTL_UART13_RXD; HPM_IOC->PAD[IOC_PAD_PZ09].FUNC_CTL = IOC_PZ09_FUNC_CTL_UART13_TXD; - HPM_BIOC->PAD[IOC_PAD_PZ08].FUNC_CTL = IOC_PZ08_FUNC_CTL_SOC_PZ_08; - HPM_BIOC->PAD[IOC_PAD_PZ09].FUNC_CTL = IOC_PZ09_FUNC_CTL_SOC_PZ_09; + /* PZ port IO needs to configure BIOC as well */ + HPM_BIOC->PAD[IOC_PAD_PZ08].FUNC_CTL = BIOC_PZ08_FUNC_CTL_SOC_PZ_08; + HPM_BIOC->PAD[IOC_PAD_PZ09].FUNC_CTL = BIOC_PZ09_FUNC_CTL_SOC_PZ_09; } else if (ptr == HPM_UART14) { HPM_IOC->PAD[IOC_PAD_PZ10].FUNC_CTL = IOC_PZ10_FUNC_CTL_UART14_RXD; HPM_IOC->PAD[IOC_PAD_PZ11].FUNC_CTL = IOC_PZ11_FUNC_CTL_UART14_TXD; - HPM_BIOC->PAD[IOC_PAD_PZ10].FUNC_CTL = IOC_PZ10_FUNC_CTL_SOC_PZ_10; - HPM_BIOC->PAD[IOC_PAD_PZ11].FUNC_CTL = IOC_PZ11_FUNC_CTL_SOC_PZ_11; + /* PZ port IO needs to configure BIOC as well */ + HPM_BIOC->PAD[IOC_PAD_PZ10].FUNC_CTL = BIOC_PZ10_FUNC_CTL_SOC_PZ_10; + HPM_BIOC->PAD[IOC_PAD_PZ11].FUNC_CTL = BIOC_PZ11_FUNC_CTL_SOC_PZ_11; + } else if (ptr == HPM_PUART) { + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = PIOC_PY07_FUNC_CTL_PUART_RXD; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = PIOC_PY06_FUNC_CTL_PUART_TXD; + } +} + +void init_uart_pin_as_gpio(UART_Type *ptr) +{ + if (ptr == HPM_UART7) { + /* pull-up */ + HPM_IOC->PAD[IOC_PAD_PC02].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PC03].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + + HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PC02_FUNC_CTL_GPIO_C_02; + HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PC03_FUNC_CTL_GPIO_C_03; + } else if (ptr == HPM_UART13) { + /* pull-up */ + HPM_IOC->PAD[IOC_PAD_PZ08].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PZ09].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + + /* PZ port IO needs to configure BIOC as well */ + HPM_IOC->PAD[IOC_PAD_PZ08].FUNC_CTL = IOC_PZ08_FUNC_CTL_GPIO_Z_08; + HPM_BIOC->PAD[IOC_PAD_PZ08].FUNC_CTL = BIOC_PZ08_FUNC_CTL_SOC_PZ_08; + + /* PZ port IO needs to configure BIOC as well */ + HPM_IOC->PAD[IOC_PAD_PZ09].FUNC_CTL = IOC_PZ09_FUNC_CTL_GPIO_Z_09; + HPM_BIOC->PAD[IOC_PAD_PZ09].FUNC_CTL = BIOC_PZ09_FUNC_CTL_SOC_PZ_09; } } void init_lcd_pins(LCDC_Type *ptr) { + (void)ptr; + HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_DIS0_R_0; HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_DIS0_R_1; HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PB00_FUNC_CTL_DIS0_R_2; @@ -85,6 +120,12 @@ void init_cap_pins(void) HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_GPIO_B_09; } +void init_trgmux_pins(uint32_t pin) +{ + /* all trgmux pin ALT_SELECT fixed to 16*/ + HPM_IOC->PAD[pin].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16); +} + void init_i2c_pins_as_gpio(I2C_Type *ptr) { if (ptr == HPM_I2C0) { @@ -92,7 +133,8 @@ void init_i2c_pins_as_gpio(I2C_Type *ptr) HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_GPIO_B_11; HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_GPIO_B_10; } else { - while(1); + while (1) { + } } } @@ -113,7 +155,8 @@ void init_i2c_pins(I2C_Type *ptr) HPM_IOC->PAD[IOC_PAD_PB14].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; HPM_IOC->PAD[IOC_PAD_PB13].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; } else { - while(1); + while (1) { + } } } @@ -162,25 +205,75 @@ void init_sdram_pins(void) HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PC31_FUNC_CTL_FEMC_DM_1; } +void init_sram_pins(void) +{ + /* Non-MUX */ /* MUX */ + HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A0 */ /* A16 */ + HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A1 */ /* A17 */ + HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A2 */ /* A18 */ + HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A3 */ /* A19 */ + HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A4 */ /* A20 */ + HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A5 */ /* A21 */ + HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A6 */ /* A22 */ + HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A7 */ /* A23 */ + HPM_IOC->PAD[IOC_PAD_PC01].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A8 */ + HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A9 */ + HPM_IOC->PAD[IOC_PAD_PB31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A10 */ + HPM_IOC->PAD[IOC_PAD_PB28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A11 */ + HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A12 */ + HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A13 */ + HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A14 */ + HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A15 */ + HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A16 */ + HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A17 */ + HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A18 */ + HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A19 */ + HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A20 */ + HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A21 */ + HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A22 */ + HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A23 */ + + HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D0 */ /* AD0 */ + HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D1 */ /* AD1 */ + HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D2 */ /* AD2 */ + HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D3 */ /* AD3 */ + HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D4 */ /* AD4 */ + HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D5 */ /* AD5 */ + HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D6 */ /* AD6 */ + HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D7 */ /* AD7 */ + HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D8 */ /* AD8 */ + HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D9 */ /* AD9 */ + HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D10 */ /* AD10 */ + HPM_IOC->PAD[IOC_PAD_PD06].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D11 */ /* AD11 */ + HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D12 */ /* AD12 */ + HPM_IOC->PAD[IOC_PAD_PD09].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D13 */ /* AD13 */ + HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D14 */ /* AD14 */ + HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D15 */ /* AD15 */ + + HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #CE */ + HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #OE */ + HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #WE */ + HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #UB */ + HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #LB */ + HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #ADV */ +} + void init_gpio_pins(void) { uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); - /* Green LED*/ - HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_GPIO_B_18; - HPM_IOC->PAD[IOC_PAD_PB18].PAD_CTL = pad_ctl; - #ifdef USING_GPIO0_FOR_GPIOZ HPM_IOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_GPIO_Z_02; HPM_IOC->PAD[IOC_PAD_PZ02].PAD_CTL = pad_ctl; - HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_SOC_PZ_02; + /* PZ port IO needs to configure BIOC as well */ + HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = BIOC_PZ02_FUNC_CTL_SOC_PZ_02; #endif } void init_spi_pins(SPI_Type *ptr) { if (ptr == HPM_SPI1) { - HPM_IOC->PAD[IOC_PAD_PE03].FUNC_CTL = IOC_PE03_FUNC_CTL_GPIO_E_03; + HPM_IOC->PAD[IOC_PAD_PE03].FUNC_CTL = IOC_PE03_FUNC_CTL_SPI1_CSN; HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_SPI1_MOSI; HPM_IOC->PAD[IOC_PAD_PD30].FUNC_CTL = IOC_PD30_FUNC_CTL_SPI1_MISO; HPM_IOC->PAD[IOC_PAD_PD31].FUNC_CTL = IOC_PD31_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); @@ -197,23 +290,59 @@ void init_spi_pins(SPI_Type *ptr) } } +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + if (ptr == HPM_SPI1) { + HPM_IOC->PAD[IOC_PAD_PE03].FUNC_CTL = IOC_PE03_FUNC_CTL_GPIO_E_03; + HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_SPI1_MOSI; + HPM_IOC->PAD[IOC_PAD_PD30].FUNC_CTL = IOC_PD30_FUNC_CTL_SPI1_MISO; + HPM_IOC->PAD[IOC_PAD_PD31].FUNC_CTL = IOC_PD31_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + } else if (ptr == HPM_SPI2) { + HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PB24_FUNC_CTL_GPIO_B_24; + HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_SPI2_MOSI; + HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PB25_FUNC_CTL_SPI2_MISO; + HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_SPI2_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + } else if (ptr == HPM_SPI3) { + HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PB29_FUNC_CTL_GPIO_B_29; + HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PB30_FUNC_CTL_SPI3_MOSI; + HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PC03_FUNC_CTL_SPI3_MISO; + HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PC02_FUNC_CTL_SPI3_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + } +} + void init_pins(void) { - init_uart_pins(BOARD_CONSOLE_BASE); +#ifdef BOARD_CONSOLE_UART_BASE + init_uart_pins(BOARD_CONSOLE_UART_BASE); +#endif init_sdram_pins(); } void init_gptmr_pins(GPTMR_Type *ptr) { - if (ptr == HPM_GPTMR4) { - /* TMR4 capture 1 */ - HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PE25_FUNC_CTL_GPTMR4_CAPT_1; - } else if (ptr == HPM_GPTMR5) { + if (ptr == HPM_GPTMR5) { + /* TMR5 capture 0 */ + HPM_IOC->PAD[IOC_PAD_PF06].FUNC_CTL = IOC_PF06_FUNC_CTL_GPTMR5_CAPT_1; /* TMR5 compare 0 */ HPM_IOC->PAD[IOC_PAD_PF04].FUNC_CTL = IOC_PF04_FUNC_CTL_GPTMR5_COMP_0; + /* TMR5 compare 1*/ + HPM_IOC->PAD[IOC_PAD_PF09].FUNC_CTL = IOC_PF09_FUNC_CTL_GPTMR5_COMP_1; } } +void init_hall_trgm_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PD19].FUNC_CTL = IOC_PD19_FUNC_CTL_TRGM2_P_09; + HPM_IOC->PAD[IOC_PAD_PD23].FUNC_CTL = IOC_PD23_FUNC_CTL_TRGM2_P_11; + HPM_IOC->PAD[IOC_PAD_PD24].FUNC_CTL = IOC_PD24_FUNC_CTL_TRGM2_P_10; +} + +void init_qei_trgm_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PD16].FUNC_CTL = IOC_PD16_FUNC_CTL_TRGM2_P_06; + HPM_IOC->PAD[IOC_PAD_PD20].FUNC_CTL = IOC_PD20_FUNC_CTL_TRGM2_P_07; +} + void init_i2s_pins(I2S_Type *ptr) { if (ptr == HPM_I2S0) { @@ -235,14 +364,15 @@ void init_pdm_pins(void) { HPM_IOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_PDM0_CLK; HPM_IOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_PDM0_D_0; - HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_SOC_PY_10; - HPM_PIOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_SOC_PY_11; + /* PY port IO needs to configure PIOC as well */ + HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = PIOC_PY10_FUNC_CTL_SOC_PY_10; + HPM_PIOC->PAD[IOC_PAD_PY11].FUNC_CTL = PIOC_PY11_FUNC_CTL_SOC_PY_11; } void init_vad_pins(void) { - HPM_PIOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY10_FUNC_CTL_VAD_CLK; - HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY11_FUNC_CTL_VAD_DAT; + HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = PIOC_PY10_FUNC_CTL_VAD_CLK; + HPM_PIOC->PAD[IOC_PAD_PY11].FUNC_CTL = PIOC_PY11_FUNC_CTL_VAD_DAT; } void init_cam_pins(CAM_Type *ptr) @@ -265,31 +395,39 @@ void init_cam_pins(CAM_Type *ptr) void init_butn_pins(void) { - HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_PBUTN; - HPM_BIOC->PAD[IOC_PAD_PZ03].FUNC_CTL = IOC_PZ03_FUNC_CTL_WBUTN; - HPM_BIOC->PAD[IOC_PAD_PZ04].FUNC_CTL = IOC_PZ04_FUNC_CTL_PLED; - HPM_BIOC->PAD[IOC_PAD_PZ05].FUNC_CTL = IOC_PZ05_FUNC_CTL_WLED; + HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = BIOC_PZ02_FUNC_CTL_PBUTN; + HPM_BIOC->PAD[IOC_PAD_PZ03].FUNC_CTL = BIOC_PZ03_FUNC_CTL_WBUTN; + HPM_BIOC->PAD[IOC_PAD_PZ04].FUNC_CTL = BIOC_PZ04_FUNC_CTL_PLED; + HPM_BIOC->PAD[IOC_PAD_PZ05].FUNC_CTL = BIOC_PZ05_FUNC_CTL_WLED; } void init_acmp_pins(void) { + /* configure to ACMP_COMP_1(ALT16) function */ + HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PE25_FUNC_CTL_ACMP_COMP_1; + /* configure to CMP1_INP7 function */ + HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + /* configure to CMP1_INN6 function */ + HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; } void init_enet_pins(ENET_Type *ptr) { if (ptr == HPM_ENET1) { - /* RST */ HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = IOC_PD15_FUNC_CTL_GPIO_D_15; HPM_IOC->PAD[IOC_PAD_PD11].FUNC_CTL = IOC_PD11_FUNC_CTL_ETH1_MDC; HPM_IOC->PAD[IOC_PAD_PD14].FUNC_CTL = IOC_PD14_FUNC_CTL_ETH1_MDIO; - HPM_IOC->PAD[IOC_PAD_PE14].FUNC_CTL = IOC_PE14_FUNC_CTL_ETH1_TXEN; - HPM_IOC->PAD[IOC_PAD_PE15].FUNC_CTL = IOC_PE15_FUNC_CTL_ETH1_RXDV; - HPM_IOC->PAD[IOC_PAD_PE16].FUNC_CTL = IOC_PE16_FUNC_CTL_ETH1_REFCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; - HPM_IOC->PAD[IOC_PAD_PE17].FUNC_CTL = IOC_PE17_FUNC_CTL_ETH1_TXD_1; + HPM_IOC->PAD[IOC_PAD_PE18].FUNC_CTL = IOC_PE18_FUNC_CTL_ETH1_RXD_1; HPM_IOC->PAD[IOC_PAD_PE19].FUNC_CTL = IOC_PE19_FUNC_CTL_ETH1_TXD_0; HPM_IOC->PAD[IOC_PAD_PE20].FUNC_CTL = IOC_PE20_FUNC_CTL_ETH1_RXD_0; + + HPM_IOC->PAD[IOC_PAD_PE14].FUNC_CTL = IOC_PE14_FUNC_CTL_ETH1_TXEN; + HPM_IOC->PAD[IOC_PAD_PE15].FUNC_CTL = IOC_PE15_FUNC_CTL_ETH1_RXDV; + HPM_IOC->PAD[IOC_PAD_PE17].FUNC_CTL = IOC_PE17_FUNC_CTL_ETH1_TXD_1; + + HPM_IOC->PAD[IOC_PAD_PE16].FUNC_CTL = IOC_PAD_FUNC_CTL_LOOP_BACK_MASK | IOC_PE16_FUNC_CTL_ETH1_REFCLK; } } @@ -301,23 +439,34 @@ void init_pwm_pins(PWM_Type *ptr) HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PB26_FUNC_CTL_PWM0_P_5; HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PB27_FUNC_CTL_PWM0_P_4; } else if (ptr == HPM_PWM1) { - HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_PWM1_P_1; - HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_PWM1_P_0; + HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_PWM1_P_3; + HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_PWM1_P_2; + HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PB24_FUNC_CTL_PWM1_P_5; + HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PB25_FUNC_CTL_PWM1_P_4; + HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PB29_FUNC_CTL_PWM1_P_7; + HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PB30_FUNC_CTL_PWM1_P_6; } else if (ptr == HPM_PWM3) { HPM_IOC->PAD[IOC_PAD_PE05].FUNC_CTL = IOC_PE05_FUNC_CTL_PWM3_P_4; } } -void init_adc_pins(void) +void init_adc12_pins(void) { - /* ADC0/1/2/.VINP7 */ - HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - /* ADC0/1/2/.VINP8 */ - HPM_IOC->PAD[IOC_PAD_PE22].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - /* ADC0/1/2/.VINP9 */ - HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - /* ADC0/1/2/.VINP10 */ - HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + /* ADC0.VINP14 */ + HPM_IOC->PAD[IOC_PAD_PE28].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_adc16_pins(void) +{ + /* ADC3.INA2 */ + HPM_IOC->PAD[IOC_PAD_PE29].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_adc_bldc_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PE15].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PE16].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PE17].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; } void init_usb_pins(USB_Type *ptr) @@ -325,8 +474,11 @@ void init_usb_pins(USB_Type *ptr) if (ptr == HPM_USB0) { /* USB0 ID */ HPM_IOC->PAD[IOC_PAD_PF10].FUNC_CTL = IOC_PF10_FUNC_CTL_GPIO_F_10; + HPM_IOC->PAD[IOC_PAD_PF10].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); + /* USB0 OC */ HPM_IOC->PAD[IOC_PAD_PF08].FUNC_CTL = IOC_PF08_FUNC_CTL_GPIO_F_08; + HPM_IOC->PAD[IOC_PAD_PF08].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); } } @@ -338,55 +490,70 @@ void init_can_pins(CAN_Type *ptr) } } -void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8) +void init_sdxc_cmd_pin(SDXC_Type *ptr, bool open_drain, bool is_1v8) { uint32_t cmd_func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); - uint32_t func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17); - uint32_t pad_ctl = IOC_PAD_PAD_CTL_MS_SET(use_1v8) | IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | - IOC_PAD_PAD_CTL_PS_SET(1); + uint32_t cmd_pad_ctl = IOC_PAD_PAD_CTL_MS_SET(is_1v8) | IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | + IOC_PAD_PAD_CTL_PS_SET(1); + if (open_drain) { + cmd_pad_ctl |= IOC_PAD_PAD_CTL_OD_MASK; + } if (ptr == HPM_SDXC1) { - /* SDXC1.CLK */ - HPM_IOC->PAD[IOC_PAD_PD22].FUNC_CTL = func_ctl; - HPM_IOC->PAD[IOC_PAD_PD22].PAD_CTL = pad_ctl; - /* SDXC1.CMD */ HPM_IOC->PAD[IOC_PAD_PD21].FUNC_CTL = cmd_func_ctl; - HPM_IOC->PAD[IOC_PAD_PD21].PAD_CTL = pad_ctl; - - /* SDXC1.DATA0 */ - HPM_IOC->PAD[IOC_PAD_PD18].FUNC_CTL = func_ctl; - HPM_IOC->PAD[IOC_PAD_PD18].PAD_CTL = pad_ctl; - /* SDXC1.DATA1 */ - HPM_IOC->PAD[IOC_PAD_PD17].FUNC_CTL = func_ctl; - HPM_IOC->PAD[IOC_PAD_PD17].PAD_CTL = pad_ctl; - /* SDXC1.DATA2 */ - HPM_IOC->PAD[IOC_PAD_PD27].FUNC_CTL = func_ctl; - HPM_IOC->PAD[IOC_PAD_PD27].PAD_CTL = pad_ctl; - /* SDXC1.DATA3 */ - HPM_IOC->PAD[IOC_PAD_PD26].FUNC_CTL = func_ctl; - HPM_IOC->PAD[IOC_PAD_PD26].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PD21].PAD_CTL = cmd_pad_ctl; } } -void init_sdxc_power_pin(SDXC_Type *ptr) +void init_sdxc_cd_pin(SDXC_Type *ptr, bool as_gpio) { - + uint32_t cd_pad_ctl = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + if (ptr == HPM_SDXC1) { + /* SDXC1.CDN */ + uint32_t cd_func_alt = as_gpio ? IOC_PD28_FUNC_CTL_GPIO_D_28 : IOC_PD28_FUNC_CTL_SDC1_CDN; + HPM_IOC->PAD[IOC_PAD_PD28].FUNC_CTL = cd_func_alt; + HPM_IOC->PAD[IOC_PAD_PD28].PAD_CTL = cd_pad_ctl; + } } -void init_sdxc_vsel_pin(SDXC_Type *ptr) + +void init_sdxc_vsel_pin(SDXC_Type *ptr, bool as_gpio) { - /* SDXC1.VSEL */ - HPM_IOC->PAD[IOC_PAD_PD29].FUNC_CTL = IOC_PD29_FUNC_CTL_SDC1_VSEL; - HPM_IOC->PAD[IOC_PAD_PD28].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | - IOC_PAD_PAD_CTL_PS_SET(1); + uint32_t vsel_pad_ctl = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + if (ptr == HPM_SDXC1) { + uint32_t vsel_func_alt = as_gpio ? IOC_PD29_FUNC_CTL_GPIO_D_29 : IOC_PD29_FUNC_CTL_SDC1_VSEL; + HPM_IOC->PAD[IOC_PAD_PD29].FUNC_CTL = vsel_func_alt; + HPM_IOC->PAD[IOC_PAD_PD29].PAD_CTL = vsel_pad_ctl; + } } -void init_sdxc_card_detection_pin(SDXC_Type *ptr) +void init_sdxc_clk_data_pins(SDXC_Type *ptr, uint32_t width, bool is_1v8) { - /* SDXC1.CDN */ - HPM_IOC->PAD[IOC_PAD_PD28].FUNC_CTL = IOC_PD28_FUNC_CTL_SDC1_CDN; - HPM_IOC->PAD[IOC_PAD_PD28].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | + uint32_t func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17); + uint32_t pad_ctl = IOC_PAD_PAD_CTL_MS_SET(is_1v8) | IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + + if (ptr == HPM_SDXC1) { + /* SDXC1.CLK */ + HPM_IOC->PAD[IOC_PAD_PD22].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD22].PAD_CTL = pad_ctl; + + /* SDXC1.DATA0 */ + HPM_IOC->PAD[IOC_PAD_PD18].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD18].PAD_CTL = pad_ctl; + if ((width == 4)) { + /* SDXC1.DATA1 */ + HPM_IOC->PAD[IOC_PAD_PD17].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD17].PAD_CTL = pad_ctl; + /* SDXC1.DATA2 */ + HPM_IOC->PAD[IOC_PAD_PD27].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD27].PAD_CTL = pad_ctl; + /* SDXC1.DATA3 */ + HPM_IOC->PAD[IOC_PAD_PD26].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD26].PAD_CTL = pad_ctl; + } + } + } void init_clk_obs_pins(void) @@ -422,12 +589,21 @@ void init_led_pins_as_pwm(void) void init_led_pins_as_gpio(void) { - uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); - HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_GPIO_B_18; - HPM_IOC->PAD[IOC_PAD_PB18].PAD_CTL = pad_ctl; HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_GPIO_B_19; - HPM_IOC->PAD[IOC_PAD_PB19].PAD_CTL = pad_ctl; HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_GPIO_B_20; - HPM_IOC->PAD[IOC_PAD_PB20].PAD_CTL = pad_ctl; +} + +void init_enet_pps_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PF05].FUNC_CTL = IOC_PF05_FUNC_CTL_ETH0_EVTO_0; + HPM_IOC->PAD[IOC_PAD_PF06].FUNC_CTL = IOC_PF06_FUNC_CTL_ETH0_EVTO_1; + HPM_IOC->PAD[IOC_PAD_PF09].FUNC_CTL = IOC_PF09_FUNC_CTL_ETH0_EVTO_2; +} + +void init_tamper_pins(void) +{ + HPM_BIOC->PAD[IOC_PAD_PZ08].FUNC_CTL = BIOC_PZ08_FUNC_CTL_TAMP_08 | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_BIOC->PAD[IOC_PAD_PZ09].FUNC_CTL = BIOC_PZ09_FUNC_CTL_TAMP_09; + HPM_BIOC->PAD[IOC_PAD_PZ10].FUNC_CTL = BIOC_PZ10_FUNC_CTL_TAMP_10; } diff --git a/bsp/hpmicro/hpm6750evkmini/board/pinmux.h b/bsp/hpmicro/hpm6750evkmini/board/pinmux.h index 44664ae7f06..f8689ccf042 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/pinmux.h +++ b/bsp/hpmicro/hpm6750evkmini/board/pinmux.h @@ -13,12 +13,15 @@ extern "C" { #endif void init_uart_pins(UART_Type *ptr); +void init_uart_pin_as_gpio(UART_Type *ptr); void init_lcd_pins(LCDC_Type *ptr); void init_i2c_pins(I2C_Type *ptr); void init_cap_pins(void); void init_sdram_pins(void); +void init_sram_pins(void); void init_gpio_pins(void); void init_spi_pins(SPI_Type *ptr); +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); void init_pins(void); void init_gptmr_pins(GPTMR_Type *ptr); void init_hall_trgm_pins(void); @@ -36,10 +39,12 @@ void init_pwm_pins(PWM_Type *ptr); void init_adc_pins(void); void init_usb_pins(USB_Type *ptr); void init_can_pins(CAN_Type *ptr); -void init_sdxc_power_pin(SDXC_Type *ptr); -void init_sdxc_vsel_pin(SDXC_Type *ptr); -void init_sdxc_card_detection_pin(SDXC_Type *ptr); -void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8); +void init_sdxc_cmd_pin(SDXC_Type *ptr, bool open_drain, bool is_1v8); +void init_sdxc_cd_pin(SDXC_Type *ptr, bool as_gpio); +void init_sdxc_clk_data_pins(SDXC_Type *ptr, uint32_t width, bool is_1v8); +void init_sdxc_vsel_pin(SDXC_Type *ptr, bool as_gpio); +void init_adc12_pins(void); +void init_adc16_pins(void); void init_adc_bldc_pins(void); void init_i2c_pins_as_gpio(I2C_Type *ptr); @@ -47,6 +52,10 @@ void init_i2c_pins_as_gpio(I2C_Type *ptr); void init_beep_pwm_pins(void); void init_led_pins_as_pwm(void); void init_led_pins_as_gpio(void); +void init_trgmux_pins(uint32_t pin); +void init_enet_pps_pins(void); +void init_tamper_pins(void); + #ifdef __cplusplus } #endif diff --git a/bsp/hpmicro/hpm6750evkmini/board/rtt_board.c b/bsp/hpmicro/hpm6750evkmini/board/rtt_board.c index a684a369d3e..293167c529c 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/rtt_board.c +++ b/bsp/hpmicro/hpm6750evkmini/board/rtt_board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2024 HPMicro * SPDX-License-Identifier: BSD-3-Clause * */ @@ -8,18 +8,34 @@ #include "rtt_board.h" #include "hpm_uart_drv.h" #include "hpm_gpio_drv.h" -#include "hpm_mchtmr_drv.h" #include "hpm_pmp_drv.h" #include "assert.h" #include "hpm_clock_drv.h" #include "hpm_sysctl_drv.h" #include #include -#include "hpm_dma_manager.h" +#include "hpm_dma_mgr.h" +#include "hpm_mchtmr_drv.h" +extern int rt_hw_uart_init(void); void os_tick_config(void); +void rtt_board_init(void); -extern int rt_hw_uart_init(void); +void rt_hw_board_init(void) +{ + rtt_board_init(); + + /* Call the RT-Thread Component Board Initialization */ + rt_components_board_init(); +} + +void os_tick_config(void) +{ + sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1); + sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0); + mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND); + enable_mchtmr_irq(); +} void rtt_board_init(void) { @@ -27,7 +43,7 @@ void rtt_board_init(void) board_init_console(); board_init_pmp(); - dma_manager_init(); + dma_mgr_init(); /* initialize memory system */ rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); @@ -72,24 +88,6 @@ void app_led_write(uint32_t index, bool state) } } -void os_tick_config(void) -{ - sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1); - sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0); - - mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND); - - enable_mchtmr_irq(); -} - -void rt_hw_board_init(void) -{ - rtt_board_init(); - - /* Call the RT-Thread Component Board Initialization */ - rt_components_board_init(); -} - void rt_hw_console_output(const char *str) { while (*str != '\0') @@ -98,21 +96,18 @@ void rt_hw_console_output(const char *str) } } +void app_init_usb_pins(void) +{ + board_init_usb_pins(); +} + ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) { HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND; - rt_interrupt_enter(); rt_tick_increase(); - rt_interrupt_leave(); } -void rt_hw_us_delay(rt_uint32_t us) -{ - clock_cpu_delay_us(us); -} - - void rt_hw_cpu_reset(void) { HPM_PPOR->RESET_ENABLE = (1UL << 31); @@ -125,4 +120,4 @@ void rt_hw_cpu_reset(void) } } -MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board); \ No newline at end of file +MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board); diff --git a/bsp/hpmicro/hpm6750evkmini/board/rtt_board.h b/bsp/hpmicro/hpm6750evkmini/board/rtt_board.h index 100b5dbb0ad..474555a89a0 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/rtt_board.h +++ b/bsp/hpmicro/hpm6750evkmini/board/rtt_board.h @@ -20,8 +20,8 @@ #define APP_LED2_GPIO_CTRL HPM_GPIO0 #define APP_LED2_GPIO_INDEX GPIO_DI_GPIOB #define APP_LED2_GPIO_PIN 20 -#define APP_LED_ON (0) -#define APP_LED_OFF (1) +#define APP_LED_ON (1) +#define APP_LED_OFF (0) @@ -38,6 +38,19 @@ /* CAN section */ #define BOARD_CAN_NAME "can1" +#define BOARD_CAN_HWFILTER_INDEX (1U) + +/* PWM section */ +#define BOARD_PWM_NAME "pwm1" +#define BOARD_PWM_CHANNEL (2) + +/* UART section */ +#define BOARD_UART_NAME "uart13" +#define BOARD_UART_RX_BUFFER_SIZE BSP_UART13_RX_BUFSIZE + +#define BOARD_SD_NAME "sd1" + +#define IRQn_PendSV IRQn_DEBUG_0 /*************************************************************** * @@ -65,7 +78,7 @@ extern "C" { void app_init_led_pins(void); void app_led_write(uint32_t index, bool state); - +void app_init_usb_pins(void); #if defined(__cplusplus) diff --git a/bsp/hpmicro/hpm6750evkmini/board/rw007_port.c b/bsp/hpmicro/hpm6750evkmini/board/rw007_port.c index 5ce069ff643..c0db34fcc9f 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/rw007_port.c +++ b/bsp/hpmicro/hpm6750evkmini/board/rw007_port.c @@ -118,4 +118,4 @@ void spi_wifi_int_cmd(rt_bool_t cmd) rt_pin_irq_enable(RW007_INT_BUSY_PIN, cmd); } -#endif /* if defined(RT_USING_WIFI) && defined(BSP_USING_SPI1) */ +#endif /* ifdefined(RT_USING_WIFI) && defined(BSP_USING_SPI1) */ diff --git a/bsp/hpmicro/hpm6750evkmini/rtconfig.h b/bsp/hpmicro/hpm6750evkmini/rtconfig.h index 40753e19552..ed2766da40a 100644 --- a/bsp/hpmicro/hpm6750evkmini/rtconfig.h +++ b/bsp/hpmicro/hpm6750evkmini/rtconfig.h @@ -17,14 +17,17 @@ #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 512 +#define IDLE_THREAD_STACK_SIZE 1024 #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_THREAD_STACK_SIZE 1024 /* kservice optimization */ +/* klibc optimization */ + + /* Inter-Thread communication */ #define RT_USING_SEMAPHORE @@ -43,7 +46,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart0" -#define RT_VER_NUM 0x50100 +#define RT_VER_NUM 0x50200 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* RT-Thread Components */ @@ -78,7 +81,6 @@ #define RT_USING_SERIAL #define RT_USING_SERIAL_V1 #define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_RTC #define RT_USING_PIN /* Using USB */ @@ -179,20 +181,15 @@ /* peripheral libraries and drivers */ -/* HAL & SDK Drivers */ - -/* STM32 HAL & SDK Drivers */ - - -/* Kendryte SDK */ - - /* sensors drivers */ /* touch drivers */ +/* Kendryte SDK */ + + /* AI packages */ diff --git a/bsp/hpmicro/hpm6750evkmini/rtconfig.py b/bsp/hpmicro/hpm6750evkmini/rtconfig.py index f199f0f3653..d0781627b3f 100644 --- a/bsp/hpmicro/hpm6750evkmini/rtconfig.py +++ b/bsp/hpmicro/hpm6750evkmini/rtconfig.py @@ -81,8 +81,8 @@ LFLAGS += ' -O0' LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' elif BUILD == 'ram_release': - CFLAGS += ' -O2 -Os' - LFLAGS += ' -O2 -Os' + CFLAGS += ' -O2' + LFLAGS += ' -O2' LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' elif BUILD == 'flash_debug': CFLAGS += ' -gdwarf-2' @@ -92,13 +92,13 @@ CFLAGS += ' -DFLASH_XIP=1' LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' elif BUILD == 'flash_release': - CFLAGS += ' -O2 -Os' - LFLAGS += ' -O2 -Os' + CFLAGS += ' -O2' + LFLAGS += ' -O2' CFLAGS += ' -DFLASH_XIP=1' LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' else: - CFLAGS += ' -O2 -Os' - LFLAGS += ' -O2 -Os' + CFLAGS += ' -O2' + LFLAGS += ' -O2' LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' LFLAGS += ' -T ' + LINKER_FILE diff --git a/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/start.S b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/start.S index 5c47c92afe7..238e05b43bb 100644 --- a/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/start.S +++ b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/start.S @@ -25,6 +25,15 @@ _start: ori t1, t1, 0x80 sw t1, 0(t0) +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + #ifdef INIT_EXT_RAM_FOR_DATA la t0, _stack_in_dlm mv sp, t0 diff --git a/bsp/hpmicro/hpm6800evk/.config b/bsp/hpmicro/hpm6800evk/.config new file mode 100644 index 00000000000..df2b1e92fd4 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/.config @@ -0,0 +1,1096 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=1024 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024 + +# +# kservice optimization +# +# CONFIG_RT_USING_TINY_FFS is not set + +# +# klibc optimization +# +# CONFIG_RT_KLIBC_USING_STDLIB is not set +# CONFIG_RT_KLIBC_USING_TINY_SIZE is not set +# CONFIG_RT_KLIBC_USING_PRINTF_LONGLONG is not set +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +# CONFIG_RT_USING_SCHED_THREAD_CTX is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x50200 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# CONFIG_RT_USING_CACHE is not set +# CONFIG_RT_USING_HW_ATOMIC is not set +# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_USING_HW_THREAD_SELF is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_USING_SERIAL_V1 is not set +CONFIG_RT_USING_SERIAL_V2=y +CONFIG_RT_SERIAL_USING_DMA=y +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_SPI_BITOPS is not set +# CONFIG_RT_USING_QSPI is not set +# CONFIG_RT_USING_SPI_MSD is not set +# CONFIG_RT_USING_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set + +# +# peripheral libraries and drivers +# + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ESP_IDF is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set + +# +# Uncategorized +# + +# +# Hardware Drivers Config +# +CONFIG_SOC_HPM6000=y +# CONFIG_BSP_USING_ENET_PHY_RTL8211 is not set + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_UART0_RX_USING_DMA is not set +# CONFIG_BSP_UART0_TX_USING_DMA is not set +CONFIG_BSP_UART0_RX_BUFSIZE=128 +CONFIG_BSP_UART0_TX_BUFSIZE=0 +CONFIG_BSP_USING_UART3=y +# CONFIG_BSP_UART3_RX_USING_DMA is not set +# CONFIG_BSP_UART3_TX_USING_DMA is not set +CONFIG_BSP_UART3_RX_BUFSIZE=1024 +CONFIG_BSP_UART3_TX_BUFSIZE=0 +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_ETH is not set +# CONFIG_BSP_USING_SDXC is not set +# CONFIG_BSP_USING_TOUCH is not set +# CONFIG_BSP_USING_LCD is not set +# CONFIG_BSP_USING_LVGL is not set +# CONFIG_BSP_USING_PDMA is not set +# CONFIG_BSP_USING_GPTMR is not set +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_FEMC is not set +# CONFIG_INIT_EXT_RAM_FOR_DATA is not set +# CONFIG_BSP_USING_XPI_FLASH is not set +# CONFIG_BSP_USING_DAO is not set +# CONFIG_BSP_USING_PDM is not set +# CONFIG_BSP_USING_I2S is not set +# CONFIG_BSP_USING_USB is not set +# CONFIG_BSP_USING_EWDG is not set +# CONFIG_BSP_USING_MCAN is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_CAMERA is not set +# CONFIG_BSP_USING_JPEG is not set +# CONFIG_BSP_USING_CAM is not set +# CONFIG_BSP_USING_PANEL is not set +# CONFIG_BSP_USING_PIXELMUX is not set +# CONFIG_BSP_USING_MIPI_CSI is not set +# CONFIG_BSP_USING_MIPI_DSI is not set +# CONFIG_BSP_USING_RTT_LCD_DRIVER is not set diff --git a/bsp/hpmicro/hpm6800evk/Kconfig b/bsp/hpmicro/hpm6800evk/Kconfig new file mode 100644 index 00000000000..79b160b8567 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/Kconfig @@ -0,0 +1,21 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" diff --git a/bsp/hpmicro/hpm6800evk/README.md b/bsp/hpmicro/hpm6800evk/README.md new file mode 100644 index 00000000000..651cd94dd0f --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/README.md @@ -0,0 +1,116 @@ +# HPMicro HPM6800EVK BSP(Board Support Package) Introduction + +[中文页](README_zh.md) | + +## Introduction + +This document provides brief introduction of the BSP (board support package) for the HPM6800EVK development board. + +The document consists of the following parts: + +- HPM6800EVK Board Resources Introduction +- Quickly Getting Started +- Refreences + +By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources. + +## Board Resources Introduction + +HPM6800EVK is a development board based on the RISC-V core launched by HPMicro, with rich on-board resources and on-chip resources for Display, Audio， motor control，etc. +![board](figures/board.png) + + +## Peripheral Condition + +Each peripheral supporting condition for this BSP is as follows: + + +| **On-board Peripherals** | **Support** | **Note** | +| ------------------------ | ----------- | ------------------------------------- | +| USB | √ | | +| QSPI Flash | √ | | +| Ethernet | √ | | +| GPIO | √ | | +| SPI | √ | | +| I2C | √ | | +| SDIO | √ | | +| RTC | √ | | +| PWM | √ | | +| On-Board Debugger | √ | ft2232 | + + +## Execution Instruction + +### Quickly Getting Started + +The BSP support being build via the 'scons' command, below is the steps of compiling the example via the 'scons' command + +#### Parpare Environment +- Step 1: Prepare [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool) +- Step 2: Prepare [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) + - Download the package and extract it into a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain` +- Step 3: Set environment variable `RTT_RISCV_TOOLCHAIN` to `\bin` + - For example: `C:\DevTools\riscv32-gnu-toolchain\bin` +- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip) + - Download and extract it to specified directory, for example: `C:\DevTools\openocd-hpmicro` + - Add `OpenOCD` environment variable `OPENOCD_HPMICRO` to `\bin` + - For example: `C:\DevTools\openocd-hpmicro\bin` + +#### Configure and Build project + +Open RT-Thread ENV command-line, and change directory to this BSP directory, then users can: + +- Configure the project via `menuconfig` in `RT-Thread ENV` +- Build the project using `scons -jN`, `N` equals to the number of CPU cores +- Clean the project using `scons -c` + +#### Hardware Connection + +- Switch BOOT pin to 2'b00 +- Connect the `PWR_DEBUG` port to PC via TYPE-C cable + + +#### Dowload / Debug + +- Users can download the project via the below command: + ```console + %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6880.cfg -f boards\debug_scripts\boards\hpm6800evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + ``` + +- Users can debug the project via the below command: + + - Connect debugger via `OpenOCD`: + +```console +%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6880.cfg -f boards\debug_scripts\boards\hpm6800evk.cfg +``` + - Start Debugger via `GDB`: + +```console +%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf +``` + - In the `gdb shell`, type the following commands: + +```console +load +c +``` + +### **Running Results** + +Once the project is successfully downloaded, the system runs automatically. The LED on the board will flash periodically. + +Connect the serial port of the board to the PC, communicate with it via a serial terminal tool(115200-8-1-N). Reset the board and the startup information of RT-Thread will be observed: + +``` + \ | / +- RT - Thread Operating System + / | \ 5.0.1 build Aug 16 2023 18:18:18 + 2006 - 2023 Copyright by RT-Thread team +``` + +## **References** + +- [RT-Thread Documnent Center](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README) +- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md) +- [HPM6800EVK RT-Thread BSP Package](https://github.com/hpmicro/rtt-bsp-hpm6800evk) \ No newline at end of file diff --git a/bsp/hpmicro/hpm6800evk/README_zh.md b/bsp/hpmicro/hpm6800evk/README_zh.md new file mode 100644 index 00000000000..b9c07228894 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/README_zh.md @@ -0,0 +1,115 @@ +# 先楫 HPM6800EVK BSP(板级支持包)说明 + +[English](README.md) | + +## 简介 + +本文档为 HPM6800EVK 的 BSP (板级支持包) 说明。 + +本文包含如下部分: + +- HPM6800EVK 板级资源介绍 +- 快速上手指南 +- 参考链接 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 板级资源介绍 + +HPM6800EVK 是由先楫半导体推出的一款基于RISCV内核的开发板，带有丰富的片上资源和板上资源，可用于显示、音频和电机控制等应用。 + +开发板外观如下图所示： + +![board](figures/board.png) + + +## 板载外设 + +本 BSP 目前对外设的支持情况如下: + + +| **板载外设** | **支持情况** | **备注** | +| ------------------------ | ----------- | ------------------------------------- | +| USB | √ | | +| QSPI Flash | √ | | +| 以太网 | √ | | +| GPIO | √ | | +| SPI | √ | | +| I2C | √ | | +| SDIO | √ | | +| RTC | √ | | +| PWM | √ | | +| 板载调试器 | √ | ft2232 | + + +## 使用说明 + +### 快速开始 + +本BSP支持通过`scons`命令来完成编译，在开始之前，需要先准备好开发所需的环境。 + +#### 准备环境 +- 步骤 1: 准备 [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool) +- 步骤 2: 准备 [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) + - 下载并解压到指定的目录，如: `C:\DevTools\riscv32-gnu-toolchain` +- 步骤 3: 设置环境变量： `RTT_RISCV_TOOLCHAIN` 为 `\bin`， 如: `C:\DevTools\riscv32-gnu-toolchain\bin` +- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip) + - 下载并解压到指定目录，如: `C:\DevTools\openocd-hpmicro` + - 将 `OPENOCD_HPMICRO`环境变量设置为 `\bin`，如： `C:\DevTools\openocd-hpmicro\bin` + +#### 配置和构建工程 + +通过 RT-Thread ENV 命令行切换目录到当前BSP所在目录后，用户可以: + +- 通过 `menuconfig` 命令 配置RT-Thread BSP的功能 +- 通过 `scons -jN` 命令完成构建, 其中`N` 最大值可以指定为CP拥有的物理内核数 +- 通过 `scons -c` 命令清除构建 + +#### 硬件连接 + +- 将BOOT 引脚拨到2'b00 +- 通过 TYPE-C线将板上的 `PWR_DEBUG` 连接到电脑 + +#### 下载 和 调试 + +- 通过如下命令完成下载: + ```console + %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6880.cfg -f boards\debug_scripts\boards\hpm6800evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + ``` + +- 通过如下命令实现调试: + + - 通过 `OpenOCD` 来连接开发板: +```console +%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6880.cfg -f boards\debug_scripts\boards\hpm6800evk.cfg +``` + - 通过 `GDB` 实现调试: +```console +%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf +``` + + - 在`GDB Shell`中使用如下命令来加载和运行: + +```console +load +c +``` + +### **运行结果** + +一旦成功下载，程序会自动运行并打印如下结果，板载LED灯会周期性闪烁。 + +配置好串口终端(串口配置为115200, 8-N-1),按复位键后，串口终端会打印如下日志： + +``` + \ | / +- RT - Thread Operating System + / | \ 5.0.1 build Aug 16 2023 18:18:18 + 2006 - 2023 Copyright by RT-Thread team +``` + +## **参考链接** + +- [RT-Thread 文档中心](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README) +- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md) +- [HPM6800EVK RT-Thread BSP 包](https://github.com/hpmicro/rtt-bsp-hpm6800evk) \ No newline at end of file diff --git a/bsp/hpmicro/hpm6800evk/SConscript b/bsp/hpmicro/hpm6800evk/SConscript new file mode 100644 index 00000000000..014c428d0a3 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/SConscript @@ -0,0 +1,17 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +ASFLAGS = ' -I' + cwd + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/hpmicro/hpm6800evk/SConstruct b/bsp/hpmicro/hpm6800evk/SConstruct new file mode 100644 index 00000000000..3dadc575c01 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/SConstruct @@ -0,0 +1,75 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../../rt-thread') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +AddOption('--run', + dest = 'run', + type='string', + nargs=1, + action = 'store', + default = "", + help = 'Upload or debug application using openocd') + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(os.path.join(SDK_ROOT, 'libraries')): + libraries_path_prefix = os.path.join(SDK_ROOT, 'libraries') +else: + libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries') + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + + +GDB = rtconfig.GDB + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +hpm_library = 'hpm_sdk' +rtconfig.BSP_LIBRARY_TYPE = hpm_library + +# include soc +objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.CHIP_NAME, 'SConscript'))) + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript'))) + +# include components +objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript'))) + + +# includes rtt drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/hpmicro/hpm6800evk/applications/SConscript b/bsp/hpmicro/hpm6800evk/applications/SConscript new file mode 100644 index 00000000000..a65aa4d8553 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/applications/SConscript @@ -0,0 +1,14 @@ +import rtconfig + +from building import * + +cwd = GetCurrentDir() + +src = Glob('*.c') + +CPPDEFINES=[] +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm6800evk/applications/main.c b/bsp/hpmicro/hpm6800evk/applications/main.c new file mode 100644 index 00000000000..a5a7f07c737 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/applications/main.c @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * Change Logs: + * Date Author Notes + * 2021-08-13 Fan YANG first version + * + */ + +#include +#include +#include "rtt_board.h" + +void thread_entry(void *arg); + +int main(void) +{ + app_init_led_pins(); + + static uint32_t led_thread_arg = 0; + rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10); + rt_thread_startup(led_thread); + + return 0; +} + +void thread_entry(void *arg) +{ + while(1){ + app_led_write(0, APP_LED_ON); + rt_thread_mdelay(500); + app_led_write(0, APP_LED_OFF); + rt_thread_mdelay(500); + app_led_write(1, APP_LED_ON); + rt_thread_mdelay(500); + app_led_write(1, APP_LED_OFF); + rt_thread_mdelay(500); + app_led_write(2, APP_LED_ON); + rt_thread_mdelay(500); + app_led_write(2, APP_LED_OFF); + rt_thread_mdelay(500); + } +} diff --git a/bsp/hpmicro/hpm6800evk/board/Kconfig b/bsp/hpmicro/hpm6800evk/board/Kconfig new file mode 100644 index 00000000000..44139d760f1 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/board/Kconfig @@ -0,0 +1,453 @@ +menu "Hardware Drivers Config" + +config SOC_HPM6000 + bool + select SOC_SERIES_HPM6000 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +config BSP_USING_ENET_PHY_RTL8211 + bool + default n + +menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN if BSP_USING_GPIO + default n + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + menuconfig BSP_USING_UART0 + bool "Enable UART0 (Debugger)" + default y + if BSP_USING_UART0 + config BSP_UART0_RX_USING_DMA + bool "Enable UART0 RX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + config BSP_UART0_TX_USING_DMA + bool "Enable UART0 TX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + config BSP_UART0_RX_BUFSIZE + int "Set UART0 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART0_TX_BUFSIZE + int "Set UART0 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + menuconfig BSP_USING_UART3 + bool "Enable UART3" + default y + if BSP_USING_UART3 + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + config BSP_UART3_TX_USING_DMA + bool "Enable UART3 TX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + config BSP_UART3_RX_BUFSIZE + int "Set UART3 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART3_TX_BUFSIZE + int "Set UART3 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + + + menuconfig BSP_USING_SPI + bool "Enable SPI" + default n + select RT_USING_SPI if BSP_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI3 + bool "Enable SPI3" + default n + if BSP_USING_SPI3 + config BSP_SPI3_USING_DMA + bool "Enable SPI3 DMA" + default n + endif + endif + + menuconfig BSP_USING_RTC + bool "Enable RTC" + default n + + menuconfig BSP_USING_ETH + bool "Enable Ethernet" + default n + + select RT_USING_ETH + if BSP_USING_ETH + choice + prompt "ETH" + default BSP_USING_ETH0 + + config BSP_USING_ETH0 + bool "Enable ETH0" + select BSP_USING_ENET_PHY_RTL8211 + endchoice + endif + + menuconfig BSP_USING_SDXC + bool "Enable SDXC" + default n + select RT_USING_SDIO if BSP_USING_SDXC + if BSP_USING_SDXC + config BSP_USING_SDXC0 + bool "Enable SDXC0" + default n + if BSP_USING_SDXC0 + choice + prompt "Select BUS_WIDTH" + default BSP_SDXC0_BUS_WIDTH_8BIT + config BSP_SDXC0_BUS_WIDTH_1BIT + bool "1-bit" + config BSP_SDXC0_BUS_WIDTH_4BIT + bool "4-bit" + config BSP_SDXC0_BUS_WIDTH_8BIT + bool "8-bit" + endchoice + choice + prompt "Select Voltage" + default BSP_SDXC0_VOLTAGE_1V8 + config BSP_SDXC0_VOLTAGE_3V3 + bool "3.3V" + config BSP_SDXC0_VOLTAGE_1V8 + bool "1.8V" + config BSP_SDXC0_VOLTAGE_DUAL + bool "Dual voltage 3.3V / 1.8V" + endchoice + config BSP_SDXC0_VSEL_PIN + default "None" + string "VSEL pin name" + config BSP_SDXC0_PWR_PIN + default "None" + string "PWR pin name" + endif + + config BSP_USING_SDXC1 + bool "Enable SDXC1" + default y + if BSP_USING_SDXC1 + choice + prompt "Select BUS_WIDTH" + default BSP_SDXC1_BUS_WIDTH_4BIT + config BSP_SDXC1_BUS_WIDTH_1BIT + bool "1-bit" + config BSP_SDXC1_BUS_WIDTH_4BIT + bool "4-bit" + endchoice + choice + prompt "Select Voltage" + default BSP_SDXC1_VOLTAGE_3V3 + config BSP_SDXC1_VOLTAGE_3V3 + bool "3.3V" + config BSP_SDXC1_VOLTAGE_1V8 + bool "1.8V" + config BSP_SDXC1_VOLTAGE_DUAL + bool "Dual voltage 3.3V / 1.8V" + endchoice + config BSP_SDXC1_VSEL_PIN + default "PD12" + string "VSEL pin name" + config BSP_SDXC1_PWR_PIN + default "PD07" + string "PWR pin name" + endif + endif + + menuconfig BSP_USING_TOUCH + bool "Enable touch" + default n + if BSP_USING_TOUCH + config BSP_USING_TOUCH_GT911 + bool "Enable GT911" + default y + + config BSP_USING_TOUCH_FT5406 + bool "Enable FT5406" + default n + endif + + menuconfig BSP_USING_LCD + bool "Enable LCD" + default n + if BSP_USING_LCD + config BSP_USING_LCD_ISR + bool "Enable LCD interrupt" + default n + endif + + menuconfig BSP_USING_LVGL + bool "Enable LVGL" + default n + select PKG_USING_LVGL if BSP_USING_LVGL + select BSP_USING_PDMA if BSP_USING_LVGL + + menuconfig BSP_USING_PDMA + bool "Enable PDMA Driver" + default n + + menuconfig BSP_USING_GPTMR + bool "Enable GPTMR" + default n + select RT_USING_HWTIMER if BSP_USING_GPTMR + if BSP_USING_GPTMR + config BSP_USING_GPTMR1 + bool "Enable GPTMR1" + default n + config BSP_USING_GPTMR2 + bool "Enable GPTMR2" + default n + config BSP_USING_GPTMR3 + bool "Enable GPTMR3" + default n + config BSP_USING_GPTMR4 + bool "Enable GPTMR4" + default n + config BSP_USING_GPTMR5 + bool "Enable GPTMR5" + default n + config BSP_USING_GPTMR6 + bool "Enable GPTMR6" + default n + config BSP_USING_GPTMR7 + bool "Enable GPTMR7" + default n + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C" + default n + select RT_USING_I2C if BSP_USING_I2C + if BSP_USING_I2C + config BSP_USING_I2C0 + bool "Enable I2C0" + default y + config BSP_USING_I2C1 + bool "Enable I2C1" + default n + config BSP_USING_I2C3 + bool "Enable I2C3" + default n + endif + if BSP_USING_I2C0 + config BSP_I2C0_USING_DMA + bool "Enable I2C0 DMA" + default n + endif + if BSP_USING_I2C1 + config BSP_I2C1_USING_DMA + bool "Enable I2C1 DMA" + default n + endif + if BSP_USING_I2C3 + config BSP_I2C3_USING_DMA + bool "Enable I2C3 DMA" + default n + endif + + menuconfig BSP_USING_FEMC + bool "Enable DRAM" + default y + + menuconfig INIT_EXT_RAM_FOR_DATA + bool "INIT_EXT_RAM_FOR_DATA" + default y + + + menuconfig BSP_USING_XPI_FLASH + bool "Enable XPI FLASH" + default n + select RT_USING_FAL if BSP_USING_XPI_FLASH + + menuconfig BSP_USING_DAO + bool "Enable Audio DAO play" + default n + select RT_USING_AUDIO if BSP_USING_DAO + + menuconfig BSP_USING_PDM + bool "Enable Audio PDM record" + default n + select RT_USING_AUDIO if BSP_USING_PDM + + menuconfig BSP_USING_I2S + bool "Enable Audio I2S device" + default n + select RT_USING_AUDIO if BSP_USING_I2S + if BSP_USING_I2S + config BSP_USING_I2S3 + bool "Enable I2S3" + default y + config BSP_USING_AUDIO_CODEC_WM8960 + bool "Enable audio codec on board" + default y + endif + + menuconfig BSP_USING_USB + bool "Enable USB" + default n + if BSP_USING_USB + config BSP_USING_USB_DEVICE + bool "Enable USB Device" + default n + config BSP_USING_USB_HOST + bool "Enable USB Host" + select RT_USING_CACHE + default n + endif + + + menuconfig BSP_USING_EWDG + bool "Enable EWDG" + default n + select RT_USING_WDT if BSP_USING_EWDG + if BSP_USING_EWDG + config BSP_USING_EWDG0 + bool "Enable EWDG0" + default n + config BSP_USING_EWDG1 + bool "Enable EWDG1" + default n + endif + + menuconfig BSP_USING_MCAN + bool "Enable MCAN" + default n + select RT_USING_CAN if BSP_USING_MCAN + if BSP_USING_MCAN + config BSP_USING_MCAN0 + bool "Enable MCAN0" + default n + config BSP_USING_MCAN1 + bool "Enable MCAN1" + default n + config BSP_USING_MCAN2 + bool "Enable MCAN2" + default n + config BSP_USING_MCAN3 + bool "Enable MCAN3" + default n + config BSP_USING_MCAN4 + bool "Enable MCAN4" + default n + config BSP_USING_MCAN5 + bool "Enable MCAN5" + default n + config BSP_USING_MCAN6 + bool "Enable MCAN6" + default n + config BSP_USING_MCAN7 + bool "Enable MCAN7" + default n + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC if BSP_USING_ADC + if BSP_USING_ADC + menuconfig BSP_USING_ADC12 + bool "Enable ADC12" + default n + if BSP_USING_ADC12 + config BSP_USING_ADC0 + bool "Enable ADC0" + default n + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + config BSP_USING_ADC2 + bool "Enable ADC2" + default n + endif + menuconfig BSP_USING_ADC16 + bool "Enable ADC16" + default n + if BSP_USING_ADC16 + config BSP_USING_ADC3 + bool "Enable ADC3" + default n + endif + endif + + menuconfig BSP_USING_CAMERA + bool "Enable camera" + default n + if BSP_USING_CAMERA + config BSP_USING_CAMERA_MT9M114 + bool "Enable mt9m114" + default y + + config BSP_USING_CAMERA_OV5640 + bool "Enable ov5640" + default n + + config BSP_USING_CAMERA_OV7725 + bool "Enable ov7725" + default n + endif + + menuconfig BSP_USING_JPEG + bool "Enable JPEG Driver" + default n + + menuconfig BSP_USING_CAM + bool "Enable CAM Driver" + default n + + menuconfig BSP_USING_PANEL + bool "Enable panel" + default n + if BSP_USING_PANEL + config BSP_USEING_PANEL_RGB_TM070RDH13 + bool "Enable RGB TM070RDH13" + default n + config BSP_USEING_PANEL_MIPI_MC10128007_31B + bool "Enable MIPI MC10128007_31B" + default y + config BSP_USEING_PANEL_LVDS_TM103XDGP01 + bool "Enable LVDS TM103XDGP01" + default n + config BSP_USEING_PANEL_LVDS_CC10128007 + bool "Enable LVDS CC10128007" + default n + endif + + menuconfig BSP_USING_PIXELMUX + bool "Enable pixelmux Driver" + default n + + menuconfig BSP_USING_MIPI_CSI + bool "Enable MIPI CSI Driver" + default n + + menuconfig BSP_USING_MIPI_DSI + bool "Enable MIPI DSI Driver" + default n + menuconfig BSP_USING_RTT_LCD_DRIVER + bool "Enable RTT LCD Driver" + select BSP_USING_LCD + default n +endmenu + +endmenu + diff --git a/bsp/hpmicro/hpm6800evk/board/SConscript b/bsp/hpmicro/hpm6800evk/board/SConscript new file mode 100644 index 00000000000..d6bfd64ec29 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/board/SConscript @@ -0,0 +1,19 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers +src = Split(""" + board.c + rtt_board.c + pinmux.c + fal_flash_port.c + hpm_wm8960.c +""") + +CPPPATH = [cwd] +CPPDEFINES=['D45', 'HPM6880'] + +group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm6800evk/board/board.c b/bsp/hpmicro/hpm6800evk/board/board.c new file mode 100644 index 00000000000..a483ab39051 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/board/board.c @@ -0,0 +1,1489 @@ +/* + * Copyright (c) 2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + * + * + */ + +#include "board.h" +#include "hpm_uart_drv.h" +#include "hpm_gptmr_drv.h" +#include "hpm_lcdc_drv.h" +#include "hpm_i2c_drv.h" +#include "hpm_gpio_drv.h" +#include "pinmux.h" +#include "hpm_pmp_drv.h" +#include "hpm_clock_drv.h" +#include "hpm_sysctl_drv.h" +#include "hpm_pllctlv2_drv.h" +#include "hpm_sdxc_drv.h" +#include "hpm_ddrctl_regs.h" +#include "hpm_ddrphy_regs.h" +#include "hpm_pcfg_drv.h" +#include "hpm_pixelmux_drv.h" +#include "hpm_lvb_drv.h" +#include "hpm_enet_drv.h" +#include "hpm_usb_drv.h" +#include "hpm_mipi_dsi_drv.h" +#include "hpm_mipi_dsi_phy_drv.h" + +static board_timer_cb timer_cb; + +/** + * @brief FLASH configuration option definitions: + * option[0]: + * [31:16] 0xfcf9 - FLASH configuration option tag + * [15:4] 0 - Reserved + * [3:0] option words (exclude option[0]) + * option[1]: + * [31:28] Flash probe type + * 0 - SFDP SDR / 1 - SFDP DDR + * 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) + * 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V + * 6 - OctaBus DDR (SPI -> OPI DDR) + * 8 - Xccela DDR (SPI -> OPI DDR) + * 10 - EcoXiP DDR (SPI -> OPI DDR) + * [27:24] Command Pads after Power-on Reset + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [23:20] Command Pads after Configuring FLASH + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) + * 0 - Not needed + * 1 - QE bit is at bit 6 in Status Register 1 + * 2 - QE bit is at bit1 in Status Register 2 + * 3 - QE bit is at bit7 in Status Register 2 + * 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 + * [15:8] Dummy cycles + * 0 - Auto-probed / detected / default value + * Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet + * [7:4] Misc. + * 0 - Not used + * 1 - SPI mode + * 2 - Internal loopback + * 3 - External DQS + * [3:0] Frequency option + * 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz + * + * option[2] (Effective only if the bit[3:0] in option[0] > 1) + * [31:20] Reserved + * [19:16] IO voltage + * 0 - 3V / 1 - 1.8V + * [15:12] Pin group + * 0 - 1st group / 1 - 2nd group + * [11:8] Connection selection + * 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) + * [7:0] Drive Strength + * 0 - Default value + * option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports + * JESD216) + * [31:16] reserved + * [15:12] Sector Erase Command Option, not required here + * [11:8] Sector Size Option, not required here + * [7:0] Flash Size Option + * 0 - 4MB / 1 - 8MB / 2 - 16MB + */ +#if defined(FLASH_XIP) && FLASH_XIP +__attribute__((section(".nor_cfg_option"))) const uint32_t option[4] = { 0xfcf90001, 0x00000007, 0x0, 0x0 }; +#endif + +#if defined(FLASH_UF2) && FLASH_UF2 +ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; +#endif + +void board_init_console(void) +{ +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART + console_config_t cfg; + + /* uart needs to configure pin function before enabling clock, otherwise the level change of + * uart rx pin when configuring pin function will cause a wrong data to be received. + * And a uart rx dma request will be generated by default uart fifo dma trigger level. + */ + init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE); + + /* Configure the UART clock to 24MHz */ + clock_set_source_divider(BOARD_CONSOLE_UART_CLK_NAME, clk_src_osc24m, 1U); + clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0); + + cfg.type = BOARD_CONSOLE_TYPE; + cfg.base = (uint32_t) BOARD_CONSOLE_UART_BASE; + cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_UART_CLK_NAME); + cfg.baudrate = BOARD_CONSOLE_UART_BAUDRATE; + + if (status_success != console_init(&cfg)) { + /* failed to initialize debug console */ + while (1) { + } + } +#else + while (1) + ; +#endif +#endif +} + +void board_print_clock_freq(void) +{ + printf("==============================\n"); + printf(" %s clock summary\n", BOARD_NAME); + printf("==============================\n"); + printf("cpu0:\t\t %dHz\n", clock_get_frequency(clock_cpu0)); + printf("gpu0:\t\t %dHz\n", clock_get_frequency(clock_gpu0)); + printf("axis:\t\t %dHz\n", clock_get_frequency(clock_axis)); + printf("axic:\t\t %dHz\n", clock_get_frequency(clock_axic)); + printf("axif:\t\t %dHz\n", clock_get_frequency(clock_axif)); + printf("axid:\t\t %dHz\n", clock_get_frequency(clock_axid)); + printf("axiv:\t\t %dHz\n", clock_get_frequency(clock_axiv)); + printf("axig:\t\t %dHz\n", clock_get_frequency(clock_axig)); + printf("mchtmr0:\t %dHz\n", clock_get_frequency(clock_mchtmr0)); + printf("xpi0:\t\t %dHz\n", clock_get_frequency(clock_xpi0)); + printf("==============================\n"); +} + +void board_init_uart(UART_Type *ptr) +{ + /* configure uart's pin before opening uart's clock */ + init_uart_pins(ptr); + board_init_uart_clock(ptr); +} + +void board_print_banner(void) +{ + const uint8_t banner[] = { "\n\ +----------------------------------------------------------------------\n\ +$$\\ $$\\ $$$$$$$\\ $$\\ $$\\ $$\\\n\ +$$ | $$ |$$ __$$\\ $$$\\ $$$ |\\__|\n\ +$$ | $$ |$$ | $$ |$$$$\\ $$$$ |$$\\ $$$$$$$\\ $$$$$$\\ $$$$$$\\\n\ +$$$$$$$$ |$$$$$$$ |$$\\$$\\$$ $$ |$$ |$$ _____|$$ __$$\\ $$ __$$\\\n\ +$$ __$$ |$$ ____/ $$ \\$$$ $$ |$$ |$$ / $$ | \\__|$$ / $$ |\n\ +$$ | $$ |$$ | $$ |\\$ /$$ |$$ |$$ | $$ | $$ | $$ |\n\ +$$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\n\ +\\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n\ +----------------------------------------------------------------------\n" }; +#ifdef SDK_VERSION_STRING + printf("hpm_sdk: %s\n", SDK_VERSION_STRING); +#endif + printf("%s", banner); +} + + +uint8_t board_get_led_gpio_off_level(void) +{ + return BOARD_LED_OFF_LEVEL; +} + +void board_ungate_mchtmr_at_lp_mode(void) +{ + /* Keep cpu clock on wfi, so that mchtmr irq can still work after wfi */ + sysctl_set_cpu0_lp_mode(HPM_SYSCTL, cpu_lp_mode_ungate_cpu_clock); +} + +void board_init(void) +{ + board_init_clock(); + board_init_console(); + board_init_pmp(); +#if BOARD_SHOW_CLOCK + board_print_clock_freq(); +#endif +#if BOARD_SHOW_BANNER + board_print_banner(); +#endif +} + +void board_delay_us(uint32_t us) +{ + clock_cpu_delay_us(us); +} + +void board_delay_ms(uint32_t ms) +{ + clock_cpu_delay_ms(ms); +} + +void board_timer_isr(void) +{ + if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) { + gptmr_clear_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH)); + timer_cb(); + } +} + +SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr); + +void board_timer_create(uint32_t ms, board_timer_cb cb) +{ + uint32_t gptmr_freq; + gptmr_channel_config_t config; + + timer_cb = cb; + gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config); + + clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0); + gptmr_freq = clock_get_frequency(BOARD_CALLBACK_TIMER_CLK_NAME); + + config.reload = gptmr_freq / 1000 * ms; + gptmr_channel_config(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH, &config, false); + gptmr_enable_irq(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_IRQ_MASK(BOARD_CALLBACK_TIMER_CH)); + intc_m_enable_irq_with_priority(BOARD_CALLBACK_TIMER_IRQ, 1); + + gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH); +} + +void board_i2c_bus_clear(I2C_Type *ptr) +{ + if (i2c_get_line_scl_status(ptr) == false) { + printf("CLK is low, please power cycle the board\n"); + while (1) { + } + } + if (i2c_get_line_sda_status(ptr) == false) { + printf("SDA is low, try to issue I2C bus clear\n"); + } else { + printf("I2C bus is ready\n"); + return; + } + i2s_gen_reset_signal(ptr, 9); + board_delay_ms(100); + printf("I2C bus is cleared\n"); +} + +void board_init_i2c(I2C_Type *ptr) +{ + hpm_stat_t stat; + uint32_t freq; + i2c_config_t config; + + init_i2c_pins(ptr); + board_i2c_bus_clear(ptr); + + if (ptr == HPM_I2C0) { + clock_add_to_group(clock_i2c0, 0); + clock_set_source_divider(clock_i2c0, clk_src_osc24m, 1U); + freq = clock_get_frequency(clock_i2c0); + } else if (ptr == HPM_I2C1) { + clock_add_to_group(clock_i2c1, 0); + clock_set_source_divider(clock_i2c1, clk_src_osc24m, 1U); + freq = clock_get_frequency(clock_i2c1); + } else if (ptr == HPM_I2C2) { + clock_add_to_group(clock_i2c2, 0); + clock_set_source_divider(clock_i2c2, clk_src_osc24m, 1U); + freq = clock_get_frequency(clock_i2c2); + } else if (ptr == HPM_I2C3) { + clock_add_to_group(clock_i2c3, 0); + clock_set_source_divider(clock_i2c3, clk_src_osc24m, 1U); + freq = clock_get_frequency(clock_i2c3); + } else { + printf("invild i2c base address 0x%x\n", (uint32_t) ptr); + while (1) { + } + } + + config.i2c_mode = i2c_mode_normal; + config.is_10bit_addressing = false; + stat = i2c_init_master(ptr, freq, &config); + if (stat != status_success) { + printf("failed to initialize i2c 0x%x\n", (uint32_t) ptr); + while (1) { + } + } +} + +uint32_t board_init_spi_clock(SPI_Type *ptr) +{ + if (ptr == HPM_SPI1) { + /* SPI1 clock configure */ + clock_add_to_group(clock_spi1, 0); + return clock_get_frequency(clock_spi1); + } else if (ptr == HPM_SPI2) { + /* SPI2 clock configure */ + clock_add_to_group(clock_spi2, 0); + return clock_get_frequency(clock_spi2); + } else if (ptr == HPM_SPI3) { + /* SPI3 clock configure */ + clock_add_to_group(clock_spi3, 0); + return clock_get_frequency(clock_spi3); + } + return 0; +} + +void board_init_gpio_pins(void) +{ + init_gpio_pins(); +} + +void board_init_spi_pins(SPI_Type *ptr) +{ + init_spi_pins(ptr); +} + +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + init_spi_pins_with_gpio_as_cs(ptr); + gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN), + GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL); +} + +void board_write_spi_cs(uint32_t pin, uint8_t state) +{ + gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state); +} + +void board_init_led_pins(void) +{ + init_led_pins_as_gpio(); + gpio_set_pin_output_with_initial(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, + board_get_led_gpio_off_level()); + gpio_set_pin_output_with_initial(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, + board_get_led_gpio_off_level()); + gpio_set_pin_output_with_initial(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, + board_get_led_gpio_off_level()); +} + +void board_led_toggle(void) +{ +#ifdef BOARD_LED_TOGGLE_RGB + static uint8_t i; + switch (i) { + case 1: + gpio_write_pin(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_OFF_LEVEL); + gpio_write_pin(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_ON_LEVEL); + gpio_write_pin(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_OFF_LEVEL); + break; + + case 2: + gpio_write_pin(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_OFF_LEVEL); + gpio_write_pin(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_OFF_LEVEL); + gpio_write_pin(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_ON_LEVEL); + break; + + case 0: + default: + gpio_write_pin(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_ON_LEVEL); + gpio_write_pin(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_OFF_LEVEL); + gpio_write_pin(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_OFF_LEVEL); + break; + } + i++; + i = i % 3; +#else + gpio_toggle_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN); +#endif +} + +void board_led_write(uint8_t state) +{ + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state); +} + +void board_init_pmp(void) +{ + extern uint32_t __noncacheable_start__[]; + extern uint32_t __noncacheable_end__[]; + + uint32_t start_addr = (uint32_t) __noncacheable_start__; + uint32_t end_addr = (uint32_t) __noncacheable_end__; + uint32_t length = end_addr - start_addr; + + if (length == 0) { + return; + } + + /* Ensure the address and the length are power of 2 aligned */ + assert((length & (length - 1U)) == 0U); + assert((start_addr & (length - 1U)) == 0U); + + pmp_entry_t pmp_entry[3] = { 0 }; + pmp_entry[0].pmp_addr = PMP_NAPOT_ADDR(0x0000000, 0x80000000); + pmp_entry[0].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK); + + + pmp_entry[1].pmp_addr = PMP_NAPOT_ADDR(0x80000000, 0x80000000); + pmp_entry[1].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK); + + pmp_entry[2].pmp_addr = PMP_NAPOT_ADDR(start_addr, length); + pmp_entry[2].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK); + pmp_entry[2].pma_addr = PMA_NAPOT_ADDR(start_addr, length); + pmp_entry[2].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN); + pmp_config(&pmp_entry[0], ARRAY_SIZE(pmp_entry)); +} + +void board_init_display_system_clock(void) +{ + clock_add_to_group(clock_gpu0, 0); + clock_add_to_group(clock_gwc0, 0); + clock_add_to_group(clock_gwc1, 0); + clock_add_to_group(clock_lvb, 0); + clock_add_to_group(clock_lcb, 0); + clock_add_to_group(clock_lcd0, 0); + clock_add_to_group(clock_dsi0, 0); + clock_add_to_group(clock_dsi1, 0); + clock_add_to_group(clock_cam0, 0); + clock_add_to_group(clock_cam1, 0); + clock_add_to_group(clock_jpeg, 0); + clock_add_to_group(clock_pdma, 0); +} + +void board_init_clock(void) +{ + uint32_t cpu0_freq = clock_get_frequency(clock_cpu0); + if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) { + /* Configure the External OSC ramp-up time: ~9ms */ + pllctlv2_xtal_set_rampup_time(HPM_PLLCTLV2, 32UL * 1000UL * 9U); + + /* Select clock setting preset1 */ + sysctl_clock_set_preset(HPM_SYSCTL, 2); + } + /* Add most Clocks to group 0 */ + /* not open uart clock in this API, uart should configure pin function before opening clock */ + clock_add_to_group(clock_cpu0, 0); + clock_add_to_group(clock_ahb, 0); + clock_add_to_group(clock_axic, 0); + clock_add_to_group(clock_axis, 0); + clock_add_to_group(clock_axiv, 0); + clock_add_to_group(clock_axid, 0); + clock_add_to_group(clock_axig, 0); + + clock_add_to_group(clock_mchtmr0, 0); + clock_add_to_group(clock_xpi0, 0); + clock_add_to_group(clock_gptmr0, 0); + clock_add_to_group(clock_gptmr1, 0); + clock_add_to_group(clock_gptmr2, 0); + clock_add_to_group(clock_gptmr3, 0); + clock_add_to_group(clock_i2c0, 0); + clock_add_to_group(clock_i2c1, 0); + clock_add_to_group(clock_i2c2, 0); + clock_add_to_group(clock_i2c3, 0); + clock_add_to_group(clock_spi0, 0); + clock_add_to_group(clock_spi1, 0); + clock_add_to_group(clock_spi2, 0); + clock_add_to_group(clock_spi3, 0); + clock_add_to_group(clock_can0, 0); + clock_add_to_group(clock_can1, 0); + clock_add_to_group(clock_can2, 0); + clock_add_to_group(clock_can3, 0); + clock_add_to_group(clock_can4, 0); + clock_add_to_group(clock_can5, 0); + clock_add_to_group(clock_can6, 0); + clock_add_to_group(clock_can7, 0); + clock_add_to_group(clock_ptpc, 0); + clock_add_to_group(clock_ref0, 0); + clock_add_to_group(clock_ref1, 0); + clock_add_to_group(clock_watchdog0, 0); + clock_add_to_group(clock_sdp, 0); + clock_add_to_group(clock_xdma, 0); + clock_add_to_group(clock_xram, 0); + clock_add_to_group(clock_usb0, 0); + clock_add_to_group(clock_kman, 0); + clock_add_to_group(clock_gpio, 0); + clock_add_to_group(clock_mbx0, 0); + clock_add_to_group(clock_hdma, 0); + clock_add_to_group(clock_rng, 0); + clock_add_to_group(clock_adc0, 0); + clock_add_to_group(clock_adc1, 0); + clock_add_to_group(clock_crc0, 0); + clock_add_to_group(clock_dao, 0); + clock_add_to_group(clock_pdm, 0); + clock_add_to_group(clock_smix, 0); + + clock_add_to_group(clock_i2s0, 0); + clock_add_to_group(clock_i2s1, 0); + clock_add_to_group(clock_i2s2, 0); + clock_add_to_group(clock_i2s3, 0); + + clock_add_to_group(clock_eth0, 0); + clock_add_to_group(clock_ffa, 0); + + clock_add_to_group(clock_tsns, 0); + + board_init_display_system_clock(); + + /* Connect Group0 to CPU0 */ + clock_connect_group_to_cpu(0, 0); + + /* Bump up DCDC voltage to 1150mv */ + pcfg_dcdc_set_voltage(HPM_PCFG, 1150); + + /* Configure PLL1_CLK0 Post Divider to 1 */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 0, 0); + pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 0, BOARD_CPU_FREQ); + + /* Configure axis to 200MHz */ + clock_set_source_divider(clock_axis, clk_src_pll1_clk0, 4); + + /* Configure axig/clock_gpu0 to 400MHz */ + clock_set_source_divider(clock_axig, clk_src_pll1_clk0, 2); + + /* Configure mchtmr to 24MHz */ + clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1); + + clock_update_core_clock(); +} + +void board_init_can(MCAN_Type *ptr) +{ + init_can_pins(ptr); +} + +uint32_t board_init_can_clock(MCAN_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_MCAN0) { + /* Set the CAN0 peripheral clock to 80MHz */ + clock_set_source_divider(clock_can0, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can0); + } else if (ptr == HPM_MCAN1) { + /* Set the CAN1 peripheral clock to 80MHz */ + clock_set_source_divider(clock_can1, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can1); + } else if (ptr == HPM_MCAN2) { + /* Set the CAN2 peripheral clock to 8MHz */ + clock_set_source_divider(clock_can2, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can2); + } else if (ptr == HPM_MCAN3) { + /* Set the CAN3 peripheral clock to 80MHz */ + clock_set_source_divider(clock_can3, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can3); + } else if (ptr == HPM_MCAN4) { + /* Set the CAN4 peripheral clock to 80MHz */ + clock_set_source_divider(clock_can4, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can4); + } else if (ptr == HPM_MCAN5) { + /* Set the CAN5 peripheral clock to 80MHz */ + clock_set_source_divider(clock_can5, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can5); + } else if (ptr == HPM_MCAN6) { + /* Set the CAN6 peripheral clock to 80MHz */ + clock_set_source_divider(clock_can6, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can6); + } else if (ptr == HPM_MCAN7) { + /* Set the CAN7 peripheral clock to 80MHz */ + clock_set_source_divider(clock_can7, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can7); + } else { + /* Invalid CAN instance */ + } + return freq; +} + +uint32_t board_init_uart_clock(UART_Type *ptr) +{ + uint32_t freq = 0U; + if (ptr == HPM_UART0) { + clock_set_source_divider(clock_uart0, clk_src_osc24m, 1); + clock_add_to_group(clock_uart0, 0); + freq = clock_get_frequency(clock_uart0); + } else if (ptr == HPM_UART1) { + clock_set_source_divider(clock_uart1, clk_src_osc24m, 1); + clock_add_to_group(clock_uart1, 0); + freq = clock_get_frequency(clock_uart1); + } else if (ptr == HPM_UART2) { + clock_set_source_divider(clock_uart2, clk_src_osc24m, 1); + clock_add_to_group(clock_uart2, 0); + freq = clock_get_frequency(clock_uart2); + } else if (ptr == HPM_UART3) { + clock_set_source_divider(clock_uart3, clk_src_osc24m, 1); + clock_add_to_group(clock_uart3, 0); + freq = clock_get_frequency(clock_uart3); + } else { + /* Not supported */ + } + return freq; +} + +uint32_t board_lcdc_clock_init(clock_name_t clock_name, uint32_t pixel_clk_khz); + +#if defined(CONFIG_PANEL_RGB_TM070RDH13) && CONFIG_PANEL_RGB_TM070RDH13 +static void set_reset_pin_level_tm070rdh13(uint8_t level) +{ + gpio_write_pin(HPM_GPIO0, GPIO_DO_GPIOA, 14, level); +} + +static void set_backlight_tm070rdh13(uint16_t percent) +{ + gpio_write_pin(HPM_GPIO0, GPIO_DO_GPIOA, 9, percent > 0 ? 1 : 0); +} + +static void set_video_router_tm070rdh13(void) +{ + pixelmux_rgb_data_source_enable(pixelmux_rgb_sel_lcdc0); +} + +void board_init_lcd_rgb_tm070rdh13(void) +{ + init_lcd_rgb_ctl_pins(); + init_lcd_rgb_pins(); + + gpio_set_pin_output(HPM_GPIO0, GPIO_DO_GPIOY, 5); + gpio_write_pin(HPM_GPIO0, GPIO_DO_GPIOY, 5, 1); + + gpio_set_pin_output(HPM_GPIO0, GPIO_DO_GPIOA, 9); + gpio_set_pin_output(HPM_GPIO0, GPIO_DO_GPIOA, 14); + + hpm_panel_hw_interface_t hw_if = {0}; + hpm_panel_t *panel = hpm_panel_find_device_default(); + const hpm_panel_timing_t *timing = hpm_panel_get_timing(panel); + uint32_t lcdc_pixel_clk_khz = board_lcdc_clock_init(clock_lcd0, timing->pixel_clock_khz); + hw_if.set_reset_pin_level = set_reset_pin_level_tm070rdh13; + hw_if.set_backlight = set_backlight_tm070rdh13; + hw_if.set_video_router = set_video_router_tm070rdh13; + hw_if.lcdc_pixel_clk_khz = lcdc_pixel_clk_khz; + hpm_panel_register_interface(panel, &hw_if); + + printf("name: %s, lcdc_clk: %ukhz\n", + hpm_panel_get_name(panel), + lcdc_pixel_clk_khz); + + hpm_panel_reset(panel); + hpm_panel_init(panel); + hpm_panel_power_on(panel); +} + +#endif + +#if defined(CONFIG_PANEL_LVDS_CC10128007) && CONFIG_PANEL_LVDS_CC10128007 +static void set_backlight_cc10128007(uint16_t percent) +{ + gpio_write_pin(HPM_GPIO0, GPIO_DO_GPIOA, 31, percent > 0 ? 1 : 0); + gpio_write_pin(HPM_GPIO0, GPIO_DO_GPIOA, 30, percent > 0 ? 1 : 0); +} + +static void set_video_router_cc10128007(void) +{ + pixelmux_config_tx_phy1_mode(pixelmux_tx_phy_mode_lvds); + pixelmux_lvb_di0_data_source_enable(pixelmux_lvb_di0_sel_lcdc0); +} + +void board_init_lcd_lvds_cc10128007(void) +{ + init_lcd_lvds_single_ctl_pins(); + gpio_set_pin_output(HPM_GPIO0, GPIO_DO_GPIOA, 30); + gpio_set_pin_output(HPM_GPIO0, GPIO_DO_GPIOA, 31); + + init_mipi_lvds_tx_phy1_pin(); + + hpm_panel_hw_interface_t hw_if = {0}; + hpm_panel_t *panel = hpm_panel_find_device_default(); + const hpm_panel_timing_t *timing = hpm_panel_get_timing(panel); + + uint32_t lcdc_pixel_clk_khz = board_lcdc_clock_init(clock_lcd0, timing->pixel_clock_khz); + hw_if.set_video_router = set_video_router_cc10128007; + hw_if.set_backlight = set_backlight_cc10128007; + hw_if.lcdc_pixel_clk_khz = lcdc_pixel_clk_khz; + hw_if.video.lvds.channel_di_index = 0; + hw_if.video.lvds.channel_index = 1; /* ch1 -> phy1*/ + hw_if.video.lvds.lvb_base = HPM_LVB; + + hpm_panel_register_interface(panel, &hw_if); + + printf("name: %s, lcdc_clk: %ukhz\n", + hpm_panel_get_name(panel), + lcdc_pixel_clk_khz); + + hpm_panel_reset(panel); + hpm_panel_init(panel); + hpm_panel_power_on(panel); +} +#endif + +#if defined(CONFIG_PANEL_MIPI_MC10128007_31B) && CONFIG_PANEL_MIPI_MC10128007_31B +static void set_reset_pin_level_mc10128007_31b(uint8_t level) +{ + gpio_write_pin(HPM_GPIO0, GPIO_DO_GPIOB, 1, level); +} + +static void set_video_router_mc10128007_31b(void) +{ + pixelmux_mipi_dsi0_data_source_enable(pixelmux_mipi_dsi0_sel_lcdc0); + pixelmux_config_tx_phy0_mode(pixelmux_tx_phy_mode_mipi); +} + +void board_init_lcd_mipi_mc10128007_31b(void) +{ + /* RESET */ + init_lcd_mipi_ctl_pins(); + gpio_set_pin_output(HPM_GPIO0, GPIO_DO_GPIOB, 1); + + init_mipi_lvds_tx_phy0_pin(); + + hpm_panel_hw_interface_t hw_if = {0}; + hpm_panel_t *panel = hpm_panel_find_device_default(); + const hpm_panel_timing_t *timing = hpm_panel_get_timing(panel); + uint32_t lcdc_pixel_clk_khz = board_lcdc_clock_init(clock_lcd0, timing->pixel_clock_khz); + hw_if.set_reset_pin_level = set_reset_pin_level_mc10128007_31b; + hw_if.set_video_router = set_video_router_mc10128007_31b; + hw_if.lcdc_pixel_clk_khz = lcdc_pixel_clk_khz; + hw_if.video.mipi.format = HPM_PANEL_MIPI_FORMAT_RGB888; + hw_if.video.mipi.mipi_host_base = HPM_MIPI_DSI0; + hw_if.video.mipi.mipi_phy_base = HPM_MIPI_DSI_PHY0; + hpm_panel_register_interface(panel, &hw_if); + + printf("name: %s, lcdc_clk: %ukhz\n", + hpm_panel_get_name(panel), + lcdc_pixel_clk_khz); + + hpm_panel_reset(panel); + hpm_panel_init(panel); + hpm_panel_power_on(panel); +} +#endif + +#if defined(CONFIG_PANEL_LVDS_TM103XDGP01) && CONFIG_PANEL_LVDS_TM103XDGP01 +static void set_reset_pin_level_tm103xdgp01(uint8_t level) +{ + gpio_write_pin(HPM_GPIO0, GPIO_DO_GPIOA, 31, level); +} + +static void set_video_router_tm103xdgp01(void) +{ + pixelmux_config_tx_phy0_mode(pixelmux_tx_phy_mode_lvds); + pixelmux_config_tx_phy1_mode(pixelmux_tx_phy_mode_lvds); + + pixelmux_lvb_di1_data_source_enable(pixelmux_lvb_di1_sel_lcdc0); + pixelmux_lvb_di0_data_source_enable(pixelmux_lvb_di0_sel_lcdc0); +} + +void board_init_lcd_lvds_tm103xdgp01(void) +{ + init_lcd_lvds_double_ctl_pins(); + gpio_set_pin_output(HPM_GPIO0, GPIO_DO_GPIOA, 31); + + init_mipi_lvds_tx_phy0_pin(); + init_mipi_lvds_tx_phy1_pin(); + + hpm_panel_hw_interface_t hw_if = {0}; + hpm_panel_t *panel = hpm_panel_find_device_default(); + const hpm_panel_timing_t *timing = hpm_panel_get_timing(panel); + + /* In split mode: lcdc_pixel_clk = 2 * panel_pixel_clk */ + uint32_t lcdc_pixel_clk_khz = board_lcdc_clock_init(clock_lcd0, timing->pixel_clock_khz * 2); + hw_if.set_reset_pin_level = set_reset_pin_level_tm103xdgp01; + hw_if.set_video_router = set_video_router_tm103xdgp01; + hw_if.lcdc_pixel_clk_khz = lcdc_pixel_clk_khz; + hw_if.video.lvds.channel_di_index = 0; + hw_if.video.lvds.lvb_base = HPM_LVB; + + hpm_panel_register_interface(panel, &hw_if); + + printf("name: %s, lcdc_clk: %ukhz\n", + hpm_panel_get_name(panel), + lcdc_pixel_clk_khz); + + hpm_panel_reset(panel); + hpm_panel_init(panel); + hpm_panel_power_on(panel); +} +#endif + +#ifdef CONFIG_HPM_PANEL + +void board_lcd_backlight(bool is_on) +{ + hpm_panel_t *panel = hpm_panel_find_device_default(); + hpm_panel_set_backlight(panel, is_on == true ? 100 : 0); +} + +uint32_t board_lcdc_clock_init(clock_name_t clock_name, uint32_t pixel_clk_khz) +{ + clock_add_to_group(clock_name, 0); + + uint32_t freq_khz = clock_get_frequency(clk_pll4clk0) / 1000; + uint32_t div = (freq_khz + pixel_clk_khz / 2) / pixel_clk_khz; + clock_set_source_divider(clock_name, clk_src_pll4_clk0, div); + return clock_get_frequency(clock_name) / 1000; +} + +void board_init_lcd(void) +{ +#if defined(CONFIG_PANEL_RGB_TM070RDH13) && CONFIG_PANEL_RGB_TM070RDH13 + board_init_lcd_rgb_tm070rdh13(); +#endif + +#if defined(CONFIG_PANEL_LVDS_CC10128007) && CONFIG_PANEL_LVDS_CC10128007 + board_init_lcd_lvds_cc10128007(); +#endif + +#if defined(CONFIG_PANEL_MIPI_MC10128007_31B) && CONFIG_PANEL_MIPI_MC10128007_31B + board_init_lcd_mipi_mc10128007_31b(); +#endif + +#if defined(CONFIG_PANEL_LVDS_TM103XDGP01) && CONFIG_PANEL_LVDS_TM103XDGP01 + board_init_lcd_lvds_tm103xdgp01(); +#endif +} + +void board_panel_para_to_lcdc(lcdc_config_t *config) +{ + const hpm_panel_timing_t *timing; + hpm_panel_t *panel = hpm_panel_find_device_default(); + + timing = hpm_panel_get_timing(panel); + config->resolution_x = timing->hactive; + config->resolution_y = timing->vactive; + + config->hsync.pulse_width = timing->hsync_len; + config->hsync.back_porch_pulse = timing->hback_porch; + config->hsync.front_porch_pulse = timing->hfront_porch; + + config->vsync.pulse_width = timing->vsync_len; + config->vsync.back_porch_pulse = timing->vback_porch; + config->vsync.front_porch_pulse = timing->vfront_porch; + + config->control.invert_hsync = timing->hsync_pol; + config->control.invert_vsync = timing->vsync_pol; + config->control.invert_href = timing->de_pol; + config->control.invert_pixel_data = timing->pixel_data_pol; + config->control.invert_pixel_clock = timing->pixel_clk_pol; +} +#endif + +void board_init_gwc(void) +{ + clock_add_to_group(clock_gwc0, 0); + clock_add_to_group(clock_gwc1, 0); + clock_add_to_group(clock_lcd0, 0); +} + +void board_init_cap_touch(void) +{ + init_cap_pins(); + gpio_set_pin_output_with_initial(BOARD_CAP_RST_GPIO, BOARD_CAP_RST_GPIO_INDEX, BOARD_CAP_RST_GPIO_PIN, 0); + gpio_set_pin_output_with_initial(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 0); + + board_delay_ms(1); + gpio_write_pin(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 0); + board_delay_ms(1); + gpio_write_pin(BOARD_CAP_RST_GPIO, BOARD_CAP_RST_GPIO_INDEX, BOARD_CAP_RST_GPIO_PIN, 1); + board_delay_ms(6); + gpio_write_pin(BOARD_CAP_RST_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 0); + + board_init_i2c(BOARD_CAP_I2C_BASE); +} + +void board_init_cam_pins(void) +{ + init_cam_pins(); + /* enable cam RST pin out with high level */ + gpio_set_pin_output_with_initial(BOARD_CAM_RST_GPIO_CTRL, BOARD_CAM_RST_GPIO_INDEX, BOARD_CAM_RST_GPIO_PIN, 1); + /* PWDN pin set to low when power up */ + gpio_set_pin_output_with_initial(BOARD_CAM_PWDN_GPIO_CTRL, BOARD_CAM_PWDN_GPIO_INDEX, BOARD_CAM_PWDN_GPIO_PIN, 0); + pixelmux_cam0_data_source_enable(pixelmux_cam0_sel_dvp); +} + +void board_write_cam_rst(uint8_t state) +{ + gpio_write_pin(BOARD_CAM_RST_GPIO_CTRL, BOARD_CAM_RST_GPIO_INDEX, BOARD_CAM_RST_GPIO_PIN, state); +} + +void board_write_cam_pwdn(uint8_t state) +{ + gpio_write_pin(BOARD_CAM_PWDN_GPIO_CTRL, BOARD_CAM_PWDN_GPIO_INDEX, BOARD_CAM_PWDN_GPIO_PIN, state); +} + +uint32_t board_init_cam_clock(CAM_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_CAM0) { + /* Configure camera clock to 24MHz */ + clock_set_source_divider(clock_cam0, clk_src_osc24m, 1U); + freq = clock_get_frequency(clock_cam0); + } else if (ptr == HPM_CAM1) { + /* Configure camera clock to 24MHz */ + clock_set_source_divider(clock_cam1, clk_src_osc24m, 1U); + freq = clock_get_frequency(clock_cam1); + } else { + /* Invalid camera instance */ + } + return freq; +} + +void board_init_mipi_csi_cam_pins(void) +{ + init_cam_mipi_csi_pins(); + init_mipi_lvds_rx_phy1_pin(); + + /* enable cam RST pin out with high level */ + gpio_set_pin_output_with_initial(HPM_GPIO0, GPIO_DI_GPIOB, 0, 1); +} + +void board_write_mipi_csi_cam_rst(uint8_t state) +{ + gpio_write_pin(HPM_GPIO0, GPIO_DI_GPIOB, 0, state); +} + + +static void _cpu_wait_ms(uint32_t cpu_freq, uint32_t ms) +{ + uint32_t ticks_per_us = (cpu_freq + 1000000UL - 1UL) / 1000000UL; + uint64_t expected_ticks = hpm_csr_get_core_mcycle() + (uint64_t)ticks_per_us * 1000UL * ms; + while (hpm_csr_get_core_mcycle() < expected_ticks) { + } +} + +void init_ddr2_800(void) +{ + /* Enable On-chip DCDC 1.8V output */ + HPM_PCFG->DCDCM_MODE = PCFG_DCDCM_MODE_VOLT_SET(1800) | PCFG_DCDCM_MODE_MODE_SET(1); + + /* Change DDR clock to 200MHz, namely: DDR2-800 */ + clock_set_source_divider(clock_axif, clk_src_pll1_clk0, 4); + + /* Enable DDR clock first */ + clock_add_to_group(clock_ddr0, 0); + + /* Wait until the clock is stable */ + uint32_t core_clock_freq = clock_get_frequency(clock_cpu0); + _cpu_wait_ms(core_clock_freq, 5); + + /* Clear DFI_INIT_COMPLETE_EN bit */ + HPM_DDRCTL->DFIMISC &= ~DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_MASK; + + /* Release DDR core reset */ + *(volatile uint32_t *) (HPM_DDRCTL_BASE + 0x3000UL) |= (1UL << 26); + + /* Enable PORT */ + HPM_DDRCTL->PCFG[0].CTRL = 1; + + /* Configure W972GG6KB parameters, configure DDRCTL first */ + HPM_DDRCTL->MSTR = DDRCTL_MSTR_ACTIVE_RANKS_SET(1) /* RANK=1 */ + | DDRCTL_MSTR_BURST_RDWR_SET(4) /* Burst Length = 8 */ + | DDRCTL_MSTR_DATA_BUS_WIDTH_SET(0) /* Full DQ bus width */ + | DDRCTL_MSTR_DDR3_SET(0); /* DDR2 Device */ + + /* Skip SDRAM Initialization in controller, the initialization sequence will be performed by PHY */ + HPM_DDRCTL->INIT0 = DDRCTL_INIT0_SKIP_DRAM_INIT_SET(1) + | DDRCTL_INIT0_POST_CKE_X1024_SET(2) /* Default setting */ + | DDRCTL_INIT0_PRE_CKE_X1024_SET(0x4e); /* Default setting */ + + /* Configure DFI timing */ + HPM_DDRCTL->DFITMG0 = 0x03010101UL; + HPM_DDRCTL->DFITMG1 = 0x00020101UL; + HPM_DDRCTL->DFIUPD0 = 0x40005UL; + HPM_DDRCTL->DFIUPD1 = 0x00020008UL; + + HPM_DDRCTL->ODTCFG = 0x06000600UL; /* BL=8 */ + + /* Configure ADDRMAP */ + HPM_DDRCTL->ADDRMAP0 = 0x001F1F1FUL; /* RANK0 not used */ + HPM_DDRCTL->ADDRMAP1 = 0x00121212UL; /* HIF bit[24:22] as BANK[2:0] */ + HPM_DDRCTL->ADDRMAP2 = 0; /* HIF bit[6:3] as COL_B[6:3] */ + HPM_DDRCTL->ADDRMAP3 = 0; /* HIF bit [10:7] as COL_B[11,9:6:7] */ + HPM_DDRCTL->ADDRMAP4 = 0xF0FUL; /* not used */ + HPM_DDRCTL->ADDRMAP5 = 0x06030303UL; /* HIF bit[21:11] as ROW[10:0], HIF bit[25] as ROW[11] */ + HPM_DDRCTL->ADDRMAP6 = 0x0F0F0606UL; /* HIF bit[27:26] as ROW[13:12] */ + + /* Release DDR AXI reset */ + *(volatile uint32_t *) (HPM_DDRCTL_BASE + 0x3000UL) |= (1UL << 27); + + /* Release DDR PHY */ + *(volatile uint32_t *) (HPM_DDRPHY_BASE + 0x3000UL) |= (1UL << 4); + + HPM_DDRPHY->DCR = DDRPHY_DCR_DDRMD_SET(2) /* Set to DDR2 mode */ + | DDRPHY_DCR_DDR8BNK_MASK /* BANK = 8 */ + | DDRPHY_DCR_BYTEMASK_MASK; /* BYTEMASK = 1 */ + HPM_DDRPHY->DSGCR |= DDRPHY_DSGCR_RRMODE_MASK; /* Enable RRMode */ + + /* Configure DDR2 registers */ + HPM_DDRPHY->MR = (3UL << 0) /* BL = 3 */ + | (0UL << 3) /* BT = 0 */ + | (6UL << 4) /* CL = 6 */ + | (0UL << 7) /* Operating mode */ + | (0UL << 8) /* DLL Reset = 0 */ + | (6UL << 9); /* WR = 6 */ + HPM_DDRPHY->EMR = (1UL << 0) /* DLL Enable */ + | (0UL << 1) /* Output Driver Impedance Control */ + | (0UL << 6) | (1UL << 2) /* On Die Termination */ + | (0UL << 3) /* AL(Posted CAS Additive Latency) = 0 */ + | (0UL << 7) /* OCD = 0*/ + | (0UL << 10) /* DQS */ + | (0UL << 11) /* RDQS */ + | (0UL << 12); /* QOFF */ + HPM_DDRPHY->EMR2 = 0; + HPM_DDRPHY->EMR3 = 0; + HPM_DDRPHY->DTPR0 = (4UL << 0) + | (5UL << 4) + | (14UL << 8) + | (15UL << 12) + | (50UL << 16) + | (10UL << 22) + | (60UL << 26); + HPM_DDRPHY->DTPR1 = (2UL << 0) + | (31UL << 5) + | (80UL << 11) + | (40UL << 20) + | (0x8 << 26); + HPM_DDRPHY->DTPR2 = (256UL << 0) + | (6UL << 10) + | (4UL << 15) + | (512UL << 19); + + /* tREFPRD */ + HPM_DDRPHY->PGCR2 = 0xF06D50; + + /* Set DFI_INIT_COMPLETE_EN bit */ + HPM_DDRCTL->DFIMISC |= DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_MASK; + + /* Start PHY Init First */ + HPM_DDRPHY->PIR |= DDRPHY_PIR_INIT_MASK; + while ((HPM_DDRPHY->PGSR0 & DDRPHY_PGSR0_IDONE_MASK) == 0) { + } + /** Data training + * RANKEN = 1, Others: default value + */ + HPM_DDRPHY->DTCR = 0x91003587UL; + + /* Trigger PHY to do the PHY initialization and DRAM initialization */ + HPM_DDRPHY->PIR = 0xF501UL; + + /* Wait until the initialization sequence started */ + while ((HPM_DDRPHY->PGSR0 & DDRPHY_PGSR0_IDONE_MASK) != 0) { + } + /* Wait until the initialization sequence completed */ + while ((HPM_DDRPHY->PGSR0 & DDRPHY_PGSR0_IDONE_MASK) == 0) { + } + + /* Wait for normal mode */ + while ((HPM_DDRCTL->STAT & DDRCTL_STAT_OPERATING_MODE_MASK) != 0x1) { + } +} + +void init_ddr3l_1333(void) +{ + /* Enable On-chip DCDC 1.4V output */ + HPM_PCFG->DCDCM_MODE = PCFG_DCDCM_MODE_VOLT_SET(1400) | PCFG_DCDCM_MODE_MODE_SET(5); + + /* Change DDR clock to 333.33MHz, namely: DDR3-1333 */ + clock_set_source_divider(clock_axif, clk_src_pll1_clk1, 2); + + /* Enable DDR clock first */ + clock_add_to_group(clock_ddr0, 0); + + /* Wait until the clock is stable */ + uint32_t core_clock_freq = clock_get_frequency(clock_cpu0); + _cpu_wait_ms(core_clock_freq, 5); + + /* Release DDR PHY */ + *(volatile uint32_t *) (HPM_DDRPHY_BASE + 0x3000UL) |= (1UL << 4); + + /* Clear DFI_INIT_COMPLETE_EN bit */ + HPM_DDRCTL->DFIMISC &= ~DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_MASK; + + HPM_DDRPHY->DSGCR = 0xf004641f; + + *(volatile uint32_t *) (HPM_DDRPHY_BASE + 0x3000UL) |= (1UL << 0); + + /* Release DDR core reset */ + *(volatile uint32_t *) (HPM_DDRCTL_BASE + 0x3000UL) |= (1UL << 26); + + /* Configure DDRCTL first */ + HPM_DDRCTL->MSTR = DDRCTL_MSTR_ACTIVE_RANKS_SET(1) /* RANK=1 */ + | DDRCTL_MSTR_BURST_RDWR_SET(4) /* Burst Length = 8 */ + | DDRCTL_MSTR_DATA_BUS_WIDTH_SET(0) /* Full DQ bus width */ + | DDRCTL_MSTR_DDR3_SET(1); /* DDR3 Device */ + + /* Enable PORT */ + HPM_DDRCTL->PCFG[0].CTRL = 1; + + /* Skip SDRAM Initialization in controller, the initialization sequence will be performed by PHY */ + HPM_DDRCTL->INIT0 = DDRCTL_INIT0_SKIP_DRAM_INIT_SET(1) + | DDRCTL_INIT0_POST_CKE_X1024_SET(2) /* Default setting */ + | DDRCTL_INIT0_PRE_CKE_X1024_SET(0x4e); /* Default setting */ + HPM_DDRCTL->DRAMTMG4 = 0x05010407; + + /* Configure DFI timing */ + HPM_DDRCTL->DFITMG0 = 0x07040102; + HPM_DDRCTL->DFITMG1 = 0x20404; + HPM_DDRCTL->DFIUPD1 = 0x20008; + HPM_DDRCTL->ODTCFG = 0x06000600UL; /* BL=8 */ + HPM_DDRCTL->ODTMAP = 0x11; + + /* Configure ADDRMAP */ + HPM_DDRCTL->ADDRMAP0 = 0x001F1F1FUL; /* RANK0 not used */ + HPM_DDRCTL->ADDRMAP1 = 0x00121212UL; /* HIF bit[24:22] as BANK[2:0] */ + HPM_DDRCTL->ADDRMAP2 = 0; /* HIF bit[6:3] as COL_B[6:3] */ + HPM_DDRCTL->ADDRMAP3 = 0; /* HIF bit [10:7] as COL_B[11,9:6:7] */ + HPM_DDRCTL->ADDRMAP4 = 0xF0FUL; /* not used */ + HPM_DDRCTL->ADDRMAP5 = 0x06030303UL; /* HIF bit[21:11] as ROW[10:0], HIF bit[25] as ROW[11] */ + HPM_DDRCTL->ADDRMAP6 = 0x0F060606UL; /* HIF bit[27:26] as ROW[13:12] */ + + /* Release DDR AXI reset */ + *(volatile uint32_t *) (HPM_DDRCTL_BASE + 0x3000UL) |= (1UL << 27); + + /* Configure DDR3 registers */ + HPM_DDRPHY->MR0 = 0xC70; + HPM_DDRPHY->MR1 = 0x6; + HPM_DDRPHY->MR2 = 0x18; + HPM_DDRPHY->MR3 = 0; + + HPM_DDRPHY->ODTCR = 0x84210000; + + HPM_DDRPHY->DTPR0 = 0x919c8866; + HPM_DDRPHY->DTPR1 = 0x1a838360; + HPM_DDRPHY->DTPR2 = 0x3002d200; + + /* tREFPRD */ + HPM_DDRPHY->PGCR2 = 0xf06d28; + + /* Set DFI_INIT_COMPLETE_EN bit */ + HPM_DDRCTL->DFIMISC |= DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_MASK; + + /* Start PHY Init First */ + HPM_DDRPHY->PIR |= DDRPHY_PIR_INIT_MASK; + while ((HPM_DDRPHY->PGSR0 & DDRPHY_PGSR0_IDONE_MASK) == 0) { + } + /** Data training + * RANKEN = 1, Others: default value + */ + HPM_DDRPHY->DTCR = 0x930035D7; + + /* Trigger PHY to do the PHY initialization and DRAM initialization */ + HPM_DDRPHY->PIR = 0xFF81UL; + + /* Wait until the initialization sequence started */ + while ((HPM_DDRPHY->PGSR0 & DDRPHY_PGSR0_IDONE_MASK) != 0) { + } + /* Wait until the initialization sequence completed */ + while ((HPM_DDRPHY->PGSR0 & DDRPHY_PGSR0_IDONE_MASK) == 0) { + } + + /* Wait for normal mode */ + while ((HPM_DDRCTL->STAT & DDRCTL_STAT_OPERATING_MODE_MASK) != 0x1) { + } +} + +void _init_ext_ram(void) +{ +#if (BOARD_DDR_TYPE == DDR_TYPE_DDR2) + init_ddr2_800(); +#endif +#if (BOARD_DDR_TYPE == DDR_TYPE_DDR3L) + init_ddr3l_1333(); +#endif +} + +void board_init_usb_pins(void) +{ + init_usb_pins(); + usb_hcd_set_power_ctrl_polarity(BOARD_USB, true); + /* Wait USB_PWR pin control vbus power stable. Time depend on decoupling capacitor, you can decrease or increase this time */ + board_delay_ms(100); +} + +void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level) +{ + (void) usb_index; + (void) level; +} + +void board_sd_power_switch(SDXC_Type *ptr, bool power_on) +{ + if (ptr == HPM_SDXC1) { + init_sdxc_pwr_pin(ptr, true); + uint32_t gpio_index = BOARD_APP_SDCARD_POWER_SWITCH_PIN / 32; + uint32_t pin_index = BOARD_APP_SDCARD_POWER_SWITCH_PIN % 32; + + if (power_on) { + HPM_GPIO0->DO[gpio_index].SET = 1UL << pin_index; + } else { + HPM_GPIO0->DO[gpio_index].CLEAR = 1UL << pin_index; + } + } +} + +void board_init_sd_pins(SDXC_Type *ptr) +{ + if (ptr == HPM_SDXC0) { + init_sdxc_cmd_pin(ptr, false, true); + init_sdxc_clk_data_pins(ptr, 8, true); + } else { + init_sdxc_cmd_pin(ptr, false, false); + init_sdxc_clk_data_pins(ptr, 4, false); + } +} + +uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inverse) +{ + uint32_t actual_freq = 0; + do { + if ((ptr != HPM_SDXC0) && (ptr != HPM_SDXC1)) { + break; + } + clock_name_t sdxc_clk = (ptr == HPM_SDXC0) ? clock_sdxc0 : clock_sdxc1; + clock_add_to_group(sdxc_clk, 0); + sdxc_enable_inverse_clock(ptr, false); + sdxc_enable_sd_clock(ptr, false); + + + clock_set_source_divider(sdxc_clk, clk_src_pll1_clk0, 4U); + /* Configure the clock below 400KHz for the identification state */ + if (freq <= 400000UL) { + /* Set clock to 375KHz */ + sdxc_set_clock_divider(ptr, 534U); + } + /* configure the clock to 24MHz for the SDR12/Default speed */ + else if (freq <= 26000000UL) { + /* Set clock to 25MHz */ + sdxc_set_clock_divider(ptr, 8U); + } + /* Configure the clock to 50MHz for the SDR25/High speed/50MHz DDR/50MHz SDR */ + else if (freq <= 52000000UL) { + /* Set clock to 50MHz */ + sdxc_set_clock_divider(ptr, 4U); + } + /* Configure the clock to 100MHz for the SDR50 */ + else if (freq <= 100000000UL) { + /* Set clock to 100MHz */ + sdxc_set_clock_divider(ptr, 2U); + } + /* Configure the clock to 133MHz for SDR104/HS200/HS400 */ + else if (freq <= 208000000UL) { + /* 166MHz */ + clock_set_source_divider(sdxc_clk, clk_src_pll1_clk1, 5U); + sdxc_set_clock_divider(ptr, 1U); + } + /* For other unsupported clock ranges, configure the clock to 24MHz */ + else { + /* Set clock to 25MHz */ + sdxc_set_clock_divider(ptr, 5U); + } + if (need_inverse) { + sdxc_enable_inverse_clock(ptr, true); + } + sdxc_enable_sd_clock(ptr, true); + actual_freq = clock_get_frequency(sdxc_clk) / sdxc_get_clock_divider(ptr); + } while (false); + + return actual_freq; +} + +uint32_t board_init_dao_clock(void) +{ + return clock_get_frequency(clock_dao); +} + +uint32_t board_init_pdm_clock(void) +{ + return clock_get_frequency(clock_pdm); +} + +uint32_t board_init_i2s_clock(I2S_Type *ptr) +{ + if (ptr == HPM_I2S0) { + return clock_get_frequency(clock_i2s0); + } else if (ptr == HPM_I2S1) { + return clock_get_frequency(clock_i2s1); + } else if (ptr == HPM_I2S2) { + return clock_get_frequency(clock_i2s2); + } else if (ptr == HPM_I2S3) { + return clock_get_frequency(clock_i2s3); + } else { + return 0; + } +} + +/* adjust I2S source clock base on sample rate */ +uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate) +{ + if (ptr == HPM_I2S0) { + if ((sample_rate % 22050) == 0) { + clock_set_source_divider(clock_aud0, clk_src_pll1_clk0, 71); /* config clock_aud1 for 22050*n sample rate */ + clock_add_to_group(clock_i2s0, 0); + clock_set_i2s_source(clock_i2s0, clk_i2s_src_aud0); + } else { + clock_set_source_divider(clock_aud0, clk_src_pll3_clk0, 21); /* default 24576000Hz */ + clock_add_to_group(clock_i2s0, 0); + clock_set_i2s_source(clock_i2s0, clk_i2s_src_aud0); + } + return clock_get_frequency(clock_i2s0); + } else if (ptr == HPM_I2S1) { + if ((sample_rate % 22050) == 0) { + clock_set_source_divider(clock_aud1, clk_src_pll1_clk0, 71); /* config clock_aud1 for 22050*n sample rate */ + clock_add_to_group(clock_i2s1, 0); + clock_set_i2s_source(clock_i2s1, clk_i2s_src_aud1); + } else { + clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 21); /* default 24576000Hz */ + clock_add_to_group(clock_i2s1, 0); + clock_set_i2s_source(clock_i2s1, clk_i2s_src_aud1); + } + return clock_get_frequency(clock_i2s1); + } else if (ptr == HPM_I2S3) { + if ((sample_rate % 22050) == 0) { + clock_set_source_divider(clock_aud3, clk_src_pll1_clk0, 71); /* config clock_aud1 for 22050*n sample rate */ + clock_add_to_group(clock_i2s3, 0); + clock_set_i2s_source(clock_i2s3, clk_i2s_src_aud3); + } else { + clock_set_source_divider(clock_aud3, clk_src_pll3_clk0, 21); /* default 24576000Hz */ + clock_add_to_group(clock_i2s3, 0); + clock_set_i2s_source(clock_i2s3, clk_i2s_src_aud3); + } + return clock_get_frequency(clock_i2s3); + } + return 0; +} + +hpm_stat_t board_init_enet_pins(ENET_Type *ptr) +{ + init_enet_pins(ptr); + + if (ptr == HPM_ENET0) { + gpio_set_pin_output_with_initial(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, + BOARD_ENET_RGMII_RST_GPIO_PIN, 0); + } else { + return status_invalid_argument; + } + + return status_success; +} + +hpm_stat_t board_reset_enet_phy(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + gpio_write_pin(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 0); + board_delay_ms(1); + gpio_write_pin(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 1); + } else { + return status_invalid_argument; + } + + return status_success; +} + +uint8_t board_get_enet_dma_pbl(ENET_Type *ptr) +{ + (void) ptr; + return enet_pbl_32; +} + +hpm_stat_t board_enable_enet_irq(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + intc_m_enable_irq(IRQn_ENET0); + } else { + return status_invalid_argument; + } + + return status_success; +} + +hpm_stat_t board_disable_enet_irq(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + intc_m_disable_irq(IRQn_ENET0); + } else { + return status_invalid_argument; + } + + return status_success; +} + +void board_init_enet_pps_pins(ENET_Type *ptr) +{ + (void) ptr; + init_enet_pps_pins(); +} + +hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr) +{ + /* set clock source */ + if (ptr == HPM_ENET0) { + /* make sure pll0_clk0 output clock at 800MHz to get a clock at 100MHz for the enet0 ptp function */ + clock_set_source_divider(clock_ptp0, clk_src_pll1_clk0, 8); /* 100MHz */ + } else { + return status_invalid_argument; + } + + return status_success; +} + +hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) +{ + (void) ptr; + (void) internal; + return status_success; +} + +hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + return enet_rgmii_set_clock_delay(ptr, BOARD_ENET_RGMII_TX_DLY, BOARD_ENET_RGMII_RX_DLY); + } + + return status_invalid_argument; +} + +void board_init_adc16_pins(void) +{ + init_adc_pins(); +} + +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) +{ + uint32_t freq = 0; + + if (ptr == HPM_ADC0) { + if (clk_src_ahb) { + /* Configure the ADC clock from AXI (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll0_clk1 divided by 4 (@200MHz by default) */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U); + } + + freq = clock_get_frequency(clock_adc0); + } + + return freq; +} + + +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) +{ + uint32_t freq = 0; + + if (ptr == HPM_GPTMR0) { + clock_add_to_group(clock_gptmr0, 0); + clock_set_source_divider(clock_gptmr0, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_gptmr0); + } + else if (ptr == HPM_GPTMR1) { + clock_add_to_group(clock_gptmr1, 0); + clock_set_source_divider(clock_gptmr1, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_gptmr1); + } + else if (ptr == HPM_GPTMR2) { + clock_add_to_group(clock_gptmr2, 0); + clock_set_source_divider(clock_gptmr2, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_gptmr2); + } + else if (ptr == HPM_GPTMR3) { + clock_add_to_group(clock_gptmr3, 0); + clock_set_source_divider(clock_gptmr3, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_gptmr3); + } + else if (ptr == HPM_GPTMR4) { + clock_add_to_group(clock_gptmr4, 0); + clock_set_source_divider(clock_gptmr4, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_gptmr4); + } + else if (ptr == HPM_GPTMR5) { + clock_add_to_group(clock_gptmr5, 0); + clock_set_source_divider(clock_gptmr5, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_gptmr5); + } + else if (ptr == HPM_GPTMR6) { + clock_add_to_group(clock_gptmr6, 0); + clock_set_source_divider(clock_gptmr6, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_gptmr6); + } + else if (ptr == HPM_GPTMR7) { + clock_add_to_group(clock_gptmr7, 0); + clock_set_source_divider(clock_gptmr7, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_gptmr7); + } + else { + /* Invalid instance */ + } +} + diff --git a/bsp/hpmicro/hpm6800evk/board/board.h b/bsp/hpmicro/hpm6800evk/board/board.h new file mode 100644 index 00000000000..6753711b5f0 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/board/board.h @@ -0,0 +1,490 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_BOARD_H +#define _HPM_BOARD_H +#include +#include "hpm_common.h" +#include "hpm_clock_drv.h" +#include "hpm_lcdc_drv.h" +#include "hpm_soc.h" +#include "hpm_soc_feature.h" +#include "pinmux.h" +#ifdef CONFIG_HPM_PANEL +#include "hpm_panel.h" +#endif +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#include "hpm_debug_console.h" +#endif + +#define BOARD_NAME "hpm6800evk" +#define BOARD_UF2_SIGNATURE (0x0A4D5048UL) + +/* dma section */ +#define BOARD_APP_XDMA HPM_XDMA +#define BOARD_APP_HDMA HPM_HDMA +#define BOARD_APP_XDMA_IRQ IRQn_XDMA +#define BOARD_APP_HDMA_IRQ IRQn_HDMA +#define BOARD_APP_DMAMUX HPM_DMAMUX +#define TEST_DMA_CONTROLLER HPM_HDMA +#define TEST_DMA_IRQ IRQn_HDMA + +#ifndef BOARD_RUNNING_CORE +#define BOARD_RUNNING_CORE HPM_CORE0 +#endif + +/* uart section */ +#ifndef BOARD_APP_UART_BASE +#define BOARD_APP_UART_BASE HPM_UART3 +#define BOARD_APP_UART_IRQ IRQn_UART3 +#define BOARD_APP_UART_BAUDRATE (115200UL) +#define BOARD_APP_UART_CLK_NAME clock_uart3 +#define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART3_RX +#define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART3_TX +#endif + +/* uart lin sample section */ +#define BOARD_UART_LIN BOARD_APP_UART_BASE +#define BOARD_UART_LIN_IRQ BOARD_APP_UART_IRQ +#define BOARD_UART_LIN_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_UART_LIN_TX_PORT GPIO_DI_GPIOE +#define BOARD_UART_LIN_TX_PIN (15U) /* PE15 should align with used pin in pinmux configuration */ + + +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#ifndef BOARD_CONSOLE_TYPE +#define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART +#endif +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART +#ifndef BOARD_CONSOLE_UART_BASE +#define BOARD_CONSOLE_UART_BASE HPM_UART0 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART0 +#define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX +#define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX +#endif +#define BOARD_CONSOLE_UART_BAUDRATE (115200UL) +#endif +#endif + +/* uart microros sample section */ +#define BOARD_MICROROS_UART_BASE BOARD_APP_UART_BASE +#define BOARD_MICROROS_UART_IRQ BOARD_APP_UART_IRQ +#define BOARD_MICROROS_UART_CLK_NAME BOARD_APP_UART_CLK_NAME + +/* rtthread-nano finsh section */ +#define BOARD_RT_CONSOLE_BASE BOARD_CONSOLE_UART_BASE + +/* usb cdc acm uart section */ +#define BOARD_USB_CDC_ACM_UART BOARD_APP_UART_BASE +#define BOARD_USB_CDC_ACM_UART_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_USB_CDC_ACM_UART_TX_DMA_SRC BOARD_APP_UART_TX_DMA_REQ +#define BOARD_USB_CDC_ACM_UART_RX_DMA_SRC BOARD_APP_UART_RX_DMA_REQ + +/* modbus sample section */ +#define BOARD_MODBUS_UART_BASE BOARD_APP_UART_BASE +#define BOARD_MODBUS_UART_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_MODBUS_UART_RX_DMA_REQ BOARD_APP_UART_RX_DMA_REQ +#define BOARD_MODBUS_UART_TX_DMA_REQ BOARD_APP_UART_TX_DMA_REQ + +/* lin section */ +#define BOARD_LIN HPM_LIN0 +#define BOARD_LIN_CLK_NAME clock_lin0 +#define BOARD_LIN_IRQ IRQn_LIN0 +#define BOARD_LIN_BAUDRATE (19200U) + +/* nor flash section */ +#define BOARD_FLASH_BASE_ADDRESS (0x80000000UL) +#define BOARD_FLASH_SIZE (16 * SIZE_1MB) + +/* i2c section */ +#define BOARD_APP_I2C_BASE HPM_I2C1 +#define BOARD_APP_I2C_IRQ IRQn_I2C1 +#define BOARD_APP_I2C_CLK_NAME clock_i2c1 +#define BOARD_APP_I2C_DMA HPM_HDMA +#define BOARD_APP_I2C_DMAMUX HPM_DMAMUX +#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C1 +#define BOARD_APP_I2C_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 + +/* cam */ +#define BOARD_CAM_I2C_BASE HPM_I2C0 +#define BOARD_CAM_I2C_CLK_NAME clock_i2c0 +#define BOARD_SUPPORT_CAM_RESET +#define BOARD_SUPPORT_CAM_PWDN +#define BOARD_CAM_RST_GPIO_CTRL HPM_GPIO0 +#define BOARD_CAM_RST_GPIO_INDEX GPIO_DI_GPIOA +#define BOARD_CAM_RST_GPIO_PIN 22 +#define BOARD_CAM_PWDN_GPIO_CTRL HPM_GPIO0 +#define BOARD_CAM_PWDN_GPIO_INDEX GPIO_DI_GPIOA +#define BOARD_CAM_PWDN_GPIO_PIN 21 + +/* touch panel */ +#define BOARD_CAP_I2C_BASE (HPM_I2C0) +#define BOARD_CAP_I2C_CLK_NAME clock_i2c0 +#define BOARD_CAP_RST_GPIO (HPM_GPIO0) +#define BOARD_CAP_RST_GPIO_INDEX (GPIO_DI_GPIOY) +#define BOARD_CAP_RST_GPIO_PIN (7) +#define BOARD_CAP_RST_GPIO_IRQ (IRQn_GPIO0_Y) +#define BOARD_CAP_INTR_GPIO (HPM_GPIO0) +#define BOARD_CAP_INTR_GPIO_INDEX (GPIO_DI_GPIOY) +#define BOARD_CAP_INTR_GPIO_PIN (6) +#define BOARD_CAP_INTR_GPIO_IRQ (IRQn_GPIO0_Y) +#define BOARD_CAP_I2C_GPIO HPM_GPIO0 +#define BOARD_CAP_I2C_SDA_GPIO_INDEX (GPIO_DI_GPIOF) +#define BOARD_CAP_I2C_SDA_GPIO_PIN (9) +#define BOARD_CAP_I2C_CLK_GPIO_INDEX (GPIO_DI_GPIOF) +#define BOARD_CAP_I2C_CLK_GPIO_PIN (8) + +/* i2s section */ +#define BOARD_APP_I2S_BASE HPM_I2S3 +#define BOARD_APP_I2S_DATA_LINE (2U) +#define BOARD_APP_I2S_CLK_NAME clock_i2s3 +#define BOARD_APP_I2S_TX_DMA_REQ HPM_DMA_SRC_I2S3_TX +#define BOARD_APP_I2S_IRQ IRQn_I2S3 +#define BOARD_APP_AUDIO_CLK_SRC clock_source_pll3_clk0 +#define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll3clk0 +#define BOARD_PDM_SINGLE_CHANNEL_MASK (0x02U) +#define BOARD_PDM_DUAL_CHANNEL_MASK (0x22U) + +/* i2c for i2s codec section */ +#define BOARD_CODEC_I2C_BASE HPM_I2C3 +#define BOARD_CODEC_I2C_CLK_NAME clock_i2c3 + +/* dma section */ +#define BOARD_APP_XDMA HPM_XDMA +#define BOARD_APP_HDMA HPM_HDMA +#define BOARD_APP_XDMA_IRQ IRQn_XDMA +#define BOARD_APP_HDMA_IRQ IRQn_HDMA +#define BOARD_APP_DMAMUX HPM_DMAMUX + +/* gptmr section */ +#define BOARD_GPTMR HPM_GPTMR2 +#define BOARD_GPTMR_IRQ IRQn_GPTMR2 +#define BOARD_GPTMR_CHANNEL 0 +#define BOARD_GPTMR_DMA_SRC HPM_DMA_SRC_GPTMR2_0 +#define BOARD_GPTMR_CLK_NAME clock_gptmr2 +#define BOARD_GPTMR_PWM HPM_GPTMR2 +#define BOARD_GPTMR_PWM_CHANNEL 0 +#define BOARD_GPTMR_PWM_DMA_SRC HPM_DMA_SRC_GPTMR2_0 +#define BOARD_GPTMR_PWM_CLK_NAME clock_gptmr2 +#define BOARD_GPTMR_PWM_IRQ IRQn_GPTMR2 +#define BOARD_GPTMR_PWM_SYNC HPM_GPTMR2 +#define BOARD_GPTMR_PWM_SYNC_CHANNEL 1 +#define BOARD_GPTMR_PWM_SYNC_CLK_NAME clock_gptmr2 + +/* pinmux section */ +#define USING_GPIO0_FOR_GPIOZ +#ifndef USING_GPIO0_FOR_GPIOZ +#define BOARD_APP_GPIO_CTRL HPM_BGPIO +#define BOARD_APP_GPIO_IRQ IRQn_BGPIO +#else +#define BOARD_APP_GPIO_CTRL HPM_GPIO0 +#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_F +#endif + +/* gpiom section */ +#define BOARD_APP_GPIOM_BASE HPM_GPIOM +#define BOARD_APP_GPIOM_USING_CTRL HPM_FGPIO +#define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast +/* + * in errata, for gpiom, setting the ASSIGN register of GPIOF is invalid. + * so need to configure GPIOE to make it effective at the same time. + */ +#define BOARD_LED_GPIOM_GPIO_INDEX GPIO_DI_GPIOE + +/* spi section */ +#define BOARD_APP_SPI_BASE HPM_SPI3 +#define BOARD_APP_SPI_CLK_NAME clock_spi3 +#define BOARD_APP_SPI_IRQ IRQn_SPI3 +#define BOARD_APP_SPI_SCLK_FREQ (20000000UL) +#define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U) +#define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U) +#define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI3_RX +#define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI3_TX +#define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 +#define BOARD_SPI_CS_PIN IOC_PAD_PE04 +#define BOARD_SPI_CS_ACTIVE_LEVEL (0U) + +/* Flash section */ +#define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) +#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90001U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000005U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) + +/* ADC section */ +#define BOARD_APP_ADC16_NAME "ADC0" +#define BOARD_APP_ADC16_BASE HPM_ADC0 +#define BOARD_APP_ADC16_IRQn IRQn_ADC0 +#define BOARD_APP_ADC16_CH_1 (8U) +#define BOARD_APP_ADC16_CLK_NAME (clock_adc0) + +#define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A + +/* CAN section */ +#define BOARD_APP_CAN_BASE HPM_MCAN3 +#define BOARD_APP_CAN_IRQn IRQn_MCAN3 + +/* + * timer for board delay + */ +#define BOARD_DELAY_TIMER (HPM_GPTMR3) +#define BOARD_DELAY_TIMER_CH 0 +#define BOARD_DELAY_TIMER_CLK_NAME (clock_gptmr3) + +#define BOARD_CALLBACK_TIMER (HPM_GPTMR3) +#define BOARD_CALLBACK_TIMER_CH 1 +#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR3 +#define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr3) + +#define BOARD_CPU_FREQ (500000000UL) + +/* LED */ +#define BOARD_R_GPIO_CTRL HPM_GPIO0 +#define BOARD_R_GPIO_INDEX GPIO_DI_GPIOF +#define BOARD_R_GPIO_PIN 1 +#define BOARD_G_GPIO_CTRL HPM_GPIO0 +#define BOARD_G_GPIO_INDEX GPIO_DI_GPIOF +#define BOARD_G_GPIO_PIN 2 +#define BOARD_B_GPIO_CTRL HPM_GPIO0 +#define BOARD_B_GPIO_INDEX GPIO_DI_GPIOF +#define BOARD_B_GPIO_PIN 5 + +#define BOARD_RGB_RED 0 +#define BOARD_RGB_GREEN (BOARD_RGB_RED + 1) +#define BOARD_RGB_BLUE (BOARD_RGB_RED + 2) + +#define BOARD_LED_GPIO_CTRL BOARD_G_GPIO_CTRL +#define BOARD_LED_GPIO_INDEX BOARD_G_GPIO_INDEX +#define BOARD_LED_GPIO_PIN BOARD_G_GPIO_PIN + +#define BOARD_LED_OFF_LEVEL 0 +#define BOARD_LED_ON_LEVEL !BOARD_LED_OFF_LEVEL +#define BOARD_LED_TOGGLE_RGB 1 + +/* Key */ +#define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOF +#define BOARD_APP_GPIO_PIN 6 + +/* ACMP desction */ +#define BOARD_ACMP 0 +#define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 +#define BOARD_ACMP_IRQ 0 +#define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ +#define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_6 /* align with used pin */ + +#define BOARD_GWC_BASE HPM_GWC0 +#define BOARD_GWC_FUNC_IRQ IRQn_GWCK0_FUNC +#define BOARD_GWC_ERR_IRQ IRQn_GWCK0_ERR +#define BOARD_GWC_PIXEL_WIDTH 1920 +#define BOARD_GWC_PIXEL_HEIGHT 1080 + +/* lcd section */ +#define BOARD_LCD_BASE HPM_LCDC +#define BOARD_LCD_IRQ IRQn_LCDC +#define clock_display clock_lcd0 + +#ifndef BOARD_LCD_WIDTH +#define BOARD_LCD_WIDTH PANEL_SIZE_WIDTH +#endif +#ifndef BOARD_LCD_HEIGHT +#define BOARD_LCD_HEIGHT PANEL_SIZE_HEIGHT +#endif + +/* pdma section */ +#define BOARD_PDMA_BASE HPM_PDMA +#ifndef IRQn_PDMA_D0 +#define IRQn_PDMA_D0 IRQn_PDMA +#endif + +#ifndef BOARD_SHOW_CLOCK +#define BOARD_SHOW_CLOCK 1 +#endif +#ifndef BOARD_SHOW_BANNER +#define BOARD_SHOW_BANNER 1 +#endif + +/* USB */ +#define BOARD_USB HPM_USB0 + +/* FreeRTOS Definitions */ +#define BOARD_FREERTOS_TIMER HPM_GPTMR2 +#define BOARD_FREERTOS_TIMER_CHANNEL 1 +#define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR2 +#define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr2 + +/* Threadx Definitions */ +#define BOARD_THREADX_TIMER HPM_GPTMR2 +#define BOARD_THREADX_TIMER_CHANNEL 1 +#define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR2 +#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr2 +/* SDXC section */ +#define BOARD_APP_SDCARD_SDXC_BASE (HPM_SDXC1) +#define BOARD_APP_SDCARD_SUPPORT_3V3 (1) +#define BOARD_APP_SDCARD_SUPPORT_1V8 (1) +#define BOARD_APP_SDCARD_SUPPORT_4BIT (1) +#define BOARD_APP_SDCARD_SUPPORT_CARD_DETECTION (1) +#define BOARD_APP_SDCARD_SUPPORT_POWER_SWITCH (1) +#define BOARD_APP_SDCARD_SUPPORT_VOLTAGE_SWITCH (1) + +#define BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO (1) +#define BOARD_APP_SDCARD_POWER_SWITCH_USING_GPIO (1) +#define BOARD_APP_SDCARD_VOLTAGE_SWITCH_USING_GPIO (1) +#if BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO +#define BOARD_APP_SDCARD_CARD_DETECTION_PIN IOC_PAD_PD05 +#define BOARD_APP_SDCARD_CARD_DETECTION_PIN_POL (1) /* pin value 0 means card was detected*/ +#endif +#ifdef BOARD_APP_SDCARD_POWER_SWITCH_USING_GPIO +#define BOARD_APP_SDCARD_POWER_SWITCH_PIN IOC_PAD_PD07 +#endif +#ifdef BOARD_APP_SDCARD_VOLTAGE_SWITCH_USING_GPIO +#define BOARD_APP_SDCARD_VSEL_PIN IOC_PAD_PD12 +#endif + +#define BOARD_APP_EMMC_SDXC_BASE (HPM_SDXC0) +#define BOARD_APP_EMMC_SUPPORT_3V3 (0) +#define BOARD_APP_EMMC_SUPPORT_1V8 (1) +#define BOARD_APP_EMMC_SUPPORT_4BIT (1) +#define BOARD_APP_EMMC_SUPPORT_8BIT (1) +#define BOARD_APP_EMMC_SUPPORT_DS (1) +#define BOARD_APP_EMMC_HOST_USING_IRQ (0) + +/* enet section */ +#define BOARD_ENET_COUNT (1U) +#define BOARD_ENET_PPS HPM_ENET0 +#define BOARD_ENET_PPS_IDX enet_pps_0 +#define BOARD_ENET_PPS_PTP_CLOCK clock_ptp0 + +#define BOARD_ENET_RGMII_PHY_ITF enet_inf_rgmii +#define BOARD_ENET_RGMII_RST_GPIO HPM_GPIO0 +#define BOARD_ENET_RGMII_RST_GPIO_INDEX GPIO_DO_GPIOD +#define BOARD_ENET_RGMII_RST_GPIO_PIN (18U) +#define BOARD_ENET_RGMII HPM_ENET0 +#define BOARD_ENET_RGMII_TX_DLY (0U) +#define BOARD_ENET_RGMII_RX_DLY (0U) +#define BOARD_ENET_RGMII_PTP_CLOCK clock_ptp0 +#define BOARD_ENET_RGMII_PPS0_PINOUT (1) + +#define BOARD_ENET0_INF (1U) /* 0: RMII, 1: RGMII */ +#define BOARD_ENET0_INT_REF_CLK (0U) +#define BOARD_ENET0_PHY_RST_TIME (30) +#if BOARD_ENET0_INF +#define BOARD_ENET0_TX_DLY (0U) +#define BOARD_ENET0_RX_DLY (0U) +#endif +#if __USE_ENET_PTP +#define BOARD_ENET0_PTP_CLOCK (clock_ptp0) +#endif + + +/* dram section */ +#define DDR_TYPE_DDR2 (0U) +#define DDR_TYPE_DDR3L (1U) +#define BOARD_DDR_TYPE DDR_TYPE_DDR3L + +#define BOARD_SDRAM_ADDRESS (0x40000000UL) +#if (BOARD_DDR_TYPE == DDR_TYPE_DDR2) +#define BOARD_SDRAM_SIZE (256UL * 1024UL * 1024UL) +#else +#define BOARD_SDRAM_SIZE (512UL * 1024UL * 1024UL) +#endif + +/* Tamper Section */ +#define BOARD_TAMP_ACTIVE_CH 4 +#define BOARD_TAMP_LOW_LEVEL_CH 6 + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +typedef void (*board_timer_cb)(void); + +void board_init(void); +void board_init_console(void); + +void board_init_uart(UART_Type *ptr); +void board_init_i2c(I2C_Type *ptr); +void board_init_can(MCAN_Type *ptr); + +void board_init_gpio_pins(void); +void board_init_spi_pins(SPI_Type *ptr); +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); +void board_write_spi_cs(uint32_t pin, uint8_t state); +uint8_t board_get_led_gpio_off_level(void); +void board_init_led_pins(void); +void board_disable_output_rgb_led(uint8_t color); +void board_enable_output_rgb_led(uint8_t color); + +void board_led_write(uint8_t state); +void board_led_toggle(void); + +/* Initialize SoC overall clocks */ +void board_init_clock(void); + +uint32_t board_init_spi_clock(SPI_Type *ptr); +uint32_t board_init_can_clock(MCAN_Type *ptr); + +void board_init_enet_pps_pins(ENET_Type *ptr); +uint8_t board_get_enet_dma_pbl(ENET_Type *ptr); +hpm_stat_t board_reset_enet_phy(ENET_Type *ptr); +hpm_stat_t board_init_enet_pins(ENET_Type *ptr); +hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal); +hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr); +hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr); +hpm_stat_t board_enable_enet_irq(ENET_Type *ptr); +hpm_stat_t board_disable_enet_irq(ENET_Type *ptr); + +/* + * @brief Initialize PMP and PMA for but not limited to the following purposes: + * -- non-cacheable memory initialization + */ +void board_init_pmp(void); + +void board_delay_us(uint32_t us); +void board_delay_ms(uint32_t ms); + +void board_timer_create(uint32_t ms, board_timer_cb cb); +void board_ungate_mchtmr_at_lp_mode(void); + +/* Initialize the UART clock */ +uint32_t board_init_uart_clock(UART_Type *ptr); + +void board_lcd_backlight(bool is_on); +void board_init_lcd(void); +void board_panel_para_to_lcdc(lcdc_config_t *config); +void board_init_gwc(void); +void board_init_cap_touch(void); +void board_init_usb_pins(void); +void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); + +void board_init_sd_pins(SDXC_Type *ptr); +uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inverse); +void board_sd_switch_pins_to_1v8(SDXC_Type *ptr); +bool board_sd_detect_card(SDXC_Type *ptr); + +uint32_t board_init_dao_clock(void); +uint32_t board_init_pdm_clock(void); +uint32_t board_init_i2s_clock(I2S_Type *ptr); +uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate); + +void board_init_adc16_pins(void); +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb); + +void board_init_cam_pins(void); +void board_write_cam_rst(uint8_t state); +void board_write_cam_pwdn(uint8_t state); +uint32_t board_init_cam_clock(CAM_Type *ptr); + +void board_init_mipi_csi_cam_pins(void); +void board_write_mipi_csi_cam_rst(uint8_t state); +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); + +void board_sd_power_switch(SDXC_Type *ptr, bool on_off); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _HPM_BOARD_H */ diff --git a/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/boards/hpm6800evk.cfg b/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/boards/hpm6800evk.cfg new file mode 100644 index 00000000000..cbc88524f1e --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/boards/hpm6800evk.cfg @@ -0,0 +1,220 @@ +# Copyright (c) 2023 HPMicro +# SPDX-License-Identifier: BSD-3-Clause +flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x7 + +proc init_clock {} { + $::_TARGET0 riscv dmi_write 0x39 0xF4000800 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000810 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000820 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000830 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + echo "clocks has been enabled!" +} + +proc init_ddr3 {} { +# ddr dcdc setup + $::_TARGET0 riscv dmi_write 0x39 0xF4104080 + $::_TARGET0 riscv dmi_write 0x3C 0x10578 + +# ddr3 setup + $::_TARGET0 riscv dmi_write 0x39 0xF40C0180 + $::_TARGET0 riscv dmi_write 0x3C 0x30000019 + $::_TARGET0 riscv dmi_write 0x39 0xF400180C + $::_TARGET0 riscv dmi_write 0x3C 0x09100401 + + $::_TARGET0 riscv dmi_write 0x39 0xF4153000 + $::_TARGET0 riscv dmi_write 0x3C 0xF0000010 + + $::_TARGET0 riscv dmi_write 0x39 0xF30101B0 + $::_TARGET0 riscv dmi_write 0x3C 0 + + $::_TARGET0 riscv dmi_write 0x39 0xF4150040 + $::_TARGET0 riscv dmi_write 0x3C 0xf004641f + + $::_TARGET0 riscv dmi_write 0x39 0xF4153000 + $::_TARGET0 riscv dmi_write 0x3C 0xf0000011 + + $::_TARGET0 riscv dmi_write 0x39 0xF3013000 + $::_TARGET0 riscv dmi_write 0x3C 0xf4000000 + + $::_TARGET0 riscv dmi_write 0x39 0xF3010490 + $::_TARGET0 riscv dmi_write 0x3C 1 + + $::_TARGET0 riscv dmi_write 0x39 0xF3010000 + $::_TARGET0 riscv dmi_write 0x3C 0x1040001 + + $::_TARGET0 riscv dmi_write 0x39 0xF30100D0 + $::_TARGET0 riscv dmi_write 0x3C 0x4002004e + + $::_TARGET0 riscv dmi_write 0x39 0xF3010110 + $::_TARGET0 riscv dmi_write 0x3C 0x05010407 + $::_TARGET0 riscv dmi_write 0x39 0xF3010190 + $::_TARGET0 riscv dmi_write 0x3C 0x07040102 + $::_TARGET0 riscv dmi_write 0x39 0xF3010194 + $::_TARGET0 riscv dmi_write 0x3C 0x20404 + $::_TARGET0 riscv dmi_write 0x39 0xF30101A4 + $::_TARGET0 riscv dmi_write 0x3C 0x20008 + $::_TARGET0 riscv dmi_write 0x39 0xF3010240 + $::_TARGET0 riscv dmi_write 0x3C 0x06000600 + + $::_TARGET0 riscv dmi_write 0x39 0xF3010200 + $::_TARGET0 riscv dmi_write 0x3C 0x1F1F1F + $::_TARGET0 riscv dmi_write 0x39 0xF3010204 + $::_TARGET0 riscv dmi_write 0x3C 0x121212 + $::_TARGET0 riscv dmi_write 0x39 0xF3010208 + $::_TARGET0 riscv dmi_write 0x3C 0 + $::_TARGET0 riscv dmi_write 0x39 0xF301020C + $::_TARGET0 riscv dmi_write 0x3C 0 + $::_TARGET0 riscv dmi_write 0x39 0xF3010210 + $::_TARGET0 riscv dmi_write 0x3C 0x1F1F + $::_TARGET0 riscv dmi_write 0x39 0xF3010214 + $::_TARGET0 riscv dmi_write 0x3C 0x06030303 + $::_TARGET0 riscv dmi_write 0x39 0xF3010218 + $::_TARGET0 riscv dmi_write 0x3C 0x0F060606 + + $::_TARGET0 riscv dmi_write 0x39 0xF3013000 + $::_TARGET0 riscv dmi_write 0x3C 0xFC000000 + + $::_TARGET0 riscv dmi_write 0x39 0xF4150054 + $::_TARGET0 riscv dmi_write 0x3C 0xc70 + $::_TARGET0 riscv dmi_write 0x39 0xF4150058 + $::_TARGET0 riscv dmi_write 0x3C 0x6 + $::_TARGET0 riscv dmi_write 0x39 0xF415005c + $::_TARGET0 riscv dmi_write 0x3C 0x18 + $::_TARGET0 riscv dmi_write 0x39 0xF4150048 + $::_TARGET0 riscv dmi_write 0x3C 0x919c8866 + $::_TARGET0 riscv dmi_write 0x39 0xF415004c + $::_TARGET0 riscv dmi_write 0x3C 0x1a838360 + $::_TARGET0 riscv dmi_write 0x39 0xF415008c + $::_TARGET0 riscv dmi_write 0x3C 0xf06d50 + $::_TARGET0 riscv dmi_write 0x39 0xF4150050 + $::_TARGET0 riscv dmi_write 0x3C 0x3002d200 + + + $::_TARGET0 riscv dmi_write 0x39 0xF30101b0 + $::_TARGET0 riscv dmi_write 0x3C 1 + sleep 100 + + $::_TARGET0 riscv dmi_write 0x39 0xF4150068 + $::_TARGET0 riscv dmi_write 0x3C 0x930035C7 + $::_TARGET0 riscv dmi_write 0x39 0xF4150004 + $::_TARGET0 riscv dmi_write 0x3C 0xFF81 + sleep 200 + + echo "ddr3 has been enabled!" +} + +proc init_dram {} { +# ddr dcdc setup + $::_TARGET0 riscv dmi_write 0x39 0xF4104080 + $::_TARGET0 riscv dmi_write 0x3C 0x10708 + +# pll1 setup + $::_TARGET0 riscv dmi_write 0x39 0xF40c0180 + $::_TARGET0 riscv dmi_write 0x3C 0xb0000016 + $::_TARGET0 riscv dmi_write 0x39 0xF40c0184 + $::_TARGET0 riscv dmi_write 0x3C 0 + $::_TARGET0 riscv dmi_write 0x39 0xF40c0188 + $::_TARGET0 riscv dmi_write 0x3C 0xe4e1c00 + +#ddr setup + $::_TARGET0 riscv dmi_write 0x39 0xF3010000 + $::_TARGET0 riscv dmi_write 0x3C 0x3040000 + + $::_TARGET0 riscv dmi_write 0x39 0xF30101B0 + $::_TARGET0 riscv dmi_write 0x3C 0 + + $::_TARGET0 riscv dmi_write 0x39 0xF4150044 + $::_TARGET0 riscv dmi_write 0x3C 0x40a + + $::_TARGET0 riscv dmi_write 0x39 0xF4150040 + $::_TARGET0 riscv dmi_write 0x3C 0xf004641f + + $::_TARGET0 riscv dmi_write 0x39 0xF4153000 + $::_TARGET0 riscv dmi_write 0x3C 0xf0000011 + + $::_TARGET0 riscv dmi_write 0x39 0xF3013000 + $::_TARGET0 riscv dmi_write 0x3C 0xf4000000 + + $::_TARGET0 riscv dmi_write 0x39 0xF3010490 + $::_TARGET0 riscv dmi_write 0x3C 1 + + $::_TARGET0 riscv dmi_write 0x39 0xF3010000 + $::_TARGET0 riscv dmi_write 0x3C 0x1040000 + $::_TARGET0 riscv dmi_write 0x39 0xF3010190 + $::_TARGET0 riscv dmi_write 0x3C 0x07010101 + $::_TARGET0 riscv dmi_write 0x39 0xF3010194 + $::_TARGET0 riscv dmi_write 0x3C 0x20404 + $::_TARGET0 riscv dmi_write 0x39 0xF30101A4 + $::_TARGET0 riscv dmi_write 0x3C 0x20008 + $::_TARGET0 riscv dmi_write 0x39 0xF3010240 + $::_TARGET0 riscv dmi_write 0x3C 0x6000600 + $::_TARGET0 riscv dmi_write 0x39 0xF3010200 + $::_TARGET0 riscv dmi_write 0x3C 0x1f1f1f + $::_TARGET0 riscv dmi_write 0x39 0xF3010204 + $::_TARGET0 riscv dmi_write 0x3C 0x70707 + $::_TARGET0 riscv dmi_write 0x39 0xF3010208 + $::_TARGET0 riscv dmi_write 0x3C 0 + $::_TARGET0 riscv dmi_write 0x39 0xF301020c + $::_TARGET0 riscv dmi_write 0x3C 0 + $::_TARGET0 riscv dmi_write 0x39 0xF3010210 + $::_TARGET0 riscv dmi_write 0x3C 0x1f1f + $::_TARGET0 riscv dmi_write 0x39 0xF3010214 + $::_TARGET0 riscv dmi_write 0x3C 0x6060606 + $::_TARGET0 riscv dmi_write 0x39 0xF3010218 + $::_TARGET0 riscv dmi_write 0x3C 0xf0f0606 + + $::_TARGET0 riscv dmi_write 0x39 0xF3013000 + $::_TARGET0 riscv dmi_write 0x3C 0xfc000000 + $::_TARGET0 riscv dmi_write 0x39 0xF4150020 + $::_TARGET0 riscv dmi_write 0x3C 0x3000100 + $::_TARGET0 riscv dmi_write 0x39 0xF4150028 + $::_TARGET0 riscv dmi_write 0x3C 0x18002356 + $::_TARGET0 riscv dmi_write 0x39 0xF415002c + $::_TARGET0 riscv dmi_write 0x3C 0x0aac4156 + $::_TARGET0 riscv dmi_write 0x39 0xF4150054 + $::_TARGET0 riscv dmi_write 0x3C 0xe73 + $::_TARGET0 riscv dmi_write 0x39 0xF4150058 + $::_TARGET0 riscv dmi_write 0x3C 0x5 + $::_TARGET0 riscv dmi_write 0x39 0xF415005c + $::_TARGET0 riscv dmi_write 0x3C 0 + $::_TARGET0 riscv dmi_write 0x39 0xF4150048 + $::_TARGET0 riscv dmi_write 0x3C 0xf2adfe53 + $::_TARGET0 riscv dmi_write 0x39 0xF415004c + $::_TARGET0 riscv dmi_write 0x3C 0x22820362 + $::_TARGET0 riscv dmi_write 0x39 0xF4150050 + $::_TARGET0 riscv dmi_write 0x3C 0x30020100 + $::_TARGET0 riscv dmi_write 0x39 0xF415008c + $::_TARGET0 riscv dmi_write 0x3C 0xf06d50 + + $::_TARGET0 riscv dmi_write 0x39 0xF30101b0 + $::_TARGET0 riscv dmi_write 0x3C 1 + sleep 100 + + $::_TARGET0 riscv dmi_write 0x39 0xF4150068 + $::_TARGET0 riscv dmi_write 0x3C 0x91003587 + $::_TARGET0 riscv dmi_write 0x39 0xF4150004 + $::_TARGET0 riscv dmi_write 0x3C 0xF501 + sleep 200 + echo "ddr has been enabled!" +} + +$_TARGET0 configure -event reset-end { + init_clock + # init_ddr3 +} + +$_TARGET0 configure -event reset-init { + init_clock + init_ddr3 +} + +$_TARGET0 configure -event gdb-attach { + reset halt +} diff --git a/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg b/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg new file mode 100644 index 00000000000..b9ae1121044 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg @@ -0,0 +1,11 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 + +source [find interface/cmsis-dap.cfg] + +transport select jtag +reset_config srst_only diff --git a/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/probes/ft2232.cfg b/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/probes/ft2232.cfg new file mode 100644 index 00000000000..580d98ef853 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/probes/ft2232.cfg @@ -0,0 +1,15 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +reset_config trst_and_srst +adapter srst delay 50 + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0208 0x020b +ftdi_layout_signal nTRST -data 0x0200 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0100 -noe 0x0800 + diff --git a/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/probes/ft232.cfg b/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/probes/ft232.cfg new file mode 100644 index 00000000000..4fb0fba2e70 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/probes/ft232.cfg @@ -0,0 +1,14 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +reset_config trst_and_srst +adapter srst delay 50 + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6014 + +ftdi_layout_init 0x0018 0x001b +ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/probes/jlink.cfg b/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/probes/jlink.cfg new file mode 100644 index 00000000000..fd8f04428c9 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/probes/jlink.cfg @@ -0,0 +1,11 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 + +source [find interface/jlink.cfg] + +transport select jtag +reset_config srst_only diff --git a/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg b/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg new file mode 100644 index 00000000000..e9d6e6d6984 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg @@ -0,0 +1,14 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 +reset_config srst_only + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x010b +ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/soc/hpm6880.cfg b/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/soc/hpm6880.cfg new file mode 100644 index 00000000000..f1785609bab --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/soc/hpm6880.cfg @@ -0,0 +1,13 @@ +# Copyright (c) 2023 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +set _CHIP hpm6880 +set _CPUTAPID 0x1000563D +jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID + +set _TARGET0 $_CHIP.cpu0 +target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0 + +$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 + +targets $_TARGET0 diff --git a/bsp/hpmicro/hpm6800evk/board/fal_cfg.h b/bsp/hpmicro/hpm6800evk/board/fal_cfg.h new file mode 100644 index 00000000000..3533c1fbb2c --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/board/fal_cfg.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + +#ifdef RT_USING_FAL +#define NOR_FLASH_DEV_NAME "norflash0" +#define NOR_FLASH_MEM_BASE 0x80000000UL +#define NOR_FLASH_SIZE_IN_BYTES 0x1000000UL + +/* ===================== Flash device Configuration ========================= */ +extern const struct fal_flash_dev stm32f2_onchip_flash; +extern struct fal_flash_dev nor_flash0; + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &nor_flash0, \ +} +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG +/* partition table */ +#ifdef CONFIG_WEBNET_FAL_FS +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WORD, "app", NOR_FLASH_DEV_NAME, 0, 6*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "fs", NOR_FLASH_DEV_NAME, 6*1024*1024, 10*1024*1024, 0}, \ +} +#else +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WORD, "app", NOR_FLASH_DEV_NAME, 0, 4*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME, 4*1024*1024, 3*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "download", NOR_FLASH_DEV_NAME, 7*1024*1024, 8*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "flashdb", NOR_FLASH_DEV_NAME, 15*1024*1024, 1*1024*1024, 0}, \ +} +#endif +#endif /* FAL_PART_HAS_TABLE_CFG */ +#endif /* RT_USING_FAL */ + +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/hpmicro/hpm6800evk/board/fal_flash_port.c b/bsp/hpmicro/hpm6800evk/board/fal_flash_port.c new file mode 100644 index 00000000000..6960ab7f675 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/board/fal_flash_port.c @@ -0,0 +1,268 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2022-03-09 hpmicro First implementation + * 2022-08-01 hpmicro Fixed random crashing during kvdb_init + * 2022-08-03 hpmicro Improved erase speed + * 2023-05-15 hpmicro Disable global interrupt during FLASH operation for FLASH build + * + */ +#include +#include +#ifdef RT_USING_FAL +#include "fal.h" +#include "hpm_romapi.h" +#include "board.h" +#include "hpm_l1c_drv.h" + +#if defined(FLASH_XIP) && (FLASH_XIP == 1) + +static rt_base_t s_interrupt_level; +#define FAL_ENTER_CRITICAL() do {\ + rt_exit_critical();\ + fencei();\ + s_interrupt_level = rt_hw_interrupt_disable();\ + } while(0) + +#define FAL_EXIT_CRITICAL() do {\ + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(BOARD_APP_XPI_NOR_XPI_BASE);\ + fencei();\ + rt_exit_critical();\ + rt_hw_interrupt_enable(s_interrupt_level);\ + } while(0) + +#define FAL_RAMFUNC __attribute__((section(".isr_vector"))) + +#else +#define FAL_ENTER_CRITICAL() rt_enter_critical() + +#define FAL_EXIT_CRITICAL() rt_exit_critical() + +#define FAL_RAMFUNC + +#endif + +/*************************************************************************************************** + * FAL Porting Guide + * + * 1. Most FLASH devices do not support RWW (Read-while-Write), the codes to access the FLASH + * must be placed at RAM or ROM code + * 2. During FLASH erase/program, it is recommended to disable the interrupt, or place the + * interrupt related codes to RAM + * + ***************************************************************************************************/ + +static int init(void); +static int read(long offset, uint8_t *buf, size_t size); +static int write(long offset, const uint8_t *buf, size_t size); +static int erase(long offset, size_t size); + +static xpi_nor_config_t s_flashcfg; + +/** + * @brief FAL Flash device context + */ +struct fal_flash_dev nor_flash0 = + { + .name = NOR_FLASH_DEV_NAME, + /* If porting this code to the device with FLASH connected to XPI1, the address must be changed to 0x90000000 */ + .addr = NOR_FLASH_MEM_BASE, + .len = 8 * 1024 * 1024, + .blk_size = 4096, + .ops = { .init = init, .read = read, .write = write, .erase = erase }, + .write_gran = 1 + }; + +/** + * @brief FAL initialization + * This function probes the FLASH using the ROM API + */ +FAL_RAMFUNC static int init(void) +{ + int ret = RT_EOK; + xpi_nor_config_option_t cfg_option; + cfg_option.header.U = BOARD_APP_XPI_NOR_CFG_OPT_HDR; + cfg_option.option0.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT0; + cfg_option.option1.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT1; + + FAL_ENTER_CRITICAL(); + hpm_stat_t status = rom_xpi_nor_auto_config(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, &cfg_option); + FAL_EXIT_CRITICAL(); + if (status != status_success) + { + ret = -RT_ERROR; + } + else + { + /* update the flash chip information */ + uint32_t sector_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, §or_size); + uint32_t flash_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_total_size, &flash_size); + nor_flash0.blk_size = sector_size; + nor_flash0.len = flash_size; + } + + return ret; +} + +/** + * @brief FAL read function + * Read data from FLASH + * @param offset FLASH offset + * @param buf Buffer to hold data read by this API + * @param size Size of data to be read + * @return actual read bytes + */ +FAL_RAMFUNC static int read(long offset, uint8_t *buf, size_t size) +{ + uint32_t flash_addr = nor_flash0.addr + offset; + uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN(flash_addr); + uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP(flash_addr + size); + uint32_t aligned_size = aligned_end - aligned_start; + rt_base_t level = rt_hw_interrupt_disable(); + l1c_dc_invalidate(aligned_start, aligned_size); + rt_hw_interrupt_enable(level); + + (void) rt_memcpy(buf, (void*) flash_addr, size); + + return size; +} + +/** + * @brief Write unaligned data to the page + * @param offset FLASH offset + * @param buf Data buffer + * @param size Size of data to be written + * @return actual size of written data or error code + */ +FAL_RAMFUNC static int write_unaligned_page_data(long offset, const uint32_t *buf, size_t size) +{ + hpm_stat_t status; + + FAL_ENTER_CRITICAL(); + status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, buf, offset, size); + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + return -RT_ERROR; + rt_kprintf("write failed, status=%d\n", status); + } + + return size; +} + +/** + * @brief FAL write function + * Write data to specified FLASH address + * @param offset FLASH offset + * @param buf Data buffer + * @param size Size of data to be written + * @return actual size of written data or error code + */ +FAL_RAMFUNC static int write(long offset, const uint8_t *buf, size_t size) +{ + uint32_t *src = NULL; + uint32_t buf_32[64]; + uint32_t write_size; + size_t remaining_size = size; + int ret = (int)size; + + uint32_t page_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_page_size, &page_size); + uint32_t offset_in_page = offset % page_size; + if (offset_in_page != 0) + { + uint32_t write_size_in_page = page_size - offset_in_page; + uint32_t write_page_size = MIN(write_size_in_page, size); + (void) rt_memcpy(buf_32, buf, write_page_size); + write_size = write_unaligned_page_data(offset, buf_32, write_page_size); + if (write_size < 0) + { + ret = -RT_ERROR; + goto write_quit; + } + + remaining_size -= write_page_size; + offset += write_page_size; + buf += write_page_size; + } + + while (remaining_size > 0) + { + write_size = MIN(remaining_size, sizeof(buf_32)); + rt_memcpy(buf_32, buf, write_size); + src = &buf_32[0]; + + FAL_ENTER_CRITICAL(); + hpm_stat_t status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, src, + offset, write_size); + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + ret = -RT_ERROR; + rt_kprintf("write failed, status=%d\n", status); + break; + } + + remaining_size -= write_size; + buf += write_size; + offset += write_size; + } + +write_quit: + return ret; +} + +/** + * @brief FAL erase function + * Erase specified FLASH region + * @param offset the start FLASH address to be erased + * @param size size of the region to be erased + * @ret RT_EOK Erase operation is successful + * @retval -RT_ERROR Erase operation failed + */ +FAL_RAMFUNC static int erase(long offset, size_t size) +{ + uint32_t aligned_size = (size + nor_flash0.blk_size - 1U) & ~(nor_flash0.blk_size - 1U); + hpm_stat_t status; + int ret = (int)size; + + uint32_t block_size; + uint32_t sector_size; + (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, §or_size); + (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_block_size, &block_size); + uint32_t erase_unit; + while (aligned_size > 0) + { + FAL_ENTER_CRITICAL(); + if ((offset % block_size == 0) && (aligned_size >= block_size)) + { + erase_unit = block_size; + status = rom_xpi_nor_erase_block(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset); + } + else + { + erase_unit = sector_size; + status = rom_xpi_nor_erase_sector(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset); + } + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + ret = -RT_ERROR; + break; + } + offset += erase_unit; + aligned_size -= erase_unit; + } + + return ret; +} +#endif /* RT_USING_FAL */ diff --git a/bsp/hpmicro/hpm6800evk/board/hpm_wm8960.c b/bsp/hpmicro/hpm6800evk/board/hpm_wm8960.c new file mode 100644 index 00000000000..bbb1b25beb4 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/board/hpm_wm8960.c @@ -0,0 +1,543 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include +#include "hpm_wm8960.h" + +#ifndef HPM_WM8960_MCLK_TOLERANCE +#define HPM_WM8960_MCLK_TOLERANCE (4U) +#endif + +/* wm8960 register default value */ +static const uint16_t wm8960_default_reg_val[WM8960_REG_NUM] = { + 0x0097, 0x0097, 0x0000, 0x0000, 0x0000, 0x0008, 0x0000, 0x000a, 0x01c0, 0x0000, 0x00ff, 0x00ff, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x007b, 0x0100, 0x0032, 0x0000, 0x00c3, 0x00c3, 0x01c0, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0100, 0x0100, 0x0050, 0x0050, 0x0050, 0x0050, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0040, 0x0000, 0x0000, 0x0050, 0x0050, 0x0000, 0x0002, 0x0037, 0x004d, 0x0080, 0x0008, 0x0031, 0x0026, 0x00e9, +}; + +/* store reg value */ +static uint16_t wm8960_reg_val[WM8960_REG_NUM]; + +hpm_stat_t wm8960_init(wm8960_control_t *control, wm8960_config_t *config) +{ + assert(control != NULL); + assert(config != NULL); + + hpm_stat_t stat = status_success; + + (void)memcpy(wm8960_reg_val, wm8960_default_reg_val, sizeof(wm8960_default_reg_val)); + + /* Reset */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RESET, 0x00)); + + /* Power on input modules */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, 0xFE)); + /* Power on output modules */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER2, 0x1F8)); + /* Power on PGA and mixer */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x3C)); + + /* ADC and DAC uses same clock */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_IFACE2, 0x40)); + + /* set data protocol */ + HPM_CHECK_RET(wm8960_set_protocol(control, config->bus)); + + /* set wm8960 as slave */ + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_MS_MASK, WM8960_IFACE1_MS_SET(0))); + + /* invert LRCLK */ + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_LRP_MASK, WM8960_IFACE1_LRP_SET(1))); + + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ADDCTL1, 0xC0)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ADDCTL4, 0x40)); + + /* ADC volume, 8dB */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LADC, 0x1D3)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RADC, 0x1D3)); + + /* Digital DAC volume, 0dB */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LDAC, 0x1E0)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RDAC, 0x1E0)); + + /* Headphone volume, LOUT1 and ROUT1, 6dB */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT1, 0x17F)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT1, 0x17F)); + + /* speaker volume 6dB */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT2, 0x1ff)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT2, 0x1ff)); + /* enable class D output */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_CLASSD1, 0xf7)); + + /* Unmute DAC. */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_DACCTL1, 0x0000)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, 0x117)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, 0x117)); + + HPM_CHECK_RET(wm8960_set_data_format(control, config->format.mclk_hz, config->format.sample_rate, config->format.bit_width)); + + /* set data route */ + HPM_CHECK_RET(wm8960_set_data_route(control, config)); + + return status_success; +} + +hpm_stat_t wm8960_deinit(wm8960_control_t *control) +{ + hpm_stat_t stat = status_success; + + /* power off all modules */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, 0x00U)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER2, 0x00U)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x00U)); + + return status_success; +} + +hpm_stat_t wm8960_set_protocol(wm8960_control_t *control, wm8960_protocol_t protocol) +{ + return wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_FORMAT_MASK, (uint16_t)protocol); +} + +hpm_stat_t wm8960_set_module(wm8960_control_t *control, wm8960_module_t module, bool enable) +{ + hpm_stat_t stat = status_success; + switch (module) { + case wm8960_module_adc: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_ADCL_MASK, + ((uint16_t)enable << WM8960_POWER1_ADCL_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_ADCR_MASK, + ((uint16_t)enable << WM8960_POWER1_ADCR_SHIFT))); + break; + case wm8960_module_dac: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_DACL_MASK, + ((uint16_t)enable << WM8960_POWER2_DACL_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_DACR_MASK, + ((uint16_t)enable << WM8960_POWER2_DACR_SHIFT))); + break; + case wm8960_module_vref: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_VREF_MASK, + ((uint16_t)enable << WM8960_POWER1_VREF_SHIFT))); + break; + case wm8960_module_ana_in: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_AINL_MASK, + ((uint16_t)enable << WM8960_POWER1_AINL_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_AINR_MASK, + ((uint16_t)enable << WM8960_POWER1_AINR_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER3, WM8960_POWER3_LMIC_MASK, + ((uint16_t)enable << WM8960_POWER3_LMIC_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER3, WM8960_POWER3_RMIC_MASK, + ((uint16_t)enable << WM8960_POWER3_RMIC_SHIFT))); + break; + case wm8960_module_lineout: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_LOUT1_MASK, + ((uint16_t)enable << WM8960_POWER2_LOUT1_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_ROUT1_MASK, + ((uint16_t)enable << WM8960_POWER2_ROUT1_SHIFT))); + break; + case wm8960_module_micbais: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_MICB_MASK, + ((uint16_t)enable << WM8960_POWER1_MICB_SHIFT))); + break; + case wm8960_module_speaker: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_SPKL_MASK, + ((uint16_t)enable << WM8960_POWER2_SPKL_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_SPKR_MASK, + ((uint16_t)enable << WM8960_POWER2_SPKR_SHIFT))); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_CLASSD1, 0xF7)); + break; + case wm8960_module_output_mixer: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER3, WM8960_POWER3_LOMIX_MASK, + ((uint16_t)enable << WM8960_POWER3_LOMIX_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER3, WM8960_POWER3_ROMIX_MASK, + ((uint16_t)enable << WM8960_POWER3_ROMIX_SHIFT))); + break; + default: + stat = status_invalid_argument; + break; + } + return stat; +} + +hpm_stat_t wm8960_set_data_route(wm8960_control_t *control, wm8960_config_t *config) +{ + hpm_stat_t stat = status_success; + + /* select left input */ + HPM_CHECK_RET(wm8960_set_left_input(control, config->left_input)); + /* select right input */ + HPM_CHECK_RET(wm8960_set_right_input(control, config->right_input)); + /* select source to output mixer */ + HPM_CHECK_RET(wm8960_config_input_to_output_mixer(control, config->play_source)); + + switch (config->route) { + case wm8960_route_bypass: + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_micbais, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_ana_in, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_output_mixer, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_lineout, true)); + break; + case wm8960_route_playback: + /* I2S_IN-> DAC-> HP */ + /* Set power for DAC */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x0C)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_dac, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_output_mixer, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_lineout, true)); + break; + case wm8960_route_playback_and_record: + /* Set power */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x3C)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_adc, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_micbais, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_ana_in, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_dac, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_output_mixer, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_lineout, true)); + break; + case wm8960_route_record: + /* ANA_IN->ADC->I2S_OUT */ + /* Power up ADC and AIN */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x30)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_micbais, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_ana_in, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_adc, true)); + break; + default: + stat = status_invalid_argument; + break; + } + return stat; +} + +hpm_stat_t wm8960_set_left_input(wm8960_control_t *control, wm8960_input_t input) +{ + hpm_stat_t stat = status_success; + uint16_t val = 0; + + switch (input) { + case wm8960_input_closed: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val &= (uint16_t) ~(WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + break; + case wm8960_input_single_ended_mic: + /* Only LMN1 enabled, LMICBOOST to 13db, LMIC2B enabled */ + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK | WM8960_POWER1_MICB_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINPATH, 0x138)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, 0x117)); + break; + case wm8960_input_differential_mic_input2: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK | WM8960_POWER1_MICB_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINPATH, 0x178)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, 0x117)); + break; + case wm8960_input_differential_mic_input3: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK | WM8960_POWER1_MICB_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINPATH, 0x1B8)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, 0x117)); + break; + case wm8960_input_line_input2: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_read_reg(WM8960_INBMIX1, &val)); + val |= 0xEU; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_INBMIX1, val)); + break; + case wm8960_input_line_input3: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_read_reg(WM8960_INBMIX1, &val)); + val |= 0x70U; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_INBMIX1, val)); + break; + default: + stat = status_invalid_argument; + break; + } + + return stat; +} + +hpm_stat_t wm8960_set_right_input(wm8960_control_t *control, wm8960_input_t input) +{ + hpm_stat_t stat = status_success; + uint16_t val = 0; + + switch (input) { + case wm8960_input_closed: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val &= (uint16_t) ~(WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + break; + case wm8960_input_single_ended_mic: + /* Only LMN1 enabled, LMICBOOST to 13db, LMIC2B enabled */ + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK | WM8960_POWER1_MICB_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINPATH, 0x138)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, 0x117)); + break; + case wm8960_input_differential_mic_input2: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK | WM8960_POWER1_MICB_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINPATH, 0x178)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, 0x117)); + break; + case wm8960_input_differential_mic_input3: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK | WM8960_POWER1_MICB_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINPATH, 0x1B8)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, 0x117)); + break; + case wm8960_input_line_input2: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_read_reg(WM8960_INBMIX2, &val)); + val |= 0xEU; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_INBMIX2, val)); + break; + case wm8960_input_line_input3: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_read_reg(WM8960_INBMIX2, &val)); + val |= 0x70U; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_INBMIX2, val)); + break; + default: + stat = status_invalid_argument; + break; + } + + return stat; +} + +hpm_stat_t wm8960_set_volume(wm8960_control_t *control, wm8960_module_t module, uint32_t volume) +{ + uint16_t vol = 0; + hpm_stat_t stat = status_success; + switch (module) { + case wm8960_module_adc: + if (volume > 255U) { + stat = status_invalid_argument; + } else { + vol = (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LADC, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RADC, vol)); + /* Update volume */ + vol = (uint16_t)(0x100U | volume); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LADC, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RADC, vol)); + } + break; + case wm8960_module_dac: + if (volume > 255U) { + stat = status_invalid_argument; + } else { + vol = (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LDAC, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RDAC, vol)); + vol = 0x100U | (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LDAC, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RDAC, vol)); + } + break; + case wm8960_module_headphone: + if (volume > 0x7FU) { + stat = status_invalid_argument; + } else { + vol = (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT1, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT1, vol)); + vol = 0x100U | (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT1, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT1, vol)); + } + break; + case wm8960_module_ana_in: + if (volume > 0x3FU) { + stat = status_invalid_argument; + } else { + vol = (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, vol)); + vol = 0x100U | (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, vol)); + } + break; + case wm8960_module_speaker: + if (volume > 0x7FU) { + stat = status_invalid_argument; + } else { + vol = (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT2, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT2, vol)); + vol = 0x100U | (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT2, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT2, vol)); + } + break; + default: + stat = status_invalid_argument; + break; + } + return stat; +} + +static bool wm8960_check_clock_tolerance(uint32_t source, uint32_t target) +{ + uint32_t delta = (source >= target) ? (source - target) : (target - source); + if (delta * 100 <= HPM_WM8960_MCLK_TOLERANCE * target) { + return true; + } + return false; +} + +hpm_stat_t wm8960_set_data_format(wm8960_control_t *control, uint32_t sysclk, uint32_t sample_rate, uint32_t bits) +{ + hpm_stat_t stat = status_success; + uint16_t val = 0; + uint32_t ratio[7] = {256, 256 * 1.5, 256 * 2, 256 * 3, 256 * 4, 256 * 5.5, 256 * 6}; + bool clock_meet_requirement = false; + + if (sysclk / sample_rate > 256 * 6) { + sysclk = sysclk / 2; + val = WM8960_CLOCK1_SYSCLKDIV_SET(2U); /* SYSCLK Pre-divider */ + } + + for (uint8_t i = 0; i < 7; i++) { + if (wm8960_check_clock_tolerance(sysclk, sample_rate * ratio[i])) { + val |= ((i << WM8960_CLOCK1_ADCDIV_SHIFT) | (i << WM8960_CLOCK1_DACDIV_SHIFT)); + clock_meet_requirement = true; + break; + } + } + + if (!clock_meet_requirement) { + return status_invalid_argument; + } + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_CLOCK1, 0x1FEU, val)); + + /* set sample bit */ + switch (bits) { + case 16: + stat = wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, WM8960_IFACE1_WL_SET(0U)); + break; + case 20: + stat = wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, WM8960_IFACE1_WL_SET(1U)); + break; + case 24: + stat = wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, WM8960_IFACE1_WL_SET(2U)); + break; + case 32: + stat = wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, WM8960_IFACE1_WL_SET(3U)); + break; + default: + stat = status_invalid_argument; + break; + } + + return stat; +} + +hpm_stat_t wm8960_config_input_to_output_mixer(wm8960_control_t *control, uint32_t play_source) +{ + hpm_stat_t stat = status_success; + + if ((play_source & (uint32_t)wm8960_play_source_input_mixer) != 0U) { + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS1, 0x80U, 0x80U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS2, 0x80U, 0x80U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_LOUTMIX, 0x180U, 0U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_ROUTMIX, 0x180U, 0U)); + } + + if ((play_source & (uint32_t)wm8960_play_source_dac) != 0U) { + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS1, 0x80U, 0x00U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS2, 0x80U, 0x00U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_LOUTMIX, 0x180U, 0x100U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_ROUTMIX, 0x180U, 0x100U)); + } + + if ((play_source & (uint32_t)wm8960_play_source_input3) != 0U) { + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS1, 0x80U, 0x0U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS2, 0x80U, 0x0U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_LOUTMIX, 0x180U, 0x80U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_ROUTMIX, 0x180U, 0x80U)); + } + + return stat; +} + + +hpm_stat_t wm8960_write_reg(wm8960_control_t *control, uint8_t reg, uint16_t val) +{ + /* The first 7 bits (B15 to B9) are address bits that select which control register */ + /* is accessed. The remaining 9 bits (B8 to B0) are data bits */ + rt_size_t size; + rt_uint8_t data[2]; + data[0] = (reg << 1) | (uint8_t)((val >> 8U) & 0x0001U); + data[1] = (uint8_t)(val & 0xFFU); + + size = rt_i2c_master_send(control->i2c_bus, control->slave_address, RT_I2C_WR, data, 2U); + if (size != 2) { + return status_fail; + } + + wm8960_reg_val[reg] = val; + return status_success; +} + +hpm_stat_t wm8960_read_reg(uint8_t reg, uint16_t *val) +{ + if (reg >= WM8960_REG_NUM) { + return status_invalid_argument; + } + *val = wm8960_reg_val[reg]; + + return status_success; +} + +hpm_stat_t wm8960_modify_reg(wm8960_control_t *control, uint8_t reg, uint16_t mask, uint16_t val) +{ + hpm_stat_t stat = 0; + uint16_t reg_val; + + /* Read the register value out */ + stat = wm8960_read_reg(reg, ®_val); + if (stat != status_success) { + return status_fail; + } + + /* Modify the value */ + reg_val &= (uint16_t)~mask; + reg_val |= val; + + /* Write the data to register */ + stat = wm8960_write_reg(control, reg, reg_val); + if (stat != status_success) { + return status_fail; + } + + return status_success; +} diff --git a/bsp/hpmicro/hpm6800evk/board/hpm_wm8960.h b/bsp/hpmicro/hpm6800evk/board/hpm_wm8960.h new file mode 100644 index 00000000000..a288b08db97 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/board/hpm_wm8960.h @@ -0,0 +1,227 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_WM8960_H_ +#define _HPM_WM8960_H_ + +//#include "hpm_i2c_drv.h" +//#include "hpm_common.h" +#include +#include +#include "rtt_board.h" +#include "drivers/i2c.h" +#include "hpm_wm8960_regs.h" + +#define WM8960_I2C_ADDR 0x1A + +typedef enum wm8960_module { + wm8960_module_adc = 0, /* ADC module in WM8960 */ + wm8960_module_dac = 1, /* DAC module in WM8960 */ + wm8960_module_vref = 2, /* VREF module */ + wm8960_module_headphone = 3, /* Headphone */ + wm8960_module_micbais = 4, /* Mic bias */ + wm8960_module_ana_in = 6, /* Analog in PGA */ + wm8960_module_lineout = 7, /* Line out module */ + wm8960_module_speaker = 8, /* Speaker module */ + wm8960_module_output_mixer = 9, /* Output mixer */ +} wm8960_module_t; + +/* wm8960 play source for output mixer */ +typedef enum wm8960_play_source { + wm8960_play_source_input_mixer = 1, /* Input Boost Mixer to Output Mixer */ + wm8960_play_source_input3 = 2, /* L/RINPUT3 to Output Mixer */ + wm8960_play_source_dac = 4, /* DAC to Output Mixer */ +} wm8960_play_source_t; + +/* WM8960 data route */ +typedef enum wm8960_route { + wm8960_route_bypass = 0, /* ANA_IN->Headphone. */ + wm8960_route_playback = 1, /* I2SIN->DAC->Headphone. */ + wm8960_route_playback_and_record = 2, /* I2SIN->DAC->Headphone, ANA_IN->ADC->I2SOUT. */ + wm8960_route_record = 5 /* ANA_IN->ADC->I2SOUT. */ +} wm8960_route_t; + +/* The audio data transfer protocol choice */ +typedef enum wm8960_protocol { + wm8960_bus_i2s = 2, /* I2S type */ + wm8960_bus_left_justified = 1, /* Left justified mode */ + wm8960_bus_right_justified = 0, /* Right justified mode */ + wm8960_bus_pcma = 3, /* PCM A mode */ + wm8960_bus_pcmb = 3 | (1 << 4) /* PCM B mode */ +} wm8960_protocol_t; + +/* wm8960 input source */ +typedef enum wm8960_input { + wm8960_input_closed = 0, /* Input device is closed */ + wm8960_input_single_ended_mic = 1, /* Input as single ended mic, only use L/RINPUT1 */ + wm8960_input_differential_mic_input2 = 2, /* Input as differential mic, use L/RINPUT1 and L/RINPUT2 */ + wm8960_input_differential_mic_input3 = 3, /* Input as differential mic, use L/RINPUT1 and L/RINPUT3*/ + wm8960_input_line_input2 = 4, /* Input as line input, only use L/RINPUT2 */ + wm8960_input_line_input3 = 5 /* Input as line input, only use L/RINPUT3 */ +} wm8960_input_t; + +/* wm8960 audio format */ +typedef struct wm8960_audio_format { + uint32_t mclk_hz; /* master clock frequency */ + uint32_t sample_rate; /* sample rate */ + uint32_t bit_width; /* bit width */ +} wm8960_audio_format_t; + +/* configure structure of WM8960 */ +typedef struct wm8960_config { + wm8960_route_t route; /* Audio data route.*/ + wm8960_protocol_t bus; /* Audio transfer protocol */ + bool enable_speaker; /* True means enable class D speaker as output, false means no */ + wm8960_input_t left_input; /* Left input source for WM8960 */ + wm8960_input_t right_input; /* Right input source for wm8960 */ + wm8960_play_source_t play_source; /* play source */ + wm8960_audio_format_t format; /* Audio format */ +} wm8960_config_t; + +typedef struct { + struct rt_i2c_bus_device *i2c_bus; /* I2C bus device */ + uint8_t slave_address; /* code device address */ +} wm8960_control_t; + + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * @brief WM8960 initialize function. + * + * @param control WM8960 control structure. + * @param config WM8960 configuration structure. + */ +hpm_stat_t wm8960_init(wm8960_control_t *control, wm8960_config_t *config); + +/** + * @brief Deinit the WM8960 codec. + * + * This function close all modules in WM8960 to save power. + * + * @param control WM8960 control structure pointer. + */ +hpm_stat_t wm8960_deinit(wm8960_control_t *control); + +/** + * @brief Set audio data route in WM8960. + * + * This function would set the data route according to route. + * + * @param control WM8960 control structure. + * @param config Audio configure structure in WM8960. + */ +hpm_stat_t wm8960_set_data_route(wm8960_control_t *control, wm8960_config_t *config); + +/** + * @brief Set left audio input source in WM8960. + * + * @param control WM8960 control structure. + * @param input Audio input source. + */ +hpm_stat_t wm8960_set_left_input(wm8960_control_t *control, wm8960_input_t input); + +/** + * @brief Set right audio input source in WM8960. + * + * @param control WM8960 control structure. + * @param input Audio input source. + */ +hpm_stat_t wm8960_set_right_input(wm8960_control_t *control, wm8960_input_t input); + +/** + * @brief Set the audio transfer protocol. + * + * @param control WM8960 control structure. + * @param protocol Audio data transfer protocol. + */ +hpm_stat_t wm8960_set_protocol(wm8960_control_t *control, wm8960_protocol_t protocol); + +/** + * @brief Set the volume of different modules in WM8960. + * + * This function would set the volume of WM8960 modules. Uses need to appoint the module. + * The function assume that left channel and right channel has the same volume. + * + * Module:wm8960_module_adc, volume range value: 0 is mute, 1-255 is -97db to 30db + * Module:wm8960_module_dac, volume range value: 0 is mute, 1-255 is -127db to 0db + * Module:wm8960_module_headphone, volume range value: 0 - 2F is mute, 0x30 - 0x7F is -73db to 6db + * Module:wm8960_module_ana_in, volume range value: 0 - 0x3F is -17.25db to 30db + * Module:wm8960_module_speaker, volume range value: 0 - 2F is mute, 0x30 - 0x7F is -73db to 6db + * + * + * @param control WM8960 control structure. + * @param module Module to set volume, it can be ADC, DAC, Headphone and so on. + * @param volume Volume value need to be set. + */ +hpm_stat_t wm8960_set_volume(wm8960_control_t *control, wm8960_module_t module, uint32_t volume); + +/** + * @brief Enable/disable expected module. + * + * @param control WM8960 control structure. + * @param module Module expected to enable. + * @param enable Enable or disable moudles. + */ +hpm_stat_t wm8960_set_module(wm8960_control_t *control, wm8960_module_t module, bool enable); + +/** + * @brief SET the WM8960 play source. + * + * @param control WM8960 control structure. + * @param play_source play source + * + * @return kStatus_WM8904_Success if successful, different code otherwise.. + */ +hpm_stat_t wm8960_config_input_to_output_mixer(wm8960_control_t *control, uint32_t play_source); + +/** + * @brief Configure the data format of audio data. + * + * This function would configure the registers about the sample rate, bit depths. + * + * @param control WM8960 control structure pointer. + * @param sysclk system clock of the codec which can be generated by MCLK or PLL output. + * @param sample_rate Sample rate of audio file running in WM8960. WM8960 now + * supports 8k, 11.025k, 12k, 16k, 22.05k, 24k, 32k, 44.1k, 48k and 96k sample rate. + * @param bits Bit depth of audio file (WM8960 only supports 16bit, 20bit, 24bit + * and 32 bit in HW). + */ +hpm_stat_t wm8960_set_data_format(wm8960_control_t *control, uint32_t sysclk, uint32_t sample_rate, uint32_t bits); + + +/** + * @brief Write register to WM8960 using I2C. + * + * @param control WM8960 control structure. + * @param reg The register address in WM8960. + * @param val Value needs to write into the register. + */ +hpm_stat_t wm8960_write_reg(wm8960_control_t *control, uint8_t reg, uint16_t val); + +/** + * @brief Read register from WM8960 using I2C. + * @param reg The register address in WM8960. + * @param val Value written to. + */ +hpm_stat_t wm8960_read_reg(uint8_t reg, uint16_t *val); + +/** + * @brief Modify some bits in the register using I2C. + * @param control WM8960 control structure. + * @param reg The register address in WM8960. + * @param mask The mask code for the bits want to write. The bit you want to write should be 0. + * @param val Value needs to write into the register. + */ +hpm_stat_t wm8960_modify_reg(wm8960_control_t *control, uint8_t reg, uint16_t mask, uint16_t val); + + +#endif /* _HPM_WM8960_H_ */ diff --git a/bsp/hpmicro/hpm6800evk/board/hpm_wm8960_regs.h b/bsp/hpmicro/hpm6800evk/board/hpm_wm8960_regs.h new file mode 100644 index 00000000000..a484f2937c1 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/board/hpm_wm8960_regs.h @@ -0,0 +1,2139 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_WM8960_REG_H_ +#define _HPM_WM8960_REG_H_ + +/* WM8960 register number */ +#define WM8960_REG_NUM 56U + +/* Define the register address of WM8960 */ +#define WM8960_LINVOL 0x0U /* Left Input Volume */ +#define WM8960_RINVOL 0x1U /* Right Input Volume */ +#define WM8960_LOUT1 0x2U /* LOUT1 Volume */ +#define WM8960_ROUT1 0x3U /* ROUT1 Volume */ +#define WM8960_CLOCK1 0x4U /* Clocking(1) */ +#define WM8960_DACCTL1 0x5U /* ADC and DAC Control (1) */ +#define WM8960_DACCTL2 0x6U /* ADC and DAC Control (2) */ +#define WM8960_IFACE1 0x7U /* Audio Interface */ +#define WM8960_CLOCK2 0x8U /* Clocking(2) */ +#define WM8960_IFACE2 0x9U /* Audio Interface */ +#define WM8960_LDAC 0xaU /* Left DAC */ +#define WM8960_RDAC 0xbU /* Right DAC Volume */ +#define WM8960_RESET 0xfU /* RESET */ +#define WM8960_3D 0x10U /* 3D Control */ +#define WM8960_ALC1 0x11U /* ALC (1) */ +#define WM8960_ALC2 0x12U /* ALC (2) */ +#define WM8960_ALC3 0x13U /* ALC (3) */ +#define WM8960_NOISEG 0x14U /* Noise Gate */ +#define WM8960_LADC 0x15U /* Left ADC Volume */ +#define WM8960_RADC 0x16U /* Right ADC Volume */ +#define WM8960_ADDCTL1 0x17U /* Additional Control (1) */ +#define WM8960_ADDCTL2 0x18U /* Additional Control (2) */ +#define WM8960_POWER1 0x19U /* Power Mgmt (1) */ +#define WM8960_POWER2 0x1aU /* Power Mgmt (2) */ +#define WM8960_ADDCTL3 0x1bU /* Additional Control (3) */ +#define WM8960_APOP1 0x1cU /* Anti-Pop 1 */ +#define WM8960_APOP2 0x1dU /* Anti-pop 2 */ +#define WM8960_LINPATH 0x20U /* ADCL Signal Path */ +#define WM8960_RINPATH 0x21U /* ADCR Signal Path */ +#define WM8960_LOUTMIX 0x22U /* Left Out Mix */ +#define WM8960_ROUTMIX 0x25U /* Right Out Mix */ +#define WM8960_MONOMIX1 0x26U /* Mono Out Mix (1) */ +#define WM8960_MONOMIX2 0x27U /* Mono Out Mix (2) */ +#define WM8960_LOUT2 0x28U /* Left Speaker Volume */ +#define WM8960_ROUT2 0x29U /* Right Speaker Volume */ +#define WM8960_MONO 0x2aU /* OUT3 Volume */ +#define WM8960_INBMIX1 0x2bU /* Left Input Boost Mixer */ +#define WM8960_INBMIX2 0x2cU /* Right Input Boost Mixer */ +#define WM8960_BYPASS1 0x2dU /* Left Bypass */ +#define WM8960_BYPASS2 0x2eU /* Right Bypass */ +#define WM8960_POWER3 0x2fU /* Power Mgmt (3) */ +#define WM8960_ADDCTL4 0x30U /* Additional Control (4) */ +#define WM8960_CLASSD1 0x31U /* Class D Control (1) */ +#define WM8960_CLASSD3 0x33U /* Class D Control (2) */ +#define WM8960_PLL1 0x34U /* PLL (1) */ +#define WM8960_PLL2 0x35U /* PLL (2) */ +#define WM8960_PLL3 0x36U /* PLL (3) */ +#define WM8960_PLL4 0x37U /* PLL (4) */ + +/* Bitfield definition for register: LINVO */ +/* + * IPVU (RW) + * + * Input PGA Volume Update + * Writing a 1 to this bit will cause left and right input PGA volumes to be updated (LINVOL and RINVOL) + */ +#define WM8960_LINVO_IPVU_MASK (0x100U) +#define WM8960_LINVO_IPVU_SHIFT (8U) +#define WM8960_LINVO_IPVU_SET(x) (((uint16_t)(x) << WM8960_LINVO_IPVU_SHIFT) & WM8960_LINVO_IPVU_MASK) +#define WM8960_LINVO_IPVU_GET(x) (((uint16_t)(x) & WM8960_LINVO_IPVU_MASK) >> WM8960_LINVO_IPVU_SHIFT) + +/* + * LINMUTE (RW) + * + * Left Input PGA Analogue Mute 1 = Enable Mute 0 = Disable Mute Note: IPVU must be set to un-mute. + */ +#define WM8960_LINVO_LINMUTE_MASK (0x80U) +#define WM8960_LINVO_LINMUTE_SHIFT (7U) +#define WM8960_LINVO_LINMUTE_SET(x) (((uint16_t)(x) << WM8960_LINVO_LINMUTE_SHIFT) & WM8960_LINVO_LINMUTE_MASK) +#define WM8960_LINVO_LINMUTE_GET(x) (((uint16_t)(x) & WM8960_LINVO_LINMUTE_MASK) >> WM8960_LINVO_LINMUTE_SHIFT) + +/* + * LIZC (RW) + * + * Left Input PGA Zero Cross Detector 1 = Change gain on zero cross only 0 = Change gain immediately + */ +#define WM8960_LINVO_LIZC_MASK (0x40U) +#define WM8960_LINVO_LIZC_SHIFT (6U) +#define WM8960_LINVO_LIZC_SET(x) (((uint16_t)(x) << WM8960_LINVO_LIZC_SHIFT) & WM8960_LINVO_LIZC_MASK) +#define WM8960_LINVO_LIZC_GET(x) (((uint16_t)(x) & WM8960_LINVO_LIZC_MASK) >> WM8960_LINVO_LIZC_SHIFT) + +/* + * LINVOL (RW) + * + * Left Input PGA Volume Control + * 111111 = +30dB + * 111110 = +29.25dB + * . . 0.75dB steps down to + * 000000 = -17.25dB + */ +#define WM8960_LINVO_LINVOL_MASK (0x3FU) +#define WM8960_LINVO_LINVOL_SHIFT (0U) +#define WM8960_LINVO_LINVOL_SET(x) (((uint16_t)(x) << WM8960_LINVO_LINVOL_SHIFT) & WM8960_LINVO_LINVOL_MASK) +#define WM8960_LINVO_LINVOL_GET(x) (((uint16_t)(x) & WM8960_LINVO_LINVOL_MASK) >> WM8960_LINVO_LINVOL_SHIFT) + +/* Bitfield definition for register: RINVOL */ +/* + * IPVU (RW) + * + * Input PGA Volume Update + * Writing a 1 to this bit will cause left and right + * input PGA volumes to be updated (LINVOL and RINVOL) + */ +#define WM8960_RINVOL_IPVU_MASK (0x100U) +#define WM8960_RINVOL_IPVU_SHIFT (8U) +#define WM8960_RINVOL_IPVU_SET(x) (((uint16_t)(x) << WM8960_RINVOL_IPVU_SHIFT) & WM8960_RINVOL_IPVU_MASK) +#define WM8960_RINVOL_IPVU_GET(x) (((uint16_t)(x) & WM8960_RINVOL_IPVU_MASK) >> WM8960_RINVOL_IPVU_SHIFT) + +/* + * RINMUTE (RW) + * + * Right Input PGA Analogue Mute + * 1 = Enable Mute + * 0 = Disable Mute + * Note: IPVU must be set to un-mute. + */ +#define WM8960_RINVOL_RINMUTE_MASK (0x80U) +#define WM8960_RINVOL_RINMUTE_SHIFT (7U) +#define WM8960_RINVOL_RINMUTE_SET(x) (((uint16_t)(x) << WM8960_RINVOL_RINMUTE_SHIFT) & WM8960_RINVOL_RINMUTE_MASK) +#define WM8960_RINVOL_RINMUTE_GET(x) (((uint16_t)(x) & WM8960_RINVOL_RINMUTE_MASK) >> WM8960_RINVOL_RINMUTE_SHIFT) + +/* + * RIZC (RW) + * + * Right Input PGA Zero Cross Detector + * 1 = Change gain on zero cross only + * 0 = Change gain immediately + */ +#define WM8960_RINVOL_RIZC_MASK (0x40U) +#define WM8960_RINVOL_RIZC_SHIFT (6U) +#define WM8960_RINVOL_RIZC_SET(x) (((uint16_t)(x) << WM8960_RINVOL_RIZC_SHIFT) & WM8960_RINVOL_RIZC_MASK) +#define WM8960_RINVOL_RIZC_GET(x) (((uint16_t)(x) & WM8960_RINVOL_RIZC_MASK) >> WM8960_RINVOL_RIZC_SHIFT) + +/* + * RINVOL (RW) + * + * Right Input PGA Volume Control + * 111111 = +30dB + * 111110 = +29.25dB + * . . 0.75dB steps down to + * 000000 = -17.25dB + */ +#define WM8960_RINVOL_RINVOL_MASK (0x3FU) +#define WM8960_RINVOL_RINVOL_SHIFT (0U) +#define WM8960_RINVOL_RINVOL_SET(x) (((uint16_t)(x) << WM8960_RINVOL_RINVOL_SHIFT) & WM8960_RINVOL_RINVOL_MASK) +#define WM8960_RINVOL_RINVOL_GET(x) (((uint16_t)(x) & WM8960_RINVOL_RINVOL_MASK) >> WM8960_RINVOL_RINVOL_SHIFT) + +/* Bitfield definition for register: LOUT1 */ +/* + * OUT1VU (RW) + * + * Headphone Output PGA Volume Update + * Writing a 1 to this bit will cause left and right + * headphone output volumes to be updated + * (LOUT1VOL and ROUT1VOL) + */ +#define WM8960_LOUT1_OUT1VU_MASK (0x100U) +#define WM8960_LOUT1_OUT1VU_SHIFT (8U) +#define WM8960_LOUT1_OUT1VU_SET(x) (((uint16_t)(x) << WM8960_LOUT1_OUT1VU_SHIFT) & WM8960_LOUT1_OUT1VU_MASK) +#define WM8960_LOUT1_OUT1VU_GET(x) (((uint16_t)(x) & WM8960_LOUT1_OUT1VU_MASK) >> WM8960_LOUT1_OUT1VU_SHIFT) + +/* + * LO1ZC (RW) + * + * Left Headphone Output Zero Cross Enable + * 0 = Change gain immediately + * 1 = Change gain on zero cross only + */ +#define WM8960_LOUT1_LO1ZC_MASK (0x80U) +#define WM8960_LOUT1_LO1ZC_SHIFT (7U) +#define WM8960_LOUT1_LO1ZC_SET(x) (((uint16_t)(x) << WM8960_LOUT1_LO1ZC_SHIFT) & WM8960_LOUT1_LO1ZC_MASK) +#define WM8960_LOUT1_LO1ZC_GET(x) (((uint16_t)(x) & WM8960_LOUT1_LO1ZC_MASK) >> WM8960_LOUT1_LO1ZC_SHIFT) + +/* + * LOUT1VOL (RW) + * + * LOUT1 Volume + * 1111111 = +6dB + * … 1dB steps down to + * 0110000 = -73dB + * 0101111 to 0000000 = Analogue MUTE + */ +#define WM8960_LOUT1_LOUT1VOL_MASK (0x7FU) +#define WM8960_LOUT1_LOUT1VOL_SHIFT (0U) +#define WM8960_LOUT1_LOUT1VOL_SET(x) (((uint16_t)(x) << WM8960_LOUT1_LOUT1VOL_SHIFT) & WM8960_LOUT1_LOUT1VOL_MASK) +#define WM8960_LOUT1_LOUT1VOL_GET(x) (((uint16_t)(x) & WM8960_LOUT1_LOUT1VOL_MASK) >> WM8960_LOUT1_LOUT1VOL_SHIFT) + +/* Bitfield definition for register: ROUT1 */ +/* + * OUT1VU (RW) + * + * Headphone Output PGA Volume Update + * Writing a 1 to this bit will cause left and right + * headphone output volumes to be updated + * (LOUT1VOL and ROUT1VOL) + */ +#define WM8960_ROUT1_OUT1VU_MASK (0x100U) +#define WM8960_ROUT1_OUT1VU_SHIFT (8U) +#define WM8960_ROUT1_OUT1VU_SET(x) (((uint16_t)(x) << WM8960_ROUT1_OUT1VU_SHIFT) & WM8960_ROUT1_OUT1VU_MASK) +#define WM8960_ROUT1_OUT1VU_GET(x) (((uint16_t)(x) & WM8960_ROUT1_OUT1VU_MASK) >> WM8960_ROUT1_OUT1VU_SHIFT) + +/* + * RO1ZC (RW) + * + * Right Headphone Output Zero Cross Enable + * 0 = Change gain immediately + * 1 = Change gain on zero cross only + */ +#define WM8960_ROUT1_RO1ZC_MASK (0x80U) +#define WM8960_ROUT1_RO1ZC_SHIFT (7U) +#define WM8960_ROUT1_RO1ZC_SET(x) (((uint16_t)(x) << WM8960_ROUT1_RO1ZC_SHIFT) & WM8960_ROUT1_RO1ZC_MASK) +#define WM8960_ROUT1_RO1ZC_GET(x) (((uint16_t)(x) & WM8960_ROUT1_RO1ZC_MASK) >> WM8960_ROUT1_RO1ZC_SHIFT) + +/* + * ROUT1VOL (RW) + * + * ROUT1 Volume + * 1111111 = +6dB + * … 1dB steps down to + * 0110000 = -73dB + * 0101111 to 0000000 = Analogue MUTE + */ +#define WM8960_ROUT1_ROUT1VOL_MASK (0x7FU) +#define WM8960_ROUT1_ROUT1VOL_SHIFT (0U) +#define WM8960_ROUT1_ROUT1VOL_SET(x) (((uint16_t)(x) << WM8960_ROUT1_ROUT1VOL_SHIFT) & WM8960_ROUT1_ROUT1VOL_MASK) +#define WM8960_ROUT1_ROUT1VOL_GET(x) (((uint16_t)(x) & WM8960_ROUT1_ROUT1VOL_MASK) >> WM8960_ROUT1_ROUT1VOL_SHIFT) + +/* Bitfield definition for register: CLOCK1 */ +/* + * ADCDIV (RW) + * + * ADC Sample rate divider (Also determines + * ADCLRC in master mode) + * 000 = SYSCLK / (1.0 * 256) + * 001 = SYSCLK / (1.5 * 256) + * 010 = SYSCLK / (2 * 256) + * 011 = SYSCLK / (3 * 256) + * 100 = SYSCLK / (4 * 256) + * 101 = SYSCLK / (5.5 * 256) + * 110 = SYSCLK / (6 * 256) + * 111 = Reserved + */ +#define WM8960_CLOCK1_ADCDIV_MASK (0x1C0U) +#define WM8960_CLOCK1_ADCDIV_SHIFT (6U) +#define WM8960_CLOCK1_ADCDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK1_ADCDIV_SHIFT) & WM8960_CLOCK1_ADCDIV_MASK) +#define WM8960_CLOCK1_ADCDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK1_ADCDIV_MASK) >> WM8960_CLOCK1_ADCDIV_SHIFT) + +/* + * DACDIV (RW) + * + * DAC Sample rate divider (Also determines + * DACLRC in master mode) + * 000 = SYSCLK / (1.0 * 256) + * 001 = SYSCLK / (1.5 * 256) + * 010 = SYSCLK / (2 * 256) + * 011 = SYSCLK / (3 * 256) + * 100 = SYSCLK / (4 * 256) + * 101 = SYSCLK / (5.5 * 256) + * 110 = SYSCLK / (6 * 256) + * 111 = Reserved + */ +#define WM8960_CLOCK1_DACDIV_MASK (0x38U) +#define WM8960_CLOCK1_DACDIV_SHIFT (3U) +#define WM8960_CLOCK1_DACDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK1_DACDIV_SHIFT) & WM8960_CLOCK1_DACDIV_MASK) +#define WM8960_CLOCK1_DACDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK1_DACDIV_MASK) >> WM8960_CLOCK1_DACDIV_SHIFT) + +/* + * SYSCLKDIV (RW) + * + * SYSCLK Pre-divider. Clock source (MCLK or + * PLL output) will be divided by this value to + * generate SYSCLK. + * 00 = Divide SYSCLK by 1 + * 01 = Reserved + * 10 = Divide SYSCLK by 2 + * 11 = Reserved + */ +#define WM8960_CLOCK1_SYSCLKDIV_MASK (0x6U) +#define WM8960_CLOCK1_SYSCLKDIV_SHIFT (1U) +#define WM8960_CLOCK1_SYSCLKDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK1_SYSCLKDIV_SHIFT) & WM8960_CLOCK1_SYSCLKDIV_MASK) +#define WM8960_CLOCK1_SYSCLKDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK1_SYSCLKDIV_MASK) >> WM8960_CLOCK1_SYSCLKDIV_SHIFT) + +/* + * CLKSEL (RW) + * + * SYSCLK Selection + * 0 = SYSCLK derived from MCLK + * 1 = SYSCLK derived from PLL output + */ +#define WM8960_CLOCK1_CLKSEL_MASK (0x1U) +#define WM8960_CLOCK1_CLKSEL_SHIFT (0U) +#define WM8960_CLOCK1_CLKSEL_SET(x) (((uint16_t)(x) << WM8960_CLOCK1_CLKSEL_SHIFT) & WM8960_CLOCK1_CLKSEL_MASK) +#define WM8960_CLOCK1_CLKSEL_GET(x) (((uint16_t)(x) & WM8960_CLOCK1_CLKSEL_MASK) >> WM8960_CLOCK1_CLKSEL_SHIFT) + +/* Bitfield definition for register: DACCTL1 */ +/* + * DACDIV2 (RW) + * + * DAC 6dB Attenuate Enable + * 0 = Disabled (0dB) + * 1 = -6dB Enabled + */ +#define WM8960_DACCTL1_DACDIV2_MASK (0x80U) +#define WM8960_DACCTL1_DACDIV2_SHIFT (7U) +#define WM8960_DACCTL1_DACDIV2_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_DACDIV2_SHIFT) & WM8960_DACCTL1_DACDIV2_MASK) +#define WM8960_DACCTL1_DACDIV2_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_DACDIV2_MASK) >> WM8960_DACCTL1_DACDIV2_SHIFT) + +/* + * ADCPOL (RW) + * + * ADC polarity control: + * 00 = Polarity not inverted + * 01 = ADC L inverted + * 10 = ADC R inverted + * 11 = ADC L and R inverted + */ +#define WM8960_DACCTL1_ADCPOL_MASK (0x60U) +#define WM8960_DACCTL1_ADCPOL_SHIFT (5U) +#define WM8960_DACCTL1_ADCPOL_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_ADCPOL_SHIFT) & WM8960_DACCTL1_ADCPOL_MASK) +#define WM8960_DACCTL1_ADCPOL_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_ADCPOL_MASK) >> WM8960_DACCTL1_ADCPOL_SHIFT) + +/* + * DACMU (RW) + * + * DAC Digital Soft Mute + * 1 = Mute + * 0 = No mute (signal active) + */ +#define WM8960_DACCTL1_DACMU_MASK (0x8U) +#define WM8960_DACCTL1_DACMU_SHIFT (3U) +#define WM8960_DACCTL1_DACMU_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_DACMU_SHIFT) & WM8960_DACCTL1_DACMU_MASK) +#define WM8960_DACCTL1_DACMU_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_DACMU_MASK) >> WM8960_DACCTL1_DACMU_SHIFT) + +/* + * DEEMPH (RW) + * + * De-emphasis Control + * 11 = 48kHz sample rate + * 10 = 44.1kHz sample rate + * 01 = 32kHz sample rate + * 00 = No de-emphasis + */ +#define WM8960_DACCTL1_DEEMPH_MASK (0x6U) +#define WM8960_DACCTL1_DEEMPH_SHIFT (1U) +#define WM8960_DACCTL1_DEEMPH_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_DEEMPH_SHIFT) & WM8960_DACCTL1_DEEMPH_MASK) +#define WM8960_DACCTL1_DEEMPH_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_DEEMPH_MASK) >> WM8960_DACCTL1_DEEMPH_SHIFT) + +/* + * ADCHPD (RW) + * + * ADC High Pass Filter Disable + * 0 = Enable high pass filter on left and right channels + * 1 = Disable high pass filter on left and right channels + */ +#define WM8960_DACCTL1_ADCHPD_MASK (0x1U) +#define WM8960_DACCTL1_ADCHPD_SHIFT (0U) +#define WM8960_DACCTL1_ADCHPD_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_ADCHPD_SHIFT) & WM8960_DACCTL1_ADCHPD_MASK) +#define WM8960_DACCTL1_ADCHPD_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_ADCHPD_MASK) >> WM8960_DACCTL1_ADCHPD_SHIFT) + +/* Bitfield definition for register: DACCTL2 */ +/* + * DACPOL (RW) + * + * DAC polarity control: + * 00 = Polarity not inverted + * 01 = DAC L inverted + * 10 = DAC R inverted + * 11 = DAC L and R inverted + */ +#define WM8960_DACCTL2_DACPOL_MASK (0x60U) +#define WM8960_DACCTL2_DACPOL_SHIFT (5U) +#define WM8960_DACCTL2_DACPOL_SET(x) (((uint16_t)(x) << WM8960_DACCTL2_DACPOL_SHIFT) & WM8960_DACCTL2_DACPOL_MASK) +#define WM8960_DACCTL2_DACPOL_GET(x) (((uint16_t)(x) & WM8960_DACCTL2_DACPOL_MASK) >> WM8960_DACCTL2_DACPOL_SHIFT) + +/* + * DACSMM (RW) + * + * DAC Soft Mute Mode + * 0 = Disabling soft-mute (DACMU=0) will cause + * the volume to change immediately to the + * LDACVOL / RDACVOL settings + * 1 = Disabling soft-mute (DACMU=0) will cause + * the volume to ramp up gradually to the + * LDACVOL / RDACVOL settings + */ +#define WM8960_DACCTL2_DACSMM_MASK (0x8U) +#define WM8960_DACCTL2_DACSMM_SHIFT (3U) +#define WM8960_DACCTL2_DACSMM_SET(x) (((uint16_t)(x) << WM8960_DACCTL2_DACSMM_SHIFT) & WM8960_DACCTL2_DACSMM_MASK) +#define WM8960_DACCTL2_DACSMM_GET(x) (((uint16_t)(x) & WM8960_DACCTL2_DACSMM_MASK) >> WM8960_DACCTL2_DACSMM_SHIFT) + +/* + * DACMR (RW) + * + * DAC Soft Mute Ramp Rate + * 0 = Fast ramp (24kHz at fs=48k, providing + * maximum delay of 10.7ms) + * 1 = Slow ramp (1.5kHz at fs=48k, providing + * maximum delay of 171ms) + */ +#define WM8960_DACCTL2_DACMR_MASK (0x4U) +#define WM8960_DACCTL2_DACMR_SHIFT (2U) +#define WM8960_DACCTL2_DACMR_SET(x) (((uint16_t)(x) << WM8960_DACCTL2_DACMR_SHIFT) & WM8960_DACCTL2_DACMR_MASK) +#define WM8960_DACCTL2_DACMR_GET(x) (((uint16_t)(x) & WM8960_DACCTL2_DACMR_MASK) >> WM8960_DACCTL2_DACMR_SHIFT) + +/* + * DACSLOPE (RW) + * + * Selects DAC filter characteristics + * 0 = Normal mode + * 1 = Sloping stopband + */ +#define WM8960_DACCTL2_DACSLOPE_MASK (0x2U) +#define WM8960_DACCTL2_DACSLOPE_SHIFT (1U) +#define WM8960_DACCTL2_DACSLOPE_SET(x) (((uint16_t)(x) << WM8960_DACCTL2_DACSLOPE_SHIFT) & WM8960_DACCTL2_DACSLOPE_MASK) +#define WM8960_DACCTL2_DACSLOPE_GET(x) (((uint16_t)(x) & WM8960_DACCTL2_DACSLOPE_MASK) >> WM8960_DACCTL2_DACSLOPE_SHIFT) + +/* Bitfield definition for register: IFACE1 */ +/* + * ALRSWAP (RW) + * + * Left/Right ADC Channel Swap + * 1 = Swap left and right ADC data in audio + * interface + * 0 = Output left and right data as normal + */ +#define WM8960_IFACE1_ALRSWAP_MASK (0x100U) +#define WM8960_IFACE1_ALRSWAP_SHIFT (8U) +#define WM8960_IFACE1_ALRSWAP_SET(x) (((uint16_t)(x) << WM8960_IFACE1_ALRSWAP_SHIFT) & WM8960_IFACE1_ALRSWAP_MASK) +#define WM8960_IFACE1_ALRSWAP_GET(x) (((uint16_t)(x) & WM8960_IFACE1_ALRSWAP_MASK) >> WM8960_IFACE1_ALRSWAP_SHIFT) + +/* + * BCLKINV (RW) + * + * BCLK invert bit (for master and slave modes) + * 0 = BCLK not inverted + * 1 = BCLK inverted + */ +#define WM8960_IFACE1_BCLKINV_MASK (0x80U) +#define WM8960_IFACE1_BCLKINV_SHIFT (7U) +#define WM8960_IFACE1_BCLKINV_SET(x) (((uint16_t)(x) << WM8960_IFACE1_BCLKINV_SHIFT) & WM8960_IFACE1_BCLKINV_MASK) +#define WM8960_IFACE1_BCLKINV_GET(x) (((uint16_t)(x) & WM8960_IFACE1_BCLKINV_MASK) >> WM8960_IFACE1_BCLKINV_SHIFT) + +/* + * MS (RW) + * + * Master / Slave Mode Control + * 0 = Enable slave mode + * 1 = Enable master mode + */ +#define WM8960_IFACE1_MS_MASK (0x40U) +#define WM8960_IFACE1_MS_SHIFT (6U) +#define WM8960_IFACE1_MS_SET(x) (((uint16_t)(x) << WM8960_IFACE1_MS_SHIFT) & WM8960_IFACE1_MS_MASK) +#define WM8960_IFACE1_MS_GET(x) (((uint16_t)(x) & WM8960_IFACE1_MS_MASK) >> WM8960_IFACE1_MS_SHIFT) + +/* + * DLRSWAP (RW) + * + * Left/Right DAC Channel Swap + * 0 = Output left and right data as normal + * 1 = Swap left and right DAC data in audio interface + */ +#define WM8960_IFACE1_DLRSWAP_MASK (0x20U) +#define WM8960_IFACE1_DLRSWAP_SHIFT (5U) +#define WM8960_IFACE1_DLRSWAP_SET(x) (((uint16_t)(x) << WM8960_IFACE1_DLRSWAP_SHIFT) & WM8960_IFACE1_DLRSWAP_MASK) +#define WM8960_IFACE1_DLRSWAP_GET(x) (((uint16_t)(x) & WM8960_IFACE1_DLRSWAP_MASK) >> WM8960_IFACE1_DLRSWAP_SHIFT) + +/* + * LRP (RW) + * + * Right, left and I2S modes – LRCLK polarity + * 0 = normal LRCLK polarity + * 1 = invert LRCLK polarity + * DSP Mode – mode A/B select + * 0 = MSB is available on 2nd BCLK rising edge after LRC rising edge (mode A) + * 1 = MSB is available on 1st BCLK rising edge after LRC rising edge (mode B) + */ +#define WM8960_IFACE1_LRP_MASK (0x10U) +#define WM8960_IFACE1_LRP_SHIFT (4U) +#define WM8960_IFACE1_LRP_SET(x) (((uint16_t)(x) << WM8960_IFACE1_LRP_SHIFT) & WM8960_IFACE1_LRP_MASK) +#define WM8960_IFACE1_LRP_GET(x) (((uint16_t)(x) & WM8960_IFACE1_LRP_MASK) >> WM8960_IFACE1_LRP_SHIFT) + +/* + * WL (RW) + * + * Audio Data Word Length + * 00 = 16 bits + * 01 = 20 bits + * 10 = 24 bits + * 11 = 32 bits (see Note) + */ +#define WM8960_IFACE1_WL_MASK (0xCU) +#define WM8960_IFACE1_WL_SHIFT (2U) +#define WM8960_IFACE1_WL_SET(x) (((uint16_t)(x) << WM8960_IFACE1_WL_SHIFT) & WM8960_IFACE1_WL_MASK) +#define WM8960_IFACE1_WL_GET(x) (((uint16_t)(x) & WM8960_IFACE1_WL_MASK) >> WM8960_IFACE1_WL_SHIFT) + +/* + * FORMAT (RW) + * + * 00 = Right justified + * 01 = Left justified + * 10 = I2S Format + * 11 = DSP Mode + */ +#define WM8960_IFACE1_FORMAT_MASK (0x3U) +#define WM8960_IFACE1_FORMAT_SHIFT (0U) +#define WM8960_IFACE1_FORMAT_SET(x) (((uint16_t)(x) << WM8960_IFACE1_FORMAT_SHIFT) & WM8960_IFACE1_FORMAT_MASK) +#define WM8960_IFACE1_FORMAT_GET(x) (((uint16_t)(x) & WM8960_IFACE1_FORMAT_MASK) >> WM8960_IFACE1_FORMAT_SHIFT) + +/* Bitfield definition for register: CLOCK2 */ +/* + * DCLKDIV (RW) + * + * Class D switching clock divider. + * 000 = SYSCLK / 1.5 (Not recommended) + * 001 = SYSCLK / 2 + * 010 = SYSCLK / 3 + * 011 = SYSCLK / 4 + * 100 = SYSCLK / 6 + * 101 = SYSCLK / 8 + * 110 = SYSCLK / 12 + * 111 = SYSCLK / 16 + */ +#define WM8960_CLOCK2_DCLKDIV_MASK (0x1C0U) +#define WM8960_CLOCK2_DCLKDIV_SHIFT (6U) +#define WM8960_CLOCK2_DCLKDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK2_DCLKDIV_SHIFT) & WM8960_CLOCK2_DCLKDIV_MASK) +#define WM8960_CLOCK2_DCLKDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK2_DCLKDIV_MASK) >> WM8960_CLOCK2_DCLKDIV_SHIFT) + +/* + * BCLKDIV (RW) + * + * BCLK Frequency (Master Mode) + * 0000 = SYSCLK + * 0001 = SYSCLK / 1.5 + * 0010 = SYSCLK / 2 + * 0011 = SYSCLK / 3 + * 0100 = SYSCLK / 4 + * 0101 = SYSCLK / 5.5 + * 0110 = SYSCLK / 6 + * 0111 = SYSCLK / 8 + * 1000 = SYSCLK / 11 + * 1001 = SYSCLK / 12 + * 1010 = SYSCLK / 16 + * 1011 = SYSCLK / 22 + * 1100 = SYSCLK / 24 + * 1101 to 1111 = SYSCLK / 32 + */ +#define WM8960_CLOCK2_BCLKDIV_MASK (0xFU) +#define WM8960_CLOCK2_BCLKDIV_SHIFT (0U) +#define WM8960_CLOCK2_BCLKDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK2_BCLKDIV_SHIFT) & WM8960_CLOCK2_BCLKDIV_MASK) +#define WM8960_CLOCK2_BCLKDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK2_BCLKDIV_MASK) >> WM8960_CLOCK2_BCLKDIV_SHIFT) + +/* Bitfield definition for register: IFACE2 */ +/* + * ALRCGPIO (RW) + * + * ADCLRC/GPIO1 Pin Function Select + * 0 = ADCLRC frame clock for ADC + * 1 = GPIO pin + */ +#define WM8960_IFACE2_ALRCGPIO_MASK (0x40U) +#define WM8960_IFACE2_ALRCGPIO_SHIFT (6U) +#define WM8960_IFACE2_ALRCGPIO_SET(x) (((uint16_t)(x) << WM8960_IFACE2_ALRCGPIO_SHIFT) & WM8960_IFACE2_ALRCGPIO_MASK) +#define WM8960_IFACE2_ALRCGPIO_GET(x) (((uint16_t)(x) & WM8960_IFACE2_ALRCGPIO_MASK) >> WM8960_IFACE2_ALRCGPIO_SHIFT) + +/* + * WL8 (RW) + * + * 8-Bit Word Length Select (Used with + * companding) + * 0 = Off + * 1 = Device operates in 8-bit mode. + */ +#define WM8960_IFACE2_WL8_MASK (0x20U) +#define WM8960_IFACE2_WL8_SHIFT (5U) +#define WM8960_IFACE2_WL8_SET(x) (((uint16_t)(x) << WM8960_IFACE2_WL8_SHIFT) & WM8960_IFACE2_WL8_MASK) +#define WM8960_IFACE2_WL8_GET(x) (((uint16_t)(x) & WM8960_IFACE2_WL8_MASK) >> WM8960_IFACE2_WL8_SHIFT) + +/* + * DACCOMP (RW) + * + * DAC companding + * 00 = off + * 01 = reserved + * 10 = μ-law + * 11 = A-law + */ +#define WM8960_IFACE2_DACCOMP_MASK (0x18U) +#define WM8960_IFACE2_DACCOMP_SHIFT (3U) +#define WM8960_IFACE2_DACCOMP_SET(x) (((uint16_t)(x) << WM8960_IFACE2_DACCOMP_SHIFT) & WM8960_IFACE2_DACCOMP_MASK) +#define WM8960_IFACE2_DACCOMP_GET(x) (((uint16_t)(x) & WM8960_IFACE2_DACCOMP_MASK) >> WM8960_IFACE2_DACCOMP_SHIFT) + +/* + * ADCCOMP (RW) + * + * ADC companding + * 00 = off + * 01 = reserved + * 10 = μ-law + * 11 = A-law + */ +#define WM8960_IFACE2_ADCCOMP_MASK (0x6U) +#define WM8960_IFACE2_ADCCOMP_SHIFT (1U) +#define WM8960_IFACE2_ADCCOMP_SET(x) (((uint16_t)(x) << WM8960_IFACE2_ADCCOMP_SHIFT) & WM8960_IFACE2_ADCCOMP_MASK) +#define WM8960_IFACE2_ADCCOMP_GET(x) (((uint16_t)(x) & WM8960_IFACE2_ADCCOMP_MASK) >> WM8960_IFACE2_ADCCOMP_SHIFT) + +/* + * LOOPBACK (RW) + * + * Digital Loopback Function + * 0 = No loopback. + * 1 = Loopback enabled, ADC data output is fed + * directly into DAC data input + */ +#define WM8960_IFACE2_LOOPBACK_MASK (0x1U) +#define WM8960_IFACE2_LOOPBACK_SHIFT (0U) +#define WM8960_IFACE2_LOOPBACK_SET(x) (((uint16_t)(x) << WM8960_IFACE2_LOOPBACK_SHIFT) & WM8960_IFACE2_LOOPBACK_MASK) +#define WM8960_IFACE2_LOOPBACK_GET(x) (((uint16_t)(x) & WM8960_IFACE2_LOOPBACK_MASK) >> WM8960_IFACE2_LOOPBACK_SHIFT) + +/* Bitfield definition for register: LDAC */ +/* + * DACVU (RW) + * + * DAC Volume Update + * Writing a 1 to this bit will cause left and right + * DAC volumes to be updated (LDACVOL and RDACVOL) + */ +#define WM8960_LDAC_DACVU_MASK (0x100U) +#define WM8960_LDAC_DACVU_SHIFT (8U) +#define WM8960_LDAC_DACVU_SET(x) (((uint16_t)(x) << WM8960_LDAC_DACVU_SHIFT) & WM8960_LDAC_DACVU_MASK) +#define WM8960_LDAC_DACVU_GET(x) (((uint16_t)(x) & WM8960_LDAC_DACVU_MASK) >> WM8960_LDAC_DACVU_SHIFT) + +/* + * LDACVOL (RW) + * + * Left DAC Digital Volume Control + * 0000 0000 = Digital Mute + * 0000 0001 = -127dB + * 0000 0010 = -126.5dB + * ... 0.5dB steps up to + * 1111 1111 = 0dB + */ +#define WM8960_LDAC_LDACVOL_MASK (0xFFU) +#define WM8960_LDAC_LDACVOL_SHIFT (0U) +#define WM8960_LDAC_LDACVOL_SET(x) (((uint16_t)(x) << WM8960_LDAC_LDACVOL_SHIFT) & WM8960_LDAC_LDACVOL_MASK) +#define WM8960_LDAC_LDACVOL_GET(x) (((uint16_t)(x) & WM8960_LDAC_LDACVOL_MASK) >> WM8960_LDAC_LDACVOL_SHIFT) + +/* Bitfield definition for register: RDAC */ +/* + * DACVU (RW) + * + * DAC Volume Update + * Writing a 1 to this bit will cause left and right + * DAC volumes to be updated (LDACVOL and RDACVOL) + */ +#define WM8960_RDAC_DACVU_MASK (0x100U) +#define WM8960_RDAC_DACVU_SHIFT (8U) +#define WM8960_RDAC_DACVU_SET(x) (((uint16_t)(x) << WM8960_RDAC_DACVU_SHIFT) & WM8960_RDAC_DACVU_MASK) +#define WM8960_RDAC_DACVU_GET(x) (((uint16_t)(x) & WM8960_RDAC_DACVU_MASK) >> WM8960_RDAC_DACVU_SHIFT) + +/* + * RDACVOL (RW) + * + * Right DAC Digital Volume Control + * 0000 0000 = Digital Mute + * 0000 0001 = -127dB + * 0000 0010 = -126.5dB + * ... 0.5dB steps up to + * 1111 1111 = 0dB + */ +#define WM8960_RDAC_RDACVOL_MASK (0xFFU) +#define WM8960_RDAC_RDACVOL_SHIFT (0U) +#define WM8960_RDAC_RDACVOL_SET(x) (((uint16_t)(x) << WM8960_RDAC_RDACVOL_SHIFT) & WM8960_RDAC_RDACVOL_MASK) +#define WM8960_RDAC_RDACVOL_GET(x) (((uint16_t)(x) & WM8960_RDAC_RDACVOL_MASK) >> WM8960_RDAC_RDACVOL_SHIFT) + +/* Bitfield definition for register: RESET */ +/* + * RESET (RW) + * + * Writing to this register resets all registers to their default state. + */ +#define WM8960_RESET_RESET_MASK (0x1FFU) +#define WM8960_RESET_RESET_SHIFT (0U) +#define WM8960_RESET_RESET_SET(x) (((uint16_t)(x) << WM8960_RESET_RESET_SHIFT) & WM8960_RESET_RESET_MASK) +#define WM8960_RESET_RESET_GET(x) (((uint16_t)(x) & WM8960_RESET_RESET_MASK) >> WM8960_RESET_RESET_SHIFT) + +/* Bitfield definition for register: 3D */ +/* + * 3DUC (RW) + * + * 3D Enhance Filter Upper Cut-Off Frequency + * 0 = High (Recommended for fs>=32kHz) + * 1 = Low (Recommended for fs<32kHz) + */ +#define WM8960_3D_3DUC_MASK (0x40U) +#define WM8960_3D_3DUC_SHIFT (6U) +#define WM8960_3D_3DUC_SET(x) (((uint16_t)(x) << WM8960_3D_3DUC_SHIFT) & WM8960_3D_3DUC_MASK) +#define WM8960_3D_3DUC_GET(x) (((uint16_t)(x) & WM8960_3D_3DUC_MASK) >> WM8960_3D_3DUC_SHIFT) + +/* + * 3DLC (RW) + * + * 3D Enhance Filter Lower Cut-Off Frequency + * 0 = Low (Recommended for fs>=32kHz) + * 1 = High (Recommended for fs<32kHz) + */ +#define WM8960_3D_3DLC_MASK (0x20U) +#define WM8960_3D_3DLC_SHIFT (5U) +#define WM8960_3D_3DLC_SET(x) (((uint16_t)(x) << WM8960_3D_3DLC_SHIFT) & WM8960_3D_3DLC_MASK) +#define WM8960_3D_3DLC_GET(x) (((uint16_t)(x) & WM8960_3D_3DLC_MASK) >> WM8960_3D_3DLC_SHIFT) + +/* + * 3DDEPTH (RW) + * + * 3D Stereo Depth + * 0000 = 0% (minimum 3D effect) + * 0001 = 6.67% + * .... + * 1110 = 93.3% + * 1111 = 100% (maximum 3D effect) + */ +#define WM8960_3D_3DDEPTH_MASK (0x1EU) +#define WM8960_3D_3DDEPTH_SHIFT (1U) +#define WM8960_3D_3DDEPTH_SET(x) (((uint16_t)(x) << WM8960_3D_3DDEPTH_SHIFT) & WM8960_3D_3DDEPTH_MASK) +#define WM8960_3D_3DDEPTH_GET(x) (((uint16_t)(x) & WM8960_3D_3DDEPTH_MASK) >> WM8960_3D_3DDEPTH_SHIFT) + +/* + * 3DEN (RW) + * + * 3D Stereo Enhancement Enable + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_3D_3DEN_MASK (0x1U) +#define WM8960_3D_3DEN_SHIFT (0U) +#define WM8960_3D_3DEN_SET(x) (((uint16_t)(x) << WM8960_3D_3DEN_SHIFT) & WM8960_3D_3DEN_MASK) +#define WM8960_3D_3DEN_GET(x) (((uint16_t)(x) & WM8960_3D_3DEN_MASK) >> WM8960_3D_3DEN_SHIFT) + +/* Bitfield definition for register: ALC1 */ +/* + * ALCSEL (RW) + * + * ALC Function Select + * 00 = ALC off (PGA gain set by register) + * 01 = Right channel only + * 10 = Left channel only + * 11 = Stereo (PGA registers unused) Note: + * ensure that LINVOL and RINVOL settings + * (reg. 0 and 1) are the same before entering this mode. + */ +#define WM8960_ALC1_ALCSEL_MASK (0x180U) +#define WM8960_ALC1_ALCSEL_SHIFT (7U) +#define WM8960_ALC1_ALCSEL_SET(x) (((uint16_t)(x) << WM8960_ALC1_ALCSEL_SHIFT) & WM8960_ALC1_ALCSEL_MASK) +#define WM8960_ALC1_ALCSEL_GET(x) (((uint16_t)(x) & WM8960_ALC1_ALCSEL_MASK) >> WM8960_ALC1_ALCSEL_SHIFT) + +/* + * MAXGAIN (RW) + * + * Set Maximum Gain of PGA (During ALC + * operation) + * 111 : +30dB + * 110 : +24dB + * ….(-6dB steps) + * 001 : -6dB + * 000 : -12dB + */ +#define WM8960_ALC1_MAXGAIN_MASK (0x70U) +#define WM8960_ALC1_MAXGAIN_SHIFT (4U) +#define WM8960_ALC1_MAXGAIN_SET(x) (((uint16_t)(x) << WM8960_ALC1_MAXGAIN_SHIFT) & WM8960_ALC1_MAXGAIN_MASK) +#define WM8960_ALC1_MAXGAIN_GET(x) (((uint16_t)(x) & WM8960_ALC1_MAXGAIN_MASK) >> WM8960_ALC1_MAXGAIN_SHIFT) + +/* + * ALCL (RW) + * + * ALC Target (Sets signal level at ADC input) + * 0000 = -22.5dB FS + * 0001 = -21.0dB FS + * … (1.5dB steps) + * 1101 = -3.0dB FS + * 1110 = -1.5dB FS + * 1111 = -1.5dB FS + */ +#define WM8960_ALC1_ALCL_MASK (0xFU) +#define WM8960_ALC1_ALCL_SHIFT (0U) +#define WM8960_ALC1_ALCL_SET(x) (((uint16_t)(x) << WM8960_ALC1_ALCL_SHIFT) & WM8960_ALC1_ALCL_MASK) +#define WM8960_ALC1_ALCL_GET(x) (((uint16_t)(x) & WM8960_ALC1_ALCL_MASK) >> WM8960_ALC1_ALCL_SHIFT) + +/* Bitfield definition for register: ALC2 */ +/* + * MINGAIN (RW) + * + * Set Minimum Gain of PGA (During ALC + * operation) + * 000 = -17.25dB + * 001 = -11.25dB + * 010 = -5.25dB + * 011 = +0.75dB + * 100 = +6.75dB + * 101 = +12.75dB + * 110 = +18.75dB + * 111 = +24.75dB + */ +#define WM8960_ALC2_MINGAIN_MASK (0x70U) +#define WM8960_ALC2_MINGAIN_SHIFT (4U) +#define WM8960_ALC2_MINGAIN_SET(x) (((uint16_t)(x) << WM8960_ALC2_MINGAIN_SHIFT) & WM8960_ALC2_MINGAIN_MASK) +#define WM8960_ALC2_MINGAIN_GET(x) (((uint16_t)(x) & WM8960_ALC2_MINGAIN_MASK) >> WM8960_ALC2_MINGAIN_SHIFT) + +/* + * HLD (RW) + * + * ALC hold time before gain is increased. + * 0000 = 0ms + * 0001 = 2.67ms + * 0010 = 5.33ms + * … (time doubles with every step) + * 1111 = 43.691s + */ +#define WM8960_ALC2_HLD_MASK (0xFU) +#define WM8960_ALC2_HLD_SHIFT (0U) +#define WM8960_ALC2_HLD_SET(x) (((uint16_t)(x) << WM8960_ALC2_HLD_SHIFT) & WM8960_ALC2_HLD_MASK) +#define WM8960_ALC2_HLD_GET(x) (((uint16_t)(x) & WM8960_ALC2_HLD_MASK) >> WM8960_ALC2_HLD_SHIFT) + +/* Bitfield definition for register: ALC3 */ +/* + * ALCMODE (RW) + * + * Determines the ALC mode of operation: + * 0 = ALC mode + * 1 = Limiter mode + */ +#define WM8960_ALC3_ALCMODE_MASK (0x100U) +#define WM8960_ALC3_ALCMODE_SHIFT (8U) +#define WM8960_ALC3_ALCMODE_SET(x) (((uint16_t)(x) << WM8960_ALC3_ALCMODE_SHIFT) & WM8960_ALC3_ALCMODE_MASK) +#define WM8960_ALC3_ALCMODE_GET(x) (((uint16_t)(x) & WM8960_ALC3_ALCMODE_MASK) >> WM8960_ALC3_ALCMODE_SHIFT) + +/* + * DCY (RW) + * + * ALC decay (gain ramp-up) time + * 0000 = 24ms + * 0001 = 48ms + * 0010 = 96ms + * … (time doubles with every step) + * 1010 or higher = 24.58s + */ +#define WM8960_ALC3_DCY_MASK (0xF0U) +#define WM8960_ALC3_DCY_SHIFT (4U) +#define WM8960_ALC3_DCY_SET(x) (((uint16_t)(x) << WM8960_ALC3_DCY_SHIFT) & WM8960_ALC3_DCY_MASK) +#define WM8960_ALC3_DCY_GET(x) (((uint16_t)(x) & WM8960_ALC3_DCY_MASK) >> WM8960_ALC3_DCY_SHIFT) + +/* + * ATK (RW) + * + * ALC attack (gain ramp-down) time + * 0000 = 6ms + * 0001 = 12ms + * 0010 = 24ms + * … (time doubles with every step) + * 1010 or higher = 6.14s + */ +#define WM8960_ALC3_ATK_MASK (0xFU) +#define WM8960_ALC3_ATK_SHIFT (0U) +#define WM8960_ALC3_ATK_SET(x) (((uint16_t)(x) << WM8960_ALC3_ATK_SHIFT) & WM8960_ALC3_ATK_MASK) +#define WM8960_ALC3_ATK_GET(x) (((uint16_t)(x) & WM8960_ALC3_ATK_MASK) >> WM8960_ALC3_ATK_SHIFT) + +/* Bitfield definition for register: NOISEG */ +/* + * NGTH (RW) + * + * Noise gate threshold + * 00000 -76.5dBfs + * 00001 -75dBfs + * … 1.5 dB steps + * 11110 -31.5dBfs + * 11111 -30dBfs + */ +#define WM8960_NOISEG_NGTH_MASK (0xF8U) +#define WM8960_NOISEG_NGTH_SHIFT (3U) +#define WM8960_NOISEG_NGTH_SET(x) (((uint16_t)(x) << WM8960_NOISEG_NGTH_SHIFT) & WM8960_NOISEG_NGTH_MASK) +#define WM8960_NOISEG_NGTH_GET(x) (((uint16_t)(x) & WM8960_NOISEG_NGTH_MASK) >> WM8960_NOISEG_NGTH_SHIFT) + +/* + * NGAT (RW) + * + * Noise gate function enable + * 0 = disable + * 1 = enable + */ +#define WM8960_NOISEG_NGAT_MASK (0x1U) +#define WM8960_NOISEG_NGAT_SHIFT (0U) +#define WM8960_NOISEG_NGAT_SET(x) (((uint16_t)(x) << WM8960_NOISEG_NGAT_SHIFT) & WM8960_NOISEG_NGAT_MASK) +#define WM8960_NOISEG_NGAT_GET(x) (((uint16_t)(x) & WM8960_NOISEG_NGAT_MASK) >> WM8960_NOISEG_NGAT_SHIFT) + +/* Bitfield definition for register: LADC */ +/* + * ADCVU (RW) + * + * ADC Volume Update + * Writing a 1 to this bit will cause left and right + * ADC volumes to be updated (LADCVOL and + * RADCVOL) + */ +#define WM8960_LADC_ADCVU_MASK (0x100U) +#define WM8960_LADC_ADCVU_SHIFT (8U) +#define WM8960_LADC_ADCVU_SET(x) (((uint16_t)(x) << WM8960_LADC_ADCVU_SHIFT) & WM8960_LADC_ADCVU_MASK) +#define WM8960_LADC_ADCVU_GET(x) (((uint16_t)(x) & WM8960_LADC_ADCVU_MASK) >> WM8960_LADC_ADCVU_SHIFT) + +/* + * LADCVOL (RW) + * + * Left ADC Digital Volume Control + * 0000 0000 = Digital Mute + * 0000 0001 = -97dB + * 0000 0010 = -96.5dB + * ... 0.5dB steps up to + * 1111 1111 = +30dB + */ +#define WM8960_LADC_LADCVOL_MASK (0xFFU) +#define WM8960_LADC_LADCVOL_SHIFT (0U) +#define WM8960_LADC_LADCVOL_SET(x) (((uint16_t)(x) << WM8960_LADC_LADCVOL_SHIFT) & WM8960_LADC_LADCVOL_MASK) +#define WM8960_LADC_LADCVOL_GET(x) (((uint16_t)(x) & WM8960_LADC_LADCVOL_MASK) >> WM8960_LADC_LADCVOL_SHIFT) + +/* Bitfield definition for register: RADC */ +/* + * ADCVU (RW) + * + * ADC Volume Update + * Writing a 1 to this bit will cause left and right + * ADC volumes to be updated (LADCVOL and RADCVOL) + */ +#define WM8960_RADC_ADCVU_MASK (0x100U) +#define WM8960_RADC_ADCVU_SHIFT (8U) +#define WM8960_RADC_ADCVU_SET(x) (((uint16_t)(x) << WM8960_RADC_ADCVU_SHIFT) & WM8960_RADC_ADCVU_MASK) +#define WM8960_RADC_ADCVU_GET(x) (((uint16_t)(x) & WM8960_RADC_ADCVU_MASK) >> WM8960_RADC_ADCVU_SHIFT) + +/* + * RADCVOL (RW) + * + * Right ADC Digital Volume Control + * 0000 0000 = Digital Mute + * 0000 0001 = -97dB + * 0000 0010 = -96.5dB + * ... 0.5dB steps up to + * 1111 1111 = +30dB + */ +#define WM8960_RADC_RADCVOL_MASK (0xFFU) +#define WM8960_RADC_RADCVOL_SHIFT (0U) +#define WM8960_RADC_RADCVOL_SET(x) (((uint16_t)(x) << WM8960_RADC_RADCVOL_SHIFT) & WM8960_RADC_RADCVOL_MASK) +#define WM8960_RADC_RADCVOL_GET(x) (((uint16_t)(x) & WM8960_RADC_RADCVOL_MASK) >> WM8960_RADC_RADCVOL_SHIFT) + +/* Bitfield definition for register: ADDCTL1 */ +/* + * TSDEN (RW) + * + * Thermal Shutdown Enable + * 0 = Thermal shutdown disabled + * 1 = Thermal shutdown enabled + * (TSENSEN must be enabled for this function to work) + */ +#define WM8960_ADDCTL1_TSDEN_MASK (0x100U) +#define WM8960_ADDCTL1_TSDEN_SHIFT (8U) +#define WM8960_ADDCTL1_TSDEN_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_TSDEN_SHIFT) & WM8960_ADDCTL1_TSDEN_MASK) +#define WM8960_ADDCTL1_TSDEN_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_TSDEN_MASK) >> WM8960_ADDCTL1_TSDEN_SHIFT) + +/* + * VSEL (RW) + * + * Analogue Bias Optimisation + * 00 = Reserved + * 01 = Increased bias current optimized for + * AVDD=2.7V + * 1X = Lowest bias current, optimized for + * AVDD=3.3V + */ +#define WM8960_ADDCTL1_VSEL_MASK (0xC0U) +#define WM8960_ADDCTL1_VSEL_SHIFT (6U) +#define WM8960_ADDCTL1_VSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_VSEL_SHIFT) & WM8960_ADDCTL1_VSEL_MASK) +#define WM8960_ADDCTL1_VSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_VSEL_MASK) >> WM8960_ADDCTL1_VSEL_SHIFT) + +/* + * DMONOMIX (RW) + * + * DAC Mono Mix + * 0 = Stereo + * 1 = Mono (Mono MIX output on enabled DACs + */ +#define WM8960_ADDCTL1_DMONOMIX_MASK (0x10U) +#define WM8960_ADDCTL1_DMONOMIX_SHIFT (4U) +#define WM8960_ADDCTL1_DMONOMIX_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_DMONOMIX_SHIFT) & WM8960_ADDCTL1_DMONOMIX_MASK) +#define WM8960_ADDCTL1_DMONOMIX_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_DMONOMIX_MASK) >> WM8960_ADDCTL1_DMONOMIX_SHIFT) + +/* + * DATSEL (RW) + * + * ADC Data Output Select + * 00: left data = left ADC; right data =right ADC + * 01: left data = left ADC; right data = left ADC + * 10: left data = right ADC; right data =right ADC + * 11: left data = right ADC; right data = left ADC + */ +#define WM8960_ADDCTL1_DATSEL_MASK (0xCU) +#define WM8960_ADDCTL1_DATSEL_SHIFT (2U) +#define WM8960_ADDCTL1_DATSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_DATSEL_SHIFT) & WM8960_ADDCTL1_DATSEL_MASK) +#define WM8960_ADDCTL1_DATSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_DATSEL_MASK) >> WM8960_ADDCTL1_DATSEL_SHIFT) + +/* + * TOCLKSEL (RW) + * + * Slow Clock Select (Used for volume update + * timeouts and for jack detect debounce) + * 0 = SYSCLK / 221 (Slower Response) + * 1 = SYSCLK / 219 (Faster Response) + */ +#define WM8960_ADDCTL1_TOCLKSEL_MASK (0x2U) +#define WM8960_ADDCTL1_TOCLKSEL_SHIFT (1U) +#define WM8960_ADDCTL1_TOCLKSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_TOCLKSEL_SHIFT) & WM8960_ADDCTL1_TOCLKSEL_MASK) +#define WM8960_ADDCTL1_TOCLKSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_TOCLKSEL_MASK) >> WM8960_ADDCTL1_TOCLKSEL_SHIFT) + +/* + * TOEN (RW) + * + * Enables Slow Clock for Volume Update Timeout + * and Jack Detect Debounce + * 0 = Slow clock disabled + * 1 = Slow clock enabled + */ +#define WM8960_ADDCTL1_TOEN_MASK (0x1U) +#define WM8960_ADDCTL1_TOEN_SHIFT (0U) +#define WM8960_ADDCTL1_TOEN_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_TOEN_SHIFT) & WM8960_ADDCTL1_TOEN_MASK) +#define WM8960_ADDCTL1_TOEN_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_TOEN_MASK) >> WM8960_ADDCTL1_TOEN_SHIFT) + +/* Bitfield definition for register: ADDCTL2 */ +/* + * HPSWEN (RW) + * + * Headphone Switch Enable + * 0 = Headphone switch disabled + * 1 = Headphone switch enabled + */ +#define WM8960_ADDCTL2_HPSWEN_MASK (0x40U) +#define WM8960_ADDCTL2_HPSWEN_SHIFT (6U) +#define WM8960_ADDCTL2_HPSWEN_SET(x) (((uint16_t)(x) << WM8960_ADDCTL2_HPSWEN_SHIFT) & WM8960_ADDCTL2_HPSWEN_MASK) +#define WM8960_ADDCTL2_HPSWEN_GET(x) (((uint16_t)(x) & WM8960_ADDCTL2_HPSWEN_MASK) >> WM8960_ADDCTL2_HPSWEN_SHIFT) + +/* + * HPSWPOL (RW) + * + * Headphone Switch Polarity + * 0 = HPDETECT high = headphone + * 1 = HPDETECT high = speaker + */ +#define WM8960_ADDCTL2_HPSWPOL_MASK (0x20U) +#define WM8960_ADDCTL2_HPSWPOL_SHIFT (5U) +#define WM8960_ADDCTL2_HPSWPOL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL2_HPSWPOL_SHIFT) & WM8960_ADDCTL2_HPSWPOL_MASK) +#define WM8960_ADDCTL2_HPSWPOL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL2_HPSWPOL_MASK) >> WM8960_ADDCTL2_HPSWPOL_SHIFT) + +/* + * TRIS (RW) + * + * Tristates ADCDAT and switches ADCLRC, + * DACLRC and BCLK to inputs. + * 0 = ADCDAT is an output; ADCLRC, DACLRC + * and BCLK are inputs (slave mode) or outputs + * (master mode) + * 1 = ADCDAT is tristated; DACLRC and BCLK + * are inputs; ADCLRC is an input (when not + * configured as a GPIO) + */ +#define WM8960_ADDCTL2_TRIS_MASK (0x8U) +#define WM8960_ADDCTL2_TRIS_SHIFT (3U) +#define WM8960_ADDCTL2_TRIS_SET(x) (((uint16_t)(x) << WM8960_ADDCTL2_TRIS_SHIFT) & WM8960_ADDCTL2_TRIS_MASK) +#define WM8960_ADDCTL2_TRIS_GET(x) (((uint16_t)(x) & WM8960_ADDCTL2_TRIS_MASK) >> WM8960_ADDCTL2_TRIS_SHIFT) + +/* + * LRCM (RW) + * + * Selects disable mode for ADCLRC and DACLRC + * (Master mode) + * 0 = ADCLRC disabled when ADC (Left and + * Right) disabled; DACLRC disabled when + * DAC (Left and Right) disabled. + * 1 = ADCLRC and DACLRC disabled only when + * ADC (Left and Right) and DAC (Left and Right) + * are disabled. + */ +#define WM8960_ADDCTL2_LRCM_MASK (0x4U) +#define WM8960_ADDCTL2_LRCM_SHIFT (2U) +#define WM8960_ADDCTL2_LRCM_SET(x) (((uint16_t)(x) << WM8960_ADDCTL2_LRCM_SHIFT) & WM8960_ADDCTL2_LRCM_MASK) +#define WM8960_ADDCTL2_LRCM_GET(x) (((uint16_t)(x) & WM8960_ADDCTL2_LRCM_MASK) >> WM8960_ADDCTL2_LRCM_SHIFT) + +/* Bitfield definition for register: POWER1 */ +/* + * VMIDSEL (RW) + * + * Vmid Divider Enable and Select + * 00 = Vmid disabled (for OFF mode) + * 01 = 2 x 50k divider enabled (for playback / + * record) + * 10 = 2 x 250k divider enabled (for low-power + * standby) + * 11 = 2 x 5k divider enabled (for fast start-up) + */ +#define WM8960_POWER1_VMIDSEL_MASK (0x180U) +#define WM8960_POWER1_VMIDSEL_SHIFT (7U) +#define WM8960_POWER1_VMIDSEL_SET(x) (((uint16_t)(x) << WM8960_POWER1_VMIDSEL_SHIFT) & WM8960_POWER1_VMIDSEL_MASK) +#define WM8960_POWER1_VMIDSEL_GET(x) (((uint16_t)(x) & WM8960_POWER1_VMIDSEL_MASK) >> WM8960_POWER1_VMIDSEL_SHIFT) + +/* + * VREF (RW) + * + * VREF (necessary for all other functions) + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER1_VREF_MASK (0x40U) +#define WM8960_POWER1_VREF_SHIFT (6U) +#define WM8960_POWER1_VREF_SET(x) (((uint16_t)(x) << WM8960_POWER1_VREF_SHIFT) & WM8960_POWER1_VREF_MASK) +#define WM8960_POWER1_VREF_GET(x) (((uint16_t)(x) & WM8960_POWER1_VREF_MASK) >> WM8960_POWER1_VREF_SHIFT) + +/* + * AINL (RW) + * + * Analogue in PGA Left + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER1_AINL_MASK (0x20U) +#define WM8960_POWER1_AINL_SHIFT (5U) +#define WM8960_POWER1_AINL_SET(x) (((uint16_t)(x) << WM8960_POWER1_AINL_SHIFT) & WM8960_POWER1_AINL_MASK) +#define WM8960_POWER1_AINL_GET(x) (((uint16_t)(x) & WM8960_POWER1_AINL_MASK) >> WM8960_POWER1_AINL_SHIFT) + +/* + * AINR (RW) + * + * Analogue in PGA Right + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER1_AINR_MASK (0x10U) +#define WM8960_POWER1_AINR_SHIFT (4U) +#define WM8960_POWER1_AINR_SET(x) (((uint16_t)(x) << WM8960_POWER1_AINR_SHIFT) & WM8960_POWER1_AINR_MASK) +#define WM8960_POWER1_AINR_GET(x) (((uint16_t)(x) & WM8960_POWER1_AINR_MASK) >> WM8960_POWER1_AINR_SHIFT) + +/* + * ADCL (RW) + * + * ADC Left + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER1_ADCL_MASK (0x8U) +#define WM8960_POWER1_ADCL_SHIFT (3U) +#define WM8960_POWER1_ADCL_SET(x) (((uint16_t)(x) << WM8960_POWER1_ADCL_SHIFT) & WM8960_POWER1_ADCL_MASK) +#define WM8960_POWER1_ADCL_GET(x) (((uint16_t)(x) & WM8960_POWER1_ADCL_MASK) >> WM8960_POWER1_ADCL_SHIFT) + +/* + * ADCR (RW) + * + * ADC Right + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER1_ADCR_MASK (0x4U) +#define WM8960_POWER1_ADCR_SHIFT (2U) +#define WM8960_POWER1_ADCR_SET(x) (((uint16_t)(x) << WM8960_POWER1_ADCR_SHIFT) & WM8960_POWER1_ADCR_MASK) +#define WM8960_POWER1_ADCR_GET(x) (((uint16_t)(x) & WM8960_POWER1_ADCR_MASK) >> WM8960_POWER1_ADCR_SHIFT) + +/* + * MICB (RW) + * + * MICBIAS + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER1_MICB_MASK (0x2U) +#define WM8960_POWER1_MICB_SHIFT (1U) +#define WM8960_POWER1_MICB_SET(x) (((uint16_t)(x) << WM8960_POWER1_MICB_SHIFT) & WM8960_POWER1_MICB_MASK) +#define WM8960_POWER1_MICB_GET(x) (((uint16_t)(x) & WM8960_POWER1_MICB_MASK) >> WM8960_POWER1_MICB_SHIFT) + +/* + * DIGENB (RW) + * + * Master Clock Disable + * 0 = Master clock enabled + * 1 = Master clock disabled + */ +#define WM8960_POWER1_DIGENB_MASK (0x1U) +#define WM8960_POWER1_DIGENB_SHIFT (0U) +#define WM8960_POWER1_DIGENB_SET(x) (((uint16_t)(x) << WM8960_POWER1_DIGENB_SHIFT) & WM8960_POWER1_DIGENB_MASK) +#define WM8960_POWER1_DIGENB_GET(x) (((uint16_t)(x) & WM8960_POWER1_DIGENB_MASK) >> WM8960_POWER1_DIGENB_SHIFT) + +/* Bitfield definition for register: POWER2 */ +/* + * DACL (RW) + * + * DAC Left + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_DACL_MASK (0x100U) +#define WM8960_POWER2_DACL_SHIFT (8U) +#define WM8960_POWER2_DACL_SET(x) (((uint16_t)(x) << WM8960_POWER2_DACL_SHIFT) & WM8960_POWER2_DACL_MASK) +#define WM8960_POWER2_DACL_GET(x) (((uint16_t)(x) & WM8960_POWER2_DACL_MASK) >> WM8960_POWER2_DACL_SHIFT) + +/* + * DACR (RW) + * + * DAC Right + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_DACR_MASK (0x80U) +#define WM8960_POWER2_DACR_SHIFT (7U) +#define WM8960_POWER2_DACR_SET(x) (((uint16_t)(x) << WM8960_POWER2_DACR_SHIFT) & WM8960_POWER2_DACR_MASK) +#define WM8960_POWER2_DACR_GET(x) (((uint16_t)(x) & WM8960_POWER2_DACR_MASK) >> WM8960_POWER2_DACR_SHIFT) + +/* + * LOUT1 (RW) + * + * LOUT1 Output Buffer + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_LOUT1_MASK (0x40U) +#define WM8960_POWER2_LOUT1_SHIFT (6U) +#define WM8960_POWER2_LOUT1_SET(x) (((uint16_t)(x) << WM8960_POWER2_LOUT1_SHIFT) & WM8960_POWER2_LOUT1_MASK) +#define WM8960_POWER2_LOUT1_GET(x) (((uint16_t)(x) & WM8960_POWER2_LOUT1_MASK) >> WM8960_POWER2_LOUT1_SHIFT) + +/* + * ROUT1 (RW) + * + * ROUT1 Output Buffer + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_ROUT1_MASK (0x20U) +#define WM8960_POWER2_ROUT1_SHIFT (5U) +#define WM8960_POWER2_ROUT1_SET(x) (((uint16_t)(x) << WM8960_POWER2_ROUT1_SHIFT) & WM8960_POWER2_ROUT1_MASK) +#define WM8960_POWER2_ROUT1_GET(x) (((uint16_t)(x) & WM8960_POWER2_ROUT1_MASK) >> WM8960_POWER2_ROUT1_SHIFT) + +/* + * SPKL (RW) + * + * SPK_LP/SPK_LN Output Buffers + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_SPKL_MASK (0x10U) +#define WM8960_POWER2_SPKL_SHIFT (4U) +#define WM8960_POWER2_SPKL_SET(x) (((uint16_t)(x) << WM8960_POWER2_SPKL_SHIFT) & WM8960_POWER2_SPKL_MASK) +#define WM8960_POWER2_SPKL_GET(x) (((uint16_t)(x) & WM8960_POWER2_SPKL_MASK) >> WM8960_POWER2_SPKL_SHIFT) + +/* + * SPKR (RW) + * + * SPK_RP/SPK_RN Output Buffers + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_SPKR_MASK (0x8U) +#define WM8960_POWER2_SPKR_SHIFT (3U) +#define WM8960_POWER2_SPKR_SET(x) (((uint16_t)(x) << WM8960_POWER2_SPKR_SHIFT) & WM8960_POWER2_SPKR_MASK) +#define WM8960_POWER2_SPKR_GET(x) (((uint16_t)(x) & WM8960_POWER2_SPKR_MASK) >> WM8960_POWER2_SPKR_SHIFT) + +/* + * OUT3 (RW) + * + * OUT3 Output Buffer + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_OUT3_MASK (0x2U) +#define WM8960_POWER2_OUT3_SHIFT (1U) +#define WM8960_POWER2_OUT3_SET(x) (((uint16_t)(x) << WM8960_POWER2_OUT3_SHIFT) & WM8960_POWER2_OUT3_MASK) +#define WM8960_POWER2_OUT3_GET(x) (((uint16_t)(x) & WM8960_POWER2_OUT3_MASK) >> WM8960_POWER2_OUT3_SHIFT) + +/* + * PLL_EN (RW) + * + * PLL Enable + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_PLL_EN_MASK (0x1U) +#define WM8960_POWER2_PLL_EN_SHIFT (0U) +#define WM8960_POWER2_PLL_EN_SET(x) (((uint16_t)(x) << WM8960_POWER2_PLL_EN_SHIFT) & WM8960_POWER2_PLL_EN_MASK) +#define WM8960_POWER2_PLL_EN_GET(x) (((uint16_t)(x) & WM8960_POWER2_PLL_EN_MASK) >> WM8960_POWER2_PLL_EN_SHIFT) + +/* Bitfield definition for register: ADDCTL3 */ +/* + * VROI (RW) + * + * VREF to Analogue Output Resistance (Disabled + * Outputs) + * 0 = 500 VMID to output + * 1 = 20k VMID to output + */ +#define WM8960_ADDCTL3_VROI_MASK (0x40U) +#define WM8960_ADDCTL3_VROI_SHIFT (6U) +#define WM8960_ADDCTL3_VROI_SET(x) (((uint16_t)(x) << WM8960_ADDCTL3_VROI_SHIFT) & WM8960_ADDCTL3_VROI_MASK) +#define WM8960_ADDCTL3_VROI_GET(x) (((uint16_t)(x) & WM8960_ADDCTL3_VROI_MASK) >> WM8960_ADDCTL3_VROI_SHIFT) + +/* + * OUT3CAP (RW) + * + * Capless Mode Headphone Switch Enable + * 0 = OUT3 unaffected by jack detect events + * 1 = OUT3 enabled and disabled together with + * HP_L and HP_R in response to jack detect + * events + */ +#define WM8960_ADDCTL3_OUT3CAP_MASK (0x8U) +#define WM8960_ADDCTL3_OUT3CAP_SHIFT (3U) +#define WM8960_ADDCTL3_OUT3CAP_SET(x) (((uint16_t)(x) << WM8960_ADDCTL3_OUT3CAP_SHIFT) & WM8960_ADDCTL3_OUT3CAP_MASK) +#define WM8960_ADDCTL3_OUT3CAP_GET(x) (((uint16_t)(x) & WM8960_ADDCTL3_OUT3CAP_MASK) >> WM8960_ADDCTL3_OUT3CAP_SHIFT) + +/* + * ADC_ALC_SR (RW) + * + * ALC Sample Rate + * 000 = 44.1k / 48k + * 001 = 32k + * 010 = 22.05k / 24k + * 011 = 16k + * 100 = 11.25k / 12k + * 101 = 8k + * 110 and 111 = Reserved + */ +#define WM8960_ADDCTL3_ADC_ALC_SR_MASK (0x7U) +#define WM8960_ADDCTL3_ADC_ALC_SR_SHIFT (0U) +#define WM8960_ADDCTL3_ADC_ALC_SR_SET(x) (((uint16_t)(x) << WM8960_ADDCTL3_ADC_ALC_SR_SHIFT) & WM8960_ADDCTL3_ADC_ALC_SR_MASK) +#define WM8960_ADDCTL3_ADC_ALC_SR_GET(x) (((uint16_t)(x) & WM8960_ADDCTL3_ADC_ALC_SR_MASK) >> WM8960_ADDCTL3_ADC_ALC_SR_SHIFT) + +/* Bitfield definition for register: APOP1 */ +/* + * POBCTRL (RW) + * + * Selects the bias current source for output + * amplifiers and VMID buffer + * 0 = VMID / R bias + * 1 = VGS / R bias + */ +#define WM8960_APOP1_POBCTRL_MASK (0x80U) +#define WM8960_APOP1_POBCTRL_SHIFT (7U) +#define WM8960_APOP1_POBCTRL_SET(x) (((uint16_t)(x) << WM8960_APOP1_POBCTRL_SHIFT) & WM8960_APOP1_POBCTRL_MASK) +#define WM8960_APOP1_POBCTRL_GET(x) (((uint16_t)(x) & WM8960_APOP1_POBCTRL_MASK) >> WM8960_APOP1_POBCTRL_SHIFT) + +/* + * BUFDCOPEN (RW) + * + * Enables the VGS / R current generator + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_APOP1_BUFDCOPEN_MASK (0x10U) +#define WM8960_APOP1_BUFDCOPEN_SHIFT (4U) +#define WM8960_APOP1_BUFDCOPEN_SET(x) (((uint16_t)(x) << WM8960_APOP1_BUFDCOPEN_SHIFT) & WM8960_APOP1_BUFDCOPEN_MASK) +#define WM8960_APOP1_BUFDCOPEN_GET(x) (((uint16_t)(x) & WM8960_APOP1_BUFDCOPEN_MASK) >> WM8960_APOP1_BUFDCOPEN_SHIFT) + +/* + * BUFIOEN (RW) + * + * Enables the VGS / R current generator and the + * analogue input and output bias + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_APOP1_BUFIOEN_MASK (0x8U) +#define WM8960_APOP1_BUFIOEN_SHIFT (3U) +#define WM8960_APOP1_BUFIOEN_SET(x) (((uint16_t)(x) << WM8960_APOP1_BUFIOEN_SHIFT) & WM8960_APOP1_BUFIOEN_MASK) +#define WM8960_APOP1_BUFIOEN_GET(x) (((uint16_t)(x) & WM8960_APOP1_BUFIOEN_MASK) >> WM8960_APOP1_BUFIOEN_SHIFT) + +/* + * SOFT_ST (RW) + * + * Enables VMID soft start + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_APOP1_SOFT_ST_MASK (0x4U) +#define WM8960_APOP1_SOFT_ST_SHIFT (2U) +#define WM8960_APOP1_SOFT_ST_SET(x) (((uint16_t)(x) << WM8960_APOP1_SOFT_ST_SHIFT) & WM8960_APOP1_SOFT_ST_MASK) +#define WM8960_APOP1_SOFT_ST_GET(x) (((uint16_t)(x) & WM8960_APOP1_SOFT_ST_MASK) >> WM8960_APOP1_SOFT_ST_SHIFT) + +/* + * HPSTBY (RW) + * + * Headphone Amplifier Standby + * 0 = Standby mode disabled (Normal operation) + * 1 = Standby mode enabled + */ +#define WM8960_APOP1_HPSTBY_MASK (0x1U) +#define WM8960_APOP1_HPSTBY_SHIFT (0U) +#define WM8960_APOP1_HPSTBY_SET(x) (((uint16_t)(x) << WM8960_APOP1_HPSTBY_SHIFT) & WM8960_APOP1_HPSTBY_MASK) +#define WM8960_APOP1_HPSTBY_GET(x) (((uint16_t)(x) & WM8960_APOP1_HPSTBY_MASK) >> WM8960_APOP1_HPSTBY_SHIFT) + +/* Bitfield definition for register: APOP2 */ +/* + * DISOP (RW) + * + * Discharges the DC-blocking headphone + * capacitors on HP_L and HP_R + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_APOP2_DISOP_MASK (0x40U) +#define WM8960_APOP2_DISOP_SHIFT (6U) +#define WM8960_APOP2_DISOP_SET(x) (((uint16_t)(x) << WM8960_APOP2_DISOP_SHIFT) & WM8960_APOP2_DISOP_MASK) +#define WM8960_APOP2_DISOP_GET(x) (((uint16_t)(x) & WM8960_APOP2_DISOP_MASK) >> WM8960_APOP2_DISOP_SHIFT) + +/* + * DRES (RW) + * + * DRES determines the value of the resistors used + * to discharge the DC-blocking headphone + * capacitors when DISOP=1 + * DRES[1:0] Resistance (Ohms) + * 0 0 400 + * 0 1 200 + * 1 0 600 + * 1 1 150 + */ +#define WM8960_APOP2_DRES_MASK (0x30U) +#define WM8960_APOP2_DRES_SHIFT (4U) +#define WM8960_APOP2_DRES_SET(x) (((uint16_t)(x) << WM8960_APOP2_DRES_SHIFT) & WM8960_APOP2_DRES_MASK) +#define WM8960_APOP2_DRES_GET(x) (((uint16_t)(x) & WM8960_APOP2_DRES_MASK) >> WM8960_APOP2_DRES_SHIFT) + +/* Bitfield definition for register: LINPATH */ +/* + * LMN1 (RW) + * + * Connect LINPUT1 to inverting input of Left Input + * PGA + * 0 = LINPUT1 not connected to PGA + * 1 = LINPUT1 connected to PGA + */ +#define WM8960_LINPATH_LMN1_MASK (0x100U) +#define WM8960_LINPATH_LMN1_SHIFT (8U) +#define WM8960_LINPATH_LMN1_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMN1_SHIFT) & WM8960_LINPATH_LMN1_MASK) +#define WM8960_LINPATH_LMN1_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMN1_MASK) >> WM8960_LINPATH_LMN1_SHIFT) + +/* + * LMP3 (RW) + * + * Connect LINPUT3 to non-inverting input of Left + * Input PGA + * 0 = LINPUT3 not connected to PGA + * 1 = LINPUT3 connected to PGA (Constant input + * impedance) + */ +#define WM8960_LINPATH_LMP3_MASK (0x80U) +#define WM8960_LINPATH_LMP3_SHIFT (7U) +#define WM8960_LINPATH_LMP3_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMP3_SHIFT) & WM8960_LINPATH_LMP3_MASK) +#define WM8960_LINPATH_LMP3_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMP3_MASK) >> WM8960_LINPATH_LMP3_SHIFT) + +/* + * LMP2 (RW) + * + * Connect LINPUT2 to non-inverting input of Left + * Input PGA + * 0 = LINPUT2 not connected to PGA + * 1 = LINPUT2 connected to PGA (Constant input impedance) + */ +#define WM8960_LINPATH_LMP2_MASK (0x40U) +#define WM8960_LINPATH_LMP2_SHIFT (6U) +#define WM8960_LINPATH_LMP2_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMP2_SHIFT) & WM8960_LINPATH_LMP2_MASK) +#define WM8960_LINPATH_LMP2_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMP2_MASK) >> WM8960_LINPATH_LMP2_SHIFT) + +/* + * LMICBOOST (RW) + * + * Left Channel Input PGA Boost Gain + * 00 = +0dB + * 01 = +13dB + * 10 = +20dB + * 11 = +29dB + */ +#define WM8960_LINPATH_LMICBOOST_MASK (0x30U) +#define WM8960_LINPATH_LMICBOOST_SHIFT (4U) +#define WM8960_LINPATH_LMICBOOST_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMICBOOST_SHIFT) & WM8960_LINPATH_LMICBOOST_MASK) +#define WM8960_LINPATH_LMICBOOST_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMICBOOST_MASK) >> WM8960_LINPATH_LMICBOOST_SHIFT) + +/* + * LMIC2B (RW) + * + * Connect Left Input PGA to Left Input Boost Mixer + * 0 = Not connected + * 1 = Connected + */ +#define WM8960_LINPATH_LMIC2B_MASK (0x8U) +#define WM8960_LINPATH_LMIC2B_SHIFT (3U) +#define WM8960_LINPATH_LMIC2B_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMIC2B_SHIFT) & WM8960_LINPATH_LMIC2B_MASK) +#define WM8960_LINPATH_LMIC2B_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMIC2B_MASK) >> WM8960_LINPATH_LMIC2B_SHIFT) + +/* Bitfield definition for register: RINPATH */ +/* + * RMN1 (RW) + * + * Connect RINPUT1 to inverting input of Right + * Input PGA + * 0 = RINPUT1 not connected to PGA + * 1 = RINPUT1 connected to PGA + */ +#define WM8960_RINPATH_RMN1_MASK (0x100U) +#define WM8960_RINPATH_RMN1_SHIFT (8U) +#define WM8960_RINPATH_RMN1_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMN1_SHIFT) & WM8960_RINPATH_RMN1_MASK) +#define WM8960_RINPATH_RMN1_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMN1_MASK) >> WM8960_RINPATH_RMN1_SHIFT) + +/* + * RMP3 (RW) + * + * Connect RINPUT3 to non-inverting input of Right + * Input PGA + * 0 = RINPUT3 not connected to PGA + * 1 = RINPUT3 connected to PGA (Constant input impedance) + */ +#define WM8960_RINPATH_RMP3_MASK (0x80U) +#define WM8960_RINPATH_RMP3_SHIFT (7U) +#define WM8960_RINPATH_RMP3_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMP3_SHIFT) & WM8960_RINPATH_RMP3_MASK) +#define WM8960_RINPATH_RMP3_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMP3_MASK) >> WM8960_RINPATH_RMP3_SHIFT) + +/* + * RMP2 (RW) + * + * Connect RINPUT2 to non-inverting input of Right + * Input PGA + * 0 = RINPUT2 not connected to PGA + * 1 = RINPUT2 connected to PGA (Constant input + * impedance) + */ +#define WM8960_RINPATH_RMP2_MASK (0x40U) +#define WM8960_RINPATH_RMP2_SHIFT (6U) +#define WM8960_RINPATH_RMP2_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMP2_SHIFT) & WM8960_RINPATH_RMP2_MASK) +#define WM8960_RINPATH_RMP2_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMP2_MASK) >> WM8960_RINPATH_RMP2_SHIFT) + +/* + * RMICBOOST (RW) + * + * Right Channel Input PGA Boost Gain + * 00 = +0dB + * 01 = +13dB + * 10 = +20dB + * 11 = +29dB + */ +#define WM8960_RINPATH_RMICBOOST_MASK (0x30U) +#define WM8960_RINPATH_RMICBOOST_SHIFT (4U) +#define WM8960_RINPATH_RMICBOOST_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMICBOOST_SHIFT) & WM8960_RINPATH_RMICBOOST_MASK) +#define WM8960_RINPATH_RMICBOOST_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMICBOOST_MASK) >> WM8960_RINPATH_RMICBOOST_SHIFT) + +/* + * RMIC2B (RW) + * + * Connect Right Input PGA to Right Input Boost + * Mixer + * 0 = Not connected + * 1 = Connected + */ +#define WM8960_RINPATH_RMIC2B_MASK (0x8U) +#define WM8960_RINPATH_RMIC2B_SHIFT (3U) +#define WM8960_RINPATH_RMIC2B_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMIC2B_SHIFT) & WM8960_RINPATH_RMIC2B_MASK) +#define WM8960_RINPATH_RMIC2B_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMIC2B_MASK) >> WM8960_RINPATH_RMIC2B_SHIFT) + +/* Bitfield definition for register: LOUTMIX */ +/* + * LD2LO (RW) + * + * Left DAC to Left Output Mixer + * 0 = Disable (Mute) + * 1 = Enable Path + */ +#define WM8960_LOUTMIX_LD2LO_MASK (0x100U) +#define WM8960_LOUTMIX_LD2LO_SHIFT (8U) +#define WM8960_LOUTMIX_LD2LO_SET(x) (((uint16_t)(x) << WM8960_LOUTMIX_LD2LO_SHIFT) & WM8960_LOUTMIX_LD2LO_MASK) +#define WM8960_LOUTMIX_LD2LO_GET(x) (((uint16_t)(x) & WM8960_LOUTMIX_LD2LO_MASK) >> WM8960_LOUTMIX_LD2LO_SHIFT) + +/* + * LI2LO (RW) + * + * LINPUT3 to Left Output Mixer + * 0 = Disable (Mute) + * 1 = Enable Path + */ +#define WM8960_LOUTMIX_LI2LO_MASK (0x80U) +#define WM8960_LOUTMIX_LI2LO_SHIFT (7U) +#define WM8960_LOUTMIX_LI2LO_SET(x) (((uint16_t)(x) << WM8960_LOUTMIX_LI2LO_SHIFT) & WM8960_LOUTMIX_LI2LO_MASK) +#define WM8960_LOUTMIX_LI2LO_GET(x) (((uint16_t)(x) & WM8960_LOUTMIX_LI2LO_MASK) >> WM8960_LOUTMIX_LI2LO_SHIFT) + +/* + * LI2LOVOL (RW) + * + * LINPUT3 to Left Output Mixer Volume + * 000 = 0dB + * ...(3dB steps) + * 111 = -21dB + */ +#define WM8960_LOUTMIX_LI2LOVOL_MASK (0x70U) +#define WM8960_LOUTMIX_LI2LOVOL_SHIFT (4U) +#define WM8960_LOUTMIX_LI2LOVOL_SET(x) (((uint16_t)(x) << WM8960_LOUTMIX_LI2LOVOL_SHIFT) & WM8960_LOUTMIX_LI2LOVOL_MASK) +#define WM8960_LOUTMIX_LI2LOVOL_GET(x) (((uint16_t)(x) & WM8960_LOUTMIX_LI2LOVOL_MASK) >> WM8960_LOUTMIX_LI2LOVOL_SHIFT) + +/* Bitfield definition for register: ROUTMIX */ +/* + * RD2RO (RW) + * + * Right DAC to Right Output Mixer + * 0 = Disable (Mute) + * 1 = Enable Path + */ +#define WM8960_ROUTMIX_RD2RO_MASK (0x100U) +#define WM8960_ROUTMIX_RD2RO_SHIFT (8U) +#define WM8960_ROUTMIX_RD2RO_SET(x) (((uint16_t)(x) << WM8960_ROUTMIX_RD2RO_SHIFT) & WM8960_ROUTMIX_RD2RO_MASK) +#define WM8960_ROUTMIX_RD2RO_GET(x) (((uint16_t)(x) & WM8960_ROUTMIX_RD2RO_MASK) >> WM8960_ROUTMIX_RD2RO_SHIFT) + +/* + * RI2RO (RW) + * + * RINPUT3 to Right Output Mixer + * 0 = Disable (Mute) + * 1 = Enable Path + */ +#define WM8960_ROUTMIX_RI2RO_MASK (0x80U) +#define WM8960_ROUTMIX_RI2RO_SHIFT (7U) +#define WM8960_ROUTMIX_RI2RO_SET(x) (((uint16_t)(x) << WM8960_ROUTMIX_RI2RO_SHIFT) & WM8960_ROUTMIX_RI2RO_MASK) +#define WM8960_ROUTMIX_RI2RO_GET(x) (((uint16_t)(x) & WM8960_ROUTMIX_RI2RO_MASK) >> WM8960_ROUTMIX_RI2RO_SHIFT) + +/* + * RI2ROVOL (RW) + * + * RINPUT3 to Right Output Mixer Volume + * 000 = 0dB + * ...(3dB steps) + * 111 = -21dB + */ +#define WM8960_ROUTMIX_RI2ROVOL_MASK (0x70U) +#define WM8960_ROUTMIX_RI2ROVOL_SHIFT (4U) +#define WM8960_ROUTMIX_RI2ROVOL_SET(x) (((uint16_t)(x) << WM8960_ROUTMIX_RI2ROVOL_SHIFT) & WM8960_ROUTMIX_RI2ROVOL_MASK) +#define WM8960_ROUTMIX_RI2ROVOL_GET(x) (((uint16_t)(x) & WM8960_ROUTMIX_RI2ROVOL_MASK) >> WM8960_ROUTMIX_RI2ROVOL_SHIFT) + +/* Bitfield definition for register: MONOMIX1 */ +/* + * L2MO (RW) + * + * Left Output Mixer to Mono Output Mixer Control + * 0 = Left channel mix disabled + * 1 = Left channel mix enabled + */ +#define WM8960_MONOMIX1_L2MO_MASK (0x80U) +#define WM8960_MONOMIX1_L2MO_SHIFT (7U) +#define WM8960_MONOMIX1_L2MO_SET(x) (((uint16_t)(x) << WM8960_MONOMIX1_L2MO_SHIFT) & WM8960_MONOMIX1_L2MO_MASK) +#define WM8960_MONOMIX1_L2MO_GET(x) (((uint16_t)(x) & WM8960_MONOMIX1_L2MO_MASK) >> WM8960_MONOMIX1_L2MO_SHIFT) + +/* Bitfield definition for register: MONOMIX2 */ +/* + * R2MO (RW) + * + * Right Output Mixer to Mono Output Mixer Control + * 0 = Right channel mix disabled + * 1 = Right channel mix enabled + */ +#define WM8960_MONOMIX2_R2MO_MASK (0x80U) +#define WM8960_MONOMIX2_R2MO_SHIFT (7U) +#define WM8960_MONOMIX2_R2MO_SET(x) (((uint16_t)(x) << WM8960_MONOMIX2_R2MO_SHIFT) & WM8960_MONOMIX2_R2MO_MASK) +#define WM8960_MONOMIX2_R2MO_GET(x) (((uint16_t)(x) & WM8960_MONOMIX2_R2MO_MASK) >> WM8960_MONOMIX2_R2MO_SHIFT) + +/* Bitfield definition for register: LOUT2 */ +/* + * SPKVU (RW) + * + * Speaker Volume Update + * Writing a 1 to this bit will cause left and right speaker volumes to be updated (SPKLVOL and SPKRVOL) + */ +#define WM8960_LOUT2_SPKVU_MASK (0x100U) +#define WM8960_LOUT2_SPKVU_SHIFT (8U) +#define WM8960_LOUT2_SPKVU_SET(x) (((uint16_t)(x) << WM8960_LOUT2_SPKVU_SHIFT) & WM8960_LOUT2_SPKVU_MASK) +#define WM8960_LOUT2_SPKVU_GET(x) (((uint16_t)(x) & WM8960_LOUT2_SPKVU_MASK) >> WM8960_LOUT2_SPKVU_SHIFT) + +/* + * SPKLZC (RW) + * + * Left Speaker Zero Cross Enable + * 1 = Change gain on zero cross only + * 0 = Change gain immediately + */ +#define WM8960_LOUT2_SPKLZC_MASK (0x80U) +#define WM8960_LOUT2_SPKLZC_SHIFT (7U) +#define WM8960_LOUT2_SPKLZC_SET(x) (((uint16_t)(x) << WM8960_LOUT2_SPKLZC_SHIFT) & WM8960_LOUT2_SPKLZC_MASK) +#define WM8960_LOUT2_SPKLZC_GET(x) (((uint16_t)(x) & WM8960_LOUT2_SPKLZC_MASK) >> WM8960_LOUT2_SPKLZC_SHIFT) + +/* + * SPKLVOL (RW) + * + * SPK_LP/SPK_LN Volume + * 1111111 = +6dB + * … 1dB steps down to + * 0110000 = -73dB + * 0101111 to 0000000 = Analogue MUTE + */ +#define WM8960_LOUT2_SPKLVOL_MASK (0x7FU) +#define WM8960_LOUT2_SPKLVOL_SHIFT (0U) +#define WM8960_LOUT2_SPKLVOL_SET(x) (((uint16_t)(x) << WM8960_LOUT2_SPKLVOL_SHIFT) & WM8960_LOUT2_SPKLVOL_MASK) +#define WM8960_LOUT2_SPKLVOL_GET(x) (((uint16_t)(x) & WM8960_LOUT2_SPKLVOL_MASK) >> WM8960_LOUT2_SPKLVOL_SHIFT) + +/* Bitfield definition for register: ROUT2 */ +/* + * SPKVU (RW) + * + * Speaker Volume Update + * Writing a 1 to this bit will cause left and right + * speaker volumes to be updated (SPKLVOL and SPKRVOL) + */ +#define WM8960_ROUT2_SPKVU_MASK (0x100U) +#define WM8960_ROUT2_SPKVU_SHIFT (8U) +#define WM8960_ROUT2_SPKVU_SET(x) (((uint16_t)(x) << WM8960_ROUT2_SPKVU_SHIFT) & WM8960_ROUT2_SPKVU_MASK) +#define WM8960_ROUT2_SPKVU_GET(x) (((uint16_t)(x) & WM8960_ROUT2_SPKVU_MASK) >> WM8960_ROUT2_SPKVU_SHIFT) + +/* + * SPKRZC (RW) + * + * Right Speaker Zero Cross Enable + * 1 = Change gain on zero cross only + * 0 = Change gain immediately + */ +#define WM8960_ROUT2_SPKRZC_MASK (0x80U) +#define WM8960_ROUT2_SPKRZC_SHIFT (7U) +#define WM8960_ROUT2_SPKRZC_SET(x) (((uint16_t)(x) << WM8960_ROUT2_SPKRZC_SHIFT) & WM8960_ROUT2_SPKRZC_MASK) +#define WM8960_ROUT2_SPKRZC_GET(x) (((uint16_t)(x) & WM8960_ROUT2_SPKRZC_MASK) >> WM8960_ROUT2_SPKRZC_SHIFT) + +/* + * SPKRVOL (RW) + * + * SPK_RP/SPK_RN Volume + * 1111111 = +6dB + * … 1dB steps down to + * 0110000 = -73dB + * 0101111 to 0000000 = Analogue MUTE + */ +#define WM8960_ROUT2_SPKRVOL_MASK (0x7FU) +#define WM8960_ROUT2_SPKRVOL_SHIFT (0U) +#define WM8960_ROUT2_SPKRVOL_SET(x) (((uint16_t)(x) << WM8960_ROUT2_SPKRVOL_SHIFT) & WM8960_ROUT2_SPKRVOL_MASK) +#define WM8960_ROUT2_SPKRVOL_GET(x) (((uint16_t)(x) & WM8960_ROUT2_SPKRVOL_MASK) >> WM8960_ROUT2_SPKRVOL_SHIFT) + +/* Bitfield definition for register: MONO */ +/* + * MOUTVOL (RW) + * + * Mono Output Mixer Volume Control + * 0 = 0dB + * 1 = -6dB + */ +#define WM8960_MONO_MOUTVOL_MASK (0x40U) +#define WM8960_MONO_MOUTVOL_SHIFT (6U) +#define WM8960_MONO_MOUTVOL_SET(x) (((uint16_t)(x) << WM8960_MONO_MOUTVOL_SHIFT) & WM8960_MONO_MOUTVOL_MASK) +#define WM8960_MONO_MOUTVOL_GET(x) (((uint16_t)(x) & WM8960_MONO_MOUTVOL_MASK) >> WM8960_MONO_MOUTVOL_SHIFT) + +/* Bitfield definition for register: INBMIX1 */ +/* + * LIN3BOOST (RW) + * + * LINPUT3 to Boost Mixer Gain + * 000 = Mute + * 001 = -12dB + * ...3dB steps up to + * 111 = +6dB + */ +#define WM8960_INBMIX1_LIN3BOOST_MASK (0x70U) +#define WM8960_INBMIX1_LIN3BOOST_SHIFT (4U) +#define WM8960_INBMIX1_LIN3BOOST_SET(x) (((uint16_t)(x) << WM8960_INBMIX1_LIN3BOOST_SHIFT) & WM8960_INBMIX1_LIN3BOOST_MASK) +#define WM8960_INBMIX1_LIN3BOOST_GET(x) (((uint16_t)(x) & WM8960_INBMIX1_LIN3BOOST_MASK) >> WM8960_INBMIX1_LIN3BOOST_SHIFT) + +/* + * LIN2BOOST (RW) + * + * LINPUT2 to Boost Mixer Gain + * 000 = Mute + * 001 = -12dB + * ...3dB steps up to + * 111 = +6dB + */ +#define WM8960_INBMIX1_LIN2BOOST_MASK (0xEU) +#define WM8960_INBMIX1_LIN2BOOST_SHIFT (1U) +#define WM8960_INBMIX1_LIN2BOOST_SET(x) (((uint16_t)(x) << WM8960_INBMIX1_LIN2BOOST_SHIFT) & WM8960_INBMIX1_LIN2BOOST_MASK) +#define WM8960_INBMIX1_LIN2BOOST_GET(x) (((uint16_t)(x) & WM8960_INBMIX1_LIN2BOOST_MASK) >> WM8960_INBMIX1_LIN2BOOST_SHIFT) + +/* Bitfield definition for register: INBMIX2 */ +/* + * RIN3BOOST (RW) + * + * RINPUT3 to Boost Mixer Gain + * 000 = Mute + * 001 = -12dB + * ...3dB steps up to + * 111 = +6dB + */ +#define WM8960_INBMIX2_RIN3BOOST_MASK (0x70U) +#define WM8960_INBMIX2_RIN3BOOST_SHIFT (4U) +#define WM8960_INBMIX2_RIN3BOOST_SET(x) (((uint16_t)(x) << WM8960_INBMIX2_RIN3BOOST_SHIFT) & WM8960_INBMIX2_RIN3BOOST_MASK) +#define WM8960_INBMIX2_RIN3BOOST_GET(x) (((uint16_t)(x) & WM8960_INBMIX2_RIN3BOOST_MASK) >> WM8960_INBMIX2_RIN3BOOST_SHIFT) + +/* + * RIN2BOOST (RW) + * + * RINPUT2 to Boost Mixer Gain + * 000 = Mute + * 001 = -12dB + * ...3dB steps up to + * 111 = +6dB + */ +#define WM8960_INBMIX2_RIN2BOOST_MASK (0xEU) +#define WM8960_INBMIX2_RIN2BOOST_SHIFT (1U) +#define WM8960_INBMIX2_RIN2BOOST_SET(x) (((uint16_t)(x) << WM8960_INBMIX2_RIN2BOOST_SHIFT) & WM8960_INBMIX2_RIN2BOOST_MASK) +#define WM8960_INBMIX2_RIN2BOOST_GET(x) (((uint16_t)(x) & WM8960_INBMIX2_RIN2BOOST_MASK) >> WM8960_INBMIX2_RIN2BOOST_SHIFT) + +/* Bitfield definition for register: BYPASS1 */ +/* + * LB2LO (RW) + * + * Left Input Boost Mixer to Left Output Mixer + * 0 = Disable (Mute) + * 1 = Enable Path + */ +#define WM8960_BYPASS1_LB2LO_MASK (0x80U) +#define WM8960_BYPASS1_LB2LO_SHIFT (7U) +#define WM8960_BYPASS1_LB2LO_SET(x) (((uint16_t)(x) << WM8960_BYPASS1_LB2LO_SHIFT) & WM8960_BYPASS1_LB2LO_MASK) +#define WM8960_BYPASS1_LB2LO_GET(x) (((uint16_t)(x) & WM8960_BYPASS1_LB2LO_MASK) >> WM8960_BYPASS1_LB2LO_SHIFT) + +/* + * LB2LOVOL (RW) + * + * Left Input Boost Mixer to Left Output Mixer + * Volume + * 000 = 0dB + * ...(3dB steps) + * 111 = -21dB + */ +#define WM8960_BYPASS1_LB2LOVOL_MASK (0x70U) +#define WM8960_BYPASS1_LB2LOVOL_SHIFT (4U) +#define WM8960_BYPASS1_LB2LOVOL_SET(x) (((uint16_t)(x) << WM8960_BYPASS1_LB2LOVOL_SHIFT) & WM8960_BYPASS1_LB2LOVOL_MASK) +#define WM8960_BYPASS1_LB2LOVOL_GET(x) (((uint16_t)(x) & WM8960_BYPASS1_LB2LOVOL_MASK) >> WM8960_BYPASS1_LB2LOVOL_SHIFT) + +/* Bitfield definition for register: BYPASS2 */ +/* + * RB2RO (RW) + * + * Right Input Boost Mixer to Right Output Mixer + * 0 = Disable (Mute) + * 1 = Enable Path + */ +#define WM8960_BYPASS2_RB2RO_MASK (0x80U) +#define WM8960_BYPASS2_RB2RO_SHIFT (7U) +#define WM8960_BYPASS2_RB2RO_SET(x) (((uint16_t)(x) << WM8960_BYPASS2_RB2RO_SHIFT) & WM8960_BYPASS2_RB2RO_MASK) +#define WM8960_BYPASS2_RB2RO_GET(x) (((uint16_t)(x) & WM8960_BYPASS2_RB2RO_MASK) >> WM8960_BYPASS2_RB2RO_SHIFT) + +/* + * RB2ROVOL (RW) + * + * Right Input Boost Mixer to Right Output Mixer + * Volume + * 000 = 0dB + * ...(3dB steps) + * 111 = -21dB + */ +#define WM8960_BYPASS2_RB2ROVOL_MASK (0x70U) +#define WM8960_BYPASS2_RB2ROVOL_SHIFT (4U) +#define WM8960_BYPASS2_RB2ROVOL_SET(x) (((uint16_t)(x) << WM8960_BYPASS2_RB2ROVOL_SHIFT) & WM8960_BYPASS2_RB2ROVOL_MASK) +#define WM8960_BYPASS2_RB2ROVOL_GET(x) (((uint16_t)(x) & WM8960_BYPASS2_RB2ROVOL_MASK) >> WM8960_BYPASS2_RB2ROVOL_SHIFT) + +/* Bitfield definition for register: POWER3 */ +/* + * LMIC (RW) + * + * Left Channel Input PGA Enable + * 0 = PGA disabled + * 1 = PGA enabled (if AINL = 1) + */ +#define WM8960_POWER3_LMIC_MASK (0x20U) +#define WM8960_POWER3_LMIC_SHIFT (5U) +#define WM8960_POWER3_LMIC_SET(x) (((uint16_t)(x) << WM8960_POWER3_LMIC_SHIFT) & WM8960_POWER3_LMIC_MASK) +#define WM8960_POWER3_LMIC_GET(x) (((uint16_t)(x) & WM8960_POWER3_LMIC_MASK) >> WM8960_POWER3_LMIC_SHIFT) + +/* + * RMIC (RW) + * + * Right Channel Input PGA Enable + * 0 = PGA disabled + * 1 = PGA enabled (if AINR = 1) + */ +#define WM8960_POWER3_RMIC_MASK (0x10U) +#define WM8960_POWER3_RMIC_SHIFT (4U) +#define WM8960_POWER3_RMIC_SET(x) (((uint16_t)(x) << WM8960_POWER3_RMIC_SHIFT) & WM8960_POWER3_RMIC_MASK) +#define WM8960_POWER3_RMIC_GET(x) (((uint16_t)(x) & WM8960_POWER3_RMIC_MASK) >> WM8960_POWER3_RMIC_SHIFT) + +/* + * LOMIX (RW) + * + * Left Output Mixer Enable Control + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_POWER3_LOMIX_MASK (0x8U) +#define WM8960_POWER3_LOMIX_SHIFT (3U) +#define WM8960_POWER3_LOMIX_SET(x) (((uint16_t)(x) << WM8960_POWER3_LOMIX_SHIFT) & WM8960_POWER3_LOMIX_MASK) +#define WM8960_POWER3_LOMIX_GET(x) (((uint16_t)(x) & WM8960_POWER3_LOMIX_MASK) >> WM8960_POWER3_LOMIX_SHIFT) + +/* + * ROMIX (RW) + * + * Right Output Mixer Enable Control + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_POWER3_ROMIX_MASK (0x4U) +#define WM8960_POWER3_ROMIX_SHIFT (2U) +#define WM8960_POWER3_ROMIX_SET(x) (((uint16_t)(x) << WM8960_POWER3_ROMIX_SHIFT) & WM8960_POWER3_ROMIX_MASK) +#define WM8960_POWER3_ROMIX_GET(x) (((uint16_t)(x) & WM8960_POWER3_ROMIX_MASK) >> WM8960_POWER3_ROMIX_SHIFT) + +/* Bitfield definition for register: ADDCTL4 */ +/* + * GPIOPOL (RW) + * + * GPIO Polarity Invert + * 0 = Non inverted + * 1 = Inverted + */ +#define WM8960_ADDCTL4_GPIOPOL_MASK (0x80U) +#define WM8960_ADDCTL4_GPIOPOL_SHIFT (7U) +#define WM8960_ADDCTL4_GPIOPOL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_GPIOPOL_SHIFT) & WM8960_ADDCTL4_GPIOPOL_MASK) +#define WM8960_ADDCTL4_GPIOPOL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_GPIOPOL_MASK) >> WM8960_ADDCTL4_GPIOPOL_SHIFT) + +/* + * GPIOSEL (RW) + * + * ADCLRC/GPIO1 GPIO Function Select: + * 000 = Jack detect input + * 001 = Reserved + * 010 = Temperature ok + * 011 = Debounced jack detect output + * 100 = SYSCLK output + * 101 = PLL lock + * 110 = Logic 0 + * 111 = Logic 1 + */ +#define WM8960_ADDCTL4_GPIOSEL_MASK (0x70U) +#define WM8960_ADDCTL4_GPIOSEL_SHIFT (4U) +#define WM8960_ADDCTL4_GPIOSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_GPIOSEL_SHIFT) & WM8960_ADDCTL4_GPIOSEL_MASK) +#define WM8960_ADDCTL4_GPIOSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_GPIOSEL_MASK) >> WM8960_ADDCTL4_GPIOSEL_SHIFT) + +/* + * HPSEL (RW) + * + * Headphone Switch Input Select + * 0X = GPIO1 used for jack detect input (Requires + * ADCLRC pin to be configured as a GPIO) + * 10 = JD2 used for jack detect input + * 11 = JD3 used for jack detect input + */ +#define WM8960_ADDCTL4_HPSEL_MASK (0xCU) +#define WM8960_ADDCTL4_HPSEL_SHIFT (2U) +#define WM8960_ADDCTL4_HPSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_HPSEL_SHIFT) & WM8960_ADDCTL4_HPSEL_MASK) +#define WM8960_ADDCTL4_HPSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_HPSEL_MASK) >> WM8960_ADDCTL4_HPSEL_SHIFT) + +/* + * TSENSEN (RW) + * + * Temperature Sensor Enable + * 0 = Temperature sensor disabled + * 1 = Temperature sensor enabled + */ +#define WM8960_ADDCTL4_TSENSEN_MASK (0x2U) +#define WM8960_ADDCTL4_TSENSEN_SHIFT (1U) +#define WM8960_ADDCTL4_TSENSEN_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_TSENSEN_SHIFT) & WM8960_ADDCTL4_TSENSEN_MASK) +#define WM8960_ADDCTL4_TSENSEN_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_TSENSEN_MASK) >> WM8960_ADDCTL4_TSENSEN_SHIFT) + +/* + * MBSEL (RW) + * + * Microphone Bias Voltage Control + * 0 = 0.9 * AVDD + * 1 = 0.65 * AVDD + */ +#define WM8960_ADDCTL4_MBSEL_MASK (0x1U) +#define WM8960_ADDCTL4_MBSEL_SHIFT (0U) +#define WM8960_ADDCTL4_MBSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_MBSEL_SHIFT) & WM8960_ADDCTL4_MBSEL_MASK) +#define WM8960_ADDCTL4_MBSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_MBSEL_MASK) >> WM8960_ADDCTL4_MBSEL_SHIFT) + +/* Bitfield definition for register: CLASSD1 */ +/* + * SPK_OP_EN (RW) + * + * Enable Class D Speaker Outputs + * 00 = Off + * 01 = Left speaker only + * 10 = Right speaker only + * 11 = Left and right speakers enabled + */ +#define WM8960_CLASSD1_SPK_OP_EN_MASK (0xC0U) +#define WM8960_CLASSD1_SPK_OP_EN_SHIFT (6U) +#define WM8960_CLASSD1_SPK_OP_EN_SET(x) (((uint16_t)(x) << WM8960_CLASSD1_SPK_OP_EN_SHIFT) & WM8960_CLASSD1_SPK_OP_EN_MASK) +#define WM8960_CLASSD1_SPK_OP_EN_GET(x) (((uint16_t)(x) & WM8960_CLASSD1_SPK_OP_EN_MASK) >> WM8960_CLASSD1_SPK_OP_EN_SHIFT) + +/* Bitfield definition for register: CLASSD3 */ +/* + * DCGAIN (RW) + * + * DC Speaker Boost (Boosts speaker DC output + * level by up to 1.8 x on left and right channels) + * 000 = 1.00x boost (+0dB) + * 001 = 1.27x boost (+2.1dB) + * 010 = 1.40x boost (+2.9dB) + * 011 = 1.52x boost (+3.6dB) + * 100 = 1.67x boost (+4.5dB) + * 101 = 1.8x boost (+5.1dB) + * 110 to 111 = Reserved + */ +#define WM8960_CLASSD3_DCGAIN_MASK (0x38U) +#define WM8960_CLASSD3_DCGAIN_SHIFT (3U) +#define WM8960_CLASSD3_DCGAIN_SET(x) (((uint16_t)(x) << WM8960_CLASSD3_DCGAIN_SHIFT) & WM8960_CLASSD3_DCGAIN_MASK) +#define WM8960_CLASSD3_DCGAIN_GET(x) (((uint16_t)(x) & WM8960_CLASSD3_DCGAIN_MASK) >> WM8960_CLASSD3_DCGAIN_SHIFT) + +/* + * ACGAIN (RW) + * + * AC Speaker Boost (Boosts speaker AC output + * signal by up to 1.8 x on left and right channels) + * 000 = 1.00x boost (+0dB) + * 001 = 1.27x boost (+2.1dB) + * 010 = 1.40x boost (+2.9dB) + * 011 = 1.52x boost (+3.6dB) + * 100 = 1.67x boost (+4.5dB) + * 101 = 1.8x boost (+5.1dB) + * 110 to 111 = Reserved + */ +#define WM8960_CLASSD3_ACGAIN_MASK (0x7U) +#define WM8960_CLASSD3_ACGAIN_SHIFT (0U) +#define WM8960_CLASSD3_ACGAIN_SET(x) (((uint16_t)(x) << WM8960_CLASSD3_ACGAIN_SHIFT) & WM8960_CLASSD3_ACGAIN_MASK) +#define WM8960_CLASSD3_ACGAIN_GET(x) (((uint16_t)(x) & WM8960_CLASSD3_ACGAIN_MASK) >> WM8960_CLASSD3_ACGAIN_SHIFT) + +/* Bitfield definition for register: PLL1 */ +/* + * OPCLKDIV (RW) + * + * SYSCLK Output to GPIO Clock Division ratio + * 000 = SYSCLK + * 001 = SYSCLK / 2 + * 010 = SYSCLK / 3 + * 011 = SYSCLK / 4 + * 100 = SYSCLK / 5.5 + * 101 = SYSCLK / 6 + */ +#define WM8960_PLL1_OPCLKDIV_MASK (0x1C0U) +#define WM8960_PLL1_OPCLKDIV_SHIFT (6U) +#define WM8960_PLL1_OPCLKDIV_SET(x) (((uint16_t)(x) << WM8960_PLL1_OPCLKDIV_SHIFT) & WM8960_PLL1_OPCLKDIV_MASK) +#define WM8960_PLL1_OPCLKDIV_GET(x) (((uint16_t)(x) & WM8960_PLL1_OPCLKDIV_MASK) >> WM8960_PLL1_OPCLKDIV_SHIFT) + +/* + * SDM (RW) + * + * Enable Integer Mode + * 0 = Integer mode + * 1 = Fractional mode + */ +#define WM8960_PLL1_SDM_MASK (0x20U) +#define WM8960_PLL1_SDM_SHIFT (5U) +#define WM8960_PLL1_SDM_SET(x) (((uint16_t)(x) << WM8960_PLL1_SDM_SHIFT) & WM8960_PLL1_SDM_MASK) +#define WM8960_PLL1_SDM_GET(x) (((uint16_t)(x) & WM8960_PLL1_SDM_MASK) >> WM8960_PLL1_SDM_SHIFT) + +/* + * PLLPRESCALE (RW) + * + * Divide MCLK by 2 before input to PLL + * 0 = Divide by 1 + * 1 = Divide by 2 + */ +#define WM8960_PLL1_PLLPRESCALE_MASK (0x10U) +#define WM8960_PLL1_PLLPRESCALE_SHIFT (4U) +#define WM8960_PLL1_PLLPRESCALE_SET(x) (((uint16_t)(x) << WM8960_PLL1_PLLPRESCALE_SHIFT) & WM8960_PLL1_PLLPRESCALE_MASK) +#define WM8960_PLL1_PLLPRESCALE_GET(x) (((uint16_t)(x) & WM8960_PLL1_PLLPRESCALE_MASK) >> WM8960_PLL1_PLLPRESCALE_SHIFT) + +/* + * PLLN (RW) + * + * Integer (N) part of PLL input/output frequency + * ratio. Use values greater than 5 and less than 13 + */ +#define WM8960_PLL1_PLLN_MASK (0xFU) +#define WM8960_PLL1_PLLN_SHIFT (0U) +#define WM8960_PLL1_PLLN_SET(x) (((uint16_t)(x) << WM8960_PLL1_PLLN_SHIFT) & WM8960_PLL1_PLLN_MASK) +#define WM8960_PLL1_PLLN_GET(x) (((uint16_t)(x) & WM8960_PLL1_PLLN_MASK) >> WM8960_PLL1_PLLN_SHIFT) + +/* Bitfield definition for register: PLL2 */ +/* + * PLLK (RW) + * + * Fractional (K) part of PLL1 input/output + * frequency ratio (treat as one 24-digit binary number). + */ +#define WM8960_PLL2_PLLK_MASK (0xFFU) +#define WM8960_PLL2_PLLK_SHIFT (0U) +#define WM8960_PLL2_PLLK_SET(x) (((uint16_t)(x) << WM8960_PLL2_PLLK_SHIFT) & WM8960_PLL2_PLLK_MASK) +#define WM8960_PLL2_PLLK_GET(x) (((uint16_t)(x) & WM8960_PLL2_PLLK_MASK) >> WM8960_PLL2_PLLK_SHIFT) + +/* Bitfield definition for register: PLL3 */ +/* + * PLLK (RW) + * + * Fractional (K) part of PLL1 input/output + * frequency ratio (treat as one 24-digit binary number). + */ +#define WM8960_PLL3_PLLK_MASK (0xFFU) +#define WM8960_PLL3_PLLK_SHIFT (0U) +#define WM8960_PLL3_PLLK_SET(x) (((uint16_t)(x) << WM8960_PLL3_PLLK_SHIFT) & WM8960_PLL3_PLLK_MASK) +#define WM8960_PLL3_PLLK_GET(x) (((uint16_t)(x) & WM8960_PLL3_PLLK_MASK) >> WM8960_PLL3_PLLK_SHIFT) + +/* Bitfield definition for register: PLL4 */ +/* + * PLLK (RW) + * + * Fractional (K) part of PLL1 input/output + * frequency ratio (treat as one 24-digit binary number). + */ +#define WM8960_PLL4_PLLK_MASK (0xFFU) +#define WM8960_PLL4_PLLK_SHIFT (0U) +#define WM8960_PLL4_PLLK_SET(x) (((uint16_t)(x) << WM8960_PLL4_PLLK_SHIFT) & WM8960_PLL4_PLLK_MASK) +#define WM8960_PLL4_PLLK_GET(x) (((uint16_t)(x) & WM8960_PLL4_PLLK_MASK) >> WM8960_PLL4_PLLK_SHIFT) + + +#endif /* _HPM_WM8960_REG_H_ */ diff --git a/bsp/hpmicro/hpm6800evk/board/linker_scripts/flash_rtt.ld b/bsp/hpmicro/hpm6800evk/board/linker_scripts/flash_rtt.ld new file mode 100644 index 00000000000..a5ba14d4fb6 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/board/linker_scripts/flash_rtt.ld @@ -0,0 +1,309 @@ +/* + * Copyright 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 128K; +FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 256K; +SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 256M; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE + ILM (wx) : ORIGIN = 0, LENGTH = 256K + DLM (w) : ORIGIN = 0x80000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x01200000, LENGTH = 256K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x01240000, LENGTH = NONCACHEABLE_SIZE + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF4130000, LENGTH = 16k +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .fast : AT(etext + __data_end__ - __tdata_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + + /* RT-Thread Core Start */ + KEEP(*context_gcc.o(.text* .rodata*)) + KEEP(*port*.o (.text .text* .rodata .rodata*)) + KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) + KEEP(*trap_common.o (.text .text* .rodata .rodata*)) + KEEP(*irq.o (.text .text* .rodata .rodata*)) + KEEP(*clock.o (.text .text* .rodata .rodata*)) + KEEP(*kservice.o (.text .text* .rodata .rodata*)) + KEEP(*scheduler.o (.text .text* .rodata .rodata*)) + KEEP(*trap*.o (.text .text* .rodata .rodata*)) + KEEP(*idle.o (.text .text* .rodata .rodata*)) + KEEP(*ipc.o (.text .text* .rodata .rodata*)) + KEEP(*thread.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*timer.o (.text .text* .rodata .rodata*)) + KEEP(*mem.o (.text .text* .rodata .rodata*)) + KEEP(*mempool.o (.text .text* .rodata .rodata*)) + /* RT-Thread Core End */ + + /* HPMicro Driver Wrapper */ + KEEP(*drv_*.o (.text .text* .rodata .rodata*)) + + . = ALIGN(8); + __ramfunc_end__ = .; + } > ILM + + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + /* Note: the .tbss and .tdata section should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > DLM + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > DLM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + + .heap(NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE( __rt_rvstack = . ); + } > AXI_SRAM + + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + + .sdram (NOLOAD) : { + . = ALIGN(8); + __sdram_start__ = .; + __sdram_end__ = .; + } > SDRAM +} diff --git a/bsp/hpmicro/hpm6800evk/board/linker_scripts/flash_rtt_enet.ld b/bsp/hpmicro/hpm6800evk/board/linker_scripts/flash_rtt_enet.ld new file mode 100644 index 00000000000..5b4b3188800 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/board/linker_scripts/flash_rtt_enet.ld @@ -0,0 +1,330 @@ +/* + * Copyright 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 128K; +FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 128K; +SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 256M; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE + ILM (wx) : ORIGIN = 0, LENGTH = 256K + DLM (w) : ORIGIN = 0x80000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x1200000, LENGTH = 384K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x01260000, LENGTH = NONCACHEABLE_SIZE + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF4130000, LENGTH = 16k +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + + . = ALIGN(8); + __vector_ram_end__ = .; + } > AXI_SRAM + + .fast : AT(etext + __data_end__ - __tdata_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + + /* RT-Thread Core Start */ + KEEP(*context_gcc.o(.text* .rodata*)) + KEEP(*port*.o (.text .text* .rodata .rodata*)) + KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) + KEEP(*trap_common.o (.text .text* .rodata .rodata*)) + KEEP(*irq.o (.text .text* .rodata .rodata*)) + KEEP(*clock.o (.text .text* .rodata .rodata*)) + KEEP(*kservice.o (.text .text* .rodata .rodata*)) + KEEP(*scheduler*.o (.text .text* .rodata .rodata*)) + KEEP(*trap*.o (.text .text* .rodata .rodata*)) + KEEP(*idle.o (.text .text* .rodata .rodata*)) + KEEP(*ipc.o (.text .text* .rodata .rodata*)) + KEEP(*slab.o (.text .text* .rodata .rodata*)) + KEEP(*thread.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*timer.o (.text .text* .rodata .rodata*)) + KEEP(*mem.o (.text .text* .rodata .rodata*)) + KEEP(*memheap.o (.text .text* .rodata .rodata*)) + KEEP(*mempool.o (.text .text* .rodata .rodata*)) + /* RT-Thread Core End */ + + /* HPMicro Driver Wrapper */ + KEEP(*drv_*.o (.text .text* .rodata .rodata*)) + KEEP(*api_lib*.o (.text .text* .rodata .rodata*)) + KEEP(*api_msg*.o (.text .text* .rodata .rodata*)) + KEEP(*if_api*.o (.text .text* .rodata .rodata*)) + KEEP(*netbuf*.o (.text .text* .rodata .rodata*)) + KEEP(*netdb*.o (.text .text* .rodata .rodata*)) + KEEP(*netifapi*.o (.text .text* .rodata .rodata*)) + KEEP(*sockets*.o (.text .text* .rodata .rodata*)) + KEEP(*tcpip*.o (.text .text* .rodata .rodata*)) + KEEP(*inet_chksum*.o (.text .text* .rodata .rodata*)) + KEEP(*ip*.o (.text .text* .rodata .rodata*)) + KEEP(*memp*.o (.text .text* .rodata .rodata*)) + KEEP(*netif*.o (.text .text* .rodata .rodata*)) + KEEP(*pbuf*.o (.text .text* .rodata .rodata*)) + KEEP(*tcp_in*.o (.text .text* .rodata .rodata*)) + KEEP(*tcp_out*.o (.text .text* .rodata .rodata*)) + KEEP(*tcp*.o (.text .text* .rodata .rodata*)) + KEEP(*ethernet*.o (.text .text* .rodata .rodata*)) + KEEP(*ethernetif*.o (.text .text* .rodata .rodata*)) + + . = ALIGN(8); + __ramfunc_end__ = .; + } > AXI_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + /* Note: the .tbss and .tdata section should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > AXI_SRAM + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > AXI_SRAM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + + .heap(NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE( __rt_rvstack = . ); + } > AXI_SRAM + + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + + .sdram (NOLOAD) : { + . = ALIGN(8); + __sdram_start__ = .; + . += SDRAM_SIZE; + __sdram_end__ = .; + } > SDRAM +} diff --git a/bsp/hpmicro/hpm6800evk/board/linker_scripts/flash_sdram_rtt.ld b/bsp/hpmicro/hpm6800evk/board/linker_scripts/flash_sdram_rtt.ld new file mode 100644 index 00000000000..0a9399843e8 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/board/linker_scripts/flash_sdram_rtt.ld @@ -0,0 +1,303 @@ +/* + * Copyright 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 8M; +FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; +SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 256M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 32M; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE + ILM (wx) : ORIGIN = 0, LENGTH = 256K + DLM (w) : ORIGIN = 0x80000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x1200000, LENGTH = 512K + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE + NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF4130000, LENGTH = 16k +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .fast : AT(etext + __data_end__ - __tdata_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + + /* RT-Thread Core Start */ + KEEP(*context_gcc.o(.text* .rodata*)) + KEEP(*port*.o (.text .text* .rodata .rodata*)) + KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) + KEEP(*trap_common.o (.text .text* .rodata .rodata*)) + KEEP(*irq.o (.text .text* .rodata .rodata*)) + KEEP(*clock.o (.text .text* .rodata .rodata*)) + KEEP(*kservice.o (.text .text* .rodata .rodata*)) + KEEP(*scheduler.o (.text .text* .rodata .rodata*)) + KEEP(*trap*.o (.text .text* .rodata .rodata*)) + KEEP(*idle.o (.text .text* .rodata .rodata*)) + KEEP(*ipc.o (.text .text* .rodata .rodata*)) + KEEP(*thread.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*timer.o (.text .text* .rodata .rodata*)) + KEEP(*mem.o (.text .text* .rodata .rodata*)) + KEEP(*mempool.o (.text .text* .rodata .rodata*)) + /* RT-Thread Core End */ + + /* HPMicro Driver Wrapper */ + KEEP(*drv_*.o (.text .text* .rodata .rodata*)) + + . = ALIGN(8); + __ramfunc_end__ = .; + } > ILM + + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > DLM + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > DLM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + + .heap(NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > SDRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > SDRAM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE( __rt_rvstack = . ); + } > AXI_SRAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); +} diff --git a/bsp/hpmicro/hpm6800evk/board/linker_scripts/ram_rtt.ld b/bsp/hpmicro/hpm6800evk/board/linker_scripts/ram_rtt.ld new file mode 100644 index 00000000000..2ffd29d0b27 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/board/linker_scripts/ram_rtt.ld @@ -0,0 +1,261 @@ +/* + * Copyright 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 128K; +SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 256M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 64K; + +MEMORY +{ + ILM (wx) : ORIGIN = 0, LENGTH = 256K + DLM (w) : ORIGIN = 0x80000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x01200000, LENGTH = 448K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x01270000, LENGTH = NONCACHEABLE_SIZE + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF4130000, LENGTH = 16k +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > AXI_SRAM + + .vectors : { + . = ALIGN(8); + KEEP(*(.isr_vector)) + KEEP(*(.vector_table)) + . = ALIGN(8); + } > AXI_SRAM + + .text : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + *(FalPartTable) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + } > AXI_SRAM + + .rel : { + KEEP(*(.rel*)) + } > AXI_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + /* Note: .tbss and .tdata should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > DLM + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > DLM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + + .fast : AT(etext + __data_end__ - __tdata_start__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > AXI_SRAM + + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE (__rt_rvstack = .); + } > DLM + + .framebuffer (NOLOAD) : { + KEEP(*(.framebuffer)) + } > AXI_SRAM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + + } > AXI_SRAM + + .sdram (NOLOAD) : { + . = ALIGN(8); + __sdram_start__ = .; + . += SDRAM_SIZE; + __sdram_end__ = .; + } > SDRAM +} diff --git a/bsp/hpmicro/hpm6800evk/board/linker_scripts/ram_sdram_rtt.ld b/bsp/hpmicro/hpm6800evk/board/linker_scripts/ram_sdram_rtt.ld new file mode 100644 index 00000000000..d0d07958ccb --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/board/linker_scripts/ram_sdram_rtt.ld @@ -0,0 +1,254 @@ +/* + * Copyright 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K; +SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 256M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 32M; + +MEMORY +{ + ILM (wx) : ORIGIN = 0, LENGTH = 256K + DLM (w) : ORIGIN = 0x80000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x01200000, LENGTH = 512K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF4130000, LENGTH = 16k +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > AXI_SRAM + + .vectors : { + . = ALIGN(8); + KEEP(*(.isr_vector)) + KEEP(*(.vector_table)) + . = ALIGN(8); + } > AXI_SRAM + + .text : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + *(FalPartTable) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + } > AXI_SRAM + + .rel : { + KEEP(*(.rel*)) + } > AXI_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + /* Note: .tbss and .tdata should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > AXI_SRAM + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > AXI_SRAM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + + .fast : AT(etext + __data_end__ - __tdata_start__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > AXI_SRAM + + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE (__rt_rvstack = .); + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + KEEP(*(.framebuffer)) + } > SDRAM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + + } > SDRAM +} diff --git a/bsp/hpmicro/hpm6800evk/board/pinmux.c b/bsp/hpmicro/hpm6800evk/board/pinmux.c new file mode 100644 index 00000000000..203c6756d63 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/board/pinmux.c @@ -0,0 +1,549 @@ +/* + * Copyright (c) 2023 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* + * Note: + * PY and PZ IOs: if any SOC pin function needs to be routed to these IOs, + * besides of IOC, PIOC/BIOC needs to be configured SOC_GPIO_X_xx, so that + * expected SoC function can be enabled on these IOs. + * + */ +#include "board.h" + +void init_uart_pins(UART_Type *ptr) +{ + if (ptr == HPM_UART0) { + HPM_IOC->PAD[IOC_PAD_PA00].FUNC_CTL = IOC_PA00_FUNC_CTL_UART0_TXD; + HPM_IOC->PAD[IOC_PAD_PA01].FUNC_CTL = IOC_PA01_FUNC_CTL_UART0_RXD; + } else if (ptr == HPM_UART3) { + HPM_IOC->PAD[IOC_PAD_PE14].FUNC_CTL = IOC_PE14_FUNC_CTL_UART3_RXD; + HPM_IOC->PAD[IOC_PAD_PE15].FUNC_CTL = IOC_PE15_FUNC_CTL_UART3_TXD; + } else if (ptr == HPM_PUART) { + HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_PURT_TXD; + HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_PURT_RXD; + } else { + ; + } +} + +/* for uart_lin case, need to configure pin as gpio to sent break signal */ +void init_uart_pin_as_gpio(UART_Type *ptr) +{ + /* pull-up */ + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + + if (ptr == HPM_UART3) { + HPM_IOC->PAD[IOC_PAD_PE14].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PE15].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PE14].FUNC_CTL = IOC_PE14_FUNC_CTL_GPIO_E_14; + HPM_IOC->PAD[IOC_PAD_PE15].FUNC_CTL = IOC_PE15_FUNC_CTL_GPIO_E_15; + } +} + +void init_cap_pins(void) +{ + /* CAP_INT */ + HPM_IOC->PAD[IOC_PAD_PY06].PAD_CTL = IOC_PAD_PAD_CTL_PE_MASK; + HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_GPIO_Y_06; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = PIOC_PY06_FUNC_CTL_SOC_PY_06; + /* CAP_RST */ + HPM_IOC->PAD[IOC_PAD_PY07].PAD_CTL = IOC_PAD_PAD_CTL_PE_MASK; + HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_GPIO_Y_07; + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = PIOC_PY07_FUNC_CTL_SOC_PY_07; +} + +void init_i2c_pins_as_gpio(I2C_Type *ptr) +{ + if (ptr == HPM_I2C3) { + HPM_IOC->PAD[IOC_PAD_PD28].FUNC_CTL = IOC_PD28_FUNC_CTL_GPIO_D_28; + HPM_IOC->PAD[IOC_PAD_PD29].FUNC_CTL = IOC_PD29_FUNC_CTL_GPIO_D_29; + } else if (ptr == HPM_I2C1) { + HPM_IOC->PAD[IOC_PAD_PE12].FUNC_CTL = IOC_PE12_FUNC_CTL_GPIO_E_12; + HPM_IOC->PAD[IOC_PAD_PE13].FUNC_CTL = IOC_PE13_FUNC_CTL_GPIO_E_13; + } else if (ptr == HPM_I2C0) { + HPM_IOC->PAD[IOC_PAD_PF09].FUNC_CTL = IOC_PF09_FUNC_CTL_GPIO_F_09; + HPM_IOC->PAD[IOC_PAD_PF08].FUNC_CTL = IOC_PF08_FUNC_CTL_GPIO_F_08; + } else { + ; + } +} + +void init_i2c_pins(I2C_Type *ptr) +{ + if (ptr == HPM_I2C3) { /* Audio */ + HPM_IOC->PAD[IOC_PAD_PD28].FUNC_CTL = IOC_PD28_FUNC_CTL_I2C3_SDA + | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PD29].FUNC_CTL = IOC_PD29_FUNC_CTL_I2C3_SCL + | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PD28].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; + HPM_IOC->PAD[IOC_PAD_PD29].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; + } else if (ptr == HPM_I2C1) { /* Storage */ + HPM_IOC->PAD[IOC_PAD_PE12].FUNC_CTL = IOC_PE12_FUNC_CTL_I2C1_SDA + | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PE13].FUNC_CTL = IOC_PE13_FUNC_CTL_I2C1_SCL + | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PE12].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; + HPM_IOC->PAD[IOC_PAD_PE13].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; + } else if (ptr == HPM_I2C0) { /* Touch Panel/ Camera */ + HPM_IOC->PAD[IOC_PAD_PF09].FUNC_CTL = IOC_PF09_FUNC_CTL_I2C0_SDA + | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PF08].FUNC_CTL = IOC_PF08_FUNC_CTL_I2C0_SCL + | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PF09].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; + HPM_IOC->PAD[IOC_PAD_PF08].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; + } else { + ; + } +} + +void init_cam_pins(void) +{ + /* configure rst pin function */ + HPM_IOC->PAD[IOC_PAD_PA22].FUNC_CTL = IOC_PA22_FUNC_CTL_GPIO_A_22; + /* configure pwdn pin function */ + HPM_PIOC->PAD[IOC_PAD_PA21].FUNC_CTL = IOC_PA21_FUNC_CTL_GPIO_A_21; + + HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_CAM0_XCLK; + HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_CAM0_PIXCLK; + HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_CAM0_VSYNC; + HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_CAM0_HSYNC; + HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_CAM0_D_2; + HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_CAM0_D_3; + HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_CAM0_D_4; + HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PA24_FUNC_CTL_CAM0_D_5; + HPM_IOC->PAD[IOC_PAD_PB16].FUNC_CTL = IOC_PB16_FUNC_CTL_CAM0_D_6; + HPM_IOC->PAD[IOC_PAD_PB17].FUNC_CTL = IOC_PB17_FUNC_CTL_CAM0_D_7; + HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_CAM0_D_8; + HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_CAM0_D_9; +} + +void init_cam_mipi_csi_pins(void) +{ + /* configure rst pin function */ + HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PB00_FUNC_CTL_GPIO_B_00; + HPM_IOC->PAD[IOC_PAD_PB00].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; +} + +void init_sdm_pins(void) +{ + +} + +void init_gpio_pins(void) +{ + /* configure pad setting: pull enable and pull up, schmitt trigger enable */ + /* enable schmitt trigger to eliminate jitter of pin used as button */ + HPM_IOC->PAD[IOC_PAD_PF06].FUNC_CTL = IOC_PF06_FUNC_CTL_GPIO_F_06; + HPM_IOC->PAD[IOC_PAD_PF06].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_MASK | IOC_PAD_PAD_CTL_PRS_SET(11); + + HPM_IOC->PAD[IOC_PAD_PF07].FUNC_CTL = IOC_PF07_FUNC_CTL_GPIO_F_07; + HPM_IOC->PAD[IOC_PAD_PF07].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_MASK | IOC_PAD_PAD_CTL_PRS_SET(11); +} + +void init_spi_pins(SPI_Type *ptr) +{ + if (ptr == HPM_SPI3) { + HPM_IOC->PAD[IOC_PAD_PE05].FUNC_CTL = IOC_PE05_FUNC_CTL_SPI3_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + HPM_IOC->PAD[IOC_PAD_PE06].FUNC_CTL = IOC_PE06_FUNC_CTL_SPI3_MISO; + HPM_IOC->PAD[IOC_PAD_PE07].FUNC_CTL = IOC_PE07_FUNC_CTL_SPI3_MOSI; + HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_SPI3_CS_0; + } +} + +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + if (ptr == HPM_SPI3) { + HPM_IOC->PAD[IOC_PAD_PE05].FUNC_CTL = IOC_PE05_FUNC_CTL_SPI3_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + HPM_IOC->PAD[IOC_PAD_PE06].FUNC_CTL = IOC_PE06_FUNC_CTL_SPI3_MISO; + HPM_IOC->PAD[IOC_PAD_PE07].FUNC_CTL = IOC_PE07_FUNC_CTL_SPI3_MOSI; + HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_GPIO_E_04; + } +} + +void init_pins(void) +{ +#ifdef BOARD_CONSOLE_UART_BASE + init_uart_pins(BOARD_CONSOLE_UART_BASE); +#endif +} + +void init_gptmr_pins(GPTMR_Type *ptr) +{ + if (ptr == HPM_GPTMR2) { + HPM_IOC->PAD[IOC_PAD_PE22].FUNC_CTL = IOC_PE22_FUNC_CTL_GPTMR2_CAPT_0; + HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PE23_FUNC_CTL_GPTMR2_COMP_0; + HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PE24_FUNC_CTL_GPTMR2_COMP_1; + } +} + +void init_butn_pins(void) +{ + +} + +void init_acmp_pins(void) +{ + +} + +void init_sdxc_cmd_pin(SDXC_Type *ptr, bool open_drain, bool is_1v8) +{ + (void) is_1v8; + /* Pull-up */ + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PRS_SET(2) | \ + IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_DS_SET(6); + if (ptr == HPM_SDXC0) { + if (open_drain) { + pad_ctl |= IOC_PAD_PAD_CTL_OD_MASK; + } + HPM_IOC->PAD[IOC_PAD_PC01].FUNC_CTL = IOC_PC01_FUNC_CTL_SDC0_CMD | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + HPM_IOC->PAD[IOC_PAD_PC01].PAD_CTL = pad_ctl; + } + if (ptr == HPM_SDXC1) { + HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_SDC1_CMD | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + HPM_IOC->PAD[IOC_PAD_PC13].PAD_CTL = pad_ctl; + } +} + + +void init_sdxc_ds_pin(SDXC_Type *ptr) +{ +#define SDXC_DS_PIN_SETTING (IOC_PAD_PAD_CTL_PE_SET(1) \ + | IOC_PAD_PAD_CTL_SPD_SET(3) \ + | IOC_PAD_PAD_CTL_SR_SET(1)) + if (ptr == HPM_SDXC0) { + HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PC00_FUNC_CTL_SDC0_DS; + HPM_IOC->PAD[IOC_PAD_PC00].PAD_CTL = SDXC_DS_PIN_SETTING; + } +} + +void init_sdxc_pwr_pin(SDXC_Type *ptr, bool as_gpio) +{ + if (ptr == HPM_SDXC1) { + if (as_gpio) { + /* SD_PWR */ + HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PD07_FUNC_CTL_GPIO_D_07; + HPM_IOC->PAD[IOC_PAD_PD07].PAD_CTL = + IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_DS_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_GPIO0->OE[GPIO_OE_GPIOD].SET = 1UL << 7; + } + } +} + +void init_sdxc_vsel_pin(SDXC_Type *ptr, bool as_gpio) +{ + if (ptr == HPM_SDXC1) { + if (as_gpio) { + /* VSEL */ + HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PD12_FUNC_CTL_GPIO_D_12; + HPM_IOC->PAD[IOC_PAD_PD12].PAD_CTL = + IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_DS_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_GPIO0->OE[GPIO_OE_GPIOD].SET = 1UL << 12; + } + } +} + +void init_sdxc_cd_pin(SDXC_Type *ptr, bool as_gpio) +{ + if (ptr == HPM_SDXC1) { + if (as_gpio) { + /* CDN */ + HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PD05_FUNC_CTL_GPIO_D_05; + HPM_IOC->PAD[IOC_PAD_PD05].PAD_CTL = + IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_DS_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_GPIO0->OE[GPIO_OE_GPIOD].CLEAR = 1UL << 5; + } + } +} + +void init_sdxc_clk_data_pins(SDXC_Type *ptr, uint32_t width, bool is_1v8) +{ + (void) is_1v8; +#define SDXC_PIN_SETTING_COMMON (IOC_PAD_PAD_CTL_PE_SET(1) \ + | IOC_PAD_PAD_CTL_SPD_SET(3) \ + | IOC_PAD_PAD_CTL_SR_SET(1)) +#define SDXC_PIN_SETTING (IOC_PAD_PAD_CTL_DS_SET(7) \ + | SDXC_PIN_SETTING_COMMON \ + | IOC_PAD_PAD_CTL_PS_SET(1) \ + | IOC_PAD_PAD_CTL_PRS_SET(3)) + + uint32_t pad_ctl = SDXC_PIN_SETTING; + if (ptr == HPM_SDXC0) { + /*CLK*/ + HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PC02_FUNC_CTL_SDC0_CLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + HPM_IOC->PAD[IOC_PAD_PC02].PAD_CTL = pad_ctl; + + /* DAT0-DATA7 */ + HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_SDC0_DATA_0; + HPM_IOC->PAD[IOC_PAD_PC06].PAD_CTL = pad_ctl; + if ((width == 4) || (width == 8)) { + HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PC03_FUNC_CTL_SDC0_DATA_1; + HPM_IOC->PAD[IOC_PAD_PC03].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PC04_FUNC_CTL_SDC0_DATA_2; + HPM_IOC->PAD[IOC_PAD_PC04].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_SDC0_DATA_3; + HPM_IOC->PAD[IOC_PAD_PC05].PAD_CTL = pad_ctl; + } + if (width == 8) { + HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_SDC0_DATA_4; + HPM_IOC->PAD[IOC_PAD_PC08].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PC09_FUNC_CTL_SDC0_DATA_5; + HPM_IOC->PAD[IOC_PAD_PC09].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_SDC0_DATA_6; + HPM_IOC->PAD[IOC_PAD_PC10].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_SDC0_DATA_7; + HPM_IOC->PAD[IOC_PAD_PC11].PAD_CTL = pad_ctl; + } + } + if (ptr == HPM_SDXC1) { + /*CLK*/ + HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PC16_FUNC_CTL_SDC1_CLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + HPM_IOC->PAD[IOC_PAD_PC16].PAD_CTL = pad_ctl; + + /* DAT0 -DATA3 */ + HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PC17_FUNC_CTL_SDC1_DATA_0; + HPM_IOC->PAD[IOC_PAD_PC17].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_SDC1_DATA_1; + HPM_IOC->PAD[IOC_PAD_PC15].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PC14_FUNC_CTL_SDC1_DATA_2; + HPM_IOC->PAD[IOC_PAD_PC14].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_SDC1_DATA_3; + HPM_IOC->PAD[IOC_PAD_PC12].PAD_CTL = pad_ctl; + } +} + + + +void init_usb_pins(void) +{ + /* USB0_ID */ + HPM_IOC->PAD[IOC_PAD_PF04].FUNC_CTL = IOC_PF04_FUNC_CTL_USB0_ID; + /* USB0_OC */ + HPM_IOC->PAD[IOC_PAD_PF03].FUNC_CTL = IOC_PF03_FUNC_CTL_USB0_OC; + /* USB0_PWR */ + HPM_IOC->PAD[IOC_PAD_PF00].FUNC_CTL = IOC_PF00_FUNC_CTL_USB0_PWR; +} + +void init_can_pins(MCAN_Type *ptr) +{ + if (ptr == HPM_MCAN3) { + HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = IOC_PD15_FUNC_CTL_MCAN3_TXD; + HPM_IOC->PAD[IOC_PAD_PD14].FUNC_CTL = IOC_PD14_FUNC_CTL_MCAN3_RXD; + HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PD13_FUNC_CTL_MCAN3_STBY; + } +} + +void init_clk_obs_pins(void) +{ + /* HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_SYSCTL_CLK_OBS_0; */ +} + +void init_led_pins_as_gpio(void) +{ + HPM_IOC->PAD[IOC_PAD_PF01].FUNC_CTL = IOC_PF01_FUNC_CTL_GPIO_F_01; + HPM_IOC->PAD[IOC_PAD_PF02].FUNC_CTL = IOC_PF02_FUNC_CTL_GPIO_F_02; + HPM_IOC->PAD[IOC_PAD_PF05].FUNC_CTL = IOC_PF05_FUNC_CTL_GPIO_F_05; +} + +void init_mipi_lvds_tx_phy0_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /*REXT*/ +} + +void init_mipi_lvds_tx_phy1_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB28].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB31].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /*REXT*/ +} + +void init_mipi_lvds_rx_phy0_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /*REXT*/ +} + +void init_mipi_lvds_rx_phy1_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PB16].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB17].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /*REXT*/ +} + +void init_lcd_mipi_ctl_pins(void) +{ + /* RESET */ + HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PB01_FUNC_CTL_GPIO_B_01; +} + +void init_lcd_lvds_double_ctl_pins(void) +{ + /* RESET */ + HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_GPIO_A_31; +} + +void init_lcd_lvds_single_ctl_pins(void) +{ + /* LED-EN */ + HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_GPIO_A_30; + + /* PWM */ + HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_GPIO_A_31; +} + +void init_lcd_rgb_ctl_pins(void) +{ + /* PWM */ + HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_GPIO_A_09; + /* RST */ + HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_GPIO_A_14; + + HPM_IOC->PAD[IOC_PAD_PY05].PAD_CTL = IOC_PAD_PAD_CTL_PE_MASK; + HPM_IOC->PAD[IOC_PAD_PY05].FUNC_CTL = IOC_PY05_FUNC_CTL_GPIO_Y_05; + HPM_PIOC->PAD[IOC_PAD_PY05].FUNC_CTL = PIOC_PY05_FUNC_CTL_SOC_PY_05; +} + +void init_lcd_rgb_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_DIS0_G_4; + HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_DIS0_G_3; + HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = IOC_PA12_FUNC_CTL_DIS0_G_6; + HPM_IOC->PAD[IOC_PAD_PA13].FUNC_CTL = IOC_PA13_FUNC_CTL_DIS0_G_5; + HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_DIS0_R_3; + HPM_IOC->PAD[IOC_PAD_PA16].FUNC_CTL = IOC_PA16_FUNC_CTL_DIS0_R_5; + HPM_IOC->PAD[IOC_PAD_PA17].FUNC_CTL = IOC_PA17_FUNC_CTL_DIS0_R_4; + HPM_IOC->PAD[IOC_PAD_PA18].FUNC_CTL = IOC_PA18_FUNC_CTL_DIS0_R_7; + HPM_IOC->PAD[IOC_PAD_PA19].FUNC_CTL = IOC_PA19_FUNC_CTL_DIS0_R_6; + HPM_IOC->PAD[IOC_PAD_PA20].FUNC_CTL = IOC_PA20_FUNC_CTL_DIS0_G_2; + HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_DIS0_R_0; + HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_DIS0_R_2; + HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_DIS0_R_1; + + HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PB00_FUNC_CTL_DIS0_G_1; + HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PB01_FUNC_CTL_DIS0_G_0; + HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_DIS0_B_1; + HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_DIS0_B_0; + HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_DIS0_B_2; + HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_DIS0_G_7; + HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_DIS0_B_3; + HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_DIS0_B_4; + HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_DIS0_B_6; + HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_DIS0_B_5; + HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_DIS0_EN; + HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_DIS0_B_7; + HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_DIS0_HSYNC; + HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PB14_FUNC_CTL_DIS0_VSYNC; + + HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_DIS0_CLK; /*A.CLK*/ +} + +void init_i2s_pins(I2S_Type *ptr) +{ + if (ptr == HPM_I2S3) { + HPM_IOC->PAD[IOC_PAD_PD30].FUNC_CTL = IOC_PD30_FUNC_CTL_I2S3_MCLK; + HPM_IOC->PAD[IOC_PAD_PD24].FUNC_CTL = IOC_PD24_FUNC_CTL_I2S3_BCLK; + HPM_IOC->PAD[IOC_PAD_PD25].FUNC_CTL = IOC_PD25_FUNC_CTL_I2S3_FCLK; + HPM_IOC->PAD[IOC_PAD_PD27].FUNC_CTL = IOC_PD27_FUNC_CTL_I2S3_TXD_2; + HPM_IOC->PAD[IOC_PAD_PD23].FUNC_CTL = IOC_PD23_FUNC_CTL_I2S3_RXD_2; + } +} + +void init_dao_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PC31_FUNC_CTL_DAO_LP; + HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PC30_FUNC_CTL_DAO_LN; + HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PD01_FUNC_CTL_DAO_RP; + HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PD00_FUNC_CTL_DAO_RN; +} + +void init_pdm_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PE00].FUNC_CTL = IOC_PE00_FUNC_CTL_PDM0_CLK; + HPM_IOC->PAD[IOC_PAD_PE01].FUNC_CTL = IOC_PE01_FUNC_CTL_PDM0_D_1; +} + +void init_enet_pins(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + HPM_IOC->PAD[IOC_PAD_PD18].FUNC_CTL = IOC_PD18_FUNC_CTL_GPIO_D_18; + + HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PD02_FUNC_CTL_ETH0_MDC; + HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PD03_FUNC_CTL_ETH0_MDIO; + + HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PC29_FUNC_CTL_ETH0_RXD_0; + HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PC28_FUNC_CTL_ETH0_RXD_1; + HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_ETH0_RXD_2; + HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_ETH0_RXD_3; + HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_ETH0_RXCK; + HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_ETH0_RXDV; + + HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PC22_FUNC_CTL_ETH0_TXD_0; + HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_ETH0_TXD_1; + HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_ETH0_TXD_2; + HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PC18_FUNC_CTL_ETH0_TXD_3; + HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PC20_FUNC_CTL_ETH0_TXCK; + HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_ETH0_TXEN; + } +} + +void init_enet_pps_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PD31].FUNC_CTL = IOC_PD31_FUNC_CTL_ETH0_EVTO_0; +} + +void init_adc_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PE16].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PE17].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PE18].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PE19].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PE22].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PE26].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PE27].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PE28].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PE29].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PE30].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PE31].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_tamper_pins(void) +{ + HPM_BIOC->PAD[IOC_PAD_PZ04].FUNC_CTL = BIOC_PZ04_FUNC_CTL_TAMP_PZ_04 | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_BIOC->PAD[IOC_PAD_PZ05].FUNC_CTL = BIOC_PZ05_FUNC_CTL_TAMP_PZ_05; + HPM_BIOC->PAD[IOC_PAD_PZ06].FUNC_CTL = BIOC_PZ06_FUNC_CTL_TAMP_PZ_06; +} diff --git a/bsp/hpmicro/hpm6800evk/board/pinmux.h b/bsp/hpmicro/hpm6800evk/board/pinmux.h new file mode 100644 index 00000000000..e71c1039643 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/board/pinmux.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2023 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PINMUX_H +#define HPM_PINMUX_H + +#ifdef __cplusplus +extern "C" { +#endif +void init_uart_pins(UART_Type *ptr); +void init_uart_pin_as_gpio(UART_Type *ptr); +void init_cap_pins(void); +void init_i2c_pins_as_gpio(I2C_Type *ptr); +void init_i2c_pins(I2C_Type *ptr); +void init_gpio_pins(void); +void init_spi_pins(SPI_Type *ptr); +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); +void init_pins(void); +void init_gptmr_pins(GPTMR_Type *ptr); +void init_hall_trgm_pins(void); +void init_qei_trgm_pins(void); +void init_butn_pins(void); +void init_acmp_pins(void); +void init_adc_pins(void); +void init_usb_pins(void); +void init_can_pins(MCAN_Type *ptr); +void init_i2c_pins_as_gpio(I2C_Type *ptr); +void init_led_pins_as_gpio(void); +void init_cam_pins(void); +void init_cam_mipi_csi_pins(void); +void init_sdm_pins(void); +void init_mipi_lvds_tx_phy0_pin(void); +void init_mipi_lvds_tx_phy1_pin(void); +void init_mipi_lvds_rx_phy0_pin(void); +void init_mipi_lvds_rx_phy1_pin(void); +void init_lcd_mipi_ctl_pins(void); +void init_lcd_lvds_double_ctl_pins(void); +void init_lcd_lvds_single_ctl_pins(void); +void init_lcd_rgb_ctl_pins(void); +void init_lcd_rgb_pins(void); +void init_sdxc_cmd_pin(SDXC_Type *ptr, bool open_drain, bool is_1v8); +void init_sdxc_ds_pin(SDXC_Type *ptr); +void init_sdxc_pwr_pin(SDXC_Type *ptr, bool as_gpio); +void init_sdxc_cd_pin(SDXC_Type *ptr, bool as_gpio); +void init_sdxc_clk_data_pins(SDXC_Type *ptr, uint32_t width, bool is_1v8); +void init_sdxc_vsel_pin(SDXC_Type *ptr, bool as_gpio); +void init_i2s_pins(I2S_Type *ptr); +void init_dao_pins(void); +void init_pdm_pins(void); +void init_enet_pins(ENET_Type *ptr); +void init_enet_pps_pins(void); +void init_adc_pins(void); +void init_tamper_pins(void); + +#ifdef __cplusplus +} +#endif +#endif /* HPM_PINMUX_H */ diff --git a/bsp/hpmicro/hpm6800evk/board/rtt_board.c b/bsp/hpmicro/hpm6800evk/board/rtt_board.c new file mode 100644 index 00000000000..6146ee7df6a --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/board/rtt_board.c @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "board.h" +#include "rtt_board.h" +#include "hpm_uart_drv.h" +#include "hpm_gpio_drv.h" +#include "hpm_mchtmr_drv.h" +#include "hpm_pmp_drv.h" +#include "assert.h" +#include "hpm_clock_drv.h" +#include "hpm_sysctl_drv.h" +#include +#include +#include "hpm_dma_mgr.h" +#include "hpm_mchtmr_drv.h" + +extern int rt_hw_uart_init(void); +void os_tick_config(void); +void rtt_board_init(void); + +void rt_hw_board_init(void) +{ + rtt_board_init(); + + /* Call the RT-Thread Component Board Initialization */ + rt_components_board_init(); +} + +void os_tick_config(void) +{ + sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1); + sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0); + mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND); + enable_mchtmr_irq(); +} + +void rtt_board_init(void) +{ + board_init_clock(); + board_init_console(); + board_init_pmp(); + + dma_mgr_init(); + + /* initialize memory system */ + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); + + /* Configure the OS Tick */ + os_tick_config(); + + /* Initialize the UART driver first, because later driver initialization may require the rt_kprintf */ + rt_hw_uart_init(); + + /* Set console device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +} + +void app_init_led_pins(void) +{ + gpio_set_pin_output(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN); + gpio_set_pin_output(APP_LED1_GPIO_CTRL, APP_LED1_GPIO_INDEX, APP_LED1_GPIO_PIN); + gpio_set_pin_output(APP_LED2_GPIO_CTRL, APP_LED2_GPIO_INDEX, APP_LED2_GPIO_PIN); + + gpio_write_pin(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN, APP_LED_OFF); + gpio_write_pin(APP_LED1_GPIO_CTRL, APP_LED1_GPIO_INDEX, APP_LED1_GPIO_PIN, APP_LED_OFF); + gpio_write_pin(APP_LED2_GPIO_CTRL, APP_LED2_GPIO_INDEX, APP_LED2_GPIO_PIN, APP_LED_OFF); +} + +void app_led_write(uint32_t index, bool state) +{ + switch (index) + { + case 0: + gpio_write_pin(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN, state); + break; + case 1: + gpio_write_pin(APP_LED1_GPIO_CTRL, APP_LED1_GPIO_INDEX, APP_LED1_GPIO_PIN, state); + break; + case 2: + gpio_write_pin(APP_LED2_GPIO_CTRL, APP_LED2_GPIO_INDEX, APP_LED2_GPIO_PIN, state); + break; + default: + /* Suppress the toolchain warnings */ + break; + } +} + +void rt_hw_console_output(const char *str) +{ + while (*str != '\0') + { + uart_send_byte(BOARD_APP_UART_BASE, *str++); + } +} + +void app_init_usb_pins(void) +{ + board_init_usb_pins(); +} + +ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) +{ + HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND; + + rt_tick_increase(); +} + +void rt_hw_cpu_reset(void) +{ + HPM_PPOR->RESET_ENABLE = (1UL << 31); + HPM_PPOR->SOFTWARE_RESET = 1000U; + while(1) { + + } +} + +MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board); diff --git a/bsp/hpmicro/hpm6800evk/board/rtt_board.h b/bsp/hpmicro/hpm6800evk/board/rtt_board.h new file mode 100644 index 00000000000..ebba0c10e39 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/board/rtt_board.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _RTT_BOARD_H +#define _RTT_BOARD_H +#include "hpm_common.h" +#include "hpm_soc.h" + +/* gpio section */ +#define APP_LED0_GPIO_CTRL HPM_GPIO0 +#define APP_LED0_GPIO_INDEX GPIO_DI_GPIOF +#define APP_LED0_GPIO_PIN 1 +#define APP_LED1_GPIO_CTRL HPM_GPIO0 +#define APP_LED1_GPIO_INDEX GPIO_DI_GPIOF +#define APP_LED1_GPIO_PIN 2 +#define APP_LED2_GPIO_CTRL HPM_GPIO0 +#define APP_LED2_GPIO_INDEX GPIO_DI_GPIOF +#define APP_LED2_GPIO_PIN 5 +#define APP_LED_ON (1) +#define APP_LED_OFF (0) + + + +/* mchtimer section */ +#define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL) + +/* CAN section */ +#define BOARD_CAN_NAME "can3" +#define BOARD_CAN_HWFILTER_INDEX (3U) + +/* UART section */ +#define BOARD_UART_NAME "uart3" +#define BOARD_UART_RX_BUFFER_SIZE BSP_UART3_RX_BUFSIZE + +/* eeprom section */ +#define BOARD_EEPROM_I2C_NAME "i2c1" + +#define BOARD_SD_NAME "sd1" +/* audio section */ +#define BOARD_AUDIO_CODEC_I2C_NAME "i2c3" +#define BOARD_AUDIO_CODEC_I2S_NAME "i2s3" + +#define IRQn_PendSV IRQn_DEBUG0 + +/*************************************************************** + * + * RT-Thread related definitions + * + **************************************************************/ +extern unsigned int __heap_start__; +extern unsigned int __heap_end__; + +#define RT_HW_HEAP_BEGIN ((void*)&__heap_start__) +#define RT_HW_HEAP_END ((void*)&__heap_end__) + + +typedef struct { + uint16_t vdd; + uint8_t bus_width; + uint8_t drive_strength; +}sdxc_io_cfg_t; + + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + + +void app_init_led_pins(void); +void app_led_write(uint32_t index, bool state); +void app_init_usb_pins(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _RTT_BOARD_H */ diff --git a/bsp/hpmicro/hpm6800evk/figures/board.png b/bsp/hpmicro/hpm6800evk/figures/board.png new file mode 100644 index 00000000000..94affe2bb06 Binary files /dev/null and b/bsp/hpmicro/hpm6800evk/figures/board.png differ diff --git a/bsp/hpmicro/hpm6800evk/rtconfig.h b/bsp/hpmicro/hpm6800evk/rtconfig.h new file mode 100644 index 00000000000..2a4db1dda7e --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/rtconfig.h @@ -0,0 +1,262 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 1024 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 1024 + +/* kservice optimization */ + + +/* klibc optimization */ + +#define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x50200 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V2 +#define RT_SERIAL_USING_DMA +#define RT_USING_SPI +#define RT_USING_PIN + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + + +/* Memory protection */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* CYW43012 WiFi */ + + +/* BL808 WiFi */ + + +/* CYW43439 WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + +/* sensors drivers */ + + +/* touch drivers */ + + +/* Kendryte SDK */ + + +/* AI packages */ + + +/* Signal Processing and Control Algorithm Packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Arduino libraries */ + + +/* Projects and Demos */ + + +/* Sensors */ + + +/* Display */ + + +/* Timing */ + + +/* Data Processing */ + + +/* Data Storage */ + +/* Communication */ + + +/* Device Control */ + + +/* Other */ + + +/* Signal IO */ + + +/* Uncategorized */ + +/* Hardware Drivers Config */ + +#define SOC_HPM6000 + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART0 +#define BSP_UART0_RX_BUFSIZE 128 +#define BSP_UART0_TX_BUFSIZE 0 +#define BSP_USING_UART3 +#define BSP_UART3_RX_BUFSIZE 1024 +#define BSP_UART3_TX_BUFSIZE 0 + +#endif diff --git a/bsp/hpmicro/hpm6800evk/rtconfig.py b/bsp/hpmicro/hpm6800evk/rtconfig.py new file mode 100644 index 00000000000..0a81fdf1678 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/rtconfig.py @@ -0,0 +1,109 @@ +# Copyright 2021-2023 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +import os +import sys + +# toolchains options +ARCH='risc-v' +CPU='hpmicro' +CHIP_NAME='HPM6880' + +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +# Fallback toolchain info +FALLBACK_TOOLCHAIN_VENDOR='RISC-V' +FALLBACK_TOOLCHAIN_PKG='RISC-V-GCC-RV32' +FALLBACK_TOOLCHAIN_VER='2022-04-12' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +RTT_EXEC_PATH = os.getenv('RTT_EXEC_PATH') +if RTT_EXEC_PATH != None: + folders = RTT_EXEC_PATH.split(os.sep) + # If the `RT-Thread Env` is from the RT-Thread Studio, generate the RTT_EXEC_PATH using `FALLBACK_TOOLCHAIN_INFO` + if 'arm_gcc' in folders and 'platform' in folders: + RTT_EXEC_PATH = '' + for path in folders: + if path != 'platform': + RTT_EXEC_PATH = RTT_EXEC_PATH + path + os.sep + else: + break + RTT_EXEC_PATH = os.path.join(RTT_EXEC_PATH, 'repo', 'Extract', 'ToolChain_Support_Packages', FALLBACK_TOOLCHAIN_VENDOR, FALLBACK_TOOLCHAIN_PKG, FALLBACK_TOOLCHAIN_VER, 'bin') + # Override the 'RTT_RISCV_TOOLCHAIN' only if the `RT-Thread ENV` is from the RT-Thread Studio + if 'platform' in folders: + os.environ['RTT_RISCV_TOOLCHAIN'] = RTT_EXEC_PATH + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler path, for example, GNU RISC-V toolchain, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + if os.getenv('RTT_RISCV_TOOLCHAIN'): + EXEC_PATH = os.getenv('RTT_RISCV_TOOLCHAIN') + else: + EXEC_PATH = r'/opt/riscv-gnu-gcc/bin' +else: + print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL) + +BUILD = 'flash_debug' + +if PLATFORM == 'gcc': + PREFIX = 'riscv32-unknown-elf-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + GDB = PREFIX + 'gdb' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + ARCH_ABI = ' -mcmodel=medlow ' + DEVICE = ARCH_ABI + ' -DUSE_NONVECTOR_MODE=1 ' + ' -ffunction-sections -fdata-sections -fno-common ' + CFLAGS = DEVICE + AFLAGS = CFLAGS + LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections ' + + CPATH = '' + LPATH = '' + + if BUILD == 'ram_debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + LFLAGS += ' -O0' + LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + elif BUILD == 'ram_release': + CFLAGS += ' -O2' + LFLAGS += ' -O2' + LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + elif BUILD == 'flash_debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + LFLAGS += ' -O0' + CFLAGS += ' -DFLASH_XIP=1' + LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + elif BUILD == 'flash_release': + CFLAGS += ' -O2' + LFLAGS += ' -O2' + CFLAGS += ' -DFLASH_XIP=1' + LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + else: + CFLAGS += ' -O2' + LFLAGS += ' -O2' + LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + LFLAGS += ' -T ' + LINKER_FILE + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + + # module setting + CXXFLAGS = CFLAGS + ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' + CFLAGS = CFLAGS + ' -std=gnu11' \ No newline at end of file diff --git a/bsp/hpmicro/hpm6800evk/rtconfig_preinc.h b/bsp/hpmicro/hpm6800evk/rtconfig_preinc.h new file mode 100644 index 00000000000..4894223a97e --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/rtconfig_preinc.h @@ -0,0 +1,13 @@ + +#ifndef RTCONFIG_PREINC_H__ +#define RTCONFIG_PREINC_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread pre-include file */ +#define D45 +#define HAVE_CCONFIG_H +#define HPM6880 +#define RT_USING_NEWLIB +#define __RTTHREAD__ + +#endif /*RTCONFIG_PREINC_H__*/ diff --git a/bsp/hpmicro/hpm6800evk/startup/HPM6880/SConscript b/bsp/hpmicro/hpm6800evk/startup/HPM6880/SConscript new file mode 100644 index 00000000000..a1ec2c8e79f --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/startup/HPM6880/SConscript @@ -0,0 +1,19 @@ +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() + +# add the startup files + +src = Glob('*.c') + +if rtconfig.PLATFORM == 'gcc': + src += [os.path.join('toolchains', 'gcc', 'start.S')] + src += [os.path.join('toolchains', 'gcc', 'port_gcc.S')] + +CPPPATH = [cwd] +CPPDEFINES=['D45', rtconfig.CHIP_NAME] + +group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm6800evk/startup/HPM6880/startup.c b/bsp/hpmicro/hpm6800evk/startup/HPM6880/startup.c new file mode 100644 index 00000000000..b0bab335d52 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/startup/HPM6880/startup.c @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * + */ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" +#include + +void system_init(void); + +extern int entry(void); + +extern void __libc_init_array(void); +extern void __libc_fini_array(void); + +void system_init(void) +{ + disable_global_irq(CSR_MSTATUS_MIE_MASK); + disable_irq_from_intc(); + enable_irq_from_intc(); + enable_global_irq(CSR_MSTATUS_MIE_MASK); +#ifndef CONFIG_NOT_ENABLE_ICACHE + l1c_ic_enable(); +#endif +#ifndef CONFIG_NOT_ENABLE_DCACHE + l1c_dc_enable(); +#endif +} + +__attribute__((weak)) void c_startup(void) +{ + uint32_t i, size; +#ifdef FLASH_XIP + extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; + size = __vector_ram_end__ - __vector_ram_start__; + for (i = 0; i < size; i++) { + *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); + } +#endif + + extern uint8_t __etext[]; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __tbss_start__[], __tbss_end__[]; + extern uint8_t __tdata_start__[], __tdata_end__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + + /* tbss section */ + size = __tbss_end__ - __tbss_start__; + for (i = 0; i < size; i++) { + *(__tbss_start__ + i) = 0; + } + + /* bss section */ + size = __bss_end__ - __bss_start__; + for (i = 0; i < size; i++) { + *(__bss_start__ + i) = 0; + } + + /* noncacheable bss section */ + size = __noncacheable_bss_end__ - __noncacheable_bss_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_bss_start__ + i) = 0; + } + + /* tdata section LMA: etext */ + size = __tdata_end__ - __tdata_start__; + for (i = 0; i < size; i++) { + *(__tdata_start__ + i) = *(__etext + i); + } + + /* data section LMA: etext */ + size = __data_end__ - __data_start__; + for (i = 0; i < size; i++) { + *(__data_start__ + i) = *(__etext + (__tdata_end__ - __tdata_start__) + i); + } + + /* ramfunc section LMA: etext + data length */ + size = __ramfunc_end__ - __ramfunc_start__; + for (i = 0; i < size; i++) { + *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + i); + } + + /* noncacheable init section LMA: etext + data length + ramfunc length */ + size = __noncacheable_init_end__ - __noncacheable_init_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); + } +} + +__attribute__((weak)) int main(void) +{ + while(1); +} + +void reset_handler(void) +{ + /** + * Disable preemptive interrupt + */ + HPM_PLIC->FEATURE = 0; + /* + * Initialize LMA/VMA sections. + * Relocation for any sections that need to be copied from LMA to VMA. + */ + c_startup(); + + /* Call platform specific hardware initialization */ + system_init(); + + /* Do global constructors */ + __libc_init_array(); + + + + /* Entry function */ + entry(); +} + + +__attribute__((weak)) void _init() +{ +} diff --git a/bsp/hpmicro/hpm6800evk/startup/HPM6880/toolchains/gcc/port_gcc.S b/bsp/hpmicro/hpm6800evk/startup/HPM6880/toolchains/gcc/port_gcc.S new file mode 100644 index 00000000000..2708b48e455 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/startup/HPM6880/toolchains/gcc/port_gcc.S @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "cpuport.h" + + .globl rt_hw_do_after_save_above + .type rt_hw_do_after_save_above,@function +rt_hw_do_after_save_above: + addi sp, sp, -4 + STORE ra, 0 * REGBYTES(sp) + + csrr t1, mcause + andi t1, t1, 0x3FF + /* get ISR */ + la t2, trap_entry + jalr t2 + + LOAD ra, 0 * REGBYTES(sp) + addi sp, sp, 4 + ret diff --git a/bsp/hpmicro/hpm6800evk/startup/HPM6880/toolchains/gcc/start.S b/bsp/hpmicro/hpm6800evk/startup/HPM6880/toolchains/gcc/start.S new file mode 100644 index 00000000000..63433e71ae0 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/startup/HPM6880/toolchains/gcc/start.S @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + #include + #include "hpm_csr_regs.h" + .section .start, "ax" + + .global _start + .type _start,@function + +_start: + /* Initialize global pointer */ + .option push + .option norelax + la gp, __global_pointer$ + la tp, __thread_pointer + .option pop + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + +#ifdef INIT_EXT_RAM_FOR_DATA + la t0, _stack_in_dlm + mv sp, t0 + call _init_ext_ram +#endif + + /* Initialize stack pointer */ + la t0, _stack + mv sp, t0 + +#ifdef __nds_execit + /* Initialize EXEC.IT table */ + la t0, _ITB_BASE_ + csrw uitb, t0 +#endif + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + +#ifdef HPM_USING_VECTOR_PREEMPTED_MODE + /* Initial machine trap-vector Base */ + la t0, __vector_table + csrw mtvec, t0 + /* Enable vectored external PLIC interrupt */ + csrsi CSR_MMISC_CTL, 2 +#else + /* Initial machine trap-vector Base */ + la t0, SW_handler + csrw mtvec, t0 + /* Disable vectored external PLIC interrupt */ + csrci CSR_MMISC_CTL, 2 +#endif + + /* System reset handler */ + call reset_handler + + /* Infinite loop, if returned accidently */ +1: j 1b + + .weak nmi_handler +nmi_handler: +1: j 1b + + .global default_irq_handler + .weak default_irq_handler + .align 2 +default_irq_handler: +1: j 1b + + .macro IRQ_HANDLER irq + .weak default_isr_\irq + .set default_isr_\irq, default_irq_handler + .long default_isr_\irq + .endm + +#include "vectors.S" diff --git a/bsp/hpmicro/hpm6800evk/startup/HPM6880/toolchains/gcc/vectors.S b/bsp/hpmicro/hpm6800evk/startup/HPM6880/toolchains/gcc/vectors.S new file mode 100644 index 00000000000..319bd00b272 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/startup/HPM6880/toolchains/gcc/vectors.S @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + .section .vector_table, "a" + .global __vector_table + .align 9 +__vector_table: + .weak default_isr_trap + .set default_isr_trap, SW_handler + .long default_isr_trap + IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_HANDLER 5 /* GPIO0_E IRQ handler */ + IRQ_HANDLER 6 /* GPIO0_F IRQ handler */ + IRQ_HANDLER 7 /* GPIO0_X IRQ handler */ + IRQ_HANDLER 8 /* GPIO0_Y IRQ handler */ + IRQ_HANDLER 9 /* GPIO0_Z IRQ handler */ + IRQ_HANDLER 10 /* CAN0 IRQ handler */ + IRQ_HANDLER 11 /* CAN1 IRQ handler */ + IRQ_HANDLER 12 /* CAN2 IRQ handler */ + IRQ_HANDLER 13 /* CAN3 IRQ handler */ + IRQ_HANDLER 14 /* CAN4 IRQ handler */ + IRQ_HANDLER 15 /* CAN5 IRQ handler */ + IRQ_HANDLER 16 /* CAN6 IRQ handler */ + IRQ_HANDLER 17 /* CAN7 IRQ handler */ + IRQ_HANDLER 18 /* PTPC IRQ handler */ + IRQ_HANDLER 19 /* Reserved */ + IRQ_HANDLER 20 /* Reserved */ + IRQ_HANDLER 21 /* Reserved */ + IRQ_HANDLER 22 /* Reserved */ + IRQ_HANDLER 23 /* Reserved */ + IRQ_HANDLER 24 /* Reserved */ + IRQ_HANDLER 25 /* Reserved */ + IRQ_HANDLER 26 /* Reserved */ + IRQ_HANDLER 27 /* UART0 IRQ handler */ + IRQ_HANDLER 28 /* UART1 IRQ handler */ + IRQ_HANDLER 29 /* UART2 IRQ handler */ + IRQ_HANDLER 30 /* UART3 IRQ handler */ + IRQ_HANDLER 31 /* UART4 IRQ handler */ + IRQ_HANDLER 32 /* UART5 IRQ handler */ + IRQ_HANDLER 33 /* UART6 IRQ handler */ + IRQ_HANDLER 34 /* UART7 IRQ handler */ + IRQ_HANDLER 35 /* I2C0 IRQ handler */ + IRQ_HANDLER 36 /* I2C1 IRQ handler */ + IRQ_HANDLER 37 /* I2C2 IRQ handler */ + IRQ_HANDLER 38 /* I2C3 IRQ handler */ + IRQ_HANDLER 39 /* SPI0 IRQ handler */ + IRQ_HANDLER 40 /* SPI1 IRQ handler */ + IRQ_HANDLER 41 /* SPI2 IRQ handler */ + IRQ_HANDLER 42 /* SPI3 IRQ handler */ + IRQ_HANDLER 43 /* GPTMR0 IRQ handler */ + IRQ_HANDLER 44 /* GPTMR1 IRQ handler */ + IRQ_HANDLER 45 /* GPTMR2 IRQ handler */ + IRQ_HANDLER 46 /* GPTMR3 IRQ handler */ + IRQ_HANDLER 47 /* GPTMR4 IRQ handler */ + IRQ_HANDLER 48 /* GPTMR5 IRQ handler */ + IRQ_HANDLER 49 /* GPTMR6 IRQ handler */ + IRQ_HANDLER 50 /* GPTMR7 IRQ handler */ + IRQ_HANDLER 51 /* WDG0 IRQ handler */ + IRQ_HANDLER 52 /* WDG1 IRQ handler */ + IRQ_HANDLER 53 /* MBX0A IRQ handler */ + IRQ_HANDLER 54 /* MBX0B IRQ handler */ + IRQ_HANDLER 55 /* MBX1A IRQ handler */ + IRQ_HANDLER 56 /* MBX1B IRQ handler */ + IRQ_HANDLER 57 /* RNG IRQ handler */ + IRQ_HANDLER 58 /* HDMA IRQ handler */ + IRQ_HANDLER 59 /* ADC0 IRQ handler */ + IRQ_HANDLER 60 /* ADC1 IRQ handler */ + IRQ_HANDLER 61 /* SDM IRQ handler */ + IRQ_HANDLER 62 /* OPAMP IRQ handler */ + IRQ_HANDLER 63 /* I2S0 IRQ handler */ + IRQ_HANDLER 64 /* I2S1 IRQ handler */ + IRQ_HANDLER 65 /* I2S2 IRQ handler */ + IRQ_HANDLER 66 /* I2S3 IRQ handler */ + IRQ_HANDLER 67 /* DAO IRQ handler */ + IRQ_HANDLER 68 /* PDM IRQ handler */ + IRQ_HANDLER 69 /* SMIX_DMA IRQ handler */ + IRQ_HANDLER 70 /* SMIX_ASRC IRQ handler */ + IRQ_HANDLER 71 /* CAM0 IRQ handler */ + IRQ_HANDLER 72 /* CAM1 IRQ handler */ + IRQ_HANDLER 73 /* LCDC IRQ handler */ + IRQ_HANDLER 74 /* LCDC1 IRQ handler */ + IRQ_HANDLER 75 /* PDMA IRQ handler */ + IRQ_HANDLER 76 /* JPEG IRQ handler */ + IRQ_HANDLER 77 /* GWCK0_FUNC IRQ handler */ + IRQ_HANDLER 78 /* GWCK0_ERR IRQ handler */ + IRQ_HANDLER 79 /* GWCK1_FUNC IRQ handler */ + IRQ_HANDLER 80 /* GWCK1_ERR IRQ handler */ + IRQ_HANDLER 81 /* MIPI_DSI0 IRQ handler */ + IRQ_HANDLER 82 /* MIPI_DSI1 IRQ handler */ + IRQ_HANDLER 83 /* MIPI_CSI0 IRQ handler */ + IRQ_HANDLER 84 /* MIPI_CSI0_AP IRQ handler */ + IRQ_HANDLER 85 /* MIPI_CSI0_DIAG IRQ handler */ + IRQ_HANDLER 86 /* MIPI_CSI1_AP IRQ handler */ + IRQ_HANDLER 87 /* MIPI_CSI1_DIAG IRQ handler */ + IRQ_HANDLER 88 /* MIPI_CSI1 IRQ handler */ + IRQ_HANDLER 89 /* LCB0 IRQ handler */ + IRQ_HANDLER 90 /* LCB1 IRQ handler */ + IRQ_HANDLER 91 /* GPU IRQ handler */ + IRQ_HANDLER 92 /* ENET0 IRQ handler */ + IRQ_HANDLER 93 /* NTMR0 IRQ handler */ + IRQ_HANDLER 94 /* USB0 IRQ handler */ + IRQ_HANDLER 95 /* SDXC0 IRQ handler */ + IRQ_HANDLER 96 /* SDXC1 IRQ handler */ + IRQ_HANDLER 97 /* SDP IRQ handler */ + IRQ_HANDLER 98 /* XPI0 IRQ handler */ + IRQ_HANDLER 99 /* XDMA IRQ handler */ + IRQ_HANDLER 100 /* DDR IRQ handler */ + IRQ_HANDLER 101 /* FFA IRQ handler */ + IRQ_HANDLER 102 /* PSEC IRQ handler */ + IRQ_HANDLER 103 /* TSNS IRQ handler */ + IRQ_HANDLER 104 /* VAD IRQ handler */ + IRQ_HANDLER 105 /* PGPIO IRQ handler */ + IRQ_HANDLER 106 /* PWDG IRQ handler */ + IRQ_HANDLER 107 /* PTMR IRQ handler */ + IRQ_HANDLER 108 /* PUART IRQ handler */ + IRQ_HANDLER 109 /* FUSE IRQ handler */ + IRQ_HANDLER 110 /* SECMON IRQ handler */ + IRQ_HANDLER 111 /* RTC IRQ handler */ + IRQ_HANDLER 112 /* BGPIO IRQ handler */ + IRQ_HANDLER 113 /* BVIO IRQ handler */ + IRQ_HANDLER 114 /* BROWNOUT IRQ handler */ + IRQ_HANDLER 115 /* SYSCTL IRQ handler */ + IRQ_HANDLER 116 /* DEBUG0 IRQ handler */ + IRQ_HANDLER 117 /* DEBUG1 IRQ handler */ \ No newline at end of file diff --git a/bsp/hpmicro/hpm6800evk/startup/HPM6880/trap.c b/bsp/hpmicro/hpm6800evk/startup/HPM6880/trap.c new file mode 100644 index 00000000000..b87eaee5244 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/startup/HPM6880/trap.c @@ -0,0 +1,304 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_common.h" +#include "hpm_soc.h" +#include +#include "rt_hw_stack_frame.h" + +#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) //!< Instruction Address misaligned +#define MCAUSE_INSTR_ACCESS_FAULT (1U) //!< Instruction access fault +#define MCAUSE_ILLEGAL_INSTR (2U) //!< Illegal instruction +#define MCAUSE_BREAKPOINT (3U) //!< Breakpoint +#define MCAUSE_LOAD_ADDR_MISALIGNED (4U) //!< Load address misaligned +#define MCAUSE_LOAD_ACCESS_FAULT (5U) //!< Load access fault +#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U) //!< Store/AMO address misaligned +#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U) //!< Store/AMO access fault +#define MCAUSE_ECALL_FROM_USER_MODE (8U) //!< Environment call from User mode +#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U) //!< Environment call from Supervisor mode +#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U) //!< Environment call from machine mode +#define MCAUSE_INSTR_PAGE_FAULT (12U) //!< Instruction page fault +#define MCAUSE_LOAD_PAGE_FAULT (13) //!< Load page fault +#define MCAUSE_STORE_AMO_PAGE_FAULT (15U) //!< Store/AMO page fault + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#ifdef DEBUG +#define RT_EXCEPTION_TRACE rt_kprintf +#else +#define RT_EXCEPTION_TRACE(...) +#endif + +typedef void (*isr_func_t)(void); + +static volatile rt_hw_stack_frame_t *s_stack_frame; + +__attribute((weak)) void mchtmr_isr(void) +{ +} + +__attribute__((weak)) void mswi_isr(void) +{ +} + +__attribute__((weak)) void syscall_handler(uint32_t n, uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3) +{ +} + +void rt_show_stack_frame(void) +{ + RT_EXCEPTION_TRACE("Stack frame:\r\n----------------------------------------\r\n"); + RT_EXCEPTION_TRACE("ra : 0x%08x\r\n", s_stack_frame->ra); + RT_EXCEPTION_TRACE("mstatus : 0x%08x\r\n", read_csr(0x300));//mstatus + RT_EXCEPTION_TRACE("t0 : 0x%08x\r\n", s_stack_frame->t0); + RT_EXCEPTION_TRACE("t1 : 0x%08x\r\n", s_stack_frame->t1); + RT_EXCEPTION_TRACE("t2 : 0x%08x\r\n", s_stack_frame->t2); + RT_EXCEPTION_TRACE("a0 : 0x%08x\r\n", s_stack_frame->a0); + RT_EXCEPTION_TRACE("a1 : 0x%08x\r\n", s_stack_frame->a1); + RT_EXCEPTION_TRACE("a2 : 0x%08x\r\n", s_stack_frame->a2); + RT_EXCEPTION_TRACE("a3 : 0x%08x\r\n", s_stack_frame->a3); + RT_EXCEPTION_TRACE("a4 : 0x%08x\r\n", s_stack_frame->a4); + RT_EXCEPTION_TRACE("a5 : 0x%08x\r\n", s_stack_frame->a5); +#ifndef __riscv_32e + RT_EXCEPTION_TRACE("a6 : 0x%08x\r\n", s_stack_frame->a6); + RT_EXCEPTION_TRACE("a7 : 0x%08x\r\n", s_stack_frame->a7); + RT_EXCEPTION_TRACE("t3 : 0x%08x\r\n", s_stack_frame->t3); + RT_EXCEPTION_TRACE("t4 : 0x%08x\r\n", s_stack_frame->t4); + RT_EXCEPTION_TRACE("t5 : 0x%08x\r\n", s_stack_frame->t5); + RT_EXCEPTION_TRACE("t6 : 0x%08x\r\n", s_stack_frame->t6); +#endif +} + +uint32_t exception_handler(uint32_t cause, uint32_t epc) +{ + /* Unhandled Trap */ + uint32_t mdcause = read_csr(CSR_MDCAUSE); + uint32_t mtval = read_csr(CSR_MTVAL); + rt_uint32_t mscratch = read_csr(0x340); + + s_stack_frame = (rt_hw_stack_frame_t *)mscratch; + rt_show_stack_frame(); + + switch (cause) + { + case MCAUSE_INSTR_ADDR_MISALIGNED: + RT_EXCEPTION_TRACE("exception: instruction address was mis-aligned, mtval=0x%08x\n", mtval); + break; + case MCAUSE_INSTR_ACCESS_FAULT: + RT_EXCEPTION_TRACE("exception: instruction access fault happened, mtval=0x%08x, epc=0x%08x\n", mtval, epc); + switch (mdcause & 0x07) + { + case 1: + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); + break; + case 4: + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); + break; + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_ILLEGAL_INSTR: + RT_EXCEPTION_TRACE("exception: illegal instruction was met, mtval=0x%08x\n", mtval); + switch (mdcause & 0x07) + { + case 0: + RT_EXCEPTION_TRACE("mdcause: the actual faulting instruction is stored in the mtval CSR\r\n"); + break; + case 1: + RT_EXCEPTION_TRACE("mdcause: FP disabled exception \r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: ACE disabled exception \r\n"); + break; + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_BREAKPOINT: + RT_EXCEPTION_TRACE("exception: breakpoint was hit, mtval=0x%08x\n", mtval); + break; + case MCAUSE_LOAD_ADDR_MISALIGNED: + RT_EXCEPTION_TRACE("exception: load address was mis-aligned, mtval=0x%08x\n", mtval); + break; + case MCAUSE_LOAD_ACCESS_FAULT: + RT_EXCEPTION_TRACE("exception: load access fault happened, epc=%08x, mdcause=0x%x\n", epc, mdcause); + switch (mdcause & 0x07) + { + case 1: + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); + break; + case 4: + RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n"); + break; + case 5: + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); + break; + case 6: + RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n"); + break; + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_STORE_AMO_ADDR_MISALIGNED: + RT_EXCEPTION_TRACE("exception: store amo address was misaligned, epc=%08x\n", epc); + break; + case MCAUSE_STORE_AMO_ACCESS_FAULT: + RT_EXCEPTION_TRACE("exception: store amo access fault happened, epc=%08x\n", epc); + switch (mdcause & 0x07) + { + case 1: + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); + break; + case 4: + RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n"); + break; + case 5: + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); + break; + case 6: + RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n"); + break; + case 7: + RT_EXCEPTION_TRACE("mdcause: PMA NAMO exception \r\n"); + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + default: + RT_EXCEPTION_TRACE("Unknown exception happened, cause=%d\n", cause); + break; + } + + rt_kprintf("cause=0x%08x, epc=0x%08x, ra=0x%08x\n", cause, epc, s_stack_frame->ra); + while(1) { + } +} + +void trap_entry(void); + +void trap_entry(void) +{ + uint32_t mcause = read_csr(CSR_MCAUSE); + uint32_t mepc = read_csr(CSR_MEPC); + uint32_t mstatus = read_csr(CSR_MSTATUS); + +#if SUPPORT_PFT_ARCH + uint32_t mxstatus = read_csr(CSR_MXSTATUS); +#endif +#ifdef __riscv_dsp + int ucode = read_csr(CSR_UCODE); +#endif +#ifdef __riscv_flen + int fcsr = read_fcsr(); +#endif + + /* clobbers list for ecall */ +#ifdef __riscv_32e + __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3"); +#else + __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3"); +#endif + + /* Do your trap handling */ + uint32_t cause_type = mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK; + uint32_t irq_index; + if (mcause & CSR_MCAUSE_INTERRUPT_MASK) + { + switch (cause_type) + { + /* Machine timer interrupt */ + case IRQ_M_TIMER: + mchtmr_isr(); + break; + /* Machine EXT interrupt */ + case IRQ_M_EXT: + /* Claim interrupt */ + irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); + /* Execute EXT interrupt handler */ + if (irq_index > 0) + { + ((isr_func_t) __vector_table[irq_index])(); + /* Complete interrupt */ + __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index); + } + break; + /* Machine SWI interrupt */ + case IRQ_M_SOFT: + mswi_isr(); + intc_m_complete_swi(); + break; + } + } + else if (cause_type == MCAUSE_ECALL_FROM_MACHINE_MODE) + { + /* Machine Syscal call */ + __asm volatile( + "mv a4, a3\n" + "mv a3, a2\n" + "mv a2, a1\n" + "mv a1, a0\n" +#ifdef __riscv_32e + "mv a0, t0\n" +#else + "mv a0, a7\n" +#endif + "call syscall_handler\n" + : : : "a4" + ); + mepc += 4; + } + else + { + mepc = exception_handler(mcause, mepc); + } + + /* Restore CSR */ + write_csr(CSR_MSTATUS, mstatus); + write_csr(CSR_MEPC, mepc); +#if SUPPORT_PFT_ARCH + write_csr(CSR_MXSTATUS, mxstatus); +#endif +#ifdef __riscv_dsp + write_csr(CSR_UCODE, ucode); +#endif +#ifdef __riscv_flen + write_fcsr(fcsr); +#endif +} diff --git a/bsp/hpmicro/hpm6800evk/startup/SConscript b/bsp/hpmicro/hpm6800evk/startup/SConscript new file mode 100644 index 00000000000..de51a7c0d63 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/startup/SConscript @@ -0,0 +1,13 @@ +# for module compiling +import os +Import('rtconfig') +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] + +objs = objs + SConscript(os.path.join(cwd, rtconfig.CHIP_NAME, 'SConscript')) +ASFLAGS = ' -I' + cwd + +Return('objs') \ No newline at end of file diff --git a/bsp/hpmicro/libraries/drivers/SConscript b/bsp/hpmicro/libraries/drivers/SConscript index 1eae2a511bd..a8109d0a8e4 100644 --- a/bsp/hpmicro/libraries/drivers/SConscript +++ b/bsp/hpmicro/libraries/drivers/SConscript @@ -19,8 +19,12 @@ if GetDepend('BSP_USING_RTC'): if GetDepend('BSP_USING_WDG'): src += ['drv_wdt.c'] +if GetDepend('BSP_USING_EWDG'): + src += ['drv_ewdt.c'] + if GetDepend('BSP_USING_ETH'): src += ['drv_enet.c'] + src += ['drv_enet_phy.c'] if GetDepend('BSP_USING_SDXC'): src += ['drv_sdio.c'] @@ -46,8 +50,8 @@ if GetDepend('BSP_USING_UART'): if GetDepend('BSP_USING_ADC'): src += ['drv_adc.c'] -if GetDepend('BSP_USING_USB_HOST'): - src += ['drv_usb.c'] +# if GetDepend('BSP_USING_USB_HOST'): +# src += ['drv_usb.c'] if GetDepend('BSP_USING_DAO'): src += ['drv_dao.c'] @@ -61,6 +65,8 @@ if GetDepend('BSP_USING_I2S'): if GetDepend('BSP_USING_MCAN'): src += ['drv_mcan.c'] +if GetDepend(['BSP_USING_RTT_LCD_DRIVER']): + src += ['drv_lcd.c'] path = [cwd] diff --git a/bsp/hpmicro/libraries/drivers/drv_adc.c b/bsp/hpmicro/libraries/drivers/drv_adc.c index 48e3ab56354..d3dbcefcb6e 100644 --- a/bsp/hpmicro/libraries/drivers/drv_adc.c +++ b/bsp/hpmicro/libraries/drivers/drv_adc.c @@ -112,11 +112,11 @@ static uint32_t hpm_adc_init_clock(struct rt_adc_device *device) #if defined(ADC12_SOC_MAX_CH_NUM) if (hpm_adc->is_adc12) { - clock_freq = board_init_adc12_clock((ADC12_Type*)hpm_adc->adc_base); + clock_freq = board_init_adc12_clock((ADC12_Type*)hpm_adc->adc_base,true); } else #endif { - clock_freq = board_init_adc16_clock((ADC16_Type*)hpm_adc->adc_base); + clock_freq = board_init_adc16_clock((ADC16_Type*)hpm_adc->adc_base,true); } return clock_freq; } @@ -135,7 +135,7 @@ static rt_err_t init_adc_config(hpm_rtt_adc *adc) cfg.adc_clk_div = 3; ret = adc12_init((ADC12_Type *)adc->adc_base, &cfg); if (ret != status_success) { - return RT_ERROR; + return -RT_ERROR; } #endif } else { @@ -151,8 +151,12 @@ static rt_err_t init_adc_config(hpm_rtt_adc *adc) cfg.wait_dis = 0; ret = adc16_init((ADC16_Type *)adc->adc_base, &cfg); if (ret != status_success) { - return RT_ERROR; + return -RT_ERROR; } +#endif +#if defined(ADC_SOC_BUSMODE_ENABLE_CTRL_SUPPORT) && ADC_SOC_BUSMODE_ENABLE_CTRL_SUPPORT + /* enable oneshot mode */ + adc16_enable_oneshot_mode((ADC16_Type *)adc->adc_base); #endif } return RT_EOK; @@ -167,13 +171,13 @@ static rt_err_t init_channel_config(hpm_rtt_adc *adc, uint16_t channel) adc12_channel_config_t ch_cfg; adc12_get_channel_default_config(&ch_cfg); - ch_cfg.ch = adc->channel; + ch_cfg.ch = channel; ch_cfg.diff_sel = adc12_sample_signal_single_ended; ch_cfg.sample_cycle = 20; ret = adc12_init_channel((ADC12_Type *)adc->adc_base, &ch_cfg); if (ret != status_success) { - return RT_ERROR; + return -RT_ERROR; } #endif } else { @@ -185,7 +189,7 @@ static rt_err_t init_channel_config(hpm_rtt_adc *adc, uint16_t channel) ch_cfg.sample_cycle = 20; ret = adc16_init_channel((ADC16_Type *)adc->adc_base, &ch_cfg); if (ret != status_success) { - return RT_ERROR; + return -RT_ERROR; } #endif } @@ -207,7 +211,7 @@ static rt_err_t hpm_adc_enabled(struct rt_adc_device *device, rt_int8_t channel, (void)hpm_adc_init_clock(device); ret = init_adc_config(hpm_adc); if (ret != RT_EOK) { - return RT_ERROR; + return -RT_ERROR; } hpm_adc->adc_enabled = true; } @@ -215,7 +219,7 @@ static rt_err_t hpm_adc_enabled(struct rt_adc_device *device, rt_int8_t channel, ret = init_channel_config(hpm_adc, channel); if (ret != RT_EOK) { - return RT_ERROR; + return -RT_ERROR; } } } diff --git a/bsp/hpmicro/libraries/drivers/drv_can.c b/bsp/hpmicro/libraries/drivers/drv_can.c index 7e4603a8027..7325c5387f1 100644 --- a/bsp/hpmicro/libraries/drivers/drv_can.c +++ b/bsp/hpmicro/libraries/drivers/drv_can.c @@ -411,6 +411,12 @@ static rt_err_t hpm_can_control(struct rt_can_device *can, int cmd, void *arg) drv_can->filter_num = 0; } err = hpm_can_configure(can, &drv_can->can_dev.config); +#ifdef RT_CAN_USING_HDR + if (filter == RT_NULL) { + /*if use RT_CAN_USING_HDR, but if want to receive everything without filtering, use default filter, need to return NO-RT-OK status*/ + err = -RT_ETRAP; + } +#endif } break; case RT_CAN_CMD_SET_MODE: @@ -505,6 +511,7 @@ static rt_err_t hpm_can_control(struct rt_can_device *can, int cmd, void *arg) rt_memcpy(arg, &drv_can->can_dev.status, sizeof(drv_can->can_dev.status)); break; } + return err; } static int hpm_can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno) @@ -537,11 +544,10 @@ static int hpm_can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32 } #ifdef RT_CAN_USING_CANFD + tx_buf.bitrate_switch = can_msg->brs; if (can_msg->fd_frame != 0) { tx_buf.canfd_frame = 1; - tx_buf.bitrate_switch = 1; - RT_ASSERT(can_msg->len <= 15); } else @@ -627,12 +633,20 @@ static int hpm_can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t box else { can_msg->rtr = RT_CAN_DTR; } - +#ifdef RT_CAN_USING_CANFD + can_msg->fd_frame = rx_buf.canfd_frame; + can_msg->brs = rx_buf.bitrate_switch; +#endif can_msg->len = rx_buf.dlc; uint32_t msg_len = can_get_data_bytes_from_dlc(can_msg->len); for(uint32_t i = 0; i < msg_len; i++) { can_msg->data[i] = rx_buf.data[i]; } +#ifdef RT_CAN_USING_HDR + /* Hardware filter messages are valid */ + can_msg->hdr_index = boxno; + can->hdr[can_msg->hdr_index].connected = 1; +#endif } else { return -RT_EEMPTY; @@ -686,7 +700,9 @@ int rt_hw_can_init(void) config.privmode = RT_CAN_MODE_NOPRIV; config.sndboxnumber = CAN_SENDBOX_NUM; config.ticks = 50; - +#ifdef RT_CAN_USING_HDR + config.maxhdr = 16; +#endif for (uint32_t i = 0; i < ARRAY_SIZE(hpm_cans); i++) { hpm_cans[i]->can_dev.config = config; diff --git a/bsp/hpmicro/libraries/drivers/drv_dao.c b/bsp/hpmicro/libraries/drivers/drv_dao.c index eb3e73acff9..3143fca99b8 100644 --- a/bsp/hpmicro/libraries/drivers/drv_dao.c +++ b/bsp/hpmicro/libraries/drivers/drv_dao.c @@ -18,11 +18,15 @@ #include "hpm_dao_drv.h" #include "board.h" #include "drv_dao.h" +#ifdef HPMSOC_HAS_HPMSDK_DMAV2 +#include "hpm_dmav2_drv.h" +#else #include "hpm_dma_drv.h" +#endif #include "hpm_dmamux_drv.h" #include "hpm_l1c_drv.h" #include "hpm_clock_drv.h" -#include "hpm_dma_manager.h" +#include "hpm_dma_mgr.h" /* DAO connect to I2S1 TX*/ #define DAO_DMA_REQ HPM_DMA_SRC_I2S1_TX @@ -36,13 +40,11 @@ struct hpm_dao }; struct hpm_dao hpm_dao_dev = { 0 }; -static hpm_dma_resource_t dma_resource = { 0 }; +static dma_resource_t dma_resource = { 0 }; -void dao_dma_callback(DMA_Type *ptr, uint32_t channel, void *user_data, uint32_t int_stat) +void dao_dma_tc_callback(DMA_Type *ptr, uint32_t channel, void *user_data) { - if (int_stat == DMA_CHANNEL_STATUS_TC) { - rt_audio_tx_complete(&hpm_dao_dev.audio); - } + rt_audio_tx_complete(&hpm_dao_dev.audio); } static rt_err_t hpm_dao_getcaps(struct rt_audio_device* audio, struct rt_audio_caps* caps) @@ -92,6 +94,11 @@ static rt_err_t hpm_dao_getcaps(struct rt_audio_device* audio, struct rt_audio_c return result; } +static bool i2s_is_enabled(I2S_Type *ptr) +{ + return ((ptr->CTRL & I2S_CTRL_I2S_EN_MASK) != 0); +} + static rt_err_t hpm_dao_set_samplerate(uint32_t samplerate) { uint32_t mclk_hz; @@ -100,11 +107,19 @@ static rt_err_t hpm_dao_set_samplerate(uint32_t samplerate) mclk_hz = clock_get_frequency(clock_i2s1); i2s_get_default_transfer_config_for_dao(&transfer); transfer.sample_rate = samplerate; + bool is_enabled = i2s_is_enabled(DAO_I2S); + if (is_enabled) { + dma_abort_channel(dma_resource.base, dma_resource.channel); + } if (status_success != i2s_config_tx(DAO_I2S, mclk_hz, &transfer)) { LOG_E("dao_i2s configure transfer failed\n"); return -RT_ERROR; } + if (is_enabled) + { + i2s_enable(DAO_I2S); + } return RT_EOK; } @@ -185,12 +200,15 @@ static rt_err_t hpm_dao_start(struct rt_audio_device* audio, int stream) { RT_ASSERT(audio != RT_NULL); - dao_start(HPM_DAO); + i2s_disable(DAO_I2S); + i2s_disable_tx_dma_request(DAO_I2S); + dao_stop(HPM_DAO); + dao_software_reset(HPM_DAO); - if (dma_manager_request_resource(&dma_resource) == status_success) { + if (dma_mgr_request_resource(&dma_resource) == status_success) { uint8_t dmamux_ch; - dma_manager_install_interrupt_callback(&dma_resource, dao_dma_callback, NULL); - dma_manager_enable_dma_interrupt(&dma_resource, 1); + dma_mgr_install_chn_tc_callback(&dma_resource, dao_dma_tc_callback, NULL); + dma_mgr_enable_dma_irq_with_priority(&dma_resource, 1); dmamux_ch = DMA_SOC_CHN_TO_DMAMUX_CHN(dma_resource.base, dma_resource.channel); dmamux_config(HPM_DMAMUX, dmamux_ch, DAO_DMA_REQ, true); } else { @@ -198,7 +216,15 @@ static rt_err_t hpm_dao_start(struct rt_audio_device* audio, int stream) return -RT_ERROR; } + /* fill 2 dummy data, it is suitable for 1/2 channel of audio */ + i2s_reset_tx(DAO_I2S); + if (i2s_fill_tx_dummy_data(DAO_I2S, DAO_I2S_DATA_LINE, 2) != status_success) { + return -RT_ERROR; + } rt_audio_tx_complete(audio); + i2s_enable(DAO_I2S); + i2s_enable_tx_dma_request(DAO_I2S); + dao_start(HPM_DAO); return RT_EOK; } @@ -208,8 +234,10 @@ static rt_err_t hpm_dao_stop(struct rt_audio_device* audio, int stream) RT_ASSERT(audio != RT_NULL); dao_stop(HPM_DAO); + i2s_stop(DAO_I2S); - dma_manager_release_resource(&dma_resource); + dma_abort_channel(dma_resource.base, dma_resource.channel); + dma_mgr_release_resource(&dma_resource); return RT_EOK; } diff --git a/bsp/hpmicro/libraries/drivers/drv_enet.c b/bsp/hpmicro/libraries/drivers/drv_enet.c index 538c56621a0..d5cb00896a5 100644 --- a/bsp/hpmicro/libraries/drivers/drv_enet.c +++ b/bsp/hpmicro/libraries/drivers/drv_enet.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 - 2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -50,7 +50,7 @@ static enet_ptp_config_t ptp_config0 = {.timestamp_rollover_mode = enet_ts_dig_r }; #endif -static hpm_enet_t enet0 = {.name = "ETH0", +static hpm_enet_t enet0 = {.name = "E0", .base = HPM_ENET0, .irq_num = IRQn_ENET0, .inf = BOARD_ENET0_INF, @@ -75,6 +75,11 @@ static hpm_enet_t enet0 = {.name = "ETH0", }; #endif +mac_init_t mac_init[] = { + {MAC0_ADDR0, MAC0_ADDR1, MAC0_ADDR2, MAC0_ADDR3, MAC0_ADDR4, MAC0_ADDR5}, + {MAC1_ADDR0, MAC1_ADDR1, MAC1_ADDR2, MAC1_ADDR3, MAC1_ADDR4, MAC1_ADDR5} +}; + #ifdef BSP_USING_ETH1 ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(ENET_SOC_DESC_ADDR_ALIGNMENT) @@ -109,7 +114,7 @@ static enet_ptp_config_t ptp_config1 = {.timestamp_rollover_mode = enet_ts_dig_r }; #endif -static hpm_enet_t enet1 = {.name = "ETH1", +static hpm_enet_t enet1 = {.name = "E1", .base = HPM_ENET1, .irq_num = IRQn_ENET1, .inf = BOARD_ENET1_INF, @@ -144,37 +149,55 @@ static hpm_enet_t *s_geths[] = { #endif }; -ATTR_WEAK void enet_get_mac_address(uint8_t *mac) +ATTR_WEAK uint8_t enet_get_mac_address(ENET_Type *ptr, uint8_t *mac) { - uint32_t uuid[OTP_SOC_UUID_LEN / sizeof(uint32_t)]; - - for (int i = 0; i < ARRAY_SIZE(uuid); i++) { - uuid[i] = otp_read_from_shadow(OTP_SOC_UUID_IDX + i); - } - - if (!IS_UUID_INVALID(uuid)) { - uuid[0] &= 0xfc; - memcpy(mac, &uuid, ENET_MAC); - } else { - mac[0] = MAC_ADDR0; - mac[1] = MAC_ADDR1; - mac[2] = MAC_ADDR2; - mac[3] = MAC_ADDR3; - mac[4] = MAC_ADDR4; - mac[5] = MAC_ADDR5; - } + uint32_t macl, mach; + uint8_t i; + + i = (ptr == HPM_ENET0) ? 0 : 1; + + if (mac == NULL) { + return ENET_MAC_ADDR_PARA_ERROR; + } + + /* load mac address from OTP MAC area */ + if (i == 0) { + macl = otp_read_from_shadow(OTP_SOC_MAC0_IDX); + mach = otp_read_from_shadow(OTP_SOC_MAC0_IDX + 1); + + mac[0] = (macl >> 0) & 0xff; + mac[1] = (macl >> 8) & 0xff; + mac[2] = (macl >> 16) & 0xff; + mac[3] = (macl >> 24) & 0xff; + mac[4] = (mach >> 0) & 0xff; + mac[5] = (mach >> 8) & 0xff; + } else { + macl = otp_read_from_shadow(OTP_SOC_MAC0_IDX + 1); + mach = otp_read_from_shadow(OTP_SOC_MAC0_IDX + 2); + + mac[0] = (macl >> 16) & 0xff; + mac[1] = (macl >> 24) & 0xff; + mac[2] = (mach >> 0) & 0xff; + mac[3] = (mach >> 8) & 0xff; + mac[4] = (mach >> 16) & 0xff; + mac[5] = (mach >> 24) & 0xff; + } + + if (!IS_MAC_INVALID(mac)) { + return ENET_MAC_ADDR_FROM_OTP_MAC; + } + + /* load MAC address from MACRO definitions */ + memcpy(mac, &mac_init[i], ENET_MAC); + return ENET_MAC_ADDR_FROM_MACRO; } static rt_err_t hpm_enet_init(enet_device *init) { - /* Initialize eth controller */ - enet_controller_init(init->instance, init->media_interface, &init->desc, &init->mac_config, &init->int_config); - if (init->media_interface == enet_inf_rmii) { /* Initialize reference clock */ board_init_enet_rmii_reference_clock(init->instance, init->int_refclk); - enet_rmii_enable_clock(init->instance, init->int_refclk); } #if ENET_SOC_RGMII_EN @@ -186,6 +209,9 @@ static rt_err_t hpm_enet_init(enet_device *init) } #endif + /* Initialize eth controller */ + enet_controller_init(init->instance, init->media_interface, &init->desc, &init->mac_config, &init->int_config); + #if __USE_ENET_PTP /* initialize PTP Clock */ board_init_enet_ptp_clock(init->instance); @@ -217,7 +243,7 @@ static rt_err_t rt_hpm_eth_init(rt_device_t dev) board_reset_enet_phy(enet_dev->instance); /* Get MAC address */ - enet_get_mac_address(mac); + enet_get_mac_address(enet_dev->instance, mac); /* Set mac0 address */ enet_dev->mac_config.mac_addr_high[0] = mac[5] << 8 | mac[4]; @@ -233,7 +259,7 @@ static rt_err_t rt_hpm_eth_init(rt_device_t dev) else { LOG_D("Ethernet control initialize unsuccessfully\n"); - return RT_ERROR; + return -RT_ERROR; } } @@ -260,13 +286,14 @@ static rt_ssize_t rt_hpm_eth_write(rt_device_t dev, rt_off_t pos, const void * b static rt_err_t rt_hpm_eth_control(rt_device_t dev, int cmd, void * args) { uint8_t *mac = (uint8_t *)args; + enet_device *enet_dev = (enet_device *)dev->user_data; switch (cmd) { case NIOCTL_GADDR: if (args != NULL) { - enet_get_mac_address((uint8_t *)mac); + enet_get_mac_address(enet_dev->instance, (uint8_t *)mac); SMEMCPY(args, mac, ENET_MAC); } else @@ -406,54 +433,57 @@ static struct pbuf *rt_hpm_eth_rx(rt_device_t dev) { /* allocate a pbuf chain of pbufs from the Lwip buffer pool */ p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); - } - if (p != NULL) - { - dma_rx_desc = frame.rx_desc; - buffer_offset = 0; - for (q = p; q != NULL; q = q->next) + if (p != NULL) { - bytes_left_to_copy = q->len; - payload_offset = 0; - - /* Check if the length of bytes to copy in current pbuf is bigger than Rx buffer size*/ - while ((bytes_left_to_copy + buffer_offset) > rx_buff_size) + dma_rx_desc = frame.rx_desc; + buffer_offset = 0; + for (q = p; q != NULL; q = q->next) { - /* Copy data to pbuf */ - SMEMCPY((uint8_t *)((uint8_t *)q->payload + payload_offset), (uint8_t *)((uint8_t *)buffer + buffer_offset), (rx_buff_size - buffer_offset)); + bytes_left_to_copy = q->len; + payload_offset = 0; + + /* Check if the length of bytes to copy in current pbuf is bigger than Rx buffer size*/ + while ((bytes_left_to_copy + buffer_offset) > rx_buff_size) + { + /* Copy data to pbuf */ + SMEMCPY((uint8_t *)((uint8_t *)q->payload + payload_offset), (uint8_t *)((uint8_t *)buffer + buffer_offset), (rx_buff_size - buffer_offset)); - /* Point to next descriptor */ - dma_rx_desc = (enet_rx_desc_t *)(dma_rx_desc->rdes3_bm.next_desc); - buffer = (uint8_t *)(dma_rx_desc->rdes2_bm.buffer1); + /* Point to next descriptor */ + dma_rx_desc = (enet_rx_desc_t *)(dma_rx_desc->rdes3_bm.next_desc); + buffer = (uint8_t *)(dma_rx_desc->rdes2_bm.buffer1); - bytes_left_to_copy = bytes_left_to_copy - (rx_buff_size - buffer_offset); - payload_offset = payload_offset + (rx_buff_size - buffer_offset); - buffer_offset = 0; + bytes_left_to_copy = bytes_left_to_copy - (rx_buff_size - buffer_offset); + payload_offset = payload_offset + (rx_buff_size - buffer_offset); + buffer_offset = 0; + } + /* Copy remaining data in pbuf */ + q->payload = (void *)sys_address_to_core_local_mem(0, (uint32_t)buffer); + buffer_offset = buffer_offset + bytes_left_to_copy; } - /* Copy remaining data in pbuf */ - q->payload = (void *)sys_address_to_core_local_mem(0, (uint32_t)buffer); - buffer_offset = buffer_offset + bytes_left_to_copy; } - } - else - { - return NULL; - } - /* Release descriptors to DMA */ - /* Point to first descriptor */ - dma_rx_desc = frame.rx_desc; + /* Release descriptors to DMA */ + /* Point to first descriptor */ + dma_rx_desc = frame.rx_desc; - /* Set Own bit in Rx descriptors: gives the buffers back to DMA */ - for (i = 0; i < enet_dev->desc.rx_frame_info.seg_count; i++) - { - dma_rx_desc->rdes0_bm.own = 1; - dma_rx_desc = (enet_rx_desc_t*)(dma_rx_desc->rdes3_bm.next_desc); + /* Set Own bit in Rx descriptors: gives the buffers back to DMA */ + for (i = 0; i < enet_dev->desc.rx_frame_info.seg_count; i++) + { + dma_rx_desc->rdes0_bm.own = 1; + dma_rx_desc = (enet_rx_desc_t*)(dma_rx_desc->rdes3_bm.next_desc); + } + + /* Clear Segment_Count */ + enet_dev->desc.rx_frame_info.seg_count = 0; } - /* Clear Segment_Count */ - enet_dev->desc.rx_frame_info.seg_count = 0; + /* Resume Rx Process */ + if (ENET_DMA_STATUS_RU_GET(enet_dev->instance->DMA_STATUS)) + { + enet_dev->instance->DMA_STATUS = ENET_DMA_STATUS_RU_MASK; + enet_dev->instance->DMA_RX_POLL_DEMAND = 1; + } return p; } @@ -526,7 +556,7 @@ int rt_hw_eth_init(void) s_geths[i]->enet_dev->desc.rx_buff_cfg.size = s_geths[i]->rx_buff_cfg->size; /* Set DMA PBL */ - s_geths[i]->enet_dev->mac_config.dma_pbl = board_enet_get_dma_pbl(s_geths[i]->base); + s_geths[i]->enet_dev->mac_config.dma_pbl = board_get_enet_dma_pbl(s_geths[i]->base); /* Set instance */ s_geths[i]->enet_dev->instance = s_geths[i]->base; @@ -578,11 +608,11 @@ int rt_hw_eth_init(void) if (RT_EOK == err) { - LOG_D("Ethernet device initialize successfully!\n"); + LOG_D("Ethernet device %d initialize successfully!\n", i); } else { - LOG_D("Ethernet device initialize unsuccessfully!\n"); + LOG_D("Ethernet device %d initialize unsuccessfully!\n"); return err; } } diff --git a/bsp/hpmicro/libraries/drivers/drv_enet.h b/bsp/hpmicro/libraries/drivers/drv_enet.h index 8830980717e..c8137e365d4 100644 --- a/bsp/hpmicro/libraries/drivers/drv_enet.h +++ b/bsp/hpmicro/libraries/drivers/drv_enet.h @@ -12,6 +12,22 @@ #include "hpm_enet_drv.h" #include "board.h" +typedef enum { + ENET_MAC_ADDR_PARA_ERROR = -1, + ENET_MAC_ADDR_FROM_OTP_MAC, + ENET_MAC_ADDR_FROM_OTP_UUID, + ENET_MAC_ADDR_FROM_MACRO +} enet_mac_addr_t; + +typedef struct { + uint8_t mac_addr0; + uint8_t mac_addr1; + uint8_t mac_addr2; + uint8_t mac_addr3; + uint8_t mac_addr4; + uint8_t mac_addr5; +} mac_init_t; + typedef struct { ENET_Type * instance; enet_desc_t desc; @@ -59,6 +75,13 @@ typedef struct _hpm_enet UUID[2] == 0 && \ UUID[3] == 0) +#define IS_MAC_INVALID(MAC) (MAC[0] == 0 && \ + MAC[1] == 0 && \ + MAC[2] == 0 && \ + MAC[3] == 0 && \ + MAC[4] == 0 && \ + MAC[5] == 0) + #if ENET_SOC_RGMII_EN #ifndef ENET0_TX_BUFF_COUNT #define ENET0_TX_BUFF_COUNT (50U) @@ -101,30 +124,54 @@ typedef struct _hpm_enet #define ENET1_TX_BUFF_SIZE ENET_MAX_FRAME_SIZE #endif -#ifndef MAC_ADDR0 -#define MAC_ADDR0 (0x98U) +#ifndef MAC0_ADDR0 +#define MAC0_ADDR0 (0x98U) +#endif + +#ifndef MAC0_ADDR1 +#define MAC0_ADDR1 (0x2CU) +#endif + +#ifndef MAC0_ADDR2 +#define MAC0_ADDR2 (0xBCU) #endif -#ifndef MAC_ADDR1 -#define MAC_ADDR1 (0x2CU) +#ifndef MAC0_ADDR3 +#define MAC0_ADDR3 (0xB1U) #endif -#ifndef MAC_ADDR2 -#define MAC_ADDR2 (0xBCU) +#ifndef MAC0_ADDR4 +#define MAC0_ADDR4 (0x9FU) #endif -#ifndef MAC_ADDR3 -#define MAC_ADDR3 (0xB1U) +#ifndef MAC0_ADDR5 +#define MAC0_ADDR5 (0x17U) #endif -#ifndef MAC_ADDR4 -#define MAC_ADDR4 (0x9FU) + +#ifndef MAC1_ADDR0 +#define MAC1_ADDR0 (0x98U) +#endif + +#ifndef MAC1_ADDR1 +#define MAC1_ADDR1 (0x2CU) +#endif + +#ifndef MAC1_ADDR2 +#define MAC1_ADDR2 (0xBCU) +#endif + +#ifndef MAC1_ADDR3 +#define MAC1_ADDR3 (0xB1U) #endif -#ifndef MAC_ADDR5 -#define MAC_ADDR5 (0x17U) +#ifndef MAC1_ADDR4 +#define MAC1_ADDR4 (0x9FU) #endif +#ifndef MAC1_ADDR5 +#define MAC1_ADDR5 (0x27U) +#endif int rt_hw_eth_init(void); #endif /* DRV_ENET_H */ diff --git a/bsp/hpmicro/hpm6750evk2/board/eth_phy_port.c b/bsp/hpmicro/libraries/drivers/drv_enet_phy.c similarity index 52% rename from bsp/hpmicro/hpm6750evk2/board/eth_phy_port.c rename to bsp/hpmicro/libraries/drivers/drv_enet_phy.c index 10074b1a4d5..6ded32f75f3 100644 --- a/bsp/hpmicro/hpm6750evk2/board/eth_phy_port.c +++ b/bsp/hpmicro/libraries/drivers/drv_enet_phy.c @@ -1,11 +1,12 @@ /* - * Copyright (c) 2023 hpmicro + * Copyright (c) 2023-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * * Change Logs: * Date Author Notes - * 2022-01-11 hpmicro First version + * 2023-12-20 Jiading Optimization for all-in-one version + * 2024-04-17 Jiading Support multiple PHYs */ #include "rtthread.h" @@ -14,7 +15,8 @@ #include #include #include "hpm_enet_drv.h" -#include "eth_phy_port.h" +#include "drv_enet_phy.h" +#include "hpm_enet_phy.h" #include "hpm_soc.h" #include "netif/ethernetif.h" #include "board.h" @@ -36,9 +38,9 @@ typedef struct #ifdef BSP_USING_ETH0 extern struct eth_device eth0_dev; -static struct rt_mdio_bus mdio0_bus; +static struct rt_mdio_bus_ops mdio0_bus_ops; +static struct rt_mdio_bus mdio0_bus = {.ops = &mdio0_bus_ops}; static phy_device_t phy0_dev; -static uint8_t phy0_reg_list[]= {PHY0_REG_LIST}; static eth_phy_handle_t eth0_phy_handle = { @@ -52,9 +54,9 @@ static eth_phy_handle_t eth0_phy_handle = #ifdef BSP_USING_ETH1 extern struct eth_device eth1_dev; -static struct rt_mdio_bus mdio1_bus; +static struct rt_mdio_bus_ops mdio1_bus_ops; +static struct rt_mdio_bus mdio1_bus = {.ops = &mdio1_bus_ops}; static phy_device_t phy1_dev; -static uint8_t phy1_reg_list[]= {PHY1_REG_LIST}; static eth_phy_handle_t eth1_phy_handle = { @@ -77,17 +79,6 @@ static eth_phy_handle_t *s_gphys[] = #endif }; -static uint8_t *s_gphy_reg_list[] = -{ -#ifdef BSP_USING_ETH0 -phy0_reg_list, -#endif - -#ifdef BSP_USING_ETH1 -phy1_reg_list, -#endif -}; - eth_phy_monitor_handle_t phy_monitor_handle = { .phy_handle_cnt = ARRAY_SIZE(s_gphys), @@ -98,19 +89,97 @@ static struct rt_phy_ops phy_ops; static rt_phy_status phy_init(void *object, rt_uint32_t phy_addr, rt_uint32_t src_clock_hz) { -#ifdef BSP_USING_ETH0 - return PHY_STATUS_OK; +#if defined(BSP_USING_ETH0) && defined(BSP_USING_ENET_PHY_DP83867) + if ((ENET_Type *)object == HPM_ENET0) + { + dp83867_config_t phy_config; + + dp83867_reset((ENET_Type *)object); + #if defined(__DISABLE_AUTO_NEGO) && __DISABLE_AUTO_NEGO + dp83867_set_mdi_crossover_mode((ENET_Type *)object, enet_phy_mdi_crossover_manual_mdix); + #endif + dp83867_basic_mode_default_config((ENET_Type *)object, &phy_config); + if (dp83867_basic_mode_init((ENET_Type *)object, &phy_config) == true) { + return PHY_STATUS_OK; + } else { + return PHY_STATUS_FAIL; + } + } #endif -#ifdef BSP_USING_ETH1 - rtl8201_config_t phy_config; - rtl8201_reset((ENET_Type *)object); - rtl8201_basic_mode_default_config((ENET_Type *)object, &phy_config); - if (rtl8201_basic_mode_init((ENET_Type *)object, &phy_config) == true) { - return PHY_STATUS_OK; - } else { - return PHY_STATUS_FAIL; +#if defined(BSP_USING_ETH0) && defined(BSP_USING_ENET_PHY_RTL8211) + if ((ENET_Type *)object == HPM_ENET0) + { + rtl8211_config_t phy_config; + + rtl8211_reset((ENET_Type *)object); + rtl8211_basic_mode_default_config((ENET_Type *)object, &phy_config); + if (rtl8211_basic_mode_init((ENET_Type *)object, &phy_config) == true) { + return PHY_STATUS_OK; + } else { + return PHY_STATUS_FAIL; + } + } +#endif + +#if defined(BSP_USING_ETH0) && defined(BSP_USING_ENET_PHY_RTL8201) && !defined(BSP_USING_ETH1) + if ((ENET_Type *)object == HPM_ENET0) + { + rtl8201_config_t phy_config; + + rtl8201_reset((ENET_Type *)object); + rtl8201_basic_mode_default_config((ENET_Type *)object, &phy_config); + if (rtl8201_basic_mode_init((ENET_Type *)object, &phy_config) == true) { + return PHY_STATUS_OK; + } else { + return PHY_STATUS_FAIL; + } + } +#endif + +#if defined(BSP_USING_ETH1) && defined(BSP_USING_ENET_PHY_DP83848) + if ((ENET_Type *)object == HPM_ENET1) + { + dp83848_config_t phy_config; + + dp83848_reset((ENET_Type *)object); + dp83848_basic_mode_default_config((ENET_Type *)object, &phy_config); + if (dp83848_basic_mode_init((ENET_Type *)object, &phy_config) == true) { + return PHY_STATUS_OK; + } else { + return PHY_STATUS_FAIL; + } + } +#endif + +#if defined(BSP_USING_ETH1) && defined(BSP_USING_ENET_PHY_RTL8201) + if ((ENET_Type *)object == HPM_ENET1) + { + rtl8201_config_t phy_config; + + rtl8201_reset((ENET_Type *)object); + rtl8201_basic_mode_default_config((ENET_Type *)object, &phy_config); + if (rtl8201_basic_mode_init((ENET_Type *)object, &phy_config) == true) { + return PHY_STATUS_OK; + } else { + return PHY_STATUS_FAIL; + } + } +#endif + +#if defined(BSP_USING_ETH1) && defined(BSP_USING_ENET_PHY_LAN8720) + if ((ENET_Type *)object == HPM_ENET1) + { + lan8720_config_t phy_config; + + lan8720_reset((ENET_Type *)object); + lan8720_basic_mode_default_config((ENET_Type *)object, &phy_config); + if (lan8720_basic_mode_init((ENET_Type *)object, &phy_config) == true) { + return PHY_STATUS_OK; + } else { + return PHY_STATUS_FAIL; + } } #endif } @@ -131,51 +200,83 @@ static rt_size_t phy_write(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *d static rt_phy_status phy_get_link_status(rt_phy_t *phy, rt_bool_t *status) { - uint16_t reg_status; + enet_phy_status_t phy_status; - reg_status = enet_read_phy(phy->bus->hw_obj, phy->addr, phy->reg_list[PHY_BASIC_STATUS_REG_IDX]); + if (phy->bus->hw_obj == HPM_ENET0) + { + #if defined(__USE_DP83867) && __USE_DP83867 + dp83867_get_phy_status(phy->bus->hw_obj, &phy_status); + #endif - #if PHY_AUTO_NEGO - reg_status &= PHY_AUTONEGO_COMPLETE_MASK | PHY_LINKED_STATUS_MASK; - *status = reg_status ? RT_TRUE : RT_FALSE; + #if defined(__USE_RTL8211) && __USE_RTL8211 + rtl8211_get_phy_status(phy->bus->hw_obj, &phy_status); + #endif - #else - reg_status &= PHY_LINKED_STATUS_MASK; - *status = reg_status ? RT_TRUE : RT_FALSE; - #endif + #if defined(__USE_RTL8201) && __USE_RTL8201 && !defined(BSP_USING_ETH1) + rtl8201_get_phy_status(phy->bus->hw_obj, &phy_status); + #endif + } + +#if defined(HPM_ENET1_BASE) + if (phy->bus->hw_obj == HPM_ENET1) + { + #if defined(__USE_DP83848) && __USE_DP83848 + dp83848_get_phy_status(phy->bus->hw_obj, &phy_status); + #endif + + #if defined(__USE_RTL8201) && __USE_RTL8201 + rtl8201_get_phy_status(phy->bus->hw_obj, &phy_status); + #endif + + #if defined(__USE_LAN8720) && __USE_LAN8720 + lan8720_get_phy_status(phy->bus->hw_obj, &phy_status); + #endif + } +#endif + + *status = phy_status.enet_phy_link; return PHY_STATUS_OK; } static rt_phy_status phy_get_link_speed_duplex(rt_phy_t *phy, rt_uint32_t *speed, rt_uint32_t *duplex) { - uint16_t reg_status; + enet_phy_status_t phy_status; - reg_status = enet_read_phy(phy->bus->hw_obj, phy->addr, phy->reg_list[PHY_STATUS_REG_IDX]); -#if RGMII - if (PHY_STATUS_SPEED_1000M(reg_status)) - { - *speed = PHY_SPEED_1000M; - } - else if (PHY_STATUS_SPEED_100M(reg_status)) - { - *speed = PHY_SPEED_100M; - } - else - { - *speed = PHY_SPEED_10M; - } -#else - if (PHY_STATUS_SPEED_100M(reg_status)) + if (phy->bus->hw_obj == HPM_ENET0) { - *speed = PHY_SPEED_100M; + #if defined(__USE_DP83867) && __USE_DP83867 + dp83867_get_phy_status(phy->bus->hw_obj, &phy_status); + #endif + + #if defined(__USE_RTL8211) && __USE_RTL8211 + rtl8211_get_phy_status(phy->bus->hw_obj, &phy_status); + #endif + + #if defined(__USE_RTL8201) && __USE_RTL8201 && !defined(BSP_USING_ETH1) + rtl8201_get_phy_status(phy->bus->hw_obj, &phy_status); + #endif } - else + +#if defined(HPM_ENET1_BASE) + if (phy->bus->hw_obj == HPM_ENET1) { - *speed = PHY_SPEED_10M; + #if defined(__USE_DP83848) && __USE_DP83848 + dp83848_get_phy_status(phy->bus->hw_obj, &phy_status); + #endif + + #if defined(__USE_RTL8201) && __USE_RTL8201 + rtl8201_get_phy_status(phy->bus->hw_obj, &phy_status); + #endif + + #if defined(__USE_LAN8720) && __USE_LAN8720 + lan8720_get_phy_status(phy->bus->hw_obj, &phy_status); + #endif } #endif - *duplex = PHY_STATUS_FULL_DUPLEX(reg_status) ? PHY_FULL_DUPLEX: PHY_HALF_DUPLEX; + + *speed = phy_status.enet_phy_speed; + *duplex = phy_status.enet_phy_duplex; return PHY_STATUS_OK; } @@ -217,6 +318,7 @@ static void phy_poll_status(void *parameter) { phy_dev->phy_link = status ? PHY_LINK_UP : PHY_LINK_DOWN; eth_device_linkchange(eth_dev, status); + LOG_I("%s", phy_dev->phy.bus->hw_obj == HPM_ENET0 ? "ENET0" : "ENET1"); LOG_I("PHY Status: %s", status ? "Link up" : "Link down\n"); if (status == PHY_LINK_UP) { @@ -231,38 +333,15 @@ static void phy_poll_status(void *parameter) static void phy_detection(void *parameter) { - uint8_t detected_count = 0; - struct rt_phy_msg msg = {0, 0}; phy_device_t *phy_dev = (phy_device_t *)parameter; - rt_uint32_t i; - msg.reg = phy_dev->phy.reg_list[PHY_ID1_REG_IDX]; - while(phy_dev->phy.addr == 0xffff) + if (phy_dev->phy.ops->init(phy_dev->phy.bus->hw_obj, 0, PHY_MDIO_CSR_CLK_FREQ) != PHY_STATUS_OK) { - /* Search a PHY */ - for (i = 0; i <= 0x1f; i++) - { - ((rt_phy_t *)(phy_dev->phy.parent.user_data))->addr = i; - phy_dev->phy.parent.read(&(phy_dev->phy.parent), 0, &msg, 1); - if (msg.value == PHY_ID1) - { - phy_dev->phy.addr = i; - LOG_D("Found a PHY device[address:0x%02x].\n", phy_dev->phy.addr); - phy_dev->phy.ops->init(phy_dev->phy.bus->hw_obj, phy_dev->phy.addr, PHY_MDIO_CSR_CLK_FREQ); - return; - } - } + LOG_E("No any PHY device is detected! Please check your hardware!\n"); + } - phy_dev->phy.addr = 0xffff; - detected_count++; - rt_thread_mdelay(1000); + return; - if (detected_count > 3) - { - LOG_E("No any PHY device is detected! Please check your hardware!\n"); - return; - } - } } static void phy_monitor_thread_entry(void *args) @@ -287,7 +366,7 @@ static void phy_monitor_thread_entry(void *args) int phy_device_register(void) { - rt_err_t err = RT_ERROR; + rt_err_t err = -RT_ERROR; rt_thread_t thread_phy_monitor; /* Set ops for PHY */ @@ -308,10 +387,7 @@ int phy_device_register(void) s_gphys[i]->phy_dev->phy.bus = s_gphys[i]->mdio_bus; s_gphys[i]->phy_dev->phy.ops = &phy_ops; - /* Set PHY register list */ - s_gphys[i]->phy_dev->phy.reg_list = s_gphy_reg_list[i]; - - rt_hw_phy_register(&s_gphys[i]->phy_dev->phy, PHY_NAME); + rt_hw_phy_register(&s_gphys[i]->phy_dev->phy, NULL); } /* Start PHY monitor */ @@ -323,7 +399,7 @@ int phy_device_register(void) } else { - err = RT_ERROR; + err = -RT_ERROR; } return err; diff --git a/bsp/hpmicro/libraries/drivers/drv_enet_phy.h b/bsp/hpmicro/libraries/drivers/drv_enet_phy.h new file mode 100644 index 00000000000..77da6a4fdaa --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_enet_phy.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2023-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef DRV_ENET_PHY_H +#define DRV_ENET_PHY_H + +#include "hpm_ioc_regs.h" +#include + +#if defined(BSP_USING_ENET_PHY_DP83867) +#include "hpm_dp83867.h" +#endif + +#if defined(BSP_USING_ENET_PHY_RTL8211) +#include "hpm_rtl8211.h" +#endif + +#if defined(BSP_USING_ENET_PHY_DP83848) +#include "hpm_dp83848.h" +#endif + +#if defined(BSP_USING_ENET_PHY_RTL8201) +#include "hpm_rtl8201.h" +#endif + +#if defined(BSP_USING_ENET_PHY_LAN8720) +#include "hpm_lan8720.h" +#endif + +#ifndef PHY_AUTO_NEGO +#define PHY_AUTO_NEGO (1U) +#endif + +#ifndef PHY_MDIO_CSR_CLK_FREQ +#define PHY_MDIO_CSR_CLK_FREQ (200000000U) +#endif + +enum phy_link_status +{ + PHY_LINK_DOWN = 0U, + PHY_LINK_UP +}; + +typedef struct { + rt_uint32_t phy_speed; + rt_uint32_t phy_duplex; +} phy_info_t; + +typedef struct { + rt_uint32_t phy_link; + rt_phy_t phy; + phy_info_t phy_info; +} phy_device_t; + +#endif /* DRV_ENET_PHY_H */ + + + + diff --git a/bsp/hpmicro/libraries/drivers/drv_ewdt.c b/bsp/hpmicro/libraries/drivers/drv_ewdt.c new file mode 100644 index 00000000000..40a6502e7d1 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_ewdt.c @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include +#include +#include +#include "board.h" +#include "drv_ewdt.h" +#include "hpm_ewdg_drv.h" +#include "hpm_sysctl_drv.h" + + + +#ifdef BSP_USING_EWDG + +#define EWDG_CNT_CLK_FREQ 32768UL + + +typedef struct hpm_wdog +{ + EWDG_Type *wdog_base; + char *device_name; + clock_name_t clock_name; + uint32_t irq_num; + rt_watchdog_t *wdog; +}hpm_wdog_t; + +static rt_err_t hpm_wdog_init(rt_watchdog_t *wdt); +static rt_err_t hpm_wdog_open(rt_watchdog_t *wdt, rt_uint16_t oflag); +static rt_err_t hpm_wdog_close(rt_watchdog_t *wdt); +static rt_err_t hpm_wdog_refresh(rt_watchdog_t *wdt); +static rt_err_t hpm_wdog_control(rt_watchdog_t *wdt, int cmd, void *args); + +static void hpm_wdog_isr(rt_watchdog_t *wdt); + +#if defined(BSP_USING_EWDG0) +rt_watchdog_t wdog0; +void wdog0_isr(void) +{ + hpm_wdog_isr(&wdog0); +} +SDK_DECLARE_EXT_ISR_M(IRQn_EWDG0, wdog0_isr) +#endif + +#if defined(BSP_USING_EWDG1) +rt_watchdog_t wdog1; +void wdog1_isr(void) +{ + hpm_wdog_isr(&wdog1); +} +SDK_DECLARE_EXT_ISR_M(IRQn_EWDG1, wdog1_isr) +#endif + +#if defined(BSP_USING_EWDG2) +rt_watchdog_t wdog2; +void wdog2_isr(void) +{ + hpm_wdog_isr(&wdog2); +} +SDK_DECLARE_EXT_ISR_M(IRQn_EWDG2, wdog2_isr) +#endif + +#if defined(BSP_USING_EWDG3) +rt_watchdog_t wdog3; +void wdog3_isr(void) +{ + hpm_wdog_isr(&wdog3); +} +SDK_DECLARE_EXT_ISR_M(IRQn_EWDG3, wdog3_isr) +#endif + +static hpm_wdog_t wdogs[] = { +#ifdef BSP_USING_EWDG0 + { + .wdog_base = HPM_EWDG0, + .device_name = "wdt0", + .clock_name = clock_watchdog0, + .irq_num = IRQn_EWDG0, + .wdog = &wdog0, + }, +#endif + +#ifdef BSP_USING_EWDG1 + { + .wdog_base = HPM_EWDG1, + .device_name = "wdt1", + .clock_name = clock_watchdog1, + .irq_num = IRQn_EWDG1, + .wdog = &wdog1, + }, +#endif + +#ifdef BSP_USING_EWDG2 + { + .wdog_base = HPM_EWDG2, + .device_name = "wdt2", + .clock_name = clock_watchdog2, + .irq_num = IRQn_EWDG2, + .wdog = &wdog2, + }, +#endif + +#ifdef BSP_USING_EWDG3 + { + .wdog_name = HPM_EWDG3, + .device_name = "wdt3", + .clock_name = clock_watchdog3, + .irq_num = IRQn_EWDG3, + .wdog = &wdog3, + }, +#endif +}; + +static struct rt_watchdog_ops hpm_wdog_ops = { + .init = hpm_wdog_init, + .control = hpm_wdog_control, +}; + +static rt_err_t hpm_wdog_init(rt_watchdog_t *wdt) +{ + hpm_wdog_t *hpm_wdog = (hpm_wdog_t*)wdt->parent.user_data; + EWDG_Type *base = hpm_wdog->wdog_base; + + ewdg_config_t config; + + printf("Init Watchdog\n"); + ewdg_get_default_config(base, &config); + /* Enable EWDG */ + config.enable_watchdog = true; + config.ctrl_config.use_lowlevel_timeout = false; + /* Enable EWDG Timeout Reset */ + config.int_rst_config.enable_timeout_reset = true; + /* Set EWDG Count clock source to OSC32 */ + config.ctrl_config.cnt_clk_sel = ewdg_cnt_clk_src_ext_osc_clk; + + /* Set the EWDG reset timeout to 101ms */ + config.cnt_src_freq = EWDG_CNT_CLK_FREQ; + config.ctrl_config.timeout_reset_us = 101UL * 1000UL; + + ewdg_init(base, &config); + + return RT_EOK; +} + +static rt_err_t hpm_wdog_open(rt_watchdog_t *wdt, rt_uint16_t oflag) +{ + hpm_wdog_t *hpm_wdog = (hpm_wdog_t*)wdt->parent.user_data; + EWDG_Type *base = hpm_wdog->wdog_base; + + rt_enter_critical(); + ewdg_enable(base); + rt_exit_critical(); +} + +static rt_err_t hpm_wdog_close(rt_watchdog_t *wdt) +{ + hpm_wdog_t *hpm_wdog = (hpm_wdog_t*)wdt->parent.user_data; + EWDG_Type *base = hpm_wdog->wdog_base; + + rt_enter_critical(); + ewdg_disable(base); + rt_exit_critical(); + + return RT_EOK; +} + +static rt_err_t hpm_wdog_refresh(rt_watchdog_t *wdt) +{ + hpm_wdog_t *hpm_wdog = (hpm_wdog_t*)wdt->parent.user_data; + EWDG_Type *base = hpm_wdog->wdog_base; + + rt_enter_critical(); + ewdg_refresh(base); + rt_exit_critical(); + + return RT_EOK; +} + +static rt_err_t hpm_wdog_control(rt_watchdog_t *wdt, int cmd, void *args) +{ + rt_err_t ret = RT_EOK; + + hpm_wdog_t *hpm_wdog = (hpm_wdog_t*)wdt->parent.user_data; + EWDG_Type *base = hpm_wdog->wdog_base; + + ewdg_config_t config; + + uint32_t temp; + switch (cmd) + { + case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: + RT_ASSERT(*(uint32_t *)args != 0); + temp = *(uint32_t *)args; + temp *= 1000000U; /* Convert to microseconds */ + + ewdg_get_default_config(base, &config); + config.enable_watchdog = true; + config.int_rst_config.enable_timeout_reset = true; + config.ctrl_config.use_lowlevel_timeout = false; + uint32_t ewdg_src_clk_freq = EWDG_CNT_CLK_FREQ; + config.ctrl_config.cnt_clk_sel = ewdg_cnt_clk_src_ext_osc_clk; + + /* Set the EWDG reset timeout to 1 second */ + config.cnt_src_freq = ewdg_src_clk_freq; + config.ctrl_config.timeout_reset_us = temp; + + /* Initialize the EWDG */ + hpm_stat_t status = ewdg_init(base, &config); + if (status != status_success) { + printf(" EWDG initialization failed, error_code=%d\n", status); + } + /* delay 1ms to ensure above configure take effective*/ + rt_thread_mdelay(1); + break; + case RT_DEVICE_CTRL_WDT_KEEPALIVE: + hpm_wdog_refresh(wdt); + break; + case RT_DEVICE_CTRL_WDT_START: + hpm_wdog_open(wdt, *(uint16_t*)args); + break; + case RT_DEVICE_CTRL_WDT_STOP: + hpm_wdog_close(wdt); + break; + default: + ret = RT_EINVAL; + break; + } + + return RT_EOK; +} + +void hpm_wdog_isr(rt_watchdog_t *wdt) +{ + hpm_wdog_t *hpm_wdog = (hpm_wdog_t*)wdt->parent.user_data; + EWDG_Type *base = hpm_wdog->wdog_base; + + uint32_t ewdg_stat = ewdg_get_status_flags(base); + + if ((ewdg_stat & EWDG_INT_TIMEOUT) != 0) { + ewdg_refresh(base); + } + ewdg_clear_status_flags(base, ewdg_stat); +} + +int rt_hw_wdt_init(void) +{ + rt_err_t err = RT_EOK; + +#if defined(BSP_USING_EWDG) + for (uint32_t i = 0; i < sizeof(wdogs) / sizeof(wdogs[0]); i++) + { + wdogs[i].wdog->ops = &hpm_wdog_ops; + clock_add_to_group(wdogs[i].clock_name, 0); + err = rt_hw_watchdog_register(wdogs[i].wdog, wdogs[i].device_name, RT_DEVICE_FLAG_RDWR, (void *)&wdogs[i]); + if (err != RT_EOK) + { + LOG_E("rt device %s failed, status=%d\n", wdogs[i].device_name, err); + } + } +#endif + return err; +} + +INIT_BOARD_EXPORT(rt_hw_wdt_init); +#endif /* RT_USING_WDT */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/drivers/drv_ewdt.h b/bsp/hpmicro/libraries/drivers/drv_ewdt.h new file mode 100644 index 00000000000..4c69255af0f --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_ewdt.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef DRV_WDT_H +#define DRV_WDT_H + + +int rt_hw_wdt_init(void); + +#endif \ No newline at end of file diff --git a/bsp/hpmicro/libraries/drivers/drv_gpio.c b/bsp/hpmicro/libraries/drivers/drv_gpio.c index 6877fa607af..9a4e879bd71 100644 --- a/bsp/hpmicro/libraries/drivers/drv_gpio.c +++ b/bsp/hpmicro/libraries/drivers/drv_gpio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -9,6 +9,9 @@ * 2022-07-28 HPMicro Fixed compiling warnings * 2023-05-08 HPMicro Adapt RT-Thread V5.0.0 * 2023-08-15 HPMicro Enable pad loopback feature + * 2024-01-08 HPMicro Implemented pin_get + * 2024-04-17 HPMicro Refined pin irq implementation + * 2024-05-31 HPMicro Adapt later PIN driver framework */ #include @@ -23,49 +26,105 @@ #include "hpm_clock_drv.h" #include "hpm_soc_feature.h" + typedef struct { uint32_t gpio_idx; uint32_t irq_num; + struct rt_pin_irq_hdr *pin_irq_tbl; } gpio_irq_map_t; +#ifdef IRQn_GPIO0_A +static struct rt_pin_irq_hdr hpm_gpio0_a_pin_hdr[32]; +#endif +#ifdef IRQn_GPIO0_B +static struct rt_pin_irq_hdr hpm_gpio0_b_pin_hdr[32]; +#endif +#ifdef IRQn_GPIO0_C +static struct rt_pin_irq_hdr hpm_gpio0_c_pin_hdr[32]; +#endif +#ifdef IRQn_GPIO0_D +static struct rt_pin_irq_hdr hpm_gpio0_d_pin_hdr[32]; +#endif +#ifdef IRQn_GPIO0_E +static struct rt_pin_irq_hdr hpm_gpio0_e_pin_hdr[32]; +#endif +#ifdef IRQn_GPIO0_F +static struct rt_pin_irq_hdr hpm_gpio0_f_pin_hdr[32]; +#endif +#ifdef IRQn_GPIO0_V +static struct rt_pin_irq_hdr hpm_gpio0_v_pin_hdr[32]; +#endif +#ifdef IRQn_GPIO0_W +static struct rt_pin_irq_hdr hpm_gpio0_w_pin_hdr[32]; +#endif +#ifdef IRQn_GPIO0_X +static struct rt_pin_irq_hdr hpm_gpio0_x_pin_hdr[32]; +#endif +#ifdef IRQn_GPIO0_Y +static struct rt_pin_irq_hdr hpm_gpio0_y_pin_hdr[32]; +#endif +#ifdef IRQn_GPIO0_Z +static struct rt_pin_irq_hdr hpm_gpio0_z_pin_hdr[32]; +#endif + static const gpio_irq_map_t hpm_gpio_irq_map[] = { #ifdef IRQn_GPIO0_A - { GPIO_IE_GPIOA, IRQn_GPIO0_A }, + { GPIO_IE_GPIOA, IRQn_GPIO0_A, hpm_gpio0_a_pin_hdr }, #endif #ifdef IRQn_GPIO0_B - { GPIO_IE_GPIOB, IRQn_GPIO0_B }, + { GPIO_IE_GPIOB, IRQn_GPIO0_B, hpm_gpio0_b_pin_hdr }, #endif #ifdef IRQn_GPIO0_C - { GPIO_IE_GPIOC, IRQn_GPIO0_C }, + { GPIO_IE_GPIOC, IRQn_GPIO0_C, hpm_gpio0_c_pin_hdr }, #endif -#ifdef GPIO_IE_GPIOD - { GPIO_IE_GPIOD, IRQn_GPIO0_D }, +#ifdef IRQn_GPIO0_D + { GPIO_IE_GPIOD, IRQn_GPIO0_D, hpm_gpio0_d_pin_hdr }, #endif #ifdef IRQn_GPIO0_E - { GPIO_IE_GPIOE, IRQn_GPIO0_E }, + { GPIO_IE_GPIOE, IRQn_GPIO0_E, hpm_gpio0_e_pin_hdr }, #endif #ifdef IRQn_GPIO0_F - { GPIO_IE_GPIOF, IRQn_GPIO0_F }, + { GPIO_IE_GPIOF, IRQn_GPIO0_F, hpm_gpio0_f_pin_hdr }, +#endif +#ifdef IRQn_GPIO0_V + { GPIO_IE_GPIOV, IRQn_GPIO0_V, hpm_gpio0_v_pin_hdr }, +#endif +#ifdef IRQn_GPIO0_W + { GPIO_IE_GPIOW, IRQn_GPIO0_W, hpm_gpio0_w_pin_hdr }, #endif #ifdef IRQn_GPIO0_X - { GPIO_IE_GPIOX, IRQn_GPIO0_X }, + { GPIO_IE_GPIOX, IRQn_GPIO0_X, hpm_gpio0_x_pin_hdr }, #endif #ifdef IRQn_GPIO0_Y - { GPIO_IE_GPIOY, IRQn_GPIO0_Y }, + { GPIO_IE_GPIOY, IRQn_GPIO0_Y, hpm_gpio0_y_pin_hdr }, #endif #ifdef IRQn_GPIO0_Z - { GPIO_IE_GPIOZ, IRQn_GPIO0_Z }, + { GPIO_IE_GPIOZ, IRQn_GPIO0_Z, hpm_gpio0_z_pin_hdr }, #endif - }; +}; -static struct rt_pin_irq_hdr hpm_gpio_pin_hdr_tbl[IOC_SOC_PAD_MAX]; +static struct rt_pin_irq_hdr *lookup_pin_irq_hdr_tbl(rt_base_t pin) +{ + struct rt_pin_irq_hdr *pin_irq_hdr_tbl = RT_NULL; + uint32_t gpio_idx = pin >> 5; -static int hpm_get_gpi_irq_num(uint32_t gpio_idx) + for (uint32_t i = 0; i < ARRAY_SIZE(hpm_gpio_irq_map); i++) + { + if (hpm_gpio_irq_map[i].gpio_idx == gpio_idx) + { + pin_irq_hdr_tbl = hpm_gpio_irq_map[i].pin_irq_tbl; + break; + } + } + return pin_irq_hdr_tbl; +} + +static int hpm_get_gpio_irq_num(uint32_t gpio_idx) { int irq_num = -1; - for (uint32_t i = 0; i < sizeof(hpm_gpio_irq_map) / sizeof(hpm_gpio_irq_map[0]); i++) + for (uint32_t i = 0; i < ARRAY_SIZE(hpm_gpio_irq_map); i++) { if (hpm_gpio_irq_map[i].gpio_idx == gpio_idx) { @@ -76,24 +135,34 @@ static int hpm_get_gpi_irq_num(uint32_t gpio_idx) return irq_num; } -static void hpm_gpio_isr(uint32_t gpio_index, GPIO_Type *base) +static void hpm_gpio_isr(uint32_t gpio_idx, GPIO_Type *base) { - uint32_t pin_idx = 0; - for(pin_idx = 0; pin_idx < 32; pin_idx++) + /* Lookup the Pin IRQ Header Table */ + struct rt_pin_irq_hdr *pin_irq_hdr = RT_NULL; + for (uint32_t i = 0; i < ARRAY_SIZE(hpm_gpio_irq_map); i++) + { + if (hpm_gpio_irq_map[i].gpio_idx == gpio_idx) + { + pin_irq_hdr = hpm_gpio_irq_map[i].pin_irq_tbl; + break; + } + } + + for(uint32_t pin_idx = 0; pin_idx < 32; pin_idx++) { - if (gpio_check_pin_interrupt_flag(base, gpio_index, pin_idx)) + if (gpio_check_pin_interrupt_flag(base, gpio_idx, pin_idx)) { - uint32_t pin = gpio_index * 32U + pin_idx; - gpio_clear_pin_interrupt_flag(base, gpio_index, pin_idx); - if (hpm_gpio_pin_hdr_tbl[pin].hdr != RT_NULL) + gpio_clear_pin_interrupt_flag(base, gpio_idx, pin_idx); + + if (pin_irq_hdr[pin_idx].hdr != RT_NULL) { - hpm_gpio_pin_hdr_tbl[pin].hdr(hpm_gpio_pin_hdr_tbl[pin].args); + pin_irq_hdr[pin_idx].hdr(pin_irq_hdr[pin_idx].args); } } } } -#ifdef GPIO_IF_GPIOA +#ifdef IRQn_GPIO0_A void gpioa_isr(void) { hpm_gpio_isr(GPIO_IF_GPIOA, HPM_GPIO0); @@ -101,7 +170,7 @@ void gpioa_isr(void) SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_A, gpioa_isr) #endif -#ifdef GPIO_IF_GPIOB +#ifdef IRQn_GPIO0_B void gpiob_isr(void) { hpm_gpio_isr(GPIO_IF_GPIOB, HPM_GPIO0); @@ -109,7 +178,7 @@ void gpiob_isr(void) SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_B, gpiob_isr) #endif -#ifdef GPIO_IF_GPIOC +#ifdef IRQn_GPIO0_C void gpioc_isr(void) { hpm_gpio_isr(GPIO_IF_GPIOC, HPM_GPIO0); @@ -117,7 +186,7 @@ void gpioc_isr(void) SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_C, gpioc_isr) #endif -#ifdef GPIO_IF_GPIOD +#ifdef IRQn_GPIO0_D void gpiod_isr(void) { hpm_gpio_isr(GPIO_IF_GPIOD, HPM_GPIO0); @@ -125,7 +194,7 @@ void gpiod_isr(void) SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_D, gpiod_isr) #endif -#ifdef GPIO_IF_GPIOE +#ifdef IRQn_GPIO0_E void gpioe_isr(void) { hpm_gpio_isr(GPIO_IF_GPIOE, HPM_GPIO0); @@ -133,7 +202,7 @@ void gpioe_isr(void) SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_E, gpioe_isr) #endif -#ifdef GPIO_IF_GPIOF +#ifdef IRQn_GPIO0_F void gpiof_isr(void) { hpm_gpio_isr(GPIO_IF_GPIOF, HPM_GPIO0); @@ -141,7 +210,23 @@ void gpiof_isr(void) SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_F, gpiof_isr) #endif -#ifdef GPIO_IF_GPIOX +#ifdef IRQn_GPIO0_V +void gpiox_isr(void) +{ + hpm_gpio_isr(GPIO_IF_GPIOV, HPM_GPIO0); +} +SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_V, gpiox_isr) +#endif + +#ifdef IRQn_GPIO0_W +void gpiox_isr(void) +{ + hpm_gpio_isr(GPIO_IF_GPIOW, HPM_GPIO0); +} +SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_W, gpiox_isr) +#endif + +#ifdef IRQn_GPIO0_X void gpiox_isr(void) { hpm_gpio_isr(GPIO_IF_GPIOX, HPM_GPIO0); @@ -149,7 +234,7 @@ void gpiox_isr(void) SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_X, gpiox_isr) #endif -#ifdef GPIO_IF_GPIOY +#ifdef IRQn_GPIO0_Y void gpioy_isr(void) { hpm_gpio_isr(GPIO_IF_GPIOY, HPM_GPIO0); @@ -157,7 +242,7 @@ void gpioy_isr(void) SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_Y, gpioy_isr) #endif -#ifdef GPIO_IF_GPIOZ +#ifdef IRQn_GPIO0_Z void gpioz_isr(void) { hpm_gpio_isr(GPIO_IF_GPIOZ, HPM_GPIO0); @@ -165,6 +250,29 @@ void gpioz_isr(void) SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_Z, gpioz_isr) #endif +/** + * @brief Get Pin index from name + * + * Name rule is : + * for example: PA00, PZ03 + * + **/ +static rt_base_t hpm_pin_get(const char *name) +{ + if (!( (rt_strlen(name) == 4) && + (name[0] == 'P') && + ((('A' <= name[1]) && (name[1] <= 'F')) || (('V' <= name[1]) && (name[1] <= 'Z'))) && + (('0' <= name[2]) && (name[2] <= '9')) && + (('0' <= name[3]) && (name[3] <= '9')) + )) + { + return -RT_EINVAL; + } + + uint32_t gpio_idx = (name[1] <= 'F') ? (name[1] - 'A') : (11 + name[1] - 'V'); + uint32_t pin_idx = (uint32_t)(name[2] - '0') * 10 + (name[3] - '0'); + return (gpio_idx * 32 + pin_idx); +} static void hpm_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) { @@ -182,7 +290,9 @@ static void hpm_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) HPM_PIOC->PAD[pin].FUNC_CTL = 3; break; case GPIO_DI_GPIOZ : +#ifdef HPM_BIOC HPM_BIOC->PAD[pin].FUNC_CTL = 3; +#endif break; default : break; @@ -241,13 +351,18 @@ static rt_err_t hpm_pin_attach_irq(struct rt_device *device, void (*hdr)(void *args), void *args) { + struct rt_pin_irq_hdr *pin_irq_hdr_tbl = lookup_pin_irq_hdr_tbl(pin); + if (pin_irq_hdr_tbl == RT_NULL) + { + return -RT_EINVAL; + } - rt_base_t level; - level = rt_hw_interrupt_disable(); - hpm_gpio_pin_hdr_tbl[pin].pin = pin; - hpm_gpio_pin_hdr_tbl[pin].hdr = hdr; - hpm_gpio_pin_hdr_tbl[pin].mode = mode; - hpm_gpio_pin_hdr_tbl[pin].args = args; + rt_base_t level = rt_hw_interrupt_disable(); + uint32_t pin_idx = pin & 0x1FUL; + pin_irq_hdr_tbl[pin_idx].pin = pin; + pin_irq_hdr_tbl[pin_idx].hdr = hdr; + pin_irq_hdr_tbl[pin_idx].mode = mode; + pin_irq_hdr_tbl[pin_idx].args = args; rt_hw_interrupt_enable(level); return RT_EOK; @@ -255,12 +370,17 @@ static rt_err_t hpm_pin_attach_irq(struct rt_device *device, static rt_err_t hpm_pin_detach_irq(struct rt_device *device, rt_base_t pin) { - rt_base_t level; - level = rt_hw_interrupt_disable(); - hpm_gpio_pin_hdr_tbl[pin].pin = -1; - hpm_gpio_pin_hdr_tbl[pin].hdr = RT_NULL; - hpm_gpio_pin_hdr_tbl[pin].mode = 0; - hpm_gpio_pin_hdr_tbl[pin].args = RT_NULL; + struct rt_pin_irq_hdr *pin_irq_hdr_tbl = lookup_pin_irq_hdr_tbl(pin); + if (pin_irq_hdr_tbl == RT_NULL) + { + return -RT_EINVAL; + } + rt_base_t level = rt_hw_interrupt_disable(); + uint32_t pin_idx = pin & 0x1FUL; + pin_irq_hdr_tbl[pin_idx].pin = -1; + pin_irq_hdr_tbl[pin_idx].hdr = RT_NULL; + pin_irq_hdr_tbl[pin_idx].mode = 0; + pin_irq_hdr_tbl[pin_idx].args = RT_NULL; rt_hw_interrupt_enable(level); return RT_EOK; @@ -272,10 +392,16 @@ static rt_err_t hpm_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_u uint32_t gpio_idx = pin >> 5; uint32_t pin_idx = pin & 0x1FU; + struct rt_pin_irq_hdr *pin_irq_hdr_tbl = lookup_pin_irq_hdr_tbl(pin); + if (pin_irq_hdr_tbl == RT_NULL) + { + return -RT_EINVAL; + } + gpio_interrupt_trigger_t trigger; if (enabled == PIN_IRQ_ENABLE) { - switch(hpm_gpio_pin_hdr_tbl[pin].mode) + switch(pin_irq_hdr_tbl[pin_idx].mode) { case PIN_IRQ_MODE_RISING: trigger = gpio_interrupt_trigger_edge_rising; @@ -294,7 +420,7 @@ static rt_err_t hpm_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_u break; } gpio_config_pin_interrupt(HPM_GPIO0, gpio_idx, pin_idx, trigger); - uint32_t irq_num = hpm_get_gpi_irq_num(gpio_idx); + uint32_t irq_num = hpm_get_gpio_irq_num(gpio_idx); gpio_enable_pin_interrupt(HPM_GPIO0, gpio_idx, pin_idx); intc_m_enable_irq_with_priority(irq_num, 1); } @@ -304,20 +430,20 @@ static rt_err_t hpm_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_u } else { - return RT_EINVAL; + return -RT_EINVAL; } return RT_EOK; } -const static struct rt_pin_ops hpm_pin_ops = -{ - .pin_mode = hpm_pin_mode, - .pin_write = hpm_pin_write, - .pin_read = hpm_pin_read, - .pin_attach_irq = hpm_pin_attach_irq, - .pin_detach_irq = hpm_pin_detach_irq, - .pin_irq_enable = hpm_pin_irq_enable +const static struct rt_pin_ops hpm_pin_ops = { + .pin_mode = hpm_pin_mode, + .pin_write = hpm_pin_write, + .pin_read = hpm_pin_read, + .pin_attach_irq = hpm_pin_attach_irq, + .pin_detach_irq = hpm_pin_detach_irq, + .pin_irq_enable = hpm_pin_irq_enable, + .pin_get = hpm_pin_get, }; int rt_hw_pin_init(void) diff --git a/bsp/hpmicro/libraries/drivers/drv_hwtimer.c b/bsp/hpmicro/libraries/drivers/drv_hwtimer.c index 64198914566..5b6118f69c8 100644 --- a/bsp/hpmicro/libraries/drivers/drv_hwtimer.c +++ b/bsp/hpmicro/libraries/drivers/drv_hwtimer.c @@ -14,6 +14,7 @@ #include "board.h" #include "hpm_gptmr_drv.h" + typedef struct _hpm_gptimer { GPTMR_Type *base; @@ -168,10 +169,10 @@ SDK_DECLARE_EXT_ISR_M(IRQn_GPTMR7, gptmr7_isr); static void hpm_hwtmr_isr(hpm_gptimer_t *timer) { uint32_t hwtmr_stat = gptmr_get_status(timer->base); - if ((hwtmr_stat & GPTMR_CH_CMP_STAT_MASK(0, 0)) != 0U) + if ((hwtmr_stat & GPTMR_CH_RLD_STAT_MASK(timer->channel)) != 0U) { rt_device_hwtimer_isr(&timer->timer); - gptmr_clear_status(timer->base, GPTMR_CH_CMP_STAT_MASK(0, 0)); + gptmr_clear_status(timer->base, GPTMR_CH_RLD_STAT_MASK(timer->channel)); } } diff --git a/bsp/hpmicro/libraries/drivers/drv_i2c.c b/bsp/hpmicro/libraries/drivers/drv_i2c.c index 17b178c0337..425eda368e2 100644 --- a/bsp/hpmicro/libraries/drivers/drv_i2c.c +++ b/bsp/hpmicro/libraries/drivers/drv_i2c.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 HPMicro + * Copyright (c) 2022-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -11,16 +11,32 @@ #ifdef BSP_USING_I2C #include "drv_i2c.h" #include "hpm_i2c_drv.h" +#include "hpm_dma_mgr.h" +#include "hpm_dmamux_drv.h" +#include "hpm_l1c_drv.h" #include "board.h" + #ifdef RT_USING_I2C +#define HPM_RTT_DRV_RETRY_TIMEOUT (1000000) + +#ifndef HPM_I2C_DRV_DEFAULT_RETRY_COUNT +#define HPM_I2C_DRV_DEFAULT_RETRY_COUNT (5000U) +#endif + struct hpm_i2c { struct rt_i2c_bus_device bus; I2C_Type *base; clock_name_t clk_name; char *bus_name; + rt_sem_t xfer_sem; + rt_bool_t enable_dma; + rt_uint8_t dmamux; + dma_resource_t dma; + rt_uint8_t i2c_irq; + rt_uint8_t is_read; }; static struct hpm_i2c hpm_i2cs[] = @@ -30,6 +46,11 @@ static struct hpm_i2c hpm_i2cs[] = .base = HPM_I2C0, .bus_name = "i2c0", .clk_name = clock_i2c0, +#if defined(BSP_I2C0_USING_DMA) + .enable_dma = RT_TRUE, +#endif + .dmamux = HPM_DMA_SRC_I2C0, + .i2c_irq = IRQn_I2C0, }, #endif #if defined(BSP_USING_I2C1) @@ -37,6 +58,11 @@ static struct hpm_i2c hpm_i2cs[] = .base = HPM_I2C1, .bus_name = "i2c1", .clk_name = clock_i2c1, +#if defined(BSP_I2C1_USING_DMA) + .enable_dma = RT_TRUE, +#endif + .dmamux = HPM_DMA_SRC_I2C1, + .i2c_irq = IRQn_I2C1, }, #endif #if defined(BSP_USING_I2C2) @@ -44,6 +70,11 @@ static struct hpm_i2c hpm_i2cs[] = .base = HPM_I2C2, .bus_name = "i2c2", .clk_name = clock_i2c2, +#if defined(BSP_I2C2_USING_DMA) + .enable_dma = RT_TRUE, +#endif + .dmamux = HPM_DMA_SRC_I2C2, + .i2c_irq = IRQn_I2C2, }, #endif #if defined(BSP_USING_I2C3) @@ -51,12 +82,19 @@ static struct hpm_i2c hpm_i2cs[] = .base = HPM_I2C3, .bus_name = "i2c3", .clk_name = clock_i2c3, +#if defined(BSP_I2C3_USING_DMA) + .enable_dma = RT_TRUE, +#endif + .dmamux = HPM_DMA_SRC_I2C3, + .i2c_irq = IRQn_I2C3, }, #endif }; - +static hpm_stat_t i2c_transfer(I2C_Type *ptr, const uint16_t device_address, + uint8_t *buf, const uint32_t size, uint16_t flags); static rt_ssize_t hpm_i2c_master_transfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num); - +static hpm_stat_t i2c_tx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, I2C_Type *i2c_ptr, uint32_t src, uint32_t size); +static hpm_stat_t i2c_rx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, I2C_Type *i2c_ptr, uint32_t dst, uint32_t size); struct rt_i2c_bus_device_ops hpm_i2c_ops = { @@ -65,6 +103,205 @@ struct rt_i2c_bus_device_ops hpm_i2c_ops = RT_NULL }; +static inline void handle_i2c_isr(I2C_Type *ptr) +{ + volatile uint32_t irq_status; + RT_ASSERT(ptr != RT_NULL); + rt_base_t level; + level = rt_hw_interrupt_disable(); + irq_status = i2c_get_status(ptr); + if (irq_status & I2C_EVENT_TRANSACTION_COMPLETE) + { + for (uint32_t i = 0; i < sizeof(hpm_i2cs) / sizeof(hpm_i2cs[0]); i++) + { + if (hpm_i2cs[i].base == ptr) + { + rt_sem_release(hpm_i2cs[i].xfer_sem); + } + } + i2c_disable_irq(ptr, I2C_EVENT_TRANSACTION_COMPLETE); + i2c_clear_status(ptr, I2C_EVENT_TRANSACTION_COMPLETE); + } + rt_hw_interrupt_enable(level); +} + +#if defined(BSP_USING_I2C0) +void i2c0_isr(void) +{ + handle_i2c_isr(HPM_I2C0); +} +SDK_DECLARE_EXT_ISR_M(IRQn_I2C0, i2c0_isr); +#endif + +#if defined(BSP_USING_I2C1) +void i2c1_isr(void) +{ + handle_i2c_isr(HPM_I2C1); +} +SDK_DECLARE_EXT_ISR_M(IRQn_I2C1, i2c1_isr); +#endif + +#if defined(BSP_USING_I2C2) +void i2c2_isr(void) +{ + handle_i2c_isr(HPM_I2C2); +} +SDK_DECLARE_EXT_ISR_M(IRQn_I2C2, i2c2_isr); +#endif + +#if defined(BSP_USING_I2C3) +void i2c3_isr(void) +{ + handle_i2c_isr(HPM_I2C3); +} +SDK_DECLARE_EXT_ISR_M(IRQn_I2C3, i2c3_isr); +#endif + +static hpm_stat_t i2c_transfer(I2C_Type *ptr, const uint16_t device_address, + uint8_t *buf, const uint32_t size, uint16_t flags) +{ + uint32_t ctrl = 0; + uint32_t retry = 0; + uint32_t left = 0; + if (((size == 0) || (size > I2C_SOC_TRANSFER_COUNT_MAX))) { + return status_invalid_argument; + } + /* W1C, clear CMPL bit to avoid blocking the transmission */ + ptr->STATUS = I2C_STATUS_CMPL_MASK; + ptr->CMD = I2C_CMD_CLEAR_FIFO; + ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); + + if (flags & RT_I2C_RD) { + ctrl |= I2C_CTRL_DIR_SET(I2C_DIR_MASTER_READ); + } else { + ctrl |= I2C_CTRL_DIR_SET(I2C_DIR_MASTER_WRITE);/* is write flag */ + } + /* no start signal send*/ + if (flags & RT_I2C_NO_START) { + ctrl |= I2C_CTRL_PHASE_START_SET(false) | I2C_CTRL_PHASE_STOP_SET(true) \ + | I2C_CTRL_PHASE_ADDR_SET(true); + } else if (flags & RT_I2C_NO_STOP) { /* no end signal send*/ + ctrl |= I2C_CTRL_PHASE_START_SET(true) | I2C_CTRL_PHASE_STOP_SET(false) \ + | I2C_CTRL_PHASE_ADDR_SET(true); + } else { + ctrl |= I2C_CTRL_PHASE_START_SET(true) | I2C_CTRL_PHASE_STOP_SET(true) \ + | I2C_CTRL_PHASE_ADDR_SET(true); + } + ptr->CTRL = ctrl | I2C_CTRL_PHASE_DATA_SET(true) \ + | I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(size) >> 8U) \ + | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); + /* disable auto ack */ + ptr->INTEN |= I2C_EVENT_BYTE_RECEIVED; + ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; + retry = 0; + left = size; + if (flags & RT_I2C_RD) { + while (left) { + if (!(ptr->STATUS & I2C_STATUS_FIFOEMPTY_MASK)) { + *(buf++) = ptr->DATA; + left--; + if (left == 0) { + ptr->CMD = I2C_CMD_NACK; + } else { + /* ACK is sent when reading */ + if (!(flags & RT_I2C_NO_READ_ACK)) { + ptr->CMD = I2C_CMD_ACK; + } + } + retry = 0; + } else { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + } else { + while (left) { + if (!(ptr->STATUS & I2C_STATUS_FIFOFULL_MASK)) { + ptr->DATA = *(buf++); + left--; + retry = 0; + } else { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + } + retry = 0; + while (!(ptr->STATUS & I2C_STATUS_CMPL_MASK)) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + }; + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + + if (i2c_get_data_count(ptr) && (size)) { + return status_i2c_transmit_not_completed; + } +} + +static hpm_stat_t i2c_tx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, I2C_Type *i2c_ptr, uint32_t src, uint32_t size) +{ + dma_handshake_config_t config; + + dma_default_handshake_config(dma_ptr, &config); + config.ch_index = ch_num; + config.dst = (uint32_t)&i2c_ptr->DATA; + config.dst_fixed = true; + config.src = src; + config.src_fixed = false; + config.data_width = DMA_TRANSFER_WIDTH_BYTE; + config.size_in_byte = size; + + return dma_setup_handshake(dma_ptr, &config, true); +} + +static hpm_stat_t i2c_rx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, I2C_Type *i2c_ptr, uint32_t dst, uint32_t size) +{ + dma_handshake_config_t config; + + dma_default_handshake_config(dma_ptr, &config); + config.ch_index = ch_num; + config.dst = dst; + config.dst_fixed = false; + config.src = (uint32_t)&i2c_ptr->DATA; + config.src_fixed = true; + config.data_width = DMA_TRANSFER_WIDTH_BYTE; + config.size_in_byte = size; + + return dma_setup_handshake(dma_ptr, &config, true); +} + +void i2c_dma_channel_tc_callback(DMA_Type *ptr, uint32_t channel, void *user_data) +{ + struct hpm_i2c *i2c = (struct hpm_i2c *)user_data; + RT_ASSERT(i2c != RT_NULL); + RT_ASSERT(ptr != RT_NULL); + rt_base_t level; + level = rt_hw_interrupt_disable(); + if ((i2c->dma.base == ptr) && i2c->dma.channel == channel) + { + dma_mgr_disable_chn_irq(&i2c->dma, DMA_MGR_INTERRUPT_MASK_TC); + if (i2c->is_read == true) + { + rt_sem_release(i2c->xfer_sem); + } + } + rt_hw_interrupt_enable(level); +} + static rt_ssize_t hpm_i2c_master_transfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num) { RT_ASSERT(bus != RT_NULL); @@ -76,10 +313,43 @@ static rt_ssize_t hpm_i2c_master_transfer(struct rt_i2c_bus_device *bus, struct hpm_stat_t i2c_stat = status_success; rt_size_t ret = 0; rt_uint32_t i; - + rt_uint8_t *raw_alloc_buf = RT_NULL; + rt_uint8_t *aligned_buf = RT_NULL; + rt_uint8_t *dummy_buf = RT_NULL; + rt_uint32_t aligned_len = 0; + rt_uint32_t remaining_size = 0; + rt_uint32_t transfer_len; for (i = 0; i < num; i++) { msg = &msgs[i]; + remaining_size = msg->len; + if ((msg->len > 0) && (i2c_info->enable_dma)) + { + aligned_len = (msg->len + HPM_L1C_CACHELINE_SIZE - 1U) & ~(HPM_L1C_CACHELINE_SIZE - 1U); + if (l1c_dc_is_enabled()) + { + if (msg->flags & RT_I2C_RD) + { + /* The allocated pointer is always RT_ALIGN_SIZE aligned */ + raw_alloc_buf = (uint8_t*)rt_malloc(aligned_len + HPM_L1C_CACHELINE_SIZE - RT_ALIGN_SIZE); + RT_ASSERT(raw_alloc_buf != RT_NULL); + } + else + { + aligned_buf = (uint8_t*)HPM_L1C_CACHELINE_ALIGN_UP((uint32_t)raw_alloc_buf); + /* The allocated pointer is always RT_ALIGN_SIZE aligned */ + raw_alloc_buf = (uint8_t*)rt_malloc(aligned_len + HPM_L1C_CACHELINE_SIZE - RT_ALIGN_SIZE); + RT_ASSERT(raw_alloc_buf != RT_NULL); + aligned_buf = (uint8_t*)HPM_L1C_CACHELINE_ALIGN_UP((uint32_t)raw_alloc_buf); + rt_memcpy(aligned_buf, msg->buf, msg->len); + l1c_dc_flush((uint32_t)aligned_buf, aligned_len); + } + } + } + else + { + aligned_buf = (uint8_t*) msg->buf; + } if (msg->flags & RT_I2C_ADDR_10BIT) { @@ -89,16 +359,111 @@ static rt_ssize_t hpm_i2c_master_transfer(struct rt_i2c_bus_device *bus, struct { i2c_enable_10bit_address_mode(i2c_info->base, false); } - + dummy_buf = aligned_buf; if (msg->flags & RT_I2C_RD) { - i2c_stat = i2c_master_read(i2c_info->base, msg->addr, msg->buf, msg->len); + /* maybe probe i2c device */ + if (msg->len == 0) + { + i2c_stat = i2c_master_read(i2c_info->base, msg->addr, dummy_buf, remaining_size); + } + else + { + while (remaining_size) + { + transfer_len = MIN(I2C_SOC_TRANSFER_COUNT_MAX, remaining_size); + if ((i2c_info->enable_dma)) + { + /* sequential transfer now is not support dma */ + if ((msg->flags & RT_I2C_NO_START) || (msg->flags & RT_I2C_NO_STOP) || + (msg->flags & RT_I2C_NO_READ_ACK) || (msg->flags & RT_I2C_NO_READ_ACK) ) { + i2c_stat = status_invalid_argument; + break; + } + i2c_info->is_read = true; + i2c_enable_irq(i2c_info->base, I2C_EVENT_TRANSACTION_COMPLETE); + dmamux_config(HPM_DMAMUX, i2c_info->dma.channel, i2c_info->dmamux, true); + i2c_stat = i2c_rx_trigger_dma(i2c_info->dma.base, i2c_info->dma.channel, i2c_info->base, + core_local_mem_to_sys_address(0, (uint32_t) dummy_buf), transfer_len); + if (i2c_stat != status_success) + { + break; + } + i2c_stat = i2c_master_start_dma_read(i2c_info->base, msg->addr, msg->len); + if (i2c_stat != status_success) + { + break; + } + rt_sem_take(i2c_info->xfer_sem, RT_WAITING_FOREVER); + } + else + { + i2c_transfer(i2c_info->base, msg->addr, dummy_buf, transfer_len, msg->flags); + } + dummy_buf += transfer_len; + remaining_size -= transfer_len; + } + if (raw_alloc_buf != RT_NULL) + { + l1c_dc_invalidate((uint32_t) aligned_buf, aligned_len); + rt_memcpy(msg->buf, aligned_buf, msg->len); + rt_free(raw_alloc_buf); + raw_alloc_buf = RT_NULL; + aligned_buf = RT_NULL; + } + } } else { - i2c_stat = i2c_master_write(i2c_info->base, msg->addr, msg->buf, msg->len); + /* maybe probe i2c device */ + if (msg->len == 0) + { + i2c_stat = i2c_master_write(i2c_info->base, msg->addr, dummy_buf, remaining_size); + } + else + { + while (remaining_size) + { + transfer_len = MIN(I2C_SOC_TRANSFER_COUNT_MAX, remaining_size); + if (i2c_info->enable_dma) + { + /* sequential transfer now is not support dma */ + if ((msg->flags & RT_I2C_NO_START) || (msg->flags & RT_I2C_NO_STOP) || + (msg->flags & RT_I2C_NO_READ_ACK) || (msg->flags & RT_I2C_NO_READ_ACK) ) { + i2c_stat = status_invalid_argument; + break; + } + i2c_info->is_read = false; + i2c_enable_irq(i2c_info->base, I2C_EVENT_TRANSACTION_COMPLETE); + dmamux_config(HPM_DMAMUX, i2c_info->dma.channel, i2c_info->dmamux, true); + i2c_stat = i2c_tx_trigger_dma(i2c_info->dma.base, i2c_info->dma.channel, i2c_info->base, + core_local_mem_to_sys_address(0, (uint32_t) dummy_buf), transfer_len); + if (i2c_stat != status_success) + { + break; + } + i2c_stat = i2c_master_start_dma_write(i2c_info->base, msg->addr, msg->len); + if (i2c_stat != status_success) + { + break; + } + rt_sem_take(i2c_info->xfer_sem, RT_WAITING_FOREVER); + } + else + { + i2c_transfer(i2c_info->base, msg->addr, dummy_buf, transfer_len, msg->flags); + } + dummy_buf += transfer_len; + remaining_size -= transfer_len; + } + if (raw_alloc_buf != RT_NULL) + { + rt_free(raw_alloc_buf); + raw_alloc_buf = RT_NULL; + aligned_buf = RT_NULL; + } + } } - if (i2c_stat != status_success) { break; @@ -121,6 +486,7 @@ int rt_hw_i2c_init(void) hpm_stat_t stat; i2c_config_t config; rt_uint32_t freq; + char sem_name[RT_NAME_MAX]; for (uint32_t i = 0; i < sizeof(hpm_i2cs) / sizeof(hpm_i2cs[0]); i++) { init_i2c_pins(hpm_i2cs[i].base); @@ -136,6 +502,25 @@ int rt_hw_i2c_init(void) } hpm_i2cs[i].bus.ops = &hpm_i2c_ops; + if (hpm_i2cs[i].enable_dma) + { + stat = dma_mgr_request_resource(&hpm_i2cs[i].dma); + if (stat != status_success) + { + return -RT_ERROR; + } + dma_mgr_install_chn_tc_callback(&hpm_i2cs[i].dma, i2c_dma_channel_tc_callback, (void *)&hpm_i2cs[i]); + dma_mgr_enable_dma_irq_with_priority(&hpm_i2cs[i].dma, 1); + intc_m_enable_irq_with_priority(hpm_i2cs[i].i2c_irq, 2); + i2c_disable_irq(hpm_i2cs[i].base, I2C_EVENT_TRANSACTION_COMPLETE); + rt_sprintf(sem_name, "%s_s", hpm_i2cs[i].bus_name); + hpm_i2cs[i].xfer_sem = rt_sem_create(sem_name, 0, RT_IPC_FLAG_PRIO); + if (hpm_i2cs[i].xfer_sem == RT_NULL) + { + ret = RT_ENOMEM; + break; + } + } ret = rt_i2c_bus_device_register(&hpm_i2cs[i].bus, hpm_i2cs[i].bus_name); if (ret != RT_EOK) { LOG_E("rt i2c device %s register failed, status=%d\n", hpm_i2cs[i].bus_name, ret); diff --git a/bsp/hpmicro/libraries/drivers/drv_i2s.c b/bsp/hpmicro/libraries/drivers/drv_i2s.c index 164c7882982..c9092766c10 100644 --- a/bsp/hpmicro/libraries/drivers/drv_i2s.c +++ b/bsp/hpmicro/libraries/drivers/drv_i2s.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 HPMicro + * Copyright (c) 2022-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -15,23 +15,36 @@ #ifdef BSP_USING_I2S #include "hpm_i2s_drv.h" #include "board.h" +#ifdef HPMSOC_HAS_HPMSDK_DMAV2 +#include "hpm_dmav2_drv.h" +#else #include "hpm_dma_drv.h" +#endif #include "hpm_dmamux_drv.h" #include "hpm_l1c_drv.h" #include "hpm_clock_drv.h" -#include "hpm_dma_manager.h" +#include "hpm_dma_mgr.h" #include "drv_i2s.h" #include "drivers/audio.h" static rt_ssize_t hpm_i2s_transmit(struct rt_audio_device* audio, const void* writeBuf, void* readBuf, rt_size_t size); +/** + * I2S state + */ +typedef enum { + hpm_i2s_state_stop, + hpm_i2s_state_read, + hpm_i2s_state_write, +} hpm_i2s_state_t; + struct hpm_i2s { struct rt_audio_device audio; struct rt_audio_configure audio_config; - hpm_dma_resource_t rx_dma_resource; - hpm_dma_resource_t tx_dma_resource; + dma_resource_t rx_dma_resource; + dma_resource_t tx_dma_resource; char *dev_name; I2S_Type *base; clock_name_t clk_name; @@ -40,6 +53,7 @@ struct hpm_i2s uint8_t tx_dma_req; rt_uint8_t* tx_buff; rt_uint8_t* rx_buff; + hpm_i2s_state_t i2s_state; }; #if defined(BSP_USING_I2S0) @@ -61,7 +75,7 @@ ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t i2s3_rx_buff[I2S_FIFO_SIZE]; static struct hpm_i2s hpm_i2s_set[] = { -#if defined(BSP_USING_I2S0) +#if defined(BSP_USING_I2S0) && defined(HPM_I2S0) { .dev_name = "i2s0", .base = HPM_I2S0, @@ -72,7 +86,7 @@ static struct hpm_i2s hpm_i2s_set[] = .rx_buff = i2s0_rx_buff, }, #endif -#if defined(BSP_USING_I2S1) +#if defined(BSP_USING_I2S1) && defined(HPM_I2S1) { .dev_name = "i2s1", .base = HPM_I2S1; @@ -83,7 +97,7 @@ static struct hpm_i2s hpm_i2s_set[] = .rx_buff = i2s1_rx_buff, }, #endif -#if defined(BSP_USING_I2S2) +#if defined(BSP_USING_I2S2) && defined(HPM_I2S2) { .dev_name = "i2s2", .base = HPM_I2S2, @@ -94,7 +108,7 @@ static struct hpm_i2s hpm_i2s_set[] = .rx_buff = i2s2_rx_buff, }, #endif -#if defined(BSP_USING_I2S3) +#if defined(BSP_USING_I2S3) && defined(HPM_I2S3) { .dev_name = "i2s3", .base = HPM_I2S3, @@ -108,22 +122,18 @@ static struct hpm_i2s hpm_i2s_set[] = }; /* I2S TX DMA callback function: trigger next transfer */ -void i2s_tx_dma_callback(DMA_Type *ptr, uint32_t channel, void *user_data, uint32_t int_stat) +void i2s_tx_dma_tc_callback(DMA_Type *ptr, uint32_t channel, void *user_data) { - if (int_stat == DMA_CHANNEL_STATUS_TC) { - struct hpm_i2s* hpm_audio = (struct hpm_i2s*) user_data; - rt_audio_tx_complete(&hpm_audio->audio); - } + struct hpm_i2s* hpm_audio = (struct hpm_i2s*) user_data; + rt_audio_tx_complete(&hpm_audio->audio); } /* I2S RX DMA callback function: write data into record->pipe and trigger next transfer */ -void i2s_rx_dma_callback(DMA_Type *ptr, uint32_t channel, void *user_data, uint32_t int_stat) +void i2s_rx_dma_tc_callback(DMA_Type *ptr, uint32_t channel, void *user_data) { - if (int_stat == DMA_CHANNEL_STATUS_TC) { - struct hpm_i2s* hpm_audio = (struct hpm_i2s*) user_data; - rt_audio_rx_done(&hpm_audio->audio, hpm_audio->rx_buff, I2S_FIFO_SIZE); - hpm_i2s_transmit(&hpm_audio->audio, NULL, hpm_audio->rx_buff, I2S_FIFO_SIZE); - } + struct hpm_i2s* hpm_audio = (struct hpm_i2s*) user_data; + rt_audio_rx_done(&hpm_audio->audio, hpm_audio->rx_buff, I2S_FIFO_SIZE); + hpm_i2s_transmit(&hpm_audio->audio, NULL, hpm_audio->rx_buff, I2S_FIFO_SIZE); } @@ -139,26 +149,25 @@ static rt_err_t hpm_i2s_init(struct rt_audio_device* audio) init_i2s_pins(hpm_audio->base); board_init_i2s_clock(hpm_audio->base); - //使用DMA传输 + /* enable dma request */ i2s_enable_rx_dma_request(hpm_audio->base); i2s_enable_tx_dma_request(hpm_audio->base); i2s_get_default_config(hpm_audio->base, &i2s_config); i2s_config.enable_mclk_out = true; - i2s_config.frame_start_at_rising_edge = true; //左对齐与右对齐方式， 对应上升沿 i2s_init(hpm_audio->base, &i2s_config); mclk_hz = clock_get_frequency(hpm_audio->clk_name); i2s_get_default_transfer_config(&transfer); - /* 初始化I2S配置, 应用使用configure ops修改属性 */ - transfer.sample_rate = 24000U; + /* init I2S parameter */ + transfer.sample_rate = 48000U; transfer.protocol = I2S_PROTOCOL_LEFT_JUSTIFIED; - transfer.channel_slot_mask = I2S_CHANNEL_SLOT_MASK(0); /* 1个通道 */ + transfer.channel_slot_mask = I2S_CHANNEL_SLOT_MASK(0); /* one channel */ transfer.audio_depth = i2s_audio_depth_16_bits; transfer.master_mode = true; hpm_audio->transfer = transfer; - //将初始参数记录到audio_config - hpm_audio->audio_config.samplerate = 24000U; + /* record i2s parameter to audio_config */ + hpm_audio->audio_config.samplerate = 48000U; hpm_audio->audio_config.samplebits = 16; hpm_audio->audio_config.channels = 1; if (status_success != i2s_config_transfer(hpm_audio->base, mclk_hz, &transfer)) @@ -167,6 +176,8 @@ static rt_err_t hpm_i2s_init(struct rt_audio_device* audio) return -RT_ERROR; } + hpm_audio->i2s_state = hpm_i2s_state_stop; + return RT_EOK; } @@ -277,9 +288,13 @@ static rt_err_t hpm_i2s_getcaps(struct rt_audio_device* audio, struct rt_audio_c return result; } -static rt_err_t hpm_i2s_configure(struct rt_audio_device* audio, struct rt_audio_caps* caps) +static bool i2s_is_enabled(I2S_Type *ptr) { + return ((ptr->CTRL & I2S_CTRL_I2S_EN_MASK) != 0); +} +static rt_err_t hpm_i2s_configure(struct rt_audio_device* audio, struct rt_audio_caps* caps) +{ rt_err_t result = RT_EOK; RT_ASSERT(audio != RT_NULL); struct hpm_i2s* hpm_audio = (struct hpm_i2s*)audio->parent.user_data; @@ -375,7 +390,7 @@ static rt_err_t hpm_i2s_configure(struct rt_audio_device* audio, struct rt_audio break; } - /* 设置 I2S transfer */ + /* configure I2S transfer */ if (hpm_audio->audio_config.channels == i2s_mono_left) { hpm_audio->transfer.channel_slot_mask = I2S_CHANNEL_SLOT_MASK(0); } else if (hpm_audio->audio_config.channels == i2s_mono_right) { @@ -389,14 +404,34 @@ static rt_err_t hpm_i2s_configure(struct rt_audio_device* audio, struct rt_audio hpm_audio->transfer.sample_rate = hpm_audio->audio_config.samplerate; - //i2s dma方式仅支持采样位宽为：16bit, 32bit + /* i2s dma only support sample bit: 16 and 32 bits */ assert(hpm_audio->audio_config.samplebits == 16 || hpm_audio->audio_config.samplebits == 32); hpm_audio->transfer.audio_depth = hpm_audio->audio_config.samplebits; + /* Stop I2S transfer if the I2S needs to be re-configured */ + bool is_enabled = i2s_is_enabled(hpm_audio->base); + if (is_enabled) + { + if (hpm_audio->i2s_state == hpm_i2s_state_read) + { + dma_abort_channel(hpm_audio->rx_dma_resource.base, hpm_audio->rx_dma_resource.channel); + } + if (hpm_audio->i2s_state == hpm_i2s_state_write) + { + dma_abort_channel(hpm_audio->tx_dma_resource.base, hpm_audio->tx_dma_resource.channel); + } + } if (status_success != i2s_config_transfer(hpm_audio->base, clock_get_frequency(hpm_audio->clk_name), &hpm_audio->transfer)) { LOG_E("%s configure transfer failed.\n", hpm_audio->dev_name); + return -RT_ERROR; + } + /* Restore I2S to previous state */ + if (is_enabled) + { + i2s_enable(hpm_audio->base); } + return result; } @@ -406,36 +441,49 @@ static rt_err_t hpm_i2s_start(struct rt_audio_device* audio, int stream) struct hpm_i2s* hpm_audio = (struct hpm_i2s*)audio->parent.user_data; - /* 申请DMA resource用于I2S transfer */ + /* request DMA resource for audio data transfer */ if (stream == AUDIO_STREAM_REPLAY) { - hpm_dma_resource_t *dma_resource = &hpm_audio->tx_dma_resource; - if (dma_manager_request_resource(dma_resource) == status_success) { + i2s_disable(hpm_audio->base); + i2s_disable_tx_dma_request(hpm_audio->base); + dma_resource_t *dma_resource = &hpm_audio->tx_dma_resource; + if (dma_mgr_request_resource(dma_resource) == status_success) { uint8_t dmamux_ch; - dma_manager_install_interrupt_callback(dma_resource, i2s_tx_dma_callback, hpm_audio); - dma_manager_enable_dma_interrupt(dma_resource, 1); + dma_mgr_install_chn_tc_callback(dma_resource, i2s_tx_dma_tc_callback, hpm_audio); + dma_mgr_enable_dma_irq_with_priority(dma_resource, 1); dmamux_ch = DMA_SOC_CHN_TO_DMAMUX_CHN(dma_resource->base, dma_resource->channel); dmamux_config(HPM_DMAMUX, dmamux_ch, hpm_audio->tx_dma_req, true); } else { LOG_E("no dma resource available for I2S TX transfer.\n"); return -RT_ERROR; } + i2s_reset_tx(hpm_audio->base); /* disable and reset tx */ + /* fill 2 dummy data, it is suitable for 1/2 channel of audio */ + if (i2s_fill_tx_dummy_data(hpm_audio->base, hpm_audio->transfer.data_line , 2) != status_success) { + return -RT_ERROR; + } rt_audio_tx_complete(audio); + i2s_enable(hpm_audio->base); + i2s_enable_tx_dma_request(hpm_audio->base); } else if (stream == AUDIO_STREAM_RECORD) { - hpm_dma_resource_t *dma_resource = &hpm_audio->rx_dma_resource; - if (dma_manager_request_resource(dma_resource) == status_success) { + i2s_disable(hpm_audio->base); + i2s_disable_rx_dma_request(hpm_audio->base); + dma_resource_t *dma_resource = &hpm_audio->rx_dma_resource; + if (dma_mgr_request_resource(dma_resource) == status_success) { uint8_t dmamux_ch; - dma_manager_install_interrupt_callback(dma_resource, i2s_rx_dma_callback, hpm_audio); - dma_manager_enable_dma_interrupt(dma_resource, 1); + dma_mgr_install_chn_tc_callback(dma_resource, i2s_rx_dma_tc_callback, hpm_audio); + dma_mgr_enable_dma_irq_with_priority(dma_resource, 1); dmamux_ch = DMA_SOC_CHN_TO_DMAMUX_CHN(dma_resource->base, dma_resource->channel); dmamux_config(HPM_DMAMUX, dmamux_ch, hpm_audio->rx_dma_req, true); } else { LOG_E("no dma resource available for I2S RX transfer.\n"); return -RT_ERROR; } - - if (RT_EOK != hpm_i2s_transmit(&hpm_audio->audio, NULL, hpm_audio->rx_buff, I2S_FIFO_SIZE)) { - return RT_ERROR; + i2s_reset_rx(hpm_audio->base); /* disable and reset rx */ + if (I2S_FIFO_SIZE != hpm_i2s_transmit(&hpm_audio->audio, NULL, hpm_audio->rx_buff, I2S_FIFO_SIZE)) { + return -RT_ERROR; } + i2s_enable(hpm_audio->base); + i2s_enable_rx_dma_request(hpm_audio->base); } else { return -RT_ERROR; } @@ -448,17 +496,23 @@ static rt_err_t hpm_i2s_stop(struct rt_audio_device* audio, int stream) RT_ASSERT(audio != RT_NULL); struct hpm_i2s* hpm_audio = (struct hpm_i2s*)audio->parent.user_data; + i2s_disable(hpm_audio->base); + if (stream == AUDIO_STREAM_REPLAY) { - hpm_dma_resource_t *dma_resource = &hpm_audio->tx_dma_resource; - dma_manager_release_resource(dma_resource); + dma_resource_t *dma_resource = &hpm_audio->tx_dma_resource; + dma_abort_channel(dma_resource->base, dma_resource->channel); + dma_mgr_release_resource(dma_resource); } else if (stream == AUDIO_STREAM_RECORD) { - hpm_dma_resource_t *dma_resource = &hpm_audio->rx_dma_resource; - dma_manager_release_resource(dma_resource); + dma_resource_t *dma_resource = &hpm_audio->rx_dma_resource; + dma_abort_channel(dma_resource->base, dma_resource->channel); + dma_mgr_release_resource(dma_resource); } else { return -RT_ERROR; } + hpm_audio->i2s_state = hpm_i2s_state_stop; + return RT_EOK; } @@ -467,12 +521,12 @@ static rt_ssize_t hpm_i2s_transmit(struct rt_audio_device* audio, const void* wr RT_ASSERT(audio != RT_NULL); struct hpm_i2s* hpm_audio = (struct hpm_i2s*)audio->parent.user_data; - //支持采样位宽16bit, 32bit + /* i2s dma only support sample bit: 16 and 32 bits */ uint8_t data_width; uint8_t data_shift_byte; if (hpm_audio->transfer.audio_depth == i2s_audio_depth_16_bits) { data_width = DMA_TRANSFER_WIDTH_HALF_WORD; - data_shift_byte = 2U ; //16位音频数据位于寄存器的高位 + data_shift_byte = 2U ; /* put 16bit data on high bit of register */ } else { data_width = DMA_TRANSFER_WIDTH_WORD; data_shift_byte = 0U; @@ -480,7 +534,7 @@ static rt_ssize_t hpm_i2s_transmit(struct rt_audio_device* audio, const void* wr if(writeBuf != RT_NULL) { - hpm_dma_resource_t *dma_resource = &hpm_audio->tx_dma_resource; + dma_resource_t *dma_resource = &hpm_audio->tx_dma_resource; dma_channel_config_t ch_config = {0}; dma_default_channel_config(dma_resource->base, &ch_config); ch_config.src_addr = core_local_mem_to_sys_address(HPM_CORE0, (uint32_t)writeBuf); @@ -498,12 +552,13 @@ static rt_ssize_t hpm_i2s_transmit(struct rt_audio_device* audio, const void* wr l1c_dc_writeback((uint32_t)writeBuf, size); } + hpm_audio->i2s_state = hpm_i2s_state_write; if (status_success != dma_setup_channel(dma_resource->base, dma_resource->channel, &ch_config, true)) { LOG_E("dma setup channel failed\n"); return -RT_ERROR; } } else if (readBuf != RT_NULL){ - hpm_dma_resource_t *dma_resource = &hpm_audio->rx_dma_resource; + dma_resource_t *dma_resource = &hpm_audio->rx_dma_resource; dma_channel_config_t ch_config = {0}; dma_default_channel_config(dma_resource->base, &ch_config); ch_config.src_addr = (uint32_t)&hpm_audio->base->RXD[hpm_audio->transfer.data_line] + data_shift_byte; @@ -516,6 +571,7 @@ static rt_ssize_t hpm_i2s_transmit(struct rt_audio_device* audio, const void* wr ch_config.src_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; ch_config.src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; + hpm_audio->i2s_state = hpm_i2s_state_read; if (status_success != dma_setup_channel(dma_resource->base, dma_resource->channel, &ch_config, true)) { LOG_E("dma setup channel failed\n"); return -RT_ERROR; diff --git a/bsp/hpmicro/libraries/drivers/drv_i2s.h b/bsp/hpmicro/libraries/drivers/drv_i2s.h index 8034b1d2f2b..7f5ef0b5569 100644 --- a/bsp/hpmicro/libraries/drivers/drv_i2s.h +++ b/bsp/hpmicro/libraries/drivers/drv_i2s.h @@ -9,7 +9,7 @@ #define I2S_FIFO_SIZE (2048) -//AUDIO CONCTRL的参数定义 +/* channel parameter of I2S intsance */ #define AUDIO_PARM_I2S_DATA_LINE 4 int rt_hw_i2s_init(void); diff --git a/bsp/hpmicro/libraries/drivers/drv_lcd.c b/bsp/hpmicro/libraries/drivers/drv_lcd.c new file mode 100644 index 00000000000..645b04e7101 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_lcd.c @@ -0,0 +1,247 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2024-02-20 HPMicro First version + */ + +#include + +#ifdef BSP_USING_RTT_LCD_DRIVER +#include "board.h" +#include "hpm_l1c_drv.h" +#include "hpm_lcdc_drv.h" +#include "hpm_pdma_drv.h" +#include "hpm_panel.h" + + +#define LCD_BITS_PER_PIXEL 16 +#define LCD_PIXEL_FORMAT RTGRAPHIC_PIXEL_FORMAT_RGB565 +#define LCD_LAYER_INDEX (0) +#define LCD_LAYER_DONE_MASK (1U << LCD_LAYER_INDEX) +struct hpm_lcd +{ + LCDC_Type *lcd_base; + rt_uint8_t lcd_irq; + struct rt_semaphore lcd_lock; + char *bus_name; + struct rt_device parent; + struct rt_device_graphic_info lcd_info; + uint32_t lcd_buffer_size; +}; + +static rt_err_t hpm_lcd_init(struct rt_device *device); +static rt_err_t hpm_lcd_control(struct rt_device *device, int cmd, void *args); +static int hpm_lcdc_init(struct hpm_lcd *lcd, struct rt_device_graphic_info *info); + +static uint8_t __attribute__((section(".framebuffer"), aligned(HPM_L1C_CACHELINE_SIZE))) lcdc_framebuffer[PANEL_SIZE_WIDTH * PANEL_SIZE_HEIGHT * LCD_BITS_PER_PIXEL / 8]; + + +#ifdef RT_USING_DEVICE_OPS +const struct rt_device_ops hpm_lcd_ops = { + .init = hpm_lcd_init, + .open = RT_NULL, + .close = RT_NULL, + .read = RT_NULL, + .write = RT_NULL, + .control = hpm_lcd_control, +}; +#endif + +static struct hpm_lcd hpm_lcds[] = +{ + { + .bus_name = "lcd0", + .lcd_buffer_size = (PANEL_SIZE_WIDTH * PANEL_SIZE_HEIGHT * LCD_BITS_PER_PIXEL / 8), + .lcd_base = HPM_LCDC, + .lcd_irq = BOARD_LCD_IRQ, + .parent.type = RT_Device_Class_Graphic, +#ifdef RT_USING_DEVICE_OPS + .parent.ops = &hpm_lcd_ops, +#else + .parent.init = hpm_lcd_init, + .parent.open = RT_NULL, + .parent.close = RT_NULL, + .parent.read = RT_NULL, + .parent.write = RT_NULL, + .parent.control = hpm_lcd_control, +#endif + }, +}; + +void isr_lcd_d0(void) +{ + lcdc_disable_interrupt(hpm_lcds[0].lcd_base, LCDC_INT_EN_VSYNC_MASK); + rt_sem_release(&hpm_lcds[0].lcd_lock); + lcdc_clear_status(hpm_lcds[0].lcd_base, LCDC_ST_VSYNC_MASK); +} +SDK_DECLARE_EXT_ISR_M(BOARD_LCD_IRQ, isr_lcd_d0) + +static rt_err_t hpm_lcd_init(struct rt_device *device) +{ + /* nothing, right now */ + (void *)device; + return RT_EOK; +} + +static rt_err_t hpm_lcd_control(struct rt_device *device, int cmd, void *args) +{ + uint32_t aligned_start, aligned_end, aligned_size; + struct hpm_lcd *lcd = (struct hpm_lcd *)device->user_data; + hpm_panel_t *panel = hpm_panel_find_device_default(); + struct rt_device_graphic_info *info = RT_NULL; + uint32_t buffer; + + switch (cmd) + { + case RTGRAPHIC_CTRL_SET_MODE: + info = (struct rt_device_graphic_info *)args; + rt_sem_trytake(&lcd->lcd_lock); + lcdc_disable_interrupt(lcd->lcd_base, LCDC_INT_EN_VSYNC_MASK); + rt_thread_delay(10); + hpm_lcdc_init(lcd, info); + break; + + case RTGRAPHIC_CTRL_RECT_UPDATE: + if (args != RT_NULL) + { + buffer = (uint32_t)args; + } + else + { + buffer = (uint32_t)lcd->lcd_info.framebuffer; + } + if (l1c_dc_is_enabled()) + { + aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN(buffer); + aligned_end = HPM_L1C_CACHELINE_ALIGN_UP(buffer + lcd->lcd_buffer_size); + aligned_size = aligned_end - aligned_start; + l1c_dc_writeback(aligned_start, aligned_size); + } + if (lcdc_layer_control_shadow_loaded(lcd->lcd_base, 0)) + { + lcdc_layer_set_next_buffer(lcd->lcd_base, 0, (rt_uint32_t)buffer); + } + break; + + case RTGRAPHIC_CTRL_WAIT_VSYNC: + rt_sem_trytake(&lcd->lcd_lock); + lcdc_enable_interrupt(lcd->lcd_base, LCDC_INT_EN_VSYNC_MASK); + rt_sem_take(&lcd->lcd_lock, RT_WAITING_FOREVER); + break; + + case RTGRAPHIC_CTRL_POWERON: + hpm_panel_set_backlight(panel, true); + break; + + case RTGRAPHIC_CTRL_POWEROFF: + hpm_panel_set_backlight(panel, false); + break; + + case RTGRAPHIC_CTRL_GET_INFO: + info = (struct rt_device_graphic_info *)args; + + RT_ASSERT(info != RT_NULL); + info->pixel_format = lcd->lcd_info.pixel_format; + info->bits_per_pixel = 16; + info->width = lcd->lcd_info.width; + info->height = lcd->lcd_info.height; + info->framebuffer = lcd->lcd_info.framebuffer; + break; + + default: + break; + } +} + +static int hpm_lcdc_init(struct hpm_lcd *lcd, struct rt_device_graphic_info *info) +{ + lcdc_config_t config = {0}; + display_pixel_format_t pixel_format; + lcdc_get_default_config(lcd->lcd_base, &config); + board_panel_para_to_lcdc(&config); + + if (info->framebuffer == RT_NULL) + { + return -RT_ERROR; + } + rt_memcpy(&lcd->lcd_info, info, sizeof(struct rt_device_graphic_info)); + lcd->lcd_info.framebuffer = lcdc_framebuffer; + if (info->pixel_format == RTGRAPHIC_PIXEL_FORMAT_RGB565) + { + pixel_format = display_pixel_format_rgb565; + } + else if (info->pixel_format == RTGRAPHIC_PIXEL_FORMAT_ARGB888) + { + pixel_format = display_pixel_format_rgb565; + } + else { + return -RT_ERROR; + } + lcdc_init(lcd->lcd_base, &config); + memset(lcd->lcd_info.framebuffer, 0, info->width * info->height * info->bits_per_pixel / 8); + lcdc_layer_config_t layer; + lcdc_get_default_layer_config(lcd->lcd_base, &layer, pixel_format, LCD_LAYER_INDEX); + + layer.position_x = 0; + layer.position_y = 0; + layer.width = info->width; + layer.height = info->height; + layer.buffer = (rt_uint32_t)lcd->lcd_info.framebuffer; + layer.background.u = 0; + + if (status_success != lcdc_config_layer(lcd->lcd_base, LCD_LAYER_INDEX, &layer, true)) { + return -RT_ERROR; + } + + lcdc_turn_on_display(lcd->lcd_base); + lcdc_enable_interrupt(lcd->lcd_base, LCDC_INT_EN_VSYNC_MASK); + intc_m_enable_irq_with_priority(lcd->lcd_irq, 7); + return 0; +} + +int drv_lcd_hw_init(void) +{ + rt_err_t result = RT_EOK; + struct rt_device_graphic_info lcd_info; + for (uint32_t i = 0; i < sizeof(hpm_lcds) / sizeof(hpm_lcds[0]); i++) + { + struct hpm_lcd *lcd = &hpm_lcds[i]; + struct rt_device *device = &lcd->parent; + lcd->parent.user_data = lcd; + /* init lcd_lock semaphore */ + result = rt_sem_init(&hpm_lcds[0].lcd_lock, "lcd_lock", 0, RT_IPC_FLAG_FIFO); + if (result != RT_EOK) + { + result = -RT_ENOMEM; + goto __exit; + } + /* config LCD dev info */ + + lcd_info.height = PANEL_SIZE_HEIGHT; + lcd_info.width = PANEL_SIZE_WIDTH; + lcd_info.bits_per_pixel = LCD_BITS_PER_PIXEL; + lcd_info.pixel_format = LCD_PIXEL_FORMAT; + lcd_info.framebuffer = lcdc_framebuffer; + /* register lcd device */ + rt_device_register(device, hpm_lcds[i].bus_name, RT_DEVICE_FLAG_RDWR); + board_init_lcd(); + if (hpm_lcdc_init(&hpm_lcds[i], &lcd_info) != RT_EOK) + { + result = -RT_ERROR; + goto __exit; + } +__exit: + if (result != RT_EOK) + { + rt_sem_delete(&hpm_lcds[i].lcd_lock); + } + return result; + } +} +INIT_BOARD_EXPORT(drv_lcd_hw_init); + +#endif /* BSP_USING_RTT_LCD_DRIVER */ diff --git a/bsp/hpmicro/libraries/drivers/drv_mcan.c b/bsp/hpmicro/libraries/drivers/drv_mcan.c index c9dd7057576..01d5a626865 100644 --- a/bsp/hpmicro/libraries/drivers/drv_mcan.c +++ b/bsp/hpmicro/libraries/drivers/drv_mcan.c @@ -1,11 +1,12 @@ /* - * Copyright (c) 2021 - 2023 HPMicro + * Copyright (c) 2023-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * * Change Logs: * Date Author Notes * 2023-04-07 HPMicro the first version + * 2023-05-31 HPMicro add MCAN4-MCAN7 support */ #include @@ -15,6 +16,7 @@ #include "hpm_mcan_drv.h" + #define CAN_SEND_WAIT_MS_MAX (1000U) /* CAN maximum wait time for transmission */ #define CAN_SENDBOX_NUM (1U) /* CAN Hardware Transmission buffer number */ #define CAN_STD_FILTER_NUM_MAX (128U) /* std Filter number */ @@ -128,7 +130,7 @@ static hpm_can_t dev_can0 = { .can_base = HPM_MCAN0, .name = "can0", - .irq_num = IRQn_CAN0, + .irq_num = IRQn_MCAN0, .fifo_index = 0, }; @@ -136,7 +138,7 @@ void can0_isr(void) { hpm_mcan_isr(&dev_can0); } -SDK_DECLARE_EXT_ISR_M(IRQn_CAN0, can0_isr); +SDK_DECLARE_EXT_ISR_M(IRQn_MCAN0, can0_isr); #endif @@ -145,14 +147,14 @@ static hpm_can_t dev_can1 = { .can_base = HPM_MCAN1, .name = "can1", - .irq_num = IRQn_CAN1, + .irq_num = IRQn_MCAN1, .fifo_index = 1, }; void can1_isr(void) { hpm_mcan_isr(&dev_can1); } -SDK_DECLARE_EXT_ISR_M(IRQn_CAN1, can1_isr); +SDK_DECLARE_EXT_ISR_M(IRQn_MCAN1, can1_isr); #endif #if defined(HPM_MCAN2_BASE) && defined(BSP_USING_MCAN2) @@ -160,14 +162,14 @@ static hpm_can_t dev_can2 = { .can_base = HPM_MCAN2, .name = "can2", - .irq_num = IRQn_CAN2, + .irq_num = IRQn_MCAN2, .fifo_index = 2, }; void can2_isr(void) { hpm_mcan_isr(&dev_can2); } -SDK_DECLARE_EXT_ISR_M(IRQn_CAN2, can2_isr); +SDK_DECLARE_EXT_ISR_M(IRQn_MCAN2, can2_isr); #endif #if defined(HPM_MCAN3_BASE) && defined(BSP_USING_MCAN3) @@ -175,14 +177,74 @@ static hpm_can_t dev_can3 = { .can_base = HPM_MCAN3, .name = "can3", - .irq_num = IRQn_CAN3, + .irq_num = IRQn_MCAN3, .fifo_index = 3, }; void can3_isr(void) { hpm_mcan_isr(&dev_can3); } -SDK_DECLARE_EXT_ISR_M(IRQn_CAN3, can3_isr); +SDK_DECLARE_EXT_ISR_M(IRQn_MCAN3, can3_isr); +#endif + +#if defined(HPM_MCAN4_BASE) && defined(BSP_USING_MCAN4) +static hpm_can_t dev_can4 = +{ + .can_base = HPM_MCAN4, + .name = "can4", + .irq_num = IRQn_MCAN4, + .fifo_index = 4, +}; +void can4_isr(void) +{ + hpm_mcan_isr(&dev_can4); +} +SDK_DECLARE_EXT_ISR_M(IRQn_MCAN4, can4_isr); +#endif + +#if defined(HPM_MCAN5_BASE) && defined(BSP_USING_MCAN5) +static hpm_can_t dev_can5 = +{ + .can_base = HPM_MCAN5, + .name = "can5", + .irq_num = IRQn_MCAN5, + .fifo_index = 5, +}; +void can5_isr(void) +{ + hpm_mcan_isr(&dev_can5); +} +SDK_DECLARE_EXT_ISR_M(IRQn_MCAN5, can5_isr); +#endif + +#if defined(HPM_MCAN6_BASE) && defined(BSP_USING_MCAN6) +static hpm_can_t dev_can6 = +{ + .can_base = HPM_MCAN6, + .name = "can6", + .irq_num = IRQn_MCAN6, + .fifo_index = 6, +}; +void can6_isr(void) +{ + hpm_mcan_isr(&dev_can6); +} +SDK_DECLARE_EXT_ISR_M(IRQn_MCAN6, can6_isr); +#endif + +#if defined(HPM_MCAN7_BASE) && defined(BSP_USING_MCAN7) +static hpm_can_t dev_can7 = +{ + .can_base = HPM_MCAN7, + .name = "can7", + .irq_num = IRQn_MCAN7, + .fifo_index = 7, +}; +void can7_isr(void) +{ + hpm_mcan_isr(&dev_can7); +} +SDK_DECLARE_EXT_ISR_M(IRQn_MCAN7, can7_isr); #endif static hpm_can_t *hpm_cans[] = { @@ -197,6 +259,18 @@ static hpm_can_t *hpm_cans[] = { #endif #if defined(HPM_MCAN3_BASE) && defined(BSP_USING_MCAN3) &dev_can3, +#endif +#if defined(HPM_MCAN4_BASE) && defined(BSP_USING_MCAN4) + &dev_can4, +#endif +#if defined(HPM_MCAN5_BASE) && defined(BSP_USING_MCAN5) + &dev_can5, +#endif +#if defined(HPM_MCAN6_BASE) && defined(BSP_USING_MCAN6) + &dev_can6, +#endif +#if defined(HPM_MCAN7_BASE) && defined(BSP_USING_MCAN7) + &dev_can7, #endif }; @@ -339,6 +413,7 @@ static rt_err_t hpm_mcan_configure(struct rt_can_device *can, struct can_configu drv_can->can_config.all_filters_config.ext_id_filter_list.filter_elem_list = &drv_can->ext_can_filters[0]; drv_can->can_config.all_filters_config.ext_id_filter_list.mcan_filter_elem_count = drv_can->ext_filter_num; drv_can->can_config.all_filters_config.ext_id_mask = (1UL << 30) - 1UL; + drv_can->can_config.txbuf_trans_interrupt_mask = ~0UL; hpm_stat_t status = mcan_init(drv_can->can_base, &drv_can->can_config, can_clk); if (status != status_success) @@ -360,6 +435,7 @@ static rt_err_t hpm_mcan_control(struct rt_can_device *can, int cmd, void *arg) rt_err_t err = RT_EOK; uint32_t temp; + uint32_t irq_txrx_mask; switch (cmd) { @@ -368,19 +444,22 @@ static rt_err_t hpm_mcan_control(struct rt_can_device *can, int cmd, void *arg) intc_m_disable_irq(drv_can->irq_num); if (arg_val == RT_DEVICE_FLAG_INT_RX) { - uint32_t irq_txrx_mask = MCAN_EVENT_RECEIVE; + irq_txrx_mask = MCAN_EVENT_RECEIVE; drv_can->irq_txrx_err_enable_mask &= ~irq_txrx_mask; + drv_can->can_config.interrupt_mask &= ~irq_txrx_mask; mcan_disable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask); } else if (arg_val == RT_DEVICE_FLAG_INT_TX) { - uint32_t irq_txrx_mask = MCAN_EVENT_TRANSMIT; + irq_txrx_mask = MCAN_EVENT_TRANSMIT; drv_can->irq_txrx_err_enable_mask &= ~irq_txrx_mask; + drv_can->can_config.interrupt_mask &= ~irq_txrx_mask; mcan_disable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask); mcan_disable_txbuf_interrupt(drv_can->can_base, ~0UL); } else if (arg_val == RT_DEVICE_CAN_INT_ERR) { - uint32_t irq_txrx_mask = MCAN_EVENT_ERROR; + irq_txrx_mask = MCAN_EVENT_ERROR; drv_can->irq_txrx_err_enable_mask &= ~irq_txrx_mask; + drv_can->can_config.interrupt_mask &= ~irq_txrx_mask; mcan_disable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask); } else { err = -RT_ERROR; @@ -390,23 +469,26 @@ static rt_err_t hpm_mcan_control(struct rt_can_device *can, int cmd, void *arg) arg_val = (uint32_t) arg; if (arg_val == RT_DEVICE_FLAG_INT_RX) { - uint32_t irq_txrx_mask = MCAN_EVENT_RECEIVE; + irq_txrx_mask = MCAN_EVENT_RECEIVE; drv_can->irq_txrx_err_enable_mask |= irq_txrx_mask; + drv_can->can_config.interrupt_mask |= irq_txrx_mask; mcan_enable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask); intc_m_enable_irq_with_priority(drv_can->irq_num, 1); } else if (arg_val == RT_DEVICE_FLAG_INT_TX) { - uint32_t irq_txrx_mask = MCAN_EVENT_TRANSMIT; + irq_txrx_mask = MCAN_EVENT_TRANSMIT; drv_can->irq_txrx_err_enable_mask |= irq_txrx_mask; + drv_can->can_config.interrupt_mask |= irq_txrx_mask; mcan_enable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask); mcan_enable_txbuf_interrupt(drv_can->can_base, ~0UL); intc_m_enable_irq_with_priority(drv_can->irq_num, 1); } else if (arg_val == RT_DEVICE_CAN_INT_ERR) { - uint32_t irq_txrx_mask = MCAN_EVENT_ERROR; + irq_txrx_mask = MCAN_EVENT_ERROR; drv_can->irq_txrx_err_enable_mask |= irq_txrx_mask; + drv_can->can_config.interrupt_mask |= irq_txrx_mask; mcan_enable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask); intc_m_enable_irq_with_priority(drv_can->irq_num, 1); } @@ -491,6 +573,12 @@ static rt_err_t hpm_mcan_control(struct rt_can_device *can, int cmd, void *arg) drv_can->can_config.all_filters_config.ext_id_filter_list.mcan_filter_elem_count = 1; } err = hpm_mcan_configure(can, &drv_can->can_dev.config); +#ifdef RT_CAN_USING_HDR + if (filter == RT_NULL) { + /*if use RT_CAN_USING_HDR, but if want to receive everything without filtering, use default filter, need to return NO-RT-OK status*/ + err = -RT_ETRAP; + } +#endif } break; case RT_CAN_CMD_SET_MODE: @@ -587,6 +675,7 @@ static rt_err_t hpm_mcan_control(struct rt_can_device *can, int cmd, void *arg) rt_memcpy(arg, &drv_can->can_dev.status, sizeof(drv_can->can_dev.status)); break; } + return err; } static int hpm_mcan_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno) @@ -620,10 +709,10 @@ static int hpm_mcan_sendmsg(struct rt_can_device *can, const void *buf, rt_uint3 } #ifdef RT_CAN_USING_CANFD + tx_frame.bitrate_switch = can_msg->brs; if (can_msg->fd_frame != 0) { tx_frame.canfd_frame = 1; - tx_frame.bitrate_switch = 1; RT_ASSERT(can_msg->len <= 15); } else @@ -688,13 +777,20 @@ static int hpm_mcan_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t bo else { can_msg->rtr = RT_CAN_DTR; } - +#ifdef RT_CAN_USING_CANFD + can_msg->fd_frame = rx_buf.canfd_frame; + can_msg->brs = rx_buf.bitrate_switch; +#endif can_msg->len = rx_buf.dlc; uint32_t msg_len = mcan_get_message_size_from_dlc(can_msg->len); for(uint32_t i = 0; i < msg_len; i++) { can_msg->data[i] = rx_buf.data_8[i]; } - +#ifdef RT_CAN_USING_HDR + /* Hardware filter messages are valid */ + can_msg->hdr_index = boxno; + can->hdr[can_msg->hdr_index].connected = 1; +#endif } else { @@ -710,7 +806,9 @@ int rt_hw_mcan_init(void) config.privmode = RT_CAN_MODE_NOPRIV; config.sndboxnumber = CAN_SENDBOX_NUM; config.ticks = 50; - +#ifdef RT_CAN_USING_HDR + config.maxhdr = 32; +#endif for (uint32_t i = 0; i < ARRAY_SIZE(hpm_cans); i++) { hpm_cans[i]->can_dev.config = config; diff --git a/bsp/hpmicro/libraries/drivers/drv_pdm.c b/bsp/hpmicro/libraries/drivers/drv_pdm.c index 172191bce46..1648b1ecb4e 100644 --- a/bsp/hpmicro/libraries/drivers/drv_pdm.c +++ b/bsp/hpmicro/libraries/drivers/drv_pdm.c @@ -18,10 +18,14 @@ #include "hpm_i2s_drv.h" #include "hpm_pdm_drv.h" #include "drv_pdm.h" +#ifdef HPMSOC_HAS_HPMSDK_DMAV2 +#include "hpm_dmav2_drv.h" +#else #include "hpm_dma_drv.h" +#endif #include "hpm_dmamux_drv.h" #include "hpm_l1c_drv.h" -#include "hpm_dma_manager.h" +#include "hpm_dma_mgr.h" /* PDM connect to I2S0 RX */ @@ -36,16 +40,14 @@ struct hpm_pdm }; struct hpm_pdm hpm_pdm_dev = { 0 }; -static hpm_dma_resource_t dma_resource = { 0 }; +static dma_resource_t dma_resource = { 0 }; static rt_err_t hpm_pdm_dma_transmit(); -void pdm_dma_callback(DMA_Type *ptr, uint32_t channel, void *user_data, uint32_t int_stat) +void pdm_dma_tc_callback(DMA_Type *ptr, uint32_t channel, void *user_data) { - if (int_stat == DMA_CHANNEL_STATUS_TC) { - rt_audio_rx_done(&hpm_pdm_dev.audio, hpm_pdm_dev.rx_fifo, PDM_FIFO_SIZE); - hpm_pdm_dma_transmit(); - } + rt_audio_rx_done(&hpm_pdm_dev.audio, hpm_pdm_dev.rx_fifo, PDM_FIFO_SIZE); + hpm_pdm_dma_transmit(); } static rt_err_t hpm_pdm_getcaps(struct rt_audio_device* audio, struct rt_audio_caps* caps) @@ -95,6 +97,11 @@ static rt_err_t hpm_pdm_getcaps(struct rt_audio_device* audio, struct rt_audio_c return result; } +static bool i2s_is_enabled(I2S_Type *ptr) +{ + return ((ptr->CTRL & I2S_CTRL_I2S_EN_MASK) != 0); +} + static rt_err_t hpm_pdm_set_channels(uint32_t channel) { uint32_t mclk_hz; @@ -102,21 +109,29 @@ static rt_err_t hpm_pdm_set_channels(uint32_t channel) mclk_hz = clock_get_frequency(clock_i2s0); i2s_get_default_transfer_config_for_pdm(&transfer); - transfer.data_line = I2S_DATA_LINE_0; + transfer.data_line = PDM_I2S_DATA_LINE; if (channel == 1) { - transfer.channel_slot_mask = I2S_CHANNEL_SLOT_MASK(0); + transfer.channel_slot_mask = BOARD_PDM_SINGLE_CHANNEL_MASK; } else if(channel == 2) { - transfer.channel_slot_mask = I2S_CHANNEL_SLOT_MASK(0) | I2S_CHANNEL_SLOT_MASK(1); + transfer.channel_slot_mask = BOARD_PDM_DUAL_CHANNEL_MASK; } else { LOG_E("PDM not support channels number %d.\n", channel); return -RT_ERROR; } + bool is_enabled = i2s_is_enabled(PDM_I2S); + if (is_enabled) { + dma_abort_channel(dma_resource.base, dma_resource.channel); + } if (status_success != i2s_config_rx(PDM_I2S, mclk_hz, &transfer)) { - LOG_E("dao_i2s configure transfer failed\n"); + LOG_E("pdm_i2s configure transfer failed\n"); return -RT_ERROR; } + if (is_enabled) + { + i2s_enable(PDM_I2S); + } return RT_EOK; } @@ -172,8 +187,8 @@ static rt_err_t hpm_pdm_init(struct rt_audio_device* audio) i2s_init(PDM_I2S, &i2s_config); i2s_get_default_transfer_config_for_pdm(&transfer); - transfer.data_line = I2S_DATA_LINE_0; - transfer.channel_slot_mask = I2S_CHANNEL_SLOT_MASK(0); + transfer.data_line = PDM_I2S_DATA_LINE; + transfer.channel_slot_mask = BOARD_PDM_SINGLE_CHANNEL_MASK; if (status_success != i2s_config_rx(PDM_I2S, clock_get_frequency(clock_i2s0), &transfer)) { LOG_E("pdm_i2s configure receive failed\n"); @@ -182,7 +197,7 @@ static rt_err_t hpm_pdm_init(struct rt_audio_device* audio) /* init audio configure */ hpm_pdm_dev.record_config.channels = 1U; - hpm_pdm_dev.record_config.samplebits = 32U; /* 数据为32位，实际有效位24bit，高位为0 */ + hpm_pdm_dev.record_config.samplebits = 32U; /* the actual significant bit is 24 bits, and the low bit is 0 */ hpm_pdm_dev.record_config.samplerate = PDM_SOC_SAMPLE_RATE_IN_HZ; /* fix 16KHz */ pdm_get_default_config(HPM_PDM, &pdm_config); @@ -201,12 +216,15 @@ static rt_err_t hpm_pdm_start(struct rt_audio_device* audio, int stream) if (stream == AUDIO_STREAM_RECORD) { - pdm_start(HPM_PDM); + i2s_disable(PDM_I2S); + i2s_disable_rx_dma_request(PDM_I2S); + pdm_stop(HPM_PDM); + pdm_software_reset(HPM_PDM); - if (dma_manager_request_resource(&dma_resource) == status_success) { + if (dma_mgr_request_resource(&dma_resource) == status_success) { uint8_t dmamux_ch; - dma_manager_install_interrupt_callback(&dma_resource, pdm_dma_callback, NULL); - dma_manager_enable_dma_interrupt(&dma_resource, 1); + dma_mgr_install_chn_tc_callback(&dma_resource, pdm_dma_tc_callback, NULL); + dma_mgr_enable_dma_irq_with_priority(&dma_resource, 1); dmamux_ch = DMA_SOC_CHN_TO_DMAMUX_CHN(dma_resource.base, dma_resource.channel); dmamux_config(HPM_DMAMUX, dmamux_ch, PDM_DMA_REQ, true); } else { @@ -214,9 +232,14 @@ static rt_err_t hpm_pdm_start(struct rt_audio_device* audio, int stream) return -RT_ERROR; } + i2s_reset_rx(PDM_I2S); if (RT_EOK != hpm_pdm_dma_transmit()) { - return RT_ERROR; + return -RT_ERROR; } + + pdm_start(HPM_PDM); + i2s_enable_rx_dma_request(PDM_I2S); + i2s_start(PDM_I2S); } return RT_EOK; @@ -226,12 +249,13 @@ static rt_err_t hpm_pdm_stop(struct rt_audio_device* audio, int stream) { RT_ASSERT(audio != RT_NULL); - if (stream == AUDIO_STREAM_RECORD) - { + if (stream == AUDIO_STREAM_RECORD) { pdm_stop(HPM_PDM); - } + i2s_stop(PDM_I2S); - dma_manager_release_resource(&dma_resource); + dma_abort_channel(dma_resource.base, dma_resource.channel); + dma_mgr_release_resource(&dma_resource); + } return RT_EOK; } @@ -252,7 +276,7 @@ static rt_err_t hpm_pdm_dma_transmit() if (status_success != dma_setup_channel(dma_resource.base, dma_resource.channel, &ch_config, true)) { LOG_E("dma setup channel failed\n"); - return RT_ERROR; + return -RT_ERROR; } if (l1c_dc_is_enabled()) { diff --git a/bsp/hpmicro/libraries/drivers/drv_pwm.c b/bsp/hpmicro/libraries/drivers/drv_pwm.c index f8122f68ae2..c98c22dca72 100644 --- a/bsp/hpmicro/libraries/drivers/drv_pwm.c +++ b/bsp/hpmicro/libraries/drivers/drv_pwm.c @@ -43,31 +43,19 @@ static PWM_Type * pwm_base_tbl[PWM_INSTANCE_NUM] = { HPM_PWM3 #endif }; -static const clock_name_t pwm_clock_tbl[4] = {clock_mot0, -#if (PWM_INSTANCE_NUM > 1) -clock_mot1, -#endif -#if (PWM_INSTANCE_NUM > 2) -clock_mot2, -#endif -#if (PWM_INSTANCE_NUM > 3) -clock_mot3 -#endif -}; rt_err_t hpm_generate_central_aligned_waveform(uint8_t pwm_index, uint8_t channel, uint32_t period, uint32_t pulse) { uint32_t duty; - pwm_cmp_config_t cmp_config[4] = {0}; + pwm_cmp_config_t cmp_config[2] = {0}; pwm_config_t pwm_config = {0}; uint32_t reload = 0; uint32_t freq; PWM_Type * pwm_name_index; - clock_name_t pwm_clock; - pwm_clock = pwm_clock_tbl[pwm_index]; pwm_name_index = pwm_base_tbl[pwm_index]; - freq = clock_get_frequency(pwm_clock); + init_pwm_pins(pwm_name_index); + freq = board_init_pwm_clock(pwm_name_index); if(period != 0) { reload = (uint64_t)freq * period / 1000000000; } else { @@ -84,53 +72,45 @@ rt_err_t hpm_generate_central_aligned_waveform(uint8_t pwm_index, uint8_t channe pwm_set_start_count(pwm_name_index, 0, 0); /* - * config cmp1 and cmp2 and cmp3 + * config cmp1 and cmp2 */ + duty = (uint64_t)freq * pulse / 1000000000; + cmp_config[0].mode = pwm_cmp_mode_output_compare; - cmp_config[0].cmp = reload + 1; - cmp_config[0].update_trigger = pwm_shadow_register_update_on_hw_event; + cmp_config[0].cmp = (reload - duty) >> 1; + cmp_config[0].update_trigger = pwm_shadow_register_update_on_shlk; cmp_config[1].mode = pwm_cmp_mode_output_compare; - cmp_config[1].cmp = reload + 1; - cmp_config[1].update_trigger = pwm_shadow_register_update_on_hw_event; + cmp_config[1].cmp = (reload + duty) >> 1; + cmp_config[1].update_trigger = pwm_shadow_register_update_on_shlk; - cmp_config[3].mode = pwm_cmp_mode_output_compare; - cmp_config[3].cmp = reload; - cmp_config[3].update_trigger = pwm_shadow_register_update_on_modify; pwm_config.enable_output = true; pwm_config.dead_zone_in_half_cycle = 0; - pwm_config.invert_output = true; + pwm_config.invert_output = false; /* * config pwm */ if (status_success != pwm_setup_waveform(pwm_name_index, channel, &pwm_config, channel * 2, cmp_config, 2)) { - return RT_FALSE; + return -RT_ERROR; } - pwm_load_cmp_shadow_on_match(pwm_name_index, 17, &cmp_config[3]); pwm_start_counter(pwm_name_index); pwm_issue_shadow_register_lock_event(pwm_name_index); - duty = (uint64_t)freq * pulse / 1000000000; - - pwm_update_raw_cmp_central_aligned(pwm_name_index, channel * 2, channel * 2 + 1, (reload - duty) >> 1, (reload + duty) >> 1); - return RT_TRUE; + return RT_EOK; } rt_err_t hpm_set_central_aligned_waveform(uint8_t pwm_index, uint8_t channel, uint32_t period, uint32_t pulse) { uint32_t duty; - pwm_cmp_config_t cmp_config[4] = {0}; pwm_config_t pwm_config = {0}; uint32_t reload = 0; uint32_t freq; PWM_Type * pwm_name_index; - clock_name_t pwm_clock; - pwm_clock = pwm_clock_tbl[pwm_index]; pwm_name_index = pwm_base_tbl[pwm_index]; - freq = clock_get_frequency(pwm_clock); + freq = board_init_pwm_clock(pwm_name_index); if(period != 0) { reload = (uint64_t)freq * period / 1000000000; } else { @@ -139,22 +119,18 @@ rt_err_t hpm_set_central_aligned_waveform(uint8_t pwm_index, uint8_t channel, ui pwm_get_default_pwm_config(pwm_name_index, &pwm_config); pwm_set_reload(pwm_name_index, 0, reload); - cmp_config[3].mode = pwm_cmp_mode_output_compare; - cmp_config[3].cmp = reload; - cmp_config[3].update_trigger = pwm_shadow_register_update_on_modify; - pwm_config_cmp(pwm_name_index, 17, &cmp_config[3]); - pwm_issue_shadow_register_lock_event(pwm_name_index); duty = (uint64_t)freq * pulse / 1000000000; pwm_update_raw_cmp_central_aligned(pwm_name_index, channel * 2, channel * 2 + 1, (reload - duty) >> 1, (reload + duty) >> 1); + pwm_issue_shadow_register_lock_event(pwm_name_index); - return RT_TRUE; + return RT_EOK; } rt_err_t hpm_disable_pwm(uint8_t pwm_index, uint8_t channel) { pwm_disable_output(pwm_base_tbl[pwm_index], channel); - return RT_TRUE; + return RT_EOK; } @@ -163,7 +139,7 @@ rt_err_t hpm_pwm_control(struct rt_device_pwm * device, int cmd, void *arg) uint8_t channel; uint32_t period; uint32_t pulse; - rt_err_t sta = RT_TRUE; + rt_err_t sta = RT_EOK; unsigned char pwm_name; struct rt_pwm_configuration * configuration; configuration = (struct rt_pwm_configuration * )arg; @@ -179,7 +155,7 @@ rt_err_t hpm_pwm_control(struct rt_device_pwm * device, int cmd, void *arg) } else if (strcmp("pwm3", device->parent.parent.name) == 0) { pwm_name = 3; } else { - return RT_FALSE; + return -RT_ERROR; } switch(cmd) { @@ -196,11 +172,11 @@ rt_err_t hpm_pwm_control(struct rt_device_pwm * device, int cmd, void *arg) break; } case PWM_CMD_GET: { - sta = RT_TRUE; + sta = RT_EOK; break; } default: { - sta = RT_FALSE; + sta = -RT_ERROR; break; } } @@ -212,7 +188,7 @@ rt_err_t hpm_pwm_dev_control(rt_device_t device, int cmd, void *arg) uint8_t channel; uint32_t period; uint32_t pulse; - rt_err_t sta = RT_TRUE; + rt_err_t sta = RT_EOK; uint8_t pwm_name; struct rt_pwm_configuration * configuration; configuration = (struct rt_pwm_configuration * )arg; @@ -228,7 +204,7 @@ rt_err_t hpm_pwm_dev_control(rt_device_t device, int cmd, void *arg) } else if (strcmp("pwm3", device->parent.name) == 0) { pwm_name = 3; } else { - return RT_FALSE; + return -RT_ERROR; } switch(cmd) { @@ -245,11 +221,11 @@ rt_err_t hpm_pwm_dev_control(rt_device_t device, int cmd, void *arg) break; } case PWM_CMD_GET: { - sta = RT_TRUE; + sta = RT_EOK; break; } default: { - sta = RT_FALSE; + sta = -RT_ERROR; break; } } diff --git a/bsp/hpmicro/libraries/drivers/drv_rtc.c b/bsp/hpmicro/libraries/drivers/drv_rtc.c index 3c75ff9ecc7..1968629326b 100644 --- a/bsp/hpmicro/libraries/drivers/drv_rtc.c +++ b/bsp/hpmicro/libraries/drivers/drv_rtc.c @@ -11,6 +11,7 @@ #include "board.h" #include "drv_rtc.h" #include "hpm_rtc_drv.h" +#include "hpm_bpor_drv.h" #include #include @@ -69,6 +70,8 @@ static struct rt_device hpm_rtc= { ******************************************************************************************/ static rt_err_t hpm_rtc_init(rt_device_t dev) { + /* Enable Power retention mode for the battery domain */ + bpor_enable_reg_value_retention(HPM_BPOR); return RT_EOK; } static rt_err_t hpm_rtc_open(rt_device_t dev, rt_uint16_t oflag) diff --git a/bsp/hpmicro/libraries/drivers/drv_sdio.c b/bsp/hpmicro/libraries/drivers/drv_sdio.c index ff892f1807b..c7946a0d00e 100644 --- a/bsp/hpmicro/libraries/drivers/drv_sdio.c +++ b/bsp/hpmicro/libraries/drivers/drv_sdio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023 HPMicro + * Copyright (c) 2022-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -8,7 +8,11 @@ * 2022-02-23 HPMicro First version * 2022-07-19 HPMicro Fixed the multi-block read/write issue * 2023-07-27 HPMicro Fixed clock setting issue - * 2023-08-02 HPMicro Add speed mode setting + * 2023-08-02 HPMicro Added speed mode setting + * 2024-01-03 HPMicro Added multiple instance support + * 2024-05-23 HPMicro Fixed unaligned transfer issue in the SDIO case + * 2024-05-25 HPMicro Added HS200 & HS400 support, optimize the cache-management policy for read + * 2024-05-26 HPMicro Added UHS-I support, added DDR50 and High Speed DDR mode support */ #include @@ -31,30 +35,177 @@ #define SDXC_CACHELINE_ALIGN_UP(x) HPM_L1C_CACHELINE_ALIGN_UP(x) #define SDXC_IS_CACHELINE_ALIGNED(n) ((uint32_t)(n) % (uint32_t)(CACHE_LINESIZE) == 0U) +/** + * Note: Allocate cache-line aligned buffer in the SD/eMMC read/write case may require larger heap size + * if the read/write length is a big number (for example: 64KB), the RT-Thread RTOS may + * be unable to allocate enough size of buffer if the heap size is small. + * + * Keep this option disabled by default, please enable it if the default setting cannot meet + * real requirement of application. + */ +#define HPM_SDXC_ALLOC_CACHELINE_ALIGNED_BUF 0 + struct hpm_mmcsd { struct rt_mmcsd_host *host; struct rt_mmcsd_req *req; struct rt_mmcsd_cmd *cmd; struct rt_timer *timer; + + char name[RT_NAME_MAX]; rt_uint32_t *buf; SDXC_Type *sdxc_base; int32_t irq_num; uint32_t *sdxc_adma2_table; - + bool support_8bit; + bool support_4bit; + bool support_1v8; + bool support_3v3; uint8_t power_mode; uint8_t bus_width; uint8_t timing; uint8_t bus_mode; uint32_t freq; + uint16_t vdd; + const char *vsel_pin_name; + const char *pwr_pin_name; }; +/** + * @brief SDIO CMD53 argument + */ +typedef union +{ + uint32_t value; + struct + { + uint32_t count :9; + uint32_t reg_addr :17; + uint32_t op_code :1; + uint32_t block_mode :1; + uint32_t func_num :3; + uint32_t rw_flag :1; + }; +} sdio_cmd53_arg_t; + static void hpm_sdmmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req); static void hpm_sdmmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg); static void hpm_sdmmc_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t en); static void hpm_sdmmc_host_recovery(SDXC_Type *base); -static int hpm_sdmmc_transfer(SDXC_Type *base, sdxc_adma_config_t *dma_config, sdxc_xfer_t *xfer); +static hpm_stat_t hpm_sdmmc_transfer(SDXC_Type *base, sdxc_adma_config_t *dma_config, sdxc_xfer_t *xfer); +static rt_int32_t hpm_sdmmc_execute_tuning(struct rt_mmcsd_host *host, rt_int32_t opcode); +static rt_int32_t hpm_sdmmc_switch_uhs_voltage(struct rt_mmcsd_host *host); + +static void hpm_sdmmc_power_on_via_pin(struct hpm_mmcsd *mmcsd); +static void hpm_sdmmc_power_off_via_pin(struct hpm_mmcsd *mmcsd); + +static void hpm_sdmmc_switch_to_3v3_via_pin(struct hpm_mmcsd *mmcsd); +static void hpm_sdmmc_switch_to_1v8_via_pin(struct hpm_mmcsd *mmcsd); + + + +static void hpm_sdmmc_pin_init(const char *pin_name, bool is_output); +static void hpm_sdmmc_pin_write(const char *pin_name, rt_uint8_t value); +static void hpm_sdmmc_pin_init(const char *pin_name, bool is_output) +{ + rt_base_t pin = rt_pin_get(pin_name); + if (pin < 0) { + return; + } + + rt_uint8_t mode = (is_output) ? PIN_MODE_OUTPUT : PIN_MODE_INPUT_PULLUP; + if (is_output) + { + rt_pin_mode(pin, mode); + } +} + +static void hpm_sdmmc_pin_write(const char *pin_name, rt_uint8_t value) +{ + rt_base_t pin = rt_pin_get(pin_name); + if (pin < 0) + { + return; + } + + rt_pin_write(pin, value); +} + +static void hpm_sdmmc_power_on_via_pin(struct hpm_mmcsd *mmcsd) +{ + hpm_sdmmc_pin_write(mmcsd->pwr_pin_name, 1); +} + +static void hpm_sdmmc_power_off_via_pin(struct hpm_mmcsd *mmcsd) +{ + hpm_sdmmc_pin_write(mmcsd->pwr_pin_name, 0); +} + +static void hpm_sdmmc_switch_to_3v3_via_pin(struct hpm_mmcsd *mmcsd) +{ + hpm_sdmmc_pin_write(mmcsd->vsel_pin_name, 0); +} + +static void hpm_sdmmc_switch_to_1v8_via_pin(struct hpm_mmcsd *mmcsd) +{ + hpm_sdmmc_pin_write(mmcsd->vsel_pin_name, 1); +} + + +static rt_int32_t hpm_sdmmc_switch_uhs_voltage(struct rt_mmcsd_host *host) +{ + struct hpm_mmcsd *mmcsd = (struct hpm_mmcsd *) host->private_data; + SDXC_Type *base = mmcsd->sdxc_base; + + /* 1. Stop providing clock to the card */ + sdxc_enable_inverse_clock(mmcsd->sdxc_base, false); + sdxc_enable_sd_clock(mmcsd->sdxc_base, false); + + /* 2. Wait until DAT[3:0] are 4'b0000 */ + uint32_t data3_0_level; + uint32_t delay_cnt = 1000000UL; + do + { + data3_0_level = sdxc_get_data3_0_level(mmcsd->sdxc_base); + --delay_cnt; + } while ((data3_0_level != 0U) && (delay_cnt > 0U)); + if (delay_cnt < 1) + { + return -RT_ETIMEOUT; + } + + /* 3. Switch to 1.8V */ + hpm_sdmmc_switch_to_1v8_via_pin(mmcsd); + sdxc_select_voltage(mmcsd->sdxc_base, sdxc_bus_voltage_sd_1v8); + + /* 4. spec:host delay 5ms, host: give more delay time here */ + rt_thread_mdelay(10); + + /* 5. Provide SD clock the card again */ + sdxc_enable_inverse_clock(mmcsd->sdxc_base, true); + sdxc_enable_sd_clock(mmcsd->sdxc_base, true); + + /* 6. spec: wait 1ms, host: give more delay time here */ + rt_thread_mdelay(5); + + /* 7. Check DAT[3:0], make sure the value is 4'b0000 */ + delay_cnt = 1000000UL; + data3_0_level; + do + { + data3_0_level = sdxc_get_data3_0_level(mmcsd->sdxc_base); + --delay_cnt; + } while ((data3_0_level == 0U) && (delay_cnt > 0U)); + if (delay_cnt < 1) + { + return -RT_ETIMEOUT; + } + + return RT_EOK; +} + + static const struct rt_mmcsd_host_ops hpm_mmcsd_host_ops = @@ -62,14 +213,118 @@ static const struct rt_mmcsd_host_ops hpm_mmcsd_host_ops = .request = hpm_sdmmc_request, .set_iocfg = hpm_sdmmc_set_iocfg, .get_card_status = NULL, - .enable_sdio_irq = NULL, // Do not use the interrupt mode, use DMA instead + .enable_sdio_irq = NULL, + .execute_tuning = hpm_sdmmc_execute_tuning, + .switch_uhs_voltage = hpm_sdmmc_switch_uhs_voltage, + }; +#if defined(BSP_USING_SDXC0) /* Place the ADMA2 table to non-cacheable region */ -ATTR_PLACE_AT_NONCACHEABLE static uint32_t s_sdxc_adma2_table[SDXC_ADMA_TABLE_WORDS]; +ATTR_PLACE_AT_NONCACHEABLE static uint32_t s_sdxc0_adma2_table[SDXC_ADMA_TABLE_WORDS]; +/* SDXC0 */ +static struct hpm_mmcsd s_hpm_sdxc0 = +{ + .name = "sd0", + .sdxc_base = HPM_SDXC0, + .sdxc_adma2_table = s_sdxc0_adma2_table, + .irq_num = IRQn_SDXC0, +#if defined(BSP_SDXC0_BUS_WIDTH_8BIT) + .support_8bit = true, + .support_4bit = true, +#elif defined(BSP_SDXC0_BUS_WIDTH_4BIT) + .support_4bit = true, +#elif defined(BSP_SDXC0_BUS_WIDTH_1BIT) +#else + .support_4bit = true, +#endif +#if defined(BSP_SDXC0_VOLTAGE_3V3) + .support_3v3 = true, +#endif +#if defined(BSP_SDXC0_VOLTAGE_1V8) + .support_1v8 = true, +#endif +#if defined(BSP_SDXC0_VOLTAGE_DUAL) + .support_3v3 = true, + .support_1v8 = true, +#endif + +#if defined(BSP_SDXC0_VSEL_PIN) + .vsel_pin_name = BSP_SDXC0_VSEL_PIN, +#endif +#if defined(BSP_SDXC0_PWR_PIN) + .pwr_pin_name = BSP_SDXC0_PWR_PIN, +#endif +}; +#endif + +#if defined(BSP_USING_SDXC1) +/* Place the ADMA2 table to non-cacheable region */ +ATTR_PLACE_AT_NONCACHEABLE static uint32_t s_sdxc1_adma2_table[SDXC_ADMA_TABLE_WORDS]; +static struct hpm_mmcsd s_hpm_sdxc1 = +{ + .name = "sd1", + .sdxc_base = HPM_SDXC1, + .sdxc_adma2_table = s_sdxc1_adma2_table, + .irq_num = IRQn_SDXC1, +#if defined(BSP_SDXC1_BUS_WIDTH_8BIT) + .support_8bit = true, + .support_4bit = true, +#elif defined(BSP_SDXC1_BUS_WIDTH_4BIT) + .support_4bit = true, +#elif defined(BSP_SDXC1_BUS_WIDTH_1BIT) +#else + .support_4bit = true, +#endif -static int hpm_sdmmc_transfer(SDXC_Type *base, sdxc_adma_config_t *dma_config, sdxc_xfer_t *xfer) +#if defined(BSP_SDXC1_VOLTAGE_3V3) + .support_3v3 = true, +#endif +#if defined(BSP_SDXC1_VOLTAGE_1V8) + .support_1v8 = true, +#endif +#if defined(BSP_SDXC1_VOLTAGE_DUAL) + .support_3v3 = true, + .support_1v8 = true, +#endif +#if defined(BSP_SDXC1_VSEL_PIN) + .vsel_pin_name = BSP_SDXC1_VSEL_PIN, +#endif +#if defined(BSP_SDXC1_PWR_PIN) + .pwr_pin_name = BSP_SDXC1_PWR_PIN, +#endif +}; +#endif + +static struct hpm_mmcsd *hpm_sdxcs[] = +{ +#if defined(BSP_USING_SDXC0) + &s_hpm_sdxc0, +#endif +#if defined(BSP_USING_SDXC1) + &s_hpm_sdxc1, +#endif +}; + +static rt_int32_t hpm_sdmmc_execute_tuning(struct rt_mmcsd_host *host, rt_int32_t opcode) +{ + RT_ASSERT(host != RT_NULL); RT_ASSERT(host->private_data != RT_NULL); + + struct hpm_mmcsd *mmcsd = (struct hpm_mmcsd *) host->private_data; + SDXC_Type *base = mmcsd->sdxc_base; + + /* Prepare the Auto tuning environment */ + sdxc_stop_clock_during_phase_code_change(base, true); + sdxc_set_post_change_delay(base, 3U); + sdxc_select_cardclk_delay_source(base, false); + sdxc_enable_power(base, true); + hpm_stat_t err = sdxc_perform_auto_tuning(base, opcode); + + return (err != status_success) ? -RT_EPERM : RT_EOK; +} + +static hpm_stat_t hpm_sdmmc_transfer(SDXC_Type *base, sdxc_adma_config_t *dma_config, sdxc_xfer_t *xfer) { hpm_stat_t status; sdxc_command_t *cmd = xfer->command; @@ -103,7 +358,7 @@ static int hpm_sdmmc_transfer(SDXC_Type *base, sdxc_adma_config_t *dma_config, s } } - return (status == status_success) ? RT_EOK : -RT_ERROR; + return status; } /** @@ -120,7 +375,8 @@ static void hpm_sdmmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r sdxc_xfer_t xfer = { 0 }; sdxc_command_t sdxc_cmd = { 0 }; sdxc_data_t sdxc_data = { 0 }; - uint32_t *aligned_buf = NULL; + uint32_t *raw_alloc_buf = RT_NULL; + uint32_t *aligned_buf = RT_NULL; hpm_stat_t err = status_invalid_argument; struct hpm_mmcsd *mmcsd = (struct hpm_mmcsd *) host->private_data; struct rt_mmcsd_cmd *cmd = req->cmd; @@ -166,6 +422,7 @@ static void hpm_sdmmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r } sdxc_cmd.cmd_flags = 0UL; xfer.command = &sdxc_cmd; + xfer.data = NULL; if (data != NULL) { sdxc_data.enable_auto_cmd12 = false; @@ -181,50 +438,82 @@ static void hpm_sdmmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r adma_config.adma_table = (uint32_t*) core_local_mem_to_sys_address(BOARD_RUNNING_CORE, (uint32_t) mmcsd->sdxc_adma2_table); adma_config.adma_table_words = SDXC_ADMA_TABLE_WORDS; - + size_t xfer_buf_addr = (uint32_t)data->buf; + uint32_t xfer_len = data->blks * data->blksize; if ((req->data->flags & DATA_DIR_WRITE) != 0U) { - uint32_t write_size = data->blks * data->blksize; - if (!SDXC_IS_CACHELINE_ALIGNED(data->buf) || !SDXC_IS_CACHELINE_ALIGNED(write_size)) + uint32_t write_size = xfer_len; + size_t aligned_start; + uint32_t aligned_size; +#if defined(HPM_SDXC_ALLOC_CACHELINE_ALIGNED_BUF) && (HPM_SDXC_ALLOC_CACHELINE_ALIGNED_BUF == 1) + if (!SDXC_IS_CACHELINE_ALIGNED(xfer_buf_addr) || !SDXC_IS_CACHELINE_ALIGNED(write_size)) +#else + if ((xfer_buf_addr % 4 != 0) && (write_size % 4 != 0)) +#endif { - write_size = SDXC_CACHELINE_ALIGN_UP(write_size); - aligned_buf = (uint32_t *) rt_malloc_align(write_size, CACHE_LINESIZE); - rt_memcpy(aligned_buf, data->buf, write_size); - sdxc_data.tx_data = aligned_buf; - rt_enter_critical(); - l1c_dc_flush((uint32_t) sdxc_data.tx_data, write_size); - rt_exit_critical(); + write_size = SDXC_CACHELINE_ALIGN_UP(xfer_len); + raw_alloc_buf = (uint32_t *) rt_malloc(write_size + CACHE_LINESIZE - RT_ALIGN_SIZE); + RT_ASSERT(raw_alloc_buf != RT_NULL); + aligned_buf = (uint32_t *) SDXC_CACHELINE_ALIGN_UP(raw_alloc_buf); + RT_ASSERT(aligned_buf != RT_NULL); + memcpy(aligned_buf, data->buf, xfer_len); + memset(aligned_buf + write_size, 0, write_size - xfer_len); + sdxc_data.tx_data = (uint32_t const *) core_local_mem_to_sys_address(BOARD_RUNNING_CORE, (uint32_t) aligned_buf); + + aligned_start = (uint32_t)sdxc_data.tx_data; + aligned_size = write_size; } else { - sdxc_data.tx_data = (uint32_t const *) core_local_mem_to_sys_address(BOARD_RUNNING_CORE, - (uint32_t) data->buf); - rt_enter_critical(); - l1c_dc_flush((uint32_t) data->buf, write_size); - rt_exit_critical(); + sdxc_data.tx_data = (uint32_t const *) core_local_mem_to_sys_address(BOARD_RUNNING_CORE, xfer_buf_addr); + + aligned_start = SDXC_CACHELINE_ALIGN_DOWN(sdxc_data.tx_data); + size_t aligned_end = SDXC_CACHELINE_ALIGN_UP((uint32_t)sdxc_data.tx_data + write_size); + aligned_size = aligned_end - aligned_start; } + rt_base_t level = rt_hw_interrupt_disable(); + l1c_dc_flush(aligned_start, aligned_size); + rt_hw_interrupt_enable(level); sdxc_data.rx_data = NULL; } else { - uint32_t read_size = data->blks * data->blksize; - if (!SDXC_IS_CACHELINE_ALIGNED(data->buf) || !SDXC_IS_CACHELINE_ALIGNED(read_size)) + uint32_t read_size = xfer_len; +#if defined(HPM_SDXC_ALLOC_CACHELINE_ALIGNED_BUF) && (HPM_SDXC_ALLOC_CACHELINE_ALIGNED_BUF == 1) + if (!SDXC_IS_CACHELINE_ALIGNED(xfer_buf_addr) || !SDXC_IS_CACHELINE_ALIGNED(read_size)) +#else + if ((xfer_buf_addr % 4 != 0) || (read_size % 4 != 0)) +#endif { uint32_t aligned_read_size = SDXC_CACHELINE_ALIGN_UP(read_size); - aligned_buf = (uint32_t *) rt_malloc_align(aligned_read_size, CACHE_LINESIZE); - sdxc_data.rx_data = aligned_buf; + raw_alloc_buf = (uint32_t *) rt_malloc(aligned_read_size + CACHE_LINESIZE - RT_ALIGN_SIZE); + RT_ASSERT(raw_alloc_buf != RT_NULL); + aligned_buf = (uint32_t *) SDXC_CACHELINE_ALIGN_UP(raw_alloc_buf); + sdxc_data.rx_data = (uint32_t*) core_local_mem_to_sys_address(BOARD_RUNNING_CORE, (uint32_t) aligned_buf); } else { - sdxc_data.rx_data = (uint32_t*) core_local_mem_to_sys_address(BOARD_RUNNING_CORE, (uint32_t) data->buf); + sdxc_data.rx_data = (uint32_t*) core_local_mem_to_sys_address(BOARD_RUNNING_CORE, xfer_buf_addr); + size_t aligned_start = SDXC_CACHELINE_ALIGN_DOWN(sdxc_data.rx_data); + size_t aligned_end = SDXC_CACHELINE_ALIGN_UP((uint32_t)sdxc_data.rx_data + read_size); + uint32_t aligned_size = aligned_end - aligned_start; + rt_base_t level = rt_hw_interrupt_disable(); + l1c_dc_flush(aligned_start, aligned_size); + rt_hw_interrupt_enable(level); } - sdxc_data.tx_data = NULL; + sdxc_data.tx_data = RT_NULL; } xfer.data = &sdxc_data; - } - else - { - xfer.data = NULL; + + /* Align the write/read size since the ADMA2 engine in the SDXC cannot transfer unaligned size of data */ + if ((cmd->cmd_code == SD_IO_RW_EXTENDED) && (xfer_len % 4 != 0)) + { + sdio_cmd53_arg_t cmd53_arg; + cmd53_arg.value = sdxc_cmd.cmd_argument; + cmd53_arg.count = HPM_ALIGN_UP(xfer_len, 4); + sdxc_cmd.cmd_argument = cmd53_arg.value; + sdxc_data.block_size = HPM_ALIGN_UP(xfer_len, 4); + } } if ((req->data->blks > 1) && ((cmd->cmd_code == READ_MULTIPLE_BLOCK) || ((cmd->cmd_code == WRITE_MULTIPLE_BLOCK)))) @@ -237,7 +526,10 @@ static void hpm_sdmmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r if (err != status_success) { hpm_sdmmc_host_recovery(mmcsd->sdxc_base); - LOG_E(" ***hpm_sdmmc_transfer error: %d*** -->\n", err); + if (err != status_sdxc_cmd_timeout_error) /* Ignore command timeout error by default */ + { + LOG_E(" ***hpm_sdmmc_transfer error: %d, cmd:%d, arg:0x%x*** -->\n", err, cmd->cmd_code, cmd->arg); + } cmd->err = -RT_ERROR; } else @@ -256,26 +548,30 @@ static void hpm_sdmmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r if ((sdxc_data.rx_data != NULL) && (cmd->err == RT_EOK)) { uint32_t read_size = data->blks * data->blksize; - if (aligned_buf != NULL) + if (aligned_buf != RT_NULL) { uint32_t aligned_read_size = SDXC_CACHELINE_ALIGN_UP(read_size); - rt_enter_critical(); + rt_base_t level = rt_hw_interrupt_disable(); l1c_dc_invalidate((uint32_t) aligned_buf, aligned_read_size); - rt_exit_critical(); - rt_memcpy(data->buf, aligned_buf, read_size); + rt_hw_interrupt_enable(level); + memcpy(data->buf, aligned_buf, read_size); } else { - rt_enter_critical(); - l1c_dc_invalidate((uint32_t) data->buf, read_size); - rt_exit_critical(); + size_t aligned_start = SDXC_CACHELINE_ALIGN_DOWN(sdxc_data.rx_data); + size_t aligned_end = SDXC_CACHELINE_ALIGN_UP((uint32_t)sdxc_data.rx_data + read_size); + uint32_t aligned_size = aligned_end - aligned_start; + rt_base_t level = rt_hw_interrupt_disable(); + l1c_dc_invalidate(aligned_start, aligned_size); + rt_hw_interrupt_enable(level); } } - if (aligned_buf != NULL) + if (raw_alloc_buf != RT_NULL) { - rt_free_align(aligned_buf); - aligned_buf = NULL; + rt_free(raw_alloc_buf); + raw_alloc_buf = RT_NULL; + aligned_buf = RT_NULL; } if ((cmd->flags & RESP_MASK) == RESP_R2) @@ -293,6 +589,23 @@ static void hpm_sdmmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r mmcsd_req_complete(host); } +static void hpm_sdmmc_set_cardclk_delay_chain(struct hpm_mmcsd *mmcsd) +{ + SDXC_Type *base = mmcsd->sdxc_base; + bool need_inverse = sdxc_is_inverse_clock_enabled(base); + sdxc_enable_inverse_clock(base, false); + sdxc_enable_sd_clock(base, false); + uint32_t num_delaycells = sdxc_get_default_cardclk_delay_chain(base, mmcsd->freq); + sdxc_set_cardclk_delay_chain(base, num_delaycells); + sdxc_enable_inverse_clock(base, need_inverse); + sdxc_enable_sd_clock(base, true); +} + +ATTR_WEAK void init_sdxc_ds_pin(SDXC_Type *base) +{ + LOG_W("Ignore this warning if the DS pin is not supported\n"); +} + /** * !@brief Set IO Configuration for HPMicro IO and SDXC Host */ @@ -303,21 +616,26 @@ static void hpm_sdmmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_c RT_ASSERT(io_cfg != RT_NULL); struct hpm_mmcsd *mmcsd = (struct hpm_mmcsd *) host->private_data; + + /* Power control */ uint32_t vdd = io_cfg->vdd; if (io_cfg->power_mode != mmcsd->power_mode) { switch(io_cfg->power_mode) { case MMCSD_POWER_OFF: - board_sd_power_switch(mmcsd->sdxc_base, false); + hpm_sdmmc_power_off_via_pin(mmcsd); break; case MMCSD_POWER_ON: - board_sd_power_switch(mmcsd->sdxc_base, true); + hpm_sdmmc_power_on_via_pin(mmcsd); break; case MMCSD_POWER_UP: - board_sd_power_switch(mmcsd->sdxc_base, false); + hpm_sdmmc_power_off_via_pin(mmcsd); rt_thread_mdelay(10); - board_sd_power_switch(mmcsd->sdxc_base, true); + hpm_sdmmc_power_on_via_pin(mmcsd); + /* After power up, wait 1ms, then wait 74 card clock */ + rt_thread_mdelay(1); + sdxc_wait_card_active(mmcsd->sdxc_base); break; default: /* Do nothing */ @@ -326,6 +644,23 @@ static void hpm_sdmmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_c mmcsd->power_mode = io_cfg->power_mode; } + /* Voltage switch */ + if (mmcsd->vdd != vdd) + { + if (vdd == 7) + { + /* Switch to 1.8V */ + hpm_sdmmc_switch_to_1v8_via_pin(mmcsd); + } + else + { + /* Switch to 3V */ + hpm_sdmmc_switch_to_3v3_via_pin(mmcsd); + } + mmcsd->vdd = vdd; + } + + /* Set bus width */ if (mmcsd->bus_width != io_cfg->bus_width) { switch (io_cfg->bus_width) @@ -343,6 +678,9 @@ static void hpm_sdmmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_c mmcsd->bus_width = io_cfg->bus_width; } + /* Set timing mode */ + + bool need_config_ds = false; if (mmcsd->timing != io_cfg->timing) { switch (io_cfg->timing) @@ -368,30 +706,72 @@ static void hpm_sdmmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_c break; case MMCSD_TIMING_UHS_DDR50: sdxc_set_speed_mode(mmcsd->sdxc_base, sdxc_sd_speed_ddr50); + /* Must switch to 1.8V signaling for UHS_DDR50 */ + sdxc_select_voltage(mmcsd->sdxc_base, sdxc_bus_voltage_sd_1v8); break; case MMCSD_TIMING_MMC_DDR52: + sdxc_enable_emmc_support(mmcsd->sdxc_base, true); sdxc_set_speed_mode(mmcsd->sdxc_base, sdxc_emmc_speed_high_speed_ddr); break; case MMCSD_TIMING_MMC_HS200: + sdxc_enable_emmc_support(mmcsd->sdxc_base, true); sdxc_set_speed_mode(mmcsd->sdxc_base, sdxc_emmc_speed_hs200); break; case MMCSD_TIMING_MMC_HS400: + case MMCSD_TIMING_MMC_HS400_ENH_DS: + sdxc_enable_emmc_support(mmcsd->sdxc_base, true); sdxc_set_speed_mode(mmcsd->sdxc_base, sdxc_emmc_speed_hs400); + if (io_cfg->timing == MMCSD_TIMING_MMC_HS400_ENH_DS) + { + sdxc_enable_enhanced_strobe(mmcsd->sdxc_base, true); + uint32_t num_delaycells = sdxc_get_default_strobe_delay(mmcsd->sdxc_base); + sdxc_set_data_strobe_delay(mmcsd->sdxc_base, num_delaycells); + } + need_config_ds = true; break; } mmcsd->timing = io_cfg->timing; } - board_init_sd_pins(mmcsd->sdxc_base); + /* Initialize SDXC Pins */ + bool open_drain = io_cfg->bus_mode == MMCSD_BUSMODE_OPENDRAIN; + bool is_1v8 = (io_cfg->vdd == 7) || (mmcsd->host->valid_ocr == VDD_165_195); + uint32_t width = (io_cfg->bus_width == MMCSD_BUS_WIDTH_8) ? 8 : ((io_cfg->bus_width == MMCSD_BUS_WIDTH_4) ? 4 : 1); + init_sdxc_cmd_pin(mmcsd->sdxc_base, open_drain, is_1v8); + init_sdxc_clk_data_pins(mmcsd->sdxc_base, width, is_1v8); + rt_thread_mdelay(1); + if (need_config_ds) + { + init_sdxc_ds_pin(mmcsd->sdxc_base); + rt_thread_mdelay(1); + } + /* Initialize SDXC clock */ uint32_t sdxc_clock = io_cfg->clock; if (sdxc_clock != 0U) { if (mmcsd->freq != sdxc_clock) { + bool need_reverse = true; + bool need_card_delay_clk = false; + if ((mmcsd->timing == MMCSD_TIMING_UHS_DDR50) || + (mmcsd->timing == MMCSD_TIMING_MMC_DDR52) || + (mmcsd->timing == MMCSD_TIMING_MMC_HS400) || + (mmcsd->timing == MMCSD_TIMING_MMC_HS400_ENH_DS)) + { + need_reverse = false; + need_card_delay_clk = true; + } + /* Ensure request frequency from mmcsd stack level doesn't exceed maximum supported frequency by host */ uint32_t clock_freq = MIN(mmcsd->host->freq_max, sdxc_clock); - board_sd_configure_clock(mmcsd->sdxc_base, clock_freq); + clock_freq = board_sd_configure_clock(mmcsd->sdxc_base, clock_freq, need_reverse); + LOG_I("mmcsd clock: %dHz\n", clock_freq); mmcsd->freq = sdxc_clock; + + if (need_card_delay_clk) + { + hpm_sdmmc_set_cardclk_delay_chain(mmcsd); + } } } } @@ -431,7 +811,6 @@ static void hpm_sdmmc_host_recovery(SDXC_Type *base) } uint32_t int_stat = sdxc_get_interrupt_status(base); - if ((int_stat & 0xF0000UL) != 0U) { need_reset_cmd_line = true; @@ -456,7 +835,6 @@ static void hpm_sdmmc_host_recovery(SDXC_Type *base) } rt_thread_mdelay(10); - LOG_E("%s\n", __func__); } int rt_hw_sdio_init(void) @@ -465,51 +843,104 @@ int rt_hw_sdio_init(void) struct rt_mmcsd_host *host = NULL; struct hpm_mmcsd *mmcsd = NULL; - do - { + + for (uint32_t i = 0; i < ARRAY_SIZE(hpm_sdxcs); i++) { host = mmcsd_alloc_host(); if (host == NULL) { err = -RT_ERROR; break; } - mmcsd = rt_malloc(sizeof(struct hpm_mmcsd)); - if (mmcsd == NULL) + mmcsd = hpm_sdxcs[i]; + host->ops = &hpm_mmcsd_host_ops; + host->freq_min = 375000; + host->freq_max = 50000000; + host->valid_ocr = 0; + + /* Determine supported Voltage range */ + if (mmcsd->support_3v3) { - LOG_E("allocate hpm_mmcsd failed\n"); - err = -RT_ERROR; - break; + host->valid_ocr |= VDD_30_31 | VDD_31_32 | VDD_32_33 | VDD_33_34; + } + if (mmcsd->support_1v8) + { + host->valid_ocr |= VDD_165_195; } - rt_memset(mmcsd, 0, sizeof(struct hpm_mmcsd)); - mmcsd->sdxc_base = BOARD_APP_SDCARD_SDXC_BASE; - mmcsd->sdxc_adma2_table = s_sdxc_adma2_table; + /* Determine Host supported features */ + host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ; + if (mmcsd->support_4bit) + { + host->flags |= MMCSD_BUSWIDTH_4; + } + if (mmcsd->support_8bit) { + host->flags |= MMCSD_BUSWIDTH_8; + } - host->ops = &hpm_mmcsd_host_ops; - host->freq_min = 375000; - host->freq_max = 50000000; - host->valid_ocr = VDD_30_31 | VDD_31_32 | VDD_32_33 | VDD_33_34; - host->flags = MMCSD_MUTBLKWRITE | MMCSD_BUSWIDTH_4 | MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ; + if (mmcsd->support_1v8) + { + host->freq_max = 166000000; + host->flags |= MMCSD_SUP_HS200_1V8; + + host->flags |= MMCSD_SUP_SDR50 | MMCSD_SUP_SDR104; + if (sdxc_is_ddr50_supported(mmcsd->sdxc_base)) + { + host->flags |= MMCSD_SUP_DDR50; + } + + if (mmcsd->support_8bit) + { + host->flags |= MMCSD_SUP_HS400_1V8 | MMCSD_SUP_ENH_DS; + } + } - host->max_seg_size = 65535; - host->max_dma_segs = 2; + /* For eMMC device, add High Speed DDR mode support as long as it is supported by the host controller */ + if (sdxc_is_ddr50_supported(mmcsd->sdxc_base)) + { + host->flags |= MMCSD_SUP_HIGHSPEED_DDR; + } + + rt_strncpy(host->name, mmcsd->name, RT_NAME_MAX); + + host->max_seg_size = 0x80000; + host->max_dma_segs = 1; host->max_blk_size = 512; - host->max_blk_count = 4096; + host->max_blk_count = 1024; mmcsd->host = host; /* Perform necessary initialization */ - board_sd_configure_clock(mmcsd->sdxc_base, 375000); + board_sd_configure_clock(mmcsd->sdxc_base, 375000, true); sdxc_config_t sdxc_config = { 0 }; - sdxc_config.data_timeout = SDXC_DATA_TIMEOUT; + sdxc_config.data_timeout = 1000; sdxc_init(mmcsd->sdxc_base, &sdxc_config); host->private_data = mmcsd; - mmcsd_change(host); + /* Initialize PWR pin and VSEL pin */ + if (mmcsd->pwr_pin_name != RT_NULL) + { + hpm_sdmmc_pin_init(mmcsd->pwr_pin_name, true); + rt_thread_mdelay(1); - } while (false); + if (host->valid_ocr == VDD_165_195) + { + hpm_sdmmc_switch_to_1v8_via_pin(mmcsd); + } + else + { + hpm_sdmmc_switch_to_3v3_via_pin(mmcsd); + } + } + if (mmcsd->vsel_pin_name != RT_NULL) + { + hpm_sdmmc_pin_init(mmcsd->vsel_pin_name, true); + rt_thread_mdelay(1); + } + + mmcsd_change(host); + }; if (err != RT_EOK) { diff --git a/bsp/hpmicro/libraries/drivers/drv_spi.c b/bsp/hpmicro/libraries/drivers/drv_spi.c index cf033e345c9..9a5f972262b 100644 --- a/bsp/hpmicro/libraries/drivers/drv_spi.c +++ b/bsp/hpmicro/libraries/drivers/drv_spi.c @@ -8,6 +8,7 @@ * 2022-02-01 HPMicro First version * 2023-02-15 HPMicro Add DMA support * 2023-07-14 HPMicro Manage the DMA buffer alignment in driver + * 2023-12-14 HPMicro change state blocking wait to interrupt semaphore wait for DMA */ #include @@ -17,12 +18,13 @@ #include "drv_spi.h" #include "hpm_spi_drv.h" #include "hpm_sysctl_drv.h" -#include "hpm_dma_manager.h" +#include "hpm_dma_mgr.h" #include "hpm_dmamux_drv.h" #include "hpm_l1c_drv.h" + struct hpm_spi { uint32_t instance; @@ -34,8 +36,12 @@ struct hpm_spi rt_bool_t enable_dma; rt_uint8_t tx_dmamux; rt_uint8_t rx_dmamux; - hpm_dma_resource_t tx_dma; - hpm_dma_resource_t rx_dma; + dma_resource_t tx_dma; + dma_resource_t rx_dma; + rt_uint8_t spi_irq; + rt_sem_t spi_xfer_done_sem; + rt_sem_t txdma_xfer_done_sem; + rt_sem_t rxdma_xfer_done_sem; }; static rt_err_t hpm_spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg); @@ -47,36 +53,48 @@ static struct hpm_spi hpm_spis[] = { .bus_name = "spi0", .spi_base = HPM_SPI0, +#if defined(BSP_SPI0_USING_DMA) .enable_dma = RT_TRUE, +#endif .tx_dmamux = HPM_DMA_SRC_SPI0_TX, .rx_dmamux = HPM_DMA_SRC_SPI0_RX, + .spi_irq = IRQn_SPI0, }, #endif #if defined(BSP_USING_SPI1) { .bus_name = "spi1", .spi_base = HPM_SPI1, +#if defined(BSP_SPI1_USING_DMA) .enable_dma = RT_TRUE, +#endif .tx_dmamux = HPM_DMA_SRC_SPI1_TX, .rx_dmamux = HPM_DMA_SRC_SPI1_RX, + .spi_irq = IRQn_SPI1, }, #endif #if defined(BSP_USING_SPI2) { .bus_name = "spi2", .spi_base = HPM_SPI2, +#if defined(BSP_SPI2_USING_DMA) .enable_dma = RT_TRUE, +#endif .tx_dmamux = HPM_DMA_SRC_SPI2_TX, .rx_dmamux = HPM_DMA_SRC_SPI2_RX, + .spi_irq = IRQn_SPI2, }, #endif #if defined(BSP_USING_SPI3) { .bus_name = "spi3", .spi_base = HPM_SPI3, +#if defined(BSP_SPI3_USING_DMA) .enable_dma = RT_TRUE, +#endif .tx_dmamux = HPM_DMA_SRC_SPI3_TX, .rx_dmamux = HPM_DMA_SRC_SPI3_RX, + .spi_irq = IRQn_SPI3, }, #endif }; @@ -87,6 +105,80 @@ static struct rt_spi_ops hpm_spi_ops = .xfer = hpm_spi_xfer, }; +static inline void handle_spi_isr(SPI_Type *ptr) +{ + volatile uint32_t irq_status; + RT_ASSERT(ptr != RT_NULL); + rt_base_t level; + level = rt_hw_interrupt_disable(); + irq_status = spi_get_interrupt_status(ptr); + if (irq_status & spi_end_int) + { + for (uint32_t i = 0; i < sizeof(hpm_spis) / sizeof(hpm_spis[0]); i++) + { + if (hpm_spis[i].spi_base == ptr) + { + rt_sem_release(hpm_spis[i].spi_xfer_done_sem); + } + } + spi_disable_interrupt(ptr, spi_end_int); + spi_clear_interrupt_status(ptr, spi_end_int); + } + rt_hw_interrupt_enable(level); +} + +#if defined(BSP_USING_SPI0) +void spi0_isr(void) +{ + handle_spi_isr(HPM_SPI0); +} +SDK_DECLARE_EXT_ISR_M(IRQn_SPI0, spi0_isr); +#endif + +#if defined(BSP_USING_SPI1) +void spi1_isr(void) +{ + handle_spi_isr(HPM_SPI1); +} +SDK_DECLARE_EXT_ISR_M(IRQn_SPI1, spi1_isr); +#endif + +#if defined(BSP_USING_SPI2) +void spi2_isr(void) +{ + handle_spi_isr(HPM_SPI2); +} +SDK_DECLARE_EXT_ISR_M(IRQn_SPI2, spi2_isr); +#endif + +#if defined(BSP_USING_SPI3) +void spi3_isr(void) +{ + handle_spi_isr(HPM_SPI3); +} +SDK_DECLARE_EXT_ISR_M(IRQn_SPI3, spi3_isr); +#endif + +void spi_dma_channel_tc_callback(DMA_Type *ptr, uint32_t channel, void *user_data) +{ + struct hpm_spi *spi = (struct hpm_spi *)user_data; + RT_ASSERT(spi != RT_NULL); + RT_ASSERT(ptr != RT_NULL); + rt_base_t level; + level = rt_hw_interrupt_disable(); + if ((spi->tx_dma.base == ptr) && spi->tx_dma.channel == channel) + { + dma_mgr_disable_chn_irq(&spi->tx_dma, DMA_MGR_INTERRUPT_MASK_TC); + rt_sem_release(spi->txdma_xfer_done_sem); + } + if ((spi->rx_dma.base == ptr) && spi->rx_dma.channel == channel) + { + dma_mgr_disable_chn_irq(&spi->rx_dma, DMA_MGR_INTERRUPT_MASK_TC); + rt_sem_release(spi->rxdma_xfer_done_sem); + } + rt_hw_interrupt_enable(level); +} + static rt_err_t hpm_spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg) { spi_timing_config_t timing_config = { 0 }; @@ -99,13 +191,13 @@ static rt_err_t hpm_spi_configure(struct rt_spi_device *device, struct rt_spi_co if (cfg->data_width != 8 && cfg->data_width != 16 && cfg->data_width != 32) { - return RT_EINVAL; + return -RT_EINVAL; } spi_master_get_default_timing_config(&timing_config); spi_master_get_default_format_config(&format_config); - init_spi_pins(spi->spi_base); + init_spi_pins_with_gpio_as_cs(spi->spi_base); timing_config.master_config.clk_src_freq_in_hz = board_init_spi_clock(spi->spi_base); @@ -124,7 +216,6 @@ static rt_err_t hpm_spi_configure(struct rt_spi_device *device, struct rt_spi_co spi_master_timing_init(spi->spi_base, &timing_config); - spi_master_get_default_control_config(&spi->control_config); spi->control_config.master_config.addr_enable = false; spi->control_config.master_config.cmd_enable = false; @@ -147,7 +238,7 @@ static hpm_stat_t hpm_spi_xfer_polling(struct rt_spi_device *device, struct rt_s uint8_t *rx_buf = (uint8_t*) msg->recv_buf; while (remaining_size > 0) { - transfer_len = MIN(512, remaining_size); + transfer_len = MIN(SPI_SOC_TRANSFER_COUNT_MAX, remaining_size); spi->control_config.common_config.tx_dma_enable = false; spi->control_config.common_config.rx_dma_enable = false; if (msg->send_buf != NULL && msg->recv_buf != NULL) @@ -221,22 +312,6 @@ hpm_stat_t spi_rx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, SPI_Type *spi_p return dma_setup_handshake(dma_ptr, &config, true); } - -static hpm_stat_t hpm_spi_wait_idle(SPI_Type *ptr) -{ - hpm_stat_t status = status_success; - rt_tick_t start_tick = rt_tick_get(); - while(ptr->STATUS & SPI_STATUS_SPIACTIVE_MASK) - { - if ((rt_tick_get() - start_tick) > RT_TICK_PER_SECOND) - { - status = status_timeout; - break; - } - } - return status; -} - static rt_uint32_t hpm_spi_xfer_dma(struct rt_spi_device *device, struct rt_spi_message *msg) { struct hpm_spi *spi = (struct hpm_spi *) (device->bus->parent.user_data); @@ -248,63 +323,66 @@ static rt_uint32_t hpm_spi_xfer_dma(struct rt_spi_device *device, struct rt_spi_ uint8_t *aligned_tx_buf = RT_NULL; uint8_t *aligned_rx_buf = RT_NULL; uint32_t aligned_len = 0; - if (msg->length > 0) + if (msg->length <= 0) { - aligned_len = (msg->length + HPM_L1C_CACHELINE_SIZE - 1U) & ~(HPM_L1C_CACHELINE_SIZE - 1U); - if (msg->send_buf != RT_NULL) + return status_invalid_argument; + } + aligned_len = (msg->length + HPM_L1C_CACHELINE_SIZE - 1U) & ~(HPM_L1C_CACHELINE_SIZE - 1U); + if (msg->send_buf != RT_NULL) + { + if (l1c_dc_is_enabled()) { - if (l1c_dc_is_enabled()) - { - /* The allocated pointer is always RT_ALIGN_SIZE aligned */ + /* The allocated pointer is always RT_ALIGN_SIZE aligned */ raw_alloc_tx_buf = (uint8_t*)rt_malloc(aligned_len + HPM_L1C_CACHELINE_SIZE - RT_ALIGN_SIZE); RT_ASSERT(raw_alloc_tx_buf != RT_NULL); aligned_tx_buf = (uint8_t*)HPM_L1C_CACHELINE_ALIGN_UP((uint32_t)raw_alloc_tx_buf); rt_memcpy(aligned_tx_buf, msg->send_buf, msg->length); l1c_dc_flush((uint32_t) aligned_tx_buf, aligned_len); - } - else - { - aligned_tx_buf = (uint8_t*) msg->send_buf; - } + } - if (msg->recv_buf != RT_NULL) + else { - if (l1c_dc_is_enabled()) - { - /* The allocated pointer is always RT_ALIGN_SIZE aligned */ - raw_alloc_rx_buf = (uint8_t*)rt_malloc(aligned_len + HPM_L1C_CACHELINE_SIZE - RT_ALIGN_SIZE); - RT_ASSERT(raw_alloc_rx_buf != RT_NULL); - aligned_rx_buf = (uint8_t*)HPM_L1C_CACHELINE_ALIGN_UP((uint32_t)raw_alloc_rx_buf); - } - else - { - aligned_rx_buf = msg->recv_buf; - } + aligned_tx_buf = (uint8_t*) msg->send_buf; + } + } + if (msg->recv_buf != RT_NULL) + { + if (l1c_dc_is_enabled()) + { + /* The allocated pointer is always RT_ALIGN_SIZE aligned */ + raw_alloc_rx_buf = (uint8_t*)rt_malloc(aligned_len + HPM_L1C_CACHELINE_SIZE - RT_ALIGN_SIZE); + RT_ASSERT(raw_alloc_rx_buf != RT_NULL); + aligned_rx_buf = (uint8_t*)HPM_L1C_CACHELINE_ALIGN_UP((uint32_t)raw_alloc_rx_buf); + } + else + { + aligned_rx_buf = msg->recv_buf; } } + uint8_t *tx_buf = aligned_tx_buf; uint8_t *rx_buf = aligned_rx_buf; uint32_t core_id = read_csr(CSR_MHARTID); spi->spi_base->CTRL &= ~(SPI_CTRL_TXDMAEN_MASK | SPI_CTRL_RXDMAEN_MASK); + spi->control_config.common_config.tx_dma_enable = false; + spi->control_config.common_config.rx_dma_enable = false; + spi_disable_interrupt(spi->spi_base, spi_end_int); while (remaining_size > 0) { - transfer_len = MIN(512, remaining_size); - spi->control_config.common_config.tx_dma_enable = false; - spi->control_config.common_config.rx_dma_enable = false; + transfer_len = MIN(SPI_SOC_TRANSFER_COUNT_MAX, remaining_size); if (msg->send_buf != NULL && msg->recv_buf != NULL) { - spi->control_config.common_config.trans_mode = spi_trans_write_read_together; + spi_enable_interrupt(spi->spi_base, spi_end_int); spi->control_config.common_config.tx_dma_enable = true; spi->control_config.common_config.rx_dma_enable = true; spi->control_config.common_config.trans_mode = spi_trans_write_read_together; spi_stat = spi_setup_dma_transfer(spi->spi_base, &spi->control_config, NULL, NULL, transfer_len, - transfer_len); + transfer_len); if (spi_stat != status_success) { break; } - dmamux_config(HPM_DMAMUX, spi->tx_dma.channel, spi->tx_dmamux, true); spi_stat = spi_tx_trigger_dma(spi->tx_dma.base, spi->tx_dma.channel, spi->spi_base, core_local_mem_to_sys_address(core_id, (uint32_t) tx_buf), @@ -319,9 +397,15 @@ static rt_uint32_t hpm_spi_xfer_dma(struct rt_spi_device *device, struct rt_spi_ { break; } + dma_mgr_enable_chn_irq(&spi->tx_dma, DMA_MGR_INTERRUPT_MASK_TC); + dma_mgr_enable_chn_irq(&spi->rx_dma, DMA_MGR_INTERRUPT_MASK_TC); + rt_sem_take(spi->spi_xfer_done_sem, RT_WAITING_FOREVER); + rt_sem_take(spi->txdma_xfer_done_sem, RT_WAITING_FOREVER); + rt_sem_take(spi->rxdma_xfer_done_sem, RT_WAITING_FOREVER); } else if (msg->send_buf != NULL) { + spi_enable_interrupt(spi->spi_base, spi_end_int); spi->control_config.common_config.tx_dma_enable = true; spi->control_config.common_config.trans_mode = spi_trans_write_only; spi_stat = spi_setup_dma_transfer(spi->spi_base, &spi->control_config, NULL, NULL, transfer_len, 0); @@ -329,7 +413,6 @@ static rt_uint32_t hpm_spi_xfer_dma(struct rt_spi_device *device, struct rt_spi_ { break; } - dmamux_config(HPM_DMAMUX, spi->tx_dma.channel, spi->tx_dmamux, true); spi_stat = spi_tx_trigger_dma(spi->tx_dma.base, spi->tx_dma.channel, spi->spi_base, core_local_mem_to_sys_address(core_id, (uint32_t) tx_buf), @@ -338,6 +421,9 @@ static rt_uint32_t hpm_spi_xfer_dma(struct rt_spi_device *device, struct rt_spi_ { break; } + dma_mgr_enable_chn_irq(&spi->tx_dma, DMA_MGR_INTERRUPT_MASK_TC); + rt_sem_take(spi->spi_xfer_done_sem, RT_WAITING_FOREVER); + rt_sem_take(spi->txdma_xfer_done_sem, RT_WAITING_FOREVER); } else { @@ -348,7 +434,6 @@ static rt_uint32_t hpm_spi_xfer_dma(struct rt_spi_device *device, struct rt_spi_ { break; } - /* setup spi rx trigger dma transfer*/ dmamux_config(HPM_DMAMUX, spi->rx_dma.channel, spi->rx_dmamux, true); spi_stat = spi_rx_trigger_dma(spi->rx_dma.base, spi->rx_dma.channel, spi->spi_base, @@ -358,13 +443,11 @@ static rt_uint32_t hpm_spi_xfer_dma(struct rt_spi_device *device, struct rt_spi_ { break; } + spi_enable_interrupt(spi->spi_base, spi_end_int); + dma_mgr_enable_chn_irq(&spi->rx_dma, DMA_MGR_INTERRUPT_MASK_TC); + rt_sem_take(spi->spi_xfer_done_sem, RT_WAITING_FOREVER); + rt_sem_take(spi->rxdma_xfer_done_sem, RT_WAITING_FOREVER); } - spi_stat = hpm_spi_wait_idle(spi->spi_base); - if (spi_stat != status_success) - { - break; - } - if (tx_buf != NULL) { tx_buf += transfer_len; @@ -474,17 +557,22 @@ int rt_hw_spi_init(void) spi->spi_bus.parent.user_data = spi; if (spi->enable_dma) { - stat = dma_manager_request_resource(&spi->tx_dma); + stat = dma_mgr_request_resource(&spi->tx_dma); + dma_mgr_install_chn_tc_callback(&spi->tx_dma, spi_dma_channel_tc_callback, (void *)&hpm_spis[i]); if (stat != status_success) { return -RT_ERROR; } - stat = dma_manager_request_resource(&spi->rx_dma); + stat = dma_mgr_request_resource(&spi->rx_dma); + dma_mgr_install_chn_tc_callback(&spi->rx_dma, spi_dma_channel_tc_callback, (void *)&hpm_spis[i]); if (stat != status_success) { return -RT_ERROR; } + intc_m_enable_irq_with_priority(hpm_spis[i].spi_irq, 2); + dma_mgr_enable_dma_irq_with_priority(&spi->tx_dma, 1); + dma_mgr_enable_dma_irq_with_priority(&spi->rx_dma, 1); } ret = rt_spi_bus_register(&spi->spi_bus, spi->bus_name, &hpm_spi_ops); @@ -496,6 +584,35 @@ int rt_hw_spi_init(void) char sem_name[RT_NAME_MAX]; rt_sprintf(sem_name, "%s_s", hpm_spis[i].bus_name); hpm_spis[i].xfer_sem = rt_sem_create(sem_name, 0, RT_IPC_FLAG_PRIO); + if (hpm_spis[i].xfer_sem == RT_NULL) + { + ret = RT_ENOMEM; + break; + } + + rt_sprintf(sem_name, "%s_ds", hpm_spis[i].bus_name); + hpm_spis[i].spi_xfer_done_sem = rt_sem_create(sem_name, 0, RT_IPC_FLAG_PRIO); + if (hpm_spis[i].spi_xfer_done_sem == RT_NULL) + { + ret = RT_ENOMEM; + break; + } + + rt_sprintf(sem_name, "%s_rds", hpm_spis[i].bus_name); + hpm_spis[i].rxdma_xfer_done_sem = rt_sem_create(sem_name, 0, RT_IPC_FLAG_PRIO); + if (hpm_spis[i].rxdma_xfer_done_sem == RT_NULL) + { + ret = RT_ENOMEM; + break; + } + + rt_sprintf(sem_name, "%s_tds", hpm_spis[i].bus_name); + hpm_spis[i].txdma_xfer_done_sem = rt_sem_create(sem_name, 0, RT_IPC_FLAG_PRIO); + if (hpm_spis[i].txdma_xfer_done_sem == RT_NULL) + { + ret = RT_ENOMEM; + break; + } } return ret; diff --git a/bsp/hpmicro/libraries/drivers/drv_uart.c b/bsp/hpmicro/libraries/drivers/drv_uart.c index 3889ee253d8..6e57d117783 100644 --- a/bsp/hpmicro/libraries/drivers/drv_uart.c +++ b/bsp/hpmicro/libraries/drivers/drv_uart.c @@ -16,6 +16,7 @@ #include "hpm_uart_drv.h" #include "hpm_sysctl_drv.h" + #ifdef RT_USING_SERIAL #define UART_ROOT_CLK_FREQ BOARD_APP_UART_SRC_FREQ @@ -350,15 +351,8 @@ static void hpm_uart_isr(struct rt_serial_device *serial) uart = (struct hpm_uart *)serial->parent.user_data; RT_ASSERT(uart != RT_NULL); - - /* enter interrupt */ - rt_interrupt_enter(); - /* UART in mode Receiver */ rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); - - /* leave interrupt */ - rt_interrupt_leave(); } diff --git a/bsp/hpmicro/libraries/drivers/drv_uart.h b/bsp/hpmicro/libraries/drivers/drv_uart.h index b316d47ea40..4c4a67db821 100644 --- a/bsp/hpmicro/libraries/drivers/drv_uart.h +++ b/bsp/hpmicro/libraries/drivers/drv_uart.h @@ -11,4 +11,4 @@ int rt_hw_uart_init(void); -#endif /* DRV_UART_H */ +#endif /* DRV_UART_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/drivers/drv_uart_v2.c b/bsp/hpmicro/libraries/drivers/drv_uart_v2.c index eceafb8d0e1..b1c831834dd 100644 --- a/bsp/hpmicro/libraries/drivers/drv_uart_v2.c +++ b/bsp/hpmicro/libraries/drivers/drv_uart_v2.c @@ -18,11 +18,10 @@ #include "hpm_uart_drv.h" #include "hpm_sysctl_drv.h" #include "hpm_l1c_drv.h" -#include "hpm_dma_drv.h" -#include "hpm_dmamux_drv.h" -#include "hpm_dma_manager.h" +#include "hpm_dma_mgr.h" #include "hpm_soc.h" + #ifdef RT_USING_SERIAL_V2 #ifdef RT_SERIAL_USING_DMA @@ -31,7 +30,7 @@ typedef struct dma_channel { struct rt_serial_device *serial; - hpm_dma_resource_t resource; + dma_resource_t resource; void (*tranfer_done)(struct rt_serial_device *serial); void (*tranfer_abort)(struct rt_serial_device *serial); void (*tranfer_error)(struct rt_serial_device *serial); @@ -39,6 +38,7 @@ typedef struct dma_channel { //static struct dma_channel dma_channels[DMA_SOC_CHANNEL_NUM]; static int hpm_uart_dma_config(struct rt_serial_device *serial, void *arg); +static void hpm_uart_receive_dma_next(struct rt_serial_device *serial); #endif #define UART_ROOT_CLK_FREQ BOARD_APP_UART_SRC_FREQ @@ -56,7 +56,7 @@ struct hpm_uart { hpm_dma_channel_handle_t rx_chn_ctx; bool tx_resource_allocated; bool rx_resource_allocated; -#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) && defined(RT_SERIAL_USING_DMA) +#if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1) && defined(RT_SERIAL_USING_DMA) ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t rx_idle_tmp_buffer[1024]; #endif #endif @@ -500,7 +500,7 @@ enum #endif #if defined(BSP_USING_UART5) - HPM_UART15_INDEX, + HPM_UART5_INDEX, #endif #if defined(BSP_USING_UART6) @@ -516,7 +516,7 @@ enum #endif #if defined(BSP_USING_UART9) - HPM_UART10_INDEX, + HPM_UART9_INDEX, #endif #if defined(BSP_USING_UART10) @@ -546,32 +546,36 @@ enum #if defined(RT_SERIAL_USING_DMA) -static void uart_dma_callback(DMA_Type *base, uint32_t channel, void *user_data, uint32_t int_stat) +static void uart_dma_tc_callback(DMA_Type *base, uint32_t channel, void *user_data) { hpm_dma_channel_handle_t *dma_handle = (hpm_dma_channel_handle_t*)user_data; if ((dma_handle->resource.base != base) || (dma_handle->resource.channel != channel)) { return; } + dma_handle->tranfer_done(dma_handle->serial); +} - if (IS_HPM_BITMASK_SET(int_stat, DMA_CHANNEL_STATUS_TC) && (dma_handle->tranfer_done != NULL)) - { - dma_handle->tranfer_done(dma_handle->serial); - } - - if (IS_HPM_BITMASK_SET(int_stat, DMA_CHANNEL_STATUS_ABORT) && (dma_handle->tranfer_abort != NULL)) +static void uart_dma_abort_callback(DMA_Type *base, uint32_t channel, void *user_data) +{ + hpm_dma_channel_handle_t *dma_handle = (hpm_dma_channel_handle_t*)user_data; + if ((dma_handle->resource.base != base) || (dma_handle->resource.channel != channel)) { - dma_handle->tranfer_abort(dma_handle->serial); + return; } + dma_handle->tranfer_abort(dma_handle->serial); +} - if (IS_HPM_BITMASK_SET(int_stat, DMA_CHANNEL_STATUS_ERROR) && (dma_handle->tranfer_error != NULL)) +static void uart_dma_error_callback(DMA_Type *base, uint32_t channel, void *user_data) +{ + hpm_dma_channel_handle_t *dma_handle = (hpm_dma_channel_handle_t*)user_data; + if ((dma_handle->resource.base != base) || (dma_handle->resource.channel != channel)) { - dma_handle->tranfer_error(dma_handle->serial); + return; } + dma_handle->tranfer_error(dma_handle->serial); } - - static void uart_tx_done(struct rt_serial_device *serial) { rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE); @@ -581,11 +585,11 @@ static void uart_rx_done(struct rt_serial_device *serial) { struct rt_serial_rx_fifo *rx_fifo; rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; - #if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) && defined(RT_SERIAL_USING_DMA) + #if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1) && defined(RT_SERIAL_USING_DMA) uint32_t uart_recv_data_count = 0; struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data; uint32_t rx_idle_tmp_buffer_size = sizeof(uart->rx_idle_tmp_buffer); - uart_recv_data_count = rx_idle_tmp_buffer_size - dma_get_residue_transfer_size(uart->rx_chn_ctx.resource.base, uart->rx_chn_ctx.resource.channel); + uart_recv_data_count = rx_idle_tmp_buffer_size - dma_get_remaining_transfer_size(uart->rx_chn_ctx.resource.base, uart->rx_chn_ctx.resource.channel); if (l1c_dc_is_enabled()) { uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)uart->rx_idle_tmp_buffer); uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP((uint32_t)uart->rx_idle_tmp_buffer + rx_idle_tmp_buffer_size); @@ -604,7 +608,7 @@ static void uart_rx_done(struct rt_serial_device *serial) rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (serial->config.rx_bufsz << 8)); #endif /* prepare for next read */ - hpm_uart_dma_config(serial, (void *)RT_DEVICE_FLAG_DMA_RX); + hpm_uart_receive_dma_next(serial); } #endif /* RT_SERIAL_USING_DMA */ @@ -628,10 +632,7 @@ static void hpm_uart_isr(struct rt_serial_device *serial) struct rt_serial_rx_fifo *rx_fifo; rx_fifo = (struct rt_serial_rx_fifo *) serial->serial_rx; - /* enter interrupt */ - rt_interrupt_enter(); stat = uart_get_status(uart->uart_base); - enabled_irq = uart_get_enabled_irq(uart->uart_base); irq_id = uart_get_irq_id(uart->uart_base); if (irq_id == uart_intr_id_rx_data_avail) { @@ -654,7 +655,7 @@ static void hpm_uart_isr(struct rt_serial_device *serial) rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); } - if ((enabled_irq & uart_intr_tx_slot_avail) && (stat & uart_stat_tx_slot_avail)) { + if ((irq_id & uart_intr_tx_slot_avail) && (stat & uart_stat_tx_slot_avail)) { /* UART in mode Transmitter */ struct rt_serial_tx_fifo *tx_fifo; tx_fifo = (struct rt_serial_tx_fifo *) serial->serial_tx; @@ -664,27 +665,24 @@ static void hpm_uart_isr(struct rt_serial_device *serial) uart_disable_irq(uart->uart_base, uart_intr_tx_slot_avail); fifo_size = uart_get_fifo_size(uart->uart_base); ringbuffer_data_len = rt_ringbuffer_data_len(&tx_fifo->rb); - tx_size = (ringbuffer_data_len > fifo_size) ? fifo_size : ringbuffer_data_len; - for (uint32_t i = 0; i < tx_size; i++) { - rt_ringbuffer_getchar(&tx_fifo->rb, &put_char); - uart_write_byte(uart->uart_base, put_char); - } - ringbuffer_data_len = rt_ringbuffer_data_len(&tx_fifo->rb);; - if (ringbuffer_data_len) { - uart_enable_irq(uart->uart_base, uart_intr_tx_slot_avail); - } else { + if (ringbuffer_data_len <= 0) { rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE); + } else { + tx_size = (ringbuffer_data_len > fifo_size) ? fifo_size : ringbuffer_data_len; + for (uint32_t i = 0; i < tx_size; i++) { + rt_ringbuffer_getchar(&tx_fifo->rb, &put_char); + uart_write_byte(uart->uart_base, put_char); + } + uart_enable_irq(uart->uart_base, uart_intr_tx_slot_avail); } } - #if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) && defined(RT_SERIAL_USING_DMA) + #if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1) && defined(RT_SERIAL_USING_DMA) if (uart_is_rxline_idle(uart->uart_base)) { uart_rx_done(serial); uart_clear_rxline_idle_flag(uart->uart_base); uart_flush(uart->uart_base); } #endif - /* leave interrupt */ - rt_interrupt_leave(); } @@ -715,11 +713,11 @@ static rt_err_t hpm_uart_configure(struct rt_serial_device *serial, struct seria if (uart->dma_flags & RT_DEVICE_FLAG_DMA_RX) { uart_config.rx_fifo_level = uart_rx_fifo_trg_not_empty; } -#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) +#if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1) uart_config.rxidle_config.detect_enable = true; uart_config.rxidle_config.detect_irq_enable = true; uart_config.rxidle_config.idle_cond = uart_rxline_idle_cond_rxline_logic_one; - uart_config.rxidle_config.threshold = 10U; /* 10bit */ + uart_config.rxidle_config.threshold = 16U; /* 10bit */ #endif } @@ -737,12 +735,14 @@ hpm_stat_t hpm_uart_dma_rx_init(struct hpm_uart *uart_ctx) hpm_stat_t status = status_fail; if (!uart_ctx->rx_resource_allocated) { - status = dma_manager_request_resource(&uart_ctx->rx_chn_ctx.resource); + status = dma_mgr_request_resource(&uart_ctx->rx_chn_ctx.resource); if (status == status_success) { uart_ctx->dma_flags |= RT_DEVICE_FLAG_DMA_RX; uart_ctx->rx_resource_allocated = true; - dma_manager_install_interrupt_callback(&uart_ctx->rx_chn_ctx.resource, uart_dma_callback, &uart_ctx->rx_chn_ctx); + dma_mgr_install_chn_tc_callback(&uart_ctx->rx_chn_ctx.resource, uart_dma_tc_callback, &uart_ctx->rx_chn_ctx); + dma_mgr_install_chn_abort_callback(&uart_ctx->rx_chn_ctx.resource, uart_dma_abort_callback, &uart_ctx->rx_chn_ctx); + dma_mgr_install_chn_error_callback(&uart_ctx->rx_chn_ctx.resource, uart_dma_error_callback, &uart_ctx->rx_chn_ctx); } } return status; @@ -753,12 +753,14 @@ hpm_stat_t hpm_uart_dma_tx_init(struct hpm_uart *uart_ctx) hpm_stat_t status = status_fail; if (!uart_ctx->tx_resource_allocated) { - status = dma_manager_request_resource(&uart_ctx->tx_chn_ctx.resource); + status = dma_mgr_request_resource(&uart_ctx->tx_chn_ctx.resource); if (status == status_success) { uart_ctx->dma_flags |= RT_DEVICE_FLAG_DMA_TX; uart_ctx->tx_resource_allocated = true; - dma_manager_install_interrupt_callback(&uart_ctx->tx_chn_ctx.resource, uart_dma_callback, &uart_ctx->tx_chn_ctx); + dma_mgr_install_chn_tc_callback(&uart_ctx->tx_chn_ctx.resource, uart_dma_tc_callback, &uart_ctx->tx_chn_ctx); + dma_mgr_install_chn_abort_callback(&uart_ctx->tx_chn_ctx.resource, uart_dma_abort_callback, &uart_ctx->tx_chn_ctx); + dma_mgr_install_chn_error_callback(&uart_ctx->tx_chn_ctx.resource, uart_dma_error_callback, &uart_ctx->tx_chn_ctx); } } return status; @@ -768,59 +770,82 @@ static int hpm_uart_dma_config(struct rt_serial_device *serial, void *arg) { rt_ubase_t ctrl_arg = (rt_ubase_t) arg; struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data; - dma_handshake_config_t config; struct rt_serial_rx_fifo *rx_fifo; - + dma_mgr_chn_conf_t chg_config; + dma_mgr_get_default_chn_config(&chg_config); if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) { rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; - config.ch_index = uart->rx_chn_ctx.resource.channel; -#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) - config.dst = (uint32_t)uart->rx_idle_tmp_buffer; -#else - config.dst = (uint32_t) rx_fifo->rb.buffer_ptr; -#endif - - config.dst_fixed = false; - config.src = (uint32_t)&(uart->uart_base->RBR); - config.src_fixed = true; - config.data_width = DMA_TRANSFER_WIDTH_BYTE; -#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) - config.size_in_byte = sizeof(uart->rx_idle_tmp_buffer); + chg_config.dst_addr_ctrl = DMA_MGR_ADDRESS_CONTROL_INCREMENT; + chg_config.dst_mode = DMA_MGR_HANDSHAKE_MODE_NORMAL; + chg_config.dst_width = DMA_TRANSFER_WIDTH_BYTE; + chg_config.en_dmamux = true; + chg_config.dmamux_src = uart->rx_dma_mux; + chg_config.src_addr = (uint32_t)&(uart->uart_base->RBR); + chg_config.src_addr_ctrl = DMA_MGR_ADDRESS_CONTROL_FIXED; + chg_config.src_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; + chg_config.src_width = DMA_TRANSFER_WIDTH_BYTE; + +#if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1) + chg_config.dst_addr = (uint32_t)uart->rx_idle_tmp_buffer; + chg_config.size_in_byte = sizeof(uart->rx_idle_tmp_buffer); #else - config.size_in_byte = serial->config.rx_bufsz; + chg_config.dst_addr = (uint32_t)rx_fifo->rb.buffer_ptr; + chg_config.size_in_byte = serial->config.rx_bufsz; #endif - if (status_success != dma_setup_handshake(uart->rx_chn_ctx.resource.base, &config, true)) { - return RT_ERROR; + if (status_success != dma_mgr_setup_channel(&uart->rx_chn_ctx.resource, &chg_config)) { + return -RT_ERROR; } - uint32_t mux = DMA_SOC_CHN_TO_DMAMUX_CHN(uart->rx_chn_ctx.resource.base, uart->rx_dma_mux); - dmamux_config(BOARD_UART_DMAMUX, uart->rx_chn_ctx.resource.channel, mux, true); - #if !defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) || (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 0) + dma_mgr_enable_channel(&uart->rx_chn_ctx.resource); + dma_mgr_enable_chn_irq(&uart->rx_chn_ctx.resource, DMA_MGR_INTERRUPT_MASK_TC); + dma_mgr_enable_dma_irq_with_priority(&uart->rx_chn_ctx.resource, 1); +#if !defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) || (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 0) hpm_uart_dma_register_channel(serial, false, uart_rx_done, RT_NULL, RT_NULL); - intc_m_enable_irq(uart->rx_chn_ctx.resource.irq_num); #else intc_m_enable_irq_with_priority(uart->irq_num, 1); #endif } else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) { - uint32_t mux = DMA_SOC_CHN_TO_DMAMUX_CHN(uart->tx_chn_ctx.resource.base, uart->tx_dma_mux); - dmamux_config(BOARD_UART_DMAMUX, uart->tx_chn_ctx.resource.channel, mux, true); - intc_m_enable_irq(uart->tx_chn_ctx.resource.irq_num); + chg_config.src_addr_ctrl = DMA_MGR_ADDRESS_CONTROL_INCREMENT; + chg_config.src_mode = DMA_MGR_HANDSHAKE_MODE_NORMAL; + chg_config.src_width = DMA_TRANSFER_WIDTH_BYTE; + chg_config.dst_addr = (uint32_t)&uart->uart_base->THR; + chg_config.dst_addr_ctrl = DMA_MGR_ADDRESS_CONTROL_FIXED; + chg_config.dst_mode = DMA_MGR_HANDSHAKE_MODE_HANDSHAKE; + chg_config.dst_width = DMA_TRANSFER_WIDTH_BYTE; + chg_config.en_dmamux = true; + chg_config.dmamux_src = uart->tx_dma_mux; + if (status_success != dma_mgr_setup_channel(&uart->tx_chn_ctx.resource, &chg_config)) { + return -RT_ERROR; + } + dma_mgr_enable_chn_irq(&uart->tx_chn_ctx.resource, DMA_MGR_INTERRUPT_MASK_TC); + dma_mgr_enable_dma_irq_with_priority(&uart->tx_chn_ctx.resource, 1); } return RT_EOK; } -static void hpm_uart_transmit_dma(DMA_Type *dma, uint32_t ch_num, UART_Type *uart, uint8_t *src, uint32_t size) +static void hpm_uart_receive_dma_next(struct rt_serial_device *serial) { - rt_base_t align = 0; - dma_handshake_config_t config; - - config.ch_index = ch_num; - config.dst = (uint32_t)&uart->THR; - config.dst_fixed = true; - config.src = (uint32_t) src; - config.src_fixed = false; - config.size_in_byte = size; - config.data_width = DMA_TRANSFER_WIDTH_BYTE; - dma_setup_handshake(dma, &config, true); + uint32_t buf_addr; + uint32_t buf_size; + struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data; + struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; +#if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1) + buf_addr = (uint32_t)uart->rx_idle_tmp_buffer; + buf_size = sizeof(uart->rx_idle_tmp_buffer); +#else + buf_addr = (uint32_t)rx_fifo->rb.buffer_ptr; + buf_size = serial->config.rx_bufsz; +#endif + dma_mgr_set_chn_dst_addr(&uart->rx_chn_ctx.resource, buf_addr); + dma_mgr_set_chn_transize(&uart->rx_chn_ctx.resource, buf_size); + dma_mgr_enable_channel(&uart->rx_chn_ctx.resource); +} + +static void hpm_uart_transmit_dma(struct rt_serial_device *serial, uint8_t *src, uint32_t size) +{ + struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data; + dma_mgr_set_chn_src_addr(&uart->tx_chn_ctx.resource, (uint32_t)src); + dma_mgr_set_chn_transize(&uart->tx_chn_ctx.resource, size); + dma_mgr_enable_channel(&uart->tx_chn_ctx.resource); } #endif /* RT_SERIAL_USING_DMA */ @@ -876,10 +901,10 @@ static rt_err_t hpm_uart_control(struct rt_serial_device *serial, int cmd, void } #ifdef RT_SERIAL_USING_DMA else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) { - dma_manager_disable_channel_interrupt(&uart->tx_chn_ctx.resource, DMA_INTERRUPT_MASK_ALL); + dma_mgr_disable_chn_irq(&uart->tx_chn_ctx.resource, DMA_INTERRUPT_MASK_ALL); dma_abort_channel(uart->tx_chn_ctx.resource.base, uart->tx_chn_ctx.resource.channel); } else if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) { - dma_manager_disable_channel_interrupt(&uart->rx_chn_ctx.resource, DMA_INTERRUPT_MASK_ALL); + dma_mgr_disable_chn_irq(&uart->rx_chn_ctx.resource, DMA_INTERRUPT_MASK_ALL); dma_abort_channel(uart->rx_chn_ctx.resource.base, uart->rx_chn_ctx.resource.channel); } #endif @@ -889,7 +914,7 @@ static rt_err_t hpm_uart_control(struct rt_serial_device *serial, int cmd, void if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) { /* enable rx irq */ uart_enable_irq(uart->uart_base, uart_intr_rx_data_avail_or_timeout); - intc_m_enable_irq_with_priority(uart->irq_num, 1); + intc_m_enable_irq_with_priority(uart->irq_num, 2); } else if (ctrl_arg == RT_DEVICE_FLAG_INT_TX) { /* enable tx irq */ uart_enable_irq(uart->uart_base, uart_intr_tx_slot_avail); @@ -999,7 +1024,7 @@ static rt_ssize_t hpm_uart_transmit(struct rt_serial_device *serial, uint32_t aligned_size = aligned_end - aligned_start; l1c_dc_flush(aligned_start, aligned_size); } - hpm_uart_transmit_dma(uart->tx_chn_ctx.resource.base, uart->tx_chn_ctx.resource.channel, uart->uart_base, buf, size); + hpm_uart_transmit_dma(serial, buf, size); return size; } else { #else @@ -1007,7 +1032,7 @@ static rt_ssize_t hpm_uart_transmit(struct rt_serial_device *serial, #endif if (size > 0) { - if (uart_check_status(uart->uart_base, uart_stat_transmitter_empty)) { + if (uart_check_status(uart->uart_base, uart_stat_tx_slot_avail)) { uart_disable_irq(uart->uart_base, uart_intr_tx_slot_avail); fifo_size = uart_get_fifo_size(uart->uart_base); ringbuffer_data_len = rt_ringbuffer_data_len(&tx_fifo->rb); @@ -1016,11 +1041,7 @@ static rt_ssize_t hpm_uart_transmit(struct rt_serial_device *serial, rt_ringbuffer_getchar(&tx_fifo->rb, &ch); uart_write_byte(uart->uart_base, ch); } - if (rt_ringbuffer_data_len(&tx_fifo->rb)) { - uart_enable_irq(uart->uart_base, uart_intr_tx_slot_avail); - } else { - rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE); - } + uart_enable_irq(uart->uart_base, uart_intr_tx_slot_avail); } } } @@ -1216,7 +1237,7 @@ static int hpm_uart_config(void) return -RT_ERROR; } #endif //BSP_UART7_RX_USING_DMA -#ifdef BSP_UART0_TX_USING_DMA +#ifdef BSP_UART7_TX_USING_DMA status = hpm_uart_dma_tx_init(&uarts[HPM_UART7_INDEX]); if (status != status_success) { @@ -1239,7 +1260,7 @@ static int hpm_uart_config(void) return -RT_ERROR; } #endif //BSP_UART8_RX_USING_DMA -#ifdef BSP_UART0_TX_USING_DMA +#ifdef BSP_UART8_TX_USING_DMA status = hpm_uart_dma_tx_init(&uarts[HPM_UART8_INDEX]); if (status != status_success) { @@ -1429,7 +1450,7 @@ int rt_hw_uart_init(void) } if (RT_EOK != hpm_uart_config()) { - return RT_ERROR; + return -RT_ERROR; } for (uint32_t i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++) { diff --git a/bsp/hpmicro/libraries/drivers/drv_wdt.c b/bsp/hpmicro/libraries/drivers/drv_wdt.c index 63540a886d5..d594dbc4493 100644 --- a/bsp/hpmicro/libraries/drivers/drv_wdt.c +++ b/bsp/hpmicro/libraries/drivers/drv_wdt.c @@ -14,6 +14,7 @@ #include "hpm_sysctl_drv.h" + #ifdef BSP_USING_WDG @@ -49,7 +50,7 @@ void wdog0_isr(void) { hpm_wdog_isr(&wdog0); } -SDK_DECLARE_EXT_ISR_M(IRQn_WDOG0, wdog0_isr) +SDK_DECLARE_EXT_ISR_M(IRQn_WDG0, wdog0_isr) #endif #if defined(BSP_USING_WDG1) @@ -58,7 +59,7 @@ void wdog1_isr(void) { hpm_wdog_isr(&wdog1); } -SDK_DECLARE_EXT_ISR_M(IRQn_WDOG1, wdog1_isr) +SDK_DECLARE_EXT_ISR_M(IRQn_WDG1, wdog1_isr) #endif #if defined(BSP_USING_WDG2) @@ -67,7 +68,7 @@ void wdog2_isr(void) { hpm_wdog_isr(&wdog2); } -SDK_DECLARE_EXT_ISR_M(IRQn_WDOG2, wdog2_isr) +SDK_DECLARE_EXT_ISR_M(IRQn_WDG2, wdog2_isr) #endif #if defined(BSP_USING_WDG3) @@ -76,7 +77,7 @@ void wdog3_isr(void) { hpm_wdog_isr(&wdog3); } -SDK_DECLARE_EXT_ISR_M(IRQn_WDOG3, wdog3_isr) +SDK_DECLARE_EXT_ISR_M(IRQn_WDG3, wdog3_isr) #endif static hpm_wdog_t wdogs[] = { @@ -246,4 +247,4 @@ int rt_hw_wdt_init(void) } INIT_BOARD_EXPORT(rt_hw_wdt_init); -#endif /* RT_USING_WDT */ +#endif /* RT_USING_WDT */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/drivers/drv_wdt.h b/bsp/hpmicro/libraries/drivers/drv_wdt.h index 100ffc27dd8..4c69255af0f 100644 --- a/bsp/hpmicro/libraries/drivers/drv_wdt.h +++ b/bsp/hpmicro/libraries/drivers/drv_wdt.h @@ -11,4 +11,4 @@ int rt_hw_wdt_init(void); -#endif +#endif \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/CHANGELOG.md b/bsp/hpmicro/libraries/hpm_sdk/CHANGELOG.md index a9c9b0be666..6c383ae0343 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/CHANGELOG.md +++ b/bsp/hpmicro/libraries/hpm_sdk/CHANGELOG.md @@ -1,5 +1,588 @@ # Change Log +## [1.5.0] - 2024-02-29: + +Main changes since 1.4.0 + +Tested Segger Embedded Studio Version: 7.32a +Tested IAR Embedded Workbench for RISC-V Version: 3.20.1 + +### Known Issue: + - some IAR projects does not work properly when optimization level is increased + +### Changed: + - soc: iomux: update macro prefix in pmic_iomux and batt_iomux. + - soc: feature: change usb endpoint max number from 8 to 16 + - soc: correct svd files and add subpart module list + - drivers: usb: change usb_phy_get_line_state() to external function + - drivers: qeiv2: update filter length setting + - drivers: adc12/adc16: add sanity check for sample cycle + - drivers: femc: add delay_cell_disable config option + - drivers: i2s: change fifo threshold parameter. + - drivers: i2c: replace and use the macro definition of hpm_soc_ip_feature. + - drivers: uart: supplementary description of uart_check_status API. + - components: enet_phy: lan8720/rtl8201/rtl8211: unify the default config with type bool + - components: enet_phy: remove unused included header file + - components: enet_phy: rtl8201/rtl8211: update register description + - components: dma_mgr: change isr handler from static to public + - middleware: tinyusb: host: use echi drivers + - middleware: tinyusb: rename CFG_TUSB_HOST_DEVICE_MAX to CFG_TUH_DEVICE_MAX + - middleware: tinyusb: update to v0.16 + - middleware: rtthread-nano: use soc reset_handler and define MAIN_ENTRY as entry + - middleware: fatfs: tinyusb: adapter to tinyusb update + - middleware: threadx: use TX_TIMER_TICKS_PER_SECOND to config work ticks + - middleware: threadx: use samples tx_user.h + - middleware: uC/OS-III: enable sw interrupt in OSCtxSw/OSIntCtxSw + - middleware: ucos: ports: Added IAR portable layer for ucos. + - middleware: cherryusb/azure_rtos: add defined __ICCRISCV__ for iar + - middleware: hpm_math: simplify libdsp path. + - middleware: cherryusb: update to v1.1.0 + - middleware: rtthread-nano:halt cpu when exception occur. + - middleware: hpm_math: simplify libnn path. + - middleware: threadx: move frequently called function to ram. + - middleware: tinyusb: change endpoint number from 8 to 16 + - middleware: usbx: change endpoint number from 8 to 16 + - middleware: cherryusb: msc device: update to support multi lun and deinit + - middleware: eclipse_threadx: update license + - middleware: fatfs: tinyusb: add osal_task_delay() when use rtos wait + - middleware: tinyusb: update CMakeLists.txt and delete custom osal_task_delay() + - middleware: tinyusb: add debounce in port change isr + - samples: erpc: add middleware src use middleware CMakeLists.txt + - samples: multicore: core1: use board_init_core1() API + - samples: multicore: coremark: delete custom reset_handler and use app_main as MAIN_ENTRY + - samples: tinyusb: update samples to adapter tinyusb v0.16 + - samples: usbx: host: delete unused hpm_usb_host.h + - samples: usb: delete CONFIG_USB_HOST set + - samples: lvgl_coremark: disable freqswitch_btn when coremark running + - samples: mono: move to driver directory. + - samples: freertos: change configMAX_PRIORITIES from 7 to 32 + - samples: rtthread: delete unused macro RT_THREAD_PRIORITY_32 + - samples: cherryusb: usbnet: decrease rtos stack config size + - samples: lwip: all: unify logs about IP information + - samples: lwip: lwip_https_server: remove an unused file + - samples: lwip: all: update DHCP progress logic + - samples: lwip: common: remove s_pxNetIf + - samples: lwip: adjust the directories of netconf.c/netcof.h + - samples: lwip: common: optimize speed for getting IP from DHCP server + - samples: lwip: rename common_lwip.c to common.c + - samples: lwip: common: adjust the call logic of netif_set_up/netif_set_down + - samples: lwip: common: change the time of invoking netif_user_notification + - samples: lwip: common: rename user_notification to netif_user_notification + - samples: lwip: adjust directory structures to be compatible with single and multiple network ports + - samples: use generate_ide_projects for new samples + - samples: cherryusb: device: cdc acm: reorganize directory structure + - samplse: gptmr: t_shape_accel_decel: modify the source address mode of DMA. + - samples: cherryusb: device: change readbuf size from 2048 to CDC_MAX_MPS + - samples: drivers: femc: update sdram dqs config + - samples: update app.yaml to use ip_feature + - samples: drivers: uart: change to app uart + - samples: audio_codec: update wm8960 I2S protocol. + - samples: drivers: cam: change cam sample to cam_dvp sample. + - samples: usbx: device: msc: decrease ram disk size to 16KB + - samples: cherryusb: msc device: update to support multi lun + - samples: driver: uart_lin: support LIN transceiver on board. + - samples: adc: temp: rename temp to adc16_temperature + - samples: bldc block: Compatible with both hall and qeiv2 peripherals. + - samples: motor_ctrl: Modify the value of pwm reload. + - samples: lwip: common: single/multiple: update the size passed into sys_mbox_new() + - samples: lwip: common: single/multiple: replace enet_get_link_status with netif_is_link_up + - samples: lwip: lwip_https_server: remove unused header file + - samples: lwip: rename macro TCP_XXX_PORT + - samples: lwip: add cmake flag for netconn/socket api + - samples: decode_wav: sd_fafts: update sd_choose_music. + - samples: power_mode_switch: maintain xpi0 clock on switching preset + - samples: dhrystone Change the optmization level to O3. + - samples: tinyusb: hid_generic_inout: delete redundant image + - samples: power_mode_switch: hpm67/hpm63: preserve femc clock at wait/stop mode + - samples: erpc: core1: use optimization -os + - samples: update uart_tamagawa to use software trig if TRGM not exist. + - samples: eeprom_emulation: reduce management area + - samples: sdxc: use block_size instead of 512 + - samples: erpc: add -fno-exceptions compile option + - samples: tinyusb: disable debug log print + - boards: hpm5300evk and hpm6800evk: add delay after USB_PWR Pin init for power stable + - boards: hpm6750evkmini: modify gptmr pins. + - boards: hpm6200evk: modify gptmr pins. + - boards: hpm6200evk: modify the i2c pins. + - boards: hpm6750xxx: update sdram dqs config + - boards: hpm6800evk:pinmux Increase drive strength for sdxc pins + - boards: iomux: update macro prefix for pmic_iomux and batt_iomux. + - boards: rename board feature + - boards: update BOARD_APP_UART definition + - boards: rename console definitions + - boards: hpm5301evklite: update uart clock in board.c. + - boards: hpm6750evkmini: change BOARD_GPTMR_PWM_DMA_SRC definition. + - docs: samples: use glob in high level readme. + - docs: update top level readme. + - docs: netxduo: update sntp readme. + - docs: threadx: update threadx hello readme. + - docs: lwip: align pictures to the left + - docs: pip: add cmake doc dependency + - docs: add changelog to sphnix-doc. + - scripts: ses: generate asm after build by default. + - scripts: update linked project path logic. + - scripts: check_board_cap.py: check ip feature's availability + - cmake: remove CMP0116 setting. + - cmake&scripts: clarify the error caused by core1 compiling failure. + - scripts: ses/iar: use relpath in project file + +### Added: + - soc: hpm6360/hpm6750/hpm6800: add MAC-related definitions in OTP section + - soc: reset: add MAIN_ENTRY macro to custom define main entry + - soc: add hpm6850 and hpm6830 part. + - soc: soc_modules.list: add tamper drivers + - soc: Add IAR toolchain support. + - soc: add ip feature to soc_modules.list + - soc: add hpm_soc_ip_feature.h + - soc: driver: ppor: add reset hold operation APIs + - soc: clock_driver add the clock_get_divider API. + - soc: sysctl: add apis to control clock preservation + - soc: toolchains: gcc: ram linker: add ILM last address overflow check + - drivers: mcan Add timeout counter support. + - drivers: tamper: add tamper driver + - drivers: cam: add cam_update_buffer2 API + - drivers: opamp: Add user configuration code. + - drivers: lcdc: add stride for layer config. + - drivers: pdma: add pdma_blit_ex. + - drivers:pllctl add out-of-bound check in pllctl driver. + - components:uart_lin: add hpm_uart_lin_send_wakeup() API + - components: enet_phy: add LAN8720 driver + - components: enet_phy: add definition of enet_phy_link_status_t + - middleware: cherryusb: host: add dual port support + - middleware: cmsis_os2: adapter to rtthread wrapper + - middleware: cmsis_os2: update freertos files + - middleware: cmsis_os2: adapter to threadx wrapper + - middleware: cmsis_os2: adapter to ucOS-III wrapper + - middleware: hpm_sdmmc Add eMMC config partition API. + - middleware: cherryusb Add IAR toolchain support + - middleware: erpc Fix IAR RISC-V support issue + - middleware: tflm: add IAR riscv support in flatbuffer + - middleware: FreeRTOS: portable:Added IAR portable layer. + - middleware: segger_rtt Added EWRISCV support + - middleware: hpm_math Add nds_dsp library for IAR. + - middleware: lwip: cc: add PACK_STRUCT_XXX definitions for IAR platform + - middleware: uC/OS-III: enable plicsw in IAR asm code + - middleware: add tinyengine + - middleware: threadx: add support for gptmr. + - middleware: threadx: add profile support. + - middleware: add agile_modbus. + - middleware: add cherryrb. + - middleware: cherryusb Add missing swap32/swap16 implementation. + - middleware: hpm_mclv2: add block type drive motors + - middleware: cherryusb: fix usbh_core ep0 buffer index + - boards: hpm6200xxx and hpm6750xxx: add board_init_core1() API + - boards: add tamper feature and pins init + - boards: hpm5300evk: add board_init_console() declaration in board.h + - boards: hpm6750evk/hpm6750evk2: add board_dual_usb feature + - boards: openocd: add windows guide to *_all_in_one.cfg + - boards: openocd: soc: add reset_soc proc + - board:add pgpio configuration on hpm5301evklite + - samples: drivers: add mono sample. + - samples: drivers:mcan Add timeout counter sample. + - samples: drivers: tamper: add tamper sample + - samples: cmsis_os2: blinky: add rtthread samples + - samples: cmsis_os2: add msg_queue sample + - samples: cmsis_os2: add mem_pool samples + - samples: cmsis_os2: msg_queue: add ucOS-III support + - samples: cmsis_os2: blinky: add ucOS-III support + - samples: lwip: common: add a task netif_update_link_status + - samples: lwip: add MAC address load from OPT MAC area + - samples: cherryusb: device: cdc acm: add cdc_acm_uart_com sample + - samples: cherryusb: device: add msc sdcard sample + - samples: tinyengine: add person detection. + - samples: rtos: add threadx gptmr sample. + - samples: modbus: tcp: add tcp samples. + - samples: modbus: rtu: add rtu sample. + - samples: add cherryrb sample. + - samples: cherryusb: host: add dual port sample + - samples: cherryusb: device: add dual port sample + - samples: cherryusb: device: add dual lun msc sample + - samples: lwip: ports: rtthread-nano: multiple: add arch-related files + - samples: lwip: ports: freertos: multiple: add arch-related files + - samples: lwip: common: multiple: osal: add osTaskFunction definition + - samples: lwip: add a lwip_tcpecho_multi_ports_rtthread-nano sample + - samples: lwip: add a lwip_tcpecho_multi_ports_freertos + - samples: lwip: lwip_tcpecho_xxx: add definitions for task priorities + - samples: lwip: lwip_tcpecho_freertos_socket: newly add + - samples: lwip: lwip_tcpclient: newly add + - samples: lwip: add lwip_tcpclient_freertos_socket + - samples: vglite: add sample of rotate tiger. + - samples: lwip: lwip_tcpclient_freertos_socket: fix failure to run + - samples: lwip: lwip_tcpclient: fix failure to run with some release-related type + - samples: jpeg: jpeg_encode: add debounce for button. + - docs: add cmake doc + - docs: hpm5300evk: add qeiv2 sin/cos pins + - scripts: support sdk project localization. + - cmake: add nds-gcc options to sdk_lib for nds-gcc. + - cmake/scripts: add IAR project generation support + - cmake: add symbols to specify linker for tools. + - cmake: add sdk_*_src_glob. + - cmake: add custom targets for localization. + +### Fixed: + - soc: hpm6750: fix segger linker vectors order + - soc: hpm_interrupt.h Fix compiling warning for DSP related macros + - soc: hpm6750: otp Fix OTP program and read logic + - soc: hpm6880: clock Fix wrong enum value for TSNS clock. + - soc: clock driver: correct the clock name value for pll clocks. + - soc: HPM6280: fix adc/dac clock setting + - soc: ppor: fix ppor clear reset flag and set reset type API error + - soc: HPM6880: fix i2s clock config driver + - drivers: adc12: fix calibration setting error + - drivers: cam: DMASA_FB2 need to be assigned whether FB2 buffer is enable or not. + - drivers:can correct the logic of disabling re-transmission for ptb & stb. + - drivers: qeo: fix driver error + - drivers: i2s: ensure valid BCLK before call software reset. + - drivers: pdma: fixed OUT_PS[] config. + - components: wm8960: invert LRCLK to align with soc I2S. + - middleware: uC/OS-III: fix register t0 unsafe. + - middleware: ptpd: fix netShutdown error in ptpd initialization + - middleware: cmsis_os2: task should call exit interface before exit + - middleware: threadx: fix threadx profile RA register save and restore bug. + - middleware: hpm_mcl: fix divide-by-zero error. refs: hpm_sdk-#1091 + - middleware: cherryusb/tinyusb/usbx: device: fix transfer_len not reset + - middleware: cherryusb/usbx: fix dtd return problem + - middleware: cherryusb/tinyusb/usbx: fix usb device interrupt should be check active status + - middleware: tinyusb: fix ehci cap_reg address error + - middleware: tinyusb: fix hid report id + - middleware: cherryusb: fix usbd_ep_close not reset ep_enable flag + - middleware: cherryusb: fix rndis message length check + - middleware: freertos: fix implementation error in xPortIsInsideInterrupt. + - boards: hpm6200evk: fix tamper pin config + - board: openocd: all_in_one: hpm6800 config file is missed. + - boards: openocd: all_in_one: hpm5300: correct soc config name. + - samples: threadx hello: fix printing errors. + - samples: drivers: ad12/adc16: fix initialization sequence for trigger source, trigger mux and trigger target config + - samples: lwip: lwip_ptp: fix netSend error before link-up + - samples: dma: fix dma uart init position + - samples: drivers:spi:master_trans_large_amound_of_data Fix logic error if SPI support 4GB transfer size + - samples: sdxc: add boundary protection for last 1024 blocks test + - samples: lwip: common: multiple: fix typo of enet_update_dhcp_state() + - samples: lwip: common: single/multiple: fix timeout passed into sys_arch_mbox_fetch() + - samples: e2prom: bugfix: base read fail if run perf firstly .refs:hpm_sdk-#1499 + - samples: modbus: tcp: use volatile to prevent the compiler from optimizing out key variables + - samples: modbus: rtu: fixed failed to run after turning on optimization issue. + - samples: power_mode_switch: hpm68xx: fix ddr access issue for wait/stop mode + - samples: cherryrb: fixed stack overflow issue + - samples: lwip: lwip_tcpecho_multi_ports_ports_rtthread-nano: fix failure to run + - sample: jpeg: jpeg_encode: fix that udisk can't be mounted when first capture. + - cmake: correct board search path symbol for core1. + - cmake: gcc: fix system include path. + - cmake: fix sdk_link_libraries failed to link std lib. + - cmake: EXTAR_LD_FLAGS to be added as ld options. + - docs: lwip_ptp: v1: salve: fix format error + - docs: samples: ppor: change title from sysctl to ppor + - docs: hpm6750evk2: fix table display error + +## [1.4.0] - 2023-12-29: + +Main changes since 1.3.0 + +Tested Segger Embedded Studio Version: 7.32 + +### Changed: + - soc: hpm5301: add hpm5301 + - soc: hpm6880: add hpm6880 + - soc: HPM6750: pcfg: update dcdc dcm mode config + - soc: clock driver: update clock_set_source_divider() and clock_get_source() + - boards: add hpm5301evklite + - boards: add hpm6800evk + - boards: update clock_set_source_divider() to use clk_src_t type param + - boards: hpm6750evkmini: use the same uart port as core1 for some samples. + - drivers: dao: update driver support new feature on hpm6800 + - drivers: adc16: update comment about cal_avg_cfg in calibration + - drivers: qeiv2: change adc trigmux name x to 0 and y to 1 + - drivers: femc: add overflow protect to time config + - drivers: mcan Enlarge the range of CAN_EVENT_ERROR. + - components: serial_nor: add subdirectory in cmakelists + - middleware: cherryusb: update to v0.10.2 + - middleware: cherryusb: rename host and device isr + - middleware: FreeRTOS: xPortIsInsideInterrupt() using CSR_MSCRATCH + - middleware:hpm_sdmmc Enhanced all speed modes support for SD and eMMC. + - middleware: usbx: device: support chain transfer + - samples: cherryusb: host: rndis: integrate dhcp thread into ping thread for host rndis ping and iperf sample + - samples: adc: temp: add isr for temp out of thresholds + - samples: drivers: acmp: optimization for comparing input voltage + - samples: lwip: add DHCP macro definition in CMakeLists.txt + - samples: lwip_ptp: enable DHCP feature in PTP samples + - samples: drivers: qeiv2: update API for adc-qeiv2 pin initialization + - samples: bldc_foc: change adc buffer size from 40 words to 48 words + - samples: remove explicitly c++ standard setting. + - samples: driver: cam: set default cmake build type + - samples: lwip: update to Class C static IP adress + - samples: tinyuf2: remove unnecessary cache ops. + - samples: lwip: lwip_tcpecho_freertos: optimization for API call in a thread-safe way + - samples: lwip: lwip_ptp: v1: slave: update static ip + - samples: lwip: optimize DHCP enable logic + - samples: lwip: opts: adjust the allocation strategy of memory pool + - samples: lwip: lwip_iperf: adjust MEM_SIZE for saving memory consumption + - samples: lwip: lwip_tcpecho_multi_ports: update the second IP with C class + - samples: enet: optimization for PHY selections + - samples: dma: update uart rx circle transfer buffer size + - samples: drivers: sdxc/emmc Correct doc for emmc sample. + - cmake: sdk_link_libraries link libraries for supported tools. + - cmake: add project name for hpm_sdk sub directory. + - cmake: decouple CMAKE_BUILD_TYPE and linker script. + - cmake: ses: remove -Ox from gcc option list. + - cmake: set default c++ standard to c++11. + - Update CONFIG_HAS_xxx to HPMSOC_HAS_xxx. + - segger: enable all warnings. + - segger: release: release optimization level use cmakelist config + - scripts: ses: set intermediate dir in project file. + - docs: remove quick start guide from top level readme + - docs: change doc structure. + +### Added: + - soc: HPM5361: add trgm filter shift length feature + - soc & drivers: hpm5300: add DMAMUX_SOC_WRITEONLY and TRGM_SOC_HAS_DMAMUX_EN features + - drivers: lcb: add lcb driver. + - drivers: sdxc add more APIs for timing and power control. + - drivers: mipi_csi: add mipi csi. + - drivers: cam: add cam_stop_safely API + - components: usb: device: add dtd chain transfer + - components: panel: enable panel component. + - components: camera: ov5640: add mipi interface. + - middleware: rtthread-nano: add v3.1.5 + - middleware: rtthread-nano: add FPU support. + - middleware: tinyusb: device: update to support chain transfer + - middleware: cherryusb: device: update to support chain transfer + - middleware: vglite: add 4.0.49. + - middleware: cherryusb: add USB_OSAL_WAITING_FOREVER for sem and mq use + - middleware: add hpm_mcl_v2 + - middleware: lwip: add ptpd v1 & v2 + - middleware: cmsis_os2: add source files. + - samples: mcl: add step motor. + - samples: lwip: lwip_ptp: v2: support IEEE1588 V2 + - samples: cherryusb: add audio_v2_mic_speaker_rtthread sample + - samples: cherryusb: host: add hid and msc rtthread samples + - samples: cherryusb: host: usbnet: add support ec20 module sample. + - samples: cmsis_os2: add blinky sample. + - samples: driver: mipi_csi: add mipi_csi. + - samples: mcan Support MCAN4-7 loopback testing. + - cmake: support custom output file name. + +### Fixed: + - soc: fix cache maintenance at startup + - soc: hpm53xx Correct exip API tree offset. + - soc: toolchain: missing .fast.* in gnu ld linker script. + - soc: fix tbss and tdata section not initialized. + - soc: sysctl: sysctl_enable_group_resource() should be check LOC_BUSY + - soc: hpm5300 Correct Cache size and Cacheline size. + - boards: hpm6750evkmini Fix the issue that eMMC is still 3.3V even 1.8V is selected. + - boards: hpm5301evklite correct jlink script device number. + - components: camera: power_up is enable by default for ov5640/ov7725. + - docs: samples: drivers: add numberic index. + - drivers/soc: fix build warning + - drivers: i2c: add slave device response judgment for master read/write APIs + - drivers: opamp: fix opamp vssa connect error. + - drivers: pllv2: fix pllctlv2_pll_is_stable() API + - drivers: qeiv2: fix invalid argument check + - drivers: dac: fix the upper limit value setting for DAC_OUTPUT + - drivers: jpeg: fix pixel format index for out buffer. + - drivers: uart: fix not support oversample 32 for rx idle detection on hpm5300 + - middleware:ftafs Fix SD card init crash. + - middleware: mcl: fix path plan error. + - middleware: hpm_sdmmc Fix the issue that IO initialization work unstable on HPM6300. + - middleware: hpm_sdmmc Fix voltage switch setting issue for SD and eMMC. + - middleware: hpm_sdmmc Fix the PWR and VSEL IO initiaization issue. refs:hpm-sdk-#863 + - samples: sei: fix nikon sample crc calc error. + - samples: cherryusb: msc device: add pre-format fat12 file system in u disk + - samples: adcx: replace const with a macro for ADC sample cycle + - samples: tinyusb:fix the usb host pin init. + - samples: motor_ctrl: bldc_littlevgl_foc: program crash. + - samples: qeiv2: uvw: fix uninitialized pointer usage + - samples: cherryusb: fix semaphore give in isr + - samples: drivers: Fix the issue that can error example may block. + - samples: uart_irq: fix unable to limit receive large than buffer size. + - samples: drivers:sdxc:emmc remove infinite loop for emmc initialization. + - samples: drivers: i2s: fix tx underflow during tx start + - samples: lwip: lwip_tcpecho_multiple_ports: fix no echo data when receiving large amounts of data + - samples: mcl: pwm duty set error. + - samples: cherryusb: host: usbnet: fixed when performing a stress test with a large amount of iperf data, will send fai. + - samples: cherryusb: audio_v2_mic_speaker_rtthread: fix mic no voice problem + - samples: jpeg_decode: add delay after usb pins init for waiting power stable + - samples: hfi: hpm6750evk2: fix the motor shake. + - cmake: segger: remove workstation specific path info. + - cmake/soc: fix heap/stack size setting for andes toolchain. + - cmake: ses: correct device name for core1. + +## [1.3.0] - 2023-09-28: + +Main changes since 1.2.0 + +Tested Segger Embedded Studio Version: 7.32 + +### Changed: + - boards: hpm6200evk/hpm6300evk: delete unwanted clock_ahb div set + - boards: hpm6750xxx: switch dcdc work mode to dcm mode + - docs: sdk: boards: hpm6750evk2: add pps pin information + - component: wm8960: support sysclk pre-divider + - components: serial_nor: add serial nor flash. + - openocd: probes: ft2232: remove trst and srst config. + - ip: cam：remove 0x5c MAX_WN_CYCLE register in regs.h + - driver: cam: remove invalid register + - drivers: i2s: update API + - drivers: adc: adc12/adc16: rename adc16_get_busywait to adc16_is_nonblocking_mode + - drivers: adc: adc12/adc16: update adcx_init API + - drivers: pllctrl: update pllctrl drivers + - drivers: spi : add spi enable and disable datamerge + - drivers: spi : add spi_set_address_len API + - drivers: pdgo Add missing APIs + - drivers: uart: update uart rx idle flag process and fifo control + - soc: delete_unnecessary_ppor_reset_bit_field + - soc: hpm_gpiom_soc_drv.h: delete gpiom_gpio_t soc name + - soc: delete DMA_SOC_BUS_NUM Macro + - soc: pcfg: update pcfg SCG_CTRL related drivers + - soc: hpm6750:startup Enable LMM1 clock before access to LMM1 + - soc: gcc ld: add memory used size check + - middleware: cherryusb: update to v0.10.1 + - middleware: guix: demo adapts to 800 * 480 resolution + - middleware: guix: improve demo display performance + - middleware: cherryusb: update for midi descriptor define + - middleware: cherryusb: update for midi + - samples: drivers: adc: adc12/adc16: speed optimization for oneshot reading + - samples: drivers: adc: adc12/adc16： update API call used for nonblocking judgement + - samples: drivers: adc: adc12/adc16: update API call related to blocking setting in oneshot mode + - samples: drivers: adc: adc12/adc16: reduce the input parameters of init_trigger_target function + - samples: drivers: adc: adc12/adc16: update init_oneshot_config + - samples: drivers: adc: adc12/adc16: optimization for clearing interrupt status + - samples: drivers: pwm: Add pwm clock jitter demo + - samples: cherryusb: hid host: separate mouse and keyboard urb + - samples: hrpwm: Add demo for updating hrpwm frequency + - samples: drivers:mcan Add CAN error handling and refined logic. + - samples: mbx: move dualcore mbx sample to multicore folder + - samples: cherryusb: update for v0.10.1 + - samples: motor_ctrl: bldc smc: gcc toolcahin enable fpu. + - samples: lwip: lwip_tcpecho_freertos: optimization in a thread-safety way + - samples: qeo: update qeo abz frequency configuration + - samples: gptmr: add sent_signal sample. + - samples: lwip: lwip_ptp: remove the dependency on pps0 pinout + - samples: dma_manager: update for use dma_mgr_setup_channel() + - samples: drivers: gptmr: pwm_measure: support use dma + - samples: lwip: lwip_httpsrv/lwip_https_server: rename project names for uniform naming + - samples: multicore: lvgl_coremark: delete custom linker files and using andes toolchain + - samples: flash_algo: update device size. + - samples: cherryusb: host: hid: use ep_mps to fill urb + +### Added: + - cmake: ses: support specify custom openocd board cfg file. + - cmake: support specifying minimum sdk version in app.yaml. + - boards: add hpm5300evk + - components: eeprom_emulation: add hpm nor-flash support + - components: eeprom_emulation: add eeprom emulation component + - soc: add APIs for get or set sysctl resource status + - drivers: common: add HPM_ALIGN_DOWN and HPM_ALIGN_UP define + - drivers: adc: ad12/adc16: add adcx_set_blocking_read/adcx_set_nonblocking_read + - drivers: add encoder position driver + - drivers: lcdc: add enable/disable background in alpha blender. + - drivers: usb: add api to set dp/dm pin pulldown resistance + - drivers: spi: add spi_get_rx_fifo_valid_data_size and spi_get_tx_fifo_valid_data_size APIs + - drivers: spi: add directIO function APIs + - drivers: enet: add rx resume API + - drivers: adc16: add resolution setting in adc16_get_default_config API + - drivers:rtc Add rtc_get_timeval API. + - drivers:mcan Add mcan_transmit_via_txfifo_nonblocking API. + - drivers: usb: add usb_hcd_set_power_ctrl_polarity() API + - drivers: plb: add plb drivers + - drivers: linv2: add linv2 driver + - drivers: sei: add sei driver + - drivers: dmav2: add dmav2 driver + - drivers: qeo: add qeo driver + - drivers: qeiv2: add qeiv2 driver + - drivers: mmc: add mmc driver + - drivers: rdc: add rdc driver + - drivers: add opamp driver + - drivers: bgpr: add related APIs for bgpr + - middleware: FreeRTOS: add xPortIsInsideInterrupt() API + - middleware: threadx: add definition automatically when enable traceX + - middleware: freeRTOS: add use gptmr to generate interrupt + - middleware: hpm_mcl: add hfi + - samples: drivers: adc: adc12/adc16: add wdog feature + - samples: add opamp demo + - samples: cherryusb: rndis: host: add iperf sample. + - samples: cherryusb: rndis: host: add ping sample. + - samples: drivers: adc: adc12/adc16: add hw trigger configuration in sequence mode + - samples: eeprom_emulation: add eeprom emulation perf test sample + - samples: eeprom_emulation: add base api demo + - samples: tracex: add demo for traceX usage + - samples: cherryusb: add audio_v1_mic_speaker_midi sample + - samples: cherryusb: add midi device sample + - samples: drivers: sei: add sei samples + - samples: drivers: plb: add plb demo + - samples: drivers: mmc: add mmc demo + - samples: drivers: qeiv2: add qeiv2 demo + - samples: drivers: qeo: add qeo demo + - samples: drivers: dmav2: add dmav2 demo + - samples: drivers: linv2: add linv2 demo + - samples: drivers: rdc: add rdc demo + - samples: drivers: pdgo Add PDGO samples + - samples: drivers: ewdg Add EWDG sample + - samples: lwip: add a lwip_tcpecho_multi_ports sample + - samples: motor_ctrl: add hfi + +### Fixed: + - cmake: fix segger default heap and stack size config + - cmake: fix add_subdirectory_ifdef arg processing. + - doc: boards: hpm6300evk: fix acmp pin info. + - boards: hpm6750evkmini: fix board_init_rgb_pwm_pins() problem + - boards: hpm6200evk: fix BOARD_G_GPIO_CTRL defined in wrong position + - openocd: hpm6750-dual-core: fix expression warning. + - component: wm8960: fix clock tolerance process + - soc: toolchains: segger: block tls add with fixed order + - soc: toolchain: gcc: fix Thread-Local Storage problem + - soc: segger linker files: fix heap and ctors initialize + - soc: fix interrupt complete operation + - soc: pcfg: fix DCDC_PROT[OVERLOAD_LP] bit access + - soc: ip: adc12: fix ADC12 threshold setting + - soc: HPM6750: fix clock setting and frequency obatining error + - soc: HPM6360: fix clock source definitions for ADC16 + - soc: HPM6280: fix clock source definitions for ADC16 + - soc: HPM6360: fix obtaining clock source error for DAC + - soc: HPM6280: fix obtaining clock source for DAC + - drivers: adc16: add bus mode enable control APIs + - drivers: adc16: fix ahb setting + - drivers: cam: clear the status of CAM should not affect other bits + - drivers: trgmux: filter function can't work. + - drivers: src: adc16: fix end count setting + - drivers: adc/dac: fix interrupt status clearing + - drivers: adc16: fix DMA access format + - drivers: sdm: fix over sample rate and signal sync problem + - drivers: pwm: fix pwm xcmp enable setting + - drivers: pwm: correct external fault polarity setting. + - drivers: pwm: add update hrpwm reload shadow api + - drivers: spi: fix can't set change data_bits use spi_set_data_bits API + - drivers: ptpc: fix ptpc_clear_irq_status API issue. + - drivers: i2c: fix i2c_clear_status API issue. + - drivers: gptmr: fix gptmr_clear_status API issue. + - middleware: erpc: rpmsg_lite: fix platform_in_isr() error + - middleware:hpm_sdmmc Fix the issue sdsc cards are not supported. + - middleware: threadx: fix D extend asm code error + - samples: usbx: add multi devices and hot plug support + - samples: motor_ctrl: fix adc trig invalidate. + - samples: lwip: fix TCP reception error when size over 2KB + - samples: lwip: DHCP failure in lwip_tcpecho_freertos + - samples: drivers: adc: adc12: fix the status flag judgement in isr process + - samples: rgb_led: fix cmp shadow error + - samples: gptmr: pwm_generate: fix inaccurate duty in high frequency + - samples: lwip: low_level_input: fix the network storm issue + - samples: timer_basic: fix inconsistent use of defines + - samples: drivers: adc: adc16: fix the bit of interrupt status clearing in sequence mode + - samples: power_mode_switch: trigger system lowpower for standby mode + - samples: touch_panel: fix error data when 5 fingers touch screen at same time. + - samples: jpeg: jpeg_decode: fixed lcd display is tore when decoder is running + - samples: jpeg: jpeg_decode: malloc out of memory on gcc + - samples: drivers:can Fix abnormal behavior on can error sample. + - samples: segger_rtt: call board_init_clock. + - samples: drivers: acmp: fix one toggle value but multi toggle pulses + - samples: lwip_tcpecho_freerstos: fix code stuck with gcc toolchain + - samples: jpeg: fix JPEG_USE_UDISK compile error + - samples: bldc_foc: fix input value range. + - samples: cherryusb: rndis: udp_echo: fix echo extra char + - samples: usbx: fix global var placement + - samples: power_mode_switch: set to preset_1 after exiting wait mode. + - samples: pla: fix pla first pulse abnormal. + - samples: plb: fix the first pulse is abnormal. + ## [1.2.0] - 2023-06-30: Main changes since 1.1.0 @@ -496,7 +1079,7 @@ Main changes since 0.10.0-hpm6360-er - boards: LED status is not the same between hpm6750mini rev-A and rev-B - boards: update board_led_write. -## Added: +### Added: - driver: add spi_setup_dma_transfer() API - middleware: hpm_math: add software fft function - middleware: hpm_math: add ffa to hpm_math @@ -680,3 +1263,4 @@ All changes since 0.6.2 - samples: drivers: gpiom: Add example to demonstrate gpiom's function - drivers: common: add macro to put data into noncacheable sections - middleware: integrate lwip + diff --git a/bsp/hpmicro/libraries/hpm_sdk/README.md b/bsp/hpmicro/libraries/hpm_sdk/README.md index 95212bc5a78..389c0384ebb 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/README.md +++ b/bsp/hpmicro/libraries/hpm_sdk/README.md @@ -3,10 +3,10 @@ gantt title HPM SDK Release Plan dateFormat YYYY-MM-DD section Mainline Release - v1.1.0 :a1, 2023-01-01, 2023-03-31 - v1.2.0 :a2, 2023-04-01, 2023-06-30 - v1.3.0 :a3, 2023-07-01, 2023-09-30 - v1.4.0 :a4, 2023-10-01, 2023-12-31 + v1.5.0 :a1, 2024-01-01, 2024-03-31 + v1.6.0 :a2, 2024-04-01, 2024-06-30 + v1.7.0 :a3, 2024-07-01, 2024-09-30 + v1.8.0 :a4, 2024-10-01, 2024-12-31 ``` [中文](README_zh.md) @@ -35,259 +35,16 @@ The HPM SDK Project is a software development kit based on HPMicro's MCUs, which SDK documentation can be built locally, once it's done, it can be accessed with the following entries: - >/docs/index.html - >/docs/index_zh.html - > Please refer to /docs/README.md for more details about documentation building. + > Please refer to for [hpm_sdk Getting Started](docs/en/get_started.md) more details about documentation building. - Online: - http://hpm-sdk.readthedocs.io/ - http://hpm-sdk-zh.readthedocs.io/ -## HPM SDK Quick Start Guide - -### Minimum required version of dependencies are: - - | Name | Version | - | -------|---------- | - |CMake | 3.13 | - | Python | 3.8 | - -### Install Dependencies - - Ubuntu - - install tools - - ```shell - sudo apt install build-essential cmake ninja-build libc6-i386 libc6-i386-cross libstdc++6-i386-cross - ``` - - install python3 (3.8.5 minimum) and pip - - ```shell - sudo apt install python3 python3-pip - ``` - - - Windows - - Windows Command Prompt - The following commands assume you are using cmd.exe, it might differ if you are using PowerShell. - - Install Chocolatey (https://chocolatey.org/) - It is a package manager for Windows, with which it's not that difficult to install native Windows dependencies. - 1. Install Chocolatey by the following instructions on the Chocolatey Install (https://chocolatey.org/install) page. - 2. Open "cmd.exe" as "Administrator" - 3. Disable global confirmation to avoid having to confirm installation of individual programs: - - ```Batchfile - choco feature enable -n allowGlobalConfirmation - ``` - - 4. Install CMake - - ```Batchfile - choco install cmake --installargs 'ADD_CMAKE_TO_PATH=System' - ``` - 5. Install other tools: - - ```Batchfile - choco install git python ninja - ``` - 6. Close the Administrator command prompt window. - -- Prepare Toolchain & Environment Variables - - Supported toolchains: - - gnu-gcc <-- default toolchain - - nds-gcc - - Toolchain setup: - - gnu-gcc: - 1. Grab a copy of toolchain zip package and unzip to certain path, take TOOLCHAIN_PATH for example, (riscv32-unknown-elf-gcc is supposed to be found in TOOLCHAIN_PATH/bin) - 2. Declare a system environment variable of "GNURISCV_TOOLCHAIN_PATH" to the path of toolchain: - - Linux, taking zsh for example (replace TOOLCHAIN_PATH with the path of toolchain on your workstation): - ```shell - export GNURISCV_TOOLCHAIN_PATH=TOOLCHAIN_PATH - export HPM_SDK_TOOLCHAIN_VARIANT= - ``` - - Windows command prompt: - ```Batchfile - set GNURISCV_TOOLCHAIN_PATH=TOOLCHAIN_PATH - set HPM_SDK_TOOLCHAIN_VARIANT= - ``` - - nds-gcc: - 1. Grab a copy of toolchain zip package and unzip to certain path, take TOOLCHAIN_PATH for example, (riscv32-elf-gcc is supposed to be found in TOOLCHAIN_PATH/bin) - 2. Declare two system environment variables: "GNURISCV_TOOLCHAIN_PATH" to the path of toolchain; "HPM_SDK_TOOLCHAIN_VARIANT" to "nds-gcc": - - Linux, taking zsh for example (replace TOOLCHAIN_PATH with the path of toolchain on your workstation): - ```shell - export GNURISCV_TOOLCHAIN_PATH=TOOLCHAIN_PATH - export HPM_SDK_TOOLCHAIN_VARIANT=nds-gcc - ``` - - Windows command prompt: - ```Batchfile - set GNURISCV_TOOLCHAIN_PATH=TOOLCHAIN_PATH - set HPM_SDK_TOOLCHAIN_VARIANT=nds-gcc - ``` - Note: For windows, Andes compiler needs following libraries: - - cygwin1.dll - - cygncursesw-10.dll - make sure its path is appended to the system environment variable "PATH". - - Environment Variables: - - Using provided scripts to set the environment variable: - - Linux: - ```shell - $ source env.sh - ``` - - Windows command prompt: - ```Batchfile - env.cmd - ``` - - Manually declare a environment variable of "HPM_SDK_BASE" to the path of SDK root: - - Linux, taking zsh for example (assume SDK is located at $HOME/hpm_sdk): - ```shell - export HPM_SDK_BASE=$HOME/hpm_sdk - ``` - - Windows command prompt (assume SDK is located at c:\hpm_sdk): - ```Batchfile - set HPM_SDK_BASE=c:\hpm_sdk - ``` - -- Install python dependencies - - Linux: - ```shell - pip3 install --user -r "$HPM_SDK_BASE/scripts/requirements.txt" - ``` - - - Window (by default, python3/pip3 is not available after Python 3.x installed on Windows, but only python/pip): - - ```Batchfile - pip install --user -r "%HPM_SDK_BASE%/scripts/requirements.txt" - ``` - -- Build An Application with GNU GCC toolchain - On finishing the steps mentioned above, SDK projects can be generated and built. - The following steps describe how a demo can be built: - 1. Go to application directory, taking hello_world for example: - - ```shell - cd samples/hello_world - ``` - - 2. create a directory for build - - Linux: - - ```shell - mkdir build - ``` - - - Windows: - - ```Batchfile - md build - ``` - - 3. Change directory to "build" - - ```Batchfile - cd build - ``` - - 4. Generate build files for Ninja: - ```shell - cmake -GNinja -DBOARD=hpm6750evk .. - ``` - Note: if it complains about "CMAKE_MAKE_PROGRAM is not set", please - append -DCMAKE_MAKE_PROGRAM=YOUR_MAKE_EXECUTABLE_PATH to the previous - command (NINJA_PATH is the folder in which ninja can be found): - - ```shell - cmake -GNinja -DBOARD=hpm6750evk -DCMAKE_MAKE_PROGRAM=NINJA_PATH/ninja .. - ``` - - 5. Building: - - ```shell - ninja - ``` - - When it's done the elf and other application related files can be found in the directory of "output", like map file, assembly source or binary file - -- Quick Guide to Run/Debug An Application (hello_world): - 1. Wire up the board, including debug probe (by default it supports jlink) and serial port - 2. power up the board - 3. open console connecting to the debug console (target serial port) with baudrate of 115200 - 4. get a copy of openocd. it can be installed via package management system or downloaded from sourceforge or github. But please make sure its revision is > 0.11 - 5. Go to SDK root directory, run provided environment variable scripts: - - Linux: - ```shell - $ source env.sh - ``` - - - Windows command prompt: - ```Batchfile - env.cmd - ``` - or setup environment variable OPENOCD_SCRIPTS manually: - - - Linux: - ``` shell - $ export OPENOCD_SCRIPTS=${HPM_SDK_BASE}/boards/openocd - ``` - - - Windows: - ``` - set OPENOCD_SCRIPTS=%HPM_SDK_BASE%\boards\openocd - ``` - - 6. Start openocd with several configuration files in order of type of probe, type of core, type of board. For example, the following command will setup an openocd gdb server with ft2232 to single core on hpm6750evk - - ```shell - openocd -f probes/ft2232.cfg -f soc/hpm6750-single-core.cfg -f boards/hpm6750evk.cfg - ``` - Note: If using FTDI debugger and meet `Error: libusb_open() failed with LIBUSB_ERROR_NOT_FOUND` , please check the FTDI usb driver. If it is not installed correctly, use [zadig](https://github.com/pbatard/libwdi/releases/download/b730/zadig-2.5.exe) to update: - - Open zadig, click Options-> List All Devices. - - ![List All Devices](docs/assets/zadig_list_all_devices.png) - - Select Dual RS232-HS (Interface 0). - - ![Select Dual RS232-HS (Interface 0)](docs/assets/zadig_select_dual_rs232-hs.png) - - Then click Install Driver or Replace Driver. - - ![Replace Driver](docs/assets/zadig_replace_driver.png) - - 7. Go to hello_world directory - - ```shell - cd samples/hello_world - ``` - - 8. open up another terminal to start a gdb client - - gnu-gcc: - - ```shell - TOOLCHAIN_PATH/bin/riscv32-unknown-elf-gdb - ``` - - - nds-gcc: - - ```shell - TOOLCHAIN_PATH/bin/riscv32-elf-gdb - ``` - - 9. connect gdb client to the gdbserver started by openocd, (by default, gdbserver port is 3333) - - ```GDB - gdb> file build/output/demo.elf - gdb> target remote localhost:3333 - gdb> load - gdb> b main - gdb> c - ``` - - 10. on the debug console, "hello_world" is printed. - -- Build An Application with Segger Embedded Studio - - Segger Embedded Studio for RISC-V can be downloaded from https://www.segger.com/downloads/embedded-studio/ - - Project file for Segger Embedded Studio will be generated while generating build files for Ninja mentioned in "Build An Application with GNU GCC toolchain"->"4. Generate build files for Ninja" - - The project file (.emProject) can be found at build/segger_embedded_studio/. - - Note: openocd executable needs to be found in the PATH variable of current console, otherwise debug configuration will not be generated to project file and needs to be configured manually in Segger Embedded Studio later. - -# Community Support -- github page: https://hpmicro.github.io -- github: https://github.com/hpmicro/hpm_sdk -- gitee: https://gitee.com/hpmicro/hpm_sdk +## Repositories +- hpm_sdk: https://github.com/hpmicro/hpm_sdk +- sdk_env: https://github.com/hpmicro/sdk_env +- sdk extra demo: https://github.com/hpmicro/hpm_sdk_extra +- openocd (hpmicro patched): https://github.com/hpmicro/riscv-openocd +- gnu gcc toolchain: https://github.com/hpmicro/riscv-gnu-toolchain +> Note: repositories are mirrored on gitee. diff --git a/bsp/hpmicro/libraries/hpm_sdk/README_zh.md b/bsp/hpmicro/libraries/hpm_sdk/README_zh.md index 2e0c30cd3b5..22b86f655ad 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/README_zh.md +++ b/bsp/hpmicro/libraries/hpm_sdk/README_zh.md @@ -3,10 +3,10 @@ gantt title HPM SDK Release Plan dateFormat YYYY-MM-DD section Mainline Release - v1.1.0 :a1, 2023-01-01, 2023-03-31 - v1.2.0 :a2, 2023-04-01, 2023-06-30 - v1.3.0 :a3, 2023-07-01, 2023-09-30 - v1.4.0 :a4, 2023-10-01, 2023-12-31 + v1.5.0 :a1, 2024-01-01, 2024-03-31 + v1.6.0 :a2, 2024-04-01, 2024-06-30 + v1.7.0 :a3, 2024-07-01, 2024-09-30 + v1.8.0 :a4, 2024-10-01, 2024-12-31 ``` [English](README.md) @@ -35,266 +35,16 @@ HPM SDK项目是基于HPMicro 公司的MCU编写的软件开发包，支持多 SDK文档可以进行本地编译，成功编译之后可以通过以下入口访问本地文档: - >/docs/index.html - >/docs/index_zh.html - > 文档编译方式请参考/docs/README.md + > 文档编译方式请参考[hpm_sdk Getting Started](docs/zh/get_started.md) - 在线文档： - http://hpm-sdk.readthedocs.io/ - http://hpm-sdk-zh.readthedocs.io/ -## HPM SDK使用说明 +## 代码仓库 +- hpm_sdk github: https://github.com/hpmicro/hpm_sdk +- sdk_env github: https://github.com/hpmicro/sdk_env +- sdk extra demo: https://github.com/hpmicro/hpm_sdk_extra +- openocd (hpmicro patched): https://github.com/hpmicro/riscv-openocd +- gnu gcc toolchain: https://github.com/hpmicro/riscv-gnu-toolchain -### 依赖软件最低版本要求 - -| 软件名称 | 版本号 | -|--- | --- | -| CMake | 3.13 | -| Python | 3.8 | - -### 安装依赖 - -- Ubuntu: - - 安装工具: - -```shell - sudo apt install build-essential cmake ninja-build libc6-i386 libc6-i386-cross libstdc++6-i386-cross -``` - - - 安装python3 (3.8.5 minimum) 与pip: - -```shell - sudo apt install python3 python3-pip -``` - -- Windows: - - Windows命令行: - 以下所使用的命令都以Windows命令行(cmd.exe)为例: - - 安装 Chocolatey (): - 该工具为Windows下的包管理软件,通过该工具可以方便地在Windows平台上安装依赖软件: - 1. 根据Chocolatey官方步骤进行安装() - 2. 以管理员身份打开"cmd.exe" - 3. 禁用全局安装确认: - - ```Batchfile - choco feature enable -n allowGlobalConfirmation - ``` - - 4. 安装CMake: - - ```Batchfile - choco install cmake --installargs 'ADD_CMAKE_TO_PATH=System' - ``` - - 5. 安装其他工具: - - ```Batchfile - choco install git python ninja - ``` - - 6. 关闭该命令行窗口 - -## 准备工具链与环境变量配置 - -- 支持的工具链: - - gnu-gcc <-- 缺省工具链 - - nds-gcc -- 工具链: - - gnu-gcc: - - 下载工具链压缩包,并解压.假定TOOLCHAIN_PATH作为工具链的解压目录(需要满足在TOOLCHAIN_PATH\bin下可以找到riscv32-unknown-elf-gcc) - - 申明系统环境变量"GNURISCV_TOOLCHAIN_PATH"指向工具链路径: - - Linux, 以zsh为例(确保将TOOLCHAIN_PATH替换成你自己的路径): - ```shell - export GNURISCV_TOOLCHAIN_PATH=TOOLCHAIN_PATH - export HPM_SDK_TOOLCHAIN_VARIANT= - ``` - - Windows命令行: - ```Batchfile - set GNURISCV_TOOLCHAIN_PATH=TOOLCHAIN_PATH - set HPM_SDK_TOOLCHAIN_VARIANT= - ``` - - nds-gcc: - - 下载工具链压缩包,并解压.假定TOOLCHAIN_PATH作为工具链的解压目录(需要满足在TOOLCHAIN_PATH\bin下可以找到riscv32-elf-gcc) - - 申明系统环境变量"GNURISCV_TOOLCHAIN_PATH"指向工具链路径: - - Linux, 以zsh为例(确保将TOOLCHAIN_PATH替换成你自己的路径): - ```shell - export GNURISCV_TOOLCHAIN_PATH=TOOLCHAIN_PATH - export HPM_SDK_TOOLCHAIN_VARIANT=nds-gcc - ``` - - Windows命令行: - ```Batchfile - set GNURISCV_TOOLCHAIN_PATH=TOOLCHAIN_PATH - set HPM_SDK_TOOLCHAIN_VARIANT=nds-gcc - ``` - Note: Windows平台上Andes toolchain需要以下cygwin库文件: - - cygwin1.dll - - cygncursesw-10.dll - 务必确保以上库文件所在目录被包含在系统环境变量PATH中 - -- SDK编译所需环境变量设置: - - 通过运行提供的脚本执行: - - Linux: - - ```shell - source env.sh - ``` - - - Windows 命令行: - - ```Batchfile - env.cmd - ``` - - - 手工设置环境变量"HPM_SDK_BASE"指向SDK根目录: - - Linux, 以zsh为例(假定$HOME/hpm_sdk为SDK根目录): - - ```shell - export HPM_SDK_BASE=$HOME/hpm_sdk - ``` - - - Windows 命令行(假定c:\hpm_sdk为SDK根目录): - ```Batchfile - set HPM_SDK_BASE=c:\hpm_sdk - ``` - -- 安装Python依赖包: - - Linux: - - ```shell - pip3 install --user -r "$HPM_SDK_BASE/scripts/requirements.txt" - ``` - - - Window (Windows平台上Python 3.x 安装之后无法找到 python3/pip3, 只有python/pip): - ```Batchfile - pip install --user -r "%HPM_SDK_BASE%/scripts/requirements.txt" - ``` - -- 使用GNU GCC工具链编译示例应用: - 做完尚书步骤之后, 就可以构建编译SDK示例工程. 以下步骤描述了如何编译hello_world: - 1. 切换到示例应用目录: - - ```shell - cd samples/hello_world - ``` - - 2. 创建build目录: - - Linux: - - ```shell - mkdir build - ``` - - - Windows: - - ```Batchfile - md build - ``` - - 3. 切换目录到"build" - - ```shell - cd build - ``` - - 4. 为Ninja-build产生构建文件: - - ```shell - cmake -GNinja -DBOARD=hpm6750evk .. - ``` - - Note: 如果提示"CMAKE_MAKE_PROGRAM is not set", 可以通过在以上命令中追加"-DCMAKE_MAKE_PROGRAM=YOUR_MAKE_EXECUTABLE_PATH" (NINJA_PATH为ninja-build的目录,在其下可以找到ninja): - # cmake -GNinja -DBOARD=hpm6750evk -DCMAKE_MAKE_PROGRAM=NINJA_PATH/ninja .. - - 5. 编译: - - ```shell - ninja - ``` - - 当编译完成后,生成的elf以及对应的其他文件可以在output目录中找到. - -- 运行/调试示例程序说明(hello_world): - 1. 完成评估板连线,包括调试器,串口线以及电源线 - 2. 打开电源 - 3. 打开串口软件,设置baudrate为115200 - 4. 安装openocd(0.11以上) - 5. 切换至SDK根目录, 运行设置环境变量脚本: - - Linux: - - ```shell - $ source env.sh - ``` - - Windows command prompt: - - ```Batchfile - env.cmd - ``` - 或者手动设置名为OPENOCD_SCRIPTS的环境变量: - - Linux: - ``` shell - $ export OPENOCD_SCRIPTS=${HPM_SDK_BASE}/boards/openocd - - ``` - - Windows: - ``` - set OPENOCD_SCRIPTS=%HPM_SDK_BASE%\boards\openocd - ``` - - 6. 运行openocd, 需要按顺序指定配置文件: 调试器配置, 内核配置, 目标板配置。例如，通过ft2232在hpm6750evk上进行单核调试，可以运行如下命令: - - ```shell - openocd -f probes/ft2232.cfg -f soc/hpm6750-single-core.cfg -f boards/hpm6750evk.cfg - ``` - - Note: 如果使用FTDI调试器并遇到提示`Error: libusb_open() failed with LIBUSB_ERROR_NOT_FOUND` , 请检查FTDI usb驱动。如果驱动未正确安装，使用 [zadig](https://github.com/pbatard/libwdi/releases/download/b730/zadig-2.5.exe) 更新驱动： - - 打开zadig，点击 Options->List All Devices. - - ![List All Devices](docs/assets/zadig_list_all_devices.png) - - 选择 Dual RS232-HS (Interface 0). - - ![Select Dual RS232-HS (Interface 0)](docs/assets/zadig_select_dual_rs232-hs.png) - - 然后点击 Install Driver 或 Replace Driver. - - ![Replace Driver](docs/assets/zadig_replace_driver.png) - - 7. 切换到hello_world目录 - - ```shell - cd samples/hello_world - ``` - - 8. 打开另一个终端,启动GDB client: - - gnu-gcc: - - ```shell - TOOLCHAIN_PATH/bin/riscv32-unknown-elf-gdb - ``` - - - nds-gcc: - - ```shell - TOOLCHAIN_PATH/bin/riscv32-elf-gdb - ``` - - 9. 连接GDB client到openocd GDB server (缺省状态下, openocd gdbserver 端口为 3333) - - ```GDB - gdb> file build/output/demo.elf - gdb> target remote localhost:3333 - gdb> load - gdb> b main - gdb> c - ``` - 10. 顺利运行后可以在串口终端上打印"hello_world". - -- 使用Segger Embedded Studio for RISC-V编译应用 - - Segger Embedded Studio for RISC-V 可以从 https://www.segger.com/downloads/embedded-studio/ 下载 - - Segger Embedded Studio for RISC-V 工程文件会在 "使用GNU GCC工具链编译示例应用:" -> "4. 为Ninja-build产生构建文件:" 描述的过程中 - - 产生的工程文件(.emProject)可以在build/segger_embedded_studio目录中找到 - - 注意：openocd可执行文件应该可以通过当前终端的PATH环境变量中可以找到, 否则无法在工程文件中生成相应的调试配置，需要之后在Segger Embedded Studio中手工配置。 - -## 社区支持 -- github page: https://hpmicro.github.io -- github: https://github.com/hpmicro/hpm_sdk -- gitee: https://gitee.com/hpmicro/hpm_sdk +> 仓库在gitee上有对应的镜像。 diff --git a/bsp/hpmicro/libraries/hpm_sdk/SConscript b/bsp/hpmicro/libraries/hpm_sdk/SConscript index 978f6501413..182e7beb4e2 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/SConscript +++ b/bsp/hpmicro/libraries/hpm_sdk/SConscript @@ -10,12 +10,18 @@ path = [ cwd + '/arch', cwd + "/drivers/inc", cwd + '/soc/ip'] # The set of source files associated with this SConscript file. src = [] +CPPDEFINES=[] + src += ['drivers/src/hpm_pmp_drv.c'] src += ['drivers/src/hpm_pllctl_drv.c'] src += ['drivers/src/hpm_pllctlv2_drv.c'] -src += ['drivers/src/hpm_dma_drv.c'] src += ['drivers/src/hpm_pcfg_drv.c'] +if rtconfig.CHIP_NAME == "HPM6750" or rtconfig.CHIP_NAME == "HPM6360" or rtconfig.CHIP_NAME == "HPM6280": + src += ['drivers/src/hpm_dma_drv.c'] +else: + src += ['drivers/src/hpm_dmav2_drv.c'] + CPPDEFINES = ['HPMSOC_HAS_HPMSDK_DMAV2'] if GetDepend(['BSP_USING_GPIO']): src += ['drivers/src/hpm_gpio_drv.c'] @@ -35,6 +41,9 @@ if GetDepend(['BSP_USING_RTC']): if GetDepend(['BSP_USING_WDG']): src += ['drivers/src/hpm_wdg_drv.c'] +if GetDepend(['BSP_USING_EWDG']): + src += ['drivers/src/hpm_ewdg_drv.c'] + if GetDepend(['BSP_USING_ADC']): if GetDepend(['BSP_USING_ADC12']): src += ['drivers/src/hpm_adc12_drv.c'] @@ -59,7 +68,7 @@ if GetDepend(['BSP_USING_SDXC']): if GetDepend(['BSP_USING_LCD']): src += ['drivers/src/hpm_lcdc_drv.c'] -if GetDepend(['BSP_USING_GPTMR']): +if GetDepend(['BSP_USING_GPTMR']) or GetDepend('HPM_USING_VECTOR_PREEMPTED_MODE'): src += ['drivers/src/hpm_gptmr_drv.c'] if GetDepend(['BSP_USING_FEMC']): @@ -85,6 +94,22 @@ if GetDepend(['BSP_USING_DAO']): if GetDepend(['BSP_USING_PDMA']): src += ['drivers/src/hpm_pdma_drv.c'] -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) +if GetDepend(['BSP_USING_JPEG']): + src += ['drivers/src/hpm_jpeg_drv.c'] + +if GetDepend(['BSP_USING_CAM']): + src += ['drivers/src/hpm_cam_drv.c'] + +if GetDepend(['BSP_USING_PIXELMUX']): + src += ['drivers/src/hpm_pixelmux_drv.c'] + +if GetDepend(['BSP_USING_MIPI_CSI']): + src += ['drivers/src/hpm_mipi_csi_drv.c'] + src += ['drivers/src/hpm_mipi_csi_phy_drv.c'] + +if GetDepend(['BSP_USING_MIPI_DSI']): + src += ['drivers/src/hpm_mipi_dsi_drv.c'] + src += ['drivers/src/hpm_mipi_dsi_phy_drv.c'] +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES=CPPDEFINES) Return ('group') diff --git a/bsp/hpmicro/libraries/hpm_sdk/VERSION b/bsp/hpmicro/libraries/hpm_sdk/VERSION index cca691de9ad..e110767a670 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/VERSION +++ b/bsp/hpmicro/libraries/hpm_sdk/VERSION @@ -1,5 +1,5 @@ VERSION_MAJOR = 1 -VERSION_MINOR = 2 +VERSION_MINOR = 5 PATCHLEVEL = 0 VERSION_TWEAK = 0 EXTRAVERSION = 0 diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/SConscript b/bsp/hpmicro/libraries/hpm_sdk/components/SConscript index 5fe6980bccc..bf10b43d427 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/SConscript +++ b/bsp/hpmicro/libraries/hpm_sdk/components/SConscript @@ -8,36 +8,111 @@ cwd = GetCurrentDir() CPPDEFINES=[] # Update include path -path = [ os.path.join(cwd, 'debug_console'), os.path.join(cwd, 'touch'), os.path.join(cwd, 'usb'), os.path.join(cwd, 'dma_manager')] +path = [ os.path.join(cwd, 'debug_console'), os.path.join(cwd, 'touch'), os.path.join(cwd, 'usb'), os.path.join(cwd, 'dma_mgr')] # The set of source files associated with this SConscript file. src = [] src += [ os.path.join(cwd, 'debug_console', 'hpm_debug_console.c') ] -src += [ os.path.join(cwd, 'dma_manager', 'hpm_dma_manager.c') ] +src += [ os.path.join(cwd, 'dma_mgr', 'hpm_dma_mgr.c') ] if GetDepend(['BSP_USING_TOUCH_GT911']): src += [os.path.join(cwd, 'touch', 'gt911', 'hpm_touch_gt911.c') ] src += [os.path.join(cwd, 'touch', 'gt911', 'hpm_gt911.c') ] path += [ os.path.join(cwd, 'touch', 'gt911') ] - CPPDEFINES = ['CONFIG_TOUCH_GT911=1'] + CPPDEFINES += ['CONFIG_TOUCH_GT911=1'] if GetDepend(['BSP_USING_TOUCH_FT5406']): src += [ os.path.join(cwd, 'touch', 'ft5406', 'hpm_touch_ft5406.c') ] src += [ os.path.join(cwd, 'touch', 'ft5406', 'hpm_ft5406.c') ] path += [ os.path.join(cwd, 'touch', 'ft5406') ] - CPPDEFINES = ['CONFIG_TOUCH_FT5406=1'] + CPPDEFINES += ['CONFIG_TOUCH_FT5406=1'] if GetDepend(['BSP_USING_USB_DEVICE']): src += [ os.path.join(cwd, 'usb', 'device', 'hpm_usb_device.c') ] path += [ os.path.join(cwd, 'usb', 'device') ] if GetDepend(['BSP_USING_USB_HOST']): src += [ os.path.join(cwd, 'usb', 'host', 'hpm_usb_host.c') ] path += [ os.path.join(cwd, 'usb', 'host') ] + CPPDEFINES += ['USB_HOST_MCU_CORE=HPM_CORE0'] +if GetDepend(['BSP_USING_ETH0']): + if GetDepend(['BSP_USING_ENET_PHY_DP83867']): + src += [ os.path.join(cwd, 'enet_phy/dp83867/hpm_dp83867.c') ] + path += [ os.path.join(cwd, 'enet_phy') ] + path += [ os.path.join(cwd, 'enet_phy/dp83867') ] + CPPDEFINES += ['__USE_DP83867=1'] +if GetDepend(['BSP_USING_ETH1']): + if GetDepend(['BSP_USING_ENET_PHY_DP83848']): + src += [ os.path.join(cwd, 'enet_phy/dp83848/hpm_dp83848.c') ] + path += [ os.path.join(cwd, 'enet_phy') ] + path += [ os.path.join(cwd, 'enet_phy/dp83848') ] + CPPDEFINES += ['__USE_DP83848=1'] +if GetDepend(['BSP_USING_ETH0']): + if GetDepend(['BSP_USING_ENET_PHY_RTL8211']): + src += [ os.path.join(cwd, 'enet_phy/rtl8211/hpm_rtl8211.c') ] + path += [ os.path.join(cwd, 'enet_phy') ] + path += [ os.path.join(cwd, 'enet_phy/rtl8211') ] + CPPDEFINES += ['__USE_RTL8211=1'] + if GetDepend(['BSP_USING_ENET_PHY_RTL8201']): + src += [ os.path.join(cwd, 'enet_phy/rtl8201/hpm_rtl8201.c') ] + path += [ os.path.join(cwd, 'enet_phy') ] + path += [ os.path.join(cwd, 'enet_phy/rtl8201') ] + CPPDEFINES += ['__USE_RTL8201=1'] if GetDepend(['BSP_USING_ETH1']): - if GetDepend(['BSP_USING_ENET_PHY_RTL8201']): - src += [ os.path.join(cwd, 'enet_phy/rtl8201/hpm_rtl8201.c') ] + if GetDepend(['BSP_USING_ENET_PHY_RTL8201']): + src += [ os.path.join(cwd, 'enet_phy/rtl8201/hpm_rtl8201.c') ] path += [ os.path.join(cwd, 'enet_phy') ] path += [ os.path.join(cwd, 'enet_phy/rtl8201') ] - + CPPDEFINES += ['__USE_RTL8201=1'] + if GetDepend(['BSP_USING_ENET_PHY_LAN8720']): + src += [ os.path.join(cwd, 'enet_phy/lan8720/hpm_lan8720.c') ] + path += [ os.path.join(cwd, 'enet_phy') ] + path += [ os.path.join(cwd, 'enet_phy/lan8720') ] + CPPDEFINES += ['__USE_LAN8720=1'] +if GetDepend(['BSP_USING_CAMERA']): + path += [ os.path.join(cwd, 'camera') ] +if GetDepend(['BSP_USING_CAMERA_MT9M114']): + src += [os.path.join(cwd, 'camera', 'mt9m114', 'hpm_mt9m114.c') ] + src += [os.path.join(cwd, 'camera', 'mt9m114', 'hpm_camera_mt9m114.c') ] + path += [ os.path.join(cwd, 'camera', 'mt9m114') ] + CPPDEFINES += ['CONFIG_CAMERA_MT9M114=1'] +if GetDepend(['BSP_USING_CAMERA_OV5640']): + src += [os.path.join(cwd, 'camera', 'ov5640', 'hpm_camera_ov5640.c') ] + src += [os.path.join(cwd, 'camera', 'ov5640', 'hpm_ov5640.c') ] + path += [ os.path.join(cwd, 'camera', 'ov5640') ] + CPPDEFINES += ['CONFIG_CAMERA_OV5640=1'] +if GetDepend(['BSP_USING_CAMERA_OV7725']): + src += [os.path.join(cwd, 'camera', 'ov7725', 'hpm_camera_ov7725.c') ] + src += [os.path.join(cwd, 'camera', 'ov7725', 'hpm_ov7725.c') ] + path += [ os.path.join(cwd, 'camera', 'ov7725') ] + CPPDEFINES += ['CONFIG_CAMERA_OV7725=1'] +if GetDepend(['BSP_USING_PANEL']): + path += [ os.path.join(cwd, 'panel') ] + src += [os.path.join(cwd, 'panel', 'hpm_panel.c') ] + CPPDEFINES += ['CONFIG_HPM_PANEL'] +if GetDepend(['BSP_USEING_PANEL_RGB_TM070RDH13']): + src += [os.path.join(cwd, 'panel', 'panels', 'tm070rdh13.c') ] + path += [ os.path.join(cwd, 'panel', 'panels') ] + CPPDEFINES += ['PANEL_SIZE_WIDTH=800'] + CPPDEFINES += ['PANEL_SIZE_HEIGHT=480'] + CPPDEFINES += ['CONFIG_PANEL_RGB_TM070RDH13=1'] +if GetDepend(['BSP_USEING_PANEL_MIPI_MC10128007_31B']): + src += [os.path.join(cwd, 'panel', 'panels', 'mc10128007_31b.c') ] + path += [ os.path.join(cwd, 'panel', 'panels') ] + CPPDEFINES += ['PANEL_SIZE_WIDTH=800'] + CPPDEFINES += ['PANEL_SIZE_HEIGHT=1280'] + CPPDEFINES += ['CONFIG_PANEL_MIPI_MC10128007_31B=1'] +if GetDepend(['BSP_USEING_PANEL_LVDS_TM103XDGP01']): + src += [os.path.join(cwd, 'panel', 'panels', 'tm103xdgp01.c') ] + path += [ os.path.join(cwd, 'panel', 'panels') ] + CPPDEFINES += ['PANEL_SIZE_WIDTH=1920'] + CPPDEFINES += ['PANEL_SIZE_HEIGHT=720'] + CPPDEFINES += ['CONFIG_PANEL_LVDS_TM103XDGP01=1'] +if GetDepend(['BSP_USEING_PANEL_LVDS_CC10128007']): + src += [os.path.join(cwd, 'panel', 'panels', 'cc10128007.c') ] + path += [ os.path.join(cwd, 'panel', 'panels') ] + CPPDEFINES += ['PANEL_SIZE_WIDTH=800'] + CPPDEFINES += ['PANEL_SIZE_HEIGHT=1280'] + CPPDEFINES += ['CONFIG_PANEL_LVDS_CC10128007=1'] + group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES=CPPDEFINES) Return ('group') diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/adc/hpm_adc.h b/bsp/hpmicro/libraries/hpm_sdk/components/adc/hpm_adc.h index 27198476e60..2aaafaaf08f 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/adc/hpm_adc.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/adc/hpm_adc.h @@ -8,10 +8,10 @@ #define HPM_ADC_H #include "hpm_common.h" -#ifdef CONFIG_HAS_HPMSDK_ADC12 +#ifdef HPMSOC_HAS_HPMSDK_ADC12 #include "hpm_adc12_drv.h" #endif -#ifdef CONFIG_HAS_HPMSDK_ADC16 +#ifdef HPMSOC_HAS_HPMSDK_ADC16 #include "hpm_adc16_drv.h" #endif #include "hpm_soc_feature.h" @@ -27,10 +27,10 @@ * */ typedef union { -#ifdef CONFIG_HAS_HPMSDK_ADC12 +#ifdef HPMSOC_HAS_HPMSDK_ADC12 ADC12_Type *adc12; #endif -#ifdef CONFIG_HAS_HPMSDK_ADC16 +#ifdef HPMSOC_HAS_HPMSDK_ADC16 ADC16_Type *adc16; #endif } adc_base; @@ -55,10 +55,10 @@ typedef struct { adc_module module; adc_base adc_base; struct { -#ifdef CONFIG_HAS_HPMSDK_ADC12 +#ifdef HPMSOC_HAS_HPMSDK_ADC12 adc12_config_t adc12; #endif -#ifdef CONFIG_HAS_HPMSDK_ADC16 +#ifdef HPMSOC_HAS_HPMSDK_ADC16 adc16_config_t adc16; #endif } config; @@ -72,10 +72,10 @@ typedef struct { adc_module module; adc_base adc_base; struct { -#ifdef CONFIG_HAS_HPMSDK_ADC12 +#ifdef HPMSOC_HAS_HPMSDK_ADC12 adc12_channel_config_t adc12_ch; #endif -#ifdef CONFIG_HAS_HPMSDK_ADC16 +#ifdef HPMSOC_HAS_HPMSDK_ADC16 adc16_channel_config_t adc16_ch; #endif } config; @@ -89,10 +89,10 @@ typedef struct { adc_module module; adc_base adc_base; struct { -#ifdef CONFIG_HAS_HPMSDK_ADC12 +#ifdef HPMSOC_HAS_HPMSDK_ADC12 adc12_dma_config_t adc12; #endif -#ifdef CONFIG_HAS_HPMSDK_ADC16 +#ifdef HPMSOC_HAS_HPMSDK_ADC16 adc16_dma_config_t adc16; #endif } config; @@ -106,10 +106,10 @@ typedef struct { adc_module module; adc_base adc_base; struct { -#ifdef CONFIG_HAS_HPMSDK_ADC12 +#ifdef HPMSOC_HAS_HPMSDK_ADC12 adc12_prd_config_t adc12; #endif -#ifdef CONFIG_HAS_HPMSDK_ADC16 +#ifdef HPMSOC_HAS_HPMSDK_ADC16 adc16_prd_config_t adc16; #endif } config; @@ -123,10 +123,10 @@ typedef struct { adc_module module; adc_base adc_base; struct { -#ifdef CONFIG_HAS_HPMSDK_ADC12 +#ifdef HPMSOC_HAS_HPMSDK_ADC12 adc12_seq_config_t adc12; #endif -#ifdef CONFIG_HAS_HPMSDK_ADC16 +#ifdef HPMSOC_HAS_HPMSDK_ADC16 adc16_seq_config_t adc16; #endif } config; @@ -140,10 +140,10 @@ typedef struct { adc_module module; adc_base adc_base; struct { -#ifdef CONFIG_HAS_HPMSDK_ADC12 +#ifdef HPMSOC_HAS_HPMSDK_ADC12 adc12_pmt_config_t adc12; #endif -#ifdef CONFIG_HAS_HPMSDK_ADC16 +#ifdef HPMSOC_HAS_HPMSDK_ADC16 adc16_pmt_config_t adc16; #endif } config; @@ -170,11 +170,11 @@ extern "C" { static inline void hpm_adc_init_default_config(adc_config_t *config) { if (config->module == adc_module_adc12) { -#ifdef CONFIG_HAS_HPMSDK_ADC12 +#ifdef HPMSOC_HAS_HPMSDK_ADC12 adc12_get_default_config(&config->config.adc12); #endif } else if (config->module == adc_module_adc16) { -#ifdef CONFIG_HAS_HPMSDK_ADC16 +#ifdef HPMSOC_HAS_HPMSDK_ADC16 adc16_get_default_config(&config->config.adc16); #endif } @@ -189,11 +189,11 @@ static inline void hpm_adc_init_default_config(adc_config_t *config) static inline void hpm_adc_init_channel_default_config(adc_channel_config_t *config) { if (config->module == adc_module_adc12) { -#ifdef CONFIG_HAS_HPMSDK_ADC12 +#ifdef HPMSOC_HAS_HPMSDK_ADC12 adc12_get_channel_default_config(&config->config.adc12_ch); #endif } else if (config->module == adc_module_adc16) { -#ifdef CONFIG_HAS_HPMSDK_ADC16 +#ifdef HPMSOC_HAS_HPMSDK_ADC16 adc16_get_channel_default_config(&config->config.adc16_ch); #endif } @@ -209,13 +209,13 @@ static inline void hpm_adc_init_channel_default_config(adc_channel_config_t *con static inline hpm_stat_t hpm_adc_init(adc_config_t *config) { if (config->module == adc_module_adc12) { -#ifdef CONFIG_HAS_HPMSDK_ADC12 +#ifdef HPMSOC_HAS_HPMSDK_ADC12 return adc12_init(config->adc_base.adc12, &config->config.adc12); #else return status_invalid_argument; #endif } else if (config->module == adc_module_adc16) { -#ifdef CONFIG_HAS_HPMSDK_ADC16 +#ifdef HPMSOC_HAS_HPMSDK_ADC16 return adc16_init(config->adc_base.adc16, &config->config.adc16); #else return status_invalid_argument; @@ -235,13 +235,13 @@ static inline hpm_stat_t hpm_adc_init(adc_config_t *config) static inline hpm_stat_t hpm_adc_channel_init(adc_channel_config_t *config) { if (config->module == adc_module_adc12) { -#ifdef CONFIG_HAS_HPMSDK_ADC12 +#ifdef HPMSOC_HAS_HPMSDK_ADC12 return adc12_init_channel(config->adc_base.adc12, &config->config.adc12_ch); #else return status_invalid_argument; #endif } else if (config->module == adc_module_adc16) { -#ifdef CONFIG_HAS_HPMSDK_ADC16 +#ifdef HPMSOC_HAS_HPMSDK_ADC16 return adc16_init_channel(config->adc_base.adc16, &config->config.adc16_ch); #else return status_invalid_argument; @@ -262,13 +262,13 @@ static inline hpm_stat_t hpm_adc_channel_init(adc_channel_config_t *config) static inline hpm_stat_t hpm_adc_set_period_config(adc_prd_config_t *config) { if (config->module == adc_module_adc12) { -#ifdef CONFIG_HAS_HPMSDK_ADC12 +#ifdef HPMSOC_HAS_HPMSDK_ADC12 return adc12_set_prd_config(config->adc_base.adc12, &config->config.adc12); #else return status_invalid_argument; #endif } else if (config->module == adc_module_adc16) { -#ifdef CONFIG_HAS_HPMSDK_ADC16 +#ifdef HPMSOC_HAS_HPMSDK_ADC16 return adc16_set_prd_config(config->adc_base.adc16, &config->config.adc16); #else return status_invalid_argument; @@ -288,13 +288,13 @@ static inline hpm_stat_t hpm_adc_set_period_config(adc_prd_config_t *config) static inline hpm_stat_t hpm_adc_set_sequence_config(adc_seq_config_t *config) { if (config->module == adc_module_adc12) { -#ifdef CONFIG_HAS_HPMSDK_ADC12 +#ifdef HPMSOC_HAS_HPMSDK_ADC12 return adc12_set_seq_config(config->adc_base.adc12, &config->config.adc12); #else return status_invalid_argument; #endif } else if (config->module == adc_module_adc16) { -#ifdef CONFIG_HAS_HPMSDK_ADC16 +#ifdef HPMSOC_HAS_HPMSDK_ADC16 return adc16_set_seq_config(config->adc_base.adc16, &config->config.adc16); #else return status_invalid_argument; @@ -314,13 +314,13 @@ static inline hpm_stat_t hpm_adc_set_sequence_config(adc_seq_config_t *config) static inline hpm_stat_t hpm_adc_set_preempt_config(adc_pmt_config_t *config) { if (config->module == adc_module_adc12) { -#ifdef CONFIG_HAS_HPMSDK_ADC12 +#ifdef HPMSOC_HAS_HPMSDK_ADC12 return adc12_set_pmt_config(config->adc_base.adc12, &config->config.adc12); #else return status_invalid_argument; #endif } else if (config->module == adc_module_adc16) { -#ifdef CONFIG_HAS_HPMSDK_ADC16 +#ifdef HPMSOC_HAS_HPMSDK_ADC16 return adc16_set_pmt_config(config->adc_base.adc16, &config->config.adc16); #else return status_invalid_argument; @@ -339,11 +339,11 @@ static inline hpm_stat_t hpm_adc_set_preempt_config(adc_pmt_config_t *config) static inline void hpm_adc_set_seq_stop_pos(adc_type *ptr, uint16_t stop_pos) { if (ptr->module == adc_module_adc12) { -#ifdef CONFIG_HAS_HPMSDK_ADC12 +#ifdef HPMSOC_HAS_HPMSDK_ADC12 adc12_set_seq_stop_pos(ptr->adc_base.adc12, stop_pos); #endif } else if (ptr->module == adc_module_adc16) { -#ifdef CONFIG_HAS_HPMSDK_ADC16 +#ifdef HPMSOC_HAS_HPMSDK_ADC16 adc16_set_seq_stop_pos(ptr->adc_base.adc16, stop_pos); #endif } @@ -358,11 +358,11 @@ static inline void hpm_adc_set_seq_stop_pos(adc_type *ptr, uint16_t stop_pos) static inline void hpm_adc_init_pmt_dma(adc_type *ptr, uint32_t addr) { if (ptr->module == adc_module_adc12) { -#ifdef CONFIG_HAS_HPMSDK_ADC12 +#ifdef HPMSOC_HAS_HPMSDK_ADC12 adc12_init_pmt_dma(ptr->adc_base.adc12, addr); #endif } else if (ptr->module == adc_module_adc16) { -#ifdef CONFIG_HAS_HPMSDK_ADC16 +#ifdef HPMSOC_HAS_HPMSDK_ADC16 adc16_init_pmt_dma(ptr->adc_base.adc16, addr); #endif } @@ -376,11 +376,11 @@ static inline void hpm_adc_init_pmt_dma(adc_type *ptr, uint32_t addr) static inline void hpm_adc_init_seq_dma(adc_dma_config_t *config) { if (config->module == adc_module_adc12) { -#ifdef CONFIG_HAS_HPMSDK_ADC12 +#ifdef HPMSOC_HAS_HPMSDK_ADC12 adc12_init_seq_dma(config->adc_base.adc12, &config->config.adc12); #endif } else if (config->module == adc_module_adc16) { -#ifdef CONFIG_HAS_HPMSDK_ADC16 +#ifdef HPMSOC_HAS_HPMSDK_ADC16 adc16_init_seq_dma(config->adc_base.adc16, &config->config.adc16); #endif } @@ -395,11 +395,11 @@ static inline void hpm_adc_init_seq_dma(adc_dma_config_t *config) static inline void hpm_adc_disable_busywait(adc_dma_config_t *config) { if (config->module == adc_module_adc12) { -#ifdef CONFIG_HAS_HPMSDK_ADC12 +#ifdef HPMSOC_HAS_HPMSDK_ADC12 adc12_disable_busywait(config->adc_base.adc12); #endif } else if (config->module == adc_module_adc16) { -#ifdef CONFIG_HAS_HPMSDK_ADC16 +#ifdef HPMSOC_HAS_HPMSDK_ADC16 adc16_disable_busywait(config->adc_base.adc16); #endif } @@ -414,11 +414,11 @@ static inline void hpm_adc_disable_busywait(adc_dma_config_t *config) static inline void hpm_adc_enable_busywait(adc_dma_config_t *config) { if (config->module == adc_module_adc12) { -#ifdef CONFIG_HAS_HPMSDK_ADC12 +#ifdef HPMSOC_HAS_HPMSDK_ADC12 adc12_enable_busywait(config->adc_base.adc12); #endif } else if (config->module == adc_module_adc16) { -#ifdef CONFIG_HAS_HPMSDK_ADC16 +#ifdef HPMSOC_HAS_HPMSDK_ADC16 adc16_enable_busywait(config->adc_base.adc16); #endif } @@ -435,13 +435,13 @@ static inline void hpm_adc_enable_busywait(adc_dma_config_t *config) static inline uint32_t hpm_adc_get_status_flags(adc_type *ptr) { if (ptr->module == adc_module_adc12) { -#ifdef CONFIG_HAS_HPMSDK_ADC12 +#ifdef HPMSOC_HAS_HPMSDK_ADC12 return adc12_get_status_flags(ptr->adc_base.adc12); #else return status_invalid_argument; #endif } else if (ptr->module == adc_module_adc16) { -#ifdef CONFIG_HAS_HPMSDK_ADC16 +#ifdef HPMSOC_HAS_HPMSDK_ADC16 return adc16_get_status_flags(ptr->adc_base.adc16); #else return status_invalid_argument; @@ -463,13 +463,13 @@ static inline uint32_t hpm_adc_get_status_flags(adc_type *ptr) static inline bool hpm_adc_get_conv_valid_status(adc_type *ptr, uint8_t ch) { if (ptr->module == adc_module_adc12) { -#ifdef CONFIG_HAS_HPMSDK_ADC12 +#ifdef HPMSOC_HAS_HPMSDK_ADC12 return adc12_get_conv_valid_status(ptr->adc_base.adc12, ch); #else return status_invalid_argument; #endif } else if (ptr->module == adc_module_adc16) { -#ifdef CONFIG_HAS_HPMSDK_ADC16 +#ifdef HPMSOC_HAS_HPMSDK_ADC16 return adc16_get_conv_valid_status(ptr->adc_base.adc16, ch); #else return status_invalid_argument; @@ -490,11 +490,11 @@ static inline bool hpm_adc_get_conv_valid_status(adc_type *ptr, uint8_t ch) static inline void hpm_adc_clear_status_flags(adc_type *ptr, uint32_t mask) { if (ptr->module == adc_module_adc12) { -#ifdef CONFIG_HAS_HPMSDK_ADC12 +#ifdef HPMSOC_HAS_HPMSDK_ADC12 adc12_clear_status_flags(ptr->adc_base.adc12, mask); #endif } else if (ptr->module == adc_module_adc16) { -#ifdef CONFIG_HAS_HPMSDK_ADC16 +#ifdef HPMSOC_HAS_HPMSDK_ADC16 adc16_clear_status_flags(ptr->adc_base.adc16, mask); #endif } @@ -509,11 +509,11 @@ static inline void hpm_adc_clear_status_flags(adc_type *ptr, uint32_t mask) static inline void hpm_adc_enable_interrupts(adc_type *ptr, uint32_t mask) { if (ptr->module == adc_module_adc12) { -#ifdef CONFIG_HAS_HPMSDK_ADC12 +#ifdef HPMSOC_HAS_HPMSDK_ADC12 adc12_enable_interrupts(ptr->adc_base.adc12, mask); #endif } else if (ptr->module == adc_module_adc16) { -#ifdef CONFIG_HAS_HPMSDK_ADC16 +#ifdef HPMSOC_HAS_HPMSDK_ADC16 adc16_enable_interrupts(ptr->adc_base.adc16, mask); #endif } @@ -528,11 +528,11 @@ static inline void hpm_adc_enable_interrupts(adc_type *ptr, uint32_t mask) static inline void hpm_adc_disable_interrupts(adc_type *ptr, uint32_t mask) { if (ptr->module == adc_module_adc12) { -#ifdef CONFIG_HAS_HPMSDK_ADC12 +#ifdef HPMSOC_HAS_HPMSDK_ADC12 adc12_disable_interrupts(ptr->adc_base.adc12, mask); #endif } else if (ptr->module == adc_module_adc16) { -#ifdef CONFIG_HAS_HPMSDK_ADC16 +#ifdef HPMSOC_HAS_HPMSDK_ADC16 adc16_disable_interrupts(ptr->adc_base.adc16, mask); #endif } @@ -551,13 +551,13 @@ static inline void hpm_adc_disable_interrupts(adc_type *ptr, uint32_t mask) static inline hpm_stat_t hpm_adc_get_oneshot_result(adc_type *ptr, uint8_t ch, uint16_t *result) { if (ptr->module == adc_module_adc12) { -#ifdef CONFIG_HAS_HPMSDK_ADC12 +#ifdef HPMSOC_HAS_HPMSDK_ADC12 return adc12_get_oneshot_result(ptr->adc_base.adc12, ch, result); #else return status_invalid_argument; #endif } else if (ptr->module == adc_module_adc16) { -#ifdef CONFIG_HAS_HPMSDK_ADC16 +#ifdef HPMSOC_HAS_HPMSDK_ADC16 return adc16_get_oneshot_result(ptr->adc_base.adc16, ch, result); #else return status_invalid_argument; @@ -580,13 +580,13 @@ static inline hpm_stat_t hpm_adc_get_oneshot_result(adc_type *ptr, uint8_t ch, u static inline hpm_stat_t hpm_adc_get_prd_result(adc_type *ptr, uint8_t ch, uint16_t *result) { if (ptr->module == adc_module_adc12) { -#ifdef CONFIG_HAS_HPMSDK_ADC12 +#ifdef HPMSOC_HAS_HPMSDK_ADC12 return adc12_get_prd_result(ptr->adc_base.adc12, ch, result); #else return status_invalid_argument; #endif } else if (ptr->module == adc_module_adc16) { -#ifdef CONFIG_HAS_HPMSDK_ADC16 +#ifdef HPMSOC_HAS_HPMSDK_ADC16 return adc16_get_prd_result(ptr->adc_base.adc16, ch, result); #else return status_invalid_argument; @@ -605,11 +605,11 @@ static inline hpm_stat_t hpm_adc_get_prd_result(adc_type *ptr, uint8_t ch, uint1 static inline hpm_stat_t hpm_adc_trigger_seq_by_sw(adc_type *ptr) { if (ptr->module == adc_module_adc12) { -#ifdef CONFIG_HAS_HPMSDK_ADC12 +#ifdef HPMSOC_HAS_HPMSDK_ADC12 return adc12_trigger_seq_by_sw(ptr->adc_base.adc12); #endif } else if (ptr->module == adc_module_adc16) { -#ifdef CONFIG_HAS_HPMSDK_ADC16 +#ifdef HPMSOC_HAS_HPMSDK_ADC16 return adc16_trigger_seq_by_sw(ptr->adc_base.adc16); #endif } else { diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/hpm_camera_config.h b/bsp/hpmicro/libraries/hpm_sdk/components/camera/hpm_camera_config.h index c40b4fe37fb..77872164d94 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/camera/hpm_camera_config.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/camera/hpm_camera_config.h @@ -28,6 +28,12 @@ typedef struct { bool vsync_active_low; } camera_param_dvp_t; +typedef struct { + bool de_active_low; + bool hsync_active_low; + bool vsync_active_low; +} camera_param_mipi_t; + typedef enum { camera_interface_dvp, camera_interface_mipi, @@ -85,6 +91,8 @@ extern "C" { */ hpm_stat_t camera_device_init(camera_context_t *camera_context, camera_config_t *camera_config); hpm_stat_t camera_device_get_dvp_param(camera_context_t *camera_context, camera_config_t *camera_config); +hpm_stat_t camera_device_get_mipi_param(camera_context_t *camera_context, camera_config_t *camera_config); + #ifdef __cplusplus } #endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_camera_ov5640.c b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_camera_ov5640.c index 5832531c9e5..b9d0b675b35 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_camera_ov5640.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_camera_ov5640.c @@ -12,16 +12,20 @@ static camera_param_dvp_t camera_dvp_param = { .vsync_active_low = false, }; +static camera_param_mipi_t camera_mipi_param = { + .de_active_low = true, + .hsync_active_low = false, + .vsync_active_low = false, +}; + hpm_stat_t camera_device_init(camera_context_t *camera_context, camera_config_t *camera_config) { assert(camera_context->delay_ms != NULL); hpm_stat_t stat = status_success; -#ifdef HPM_CAM_EXECUTE_POWER_UP_SEQUENCE /* execute power up sequence */ ov5640_power_up(camera_context); -#endif /* software reset */ stat = ov5640_software_reset(camera_context); @@ -37,6 +41,14 @@ hpm_stat_t camera_device_init(camera_context_t *camera_context, camera_config_t hpm_stat_t camera_device_get_dvp_param(camera_context_t *camera_context, camera_config_t *camera_config) { + (void)camera_context; camera_config->interface_param = (void *)&camera_dvp_param; return status_success; } + +hpm_stat_t camera_device_get_mipi_param(camera_context_t *camera_context, camera_config_t *camera_config) +{ + (void)camera_context; + camera_config->interface_param = (void *)&camera_mipi_param; + return status_success; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_ov5640.c b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_ov5640.c index 30c195c2d53..d6996143b57 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_ov5640.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_ov5640.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -8,12 +8,23 @@ #include "hpm_ov5640.h" static const ov5640_reg_val_t ov5640_init_param[] = { - /* system setting */ - {0x3008, 0x42}, /* software power down, bit[6] */ - {0x3103, 0x03}, /* system clock from PLL, bit[1] */ - {0x3037, 0x13}, /* PLL root divider, bit[4], PLL pre-divider, bit[3:0] */ - {0x3108, 0x01}, /* PCLK root divider, bit[5:4], SCLK2x root divider, bit[3:2], SCLK root divider, bit[1:0] */ - + {0x3008, 0x42}, + /* System setting. */ + {0x3103, 0x03}, + {0x3000, 0x00}, + {0x3004, 0xff}, + {0x3002, 0x1c}, + {0x3006, 0xc3}, + {0x302e, 0x08}, + {0x3037, 0x13}, + {0x3108, 0x01}, + {0x3618, 0x00}, + {0x3612, 0x29}, + {0x3708, 0x64}, + {0x3709, 0x52}, + {0x370c, 0x03}, + {0x3820, 0x41}, + {0x3821, 0x07}, {0x3630, 0x36}, {0x3631, 0x0e}, {0x3632, 0xe2}, @@ -21,24 +32,6 @@ static const ov5640_reg_val_t ov5640_init_param[] = { {0x3621, 0xe0}, {0x3704, 0xa0}, {0x3703, 0x5a}, - - {0x302c, 0xc2}, /* pad control */ - {0x4004, 0x02}, /* BLC 2 lines */ - {0x3002, 0x1c}, /* reset JFIFO, SFIFO, JPEG */ - {0x3006, 0xc3}, /* disable clock of JPEG2x, JPEG */ - {0x4713, 0x03}, /* JPEG mode 3 */ - {0x4407, 0x04}, /* Quantization scale */ - {0x460b, 0x35}, - {0x5001, 0xa3}, /* SDE on, scale on, UV average off, color matrix on, AWB on */ - {0x3503, 0x00}, /* AEC/AGC on */ - {0x3c07, 0x08}, /* light meter 1 threshold [7:0] */ - {0x3820, 0x41}, /* Sensor flip off, ISP flip on */ - {0x3821, 0x07}, /* Sensor mirror on, ISP mirror on, H binning on */ - {0x3618, 0x00}, - {0x3612, 0x29}, - {0x3709, 0x52}, - {0x370c, 0x03}, - {0x3715, 0x78}, {0x3717, 0x01}, {0x370b, 0x60}, @@ -47,49 +40,122 @@ static const ov5640_reg_val_t ov5640_init_param[] = { {0x3906, 0x10}, {0x3901, 0x0a}, {0x3731, 0x12}, - {0x3600, 0x08}, /* VCM control */ - {0x3601, 0x33}, /* VCM control */ - {0x302d, 0x60}, /* system control */ + {0x3600, 0x08}, + {0x3601, 0x33}, + {0x302d, 0x60}, {0x3620, 0x52}, {0x371b, 0x20}, {0x471c, 0x50}, - {0x3a13, 0x43}, /* pre-gain = 1.047x */ - {0x3a18, 0x00}, /* gain ceiling */ - {0x3a19, 0xf8}, /* gain ceiling = 15.5x */ + {0x3a13, 0x43}, + {0x3a18, 0x00}, + {0x3a19, 0x7c}, {0x3635, 0x13}, {0x3636, 0x03}, {0x3634, 0x40}, {0x3622, 0x01}, - /* 50/60Hz detection */ - {0x3a02, 0x0b}, /* 60Hz max exposure, night mode 5fps */ - {0x3a03, 0x88}, /* 60Hz max exposure */ - {0x3a14, 0x0b}, /* 50Hz max exposure, night mode 5fps */ - {0x3a15, 0x88}, /* 50Hz max exposure */ - {0x3c01, 0x34}, /* Band auto, bit[7] */ - {0x3c04, 0x28}, /* threshold low sum */ - {0x3c05, 0x98}, /* threshold high sum */ - {0x3c06, 0x00}, /* light meter 1 threshold[15:8] */ - {0x3c07, 0x08}, /* light meter 1 threshold[7:0] */ - {0x3c08, 0x00}, /* light meter 2 threshold[15:8] */ - {0x3c09, 0x1c}, /* light meter 2 threshold[7:0] */ - {0x3c0a, 0x9c}, /* sample number[15:8] */ - {0x3c0b, 0x40}, /* sample number[7:0] */ - {0x3708, 0x64}, - {0x4001, 0x02}, /* BLC start from line 2 */ - {0x4005, 0x1a}, /* BLC always update */ - {0x3000, 0x00}, /* enable blocks */ - {0x3004, 0xff}, /* enable clocks */ - {0x302e, 0x00}, - {0x440e, 0x00}, - {0x5000, 0xa7}, /* Lenc on, raw gamma on, BPC on, WPC on, CIP on */ - /* AEC target */ - {0x3a0f, 0x30}, /* stable range in high */ - {0x3a10, 0x28}, /* stable range in low */ - {0x3a1b, 0x30}, /* stable range out high */ - {0x3a1e, 0x26}, /* stable range out low */ - {0x3a11, 0x60}, /* fast zone high */ - {0x3a1f, 0x14}, /* fast zone low */ - /* Lens correction */ + {0x3c01, 0x00}, + {0x3a00, 0x58}, + {0x4001, 0x02}, + {0x4004, 0x02}, + {0x4005, 0x1a}, + {0x5001, 0xa3}, + + /* AEC */ + {0x3a0f, 0x30}, + {0x3a10, 0x28}, + {0x3a1b, 0x30}, + {0x3a1e, 0x26}, + {0x3a11, 0x60}, + {0x3a1f, 0x14}, + + /* AWB */ + {0x5180, 0xff}, + {0x5181, 0xf2}, + {0x5182, 0x00}, + {0x5183, 0x14}, + {0x5184, 0x25}, + {0x5185, 0x24}, + {0x5186, 0x09}, + {0x5187, 0x09}, + {0x5188, 0x09}, + {0x5189, 0x88}, + {0x518a, 0x54}, + {0x518b, 0xee}, + {0x518c, 0xb2}, + {0x518d, 0x50}, + {0x518e, 0x34}, + {0x518f, 0x6b}, + {0x5190, 0x46}, + {0x5191, 0xf8}, + {0x5192, 0x04}, + {0x5193, 0x70}, + {0x5194, 0xf0}, + {0x5195, 0xf0}, + {0x5196, 0x03}, + {0x5197, 0x01}, + {0x5198, 0x04}, + {0x5199, 0x6c}, + {0x519a, 0x04}, + {0x519b, 0x00}, + {0x519c, 0x09}, + {0x519d, 0x2b}, + {0x519e, 0x38}, + + /* Color Matrix */ + {0x5381, 0x1e}, + {0x5382, 0x5b}, + {0x5383, 0x08}, + {0x5384, 0x0a}, + {0x5385, 0x7e}, + {0x5386, 0x88}, + {0x5387, 0x7c}, + {0x5388, 0x6c}, + {0x5389, 0x10}, + {0x538a, 0x01}, + {0x538b, 0x98}, + + /* sharp */ + {0x5300, 0x08}, + {0x5301, 0x30}, + {0x5302, 0x10}, + {0x5303, 0x00}, + {0x5304, 0x08}, + {0x5305, 0x30}, + {0x5306, 0x08}, + {0x5307, 0x16}, + {0x5309, 0x08}, + {0x530a, 0x30}, + {0x530b, 0x04}, + {0x530c, 0x06}, + + /* Gamma */ + {0x5480, 0x01}, + {0x5481, 0x08}, + {0x5482, 0x14}, + {0x5483, 0x28}, + {0x5484, 0x51}, + {0x5485, 0x65}, + {0x5486, 0x71}, + {0x5487, 0x7d}, + {0x5488, 0x87}, + {0x5489, 0x91}, + {0x548a, 0x9a}, + {0x548b, 0xaa}, + {0x548c, 0xb8}, + {0x548d, 0xcd}, + {0x548e, 0xdd}, + {0x548f, 0xea}, + {0x5490, 0x1d}, + + /* UV adjust. */ + {0x5580, 0x02}, + {0x5583, 0x40}, + {0x5584, 0x10}, + {0x5589, 0x10}, + {0x558a, 0x00}, + {0x558b, 0xf8}, + + /* Lens correction. */ {0x5800, 0x23}, {0x5801, 0x14}, {0x5802, 0x0f}, @@ -151,94 +217,32 @@ static const ov5640_reg_val_t ov5640_init_param[] = { {0x583a, 0x26}, {0x583b, 0x28}, {0x583c, 0x42}, - {0x583d, 0xce}, /* lenc BR offset */ - /* AWB */ - {0x5180, 0xff}, /* AWB B block */ - {0x5181, 0xf2}, /* AWB control */ - {0x5182, 0x00}, /* [7:4] max local counter, [3:0] max fast counter */ - {0x5183, 0x14}, /* AWB advanced */ - {0x5184, 0x25}, - {0x5185, 0x24}, - {0x5186, 0x09}, - {0x5187, 0x09}, - {0x5188, 0x09}, - {0x5189, 0x75}, - {0x518a, 0x54}, - {0x518b, 0xe0}, - {0x518c, 0xb2}, - {0x518d, 0x42}, - {0x518e, 0x3d}, - {0x518f, 0x56}, - {0x5190, 0x46}, - {0x5191, 0xf8}, /* AWB top limit */ - {0x5192, 0x04}, /* AWB bottom limit */ - {0x5193, 0x70}, /* red limit */ - {0x5194, 0xf0}, /* green limit */ - {0x5195, 0xf0}, /* blue limit */ - {0x5196, 0x03}, /* AWB control */ - {0x5197, 0x01}, /* local limit */ - {0x5198, 0x04}, - {0x5199, 0x12}, - {0x519a, 0x04}, - {0x519b, 0x00}, - {0x519c, 0x06}, - {0x519d, 0x82}, - {0x519e, 0x38}, /* AWB control */ + {0x583d, 0xce}, + {0x481c, 0x00}, + {0x481d, 0x1}, - /* Gamma */ - {0x5480, 0x01}, /* Gamma bias plus on, bit[0] */ - {0x5481, 0x08}, - {0x5482, 0x14}, - {0x5483, 0x28}, - {0x5484, 0x51}, - {0x5485, 0x65}, - {0x5486, 0x71}, - {0x5487, 0x7d}, - {0x5488, 0x87}, - {0x5489, 0x91}, - {0x548a, 0x9a}, - {0x548b, 0xaa}, - {0x548c, 0xb8}, - {0x548d, 0xcd}, - {0x548e, 0xdd}, - {0x548f, 0xea}, - {0x5490, 0x1d}, - /* color matrix */ - {0x5381, 0x1e}, /* CMX1 for Y */ - {0x5382, 0x5b}, /* CMX2 for Y */ - {0x5383, 0x08}, /* CMX3 for Y */ - {0x5384, 0x0a}, /* CMX4 for U */ - {0x5385, 0x7e}, /* CMX5 for U */ - {0x5386, 0x88}, /* CMX6 for U */ - {0x5387, 0x7c}, /* CMX7 for V */ - {0x5388, 0x6c}, /* CMX8 for V */ - {0x5389, 0x10}, /* CMX9 for V */ - {0x538a, 0x01}, /* sign[9] */ - {0x538b, 0x98}, /* sign[8:1] */ - /* UV adjust */ - {0x5580, 0x06}, /* saturation on, bit[1] */ - {0x5583, 0x40}, - {0x5584, 0x10}, - {0x5003, 0x08}, - {0x5589, 0x10}, - {0x558a, 0x00}, - {0x558b, 0xf8}, - {0x501d, 0x40}, /* enable manual offset of contrast */ - /* CIP */ - {0x5300, 0x08}, /* CIP sharpen MT threshold 1 */ - {0x5301, 0x30}, /* CIP sharpen MT threshold 2 */ - {0x5302, 0x10}, /* CIP sharpen MT offset 1 */ - {0x5303, 0x00}, /* CIP sharpen MT offset 2 */ - {0x5304, 0x08}, /* CIP DNS threshold 1 */ - {0x5305, 0x30}, /* CIP DNS threshold 2 */ - {0x5306, 0x08}, /* CIP DNS offset 1 */ - {0x5307, 0x16}, /* CIP DNS offset 2 */ - {0x5309, 0x08}, /* CIP sharpen TH threshold 1 */ - {0x530a, 0x30}, /* CIP sharpen TH threshold 2 */ - {0x530b, 0x04}, /* CIP sharpen TH offset 1 */ - {0x530c, 0x06}, /* CIP sharpen TH offset 2 */ - {0x5025, 0x00}, - {0x3008, 0x02}, /* wake up from standby, bit[6] */ + /* 50/60Hz detection */ + {0x3a02, 0x0b}, /* 60Hz max exposure, night mode 5fps */ + {0x3a03, 0x88}, /* 60Hz max exposure */ + {0x3a14, 0x0b}, /* 50Hz max exposure, night mode 5fps */ + {0x3a15, 0x88}, /* 50Hz max exposure */ + {0x3c01, 0x34}, /* Band auto, bit[7] */ + {0x3c04, 0x28}, /* threshold low sum */ + {0x3c05, 0x98}, /* threshold high sum */ + {0x3c06, 0x00}, /* light meter 1 threshold[15:8] */ + {0x3c07, 0x08}, /* light meter 1 threshold[7:0] */ + {0x3c08, 0x00}, /* light meter 2 threshold[15:8] */ + {0x3c09, 0x1c}, /* light meter 2 threshold[7:0] */ + {0x3c0a, 0x9c}, /* sample number[15:8] */ + {0x3c0b, 0x40}, /* sample number[7:0] */ + {0x3708, 0x64}, + {0x4001, 0x02}, /* BLC start from line 2 */ + {0x4005, 0x1a}, /* BLC always update */ + {0x3000, 0x00}, /* enable blocks */ + {0x3004, 0xff}, /* enable clocks */ + {0x302e, 0x00}, + {0x440e, 0x00}, + {0x5000, 0xa7}, /* Lenc on, raw gamma on, BPC on, WPC on, CIP on */ }; /* Resolution configuration */ @@ -342,6 +346,58 @@ static const ov5640_clock_config_t ov5640_dvp_clock_configs[] = { }, }; +/* MIPI clock */ +static const ov5640_clock_config_t ov5640_mipi_clock_configs[] = { + { + .resolution = (uint32_t)video_resolution_800_480, + .pllctrl1 = 0x14, + .pllctrl2 = 0x38, + .vfifoctrl0c = 0x22, + .pclkdiv = 0x02, + .pclkperiod = 0x0a, + }, + { + .resolution = (uint32_t)video_resolution_vga, + .pllctrl1 = 0x14, + .pllctrl2 = 0x38, + .vfifoctrl0c = 0x22, + .pclkdiv = 0x02, + .pclkperiod = 0x0a, + }, + { + .resolution = (uint32_t)video_resolution_qvga, + .pllctrl1 = 0x14, + .pllctrl2 = 0x38, + .vfifoctrl0c = 0x22, + .pclkdiv = 0x02, + .pclkperiod = 0x0a, + }, + { + .resolution = (uint32_t)video_resolution_480_272, + .pllctrl1 = 0x14, + .pllctrl2 = 0x38, + .vfifoctrl0c = 0x22, + .pclkdiv = 0x02, + .pclkperiod = 0x0a, + }, + { + .resolution = (uint32_t)video_resolution_720p, + .pllctrl1 = 0x21, + .pllctrl2 = 0x54, + .vfifoctrl0c = 0x20, + .pclkdiv = 0x04, + .pclkperiod = 0x0a, + }, + { + .resolution = (uint32_t)video_resolution_1080p, + .pllctrl1 = 0x11, + .pllctrl2 = 0x54, + .vfifoctrl0c = 0x20, + .pclkdiv = 0x04, + .pclkperiod = 0x0a, + }, +}; + static const ov5640_light_mode_config_t ov5640_light_mode_configs[] = { /* Auto. */ { @@ -462,6 +518,12 @@ static const ov5640_clock_config_t *ov5640_get_clock_config(const camera_config_ return &ov5640_dvp_clock_configs[i]; } } + } else if (camera_interface_mipi == config->interface) { + for (i = 0; i < ARRAY_SIZE(ov5640_mipi_clock_configs); i++) { + if (HPM_CAMERA_RESOLUTION(config->width, config->height) == ov5640_mipi_clock_configs[i].resolution) { + return &ov5640_mipi_clock_configs[i]; + } + } } return NULL; @@ -520,6 +582,10 @@ hpm_stat_t ov5640_set_pixel_format(camera_context_t *context, display_pixel_form HPM_CHECK_RET(ov5640_write_register(context, 0x4300, 0x30)); HPM_CHECK_RET(ov5640_write_register(context, 0x501f, 0x00)); break; + case display_pixel_format_ycbcr422: + HPM_CHECK_RET(ov5640_write_register(context, 0x4300, 0x32)); + HPM_CHECK_RET(ov5640_write_register(context, 0x501f, 0x00)); + break; case display_pixel_format_rgb565: HPM_CHECK_RET(ov5640_write_register(context, 0x4300, 0x6F)); HPM_CHECK_RET(ov5640_write_register(context, 0x501f, 0x01)); @@ -614,6 +680,17 @@ hpm_stat_t ov5640_set_interface(camera_context_t *context, camera_config_t *ov_c /* DVP mode */ HPM_CHECK_RET(ov5640_write_register(context, 0x300e, 0x58)); + } else if (camera_interface_mipi == ov_config->interface) { + HPM_CHECK_RET(ov5640_write_register(context, 0x481D, 0x20)); + HPM_CHECK_RET(ov5640_write_register(context, 0x481C, 0x0)); + HPM_CHECK_RET(ov5640_write_register(context, 0x3034, 0x18)); + HPM_CHECK_RET(ov5640_write_register(context, 0x3017, 0x00)); + HPM_CHECK_RET(ov5640_write_register(context, 0x3018, 0x00)); + /* 2lanes mode */ + HPM_CHECK_RET(ov5640_write_register(context, 0x300e, 0x45)); + HPM_CHECK_RET(ov5640_write_register(context, 0x302e, 0x08)); + + HPM_CHECK_RET(ov5640_write_register(context, 0x4800, 0x04)); } return stat; @@ -798,13 +875,21 @@ hpm_stat_t ov5640_init(camera_context_t *context, camera_config_t *ov_config) void ov5640_power_up(camera_context_t *context) { - assert((context->delay_ms != NULL) && (context->write_rst != NULL) && (context->write_pwdn != NULL)); + assert(context->delay_ms != NULL); - context->write_rst(OV5640_RST_ACTIVE); - context->write_pwdn(OV5640_PWDN_ACTIVE); + if (context->write_rst) { + context->write_rst(OV5640_RST_ACTIVE); + } + if (context->write_pwdn) { + context->write_pwdn(OV5640_PWDN_ACTIVE); + } context->delay_ms(5); - context->write_pwdn(OV5640_PWDN_INACTIVE); + if (context->write_pwdn) { + context->write_pwdn(OV5640_PWDN_INACTIVE); + } context->delay_ms(2); - context->write_rst(OV5640_RST_INACTIVE); + if (context->write_rst) { + context->write_rst(OV5640_RST_INACTIVE); + } context->delay_ms(20); } diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_camera_ov7725.c b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_camera_ov7725.c index f140ad2c6bd..1c436b7280b 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_camera_ov7725.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_camera_ov7725.c @@ -18,10 +18,8 @@ hpm_stat_t camera_device_init(camera_context_t *camera_context, camera_config_t hpm_stat_t stat = status_success; -#ifdef HPM_CAM_EXECUTE_POWER_UP_SEQUENCE /* execute power up sequence */ ov7725_power_up(camera_context); -#endif /* software reset */ stat = ov7725_software_reset(camera_context); @@ -37,6 +35,7 @@ hpm_stat_t camera_device_init(camera_context_t *camera_context, camera_config_t hpm_stat_t camera_device_get_dvp_param(camera_context_t *camera_context, camera_config_t *camera_config) { + (void)camera_context; camera_config->interface_param = (void *)&camera_dvp_param; return status_success; } diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_ov7725.c b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_ov7725.c index 675fab0a5ce..8e6c09f4e22 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_ov7725.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_ov7725.c @@ -334,13 +334,21 @@ hpm_stat_t ov7725_init(camera_context_t *context, camera_config_t *ov_config) void ov7725_power_up(camera_context_t *context) { - assert((context->delay_ms != NULL) && (context->write_rst != NULL) && (context->write_pwdn != NULL)); + assert(context->delay_ms != NULL); - context->write_rst(OV7725_RST_ACTIVE); - context->write_pwdn(OV7725_PWDN_ACTIVE); + if (context->write_rst) { + context->write_rst(OV7725_RST_ACTIVE); + } + if (context->write_pwdn) { + context->write_pwdn(OV7725_PWDN_ACTIVE); + } context->delay_ms(5); - context->write_pwdn(OV7725_PWDN_INACTIVE); + if (context->write_pwdn) { + context->write_pwdn(OV7725_PWDN_INACTIVE); + } context->delay_ms(2); - context->write_rst(OV7725_RST_INACTIVE); + if (context->write_rst) { + context->write_rst(OV7725_RST_INACTIVE); + } context->delay_ms(20); } diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/codec/sgtl5000/hpm_sgtl5000.c b/bsp/hpmicro/libraries/hpm_sdk/components/codec/sgtl5000/hpm_sgtl5000.c index 46d00683069..64dcd75d880 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/codec/sgtl5000/hpm_sgtl5000.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/codec/sgtl5000/hpm_sgtl5000.c @@ -426,6 +426,15 @@ hpm_stat_t sgtl_set_mute(sgtl_context_t *context, sgtl_module_t module, bool mut return stat; } +static bool sgtl_check_clock_tolerance(uint32_t source, uint32_t target) +{ + uint32_t delta = (source >= target) ? (source - target) : (target - source); + if (delta * 100 <= HPM_SGTL5000_MCLK_TOLERANCE * target) { + return true; + } + return false; +} + hpm_stat_t sgtl_config_data_format(sgtl_context_t *context, uint32_t mclk, uint32_t sample_rate, uint32_t bits) { uint16_t val = 0; @@ -515,11 +524,12 @@ hpm_stat_t sgtl_config_data_format(sgtl_context_t *context, uint32_t mclk, uint3 } mul_div = mclk / sysFs; - if (abs(mul_div - 256) <= 256 * HPM_SGTL5000_MCLK_TOLERANCE) { + + if (sgtl_check_clock_tolerance(mul_div, 256)) { mul_div = 256; - } else if (abs(mul_div - 384) <= 384 * HPM_SGTL5000_MCLK_TOLERANCE) { + } else if (sgtl_check_clock_tolerance(mul_div, 384)) { mul_div = 384; - } else if (abs(mul_div - 512) <= 512 * HPM_SGTL5000_MCLK_TOLERANCE) { + } else if (sgtl_check_clock_tolerance(mul_div, 512)) { mul_div = 512; } else { return status_invalid_argument; diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/codec/sgtl5000/hpm_sgtl5000.h b/bsp/hpmicro/libraries/hpm_sdk/components/codec/sgtl5000/hpm_sgtl5000.h index 96e676b30eb..dbf146933ed 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/codec/sgtl5000/hpm_sgtl5000.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/codec/sgtl5000/hpm_sgtl5000.h @@ -836,7 +836,7 @@ typedef struct _sgtl_config { } sgtl_config_t; typedef struct { - I2C_Type *ptr;; /*!< sgtl I2C pointer */ + I2C_Type *ptr; /*!< sgtl I2C pointer */ uint8_t slave_address; /*!< code device slave address */ } sgtl_context_t; diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960.c b/bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960.c index d4a7e86037e..25493d1289d 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960.c @@ -52,6 +52,9 @@ hpm_stat_t wm8960_init(wm8960_control_t *control, wm8960_config_t *config) /* set wm8960 as slave */ HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_MS_MASK, WM8960_IFACE1_MS_SET(0))); + /* invert LRCLK */ + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_LRP_MASK, WM8960_IFACE1_LRP_SET(1))); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ADDCTL1, 0xC0)); HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ADDCTL4, 0x40)); @@ -401,41 +404,36 @@ hpm_stat_t wm8960_set_volume(wm8960_control_t *control, wm8960_module_t module, return stat; } +static bool wm8960_check_clock_tolerance(uint32_t source, uint32_t target) +{ + uint32_t delta = (source >= target) ? (source - target) : (target - source); + if (delta * 100 <= HPM_WM8960_MCLK_TOLERANCE * target) { + return true; + } + return false; +} + hpm_stat_t wm8960_set_data_format(wm8960_control_t *control, uint32_t sysclk, uint32_t sample_rate, uint32_t bits) { hpm_stat_t stat = status_success; - uint32_t divider = 0; - uint16_t val = 0; + uint16_t val = 0; + uint32_t ratio[7] = {256, 256 * 1.5, 256 * 2, 256 * 3, 256 * 4, 256 * 5.5, 256 * 6}; + bool clock_meet_requirement = false; - /* Compute sample rate divider and SYSCLK Pre-divider, dac and adc are the same sample rate */ - divider = sysclk / sample_rate; + if (sysclk / sample_rate > 256 * 6) { + sysclk = sysclk / 2; + val = WM8960_CLOCK1_SYSCLKDIV_SET(2U); /* SYSCLK Pre-divider */ + } - if (divider > 6 * 512 * HPM_WM8960_MCLK_TOLERANCE / 100 + 6 * 512) { - divider = divider / 2; /* SYSCLK Pre-divider */ - val |= WM8960_CLOCK1_SYSCLKDIV_SET(2U); + for (uint8_t i = 0; i < 7; i++) { + if (wm8960_check_clock_tolerance(sysclk, sample_rate * ratio[i])) { + val |= ((i << WM8960_CLOCK1_ADCDIV_SHIFT) | (i << WM8960_CLOCK1_DACDIV_SHIFT)); + clock_meet_requirement = true; + break; + } } - if (abs(divider - 256) <= 256 * HPM_WM8960_MCLK_TOLERANCE) { - divider = 256; - } else if (abs(divider - 256 * 1.5) <= 256 * 1.5 * HPM_WM8960_MCLK_TOLERANCE) { - divider = 256 * 1.5; - val |= ((1 << WM8960_CLOCK1_ADCDIV_SHIFT) | (1 << WM8960_CLOCK1_DACDIV_SHIFT)); - } else if (abs(divider - 256 * 2) <= 256 * 2 * HPM_WM8960_MCLK_TOLERANCE) { - divider = 256 * 2; - val |= ((2 << WM8960_CLOCK1_ADCDIV_SHIFT) | (2 << WM8960_CLOCK1_DACDIV_SHIFT)); - } else if (abs(divider - 256 * 3) <= 256 * 3 * HPM_WM8960_MCLK_TOLERANCE) { - divider = 256 * 3; - val |= ((3 << WM8960_CLOCK1_ADCDIV_SHIFT) | (3 << WM8960_CLOCK1_DACDIV_SHIFT)); - } else if (abs(divider - 256 * 4) <= 256 * 4 * HPM_WM8960_MCLK_TOLERANCE) { - divider = 256 * 4; - val |= ((4 << WM8960_CLOCK1_ADCDIV_SHIFT) | (4 << WM8960_CLOCK1_DACDIV_SHIFT)); - } else if (abs(divider - 256 * 5.5) <= 256 * 5.5 * HPM_WM8960_MCLK_TOLERANCE) { - divider = 256 * 5.5; - val |= ((5 << WM8960_CLOCK1_ADCDIV_SHIFT) | (5 << WM8960_CLOCK1_DACDIV_SHIFT)); - } else if (abs(divider - 256 * 6) <= 256 * 6 * HPM_WM8960_MCLK_TOLERANCE) { - divider = 256 * 6; - val |= ((6 << WM8960_CLOCK1_ADCDIV_SHIFT) | (6 << WM8960_CLOCK1_DACDIV_SHIFT)); - } else { + if (!clock_meet_requirement) { return status_invalid_argument; } HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_CLOCK1, 0x1FEU, val)); diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960.h b/bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960.h index 10d4be18e20..6b85407368c 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960.h @@ -81,7 +81,7 @@ typedef struct wm8960_config { } wm8960_config_t; typedef struct { - I2C_Type *ptr;; /* I2C bus */ + I2C_Type *ptr; /* I2C bus */ uint8_t slave_address; /* code device address */ } wm8960_control_t; diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/debug_console/hpm_debug_console.c b/bsp/hpmicro/libraries/hpm_sdk/components/debug_console/hpm_debug_console.c index ac79d814444..d23935db9c6 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/debug_console/hpm_debug_console.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/debug_console/hpm_debug_console.c @@ -5,7 +5,9 @@ * */ +#ifndef __ICCRISCV__ #include +#endif #include "hpm_debug_console.h" #include "hpm_uart_drv.h" @@ -61,7 +63,7 @@ FILE *stderr = &__SEGGER_RTL_stderr_file; /* NOTE: Provide implementation of std int __SEGGER_RTL_X_file_write(__SEGGER_RTL_FILE *file, const char *data, unsigned int size) { - int count; + unsigned int count; (void)file; for (count = 0; count < size; count++) { if (data[count] == '\n') { @@ -80,6 +82,7 @@ int __SEGGER_RTL_X_file_write(__SEGGER_RTL_FILE *file, const char *data, unsigne int __SEGGER_RTL_X_file_read(__SEGGER_RTL_FILE *file, char *s, unsigned int size) { (void)file; + (void) size; while (status_success != uart_receive_byte(g_console_uart, (uint8_t *)s)) { } return 1; @@ -87,11 +90,13 @@ int __SEGGER_RTL_X_file_read(__SEGGER_RTL_FILE *file, char *s, unsigned int size int __SEGGER_RTL_X_file_stat(__SEGGER_RTL_FILE *stream) { + (void) stream; return 0; } int __SEGGER_RTL_X_file_bufsize(__SEGGER_RTL_FILE *stream) { + (void) stream; return 1; } @@ -111,6 +116,7 @@ int __SEGGER_RTL_X_file_unget(__SEGGER_RTL_FILE *stream, int c) int __SEGGER_RTL_X_file_flush(__SEGGER_RTL_FILE *__stream) { + (void) __stream; return 1; } @@ -136,13 +142,32 @@ int _write(int file, char *data, int size) int _read(int file, char *s, int size) { (void)file; + (void) size; while (status_success != uart_receive_byte(g_console_uart, (uint8_t *)s)) { } return 1; } +#ifndef __ICCRISCV__ int _fstat(int file, struct stat *s) { + (void) file; s->st_mode = S_IFCHR; return 0; } +#else + +#ifndef _DLIB_FILE_DESCRIPTOR +#define _DLIB_FILE_DESCRIPTOR 0 +#endif + +int __write(int file, char *data, int size) +{ + return _write(file, data, size); +} + +int __read(int file, char *s, int size) +{ + return _read(file, s, size); +} +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/dma_manager/hpm_dma_manager.c b/bsp/hpmicro/libraries/hpm_sdk/components/dma_manager/hpm_dma_manager.c deleted file mode 100644 index 699f55b3b6d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/dma_manager/hpm_dma_manager.c +++ /dev/null @@ -1,294 +0,0 @@ -/* - * Copyright (c) 2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include -#include "hpm_dma_manager.h" -#include "hpm_soc.h" - -/***************************************************************************************************************** - * - * Definitions - * - *****************************************************************************************************************/ - -typedef struct _dma_instance_info { - DMA_Type *base; - int32_t irq_num; -} dma_channel_info_t; - -/** - * @brief DMA Manager Context Structure - * - */ -typedef struct _dma_manager_context { - dma_channel_info_t dma_instance[DMA_SOC_MAX_COUNT]; /**< DMA instances */ - hpm_dma_channel_context_t channels[DMA_SOC_MAX_COUNT][DMA_SOC_CHANNEL_NUM]; /**< Array of DMA channels */ -} hpm_dma_manager_context_t; - -#define DMA_DISABLE_ALL_CHN_INT (DMA_INTERRUPT_MASK_ERROR | DMA_INTERRUPT_MASK_ABORT | DMA_INTERRUPT_MASK_TERMINAL_COUNT) - - -/***************************************************************************************************************** - * - * Prototypes - * - *****************************************************************************************************************/ - -/** - * @brief Search DMA channel context for specified DMA channel resource - * - * @param [in] resource DMA Channel resource - * @return The request DMA channel context if resource is valid or NULL if resource in invalid - */ -static hpm_dma_channel_context_t *dma_manager_search_channel_context(const hpm_dma_resource_t *resource); - -static uint32_t dma_manager_enter_critical(void); -static void dma_manager_exit_critical(uint32_t level); - -static void dma0_isr(void); -SDK_DECLARE_EXT_ISR_M(IRQn_HDMA, dma0_isr); - -#if defined(DMA_SOC_MAX_COUNT) && (DMA_SOC_MAX_COUNT > 1) -static void dma1_isr(void); -SDK_DECLARE_EXT_ISR_M(IRQn_XDMA, dma1_isr); -#endif - -/***************************************************************************************************************** - * - * Variables - * - *****************************************************************************************************************/ -static hpm_dma_manager_context_t s_dma_mngr_ctx; -#define HPM_DMA_MGR (&s_dma_mngr_ctx) - - - -/***************************************************************************************************************** - * - * Codes - * - *****************************************************************************************************************/ -static inline void handle_dma_isr(DMA_Type *ptr, uint32_t instance) -{ - for (uint8_t channel = 0; channel < DMA_SOC_CHANNEL_NUM; channel++) { - uint32_t int_disable_mask = dma_check_channel_interrupt_mask(ptr, channel); - /* If Channel interrupt is enabled */ - if (int_disable_mask != DMA_DISABLE_ALL_CHN_INT) { - uint32_t chn_int_stat = dma_check_transfer_status(ptr, channel); - if (chn_int_stat != DMA_CHANNEL_STATUS_ONGOING) { - hpm_dma_channel_context_t *chn_ctx = &HPM_DMA_MGR->channels[instance][channel]; - if (chn_ctx->callback != NULL) { - chn_ctx->callback(ptr, channel, chn_ctx->user_data, chn_int_stat); - } - } /* end if (chn_int_stat != DMA_CHANNEL_STATUS_ONGOING) */ - } /* end if (int_disable_mask != DMA_DISABLE_ALL_CHN_INT) */ - } /* end for (uint8_t channel = 0; channel < DMA_SOC_MAX_COUNT; channel++) */ -} - -void dma0_isr(void) -{ - handle_dma_isr(HPM_HDMA, 0); -} - -#if defined(DMA_SOC_MAX_COUNT) && (DMA_SOC_MAX_COUNT > 1) -void dma1_isr(void) -{ - handle_dma_isr(HPM_XDMA, 1); -} -#endif - -static uint32_t dma_manager_enter_critical(void) -{ - uint32_t level = read_csr(CSR_MSTATUS); - disable_global_irq(CSR_MSTATUS_MIE_MASK); - return level; -} - -static void dma_manager_exit_critical(uint32_t level) -{ - write_csr(CSR_MSTATUS, level); -} - -/* See hpm_dma_manager.h for more details */ -void dma_manager_init(void) -{ - (void) memset(HPM_DMA_MGR, 0, sizeof(*HPM_DMA_MGR)); - HPM_DMA_MGR->dma_instance[0].base = HPM_HDMA, - HPM_DMA_MGR->dma_instance[0].irq_num = IRQn_HDMA; - #if defined(DMA_SOC_MAX_COUNT) && (DMA_SOC_MAX_COUNT > 1) - HPM_DMA_MGR->dma_instance[1].base = HPM_XDMA; - HPM_DMA_MGR->dma_instance[1].irq_num = IRQn_XDMA; - #endif -} - -/* See hpm_dma_manager.h for more details */ -hpm_stat_t dma_manager_request_resource(hpm_dma_resource_t *resource) -{ - hpm_stat_t status; - - if (resource == NULL) { - status = status_invalid_argument; - } else { - uint32_t instance; - uint32_t channel; - bool has_found = false; - uint32_t level = dma_manager_enter_critical(); - for (instance = 0; instance < DMA_SOC_MAX_COUNT; instance++) { - for (channel = 0; channel < DMA_SOC_CHANNEL_NUM; channel++) { - if (!HPM_DMA_MGR->channels[instance][channel].is_allocated) { - has_found = true; - break; - } - } - if (has_found) { - break; - } - } - - if (has_found) { - HPM_DMA_MGR->channels[instance][channel].is_allocated = true; - resource->base = HPM_DMA_MGR->dma_instance[instance].base; - resource->channel = channel; - resource->irq_num = HPM_DMA_MGR->dma_instance[instance].irq_num; - status = status_success; - } else { - status = status_dma_manager_no_resource; - } - - dma_manager_exit_critical(level); - } - - return status; -} - -static hpm_dma_channel_context_t *dma_manager_search_channel_context(const hpm_dma_resource_t *resource) -{ - hpm_dma_channel_context_t *channel_ctx = NULL; - - if ((resource != NULL) && (resource->channel < DMA_SOC_CHANNEL_NUM)) { - uint32_t instance; - uint32_t channel; - bool has_found = false; - for (instance = 0; instance < DMA_SOC_MAX_COUNT; instance++) { - if (resource->base == HPM_DMA_MGR->dma_instance[instance].base) { - has_found = true; - break; - } - } - - channel = resource->channel; - if (has_found) { - channel_ctx = &HPM_DMA_MGR->channels[instance][channel]; - } - } - - return channel_ctx; -} - -/* See hpm_dma_manager.h for more details */ -hpm_stat_t dma_manager_release_resource(const hpm_dma_resource_t *resource) -{ - hpm_stat_t status; - - hpm_dma_channel_context_t *channel_ctx = dma_manager_search_channel_context(resource); - - if (channel_ctx == NULL) { - status = status_invalid_argument; - } else { - - uint32_t level = dma_manager_enter_critical(); - channel_ctx->is_allocated = false; - channel_ctx->user_data = NULL; - channel_ctx->callback = NULL; - status = status_success; - dma_manager_exit_critical(level); - } - return status; -} - -/* See hpm_dma_manager.h for more details */ -hpm_stat_t dma_manager_enable_channel_interrupt(const hpm_dma_resource_t *resource, uint32_t irq_mask) -{ - hpm_stat_t status; - - hpm_dma_channel_context_t *channel_ctx = dma_manager_search_channel_context(resource); - - if (channel_ctx == NULL) { - status = status_invalid_argument; - } else { - dma_enable_channel_interrupt(resource->base, resource->channel, irq_mask); - status = status_success; - } - return status; -} - -/* See hpm_dma_manager.h for more details */ -hpm_stat_t dma_manager_disable_channel_interrupt(const hpm_dma_resource_t *resource, uint32_t irq_mask) -{ - hpm_stat_t status; - - hpm_dma_channel_context_t *channel_ctx = dma_manager_search_channel_context(resource); - - if (channel_ctx == NULL) { - status = status_invalid_argument; - } else { - dma_disable_channel_interrupt(resource->base, resource->channel, irq_mask); - status = status_success; - } - return status; -} - - -/* See hpm_dma_manager.h for more details */ -hpm_stat_t dma_manager_enable_dma_interrupt(const hpm_dma_resource_t *resource, uint32_t priority) -{ - hpm_stat_t status; - - hpm_dma_channel_context_t *channel_ctx = dma_manager_search_channel_context(resource); - - if (channel_ctx == NULL) { - status = status_invalid_argument; - } else { - intc_m_enable_irq_with_priority(resource->irq_num, priority); - status = status_success; - } - return status; -} - -/* See hpm_dma_manager.h for more details */ -hpm_stat_t dma_manager_disable_dma_interrupt(const hpm_dma_resource_t *resource) -{ - hpm_stat_t status; - - hpm_dma_channel_context_t *channel_ctx = dma_manager_search_channel_context(resource); - - if (channel_ctx == NULL) { - status = status_invalid_argument; - } else { - intc_m_disable_irq(resource->irq_num); - status = status_success; - } - return status; -} - - -/* See hpm_dma_manager.h for more details */ -hpm_stat_t dma_manager_install_interrupt_callback(const hpm_dma_resource_t *resource, hpm_dma_channel_callback_t callback, void *user_data) -{ - hpm_stat_t status; - - hpm_dma_channel_context_t *channel_ctx = dma_manager_search_channel_context(resource); - - if (channel_ctx == NULL) { - status = status_invalid_argument; - } else { - channel_ctx->user_data = user_data; - channel_ctx->callback = callback; - status = status_success; - } - return status; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/dma_manager/hpm_dma_manager.h b/bsp/hpmicro/libraries/hpm_sdk/components/dma_manager/hpm_dma_manager.h deleted file mode 100644 index e7839dd1e38..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/dma_manager/hpm_dma_manager.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Copyright (c) 2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_DMA_MANAGER_H -#define HPM_DMA_MANAGER_H - -#include "hpm_common.h" -#ifdef CONFIG_HAS_HPMSDK_DMAV2 -#include "hpm_dmav2_drv.h" -#else -#include "hpm_dma_drv.h" -#endif -#include "hpm_soc_feature.h" - - -#ifdef __cplusplus - -extern "C" { -#endif - - -/** - * @brief DMA Manager status codes - */ -enum { - status_dma_manager_no_resource = MAKE_STATUS(status_group_dma_manager, 0), /**< No DMA resource available */ -}; - -/** - * @brief DMA Channel Interrupt callback - * - * @param [in] DMA base address - * @param [in] channel DMA channel index - * @param [in/out] user_data User Data context - * @param [in] int_stat DMA interrupt status - * bit0 - DMA_CHANNEL_STATUS_ONGOING - * bit1 - DMA_CHANNEL_STATUS_ERROR - * bit2 - DMA_CHANNEL_STATUS_ABORT - * bit3 - DMA_CHANNEL_STATUS_TC - */ -typedef void (*hpm_dma_channel_callback_t)(DMA_Type *base, uint32_t channel, void *user_data, uint32_t int_stat); - -/** - * @brief DMA Resource Structure - */ -typedef struct _dma_resource { - DMA_Type *base; /**< The DMA intance that the allocated channel belongs to */ - uint32_t channel; /**< Channel index */ - int32_t irq_num; /**< DMA IRQ number */ -} hpm_dma_resource_t; - -/** - * @brief DMA Channel Context Structure - */ -typedef struct _dma_channel_context { - bool is_allocated; /**< Whether DMA channel was allocated */ - void *user_data; /**< User data required by DMA channel callback */ - hpm_dma_channel_callback_t callback;/**< DMA channel callback */ -} hpm_dma_channel_context_t; - - -/** - * @brief Initialize DMA Manager Context - */ -void dma_manager_init(void); - -/** - * @brief Request DMA resource from DMA Manager - * - * @param [out] resource DMA resource - * @retval status_success if no error occurred - * @retval status_invalid_argument if the parameter is invalid - * @retval status_dma_manager_no_resource if all DMA channels are occupied; - */ -hpm_stat_t dma_manager_request_resource(hpm_dma_resource_t *resource); - -/** - * @brief Release DMA resource - * - * @param [in] resource DMA resource - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if the parameter is invalid - */ -hpm_stat_t dma_manager_release_resource(const hpm_dma_resource_t *resource); - - -/** - * @brief Enable Resource interrupt - * @param [in] resource DMA resource - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_manager_enable_channel_interrupt(const hpm_dma_resource_t *resource, uint32_t irq_mask); - - -/** - * @brief Disable Resource interrupt - * @param [in] resource DMA resource - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_manager_disable_channel_interrupt(const hpm_dma_resource_t *resource, uint32_t irq_mask); - - -/** - * @brief Enable DMa interrupt - * @param [in] resource DMA resource - * @param [in] priority Interrupt Priority - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_manager_enable_dma_interrupt(const hpm_dma_resource_t *resource, uint32_t priority); - -/** - * @brief Disable DMA interrupt - * NOTE: Each DMA instance consists of several DMA channels, disabling the DMA interrupt - * will disable the global DMA interrupt for all DMA channels. Please be aware of the - * impact - * @param [in] resource DMA resource - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_manager_disable_dma_interrupt(const hpm_dma_resource_t *resource); - - -/** - * @brief Install Interrupt Callback for the DMA resource - * - * @param [in] resource DMA resource - * @param [in] callback Interrupt callback for DMA resource - * @param [in] user_data User data used in the callback - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_manager_install_interrupt_callback(const hpm_dma_resource_t *resource, hpm_dma_channel_callback_t callback, void *user_data); - - - -#ifdef __cplusplus -} -#endif - -#endif /* HPM_DMA_MANAGER_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/dma_mgr/hpm_dma_mgr.c b/bsp/hpmicro/libraries/hpm_sdk/components/dma_mgr/hpm_dma_mgr.c new file mode 100644 index 00000000000..19068e5c316 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/dma_mgr/hpm_dma_mgr.c @@ -0,0 +1,778 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include +#include "hpm_dma_mgr.h" +#include "hpm_soc.h" + +/***************************************************************************************************************** + * + * Definitions + * + *****************************************************************************************************************/ + +typedef struct _dma_instance_info { + DMA_Type *base; + int32_t irq_num; +} dma_chn_info_t; + +/** + * @brief DMA Channel Context Structure + */ +typedef struct _dma_channel_context { + bool is_allocated; /**< Whether DMA channel was allocated */ + void *tc_cb_data_ptr; /**< User data required by transfer complete callback */ + void *half_tc_cb_data_ptr; /**< User data required by half transfer complete callback */ + void *error_cb_data_ptr; /**< User data required by error callback */ + void *abort_cb_data_ptr; /**< User data required by abort callback */ + dma_mgr_chn_cb_t tc_cb; /**< DMA channel transfer complete callback */ + dma_mgr_chn_cb_t half_tc_cb; /**< DMA channel half transfer complete callback */ + dma_mgr_chn_cb_t error_cb; /**< DMA channel error callback */ + dma_mgr_chn_cb_t abort_cb; /**< DMA channel abort callback */ +} dma_chn_context_t; + +/** + * @brief DMA Manager Context Structure + * + */ +typedef struct _dma_mgr_context { + dma_chn_info_t dma_instance[DMA_SOC_MAX_COUNT]; /**< DMA instances */ + dma_chn_context_t channels[DMA_SOC_MAX_COUNT][DMA_SOC_CHANNEL_NUM]; /**< Array of DMA channels */ +} dma_mgr_context_t; + + +/***************************************************************************************************************** + * + * Prototypes + * + *****************************************************************************************************************/ + +/** + * @brief Search DMA channel context for specified DMA channel resource + * + * @param [in] resource DMA Channel resource + * @return The request DMA channel context if resource is valid or NULL if resource in invalid + */ +static dma_chn_context_t *dma_mgr_search_chn_context(const dma_resource_t *resource); + +static uint32_t dma_mgr_enter_critical(void); +static void dma_mgr_exit_critical(uint32_t level); + +static void dma0_isr(void); +SDK_DECLARE_EXT_ISR_M(IRQn_HDMA, dma0_isr); + +#if defined(DMA_SOC_MAX_COUNT) && (DMA_SOC_MAX_COUNT > 1) +static void dma1_isr(void); +SDK_DECLARE_EXT_ISR_M(IRQn_XDMA, dma1_isr); +#endif + +/***************************************************************************************************************** + * + * Variables + * + *****************************************************************************************************************/ +static dma_mgr_context_t s_dma_mngr_ctx; +#define HPM_DMA_MGR (&s_dma_mngr_ctx) + +/***************************************************************************************************************** + * + * Codes + * + *****************************************************************************************************************/ +void dma_mgr_isr_handler(DMA_Type *ptr, uint32_t instance) +{ + uint32_t int_disable_mask; + uint32_t chn_int_stat; + dma_chn_context_t *chn_ctx; + + for (uint8_t channel = 0; channel < DMA_SOC_CHANNEL_NUM; channel++) { + int_disable_mask = dma_check_channel_interrupt_mask(ptr, channel); + chn_int_stat = dma_check_transfer_status(ptr, channel); + chn_ctx = &HPM_DMA_MGR->channels[instance][channel]; + + if (((int_disable_mask & DMA_MGR_INTERRUPT_MASK_TC) == 0) && ((chn_int_stat & DMA_MGR_CHANNEL_STATUS_TC) != 0)) { + if (chn_ctx->tc_cb != NULL) { + chn_ctx->tc_cb(ptr, channel, chn_ctx->tc_cb_data_ptr); + } + } + if (((int_disable_mask & DMA_MGR_INTERRUPT_MASK_HALF_TC) == 0) && ((chn_int_stat & DMA_MGR_CHANNEL_STATUS_HALF_TC) != 0)) { + if (chn_ctx->half_tc_cb != NULL) { + chn_ctx->half_tc_cb(ptr, channel, chn_ctx->half_tc_cb_data_ptr); + } + } + if (((int_disable_mask & DMA_MGR_INTERRUPT_MASK_ERROR) == 0) && ((chn_int_stat & DMA_MGR_CHANNEL_STATUS_ERROR) != 0)) { + if (chn_ctx->error_cb != NULL) { + chn_ctx->error_cb(ptr, channel, chn_ctx->error_cb_data_ptr); + } + } + if (((int_disable_mask & DMA_MGR_INTERRUPT_MASK_ABORT) == 0) && ((chn_int_stat & DMA_MGR_CHANNEL_STATUS_ABORT) != 0)) { + if (chn_ctx->abort_cb != NULL) { + chn_ctx->abort_cb(ptr, channel, chn_ctx->abort_cb_data_ptr); + } + } + } +} + +void dma0_isr(void) +{ + dma_mgr_isr_handler(HPM_HDMA, 0); +} + +#if defined(DMA_SOC_MAX_COUNT) && (DMA_SOC_MAX_COUNT > 1) +void dma1_isr(void) +{ + dma_mgr_isr_handler(HPM_XDMA, 1); +} +#endif + +static uint32_t dma_mgr_enter_critical(void) +{ + return disable_global_irq(CSR_MSTATUS_MIE_MASK); +} + +static void dma_mgr_exit_critical(uint32_t level) +{ + restore_global_irq(level); +} + +void dma_mgr_init(void) +{ + (void) memset(HPM_DMA_MGR, 0, sizeof(*HPM_DMA_MGR)); + HPM_DMA_MGR->dma_instance[0].base = HPM_HDMA, + HPM_DMA_MGR->dma_instance[0].irq_num = IRQn_HDMA; + #if defined(DMA_SOC_MAX_COUNT) && (DMA_SOC_MAX_COUNT > 1) + HPM_DMA_MGR->dma_instance[1].base = HPM_XDMA; + HPM_DMA_MGR->dma_instance[1].irq_num = IRQn_XDMA; + #endif +} + +hpm_stat_t dma_mgr_request_resource(dma_resource_t *resource) +{ + hpm_stat_t status; + + if (resource == NULL) { + status = status_invalid_argument; + } else { + uint32_t instance; + uint32_t channel; + bool has_found = false; + uint32_t level = dma_mgr_enter_critical(); + for (instance = 0; instance < DMA_SOC_MAX_COUNT; instance++) { + for (channel = 0; channel < DMA_SOC_CHANNEL_NUM; channel++) { + if (!HPM_DMA_MGR->channels[instance][channel].is_allocated) { + has_found = true; + break; + } + } + if (has_found) { + break; + } + } + + if (has_found) { + HPM_DMA_MGR->channels[instance][channel].is_allocated = true; + resource->base = HPM_DMA_MGR->dma_instance[instance].base; + resource->channel = channel; + resource->irq_num = HPM_DMA_MGR->dma_instance[instance].irq_num; + status = status_success; + } else { + status = status_dma_mgr_no_resource; + } + + dma_mgr_exit_critical(level); + } + + return status; +} + +static dma_chn_context_t *dma_mgr_search_chn_context(const dma_resource_t *resource) +{ + dma_chn_context_t *chn_ctx = NULL; + + if ((resource != NULL) && (resource->channel < DMA_SOC_CHANNEL_NUM)) { + uint32_t instance; + uint32_t channel; + bool has_found = false; + for (instance = 0; instance < DMA_SOC_MAX_COUNT; instance++) { + if (resource->base == HPM_DMA_MGR->dma_instance[instance].base) { + has_found = true; + break; + } + } + + channel = resource->channel; + if (has_found) { + if (HPM_DMA_MGR->channels[instance][channel].is_allocated) { + chn_ctx = &HPM_DMA_MGR->channels[instance][channel]; + } + } + } + + return chn_ctx; +} + +hpm_stat_t dma_mgr_release_resource(const dma_resource_t *resource) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + uint32_t level = dma_mgr_enter_critical(); + chn_ctx->is_allocated = false; + chn_ctx->tc_cb_data_ptr = NULL; + chn_ctx->half_tc_cb_data_ptr = NULL; + chn_ctx->error_cb_data_ptr = NULL; + chn_ctx->abort_cb_data_ptr = NULL; + chn_ctx->tc_cb = NULL; + chn_ctx->half_tc_cb = NULL; + chn_ctx->error_cb = NULL; + chn_ctx->abort_cb = NULL; + status = status_success; + dma_mgr_exit_critical(level); + } + return status; +} + +hpm_stat_t dma_mgr_enable_dma_irq_with_priority(const dma_resource_t *resource, uint32_t priority) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + intc_m_enable_irq_with_priority(resource->irq_num, priority); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_disable_dma_irq(const dma_resource_t *resource) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + intc_m_disable_irq(resource->irq_num); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_install_chn_tc_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + chn_ctx->tc_cb_data_ptr = user_data; + chn_ctx->tc_cb = callback; + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_install_chn_half_tc_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + chn_ctx->half_tc_cb_data_ptr = user_data; + chn_ctx->half_tc_cb = callback; + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_install_chn_error_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + chn_ctx->error_cb_data_ptr = user_data; + chn_ctx->error_cb = callback; + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_install_chn_abort_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + chn_ctx->abort_cb_data_ptr = user_data; + chn_ctx->abort_cb = callback; + status = status_success; + } + return status; +} + +void dma_mgr_get_default_chn_config(dma_mgr_chn_conf_t *config) +{ + config->en_dmamux = false; + config->dmamux_src = 0; + config->priority = DMA_MGR_CHANNEL_PRIORITY_LOW; + config->src_burst_size = DMA_MGR_NUM_TRANSFER_PER_BURST_1T; + config->src_mode = DMA_MGR_HANDSHAKE_MODE_NORMAL; + config->dst_mode = DMA_MGR_HANDSHAKE_MODE_NORMAL; + config->src_width = DMA_MGR_TRANSFER_WIDTH_BYTE; + config->dst_width = DMA_MGR_TRANSFER_WIDTH_BYTE; + config->src_addr_ctrl = DMA_MGR_ADDRESS_CONTROL_INCREMENT; + config->dst_addr_ctrl = DMA_MGR_ADDRESS_CONTROL_INCREMENT; + config->src_addr = 0; + config->dst_addr = 0; + config->size_in_byte = 0; + config->linked_ptr = 0; + config->interrupt_mask = DMA_MGR_INTERRUPT_MASK_ALL; + config->en_infiniteloop = false; + config->handshake_opt = DMA_MGR_HANDSHAKE_OPT_ONE_BURST; + config->burst_opt = DMA_MGR_SRC_BURST_OPT_STANDAND_SIZE; +} + +hpm_stat_t dma_mgr_setup_channel(const dma_resource_t *resource, dma_mgr_chn_conf_t *config) +{ + hpm_stat_t status; + uint32_t dmamux_ch; + dma_channel_config_t dma_config; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dmamux_ch = DMA_SOC_CHN_TO_DMAMUX_CHN(resource->base, resource->channel); + dmamux_config(HPM_DMAMUX, dmamux_ch, config->dmamux_src, config->en_dmamux); + dma_config.priority = config->priority; + dma_config.src_burst_size = config->src_burst_size; + dma_config.src_mode = config->src_mode; + dma_config.dst_mode = config->dst_mode; + dma_config.src_width = config->src_width; + dma_config.dst_width = config->dst_width; + dma_config.src_addr_ctrl = config->src_addr_ctrl; + dma_config.dst_addr_ctrl = config->dst_addr_ctrl; + dma_config.src_addr = config->src_addr; + dma_config.dst_addr = config->dst_addr; + dma_config.size_in_byte = config->size_in_byte; + dma_config.linked_ptr = config->linked_ptr; + dma_config.interrupt_mask = config->interrupt_mask; +#ifdef DMA_MGR_HAS_INFINITE_LOOP + dma_config.en_infiniteloop = config->en_infiniteloop; +#endif +#ifdef DMA_MGR_HAS_HANDSHAKE_OPT + dma_config.handshake_opt = config->handshake_opt; +#endif +#ifdef DMA_MGR_HAS_BURST_OPT + dma_config.burst_opt = config->burst_opt; +#endif + status = dma_setup_channel(resource->base, resource->channel, &dma_config, false); + } + return status; +} + +hpm_stat_t dma_mgr_config_linked_descriptor(const dma_resource_t *resource, dma_mgr_chn_conf_t *config, dma_mgr_linked_descriptor_t *descriptor) +{ + hpm_stat_t status; + dma_channel_config_t dma_config; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_config.priority = config->priority; + dma_config.src_burst_size = config->src_burst_size; + dma_config.src_mode = config->src_mode; + dma_config.dst_mode = config->dst_mode; + dma_config.src_width = config->src_width; + dma_config.dst_width = config->dst_width; + dma_config.src_addr_ctrl = config->src_addr_ctrl; + dma_config.dst_addr_ctrl = config->dst_addr_ctrl; + dma_config.src_addr = config->src_addr; + dma_config.dst_addr = config->dst_addr; + dma_config.size_in_byte = config->size_in_byte; + dma_config.linked_ptr = config->linked_ptr; + dma_config.interrupt_mask = config->interrupt_mask; +#ifdef DMA_MGR_HAS_INFINITE_LOOP + dma_config.en_infiniteloop = config->en_infiniteloop; +#endif +#ifdef DMA_MGR_HAS_HANDSHAKE_OPT + dma_config.handshake_opt = config->handshake_opt; +#endif +#ifdef DMA_MGR_HAS_BURST_OPT + dma_config.burst_opt = config->burst_opt; +#endif + status = dma_config_linked_descriptor(resource->base, (dma_linked_descriptor_t *)descriptor, resource->channel, &dma_config); + } + return status; +} + +hpm_stat_t dma_mgr_enable_channel(const dma_resource_t *resource) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + status = dma_enable_channel(resource->base, resource->channel); + } + return status; +} + +hpm_stat_t dma_mgr_disable_channel(const dma_resource_t *resource) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_disable_channel(resource->base, resource->channel); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_check_chn_enable(const dma_resource_t *resource, bool *enable) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + *enable = dma_channel_is_enable(resource->base, resource->channel); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_enable_chn_irq(const dma_resource_t *resource, uint32_t irq_mask) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_enable_channel_interrupt(resource->base, resource->channel, irq_mask); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_disable_chn_irq(const dma_resource_t *resource, uint32_t irq_mask) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_disable_channel_interrupt(resource->base, resource->channel, irq_mask); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_set_chn_priority(const dma_resource_t *resource, uint8_t priority) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_set_priority(resource->base, resource->channel, priority); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_set_chn_src_work_mode(const dma_resource_t *resource, uint8_t mode) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_set_source_work_mode(resource->base, resource->channel, mode); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_set_chn_dst_work_mode(const dma_resource_t *resource, uint8_t mode) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_set_destination_work_mode(resource->base, resource->channel, mode); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_set_chn_src_burst_size(const dma_resource_t *resource, uint8_t burstsize) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_set_source_burst_size(resource->base, resource->channel, burstsize); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_get_chn_remaining_transize(const dma_resource_t *resource, uint32_t *size) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + *size = dma_get_remaining_transfer_size(resource->base, resource->channel); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_set_chn_transize(const dma_resource_t *resource, uint32_t size) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_set_transfer_size(resource->base, resource->channel, size); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_set_chn_src_width(const dma_resource_t *resource, uint8_t width) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_set_source_width(resource->base, resource->channel, width); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_set_chn_dst_width(const dma_resource_t *resource, uint8_t width) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_set_destination_width(resource->base, resource->channel, width); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_set_chn_src_addr(const dma_resource_t *resource, uint32_t addr) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_set_source_address(resource->base, resource->channel, addr); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_set_chn_dst_addr(const dma_resource_t *resource, uint32_t addr) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_set_destination_address(resource->base, resource->channel, addr); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_set_chn_src_addr_ctrl(const dma_resource_t *resource, uint8_t addr_ctrl) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_set_source_address_ctrl(resource->base, resource->channel, addr_ctrl); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_set_chn_dst_addr_ctrl(const dma_resource_t *resource, uint8_t addr_ctrl) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_set_destination_address_ctrl(resource->base, resource->channel, addr_ctrl); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_set_chn_infinite_loop_mode(const dma_resource_t *resource, bool infinite_loop) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { +#ifdef DMA_MGR_HAS_INFINITE_LOOP + dma_set_infinite_loop_mode(resource->base, resource->channel, infinite_loop); + status = status_success; +#else + (void)infinite_loop; + status = status_fail; +#endif + } + return status; +} + +hpm_stat_t dma_mgr_set_chn_src_busrt_option(const dma_resource_t *resource, uint8_t burst_opt) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { +#ifdef DMA_MGR_HAS_BURST_OPT + dma_set_src_busrt_option(resource->base, resource->channel, burst_opt); + status = status_success; +#else + (void)burst_opt; + status = status_fail; +#endif + } + return status; +} + +hpm_stat_t dma_mgr_set_chn_handshake_option(const dma_resource_t *resource, uint8_t handshake_opt) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { +#ifdef DMA_MGR_HAS_HANDSHAKE_OPT + dma_set_handshake_option(resource->base, resource->channel, handshake_opt); + status = status_success; +#else + (void)handshake_opt; + status = status_fail; +#endif + } + return status; +} + +hpm_stat_t dma_mgr_abort_chn_transfer(const dma_resource_t *resource) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_abort_channel(resource->base, 1u << resource->channel); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_check_chn_transfer_status(const dma_resource_t *resource, uint32_t *status) +{ + hpm_stat_t stat; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + stat = status_invalid_argument; + } else { + *status = dma_check_transfer_status(resource->base, resource->channel); + stat = status_success; + } + return stat; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/dma_mgr/hpm_dma_mgr.h b/bsp/hpmicro/libraries/hpm_sdk/components/dma_mgr/hpm_dma_mgr.h new file mode 100644 index 00000000000..783ed4504d0 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/dma_mgr/hpm_dma_mgr.h @@ -0,0 +1,557 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_DMA_MGR_H +#define HPM_DMA_MGR_H + +#include "hpm_common.h" +#include "hpm_dmamux_drv.h" +#include "hpm_dmamux_src.h" +#ifdef HPMSOC_HAS_HPMSDK_DMAV2 +#include "hpm_dmav2_drv.h" +#else +#include "hpm_dma_drv.h" +#endif +#include "hpm_soc_feature.h" + +#ifdef HPMSOC_HAS_HPMSDK_DMAV2 +#define DMA_MGR_HAS_INFINITE_LOOP (1U) +#define DMA_MGR_HAS_HALF_TC_INT (1U) +#define DMA_MGR_HAS_HANDSHAKE_OPT (1U) +#define DMA_MGR_HAS_BURST_OPT (1U) +#endif + +#define DMA_MGR_CHANNEL_PRIORITY_LOW DMA_CHANNEL_PRIORITY_LOW +#define DMA_MGR_CHANNEL_PRIORITY_HIGH DMA_CHANNEL_PRIORITY_HIGH + +#define DMA_MGR_NUM_TRANSFER_PER_BURST_1T DMA_NUM_TRANSFER_PER_BURST_1T +#define DMA_MGR_NUM_TRANSFER_PER_BURST_2T DMA_NUM_TRANSFER_PER_BURST_2T +#define DMA_MGR_NUM_TRANSFER_PER_BURST_4T DMA_NUM_TRANSFER_PER_BURST_4T +#define DMA_MGR_NUM_TRANSFER_PER_BURST_8T DMA_NUM_TRANSFER_PER_BURST_8T +#define DMA_MGR_NUM_TRANSFER_PER_BURST_16T DMA_NUM_TRANSFER_PER_BURST_16T +#define DMA_MGR_NUM_TRANSFER_PER_BURST_32T DMA_NUM_TRANSFER_PER_BURST_32T +#define DMA_MGR_NUM_TRANSFER_PER_BURST_64T DMA_NUM_TRANSFER_PER_BURST_64T +#define DMA_MGR_NUM_TRANSFER_PER_BURST_128T DMA_NUM_TRANSFER_PER_BURST_128T +#define DMA_MGR_NUM_TRANSFER_PER_BURST_256T DMA_NUM_TRANSFER_PER_BURST_256T +#define DMA_MGR_NUM_TRANSFER_PER_BURST_512T DMA_NUM_TRANSFER_PER_BURST_512T +#define DMA_MGR_NUM_TRANSFER_PER_BURST_1024T DMA_NUM_TRANSFER_PER_BURST_1024T + +#define DMA_MGR_TRANSFER_WIDTH_BYTE DMA_TRANSFER_WIDTH_BYTE +#define DMA_MGR_TRANSFER_WIDTH_HALF_WORD DMA_TRANSFER_WIDTH_HALF_WORD +#define DMA_MGR_TRANSFER_WIDTH_WORD DMA_TRANSFER_WIDTH_WORD +#define DMA_MGR_TRANSFER_WIDTH_DOUBLE_WORD DMA_TRANSFER_WIDTH_DOUBLE_WORD + +#define DMA_MGR_HANDSHAKE_MODE_NORMAL DMA_HANDSHAKE_MODE_NORMAL +#define DMA_MGR_HANDSHAKE_MODE_HANDSHAKE DMA_HANDSHAKE_MODE_HANDSHAKE + +#define DMA_MGR_ADDRESS_CONTROL_INCREMENT DMA_ADDRESS_CONTROL_INCREMENT +#define DMA_MGR_ADDRESS_CONTROL_DECREMENT DMA_ADDRESS_CONTROL_DECREMENT +#define DMA_MGR_ADDRESS_CONTROL_FIXED DMA_ADDRESS_CONTROL_FIXED + +#ifdef DMA_MGR_HAS_BURST_OPT +#define DMA_MGR_SRC_BURST_OPT_STANDAND_SIZE DMA_SRC_BURST_OPT_STANDAND_SIZE +#define DMA_MGR_SRC_BURST_OPT_CUSTOM_SIZE DMA_SRC_BURST_OPT_CUSTOM_SIZE +#else +#define DMA_MGR_SRC_BURST_OPT_STANDAND_SIZE 0 +#define DMA_MGR_SRC_BURST_OPT_CUSTOM_SIZE 0 +#endif + +#ifdef DMA_MGR_HAS_HANDSHAKE_OPT +#define DMA_MGR_HANDSHAKE_OPT_ONE_BURST DMA_HANDSHAKE_OPT_ONE_BURST +#define DMA_MGR_HANDSHAKE_OPT_ALL_TRANSIZE DMA_HANDSHAKE_OPT_ALL_TRANSIZE +#else +#define DMA_MGR_HANDSHAKE_OPT_ONE_BURST 0 +#define DMA_MGR_HANDSHAKE_OPT_ALL_TRANSIZE 0 +#endif + +#define DMA_MGR_CHANNEL_STATUS_ONGOING DMA_CHANNEL_STATUS_ONGOING +#define DMA_MGR_CHANNEL_STATUS_ERROR DMA_CHANNEL_STATUS_ERROR +#define DMA_MGR_CHANNEL_STATUS_ABORT DMA_CHANNEL_STATUS_ABORT +#define DMA_MGR_CHANNEL_STATUS_TC DMA_CHANNEL_STATUS_TC +#ifdef DMA_MGR_HAS_HALF_TC_INT +#define DMA_MGR_CHANNEL_STATUS_HALF_TC DMA_CHANNEL_STATUS_HALF_TC +#else +#define DMA_MGR_CHANNEL_STATUS_HALF_TC 0 +#endif +#define DMA_MGR_INTERRUPT_MASK_NONE DMA_INTERRUPT_MASK_NONE +#define DMA_MGR_INTERRUPT_MASK_ERROR DMA_INTERRUPT_MASK_ERROR +#define DMA_MGR_INTERRUPT_MASK_ABORT DMA_INTERRUPT_MASK_ABORT +#define DMA_MGR_INTERRUPT_MASK_TC DMA_INTERRUPT_MASK_TERMINAL_COUNT +#ifdef DMA_MGR_HAS_HALF_TC_INT +#define DMA_MGR_INTERRUPT_MASK_HALF_TC DMA_INTERRUPT_MASK_HALF_TC +#else +#define DMA_MGR_INTERRUPT_MASK_HALF_TC 0 +#endif +#define DMA_MGR_INTERRUPT_MASK_ALL DMA_INTERRUPT_MASK_ALL + +#ifdef __cplusplus + +extern "C" { +#endif + +/** + * @brief DMA Manager status codes + */ +enum { + status_dma_mgr_no_resource = MAKE_STATUS(status_group_dma_manager, 0), /**< No DMA resource available */ +}; + +/** + * @brief DMA Channel Interrupt callback + * + * @param [in] DMA base address + * @param [in] channel DMA channel index + * @param [in/out] cb_data_ptr callback Data pointer + */ +typedef void (*dma_mgr_chn_cb_t)(DMA_Type *base, uint32_t channel, void *cb_data_ptr); + +/** + * @brief DMA Resource Structure + */ +typedef struct _dma_resource { + DMA_Type *base; /**< The DMA intance that the allocated channel belongs to */ + uint32_t channel; /**< Channel index */ + int32_t irq_num; /**< DMA IRQ number */ +} dma_resource_t; + +typedef struct hpm_dma_mgr_chn_conf { + bool en_dmamux; /**< DMAMUX enable */ + uint8_t dmamux_src; /**< DMAMUX source */ + uint8_t priority; /**< Channel priority */ + uint8_t src_burst_size; /**< Source burst size */ + uint8_t src_mode; /**< Source work mode: 0-Normal, 1-Handshake */ + uint8_t dst_mode; /**< Destination work mode: 0-Normal, 1-Handshake */ + uint8_t src_width; /**< Source width */ + uint8_t dst_width; /**< Destination width */ + uint8_t src_addr_ctrl; /**< Source address control: 0-inc, 1-dec, 2-fix */ + uint8_t dst_addr_ctrl; /**< Destination address control: 0-inc, 1-dec, 2-fix */ + uint16_t interrupt_mask; /**< Interrupt mask */ + uint32_t src_addr; /**< Source address */ + uint32_t dst_addr; /**< Destination address */ + uint32_t linked_ptr; /**< Next linked descriptor */ + uint32_t size_in_byte; /**< Total size to be transferred in byte */ + bool en_infiniteloop; /**< Infinite loop transfer enable. Attention: only DMAV2 support */ + uint8_t handshake_opt; /**< Handshake transfer option. Attention: only DMAV2 support */ + uint8_t burst_opt; /**< Burst size option. Attention: only DMAV2 support */ +} dma_mgr_chn_conf_t; + +typedef struct hpm_dma_mgr_linked_descriptor { + uint32_t descriptor[8]; +} dma_mgr_linked_descriptor_t; + +/** + * @brief DMA Manager ISR handler + */ +void dma_mgr_isr_handler(DMA_Type *ptr, uint32_t instance); + +/** + * @brief Initialize DMA Manager Context + */ +void dma_mgr_init(void); + +/** + * @brief Request DMA resource from DMA Manager + * + * @param [out] resource DMA resource + * @retval status_success if no error occurred + * @retval status_invalid_argument if the parameter is invalid + * @retval status_dma_mgr_no_resource if all DMA channels are occupied; + */ +hpm_stat_t dma_mgr_request_resource(dma_resource_t *resource); + +/** + * @brief Release DMA resource + * + * @param [in] resource DMA resource + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if the parameter is invalid + */ +hpm_stat_t dma_mgr_release_resource(const dma_resource_t *resource); + +/** + * @brief Enable DMA interrupt with priority + * @param [in] resource DMA resource + * @param [in] priority Interrupt Priority + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_enable_dma_irq_with_priority(const dma_resource_t *resource, uint32_t priority); + +/** + * @brief Disable DMA interrupt + * NOTE: Each DMA instance consists of several DMA channels, disabling the DMA interrupt + * will disable the global DMA interrupt for all DMA channels. Please be aware of the + * impact + * @param [in] resource DMA resource + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_disable_dma_irq(const dma_resource_t *resource); + +/** + * @brief Install Interrupt Callback for DMA channel transfer complete + * + * @param [in] resource DMA resource + * @param [in] callback Interrupt callback for DMA resource + * @param [in] user_data User data used in the callback + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_install_chn_tc_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data); + +/** + * @brief Install Interrupt Callback for DMA channel half transfer complete + * + * @param [in] resource DMA resource + * @param [in] callback Interrupt callback for DMA resource + * @param [in] user_data User data used in the callback + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_install_chn_half_tc_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data); + +/** + * @brief Install Interrupt Callback for DMA channel transfer error + * + * @param [in] resource DMA resource + * @param [in] callback Interrupt callback for DMA resource + * @param [in] user_data User data used in the callback + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_install_chn_error_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data); + +/** + * @brief Install Interrupt Callback for DMA channel transfer abort + * + * @param [in] resource DMA resource + * @param [in] callback Interrupt callback for DMA resource + * @param [in] user_data User data used in the callback + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_install_chn_abort_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data); + +/** + * @brief Get DMA channel default config + * + * @param [out] config config data pointer + */ +void dma_mgr_get_default_chn_config(dma_mgr_chn_conf_t *config); + +/** + * @brief Setup channel config + * + * @param [in] resource DMA resource + * @param [in] config DMA channel config + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_setup_channel(const dma_resource_t *resource, dma_mgr_chn_conf_t *config); + +/** + * @brief Setup chain linked descriptor config + * + * @param [in] resource DMA resource + * @param [in] config DMA channel config + * @param [out] descriptor linked descriptor config data pointer + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_config_linked_descriptor(const dma_resource_t *resource, dma_mgr_chn_conf_t *config, dma_mgr_linked_descriptor_t *descriptor); + +/** + * @brief Enable DMA channel, start transfer + * + * @param [in] resource DMA resource + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_enable_channel(const dma_resource_t *resource); + +/** + * @brief Disable DMA channel + * + * @param [in] resource DMA resource + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_disable_channel(const dma_resource_t *resource); + +/** + * @brief Check DMA channel enable status + * + * @param [in] resource DMA resource + * @param [out] enable enable status + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_check_chn_enable(const dma_resource_t *resource, bool *enable); + +/** + * @brief Enable DMA channel interrupt + * @param [in] resource DMA resource + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_enable_chn_irq(const dma_resource_t *resource, uint32_t irq_mask); + +/** + * @brief Disable DMA channel interrupt + * @param [in] resource DMA resource + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_disable_chn_irq(const dma_resource_t *resource, uint32_t irq_mask); + +/** + * @brief Set DMA channel priority + * + * @param [in] resource DMA resource + * @param [in] priority DMA channel priority + * @arg @ref DMA_MGR_PRIORITY_LOW + * @arg @ref DMA_MGR_PRIORITY_HIGH + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_set_chn_priority(const dma_resource_t *resource, uint8_t priority); + +/** + * @brief Set DMA channel source work mode + * + * @param [in] resource DMA resource + * @param [in] mode DMA source work mode + * @arg @ref DMA_MGR_HANDSHAKE_MODE_NORMAL + * @arg @ref DMA_MGR_HANDSHAKE_MODE_HANDSHAKE + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_set_chn_src_work_mode(const dma_resource_t *resource, uint8_t mode); + +/** + * @brief Set DMA channel destination work mode + * + * @param [in] resource DMA resource + * @param [in] mode DMA destination work mode + * @arg @ref DMA_MGR_HANDSHAKE_MODE_NORMAL + * @arg @ref DMA_MGR_HANDSHAKE_MODE_HANDSHAKE + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_set_chn_dst_work_mode(const dma_resource_t *resource, uint8_t mode); + +/** + * @brief Set DMA channel source burst size + * + * @param [in] resource DMA resource + * @param [in] burstsize DMA source burst size + * when BURSTOPT is 0, please reference follows: + * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_1T + * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_2T + * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_4T + * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_8T + * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_16T + * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_32T + * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_64T + * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_128T + * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_256T + * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_512T + * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_1024T + * when BURSTOPT is 1, burst size is (burstsize + 1). Attention: only DMAV2 support + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_set_chn_src_burst_size(const dma_resource_t *resource, uint8_t burstsize); + +/** + * @brief Get DMA channel remaining transfer size + * + * @param [in] resource DMA resource + * @param [out] size remaining transfer size of the channel. + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_get_chn_remaining_transize(const dma_resource_t *resource, uint32_t *size); + +/** + * @brief Set DMA channel transfer size + * + * @param [in] resource DMA resource + * @param [in] size transfer size of the channel. + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_set_chn_transize(const dma_resource_t *resource, uint32_t size); + +/** + * @brief Set DMA channel source width + * + * @param [in] resource DMA resource + * @param [in] width transfer source width of the channel + * @arg @ref DMA_MGR_TRANSFER_WIDTH_BYTE + * @arg @ref DMA_MGR_TRANSFER_WIDTH_HALF_WORD + * @arg @ref DMA_MGR_TRANSFER_WIDTH_WORD + * @arg @ref DMA_MGR_TRANSFER_WIDTH_DOUBLE_WORD + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_set_chn_src_width(const dma_resource_t *resource, uint8_t width); + +/** + * @brief Set DMA channel destination width + * + * @param [in] resource DMA resource + * @param [in] width transfer destination width of the channel + * @arg @ref DMA_MGR_TRANSFER_WIDTH_BYTE + * @arg @ref DMA_MGR_TRANSFER_WIDTH_HALF_WORD + * @arg @ref DMA_MGR_TRANSFER_WIDTH_WORD + * @arg @ref DMA_MGR_TRANSFER_WIDTH_DOUBLE_WORD + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_set_chn_dst_width(const dma_resource_t *resource, uint8_t width); + +/** + * @brief Set DMA channel source address + * + * @param [in] resource DMA resource + * @param [in] addr source address + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_set_chn_src_addr(const dma_resource_t *resource, uint32_t addr); + +/** + * @brief Set DMA channel destination address + * + * @param [in] resource DMA resource + * @param [in] addr destination address + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_set_chn_dst_addr(const dma_resource_t *resource, uint32_t addr); + +/** + * @brief Set DMA channel source address control mode + * + * @param [in] resource DMA resource + * @param [in] addr_ctrl source address control mode + * @arg @ref DMA_MGR_ADDRESS_CONTROL_INCREMENT + * @arg @ref DMA_MGR_ADDRESS_CONTROL_DECREMENT + * @arg @ref DMA_MGR_ADDRESS_CONTROL_FIXED + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_set_chn_src_addr_ctrl(const dma_resource_t *resource, uint8_t addr_ctrl); + +/** + * @brief Set DMA channel destination address control mode + * + * @param [in] resource DMA resource + * @param [in] addr_ctrl destination address control mode + * @arg @ref DMA_MGR_ADDRESS_CONTROL_INCREMENT + * @arg @ref DMA_MGR_ADDRESS_CONTROL_DECREMENT + * @arg @ref DMA_MGR_ADDRESS_CONTROL_FIXED + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_set_chn_dst_addr_ctrl(const dma_resource_t *resource, uint8_t addr_ctrl); + +/** + * @brief Set DMA channel infinite loop mode. Attention: only DMAV2 support + * + * @param [in] resource DMA resource + * @param [in] infinite_loop false - normal mode(single times mode); true - infinite loop mode(cycle mode) + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_set_chn_infinite_loop_mode(const dma_resource_t *resource, bool infinite_loop); + +/** + * @brief Set DMA channel source burst option. Attention: only DMAV2 support + * + * @param [in] resource DMA resource + * @param [in] burst_opt burst option + * @arg @ref DMA_MGR_SRC_BURST_OPT_STANDAND_SIZE + * @arg @ref DMA_MGR_SRC_BURST_OPT_CUSTOM_SIZE + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_set_chn_src_busrt_option(const dma_resource_t *resource, uint8_t burst_opt); + +/** + * @brief Set DMA channel handshake option. Attention: only DMAV2 support + * + * @param [in] resource DMA resource + * @param [in] handshake_opt handshake option + * @arg @ref DMA_HANDSHAKE_OPT_ONE_BURST + * @arg @ref DMA_HANDSHAKE_OPT_ALL_TRANSIZE + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_set_chn_handshake_option(const dma_resource_t *resource, uint8_t handshake_opt); + +/** + * @brief Abort DMA channel transfer + * + * @param [in] resource DMA resource + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_abort_chn_transfer(const dma_resource_t *resource); + +/** + * @brief Check DMA channel transfer status + * + * @param [in] resource DMA resource + * @param [out] sts transfer status + * DMA_MGR_CHANNEL_STATUS_ONGOING if transfer is still ongoing + * DMA_MGR_CHANNEL_STATUS_ERROR if any error occurred during transferring + * DMA_MGR_CHANNEL_STATUS_ABORT if transfer is aborted + * DMA_MGR_CHANNEL_STATUS_TC if transfer is finished without error + * DMA_MGR_CHANNEL_STATUS_HALF_TC if half transfer complete without error. Attention: only DMAV2 support + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_check_chn_transfer_status(const dma_resource_t *resource, uint32_t *status); + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_DMA_MGR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848.c b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848.c index 37210298209..b48617bda26 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848.c @@ -12,6 +12,7 @@ #include "hpm_enet_drv.h" #include "hpm_dp83848_regs.h" #include "hpm_dp83848.h" + /*--------------------------------------------------------------------- * Internal API *--------------------------------------------------------------------- @@ -49,8 +50,10 @@ void dp83848_reset(ENET_Type *ptr) void dp83848_basic_mode_default_config(ENET_Type *ptr, dp83848_config_t *config) { + (void)ptr; + config->loopback = false; /* Disable PCS loopback mode */ - #if __DISABLE_AUTO_NEGO + #if defined(__DISABLE_AUTO_NEGO) && (__DISABLE_AUTO_NEGO) config->auto_negotiation = false; /* Disable Auto-Negotiation */ config->speed = enet_phy_port_speed_100mbps; config->duplex = enet_phy_duplex_full; diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867.c b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867.c index 8a43504c121..97c069326de 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867.c @@ -79,8 +79,10 @@ void dp83867_reset(ENET_Type *ptr) void dp83867_basic_mode_default_config(ENET_Type *ptr, dp83867_config_t *config) { + (void)ptr; + config->loopback = false; /* Disable PCS loopback mode */ - #if __DISABLE_AUTO_NEGO + #if defined(__DISABLE_AUTO_NEGO) && (__DISABLE_AUTO_NEGO) config->auto_negotiation = false; /* Disable Auto-Negotiation */ config->speed = enet_phy_port_speed_100mbps; config->duplex = enet_phy_duplex_full; diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy.h index e2ff32796ed..5047258dbc4 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -8,6 +8,11 @@ #define HPM_ENET_PHY_H #include +typedef enum { + enet_phy_link_down = 0, + enet_phy_link_up +} enet_phy_link_status_t; + typedef enum { enet_phy_port_speed_10mbps = 0, enet_phy_port_speed_100mbps, diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy_common.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy_common.h index a82ab02d721..5bb3b0adddc 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy_common.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy_common.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -10,17 +10,26 @@ #if defined(__USE_DP83867) && __USE_DP83867 #include "hpm_dp83867.h" #include "hpm_dp83867_regs.h" -#elif defined(__USE_RTL8211) && __USE_RTL8211 +#endif + +#if defined(__USE_RTL8211) && __USE_RTL8211 #include "hpm_rtl8211.h" #include "hpm_rtl8211_regs.h" -#elif defined(__USE_DP83848) && __USE_DP83848 +#endif + +#if defined(__USE_DP83848) && __USE_DP83848 #include "hpm_dp83848.h" #include "hpm_dp83848_regs.h" -#elif defined(__USE_RTL8201) && __USE_RTL8201 +#endif + +#if defined(__USE_RTL8201) && __USE_RTL8201 #include "hpm_rtl8201.h" #include "hpm_rtl8201_regs.h" -#else - #error no specified Ethernet PHY !!! +#endif + +#if defined(__USE_LAN8720) && __USE_LAN8720 + #include "hpm_lan8720.h" + #include "hpm_lan8720_regs.h" #endif #endif /* HPM_ENET_PHY_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/lan8720/hpm_lan8720.c b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/lan8720/hpm_lan8720.c new file mode 100644 index 00000000000..e487972eb12 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/lan8720/hpm_lan8720.c @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/*--------------------------------------------------------------------- + * Includes + *--------------------------------------------------------------------- + */ +#include "hpm_enet_drv.h" +#include "hpm_lan8720_regs.h" +#include "hpm_lan8720.h" + +/*--------------------------------------------------------------------- + * Internal API + *--------------------------------------------------------------------- + */ +static bool lan8720_check_id(ENET_Type *ptr) +{ + uint16_t id1, id2; + + id1 = enet_read_phy(ptr, LAN8720_ADDR, LAN8720_PHYID1); + id2 = enet_read_phy(ptr, LAN8720_ADDR, LAN8720_PHYID2); + + if (LAN8720_PHYID1_OUI_MSB_GET(id1) == LAN8720_ID1 && LAN8720_PHYID2_OUI_LSB_GET(id2) == LAN8720_ID2) { + return true; + } else { + return false; + } +} + +/*--------------------------------------------------------------------- + * API + *--------------------------------------------------------------------- + */ +void lan8720_reset(ENET_Type *ptr) +{ + uint16_t data; + + /* PHY reset */ + enet_write_phy(ptr, LAN8720_ADDR, LAN8720_BMCR, LAN8720_BMCR_RESET_SET(1)); + + /* wait until the reset is completed */ + do { + data = enet_read_phy(ptr, LAN8720_ADDR, LAN8720_BMCR); + } while (LAN8720_BMCR_RESET_GET(data)); +} + +void lan8720_basic_mode_default_config(ENET_Type *ptr, lan8720_config_t *config) +{ + config->loopback = false; /* Disable PCS loopback mode */ + #if defined(__DISABLE_AUTO_NEGO) && __DISABLE_AUTO_NEGO + config->auto_negotiation = false; /* Disable Auto-Negotiation */ + config->speed = enet_phy_port_speed_100mbps; + config->duplex = enet_phy_duplex_full; + #else + config->auto_negotiation = true; /* Enable Auto-Negotiation */ + #endif +} + +bool lan8720_basic_mode_init(ENET_Type *ptr, lan8720_config_t *config) +{ + uint16_t data = 0; + + data |= LAN8720_BMCR_RESET_SET(0) /* Normal operation */ + | LAN8720_BMCR_LOOPBACK_SET(config->loopback) /* configure PCS loopback mode */ + | LAN8720_BMCR_ANE_SET(config->auto_negotiation) /* configure Auto-Negotiation */ + | LAN8720_BMCR_PWD_SET(0) /* Normal operation */ + | LAN8720_BMCR_ISOLATE_SET(0) /* Normal operation */ + | LAN8720_BMCR_RESTART_AN_SET(0); /* Normal operation (ignored when Auto-Negotiation is disabled) */ + + if (config->auto_negotiation == 0) { + data |= LAN8720_BMCR_SPEED_SET(config->speed); /* Set port speed */ + data |= LAN8720_BMCR_DUPLEX_SET(config->duplex); /* Set duplex mode */ + } + + /* check the id of lan8720 */ + if (lan8720_check_id(ptr) == false) { + return false; + } + + enet_write_phy(ptr, LAN8720_ADDR, LAN8720_BMCR, data); + + return true; +} + +void lan8720_get_phy_status(ENET_Type *ptr, enet_phy_status_t *status) +{ + uint16_t data; + + data = enet_read_phy(ptr, LAN8720_ADDR, LAN8720_BMSR); + status->enet_phy_link = LAN8720_BMSR_LINK_STATUS_GET(data); + + data = enet_read_phy(ptr, LAN8720_ADDR, LAN8720_PSCSR); + status->enet_phy_speed = LAN8720_PSCSR_SPEED_GET(data) == 1 ? enet_phy_port_speed_10mbps : enet_phy_port_speed_100mbps; + status->enet_phy_duplex = LAN8720_PSCSR_DUPLEX_GET(data); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/lan8720/hpm_lan8720.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/lan8720/hpm_lan8720.h new file mode 100644 index 00000000000..2f31ca906e1 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/lan8720/hpm_lan8720.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_LAN8720_H +#define HPM_LAN8720_H + +/*--------------------------------------------------------------------- + * Includes + *--------------------------------------------------------------------- + */ +#include "hpm_enet_phy.h" +#include "hpm_common.h" +#include "hpm_enet_regs.h" +/*--------------------------------------------------------------------- + * Macro Const Definitions + *--------------------------------------------------------------------- + */ +#ifndef LAN8720_ADDR +#define LAN8720_ADDR (0U) +#endif + +#define LAN8720_ID1 (0x0007U) +#define LAN8720_ID2 (0x30U) + +/*--------------------------------------------------------------------- + * Typedef Struct Declarations + *--------------------------------------------------------------------- + */ +typedef struct { + bool loopback; + uint8_t speed; + bool auto_negotiation; + uint8_t duplex; +} lan8720_config_t; + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ +/*--------------------------------------------------------------------- + * Exported Functions + *--------------------------------------------------------------------- + */ +void lan8720_reset(ENET_Type *ptr); +void lan8720_basic_mode_default_config(ENET_Type *ptr, lan8720_config_t *config); +bool lan8720_basic_mode_init(ENET_Type *ptr, lan8720_config_t *config); +void lan8720_get_phy_status(ENET_Type *ptr, enet_phy_status_t *status); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* HPM_LAN8720_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/lan8720/hpm_lan8720_regs.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/lan8720/hpm_lan8720_regs.h new file mode 100644 index 00000000000..522057ccea0 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/lan8720/hpm_lan8720_regs.h @@ -0,0 +1,457 @@ +/* + * Copyright (c) 2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_LAN8720_REGS_H +#define HPM_LAN8720_REGS_H + +typedef enum { + LAN8720_BMCR = 0, /* 0x0: Basic Mode Control Register */ + LAN8720_BMSR = 1, /* 0x1: Basic Mode Status Register */ + LAN8720_PHYID1 = 2, /* 0x2: PHY Identifier Register 1 */ + LAN8720_PHYID2 = 3, /* 0x3: PHY Identifier Register 2 */ + LAN8720_SMR = 18, /* 0x12: Special Modes Register */ + LAN8720_SECR = 26, /* 0x1A: Symbol Error Counter Register */ + LAN8720_ISFR = 29, /* 0x1D: Interrupt Source Flag Register */ + LAN8720_IMR = 30, /* 0x1E: Interrupt Mask Register */ + LAN8720_PSCSR = 31, /* 0x1F: PHY Special Control/Status Register */ +} LAN8720_REG_Type; + + +/* Bitfield definition for register: BMCR */ +/* + * RESET (RW/SC) + * + * 1 = software reset. Bit is self-clearing. When setting this bit do not set other + * bits in this register. The configuration is set from the register bit values, and not + * from the mode pins. + */ +#define LAN8720_BMCR_RESET_MASK (0x8000U) +#define LAN8720_BMCR_RESET_SHIFT (15U) +#define LAN8720_BMCR_RESET_SET(x) (((uint16_t)(x) << LAN8720_BMCR_RESET_SHIFT) & LAN8720_BMCR_RESET_MASK) +#define LAN8720_BMCR_RESET_GET(x) (((uint16_t)(x) & LAN8720_BMCR_RESET_MASK) >> LAN8720_BMCR_RESET_SHIFT) + +/* + * LOOPBACK (RW) + * + * 0 = normal operation + * 1 = loopback mode + */ +#define LAN8720_BMCR_LOOPBACK_MASK (0x4000U) +#define LAN8720_BMCR_LOOPBACK_SHIFT (14U) +#define LAN8720_BMCR_LOOPBACK_SET(x) (((uint16_t)(x) << LAN8720_BMCR_LOOPBACK_SHIFT) & LAN8720_BMCR_LOOPBACK_MASK) +#define LAN8720_BMCR_LOOPBACK_GET(x) (((uint16_t)(x) & LAN8720_BMCR_LOOPBACK_MASK) >> LAN8720_BMCR_LOOPBACK_SHIFT) + +/* + * SPEED (RW) + * + * 0 = 10Mbps + * 1 = 100Mbps + * Ignored if Auto-negotiation is enabled (0.12 = 1). + */ +#define LAN8720_BMCR_SPEED_MASK (0x2000U) +#define LAN8720_BMCR_SPEED_SHIFT (13U) +#define LAN8720_BMCR_SPEED_SET(x) (((uint16_t)(x) << LAN8720_BMCR_SPEED_SHIFT) & LAN8720_BMCR_SPEED_MASK) +#define LAN8720_BMCR_SPEED_GET(x) (((uint16_t)(x) & LAN8720_BMCR_SPEED_MASK) >> LAN8720_BMCR_SPEED_SHIFT) + +/* + * ANE (RW) + * + * Auto-Negotiation Enable + * 0 = disable auto-negotiate process + * 1 = enable auto-negotiate process (overrides 0.13 and 0.8) + */ +#define LAN8720_BMCR_ANE_MASK (0x1000U) +#define LAN8720_BMCR_ANE_SHIFT (12U) +#define LAN8720_BMCR_ANE_SET(x) (((uint16_t)(x) << LAN8720_BMCR_ANE_SHIFT) & LAN8720_BMCR_ANE_MASK) +#define LAN8720_BMCR_ANE_GET(x) (((uint16_t)(x) & LAN8720_BMCR_ANE_MASK) >> LAN8720_BMCR_ANE_SHIFT) + +/* + * PWD (RW) + * + * 0 = normal operation + * 1 = General power down mode + * The Auto-Negotiation Enable must be cleared before setting the Power + * Down. + */ +#define LAN8720_BMCR_PWD_MASK (0x800U) +#define LAN8720_BMCR_PWD_SHIFT (11U) +#define LAN8720_BMCR_PWD_SET(x) (((uint16_t)(x) << LAN8720_BMCR_PWD_SHIFT) & LAN8720_BMCR_PWD_MASK) +#define LAN8720_BMCR_PWD_GET(x) (((uint16_t)(x) & LAN8720_BMCR_PWD_MASK) >> LAN8720_BMCR_PWD_SHIFT) + +/* + * ISOLATE (RW) + * + * 0 = normal operation + * 1 = electrical isolation of PHY from the RMII + */ +#define LAN8720_BMCR_ISOLATE_MASK (0x400U) +#define LAN8720_BMCR_ISOLATE_SHIFT (10U) +#define LAN8720_BMCR_ISOLATE_SET(x) (((uint16_t)(x) << LAN8720_BMCR_ISOLATE_SHIFT) & LAN8720_BMCR_ISOLATE_MASK) +#define LAN8720_BMCR_ISOLATE_GET(x) (((uint16_t)(x) & LAN8720_BMCR_ISOLATE_MASK) >> LAN8720_BMCR_ISOLATE_SHIFT) + +/* + * RESTART_AN (RW/SC) + * + * 0 = normal operation + * 1 = restart auto-negotiate process + * Bit is self-clearing. + */ +#define LAN8720_BMCR_RESTART_AN_MASK (0x200U) +#define LAN8720_BMCR_RESTART_AN_SHIFT (9U) +#define LAN8720_BMCR_RESTART_AN_SET(x) (((uint16_t)(x) << LAN8720_BMCR_RESTART_AN_SHIFT) & LAN8720_BMCR_RESTART_AN_MASK) +#define LAN8720_BMCR_RESTART_AN_GET(x) (((uint16_t)(x) & LAN8720_BMCR_RESTART_AN_MASK) >> LAN8720_BMCR_RESTART_AN_SHIFT) + +/* + * DUPLEX (RW) + * + * 0 = half duplex + * 1 = full duplex + * Ignored if Auto-Negotiation is enabled (0.12 = 1). + */ +#define LAN8720_BMCR_DUPLEX_MASK (0x100U) +#define LAN8720_BMCR_DUPLEX_SHIFT (8U) +#define LAN8720_BMCR_DUPLEX_SET(x) (((uint16_t)(x) << LAN8720_BMCR_DUPLEX_SHIFT) & LAN8720_BMCR_DUPLEX_MASK) +#define LAN8720_BMCR_DUPLEX_GET(x) (((uint16_t)(x) & LAN8720_BMCR_DUPLEX_MASK) >> LAN8720_BMCR_DUPLEX_SHIFT) + +/* Bitfield definition for register: BMSR */ +/* + * 100BASE_T4 (RO) + * + * 0 = no T4 ability + * 1 = T4 able + */ +#define LAN8720_BMSR_100BASE_T4_MASK (0x8000U) +#define LAN8720_BMSR_100BASE_T4_SHIFT (15U) +#define LAN8720_BMSR_100BASE_T4_GET(x) (((uint16_t)(x) & LAN8720_BMSR_100BASE_T4_MASK) >> LAN8720_BMSR_100BASE_T4_SHIFT) + +/* + * 100BASE_TX_FULL (RO) + * + * 0 = no TX full duplex ability + * 1 = TX with full duplex + */ +#define LAN8720_BMSR_100BASE_TX_FULL_MASK (0x4000U) +#define LAN8720_BMSR_100BASE_TX_FULL_SHIFT (14U) +#define LAN8720_BMSR_100BASE_TX_FULL_GET(x) (((uint16_t)(x) & LAN8720_BMSR_100BASE_TX_FULL_MASK) >> LAN8720_BMSR_100BASE_TX_FULL_SHIFT) + +/* + * 100BASE_TX_HALF (RO) + * + * 0 = no TX half duplex ability + * 1 = TX with half duplex + */ +#define LAN8720_BMSR_100BASE_TX_HALF_MASK (0x2000U) +#define LAN8720_BMSR_100BASE_TX_HALF_SHIFT (13U) +#define LAN8720_BMSR_100BASE_TX_HALF_GET(x) (((uint16_t)(x) & LAN8720_BMSR_100BASE_TX_HALF_MASK) >> LAN8720_BMSR_100BASE_TX_HALF_SHIFT) + +/* + * 10BASE_T_FULL (RO) + * + * 0 = no 10Mbps with full duplex ability + * 1 = 10Mbps with full duplex + */ +#define LAN8720_BMSR_10BASE_T_FULL_MASK (0x1000U) +#define LAN8720_BMSR_10BASE_T_FULL_SHIFT (12U) +#define LAN8720_BMSR_10BASE_T_FULL_GET(x) (((uint16_t)(x) & LAN8720_BMSR_10BASE_T_FULL_MASK) >> LAN8720_BMSR_10BASE_T_FULL_SHIFT) + +/* + * 10BASE_T_HALF (RO) + * + * 0 = no 10Mbps with half duplex ability + * 1 = 10Mbps with half duplex + */ +#define LAN8720_BMSR_10BASE_T_HALF_MASK (0x800U) +#define LAN8720_BMSR_10BASE_T_HALF_SHIFT (11U) +#define LAN8720_BMSR_10BASE_T_HALF_GET(x) (((uint16_t)(x) & LAN8720_BMSR_10BASE_T_HALF_MASK) >> LAN8720_BMSR_10BASE_T_HALF_SHIFT) + +/* + * 100BASE_T2_FULL (RO) + * + * 0 = PHY not able to perform full duplex 100BASE-T2 + * 1 = PHY able to perform full duplex 100BASE-T2 + */ +#define LAN8720_BMSR_100BASE_T2_FULL_MASK (0x400U) +#define LAN8720_BMSR_100BASE_T2_FULL_SHIFT (10U) +#define LAN8720_BMSR_100BASE_T2_FULL_GET(x) (((uint16_t)(x) & LAN8720_BMSR_100BASE_T2_FULL_MASK) >> LAN8720_BMSR_100BASE_T2_FULL_SHIFT) + +/* + * 100BASE_T2_HALF (RO) + * + * 0 = PHY not able to perform half duplex 100BASE-T2 + * 1 = PHY able to perform half duplex 100BASE-T2 + */ +#define LAN8720_BMSR_100BASE_T2_HALF_MASK (0x200U) +#define LAN8720_BMSR_100BASE_T2_HALF_SHIFT (9U) +#define LAN8720_BMSR_100BASE_T2_HALF_GET(x) (((uint16_t)(x) & LAN8720_BMSR_100BASE_T2_HALF_MASK) >> LAN8720_BMSR_100BASE_T2_HALF_SHIFT) + +/* + * EXTENDED_STATUS (RO) + * + * 0 = no extended status information in register 15 + * 1 = extended status information in register 15 + */ +#define LAN8720_BMSR_EXTENDED_STATUS_MASK (0x100U) +#define LAN8720_BMSR_EXTENDED_STATUS_SHIFT (8U) +#define LAN8720_BMSR_EXTENDED_STATUS_GET(x) (((uint16_t)(x) & LAN8720_BMSR_EXTENDED_STATUS_MASK) >> LAN8720_BMSR_EXTENDED_STATUS_SHIFT) + +/* + * AUTO_NEGOTIATION_COMPLETE (RO) + * + * 0 = auto-negotiate process not completed + * 1 = auto-negotiate process completed + */ +#define LAN8720_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK (0x20U) +#define LAN8720_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT (5U) +#define LAN8720_BMSR_AUTO_NEGOTIATION_COMPLETE_GET(x) (((uint16_t)(x) & LAN8720_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK) >> LAN8720_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT) + +/* + * REMOTE_FAULT (RC) + * + * 1 = remote fault condition detected + * 0 = no remote fault + */ +#define LAN8720_BMSR_REMOTE_FAULT_MASK (0x10U) +#define LAN8720_BMSR_REMOTE_FAULT_SHIFT (4U) +#define LAN8720_BMSR_REMOTE_FAULT_GET(x) (((uint16_t)(x) & LAN8720_BMSR_REMOTE_FAULT_MASK) >> LAN8720_BMSR_REMOTE_FAULT_SHIFT) + +/* + * AUTO_NEGOTIATION_ABILITY (RO) + * + * 0 = unable to perform auto-negotiation function + * 1 = able to perform auto-negotiation function + */ +#define LAN8720_BMSR_AUTO_NEGOTIATION_ABILITY_MASK (0x8U) +#define LAN8720_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT (3U) +#define LAN8720_BMSR_AUTO_NEGOTIATION_ABILITY_GET(x) (((uint16_t)(x) & LAN8720_BMSR_AUTO_NEGOTIATION_ABILITY_MASK) >> LAN8720_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT) + +/* + * LINK_STATUS (RO) + * + * 0 = link is down + * 1 = link is up + */ +#define LAN8720_BMSR_LINK_STATUS_MASK (0x4U) +#define LAN8720_BMSR_LINK_STATUS_SHIFT (2U) +#define LAN8720_BMSR_LINK_STATUS_GET(x) (((uint16_t)(x) & LAN8720_BMSR_LINK_STATUS_MASK) >> LAN8720_BMSR_LINK_STATUS_SHIFT) + +/* + * JABBER_DETECT (RO) + * + * 0 = no jabber condition detected + * 1 = jabber condition detected + */ +#define LAN8720_BMSR_JABBER_DETECT_MASK (0x2U) +#define LAN8720_BMSR_JABBER_DETECT_SHIFT (1U) +#define LAN8720_BMSR_JABBER_DETECT_GET(x) (((uint16_t)(x) & LAN8720_BMSR_JABBER_DETECT_MASK) >> LAN8720_BMSR_JABBER_DETECT_SHIFT) + +/* + * EXTENDED_CAPABILITY (RO) + * + * 0 = does not support extended capabilities registers + * 1 = supports extended capabilities registers + */ +#define LAN8720_BMSR_EXTENDED_CAPABILITY_MASK (0x1U) +#define LAN8720_BMSR_EXTENDED_CAPABILITY_SHIFT (0U) +#define LAN8720_BMSR_EXTENDED_CAPABILITY_GET(x) (((uint16_t)(x) & LAN8720_BMSR_EXTENDED_CAPABILITY_MASK) >> LAN8720_BMSR_EXTENDED_CAPABILITY_SHIFT) + +/* Bitfield definition for register: PHYID1 */ +/* + * OUI_MSB (RO) + * + * Assigned to the 3rd through 18th bits of the Organizationally Unique Identifier + * (OUI), respectively. + */ +#define LAN8720_PHYID1_OUI_MSB_MASK (0xFFFFU) +#define LAN8720_PHYID1_OUI_MSB_SHIFT (0U) +#define LAN8720_PHYID1_OUI_MSB_GET(x) (((uint16_t)(x) & LAN8720_PHYID1_OUI_MSB_MASK) >> LAN8720_PHYID1_OUI_MSB_SHIFT) + +/* Bitfield definition for register: PHYID2 */ +/* + * OUI_LSB (RO) + * + * Assigned to the 19th through 24th bits of the OUI. + */ +#define LAN8720_PHYID2_OUI_LSB_MASK (0xFC00U) +#define LAN8720_PHYID2_OUI_LSB_SHIFT (10U) +#define LAN8720_PHYID2_OUI_LSB_GET(x) (((uint16_t)(x) & LAN8720_PHYID2_OUI_LSB_MASK) >> LAN8720_PHYID2_OUI_LSB_SHIFT) + +/* + * MODEL_NUMBER (RO) + * + * Six-bit manufacturer’s model number. + */ +#define LAN8720_PHYID2_MODEL_NUMBER_MASK (0x3F0U) +#define LAN8720_PHYID2_MODEL_NUMBER_SHIFT (4U) +#define LAN8720_PHYID2_MODEL_NUMBER_GET(x) (((uint16_t)(x) & LAN8720_PHYID2_MODEL_NUMBER_MASK) >> LAN8720_PHYID2_MODEL_NUMBER_SHIFT) + +/* + * REVISION_NUMBER (RO) + * + * Four-bit manufacturer’s revision number. + */ +#define LAN8720_PHYID2_REVISION_NUMBER_MASK (0xFU) +#define LAN8720_PHYID2_REVISION_NUMBER_SHIFT (0U) +#define LAN8720_PHYID2_REVISION_NUMBER_GET(x) (((uint16_t)(x) & LAN8720_PHYID2_REVISION_NUMBER_MASK) >> LAN8720_PHYID2_REVISION_NUMBER_SHIFT) + +/* Bitfield definition for register: SMR */ +/* + * MODE (R/W) + * + * Transceiver mode of operation + */ +#define LAN8720_SMR_MODE_MASK (0xE0U) +#define LAN8720_SMR_MODE_SHIFT (5U) +#define LAN8720_SMR_MODE_SET(x) (((uint16_t)(x) << LAN8720_SMR_MODE_SHIFT) & LAN8720_SMR_MODE_MASK) +#define LAN8720_SMR_MODE_GET(x) (((uint16_t)(x) & LAN8720_SMR_MODE_MASK) >> LAN8720_SMR_MODE_SHIFT) + +/* + * PHYAD (R/W) + * + * PHY Address. The PHY Address is used for the SMI address and for initial- + * ization of the Cipher (Scrambler) key. + */ +#define LAN8720_SMR_PHYAD_MASK (0x1FU) +#define LAN8720_SMR_PHYAD_SHIFT (0U) +#define LAN8720_SMR_PHYAD_SET(x) (((uint16_t)(x) << LAN8720_SMR_PHYAD_SHIFT) & LAN8720_SMR_PHYAD_MASK) +#define LAN8720_SMR_PHYAD_GET(x) (((uint16_t)(x) & LAN8720_SMR_PHYAD_MASK) >> LAN8720_SMR_PHYAD_SHIFT) + +/* Bitfield definition for register: SECR */ +/* + * SYM_ERR_CNT (RO) + * + * The symbol error counter increments whenever an invalid code symbol is + * received (including IDLE symbols) in 100BASE-TX mode. The counter is + * incremented only once per packet, even when the received packet contains + * more than one symbol error. This counter increments up to 65,536 (2^16) and + * rolls over to 0 after reaching the maximum value. + * Note: This register is cleared on reset, but is not cleared by reading the + * register. This register does not increment in 10BASE-T mode. + */ +#define LAN8720_SECR_SYM_ERR_CNT_MASK (0xFFFFU) +#define LAN8720_SECR_SYM_ERR_CNT_SHIFT (0U) +#define LAN8720_SECR_SYM_ERR_CNT_GET(x) (((uint16_t)(x) & LAN8720_SECR_SYM_ERR_CNT_MASK) >> LAN8720_SECR_SYM_ERR_CNT_SHIFT) + +/* Bitfield definition for register: ISFR */ +/* + * INT7 (RO) + * + * 0 = not source of interrupt + * 1 = ENERGYON generated + */ +#define LAN8720_ISFR_INT7_MASK (0x80U) +#define LAN8720_ISFR_INT7_SHIFT (7U) +#define LAN8720_ISFR_INT7_GET(x) (((uint16_t)(x) & LAN8720_ISFR_INT7_MASK) >> LAN8720_ISFR_INT7_SHIFT) + +/* + * INT6 (RO) + * + * 0 = not source of interrupt + * 1 = Auto-Negotiation complete + */ +#define LAN8720_ISFR_INT6_MASK (0x40U) +#define LAN8720_ISFR_INT6_SHIFT (6U) +#define LAN8720_ISFR_INT6_GET(x) (((uint16_t)(x) & LAN8720_ISFR_INT6_MASK) >> LAN8720_ISFR_INT6_SHIFT) + +/* + * INT5 (RO) + * + * 0 = not source of interrupt + * 1 = Remote Fault Detected + */ +#define LAN8720_ISFR_INT5_MASK (0x20U) +#define LAN8720_ISFR_INT5_SHIFT (5U) +#define LAN8720_ISFR_INT5_GET(x) (((uint16_t)(x) & LAN8720_ISFR_INT5_MASK) >> LAN8720_ISFR_INT5_SHIFT) + +/* + * INT4 (RO) + * + * 0 = not source of interrupt + * 1 = Link Down (link status negated) + */ +#define LAN8720_ISFR_INT4_MASK (0x10U) +#define LAN8720_ISFR_INT4_SHIFT (4U) +#define LAN8720_ISFR_INT4_GET(x) (((uint16_t)(x) & LAN8720_ISFR_INT4_MASK) >> LAN8720_ISFR_INT4_SHIFT) + +/* + * INT3 (RO) + * + * 0 = not source of interrupt + * 1 = Auto-Negotiation LP Acknowledge + */ +#define LAN8720_ISFR_INT3_MASK (0x8U) +#define LAN8720_ISFR_INT3_SHIFT (3U) +#define LAN8720_ISFR_INT3_GET(x) (((uint16_t)(x) & LAN8720_ISFR_INT3_MASK) >> LAN8720_ISFR_INT3_SHIFT) + +/* + * INT2 (RO) + * + * 0 = not source of interrupt + * 1 = Parallel Detection Fault + */ +#define LAN8720_ISFR_INT2_MASK (0x4U) +#define LAN8720_ISFR_INT2_SHIFT (2U) +#define LAN8720_ISFR_INT2_GET(x) (((uint16_t)(x) & LAN8720_ISFR_INT2_MASK) >> LAN8720_ISFR_INT2_SHIFT) + +/* + * INT1 (RO) + * + * 0 = not source of interrupt + * 1 = Auto-Negotiation Page Received + */ +#define LAN8720_ISFR_INT1_MASK (0x2U) +#define LAN8720_ISFR_INT1_SHIFT (1U) +#define LAN8720_ISFR_INT1_GET(x) (((uint16_t)(x) & LAN8720_ISFR_INT1_MASK) >> LAN8720_ISFR_INT1_SHIFT) + +/* Bitfield definition for register: IMR */ +/* + * MASK (R/W) + * + * 0 = interrupt source is masked + * 1 = interrupt source is enabled + */ +#define LAN8720_IMR_MASK_MASK (0xFEU) +#define LAN8720_IMR_MASK_SHIFT (1U) +#define LAN8720_IMR_MASK_SET(x) (((uint16_t)(x) << LAN8720_IMR_MASK_SHIFT) & LAN8720_IMR_MASK_MASK) +#define LAN8720_IMR_MASK_GET(x) (((uint16_t)(x) & LAN8720_IMR_MASK_MASK) >> LAN8720_IMR_MASK_SHIFT) + +/* Bitfield definition for register: PSCSR */ +/* + * AUTODONE (RO) + * + * 0 = Auto-negotiation is not done or disabled (or not active) + * 1 = Auto-negotiation is done + */ +#define LAN8720_PSCSR_AUTODONE_MASK (0x1000U) +#define LAN8720_PSCSR_AUTODONE_SHIFT (12U) +#define LAN8720_PSCSR_AUTODONE_GET(x) (((uint16_t)(x) & LAN8720_PSCSR_AUTODONE_MASK) >> LAN8720_PSCSR_AUTODONE_SHIFT) + +/* + * DUPLEX (RO) + * + * 0: Half duplex + * 1: Full duplex + */ +#define LAN8720_PSCSR_DUPLEX_MASK (0x10U) +#define LAN8720_PSCSR_DUPLEX_SHIFT (4U) +#define LAN8720_PSCSR_DUPLEX_GET(x) (((uint16_t)(x) & LAN8720_PSCSR_DUPLEX_MASK) >> LAN8720_PSCSR_DUPLEX_SHIFT) + +/* + * SPEED (RO) + * + * HCDSPEED value: + * 01 = 10BASE-T + * 10 = 100BASE-TX + */ +#define LAN8720_PSCSR_SPEED_MASK (0xCU) +#define LAN8720_PSCSR_SPEED_SHIFT (2U) +#define LAN8720_PSCSR_SPEED_GET(x) (((uint16_t)(x) & LAN8720_PSCSR_SPEED_MASK) >> LAN8720_PSCSR_SPEED_SHIFT) + + + + +#endif /* HPM_LAN8720_REGS_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201.c b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201.c index 2e931f33ed2..63d70432cc5 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201.c @@ -12,7 +12,6 @@ #include "hpm_enet_drv.h" #include "hpm_rtl8201_regs.h" #include "hpm_rtl8201.h" -#include "board.h" /*--------------------------------------------------------------------- * Internal API @@ -51,13 +50,15 @@ void rtl8201_reset(ENET_Type *ptr) void rtl8201_basic_mode_default_config(ENET_Type *ptr, rtl8201_config_t *config) { - config->loopback = 0; /* Disable PCS loopback mode */ - #if __DISABLE_AUTO_NEGO + (void)ptr; + + config->loopback = false; /* Disable PCS loopback mode */ + #if defined(__DISABLE_AUTO_NEGO) && (__DISABLE_AUTO_NEGO) config->auto_negotiation = false; /* Disable Auto-Negotiation */ config->speed = enet_phy_port_speed_100mbps; config->duplex = enet_phy_duplex_full; #else - config->auto_negotiation = 1; /* Enable Auto-Negotiation */ + config->auto_negotiation = true; /* Enable Auto-Negotiation */ #endif config->txc_input = true; /* Set TXC as input mode */ } diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201_regs.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201_regs.h index 404aaa6e6b1..17e237806a7 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -11,7 +11,7 @@ typedef enum { RTL8201_BMCR = 0, /* 0x0: Basic Mode Control Register */ - RTL8201_BMSR = 1, /* 0x1: (Basic Mode Status Register */ + RTL8201_BMSR = 1, /* 0x1: Basic Mode Status Register */ RTL8201_PHYID1 = 2, /* 0x2: PHY Identifier Register 1 */ RTL8201_PHYID2 = 3, /* 0x3: PHY Identifier Register 2 */ RTL8201_RMSR_P7 = 16, /* 0x10: RMII Mode Setting Register */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211.c b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211.c index 93f1f757b86..d7422f22b05 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211.c @@ -12,7 +12,6 @@ #include "hpm_enet_drv.h" #include "hpm_rtl8211_regs.h" #include "hpm_rtl8211.h" -#include "board.h" /*--------------------------------------------------------------------- * Internal API @@ -51,13 +50,15 @@ void rtl8211_reset(ENET_Type *ptr) void rtl8211_basic_mode_default_config(ENET_Type *ptr, rtl8211_config_t *config) { - config->loopback = 0; /* Disable PCS loopback mode */ - #if __DISABLE_AUTO_NEGO + (void)ptr; + + config->loopback = false; /* Disable PCS loopback mode */ + #if defined(__DISABLE_AUTO_NEGO) && (__DISABLE_AUTO_NEGO) config->auto_negotiation = false; /* Disable Auto-Negotiation */ config->speed = enet_phy_port_speed_100mbps; config->duplex = enet_phy_duplex_full; #else - config->auto_negotiation = 1; /* Enable Auto-Negotiation */ + config->auto_negotiation = true; /* Enable Auto-Negotiation */ #endif } diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211_regs.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211_regs.h index dabd89a6b8d..ac2343579de 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -11,7 +11,7 @@ typedef enum { RTL8211_BMCR = 0, /* 0x0: Basic Mode Control Register */ - RTL8211_BMSR = 1, /* 0x1: (Basic Mode Status Register */ + RTL8211_BMSR = 1, /* 0x1: Basic Mode Status Register */ RTL8211_PHYID1 = 2, /* 0x2: PHY Identifier Register 1 */ RTL8211_PHYID2 = 3, /* 0x3: PHY Identifier Register 2 */ RTL8211_PHYSR = 17, /* 0x11: PHY Specific Status Register */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/panel/hpm_panel.c b/bsp/hpmicro/libraries/hpm_sdk/components/panel/hpm_panel.c new file mode 100644 index 00000000000..02d55c97b9f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/panel/hpm_panel.c @@ -0,0 +1,122 @@ + +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_panel.h" +#include "hpm_clock_drv.h" + +extern hpm_panel_t panel_tm070rdh13; +extern hpm_panel_t panel_cc10128007; +extern hpm_panel_t panel_mc10128007_31b; +extern hpm_panel_t panel_tm103xdgp01; + +static hpm_panel_t *panel_list[] = { +#if defined(CONFIG_PANEL_RGB_TM070RDH13) && CONFIG_PANEL_RGB_TM070RDH13 + &panel_tm070rdh13, +#endif + +#if defined(CONFIG_PANEL_LVDS_CC10128007) && CONFIG_PANEL_LVDS_CC10128007 + &panel_cc10128007, +#endif + +#if defined(CONFIG_PANEL_MIPI_MC10128007_31B) && CONFIG_PANEL_MIPI_MC10128007_31B + &panel_mc10128007_31b, +#endif + +#if defined(CONFIG_PANEL_LVDS_TM103XDGP01) && CONFIG_PANEL_LVDS_TM103XDGP01 + &panel_tm103xdgp01, +#endif +}; + +hpm_panel_t *hpm_panel_find_device_default(void) +{ + if (sizeof(panel_list) > 0) + return panel_list[0]; + return NULL; +} + +hpm_panel_t *hpm_panel_find_device(const char *name) +{ + int n = sizeof(panel_list) / sizeof(panel_list[0]); + + for (int i = 0; i < n; i++) + if (!strcmp(panel_list[i]->name, name)) + return panel_list[i]; + + return NULL; +} + +const char *hpm_panel_get_name(hpm_panel_t *panel) +{ + return panel->name; +} + +const hpm_panel_timing_t *hpm_panel_get_timing(hpm_panel_t *panel) +{ + return &panel->timing; +} + +hpm_panel_if_type_t hpm_panel_get_if_type(hpm_panel_t *panel) +{ + return panel->if_type; +} + +void hpm_panel_register_interface(hpm_panel_t *panel, hpm_panel_hw_interface_t *hw_if) +{ + if (hw_if) + memcpy(&panel->hw_if, hw_if, sizeof(*hw_if)); +} + +void hpm_panel_reset(hpm_panel_t *panel) +{ + if (panel->funcs.reset) + panel->funcs.reset(panel); +} + +void hpm_panel_init(hpm_panel_t *panel) +{ + if (panel->funcs.init) + panel->funcs.init(panel); +} + +void hpm_panel_power_on(hpm_panel_t *panel) +{ + if (panel->funcs.power_on) + panel->funcs.power_on(panel); +} + +void hpm_panel_power_off(hpm_panel_t *panel) +{ + if (panel->funcs.power_off) + panel->funcs.power_off(panel); +} + +void hpm_panel_set_backlight(hpm_panel_t *panel, uint16_t percent) +{ + if (percent > 100) + percent = 100; + + if (panel->hw_if.set_backlight && + panel->state.backlight_percent != percent) { + panel->hw_if.set_backlight(percent); + panel->state.backlight_percent = percent; + } +} + +uint8_t hpm_panel_get_backlight(hpm_panel_t *panel) +{ + return panel->state.backlight_percent; +} + +void hpm_panel_delay_ms(uint32_t ms) +{ + clock_cpu_delay_ms(ms); +} + +void hpm_panel_delay_us(uint32_t us) +{ + clock_cpu_delay_us(us); +} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/panel/hpm_panel.h b/bsp/hpmicro/libraries/hpm_sdk/components/panel/hpm_panel.h new file mode 100644 index 00000000000..d5acf271296 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/panel/hpm_panel.h @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_PANEL_H +#define _HPM_PANEL_H + +#include +#include +#include + +struct hpm_panel; +typedef struct hpm_panel hpm_panel_t; + +typedef struct hpm_panel_timing { + uint32_t pixel_clock_khz; /*!< pixel clocl,UINT: KHz */ + uint32_t hactive; /*!< Horizontal active video */ + uint32_t hfront_porch; /*!< Horizontal Front Porch */ + uint32_t hback_porch; /*!< Horizontal Back Porch */ + uint32_t hsync_len; /*!< Horizontal sync len */ + + uint32_t vactive; /*!< Vertical active video */ + uint32_t vfront_porch; /*!< Vertical Front Porch */ + uint32_t vback_porch; /*!< Vertical Back Porch */ + uint32_t vsync_len; /*!< Vertical sync len */ + uint32_t hsync_pol :1; /*!< Horizontal Synchronization Signal Polarity, 0: High Active, 1: Low Active */ + uint32_t vsync_pol :1; /*!< Vertical Synchronization Signal Polarity, 0: High Active, 1: Low Active */ + uint32_t de_pol :1; /*!< Data Enable Signal Polarity, 0: High Active, 1: Low Active */ + uint32_t pixel_clk_pol :1; /*!< Pixel Clock Signal Polarity, 0: High Active, 1: Low Active */ + uint32_t pixel_data_pol :1;/*!< Pixel Data Signal Polarity, 0: High Active, 1: Low Active */ +} hpm_panel_timing_t; + +typedef enum hpm_panel_mipi_format { + HPM_PANEL_MIPI_FORMAT_RGB888, + HPM_PANEL_MIPI_FORMAT_RGB666, + HPM_PANEL_MIPI_FORMAT_RGB666_PACKED, + HPM_PANEL_MIPI_FORMAT_RGB565 +} hpm_panel_mipi_format; + +typedef struct hpm_panel_hw_interface { + uint32_t lcdc_pixel_clk_khz; + void (*set_reset_pin_level)(uint8_t level); + void (*set_backlight)(uint16_t percent); + void (*set_video_router)(void); + union { + struct { + hpm_panel_mipi_format format; + void *mipi_host_base; + void *mipi_phy_base; + } mipi; + struct { + uint32_t channel_di_index :8; + uint32_t channel_index :8; + void *lvb_base; + } lvds; + } video; +} hpm_panel_hw_interface_t; + +typedef struct hpm_panel_funcs { + void (*reset)(hpm_panel_t *panel); + void (*init)(hpm_panel_t *panel); + void (*power_on)(hpm_panel_t *panel); + void (*power_off)(hpm_panel_t *panel); +} hpm_panel_funcs_t; + +typedef enum hpm_panel_if_type { + HPM_PANEL_IF_TYPE_RGB, + HPM_PANEL_IF_TYPE_LVDS_SINGLE, + HPM_PANEL_IF_TYPE_LVDS_SPLIT, + HPM_PANEL_IF_TYPE_MIPI, +} hpm_panel_if_type_t; + +typedef enum hpm_panel_state_power { + HPM_PANEL_STATE_POWER_OFF, + HPM_PANEL_STATE_POWER_ON +} hpm_panel_power_state_t; + +typedef struct hpm_panel_state { + uint8_t backlight_percent; + uint8_t power_state; +} hpm_panel_state_t; + +struct hpm_panel { + const char *name; + hpm_panel_if_type_t if_type; + const hpm_panel_timing_t timing; + hpm_panel_state_t state; + hpm_panel_hw_interface_t hw_if; + hpm_panel_funcs_t funcs; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Find default panel + * + * @return pointer of panel instance + */ +hpm_panel_t *hpm_panel_find_device_default(void); + +/** + * @brief Find panel for name + * + * @param [in] name of panel + * + * @return pointer of panel instance + */ +hpm_panel_t *hpm_panel_find_device(const char *name); + +/** + * @brief Get panel name + * + * @param panel pointer of panel instance + * + * @return panel name + */ +const char *hpm_panel_get_name(hpm_panel_t *panel); + +/** + * @brief Get panel timing + * + * @param panel pointer of panel instance + * + * @return pointer of timing + */ +const hpm_panel_timing_t *hpm_panel_get_timing(hpm_panel_t *panel); + +/** + * @brief Get panel interface type + * + * @param [in] panel pointer of panel instance + * + * @return panel interface type @ref hpm_panel_if_type_t + */ +hpm_panel_if_type_t hpm_panel_get_if_type(hpm_panel_t *panel); + +/** + * @brief Register platform level hardware interface + * + * @param [in] panel pointer of panel instance + * @param [in] hw_if pointer of hardware interface + */ +void hpm_panel_register_interface(hpm_panel_t *panel, hpm_panel_hw_interface_t *hw_if); + +/** + * @brief Reset the panel + * + * @param [in] panel pointer of panel instance + */ +void hpm_panel_reset(hpm_panel_t *panel); + +/** + * @brief Initialize the panel + * + * @param [in] panel pointer of panel instance + */ +void hpm_panel_init(hpm_panel_t *panel); + +/** + * @brief Power on the panel + * + * @param [in] panel pointer of panel instance + */ +void hpm_panel_power_on(hpm_panel_t *panel); + +/** + * @brief Power off the panel + * + * @param [in] panel pointer of panel instance + */ +void hpm_panel_power_off(hpm_panel_t *panel); + +/** + * @brief Set backlight value + * + * @param [in] panel pointer of panel instance + * @param [in] percent percent of backlight [0 - 100] + */ +void hpm_panel_set_backlight(hpm_panel_t *panel, uint16_t percent); + +/** + * + * @brief Get backlight value + * + * @param [in] panel pointer of panel instance + * @return percent of backlight [0 - 100] + */ +uint8_t hpm_panel_get_backlight(hpm_panel_t *panel); + +/** + * @brief Delay specified milliseconds + * + * @param [in] ms expected delay interval in milliseconds + */ +void hpm_panel_delay_ms(uint32_t ms); + +/** + * @brief Delay specified microseconds + * + * @param [in] us expected delay interval in microseconds + */ +void hpm_panel_delay_us(uint32_t us); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPM_PANEL_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/hpm_serial_nor.c b/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/hpm_serial_nor.c new file mode 100644 index 00000000000..014aec1dcfd --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/hpm_serial_nor.c @@ -0,0 +1,1170 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_serial_nor.h" +#include "hpm_clock_drv.h" + +#ifndef SERIALNOR_CMD_PAGE_PROGRAM_1_1_4_3B +#define SERIALNOR_CMD_PAGE_PROGRAM_1_1_4_3B (0x32U) +#endif + +#ifndef SERIALNOR_CMD_READ_SDR_1_2_2_4B +#define SERIALNOR_CMD_READ_SDR_1_2_2_4B (0xBCU) +#endif + +#ifndef SERIALNOR_CMD_READ_SDR_1_2_2_3B +#define SERIALNOR_CMD_READ_SDR_1_2_2_3B (0xBBU) +#endif + +#ifndef SERIALNOR_CMD_READ_SDR_1_1_2_3B +#define SERIALNOR_CMD_READ_SDR_1_1_2_3B (0x3BU) +#endif + +#ifndef SERIALNOR_CMD_READ_SDR_1_1_2_4B +#define SERIALNOR_CMD_READ_SDR_1_1_2_4B (0x3CU) +#endif + +#ifndef SERIALNOR_CMD_WRITE_STATUS_REG3 +#define SERIALNOR_CMD_WRITE_STATUS_REG3 (0x11U) +#endif + +#ifndef SERIALNOR_CMD_READ_STATUS_REG3 +#define SERIALNOR_CMD_READ_STATUS_REG3 (0x15U) +#endif + +#ifndef kSERIALNOR_CMD_WRITE_STATUS_REG2_VIA_0X31 +#define kSERIALNOR_CMD_WRITE_STATUS_REG2_VIA_0X31 (0x31U) +#endif + + +#ifndef kSERIALNOR_CMD_READ_STATUS_REG2_VIA_0X31 +#define kSERIALNOR_CMD_READ_STATUS_REG2_VIA_0X31 (0x35U) +#endif + + +#define MAX_24BIT_ADDRESSING_SIZE ((1UL << 24)) +#define MAX_24BIT_ADDR_SIZE_IN_KBYTES ((1UL << 24) / SIZE_1KB) + +#define SPI_READ_SFDP_FREQUENCY (10000000U) + +/** + * @brief QE bit enable sequence option + */ +typedef enum { + spi_nor_quad_en_auto_or_ignore = 0U, /**< Auto enable or ignore */ + spi_nor_quad_en_set_bit6_in_status_reg1 = 1U, /**< QE bit is at bit6 in Status register 1 */ + spi_nor_quad_en_set_bit1_in_status_reg2 = 2U, /**< QE bit is at bit1 in Status register 2 register 2 */ + spi_nor_quad_en_set_bit7_in_status_reg2 = 3U, /**< QE bit is at bit7 in Status register 2 */ + spi_nor_quad_en_set_bi1_in_status_reg2_via_0x31_cmd = 4U, /**< QE bit is in status register 2 and configured by CMD 0x31 */ +} spi_nor_quad_enable_seq_t; + +static hpm_stat_t hpm_serial_nor_read_sfdp_info(hpm_serial_nor_t *flash, jedec_info_table_t *tbl, bool address_shift_enable); +static hpm_stat_t hpm_spi_get_read_para(hpm_serial_nor_t *flash, jedec_info_table_t *jedec_info); +static hpm_stat_t hpm_spi_get_program_para(hpm_serial_nor_t *flash, jedec_info_table_t *jedec_info); +static hpm_stat_t hpm_spi_nor_read_sfdp(hpm_serial_nor_t *flash, uint32_t addr, + uint32_t *buffer, uint32_t bytes); +static hpm_stat_t hpm_spi_nor_set_command(hpm_serial_nor_t *flash, uint8_t cmd); +static hpm_stat_t get_page_sector_block_size_from_sfdp(hpm_serial_nor_info_t *config, jedec_info_table_t *tbl); +static hpm_stat_t hpm_spi_nor_read_status_register(hpm_serial_nor_t *flash, uint8_t *reg_data, uint8_t status_reg); +static hpm_stat_t hpm_spi_nor_write_status_register(hpm_serial_nor_t *flash, uint8_t reg_data, uint8_t status_reg); +static hpm_stat_t prepare_quad_mode_enable_sequence(hpm_serial_nor_t *flash, jedec_info_table_t *jedec_info); + +__attribute__((weak)) void hpm_spi_nor_udelay(uint32_t us) +{ + clock_cpu_delay_us(us); +} + +static hpm_stat_t hpm_spi_get_read_para(hpm_serial_nor_t *flash, jedec_info_table_t *jedec_info) +{ + uint32_t address_bits; + uint32_t dummy_cycles = 0; + uint8_t mode_cycles = 0; + uint8_t dummy_count = 0; + jedec_flash_param_table_t *param_tbl = &jedec_info->flash_param_tbl; + jedec_4byte_addressing_inst_table_t *flash_4b_tbl = &jedec_info->flash_4b_inst_tbl; + flash->nor_read_para.data_phase_format = quad_io_mode; + flash->nor_read_para.addr_phase_format = single_io_mode; + flash->nor_read_para.data_dummy_count = 1; + address_bits = (flash->flash_info.size_in_kbytes > MAX_24BIT_ADDR_SIZE_IN_KBYTES) ? 32U : 24U; + if (address_bits == 32) { + flash->nor_read_para.addr_bit = flash_addrlen_32bit; + } else { + flash->nor_read_para.addr_bit = flash_addrlen_24bit; + } + + if (flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_QUAD_IO_MODE) { + if (address_bits == 24U) { + if (param_tbl->misc.supports_1_4_4_fast_read != 0U) { + flash->nor_read_para.read_cmd = param_tbl->read_1_4_info.inst_1_4_4_read; + } else if (param_tbl->misc.support_1_1_4_fast_read != 0U) { + flash->nor_read_para.read_cmd = param_tbl->read_1_4_info.inst_1_1_4_read; + } else { + flash->nor_read_para.read_cmd = SERIALNOR_CMD_BASICREAD_3B; + dummy_cycles = 0; + mode_cycles = 0; + } + } else { + if (jedec_info->has_4b_addressing_inst_table) { + if (flash_4b_tbl->cmd_4byte_support_info.support_1_4_4_fast_read != 0U) { + flash->nor_read_para.read_cmd = SERIALNOR_CMD_READ_SDR_1_4_4_4B; + flash->nor_read_para.addr_phase_format = quad_io_mode; + } else if (flash_4b_tbl->cmd_4byte_support_info.support_1_1_4_fast_read != 0U) { + flash->nor_read_para.read_cmd = SERIALNOR_CMD_READ_SDR_1_1_4_4B; + } else { + flash->nor_read_para.read_cmd = SERIALNOR_CMD_BASICREAD_4B; + dummy_cycles = 0; + mode_cycles = 0; + } + } else if (param_tbl->misc.supports_1_4_4_fast_read != 0U) { /* For device that is only compliant with JESD216 */ + flash->nor_read_para.read_cmd = SERIALNOR_CMD_READ_SDR_1_4_4_4B; + } else if (param_tbl->misc.support_1_1_4_fast_read != 0U) { + flash->nor_read_para.read_cmd = SERIALNOR_CMD_READ_SDR_1_1_4_4B; + } else { + flash->nor_read_para.read_cmd = SERIALNOR_CMD_BASICREAD_4B; + dummy_cycles = 0; + mode_cycles = 0; + } + } + } else if (flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_DUAL_IO_MODE) { + if (address_bits == 24U) { + if (param_tbl->misc.support_1_2_2_fast_read != 0U) { + flash->nor_read_para.read_cmd = param_tbl->read_1_2_info.inst_1_2_2_read; + flash->nor_read_para.data_phase_format = dual_io_mode; + } else if (param_tbl->misc.support_1_1_2_fast_read != 0U) { + flash->nor_read_para.read_cmd = param_tbl->read_1_2_info.inst_1_1_2_read; + } else { + flash->nor_read_para.read_cmd = SERIALNOR_CMD_BASICREAD_3B; + dummy_cycles = 0; + mode_cycles = 0; + } + } else { + if (jedec_info->has_4b_addressing_inst_table) { + if (flash_4b_tbl->cmd_4byte_support_info.support_1_2_2_fast_read != 0U) { + flash->nor_read_para.read_cmd = SERIALNOR_CMD_READ_SDR_1_2_2_4B; + flash->nor_read_para.data_phase_format = dual_io_mode; + } else if (flash_4b_tbl->cmd_4byte_support_info.support_1_1_2_fast_read != 0U) { + flash->nor_read_para.read_cmd = SERIALNOR_CMD_READ_SDR_1_1_2_4B; + flash->nor_read_para.data_phase_format = dual_io_mode; + } else { + flash->nor_read_para.data_phase_format = single_io_mode; + flash->nor_read_para.read_cmd = SERIALNOR_CMD_BASICREAD_4B; + dummy_cycles = 0; + mode_cycles = 0; + } + } else if (param_tbl->misc.support_1_2_2_fast_read != 0U) { /* For device that is only compliant with JESD216 */ + flash->nor_read_para.read_cmd = SERIALNOR_CMD_READ_SDR_1_2_2_4B; + flash->nor_read_para.data_phase_format = dual_io_mode; + } else if (param_tbl->misc.support_1_1_2_fast_read != 0U) { + flash->nor_read_para.read_cmd = SERIALNOR_CMD_READ_SDR_1_1_2_4B; + flash->nor_read_para.data_phase_format = dual_io_mode; + } else { + flash->nor_read_para.data_phase_format = single_io_mode; + flash->nor_read_para.read_cmd = SERIALNOR_CMD_BASICREAD_4B; + dummy_cycles = 0; + mode_cycles = 0; + } + } + + } else { + flash->nor_read_para.read_cmd = (address_bits == 32U) ? SERIALNOR_CMD_BASICREAD_4B : SERIALNOR_CMD_BASICREAD_3B; + flash->nor_read_para.data_phase_format = single_io_mode; + flash->nor_read_para.data_dummy_count = 0; + dummy_cycles = 0; + mode_cycles = 0; + } + + /* Determine Read command based on SFDP */ + if (flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_QUAD_IO_MODE) { + if (param_tbl->misc.supports_1_4_4_fast_read != 0U) { + flash->nor_read_para.addr_phase_format = quad_io_mode; + mode_cycles = param_tbl->read_1_4_info.mode_clocks_1_4_4_read; + dummy_cycles = param_tbl->read_1_4_info.dummy_clocks_1_4_4_read; + } else if (param_tbl->misc.support_1_1_4_fast_read != 0U) { + mode_cycles = param_tbl->read_1_4_info.mode_clocks_1_1_4_read; + dummy_cycles = param_tbl->read_1_4_info.dummy_clocks_1_1_4_read; + } else { + /* Reserved for future use */ + } + } else if (flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_DUAL_IO_MODE) { + if (param_tbl->misc.support_1_2_2_fast_read != 0U) { + flash->nor_read_para.addr_phase_format = dual_io_mode; + mode_cycles = param_tbl->read_1_2_info.mode_clocks_1_2_2_read; + dummy_cycles = param_tbl->read_1_2_info.dummy_clocks_1_2_2_read; + } else if (param_tbl->misc.support_1_1_2_fast_read != 0U) { + flash->nor_read_para.addr_phase_format = single_io_mode; + mode_cycles = param_tbl->read_1_2_info.mode_clocks_1_1_2_read; + dummy_cycles = param_tbl->read_1_2_info.dummy_clocks_1_1_2_read; + } else { + /* Reserved for future use */ + } + } + + if ((dummy_cycles) && (!(flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_SINGLE_IO_MODE))) { + if (flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_DUAL_IO_MODE) { + dummy_count = ((dummy_cycles + mode_cycles) / 4); + } else { + dummy_count = ((dummy_cycles + mode_cycles) / 2); + } + /* SPI is only support 4 dummy count*/ + if (dummy_count > 5) { + flash->nor_read_para.data_phase_format = single_io_mode; + flash->nor_read_para.addr_phase_format = single_io_mode; + flash->nor_read_para.read_cmd = (address_bits == 32U) ? SERIALNOR_CMD_BASICREAD_4B : SERIALNOR_CMD_BASICREAD_3B; + } else { + flash->nor_read_para.data_dummy_count = dummy_count; + } + } + return status_success; +} + +static hpm_stat_t hpm_spi_get_program_para(hpm_serial_nor_t *flash, jedec_info_table_t *jedec_info) +{ + jedec_4byte_addressing_inst_table_t *flash_4b_tbl; + flash_4b_tbl = &jedec_info->flash_4b_inst_tbl; + flash->nor_program_para.has_4b_addressing_inst_table = jedec_info->has_4b_addressing_inst_table; + flash->nor_program_para.support_1_1_4_page_program = flash_4b_tbl->cmd_4byte_support_info.support_1_1_4_page_program; + flash->nor_program_para.support_1_4_4_page_program = flash_4b_tbl->cmd_4byte_support_info.support_1_4_4_page_program; + return status_success; +} + +static hpm_stat_t hpm_spi_nor_read_sfdp(hpm_serial_nor_t *flash, uint32_t addr, uint32_t *buffer, uint32_t bytes) +{ + hpm_serial_nor_transfer_seq_t command_seq = {0}; + command_seq.use_dma = false; + command_seq.cmd_phase.cmd = SERIAL_FLASH_READ_SFDP; + command_seq.addr_phase.addr = addr; + command_seq.addr_phase.enable = true; + command_seq.addr_phase.addr_bit = flash_addrlen_24bit; + command_seq.addr_phase.addr_io_mode = single_io_mode; + command_seq.dummy_phase.dummy_count = 1; + command_seq.data_phase.direction = read_direction; + command_seq.data_phase.data_io_mode = single_io_mode; + command_seq.data_phase.buf = (uint8_t *)buffer; + command_seq.data_phase.len = bytes; + return flash->host.host_ops.transfer(flash->host.host_ops.user_data, &command_seq); +} + +static hpm_stat_t hpm_spi_nor_set_command(hpm_serial_nor_t *flash, uint8_t cmd) +{ + hpm_serial_nor_transfer_seq_t command_seq = {0}; + command_seq.use_dma = false; + command_seq.cmd_phase.cmd = cmd; + return flash->host.host_ops.transfer(flash->host.host_ops.user_data, &command_seq); +} + +static hpm_stat_t get_page_sector_block_size_from_sfdp(hpm_serial_nor_info_t *config, jedec_info_table_t *tbl) +{ + hpm_stat_t status = status_invalid_argument; + jedec_flash_param_table_t *param_tbl = &tbl->flash_param_tbl; + jedec_4byte_addressing_inst_table_t *flash_4b_tbl = &tbl->flash_4b_inst_tbl; + + /* Calculate Flash Size */ + uint32_t flash_size; + uint32_t flash_density = tbl->flash_param_tbl.flash_density; + uint32_t page_size; + uint32_t sector_size = 0xFFFFFFUL; + uint32_t block_size = 0U; + uint32_t block_erase_type = 0U; + uint32_t sector_erase_type = 0U; + + if (IS_HPM_BIT_SET(flash_density, 31)) { + /* Flash size >= 4G bits */ + flash_size = 1UL << ((flash_density & ~(1UL << 0x1F)) - 3U); + } else { + /* Flash size < 4G bits */ + flash_size = (flash_density + 1U) >> 3; + } + + do { + HPM_BREAK_IF(flash_size < 1U); + config->size_in_kbytes = flash_size / SIZE_1KB; + /* Calculate Page size */ + if (tbl->flash_param_tbl_size < SFDP_BASIC_PROTOCOL_TABLE_SIZE_REVA) { + config->page_size = 256U; + } else { + page_size = 1UL << (param_tbl->chip_erase_progrm_info.page_size); + config->page_size = (page_size == (1UL << 15)) ? 256U : page_size; + } + /* Calculate Sector Size */ + for (uint32_t index = 0; index < 4U; index++) { + if (param_tbl->erase_info[index].size != 0U) { + uint32_t current_erase_size = 1UL << param_tbl->erase_info[index].size; + if (current_erase_size < SIZE_1KB) { + continue; + } + if (current_erase_size < sector_size) { + sector_size = current_erase_size; + sector_erase_type = index; + } + if ((current_erase_size > block_size) && (current_erase_size < (1024U * 1024U))) { + block_size = current_erase_size; + block_erase_type = index; + } + } + } + + config->sector_size_kbytes = sector_size / SIZE_1KB; + + config->block_size_kbytes = block_size / SIZE_1KB; + + if (flash_size > MAX_24BIT_ADDRESSING_SIZE) { + if (tbl->has_4b_addressing_inst_table) { + config->sector_erase_cmd = flash_4b_tbl->erase_inst_info.erase_inst[sector_erase_type]; + config->block_erase_cmd = flash_4b_tbl->erase_inst_info.erase_inst[block_erase_type]; + } else { + switch (param_tbl->erase_info[sector_erase_type].inst) { + case SERIALNOR_CMD_SE4K_3B: + config->sector_erase_cmd = SERIALNOR_CMD_SE4K_4B; + break; + case SERIALNOR_CMD_SE64K_3B: + config->sector_erase_cmd = SERIALNOR_CMD_SE64K_4B; + break; + default: + /* Reserved for future use */ + break; + } + switch (param_tbl->erase_info[block_erase_type].inst) { + case SERIALNOR_CMD_SE4K_3B: + config->block_erase_cmd = SERIALNOR_CMD_SE4K_4B; + break; + case SERIALNOR_CMD_SE64K_3B: + config->block_erase_cmd = SERIALNOR_CMD_SE64K_4B; + break; + default: + /* Reserved for future use */ + break; + } + } + } else { + config->sector_erase_cmd = param_tbl->erase_info[sector_erase_type].inst; + config->block_erase_cmd = param_tbl->erase_info[block_erase_type].inst; + } + + status = status_success; + + } while (false); + + return status; +} + +static hpm_stat_t hpm_spi_nor_read_status_register(hpm_serial_nor_t *flash, uint8_t *reg_data, uint8_t status_reg) +{ + hpm_serial_nor_transfer_seq_t command_seq = {0}; + command_seq.use_dma = false; + command_seq.cmd_phase.cmd = status_reg; + command_seq.data_phase.direction = read_direction; + command_seq.data_phase.buf = reg_data; + command_seq.data_phase.data_io_mode = single_io_mode; + command_seq.data_phase.len = sizeof(uint8_t); + return flash->host.host_ops.transfer(flash->host.host_ops.user_data, &command_seq); +} + +static hpm_stat_t hpm_spi_nor_write_status_register(hpm_serial_nor_t *flash, uint8_t reg_data, uint8_t status_reg) +{ + hpm_stat_t stat; + hpm_serial_nor_transfer_seq_t command_seq = {0}; + stat = status_spi_nor_flash_is_busy; + while (stat == status_spi_nor_flash_is_busy) { + stat = hpm_serial_nor_is_busy(flash); + if ((stat != status_success) && (stat != status_spi_nor_flash_is_busy)) { + return stat; + } else { + if (stat == status_success) { + break; + } else { + if (stat == status_success) { + break; + } else { + hpm_spi_nor_udelay(1); + } + } + } + } + + stat = hpm_serial_nor_write_enable(flash); + if (stat != status_success) { + return stat; + } + command_seq.use_dma = false; + command_seq.cmd_phase.cmd = status_reg; + command_seq.data_phase.direction = write_direction; + command_seq.data_phase.buf = (uint8_t *)®_data; + command_seq.data_phase.data_io_mode = single_io_mode; + command_seq.data_phase.len = sizeof(uint8_t); + return flash->host.host_ops.transfer(flash->host.host_ops.user_data, &command_seq); +} + +static hpm_stat_t prepare_quad_mode_enable_sequence(hpm_serial_nor_t *flash, jedec_info_table_t *jedec_info) +{ + hpm_stat_t status = status_success; + uint8_t status_val = 0; + uint8_t read_status_reg = 0; + uint8_t write_status_reg = 0; + /* See JESD216B 6.4.18 for more details. */ + do { + /* Enter Quad mode */ + spi_nor_quad_enable_seq_t enter_quad_mode_option = spi_nor_quad_en_auto_or_ignore; + /* Ideally, we only need one condition here, however, for some Flash devices that actually support JESD216A + * before the standard is publicly released, the JESD minor revision is still the initial version. That is why + * we use two conditions to handle below logic. + */ + if ((jedec_info->standard_version >= SFDP_VERSION_MINOR_A) || + (jedec_info->flash_param_tbl_size >= SFDP_BASIC_PROTOCOL_TABLE_SIZE_REVA)) { + switch (jedec_info->flash_param_tbl.mode_4_4_info.quad_enable_requirement) { + case 1: + case 4: + case 5: + enter_quad_mode_option = spi_nor_quad_en_set_bit1_in_status_reg2; + break; + case 6: + enter_quad_mode_option = spi_nor_quad_en_set_bi1_in_status_reg2_via_0x31_cmd; + break; + case 2: + enter_quad_mode_option = spi_nor_quad_en_set_bit6_in_status_reg1; + break; + case 3: + enter_quad_mode_option = spi_nor_quad_en_set_bit7_in_status_reg2; + break; + default: + enter_quad_mode_option = spi_nor_quad_en_auto_or_ignore; + flash->flash_info.en_dev_mode_cfg = 0; + break; + } + } else { + /* Device does not have a QE bit. Device detects 1-1-4 and 1-4-4 reads based on instruction */ + enter_quad_mode_option = spi_nor_quad_en_auto_or_ignore; + status = status_spi_nor_flash_not_qe_bit_in_sfdp; + } + /* Retrieve the read status command */ + if (enter_quad_mode_option != spi_nor_quad_en_auto_or_ignore) { + + switch (enter_quad_mode_option) { + case spi_nor_quad_en_set_bit1_in_status_reg2: + case spi_nor_quad_en_set_bi1_in_status_reg2_via_0x31_cmd: + read_status_reg = kSERIALNOR_CMD_READ_STATUS_REG2_VIA_0X31; + break; + case spi_nor_quad_en_set_bit6_in_status_reg1: + read_status_reg = SERIALNOR_CMD_READ_STATUS_REG1; + break; + case spi_nor_quad_en_set_bit7_in_status_reg2: + read_status_reg = SERIALNOR_CMD_READ_STATUS_REG2; + break; + default: + /* Reserved for future use */ + break; + } + status = hpm_spi_nor_read_status_register(flash, &status_val, read_status_reg); + HPM_BREAK_IF(status != status_success); + + /* Do modify-after-read status and then create Quad mode Enable sequence + * Enable QE bit only if it is not enabled. + */ + flash->flash_info.en_dev_mode_cfg = 0; + switch (enter_quad_mode_option) { + case spi_nor_quad_en_set_bit6_in_status_reg1: + if (!IS_HPM_BIT_SET(status_val, 6)) { + write_status_reg = SERIALNOR_CMD_WRITE_STATUS_REG1; + status_val &= (uint8_t) ~0x3cU; /* Clear Block protection */ + status_val |= HPM_BITSMASK(1U, 6); + status = hpm_spi_nor_write_status_register(flash, status_val, write_status_reg); + HPM_BREAK_IF(status != status_success); + flash->flash_info.en_dev_mode_cfg = 1U; + } + break; + case spi_nor_quad_en_set_bit1_in_status_reg2: + if (!IS_HPM_BIT_SET(status_val, 1)) { + write_status_reg = SERIALNOR_CMD_WRITE_STATUS_REG1; + status_val |= HPM_BITSMASK(1U, 1); + /* QE bit will be programmed after status1 register, so need to left shit 8 bit */ + status_val <<= 8; + status = hpm_spi_nor_write_status_register(flash, status_val, write_status_reg); + HPM_BREAK_IF(status != status_success); + flash->flash_info.en_dev_mode_cfg = 1U; + } + break; + case spi_nor_quad_en_set_bi1_in_status_reg2_via_0x31_cmd: + if (!IS_HPM_BIT_SET(status_val, 1)) { + write_status_reg = kSERIALNOR_CMD_WRITE_STATUS_REG2_VIA_0X31; + status_val |= HPM_BITSMASK(1U, 1); + status = hpm_spi_nor_write_status_register(flash, status_val, write_status_reg); + HPM_BREAK_IF(status != status_success); + flash->flash_info.en_dev_mode_cfg = 1U; + } + break; + case spi_nor_quad_en_set_bit7_in_status_reg2: + if (!IS_HPM_BIT_SET(status_val, 7)) { + write_status_reg = SERIALNOR_CMD_WRITE_STATUS_REG2; + status_val |= HPM_BITSMASK(1U, 7); + status = hpm_spi_nor_write_status_register(flash, status_val, write_status_reg); + HPM_BREAK_IF(status != status_success); + flash->flash_info.en_dev_mode_cfg = 1U; + } + break; + default: + flash->flash_info.en_dev_mode_cfg = 0U; + break; + } + } + } while (false); + + return status; +} + +static hpm_stat_t hpm_serial_nor_read_sfdp_info(hpm_serial_nor_t *flash, jedec_info_table_t *tbl, bool address_shift_enable) +{ + hpm_stat_t status = status_spi_nor_sfdp_not_found; + do { + sfdp_header_t sfdp_header; + uint32_t address; + uint32_t parameter_header_number; + uint32_t max_hdr_count; + uint32_t parameter_id; + uint32_t table_size; + + status = hpm_spi_nor_read_sfdp(flash, 0, &sfdp_header.words[0], sizeof(sfdp_header)); + HPM_BREAK_IF(status != status_success); + + if (sfdp_header.signature != SFDP_SIGNATURE) { + status = status_spi_nor_sfdp_not_found; + break; + } + + parameter_header_number = (uint32_t) sfdp_header.param_hdr_num + 1U; + + sfdp_parameter_header_t sfdp_param_hdrs[10]; + (void) memset(&sfdp_param_hdrs, 0, sizeof(sfdp_param_hdrs)); + max_hdr_count = parameter_header_number > 10U ? 10U : parameter_header_number; + address = 0x08U; + if (address_shift_enable) { + address <<= 8; + } + status = hpm_spi_nor_read_sfdp(flash, address, &sfdp_param_hdrs[0].words[0], + max_hdr_count * sizeof(sfdp_parameter_header_t)); + HPM_BREAK_IF(status != status_success); + + (void) memset(tbl, 0, sizeof(*tbl)); + + /* Save the standard version for later use. */ + tbl->standard_version = sfdp_header.minor_rev; + + for (uint32_t i = 0; i < max_hdr_count; i++) { + parameter_id = sfdp_param_hdrs[i].parameter_id_lsb + ((uint32_t) sfdp_param_hdrs[i].parameter_id_msb << 8); + + if ((parameter_id == PARAMETER_ID_BASIC_SPIPROTOCOL) || + (parameter_id == PARAMETER_ID_4BYTEADDRESS_INSTRUCTION_TABLE) || + (parameter_id == PARAMETER_ID_CMDSEQ_CHANGE_TO_OCTAL_DDR) || + (parameter_id == PARAMETER_ID_XSPIPROFILE1_0) || (parameter_id == PARAMETER_ID_STACTRLCFGREGMAP)) { + address = 0; + for (int32_t index = 2; index >= 0; index--) { + address <<= 8; + address |= sfdp_param_hdrs[i].parameter_table_pointer[index]; + } + table_size = (uint32_t) sfdp_param_hdrs[i].table_length_in_32bit * sizeof(uint32_t); + + if (address_shift_enable) { + address <<= 8; + } + + if (parameter_id == PARAMETER_ID_BASIC_SPIPROTOCOL) { + /* Limit table size to the max supported standard */ + if (table_size > sizeof(jedec_flash_param_table_t)) { + table_size = sizeof(jedec_flash_param_table_t); + } + status = hpm_spi_nor_read_sfdp(flash, address, &tbl->flash_param_tbl.words[0], table_size); + HPM_BREAK_IF(status != status_success); + + tbl->flash_param_tbl_size = table_size; + } else if (parameter_id == PARAMETER_ID_4BYTEADDRESS_INSTRUCTION_TABLE) { + status = hpm_spi_nor_read_sfdp(flash, address, &tbl->flash_4b_inst_tbl.words[0], table_size); + HPM_BREAK_IF(status != status_success); + + tbl->has_4b_addressing_inst_table = true; + } else if (parameter_id == PARAMETER_ID_CMDSEQ_CHANGE_TO_OCTAL_DDR) { + status = hpm_spi_nor_read_sfdp(flash, address, &tbl->otcal_ddr_mode_enable_sequence.words[0], + sizeof(jedec_cmd_sequence_change_to_octal_mode_t)); + HPM_BREAK_IF(status != status_success); + + tbl->has_otcal_ddr_mode_enable_sequence_table = true; + } else if (parameter_id == PARAMETER_ID_XSPIPROFILE1_0) { + status = hpm_spi_nor_read_sfdp(flash, address, &tbl->profile1_0_table.words[0], + sizeof(jedec_x_spi_profile1_0_table_t)); + HPM_BREAK_IF(status != status_success); + + tbl->has_spi_profile1_0_table = true; + } else if (parameter_id == PARAMETER_ID_STACTRLCFGREGMAP) { + status = hpm_spi_nor_read_sfdp(flash, address, &tbl->sccr_map.words[0], + sizeof(jedec_status_control_configuration_reg_map_t)); + HPM_BREAK_IF(status != status_success); + + tbl->has_sccr_map = true; + } else { + /* Reserved for future use */ + } + } else { + /* Unsupported parameter type, ignore */ + } + } + + } while (false); + + return status; +} + +hpm_stat_t hpm_serial_nor_is_busy(hpm_serial_nor_t *flash) +{ + uint8_t sr = 0; + hpm_stat_t stat; + if (flash == NULL) { + return status_invalid_argument; + } + stat = hpm_spi_nor_read_status_register(flash, &sr, SERIALNOR_CMD_READ_STATUS_REG1); + if (stat != status_success) { + return stat; + } + return (sr & 0b1) ? status_spi_nor_flash_is_busy : status_success; +} + +hpm_stat_t hpm_serial_nor_write_enable(hpm_serial_nor_t *flash) +{ + hpm_stat_t stat; + uint8_t cmd; + if (flash == NULL) { + return status_invalid_argument; + } + cmd = SERIALNOR_CMD_WRITEENABLE; + stat = hpm_spi_nor_set_command(flash, cmd); + if (stat != status_success) { + return stat; + } + hpm_spi_nor_udelay(1); + return stat; +} + +hpm_stat_t hpm_serial_nor_erase_chip(hpm_serial_nor_t *flash) +{ + hpm_stat_t stat; + uint8_t cmd; + if (flash == NULL) { + return status_invalid_argument; + } + stat = status_spi_nor_flash_is_busy; + while (stat == status_spi_nor_flash_is_busy) { + stat = hpm_serial_nor_is_busy(flash); + if ((stat != status_success) && (stat != status_spi_nor_flash_is_busy)) { + return stat; + } else { + if (stat == status_success) { + break; + } else { + hpm_spi_nor_udelay(1); + } + } + } + + stat = hpm_serial_nor_write_enable(flash); + if (stat != status_success) { + return stat; + } + + cmd = SERIALNOR_CMD_CHIPERASE; + stat = hpm_spi_nor_set_command(flash, cmd); + if (stat != status_success) { + return stat; + } + + stat = status_spi_nor_flash_is_busy; + while (stat == status_spi_nor_flash_is_busy) { + stat = hpm_serial_nor_is_busy(flash); + if ((stat != status_success) && (stat != status_spi_nor_flash_is_busy)) { + return stat; + } else { + if (stat == status_success) { + break; + } else { + hpm_spi_nor_udelay(1); + } + } + } + return stat; +} + +hpm_stat_t hpm_serial_nor_erase_block_blocking(hpm_serial_nor_t *flash, uint32_t block_addr) +{ + hpm_stat_t stat; + uint8_t cmd; + uint32_t addr; + hpm_serial_nor_transfer_seq_t command_seq = {0}; + + if (flash == NULL) { + return status_invalid_argument; + } + + stat = status_spi_nor_flash_is_busy; + while (stat == status_spi_nor_flash_is_busy) { + stat = hpm_serial_nor_is_busy(flash); + if ((stat != status_success) && (stat != status_spi_nor_flash_is_busy)) { + return stat; + } else { + if (stat == status_success) { + break; + } else { + hpm_spi_nor_udelay(1); + } + } + } + + stat = hpm_serial_nor_write_enable(flash); + if (stat != status_success) { + return stat; + } + cmd = flash->flash_info.block_erase_cmd; + addr = (flash->flash_info.size_in_kbytes > MAX_24BIT_ADDR_SIZE_IN_KBYTES) ? 32U : 24U; + if (addr == 32) { + command_seq.addr_phase.addr_bit = flash_addrlen_32bit; + } else { + command_seq.addr_phase.addr_bit = flash_addrlen_24bit; + } + command_seq.addr_phase.enable = true; + command_seq.cmd_phase.cmd = cmd; + command_seq.addr_phase.addr = block_addr; + command_seq.addr_phase.addr_io_mode = single_io_mode; + command_seq.dummy_phase.dummy_count = 0; + command_seq.use_dma = false; + stat = flash->host.host_ops.transfer(flash->host.host_ops.user_data, &command_seq); + + if (stat != status_success) { + return stat; + } + stat = status_spi_nor_flash_is_busy; + while (stat == status_spi_nor_flash_is_busy) { + stat = hpm_serial_nor_is_busy(flash); + if ((stat != status_success) && (stat != status_spi_nor_flash_is_busy)) { + return stat; + } else { + if (stat == status_success) { + break; + } else { + hpm_spi_nor_udelay(1); + } + } + } + return stat; +} + +hpm_stat_t hpm_serial_nor_erase_sector_blocking(hpm_serial_nor_t *flash, uint32_t sector_addr) +{ + hpm_stat_t stat; + uint32_t addr; + hpm_serial_nor_transfer_seq_t command_seq = {0}; + if (flash == NULL) { + return status_invalid_argument; + } + + stat = status_spi_nor_flash_is_busy; + while (stat == status_spi_nor_flash_is_busy) { + stat = hpm_serial_nor_is_busy(flash); + if ((stat != status_success) && (stat != status_spi_nor_flash_is_busy)) { + return stat; + } else { + if (stat == status_success) { + break; + } else { + hpm_spi_nor_udelay(1); + } + } + } + + stat = hpm_serial_nor_write_enable(flash); + if (stat != status_success) { + return stat; + } + + addr = (flash->flash_info.size_in_kbytes > MAX_24BIT_ADDR_SIZE_IN_KBYTES) ? 32U : 24U; + command_seq.cmd_phase.cmd = flash->flash_info.sector_erase_cmd; + if (addr == 32) { + command_seq.addr_phase.addr_bit = flash_addrlen_32bit; + } else { + command_seq.addr_phase.addr_bit = flash_addrlen_24bit; + } + command_seq.addr_phase.enable = true; + command_seq.addr_phase.addr = sector_addr; + command_seq.addr_phase.addr_io_mode = single_io_mode; + command_seq.use_dma = false; + stat = flash->host.host_ops.transfer(flash->host.host_ops.user_data, &command_seq); + if (stat != status_success) { + return stat; + } + + stat = status_spi_nor_flash_is_busy; + while (stat == status_spi_nor_flash_is_busy) { + stat = hpm_serial_nor_is_busy(flash); + if ((stat != status_success) && (stat != status_spi_nor_flash_is_busy)) { + return stat; + } else { + if (stat == status_success) { + break; + } else { + hpm_spi_nor_udelay(1); + } + } + } + return stat; +} + +hpm_stat_t hpm_serial_nor_erase_block_noblocking(hpm_serial_nor_t *flash, uint32_t block_addr) +{ + hpm_stat_t stat; + uint32_t addr; + hpm_serial_nor_transfer_seq_t command_seq = {0}; + + if (flash == NULL) { + return status_invalid_argument; + } + + stat = hpm_serial_nor_write_enable(flash); + if (stat != status_success) { + return stat; + } + + addr = (flash->flash_info.size_in_kbytes > MAX_24BIT_ADDR_SIZE_IN_KBYTES) ? 32U : 24U; + if (addr == 32) { + command_seq.addr_phase.addr_bit = flash_addrlen_32bit; + } else { + command_seq.addr_phase.addr_bit = flash_addrlen_24bit; + } + command_seq.addr_phase.enable = true; + command_seq.addr_phase.addr = block_addr; + command_seq.addr_phase.addr_io_mode = single_io_mode; + command_seq.cmd_phase.cmd = flash->flash_info.block_erase_cmd; + command_seq.use_dma = false; + stat = flash->host.host_ops.transfer(flash->host.host_ops.user_data, &command_seq); + if (stat != status_success) { + return stat; + } + return stat; +} + +hpm_stat_t hpm_serial_nor_erase_sector_noblocking(hpm_serial_nor_t *flash, uint32_t sector_addr) +{ + hpm_stat_t stat; + uint32_t addr; + hpm_serial_nor_transfer_seq_t command_seq = {0}; + + if (flash == NULL) { + return status_invalid_argument; + } + + stat = hpm_serial_nor_write_enable(flash); + if (stat != status_success) { + return stat; + } + + addr = (flash->flash_info.size_in_kbytes > MAX_24BIT_ADDR_SIZE_IN_KBYTES) ? 32U : 24U; + if (addr == 32) { + command_seq.addr_phase.addr_bit = flash_addrlen_32bit; + } else { + command_seq.addr_phase.addr_bit = flash_addrlen_24bit; + } + command_seq.addr_phase.enable = true; + command_seq.addr_phase.addr = sector_addr; + command_seq.addr_phase.addr_io_mode = single_io_mode; + command_seq.cmd_phase.cmd = flash->flash_info.sector_erase_cmd; + command_seq.use_dma = false; + stat = flash->host.host_ops.transfer(flash->host.host_ops.user_data, &command_seq); + if (stat != status_success) { + return stat; + } + + return stat; +} + +hpm_stat_t hpm_serial_nor_erase_blocking(hpm_serial_nor_t *flash, uint32_t start, uint32_t length) +{ + hpm_stat_t status = status_invalid_argument; + uint32_t sector_size; + uint32_t block_size; + uint32_t aligned_start; + uint32_t aligned_len; + uint32_t remaining_len; + if (flash == NULL) { + return status_invalid_argument; + } + do { + sector_size = flash->flash_info.sector_size_kbytes * 1024U; + block_size = flash->flash_info.block_size_kbytes * 1024U; + aligned_start = HPM_ALIGN_DOWN(start, sector_size); + aligned_len = HPM_ALIGN_UP(start + length, sector_size) - aligned_start; + + /* If erase address is not block aligned */ + remaining_len = aligned_len; + while (remaining_len > 0U) { + if ((aligned_start % block_size != 0U) || (remaining_len < block_size)) { + status = hpm_serial_nor_erase_sector_blocking(flash, aligned_start); + HPM_BREAK_IF(status != status_success); + aligned_start += sector_size; + remaining_len -= sector_size; + } else { + status = hpm_serial_nor_erase_block_blocking(flash, aligned_start); + HPM_BREAK_IF(status != status_success); + aligned_start += block_size; + remaining_len -= block_size; + } + } + } while (false); + return status; +} + +hpm_stat_t hpm_serial_nor_program_blocking(hpm_serial_nor_t *flash, uint8_t *buf, uint32_t data_len, uint32_t address) +{ + hpm_stat_t stat = status_success; + uint32_t program_size = 0; + uint32_t offset_in_page; + uint32_t remaining_page_size; + uint8_t *src_8; + uint32_t address_bits; + uint32_t offset; + hpm_serial_nor_transfer_seq_t command_seq = {0}; + + if ((buf == NULL) || (data_len == 0) || (flash == NULL)) { + return status_invalid_argument; + } + + command_seq.addr_phase.addr_io_mode = single_io_mode; + command_seq.data_phase.data_io_mode = quad_io_mode; + do { + HPM_BREAK_IF(data_len > (flash->flash_info.size_in_kbytes * SIZE_1KB)); + + stat = status_spi_nor_flash_is_busy; + while (stat == status_spi_nor_flash_is_busy) { + stat = hpm_serial_nor_is_busy(flash); + if ((stat != status_success) && (stat != status_spi_nor_flash_is_busy)) { + return stat; + } else { + if (stat == status_success) { + break; + } else { + hpm_spi_nor_udelay(1); + } + } + } + + offset_in_page = address % flash->flash_info.page_size; + remaining_page_size = flash->flash_info.page_size - offset_in_page; + address_bits = (flash->flash_info.size_in_kbytes > MAX_24BIT_ADDR_SIZE_IN_KBYTES) ? 32U : 24U; + if (address_bits == 32) { + command_seq.addr_phase.addr_bit = flash_addrlen_32bit; + if ((flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_QUAD_IO_MODE) && (flash->nor_program_para.has_4b_addressing_inst_table)) { + if (flash->nor_program_para.support_1_4_4_page_program == true) { + flash->nor_program_para.page_program_cmd = SERIALNOR_CMD_PAGEPROGRAM_1_4_4_4B; + command_seq.addr_phase.addr_io_mode = dual_io_mode; + } else if (flash->nor_program_para.support_1_1_4_page_program == true) { + flash->nor_program_para.page_program_cmd = SERIALNOR_CMD_PAGEPROGRAM_1_1_4_4B; + } else { + /* 1_1_1_page_program */ + flash->nor_program_para.page_program_cmd = SERIALNOR_CMD_PAGEPROGRAM_1_1_1_4B; + command_seq.data_phase.data_io_mode = single_io_mode; + } + } else { /* Only consider 1-1-1 Program */ + flash->nor_program_para.page_program_cmd = SERIALNOR_CMD_PAGEPROGRAM_1_1_1_4B; + command_seq.data_phase.data_io_mode = single_io_mode; + } + } else { + command_seq.addr_phase.addr_bit = flash_addrlen_24bit; + flash->nor_program_para.page_program_cmd = (flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_QUAD_IO_MODE) ? + SERIALNOR_CMD_PAGE_PROGRAM_1_1_4_3B : SERIALNOR_CMD_PAGEPROGRAM_1_1_1_3B; + + command_seq.data_phase.data_io_mode = (flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_QUAD_IO_MODE) ? + quad_io_mode : single_io_mode; + } + command_seq.cmd_phase.cmd = flash->nor_program_para.page_program_cmd; + command_seq.data_phase.direction = write_direction; + command_seq.use_dma = true; + command_seq.addr_phase.enable = true; + while (data_len > 0) { + /* Send page program command */ + program_size = MIN(data_len, remaining_page_size); + /* Ensure the address doesn't across page boundary */ + offset = address % flash->flash_info.page_size; + HPM_BREAK_IF((offset + program_size) > flash->flash_info.page_size); + stat = hpm_serial_nor_write_enable(flash); + if (stat != status_success) { + return stat; + } + command_seq.addr_phase.addr = address; + command_seq.data_phase.buf = buf; + command_seq.data_phase.len = program_size; + stat = flash->host.host_ops.transfer(flash->host.host_ops.user_data, &command_seq); + + HPM_BREAK_IF(stat != status_success); + stat = status_spi_nor_flash_is_busy; + while (stat == status_spi_nor_flash_is_busy) { + stat = hpm_serial_nor_is_busy(flash); + if ((stat != status_success) && (stat != status_spi_nor_flash_is_busy)) { + return stat; + } else { + if (stat == status_success) { + break; + } else { + if (stat == status_success) { + break; + } else { + hpm_spi_nor_udelay(1); + } + } + } + } + /* Get the new address and length for next iteration */ + address += program_size; + data_len -= program_size; + remaining_page_size = flash->flash_info.page_size; + src_8 = (uint8_t *) buf + program_size; + buf = (uint8_t *) src_8; + } + } while (false); + return stat; +} + +hpm_stat_t hpm_serial_nor_page_program_noblocking(hpm_serial_nor_t *flash, uint8_t *buf, uint32_t data_len, uint32_t address) +{ + hpm_stat_t stat = status_success; + uint32_t program_size = 0; + uint32_t offset_in_page; + uint32_t remaining_page_size; + uint32_t address_bits; + hpm_serial_nor_transfer_seq_t command_seq = {0}; + + if ((buf == NULL) || (data_len == 0) || (flash == NULL)) { + return status_invalid_argument; + } + + command_seq.addr_phase.addr_io_mode = single_io_mode; + command_seq.data_phase.data_io_mode = quad_io_mode; + offset_in_page = address % flash->flash_info.page_size; + remaining_page_size = flash->flash_info.page_size - offset_in_page; + program_size = MIN(data_len, remaining_page_size); + if ((data_len > flash->flash_info.page_size) || + ((offset_in_page + program_size) > flash->flash_info.page_size)) { + return status_invalid_argument; + } + + do { + offset_in_page = address % flash->flash_info.page_size; + remaining_page_size = flash->flash_info.page_size - offset_in_page; + address_bits = (flash->flash_info.size_in_kbytes > MAX_24BIT_ADDR_SIZE_IN_KBYTES) ? 32U : 24U; + if (address_bits == 32) { + command_seq.addr_phase.addr_bit = flash_addrlen_32bit; + if ((flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_QUAD_IO_MODE) && (flash->nor_program_para.has_4b_addressing_inst_table)) { + if (flash->nor_program_para.support_1_4_4_page_program > 0U) { + flash->nor_program_para.page_program_cmd = SERIALNOR_CMD_PAGEPROGRAM_1_4_4_4B; + command_seq.addr_phase.addr_io_mode = dual_io_mode; + } else if (flash->nor_program_para.support_1_1_4_page_program > 0U) { + flash->nor_program_para.page_program_cmd = SERIALNOR_CMD_PAGEPROGRAM_1_1_4_4B; + } else { + /* 1_1_1_page_program */ + flash->nor_program_para.page_program_cmd = SERIALNOR_CMD_PAGEPROGRAM_1_1_1_4B; + command_seq.data_phase.data_io_mode = single_io_mode; + } + } else { /* Only consider 1-1-1 Program */ + flash->nor_program_para.page_program_cmd = SERIALNOR_CMD_PAGEPROGRAM_1_1_1_4B; + command_seq.data_phase.data_io_mode = single_io_mode; + } + } else { + command_seq.addr_phase.addr_bit = flash_addrlen_24bit; + flash->nor_program_para.page_program_cmd = (flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_QUAD_IO_MODE) ? + SERIALNOR_CMD_PAGE_PROGRAM_1_1_4_3B : SERIALNOR_CMD_PAGEPROGRAM_1_1_1_3B; + + command_seq.data_phase.data_io_mode = (flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_QUAD_IO_MODE) ? + quad_io_mode : single_io_mode; + } + command_seq.cmd_phase.cmd = flash->nor_program_para.page_program_cmd; + stat = hpm_serial_nor_write_enable(flash); + if (stat != status_success) { + return stat; + } + command_seq.use_dma = true; + command_seq.addr_phase.addr = address; + command_seq.data_phase.buf = buf; + command_seq.data_phase.len = program_size; + command_seq.data_phase.direction = write_direction; + command_seq.addr_phase.enable = true; + stat = flash->host.host_ops.transfer(flash->host.host_ops.user_data, &command_seq); + HPM_BREAK_IF(stat != status_success); + } while (false); + + return stat; +} + +hpm_stat_t hpm_serial_nor_read(hpm_serial_nor_t *flash, uint8_t *buf, uint16_t data_len, uint32_t address) +{ + hpm_stat_t stat; + hpm_serial_nor_transfer_seq_t command_seq = {0}; + uint32_t read_start = address; + + if ((buf == NULL) || (data_len == 0) || (flash == NULL)) { + return status_invalid_argument; + } + + command_seq.addr_phase.addr = read_start; + command_seq.addr_phase.addr_bit = flash->nor_read_para.addr_bit; + command_seq.addr_phase.addr_io_mode = flash->nor_read_para.addr_phase_format; + command_seq.dummy_phase.dummy_count = flash->nor_read_para.data_dummy_count; + command_seq.data_phase.data_io_mode = flash->nor_read_para.data_phase_format; + command_seq.data_phase.buf = buf; + command_seq.data_phase.len = data_len; + command_seq.cmd_phase.cmd = flash->nor_read_para.read_cmd; + command_seq.data_phase.direction = read_direction; + command_seq.use_dma = true; + command_seq.addr_phase.enable = true; + stat = flash->host.host_ops.transfer(flash->host.host_ops.user_data, &command_seq); + return stat; +} + + +hpm_stat_t hpm_serial_nor_init(hpm_serial_nor_t *flash, hpm_serial_nor_info_t *info) +{ + jedec_info_table_t jedec_info; + hpm_stat_t stat; + if (flash == NULL) { + return status_invalid_argument; + } + if (flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_SPI_INTERFACE) { + serial_nor_host_ops_use_spi(flash); + } else { + /* Reserved for use by other interfaces */ + } + flash->host.host_ops.user_data = &flash->host; + flash->host.host_ops.init(flash->host.host_ops.user_data); + /* in order to ensure read sfdp parameter are correct, spi frequency must be less than 50M, and here,default value is 20M */ + flash->host.host_ops.set_frequency(flash->host.host_ops.user_data, SPI_READ_SFDP_FREQUENCY); + stat = hpm_serial_nor_read_sfdp_info(flash, &jedec_info, false); + if (stat != status_success) { + return stat; + } + flash->host.host_ops.set_frequency(flash->host.host_ops.user_data, flash->host.host_param.param.frequency); + get_page_sector_block_size_from_sfdp(&flash->flash_info, &jedec_info); + memcpy(info, &flash->flash_info, sizeof(hpm_serial_nor_info_t)); + if (flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_QUAD_IO_MODE) { + stat = prepare_quad_mode_enable_sequence(flash, &jedec_info); + flash->flash_info.sfdp_version = jedec_info.standard_version; + info->sfdp_version = jedec_info.standard_version; + if (stat != status_success) { + flash->host.host_param.flags &= ~SERIAL_NOR_HOST_SUPPORT_QUAD_IO_MODE | SERIAL_NOR_HOST_SUPPORT_SINGLE_IO_MODE; + } + } + hpm_spi_get_read_para(flash, &jedec_info); + hpm_spi_get_program_para(flash, &jedec_info); + return stat; +} + +hpm_stat_t hpm_serial_nor_get_info(hpm_serial_nor_t *flash, hpm_serial_nor_info_t *info) +{ + if (flash == NULL) { + return status_invalid_argument; + } + memcpy(info, &flash->flash_info, sizeof(hpm_serial_nor_info_t)); + return status_success; +} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/hpm_serial_nor.h b/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/hpm_serial_nor.h new file mode 100644 index 00000000000..bcd81e4f788 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/hpm_serial_nor.h @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_SERIAL_NOR_H +#define _HPM_SERIAL_NOR_H + +#include "hpm_serial_nor_host.h" + +/** + * @brief spi nor API error codes + */ +enum { + status_spi_nor_sfdp_not_found = MAKE_STATUS(status_group_spi_nor_flash, 0), /**< SFDP table was not found */ + status_spi_nor_ddr_read_dummy_cycle_probe_failed = MAKE_STATUS(status_group_spi_nor_flash, 1), /**< Probing Dummy cyles for DDR read failed */ + status_spi_nor_flash_not_found = MAKE_STATUS(status_group_spi_nor_flash, 2), /**< FLASH was not detected */ + status_spi_nor_flash_para_err = MAKE_STATUS(status_group_spi_nor_flash, 3), + status_spi_nor_flash_is_busy = MAKE_STATUS(status_group_spi_nor_flash, 4), + status_spi_nor_flash_not_qe_bit_in_sfdp = MAKE_STATUS(status_group_spi_nor_flash, 5), +}; + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @brief determine whether the serial nor flash is busy + * @param [in] host the serial nor context + * @return hpm_stat_t: status_spi_nor_flash_is_busy if the serial nor flash is busy + */ +hpm_stat_t hpm_serial_nor_is_busy(hpm_serial_nor_t *flash); + +/** + * @brief set serial nor flash write enable + * @param [in] channel serial nor flash channel + * @return hpm_stat_t: status_success if write enable success + */ +hpm_stat_t hpm_serial_nor_write_enable(hpm_serial_nor_t *flash); + +/** + * @brief erase the serial nor flash chip + * @param [in] host the serial nor context + * @return hpm_stat_t: status_success if erase chip success + */ +hpm_stat_t hpm_serial_nor_erase_chip(hpm_serial_nor_t *flash); + +/** + * @brief erase the serial nor flash block using blocking transfer + * + * @note the erase block address must be block alignment + * + * @param [in] host the serial nor context + * @param [in] block_addr the serial nor flash block address + * @return hpm_stat_t: status_success if erase block success + */ +hpm_stat_t hpm_serial_nor_erase_block_blocking(hpm_serial_nor_t *flash, uint32_t block_addr); + +/** + * @brief erase the serial nor flash block using noblocking transfer + * + * @note the erase block address must be block alignment, it'not wait flash busy status. + * + * @param [in] host the serial nor context + * @param [in] block_addr the serial nor flash block address + * @return hpm_stat_t: status_success if erase block success + */ +hpm_stat_t hpm_serial_nor_erase_block_noblocking(hpm_serial_nor_t *flash, uint32_t block_addr); + +/** + * @brief erase the serial nor flash sector using blocking transfer + * + * @note the erase sector address must be sector alignment + * + * @param [in] host the serial nor context + * @param [in] sector_addr the serial nor flash sector address + * @return hpm_stat_t: status_success if erase sector success + */ +hpm_stat_t hpm_serial_nor_erase_sector_blocking(hpm_serial_nor_t *flash, uint32_t sector_addr); + +/** + * @brief erase the serial nor flash sector using noblocking transfer + * + * @note the erase sector address must be sector alignment, it'not wait flash busy status. + * + * @param [in] host the serial nor context + * @param [in] sector_addr the serial nor flash sector address + * @return hpm_stat_t: status_success if erase sector success + */ +hpm_stat_t hpm_serial_nor_erase_sector_noblocking(hpm_serial_nor_t *flash, uint32_t sector_addr); + +/** + * @brief erase the serial nor flash specified start address and length using blocking transfer + * + * @note the erase sector address must be sector alignment + * + * @param [in] host the serial nor context + * @param [in] sector_addr the serial nor flash sector address + * @return hpm_stat_t: status_success if erase success + */ +hpm_stat_t hpm_serial_nor_erase_blocking(hpm_serial_nor_t *flash, uint32_t start, uint32_t length); + +/** + * @brief program data to the specified serial nor flash address using blocking transfer + * @param [in] host the serial nor context + * @param [in] buf the data source pointer + * @param [in] data_len the data length + * @param [in] address the serial nor flash programming address + * @return hpm_stat_t: status_success if program success + */ +hpm_stat_t hpm_serial_nor_program_blocking(hpm_serial_nor_t *flash, uint8_t *buf, uint32_t data_len, + uint32_t address); + +/** + * @brief program data to the page nor flash address using noblocking transfer + * @param [in] host the serial nor context + * @param [in] buf the data source pointer + * @param [in] data_len the data length + * @param [in] address the serial nor flash programming address + * @return hpm_stat_t: status_success if program success + */ +hpm_stat_t hpm_serial_nor_page_program_noblocking(hpm_serial_nor_t *flash, uint8_t *buf, + uint32_t data_len, + uint32_t address); + +/** + * @brief read the data of specified serial nor flash address + * @param [in] host the serial nor context + * @param [in] buf the data source pointer + * @param [in] data_len the data length + * @param [in] address the serial nor flash reading address + * @return hpm_stat_t: status_success if read success + */ +hpm_stat_t hpm_serial_nor_read(hpm_serial_nor_t *flash, uint8_t *buf, uint16_t data_len, + uint32_t address); + +/** + * @brief the serial nor flash initialization + * @param [in] host the serial nor context + * @param [out] info serial_nor_flash_info_t + * @return hpm_stat_t: status_success if initialization success + */ +hpm_stat_t hpm_serial_nor_init(hpm_serial_nor_t *flash, hpm_serial_nor_info_t *info); + +/** + * @brief get the serial nor flash information + * @param [in] host the serial nor context + * @param [out] info serial_nor_flash_info_t + * @return hpm_stat_t: status_success if get information success + */ +hpm_stat_t hpm_serial_nor_get_info(hpm_serial_nor_t *flash, hpm_serial_nor_info_t *info); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/hpm_serial_nor_host.h b/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/hpm_serial_nor_host.h new file mode 100644 index 00000000000..78c2246099c --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/hpm_serial_nor_host.h @@ -0,0 +1,204 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_SERIAL_NOR_HOST_H +#define _HPM_SERIAL_NOR_HOST_H +#include "hpm_common.h" +#include "sfdp_def.h" + +#define SERIAL_NOR_HOST_SUPPORT_SINGLE_IO_MODE (1UL << 0) +#define SERIAL_NOR_HOST_SUPPORT_DUAL_IO_MODE (1UL << 1) +#define SERIAL_NOR_HOST_SUPPORT_QUAD_IO_MODE (1UL << 2) +#define SERIAL_NOR_HOST_SUPPORT_SPI_INTERFACE (1UL << 3) +#define SERIAL_NOR_HOST_SUPPORT_DMA (1UL << 8) +#define SERIAL_NOR_HOST_CS_CONTROL_AUTO (1UL << 9) + +/** + * @brief IO mode of serial nor flash sequence + */ +typedef enum { + single_io_mode = 0, + dual_io_mode, + quad_io_mode +} hpm_serial_nor_seq_io_mode_t; + +/** + * @brief number of address bits of serial nor flash sequence + */ +typedef enum { + flash_addrlen_24bit = 0, + flash_addrlen_32bit +} hpm_serial_nor_seq_addr_bit_t; + +/** + * @brief transfer direction serial nor flash sequence + */ +typedef enum { + write_direction = 0, + read_direction +} hpm_serial_nor_seq_direction_t; + +/** + * @brief information of serial nor flash + */ +typedef struct { + uint8_t en_dev_mode_cfg; + uint8_t sfdp_version; + uint8_t sector_erase_cmd; + uint8_t block_erase_cmd; + uint32_t size_in_kbytes; + uint16_t page_size; + uint16_t sector_size_kbytes; + uint16_t block_size_kbytes; +} hpm_serial_nor_info_t; + +/** + * @brief dma control param of serial nor flash host + */ +typedef struct { + uint8_t rx_dma_ch; + uint8_t tx_dma_ch; + uint8_t rx_dma_req; + uint8_t tx_dma_req; + void *dma_base; + void *dmamux_base; +} hpm_nor_host_dma_control_t; + +/** + * @brief param and operation of serial nor flash host + */ +typedef struct { + uint8_t pin_or_cs_index; + hpm_nor_host_dma_control_t dma_control; + uint32_t clock_name; + uint32_t frequency; + uint32_t transfer_max_size; + void *host_base; + void (*set_cs)(uint32_t cs_pin, uint8_t state); + void (*set_frequency)(void *host, uint32_t freq); +} hpm_nor_host_param_t; + +/** + * @brief spi nor read parameters structure + */ +typedef struct { + uint8_t read_cmd; + uint8_t data_dummy_count; + hpm_serial_nor_seq_addr_bit_t addr_bit; + hpm_serial_nor_seq_io_mode_t data_phase_format; + hpm_serial_nor_seq_io_mode_t addr_phase_format; +} hpm_sfdp_read_para_t; + +/** + * @brief spi nor program parameters structure + */ +typedef struct { + bool has_4b_addressing_inst_table; + bool support_1_4_4_page_program; + bool support_1_1_4_page_program; + uint8_t page_program_cmd; +} hpm_sfdp_program_para_t; + +/** + * @brief param of serial nor flash host + */ +typedef struct { + uint32_t flags; + hpm_nor_host_param_t param; + void *user_data; +} hpm_serial_nor_host_param_t; + +/** + * @brief operation sequence of serial nor flash + * + * @note it's include command + address(optional) + dummy(optional) + data(optional) + * + */ +typedef struct { + /* can choose whether to use DMA in a transfer, even if the flags has DMA*/ + uint8_t use_dma; + + struct { + uint8_t cmd; + } cmd_phase; + + struct { + bool enable; + hpm_serial_nor_seq_addr_bit_t addr_bit; + hpm_serial_nor_seq_io_mode_t addr_io_mode; + uint32_t addr; + } addr_phase; + + struct { + uint8_t dummy_count; + } dummy_phase; + + struct { + /* the operation direction of the data phase, it's include write and read */ + hpm_serial_nor_seq_direction_t direction; + /* the SPI operation mode of the data phase, it's include SPI/DUAL SPI/QUAD SPI and so on */ + hpm_serial_nor_seq_io_mode_t data_io_mode; + uint32_t len; + uint8_t *buf; + } data_phase; + +} hpm_serial_nor_transfer_seq_t; + +/** + * @brief operation of serial nor flash host + */ +typedef struct { + hpm_stat_t (*init)(void *host); + + hpm_stat_t (*transfer)(void *host, hpm_serial_nor_transfer_seq_t *command_seq); + + void (*set_cs)(uint32_t cs_pin, uint8_t state); + + void (*set_frequency)(void *host, uint32_t freq); + + void *user_data; +} serial_nor_host_ops_t; + +/** + * @brief serial nor flash host parameters structure + */ +typedef struct { + hpm_serial_nor_host_param_t host_param; + serial_nor_host_ops_t host_ops; + void *user_data; +} hpm_serial_nor_host_t; + +/** + * @brief serial nor flash parameters structure + */ +typedef struct { + hpm_serial_nor_host_t host; + hpm_sfdp_read_para_t nor_read_para; + hpm_sfdp_program_para_t nor_program_para; + hpm_serial_nor_info_t flash_info; +} hpm_serial_nor_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief serial nor host operation is use spi operation + * @param [in] dev serial nor device + * @return hpm_stat_t: status_success if success + */ +hpm_stat_t serial_nor_host_ops_use_spi(hpm_serial_nor_t *dev); +/** + * @} + * + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/interface/spi/hpm_serial_nor_host_spi.c b/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/interface/spi/hpm_serial_nor_host_spi.c new file mode 100644 index 00000000000..6512d6e4d6e --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/interface/spi/hpm_serial_nor_host_spi.c @@ -0,0 +1,369 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifdef HPMSOC_HAS_HPMSDK_DMAV2 +#include "hpm_dmav2_drv.h" +#else +#include "hpm_dma_drv.h" +#endif +#include "hpm_dmamux_drv.h" +#include "hpm_spi_drv.h" +#include "hpm_l1c_drv.h" +#include "board.h" +#include "hpm_serial_nor_host.h" + +static hpm_stat_t spi_nor_rx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, SPI_Type *spi_ptr, + uint32_t dst, uint8_t data_width, uint32_t size, uint8_t burst_size); + +static hpm_stat_t spi_nor_rx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, SPI_Type *spi_ptr, uint32_t dst, + uint8_t data_width, uint32_t size, uint8_t burst_size); + +static void hpm_config_cmd_addr_format(void *ops, hpm_serial_nor_transfer_seq_t *cmd_seq, spi_control_config_t *control_config); + +static hpm_stat_t hpm_spi_transfer_via_dma(hpm_serial_nor_host_t *host, spi_control_config_t *control_config, + uint8_t cmd, uint32_t addr, + uint8_t *buf, uint32_t len, bool is_read); + +static hpm_stat_t transfer(void *host, hpm_serial_nor_transfer_seq_t *command_seq); + +static hpm_stat_t init(void *ops); + +static hpm_stat_t write(void *ops, hpm_serial_nor_transfer_seq_t *cmd_seq); + +static hpm_stat_t read(void *ops, hpm_serial_nor_transfer_seq_t *cmd_seq); + +ATTR_WEAK hpm_stat_t serial_nor_host_ops_use_spi(hpm_serial_nor_t *dev) +{ + if (dev == NULL) { + return status_invalid_argument; + } + dev->host.host_ops.init = init; + dev->host.host_ops.transfer = transfer; + dev->host.host_ops.set_cs = dev->host.host_param.param.set_cs; + dev->host.host_ops.set_frequency = dev->host.host_param.param.set_frequency; + return status_success; +} + +static hpm_stat_t transfer(void *host, hpm_serial_nor_transfer_seq_t *command_seq) +{ + hpm_stat_t stat = status_success; + if (command_seq->data_phase.direction == read_direction) { + stat = read(host, command_seq); + } else { + stat = write(host, command_seq); + } + return stat; +} + +static hpm_stat_t spi_nor_tx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, SPI_Type *spi_ptr, + uint32_t src, uint8_t data_width, uint32_t size, uint8_t burst_size) +{ + hpm_stat_t stat; + dma_channel_config_t config; + if (ch_num >= DMA_SOC_CHANNEL_NUM) { + return status_invalid_argument; + } + dma_default_channel_config(dma_ptr, &config); + config.dst_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; + config.dst_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; + config.src_addr_ctrl = DMA_ADDRESS_CONTROL_INCREMENT; + config.src_mode = DMA_HANDSHAKE_MODE_NORMAL; + config.src_width = data_width; + config.dst_width = data_width; + config.src_addr = src; + config.dst_addr = (uint32_t)&spi_ptr->DATA; + config.size_in_byte = size; + config.src_burst_size = burst_size; + stat = dma_setup_channel(dma_ptr, ch_num, &config, true); + if (stat != status_success) { + return stat; + } + return stat; +} + +static hpm_stat_t spi_nor_rx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, SPI_Type *spi_ptr, uint32_t dst, + uint8_t data_width, uint32_t size, uint8_t burst_size) +{ + hpm_stat_t stat; + dma_channel_config_t config; + if (ch_num >= DMA_SOC_CHANNEL_NUM) { + return status_invalid_argument; + } + dma_default_channel_config(dma_ptr, &config); + config.dst_addr_ctrl = DMA_ADDRESS_CONTROL_INCREMENT; + config.dst_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; + config.src_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; + config.src_mode = DMA_HANDSHAKE_MODE_NORMAL; + config.src_width = data_width; + config.dst_width = data_width; + config.src_addr = (uint32_t)&spi_ptr->DATA; + config.dst_addr = dst; + config.size_in_byte = size; + config.src_burst_size = burst_size; + stat = dma_setup_channel(dma_ptr, ch_num, &config, true); + if (stat != status_success) { + return stat; + } + return stat; +} + +static void hpm_config_cmd_addr_format(void *ops, hpm_serial_nor_transfer_seq_t *cmd_seq, spi_control_config_t *control_config) +{ + spi_trans_mode_t _trans_mode; + hpm_serial_nor_host_t *host = (hpm_serial_nor_host_t *)ops; + control_config->master_config.cmd_enable = true; + + /* judge the valid of addr */ + if (cmd_seq->addr_phase.enable == true) { + control_config->master_config.addr_enable = true; + if (cmd_seq->addr_phase.addr_io_mode == single_io_mode) { + control_config->master_config.addr_phase_fmt = spi_address_phase_format_single_io_mode; + } else { + control_config->master_config.addr_phase_fmt = spi_address_phase_format_dualquad_io_mode; + } + if (cmd_seq->addr_phase.addr_bit == flash_addrlen_24bit) { + spi_set_address_len((SPI_Type *)host->host_param.param.host_base, addrlen_24bit); + } else { + spi_set_address_len((SPI_Type *)host->host_param.param.host_base, addrlen_32bit); + } + } else { + control_config->master_config.addr_enable = false; + } + + /* judge the valid of buf */ + if ((cmd_seq->data_phase.buf != NULL) || (cmd_seq->data_phase.len != 0)) { + if (cmd_seq->dummy_phase.dummy_count == 0) { + _trans_mode = (cmd_seq->data_phase.direction == read_direction) ? spi_trans_read_only : spi_trans_write_only; + } else { + control_config->common_config.dummy_cnt = cmd_seq->dummy_phase.dummy_count - 1; + _trans_mode = (cmd_seq->data_phase.direction == read_direction) ? spi_trans_dummy_read : spi_trans_dummy_write; + } + control_config->common_config.trans_mode = _trans_mode; + + if ((cmd_seq->data_phase.data_io_mode == single_io_mode) + || (host->host_param.flags & SERIAL_NOR_HOST_SUPPORT_SINGLE_IO_MODE)) { + control_config->common_config.data_phase_fmt = spi_single_io_mode; + } else if (cmd_seq->data_phase.data_io_mode == dual_io_mode) { + control_config->common_config.data_phase_fmt = spi_dual_io_mode; + } else { + control_config->common_config.data_phase_fmt = spi_quad_io_mode; + } + } else { + control_config->common_config.trans_mode = spi_trans_no_data; + } +} + +static hpm_stat_t init(void *ops) +{ + spi_format_config_t format_config = {0}; + hpm_serial_nor_host_t *host = (hpm_serial_nor_host_t *)ops; + if ((host == NULL) || (host->host_param.param.host_base == NULL)) { + return status_invalid_argument; + } + spi_master_get_default_format_config(&format_config); + format_config.common_config.data_len_in_bits = 8; + format_config.common_config.mode = spi_master_mode; + format_config.common_config.cpol = spi_sclk_low_idle; + format_config.common_config.cpha = spi_sclk_sampling_odd_clk_edges; + format_config.common_config.data_merge = false; + spi_format_init(host->host_param.param.host_base, &format_config); + if (host->host_param.flags & SERIAL_NOR_HOST_SUPPORT_DMA) { + if ((host->host_param.param.dma_control.dma_base == NULL) || (host->host_param.param.dma_control.dmamux_base == NULL)) { + return status_invalid_argument; + } + dmamux_config(host->host_param.param.dma_control.dmamux_base, + DMA_SOC_CHN_TO_DMAMUX_CHN(host->host_param.param.dma_control.dma_base, + host->host_param.param.dma_control.rx_dma_ch), + host->host_param.param.dma_control.rx_dma_req, true); + + dmamux_config(host->host_param.param.dma_control.dmamux_base, + DMA_SOC_CHN_TO_DMAMUX_CHN(host->host_param.param.dma_control.dma_base, + host->host_param.param.dma_control.tx_dma_ch), + host->host_param.param.dma_control.tx_dma_req, true); + } + return status_success; +} + +static hpm_stat_t hpm_spi_transfer_via_dma(hpm_serial_nor_host_t *host, spi_control_config_t *control_config, + uint8_t cmd, uint32_t addr, + uint8_t *buf, uint32_t len, bool is_read) +{ + hpm_stat_t stat; + uint32_t data_width = 0; + uint8_t burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; + uint32_t timeout_count = 0; + uint16_t dma_send_size; + if (is_read) { + /*The supplement of the byte less than the integer multiple of four bytes is an integer multiple of four bytes to DMA*/ + data_width = DMA_TRANSFER_WIDTH_WORD; + if ((len % 4) == 0) { + dma_send_size = len; + } else { + dma_send_size = ((len >> 2) + 1) << 2; + } + stat = spi_setup_dma_transfer((SPI_Type *)host->host_param.param.host_base, control_config, &cmd, &addr, 0, len); + stat = spi_nor_rx_trigger_dma((DMA_Type *)host->host_param.param.dma_control.dma_base, + host->host_param.param.dma_control.rx_dma_ch, + (SPI_Type *)host->host_param.param.host_base, + core_local_mem_to_sys_address(BOARD_RUNNING_CORE, (uint32_t)buf), + data_width, + dma_send_size, burst_size); + while (spi_is_active((SPI_Type *)host->host_param.param.host_base)) { + timeout_count++; + if (timeout_count >= 0xFFFFFF) { + stat = status_timeout; + break; + } + } + timeout_count = 0; + if ((dma_check_transfer_status( + (DMA_Type *)host->host_param.param.dma_control.dma_base, + host->host_param.param.dma_control.rx_dma_ch) && + DMA_CHANNEL_STATUS_TC) == 0) { + dma_disable_channel((DMA_Type *)host->host_param.param.dma_control.dma_base, host->host_param.param.dma_control.rx_dma_ch); + dma_reset((DMA_Type *)host->host_param.param.dma_control.dma_base); + } + } else { + if ((len % 4) == 0) { + spi_enable_data_merge((SPI_Type *)host->host_param.param.host_base); + data_width = DMA_TRANSFER_WIDTH_WORD; + } else { + data_width = DMA_TRANSFER_WIDTH_BYTE; + } + spi_set_tx_fifo_threshold((SPI_Type *)host->host_param.param.host_base, 3); + burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; + stat = spi_setup_dma_transfer((SPI_Type *)host->host_param.param.host_base, control_config, &cmd, &addr, len, 0); + + stat = spi_nor_tx_trigger_dma((DMA_Type *)host->host_param.param.dma_control.dma_base, + host->host_param.param.dma_control.tx_dma_ch, + (SPI_Type *)host->host_param.param.host_base, + core_local_mem_to_sys_address(BOARD_RUNNING_CORE, (uint32_t)buf), + data_width, len, burst_size); + + while (spi_is_active((SPI_Type *)host->host_param.param.host_base)) { + timeout_count++; + if (timeout_count >= 0xFFFFFF) { + stat = status_timeout; + break; + } + } + timeout_count = 0; + spi_disable_data_merge((SPI_Type *)host->host_param.param.host_base); + } + return stat; +} +static hpm_stat_t write(void *ops, hpm_serial_nor_transfer_seq_t *cmd_seq) +{ + hpm_stat_t stat = status_success; + spi_control_config_t control_config = {0}; + hpm_serial_nor_host_t *host = (hpm_serial_nor_host_t *)ops; + uint32_t aligned_start; + uint32_t aligned_end; + uint32_t aligned_size; + if ((cmd_seq->data_phase.len > host->host_param.param.transfer_max_size) || (host == NULL) + || (host->host_param.param.host_base == NULL)) { + return status_invalid_argument; + } + + if (!(host->host_param.flags & SERIAL_NOR_HOST_CS_CONTROL_AUTO)) { + if (host->host_param.param.set_cs == NULL) { + return status_fail; + } + host->host_param.param.set_cs(host->host_param.param.pin_or_cs_index, false); + } + + spi_master_get_default_control_config(&control_config); + hpm_config_cmd_addr_format(ops, cmd_seq, &control_config); + + if ((host->host_param.flags & SERIAL_NOR_HOST_SUPPORT_DMA) && (cmd_seq->use_dma == 1)) { + control_config.common_config.tx_dma_enable = true; + control_config.common_config.rx_dma_enable = false; + if (l1c_dc_is_enabled()) { + /* cache writeback for sent buff */ + aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)cmd_seq->data_phase.buf); + aligned_end = HPM_L1C_CACHELINE_ALIGN_UP((uint32_t)cmd_seq->data_phase.buf + cmd_seq->data_phase.len); + aligned_size = aligned_end - aligned_start; + l1c_dc_writeback(aligned_start, aligned_size); + } + stat = hpm_spi_transfer_via_dma(host, &control_config, cmd_seq->cmd_phase.cmd, cmd_seq->addr_phase.addr, + (uint8_t *)cmd_seq->data_phase.buf, cmd_seq->data_phase.len, false); + } else { + stat = spi_transfer((SPI_Type *)host->host_param.param.host_base, &control_config, + &cmd_seq->cmd_phase.cmd, &cmd_seq->addr_phase.addr, + cmd_seq->data_phase.buf, cmd_seq->data_phase.len, NULL, 0); + } + if (!(host->host_param.flags & SERIAL_NOR_HOST_CS_CONTROL_AUTO)) { + host->host_param.param.set_cs(host->host_param.param.pin_or_cs_index, true); + } + return stat; +} + +static hpm_stat_t read(void *ops, hpm_serial_nor_transfer_seq_t *cmd_seq) +{ + hpm_stat_t stat = status_success; + uint32_t aligned_start; + uint32_t aligned_end; + uint32_t aligned_size; + spi_control_config_t control_config = {0}; + hpm_serial_nor_host_t *host = (hpm_serial_nor_host_t *)ops; + uint32_t read_size = 0; + uint32_t read_start = cmd_seq->addr_phase.addr; + uint8_t *dst_8 = (uint8_t *) cmd_seq->data_phase.buf; + uint32_t remaining_len = cmd_seq->data_phase.len; + + if ((host == NULL) || (host->host_param.param.host_base == NULL)) { + return status_invalid_argument; + } + if (!(host->host_param.flags & SERIAL_NOR_HOST_CS_CONTROL_AUTO)) { + if (host->host_param.param.set_cs == NULL) { + return status_fail; + } + } + + spi_master_get_default_control_config(&control_config); + hpm_config_cmd_addr_format(ops, cmd_seq, &control_config); + + if ((host->host_param.flags & SERIAL_NOR_HOST_SUPPORT_DMA) && (cmd_seq->use_dma == 1)) { + if (host->host_param.param.dma_control.dma_base == NULL) { + return status_fail; + } + if (((uint32_t)dst_8 % HPM_L1C_CACHELINE_SIZE) != 0) { + return status_invalid_argument; + } + control_config.common_config.tx_dma_enable = false; + control_config.common_config.rx_dma_enable = true; + } + while (remaining_len > 0U) { + if (!(host->host_param.flags & SERIAL_NOR_HOST_CS_CONTROL_AUTO)) { + host->host_param.param.set_cs(host->host_param.param.pin_or_cs_index, false); + } + read_size = MIN(remaining_len, host->host_param.param.transfer_max_size); + if ((host->host_param.flags & SERIAL_NOR_HOST_SUPPORT_DMA) && (cmd_seq->use_dma == 1)) { + spi_enable_data_merge((SPI_Type *)host->host_param.param.host_base); + stat = hpm_spi_transfer_via_dma(host, &control_config, cmd_seq->cmd_phase.cmd, read_start, dst_8, read_size, true); + } else { + stat = spi_transfer((SPI_Type *)host->host_param.param.host_base, &control_config, &cmd_seq->cmd_phase.cmd, + &read_start, NULL, 0, dst_8, read_size); + } + HPM_BREAK_IF(stat != status_success); + if (l1c_dc_is_enabled()) { + /* cache invalidate for receive buff */ + aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)dst_8); + aligned_end = HPM_L1C_CACHELINE_ALIGN_UP(read_size); + aligned_size = aligned_end - aligned_start; + l1c_dc_invalidate(aligned_start, aligned_size); + } + read_start += read_size; + remaining_len -= read_size; + dst_8 += read_size; + if (!(host->host_param.flags & SERIAL_NOR_HOST_CS_CONTROL_AUTO)) { + host->host_param.param.set_cs(host->host_param.param.pin_or_cs_index, true); + } + } + spi_disable_data_merge((SPI_Type *)host->host_param.param.host_base); + return stat; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/sfdp_def.h b/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/sfdp_def.h index 14cfbe9ef16..20184cef132 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/sfdp_def.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/sfdp_def.h @@ -9,22 +9,22 @@ #include "hpm_common.h" /* ! @brief Commands for probing the FLASH device */ -#define kSerialFlash_ReadSFDP (0x5AU) -#define kSerialFlash_ReadManufacturerId (0x9FU) +#define SERIAL_FLASH_READ_SFDP (0x5AU) +#define SERIAL_FLASH_READ_MANUFACTURE_ID (0x9FU) /* !@brief SFDP related definitions */ #define SFDP_SIGNATURE (0x50444653UL) /* ASCII: SFDP */ -#define kSfdp_Version_Major_1_0 (1U) -#define kSfdp_Version_Minor_0 (0U) /* JESD216 */ -#define kSfdp_Version_Minor_A (5U) /* JESD216A */ -#define kSfdp_Version_Minor_B (6U) /* JESD216B */ -#define kSfdp_Version_Minor_C (7U) /* JESD216C */ -#define kSfdp_Version_Minor_D (8U) /* JESD216D */ -#define kSfdp_BasicProtocolTableSize_Rev0 (36U) -#define kSfdp_BasicProtocolTableSize_RevA (64U) -#define kSfdp_BasicProtocolTableSize_RevB kSfdp_BasicProtocolTableSize_RevA -#define kSfdp_BasicProtocolTableSize_RevC (80U) -#define kSfdp_BasicProtocolTableSize_RevD kSfdp_BasicProtocolTableSize_RevC +#define SFDP_VERSION_MAJOR_1_0 (1U) +#define SFDP_VERSION_MINOR_0 (0U) /* JESD216 */ +#define SFDP_VERSION_MINOR_A (5U) /* JESD216A */ +#define SFDP_VERSION_MINOR_B (6U) /* JESD216B */ +#define SFDP_VERSION_MINOR_C (7U) /* JESD216C */ +#define SFDP_VERSION_MINOR_D (8U) /* JESD216D */ +#define SFDP_BASIC_PROTOCOL_TABLE_SIZE_REV0 (36U) +#define SFDP_BASIC_PROTOCOL_TABLE_SIZE_REVA (64U) +#define SFDP_BASIC_PROTOCOL_TABLE_SIZE_REVB SFDP_BASIC_PROTOCOL_TABLE_SIZE_REVA +#define SFDP_BASIC_PROTOCOL_TABLE_SIZE_REVC (80U) +#define SFDP_BASIC_PROTOCOL_TABLE_SIZE_REVD SFDP_BASIC_PROTOCOL_TABLE_SIZE_REVC typedef union _sfdp_header { uint32_t words[2]; @@ -39,28 +39,28 @@ typedef union _sfdp_header { } sfdp_header_t; /* !@brief SFDP parameter Type ID definitions */ -#define kParameterID_BasicSpiProtocol (0xFF00U) +#define PARAMETER_ID_BASIC_SPIPROTOCOL (0xFF00U) /* New Table added in JESD216B */ -#define kParameterID_SectorMap (0xFF81U) -#define kParameterID_4ByteAddressInstructionTable (0xFF84U) +#define PARAMETER_ID_SECTOR_MAP (0xFF81U) +#define PARAMETER_ID_4BYTEADDRESS_INSTRUCTION_TABLE (0xFF84U) /* New Table added in JESD216C */ -#define kParameterID_xSpiProfile1_0 (0xFF05U) -#define kParameterID_xSpiOrofile2_0 (0xFF06U) -#define kParameterID_StaCtrlCfgRegMap (0xFF87U) -#define kParameterID_OpiEnableSeq (0xFF09U) -#define kParameterID_CmdSeqChangeToOctalDdr (0xFF0AU) +#define PARAMETER_ID_XSPIPROFILE1_0 (0xFF05U) +#define PARAMETER_ID_XSPIOROFILE2_0 (0xFF06U) +#define PARAMETER_ID_STACTRLCFGREGMAP (0xFF87U) +#define PARAMETER_ID_OPIENABLESEQ (0xFF09U) +#define PARAMETER_ID_CMDSEQ_CHANGE_TO_OCTAL_DDR (0xFF0AU) -#define kNorFlash_AddressBits_3B (0U) -#define kNorFlash_AddressBits_3B_4B (1U) -#define kNorFlash_AddressBits_4B (2U) +#define NORFLASH_ADDRESSBITS_3B (0U) +#define NORFLASH_ADDRESSBITS_3B_4B (1U) +#define NORFLASH_ADDRESSBITS_4B (2U) -#define kCommandExtensionSameAsCommand (0U) -#define kCommandExtensionInverseOfCommand (1U) -#define kCommandAndCommandExtension16BitWord (2U) +#define COMMAND_EXTENSION_SAME_AS_COMMAND (0U) +#define COMMAND_EXTENSION_INVERSE_OF_COMMAND (1U) +#define COMMAND_AND_COMMANDEXTENSION_16BITWORD (2U) /* !@brief Supported methods to enter 8-8-8 mode from 1-1-1 mode, More details please refer to JESD216C/D */ -#define kEnterOctalMode_Option0 HPM_BITSMASK(1U, 1) -#define kEnterOctalMode_Option1 HPM_BITSMASK(1U, 2) +#define ENTER_OCTAL_MODE_OPTION0 HPM_BITSMASK(1U, 1) +#define ENTER_OCTAL_MODE_OPTION1 HPM_BITSMASK(1U, 2) /* !@brief SFDP Parameter Header, see JESD216D doc for more details */ typedef union _sfdp_parameter_header { @@ -104,12 +104,12 @@ typedef union _jedec_flash_param_table { uint32_t inst_1_1_4_read : 8; } read_1_4_info; /* 3rd word */ struct { - uint32_t dummy_clocks_1_2_2_read : 5; - uint32_t mode_clocks_1_2_2_read : 3; - uint32_t inst_1_2_2_read : 8; uint32_t dummy_clocks_1_1_2_read : 5; uint32_t mode_clocks_1_1_2_read : 3; uint32_t inst_1_1_2_read : 8; + uint32_t dummy_clocks_1_2_2_read : 5; + uint32_t mode_clocks_1_2_2_read : 3; + uint32_t inst_1_2_2_read : 8; } read_1_2_info; /* 4th word */ struct { @@ -373,30 +373,30 @@ typedef struct _jdec_query_table { /* !@brief Typical Serial NOR commands supported by most Serial NOR devices */ -#define kSerialNorCmd_BasicRead_3B (0x03U) -#define kSerialNorCmd_BasicRead_4B (0x13U) -#define kSerialNorCmd_PageProgram_1_1_1_3B (0x02U) -#define kSerialNorCmd_PageProgram_1_1_1_4B (0x12U) -#define kSerialNorCmd_PageProgram_1_4_4_4B (0x3EU) -#define kSerialNorCmd_PageProgram_1_1_4_4B (0x34U) -#define kSerialNorCmd_Read_SDR_1_4_4_3B (0xEBU) -#define kSerialNorCmd_Read_DDR_1_4_4_3B (0xEDU) -#define kSerialNorCmd_Read_SDR_1_4_4_4B (0xECU) -#define kSerialNorCmd_Read_SDR_1_1_4_4B (0x6CU) -#define kSerialNorCmd_Read_DDR_1_4_4_4B (0xEEU) -#define kSerialNorCmd_ChipErase (0x60U) -#define kSerialNorCmd_WriteEnable (0x06U) -#define kSerialNorCmd_WriteStatusReg1 (0x01U) -#define kSerialNorCmd_ReadStatusReg1 (0x05U) -#define kSerialNorCmd_WriteStatusReg2 (0x3EU) -#define kSerialNorCmd_ReadStatusReg2 (0x3FU) -#define kSerialNorCmd_ReadFlagReg (0x70U) -#define kSerialNorCmd_ReadId (0x9FU) -#define kSerialNorCmd_Read_DDR_4B (0x0CU) -#define kSerialNorCmd_Read_DDR_3B (0x0BU) -#define kSerialNorCmd_SE4K_3B (0x20U) -#define kSerialNorCmd_SE4K_4B (0x21U) -#define kSerialNorCmd_SE64K_3B (0xD8U) -#define kSerialNorCmd_SE64K_4B (0xDCU) +#define SERIALNOR_CMD_BASICREAD_3B (0x03U) +#define SERIALNOR_CMD_BASICREAD_4B (0x13U) +#define SERIALNOR_CMD_PAGEPROGRAM_1_1_1_3B (0x02U) +#define SERIALNOR_CMD_PAGEPROGRAM_1_1_1_4B (0x12U) +#define SERIALNOR_CMD_PAGEPROGRAM_1_4_4_4B (0x3EU) +#define SERIALNOR_CMD_PAGEPROGRAM_1_1_4_4B (0x34U) +#define SERIALNOR_CMD_READ_SDR_1_4_4_3B (0xEBU) +#define SERIALNOR_CMD_READ_DDR_1_4_4_3B (0xEDU) +#define SERIALNOR_CMD_READ_SDR_1_4_4_4B (0xECU) +#define SERIALNOR_CMD_READ_SDR_1_1_4_4B (0x6CU) +#define SERIALNOR_CMD_READ_DDR_1_4_4_4B (0xEEU) +#define SERIALNOR_CMD_CHIPERASE (0x60U) +#define SERIALNOR_CMD_WRITEENABLE (0x06U) +#define SERIALNOR_CMD_WRITE_STATUS_REG1 (0x01U) +#define SERIALNOR_CMD_READ_STATUS_REG1 (0x05U) +#define SERIALNOR_CMD_WRITE_STATUS_REG2 (0x3EU) +#define SERIALNOR_CMD_READ_STATUS_REG2 (0x3FU) +#define SERIALNOR_CMD_READ_FLAGREG (0x70U) +#define SERIALNOR_CMD_READID (0x9FU) +#define SERIALNOR_CMD_READ_DDR_4B (0x0CU) +#define SERIALNOR_CMD_READ_DDR_3B (0x0BU) +#define SERIALNOR_CMD_SE4K_3B (0x20U) +#define SERIALNOR_CMD_SE4K_4B (0x21U) +#define SERIALNOR_CMD_SE64K_3B (0xD8U) +#define SERIALNOR_CMD_SE64K_4B (0xDCU) #endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/smbus/hpm_smbus.c b/bsp/hpmicro/libraries/hpm_sdk/components/smbus/hpm_smbus.c index aef45cfddd8..8b7633c1567 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/smbus/hpm_smbus.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/smbus/hpm_smbus.c @@ -57,7 +57,6 @@ hpm_stat_t hpm_smbus_master_write_byte_in_command(I2C_Type *ptr, uint8_t slave_a hpm_stat_t hpm_smbus_master_write_word_in_command(I2C_Type *ptr, uint8_t slave_address, uint8_t command, uint16_t data) { hpm_stat_t stat; - uint8_t pec; uint8_t buf[5]; /* addr + rw bit*/ buf[0] = slave_address << 1; @@ -129,7 +128,6 @@ hpm_stat_t hpm_smbus_master_read_word_in_command(I2C_Type *ptr, uint8_t slave_ad hpm_stat_t hpm_smbus_master_write_block_in_command(I2C_Type *ptr, uint8_t slave_address, uint8_t command, uint8_t *data, uint32_t size) { hpm_stat_t stat; - uint8_t pec; uint8_t buf[I2C_SOC_TRANSFER_COUNT_MAX]; uint16_t buf_size; /* frame included addr, command, data, and pec */ @@ -150,7 +148,6 @@ hpm_stat_t hpm_smbus_master_read_block_in_command(I2C_Type *ptr, uint8_t slave_a hpm_stat_t stat; uint8_t pec; uint8_t buf[I2C_SOC_TRANSFER_COUNT_MAX]; - uint16_t buf_size; /* frame included addr, command, data, and pec */ assert(size > 0 && size <= (I2C_SOC_TRANSFER_COUNT_MAX - 3)); /* addr + rw bit*/ @@ -182,7 +179,6 @@ hpm_stat_t hpm_smbus_master_read_block_in_command(I2C_Type *ptr, uint8_t slave_a hpm_stat_t hpm_smbus_master_write(I2C_Type *ptr, uint8_t slave_address, uint8_t *data, uint32_t size) { hpm_stat_t stat; - uint8_t pec; uint8_t buf[I2C_SOC_TRANSFER_COUNT_MAX]; uint16_t buf_size; /* frame included addr, data, and pec */ @@ -201,7 +197,6 @@ hpm_stat_t hpm_smbus_master_read(I2C_Type *ptr, uint8_t slave_address, uint8_t * hpm_stat_t stat; uint8_t pec; uint8_t buf[I2C_SOC_TRANSFER_COUNT_MAX]; - uint16_t buf_size; /* frame included addr, data, and pec */ assert(size > 0 && size <= (I2C_SOC_TRANSFER_COUNT_MAX - 2)); buf[0] = (slave_address << 1); @@ -220,7 +215,6 @@ hpm_stat_t hpm_smbus_master_read(I2C_Type *ptr, uint8_t slave_address, uint8_t * hpm_stat_t hpm_smbus_slave_write(I2C_Type *ptr, uint8_t *data, uint32_t size) { hpm_stat_t stat; - uint8_t pec; uint8_t buf[I2C_SOC_TRANSFER_COUNT_MAX]; uint16_t buf_size; uint8_t slave_address; @@ -241,7 +235,6 @@ hpm_stat_t hpm_smbus_slave_read(I2C_Type *ptr, uint8_t *data, uint32_t size) hpm_stat_t stat; uint8_t pec; uint8_t buf[I2C_SOC_TRANSFER_COUNT_MAX]; - uint16_t buf_size; uint8_t slave_address; /* frame included addr, data, and pec */ assert(size > 0 && size <= (I2C_SOC_TRANSFER_COUNT_MAX - 2)); diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/spi/hpm_spi.c b/bsp/hpmicro/libraries/hpm_sdk/components/spi/hpm_spi.c index 3343bcddc46..253c9a75fb8 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/spi/hpm_spi.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/spi/hpm_spi.c @@ -248,10 +248,13 @@ static hpm_stat_t spi_setup_trans_with_dma_chain(spi_context_t *context, spi_con DMAMUX_Type *dmamux_ptr = context->dma_context.dmamux_ptr; dma_linked_descriptor_t *dma_linked_descriptor = context->dma_linked_descriptor; uint32_t *spi_transctrl = context->spi_transctrl; - uint32_t dma_channel; + uint32_t dma_channel = 0; uint32_t trans_count; dma_channel_config_t dma_ch_config = {0}; + /* use a dummy dma transfer to start SPI trans dma chain */ + static uint32_t dummy_data1 = 0xff, dummy_data2 = 0xff; + trans_count = hpm_spi_get_trans_count(context, config); /* active spi cs pin */ @@ -294,11 +297,10 @@ static hpm_stat_t spi_setup_trans_with_dma_chain(spi_context_t *context, spi_con if (stat != status_success) { return stat; } + } else { + return status_invalid_argument; } - /* use a dummy dma transfer to start SPI trans dma chain */ - static uint32_t dummy_data1 = 0xff, dummy_data2 = 0xff; - dma_default_channel_config(context->dma_context.dma_ptr, &dma_ch_config); dma_ch_config.src_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&dummy_data1); dma_ch_config.dst_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&dummy_data2); @@ -372,7 +374,6 @@ hpm_stat_t hpm_spi_setup_dma_transfer(spi_context_t *context, spi_control_config assert(context->per_trans_max); hpm_stat_t stat = status_success; - uint32_t trans_mode = config->common_config.trans_mode; if (l1c_dc_is_enabled()) { /* cache writeback for tx buff */ @@ -393,9 +394,9 @@ hpm_stat_t hpm_spi_setup_dma_transfer(spi_context_t *context, spi_control_config if ((context->rx_count > context->per_trans_max) || (context->tx_count > context->per_trans_max)) { /* multiple SPI transmissions with chained DMA */ - assert(trans_mode == spi_trans_read_only || trans_mode == spi_trans_dummy_read - || trans_mode == spi_trans_write_only || trans_mode == spi_trans_dummy_write - || trans_mode == spi_trans_write_read_together); + assert(config->common_config.trans_mode == spi_trans_read_only || config->common_config.trans_mode == spi_trans_dummy_read + || config->common_config.trans_mode == spi_trans_write_only || config->common_config.trans_mode == spi_trans_dummy_write + || config->common_config.trans_mode == spi_trans_write_read_together); /* master mode */ assert((context->ptr->TRANSFMT & SPI_TRANSFMT_SLVMODE_MASK) != SPI_TRANSFMT_SLVMODE_MASK); /* GPIO should be used to replace SPI CS pin for SPI chained DMA transmissions */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/spi/hpm_spi.h b/bsp/hpmicro/libraries/hpm_sdk/components/spi/hpm_spi.h index ae022c61fb9..a4441b06648 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/spi/hpm_spi.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/spi/hpm_spi.h @@ -10,7 +10,7 @@ #include "hpm_common.h" #include "hpm_spi_drv.h" -#ifdef CONFIG_HAS_HPMSDK_DMAV2 +#ifdef HPMSOC_HAS_HPMSDK_DMAV2 #include "hpm_dmav2_drv.h" #else #include "hpm_dma_drv.h" diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_gt911.h b/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_gt911.h index 90bbd76134f..4d91f1d52bf 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_gt911.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_gt911.h @@ -54,9 +54,9 @@ #define GT911_TOUCH_YH (0x8149U) #define GT911_VENDOR_ID (0x814AU) #define GT911_STATUS (0x814EU) -#define GT911_GET_STATUS_NUM_OF_POINTS(x) ((x) & 0xFU) -#define GT911_GET_STATUS_LARGE_DETECT(x) (((x) & 0x40U) >> 6) -#define GT911_GET_STATUS_BUFFER_STAT(x) (((x) & 0x80U) >> 7) +#define GT911_GET_STATUS_NUM_OF_POINTS(x) ((x) & 0xFU) +#define GT911_GET_STATUS_LARGE_DETECT(x) (((x) & 0x40U) >> 6) +#define GT911_GET_STATUS_BUFFER_STAT(x) (((x) & 0x80U) >> 7) #define GT911_FIRST_POINT (0x814FU) #define GT911_MAX_TOUCH_POINTS (5U) diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_touch_gt911.c b/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_touch_gt911.c index ee9fb497af5..6543b7e9829 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_touch_gt911.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_touch_gt911.c @@ -9,6 +9,7 @@ #include "hpm_touch.h" #include "hpm_gpio_drv.h" #include "hpm_gt911.h" +#include "hpm_touch.h" gt911_context_t gt911 = {0}; @@ -23,16 +24,21 @@ hpm_stat_t touch_get_data(touch_point_t *points, uint8_t *num_of_points) printf("gt911 read data failed\n"); return stat; } - - num = GT911_GET_STATUS_NUM_OF_POINTS(touch_data.status); - *num_of_points = num; - if (num > 0 && num < GT911_MAX_TOUCH_POINTS) { - for (i = 0; i < num; i++) { - points[i].x = (touch_data.points[i].x_h & 0xF) << 8 | touch_data.points[i].x_l; - points[i].y = (touch_data.points[i].y_h & 0xF) << 8 | touch_data.points[i].y_l; + /* the buffer status is ready*/ + if (GT911_GET_STATUS_BUFFER_STAT(touch_data.status) == 1) { + num = GT911_GET_STATUS_NUM_OF_POINTS(touch_data.status); + *num_of_points = num; + if (num > 0 && num <= GT911_MAX_TOUCH_POINTS) { + for (i = 0; i < num; i++) { + points[i].x = (touch_data.points[i].x_h & 0xF) << 8 | touch_data.points[i].x_l; + points[i].y = (touch_data.points[i].y_h & 0xF) << 8 | touch_data.points[i].y_l; + } + } else { + stat = status_touch_points_over_number; } + } else { + stat = status_touch_buffer_no_ready; } - gt911_write_register(>911, GT911_STATUS, 0); return stat; } @@ -40,7 +46,7 @@ hpm_stat_t touch_get_data(touch_point_t *points, uint8_t *num_of_points) void pull_int_pin(bool high) { gpio_set_pin_output(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN); - gpio_write_pin(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 1); + gpio_write_pin(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, high); } void float_int_pin(void) diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/touch/hpm_touch.h b/bsp/hpmicro/libraries/hpm_sdk/components/touch/hpm_touch.h index 41e68e7a04f..64b012e5d08 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/touch/hpm_touch.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/touch/hpm_touch.h @@ -20,6 +20,11 @@ #error "unknown touch type, either have CONFIG_FT5406 or CONFIG_GT911 defined" #endif +enum { + status_touch_buffer_no_ready = MAKE_STATUS(status_group_touch, 0), + status_touch_points_over_number = MAKE_STATUS(status_group_touch, 1), +}; + typedef struct { uint16_t x; uint16_t y; diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/uart_lin/hpm_uart_lin.c b/bsp/hpmicro/libraries/hpm_sdk/components/uart_lin/hpm_uart_lin.c index 8943eddeea6..8367d282321 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/uart_lin/hpm_uart_lin.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/uart_lin/hpm_uart_lin.c @@ -12,7 +12,11 @@ #endif #ifndef HPM_UART_LIN_BREAK_LENGTH -#define HPM_UART_LIN_BREAK_LENGTH (13U) +#define HPM_UART_LIN_BREAK_LENGTH (13U) /* bits */ +#endif + +#ifndef HPM_UART_LIN_WAKEUP_LENGTH +#define HPM_UART_LIN_WAKEUP_LENGTH (400U) /* us */ #endif @@ -86,6 +90,16 @@ static void hpm_uart_lin_send_sync(UART_Type *ptr) uart_write_byte(ptr, 0x55); /* sync phase */ } +void hpm_uart_lin_send_wakeup(UART_Type *ptr, uart_lin_master_pin_ctrl_t *pin_ctrl) +{ + pin_ctrl->config_uart_pin_as_gpio(ptr); + gpio_set_pin_output(pin_ctrl->ptr, pin_ctrl->tx_port, pin_ctrl->tx_pin); + gpio_write_pin(pin_ctrl->ptr, pin_ctrl->tx_port, pin_ctrl->tx_pin, 0); + pin_ctrl->delay_us(HPM_UART_LIN_WAKEUP_LENGTH); + gpio_write_pin(pin_ctrl->ptr, pin_ctrl->tx_port, pin_ctrl->tx_pin, 1); + pin_ctrl->config_uart_pin(ptr); +} + uart_lin_stat_t hpm_uart_lin_master_send_frame(uart_lin_master_config_t *config) { uint32_t retry; @@ -229,7 +243,7 @@ uart_lin_stat_t hpm_uart_lin_master_receive_data(uart_lin_master_config_t *confi UART_Type *ptr = config->ptr; uart_lin_data_t data = config->data; uint8_t pid = hpm_uart_lin_calculate_protected_id(config->id); - uint8_t checksum; + uint8_t checksum = 0; uint8_t index = 0; uint8_t *buff = data.buff; diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/uart_lin/hpm_uart_lin.h b/bsp/hpmicro/libraries/hpm_sdk/components/uart_lin/hpm_uart_lin.h index 812aabef8d6..f79790b5d0a 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/uart_lin/hpm_uart_lin.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/uart_lin/hpm_uart_lin.h @@ -143,6 +143,16 @@ void hpm_uart_lin_slave_send_data(uart_lin_slave_config_t *config); */ uart_lin_stat_t hpm_uart_lin_slave_receive_data(uart_lin_slave_config_t *config); +/** + * @brief uart_lin send break signal + * + * @note The low-level length of the wakeup signal is defined as HPM_UART_LIN_WAKEUP_LENGTH + * + * @param [in] ptr UART base address + * @param [in] pin_ctrl uart_lin_master_pin_ctrl_t + */ +void hpm_uart_lin_send_wakeup(UART_Type *ptr, uart_lin_master_pin_ctrl_t *pin_ctrl); + #ifdef __cplusplus } #endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/usb/device/hpm_usb_device.c b/bsp/hpmicro/libraries/hpm_sdk/components/usb/device/hpm_usb_device.c index 5066d5cbbbf..8c191fd50a4 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/usb/device/hpm_usb_device.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/usb/device/hpm_usb_device.c @@ -41,7 +41,7 @@ dcd_qhd_t *usb_device_qhd_get(usb_device_handle_t *handle, uint8_t ep_idx) dcd_qtd_t *usb_device_qtd_get(usb_device_handle_t *handle, uint8_t ep_idx) { - return &handle->dcd_data->qtd[ep_idx]; + return &handle->dcd_data->qtd[ep_idx * USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT]; } void usb_device_bus_reset(usb_device_handle_t *handle, uint16_t ep0_max_packet_size) @@ -96,7 +96,7 @@ void usb_device_deinit(usb_device_handle_t *handle) usb_dcd_deinit(handle->regs); - for (int i = 0; i < USB_SOC_DCD_MAX_ENDPOINT_COUNT; i++) { + for (uint32_t i = 0; i < USB_SOC_DCD_MAX_ENDPOINT_COUNT; i++) { usb_dcd_edpt_close(handle->regs, (i | (usb_dir_in << 0x07))); usb_dcd_edpt_close(handle->regs, (i | (usb_dir_out << 0x07))); } @@ -215,13 +215,18 @@ bool usb_device_edpt_open(usb_device_handle_t *handle, usb_endpoint_config_t *co return true; } -bool usb_device_edpt_xfer(usb_device_handle_t *handle, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) +bool usb_device_edpt_xfer(usb_device_handle_t *handle, uint8_t ep_addr, uint8_t *buffer, uint32_t total_bytes) { uint8_t const epnum = ep_addr & 0x0f; uint8_t const dir = (ep_addr & 0x80) >> 7; uint8_t const ep_idx = 2 * epnum + dir; + uint8_t qtd_num; + uint8_t i; + uint32_t xfer_len; dcd_qhd_t *p_qhd; dcd_qtd_t *p_qtd; + dcd_qtd_t *first_p_qtd = NULL; + dcd_qtd_t *prev_p_qtd = NULL; if (epnum == 0) { /* follows UM Setup packet handling using setup lockout mechanism @@ -231,17 +236,43 @@ bool usb_device_edpt_xfer(usb_device_handle_t *handle, uint8_t ep_addr, uint8_t } } - p_qhd = &handle->dcd_data->qhd[ep_idx]; - p_qtd = &handle->dcd_data->qtd[ep_idx]; + qtd_num = (total_bytes + 0x3fff) / 0x4000; + if (qtd_num > USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT) { + return false; + } - /* Prepare qtd */ if (buffer != NULL) { buffer = (uint8_t *)core_local_mem_to_sys_address(0, (uint32_t)buffer); } + p_qhd = &handle->dcd_data->qhd[ep_idx]; + i = 0; + do { + p_qtd = &handle->dcd_data->qtd[ep_idx * USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT + i]; + i++; + + if (total_bytes > 0x4000) { + xfer_len = 0x4000; + total_bytes -= 0x4000; + } else { + xfer_len = total_bytes; + total_bytes = 0; + } - usb_qtd_init(p_qtd, (void *)buffer, total_bytes); - p_qtd->int_on_complete = true; - p_qhd->qtd_overlay.next = core_local_mem_to_sys_address(0, (uint32_t) p_qtd); /* link qtd to qhd */ + usb_qtd_init(p_qtd, (void *)buffer, xfer_len); + if (total_bytes == 0) { + p_qtd->int_on_complete = true; + } + buffer += xfer_len; + + if (prev_p_qtd) { + prev_p_qtd->next = (uint32_t)p_qtd; + } else { + first_p_qtd = p_qtd; + } + prev_p_qtd = p_qtd; + } while (total_bytes > 0); + + p_qhd->qtd_overlay.next = core_local_mem_to_sys_address(0, (uint32_t) first_p_qtd); /* link qtd to qhd */ if (usb_dcd_edpt_get_type(handle->regs, ep_addr) == usb_xfer_isochronous) { p_qhd->iso_mult = 1; @@ -261,6 +292,11 @@ void usb_device_edpt_clear_stall(usb_device_handle_t *handle, uint8_t ep_addr) usb_dcd_edpt_clear_stall(handle->regs, ep_addr); } +bool usb_device_edpt_check_stall(usb_device_handle_t *handle, uint8_t ep_addr) +{ + return usb_dcd_edpt_check_stall(handle->regs, ep_addr); +} + void usb_device_edpt_close(usb_device_handle_t *handle, uint8_t ep_addr) { usb_dcd_edpt_close(handle->regs, ep_addr); @@ -268,9 +304,7 @@ void usb_device_edpt_close(usb_device_handle_t *handle, uint8_t ep_addr) void usb_device_edpt_close_all(usb_device_handle_t *handle) { - int i; - - for (i = 1; i < USB_SOC_DCD_MAX_ENDPOINT_COUNT; i++) { + for (uint32_t i = 1; i < USB_SOC_DCD_MAX_ENDPOINT_COUNT; i++) { usb_device_edpt_close(handle, i); } } diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/usb/device/hpm_usb_device.h b/bsp/hpmicro/libraries/hpm_sdk/components/usb/device/hpm_usb_device.h index a78e7d51d7f..71142f6af14 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/usb/device/hpm_usb_device.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/usb/device/hpm_usb_device.h @@ -132,7 +132,7 @@ void usb_device_disconnect(usb_device_handle_t *handle); bool usb_device_edpt_open(usb_device_handle_t *handle, usb_endpoint_config_t *config); /* Submit a transfe */ -bool usb_device_edpt_xfer(usb_device_handle_t *handle, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes); +bool usb_device_edpt_xfer(usb_device_handle_t *handle, uint8_t ep_addr, uint8_t *buffer, uint32_t total_bytes); /* Stall endpoint */ void usb_device_edpt_stall(usb_device_handle_t *handle, uint8_t ep_addr); @@ -140,6 +140,9 @@ void usb_device_edpt_stall(usb_device_handle_t *handle, uint8_t ep_addr); /* clear stall */ void usb_device_edpt_clear_stall(usb_device_handle_t *handle, uint8_t ep_addr); +/* check stall */ +bool usb_device_edpt_check_stall(usb_device_handle_t *handle, uint8_t ep_addr); + /* close a specified endpoint */ void usb_device_edpt_close(usb_device_handle_t *handle, uint8_t ep_addr); diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/usb/host/hpm_usb_host.c b/bsp/hpmicro/libraries/hpm_sdk/components/usb/host/hpm_usb_host.c index 2b661df2d7d..d74cb9cc9db 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/usb/host/hpm_usb_host.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/usb/host/hpm_usb_host.c @@ -261,7 +261,7 @@ static void usb_host_qtd_init(hcd_qtd_t *p_qtd, void *buffer, uint16_t total_byt if (buffer != NULL) { p_qtd->buffer[0] = (uint32_t)buffer; - for (uint8_t i = 1; i < USB_SOC_HCD_QTD_BUFFER_COUNT; i++) { + for (uint8_t i = 1; i < USB_SOC_DCD_QHD_BUFFER_COUNT; i++) { p_qtd->buffer[i] |= usb_host_align4k(p_qtd->buffer[i-1]) + 4096UL; } } diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/usb/host/hpm_usb_host.h b/bsp/hpmicro/libraries/hpm_sdk/components/usb/host/hpm_usb_host.h index 91dd5e4fa5c..b948938342e 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/usb/host/hpm_usb_host.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/usb/host/hpm_usb_host.h @@ -131,7 +131,7 @@ typedef struct { volatile uint32_t data_toggle : 1 ; /* Data Toggle bit */ /* Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page */ - volatile uint32_t buffer[USB_SOC_HCD_QTD_BUFFER_COUNT]; + volatile uint32_t buffer[USB_SOC_DCD_QHD_BUFFER_COUNT]; } hcd_qtd_t; /* Queue Head */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_adc12_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_adc12_drv.h index 564cdd47b7f..ad49a8bcc61 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_adc12_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_adc12_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -25,6 +25,9 @@ /** @brief Define ADC12 validity check for the channel number */ #define ADC12_IS_CHANNEL_INVALID(CH) (CH > ADC12_SOC_MAX_CH_NUM) +/** @brief Define ADC12 validity check for the channel sample cycle */ +#define ADC12_IS_CHANNEL_SAMPLE_CYCLE_INVALID(CYC) (CYC == 0) + /** @brief Define ADC12 validity check for the trigger number */ #define ADC12_IS_TRIG_CH_INVLAID(CH) (CH > ADC_SOC_MAX_TRIG_CH_NUM) @@ -63,6 +66,26 @@ typedef enum { adc12_conv_mode_preemption } adc12_conversion_mode_t; +/** @brief Define ADC12 Clock Divider */ +typedef enum { + adc12_clock_divider_1 = 1, + adc12_clock_divider_2, + adc12_clock_divider_3, + adc12_clock_divider_4, + adc12_clock_divider_5, + adc12_clock_divider_6, + adc12_clock_divider_7, + adc12_clock_divider_8, + adc12_clock_divider_9, + adc12_clock_divider_10, + adc12_clock_divider_11, + adc12_clock_divider_12, + adc12_clock_divider_13, + adc12_clock_divider_14, + adc12_clock_divider_15, + adc12_clock_divider_16, +} adc12_clock_divider_t; + /** @brief Define ADC12 irq events. */ typedef enum { /** This mask indicates that a trigger conversion is complete. */ @@ -96,26 +119,6 @@ typedef enum { adc12_event_dma_fifo_full = ADC12_INT_STS_DMA_FIFO_FULL_MASK } adc12_irq_event_t; -/** @brief Define ADC12 Clock Divider */ -typedef enum { - adc12_clock_divider_1 = 1, - adc12_clock_divider_2, - adc12_clock_divider_3, - adc12_clock_divider_4, - adc12_clock_divider_5, - adc12_clock_divider_6, - adc12_clock_divider_7, - adc12_clock_divider_8, - adc12_clock_divider_9, - adc12_clock_divider_10, - adc12_clock_divider_11, - adc12_clock_divider_12, - adc12_clock_divider_13, - adc12_clock_divider_14, - adc12_clock_divider_15, - adc12_clock_divider_16, -} adc12_clock_divider_t; - /** @brief ADC12 common configuration struct. */ typedef struct { uint8_t res; @@ -132,10 +135,18 @@ typedef struct { uint8_t diff_sel; uint16_t thshdh; uint16_t thshdl; + bool wdog_int_en; uint8_t sample_cycle_shift; uint32_t sample_cycle; } adc12_channel_config_t; +/** @brief ADC12 channel configuration struct. */ +typedef struct { + uint8_t ch; + uint16_t thshdh; + uint16_t thshdl; +} adc12_channel_threshold_t; + /** @brief ADC12 DMA configuration struct. */ typedef struct { uint32_t *start_addr; @@ -220,6 +231,16 @@ void adc12_get_default_config(adc12_config_t *config); */ void adc12_get_channel_default_config(adc12_channel_config_t *config); +/** + * @brief De-initialize an ADC12 instance. + * + * @param[in] ptr An ADC12 peripheral base address. + * @return A result of de-initializing an ADC12 instance. + * @retval status_success De-initialize an ADC12 instance successfully. Please refer to @ref hpm_stat_t. + * @retval status_invalid_argument De-initialize an ADC12 instance unsuccessfully due to passing one or more invalid arguments. Please refer to @ref hpm_stat_t. + */ +hpm_stat_t adc12_deinit(ADC12_Type *ptr); + /** * @brief Initialize an ADC12 instance. * @@ -242,6 +263,18 @@ hpm_stat_t adc12_init(ADC12_Type *ptr, adc12_config_t *config); */ hpm_stat_t adc12_init_channel(ADC12_Type *ptr, adc12_channel_config_t *config); +/** + * @brief Get thresholds of an ADC12 channel + * + * @param[in] ptr An ADC12 peripheral base address. + * @param[in] ch An ADC12 channel number + * @param[out] config A pointer to the structure of channel threshold + * @return A result of getting thresholds of an ADC12 channel . + * @retval status_success Initialize an ADC12 channel successfully. Please refer to @ref hpm_stat_t. + * @retval status_invalid_argument Initialize an ADC12 channel unsuccessfully due to passing one or more invalid arguments. Please refer to @ref hpm_stat_t. + */ +hpm_stat_t adc12_get_channel_threshold(ADC12_Type *ptr, uint8_t ch, adc12_channel_threshold_t *config); + /** * @brief Configure the the period mode for an ADC12 instance. * @@ -283,7 +316,7 @@ hpm_stat_t adc12_set_pmt_config(ADC12_Type *ptr, adc12_pmt_config_t *config); */ /** - * @brief Configure the stop position offset in the specified memory of DMA write operation for the the sequence mode. + * @brief Configure the stop position offset in the specified memory of DMA write operation for the sequence mode. * * @param[in] ptr An ADC12 peripheral base address. * @param[in] stop_pos A stop position offset. @@ -337,9 +370,10 @@ static inline uint32_t adc12_get_status_flags(ADC12_Type *ptr) /** * @brief Set value of the WAIT_DIS bit. The ADC does not block access to the associated peripheral bus - * until the ADC has completed its conversion. + * until the ADC has completed its conversion. * * * @param[in] ptr An ADC12 peripheral base address. + * @deprecated This API will be removed from V2.0.x */ static inline void adc12_disable_busywait(ADC12_Type *ptr) { @@ -351,18 +385,55 @@ static inline void adc12_disable_busywait(ADC12_Type *ptr) * until the ADC completes the conversion. * * @param[in] ptr An ADC12 peripheral base address. + * @deprecated This API will be removed from V2.0.x */ static inline void adc12_enable_busywait(ADC12_Type *ptr) { ptr->BUF_CFG0 &= ~ADC12_BUF_CFG0_WAIT_DIS_MASK; } +/** + * @brief Set nonblocking read in oneshot mode. + * @note An ADC does not block access to the associated peripheral whether it completes a conversion or not. + * + * @param[in] ptr An ADC12 peripheral base address. + */ +static inline void adc12_set_nonblocking_read(ADC12_Type *ptr) +{ + ptr->BUF_CFG0 |= ADC12_BUF_CFG0_WAIT_DIS_MASK; +} + +/** + * @brief Set blocking read in oneshot mode. + * @note An ADC blocks access to the associated peripheral bus until it completes a conversion. + * + * @param[in] ptr An ADC12 peripheral base address. + */ +static inline void adc12_set_blocking_read(ADC12_Type *ptr) +{ + ptr->BUF_CFG0 &= ~ADC12_BUF_CFG0_WAIT_DIS_MASK; +} + +/** + * @brief Judge whether the current setting is none-blocking mode or not. + * + * @param[in] ptr An ADC12 peripheral base address. + * @return A result indicating the status of bus waiting. + * @retval True means that nonblocking reading. + * @retval False means that blocking reading. + * + */ +static inline bool adc12_is_nonblocking_mode(ADC12_Type *ptr) +{ + return (ADC12_BUF_CFG0_WAIT_DIS_GET(ptr->BUF_CFG0) ? true : false); +} + /** * @brief Get the status of a conversion validity. * * @param[in] ptr An ADC12 peripheral base address. * @param[in] ch An ADC12 peripheral channel. - * @retval Status indicating the validity of the current conversion result. + * @return Status indicating the validity of the current conversion result. * * @note This function is only used when the WAIT_DIS bit in the BUF_RESULT register is 1. */ @@ -382,7 +453,7 @@ static inline bool adc12_get_conv_valid_status(ADC12_Type *ptr, uint8_t ch) */ static inline void adc12_clear_status_flags(ADC12_Type *ptr, uint32_t mask) { - ptr->INT_STS |= mask; + ptr->INT_STS = mask; } /** @} */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_adc16_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_adc16_drv.h index 0870efbf021..47e5afcbd9a 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_adc16_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_adc16_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -26,6 +26,9 @@ #define ADC16_IS_CHANNEL_INVALID(CH) (CH > ADC16_SOC_MAX_CH_NUM) #endif +/** @brief Define ADC16 validity check for the channel sample cycle */ +#define ADC16_IS_CHANNEL_SAMPLE_CYCLE_INVALID(CYC) (CYC == 0) + /** @brief Define ADC16 validity check for the trigger number */ #define ADC16_IS_TRIG_CH_INVLAID(CH) (CH > ADC_SOC_MAX_TRIG_CH_NUM) @@ -57,7 +60,7 @@ typedef enum { adc16_conv_mode_preemption } adc16_conversion_mode_t; -/** @brief Define adc16 Clock Divider */ +/** @brief Define ADC16 Clock Divider */ typedef enum { adc16_clock_divider_1 = 1, adc16_clock_divider_2, @@ -116,7 +119,7 @@ typedef struct { uint8_t conv_mode; uint32_t adc_clk_div; uint16_t conv_duration; - bool port3_rela_time; + bool port3_realtime; bool wait_dis; bool sel_sync_ahb; bool adc_ahb_en; @@ -127,10 +130,18 @@ typedef struct { uint8_t ch; uint16_t thshdh; uint16_t thshdl; + bool wdog_int_en; uint8_t sample_cycle_shift; uint32_t sample_cycle; } adc16_channel_config_t; +/** @brief ADC16 channel configuration struct. */ +typedef struct { + uint8_t ch; + uint16_t thshdh; + uint16_t thshdl; +} adc16_channel_threshold_t; + /** @brief ADC16 DMA configuration struct. */ typedef struct { uint32_t *start_addr; @@ -140,6 +151,7 @@ typedef struct { } adc16_dma_config_t; /** @brief ADC16 DMA configuration struct for the sequence mode. */ +#if defined(ADC_SOC_IP_VERSION) && (ADC_SOC_IP_VERSION < 2) typedef struct { uint32_t result :16; uint32_t seq_num :4; @@ -148,8 +160,18 @@ typedef struct { uint32_t :2; uint32_t cycle_bit :1; } adc16_seq_dma_data_t; +#else +typedef struct { + uint32_t result :16; + uint32_t seq_num :4; + uint32_t adc_ch :5; + uint32_t :6; + uint32_t cycle_bit :1; +} adc16_seq_dma_data_t; +#endif /** @brief ADC16 DMA configuration struct for the preemption mode. */ +#if defined(ADC_SOC_IP_VERSION) && (ADC_SOC_IP_VERSION < 2) typedef struct { uint32_t result :16; uint32_t seq_num :2; @@ -159,8 +181,18 @@ typedef struct { uint32_t :2; uint32_t cycle_bit :1; } adc16_pmt_dma_data_t; +#else +typedef struct { + uint32_t result :16; + uint32_t :4; + uint32_t adc_ch :5; + uint32_t trig_ch :4; + uint32_t seq_num :2; + uint32_t cycle_bit :1; +} adc16_pmt_dma_data_t; +#endif -/** @brief ADC16 configuration struct for the the period mode. */ +/** @brief ADC16 configuration struct for the period mode. */ typedef struct { uint8_t ch; uint8_t prescale; @@ -214,6 +246,16 @@ void adc16_get_default_config(adc16_config_t *config); */ void adc16_get_channel_default_config(adc16_channel_config_t *config); +/** + * @brief De-initialize an ADC16 instance. + * + * @param[in] ptr An ADC16 peripheral base address. + * @return A result of de-initializing an ADC16 instance. + * @retval status_success De-initialize an ADC16 instance successfully. Please refer to @ref hpm_stat_t. + * @retval status_invalid_argument De-initialize an ADC16 instance unsuccessfully due to passing one or more invalid arguments. Please refer to @ref hpm_stat_t. + */ +hpm_stat_t adc16_deinit(ADC16_Type *ptr); + /** * @brief Initialize an ADC16 instance. * @@ -236,6 +278,34 @@ hpm_stat_t adc16_init(ADC16_Type *ptr, adc16_config_t *config); */ hpm_stat_t adc16_init_channel(ADC16_Type *ptr, adc16_channel_config_t *config); +/** + * @brief Get thresholds of an ADC16 channel + * + * @param[in] ptr An ADC16 peripheral base address. + * @param[in] ch An ADC16 channel number + * @param[out] config A pointer to the structure of channel threshold + * @return A result of getting thresholds of an ADC16 channel . + * @retval status_success Initialize an ADC16 channel successfully. Please refer to @ref hpm_stat_t. + * @retval status_invalid_argument Initialize an ADC16 channel unsuccessfully due to passing one or more invalid arguments. Please refer to @ref hpm_stat_t. + */ +hpm_stat_t adc16_get_channel_threshold(ADC16_Type *ptr, uint8_t ch, adc16_channel_threshold_t *config); + +#if defined (ADC_SOC_BUSMODE_ENABLE_CTRL_SUPPORT) && ADC_SOC_BUSMODE_ENABLE_CTRL_SUPPORT +/** + * @brief Enable oneshot mode (bus mode) + * + * @param[in] ptr An ADC16 peripheral base address. + */ +void adc16_enable_oneshot_mode(ADC16_Type *ptr); + +/** + * @brief Disable oneshot mode (bus mode) + * + * @param[in] ptr An ADC16 peripheral base address. + */ +void adc16_disable_oneshot_mode(ADC16_Type *ptr); +#endif + /** * @brief Configure the the period mode for an ADC16 instance. * @@ -275,6 +345,7 @@ hpm_stat_t adc16_set_pmt_config(ADC16_Type *ptr, adc16_pmt_config_t *config); * @param[in] ptr An ADC16 peripheral base address. * @param[in] trig_ch An ADC16 peripheral trigger channel. * @param[in] enable A enable control + * @return A result of setting queue enable in preemption * @retval status_success Get the result of an ADC16 conversion in oneshot mode successfully. * @retval status_invalid_argument Get the result of an ADC16 conversion in oneshot mode unsuccessfully due to passing invalid arguments. */ @@ -311,7 +382,7 @@ static inline void adc16_init_pmt_dma(ADC16_Type *ptr, uint32_t addr) } /** - * @brief Configure the start address of DMA write operation for the preemption mode. + * @brief Configure the start address of DMA write operation for the sequence mode. * * @param[in] ptr An ADC16 peripheral base address. * @param[in] config A pointer to configuration struct of @ref adc16_dma_config_t. @@ -345,6 +416,7 @@ static inline uint32_t adc16_get_status_flags(ADC16_Type *ptr) * until the ADC has completed its conversion. * * @param[in] ptr An ADC16 peripheral base address. + * @deprecated This API will be removed from V2.0.x */ static inline void adc16_disable_busywait(ADC16_Type *ptr) { @@ -356,18 +428,55 @@ static inline void adc16_disable_busywait(ADC16_Type *ptr) * until the ADC completes the conversion. * * @param[in] ptr An ADC16 peripheral base address. + * @deprecated This API will be removed from V2.0.x */ static inline void adc16_enable_busywait(ADC16_Type *ptr) { ptr->BUF_CFG0 &= ~ADC16_BUF_CFG0_WAIT_DIS_MASK; } +/** + * @brief Set nonblocking read in oneshot mode. + * @note An ADC does not block access to the associated peripheral whether it completes a conversion or not. + * + * @param[in] ptr An ADC16 peripheral base address. + */ +static inline void adc16_set_nonblocking_read(ADC16_Type *ptr) +{ + ptr->BUF_CFG0 |= ADC16_BUF_CFG0_WAIT_DIS_MASK; +} + +/** + * @brief Set blocking read in oneshot mode. + * @note An ADC blocks access to the associated peripheral bus until it completes a conversion. + * + * @param[in] ptr An ADC16 peripheral base address. + */ +static inline void adc16_set_blocking_read(ADC16_Type *ptr) +{ + ptr->BUF_CFG0 &= ~ADC16_BUF_CFG0_WAIT_DIS_MASK; +} + +/** + * @brief Judge whether the current setting is none-blocking mode or not. + * + * @param[in] ptr An ADC16 peripheral base address. + * @return A result indicating the status of bus waiting. + * @retval True means that nonblocking reading. + * @retval False means that blocking reading. + * + */ +static inline bool adc16_is_nonblocking_mode(ADC16_Type *ptr) +{ + return (ADC16_BUF_CFG0_WAIT_DIS_GET(ptr->BUF_CFG0) ? true : false); +} + /** * @brief Get the status of a conversion validity. * * @param[in] ptr An ADC16 peripheral base address. * @param[in] ch An ADC16 peripheral channel. - * @retval Status indicating the validity of the current conversion result. + * @return Status indicating the validity of the current conversion result. * * @note This function is only used when the WAIT_DIS bit in the BUF_RESULT register is 1. */ @@ -387,7 +496,7 @@ static inline bool adc16_get_conv_valid_status(ADC16_Type *ptr, uint8_t ch) */ static inline void adc16_clear_status_flags(ADC16_Type *ptr, uint32_t mask) { - ptr->INT_STS |= mask; + ptr->INT_STS = mask; } /** @} */ @@ -488,6 +597,16 @@ void adc16_enable_temp_sensor(ADC16_Type *ptr); void adc16_disable_temp_sensor(ADC16_Type *ptr); #endif +/** + * @brief enable the transmission of adc data to the motor sensor unit. + * + * @param[in] ptr An ADC16 peripheral base address. + */ +static inline void adc16_enable_motor(ADC16_Type *ptr) +{ + ptr->ANA_CTRL0 |= ADC16_ANA_CTRL0_MOTO_EN_MASK; +} + /** @} */ #ifdef __cplusplus diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_bgpr_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_bgpr_drv.h new file mode 100644 index 00000000000..83d9b67a280 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_bgpr_drv.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_BGPR_DRV_H +#define HPM_BGPR_DRV_H + +#include "hpm_common.h" +#include "hpm_soc_feature.h" +#include "hpm_bgpr_regs.h" + +/** + * + * @brief BGPR driver APIs + * @defgroup bgpr_interfaces BGPR driver APIs + * @ingroup io_interfaces + * @{ + */ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief read BGPR value + * + * @note the bgpr_index range is 0 ~ (GPR count of BGPR - 1) + * + * @param ptr BGPR base address + * @param bgpr_index BGPR GPR index + * @param bgpr_val the BGPR GPR value pointer + * + * @return hpm_stat_t status_success if read bgpr without any error + */ +static inline hpm_stat_t bgpr_read32(BGPR_Type *ptr, uint8_t bgpr_index, uint32_t *bgpr_val) +{ + hpm_stat_t stat = status_invalid_argument; + uint8_t gpr_count = sizeof(ptr->GPR) / sizeof(uint32_t); + if (bgpr_index < gpr_count) { + (*bgpr_val) = ptr->GPR[bgpr_index]; + stat = status_success; + } + return stat; +} + +/** + * @brief write BGPR value + * + * @note the bgpr_index range is 0 ~ (GPR count of BGPR - 1) + * + * @param ptr BGPR base address + * @param bgpr_index BGPR GPR index + * @param bgpr_val the BGPR GPR value + * + * @return hpm_stat_t status_success if write bgpr without any error + */ +static inline hpm_stat_t bgpr_write32(BGPR_Type *ptr, uint8_t bgpr_index, uint32_t bgpr_val) +{ + hpm_stat_t stat = status_invalid_argument; + uint8_t gpr_count = sizeof(ptr->GPR) / sizeof(uint32_t); + if (bgpr_index < gpr_count) { + ptr->GPR[bgpr_index] = bgpr_val; + stat = status_success; + } + return stat; +} + +/** + * @} + */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_cam_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_cam_drv.h index a0a57486459..1e7156630c9 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_cam_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_cam_drv.h @@ -32,6 +32,7 @@ */ #define CAM_SENSOR_BITWIDTH_8BITS (CAM_CR1_SENSOR_BIT_WIDTH_SET(0)) #define CAM_SENSOR_BITWIDTH_10BITS (CAM_CR1_SENSOR_BIT_WIDTH_SET(1)) +#define CAM_SENSOR_BITWIDTH_24BITS (CAM_CR1_SENSOR_BIT_WIDTH_SET(3)) /** * @brief CAM IRQ mask @@ -79,11 +80,11 @@ typedef struct { uint32_t width; uint32_t height; bool pixclk_sampling_falling; + bool de_active_low; /* de_active_low must is same with hsync_active_low when dvp be used */ bool hsync_active_low; bool vsync_active_low; bool color_ext; bool data_pack_msb; - bool enable_buffer2; uint16_t data_store_mode; uint8_t color_format; uint8_t sensor_bitwidth; @@ -182,11 +183,33 @@ void cam_start(CAM_Type *ptr); /** * @brief CAM stop * + * @note this API will stop CAM immediately no matter there's any frame is being processed or not + * * @param [in] ptr CAM base address */ void cam_stop(CAM_Type *ptr); -void cam_update_buffer(CAM_Type *ptr, uint32_t buffer); +/** + * @brief CAM update DMASA_FB1 buffer + * + * @param [in] ptr CAM base address + * @param [in] buffer buffer point address + */ +static inline void cam_update_buffer(CAM_Type *ptr, uint32_t buffer) +{ + ptr->DMASA_FB1 = buffer; +} + +/** + * @brief CAM update DMASA_FB2 buffer + * + * @param [in] ptr CAM base address + * @param [in] buffer buffer point address + */ +static inline void cam_update_buffer2(CAM_Type *ptr, uint32_t buffer) +{ + ptr->DMASA_FB2 = buffer; +} /** * @brief CAM enable binary output @@ -300,9 +323,17 @@ static inline bool cam_check_status(CAM_Type *ptr, cam_status_mask_t sta_mask) */ static inline void cam_clear_status(CAM_Type *ptr, cam_status_mask_t sta_mask) { - ptr->STA |= sta_mask; + ptr->STA = sta_mask; } +/** + * @brief CAM safety stop + * + * @note this API will wait for end-of-frame event before stopping CAM + * + * @param [in] ptr CAM base address + */ +void cam_stop_safely(CAM_Type *ptr); /** * @} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_can_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_can_drv.h index 4c9c505ece9..db9ff715660 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_can_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_can_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -239,12 +239,12 @@ typedef struct { }; }; - can_node_mode_t mode; /**< CAN work mode */ + can_node_mode_t mode; /**< CAN work mode */ bool use_lowlevel_timing_setting; /**< Use low-level timing setting */ bool enable_canfd; /**< Enable CAN FD */ bool enable_self_ack; /**< CAN self-ack flag */ - bool disable_re_transmission_for_ptb; /**< disable re-transmission for primary transmit buffer */ - bool disable_re_transmission_for_stb; /**< disable re-transmission for secondary transmit buffer */ + bool disable_ptb_retransmission; /**< disable re-transmission for primary transmit buffer */ + bool disable_stb_retransmission; /**< disable re-transmission for secondary transmit buffer */ bool enable_tdc; /**< Enable transmittor delay compensation */ uint8_t filter_list_num; /**< element number of CAN filters in filter list */ @@ -336,6 +336,61 @@ static inline void can_enter_standby_mode(CAN_Type *base, bool enable) } } +/** + * @brief Disable the re-transmission for the primary transmission buffer + * + * @param [in] base CAN base address + * @param [in] enable Flag for disabling re-transmission for PTB + */ +static inline void can_disable_ptb_retransmission(CAN_Type *base, bool enable) +{ + if (enable) { + base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TPSS_MASK; + } else { + base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_TPSS_MASK; + } +} + +/** + * @brief Check whether re-transmission is disabled for PTB or not + * + * @param [in] base CAN base address + * @return true Re-transmission is disabled for PTB + * @return false Re-transmission is enabled for PTB + */ +static inline bool can_is_ptb_retransmission_disabled(CAN_Type *base) +{ + return ((base->CMD_STA_CMD_CTRL & CAN_CMD_STA_CMD_CTRL_TPSS_MASK) != 0); +} + +/** + * @brief Disable the re-transmission for the secondary transmission buffer + * + * @param [in] base CAN base address + * @param [in] enable Flag for disabling re-transmission for STB + */ +static inline void can_disable_stb_retransmission(CAN_Type *base, bool enable) +{ + if (enable) { + base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TSSS_MASK; + } else { + base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_TSSS_MASK; + } +} + +/** + * @brief Check whether re-transmission is disabled for STB or not + * + * @param [in] base CAN base address + * @return true Re-transmission is disabled for STB + * @return false Re-transmission is enabled for STB + */ +static inline bool can_is_stb_retransmission_disabled(CAN_Type *base) +{ + return ((base->CMD_STA_CMD_CTRL & CAN_CMD_STA_CMD_CTRL_TSSS_MASK) != 0); +} + + /** * @brief Select CAN TX buffer * @param [in] base CAN base address @@ -679,6 +734,8 @@ static inline uint8_t can_get_last_arbitration_lost_position(CAN_Type *base) static inline void can_set_transmitter_delay_compensation(CAN_Type *base, uint8_t sample_point, bool enable) { #if defined(CAN_SOC_CANFD_TDC_REQUIRE_STUFF_EXCEPTION_WORKAROUND) && (CAN_SOC_CANFD_TDC_REQUIRE_STUFF_EXCEPTION_WORKAROUND == 1) + (void) sample_point; + (void) enable; base->TDC = CAN_TDC_TDCEN_SET((uint8_t) enable); #else base->TDC = CAN_TDC_SSPOFF_SET(sample_point) | CAN_TDC_TDCEN_SET((uint8_t) enable); @@ -717,7 +774,18 @@ static inline uint8_t can_get_transmit_error_count(CAN_Type *base) } /** - * @brief Disable CAN filter + * @brief Enable a specified CAN filter + * + * @param [in] base CAN base address + * @param index CAN filter index + */ +static inline void can_enable_filter(CAN_Type *base, uint32_t index) +{ + base->ACF_EN |= (uint16_t) (1U << index); +} + +/** + * @brief Disable a specified CAN filter * * @param [in] base CAN base address * @param index CAN filter index @@ -744,6 +812,14 @@ hpm_stat_t can_get_default_config(can_config_t *config); hpm_stat_t can_init(CAN_Type *base, can_config_t *config, uint32_t src_clk_freq); +/** + * @brief De-initialize the CAN controller + * + * @param [in] base CAN base address + */ +void can_deinit(CAN_Type *base); + + /** * @brief Configure the Slow Speed Bit timing using low-level interface * @param [in] base CAN base address @@ -840,27 +916,30 @@ hpm_stat_t can_send_high_priority_message_nonblocking(CAN_Type *base, const can_ /** * @brief Receive CAN message using blocking transfer + * * @param [in] base CAN base address * @param [out] message CAN message buffer - * @retval API execution status - * @arg status_success API exection is successful - * @arg status_invalid_argument Invalid parameters - * @arg status_can_bit_error CAN bit error happened during receiving message - * @arg status_can_form_error CAN form error happened during receiving message - * @arg status_can_stuff_error CAN stuff error happened during receiving message - * @arg status_can_ack_error CAN ack error happened during receiving message - * @arg status_can_crc_error CAN crc error happened during receiving message - * @arg status_can_other_error Other error happened during receiving message + * + * @retval status_success API exection is successful + * @retval status_invalid_argument Invalid parameters + * @retval status_can_bit_error CAN bit error happened during receiving message + * @retval status_can_form_error CAN form error happened during receiving message + * @retval status_can_stuff_error CAN stuff error happened during receiving message + * @retval status_can_ack_error CAN ack error happened during receiving message + * @retval status_can_crc_error CAN crc error happened during receiving message + * @retval status_can_other_error Other error happened during receiving message */ hpm_stat_t can_receive_message_blocking(CAN_Type *base, can_receive_buf_t *message); /** * @brief Read Received CAN message + * * @note This API assumes that the received CAN message is available. * It can be used in the interrupt handler * @param [in] base CAN base address * @param [out] message CAN message buffer + * * @retval status_success API exection is successful * @retval status_invalid_argument Invalid parameters * @retval status_can_bit_error CAN bit error happened during receiving message diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_common.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_common.h index 78eb6615d85..d89bae16051 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_common.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_common.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -49,6 +49,14 @@ #define MIN(a, b) ((a) < (b) ? (a) : (b)) #endif +#ifndef HPM_ALIGN_DOWN +#define HPM_ALIGN_DOWN(a, n) ((uint32_t)(a) & ~(n-1U)) +#endif + +#ifndef HPM_ALIGN_UP +#define HPM_ALIGN_UP(a, n) (((uint32_t)(a) + (n-1U)) & ~(n-1U)) +#endif + #define HPM_BITSMASK(val, offset) ((uint32_t)(val) << (offset)) #define IS_HPM_BITMASK_SET(val, mask) (((uint32_t)(val) & (uint32_t)(mask)) != 0U) #define IS_HPM_BIT_SET(val, offset) (((uint32_t)(val) & (1UL << (offset))) != 0U) @@ -58,6 +66,12 @@ #define HPM_BREAK_IF(cond) if (cond) { break; } #define HPM_CONTINUE_IF(cond) if (cond) { continue; } +#define HPM_DIV_ROUND_CLOSEST(x, div) (((x) + (div) / 2) / (div)) +#define HPM_DIV_ROUND_UP(x, div) (((x) + (div) - 1) / (div)) + +#define HPM_NUM_TO_EVEN_CEILING(x) ((x + 1) & 0xFFFFFFFEUL) +#define HPM_NUM_TO_EVEN_FLOOR(x) ((x) & 0xFFFFFFFEUL) + #define HPM_CHECK_RET(x) \ do { \ stat = (x); \ @@ -69,6 +83,39 @@ #define SIZE_1KB (1024UL) #define SIZE_1MB (1048576UL) +#define BIT0_MASK (0x00000001UL) +#define BIT1_MASK (0x00000002UL) +#define BIT2_MASK (0x00000004UL) +#define BIT3_MASK (0x00000008UL) +#define BIT4_MASK (0x00000010UL) +#define BIT5_MASK (0x00000020UL) +#define BIT6_MASK (0x00000040UL) +#define BIT7_MASK (0x00000080UL) +#define BIT8_MASK (0x00000100UL) +#define BIT9_MASK (0x00000200UL) +#define BIT10_MASK (0x00000400UL) +#define BIT11_MASK (0x00000800UL) +#define BIT12_MASK (0x00001000UL) +#define BIT13_MASK (0x00002000UL) +#define BIT14_MASK (0x00004000UL) +#define BIT15_MASK (0x00008000UL) +#define BIT16_MASK (0x00010000UL) +#define BIT17_MASK (0x00020000UL) +#define BIT18_MASK (0x00040000UL) +#define BIT19_MASK (0x00080000UL) +#define BIT20_MASK (0x00100000UL) +#define BIT21_MASK (0x00200000UL) +#define BIT22_MASK (0x00400000UL) +#define BIT23_MASK (0x00800000UL) +#define BIT24_MASK (0x01000000UL) +#define BIT25_MASK (0x02000000UL) +#define BIT26_MASK (0x04000000UL) +#define BIT27_MASK (0x08000000UL) +#define BIT28_MASK (0x10000000UL) +#define BIT29_MASK (0x20000000UL) +#define BIT30_MASK (0x40000000UL) +#define BIT31_MASK (0x80000000UL) + typedef uint32_t hpm_stat_t; /* @brief Enum definition for the Status group @@ -108,11 +155,14 @@ enum { status_group_pllctlv2, status_group_ffa, status_group_mcan, + status_group_ewdg, status_group_middleware_start = 500, status_group_sdmmc = status_group_middleware_start, status_group_audio_codec, status_group_dma_manager, + status_group_spi_nor_flash, + status_group_touch, }; /* @brief Common status code definitions */ @@ -162,6 +212,60 @@ ATTR_PLACE_AT(section_name) ATTR_ALIGN(alignment) #define NOP() __asm volatile("nop") #define WFI() __asm volatile("wfi") +#define HPM_ATTR_MACHINE_INTERRUPT __attribute__ ((section(".isr_vector"), interrupt("machine"), aligned(4))) +#define HPM_ATTR_SUPERVISOR_INTERRUPT __attribute__ ((section(".isr_s_vector"), interrupt("supervisor"), aligned(4))) + +#elif defined(__ICCRISCV__) + + +/* alway_inline */ +#define ATTR_ALWAYS_INLINE __attribute__((always_inline)) + +/* weak */ +#define ATTR_WEAK __weak + +/* alignment */ +#define ATTR_ALIGN(alignment) __attribute__((aligned(alignment))) + +/* place var_declare at section_name, e.x. PLACE_AT(".target_section", var); */ +#define ATTR_PLACE_AT(section_name) __attribute__((section(section_name))) + +#define ATTR_PLACE_AT_WITH_ALIGNMENT(section_name, alignment) \ +ATTR_PLACE_AT(section_name) ATTR_ALIGN(alignment) + +#define ATTR_PLACE_AT_NONCACHEABLE ATTR_PLACE_AT(".noncacheable.bss") +#define ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(alignment) \ + ATTR_PLACE_AT_NONCACHEABLE ATTR_ALIGN(alignment) + +#define ATTR_PLACE_AT_NONCACHEABLE_BSS ATTR_PLACE_AT(".noncacheable.bss") +#define ATTR_PLACE_AT_NONCACHEABLE_BSS_WITH_ALIGNMENT(alignment) \ + ATTR_PLACE_AT_NONCACHEABLE_BSS ATTR_ALIGN(alignment) + +/* initialize variable x with y using PLACE_AT_NONCACHEABLE_INIT(x) = {y}; */ +#define ATTR_PLACE_AT_NONCACHEABLE_INIT ATTR_PLACE_AT(".noncacheable.init") +#define ATTR_PLACE_AT_NONCACHEABLE_INIT_WITH_ALIGNMENT(alignment) \ + ATTR_PLACE_AT_NONCACHEABLE_INIT ATTR_ALIGN(alignment) + +#define ATTR_RAMFUNC ATTR_PLACE_AT(".fast") +#define ATTR_RAMFUNC_WITH_ALIGNMENT(alignment) \ + ATTR_RAMFUNC ATTR_ALIGN(alignment) + +#define ATTR_SHARE_MEM ATTR_PLACE_AT(".sh_mem") + +#define NOP() __asm volatile("nop") +#define WFI() __asm volatile("wfi") + +#define HPM_ATTR_MACHINE_INTERRUPT __machine __interrupt +#define HPM_ATTR_SUPERVISOR_INTERRUPT __supervisor __interrupt + +#ifndef __TIMEVAL_DEFINED +#define __TIMEVAL_DEFINED 1 +struct timeval { + long tv_sec; /* Seconds since the Epoch */ + long tv_usec; /* Microseconds */ +}; +#endif + #else #error Unknown toolchain #endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_crc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_crc_drv.h index 90a0f193163..a4d91124f07 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_crc_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_crc_drv.h @@ -110,22 +110,9 @@ typedef struct crc_channel_config { extern "C" { #endif -/** - * @brief Reset CRC channel - * - * @param[in] ptr CRC base address - * @param[in] ch_index Index of the channel to be reset - * - */ -static inline void crc_reset(CRC_Type *ptr, uint32_t ch_index) -{ - ptr->CHN[ch_index].CLR |= CRC_CHN_CLR_CLR_MASK; -} - /** * @brief Get default channel config * - * @param[in] ptr CRC base address * @param[in] cfg Channel config */ void crc_get_default_channel_config(crc_channel_config_t *cfg); diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dac_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dac_drv.h index 5c067f1199e..7bd26403c2a 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dac_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dac_drv.h @@ -12,7 +12,7 @@ #include "hpm_soc_feature.h" /* The range of DAC output value setting is from 0.0 to 10000.0, which is mapped to 0 to 100 in percentage. */ -#define DAC_OUTPUT(PERCENT) (PERCENT / 10000.0f * (DAC_SOC_MAX_DATA + 1)) +#define DAC_OUTPUT(PERCENT) (PERCENT / 10000.0f * DAC_SOC_MAX_DATA) #define DAC_AHB_ERROR_EVENT DAC_IRQ_EN_AHB_ERROR_MASK #define DAC_FIFO_EMPTY_EVENT DAC_IRQ_EN_FIFO_EMPTY_MASK @@ -23,7 +23,8 @@ typedef enum { dac_mode_direct = 0, dac_mode_step, - dac_mode_buffer + dac_mode_buffer, + dac_mode_trig } dac_mode_t; typedef enum { diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dao_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dao_drv.h index c29f3507ee6..475bbd41ace 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dao_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dao_drv.h @@ -12,6 +12,7 @@ #include "hpm_common.h" #include "hpm_dao_regs.h" #include "hpm_i2s_common.h" +#include "hpm_soc_feature.h" /** * @brief DAO driver APIs @@ -43,8 +44,21 @@ typedef struct dao_config { bool enable_mono_output; uint8_t default_output_level; uint8_t channel_count; +#if defined(DAO_SOC_SUPPORT_DATA_FORMAT_CONFIG) && (DAO_SOC_SUPPORT_DATA_FORMAT_CONFIG == 1) + bool enable_tdm_mode; + bool frame_start_at_rising_edge; + uint8_t protocol; + uint8_t channel_length; + uint8_t audio_depth; +#endif + uint8_t channel_slot_mask; } dao_config_t; +typedef enum { + dao_right_channel = DAO_CTRL_RIGHT_EN_MASK, + dao_left_channel = DAO_CTRL_LEFT_EN_MASK, +} dao_channel_t; + #ifdef __cplusplus extern "C" { #endif @@ -94,7 +108,7 @@ static inline void dao_disable_hpf(DAO_Type *ptr) * @brief enable channel * * @param [in] ptr DAO base address - * @param [in] ch channel number + * @param [in] ch channel defined in dao_channel_t */ static inline void dao_enable_channel(DAO_Type *ptr, uint32_t ch) { @@ -105,7 +119,7 @@ static inline void dao_enable_channel(DAO_Type *ptr, uint32_t ch) * @brief disable channel * * @param [in] ptr DAO base address - * @param [in] ch channel number + * @param [in] ch channel defined in dao_channel_t */ static inline void dao_disable_channel(DAO_Type *ptr, uint32_t ch) { diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_display_common.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_display_common.h index 3031746615f..0e576e25c6b 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_display_common.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_display_common.h @@ -148,6 +148,29 @@ typedef struct display_rgb2yuv_config { uint16_t y_offset; } display_rgb2yuv_config_t; +typedef enum display_buf_format { + display_buf_format_argb8888, /*!< memory layout in byte(low->high): b0[7:0], g0[7:0], r0[7:0], a0[7:0], b1[7:1], g1[7:1], r1[7:0], a1[7:0], ... */ + display_buf_format_bgra8888, /*!< memory layout in byte(low->high): a0[7:0], r0[7:0], g0[7:0], b0[7:0], a1[7:1], r1[7:1], g1[7:0], b1[7:0], ... */ + display_buf_format_rgb565, /*!< memory layout in byte(low->high): g0[2:0]:b0[4:0], r0[4:0]:g0[5:3], g1[2:0]:b1[4:0], r1[4:0]:g1[5:3], ... */ + display_buf_format_rgb565_swap, /*!< memory layout in byte(low->high): r0[4:0]:g0[5:3], g0[2:0]:b0[4:0], r2[4:0]:g2[5:3], g1[2:0]:b1[4:0], ... */ + display_buf_format_yuyv, /*!< memory layout in byte(low->high): y0, u0, y1, v0, y2, u2, y3, v2, ... */ + display_buf_format_uyvy, /*!< memory layout in byte(low->high): u0, y0, v0, y1, u2, y2, v2, y3, ... */ + display_buf_format_y8, /*!< memory layout in byte(low->high): y0, y1, y2, y3, y4, y5, ... */ + display_buf_format_max, +} display_buf_format_t; + +typedef struct display_buf { + void *buf; /*!< point pixel memory */ + uint16_t width; /*!< width in pixel */ + uint16_t height; /*!< height in pixel */ + uint32_t stride; /*!< stride each line, in byte */ + display_buf_format_t format; + struct { + display_alpha_op_t op; + uint8_t val; + } alpha; +} display_buf_t; + #ifdef __cplusplus extern "C" { #endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dma_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dma_drv.h index f732c389ec6..d33f2afe9c2 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dma_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dma_drv.h @@ -20,6 +20,9 @@ * @{ */ +#define DMA_CHANNEL_PRIORITY_LOW (0U) +#define DMA_CHANNEL_PRIORITY_HIGH (1U) + #define DMA_NUM_TRANSFER_PER_BURST_1T (0U) #define DMA_NUM_TRANSFER_PER_BURST_2T (1U) #define DMA_NUM_TRANSFER_PER_BURST_4T (2U) @@ -37,28 +40,32 @@ #define DMA_TRANSFER_WIDTH_WORD (2U) #define DMA_TRANSFER_WIDTH_DOUBLE_WORD (3U) +#define DMA_ALIGN_HALF_WORD(x) (x & ~(1u)) +#define DMA_ALIGN_WORD(x) (x & ~(3u)) +#define DMA_ALIGN_DOUBLE_WORD(x) (x & ~(7u)) + #define DMA_STATUS_ERROR_SHIFT (0U) #define DMA_STATUS_ABORT_SHIFT (8U) #define DMA_STATUS_TC_SHIFT (16U) -#define DMA_CHANNEL_STATUS_ONGOING (1U) -#define DMA_CHANNEL_STATUS_ERROR (2U) -#define DMA_CHANNEL_STATUS_ABORT (4U) -#define DMA_CHANNEL_STATUS_TC (8U) +#define DMA_CHANNEL_STATUS_ONGOING (1U) +#define DMA_CHANNEL_STATUS_ERROR (2U) +#define DMA_CHANNEL_STATUS_ABORT (4U) +#define DMA_CHANNEL_STATUS_TC (8U) -#define DMA_CHANNEL_IRQ_STATUS_ERROR(x) (uint32_t)(1 << (DMA_STATUS_ERROR_SHIFT + x)) -#define DMA_CHANNEL_IRQ_STATUS_ABORT(x) (uint32_t)(1 << (DMA_STATUS_ABORT_SHIFT + x)) -#define DMA_CHANNEL_IRQ_STATUS_TC(x) (uint32_t)(1 << (DMA_STATUS_TC_SHIFT + x)) -#define DMA_CHANNEL_IRQ_STATUS(x) (uint32_t)(DMA_CHANNEL_IRQ_STATUS_TC(x) | \ - DMA_CHANNEL_IRQ_STATUS_ABORT(x) | \ - DMA_CHANNEL_IRQ_STATUS_ERROR(x)) +#define DMA_CHANNEL_IRQ_STATUS_ERROR(x) (uint32_t)(1 << (DMA_STATUS_ERROR_SHIFT + x)) +#define DMA_CHANNEL_IRQ_STATUS_ABORT(x) (uint32_t)(1 << (DMA_STATUS_ABORT_SHIFT + x)) +#define DMA_CHANNEL_IRQ_STATUS_TC(x) (uint32_t)(1 << (DMA_STATUS_TC_SHIFT + x)) +#define DMA_CHANNEL_IRQ_STATUS(x) (uint32_t)(DMA_CHANNEL_IRQ_STATUS_TC(x) | \ + DMA_CHANNEL_IRQ_STATUS_ABORT(x) | \ + DMA_CHANNEL_IRQ_STATUS_ERROR(x)) #define DMA_CHANNEL_IRQ_STATUS_GET_ALL_TC(x) ((x) & (((0x01UL << DMA_SOC_CHANNEL_NUM) - 1) << DMA_STATUS_TC_SHIFT)) #define DMA_CHANNEL_IRQ_STATUS_GET_ALL_ABORT(x) ((x) & (((0x01UL << DMA_SOC_CHANNEL_NUM) - 1) << DMA_STATUS_ABORT_SHIFT)) #define DMA_CHANNEL_IRQ_STATUS_GET_ALL_ERROR(x) ((x) & (((0x01UL << DMA_SOC_CHANNEL_NUM) - 1) << DMA_STATUS_ERROR_SHIFT)) -#define DMA_HANDSHAKE_MODE_HANDSHAKE (1U) #define DMA_HANDSHAKE_MODE_NORMAL (0U) +#define DMA_HANDSHAKE_MODE_HANDSHAKE (1U) #define DMA_ADDRESS_CONTROL_INCREMENT (0U) #define DMA_ADDRESS_CONTROL_DECREMENT (1U) @@ -196,15 +203,84 @@ static inline bool dma_channel_is_enable(DMA_Type *ptr, uint32_t ch_index) } /** - * @brief Get DMA channel residue transfer size + * @brief Set DMA channel priority * * @param[in] ptr DMA base address * @param[in] ch_index Index of the channel + * @param[in] priority dma priority + * @arg @ref DMA_CHANNEL_PRIORITY_LOW + * @arg @ref DMA_CHANNEL_PRIORITY_HIGH * - * @return residue transfer size + */ +static inline void dma_set_priority(DMA_Type *ptr, uint32_t ch_index, uint8_t priority) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_PRIORITY_MASK) | DMA_CHCTRL_CTRL_PRIORITY_SET(priority); +} + +/** + * @brief Set DMA channel source work mode + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] mode source work mode + * @arg @ref DMA_HANDSHAKE_MODE_NORMAL + * @arg @ref DMA_HANDSHAKE_MODE_HANDSHAKE + * + */ +static inline void dma_set_source_work_mode(DMA_Type *ptr, uint32_t ch_index, uint8_t mode) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_SRCMODE_MASK) | DMA_CHCTRL_CTRL_SRCMODE_SET(mode); +} + +/** + * @brief Set DMA channel destination work mode + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] mode destination work mode + * @arg @ref DMA_HANDSHAKE_MODE_NORMAL + * @arg @ref DMA_HANDSHAKE_MODE_HANDSHAKE * */ -static inline uint32_t dma_get_residue_transfer_size(DMA_Type *ptr, uint32_t ch_index) +static inline void dma_set_destination_work_mode(DMA_Type *ptr, uint32_t ch_index, uint8_t mode) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_DSTMODE_MASK) | DMA_CHCTRL_CTRL_DSTMODE_SET(mode); +} + +/** + * @brief Set DMA channel source burst size + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] burstsize source burst size + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_1T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_2T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_4T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_8T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_16T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_32T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_64T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_128T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_256T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_512T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_1024T + * + */ +static inline void dma_set_source_burst_size(DMA_Type *ptr, uint32_t ch_index, uint8_t burstsize) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_SRCBURSTSIZE_MASK) | DMA_CHCTRL_CTRL_SRCBURSTSIZE_SET(burstsize); +} + +/** + * @brief Get DMA channel remaining transfer size + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * + * @return remaining transfer size + * + */ +static inline uint32_t dma_get_remaining_transfer_size(DMA_Type *ptr, uint32_t ch_index) { return ptr->CHCTRL[ch_index].TRANSIZE; } @@ -223,6 +299,38 @@ static inline void dma_set_transfer_size(DMA_Type *ptr, uint32_t ch_index, uint3 ptr->CHCTRL[ch_index].TRANSIZE = DMA_CHCTRL_TRANSIZE_TRANSIZE_SET(size_in_width); } +/** + * @brief Set DMA channel source width + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] width transfer source width of the channel + * @arg @ref DMA_TRANSFER_WIDTH_BYTE + * @arg @ref DMA_TRANSFER_WIDTH_HALF_WORD + * @arg @ref DMA_TRANSFER_WIDTH_WORD + * @arg @ref DMA_TRANSFER_WIDTH_DOUBLE_WORD + */ +static inline void dma_set_source_width(DMA_Type *ptr, uint32_t ch_index, uint8_t width) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_SRCWIDTH_MASK) | DMA_CHCTRL_CTRL_SRCWIDTH_SET(width); +} + +/** + * @brief Set DMA channel destination width + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] width transfer destination width of the channel + * @arg @ref DMA_TRANSFER_WIDTH_BYTE + * @arg @ref DMA_TRANSFER_WIDTH_HALF_WORD + * @arg @ref DMA_TRANSFER_WIDTH_WORD + * @arg @ref DMA_TRANSFER_WIDTH_DOUBLE_WORD + */ +static inline void dma_set_destination_width(DMA_Type *ptr, uint32_t ch_index, uint8_t width) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_DSTWIDTH_MASK) | DMA_CHCTRL_CTRL_DSTWIDTH_SET(width); +} + /** * @brief Set DMA channel transfer width and size in byte * @@ -271,6 +379,38 @@ static inline void dma_set_destination_address(DMA_Type *ptr, uint32_t ch_index, ptr->CHCTRL[ch_index].DSTADDR = addr; } +/** + * @brief Set DMA channel source address control mode + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] addr_ctrl source address control mode + * @arg @ref DMA_ADDRESS_CONTROL_INCREMENT + * @arg @ref DMA_ADDRESS_CONTROL_DECREMENT + * @arg @ref DMA_ADDRESS_CONTROL_FIXED + * + */ +static inline void dma_set_source_address_ctrl(DMA_Type *ptr, uint32_t ch_index, uint8_t addr_ctrl) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_SRCADDRCTRL_MASK) | DMA_CHCTRL_CTRL_SRCADDRCTRL_SET(addr_ctrl); +} + +/** + * @brief Set DMA channel destination address control mode + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] addr_ctrl destination address control mode + * @arg @ref DMA_ADDRESS_CONTROL_INCREMENT + * @arg @ref DMA_ADDRESS_CONTROL_DECREMENT + * @arg @ref DMA_ADDRESS_CONTROL_FIXED + * + */ +static inline void dma_set_destination_address_ctrl(DMA_Type *ptr, uint32_t ch_index, uint8_t addr_ctrl) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_DSTADDRCTRL_MASK) | DMA_CHCTRL_CTRL_DSTADDRCTRL_SET(addr_ctrl); +} + /** * @brief Abort channel transfer with mask * @@ -315,10 +455,10 @@ static inline bool dma_has_linked_pointer_configured(DMA_Type *ptr, uint32_t ch_ * @param[in] ptr DMA base address * @param[in] ch_index Target channel index to be checked * - * @retval 1 if transfer is still ongoing - * @retval 2 if any error occurred during transferring - * @retval 4 if transfer is aborted - * @retval 8 if transfer is finished without error + * @retval DMA_CHANNEL_STATUS_ONGOING if transfer is still ongoing + * @retval DMA_CHANNEL_STATUS_ERROR if any error occurred during transferring + * @retval DMA_CHANNEL_STATUS_ABORT if transfer is aborted + * @retval DMA_CHANNEL_STATUS_TC if transfer is finished without error */ static inline uint32_t dma_check_transfer_status(DMA_Type *ptr, uint8_t ch_index) { @@ -369,7 +509,7 @@ static inline void dma_clear_transfer_status(DMA_Type *ptr, uint8_t ch_index) */ static inline void dma_enable_channel_interrupt(DMA_Type *ptr, uint8_t ch_index, int32_t interrupt_mask) { - ptr->CHCTRL[ch_index].CTRL &= ~(interrupt_mask & (DMA_INTERRUPT_MASK_ERROR | DMA_INTERRUPT_MASK_ABORT | DMA_INTERRUPT_MASK_TERMINAL_COUNT)); + ptr->CHCTRL[ch_index].CTRL &= ~(interrupt_mask & DMA_INTERRUPT_MASK_ALL); } /** @@ -381,7 +521,7 @@ static inline void dma_enable_channel_interrupt(DMA_Type *ptr, uint8_t ch_index, */ static inline void dma_disable_channel_interrupt(DMA_Type *ptr, uint8_t ch_index, int32_t interrupt_mask) { - ptr->CHCTRL[ch_index].CTRL |= (interrupt_mask & (DMA_INTERRUPT_MASK_ERROR | DMA_INTERRUPT_MASK_ABORT | DMA_INTERRUPT_MASK_TERMINAL_COUNT)); + ptr->CHCTRL[ch_index].CTRL |= (interrupt_mask & DMA_INTERRUPT_MASK_ALL); } @@ -394,7 +534,7 @@ static inline void dma_disable_channel_interrupt(DMA_Type *ptr, uint8_t ch_index */ static inline uint32_t dma_check_channel_interrupt_mask(DMA_Type *ptr, uint8_t ch_index) { - return ptr->CHCTRL[ch_index].CTRL & (DMA_INTERRUPT_MASK_ERROR | DMA_INTERRUPT_MASK_ABORT | DMA_INTERRUPT_MASK_TERMINAL_COUNT); + return ptr->CHCTRL[ch_index].CTRL & DMA_INTERRUPT_MASK_ALL; } /** diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dmamux_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dmamux_drv.h index 2e7408a55af..a4e350e2b10 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dmamux_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dmamux_drv.h @@ -23,6 +23,8 @@ extern "C" { #endif +#if !defined(DMAMUX_SOC_WRITEONLY) || !DMAMUX_SOC_WRITEONLY + /** * @brief Enable dmamux channel * @@ -45,6 +47,8 @@ static inline void dmamux_disable_channel(DMAMUX_Type *ptr, uint8_t ch_index) ptr->MUXCFG[ch_index] &= ~DMAMUX_MUXCFG_ENABLE_MASK; } +#endif + /** * @brief Config DMAMUX * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dmav2_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dmav2_drv.h new file mode 100644 index 00000000000..407818608bb --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dmav2_drv.h @@ -0,0 +1,686 @@ +/* + * Copyright (c) 2021-2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_DMAV2_DRV_H +#define HPM_DMAV2_DRV_H +#include "hpm_common.h" +#include "hpm_soc_feature.h" +#include "hpm_dmav2_regs.h" + +/** + * + * @brief DMA driver APIs + * @defgroup dma_interface DMA driver APIs + * @ingroup io_interfaces + * @{ + */ + +#define DMA_Type DMAV2_Type + +#define DMA_CHANNEL_PRIORITY_LOW (0U) +#define DMA_CHANNEL_PRIORITY_HIGH (1U) + +#define DMA_NUM_TRANSFER_PER_BURST_1T (0U) +#define DMA_NUM_TRANSFER_PER_BURST_2T (1U) +#define DMA_NUM_TRANSFER_PER_BURST_4T (2U) +#define DMA_NUM_TRANSFER_PER_BURST_8T (3U) +#define DMA_NUM_TRANSFER_PER_BURST_16T (4U) +#define DMA_NUM_TRANSFER_PER_BURST_32T (5U) +#define DMA_NUM_TRANSFER_PER_BURST_64T (6U) +#define DMA_NUM_TRANSFER_PER_BURST_128T (7U) +#define DMA_NUM_TRANSFER_PER_BURST_256T (8U) +#define DMA_NUM_TRANSFER_PER_BURST_512T (9U) +#define DMA_NUM_TRANSFER_PER_BURST_1024T (10U) + +#define DMA_TRANSFER_WIDTH_BYTE (0U) +#define DMA_TRANSFER_WIDTH_HALF_WORD (1U) +#define DMA_TRANSFER_WIDTH_WORD (2U) +#define DMA_TRANSFER_WIDTH_DOUBLE_WORD (3U) + +#define DMA_ALIGN_HALF_WORD(x) (x & ~(1u)) +#define DMA_ALIGN_WORD(x) (x & ~(3u)) +#define DMA_ALIGN_DOUBLE_WORD(x) (x & ~(7u)) + +#define DMA_CHANNEL_STATUS_ONGOING (1U) +#define DMA_CHANNEL_STATUS_ERROR (2U) +#define DMA_CHANNEL_STATUS_ABORT (4U) +#define DMA_CHANNEL_STATUS_TC (8U) +#define DMA_CHANNEL_STATUS_HALF_TC (16U) + +#define DMA_CHANNEL_IRQ_STATUS_ERROR(x) (uint32_t)(1 << x) +#define DMA_CHANNEL_IRQ_STATUS_ABORT(x) (uint32_t)(1 << x) +#define DMA_CHANNEL_IRQ_STATUS_TC(x) (uint32_t)(1 << x) +#define DMA_CHANNEL_IRQ_STATUS_HALF_TC(x) (uint32_t)(1 << x) + +#define DMA_HANDSHAKE_MODE_NORMAL (0U) +#define DMA_HANDSHAKE_MODE_HANDSHAKE (1U) + +#define DMA_ADDRESS_CONTROL_INCREMENT (0U) +#define DMA_ADDRESS_CONTROL_DECREMENT (1U) +#define DMA_ADDRESS_CONTROL_FIXED (2U) + +#define DMA_SRC_BURST_OPT_STANDAND_SIZE (0U) +#define DMA_SRC_BURST_OPT_CUSTOM_SIZE (1U) + +#define DMA_HANDSHAKE_OPT_ONE_BURST (0U) +#define DMA_HANDSHAKE_OPT_ALL_TRANSIZE (1U) + +#define DMA_INTERRUPT_MASK_NONE (0U) +#define DMA_INTERRUPT_MASK_ERROR DMAV2_CHCTRL_CTRL_INTERRMASK_MASK +#define DMA_INTERRUPT_MASK_ABORT DMAV2_CHCTRL_CTRL_INTABTMASK_MASK +#define DMA_INTERRUPT_MASK_TERMINAL_COUNT DMAV2_CHCTRL_CTRL_INTTCMASK_MASK +#define DMA_INTERRUPT_MASK_HALF_TC DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_MASK +#define DMA_INTERRUPT_MASK_ALL \ + (uint8_t)(DMA_INTERRUPT_MASK_TERMINAL_COUNT \ + | DMA_INTERRUPT_MASK_ABORT \ + | DMA_INTERRUPT_MASK_ERROR \ + | DMA_INTERRUPT_MASK_HALF_TC) + +#define DMA_SUPPORT_64BIT_ADDR (0) + + +enum { + dmav2_state_idle = 0, + dmav2_state_read, + dmav2_state_read_ack, + dmav2_state_write, + dmav2_state_write_ack, + dmav2_state_ll, + dmav2_state_end, + dmav2_state_end_wait, +}; + +/** + * @brief Linked descriptor + * + * It is consumed by DMA controlled directly + */ +typedef struct dma_linked_descriptor { + uint32_t ctrl; /**< Control */ + uint32_t trans_size; /**< Transfer size in source width */ + uint32_t src_addr; /**< Source address */ + uint32_t req_ctrl; /**< Request select */ + uint32_t dst_addr; /**< Destination address */ + uint32_t reserved0; /**< not used on dmav2 */ + uint32_t linked_ptr; /**< Linked descriptor address */ + uint32_t reserved1; /**< not used on dmav2 */ +} dma_linked_descriptor_t; + +/* @brief Channel config */ +typedef struct dma_channel_config { + uint8_t priority; /**< Channel priority */ + uint8_t src_burst_size; /**< Source burst size */ + uint8_t src_mode; /**< Source work mode */ + uint8_t dst_mode; /**< Destination work mode */ + uint8_t src_width; /**< Source width */ + uint8_t dst_width; /**< Destination width */ + uint8_t src_addr_ctrl; /**< Source address control */ + uint8_t dst_addr_ctrl; /**< Destination address control */ + uint16_t interrupt_mask; /**< Interrupt mask */ + uint32_t src_addr; /**< Source address */ + uint32_t dst_addr; /**< Destination address */ + uint32_t linked_ptr; /**< Next linked descriptor */ + uint32_t size_in_byte; /**< Total size to be transferred in byte */ + bool en_infiniteloop; /**< Infinite loop transfer enable. Attention: only DMAV2 support */ + uint8_t handshake_opt; /**< Handshake transfer option. Attention: only DMAV2 support */ + uint8_t burst_opt; /**< Burst size option. Attention: only DMAV2 support */ +} dma_channel_config_t; + +/* @brief Channel config */ +typedef struct dma_handshake_config { + uint32_t dst; + uint32_t src; + uint32_t size_in_byte; + uint8_t data_width; /* data width, value defined by DMA_TRANSFER_WIDTH_xxx */ + uint8_t ch_index; + bool dst_fixed; + bool src_fixed; + bool en_infiniteloop; + uint16_t interrupt_mask; +} dma_handshake_config_t; + + +/* @brief DMA specific status */ +enum { + status_dma_transfer_done = MAKE_STATUS(status_group_dma, 0), + status_dma_transfer_error = MAKE_STATUS(status_group_dma, 1), + status_dma_transfer_abort = MAKE_STATUS(status_group_dma, 2), + status_dma_transfer_ongoing = MAKE_STATUS(status_group_dma, 3), + status_dma_alignment_error = MAKE_STATUS(status_group_dma, 4), + status_dma_transfer_half_done = MAKE_STATUS(status_group_dma, 5), +}; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Reset DMA + * + * @param[in] ptr DMA base address + */ +static inline void dma_reset(DMAV2_Type *ptr) +{ + ptr->DMACTRL |= DMAV2_DMACTRL_RESET_MASK; +} + +/** + * @brief Enable DMA channel + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel to be enabled + * + * @return status_success if everything's okay + */ +static inline hpm_stat_t dma_enable_channel(DMAV2_Type *ptr, uint32_t ch_index) +{ + ptr->CHCTRL[ch_index].CTRL |= DMAV2_CHCTRL_CTRL_ENABLE_MASK; + + if ((ptr->CHEN == 0) || !(ptr->CHEN & 1 << ch_index)) { + return status_fail; + } + return status_success; +} + +/** + * @brief Disable DMA channel + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel to be disabled + * + */ +static inline void dma_disable_channel(DMAV2_Type *ptr, uint32_t ch_index) +{ + ptr->CHCTRL[ch_index].CTRL &= ~DMAV2_CHCTRL_CTRL_ENABLE_MASK; +} + +/** + * @brief Check whether DMA channel is enable + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * + * @return true if DMA channel is enable + * + */ +static inline bool dma_channel_is_enable(DMAV2_Type *ptr, uint32_t ch_index) +{ + return (ptr->CHCTRL[ch_index].CTRL & DMAV2_CHCTRL_CTRL_ENABLE_MASK) ? true : false; +} + +/** + * @brief Set DMA channel priority + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] priority dma priority + * @arg @ref DMA_CHANNEL_PRIORITY_LOW + * @arg @ref DMA_CHANNEL_PRIORITY_HIGH + * + */ +static inline void dma_set_priority(DMAV2_Type *ptr, uint32_t ch_index, uint8_t priority) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_PRIORITY_MASK) | DMAV2_CHCTRL_CTRL_PRIORITY_SET(priority); +} + +/** + * @brief Set DMA channel source work mode + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] mode source work mode + * @arg @ref DMA_HANDSHAKE_MODE_NORMAL + * @arg @ref DMA_HANDSHAKE_MODE_HANDSHAKE + * + */ +static inline void dma_set_source_work_mode(DMAV2_Type *ptr, uint32_t ch_index, uint8_t mode) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_SRCMODE_MASK) | DMAV2_CHCTRL_CTRL_SRCMODE_SET(mode); +} + +/** + * @brief Set DMA channel destination work mode + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] mode destination work mode + * @arg @ref DMA_HANDSHAKE_MODE_NORMAL + * @arg @ref DMA_HANDSHAKE_MODE_HANDSHAKE + * + */ +static inline void dma_set_destination_work_mode(DMAV2_Type *ptr, uint32_t ch_index, uint8_t mode) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_DSTMODE_MASK) | DMAV2_CHCTRL_CTRL_DSTMODE_SET(mode); +} + +/** + * @brief Set DMA channel source burst size + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] burstsize source burst size + * when BURSTOPT is 0, please reference follows: + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_1T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_2T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_4T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_8T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_16T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_32T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_64T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_128T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_256T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_512T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_1024T + * when BURSTOPT is 1, burst size is (burstsize + 1). + * + */ +static inline void dma_set_source_burst_size(DMAV2_Type *ptr, uint32_t ch_index, uint8_t burstsize) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_MASK) | DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SET(burstsize); +} + +/** + * @brief Get DMA channel remaining transfer size + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * + * @return remaining transfer size + * + */ +static inline uint32_t dma_get_remaining_transfer_size(DMAV2_Type *ptr, uint32_t ch_index) +{ + return ptr->CHCTRL[ch_index].TRANSIZE; +} + +/** + * @brief Set DMA channel transfer size + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] size_in_width transfer size of the channel. The width is current dma channel configured source width. + * Transfer total bytes are (size_in_width * source width). + * + */ +static inline void dma_set_transfer_size(DMAV2_Type *ptr, uint32_t ch_index, uint32_t size_in_width) +{ + ptr->CHCTRL[ch_index].TRANSIZE = DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SET(size_in_width); +} + +/** + * @brief Set DMA channel source width + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] width transfer source width of the channel + * @arg @ref DMA_TRANSFER_WIDTH_BYTE + * @arg @ref DMA_TRANSFER_WIDTH_HALF_WORD + * @arg @ref DMA_TRANSFER_WIDTH_WORD + * @arg @ref DMA_TRANSFER_WIDTH_DOUBLE_WORD + */ +static inline void dma_set_source_width(DMAV2_Type *ptr, uint32_t ch_index, uint8_t width) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_SRCWIDTH_MASK) | DMAV2_CHCTRL_CTRL_SRCWIDTH_SET(width); +} + +/** + * @brief Set DMA channel destination width + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] width transfer destination width of the channel + * @arg @ref DMA_TRANSFER_WIDTH_BYTE + * @arg @ref DMA_TRANSFER_WIDTH_HALF_WORD + * @arg @ref DMA_TRANSFER_WIDTH_WORD + * @arg @ref DMA_TRANSFER_WIDTH_DOUBLE_WORD + */ +static inline void dma_set_destination_width(DMAV2_Type *ptr, uint32_t ch_index, uint8_t width) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_DSTWIDTH_MASK) | DMAV2_CHCTRL_CTRL_DSTWIDTH_SET(width); +} + +/** + * @brief Set DMA channel transfer width and size in byte + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] src_width transfer source width of the channel + * @arg @ref DMA_TRANSFER_WIDTH_BYTE + * @arg @ref DMA_TRANSFER_WIDTH_HALF_WORD + * @arg @ref DMA_TRANSFER_WIDTH_WORD + * @arg @ref DMA_TRANSFER_WIDTH_DOUBLE_WORD + * @param[in] size_in_byte transfer size in byte of the channel. The dma transfer size is (size_in_byte >> src_width). + * + */ +static inline void dma_set_transfer_src_width_byte_size(DMAV2_Type *ptr, uint32_t ch_index, uint8_t src_width, uint32_t size_in_byte) +{ + assert((src_width == DMA_TRANSFER_WIDTH_BYTE) || (src_width == DMA_TRANSFER_WIDTH_HALF_WORD) + || (src_width == DMA_TRANSFER_WIDTH_WORD) || (src_width == DMA_TRANSFER_WIDTH_DOUBLE_WORD)); + + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_SRCWIDTH_MASK) | DMAV2_CHCTRL_CTRL_SRCWIDTH_SET(src_width); + ptr->CHCTRL[ch_index].TRANSIZE = DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SET(size_in_byte >> src_width); +} + +/** + * @brief Set DMA channel source address + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] addr source address + * + */ +static inline void dma_set_source_address(DMAV2_Type *ptr, uint32_t ch_index, uint32_t addr) +{ + ptr->CHCTRL[ch_index].SRCADDR = addr; +} + +/** + * @brief Set DMA channel destination address + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] addr destination address + * + */ +static inline void dma_set_destination_address(DMAV2_Type *ptr, uint32_t ch_index, uint32_t addr) +{ + ptr->CHCTRL[ch_index].DSTADDR = addr; +} + +/** + * @brief Set DMA channel source address control mode + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] addr_ctrl source address control mode + * @arg @ref DMA_ADDRESS_CONTROL_INCREMENT + * @arg @ref DMA_ADDRESS_CONTROL_DECREMENT + * @arg @ref DMA_ADDRESS_CONTROL_FIXED + * + */ +static inline void dma_set_source_address_ctrl(DMAV2_Type *ptr, uint32_t ch_index, uint8_t addr_ctrl) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_SRCADDRCTRL_MASK) | DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SET(addr_ctrl); +} + +/** + * @brief Set DMA channel destination address control mode + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] addr_ctrl destination address control mode + * @arg @ref DMA_ADDRESS_CONTROL_INCREMENT + * @arg @ref DMA_ADDRESS_CONTROL_DECREMENT + * @arg @ref DMA_ADDRESS_CONTROL_FIXED + * + */ +static inline void dma_set_destination_address_ctrl(DMAV2_Type *ptr, uint32_t ch_index, uint8_t addr_ctrl) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_DSTADDRCTRL_MASK) | DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SET(addr_ctrl); +} + +/** + * @brief Set DMA channel infinite loop mode + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] infinite_loop false - normal mode(single times mode); true - infinite loop mode(cycle mode) + * + */ +static inline void dma_set_infinite_loop_mode(DMAV2_Type *ptr, uint32_t ch_index, bool infinite_loop) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_INFINITELOOP_MASK) | DMAV2_CHCTRL_CTRL_INFINITELOOP_SET(infinite_loop); +} + +/** + * @brief Set DMA channel source burst option + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] burst_opt burst option + * @arg @ref DMA_SRC_BURST_OPT_STANDAND_SIZE + * @arg @ref DMA_SRC_BURST_OPT_CUSTOM_SIZE + * + */ +static inline void dma_set_src_busrt_option(DMAV2_Type *ptr, uint32_t ch_index, uint8_t burst_opt) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_BURSTOPT_MASK) | DMAV2_CHCTRL_CTRL_BURSTOPT_SET(burst_opt); +} + +/** + * @brief Set DMA channel handshake option + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] handshake_opt handshake option + * @arg @ref DMA_HANDSHAKE_OPT_ONE_BURST + * @arg @ref DMA_HANDSHAKE_OPT_ALL_TRANSIZE + * + */ +static inline void dma_set_handshake_option(DMAV2_Type *ptr, uint32_t ch_index, uint8_t handshake_opt) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_MASK) | DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SET(handshake_opt); +} + +/** + * @brief Abort channel transfer with mask + * + * @param[in] ptr DMA base address + * @param[in] ch_index_mask Mask of channels to be aborted + */ +static inline void dma_abort_channel(DMAV2_Type *ptr, uint32_t ch_index_mask) +{ + ptr->CHABORT |= DMAV2_CHABORT_CHABORT_SET(ch_index_mask); +} + +/** + * @brief Check if channels are enabled with mask + * + * @param[in] ptr DMA base address + * @param[in] ch_index_mask Mask of channels to be checked + * + * @return Enabled channel mask + */ +static inline uint32_t dma_check_enabled_channel(DMAV2_Type *ptr, + uint32_t ch_index_mask) +{ + return (ch_index_mask & ptr->CHEN); +} + +/** + * @brief Check if linked pointer has been configured + * + * @param[in] ptr DMA base address + * @param[in] ch_index Target channel index to be checked + * + * @return true if linked pointer has been configured + */ +static inline bool dma_has_linked_pointer_configured(DMAV2_Type *ptr, uint32_t ch_index) +{ + return ptr->CHCTRL[ch_index].LLPOINTER != 0; +} + +/** + * @brief Check transfer status + * + * @param[in] ptr DMA base address + * @param[in] ch_index Target channel index to be checked + * + * @retval DMA_CHANNEL_STATUS_ONGOING if transfer is still ongoing + * @retval DMA_CHANNEL_STATUS_ERROR if any error occurred during transferring + * @retval DMA_CHANNEL_STATUS_ABORT if transfer is aborted + * @retval DMA_CHANNEL_STATUS_TC if transfer is finished without error + * @retval DMA_CHANNEL_STATUS_HALF_TC if half transfer complete without error + */ +static inline uint32_t dma_check_transfer_status(DMAV2_Type *ptr, uint8_t ch_index) +{ + uint32_t dma_status = 0; + + if (ptr->INTTCSTS & (1 << ch_index)) { + dma_status |= DMA_CHANNEL_STATUS_TC; + ptr->INTTCSTS = (1 << ch_index); /* W1C clear status*/ + } + if (ptr->INTHALFSTS & (1 << ch_index)) { + dma_status |= DMA_CHANNEL_STATUS_HALF_TC; + ptr->INTHALFSTS = (1 << ch_index); /* W1C clear status*/ + } + if (ptr->INTERRSTS & (1 << ch_index)) { + dma_status |= DMA_CHANNEL_STATUS_ERROR; + ptr->INTERRSTS = (1 << ch_index); /* W1C clear status*/ + } + if (ptr->INTABORTSTS & (1 << ch_index)) { + dma_status |= DMA_CHANNEL_STATUS_ABORT; + ptr->INTABORTSTS = (1 << ch_index); /* W1C clear status*/ + } + if (dma_status == 0) { + dma_status = DMA_CHANNEL_STATUS_ONGOING; + } + return dma_status; +} + +/** + * @brief Clear transfer status + * + * @param[in] ptr DMA base address + * @param[in] ch_index Target channel index + * + */ +static inline void dma_clear_transfer_status(DMAV2_Type *ptr, uint8_t ch_index) +{ + /* W1C */ + ptr->INTHALFSTS = (1 << ch_index); + ptr->INTTCSTS = (1 << ch_index); + ptr->INTABORTSTS = (1 << ch_index); + ptr->INTERRSTS = (1 << ch_index); +} + +/** + * @brief Enable DMA Channel interrupt + * + * @param [in] ptr DMA base address + * @param [in] ch_index Target channel index + * @param [in] interrupt_mask Interrupt mask + */ +static inline void dma_enable_channel_interrupt(DMAV2_Type *ptr, uint8_t ch_index, int32_t interrupt_mask) +{ + ptr->CHCTRL[ch_index].CTRL &= ~(interrupt_mask & DMA_INTERRUPT_MASK_ALL); +} + +/** + * @brief Disable DMA Channel interrupt + * + * @param [in] ptr DMA base address + * @param [in] ch_index Target channel index + * @param [in] interrupt_mask Interrupt mask + */ +static inline void dma_disable_channel_interrupt(DMAV2_Type *ptr, uint8_t ch_index, int32_t interrupt_mask) +{ + ptr->CHCTRL[ch_index].CTRL |= (interrupt_mask & DMA_INTERRUPT_MASK_ALL); +} + + +/** + * @brief Check Channel interrupt master + * + * @param[in] ptr DMA base address + * @param[in] ch_index Target channel index to be checked + * @return uint32_t Interrupt mask + */ +static inline uint32_t dma_check_channel_interrupt_mask(DMAV2_Type *ptr, uint8_t ch_index) +{ + return ptr->CHCTRL[ch_index].CTRL & DMA_INTERRUPT_MASK_ALL; +} + +/** + * @brief Get default channel config + * + * @param[in] ptr DMA base address + * @param[in] ch Channel config + */ +void dma_default_channel_config(DMAV2_Type *ptr, dma_channel_config_t *ch); + +/** + * @brief Setup DMA channel + * + * @param[in] ptr DMA base address + * @param[in] ch_num Target channel index to be configured + * @param[in] ch Channel config + * @param[in] start_transfer Set true to start transfer + * + * @return status_success if everything is okay + */ +hpm_stat_t dma_setup_channel(DMAV2_Type *ptr, uint8_t ch_num, + dma_channel_config_t *ch, bool start_transfer); + +/** + * @brief Config linked descriptor function + * + * @param[in] ptr DMA base address + * @param[in] descriptor Linked descriptor pointer + * @param[in] ch_num Target channel index to be configured + * @param[in] config Descriptor config pointer + * + * @return status_success if everything is okay + */ +hpm_stat_t dma_config_linked_descriptor(DMAV2_Type *ptr, dma_linked_descriptor_t *descriptor, uint8_t ch_num, dma_channel_config_t *config); + +/** + * @brief Start DMA copy + * + * @param[in] ptr DMA base address + * @param[in] ch_num Target channel index + * @param[in] dst Destination address + * @param[in] src Source Address + * @param[in] size_in_byte Size in byte + * @param[in] burst_len_in_byte Burst length in byte + * + * @return status_success if everthing is okay + * @note: dst, src, size should be aligned with burst_len_in_byte + */ +hpm_stat_t dma_start_memcpy(DMAV2_Type *ptr, uint8_t ch_num, + uint32_t dst, uint32_t src, + uint32_t size_in_byte, uint32_t burst_len_in_byte); + +/** + * @brief Get default handshake config + * + * @param[in] ptr DMA base address + * @param[in] config default config + */ +void dma_default_handshake_config(DMAV2_Type *ptr, dma_handshake_config_t *config); + +/** + * @brief config dma handshake function + * + * @param[in] ptr DMA base address + * @param[in] pconfig dma handshake config pointer + * @param[in] start_transfer Set true to start transfer + * + * @return status_success if everything is okay + */ +hpm_stat_t dma_setup_handshake(DMAV2_Type *ptr, dma_handshake_config_t *pconfig, bool start_transfer); + +/** + * @brief Check whether DMA is idle + * @param [in] ptr DMA base address + * @return true DMA is idle + * @return false DMA is busy + */ +static inline bool dma_is_idle(DMAV2_Type *ptr) +{ + return (DMAV2_IDMISC_DMASTATE_GET(ptr->IDMISC) == dmav2_state_idle) ? true : false; +} + + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_DMAV2_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_enc_pos_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_enc_pos_drv.h new file mode 100644 index 00000000000..677c3943309 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_enc_pos_drv.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_ENC_POS_COMMON_H +#define HPM_ENC_POS_COMMON_H + +#include "hpm_common.h" + +/** + * + * @brief enc pos driver APIs + * @defgroup enc_pos_interface Encode Position driver APIs + * @ingroup io_interface + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief caculate degree of angle from pos + * + * @param[in] pos position value + * @return degree of angle. + */ +float encoder_position_to_deg(uint32_t pos); + +/** + * @brief caculate posistion from degree of angle + * + * @param[in] deg degree of angle + * @return position value. + */ +uint32_t encoder_deg_to_position(float deg); + +/** + * @brief caculate radian of angle from pos + * + * @param[in] pos position value + * @return radian of angle. + */ +float encoder_position_to_rad(uint32_t pos); + +/** + * @brief caculate posistion from radian of angle + * + * @param[in] rad radian of angle + * @return position value. + */ +uint32_t encoder_rad_to_position(float rad); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* HPM_ENC_POS_COMMON_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_enet_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_enet_drv.h index c0cf51e96f9..395fdc4eb8b 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_enet_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_enet_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -55,14 +55,14 @@ *--------------------------------------------------------------------- */ -/** @brief Programmable burst length selections */ +/** @brief interrupt enable type */ typedef enum { enet_normal_int_sum_en = ENET_DMA_INTR_EN_NIE_MASK, enet_aboarmal_int_sum_en = ENET_DMA_INTR_EN_AIE_MASK, enet_receive_int_en = ENET_DMA_INTR_EN_RIE_MASK } enet_interrupt_enable_t; -/** @brief Programmable burst length selections */ +/** @brief interrupt mask type */ typedef enum { enet_lpi_int_mask = ENET_INTR_MASK_LPIIM_MASK, enet_rgsmii_int_mask = ENET_INTR_MASK_RGSMIIIM_MASK @@ -557,7 +557,7 @@ uint32_t enet_get_interrupt_status(ENET_Type *ptr); * @brief Mask the specified mmc interrupt evenets of received frames * * @param[in] ptr An Ethernet peripheral base address - * @param[in] config A mask of the specified evenets + * @param[in] mask A mask of the specified evenets */ void enet_mask_mmc_rx_interrupt_event(ENET_Type *ptr, uint32_t mask); @@ -565,7 +565,7 @@ void enet_mask_mmc_rx_interrupt_event(ENET_Type *ptr, uint32_t mask); * @brief Mask the specified mmc interrupt evenets of transmitted frames * * @param[in] ptr An Ethernet peripheral base address - * @param[in] config A mask of the specified evenets + * @param[in] mask A mask of the specified evenets */ void enet_mask_mmc_tx_interrupt_event(ENET_Type *ptr, uint32_t mask); @@ -591,15 +591,16 @@ uint32_t enet_get_mmc_tx_interrupt_status(ENET_Type *ptr); * @param[in] inf_type the specified interface * @param[in] desc A pointer to descriptor config * @param[in] cfg A pointer to mac config - * @param[in] int_cfg A pointer to the masks of the specified enabled interrupts and the specified masked interrupts + * @param[in] int_config A pointer to the masks of the specified enabled interrupts and the specified masked interrupts + * @return A result of the specified controller initialization */ -int enet_controller_init(ENET_Type *ptr, enet_inf_type_t inf_type, enet_desc_t *desc, enet_mac_config_t *cfg, enet_int_config_t *int_config); +hpm_stat_t enet_controller_init(ENET_Type *ptr, enet_inf_type_t inf_type, enet_desc_t *desc, enet_mac_config_t *cfg, enet_int_config_t *int_config); /** * @brief Set port line speed * * @param[in] ptr An Ethernet peripheral base address - * @param[in] line_speed An enum variable of @ref enet_line_speed_t + * @param[in] speed An enum variable of @ref enet_line_speed_t */ void enet_set_line_speed(ENET_Type *ptr, enet_line_speed_t speed); @@ -631,6 +632,14 @@ uint16_t enet_read_phy(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr); */ void enet_write_phy(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr, uint32_t data); +/** + * @brief Resume reception process + * + * @param[in] ptr An Ethernet peripheral base address + * + */ +void enet_rx_resume(ENET_Type *ptr); + /** * @brief Check if there is a received frame * @@ -800,7 +809,7 @@ void enet_set_snapshot_ptp_message_type(ENET_Type *ptr, enet_ts_ss_ptp_msg_t ts_ * @brief Set the pps0 control output * * @param[in] ptr An Ethernet peripheral base address - * @param[in] enet_pps_ctrl_t An enum value indicating the specified pps frequency + * @param[in] freq An enum value indicating the specified pps frequency */ void enet_set_pps0_control_output(ENET_Type *ptr, enet_pps_ctrl_t freq); @@ -818,7 +827,7 @@ hpm_stat_t enet_set_ppsx_command(ENET_Type *ptr, enet_pps_cmd_t cmd, enet_pps_id * @brief Set a pps config for ppsx * * @param[in] ptr An Ethernet peripheral base address - * @param[in] cmd An enum value indicating the specified pps config + * @param[in] cmd_cfg An enum value indicating the specified pps config * @param[in] idx An enum value indicating the index of pps instance * @retval hpm_stat_t @ref status_invalid_argument or @ref status_success */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ewdg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ewdg_drv.h new file mode 100644 index 00000000000..6c6398982f3 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ewdg_drv.h @@ -0,0 +1,520 @@ +/* + * Copyright (c) 2023-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_EWDG_DRV_H +#define HPM_EWDG_DRV_H + +#include "hpm_common.h" +#include "hpm_ewdg_regs.h" +#include "hpm_soc_feature.h" + +/** + * @brief EWDG driver APIs + * @defgroup ewdg_interface EWDG driver APIs + * @addtogroup ewdg_interface + * @{ + */ + + +/** + * @brief EWDG error codes + */ +enum { + status_ewdg_tick_out_of_range = MAKE_STATUS(status_group_ewdg, 0), /*!< The tick is out of range */ + status_ewdg_div_out_of_range = MAKE_STATUS(status_group_ewdg, 1), /*!< Clock Divider is out of range */ + status_ewdg_feature_unsupported = MAKE_STATUS(status_group_ewdg, 2), /*!< Feature is not supported */ +}; + +/** + * @brief EWDG Password Definitions + * + * @defgroup ewdg_password_def EWDG Password definitions + * @{ + */ +#define EWDG_REFRESH_UNLOCK_PASSWORD_DEFAULT (0xED09U) /*!< Default EWDG Refresh Password */ +#define EWDG_UPDATE_PASSWORD_DEFAULT (0xECF9U) /*!< Default EWDG Update Password */ +#define EWDG_REFRESH_UNLOCK_FIXED_KEY (0x55AAU) /*!< EWDG Unlock Fixed key */ +#define EWDG_REFRESH_KEY (0x5A45524FUL) /*!< EWDG Refresh key */ +/** + * @} + */ + +/** + * @brief EWDG Events + * + * @defgroup ewdg_event EWDG Event definitions + * @{ + */ +#define EWDG_EVENT_PARITY_ERROR (1UL << 6) /*!< Parity Error Event */ +#define EWDG_EVENT_TIMEOUT_RESET (1UL << 5) /*!< Timeout Reset Event */ +#define EWDG_EVENT_TIMEOUT_INTERRUPT (1UL << 4) /*!< Timeout Interrupt Event */ +#define EWDG_EVENT_CFG_REG_UPDATE_UNLOCK_FAIL (1UL << 3) /*!< Update Unlock Fail Event */ +#define EWDG_EVENT_CFG_REG_UPDATE_VIOLATION (1UL << 2) /*!< Update Violation Event */ +#define EWDG_EVENT_REFRESH_UNLOCK_FAIL (1UL << 1) /*!< Refresh Unlock Fail Event */ +#define EWDG_EVENT_REFRESH_VIOLATION (1UL << 0) /*!< Refresh Violation Event */ +/** + * @} + */ + +/** + * @brief EWDG Interrupts + * @defgroup ewdg_interrupt EWDG interrupt definitions + * @{ + */ +#define EWDG_INT_PARITY_FAIL (1UL << 2) /*!< Parity Error Interrupt */ +#define EWDG_INT_CTRL_REG_UNLOCK_FAIL (1UL << 4) /*!< Unlock Control Register Fail Interrupt */ +#define EWDG_INT_CTRL_REG_UPDATE_FAIL (1UL << 6) /*!< Update Control Register Violation Interrupt */ +#define EWDG_INT_TIMEOUT (1UL << 16) /*!< Watchdog Timeout Interrupt */ +#define EWDG_INT_REFRESH_UNLOCK_FAIL (1UL << 20) /*!< Refresh Register Unlock Fail interrupt */ +#define EWDG_INT_REFRESH_VIOLATION (1UL << 22) /*!< Refresh Register Violation interrupt */ +/*! All Interrupt masks */ +#define EWDG_INT_ALL (EWDG_INT_PARITY_FAIL | EWDG_INT_CTRL_REG_UNLOCK_FAIL | EWDG_INT_CTRL_REG_UPDATE_FAIL | \ + EWDG_INT_TIMEOUT | EWDG_INT_REFRESH_UNLOCK_FAIL | EWDG_INT_REFRESH_VIOLATION) +/** + * @} + */ + +/** + * @brief EWDG Resets + * + * @defgroup ewdg_reset_source EWDG reset source definitions + * @{ + */ +#define EWDG_RST_PARITY_FAIL (1UL << 3) /*!< Parity Error Reset */ +#define EWDG_RST_CTRL_REG_UNLOCK_FAIL (1UL << 5) /*!< Unlock Control Register Fail Reset */ +#define EWDG_RST_CTRL_REG_UPDATE_FAIL (1UL << 7) /*!< Update Control Register Violation Reset */ +#define EWDG_RST_TIMEOUT (1UL << 17) /*!< Watchdog Timeout Reset */ +#define EWDG_RST_REFRESH_UNLOCK_FAIL (1UL << 21) /*!< Refresh Register Unlock Fail Reset */ +#define EWDG_RST_REFRESH_VIOLATION (1UL << 23) /*!< Refresh Register Violation Reset */ +/*! All Reset masks */ +#define EWDG_RST_ALL (EWDG_RST_PARITY_FAIL | EWDG_RST_CTRL_REG_UNLOCK_FAIL | EWDG_RST_CTRL_REG_UPDATE_FAIL | \ + EWDG_RST_TIMEOUT | EWDG_RST_REFRESH_UNLOCK_FAIL | EWDG_RST_REFRESH_VIOLATION) +/** + * @} + */ + + + +/** + * @brief EWDG Refresh Unlock Methods + */ +typedef enum { + /*! Use the Unlock Password directly */ + ewdg_refresh_unlock_method_password = 0, + /*! Use password[14:0] | password[15] */ + ewdg_refresh_unlock_method_ring_left_shift_password_by_1 = 1, + /*! Use fixed key: 0x55AA */ + ewdg_refresh_unlock_method_fixed_key = 2, + /*! Use last_password[14:0] | (last_password[15] ^ password[0]) */ + ewdg_refresh_unlock_method_ring_left_shift_password_by_1_bit0_xor_password_bit0 = 3, + /*! Max allowed range */ + ewdg_refresh_unlock_method_max = ewdg_refresh_unlock_method_ring_left_shift_password_by_1_bit0_xor_password_bit0 +} ewdg_refresh_unlock_method_t; + +/** + * @brief EWDG Clock source for internal counter + */ +typedef enum { + ewdg_cnt_clk_src_bus_clk, /*!< Clock is from BUS clock */ + ewdg_cnt_clk_src_ext_osc_clk, /*!< Clock is from External OSC */ +} ewdg_cnt_clk_sel_t; + +/** + * @brief EWDG Lower Window Limitations + */ +typedef enum { + /*! Refresh should be issued after 8/16 of timeout period */ + ewdg_window_lower_timeout_period_8_div_16 = 0, + /*! Refresh should be issued after 10/16 of timeout period */ + ewdg_window_lower_timeout_period_10_div_16 = 1, + /*! Refresh should be issued after 12/16 of timeout period */ + ewdg_window_lower_timeout_period_12_div_16 = 2, + /*! Refresh should be issued after 14/16 of timeout period */ + ewdg_window_lower_timeout_period_14_div_16 = 3, + /*! Maximum allowed limit value */ + ewdg_window_lower_timeout_period_max = ewdg_window_lower_timeout_period_14_div_16 +} ewdg_window_low_limit_t; + +/** + * @brief EWDG Upper Window Limitations + * + * The Actual Upper Window = Lower Window + Upper Window Limit + */ +typedef enum { + ewdg_window_upper_timeout_period_8_div_16 = 0, /*!< 8/16 of timeout_reset_val */ + ewdg_window_upper_timeout_period_1_div_16 = 1, /*!< 1/16 of timeout_reset_val */ + ewdg_window_upper_timeout_period_2_div_16 = 2, /*!< 2/16 of timeout_reset_val */ + ewdg_window_upper_timeout_period_3_div_16 = 3, /*!< 3/16 of timeout_reset_val */ + ewdg_window_upper_timeout_period_4_div_16 = 4, /*!< 4/16 of timeout_reset_val */ + ewdg_window_upper_timeout_period_5_div_16 = 5, /*!< 5/16 of timeout_reset_val */ + ewdg_window_upper_timeout_period_6_div_16 = 6, /*!< 6/16 of timeout_reset_val */ + ewdg_window_upper_timeout_period_7_div_16 = 8, /*!< 7/16 of timeout_reset_val */ + /*! Maximum allowed upper limit */ + ewdg_window_upper_timeout_period_max = ewdg_window_upper_timeout_period_7_div_16 +} ewdg_window_upper_limit_t; + +typedef enum { + ewdg_low_power_mode_halt = 0, /*!< Watchdog is halted in low power mode */ + ewdg_low_power_mode_work_clock_div_4 = 1, /*!< Watchdog is will work with 1/4 normal clock in low power mode */ + ewdg_low_power_mode_work_clock_div_2 = 2, /*!< Watchdog is will work with 1/2 normal clock in low power mode */ + ewdg_low_power_mode_work_clock_normal = 3, /*!< Watchdog is will work with normal clock in low power mode */ +} ewdg_low_power_mode_t; + +/*** + * @brief EWDG Function Control Configurations + */ +typedef struct { + ewdg_cnt_clk_sel_t cnt_clk_sel; /*!< Clock source for counter */ + bool enable_window_mode; /*!< Enable window mode */ + ewdg_window_low_limit_t window_lower_limit; /*!< Lower limit of the window */ + /*! Upper limit of the window + * The real upper window = (window_lower_limit/8 + window_upper_limit/16) * timeout_reset_val + */ + ewdg_window_upper_limit_t window_upper_limit; + + bool enable_config_lock; /*!< Enable Lock for the Configuration Registers */ + + bool enable_refresh_period; /*!< Enable Refresh period */ + bool enable_refresh_lock; /*!< Enable Refresh lock */ + ewdg_refresh_unlock_method_t refresh_unlock_method; /*!< Method to unlock REFRESH_REG */ + + bool enable_overtime_self_clear; /*!< Enable Over time self clear */ + + bool keep_running_in_debug_mode; /*!< Keep running even in debug mode */ + ewdg_low_power_mode_t low_power_mode; /*!< Watchdog behavior in low power mode */ + /*! + * Select timeout value type + * - true: use the IP-level value (in terms of EWDG counter ticks) + * - false: Use the user friendly timeout value (in terms of microseconds) + */ + bool use_lowlevel_timeout; + union { + struct { + uint32_t timeout_interrupt_us; /*!< Timeout value for interrupt (in terms of microseconds) */ + uint32_t timeout_reset_us; /*!< Timeout value for reset (in terms of microseconds */ + }; + struct { + uint32_t timeout_interrupt_val; /*!< Timeout value for interrupt (in terms of counter ticks) */ + /*! Timeout value for reset (in terms of counter ticks + * Note: timeout_reset_val must > timeout_interrupt_val + */ + uint32_t timeout_reset_val; + uint32_t clock_div_by_power_of_2; /*!< Power of 2 Divider */ + }; + }; + + uint16_t refresh_period_in_bus_cycles; /*!< Refresh period */ + uint16_t refresh_unlock_password; /*!< Password for unlocking write to REFRESH_REG */ + + uint16_t ctrl_reg_update_password; /*!< Update Password */ + uint16_t ctrl_reg_update_period_bus_clk_x_128; /*!< Update Period */ +} ewdg_func_ctrl_config_t; + +/** + * @brief EWDG Reset and Interrupt Configurations + */ +typedef struct { + bool enable_ctrl_parity_fail_interrupt; /*!< Enable Parity Fail Interrupt */ + bool enable_ctrl_parity_fail_reset; /*!< Enable Parity Fail Reset */ + bool enable_ctrl_unlock_fail_interrupt; /*!< Enable Control Register Unlock Fail Interrupt */ + bool enable_ctrl_unlock_fail_reset; /*!< Enable Control Register Unlock Fail Reset */ + bool enable_ctrl_update_violation_interrupt; /*!< Enable Control Register Update Violation Interrupt */ + bool enable_ctrl_update_violation_reset; /*!< Enable Control Register Update Violation Reset */ + bool enable_timeout_interrupt; /*!< Enable Timeout Interrupt */ + bool enable_timeout_reset; /*!< Enable Timeout Reset */ + bool enable_refresh_unlock_fail_interrupt; /*!< Enable Refresh Unlock Fail Interrupt */ + bool enable_refresh_unlock_fail_reset; /*!< Enable Refresh Unlock Fail Reset */ + bool enable_refresh_violation_interrupt; /*!< Enable Refresh Violation Interrupt */ + bool enable_refresh_violation_reset; /*!< Enable Refresh Violation Reset */ +} ewdg_interrupt_reset_config_t; + +/** + * @brief Enhanced Watchdog Configuration Structure + */ +typedef struct { + ewdg_interrupt_reset_config_t int_rst_config; /*!< Error Control Configuration */ + ewdg_func_ctrl_config_t ctrl_config; /*!< Function Control Configuration */ + bool enable_watchdog; /*!< Enable Watchdog */ + uint32_t cnt_src_freq; /*!< Frequency for the clock used as the counter clock source */ +} ewdg_config_t; + +/** + * @brief Check whether the Control Registers are locked + * + * @param [in] ptr EWDG base + * + * @retval true Control Registers are locked + * @retval false Control Registers are unlocked + */ +static inline bool ewdg_is_ctrl_reg_locked(EWDG_Type *ptr) +{ + return ((ptr->CTRL0 & EWDG_CTRL0_CFG_LOCK_MASK) != 0U); +} + +/** + * @brief Get the Divider for Counter Clock + * + * @param [in] ptr EWDG base + * + * @return divider value + */ +static inline uint32_t ewdg_get_count_clk_divider(EWDG_Type *ptr) +{ + return (1UL << EWDG_CTRL0_DIV_VALUE_GET(ptr->CTRL0)); +} + +/** + * @brief Check whether the Refresh register is locked + * + * @param [in] ptr EWDG base + * + * @retval true Control Registers are locked + * @retval false Control Registers are unlocked + */ +static inline bool ewdg_is_refresh_locked(EWDG_Type *ptr) +{ + return ((ptr->CTRL0 & EWDG_CTRL0_REF_LOCK_MASK) != 0U); +} + +/** + * @brief Unlock Write to Control Registers + * + * @param [in] ptr EWDG base + */ +static inline void ewdg_unlock_ctrl_regs(EWDG_Type *ptr) +{ + uint32_t ctrl_update_prot = ptr->CFG_PROT; + ptr->CFG_PROT = ctrl_update_prot; +} + +/** + * @brief Write Refresh Magic Number to EWDG Refresh register + * @param [in] ptr EWDG base + */ +static inline void ewdg_write_refresh_reg(EWDG_Type *ptr) +{ + ptr->WDT_REFRESH_REG = EWDG_REFRESH_KEY; +} + +/** + * @brief Get the Timeout Reset ticks + * @param [in] ptr EWDG base + * @return Timeout Reset ticks + */ +static inline uint32_t ewdg_get_timeout_reset_ticks(EWDG_Type *ptr) +{ + return ptr->OT_RST_VAL; +} + +#if !defined(EWDG_SOC_SUPPORT_TIMEOUT_INTERRUPT) || (EWDG_SOC_SUPPORT_TIMEOUT_INTERRUPT == 1) +/** + * @brief Get the Timeout Interrupt ticks + * @param [in] ptr EWDG base + * @return Timeout Interrupt ticks + */ +static inline uint32_t ewdg_get_timeout_interrupt_ticks(EWDG_Type *ptr) +{ + return ptr->OT_INT_VAL; +} +#endif + +/** + * @brief Clear Interrupt Status for EWDG + * + * @note The TIMEOUT_INT_EVENT cannot be cleared directly, it needs to be cleared by the refresh sequence + * + * @param [in] ptr EWDG base + * @param [in] mask Status Mask Bits, @ref ewdg_event + */ +static inline void ewdg_clear_status_flags(EWDG_Type *ptr, uint32_t mask) +{ + ptr->WDT_STATUS = mask; +} + +/** + * @brief Get the Status of EWDG + * + * @param [in] ptr EWDG base + * + * @return STATUS register value + */ +static inline uint32_t ewdg_get_status_flags(EWDG_Type *ptr) +{ + return ptr->WDT_STATUS; +} + +/** + * @brief Get the Refresh Unlock Mechanism + * @param [in] ptr EWDG base + * @return EWDG refresh unlock method + */ +static inline ewdg_refresh_unlock_method_t ewdg_get_refresh_unlock_method(EWDG_Type *ptr) +{ + return (ewdg_refresh_unlock_method_t) (EWDG_CTRL0_REF_UNLOCK_MEC_GET(ptr->CTRL0)); +} + +/** + * @brief Enable EWDG + * + * This function enables the functionality of the EWDG and start the watchdog timer + * + * @param [in] ptr EWDG base + * + * @note Once the EWDG is enabled, + * - if the software needs to update the control register, the update unlock must be + * performed first if the control register lock is enabled. + * + */ +void ewdg_enable(EWDG_Type *ptr); + + +/** + * @brief Disable EWDG + * @param [in] ptr EWDG base + */ +void ewdg_disable(EWDG_Type *ptr); + +/** + * @brief Initialize the Control function for EWDG + * + * @param [in] ptr EWDG base + * @param [in] config Control Function Configuration + * @param [in] cnt_src_freq Source frequency for EWDG counter + * + * @retval status_invalid_argument Invalid argument was detected + * @retval status_success No error happened + */ +hpm_stat_t ewdg_init_ctrl_func(EWDG_Type *ptr, ewdg_func_ctrl_config_t *config, uint32_t cnt_src_freq); + +/** + * @brief Initialize the Error function for EWDG + * + * @param [in] ptr EWDG base + * @param [in] config Error Function Configuration + * + * @retval status_invalid_argument Invalid argument was detected + * @retval status_success No error happened + */ +hpm_stat_t ewdg_init_interrupt_reset(EWDG_Type *ptr, ewdg_interrupt_reset_config_t *config); + +/** + * @brief Get default configuration for EWDG + * @param [in] ptr EWDG base + * @param [out] config EWDG Configuration + */ +void ewdg_get_default_config(EWDG_Type *ptr, ewdg_config_t *config); + +/** + * @brief Initialize the EWDG module + * + * @param [in] ptr EWDG base + * @param [in] config EWDG configuration + * + * @retval status_invalid_argument Invalid argument was detected + * @retval status_success No error happened + */ +hpm_stat_t ewdg_init(EWDG_Type *ptr, ewdg_config_t *config); + +/** + * @brief Unlock the write to refresh register + * + * @param [in] ptr EWDG base + * + * @retval status_invalid_argument Invalid argument was detected + * @retval status_success No error happened + */ +hpm_stat_t ewdg_unlock_refresh(EWDG_Type *ptr); + +/** + * @brief Refresh EWDG + * + * @param [in] ptr EWDG base + * + * @retval status_invalid_argument Invalid argument was detected + * @retval status_success No error happened + */ +hpm_stat_t ewdg_refresh(EWDG_Type *ptr); + +/** + * @brief Get the Divided Counter Clock Frequency for EWDG + * + * @param [in] ptr EWDG base + * @param [in] src_clk_freq Source clock of the Counter clock + * + * @return divided Counter clock Frequency + */ +uint32_t ewdg_get_count_clock_freq(EWDG_Type *ptr, uint32_t src_clk_freq); + +/** + * @brief Convert the timeout in terms of microseconds to the timeout in terms of timeout ticks + * + * @param [in] src_clk_freq Clock Frequency of the counter clock source + * @param [in] timeout_us Timeout in terms of microseconds + * + * @return timeout in terms of counter clock ticks + */ +uint64_t ewdg_convert_timeout_us_to_timeout_ticks(uint32_t src_clk_freq, uint32_t timeout_us); + +/** + * @brief Convert the timeout in terms of timeout ticks to the timeout in terms of microseconds + * + * @param [in] ptr EWDG base + * @param [in] src_clk_freq Clock Frequency of the counter clock source + * @param [in] timeout_ticks Timeout in terms of ticks + * + * @return timeout in terms of counter clock ticks + */ +uint32_t ewdg_convert_timeout_ticks_to_timeout_us(EWDG_Type *ptr, uint32_t src_clk_freq, uint32_t timeout_ticks); + +/** + * @brief Enable EWDG interrupt + * @param [in] ptr EWDG base + * @param [in] mask Interrupt Mask, valid value refer to @ref ewdg_interrupt + */ +void ewdg_enable_interrupt(EWDG_Type *ptr, uint32_t mask); + +/** + * @brief Disable EWDG interrupt + * @param [in] ptr EWDG base + * @param [in] mask Interrupt Mask, valid value refer to @ref ewdg_interrupt + */ +void ewdg_disable_interrupt(EWDG_Type *ptr, uint32_t mask); + +/** + * @brief Enable EWDG Reset + * @param [in] ptr EWDG base + * @param [in] mask Reset Mask, valid value refer to @ref ewdg_reset_source + */ +void ewdg_enable_reset(EWDG_Type *ptr, uint32_t mask); + +/** + * @brief Disable EWDG Reset + * @param [in] ptr EWDG base + * @param [in] mask Reset Mask, valid value refer to @ref ewdg_reset_source + */ +void ewdg_disable_reset(EWDG_Type *ptr, uint32_t mask); + +/** + * @brief Switch the EWDG clock source + * @param [in] ptr EWDG base + * @param [in] clk_sel Clock source selection for EWDG counter + */ +void ewdg_switch_clock_source(EWDG_Type *ptr, ewdg_cnt_clk_sel_t clk_sel); + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* HPM_EWDG_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_femc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_femc_drv.h index 4d532ad4bf4..e9f3af7712b 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_femc_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_femc_drv.h @@ -127,6 +127,7 @@ typedef struct { uint8_t idle_timeout_in_ns; uint8_t data_width_in_byte; uint8_t auto_refresh_count_in_one_burst; + bool delay_cell_disable; /**< Delay cell disable */ uint8_t delay_cell_value; /**< Delay cell value */ } femc_sdram_config_t; diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gpio_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gpio_drv.h index 2f63a38c5eb..d0be414a14e 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gpio_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gpio_drv.h @@ -10,6 +10,7 @@ #include "hpm_common.h" #include "hpm_gpio_regs.h" +#include "hpm_soc_feature.h" #ifndef PORT_PIN_COUNT #define PORT_PIN_COUNT (32U) @@ -33,6 +34,9 @@ typedef enum gpio_interrupt_trigger { gpio_interrupt_trigger_level_low, gpio_interrupt_trigger_edge_rising, gpio_interrupt_trigger_edge_falling, +#if defined(GPIO_SOC_HAS_EDGE_BOTH_INTERRUPT) && (GPIO_SOC_HAS_EDGE_BOTH_INTERRUPT == 1) + gpio_interrupt_trigger_edge_both, +#endif } gpio_interrupt_trigger_t; #ifdef __cplusplus @@ -53,6 +57,20 @@ static inline uint8_t gpio_read_pin(GPIO_Type *ptr, uint32_t port, uint8_t pin) return (ptr->DI[port].VALUE & (1 << pin)) >> pin; } +/** + * @brief Read target pin output state + * + * @param ptr GPIO base address + * @param port Port index + * @param pin Pin index + * + * @return Pin output state + */ +static inline uint32_t gpio_get_pin_output_status(GPIO_Type *ptr, uint32_t port, uint8_t pin) +{ + return (ptr->DO[port].VALUE & (1 << pin)) >> pin; +} + /** * @brief Toggle pin level * @@ -153,7 +171,7 @@ static inline void gpio_clear_pin_interrupt_flag(GPIO_Type *ptr, uint32_t port, */ static inline bool gpio_check_pin_interrupt_enabled(GPIO_Type *ptr, uint32_t port, uint8_t pin) { - return (ptr->IE[port].VALUE & (1 << pin)) == (1 << pin); + return (ptr->IE[port].VALUE & (1 << pin)) == (uint32_t) (1 << pin); } /** diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gptmr_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gptmr_drv.h index 2ba06c88df4..ca1e1731b0a 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gptmr_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gptmr_drv.h @@ -267,7 +267,7 @@ static inline bool gptmr_check_status(GPTMR_Type *ptr, uint32_t mask) */ static inline void gptmr_clear_status(GPTMR_Type *ptr, uint32_t mask) { - ptr->SR |= mask; + ptr->SR = mask; } /** @@ -330,6 +330,7 @@ static inline void gptmr_disable_cmp_output(GPTMR_Type *ptr, uint8_t ch_index) * * @param [in] ptr GPTMR base address * @param [in] ch_index channel index + * @param [in] mode enum gptmr_work_mode_capture_at_rising_edge or gptmr_work_mode_capture_at_falling_edge and so on */ static inline void gptmr_channel_set_capmode(GPTMR_Type *ptr, uint8_t ch_index, gptmr_work_mode_t mode) { diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gwc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gwc_drv.h new file mode 100644 index 00000000000..dc4da1278f1 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gwc_drv.h @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_GWC_DRV_H +#define HPM_GWC_DRV_H + +/** + * @brief GWC APIs + * @defgroup gwc_interface GWC driver APIs + * @ingroup gwc_interfaces + * @{ + */ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_gwc_regs.h" + +/** + * @brief gwc channel config + * + * @note area of channel do not overlap. in other words, eache pixel belongs to a single channel at most. + */ +typedef struct gwc_ch_config { + bool freeze; /*!< freeze the channel configuration except reference CRC32 value setting. */ + uint16_t start_col; /*!< start col is X of upper left corner. Range: 0 to 2^13-1. */ + uint16_t start_row; /*!< start row is Y of upper left corner. Range: 0 to 2^12-1. */ + uint16_t end_col; /*!< end col is X of lower right corner. Range: 0 to 2^13-1. */ + uint16_t end_row; /*!< end row is Y of lower right corner. Range: 0 to 2^12-1. */ + uint32_t ref_crc; /*!< Reference CRC32 value.*/ +} gwc_ch_config_t; + +/** + * @brief gwc clk polarity + */ +typedef enum gwc_clk_pol { + gwc_clk_pol_normal = 0, + gwc_clk_pol_invert +} gwc_clk_pol_t; + +/** + * @brief gwc config + */ +typedef struct gwc_config { + gwc_clk_pol_t clk_pol; +} gwc_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief init the gwc + * + * @param[in] cfg GWC config @ref gwc_config_t + */ +void gwc_get_default_config(gwc_config_t *cfg); + +/** + * @brief init the gwc + * + * @param[in] ptr GWC base address + * @param[in] cfg GWC config @ref gwc_config_t + * + * @note the function is called while gwc is disable only + */ +void gwc_init(GWC_Type *ptr, gwc_config_t *cfg); + +/** + * @brief enable the gwc + * + * @param[in] ptr GWC base address + */ +void gwc_enable(GWC_Type *ptr); + +/** + * @brief disable the gwc + * + * @param[in] ptr GWC base address + */ +void gwc_disable(GWC_Type *ptr); + +/** + * @brief enable interrupts + * + * @param[in] ptr GWC base address + * @param[in] mask Mask of interrupt events that would be enabled + * @ref GWC_IRQ_MASK_ERR_MASK_MASK + * @ref GWC_IRQ_MASK_FUNC_MASK_MASK + */ +static inline void gwc_enable_interrupt(GWC_Type *ptr, uint32_t mask) +{ + ptr->IRQ_MASK &= ~mask; +} + +/** + * @brief disable interrupts. + * + * @param[in] ptr GWC base address + * @param[in] mask mask of interrupt events that would be enabled. + * @ref GWC_IRQ_MASK_ERR_MASK_MASK + * @ref GWC_IRQ_MASK_FUNC_MASK_MASK + */ +static inline void gwc_disable_interrupt(GWC_Type *ptr, uint32_t mask) +{ + ptr->IRQ_MASK |= mask; +} + +/** + * @brief get gwc status flag + * + * @param[in] ptr GWC base address + * @return gwc status + */ +static inline uint32_t gwc_get_status(GWC_Type *ptr) +{ + return ptr->IRQ_STS; +} + +/** + * @brief clear gwc status flag + * + * @param[in] ptr GWC base address + * @param[in] mask logical OR'ed of GWC_IRQ_STS_XXX_STS_MASK + */ +static inline void gwc_clear_status(GWC_Type *ptr, uint32_t mask) +{ + ptr->IRQ_STS = mask; +} + +/** + * @brief disable change of interrupt masks + * + * Once this function is called, the interrupt enabled status could not be changed + * until reset. + * + * @param[in] ptr GWC base address + */ +void gwc_freeze_interrupt_control(GWC_Type *ptr); + +/** + * @brief init gwc channel + * + * @param[in] ptr GWC base address + * @param[in] ch_index channel index ref GWC_CHANNEL_CHn + * @param[in] cfg config of gwc channel + * + * @note the function is called while gwc channel is disable only + */ +void gwc_ch_init(GWC_Type *ptr, uint8_t ch_index, gwc_ch_config_t *cfg); + +/** + * @brief enable gwc channel + * + * @param[in] ptr GWC base address + * @param[in] ch_index channel index ref GWC_CHANNEL_CHn + */ +static inline void gwc_ch_enable(GWC_Type *ptr, uint8_t ch_index) +{ + assert(ch_index <= GWC_CHANNEL_CH15); + ptr->CHANNEL[ch_index].CFG0 |= GWC_CHANNEL_CFG0_ENABLE_MASK; +} + +/** + * @brief disable gwc channel + * + * @param[in] ptr GWC base address + * @param[in] ch_index channel index ref GWC_CHANNEL_CHn + */ +static inline void gwc_ch_disable(GWC_Type *ptr, uint8_t ch_index) +{ + assert(ch_index <= GWC_CHANNEL_CH15); + ptr->CHANNEL[ch_index].CFG0 &= ~GWC_CHANNEL_CFG0_ENABLE_MASK; +} + +/** + * @brief get gwc channel calc crc + * + * @param[in] ptr GWC base address + * @param[in] ch_index channel index ref GWC_CHANNEL_CHn + */ +static inline uint32_t gwc_ch_get_crc(GWC_Type *ptr, uint8_t ch_index) +{ + assert(ch_index <= GWC_CHANNEL_CH15); + return ptr->CHANNEL[ch_index].CALCRC; +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ +#endif /* HPM_GWC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2c_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2c_drv.h index 18f50a25b6e..aefc9507905 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2c_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2c_drv.h @@ -29,7 +29,7 @@ enum { status_i2c_not_supported = MAKE_STATUS(status_group_i2c, 9), }; -/* convert data count value into CTRL[DATACNT] value map */ +/* convert data count value into register(CTRL[DATACNT] and CTRL[DATACNT_HIGH] if exist) */ /* x range from 1 to I2C_SOC_TRANSFER_COUNT_MAX */ /* 0 for I2C_SOC_TRANSFER_COUNT_MAX */ #define I2C_DATACNT_MAP(x) (((x) == I2C_SOC_TRANSFER_COUNT_MAX) ? 0 : x) @@ -85,6 +85,13 @@ enum { #define I2C_STATUS_BUS_BUSY I2C_STATUS_BUSBUSY_MASK #define I2C_STATUS_ACK I2C_STATUS_ACK_MASK +#define I2C_WR 0x0000 /* not operable with read flags*/ +#define I2C_RD (1u << 0) /* not operable with write flags*/ +#define I2C_ADDR_10BIT (1u << 2) /* this is a ten bit chip address */ +#define I2C_NO_START (1u << 4) /* no start */ +#define I2C_NO_READ_ACK (1u << 6) /* when I2C reading, we do not ACK */ +#define I2C_NO_STOP (1u << 7) /* no stop */ + /** * @brief I2C config */ @@ -158,7 +165,8 @@ static inline void i2c_clear_fifo(I2C_Type *ptr) */ static inline uint8_t i2c_get_data_count(I2C_Type *ptr) { - return I2C_CTRL_DATACNT_GET(ptr->CTRL); + uint32_t i2c_ctrl = ptr->CTRL; + return (I2C_CTRL_DATACNT_HIGH_GET(i2c_ctrl) << 8U) + I2C_CTRL_DATACNT_GET(i2c_ctrl); } /** @@ -263,7 +271,7 @@ static inline bool i2c_get_line_scl_status(I2C_Type *ptr) */ static inline void i2c_clear_status(I2C_Type *ptr, uint32_t mask) { - ptr->STATUS |= (mask & I2C_EVENT_ALL_MASK); + ptr->STATUS = mask; } /** @@ -599,8 +607,8 @@ hpm_stat_t i2c_master_configure_transfer(I2C_Type *i2c_ptr, const uint16_t devic /** * @brief sequential transmit in master I2C mode an amount of data in blocking * - * @param i2c_ptr [in] ptr I2C base address - * @param device_address [in] I2C slave address + * @param [in] ptr ptr I2C base address + * @param [in] device_address I2C slave address * @param [in] buf pointer of the buffer to store data sent from device * @param [in] size size of data to be sent in bytes * @param [in] opt I2c sequential transfer options @@ -612,8 +620,8 @@ hpm_stat_t i2c_master_seq_transmit(I2C_Type *ptr, const uint16_t device_address, /** * @brief sequential receive in master I2C mode an amount of data in blocking * - * @param i2c_ptr [in] ptr I2C base address - * @param device_address [in] I2C slave address + * @param [in] ptr ptr I2C base address + * @param [in] device_address I2C slave address * @param [in] buf pointer of the buffer to store data sent from device * @param [in] size size of data to be sent in bytes * @param [in] opt I2c sequential transfer options @@ -622,6 +630,32 @@ hpm_stat_t i2c_master_seq_transmit(I2C_Type *ptr, const uint16_t device_address, hpm_stat_t i2c_master_seq_receive(I2C_Type *ptr, const uint16_t device_address, uint8_t *buf, const uint32_t size, i2c_seq_transfer_opt_t opt); +#if defined(HPM_IP_FEATURE_I2C_SUPPORT_RESET) && (HPM_IP_FEATURE_I2C_SUPPORT_RESET == 1) +/** + * @brief generate SCL clock as reset signal + * + * @param ptr [in] ptr I2C base address + * @param [in] clk_len SCL clock length + */ +static inline void i2s_gen_reset_signal(I2C_Type *ptr, uint8_t clk_len) +{ + ptr->CTRL = (ptr->CTRL & ~I2C_CTRL_RESET_LEN_MASK) | I2C_CTRL_RESET_LEN_SET(clk_len) \ + | I2C_CTRL_RESET_HOLD_SCKIN_MASK | I2C_CTRL_RESET_ON_MASK; +} +#endif + +/** + * @brief data transfer on master I2C mode in blocking + * + * @param [in] ptr ptr I2C base address + * @param [in] device_address I2C slave address + * @param [in] buf pointer of the buffer to store data sent from device + * @param [in] size size of data to be sent in bytes + * @param [in] flags flag bit, which can be other flag bits except I2C_WR I2C_RD, and can perform "|" operation + * @retval hpm_stat_t status_success if receive is completed without any error + */ +hpm_stat_t i2c_master_transfer(I2C_Type *ptr, const uint16_t device_address, + uint8_t *buf, const uint32_t size, uint16_t flags); /** * @} */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2s_common.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2s_common.h index 7ff4be01257..146e494c999 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2s_common.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2s_common.h @@ -22,6 +22,13 @@ #define I2S_PROTOCOL_RIGHT_JUSTIFIED (2U) #define I2S_PROTOCOL_PCM (3U) +/* i2s channel slot mask */ +#define I2S_CHANNEL_SLOT_MASK(x) (1U << (x)) +/* convert audio depth value into CFGR[DATASIZ] value map */ +#define I2S_CFGR_DATASIZ(x) ((x - 16) >> 3) +/* convert channel length value into CFGR[CHSIZ] value map */ +#define I2S_CFGR_CHSIZ(x) ((x - 16) >> 4) + /** * @brief I2S audio depth */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2s_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2s_drv.h index 2b6399559f8..10fbf56312a 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2s_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2s_drv.h @@ -19,13 +19,6 @@ * @{ */ -/* i2s channel slot mask */ -#define I2S_CHANNEL_SLOT_MASK(x) (1U << (x)) -/* convert audio depth value into CFGR[DATASIZ] value map */ -#define I2S_CFGR_DATASIZ(x) ((x - 16) >> 3) -/* convert channel length value into CFGR[CHSIZ] value map */ -#define I2S_CFGR_CHSIZ(x) ((x - 16) >> 4) - /** * @brief I2S data line */ @@ -50,7 +43,8 @@ typedef struct i2s_config { bool use_external_fclk; bool enable_mclk_out; bool frame_start_at_rising_edge; - uint16_t fifo_threshold; + uint16_t tx_fifo_threshold; + uint16_t rx_fifo_threshold; } i2s_config_t; /** @@ -234,6 +228,8 @@ static inline void i2s_disable_irq(I2S_Type *ptr, uint32_t mask) /** * @brief I2S enable * + * @note dropped API, please use i2s_start + * * @param [in] ptr I2S base address */ static inline void i2s_enable(I2S_Type *ptr) @@ -244,6 +240,8 @@ static inline void i2s_enable(I2S_Type *ptr) /** * @brief I2S disable * + * @note dropped API, please use i2s_stop + * * @param [in] ptr I2S base address */ static inline void i2s_disable(I2S_Type *ptr) @@ -251,6 +249,26 @@ static inline void i2s_disable(I2S_Type *ptr) ptr->CTRL &= ~I2S_CTRL_I2S_EN_MASK; } +/** + * @brief I2S start + * + * @param [in] ptr I2S base address + */ +static inline void i2s_start(I2S_Type *ptr) +{ + ptr->CTRL |= I2S_CTRL_I2S_EN_MASK; +} + +/** + * @brief I2S stop + * + * @param [in] ptr I2S base address + */ +static inline void i2s_stop(I2S_Type *ptr) +{ + ptr->CTRL &= ~I2S_CTRL_I2S_EN_MASK; +} + /** * @brief I2S enable rx function * @@ -296,61 +314,80 @@ static inline void i2s_disable_tx(I2S_Type *ptr, uint8_t tx_mask) } /** - * @brief I2S clear tx fifo + * @brief I2S reset clock generator * * @param [in] ptr I2S base address */ -static inline void i2s_clear_tx_fifo(I2S_Type *ptr) +static inline void i2s_reset_clock_gen(I2S_Type *ptr) { - ptr->CTRL |= I2S_CTRL_TXFIFOCLR_MASK; - while (ptr->CTRL & I2S_CTRL_TXFIFOCLR_MASK) { - } + ptr->CTRL |= I2S_CTRL_SFTRST_CLKGEN_MASK; + ptr->CTRL &= ~I2S_CTRL_SFTRST_CLKGEN_MASK; } /** - * @brief I2S clear rx fifo + * @brief I2S reset tx function + * + * @note This API will disable I2S, reset tx function + * Please ensure that there is a valid BCLK when calling this function * * @param [in] ptr I2S base address */ -static inline void i2s_clear_rx_fifo(I2S_Type *ptr) +static inline void i2s_reset_tx(I2S_Type *ptr) { - ptr->CTRL |= I2S_CTRL_RXFIFOCLR_MASK; - while (ptr->CTRL & I2S_CTRL_RXFIFOCLR_MASK) { - } + /* disable I2S */ + ptr->CTRL &= ~I2S_CTRL_I2S_EN_MASK; + + /* reset tx and clear fifo */ + ptr->CTRL |= (I2S_CTRL_TXFIFOCLR_MASK | I2S_CTRL_SFTRST_TX_MASK); + ptr->CTRL &= ~(I2S_CTRL_TXFIFOCLR_MASK | I2S_CTRL_SFTRST_TX_MASK); } /** - * @brief I2S reset clock generator + * @brief I2S reset rx function + * + * @note This API will disable I2S, reset rx function + * Please ensure that there is a valid BCLK when calling this function * * @param [in] ptr I2S base address */ -static inline void i2s_reset_clock_gen(I2S_Type *ptr) +static inline void i2s_reset_rx(I2S_Type *ptr) { - ptr->CTRL |= I2S_CTRL_SFTRST_CLKGEN_MASK; - ptr->CTRL &= ~I2S_CTRL_SFTRST_CLKGEN_MASK; + /* disable I2S */ + ptr->CTRL &= ~I2S_CTRL_I2S_EN_MASK; + + /* reset rx and clear fifo */ + ptr->CTRL |= (I2S_CTRL_RXFIFOCLR_MASK | I2S_CTRL_SFTRST_RX_MASK); + ptr->CTRL &= ~(I2S_CTRL_RXFIFOCLR_MASK | I2S_CTRL_SFTRST_RX_MASK); } /** - * @brief I2S reset tx function + * @brief I2S reset tx and rx function + * + * @note This API will disable I2S, reset tx/rx function + * Please ensure that there is a valid BCLK when calling this function * * @param [in] ptr I2S base address */ -static inline void i2s_reset_tx(I2S_Type *ptr) +static inline void i2s_reset_tx_rx(I2S_Type *ptr) { - ptr->CTRL |= I2S_CTRL_SFTRST_TX_MASK; - ptr->CTRL &= ~I2S_CTRL_SFTRST_TX_MASK; + /* disable I2S */ + ptr->CTRL &= ~I2S_CTRL_I2S_EN_MASK; + + /* reset tx/rx and clear fifo */ + ptr->CTRL |= (I2S_CTRL_TXFIFOCLR_MASK | I2S_CTRL_RXFIFOCLR_MASK | I2S_CTRL_SFTRST_TX_MASK | I2S_CTRL_SFTRST_RX_MASK); + ptr->CTRL &= ~(I2S_CTRL_TXFIFOCLR_MASK | I2S_CTRL_RXFIFOCLR_MASK | I2S_CTRL_SFTRST_TX_MASK | I2S_CTRL_SFTRST_RX_MASK); } /** - * @brief I2S reset rx function + * @brief I2S reset tx/rx and clock generator module + * + * @note This API will disable I2S, reset tx/rx and clock generator module + * This function uses an internal clock to generate BCLK, then do reset operation, + * and finally restores the previous clock settings * * @param [in] ptr I2S base address */ -static inline void i2s_reset_rx(I2S_Type *ptr) -{ - ptr->CTRL |= I2S_CTRL_SFTRST_RX_MASK; - ptr->CTRL &= ~I2S_CTRL_SFTRST_RX_MASK; -} +void i2s_reset_all(I2S_Type *ptr); /** * @brief I2S get tx fifo level @@ -469,6 +506,8 @@ static inline void i2s_stop_transfer(I2S_Type *ptr) /** * @brief I2S config tx * + * @note This API will disable I2S and configure parameters, could call i2s_enable() to enable I2S + * * @param [in] ptr I2S base address * @param [in] mclk_in_hz mclk frequency in Hz * @param [in] config i2s_transfer_config_t @@ -479,6 +518,8 @@ hpm_stat_t i2s_config_tx(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config /** * @brief I2S config tx for slave * + * @note This API will disable I2S and configure parameters, could call i2s_enable() to enable I2S + * * @param [in] ptr I2S base address * @param [in] config i2s_transfer_config_t */ @@ -487,6 +528,8 @@ hpm_stat_t i2s_config_tx_slave(I2S_Type *ptr, i2s_transfer_config_t *config); /** * @brief I2S config rx * + * @note This API will disable I2S and configure parameters, could call i2s_enable() to enable I2S + * * @param [in] ptr I2S base address * @param [in] mclk_in_hz mclk frequency in Hz * @param [in] config i2s_transfer_config_t @@ -497,6 +540,8 @@ hpm_stat_t i2s_config_rx(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config /** * @brief I2S config rx for slave * + * @note This API will disable I2S and configure parameters, could call i2s_enable() to enable I2S + * * @param [in] ptr I2S base address * @param [in] config i2s_transfer_config_t * @retval hpm_stat_t status_invalid_argument or status_success @@ -506,6 +551,8 @@ hpm_stat_t i2s_config_rx_slave(I2S_Type *ptr, i2s_transfer_config_t *config); /** * @brief I2S config transfer * + * @note This API will disable I2S and configure parameters, could call i2s_enable() to enable I2S + * * @param [in] ptr I2S base address * @param [in] mclk_in_hz mclk frequency in Hz * @param [in] config i2s_transfer_config_t @@ -516,6 +563,8 @@ hpm_stat_t i2s_config_transfer(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_ /** * @brief I2S config transfer for slave * + * @note This API will disable I2S and configure parameters, could call i2s_enable() to enable I2S + * * @param [in] ptr I2S base address * @param [in] config i2s_transfer_config_t * @retval hpm_stat_t status_invalid_argument or status_success @@ -609,6 +658,19 @@ void i2s_get_default_transfer_config_for_dao(i2s_transfer_config_t *transfer); */ void i2s_get_default_transfer_config(i2s_transfer_config_t *transfer); +/** + * @brief I2S fill dummy data into TX fifo + * + * @note workaround: fill dummy data into TX fifo to avoid TX underflow during tx start + * + * @param [in] ptr I2S base address + * @param [in] data_line data line + * @param [in] data_count dummy data count, This value should be the same as the number of audio channels + * + * @retval status_success if no error occurred + */ +hpm_stat_t i2s_fill_tx_dummy_data(I2S_Type *ptr, uint8_t data_line, uint8_t data_count); + /** * @} */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lcb_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lcb_drv.h new file mode 100644 index 00000000000..2dae9197cfc --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lcb_drv.h @@ -0,0 +1,234 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_LCB_DRV_H +#define HPM_LCB_DRV_H + +/** + * @brief LCB APIs + * @defgroup lcb_interface LCB driver APIs + * @ingroup lcb_interfaces + * @{ + */ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_lcb_regs.h" + +typedef enum lcb_rxclk_sel { + lcb_rxclk_sel_phy0 = 0, + lcb_rxclk_sel_phy1 = 1, +} lcb_rxclk_sel_t; + +typedef enum lcb_mode { + lcb_mode_display = 0, + lcb_mode_cam_link = 1, +} lcb_mode_t; + +typedef enum lcb_display_mode_mapping { + lcb_display_mode_mapping_vesa = 0, + lcb_display_mode_mapping_jeida = 1, +} lcb_display_mode_mapping_t; + +typedef enum lcb_display_mode_data_width { + lcb_display_mode_data_width_18bit = 0, + lcb_display_mode_data_width_24bit = 1, +} lcb_display_mode_data_width_t; + +typedef struct lcb_display_mode_config { + lcb_display_mode_mapping_t map; + lcb_display_mode_data_width_t data_width; +} lcb_display_mode_config_t; + +typedef enum lcb_cam_link_mode_data_width { + lcb_cam_link_mode_data_width_24bit = 0, + lcb_cam_link_mode_data_width_30bit = 1, + lcb_cam_link_mode_data_width_36bit = 1, +} lcb_cam_link_mode_data_width_t; + +typedef struct lcb_cam_link_mode_config { + lcb_cam_link_mode_data_width_t data_width; +} lcb_cam_link_mode_config_t; + +typedef struct lcb_config { + lcb_rxclk_sel_t rxclk_sel; + lcb_mode_t mode; + union { + lcb_display_mode_config_t display; + lcb_cam_link_mode_config_t cam_link; + }; +} lcb_config_t; + +/** + * @brief Terminal impedance regulation + */ +typedef enum lcb_lvds_phy_rterm { + lcb_lvds_phy_rterm_hi_z = 0, + lcb_lvds_phy_rterm_150_ohm = 1, + lcb_lvds_phy_rterm_100_ohm = 8, + lcb_lvds_phy_rterm_75_ohm = 15, +} lcb_lvds_phy_rterm_t; + +typedef struct lcb_lvds_phy_data_lane_config { + uint8_t dline_adj; /*!< Lane N skew adjustment value between data and clock. 0000000: max; 1111111: min */ + lcb_lvds_phy_rterm_t rterm; /*!< Terminal impedance regulation */ +} lcb_lvds_phy_data_lane_config_t; + +/** + * @brief DLL loop delay adjustment minimum frequency + */ +typedef enum lcb_lvds_phy_dll_delay_adj_min_freq { + lcb_lvds_phy_dll_delay_adj_min_freq_40_70mhz = 0, + lcb_lvds_phy_dll_delay_adj_min_freq_70_110mhz = 0, +} lcb_lvds_phy_dll_delay_adj_min_freq_t; + +typedef struct lcb_lvds_phy_clk_lane_config { + lcb_lvds_phy_dll_delay_adj_min_freq_t min_adj; + uint16_t dll_tuning_int; /*!< DLL loop delay coarse adjustment initial value. 00000000: min ; 11111111: max */ + lcb_lvds_phy_rterm_t rterm; /*!< Terminal impedance regulation */ +} lcb_lvds_phy_clk_lane_config_t; + +typedef enum lcb_lvds_phy_data_lane_id { + lcb_lvds_phy_data_lane_id_0 = 0, + lcb_lvds_phy_data_lane_id_1 = 1, +} lcb_lvds_phy_data_lane_id_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief get LCB of default config + * + * @param[out] cfg config of LCB + */ +void lcb_get_default_config(lcb_config_t *cfg); + +/** + * @brief LCB init + * + * @param[in] ptr LCB base address + * @param[in] cfg config of LCB + */ +void lcb_init(LCB_Type *ptr, lcb_config_t *cfg); + +/** + * @brief get LCB clk_lane of default config + * + * @param[out] cfg config of clk_lane + */ +void lcb_get_phy_clk_lane_default_config(lcb_lvds_phy_clk_lane_config_t *cfg); + +/** + * @brief get LCB data_lane of default config + * + * @param[out] cfg config of data_lane + */ +void lcb_get_phy_data_lane_default_config(lcb_lvds_phy_data_lane_config_t *cfg); + +/** + * @brief LCB phy0 data lane config + * + * @param[in] ptr LCB base address + * @param[in] cfg config of phy0 data lane + * @param[in] lane_id data lane id + */ +void lcb_lvds_phy0_data_lane_config(LCB_Type *ptr, lcb_lvds_phy_data_lane_config_t *cfg, lcb_lvds_phy_data_lane_id_t lane_id); + +/** + * @brief LCB phy0 clk lane config + * + * @param[in] ptr LCB base address + * @param[in] cfg config of phy0 clk lane + */ +void lcb_lvds_phy0_clk_lane_config(LCB_Type *ptr, lcb_lvds_phy_clk_lane_config_t *cfg); + +/** + * @brief LCB phy1 data lane config + * + * @param[in] ptr LCB base address + * @param[in] cfg config of phy1 data lane + * @param[in] lane_id data lane id + */ +void lcb_lvds_phy1_data_lane_config(LCB_Type *ptr, lcb_lvds_phy_data_lane_config_t *cfg, lcb_lvds_phy_data_lane_id_t lane_id); + +/** + * @brief LCB phy1 clk lane config + * + * @param[in] ptr LCB base address + * @param[in] cfg config of phy1 clk lane + */ +void lcb_lvds_phy1_clk_lane_config(LCB_Type *ptr, lcb_lvds_phy_clk_lane_config_t *cfg); + +/** + * @brief power on LCB phy0 + * + * @param[in] ptr LCB base address + */ +void lcb_lvds_phy0_poweron(LCB_Type *ptr); + +/** + * @brief power on LCB phy1 + * + * @param[in] ptr LCB base address + */ +void lcb_lvds_phy1_poweron(LCB_Type *ptr); + +/** + * @brief power down LCB phy0 + * + * @param[in] ptr LCB base address + */ +void lcb_lvds_phy0_powerdown(LCB_Type *ptr); + +/** + * @brief power on LCB phy1 + * + * @param[in] ptr LCB base address + */ +void lcb_lvds_phy1_powerdown(LCB_Type *ptr); + +/** + * @brief check LCB phy0 is lock + * + * @param[in] ptr LCB base address + */ +static inline bool lcb_lvds_phy0_dll_is_lock(LCB_Type *ptr) +{ + return !!LCB_PHY_STAT_LVDS0_RX_PHY_DLL_LOCK_GET(ptr->PHY_STAT); +} + +/** + * @brief check LCB phy1 is lock + * + * @param[in] ptr LCB base address + */ +static inline bool lcb_lvds_phy1_dll_is_lock(LCB_Type *ptr) +{ + return !!LCB_PHY_STAT_LVDS1_RX_PHY_DLL_LOCK_GET(ptr->PHY_STAT); +} + +/** + * @brief check LCB display phy is lock + * + * @param[in] ptr LCB base address + */ +static inline bool lcb_lvds_display_phy_dll_is_lock(LCB_Type *ptr) +{ + return !!LCB_PHY_STAT_LVDS0_RX_PHY_DLL_LOCK_GET(ptr->PHY_STAT) && + !!LCB_PHY_STAT_LVDS1_RX_PHY_DLL_LOCK_GET(ptr->PHY_STAT); +} + + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ +#endif /* HPM_LCB_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lcdc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lcdc_drv.h index dbf95124592..c6bc1bae3aa 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lcdc_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lcdc_drv.h @@ -101,6 +101,7 @@ typedef struct lcdc_layer_config { uint16_t position_y; /**< Layer output position Y coord */ display_color_32b_t background; /**< Background color */ uint32_t buffer; /**< Pointer of layer display buffer */ + uint32_t stride; /**< stride of lines in bytes. stride is calculated by driver if stride == 0. */ } lcdc_layer_config_t; #ifdef __cplusplus @@ -383,6 +384,31 @@ static inline void lcdc_set_background(LCDC_Type *ptr, | LCDC_BGND_CL_B_SET(color.b); } +/** + * + * @brief enable background on alpha blender + * + * @note it not depend the background color of the layer itself. it can be used with lcdc_set_background API + * + * @param[in] ptr LCD base address + */ +static inline void lcdc_enable_background_in_alpha_blender(LCDC_Type *ptr) +{ + ptr->CTRL |= LCDC_CTRL_BGDCL4CLR_MASK; +} + +/** + * + * @brief disable background on alpha blender + * + * @note if not use background but want depend the the background color of the layer itself, can be use the API + * + * @param[in] ptr LCD base address + */ +static inline void lcdc_disable_background_in_alpha_blender(LCDC_Type *ptr) +{ + ptr->CTRL &= ~LCDC_CTRL_BGDCL4CLR_MASK; +} /** * * @brief Get default layer configuration value diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_linv2_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_linv2_drv.h new file mode 100644 index 00000000000..57ce9e6371d --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_linv2_drv.h @@ -0,0 +1,376 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_LINV2_DRV_H +#define HPM_LINV2_DRV_H + +#include +#include "hpm_common.h" +#include "hpm_linv2_regs.h" +#include "hpm_soc_feature.h" + +/** + * @brief LINV2 driver APIs + * @defgroup linv2_interface LINV2 driver APIs + * @ingroup linv2_interfaces + * @{ + */ + +/** bit4 and bit5 encode data length in ID */ +#define LIN_ID_DATA_LEN_SHIFT 4U +#define LIN_ID_DATA_LEN_MASK 0x30U +#define LIN_ID_DATA_LEN_GET(x) (((uint8_t)(x) & LIN_ID_DATA_LEN_MASK) >> LIN_ID_DATA_LEN_SHIFT) + +/** + * @brief data length in ID bit4 and bit5 + */ +typedef enum { + id_data_length_2bytes, + id_data_length_2bytes_2, /**< both 0 and 1 represent 2 bytes */ + id_data_length_4bytes, + id_data_length_8bytes +} lin_id_data_length_t; + +/** + * @brief bus inactivity tome to go to sleep + */ +typedef enum { + bus_inactivity_time_4s, + bus_inactivity_time_6s, + bus_inactivity_time_8s, + bus_inactivity_time_10s +} lin_bus_inactivity_time_t; + +/** + * @brief wakeup repeat time + */ +typedef enum { + wakeup_repeat_time_180ms, + wakeup_repeat_time_200ms, + wakeup_repeat_time_220ms, + wakeup_repeat_time_240ms +} lin_wakeup_repeat_time_t; + +typedef struct { + uint32_t src_freq_in_hz; /**< Source clock frequency in Hz */ + uint32_t baudrate; /**< Baudrate */ +} lin_timing_t; + +/** + * @brief LIN config + */ +typedef struct { + uint8_t id; /**< ID */ + uint8_t *data_buff; /**< data buff */ + bool data_length_from_id; /**< data length should be decoded from the identifier or not, dma mode not use this config */ + uint8_t data_length; /**< used when data_length_from_id is false or dma mode */ + bool enhanced_checksum; /**< true for enhanced checksum; false for classic checksum */ + bool transmit; /**< true for transmit operation; false for receive operation */ + /* bool start; */ /**< true for start operation; false for only configuration */ +} lin_trans_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief lin get control and status register value + * + * @param [in] ptr lin base address + * @return uint32_t control and status register value + */ +static inline uint32_t lin_get_control_and_status(LINV2_Type *ptr) +{ + return ptr->CONTROL_STATUS; +} + +/** + * @brief lin reset interrupt + * + * @param ptr lin base address + */ +static inline void lin_reset_interrupt(LINV2_Type *ptr) +{ + ptr->CONTROL_STATUS = ((ptr->CONTROL_STATUS) & ~LINV2_CONTROL_STATUS_SLEEP_MASK) | LINV2_CONTROL_STATUS_RESET_INT_MASK; +} + +/** + * @brief lin reset error + * + * @param ptr lin base address + */ +static inline void lin_reset_error(LINV2_Type *ptr) +{ + ptr->CONTROL_STATUS = ((ptr->CONTROL_STATUS) & ~LINV2_CONTROL_STATUS_SLEEP_MASK) | LINV2_CONTROL_STATUS_RESET_ERROR_MASK; +} + +/** + * @brief lin wakeup + * + * @param ptr lin base address + */ +static inline void lin_wakeup(LINV2_Type *ptr) +{ + ptr->CONTROL_STATUS = ((ptr->CONTROL_STATUS) & ~LINV2_CONTROL_STATUS_SLEEP_MASK) | LINV2_CONTROL_STATUS_WAKEUP_REQ_MASK; +} + +/** + * @brief lin sleep + * + * @param ptr lin base address + */ +static inline void lin_sleep(LINV2_Type *ptr) +{ + ptr->CONTROL_STATUS |= LINV2_CONTROL_STATUS_SLEEP_MASK; +} + +/** + * @brief lin slave stop + * + * @param ptr lin base address + */ +static inline void lin_slave_stop(LINV2_Type *ptr) +{ + ptr->CONTROL_STATUS = ((ptr->CONTROL_STATUS) & ~LINV2_CONTROL_STATUS_SLEEP_MASK) | LINV2_CONTROL_STATUS_STOP_MASK; +} + +/** + * @brief lin slave ack + * + * @param ptr lin base address + */ +static inline void lin_slave_ack(LINV2_Type *ptr) +{ + ptr->CONTROL_STATUS = ((ptr->CONTROL_STATUS) & ~LINV2_CONTROL_STATUS_SLEEP_MASK) | LINV2_CONTROL_STATUS_DATA_ACK_MASK; +} + +/** + * @brief lin slave set bus inactivity time + * + * @param ptr lin base address + * @param time lin_bus_inactivity_time_t + */ +static inline void lin_slave_set_bus_inactivity_time(LINV2_Type *ptr, lin_bus_inactivity_time_t time) +{ + ptr->TIMING_CONTROL = (ptr->TIMING_CONTROL & (~LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_MASK)) + | LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_SET(time); +} + +/** + * @brief lin slave set wakeup repeat time + * + * @param ptr lin base address + * @param time lin_wakeup_repeat_time_t + */ +static inline void lin_slave_set_wakeup_repeat_time(LINV2_Type *ptr, lin_wakeup_repeat_time_t time) +{ + ptr->TIMING_CONTROL = (ptr->TIMING_CONTROL & (~LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_MASK)) + | LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_SET(time); +} + +/** + * @brief lin set mode + * + * @param ptr lin base address + * @param master true for master mode, false for slave mode + */ +static inline void lin_set_mode(LINV2_Type *ptr, bool master) +{ + if (master) { + ptr->TIMING_CONTROL |= LINV2_TIMING_CONTROL_MASTER_MODE_MASK; + } else { + ptr->TIMING_CONTROL &= ~LINV2_TIMING_CONTROL_MASTER_MODE_MASK; + } +} + +/** + * @brief lin set checksum mode + * + * @param ptr lin base address + * @param enhance_checksum true for enhance checksum mode, false for normal checksum mode + */ +static inline void lin_set_checksum_mode(LINV2_Type *ptr, bool enhance_checksum) +{ + if (enhance_checksum) { + ptr->DATA_LEN_ID |= LINV2_DATA_LEN_ID_ENH_CHECK_MASK; + } else { + ptr->DATA_LEN_ID &= ~LINV2_DATA_LEN_ID_ENH_CHECK_MASK; + } +} + +/** + * @brief lin get data value in byte + * + * @param ptr lin base address + * @param index byte index + * @return uint8_t byte value + */ +static inline uint8_t lin_get_data_byte(LINV2_Type *ptr, uint8_t index) +{ + return ptr->DATA_BYTE[index]; +} + +/** + * @brief lin write data value in byte + * + * @param ptr lin base address + * @param index byte index + * @param data byte value + */ +static inline void lin_write_data_byte(LINV2_Type *ptr, uint8_t index, uint8_t data) +{ + ptr->DATA_BYTE[index] = data; +} + +/** + * @brief lin get ID + * + * @param ptr lin base address + * @return uint8_t ID value + */ +static inline uint8_t lin_get_id(LINV2_Type *ptr) +{ + return (uint8_t)LINV2_DATA_LEN_ID_ID_GET(ptr->DATA_LEN_ID); +} + +/** + * @brief lin get checksum value + * + * @param ptr lin base address + * @return uint8_t checksum value + */ +static inline uint8_t lin_get_checksum(LINV2_Type *ptr) +{ + return (uint8_t)LINV2_DATA_LEN_ID_CHECKSUM_GET(ptr->DATA_LEN_ID); +} + +/** + * @brief lin active status + * + * @param ptr lin base address + * @return bool true for active, false for inactive + */ +static inline uint8_t lin_is_active(LINV2_Type *ptr) +{ + return ((ptr->CONTROL_STATUS & LINV2_CONTROL_STATUS_LIN_ACTIVE_MASK) == LINV2_CONTROL_STATUS_LIN_ACTIVE_MASK) ? true : false; +} + +/** + * @brief lin complete status + * + * @param ptr lin base address + * @return bool true for complete, false for incomplete + */ +static inline uint8_t lin_is_complete(LINV2_Type *ptr) +{ + return ((ptr->CONTROL_STATUS & LINV2_CONTROL_STATUS_COMPLETE_MASK) == LINV2_CONTROL_STATUS_COMPLETE_MASK) ? true : false; +} + +/** + * @brief lin configure timing on master mode + * + * @param ptr lin base address + * @param timing lin_timing_t + * @return hpm_stat_t + */ +hpm_stat_t lin_master_configure_timing(LINV2_Type *ptr, lin_timing_t *timing); + +/** + * @brief lin config timing on slave mode + * + * @param ptr lin base address + * @param src_freq_in_hz source frequency + * @return hpm_stat_t + */ +hpm_stat_t lin_slave_configure_timing(LINV2_Type *ptr, uint32_t src_freq_in_hz); + +/** + * @brief lin transfer on master mode + * + * @param ptr lin base address + * @param config lin_trans_config_t + */ +void lin_master_transfer(LINV2_Type *ptr, lin_trans_config_t *config); + +/** + * @brief lin transfer on slave mode + * + * @note call this function after lin generate data request interrupt + * + * @param ptr lin base address + * @param config lin_trans_config_t + */ +void lin_slave_transfer(LINV2_Type *ptr, lin_trans_config_t *config); + +/** + * @brief get data length + * + * @note data length is determined by DATA_LEN register and ID + * + * @param ptr lin base address + * @return uint8_t data length + */ +uint8_t lin_get_data_length(LINV2_Type *ptr); + +/** + * @brief lin send data on master mode + * + * @param ptr lin base address + * @param config lin_trans_config_t + * @return status_timeout + * @return status_success + */ +hpm_stat_t lin_master_sent(LINV2_Type *ptr, lin_trans_config_t *config); + +/** + * @brief lin receive data on master mode + * + * @param ptr lin base address + * @param config lin_trans_config_t + * @return status_timeout + * @return status_success + */ +hpm_stat_t lin_master_receive(LINV2_Type *ptr, lin_trans_config_t *config); + +/** + * @brief lin send data on slave mode + * + * @param ptr lin base address + * @param config lin_trans_config_t + * @return status_timeout + * @return status_success + */ +hpm_stat_t lin_slave_sent(LINV2_Type *ptr, lin_trans_config_t *config); + +/** + * @brief lin receive data on slave mode + * + * @param ptr lin base address + * @param config lin_trans_config_t + * @return status_timeout + * @return status_success + */ +hpm_stat_t lin_slave_receive(LINV2_Type *ptr, lin_trans_config_t *config); + +/** + * @brief lin slave dma transfer + * + * @param ptr lin base address + * @param config lin_trans_config_t + */ +void lin_slave_dma_transfer(LINV2_Type *ptr, lin_trans_config_t *config); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* HPM_LINV2_DRV_H */ + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lvb_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lvb_drv.h new file mode 100644 index 00000000000..efc5f7b33e9 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lvb_drv.h @@ -0,0 +1,289 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_LVB_DRV_H +#define HPM_LVB_DRV_H + +/** + * @brief LVB APIs + * @defgroup lvb_interface LVB driver APIs + * @ingroup lvb_interfaces + * @{ + */ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_lvb_regs.h" + +/** + * @brief LVB DI vsync polarity + */ +typedef enum lvb_di_vsync_polarity { + lvb_di_vsync_polarity_active_high = 0, + lvb_di_vsync_polarity_active_low +} lvb_di_vsync_polarity_t; + +/** + * @brief Shift the LVDS TX PHY clock in relation to the data + */ +typedef enum lvb_txclk_shift { + lvb_txclk_shift_1100011 = 0, + lvb_txclk_shift_1110001, + lvb_txclk_shift_1111000, + lvb_txclk_shift_1000111, + lvb_txclk_shift_0001111, + lvb_txclk_shift_0011110, + lvb_txclk_shift_0111100, +} lvb_txclk_shift_t; + +/** + * @brief LVB config + */ +typedef struct lvb_config { + bool split_ch_is_reverse; /*!< Just for split mode, reverse two channel data */ + bool split_ch_data_is_unaligned; /*!< Just for split mode, two channel pixel data are aligned */ + bool split_hswhbp_width_is_even; /*!< Just for split mode, the sum of HSW and HBP width is even */ + bool split_mode_en; /*!< Note: when using split mode, ch0/1 should be enabled, and should select same DI */ + lvb_di_vsync_polarity_t di1_vsync_polarity; /*!< lvb di1 vsync polarity */ + lvb_di_vsync_polarity_t di0_vsync_polarity; /*!< lvb di0 vsync polarity */ + lvb_txclk_shift_t txclk_shift; /*!< Shift the LVDS TX PHY clock in relation to the data */ +} lvb_config_t; + +/** + * @brief LVB channel pixel data mapping + */ +typedef enum lvb_ch_mapping { + lvb_ch_mapping_vesa = 0, + lvb_ch_mapping_jeida, +} lvb_ch_mapping_t; + +/** + * @brief LVB channel pixel data source + */ +typedef enum lvb_ch_data_source { + lvb_ch_data_source_di0 = 0, + lvb_ch_data_source_di1, +} lv_ch_data_source_t; + +/** + * @brief LVB channel number + */ +typedef enum lvb_ch_num { + lvb_ch_num_0 = 0, + lvb_ch_num_1 = 1 +} lvb_ch_num_t; + +/** + * @brief LVB channel config + */ +typedef struct lvb_ch_config { + lvb_ch_mapping_t map; + lv_ch_data_source_t data_src; +} lvb_ch_config_t; + +typedef enum lvb_lvds_lane_phase_sel { + lvb_lvds_lane_phase_sel_0_ui = 0, + lvb_lvds_lane_phase_sel_1_16_ui, + lvb_lvds_lane_phase_sel_2_16_ui, + lvb_lvds_lane_phase_sel_3_16_ui, + lvb_lvds_lane_phase_sel_4_16_ui, + lvb_lvds_lane_phase_sel_5_16_ui, + lvb_lvds_lane_phase_sel_6_16_ui, + lvb_lvds_lane_phase_sel_7_16_ui, + lvb_lvds_lane_phase_sel_8_16_ui, + lvb_lvds_lane_phase_sel_9_16_ui, + lvb_lvds_lane_phase_sel_10_16_ui, + lvb_lvds_lane_phase_sel_11_16_ui, + lvb_lvds_lane_phase_sel_12_16_ui, + lvb_lvds_lane_phase_sel_13_16_ui, + lvb_lvds_lane_phase_sel_14_16_ui, + lvb_lvds_lane_phase_sel_15_16_ui, +} lvb_lvds_lane_phase_sel_t; + +typedef enum lvb_lvds_lane_amp { + lvb_lvds_lane_amp_50_mv = 0, + lvb_lvds_lane_amp_100_mv, + lvb_lvds_lane_amp_150_mv, + lvb_lvds_lane_amp_200_mv, + lvb_lvds_lane_amp_250_mv, + lvb_lvds_lane_amp_300_mv, + lvb_lvds_lane_amp_350_mv, + lvb_lvds_lane_amp_400_mv, + lvb_lvds_lane_amp_450_mv, + lvb_lvds_lane_amp_500_mv, + lvb_lvds_lane_amp_550_mv, + lvb_lvds_lane_amp_600_mv +} lvb_lvds_lane_amp_t; + +typedef enum lvb_lvds_lane_vcom { + lvb_lvds_lane_vcom_0_7_v = 0, + lvb_lvds_lane_vcom_0_8_v, + lvb_lvds_lane_vcom_0_9_v, + lvb_lvds_lane_vcom_1_0_v, + lvb_lvds_lane_vcom_1_1_v, + lvb_lvds_lane_vcom_1_2_v, + lvb_lvds_lane_vcom_1_3_v, + lvb_lvds_lane_vcom_1_4_v, + lvb_lvds_lane_vcom_1_5_v, +} lvb_lvds_lane_vcom_t; + +typedef struct lvb_lvds_phy_lane_config { + bool rterm_enable; + bool tx_idle; + lvb_lvds_lane_phase_sel_t phase_sel; + lvb_lvds_lane_amp_t amp; + lvb_lvds_lane_vcom_t vcom; + bool fvco_div4; +} lvb_lvds_phy_lane_config_t; + +typedef enum lvb_lvds_lane_idx { + lvb_lvds_lane_idx_lvds0_tx0 = LVB_TX_PHY_LVDS0_TX0, + lvb_lvds_lane_idx_lvds0_tx1 = LVB_TX_PHY_LVDS0_TX1, + lvb_lvds_lane_idx_lvds0_tx2 = LVB_TX_PHY_LVDS0_TX2, + lvb_lvds_lane_idx_lvds0_tx3 = LVB_TX_PHY_LVDS0_TX3, + lvb_lvds_lane_idx_lvds0_txck = LVB_TX_PHY_LVDS0_TXCK, + lvb_lvds_lane_idx_lvds1_tx0 = LVB_TX_PHY_LVDS1_TX0, + lvb_lvds_lane_idx_lvds1_tx1 = LVB_TX_PHY_LVDS1_TX1, + lvb_lvds_lane_idx_lvds1_tx2 = LVB_TX_PHY_LVDS1_TX2, + lvb_lvds_lane_idx_lvds1_tx3 = LVB_TX_PHY_LVDS1_TX3, + lvb_lvds_lane_idx_lvds1_txck = LVB_TX_PHY_LVDS1_TXCK, +} lvb_lvds_lane_idx_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief get LVB of default config + * + * @param[out] cfg config of LVB + */ +void lvb_get_default_config(lvb_config_t *cfg); + +/** + * @brief LVB init + * + * @param[in] ptr LVB base address + * @param[in] cfg config of LVB + */ +void lvb_init(LVB_Type *ptr, lvb_config_t *cfg); + +/** + * @brief get LVB channel of default config + * + * @param[out] ch_cfg config of LVB + */ +void lvb_get_ch_default_config(lvb_ch_config_t *ch_cfg); + +/** + * @brief LVB channel config + * + * @param[in] ptr LVB base address + * @param[in] ch_num LVB channel number + * @param[in] ch_cfg config of LVB channel + */ +void lvb_ch_config(LVB_Type *ptr, lvb_ch_num_t ch_num, lvb_ch_config_t *ch_cfg); + +/** + * @brief LVB channel enable + * + * @param[in] ptr LVB base address + * @param[in] ch_num LVB channel number + */ +void lvb_ch_enable(LVB_Type *ptr, lvb_ch_num_t ch_num); + +/** + * @brief LVB channel disable + * + * @param[in] ptr LVB base address + * @param[in] ch_num LVB channel number + */ +void lvb_ch_disable(LVB_Type *ptr, lvb_ch_num_t ch_num); + +/** + * @brief check LVB phy0 is lock + * + * @param[in] ptr LVB base address + */ +static inline bool lvb_lvds_phy0_pll_is_lock(LVB_Type *ptr) +{ + return !!LVB_PHY_STAT_LVDS0_TX_PHY_PLL_LOCK_GET(ptr->PHY_STAT); +} + +/** + * @brief check LVB phy1 is lock + * + * @param[in] ptr LVB base address + */ +static inline bool lvb_lvds_phy1_pll_is_lock(LVB_Type *ptr) +{ + return !!LVB_PHY_STAT_LVDS1_TX_PHY_PLL_LOCK_GET(ptr->PHY_STAT); +} + +/** + * @brief check LVB phy0 and phy1 is lock + * + * @param[in] ptr LVB base address + */ +static inline bool lvb_lvds_phy_split_pll_is_lock(LVB_Type *ptr) +{ + return !!LVB_PHY_STAT_LVDS0_TX_PHY_PLL_LOCK_GET(ptr->PHY_STAT) && + !!LVB_PHY_STAT_LVDS1_TX_PHY_PLL_LOCK_GET(ptr->PHY_STAT); +} + +/** + * @brief lvb lvds lane get default config + * + * @param[out] cfg lvds lane config @ref lvb_lvds_phy_lane_config_t + */ +void lvb_lvds_phy_lane_get_default_config(lvb_lvds_phy_lane_config_t *cfg); + +/** + * @brief lvb lvds lane init and config + * + * @param[in] ptr LVB base address + * @param[in] tx_index lvds phy lane index @ref lvb_lvds_lane_idx_t + * @param[in] cfg lvds lane config @ref lvb_lvds_phy_lane_config_t + */ +void lvb_lvds_phy_lane_init(LVB_Type *ptr, lvb_lvds_lane_idx_t tx_index, lvb_lvds_phy_lane_config_t *cfg); + +/** + * @brief power on LVB phy0 + * + * @param[in] ptr LVB base address + */ +void lvb_lvds_phy0_poweron(LVB_Type *ptr); + +/** + * @brief power on LVB phy1 + * + * @param[in] ptr LVB base address + */ +void lvb_lvds_phy1_poweron(LVB_Type *ptr); + +/** + * @brief power down LVB phy0 + * + * @param[in] ptr LVB base address + */ +void lvb_lvds_phy0_powerdown(LVB_Type *ptr); + +/** + * @brief power down LVB phy0 + * + * @param[in] ptr LVB base address + */ +void lvb_lvds_phy1_powerdown(LVB_Type *ptr); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ +#endif /* HPM_LVB_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mcan_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mcan_drv.h index 70b24f8dff4..766fb73a710 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mcan_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mcan_drv.h @@ -38,6 +38,7 @@ enum { status_mcan_tx_evt_fifo_empty, status_mcan_timestamp_not_exist, status_mcan_ram_out_of_range, + status_mcan_timeout, }; /** @@ -78,12 +79,12 @@ enum { #define MCAN_INT_RXFIFO0_MSG_LOST MCAN_IR_RF0L_MASK /*!< RX FIFO0 Message Lost */ #define MCAN_INT_RXFIFO0_FULL MCAN_IR_RF0F_MASK /*!< RX FIFO0 Full */ #define MCAN_INT_RXFIFO0_WMK_REACHED MCAN_IR_RF0W_MASK /*!< RX FIFO0 Watermark Reached */ -#define MCAN_INT_RXFIFI0_NEW_MSG MCAN_IR_RF0N_MASK /*!< RX FIFO0 New Message */ +#define MCAN_INT_RXFIFO0_NEW_MSG MCAN_IR_RF0N_MASK /*!< RX FIFO0 New Message */ /** * @brief MCAN Receive Event Flags */ -#define MCAN_EVENT_RECEIVE (MCAN_INT_RXFIFI0_NEW_MSG | MCAN_INT_RXFIFO1_NEW_MSG | MCAN_INT_MSG_STORE_TO_RXBUF) +#define MCAN_EVENT_RECEIVE (MCAN_INT_RXFIFO0_NEW_MSG | MCAN_INT_RXFIFO1_NEW_MSG | MCAN_INT_MSG_STORE_TO_RXBUF) /** * @brief MCAN Transmit Event Flags @@ -93,7 +94,8 @@ enum { * @brief MCAN Error Event Flags */ #define MCAN_EVENT_ERROR (MCAN_INT_BUS_OFF_STATUS | MCAN_INT_WARNING_STATUS \ - | MCAN_INT_ERROR_PASSIVE | MCAN_INT_BIT_ERROR_UNCORRECTED) + | MCAN_INT_ERROR_PASSIVE | MCAN_INT_BIT_ERROR_UNCORRECTED \ + | MCAN_INT_PROTOCOL_ERR_IN_DATA_PHASE | MCAN_INT_PROTOCOL_ERR_IN_ARB_PHASE) /** * @brief Maximum Transmission Retry Count @@ -104,6 +106,30 @@ enum { */ #define MCAN_RX_RETRY_COUNT_MAX (80000000UL) +/** + * @brief MCAN Last Error Code + */ +typedef enum mcan_last_error_code { + mcan_last_error_code_no_error = 0, /*!< No error happened */ + mcan_last_error_code_stuff_error, /*!< Stuff Error */ + mcan_last_error_code_format_error, /*!< Format Error */ + mcan_last_error_code_ack_error, /*!< Acknowledge Error */ + mcan_last_error_code_bit1_error, /*!< Sent logic 1 but monitored value is logic 0 */ + mcan_last_error_code_bit0_error, /*!< Sent logic 0 but monitored value is logic 1 */ + mcan_last_error_code_crc_error, /*!< CRC checksum for received message is wrong */ + mcan_last_error_code_no_change, /*!< Error code was not changed */ +} mcan_last_err_code_t; + +/** + * @brief MCAN Communication State + */ +typedef enum mcan_activity_enum { + mcan_activity_sync = 0, /*!< Node is synchronizing on CAN communication */ + mcan_activity_idle, /*!< Node is neither receiver nor transmitter */ + mcan_activity_receiver, /*!< Node is operating as receiver */ + mcan_activity_transmitter, /*!< Node is operating as transmitter */ +} mcan_activity_state_t; + /*********************************************************************************************************************** * @brief Default CAN RAM definitions **********************************************************************************************************************/ @@ -385,7 +411,7 @@ typedef union { /** * @brief MCAN RAM Flexible Configuration * - * @Note This Configration provides the full MCAN RAM configuration, this configuration is recommended only for + * @note This Configuration provides the full MCAN RAM configuration, this configuration is recommended only for * experienced developers who is skilled at the MCAN IP */ typedef struct mcan_ram_flexible_config_struct { @@ -413,7 +439,7 @@ typedef struct mcan_ram_flexible_config_struct { /** * @brief MCAN RAM configuration * - * @Note: This Configuration focuses on the minimum required information for MCAN RAM configuration + * @note: This Configuration focuses on the minimum required information for MCAN RAM configuration * The Start address of each BUF/FIFO will be automatically calculated by the MCAN Driver API * This RAM configuration is recommended for the most developers */ @@ -513,7 +539,7 @@ typedef struct mcan_std_id_filter_elem_struct { }; /* This definition takes effect if the filter configuration is "store into RX Buffer or as debug message" * - * In this definition, only the extact ID matching mode is activated + * In this definition, only the exact ID matching mode is activated */ struct { uint32_t match_id; /*!< Matching ID */ @@ -536,7 +562,7 @@ typedef struct mcan_filter_elem_list_struct { /** * @brief MCAN Configuration for all filters * - * @Note The MCAN RAM related settings are excluded + * @note The MCAN RAM related settings are excluded */ typedef struct mcan_all_filters_config_struct { mcan_global_filter_config_t global_filter_config; /*!< Global Filter configuration */ @@ -578,7 +604,8 @@ typedef struct mcan_tsu_config_struct { uint16_t prescaler; /*!< Prescaler for MCAN clock, Clock source: AHB clock */ bool capture_on_sof; /*!< Capture On SOF, true - Capture on SOF, false - Capture on EOF */ bool use_ext_timebase; /*!< Use External Timebase */ - uint16_t ext_timebase_src; /*!< External Timebase source, see the hpm_mcan_soc.h for more details */ + uint8_t ext_timebase_src; /*!< External Timebase source, see the hpm_mcan_soc.h for more details */ + uint8_t tbsel_option; /*!< Timebase selection option, see the hpm_mcan_soc.h for more details */ bool enable_tsu; /*!< Enable Timestamp Unit */ bool enable_64bit_timestamp; /*!< Enable 64bit Timestamp */ } mcan_tsu_config_t; @@ -600,12 +627,31 @@ typedef struct mcan_internal_timestamp_config_struct { uint8_t timestamp_selection; /*!< Timestamp Select */ } mcan_internal_timestamp_config_t; +/** + * @brief MCAN Timeout Selection Options + */ +typedef enum mcan_timeout_sel_enum { + mcan_timeout_continuous_operation = 0, /*!< Continuously count down timeout after writing to TOCV register */ + mcan_timeout_triggered_by_tx_evt_fifo = 1, /*!< Count down if the TX EVT FIFO is not empty */ + mcan_timeout_triggered_by_rx_fifo0 = 2, /*!< Count down if the RX FIFO0 is not empty */ + mcan_timeout_triggered_by_rx_fifo1 = 3, /*!< Count down if the RX FIFO1 is not empty */ +} mcan_timeout_sel_t; + +/** + * @brief MCAN Timeout configuration structure + */ +typedef struct mcan_timeout_config_struct { + bool enable_timeout_counter; /*!< Enable Timeout Counter */ + mcan_timeout_sel_t timeout_sel; /*!< Timeout source selection */ + uint16_t timeout_period; /*!< Timeout period */ +} mcan_timeout_config_t; + /** * @brief MCAN Configuration Structure */ typedef struct mcan_config_struct { union { - /* This struct takes effect if use_lowlevl_timing_setting = false */ + /* This struct takes effect if "use_lowlevel_timing_setting = false" */ struct { uint32_t baudrate; /*!< CAN 2.0 baudrate/CAN-FD Nominal Baudrate, in terms of bps */ uint32_t baudrate_fd; /*!< CANFD data baudrate, in terms of bps */ @@ -614,7 +660,7 @@ typedef struct mcan_config_struct { uint16_t canfd_samplepoint_min; /*!< Value = Minimum CANFD sample point * 10 */ uint16_t canfd_samplepoint_max; /*!< Value = Maximum CANFD sample point * 10 */ }; - /* This struct takes effect if use_lowlevl_timing_setting = true */ + /* This struct takes effect if "use_lowlevel_timing_setting = true" */ struct { mcan_bit_timing_param_t can_timing; /*!< CAN2.0/CANFD nominal timing setting */ mcan_bit_timing_param_t canfd_timing; /*!< CANFD data timing setting */ @@ -630,10 +676,19 @@ typedef struct mcan_config_struct { bool use_timestamping_unit; /*!< Use external Timestamp Unit */ bool enable_canfd; /*!< Enable CANFD mode */ bool enable_tdc; /*!< Enable transmitter delay compensation */ + bool enable_restricted_operation_mode; /*!< Enable Restricted Operation Mode: Receive only */ + bool disable_auto_retransmission; /*!< Disable auto retransmission */ + uint8_t padding[2]; mcan_internal_timestamp_config_t timestamp_cfg; /*!< Internal Timestamp Configuration */ mcan_tsu_config_t tsu_config; /*!< TSU configuration */ mcan_ram_config_t ram_config; /*!< MCAN RAM configuration */ mcan_all_filters_config_t all_filters_config; /*!< All Filter configuration */ + + mcan_timeout_config_t timeout_cfg; /*!< Timeout configuration */ + + uint32_t interrupt_mask; /*!< Interrupt Enable mask */ + uint32_t txbuf_trans_interrupt_mask; /*!< Tx Buffer Transmission Interrupt Enable mask */ + uint32_t txbuf_cancel_finish_interrupt_mask; /*!< TX Buffer Cancellation Finished Interrupt Enable Mask */ } mcan_config_t; /** @@ -663,6 +718,22 @@ typedef struct mcan_error_count_struct { uint8_t can_error_logging_count; /*!< CAN Error Logging count */ } mcan_error_count_t; +/** + * @brief MCAN Protocol Status + */ +typedef struct mcan_protocol_status { + uint8_t tdc_val; /*!< Transmitter Delay Compensation Value */ + mcan_activity_state_t activity; /*!< Current communication state */ + mcan_last_err_code_t last_error_code; /*!< Last Error code */ + bool protocol_exception_evt_occurred; /*!< Protocol Exception Event occurred */ + bool canfd_msg_received; /*!< CANFD message was received */ + bool brs_flag_set_in_last_rcv_canfd_msg; /*!< Bitrate Switch bit is set in last received CANFD message */ + bool esi_flag_set_in_last_rcv_canfd_msg; /*!< Error State Indicator bit is set in last received CANFD message */ + bool in_bus_off_state; /*!< Node is in bus-off state */ + bool in_warning_state; /*!< Node is in warning state */ + bool in_error_passive_state; /*!< Node is in error passive state */ +} mcan_protocol_status_t; + /** * @brief MCAN Transmitter Delay Compensation Configuration */ @@ -839,48 +910,62 @@ static inline void mcan_disable_auto_retransmission(MCAN_Type *ptr) } /** - * @brief Disable Bus monitoring Mode + * @brief Enable Bus monitoring Mode * @param [in] ptr MCAN base */ -static inline void mcan_disable_bus_monitoring_mode(MCAN_Type *ptr) +static inline void mcan_enable_bus_monitoring_mode(MCAN_Type *ptr) { - ptr->CCCR &= ~MCAN_CCCR_MON_MASK; + ptr->CCCR |= MCAN_CCCR_MON_MASK; } /** - * @brief Enable Clock Stop Request + * @brief Stop MCAN clock * @param [in] ptr MCAN base */ -static inline void mcan_enable_clock_stop_request(MCAN_Type *ptr) +static inline void mcan_stop_clock(MCAN_Type *ptr) { ptr->CCCR |= MCAN_CCCR_CSR_MASK; } /** - * @brief Disable Clock Stop Request + * @brief Enable MCAN clock * @param [in] ptr MCAN base */ -static inline void mcan_disable_clock_stop_request(MCAN_Type *ptr) +static inline void mcan_enable_clock(MCAN_Type *ptr) { ptr->CCCR &= ~MCAN_CCCR_CSR_MASK; } +static inline bool mcan_is_clock_enabled(MCAN_Type *ptr) +{ + return ((ptr->CCCR & MCAN_CCCR_CSR_MASK) == 0UL); +} + +/** + * @brief Disable Bus monitoring Mode + * @param [in] ptr MCAN base + */ +static inline void mcan_disable_bus_monitoring_mode(MCAN_Type *ptr) +{ + ptr->CCCR &= ~MCAN_CCCR_MON_MASK; +} + /** - * @brief Enable Clock Stop Acknowledge + * @brief Check whether CAN clock is stopped or not * @param [in] ptr MCAN base */ -static inline void mcan_enable_clock_stop_acknowledge(MCAN_Type *ptr) +static inline bool mcan_is_clock_stopped(MCAN_Type *ptr) { - ptr->CCCR |= MCAN_CCCR_CSA_MASK; + return ((ptr->CCCR & MCAN_CCCR_CSA_MASK) != 0U); } /** - * @brief Disable Clock Stop Acknowledge + * @brief Enable Restricted Operation Mode * @param [in] ptr MCAN base */ -static inline void mcan_disable_clock_stop_acknowledge(MCAN_Type *ptr) +static inline void mcan_enable_restricted_operation_mode(MCAN_Type *ptr) { - ptr->CCCR &= ~MCAN_CCCR_CSA_MASK; + ptr->CCCR |= MCAN_CCCR_ASM_MASK; } /** @@ -892,6 +977,24 @@ static inline void mcan_disable_restricted_operation_mode(MCAN_Type *ptr) ptr->CCCR &= ~MCAN_CCCR_ASM_MASK; } +/** + * @brief Enable Write Access to Protected Configuration Registers + * @param [in] ptr MCAN base + */ +static inline void mcan_enable_write_to_prot_config_registers(MCAN_Type *ptr) +{ + ptr->CCCR |= MCAN_CCCR_CCE_MASK; +} + +/** + * @brief Disalbe Write Access to Protected Configuration Registers + * @param [in] ptr MCAN base + */ +static inline void mcan_disable_write_to_prot_config_registers(MCAN_Type *ptr) +{ + ptr->CCCR &= ~MCAN_CCCR_CCE_MASK; +} + /** * @brief Get Timestamp Counter Value * @param [in] ptr MCAN base @@ -902,6 +1005,24 @@ static inline uint16_t mcan_get_timestamp_counter_value(MCAN_Type *ptr) return ptr->TSCV; } +/** + * @brief Switch MCAN to Initialization mode + * @param [in] ptr MCAN base + */ +static inline void mcan_enter_init_mode(MCAN_Type *ptr) +{ + ptr->CCCR |= MCAN_CCCR_INIT_MASK; +} + +/** + * @brief Switch MCAN to Normal mode + * @param [in] ptr MCAN base + */ +static inline void mcan_enter_normal_mode(MCAN_Type *ptr) +{ + ptr->CCCR &= ~MCAN_CCCR_INIT_MASK; +} + /** * @brief Get Timeout value * @param [in] ptr MCAN base @@ -912,6 +1033,16 @@ static inline uint16_t mcan_get_timeout_counter_value(MCAN_Type *ptr) return ptr->TOCV; } +/** + * @brief Reset Timeout counter value + * + * @param [in] ptr MCAN base + */ +static inline void mcan_reset_timeout_counter_value(MCAN_Type *ptr) +{ + *((volatile uint32_t *) &ptr->TOCV) = 0; +} + /** * @brief Get Error Counter Information * @param [in] ptr MCAN base @@ -989,6 +1120,7 @@ static inline bool mcan_is_in_busoff_state(MCAN_Type *ptr) /** * @brief Get the Last Data Phase Error * @param [in] ptr MCAN base + * @deprecated This API will be removed in later SDK release * @return The last Data Phase Error */ static inline uint8_t mcan_get_data_phase_last_error_code(MCAN_Type *ptr) @@ -1080,6 +1212,7 @@ static inline void mcan_enable_interrupts(MCAN_Type *ptr, uint32_t mask) /** * @brief Enable TXBUF Interrupt + * @deprecated This API is deprecated, will be removed in later SDK release * @param [in] ptr MCAN base * @param [in] mask Interrupt mask */ @@ -1090,6 +1223,7 @@ static inline void mcan_enable_txbuf_interrupt(MCAN_Type *ptr, uint32_t mask) /** * @brief Disable TXBUF Interrupt + * @deprecated This API is deprecated, will be removed in later SDK release * @param [in] ptr MCAN base * @param [in] mask Interrupt mask */ @@ -1262,6 +1396,14 @@ static inline bool mcan_is_interrupt_flag_set(MCAN_Type *ptr, uint32_t mask) return ((ptr->IR & mask) != 0U); } +/** + * @brief Check whether the TSU timestamp is available + * + * @param [in] ptr MCAN base + * @param [in] index Timestamp pointer + * @retval true TSU Timestamp is available + * @retval false TSU timestamp is unavailable + */ static inline bool mcan_is_tsu_timestamp_available(MCAN_Type *ptr, uint32_t index) { bool is_available = false; @@ -1308,6 +1450,12 @@ void mcan_get_default_config(MCAN_Type *ptr, mcan_config_t *config); */ uint8_t mcan_get_message_size_from_dlc(uint8_t dlc); +/** + * @brief Get the Data field size from data field size option + * + * @param [in] data_field_size_option Data size option + * @return data field size in bytes + */ uint8_t mcan_get_data_field_size(uint8_t data_field_size_option); /** @@ -1320,16 +1468,21 @@ uint8_t mcan_get_data_field_size(uint8_t data_field_size_option); * - Dedicated TXBUF element count: 16 * - TXFIFO/QQueue element count: 16 * - Data Field Size: 8 + * . * - RXFIFO0 Elements Info: * - Element Count :32 * - Data Field Size: 8 + * . * - RXFIFO1 Elements Info: * - Element Count : 32 * - Data Field Size: 8 + * . * - RXBUF Element Info: * - Element Count: 16 * - Data Field Size : 8 + * . * - TX Event FIFO Element Count: 32 + * . * If the device is configured as CANFD node, the default CAN RAM settings are as below: * - Standard Identifier Filter Elements: 16 * - Extended Identifier Filter Elements: 16 @@ -1338,17 +1491,21 @@ uint8_t mcan_get_data_field_size(uint8_t data_field_size_option); * - Dedicated TXBUF element count: 4 * - TXFIFO/QQueue element count: 4 * - Data Field Size: 64 + * . * - RXFIFO0 Elements Info: * - Element Count : 8 * - Data Field Size: 64 + * . * - RXFIFO1 Elements Info: * - Element Count : 8 * - Data Field Size: 64 + * . * - RXBUF Element Info: * - Element Count: 4 * - Data Field Size : 64 + * . * - TX Event FIFO Element Count: 8 - * + * . * @param [in] ptr MCAN base * @param [out] ram_config CAN RAM Configuration * @param [in] enable_canfd CANFD enable flag @@ -1365,16 +1522,21 @@ void mcan_get_default_ram_flexible_config(MCAN_Type *ptr, mcan_ram_flexible_conf * - Dedicated TXBUF element count: 16 * - TXFIFO/QQueue element count: 16 * - Data Field Size: 8 + * . * - RXFIFO0 Elements Info: * - Element Count :32 * - Data Field Size: 8 + * . * - RXFIFO1 Elements Info: * - Element Count : 32 * - Data Field Size: 8 + * . * - RXBUF Element Info: * - Element Count: 16 * - Data Field Size : 8 + * . * - TX Event FIFO Element Count: 32 + * . * If the device is configured as CANFD node, the default CAN RAM settings are as below: * - Standard Identifier Filter Elements: 16 * - Extended Identifier Filter Elements: 16 @@ -1383,19 +1545,23 @@ void mcan_get_default_ram_flexible_config(MCAN_Type *ptr, mcan_ram_flexible_conf * - Dedicated TXBUF element count: 4 * - TXFIFO/QQueue element count: 4 * - Data Field Size: 64 + * . * - RXFIFO0 Elements Info: * - Element Count : 8 * - Data Field Size: 64 + * . * - RXFIFO1 Elements Info: * - Element Count : 8 * - Data Field Size: 64 + * . * - RXBUF Element Info: * - Element Count: 4 * - Data Field Size : 64 + * . * - TX Event FIFO Element Count: 8 - * + * . * @param [in] ptr MCAN base - * @param [out] ram_config CAN RAM Configuration + * @param [out] simple_config Simple CAN RAM Configuration * @param [in] enable_canfd CANFD enable flag */ void mcan_get_default_ram_config(MCAN_Type *ptr, mcan_ram_config_t *simple_config, bool enable_canfd); @@ -1410,6 +1576,13 @@ void mcan_get_default_ram_config(MCAN_Type *ptr, mcan_ram_config_t *simple_confi */ hpm_stat_t mcan_init(MCAN_Type *ptr, mcan_config_t *config, uint32_t src_clk_freq); +/** + * @brief De-Initialize CAN controller + * + * @param [in] ptr MCAN base + */ +void mcan_deinit(MCAN_Type *ptr); + /** * @brief Configure MCAN RAM will Full RAM configuration * @param [in] ptr MCAN base @@ -1513,9 +1686,20 @@ hpm_stat_t mcan_read_tx_evt_fifo(MCAN_Type *ptr, mcan_tx_event_fifo_elem_t *tx_e hpm_stat_t mcan_transmit_blocking(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame); /** - * @brief Transmit CAN message via TX in blocking way + * @brief Transmit CAN message via TX FIFO in non-blocking way * @param [in] ptr MCAN base * @param [in] tx_frame CAN Transmit Message buffer + * @param [out] fifo_index The index of the element in FIFO assigned to the tx_frame + * + * @return status_success if no errors reported + */ +hpm_stat_t mcan_transmit_via_txfifo_nonblocking(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame, uint32_t *fifo_index); + +/** + * @brief Transmit CAN message via TX in non-blocking way + * @param [in] ptr MCAN base + * @param [in] index Index of TX Buffer + * @param [in] tx_frame CAN Transmit Message buffer * @return status_success if no errors reported */ hpm_stat_t mcan_transmit_via_txbuf_nonblocking(MCAN_Type *ptr, uint32_t index, mcan_tx_frame_t *tx_frame); @@ -1564,6 +1748,26 @@ hpm_stat_t mcan_get_timestamp_from_received_message(MCAN_Type *ptr, const mcan_rx_message_t *rx_msg, mcan_timestamp_value_t *timestamp); +/** + * @brief Parse the Protocol Status register value + * @param [in] psr Protocol Status Register Value + * @param [out] protocol_status Translated Protocol Status + * + * @retval status_invalid_argument if any parameters are invalid + * @retval status_success if no errors happened + */ +hpm_stat_t mcan_parse_protocol_status(uint32_t psr, mcan_protocol_status_t *protocol_status); + +/** + * @brief Get MCAN Protocol Status + * @param [in] ptr MCAN base + * @param [out] protocol_status Translated Protocol status + * + * @retval status_invalid_argument if any parameters are invalid + * @retval status_success if no errors happened + */ +hpm_stat_t mcan_get_protocol_status(MCAN_Type *ptr, mcan_protocol_status_t *protocol_status); + /** * @} * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mipi_csi_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mipi_csi_drv.h new file mode 100644 index 00000000000..e04d7feb0e1 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mipi_csi_drv.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_MIPI_CSI_DRV_H +#define HPM_MIPI_CSI_DRV_H + +/** + * @brief MIPI_CSI APIs + * @defgroup mipi_csi_interface MIPI_CSI driver APIs + * @ingroup mipi_csi_interfaces + * @{ + */ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_mipi_csi_regs.h" + +#define MIPI_CSI_PHY_STOP_MASK_CLK_LANE (0x01u<<16) +#define MIPI_CSI_PHY_STOP_MASK_DATA1_LANE (0x01u<<1) +#define MIPI_CSI_PHY_STOP_MASK_DATA0_LANE (0x01u<<0) + + +typedef enum mipi_csi_data_type { + mipi_csi_data_type_yuv420_8bit = 0x18, + mipi_csi_data_type_yuv422_8bit = 0x1e, + mipi_csi_data_type_rgb565 = 0x22, + mipi_csi_data_type_rgb666 = 0x23, + mipi_csi_data_type_rgb888 = 0x24, +} mipi_csi_data_type_t; + +typedef struct mipi_csi_config { + uint8_t lanes; /* !< max: 2. number of lane*/ + mipi_csi_data_type_t data_type; +} mipi_csi_config_t; + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief get MIPI_CSI default config + * + * @param cfg: MIPI_CSI default config + */ +void mipi_csi_get_defconfig(mipi_csi_config_t *cfg); + +/** + * @brief MIPI_CSI init + * + * @param ptr MIPI_CSI base address + * @param cfg config of MIPI_CSI + */ +void mipi_csi_init(MIPI_CSI_Type *ptr, mipi_csi_config_t *cfg); + +/** + * @brief MIPI_CSI phy interface power on + * + * @param ptr MIPI_DCI base address + */ +void mipi_csi_phy_poweron(MIPI_CSI_Type *ptr); + +/** + * @brief MIPI_CSI phy interface power down + * + * @param ptr MIPI_CSI base address + */ +void mipi_csi_phy_powerdown(MIPI_CSI_Type *ptr); + +/** + * @brief MIPI_CSI check clklane whether on HS state + * + * @param ptr MIPI_DCI base address + * @return: true on HS or false not on HS. + */ +static inline bool mipi_csi_clklane_is_entry_hs(MIPI_CSI_Type *ptr) +{ + return !!(ptr->PHY_RX & MIPI_CSI_PHY_RX_PHY_RXCLKACTIVEHS_MASK); +} + + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ +#endif /* HPM_MIPI_CSI_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mipi_csi_phy_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mipi_csi_phy_drv.h new file mode 100644 index 00000000000..96f1378292b --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mipi_csi_phy_drv.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_MIPI_CSI_PHY_DRV_H +#define HPM_MIPI_CSI_PHY_DRV_H + +/** + * @brief MIPI_CSI_PHY APIs + * @defgroup mipi_csi_phy_interface MIPI_CSI_PHY driver APIs + * @ingroup mipi_csi_phy_interfaces + * @{ + */ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_mipi_csi_phy_regs.h" + + +typedef struct mipi_csi_phy_clane_config { + uint16_t t_term_en_ns; /* !< unit: nanosecond. Time for the Clock Lane receiver to enable the HS line termination, starting from the time point when Dn crosses VIL,MAX */ + uint16_t t_settle_ns; /* !< unit: nanosecond. Time interval during which the HS receiver should ignore any Clock Lane HS transitions, starting from the beginning of TCLK-PREPARE */ +} mipi_csi_phy_clane_config_t; + +typedef struct mipi_csi_phy_dlane_config { + uint16_t t_term_en_ns; /* !< unit: nanosecond. Time for the Data Lane receiver to enable the HS line termination, starting from the time point when Dn crosses VIL,MAX */ + uint16_t t_settle_ns; /* !< unit: nanosecond. Time interval during which the HS receiver shall ignore any Data Lane HS transitions, starting from the beginning of THS-PREPARE */ +} mipi_csi_phy_dlane_config_t; + +typedef struct mipi_csi_phy_config { + mipi_csi_phy_clane_config_t clane_cfg; /*!< clk lane config */ + mipi_csi_phy_dlane_config_t dlane_cfg; /*!< data lane config */ +} mipi_csi_phy_config_t; + + + +/** + * @brief get MIPI CSI PHY of default config + * + * @param[out] cfg config of MIPI CSI PHY + */ +void mipi_csi_phy_default_config(mipi_csi_phy_config_t *cfg); + +/** + * @brief MIPI_CSI_PHY init + * + * @param ptr MIPI_CSI_PHY base address + * @param cfg config of MIPI_CSI_PHY + */ +void mipi_csi_phy_init(MIPI_CSI_PHY_Type *ptr, mipi_csi_phy_config_t *cfg); + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ +#endif /* HPM_MIPI_CSI_PHY_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mipi_dsi_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mipi_dsi_drv.h new file mode 100644 index 00000000000..6060aa45718 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mipi_dsi_drv.h @@ -0,0 +1,307 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_MIPI_DSI_DRV_H +#define HPM_MIPI_DSI_DRV_H + +/** + * @brief MIPI_DSI APIs + * @defgroup mipi_dsi_interface MIPI_DSI driver APIs + * @ingroup mipi_dsi_interfaces + * @{ + */ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_mipi_dsi_regs.h" + + +/* MIPI DSI Processor-to-Peripheral transaction types */ +typedef enum mipi_dsi_tx_cmd { + MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22, + MIPI_DSI_TURN_ON_PERIPHERAL = 0x32, + MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03, + MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13, + MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23, + MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04, + MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14, + MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24, + MIPI_DSI_DCS_SHORT_WRITE = 0x05, + MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15, + MIPI_DSI_DCS_READ = 0x06, + MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37, + MIPI_DSI_GENERIC_LONG_WRITE = 0x29, + MIPI_DSI_DCS_LONG_WRITE = 0x39 +} mipi_dsi_tx_cmd_t; + +/* MIPI DCS commands */ +typedef enum mipi_dcs_cmd { + MIPI_DCS_NOP = 0x00, + MIPI_DCS_SOFT_RESET = 0x01, + MIPI_DCS_GET_DISPLAY_ID = 0x04, + MIPI_DCS_GET_RED_CHANNEL = 0x06, + MIPI_DCS_GET_GREEN_CHANNEL = 0x07, + MIPI_DCS_GET_BLUE_CHANNEL = 0x08, + MIPI_DCS_GET_DISPLAY_STATUS = 0x09, + MIPI_DCS_GET_POWER_MODE = 0x0A, + MIPI_DCS_GET_ADDRESS_MODE = 0x0B, + MIPI_DCS_GET_PIXEL_FORMAT = 0x0C, + MIPI_DCS_GET_DISPLAY_MODE = 0x0D, + MIPI_DCS_GET_SIGNAL_MODE = 0x0E, + MIPI_DCS_GET_DIAGNOSTIC_RESULT = 0x0F, + MIPI_DCS_ENTER_SLEEP_MODE = 0x10, + MIPI_DCS_EXIT_SLEEP_MODE = 0x11, + MIPI_DCS_ENTER_PARTIAL_MODE = 0x12, + MIPI_DCS_ENTER_NORMAL_MODE = 0x13, + MIPI_DCS_EXIT_INVERT_MODE = 0x20, + MIPI_DCS_ENTER_INVERT_MODE = 0x21, + MIPI_DCS_SET_GAMMA_CURVE = 0x26, + MIPI_DCS_SET_DISPLAY_OFF = 0x28, + MIPI_DCS_SET_DISPLAY_ON = 0x29, + MIPI_DCS_SET_COLUMN_ADDRESS = 0x2A, + MIPI_DCS_SET_PAGE_ADDRESS = 0x2B, + MIPI_DCS_WRITE_MEMORY_START = 0x2C, + MIPI_DCS_WRITE_LUT = 0x2D, + MIPI_DCS_READ_MEMORY_START = 0x2E, + MIPI_DCS_SET_PARTIAL_AREA = 0x30, + MIPI_DCS_SET_SCROLL_AREA = 0x33, + MIPI_DCS_SET_TEAR_OFF = 0x34, + MIPI_DCS_SET_TEAR_ON = 0x35, + MIPI_DCS_SET_ADDRESS_MODE = 0x36, + MIPI_DCS_SET_SCROLL_START = 0x37, + MIPI_DCS_EXIT_IDLE_MODE = 0x38, + MIPI_DCS_ENTER_IDLE_MODE = 0x39, + MIPI_DCS_SET_PIXEL_FORMAT = 0x3A, + MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C, + MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E, + MIPI_DCS_SET_TEAR_SCANLINE = 0x44, + MIPI_DCS_GET_SCANLINE = 0x45, + MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51, /* MIPI DCS 1.3 */ + MIPI_DCS_GET_DISPLAY_BRIGHTNESS = 0x52, /* MIPI DCS 1.3 */ + MIPI_DCS_WRITE_CONTROL_DISPLAY = 0x53, /* MIPI DCS 1.3 */ + MIPI_DCS_GET_CONTROL_DISPLAY = 0x54, /* MIPI DCS 1.3 */ + MIPI_DCS_WRITE_POWER_SAVE = 0x55, /* MIPI DCS 1.3 */ + MIPI_DCS_GET_POWER_SAVE = 0x56, /* MIPI DCS 1.3 */ + MIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 0x5E, /* MIPI DCS 1.3 */ + MIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 0x5F, /* MIPI DCS 1.3 */ + MIPI_DCS_READ_DDB_START = 0xA1, + MIPI_DCS_READ_DDB_CONTINUE = 0xA8, +} mipi_dcs_cmd_t; + +typedef enum mipi_dsi_pixel_format { + MIPI_DSI_FMT_RGB888, + MIPI_DSI_FMT_RGB666, + MIPI_DSI_FMT_RGB666_PACKED, + MIPI_DSI_FMT_RGB565, +} mipi_dsi_pixel_format_t; + +typedef enum mipi_dsi_video_mode { + MIPI_DSI_VIDEO_MODE_SYNC_PULSE = 0x00, + MIPI_DSI_VIDEO_MODE_SYNC_EVENT = 0x01, + MIPI_DSI_VIDEO_MODE_BURST = 0x02, +} mipi_dsi_video_mode_t; + +/** + * mipi_dsi_msg_t - read/write DSI buffer + */ +typedef struct mipi_dsi_msg { + uint8_t channel; /*!< virtual channel id */ + uint8_t type; /*!< payload data type */ + uint16_t tx_len; /*!< length of tx_buf */ + const void *tx_buf; /*!< data to be written */ + uint16_t rx_len; /*!< length of rx_buf */ + void *rx_buf; /*!< data to be read, or NULL */ +} mipi_dsi_msg_t; + +typedef struct mipi_video_para { + uint32_t pixel_clock_khz; + uint32_t hactive; /*!< hor. active video */ + uint32_t hfront_porch; /*!< hor. front porch */ + uint32_t hback_porch; /*!< hor. back porch */ + uint32_t hsync_len; /*!< hor. sync len */ + + uint32_t vactive; /*!< ver. active video */ + uint32_t vfront_porch; /*!< ver. front porch */ + uint32_t vback_porch; /*!< ver. back porch */ + uint32_t vsync_len; /*!< ver. sync len */ +} mipi_video_para_t; + +typedef struct mipi_dsi_config { + uint32_t lane_mbps; + uint8_t channel; + uint8_t lanes; + bool disable_eotp; + mipi_dsi_pixel_format_t pixel_format; + mipi_video_para_t video_para; + mipi_dsi_video_mode_t video_mode; +} mipi_dsi_config_t; + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief get MIPI_DSI default config on video mode + * + * @param cfg: MIPI_DSI default config + */ +void mipi_dsi_get_defconfig_on_video(mipi_dsi_config_t *cfg); + +/** + * @brief MIPI_DSI init + * + * @param ptr MIPI_DSI base address + * @param cfg config of MIPI_DSI + */ +void mipi_dsi_init(MIPI_DSI_Type *ptr, mipi_dsi_config_t *cfg); + +/** + * @brief MIPI_DSI phy interface power on + * + * @param ptr MIPI_DSI base address + */ +void mipi_dsi_phy_poweron(MIPI_DSI_Type *ptr); + +/** + * @brief MIPI_DSI phy interface power down + * + * @param ptr MIPI_DSI base address + */ +void mipi_dsi_phy_powerdown(MIPI_DSI_Type *ptr); + +/** + * @brief MIPI_DSI hs transfer start + * + * @param ptr MIPI_DSI base address + */ +void mipi_dsi_video_mode_hs_transfer_enable(MIPI_DSI_Type *ptr); + +/** + * @brief MIPI_DSI hs transfer stop + * + * @param ptr MIPI_DSI base address + */ +void mipi_dsi_video_mode_hs_transfer_disable(MIPI_DSI_Type *ptr); + +/** + * @brief transmit data using mipi dsi message in low power mode + * + * @param ptr MIPI_DSI base address + * @param msg MPI_DSI message + * + * @return The number of bytes transmitted on success or a negative error code + * on failure. + */ +int mipi_dsi_lp_cmd_transfer(MIPI_DSI_Type *ptr, const mipi_dsi_msg_t *msg); + +/** + * @brief specify the maximum size of the + * the payload in a long packet transmitted from the peripheral back to the + * host processor + * + * @param ptr: MIPI_DSI base address + * @param channel: virtual channel + * @param value: the maximum size of the payload + * + * @return: true on success or false on failure. + */ +int mipi_dsi_set_maximum_return_packet_size(MIPI_DSI_Type *ptr, uint8_t channel, uint16_t value); + +/** + * @brief transmit data using a generic write packet + * + * @param ptr: MIPI_DSI base address + * @param channel: virtual channel + * @param payload: buffer containing the payload + * @param size: size of payload buffer + * + * This function will automatically choose the right data type depending on + * the payload length. + * + * @return: The number of bytes transmitted on success or a negative error code + * on failure. + */ +int mipi_dsi_generic_write(MIPI_DSI_Type *ptr, uint8_t channel, const void *payload, + uint16_t size); + +/** + * @brief receive data using a generic read packet + * + * @param ptr: MIPI_DSI base address + * @param channel: virtual channel + * @param params: buffer containing the request parameters + * @param num_params: number of request parameters + * @param data: buffer in which to return the received data + * @param size: size of receive buffer + * + * This function will automatically choose the right data type depending on + * the number of parameters passed in. + * + * @return: The number of bytes successfully read or a negative error code on + * failure. + */ +int mipi_dsi_generic_read(MIPI_DSI_Type *ptr, uint8_t channel, const void *params, + uint16_t num_params, void *data, uint16_t size); + +/** + * @brief transmit a DCS command with payload + * + * @param ptr: MIPI_DSI base address + * @param channel: virtual channel + * @param data: buffer containing data to be transmitted + * @param len: size of transmission buffer + * + * This function will automatically choose the right data type depending on + * the command payload length. + * + * @return: The number of bytes successfully transmitted or a negative error + * code on failure. + */ +int mipi_dsi_dcs_write_buffer(MIPI_DSI_Type *ptr, uint8_t channel, + const void *data, uint16_t len); + +/** + * @brief send DCS write command + * + * @param ptr: MIPI_DSI base address + * @param channel: virtual channel + * @param cmd: DCS command + * @param data: buffer containing the command payload + * @param len: command payload length + * + * This function will automatically choose the right data type depending on + * the command payload length. + * + * @return: The number of bytes successfully transmitted or a negative error + * code on failure. + */ +int mipi_dsi_dcs_write(MIPI_DSI_Type *ptr, uint8_t channel, uint8_t cmd, + const void *data, uint16_t len); + +/** + * @brief send DCS read request command + * + * @param ptr: MIPI_DSI base address + * @param channel: virtual channel + * @param cmd: DCS command + * @param data: buffer in which to receive data + * @param len: size of receive buffer + * + * @return: The number of bytes read or a negative error code on failure. + */ +int mipi_dsi_dcs_read(MIPI_DSI_Type *ptr, uint8_t channel, uint8_t cmd, void *data, uint16_t len); + + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ +#endif /* HPM_MIPI_DSI_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mipi_dsi_phy_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mipi_dsi_phy_drv.h new file mode 100644 index 00000000000..0cc0038ca83 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mipi_dsi_phy_drv.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_MIPI_DSI_PHY_DRV_H +#define HPM_MIPI_DSI_PHY_DRV_H + +/** + * @brief MIPI_DSI_PHY APIs + * @defgroup mipi_dsi_phy_interface MIPI_DSI_PHY driver APIs + * @ingroup mipi_dsi_phy_interfaces + * @{ + */ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_mipi_dsi_phy_regs.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct mipi_dsi_phy_config { + uint32_t lane_mbps; /*!< lane speed */ + uint8_t lanes; /*!< number of lane */ +} mipi_dsi_phy_config_t; + +/** + * @brief MIPI_DSI_PHY init + * + * @param ptr MIPI_DSI_PHY base address + * @param cfg config of MIPI_DSI_PHY + */ +void mipi_dsi_phy_init(MIPI_DSI_PHY_Type *ptr, mipi_dsi_phy_config_t *cfg); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ +#endif /* HPM_MIPI_DSI_PHY_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mmc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mmc_drv.h new file mode 100644 index 00000000000..aec551480e3 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mmc_drv.h @@ -0,0 +1,611 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_MMC_DRV_H +#define HPM_MMC_DRV_H + +#include "hpm_common.h" +#include "hpm_mmc_regs.h" +/** + * @brief MMC driver APIs + * @defgroup mmc_interface MMC driver APIs + * @ingroup mmc_interfaces + * @{ + */ + +/* trigger source to update position parameter */ +typedef enum { + mmc_pos_update_by_timestamp = 0, + mmc_pos_update_by_intrgr0_rise_edge = 1, + mmc_pos_update_by_intrgr1_rise_edge = 2, + mmc_pos_update_by_outtrgr0_rise_edge = 3, + mmc_pos_update_by_outtrgr1_rise_edge = 4, + mmc_pos_update_by_self_pos_thr = 5, + mmc_pos_update_by_self_speed_thr = 6, +} mmc_pos_update_trigger_t; + + +/* cmd mask to update position parameter */ +typedef enum { + mmc_pos_update_none = 0, + mmc_pos_update_position = 1 << 0, + mmc_pos_update_revolution = 1 << 1, + mmc_pos_update_speed = 1 << 2, + mmc_pos_update_accel = 1 << 3, + mmc_pos_update_all = 0b1111, +} mmc_pos_update_cmd_mask_t; + +typedef enum { + mmc_coef_not_update = 0, + mmc_coef_p_update = 1 << 0, + mmc_coef_i_update = 1 << 1, + mmc_coef_a_update = 1 << 2, + mmc_coef_update_all = 0b111, +} mmc_coef_update_cmd_mask_t; + +typedef struct { + bool discrete_pos_mode; + uint32_t discrete_line; + uint32_t continuous_step_thr; + uint32_t continuous_circ_thr; + uint32_t oosync_theta_thr; +} mmc_track_pos_mode_t; + +typedef struct { + bool force_accel_to_zero; + bool en_ms_coef; + bool open_loop_mode; + bool pos_16bit_type; /* true for output 16bit position, false for output 32bit position */ + bool sync_new_pos; /* predictor base new track position data */ + mmc_track_pos_mode_t pos_mode; +} mmc_track_mode_t; + +typedef struct { + uint32_t pos_time; + uint32_t position; + int32_t revolution; + double speed; + double accel; + uint32_t cmd_mask; /*!< cmd to to select which parameters to update */ + uint32_t trigger; /*!< trigger source for when to update parameters */ +} mmc_pos_or_delta_pos_input_t; + +typedef struct { + uint32_t coef_time; + double coef_p; + double coef_i; + double coef_a; + uint32_t cmd_mask; /* cmd to select change which parameter */ +} mmc_coef_input_t; + +typedef struct { + uint32_t err_thr; + uint32_t hold_time; + double coef_p; + double coef_i; + double coef_a; +} mmc_coef_trig_config_t; + +typedef struct { + uint32_t time; + uint32_t position; + int32_t revolution; + double speed; + double accel; +} mmc_pos_out_t; + +typedef struct { + double coef_p; + double coef_i; + double coef_a; +} mmc_coef_out_t; + +/* track event, definition align with interrupt mask and status mask */ +typedef enum { + mmc_track_shadow_read_done = 1 << 0, + mmc_track_init_coefs_done = 1 << 1, + mmc_track_init_pos_done = 1 << 2, + mmc_track_oosync = 1 << 4, + mmc_track_idle = 1 << 5, /*!< no corresponding interrupt */ + mmc_pred1_init_pos_done = 1 << 6, + mmc_pred0_init_pos_done = 1 << 7, + mmc_track_init_delta_pos_done = 1 << 8, + mmc_track_pos_trig_valid = 1 << 9, + mmc_track_speed_trig_valid = 1 << 10, +} mmc_track_event_t; + +typedef enum { + mmc_pred_idle = MMC_BR_BR_ST_IDLE_MASK, + mmc_pred_init_delta_pos_done = MMC_BR_BR_ST_INI_DELTA_POS_DONE_MASK, + mmc_pred_pos_trig_valid = MMC_BR_BR_ST_POS_TRG_VLD_MASK, + mmc_pred_speed_trig_valid = MMC_BR_BR_ST_SPEED_TRG_VLD_MASK, + mmc_pred_open_loop = MMC_BR_BR_ST_OPEN_LOOP_ST_MASK, +} mmc_pred_event_t; + +typedef enum { + mmc_pred_pos_trig_valid_int = MMC_BR_BR_CTRL_POS_TRG_VALID_IE_MASK, + mmc_pred_speed_trig_valid_int = MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_MASK, + mmc_pred_init_delta_pos_done_int = MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_MASK +} mmc_pred_int_t; + +typedef struct { + bool speed_trig_int; + bool position_trig_int; + bool delta_pos_done_trig_int; + bool open_loop_mode; + uint8_t pred_mode; + uint8_t not_first_pred_trig_type; + uint8_t first_pred_trig_type; +} mmc_pred_mode_t; + +typedef enum { + mmc_pred_not_reload_pos_cmd = 0, + mmc_pred_0_reload_pos_cmd = 2, + mmc_pred_1_reload_pos_cmd = 1, + mmc_pred_both_reload_pos_cmd = 3, +} mmc_pred_reload_pos_cmd_t; + +typedef enum { + mmc_pred_by_period = 0, + mmc_pred_continuously_repeat = 1, + mmc_pred_only_once = 2, +} mmc_pred_time_t; + +/* using for mmc_pred_by_period mode */ +typedef struct { + uint32_t offset_time; + uint32_t period_time; + uint32_t first_time; +} mmc_pred_period_time_t; + +typedef struct { + bool less_than; /*!< true for less than, false for greater than */ + bool enable; + uint32_t position_thr; /*!< position in a cycle */ + int32_t revolution_thr; /*!< cycle */ +} mmc_pos_trig_t; + +typedef struct { + bool absolute_compare; /*!< true for absolute value compare, false for signed value compare */ + bool less_than; /*!< true for less than, false for greater than */ + bool enable; + int32_t speed_thr; +} mmc_speed_trig_t; + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief MMC set frequency + * @param [in] base MMC base address + * @param [in] freq the moto system freq + */ +static inline void mmc_set_sysclk_freq(MMC_Type *base, uint32_t freq) +{ + uint32_t period; + base->SYSCLK_FREQ = freq; + /* 1/freq *(2^24)*(2^20) */ + period = (uint32_t)((double)(1 << 20) * (1 << 24) / freq); + base->SYSCLK_PERIOD = period; +} + +/** + * @brief MMC software reset + * @param [in] base MMC base address + */ +static inline void mmc_software_reset(MMC_Type *base) +{ + base->CR |= MMC_CR_SFTRST_MASK; + base->CR &= ~MMC_CR_SFTRST_MASK; +} + +/** + * @brief MMC module enable + * @param [in] base MMC base address + */ +static inline void mmc_enable_module(MMC_Type *base) +{ + base->CR |= MMC_CR_MOD_EN_MASK; +} + +/** + * @brief MMC module disable + * @param [in] base MMC base address + */ +static inline void mmc_disable_module(MMC_Type *base) +{ + base->CR &= ~MMC_CR_MOD_EN_MASK; +} + +/** + * @brief MMC track set loop mode + * @param [in] base MMC base address + * @param [in] open_loop true for open loop, false for close loop + */ +static inline void mmc_track_set_open_loop_mode(MMC_Type *base, bool open_loop) +{ + if (open_loop) { + base->CR |= MMC_CR_OPEN_LOOP_MODE_MASK; + } else { + base->CR &= ~MMC_CR_OPEN_LOOP_MODE_MASK; + } +} + +/** + * @brief MMC track set adjop mode + * @param [in] base MMC base address + * @param [in] adjop true for adjop mode, false for normal mode + */ +static inline void mmc_track_set_adjop_mode(MMC_Type *base, bool adjop) +{ + if (adjop) { + base->CR |= MMC_CR_ADJOP_MASK; + } else { + base->CR &= ~MMC_CR_ADJOP_MASK; + } +} + +/** + * @brief MMC track request shadow read + * @param [in] base MMC base address + * + * @note request shadow before read mmc track resoult register + */ +static inline void mmc_track_enable_shadow_read(MMC_Type *base) +{ + base->CR |= MMC_CR_SHADOW_RD_REQ_MASK; + /* SHADOW_RD_REQ clear indicates that the shadow is complete */ + while ((base->CR & MMC_CR_SHADOW_RD_REQ_MASK) == MMC_CR_SHADOW_RD_REQ_MASK) { + } +} + +/** + * @brief MMC track enable interrupt + * @param [in] base MMC base address + * @param [in] int_mask interrupt_mask @ref mmc_track_event_t + */ +static inline void mmc_track_enable_interrupt(MMC_Type *base, uint32_t int_mask) +{ + base->INT_EN = int_mask; +} + +/** + * @brief MMC track disable interrupt + * @param [in] base MMC base address + * @param [in] int_mask interrupt_mask @ref mmc_track_event_t + */ +static inline void mmc_track_disable_interrupt(MMC_Type *base, uint32_t int_mask) +{ + base->INT_EN &= ~int_mask; +} + +/** + * @brief MMC track get status register value + * @param [in] base MMC base address + * @retval status register value + */ +static inline uint32_t mmc_track_get_status(MMC_Type *base) +{ + return base->STA; +} + +/** + * @brief MMC track clear status flag in status register + * @param [in] base MMC base address + * @param [in] clr_mask @ref mmc_track_event_t + */ +static inline void mmc_track_clear_status(MMC_Type *base, uint32_t clr_mask) +{ + base->STA = clr_mask; /* W1C */ +} + +/** + * @brief MMC track set the threshold of theta for out-of-sync + * @param [in] base MMC base address + * @param [in] threshold threshold value + */ +static inline void mmc_track_set_oosync_theta_threshold(MMC_Type *base, uint32_t threshold) +{ + base->OOSYNC_THETA_THR = MMC_OOSYNC_THETA_THR_VAL_SET(threshold); +} + +/** + * @brief MMC track config position mode + * @param [in] base MMC base address + * @param [in] mode mmc_track_pos_mode_t + */ +void mmc_track_config_pos_mode(MMC_Type *base, mmc_track_pos_mode_t *mode); + +/** + * @brief MMC track get default mode config + * @param [in] base MMC base address + * @param [in] config mmc_track_mode_t + */ +void mmc_track_get_default_mode_config(MMC_Type *base, mmc_track_mode_t *config); + +/** + * @brief MMC track config mode + * @param [in] base MMC base address + * @param [in] config mmc_track_mode_t + */ +void mmc_track_config_mode(MMC_Type *base, mmc_track_mode_t *config); + +/** + * @brief MMC track config position parameter + * @param [in] base MMC base address + * @param [in] para mmc_pos_or_delta_pos_input_t + */ +void mmc_track_config_pos_para(MMC_Type *base, mmc_pos_or_delta_pos_input_t *para); + +/** + * @brief MMC track config delta parameter + * @param [in] base MMC base address + * @param [in] para mmc_pos_or_delta_pos_input_t + */ +void mmc_track_config_delta_para(MMC_Type *base, mmc_pos_or_delta_pos_input_t *para); + +/** + * @brief MMC track config coef parameter + * @param [in] base MMC base address + * @param [in] para mmc_coef_input_t + */ +void mmc_track_config_coef_para(MMC_Type *base, mmc_coef_input_t *para); + +/** + * @brief MMC track config position trigger + * @param [in] base MMC base address + * @param [in] trig mmc_pos_trig_t + */ +void mmc_track_config_position_trig(MMC_Type *base, mmc_pos_trig_t *trig); + +/** + * @brief MMC track config speed trigger + * @param [in] base MMC base address + * @param [in] trig mmc_speed_trig_t + */ +void mmc_track_config_speed_trig(MMC_Type *base, mmc_speed_trig_t *trig); + +/** + * @brief MMC track disable position trigger + * @param [in] base MMC base address + */ +static inline void mmc_track_disable_position_trig(MMC_Type *base) +{ + base->POS_TRG_CFG &= ~MMC_POS_TRG_CFG_EN_MASK; +} + +/** + * @brief MMC track disable speed trigger + * @param [in] base MMC base address + */ +static inline void mmc_track_disable_speed_trig(MMC_Type *base) +{ + base->SPEED_TRG_CFG &= ~MMC_SPEED_TRG_CFG_EN_MASK; +} + +/** + * @brief MMC track config multiple coef trigger + * @param [in] base MMC base address + * @param [in] index coef trigger index(0/1/2) + * @param [in] config mmc_coef_trig_config_t + */ +void mmc_track_config_coef_trig(MMC_Type *base, uint8_t index, mmc_coef_trig_config_t *config); + +/** + * @brief MMC track get result + * @param [in] base MMC base address + * @param [out] pos_out mmc_pos_out_t + * @param [out] coef_out mmc_coef_out_t + */ +void mmc_track_get_result(MMC_Type *base, mmc_pos_out_t *pos_out, mmc_coef_out_t *coef_out); + +/* predictor */ +/** + * @brief MMC enable predictor + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + */ +static inline void mmc_enable_pred(MMC_Type *base, uint8_t index) +{ + base->BR[index].BR_CTRL |= MMC_BR_BR_CTRL_BR_EN_MASK; +} + +/** + * @brief MMC disable predictor + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + */ +static inline void mmc_disable_pred(MMC_Type *base, uint8_t index) +{ + base->BR[index].BR_CTRL &= ~MMC_BR_BR_CTRL_BR_EN_MASK; +} + +/** + * @brief MMC predictor set loop mode + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + * @param [in] open_loop true for open loop, false for close loop + */ +static inline void mmc_pred_set_open_loop_mode(MMC_Type *base, uint8_t index, bool open_loop) +{ + if (open_loop) { + base->BR[index].BR_CTRL |= MMC_BR_BR_CTRL_OPEN_LOOP_MODE_MASK; + } else { + base->BR[index].BR_CTRL &= ~MMC_BR_BR_CTRL_OPEN_LOOP_MODE_MASK; + } +} + +/** + * @brief MMC predictor set pred time + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + * @param [in] time mmc_pred_time_t + */ +static inline void mmc_pred_set_pred_time(MMC_Type *base, uint8_t index, mmc_pred_time_t time) +{ + base->BR[index].BR_CTRL &= ~MMC_BR_BR_CTRL_PRED_MODE_MASK; + base->BR[index].BR_CTRL |= MMC_BR_BR_CTRL_PRED_MODE_SET(time); +} + +/** + * @brief MMC pred enable interrupt + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + * @param [in] int_mask interrupt_mask @ref mmc_pred_int_t + */ +static inline void mmc_pred_enable_interrupt(MMC_Type *base, uint8_t index, uint32_t int_mask) +{ + base->BR[index].BR_CTRL |= int_mask; +} + +/** + * @brief MMC pred disable interrupt + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + * @param [in] int_mask interrupt_mask @ref mmc_pred_int_t + */ +static inline void mmc_pred_disable_interrupt(MMC_Type *base, uint8_t index, uint32_t int_mask) +{ + base->BR[index].BR_CTRL &= ~int_mask; +} + +/** + * @brief MMC predictor get status register value + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + * @retval predictor status register value + */ +static inline uint32_t mmc_pred_get_status(MMC_Type *base, uint8_t index) +{ + return base->BR[index].BR_ST; +} + +/** + * @brief MMC predictor clear status bit in reigster + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + * @param [in] clr_mask bit mask @ref mmc_pred_event_t + */ +static inline void mmc_pred_clear_status(MMC_Type *base, uint8_t index, uint32_t clr_mask) +{ + base->BR[index].BR_ST = clr_mask; /*!< W1C */ +} + +/** + * @brief MMC predictor get default mode config + * @param [in] base MMC base address + * @param [in] config mmc_pred_mode_t + */ +void mmc_pred_get_default_mode_config(MMC_Type *base, mmc_pred_mode_t *config); + +/** + * @brief MMC predictor config mode + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + * @param [in] config mmc_pred_mode_t + */ +void mmc_pred_config_mode(MMC_Type *base, uint8_t index, mmc_pred_mode_t *config); + +/** + * @brief MMC predictor config position parameter + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + * @param [in] para mmc_pos_or_delta_pos_input_t + * @param [in] req_reload request to update parameter cmd + * + * @note 2 predictors can be set simultaneously by call mmc_pred_reload_pos_cmd() + */ +void mmc_pred_config_pos_para(MMC_Type *base, uint8_t index, mmc_pos_or_delta_pos_input_t *para, bool req_reload); + +/** + * @brief MMC predictor reload position parameter cmd + * @param [in] base MMC base address + * @param [in] cmd mmc_pred_reload_pos_cmd_t + */ +static inline void mmc_pred_reload_pos_cmd(MMC_Type *base, mmc_pred_reload_pos_cmd_t cmd) +{ + base->CR &= ~(MMC_CR_INI_BR0_POS_REQ_MASK | MMC_CR_INI_BR0_POS_REQ_MASK); + base->CR |= cmd << MMC_CR_INI_BR1_POS_REQ_SHIFT; +} + +/** + * @brief MMC predictor update delta parameter + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + * @param [in] para mmc_pos_or_delta_pos_input_t + */ +void mmc_pred_config_delta_para(MMC_Type *base, uint8_t index, mmc_pos_or_delta_pos_input_t *para); + +/** + * @brief MMC predictor config period time + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + * @param [in] time mmc_pred_period_time_t + */ +void mmc_pred_config_period_time(MMC_Type *base, uint8_t index, mmc_pred_period_time_t *time); + +/** + * @brief MMC predictor config position trigger + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + * @param [in] trig mmc_pos_trig_t + */ +void mmc_pred_config_position_trig(MMC_Type *base, uint8_t index, mmc_pos_trig_t *trig); + +/** + * @brief MMC predictor config speed trigger + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + * @param [in] trig mmc_speed_trig_t + */ +void mmc_pred_config_speed_trig(MMC_Type *base, uint8_t index, mmc_speed_trig_t *trig); + +/** + * @brief MMC predictor disable position trigger + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + */ +static inline void mmc_pred_disable_position_trig(MMC_Type *base, uint8_t index) +{ + base->BR[index].BR_TRG_POS_CFG &= ~MMC_BR_BR_TRG_POS_CFG_EN_MASK; +} + +/** + * @brief MMC predictor disable speed trigger + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + */ +static inline void mmc_pred_disable_speed_trig(MMC_Type *base, uint8_t index) +{ + base->BR[index].BR_TRG_SPEED_CFG &= ~MMC_BR_BR_TRG_SPEED_CFG_EN_MASK; +} + +/** + * @brief MMC predictor get result + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + * @param [out] pos_out mmc_pos_out_t + */ +void mmc_pred_get_result(MMC_Type *base, uint8_t index, mmc_pos_out_t *pos_out); + +/** + * @brief MMC predictor get result + * @param [in] base MMC base address + * @param [out] para mmc_pos_or_delta_pos_input_t + */ +void mmc_get_default_pos_or_delta_pos_para(MMC_Type *base, mmc_pos_or_delta_pos_input_t *para); + + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_MMC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mono_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mono_drv.h index eaa2a39fad1..e711dcfb5bd 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mono_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mono_drv.h @@ -24,56 +24,19 @@ extern "C" { #endif -/** - * @brief Get counter high - * - * @param[in] ptr MONO base address - * - * @return counter value high 16 bits - */ -static inline uint16_t mono_get_counter_high(MONO_Type *ptr) -{ - return MONO_MONOH_COUNTER_GET(ptr->MONOH); -} - -/** - * @brief Get counter low - * - * @param[in] ptr MONO base address - * - * @return counter value low 32 bits - */ -static inline uint32_t mono_get_counter_low(MONO_Type *ptr) -{ - return MONO_MONOL_COUNTER_GET(ptr->MONOL); -} - /** * @brief Get counter * * @param[in] ptr MONO base address * - * @return 48 bits counter value + * @return 64 bits counter value */ static inline uint64_t mono_get_counter(MONO_Type *ptr) { - return (uint64_t)((uint64_t)mono_get_counter_high(ptr) << 32) - | (uint64_t)mono_get_counter_low(ptr); -} - -/** - * @brief Get epoch - * - * @param[in] ptr MONO Base address - * - * @return epoch value 16 bits - */ -static inline uint32_t mono_get_epoch(MONO_Type *ptr) -{ - return MONO_MONOH_EPOCH_GET(ptr->MONOH); + return (uint64_t)((uint64_t)((ptr->MONOH) << 32)) + | (uint64_t)((ptr->MONOL)); } - /** * @brief Update MONO counter by 1 * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_opamp_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_opamp_drv.h new file mode 100644 index 00000000000..329db9f02e5 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_opamp_drv.h @@ -0,0 +1,546 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_OPAMP_DRV_H +#define HPM_OPAMP_DRV_H + +#include "hpm_common.h" +#include "hpm_opamp_regs.h" +#include "hpm_soc_feature.h" + +/** + * @brief OPMAP driver APIs + * @defgroup opamp_interface OPAMP driver APIs + * @ingroup io_interfaces + * @{ + * + */ +#define OPAMP_MODE_FOLLOW_KEY (0x06) +#define OPAMP_MODE_INVERT_INDEX0_KEY (0x08) +#define OPAMP_MODE_INVERT_INDEX1_KEY (0x18) +#define OPAMP_MODE_NON_INVERT_INDEX0_KEY (0x01) +#define OPAMP_MODE_NON_INVERT_INDEX1_KEY (0x09) +#define OPAMP_MODE_NON_INVERT_INDEX2_KEY (0x11) +#define OPAMP_MODE_NON_INVERT_INDEX3_KEY (0x19) +#define OPAMP_MODE_NON_INVERT_INDEX4_KEY (0x09) +#define OPAMP_MODE_USER_DEFINE_KEY (0x04) + +/** + * @brief Reverse Input Pin Selection + * + */ +typedef enum { + inm_pad_vim0 = 0, /**< Connect pad vim0 */ + inm_pad_vim1 = 1, /**< Connect pad vim1 */ + inm_pad_vim2 = 2, /**< Connect pad vim2 */ + inm_pad_dac = 3, /**< Connect pad vim dac */ + inm_pad_floating = 4 /**< Connect inm floating */ +} opamp_inm_pad_t; + +/** + * @brief Gain multiplier selection + * + */ +typedef enum { + gain_x_2 = 0, /**< gain x2 */ + gain_x_4 = 1, + gain_x_8 = 2, + gain_x_16 = 3, + gain_x_32 = 4, + gain_x_64 = 5, + gain_x_128 = 6, /**< gain x128 */ +} opamp_gain_t; + +/** + * @brief Miller Capacitor Selection + * + */ +typedef enum { + miller_cap_x_7 = 0, /**< 7 unit cap */ + miller_cap_x_8 = 1, + miller_cap_x_10 = 2, + miller_cap_x_13 = 3, + miller_cap_x_15 = 4, /**< 15 unit cap */ + miller_cap_x_18 = 5, + miller_cap_x_5 = 6, + miller_cap_x_6 = 7, /**< 6 unit cap */ +} opamp_miller_cap_t; + +/** + * @brief Positive Input Pin Selection + * + */ +typedef enum { + inp_pad_vip0 = 0, /**< Connect pad vip0 */ + inp_pad_vip1 = 1, /**< Connect pad vip1 */ + inp_pad_vip2 = 2, /**< Connect pad vip2 */ + inp_pad_dac = 3, /**< Connect pad vip dac */ + inp_pad_vsupply_x_0_25 = 4, /**< Connect reference = 0.25 * vsupply */ + inp_pad_vsupply_x_0_5 = 5, /**< Connect reference = 0.5 * vsupply */ + inp_pad_vsupply_x_0_75 = 6, /**< Connect reference = 0.75 * vsupply */ + inp_pad_floating = 7 /**< Connect inp floating */ +} opamp_inp_pad_t; + +/** + * @brief opamp preset channel + * + */ +typedef enum { + cfg_preset_0 = OPAMP_CFG_PRESET0, + cfg_preset_1 = OPAMP_CFG_PRESET1, + cfg_preset_2 = OPAMP_CFG_PRESET2, + cfg_preset_3 = OPAMP_CFG_PRESET3, + cfg_preset_4 = OPAMP_CFG_PRESET4, + cfg_preset_5 = OPAMP_CFG_PRESET5, + cfg_preset_6 = OPAMP_CFG_PRESET6, + cfg_preset_7 = OPAMP_CFG_PRESET7, +} opamp_cfg_preset_chn_t; + +/** + * @brief operational amplifier + * + */ +typedef enum { + mode_follow = 0, /**< opamp follow mode */ + mode_invert_intern_vol = 1, /**< inverting opamp */ + mode_invert_extern_vol = 2, /**< inverted amplification mode, external reference voltage */ + mode_invert_dac_vol = 3, /**< inverted amplification mode, DAC output reference voltage */ + mode_non_invert_gnd_vol = 4, /**< forward amplification mode, GND is the reference voltage */ + mode_non_invert_extern_vol = 5, /**< forward amplification mode, external reference voltage */ + mode_non_invert_dac_vol = 6, /**< forward amplification mode, DAC output reference voltage */ + mode_user = 7, /**< custom Mode */ +} opamp_mode_t; + +/** + * @brief opamp configuration preset0 + * + */ +typedef union opamp_cfg_preset0 { + struct { + uint32_t vip_select: 3; + uint32_t vim_select: 3; + uint32_t vswitch_select: 3; + uint32_t cap_select: 4; + uint32_t reserve: 19; + }; + uint32_t val; +} opamp_ctrl_cfg_preset0_t; + +/** + * @brief opamp configuration preset1 + * + */ +typedef union opamp_cfg_preset1 { + struct { + uint32_t res_select: 3; + uint32_t function_mode: 5; + uint32_t iref_select: 2; + uint32_t opaout_select: 2; + uint32_t is_vssa_disconnect: 1; + uint32_t en_lv: 1; + uint32_t hw_trig_en: 1; + uint32_t reserve: 17; + }; + uint32_t val; +} opamp_ctrl_cfg_preset1_t; + +typedef struct opamp_cfg { + opamp_mode_t mode; + opamp_inm_pad_t negative_input_pin; + opamp_inp_pad_t positive_input_pin; + opamp_gain_t gain; + opamp_miller_cap_t miller_cap; + bool enable_extern_filter_cap; + bool enable_phase_margin_cap; +} opamp_cfg_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief opamp initialisation functions + * Use this function to initialise the op-amp to different modes + * @param opamp @ref OPAMP_Type + * @param cfg @ref opamp_cfg_t + * @return @ref hpm_stat_t + */ +hpm_stat_t opamp_init(OPAMP_Type *opamp, opamp_cfg_t *cfg); +/** + * @brief enable opamp function + * + * @param opamp @ref OPAMP_Type + */ +static inline void opamp_enable(OPAMP_Type *opamp) +{ + opamp->CTRL0 |= OPAMP_CTRL0_EN_LV_MASK; +} + +/** + * @brief preset enable opamp function + * + * @param opamp @ref OPAMP_Type + * @param preset_chn preset channel + */ +static inline void opamp_preset_opamp_enable(OPAMP_Type *opamp, uint8_t preset_chn) +{ + opamp->CFG[preset_chn].CFG1 |= OPAMP_CFG_CFG1_EN_LV_MASK; +} + +/** + * @brief disable opamp function + * + * @param opamp @ref OPAMP_Type + */ +static inline void opamp_disable(OPAMP_Type *opamp) +{ + opamp->CTRL0 &= ~OPAMP_CTRL0_EN_LV_MASK; +} + +/** + * @brief preset disable opamp function + * + * @param opamp @ref OPAMP_Type + * @param preset_chn preset channel + */ +static inline void opamp_preset_opamp_disable(OPAMP_Type *opamp, uint8_t preset_chn) +{ + opamp->CFG[preset_chn].CFG1 &= ~OPAMP_CFG_CFG1_EN_LV_MASK; +} + +/** + * @brief opamp miller cap selection + * + * @param opamp @ref OPAMP_Type + * @param select @ref opamp_miller_cap_t + */ +static inline void opamp_miller_cap_select(OPAMP_Type *opamp, opamp_miller_cap_t select) +{ + opamp->CTRL0 = (opamp->CTRL0 & (~OPAMP_CTRL0_MILLER_SEL_MASK)) | OPAMP_CTRL0_MILLER_SEL_SET(select); +} + +/** + * @brief opamp miller cap selection preset + * + * @param opamp @ref OPAMP_Type + * @param preset_chn preset channel + * @param select @ref opamp_miller_cap_t + */ +static inline void opamp_preset_miller_cap_select(OPAMP_Type *opamp, uint8_t preset_chn, opamp_miller_cap_t select) +{ + opamp->CFG[preset_chn].CFG0 = (opamp->CFG[preset_chn].CFG0 & (~OPAMP_CFG_CFG0_MILLER_SEL_MASK)) | OPAMP_CFG_CFG0_MILLER_SEL_SET(select); +} + +/** + * @brief enable phase margin compensation cap + * + * @param opamp @ref OPAMP_Type + */ +static inline void opamp_phase_margin_cap_enable(OPAMP_Type *opamp) +{ + opamp->CTRL0 &= ~OPAMP_CTRL0_DISABLE_PM_CAP_MASK; +} + +/** + * @brief enable phase margin compensation cap preset + * + * @param opamp @ref OPAMP_Type + * @param preset_chn preset channel + */ +static inline void opamp_preset_phase_margin_cap_enable(OPAMP_Type *opamp, uint8_t preset_chn) +{ + opamp->CFG[preset_chn].CFG0 &= ~OPAMP_CFG_CFG0_DISABLE_PM_CAP_MASK; +} + +/** + * @brief disable phase margin compensation cap + * + * @param opamp @ref OPAMP_Type + */ +static inline void opamp_phase_margin_cap_disable(OPAMP_Type *opamp) +{ + opamp->CTRL0 |= OPAMP_CTRL0_DISABLE_PM_CAP_MASK; +} + +/** + * @brief disable phase margin compensation cap preset + * + * @param opamp @ref OPAMP_Type + * @param preset_chn preset channel + */ +static inline void opamp_preset_phase_margin_cap_disable(OPAMP_Type *opamp, uint8_t preset_chn) +{ + opamp->CFG[preset_chn].CFG0 |= OPAMP_CFG_CFG0_DISABLE_PM_CAP_MASK; +} + +/** + * @brief opamp core inm connect pad + * + * @param opamp @ref OPAMP_Type + * @param select @ref opamp_inm_pad_t + */ +static inline void opamp_inn_pad_select(OPAMP_Type *opamp, opamp_inm_pad_t select) +{ + opamp->CTRL0 = (opamp->CTRL0 & (~OPAMP_CTRL0_VIM_SEL_MASK)) | OPAMP_CTRL0_VIM_SEL_SET(select); +} + +/** + * @brief opamp core inm connect pad preset + * + * @param opamp @ref OPAMP_Type + * @param preset_chn preset channel + * @param select @ref opamp_inm_pad_t + */ +static inline void opamp_preset_inn_pad_select(OPAMP_Type *opamp, uint8_t preset_chn, opamp_inm_pad_t select) +{ + opamp->CFG[preset_chn].CFG0 = (opamp->CFG[preset_chn].CFG0 & (~OPAMP_CFG_CFG0_VIM_SEL_MASK)) | OPAMP_CFG_CFG0_VIM_SEL_SET(select); +} + +/** + * @brief main string resistor selection + * + * @param opamp @ref OPAMP_Type + * @param select @ref opamp_gain_t + * + */ +static inline void opamp_gain_select(OPAMP_Type *opamp, opamp_gain_t select) +{ + opamp->CTRL0 = (opamp->CTRL0 & (~OPAMP_CTRL0_GAIN_SEL_MASK)) | OPAMP_CTRL0_GAIN_SEL_SET(select); +} + +/** + * @brief main string resistor selection preset + * + * @param opamp @ref OPAMP_Type + * @param preset_chn preset channel + * @param select @ref opamp_gain_t + * + */ +static inline void opamp_preset_gain_select(OPAMP_Type *opamp, uint8_t preset_chn, opamp_gain_t select) +{ + opamp->CFG[preset_chn].CFG1 = (opamp->CFG[preset_chn].CFG1 & (~OPAMP_CFG_CFG1_GAIN_SEL_MASK)) | OPAMP_CFG_CFG1_GAIN_SEL_SET(select); +} + +/** + * @brief disconnect the main series resistor and VSSA + * + * @param opamp @ref OPAMP_Type + */ +static inline void opamp_disconnect_vssa(OPAMP_Type *opamp) +{ + opamp->CTRL0 |= OPAMP_CTRL0_VBYPASS_MASK; +} + +/** + * @brief disconnect the main series resistor and VSSA preset + * + * @param opamp @ref OPAMP_Type + * @param preset_chn preset channel + */ +static inline void opamp_preset_disconnect_vssa(OPAMP_Type *opamp, uint8_t preset_chn) +{ + opamp->CFG[preset_chn].CFG1 |= OPAMP_CFG_CFG1_VBYPASS_LV_MASK; +} + +/** + * @brief connect the main series resistor and VSSA + * + * @param opamp @ref OPAMP_Type + */ +static inline void opamp_connect_vssa(OPAMP_Type *opamp) +{ + opamp->CTRL0 &= ~OPAMP_CTRL0_VBYPASS_MASK; +} + +/** + * @brief connect the main series resistor and VSSA preset + * + * @param opamp @ref OPAMP_Type + * @param preset_chn preset channel + */ +static inline void opamp_preset_connect_vssa(OPAMP_Type *opamp, uint8_t preset_chn) +{ + opamp->CFG[preset_chn].CFG1 &= ~OPAMP_CFG_CFG1_VBYPASS_LV_MASK; +} + +/** + * @brief opamp inp select + * + * @param opamp @ref OPAMP_Type + * @param select @ref opamp_inp_pad_t + */ +static inline void opamp_inp_pad_select(OPAMP_Type *opamp, opamp_inp_pad_t select) +{ + opamp->CTRL0 = (opamp->CTRL0 & (~OPAMP_CTRL0_VIP_SEL_MASK)) | OPAMP_CTRL0_VIP_SEL_SET(select); +} + +/** + * @brief opamp inp select preset + * + * @param opamp @ref OPAMP_Type + * @param preset_chn preset channel + * @param select @ref opamp_inp_pad_t + */ +static inline void opamp_preset_inp_pad_select(OPAMP_Type *opamp, uint8_t preset_chn, opamp_inp_pad_t select) +{ + opamp->CFG[preset_chn].CFG0 = (opamp->CFG[preset_chn].CFG0 & (~OPAMP_CFG_CFG0_VIP_SEL_MASK)) | OPAMP_CFG_CFG0_VIP_SEL_SET(select); +} + + +/** + * @brief opamp get current preset + * + * @param opamp @ref OPAMP_Type + * @return value + */ +static inline uint8_t opamp_get_cur_preset(OPAMP_Type *opamp) +{ + return OPAMP_STATUS_CUR_PRESET_GET(opamp->STATUS); +} + +/** + * @brief get the current preset value + * + * @param opamp @ref OPAMP_Type + * @return true one of cur_preset is selected for opamp + * @return false opamp use cfg0 parameters + */ +static inline bool opamp_get_is_preset(OPAMP_Type *opamp) +{ + return OPAMP_STATUS_PRESET_ACT_GET(opamp->STATUS); +} + +/** + * @brief Get the trigger conflict status + * + * @param opamp @ref OPAMP_Type + * @return if more than one hardware trigger is set, will put all trigger input there. + */ +static inline uint8_t opamp_get_trig_conflict_status(OPAMP_Type *opamp) +{ + return OPAMP_STATUS_TRIG_CONFLICT_GET(opamp->STATUS); +} + +/** + * @brief Clear the trigger conflict status + * + * @param opamp @ref OPAMP_Type + */ +static inline void opamp_clear_conflict_status(OPAMP_Type *opamp) +{ + opamp->STATUS = OPAMP_STATUS_TRIG_CONFLICT_MASK; +} + +/** + * @brief Set opamp preset value + * + * @param opamp @ref OPAMP_Type + * @param val @ref opamp_cfg_preset_chn_t + */ +static inline void opamp_set_sw_preset_val(OPAMP_Type *opamp, opamp_cfg_preset_chn_t val) +{ + opamp->CTRL1 = (opamp->CTRL1 & (~OPAMP_CTRL1_SW_SEL_MASK)) | OPAMP_CTRL1_SW_SEL_SET(val); +} + +/** + * @brief Enable software preset + * + * @param opamp @ref OPAMP_Type + */ +static inline void opamp_enable_sw_preset(OPAMP_Type *opamp) +{ + opamp->CTRL1 |= OPAMP_CTRL1_SW_PRESET_MASK; +} + +/** + * @brief Disable software preset + * + * @param opamp @ref OPAMP_Type + */ +static inline void opamp_disable_sw_preset(OPAMP_Type *opamp) +{ + opamp->CTRL1 &= ~OPAMP_CTRL1_SW_PRESET_MASK; +} + + +/** + * @brief Set preset x channel value + * + * @param opamp @ref OPAMP_Type + * @param preset_chn preset channel + * @param chn channel + */ +static inline void opamp_set_preset_x_chn(OPAMP_Type *opamp, uint8_t preset_chn, uint8_t chn) +{ + opamp->CFG[preset_chn].CFG2 = OPAMP_CFG_CFG2_CHANNEL_SET(chn); +} + +/** + * @brief Set preset cfg + * + * @param opamp @ref OPAMP_Type + * @param preset_chn preset channel + * @param cfg @ref opamp_cfg_t + * @return hpm_stat_t + */ +hpm_stat_t opamp_set_preset_cfg(OPAMP_Type *opamp, uint8_t preset_chn, opamp_cfg_t *cfg); + +/** + * @brief opamp enable preset hardware trig + * + * @param opamp @ref OPAMP_Type + * @param preset_chn preset channel + */ +static inline void opamp_preset_enable_hw_trig(OPAMP_Type *opamp, uint8_t preset_chn) +{ + opamp->CFG[preset_chn].CFG1 |= OPAMP_CFG_CFG1_HW_TRIG_EN_MASK; +} + +/** + * @brief opamp disable preset hardware trig + * + * @param opamp @ref OPAMP_Type + * @param preset_chn preset channel + */ +static inline void opamp_preset_disable_hw_trig(OPAMP_Type *opamp, uint8_t preset_chn) +{ + opamp->CFG[preset_chn].CFG1 &= ~OPAMP_CFG_CFG1_HW_TRIG_EN_MASK; +} + +/** + * @brief opamp set mode + * + * @param opamp @ref OPAMP_Type + * @param mode OPAMP_MODE_XX + */ +static inline void opamp_mode_set(OPAMP_Type *opamp, uint8_t mode) +{ + opamp->CTRL0 = (opamp->CTRL0 & (~OPAMP_CTRL0_MODE_MASK)) | OPAMP_CTRL0_MODE_SET(mode); +} + +/** + * @brief opamp preset set mode + * + * @param opamp @ref OPAMP_Type + * @param preset_chn preset channel + * @param mode OPAMP_MODE_XX + */ +static inline void opamp_preset_mode_set(OPAMP_Type *opamp, uint8_t preset_chn, uint8_t mode) +{ + opamp->CFG[preset_chn].CFG1 = (opamp->CFG[preset_chn].CFG1 & (~OPAMP_CFG_CFG1_MODE_MASK)) | OPAMP_CFG_CFG1_MODE_SET(mode); +} + +/** + * @} + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_ACMP_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pdgo_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pdgo_drv.h new file mode 100644 index 00000000000..d36edc9dc00 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pdgo_drv.h @@ -0,0 +1,285 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PDGO_DRV_H +#define HPM_PDGO_DRV_H + +#include "hpm_common.h" +#include "hpm_pdgo_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define DGO_GPR_WORD_COUNT (4U) /*!< DGO GPR register count */ +#define DGO_WAKEUP_COUNTER_TICKS_PER_SEC (32768UL) /*!< DGO Wakeup Counter frequency */ +#define DGO_TURNOFF_COUNTER_TICKS_PER_SEC (24000000UL) /*!< DGO Turn-off counter frequency */ +#define DGO_WAKEUP_TICK_IN_US (1000000UL / DGO_WAKEUP_COUNTER_TICKS_PER_SEC) +#define DGO_TURNOFF_TICKS_PER_US (DGO_TURNOFF_COUNTER_TICKS_PER_SEC / 1000000UL) + +/** +* +* @brief PDGO driver APIs +* @defgroup pdgo_interface DGO driver APIs +* @ingroup pdgo_interfaces +* @{ +* +*/ + +/** + * @brief Set DGO turn-off counter + * @param [in] ptr DGO base address + * @param [in] counter Turn-off counter value. Clock source is 32K + */ +static inline void pdgo_set_turnoff_counter(PDGO_Type *ptr, uint32_t counter) +{ + ptr->DGO_TURNOFF = counter; +} + +/** + * @brief Enable Software Wake-up feature on DGO + * @param [in] ptr DGO base address + */ +static inline void pdgo_enable_software_wakeup(PDGO_Type *ptr) +{ + ptr->DGO_CTR1 |= PDGO_DGO_CTR1_WAKEUP_EN_MASK; +} + +/** + * @brief Disable Software Wake-up feature on DGO + * @param [in] ptr DGO base address + */ +static inline void pdgo_disable_software_wakeup(PDGO_Type *ptr) +{ + ptr->DGO_CTR1 &= ~PDGO_DGO_CTR1_WAKEUP_EN_MASK; +} + +/** + * @brief Set DGO to one-shot wakeup mode + * @param [in] ptr DGO base address + */ +static inline void pdgo_enable_oneshot_wakeup(PDGO_Type *ptr) +{ + ptr->DGO_CTR1 &= ~PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK; +} + +/** + * @brief Enable DGO register retention mode + * @param [in] ptr DGO base address + */ +static inline void pdgo_enable_retention_mode(PDGO_Type *ptr) +{ + ptr->DGO_CTR1 |= PDGO_DGO_CTR0_RETENTION_MASK; +} + +/** + * @brief Check whether the DGO retention mode is enabled or not + * @param [in] ptr DGO base address + * + * @retval true Retention mode is enabled + * @retval false Retention mode is disabled + */ +static inline bool pdgo_is_retention_mode_enabled(PDGO_Type *ptr) +{ + return ((ptr->DGO_CTR1 & PDGO_DGO_CTR0_RETENTION_MASK) != 0U); +} + +/** + * @brief Disable DGO register retention mode + * @param [in] ptr DGO base address + */ +static inline void pdgo_disable_retention_mode(PDGO_Type *ptr) +{ + ptr->DGO_CTR1 &= ~PDGO_DGO_CTR0_RETENTION_MASK; +} + +/** + * @brief Set DGO to automatic wakeup mode + * @param [in] ptr DGO base address + */ +static inline void pdgo_enable_auto_wakeup(PDGO_Type *ptr) +{ + ptr->DGO_CTR1 |= PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK; +} + +#if defined(PDGO_SUPPORT_SYS_WAKEUP_STATUS) && (PDGO_SUPPORT_SYS_WAKEUP_STATUS == 1) +/** + * @brief Check whether DGO is waked up by System/Software + * @param [in] ptr DGO base address + * + * @retval true if DGO is waked up by System/Software + */ +static inline bool pdgo_is_system_wakeup(PDGO_Type *ptr) +{ + return ((ptr->DGO_CTR1 & PDGO_DGO_CTR1_SYS_WAKEUP_STATUS_MASK) != 0U); +} +#endif + +/** + * @brief Check whether DGO is waked up by Wake-up/Reset Pin + * @param [in] ptr DGO base address + * + * @retval true if DGO is waked up by Wakeup/Reset pin + */ +static inline bool pdgo_is_pin_wakeup(PDGO_Type *ptr) +{ + return ((ptr->DGO_CTR1 & PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_MASK) != 0U); +} + + +/** + * @brief Check whether Auto wake-up is enabled + * @param [in] ptr DGO base address + * + * @retval true - Auto wake-up is enabled + * @retval false - Auto wake-up is disabled + */ +static inline bool pdgo_is_auto_wakeup_enabled(PDGO_Type *ptr) +{ + return ((ptr->DGO_CTR1 & PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK) != 0U); +} + +/** + * @brief Enable pull-up resistor for Reset Pin + * [in] ptr DGO base address + */ +static inline void pdgo_enable_pullup_resistor_for_reset_pin(PDGO_Type *ptr) +{ + ptr->DGO_CTR2 &= ~PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_MASK; +} + +/** + * @brief Disable pull-up resistor for Reset Pin + * [in] ptr DGO base address + */ +static inline void pdgo_disable_pullup_resistor_for_reset_pin(PDGO_Type *ptr) +{ + ptr->DGO_CTR2 |= PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_MASK; +} + +/** + * Enable pull-down resistor for Wakeup pin + * [in] ptr DGO base address + */ +static inline void pdgo_enable_pulldown_resistor_for_wakeup_pin(PDGO_Type *ptr) +{ + ptr->DGO_CTR2 &= ~PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_MASK; +} + +/** + * Disable pull-down resistor for Wakeup pin + * [in] ptr DGO base address + */ +static inline void pdgo_disable_pulldown_resistor_for_wakeup_pin(PDGO_Type *ptr) +{ + ptr->DGO_CTR2 |= PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_MASK; +} + +/** + * @brief Set DGO wakeup counter + * @param [in] ptr DGO base address + * @param [in] wakeup_ctr Wakeup counter value. clock source is 32K + */ +static inline void pdgo_set_wakeup_counter(PDGO_Type *ptr, uint32_t wakeup_ctr) +{ + ptr->DGO_CTR3 = wakeup_ctr; +} + +/** + * @brief Get DGO wakeup counter value + * @param [in] ptr DGO base address + * + * @return DGO wakeup counter value + */ +static inline uint32_t pdgo_get_wakeup_counter(PDGO_Type *ptr) +{ + return ptr->DGO_CTR3; +} + +/** + * @brief Write data to DGO GPR register + * @param [in] ptr DGO base address + * @param [in] index GPR register index + * @param [in] content Data to be written to DGO GPR register + */ +static inline void pdgo_write_gpr(PDGO_Type *ptr, uint32_t index, uint32_t content) +{ + if (index < DGO_GPR_WORD_COUNT) { + *(volatile uint32_t *) ((uint32_t) &ptr->DGO_GPR00 + index * 4) = content; + } +} + +/** + * @brief Read data from DGO GPR register + * @param [in] ptr DGO base address + * @param [in] index GPR register index + * + * @return DGO GPR register value + */ +static inline uint32_t pdgo_read_gpr(PDGO_Type *ptr, uint32_t index) +{ + uint32_t reg_val = 0; + if (index < DGO_GPR_WORD_COUNT) { + reg_val = *(volatile uint32_t *) ((uint32_t) &ptr->DGO_GPR00 + index * 4); + } + return reg_val; +} + +/** + * @brief Convert the microsecond to DGO Wake-up counter value + * @param [in] us microsecond to be converted + * + * @return Converted DGO Wake-up counter value + */ +static inline uint32_t pdgo_get_wakeup_counter_from_us(uint32_t us) +{ + return (us + DGO_WAKEUP_TICK_IN_US - 1U) / DGO_WAKEUP_TICK_IN_US; +} + +/** + * @brief Convert the DGO Wake-up counter to microseconds + * @param [in] counter DGO counter + * + * @return Converted microseconds + */ +static inline uint32_t pdgo_get_us_from_wakeup_counter(uint32_t counter) +{ + return (counter * DGO_WAKEUP_TICK_IN_US); +} + +/** + * @brief Convert the microsecond to DGO Turn-off counter value + * @param [in] us microsecond to be converted + * + * @return Converted DGO Turn-off counter value + */ +static inline uint32_t pdgo_get_turnoff_counter_from_us(uint32_t us) +{ + return (us * DGO_TURNOFF_TICKS_PER_US); +} + +/** + * @brief Convert the DGO Turn-off counter to microseconds + * @param [in] counter DGO Turn-off counter + * + * @return Converted microseconds + */ +static inline uint32_t pdgo_get_us_from_turnoff_counter(uint32_t counter) +{ + return (counter + DGO_TURNOFF_TICKS_PER_US - 1U) / DGO_TURNOFF_TICKS_PER_US; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* HPM_DGO_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pdma_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pdma_drv.h index c7ab9729a66..8917a26946a 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pdma_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pdma_drv.h @@ -150,6 +150,21 @@ typedef struct pdma_plane_info { display_pixel_format_t format; /**< pixel format */ } pdma_plane_info_t; + +typedef struct pdma_blit_option { + display_alphablend_mode_t blend; + struct { + uint16_t x; + uint16_t y; + } translate; + pdma_flip_t flip; + pdma_rotate_t rotate; + struct { + float x; /* 0.0625 - 4095 */ + float y; /* 0.0625 - 4095 */ + } scale; +} pdma_blit_option_t; + #ifdef __cplusplus extern "C" { #endif @@ -344,6 +359,29 @@ hpm_stat_t pdma_scale(PDMA_Type *ptr, uint8_t alpha, display_pixel_format_t format, bool wait, uint32_t *status); +/** + * @brief PDMA get default blit option + * + * @param op option of blit + */ +void pdma_get_default_blit_option(pdma_blit_option_t *op); + +/** + * @brief PDMA blit plane by option + * + * @param ptr PDMA base address + * @param dst target buff address + * @param src source buff address + * @param op option of blit + * @param wait wait for execution to complete + * @param status pdma status + * @retval hpm_stat_t: status_success if flip and rotate plane without any error + */ +hpm_stat_t pdma_blit_ex(PDMA_Type *ptr, + display_buf_t *dst, + display_buf_t *src, + pdma_blit_option_t *op, + bool wait, uint32_t *status); /** * @brief PDMA set block size diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pixelmux_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pixelmux_drv.h new file mode 100644 index 00000000000..d9f26eb9f38 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pixelmux_drv.h @@ -0,0 +1,312 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PIXELMUX_DRV_H +#define HPM_PIXELMUX_DRV_H + +/** + * @brief PIXELMUX APIs + * @defgroup pixelmux_interface PIXELMUX driver APIs + * @ingroup pixelmux_interfaces + * @{ + */ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_pixelmux_regs.h" + +/** + * @brief rgb interface pixel data source + */ +typedef enum { + pixelmux_rgb_sel_lcdc0 = 0, + pixelmux_rgb_sel_lcdc1 +} pixelmux_rgb_select_t; + +/** + * @brief gwc1 pixel data source + */ +typedef enum { + pixelmux_gwc1_sel_lcdc0 = 0, + pixelmux_gwc1_sel_lcdc1 +} pixelmux_gwc1_select_t; + +/** + * @brief gwc0 pixel data source + */ +typedef enum { + pixelmux_gwc0_sel_lcdc0 = 0, + pixelmux_gwc0_sel_lcdc1 +} pixelmux_gwc0_select_t; + +/** + * @brief lvb di1 pixel data source + */ +typedef enum { + pixelmux_lvb_di1_sel_lcdc0 = 0, + pixelmux_lvb_di1_sel_lcdc1 +} pixelmux_lvb_di1_select_t; + +/** + * @brief lvb di0 pixel data source + */ +typedef enum { + pixelmux_lvb_di0_sel_lcdc0 = 0, + pixelmux_lvb_di0_sel_lcdc1 +} pixelmux_lvb_di0_select_t; + +/** + * @brief mipi dsi1 pixel data source + */ +typedef enum { + pixelmux_mipi_dsi1_sel_lcdc0 = 0, + pixelmux_mipi_dsi1_sel_lcdc1 +} pixelmux_mipi_dsi1_select_t; + +/** + * @brief mipi dsi0 pixel data source + */ +typedef enum { + pixelmux_mipi_dsi0_sel_lcdc0 = 0, + pixelmux_mipi_dsi0_sel_lcdc1 +} pixelmux_mipi_dsi0_select_t; + +/** + * @brief cam1 pixel data source + */ +typedef enum { + pixelmux_cam1_sel_dvp = 0, + pixelmux_cam1_sel_mipi_csi0, + pixelmux_cam1_sel_mipi_csi1, + pixelmux_cam1_sel_lcdc0, + pixelmux_cam1_sel_lcdc1, + pixelmux_cam1_sel_lcb_do0, + pixelmux_cam1_sel_lcb_do1, +} pixelmux_cam1_select_t; + +/** + * @brief cam0 pixel data source + */ +typedef enum { + pixelmux_cam0_sel_dvp = 0, + pixelmux_cam0_sel_mipi_csi0, + pixelmux_cam0_sel_mipi_csi1, + pixelmux_cam0_sel_lcdc0, + pixelmux_cam0_sel_lcdc1, + pixelmux_cam0_sel_lcb_do0, + pixelmux_cam0_sel_lcb_do1, +} pixelmux_cam0_select_t; + +#define PIXELMUX_LVDS_TX_PHY_PFD_FREQ_MAX 40000000UL +#define PIXELMUX_LVDS_TX_PHY_PFD_FREQ_MIN 10000000UL + +#define PIXELMUX_LVDS_TX_PHY_VCO_FREQ_MAX 4000000000UL +#define PIXELMUX_LVDS_TX_PHY_VCO_FREQ_MIN 2000000000UL + +#define PIXELMUX_LVDS_TX_PHY_DATA_LANE_FREQ_MAX 1000000000UL + +typedef struct lvds_phy_clk_reg { + uint32_t rate_lvds; /*!< rate_lvds[1:0] */ + uint32_t data_rate_div4; + uint32_t refclk_div; /*!< refclk_div[3:0] */ + uint32_t pll_div; /*!< pll_div[14:0] */ +} lvds_phy_clk_reg_t; + +typedef struct lvds_phy_clk_param { + lvds_phy_clk_reg_t reg; + uint32_t fvco_freq_hz; + uint32_t pfd_freq_hz; + uint32_t lane_data_rate_hz; + uint32_t hsclk_freq_hz; +} lvds_phy_clk_param_t; + +typedef enum pixelmux_tx_phy_mode { + pixelmux_tx_phy_mode_gpio = 0, + pixelmux_tx_phy_mode_lvds = 1, + pixelmux_tx_phy_mode_mipi = 2 +} pixelmux_tx_phy_mode_t; + +typedef enum pixelmux_rx_phy_mode { + pixelmux_rx_phy_mode_gpio = 0, + pixelmux_rx_phy_mode_lvds = 1, + pixelmux_rx_phy_mode_mipi = 2, + pixelmux_rx_phy_mode_lvds_camera = 3 +} pixelmux_rx_phy_mode_t; + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief select pixel data source and enable for rgb interface + * + * @param[in] src rgb pixel data source options + */ +void pixelmux_rgb_data_source_enable(pixelmux_rgb_select_t src); + +/** + * @brief disable rgb interface pixel data source + */ +void pixelmux_rgb_data_source_disable(void); + +/** + * @brief select pixel data source and enable for gwc1 + * + * @param[in] src gwc1 pixel data source options + */ +void pixelmux_gwc1_data_source_enable(pixelmux_gwc1_select_t src); + +/** + * @brief disable gwc1 pixel data source + */ +void pixelmux_gwc1_data_source_disable(void); + +/** + * @brief select pixel data source and enable for gwc0 + * + * @param[in] src gwc0 pixel data source options + */ +void pixelmux_gwc0_data_source_enable(pixelmux_gwc0_select_t src); + +/** + * @brief disable gwc0 pixel data source + */ +void pixelmux_gwc0_data_source_disable(void); + +/** + * @brief select pixel data source and enable for lvb di1 + * + * @param[in] src lvb di1 pixel data source options + */ +void pixelmux_lvb_di1_data_source_enable(pixelmux_lvb_di1_select_t src); + +/** + * @brief disable lvb di1 pixel data source + */ +void pixelmux_lvb_di1_data_source_disable(void); + +/** + * @brief select pixel data source and enable for lvb di0 + * + * @param[in] src lvb di0 pixel data source options + */ +void pixelmux_lvb_di0_data_source_enable(pixelmux_lvb_di0_select_t src); + +/** + * @brief disable lvb di0 pixel data source + */ +void pixelmux_lvb_di0_data_source_disable(void); + +/** + * @brief select pixel data source and enable for mipi dsi1 + * + * @param[in] src mipi dsi1 pixel data source options + */ +void pixelmux_mipi_dsi1_data_source_enable(pixelmux_mipi_dsi1_select_t src); + +/** + * @brief disable mipi dis1 pixel data source + */ +void pixelmux_mipi_dsi1_data_source_disable(void); + +/** + * @brief select pixel data source and enable for mipi dsi0 + * + * @param[in] src mipi dsi0 pixel data source options + */ +void pixelmux_mipi_dsi0_data_source_enable(pixelmux_mipi_dsi0_select_t src); + +/** + * @brief disable mipi dsi0 pixel data source + */ +void pixelmux_mipi_dsi0_data_source_disable(void); + +/** + * @brief select pixel data source and enable for camera1 + * + * @param[in] src camera1 pixel data source options + */ +void pixelmux_cam1_data_source_enable(pixelmux_cam1_select_t src); + +/** + * @brief disable camera1 pixel data source + */ +void pixelmux_cam1_data_source_disable(void); + +/** + * @brief select pixel data source and enable for camera0 + * + * @param[in] src camera0 pixel data source options + */ +void pixelmux_cam0_data_source_enable(pixelmux_cam0_select_t src); + +/** + * @brief disable camera0 pixel data source + */ +void pixelmux_cam0_data_source_disable(void); + +/** + * @brief calculate pll config base pixel frequency + * + * @param[in] pixel_freq_hz lcdc pixel frequency + * @param[in] is_split 1: enable split mode, 0: disable split mode + * @param[out] param use for lvds phy config + * @return status + */ +hpm_stat_t pixelmux_lvds_phy_calc_pll_cfg(uint32_t pixel_freq_hz, bool is_split, lvds_phy_clk_param_t *param); + +/** + * @brief config tx phy0 mode + * + * @param[in] mode phy mode + */ +void pixelmux_config_tx_phy0_mode(pixelmux_tx_phy_mode_t mode); + +/** + * @brief config tx phy1 mode + * + * @param[in] mode phy mode + */ +void pixelmux_config_tx_phy1_mode(pixelmux_tx_phy_mode_t mode); + +/** + * @brief config lvds tx phy0 clock + * + * @param[in] clk_reg phy register config + */ +void pixelmux_config_lvds_tx_phy0_clk(const lvds_phy_clk_reg_t *clk_reg); + +/** + * @brief config lvds tx phy1 clock + * + * @param[in] clk_reg phy register config + */ +void pixelmux_config_lvds_tx_phy1_clk(const lvds_phy_clk_reg_t *clk_reg); + +/** + * @brief config rx phy0 mode + * + * @param[in] mode phy mode + */ +void pixelmux_config_rx_phy0_mode(pixelmux_rx_phy_mode_t mode); + +/** + * @brief config rx phy1 mode + * + * @param[in] mode phy mode + */ +void pixelmux_config_rx_phy1_mode(pixelmux_rx_phy_mode_t mode); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ +#endif /* HPM_PIXELMUX_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pla_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pla_drv.h index f3be449bfdd..33f7f814d55 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pla_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pla_drv.h @@ -275,7 +275,7 @@ extern "C" { * @brief Configure one channel of aoi_16to8 * * @param pla @ref PLA_Type - * @param cfg @ref pla_aoi_16to8_cfg_t + * @param cfg @ref pla_aoi_16to8_chn_cfg_t */ void pla_set_aoi_16to8_one_channel(PLA_Type * pla, pla_aoi_16to8_chn_cfg_t *cfg); @@ -353,7 +353,7 @@ void pla_get_aoi_8to7_one_channel(PLA_Type *pla, * * @param pla @ref PLA_Type * @param chn @ref pla_channel_type_t - * @param aoi_16to8_chn @ref pla_aoi_8to7_channel_type_t + * @param aoi_8to7_chn @ref pla_aoi_8to7_channel_type_t * @param cfg @ref pla_aoi_8to7_cfg_unit_t */ void pla_set_aoi_8to7_input_signal(PLA_Type *pla, diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_plb_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_plb_drv.h new file mode 100644 index 00000000000..e85fc2821ff --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_plb_drv.h @@ -0,0 +1,237 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PLB_DRV_H +#define HPM_PLB_DRV_H + +#include "hpm_common.h" +#include "hpm_plb_regs.h" + +/** + * @brief PLB driver APIs + * @defgroup plb_interface PLB driver APIs + * @ingroup io_interfaces + * @{ + */ + +#define PLB_SLICE_MASK (0xf) +#define PLB_SLICE_HIGH_BIT_MASK_SET(slice) (PLB_SLICE_MASK << ((slice - plb_type_b_slice_8) << 2)) +#define PLB_SLICE_HIGH_BIT_SHIFT(slice) ((slice - plb_type_b_slice_8) << 2) +#define PLB_SLICE_LOW_BIT_MASK_SET(slice) (PLB_SLICE_MASK << (slice << 2)) +#define PLB_SLICE_LOW_BIT_SHIFT(slice) (slice << 2) + +/** + * @brief plb channels + * + */ +typedef enum plb_chn { + plb_chn0 = 0, + plb_chn1 = 1, + plb_chn2 = 2, + plb_chn3 = 3, +} plb_chn_t; + +/** + * @brief PLB look-up table unit + * + */ +typedef enum plb_type_a_lut_num { + plb_type_a_table0 = PLB_TYPE_A_0, + plb_type_a_table1 = PLB_TYPE_A_1, + plb_type_a_table2 = PLB_TYPE_A_2, + plb_type_a_table3 = PLB_TYPE_A_3, +} plb_type_a_lut_num_t; + +/** + * @brief PLB truth table configuration unit + * + */ +typedef union { + struct { + uint16_t index0_1bit_out: 1; + uint16_t index1_1bit_out: 1; + uint16_t index2_1bit_out: 1; + uint16_t index3_1bit_out: 1; + uint16_t index4_1bit_out: 1; + uint16_t index5_1bit_out: 1; + uint16_t index6_1bit_out: 1; + uint16_t index7_1bit_out: 1; + uint16_t index8_1bit_out: 1; + uint16_t index9_1bit_out: 1; + uint16_t index10_1bit_out: 1; + uint16_t index11_1bit_out: 1; + uint16_t index12_1bit_out: 1; + uint16_t index13_1bit_out: 1; + uint16_t index14_1bit_out: 1; + uint16_t index15_1bit_out: 1; + }; + uint16_t val; +} plb_type_a_truth_t; + +/** + * @brief Index of slice + * + */ +typedef enum plb_type_b_lut_slice { + plb_type_b_slice_0 = 0, + plb_type_b_slice_1 = 1, + plb_type_b_slice_2 = 2, + plb_type_b_slice_3 = 3, + plb_type_b_slice_4 = 4, + plb_type_b_slice_5 = 5, + plb_type_b_slice_6 = 6, + plb_type_b_slice_7 = 7, + plb_type_b_slice_8 = 8, + plb_type_b_slice_9 = 9, + plb_type_b_slice_10 = 10, + plb_type_b_slice_11 = 11, + plb_type_b_slice_12 = 12, + plb_type_b_slice_13 = 13, + plb_type_b_slice_14 = 14, + plb_type_b_slice_15 = 15, +} plb_type_b_lut_slice_t; + +/** + * @brief Configuration of slice + * + */ +typedef enum plb_type_b_slice_opt { + plb_slice_opt_keep = 0, /**< The data unit keeps the value of the previous cycle */ + plb_slice_opt_get_cmp0_val = 1, /**< The data unit will take the value of the cmp0 register as the value for the next cycle */ + plb_slice_opt_get_cmp1_val = 2, /**< The data unit will take the value of the cmp1 register as the value for the next cycle */ + plb_slice_opt_get_cmp2_val = 3, /**< The data unit will take the value of the cmp2 register as the value for the next cycle */ + plb_slice_opt_add_one = 4, /**< The next cycle value of the data cell is the current value plus 1 */ + plb_slice_opt_add_two = 5, /**< The next cycle value of the data cell is the current value plus 2 */ + plb_slice_opt_sub_one = 6, /**< The next cycle value of the data cell is the current value minus 1 */ + plb_slice_opt_sub_two = 7, /**< The next cycle value of the data cell is the current value minus 2 */ + plb_slice_opt_shift_left = 4 << 8, /**< The value of the next cycle of the data cell is shifted one place to the left of the current value */ + plb_slice_opt_shift_left_add_one = 5 << 8, /**< The next cycle value of the data cell is the current value shifted one place to the left, with the lower bit complemented by one */ + plb_slice_opt_shift_right = 6 << 8, /**< The value of the next cycle of the data cell is shifted one place to the right of the current value */ + plb_slice_opt_shift_right_add_one = 7 << 8, /**< The next cycle value of the data cell is the current value shifted one place to the right, with the lower bit complemented by one */ +} plb_type_b_slice_opt_t; + +/** + * @brief Comparator index + * + */ +typedef enum plb_type_b_cmp { + plb_type_b_cmp0 = PLB_TYPE_B_CMP_0, + plb_type_b_cmp1 = PLB_TYPE_B_CMP_1, + plb_type_b_cmp2 = PLB_TYPE_B_CMP_2, + plb_type_b_cmp3 = PLB_TYPE_B_CMP_3, +} plb_type_b_cmp_t; + +/** + * @brief Comparator operation + * + */ +typedef enum plb_type_b_cmp_mode { + plb_cmp_mode_out_zero = 0, /**< output zero */ + plb_cmp_mode_out_one = 1, /**< output one */ + plb_cmp_mode_gt = 2, /**< Data unit greater than cmp output one, otherwise output zero */ + plb_cmp_mode_lt = 3, /**< Data unit less than cmp output one, otherwise output zero */ + plb_cmp_mode_eq = 4, /**< Data unit equal to cmp output one, otherwise output zero */ + plb_cmp_mode_ne = 5, /**< Data unit not equal to cmp output one, otherwise output zero */ + plb_cmp_mode_ge = 6, /**< Data unit greater than or equal to cmp output one, otherwise output zero */ + plb_cmp_mode_le = 7, /**< Data unit less than or equal to cmp output one, otherwise output zero */ + plb_cmp_mode_and_mask = 10, /**< The data cell corresponding to the bit set to one by cmp is and */ + plb_cmp_mode_or_mask = 11, /**< The data cell corresponding to the bit set to one by cmp is or */ + plb_cmp_mode_xor_mask = 12, /**< The data cell corresponding to the bit set to one by cmp is xor */ + plb_cmp_mode_nand_mask = 13, /**< The data cell corresponding to the bit set to one by cmp is nand */ + plb_cmp_mode_nor_mask = 14, /**< The data cell corresponding to the bit set to one by cmp is nor */ + plb_cmp_mode_xnor_mask = 15, /**< The data cell corresponding to the bit set to one by cmp is xnor */ +} plb_type_b_cmp_mode_t; + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Configuring the truth table for lookup tables + * + * @param plb @ref PLB_Type plb base + * @param chn @ref plb_chn_t + * @param lut_num @ref plb_type_a_lut_num_t + * @param truth @ref plb_type_a_truth_t + */ +static inline void plb_type_a_set_lut(PLB_Type *plb, plb_chn_t chn, plb_type_a_lut_num_t lut_num, plb_type_a_truth_t *truth) +{ + plb->TYPE_A[chn].LOOKUP_TABLE[lut_num] = PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_SET(truth->val); +} + +/** + * @brief The software injects a cycle value into the TYPE A channel. + * + * @param plb @ref PLB_Type plb base + * @param chn @ref plb_chn_t + * @param inject_val Injected values + */ +static inline void plb_type_a_inject_by_sw(PLB_Type *plb, plb_chn_t chn, uint8_t inject_val) +{ + plb->TYPE_A[chn].SW_INJECT = PLB_TYPE_A_SW_INJECT_SW_INJECT_SET(inject_val); +} + +/** + * @brief Configure the value of the CMP + * + * @param plb @ref PLB_Type plb base + * @param chn @ref plb_chn_t + * @param cmp_index @ref plb_type_b_cmp_t + * @param val CMP value + */ +static inline void plb_type_b_set_cmp_val(PLB_Type *plb, plb_chn_t chn, plb_type_b_cmp_t cmp_index, uint32_t val) +{ + plb->TYPE_B[chn].CMP[cmp_index] = PLB_TYPE_B_CMP_CMP_VALUE_SET(val); +} + +/** + * @brief Setting the mode of the CMP + * + * @param plb @ref PLB_Type plb base + * @param chn @ref plb_chn_t + * @param cmp_index @ref plb_type_b_cmp_t + * @param cmp_mode @ref plb_type_b_cmp_mode_t + */ +static inline void plb_type_b_set_cmp_mode(PLB_Type *plb, plb_chn_t chn, plb_type_b_cmp_t cmp_index, plb_type_b_cmp_mode_t cmp_mode) +{ + plb->TYPE_B[chn].MODE = (plb->TYPE_B[chn].MODE & (~(PLB_TYPE_B_MODE_OUT0_SEL_MASK << (cmp_index << 2)))) | + ((PLB_TYPE_B_MODE_OUT0_SEL_MASK & cmp_mode) << (cmp_index << 2)); +} + +/** + * @brief Software injection values + * + * @param plb @ref PLB_Type plb base + * @param chn @ref plb_chn_t + * @param val value + */ +static inline void plb_type_b_inject_by_sw(PLB_Type *plb, plb_chn_t chn, uint32_t val) +{ + plb->TYPE_B[chn].SW_INJECT = val; +} + +/** + * @brief Configuring the PLB type_b's lookup table + * + * @param plb @ref PLB_Type plb base + * @param chn @ref plb_chn_t + * @param slice @ref plb_type_b_lut_slice_t + * @param opt @ref plb_type_b_slice_opt_t + */ +void plb_type_b_set_lut(PLB_Type *plb, plb_chn_t chn, plb_type_b_lut_slice_t slice, plb_type_b_slice_opt_t opt); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* HPM_PLB_DRV_H */ + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pllctl_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pllctl_drv.h index fcfd3215bf6..c601e88f4db 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pllctl_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pllctl_drv.h @@ -219,7 +219,7 @@ static inline hpm_stat_t pllctl_set_postdiv1(PLLCTL_Type *ptr, uint8_t pll, uint static inline hpm_stat_t pllctl_set_fbdiv_int(PLLCTL_Type *ptr, uint8_t pll, uint16_t fbdiv) { if ((pll > (PLLCTL_SOC_PLL_MAX_COUNT - 1)) - || ((fbdiv - 1) > (PLLCTL_PLL_CFG2_FBDIV_INT_MASK >> PLLCTL_PLL_CFG2_FBDIV_INT_SHIFT))) { + || ((fbdiv - 1) > (uint16_t)(PLLCTL_PLL_CFG2_FBDIV_INT_MASK >> PLLCTL_PLL_CFG2_FBDIV_INT_SHIFT))) { return status_invalid_argument; } @@ -242,7 +242,7 @@ static inline hpm_stat_t pllctl_set_fbdiv_int(PLLCTL_Type *ptr, uint8_t pll, uin static inline hpm_stat_t pllctl_set_fbdiv_frac(PLLCTL_Type *ptr, uint8_t pll, uint16_t fbdiv) { if ((pll > (PLLCTL_SOC_PLL_MAX_COUNT - 1)) - || ((fbdiv - 1) > (PLLCTL_PLL_FREQ_FBDIV_FRAC_MASK >> PLLCTL_PLL_FREQ_FBDIV_FRAC_SHIFT))) { + || ((fbdiv - 1) > (uint16_t) (PLLCTL_PLL_FREQ_FBDIV_FRAC_MASK >> PLLCTL_PLL_FREQ_FBDIV_FRAC_SHIFT))) { return status_invalid_argument; } @@ -307,7 +307,7 @@ static inline hpm_stat_t pllctl_set_div(PLLCTL_Type *ptr, uint8_t pll, uint8_t d { if ((pll > (PLLCTL_SOC_PLL_MAX_COUNT - 1)) || !(PLLCTL_SOC_PLL_HAS_DIV0(pll)) - || ((div - 1) > (PLLCTL_PLL_DIV0_DIV_MASK >> PLLCTL_PLL_DIV0_DIV_SHIFT))) { + || ((div - 1) > (uint16_t) (PLLCTL_PLL_DIV0_DIV_MASK >> PLLCTL_PLL_DIV0_DIV_SHIFT))) { return status_invalid_argument; } @@ -389,6 +389,17 @@ static inline void pllctl_xtal_set_rampup_time(PLLCTL_Type *ptr, uint32_t cycles ptr->XTAL = (ptr->XTAL & ~PLLCTL_XTAL_RAMP_TIME_MASK) | PLLCTL_XTAL_RAMP_TIME_SET(cycles); } +/** + * @brief Set pll work mode + * + * @param[in] ptr PLLCTL base address + * @param[in] pll Target PLL index + * @param[in] int_mode true: integer mode, false - fraction mode + * + * @return status_success if everything is okay + */ +hpm_stat_t pllctl_set_pll_work_mode(PLLCTL_Type *ptr, uint8_t pll, bool int_mode); + /** * @brief Set refdiv * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pllctlv2_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pllctlv2_drv.h index cbc85cfb5fb..7608202b937 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pllctlv2_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pllctlv2_drv.h @@ -60,7 +60,7 @@ static inline void pllctlv2_xtal_set_rampup_time(PLLCTLV2_Type *ptr, uint32_t rc */ static inline bool pllctlv2_pll_is_stable(PLLCTLV2_Type *ptr, uint8_t pll) { - return IS_HPM_BITMASK_SET(ptr->PLL[pll].MFI, PLLCTLV2_PLL_MFI_BUSY_MASK); + return IS_HPM_BITMASK_SET(ptr->PLL[pll].MFI, PLLCTLV2_PLL_MFI_RESPONSE_MASK); } /** diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pmp_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pmp_drv.h index 0e514c91743..2bb58051c00 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pmp_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pmp_drv.h @@ -8,6 +8,7 @@ #define HPM_PMP_DRV_H #include "hpm_common.h" +#include "hpm_soc_feature.h" /** * @brief PMP Entry structure @@ -26,6 +27,7 @@ typedef struct pmp_entry_struct { } pmp_cfg; uint8_t reserved0[3]; uint32_t pmp_addr; +#if (!defined(PMP_SUPPORT_PMA)) || (defined(PMP_SUPPORT_PMA) && (PMP_SUPPORT_PMA == 1)) union { struct { uint8_t entry_addr_matching_mode: 2; @@ -37,6 +39,7 @@ typedef struct pmp_entry_struct { } pma_cfg; uint8_t reserved1[3]; uint32_t pma_addr; +#endif } pmp_entry_t; /** @@ -134,13 +137,6 @@ extern "C" { */ void write_pmp_cfg(uint32_t value, uint32_t idx); -/** - * @brief Write PMA Configuration to corresponding PMA_CFG register - * @param value PMA configuration - * @param idx PMA entry index, valid value is 0-15 - */ -void write_pma_cfg(uint32_t value, uint32_t idx); - /** * @brief Read PMP configuration * @param idx PMP entry index @@ -148,6 +144,22 @@ void write_pma_cfg(uint32_t value, uint32_t idx); */ uint32_t read_pmp_cfg(uint32_t idx); + +/** + * @brief Write PMP address to corresponding PMP_ADDR register + * @param value PMP address + * @param idx PMP address entry index, valid value is 0-15 + */ +void write_pmp_addr(uint32_t value, uint32_t idx); + +/** + * @brief Read PMP address entry + * @param idx PMP address entry index + * @return PMP address + */ +uint32_t read_pmp_addr(uint32_t idx); + +#if (!defined(PMP_SUPPORT_PMA)) || (defined(PMP_SUPPORT_PMA) && (PMP_SUPPORT_PMA == 1)) /** * @brief Read PMA configuration * @param idx PMA entry index @@ -156,11 +168,11 @@ uint32_t read_pmp_cfg(uint32_t idx); uint32_t read_pma_cfg(uint32_t idx); /** - * @brief Write PMP address to corresponding PMP_ADDR register - * @param value PMP address - * @param idx PMP address entry index, valid value is 0-15 + * @brief Write PMA Configuration to corresponding PMA_CFG register + * @param value PMA configuration + * @param idx PMA entry index, valid value is 0-15 */ -void write_pmp_addr(uint32_t value, uint32_t idx); +void write_pma_cfg(uint32_t value, uint32_t idx); /** * @brief Write PMA address to corresponding PMA_ADDR register @@ -169,20 +181,13 @@ void write_pmp_addr(uint32_t value, uint32_t idx); */ void write_pma_addr(uint32_t value, uint32_t idx); -/** - * @brief Read PMP address entry - * @param idx PMP address entry index - * @return PMP address - */ -uint32_t read_pmp_addr(uint32_t idx); - /** * @brief Read PMA address entry * @param idx PMA address entry index, valid value is 0-15 * @return PMA address */ uint32_t read_pma_addr(uint32_t idx); - +#endif /* #if (!defined(PMP_SUPPORT_PMA)) || (defined(PMP_SUPPORT_PMA) && (PMP_SUPPORT_PMA == 1)) */ /** * @brief Configure PMP and PMA for specified PMP/PMA entry diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ptpc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ptpc_drv.h index 5e9d06d1fd1..2dce934fc43 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ptpc_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ptpc_drv.h @@ -290,7 +290,7 @@ static inline uint32_t ptpc_get_capture_second(PTPC_Type *ptr, uint8_t index) */ static inline void ptpc_clear_irq_status(PTPC_Type *ptr, uint32_t mask) { - ptr->INT_STS |= mask; + ptr->INT_STS = mask; } /** diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pwm_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pwm_drv.h index deb4995222d..03dffb9ef5f 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pwm_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pwm_drv.h @@ -10,6 +10,7 @@ #include "hpm_common.h" #include "hpm_pwm_regs.h" +#include "hpm_soc_feature.h" /** * @brief PWM driver APIs * @defgroup pwm_interface PWM driver APIs @@ -132,7 +133,7 @@ typedef enum pwm_output_type { typedef struct pwm_cmp_config { uint32_t cmp; /**< compare value */ bool enable_ex_cmp; /**< enable extended compare value */ -#if PWM_SOC_HRPWM_SUPPORT +#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT bool enable_hrcmp; /**< enable high precision pwm */ #endif uint8_t mode; /**< compare work mode: pwm_cmp_mode_output_compare or pwm_cmp_mode_input_capture */ @@ -140,7 +141,7 @@ typedef struct pwm_cmp_config { uint8_t ex_cmp; /**< extended compare value */ uint8_t half_clock_cmp; /**< half clock compare value*/ uint8_t jitter_cmp; /**< jitter compare value */ -#if PWM_SOC_HRPWM_SUPPORT +#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT uint8_t hrcmp; /**< high precision pwm */ #endif } pwm_cmp_config_t; @@ -159,10 +160,11 @@ typedef struct pwm_output_channel { * */ typedef struct pwm_fault_source_config { - uint32_t source_mask; /**< fault source mask*/ - bool fault_recover_at_rising_edge; /**< recover fault at rising edge */ - bool external_fault_active_low; /**< active external fault by low */ - uint8_t fault_output_recovery_trigger; /**< fault output recoverty trigger */ + uint32_t source_mask; /**< fault source mask*/ + bool fault_recover_at_rising_edge; /**< recover fault at rising edge */ + bool fault_external_0_active_low; /**< active external fault0 by low */ + bool fault_external_1_active_low; /**< active external fault1 by low */ + uint8_t fault_output_recovery_trigger; /**< fault output recoverty trigger */ } pwm_fault_source_config_t; /** @@ -170,6 +172,9 @@ typedef struct pwm_fault_source_config { * */ typedef struct pwm_config { +#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT + bool hrpwm_update_mode; /**< mode one or zero, HR CMP update timing */ +#endif bool enable_output; /**< enable pwm output */ bool invert_output; /**< invert pwm output level */ uint8_t update_trigger; /**< pwm config update trigger */ @@ -191,6 +196,33 @@ typedef struct pwm_pair_config { extern "C" { #endif +/** + * @brief pwm deinitialize function + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * + */ +static inline void pwm_deinit(PWM_Type *pwm_x) +{ + pwm_x->IRQEN = 0; + pwm_x->DMAEN = 0; + pwm_x->SR |= pwm_x->SR; + pwm_x->STA = 0; + pwm_x->RLD = PWM_RLD_RLD_MASK; + for (uint8_t i = 0; i < PWM_SOC_CMP_MAX_COUNT; i++) { + pwm_x->CMP[i] = PWM_CMP_CMP_MASK; + pwm_x->CMPCFG[i] = 0; + pwm_x->CHCFG[i] = PWM_CHCFG_CMPSELEND_SET(PWM_SOC_CMP_MAX_COUNT - 1) | PWM_CHCFG_CMPSELBEG_SET(PWM_SOC_CMP_MAX_COUNT - 1); + } + pwm_x->FRCMD = 0; + pwm_x->GCR = 0; + pwm_x->SHCR = 0; + pwm_x->HRPWM_CFG = 0; + for (uint8_t i = 0; i < PWM_SOC_OUTPUT_TO_PWM_MAX_COUNT; i++) { + pwm_x->PWMCFG[i] = 0; + } +} + /** * @brief issue all shawdow register * @@ -244,7 +276,7 @@ static inline void pwm_set_start_count(PWM_Type *pwm_x, | PWM_STA_STA_SET(start); } -#if PWM_SOC_HRPWM_SUPPORT +#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT /** * @brief set hrpwm counter start value @@ -276,7 +308,7 @@ static inline void pwm_set_reload(PWM_Type *pwm_x, | PWM_RLD_RLD_SET(reload); } -#if PWM_SOC_HRPWM_SUPPORT +#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT /** * @brief set the hr pwm reload value @@ -312,7 +344,7 @@ static inline void pwm_clear_status(PWM_Type *pwm_x, uint32_t mask) pwm_x->SR |= mask; } -#if PWM_SOC_TIMER_RESET_SUPPORT +#if defined(PWM_SOC_TIMER_RESET_SUPPORT) && PWM_SOC_TIMER_RESET_SUPPORT /** * @brief Reset timer and extension timer @@ -462,7 +494,20 @@ static inline void pwm_load_cmp_shadow_on_capture(PWM_Type *pwm_x, | PWM_GCR_HWSHDWEDG_SET(is_falling_edge)); } -#if PWM_SOC_SHADOW_TRIG_SUPPORT +#if defined(PWM_SOC_SHADOW_TRIG_SUPPORT) && PWM_SOC_SHADOW_TRIG_SUPPORT + +/** + * @brief RLD, STA shadow registers take effect at the reload point + * + * @param pwm_x pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param is_enable true or false + */ +static inline void pwm_set_cnt_shadow_trig_reload(PWM_Type *pwm_x, bool is_enable) +{ + pwm_x->SHCR = ((pwm_x->SHCR & ~PWM_SHCR_CNT_UPDATE_RELOAD_MASK) + | PWM_SHCR_CNT_UPDATE_RELOAD_SET(is_enable)); +} + /** * @brief Set the timer shadow register to update the trigger edge * @@ -543,7 +588,7 @@ static inline void pwm_cmp_update_cmp_value(PWM_Type *pwm_x, uint8_t index, | PWM_CMP_CMP_SET(cmp) | PWM_CMP_XCMP_SET(ex_cmp); } -#if PWM_SOC_HRPWM_SUPPORT +#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT /** * @brief update high-precision cmp value * @@ -583,20 +628,20 @@ static inline void pwm_config_cmp(PWM_Type *pwm_x, uint8_t index, pwm_cmp_config { pwm_shadow_register_unlock(pwm_x); if (config->mode == pwm_cmp_mode_output_compare) { -#if PWM_SOC_HRPWM_SUPPORT +#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT if (config->enable_hrcmp) { pwm_x->CMPCFG[index] = PWM_CMPCFG_CMPSHDWUPT_SET(config->update_trigger); pwm_x->CMP[index] = PWM_CMP_HRPWM_CMP_SET(config->cmp) | PWM_CMP_HRPWM_CMP_HR_SET(config->hrcmp); } else { #endif - pwm_x->CMPCFG[index] = PWM_CMPCFG_XCNTCMPEN_SET(config->enable_ex_cmp) + pwm_x->CMPCFG[index] = (config->enable_ex_cmp ? PWM_CMPCFG_XCNTCMPEN_MASK : 0) | PWM_CMPCFG_CMPSHDWUPT_SET(config->update_trigger); pwm_x->CMP[index] = PWM_CMP_CMP_SET(config->cmp) | PWM_CMP_XCMP_SET(config->ex_cmp) | PWM_CMP_CMPHLF_SET(config->half_clock_cmp) | PWM_CMP_CMPJIT_SET(config->jitter_cmp); -#if PWM_SOC_HRPWM_SUPPORT +#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT } #endif } else { @@ -632,7 +677,7 @@ static inline void pwm_config_fault_source(PWM_Type *pwm_x, pwm_fault_source_con | PWM_GCR_FAULTRECEDG_MASK | PWM_GCR_FAULTEXPOL_MASK | PWM_GCR_FAULTRECHWSEL_MASK)) | config->source_mask - | PWM_GCR_FAULTEXPOL_SET(config->external_fault_active_low) + | PWM_GCR_FAULTEXPOL_SET((config->fault_external_0_active_low ? 0x1 : 0) | (config->fault_external_1_active_low ? 0x2 : 0)) | PWM_GCR_FAULTRECEDG_SET(config->fault_recover_at_rising_edge) | PWM_GCR_FAULTRECHWSEL_SET(config->fault_output_recovery_trigger); } @@ -645,6 +690,7 @@ static inline void pwm_config_fault_source(PWM_Type *pwm_x, pwm_fault_source_con static inline void pwm_clear_fault(PWM_Type *pwm_x) { pwm_x->GCR |= PWM_GCR_FAULTCLR_MASK; + pwm_x->GCR &= ~PWM_GCR_FAULTCLR_MASK; } /** @@ -796,9 +842,56 @@ static inline void pwm_config_pwm(PWM_Type *pwm_x, uint8_t index, | PWM_PWMCFG_FAULTRECTIME_SET(config->fault_recovery_trigger) | PWM_PWMCFG_FRCSRCSEL_SET(config->force_source) | PWM_PWMCFG_PAIR_SET(enable_pair_mode) +#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT + | PWM_PWMCFG_HR_UPDATE_MODE_SET(config->hrpwm_update_mode) +#endif | PWM_PWMCFG_DEADAREA_SET(config->dead_zone_in_half_cycle); } +/** + * @brief getting the counter reload value for a pwm timer + * + * @param pwm_x PWM base address, HPM_PWMx(x=0..n) + * @retval pwm reload value + */ +static inline uint32_t pwm_get_reload_val(PWM_Type *pwm_x) +{ + return PWM_RLD_RLD_GET(pwm_x->RLD); +} + +/** + * @brief getting the extended counter reload value for a pwm timer + * + * @param pwm_x PWM base address, HPM_PWMx(x=0..n) + * @retval pwm extended reload value + */ +static inline uint32_t pwm_get_ex_reload_val(PWM_Type *pwm_x) +{ + return PWM_RLD_XRLD_GET(pwm_x->RLD); +} + +/** + * @brief getting the value of the pwm counter + * + * @param pwm_x PWM base address, HPM_PWMx(x=0..n) + * @retval pwm counter value + */ +static inline uint32_t pwm_get_counter_val(PWM_Type *pwm_x) +{ + return PWM_CNT_CNT_GET(pwm_x->CNT); +} + +/** + * @brief getting the value of the pwm extended counter + * + * @param pwm_x PWM base address, HPM_PWMx(x=0..n) + * @retval pwm counter value + */ +static inline uint32_t pwm_get_ex_counter_val(PWM_Type *pwm_x) +{ + return PWM_CNT_XCNT_GET(pwm_x->CNT); +} + /** * @brief pwm load cmp shadow on match * @@ -906,7 +999,7 @@ hpm_stat_t pwm_update_raw_cmp_edge_aligned(PWM_Type *pwm_x, uint8_t cmp_index, */ hpm_stat_t pwm_update_raw_cmp_central_aligned(PWM_Type *pwm_x, uint8_t cmp1_index, uint8_t cmp2_index, uint32_t target_cmp1, uint32_t target_cmp2); -#if PWM_SOC_HRPWM_SUPPORT +#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT /** * @brief Enable high-precision pwm * @@ -972,6 +1065,29 @@ static inline uint32_t pwm_get_cal_hrpwm_status(PWM_Type *pwm_x, uint8_t chn) return PWM_ANASTS_CALON_GET(pwm_x->ANASTS[chn]); } +/** + * @brief getting the counter reload value for hrpwm counter + * + * @param pwm_x pwm_x @ref PWM_Type PWM base address + * @return uint32_t hrpwm reload + */ +static inline uint32_t pwm_get_hrpwm_reload_val(PWM_Type *pwm_x) +{ + return PWM_RLD_HRPWM_RLD_GET(pwm_x->RLD_HRPWM); +} + +/** + * @brief getting the counter reload value for hrpwm hr counter + * + * @param pwm_x pwm_x @ref PWM_Type PWM base address + * @return uint32_t hrpwm hr reload + */ +static inline uint32_t pwm_get_hrpwm_hr_reload_val(PWM_Type *pwm_x) +{ + return PWM_RLD_HRPWM_RLD_HR_GET(pwm_x->RLD_HRPWM); +} + + /** * @brief update raw high-precision compare value for edge aligned waveform * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_qei_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_qei_drv.h index 6b52d498bab..0388eb74e54 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_qei_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_qei_drv.h @@ -361,6 +361,50 @@ static inline uint32_t qei_get_current_count(QEI_Type *qei_x, return *(&qei_x->COUNT[QEI_COUNT_CURRENT].Z + type); } +/** + * @brief get current phcnt value + * + * @param qei_x QEI base address, HPM_QEIx(x=0...n) + * @return phcnt value + */ +static inline uint32_t qei_get_current_phase_phcnt(QEI_Type *qei_x) +{ + return QEI_COUNT_PH_PHCNT_GET(qei_get_current_count(qei_x, qei_counter_type_phase)); +} + +/** + * @brief get current a phase status + * + * @param qei_x QEI base address, HPM_QEIx(x=0...n) + * @return a phase level + */ +static inline bool qei_get_current_phase_astat(QEI_Type *qei_x) +{ + return QEI_COUNT_PH_ASTAT_GET(qei_get_current_count(qei_x, qei_counter_type_phase)); +} + +/** + * @brief get current b phase status + * + * @param qei_x QEI base address, HPM_QEIx(x=0...n) + * @return b phase level + */ +static inline bool qei_get_current_phase_bstat(QEI_Type *qei_x) +{ + return QEI_COUNT_PH_BSTAT_GET(qei_get_current_count(qei_x, qei_counter_type_phase)); +} + +/** + * @brief get current phase dir + * + * @param qei_x QEI base address, HPM_QEIx(x=0...n) + * @return dir + */ +static inline bool qei_get_current_phase_dir(QEI_Type *qei_x) +{ + return QEI_COUNT_PH_DIR_GET(qei_get_current_count(qei_x, qei_counter_type_phase)); +} + /** * @brief get read event count value * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_qeiv2_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_qeiv2_drv.h new file mode 100644 index 00000000000..36cca85e4c0 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_qeiv2_drv.h @@ -0,0 +1,1424 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_QEIV2_DRV_H +#define HPM_QEIV2_DRV_H + +#include "hpm_common.h" +#include "hpm_qeiv2_regs.h" +/** + * @brief QEIV2 driver APIs + * @defgroup qeiv2_interface QEIV2 driver APIs + * @ingroup io_interfaces + * @{ + */ +#define QEIV2_EVENT_WDOG_FLAG_MASK (1U << 31U) /**< watchdog flag */ +#define QEIV2_EVENT_HOME_FLAG_MASK (1U << 30U) /**< home flag */ +#define QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK (1U << 29U) /**< postion compare match flag */ +#define QEIV2_EVENT_Z_PHASE_FLAG_MASK (1U << 28U) /**< z input flag */ +#define QEIV2_EVENT_Z_MISS_FLAG_MASK (1U << 27U) /**< z miss flag */ +#define QEIV2_EVENT_WIDTH_TIME_FLAG_MASK (1U << 26U) /**< width time flag */ +#define QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK (1U << 25U) /**< postion2 compare match flag */ +#define QEIV2_EVENT_DIR_CHG_FLAG_MASK (1U << 24U) /**< direction change flag */ +#define QEIV2_EVENT_CYCLE0_FLAG_MASK (1U << 23U) /**< cycle0 flag */ +#define QEIV2_EVENT_CYCLE1_FLAG_MASK (1U << 22U) /**< cycle1 flag */ +#define QEIV2_EVENT_PULSE0_FLAG_MASK (1U << 21U) /**< pulse0 flag */ +#define QEIV2_EVENT_PULSE1_FLAG_MASK (1U << 20U) /**< pulse1 flag */ +#define QEIV2_EVENT_HOME2_FLAG_MASK (1U << 19U) /**< home2 flag */ +#define QEIV2_EVENT_FAULT_FLAG_MASK (1U << 18U) /**< fault flag */ + +/** + * @brief qeiv2 work mode + * + */ +typedef enum qeiv2_work_mode { + qeiv2_work_mode_abz = 0, /**< Orthogonal decoder mode */ + qeiv2_work_mode_pd = 1, /**< Directional (PD) mode */ + qeiv2_work_mode_ud = 2, /**< Up and Down (UD) mode */ + qeiv2_work_mode_uvw = 3, /**< UVW mode */ + qeiv2_work_mode_single = 4, /**< Single-phase mode */ + qeiv2_work_mode_sin = 5, /**< Single sinewave mode */ + qeiv2_work_mode_sincos = 6, /**< Orthogonal sinewave mode */ +} qeiv2_work_mode_t; + +/** + * @brief spd and tmr read selection + * + */ +typedef enum qeiv2_spd_tmr_content { + qeiv2_spd_tmr_as_spd_tm = 0, /**< spd and timer register as spd and time */ + qeiv2_spd_tmr_as_pos_angle = 1, /**< spd and timer register as position and angle */ +} qeiv2_spd_tmr_content_t; + +/** + * @brief compare match rotate direction + * + */ +typedef enum qeiv2_rotate_dir { + qeiv2_rotate_dir_forward = 0, + qeiv2_rotate_dir_reverse = 1, +} qeiv2_rotate_dir_t; /**< compare match rotate direction */ + +/** + * @brief compare match position direction + * + */ +typedef enum qeiv2_position_dir { + qeiv2_pos_dir_decrease = 0, + qeiv2_pos_dir_increase = 1, +} qeiv2_position_dir_t; /**< compare match position direction */ + +/** + * @brief counting mode of Z-phase counter + * + */ +typedef enum qeiv2_z_count_work_mode { + qeiv2_z_count_inc_on_z_input_assert = 0, /**< zcnt will increment or decrement when Z input assert */ + qeiv2_z_count_inc_on_phase_count_max = 1, /**< zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 */ +} qeiv2_z_count_work_mode_t; + +/** + * @brief counter type + * + */ +typedef enum qeiv2_counter_type { + qeiv2_counter_type_z = 0, /**< Z counter */ + qeiv2_counter_type_phase = 1, /**< Phase counter */ + qeiv2_counter_type_speed = 2, /**< Speed counter */ + qeiv2_counter_type_timer = 3, /**< Timer counter */ +} qeiv2_counter_type_t; + +/** + * @brief filter mode + * + */ +typedef enum qeiv2_filter_mode { + qeiv2_filter_mode_bypass = 0, /**< bypass */ + qeiv2_filter_mode_burr = 4, /**< rapid change mode */ + qeiv2_filter_mode_delay, /**< delay filter mode */ + qeiv2_filter_mode_peak, /**< stable low mode */ + qeiv2_filter_mode_valley, /**< stable high mode */ +} qeiv2_filter_mode_t; + +/** + * @brief filter type + * + */ +typedef enum qeiv2_filter_phase { + qeiv2_filter_phase_a = 0, /**< filter phase a */ + qeiv2_filter_phase_b, /**< filter phase b */ + qeiv2_filter_phase_z, /**< filter phase z */ + qeiv2_filter_phase_h, /**< filter phase h */ + qeiv2_filter_phase_h2, /**< filter phase h2 */ + qeiv2_filter_phase_f, /**< filter phase f */ +} qeiv2_filter_phase_t; /**< qeiv2_filter_phase_t */ + +/** + * @brief uvw position option + * + */ +typedef enum qeiv2_uvw_pos_opt { + qeiv2_uvw_pos_opt_current = 0, /**< output exact point position, MMC use this */ + qeiv2_uvw_pos_opt_next, /**< output next area position, QEO use this */ +} qeiv2_uvw_pos_opt_t; + +typedef enum qeiv2_uvw_pos_sel { + qeiv2_uvw_pos_sel_low = 0, + qeiv2_uvw_pos_sel_high, + qeiv2_uvw_pos_sel_edge +} qeiv2_uvw_pos_sel_t; /**< qeiv2_uvw_pos_sel_t */ + +/** + * @brief qeiv2 uvw position selection + * + */ +#define QEIV2_UVW_POS_OPT_CUR_SEL_LOW 0u +#define QEIV2_UVW_POS_OPT_CUR_SEL_HIGH 1u +#define QEIV2_UVW_POS_OPT_CUR_SEL_EDGE 2u +#define QEIV2_UVW_POS_OPT_NEX_SEL_LOW 0u +#define QEIV2_UVW_POS_OPT_NEX_SEL_HIGH 3u + +typedef enum qeiv2_uvw_pos_idx { + qeiv2_uvw_pos0 = 0, + qeiv2_uvw_pos1, + qeiv2_uvw_pos2, + qeiv2_uvw_pos3, + qeiv2_uvw_pos4, + qeiv2_uvw_pos5, +} qeiv2_uvw_pos_idx_t; /**< qeiv2_uvw_pos_idx_t */ + +/** + * @brief phase counter compare match config structure + * + */ +typedef struct { + uint32_t phcnt_cmp_value; + bool ignore_rotate_dir; + qeiv2_rotate_dir_t rotate_dir; + bool ignore_zcmp; + uint32_t zcmp_value; +} qeiv2_phcnt_cmp_match_config_t; + +/** + * @brief position compare match config structure + * + */ +typedef struct { + uint32_t pos_cmp_value; + bool ignore_pos_dir; + qeiv2_position_dir_t pos_dir; +} qeiv2_pos_cmp_match_config_t; + +/** + * @brief uvw config structure + */ +typedef struct { + qeiv2_uvw_pos_opt_t pos_opt; + qeiv2_uvw_pos_sel_t u_pos_sel[6]; + qeiv2_uvw_pos_sel_t v_pos_sel[6]; + qeiv2_uvw_pos_sel_t w_pos_sel[6]; + uint32_t pos_cfg[6]; +} qeiv2_uvw_config_t; + +/** + * @brief adc config structure + */ +typedef struct { + uint8_t adc_select; + uint8_t adc_channel; + int16_t param0; + int16_t param1; + uint32_t offset; +} qeiv2_adc_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief load phcnt, zcnt, spdcnt and tmrcnt into their read registers + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + */ +static inline void qeiv2_load_counter_to_read_registers(QEIV2_Type *qeiv2_x) +{ + qeiv2_x->CR |= QEIV2_CR_READ_MASK; +} + +/** + * @brief config z phase counter increment and decrement mode + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] mode + * @arg 1 zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 + * @arg 0 zcnt will increment or decrement when Z input assert + */ +static inline void qeiv2_config_z_phase_counter_mode(QEIV2_Type *qeiv2_x, qeiv2_z_count_work_mode_t mode) +{ + qeiv2_x->CR = (qeiv2_x->CR & ~QEIV2_CR_ZCNTCFG_MASK) | QEIV2_CR_ZCNTCFG_SET(mode); +} + +/** + * @brief config phase max value and phase param + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] phmax maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax + */ +static inline void qeiv2_config_phmax_phparam(QEIV2_Type *qeiv2_x, uint32_t phmax) +{ + uint32_t tmp; + + if (phmax > 0u) { + phmax--; + } + qeiv2_x->PHCFG = QEIV2_PHCFG_PHMAX_SET(phmax); + if (phmax == 0u) { + qeiv2_x->PHASE_PARAM = 0xFFFFFFFFu; + } else { + tmp = (0x80000000u / (phmax + 1u)); + tmp <<= 1u; + qeiv2_x->PHASE_PARAM = QEIV2_PHASE_PARAM_PHASE_PARAM_SET(tmp); + } +} + +/** + * @brief config phase calibration value trigged by z phase + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] enable phcnt will set to phidx when Z input assert + * @param[in] phidx phcnt reset value + * @param[in] mode qeiv2_work_mode_t + */ +static inline void qeiv2_config_z_phase_calibration(QEIV2_Type *qeiv2_x, uint32_t phidx, bool enable, qeiv2_work_mode_t mode) +{ + uint32_t tmp = qeiv2_x->CR; + qeiv2_x->PHIDX = QEIV2_PHIDX_PHIDX_SET(phidx); + if (enable) { + tmp |= QEIV2_CR_PHCALIZ_MASK; + } else { + tmp &= ~QEIV2_CR_PHCALIZ_MASK; + } + if (enable && ((mode == qeiv2_work_mode_sin) || (mode == qeiv2_work_mode_sincos))) { + tmp |= QEIV2_CR_Z_ONLY_EN_MASK; + } else { + tmp &= ~QEIV2_CR_Z_ONLY_EN_MASK; + } + qeiv2_x->CR = tmp; +} + +/** + * @brief pause counter when pause assert + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] counter_mask + * @arg QEIV2_CR_PAUSEPOS_MASK + * @arg QEIV2_CR_PAUSESPD_MASK + * @arg QEIV2_CR_PAUSEPH_MASK + * @arg QEIV2_CR_PAUSEZ_MASK + * @param[in] enable enable or disable pause + */ +static inline void qeiv2_pause_counter(QEIV2_Type *qeiv2_x, uint32_t counter_mask, bool enable) +{ + if (enable) { + qeiv2_x->CR |= counter_mask; + } else { + qeiv2_x->CR &= ~counter_mask; + } +} + +/** + * @brief pause pos counter when fault assert + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] enable enable or disable pause + */ +static inline void qeiv2_pause_pos_counter_on_fault(QEIV2_Type *qeiv2_x, bool enable) +{ + if (enable) { + qeiv2_x->CR |= QEIV2_CR_FAULTPOS_MASK; + } else { + qeiv2_x->CR &= ~QEIV2_CR_FAULTPOS_MASK; + } +} + +/** + * @brief enable load phcnt, zcnt, spdcnt and tmrcnt into their snap registers + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + */ +static inline void qeiv2_enable_snap(QEIV2_Type *qeiv2_x) +{ + qeiv2_x->CR |= QEIV2_CR_SNAPEN_MASK; +} + +/** + * @brief disable snap + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + */ +static inline void qeiv2_disable_snap(QEIV2_Type *qeiv2_x) +{ + qeiv2_x->CR &= ~QEIV2_CR_SNAPEN_MASK; +} + +/** + * @brief reset zcnt, spdcnt and tmrcnt to 0, reset phcnt to phidx. + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + */ +static inline void qeiv2_reset_counter(QEIV2_Type *qeiv2_x) +{ + qeiv2_x->CR |= QEIV2_CR_RSTCNT_MASK; +} + +/** + * @brief release counter. + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + */ +static inline void qeiv2_release_counter(QEIV2_Type *qeiv2_x) +{ + qeiv2_x->CR &= ~QEIV2_CR_RSTCNT_MASK; +} + +/** + * @brief select spd and tmr register content + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] content @ref qeiv2_spd_tmr_content_t + */ +static inline void qeiv2_select_spd_tmr_register_content(QEIV2_Type *qeiv2_x, qeiv2_spd_tmr_content_t content) +{ + qeiv2_x->CR = (qeiv2_x->CR & ~QEIV2_CR_RD_SEL_MASK) | QEIV2_CR_RD_SEL_SET(content); +} + +/** + * @brief check spd and tmr register content as pos and angle + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @return true if spd and timer register as pos and angle register + */ +static inline bool qeiv2_check_spd_tmr_as_pos_angle(QEIV2_Type *qeiv2_x) +{ + return ((qeiv2_x->CR & QEIV2_CR_RD_SEL_MASK) != 0) ? true : false; +} + +/** + * @brief set qeiv2 work mode + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] mode @ref qeiv2_work_mode_t + */ +static inline void qeiv2_set_work_mode(QEIV2_Type *qeiv2_x, qeiv2_work_mode_t mode) +{ + qeiv2_x->CR = (qeiv2_x->CR & ~QEIV2_CR_ENCTYP_MASK) | QEIV2_CR_ENCTYP_SET(mode); +} + +/** + * @brief config watchdog + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] timeout watchdog timeout time + * @param[in] clr_phcnt the phase_cnt time passed, then clear wdog counter + * @param[in] enable + * @arg 1 - enable watchdog + * @arg 0 - disable watchdog + */ +static inline void qeiv2_config_wdog(QEIV2_Type *qeiv2_x, uint32_t timeout, uint8_t clr_phcnt, bool enable) +{ + uint32_t tmp; + tmp = QEIV2_WDGCFG_WDGTO_SET(timeout) | QEIV2_WDGCFG_WDOG_CFG_SET(clr_phcnt); + if (enable) { + tmp |= QEIV2_WDGCFG_WDGEN_MASK; + } else { + tmp &= ~QEIV2_WDGCFG_WDGEN_MASK; + } + qeiv2_x->WDGCFG = tmp; +} + +/** + * @brief enable trig out trigger event + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] event_mask + * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK + * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK + * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK + */ +static inline void qeiv2_enable_trig_out_trigger_event(QEIV2_Type *qeiv2_x, uint32_t event_mask) +{ + qeiv2_x->TRGOEN |= event_mask; +} + +/** + * @brief disable trig out trigger event + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] event_mask + * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK + * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK + * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK + */ +static inline void qeiv2_disable_trig_out_trigger_event(QEIV2_Type *qeiv2_x, uint32_t event_mask) +{ + qeiv2_x->TRGOEN &= ~event_mask; +} + +/** + * @brief enable load read trigger event + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] event_mask + * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK + * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK + * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK + */ +static inline void qeiv2_enable_load_read_trigger_event(QEIV2_Type *qeiv2_x, uint32_t event_mask) +{ + qeiv2_x->READEN |= event_mask; +} + +/** + * @brief disable load read trigger event + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] event_mask + * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK + * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK + * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK + */ +static inline void qeiv2_disable_load_read_trigger_event(QEIV2_Type *qeiv2_x, uint32_t event_mask) +{ + qeiv2_x->READEN &= ~event_mask; +} + +/** + * @brief enable dma request + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] mask + * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK + * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK + * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK + */ +static inline void qeiv2_enable_dma_request(QEIV2_Type *qeiv2_x, uint32_t mask) +{ + qeiv2_x->DMAEN |= mask; +} + +/** + * @brief disable qeiv2 dma + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] mask + * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK + * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK + * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK + */ +static inline void qeiv2_disable_dma_request(QEIV2_Type *qeiv2_x, uint32_t mask) +{ + qeiv2_x->DMAEN &= ~mask; +} + +/** + * @brief clear qeiv2 status register + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] mask + * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK + * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK + * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK + */ +static inline void qeiv2_clear_status(QEIV2_Type *qeiv2_x, uint32_t mask) +{ + qeiv2_x->SR = mask; +} + +/** + * @brief get qeiv2 status + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @retval qeiv2 status: + * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK + * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK + * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK + */ +static inline uint32_t qeiv2_get_status(QEIV2_Type *qeiv2_x) +{ + return qeiv2_x->SR; +} + +/** + * @brief get qeiv2 bit status + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] mask + * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK + * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK + * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK + * @retval true or false + */ +static inline bool qeiv2_get_bit_status(QEIV2_Type *qeiv2_x, uint32_t mask) +{ + return ((qeiv2_x->SR & mask) == mask) ? true : false; +} + +/** + * @brief enable qeiv2 irq + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] mask + * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK + * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK + * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK + */ +static inline void qeiv2_enable_irq(QEIV2_Type *qeiv2_x, uint32_t mask) +{ + qeiv2_x->IRQEN |= mask; +} + +/** + * @brief disable qeiv2 irq + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] mask + * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK + * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK + * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK + */ +static inline void qeiv2_disable_irq(QEIV2_Type *qeiv2_x, uint32_t mask) +{ + qeiv2_x->IRQEN &= ~mask; +} + +/** + * @brief get current counter value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] type @ref qeiv2_counter_type_t + * @retval counter value + */ +static inline uint32_t qeiv2_get_current_count(QEIV2_Type *qeiv2_x, qeiv2_counter_type_t type) +{ + return *(&qeiv2_x->COUNT[QEIV2_COUNT_CURRENT].Z + type); +} + +/** + * @brief get current phcnt value + * + * @param qeiv2_x QEI base address, HPM_QEIx(x=0...n) + * @return phcnt value + */ +static inline uint32_t qeiv2_get_current_phase_phcnt(QEIV2_Type *qeiv2_x) +{ + return QEIV2_COUNT_PH_PHCNT_GET(qeiv2_get_current_count(qeiv2_x, qeiv2_counter_type_phase)); +} + +/** + * @brief get current a phase level + * + * @param qeiv2_x QEI base address, HPM_QEIx(x=0...n) + * @return a phase level + */ +static inline bool qeiv2_get_current_phase_a_level(QEIV2_Type *qeiv2_x) +{ + return QEIV2_COUNT_PH_ASTAT_GET(qeiv2_get_current_count(qeiv2_x, qeiv2_counter_type_phase)); +} + +/** + * @brief get current b phase level + * + * @param qeiv2_x QEI base address, HPM_QEIx(x=0...n) + * @return b phase level + */ +static inline bool qeiv2_get_current_phase_b_level(QEIV2_Type *qeiv2_x) +{ + return QEIV2_COUNT_PH_BSTAT_GET(qeiv2_get_current_count(qeiv2_x, qeiv2_counter_type_phase)); +} + +/** + * @brief get current phase dir + * + * @param qeiv2_x QEI base address, HPM_QEIx(x=0...n) + * @return dir + */ +static inline bool qeiv2_get_current_phase_dir(QEIV2_Type *qeiv2_x) +{ + return QEIV2_COUNT_PH_DIR_GET(qeiv2_get_current_count(qeiv2_x, qeiv2_counter_type_phase)); +} + + +/** + * @brief get read event count value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] type @ref qeiv2_counter_type_t + * @retval counter value + */ +static inline uint32_t qeiv2_get_count_on_read_event(QEIV2_Type *qeiv2_x, qeiv2_counter_type_t type) +{ + return *(&(qeiv2_x->COUNT[QEIV2_COUNT_READ].Z) + type); +} + +/** + * @brief read the value of each phase snapshot 0 counter + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] type @ref qeiv2_counter_type_t + * @retval counter value + */ +static inline uint32_t qeiv2_get_count_on_snap0_event(QEIV2_Type *qeiv2_x, qeiv2_counter_type_t type) +{ + return *(&qeiv2_x->COUNT[QEIV2_COUNT_SNAP0].Z + type); +} + +/** + * @brief read the value of each phase snapshot 1 counter + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] type @ref qeiv2_counter_type_t + * @retval counter value + */ +static inline uint32_t qeiv2_get_count_on_snap1_event(QEIV2_Type *qeiv2_x, qeiv2_counter_type_t type) +{ + return *(&qeiv2_x->COUNT[QEIV2_COUNT_SNAP1].Z + type); +} + +/** + * @brief set zcnt compare value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] cmp zcnt compare value + */ +static inline void qeiv2_set_z_cmp_value(QEIV2_Type *qeiv2_x, uint32_t cmp) +{ + qeiv2_x->ZCMP = QEIV2_ZCMP_ZCMP_SET(cmp); +} + +/** + * @brief set phcnt compare value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] cmp phcnt compare value + */ +static inline void qeiv2_set_phcnt_cmp_value(QEIV2_Type *qeiv2_x, uint32_t cmp) +{ + qeiv2_x->PHCMP = QEIV2_PHCMP_PHCMP_SET(cmp); +} + +/** + * @brief set spdcnt or position compare value. It's selected by CR register rd_sel bit. + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] cmp spdcnt or position compare value + * when set @ref qeiv2_spd_tmr_as_spd_tm, this is spdcmp value. (ABZ encoder) + * when set @ref qeiv2_spd_tmr_as_pos_angle, this is poscmp value. (sin or sincos encoder) + */ +static inline void qeiv2_set_spd_pos_cmp_value(QEIV2_Type *qeiv2_x, uint32_t cmp) +{ + qeiv2_x->SPDCMP = QEIV2_SPDCMP_SPDCMP_SET(cmp); +} + +/** + * @brief set compare match options + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] ignore_zcmp ignore zcmp + * @param[in] ignore_phcmp ignore phcmp + * @param[in] ignore_spdposcmp ignore spdposcmp + * when set @ref qeiv2_spd_tmr_as_spd_tm, this is spdcmp value. (ABZ encoder) + * when set @ref qeiv2_spd_tmr_as_pos_angle, this is poscmp value. (sin or sincos encoder) + * @param[in] ignore_rotate_dir ignore encoder rotation direction. (ABZ encoder) + * @param[in] rotate_dir when don't ignore rotation direction, match rotation direction. @ref qeiv2_rotate_dir_t. (ABZ encoder) + * @param[in] ignore_pos_dir ignore position increase or decrease direction. (sin or sincos encoder) + * @param[in] pos_dir when don't ignore position direction, match position direction. @ref qeiv2_position_dir_t. (sin or sincos encoder) + */ +static inline void qeiv2_set_cmp_match_option(QEIV2_Type *qeiv2_x, bool ignore_zcmp, bool ignore_phcmp, bool ignore_spdposcmp, + bool ignore_rotate_dir, qeiv2_rotate_dir_t rotate_dir, bool ignore_pos_dir, qeiv2_position_dir_t pos_dir) +{ + qeiv2_x->MATCH_CFG = (qeiv2_x->MATCH_CFG & (~(QEIV2_MATCH_CFG_ZCMPDIS_MASK | QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK | QEIV2_MATCH_CFG_SPDCMPDIS_MASK + | QEIV2_MATCH_CFG_DIRCMPDIS_MASK | QEIV2_MATCH_CFG_DIRCMP_MASK + | QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK | QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK))) + | QEIV2_MATCH_CFG_ZCMPDIS_SET(ignore_zcmp) | QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SET(ignore_phcmp) + | QEIV2_MATCH_CFG_SPDCMPDIS_SET(ignore_spdposcmp) + | QEIV2_MATCH_CFG_DIRCMPDIS_SET(ignore_rotate_dir) | QEIV2_MATCH_CFG_DIRCMP_SET(rotate_dir) + | QEIV2_MATCH_CFG_POS_MATCH_OPT_SET(!ignore_pos_dir) | QEIV2_MATCH_CFG_POS_MATCH_DIR_SET(pos_dir); +} + +/** + * @brief set zcnt compare2 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] cmp zcnt compare2 value + */ +static inline void qeiv2_set_z_cmp2_value(QEIV2_Type *qeiv2_x, uint32_t cmp) +{ + qeiv2_x->ZCMP2 = QEIV2_ZCMP2_ZCMP2_SET(cmp); +} + +/** + * @brief set phcnt compare2 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] cmp phcnt compare2 value + */ +static inline void qeiv2_set_phcnt_cmp2_value(QEIV2_Type *qeiv2_x, uint32_t cmp) +{ + qeiv2_x->PHCMP2 = QEIV2_PHCMP2_PHCMP2_SET(cmp); +} + +/** + * @brief set spdcnt or position compare2 value. It's selected by CR register rd_sel bit. + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] cmp spdcnt or position compare2 value + */ +static inline void qeiv2_set_spd_pos_cmp2_value(QEIV2_Type *qeiv2_x, uint32_t cmp) +{ + qeiv2_x->SPDCMP2 = QEIV2_SPDCMP2_SPDCMP2_SET(cmp); +} + +/** + * @brief set compare2 match options + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] ignore_zcmp ignore zcmp + * @param[in] ignore_phcmp ignore phcmp + * @param[in] ignore_spdposcmp ignore spdposcmp. + * when set @ref qeiv2_spd_tmr_as_spd_tm, this is spdcmp value. (ABZ encoder) + * when set @ref qeiv2_spd_tmr_as_pos_angle, this is poscmp value. (sin or sincos encoder) + * @param[in] ignore_rotate_dir ignore encoder rotation direction. (ABZ encoder) + * @param[in] rotate_dir when don't ignore rotation direction, match rotation direction. @ref qeiv2_rotate_dir_t. (ABZ encoder) + * @param[in] ignore_pos_dir ignore position increase or decrease direction. (sin or sincos encoder) + * @param[in] pos_dir when don't ignore position direction, match position direction. @ref qeiv2_position_dir_t. (sin or sincos encoder) + */ +static inline void qeiv2_set_cmp2_match_option(QEIV2_Type *qeiv2_x, bool ignore_zcmp, bool ignore_phcmp, bool ignore_spdposcmp, + bool ignore_rotate_dir, qeiv2_rotate_dir_t rotate_dir, bool ignore_pos_dir, qeiv2_position_dir_t pos_dir) +{ + qeiv2_x->MATCH_CFG = (qeiv2_x->MATCH_CFG & ~(QEIV2_MATCH_CFG_ZCMP2DIS_MASK | QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK | QEIV2_MATCH_CFG_SPDCMP2DIS_MASK + | QEIV2_MATCH_CFG_DIRCMP2DIS_MASK | QEIV2_MATCH_CFG_DIRCMP2_MASK + | QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK | QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK)) + | QEIV2_MATCH_CFG_ZCMP2DIS_SET(ignore_zcmp) | QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SET(ignore_phcmp) + | QEIV2_MATCH_CFG_SPDCMP2DIS_SET(ignore_spdposcmp) + | QEIV2_MATCH_CFG_DIRCMP2DIS_SET(ignore_rotate_dir) | QEIV2_MATCH_CFG_DIRCMP2_SET(rotate_dir) + | QEIV2_MATCH_CFG_POS_MATCH2_OPT_SET(!ignore_pos_dir) | QEIV2_MATCH_CFG_POS_MATCH2_DIR_SET(pos_dir); +} + +/** + * @brief config signal enablement and edge + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] siga_en enable signal A/U + * @param[in] sigb_en enable signal B/V + * @param[in] sigz_en enable signal Z/W + * @param[in] posedge_en enable rise edge + * @param[in] negedge_en enable fall edge + */ +static inline void qeiv2_config_abz_uvw_signal_edge(QEIV2_Type *qeiv2_x, bool siga_en, bool sigb_en, bool sigz_en, bool posedge_en, bool negedge_en) +{ + qeiv2_x->QEI_CFG = (qeiv2_x->QEI_CFG & ~(QEIV2_QEI_CFG_SIGA_EN_MASK | QEIV2_QEI_CFG_SIGB_EN_MASK | QEIV2_QEI_CFG_SIGZ_EN_MASK + | QEIV2_QEI_CFG_POSIDGE_EN_MASK | QEIV2_QEI_CFG_NEGEDGE_EN_MASK)) + | (QEIV2_QEI_CFG_SIGA_EN_SET(siga_en) | QEIV2_QEI_CFG_SIGB_EN_SET(sigb_en) | QEIV2_QEI_CFG_SIGZ_EN_SET(sigz_en) + | QEIV2_QEI_CFG_POSIDGE_EN_SET(posedge_en) | QEIV2_QEI_CFG_NEGEDGE_EN_SET(negedge_en)); +} + +/** + * @brief set pulse0 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] pulse_num for speed detection, will count the cycle number for configed pulse_num + */ +static inline void qeiv2_set_pulse0_num(QEIV2_Type *qeiv2_x, uint32_t pulse_num) +{ + qeiv2_x->PULSE0_NUM = QEIV2_PULSE0_NUM_PULSE0_NUM_SET(pulse_num); +} + +/** + * @brief get cycle0 snap0 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @retval cycle0 snap0 value + */ +static inline uint32_t qeiv2_get_pulse0_cycle_snap0(QEIV2_Type *qeiv2_x) +{ + return qeiv2_x->CYCLE0_SNAP0; +} + +/** + * @brief get cycle0 snap1 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @retval cycle0 snap1 value + */ +static inline uint32_t qeiv2_get_pulse0_cycle_snap1(QEIV2_Type *qeiv2_x) +{ + return qeiv2_x->CYCLE0_SNAP1; +} + +/** + * @brief set pulse1 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] pulse_num for speed detection, will count the cycle number for configed pulse_num + */ +static inline void qeiv2_set_pulse1_num(QEIV2_Type *qeiv2_x, uint32_t pulse_num) +{ + qeiv2_x->PULSE1_NUM = QEIV2_PULSE1_NUM_PULSE1_NUM_SET(pulse_num); +} + +/** + * @brief get cycle1 snap0 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @retval cycle1 snap0 value + */ +static inline uint32_t qeiv2_get_pulse1_cycle_snap0(QEIV2_Type *qeiv2_x) +{ + return qeiv2_x->CYCLE1_SNAP0; +} + +/** + * @brief get cycle1 snap1 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @retval cycle1 snap1 value + */ +static inline uint32_t qeiv2_get_pulse1_cycle_snap1(QEIV2_Type *qeiv2_x) +{ + return qeiv2_x->CYCLE1_SNAP1; +} + +/** + * @brief set cycle0 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] cycle_num for speed detection, will count the pulse number for configed cycle_num + */ +static inline void qeiv2_set_cycle0_num(QEIV2_Type *qeiv2_x, uint32_t cycle_num) +{ + qeiv2_x->CYCLE0_NUM = QEIV2_CYCLE0_NUM_CYCLE0_NUM_SET(cycle_num); +} + +/** + * @brief get pulse0 snap0 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @retval pulse0 snap0 value + */ +static inline uint32_t qeiv2_get_cycle0_pulse_snap0(QEIV2_Type *qeiv2_x) +{ + return qeiv2_x->PULSE0_SNAP0; +} + +/** + * @brief get pulse0 snap1 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @retval pulse0 snap1 value + */ +static inline uint32_t qeiv2_get_cycle0_pulse_snap1(QEIV2_Type *qeiv2_x) +{ + return qeiv2_x->PULSE0_SNAP1; +} + +/** + * @brief get pulse0cycle snap0 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @retval pulse0cycle snap0 value + */ +static inline uint32_t qeiv2_get_cycle0_pulse0cycle_snap0(QEIV2_Type *qeiv2_x) +{ + return qeiv2_x->PULSE0CYCLE_SNAP0; +} + +/** + * @brief get pulse0cycle snap1 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @retval pulse0cycle snap1 value + */ +static inline uint32_t qeiv2_get_cycle0_pulse0cycle_snap1(QEIV2_Type *qeiv2_x) +{ + return qeiv2_x->PULSE0CYCLE_SNAP1; +} + +/** + * @brief set cycle1 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] cycle_num for speed detection, will count the pulse number for configed cycle_num + */ +static inline void qeiv2_set_cycle1_num(QEIV2_Type *qeiv2_x, uint32_t cycle_num) +{ + qeiv2_x->CYCLE1_NUM = QEIV2_CYCLE1_NUM_CYCLE1_NUM_SET(cycle_num); +} + +/** + * @brief get pulse1 snap0 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @retval pulse1 snap0 value + */ +static inline uint32_t qeiv2_get_cycle1_pulse_snap0(QEIV2_Type *qeiv2_x) +{ + return qeiv2_x->PULSE1_SNAP0; +} + +/** + * @brief get pulse1 snap1 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @retval pulse1 snap1 value + */ +static inline uint32_t qeiv2_get_cycle1_pulse_snap1(QEIV2_Type *qeiv2_x) +{ + return qeiv2_x->PULSE1_SNAP1; +} + +/** + * @brief get pulse1cycle snap0 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @retval pulse1cycle snap0 value + */ +static inline uint32_t qeiv2_get_cycle1_pulse1cycle_snap0(QEIV2_Type *qeiv2_x) +{ + return qeiv2_x->PULSE1CYCLE_SNAP0; +} + +/** + * @brief get pulse1cycle snap1 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @retval pulse01cycle snap1 value + */ +static inline uint32_t qeiv2_get_cycle1_pulse1cycle_snap1(QEIV2_Type *qeiv2_x) +{ + return qeiv2_x->PULSE1CYCLE_SNAP1; +} + +/** + * @brief enable or disable clear counter if detect direction change + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] enable enable or disable clear counter if detect direction change + */ +static inline void qeiv2_clear_counter_when_dir_chg(QEIV2_Type *qeiv2_x, bool enable) +{ + if (enable) { + qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK; + } else { + qeiv2_x->QEI_CFG &= ~QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK; + } +} + +/** + * @brief adcx config + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] config qeiv2_adc_config_t + * @param[in] enable enable or disable adcx + */ +static inline void qeiv2_config_adcx(QEIV2_Type *qeiv2_x, qeiv2_adc_config_t *config, bool enable) +{ + uint32_t tmp; + tmp = QEIV2_ADCX_CFG0_X_ADCSEL_SET(config->adc_select) | QEIV2_ADCX_CFG0_X_CHAN_SET(config->adc_channel); + qeiv2_x->ADCX_CFG1 = QEIV2_ADCX_CFG1_X_PARAM1_SET(config->param1) | QEIV2_ADCX_CFG1_X_PARAM0_SET(config->param0); + qeiv2_x->ADCX_CFG2 = QEIV2_ADCX_CFG2_X_OFFSET_SET(config->offset); + if (enable) { + tmp |= QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK; + } else { + tmp &= ~QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK; + } + qeiv2_x->ADCX_CFG0 = tmp; +} + +/** + * @brief adcy config + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] config qeiv2_adc_config_t + * @param[in] enable enable or disable adcy + */ +static inline void qeiv2_config_adcy(QEIV2_Type *qeiv2_x, qeiv2_adc_config_t *config, bool enable) +{ + uint32_t tmp; + tmp = QEIV2_ADCY_CFG0_Y_ADCSEL_SET(config->adc_select) | QEIV2_ADCY_CFG0_Y_CHAN_SET(config->adc_channel); + qeiv2_x->ADCY_CFG1 = QEIV2_ADCY_CFG1_Y_PARAM1_SET(config->param1) | QEIV2_ADCY_CFG1_Y_PARAM0_SET(config->param0); + qeiv2_x->ADCY_CFG2 = QEIV2_ADCY_CFG2_Y_OFFSET_SET(config->offset); + if (enable) { + tmp |= QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK; + } else { + tmp &= ~QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK; + } + qeiv2_x->ADCY_CFG0 = tmp; +} + +/** + * @brief set adcx and adcy delay + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] delay x/y delay, default 1.25us@200MHz, max 80ms + */ +static inline void qeiv2_set_adc_xy_delay(QEIV2_Type *qeiv2_x, uint32_t delay) +{ + qeiv2_x->CAL_CFG = QEIV2_CAL_CFG_XY_DELAY_SET(delay); +} + +/** + * @brief set position threshold + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] threshold Position change threshold. When two position changes exceed this value, + * it will be considered as an invalid position and no valid signal will be output. + */ +static inline void qeiv2_set_position_threshold(QEIV2_Type *qeiv2_x, uint32_t threshold) +{ + qeiv2_x->POS_THRESHOLD = QEIV2_POS_THRESHOLD_POS_THRESHOLD_SET(threshold); +} + +/** + * @brief set uvw position option + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] opt qeiv2_uvw_pos_opt_t + */ +static inline void qeiv2_set_uvw_position_opt(QEIV2_Type *qeiv2_x, qeiv2_uvw_pos_opt_t opt) +{ + qeiv2_x->QEI_CFG = (qeiv2_x->QEI_CFG & ~QEIV2_QEI_CFG_UVW_POS_OPT0_MASK) | QEIV2_QEI_CFG_UVW_POS_OPT0_SET(opt); +} + +/** + * @brief set config uvw position + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] idx uvw position config index + * @arg @ref qeiv2_uvw_pos_idx_t + * @param[in] u_pos_sel U position selection based by uvw position option + * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_LOW + * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_HIGH + * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_EDGE + * @arg @ref QEIV2_UVW_POS_OPT_NEX_SEL_LOW + * @arg @ref QEIV2_UVW_POS_OPT_NEX_SEL_HIGH + * @param[in] v_pos_sel V position selection based by uvw position option + * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_LOW + * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_HIGH + * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_EDGE + * @arg @ref QEIV2_UVW_POS_OPT_NEX_SEL_LOW + * @arg @ref QEIV2_UVW_POS_OPT_NEX_SEL_HIGH + * @param[in] w_pos_sel W position selection based by uvw position option + * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_LOW + * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_HIGH + * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_EDGE + * @arg @ref QEIV2_UVW_POS_OPT_NEX_SEL_LOW + * @arg @ref QEIV2_UVW_POS_OPT_NEX_SEL_HIGH + * @param[in] enable enable this uvw config + */ +static inline void qeiv2_set_uvw_position_sel(QEIV2_Type *qeiv2_x, qeiv2_uvw_pos_idx_t idx, uint8_t u_pos_sel, uint8_t v_pos_sel, + uint8_t w_pos_sel, bool enable) +{ + uint32_t tmp; + tmp = QEIV2_UVW_POS_CFG_U_POS_SEL_SET(u_pos_sel) + | QEIV2_UVW_POS_CFG_V_POS_SEL_SET(v_pos_sel) + | QEIV2_UVW_POS_CFG_W_POS_SEL_SET(w_pos_sel); + if (enable) { + tmp |= QEIV2_UVW_POS_CFG_POS_EN_MASK; + } else { + tmp &= ~QEIV2_UVW_POS_CFG_POS_EN_MASK; + } + qeiv2_x->UVW_POS_CFG[idx] = tmp; +} + +/** + * @brief set uvw position + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] idx uvw position config index + * @arg @ref qeiv2_uvw_pos_idx_t + * @param[in] pos angle corresponding to UVW signal position + */ +static inline void qeiv2_set_uvw_position(QEIV2_Type *qeiv2_x, qeiv2_uvw_pos_idx_t idx, uint32_t pos) +{ + qeiv2_x->UVW_POS[idx] = pos; +} + +/** + * @brief set z phase counter value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] cnt z phase counter value + */ +static inline void qeiv2_set_z_phase(QEIV2_Type *qeiv2_x, uint32_t cnt) +{ + qeiv2_x->COUNT[QEIV2_COUNT_CURRENT].Z = cnt; +} + +/** + * @brief set phase counter value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] cnt phase counter value + */ +static inline void qeiv2_set_phase_cnt(QEIV2_Type *qeiv2_x, uint32_t cnt) +{ + qeiv2_x->PHASE_CNT = cnt; +} + +/** + * @brief get phase counter value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @retval phase counter value + */ +static inline uint32_t qeiv2_get_phase_cnt(QEIV2_Type *qeiv2_x) +{ + return qeiv2_x->PHASE_CNT; +} + +/** + * @brief update phase counter value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] inc set to add value to phase_cnt + * @param[in] dec set to minus value to phase_cnt (set inc and dec same time willl act inc) + * @param[in] value value to be added or minus from phase_cnt. only valid when inc or dec is set in one 32bit write operation. + */ +static inline void qeiv2_update_phase_cnt(QEIV2_Type *qeiv2_x, bool inc, bool dec, uint32_t value) +{ + qeiv2_x->PHASE_UPDATE = QEIV2_PHASE_UPDATE_INC_SET(inc) | QEIV2_PHASE_UPDATE_DEC_SET(dec) | QEIV2_PHASE_UPDATE_VALUE_SET(value); +} + +/** + * @brief set position value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] pos position + */ +static inline void qeiv2_set_position(QEIV2_Type *qeiv2_x, uint32_t pos) +{ + qeiv2_x->POSITION = pos; +} + +/** + * @brief get position value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @retval position value + */ +static inline uint32_t qeiv2_get_postion(QEIV2_Type *qeiv2_x) +{ + return qeiv2_x->POSITION; +} + +/** + * @brief update position value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] inc set to add value to position + * @param[in] dec set to minus cnt value to position (set inc and dec same time willl act inc) + * @param[in] value value to be added or minus from position. only valid when inc or dec is set in one 32bit write operation. + */ +static inline void qeiv2_update_position(QEIV2_Type *qeiv2_x, bool inc, bool dec, uint32_t value) +{ + qeiv2_x->POSITION_UPDATE = QEIV2_POSITION_UPDATE_INC_SET(inc) | QEIV2_POSITION_UPDATE_DEC_SET(dec) | QEIV2_POSITION_UPDATE_VALUE_SET(value); +} + +/** + * @brief get angle value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @retval angle value + */ +static inline uint32_t qeiv2_get_angle(QEIV2_Type *qeiv2_x) +{ + return qeiv2_x->ANGLE; +} + +/** + * @brief set angle adjust value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] angle_adj angle adjust value + */ +static inline void qeiv2_set_angle_adjust_value(QEIV2_Type *qeiv2_x, int32_t angle_adj) +{ + qeiv2_x->ANGLE_ADJ = QEIV2_ANGLE_ADJ_ANGLE_ADJ_SET(angle_adj); +} + +/** + * @brief config position timeout for mmc module + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] tm postion timeout value + * @param[in] enable enable position timeout feature. If timeout, send valid again. + */ +static inline void qeiv2_config_position_timeout(QEIV2_Type *qeiv2_x, uint32_t tm, bool enable) +{ + uint32_t tmp; + tmp = QEIV2_POS_TIMEOUT_TIMEOUT_SET(tm); + if (enable) { + tmp |= QEIV2_POS_TIMEOUT_ENABLE_MASK; + } else { + tmp &= ~QEIV2_POS_TIMEOUT_ENABLE_MASK; + } + qeiv2_x->POS_TIMEOUT = tmp; +} + +/** + * @brief config phcnt compare match condition + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] config @ref qeiv2_phcnt_cmp_match_config_t + * @return status_invalid_argument or status_success + */ +hpm_stat_t qeiv2_config_phcnt_cmp_match_condition(QEIV2_Type *qeiv2_x, qeiv2_phcnt_cmp_match_config_t *config); + +/** + * @brief config position compare match condition + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] config @ref qeiv2_pos_cmp_match_config_t + * @return status_invalid_argument or status_success + */ +hpm_stat_t qeiv2_config_position_cmp_match_condition(QEIV2_Type *qeiv2_x, qeiv2_pos_cmp_match_config_t *config); + +/** + * @brief config phcnt compare2 match condition + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] config @ref qeiv2_phcnt_cmp_match_config_t + * @return status_invalid_argument or status_success + */ +hpm_stat_t qeiv2_config_phcnt_cmp2_match_condition(QEIV2_Type *qeiv2_x, qeiv2_phcnt_cmp_match_config_t *config); + +/** + * @brief config position compare2 match condition + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] config @ref qeiv2_pos_cmp_match_config_t + * @return status_invalid_argument or status_success + */ +hpm_stat_t qeiv2_config_position_cmp2_match_condition(QEIV2_Type *qeiv2_x, qeiv2_pos_cmp_match_config_t *config); + +/** + * @brief get uvw position default config + * + * @param[out] config uvw position default config structure pointer + */ +void qeiv2_get_uvw_position_defconfig(qeiv2_uvw_config_t *config); + +/** + * @brief config uvw position + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] config uvw position config structure pointer + * @return status_invalid_argument or status_success + */ +hpm_stat_t qeiv2_config_uvw_position(QEIV2_Type *qeiv2_x, qeiv2_uvw_config_t *config); + +/** + * @brief config signal filter + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] phase filter phase + * @arg @ref qeiv2_filter_phase_t + * @param[in] outinv Filter will invert the output + * @param[in] mode qeiv2_filter_mode_t + * @param[in] sync set to enable sychronization input signal with TRGM clock + * @param[in] filtlen defines the filter counter length. + */ +void qeiv2_config_filter(QEIV2_Type *qeiv2_x, qeiv2_filter_phase_t phase, bool outinv, qeiv2_filter_mode_t mode, bool sync, uint32_t filtlen); + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_QEIV2_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_qeo_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_qeo_drv.h new file mode 100644 index 00000000000..e6f98b4dff1 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_qeo_drv.h @@ -0,0 +1,560 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_QEO_DRV_H +#define HPM_QEO_DRV_H + +#include "hpm_common.h" +#include "hpm_qeo_regs.h" +/** + * @brief QEO driver APIs + * @defgroup qeo_interface QEO driver APIs + * @ingroup qeo_interfaces + * @{ + */ + +typedef enum { + qeo_wave_cosine = 0, + qeo_wave_saddle = 1, + qeo_wave_abs_cosine = 2, + qeo_wave_saw = 3, +} qeo_wave_type_t; + +typedef enum { + qeo_wave_above_max_limit_max_val = 0, + qeo_wave_above_max_limit_zero = 1, + qeo_wave_above_max_limit_max_level0_val = 2, + + qeo_wave_high_area_limit_max_val = 0, + qeo_wave_high_area_limit_max_level0_val = 1, + + qeo_wave_low_area_limit_zero = 0, + qeo_wave_low_area_limit_min_level1_val = 1, + + qeo_wave_below_min_limit_zero = 0, + qeo_wave_below_min_limit_max_val = 1, + qeo_wave_below_min_limit_min_level1_val = 2, +} qeo_wave_limit_t; + +typedef struct { + uint8_t above_max_limit; + uint8_t high_area0_limit; + uint8_t high_area1_limit; + uint8_t low_area0_limit; + uint8_t low_area1_limit; + uint8_t below_min_limit; +} qeo_wave_limit_config_t; + +typedef struct { + qeo_wave_limit_config_t wave0; + qeo_wave_limit_config_t wave1; + qeo_wave_limit_config_t wave2; + uint8_t wave_type; + uint8_t saddle_type; +} qeo_wave_mode_t; + +typedef enum { + qeo_abz_output_abz = 0, /*< A and B are orthogonal signals, Z is zero pulse */ + qeo_abz_output_pulse_revise = 1, /*< A is speed pulse, B is directional pulse, Z not used */ + qeo_abz_output_up_down = 2, /*< A is forward pulse, B is reverse pusle, Z not used */ + qeo_abz_output_three_phase = 3, /*< A/B/Z are 3-phase orthogonal pulse */ +} qeo_abz_type_t; + +/* take effect when output type is qeo_abz_output_abz */ +typedef enum { + qeo_z_pulse_25_percent = 0, + qeo_z_pulse_75_percent = 1, + qeo_z_pulse_100_percent = 2, +} qeo_z_pulse_period_t; + +typedef struct { + bool z_inv_pol; + bool b_inv_pol; + bool a_inv_pol; + uint8_t output_type; /*!< @ref qeo_abz_type_t */ + uint8_t z_pulse_period; /*!< @ref qeo_z_pulse_period_t */ +} qeo_abz_mode_t; + +typedef enum { + qeo_pwm_output_force_0 = 2, + qeo_pwm_output_force_1 = 3, + qeo_pwm_output_not_force = 0, +} qeo_pwm_force_output_t; + +typedef enum { + qeo_pwm_safety_output_0 = 0, + qeo_pwm_safety_output_1 = 1, + qeo_pwm_safety_output_highz = 2, +} qeo_pwm_safety_output_t; + +typedef struct { + uint8_t pwm0_output; /*!< @ref qeo_pwm_force_output_t */ + uint8_t pwm1_output; + uint8_t pwm2_output; + uint8_t pwm3_output; + uint8_t pwm4_output; + uint8_t pwm5_output; + uint8_t pwm6_output; + uint8_t pwm7_output; +} qeo_pwm_phase_output_table_t; + +typedef struct { + uint8_t pwm0_output; /*!< @ref qeo_pwm_safety_output_t */ + uint8_t pwm1_output; + uint8_t pwm2_output; + uint8_t pwm3_output; + uint8_t pwm4_output; + uint8_t pwm5_output; + uint8_t pwm6_output; + uint8_t pwm7_output; +} qeo_pwm_safety_output_table_t; + +typedef struct { + uint8_t phase_num; + bool shield_hardware_trig_safety; + bool revise_pairs_output; +} qeo_pwm_mode_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/* WAVE API */ +/** + * @brief QEO set resolution lines for wave mode + * @param [in] base QEO base address + * @param [in] lines resolution lines + */ +static inline void qeo_wave_set_resolution_lines(QEO_Type *base, uint32_t lines) +{ + base->WAVE.RESOLUTION = QEO_WAVE_RESOLUTION_LINES_SET(lines); +} + +/** + * @brief QEO set output type for wave mode + * @param [in] base QEO base address + * @param [in] type qeo_wave_type_t + */ +static inline void qeo_wave_set_output_type(QEO_Type *base, qeo_wave_type_t type) +{ + base->WAVE.MODE = (base->WAVE.MODE & ~QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK) | QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_SET(type); +} + +/** + * @brief QEO set saddle type for wave mode + * @param [in] base QEO base address + * @param [in] standard true for standard saddle, false for triangular wave stacking + */ +static inline void qeo_wave_set_saddle_type(QEO_Type *base, bool standard) +{ + if (standard) { + base->WAVE.MODE &= ~QEO_WAVE_MODE_SADDLE_TYPE_MASK; + } else { + base->WAVE.MODE |= QEO_WAVE_MODE_SADDLE_TYPE_MASK; + } +} + +/** + * @brief QEO set phase shift for wave mode + * @param [in] base QEO base address + * @param [in] index wave index(0/1/2) + * @param [in] angle left shift angle + */ +static inline void qeo_wave_set_phase_shift(QEO_Type *base, uint8_t index, double angle) +{ + assert((angle >= 0) && (angle <= 360)); + uint32_t val = (uint32_t)(angle * 0x10000U / 360); + base->WAVE.PHASE_SHIFT[index] = QEO_WAVE_PHASE_SHIFT_VAL_SET(val); +} + +/** + * @brief QEO enable vd vq inject for wave mode + * @param [in] base QEO base address + * @param [in] index wave index(0/1/2) + * @param [in] vd_val vd value + * @param [in] vq_val vq value + */ +static inline void qeo_wave_enable_vd_vq_inject(QEO_Type *base, uint8_t index, int32_t vd_val, int32_t vq_val) +{ + (void) vd_val; + assert(index < 3); + base->WAVE.MODE |= (1U << (QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_SHIFT + index)); + base->WAVE.VD_VQ_INJECT[index] = QEO_WAVE_VD_VQ_INJECT_VQ_VAL_SET(vq_val) | QEO_WAVE_VD_VQ_INJECT_VD_VAL_SET(vq_val); +} + +/** + * @brief QEO disable vd vq inject for wave mode + * @param [in] base QEO base address + * @param [in] index wave index(0/1/2) + */ +static inline void qeo_wave_disable_vd_vq_inject(QEO_Type *base, uint8_t index) +{ + assert(index < 3); + base->WAVE.MODE &= ~(1U << (QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_SHIFT + index)); +} + +/** + * @brief QEO load vd vq inject value for wave mode + * @param [in] base QEO base address + */ +static inline void qeo_wave_load_vd_vq(QEO_Type *base) +{ + base->WAVE.VD_VQ_LOAD = QEO_WAVE_VD_VQ_LOAD_LOAD_MASK; +} + +/** + * @brief QEO enable amplitude for wave mode + * @param [in] base QEO base address + * @param [in] index wave index(0/1/2) + * @param [in] amp amplitude value + */ +static inline void qeo_wave_enable_amplitude(QEO_Type *base, uint8_t index, double amp) +{ + assert(amp > 0); + uint32_t val = (uint32_t)(amp * (1U << 12U)); + base->WAVE.AMPLITUDE[index] = QEO_WAVE_AMPLITUDE_EN_SCAL_MASK | QEO_WAVE_AMPLITUDE_AMP_VAL_SET(val); +} + +/** + * @brief QEO disable amplitude for wave mode + * @param [in] base QEO base address + * @param [in] index wave index(0/1/2) + */ +static inline void qeo_wave_disable_amplitude(QEO_Type *base, uint8_t index) +{ + base->WAVE.AMPLITUDE[index] &= ~QEO_WAVE_AMPLITUDE_EN_SCAL_MASK; +} + +/** + * @brief QEO set mid point shift for wave mode + * @param [in] base QEO base address + * @param [in] index wave index(0/1/2) + * @param [in] shift mid point shift value + */ +static inline void qeo_wave_set_mid_point_shift(QEO_Type *base, uint8_t index, double shift) +{ + int32_t val = (int32_t)(shift * (1U << 27U)); + base->WAVE.MID_POINT[index] = QEO_WAVE_MID_POINT_VAL_SET(val); +} + +/** + * @brief QEO set max limmit for wave mode + * @param [in] base QEO base address + * @param [in] index wave index(0/1/2) + * @param [in] limit0 limit0 value + * @param [in] limit1 limit1 value + */ +static inline void qeo_wave_set_max_limit(QEO_Type *base, uint8_t index, uint32_t limit0, uint32_t limit1) +{ + base->WAVE.LIMIT[index].MAX = QEO_WAVE_LIMIT_MAX_LIMIT0_SET(limit0) | QEO_WAVE_LIMIT_MAX_LIMIT1_SET(limit1); +} + +/** + * @brief QEO set min limmit for wave mode + * @param [in] base QEO base address + * @param [in] index wave index(0/1/2) + * @param [in] limit0 limit0 value + * @param [in] limit1 limit1 value + */ +static inline void qeo_wave_set_min_limit(QEO_Type *base, uint8_t index, uint32_t limit0, uint32_t limit1) +{ + base->WAVE.LIMIT[index].MIN = QEO_WAVE_LIMIT_MIN_LIMIT0_SET(limit0) | QEO_WAVE_LIMIT_MIN_LIMIT1_SET(limit1); +} + +/** + * @brief QEO set deadzone shift for wave mode + * @param [in] base QEO base address + * @param [in] index wave index(0/1/2) + * @param [in] shift deadzone shift value + */ +static inline void qeo_wave_set_deadzone_shift(QEO_Type *base, uint8_t index, int16_t shift) +{ + base->WAVE.DEADZONE_SHIFT[index] = QEO_WAVE_DEADZONE_SHIFT_VAL_SET(shift); +} + +/** + * @brief QEO get wave output value + * @param [in] base QEO base address + * @param [in] index wave index(0/1/2) + * @retval wave output value + */ +static inline uint16_t qeo_get_wave_output_val(QEO_Type *base, uint8_t index) +{ + if (index == 0) { + return QEO_DEBUG0_WAVE0_GET(base->DEBUG0); + } else if (index == 1) { + return QEO_DEBUG0_WAVE1_GET(base->DEBUG0); + } else if (index == 2) { + return QEO_DEBUG1_WAVE2_GET(base->DEBUG1); + } + return 0; +} + +/** + * @brief QEO wave get defalut mode config + * @param [in] base QEO base address + * @param [in] config qeo_wave_mode_t + */ +void qeo_wave_get_default_mode_config(QEO_Type *base, qeo_wave_mode_t *config); + +/** + * @brief QEO wave config mode + * @param [in] base QEO base address + * @param [in] config qeo_wave_mode_t + */ +void qeo_wave_config_mode(QEO_Type *base, qeo_wave_mode_t *config); + +/* ABZ API */ +/** + * @brief QEO set resolution lines for ABZ mode + * @param [in] base QEO base address + * @param [in] lines resolution lines + */ +static inline void qeo_abz_set_resolution_lines(QEO_Type *base, uint32_t lines) +{ + base->ABZ.RESOLUTION = QEO_ABZ_RESOLUTION_LINES_SET(lines); +} + +/** + * @brief QEO set phase shift for ABZ mode + * @param [in] base QEO base address + * @param [in] index ABZ index(0/1/2) + * @param [in] angle left shift angle + */ +static inline void qeo_abz_set_phase_shift(QEO_Type *base, uint8_t index, double angle) +{ + assert((angle >= 0) && (angle <= 360)); + uint32_t val = (uint32_t)(angle * 0x10000U / 360); + base->ABZ.PHASE_SHIFT[index] = QEO_ABZ_PHASE_SHIFT_VAL_SET(val); +} + +/** + * @brief QEO set max frequency for ABZ mode + * @param [in] base QEO base address + * @param [in] src_freq QEO(MOTO system) frequency + * @param [in] freq abz signal frequency (A pulse frequency) + * @retval status_success or status_invalid_argument + */ +hpm_stat_t qeo_abz_set_max_frequency(QEO_Type *base, uint32_t src_freq, uint32_t freq); + +/** + * @brief QEO set wdog frequency for ABZ mode + * @param [in] base QEO base address + * @param [in] src_freq QEO(MOTO system) frequency + * @param [in] freq wdog frequency + * @retval status_success or status_invalid_argument + */ +hpm_stat_t qeo_abz_set_wdog_frequency(QEO_Type *base, uint32_t src_freq, uint32_t freq); + +/** + * @brief QEO disable wdog for ABZ mode + * @param [in] base QEO base address + */ +static inline void qeo_abz_disable_wdog(QEO_Type *base) +{ + base->ABZ.MODE &= ~QEO_ABZ_MODE_EN_WDOG_MASK; +} + +/** + * @brief QEO config reverse edge for ABZ mode + * @param [in] base QEO base address + * @param [in] speed_pulse_negedge true for reverse edge point speed pulse's negedge + * false for reverse edge point between speed pulse's posedge and negedge, min period dedicated by the num line_width + * + * @note take effect when ABZ work on qeo_abz_output_pulse_revise mode + */ +static inline void qeo_abz_config_reverse_edge(QEO_Type *base, bool speed_pulse_negedge) +{ + if (speed_pulse_negedge) { + base->ABZ.MODE |= QEO_ABZ_MODE_REVERSE_EDGE_TYPE_MASK; + } else { + base->ABZ.MODE &= ~QEO_ABZ_MODE_REVERSE_EDGE_TYPE_MASK; + } +} + +/** + * @brief QEO sync position for ABZ mode + * @param [in] base QEO base address + * @param [in] lines ABZ line counter + * @param [in] sync_pos the position value to be synchronized + */ +void qeo_abz_position_sync(QEO_Type *base, uint32_t lines, uint32_t sync_pos); + +/** + * @brief QEO ABZ get default mode config + * @param [in] base QEO base address + * @param [in] config qeo_abz_mode_t + */ +void qeo_abz_get_default_mode_config(QEO_Type *base, qeo_abz_mode_t *config); + +/** + * @brief QEO ABZ config mode + * @param [in] base QEO base address + * @param [in] config qeo_abz_mode_t + */ +void qeo_abz_config_mode(QEO_Type *base, qeo_abz_mode_t *config); + +/* PWM API */ +/** + * @brief QEO set resolution lines for PWM mode + * @param [in] base QEO base address + * @param [in] lines resolution lines + */ +static inline void qeo_pwm_set_resolution_lines(QEO_Type *base, uint32_t lines) +{ + base->PWM.RESOLUTION = QEO_PWM_RESOLUTION_LINES_SET(lines); +} + +/** + * @brief QEO set phase shift for PWM mode + * @param [in] base QEO base address + * @param [in] index PWM index(0/1/2/3) + * @param [in] angle left shift angle + */ +static inline void qeo_pwm_set_phase_shift(QEO_Type *base, uint8_t index, double angle) +{ + assert((angle >= 0) && (angle <= 360)); + uint32_t val = (uint32_t)(angle * 0x10000U / 360); + base->PWM.PHASE_SHIFT[index] = QEO_PWM_PHASE_SHIFT_VAL_SET(val); +} + +/** + * @brief QEO PWM check if it is triggered by hardware to enter safety mode + * + * @note This bit is only valid if the hardware trigger source has not been cleared + * + * @param [in] base QEO base address + * @retval true or false + */ +static inline bool qeo_pwm_check_hardware_trig_safety(QEO_Type *base) +{ + return ((base->STATUS & QEO_STATUS_PWM_SAFETY_MASK) != 0) ? true : false; +} + +/** + * @brief QEO PWM select phase table + * @param [in] base QEO base address + * @param [in] positive true for using positive phase table, false for using negative phase table + */ +static inline void qeo_pwm_select_phase_table(QEO_Type *base, bool positive) +{ + if (positive) { + base->PWM.MODE &= ~QEO_PWM_MODE_REVISE_UP_DN_MASK; + } else { + base->PWM.MODE |= QEO_PWM_MODE_REVISE_UP_DN_MASK; + } +} + +/** + * @brief QEO PWM enter safety mode by software + * + * @note call qeo_pwm_software_exit_safety to exit safety mode + * + * @param [in] base QEO base address + */ +static inline void qeo_pwm_software_enter_safety(QEO_Type *base) +{ + base->PWM.MODE |= QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK; +} + +/** + * @brief QEO PWM exit safety mode by software + * @param [in] base QEO base address + */ +static inline void qeo_pwm_software_exit_safety(QEO_Type *base) +{ + base->PWM.MODE &= ~QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK; +} + +/** + * @brief QEO PWM get default mode config + * @param [in] base QEO base address + * @param [in] config qeo_pwm_mode_t + */ +void qeo_pwm_get_default_mode_config(QEO_Type *base, qeo_pwm_mode_t *config); + +/** + * @brief QEO PWM config mode + * @param [in] base QEO base address + * @param [in] config qeo_pwm_mode_t + */ +void qeo_pwm_config_mode(QEO_Type *base, qeo_pwm_mode_t *config); + +/** + * @brief QEO PWM get default safety table + * @param [in] base QEO base address + * @param [in] table qeo_pwm_safety_output_table_t + */ +void qeo_pwm_get_default_safety_table_config(QEO_Type *base, qeo_pwm_safety_output_table_t *table); + +/** + * @brief QEO PWM get default phase table + * @param [in] base QEO base address + * @param [in] table qeo_pwm_phase_output_table_t + */ +void qeo_pwm_get_default_phase_table_config(QEO_Type *base, qeo_pwm_phase_output_table_t *table); + +/** + * @brief QEO PWM config safety table + * @param [in] base QEO base address + * @param [in] table qeo_pwm_safety_output_table_t + */ +void qeo_pwm_config_safety_table(QEO_Type *base, qeo_pwm_safety_output_table_t *table); + +/** + * @brief QEO PWM onfig phase table + * @param [in] base QEO base address + * @param [in] index phase table index + * @param [in] table qeo_pwm_phase_output_table_t + */ +void qeo_pwm_config_phase_table(QEO_Type *base, uint8_t index, qeo_pwm_phase_output_table_t *table); + +/** + * @brief QEO enable software position inject + * @param [in] base QEO base address + */ +static inline void qeo_enable_software_position_inject(QEO_Type *base) +{ + base->POSTION_SEL |= QEO_POSTION_SEL_POSTION_SEL_MASK; +} + +/** + * @brief QEO software inject position + * @param [in] base QEO base address + * @param [in] position position value + */ +static inline void qeo_software_position_inject(QEO_Type *base, uint32_t position) +{ + base->POSTION_SOFTWARE = QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_SET(position); +} + +/** + * @brief QEO disable software position inject, QEO will using position from hardware + * @param [in] base QEO base address + */ +static inline void qeo_disable_software_position_inject(QEO_Type *base) +{ + base->POSTION_SEL &= ~QEO_POSTION_SEL_POSTION_SEL_MASK; +} + +/** + * @brief QEO check calculate finish status + * @param [in] base QEO base address + * @retval true or false + */ +static inline bool qeo_check_calculate_finish(QEO_Type *base) +{ + return (QEO_DEBUG1_QEO_FINISH_GET(base->DEBUG1) != 0) ? true : false; +} + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_QEO_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_rdc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_rdc_drv.h new file mode 100644 index 00000000000..cc118e6423b --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_rdc_drv.h @@ -0,0 +1,708 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_RDC_DRV_H +#define HPM_RDC_DRV_H + +#include "hpm_common.h" +#include "hpm_rdc_regs.h" +#include "hpm_soc_feature.h" + +/** + * @brief RDC driver APIs + * @defgroup rdc_interface RDC driver APIs + * @ingroup rdc_interfaces + * @{ + */ + + +#ifdef __cplusplus +extern "C" { +#endif +/** + * @name Initialization and Deinitialization + * @{ + */ + + +/** + * @brief Rdc output precision, use n points to form an excitation signal period. + * + */ +typedef enum rdc_output_precision { + rdc_output_precision_4_point = 0, + rdc_output_precision_8_point = 1, + rdc_output_precision_16_point = 2, + rdc_output_precision_32_point = 3, + rdc_output_precision_64_point = 4, + rdc_output_precision_128_point = 5, + rdc_output_precision_256_point = 6, + rdc_output_precision_512_point = 7, + rdc_output_precision_1024_point = 8, +} rdc_output_precision_t; + +/** + * @brief Pwm output period in samples + * + */ +typedef enum rdc_output_pwm_period { + rdc_output_pwm_period_1_sample = 0, + rdc_output_pwm_period_2_sample, + rdc_output_pwm_period_3_sample, + rdc_output_pwm_period_4_sample, + rdc_output_pwm_period_5_sample, + rdc_output_pwm_period_6_sample, + rdc_output_pwm_period_7_sample, + rdc_output_pwm_period_8_sample, + rdc_output_pwm_period_9_sample, + rdc_output_pwm_period_10_sample, + rdc_output_pwm_period_11_sample, + rdc_output_pwm_period_12_sample, + rdc_output_pwm_period_13_sample, + rdc_output_pwm_period_14_sample, + rdc_output_pwm_period_15_sample, + rdc_output_pwm_period_16_sample, +} rdc_output_pwm_period_t; + + + +/** + * @brief Rdc output mode + * + */ +typedef enum rdc_output_mode { + rdc_output_dac, + rdc_output_pwm +} rdc_output_mode_t; + +/** + * @brief Synchronize output trig adc position + * + */ +typedef enum rdc_sync_out_src { + rdc_sync_out_exc_0_ph = RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SET(0), + rdc_sync_out_exc_90_ph = RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SET(1), + rdc_sync_out_exc_180_ph = RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SET(2), + rdc_sync_out_exc_270_ph = RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SET(3), + rdc_sync_out_max = RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_MASK, + rdc_sync_out_min = RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_MASK, +} rdc_sync_out_src_t; + +/** + * @brief Select reference point of rectify signal + * + */ +typedef enum rdc_rectify_signal { + rdc_rectify_signal_exc_0_ph = 0, + rdc_rectify_signal_exc_90_ph = 1, + rdc_rectify_signal_exc_180_ph = 2, + rdc_rectify_signal_exc_270_ph = 3, + rdc_rectify_signal_external = 4, + rdc_rectify_signal_external_invert = 5, +} rdc_rectify_signal_t; + +/** + * @brief Time stamp selection for accumulation + * + */ +typedef enum rdc_acc_stamp_time { + rdc_acc_stamp_end_of_acc = 0, /**< End of accumulation */ + rdc_acc_stamp_start_of_acc = 1, /**< Start of accumulation */ + rdc_acc_stamp_center_of_acc = 2, /**< Center of accumulation */ +} rdc_acc_stamp_time_t; + +/** + * @brief Rdc trigger out channel 0 or channel 1 + * + */ +typedef enum rdc_output_trig_chn { + trigger_out_0 = 0, + trigger_out_1 = 1 +} rdc_output_trig_chn_t; + + +/** + * @brief Rdc input channel + * + */ +typedef enum rdc_input_acc_chn { + rdc_acc_chn_i = 0, + rdc_acc_chn_q = 1 +} rdc_input_acc_chn_t; + +/** + * @brief Rdc status flags + * + */ +typedef enum rdc_interrupt_stat { + acc_vld_i_stat = RDC_INT_EN_ACC_VLD_I_EN_MASK, + acc_vld_q_stat = RDC_INT_EN_ACC_VLD_Q_EN_MASK, + rising_delay_i_stat = RDC_INT_EN_RISING_DELAY_I_EN_MASK, + falling_delay_i_stat = RDC_INT_EN_FALLING_DELAY_I_EN_MASK, + rising_delay_q_stat = RDC_INT_EN_RISING_DELAY_Q_EN_MASK, + falling_delay_q_stat = RDC_INT_EN_FALLING_DELAY_Q_EN_MASK, + sample_rising_i_stat = RDC_INT_EN_SAMPLE_RISING_I_EN_MASK, + sample_falling_i_stat = RDC_INT_EN_SAMPLE_FALLING_I_EN_MASK, + sample_rising_q_stat = RDC_INT_EN_SAMPLE_RISING_Q_EN_MASK, + sample_falling_q_stat = RDC_INT_EN_SAMPLE_FALLING_Q_EN_MASK, + acc_vld_i_ovh_stat = RDC_INT_EN_ACC_VLD_I_OVH_EN_MASK, + acc_vld_q_ovh_stat = RDC_INT_EN_ACC_VLD_Q_OVH_EN_MASK, + acc_vld_i_ovl_stat = RDC_INT_EN_ACC_VLD_I_OVL_EN_MASK, + acc_vld_q_ovl_stat = RDC_INT_EN_ACC_VLD_Q_OVL_EN_MASK, + acc_amp_ovh_stat = RDC_INT_EN_ACC_AMP_OVH_EN_MASK, + acc_amp_ovl_stat = RDC_INT_EN_ACC_AMP_OVL_EN_MASK, +} rdc_interrupt_stat_t; + +/** + * @brief Rdc output configuration + * + */ +typedef struct rdc_output_cfg { + rdc_output_mode_t mode; /**< pwm or dac */ + uint32_t excitation_period_cycle; /**< The period of the excitation signal, in cycles */ + rdc_output_precision_t excitation_precision; /**< Excitation signal precision */ + rdc_output_pwm_period_t pwm_period; /**< Pwm period in samples */ + bool output_swap; /**< Swap output of PWM and DAC */ + int32_t amp_offset; /**< Offset for excitation, signed value*/ + uint16_t amp_man; /**< Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp */ + uint16_t amp_exp; /**< Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp */ + bool pwm_dither_enable; /**< Enable dither of pwm */ + bool pwm_exc_p_low_active; /**< Polarity of exc_p signal */ + bool pwm_exc_n_low_active; /**< Polarity of exc_n signal */ + bool trig_by_hw; /**< Hardware triggered excitation signal generation. Software triggering is required after shutdown */ + uint32_t hw_trig_delay; /**< Trigger in delay timming in bus cycle from rising edge of trigger signal */ + uint8_t dac_chn_i_sel; /**< Output channel selection for i_channel */ + uint8_t dac_chn_q_sel; /**< Output channel selection for q_channel */ + uint8_t pwm_deadzone_p; /**< Exc_p dead zone in clock cycle before swap */ + uint8_t pwm_deadzone_n; /**< Exc_n dead zone in clock cycle before swap */ +} rdc_output_cfg_t; + + +/** + * @brief Rdc input configuration + * + */ +typedef struct rdc_input_cfg { + rdc_rectify_signal_t rectify_signal_sel; /**< Select reference point of rectify signal */ + uint8_t acc_cycle_len; /**< Accumulate time, support on the fly change */ + rdc_acc_stamp_time_t acc_stamp; /**< Time stamp selection for accumulation */ + uint32_t acc_input_chn_i; /**< Input channel selection for i_channel */ + uint32_t acc_input_port_i; /**< Input port selection for i_channel */ + uint32_t acc_input_chn_q; /**< Input channel selection for q_channel */ + uint32_t acc_input_port_q; /**< Input port selection for q_channel */ +} rdc_input_cfg_t; + +/** + * @brief Accumulated configuration information + * + */ +typedef struct rdc_acc_cfg { + struct { + uint16_t continue_edge_num: 3; /**< Filtering val: 1 - 8 */ + uint16_t edge_distance: 6; /**< Minimum distance between two edges 0-63 */ + }; + uint8_t right_shift_without_sign; /**< Right shift without sign bit */ + bool error_data_remove; /**< Toxic accumulation data be removed */ + uint32_t exc_carrier_period; /**< The num in clock cycle for period of excitation 0-NULL others-cycles */ + uint32_t sync_delay_i; /**< Delay in clock cycle for synchronous signal, the value should less than half of exc_period.exc_period. */ + uint32_t sync_delay_q; /**< Delay in clock cycle for synchronous signal, the value should less than half of exc_period.exc_period. */ + uint32_t amp_max; /**< The maximum of acc amplitude */ + uint32_t amp_min; /**< The minimum of acc amplitude */ +} rdc_acc_cfg_t; + +/** @} */ + +/** + * @name RDC Control + * @{ + */ + +/** + * @brief Rdc output configuration, can be configured pwm output or dac output + * + * @param ptr @ref RDC_Type base + * @param cfg @ref rdc_output_cfg_t + */ +void rdc_output_config(RDC_Type *ptr, rdc_output_cfg_t *cfg); + +/** + * @brief Rdc input configuration, configuration of adc signal source and calculation parameters + * + * @param ptr @ref RDC_Type base + * @param cfg @ref rdc_input_cfg_t + */ +void rdc_input_config(RDC_Type *ptr, rdc_input_cfg_t *cfg); + +/** + * @brief Configuration accumulate time, support on the fly change + * + * @param ptr @ref RDC_Type base + * @param len accumulate time 0-255 + */ +static inline void rdc_set_acc_len(RDC_Type *ptr, uint8_t len) +{ + ptr->RDC_CTL = (ptr->RDC_CTL & (~RDC_RDC_CTL_ACC_LEN_MASK)) + | RDC_RDC_CTL_ACC_LEN_SET(len); +} + +/** + * @brief Enable accumulate calculation function + * + * @param ptr @ref RDC_Type base + */ +static inline void rdc_acc_enable(RDC_Type *ptr) +{ + ptr->RDC_CTL |= RDC_RDC_CTL_ACC_EN_MASK; +} + +/** + * @brief Disable accumulate calculation function + * + * @param ptr @ref RDC_Type base + */ +static inline void rdc_acc_disable(RDC_Type *ptr) +{ + ptr->RDC_CTL &= ~RDC_RDC_CTL_ACC_EN_MASK; +} + +/** + * @brief Get the accumulate value + * + * @param ptr @ref RDC_Type base + * @param chn @ref rdc_input_acc_chn_t + * @return uint32_t accumulate value + */ +uint32_t rdc_get_acc_avl(RDC_Type *ptr, rdc_input_acc_chn_t chn); + +/** + * @brief Output trigger configuration + * Lead time for trigger out0 or out1 from center of low level , this is a signed value + * @param ptr @ref RDC_Type base + * @param chn @ref rdc_output_trig_chn_t + * @param offset lead_time + */ +void rdc_output_trig_offset_config(RDC_Type *ptr, rdc_output_trig_chn_t chn, int32_t offset); + +/** + * @brief Enable output trigger configuration + * + * @param ptr @ref RDC_Type base + * @param chn @ref rdc_output_trig_chn_t + */ +void rdc_output_trig_enable(RDC_Type *ptr, rdc_output_trig_chn_t chn); + +/** + * @brief Disable rdc output trigger configuration + * + * @param ptr @ref RDC_Type base + * @param chn @ref rdc_output_trig_chn_t + */ +void rdc_output_trig_disable(RDC_Type *ptr, rdc_output_trig_chn_t chn); + +/** + * @brief Select output synchornize signal + * + * @param ptr @ref RDC_Type base + * @param sel @ref rdc_sync_out_src_t + */ +static inline void rdc_sync_output_trig_adc_cfg(RDC_Type *ptr, rdc_sync_out_src_t sel) +{ + ptr->SYNC_OUT_CTRL = sel; +} + +/** + * @brief Enable rdc excite signal + * + * @param ptr @ref RDC_Type base + */ +static inline void rdc_exc_enable(RDC_Type *ptr) +{ + ptr->RDC_CTL |= RDC_RDC_CTL_EXC_EN_MASK; +} + +/** + * @brief Disable rdc excite signal + * + * @param ptr @ref RDC_Type base + */ +static inline void rdc_exc_disable(RDC_Type *ptr) +{ + ptr->RDC_CTL &= ~RDC_RDC_CTL_EXC_EN_MASK; +} + +/** + * @brief Software triggered excitation signal output + * + * @param ptr @ref RDC_Type base + */ +static inline void rdc_output_trig_sw(RDC_Type *ptr) +{ + ptr->RDC_CTL |= RDC_RDC_CTL_EXC_START_MASK; +} + +/** + * @brief Get I-phase maximum + * + * @param ptr @ref RDC_Type base + * @retval - other max value + * - -1 illegal data + */ +int32_t rdc_get_i_maxval(RDC_Type *ptr); + +/** + * @brief Clear Maximum + * + * @param ptr @ref RDC_Type base + */ +static inline void rdc_clear_i_maxval(RDC_Type *ptr) +{ + ptr->MAX_I = 0; +} + +/** + * @brief Get I-phase minimum + * + * @param ptr @ref RDC_Type base + * @retval - other max value + * - -1 illegal data + */ +int32_t rdc_get_i_minval(RDC_Type *ptr); + +/** + * @brief Clear I-phase minimum + * + * @param ptr @ref RDC_Type base + */ +static inline void rdc_clear_i_minval(RDC_Type *ptr) +{ + ptr->MIN_I = 0; +} + +/** + * @brief Set Acc sync delay + * + * @param ptr @ref RDC_Type base + * @param chn @ref rdc_input_acc_chn_t + * @param delay delay tick + */ +void rdc_set_acc_sync_delay(RDC_Type *ptr, rdc_input_acc_chn_t chn, uint32_t delay); + +/** + * @brief Delay bettween the delyed trigger and + * the first pwm pulse in clock cycle + * + * @param ptr @ref RDC_Type base + * @retval delay tick + */ +static inline uint32_t rdc_get_sync_output_delay(RDC_Type *ptr) +{ + return RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_GET(ptr->SYNC_OUT_CTRL); +} + +/** + * @brief Get Q-phase maximum + * + * @param ptr @ref RDC_Type base + * @retval - other max value + * - -1 illegal data + */ +int32_t rdc_get_q_maxval(RDC_Type *ptr); + +/** + * @brief Clear Q-phase maxval + * + * @param ptr @ref RDC_Type base + */ +static inline void rdc_clear_q_maxval(RDC_Type *ptr) +{ + ptr->MAX_Q = 0; +} + +/** + * @brief Get Q-phase Minval + * + * @param ptr @ref RDC_Type base + * @retval - other max value + * - -1 illegal data + */ +int32_t rdc_get_q_minval(RDC_Type *ptr); + +/** + * @brief Clear Q-phase Minval + * + * @param ptr @ref RDC_Type base + */ +static inline void rdc_clear_q_minval(RDC_Type *ptr) +{ + ptr->MIN_Q = 0; +} + +/** + * @brief The offset setting for edge detection of the i_channel or q_channel + * + * @param ptr @ref RDC_Type base + * @param chn @ref rdc_input_acc_chn_t + * @param offset offset value + */ +void rdc_set_edge_detection_offset(RDC_Type *ptr, rdc_input_acc_chn_t chn, int32_t offset); + +/** + * @brief RDC set accumulate configuration + * + * @param ptr @ref RDC_Type base + * @param cfg @ref rdc_acc_cfg_t + */ +void rdc_set_acc_config(RDC_Type *ptr, rdc_acc_cfg_t *cfg); + +/** + * @brief Get delay in clock cycle between excitation synchrnous signal and rising edge of i_channel data + * + * @param ptr @ref RDC_Type base + * @retval clock cycle + */ +static inline uint32_t rdc_get_rise_delay_i(RDC_Type *ptr) +{ + return RDC_RISE_DELAY_I_RISE_DELAY_GET(ptr->RISE_DELAY_I); +} + +/** + * @brief Get delay in clock cycle between excitation synchrnous signal and fall edge of i_channel data + * + * @param ptr @ref RDC_Type base + * @retval clock cycle + */ +static inline uint32_t rdc_get_fall_delay_i(RDC_Type *ptr) +{ + return RDC_FALL_DELAY_I_FALL_DELAY_GET(ptr->FALL_DELAY_I); +} + +/** + * @brief Get sample value on rising edge of rectify signal + * + * @param ptr @ref RDC_Type base + * @retval clock cycle + */ +static inline uint32_t rdc_get_sample_rise_i(RDC_Type *ptr) +{ + return RDC_SAMPLE_RISE_I_VALUE_GET(ptr->SAMPLE_RISE_I); +} + +/** + * @brief Get sample value on falling edge of rectify signal + * + * @param ptr @ref RDC_Type base + * @retval clock cycle + */ +static inline uint32_t rdc_get_sample_fall_i(RDC_Type *ptr) +{ + return RDC_SAMPLE_FALL_I_VALUE_GET(ptr->SAMPLE_FALL_I); +} + +/** + * @brief Get sample number during the positive of rectify signal + * + * @param ptr @ref RDC_Type base + * @retval counter + */ +static inline uint32_t rdc_get_acc_cnt_positive_i(RDC_Type *ptr) +{ + return RDC_ACC_CNT_I_CNT_POS_GET(ptr->ACC_CNT_I); +} + +/** + * @brief Get sample number during the negtive of rectify signal + * + * @param ptr @ref RDC_Type base + * @retval counter + */ +static inline uint32_t rdc_get_acc_cnt_negative_i(RDC_Type *ptr) +{ + return RDC_ACC_CNT_I_CNT_POS_GET(ptr->ACC_CNT_I); +} + +/** + * @brief Get Negative sample counter during positive rectify signal + * + * @param ptr @ref RDC_Type base + * @retval counter + */ +static inline uint32_t rdc_get_sign_cnt_poitive_i(RDC_Type *ptr) +{ + return RDC_SIGN_CNT_I_CNT_POS_GET(ptr->SIGN_CNT_I); +} + +/** + * @brief Get Positive sample counter during negative rectify signal + * + * @param ptr @ref RDC_Type base + * @retval counter + */ +static inline uint32_t rdc_get_sign_cnt_negative_i(RDC_Type *ptr) +{ + return RDC_SIGN_CNT_I_CNT_NEG_GET(ptr->SIGN_CNT_I); +} + +/** + * @brief Get delay in clock cycle between excitation synchrnous signal and rising edge of q_channel data + * + * @param ptr @ref RDC_Type base + * @retval cycles + */ +static inline uint32_t rdc_get_rise_delay_q(RDC_Type *ptr) +{ + return RDC_RISE_DELAY_Q_RISE_DELAY_GET(ptr->RISE_DELAY_Q); +} + +/** + * @brief Get delay in clock cycle between excitation synchrnous signal and falling edge of q_channel data + * + * @param ptr @ref RDC_Type base + * @retval cycles + */ +static inline uint32_t rdc_get_fall_delay_q(RDC_Type *ptr) +{ + return RDC_FALL_DELAY_Q_FALL_DELAY_GET(ptr->FALL_DELAY_Q); +} + +/** + * @brief Get q channel sample value on rising edge of rectify signal + * + * @param ptr @ref RDC_Type base + * @retval cycles + */ +static inline uint32_t rdc_get_sample_rise_q(RDC_Type *ptr) +{ + return RDC_SAMPLE_RISE_Q_VALUE_GET(ptr->SAMPLE_RISE_Q); +} + +/** + * @brief Get q channel sample value on falling edge of rectify signal + * + * @param ptr @ref RDC_Type base + * @retval cycles + */ +static inline uint32_t rdc_get_sample_fall_q(RDC_Type *ptr) +{ + return RDC_SAMPLE_FALL_Q_VALUE_GET(ptr->SAMPLE_FALL_Q); +} + +/** + * @brief Get q channel sample number during the positive of rectify signal + * + * @param ptr @ref RDC_Type base + * @retval number + */ +static inline uint32_t rdc_get_acc_cnt_positive_q(RDC_Type *ptr) +{ + return RDC_ACC_CNT_Q_CNT_POS_GET(ptr->ACC_CNT_Q); +} + +/** + * @brief Get q channel sample number during the negtive of rectify signal + * + * @param ptr @ref RDC_Type base + * @retval number + */ +static inline uint32_t rdc_get_acc_cnt_negative_q(RDC_Type *ptr) +{ + return RDC_ACC_CNT_Q_CNT_POS_GET(ptr->ACC_CNT_Q); +} + +/** + * @brief Get q channel negative sample counter during positive rectify signal + * + * @param ptr @ref RDC_Type base + * @retval counter + */ +static inline uint32_t rdc_get_sign_cnt_poitive_q(RDC_Type *ptr) +{ + return RDC_SIGN_CNT_Q_CNT_POS_GET(ptr->SIGN_CNT_Q); +} + +/** + * @brief Get q channel sample number during the negtive of rectify signal + * + * @param ptr @ref RDC_Type base + * @retval counter + */ +static inline uint32_t rdc_get_sign_cnt_negative_q(RDC_Type *ptr) +{ + return RDC_SIGN_CNT_Q_CNT_NEG_GET(ptr->SIGN_CNT_Q); +} + +/** + * @brief Enables configured interrupts + * + * @param ptr @ref RDC_Type base + * @param status @ref rdc_interrupt_stat_t + */ +static inline void rdc_interrupt_config(RDC_Type *ptr, uint32_t status) +{ + ptr->INT_EN |= status; +} + +/** + * @brief Clear interrupts configured + * + * @param ptr @ref RDC_Type base + * @param status @ref rdc_interrupt_stat_t + */ +static inline void rdc_interrupt_reset_config(RDC_Type *ptr, uint32_t status) +{ + ptr->INT_EN &= ~status; +} + +/** + * @brief Enable rdc interrupt + * + * @param ptr @ref RDC_Type base + */ +static inline void rdc_interrupt_enable(RDC_Type *ptr) +{ + ptr->INT_EN |= RDC_INT_EN_INT_EN_MASK; +} + +/** + * @brief Disable rdc interrupt + * + * @param ptr @ref RDC_Type base + */ +static inline void rdc_interrupt_disable(RDC_Type *ptr) +{ + ptr->INT_EN &= ~RDC_INT_EN_INT_EN_MASK; +} + +/** + * @brief Clear interrupt flag bits + * + * @param ptr @ref RDC_Type base + * @param mask @ref rdc_interrupt_stat_t + */ +static inline void rdc_interrupt_clear_flag_bits(RDC_Type *ptr, uint32_t mask) +{ + ptr->ADC_INT_STATE &= mask; +} + +/** + * @brief Get the interrupt status object + * + * @param ptr @ref RDC_Type base + * @return @ref rdc_interrupt_stat_t + */ +static inline uint32_t get_interrupt_status(RDC_Type *ptr) +{ + return ptr->ADC_INT_STATE; +} + +/** @} */ + +#ifdef __cplusplus +} +#endif + +/** @} */ +#endif /* HPM_ADC12_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_rtc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_rtc_drv.h index a959fef11d7..d40900ae407 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_rtc_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_rtc_drv.h @@ -17,7 +17,7 @@ #include "hpm_common.h" #include "hpm_rtc_regs.h" -#include +#include /** * @brief RTC alarm configuration @@ -70,6 +70,15 @@ hpm_stat_t rtc_config_alarm(RTC_Type *base, rtc_alarm_config_t *config); */ time_t rtc_get_time(RTC_Type *base); + +/** + * @brief Get accurate time return by RTC module + * @param [in] base RTC base address + * + * @return accurate time(including second and subsecond) + */ +struct timeval rtc_get_timeval(RTC_Type *base); + /** * @brief Enable RTC alarm interrupt * @param [in] base RTC base address @@ -94,7 +103,7 @@ static inline void rtc_enable_alarm_interrupt(RTC_Type *base, uint32_t index, bo } /** - * @brief Clear RTC alarm flag + * @brief Clear RTC alarm flag based on alarm index * @param [in] base RTC base address * @param [in] index RTC alarm index, valid value is 0 or 1 */ @@ -108,6 +117,16 @@ static inline void rtc_clear_alarm_flag(RTC_Type *base, uint32_t index) base->ALARM_FLAG = mask; } +/** + * @brief Clear RTC alarm flags based on flag masks + * @param [in] base RTC base address + * @param [in] masks RTC alarm masks + */ +static inline void rtc_clear_alarm_flags(RTC_Type *base, uint32_t masks) +{ + base->ALARM_FLAG = masks; +} + /** * @brief Check whether RTC alarm flag is set or not * @param [in] base RTC base address @@ -124,6 +143,15 @@ static inline bool rtc_is_alarm_flag_asserted(RTC_Type *base, uint32_t index) return IS_HPM_BITMASK_SET(base->ALARM_FLAG, mask); } +/** + * @brief Get the RTC alarm flags + * @param [in] base RTC base address + * @return RTC alarm flags + */ +static inline uint32_t rtc_get_alarm_flags(RTC_Type *base) +{ + return base->ALARM_FLAG; +} #ifdef __cplusplus } diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdm_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdm_drv.h index 184bd46681a..3c5f54b9254 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdm_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdm_drv.h @@ -11,6 +11,13 @@ #include "hpm_common.h" #include "hpm_sdm_regs.h" +/** + * @brief SDM APIs + * @defgroup sdm_interface SDM driver APIs + * @ingroup sdm_interfaces + * @{ + */ + /* defined channel mask macro */ #define SAMPLING_MODE_MASK (0x7U) #define CHN_SAMPLING_MODE_SHIFT(ch) ((ch) * 3U + SDM_CTRL_CHMD_SHIFT) @@ -39,8 +46,8 @@ typedef enum { } sdm_filter_type_t; typedef struct { - bool clk_signal_sync; - bool data_signal_sync; + uint8_t clk_signal_sync; /* clk sync for channel */ + uint8_t data_signal_sync; /* data sync for channel */ bool interrupt_en; } sdm_control_t; diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdxc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdxc_drv.h index 9c824d1d8b0..e4b4bd89a46 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdxc_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdxc_drv.h @@ -21,6 +21,57 @@ #include "hpm_sdxc_regs.h" #include "hpm_sdxc_soc_drv.h" +/** + * @brief Generic Definitions + * @note: + * If the Host support 1.8V, it means: + * 1. For SD card, it supports: + * - SDR12 + * - SDR25 + * - SDR50 + * - SDR104 + * - DDR50 + * 2. For eMMC, it supports: + * - DDR50 + * - HS200 + * - HS400 (if 8-bit is supported as well) + */ +#define SDXC_HOST_SUPPORT_1V8 (1UL << 0) /**< SDXC Host support 1.8v */ +#define SDXC_HOST_SUPPORT_4BIT (1UL << 1) /**< SDXC Host support 4bit */ +#define SDXC_HOST_SUPPORT_8BIT (1UL << 2) /**< SDXC Host support 8bit */ +#define SDXC_HOST_SUPPORT_EMMC (1UL << 3) /**< SDXC Host support EMMC */ + +/** + * @brief SDXC Pin features + */ +#define SDXC_HOST_SUPPORT_CD (1UL << 16) /**< SDXC Host support Card detection */ +#define SDXC_HOST_SUPPORT_VSEL (1UL << 17) /**< SDXC Host support Voltage Selection */ +#define SDXC_HOST_SUPPORT_PWR (1UL << 18) /**< SDXC Host support Power Switch */ +#define SDXC_HOST_SUPPORT_WP (1UL << 19) /**< SDXC Host support Write Protection */ +#define SDXC_HOST_SUPPORT_RST (1UL << 20) /**< SDXC Host support Reset Pin */ +#define SDXC_HOST_SUPPORT_DS (1UL << 21) /**< SDXC Host support Data Strobe */ + +/** + * @brief SDXC Pin is native or from GPIO + */ +#define SDXC_HOST_CD_IN_IP (SDXC_HOST_SUPPORT_CD << 8) /**< Card detection is controlled by IP */ +#define SDXC_HOST_VSEL_IN_IP (SDXC_HOST_SUPPORT_VSEL << 8) /**< Voltage selection is controlled by IP */ +#define SDXC_HOST_PWR_IN_IP (SDXC_HOST_SUPPORT_PWR << 8) /**< Power switch is controlled by IP */ +#define SDXC_HOST_WP_IN_IP (SDXC_HOST_SUPPORT_WP << 8) /**< Write protection is controlled by IP */ +#define SDXC_HOST_RST_IN_IP (SDXC_HOST_SUPPORT_RST << 8) /**< Reset Pin is controlled by IP */ + +/** + * @brief SDXC GPIO pin polarity + * If polarity is 0, it means: + * GPIO level 0 means disabled, 1 means enabled + * If polarity is 1, it meansL: + * GPIO level 0 means enabled, 1 means disabled + */ +#define SDXC_HOST_VSEL_PIN_POLARITY (SDXC_HOST_SUPPORT_CD << 16) +#define SDXC_HOST_CD_PIN_POLARITY (SDXC_HOST_VSEL_IN_IP << 16) +#define SDXC_HOST_PWR_PIN_POLARITY (SDXC_HOST_SUPPORT_PWR << 16) +#define SDXC_HOST_WP_PIN_POLARITY (SDXC_HOST_SUPPORT_WP << 16) +#define SDXC_HOST_RST_IN_POLARITY (SDXC_HOST_SUPPORT_DS << 16) /** * @brief Command Response Type Selection @@ -123,18 +174,18 @@ typedef enum _sdxc_speed_mode { * @brief SDXC auto command types */ typedef enum _sdxc_auto_cmd_sel { - sdxc_auto_cmd_disabled = 0U, /**< Auto Command type: Disabled */ - sdxc_auto_cmd12_enabled = 1U, /**< Auto Command type: CMD12 enabled */ - sdxc_auto_cmd23_enabled = 2U, /**< Auto Command type: CMD23 enabled */ - sdxc_auto_cmd_auto_select = 3U, /**< Auto Command type: AUto selected */ + sdxc_auto_cmd_disabled = 0U, /**< Auto Command type: Disabled */ + sdxc_auto_cmd12_enabled = 1U, /**< Auto Command type: CMD12 enabled */ + sdxc_auto_cmd23_enabled = 2U, /**< Auto Command type: CMD23 enabled */ + sdxc_auto_cmd_auto_select = 3U, /**< Auto Command type: Auto selected */ } sdxc_auto_cmd_sel_t; /** - * @brief SDXC trnasfer direction options + * @brief SDXC transfer direction options */ typedef enum _sdxc_xfer_direction { - sdxc_xfer_dir_write, - sdxc_xfer_dir_read, + sdxc_xfer_dir_write = 0, + sdxc_xfer_dir_read = 1, } sdxc_xfer_direction_t; /** @@ -142,11 +193,10 @@ typedef enum _sdxc_xfer_direction { */ typedef enum _sdxc_command_type { sdxc_cmd_type_normal_cmd = 0U, - sdxc_cmd_type_suspend_cmd, - sdxc_cmd_tye_resume_cmd, - sdxc_cmd_type_abort_cmd, - sdxc_cmd_type_empty, - + sdxc_cmd_type_suspend_cmd = 1U, + sdxc_cmd_tye_resume_cmd = 2U, + sdxc_cmd_type_abort_cmd = 3U, + sdxc_cmd_type_empty = 4U, } sdxc_command_type_t; /** @@ -162,17 +212,17 @@ typedef enum _sdxc_command_type { */ typedef enum _sdxc_boot_mode { sdxc_boot_mode_normal = 0, - sdxc_boot_mode_alternative + sdxc_boot_mode_alternative = 1, } sdxc_boot_mode_t; /** * @brief SDXC response types */ typedef enum _sdxc_response_type { - sdxc_response_type_no_resp, - sdxc_response_type_resp_len_136bit, - sdxc_response_type_resp_len_48bit, - sdxc_response_type_resp_len_48bit_check_busy, + sdxc_response_type_no_resp = 0, + sdxc_response_type_resp_len_136bit = 1, + sdxc_response_type_resp_len_48bit = 2, + sdxc_response_type_resp_len_48bit_check_busy = 3, } sdxc_response_type_t; #define SDXC_CMD_RESP_NO_RESPONSE (0UL << SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT) @@ -201,39 +251,42 @@ typedef enum _sdxc_response_type { * @brief SDXC error codes */ enum { - status_sdxc_busy = MAKE_STATUS(status_group_sdxc, 0), /**< SDXC is busy */ - status_sdxc_error = MAKE_STATUS(status_group_sdxc, 1), /**< SDXC error */ - status_sdxc_send_cmd_failed = MAKE_STATUS(status_group_sdxc, 2), /**< SDXC command failed */ - status_sdxc_cmd_timeout_error = MAKE_STATUS(status_group_sdxc, 3), /**< SDXC command timed out */ - status_sdxc_cmd_crc_error = MAKE_STATUS(status_group_sdxc, 4), /**< SDXC command CRC error */ - status_sdxc_cmd_end_bit_error = MAKE_STATUS(status_group_sdxc, 5), /**< SDXC command end bit error */ - status_sdxc_cmd_index_error = MAKE_STATUS(status_group_sdxc, 6), /**< SDXC command index error */ - status_sdxc_data_timeout_error = MAKE_STATUS(status_group_sdxc, 7), /**< SDXC data timeout error */ - status_sdxc_data_crc_error = MAKE_STATUS(status_group_sdxc, 8), /**< SDXC data CRC error */ - status_sdxc_data_end_bit_error = MAKE_STATUS(status_group_sdxc, 9), /**< SDXC data end bit error */ - status_sdxc_auto_cmd_error = MAKE_STATUS(status_group_sdxc, 10), /**< SDXC auto command error */ - status_sdxc_adma_error = MAKE_STATUS(status_group_sdxc, 11), /**< SDXC ADMA error */ - status_sdxc_tuning_error = MAKE_STATUS(status_group_sdxc, 12), /**< SDXC tuning error */ - status_sdxc_response_error = MAKE_STATUS(status_group_sdxc, 13), /**< SDXC response error */ - status_sdxc_boot_ack_error = MAKE_STATUS(status_group_sdxc, 14), /**< SDXC boot ack error */ - status_sdxc_retuning_request = MAKE_STATUS(status_group_sdxc, 15), /**< SDXC retuning request */ - status_sdxc_autocmd_cmd12_not_exec = MAKE_STATUS(status_group_sdxc, 16), /**< SDXC Auto CMD12 command not executed */ - status_sdxc_autocmd_cmd_timeout_error = MAKE_STATUS(status_group_sdxc, 17), /**< SDXC Auto CMD timed out */ - status_sdxc_autocmd_cmd_crc_error = MAKE_STATUS(status_group_sdxc, 18), /**< SDXC Auto CMD crc error */ - status_sdxc_autocmd_end_bit_error = MAKE_STATUS(status_group_sdxc, 19), /**< SDXC Auto CMD end bit error */ - status_sdxc_autocmd_cmd_index_error = MAKE_STATUS(status_group_sdxc, 20), /**< SDXC Auto CMD index error */ - status_sdxc_autocmd_cmd_response_error = MAKE_STATUS(status_group_sdxc, 21), /**< SDXC Auto CMD response error */ - status_sdxc_autocmd_cmd_not_issued_auto_cmd12 = MAKE_STATUS(status_group_sdxc, 22), /**< SDXC Auto CMD not issued auto CMD12 */ - status_sdxc_unsupported = MAKE_STATUS(status_group_sdxc, 23), /**< SDXC unsupported operation */ - status_sdxc_transfer_data_completed = MAKE_STATUS(status_group_sdxc, 24), /**< SDXC transfer data completed */ - status_sdxc_send_cmd_successful = MAKE_STATUS(status_group_sdxc, 25), /**< SDXC send command succedded */ - status_sdxc_transfer_dma_completed = MAKE_STATUS(status_group_sdxc, 26), /**< SDXC transfer DMA completed */ - status_sdxc_transfer_data_failed = MAKE_STATUS(status_group_sdxc, 27), /**< SDXC transfer data failed */ - status_sdxc_dma_addr_unaligned = MAKE_STATUS(status_group_sdxc, 28), /**< SDXC DMA address unaligned */ - status_sdxc_tuning_failed = MAKE_STATUS(status_group_sdxc, 29), /**< SDXC tuning failed */ - status_sdxc_card_removed = MAKE_STATUS(status_group_sdxc, 30), /**< SDXC Card removed */ - status_sdxc_non_recoverable_error = MAKE_STATUS(status_group_sdxc, 30), /**< SDXC non-recoverable error */ - status_sdxc_recoverable_error = MAKE_STATUS(status_group_sdxc, 31), /**< SDXC recoverable error */ + status_sdxc_busy = MAKE_STATUS(status_group_sdxc, 0), /**< SDXC is busy */ + status_sdxc_error = MAKE_STATUS(status_group_sdxc, 1), /**< SDXC error */ + status_sdxc_send_cmd_failed = MAKE_STATUS(status_group_sdxc, 2), /**< SDXC command failed */ + status_sdxc_cmd_timeout_error = MAKE_STATUS(status_group_sdxc, 3), /**< SDXC command timed out */ + status_sdxc_cmd_crc_error = MAKE_STATUS(status_group_sdxc, 4), /**< SDXC command CRC error */ + status_sdxc_cmd_end_bit_error = MAKE_STATUS(status_group_sdxc, 5), /**< SDXC command end bit error */ + status_sdxc_cmd_index_error = MAKE_STATUS(status_group_sdxc, 6), /**< SDXC command index error */ + status_sdxc_data_timeout_error = MAKE_STATUS(status_group_sdxc, 7), /**< SDXC data timeout error */ + status_sdxc_data_crc_error = MAKE_STATUS(status_group_sdxc, 8), /**< SDXC data CRC error */ + status_sdxc_data_end_bit_error = MAKE_STATUS(status_group_sdxc, 9), /**< SDXC data end bit error */ + status_sdxc_auto_cmd_error = MAKE_STATUS(status_group_sdxc, 10), /**< SDXC auto command error */ + status_sdxc_adma_error = MAKE_STATUS(status_group_sdxc, 11), /**< SDXC ADMA error */ + status_sdxc_tuning_error = MAKE_STATUS(status_group_sdxc, 12), /**< SDXC tuning error */ + status_sdxc_response_error = MAKE_STATUS(status_group_sdxc, 13), /**< SDXC response error */ + status_sdxc_boot_ack_error = MAKE_STATUS(status_group_sdxc, 14), /**< SDXC boot ack error */ + status_sdxc_retuning_request = MAKE_STATUS(status_group_sdxc, 15), /**< SDXC retuning request */ + /* SDXC Auto CMD12 command not executed */ + status_sdxc_autocmd_cmd12_not_exec = MAKE_STATUS(status_group_sdxc, 16), + status_sdxc_autocmd_cmd_timeout_error = MAKE_STATUS(status_group_sdxc, 17), /**< SDXC Auto CMD timed out */ + status_sdxc_autocmd_cmd_crc_error = MAKE_STATUS(status_group_sdxc, 18), /**< SDXC Auto CMD crc error */ + status_sdxc_autocmd_end_bit_error = MAKE_STATUS(status_group_sdxc, 19), /**< SDXC Auto CMD end bit error */ + status_sdxc_autocmd_cmd_index_error = MAKE_STATUS(status_group_sdxc, 20), /**< SDXC Auto CMD index error */ + status_sdxc_autocmd_cmd_response_error = MAKE_STATUS(status_group_sdxc, 21), /**< SDXC Auto CMD response error */ + /* SDXC Auto CMD not issued auto CMD12 */ + status_sdxc_autocmd_cmd_not_issued_auto_cmd12 = MAKE_STATUS(status_group_sdxc, 22), + /**< SDXC unsupported operation */ + status_sdxc_unsupported = MAKE_STATUS(status_group_sdxc, 23), + status_sdxc_transfer_data_completed = MAKE_STATUS(status_group_sdxc, 24), /**< SDXC transfer data completed */ + status_sdxc_send_cmd_successful = MAKE_STATUS(status_group_sdxc, 25), /**< SDXC send command succeeded */ + status_sdxc_transfer_dma_completed = MAKE_STATUS(status_group_sdxc, 26), /**< SDXC transfer DMA completed */ + status_sdxc_transfer_data_failed = MAKE_STATUS(status_group_sdxc, 27), /**< SDXC transfer data failed */ + status_sdxc_dma_addr_unaligned = MAKE_STATUS(status_group_sdxc, 28), /**< SDXC DMA address unaligned */ + status_sdxc_tuning_failed = MAKE_STATUS(status_group_sdxc, 29), /**< SDXC tuning failed */ + status_sdxc_card_removed = MAKE_STATUS(status_group_sdxc, 30), /**< SDXC Card removed */ + status_sdxc_non_recoverable_error = MAKE_STATUS(status_group_sdxc, 30), /**< SDXC non-recoverable error */ + status_sdxc_recoverable_error = MAKE_STATUS(status_group_sdxc, 31), /**< SDXC recoverable error */ }; /** @@ -471,6 +524,32 @@ typedef struct _sdxc_boot_config { bool enable_auto_stop_at_block_gap; } sdxc_boot_config_t; +typedef struct { + void (*card_inserted)(SDXC_Type *base, void *user_data); + void (*card_removed)(SDXC_Type *base, void *user_data); + void (*sdio_interrupt)(SDXC_Type *base, void *user_data); + void (*block_gap)(SDXC_Type *base, void *user_data); + void (*xfer_complete)(SDXC_Type *base, void *user_data); +} sdxc_xfer_callback_t; + +typedef struct { + sdxc_data_t *volatile data; + sdxc_command_t *volatile cmd; + volatile uint32_t xferred_words; + sdxc_xfer_callback_t callback; + void *user_data; +} sdxc_handle_t; + +typedef hpm_stat_t (*sdxc_xfer_func_t)(SDXC_Type *base, sdxc_xfer_t *content); + +typedef struct { + SDXC_Type *base; + uint32_t src_clk_hz; + sdxc_config_t config; + sdxc_capabilities_t capability; + sdxc_xfer_func_t xfer; +} sdxc_host_t; + #if defined(__cplusplus) extern "C" { @@ -497,6 +576,17 @@ static inline bool sdxc_is_card_inserted(SDXC_Type *base) return IS_HPM_BITMASK_SET(base->PSTATE, SDXC_PSTATE_CARD_INSERTED_MASK); } +/** + * @brief Check whether SD card is Write Protected + * @retval SD Card Write Protection status + * @arg true SD Card is Write protected + * @arg false SD card is not Write Protected + */ +static inline bool sdxc_is_write_protected(SDXC_Type *base) +{ + return IS_HPM_BITMASK_CLR(base->PSTATE, SDXC_PSTATE_WR_PROTECT_SW_LVL_MASK); +} + /** * @brief Clear SDXC interrupt status * @param [in] base SDXC base address @@ -635,6 +725,21 @@ static inline void sdxc_enable_high_speed(SDXC_Type *base, bool enable) } } +/** + * @brief Control the SDXC power pin + * + * @param [in] base SDXC base address + * @param [in] enable Flas to control the SDXC power pin + */ +static inline void sdxc_enable_power(SDXC_Type *base, bool enable) +{ + if (enable) { + base->PROT_CTRL |= SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_MASK; + } else { + base->PROT_CTRL &= ~SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_MASK; + } +} + /** * @brief Enable SDXC asynchronous interrupt support * @param [in] base SDXC base address @@ -813,6 +918,47 @@ static inline void sdxc_enable_auto_tuning(SDXC_Type *base, bool enable) } } +/** + * @brief Stop Clock During Phase Code Change + * + * @param [in] base SDXC base address + * @param [in] enable Flag to determine whether stopping clock during phase code change + */ +static inline void sdxc_stop_clock_during_phase_code_change(SDXC_Type *base, bool enable) +{ + if (enable) { + base->AUTO_TUNING_CTRL |= SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_MASK; + } else { + base->AUTO_TUNING_CTRL &= ~SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_MASK; + } +} + +/** + * @brief Set The delay cycles during phase switching and stable clock out + * + * @param [in] base SDXC base address + * @param [in] delay_cnt Delay cycles + */ +static inline void sdxc_set_post_change_delay(SDXC_Type *base, uint8_t delay_cnt) +{ + base->AUTO_TUNING_CTRL = (base->AUTO_TUNING_CTRL & ~SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_MASK) \ + | SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SET(delay_cnt - 1U); +} + +/** + * @brief Enable EMMC support + * @param [in] base SDXC base address + * @param [in] enable Flag to enable/disable EMMC support + */ +static inline void sdxc_enable_emmc_support(SDXC_Type *base, bool enable) +{ + if (enable) { + base->EMMC_BOOT_CTRL |= SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_MASK; + } else { + base->EMMC_BOOT_CTRL &= ~SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_MASK; + } +} + /** * @brief Enable/Disable SDXC MMC boot * @param [in] base SDXC base address @@ -899,7 +1045,7 @@ hpm_stat_t sdxc_send_command(SDXC_Type *base, sdxc_command_t *cmd); /** * @brief Receive command response * @param [in] base SDXC base address - * @param [in/out] cmd Command + * @param [in,out] cmd Command * @return status_success if no error happened */ hpm_stat_t sdxc_receive_cmd_response(SDXC_Type *base, sdxc_command_t *cmd); @@ -937,8 +1083,10 @@ void sdxc_set_data_config(SDXC_Type *base, sdxc_xfer_direction_t data_dir, uint3 * @param [in] flags Flags for AMDA transfer * @retval API execution status */ -hpm_stat_t sdxc_set_adma_table_config(SDXC_Type *base, sdxc_adma_config_t *dma_cfg, - sdxc_data_t *data_cfg, uint32_t flags); +hpm_stat_t sdxc_set_adma_table_config(SDXC_Type *base, + sdxc_adma_config_t *dma_cfg, + sdxc_data_t *data_cfg, + uint32_t flags); /** * @brief Set ADMA2 descriptor @@ -949,8 +1097,11 @@ hpm_stat_t sdxc_set_adma_table_config(SDXC_Type *base, sdxc_adma_config_t *dma_c * @param [in] flags Flags for ADMA2 descriptor * @retval API execution status */ -hpm_stat_t sdxc_set_adma2_desc(uint32_t *adma_tbl, uint32_t adma_table_words, const uint32_t *data_buf, - uint32_t data_bytes, uint32_t flags); +hpm_stat_t sdxc_set_adma2_desc(uint32_t *adma_tbl, + uint32_t adma_table_words, + const uint32_t *data_buf, + uint32_t data_bytes, + uint32_t flags); /** * @brief Set DMA configuration @@ -960,7 +1111,9 @@ hpm_stat_t sdxc_set_adma2_desc(uint32_t *adma_tbl, uint32_t adma_table_words, co * @param [in] enable_auto_cmd23 Flag to determine whether to enable auto CMD23 or not * @retval API execution status */ -hpm_stat_t sdxc_set_dma_config(SDXC_Type *base, sdxc_adma_config_t *dma_cfg, const uint32_t *data_addr, +hpm_stat_t sdxc_set_dma_config(SDXC_Type *base, + sdxc_adma_config_t *dma_cfg, + const uint32_t *data_addr, bool enable_auto_cmd23); /** @@ -974,7 +1127,7 @@ void sdxc_init(SDXC_Type *base, const sdxc_config_t *config); * @brief Set the Data Timeout Counter value for an SD/eMMC device * @param [in] base SDXC base address * @param [in] timeout_in_ms Required timeout value in milliseconds, maximum value is 131,072ms - * @param [out] actual_timeout_us Actual timeout in milliseconds, reported by this API + * @param [out] actual_timeout_ms Actual timeout in milliseconds, reported by this API */ void sdxc_set_data_timeout(SDXC_Type *base, uint32_t timeout_in_ms, uint32_t *actual_timeout_ms); diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sei_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sei_drv.h new file mode 100644 index 00000000000..fe1fffd9361 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sei_drv.h @@ -0,0 +1,1008 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_SEI_DRV_H +#define HPM_SEI_DRV_H + +#include "hpm_common.h" +#include "hpm_sei_regs.h" +#include "hpm_soc_feature.h" + +/** + * @brief sei arming action + */ +typedef enum { + sei_arming_direct_exec = 0, + sei_arming_wait_trigger +} sei_arming_mode_t; + +/** + * @brief sei watchdog action + */ +typedef enum { + sei_wdg_exec_next_instr = 0, + sei_wdg_exec_exception_instr +} sei_wdg_action_t; + +/** + * @brief sei transfer mode + */ +typedef enum { + sei_synchronous_master_mode = 0, + sei_synchronous_slave_mode, + sei_asynchronous_mode +} sei_tranceiver_mode_t; + +/** + * @brief sei asynchronous mode parity + */ +typedef enum { + sei_asynchronous_parity_even = 0, + sei_asynchronous_parity_odd +} sei_asynchronous_parity_t; + +/** + * @brief sei ilde state + */ +typedef enum { + sei_idle_low_state = 0, + sei_idle_high_state, +} sei_idle_state_t; + +/** + * @brief sei data mode + */ +typedef enum { + sei_data_mode = 0, + sei_check_mode, + sei_crc_mode +} sei_data_mode_t; + +/** + * @brief sei data bit order + */ +typedef enum { + sei_bit_lsb_first = 0, + sei_bit_msb_first +} sei_data_bit_order_t; + +/** + * @brief sei data word order + */ +typedef enum { + sei_word_nonreverse = 0, + sei_word_reverse +} sei_data_word_order_t; + +/** + * @brief sei state transition condition + */ +typedef enum { + sei_state_tran_condition_high_match = 0, + sei_state_tran_condition_low_dismatch, + sei_state_tran_condition_rise_entry, + sei_state_tran_condition_fall_leave +} sei_state_tran_condition_t; + +/** + * @brief sei trig in type + */ +typedef enum { + sei_trig_in0 = 0, + sei_trig_in1, + sei_trig_in_period, + sei_trig_in_soft +} sei_trig_in_type_t; /**< trig input type */ + +/** + * @brief sei irq event + */ +typedef enum { + sei_irq_stall_event = SEI_CTRL_IRQ_INT_FLAG_STALL_MASK, + sei_irq_execpt_event = SEI_CTRL_IRQ_INT_FLAG_EXECPT_MASK, + sei_irq_wdog_event = SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK, + sei_irq_instr_ptr0_start_event = SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK, + sei_irq_instr_ptr1_start_event = SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK, + sei_irq_instr_value0_start_event = SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK, + sei_irq_instr_value1_start_event = SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK, + sei_irq_instr_ptr0_end_event = SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK, + sei_irq_instr_ptr1_end_event = SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK, + sei_irq_instr_value0_end_event = SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK, + sei_irq_instr_value1_end_event = SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK, + sei_irq_trx_err_event = SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK, + sei_irq_timeout_event = SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK, + sei_irq_latch0_event = SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK, + sei_irq_latch1_event = SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK, + sei_irq_latch2_event = SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK, + sei_irq_latch3_event = SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK, + sei_irq_sample_err_event = SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK, + sei_irq_trig0_event = SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK, + sei_irq_trig1_event = SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK, + sei_irq_trig2_event = SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK, + sei_irq_trig3_event = SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK, + sei_irq_trig0_err_event = SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK, + sei_irq_trig1_err_event = SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK, + sei_irq_trig2_err_event = SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK, + sei_irq_trig3_err_event = SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK, +} sei_irq_event_t; /**< irq event type */ + +/** + * @brief sei select command or data + */ +#define SEI_SELECT_CMD true /**< select cmd */ +#define SEI_SELECT_DATA false /**< select data */ + +/** + * @brief sei instruction operation command + */ +#define SEI_INSTR_OP_HALT 0u /**< op halt */ +#define SEI_INSTR_OP_JUMP 1u /**< op jump */ +#define SEI_INSTR_OP_SEND_WDG 2u /**< op send with watchdog */ +#define SEI_INSTR_OP_SEND 3u /**< op send */ +#define SEI_INSTR_OP_WAIT_WDG 4u /**< op wait with watchdog */ +#define SEI_INSTR_OP_WAIT 5u /**< op wait */ +#define SEI_INSTR_OP_RECV_WDG 6u /**< op recv with watchdog */ +#define SEI_INSTR_OP_RECV 7u /**< op recv */ + +/** + * @brief sei instruction synchronous master clock type + */ +#define SEI_INSTR_M_CK_LOW 0u /**< clock low */ +#define SEI_INSTR_M_CK_RISE_FALL 1u /**< clock rise fall */ +#define SEI_INSTR_M_CK_FALL_RISE 2u /**< clock fall rise */ +#define SEI_INSTR_M_CK_HIGH 3u /**< clock high */ + +/** + * @brief sei instruction synchronous slave clock type + */ +#define SEI_INSTR_S_CK_DEFAULT 0u /**< default */ +#define SEI_INSTR_S_CK_TRX_EXCH 1u /**< rx tx exchange */ +#define SEI_INSTR_S_CK_TIMEOUT_EN 2u /**< enable timeout */ +#define SEI_INSTR_S_CK_TRX_EXCH_TIMEOUT_EN 3u /**< rx tx exchange and enable timeout */ + +/** + * @brief sei instruction jump intructions index + */ +#define SEI_JUMP_INIT_INSTR_IDX 0x00u /**< jump init instr index */ +#define SEI_JUMP_WDG_INSTR_IDX 0x01u /**< jump watchdog instr index */ +#define SEI_JUMP_CMD_TABLE_INSTR_IDX0 0x10u /**< jump command table instr ptr0 */ +#define SEI_JUMP_CMD_TABLE_INSTR_IDX1 0x11u /**< jump command table instr ptr1 */ +#define SEI_JUMP_CMD_TABLE_INSTR_IDX2 0x12u /**< jump command table instr ptr2 */ +#define SEI_JUMP_CMD_TABLE_INSTR_IDX3 0x13u /**< jump command table instr ptr3 */ +#define SEI_JUMP_CMD_TABLE_INSTR_IDX4 0x14u /**< jump command table instr ptr4 */ +#define SEI_JUMP_CMD_TABLE_INSTR_IDX5 0x15u /**< jump command table instr ptr5 */ +#define SEI_JUMP_CMD_TABLE_INSTR_IDX6 0x16u /**< jump command table instr ptr6 */ +#define SEI_JUMP_CMD_TABLE_INSTR_IDX7 0x17u /**< jump command table instr ptr7 */ +#define SEI_JUMP_CMD_TABLE_INSTR_IDX8 0x18u /**< jump command table instr ptr8 */ +#define SEI_JUMP_CMD_TABLE_INSTR_IDX9 0x19u /**< jump command table instr ptr9 */ +#define SEI_JUMP_CMD_TABLE_INSTR_IDX10 0x1Au /**< jump command table instr ptr10 */ +#define SEI_JUMP_CMD_TABLE_INSTR_IDX11 0x1Bu /**< jump command table instr ptr11 */ +#define SEI_JUMP_CMD_TABLE_INSTR_IDX12 0x1Cu /**< jump command table instr ptr12 */ +#define SEI_JUMP_CMD_TABLE_INSTR_IDX13 0x1Du /**< jump command table instr ptr13 */ +#define SEI_JUMP_CMD_TABLE_INSTR_IDX14 0x1Eu /**< jump command table instr ptr14 */ +#define SEI_JUMP_CMD_TABLE_INSTR_IDX15 0x1Fu /**< jump command table instr ptr15 */ + +/** + * @brief sei engine config structure + */ +typedef struct { + sei_arming_mode_t arming_mode; + uint8_t data_cdm_idx; + uint8_t data_base_idx; + uint8_t init_instr_idx; + bool wdg_enable; + sei_wdg_action_t wdg_action; + uint8_t wdg_instr_idx; + uint16_t wdg_time; +} sei_engine_config_t; /**< engine config struct */ + +/** + * @brief sei tranceiver synchronous master mode config structure + */ +typedef struct { + bool data_idle_high_z; + sei_idle_state_t data_idle_state; + bool clock_idle_high_z; + sei_idle_state_t clock_idle_state; + uint32_t baudrate; +} sei_tranceiver_synchronous_master_config_t; /**< tranceiver synchronous master config struct */ + +/** + * @brief sei tranceiver synchronous master mode config structure + */ +typedef struct { + bool data_idle_high_z; + sei_idle_state_t data_idle_state; + bool clock_idle_high_z; + sei_idle_state_t clock_idle_state; + uint32_t max_baudrate; + uint16_t ck0_timeout_us; + uint16_t ck1_timeout_us; +} sei_tranceiver_synchronous_slave_config_t; /**< tranceiver synchronous slave config struct */ + +/** + * @brief sei tranceiver asynchronous mode config structure + */ +typedef struct { + uint8_t wait_len; + uint8_t data_len; + bool parity_enable; + sei_asynchronous_parity_t parity; + bool data_idle_high_z; + sei_idle_state_t data_idle_state; + uint32_t baudrate; +} sei_tranceiver_asynchronous_config_t; /**< tranceiver asynchronous config struct */ + +/** + * @brief sei tranceiver config structure + */ +typedef struct { + sei_tranceiver_mode_t mode; + bool tri_sample; + uint32_t src_clk_freq; + sei_tranceiver_synchronous_master_config_t synchronous_master_config; + sei_tranceiver_synchronous_slave_config_t synchronous_slave_config; + sei_tranceiver_asynchronous_config_t asynchronous_config; +} sei_tranceiver_config_t; /**< tranceiver config struct */ + +/** + * @brief sei trigger input config structure + */ +typedef struct { + bool trig_in0_enable; + uint8_t trig_in0_select; + bool trig_in1_enable; + uint8_t trig_in1_select; + bool trig_period_enable; + sei_arming_mode_t trig_period_arming_mode; + bool trig_period_sync_enable; + uint8_t trig_period_sync_select; + uint32_t trig_period_time; +} sei_trigger_input_config_t; /**< trigger input config struct */ + +/** + * @brief sei trigger output config structure + */ +typedef struct { + uint8_t src_latch_select; + bool trig_out_enable; + uint8_t trig_out_select; +} sei_trigger_output_config_t; /**< trigger output config struct */ + +/** + * @brief sei data format config structure + */ +typedef struct { + sei_data_mode_t mode; + bool signed_flag; + sei_data_bit_order_t bit_order; + sei_data_word_order_t word_order; + uint8_t word_len; + bool crc_invert; + bool crc_shift_mode; + uint8_t crc_len; + uint8_t last_bit; + uint8_t first_bit; + uint8_t max_bit; + uint8_t min_bit; + uint32_t gold_value; + uint32_t crc_init_value; + uint32_t crc_poly; +} sei_data_format_config_t; /**< cmd or data format config struct */ + +/** + * @brief sei command table config structure + */ +typedef struct { + uint32_t cmd_min_value; + uint32_t cmd_max_value; + uint32_t cmd_mask_value; + uint8_t instr_idx[16]; +} sei_command_table_config_t; /**< cmd table config struct */ + +/** + * @brief sei state transition config structure + */ +typedef struct { + bool disable_instr_ptr_check; + sei_state_tran_condition_t instr_ptr_cfg; + uint8_t instr_ptr_value; + bool disable_clk_check; + sei_state_tran_condition_t clk_cfg; + bool disable_txd_check; + sei_state_tran_condition_t txd_cfg; + bool disable_rxd_check; + sei_state_tran_condition_t rxd_cfg; + bool disable_timeout_check; + sei_state_tran_condition_t timeout_cfg; +} sei_state_transition_config_t; /**< state transition config struct */ + +/** + * @brief sei state transition latch config structure + */ +typedef struct { + bool enable; + uint8_t output_select; + uint16_t delay; +} sei_state_transition_latch_config_t; /**< state transition latch config struct */ + +/** + * @brief sei sample config structure + */ +typedef struct { + uint8_t acc_data_idx; + uint8_t spd_data_idx; + uint8_t rev_data_idx; + uint8_t pos_data_idx; + bool acc_data_use_rx; /**< true - use rx data, false - use override data */ + bool spd_data_use_rx; /**< true - use rx data, false - use override data */ + bool rev_data_use_rx; /**< true - use rx data, false - use override data */ + bool pos_data_use_rx; /**< true - use rx data, false - use override data */ + uint8_t latch_select; + bool sample_once; + uint16_t sample_window; + uint32_t data_register_select; +} sei_sample_config_t; /**< sample config struct */ + +/** + * @brief sei update config structure + */ +typedef struct { + uint8_t acc_data_idx; + uint8_t spd_data_idx; + uint8_t rev_data_idx; + uint8_t pos_data_idx; + bool acc_data_use_rx; /**< true - use rx data, false - use override data */ + bool spd_data_use_rx; /**< true - use rx data, false - use override data */ + bool rev_data_use_rx; /**< true - use rx data, false - use override data */ + bool pos_data_use_rx; /**< true - use rx data, false - use override data */ + bool time_use_override; /**< true - use override data, false - use timestamp data */ + bool update_on_err; + uint8_t latch_select; + uint32_t data_register_select; +} sei_update_config_t; /**< update config struct */ + + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Set the SEI engine enable or disable + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] enable enable or disable + * @arg true enable + * @arg false disable + */ +static inline void sei_set_engine_enable(SEI_Type *ptr, uint8_t idx, bool enable) +{ + if (enable) { + ptr->CTRL[idx].ENGINE.CTRL |= SEI_CTRL_ENGINE_CTRL_ENABLE_MASK; + } else { + ptr->CTRL[idx].ENGINE.CTRL &= ~SEI_CTRL_ENGINE_CTRL_ENABLE_MASK; + } +} + +/** + * @brief Rewind the SEI engine + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + */ +static inline void sei_set_engine_rewind(SEI_Type *ptr, uint8_t idx) +{ + ptr->CTRL[idx].ENGINE.CTRL |= SEI_CTRL_ENGINE_CTRL_REWIND_MASK; +} + +/** + * @brief Set the SEI trigger input trig in0 enable or disable + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] enable enable or disable + * @arg true enable + * @arg false disable + */ +static inline void sei_set_trig_input_in0_enable(SEI_Type *ptr, uint8_t idx, bool enable) +{ + if (enable) { + ptr->CTRL[idx].TRG.IN_CFG |= SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK; + } else { + ptr->CTRL[idx].TRG.IN_CFG &= ~SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK; + } +} + +/** + * @brief Set the SEI trigger input trig in1 enable or disable + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] enable enable or disable + * @arg true enable + * @arg false disable + */ +static inline void sei_set_trig_input_in1_enable(SEI_Type *ptr, uint8_t idx, bool enable) +{ + if (enable) { + ptr->CTRL[idx].TRG.IN_CFG |= SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK; + } else { + ptr->CTRL[idx].TRG.IN_CFG &= ~SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK; + } +} + +/** + * @brief Set the SEI trigger input period enable or disable + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] enable enable or disable + * @arg true enable + * @arg false disable + */ +static inline void sei_set_trig_input_period_enable(SEI_Type *ptr, uint8_t idx, bool enable) +{ + if (enable) { + ptr->CTRL[idx].TRG.IN_CFG |= SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK; + } else { + ptr->CTRL[idx].TRG.IN_CFG &= ~SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK; + } +} + +/** + * @brief Set the SEI trigger input soft enable or disable + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @arg true enable + * @arg false disable + */ +static inline void sei_set_trig_input_soft_enable(SEI_Type *ptr, uint8_t idx) +{ + ptr->CTRL[idx].TRG.SW |= SEI_CTRL_TRG_SW_SOFT_MASK; +} + +/** + * @brief Set the SEI trigger input command value + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] type trigger input type @ref sei_trig_in_type_t + * @param [in] data command data + */ +static inline void sei_set_trig_input_command_value(SEI_Type *ptr, uint8_t idx, sei_trig_in_type_t type, uint32_t data) +{ + ptr->CTRL[idx].TRG_TABLE.CMD[type] = data; +} + +/** + * @brief Get the SEI trigger input time + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] type trigger input type @ref sei_trig_in_type_t + * @retval trigger input time + */ +static inline uint32_t sei_get_trig_input_time(SEI_Type *ptr, uint8_t idx, sei_trig_in_type_t type) +{ + return ptr->CTRL[idx].TRG_TABLE.TIME[type]; +} + +/** + * @brief Get the SEI latch time + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] latch_idx + * @arg SEI_LATCH_0 + * @arg SEI_LATCH_1 + * @arg SEI_LATCH_2 + * @arg SEI_LATCH_3 + * @retval latch time + */ +static inline uint32_t sei_get_latch_time(SEI_Type *ptr, uint8_t idx, uint8_t latch_idx) +{ + return ptr->CTRL[idx].LATCH[latch_idx].TIME; +} + +/** + * @brief Set the SEI tranceiver rx point + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] point rx point value + */ +static inline void sei_set_xcvr_rx_point(SEI_Type *ptr, uint8_t idx, uint16_t point) +{ + uint32_t tmp; + + assert(point > 0); + tmp = ptr->CTRL[idx].XCVR.DATA_CFG; + tmp &= ~SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK; + tmp |= SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SET(point); + ptr->CTRL[idx].XCVR.DATA_CFG = tmp; +} + +/** + * @brief Set the SEI tranceiver tx point + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] point tx point value + */ +static inline void sei_set_xcvr_tx_point(SEI_Type *ptr, uint8_t idx, uint16_t point) +{ + uint32_t tmp; + + assert(point > 0); + tmp = ptr->CTRL[idx].XCVR.DATA_CFG; + tmp &= ~SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK; + tmp |= SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SET(point); + ptr->CTRL[idx].XCVR.DATA_CFG = tmp; +} + +/** + * @brief Set the SEI tranceiver ck0 point + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] point ck0 point value + */ +static inline void sei_set_xcvr_ck0_point(SEI_Type *ptr, uint8_t idx, uint16_t point) +{ + uint32_t tmp; + + assert(point > 0); + tmp = ptr->CTRL[idx].XCVR.CLK_CFG; + tmp &= ~SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK; + tmp |= SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SET(point); + ptr->CTRL[idx].XCVR.CLK_CFG = tmp; +} + +/** + * @brief Set the SEI tranceiver ck1 point + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] point ck1 point value + */ +static inline void sei_set_xcvr_ck1_point(SEI_Type *ptr, uint8_t idx, uint16_t point) +{ + uint32_t tmp; + + assert(point > 0); + tmp = ptr->CTRL[idx].XCVR.CLK_CFG; + tmp &= ~SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK; + tmp |= SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SET(point); + ptr->CTRL[idx].XCVR.CLK_CFG = tmp; +} + +/** + * @brief Get the SEI tranceiver ck0 point + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @retval ck0 point value + */ +static inline uint16_t sei_get_xcvr_ck0_point(SEI_Type *ptr, uint8_t idx) +{ + return SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_GET(ptr->CTRL[idx].XCVR.CLK_CFG); +} + +/** + * @brief Get the SEI tranceiver ck1 point + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @retval ck1 point value + */ +static inline uint16_t sei_get_xcvr_ck1_point(SEI_Type *ptr, uint8_t idx) +{ + return SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_GET(ptr->CTRL[idx].XCVR.CLK_CFG); +} + +/** + * @brief Set the SEI command value + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] cmd command value + */ +static inline void sei_set_command_value(SEI_Type *ptr, uint8_t idx, uint32_t cmd) +{ + ptr->CTRL[idx].CMD.CMD = cmd; +} + +/** + * @brief Get the SEI command value + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @retval command value + */ +static inline uint32_t sei_get_command_value(SEI_Type *ptr, uint8_t idx) +{ + return ptr->CTRL[idx].CMD.CMD; +} + +/** + * @brief Rewind the SEI command + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + */ +static inline void sei_set_command_rewind(SEI_Type *ptr, uint8_t idx) +{ + ptr->CTRL[idx].CMD.MODE |= SEI_CTRL_CMD_MODE_REWIND_MASK; +} + +/** + * @brief Set the SEI data value + * @param [in] ptr SEI base address + * @param [in] idx SEI data index, such as SEI_DAT_2, SEI_DAT_3, etc. + * @param [in] data data value + */ +static inline void sei_set_data_value(SEI_Type *ptr, uint8_t idx, uint32_t data) +{ + ptr->DAT[idx].DATA = data; +} + +/** + * @brief Get the SEI data value + * @param [in] ptr SEI base address + * @param [in] idx SEI data index, such as SEI_DAT_2, SEI_DAT_3, etc. + * @retval data value + */ +static inline uint32_t sei_get_data_value(SEI_Type *ptr, uint8_t idx) +{ + return ptr->DAT[idx].DATA; +} + +/** + * @brief Rewind the SEI data + * @param [in] ptr SEI base address + * @param [in] idx SEI data index, such as SEI_DAT_2, SEI_DAT_3, etc. + */ +static inline void sei_set_data_rewind(SEI_Type *ptr, uint8_t idx) +{ + ptr->DAT[idx].MODE |= SEI_DAT_MODE_REWIND_MASK; +} + +/** + * @brief Set the SEI sample position (singleturn) override value + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] data position (singleturn) override value + */ +static inline void sei_set_sample_pos_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data) +{ + ptr->CTRL[idx].POS.SMP_POS = data; +} + +/** + * @brief Set the SEI sample revolution (multiturn) override value + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] data revolution (multiturn) override value + */ +static inline void sei_set_sample_rev_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data) +{ + ptr->CTRL[idx].POS.SMP_REV = data; +} + +/** + * @brief Set the SEI sample speed override value + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] data speed override value + */ +static inline void sei_set_sample_spd_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data) +{ + ptr->CTRL[idx].POS.SMP_SPD = data; +} + +/** + * @brief Set the SEI sample acceleration override value + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] data acceleration override value + */ +static inline void sei_set_sample_acc_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data) +{ + ptr->CTRL[idx].POS.SMP_ACC = data; +} + +/** + * @brief Set the SEI update position (singleturn) override value + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] data position (singleturn) override value + */ +static inline void sei_set_update_pos_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data) +{ + ptr->CTRL[idx].POS.UPD_POS = data; +} + +/** + * @brief Set the SEI update revolution (multiturn) override value + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] data revolution (multiturn) override value + */ +static inline void sei_set_update_rev_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data) +{ + ptr->CTRL[idx].POS.UPD_REV = data; +} + +/** + * @brief Set the SEI update speed override value + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] data speed override value + */ +static inline void sei_set_update_spd_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data) +{ + ptr->CTRL[idx].POS.UPD_SPD = data; +} + +/** + * @brief Set the SEI update acceleration override value + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] data acceleration override value + */ +static inline void sei_set_update_acc_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data) +{ + ptr->CTRL[idx].POS.UPD_ACC = data; +} + +/** + * @brief Set the SEI update time override value + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] data time override value + */ +static inline void sei_set_update_time_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data) +{ + ptr->CTRL[idx].POS.UPD_TIME = data; +} + +/** + * @brief Set the SEI irq match pointer0 + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] instr_idx match instr0 index + */ +static inline void sei_set_irq_match_instr0_ptr(SEI_Type *ptr, uint8_t idx, uint8_t instr_idx) +{ + ptr->CTRL[idx].IRQ.POINTER0 = SEI_CTRL_IRQ_POINTER0_POINTER_SET(instr_idx); +} + +/** + * @brief Set the SEI irq match pointer1 + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] instr_idx match instr1 index + */ +static inline void sei_set_irq_match_instr1_ptr(SEI_Type *ptr, uint8_t idx, uint8_t instr_idx) +{ + ptr->CTRL[idx].IRQ.POINTER1 = SEI_CTRL_IRQ_POINTER1_POINTER_SET(instr_idx); +} + +/** + * @brief Set the SEI irq match instr0 + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] instr_value match instr0 value + */ +static inline void sei_set_irq_match_instr0_value(SEI_Type *ptr, uint8_t idx, uint32_t instr_value) +{ + ptr->CTRL[idx].IRQ.INSTR0 = SEI_CTRL_IRQ_INSTR0_INSTR_SET(instr_value); +} + +/** + * @brief Set the SEI irq match instr1 + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] instr_value match instr1 value + */ +static inline void sei_set_irq_match_instr1_value(SEI_Type *ptr, uint8_t idx, uint32_t instr_value) +{ + ptr->CTRL[idx].IRQ.INSTR1 = SEI_CTRL_IRQ_INSTR1_INSTR_SET(instr_value); +} + +/** + * @brief Set the SEI irq enable or disable + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] irq_mask irq mask, @ref sei_irq_event_t + * @param [in] enable enable or disable + * @arg true enable + * @arg false disable + */ +static inline void sei_set_irq_enable(SEI_Type *ptr, uint8_t idx, uint32_t irq_mask, bool enable) +{ + if (enable) { + ptr->CTRL[idx].IRQ.INT_EN |= irq_mask; + } else { + ptr->CTRL[idx].IRQ.INT_EN &= ~irq_mask; + } +} + +/** + * @brief Get the SEI irq status + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] irq_mask irq mask, @ref sei_irq_event_t + * + * @retval true-has irq req, false-no irq req. + */ +static inline bool sei_get_irq_status(SEI_Type *ptr, uint8_t idx, uint32_t irq_mask) +{ + return ((ptr->CTRL[idx].IRQ.INT_FLAG & irq_mask) == irq_mask) ? true : false; +} + +/** + * @brief Clear the SEI irq flag + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] irq_mask irq mask, @ref sei_irq_event_t + */ +static inline void sei_clear_irq_flag(SEI_Type *ptr, uint8_t idx, uint32_t irq_mask) +{ + ptr->CTRL[idx].IRQ.INT_FLAG = irq_mask; +} + +/** + * @brief Init SEI tranceiver configuration + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] config tranceiver configuration @ref sei_tranceiver_config_t + * @retval API execution status + */ +hpm_stat_t sei_tranceiver_config_init(SEI_Type *ptr, uint8_t idx, sei_tranceiver_config_t *config); + +/** + * @brief Init SEI command or data format configuration + * @param [in] ptr SEI base address + * @param [in] cmd_data_select + * @arg @ref SEI_SELECT_CMD select command + * @arg @ref SEI_SELECT_DATA select data + * @param [in] idx SEI ctrl index or data index, decided by cmd_data_select, such as SEI_CTRL_0, SEI_CTRL_1, SEI_DAT_2, SEI_DAT_3, etc. + * @param [in] config command or data format configuration @ref sei_data_format_config_t + * @retval API execution status + */ +hpm_stat_t sei_cmd_data_format_config_init(SEI_Type *ptr, bool cmd_data_select, uint8_t idx, sei_data_format_config_t *config); + +/** + * @brief Init SEI command table configuration + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] table_idx command table index, 0 - 7 + * @param [in] config command table configuration @ref sei_command_table_config_t + * @retval API execution status + */ +hpm_stat_t sei_cmd_table_config_init(SEI_Type *ptr, uint8_t idx, uint8_t table_idx, sei_command_table_config_t *config); + +/** + * @brief Init SEI state transition configuration + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] latch_idx latch index + * @arg SEI_LATCH_0 + * @arg SEI_LATCH_1 + * @arg SEI_LATCH_2 + * @arg SEI_LATCH_3 + * @param [in] state transition state + * @arg SEI_CTRL_LATCH_TRAN_0_1 + * @arg SEI_CTRL_LATCH_TRAN_1_2 + * @arg SEI_CTRL_LATCH_TRAN_2_3 + * @arg SEI_CTRL_LATCH_TRAN_3_0 + * @param [in] config state transition configuration @ref sei_state_transition_config_t + * @retval API execution status + */ +hpm_stat_t sei_state_transition_config_init(SEI_Type *ptr, uint8_t idx, uint8_t latch_idx, uint8_t state, sei_state_transition_config_t *config); + +/** + * @brief Init SEI state transition latch configuration + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] latch_idx latch index + * @arg SEI_LATCH_0 + * @arg SEI_LATCH_1 + * @arg SEI_LATCH_2 + * @arg SEI_LATCH_3 + * @param [in] config state transition latch configuration @ref sei_state_transition_latch_config_t + * @retval API execution status + */ +hpm_stat_t sei_state_transition_latch_config_init(SEI_Type *ptr, uint8_t idx, uint8_t latch_idx, sei_state_transition_latch_config_t *config); + +/** + * @brief Init SEI sample configuration + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] config sample configuration @ref sei_sample_config_t + * @retval API execution status + */ +hpm_stat_t sei_sample_config_init(SEI_Type *ptr, uint8_t idx, sei_sample_config_t *config); + +/** + * @brief Init SEI update configuration + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] config update configuration @ref sei_update_config_t + * @retval API execution status + */ +hpm_stat_t sei_update_config_init(SEI_Type *ptr, uint8_t idx, sei_update_config_t *config); + +/** + * @brief Init SEI trigger input configuration + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] config trigger input configuration @ref sei_trigger_input_config_t + * @retval API execution status + */ +hpm_stat_t sei_trigger_input_config_init(SEI_Type *ptr, uint8_t idx, sei_trigger_input_config_t *config); + +/** + * @brief Init SEI trigger output configuration + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] config trigger output configuration @ref sei_trigger_output_config_t + * @retval API execution status + */ +hpm_stat_t sei_trigger_output_config_init(SEI_Type *ptr, uint8_t idx, sei_trigger_output_config_t *config); + +/** + * @brief Init SEI engine configuration + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] config engine configuration @ref sei_engine_config_t + * @retval API execution status + */ +hpm_stat_t sei_engine_config_init(SEI_Type *ptr, uint8_t idx, sei_engine_config_t *config); + +/** + * @brief Set SEI Intsructions + * @param [in] ptr SEI base address + * @param [in] idx SEI instruction index. + * @param [in] op SEI instruction operation + * @arg @ref SEI_INSTR_OP_HALT + * @arg @ref SEI_INSTR_OP_JUMP + * @arg @ref SEI_INSTR_OP_SEND_WDG + * @arg @ref SEI_INSTR_OP_SEND + * @arg @ref SEI_INSTR_OP_WAIT_WDG + * @arg @ref SEI_INSTR_OP_WAIT + * @arg @ref SEI_INSTR_OP_RECV_WDG + * @arg @ref SEI_INSTR_OP_RECV + * @param [in] ck SEI instruction clock + * [1] synchronous master clock type + * @arg @ref SEI_INSTR_M_CK_LOW + * @arg @ref SEI_INSTR_M_CK_RISE_FALL + * @arg @ref SEI_INSTR_M_CK_FALL_RISE + * @arg @ref SEI_INSTR_M_CK_HIGH + * [2] synchronous slave clock type + * @arg @ref SEI_INSTR_S_CK_DEFAULT + * @arg @ref SEI_INSTR_S_CK_TRX_EXCH + * @arg @ref SEI_INSTR_S_CK_TIMEOUT_EN + * @arg @ref SEI_INSTR_S_CK_TRX_EXCH_TIMEOUT_EN + * @param [in] crc SEI instruction crc register, such as SEI_DAT_0, SEI_DAT_1, etc. + * @param [in] data SEI instruction data register, such as SEI_DAT_0, SEI_DAT_1, etc. + * @param [in] opr SEI instruction operand. + * [1] When OP is SEI_INSTR_OP_HALT, opr is the halt time in baudrate, 0 represents infinite time. + * [2] When OP is SEI_INSTR_OP_JUMP, opr is command table pointer, init pointer or wdg pointer. + * @arg @ref SEI_JUMP_INIT_INSTR_IDX + * @arg @ref SEI_JUMP_WDG_INSTR_IDX + * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX0 + * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX1 + * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX2 + * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX3 + * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX4 + * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX5 + * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX6 + * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX7 + * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX8 + * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX9 + * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX10 + * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX11 + * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX12 + * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX13 + * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX14 + * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX15 + * [3] Other OP, this area is the data length. + */ +void sei_set_instr(SEI_Type *ptr, uint8_t idx, uint8_t op, uint8_t ck, uint8_t crc, uint8_t data, uint8_t opr); + + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_smix_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_smix_drv.h new file mode 100644 index 00000000000..bf8255ccdd5 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_smix_drv.h @@ -0,0 +1,515 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_SMIX_DRV_H +#define HPM_SMIX_DRV_H + +#include "hpm_common.h" +#include "hpm_soc_feature.h" +#include "hpm_smix_regs.h" +#include + +/** + * @brief SMIX driver APIs + * @defgroup smix_interface SMIX driver APIs + * @ingroup smix_interfaces + * @{ + */ + +typedef enum { + smix_dma_transfer_burst_1t = 0U, + smix_dma_transfer_burst_2t = 1U, + smix_dma_transfer_burst_4t = 2U, + smix_dma_transfer_burst_8t = 3U, + smix_dma_transfer_burst_16t = 4U, + smix_dma_transfer_burst_32t = 5U, + smix_dma_transfer_burst_64t = 6U, + smix_dma_transfer_burst_128t = 7U, +} smix_dma_transfer_burst_t; + +typedef enum { + smix_dma_transfer_byte = 0U, + smix_dma_transfer_half_word = 1U, + smix_dma_transfer_word = 2U, +} smix_dma_transfer_width_t; + +typedef enum { + smix_dma_address_increment = 0U, + smix_dma_address_decrement = 1U, + smix_dma_address_fixed = 2U +} smix_dma_address_control_t; + +typedef enum { + smix_dma_mode_normal = 0, + smix_dma_mode_handshake = 1, +} smix_dma_handshake_mode_t; + +typedef enum { + smix_dma_req_i2s0_rx = 6, + smix_dma_req_i2s0_tx = 7, + smix_dma_req_i2s1_rx = 8, + smix_dma_req_i2s1_tx = 9, + smix_dma_req_i2s2_rx = 10, + smix_dma_req_i2s2_tx = 11, + smix_dma_req_i2s3_rx = 12, + smix_dma_req_i2s3_tx = 13, + + smix_dma_req_mixer_src_ch0 = 16, + smix_dma_req_mixer_src_ch1 = 17, + smix_dma_req_mixer_src_ch2 = 18, + smix_dma_req_mixer_src_ch3 = 19, + smix_dma_req_mixer_src_ch4 = 20, + smix_dma_req_mixer_src_ch5 = 21, + smix_dma_req_mixer_src_ch6 = 22, + smix_dma_req_mixer_src_ch7 = 23, + smix_dma_req_mixer_src_ch8 = 24, + smix_dma_req_mixer_src_ch9 = 25, + smix_dma_req_mixer_src_ch10 = 26, + smix_dma_req_mixer_src_ch11 = 27, + smix_dma_req_mixer_src_ch12 = 28, + smix_dma_req_mixer_src_ch13 = 29, + + smix_dma_req_mixer_dst_ch0 = 30, + smix_dma_req_mixer_dst_ch1 = 31, +} smix_dma_req_t; + + +typedef enum { + smix_src_clk_i2s0_bclk = 0, + smix_src_clk_i2s0_fclk = 1, + smix_src_clk_i2s0_mclk = 2, + smix_src_clk_i2s1_bclk = 3, + smix_src_clk_i2s1_fclk = 4, + smix_src_clk_i2s1_mclk = 5, + smix_src_clk_i2s2_bclk = 6, + smix_src_clk_i2s2_fclk = 7, + smix_src_clk_i2s2_mclk = 8, + smix_src_clk_i2s3_bclk = 9, + smix_src_clk_i2s3_fclk = 10, + smix_src_clk_i2s3_mclk = 11, + smix_src_clk_none = 15, +} smix_src_clk_source_t; + + +typedef struct { + uint32_t ctrl; /**< Control */ + uint32_t trans_size; /**< Transfer size in source width */ + uint32_t src_addr; /**< Source address */ + uint32_t reserved0; /**< reserved */ + uint32_t dst_addr; /**< Destination address */ + uint32_t reserved1; /**< reserved */ + uint32_t linked_ptr; /**< Linked descriptor address */ + uint32_t reserved2; /**< resetved */ +} smix_dma_linked_descriptor_t; + + +typedef struct { + uint8_t priority; /**< Channel priority */ + uint8_t src_burst_size; /**< Source burst size */ + uint8_t src_req_sel; + uint8_t dst_req_sel; + uint8_t src_mode; /**< Source work mode */ + uint8_t dst_mode; /**< Destination work mode */ + uint8_t src_width; /**< Source width */ + uint8_t dst_width; /**< Destination width */ + uint8_t src_addr_ctrl; /**< Source address control */ + uint8_t dst_addr_ctrl; /**< Destination address control */ + bool abort_int_en; /**< enable abort interrupt */ + bool error_int_en; /**< enable error interrupt */ + bool complete_int_en; /**< enable complete interrupt */ + uint32_t src_addr; /**< Source address */ + uint32_t dst_addr; /**< Destination address */ + uint32_t linked_ptr; /**< Next linked descriptor */ + uint32_t trans_bytes; /**< Total size to be transferred in byte */ +} smix_dma_ch_config_t; + + +typedef enum { + smix_mixer_gain_decrease_12db = 0x400, + smix_mixer_gain_decrease_6db = 0x800, + smix_mixer_gain_0db = 0xfff, + smix_mixer_gain_increase_6db = 0x1800, + smix_mixer_gain_increase_12db = 0x1fff, +} smix_mixer_gain_t; + +typedef enum { + smix_mixer_no_rate_convert, + smix_mixer_upper_2x_sample, + smix_mixer_upper_3x_sample, + smix_mixer_upper_4x_sample, + smix_mixer_upper_6x_sample, + smix_mixer_upper_8x_sample, + smix_mixer_upper_12x_sample, + smix_mixer_lower_2x_sample, +} smix_mixer_rate_convert_t; + +typedef struct { + bool underflow_int_en; + uint8_t fifo_thr; + bool calsat_int_en; + bool da_int_en; + bool auto_deactivate_en; + bool fadeout_done_int_en; + bool deactivate_en; + bool active_en; + bool fadeout_now_en; + bool fadeout_auto_en; + bool fadein_en; + bool channel_en; + bool mixer_en; + + uint16_t gain; + uint32_t length; + uint32_t fadein_delta; + uint32_t fadeout_delta; + uint8_t src_ch_mask; +} smix_mixer_dst_config_t; + + +typedef struct { + uint8_t fifo_thr; + bool calsat_int_en; + bool dn_int_en; + uint8_t fir_shift; + bool auto_deactivate_en; + bool fadeout_int_en; + uint8_t convert_rate; + + uint16_t gain; + uint32_t fadein_delta; + uint32_t fadeout_delta; + uint32_t length; +} smix_mixer_source_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief smix dma check transfer complete status + * + * @param [in] ptr SMIX base address + * @param [in] ch_index dma channel + * @retval true for transfer complete + */ +static inline bool smix_dma_check_transfer_complete(SMIX_Type *ptr, uint8_t ch_index) +{ + if ((SMIX_DMAC_TC_ST_CH_GET(ptr->DMAC_TC_ST) & (1U << ch_index)) != 0) { + ptr->DMAC_TC_ST = (1U << ch_index); /* W1C clear status*/ + return true; + } + return false; +} + +/** + * @brief smix dma check transfer abort status + * + * @param [in] ptr SMIX base address + * @param [in] ch_index dma channel + * @retval true for transfer abort + */ +static inline bool smix_dma_check_transfer_abort(SMIX_Type *ptr, uint8_t ch_index) +{ + if ((SMIX_DMAC_ABRT_ST_CH_GET(ptr->DMAC_ABRT_ST) & (1U << ch_index)) != 0) { + ptr->DMAC_ABRT_ST = (1U << ch_index); /* W1C clear status*/ + return true; + } + return false; +} + +/** + * @brief smix dma check transfer error status + * + * @param [in] ptr SMIX base address + * @param [in] ch_index dma channel + * @retval true for transfer error + */ +static inline bool smix_dma_check_transfer_error(SMIX_Type *ptr, uint8_t ch_index) +{ + if ((SMIX_DMAC_ERR_ST_CH_GET(ptr->DMAC_ERR_ST) & (1U << ch_index)) != 0) { + ptr->DMAC_ERR_ST = (1U << ch_index); /* W1C clear status*/ + return true; + } + return false; +} + +/** + * @brief smix mixer enable source channel for dst + * + * @param [in] ptr SMIX base address + * @param [in] dst_ch dst channel + * @param [in] source_ch_mask source channel mask + */ +static inline void smix_mixer_dst_enable_source_channel(SMIX_Type *ptr, uint8_t dst_ch, uint32_t source_ch_mask) +{ + ptr->DST_CH[dst_ch].SOURCE_EN |= source_ch_mask; +} + +/** + * @brief smix mixer disable source channel for dst + * + * @param [in] ptr SMIX base address + * @param [in] dst_ch dst channel + * @param [in] source_ch_mask source channel mask + */ +static inline void smix_mixer_dst_disable_source_channel(SMIX_Type *ptr, uint8_t dst_ch, uint32_t source_ch_mask) +{ + ptr->DST_CH[dst_ch].SOURCE_EN &= ~source_ch_mask; +} + +/** + * @brief smix mixer active source channel for dst + * + * @param [in] ptr SMIX base address + * @param [in] dst_ch dst channel + * @param [in] source_ch_mask source channel mask + */ +static inline void smix_mixer_dst_active_source_channel(SMIX_Type *ptr, uint8_t dst_ch, uint32_t source_ch_mask) +{ + ptr->DST_CH[dst_ch].SOURCE_ACT |= source_ch_mask; +} + +/** + * @brief smix mixer deactive source channel for dst + * + * @param [in] ptr SMIX base address + * @param [in] dst_ch dst channel + * @param [in] source_ch_mask source channel mask + */ +static inline void smix_mixer_dst_deactive_source_channel(SMIX_Type *ptr, uint8_t dst_ch, uint32_t source_ch_mask) +{ + ptr->DST_CH[dst_ch].SOURCE_DEACT |= source_ch_mask; +} + +/** + * @brief smix mixer fadein source channel for dst + * + * @param [in] ptr SMIX base address + * @param [in] dst_ch dst channel + * @param [in] source_ch_mask source channel mask + */ +static inline void smix_mixer_dst_fadein_source_channel(SMIX_Type *ptr, uint8_t dst_ch, uint32_t source_ch_mask) +{ + ptr->DST_CH[dst_ch].SOURCE_FADEIN_CTRL |= source_ch_mask; +} + +/** + * @brief smix mixer fadeout source channel for dst + * + * @param [in] ptr SMIX base address + * @param [in] dst_ch dst channel + * @param [in] source_ch_mask source channel mask + */ +static inline void smix_mixer_dst_fadeout_source_channel(SMIX_Type *ptr, uint8_t dst_ch, uint32_t source_ch_mask) +{ + ptr->DST_CH[dst_ch].SOURCE_MFADEOUT_CTRL |= source_ch_mask; +} + +/** + * @brief smix mixer enable dst channel + * + * @param [in] ptr SMIX base address + * + * @note two dst channel share same enable bit in DST_CH[0].CTRL.MIXER_EN, DST_CH[1].CTRL.MIXER_EN should not be set + */ +static inline void smix_mixer_dst_enable(SMIX_Type *ptr) +{ + ptr->DST_CH[0].CTRL |= SMIX_DST_CH_CTRL_DST_EN_MASK; + ptr->DST_CH[1].CTRL &= ~SMIX_DST_CH_CTRL_DST_EN_MASK; +} + +/** + * @brief smix mixer disable dst channel + * + * @param [in] ptr SMIX base address + * + * @note two dst channel share same enable bit in DST_CH[0].CTRL.MIXER_EN, DST_CH[1].CTRL.MIXER_EN should not be set + */ +static inline void smix_mixer_dst_disable(SMIX_Type *ptr) +{ + ptr->DST_CH[0].CTRL &= ~SMIX_DST_CH_CTRL_DST_EN_MASK; +} + +/** + * @brief smix mixer get calculate saturation register value + * + * @param [in] ptr SMIX base address + * @retval calculate saturation register value + */ +static inline uint32_t smix_mixer_get_calsat_status(SMIX_Type *ptr) +{ + return ptr->CALSAT_ST; +} + +/** + * @brief smix mixer check dst channel calculate saturation error + * + * @param [in] ptr SMIX base address + * @param [in] dst_ch dst channel + * @retval true for calculate saturation error occurred + */ +static inline bool smix_mixer_check_dst_cal_saturation_error(SMIX_Type *ptr, uint8_t dst_ch) +{ + return ((SMIX_CALSAT_ST_DST_GET(ptr->CALSAT_ST) & (1U << dst_ch)) != 0) ? true : false; +} + +/** + * @brief smix mixer check source channel calculate saturation error + * + * @param [in] ptr SMIX base address + * @param [in] source_ch source channel + * @retval true for calculate saturation error occurred + */ +static inline bool smix_mixer_check_source_cal_saturation_error(SMIX_Type *ptr, uint8_t source_ch) +{ + return ((SMIX_CALSAT_ST_SRC_GET(ptr->CALSAT_ST) & (1U << source_ch)) != 0) ? true : false; +} + +/** + * @brief smix mixer check dst channel data ubderflew + * + * @param [in] ptr SMIX base address + * @param [in] dst_ch dst channel + * @retval true for data underflew + */ +static inline bool smix_mixer_check_dst_data_underflew(SMIX_Type *ptr, uint8_t dst_ch) +{ + return ((SMIX_DATA_ST_DST_UNDL_GET(ptr->DATA_ST) & (1U << dst_ch)) != 0) ? true : false; +} + +/** + * @brief smix mixer check dst channel data available + * + * @param [in] ptr SMIX base address + * @param [in] dst_ch dst channel + * @retval true for data available + */ +static inline bool smix_mixer_check_dst_data_available(SMIX_Type *ptr, uint8_t dst_ch) +{ + return ((SMIX_DATA_ST_DST_DA_GET(ptr->DATA_ST) & (1U << dst_ch)) != 0) ? true : false; +} + +/** + * @brief smix mixer check source channel data available + * + * @param [in] ptr SMIX base address + * @param [in] source_ch source channel + * @retval true for source channel need new data + */ +static inline bool smix_mixer_check_source_data_needed(SMIX_Type *ptr, uint8_t source_ch) +{ + return ((SMIX_DATA_ST_SRC_DN_GET(ptr->DATA_ST) & (1U << source_ch)) != 0) ? true : false; +} + +/** + * @brief smix mixer config dst channel fadein delta + * + * @param [in] ptr SMIX base address + * @param [in] ch dst channel + * @param [in] target_sample_rate target sample rate + * @param [in] ms fadein consumed time in ms + * @retval status_success if no error occurs + */ +hpm_stat_t smix_mixer_config_dst_fadein_delta(SMIX_Type *ptr, uint8_t ch, uint32_t target_sample_rate, uint32_t ms); + +/** + * @brief smix mixer config dst channel fadeout delta + * + * @param [in] ptr SMIX base address + * @param [in] ch dst channel + * @param [in] target_sample_rate target sample rate + * @param [in] ms fadeout consumed time in ms + * @retval status_success if no error occurs + */ +hpm_stat_t smix_mixer_config_dst_fadeout_delta(SMIX_Type *ptr, uint8_t ch, uint32_t target_sample_rate, uint32_t ms); + +/** + * @brief smix mixer config source channel fadein delta + * + * @param [in] ptr SMIX base address + * @param [in] ch source channel + * @param [in] target_sample_rate target sample rate + * @param [in] ms fadein consumed time in ms + * @retval status_success if no error occurs + */ +hpm_stat_t smix_mixer_config_source_fadein_delta(SMIX_Type *ptr, uint8_t ch, uint32_t target_sample_rate, uint32_t ms); + +/** + * @brief smix mixer config source channel fadeout delta + * + * @param [in] ptr SMIX base address + * @param [in] ch source channel + * @param [in] target_sample_rate target sample rate + * @param [in] ms fadeout consumed time in ms + * @retval status_success if no error occurs + */ +hpm_stat_t smix_mixer_config_source_fadeout_delta(SMIX_Type *ptr, uint8_t ch, uint32_t target_sample_rate, uint32_t ms); + +/** + * @brief smix get dma channel default config + * + * @param [in] ptr SMIX base address + * @param [in] config smix_dma_ch_config_t + */ +void smix_get_dma_default_ch_config(SMIX_Type *ptr, smix_dma_ch_config_t *config); + +/** + * @brief smix get dst channel default config + * + * @param [in] ptr SMIX base address + * @param [in] config smix_mixer_dst_config_t + */ +void smix_get_mixer_dst_ch_default_config(SMIX_Type *ptr, smix_mixer_dst_config_t *config); + +/** + * @brief smix get source channel default config + * + * @param [in] ptr SMIX base address + * @param [in] config smix_mixer_source_config_t + */ +void smix_get_mixer_source_ch_default_config(SMIX_Type *ptr, smix_mixer_source_config_t *config); + +/** + * @brief smix config dma channel + * + * @param [in] ptr SMIX base address + * @param [in] ch dma channel + * @param [in] config smix_dma_ch_config_t + * @param [in] start true for start dma + * @retval status_success if no error occurs + */ +hpm_stat_t smix_config_dma_channel(SMIX_Type *ptr, uint8_t ch, smix_dma_ch_config_t *config, bool start); + +/** + * @brief smix mixer config source channel + * + * @param [in] ptr SMIX base address + * @param [in] ch source channel + * @param [in] src smix_mixer_source_config_t + * @retval status_success if no error occurs + */ +hpm_stat_t smix_mixer_config_source_ch(SMIX_Type *ptr, uint8_t ch, smix_mixer_source_config_t *src); + +/** + * @brief smix mixer config dst channel + * + * @param [in] ptr SMIX base address + * @param [in] ch dst channel + * @param [in] dst smix_mixer_dst_config_t + * @retval status_success if no error occurs + */ +hpm_stat_t smix_mixer_config_dst_ch(SMIX_Type *ptr, uint8_t ch, smix_mixer_dst_config_t *dst); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* HPM_SMIX_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_spi_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_spi_drv.h index 3c65a380bff..13709be60c2 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_spi_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_spi_drv.h @@ -216,7 +216,10 @@ typedef struct { uint8_t trans_mode; uint8_t data_phase_fmt; uint8_t dummy_cnt; -} spi_common_control_config_t; +#if defined(HPM_IP_FEATURE_SPI_CS_SELECT) && (HPM_IP_FEATURE_SPI_CS_SELECT == 1) + uint8_t cs_index; +#endif +} spi_common_control_config_t; /*!< value in spi_cs_index_t */ /** * @brief spi control config structure @@ -227,6 +230,33 @@ typedef struct { spi_common_control_config_t common_config; } spi_control_config_t; +#if defined(HPM_IP_FEATURE_SPI_CS_SELECT) && (HPM_IP_FEATURE_SPI_CS_SELECT == 1) +typedef enum { + spi_cs_0 = 1, + spi_cs_1 = 2, + spi_cs_2 = 4, + spi_cs_3 = 8, +} spi_cs_index_t; +#endif + +typedef enum { + addrlen_8bit = 0, + addrlen_16bit, + addrlen_24bit, + addrlen_32bit +} spi_address_len_t; + +#if defined(HPM_IP_FEATURE_SPI_SUPPORT_DIRECTIO) && (HPM_IP_FEATURE_SPI_SUPPORT_DIRECTIO == 1) +typedef enum { + hold_pin = 0, + wp_pin, + miso_pin, + mosi_pin, + sclk_pin, + cs_pin +} spi_directio_pin_t; +#endif + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ @@ -616,7 +646,11 @@ static inline void spi_disable_rx_dma(SPI_Type *ptr) */ static inline uint32_t spi_slave_get_sent_data_count(SPI_Type *ptr) { +#if defined(HPM_IP_FEATURE_SPI_NEW_TRANS_COUNT) && (HPM_IP_FEATURE_SPI_NEW_TRANS_COUNT == 1) + return ptr->SLVDATAWCNT; +#else return SPI_SLVDATACNT_WCNT_GET(ptr->SLVDATACNT); +#endif } /** @@ -627,7 +661,11 @@ static inline uint32_t spi_slave_get_sent_data_count(SPI_Type *ptr) */ static inline uint32_t spi_slave_get_received_data_count(SPI_Type *ptr) { +#if defined(HPM_IP_FEATURE_SPI_NEW_TRANS_COUNT) && (HPM_IP_FEATURE_SPI_NEW_TRANS_COUNT == 1) + return ptr->SLVDATARCNT; +#else return SPI_SLVDATACNT_RCNT_GET(ptr->SLVDATACNT); +#endif } /** @@ -677,7 +715,8 @@ static inline spi_sclk_idle_state_t spi_get_clock_polarity(SPI_Type *ptr) /** * @brief set spi the length of each data unit in bits * - * @param [in] nbit the actual bits number of a data + * @param [in] ptr SPI base address + * @param [in] nbits the actual bits number of a data * @retval hpm_stat_t status_success if spi transfer without any error */ static inline hpm_stat_t spi_set_data_bits(SPI_Type *ptr, uint8_t nbits) @@ -685,7 +724,7 @@ static inline hpm_stat_t spi_set_data_bits(SPI_Type *ptr, uint8_t nbits) if (nbits > 32) { return status_invalid_argument; } else { - ptr->TRANSFMT |= SPI_TRANSFMT_DATALEN_SET(nbits - 1); + ptr->TRANSFMT = (ptr->TRANSFMT & ~SPI_TRANSFMT_DATALEN_MASK) | SPI_TRANSFMT_DATALEN_SET(nbits - 1); return status_success; } } @@ -719,6 +758,135 @@ static inline void spi_reset(SPI_Type *ptr) { ptr->CTRL |= SPI_CTRL_SPIRST_MASK; } + +/** + * @brief set spi the length of address + * + * @param [in] ptr SPI base address + * @param [in] addrlen address lenth enum + */ +static inline void spi_set_address_len(SPI_Type *ptr, spi_address_len_t addrlen) +{ + ptr->TRANSFMT = (ptr->TRANSFMT & ~SPI_TRANSFMT_ADDRLEN_MASK) | SPI_TRANSFMT_ADDRLEN_SET(addrlen); +} + +/** + * @brief Enable SPI data merge + * + * @param [in] ptr SPI base address + */ +static inline void spi_enable_data_merge(SPI_Type *ptr) +{ + ptr->TRANSFMT |= SPI_TRANSFMT_DATAMERGE_MASK; +} + +/** + * @brief Disable SPI data merge + * + * @param [in] ptr SPI base address + */ +static inline void spi_disable_data_merge(SPI_Type *ptr) +{ + ptr->TRANSFMT &= ~SPI_TRANSFMT_DATAMERGE_MASK; +} + +#if defined(HPM_IP_FEATURE_SPI_SUPPORT_DIRECTIO) && (HPM_IP_FEATURE_SPI_SUPPORT_DIRECTIO == 1) +/** + * @brief enable specific pin output for spi directio + * + * @note must be used spi_enable_directio API before enable output function + * + * @param [in] ptr SPI base address + * @param [in] pin spi_directio_pin_t enum + */ +hpm_stat_t spi_directio_enable_output(SPI_Type *ptr, spi_directio_pin_t pin); + +/** + * @brief disable specific pin output for spi directio + * + * @param [in] ptr SPI base address + * @param [in] pin spi_directio_pin_t enum + */ +hpm_stat_t spi_directio_disable_output(SPI_Type *ptr, spi_directio_pin_t pin); + +/** + * @brief write specified pin level for spi directio + * + * @param [in] ptr SPI base address + * @param [in] pin spi_directio_pin_t enum + * @param [in] high Pin level set to high when it is set to true + */ +hpm_stat_t spi_directio_write(SPI_Type *ptr, spi_directio_pin_t pin, bool high); + +/** + * @brief Read specified pin level for spi directio + * + * @param [in] ptr SPI base address + * @param pin spi_directio_pin_t enum + * + * @return Pin status + */ +uint8_t spi_directio_read(SPI_Type *ptr, spi_directio_pin_t pin); + +/** + * @brief Enable SPI directIO control function + * + * @note if SPI transmission is required, the function must be disable + * + * @param [in] ptr SPI base address + */ +static inline void spi_enable_directio(SPI_Type *ptr) +{ + ptr->DIRECTIO |= SPI_DIRECTIO_DIRECTIOEN_MASK; +} + +/** + * @brief Disable SPI directIO control function + * + * @param [in] ptr SPI base address + */ +static inline void spi_disable_directio(SPI_Type *ptr) +{ + ptr->DIRECTIO &= ~SPI_DIRECTIO_DIRECTIOEN_MASK; +} + +/** + * @brief get whether spi directio function is enabled + * + * @param [in] ptr SPI base address + * + * @return if pi directio function is enable, it will return 1 + */ +static inline uint8_t spi_get_directio_enable_status(SPI_Type *ptr) +{ + return SPI_DIRECTIO_DIRECTIOEN_GET(ptr->DIRECTIO); +} + +#endif + +/** + * @brief Get valid data size in receive FIFO + * + * @param [in] ptr SPI base address + * + * @return rx fifo valid data size + */ +static inline uint8_t spi_get_rx_fifo_valid_data_size(SPI_Type *ptr) +{ + return ((SPI_STATUS_RXNUM_7_6_GET(ptr->STATUS) << 5) | SPI_STATUS_RXNUM_5_0_GET(ptr->STATUS)); +} + +/** + * @brief Get valid data size in transmit FIFO + * + * @param [in] ptr SPI base address + * + * @return tx fifo valid data size + */ +static inline uint8_t spi_get_tx_fifo_valid_data_size(SPI_Type *ptr) +{ + return ((SPI_STATUS_TXNUM_7_6_GET(ptr->STATUS) << 5) | SPI_STATUS_TXNUM_5_0_GET(ptr->STATUS)); +} /** * @} */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_synt_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_synt_drv.h index f8ef7506897..a2522ec70a8 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_synt_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_synt_drv.h @@ -46,6 +46,55 @@ static inline uint32_t synt_get_current_count(SYNT_Type *ptr) return (ptr->CNT & SYNT_CNT_CNT_MASK) >> SYNT_CNT_CNT_SHIFT; } +#if defined(SYNT_SOC_HAS_TIMESTAMP) && SYNT_SOC_HAS_TIMESTAMP + +static inline void synt_enable_timestamp(SYNT_Type *ptr, bool enable) +{ + ptr->GCR = (ptr->GCR & ~(SYNT_GCR_TIMESTAMP_ENABLE_MASK)) | SYNT_GCR_TIMESTAMP_ENABLE_SET(enable); +} + +static inline void synt_enable_timestamp_debug_stop(SYNT_Type *ptr, bool enable) +{ + ptr->GCR = (ptr->GCR & ~(SYNT_GCR_TIMESTAMP_DEBUG_EN_MASK)) | SYNT_GCR_TIMESTAMP_DEBUG_EN_SET(enable); +} + +static inline void synt_reset_timestamp(SYNT_Type *ptr) +{ + ptr->GCR |= SYNT_GCR_TIMESTAMP_RESET_MASK; +} + +static inline void synt_update_timestamp_new(SYNT_Type *ptr) +{ + ptr->GCR |= SYNT_GCR_TIMESTAMP_SET_NEW_MASK; +} + +static inline void synt_update_timestamp_dec(SYNT_Type *ptr) +{ + ptr->GCR |= SYNT_GCR_TIMESTAMP_DEC_NEW_MASK; +} + +static inline void synt_update_timestamp_inc(SYNT_Type *ptr) +{ + ptr->GCR |= SYNT_GCR_TIMESTAMP_INC_NEW_MASK; +} + +static inline void synt_set_timestamp_new_value(SYNT_Type *ptr, uint32_t new_value) +{ + ptr->TIMESTAMP_NEW = SYNT_TIMESTAMP_NEW_VALUE_SET(new_value); +} + +static inline uint32_t synt_get_timestamp_save_value(SYNT_Type *ptr) +{ + return SYNT_TIMESTAMP_SAV_VALUE_GET(ptr->TIMESTAMP_SAV); +} + +static inline uint32_t synt_get_timestamp_current_value(SYNT_Type *ptr) +{ + return SYNT_TIMESTAMP_CUR_VALUE_GET(ptr->TIMESTAMP_CUR); +} + +#endif + #ifdef __cplusplus } #endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_tamp_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_tamp_drv.h new file mode 100644 index 00000000000..2dbc0d441f2 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_tamp_drv.h @@ -0,0 +1,221 @@ +/* + * Copyright (c) 2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_TAMP_DRV_H +#define HPM_TAMP_DRV_H + +#include "hpm_common.h" +#include "hpm_tamp_regs.h" + +/** + * + * @brief TAMPER driver APIs + * @defgroup tamper_interface TAMPER driver APIs + * @ingroup io_interfaces + * @{ + */ + +typedef enum { + spd_1_time_per_sec = 0, + spd_2_times_per_sec, + spd_4_times_per_sec, + spd_8_times_per_sec, + spd_16_times_per_sec, + spd_32_times_per_sec, + spd_64_times_per_sec, + spd_128_times_per_sec, + spd_256_times_per_sec, + spd_512_times_per_sec, + spd_1024_times_per_sec, + spd_2048_times_per_sec, + spd_4096_times_per_sec, + spd_8192_times_per_sec, + spd_16384_times_per_sec, + spd_32768_times_per_sec, +} tamper_speed_t; + +typedef enum { + filter_len_1_cycle = 0, + filter_len_2_cycles, + filter_len_4_cycles, + filter_len_8_cycles, + filter_len_16_cycles, + filter_len_32_cycles, + filter_len_64_cycles, + filter_len_128_cycles, + filter_len_256_cycles, + filter_len_512_cycles, + filter_len_1024_cycles, + filter_len_2048_cycles, + filter_len_4096_cycles, + filter_len_8192_cycles, + filter_len_16384_cycles, + filter_len_32768_cycles, +} tamper_filter_len_t; + + typedef struct { + bool enable; + bool active_mode; + bool filter_bypass; + bool expect_high_level; + tamper_speed_t speed; + tamper_filter_len_t filter_len; + bool auto_recover; /* used in active mode */ + uint32_t poly; /* used in active mode */ + uint32_t lfsr; /* used in active mode */ +} tamper_ch_config_t; + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Init tamper channel config + * + * @param[in] ptr tamper base address + * @param[in] ch tamper channel + * @param[in] config tamper channel config struct pointer + * + */ +void tamp_init_ch_config(TAMP_Type *ptr, uint8_t ch, tamper_ch_config_t *config); + +/** + * @brief Get tamper default channel config + * + * @param[in] ptr tamper base address + * @param[in] config tamper default channel config struct pointer + * + */ +void tamp_get_default_ch_config(TAMP_Type *ptr, tamper_ch_config_t *config); + +/** + * @brief Set tamper channel enable or disable + * + * @param[in] ptr tamper base address + * @param[in] ch tamper channel + * @param[in] enable true - enable tamper, false - disable tamper + * + */ +static inline void tamp_set_ch_enable(TAMP_Type *ptr, uint8_t ch, bool enable) +{ + ch >>= 1u; + if (enable) { + ptr->TAMP[ch].CONTROL |= TAMP_TAMP_CONTROL_ENABLE_MASK; + } else { + ptr->TAMP[ch].CONTROL &= ~TAMP_TAMP_CONTROL_ENABLE_MASK; + } +} + +/** + * @brief Set tamper channel config lock or unlock + * + * @param[in] ptr tamper base address + * @param[in] ch tamper channel + * @param[in] lock true - config lock, false - config unlock + * + */ +static inline void tamp_set_ch_config_lock(TAMP_Type *ptr, uint8_t ch, bool lock) +{ + ch >>= 1u; + if (lock) { + ptr->TAMP[ch].CONTROL |= TAMP_TAMP_CONTROL_LOCK_MASK; + } else { + ptr->TAMP[ch].CONTROL &= ~TAMP_TAMP_CONTROL_LOCK_MASK; + } +} + +/** + * @brief Get tamper all channel flags + * + * @param[in] ptr tamper base address + * + * @return all channel flags + */ +static inline uint32_t tamp_get_flags(TAMP_Type *ptr) +{ + return TAMP_TAMP_FLAG_FLAG_GET(ptr->TAMP_FLAG); +} + +/** + * @brief Clear tamper flags + * + * @param[in] ptr tamper base address + * @param[in] flags clear channel flags + * + */ +static inline void tamp_clear_flags(TAMP_Type *ptr, uint32_t flags) +{ + ptr->TAMP_FLAG = TAMP_TAMP_FLAG_FLAG_SET(flags); +} + +/** + * @brief Check tamper channel flag + * + * @param[in] ptr TAMPER base address + * @param[in] ch tamper channel + * + * @return true - flag is set, false - falg is unset. + */ +static inline bool tamp_check_ch_flag(TAMP_Type *ptr, uint8_t ch) +{ + return ((TAMP_TAMP_FLAG_FLAG_GET(ptr->TAMP_FLAG) & (1u << ch)) != 0u) ? true : false; +} + +/** + * @brief Clear tamper channel flag + * + * @param[in] ptr TAMPER base address + * @param[in] ch tamper channel + * + */ +static inline void tamp_clear_ch_flag(TAMP_Type *ptr, uint8_t ch) +{ + ptr->TAMP_FLAG = TAMP_TAMP_FLAG_FLAG_SET(1u << ch); +} + +/** + * @brief Set tamper channel irq enable or disable + * + * @param[in] ptr TAMPER base address + * @param[in] ch tamper channel + * @param[in] enable true - irq enable, false - irq disable + * + */ +static inline void tamp_enable_ch_irq(TAMP_Type *ptr, uint8_t ch, bool enable) +{ + if (enable) { + ptr->IRQ_EN |= TAMP_IRQ_EN_IRQ_EN_SET(1u << ch); + } else { + ptr->IRQ_EN &= ~TAMP_IRQ_EN_IRQ_EN_SET(1u << ch); + } +} + +/** + * @brief Set tamper irq lock or unlock + * + * @param[in] ptr tamper base address + * @param[in] lock true - irq lock, false - irq unlock + * + */ +static inline void tamp_set_irq_lock(TAMP_Type *ptr, bool lock) +{ + if (lock) { + ptr->IRQ_EN |= TAMP_IRQ_EN_LOCK_MASK; + } else { + ptr->IRQ_EN &= ~TAMP_IRQ_EN_LOCK_MASK; + } +} + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_TAMP_DRV_H */ + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_trgm_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_trgm_drv.h index fd4392e2408..8561ccb4dd7 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_trgm_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_trgm_drv.h @@ -24,10 +24,10 @@ */ typedef enum trgm_filter_mode { trgm_filter_mode_bypass = 0, - trgm_filter_mode_rapid_change = 1, - trgm_filter_mode_delay = 2, - trgm_filter_mode_stable_low = 3, - trgm_filter_mode_stable_high = 4, + trgm_filter_mode_rapid_change = 4, + trgm_filter_mode_delay = 5, + trgm_filter_mode_stable_high = 6, + trgm_filter_mode_stable_low = 7, } trgm_filter_mode_t; /** @@ -47,7 +47,7 @@ typedef enum trgm_output_type { typedef struct trgm_input_filter { bool invert; /**< Invert output */ bool sync; /**< Sync with TRGM clock */ - uint16_t filter_length; /**< Filter length in TRGM clock cycle */ + uint32_t filter_length; /**< Filter length in TRGM clock cycle */ trgm_filter_mode_t mode; /**< Filter working mode */ } trgm_input_filter_t; @@ -91,12 +91,50 @@ static inline void trgm_disable_io_output(TRGM_Type *ptr, uint32_t mask) * * @param[in] ptr TRGM base address * @param[in] input Input selection - * @param[in] length Filter length in TRGM clock cycles (0 ~ 0xFFF) + * @param[in] length Filter length in TRGM clock cycles */ -static inline void trgm_input_filter_set_filter_length(TRGM_Type *ptr, uint8_t input, uint16_t length) +static inline void trgm_input_filter_set_filter_length(TRGM_Type *ptr, uint8_t input, uint32_t length) { - ptr->FILTCFG[input] = (ptr->FILTCFG[input] & TRGM_FILTCFG_FILTLEN_MASK) +#if defined(TRGM_SOC_HAS_FILTER_SHIFT) && TRGM_SOC_HAS_FILTER_SHIFT + uint32_t len = length; + uint8_t shift; + for (shift = 0; shift <= (TRGM_FILTCFG_FILTLEN_SHIFT_MASK >> TRGM_FILTCFG_FILTLEN_SHIFT_SHIFT); shift++) { + if (shift > 0) { + len >>= 1u; + } + if (len <= (TRGM_FILTCFG_FILTLEN_BASE_MASK >> TRGM_FILTCFG_FILTLEN_BASE_SHIFT)) { + break; + } + } + if (len > (TRGM_FILTCFG_FILTLEN_BASE_MASK >> TRGM_FILTCFG_FILTLEN_BASE_SHIFT)) { + len = (TRGM_FILTCFG_FILTLEN_BASE_MASK >> TRGM_FILTCFG_FILTLEN_BASE_SHIFT); + shift = (TRGM_FILTCFG_FILTLEN_SHIFT_MASK >> TRGM_FILTCFG_FILTLEN_SHIFT_SHIFT); + } + ptr->FILTCFG[input] = (ptr->FILTCFG[input] & ~(TRGM_FILTCFG_FILTLEN_BASE_MASK | TRGM_FILTCFG_FILTLEN_SHIFT_MASK)) + | TRGM_FILTCFG_FILTLEN_BASE_SET(len) | TRGM_FILTCFG_FILTLEN_SHIFT_SET(shift); +#else + ptr->FILTCFG[input] = (ptr->FILTCFG[input] & ~TRGM_FILTCFG_FILTLEN_MASK) | TRGM_FILTCFG_FILTLEN_SET(length); +#endif +} + +/** + * @brief Set filter length + * + * @param[in] ptr TRGM base address + * @param[in] input Input selection + * @param[in] shift Filter length shift + */ +static inline void trgm_input_filter_set_filter_shift(TRGM_Type *ptr, uint8_t input, uint8_t shift) +{ +#if defined(TRGM_SOC_HAS_FILTER_SHIFT) && TRGM_SOC_HAS_FILTER_SHIFT + ptr->FILTCFG[input] = (ptr->FILTCFG[input] & ~TRGM_FILTCFG_FILTLEN_SHIFT_MASK) + | TRGM_FILTCFG_FILTLEN_SHIFT_SET(shift); +#else + (void) ptr; + (void) input; + (void) shift; +#endif } /** @@ -130,7 +168,7 @@ static inline void trgm_input_filter_disable_sync(TRGM_Type *ptr, uint8_t input) */ static inline void trgm_input_filter_set_mode(TRGM_Type *ptr, uint8_t input, trgm_filter_mode_t mode) { - ptr->FILTCFG[input] = (ptr->FILTCFG[input] & TRGM_FILTCFG_MODE_MASK) + ptr->FILTCFG[input] = (ptr->FILTCFG[input] & ~TRGM_FILTCFG_MODE_MASK) | TRGM_FILTCFG_MODE_SET(mode); } @@ -143,7 +181,7 @@ static inline void trgm_input_filter_set_mode(TRGM_Type *ptr, uint8_t input, trg */ static inline void trgm_input_filter_invert(TRGM_Type *ptr, uint8_t input, bool invert) { - ptr->FILTCFG[input] = (ptr->FILTCFG[input] & TRGM_FILTCFG_OUTINV_MASK) + ptr->FILTCFG[input] = (ptr->FILTCFG[input] & ~TRGM_FILTCFG_OUTINV_MASK) | TRGM_FILTCFG_OUTINV_SET(invert); } @@ -158,8 +196,8 @@ static inline void trgm_input_filter_config(TRGM_Type *ptr, uint8_t input, trgm_ { ptr->FILTCFG[input] = TRGM_FILTCFG_OUTINV_SET(filter->invert) | TRGM_FILTCFG_MODE_SET(filter->mode) - | TRGM_FILTCFG_SYNCEN_SET(filter->sync) - | TRGM_FILTCFG_FILTLEN_SET(filter->filter_length); + | TRGM_FILTCFG_SYNCEN_SET(filter->sync); + trgm_input_filter_set_filter_length(ptr, input, filter->filter_length); } /** @@ -199,7 +237,11 @@ static inline void trgm_output_config(TRGM_Type *ptr, uint8_t output, trgm_outpu */ static inline void trgm_dma_request_config(TRGM_Type *ptr, uint8_t dma_out, uint8_t dma_src) { +#if defined(TRGM_SOC_HAS_DMAMUX_EN) && TRGM_SOC_HAS_DMAMUX_EN + ptr->DMACFG[dma_out] = TRGM_DMACFG_DMASRCSEL_SET(dma_src) | TRGM_DMACFG_DMAMUX_EN_MASK; +#else ptr->DMACFG[dma_out] = TRGM_DMACFG_DMASRCSEL_SET(dma_src); +#endif } #ifdef __cplusplus diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_uart_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_uart_drv.h index 63367abfb47..fe7ee944a71 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_uart_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_uart_drv.h @@ -52,20 +52,7 @@ typedef enum word_length { /* @brief UART fifo trigger levels */ typedef enum uart_fifo_trg_lvl { - uart_rx_fifo_trg_not_empty = 0, - uart_rx_fifo_trg_gt_one_quarter = 1, - uart_rx_fifo_trg_gt_half = 2, - uart_rx_fifo_trg_gt_three_quarters = 3, - - uart_tx_fifo_trg_not_full = 0, - uart_tx_fifo_trg_lt_three_quarters = 1, - uart_tx_fifo_trg_lt_half = 2, - uart_tx_fifo_trg_lt_one_quarter = 3, -} uart_fifo_trg_lvl_t; - -#if defined(UART_SOC_HAS_NEW_FIFO_THR) && (UART_SOC_HAS_NEW_FIFO_THR == 1) -/* @brief UART new fifo trigger levels */ -typedef enum uart_new_fifo_trg_lvl { +#if defined(HPM_IP_FEATURE_UART_FINE_FIFO_THRLD) && (HPM_IP_FEATURE_UART_FINE_FIFO_THRLD == 1) uart_fifo_1_byte = 0, uart_fifo_2_bytes = 1, uart_fifo_3_bytes = 2, @@ -82,8 +69,28 @@ typedef enum uart_new_fifo_trg_lvl { uart_fifo_14_bytes = 13, uart_fifo_15_bytes = 14, uart_fifo_16_bytes = 15, -} uart_new_fifo_trg_lvl_t; + + uart_rx_fifo_trg_not_empty = uart_fifo_1_byte, + uart_rx_fifo_trg_gt_one_quarter = uart_fifo_4_bytes, + uart_rx_fifo_trg_gt_half = uart_fifo_8_bytes, + uart_rx_fifo_trg_gt_three_quarters = uart_fifo_12_bytes, + + uart_tx_fifo_trg_not_full = uart_fifo_16_bytes, + uart_tx_fifo_trg_lt_three_quarters = uart_fifo_12_bytes, + uart_tx_fifo_trg_lt_half = uart_fifo_8_bytes, + uart_tx_fifo_trg_lt_one_quarter = uart_fifo_4_bytes, +#else + uart_rx_fifo_trg_not_empty = 0, + uart_rx_fifo_trg_gt_one_quarter = 1, + uart_rx_fifo_trg_gt_half = 2, + uart_rx_fifo_trg_gt_three_quarters = 3, + + uart_tx_fifo_trg_not_full = 0, + uart_tx_fifo_trg_lt_three_quarters = 1, + uart_tx_fifo_trg_lt_half = 2, + uart_tx_fifo_trg_lt_one_quarter = 3, #endif +} uart_fifo_trg_lvl_t; /* @brief UART signals */ typedef enum uart_signal { @@ -108,9 +115,17 @@ typedef enum uart_intr_enable { uart_intr_tx_slot_avail = UART_IER_ETHEI_MASK, uart_intr_rx_line_stat = UART_IER_ELSI_MASK, uart_intr_modem_stat = UART_IER_EMSI_MASK, -#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) +#if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1) uart_intr_rx_line_idle = UART_IER_ERXIDLE_MASK, #endif +#if defined(HPM_IP_FEATURE_UART_9BIT_MODE) && (HPM_IP_FEATURE_UART_9BIT_MODE == 1) + uart_intr_tx_line_idle = UART_IER_ETXIDLE_MASK, +#endif +#if defined(HPM_IP_FEATURE_UART_ADDR_MATCH) && (HPM_IP_FEATURE_UART_ADDR_MATCH == 1) + uart_intr_addr_match = UART_IER_EADDRM_MASK, + uart_intr_addr_match_and_rxidle = UART_IER_EADDRM_IDLE_MASK, + uart_intr_addr_datalost = UART_IER_EDATLOST_MASK, +#endif } uart_intr_enable_t; /* @brief UART interrupt IDs */ @@ -143,15 +158,18 @@ typedef struct uart_modem_config { bool set_rts_high; /**< Set signal RTS level high flag */ } uart_modem_config_t; -#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) +#if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1) /** - * @brief UART RX Line Idle detection conditions + * @brief UART Idle detection conditions， suitable for RX and TX */ typedef enum hpm_uart_rxline_idle_cond { uart_rxline_idle_cond_rxline_logic_one = 0, /**< Treat as idle if the RX Line high duration exceeds threshold */ uart_rxline_idle_cond_state_machine_idle = 1 /**< Treat as idle if the RX state machine idle state duration exceeds threshold */ } uart_rxline_idle_cond_t; +/** + * @brief UART Idle config， suitable for RX and TX + */ typedef struct hpm_uart_rxline_idle_detect_config { bool detect_enable; /**< RX Line Idle detection flag */ bool detect_irq_enable; /**< Enable RX Line Idle detection interrupt */ @@ -171,21 +189,21 @@ typedef struct hpm_uart_config { uint8_t parity; /**< Parity */ uint8_t tx_fifo_level; /**< TX Fifo level */ uint8_t rx_fifo_level; /**< RX Fifo level */ -#if defined(UART_SOC_HAS_NEW_FIFO_THR) && (UART_SOC_HAS_NEW_FIFO_THR == 1) - bool using_new_fifo_thr; -#endif bool dma_enable; /**< DMA Enable flag */ bool fifo_enable; /**< Fifo Enable flag */ uart_modem_config_t modem_config; /**< Modem config */ -#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) +#if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1) uart_rxline_idle_config_t rxidle_config; /**< RX Idle configuration */ #endif -#if defined(UART_SOC_HAS_RXEN_CFG) && (UART_SOC_HAS_RXEN_CFG == 1) +#if defined(HPM_IP_FEATURE_UART_9BIT_MODE) && (HPM_IP_FEATURE_UART_9BIT_MODE == 1) + uart_rxline_idle_config_t txidle_config; /**< TX Idle configuration */ +#endif +#if defined(HPM_IP_FEATURE_UART_RX_EN) && (HPM_IP_FEATURE_UART_RX_EN == 1) bool rx_enable; /**< RX Enable configuration */ #endif } uart_config_t; -#if defined(UART_SOC_HAS_NEW_FIFO_THR) && (UART_SOC_HAS_NEW_FIFO_THR == 1) +#if defined(HPM_IP_FEATURE_UART_TRIG_MODE) && (HPM_IP_FEATURE_UART_TRIG_MODE == 1) typedef struct { uint16_t stop_bit_len; bool en_stop_bit_insert; @@ -222,7 +240,7 @@ static inline uint8_t uart_get_fifo_size(UART_Type *ptr) /** * @brief uart config fifo control * - * @note fifo control register is WO access, prepare all bitfiled value to write + * @note fifo control register(FCR) is WO access, if support FCCR register, it is RW access. * * @param [in] ptr UART base address * @param [in] ctrl uart_fifo_ctrl_t @@ -247,37 +265,43 @@ static inline void uart_clear_rx_fifo(UART_Type *ptr) /** * @brief Reset TX Fifo * - * @note this API may modify other bit fields in FIFO control register - * * @param [in] ptr UART base address */ static inline void uart_reset_tx_fifo(UART_Type *ptr) { - ptr->FCR = UART_FCR_TFIFORST_MASK; +#if defined(HPM_IP_FEATURE_UART_FCRR) && (HPM_IP_FEATURE_UART_FCRR == 1) + ptr->FCRR |= UART_FCRR_TFIFORST_MASK; +#else + ptr->FCR = UART_FCR_TFIFORST_MASK | (ptr->GPR); +#endif } /** * @brief Reset RX Fifo * - * @note this API may modify other bit fields in FIFO control register - * * @param [in] ptr UART base address */ static inline void uart_reset_rx_fifo(UART_Type *ptr) { - ptr->FCR = UART_FCR_RFIFORST_MASK; +#if defined(HPM_IP_FEATURE_UART_FCRR) && (HPM_IP_FEATURE_UART_FCRR == 1) + ptr->FCRR |= UART_FCRR_RFIFORST_MASK; +#else + ptr->FCR = UART_FCR_RFIFORST_MASK | (ptr->GPR); +#endif } /** * @brief [in] Reset both TX and RX Fifo * - * @note this API may modify other bit fields in FIFO control register - * * @param [in] ptr UART base address */ static inline void uart_reset_all_fifo(UART_Type *ptr) { - ptr->FCR = UART_FCR_RFIFORST_MASK | UART_FCR_TFIFORST_MASK; +#if defined(HPM_IP_FEATURE_UART_FCRR) && (HPM_IP_FEATURE_UART_FCRR == 1) + ptr->FCRR |= UART_FCRR_TFIFORST_MASK | UART_FCRR_RFIFORST_MASK; +#else + ptr->FCR = UART_FCR_RFIFORST_MASK | UART_FCR_TFIFORST_MASK | (ptr->GPR); +#endif } /** @@ -425,7 +449,10 @@ static inline uint8_t uart_get_irq_id(UART_Type *ptr) return (ptr->IIR & UART_IIR_INTRID_MASK); } -#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) +#if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1) + +/* if HPM_IP_FEATURE_UART_E00018_FIX = 1, the IIR2 register exists, should use IIR2 to get/clear rx idle status */ +#if !defined(HPM_IP_FEATURE_UART_E00018_FIX) || (HPM_IP_FEATURE_UART_E00018_FIX == 0) /** * @brief Determine whether UART RX Line is idle * @param [in] ptr UART base address @@ -442,7 +469,9 @@ static inline bool uart_is_rxline_idle(UART_Type *ptr) static inline void uart_clear_rxline_idle_flag(UART_Type *ptr) { ptr->IIR = UART_IIR_RXIDLE_FLAG_MASK; /* Write-1-Clear Logic */ + ptr->FCR = ptr->GPR; } +#endif /** * @brief Enable UART RX Idle Line detection logic @@ -473,6 +502,76 @@ hpm_stat_t uart_init_rxline_idle_detection(UART_Type *ptr, uart_rxline_idle_conf #endif +#if defined(HPM_IP_FEATURE_UART_E00018_FIX) && (HPM_IP_FEATURE_UART_E00018_FIX == 1) +/** + * @brief Determine whether UART TX Line is idle + * @param [in] ptr UART base address + */ +static inline bool uart_is_txline_idle(UART_Type *ptr) +{ + return ((ptr->IIR2 & UART_IIR2_TXIDLE_FLAG_MASK) != 0U) ? true : false; +} + +/** + * @brief Clear UART TX Line Idle Flag + * @param [in] ptr UART base address + */ +static inline void uart_clear_txline_idle_flag(UART_Type *ptr) +{ + ptr->IIR2 = UART_IIR2_TXIDLE_FLAG_MASK; /* Write-1-Clear Logic */ +} + +/** + * @brief Determine whether UART RX Line is idle + * @param [in] ptr UART base address + */ +static inline bool uart_is_rxline_idle(UART_Type *ptr) +{ + return ((ptr->IIR2 & UART_IIR2_RXIDLE_FLAG_MASK) != 0U) ? true : false; +} + +/** + * @brief Clear UART RX Line Idle Flag + * @param [in] ptr UART base address + */ +static inline void uart_clear_rxline_idle_flag(UART_Type *ptr) +{ + ptr->IIR2 = UART_IIR2_RXIDLE_FLAG_MASK; /* Write-1-Clear Logic */ +} +#endif + +#if defined(HPM_IP_FEATURE_UART_9BIT_MODE) && (HPM_IP_FEATURE_UART_9BIT_MODE == 1) +/** + * @brief Enable UART TX Idle Line detection logic + * @param [in] ptr UART base address + */ +static inline void uart_enable_txline_idle_detection(UART_Type *ptr) +{ + ptr->IDLE_CFG |= UART_IDLE_CFG_TX_IDLE_EN_MASK; +} + +/** + * @brief Disable UART TX Idle Line detection logic + * + * @param [in] ptr UART base address + */ +static inline void uart_disable_txline_idle_detection(UART_Type *ptr) +{ + ptr->IDLE_CFG &= ~UART_IDLE_CFG_TX_IDLE_EN_MASK; +} + +/** + * @brief Configure UART TX Line detection + * @param [in] ptr UART base address + * @param [in] txidle_config TXLine IDLE detection configuration + * @retval status_success if no error occurs + */ +hpm_stat_t uart_init_txline_idle_detection(UART_Type *ptr, uart_rxline_idle_config_t txidle_config); + +#endif + + + /** * @brief Get status * @@ -487,6 +586,7 @@ static inline uint8_t uart_get_status(UART_Type *ptr) /** * @brief Check uart status according to the given status mask * + * @note maybe clear other bits, such as PE/OE/LBREAK/ERRF bit. use uart_get_status API if you need to get these bits * @param [in] ptr UART base address * @param mask Status mask value to be checked against * @retval true if any bit in given mask is set @@ -586,26 +686,25 @@ hpm_stat_t uart_send_data(UART_Type *ptr, uint8_t *buf, uint32_t size_in_byte); hpm_stat_t uart_set_baudrate(UART_Type *ptr, uint32_t baudrate, uint32_t src_clock_hz); -#if defined(UART_SOC_HAS_NEW_FIFO_THR) && (UART_SOC_HAS_NEW_FIFO_THR == 1) +#if defined(HPM_IP_FEATURE_UART_TRIG_MODE) && (HPM_IP_FEATURE_UART_TRIG_MODE == 1) /** - * @brief Config uart trigger mode for communication + * @brief uart configure transfer trigger mode * - * This function is used to tomagawa communication, uart sent out data in fifo then generate interrupt after - * received specify count of data into fifo. + * This function can configure uart to send data in fifo after being triggered * * @param ptr UART base address - * @param uart_trig_config_t config + * @param config uart_trig_config_t config */ -void uart_config_trig_mode(UART_Type *ptr, uart_trig_config_t *config); +void uart_config_transfer_trig_mode(UART_Type *ptr, uart_trig_config_t *config); /** - * @brief uart trigger communication + * @brief uart software trigger transmit * - * This function triggers uart communication, the communication configed by uart_config_trig_mode() + * This function immediately triggers the transfer, the transfer configed by uart_config_transfer_trig_mode() * * @param ptr UART base address */ -static inline void uart_trigger_communication(UART_Type *ptr) +static inline void uart_software_trig_transfer(UART_Type *ptr) { ptr->MOTO_CFG &= ~UART_MOTO_CFG_HWTRG_EN_MASK; ptr->MOTO_CFG |= UART_MOTO_CFG_SWTRG_MASK; @@ -614,12 +713,12 @@ static inline void uart_trigger_communication(UART_Type *ptr) /** * @brief uart enable hardware trigger mode * - * This function configures uart start communication by hardware trigger from motor periphrals + * This function enable hardware trigger the transfer, the transfer start when hardware event occured * * @param ptr UART base address - * @param bool enable + * @param enable true for enable, false for disable */ -static inline void uart_enable_hardware_trigger_mode(UART_Type *ptr, bool enable) +static inline void uart_enable_hardware_trig_transfer(UART_Type *ptr, bool enable) { if (enable) { ptr->MOTO_CFG |= UART_MOTO_CFG_HWTRG_EN_MASK; @@ -627,6 +726,104 @@ static inline void uart_enable_hardware_trigger_mode(UART_Type *ptr, bool enable ptr->MOTO_CFG &= ~UART_MOTO_CFG_HWTRG_EN_MASK; } } + +/** + * @brief UART get data count in rx fifo + * + * @param ptr UART base address + * @retval data count + */ +static inline uint8_t uart_get_data_count_in_rx_fifo(UART_Type *ptr) +{ + return UART_LSR_RFIFO_NUM_GET(ptr->LSR); +} + +/** + * @brief UART get data count in tx fifo + * + * @param ptr UART base address + * @retval data count + */ +static inline uint8_t uart_get_data_count_in_tx_fifo(UART_Type *ptr) +{ + return UART_LSR_TFIFO_NUM_GET(ptr->LSR); +} +#endif + +#if defined(HPM_IP_FEATURE_UART_ADDR_MATCH) && (HPM_IP_FEATURE_UART_ADDR_MATCH == 1) +/** + * @brief uart enable 9bit transmit mode + * + * @param ptr UART base address + * @param enable true for enable, false for disable + */ +static inline void uart_enable_9bit_transmit_mode(UART_Type *ptr, bool enable) +{ + if (enable) { + ptr->ADDR_CFG |= UART_ADDR_CFG_TXEN_9BIT_MASK + | UART_ADDR_CFG_RXEN_ADDR_MSB_MASK + | UART_ADDR_CFG_RXEN_9BIT_MASK; + } else { + ptr->ADDR_CFG &= ~(UART_ADDR_CFG_TXEN_9BIT_MASK + | UART_ADDR_CFG_RXEN_ADDR_MSB_MASK + | UART_ADDR_CFG_RXEN_9BIT_MASK); + } +} + +/** + * @brief uart enable address0 match + * + * @param ptr UART base address + * @param addr address value + */ +static inline void uart_enable_address0_match(UART_Type *ptr, uint8_t addr) +{ + ptr->ADDR_CFG &= ~UART_ADDR_CFG_ADDR0_MASK; + ptr->ADDR_CFG |= UART_ADDR_CFG_A0_EN_MASK | UART_ADDR_CFG_ADDR0_SET(addr); +} + +/** + * @brief uart enable address1 match + * + * @param ptr UART base address + * @param addr address value + */ +static inline void uart_enable_address1_match(UART_Type *ptr, uint8_t addr) +{ + ptr->ADDR_CFG &= ~UART_ADDR_CFG_ADDR1_MASK; + ptr->ADDR_CFG |= UART_ADDR_CFG_A1_EN_MASK | UART_ADDR_CFG_ADDR1_SET(addr); +} + +/** + * @brief uart disable address0 match + * + * @param ptr UART base address + */ +static inline void uart_disable_address0_match(UART_Type *ptr) +{ + ptr->ADDR_CFG &= ~UART_ADDR_CFG_A0_EN_MASK; +} + +/** + * @brief uart disable address1 match + * + * @param ptr UART base address + */ +static inline void uart_disable_address1_match(UART_Type *ptr) +{ + ptr->ADDR_CFG &= ~UART_ADDR_CFG_A1_EN_MASK; +} + +/** + * @brief uart disable address match(address0 and address1) + * + * @param ptr UART base address + */ +static inline void uart_disable_address_match(UART_Type *ptr) +{ + ptr->ADDR_CFG &= ~(UART_ADDR_CFG_A0_EN_MASK | UART_ADDR_CFG_A1_EN_MASK); +} + #endif #ifdef __cplusplus diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_usb_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_usb_drv.h index 7cf3ec41435..71692eb4d04 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_usb_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_usb_drv.h @@ -210,11 +210,6 @@ static inline uint8_t usb_get_port_speed(USB_Type *ptr) return USB_PORTSC1_PSPD_GET(ptr->PORTSC1); } -/*--------------------------------------------------------------------- - * Device API - *--------------------------------------------------------------------- - */ - /** * @brief Initialize USB phy * @@ -222,6 +217,63 @@ static inline uint8_t usb_get_port_speed(USB_Type *ptr) */ void usb_phy_init(USB_Type *ptr); +/** + * @brief USB phy get line status + * + * @param[in] ptr A USB peripheral base address + */ +static inline uint8_t usb_phy_get_line_state(USB_Type *ptr) +{ + return USB_PHY_STATUS_LINE_STATE_GET(ptr->PHY_STATUS); +} + +/** + * @brief USB phy using internal vbus + * + * @param[in] ptr A USB peripheral base address + */ +static inline void usb_phy_using_internal_vbus(USB_Type *ptr) +{ + ptr->PHY_CTRL0 |= (USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_MASK | USB_PHY_CTRL0_SESS_VALID_OVERRIDE_MASK) + | (USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_MASK | USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_MASK); +} + +/** + * @brief USB phy using external vbus + * + * @param[in] ptr A USB peripheral base address + */ +static inline void usb_phy_using_external_vbus(USB_Type *ptr) +{ + ptr->PHY_CTRL0 &= ~((USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_MASK | USB_PHY_CTRL0_SESS_VALID_OVERRIDE_MASK) + | (USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_MASK | USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_MASK)); +} + +/** + * @brief USB phy disconnect dp/dm pins pulldown resistance + * + * @param[in] ptr A USB peripheral base address + */ +static inline void usb_phy_disable_dp_dm_pulldown(USB_Type *ptr) +{ + ptr->PHY_CTRL0 |= 0x001000E0u; +} + +/** + * @brief USB phy connect dp/dm pins pulldown resistance + * + * @param[in] ptr A USB peripheral base address + */ +static inline void usb_phy_enable_dp_dm_pulldown(USB_Type *ptr) +{ + ptr->PHY_CTRL0 &= ~0x001000E0u; +} + +/*--------------------------------------------------------------------- + * Device API + *--------------------------------------------------------------------- + */ + /** * @brief USB device bus reset * @@ -291,6 +343,15 @@ void usb_dcd_edpt_stall(USB_Type *ptr, uint8_t ep_addr); */ void usb_dcd_edpt_clear_stall(USB_Type *ptr, uint8_t ep_addr); +/** + * @brief Clear stall + * + * @param[in] ptr A USB peripheral base address + * @param[in] ep_addr An address of the specified endpoint + * @retval The status of endpoint stall, true is stall, false is not stall + */ +bool usb_dcd_edpt_check_stall(USB_Type *ptr, uint8_t ep_addr); + /** * @brief Close a specified endpoint * @@ -443,6 +504,21 @@ static inline bool usb_hcd_get_port_csc(USB_Type *ptr) return USB_PORTSC1_CSC_GET(ptr->PORTSC1); } +/** + * @brief Set power ctrl polarity + * + * @param[in] ptr A USB peripheral base address + * @param[in] high true - vbus high level enable, false - vbus low level enable + */ +static inline void usb_hcd_set_power_ctrl_polarity(USB_Type *ptr, bool high) +{ + if (high) { + ptr->OTG_CTRL0 |= USB_OTG_CTRL0_OTG_POWER_MASK_MASK; + } else { + ptr->OTG_CTRL0 &= ~USB_OTG_CTRL0_OTG_POWER_MASK_MASK; + } +} + /** * @brief Enable port power * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_acmp_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_acmp_drv.c index 10f57d1f54e..60ab4693ee3 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_acmp_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_acmp_drv.c @@ -31,6 +31,7 @@ hpm_stat_t acmp_channel_config(ACMP_Type *ptr, uint8_t ch, acmp_channel_config_t void acmp_channel_get_default_config(ACMP_Type *ptr, acmp_channel_config_t *config) { + (void) ptr; config->plus_input = ACMP_INPUT_DAC_OUT; config->minus_input = ACMP_INPUT_DAC_OUT; config->filter_mode = ACMP_FILTER_MODE_BYPASS; diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc12_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc12_drv.c index 844b559a8d3..c433e01d2c3 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc12_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc12_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -24,8 +24,9 @@ void adc12_get_channel_default_config(adc12_channel_config_t *config) config->diff_sel = adc12_sample_signal_single_ended; config->sample_cycle = 10; config->sample_cycle_shift = 0; - config->thshdh = 0; - config->thshdl = 0; + config->thshdh = 0xfff; + config->thshdl = 0x000; + config->wdog_int_en = false; } static hpm_stat_t adc12_do_calibration(ADC12_Type *ptr, adc12_sample_signal_t diff_sel) @@ -38,10 +39,11 @@ static hpm_stat_t adc12_do_calibration(ADC12_Type *ptr, adc12_sample_signal_t di } /*Set diff_sel temporarily */ - ptr->SAMPLE_CFG[0] = ADC12_SAMPLE_CFG_DIFF_SEL_SET(diff_sel); + ptr->SAMPLE_CFG[0] &= ~ADC12_SAMPLE_CFG_DIFF_SEL_MASK; + ptr->SAMPLE_CFG[0] |= ADC12_SAMPLE_CFG_DIFF_SEL_SET(diff_sel); /* Set resetcal and resetadc */ - ptr->ANA_CTRL0 |= ADC12_ANA_CTRL0_RESETCAL_MASK; + ptr->ANA_CTRL0 |= ADC12_ANA_CTRL0_RESETCAL_MASK | ADC12_ANA_CTRL0_RESETADC_MASK; /* Clear resetcal and resetadc */ ptr->ANA_CTRL0 &= ~(ADC12_ANA_CTRL0_RESETCAL_MASK | ADC12_ANA_CTRL0_RESETADC_MASK); @@ -80,6 +82,14 @@ static hpm_stat_t adc12_do_calibration(ADC12_Type *ptr, adc12_sample_signal_t di return status_success; } +hpm_stat_t adc12_deinit(ADC12_Type *ptr) +{ + /* disable all interrupts */ + ptr->INT_EN = 0; + + return status_success; +} + hpm_stat_t adc12_init(ADC12_Type *ptr, adc12_config_t *config) { uint32_t adc_clk_div; @@ -115,10 +125,7 @@ hpm_stat_t adc12_init(ADC12_Type *ptr, adc12_config_t *config) | ADC12_ADC_CFG0_ADC_AHB_EN_SET(config->adc_ahb_en); /* Set wait_dis */ - if (config->conv_mode == adc12_conv_mode_oneshot) { - /* Set wait_dis */ - ptr->BUF_CFG0 = ADC12_BUF_CFG0_WAIT_DIS_SET(config->wait_dis); - } + ptr->BUF_CFG0 = ADC12_BUF_CFG0_WAIT_DIS_SET(config->wait_dis); /*------------------------------------------------------------------------------- * Calibration @@ -166,6 +173,11 @@ hpm_stat_t adc12_init_channel(ADC12_Type *ptr, adc12_channel_config_t *config) return status_invalid_argument; } + /* Check sample cycle */ + if (ADC12_IS_CHANNEL_SAMPLE_CYCLE_INVALID(config->sample_cycle)) { + return status_invalid_argument; + } + /* Set warning threshold */ ptr->PRD_CFG[config->ch].PRD_THSHD_CFG = ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_SET(config->thshdh) | ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_SET(config->thshdl); @@ -177,6 +189,25 @@ hpm_stat_t adc12_init_channel(ADC12_Type *ptr, adc12_channel_config_t *config) | ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SET(config->sample_cycle_shift) | ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SET(config->sample_cycle); + /* Enable watchdog interrupt */ + if (config->wdog_int_en) { + ptr->INT_EN |= 1 << config->ch; + } + + return status_success; +} + +hpm_stat_t adc12_get_channel_threshold(ADC12_Type *ptr, uint8_t ch, adc12_channel_threshold_t *config) +{ + /* Check the specified channel number */ + if (ADC12_IS_CHANNEL_INVALID(ch)) { + return status_invalid_argument; + } + + config->ch = ch; + config->thshdh = ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_GET(ptr->PRD_CFG[ch].PRD_THSHD_CFG); + config->thshdl = ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_GET(ptr->PRD_CFG[ch].PRD_THSHD_CFG); + return status_success; } @@ -229,10 +260,9 @@ hpm_stat_t adc12_set_prd_config(ADC12_Type *ptr, adc12_prd_config_t *config) ptr->PRD_CFG[config->ch].PRD_CFG = (ptr->PRD_CFG[config->ch].PRD_CFG & ~ADC12_PRD_CFG_PRD_CFG_PRESCALE_MASK) | ADC12_PRD_CFG_PRD_CFG_PRESCALE_SET(config->prescale); - /* Set period count */ ptr->PRD_CFG[config->ch].PRD_CFG = (ptr->PRD_CFG[config->ch].PRD_CFG & ~ADC12_PRD_CFG_PRD_CFG_PRD_MASK) - | ADC12_PRD_CFG_PRD_CFG_PRD_SET(config->period_count); + | ADC12_PRD_CFG_PRD_CFG_PRD_SET(config->period_count); return status_success; } diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc16_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc16_drv.c index 19f35d7dc6a..b4795c98b0d 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc16_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc16_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -10,12 +10,13 @@ void adc16_get_default_config(adc16_config_t *config) { + config->res = adc16_res_16_bits; config->conv_mode = adc16_conv_mode_oneshot; config->adc_clk_div = adc16_clock_divider_1; config->conv_duration = 0; config->wait_dis = true; config->sel_sync_ahb = true; - config->port3_rela_time = false; + config->port3_realtime = false; config->adc_ahb_en = false; } @@ -24,13 +25,14 @@ void adc16_get_channel_default_config(adc16_channel_config_t *config) config->ch = 0; config->sample_cycle = 10; config->sample_cycle_shift = 0; - config->thshdh = 0; - config->thshdl = 0; + config->thshdh = 0xffff; + config->thshdl = 0x0000; + config->wdog_int_en = false; } static hpm_stat_t adc16_do_calibration(ADC16_Type *ptr) { - int i, j; + uint32_t i, j; uint32_t clk_div_temp; uint32_t adc16_params[ADC16_SOC_PARAMS_LEN]; int32_t param01; @@ -58,7 +60,7 @@ static hpm_stat_t adc16_do_calibration(ADC16_Type *ptr) ptr->ADC16_CONFIG0 |= ADC16_ADC16_CONFIG0_REG_EN_MASK | ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK; - /* Set cal_avg_cfg for 5 loops */ + /* Set cal_avg_cfg for 32 loops */ ptr->ADC16_CONFIG0 = (ptr->ADC16_CONFIG0 & ~ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK) | ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SET(5); @@ -142,6 +144,14 @@ static hpm_stat_t adc16_do_calibration(ADC16_Type *ptr) return status_success; } +hpm_stat_t adc16_deinit(ADC16_Type *ptr) +{ + /* disable all interrupts */ + ptr->INT_EN = 0; + + return status_success; +} + hpm_stat_t adc16_init(ADC16_Type *ptr, adc16_config_t *config) { uint32_t clk_div_temp; @@ -159,13 +169,11 @@ hpm_stat_t adc16_init(ADC16_Type *ptr, adc16_config_t *config) /* Set the duration of the conversion */ ptr->ADC_CFG0 = ADC16_ADC_CFG0_SEL_SYNC_AHB_SET(config->sel_sync_ahb) | ADC16_ADC_CFG0_ADC_AHB_EN_SET(config->adc_ahb_en) - | ADC16_ADC_CFG0_CONVERT_DURATION_SET(config->conv_duration); + | ADC16_ADC_CFG0_CONVERT_DURATION_SET(config->conv_duration) + | ADC16_ADC_CFG0_PORT3_REALTIME_SET(config->port3_realtime); /* Set wait_dis */ - if (config->conv_mode == adc16_conv_mode_oneshot) { - /* Set wait_dis */ - ptr->BUF_CFG0 = ADC16_BUF_CFG0_WAIT_DIS_SET(config->wait_dis); - } + ptr->BUF_CFG0 = ADC16_BUF_CFG0_WAIT_DIS_SET(config->wait_dis); /* Get input clock divider */ clk_div_temp = ADC16_CONV_CFG1_CLOCK_DIVIDER_GET(ptr->CONV_CFG1); @@ -201,6 +209,11 @@ hpm_stat_t adc16_init_channel(ADC16_Type *ptr, adc16_channel_config_t *config) return status_invalid_argument; } + /* Check sample cycle */ + if (ADC16_IS_CHANNEL_SAMPLE_CYCLE_INVALID(config->sample_cycle)) { + return status_invalid_argument; + } + /* Set warning threshold */ ptr->PRD_CFG[config->ch].PRD_THSHD_CFG = ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SET(config->thshdh) | ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SET(config->thshdl); @@ -210,9 +223,40 @@ hpm_stat_t adc16_init_channel(ADC16_Type *ptr, adc16_channel_config_t *config) ptr->SAMPLE_CFG[config->ch] = ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SET(config->sample_cycle_shift) | ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SET(config->sample_cycle); + /* Enable watchdog interrupt */ + if (config->wdog_int_en) { + ptr->INT_EN |= 1 << config->ch; + } + return status_success; } +hpm_stat_t adc16_get_channel_threshold(ADC16_Type *ptr, uint8_t ch, adc16_channel_threshold_t *config) +{ + /* Check the specified channel number */ + if (ADC16_IS_CHANNEL_INVALID(ch)) { + return status_invalid_argument; + } + + config->ch = ch; + config->thshdh = ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_GET(ptr->PRD_CFG[ch].PRD_THSHD_CFG); + config->thshdl = ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_GET(ptr->PRD_CFG[ch].PRD_THSHD_CFG); + + return status_success; +} + +#if defined(ADC_SOC_BUSMODE_ENABLE_CTRL_SUPPORT) && ADC_SOC_BUSMODE_ENABLE_CTRL_SUPPORT +void adc16_enable_oneshot_mode(ADC16_Type *ptr) +{ + ptr->BUF_CFG0 |= ADC16_BUF_CFG0_BUS_MODE_EN_MASK; +} + +void adc16_disable_oneshot_mode(ADC16_Type *ptr) +{ + ptr->BUF_CFG0 &= ~ADC16_BUF_CFG0_BUS_MODE_EN_MASK; +} +#endif + hpm_stat_t adc16_init_seq_dma(ADC16_Type *ptr, adc16_dma_config_t *dma_config) { /* Check the DMA buffer length */ @@ -236,11 +280,22 @@ hpm_stat_t adc16_init_seq_dma(ADC16_Type *ptr, adc16_dma_config_t *dma_config) ptr->SEQ_DMA_CFG = (ptr->SEQ_DMA_CFG & ~ADC16_SEQ_DMA_CFG_BUF_LEN_MASK) | ADC16_SEQ_DMA_CFG_BUF_LEN_SET(dma_config->buff_len_in_4bytes - 1); + #if defined(ADC_SOC_SEQ_HCFG_EN) && ADC_SOC_SEQ_HCFG_EN + /* Set high-half buffer length */ + ptr->SEQ_HIGH_CFG = (ptr->SEQ_HIGH_CFG & ~ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_MASK) + | ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_SET(((dma_config->buff_len_in_4bytes - 1) >> 12)); + #endif + /* Set stop_en and stop_pos */ if (dma_config->stop_en) { ptr->SEQ_DMA_CFG = (ptr->SEQ_DMA_CFG & ~ADC16_SEQ_DMA_CFG_STOP_POS_MASK) | ADC16_SEQ_DMA_CFG_STOP_EN_MASK | ADC16_SEQ_DMA_CFG_STOP_POS_SET(dma_config->stop_pos); + + #if defined(ADC_SOC_SEQ_HCFG_EN) && ADC_SOC_SEQ_HCFG_EN + ptr->SEQ_HIGH_CFG = (ptr->SEQ_HIGH_CFG & ~ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_MASK) + | ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_SET(((dma_config->stop_pos) >> 12)); + #endif } return status_success; @@ -262,10 +317,9 @@ hpm_stat_t adc16_set_prd_config(ADC16_Type *ptr, adc16_prd_config_t *config) ptr->PRD_CFG[config->ch].PRD_CFG = (ptr->PRD_CFG[config->ch].PRD_CFG & ~ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK) | ADC16_PRD_CFG_PRD_CFG_PRESCALE_SET(config->prescale); - /* Set period count */ - ptr->PRD_CFG[config->ch].PRD_CFG = (ptr->PRD_CFG[config->ch].PRD_CFG & ~ADC16_PRD_CFG_PRD_CFG_PRD_MASK) - | ADC16_PRD_CFG_PRD_CFG_PRD_SET(config->period_count); + ptr->PRD_CFG[config->ch].PRD_CFG = (ptr->PRD_CFG[config->ch].PRD_CFG & ~ADC16_PRD_CFG_PRD_CFG_PRD_MASK) + | ADC16_PRD_CFG_PRD_CFG_PRD_SET(config->period_count); return status_success; } @@ -347,6 +401,7 @@ hpm_stat_t adc16_set_pmt_config(ADC16_Type *ptr, adc16_pmt_config_t *config) hpm_stat_t adc16_set_pmt_queue_enable(ADC16_Type *ptr, uint8_t trig_ch, bool enable) { + (void) ptr; /* Check the specified trigger channel */ if (ADC16_IS_TRIG_CH_INVLAID(trig_ch)) { return status_invalid_argument; @@ -357,6 +412,7 @@ hpm_stat_t adc16_set_pmt_queue_enable(ADC16_Type *ptr, uint8_t trig_ch, bool ena ptr->CONFIG[trig_ch] |= ADC16_CONFIG_QUEUE_EN_SET(enable); return status_success; #else + (void) enable; return status_success; #endif } diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_cam_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_cam_drv.c index 3c58d8a8445..f318799b4fc 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_cam_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_cam_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -11,14 +11,17 @@ void cam_get_default_config(CAM_Type *ptr, cam_config_t *config, display_pixel_format_t pixel_format) { + (void) ptr; config->width = 320; config->height = 240; + config->buffer1 = -1; + config->buffer2 = -1; config->pixclk_sampling_falling = false; config->hsync_active_low = false; config->vsync_active_low = false; + config->de_active_low = false; config->color_ext = false; config->data_pack_msb = false; - config->enable_buffer2 = false; config->data_store_mode = CAM_DATA_STORE_MODE_NORMAL; config->color_format = pixel_format; config->sensor_bitwidth = CAM_SENSOR_BITWIDTH_10BITS; @@ -78,6 +81,10 @@ hpm_stat_t cam_init(CAM_Type *ptr, cam_config_t *config) pixel_format = config->color_format; width = config->width; + if ((int)config->buffer1 < 0) { + return status_invalid_argument; + } + if (pixel_format == CAM_COLOR_FORMAT_RAW8) { if ((width % 2) != 0) { return status_invalid_argument; @@ -89,9 +96,17 @@ hpm_stat_t cam_init(CAM_Type *ptr, cam_config_t *config) cam_reset(ptr); + /* + * In DVP mode, de_active_low and hsync_active_low are same. + */ + if (config->sensor_bitwidth != CAM_SENSOR_BITWIDTH_24BITS) { + config->de_active_low = config->hsync_active_low; + } + ptr->CR1 = CAM_CR1_INV_PIXCLK_SET(config->pixclk_sampling_falling) | CAM_CR1_INV_HSYNC_SET(config->hsync_active_low) | CAM_CR1_INV_VSYNC_SET(config->vsync_active_low) + | CAM_CR1_INV_DEN_SET(config->de_active_low) | CAM_CR1_RESTART_BUSPTR_MASK | CAM_CR1_COLOR_EXT_SET(config->color_ext) | CAM_CR1_PACK_DIR_SET(config->data_pack_msb) @@ -102,13 +117,12 @@ hpm_stat_t cam_init(CAM_Type *ptr, cam_config_t *config) ptr->IDEAL_WN_SIZE = CAM_IDEAL_WN_SIZE_HEIGHT_SET(config->height) | CAM_IDEAL_WN_SIZE_WIDTH_SET(width); - ptr->MAX_WN_CYCLE = CAM_MAX_WN_CYCLE_ROW_SET(1200) - | CAM_MAX_WN_CYCLE_COL_SET(2090); - ptr->CR2 = CAM_CR2_DMA_REQ_EN_RFF_MASK | CAM_CR2_RXFF_LEVEL_SET(CAM_RX_FIFO_THRESHOLD); ptr->DMASA_FB1 = config->buffer1; - if (config->enable_buffer2) { + if ((int)config->buffer2 < 0) { + ptr->DMASA_FB2 = config->buffer1; + } else { ptr->DMASA_FB2 = config->buffer2; } @@ -125,11 +139,6 @@ hpm_stat_t cam_init(CAM_Type *ptr, cam_config_t *config) return stat; } -void cam_update_buffer(CAM_Type *ptr, uint32_t buffer) -{ - ptr->DMASA_FB1 = buffer; -} - void cam_stop(CAM_Type *ptr) { ptr->CR18 &= ~CAM_CR18_CAM_ENABLE_MASK; @@ -140,3 +149,13 @@ void cam_start(CAM_Type *ptr) ptr->CR18 |= CAM_CR18_CAM_ENABLE_MASK; } +void cam_stop_safely(CAM_Type *ptr) +{ + /* + * waiting for capture frame to complete + */ + cam_clear_status(ptr, cam_status_end_of_frame); + while (cam_check_status(ptr, cam_status_end_of_frame) == false) { + } + cam_stop(ptr); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_can_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_can_drv.c index b7a10b0669d..284840f433a 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_can_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_can_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -611,8 +611,8 @@ hpm_stat_t can_get_default_config(can_config_t *config) config->mode = can_mode_normal; config->enable_self_ack = false; - config->disable_re_transmission_for_stb = false; - config->disable_re_transmission_for_ptb = false; + config->disable_stb_retransmission = false; + config->disable_ptb_retransmission = false; config->enable_tx_buffer_priority_mode = false; config->enable_tdc = false; @@ -671,17 +671,6 @@ hpm_stat_t can_init(CAN_Type *base, can_config_t *config, uint32_t src_clk_freq) HPM_BREAK_IF(status != status_success); - if (config->disable_re_transmission_for_ptb) { - base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TPSS_MASK; - } else { - base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_TPSS_MASK; - } - - if (config->disable_re_transmission_for_stb) { - base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TSSS_MASK; - } else { - base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_TSSS_MASK; - } /* Configure CAN filters */ if (config->filter_list_num > CAN_FILTER_NUM_MAX) { @@ -710,6 +699,13 @@ hpm_stat_t can_init(CAN_Type *base, can_config_t *config, uint32_t src_clk_freq) can_reset(base, false); + /* The following mode must be set when the CAN controller is not in reset mode */ + + /* Disable re-transmission on PTB on demand */ + can_disable_ptb_retransmission(base, config->disable_ptb_retransmission); + /* Disable re-transmission on STB on demand */ + can_disable_stb_retransmission(base, config->disable_stb_retransmission); + /* Set Self-ack mode*/ can_enable_self_ack(base, config->enable_self_ack); @@ -730,3 +726,11 @@ hpm_stat_t can_init(CAN_Type *base, can_config_t *config, uint32_t src_clk_freq) return status; } + +void can_deinit(CAN_Type *base) +{ + do { + HPM_BREAK_IF(base == NULL); + can_reset(base, true); + } while (false); +} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_crc_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_crc_drv.c index 862666bc41f..f329c1b9788 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_crc_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_crc_drv.c @@ -23,7 +23,6 @@ void crc_get_default_channel_config(crc_channel_config_t *cfg) hpm_stat_t crc_setup_channel_config(CRC_Type *ptr, uint32_t ch_index, crc_channel_config_t *cfg) { - ptr->CHN[ch_index].CLR |= CRC_CHN_CLR_CLR_MASK; ptr->CHN[ch_index].PRE_SET = cfg->preset; if (!ptr->CHN[ch_index].PRE_SET) { diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dac_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dac_drv.c index 470022cedec..1e312f18e89 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dac_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dac_drv.c @@ -16,7 +16,7 @@ void dac_get_default_config(dac_config_t *config) hpm_stat_t dac_init(DAC_Type *ptr, dac_config_t *config) { - if (config->dac_mode > dac_mode_buffer) { + if (config->dac_mode > dac_mode_trig) { return status_invalid_argument; } @@ -42,7 +42,7 @@ hpm_stat_t dac_init(DAC_Type *ptr, dac_config_t *config) ptr->CFG1 &= ~DAC_CFG1_ANA_DIV_CFG_MASK; ptr->CFG1 |= DAC_CFG1_ANA_DIV_CFG_SET(config->ana_div); - if (config->dac_mode == dac_mode_direct) { + if (config->dac_mode == dac_mode_direct || config->dac_mode == dac_mode_trig) { /* set ANA_CLK_EN */ ptr->CFG1 |= DAC_CFG1_ANA_CLK_EN_MASK; } @@ -264,7 +264,7 @@ uint32_t dac_get_status_flags(DAC_Type *ptr) void dac_set_status_flags(DAC_Type *ptr, uint32_t mask) { - ptr->IRQ_STS |= mask; + ptr->IRQ_STS = mask; } uint8_t dac_get_current_buffer_index(DAC_Type *ptr) diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dao_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dao_drv.c index b9d9500f021..d61adc0b950 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dao_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dao_drv.c @@ -5,12 +5,22 @@ * */ #include "hpm_dao_drv.h" +#include "hpm_i2s_common.h" void dao_get_default_config(DAO_Type *ptr, dao_config_t *config) { + (void) ptr; config->enable_mono_output = false; config->default_output_level = DAO_DEFAULT_OUTPUT_ALL_LOW; config->channel_count = 2; +#if defined(DAO_SOC_SUPPORT_DATA_FORMAT_CONFIG) && (DAO_SOC_SUPPORT_DATA_FORMAT_CONFIG == 1) + config->enable_tdm_mode = false; + config->frame_start_at_rising_edge = false; + config->protocol = I2S_PROTOCOL_MSB_JUSTIFIED; + config->channel_length = i2s_channel_length_32_bits; + config->audio_depth = i2s_audio_depth_32_bits; +#endif + config->channel_slot_mask = 0x3; /* 2 channel mask */ } hpm_stat_t dao_init(DAO_Type *ptr, dao_config_t *config) @@ -24,15 +34,20 @@ hpm_stat_t dao_init(DAO_Type *ptr, dao_config_t *config) | DAO_CHANNEL_BOTH | DAO_CTRL_REMAP_MASK | DAO_CTRL_FALSE_LEVEL_SET(config->default_output_level); + +#if defined(DAO_SOC_SUPPORT_DATA_FORMAT_CONFIG) && (DAO_SOC_SUPPORT_DATA_FORMAT_CONFIG == 1) + ptr->RX_CFGR = DAO_RX_CFGR_FRAME_EDGE_SET(config->frame_start_at_rising_edge) + | DAO_RX_CFGR_CH_MAX_SET(config->channel_count) + | DAO_RX_CFGR_TDM_EN_SET(config->enable_tdm_mode) + | DAO_RX_CFGR_STD_SET(config->protocol) + | DAO_RX_CFGR_DATSIZ_SET(I2S_CFGR_DATASIZ(config->audio_depth)) + | DAO_RX_CFGR_CHSIZ_SET(I2S_CFGR_CHSIZ(config->channel_length)); +#else ptr->RX_CFGR = DAO_RX_CFGR_CH_MAX_SET(config->channel_count); - if (config->channel_count < 31) { - ptr->RXSLT = (1 << config->channel_count) - 1; - } else if (config->channel_count == 32) { - ptr->RXSLT = 0xFFFFFFFF; - } else { - /* channel count is not correct */ - return status_fail; - } +#endif + + ptr->RXSLT = config->channel_slot_mask; + return status_success; } diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dma_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dma_drv.c index d4b29da0d2a..f3f9e874356 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dma_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dma_drv.c @@ -60,7 +60,8 @@ hpm_stat_t dma_setup_channel(DMA_Type *ptr, uint8_t ch_num, dma_channel_config_t void dma_default_channel_config(DMA_Type *ptr, dma_channel_config_t *ch) { - ch->priority = 0; + (void) ptr; + ch->priority = DMA_CHANNEL_PRIORITY_LOW; ch->src_mode = DMA_HANDSHAKE_MODE_NORMAL; ch->dst_mode = DMA_HANDSHAKE_MODE_NORMAL; ch->src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; @@ -132,7 +133,7 @@ hpm_stat_t dma_start_memcpy(DMA_Type *ptr, uint8_t ch_num, /* burst size checking (1-byte burst length will cause heavy overhead */ if (!burst_len_in_byte || burst_len_in_byte == 1 || burst_len_in_byte > size || burst_len_in_byte > - ((1 << DMA_SOC_TRANSFER_WIDTH_MAX(ptr)) << DMA_SOC_TRANSFER_PER_BURST_MAX(ptr))) { + (uint32_t) ((1 << DMA_SOC_TRANSFER_WIDTH_MAX(ptr)) << DMA_SOC_TRANSFER_PER_BURST_MAX(ptr))) { return status_invalid_argument; } @@ -183,6 +184,7 @@ hpm_stat_t dma_start_memcpy(DMA_Type *ptr, uint8_t ch_num, void dma_default_handshake_config(DMA_Type *ptr, dma_handshake_config_t *config) { + (void) ptr; memset(config, 0, sizeof(dma_handshake_config_t)); } diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dmav2_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dmav2_drv.c new file mode 100644 index 00000000000..c006045b5bb --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dmav2_drv.c @@ -0,0 +1,216 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_dmav2_drv.h" + +hpm_stat_t dma_setup_channel(DMAV2_Type *ptr, uint8_t ch_num, dma_channel_config_t *ch, bool start_transfer) +{ + uint32_t tmp; + + if ((ch->dst_width > DMA_SOC_TRANSFER_WIDTH_MAX(ptr)) + || (ch->src_width > DMA_SOC_TRANSFER_WIDTH_MAX(ptr)) + || (ch_num >= DMA_SOC_CHANNEL_NUM) + || (ch->en_infiniteloop && (ch->linked_ptr != 0))) { + return status_invalid_argument; + } + if ((ch->size_in_byte & ((1 << ch->dst_width) - 1)) + || (ch->src_addr & ((1 << ch->src_width) - 1)) + || (ch->dst_addr & ((1 << ch->dst_width) - 1)) + || ((1 << ch->src_width) & ((1 << ch->dst_width) - 1)) + || ((ch->linked_ptr & 0x7))) { + return status_dma_alignment_error; + } + ptr->CHCTRL[ch_num].SRCADDR = DMAV2_CHCTRL_SRCADDR_SRCADDRL_SET(ch->src_addr); + ptr->CHCTRL[ch_num].DSTADDR = DMAV2_CHCTRL_DSTADDR_DSTADDRL_SET(ch->dst_addr); + ptr->CHCTRL[ch_num].TRANSIZE = DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SET(ch->size_in_byte >> ch->src_width); + ptr->CHCTRL[ch_num].LLPOINTER = DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SET(ch->linked_ptr >> DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT); + ptr->CHCTRL[ch_num].CHANREQCTRL = DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SET(ch_num) | DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SET(ch_num); + + dma_clear_transfer_status(ptr, ch_num); + tmp = DMAV2_CHCTRL_CTRL_INFINITELOOP_SET(ch->en_infiniteloop) + | DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SET(ch->handshake_opt) + | DMAV2_CHCTRL_CTRL_BURSTOPT_SET(ch->burst_opt) + | DMAV2_CHCTRL_CTRL_PRIORITY_SET(ch->priority) + | DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SET(ch->src_burst_size) + | DMAV2_CHCTRL_CTRL_SRCWIDTH_SET(ch->src_width) + | DMAV2_CHCTRL_CTRL_DSTWIDTH_SET(ch->dst_width) + | DMAV2_CHCTRL_CTRL_SRCMODE_SET(ch->src_mode) + | DMAV2_CHCTRL_CTRL_DSTMODE_SET(ch->dst_mode) + | DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SET(ch->src_addr_ctrl) + | DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SET(ch->dst_addr_ctrl) + | ch->interrupt_mask; + + if (start_transfer) { + tmp |= DMAV2_CHCTRL_CTRL_ENABLE_MASK; + } + ptr->CHCTRL[ch_num].CTRL = tmp; + + return status_success; +} + +void dma_default_channel_config(DMAV2_Type *ptr, dma_channel_config_t *ch) +{ + (void) ptr; + ch->en_infiniteloop = false; + ch->handshake_opt = DMA_HANDSHAKE_OPT_ONE_BURST; + ch->burst_opt = DMA_SRC_BURST_OPT_STANDAND_SIZE; + ch->priority = DMA_CHANNEL_PRIORITY_LOW; + ch->src_mode = DMA_HANDSHAKE_MODE_NORMAL; + ch->dst_mode = DMA_HANDSHAKE_MODE_NORMAL; + ch->src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; + ch->src_addr_ctrl = DMA_ADDRESS_CONTROL_INCREMENT; + ch->dst_addr_ctrl = DMA_ADDRESS_CONTROL_INCREMENT; + ch->interrupt_mask = DMA_INTERRUPT_MASK_HALF_TC; /* disable half complete interrupt to keep align with dma */ + ch->linked_ptr = 0; +} + +hpm_stat_t dma_config_linked_descriptor(DMAV2_Type *ptr, dma_linked_descriptor_t *descriptor, uint8_t ch_num, dma_channel_config_t *config) +{ + (void) ptr; + uint32_t tmp; + + if ((config->dst_width > DMA_SOC_TRANSFER_WIDTH_MAX(ptr)) + || (config->src_width > DMA_SOC_TRANSFER_WIDTH_MAX(ptr)) + || (ch_num >= DMA_SOC_CHANNEL_NUM) + || (config->en_infiniteloop)) { + return status_invalid_argument; + } + if ((config->size_in_byte & ((1 << config->dst_width) - 1)) + || (config->src_addr & ((1 << config->src_width) - 1)) + || (config->dst_addr & ((1 << config->dst_width) - 1)) + || ((1 << config->src_width) & ((1 << config->dst_width) - 1)) + || ((config->linked_ptr & 0x7))) { + return status_dma_alignment_error; + } + descriptor->src_addr = DMAV2_CHCTRL_SRCADDR_SRCADDRL_SET(config->src_addr); + descriptor->dst_addr = DMAV2_CHCTRL_DSTADDR_DSTADDRL_SET(config->dst_addr); + descriptor->trans_size = DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SET(config->size_in_byte >> config->src_width); + descriptor->linked_ptr = DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SET(config->linked_ptr >> DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT); + descriptor->req_ctrl = DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SET(ch_num) | DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SET(ch_num); + + tmp = DMAV2_CHCTRL_CTRL_INFINITELOOP_SET(false) + | DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SET(config->handshake_opt) + | DMAV2_CHCTRL_CTRL_BURSTOPT_SET(config->burst_opt) + | DMAV2_CHCTRL_CTRL_PRIORITY_SET(config->priority) + | DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SET(config->src_burst_size) + | DMAV2_CHCTRL_CTRL_SRCWIDTH_SET(config->src_width) + | DMAV2_CHCTRL_CTRL_DSTWIDTH_SET(config->dst_width) + | DMAV2_CHCTRL_CTRL_SRCMODE_SET(config->src_mode) + | DMAV2_CHCTRL_CTRL_DSTMODE_SET(config->dst_mode) + | DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SET(config->src_addr_ctrl) + | DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SET(config->dst_addr_ctrl) + | config->interrupt_mask + | DMAV2_CHCTRL_CTRL_ENABLE_MASK; + descriptor->ctrl = tmp; + + return status_success; +} + +hpm_stat_t dma_start_memcpy(DMAV2_Type *ptr, uint8_t ch_num, + uint32_t dst, uint32_t src, + uint32_t size, uint32_t burst_len_in_byte) +{ + hpm_stat_t stat = status_success; + uint32_t width, count; + uint32_t burst_size; + dma_channel_config_t config = {0}; + dma_default_channel_config(ptr, &config); + + /* burst size checking (1-byte burst length will cause heavy overhead */ + if (!burst_len_in_byte || burst_len_in_byte == 1 || burst_len_in_byte > size + || burst_len_in_byte > + (uint32_t) ((1 << DMA_SOC_TRANSFER_WIDTH_MAX(ptr)) << DMA_SOC_TRANSFER_PER_BURST_MAX(ptr))) { + return status_invalid_argument; + } + + count = count_set_bits(burst_len_in_byte); + if ((count > 1) || (burst_len_in_byte & 0x1)) { + /* dma only supports 2^n bytes as burst size */ + return status_invalid_argument; + } + + if ((size & (burst_len_in_byte - 1))) { + return status_dma_alignment_error; + } + burst_size = get_first_set_bit_from_lsb(burst_len_in_byte); + + config.src_width = DMA_TRANSFER_WIDTH_HALF_WORD; + config.dst_width = DMA_TRANSFER_WIDTH_HALF_WORD; + for (width = DMA_SOC_TRANSFER_WIDTH_MAX(ptr); width > DMA_TRANSFER_WIDTH_HALF_WORD; width--) { + if (!(burst_len_in_byte & ((1 << width) - 1)) + && !(dst & ((1 << width) - 1)) + && !(src & ((1 << width) - 1)) + && !(size & ((1 << width) - 1))) { + config.src_width = width; + config.dst_width = width; + break; + } + } + + burst_size -= config.src_width; + do { + if (!(src & (((1 << config.src_width) << burst_size) - 1))) { + break; + } + burst_size--; + } while (burst_size > 0); + + config.src_addr = src; + config.dst_addr = dst; + config.size_in_byte = size; + + config.src_burst_size = burst_size; + stat = dma_setup_channel(ptr, ch_num, &config, true); + if (stat != status_success) { + return stat; + } + + return stat; +} + +void dma_default_handshake_config(DMAV2_Type *ptr, dma_handshake_config_t *config) +{ + (void) ptr; + memset(config, 0, sizeof(dma_handshake_config_t)); + config->en_infiniteloop = false; + config->interrupt_mask = DMA_INTERRUPT_MASK_HALF_TC; +} + +hpm_stat_t dma_setup_handshake(DMAV2_Type *ptr, dma_handshake_config_t *pconfig, bool start_transfer) +{ + hpm_stat_t stat = status_success; + dma_channel_config_t config = {0}; + dma_default_channel_config(ptr, &config); + + if (true == pconfig->dst_fixed) { + config.dst_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; + config.dst_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; + } + if (true == pconfig->src_fixed) { + config.src_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; + config.src_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; + } + + if (pconfig->ch_index >= DMA_SOC_CHANNEL_NUM) { + return status_invalid_argument; + } + + config.en_infiniteloop = pconfig->en_infiniteloop; + config.interrupt_mask = pconfig->interrupt_mask; + config.src_width = pconfig->data_width; + config.dst_width = pconfig->data_width; + config.src_addr = pconfig->src; + config.dst_addr = pconfig->dst; + config.size_in_byte = pconfig->size_in_byte; + /* In DMA handshake case, source burst size must be 1 transfer, that is 0. */ + config.src_burst_size = 0; + stat = dma_setup_channel(ptr, pconfig->ch_index, &config, start_transfer); + if (stat != status_success) { + return stat; + } + return stat; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_enc_pos_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_enc_pos_drv.c new file mode 100644 index 00000000000..3a437a03e52 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_enc_pos_drv.c @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_enc_pos_drv.h" + + +float encoder_position_to_deg(uint32_t pos) +{ + double tmp; + + tmp = ((double)pos / (double)0xFFFFFFFF) * (double)360.0; + + return (float)tmp; +} + +uint32_t encoder_deg_to_position(float deg) +{ + double tmp; + + while (deg < 0) { + deg += 360; + } + while (deg > 360) { + deg -= 360; + } + + tmp = ((double)deg / (double)360.0) * (double)0xFFFFFFFF; + + return (uint32_t)tmp; +} + +float encoder_position_to_rad(uint32_t pos) +{ + double tmp; + const double _2pi = 6.283185307179586; + + tmp = ((double)pos / (double)0xFFFFFFFF) * _2pi; + + return (float)tmp; +} + +uint32_t encoder_rad_to_position(float rad) +{ + double tmp; + const double _2pi = 6.283185307179586; + + while (rad < 0) { + rad += _2pi; + } + while (rad > _2pi) { + rad -= _2pi; + } + + tmp = ((double)rad / _2pi) * (double)0xFFFFFFFF; + + return (uint32_t)tmp; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_enet_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_enet_drv.c index 4741b45c81f..91f37f90efc 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_enet_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_enet_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -228,7 +228,7 @@ void enet_set_duplex_mode(ENET_Type *ptr, enet_duplex_mode_t mode) ptr->MACCFG |= ENET_MACCFG_DM_SET(mode); } -int enet_controller_init(ENET_Type *ptr, enet_inf_type_t inf_type, enet_desc_t *desc, enet_mac_config_t *config, enet_int_config_t *int_config) +hpm_stat_t enet_controller_init(ENET_Type *ptr, enet_inf_type_t inf_type, enet_desc_t *desc, enet_mac_config_t *config, enet_int_config_t *int_config) { /* select an interface */ enet_intf_selection(ptr, inf_type); @@ -248,13 +248,20 @@ int enet_controller_init(ENET_Type *ptr, enet_inf_type_t inf_type, enet_desc_t * /* mask the mmc tx interrupts */ enet_mask_mmc_tx_interrupt_event(ptr, int_config->mmc_intr_mask_tx); - return true; + return status_success; } /***************************************************************************** * DMA API - ***************************************************************************** - */ + ****************************************************************************/ +void enet_rx_resume(ENET_Type *ptr) +{ + if (ENET_DMA_STATUS_RU_GET(ptr->DMA_STATUS)) { + ptr->DMA_STATUS = ENET_DMA_STATUS_RU_MASK; + ptr->DMA_RX_POLL_DEMAND = 1; + } +} + uint32_t enet_check_received_frame(enet_rx_desc_t **parent_rx_desc_list_cur, enet_rx_frame_info_t *rx_frame_info) { enet_rx_desc_t *rx_desc_list_cur = *parent_rx_desc_list_cur; @@ -381,6 +388,7 @@ enet_frame_t enet_get_received_frame_interrupt(enet_rx_desc_t **parent_rx_desc_l void enet_get_default_tx_control_config(ENET_Type *ptr, enet_tx_control_config_t *config) { + (void) ptr; config->enable_ioc = false; config->disable_crc = true; config->disable_pad = false; diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ewdg_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ewdg_drv.c new file mode 100644 index 00000000000..d18894f98db --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ewdg_drv.c @@ -0,0 +1,486 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_ewdg_drv.h" + +/*********************************************************************************************************************** + * + * Definitions + * + **********************************************************************************************************************/ +#define EWDG_CTRL_REG_PARITY_BIT_MASK (1UL << 31) /*!< Parity bit for Control Register */ + +#ifdef EWDG_SOC_CLK_DIV_VAL_MAX +#define EWDG_CTRL_DIV_VAL_MAX EWDG_SOC_CLK_DIV_VAL_MAX +#else +#define EWDG_CTRL_DIV_VAL_MAX (EWDG_CTRL0_DIV_VALUE_MASK >> EWDG_CTRL0_DIV_VALUE_SHIFT) +#endif +#define EWDG_CTRL_WIN_UPPER_MAX (EWDG_CTRL0_WIN_UPPER_MASK >> EWDG_CTRL0_WIN_UPPER_SHIFT) + +#define EWDG_CTRL_REG_UPDATE_PERIOD_DEFAULT (4UL) /* 512 Bus clock */ + +#define EWDG_RING_LEFT_SHIFT_1(val) (((uint16_t)(val) << 1) | ((uint16_t)(val) >> 15)) + +#define EWDG_REFRESH_PERIOD_DEFAULT (10000U) + +#define EWDG_INTERRUPT_TIMEOUT_TICKS_DEFAULT (0UL) +#define EWDG_RESET_TIMEOUT_TICKS_DEFAULT (65535UL) + +#if defined(EWDG_SOC_OVERTIME_REG_WIDTH) && (EWDG_SOC_OVERTIME_REG_WIDTH == 16) +#define EWDG_TIMEOUT_TICK_MAX (65535) +#else +#define EWDG_TIMEOUT_TICK_MAX (0xFFFFFFFFUL) +#endif + +/*********************************************************************************************************************** + * + * Prototypes + * + **********************************************************************************************************************/ +static bool ewdg_need_set_parity_bit(uint32_t reg_val); + +/*********************************************************************************************************************** + * + * Codes + * + **********************************************************************************************************************/ +static bool ewdg_need_set_parity_bit(uint32_t reg_val) +{ + uint32_t non_zero_bits = 0; + while (reg_val > 0) { + reg_val &= (reg_val - 1UL); + ++non_zero_bits; + } + return ((non_zero_bits & 1UL) != 0); +} + +void ewdg_get_default_config(EWDG_Type *ptr, ewdg_config_t *config) +{ + if ((ptr != NULL) && (config != NULL)) { + + (void) memset(config, 0, sizeof(ewdg_config_t)); + + config->ctrl_config.cnt_clk_sel = ewdg_cnt_clk_src_ext_osc_clk; + config->ctrl_config.use_lowlevel_timeout = true; + + config->ctrl_config.refresh_unlock_method = ewdg_refresh_unlock_method_password; + config->ctrl_config.enable_overtime_self_clear = false; + + config->ctrl_config.timeout_interrupt_val = EWDG_INTERRUPT_TIMEOUT_TICKS_DEFAULT; + config->ctrl_config.timeout_reset_val = EWDG_RESET_TIMEOUT_TICKS_DEFAULT; + config->ctrl_config.clock_div_by_power_of_2 = 0; + + config->ctrl_config.refresh_unlock_password = EWDG_REFRESH_UNLOCK_PASSWORD_DEFAULT; + config->ctrl_config.ctrl_reg_update_password = EWDG_UPDATE_PASSWORD_DEFAULT; + config->ctrl_config.ctrl_reg_update_period_bus_clk_x_128 = EWDG_CTRL_REG_UPDATE_PERIOD_DEFAULT; + + config->ctrl_config.low_power_mode = ewdg_low_power_mode_work_clock_normal; + + config->ctrl_config.refresh_period_in_bus_cycles = EWDG_REFRESH_PERIOD_DEFAULT; + } +} + +hpm_stat_t ewdg_init_ctrl_func(EWDG_Type *ptr, ewdg_func_ctrl_config_t *config, uint32_t cnt_src_freq) +{ + hpm_stat_t status = status_invalid_argument; + + do { + if ((ptr == NULL) || (config == NULL) || (cnt_src_freq == 0)) { + break; + } + if (config->window_lower_limit > ewdg_window_lower_timeout_period_max) { + break; + } + if (config->window_upper_limit > ewdg_window_upper_timeout_period_max) { + break; + } + if (config->refresh_unlock_method > ewdg_refresh_unlock_method_max) { + break; + } + + uint32_t ctrl0 = 0; + + uint32_t ot_int_ticks; + uint32_t ot_reset_ticks; + uint32_t clock_div_by_pwr_2 = 0; + if (!config->use_lowlevel_timeout) { + uint64_t timeout_interrupt_ticks = ewdg_convert_timeout_us_to_timeout_ticks(config->timeout_interrupt_us, + cnt_src_freq); + uint64_t timeout_reset_ticks = ewdg_convert_timeout_us_to_timeout_ticks(config->timeout_reset_us, + cnt_src_freq); + clock_div_by_pwr_2 = 0; + while ((timeout_interrupt_ticks > EWDG_TIMEOUT_TICK_MAX) || (timeout_reset_ticks > EWDG_TIMEOUT_TICK_MAX)) { + ++clock_div_by_pwr_2; + timeout_interrupt_ticks >>= 1; + timeout_reset_ticks >>= 1; + } + if (clock_div_by_pwr_2 > EWDG_SOC_CLK_DIV_VAL_MAX) { + status = status_ewdg_div_out_of_range; + /* Cannot get the expected EWDG setting via the specified timeout input */ + break; + } + ot_int_ticks = (uint32_t) (timeout_interrupt_ticks & 0xFFFFFFFFUL); + ot_reset_ticks = (uint32_t) (timeout_reset_ticks & 0xFFFFFFFFUL); + + } else { + clock_div_by_pwr_2 = config->clock_div_by_power_of_2; + ot_int_ticks = config->timeout_interrupt_val; + ot_reset_ticks = config->timeout_reset_val; + + if (clock_div_by_pwr_2 > EWDG_SOC_CLK_DIV_VAL_MAX) { + status = status_ewdg_div_out_of_range; + /* Cannot get the expected EWDG setting via the specified timeout input */ + break; + } + if ((ot_int_ticks > EWDG_TIMEOUT_TICK_MAX) || (ot_reset_ticks > EWDG_TIMEOUT_TICK_MAX)) { + status = status_ewdg_tick_out_of_range; + break; + } + } + + if (config->cnt_clk_sel == ewdg_cnt_clk_src_ext_osc_clk) { + ctrl0 |= EWDG_CTRL0_CLK_SEL_MASK; + } + ctrl0 |= EWDG_CTRL0_DIV_VALUE_SET(clock_div_by_pwr_2); + if (config->enable_window_mode) { + ctrl0 |= EWDG_CTRL0_WIN_EN_MASK; + + ctrl0 |= EWDG_CTRL0_WIN_LOWER_SET(config->window_lower_limit); + ctrl0 |= EWDG_CTRL0_WIN_UPPER_SET(config->window_upper_limit); + } + + if (config->enable_config_lock) { + ctrl0 |= EWDG_CTRL0_CFG_LOCK_MASK; + } + + if (config->enable_refresh_period) { + ctrl0 |= EWDG_CTRL0_REF_OT_REQ_MASK; + } + if (config->enable_refresh_lock) { + ctrl0 |= EWDG_CTRL0_REF_LOCK_MASK; + } + ctrl0 |= EWDG_CTRL0_REF_UNLOCK_MEC_SET(config->refresh_unlock_method); + + if (config->enable_overtime_self_clear) { + ctrl0 |= EWDG_CTRL0_OT_SELF_CLEAR_MASK; + } + if (config->keep_running_in_debug_mode) { + ctrl0 |= EWDG_CTRL0_EN_DBG_MASK; + } + ctrl0 |= EWDG_CTRL0_EN_LP_SET(config->low_power_mode); + + /* Set Parity bit if necessary */ + if (ewdg_need_set_parity_bit(ctrl0)) { + ctrl0 |= EWDG_CTRL_REG_PARITY_BIT_MASK; + } + + if (ewdg_is_ctrl_reg_locked(ptr)) { + ewdg_unlock_ctrl_regs(ptr); + } + ptr->CTRL0 = ctrl0; + + ptr->CFG_PROT = EWDG_CFG_PROT_UPD_OT_TIME_SET(config->ctrl_reg_update_period_bus_clk_x_128) | + EWDG_CFG_PROT_UPD_PSD_SET(config->ctrl_reg_update_password); + + ptr->REF_TIME = config->refresh_period_in_bus_cycles; + ptr->REF_PROT = EWDG_REF_PROT_REF_UNL_PSD_SET(config->refresh_unlock_password); + + +#if !defined(EWDG_SOC_SUPPORT_TIMEOUT_INTERRUPT) || (EWDG_SOC_SUPPORT_TIMEOUT_INTERRUPT == 1) + ptr->OT_INT_VAL = ot_int_ticks; +#endif + ptr->OT_RST_VAL = ot_reset_ticks; + + status = status_success; + + } while (false); + + return status; +} + +hpm_stat_t ewdg_init_interrupt_reset(EWDG_Type *ptr, ewdg_interrupt_reset_config_t *config) +{ + hpm_stat_t status = status_invalid_argument; + + do { + if ((ptr == NULL) || (config == NULL)) { + break; + } + + uint32_t ctrl1 = 0; + if (config->enable_ctrl_parity_fail_reset) { + ctrl1 |= EWDG_RST_PARITY_FAIL; + } + if (config->enable_ctrl_unlock_fail_reset) { + ctrl1 |= EWDG_RST_CTRL_REG_UNLOCK_FAIL; + } + if (config->enable_refresh_unlock_fail_reset) { + ctrl1 |= EWDG_RST_REFRESH_UNLOCK_FAIL; + } + if (config->enable_ctrl_update_violation_reset) { + ctrl1 |= EWDG_RST_CTRL_REG_UPDATE_FAIL; + } + if (config->enable_timeout_reset) { + ctrl1 |= EWDG_RST_TIMEOUT; + } + if (config->enable_refresh_violation_reset) { + ctrl1 |= EWDG_RST_REFRESH_VIOLATION; + } + +#if defined(EWDG_SOC_SUPPORT_INTERRUPT) && (EWDG_SOC_SUPPORT_INTERRUPT == 0) + if (config->enable_timeout_interrupt) { + status = status_ewdg_feature_unsupported; + break; + } +#else + if (config->enable_timeout_interrupt) { + ctrl1 |= EWDG_INT_TIMEOUT; + } +#endif + if (config->enable_ctrl_parity_fail_interrupt) { + ctrl1 |= EWDG_INT_PARITY_FAIL; + } + if (config->enable_ctrl_unlock_fail_interrupt) { + ctrl1 |= EWDG_INT_CTRL_REG_UNLOCK_FAIL; + } + if (config->enable_refresh_unlock_fail_interrupt) { + ctrl1 |= EWDG_INT_REFRESH_UNLOCK_FAIL; + } + if (config->enable_ctrl_update_violation_interrupt) { + ctrl1 |= EWDG_INT_CTRL_REG_UPDATE_FAIL; + } + if (config->enable_refresh_violation_interrupt) { + ctrl1 |= EWDG_INT_REFRESH_VIOLATION; + } + + /* Set Parity bit if necessary */ + if (ewdg_need_set_parity_bit(ctrl1)) { + ctrl1 |= EWDG_CTRL_REG_PARITY_BIT_MASK; + } + + if (ewdg_is_ctrl_reg_locked(ptr)) { + ewdg_unlock_ctrl_regs(ptr); + } + ptr->CTRL1 = ctrl1; + + status = status_success; + + } while (false); + + return status; +} + +hpm_stat_t ewdg_init(EWDG_Type *ptr, ewdg_config_t *config) +{ + hpm_stat_t status = status_invalid_argument; + + do { + if ((ptr == NULL) || (config == NULL)) { + break; + } + + status = ewdg_init_ctrl_func(ptr, &config->ctrl_config, config->cnt_src_freq); + if (status != status_success) { + break; + } + status = ewdg_init_interrupt_reset(ptr, &config->int_rst_config); + if (status != status_success) { + break; + } + + if (ewdg_is_ctrl_reg_locked(ptr)) { + ewdg_unlock_ctrl_regs(ptr); + } + ptr->WDT_EN = (config->enable_watchdog) ? 1UL : 0UL; + + } while (false); + + return status; +} + +hpm_stat_t ewdg_unlock_refresh(EWDG_Type *ptr) +{ + hpm_stat_t status = status_invalid_argument; + + do { + if (ptr == NULL) { + break; + } + + if (!ewdg_is_refresh_locked(ptr)) { + status = status_success; + break; + } + + ewdg_refresh_unlock_method_t unlock_method = ewdg_get_refresh_unlock_method(ptr); + uint32_t unlock_password; + uint32_t reg_unlock_password = EWDG_REF_PROT_REF_UNL_PSD_GET(ptr->REF_PROT); + if (unlock_method == ewdg_refresh_unlock_method_password) { + unlock_password = reg_unlock_password; + } else if (unlock_method == ewdg_refresh_unlock_method_fixed_key) { + unlock_password = EWDG_REFRESH_UNLOCK_FIXED_KEY; + } else if (unlock_method == ewdg_refresh_unlock_method_ring_left_shift_password_by_1) { + unlock_password = EWDG_RING_LEFT_SHIFT_1(reg_unlock_password); + } else if (unlock_method == ewdg_refresh_unlock_method_ring_left_shift_password_by_1_bit0_xor_password_bit0) { + uint16_t high_15 = (reg_unlock_password << 1) & 0xFFFFU; + uint16_t low_0 = reg_unlock_password >> 15; + low_0 ^= reg_unlock_password; + unlock_password = high_15 | (low_0 & 0x1UL); + } else { + /* Should never reach this branch */ + break; + } + + ptr->REF_PROT = unlock_password; + + status = status_success; + + } while (false); + + return status; +} + +hpm_stat_t ewdg_refresh(EWDG_Type *ptr) +{ + hpm_stat_t status = ewdg_unlock_refresh(ptr); + if (status == status_success) { + ewdg_write_refresh_reg(ptr); + } + return status; +} + +uint32_t ewdg_get_count_clock_freq(EWDG_Type *ptr, uint32_t src_clk_freq) +{ + uint32_t divided_freq = 0; + if (ptr != NULL) { + uint32_t divider = ewdg_get_count_clk_divider(ptr); + divided_freq = src_clk_freq / divider; + } + return divided_freq; +} + +uint64_t ewdg_convert_timeout_us_to_timeout_ticks(uint32_t src_clk_freq, uint32_t timeout_us) +{ + uint64_t timeout_ticks = 0; + if (src_clk_freq != 0U) { + uint32_t ns_per_tick = 1000000000UL / src_clk_freq; + uint64_t timeout_ns = (uint64_t) timeout_us * 1000UL; + timeout_ticks = (timeout_ns + ns_per_tick - 1U) / ns_per_tick; + } + return timeout_ticks; +} + +uint32_t ewdg_convert_timeout_ticks_to_timeout_us(EWDG_Type *ptr, uint32_t src_clk_freq, uint32_t timeout_ticks) +{ + uint32_t timeout_us; + if (src_clk_freq == 0U) { + timeout_us = 0; + } else { + uint32_t actual_clk_freq = src_clk_freq / ewdg_get_count_clk_divider(ptr); + uint32_t ns_per_tick = 1000000000UL / actual_clk_freq; + uint64_t timeout_ns = (uint64_t) timeout_ticks * ns_per_tick; + timeout_us = timeout_ns / 1000UL; + } + return timeout_us; +} + +void ewdg_enable_interrupt(EWDG_Type *ptr, uint32_t mask) +{ + uint32_t interrupt_mask = mask & EWDG_INT_ALL; + if (ptr != NULL) { + uint32_t ctrl1 = ptr->CTRL1 | interrupt_mask; + /* Set Parity bit if necessary */ + if (ewdg_need_set_parity_bit(ctrl1)) { + ctrl1 |= EWDG_CTRL_REG_PARITY_BIT_MASK; + } + if (ewdg_is_ctrl_reg_locked(ptr)) { + ewdg_unlock_ctrl_regs(ptr); + } + ptr->CTRL1 = ctrl1; + } +} + +void ewdg_disable_interrupt(EWDG_Type *ptr, uint32_t mask) +{ + uint32_t interrupt_mask = mask & EWDG_INT_ALL; + if (ptr != NULL) { + uint32_t ctrl1 = ptr->CTRL1 & ~interrupt_mask; + /* Set Parity bit if necessary */ + if (ewdg_need_set_parity_bit(ctrl1)) { + ctrl1 |= EWDG_CTRL_REG_PARITY_BIT_MASK; + } + if (ewdg_is_ctrl_reg_locked(ptr)) { + ewdg_unlock_ctrl_regs(ptr); + } + ptr->CTRL1 = ctrl1; + } +} + +void ewdg_enable_reset(EWDG_Type *ptr, uint32_t mask) +{ + uint32_t reset_mask = mask & EWDG_RST_ALL; + if (ptr != NULL) { + uint32_t ctrl1 = ptr->CTRL1 | reset_mask; + /* Set Parity bit if necessary */ + if (ewdg_need_set_parity_bit(ctrl1)) { + ctrl1 |= EWDG_CTRL_REG_PARITY_BIT_MASK; + } + if (ewdg_is_ctrl_reg_locked(ptr)) { + ewdg_unlock_ctrl_regs(ptr); + } + ptr->CTRL1 = ctrl1; + } +} + +void ewdg_disable_reset(EWDG_Type *ptr, uint32_t mask) +{ + uint32_t reset_mask = mask & EWDG_RST_ALL; + if (ptr != NULL) { + uint32_t ctrl1 = ptr->CTRL1 & ~reset_mask; + /* Set Parity bit if necessary */ + if (ewdg_need_set_parity_bit(ctrl1)) { + ctrl1 |= EWDG_CTRL_REG_PARITY_BIT_MASK; + } + if (ewdg_is_ctrl_reg_locked(ptr)) { + ewdg_unlock_ctrl_regs(ptr); + } + ptr->CTRL1 = ctrl1; + } +} + +void ewdg_switch_clock_source(EWDG_Type *ptr, ewdg_cnt_clk_sel_t clk_sel) +{ + if (ptr != NULL) { + uint32_t ctrl0 = ptr->CTRL0 & ~EWDG_CTRL0_CLK_SEL_MASK; + /* Set Parity bit if necessary */ + if (clk_sel == ewdg_cnt_clk_src_ext_osc_clk) { + ctrl0 |= EWDG_CTRL0_CLK_SEL_MASK; + } + if (ewdg_need_set_parity_bit(ctrl0)) { + ctrl0 |= EWDG_CTRL_REG_PARITY_BIT_MASK; + } + if (ewdg_is_ctrl_reg_locked(ptr)) { + ewdg_unlock_ctrl_regs(ptr); + } + ptr->CTRL0 = ctrl0; + } +} + +void ewdg_enable(EWDG_Type *ptr) +{ + if (ewdg_is_ctrl_reg_locked(ptr)) { + ewdg_unlock_ctrl_regs(ptr); + } + ptr->WDT_EN = 1; +} + +void ewdg_disable(EWDG_Type *ptr) +{ + if (ewdg_is_ctrl_reg_locked(ptr)) { + ewdg_unlock_ctrl_regs(ptr); + } + ptr->WDT_EN = 0; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_femc_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_femc_drv.c index 888f39ee4d9..598968abf04 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_femc_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_femc_drv.c @@ -18,10 +18,10 @@ #define FEMC_PRESCALER_MAX (256UL) -static void femc_config_delay_cell(FEMC_Type *ptr, uint32_t delay_cell_value) +static void femc_config_delay_cell(FEMC_Type *ptr, bool delay_cell_en, uint32_t delay_cell_value) { ptr->DLYCFG &= ~FEMC_DLYCFG_OE_MASK; - ptr->DLYCFG = FEMC_DLYCFG_DLYSEL_SET(delay_cell_value) | FEMC_DLYCFG_DLYEN_MASK; + ptr->DLYCFG = FEMC_DLYCFG_DLYSEL_SET(delay_cell_value) | FEMC_DLYCFG_DLYEN_SET(delay_cell_en); ptr->DLYCFG |= FEMC_DLYCFG_OE_MASK; } @@ -68,7 +68,7 @@ uint32_t femc_issue_ip_cmd(FEMC_Type *ptr, uint32_t base_address, femc_cmd_t *cm } ptr->IPCMD = femc_make_cmd(cmd->opcode); - if (femc_ip_cmd_done(ptr) < 0) { + if (femc_ip_cmd_done(ptr) != status_success) { return status_femc_cmd_err; } @@ -80,6 +80,7 @@ uint32_t femc_issue_ip_cmd(FEMC_Type *ptr, uint32_t base_address, femc_cmd_t *cm void femc_default_config(FEMC_Type *ptr, femc_config_t *config) { + (void) ptr; femc_axi_q_weight_t *q; config->dqs = FEMC_DQS_FROM_PAD; config->cmd_timeout = 0; @@ -102,6 +103,7 @@ void femc_default_config(FEMC_Type *ptr, femc_config_t *config) void femc_get_typical_sdram_config(FEMC_Type *ptr, femc_sdram_config_t *config) { + (void) ptr; config->col_addr_bits = FEMC_SDRAM_COLUMN_ADDR_9_BITS; config->cas_latency = FEMC_SDRAM_CAS_LATENCY_3; config->bank_num = FEMC_SDRAM_BANK_NUM_4; @@ -199,11 +201,17 @@ static uint8_t femc_convert_burst_len(uint8_t burst_len_in_byte) } } -static uint32_t ns2cycle(uint32_t freq_in_hz, uint32_t ns) +static uint32_t ns2cycle(uint32_t freq_in_hz, uint32_t ns, uint32_t max_cycle) { uint32_t ns_per_cycle; + uint32_t cycle; + ns_per_cycle = 1000000000 / freq_in_hz; - return (ns / ns_per_cycle); + cycle = ns / ns_per_cycle; + if (cycle > max_cycle) { + cycle = max_cycle; + } + return cycle; } hpm_stat_t femc_config_sdram(FEMC_Type *ptr, uint32_t clk_in_hz, femc_sdram_config_t *config) @@ -242,17 +250,17 @@ hpm_stat_t femc_config_sdram(FEMC_Type *ptr, uint32_t clk_in_hz, femc_sdram_conf | FEMC_SDRCTRL0_CAS_SET(config->cas_latency) | FEMC_SDRCTRL0_BANK2_SET(config->bank_num); - ptr->SDRCTRL1 = FEMC_SDRCTRL1_PRE2ACT_SET(ns2cycle(clk_in_hz, config->precharge_to_act_in_ns)) - | FEMC_SDRCTRL1_ACT2RW_SET(ns2cycle(clk_in_hz, config->act_to_rw_in_ns)) - | FEMC_SDRCTRL1_RFRC_SET(ns2cycle(clk_in_hz, config->refresh_recover_in_ns)) - | FEMC_SDRCTRL1_WRC_SET(ns2cycle(clk_in_hz, config->write_recover_in_ns)) - | FEMC_SDRCTRL1_CKEOFF_SET(ns2cycle(clk_in_hz, config->cke_off_in_ns)) - | FEMC_SDRCTRL1_ACT2PRE_SET(ns2cycle(clk_in_hz, config->act_to_precharge_in_ns)); + ptr->SDRCTRL1 = FEMC_SDRCTRL1_PRE2ACT_SET(ns2cycle(clk_in_hz, config->precharge_to_act_in_ns, FEMC_SDRCTRL1_PRE2ACT_MASK >> FEMC_SDRCTRL1_PRE2ACT_SHIFT)) + | FEMC_SDRCTRL1_ACT2RW_SET(ns2cycle(clk_in_hz, config->act_to_rw_in_ns, FEMC_SDRCTRL1_ACT2RW_MASK >> FEMC_SDRCTRL1_ACT2RW_SHIFT)) + | FEMC_SDRCTRL1_RFRC_SET(ns2cycle(clk_in_hz, config->refresh_recover_in_ns, FEMC_SDRCTRL1_RFRC_MASK >> FEMC_SDRCTRL1_RFRC_SHIFT)) + | FEMC_SDRCTRL1_WRC_SET(ns2cycle(clk_in_hz, config->write_recover_in_ns, FEMC_SDRCTRL1_WRC_MASK >> FEMC_SDRCTRL1_WRC_SHIFT)) + | FEMC_SDRCTRL1_CKEOFF_SET(ns2cycle(clk_in_hz, config->cke_off_in_ns, FEMC_SDRCTRL1_CKEOFF_MASK >> FEMC_SDRCTRL1_CKEOFF_SHIFT)) + | FEMC_SDRCTRL1_ACT2PRE_SET(ns2cycle(clk_in_hz, config->act_to_precharge_in_ns, FEMC_SDRCTRL1_ACT2PRE_MASK >> FEMC_SDRCTRL1_ACT2PRE_SHIFT)); - ptr->SDRCTRL2 = FEMC_SDRCTRL2_SRRC_SET(ns2cycle(clk_in_hz, config->self_refresh_recover_in_ns)) - | FEMC_SDRCTRL2_REF2REF_SET(ns2cycle(clk_in_hz, config->refresh_to_refresh_in_ns)) - | FEMC_SDRCTRL2_ACT2ACT_SET(ns2cycle(clk_in_hz, config->act_to_act_in_ns)) - | FEMC_SDRCTRL2_ITO_SET(ns2cycle(clk_in_hz, config->idle_timeout_in_ns)); + ptr->SDRCTRL2 = FEMC_SDRCTRL2_SRRC_SET(ns2cycle(clk_in_hz, config->self_refresh_recover_in_ns, FEMC_SDRCTRL2_SRRC_MASK >> FEMC_SDRCTRL2_SRRC_SHIFT)) + | FEMC_SDRCTRL2_REF2REF_SET(ns2cycle(clk_in_hz, config->refresh_to_refresh_in_ns, FEMC_SDRCTRL2_REF2REF_MASK >> FEMC_SDRCTRL2_REF2REF_SHIFT)) + | FEMC_SDRCTRL2_ACT2ACT_SET(ns2cycle(clk_in_hz, config->act_to_act_in_ns, FEMC_SDRCTRL2_ACT2ACT_MASK >> FEMC_SDRCTRL2_ACT2ACT_SHIFT)) + | FEMC_SDRCTRL2_ITO_SET(ns2cycle(clk_in_hz, config->idle_timeout_in_ns, FEMC_SDRCTRL2_ITO_MASK >> FEMC_SDRCTRL2_ITO_SHIFT)); ptr->SDRCTRL3 = FEMC_SDRCTRL3_PRESCALE_SET(prescaler) | FEMC_SDRCTRL3_RT_SET(refresh_cycle) @@ -302,7 +310,7 @@ hpm_stat_t femc_config_sdram(FEMC_Type *ptr, uint32_t clk_in_hz, femc_sdram_conf /* * config delay cell */ - femc_config_delay_cell(ptr, config->delay_cell_value); + femc_config_delay_cell(ptr, !config->delay_cell_disable, config->delay_cell_value); cmd.opcode = FEMC_CMD_SDRAM_PRECHARGE_ALL; cmd.data = 0; @@ -335,6 +343,7 @@ hpm_stat_t femc_config_sdram(FEMC_Type *ptr, uint32_t clk_in_hz, femc_sdram_conf void femc_get_typical_sram_config(FEMC_Type *ptr, femc_sram_config_t *config) { + (void) ptr; config->base_address = 0x48000000; config->size_in_byte = 4096; config->address_mode = FEMC_SRAM_AD_NONMUX_MODE; @@ -366,14 +375,14 @@ hpm_stat_t femc_config_sram(FEMC_Type *ptr, uint32_t clk_in_hz, femc_sram_config | FEMC_SRCTRL0_ADM_SET(config->address_mode) | FEMC_SRCTRL0_PORTSZ_SET(config->port_size); - ptr->SRCTRL1 = FEMC_SRCTRL1_OEH_SET(ns2cycle(clk_in_hz, config->oeh_in_ns)) - | FEMC_SRCTRL1_OEL_SET(ns2cycle(clk_in_hz, config->oel_in_ns)) - | FEMC_SRCTRL1_WEH_SET(ns2cycle(clk_in_hz, config->weh_in_ns)) - | FEMC_SRCTRL1_WEL_SET(ns2cycle(clk_in_hz, config->wel_in_ns)) - | FEMC_SRCTRL1_AH_SET(ns2cycle(clk_in_hz, config->ah_in_ns)) - | FEMC_SRCTRL1_AS_SET(ns2cycle(clk_in_hz, config->as_in_ns)) - | FEMC_SRCTRL1_CEH_SET(ns2cycle(clk_in_hz, config->ceh_in_ns)) - | FEMC_SRCTRL1_CES_SET(ns2cycle(clk_in_hz, config->ces_in_ns)); + ptr->SRCTRL1 = FEMC_SRCTRL1_OEH_SET(ns2cycle(clk_in_hz, config->oeh_in_ns, FEMC_SRCTRL1_OEH_MASK >> FEMC_SRCTRL1_OEH_SHIFT)) + | FEMC_SRCTRL1_OEL_SET(ns2cycle(clk_in_hz, config->oel_in_ns, FEMC_SRCTRL1_OEL_MASK >> FEMC_SRCTRL1_OEL_SHIFT)) + | FEMC_SRCTRL1_WEH_SET(ns2cycle(clk_in_hz, config->weh_in_ns, FEMC_SRCTRL1_WEH_MASK >> FEMC_SRCTRL1_WEH_SHIFT)) + | FEMC_SRCTRL1_WEL_SET(ns2cycle(clk_in_hz, config->wel_in_ns, FEMC_SRCTRL1_WEL_MASK >> FEMC_SRCTRL1_WEL_SHIFT)) + | FEMC_SRCTRL1_AH_SET(ns2cycle(clk_in_hz, config->ah_in_ns, FEMC_SRCTRL1_AH_MASK >> FEMC_SRCTRL1_AH_SHIFT)) + | FEMC_SRCTRL1_AS_SET(ns2cycle(clk_in_hz, config->as_in_ns, FEMC_SRCTRL1_AS_MASK >> FEMC_SRCTRL1_AS_SHIFT)) + | FEMC_SRCTRL1_CEH_SET(ns2cycle(clk_in_hz, config->ceh_in_ns, FEMC_SRCTRL1_CEH_MASK >> FEMC_SRCTRL1_CEH_SHIFT)) + | FEMC_SRCTRL1_CES_SET(ns2cycle(clk_in_hz, config->ces_in_ns, FEMC_SRCTRL1_CES_MASK >> FEMC_SRCTRL1_CES_SHIFT)); return status_success; } diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gpio_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gpio_drv.c index 521a86d20f3..0247e280b14 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gpio_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gpio_drv.c @@ -43,6 +43,9 @@ void gpio_config_pin_interrupt(GPIO_Type *ptr, uint32_t gpio_index, uint8_t pin_ break; case gpio_interrupt_trigger_edge_falling: case gpio_interrupt_trigger_edge_rising: +#if defined(GPIO_SOC_HAS_EDGE_BOTH_INTERRUPT) && (GPIO_SOC_HAS_EDGE_BOTH_INTERRUPT == 1) + ptr->PD[gpio_index].CLEAR = 1 << pin_index; +#endif ptr->TP[gpio_index].SET = 1 << pin_index; if (trigger == gpio_interrupt_trigger_edge_rising) { ptr->PL[gpio_index].CLEAR = 1 << pin_index; @@ -50,6 +53,12 @@ void gpio_config_pin_interrupt(GPIO_Type *ptr, uint32_t gpio_index, uint8_t pin_ ptr->PL[gpio_index].SET = 1 << pin_index; } break; +#if defined(GPIO_SOC_HAS_EDGE_BOTH_INTERRUPT) && (GPIO_SOC_HAS_EDGE_BOTH_INTERRUPT == 1) + case gpio_interrupt_trigger_edge_both: + ptr->TP[gpio_index].SET = 1 << pin_index; + ptr->PD[gpio_index].SET = 1 << pin_index; + break; +#endif default: return; } diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gptmr_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gptmr_drv.c index d24205d03a5..13c46fedaed 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gptmr_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gptmr_drv.c @@ -9,6 +9,7 @@ void gptmr_channel_get_default_config(GPTMR_Type *ptr, gptmr_channel_config_t *config) { + (void) ptr; config->mode = gptmr_work_mode_no_capture; config->dma_request_event = gptmr_dma_request_disabled; config->synci_edge = gptmr_synci_edge_none; diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gwc_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gwc_drv.c new file mode 100644 index 00000000000..cde3d8b3383 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gwc_drv.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_gwc_drv.h" + +void gwc_get_default_config(gwc_config_t *cfg) +{ + cfg->clk_pol = gwc_clk_pol_normal; +} + +void gwc_init(GWC_Type *ptr, gwc_config_t *cfg) +{ + ptr->GLB_CTRL = cfg->clk_pol; +} + +void gwc_enable(GWC_Type *ptr) +{ + ptr->GLB_CTRL |= GWC_GLB_CTRL_GWC_EN_MASK; +} + +void gwc_disable(GWC_Type *ptr) +{ + ptr->GLB_CTRL &= ~GWC_GLB_CTRL_GWC_EN_MASK; +} + +void gwc_freeze_interrupt_control(GWC_Type *ptr) +{ + ptr->IRQ_MASK |= GWC_IRQ_MASK_MASK_RREEZ_MASK; +} + +void gwc_ch_init(GWC_Type *ptr, uint8_t ch_index, gwc_ch_config_t *cfg) +{ + assert(ch_index <= GWC_CHANNEL_CH15); + ptr->CHANNEL[ch_index].CFG0 = GWC_CHANNEL_CFG0_START_ROW_SET(cfg->start_row) | + GWC_CHANNEL_CFG0_START_COL_SET(cfg->start_col) | + (cfg->freeze ? GWC_CHANNEL_CFG0_FREEZE_MASK : 0); + ptr->CHANNEL[ch_index].CFG1 = GWC_CHANNEL_CFG1_END_ROW_SET(cfg->end_row) | + GWC_CHANNEL_CFG1_END_COL_SET(cfg->end_col); + ptr->CHANNEL[ch_index].REFCRC = cfg->ref_crc; +} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2c_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2c_drv.c index 66370dcd644..1b77e721b2f 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2c_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2c_drv.c @@ -165,9 +165,10 @@ hpm_stat_t i2c_master_address_read(I2C_Type *ptr, const uint16_t device_address, hpm_stat_t stat = status_success; uint32_t left; uint32_t retry; - - assert(addr_size_in_byte > 0 && addr_size_in_byte <= I2C_SOC_TRANSFER_COUNT_MAX); - assert(size_in_byte > 0 && size_in_byte <= I2C_SOC_TRANSFER_COUNT_MAX); + if (((addr_size_in_byte == 0) || (addr_size_in_byte > I2C_SOC_TRANSFER_COUNT_MAX)) || + ((size_in_byte == 0) || (size_in_byte > I2C_SOC_TRANSFER_COUNT_MAX))) { + return status_invalid_argument; + } retry = 0; while (ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { @@ -188,6 +189,7 @@ hpm_stat_t i2c_master_address_read(I2C_Type *ptr, const uint16_t device_address, | I2C_CTRL_PHASE_ADDR_MASK | I2C_CTRL_PHASE_DATA_MASK | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_WRITE) + | I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(addr_size_in_byte) >> 8U) | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(addr_size_in_byte)); ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); @@ -199,6 +201,23 @@ hpm_stat_t i2c_master_address_read(I2C_Type *ptr, const uint16_t device_address, } ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; + /* Before starting to transmit data, judge addrhit to ensure that the slave address exists on the bus. */ + retry = 0; + while (!(ptr->STATUS & I2C_STATUS_ADDRHIT_MASK)) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + /* the address misses, a stop needs to be added to prevent the bus from being busy. */ + ptr->STATUS = I2C_STATUS_CMPL_MASK; + ptr->CTRL = I2C_CTRL_PHASE_STOP_MASK; + ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; + return status_i2c_no_addr_hit; + } + ptr->STATUS = I2C_STATUS_ADDRHIT_MASK; + retry = 0; while (!(ptr->STATUS & I2C_STATUS_CMPL_MASK)) { if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { @@ -218,6 +237,7 @@ hpm_stat_t i2c_master_address_read(I2C_Type *ptr, const uint16_t device_address, | I2C_CTRL_PHASE_ADDR_MASK | I2C_CTRL_PHASE_DATA_MASK | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_READ) + | I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(addr_size_in_byte) >> 8U) | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size_in_byte)); ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; @@ -261,9 +281,11 @@ hpm_stat_t i2c_master_address_write(I2C_Type *ptr, const uint16_t device_address uint32_t left; uint32_t retry; - assert(addr_size_in_byte > 0 && addr_size_in_byte <= I2C_SOC_TRANSFER_COUNT_MAX); - assert(size_in_byte > 0 && size_in_byte <= I2C_SOC_TRANSFER_COUNT_MAX); - assert(addr_size_in_byte + size_in_byte <= I2C_SOC_TRANSFER_COUNT_MAX); + if (((addr_size_in_byte == 0) || (addr_size_in_byte > I2C_SOC_TRANSFER_COUNT_MAX)) || + ((size_in_byte == 0) || (size_in_byte > I2C_SOC_TRANSFER_COUNT_MAX)) || + ((addr_size_in_byte + size_in_byte) > I2C_SOC_TRANSFER_COUNT_MAX)) { + return status_invalid_argument; + } retry = 0; while (ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { @@ -286,6 +308,7 @@ hpm_stat_t i2c_master_address_write(I2C_Type *ptr, const uint16_t device_address | I2C_CTRL_PHASE_ADDR_MASK | I2C_CTRL_PHASE_DATA_MASK | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_WRITE) + | I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(size_in_byte + addr_size_in_byte) >> 8U) | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size_in_byte + addr_size_in_byte)); left = addr_size_in_byte; @@ -295,6 +318,19 @@ hpm_stat_t i2c_master_address_write(I2C_Type *ptr, const uint16_t device_address } ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; + /* Before starting to transmit data, judge addrhit to ensure that the slave address exists on the bus. */ + retry = 0; + while (!(ptr->STATUS & I2C_STATUS_ADDRHIT_MASK)) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_i2c_no_addr_hit; + } + ptr->STATUS = I2C_STATUS_ADDRHIT_MASK; + retry = 0; left = size_in_byte; while (left) { @@ -335,8 +371,9 @@ hpm_stat_t i2c_master_read(I2C_Type *ptr, const uint16_t device_address, hpm_stat_t stat = status_success; uint32_t left; uint32_t retry; - - assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + if (size > I2C_SOC_TRANSFER_COUNT_MAX) { + return status_invalid_argument; + } retry = 0; while (ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { @@ -357,11 +394,31 @@ hpm_stat_t i2c_master_read(I2C_Type *ptr, const uint16_t device_address, ptr->CTRL = I2C_CTRL_PHASE_START_MASK | I2C_CTRL_PHASE_STOP_MASK | I2C_CTRL_PHASE_ADDR_MASK - | I2C_CTRL_PHASE_DATA_MASK - | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_READ) - | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); + | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_READ); + if (size > 0) { + ptr->CTRL |= I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(size) >> 8U) + | I2C_CTRL_PHASE_DATA_MASK + | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); + } ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; + /* Before starting to transmit data, judge addrhit to ensure that the slave address exists on the bus. */ + retry = 0; + while (!(ptr->STATUS & I2C_STATUS_ADDRHIT_MASK)) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_i2c_no_addr_hit; + } + ptr->STATUS = I2C_STATUS_ADDRHIT_MASK; + /* when size is zero, it's probe slave device, so directly return success */ + if (size == 0) { + return status_success; + } + retry = 0; left = size; while (left) { @@ -391,12 +448,7 @@ hpm_stat_t i2c_master_read(I2C_Type *ptr, const uint16_t device_address, return status_timeout; } - if (!(ptr->STATUS & I2C_STATUS_ADDRHIT_MASK)) { - /* I2C slave did not receive this transaction correctly. */ - return status_fail; - } - - if (i2c_get_data_count(ptr)) { + if (i2c_get_data_count(ptr) && (size)) { return status_i2c_transmit_not_completed; } @@ -410,7 +462,9 @@ hpm_stat_t i2c_master_write(I2C_Type *ptr, const uint16_t device_address, uint32_t retry; uint32_t left; - assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + if (size > I2C_SOC_TRANSFER_COUNT_MAX) { + return status_invalid_argument; + } retry = 0; while (ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { @@ -431,9 +485,30 @@ hpm_stat_t i2c_master_write(I2C_Type *ptr, const uint16_t device_address, ptr->CTRL = I2C_CTRL_PHASE_START_MASK | I2C_CTRL_PHASE_STOP_MASK | I2C_CTRL_PHASE_ADDR_MASK - | I2C_CTRL_PHASE_DATA_MASK - | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_WRITE) - | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); + | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_WRITE); + if (size > 0) { + ptr->CTRL |= I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(size) >> 8U) + | I2C_CTRL_PHASE_DATA_MASK + | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); + } + ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; + + /* Before starting to transmit data, judge addrhit to ensure that the slave address exists on the bus. */ + retry = 0; + while (!(ptr->STATUS & I2C_STATUS_ADDRHIT_MASK)) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_i2c_no_addr_hit; + } + ptr->STATUS = I2C_STATUS_ADDRHIT_MASK; + /* when size is zero, it's probe slave device, so directly return success */ + if (size == 0) { + return status_success; + } retry = 0; left = size; @@ -441,7 +516,6 @@ hpm_stat_t i2c_master_write(I2C_Type *ptr, const uint16_t device_address, if (!(ptr->STATUS & I2C_STATUS_FIFOFULL_MASK)) { ptr->DATA = *(buf++); left--; - ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; retry = 0; } else { if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { @@ -465,7 +539,7 @@ hpm_stat_t i2c_master_write(I2C_Type *ptr, const uint16_t device_address, return status_timeout; } - if (i2c_get_data_count(ptr)) { + if (i2c_get_data_count(ptr) && (size)) { return status_i2c_transmit_not_completed; } @@ -506,7 +580,9 @@ hpm_stat_t i2c_slave_write(I2C_Type *ptr, uint8_t *buf, const uint32_t size) uint32_t retry; uint32_t left; - assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + if (((size == 0) || (size > I2C_SOC_TRANSFER_COUNT_MAX))) { + return status_invalid_argument; + } /* wait for address hit */ retry = 0; @@ -571,7 +647,9 @@ hpm_stat_t i2c_slave_read(I2C_Type *ptr, uint32_t retry; uint32_t left; - assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + if (((size == 0) || (size > I2C_SOC_TRANSFER_COUNT_MAX))) { + return status_invalid_argument; + } /* wait for address hit */ retry = 0; @@ -631,7 +709,9 @@ hpm_stat_t i2c_slave_read(I2C_Type *ptr, hpm_stat_t i2c_master_start_dma_write(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size) { uint32_t retry = 0; - assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + if (((size == 0) || (size > I2C_SOC_TRANSFER_COUNT_MAX))) { + return status_invalid_argument; + } while (i2c_ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { @@ -652,6 +732,7 @@ hpm_stat_t i2c_master_start_dma_write(I2C_Type *i2c_ptr, const uint16_t device_a | I2C_CTRL_PHASE_ADDR_MASK | I2C_CTRL_PHASE_DATA_MASK | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_WRITE) + | I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(size) >> 8U) | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); i2c_ptr->SETUP |= I2C_SETUP_DMAEN_MASK; @@ -664,7 +745,9 @@ hpm_stat_t i2c_master_start_dma_write(I2C_Type *i2c_ptr, const uint16_t device_a hpm_stat_t i2c_master_start_dma_read(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size) { uint32_t retry = 0; - assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + if (((size == 0) || (size > I2C_SOC_TRANSFER_COUNT_MAX))) { + return status_invalid_argument; + } while (i2c_ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { @@ -684,6 +767,7 @@ hpm_stat_t i2c_master_start_dma_read(I2C_Type *i2c_ptr, const uint16_t device_ad | I2C_CTRL_PHASE_ADDR_MASK | I2C_CTRL_PHASE_DATA_MASK | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_READ) + | I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(size) >> 8U) | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); i2c_ptr->SETUP |= I2C_SETUP_DMAEN_MASK; @@ -695,12 +779,15 @@ hpm_stat_t i2c_master_start_dma_read(I2C_Type *i2c_ptr, const uint16_t device_ad hpm_stat_t i2c_slave_dma_transfer(I2C_Type *i2c_ptr, uint32_t size) { - assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + if (((size == 0) || (size > I2C_SOC_TRANSFER_COUNT_MAX))) { + return status_invalid_argument; + } /* W1C, clear CMPL bit to avoid blocking the transmission */ i2c_ptr->STATUS = I2C_STATUS_CMPL_MASK; - i2c_ptr->CTRL |= I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); + i2c_ptr->CTRL &= ~(I2C_CTRL_DATACNT_HIGH_MASK | I2C_CTRL_DATACNT_MASK); + i2c_ptr->CTRL |= I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(size) >> 8U) | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); i2c_ptr->SETUP |= I2C_SETUP_DMAEN_MASK; @@ -710,7 +797,9 @@ hpm_stat_t i2c_slave_dma_transfer(I2C_Type *i2c_ptr, uint32_t size) hpm_stat_t i2c_master_configure_transfer(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size, bool read) { uint32_t retry = 0; - assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + if (((size == 0) || (size > I2C_SOC_TRANSFER_COUNT_MAX))) { + return status_invalid_argument; + } while (i2c_ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { @@ -730,6 +819,7 @@ hpm_stat_t i2c_master_configure_transfer(I2C_Type *i2c_ptr, const uint16_t devic | I2C_CTRL_PHASE_ADDR_MASK | I2C_CTRL_PHASE_DATA_MASK | I2C_CTRL_DIR_SET(read) + | I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(size) >> 8U) | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); i2c_ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; @@ -744,7 +834,9 @@ hpm_stat_t i2c_master_seq_transmit(I2C_Type *ptr, const uint16_t device_address, uint32_t retry = 0; uint32_t left = 0; - assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + if (((size == 0) || (size > I2C_SOC_TRANSFER_COUNT_MAX))) { + return status_invalid_argument; + } /* W1C, clear CMPL bit to avoid blocking the transmission */ ptr->STATUS = I2C_STATUS_CMPL_MASK; @@ -770,9 +862,11 @@ hpm_stat_t i2c_master_seq_transmit(I2C_Type *ptr, const uint16_t device_address, ptr->CTRL = ctrl | I2C_CTRL_PHASE_DATA_SET(true) \ | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_WRITE) \ + | I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(size) >> 8U) \ | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); /* enable auto ack */ ptr->INTEN &= ~I2C_EVENT_BYTE_RECEIVED; + ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; retry = 0; left = size; @@ -780,7 +874,6 @@ hpm_stat_t i2c_master_seq_transmit(I2C_Type *ptr, const uint16_t device_address, if (!(ptr->STATUS & I2C_STATUS_FIFOFULL_MASK)) { ptr->DATA = *(buf++); left--; - ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; retry = 0; } else { if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { @@ -818,7 +911,9 @@ hpm_stat_t i2c_master_seq_receive(I2C_Type *ptr, const uint16_t device_address, uint32_t retry = 0; uint32_t left = 0; - assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + if (((size == 0) || (size > I2C_SOC_TRANSFER_COUNT_MAX))) { + return status_invalid_argument; + } /* W1C, clear CMPL bit to avoid blocking the transmission */ ptr->STATUS = I2C_STATUS_CMPL_MASK; @@ -844,6 +939,7 @@ hpm_stat_t i2c_master_seq_receive(I2C_Type *ptr, const uint16_t device_address, ptr->CTRL = ctrl | I2C_CTRL_PHASE_DATA_SET(true) \ | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_READ) \ + | I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(size) >> 8U) \ | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); /* disable auto ack */ @@ -896,3 +992,106 @@ hpm_stat_t i2c_master_seq_receive(I2C_Type *ptr, const uint16_t device_address, return status_success; } +hpm_stat_t i2c_master_transfer(I2C_Type *ptr, const uint16_t device_address, + uint8_t *buf, const uint32_t size, uint16_t flags) +{ + uint32_t ctrl = 0; + uint32_t retry = 0; + uint32_t left = 0; + if (((size == 0) || (size > I2C_SOC_TRANSFER_COUNT_MAX))) { + return status_invalid_argument; + } + if (flags & I2C_ADDR_10BIT) { + i2c_enable_10bit_address_mode(ptr, true); + } else { + i2c_enable_10bit_address_mode(ptr, false); + } + /* W1C, clear CMPL bit to avoid blocking the transmission */ + ptr->STATUS = I2C_STATUS_CMPL_MASK; + ptr->CMD = I2C_CMD_CLEAR_FIFO; + ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); + + if (flags & I2C_RD) { + ctrl |= I2C_CTRL_DIR_SET(I2C_DIR_MASTER_READ); + } else { + ctrl |= I2C_CTRL_DIR_SET(I2C_DIR_MASTER_WRITE);/* is write flag */ + } + /* start signal */ + if (flags & I2C_NO_START) { + ctrl |= I2C_CTRL_PHASE_START_SET(false); + } else { + ctrl |= I2C_CTRL_PHASE_START_SET(true); + } + /* end signal*/ + if (flags & I2C_NO_STOP) { + ctrl |= I2C_CTRL_PHASE_STOP_SET(false); + } else { + ctrl |= I2C_CTRL_PHASE_STOP_SET(true); + } + + ptr->CTRL = ctrl | I2C_CTRL_PHASE_DATA_SET(true) \ + | I2C_CTRL_PHASE_ADDR_SET(true) \ + | I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(size) >> 8U) \ + | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); + /* disable auto ack */ + ptr->INTEN |= I2C_EVENT_BYTE_RECEIVED; + ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; + retry = 0; + left = size; + if (flags & I2C_RD) { + while (left) { + if (!(ptr->STATUS & I2C_STATUS_FIFOEMPTY_MASK)) { + *(buf++) = ptr->DATA; + left--; + if (left == 0) { + ptr->CMD = I2C_CMD_NACK; + } else { + /* ACK is sent when reading */ + if (!(flags & I2C_NO_READ_ACK)) { + ptr->CMD = I2C_CMD_ACK; + } + } + retry = 0; + } else { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + } else { + while (left) { + if (!(ptr->STATUS & I2C_STATUS_FIFOFULL_MASK)) { + ptr->DATA = *(buf++); + left--; + retry = 0; + } else { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + } + retry = 0; + while (!(ptr->STATUS & I2C_STATUS_CMPL_MASK)) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + + if (i2c_get_data_count(ptr) && (size)) { + return status_i2c_transmit_not_completed; + } + return status_success; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2s_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2s_drv.c index 3dfe9054c52..73e93c179df 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2s_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2s_drv.c @@ -13,6 +13,9 @@ #define HPM_I2S_BCLK_TOLERANCE (4U) #endif +#define HPM_I2S_SLOT_MASK I2S_TXDSLOT_EN_MASK /* TX/RX has same SLOT MASK */ + + static bool i2s_audio_depth_is_valid(uint8_t bits) { /* i2s audio depth only support 16bits, 24bits, 32bits */ @@ -31,31 +34,54 @@ static bool i2s_channel_length_is_valid(uint8_t bits) return false; } +/* work around: fill dummy data into TX fifo to avoid TX underflow during tx start */ +hpm_stat_t i2s_fill_tx_dummy_data(I2S_Type *ptr, uint8_t data_line, uint8_t data_count) +{ + uint32_t retry = 0; + + if (data_count > I2S_SOC_MAX_TX_FIFO_DEPTH) { + return status_invalid_argument; + } + + /* check dummy data count in TX FIFO */ + while (i2s_get_tx_line_fifo_level(ptr, data_line) < data_count) { + ptr->TXD[data_line] = 0; + if (retry > HPM_I2S_DRV_DEFAULT_RETRY_COUNT * data_count) { + return status_timeout; + } + retry++; + } + + return status_success; +} + +/* The I2S software reset function relies on a working BCLK */ void i2s_reset_all(I2S_Type *ptr) { - /* gate off bclk */ - ptr->CFGR |= I2S_CFGR_BCLK_GATEOFF_MASK; - /* gate off mclk */ - ptr->MISC_CFGR |= I2S_MISC_CFGR_MCLK_GATEOFF_MASK; - /* - * clear fifos - */ - ptr->CTRL |= I2S_CTRL_TXFIFOCLR_MASK | I2S_CTRL_RXFIFOCLR_MASK; - ptr->CTRL &= ~(I2S_CTRL_TXFIFOCLR_MASK | I2S_CTRL_RXFIFOCLR_MASK); - - /* - * software reset all blocks - */ - ptr->CTRL |= I2S_CTRL_SFTRST_CLKGEN_MASK | I2S_CTRL_SFTRST_TX_MASK | I2S_CTRL_SFTRST_RX_MASK; - ptr->CTRL &= ~(I2S_CTRL_SFTRST_CLKGEN_MASK | I2S_CTRL_SFTRST_TX_MASK | I2S_CTRL_SFTRST_RX_MASK); - /* - * disable i2s - */ + uint32_t cfgr_temp, misc_cfgr_temp; + + /* disable I2S */ ptr->CTRL &= ~I2S_CTRL_I2S_EN_MASK; + + /* enable internal clock for software reset function */ + cfgr_temp = ptr->CFGR; + ptr->CFGR |= I2S_CFGR_BCLK_DIV_SET(1); + ptr->CFGR &= ~(I2S_CFGR_MCK_SEL_OP_MASK | I2S_CFGR_BCLK_SEL_OP_MASK | I2S_CFGR_FCLK_SEL_OP_MASK | I2S_CFGR_BCLK_GATEOFF_MASK); + misc_cfgr_temp = ptr->MISC_CFGR; + ptr->MISC_CFGR &= ~I2S_MISC_CFGR_MCLK_GATEOFF_MASK; + + /* reset function block and clear fifo */ + ptr->CTRL |= (I2S_CTRL_TXFIFOCLR_MASK | I2S_CTRL_RXFIFOCLR_MASK | I2S_CTRL_SFTRST_CLKGEN_MASK | I2S_CTRL_SFTRST_TX_MASK | I2S_CTRL_SFTRST_RX_MASK); + ptr->CTRL &= ~(I2S_CTRL_TXFIFOCLR_MASK | I2S_CTRL_RXFIFOCLR_MASK | I2S_CTRL_SFTRST_CLKGEN_MASK | I2S_CTRL_SFTRST_TX_MASK | I2S_CTRL_SFTRST_RX_MASK); + + /* Restore the value of the register */ + ptr->CFGR = cfgr_temp; + ptr->MISC_CFGR = misc_cfgr_temp; } void i2s_get_default_config(I2S_Type *ptr, i2s_config_t *config) { + (void) ptr; config->invert_mclk_out = false; config->invert_mclk_in = false; config->use_external_mclk = false; @@ -67,7 +93,8 @@ void i2s_get_default_config(I2S_Type *ptr, i2s_config_t *config) config->use_external_fclk = false; config->enable_mclk_out = false; config->frame_start_at_rising_edge = false; - config->fifo_threshold = 4; + config->tx_fifo_threshold = 4; + config->rx_fifo_threshold = 4; } void i2s_init(I2S_Type *ptr, i2s_config_t *config) @@ -88,18 +115,8 @@ void i2s_init(I2S_Type *ptr, i2s_config_t *config) & ~(I2S_MISC_CFGR_MCLKOE_MASK | I2S_MISC_CFGR_MCLK_GATEOFF_MASK)) | I2S_MISC_CFGR_MCLKOE_SET(config->enable_mclk_out); - ptr->FIFO_THRESH = I2S_FIFO_THRESH_TX_SET(config->fifo_threshold) - | I2S_FIFO_THRESH_RX_SET(config->fifo_threshold); - /** - * @brief i2s interrupt work_around - * - */ - for (uint32_t i = 0; i <= I2S_DATA_LINE_MAX; i++) { - ptr->TXDSLOT[i] = 0; - for (uint32_t j = 0; j <= I2S_SOC_MAX_TX_CHANNEL_NUM; j++) { - ptr->TXD[i] = 0x01; - } - } + ptr->FIFO_THRESH = I2S_FIFO_THRESH_TX_SET(config->tx_fifo_threshold) + | I2S_FIFO_THRESH_RX_SET(config->rx_fifo_threshold); } static void i2s_config_cfgr(I2S_Type *ptr, @@ -159,22 +176,26 @@ static bool i2s_calculate_bclk_divider(uint32_t mclk_in_hz, uint32_t bclk_in_hz, static hpm_stat_t _i2s_config_tx(I2S_Type *ptr, i2s_transfer_config_t *config) { /* channel_num_per_frame has to even. non TDM mode, it has be 2 */ + uint8_t channel_num_per_frame = HPM_NUM_TO_EVEN_CEILING(config->channel_num_per_frame); if (!i2s_audio_depth_is_valid(config->audio_depth) || !i2s_channel_length_is_valid(config->channel_length) || !config->sample_rate - || !config->channel_num_per_frame - || (config->channel_num_per_frame > I2S_SOC_MAX_CHANNEL_NUM) - || (config->channel_num_per_frame & 1U) - || ((!config->enable_tdm_mode) && (config->channel_num_per_frame > 2))) { + || !channel_num_per_frame + || (channel_num_per_frame > I2S_SOC_MAX_CHANNEL_NUM) + || ((!config->enable_tdm_mode) && (channel_num_per_frame > 2)) + || ((config->channel_slot_mask & HPM_I2S_SLOT_MASK) == 0)) { return status_invalid_argument; } - if (config->channel_slot_mask) { - ptr->TXDSLOT[config->data_line] = config->channel_slot_mask; + ptr->TXDSLOT[config->data_line] = config->channel_slot_mask; + + /* work around: fill dummy data into TX fifo to avoid TX underflow during tx start */ + if (i2s_fill_tx_dummy_data(ptr, config->data_line, config->channel_num_per_frame) != status_success) { + return status_invalid_argument; } + ptr->CTRL = (ptr->CTRL & ~(I2S_CTRL_TX_EN_MASK)) - | I2S_CTRL_TX_EN_SET(1 << config->data_line) - | I2S_CTRL_I2S_EN_MASK; + | I2S_CTRL_TX_EN_SET(1 << config->data_line); return status_success; } @@ -182,22 +203,20 @@ static hpm_stat_t _i2s_config_tx(I2S_Type *ptr, i2s_transfer_config_t *config) static hpm_stat_t _i2s_config_rx(I2S_Type *ptr, i2s_transfer_config_t *config) { /* channel_num_per_frame has to even. non TDM mode, it has be 2 */ + uint8_t channel_num_per_frame = HPM_NUM_TO_EVEN_CEILING(config->channel_num_per_frame); if (!i2s_audio_depth_is_valid(config->audio_depth) || !i2s_channel_length_is_valid(config->channel_length) || !config->sample_rate - || !config->channel_num_per_frame - || (config->channel_num_per_frame > I2S_SOC_MAX_CHANNEL_NUM) - || (config->channel_num_per_frame & 1U) - || ((!config->enable_tdm_mode) && (config->channel_num_per_frame > 2))) { + || !channel_num_per_frame + || (channel_num_per_frame > I2S_SOC_MAX_CHANNEL_NUM) + || ((!config->enable_tdm_mode) && (channel_num_per_frame > 2)) + || ((config->channel_slot_mask & HPM_I2S_SLOT_MASK) == 0)) { return status_invalid_argument; } - if (config->channel_slot_mask) { - ptr->RXDSLOT[config->data_line] = config->channel_slot_mask; - } + ptr->RXDSLOT[config->data_line] = config->channel_slot_mask; ptr->CTRL = (ptr->CTRL & ~(I2S_CTRL_RX_EN_MASK)) - | I2S_CTRL_RX_EN_SET(1 << config->data_line) - | I2S_CTRL_I2S_EN_MASK; + | I2S_CTRL_RX_EN_SET(1 << config->data_line); return status_success; } @@ -205,31 +224,29 @@ static hpm_stat_t _i2s_config_rx(I2S_Type *ptr, i2s_transfer_config_t *config) static hpm_stat_t _i2s_config_transfer(I2S_Type *ptr, i2s_transfer_config_t *config) { /* channel_num_per_frame has to even. non TDM mode, it has be 2 */ + uint8_t channel_num_per_frame = HPM_NUM_TO_EVEN_CEILING(config->channel_num_per_frame); if (!i2s_audio_depth_is_valid(config->audio_depth) || !i2s_channel_length_is_valid(config->channel_length) || !config->sample_rate - || !config->channel_num_per_frame - || (config->channel_num_per_frame > I2S_SOC_MAX_CHANNEL_NUM) - || (config->channel_num_per_frame & 1U) - || ((!config->enable_tdm_mode) && (config->channel_num_per_frame > 2))) { + || !channel_num_per_frame + || (channel_num_per_frame > I2S_SOC_MAX_CHANNEL_NUM) + || ((!config->enable_tdm_mode) && (channel_num_per_frame > 2)) + || ((config->channel_slot_mask & HPM_I2S_SLOT_MASK) == 0)) { return status_invalid_argument; } - if (config->channel_slot_mask) { - /* Suppose RX and TX use same channel */ - ptr->RXDSLOT[config->data_line] = config->channel_slot_mask; - ptr->TXDSLOT[config->data_line] = config->channel_slot_mask; - } else { - /** - * @brief i2s interrupt work_around - * - */ - ptr->TXDSLOT[config->data_line] = 0x0000ffff; + /* Suppose RX and TX use same channel */ + ptr->RXDSLOT[config->data_line] = config->channel_slot_mask; + ptr->TXDSLOT[config->data_line] = config->channel_slot_mask; + + /* work around: fill dummy data into TX fifo to avoid TX underflow during tx start */ + if (i2s_fill_tx_dummy_data(ptr, config->data_line, config->channel_num_per_frame) != status_success) { + return status_invalid_argument; } + ptr->CTRL = (ptr->CTRL & ~(I2S_CTRL_RX_EN_MASK | I2S_CTRL_TX_EN_MASK)) | I2S_CTRL_RX_EN_SET(1 << config->data_line) - | I2S_CTRL_TX_EN_SET(1 << config->data_line) - | I2S_CTRL_I2S_EN_MASK; + | I2S_CTRL_TX_EN_SET(1 << config->data_line); return status_success; } @@ -238,8 +255,9 @@ hpm_stat_t i2s_config_tx(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config { uint32_t bclk_in_hz; uint32_t bclk_div; + uint8_t channel_num_per_frame = HPM_NUM_TO_EVEN_CEILING(config->channel_num_per_frame); - bclk_in_hz = config->sample_rate * config->channel_length * config->channel_num_per_frame; + bclk_in_hz = config->sample_rate * config->channel_length * channel_num_per_frame; if (!i2s_calculate_bclk_divider(mclk_in_hz, bclk_in_hz, &bclk_div)) { return status_invalid_argument; } @@ -263,7 +281,8 @@ hpm_stat_t i2s_config_rx(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config uint32_t bclk_in_hz; uint32_t bclk_div; - bclk_in_hz = config->sample_rate * config->channel_length * config->channel_num_per_frame; + uint8_t channel_num_per_frame = HPM_NUM_TO_EVEN_CEILING(config->channel_num_per_frame); + bclk_in_hz = config->sample_rate * config->channel_length * channel_num_per_frame; if (!i2s_calculate_bclk_divider(mclk_in_hz, bclk_in_hz, &bclk_div)) { return status_invalid_argument; } @@ -287,7 +306,8 @@ hpm_stat_t i2s_config_transfer(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_ uint32_t bclk_in_hz; uint32_t bclk_div; - bclk_in_hz = config->sample_rate * config->channel_length * config->channel_num_per_frame; + uint8_t channel_num_per_frame = HPM_NUM_TO_EVEN_CEILING(config->channel_num_per_frame); + bclk_in_hz = config->sample_rate * config->channel_length * channel_num_per_frame; if (!i2s_calculate_bclk_divider(mclk_in_hz, bclk_in_hz, &bclk_div)) { return status_invalid_argument; } @@ -399,7 +419,7 @@ void i2s_get_default_transfer_config_for_dao(i2s_transfer_config_t *transfer) transfer->enable_tdm_mode = false; transfer->protocol = I2S_PROTOCOL_MSB_JUSTIFIED; transfer->data_line = I2S_DATA_LINE_0; - transfer->channel_slot_mask = 0xFFFF; + transfer->channel_slot_mask = 0x3; } void i2s_get_default_transfer_config(i2s_transfer_config_t *transfer) @@ -411,5 +431,5 @@ void i2s_get_default_transfer_config(i2s_transfer_config_t *transfer) transfer->enable_tdm_mode = false; transfer->protocol = I2S_PROTOCOL_MSB_JUSTIFIED; transfer->data_line = I2S_DATA_LINE_0; - transfer->channel_slot_mask = 0xFFFF; + transfer->channel_slot_mask = 0x3; } diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_jpeg_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_jpeg_drv.c index c52ee65e8d2..90cf0df7924 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_jpeg_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_jpeg_drv.c @@ -66,8 +66,8 @@ void jpeg_reset(JPEG_Type *ptr) void jpeg_init(JPEG_Type *ptr) { - jpeg_clear_cfg(ptr); jpeg_reset(ptr); + jpeg_clear_cfg(ptr); } static bool jpeg_need_csc(jpeg_pixel_format_t in, jpeg_pixel_format_t out) @@ -107,6 +107,7 @@ static void jpeg_config_interal_regs(JPEG_Type *ptr, uint32_t macro_block_count, uint8_t format) { + (void) decoding; uint8_t hy, vy, hc, vc; hy = JPEG_HY(&jpeg_supported_sampling[format]); vy = JPEG_VY(&jpeg_supported_sampling[format]); @@ -274,7 +275,7 @@ hpm_stat_t jpeg_start_decode(JPEG_Type *ptr, | JPEG_OUTDMA_MISC_PACK_DIR_SET(config->out_byte_order); ptr->OUTDMABASE = JPEG_OUTDMABASE_ADDR_SET(config->out_buffer); ptr->OUTDMA_CTRL0 = JPEG_OUTDMA_CTRL0_TTLEN_SET(total_bytes) - | JPEG_OUTDMA_CTRL0_PITCH_SET(config->width_in_pixel * jpeg_supported_pixel_format[config->in_pixel_format].pixel_width); + | JPEG_OUTDMA_CTRL0_PITCH_SET(config->width_in_pixel * jpeg_supported_pixel_format[config->out_pixel_format].pixel_width); ptr->OUTDMA_CTRL1 = JPEG_OUTDMA_CTRL1_ROWLEN_SET(total_bytes >> 16); ptr->ONXT_CMD = JPEG_ONXT_CMD_ADDR_SET(5) | JPEG_ONXT_CMD_OP_VALID_MASK; @@ -301,7 +302,7 @@ hpm_stat_t jpeg_start_decode(JPEG_Type *ptr, #define JPEG_TABLE_WIDTH(x) (((x) & 0xF00000UL) >> 20) #define JPEG_TABLE_LENGTH(x) (((x) & 0xFFFF0UL) >> 4) #define JPEG_TABLE_TYPE(x) (((x) & 0xFUL)) -#define JPEG_TABLE_VALUE_MASK(x) (((x) == 4) ? (0xFFFFFFFFUL) : ((1 << ((x) << 3)) - 1)) +#define JPEG_TABLE_VALUE_MASK(x) (((x) == 4) ? (0xFFFFFFFFUL) : (uint32_t) ((1 << ((x) << 3)) - 1)) hpm_stat_t jpeg_fill_table(JPEG_Type *ptr, jpeg_table_t table, uint8_t *data, uint32_t count) { diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lcb_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lcb_drv.c new file mode 100644 index 00000000000..5f4f4b3be64 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lcb_drv.c @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_lcb_drv.h" + +void lcb_get_default_config(lcb_config_t *cfg) +{ + cfg->mode = lcb_mode_display; + cfg->rxclk_sel = lcb_rxclk_sel_phy0; + cfg->display.data_width = lcb_display_mode_data_width_24bit; + cfg->display.map = lcb_display_mode_mapping_vesa; +} + +void lcb_init(LCB_Type *ptr, lcb_config_t *cfg) +{ + uint32_t reg_val; + + if (cfg->mode == lcb_mode_display) + reg_val = (ptr->CTRL & ~(LCB_CTRL_LVDS_RXCK_SEL_MASK | + LCB_CTRL_MODE_MASK | + LCB_CTRL_DATA_WIDTH_MASK | + LCB_CTRL_BIT_MAPPING_MASK)) | + LCB_CTRL_MODE_SET(cfg->mode) | + LCB_CTRL_LVDS_RXCK_SEL_SET(cfg->rxclk_sel) | + LCB_CTRL_DATA_WIDTH_SET(cfg->display.data_width) | + LCB_CTRL_BIT_MAPPING_SET(cfg->display.map); + else + reg_val = (ptr->CTRL & ~(LCB_CTRL_LVDS_RXCK_SEL_MASK | + LCB_CTRL_MODE_MASK | + LCB_CTRL_CAM_LINK_WIDTH_MASK)) | + LCB_CTRL_MODE_SET(cfg->mode) | + LCB_CTRL_LVDS_RXCK_SEL_SET(cfg->rxclk_sel) | + LCB_CTRL_CAM_LINK_WIDTH_SET(cfg->cam_link.data_width); + + ptr->CTRL = reg_val; +} + +void lcb_get_phy_clk_lane_default_config(lcb_lvds_phy_clk_lane_config_t *cfg) +{ + cfg->rterm = lcb_lvds_phy_rterm_100_ohm; + cfg->min_adj = lcb_lvds_phy_dll_delay_adj_min_freq_70_110mhz; + cfg->dll_tuning_int = 0x1FFU; +} + +void lcb_get_phy_data_lane_default_config(lcb_lvds_phy_data_lane_config_t *cfg) +{ + cfg->rterm = lcb_lvds_phy_rterm_100_ohm; + cfg->dline_adj = 0x41; +} + +void lcb_lvds_phy0_data_lane_config(LCB_Type *ptr, lcb_lvds_phy_data_lane_config_t *cfg, lcb_lvds_phy_data_lane_id_t lane_id) +{ + ptr->PHY_D_CTRL[lane_id] = (ptr->PHY_D_CTRL[lane_id] & ~(LCB_PHY_D_CTRL_RX_RTERM_MASK)) | + LCB_PHY_D_CTRL_RX_RTERM_SET(cfg->rterm); + + if (lane_id == lcb_lvds_phy_data_lane_id_0) + ptr->PHY_ADJ_CTRL[0] = (ptr->PHY_ADJ_CTRL[0] & ~(LCB_PHY_ADJ_CTRL_LVDS_RX0_DLINE_ADJ_MASK)) | + LCB_PHY_ADJ_CTRL_LVDS_RX0_DLINE_ADJ_SET(cfg->dline_adj); + else if (lane_id == lcb_lvds_phy_data_lane_id_1) + ptr->PHY_ADJ_CTRL[0] = (ptr->PHY_ADJ_CTRL[0] & ~(LCB_PHY_ADJ_CTRL_LVDS_RX1_DLINE_ADJ_MASK)) | + LCB_PHY_ADJ_CTRL_LVDS_RX1_DLINE_ADJ_SET(cfg->dline_adj); +} + +void lcb_lvds_phy0_clk_lane_config(LCB_Type *ptr, lcb_lvds_phy_clk_lane_config_t *cfg) +{ + ptr->PHY_CK_CTRL[0] = (ptr->PHY_CK_CTRL[0] & ~(LCB_PHY_CK_CTRL_RX_RTERM_MASK | 0x0001)) | + LCB_PHY_CK_CTRL_RX_RTERM_SET(cfg->rterm) | + (uint32_t)cfg->min_adj; + + ptr->PHY_ADJ_CTRL[0] = (ptr->PHY_ADJ_CTRL[0] & ~(LCB_PHY_ADJ_CTRL_LVDS_DLL_TUNING_INT_MASK)) | + LCB_PHY_ADJ_CTRL_LVDS_DLL_TUNING_INT_SET(cfg->dll_tuning_int); +} + +void lcb_lvds_phy1_data_lane_config(LCB_Type *ptr, lcb_lvds_phy_data_lane_config_t *cfg, lcb_lvds_phy_data_lane_id_t lane_id) +{ + ptr->PHY_D_CTRL[lane_id + 2] = (ptr->PHY_D_CTRL[lane_id + 2] & ~(LCB_PHY_D_CTRL_RX_RTERM_MASK)) | + LCB_PHY_D_CTRL_RX_RTERM_SET(cfg->rterm); + + if (lane_id == lcb_lvds_phy_data_lane_id_0) + ptr->PHY_ADJ_CTRL[1] = (ptr->PHY_ADJ_CTRL[1] & ~(LCB_PHY_ADJ_CTRL_LVDS_RX0_DLINE_ADJ_MASK)) | + LCB_PHY_ADJ_CTRL_LVDS_RX0_DLINE_ADJ_SET(cfg->dline_adj); + else if (lane_id == lcb_lvds_phy_data_lane_id_1) + ptr->PHY_ADJ_CTRL[1] = (ptr->PHY_ADJ_CTRL[1] & ~(LCB_PHY_ADJ_CTRL_LVDS_RX1_DLINE_ADJ_MASK)) | + LCB_PHY_ADJ_CTRL_LVDS_RX1_DLINE_ADJ_SET(cfg->dline_adj); +} + +void lcb_lvds_phy1_clk_lane_config(LCB_Type *ptr, lcb_lvds_phy_clk_lane_config_t *cfg) +{ + ptr->PHY_CK_CTRL[1] = (ptr->PHY_CK_CTRL[1] & ~(LCB_PHY_CK_CTRL_RX_RTERM_MASK | 0x0001)) | + LCB_PHY_CK_CTRL_RX_RTERM_SET(cfg->rterm) | + (uint32_t)cfg->min_adj; + + ptr->PHY_ADJ_CTRL[1] = (ptr->PHY_ADJ_CTRL[1] & ~(LCB_PHY_ADJ_CTRL_LVDS_DLL_TUNING_INT_MASK)) | + LCB_PHY_ADJ_CTRL_LVDS_DLL_TUNING_INT_SET(cfg->dll_tuning_int); +} + +void lcb_lvds_phy0_poweron(LCB_Type *ptr) +{ + ptr->PHY_POW_CTRL[0] &= ~(LCB_PHY_POW_CTRL_IDDQ_EN_MASK | + LCB_PHY_POW_CTRL_RXCK_PD_MASK | + LCB_PHY_POW_CTRL_RX1_PD_MASK | + LCB_PHY_POW_CTRL_RX0_PD_MASK); +} + +void lcb_lvds_phy1_poweron(LCB_Type *ptr) +{ + ptr->PHY_POW_CTRL[1] &= ~(LCB_PHY_POW_CTRL_IDDQ_EN_MASK | + LCB_PHY_POW_CTRL_RXCK_PD_MASK | + LCB_PHY_POW_CTRL_RX1_PD_MASK | + LCB_PHY_POW_CTRL_RX0_PD_MASK); +} + +void lcb_lvds_phy0_powerdown(LCB_Type *ptr) +{ + ptr->PHY_POW_CTRL[0] |= (LCB_PHY_POW_CTRL_IDDQ_EN_MASK | + LCB_PHY_POW_CTRL_RXCK_PD_MASK | + LCB_PHY_POW_CTRL_RX1_PD_MASK | + LCB_PHY_POW_CTRL_RX0_PD_MASK); +} + +void lcb_lvds_phy1_powerdown(LCB_Type *ptr) +{ + ptr->PHY_POW_CTRL[1] |= (LCB_PHY_POW_CTRL_IDDQ_EN_MASK | + LCB_PHY_POW_CTRL_RXCK_PD_MASK | + LCB_PHY_POW_CTRL_RX1_PD_MASK | + LCB_PHY_POW_CTRL_RX0_PD_MASK); +} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lcdc_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lcdc_drv.c index 1b15b00a99b..6ce29f861a2 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lcdc_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lcdc_drv.c @@ -50,6 +50,7 @@ static uint8_t lcdc_byteorder(display_byteorder_t byteorder) void lcdc_get_default_layer_config(LCDC_Type *ptr, lcdc_layer_config_t *layer, display_pixel_format_t pixel_format, uint8_t layer_index) { + (void) ptr; layer->max_bytes = lcdc_layer_max_bytes_64; /* different layer has different max_ot configuration */ if (layer_index < LCDC_SOC_MAX_CSC_LAYER_COUNT) { @@ -70,6 +71,7 @@ void lcdc_get_default_layer_config(LCDC_Type *ptr, lcdc_layer_config_t *layer, d layer->alphablend.src_alpha_op = display_alpha_op_invalid; layer->alphablend.dst_alpha_op = display_alpha_op_invalid; layer->alphablend.mode = display_alphablend_mode_clear; + layer->stride = 0; switch (pixel_format) { case display_pixel_format_yuv422: @@ -110,6 +112,7 @@ void lcdc_get_default_layer_config(LCDC_Type *ptr, lcdc_layer_config_t *layer, d void lcdc_get_default_config(LCDC_Type *ptr, lcdc_config_t *config) { + (void) ptr; config->resolution_x = 480; config->resolution_y = 272; config->hsync.front_porch_pulse = 40; @@ -212,7 +215,7 @@ hpm_stat_t lcdc_config_layer(LCDC_Type *ptr, ptr->LAYER[layer_index].ALPHAS = LCDC_LAYER_ALPHAS_LOCD_SET(layer->alphablend.src_alpha) | LCDC_LAYER_ALPHAS_IND_SET(layer->alphablend.dst_alpha); - pitch = display_get_pitch_length_in_byte(layer->pixel_format, layer->width); + pitch = layer->stride > 0 ? layer->stride : display_get_pitch_length_in_byte(layer->pixel_format, layer->width); ptr->LAYER[layer_index].LINECFG = LCDC_LAYER_LINECFG_MPT_SIZE_SET(layer->max_bytes) | LCDC_LAYER_LINECFG_MAX_OT_SET(layer->max_ot) | LCDC_LAYER_LINECFG_PITCH_SET(pitch); diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_linv2_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_linv2_drv.c new file mode 100644 index 00000000000..0129cd4ec6f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_linv2_drv.c @@ -0,0 +1,373 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_linv2_drv.h" + +#define HPM_LIN_DRV_RETRY_COUNT (50000U) + +hpm_stat_t lin_master_configure_timing(LINV2_Type *ptr, lin_timing_t *timing) +{ + assert(timing->src_freq_in_hz >= 8000000U); + assert((timing->baudrate >= 1000U) && (timing->baudrate <= 20000U)); + + uint8_t prescaler, bt_mul; + uint16_t bt_div; + + /** set master mode */ + ptr->TIMING_CONTROL = LINV2_TIMING_CONTROL_MASTER_MODE_MASK; + ptr->TIMING_CONTROL |= LINV2_TIMING_CONTROL_LIN_INITIAL_MASK; + ptr->TIMING_CONTROL &= ~LINV2_TIMING_CONTROL_LIN_INITIAL_MASK; + + bt_mul = 20000U / timing->baudrate - 1U; + prescaler = (uint8_t)(log((timing->src_freq_in_hz / ((bt_mul + 1U) * timing->baudrate * 200U))) / log(2U) - 1U); + bt_div = timing->src_freq_in_hz / ((1U << (prescaler + 1U)) * (bt_mul + 1U) * timing->baudrate); + + if ((bt_div < 200) || (bt_div > 512)) { + return status_invalid_argument; + } + + /** src =20MHz baudrate = 19.2KHz */ + /** bt_div = 260, scaler = 1, bt_mul = 0 */ + ptr->TIMING_CONTROL |= LINV2_TIMING_CONTROL_BT_DIV_SET(bt_div) + | LINV2_TIMING_CONTROL_BT_MUL_SET(bt_mul) + | LINV2_TIMING_CONTROL_PRESCL_SET(prescaler); + + return status_success; +} + +hpm_stat_t lin_slave_configure_timing(LINV2_Type *ptr, uint32_t src_freq_in_hz) +{ + assert(src_freq_in_hz >= 8000000U); + + uint8_t prescaler; + uint16_t bt_div; + + /** set slave mode, clean bt_div, bit_mul, prescl */ + ptr->TIMING_CONTROL = 0; + ptr->TIMING_CONTROL |= LINV2_TIMING_CONTROL_LIN_INITIAL_MASK; + ptr->TIMING_CONTROL &= ~LINV2_TIMING_CONTROL_LIN_INITIAL_MASK; + + prescaler = (uint8_t)(log((src_freq_in_hz / (20000U * 200U))) / log(2U) - 1U); + bt_div = src_freq_in_hz / ((1U << (prescaler + 1U)) * 20000U); + + if ((bt_div < 200) || (bt_div >= 512)) { + return status_invalid_argument; + } + + /** src = 20MHz, prescaler = 1, bt_div = 250 */ + /* TODO： set wakeup_len */ + ptr->TIMING_CONTROL = LINV2_TIMING_CONTROL_BT_DIV_SET(bt_div) + | LINV2_TIMING_CONTROL_PRESCL_SET(prescaler); + + /* disable break_err detect */ + ptr->CONTROL_STATUS = LINV2_CONTROL_STATUS_BREAK_ERR_DIS_MASK; + + return status_success; +} + +uint8_t lin_get_data_length_from_id(uint8_t id) +{ + switch (LIN_ID_DATA_LEN_GET(id)) { + case id_data_length_2bytes: + return 2; + case id_data_length_2bytes_2: + return 2; + case id_data_length_4bytes: + return 4; + case id_data_length_8bytes: + return 8; + default: + return 8; + } +} + +uint8_t lin_get_data_length(LINV2_Type *ptr) +{ + uint8_t data_length = 0; + if (((ptr->DATA_LEN_ID) & LINV2_DATA_LEN_ID_DATA_LEN_MASK) == LINV2_DATA_LEN_ID_DATA_LEN_MASK) { + data_length = lin_get_data_length_from_id(lin_get_id(ptr)); + } else { + data_length = LINV2_DATA_LEN_ID_DATA_LEN_GET(ptr->DATA_LEN_ID); + } + return data_length; +} + +void lin_master_transfer(LINV2_Type *ptr, lin_trans_config_t *config) +{ + uint8_t data_length; + + /** config id */ + if (config->data_length_from_id) { + data_length = lin_get_data_length_from_id(lin_get_id(ptr)); + ptr->DATA_LEN_ID = LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_MASK | LINV2_DATA_LEN_ID_ID_SET(config->id); + } else { + data_length = config->data_length; + ptr->DATA_LEN_ID = LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_SET(data_length) | LINV2_DATA_LEN_ID_ID_SET(config->id); + } + + /** sent or receive */ + ptr->CONTROL_STATUS = 0U; + if (config->transmit) { + ptr->CONTROL_STATUS |= LINV2_CONTROL_STATUS_TRANSMIT_MASK; + } + + if (config->transmit) { + for (uint8_t i = 0; i < data_length; i++) { + ptr->DATA_BYTE[i] = *((config->data_buff)++); + } + } + + /** start */ + ptr->CONTROL_STATUS |= LINV2_CONTROL_STATUS_START_REQ_MASK; +} + +hpm_stat_t lin_master_sent(LINV2_Type *ptr, lin_trans_config_t *config) +{ + uint32_t retry = 0; + uint8_t data_length = 0; + + /** wait for lin inactive */ + while (lin_is_active(ptr)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + return status_timeout; + } + + /** config id */ + if (config->data_length_from_id) { + data_length = lin_get_data_length_from_id(lin_get_id(ptr)); + ptr->DATA_LEN_ID = LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_MASK | LINV2_DATA_LEN_ID_ID_SET(config->id); + } else { + data_length = config->data_length; + ptr->DATA_LEN_ID = LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_SET(data_length) | LINV2_DATA_LEN_ID_ID_SET(config->id); + } + + ptr->CONTROL_STATUS = LINV2_CONTROL_STATUS_TRANSMIT_MASK; + + /** load data into registers */ + for (uint8_t i = 0; i < data_length; i++) { + ptr->DATA_BYTE[i] = *((config->data_buff)++); + } + + /** start */ + ptr->CONTROL_STATUS |= LINV2_CONTROL_STATUS_START_REQ_MASK; + + /** waiting for lin complete */ + retry = 0; + while (!lin_is_complete(ptr)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { + return status_timeout; + } + return status_success; +} + +hpm_stat_t lin_master_receive(LINV2_Type *ptr, lin_trans_config_t *config) +{ + uint32_t retry = 0; + uint8_t data_length; + + /** waiting for lin inactive */ + while (lin_is_active(ptr)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + return status_timeout; + } + + /** config id */ + if (config->data_length_from_id) { + data_length = lin_get_data_length_from_id(lin_get_id(ptr)); + ptr->DATA_LEN_ID = LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_MASK | LINV2_DATA_LEN_ID_ID_SET(config->id); + } else { + data_length = config->data_length; + ptr->DATA_LEN_ID = LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_SET(data_length) | LINV2_DATA_LEN_ID_ID_SET(config->id); + } + + /** receive */ + ptr->CONTROL_STATUS = 0U; + /** start */ + ptr->CONTROL_STATUS |= LINV2_CONTROL_STATUS_START_REQ_MASK; + + /** waiting for receive complete */ + retry = 0; + while (!lin_is_complete(ptr)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { + return status_fail; + } + + /** load register data into buffer */ + for (uint8_t i = 0; i < data_length; i++) { + *((config->data_buff)++) = ptr->DATA_BYTE[i]; + } + + return status_success; +} + +void lin_slave_transfer(LINV2_Type *ptr, lin_trans_config_t *config) +{ + uint8_t data_length; + + /** transmit or receive */ + ptr->CONTROL_STATUS &= ~LINV2_CONTROL_STATUS_TRANSMIT_MASK; + if (config->transmit) { + ptr->CONTROL_STATUS |= LINV2_CONTROL_STATUS_TRANSMIT_MASK; + } + + /* clean enh_check and data_len */ + ptr->DATA_LEN_ID &= ~(LINV2_DATA_LEN_ID_ENH_CHECK_MASK | LINV2_DATA_LEN_ID_DATA_LEN_MASK); + if (config->data_length_from_id) { + data_length = lin_get_data_length_from_id(lin_get_id(ptr)); + ptr->DATA_LEN_ID |= LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_MASK; + } else { + data_length = config->data_length; + ptr->DATA_LEN_ID |= LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_SET(data_length); + } + + if (config->transmit) { + for (uint8_t i = 0; i < data_length; i++) { + ptr->DATA_BYTE[i] = *((config->data_buff)++); + } + } + + /** data ack */ + ptr->CONTROL_STATUS |= LINV2_CONTROL_STATUS_DATA_ACK_MASK; +} + +hpm_stat_t lin_slave_sent(LINV2_Type *ptr, lin_trans_config_t *config) +{ + uint32_t retry = 0; + uint8_t data_length; + + /** waiting for lin data_req */ + while (!((ptr->CONTROL_STATUS & LINV2_CONTROL_STATUS_DATA_REQ_MASK) == LINV2_CONTROL_STATUS_DATA_REQ_MASK)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + return status_timeout; + } + + /** transmit */ + ptr->CONTROL_STATUS = LINV2_CONTROL_STATUS_TRANSMIT_MASK; + + /* clean enh_check and data_len */ + ptr->DATA_LEN_ID &= ~(LINV2_DATA_LEN_ID_ENH_CHECK_MASK | LINV2_DATA_LEN_ID_DATA_LEN_MASK); + if (config->data_length_from_id) { + data_length = lin_get_data_length_from_id(lin_get_id(ptr)); + ptr->DATA_LEN_ID |= LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_MASK; + } else { + data_length = config->data_length; + ptr->DATA_LEN_ID |= LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_SET(data_length); + } + + for (uint8_t i = 0; i < data_length; i++) { + ptr->DATA_BYTE[i] = *((config->data_buff)++); + } + + /** data ack */ + ptr->CONTROL_STATUS |= LINV2_CONTROL_STATUS_DATA_ACK_MASK; + + /** waiting for lin complete */ + retry = 0; + while (!lin_is_complete(ptr)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { + return status_timeout; + } + return status_success; +} + +hpm_stat_t lin_slave_receive(LINV2_Type *ptr, lin_trans_config_t *config) +{ + uint32_t retry = 0; + uint8_t data_length; + + /** waiting for lin data_req */ + while (!((ptr->CONTROL_STATUS & LINV2_CONTROL_STATUS_DATA_REQ_MASK) == LINV2_CONTROL_STATUS_DATA_REQ_MASK)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + return status_timeout; + } + + /** receive */ + ptr->CONTROL_STATUS = 0U; + + /* clean enh_check and data_len */ + ptr->DATA_LEN_ID &= ~(LINV2_DATA_LEN_ID_ENH_CHECK_MASK | LINV2_DATA_LEN_ID_DATA_LEN_MASK); + if (config->data_length_from_id) { + data_length = lin_get_data_length_from_id(lin_get_id(ptr)); + ptr->DATA_LEN_ID |= LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_MASK; + } else { + data_length = config->data_length; + ptr->DATA_LEN_ID |= LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_SET(data_length); + } + + /** data ack */ + ptr->CONTROL_STATUS |= LINV2_CONTROL_STATUS_DATA_ACK_MASK; + + /** waiting for lin complete */ + retry = 0; + while (!lin_is_complete(ptr)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { + return status_timeout; + } + + for (uint8_t i = 0; i < data_length; i++) { + *((config->data_buff)++) = ptr->DATA_BYTE[i]; + } + + return status_success; +} + +void lin_slave_dma_transfer(LINV2_Type *ptr, lin_trans_config_t *config) +{ + ptr->DMA_CONTROL = LINV2_DMA_CONTROL_DMA_REQ_ENABLE_MASK + | LINV2_DMA_CONTROL_DMA_REQ_ID_SET(config->id) + | LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_SET(config->transmit) + | LINV2_DMA_CONTROL_DMA_REQ_LEN_SET(config->data_length) + | LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_SET(config->enhanced_checksum); +} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lvb_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lvb_drv.c new file mode 100644 index 00000000000..4cd59fa20a0 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lvb_drv.c @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_lvb_drv.h" + +void lvb_get_default_config(lvb_config_t *cfg) +{ + cfg->split_ch_is_reverse = false; + cfg->split_ch_data_is_unaligned = false; + cfg->split_hswhbp_width_is_even = true; + cfg->split_mode_en = false; + cfg->di0_vsync_polarity = lvb_di_vsync_polarity_active_high; + cfg->di1_vsync_polarity = lvb_di_vsync_polarity_active_high; + cfg->txclk_shift = lvb_txclk_shift_1100011; +} + +void lvb_init(LVB_Type *ptr, lvb_config_t *cfg) +{ + ptr->CTRL = (ptr->CTRL & ~(LVB_CTRL_SPLIT_CH_REVERSE_MASK | + LVB_CTRL_SPLIT_CH_MODE_MASK | + LVB_CTRL_SPLIT_HSWHBP_WIDTH_MASK | + LVB_CTRL_SPLIT_MODE_EN_MASK | + LVB_CTRL_DI1_VSYNC_POLARITY_MASK | + LVB_CTRL_DI0_VSYNC_POLARITY_MASK | + LVB_CTRL_LVDS_TXCLK_SHIFT_MASK)) | + LVB_CTRL_SPLIT_CH_REVERSE_SET(cfg->split_ch_is_reverse) | + LVB_CTRL_SPLIT_CH_MODE_SET(cfg->split_ch_data_is_unaligned) | + LVB_CTRL_SPLIT_HSWHBP_WIDTH_SET(cfg->split_hswhbp_width_is_even) | + LVB_CTRL_SPLIT_MODE_EN_SET(cfg->split_mode_en) | + LVB_CTRL_DI1_VSYNC_POLARITY_SET(cfg->di1_vsync_polarity) | + LVB_CTRL_DI0_VSYNC_POLARITY_SET(cfg->di0_vsync_polarity) | + LVB_CTRL_LVDS_TXCLK_SHIFT_SET(cfg->txclk_shift); +} + +void lvb_get_ch_default_config(lvb_ch_config_t *ch_cfg) +{ + ch_cfg->data_src = lvb_ch_data_source_di0; + ch_cfg->map = lvb_ch_mapping_vesa; +} + +void lvb_ch_config(LVB_Type *ptr, lvb_ch_num_t ch_num, lvb_ch_config_t *ch_cfg) +{ + uint32_t reg_val; + + if (ch_num == lvb_ch_num_0) { + reg_val = (ptr->CTRL & ~(LVB_CTRL_CH0_BIT_MAPPING_MASK | LVB_CTRL_CH0_SEL_MASK)) | + LVB_CTRL_CH0_BIT_MAPPING_SET(ch_cfg->map) | + LVB_CTRL_CH0_SEL_SET(ch_cfg->data_src); + } else { + reg_val = (ptr->CTRL & ~(LVB_CTRL_CH1_BIT_MAPPING_MASK | LVB_CTRL_CH1_SEL_MASK)) | + LVB_CTRL_CH1_BIT_MAPPING_SET(ch_cfg->map) | + LVB_CTRL_CH1_SEL_SET(ch_cfg->data_src); + } + + ptr->CTRL = reg_val; +} + +void lvb_ch_enable(LVB_Type *ptr, lvb_ch_num_t ch_num) +{ + if (ch_num == lvb_ch_num_0) { + ptr->CTRL |= LVB_CTRL_CH0_EN_MASK; + } else { + ptr->CTRL |= LVB_CTRL_CH1_EN_MASK; + } +} + +void lvb_ch_disable(LVB_Type *ptr, lvb_ch_num_t ch_num) +{ + if (ch_num == lvb_ch_num_0) { + ptr->CTRL &= ~LVB_CTRL_CH0_EN_MASK; + } else { + ptr->CTRL &= ~LVB_CTRL_CH1_EN_MASK; + } +} + +void lvb_lvds_phy_lane_get_default_config(lvb_lvds_phy_lane_config_t *cfg) +{ + cfg->tx_idle = false; + cfg->rterm_enable = true; + cfg->phase_sel = lvb_lvds_lane_phase_sel_4_16_ui; + cfg->amp = lvb_lvds_lane_amp_300_mv; + cfg->vcom = lvb_lvds_lane_vcom_1_2_v; + cfg->fvco_div4 = true; +} + +void lvb_lvds_phy_lane_init(LVB_Type *ptr, lvb_lvds_lane_idx_t tx_index, lvb_lvds_phy_lane_config_t *cfg) +{ + ptr->TX_PHY[tx_index].CTL0 = (ptr->TX_PHY[tx_index].CTL0 & ~(LVB_TX_PHY_CTL0_TX_IDLE_MASK | + LVB_TX_PHY_CTL0_TX_RTERM_EN_MASK | + LVB_TX_PHY_CTL0_TX_BUS_WIDTH_MASK | + LVB_TX_PHY_CTL0_TX_PHASE_SEL_MASK | + LVB_TX_PHY_CTL0_TX_VCOM_MASK | + LVB_TX_PHY_CTL0_TX_AMP_MASK)) | + (cfg->tx_idle ? LVB_TX_PHY_CTL0_TX_IDLE_MASK : 0) | + (cfg->rterm_enable ? LVB_TX_PHY_CTL0_TX_RTERM_EN_MASK : 0) | + LVB_TX_PHY_CTL0_TX_BUS_WIDTH_SET(2) | /* only 7bit */ + LVB_TX_PHY_CTL0_TX_PHASE_SEL_SET(cfg->phase_sel) | + LVB_TX_PHY_CTL0_TX_VCOM_SET(cfg->vcom) | + LVB_TX_PHY_CTL0_TX_AMP_SET(cfg->amp); + + if (cfg->fvco_div4) { + ptr->TX_PHY[tx_index].CTL0 |= (1ul<<7); + } else { + ptr->TX_PHY[tx_index].CTL0 &= ~(1ul<<7); + } +} + +void lvb_lvds_phy0_poweron(LVB_Type *ptr) +{ + ptr->PHY_POW_CTRL[0] = (ptr->PHY_POW_CTRL[0] & ~(LVB_PHY_POW_CTRL_TXCK_PD_MASK | + LVB_PHY_POW_CTRL_TX3_PD_MASK | LVB_PHY_POW_CTRL_TX2_PD_MASK | + LVB_PHY_POW_CTRL_TX1_PD_MASK | LVB_PHY_POW_CTRL_TX0_PD_MASK)) | + LVB_PHY_POW_CTRL_PWON_PLL_MASK; +} + +void lvb_lvds_phy1_poweron(LVB_Type *ptr) +{ + ptr->PHY_POW_CTRL[1] = (ptr->PHY_POW_CTRL[1] & ~(LVB_PHY_POW_CTRL_TXCK_PD_MASK | + LVB_PHY_POW_CTRL_TX3_PD_MASK | LVB_PHY_POW_CTRL_TX2_PD_MASK | + LVB_PHY_POW_CTRL_TX1_PD_MASK | LVB_PHY_POW_CTRL_TX0_PD_MASK)) | + LVB_PHY_POW_CTRL_PWON_PLL_MASK; +} + +void lvb_lvds_phy0_powerdown(LVB_Type *ptr) +{ + ptr->PHY_POW_CTRL[0] = (ptr->PHY_POW_CTRL[0] & ~LVB_PHY_POW_CTRL_PWON_PLL_MASK) | + LVB_PHY_POW_CTRL_TXCK_PD_MASK | LVB_PHY_POW_CTRL_TX3_PD_MASK | + LVB_PHY_POW_CTRL_TX2_PD_MASK | LVB_PHY_POW_CTRL_TX1_PD_MASK | + LVB_PHY_POW_CTRL_TX0_PD_MASK; +} + +void lvb_lvds_phy1_powerdown(LVB_Type *ptr) +{ + ptr->PHY_POW_CTRL[1] = (ptr->PHY_POW_CTRL[1] & ~LVB_PHY_POW_CTRL_PWON_PLL_MASK) | + LVB_PHY_POW_CTRL_TXCK_PD_MASK | LVB_PHY_POW_CTRL_TX3_PD_MASK | + LVB_PHY_POW_CTRL_TX2_PD_MASK | LVB_PHY_POW_CTRL_TX1_PD_MASK | + LVB_PHY_POW_CTRL_TX0_PD_MASK; +} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mcan_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mcan_drv.c index 044a95c71f7..a0ca301d2fc 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mcan_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mcan_drv.c @@ -8,14 +8,24 @@ #include #include -#define MCAN_CAN_BAUDRATE_DEFAULT (500UL * 1000UL) /*!< Default CAN2.0 baudrate:500 kbps */ -#define MCAN_CANFD_BAUDRATE_DEFAULT (2UL * 1000UL * 1000UL) /*!< Default CANFD baudrate: 2 Mbps */ - /*********************************************************************************************************************** * * Definitions * **********************************************************************************************************************/ + +#define MCAN_CAN_BAUDRATE_DEFAULT (500UL * 1000UL) /*!< Default CAN2.0 baudrate:500 kbps */ +#define MCAN_CANFD_BAUDRATE_DEFAULT (2UL * 1000UL * 1000UL) /*!< Default CANFD baudrate: 2 Mbps */ + +/* Hardware restriction of each types of element for MCAN */ +#define MCAN_STD_FILTER_ELEM_CNT_MAX (128U) +#define MCAN_EXT_FILTER_ELEM_CNT_MAX (64U) +#define MCAN_RXFIFO_ELEM_CNT_MAX (64U) +#define MCAN_RXBUF_ELEM_CNT_MAX (64U) +#define MCAN_TXEVT_FIFO_ELEM_CNT_MAX (32U) +#define MCAN_TXBUF_ELEM_CNT_MAX (32U) + + #define NUM_TQ_SYNC_SEG (1U) /** @@ -625,10 +635,19 @@ void mcan_get_default_config(MCAN_Type *ptr, mcan_config_t *config) /* Default TSU configuration */ mcan_tsu_config_t *tsu_config = &config->tsu_config; tsu_config->prescaler = 1U; - tsu_config->ext_timebase_src = MCAN_TSU_EXT_TIMEBASE_SRC_PTP; +#if defined(MCAN_SOC_TSU_SRC_TWO_STAGES) && (MCAN_SOC_TSU_SRC_TWO_STAGES == 1) + tsu_config->ext_timebase_src = MCAN_TSU_EXT_TIMEBASE_SRC_TBSEL_0; + tsu_config->tbsel_option = MCAN_TSU_TBSEL_PTPC0; +#else + tsu_config->ext_timebase_src = MCAN_TSU_EXT_TIMEBASE_SRC_PTPC; +#endif tsu_config->use_ext_timebase = false; tsu_config->capture_on_sof = false; tsu_config->enable_tsu = false; + + config->timeout_cfg.enable_timeout_counter = false; + config->timeout_cfg.timeout_period = 0xFFFFU; + config->timeout_cfg.timeout_sel = mcan_timeout_continuous_operation; } static void mcan_config_rxfifo(MCAN_Type *ptr, uint32_t index, uint32_t reg_val) @@ -648,6 +667,9 @@ hpm_stat_t mcan_config_ram(MCAN_Type *ptr, mcan_ram_config_t *config) uint32_t elem_count; uint32_t start_addr = mcan_get_ram_offset(ptr); if (config->enable_std_filter) { + if (config->std_filter_elem_count > MCAN_STD_FILTER_ELEM_CNT_MAX) { + break; + } mcan_filter_config_t filter_config = { .reg_val = 0 }; filter_config.list_size = config->std_filter_elem_count; filter_config.list_start_addr = start_addr; @@ -658,6 +680,9 @@ hpm_stat_t mcan_config_ram(MCAN_Type *ptr, mcan_ram_config_t *config) } if (config->enable_ext_filter) { + if (config->ext_filter_elem_count > MCAN_EXT_FILTER_ELEM_CNT_MAX) { + break; + } mcan_filter_config_t filter_config = { .reg_val = 0 }; filter_config.list_size = config->ext_filter_elem_count; filter_config.list_start_addr = start_addr; @@ -671,9 +696,12 @@ hpm_stat_t mcan_config_ram(MCAN_Type *ptr, mcan_ram_config_t *config) for (uint32_t i = 0; i < ARRAY_SIZE(config->rxfifos); i++) { if (config->rxfifos[i].enable) { - elem_bytes = - mcan_get_data_field_size(config->rxfifos[i].data_field_size) + MCAN_MESSAGE_HEADER_SIZE_IN_BYTES; + elem_bytes = mcan_get_data_field_size(config->rxfifos[i].data_field_size) + + MCAN_MESSAGE_HEADER_SIZE_IN_BYTES; elem_count = config->rxfifos[i].elem_count; + if (elem_count > MCAN_RXFIFO_ELEM_CNT_MAX) { + return status_invalid_argument; + } mcan_rxfifo_config_t rxfifo_config = { .reg_val = 0 }; rxfifo_config.start_addr = start_addr; rxfifo_config.watermark = 1U; @@ -701,10 +729,13 @@ hpm_stat_t mcan_config_ram(MCAN_Type *ptr, mcan_ram_config_t *config) if (config->enable_rxbuf) { elem_bytes = mcan_get_data_field_size(config->rxbuf_data_field_size) + MCAN_MESSAGE_HEADER_SIZE_IN_BYTES; elem_count = config->rxbuf_elem_count; + if (elem_count > MCAN_RXFIFO_ELEM_CNT_MAX) { + break; + } ptr->RXBC = start_addr; rx_fifo_buf_elem_config.buf_data_field_size = config->rxbuf_data_field_size; - start_addr += elem_bytes * elem_count;; + start_addr += elem_bytes * elem_count; } else { rx_fifo_buf_elem_config.buf_data_field_size = 0; ptr->RXBC = MCAN_RAM_ADDR_INVALID; @@ -719,6 +750,10 @@ hpm_stat_t mcan_config_ram(MCAN_Type *ptr, mcan_ram_config_t *config) txbuf_config.tx_fifo_queue_mode = config->txfifo_or_txqueue_mode; elem_count = config->txbuf_fifo_or_queue_elem_count + config->txbuf_dedicated_txbuf_elem_count; + if (elem_count > MCAN_TXEVT_FIFO_ELEM_CNT_MAX) { + break; + } + elem_bytes = mcan_get_data_field_size(config->txbuf_data_field_size) + MCAN_MESSAGE_HEADER_SIZE_IN_BYTES; start_addr += elem_count * elem_bytes; @@ -733,6 +768,10 @@ hpm_stat_t mcan_config_ram(MCAN_Type *ptr, mcan_ram_config_t *config) if (config->enable_tx_evt_fifo) { elem_bytes = sizeof(mcan_tx_event_fifo_elem_t); elem_count = config->tx_evt_fifo_elem_count; + if (elem_count > MCAN_TXEVT_FIFO_ELEM_CNT_MAX) { + break; + } + txevt_fifo_config.start_addr = start_addr; txevt_fifo_config.fifo_size = elem_count; txevt_fifo_config.fifo_watermark = 1U; @@ -762,30 +801,45 @@ hpm_stat_t mcan_config_ram_with_flexible_config(MCAN_Type *ptr, mcan_ram_flexibl hpm_stat_t status = status_invalid_argument; do { if (config->enable_std_filter) { + if (config->std_filter_config.list_size > MCAN_STD_FILTER_ELEM_CNT_MAX) { + break; + } ptr->SIDFC = config->std_filter_config.reg_val; } else { ptr->SIDFC = MCAN_RAM_ADDR_INVALID; } if (config->enable_ext_filter) { + if (config->std_filter_config.list_size > MCAN_EXT_FILTER_ELEM_CNT_MAX) { + break; + } ptr->XIDFC = config->ext_filter_config.reg_val; } else { ptr->XIDFC = MCAN_RAM_ADDR_INVALID; } if (config->enable_rxfifo0) { + if (config->rxfifo0_config.fifo_size > MCAN_RXFIFO_ELEM_CNT_MAX) { + break; + } ptr->RXF0C = config->rxfifo0_config.reg_val; } else { ptr->RXF0C = MCAN_RAM_ADDR_INVALID; } if (config->enable_rxfifo1) { + if (config->rxfifo1_config.fifo_size > MCAN_RXFIFO_ELEM_CNT_MAX) { + break; + } ptr->RXF1C = config->rxfifo1_config.reg_val; } else { ptr->RXF1C = MCAN_RAM_ADDR_INVALID; } if (config->enable_rxbuf) { + /* NOTE: There is no register field for SW to validate the rxbuf element count, + * users should ensure the parameters are in valid range. + */ ptr->RXBC = config->rxbuf_config.start_addr; } else { ptr->RXBC = MCAN_RAM_ADDR_INVALID; @@ -793,6 +847,10 @@ hpm_stat_t mcan_config_ram_with_flexible_config(MCAN_Type *ptr, mcan_ram_flexibl ptr->RXESC = config->rx_elem_config.reg_val; if (config->enable_txbuf) { + uint32_t tx_fifo_size = config->txbuf_config.fifo_queue_size + config->txbuf_config.dedicated_tx_buf_size; + if (tx_fifo_size > MCAN_TXBUF_ELEM_CNT_MAX) { + break; + } ptr->TXESC = config->txbuf_elem_config.data_field_size; } else { ptr->TXESC = MCAN_RAM_ADDR_INVALID; @@ -801,6 +859,9 @@ hpm_stat_t mcan_config_ram_with_flexible_config(MCAN_Type *ptr, mcan_ram_flexibl ptr->TXBC = config->txbuf_config.reg_val; if (config->enable_tx_evt_fifo) { + if (config->tx_evt_fifo_config.fifo_size > MCAN_TXEVT_FIFO_ELEM_CNT_MAX) { + break; + } ptr->TXEFC = config->tx_evt_fifo_config.reg_val; } else { ptr->TXEFC = MCAN_RAM_ADDR_INVALID; @@ -896,6 +957,9 @@ static hpm_stat_t mcan_set_tsu(MCAN_Type *ptr, mcan_tsu_config_t *config) if (config->use_ext_timebase) { tscfg |= MCAN_TSCFG_TBCS_MASK; mcan_set_tsu_ext_timebase_src(ptr, config->ext_timebase_src); +#if defined(MCAN_SOC_TSU_SRC_TWO_STAGES) && (MCAN_SOC_TSU_SRC_TWO_STAGES == 1) + mcan_set_tsu_tbsel_option(ptr, config->ext_timebase_src, config->tbsel_option); +#endif } if (config->enable_64bit_timestamp) { tscfg |= MCAN_TSCFG_EN64_MASK; @@ -937,10 +1001,32 @@ hpm_stat_t mcan_init(MCAN_Type *ptr, mcan_config_t *config, uint32_t src_clk_fre break; } - ptr->CCCR |= MCAN_CCCR_INIT_MASK; - while ((ptr->CCCR & MCAN_CCCR_INIT_MASK) == 0) { + mcan_enable_clock(ptr); + uint32_t retry_cnt = 10000UL; + do { + retry_cnt--; + if (retry_cnt == 0UL) { + break; + } + } while (!mcan_is_clock_enabled(ptr)); + if (retry_cnt == 0UL) { + status = status_timeout; + break; + } + ptr->CCCR |= MCAN_CCCR_INIT_MASK; + retry_cnt = 10000UL; + while ((ptr->CCCR & MCAN_CCCR_INIT_MASK) == 0U) { + retry_cnt--; + if (retry_cnt == 0UL) { + break; + } } + if (retry_cnt == 0UL) { + status = status_timeout; + break; + } + ptr->CCCR |= MCAN_CCCR_CCE_MASK; if (!config->use_lowlevel_timing_setting) { @@ -1027,6 +1113,18 @@ hpm_stat_t mcan_init(MCAN_Type *ptr, mcan_config_t *config, uint32_t src_clk_fre ptr->CCCR &= ~MCAN_CCCR_EFBI_MASK; } + if (config->disable_auto_retransmission) { + ptr->CCCR |= MCAN_CCCR_DAR_MASK; + } else { + ptr->CCCR &= ~MCAN_CCCR_DAR_MASK; + } + + if (config->enable_restricted_operation_mode) { + ptr->CCCR |= MCAN_CCCR_ASM_MASK; + } else { + ptr->CCCR &= ~MCAN_CCCR_ASM_MASK; + } + /* Configure Transmitter Delay Compensation */ if (config->enable_tdc) { ptr->DBTP |= MCAN_DBTP_TDC_MASK; @@ -1070,9 +1168,24 @@ hpm_stat_t mcan_init(MCAN_Type *ptr, mcan_config_t *config, uint32_t src_clk_fre status = mcan_config_all_filters(ptr, &config->all_filters_config); HPM_BREAK_IF(status != status_success); + /* Disable all interrupts by default */ + mcan_disable_interrupts(ptr, ~0UL); + mcan_disable_txbuf_transmission_interrupt(ptr, ~0UL); + mcan_disable_txbuf_cancel_finish_interrupt(ptr, ~0UL); + /* Enable interrupts on demand */ + mcan_enable_interrupts(ptr, config->interrupt_mask); + mcan_enable_txbuf_transmission_interrupt(ptr, config->txbuf_trans_interrupt_mask); + mcan_enable_txbuf_cancel_finish_interrupt(ptr, config->txbuf_cancel_finish_interrupt_mask); + /* Clear all Interrupt Flags */ mcan_clear_interrupt_flags(ptr, ~0UL); + /* Configure timeout */ + const mcan_timeout_config_t *timeout_cfg = &config->timeout_cfg; + ptr->TOCC = MCAN_TOCC_RP_SET(timeout_cfg->enable_timeout_counter) | + MCAN_TOCC_TOP_SET(timeout_cfg->timeout_period) | + MCAN_TOCC_TOS_SET(timeout_cfg->timeout_sel); + ptr->CCCR &= ~MCAN_CCCR_INIT_MASK; while ((ptr->CCCR & MCAN_CCCR_INIT_MASK) != 0U) { } @@ -1084,6 +1197,42 @@ hpm_stat_t mcan_init(MCAN_Type *ptr, mcan_config_t *config, uint32_t src_clk_fre return status; } +void mcan_deinit(MCAN_Type *ptr) +{ + if (ptr != NULL) { + + mcan_enter_init_mode(ptr); /* Stop MCAN function */ + + /* Enable write access to protected configuration registers */ + mcan_enable_write_to_prot_config_registers(ptr); + + /* Restore critical registers to default values */ + ptr->RWD = 0UL; + ptr->TSCC = 0UL; + ptr->GFC = 0UL; + ptr->SIDFC = 0UL; + ptr->XIDAM = 0UL; + ptr->XIDAM = 0x1FFFFFFFUL; + ptr->RXBC = 0UL; + ptr->RXF1C = 0UL; + ptr->RXESC = 0UL; + ptr->TXBC = 0UL; + ptr->TXESC = 0UL; + ptr->TXEFC = 0UL; + + ptr->TSCFG = 0UL; + + /* Disable all interrupts and clear all flags */ + mcan_disable_interrupts(ptr, ~0UL); + mcan_clear_interrupt_flags(ptr, ~0UL); + mcan_disable_txbuf_transmission_interrupt(ptr, ~0UL); + mcan_disable_txbuf_cancel_finish_interrupt(ptr, ~0UL); + + /* Restore CCCR to default value */ + ptr->CCCR = MCAN_CCCR_INIT_MASK; + } +} + hpm_stat_t mcan_set_filter_element(MCAN_Type *ptr, const mcan_filter_elem_t *filter_elem, uint32_t index) { hpm_stat_t status = status_invalid_argument; @@ -1463,20 +1612,12 @@ hpm_stat_t mcan_transmit_blocking(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame) { hpm_stat_t status = status_invalid_argument; do { - if ((ptr == NULL) || (tx_frame == NULL)) { - break; - } - if (mcan_is_txfifo_full(ptr)) { - status = status_mcan_txfifo_full; + uint32_t put_index = 0; + status = mcan_transmit_via_txfifo_nonblocking(ptr, tx_frame, &put_index); + if (status != status_success) { break; } - status = mcan_write_txfifo(ptr, tx_frame); - HPM_BREAK_IF(status != status_success); - - uint32_t put_index = mcan_get_txfifo_put_index(ptr); - mcan_send_add_request(ptr, put_index); - uint32_t retry_cnt = 0; while (!mcan_is_transmit_occurred(ptr, put_index)) { retry_cnt++; @@ -1493,6 +1634,35 @@ hpm_stat_t mcan_transmit_blocking(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame) return status; } +hpm_stat_t mcan_transmit_via_txfifo_nonblocking(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame, uint32_t *fifo_index) +{ + hpm_stat_t status = status_invalid_argument; + do { + if ((ptr == NULL) || (tx_frame == NULL)) { + break; + } + if (mcan_is_txfifo_full(ptr)) { + status = status_mcan_txfifo_full; + break; + } + + status = mcan_write_txfifo(ptr, tx_frame); + HPM_BREAK_IF(status != status_success); + + uint32_t put_index = mcan_get_txfifo_put_index(ptr); + mcan_send_add_request(ptr, put_index); + + if (fifo_index != NULL) { + *fifo_index = put_index; + } + + status = status_success; + + } while (false); + + return status; +} + hpm_stat_t mcan_receive_from_buf_blocking(MCAN_Type *ptr, uint32_t index, mcan_rx_message_t *rx_frame) { hpm_stat_t status = status_invalid_argument; @@ -1683,3 +1853,55 @@ hpm_stat_t mcan_get_timestamp_from_received_message(MCAN_Type *ptr, return status; } + +hpm_stat_t mcan_parse_protocol_status(uint32_t psr, mcan_protocol_status_t *protocol_status) +{ + if (protocol_status == NULL) { + return status_invalid_argument; + } + memset(protocol_status, 0, sizeof(mcan_protocol_status_t)); + uint32_t psr_val = psr; + if (MCAN_PSR_PXE_GET(psr_val) != 0U) { + protocol_status->protocol_exception_evt_occurred = true; + } + if (MCAN_PSR_RFDF_GET(psr_val) != 0U) { + protocol_status->canfd_msg_received = true; + } + if (MCAN_PSR_RBRS_GET(psr_val) != 0U) { + protocol_status->brs_flag_set_in_last_rcv_canfd_msg = true; + } + if (MCAN_PSR_RESI_GET(psr_val) != 0U) { + protocol_status->esi_flag_set_in_last_rcv_canfd_msg = true; + } + if (MCAN_PSR_BO_GET(psr_val) != 0U) { + protocol_status->in_bus_off_state = true; + } + if (MCAN_PSR_EW_GET(psr_val) != 0U) { + protocol_status->in_warning_state = true; + } + if (MCAN_PSR_EP_GET(psr_val) != 0U) { + protocol_status->in_error_passive_state = true; + } + protocol_status->activity = (mcan_activity_state_t) MCAN_PSR_ACT_GET(psr_val); + protocol_status->tdc_val = MCAN_PSR_TDCV_GET(psr_val); + + if (protocol_status->brs_flag_set_in_last_rcv_canfd_msg) { + protocol_status->last_error_code = (mcan_last_err_code_t) MCAN_PSR_DLEC_GET(psr_val); + } else { + protocol_status->last_error_code = (mcan_last_err_code_t) MCAN_PSR_LEC_GET(psr_val); + } + return status_success; +} + +hpm_stat_t mcan_get_protocol_status(MCAN_Type *ptr, mcan_protocol_status_t *protocol_status) +{ + hpm_stat_t status = status_invalid_argument; + + do { + HPM_BREAK_IF((ptr == NULL) || (protocol_status == NULL)); + status = mcan_parse_protocol_status(ptr->PSR, protocol_status); + + } while (false); + + return status; +} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_csi_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_csi_drv.c new file mode 100644 index 00000000000..ffdfd6e190f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_csi_drv.c @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_mipi_csi_drv.h" + + +void mipi_csi_get_defconfig(mipi_csi_config_t *cfg) +{ + cfg->data_type = mipi_csi_data_type_rgb565; + cfg->lanes = 2; +} + +void mipi_csi_init(MIPI_CSI_Type *ptr, mipi_csi_config_t *cfg) +{ + ptr->CSI2_RESETN = 0x01; + ptr->IPI_SOFTRSTN = 0x01; + + if (cfg->lanes < 1 || cfg->lanes > 2) + cfg->lanes = 2; + ptr->N_LANES = MIPI_CSI_N_LANES_N_LANES_SET(cfg->lanes - 1); + + /* + * only camera mode + */ + ptr->IPI_MODE = MIPI_CSI_IPI_MODE_IPI_ENABLE_MASK; + ptr->IPI_DATA_TYPE = (ptr->IPI_DATA_TYPE & ~(MIPI_CSI_IPI_DATA_TYPE_IPI_DATA_TYPE_MASK)) | + MIPI_CSI_IPI_DATA_TYPE_IPI_DATA_TYPE_SET(cfg->data_type); + + ptr->IPI_MEM_FLASH |= MIPI_CSI_IPI_MEM_FLASH_IPI_AUTO_FLUSH_MASK; + + /* + * [16]: 0: Controller selects it automatically + */ + ptr->IPI_ADV_FEATURES = 0; + + ptr->IPI_HSD_TIME = 20; + ptr->IPI_HSA_TIME = 0; +} + +void mipi_csi_phy_poweron(MIPI_CSI_Type *ptr) +{ + /* + * MIPI CSI : PHY + * ---------------------------- + * PHY_SHUTDOWNZ : ~iddqen + * DPHY_RSTZ : hw_rst_n + */ + ptr->DPHY_RSTZ = 0x01; + ptr->PHY_SHUTDOWNZ = 0x01; +} + +void mipi_csi_phy_powerdown(MIPI_CSI_Type *ptr) +{ + /* + * MIPI CSI : PHY + * ---------------------------- + * PHY_SHUTDOWNZ : ~iddqen + * DPHY_RSTZ : hw_rst_n + */ + ptr->DPHY_RSTZ = 0x00; + ptr->PHY_SHUTDOWNZ = 0x00; +} + + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_csi_phy_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_csi_phy_drv.c new file mode 100644 index 00000000000..41fd9b84541 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_csi_phy_drv.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_mipi_csi_phy_drv.h" + +void mipi_csi_phy_default_config(mipi_csi_phy_config_t *cfg) +{ + cfg->clane_cfg.t_settle_ns = 140; + cfg->clane_cfg.t_term_en_ns = 30; + + cfg->dlane_cfg.t_settle_ns = 100; + cfg->dlane_cfg.t_term_en_ns = 30; +} + +void mipi_csi_phy_init(MIPI_CSI_PHY_Type *ptr, mipi_csi_phy_config_t *cfg) +{ + ptr->SOFT_RST = 0x03; + ptr->SOFT_RST = 0x00; + + ptr->CLANE_PARA = (ptr->CLANE_PARA & ~(MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_MASK | + MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_MASK)) | + MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_SET(cfg->clane_cfg.t_term_en_ns / 10) | + MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_SET(cfg->clane_cfg.t_settle_ns / 10); + + + ptr->T_HS_TERMEN = (ptr->T_HS_TERMEN & ~(MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_MASK | + MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_MASK)) | + MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_SET(cfg->dlane_cfg.t_term_en_ns / 10) | + MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_SET(cfg->dlane_cfg.t_term_en_ns / 10); + + ptr->T_HS_SETTLE = (ptr->T_HS_SETTLE & ~(MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_MASK | + MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_MASK)) | + MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_SET(cfg->dlane_cfg.t_settle_ns / 10) | + MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_SET(cfg->dlane_cfg.t_settle_ns / 10); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_dsi_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_dsi_drv.c new file mode 100644 index 00000000000..3262758cdbc --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_dsi_drv.c @@ -0,0 +1,548 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_mipi_dsi_drv.h" + +#define MIPI_WAIT_COND(cond, timeout_us) \ +({ \ + volatile uint32_t timeout_cycle = 1000UL * (timeout_us); \ + for (;;) { \ + if (cond) \ + break; \ + if (timeout_us && timeout_cycle == 0) { \ + break; \ + } \ + timeout_cycle--; \ + } \ + (cond) ? true : false; \ +}) + +typedef struct mipi_dsi_packet { + uint8_t header[4]; /*!< the four bytes that make up the header (Data ID, Word Count or Packet Data, and ECC) */ + uint16_t payload_length; /*!< number of bytes in the payload */ + const uint8_t *payload; /*!< a pointer to a buffer containing the payload, if any */ +} mipi_dsi_packet_t; + +/** + * mipi_dsi_packet_format_is_short - check if a packet is of the short format + * @param type: MIPI DSI data type of the packet + * + * @return: true if the packet for the given data type is a short packet, false + * otherwise. + */ +static bool mipi_dsi_packet_format_is_short(uint8_t type) +{ + switch (type) { + case MIPI_DSI_SHUTDOWN_PERIPHERAL: + case MIPI_DSI_TURN_ON_PERIPHERAL: + case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: + case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: + case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: + case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: + case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: + case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: + case MIPI_DSI_DCS_SHORT_WRITE: + case MIPI_DSI_DCS_SHORT_WRITE_PARAM: + case MIPI_DSI_DCS_READ: + case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE: + return true; + } + + return false; +} + +/** + * mipi_dsi_packet_format_is_long - check if a packet is of the long format + * @param type: MIPI DSI data type of the packet + * + * @return: true if the packet for the given data type is a long packet, false + * otherwise. + */ +static bool mipi_dsi_packet_format_is_long(uint8_t type) +{ + switch (type) { + case MIPI_DSI_GENERIC_LONG_WRITE: + case MIPI_DSI_DCS_LONG_WRITE: + return true; + } + + return false; +} + +/** + * mipi_dsi_create_packet - create a packet from a message according to the + * DSI protocol + * @param packet: pointer to a DSI packet structure + * @param msg: message to translate into a packet + * + * @return: true on success or false on failure. + */ +static bool mipi_dsi_create_packet(mipi_dsi_packet_t *packet, const mipi_dsi_msg_t *msg) +{ + if (!packet || !msg) + return false; + + /* do some minimum sanity checking */ + if (!mipi_dsi_packet_format_is_short(msg->type) && + !mipi_dsi_packet_format_is_long(msg->type)) + return false; + + if (msg->channel > 3) + return false; + + memset(packet, 0, sizeof(*packet)); + packet->header[0] = ((msg->channel & 0x3) << 6) | (msg->type & 0x3f); + if (mipi_dsi_packet_format_is_long(msg->type)) { + packet->header[1] = (msg->tx_len >> 0) & 0xff; + packet->header[2] = (msg->tx_len >> 8) & 0xff; + + packet->payload_length = msg->tx_len; + packet->payload = (const uint8_t *)msg->tx_buf; + } else { + const uint8_t *tx = (const uint8_t *)msg->tx_buf; + + packet->header[1] = (msg->tx_len > 0) ? tx[0] : 0; + packet->header[2] = (msg->tx_len > 1) ? tx[1] : 0; + } + + return true; +} + +static void mipi_dsi_config_format(MIPI_DSI_Type *ptr, mipi_dsi_pixel_format_t format) +{ + uint32_t val = 0; + + switch ((uint8_t)format) { + case MIPI_DSI_FMT_RGB888: + val = MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SET(0x05); + break; + case MIPI_DSI_FMT_RGB666: + val = MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SET(0x04) | + MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_MASK; + break; + case MIPI_DSI_FMT_RGB666_PACKED: + val = MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SET(0x04); + break; + case MIPI_DSI_FMT_RGB565: + val = MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SET(0x04); + break; + } + + ptr->DPI_COLOR_CODING = val; +} + +/* Get lane byte clock cycles. */ +static int mipi_dsi_get_hcomponent_lbcc(uint32_t lane_mbps, uint32_t pixel_clock_khz, uint32_t hcomponent) +{ + uint32_t lbcc = hcomponent * lane_mbps * 1000 / 8; + + if (!pixel_clock_khz) + return 0; + + return HPM_DIV_ROUND_CLOSEST(lbcc, pixel_clock_khz); +} + +static void mipi_dsi_video_para_config(MIPI_DSI_Type *ptr, mipi_dsi_config_t *cfg) +{ + mipi_video_para_t *video_para = &cfg->video_para; + int htotal, lbcc; + + /* VID_HXXXX_TIME uint is lbcc(lane byte clock = lane_mbps / 8) */ + htotal = video_para->hactive + video_para->hsync_len + + video_para->hback_porch + video_para->hfront_porch; + lbcc = mipi_dsi_get_hcomponent_lbcc(cfg->lane_mbps, video_para->pixel_clock_khz, htotal); + ptr->VID_HLINE_TIME = lbcc; + lbcc = mipi_dsi_get_hcomponent_lbcc(cfg->lane_mbps, video_para->pixel_clock_khz, video_para->hsync_len); + ptr->VID_HSA_TIME = lbcc; + lbcc = mipi_dsi_get_hcomponent_lbcc(cfg->lane_mbps, video_para->pixel_clock_khz, video_para->hback_porch); + ptr->VID_HBP_TIME = lbcc; + + ptr->VID_VACTIVE_LINES = video_para->vactive; + ptr->VID_VSA_LINES = video_para->vsync_len; + ptr->VID_VBP_LINES = video_para->vback_porch; + ptr->VID_VFP_LINES = video_para->vfront_porch; +} + +static bool mipi_dsi_genif_wait_w_pld_fifo_not_full(MIPI_DSI_Type *ptr) +{ + uint32_t mask = MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_MASK; + return MIPI_WAIT_COND(!(ptr->CMD_PKT_STATUS & mask), 10000); +} + +static bool mipi_dsi_genif_wait_cmd_fifo_not_full(MIPI_DSI_Type *ptr) +{ + uint32_t mask = MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_MASK; + return MIPI_WAIT_COND(!(ptr->CMD_PKT_STATUS & mask), 10000); +} + +static bool mipi_dsi_genif_wait_write_fifo_empty(MIPI_DSI_Type *ptr) +{ + uint32_t mask = MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_MASK | + MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_MASK; + + return MIPI_WAIT_COND((ptr->CMD_PKT_STATUS & mask) == mask, 10000); +} + +static bool dw_mipi_dsi_read_from_fifo(MIPI_DSI_Type *ptr, + const struct mipi_dsi_msg *msg) +{ + uint8_t *payload = (uint8_t *)msg->rx_buf; + uint16_t length; + uint32_t val; + uint32_t mask; + bool ret = true; + + mask = MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_MASK; + ret = MIPI_WAIT_COND(!(ptr->CMD_PKT_STATUS & mask), 10000); + if (ret == false) { + return ret; + } + + /* Receive payload */ + for (length = msg->rx_len; length; length -= 4) { + mask = MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_MASK; + ret = MIPI_WAIT_COND(!(ptr->CMD_PKT_STATUS & mask), 10000); + if (ret == false) { + return ret; + } + + val = ptr->GEN_PLD_DATA; + + switch (length) { + case 3: + payload[2] = (val >> 16) & 0xff; + /* Fall through */ + case 2: + payload[1] = (val >> 8) & 0xff; + /* Fall through */ + case 1: + payload[0] = val & 0xff; + return ret; + } + + payload[0] = (val >> 0) & 0xff; + payload[1] = (val >> 8) & 0xff; + payload[2] = (val >> 16) & 0xff; + payload[3] = (val >> 24) & 0xff; + payload += 4; + } + + return ret; +} + +static uint32_t get_le32(const uint8_t *p) +{ + return p[0] | p[1] << 8 | p[2] << 16 | p[3] << 24; +} + +void mipi_dsi_get_defconfig_on_video(mipi_dsi_config_t *cfg) +{ + mipi_video_para_t video_para = { + .pixel_clock_khz = 59400, + .hactive = 800, + .hsync_len = 8, + .hback_porch = 48, + .hfront_porch = 52, + .vsync_len = 6, + .vactive = 1280, + .vback_porch = 16, + .vfront_porch = 15 + }; + + cfg->lanes = 4; + cfg->channel = 0; + cfg->lane_mbps = 500; + cfg->disable_eotp = false; + cfg->pixel_format = MIPI_DSI_FMT_RGB888; + cfg->video_mode = MIPI_DSI_VIDEO_MODE_BURST; + cfg->video_para = video_para; +} + +void mipi_dsi_init(MIPI_DSI_Type *ptr, mipi_dsi_config_t *cfg) +{ + uint32_t val; + + /* PWR need reset when config register */ + ptr->PWR_UP &= ~MIPI_DSI_PWR_UP_SHUTDOWNZ_MASK; + + /* escclk config about 20MHz and esc_clk_div > 1*/ + uint32_t esc_clk_div = HPM_DIV_ROUND_UP(cfg->lane_mbps / 8, 20); + esc_clk_div = esc_clk_div <= 1 ? 2 : esc_clk_div; + + ptr->CLKMGR_CFG = MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_SET(10) | + MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_SET(esc_clk_div); + + mipi_dsi_config_format(ptr, cfg->pixel_format); + ptr->DPI_VCID = MIPI_DSI_DPI_VCID_DPI_VCID_SET(cfg->channel); + ptr->DPI_LP_CMD_TIM = MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_SET(4) | + MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_SET(4); + + val = MIPI_DSI_PCKHDL_CFG_BTA_EN_MASK | + MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_MASK | + MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_MASK | + MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_MASK; + if (cfg->disable_eotp) + val &= ~MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_MASK; + ptr->PCKHDL_CFG = val; + + val = MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_MASK | + MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_MASK | + MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_MASK | + MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_MASK | + MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_MASK | + MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_MASK | + MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_SET(cfg->video_mode); + ptr->VID_MODE_CFG = val; + + ptr->VID_PKT_SIZE = cfg->video_para.hactive; + + ptr->TO_CNT_CFG = MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_SET(1000) | + MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_SET(1000); + + ptr->BTA_TO_CNT = MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_SET(0xd00); + + mipi_dsi_video_para_config(ptr, cfg); + + ptr->PHY_TMR_CFG = MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_SET(0x40) | + MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_SET(0x40); + ptr->PHY_TMR_RD = 10000; + ptr->PHY_TMR_LPCLK_CFG = MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_SET(0x40) | + MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_SET(0x40); + ptr->PHY_IF_CFG = MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_SET(0x20) | + MIPI_DSI_PHY_IF_CFG_N_LANES_SET(cfg->lanes - 1); + ptr->PWR_UP |= MIPI_DSI_PWR_UP_SHUTDOWNZ_MASK; +} + +void mipi_dsi_phy_poweron(MIPI_DSI_Type *ptr) +{ + ptr->PHY_RSTZ |= MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_MASK; + ptr->PHY_RSTZ |= MIPI_DSI_PHY_RSTZ_PHY_RSTZ_MASK; +} + +void mipi_dsi_phy_powerdown(MIPI_DSI_Type *ptr) +{ + ptr->PHY_RSTZ &= ~(MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_MASK | + MIPI_DSI_PHY_RSTZ_PHY_RSTZ_MASK); +} + +void mipi_dsi_video_mode_hs_transfer_enable(MIPI_DSI_Type *ptr) +{ + ptr->PWR_UP &= ~MIPI_DSI_PWR_UP_SHUTDOWNZ_MASK; + ptr->LPCLK_CTRL |= MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_MASK; + ptr->MODE_CFG = MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_SET(0); + ptr->PWR_UP |= MIPI_DSI_PWR_UP_SHUTDOWNZ_MASK; +} + +void mipi_dsi_video_mode_hs_transfer_disable(MIPI_DSI_Type *ptr) +{ + ptr->PWR_UP &= ~MIPI_DSI_PWR_UP_SHUTDOWNZ_MASK; + ptr->LPCLK_CTRL &= ~MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_MASK; +} + +int mipi_dsi_lp_cmd_transfer(MIPI_DSI_Type *ptr, const mipi_dsi_msg_t *msg) +{ + struct mipi_dsi_packet packet; + int ret = -1; + int val; + + /* do some minimum sanity checking */ + if (!mipi_dsi_packet_format_is_short(msg->type) && + !mipi_dsi_packet_format_is_long(msg->type)) + return ret; + + ptr->VID_MODE_CFG |= MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_MASK; + ptr->LPCLK_CTRL &= ~MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_MASK; + + /* create a packet to the DSI protocol */ + if (mipi_dsi_create_packet(&packet, msg) == false) { + return ret; + } + + ptr->CMD_MODE_CFG = 1u<<24 | 1u<<19 | 1u<<18 | 1u<<17 | + 1u<<16 | 1u<<14 | 1u<<13 | 1u<<12 | + 1u<<11 | 1u<<10 | 1u<<9 | 1u<<8; + + /* config to cmd mode */ + ptr->MODE_CFG = MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_SET(1); + + /* Send payload */ + while (packet.payload_length > 0) { + /* + * Alternatively, you can always keep the FIFO + * nearly full by monitoring the FIFO state until + * it is not full, and then writea single word of data. + * This solution is more resource consuming + * but it simultaneously avoids FIFO starvation, + * making it possible to use FIFO sizes smaller than + * the amount of data of the longest packet to be written. + */ + if (mipi_dsi_genif_wait_w_pld_fifo_not_full(ptr) == false) + return ret; + + if (packet.payload_length < 4) { + /* send residu payload */ + val = 0; + memcpy(&val, packet.payload, packet.payload_length); + packet.payload_length = 0; + } else { + val = get_le32(packet.payload); + packet.payload += 4; + packet.payload_length -= 4; + } + ptr->GEN_PLD_DATA = val; + } + + if (mipi_dsi_genif_wait_cmd_fifo_not_full(ptr) == false) + return ret; + + /* Send packet header */ + val = get_le32(packet.header); + ptr->GEN_HDR = val; + + if (mipi_dsi_genif_wait_write_fifo_empty(ptr) == false) + return ret; + + if (msg->rx_len) { + if (dw_mipi_dsi_read_from_fifo(ptr, msg) == false) + return ret; + } + + return msg->rx_len ? msg->rx_len : msg->tx_len; +} + +int mipi_dsi_set_maximum_return_packet_size(MIPI_DSI_Type *ptr, uint8_t channel, uint16_t value) +{ + uint8_t tx[2] = {value & 0xff, value >> 8}; + struct mipi_dsi_msg msg = { + .channel = channel, + .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, + .tx_len = sizeof(tx), + .tx_buf = tx, + }; + + int ret = mipi_dsi_lp_cmd_transfer(ptr, &msg); + + return (ret < 0) ? false : true; +} + +int mipi_dsi_generic_write(MIPI_DSI_Type *ptr, uint8_t channel, const void *payload, + uint16_t size) +{ + struct mipi_dsi_msg msg = { + .channel = channel, + .tx_buf = payload, + .tx_len = size + }; + + switch (size) { + case 0: + msg.type = MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM; + break; + case 1: + msg.type = MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM; + break; + case 2: + msg.type = MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM; + break; + default: + msg.type = MIPI_DSI_GENERIC_LONG_WRITE; + break; + } + + return mipi_dsi_lp_cmd_transfer(ptr, &msg); +} + + +int mipi_dsi_generic_read(MIPI_DSI_Type *ptr, uint8_t channel, const void *params, + uint16_t num_params, void *data, uint16_t size) +{ + struct mipi_dsi_msg msg = { + .channel = channel, + .tx_len = num_params, + .tx_buf = params, + .rx_len = size, + .rx_buf = data + }; + + switch (num_params) { + case 0: + msg.type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM; + break; + case 1: + msg.type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM; + break; + case 2: + msg.type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM; + break; + default: + return -1; + } + + return mipi_dsi_lp_cmd_transfer(ptr, &msg); +} + + +int mipi_dsi_dcs_write_buffer(MIPI_DSI_Type *ptr, uint8_t channel, + const void *data, uint16_t len) +{ + struct mipi_dsi_msg msg = { + .channel = channel, + .tx_buf = data, + .tx_len = len + }; + + switch (len) { + case 0: + return -1; + case 1: + msg.type = MIPI_DSI_DCS_SHORT_WRITE; + break; + case 2: + msg.type = MIPI_DSI_DCS_SHORT_WRITE_PARAM; + break; + default: + msg.type = MIPI_DSI_DCS_LONG_WRITE; + break; + } + + return mipi_dsi_lp_cmd_transfer(ptr, &msg); +} + +int mipi_dsi_dcs_write(MIPI_DSI_Type *ptr, uint8_t channel, uint8_t cmd, + const void *data, uint16_t len) +{ + int err; + uint16_t size; + uint8_t tx[128]; + + if (len < sizeof(tx)) { + size = 1 + len; + tx[0] = cmd; + if (len > 0) + memcpy(&tx[1], data, len); + } else { + return -1; + } + + err = mipi_dsi_dcs_write_buffer(ptr, channel, tx, size); + + return err; +} + +int mipi_dsi_dcs_read(MIPI_DSI_Type *ptr, uint8_t channel, uint8_t cmd, void *data, uint16_t len) +{ + struct mipi_dsi_msg msg = { + .channel = channel, + .type = MIPI_DSI_DCS_READ, + .tx_buf = &cmd, + .tx_len = 1, + .rx_buf = data, + .rx_len = len + }; + + return mipi_dsi_lp_cmd_transfer(ptr, &msg); +} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_dsi_phy_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_dsi_phy_drv.c new file mode 100644 index 00000000000..e07f6568757 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_dsi_phy_drv.c @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_mipi_dsi_phy_drv.h" + +typedef struct mipi_phy_clk_reg { + uint32_t rate; /*!< rate[2:0] */ + uint32_t pll_div; /*!< pll_div[14:0] */ +} mipi_phy_clk_reg_t; + +#define MIPI_DSI_PHY_RATE_MAX 4 +#define MIPI_DSI_PHY_REFCLK_FREQ_MHZ 24UL +#define MIPI_DSI_PHY_VCO_FREQ_MAX 4000UL +#define MIPI_DSI_PHY_PHY_VCO_FREQ_MIN 1600UL + +hpm_stat_t mipi_pll_get_cfg(uint32_t lane_mbps, mipi_phy_clk_reg_t *reg) +{ + uint32_t fvco_freq_mhz = lane_mbps; + uint32_t fvco_fraction_freq_mhz; + uint32_t rate = 0; + uint32_t pll_div_integer; /*pll_div[14:10]*/ + uint32_t pll_div_fraction; /*pll_div[9:0]*/ + + while (fvco_freq_mhz < MIPI_DSI_PHY_PHY_VCO_FREQ_MIN) { + rate++; + fvco_freq_mhz = lane_mbps * (1< 4) { + return status_invalid_argument; + } + + pll_div_integer = fvco_freq_mhz / 8 / MIPI_DSI_PHY_REFCLK_FREQ_MHZ; + fvco_fraction_freq_mhz = fvco_freq_mhz - (pll_div_integer * 8 * MIPI_DSI_PHY_REFCLK_FREQ_MHZ); + pll_div_fraction = (fvco_fraction_freq_mhz * 1024 + (8 * MIPI_DSI_PHY_REFCLK_FREQ_MHZ) / 2) /\ + (8 * MIPI_DSI_PHY_REFCLK_FREQ_MHZ); + + reg->rate = rate; + reg->pll_div = pll_div_integer<<10 | pll_div_fraction; + + return status_success; +} + +static bool mipi_dsi_phy_pll_init(MIPI_DSI_PHY_Type *ptr, uint32_t lane_mbps) +{ + hpm_stat_t state; + mipi_phy_clk_reg_t reg; + state = mipi_pll_get_cfg(lane_mbps, ®); + if (state == status_invalid_argument) + return false; + + + ptr->PLL_CTRL_PARA0 = (HPM_MIPI_DSI_PHY0->PLL_CTRL_PARA0 &\ + ~(MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_MASK | + MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_MASK | + MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_MASK)) | + MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_SET(reg.rate) | + MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_SET(0) | + MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_SET(reg.pll_div); + return true; +} + +void mipi_dsi_phy_init(MIPI_DSI_PHY_Type *ptr, mipi_dsi_phy_config_t *cfg) +{ + uint32_t byteclk_period_ps = 1000000u / (cfg->lane_mbps / 8); + uint32_t ui_ps = 1000000u / cfg->lane_mbps; + + ptr->TEST_PARA0 |= 1u<<3; + mipi_dsi_phy_pll_init(ptr, cfg->lane_mbps); + ptr->MISC_PARA = (ptr->MISC_PARA & ~(MIPI_DSI_PHY_MISC_PARA_LANE_NUM_MASK)) | + MIPI_DSI_PHY_MISC_PARA_LANE_NUM_SET(cfg->lanes - 1); + + uint32_t tlpx_ps = 50 * 1000; /* min: 50ns */ + ptr->COMMON_PARA0 = HPM_DIV_ROUND_UP(tlpx_ps, byteclk_period_ps) - 1; + + uint32_t tclk_prepare_ps = (38 + 95) * 1000 / 2; /* min: 38ns, max: 95ns */ + uint32_t tclk_zero_ps = 300 * 1000 - tclk_prepare_ps; /* min: 300ns */ + uint32_t tclk_pre_ps = 8* ui_ps; /* min: 8 * UI */ + uint32_t t_clk_post_ps = 60 * 1000 + 52 * ui_ps; /* min: 60ns + 52 * UI */ + uint32_t t_clk_trail_ps = 60 * 1000; /* min: 60ns */ + uint32_t t_hs_exit_ps = 100 * 1000; /* min: 100ns */ + + ptr->CLANE_PARA2 = MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_SET(HPM_DIV_ROUND_UP(tclk_prepare_ps, byteclk_period_ps) - 1) | + MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_SET(HPM_DIV_ROUND_UP(tclk_zero_ps, byteclk_period_ps) - 1) | + MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_SET(HPM_DIV_ROUND_UP(tclk_pre_ps, byteclk_period_ps) - 1); + + ptr->CLANE_PARA3 = MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_SET(HPM_DIV_ROUND_UP(t_clk_post_ps, byteclk_period_ps) - 1) | + MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_SET(HPM_DIV_ROUND_UP(t_clk_trail_ps, byteclk_period_ps) - 1); + + + uint32_t dlane0_para2; + uint32_t ths_prepare_ps = (40 + 85) / 2 * 1000 + (4 + 6) / 2 * ui_ps; /* min: 40ns + 4 * UI, max: 85ns + 6 * UI */ + uint32_t ths_zero_ps = 145 * 1000 + 10 * ui_ps - ths_prepare_ps; /* min: 145ns + 10 * UI */ + uint32_t ths_trail_ps0 = 8 * ui_ps; + uint32_t ths_trail_ps1 = 60 * 1000 * 4 * ui_ps; + uint32_t ths_trail_ps = ths_trail_ps0 > ths_trail_ps1 ? ths_trail_ps0 : ths_trail_ps1; + + dlane0_para2 = MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_SET(HPM_DIV_ROUND_UP(ths_prepare_ps, byteclk_period_ps) - 1) | + MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_SET(HPM_DIV_ROUND_UP(ths_zero_ps, byteclk_period_ps) - 1) | + MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_SET(HPM_DIV_ROUND_UP(ths_trail_ps, byteclk_period_ps) - 1) | + MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_SET(HPM_DIV_ROUND_UP(t_hs_exit_ps, byteclk_period_ps) - 1); + + ptr->DLANE0_PARA2 = dlane0_para2; + ptr->DLANE1_PARA2 = dlane0_para2; + ptr->DLANE2_PARA2 = dlane0_para2; + ptr->DLANE3_PARA2 = dlane0_para2; + + uint32_t ta_go_ps = 4 * tlpx_ps; /* 4 * Tlpx */ + uint32_t ta_sure_ps = tlpx_ps; /* min: Tlpx, max: 2 * Tlpx */ + uint32_t ta_get_ps = 5 * tlpx_ps; /* 4 * Tlpx */ + + ptr->DLANE0_PARA4 = MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_SET(HPM_DIV_ROUND_UP(ta_go_ps, byteclk_period_ps) - 1) | + MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_SET(HPM_DIV_ROUND_UP(ta_sure_ps, byteclk_period_ps) - 1) | + MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_SET(HPM_DIV_ROUND_UP(ta_get_ps, byteclk_period_ps) - 1); + +} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mmc_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mmc_drv.c new file mode 100644 index 00000000000..41d7bd83e5c --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mmc_drv.c @@ -0,0 +1,299 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_mmc_drv.h" + +void mmc_track_config_pos_mode(MMC_Type *base, mmc_track_pos_mode_t *mode) +{ + if (mode->discrete_pos_mode) { + base->CR |= MMC_CR_DISCRETETRC_MASK; + base->DISCRETECFG0 = MMC_DISCRETECFG0_POSMAX_SET(mode->discrete_line); + uint32_t inv_line = (uint32_t)(100000000UL / mode->discrete_line); + base->DISCRETECFG1 = MMC_DISCRETECFG1_INV_POSMAX_SET(inv_line); + } else { + base->CR &= ~MMC_CR_DISCRETETRC_MASK; + base->DISCRETECFG1 = MMC_DISCRETECFG1_INV_POSMAX_SET(mode->continuous_step_thr); + base->CONTCFG0 = MMC_CONTCFG0_HALF_CIRC_THETA_SET(mode->continuous_circ_thr); + } + + base->OOSYNC_THETA_THR = MMC_OOSYNC_THETA_THR_VAL_SET(mode->oosync_theta_thr); +} + +void mmc_track_get_default_mode_config(MMC_Type *base, mmc_track_mode_t *config) +{ + (void) base; + config->force_accel_to_zero = false; + config->en_ms_coef = false; + config->open_loop_mode = false; + config->pos_16bit_type = false; + config->sync_new_pos = false; + + config->pos_mode.discrete_pos_mode = false; + config->pos_mode.discrete_line = 0x10000; + config->pos_mode.continuous_step_thr = 0x1000000; + config->pos_mode.continuous_circ_thr = 0x1000000; + config->pos_mode.oosync_theta_thr = 0x1000000; +} + +void mmc_track_config_mode(MMC_Type *base, mmc_track_mode_t *config) +{ + base->CR &= ~(MMC_CR_FRCACCELZERO_MASK + | MMC_CR_MS_COEF_EN_MASK + | MMC_CR_OPEN_LOOP_MODE_MASK + | MMC_CR_POS_TYPE_MASK + | MMC_CR_ADJOP_MASK); + + base->CR |= MMC_CR_FRCACCELZERO_SET(config->force_accel_to_zero) + | MMC_CR_MS_COEF_EN_SET(config->en_ms_coef) + | MMC_CR_OPEN_LOOP_MODE_SET(config->open_loop_mode) + | MMC_CR_POS_TYPE_SET(config->pos_16bit_type) + | MMC_CR_ADJOP_SET(config->sync_new_pos); + + mmc_track_config_pos_mode(base, &config->pos_mode); +} + +void mmc_get_default_pos_or_delta_pos_para(MMC_Type *base, mmc_pos_or_delta_pos_input_t *para) +{ + (void) base; + para->pos_time = 0; + para->position = 0; + para->revolution = 0; + para->speed = 0; + para->accel = 0; + para->cmd_mask = mmc_pos_update_all; + para->trigger = mmc_pos_update_by_timestamp; +} + +void mmc_track_config_pos_para(MMC_Type *base, mmc_pos_or_delta_pos_input_t *para) +{ + /* speed and accel has 19bit decimal */ + int32_t speed = (int32_t)(para->speed * (1 << 19U)); + int32_t accel = (int32_t)(para->accel * (1 << 19U)); + + base->INI_SPEED = speed; + base->INI_ACCEL = accel; + base->INI_POS = para->position; + base->INI_REV = para->revolution; + base->INI_POS_TIME = para->pos_time; + + base->CR &= ~(MMC_CR_INI_POS_TRG_TYPE_MASK | MMC_CR_INI_POS_CMD_MSK_MASK | MMC_CR_INI_POS_REQ_MASK); + base->CR |= MMC_CR_INI_POS_TRG_TYPE_SET((para->trigger)) + | MMC_CR_INI_POS_CMD_MSK_SET(para->cmd_mask) + | MMC_CR_INI_POS_REQ_MASK; +} + +void mmc_track_config_delta_para(MMC_Type *base, mmc_pos_or_delta_pos_input_t *para) +{ + int32_t speed = (int32_t)(para->speed * (1 << 19U)); + int32_t accel = (int32_t)(para->accel * (1 << 19U)); + + base->INI_DELTA_SPEED = speed; + base->INI_DELTA_ACCEL = accel; + base->INI_DELTA_POS = para->position; + base->INI_DELTA_REV = para->revolution; + base->INI_DELTA_POS_TIME = para->pos_time; + + base->CR &= ~(MMC_CR_INI_DELTA_POS_TRG_TYPE_MASK | MMC_CR_INI_DELTA_POS_CMD_MSK_MASK | MMC_CR_INI_DELTA_POS_REQ_MASK); + base->CR |= MMC_CR_INI_DELTA_POS_TRG_TYPE_SET((para->trigger)) + | MMC_CR_INI_DELTA_POS_CMD_MSK_SET(para->cmd_mask) + | MMC_CR_INI_DELTA_POS_REQ_MASK; +} + +void mmc_track_config_coef_para(MMC_Type *base, mmc_coef_input_t *para) +{ + int32_t coef_p = (int32_t)(para->coef_p * (1 << 15U)); + int32_t coef_i = (int32_t)(para->coef_i * (1 << 21U)); + int32_t coef_a = (int32_t)(para->coef_a * (1 << 19U)); + + base->INI_PCOEF = coef_p; + base->INI_ICOEF = coef_i; + base->INI_ACOEF = coef_a; + base->INI_COEF_TIME = para->coef_time; + + base->CR &= ~(MMC_CR_INI_COEFS_CMD_MSK_MASK | MMC_CR_INI_COEFS_CMD_MASK); + base->CR |= MMC_CR_INI_COEFS_CMD_MSK_SET(para->cmd_mask) + | MMC_CR_INI_COEFS_CMD_MASK; +} + +void mmc_track_config_coef_trig(MMC_Type *base, uint8_t index, mmc_coef_trig_config_t *config) +{ + int32_t coef_p = (int32_t)(config->coef_p * (1 << 15U)); + int32_t coef_i = (int32_t)(config->coef_i * (1 << 21U)); + int32_t coef_a = (int32_t)(config->coef_a * (1 << 19U)); + + base->COEF_TRG_CFG[index].P = coef_p; + base->COEF_TRG_CFG[index].I = coef_i; + base->COEF_TRG_CFG[index].A = coef_a; + base->COEF_TRG_CFG[index].TIME = config->hold_time; + base->COEF_TRG_CFG[index].ERR_THR = config->err_thr; +} + +void mmc_track_get_result(MMC_Type *base, mmc_pos_out_t *pos_out, mmc_coef_out_t *coef_out) +{ + /* mmc_track_enable_shadow_read(base); */ + + base->CR |= MMC_CR_SHADOW_RD_REQ_MASK; + while ((base->CR & MMC_CR_SHADOW_RD_REQ_MASK) == MMC_CR_SHADOW_RD_REQ_MASK) { + } + + if (pos_out != NULL) { + pos_out->time = base->ESTM_TIM; + pos_out->position = base->ESTM_POS; + pos_out->revolution = (int32_t)base->ESTM_REV; + + int32_t speed = base->ESTM_SPEED; + int32_t accel = base->ESTM_ACCEL; + + pos_out->speed = (double)speed / (1 << 19U); + pos_out->accel = (double)accel / (1 << 19U); + } + + if (coef_out != NULL) { + int32_t coef_p = base->CUR_PCOEF; + int32_t coef_i = base->CUR_ICOEF; + int32_t coef_a = base->CUR_ACOEF; + + coef_out->coef_p = (double)coef_p / (1 << 15U); + coef_out->coef_i = (double)coef_i / (1 << 21U); + coef_out->coef_a = (double)coef_a / (1 << 19U); + } +} + + +void mmc_pred_get_default_mode_config(MMC_Type *base, mmc_pred_mode_t *config) +{ + (void) base; + config->speed_trig_int = false; + config->position_trig_int = false; + config->delta_pos_done_trig_int = false; + + + config->open_loop_mode = false; + config->pred_mode = 0; + config->not_first_pred_trig_type = 0; + config->first_pred_trig_type = 0; +} + +void mmc_pred_config_mode(MMC_Type *base, uint8_t index, mmc_pred_mode_t *config) +{ + base->BR[index].BR_CTRL &= ~(MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_MASK + | MMC_BR_BR_CTRL_POS_TRG_VALID_IE_MASK + | MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_MASK + | MMC_BR_BR_CTRL_OPEN_LOOP_MODE_MASK + | MMC_BR_BR_CTRL_PRED_MODE_MASK + | MMC_BR_BR_CTRL_NF_TRG_TYPE_MASK + | MMC_BR_BR_CTRL_F_TRG_TYPE_MASK); + + base->BR[index].BR_CTRL |= MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_SET(config->speed_trig_int) + | MMC_BR_BR_CTRL_POS_TRG_VALID_IE_SET(config->position_trig_int) + | MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_SET(config->delta_pos_done_trig_int) + | MMC_BR_BR_CTRL_OPEN_LOOP_MODE_SET(config->open_loop_mode) + | MMC_BR_BR_CTRL_PRED_MODE_SET(config->pred_mode) + | MMC_BR_BR_CTRL_NF_TRG_TYPE_SET(config->not_first_pred_trig_type) + | MMC_BR_BR_CTRL_F_TRG_TYPE_SET(config->first_pred_trig_type); +} + +void mmc_pred_config_pos_para(MMC_Type *base, uint8_t index, mmc_pos_or_delta_pos_input_t *para, bool req_reload) +{ + /* speed and accel has 19bit decimal */ + int32_t speed = (int32_t)(para->speed * (1 << 19U)); + int32_t accel = (int32_t)(para->accel * (1 << 19U)); + + base->BR[index].BR_INI_SPEED = speed; + base->BR[index].BR_INI_ACCEL = accel; + base->BR[index].BR_INI_POS = para->position; + base->BR[index].BR_INI_REV = para->revolution; + base->BR[index].BR_INI_POS_TIME = para->pos_time; + + base->BR[index].BR_CTRL &= ~(MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_MASK | MMC_BR_BR_CTRL_INI_POS_CMD_MSK_MASK); + base->BR[index].BR_CTRL |= MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_SET((para->trigger)) + | MMC_BR_BR_CTRL_INI_POS_CMD_MSK_SET(para->cmd_mask); + + if (req_reload) { + base->CR |= (1U << (MMC_CR_INI_BR0_POS_REQ_SHIFT - index)); + } +} + +void mmc_pred_config_delta_para(MMC_Type *base, uint8_t index, mmc_pos_or_delta_pos_input_t *para) +{ + int32_t speed = (int32_t)(para->speed * (1 << 19U)); + int32_t accel = (int32_t)(para->accel * (1 << 19U)); + + base->BR[index].BR_INI_DELTA_SPEED = speed; + base->BR[index].BR_INI_DELTA_ACCEL = accel; + base->BR[index].BR_INI_DELTA_POS = para->position; + base->BR[index].BR_INI_DELTA_REV = para->revolution; + base->BR[index].BR_INI_DELTA_POS_TIME = para->pos_time; + + base->BR[index].BR_CTRL &= ~(MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_MASK + | MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_MASK + | MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_MASK); + + base->BR[index].BR_CTRL |= MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_SET(para->trigger) + | MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_SET(para->cmd_mask) + | MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_MASK; +} + +/* 不需要shadow吗 */ +void mmc_pred_get_result(MMC_Type *base, uint8_t index, mmc_pos_out_t *pos_out) +{ + pos_out->time = base->BR[index].BR_CUR_POS_TIME; + pos_out->position = base->BR[index].BR_CUR_POS; + pos_out->revolution = (int32_t)base->BR[index].BR_CUR_REV; + + int32_t speed = base->BR[index].BR_CUR_SPEED; + int32_t accel = base->BR[index].BR_CUR_ACCEL; + + pos_out->speed = (double)speed / (1 << 19U); + pos_out->accel = (double)accel / (1 << 19U); +} + +void mmc_pred_config_period_time(MMC_Type *base, uint8_t index, mmc_pred_period_time_t *time) +{ + base->BR[index].BR_TIMEOFF = time->offset_time; + base->BR[index].BR_TRG_PERIOD = time->period_time; + base->BR[index].BR_TRG_F_TIME = time->first_time; +} + +void mmc_pred_config_position_trig(MMC_Type *base, uint8_t index, mmc_pos_trig_t *trig) +{ + base->BR[index].BR_TRG_POS_THR = trig->position_thr; + base->BR[index].BR_TRG_REV_THR = trig->revolution_thr; + + base->BR[index].BR_TRG_POS_CFG = MMC_BR_BR_TRG_POS_CFG_EDGE_SET(trig->less_than) + | MMC_BR_BR_TRG_POS_CFG_EN_SET(trig->enable); +} + +void mmc_pred_config_speed_trig(MMC_Type *base, uint8_t index, mmc_speed_trig_t *trig) +{ + /* speed has 19bit decimal */ + int32_t speed = (int32_t)(trig->speed_thr * (1 << 19U)); + + base->BR[index].BR_TRG_SPEED_THR = speed; + base->BR[index].BR_TRG_SPEED_CFG = MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_SET(trig->absolute_compare) + | MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_SET(trig->less_than) + | MMC_BR_BR_TRG_SPEED_CFG_EN_SET(trig->enable); +} + +void mmc_track_config_position_trig(MMC_Type *base, mmc_pos_trig_t *trig) +{ + base->POS_TRG_POS_THR = trig->position_thr; + base->POS_TRG_REV_THR = trig->revolution_thr; + + base->POS_TRG_CFG = MMC_POS_TRG_CFG_EDGE_SET(trig->less_than) + | MMC_POS_TRG_CFG_EN_SET(trig->enable); +} + +void mmc_track_config_speed_trig(MMC_Type *base, mmc_speed_trig_t *trig) +{ + /* speed has 19bit decimal */ + int32_t speed = (int32_t)(trig->speed_thr * (1 << 19U)); + base->SPEED_TRG_THR = speed; + base->SPEED_TRG_CFG = MMC_SPEED_TRG_CFG_COMP_TYPE_SET(trig->absolute_compare) + | MMC_SPEED_TRG_CFG_EDGE_SET(trig->less_than) + | MMC_SPEED_TRG_CFG_EN_SET(trig->enable); +} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_opamp_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_opamp_drv.c new file mode 100644 index 00000000000..4f41e295162 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_opamp_drv.c @@ -0,0 +1,218 @@ +#include "hpm_opamp_drv.h" + +hpm_stat_t opamp_init(OPAMP_Type *opamp, opamp_cfg_t *cfg) +{ + opamp_disable(opamp); + opamp->CTRL0 = 0; + opamp_inn_pad_select(opamp, cfg->negative_input_pin); + opamp_inp_pad_select(opamp, cfg->positive_input_pin); + opamp_gain_select(opamp, cfg->gain); + opamp_miller_cap_select(opamp, cfg->miller_cap); + if (cfg->enable_phase_margin_cap) { + opamp_phase_margin_cap_enable(opamp); + } else { + opamp_phase_margin_cap_disable(opamp); + } + switch (cfg->mode) { + case mode_follow: + if ((cfg->positive_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + if ((cfg->negative_input_pin & 0x04) == 0) { + return status_invalid_argument; + } + opamp_disconnect_vssa(opamp); + opamp_phase_margin_cap_enable(opamp); + opamp_mode_set(opamp, OPAMP_MODE_FOLLOW_KEY); + break; + case mode_invert_intern_vol: + if ((cfg->positive_input_pin & 0x04) == 0) { + return status_invalid_argument; + } + if ((cfg->negative_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + opamp_connect_vssa(opamp); + opamp_phase_margin_cap_disable(opamp); + opamp_mode_set(opamp, OPAMP_MODE_INVERT_INDEX0_KEY); + break; + case mode_invert_extern_vol: + if ((cfg->positive_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + if ((cfg->negative_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + if (cfg->enable_extern_filter_cap) { + opamp_mode_set(opamp, OPAMP_MODE_INVERT_INDEX1_KEY); + } else { + opamp_mode_set(opamp, OPAMP_MODE_INVERT_INDEX0_KEY); + } + break; + case mode_invert_dac_vol: + opamp_inp_pad_select(opamp, 0x02); + if ((cfg->negative_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + opamp_connect_vssa(opamp); + opamp_mode_set(opamp, OPAMP_MODE_INVERT_INDEX0_KEY); + break; + case mode_non_invert_gnd_vol: + if ((cfg->positive_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + opamp_connect_vssa(opamp); + if (!cfg->enable_extern_filter_cap) { + if ((cfg->negative_input_pin & 0x04) == 0) { + return status_invalid_argument; + } + opamp_mode_set(opamp, OPAMP_MODE_NON_INVERT_INDEX0_KEY); + } else { + if ((cfg->negative_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + opamp_mode_set(opamp, OPAMP_MODE_NON_INVERT_INDEX2_KEY); + } + break; + case mode_non_invert_extern_vol: + if ((cfg->positive_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + if ((cfg->negative_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + opamp_connect_vssa(opamp); + if (!cfg->enable_extern_filter_cap) { + opamp_mode_set(opamp, OPAMP_MODE_NON_INVERT_INDEX1_KEY); + } else { + opamp_mode_set(opamp, OPAMP_MODE_NON_INVERT_INDEX3_KEY); + } + break; + case mode_non_invert_dac_vol: + if ((cfg->positive_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + opamp_inn_pad_select(opamp, 0x02); + opamp_connect_vssa(opamp); + opamp_mode_set(opamp, OPAMP_MODE_NON_INVERT_INDEX4_KEY); + break; + case mode_user: + opamp_mode_set(opamp, OPAMP_MODE_USER_DEFINE_KEY); + break; + default: + return status_invalid_argument; + break; + } + return status_success; +} + + +hpm_stat_t opamp_set_preset_cfg(OPAMP_Type *opamp, uint8_t preset_chn, opamp_cfg_t *cfg) +{ + if (preset_chn > OPAMP_SOC_HAS_MAX_PRESET_CHN_NUM) { + return status_invalid_argument; + } + opamp->CFG[preset_chn].CFG0 = 0; + opamp->CFG[preset_chn].CFG1 = 0; + opamp_preset_inn_pad_select(opamp, preset_chn, cfg->negative_input_pin); + opamp_preset_inp_pad_select(opamp, preset_chn, cfg->positive_input_pin); + opamp_preset_gain_select(opamp, preset_chn, cfg->gain); + opamp_preset_miller_cap_select(opamp, preset_chn, cfg->miller_cap); + if (cfg->enable_phase_margin_cap) { + opamp_preset_phase_margin_cap_enable(opamp, preset_chn); + } else { + opamp_preset_phase_margin_cap_disable(opamp, preset_chn); + } + switch (cfg->mode) { + case mode_follow: + if ((cfg->positive_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + if ((cfg->negative_input_pin & 0x04) == 0) { + return status_invalid_argument; + } + opamp_preset_disconnect_vssa(opamp, preset_chn); + opamp_preset_phase_margin_cap_enable(opamp, preset_chn); + opamp_preset_mode_set(opamp, preset_chn, OPAMP_MODE_FOLLOW_KEY); + break; + case mode_invert_intern_vol: + if ((cfg->positive_input_pin & 0x04) == 0) { + return status_invalid_argument; + } + if ((cfg->negative_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + opamp_preset_disconnect_vssa(opamp, preset_chn); + opamp_preset_phase_margin_cap_disable(opamp, preset_chn); + opamp_preset_mode_set(opamp, preset_chn, OPAMP_MODE_INVERT_INDEX0_KEY); + break; + case mode_invert_extern_vol: + if ((cfg->positive_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + if ((cfg->negative_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + if (cfg->enable_extern_filter_cap) { + opamp_preset_mode_set(opamp, preset_chn, OPAMP_MODE_INVERT_INDEX1_KEY); + } else { + opamp_preset_mode_set(opamp, preset_chn, OPAMP_MODE_INVERT_INDEX0_KEY); + } + break; + case mode_invert_dac_vol: + opamp_preset_inp_pad_select(opamp, preset_chn, 0x02); + if ((cfg->negative_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + opamp_preset_disconnect_vssa(opamp, preset_chn); + opamp_preset_mode_set(opamp, preset_chn, OPAMP_MODE_INVERT_INDEX0_KEY); + break; + case mode_non_invert_gnd_vol: + if ((cfg->positive_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + opamp_preset_disconnect_vssa(opamp, preset_chn); + if (!cfg->enable_extern_filter_cap) { + if ((cfg->negative_input_pin & 0x04) == 0) { + return status_invalid_argument; + } + opamp_preset_mode_set(opamp, preset_chn, OPAMP_MODE_NON_INVERT_INDEX0_KEY); + } else { + if ((cfg->negative_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + opamp_preset_mode_set(opamp, preset_chn, OPAMP_MODE_NON_INVERT_INDEX2_KEY); + } + break; + case mode_non_invert_extern_vol: + if ((cfg->positive_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + if ((cfg->negative_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + opamp_preset_disconnect_vssa(opamp, preset_chn); + if (!cfg->enable_extern_filter_cap) { + opamp_preset_mode_set(opamp, preset_chn, OPAMP_MODE_NON_INVERT_INDEX1_KEY); + } else { + opamp_preset_mode_set(opamp, preset_chn, OPAMP_MODE_NON_INVERT_INDEX3_KEY); + } + break; + case mode_non_invert_dac_vol: + if ((cfg->positive_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + opamp_preset_inn_pad_select(opamp, preset_chn, 0x02); + opamp_preset_disconnect_vssa(opamp, preset_chn); + opamp_preset_mode_set(opamp, preset_chn, OPAMP_MODE_NON_INVERT_INDEX4_KEY); + break; + case mode_user: + return status_success; + break; + default: + return status_invalid_argument; + break; + } + return status_success; +} + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pcfg_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pcfg_drv.c index d26825b4376..669649e9f24 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pcfg_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pcfg_drv.c @@ -17,8 +17,7 @@ hpm_stat_t pcfg_ldo1p1_set_voltage(PCFG_Type *ptr, uint16_t mv) || (mv > PCFG_SOC_LDO1P1_MAX_VOLTAGE_IN_MV)) { return status_pcfg_ldo_out_of_range; } - ptr->LDO1P1 &= ~PCFG_LDO1P1_ENABLE_MASK; - ptr->LDO1P1 = PCFG_LDO1P1_ENABLE_MASK | PCFG_LDO1P1_VOLT_SET(mv); + ptr->LDO1P1 = (ptr->LDO1P1 & ~PCFG_LDO1P1_VOLT_MASK) | PCFG_LDO1P1_VOLT_SET(mv); return status_success; } diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdm_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdm_drv.c index 0b2a4fc48f1..c712f4fce42 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdm_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdm_drv.c @@ -9,6 +9,7 @@ void pdm_get_default_config(PDM_Type *ptr, pdm_config_t *config) { + (void) ptr; config->sof_at_ref_clk_falling_edge = true; config->bypass_pdm_clk_div = false; config->enable_pdm_clk_out = true; diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdma_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdma_drv.c index cb156fa71a4..5980406a66a 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdma_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdma_drv.c @@ -57,6 +57,7 @@ void pdma_enable_irq(PDMA_Type *ptr, uint32_t mask, bool enable) void pdma_get_default_config(PDMA_Type *ptr, pdma_config_t *config, display_pixel_format_t pixel_format) { + (void) ptr; config->block_size = pdma_blocksize_16x16; config->enable_plane = pdma_plane_src; @@ -73,6 +74,7 @@ void pdma_get_default_config(PDMA_Type *ptr, pdma_config_t *config, display_pixe void pdma_get_default_plane_config(PDMA_Type *ptr, pdma_plane_config_t *config, display_pixel_format_t pixel_format) { + (void) ptr; config->swap_byte3_byte1 = false; config->byteorder = display_byteorder_a3a2a1a0; config->use_background_as_clear = true; @@ -112,6 +114,7 @@ void pdma_get_default_plane_config(PDMA_Type *ptr, pdma_plane_config_t *config, void pdma_get_default_yuv2rgb_coef_config(PDMA_Type *ptr, display_yuv2rgb_coef_t *yuv2rgb_coef, display_pixel_format_t source_format) { + (void) ptr; /* Two plane share one YUV2RGB_COEF, not support one plane format is yuv422 and another is ycbcr422 */ switch (source_format) { @@ -147,6 +150,7 @@ void pdma_get_default_yuv2rgb_coef_config(PDMA_Type *ptr, display_yuv2rgb_coef_t void pdma_get_default_output_config(PDMA_Type *ptr, pdma_output_config_t *config, display_pixel_format_t pixel_format) { + (void) ptr; uint8_t i; config->alphablend.dst_alpha = 0x0; config->alphablend.src_alpha = 0x0; @@ -239,10 +243,11 @@ void pdma_init(PDMA_Type *ptr, pdma_config_t *config) mask = 0; break; } - +#if defined(PDMA_SOC_SUPPORT_BS16) && (PDMA_SOC_SUPPORT_BS16 == 1) if (config->block_size == pdma_blocksize_16x16) { mask |= PDMA_CTRL_BS16_MASK; } +#endif ptr->CTRL = PDMA_CTRL_PACK_DIR_SET(config->byteorder) | mask; } @@ -378,12 +383,12 @@ void pdma_config_output(PDMA_Type *ptr, pdma_output_config_t *config) | PDMA_OUT_LRC_Y_SET(config->height); ptr->OUT_PS[0].ULC = PDMA_OUT_PS_ULC_X_SET(config->plane[0].x) | PDMA_OUT_PS_ULC_Y_SET(config->plane[0].y); - ptr->OUT_PS[0].LRC = PDMA_OUT_PS_LRC_X_SET(config->plane[0].width) - | PDMA_OUT_PS_LRC_Y_SET(config->plane[0].height); + ptr->OUT_PS[0].LRC = PDMA_OUT_PS_LRC_X_SET(config->plane[0].x + config->plane[0].width - 1) + | PDMA_OUT_PS_LRC_Y_SET(config->plane[0].y + config->plane[0].height - 1); ptr->OUT_PS[1].ULC = PDMA_OUT_PS_ULC_X_SET(config->plane[1].x) | PDMA_OUT_PS_ULC_Y_SET(config->plane[1].y); - ptr->OUT_PS[1].LRC = PDMA_OUT_PS_LRC_X_SET(config->plane[1].width) - | PDMA_OUT_PS_LRC_Y_SET(config->plane[1].height); + ptr->OUT_PS[1].LRC = PDMA_OUT_PS_LRC_X_SET(config->plane[1].x + config->plane[1].width - 1) + | PDMA_OUT_PS_LRC_Y_SET(config->plane[1].y + config->plane[1].height - 1); ptr->OUT_CTRL = PDMA_OUT_CTRL_DSTALPHA_SET(config->alphablend.dst_alpha) | PDMA_OUT_CTRL_SRCALPHA_SET(config->alphablend.src_alpha) | PDMA_OUT_CTRL_DSTALPHA_OP_SET(config->alphablend.dst_alpha_op) @@ -785,3 +790,137 @@ hpm_stat_t pdma_scale(PDMA_Type *ptr, return status_success; } + +typedef struct pdma_buf2plane_format { + display_pixel_format_t format; + display_byteorder_t byteorder; +} pdma_buf2plane_format_t; + +static const pdma_buf2plane_format_t plane_format_tab[display_buf_format_max] = { + [display_buf_format_argb8888] = {display_pixel_format_argb8888, display_byteorder_a3a2a1a0}, + [display_buf_format_bgra8888] = {display_pixel_format_argb8888, display_byteorder_a0a1a2a3}, + [display_buf_format_rgb565] = {display_pixel_format_rgb565, display_byteorder_a3a2a1a0}, + [display_buf_format_rgb565_swap] = {display_pixel_format_rgb565, display_byteorder_a2a3a0a1}, + [display_buf_format_yuyv] = {display_pixel_format_ycbcr422, display_byteorder_a3a2a1a0}, + [display_buf_format_uyvy] = {display_pixel_format_ycbcr422, display_byteorder_a2a3a0a1}, + [display_buf_format_y8] = {display_pixel_format_y8, display_byteorder_a3a2a1a0}, +}; + +static const pdma_buf2plane_format_t out_format_tab[display_buf_format_max] = { + [display_buf_format_argb8888] = {display_pixel_format_argb8888, display_byteorder_a3a2a1a0}, + [display_buf_format_bgra8888] = {display_pixel_format_argb8888, display_byteorder_a0a1a2a3}, + [display_buf_format_rgb565] = {display_pixel_format_rgb565, display_byteorder_a3a2a1a0}, + [display_buf_format_rgb565_swap] = {display_pixel_format_rgb565, display_byteorder_a2a3a0a1}, + [display_buf_format_yuyv] = {display_pixel_format_ycbcr422, display_byteorder_a2a3a0a1}, + [display_buf_format_uyvy] = {display_pixel_format_ycbcr422, display_byteorder_a3a2a1a0}, + [display_buf_format_y8] = {display_pixel_format_y8, display_byteorder_a3a2a1a0}, +}; + +void pdma_get_default_blit_option(pdma_blit_option_t *op) +{ + op->blend = display_alphablend_mode_src_over; + op->flip = pdma_flip_none; + op->rotate = pdma_rotate_0_degree; + op->scale.x = 1.0; + op->scale.y = 1.0; + op->translate.x = 0; + op->translate.y = 0; +} + +hpm_stat_t pdma_blit_ex(PDMA_Type *ptr, + display_buf_t *dst, + display_buf_t *src, + pdma_blit_option_t *op, + bool wait, uint32_t *status) +{ + if ((!dst) || (!src) || (!src->buf) || (!dst->buf) || + (op->scale.x > 4096) || (op->scale.y > 4096) || + /* YUV422 requires width to be 2-pixel aligned */ + ((display_pixel_format_is_yuv_format(plane_format_tab[src->format].format)) && (src->width & 1)) || + ((display_pixel_format_is_yuv_format(plane_format_tab[dst->format].format)) && (dst->width & 1))) { + return status_invalid_argument; + } + + pdma_decimation_t x_dec; + pdma_decimation_t y_dec; + uint32_t x_scale; + uint32_t y_scale; + + pdma_config_t config; + pdma_plane_config_t plane_src; + pdma_plane_config_t plane_dst; + display_yuv2rgb_coef_t yuv2rgb_coef; + pdma_output_config_t output; + + pdma_calculate_scale(65536, (uint32_t)(65536 * op->scale.x), &x_dec, &x_scale); + pdma_calculate_scale(65536, (uint32_t)(65536 * op->scale.y), &y_dec, &y_scale); + + pdma_get_default_plane_config(ptr, &plane_src, plane_format_tab[src->format].format); + pdma_get_default_plane_config(ptr, &plane_dst, plane_format_tab[dst->format].format); + pdma_get_default_yuv2rgb_coef_config(ptr, &yuv2rgb_coef, plane_format_tab[src->format].format); + pdma_get_default_output_config(ptr, &output, out_format_tab[dst->format].format); + + config.enable_plane = pdma_plane_both; + config.block_size = pdma_blocksize_8x8; + config.byteorder = out_format_tab[dst->format].byteorder; + pdma_init(ptr, &config); + + plane_src.buffer = (uint32_t)src->buf; + plane_src.byteorder = plane_format_tab[src->format].byteorder; + plane_src.width = src->width; + plane_src.height = src->height; + plane_src.pitch = src->stride; + plane_src.x_scale = x_scale; + plane_src.x_dec = x_dec; + plane_src.y_scale = y_scale; + plane_src.y_dec = y_dec; + plane_src.background = 0x00000000; /* alpha must be 0 */ + plane_src.x_offset = PDMA_YUV_SCALE_DEFAULT_X_OFFSET; + plane_src.flip = op->flip; + plane_src.rotate = op->rotate; + + plane_dst.buffer = (uint32_t)dst->buf; + plane_dst.byteorder = plane_format_tab[dst->format].byteorder; + plane_dst.width = dst->width; + plane_dst.height = dst->height; + plane_dst.pitch = dst->stride; + pdma_config_planes(ptr, &plane_src, &plane_dst, &yuv2rgb_coef); + + output.buffer = plane_dst.buffer; + output.plane[pdma_plane_src].x = op->translate.x; + output.plane[pdma_plane_src].y = op->translate.y; + + /* + * aligned to lower right of dst window and non-overlapping area is filled by background of src. + * so alpha that background of src must be 0. + */ + output.plane[pdma_plane_src].width = dst->width - op->translate.x; + output.plane[pdma_plane_src].height = dst->height - op->translate.y; + + output.plane[pdma_plane_dst].x = 0; + output.plane[pdma_plane_dst].y = 0; + output.plane[pdma_plane_dst].width = plane_dst.width; + output.plane[pdma_plane_dst].height = plane_dst.height; + + output.alphablend.src_alpha = src->alpha.val; + output.alphablend.src_alpha_op = src->alpha.op; + output.alphablend.dst_alpha = dst->alpha.val; + output.alphablend.dst_alpha_op = dst->alpha.op; + output.alphablend.mode = op->blend; + + output.width = plane_dst.width; + output.height = plane_dst.height; + output.pitch = plane_dst.pitch; + + pdma_config_output(ptr, &output); + pdma_start(ptr); + if (wait) { + hpm_stat_t stat; + do { + stat = pdma_check_status(ptr, status); + } while ((stat != status_pdma_done) && (stat != status_pdma_error)); + pdma_stop(ptr); + return stat; + } + return status_success; +} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pixelmux_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pixelmux_drv.c new file mode 100644 index 00000000000..7bb5c6429e5 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pixelmux_drv.c @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_pixelmux_drv.h" + +void pixelmux_rgb_data_source_enable(pixelmux_rgb_select_t src) +{ + uint32_t reg_val = (HPM_PIXEL_MUX->PIXMUX & ~PIXELMUX_PIXMUX_RGB_SEL_MASK) | + PIXELMUX_PIXMUX_RGB_EN_MASK | PIXELMUX_PIXMUX_RGB_SEL_SET(src); + HPM_PIXEL_MUX->PIXMUX = reg_val; +} + +void pixelmux_rgb_data_source_disable(void) +{ + HPM_PIXEL_MUX->PIXMUX &= ~PIXELMUX_PIXMUX_RGB_SEL_MASK; +} + +void pixelmux_gwc1_data_source_enable(pixelmux_gwc1_select_t src) +{ + uint32_t reg_val = (HPM_PIXEL_MUX->PIXMUX & ~PIXELMUX_PIXMUX_GWC1_SEL_MASK) | + PIXELMUX_PIXMUX_GWC1_EN_MASK | PIXELMUX_PIXMUX_GWC1_SEL_SET(src); + HPM_PIXEL_MUX->PIXMUX = reg_val; +} + +void pixelmux_gwc1_data_source_disable(void) +{ + HPM_PIXEL_MUX->PIXMUX &= ~PIXELMUX_PIXMUX_GWC1_EN_MASK; +} + +void pixelmux_gwc0_data_source_enable(pixelmux_gwc0_select_t src) +{ + uint32_t reg_val = (HPM_PIXEL_MUX->PIXMUX & ~PIXELMUX_PIXMUX_GWC0_SEL_MASK) | + PIXELMUX_PIXMUX_GWC0_EN_MASK | PIXELMUX_PIXMUX_GWC0_SEL_SET(src); + HPM_PIXEL_MUX->PIXMUX = reg_val; +} + +void pixelmux_gwc0_data_source_disable(void) +{ + HPM_PIXEL_MUX->PIXMUX &= ~PIXELMUX_PIXMUX_GWC0_EN_MASK; +} + +void pixelmux_lvb_di1_data_source_enable(pixelmux_lvb_di1_select_t src) +{ + uint32_t reg_val = (HPM_PIXEL_MUX->PIXMUX & ~PIXELMUX_PIXMUX_LVB_DI1_SEL_MASK) | + PIXELMUX_PIXMUX_LVB_DI1_EN_MASK | PIXELMUX_PIXMUX_LVB_DI1_SEL_SET(src); + HPM_PIXEL_MUX->PIXMUX = reg_val; +} + +void pixelmux_lvb_di1_data_source_disable(void) +{ + HPM_PIXEL_MUX->PIXMUX &= ~PIXELMUX_PIXMUX_LVB_DI1_EN_MASK; +} + +void pixelmux_lvb_di0_data_source_enable(pixelmux_lvb_di0_select_t src) +{ + uint32_t reg_val = (HPM_PIXEL_MUX->PIXMUX & ~PIXELMUX_PIXMUX_LVB_DI0_SEL_MASK) | + PIXELMUX_PIXMUX_LVB_DI0_EN_MASK | PIXELMUX_PIXMUX_LVB_DI0_SEL_SET(src); + HPM_PIXEL_MUX->PIXMUX = reg_val; +} + +void pixelmux_lvb_di0_data_source_disable(void) +{ + HPM_PIXEL_MUX->PIXMUX &= ~PIXELMUX_PIXMUX_LVB_DI0_EN_MASK; +} + +void pixelmux_mipi_dsi1_data_source_enable(pixelmux_mipi_dsi1_select_t src) +{ + uint32_t reg_val = (HPM_PIXEL_MUX->PIXMUX & ~PIXELMUX_PIXMUX_DSI1_SEL_MASK) | + PIXELMUX_PIXMUX_DSI1_EN_MASK | PIXELMUX_PIXMUX_DSI1_SEL_SET(src); + HPM_PIXEL_MUX->PIXMUX = reg_val; +} + +void pixelmux_mipi_dsi1_data_source_disable(void) +{ + HPM_PIXEL_MUX->PIXMUX &= ~PIXELMUX_PIXMUX_DSI1_EN_MASK; +} + +void pixelmux_mipi_dsi0_data_source_enable(pixelmux_mipi_dsi0_select_t src) +{ + uint32_t reg_val = (HPM_PIXEL_MUX->PIXMUX & ~PIXELMUX_PIXMUX_DSI0_SEL_MASK) | + PIXELMUX_PIXMUX_DSI0_EN_MASK | PIXELMUX_PIXMUX_DSI0_SEL_SET(src); + HPM_PIXEL_MUX->PIXMUX = reg_val; +} + +void pixelmux_mipi_dsi0_data_source_disable(void) +{ + HPM_PIXEL_MUX->PIXMUX &= ~PIXELMUX_PIXMUX_DSI0_EN_MASK; +} + +void pixelmux_cam1_data_source_enable(pixelmux_cam1_select_t src) +{ + uint32_t reg_val = (HPM_PIXEL_MUX->PIXMUX & ~PIXELMUX_PIXMUX_CAM1_SEL_MASK) | + PIXELMUX_PIXMUX_CAM1_EN_MASK | PIXELMUX_PIXMUX_CAM1_SEL_SET(src); + HPM_PIXEL_MUX->PIXMUX = reg_val; +} + +void pixelmux_cam1_data_source_disable(void) +{ + HPM_PIXEL_MUX->PIXMUX &= ~PIXELMUX_PIXMUX_CAM1_EN_MASK; +} + +void pixelmux_cam0_data_source_enable(pixelmux_cam0_select_t src) +{ + uint32_t reg_val = (HPM_PIXEL_MUX->PIXMUX & ~PIXELMUX_PIXMUX_CAM0_SEL_MASK) | + PIXELMUX_PIXMUX_CAM0_EN_MASK | PIXELMUX_PIXMUX_CAM0_SEL_SET(src); + HPM_PIXEL_MUX->PIXMUX = reg_val; +} + +void pixelmux_cam0_data_source_disable(void) +{ + HPM_PIXEL_MUX->PIXMUX &= ~PIXELMUX_PIXMUX_CAM0_EN_MASK; +} + +hpm_stat_t pixelmux_lvds_phy_calc_pll_cfg(uint32_t pixel_freq_hz, bool is_split, lvds_phy_clk_param_t *param) +{ + uint32_t hsclk_freq_hz; + uint32_t data_rate_div4; + uint64_t fvco_freq_hz; + uint32_t fvco_fraction_freq_hz; + uint32_t lvds_rpck = is_split ? pixel_freq_hz / 2 : pixel_freq_hz; + uint32_t lane_data_rate_hz = lvds_rpck * 7; + uint32_t rate_lvds; + uint32_t pfd_freq_hz; + uint32_t pll_div_integer; /*pll_div[14:10]*/ + uint32_t pll_div_fraction; /*pll_div[9:0]*/ + int refclk_div; + + if (lvds_rpck / 16 > PIXELMUX_LVDS_TX_PHY_PFD_FREQ_MAX || + lvds_rpck < PIXELMUX_LVDS_TX_PHY_PFD_FREQ_MIN) { + return status_invalid_argument; + } + + if (lane_data_rate_hz < PIXELMUX_LVDS_TX_PHY_VCO_FREQ_MIN / (8 * 4) || + lane_data_rate_hz > PIXELMUX_LVDS_TX_PHY_DATA_LANE_FREQ_MAX) { + return status_invalid_argument; + } + + data_rate_div4 = 1; + if (lane_data_rate_hz > PIXELMUX_LVDS_TX_PHY_VCO_FREQ_MAX / 4) { + data_rate_div4 = 0; + } + + hsclk_freq_hz = data_rate_div4 ? lane_data_rate_hz * 4 : lane_data_rate_hz; + rate_lvds = 0; + fvco_freq_hz = 0; + while (rate_lvds <= 3) { + fvco_freq_hz = (uint64_t)hsclk_freq_hz * (1<= PIXELMUX_LVDS_TX_PHY_VCO_FREQ_MIN) { + break; + } + rate_lvds++; + } + + if (rate_lvds > 3 || fvco_freq_hz > PIXELMUX_LVDS_TX_PHY_VCO_FREQ_MAX) { + return status_invalid_argument; + } + + refclk_div = 15; + pfd_freq_hz = 0; + while (refclk_div >= 0) { + pfd_freq_hz = lvds_rpck / (refclk_div + 1); + if (pfd_freq_hz >= PIXELMUX_LVDS_TX_PHY_PFD_FREQ_MIN) { + break; + } + refclk_div--; + } + + if (refclk_div < 0 || pfd_freq_hz < PIXELMUX_LVDS_TX_PHY_PFD_FREQ_MIN) { + return status_invalid_argument; + } + + while (refclk_div >= 0 && pfd_freq_hz < PIXELMUX_LVDS_TX_PHY_PFD_FREQ_MAX) { + pfd_freq_hz = lvds_rpck / (refclk_div + 1); + if (fvco_freq_hz / 8 / pfd_freq_hz <= 23) { + break; + } + refclk_div--; + } + + if (refclk_div < 0 || pfd_freq_hz > PIXELMUX_LVDS_TX_PHY_PFD_FREQ_MAX || + (fvco_freq_hz / 8 / pfd_freq_hz) > 23 || (fvco_freq_hz / 8 / pfd_freq_hz) < 6) { + return status_invalid_argument; + } + + pll_div_integer = fvco_freq_hz / 8 / pfd_freq_hz; + fvco_fraction_freq_hz = fvco_freq_hz - pfd_freq_hz * pll_div_integer * 8; + pll_div_fraction = (fvco_fraction_freq_hz * 1024) / 8 / pfd_freq_hz; + + param->reg.rate_lvds = rate_lvds; + param->reg.data_rate_div4 = data_rate_div4; + param->reg.refclk_div = refclk_div; + param->reg.pll_div = pll_div_integer<<10 | pll_div_fraction; + param->fvco_freq_hz = fvco_freq_hz; + param->pfd_freq_hz = pfd_freq_hz; + param->lane_data_rate_hz = lane_data_rate_hz; + param->hsclk_freq_hz = hsclk_freq_hz; + + return status_success; +} + +void pixelmux_config_tx_phy0_mode(pixelmux_tx_phy_mode_t mode) +{ + HPM_PIXEL_MUX->GPR_WR_D2 = (HPM_PIXEL_MUX->GPR_WR_D2 & + ~PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_MASK) | + PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_SET(mode); +} + +void pixelmux_config_tx_phy1_mode(pixelmux_tx_phy_mode_t mode) +{ + HPM_PIXEL_MUX->GPR_WR_D5 = (HPM_PIXEL_MUX->GPR_WR_D5 & + ~PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_MASK) | + PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_SET(mode); +} + +void pixelmux_config_lvds_tx_phy0_clk(const lvds_phy_clk_reg_t *clk_reg) +{ + HPM_PIXEL_MUX->GPR_WR_D2 = (HPM_PIXEL_MUX->GPR_WR_D2 & + ~(PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_MASK | + PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_MASK | + PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_MASK | + PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_MASK)) | + PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_SET(clk_reg->rate_lvds) | + PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_SET(clk_reg->refclk_div) | + PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_SET(clk_reg->pll_div); + + /* + * lvds_rpck/refclk control signal + * 0: normal + * 1: inverter + */ + HPM_PIXEL_MUX->GPR_WR_D3 &= ~(0x01ul<<29); + + /* + * ckphy_ctl[2:0]:CLK_PHY divide ratio select, must be 010:div7 + * ckphy_ctl[8]:div4 enable signal + */ + HPM_PIXEL_MUX->GPR_WR_D4 = (HPM_PIXEL_MUX->GPR_WR_D4 & ~PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_MASK) | + PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_SET((clk_reg->data_rate_div4 & 0x01)<<8 | 0x02); +} + +void pixelmux_config_lvds_tx_phy1_clk(const lvds_phy_clk_reg_t *clk_reg) +{ + HPM_PIXEL_MUX->GPR_WR_D5 = (HPM_PIXEL_MUX->GPR_WR_D5 & + ~(PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_MASK | + PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_MASK | + PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_MASK | + PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_MASK)) | + PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_SET(clk_reg->rate_lvds) | + PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_SET(clk_reg->refclk_div) | + PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_SET(clk_reg->pll_div); + /* + * lvds_rpck/refclk control signal + * 0: normal + * 1: inverter + */ + HPM_PIXEL_MUX->GPR_WR_D6 &= ~(0x01ul<<29); + + /* + * ckphy_ctl[2:0]:CLK_PHY divide ratio select, must be 010:div7 + * ckphy_ctl[8]:div4 enable signal + */ + HPM_PIXEL_MUX->GPR_WR_D7 = (HPM_PIXEL_MUX->GPR_WR_D7 & ~PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_MASK) | + PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_SET((clk_reg->data_rate_div4 & 0x01)<<8 | 0x02); +} + +void pixelmux_config_rx_phy0_mode(pixelmux_rx_phy_mode_t mode) +{ + HPM_PIXEL_MUX->GPR_WR_D8 = (HPM_PIXEL_MUX->GPR_WR_D8 & + ~PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_MASK) | + PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_SET(mode); +} + +void pixelmux_config_rx_phy1_mode(pixelmux_rx_phy_mode_t mode) +{ + HPM_PIXEL_MUX->GPR_WR_D9 = (HPM_PIXEL_MUX->GPR_WR_D9 & + ~PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_MASK) | + PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_SET(mode); +} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_plb_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_plb_drv.c new file mode 100644 index 00000000000..60f8066a675 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_plb_drv.c @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_soc_feature.h" +#include "hpm_plb_drv.h" + +void plb_type_b_set_lut(PLB_Type *plb, plb_chn_t chn, plb_type_b_lut_slice_t slice, plb_type_b_slice_opt_t opt) +{ + if (opt >= plb_slice_opt_shift_left) { + opt = opt >> 8; + plb->TYPE_B[chn].MODE |= PLB_TYPE_B_MODE_OPT_SEL_SET(1); + } else { + plb->TYPE_B[chn].MODE &= ~PLB_TYPE_B_MODE_OPT_SEL_MASK; + } + if (slice >= plb_type_b_slice_8) { + plb->TYPE_B[chn].LUT[1] = (plb->TYPE_B[chn].LUT[1] & (~PLB_TYPE_B_LUT_LOOKUP_TABLE_SET(PLB_SLICE_HIGH_BIT_MASK_SET(slice)))) | PLB_TYPE_B_LUT_LOOKUP_TABLE_SET(opt << PLB_SLICE_HIGH_BIT_SHIFT(slice)); + } else { + plb->TYPE_B[chn].LUT[0] = (plb->TYPE_B[chn].LUT[0] & (~PLB_TYPE_B_LUT_LOOKUP_TABLE_SET(PLB_SLICE_LOW_BIT_MASK_SET(slice)))) | PLB_TYPE_B_LUT_LOOKUP_TABLE_SET(opt << PLB_SLICE_LOW_BIT_SHIFT(slice)); + } +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pllctl_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pllctl_drv.c index e261a3572f4..3b6fe2e436d 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pllctl_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pllctl_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -22,13 +22,39 @@ #define PLLCTL_FRAC_PLL_MIN_REF (10000000U) #define PLLCTL_INT_PLL_MIN_REF (1000000U) + +hpm_stat_t pllctl_set_pll_work_mode(PLLCTL_Type *ptr, uint8_t pll, bool int_mode) +{ + if ((ptr == NULL) || (pll >= PLLCTL_SOC_PLL_MAX_COUNT)) { + return status_invalid_argument; + } + if (int_mode) { + if (!(ptr->PLL[pll].CFG0 & PLLCTL_PLL_CFG0_DSMPD_MASK)) { + /* it was at frac mode, then it needs to be power down */ + pllctl_pll_powerdown(ptr, pll); + ptr->PLL[pll].CFG0 |= PLLCTL_PLL_CFG0_DSMPD_MASK; + pllctl_pll_poweron(ptr, pll); + } + } else { + if (ptr->PLL[pll].CFG0 & PLLCTL_PLL_CFG0_DSMPD_MASK) { + /* pll has to be powered down to configure frac mode */ + pllctl_pll_powerdown(ptr, pll); + ptr->PLL[pll].CFG0 &= ~PLLCTL_PLL_CFG0_DSMPD_MASK; + pllctl_pll_poweron(ptr, pll); + } + } + + return status_success; +} + hpm_stat_t pllctl_set_refdiv(PLLCTL_Type *ptr, uint8_t pll, uint8_t div) { uint32_t min_ref; - if ((pll > (PLLCTL_SOC_PLL_MAX_COUNT - 1)) - || (!div) - || (div > (PLLCTL_PLL_CFG0_REFDIV_MASK >> PLLCTL_PLL_CFG0_REFDIV_SHIFT))) { + if ((ptr == NULL) + || (pll > (PLLCTL_SOC_PLL_MAX_COUNT - 1)) + || (div == 0U) + || (div > (PLLCTL_PLL_CFG0_REFDIV_MASK >> PLLCTL_PLL_CFG0_REFDIV_SHIFT))) { return status_invalid_argument; } @@ -47,6 +73,7 @@ hpm_stat_t pllctl_set_refdiv(PLLCTL_Type *ptr, uint8_t pll, uint8_t div) pllctl_pll_powerdown(ptr, pll); ptr->PLL[pll].CFG0 = (ptr->PLL[pll].CFG0 & ~PLLCTL_PLL_CFG0_REFDIV_MASK) | PLLCTL_PLL_CFG0_REFDIV_SET(div); + pllctl_pll_poweron(ptr, pll); } return status_success; } @@ -54,6 +81,9 @@ hpm_stat_t pllctl_set_refdiv(PLLCTL_Type *ptr, uint8_t pll, uint8_t div) hpm_stat_t pllctl_init_int_pll_with_freq(PLLCTL_Type *ptr, uint8_t pll, uint32_t freq_in_hz) { + if ((ptr == NULL) || (pll >= PLLCTL_SOC_PLL_MAX_COUNT)) { + return status_invalid_argument; + } uint32_t freq, fbdiv, refdiv, postdiv; if ((freq_in_hz < PLLCTL_PLL_VCO_FREQ_MIN) || (freq_in_hz > PLLCTL_PLL_VCO_FREQ_MAX)) { @@ -118,6 +148,9 @@ hpm_stat_t pllctl_init_int_pll_with_freq(PLLCTL_Type *ptr, uint8_t pll, hpm_stat_t pllctl_init_frac_pll_with_freq(PLLCTL_Type *ptr, uint8_t pll, uint32_t freq_in_hz) { + if ((ptr == NULL) || (pll >= PLLCTL_SOC_PLL_MAX_COUNT)) { + return status_invalid_argument; + } uint32_t frac, refdiv, fbdiv, freq, postdiv; double div; if ((freq_in_hz < PLLCTL_PLL_VCO_FREQ_MIN) @@ -164,7 +197,7 @@ hpm_stat_t pllctl_init_frac_pll_with_freq(PLLCTL_Type *ptr, uint8_t pll, div = (double) freq / PLLCTL_SOC_PLL_REFCLK_FREQ * (refdiv * postdiv); fbdiv = freq / (PLLCTL_SOC_PLL_REFCLK_FREQ / (refdiv * postdiv)); - frac = (div - fbdiv) * (1 << 24); + frac = (uint32_t)((div - fbdiv) * (1 << 24)); /* * pll has to be powered down to configure frac mode @@ -186,6 +219,9 @@ hpm_stat_t pllctl_init_frac_pll_with_freq(PLLCTL_Type *ptr, uint8_t pll, uint32_t pllctl_get_pll_freq_in_hz(PLLCTL_Type *ptr, uint8_t pll) { + if ((ptr == NULL) || (pll >= PLLCTL_SOC_PLL_MAX_COUNT)) { + return status_invalid_argument; + } uint32_t fbdiv, frac, refdiv, postdiv, refclk, freq; if (ptr->PLL[pll].CFG1 & PLLCTL_PLL_CFG1_PLLPD_SW_MASK) { /* pll is powered down */ @@ -204,7 +240,7 @@ uint32_t pllctl_get_pll_freq_in_hz(PLLCTL_Type *ptr, uint8_t pll) /* pll frac mode */ fbdiv = PLLCTL_PLL_FREQ_FBDIV_FRAC_GET(ptr->PLL[pll].FREQ); frac = PLLCTL_PLL_FREQ_FRAC_GET(ptr->PLL[pll].FREQ); - freq = refclk * (fbdiv + ((double) frac / (1 << 24))); + freq = (uint32_t)((refclk * (fbdiv + ((double) frac / (1 << 24)))) + 0.5); } return freq; } diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pmp_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pmp_drv.c index cb66dd02ea6..975ba64647a 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pmp_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pmp_drv.c @@ -4,9 +4,8 @@ * SPDX-License-Identifier: BSD-3-Clause * */ -#include "riscv/riscv_core.h" #include "hpm_pmp_drv.h" -#include "hpm_csr_regs.h" +#include "hpm_csr_drv.h" uint32_t read_pmp_cfg(uint32_t idx) { @@ -31,29 +30,6 @@ uint32_t read_pmp_cfg(uint32_t idx) return pmp_cfg; } -uint32_t read_pma_cfg(uint32_t idx) -{ - uint32_t pma_cfg = 0; - switch (idx) { - case 0: - pma_cfg = read_csr(CSR_PMACFG0); - break; - case 1: - pma_cfg = read_csr(CSR_PMACFG1); - break; - case 2: - pma_cfg = read_csr(CSR_PMACFG2); - break; - case 3: - pma_cfg = read_csr(CSR_PMACFG3); - break; - default: - /* Do nothing */ - break; - } - return pma_cfg; -} - void write_pmp_cfg(uint32_t value, uint32_t idx) { switch (idx) { @@ -75,27 +51,6 @@ void write_pmp_cfg(uint32_t value, uint32_t idx) } } -void write_pma_cfg(uint32_t value, uint32_t idx) -{ - switch (idx) { - case 0: - write_csr(CSR_PMACFG0, value); - break; - case 1: - write_csr(CSR_PMACFG1, value); - break; - case 2: - write_csr(CSR_PMACFG2, value); - break; - case 3: - write_csr(CSR_PMACFG3, value); - break; - default: - /* Do nothing */ - break; - } -} - void write_pmp_addr(uint32_t value, uint32_t idx) { switch (idx) { @@ -153,120 +108,164 @@ void write_pmp_addr(uint32_t value, uint32_t idx) } } -void write_pma_addr(uint32_t value, uint32_t idx) +uint32_t read_pmp_addr(uint32_t idx) { + uint32_t ret_val = 0; switch (idx) { case 0: - write_csr(CSR_PMAADDR0, value); + ret_val = read_csr(CSR_PMPADDR0); break; case 1: - write_csr(CSR_PMAADDR1, value); + ret_val = read_csr(CSR_PMPADDR1); break; case 2: - write_csr(CSR_PMAADDR2, value); + ret_val = read_csr(CSR_PMPADDR2); break; case 3: - write_csr(CSR_PMAADDR3, value); + ret_val = read_csr(CSR_PMPADDR3); break; case 4: - write_csr(CSR_PMAADDR4, value); + ret_val = read_csr(CSR_PMPADDR4); break; case 5: - write_csr(CSR_PMAADDR5, value); + ret_val = read_csr(CSR_PMPADDR5); break; case 6: - write_csr(CSR_PMAADDR6, value); + ret_val = read_csr(CSR_PMPADDR6); break; case 7: - write_csr(CSR_PMAADDR7, value); + ret_val = read_csr(CSR_PMPADDR7); break; case 8: - write_csr(CSR_PMAADDR8, value); + ret_val = read_csr(CSR_PMPADDR8); break; case 9: - write_csr(CSR_PMAADDR9, value); + ret_val = read_csr(CSR_PMPADDR9); break; case 10: - write_csr(CSR_PMAADDR10, value); + ret_val = read_csr(CSR_PMPADDR10); break; case 11: - write_csr(CSR_PMAADDR11, value); + ret_val = read_csr(CSR_PMPADDR11); break; case 12: - write_csr(CSR_PMAADDR12, value); + ret_val = read_csr(CSR_PMPADDR12); break; case 13: - write_csr(CSR_PMAADDR13, value); + ret_val = read_csr(CSR_PMPADDR13); break; case 14: - write_csr(CSR_PMAADDR14, value); + ret_val = read_csr(CSR_PMPADDR14); break; case 15: - write_csr(CSR_PMAADDR15, value); + ret_val = read_csr(CSR_PMPADDR15); break; default: /* Do nothing */ break; } + return ret_val; } -uint32_t read_pmp_addr(uint32_t idx) +#if (!defined(PMP_SUPPORT_PMA)) || (defined(PMP_SUPPORT_PMA) && (PMP_SUPPORT_PMA == 1)) +uint32_t read_pma_cfg(uint32_t idx) { - uint32_t ret_val = 0; + uint32_t pma_cfg = 0; switch (idx) { case 0: - ret_val = read_csr(CSR_PMPADDR0); + pma_cfg = read_csr(CSR_PMACFG0); break; case 1: - ret_val = read_csr(CSR_PMPADDR1); + pma_cfg = read_csr(CSR_PMACFG1); break; case 2: - ret_val = read_csr(CSR_PMPADDR2); + pma_cfg = read_csr(CSR_PMACFG2); break; case 3: - ret_val = read_csr(CSR_PMPADDR3); + pma_cfg = read_csr(CSR_PMACFG3); + break; + default: + /* Do nothing */ + break; + } + return pma_cfg; +} + +void write_pma_cfg(uint32_t value, uint32_t idx) +{ + switch (idx) { + case 0: + write_csr(CSR_PMACFG0, value); + break; + case 1: + write_csr(CSR_PMACFG1, value); + break; + case 2: + write_csr(CSR_PMACFG2, value); + break; + case 3: + write_csr(CSR_PMACFG3, value); + break; + default: + /* Do nothing */ + break; + } +} +void write_pma_addr(uint32_t value, uint32_t idx) +{ + switch (idx) { + case 0: + write_csr(CSR_PMAADDR0, value); + break; + case 1: + write_csr(CSR_PMAADDR1, value); + break; + case 2: + write_csr(CSR_PMAADDR2, value); + break; + case 3: + write_csr(CSR_PMAADDR3, value); break; case 4: - ret_val = read_csr(CSR_PMPADDR4); + write_csr(CSR_PMAADDR4, value); break; case 5: - ret_val = read_csr(CSR_PMPADDR5); + write_csr(CSR_PMAADDR5, value); break; case 6: - ret_val = read_csr(CSR_PMPADDR6); + write_csr(CSR_PMAADDR6, value); break; case 7: - ret_val = read_csr(CSR_PMPADDR7); + write_csr(CSR_PMAADDR7, value); break; case 8: - ret_val = read_csr(CSR_PMPADDR8); + write_csr(CSR_PMAADDR8, value); break; case 9: - ret_val = read_csr(CSR_PMPADDR9); + write_csr(CSR_PMAADDR9, value); break; case 10: - ret_val = read_csr(CSR_PMPADDR10); + write_csr(CSR_PMAADDR10, value); break; case 11: - ret_val = read_csr(CSR_PMPADDR11); + write_csr(CSR_PMAADDR11, value); break; case 12: - ret_val = read_csr(CSR_PMPADDR12); + write_csr(CSR_PMAADDR12, value); break; case 13: - ret_val = read_csr(CSR_PMPADDR13); + write_csr(CSR_PMAADDR13, value); break; case 14: - ret_val = read_csr(CSR_PMPADDR14); + write_csr(CSR_PMAADDR14, value); break; case 15: - ret_val = read_csr(CSR_PMPADDR15); + write_csr(CSR_PMAADDR15, value); break; default: /* Do nothing */ break; } - return ret_val; } uint32_t read_pma_addr(uint32_t idx) @@ -327,6 +326,7 @@ uint32_t read_pma_addr(uint32_t idx) } return ret_val; } +#endif /* #if (!defined(PMP_SUPPORT_PMA)) || (defined(PMP_SUPPORT_PMA) && (PMP_SUPPORT_PMA == 1)) */ hpm_stat_t pmp_config_entry(const pmp_entry_t *entry, uint32_t entry_index) { @@ -340,15 +340,15 @@ hpm_stat_t pmp_config_entry(const pmp_entry_t *entry, uint32_t entry_index) uint32_t pmp_cfg = read_pmp_cfg(idx); pmp_cfg &= ~(0xFFUL << offset); pmp_cfg |= ((uint32_t) entry->pmp_cfg.val) << offset; + write_pmp_addr(entry->pmp_addr, entry_index); + write_pmp_cfg(pmp_cfg, idx); +#if (!defined(PMP_SUPPORT_PMA)) || (defined(PMP_SUPPORT_PMA) && (PMP_SUPPORT_PMA == 1)) uint32_t pma_cfg = read_pma_cfg(idx); pma_cfg &= ~(0xFFUL << offset); pma_cfg |= ((uint32_t) entry->pma_cfg.val) << offset; - - write_pmp_addr(entry->pmp_addr, entry_index); - write_pma_addr(entry->pma_addr, entry_index); - write_pma_cfg(pma_cfg, idx); - write_pmp_cfg(pmp_cfg, idx); + write_pma_addr(entry->pma_addr, entry_index); +#endif fencei(); status = status_success; @@ -367,20 +367,18 @@ hpm_stat_t pmp_config(const pmp_entry_t *entry, uint32_t num_of_entries) for (uint32_t i = 0; i < num_of_entries; i++) { uint32_t idx = i / 4; uint32_t offset = (i * 8) & 0x1F; - uint32_t pmp_cfg = read_pmp_cfg(idx); pmp_cfg &= ~(0xFFUL << offset); pmp_cfg |= ((uint32_t) entry->pmp_cfg.val) << offset; + write_pmp_addr(entry->pmp_addr, i); + write_pmp_cfg(pmp_cfg, idx); +#if (!defined(PMP_SUPPORT_PMA)) || (defined(PMP_SUPPORT_PMA) && (PMP_SUPPORT_PMA == 1)) uint32_t pma_cfg = read_pma_cfg(idx); pma_cfg &= ~(0xFFUL << offset); pma_cfg |= ((uint32_t) entry->pma_cfg.val) << offset; - - write_pmp_addr(entry->pmp_addr, i); - write_pma_addr(entry->pma_addr, i); - write_pma_cfg(pma_cfg, idx); - write_pmp_cfg(pmp_cfg, idx); - + write_pma_addr(entry->pma_addr, i); +#endif ++entry; } fencei(); @@ -399,15 +397,32 @@ void pmp_disable(void) uint32_t mcache_ctl = read_csr(CSR_MCACHE_CTL); write_csr(CSR_MCACHE_CTL, 0x0); fencei(); - write_csr(CSR_PMACFG0, 0); - write_csr(CSR_PMACFG1, 0); - write_csr(CSR_PMACFG2, 0); - write_csr(CSR_PMACFG3, 0); + write_csr(CSR_PMPCFG0, 0); write_csr(CSR_PMPCFG1, 0); write_csr(CSR_PMPCFG2, 0); write_csr(CSR_PMPCFG3, 0); - + write_csr(CSR_PMPADDR0, 0); + write_csr(CSR_PMPADDR1, 0); + write_csr(CSR_PMPADDR2, 0); + write_csr(CSR_PMPADDR3, 0); + write_csr(CSR_PMPADDR4, 0); + write_csr(CSR_PMPADDR5, 0); + write_csr(CSR_PMPADDR6, 0); + write_csr(CSR_PMPADDR7, 0); + write_csr(CSR_PMPADDR8, 0); + write_csr(CSR_PMPADDR9, 0); + write_csr(CSR_PMPADDR10, 0); + write_csr(CSR_PMPADDR11, 0); + write_csr(CSR_PMPADDR12, 0); + write_csr(CSR_PMPADDR13, 0); + write_csr(CSR_PMPADDR14, 0); + write_csr(CSR_PMPADDR15, 0); +#if (!defined(PMP_SUPPORT_PMA)) || (defined(PMP_SUPPORT_PMA) && (PMP_SUPPORT_PMA == 1)) + write_csr(CSR_PMACFG0, 0); + write_csr(CSR_PMACFG1, 0); + write_csr(CSR_PMACFG2, 0); + write_csr(CSR_PMACFG3, 0); write_csr(CSR_PMAADDR0, 0); write_csr(CSR_PMAADDR1, 0); write_csr(CSR_PMAADDR2, 0); @@ -424,6 +439,7 @@ void pmp_disable(void) write_csr(CSR_PMAADDR13, 0); write_csr(CSR_PMAADDR14, 0); write_csr(CSR_PMAADDR15, 0); +#endif fencei(); write_csr(CSR_MCACHE_CTL, mcache_ctl); fencei(); diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ptpc_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ptpc_drv.c index 689035e2d1f..57c5ac2cd58 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ptpc_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ptpc_drv.c @@ -12,6 +12,7 @@ void ptpc_get_default_config(PTPC_Type *ptr, ptpc_config_t *config) { + (void) ptr; config->capture_trigger = ptpc_capture_trigger_none; config->ns_rollover_mode = ptpc_ns_counter_rollover_digital; config->capture_keep = true; diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pwm_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pwm_drv.c index fa94e2a4fe9..4b9e7d7a8e4 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pwm_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pwm_drv.c @@ -37,10 +37,11 @@ void pwm_get_captured_count(PWM_Type *pwm_x, uint32_t *buf, pwm_counter_type_t c void pwm_get_default_cmp_config(PWM_Type *pwm_x, pwm_cmp_config_t *config) { + (void) pwm_x; config->mode = pwm_cmp_mode_output_compare; config->update_trigger = pwm_shadow_register_update_on_modify; config->enable_ex_cmp = false; -#if PWM_SOC_HRPWM_SUPPORT +#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT config->enable_hrcmp = false; config->hrcmp = 0; #endif @@ -52,6 +53,7 @@ void pwm_get_default_cmp_config(PWM_Type *pwm_x, pwm_cmp_config_t *config) void pwm_get_default_output_channel_config(PWM_Type *pwm_x, pwm_output_channel_t *config) { + (void) pwm_x; config->cmp_start_index = 0; config->cmp_end_index = 0; config->invert_output = false; @@ -59,6 +61,7 @@ void pwm_get_default_output_channel_config(PWM_Type *pwm_x, pwm_output_channel_t void pwm_get_default_pwm_config(PWM_Type *pwm_x, pwm_config_t *config) { + (void) pwm_x; config->enable_output = false; config->update_trigger = pwm_shadow_register_update_on_modify; config->fault_mode = pwm_fault_mode_force_output_highz; @@ -156,7 +159,7 @@ hpm_stat_t pwm_update_raw_cmp_central_aligned(PWM_Type *pwm_x, uint8_t cmp1_inde pwm_cmp_update_cmp_value(pwm_x, cmp2_index, target_cmp2, 0); return status_success; } -#if PWM_SOC_HRPWM_SUPPORT +#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT hpm_stat_t pwm_update_raw_hrcmp_edge_aligned(PWM_Type *pwm_x, uint8_t cmp_index, uint32_t target_cmp, uint16_t target_hrcmp) diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_qeiv2_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_qeiv2_drv.c new file mode 100644 index 00000000000..0c0ff8237ba --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_qeiv2_drv.c @@ -0,0 +1,139 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_qeiv2_drv.h" +#include "hpm_enc_pos_drv.h" + +hpm_stat_t qeiv2_config_phcnt_cmp_match_condition(QEIV2_Type *qeiv2_x, qeiv2_phcnt_cmp_match_config_t *config) +{ + if (qeiv2_check_spd_tmr_as_pos_angle(qeiv2_x)) { + return status_fail; + } + qeiv2_set_phcnt_cmp_value(qeiv2_x, config->phcnt_cmp_value); + qeiv2_set_spd_pos_cmp_value(qeiv2_x, 0); + qeiv2_set_z_cmp_value(qeiv2_x, config->zcmp_value); + qeiv2_set_cmp_match_option(qeiv2_x, config->ignore_zcmp, false, false, config->ignore_rotate_dir, config->rotate_dir, true, qeiv2_pos_dir_decrease); + return status_success; +} + +hpm_stat_t qeiv2_config_position_cmp_match_condition(QEIV2_Type *qeiv2_x, qeiv2_pos_cmp_match_config_t *config) +{ + if (!qeiv2_check_spd_tmr_as_pos_angle(qeiv2_x)) { + return status_fail; + } + qeiv2_set_spd_pos_cmp_value(qeiv2_x, config->pos_cmp_value); + qeiv2_set_cmp_match_option(qeiv2_x, true, true, false, true, qeiv2_rotate_dir_forward, config->ignore_pos_dir, config->pos_dir); + return status_success; +} + +hpm_stat_t qeiv2_config_phcnt_cmp2_match_condition(QEIV2_Type *qeiv2_x, qeiv2_phcnt_cmp_match_config_t *config) +{ + if (qeiv2_check_spd_tmr_as_pos_angle(qeiv2_x)) { + return status_fail; + } + qeiv2_set_phcnt_cmp2_value(qeiv2_x, config->phcnt_cmp_value); + qeiv2_set_spd_pos_cmp2_value(qeiv2_x, 0); + qeiv2_set_z_cmp2_value(qeiv2_x, config->zcmp_value); + qeiv2_set_cmp2_match_option(qeiv2_x, config->ignore_zcmp, false, false, config->ignore_rotate_dir, config->rotate_dir, true, qeiv2_pos_dir_decrease); + return status_success; +} + +hpm_stat_t qeiv2_config_position_cmp2_match_condition(QEIV2_Type *qeiv2_x, qeiv2_pos_cmp_match_config_t *config) +{ + if (!qeiv2_check_spd_tmr_as_pos_angle(qeiv2_x)) { + return status_fail; + } + qeiv2_set_spd_pos_cmp2_value(qeiv2_x, config->pos_cmp_value); + qeiv2_set_cmp2_match_option(qeiv2_x, true, true, false, true, qeiv2_rotate_dir_forward, config->ignore_pos_dir, config->pos_dir); + return status_success; +} + +void qeiv2_get_uvw_position_defconfig(qeiv2_uvw_config_t *config) +{ + config->pos_opt = qeiv2_uvw_pos_opt_current; + + config->u_pos_sel[0] = qeiv2_uvw_pos_sel_high; + config->v_pos_sel[0] = qeiv2_uvw_pos_sel_low; + config->w_pos_sel[0] = qeiv2_uvw_pos_sel_high; + + config->u_pos_sel[1] = qeiv2_uvw_pos_sel_high; + config->v_pos_sel[1] = qeiv2_uvw_pos_sel_low; + config->w_pos_sel[1] = qeiv2_uvw_pos_sel_low; + + config->u_pos_sel[2] = qeiv2_uvw_pos_sel_high; + config->v_pos_sel[2] = qeiv2_uvw_pos_sel_high; + config->w_pos_sel[2] = qeiv2_uvw_pos_sel_low; + + config->u_pos_sel[3] = qeiv2_uvw_pos_sel_low; + config->v_pos_sel[3] = qeiv2_uvw_pos_sel_high; + config->w_pos_sel[3] = qeiv2_uvw_pos_sel_low; + + config->u_pos_sel[4] = qeiv2_uvw_pos_sel_low; + config->v_pos_sel[4] = qeiv2_uvw_pos_sel_high; + config->w_pos_sel[4] = qeiv2_uvw_pos_sel_high; + + config->u_pos_sel[5] = qeiv2_uvw_pos_sel_low; + config->v_pos_sel[5] = qeiv2_uvw_pos_sel_low; + config->w_pos_sel[5] = qeiv2_uvw_pos_sel_high; + + config->pos_cfg[0] = encoder_deg_to_position(30); + config->pos_cfg[1] = encoder_deg_to_position(90); + config->pos_cfg[2] = encoder_deg_to_position(150); + config->pos_cfg[3] = encoder_deg_to_position(210); + config->pos_cfg[4] = encoder_deg_to_position(270); + config->pos_cfg[5] = encoder_deg_to_position(330); +} + +hpm_stat_t qeiv2_config_uvw_position(QEIV2_Type *qeiv2_x, qeiv2_uvw_config_t *config) +{ + qeiv2_set_uvw_position_opt(qeiv2_x, config->pos_opt); + for (uint8_t i = 0; i < 6; i++) { + if (config->pos_opt == qeiv2_uvw_pos_opt_next) { + if ((config->u_pos_sel[i] == qeiv2_uvw_pos_sel_edge) + || (config->v_pos_sel[i] == qeiv2_uvw_pos_sel_edge) + || (config->w_pos_sel[i] == qeiv2_uvw_pos_sel_edge)) { + return status_invalid_argument; + } + } + } + + for (uint8_t i = 0; i < 6; i++) { + if (config->pos_opt == qeiv2_uvw_pos_opt_next) { + qeiv2_set_uvw_position_sel(qeiv2_x, i, + (config->u_pos_sel[i] == qeiv2_uvw_pos_sel_high) ? QEIV2_UVW_POS_OPT_NEX_SEL_HIGH : QEIV2_UVW_POS_OPT_NEX_SEL_LOW, + (config->v_pos_sel[i] == qeiv2_uvw_pos_sel_high) ? QEIV2_UVW_POS_OPT_NEX_SEL_HIGH : QEIV2_UVW_POS_OPT_NEX_SEL_LOW, + (config->w_pos_sel[i] == qeiv2_uvw_pos_sel_high) ? QEIV2_UVW_POS_OPT_NEX_SEL_HIGH : QEIV2_UVW_POS_OPT_NEX_SEL_LOW, + true); + } else { + qeiv2_set_uvw_position_sel(qeiv2_x, i, config->u_pos_sel[i], config->v_pos_sel[i], config->w_pos_sel[i], true); + } + qeiv2_set_uvw_position(qeiv2_x, i, config->pos_cfg[i]); + } + + return status_success; +} + +void qeiv2_config_filter(QEIV2_Type *qeiv2_x, qeiv2_filter_phase_t phase, bool outinv, qeiv2_filter_mode_t mode, bool sync, uint32_t filtlen) +{ + uint32_t len = filtlen; + uint8_t shift; + for (shift = 0; shift <= 7u; shift++) { + if (shift > 0) { + len >>= 1u; + } + if (len <= 0x1FFu) { + break; + } + } + if (len > 0x1FFu) { + len = 0x1FFu; + shift = 7u; + } + + qeiv2_x->FILT_CFG[phase] = + QEIV2_FILT_CFG_OUTINV_SET(outinv) | QEIV2_FILT_CFG_MODE_SET(mode) | QEIV2_FILT_CFG_SYNCEN_SET(sync) | QEIV2_FILT_CFG_FILTLEN_SET(((shift << 9u) | len)); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_qeo_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_qeo_drv.c new file mode 100644 index 00000000000..279f093a56a --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_qeo_drv.c @@ -0,0 +1,239 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_qeo_drv.h" + +void qeo_wave_get_default_mode_config(QEO_Type *base, qeo_wave_mode_t *config) +{ + (void) base; + config->wave0.above_max_limit = qeo_wave_above_max_limit_max_val; + config->wave0.high_area0_limit = qeo_wave_high_area_limit_max_val; + config->wave0.high_area1_limit = qeo_wave_high_area_limit_max_val; + config->wave0.low_area0_limit = qeo_wave_low_area_limit_zero; + config->wave0.low_area1_limit = qeo_wave_low_area_limit_zero; + config->wave0.below_min_limit = qeo_wave_below_min_limit_zero; + + config->wave1.above_max_limit = qeo_wave_above_max_limit_max_val; + config->wave1.high_area0_limit = qeo_wave_high_area_limit_max_val; + config->wave1.high_area1_limit = qeo_wave_high_area_limit_max_val; + config->wave1.low_area0_limit = qeo_wave_low_area_limit_zero; + config->wave1.low_area1_limit = qeo_wave_low_area_limit_zero; + config->wave1.below_min_limit = qeo_wave_below_min_limit_zero; + + config->wave2.above_max_limit = qeo_wave_above_max_limit_max_val; + config->wave2.high_area0_limit = qeo_wave_high_area_limit_max_val; + config->wave2.high_area1_limit = qeo_wave_high_area_limit_max_val; + config->wave2.low_area0_limit = qeo_wave_low_area_limit_zero; + config->wave2.low_area1_limit = qeo_wave_low_area_limit_zero; + config->wave2.below_min_limit = qeo_wave_below_min_limit_zero; + + config->saddle_type = 0; + config->wave_type = qeo_wave_cosine; +} + +void qeo_wave_config_mode(QEO_Type *base, qeo_wave_mode_t *config) +{ + /* clear other bit except EN_WAVEx_VD_VQ_INJECT in MODE register */ + base->WAVE.MODE &= QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_MASK + | QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_MASK + | QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_MASK; + + base->WAVE.MODE |= QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SET(config->wave2.above_max_limit) + | QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SET(config->wave2.high_area1_limit) + | QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SET(config->wave2.high_area0_limit) + | QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SET(config->wave2.low_area1_limit) + | QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SET(config->wave2.low_area0_limit) + | QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SET(config->wave2.below_min_limit) + + | QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SET(config->wave1.above_max_limit) + | QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SET(config->wave1.high_area1_limit) + | QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SET(config->wave1.high_area0_limit) + | QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SET(config->wave1.low_area1_limit) + | QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SET(config->wave1.low_area0_limit) + | QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SET(config->wave1.below_min_limit) + + | QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SET(config->wave0.above_max_limit) + | QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SET(config->wave0.high_area1_limit) + | QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SET(config->wave0.high_area0_limit) + | QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SET(config->wave0.low_area1_limit) + | QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SET(config->wave0.low_area0_limit) + | QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SET(config->wave0.below_min_limit) + | QEO_WAVE_MODE_SADDLE_TYPE_SET(config->saddle_type) + | QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_SET(config->wave_type); +} + +void qeo_abz_get_default_mode_config(QEO_Type *base, qeo_abz_mode_t *config) +{ + (void) base; + config->a_inv_pol = false; + config->b_inv_pol = false; + config->z_inv_pol = false; + config->output_type = qeo_abz_output_abz; + config->z_pulse_period = qeo_z_pulse_100_percent; +} + +void qeo_abz_config_mode(QEO_Type *base, qeo_abz_mode_t *config) +{ + base->ABZ.MODE &= ~(QEO_ABZ_MODE_Z_POLARITY_MASK + | QEO_ABZ_MODE_B_POLARITY_MASK + | QEO_ABZ_MODE_A_POLARITY_MASK + | QEO_ABZ_MODE_Z_TYPE_MASK + | QEO_ABZ_MODE_B_TYPE_MASK + | QEO_ABZ_MODE_A_TYPE_MASK); + + base->ABZ.MODE = QEO_ABZ_MODE_Z_POLARITY_SET(config->z_inv_pol) + | QEO_ABZ_MODE_B_POLARITY_SET(config->b_inv_pol) + | QEO_ABZ_MODE_A_POLARITY_SET(config->a_inv_pol); + + if ((config->output_type == qeo_abz_output_pulse_revise) || (config->output_type == qeo_abz_output_up_down)) { + base->ABZ.MODE |= QEO_ABZ_MODE_B_TYPE_SET(config->output_type) + | QEO_ABZ_MODE_A_TYPE_SET(config->output_type); + } else if (config->output_type == qeo_abz_output_three_phase) { + base->ABZ.MODE |= QEO_ABZ_MODE_Z_TYPE_SET(config->output_type) + | QEO_ABZ_MODE_B_TYPE_SET(config->output_type) + | QEO_ABZ_MODE_A_TYPE_SET(config->output_type); + } else { + base->ABZ.MODE |= QEO_ABZ_MODE_Z_TYPE_SET(config->z_pulse_period) + | QEO_ABZ_MODE_B_TYPE_SET(config->output_type) + | QEO_ABZ_MODE_A_TYPE_SET(config->output_type); + } +} + +hpm_stat_t qeo_abz_set_max_frequency(QEO_Type *base, uint32_t src_freq, uint32_t freq) +{ + uint32_t count; + + if ((freq > 0xffffffffU / 4U) || ((src_freq % (freq * 4U)) != 0)) { + return status_invalid_argument; + } + count = src_freq / (freq * 4U); + base->ABZ.LINE_WIDTH = QEO_ABZ_LINE_WIDTH_LINE_SET(count); + + return status_success; +} + +hpm_stat_t qeo_abz_set_wdog_frequency(QEO_Type *base, uint32_t src_freq, uint32_t freq) +{ + uint32_t count; + + if ((src_freq % freq) != 0) { + return status_invalid_argument; + } + count = src_freq / freq; + base->ABZ.WDOG_WIDTH = QEO_ABZ_WDOG_WIDTH_WIDTH_SET(count); + base->ABZ.MODE |= QEO_ABZ_MODE_EN_WDOG_MASK; + + return status_success; +} + +void qeo_pwm_get_default_safety_table_config(QEO_Type *base, qeo_pwm_safety_output_table_t *table) +{ + (void) base; + table->pwm7_output = qeo_pwm_safety_output_highz; + table->pwm6_output = qeo_pwm_safety_output_highz; + table->pwm5_output = qeo_pwm_safety_output_highz; + table->pwm4_output = qeo_pwm_safety_output_highz; + table->pwm3_output = qeo_pwm_safety_output_highz; + table->pwm2_output = qeo_pwm_safety_output_highz; + table->pwm1_output = qeo_pwm_safety_output_highz; + table->pwm0_output = qeo_pwm_safety_output_highz; +} + +void qeo_pwm_get_default_phase_table_config(QEO_Type *base, qeo_pwm_phase_output_table_t *table) +{ + (void) base; + table->pwm7_output = qeo_pwm_output_force_0; + table->pwm6_output = qeo_pwm_output_force_0; + table->pwm5_output = qeo_pwm_output_force_0; + table->pwm4_output = qeo_pwm_output_force_0; + table->pwm3_output = qeo_pwm_output_force_0; + table->pwm2_output = qeo_pwm_output_force_0; + table->pwm1_output = qeo_pwm_output_force_0; + table->pwm0_output = qeo_pwm_output_force_0; +} + +void qeo_pwm_get_default_mode_config(QEO_Type *base, qeo_pwm_mode_t *config) +{ + (void) base; + config->phase_num = 4; + config->shield_hardware_trig_safety = false; + config->revise_pairs_output = false; +} + +void qeo_pwm_config_mode(QEO_Type *base, qeo_pwm_mode_t *config) +{ + base->PWM.MODE &= ~(QEO_PWM_MODE_PWM_SAFETY_BYPASS_MASK + | QEO_PWM_MODE_REVISE_UP_DN_MASK + | QEO_PWM_MODE_PHASE_NUM_MASK); + base->PWM.MODE |= QEO_PWM_MODE_PWM_SAFETY_BYPASS_SET(config->shield_hardware_trig_safety) + | QEO_PWM_MODE_REVISE_UP_DN_SET(config->revise_pairs_output) + | QEO_PWM_MODE_PHASE_NUM_SET(config->phase_num); +} + +void qeo_pwm_config_phase_table(QEO_Type *base, uint8_t index, qeo_pwm_phase_output_table_t *table) +{ + base->PWM.PHASE_TABLE[index] = QEO_PWM_PHASE_TABLE_PWM7_SET(table->pwm7_output) + | QEO_PWM_PHASE_TABLE_PWM6_SET(table->pwm6_output) + | QEO_PWM_PHASE_TABLE_PWM5_SET(table->pwm5_output) + | QEO_PWM_PHASE_TABLE_PWM4_SET(table->pwm4_output) + | QEO_PWM_PHASE_TABLE_PWM3_SET(table->pwm3_output) + | QEO_PWM_PHASE_TABLE_PWM2_SET(table->pwm2_output) + | QEO_PWM_PHASE_TABLE_PWM1_SET(table->pwm1_output) + | QEO_PWM_PHASE_TABLE_PWM0_SET(table->pwm0_output); +} + +void qeo_pwm_config_safety_table(QEO_Type *base, qeo_pwm_safety_output_table_t *table) +{ + /*< clear safety table */ + base->PWM.MODE &= ~(QEO_PWM_MODE_PWM7_SAFETY_MASK + | QEO_PWM_MODE_PWM6_SAFETY_MASK + | QEO_PWM_MODE_PWM5_SAFETY_MASK + | QEO_PWM_MODE_PWM4_SAFETY_MASK + | QEO_PWM_MODE_PWM3_SAFETY_MASK + | QEO_PWM_MODE_PWM2_SAFETY_MASK + | QEO_PWM_MODE_PWM1_SAFETY_MASK + | QEO_PWM_MODE_PWM0_SAFETY_MASK); + /*< set safety table */ + base->PWM.MODE |= QEO_PWM_MODE_PWM7_SAFETY_SET(table->pwm7_output) + | QEO_PWM_MODE_PWM6_SAFETY_SET(table->pwm6_output) + | QEO_PWM_MODE_PWM5_SAFETY_SET(table->pwm5_output) + | QEO_PWM_MODE_PWM4_SAFETY_SET(table->pwm4_output) + | QEO_PWM_MODE_PWM3_SAFETY_SET(table->pwm3_output) + | QEO_PWM_MODE_PWM2_SAFETY_SET(table->pwm2_output) + | QEO_PWM_MODE_PWM1_SAFETY_SET(table->pwm1_output) + | QEO_PWM_MODE_PWM0_SAFETY_SET(table->pwm0_output); +} + +/** + * If the line step of the position to be synchronized after position value + * to ABZ value conversion is the same as the current position, will hang the ABZ. + * ABZ value = m lines + n line_steps(0 <= m <= 3) + * This API will check the sync_pos and shift it if needed + */ +void qeo_abz_position_sync(QEO_Type *base, uint32_t lines, uint32_t sync_pos) +{ + uint32_t line_width; + uint32_t line_step_width; + uint32_t shift_pos; + uint32_t current_line_step; + uint32_t temp; + + line_width = (uint32_t)(0x100000000UL / lines); + line_step_width = line_width / 4U; + current_line_step = base->DEBUG2 & 0x3; /* get the lowest two bits */ + temp = (sync_pos % line_width) / line_step_width; + if (temp == current_line_step) { + shift_pos = sync_pos - line_step_width; + } else { + shift_pos = sync_pos; + } + + base->ABZ.POSTION_SYNC = QEO_ABZ_POSTION_SYNC_POSTION_MASK; + qeo_enable_software_position_inject(base); + qeo_software_position_inject(base, shift_pos); + qeo_disable_software_position_inject(base); +} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rdc_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rdc_drv.c new file mode 100644 index 00000000000..065ee8947f6 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rdc_drv.c @@ -0,0 +1,180 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_rdc_drv.h" + +void rdc_output_config(RDC_Type *ptr, rdc_output_cfg_t *cfg) +{ + uint32_t rate; + + rate = cfg->excitation_period_cycle >> (cfg->excitation_precision + 2); + ptr->EXC_TIMMING = RDC_EXC_TIMMING_SMP_RATE_SET(rate) | + RDC_EXC_TIMMING_SMP_NUM_SET(cfg->excitation_precision) | + RDC_EXC_TIMMING_PWM_PRD_SET(cfg->pwm_period)| + RDC_EXC_TIMMING_SWAP_SET(cfg->output_swap); + if (cfg->mode == rdc_output_dac) { + ptr->EXC_SCALING = RDC_EXC_SCALING_AMP_MAN_SET(cfg->amp_man) | + RDC_EXC_SCALING_AMP_EXP_SET(cfg->amp_exp); + ptr->EXC_OFFSET = RDC_EXC_OFFSET_AMP_OFFSET_SET(cfg->amp_offset + 0x800000); + ptr->OUT_CTL = RDC_OUT_CTL_CH_I_SEL_SET(cfg->dac_chn_i_sel) | + RDC_OUT_CTL_CH_Q_SEL_SET(cfg->dac_chn_q_sel); + } else if (cfg->mode == rdc_output_pwm) { + ptr->PWM_SCALING = RDC_EXC_SCALING_AMP_MAN_SET(cfg->amp_man) | + RDC_EXC_SCALING_AMP_EXP_SET(cfg->amp_exp) | + RDC_PWM_SCALING_DITHER_SET(cfg->pwm_dither_enable) | + RDC_PWM_SCALING_P_POL_SET(cfg->pwm_exc_p_low_active) | + RDC_PWM_SCALING_N_POL_SET(cfg->pwm_exc_n_low_active); + ptr->PWM_OFFSET = RDC_PWM_OFFSET_AMP_OFFSET_SET(cfg->amp_offset + (rate >> 1)); + ptr->PWM_DZ = RDC_PWM_DZ_DZ_N_SET(cfg->pwm_deadzone_n) | + RDC_PWM_DZ_DZ_P_SET(cfg->pwm_deadzone_p); + } + if (cfg->trig_by_hw) { + ptr->EXC_SYNC_DLY = RDC_EXC_SYNC_DLY_DELAY_SET(cfg->hw_trig_delay); + } else { + ptr->EXC_SYNC_DLY = RDC_EXC_SYNC_DLY_DISABLE_MASK; + } +} + + +void rdc_input_config(RDC_Type *ptr, rdc_input_cfg_t *cfg) +{ + ptr->RDC_CTL = (ptr->RDC_CTL & (~(RDC_RDC_CTL_RECTIFY_SEL_MASK | RDC_RDC_CTL_ACC_LEN_MASK | RDC_RDC_CTL_TS_SEL_MASK))) + | RDC_RDC_CTL_RECTIFY_SEL_SET(cfg->rectify_signal_sel) + | RDC_RDC_CTL_ACC_LEN_SET(cfg->acc_cycle_len) + | RDC_RDC_CTL_TS_SEL_SET(cfg->acc_stamp); + ptr->IN_CTL = RDC_IN_CTL_PORT_I_SEL_SET(cfg->acc_input_port_i) | + RDC_IN_CTL_CH_I_SEL_SET(cfg->acc_input_chn_i) | + RDC_IN_CTL_PORT_Q_SEL_SET(cfg->acc_input_port_q) | + RDC_IN_CTL_CH_Q_SEL_SET(cfg->acc_input_chn_q); +} + +uint32_t rdc_get_acc_avl(RDC_Type *ptr, rdc_input_acc_chn_t chn) +{ + if (chn == rdc_acc_chn_i) { + return RDC_ACC_I_ACC_GET(ptr->ACC_I); + } else { + return RDC_ACC_Q_ACC_GET(ptr->ACC_Q); + } +} + +void rdc_output_trig_offset_config(RDC_Type *ptr, rdc_output_trig_chn_t chn, int32_t offset) +{ + if (chn == trigger_out_0) { + ptr->TRIG_OUT0_CFG = (ptr->TRIG_OUT0_CFG & (~RDC_TRIG_OUT0_CFG_LEAD_TIM_MASK)) | + RDC_TRIG_OUT0_CFG_LEAD_TIM_SET(offset + RDC_TRIG_OUT0_CFG_LEAD_TIM_MASK + 1); + } else if (chn == trigger_out_1) { + ptr->TRIG_OUT1_CFG = (ptr->TRIG_OUT1_CFG & (~RDC_TRIG_OUT1_CFG_LEAD_TIM_MASK)) | + RDC_TRIG_OUT1_CFG_LEAD_TIM_SET(offset + RDC_TRIG_OUT1_CFG_LEAD_TIM_MASK + 1); + } +} + +void rdc_output_trig_enable(RDC_Type *ptr, rdc_output_trig_chn_t chn) +{ + if (chn == trigger_out_0) { + ptr->TRIG_OUT0_CFG |= RDC_TRIG_OUT0_CFG_ENABLE_MASK; + } else if (chn == trigger_out_1) { + ptr->TRIG_OUT1_CFG |= RDC_TRIG_OUT1_CFG_ENABLE_MASK; + } +} + +void rdc_output_trig_disable(RDC_Type *ptr, rdc_output_trig_chn_t chn) +{ + if (chn == trigger_out_0) { + ptr->TRIG_OUT0_CFG &= ~RDC_TRIG_OUT0_CFG_ENABLE_MASK; + } else if (chn == trigger_out_1) { + ptr->TRIG_OUT1_CFG &= ~RDC_TRIG_OUT1_CFG_ENABLE_MASK; + } +} + +int32_t rdc_get_i_maxval(RDC_Type *ptr) +{ + uint32_t val; + + val = ptr->MAX_I; + if (RDC_MAX_I_VALID_GET(val)) { + return RDC_MAX_I_MAX_GET(val); + } else { + return -1; + } + +} + +int32_t rdc_get_i_minval(RDC_Type *ptr) +{ + uint32_t val; + + val = ptr->MIN_I; + if (RDC_MIN_I_VALID_GET(val)) { + return RDC_MIN_I_MIN_GET(val); + } else { + return -1; + } +} + +int32_t rdc_get_q_maxval(RDC_Type *ptr) +{ + uint32_t val; + + val = ptr->MAX_Q; + if (RDC_MAX_Q_VALID_GET(val)) { + return RDC_MAX_Q_MAX_GET(val); + } else { + return -1; + } +} + +int32_t rdc_get_q_minval(RDC_Type *ptr) +{ + uint32_t val; + + val = ptr->MIN_Q; + if (RDC_MIN_Q_VALID_GET(val)) { + return RDC_MIN_Q_MIN_GET(val); + } else { + return -1; + } +} + +void rdc_set_edge_detection_offset(RDC_Type *ptr, rdc_input_acc_chn_t chn, int32_t offset) +{ + if (chn == rdc_acc_chn_i) { + ptr->THRS_I = RDC_THRS_I_THRS_SET(offset); + } else { + ptr->THRS_Q = RDC_THRS_Q_THRS_SET(offset); + } +} + +void rdc_set_acc_config(RDC_Type *ptr, rdc_acc_cfg_t *cfg) +{ + ptr->EDG_DET_CTL = RDC_EDG_DET_CTL_FILTER_SET(cfg->continue_edge_num) | + RDC_EDG_DET_CTL_HOLD_SET(cfg->edge_distance); + if (cfg->right_shift_without_sign < 9) { + ptr->ACC_SCALING = RDC_ACC_SCALING_ACC_SHIFT_SET(8 - cfg->right_shift_without_sign); + } else { + ptr->ACC_SCALING = RDC_ACC_SCALING_ACC_SHIFT_SET(cfg->right_shift_without_sign); + } + if (cfg->error_data_remove) { + ptr->ACC_SCALING |= RDC_ACC_SCALING_TOXIC_LK_MASK; + } else { + ptr->ACC_SCALING &= ~RDC_ACC_SCALING_TOXIC_LK_MASK; + } + ptr->EXC_PERIOD = RDC_EXC_PERIOD_EXC_PERIOD_SET(cfg->exc_carrier_period); + ptr->SYNC_DELAY_I = RDC_SYNC_DELAY_I_DELAY_SET(cfg->sync_delay_i); + ptr->SYNC_DELAY_Q = RDC_SYNC_DELAY_Q_DELAY_SET(cfg->sync_delay_q); + ptr->AMP_MAX = RDC_AMP_MAX_MAX_SET(cfg->amp_max); + ptr->AMP_MIN = RDC_AMP_MIN_MIN_SET(cfg->amp_min); +} + +void rdc_set_acc_sync_delay(RDC_Type *ptr, rdc_input_acc_chn_t chn, uint32_t delay) +{ + if (chn == rdc_acc_chn_i) { + ptr->SYNC_DELAY_I = RDC_SYNC_DELAY_I_DELAY_SET(delay); + } else { + ptr->SYNC_DELAY_Q = RDC_SYNC_DELAY_Q_DELAY_SET(delay); + } +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rng_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rng_drv.c index d0efa75103f..c3a0565a505 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rng_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rng_drv.c @@ -69,7 +69,7 @@ static hpm_stat_t rng_rand(RNG_Type *ptr, void *buf, uint32_t count_in_byte, boo } while (!fifo_level && wait); if (fifo_level) { - *(uint32_t *)(buf + i * sizeof(uint32_t)) = ptr->FO2B; + *(uint32_t *)((uint32_t)buf + i * sizeof(uint32_t)) = ptr->FO2B; } else { stat = status_rng_not_available; break; diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rtc_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rtc_drv.c index 68d230c907f..d5ba5325765 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rtc_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rtc_drv.c @@ -21,6 +21,21 @@ time_t rtc_get_time(RTC_Type *base) return time; } +struct timeval rtc_get_timeval(RTC_Type *base) +{ + struct timeval tm; + + base->SUB_SNAP = 0; /* Lock shadow registers first */ + + /* Convert sub-second ticks into micro-second */ + uint32_t sub_sec = (uint32_t)((base->SUB_SNAP >> 17) * 1.0 * 1000000 / 32768); + + tm.tv_sec = base->SEC_SNAP; + tm.tv_usec = sub_sec; + + return tm; +} + hpm_stat_t rtc_config_alarm(RTC_Type *base, rtc_alarm_config_t *config) { hpm_stat_t status = status_invalid_argument; diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdm_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdm_drv.c index 1d5a0f72f20..14dd1462c77 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdm_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdm_drv.c @@ -14,8 +14,9 @@ void sdm_get_default_module_control(SDM_Type *ptr, sdm_control_t *control) { - control->clk_signal_sync = true; - control->data_signal_sync = true; + (void) ptr; + control->clk_signal_sync = 0xf; /*!< configure clk sync for all channels */ + control->data_signal_sync = 0xf; /*!< configure data sync for all channels */ control->interrupt_en = false; } @@ -32,6 +33,7 @@ void sdm_init_module(SDM_Type *ptr, sdm_control_t *control) void sdm_get_channel_common_setting(SDM_Type *ptr, sdm_channel_common_config_t *config) { + (void) ptr; config->sampling_mode = sdm_sampling_rising_clk_edge; config->enable_err_interrupt = false; config->enable_data_ready_interrupt = false; @@ -53,6 +55,7 @@ void sdm_config_channel_common_setting(SDM_Type *ptr, uint8_t ch_index, sdm_chan void sdm_get_channel_default_filter_config(SDM_Type *ptr, sdm_filter_config_t *filter_config) { + (void) ptr; filter_config->fifo_threshold = 8; filter_config->en_fifo_threshold_int = true; filter_config->manchester_threshold = 0; @@ -79,6 +82,7 @@ void sdm_get_channel_default_filter_config(SDM_Type *ptr, sdm_filter_config_t *f void sdm_get_channel_default_comparator_config(SDM_Type *ptr, sdm_comparator_config_t *cmp_config) { + (void) ptr; cmp_config->high_threshold = 0xffff; cmp_config->zero_cross_threshold = 0xffff; cmp_config->low_threshold = 0x0; @@ -102,7 +106,7 @@ void sdm_config_channel_filter(SDM_Type *ptr, uint8_t ch_index, sdm_filter_confi ptr->CH[ch_index].SDCTRLE = SDM_CH_SDCTRLE_SGD_ORDR_SET(filter_config->filter_type) | SDM_CH_SDCTRLE_PWMSYNC_SET(filter_config->pwm_signal_sync) | SDM_CH_SDCTRLE_CIC_SCL_SET(filter_config->output_offset) - | SDM_CH_SDCTRLE_CIC_DEC_RATIO_SET(filter_config->oversampling_rate - 1) + | SDM_CH_SDCTRLE_CIC_DEC_RATIO_SET(filter_config->oversampling_rate) | SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SET(filter_config->ignore_invalid_samples); ptr->CH[ch_index].SDCTRLP = SDM_CH_SDCTRLP_MANCH_THR_SET(filter_config->manchester_threshold) diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdp_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdp_drv.c index 97e102d0275..c05ecde37f9 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdp_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdp_drv.c @@ -510,7 +510,6 @@ static hpm_stat_t aes_ccm_auth_crypt(SDP_Type *base, uint8_t *b = (uint8_t *) &aes_ctx->buf0; uint8_t *y = (uint8_t *) &aes_ctx->buf1; uint8_t *ctr = (uint8_t *) &aes_ctx->buf2; - uint32_t i = 0; /* Format B0 */ aes_ccm_format_b0(b, iv, iv_len, tag_len, aad_len, input_len); @@ -544,7 +543,6 @@ static hpm_stat_t aes_ccm_auth_crypt(SDP_Type *base, aad_src += calc_len; remaining_len -= calc_len; /* Calculate Y(i) = CIPHk(B(i) ^ Y(i-1)) */ - ++i; sdp_aes_crypt_cbc(base, aes_ctx, sdp_aes_op_encrypt, 16, b, y, y); while (remaining_len > 0U) { @@ -556,16 +554,13 @@ static hpm_stat_t aes_ccm_auth_crypt(SDP_Type *base, aad_src += calc_len; remaining_len -= calc_len; /* Calculate Y(i) = CIPHk(B(i) ^ Y(i-1)) */ - ++i; sdp_aes_crypt_cbc(base, aes_ctx, sdp_aes_op_encrypt, 16, b, y, y); } } aes_ccm_format_ctr0(ctr, iv, iv_len); - i = 0; /* Encryption/Decryption starts from CTR1 */ sdp_increment_bn(ctr, 16); - ++i; /* Continue CBC-MAC calculation + Encryption/Decryption */ uint32_t remaining_len = input_len; uint8_t *src = (uint8_t *) input; @@ -592,7 +587,6 @@ static hpm_stat_t aes_ccm_auth_crypt(SDP_Type *base, src += calc_len; dst += calc_len; remaining_len -= calc_len; - ++i; } /* Get CTR0 */ @@ -723,6 +717,7 @@ hpm_stat_t sdp_hash_init(SDP_Type *base, sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_ static void sdp_hash_internal_engine_init(SDP_Type *base, sdp_hash_ctx_t *hash_ctx) { + (void) base; sdp_hash_internal_ctx_t *ctx_internal = (sdp_hash_internal_ctx_t *) &hash_ctx->internal; ctx_internal->hash_init = true; @@ -906,6 +901,7 @@ hpm_stat_t sdp_hash_finish(SDP_Type *base, sdp_hash_ctx_t *hash_ctx, uint8_t *di hpm_stat_t sdp_memcpy(SDP_Type *base, sdp_dma_ctx_t *dma_ctx, void *dst, const void *src, uint32_t length) { + (void) dma_ctx; hpm_stat_t status = status_invalid_argument; if (length == 0) { @@ -947,6 +943,7 @@ hpm_stat_t sdp_memcpy(SDP_Type *base, sdp_dma_ctx_t *dma_ctx, void *dst, const v hpm_stat_t sdp_memset(SDP_Type *base, sdp_dma_ctx_t *sdp_ctx, void *dst, uint8_t pattern, uint32_t length) { + (void) sdp_ctx; hpm_stat_t status; uint32_t diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdxc_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdxc_drv.c index 3e4d96e481e..46757c41704 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdxc_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdxc_drv.c @@ -25,8 +25,11 @@ enum { static const uint32_t s_sdxc_boot_dummy = 0; -static hpm_stat_t sdxc_set_transfer_config(SDXC_Type *base, uint32_t xfer_flags, - uint32_t block_size, uint32_t block_cnt, uint32_t *new_flags); +static hpm_stat_t sdxc_set_transfer_config(SDXC_Type *base, + uint32_t xfer_flags, + uint32_t block_size, + uint32_t block_cnt, + uint32_t *new_flags); static void sdxc_read_data_buf(SDXC_Type *base, uint32_t *data, uint32_t num_of_words); @@ -42,13 +45,15 @@ static hpm_stat_t sdxc_tuning_error_recovery(SDXC_Type *base); static bool sdxc_is_bus_idle(SDXC_Type *base); -static hpm_stat_t sdxc_set_transfer_config(SDXC_Type *base, uint32_t xfer_flags, - uint32_t block_size, uint32_t block_cnt, uint32_t *new_flags) +static hpm_stat_t sdxc_set_transfer_config(SDXC_Type *base, + uint32_t xfer_flags, + uint32_t block_size, + uint32_t block_cnt, + uint32_t *new_flags) { uint32_t flags = base->CMD_XFER & ~(SDXC_CMD_XFER_MULTI_BLK_SEL_MASK | SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK | SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK | SDXC_CMD_XFER_DATA_XFER_DIR_MASK | - SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK | - SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK); + SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK | SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK); if (IS_HPM_BITMASK_SET(base->PSTATE, SDXC_PSTATE_CMD_INHIBIT_MASK)) { return status_sdxc_busy; } else { @@ -107,10 +112,14 @@ hpm_stat_t sdxc_receive_cmd_response(SDXC_Type *base, sdxc_command_t *cmd) /* R3-R2-R1-R0 (lowest 8 bits are invalid bits) has the same format as R2 format in SD spec * after removing internal CRC7 and end bit */ - cmd->response[0] = (base->RESP[0] << 8); - cmd->response[1] = (base->RESP[1] << 8) | (base->RESP[0] >> 24); - cmd->response[2] = (base->RESP[2] << 8) | (base->RESP[1] >> 24); - cmd->response[3] = (base->RESP[3] << 8) | (base->RESP[2] >> 24); + uint32_t resp0 = base->RESP[0]; + uint32_t resp1 = base->RESP[1]; + uint32_t resp2 = base->RESP[2]; + uint32_t resp3 = base->RESP[3]; + cmd->response[0] = (resp0 << 8); + cmd->response[1] = (resp1 << 8) | (resp0 >> 24); + cmd->response[2] = (resp2 << 8) | (resp1 >> 24); + cmd->response[3] = (resp3 << 8) | (resp2 >> 24); } if (SDXC_CMD_XFER_AUTO_CMD_ENABLE_GET(base->CMD_XFER) == sdxc_auto_cmd12_enabled) { @@ -281,7 +290,7 @@ hpm_stat_t sdxc_send_command(SDXC_Type *base, sdxc_command_t *cmd) uint32_t cmd_xfer = base->CMD_XFER; uint32_t flags = cmd->cmd_flags; - int32_t wait_cnt = 1000000L; + uint32_t wait_cnt = 1000000L; while (!sdxc_is_bus_idle(base) && (wait_cnt > 0U)) { wait_cnt--; @@ -326,20 +335,24 @@ hpm_stat_t sdxc_send_command(SDXC_Type *base, sdxc_command_t *cmd) break; } - cmd_xfer &= ~(SDXC_CMD_XFER_CMD_INDEX_MASK | SDXC_CMD_XFER_CMD_TYPE_MASK | SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK - | SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK | SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK | + cmd_xfer &= ~(SDXC_CMD_XFER_CMD_INDEX_MASK | SDXC_CMD_XFER_CMD_TYPE_MASK | SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK | + SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK | SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK | SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK | SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK | SDXC_CMD_XFER_DATA_XFER_DIR_MASK | SDXC_CMD_XFER_DMA_ENABLE_MASK | SDXC_CMD_XFER_MULTI_BLK_SEL_MASK | SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK); - cmd_xfer |= SDXC_CMD_XFER_CMD_INDEX_SET(cmd->cmd_index) | - ((flags & (SDXC_CMD_XFER_CMD_TYPE_MASK | SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK - | SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK | SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK | - SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK | SDXC_CMD_XFER_DMA_ENABLE_MASK | - SDXC_CMD_XFER_DATA_XFER_DIR_MASK | SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK | - SDXC_CMD_XFER_MULTI_BLK_SEL_MASK | SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK | - SDXC_CMD_XFER_RESP_TYPE_MASK | - SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK))); + cmd_xfer |= SDXC_CMD_XFER_CMD_INDEX_SET(cmd->cmd_index) | ((flags & (SDXC_CMD_XFER_CMD_TYPE_MASK | + SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK | + SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK | + SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK | + SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK | + SDXC_CMD_XFER_DMA_ENABLE_MASK | + SDXC_CMD_XFER_DATA_XFER_DIR_MASK | + SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK | + SDXC_CMD_XFER_MULTI_BLK_SEL_MASK | + SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK | + SDXC_CMD_XFER_RESP_TYPE_MASK | + SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK))); base->CMD_ARG = cmd->cmd_argument; base->CMD_XFER = cmd_xfer; @@ -516,10 +529,8 @@ void sdxc_init(SDXC_Type *base, const sdxc_config_t *config) void sdxc_set_data_timeout(SDXC_Type *base, uint32_t timeout_in_ms, uint32_t *actual_timeout_ms) { - static uint32_t pre_calc_timeout_list[15] = { - 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, - 32768, 65536, 131072 - }; + static uint32_t pre_calc_timeout_list[15] = {8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, + 65536, 131072}; uint32_t field_value = 0; for (uint32_t i = 0; i < ARRAY_SIZE(pre_calc_timeout_list); i++) { @@ -556,8 +567,8 @@ void sdxc_set_mmc_boot_config(SDXC_Type *base, const sdxc_boot_config_t *config) uint32_t block_attr_reg = base->BLK_ATTR & ~(SDXC_BLK_ATTR_XFER_BLOCK_SIZE_MASK | SDXC_BLK_ATTR_BLOCK_CNT_MASK); - block_attr_reg |= SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SET(config->block_size) | - SDXC_BLK_ATTR_BLOCK_CNT_SET(config->block_cnt); + block_attr_reg |= + SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SET(config->block_size) | SDXC_BLK_ATTR_BLOCK_CNT_SET(config->block_cnt); base->BLK_ATTR = block_attr_reg; base->EMMC_BOOT_CTRL = emmc_boot_reg; @@ -578,9 +589,12 @@ void sdxc_set_data_config(SDXC_Type *base, sdxc_xfer_direction_t data_dir, uint3 } } -hpm_stat_t sdxc_set_dma_config(SDXC_Type *base, sdxc_adma_config_t *dma_cfg, const uint32_t *data_addr, +hpm_stat_t sdxc_set_dma_config(SDXC_Type *base, + sdxc_adma_config_t *dma_cfg, + const uint32_t *data_addr, bool enable_auto_cmd23) { + (void) enable_auto_cmd23; if (dma_cfg->dma_type == sdxc_dmasel_sdma) { if (((uint32_t) data_addr % SDXC_SYS_DMA_ALIGN_LEN) != 0U) { @@ -600,8 +614,11 @@ hpm_stat_t sdxc_set_dma_config(SDXC_Type *base, sdxc_adma_config_t *dma_cfg, con } -hpm_stat_t sdxc_set_adma2_desc(uint32_t *adma_tbl, uint32_t adma_table_words, const uint32_t *data_buf, - uint32_t data_bytes, uint32_t flags) +hpm_stat_t sdxc_set_adma2_desc(uint32_t *adma_tbl, + uint32_t adma_table_words, + const uint32_t *data_buf, + uint32_t data_bytes, + uint32_t flags) { hpm_stat_t status = status_invalid_argument; do { @@ -682,8 +699,10 @@ hpm_stat_t sdxc_set_adma2_desc(uint32_t *adma_tbl, uint32_t adma_table_words, co return status; } -hpm_stat_t sdxc_set_adma_table_config(SDXC_Type *base, sdxc_adma_config_t *dma_cfg, - sdxc_data_t *data_cfg, uint32_t flags) +hpm_stat_t sdxc_set_adma_table_config(SDXC_Type *base, + sdxc_adma_config_t *dma_cfg, + sdxc_data_t *data_cfg, + uint32_t flags) { hpm_stat_t status = status_fail; @@ -754,10 +773,10 @@ void sdxc_select_voltage(SDXC_Type *base, sdxc_bus_voltage_option_t option) { uint32_t option_u32 = (uint32_t) option; - base->PROT_CTRL = (base->PROT_CTRL & ~SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK) | - SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SET(option_u32); + base->PROT_CTRL = + (base->PROT_CTRL & ~SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK) | SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SET(option_u32); - if ((option == sdxc_bus_voltage_sd_1v8) || (option == sdxc_bus_voltage_emmc_1v8)) { + if (option == sdxc_bus_voltage_sd_1v8) { base->AC_HOST_CTRL |= SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK; } else { base->AC_HOST_CTRL &= ~SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK; @@ -812,8 +831,8 @@ void sdxc_set_speed_mode(SDXC_Type *base, sdxc_speed_mode_t mode) { uint32_t mode_u32 = (uint32_t) mode; - base->AC_HOST_CTRL = (base->AC_HOST_CTRL & ~SDXC_AC_HOST_CTRL_UHS_MODE_SEL_MASK) | - SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SET(mode_u32); + base->AC_HOST_CTRL = + (base->AC_HOST_CTRL & ~SDXC_AC_HOST_CTRL_UHS_MODE_SEL_MASK) | SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SET(mode_u32); if ((mode_u32 & 0xFU) > sdxc_sd_speed_sdr12) { base->PROT_CTRL |= SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK; } else { @@ -981,7 +1000,7 @@ hpm_stat_t sdxc_perform_tuning_flow_sequence(SDXC_Type *base, uint8_t tuning_cmd do { base->BLK_ATTR = block_size; base->SDMASA = 1; - sdxc_send_command(base, &cmd); + status = sdxc_send_command(base, &cmd); while (!IS_HPM_BITMASK_SET(base->INT_STAT, SDXC_INT_STAT_BUF_RD_READY_MASK)) { } sdxc_clear_interrupt_status(base, SDXC_INT_STAT_BUF_RD_READY_MASK); @@ -1052,7 +1071,7 @@ hpm_stat_t sdxc_perform_software_tuning(SDXC_Type *base, uint8_t tuning_cmd) int32_t first_window_idx = -1; int32_t last_window_idx = -1; - for (int32_t i = 0; i < ARRAY_SIZE(center_phase_codes_valid); i++) { + for (int32_t i = 0; i < (int32_t) ARRAY_SIZE(center_phase_codes_valid); i++) { if (center_phase_codes_valid[i]) { first_window_idx = i; break; diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sei_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sei_drv.c new file mode 100644 index 00000000000..5caf2d7839a --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sei_drv.c @@ -0,0 +1,380 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_sei_drv.h" + +hpm_stat_t sei_tranceiver_config_init(SEI_Type *ptr, uint8_t idx, sei_tranceiver_config_t *config) +{ + uint32_t tmp; + uint32_t baudrate; + uint32_t baud_div; + uint32_t sync_point; + uint8_t data_len; + uint32_t ck0_point; + uint32_t ck1_point; + uint32_t txd_point; + uint32_t rxd_point; + + tmp = SEI_CTRL_XCVR_CTRL_TRISMP_SET(config->tri_sample) + | SEI_CTRL_XCVR_CTRL_MODE_SET(config->mode); + ptr->CTRL[idx].XCVR.CTRL = tmp; + + switch (config->mode) { + case sei_synchronous_master_mode: + tmp = SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SET(config->synchronous_master_config.data_idle_high_z) + | SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SET(config->synchronous_master_config.data_idle_state) + | SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SET(config->synchronous_master_config.clock_idle_high_z) + | SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SET(config->synchronous_master_config.clock_idle_state); + ptr->CTRL[idx].XCVR.TYPE_CFG = tmp; + + baud_div = (config->src_clk_freq + (config->synchronous_master_config.baudrate >> 1u)) / config->synchronous_master_config.baudrate; + sync_point = baud_div >> 1u; + tmp = SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SET(sync_point) + | SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SET(baud_div - 1u); + ptr->CTRL[idx].XCVR.BAUD_CFG = tmp; + + ck0_point = baud_div >> 2u; + ck1_point = ck0_point * 3u; + tmp = SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SET(ck0_point) + | SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SET(ck1_point); + ptr->CTRL[idx].XCVR.CLK_CFG = tmp; + break; + + case sei_synchronous_slave_mode: + tmp = SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SET(config->synchronous_slave_config.data_idle_high_z) + | SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SET(config->synchronous_slave_config.data_idle_state) + | SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SET(config->synchronous_slave_config.clock_idle_high_z) + | SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SET(config->synchronous_slave_config.clock_idle_state); + ptr->CTRL[idx].XCVR.TYPE_CFG = tmp; + + baud_div = (config->src_clk_freq + (config->synchronous_slave_config.max_baudrate >> 1u)) / config->synchronous_slave_config.max_baudrate; + sync_point = (baud_div * 3u) >> 3u; + tmp = SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SET(sync_point) + | SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SET(baud_div - 1u); + ptr->CTRL[idx].XCVR.BAUD_CFG = tmp; + + ck0_point = config->synchronous_slave_config.ck0_timeout_us * (config->src_clk_freq / 1000000u); + if (ck0_point > 0x7FFFu) { + ck0_point = 0x7FFFu; + } + ck1_point = config->synchronous_slave_config.ck1_timeout_us * (config->src_clk_freq / 1000000u); + if (ck1_point > 0x7FFFu) { + ck1_point = 0x7FFFu; + } + ck1_point += 0x8000u; + tmp = SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SET(ck0_point) + | SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SET(ck1_point); + ptr->CTRL[idx].XCVR.CLK_CFG = tmp; + break; + + case sei_asynchronous_mode: + default: + data_len = config->asynchronous_config.data_len; + if (data_len > 0u) { + data_len--; + } + tmp = SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SET(config->asynchronous_config.wait_len) + | SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SET(data_len) + | SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SET(config->asynchronous_config.parity) + | SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SET(config->asynchronous_config.parity_enable) + | SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SET(config->asynchronous_config.data_idle_high_z) + | SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SET(config->asynchronous_config.data_idle_state); + ptr->CTRL[idx].XCVR.TYPE_CFG = tmp; + + baudrate = (config->asynchronous_config.baudrate / 100) * 102; + baud_div = (config->src_clk_freq + (baudrate >> 1u)) / baudrate; + sync_point = (baud_div + 2u); + tmp = SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SET(sync_point) + | SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SET(baud_div - 1u); + ptr->CTRL[idx].XCVR.BAUD_CFG = tmp; + + txd_point = 0; + rxd_point = baud_div >> 1u; + tmp = SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SET(txd_point) + | SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SET(rxd_point); + ptr->CTRL[idx].XCVR.DATA_CFG = tmp; + break; + } + + return status_success; +} + +hpm_stat_t sei_cmd_data_format_config_init(SEI_Type *ptr, bool cmd_data_select, uint8_t idx, sei_data_format_config_t *config) +{ + uint32_t tmp; + uint8_t word_len; + uint8_t crc_len; + + word_len = config->word_len; + if (word_len > 0u) { + word_len--; + } + crc_len = config->crc_len; + if (crc_len > 0u) { + crc_len--; + } + tmp = SEI_DAT_MODE_MODE_SET(config->mode) + | SEI_DAT_MODE_SIGNED_SET(config->signed_flag) + | SEI_DAT_MODE_BORDER_SET(config->bit_order) + | SEI_DAT_MODE_WORDER_SET(config->word_order) + | SEI_DAT_MODE_CRC_INV_SET(config->crc_invert) + | SEI_DAT_MODE_CRC_SHIFT_SET(config->crc_shift_mode) + | SEI_DAT_MODE_WLEN_SET(word_len) + | SEI_DAT_MODE_CRC_LEN_SET(crc_len); + if (cmd_data_select) { + ptr->CTRL[idx].CMD.MODE = tmp; + } else { + ptr->DAT[idx].MODE = tmp; + } + + tmp = SEI_DAT_IDX_LAST_BIT_SET(config->last_bit) + | SEI_DAT_IDX_FIRST_BIT_SET(config->first_bit) + | SEI_DAT_IDX_MAX_BIT_SET(config->max_bit) + | SEI_DAT_IDX_MIN_BIT_SET(config->min_bit); + if (cmd_data_select) { + ptr->CTRL[idx].CMD.IDX = tmp; + } else { + ptr->DAT[idx].IDX = tmp; + } + + tmp = SEI_DAT_GOLD_GOLD_VALUE_SET(config->gold_value); + if (cmd_data_select) { + ptr->CTRL[idx].CMD.GOLD = tmp; + } else { + ptr->DAT[idx].GOLD = tmp; + } + + tmp = SEI_DAT_CRCINIT_CRC_INIT_SET(config->crc_init_value); + if (cmd_data_select) { + ptr->CTRL[idx].CMD.CRCINIT = tmp; + } else { + ptr->DAT[idx].CRCINIT = tmp; + } + + tmp = SEI_DAT_CRCPOLY_CRC_POLY_SET(config->crc_poly); + if (cmd_data_select) { + ptr->CTRL[idx].CMD.CRCPOLY = tmp; + } else { + ptr->DAT[idx].CRCPOLY = tmp; + } + + if (cmd_data_select) { + ptr->CTRL[idx].CMD.MODE |= SEI_CTRL_CMD_MODE_REWIND_MASK; + } else { + ptr->DAT[idx].MODE |= SEI_DAT_MODE_REWIND_MASK; + } + + return status_success; +} + +hpm_stat_t sei_cmd_table_config_init(SEI_Type *ptr, uint8_t idx, uint8_t table_idx, sei_command_table_config_t *config) +{ + uint32_t tmp; + + tmp = SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SET(config->cmd_min_value); + ptr->CTRL[idx].CMD_TABLE[table_idx].MIN = tmp; + + tmp = SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SET(config->cmd_max_value); + ptr->CTRL[idx].CMD_TABLE[table_idx].MAX = tmp; + + tmp = SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SET(config->cmd_mask_value); + ptr->CTRL[idx].CMD_TABLE[table_idx].MSK = tmp; + + tmp = SEI_CTRL_CMD_TABLE_PTA_PTR3_SET(config->instr_idx[3]) + | SEI_CTRL_CMD_TABLE_PTA_PTR2_SET(config->instr_idx[2]) + | SEI_CTRL_CMD_TABLE_PTA_PTR1_SET(config->instr_idx[1]) + | SEI_CTRL_CMD_TABLE_PTA_PTR0_SET(config->instr_idx[0]); + ptr->CTRL[idx].CMD_TABLE[table_idx].PTA = tmp; + + tmp = SEI_CTRL_CMD_TABLE_PTB_PTR7_SET(config->instr_idx[7]) + | SEI_CTRL_CMD_TABLE_PTB_PTR6_SET(config->instr_idx[6]) + | SEI_CTRL_CMD_TABLE_PTB_PTR5_SET(config->instr_idx[5]) + | SEI_CTRL_CMD_TABLE_PTB_PTR4_SET(config->instr_idx[4]); + ptr->CTRL[idx].CMD_TABLE[table_idx].PTB = tmp; + + tmp = SEI_CTRL_CMD_TABLE_PTC_PTR11_SET(config->instr_idx[11]) + | SEI_CTRL_CMD_TABLE_PTC_PTR10_SET(config->instr_idx[10]) + | SEI_CTRL_CMD_TABLE_PTC_PTR9_SET(config->instr_idx[9]) + | SEI_CTRL_CMD_TABLE_PTC_PTR8_SET(config->instr_idx[8]); + ptr->CTRL[idx].CMD_TABLE[table_idx].PTC = tmp; + + tmp = SEI_CTRL_CMD_TABLE_PTD_PTR15_SET(config->instr_idx[15]) + | SEI_CTRL_CMD_TABLE_PTD_PTR14_SET(config->instr_idx[14]) + | SEI_CTRL_CMD_TABLE_PTD_PTR13_SET(config->instr_idx[13]) + | SEI_CTRL_CMD_TABLE_PTD_PTR12_SET(config->instr_idx[12]); + ptr->CTRL[idx].CMD_TABLE[table_idx].PTD = tmp; + + return status_success; +} + +hpm_stat_t sei_state_transition_config_init(SEI_Type *ptr, uint8_t idx, uint8_t latch_idx, uint8_t state, sei_state_transition_config_t *config) +{ + uint32_t tmp = 0x08u; + + tmp |= SEI_CTRL_LATCH_TRAN_POINTER_SET(config->instr_ptr_value) + | SEI_CTRL_LATCH_TRAN_CFG_TM_SET(config->timeout_cfg) + | SEI_CTRL_LATCH_TRAN_CFG_TXD_SET(config->txd_cfg) + | SEI_CTRL_LATCH_TRAN_CFG_CLK_SET(config->clk_cfg) + | SEI_CTRL_LATCH_TRAN_CFG_PTR_SET(config->instr_ptr_cfg) + | SEI_CTRL_LATCH_TRAN_OV_TM_SET(config->disable_timeout_check) + | SEI_CTRL_LATCH_TRAN_OV_TXD_SET(config->disable_txd_check) + | SEI_CTRL_LATCH_TRAN_OV_CLK_SET(config->disable_clk_check) + | SEI_CTRL_LATCH_TRAN_OV_PTR_SET(config->disable_instr_ptr_check); + ptr->CTRL[idx].LATCH[latch_idx].TRAN[state] = tmp; + + return status_success; +} + +hpm_stat_t sei_state_transition_latch_config_init(SEI_Type *ptr, uint8_t idx, uint8_t latch_idx, sei_state_transition_latch_config_t *config) +{ + uint32_t tmp; + + tmp = SEI_CTRL_LATCH_CFG_DELAY_SET(config->delay) + | SEI_CTRL_LATCH_CFG_SELECT_SET(config->output_select) + | SEI_CTRL_LATCH_CFG_EN_SET(config->enable); + ptr->CTRL[idx].LATCH[latch_idx].CFG = tmp; + + return status_success; +} + +hpm_stat_t sei_sample_config_init(SEI_Type *ptr, uint8_t idx, sei_sample_config_t *config) +{ + uint32_t tmp; + + tmp = SEI_CTRL_POS_SMP_CFG_ONCE_SET(config->sample_once) + | SEI_CTRL_POS_SMP_CFG_LAT_SEL_SET(config->latch_select) + | SEI_CTRL_POS_SMP_CFG_WINDOW_SET(config->sample_window); + ptr->CTRL[idx].POS.SMP_CFG = tmp; + + ptr->CTRL[idx].POS.SMP_DAT = SEI_CTRL_POS_SMP_DAT_DAT_SEL_SET(config->data_register_select); + + tmp = SEI_CTRL_POS_SMP_EN_ACC_EN_SET(config->acc_data_use_rx) + | SEI_CTRL_POS_SMP_EN_ACC_SEL_SET(config->acc_data_idx) + | SEI_CTRL_POS_SMP_EN_SPD_EN_SET(config->spd_data_use_rx) + | SEI_CTRL_POS_SMP_EN_SPD_SEL_SET(config->spd_data_idx) + | SEI_CTRL_POS_SMP_EN_REV_EN_SET(config->rev_data_use_rx) + | SEI_CTRL_POS_SMP_EN_REV_SEL_SET(config->rev_data_idx) + | SEI_CTRL_POS_SMP_EN_POS_EN_SET(config->pos_data_use_rx) + | SEI_CTRL_POS_SMP_EN_POS_SEL_SET(config->pos_data_idx); + ptr->CTRL[idx].POS.SMP_EN = tmp; + + return status_success; +} + +hpm_stat_t sei_update_config_init(SEI_Type *ptr, uint8_t idx, sei_update_config_t *config) +{ + uint32_t tmp; + + tmp = SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SET(config->time_use_override) + | SEI_CTRL_POS_UPD_CFG_ONERR_SET(config->update_on_err) + | SEI_CTRL_POS_UPD_CFG_LAT_SEL_SET(config->latch_select); + ptr->CTRL[idx].POS.UPD_CFG = tmp; + + ptr->CTRL[idx].POS.UPD_DAT = SEI_CTRL_POS_UPD_DAT_DAT_SEL_SET(config->data_register_select); + + tmp = SEI_CTRL_POS_UPD_EN_ACC_EN_SET(config->acc_data_use_rx) + | SEI_CTRL_POS_UPD_EN_ACC_SEL_SET(config->acc_data_idx) + | SEI_CTRL_POS_UPD_EN_SPD_EN_SET(config->spd_data_use_rx) + | SEI_CTRL_POS_UPD_EN_SPD_SEL_SET(config->spd_data_idx) + | SEI_CTRL_POS_UPD_EN_REV_EN_SET(config->rev_data_use_rx) + | SEI_CTRL_POS_UPD_EN_REV_SEL_SET(config->rev_data_idx) + | SEI_CTRL_POS_UPD_EN_POS_EN_SET(config->pos_data_use_rx) + | SEI_CTRL_POS_UPD_EN_POS_SEL_SET(config->pos_data_idx); + ptr->CTRL[idx].POS.UPD_EN = tmp; + + return status_success; +} + +hpm_stat_t sei_trigger_input_config_init(SEI_Type *ptr, uint8_t idx, sei_trigger_input_config_t *config) +{ + uint32_t tmp; + uint32_t period; + + tmp = SEI_CTRL_TRG_PRD_CFG_ARMING_SET(config->trig_period_arming_mode) + | SEI_CTRL_TRG_PRD_CFG_SYNC_SET(config->trig_period_sync_enable); + ptr->CTRL[idx].TRG.PRD_CFG = tmp; + + period = config->trig_period_time; + if (period > 0) { + period--; + } + ptr->CTRL[idx].TRG.PRD = SEI_CTRL_TRG_PRD_PERIOD_SET(period); + + tmp = SEI_CTRL_TRG_IN_CFG_PRD_EN_SET(config->trig_period_enable) + | SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SET(config->trig_period_sync_select) + | SEI_CTRL_TRG_IN_CFG_IN1_EN_SET(config->trig_in1_enable) + | SEI_CTRL_TRG_IN_CFG_IN1_SEL_SET(config->trig_in1_select) + | SEI_CTRL_TRG_IN_CFG_IN0_EN_SET(config->trig_in0_enable) + | SEI_CTRL_TRG_IN_CFG_IN0_SEL_SET(config->trig_in0_select); + ptr->CTRL[idx].TRG.IN_CFG = tmp; + + return status_success; +} + +hpm_stat_t sei_trigger_output_config_init(SEI_Type *ptr, uint8_t idx, sei_trigger_output_config_t *config) +{ + uint32_t tmp; + + tmp = ptr->CTRL[idx].TRG.OUT_CFG; + if (config->src_latch_select == SEI_LATCH_0) { + tmp &= ~(SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK | SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK); + tmp |= SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SET(config->trig_out_enable) | SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SET(config->trig_out_select); + } else if (config->src_latch_select == SEI_LATCH_1) { + tmp &= ~(SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK | SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK); + tmp |= SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SET(config->trig_out_enable) | SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SET(config->trig_out_select); + } else if (config->src_latch_select == SEI_LATCH_2) { + tmp &= ~(SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK | SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK); + tmp |= SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SET(config->trig_out_enable) | SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SET(config->trig_out_select); + } else if (config->src_latch_select == SEI_LATCH_3) { + tmp &= ~(SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK | SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK); + tmp |= SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SET(config->trig_out_enable) | SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SET(config->trig_out_select); + } else { + return status_invalid_argument; + } + ptr->CTRL[idx].TRG.OUT_CFG = tmp; + + return status_success; +} + +hpm_stat_t sei_engine_config_init(SEI_Type *ptr, uint8_t idx, sei_engine_config_t *config) +{ + uint32_t tmp; + + tmp = SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SET(config->data_cdm_idx) + | SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SET(config->data_base_idx) + | SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SET(config->wdg_instr_idx) + | SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SET(config->init_instr_idx); + ptr->CTRL[idx].ENGINE.PTR_CFG = tmp; + + ptr->CTRL[idx].ENGINE.WDG_CFG = SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SET(config->wdg_time); + + tmp = SEI_CTRL_ENGINE_CTRL_WATCH_SET(config->wdg_enable) + | SEI_CTRL_ENGINE_CTRL_EXCEPT_SET(config->wdg_action) + | SEI_CTRL_ENGINE_CTRL_ARMING_SET(config->arming_mode); + ptr->CTRL[idx].ENGINE.CTRL = tmp; + + return status_success; +} + +void sei_set_instr(SEI_Type *ptr, uint8_t idx, uint8_t op, uint8_t ck, uint8_t crc, uint8_t data, uint8_t opr) +{ + uint32_t tmp; + + if ((op != SEI_INSTR_OP_HALT) && (op != SEI_INSTR_OP_JUMP) && (opr > 0)) { + opr--; + } + if (opr > 0x1F) { + opr = 0x1F; + } + tmp = SEI_INSTR_OP_SET(op) + | SEI_INSTR_CK_SET(ck) + | SEI_INSTR_CRC_SET(crc) + | SEI_INSTR_DAT_SET(data) + | SEI_INSTR_OPR_SET(opr); + + ptr->INSTR[idx] = tmp; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_smix_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_smix_drv.c new file mode 100644 index 00000000000..c3e0bd9d4f5 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_smix_drv.c @@ -0,0 +1,233 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_smix_drv.h" + +void smix_get_dma_default_ch_config(SMIX_Type *ptr, smix_dma_ch_config_t *config) +{ + (void) ptr; + config->priority = 0; + config->src_mode = smix_dma_mode_normal; + config->dst_mode = smix_dma_mode_normal; + config->src_width = smix_dma_transfer_half_word; + config->dst_width = smix_dma_transfer_half_word; + config->src_addr_ctrl = smix_dma_address_increment; + config->dst_addr_ctrl = smix_dma_address_increment; + config->src_burst_size = smix_dma_transfer_burst_1t; + config->trans_bytes = 0; + config->linked_ptr = 0; + config->src_req_sel = 0; + config->dst_req_sel = 0; + + config->abort_int_en = false; + config->error_int_en = false; + config->complete_int_en = false; +} + + +void smix_get_mixer_dst_ch_default_config(SMIX_Type *ptr, smix_mixer_dst_config_t *config) +{ + (void) ptr; + config->underflow_int_en = false; + config->fifo_thr = 8; /* Must be greater than or equal to 8 */ + config->calsat_int_en = false; + config->da_int_en = false; + config->auto_deactivate_en = false; + config->fadeout_done_int_en = false; + config->deactivate_en = false; + config->active_en = true; + config->fadeout_now_en = false; + config->fadeout_auto_en = false; + config->fadein_en = false; + config->channel_en = true; + config->mixer_en = true; + + config->gain = smix_mixer_gain_0db; + config->length = 0; /* 0 = infinite length */ + config->fadein_delta = 6; /* 48K sample rate, need 3s */ + config->fadeout_delta = 14; /* 48K sample rate, need 1/3s */ + config->src_ch_mask = 0x1; +} + +void smix_get_mixer_source_ch_default_config(SMIX_Type *ptr, smix_mixer_source_config_t *config) +{ + (void) ptr; + config->fifo_thr = 4; /* Must be greater than or equal to 4 */ + config->calsat_int_en = false; + config->dn_int_en = false; + config->fir_shift = 0; + config->auto_deactivate_en = true; + config->fadeout_int_en = false; + + config->convert_rate = smix_mixer_no_rate_convert; + config->gain = smix_mixer_gain_0db; + config->fadein_delta = 6; /* 48K sample rate, need 3s */ + config->fadeout_delta = 14; /* 48K sample rate, need 1/3s */ + config->length = 0; /* 0 = infinite length */ +} + +hpm_stat_t smix_config_dma_channel(SMIX_Type *ptr, uint8_t ch, smix_dma_ch_config_t *config, bool start) +{ + uint32_t tmp; + + if ((config->trans_bytes & ((1 << config->dst_width) - 1)) + || (config->src_addr & ((1 << config->src_width) - 1)) + || (config->dst_addr & ((1 << config->dst_width) - 1)) + || (config->linked_ptr & 0x7)) { + return status_invalid_argument; + } + + ptr->DMA_CH[ch].SRCADDR = SMIX_DMA_CH_SRCADDR_PTR_SET(config->src_addr); + ptr->DMA_CH[ch].DSTADDR = SMIX_DMA_CH_DSTADDR_PTR_SET(config->dst_addr); + ptr->DMA_CH[ch].BURST_COUNT = SMIX_DMA_CH_BURST_COUNT_NUM_SET(config->trans_bytes >> config->src_width); + ptr->DMA_CH[ch].LLP = SMIX_DMA_CH_LLP_PTR_SET(config->linked_ptr); + + /* clear status bit, W1C */ + ptr->DMAC_ERR_ST = 1 << ch; + ptr->DMAC_ABRT_ST = 1 << ch; + ptr->DMAC_TC_ST = 1 << ch; + + tmp = SMIX_DMA_CH_CTL_SRCREQSEL_SET(config->src_req_sel) + | SMIX_DMA_CH_CTL_DSTREQSEL_SET(config->dst_req_sel) + | SMIX_DMA_CH_CTL_PRIORITY_SET(config->priority) + | SMIX_DMA_CH_CTL_SRCBURSTSIZE_SET(config->src_burst_size) + | SMIX_DMA_CH_CTL_SRCWIDTH_SET(config->src_width) + | SMIX_DMA_CH_CTL_DSTWIDTH_SET(config->dst_width) + | SMIX_DMA_CH_CTL_SRCMODE_SET(config->src_mode) + | SMIX_DMA_CH_CTL_DSTMODE_SET(config->dst_mode) + | SMIX_DMA_CH_CTL_SRCADDRCTRL_SET(config->src_addr_ctrl) + | SMIX_DMA_CH_CTL_DSTADDRCTRL_SET(config->dst_addr_ctrl) + | SMIX_DMA_CH_CTL_ABRT_INT_EN_SET(config->abort_int_en) + | SMIX_DMA_CH_CTL_ERR_INT_EN_SET(config->error_int_en) + | SMIX_DMA_CH_CTL_TC_INT_EN_SET(config->complete_int_en); + + if (start) { + tmp |= SMIX_DMA_CH_CTL_EN_MASK; + } + ptr->DMA_CH[ch].CTL = tmp; + + return status_success; +} + +hpm_stat_t smix_mixer_config_source_ch(SMIX_Type *ptr, uint8_t ch, smix_mixer_source_config_t *src) +{ + /* reset fifo */ + ptr->SOURCE_CH[ch].CTRL |= SMIX_SOURCE_CH_CTRL_FIFO_RESET_MASK; + ptr->SOURCE_CH[ch].CTRL &= ~SMIX_SOURCE_CH_CTRL_FIFO_RESET_MASK; + + ptr->SOURCE_CH[ch].CTRL = SMIX_SOURCE_CH_CTRL_THRSH_SET(src->fifo_thr) + | SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_SET(src->calsat_int_en) + | SMIX_SOURCE_CH_CTRL_DN_INT_EN_SET(src->dn_int_en) + | SMIX_SOURCE_CH_CTRL_SHFT_CTRL_SET(src->fir_shift) + | SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_SET(src->auto_deactivate_en) + | SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_SET(src->fadeout_int_en) + | SMIX_SOURCE_CH_CTRL_RATECONV_SET(src->convert_rate); + + ptr->SOURCE_CH[ch].GAIN = SMIX_SOURCE_CH_GAIN_VAL_SET(src->gain); + + ptr->SOURCE_CH[ch].FADEIN = SMIX_SOURCE_CH_FADEIN_DELTA_SET(src->fadein_delta); + + ptr->SOURCE_CH[ch].FADEOUT = SMIX_SOURCE_CH_FADEOUT_DELTA_SET(src->fadeout_delta); + + if (src->length == 0) { + ptr->SOURCE_CH[ch].BUFSIZE = SMIX_SOURCE_CH_BUFSIZE_MAXIDX_SET(0); + } else { + ptr->SOURCE_CH[ch].BUFSIZE = SMIX_SOURCE_CH_BUFSIZE_MAXIDX_SET(src->length - 1); + } + + return status_success; +} + + +hpm_stat_t smix_mixer_config_dst_ch(SMIX_Type *ptr, uint8_t ch, smix_mixer_dst_config_t *dst) +{ + /* Reset */ + ptr->DST_CH[ch].CTRL |= SMIX_DST_CH_CTRL_SOFTRST_MASK; + ptr->DST_CH[ch].CTRL &= ~SMIX_DST_CH_CTRL_SOFTRST_MASK; + + ptr->DST_CH[ch].GAIN = SMIX_DST_CH_GAIN_VAL_SET(dst->gain); + + if (dst->length == 0) { + ptr->DST_CH[ch].BUFSIZE = SMIX_DST_CH_BUFSIZE_MAX_IDX_SET(0); + } else { + ptr->DST_CH[ch].BUFSIZE = SMIX_DST_CH_BUFSIZE_MAX_IDX_SET(dst->length - 1); + } + + ptr->DST_CH[ch].FADEIN = SMIX_DST_CH_FADEIN_DELTA_SET(dst->fadein_delta); + + ptr->DST_CH[ch].FADEOUT = SMIX_DST_CH_FADEOUT_DELTA_SET(dst->fadeout_delta); + + ptr->DST_CH[ch].SOURCE_EN = dst->src_ch_mask; + ptr->DST_CH[ch].SOURCE_ACT = dst->src_ch_mask; + + ptr->DST_CH[ch].CTRL = SMIX_DST_CH_CTRL_DATA_UNFL_IE_SET(dst->underflow_int_en) + | SMIX_DST_CH_CTRL_THRSH_SET(dst->fifo_thr) + | SMIX_DST_CH_CTRL_CALSAT_INT_EN_SET(dst->calsat_int_en) + | SMIX_DST_CH_CTRL_DA_INT_EN_SET(dst->da_int_en) + | SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_SET(dst->auto_deactivate_en) + | SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_SET(dst->fadeout_done_int_en) + | SMIX_DST_CH_CTRL_DST_DEACT_SET(dst->deactivate_en) + | SMIX_DST_CH_CTRL_DST_ACT_SET(dst->active_en) + | SMIX_DST_CH_CTRL_DSTFADOUT_MEN_SET(dst->fadeout_now_en) + | SMIX_DST_CH_CTRL_DSTFADOUT_AEN_SET(dst->fadeout_auto_en) + | SMIX_DST_CH_CTRL_DSTFADIN_EN_SET(dst->fadein_en) + | SMIX_DST_CH_CTRL_DST_EN_SET(dst->channel_en); + + /* Workaround: DST_CH[0].CTRL.MIXER_EN bit controls mixer module enable or disable, DST_CH[1].CTRL.MIXER_EN should not be set */ + if (dst->mixer_en) { + ptr->DST_CH[0].CTRL |= SMIX_DST_CH_CTRL_MIXER_EN_MASK; + ptr->DST_CH[1].CTRL &= ~SMIX_DST_CH_CTRL_MIXER_EN_MASK; + } + + return status_success; +} + +hpm_stat_t smix_mixer_config_dst_fadein_delta(SMIX_Type *ptr, uint8_t ch, uint32_t target_sample_rate, uint32_t ms) +{ + uint32_t delta = SMIX_DST_CH_FADEIN_DELTA_MASK * 1000 / target_sample_rate / ms; + + if (delta == 0) { + return status_invalid_argument; + } + ptr->DST_CH[ch].FADEIN = SMIX_DST_CH_FADEIN_DELTA_SET(delta); + return status_success; +} + +hpm_stat_t smix_mixer_config_dst_fadeout_delta(SMIX_Type *ptr, uint8_t ch, uint32_t target_sample_rate, uint32_t ms) +{ + uint32_t delta = (uint32_t)log2(target_sample_rate * ms / 1000); + + /* fadeout delta valid bit: 14 */ + if (delta > 0x3fff) { + return status_invalid_argument; + } + ptr->DST_CH[ch].FADEOUT = SMIX_DST_CH_FADEOUT_DELTA_SET(delta); + return status_success; +} + +hpm_stat_t smix_mixer_config_source_fadein_delta(SMIX_Type *ptr, uint8_t ch, uint32_t target_sample_rate, uint32_t ms) +{ + uint32_t delta = SMIX_DST_CH_FADEIN_DELTA_MASK * 1000 / target_sample_rate / ms; + + if (delta == 0) { + return status_invalid_argument; + } + ptr->SOURCE_CH[ch].FADEIN = SMIX_SOURCE_CH_FADEIN_DELTA_SET(delta); + return status_success; +} + +hpm_stat_t smix_mixer_config_source_fadeout_delta(SMIX_Type *ptr, uint8_t ch, uint32_t target_sample_rate, uint32_t ms) +{ + uint32_t delta = (uint32_t)log2(target_sample_rate * ms / 1000); + + /* fadeout delta valid bit: 14 */ + if (delta > 0x3fff) { + return status_invalid_argument; + } + ptr->SOURCE_CH[ch].FADEOUT = SMIX_SOURCE_CH_FADEOUT_DELTA_SET(delta); + return status_success; +} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_spi_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_spi_drv.c index 6a5624f5bb2..fb16e371e0e 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_spi_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_spi_drv.c @@ -255,6 +255,7 @@ hpm_stat_t spi_write_read_data(SPI_Type *ptr, uint8_t data_len_in_bytes, uint8_t static hpm_stat_t spi_no_data(SPI_Type *ptr, spi_mode_selection_t mode, spi_control_config_t *config) { + (void) ptr; if (mode == spi_master_mode) { if (config->master_config.cmd_enable == false && config->master_config.addr_enable == false) { return status_invalid_argument; @@ -304,6 +305,9 @@ void spi_master_get_default_control_config(spi_control_config_t *config) config->common_config.trans_mode = spi_trans_write_only; config->common_config.data_phase_fmt = spi_single_io_mode; config->common_config.dummy_cnt = spi_dummy_count_2; +#if defined(HPM_IP_FEATURE_SPI_CS_SELECT) && (HPM_IP_FEATURE_SPI_CS_SELECT == 1) + config->common_config.cs_index = spi_cs_0; +#endif } void spi_slave_get_default_control_config(spi_control_config_t *config) @@ -314,18 +318,27 @@ void spi_slave_get_default_control_config(spi_control_config_t *config) config->common_config.trans_mode = spi_trans_read_only; config->common_config.data_phase_fmt = spi_single_io_mode; config->common_config.dummy_cnt = spi_dummy_count_2; +#if defined(HPM_IP_FEATURE_SPI_CS_SELECT) && (HPM_IP_FEATURE_SPI_CS_SELECT == 1) + config->common_config.cs_index = spi_cs_0; +#endif } hpm_stat_t spi_master_timing_init(SPI_Type *ptr, spi_timing_config_t *config) { uint8_t sclk_div; - + uint8_t div_remainder; + uint8_t div_integer; if (config->master_config.sclk_freq_in_hz == 0) { return status_invalid_argument; } if (config->master_config.clk_src_freq_in_hz > config->master_config.sclk_freq_in_hz) { - sclk_div = (config->master_config.clk_src_freq_in_hz / config->master_config.sclk_freq_in_hz) / 2 - 1; + div_remainder = (config->master_config.clk_src_freq_in_hz % config->master_config.sclk_freq_in_hz); + div_integer = (config->master_config.clk_src_freq_in_hz / config->master_config.sclk_freq_in_hz); + if ((div_remainder != 0) || ((div_integer % 2) != 0)) { + return status_invalid_argument; + } + sclk_div = (div_integer / 2) - 1; } else { sclk_div = 0xff; } @@ -351,10 +364,11 @@ void spi_format_init(SPI_Type *ptr, spi_format_config_t *config) hpm_stat_t spi_control_init(SPI_Type *ptr, spi_control_config_t *config, uint32_t wcount, uint32_t rcount) { - if (wcount > SPI_SOC_TRANSFER_COUNT_MAX || rcount > SPI_SOC_TRANSFER_COUNT_MAX) { +#if defined (SPI_SOC_TRANSFER_COUNT_MAX) && (SPI_SOC_TRANSFER_COUNT_MAX == 512) + if ((wcount > SPI_SOC_TRANSFER_COUNT_MAX) || (rcount > SPI_SOC_TRANSFER_COUNT_MAX)) { return status_invalid_argument; } - +#endif /* slave data only mode only works on write read together transfer mode */ if (config->slave_config.slave_data_only == true && config->common_config.trans_mode != spi_trans_write_read_together) { return status_invalid_argument; @@ -372,6 +386,15 @@ hpm_stat_t spi_control_init(SPI_Type *ptr, spi_control_config_t *config, uint32_ SPI_TRANSCTRL_DUMMYCNT_SET(config->common_config.dummy_cnt) | SPI_TRANSCTRL_RDTRANCNT_SET(rcount - 1); +#if defined(HPM_IP_FEATURE_SPI_CS_SELECT) && (HPM_IP_FEATURE_SPI_CS_SELECT == 1) + ptr->CTRL = (ptr->CTRL & ~SPI_CTRL_CS_EN_MASK) | SPI_CTRL_CS_EN_SET(config->common_config.cs_index); +#endif + +#if defined(HPM_IP_FEATURE_SPI_NEW_TRANS_COUNT) && (HPM_IP_FEATURE_SPI_NEW_TRANS_COUNT == 1) + ptr->WR_TRANS_CNT = wcount - 1; + ptr->RD_TRANS_CNT = rcount - 1; +#endif + /* reset txfifo, rxfifo and control */ ptr->CTRL |= SPI_CTRL_TXFIFORST_MASK | SPI_CTRL_RXFIFORST_MASK | SPI_CTRL_SPIRST_MASK; @@ -481,3 +504,120 @@ hpm_stat_t spi_setup_dma_transfer(SPI_Type *ptr, return stat; } + +#if defined(HPM_IP_FEATURE_SPI_SUPPORT_DIRECTIO) && (HPM_IP_FEATURE_SPI_SUPPORT_DIRECTIO == 1) +hpm_stat_t spi_directio_enable_output(SPI_Type *ptr, spi_directio_pin_t pin) +{ + hpm_stat_t stat = status_success; + switch (pin) { + case hold_pin: + ptr->DIRECTIO |= SPI_DIRECTIO_HOLD_OE_MASK; + break; + case wp_pin: + ptr->DIRECTIO |= SPI_DIRECTIO_WP_OE_MASK; + break; + case miso_pin: + ptr->DIRECTIO |= SPI_DIRECTIO_MISO_OE_MASK; + break; + case mosi_pin: + ptr->DIRECTIO |= SPI_DIRECTIO_MOSI_OE_MASK; + break; + case sclk_pin: + ptr->DIRECTIO |= SPI_DIRECTIO_SCLK_OE_MASK; + break; + case cs_pin: + ptr->DIRECTIO |= SPI_DIRECTIO_CS_OE_MASK; + break; + default: + stat = status_invalid_argument; + break; + } + return stat; +} + +hpm_stat_t spi_directio_disable_output(SPI_Type *ptr, spi_directio_pin_t pin) +{ + hpm_stat_t stat = status_success; + switch (pin) { + case hold_pin: + ptr->DIRECTIO &= ~SPI_DIRECTIO_HOLD_OE_MASK; + break; + case wp_pin: + ptr->DIRECTIO &= ~SPI_DIRECTIO_WP_OE_MASK; + break; + case miso_pin: + ptr->DIRECTIO &= ~SPI_DIRECTIO_MISO_OE_MASK; + break; + case mosi_pin: + ptr->DIRECTIO &= ~SPI_DIRECTIO_MOSI_OE_MASK; + break; + case sclk_pin: + ptr->DIRECTIO &= ~SPI_DIRECTIO_SCLK_OE_MASK; + break; + case cs_pin: + ptr->DIRECTIO &= ~SPI_DIRECTIO_CS_OE_MASK; + break; + default: + stat = status_invalid_argument; + break; + } + return stat; +} + +hpm_stat_t spi_directio_write(SPI_Type *ptr, spi_directio_pin_t pin, bool high) +{ + hpm_stat_t stat = status_success; + switch (pin) { + case hold_pin: + (high == true) ? (ptr->DIRECTIO |= SPI_DIRECTIO_HOLD_O_MASK) : (ptr->DIRECTIO &= ~SPI_DIRECTIO_HOLD_O_MASK); + break; + case wp_pin: + (high == true) ? (ptr->DIRECTIO |= SPI_DIRECTIO_WP_O_MASK) : (ptr->DIRECTIO &= ~SPI_DIRECTIO_WP_O_MASK); + break; + case miso_pin: + (high == true) ? (ptr->DIRECTIO |= SPI_DIRECTIO_MISO_O_MASK) : (ptr->DIRECTIO &= ~SPI_DIRECTIO_MISO_O_MASK); + break; + case mosi_pin: + (high == true) ? (ptr->DIRECTIO |= SPI_DIRECTIO_MOSI_O_MASK) : (ptr->DIRECTIO &= ~SPI_DIRECTIO_MOSI_O_MASK); + break; + case sclk_pin: + (high == true) ? (ptr->DIRECTIO |= SPI_DIRECTIO_SCLK_O_MASK) : (ptr->DIRECTIO &= ~SPI_DIRECTIO_SCLK_O_MASK); + break; + case cs_pin: + (high == true) ? (ptr->DIRECTIO |= SPI_DIRECTIO_CS_O_MASK) : (ptr->DIRECTIO &= ~SPI_DIRECTIO_CS_O_MASK); + break; + default: + stat = status_invalid_argument; + break; + } + return stat; +} + +uint8_t spi_directio_read(SPI_Type *ptr, spi_directio_pin_t pin) +{ + uint8_t io_sta = 0; + switch (pin) { + case hold_pin: + io_sta = SPI_DIRECTIO_HOLD_I_GET(ptr->DIRECTIO); + break; + case wp_pin: + io_sta = SPI_DIRECTIO_WP_I_GET(ptr->DIRECTIO); + break; + case miso_pin: + io_sta = SPI_DIRECTIO_MISO_I_GET(ptr->DIRECTIO); + break; + case mosi_pin: + io_sta = SPI_DIRECTIO_MOSI_I_GET(ptr->DIRECTIO); + break; + case sclk_pin: + io_sta = SPI_DIRECTIO_SCLK_I_GET(ptr->DIRECTIO); + break; + case cs_pin: + io_sta = SPI_DIRECTIO_CS_I_GET(ptr->DIRECTIO); + break; + default: + break; + } + return io_sta; +} +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tamp_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tamp_drv.c new file mode 100644 index 00000000000..ffb838dda68 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tamp_drv.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_tamp_drv.h" + +void tamp_init_ch_config(TAMP_Type *ptr, uint8_t ch, tamper_ch_config_t *config) +{ + ch >>= 1u; + ptr->TAMP[ch].CONTROL = TAMP_TAMP_CONTROL_BYPASS_SET(config->filter_bypass) + | TAMP_TAMP_CONTROL_FILTER_SET(config->filter_len) + | TAMP_TAMP_CONTROL_VALUE_SET(config->expect_high_level) + | TAMP_TAMP_CONTROL_SPEED_SET(config->speed) + | TAMP_TAMP_CONTROL_RECOVER_SET(config->auto_recover) + | TAMP_TAMP_CONTROL_ACTIVE_SET(config->active_mode) + | TAMP_TAMP_CONTROL_ENABLE_SET(config->enable); + ptr->TAMP[ch].POLY = config->poly; + ptr->TAMP[ch].LFSR = config->lfsr; +} + +void tamp_get_default_ch_config(TAMP_Type *ptr, tamper_ch_config_t *config) +{ + (void) ptr; + config->enable = false; + config->active_mode = false; + config->expect_high_level = false; + config->filter_bypass = false; + config->filter_len = filter_len_128_cycles; + config->speed = spd_1_time_per_sec; + config->auto_recover = false; + config->poly = 0; + config->lfsr = 0; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_uart_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_uart_drv.c index 557b7ddb488..3202fefbb02 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_uart_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_uart_drv.c @@ -20,8 +20,13 @@ #define HPM_UART_BAUDRATE_DIV_MAX (0xFFFFU) #define HPM_UART_BAUDRATE_DIV_MIN (1U) +#ifndef UART_SOC_OVERSAMPLE_MAX +#define UART_SOC_OVERSAMPLE_MAX HPM_UART_OSC_MAX +#endif + void uart_default_config(UART_Type *ptr, uart_config_t *config) { + (void) ptr; config->baudrate = 115200; config->word_length = word_length_8_bits; config->parity = parity_none; @@ -33,13 +38,20 @@ void uart_default_config(UART_Type *ptr, uart_config_t *config) config->modem_config.auto_flow_ctrl_en = false; config->modem_config.loop_back_en = false; config->modem_config.set_rts_high = false; -#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) +#if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1) config->rxidle_config.detect_enable = false; config->rxidle_config.detect_irq_enable = false; config->rxidle_config.idle_cond = uart_rxline_idle_cond_rxline_logic_one; config->rxidle_config.threshold = 10; /* 10-bit for typical UART configuration (8-N-1) */ #endif -#if defined(UART_SOC_HAS_RXEN_CFG) && (UART_SOC_HAS_RXEN_CFG == 1) + /* if have 9bit_mode function, it's has be tx_idle function */ +#if defined(HPM_IP_FEATURE_UART_9BIT_MODE) && (HPM_IP_FEATURE_UART_9BIT_MODE == 1) + config->txidle_config.detect_enable = false; + config->txidle_config.detect_irq_enable = false; + config->txidle_config.idle_cond = uart_rxline_idle_cond_rxline_logic_one; + config->txidle_config.threshold = 10; /* 10-bit for typical UART configuration (8-N-1) */ +#endif +#if defined(HPM_IP_FEATURE_UART_RX_EN) && (HPM_IP_FEATURE_UART_RX_EN == 1) config->rx_enable = true; #endif } @@ -57,18 +69,8 @@ static bool uart_calculate_baudrate(uint32_t freq, uint32_t baudrate, uint16_t * tmp = (float) freq / baudrate; - for (uint8_t i = 0; i < HPM_UART_OSC_MAX; i += 2) { - /* osc range: 0 - 32, even number */ - if (i == 0) { - /* osc == 0 in bitfield, oversample rate is 32 */ - osc = HPM_UART_OSC_MAX; - } else if (i <= 8) { - /* osc <= 8 in bitfield, oversample rate is 8 */ - osc = HPM_UART_OSC_MIN; - } else { - /* osc > 8 && osc < 32 in bitfield, oversample rate is osc */ - osc = i; - } + for (osc = HPM_UART_OSC_MIN; osc <= UART_SOC_OVERSAMPLE_MAX; osc += 2) { + /* osc range: HPM_UART_OSC_MIN - UART_SOC_OVERSAMPLE_MAX, even number */ delta = 0; div = (uint16_t)(tmp / osc); if (div < HPM_UART_BAUDRATE_DIV_MIN) { @@ -76,15 +78,15 @@ static bool uart_calculate_baudrate(uint32_t freq, uint32_t baudrate, uint16_t * continue; } if (div * osc > tmp) { - delta = div * osc - tmp; + delta = (uint16_t)(div * osc - tmp); } else if (div * osc < tmp) { - delta = tmp - div * osc; + delta = (uint16_t)(tmp - div * osc); } if (delta && ((delta * 100 / tmp) > HPM_UART_BAUDRATE_TOLERANCE)) { continue; } else { *div_out = div; - *osc_out = (i <= 8 && i) ? osc : i; + *osc_out = (osc == HPM_UART_OSC_MAX) ? 0 : osc; /* osc == 0 in bitfield, oversample rate is 32 */ return true; } } @@ -105,6 +107,7 @@ hpm_stat_t uart_init(UART_Type *ptr, uart_config_t *config) if (!uart_calculate_baudrate(config->src_freq_in_hz, config->baudrate, &div, &osc)) { return status_uart_no_suitable_baudrate_parameter_found; } + ptr->OSCR = (ptr->OSCR & ~UART_OSCR_OSC_MASK) | UART_OSCR_OSC_SET(osc); ptr->DLL = UART_DLL_DLL_SET(div >> 0); @@ -156,40 +159,35 @@ hpm_stat_t uart_init(UART_Type *ptr, uart_config_t *config) ptr->LCR = tmp | UART_LCR_WLS_SET(config->word_length); -#if defined(UART_SOC_HAS_NEW_FIFO_THR) && (UART_SOC_HAS_NEW_FIFO_THR == 1) +#if defined(HPM_IP_FEATURE_UART_FINE_FIFO_THRLD) && (HPM_IP_FEATURE_UART_FINE_FIFO_THRLD == 1) + /* reset TX and RX fifo */ ptr->FCRR = UART_FCRR_TFIFORST_MASK | UART_FCRR_RFIFORST_MASK; - if (config->fifo_enable) { - /* Enable FIFO, reset TX and RX. */ - if (config->using_new_fifo_thr) { - ptr->FCRR = UART_FCRR_FIFOT4EN_MASK - | UART_FCRR_FIFOE_MASK - | UART_FCRR_TFIFOT4_SET(config->tx_fifo_level) - | UART_FCRR_RFIFOT4_SET(config->rx_fifo_level) - | UART_FCRR_DMAE_SET(config->dma_enable); - } else { - ptr->FCR = UART_FCRR_FIFOE_MASK - | UART_FCRR_TFIFOT_SET(config->tx_fifo_level) - | UART_FCRR_RFIFOT_SET(config->rx_fifo_level) - | UART_FCRR_DMAE_SET(config->dma_enable); - } - } + /* Enable FIFO */ + ptr->FCRR = UART_FCRR_FIFOT4EN_MASK + | UART_FCRR_FIFOE_SET(config->fifo_enable) + | UART_FCRR_TFIFOT4_SET(config->tx_fifo_level) + | UART_FCRR_RFIFOT4_SET(config->rx_fifo_level) + | UART_FCRR_DMAE_SET(config->dma_enable); + #else + /* reset TX and RX fifo */ ptr->FCR = UART_FCR_TFIFORST_MASK | UART_FCR_RFIFORST_MASK; - if (config->fifo_enable) { - /* Enable FIFO, reset TX and RX. */ - ptr->FCR = UART_FCR_FIFOE_MASK - | UART_FCR_TFIFOT_SET(config->tx_fifo_level) - | UART_FCR_RFIFOT_SET(config->rx_fifo_level) - | UART_FCR_DMAE_SET(config->dma_enable); - } + /* Enable FIFO */ + tmp = UART_FCR_FIFOE_SET(config->fifo_enable) + | UART_FCR_TFIFOT_SET(config->tx_fifo_level) + | UART_FCR_RFIFOT_SET(config->rx_fifo_level) + | UART_FCR_DMAE_SET(config->dma_enable); + ptr->FCR = tmp; + /* store FCR register value */ + ptr->GPR = tmp; #endif uart_modem_config(ptr, &config->modem_config); -#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) +#if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1) uart_init_rxline_idle_detection(ptr, config->rxidle_config); #endif -#if defined(UART_SOC_HAS_RXEN_CFG) && (UART_SOC_HAS_RXEN_CFG == 1) +#if defined(HPM_IP_FEATURE_UART_RX_EN) && (HPM_IP_FEATURE_UART_RX_EN == 1) if (config->rx_enable) { ptr->IDLE_CFG |= UART_IDLE_CFG_RXEN_MASK; } @@ -304,12 +302,15 @@ hpm_stat_t uart_send_data(UART_Type *ptr, uint8_t *source, uint32_t size_in_byte } -#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) +#if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1) hpm_stat_t uart_init_rxline_idle_detection(UART_Type *ptr, uart_rxline_idle_config_t rxidle_config) { - ptr->IDLE_CFG = UART_IDLE_CFG_RX_IDLE_EN_SET(rxidle_config.detect_enable) - | UART_IDLE_CFG_RX_IDLE_THR_SET(rxidle_config.threshold) - | UART_IDLE_CFG_RX_IDLE_COND_SET(rxidle_config.idle_cond); + ptr->IDLE_CFG &= ~(UART_IDLE_CFG_RX_IDLE_EN_MASK + | UART_IDLE_CFG_RX_IDLE_THR_MASK + | UART_IDLE_CFG_RX_IDLE_COND_MASK); + ptr->IDLE_CFG |= UART_IDLE_CFG_RX_IDLE_EN_SET(rxidle_config.detect_enable) + | UART_IDLE_CFG_RX_IDLE_THR_SET(rxidle_config.threshold) + | UART_IDLE_CFG_RX_IDLE_COND_SET(rxidle_config.idle_cond); if (rxidle_config.detect_irq_enable) { uart_enable_irq(ptr, uart_intr_rx_line_idle); @@ -321,11 +322,30 @@ hpm_stat_t uart_init_rxline_idle_detection(UART_Type *ptr, uart_rxline_idle_conf } #endif -#if defined(UART_SOC_HAS_NEW_FIFO_THR) && (UART_SOC_HAS_NEW_FIFO_THR == 1) -void uart_config_trig_mode(UART_Type *ptr, uart_trig_config_t *config) +/* if have 9bit_mode function, it's has be tx_idle function */ +#if defined(HPM_IP_FEATURE_UART_9BIT_MODE) && (HPM_IP_FEATURE_UART_9BIT_MODE == 1) +hpm_stat_t uart_init_txline_idle_detection(UART_Type *ptr, uart_rxline_idle_config_t txidle_config) { - ptr->MOTO_CFG &= ~UART_MOTO_CFG_TXSTP_BITS_MASK; + ptr->IDLE_CFG &= ~(UART_IDLE_CFG_TX_IDLE_EN_MASK + | UART_IDLE_CFG_TX_IDLE_THR_MASK + | UART_IDLE_CFG_TX_IDLE_COND_MASK); + ptr->IDLE_CFG |= UART_IDLE_CFG_TX_IDLE_EN_SET(txidle_config.detect_enable) + | UART_IDLE_CFG_TX_IDLE_THR_SET(txidle_config.threshold) + | UART_IDLE_CFG_TX_IDLE_COND_SET(txidle_config.idle_cond); + + if (txidle_config.detect_irq_enable) { + uart_enable_irq(ptr, uart_intr_tx_line_idle); + } else { + uart_disable_irq(ptr, uart_intr_tx_line_idle); + } + + return status_success; +} +#endif +#if defined(HPM_IP_FEATURE_UART_TRIG_MODE) && (HPM_IP_FEATURE_UART_TRIG_MODE == 1) +void uart_config_transfer_trig_mode(UART_Type *ptr, uart_trig_config_t *config) +{ ptr->MOTO_CFG = UART_MOTO_CFG_TXSTP_BITS_SET(config->stop_bit_len) | UART_MOTO_CFG_HWTRG_EN_SET(config->hardware_trig) | UART_MOTO_CFG_TRG_MODE_SET(config->trig_mode) @@ -334,13 +354,28 @@ void uart_config_trig_mode(UART_Type *ptr, uart_trig_config_t *config) } #endif -/* FCR is WO register, preprae all bit field to write */ +/* fifo control register(FCR) is WO access, if support FCCR register, it is RW access. */ void uart_config_fifo_ctrl(UART_Type *ptr, uart_fifo_ctrl_t *ctrl) { +#if defined(HPM_IP_FEATURE_UART_FINE_FIFO_THRLD) && (HPM_IP_FEATURE_UART_FINE_FIFO_THRLD == 1) + ptr->FCRR = UART_FCRR_FIFOT4EN_MASK + | UART_FCRR_TFIFOT4_SET(ctrl->tx_fifo_level) + | UART_FCRR_RFIFOT4_SET(ctrl->rx_fifo_level) + | UART_FCRR_DMAE_SET(ctrl->dma_enable) + | UART_FCRR_TFIFORST_SET(ctrl->reset_tx_fifo) + | UART_FCRR_RFIFORST_SET(ctrl->reset_rx_fifo) + | UART_FCRR_FIFOE_SET(ctrl->fifo_enable); +#else ptr->FCR = UART_FCR_TFIFOT_SET(ctrl->tx_fifo_level) | UART_FCR_RFIFOT_SET(ctrl->rx_fifo_level) | UART_FCR_TFIFORST_SET(ctrl->reset_tx_fifo) | UART_FCR_RFIFORST_SET(ctrl->reset_rx_fifo) | UART_FCR_DMAE_SET(ctrl->dma_enable) | UART_FCR_FIFOE_SET(ctrl->fifo_enable); + /* store FCR to GPR */ + ptr->GPR = UART_FCR_TFIFOT_SET(ctrl->tx_fifo_level) + | UART_FCR_RFIFOT_SET(ctrl->rx_fifo_level) + | UART_FCR_DMAE_SET(ctrl->dma_enable) + | UART_FCR_FIFOE_SET(ctrl->fifo_enable); +#endif } \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_usb_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_usb_drv.c index f8dbb290b4c..146c034956b 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_usb_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_usb_drv.c @@ -44,11 +44,6 @@ static void usb_phy_deinit(USB_Type *ptr) ptr->PHY_CTRL1 &= ~USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK; /* clear otg_suspendm */ } -static uint8_t usb_phy_get_line_state(USB_Type *ptr) -{ - return USB_PHY_STATUS_LINE_STATE_GET(ptr->PHY_STATUS); -} - /*--------------------------------------------------------------------- * Driver API *--------------------------------------------------------------------- @@ -58,6 +53,7 @@ void usb_phy_init(USB_Type *ptr) { uint32_t status; + usb_phy_enable_dp_dm_pulldown(ptr); ptr->OTG_CTRL0 |= USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK; /* set otg_utmi_reset_sw for naneng usbphy */ ptr->OTG_CTRL0 &= ~USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK; /* clr otg_utmi_suspend_m for naneng usbphy */ ptr->PHY_CTRL1 &= ~USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK; /* clr cfg_rst_n */ @@ -68,8 +64,8 @@ void usb_phy_init(USB_Type *ptr) ptr->OTG_CTRL0 |= USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK; /* set otg_utmi_suspend_m for naneng usbphy */ - for (int i = 0; i < USB_PHY_INIT_DELAY_COUNT; i++) { - ptr->PHY_CTRL0 = USB_PHY_CTRL0_GPIO_ID_SEL_N_SET(0); /* used for delay */ + for (volatile uint32_t i = 0; i < USB_PHY_INIT_DELAY_COUNT; i++) { + (void)ptr->PHY_CTRL1; /* used for delay */ } ptr->OTG_CTRL0 &= ~USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK; /* clear otg_utmi_reset_sw for naneng usbphy */ @@ -87,6 +83,7 @@ void usb_phy_init(USB_Type *ptr) void usb_dcd_bus_reset(USB_Type *ptr, uint16_t ep0_max_packet_size) { + (void) ep0_max_packet_size; /* The reset value for all endpoint types is the control endpoint. If one endpoint * direction is enabled and the paired endpoint of opposite direction is disabled, then the * endpoint type of the unused direction must be changed from the control type to any other @@ -94,7 +91,7 @@ void usb_dcd_bus_reset(USB_Type *ptr, uint16_t ep0_max_packet_size) * for the data PID tracking on the active endpoint. */ - for (int i = 1; i < USB_SOC_DCD_MAX_ENDPOINT_COUNT; i++) { + for (uint32_t i = 1; i < USB_SOC_DCD_MAX_ENDPOINT_COUNT; i++) { ptr->ENDPTCTRL[i] = USB_ENDPTCTRL_TXT_SET(usb_xfer_bulk) | USB_ENDPTCTRL_RXT_SET(usb_xfer_bulk); } @@ -253,6 +250,14 @@ void usb_dcd_edpt_clear_stall(USB_Type *ptr, uint8_t ep_addr) ptr->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_STALL << (dir ? 16 : 0)); } +bool usb_dcd_edpt_check_stall(USB_Type *ptr, uint8_t ep_addr) +{ + uint8_t const epnum = ep_addr & 0x0f; + uint8_t const dir = (ep_addr & 0x80) >> 7; + + return (ptr->ENDPTCTRL[epnum] & (ENDPTCTRL_STALL << (dir ? 16 : 0))) ? true : false; +} + void usb_dcd_edpt_close(USB_Type *ptr, uint8_t ep_addr) { uint8_t const epnum = ep_addr & 0x0f; diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_vad_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_vad_drv.c index ce2f643a27b..0f342da2372 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_vad_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_vad_drv.c @@ -9,6 +9,7 @@ void vad_get_default_config(VAD_Type *ptr, vad_config_t *config) { + (void) ptr; config->enable_buffer = true; config->enable_pdm_clock_out = true; config->enable_two_channels = true; diff --git a/bsp/hpmicro/libraries/hpm_sdk/hpm_sdk_version.h.in b/bsp/hpmicro/libraries/hpm_sdk/hpm_sdk_version.h.in deleted file mode 100644 index c195586cbea..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/hpm_sdk_version.h.in +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_SDK_VERSION_H -#define HPM_SDK_VERSION_H - -#cmakedefine SDK_VERSION_CODE @SDK_VERSION_CODE@ -#define SDK_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c)) - -#define SDKVERSION @SDKVERSION@ -#define SDK_VERSION_NUMBER @SDK_VERSION_NUMBER@ -#define SDK_VERSION_MAJOR @SDK_VERSION_MAJOR@ -#define SDK_VERSION_MINOR @SDK_VERSION_MINOR@ -#define SDK_PATCHLEVEL @SDK_PATCHLEVEL@ -#define SDK_VERSION_STRING @SDK_VERSION_STRING@ - -#define BUILD_VERSION @BUILD_VERSION@ - - -#endif /* HPM_SDK_VERSION_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/HPM5301_svd.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/HPM5301_svd.xml new file mode 100644 index 00000000000..31fdee2a554 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/HPM5301_svd.xml @@ -0,0 +1,13435 @@ + + + HPMICRO + HPM5301 + HPM5300 + 1.0 + HPM5300 device + + /* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + + + other + r0p0 + little + false + true + true + 7 + false + + + + 8 + 32 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + + + FGPIO + FGPIO + GPIO + 0xc0000 + + 0x0 + 0x8f0 + registers + + + + 15 + 0x10 + gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy + DI[%s] + no description available + 0x0 + + VALUE + GPIO input value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-only + + + + + + 15 + 0x10 + gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy + DO[%s] + no description available + 0x100 + + VALUE + GPIO output value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + SET + GPIO output set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + CLEAR + GPIO output clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + TOGGLE + GPIO output toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + + 15 + 0x10 + gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy + OE[%s] + no description available + 0x200 + + VALUE + GPIO direction value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + SET + GPIO direction set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + CLEAR + GPIO direction clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + TOGGLE + GPIO direction toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + + 15 + 0x10 + gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy + IF[%s] + no description available + 0x300 + + VALUE + GPIO interrupt flag value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + write-only + + + + + + 15 + 0x10 + gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy + IE[%s] + no description available + 0x400 + + VALUE + GPIO interrupt enable value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + SET + GPIO interrupt enable set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + CLEAR + GPIO interrupt enable clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + TOGGLE + GPIO interrupt enable toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + + 15 + 0x10 + gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy + PL[%s] + no description available + 0x500 + + VALUE + GPIO interrupt polarity value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + SET + GPIO interrupt polarity set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + CLEAR + GPIO interrupt polarity clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + TOGGLE + GPIO interrupt polarity toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + + 15 + 0x10 + gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy + TP[%s] + no description available + 0x600 + + VALUE + GPIO interrupt type value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + SET + GPIO interrupt type set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + CLEAR + GPIO interrupt type clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TOGGLE + GPIO interrupt type toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + + 15 + 0x10 + gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy + AS[%s] + no description available + 0x700 + + VALUE + GPIO interrupt asynchronous value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + SET + GPIO interrupt asynchronous set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + CLEAR + GPIO interrupt asynchronous clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + TOGGLE + GPIO interrupt asynchronous toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + + 15 + 0x10 + gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy + PD[%s] + no description available + 0x800 + + VALUE + GPIO dual edge interrupt enable value + 0x0 + 32 + 0x00000000 + 0x00000001 + + + IRQ_DUAL + GPIO dual edge interrupt enable +0: single edge interrupt +1: dual edge interrupt enable + 0 + 1 + read-write + + + + + SET + GPIO dual edge interrupt enable set + 0x4 + 32 + 0x00000000 + 0x00000001 + + + IRQ_DUAL + GPIO dual edge interrupt enable set +0: keep original edge interrupt type +1: dual edge interrupt enable + 0 + 1 + read-write + + + + + CLEAR + GPIO dual edge interrupt enable clear + 0x8 + 32 + 0x00000000 + 0x00000001 + + + IRQ_DUAL + GPIO dual edge interrupt enable clear +0: keep original edge interrupt type +1: single edge interrupt enable + 0 + 1 + read-write + + + + + TOGGLE + GPIO dual edge interrupt enable toggle + 0xc + 32 + 0x00000000 + 0x00000001 + + + IRQ_DUAL + GPIO dual edge interrupt enable toggle +0: keep original edge interrupt type +1: change original edge interrupt type to another one. + 0 + 1 + read-write + + + + + + + + GPIO0 + GPIO0 + GPIO + 0xf00d0000 + + + PGPIO + PGPIO + GPIO + 0xf411c000 + + + PLIC + PLIC + PLIC + 0xe4000000 + + 0x0 + 0x201000 + registers + + + + feature + Feature enable register + 0x0 + 32 + 0x00000000 + 0x00000003 + + + VECTORED + Vector mode enable +0: Disabled +1: Enabled + 1 + 1 + read-write + + + PREEMPT + Preemptive priority interrupt enable +0: Disabled +1: Enabled + 0 + 1 + read-write + + + + + 127 + 0x4 + PRIORITY1,PRIORITY2,PRIORITY3,PRIORITY4,PRIORITY5,PRIORITY6,PRIORITY7,PRIORITY8,PRIORITY9,PRIORITY10,PRIORITY11,PRIORITY12,PRIORITY13,PRIORITY14,PRIORITY15,PRIORITY16,PRIORITY17,PRIORITY18,PRIORITY19,PRIORITY20,PRIORITY21,PRIORITY22,PRIORITY23,PRIORITY24,PRIORITY25,PRIORITY26,PRIORITY27,PRIORITY28,PRIORITY29,PRIORITY30,PRIORITY31,PRIORITY32,PRIORITY33,PRIORITY34,PRIORITY35,PRIORITY36,PRIORITY37,PRIORITY38,PRIORITY39,PRIORITY40,PRIORITY41,PRIORITY42,PRIORITY43,PRIORITY44,PRIORITY45,PRIORITY46,PRIORITY47,PRIORITY48,PRIORITY49,PRIORITY50,PRIORITY51,PRIORITY52,PRIORITY53,PRIORITY54,PRIORITY55,PRIORITY56,PRIORITY57,PRIORITY58,PRIORITY59,PRIORITY60,PRIORITY61,PRIORITY62,PRIORITY63,PRIORITY64,PRIORITY65,PRIORITY66,PRIORITY67,PRIORITY68,PRIORITY69,PRIORITY70,PRIORITY71,PRIORITY72,PRIORITY73,PRIORITY74,PRIORITY75,PRIORITY76,PRIORITY77,PRIORITY78,PRIORITY79,PRIORITY80,PRIORITY81,PRIORITY82,PRIORITY83,PRIORITY84,PRIORITY85,PRIORITY86,PRIORITY87,PRIORITY88,PRIORITY89,PRIORITY90,PRIORITY91,PRIORITY92,PRIORITY93,PRIORITY94,PRIORITY95,PRIORITY96,PRIORITY97,PRIORITY98,PRIORITY99,PRIORITY100,PRIORITY101,PRIORITY102,PRIORITY103,PRIORITY104,PRIORITY105,PRIORITY106,PRIORITY107,PRIORITY108,PRIORITY109,PRIORITY110,PRIORITY111,PRIORITY112,PRIORITY113,PRIORITY114,PRIORITY115,PRIORITY116,PRIORITY117,PRIORITY118,PRIORITY119,PRIORITY120,PRIORITY121,PRIORITY122,PRIORITY123,PRIORITY124,PRIORITY125,PRIORITY126,PRIORITY127 + PRIORITY[%s] + no description available + 0x4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + 4 + 0x4 + PENDING0,PENDING1,PENDING2,PENDING3 + PENDING[%s] + no description available + 0x1000 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + 4 + 0x4 + TRIGGER0,TRIGGER1,TRIGGER2,TRIGGER3 + TRIGGER[%s] + no description available + 0x1080 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. +0: Level-triggered interrupt +1: Edge-triggered interrupt + 0 + 32 + read-only + + + + + NUMBER + Number of supported interrupt sources and targets + 0x1100 + 32 + 0xFFFFFFFF + + + NUM_TARGET + The number of supported targets + 16 + 16 + read-only + + + NUM_INTERRUPT + The number of supported interrupt sources + 0 + 16 + read-only + + + + + INFO + Version and the maximum priority + 0x1104 + 32 + 0xFFFFFFFF + + + MAX_PRIORITY + The maximum priority supported + 16 + 16 + read-only + + + VERSION + The version of the PLIC design + 0 + 16 + read-only + + + + + 1 + 0x80 + target0 + TARGETINT[%s] + no description available + 0x2000 + + 4 + 0x4 + INTEN0,INTEN1,INTEN2,INTEN3 + INTEN[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + + 1 + 0x1000 + target0 + TARGETCONFIG[%s] + no description available + 0x200000 + + THRESHOLD + Target0 priority threshold + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + THRESHOLD + Interrupt priority threshold. + 0 + 32 + read-write + + + + + CLAIM + Target claim and complete + 0x4 + 32 + 0x00000000 + 0x000003FF + + + INTERRUPT_ID + On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). + 0 + 10 + read-write + + + + + PPS + Preempted priority stack + 0x400 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY_PREEMPTED + Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. + 0 + 32 + read-write + + + + + + + + MCHTMR + MCHTMR + MCHTMR + 0xe6000000 + + 0x0 + 0x10 + registers + + + + MTIME + Machine Time + 0x0 + 64 + 0x0000000000020210 + 0xFFFFFFFFFFFFFFFF + + + MTIME + Machine time + 0 + 64 + read-write + + + + + MTIMECMP + Machine Time Compare + 0x8 + 64 + 0x0000000000020210 + 0xFFFFFFFFFFFFFFFF + + + MTIMECMP + Machine time compare + 0 + 64 + read-write + + + + + + + PLICSW + PLICSW + PLIC_SW + 0xe6400000 + + 0x1000 + 0x1ff008 + registers + + + + PENDING + Pending status + 0x1000 + 32 + 0x00000000 + 0x00000002 + + + INTERRUPT + writing 1 to trigger software interrupt + 1 + 1 + read-write + + + + + INTEN + Interrupt enable + 0x2000 + 32 + 0x00000000 + 0x00000001 + + + INTERRUPT + enable software interrupt + 0 + 1 + read-write + + + + + CLAIM + Claim and complete. + 0x200004 + 32 + 0x00000000 + 0x00000001 + + + INTERRUPT_ID + On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). + 0 + 1 + read-write + + + + + + + GPTMR0 + GPTMR0 + TMR + 0xf0000000 + + 0x0 + 0x20c + registers + + + + 4 + 0x40 + ch0,ch1,ch2,ch3 + CHANNEL[%s] + no description available + 0x0 + + CR + Control Register + 0x0 + 32 + 0x00000000 + 0x80007FFF + + + CNTUPT + 1- update counter to new value as CNTUPTVAL +This bit will be auto cleared after 1 cycle + 31 + 1 + write-only + + + CNTRST + 1- reset counter + 14 + 1 + read-write + + + SYNCFLW + 1- enable this channel to reset counter to reload(RLD) together with its previous channel. +This bit is not valid for channel 0. + 13 + 1 + read-write + + + SYNCIFEN + 1- SYNCI is valid on its falling edge + 12 + 1 + read-write + + + SYNCIREN + 1- SYNCI is valid on its rising edge + 11 + 1 + read-write + + + CEN + 1- counter enable + 10 + 1 + read-write + + + CMPINIT + Output compare initial poliarity +1- The channel output initial level is high +0- The channel output initial level is low +User should set this bit before set CMPEN to 1. + 9 + 1 + read-write + + + CMPEN + 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. + 8 + 1 + read-write + + + DMASEL + select one of DMA request: +00- CMP0 flag +01- CMP1 flag +10- Input signal toggle captured +11- RLD flag, counter reload; + 6 + 2 + read-write + + + DMAEN + 1- enable dma + 5 + 1 + read-write + + + SWSYNCIEN + 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set + 4 + 1 + read-write + + + DBGPAUSE + 1- counter will pause if chip is in debug mode + 3 + 1 + read-write + + + CAPMODE + This bitfield define the input capture mode +100: width measure mode, timer will calculate the input signal period and duty cycle +011: capture at both rising edge and falling edge +010: capture at falling edge +001: capture at rising edge +000: No capture + 0 + 3 + read-write + + + + + 2 + 0x4 + CMP0,CMP1 + CMP[%s] + no description available + 0x4 + 32 + 0xFFFFFFF0 + 0xFFFFFFFF + + + CMP + compare value 0 + 0 + 32 + read-write + + + + + RLD + Reload register + 0xc + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + RLD + reload value + 0 + 32 + read-write + + + + + CNTUPTVAL + Counter update value register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTUPTVAL + counter will be set to this value when software write cntupt bit in CR + 0 + 32 + read-write + + + + + CAPPOS + Capture rising edge register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPOS + This register contains the counter value captured at input signal rising edge + 0 + 32 + read-only + + + + + CAPNEG + Capture falling edge register + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + This register contains the counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPPRD + PWM period measure register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPRD + This register contains the input signal period when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CAPDTY + PWM duty cycle measure register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + MEAS_HIGH + This register contains the input signal duty cycle when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CNT + Counter + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + 32 bit counter value + 0 + 32 + read-only + + + + + + SR + Status register + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH3CMP1F + channel 3 compare value 1 match flag + 15 + 1 + write-only + + + CH3CMP0F + channel 3 compare value 1 match flag + 14 + 1 + write-only + + + CH3CAPF + channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 13 + 1 + write-only + + + CH3RLDF + channel 3 counter reload flag + 12 + 1 + write-only + + + CH2CMP1F + channel 2 compare value 1 match flag + 11 + 1 + write-only + + + CH2CMP0F + channel 2 compare value 1 match flag + 10 + 1 + write-only + + + CH2CAPF + channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 9 + 1 + write-only + + + CH2RLDF + channel 2 counter reload flag + 8 + 1 + write-only + + + CH1CMP1F + channel 1 compare value 1 match flag + 7 + 1 + write-only + + + CH1CMP0F + channel 1 compare value 1 match flag + 6 + 1 + write-only + + + CH1CAPF + channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 5 + 1 + write-only + + + CH1RLDF + channel 1 counter reload flag + 4 + 1 + write-only + + + CH0CMP1F + channel 1 compare value 1 match flag + 3 + 1 + write-only + + + CH0CMP0F + channel 1 compare value 1 match flag + 2 + 1 + write-only + + + CH0CAPF + channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 1 + 1 + write-only + + + CH0RLDF + channel 1 counter reload flag + 0 + 1 + write-only + + + + + IRQEN + Interrupt request enable register + 0x204 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH3CMP1EN + 1- generate interrupt request when ch3cmp1f flag is set + 15 + 1 + read-write + + + CH3CMP0EN + 1- generate interrupt request when ch3cmp0f flag is set + 14 + 1 + read-write + + + CH3CAPEN + 1- generate interrupt request when ch3capf flag is set + 13 + 1 + read-write + + + CH3RLDEN + 1- generate interrupt request when ch3rldf flag is set + 12 + 1 + read-write + + + CH2CMP1EN + 1- generate interrupt request when ch2cmp1f flag is set + 11 + 1 + read-write + + + CH2CMP0EN + 1- generate interrupt request when ch2cmp0f flag is set + 10 + 1 + read-write + + + CH2CAPEN + 1- generate interrupt request when ch2capf flag is set + 9 + 1 + read-write + + + CH2RLDEN + 1- generate interrupt request when ch2rldf flag is set + 8 + 1 + read-write + + + CH1CMP1EN + 1- generate interrupt request when ch1cmp1f flag is set + 7 + 1 + read-write + + + CH1CMP0EN + 1- generate interrupt request when ch1cmp0f flag is set + 6 + 1 + read-write + + + CH1CAPEN + 1- generate interrupt request when ch1capf flag is set + 5 + 1 + read-write + + + CH1RLDEN + 1- generate interrupt request when ch1rldf flag is set + 4 + 1 + read-write + + + CH0CMP1EN + 1- generate interrupt request when ch0cmp1f flag is set + 3 + 1 + read-write + + + CH0CMP0EN + 1- generate interrupt request when ch0cmp0f flag is set + 2 + 1 + read-write + + + CH0CAPEN + 1- generate interrupt request when ch0capf flag is set + 1 + 1 + read-write + + + CH0RLDEN + 1- generate interrupt request when ch0rldf flag is set + 0 + 1 + read-write + + + + + GCR + Global control register + 0x208 + 32 + 0x00000000 + 0x0000000F + + + SWSYNCT + set this bitfield to trigger software counter sync event + 0 + 4 + read-write + + + + + + + GPTMR1 + GPTMR1 + TMR + 0xf0004000 + + + PTMR + PTMR + TMR + 0xf4120000 + + + UART0 + UART0 + UART + 0xf0040000 + + 0x4 + 0x3c + registers + + + + IDLE_CFG + Idle Configuration Register + 0x4 + 32 + 0x00000000 + 0x03FF0BFF + + + TX_IDLE_COND + IDLE Detection Condition +0 - Treat as idle if TX pin is logic one +1 - Treat as idle if UART state machine state is idle + 25 + 1 + read-write + + + TX_IDLE_EN + UART TX Idle Detect Enable +0 - Disable +1 - Enable + 24 + 1 + read-write + + + TX_IDLE_THR + Threshold for UART transmit Idle detection (in terms of bits) + 16 + 8 + read-write + + + RXEN + UART receive enable. +0 - hold RX input to high, avoide wrong data input when config pinmux +1 - bypass RX input from PIN +software should set it after config pinmux + 11 + 1 + read-write + + + RX_IDLE_COND + IDLE Detection Condition +0 - Treat as idle if RX pin is logic one +1 - Treat as idle if UART state machine state is idle + 9 + 1 + read-write + + + RX_IDLE_EN + UART Idle Detect Enable +0 - Disable +1 - Enable +it should be enabled if enable address match feature + 8 + 1 + read-write + + + RX_IDLE_THR + Threshold for UART Receive Idle detection (in terms of bits) + 0 + 8 + read-write + + + + + ADDR_CFG + address match config register + 0x8 + 32 + 0x00000000 + 0x001FFFFF + + + TXEN_9BIT + set to use 9bit mode for transmitter, +will set the MSB for the first character as address flag, keep 0 for others. + 20 + 1 + read-write + + + RXEN_ADDR_MSB + set to use MSB as address flag at receiver(actually this is done by software set correct MSB in addr0/addr1). +Clr to use first character as address. +Only needed if enable address match feature + 19 + 1 + read-write + + + RXEN_9BIT + set to use 9bit mode for receiver, only valid if rxen_addr_msb is set + 18 + 1 + read-write + + + A1_EN + enable addr1 compare for the first character. +If a1_en OR a0_en, then do not receive data if address not match. +If ~a1_en AND ~a0_en, the receive all data like before. +NOTE: should set idle_tmout_en if enable address match feature + 17 + 1 + read-write + + + A0_EN + enable addr0 compare for the first character + 16 + 1 + read-write + + + ADDR1 + address 1 fileld. +in 9bit mode, this is the full address byte. +For other mode(8/7/6/5bit), MSB should be set for address flag. +If want address==0 to be matched at 8bit mode, should set addr1=0x80 + 8 + 8 + read-write + + + ADDR0 + address 0 field. + 0 + 8 + read-write + + + + + IIR2 + Interrupt Identification Register2 + 0xc + 32 + 0x00000001 + 0xF80000CF + + + RXIDLE_FLAG + UART RX IDLE Flag, assert after rxd high and then rx idle timeout, write one clear +0 - UART RX is busy +1 - UART RX is idle + 31 + 1 + write-only + + + TXIDLE_FLAG + UART TX IDLE Flag, assert after txd high and then tx idle timeout, write one clear +0 - UART TX is busy +1 - UART TX is idle + 30 + 1 + write-only + + + ADDR_MATCH + address match irq status, assert if either address match(and enabled). Write one clear +NOTE: the address byte may not moved by DMA at this point. +User can wait next addr_match_idle irq for the whole data include address + 29 + 1 + write-only + + + ADDR_MATCH_IDLE + address match and idle irq status, assert at rx bus idle if address match event triggered. +Write one clear; + 28 + 1 + write-only + + + DATA_LOST + assert if data lost before address match status, write one clear; +It will not assert if no address match occurs + 27 + 1 + write-only + + + FIFOED + FIFOs enabled +These two bits are 1 when bit 0 of the FIFO Control +Register (FIFOE) is set to 1. + 6 + 2 + read-only + + + INTRID + Interrupt ID, see IIR2 for detail decoding + 0 + 4 + read-only + + + + + Cfg + Configuration Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + FIFOSIZE + The depth of RXFIFO and TXFIFO +0: 16-byte FIFO +1: 32-byte FIFO +2: 64-byte FIFO +3: 128-byte FIFO + 0 + 2 + read-only + + + + + OSCR + Over Sample Control Register + 0x14 + 32 + 0x00000010 + 0x0000001F + + + OSC + Over-sample control +The value must be an even number; any odd value +writes to this field will be converted to an even value. +OSC=0: reserved +OSC<=8: The over-sample ratio is 8 +8 < OSC< 32: The over sample ratio is OSC + 0 + 5 + read-write + + + + + FCRR + FIFO Control Register config + 0x18 + 32 + 0x00000000 + 0x008F0FFF + + + FIFOT4EN + set to use new 4bit fifo threshold(TFIFOT4 and RFIFOT4) +clr to use 2bit(TFIFOT and RFIFOT) + 23 + 1 + read-write + + + TFIFOT4 + txfifo threshold(0 for 1byte, 0xF for 16bytes), uart will send tx_dma_req when data in fifo is less than threshold. + 16 + 4 + read-write + + + RFIFOT4 + rxfifo threshold(0 for 1byte, 0xF for 16bytes). +Uart will send rx_dma_req if data in fifo reachs the threshold, also will set the rxdata irq if enabled + 8 + 4 + read-write + + + RFIFOT + Receiver FIFO trigger level + 6 + 2 + read-write + + + TFIFOT + Transmitter FIFO trigger level + 4 + 2 + read-write + + + DMAE + DMA enable +0: Disable +1: Enable + 3 + 1 + read-write + + + TFIFORST + Transmitter FIFO reset +Write 1 to clear all bytes in the TXFIFO and resets its +counter. The Transmitter Shift Register is not cleared. +This bit will automatically be cleared. + 2 + 1 + write-only + + + RFIFORST + Receiver FIFO reset +Write 1 to clear all bytes in the RXFIFO and resets its +counter. The Receiver Shift Register is not cleared. +This bit will automatically be cleared. + 1 + 1 + write-only + + + FIFOE + FIFO enable +Write 1 to enable both the transmitter and receiver +FIFOs. +The FIFOs are reset when the value of this bit toggles. + 0 + 1 + read-write + + + + + MOTO_CFG + moto system control register + 0x1c + 32 + 0x00000000 + 0x8000FFF0 + + + SWTRG + software trigger. User should avoid use sw/hw trigger at same time, otherwise result unknown. +Hardware auto reset. + 31 + 1 + write-only + + + TXSTP_BITS + if TXSTOP_INSERT is enabled, the STOP bits to be inserted between each byte. 0 for 1 bit; 0xFF for 256bits + 8 + 8 + read-write + + + HWTRG_EN + set to enable hardware trigger(trigger from moto is shared by other UART) + 7 + 1 + read-write + + + TRG_MODE + set to enable trigger mode. +software should push needed data into txbuffer frist, uart will not start transmission at this time. +User should send trigger signal(by hw or sw), uart will send all data in txfifo till empty +NOTE: the hw_trigger should be pulse signal from trig mux. + 6 + 1 + read-write + + + TRG_CLR_RFIFO + set to enable the feature that, clear rxfifo at tx trigger(sw or hw), avoid unexpected data in rxfifo. + 5 + 1 + read-write + + + TXSTOP_INSERT + set to insert STOP bits between each tx byte till tx fifo empty. +NOTE: there will be no 1.5/2 STOP bits if enabled this feature, LCR.STB should be set to 0 if this bit is set + 4 + 1 + read-write + + + + + RBR + Receiver Buffer Register (when DLAB = 0) + UNION_20 + 0x20 + 32 + 0x00000000 + 0x000000FF + + + RBR + Receive data read port + 0 + 8 + read-only + + + + + THR + Transmitter Holding Register (when DLAB = 0) + UNION_20 + 0x20 + 32 + 0x00000000 + 0x000000FF + + + THR + Transmit data write port + 0 + 8 + write-only + + + + + DLL + Divisor Latch LSB (when DLAB = 1) + UNION_20 + 0x20 + 32 + 0x00000001 + 0x000000FF + + + DLL + Least significant byte of the Divisor Latch + 0 + 8 + read-write + + + + + IER + Interrupt Enable Register (when DLAB = 0) + UNION_24 + 0x24 + 32 + 0x00000000 + 0xF800000F + + + ERXIDLE + Enable Receive Idle interrupt +0 - Disable Idle interrupt +1 - Enable Idle interrupt + 31 + 1 + read-write + + + ETXIDLE + enable transmit idle interrupt + 30 + 1 + read-write + + + EADDRM + enable ADDR_MATCH interrupt + 29 + 1 + read-write + + + EADDRM_IDLE + enable ADDR_MATCH_IDLE interrupt + 28 + 1 + read-write + + + EDATLOST + enable DATA_LOST interrupt + 27 + 1 + read-write + + + EMSI + Enable modem status interrupt +The interrupt asserts when the status of one of the +following occurs: +The status of modem_rin, modem_dcdn, +modem_dsrn or modem_ctsn (If the auto-cts mode is +disabled) has been changed. +If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), +modem_ctsn would be used to control the transmitter. + 3 + 1 + read-write + + + ELSI + Enable receiver line status interrupt + 2 + 1 + read-write + + + ETHEI + Enable transmitter holding register interrupt + 1 + 1 + read-write + + + ERBI + Enable received data available interrupt and the +character timeout interrupt +0: Disable +1: Enable + 0 + 1 + read-write + + + + + DLM + Divisor Latch MSB (when DLAB = 1) + UNION_24 + 0x24 + 32 + 0x00000000 + 0x000000FF + + + DLM + Most significant byte of the Divisor Latch + 0 + 8 + read-write + + + + + IIR + Interrupt Identification Register + UNION_28 + 0x28 + 32 + 0x00000001 + 0x800000CF + + + RXIDLE_FLAG + UART IDLE Flag +0 - UART is busy +1 - UART is idle +NOTE: when write one to clear this bit, avoid changging FCR register since it's same address as IIR + 31 + 1 + write-only + + + FIFOED + FIFOs enabled +These two bits are 1 when bit 0 of the FIFO Control +Register (FIFOE) is set to 1. + 6 + 2 + read-only + + + INTRID + Interrupt ID, see IIR2 for detail decoding + 0 + 4 + read-only + + + + + FCR + FIFO Control Register + UNION_28 + 0x28 + 32 + 0x00000000 + 0x000000FF + + + RFIFOT + Receiver FIFO trigger level + 6 + 2 + write-only + + + TFIFOT + Transmitter FIFO trigger level + 4 + 2 + write-only + + + DMAE + DMA enable +0: Disable +1: Enable + 3 + 1 + write-only + + + TFIFORST + Transmitter FIFO reset +Write 1 to clear all bytes in the TXFIFO and resets its +counter. The Transmitter Shift Register is not cleared. +This bit will automatically be cleared. + 2 + 1 + write-only + + + RFIFORST + Receiver FIFO reset +Write 1 to clear all bytes in the RXFIFO and resets its +counter. The Receiver Shift Register is not cleared. +This bit will automatically be cleared. + 1 + 1 + write-only + + + FIFOE + FIFO enable +Write 1 to enable both the transmitter and receiver +FIFOs. +The FIFOs are reset when the value of this bit toggles. + 0 + 1 + write-only + + + + + LCR + Line Control Register + 0x2c + 32 + 0x00000000 + 0x000000FF + + + DLAB + Divisor latch access bit + 7 + 1 + read-write + + + BC + Break control + 6 + 1 + read-write + + + SPS + Stick parity +1: Parity bit is constant 0 or 1, depending on bit4 (EPS). +0: Disable the sticky bit parity. + 5 + 1 + read-write + + + EPS + Even parity select +1: Even parity (an even number of logic-1 is in the data +and parity bits) +0: Old parity. + 4 + 1 + read-write + + + PEN + Parity enable +When this bit is set, a parity bit is generated in +transmitted data before the first STOP bit and the parity +bit would be checked for the received data. + 3 + 1 + read-write + + + STB + Number of STOP bits +0: 1 bits +1: The number of STOP bit is based on the WLS setting +When WLS = 0, STOP bit is 1.5 bits +When WLS = 1, 2, 3, STOP bit is 2 bits + 2 + 1 + read-write + + + WLS + Word length setting +0: 5 bits +1: 6 bits +2: 7 bits +3: 8 bits + 0 + 2 + read-write + + + + + MCR + Modem Control Register ( + 0x30 + 32 + 0x00000000 + 0x00000032 + + + AFE + Auto flow control enable +0: Disable +1: The auto-CTS and auto-RTS setting is based on the +RTS bit setting: +When RTS = 0, auto-CTS only +When RTS = 1, auto-CTS and auto-RTS + 5 + 1 + read-write + + + LOOP + Enable loopback mode +0: Disable +1: Enable + 4 + 1 + read-write + + + RTS + Request to send +This bit controls the modem_rtsn output. +0: The modem_rtsn output signal will be driven HIGH +1: The modem_rtsn output signal will be driven LOW + 1 + 1 + read-write + + + + + LSR + Line Status Register + 0x34 + 32 + 0x00000000 + 0xC01F1FFF + + + RXIDLE + rxidle after timeout, clear after rx idle condition not match + 31 + 1 + read-only + + + TXIDLE + txidle after timeout, clear after tx idle condition not match + 30 + 1 + read-only + + + RFIFO_NUM + data bytes in rxfifo not read + 16 + 5 + read-only + + + TFIFO_NUM + data bytes in txfifo not sent + 8 + 5 + read-only + + + ERRF + Error in RXFIFO +In the FIFO mode, this bit is set when there is at least +one parity error, framing error, or line break +associated with data in the RXFIFO. It is cleared when +this register is read and there is no more error for the +rest of data in the RXFIFO. + 7 + 1 + read-only + + + TEMT + Transmitter empty +This bit is 1 when the THR (TXFIFO in the FIFO +mode) and the Transmitter Shift Register (TSR) are +both empty. Otherwise, it is zero. + 6 + 1 + read-only + + + THRE + Transmitter Holding Register empty +This bit is 1 when the THR (TXFIFO in the FIFO +mode) is empty. Otherwise, it is zero. +If the THRE interrupt is enabled, an interrupt is +triggered when THRE becomes 1. + 5 + 1 + read-only + + + LBREAK + Line break +This bit is set when the uart_sin input signal was held +LOWfor longer than the time for a full-word +transmission. A full-word transmission is the +transmission of the START, data, parity, and STOP +bits. It is cleared when this register is read. +In the FIFO mode, this bit indicates the line break for +the received data at the top of the RXFIFO. + 4 + 1 + read-only + + + FE + Framing error +This bit is set when the received STOP bit is not +HIGH. It is cleared when this register is read. +In the FIFO mode, this bit indicates the framing error +for the received data at the top of the RXFIFO. + 3 + 1 + read-only + + + PE + Parity error +This bit is set when the received parity does not match +with the parity selected in the LCR[5:4]. It is cleared +when this register is read. +In the FIFO mode, this bit indicates the parity error +for the received data at the top of the RXFIFO. + 2 + 1 + read-only + + + OE + Overrun error +This bit indicates that data in the Receiver Buffer +Register (RBR) is overrun. + 1 + 1 + read-only + + + DR + Data ready. +This bit is set when there are incoming received data +in the Receiver Buffer Register (RBR). It is cleared +when all of the received data are read. + 0 + 1 + read-only + + + + + MSR + Modem Status Register + 0x38 + 32 + 0x00000000 + 0x00000011 + + + CTS + Clear to send +0: The modem_ctsn input signal is HIGH. +1: The modem_ctsn input signal is LOW. + 4 + 1 + read-only + + + DCTS + Delta clear to send +This bit is set when the state of the modem_ctsn input +signal has been changed since the last time this +register is read. + 0 + 1 + read-only + + + + + GPR + GPR Register + 0x3c + 32 + 0x00000000 + 0x000000FF + + + DATA + A one-byte storage register + 0 + 8 + read-write + + + + + + + UART1 + UART1 + UART + 0xf0044000 + + + UART2 + UART2 + UART + 0xf0048000 + + + UART3 + UART3 + UART + 0xf004c000 + + + PUART + PUART + UART + 0xf4124000 + + + I2C0 + I2C0 + I2C + 0xf0060000 + + 0x4 + 0x30 + registers + + + + Cfg + Configuration Register + 0x10 + 32 + 0x00000001 + 0xFFFFFFFF + + + FIFOSIZE + FIFO Size: +0: 2 bytes +1: 4 bytes +2: 8 bytes +3: 16 bytes + 0 + 2 + read-only + + + + + IntEn + Interrupt Enable Register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMPL + Set to enable the Completion Interrupt. +Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. +Slave: interrupts when a transaction addressing the controller is completed. + 9 + 1 + read-write + + + BYTERECV + Set to enable the Byte Receive Interrupt. +Interrupts when a byte of data is received +Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually. + 8 + 1 + read-write + + + BYTETRANS + Set to enable the Byte Transmit Interrupt. +Interrupts when a byte of data is transmitted. + 7 + 1 + read-write + + + START + Set to enable the START Condition Interrupt. +Interrupts when a START condition/repeated START condition is detected. + 6 + 1 + read-write + + + STOP + Set to enable the STOP Condition Interrupt +Interrupts when a STOP condition is detected. + 5 + 1 + read-write + + + ARBLOSE + Set to enable the Arbitration Lose Interrupt. +Master: interrupts when the controller loses the bus arbitration +Slave: not available in this mode. + 4 + 1 + read-write + + + ADDRHIT + Set to enable the Address Hit Interrupt. +Master: interrupts when the addressed slave returned an ACK. +Slave: interrupts when the controller is addressed. + 3 + 1 + read-write + + + FIFOHALF + Set to enable the FIFO Half Interrupt. +Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. +Transmitter: Interrupts when the FIFO is half-empty, i.e. there is <= 1/2 entries in the FIFO. +This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered. + 2 + 1 + read-write + + + FIFOFULL + Set to enable the FIFO Full Interrupt. +Interrupts when the FIFO is full. + 1 + 1 + read-write + + + FIFOEMPTY + Set to enabled the FIFO Empty Interrupt +Interrupts when the FIFO is empty. + 0 + 1 + read-write + + + + + Status + Status Register + 0x18 + 32 + 0x00000001 + 0xFFFFFFFF + + + LINESDA + Indicates the current status of the SDA line on the bus +1: high +0: low + 14 + 1 + read-only + + + LINESCL + Indicates the current status of the SCL line on the bus +1: high +0: low + 13 + 1 + read-only + + + GENCALL + Indicates that the address of the current transaction is a general call address: +1: General call +0: Not general call + 12 + 1 + read-only + + + BUSBUSY + Indicates that the bus is busy +The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus +1: Busy +0: Not busy + 11 + 1 + read-only + + + ACK + Indicates the type of the last received/transmitted acknowledgement bit: +1: ACK +0: NACK + 10 + 1 + read-only + + + CMPL + Transaction Completion +Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration +Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked. + 9 + 1 + write-only + + + BYTERECV + Indicates that a byte of data has been received. + 8 + 1 + write-only + + + BYTETRANS + Indicates that a byte of data has been transmitted. + 7 + 1 + write-only + + + START + Indicates that a START Condition or a repeated START condition has been transmitted/received. + 6 + 1 + write-only + + + STOP + Indicates that a STOP Condition has been transmitted/received. + 5 + 1 + write-only + + + ARBLOSE + Indicates that the controller has lost the bus arbitration. + 4 + 1 + write-only + + + ADDRHIT + Master: indicates that a slave has responded to the transaction. +Slave: indicates that a transaction is targeting the controller (including the General Call). + 3 + 1 + write-only + + + FIFOHALF + Transmitter: Indicates that the FIFO is half-empty. + 2 + 1 + read-only + + + FIFOFULL + Indicates that the FIFO is full. + 1 + 1 + read-only + + + FIFOEMPTY + Indicates that the FIFO is empty. + 0 + 1 + read-only + + + + + Addr + Address Register + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + The slave address. +For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid + 0 + 10 + read-write + + + + + Data + Data Register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + Write this register to put one byte of data to the FIFO. +Read this register to get one byte of data from the FIFO. + 0 + 8 + read-write + + + + + Ctrl + Control Register + 0x24 + 32 + 0x00905E00 + 0xFFFFFFFF + + + DATACNT_HIGH + Data counts in bytes. +Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. +Slave: the meaning of DataCnt depends on the DMA mode: +If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. +If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. + 24 + 8 + read-write + + + RESET_LEN + reset clock cycles. the clock high/low time is defined by Setup.T_SCLHi, 50% duty cycle. + 20 + 4 + read-write + + + RESET_HOLD_SCKIN + set to hold input clock to high when reset is active + 14 + 1 + read-write + + + RESET_ON + set to send reset signals(just toggle clock bus defined by reset_len). +this register is clered when reset is end, can't be cleared by software + 13 + 1 + read-write + + + PHASE_START + Enable this bit to send a START condition at the beginning of transaction. +Master mode only. + 12 + 1 + read-write + + + PHASE_ADDR + Enable this bit to send the address after START condition. +Master mode only. + 11 + 1 + read-write + + + PHASE_DATA + Enable this bit to send the data after Address phase. +Master mode only. + 10 + 1 + read-write + + + PHASE_STOP + Enable this bit to send a STOP condition at the end of a transaction. +Master mode only. + 9 + 1 + read-write + + + DIR + Transaction direction +Master: Set this bit to determine the direction for the next transaction. +0: Transmitter +1: Receiver +Slave: The direction of the last received transaction. +0: Receiver +1: Transmitter + 8 + 1 + read-write + + + DATACNT + Data counts in bytes. +Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. +Slave: the meaning of DataCnt depends on the DMA mode: +If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. +If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. + 0 + 8 + read-write + + + + + Cmd + Command Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMD + Write this register with the following values to perform the corresponding actions: +0x0: no action +0x1: issue a data transaction (Master only) +0x2: respond with an ACK to the received byte +0x3: respond with a NACK to the received byte +0x4: clear the FIFO +0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) +When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. +Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled. + 0 + 3 + read-write + + + + + Setup + Setup Register + 0x2c + 32 + 0x05252100 + 0xFFFFFFFF + + + T_SUDAT + T_SUDAT defines the data setup time before releasing the SCL. +Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) +tpclk = PCLK period +TPM = The multiplier value in Timing Parameter Multiplier Register + 24 + 5 + read-write + + + T_SP + T_SP defines the pulse width of spikes that must be suppressed by the input filter. +Pulse width = T_SP * tpclk* (TPM+1) + 21 + 3 + read-write + + + T_HDDAT + T_HDDAT defines the data hold time after SCL goes LOW +Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) + 16 + 5 + read-write + + + T_SCLRADIO + The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. +SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) +1: ratio = 2 +0: ratio = 1 +This field is only valid when the controller is in the master mode. + 13 + 1 + read-write + + + T_SCLHI + The HIGH period of generated SCL clock is defined by T_SCLHi. +SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) +The T_SCLHi value must be greater than T_SP and T_HDDAT values. +This field is only valid when the controller is in the master mode. + 4 + 9 + read-write + + + DMAEN + Enable the direct memory access mode data transfer. +1: Enable +0: Disable + 3 + 1 + read-write + + + MASTER + Configure this device as a master or a slave. +1: Master mode +0: Slave mode + 2 + 1 + read-write + + + ADDRESSING + I2C addressing mode: +1: 10-bit addressing mode +0: 7-bit addressing mode + 1 + 1 + read-write + + + IICEN + Enable the I2C controller. +1: Enable +0: Disable + 0 + 1 + read-write + + + + + TPM + I2C Timing Paramater Multiplier + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + TPM + A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). + 0 + 5 + read-write + + + + + + + I2C1 + I2C1 + I2C + 0xf0064000 + + + I2C2 + I2C2 + I2C + 0xf0068000 + + + I2C3 + I2C3 + I2C + 0xf006c000 + + + SPI0 + SPI0 + SPI + 0xf0070000 + + 0x4 + 0x7c + registers + + + + wr_trans_cnt + Transfer count for write data + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + WRTRANCNT + Transfer count for write data +WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). +WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. +The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. +For TransMode 0, WrTranCnt must be equal to RdTranCnt. + 0 + 32 + read-write + + + + + rd_trans_cnt + Transfer count for read data + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RDTRANCNT + Transfer count for read data +RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). +RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. +The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. +For TransMode 0, WrTranCnt must equal RdTranCnt. + 0 + 32 + read-write + + + + + TransFmt + Transfer Format Register + 0x10 + 32 + 0x00020780 + 0xFFFF1F9F + + + ADDRLEN + Address length in bytes +0x0: 1 byte +0x1: 2 bytes +0x2: 3 bytes +0x3: 4 bytes + 16 + 2 + read-write + + + DATALEN + The length of each data unit in bits +The actual bit number of a data unit is (DataLen + 1) + 8 + 5 + read-write + + + DATAMERGE + Enable Data Merge mode, which does automatic data split on write and data coalescing on read. +This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. +When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed. + 7 + 1 + read-write + + + MOSIBIDIR + Bi-directional MOSI in regular (single) mode +0x0: MOSI is uni-directional signal in regular mode. +0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two + 4 + 1 + read-write + + + LSB + Transfer data with the least significant bit first +0x0: Most significant bit first +0x1: Least significant bit first + 3 + 1 + read-write + + + SLVMODE + SPI Master/Slave mode selection +0x0: Master mode +0x1: Slave mode + 2 + 1 + read-write + + + CPOL + SPI Clock Polarity +0x0: SCLK is LOW in the idle states +0x1: SCLK is HIGH in the idle states + 1 + 1 + read-write + + + CPHA + SPI Clock Phase +0x0: Sampling data at odd SCLK edges +0x1: Sampling data at even SCLK edges + 0 + 1 + read-write + + + + + DirectIO + Direct IO Control Register + 0x14 + 32 + 0x00003100 + 0x013F3F3F + + + DIRECTIOEN + Enable Direct IO +0x0: Disable +0x1: Enable + 24 + 1 + read-write + + + HOLD_OE + Output enable for the SPI Flash hold signal + 21 + 1 + read-write + + + WP_OE + Output enable for the SPI Flash write protect signal + 20 + 1 + read-write + + + MISO_OE + Output enable fo the SPI MISO signal + 19 + 1 + read-write + + + MOSI_OE + Output enable for the SPI MOSI signal + 18 + 1 + read-write + + + SCLK_OE + Output enable for the SPI SCLK signal + 17 + 1 + read-write + + + CS_OE + Output enable for SPI CS (chip select) signal + 16 + 1 + read-write + + + HOLD_O + Output value for the SPI Flash hold signal + 13 + 1 + read-write + + + WP_O + Output value for the SPI Flash write protect signal + 12 + 1 + read-write + + + MISO_O + Output value for the SPI MISO signal + 11 + 1 + read-write + + + MOSI_O + Output value for the SPI MOSI signal + 10 + 1 + read-write + + + SCLK_O + Output value for the SPI SCLK signal + 9 + 1 + read-write + + + CS_O + Output value for the SPI CS (chip select) signal + 8 + 1 + read-write + + + HOLD_I + Status of the SPI Flash hold signal + 5 + 1 + read-only + + + WP_I + Status of the SPI Flash write protect signal + 4 + 1 + read-only + + + MISO_I + Status of the SPI MISO signal + 3 + 1 + read-only + + + MOSI_I + Status of the SPI MOSI signal + 2 + 1 + read-only + + + SCLK_I + Status of the SPI SCLK signal + 1 + 1 + read-only + + + CS_I + Status of the SPI CS (chip select) signal + 0 + 1 + read-only + + + + + TransCtrl + Transfer Control Register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + SLVDATAONLY + Data-only mode (slave mode only) +0x0: Disable the data-only mode +0x1: Enable the data-only mode +Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0. + 31 + 1 + read-write + + + CMDEN + SPI command phase enable (Master mode only) +0x0: Disable the command phase +0x1: Enable the command phase + 30 + 1 + read-write + + + ADDREN + SPI address phase enable (Master mode only) +0x0: Disable the address phase +0x1: Enable the address phase + 29 + 1 + read-write + + + ADDRFMT + SPI address phase format (Master mode only) +0x0: Address phase is the regular (single) mode +0x1: The format of the address phase is the same as the data phase (DualQuad). + 28 + 1 + read-write + + + TRANSMODE + Transfer mode +The transfer sequence could be +0x0: Write and read at the same time +0x1: Write only +0x2: Read only +0x3: Write, Read +0x4: Read, Write +0x5: Write, Dummy, Read +0x6: Read, Dummy, Write +0x7: None Data (must enable CmdEn or AddrEn in master mode) +0x8: Dummy, Write +0x9: Dummy, Read +0xa~0xf: Reserved + 24 + 4 + read-write + + + DUALQUAD + SPI data phase format +0x0: Regular (Single) mode +0x1: Dual I/O mode +0x2: Quad I/O mode +0x3: Reserved + 22 + 2 + read-write + + + TOKENEN + Token transfer enable (Master mode only) +Append a one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. +0x0: Disable the one-byte special token +0x1: Enable the one-byte special token + 21 + 1 + read-write + + + WRTRANCNT + Transfer count for write data +WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). +WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. +The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. +For TransMode 0, WrTranCnt must be equal to RdTranCnt. + 12 + 9 + read-write + + + TOKENVALUE + Token value (Master mode only) +The value of the one-byte special token following the address phase for SPI read transfers. +0x0: token value = 0x00 +0x1: token value = 0x69 + 11 + 1 + read-write + + + DUMMYCNT + Dummy data count. The actual dummy count is (DummyCnt +1). +The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) +The Data pins are put into the high impedance during the dummy data phase. +DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases. + 9 + 2 + read-write + + + RDTRANCNT + Transfer count for read data +RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). +RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. +The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. +For TransMode 0, WrTranCnt must equal RdTranCnt. + 0 + 9 + read-write + + + + + Cmd + Command Register + 0x24 + 32 + 0x00000000 + 0x000000FF + + + CMD + SPI Command + 0 + 8 + read-write + + + + + Addr + Address Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + SPI Address +(Master mode only) + 0 + 32 + read-write + + + + + Data + Data Register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + Data to transmit or the received data +For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. +For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. +The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. +If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset. + 0 + 32 + read-write + + + + + Ctrl + Control Register + 0x30 + 32 + 0x00000000 + 0x0FFFFF1F + + + CS_EN + No description available + 24 + 4 + read-write + + + TXTHRES + Transmit (TX) FIFO Threshold +The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold. + 16 + 8 + read-write + + + RXTHRES + Receive (RX) FIFO Threshold +The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold. + 8 + 8 + read-write + + + TXDMAEN + TX DMA enable + 4 + 1 + read-write + + + RXDMAEN + RX DMA enable + 3 + 1 + read-write + + + TXFIFORST + Transmit FIFO reset +Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. + 2 + 1 + read-write + + + RXFIFORST + Receive FIFO reset +Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. + 1 + 1 + read-write + + + SPIRST + SPI reset +Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. + 0 + 1 + read-write + + + + + Status + Status Register + 0x34 + 32 + 0x00000000 + 0x33FFFF01 + + + TXNUM_7_6 + Number of valid entries in the Transmit FIFO + 28 + 2 + read-only + + + RXNUM_7_6 + Number of valid entries in the Receive FIFO + 24 + 2 + read-only + + + TXFULL + Transmit FIFO Full flag + 23 + 1 + read-only + + + TXEMPTY + Transmit FIFO Empty flag + 22 + 1 + read-only + + + TXNUM_5_0 + Number of valid entries in the Transmit FIFO + 16 + 6 + read-only + + + RXFULL + Receive FIFO Full flag + 15 + 1 + read-only + + + RXEMPTY + Receive FIFO Empty flag + 14 + 1 + read-only + + + RXNUM_5_0 + Number of valid entries in the Receive FIFO + 8 + 6 + read-only + + + SPIACTIVE + SPI register programming is in progress. +In master mode, SPIActive becomes 1 after the SPI command register is written and becomes 0 after the transfer is finished. +In slave mode, SPIActive becomes 1 after the SPI CS signal is asserted and becomes 0 after the SPI CS signal is deasserted. +Note that due to clock synchronization, it may take at most two spi_clock cycles for SPIActive to change when the corresponding condition happens. +Note this bit stays 0 when Direct IO Control or the memory-mapped interface is used. + 0 + 1 + read-only + + + + + IntrEn + Interrupt Enable Register + 0x38 + 32 + 0x00000000 + 0x0000003F + + + SLVCMDEN + Enable the Slave Command Interrupt. +Control whether interrupts are triggered whenever slave commands are received. +(Slave mode only) + 5 + 1 + read-write + + + ENDINTEN + Enable the End of SPI Transfer interrupt. +Control whether interrupts are triggered when SPI transfers end. +(In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.) + 4 + 1 + read-write + + + TXFIFOINTEN + Enable the SPI Transmit FIFO Threshold interrupt. +Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold. + 3 + 1 + read-write + + + RXFIFOINTEN + Enable the SPI Receive FIFO Threshold interrupt. +Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold. + 2 + 1 + read-write + + + TXFIFOURINTEN + Enable the SPI Transmit FIFO Underrun interrupt. +Control whether interrupts are triggered when the Transmit FIFO run out of data. +(Slave mode only) + 1 + 1 + read-write + + + RXFIFOORINTEN + Enable the SPI Receive FIFO Overrun interrupt. +Control whether interrupts are triggered when the Receive FIFO overflows. +(Slave mode only) + 0 + 1 + read-write + + + + + IntrSt + Interrupt Status Register + 0x3c + 32 + 0x00000000 + 0x0000003F + + + SLVCMDINT + Slave Command Interrupt. +This bit is set when Slave Command interrupts occur. +(Slave mode only) + 5 + 1 + write-only + + + ENDINT + End of SPI Transfer interrupt. +This bit is set when End of SPI Transfer interrupts occur. + 4 + 1 + write-only + + + TXFIFOINT + TX FIFO Threshold interrupt. +This bit is set when TX FIFO Threshold interrupts occur. + 3 + 1 + write-only + + + RXFIFOINT + RX FIFO Threshold interrupt. +This bit is set when RX FIFO Threshold interrupts occur. + 2 + 1 + write-only + + + TXFIFOURINT + TX FIFO Underrun interrupt. +This bit is set when TX FIFO Underrun interrupts occur. +(Slave mode only) + 1 + 1 + write-only + + + RXFIFOORINT + RX FIFO Overrun interrupt. +This bit is set when RX FIFO Overrun interrupts occur. +(Slave mode only) + 0 + 1 + write-only + + + + + Timing + Interface Timing Register + 0x40 + 32 + 0x00000000 + 0x00003FFF + + + CS2SCLK + The minimum time between the edges of SPI CS and the edges of SCLK. +SCLK_period * (CS2SCLK + 1) / 2 + 12 + 2 + read-write + + + CSHT + The minimum time that SPI CS should stay HIGH. +SCLK_period * (CSHT + 1) / 2 + 8 + 4 + read-write + + + SCLK_DIV + The clock frequency ratio between the clock source and SPI interface SCLK. +SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) +The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency. + 0 + 8 + read-write + + + + + SlvSt + Slave Status Register + 0x60 + 32 + 0x00000000 + 0x0007FFFF + + + UNDERRUN + Data underrun occurs in the last transaction + 18 + 1 + write-only + + + OVERRUN + Data overrun occurs in the last transaction + 17 + 1 + read-write + + + READY + Set this bit to indicate that the ATCSPI200 is ready for data transaction. +When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0. + 16 + 1 + read-write + + + USR_STATUS + User defined status flags + 0 + 16 + read-write + + + + + SlvDataCnt + Slave Data Count Register + 0x64 + 32 + 0x00000000 + 0x03FF03FF + + + WCNT + Slave transmitted data count + 16 + 10 + read-only + + + RCNT + Slave received data count + 0 + 10 + read-only + + + + + SlvDataWCnt + WCnt + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + No description available + 0 + 32 + read-only + + + + + SlvDataRCnt + RCnt + 0x6c + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + No description available + 0 + 32 + read-only + + + + + Config + Configuration Register + 0x7c + 32 + 0x00004311 + 0x000043FF + + + SLAVE + Support for SPI Slave mode + 14 + 1 + read-only + + + QUADSPI + Support for Quad I/O SPI + 9 + 1 + read-only + + + DUALSPI + Support for Dual I/O SPI + 8 + 1 + read-only + + + TXFIFOSIZE + Depth of TX FIFO +0x0: 2 words +0x1: 4 words +0x2: 8 words +0x3: 16 words +0x4: 32 words +0x5: 64 words +0x6: 128 words + 4 + 4 + read-only + + + RXFIFOSIZE + Depth of RX FIFO +0x0: 2 words +0x1: 4 words +0x2: 8 words +0x3: 16 words +0x4: 32 words +0x5: 64 words +0x6: 128 words + 0 + 4 + read-only + + + + + + + SPI1 + SPI1 + SPI + 0xf0074000 + + + SPI2 + SPI2 + SPI + 0xf0078000 + + + SPI3 + SPI3 + SPI + 0xf007c000 + + + CRC + CRC + CRC + 0xf0080000 + + 0x0 + 0x200 + registers + + + + 8 + 0x40 + 0,1,2,3,4,5,6,7 + CHN[%s] + no description available + 0x0 + + pre_set + &index0 pre set for crc setting + 0x0 + 32 + 0x00000000 + 0x000000FF + + + PRE_SET + 0: no pre set +1: CRC32 +2: CRC32-AUTOSAR +3: CRC16-CCITT +4: CRC16-XMODEM +5: CRC16-MODBUS +1: CRC32 +2: CRC32-autosar +3: CRC16-ccitt +4: CRC16-xmodem +5: CRC16-modbus +6: crc16_dnp +7: crc16_x25 +8: crc16_usb +9: crc16_maxim +10: crc16_ibm +11: crc8_maxim +12: crc8_rohc +13: crc8_itu +14: crc8 +15: crc5_usb + 0 + 8 + read-write + + + + + clr + chn&index0 clear crc result and setting + 0x4 + 32 + 0x00000000 + 0x00000001 + + + CLR + write 1 to clr crc setting and result for its channel. +always read 0. + 0 + 1 + read-write + + + + + poly + chn&index0 poly + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + POLY + poly setting + 0 + 32 + read-write + + + + + init_data + chn&index0 init_data + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + INIT_DATA + initial data of CRC + 0 + 32 + read-write + + + + + xorout + chn&index0 xorout + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + XOROUT + XOR for CRC result + 0 + 32 + read-write + + + + + misc_setting + chn&index0 misc_setting + 0x14 + 32 + 0x00000000 + 0x0101013F + + + BYTE_REV + 0: no wrap input byte order +1: wrap input byte order + 24 + 1 + read-write + + + REV_OUT + 0: no wrap output bit order +1: wrap output bit order + 16 + 1 + read-write + + + REV_IN + 0: no wrap input bit order +1: wrap input bit order + 8 + 1 + read-write + + + POLY_WIDTH + crc data length + 0 + 6 + read-write + + + + + data + chn&index0 data + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + data for crc + 0 + 32 + read-write + + + + + result + chn&index0 result + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + RESULT + crc result + 0 + 32 + read-write + + + + + + + + TSNS + TSNS + TSNS + 0xf0090000 + + 0x0 + 0x3c + registers + + + + T + Temperature + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Signed number of temperature in 256 x celsius degree + 0 + 32 + read-only + + + + + TMAX + Maximum Temperature + 0x4 + 32 + 0xFF800000 + 0xFFFFFFFF + + + T + maximum temperature ever found + 0 + 32 + read-only + + + + + TMIN + Minimum Temperature + 0x8 + 32 + 0x007FFFFF + 0xFFFFFFFF + + + T + minimum temperature ever found + 0 + 32 + read-only + + + + + AGE + Sample age + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + AGE + age of T register in 24MHz clock cycles + 0 + 32 + read-only + + + + + STATUS + Status + 0x10 + 32 + 0x00000000 + 0x80000001 + + + VALID + indicate value in T is valid or not +0: not valid +1:valid + 31 + 1 + read-only + + + TRIGGER + Software trigger for sensing in trigger mode, trigger will be ignored if in sensing or other mode + 0 + 1 + write-only + + + + + CONFIG + Configuration + 0x14 + 32 + 0x00600300 + 0xC3FF0713 + + + IRQ_EN + Enable interrupt + 31 + 1 + read-write + + + RST_EN + Enable reset + 30 + 1 + read-write + + + COMPARE_MIN_EN + Enable compare for minimum temperature + 25 + 1 + read-write + + + COMPARE_MAX_EN + Enable compare for maximum temperature + 24 + 1 + read-write + + + SPEED + cycles of a progressive step in 24M clock, valid from 24-255, default 96 +24: 24 cycle for a step +25: 25 cycle for a step +26: 26 cycle for a step +... +255: 255 cycle for a step + 16 + 8 + read-write + + + AVERAGE + Average time, default in 3 +0: measure and return +1: twice and average +2: 4 times and average +. . . +7: 128 times and average + 8 + 3 + read-write + + + CONTINUOUS + continuous mode that keep sampling temperature peridically +0: trigger mode +1: continuous mode + 4 + 1 + read-write + + + ASYNC + Acynchronous mode, this mode can work without clock, only available function ios compare to certain ADC value +0: active mode +1: Async mode + 1 + 1 + read-write + + + ENABLE + Enable temperature +0: disable, temperature sensor is shut down +1: enable. Temperature sensor enabled + 0 + 1 + read-write + + + + + VALIDITY + Sample validity + 0x18 + 32 + 0x016E3600 + 0xFFFFFFFF + + + VALIDITY + time for temperature values to expire in 24M clock cycles + 0 + 32 + read-write + + + + + FLAG + Temperature flag + 0x1c + 32 + 0x00000000 + 0x00330001 + + + RECORD_MIN_CLR + Clear minimum recorder of temerature, write 1 to clear + 21 + 1 + read-write + + + RECORD_MAX_CLR + Clear maximum recorder of temerature, write 1 to clear + 20 + 1 + read-write + + + UNDER_TEMP + Clear under temperature status, write 1 to clear + 17 + 1 + read-write + + + OVER_TEMP + Clear over temperature status, write 1 to clear + 16 + 1 + read-write + + + IRQ + IRQ flag, write 1 to clear + 0 + 1 + read-write + + + + + UPPER_LIM_IRQ + Maximum temperature to interrupt + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Maximum temperature for compare + 0 + 32 + read-write + + + + + LOWER_LIM_IRQ + Minimum temperature to interrupt + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Minimum temperature for compare + 0 + 32 + read-write + + + + + UPPER_LIM_RST + Maximum temperature to reset + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Maximum temperature for compare + 0 + 32 + read-write + + + + + LOWER_LIM_RST + Minimum temperature to reset + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Minimum temperature for compare + 0 + 32 + read-write + + + + + ASYNC + Configuration in asynchronous mode + 0x30 + 32 + 0x00000000 + 0x010107FF + + + ASYNC_TYPE + Compare hotter than or colder than in asynchoronous mode +0: hotter than +1: colder than + 24 + 1 + read-write + + + POLARITY + Polarity of internal comparator + 16 + 1 + read-write + + + VALUE + Value of async mode to compare + 0 + 11 + read-write + + + + + ADVAN + Advance configuration + 0x38 + 32 + 0x00000000 + 0x03010003 + + + ASYNC_IRQ + interrupt status of asynchronous mode + 25 + 1 + read-only + + + ACTIVE_IRQ + interrupt status of active mode + 24 + 1 + read-only + + + SAMPLING + temperature sampling is working + 16 + 1 + read-only + + + NEG_ONLY + use negative compare polarity only + 1 + 1 + read-write + + + POS_ONLY + use positive compare polarity only + 0 + 1 + read-write + + + + + + + MBX0A + MBX0A + MBX + 0xf00a0000 + + 0x0 + 0x24 + registers + + + + CR + Command Registers + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXRESET + Reset TX Fifo and word. + 31 + 1 + read-write + + + BARCTL + Bus Access Response Control, when bit 15:14= +00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. + 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. +10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. +11: reserved. + 14 + 2 + read-write + + + BEIE + Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. +1, enable the bus access error interrupt. +0, disable the bus access error interrupt. + 8 + 1 + read-write + + + TFMAIE + TX FIFO message available interrupt enable. +1, enable the TX FIFO massage available interrupt. +0, disable the TX FIFO message available interrupt. + 7 + 1 + read-write + + + TFMEIE + TX FIFO message empty interrupt enable. +1, enable the TX FIFO massage empty interrupt. +0, disable the TX FIFO message empty interrupt. + 6 + 1 + read-write + + + RFMAIE + RX FIFO message available interrupt enable. +1, enable the RX FIFO massage available interrupt. +0, disable the RX FIFO message available interrupt. + 5 + 1 + read-write + + + RFMFIE + RX fifo message full interrupt enable. +1, enable the RX fifo message full interrupt. +0, disable the RX fifo message full interrupt. + 4 + 1 + read-write + + + TWMEIE + TX word message empty interrupt enable. +1, enable the TX word massage empty interrupt. +0, disable the TX word message empty interrupt. + 1 + 1 + read-write + + + RWMVIE + RX word message valid interrupt enable. +1, enable the RX word massage valid interrupt. +0, disable the RX word message valid interrupt. + 0 + 1 + read-write + + + + + SR + Status Registers + 0x4 + 32 + 0x000000E2 + 0xFFFF3FFF + + + RFVC + RX FIFO valid message count + 20 + 4 + read-only + + + TFEC + TX FIFO empty message word count + 16 + 4 + read-only + + + ERRRE + bus Error for read when rx word message are still invalid, this bit is W1C bit. +1, read from word message when the word message are still invalid will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 13 + 1 + write-only + + + EWTRF + bus Error for write when tx word message are still valid, this bit is W1C bit. +1, write to word message when the word message are still valid will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 12 + 1 + write-only + + + ERRFE + bus Error for read when rx fifo empty, this bit is W1C bit. +1, read from a empty rx fifo will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 11 + 1 + write-only + + + EWTFF + bus Error for write when tx fifo full, this bit is W1C bit. +1, write to a fulled tx fifo will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 10 + 1 + write-only + + + EAIVA + bus Error for Accessing Invalid Address; this bit is W1C bit. +1, read and write to invalid address in the bus of this block, will set this bit. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 9 + 1 + write-only + + + EW2RO + bus Error for Write to Read Only address; this bit is W1C bit. +1, write to read only address happened in the bus of this block. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 8 + 1 + write-only + + + TFMA + TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. +1, TXFIFO message buffer has slot available +0, no slot available (fifo full) + 7 + 1 + read-write + + + TFME + TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. +1, no any message data in TXFIFO from other core. +0, there are some data in the 4x32 TX FIFO from other core yet. + 6 + 1 + read-write + + + RFMA + RX FIFO Message Available, available data in the 4x32 TX FIFO message buffer to the other core, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, no any data in the 4x32 TXFIFO message buffer. +0, there are some data in the the 4x32 TXFIFO message buffer already. + 5 + 1 + read-only + + + RFMF + RX FIFO Message Full, message from other core; will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, the other core had written 4x32 message in the RXFIFO. +0, no 4x32 RX FIFO message from other core yet. + 4 + 1 + read-only + + + TWME + TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, means this core had write word message to TXREG. +0, means no valid word message in the TXREG yet. + 1 + 1 + read-only + + + RWMV + RX word message valid, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, the other core had written word message in the RXREG. +0, no valid word message yet in the RXREG. + 0 + 1 + read-only + + + + + TXREG + Transmit word message to other core. + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXREG + Transmit word message to other core. + 0 + 32 + write-only + + + + + RXREG + Receive word message from other core. + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + RXREG + Receive word message from other core. + 0 + 32 + read-only + + + + + 1 + 0x4 + TXFIFO0 + TXWRD[%s] + no description available + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXFIFO + TXFIFO for sending message to other core, FIFO size, 4x32 +can write one of the word address to push data to the FIFO; +can also use 4x32 burst write from 0x010 to push 4 words to the FIFO. + 0 + 32 + write-only + + + + + 1 + 0x4 + RXFIFO0 + RXWRD[%s] + no description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXFIFO + RXFIFO for receiving message from other core, FIFO size, 4x32 +can read one of the word address to pop data to the FIFO; +can also use 4x32 burst read from 0x020 to read 4 words from the FIFO. + 0 + 32 + read-only + + + + + + + MBX0B + MBX0B + MBX + 0xf00a4000 + + + EWDG0 + EWDG0 + EWDG + 0xf00b0000 + + 0x0 + 0x28 + registers + + + + CTRL0 + wdog ctrl register 0 +Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits + 0x0 + 32 + 0x00000000 + 0x2FE2F03F + + + CLK_SEL + clock select +0：bus clock +1：ext clock + 29 + 1 + read-write + + + DIV_VALUE + clock divider, the clock divider works as 2 ^ div_value for wdt counter + 25 + 3 + read-write + + + WIN_EN + window mode enable + 24 + 1 + read-write + + + WIN_LOWER + Once window mode is opened, the lower counter value to refresh wdt +00: 4/8 overtime value +01: 5/8 of overtime value +10: 6/8 of overtime value +11: 7/8 of overtime value + 22 + 2 + read-write + + + CFG_LOCK + The register is locked and unlock is needed before re-config registers +Once the lock mechanism takes effect, the CTRL0, CTRL1, timeout int register, timeout rst register, needs unlock before re-config them. +The register update needs to be finished in the required period defined by UPD_OT_TIME register + 21 + 1 + read-write + + + OT_SELF_CLEAR + overtime reset can be self released after 32 function cycles + 17 + 1 + read-write + + + REF_OT_REQ + If refresh event has to be limited into a period after refresh unlocked. +Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter + 15 + 1 + read-write + + + WIN_UPPER + The upper threshold of window value +The window period upper limit is: lower_limit + (overtime_rst_value / 16) * upper_reg_value +If this register value is zero, then no upper level limitation + 12 + 3 + read-write + + + REF_LOCK + WDT refresh has to be unlocked firstly once refresh lock is enable. + 5 + 1 + read-write + + + REF_UNLOCK_MEC + Unlock refresh mechanism +00: the required unlock password is the same with refresh_psd_register +01: the required unlock password is a ring shift left value of refresh_psd_register +10: the required unlock password is always 16'h55AA, no matter what refresh_psd_register is +11: the required unlock password is a LSFR result of refresh_psd_register, the characteristic polynomial is X^15 + 1 + 3 + 2 + read-write + + + EN_DBG + WTD enable or not in debug mode + 2 + 1 + read-write + + + EN_LP + WDT enable or not in low power mode +2'b00: wdt is halted once in low power mode +2'b01: wdt will work with 1/4 normal clock freq in low power mode +2'b10: wdt will work with 1/2 normal clock freq in low power mode +2'b11: wdt will work with normal clock freq in low power mode + 0 + 2 + read-write + + + + + CTRL1 + wdog ctrl register 1 +Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits + 0x4 + 32 + 0x00000000 + 0x00F300FC + + + REF_FAIL_RST_EN + Refresh violation will trigger an reset. +These event will be taken as a refresh violation: +1) Not refresh in the window once window mode is enabled +2) Not unlock refresh firstly if unlock is required +3) Not refresh in the required time after unlock, once refresh unlock overtime is enabled. +4) Not write the required word to refresh wdt. + 23 + 1 + read-write + + + REF_FAIL_INT_EN + Refresh violation will trigger an interrupt + 22 + 1 + read-write + + + UNL_REF_FAIL_RST_EN + Refresh unlock fail will trigger a reset + 21 + 1 + read-write + + + UNL_REF_FAIL_INT_EN + Refresh unlock fail will trigger a interrupt + 20 + 1 + read-write + + + OT_RST_EN + WDT overtime will generate a reset + 17 + 1 + read-write + + + OT_INT_EN + WDT can generate an interrupt warning before timeout + 16 + 1 + read-write + + + CTL_VIO_RST_EN + Ctrl update violation will trigger a reset +The violation event is to try updating the locked register before unlock them + 7 + 1 + read-write + + + CTL_VIO_INT_EN + Ctrl update violation will trigger a interrupt + 6 + 1 + read-write + + + UNL_CTL_FAIL_RST_EN + Unlock register update failure will trigger a reset + 5 + 1 + read-write + + + UNL_CTL_FAIL_INT_EN + Unlock register update failure will trigger a interrupt + 4 + 1 + read-write + + + PARITY_FAIL_RST_EN + Parity error will trigger a reset +A parity check is required once writing to ctrl0 and ctrl1 register. The result should be zero by modular two addition of all bits + 3 + 1 + read-write + + + PARITY_FAIL_INT_EN + Parity error will trigger a interrupt + 2 + 1 + read-write + + + + + OT_INT_VAL + wdog timeout interrupt counter value + 0x8 + 32 + 0x00000000 + 0x0000FFFF + + + OT_INT_VAL + WDT timeout interrupt value + 0 + 16 + read-write + + + + + OT_RST_VAL + wdog timeout reset counter value + 0xc + 32 + 0x00000000 + 0x0000FFFF + + + OT_RST_VAL + WDT timeout reset value + 0 + 16 + read-write + + + + + WDT_REFRESH_REG + wdog refresh register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + WDT_REFRESH_REG + Write this register by 32'h5A45_524F to refresh wdog +Note: Reading this register can read back wdt real time counter value, while it is only used by debug purpose + 0 + 32 + write-only + + + + + WDT_STATUS + wdog status register + 0x14 + 32 + 0x00000000 + 0x0000007F + + + PARITY_ERROR + parity error +Write one to clear the bit + 6 + 1 + read-write + + + OT_RST + Timeout happens, a reset will happen once enable bit set +This bit can be cleared only by refreshing wdt or reset + 5 + 1 + read-only + + + OT_INT + Timeout happens, a interrupt will happen once enable bit set +This bit can be cleared only by refreshing wdt or reset + 4 + 1 + read-only + + + CTL_UNL_FAIL + Unlock ctrl reg update protection fail +Write one to clear the bit + 3 + 1 + read-write + + + CTL_VIO + Violate register update protection mechanism +Write one to clear the bit + 2 + 1 + read-write + + + REF_UNL_FAIL + Refresh unlock fail +Write one to clear the bit + 1 + 1 + read-write + + + REF_VIO + Refresh fail +Write one to clear the bit + 0 + 1 + read-write + + + + + CFG_PROT + ctrl register protection register + 0x18 + 32 + 0x00000000 + 0x000FFFFF + + + UPD_OT_TIME + The period in which register update has to be in after unlock +The required period is less than： 128 * 2 ^ UPD_OT_TIME * bus_clock_cycle + 16 + 4 + read-write + + + UPD_PSD + The password of unlocking register update + 0 + 16 + read-write + + + + + REF_PROT + refresh protection register + 0x1c + 32 + 0x00000000 + 0x0000FFFF + + + REF_UNL_PSD + The password to unlock refreshing + 0 + 16 + read-write + + + + + WDT_EN + Wdog enable + 0x20 + 32 + 0x00000000 + 0x00000001 + + + WDOG_EN + Wdog is enabled, the re-written of this register is impacted by enable lock function + 0 + 1 + read-write + + + + + REF_TIME + Refresh period value + 0x24 + 32 + 0x00000000 + 0x0000FFFF + + + REFRESH_PERIOD + The refresh period after refresh unlocked +Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter + 0 + 16 + read-write + + + + + + + EWDG1 + EWDG1 + EWDG + 0xf00b4000 + + + PEWDG + PEWDG + EWDG + 0xf4128000 + + + DMAMUX + DMAMUX + DMAMUX + 0xf00c4000 + + 0x0 + 0x80 + registers + + + + 32 + 0x4 + HDMA_MUX0,HDMA_MUX1,HDMA_MUX2,HDMA_MUX3,HDMA_MUX4,HDMA_MUX5,HDMA_MUX6,HDMA_MUX7,HDMA_MUX8,HDMA_MUX9,HDMA_MUX10,HDMA_MUX11,HDMA_MUX12,HDMA_MUX13,HDMA_MUX14,HDMA_MUX15,HDMA_MUX16,HDMA_MUX17,HDMA_MUX18,HDMA_MUX19,HDMA_MUX20,HDMA_MUX21,HDMA_MUX22,HDMA_MUX23,HDMA_MUX24,HDMA_MUX25,HDMA_MUX26,HDMA_MUX27,HDMA_MUX28,HDMA_MUX29,HDMA_MUX30,HDMA_MUX31 + MUXCFG[%s] + no description available + 0x0 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + write-only + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + write-only + + + + + + + HDMA + HDMA + DMAV2 + 0xf00c8000 + + 0x4 + 0x43c + registers + + + + IDMisc + ID Misc + 0x4 + 32 + 0x00000000 + 0x0000FF00 + + + DMASTATE + DMA state machine +localparam ST_IDLE = 3'b000; +localparam ST_READ = 3'b001; +localparam ST_READ_ACK = 3'b010; +localparam ST_WRITE = 3'b011; +localparam ST_WRITE_ACK = 3'b100; +localparam ST_LL = 3'b101; +localparam ST_END = 3'b110; +localparam ST_END_WAIT = 3'b111; + 13 + 3 + read-only + + + CURCHAN + current channel in used + 8 + 5 + read-only + + + + + DMACfg + DMAC Configuration Register + 0x10 + 32 + 0x00000000 + 0xC3FFFFFF + + + CHAINXFR + Chain transfer +0x0: Chain transfer is not configured +0x1: Chain transfer is configured + 31 + 1 + read-only + + + REQSYNC + DMA request synchronization. +The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, +which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. +0x0: Request synchronization is not configured +0x1: Request synchronization is configured + 30 + 1 + read-only + + + DATAWIDTH + AXI bus data width +0x0: 32 bits +0x1: 64 bits +0x2: 128 bits +0x3: 256 bits + 24 + 2 + read-only + + + ADDRWIDTH + AXI bus address width +0x18: 24 bits +0x19: 25 bits +... +0x40: 64 bits +Others: Invalid + 17 + 7 + read-only + + + CORENUM + DMA core number +0x0: 1 core +0x1: 2 cores + 16 + 1 + read-only + + + BUSNUM + AXI bus interface number +0x0: 1 AXI bus +0x1: 2 AXI busses + 15 + 1 + read-only + + + REQNUM + Request/acknowledge pair number +0x0: 0 pair +0x1: 1 pair +0x2: 2 pairs +... +0x10: 16 pairs + 10 + 5 + read-only + + + FIFODEPTH + FIFO depth +0x4: 4 entries +0x8: 8 entries +0x10: 16 entries +0x20: 32 entries +Others: Invalid + 4 + 6 + read-only + + + CHANNELNUM + Channel number +0x1: 1 channel +0x2: 2 channels +... +0x8: 8 channels +Others: Invalid + 0 + 4 + read-only + + + + + DMACtrl + DMAC Control Register + 0x14 + 32 + 0x00000000 + 0x00000001 + + + RESET + Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. +Note: The software reset may cause the in-completion of AXI transaction. + 0 + 1 + write-only + + + + + ChAbort + Channel Abort Register + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + CHABORT + Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. +Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) + 0 + 32 + write-only + + + + + INTHALFSTS + Harlf Complete Interrupt Status + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + STS + half transfer done irq status + 0 + 32 + read-write + + + + + INTTCSTS + Trans Complete Interrupt Status Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + STS + The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. +0x0: Channel n has no terminal count status +0x1: Channel n has terminal count status + 0 + 32 + write-only + + + + + INTABORTSTS + Abort Interrupt Status Register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + STS + The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. +0x0: Channel n has no abort status +0x1: Channel n has abort status + 0 + 32 + write-only + + + + + INTERRSTS + Error Interrupt Status Register + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + STS + The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: +- Bus error +- Unaligned address +- Unaligned transfer width +- Reserved configuration +0x0: Channel n has no error status +0x1: Channel n has error status + 0 + 32 + write-only + + + + + ChEN + Channel Enable Register + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + CHEN + Alias of the Enable field of all ChnCtrl registers + 0 + 32 + read-only + + + + + 32 + 0x20 + ch0,ch1,ch2,ch3,ch4,ch5,ch6,ch7,ch8,ch9,ch10,ch11,ch12,ch13,ch14,ch15,ch16,ch17,ch18,ch19,ch20,ch21,ch22,ch23,ch24,ch25,ch26,ch27,ch28,ch29,ch30,ch31 + CHCTRL[%s] + no description available + 0x40 + + Ctrl + Channel &index0 Control Register + 0x0 + 32 + 0x00000000 + 0xFFFFF01F + + + INFINITELOOP + set to loop current config infinitely + 31 + 1 + read-write + + + HANDSHAKEOPT + 0: one request to transfer one burst +1: one request to transfer all the data defined in ch_tts + 30 + 1 + read-write + + + PRIORITY + Channel priority level +0x0: Lower priority +0x1: Higher priority + 29 + 1 + read-write + + + BURSTOPT + set to change burst_size definition + 28 + 1 + read-write + + + SRCBURSTSIZE + Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. +The burst transfer byte number is (SrcBurstSize * SrcWidth). +0x0: 1 transfer +0x1: 2 transfers +0x2: 4 transfers +0x3: 8 transfers +0x4: 16 transfers +0x5: 32 transfers +0x6: 64 transfers +0x7: 128 transfers +0x8: 256 transfers +0x9:512 transfers +0xa: 1024 transfers +0xb - 0xf: Reserved, setting this field with a reserved value triggers the error exception + 24 + 4 + read-write + + + SRCWIDTH + Source transfer width +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception + 21 + 3 + read-write + + + DSTWIDTH + Destination transfer width. +Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; +otherwise the error event will be triggered. +For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. +See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception + 18 + 3 + read-write + + + SRCMODE + Source DMA handshake mode +0x0: Normal mode +0x1: Handshake mode +Normal mode is enabled and started by software set Enable bit; +Handshake mode is enabled by software set Enable bit, started by hardware dma request from DMAMUX block + 17 + 1 + read-write + + + DSTMODE + Destination DMA handshake mode +0x0: Normal mode +0x1: Handshake mode +the difference bewteen Source/Destination handshake mode is: +the dma block will response hardware request after read in Source handshake mode; +the dma block will response hardware request after write in Destination handshake mode; +NOTE: can't set SrcMode and DstMode at same time, otherwise result unknown. + 16 + 1 + read-write + + + SRCADDRCTRL + Source address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 14 + 2 + read-write + + + DSTADDRCTRL + Destination address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 12 + 2 + read-write + + + INTHALFCNTMASK + Channel half interrupt mask +0x0: Allow the half interrupt to be triggered +0x1: Disable the half interrupt + 4 + 1 + read-write + + + INTABTMASK + Channel abort interrupt mask +0x0: Allow the abort interrupt to be triggered +0x1: Disable the abort interrupt + 3 + 1 + read-write + + + INTERRMASK + Channel error interrupt mask +0x0: Allow the error interrupt to be triggered +0x1: Disable the error interrupt + 2 + 1 + read-write + + + INTTCMASK + Channel terminal count interrupt mask +0x0: Allow the terminal count interrupt to be triggered +0x1: Disable the terminal count interrupt + 1 + 1 + read-write + + + ENABLE + Channel enable bit +0x0: Disable +0x1: Enable + 0 + 1 + read-write + + + + + TranSize + Channel &index0Transfer Size Register + 0x4 + 32 + 0x00000000 + 0x0FFFFFFF + + + TRANSIZE + Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. +If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + 0 + 28 + read-write + + + + + SrcAddr + Channel &index0 Source Address Low Part Register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SRCADDRL + Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + 0 + 32 + read-write + + + + + ChanReqCtrl + Channel &index0 DMA Request Control Register + 0xc + 32 + 0x00000000 + 0x1F1F0000 + + + SRCREQSEL + Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + 24 + 5 + read-write + + + DSTREQSEL + Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + 16 + 5 + read-write + + + + + DstAddr + Channel &index0 Destination Address Low Part Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + DSTADDRL + Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + 0 + 32 + read-write + + + + + LLPointer + Channel &index0 Linked List Pointer Low Part Register + 0x18 + 32 + 0x00000000 + 0xFFFFFFF8 + + + LLPOINTERL + Low part of the pointer to the next descriptor. The pointer must be double word aligned. + 3 + 29 + read-write + + + + + + + + GPIOM + GPIOM + GPIOM + 0xf00d8000 + + 0x0 + 0x780 + registers + + + + 15 + 0x80 + gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy + ASSIGN[%s] + no description available + 0x0 + + 32 + 0x4 + PIN00,PIN01,PIN02,PIN03,PIN04,PIN05,PIN06,PIN07,PIN08,PIN09,PIN10,PIN11,PIN12,PIN13,PIN14,PIN15,PIN16,PIN17,PIN18,PIN19,PIN20,PIN21,PIN22,PIN23,PIN24,PIN25,PIN26,PIN27,PIN28,PIN29,PIN30,PIN31 + PIN[%s] + no description available + 0x0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +2: cpu0 fastgpio + 0 + 2 + read-write + + + + + + + + USB0 + USB0 + USB + 0xf300c000 + + 0x80 + 0x1a8 + registers + + + + GPTIMER0LD + General Purpose Timer #0 Load Register + 0x80 + 32 + 0x00000000 + 0x00FFFFFF + + + GPTLD + GPTLD +General Purpose Timer Load Value +These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. +This value represents the time in microseconds minus 1 for the timer duration. +Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. +NOTE: Max value is 0xFFFFFF or 16.777215 seconds. + 0 + 24 + read-write + + + + + GPTIMER0CTRL + General Purpose Timer #0 Controller Register + 0x84 + 32 + 0x00000000 + 0xC1FFFFFF + + + GPTRUN + GPTRUN +General Purpose Timer Run +GPTCNT bits are not effected when setting or clearing this bit. +0 - Stop counting +1 - Run + 31 + 1 + read-write + + + GPTRST + GPTRST +General Purpose Timer Reset +0 - No action +1 - Load counter value from GPTLD bits in n_GPTIMER0LD + 30 + 1 + write-only + + + GPTMODE + GPTMODE +General Purpose Timer Mode +In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is +reset by software; +In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the +counter value from GPTLD bits to start again. +0 - One Shot Mode +1 - Repeat Mode + 24 + 1 + read-write + + + GPTCNT + GPTCNT +General Purpose Timer Counter. +This field is the count value of the countdown timer. + 0 + 24 + read-only + + + + + GPTIMER1LD + General Purpose Timer #1 Load Register + 0x88 + 32 + 0x00000000 + 0x00FFFFFF + + + GPTLD + GPTLD +General Purpose Timer Load Value +These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. +This value represents the time in microseconds minus 1 for the timer duration. +Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. +NOTE: Max value is 0xFFFFFF or 16.777215 seconds. + 0 + 24 + read-write + + + + + GPTIMER1CTRL + General Purpose Timer #1 Controller Register + 0x8c + 32 + 0x00000000 + 0xC1FFFFFF + + + GPTRUN + GPTRUN +General Purpose Timer Run +GPTCNT bits are not effected when setting or clearing this bit. +0 - Stop counting +1 - Run + 31 + 1 + read-write + + + GPTRST + GPTRST +General Purpose Timer Reset +0 - No action +1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD + 30 + 1 + write-only + + + GPTMODE + GPTMODE +General Purpose Timer Mode +In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is +reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and +automatically reload the counter value from GPTLD bits to start again. +0 - One Shot Mode +1 - Repeat Mode + 24 + 1 + read-write + + + GPTCNT + GPTCNT +General Purpose Timer Counter. +This field is the count value of the countdown timer. + 0 + 24 + read-only + + + + + SBUSCFG + System Bus Config Register + 0x90 + 32 + 0x00000000 + 0x00000007 + + + AHBBRST + AHBBRST +AHB master interface Burst configuration +These bits control AHB master transfer type sequence (or priority). +NOTE: This register overrides n_BURSTSIZE register when its value is not zero. +000 - Incremental burst of unspecified length only +001 - INCR4 burst, then single transfer +010 - INCR8 burst, INCR4 burst, then single transfer +011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer +100 - Reserved, don't use +101 - INCR4 burst, then incremental burst of unspecified length +110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length +111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length + 0 + 3 + read-write + + + + + USBCMD + USB Command Register + 0x140 + 32 + 0x00080000 + 0x00FFFB7F + + + ITC + ITC +Interrupt Threshold Control -Read/Write. +The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. +ITC contains the maximum interrupt interval measured in micro-frames. Valid values are +shown below. +Value Maximum Interrupt Interval +00000000 - Immediate (no threshold) +00000001 - 1 micro-frame +00000010 - 2 micro-frames +00000100 - 4 micro-frames +00001000 - 8 micro-frames +00010000 - 16 micro-frames +00100000 - 32 micro-frames +01000000 - 64 micro-frames + 16 + 8 + read-write + + + FS_2 + FS_2 +Frame List Size - (Read/Write or Read Only). [host mode only] +This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. +This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. +NOTE: This field is made up from USBCMD bits 15, 3 and 2. +Value Meaning +0b000 - 1024 elements (4096 bytes) Default value +0b001 - 512 elements (2048 bytes) +0b010 - 256 elements (1024 bytes) +0b011 - 128 elements (512 bytes) +0b100 - 64 elements (256 bytes) +0b101 - 32 elements (128 bytes) +0b110 - 16 elements (64 bytes) +0b111 - 8 elements (32 bytes) + 15 + 1 + read-write + + + ATDTW + ATDTW +Add dTD TripWire - Read/Write. [device mode only] +This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's +linked list. This bit is set and cleared by software. +This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD +to a primed endpoint may go unrecognized. + 14 + 1 + read-write + + + SUTW + SUTW +Setup TripWire - Read/Write. [device mode only] +This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. +If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then +there is a hazard when new setup data arrives while the DCD is copying the setup data payload +from the QH for a previous setup packet. This bit is set and cleared by software. +This bit would also be cleared by hardware when a hazard detected. + 13 + 1 + read-write + + + PRM + Asynchronous Schedule start- Write only， host mode only。 +this bit is used to notify hostcontroller to start async schedule immediately. + 12 + 1 + write-only + + + ASPE + ASPE +Asynchronous Schedule Park Mode Enable - Read/Write. +If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. +Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. +When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. +NOTE: ASPE bit reset value: '0b' for OTG controller . + 11 + 1 + read-write + + + ASP + ASP +Asynchronous Schedule Park Mode Count - Read/Write. +If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. +It contains a count of the number of successive transactions the host controller is allowed to +execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. +Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. +This field is set to 3h in all controller core. + 8 + 2 + read-write + + + IAA + IAA +Interrupt on Async Advance Doorbell - Read/Write. +This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. +When the host controller has evicted all appropriate cached schedule states, +it sets the Interrupt on Async Advance status bit in the USBSTS register. +If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. +The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. +Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. +This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. + 6 + 1 + read-write + + + ASE + ASE +Asynchronous Schedule Enable - Read/Write. Default 0b. +This bit controls whether the host controller skips processing the Asynchronous Schedule. +Only the host controller uses this bit. +Values Meaning +0 - Do not process the Asynchronous Schedule. +1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. + 5 + 1 + read-write + + + PSE + PSE +Periodic Schedule Enable- Read/Write. Default 0b. +This bit controls whether the host controller skips processing the Periodic Schedule. +Only the host controller uses this bit. +Values Meaning +0 - Do not process the Periodic Schedule +1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. + 4 + 1 + read-write + + + FS_1 + FS_1 +See description at bit 15 + 2 + 2 + read-write + + + RST + RST +Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. +This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. +Host operation mode: +When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. +Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. +Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. +Attempting to reset an actively running host controller will result in undefined behavior. +Device operation mode: +When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. +Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. +In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. + 1 + 1 + read-write + + + RS + RS +Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. +Host operation mode: +When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. +When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. +The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. +Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). +Device operation mode: +Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. +This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. +Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. + 0 + 1 + read-write + + + + + USBSTS + USB Status Register + 0x144 + 32 + 0x00000000 + 0x030DF1FF + + + TI1 + TI1 +General Purpose Timer Interrupt 1(GPTINT1)--R/WC. +This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this +bit will clear it. + 25 + 1 + read-write + + + TI0 + TI0 +General Purpose Timer Interrupt 0(GPTINT0)--R/WC. +This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this +bit clears it. + 24 + 1 + read-write + + + UPI + USB Host Periodic Interrupt – RWC. Default = 0b. +This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction +where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. +This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. +A short packet is when the actual number of bytes received was less than expected. +This bit is not used by the device controller and will always be zero. + 19 + 1 + read-write + + + UAI + USB Host Asynchronous Interrupt – RWC. Default = 0b. +This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction +where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. +This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. +A short packet is when the actual number of bytes received was less than expected. +This bit is not used by the device controller and will always be zero + 18 + 1 + read-write + + + NAKI + NAKI +NAK Interrupt Bit--RO. +This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and +corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware +when all Enabled TX/RX Endpoint NAK bits are cleared. + 16 + 1 + read-only + + + AS + AS +Asynchronous Schedule Status - Read Only. +This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. +The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. +When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). +Only used in the host operation mode. + 15 + 1 + read-only + + + PS + PS +Periodic Schedule Status - Read Only. +This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. +The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. +When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). +Only used in the host operation mode. + 14 + 1 + read-only + + + RCL + RCL +Reclamation - Read Only. +This is a read-only status bit used to detect an empty asynchronous schedule. +Only used in the host operation mode. + 13 + 1 + read-only + + + HCH + HCH +HCHaIted - Read Only. +This bit is a zero whenever the Run/Stop bit is a one. + The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, + either by software or by the Controller hardware (for example, an internal error). +Only used in the host operation mode. +Default value is '0b' for OTG core . +This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE +register. +NOTE: HCH bit reset value: '0b' for OTG controller core . + 12 + 1 + read-only + + + SLI + SLI +DCSuspend - R/WC. +When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. +Only used in device operation mode. + 8 + 1 + read-write + + + SRI + SRI +SOF Received - R/WC. +When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. +When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. +Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. +Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. +In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. +Software writes a 1 to this bit to clear it. + 7 + 1 + read-write + + + URI + URI +USB Reset Received - R/WC. +When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. +Software can write a 1 to this bit to clear the USB Reset Received status bit. +Only used in device operation mode. + 6 + 1 + read-write + + + AAI + AAI +Interrupt on Async Advance - R/WC. +System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule +by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. +Only used in host operation mode. + 5 + 1 + read-write + + + SEI + System Error – RWC. Default = 0b. +In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. +In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) + 4 + 1 + read-write + + + FRI + FRI +Frame List Rollover - R/WC. +The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to +zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the +frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the +Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host +Controller sets this bit to a one every time FHINDEX [12] toggles. +Only used in host operation mode. + 3 + 1 + read-write + + + PCI + PCI +Port Change Detect - R/WC. +The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, +or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. +The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. +When the port controller exits the full or high-speed operation states due to Reset or Suspend events, +the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. + 2 + 1 + read-write + + + UEI + UEI +USB Error Interrupt (USBERRINT) - R/WC. +When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. +This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. + 1 + 1 + read-write + + + UI + UI +USB Interrupt (USBINT) - R/WC. +This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB +transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. +This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when +the actual number of bytes received was less than the expected number of bytes. + 0 + 1 + read-write + + + + + USBINTR + Interrupt Enable Register + 0x148 + 32 + 0x00000000 + 0x030D01FF + + + TIE1 + TIE1 +General Purpose Timer #1 Interrupt Enable +When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. + 25 + 1 + read-write + + + TIE0 + TIE0 +General Purpose Timer #0 Interrupt Enable +When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. + 24 + 1 + read-write + + + UPIE + UPIE +USB Host Periodic Interrupt Enable +When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an +interrupt at the next interrupt threshold. + 19 + 1 + read-write + + + UAIE + UAIE +USB Host Asynchronous Interrupt Enable +When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an +interrupt at the next interrupt threshold. + 18 + 1 + read-write + + + NAKE + NAKE +NAK Interrupt Enable +When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. + 16 + 1 + read-only + + + SLE + SLE +Sleep Interrupt Enable +When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. +Only used in device operation mode. + 8 + 1 + read-write + + + SRE + SRE +SOF Received Interrupt Enable +When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. + 7 + 1 + read-write + + + URE + URE +USB Reset Interrupt Enable +When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in device operation mode. + 6 + 1 + read-write + + + AAE + AAE +Async Advance Interrupt Enable +When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in host operation mode. + 5 + 1 + read-write + + + SEE + SEE +System Error Interrupt Enable +When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in host operation mode. + 4 + 1 + read-write + + + FRE + FRE +Frame List Rollover Interrupt Enable +When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in host operation mode. + 3 + 1 + read-write + + + PCE + PCE +Port Change Detect Interrupt Enable +When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. + 2 + 1 + read-write + + + UEE + UEE +USB Error Interrupt Enable +When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. + 1 + 1 + read-write + + + UE + UE +USB Interrupt Enable +When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. + 0 + 1 + read-write + + + + + FRINDEX + USB Frame Index Register + 0x14c + 32 + 0x00000000 + 0x00003FFF + + + FRINDEX + FRINDEX +Frame Index. +The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. +This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. +The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. +USBCMD [Frame List Size] Number Elements N +In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. +In either mode bits 2:0 indicate the current microframe. +The bit field values description below is represented as (Frame List Size) Number Elements N. +00000000000000 - (1024) 12 +00000000000001 - (512) 11 +00000000000010 - (256) 10 +00000000000011 - (128) 9 +00000000000100 - (64) 8 +00000000000101 - (32) 7 +00000000000110 - (16) 6 +00000000000111 - (8) 5 + 0 + 14 + read-write + + + + + DEVICEADDR + Device Address Register + UNION_154 + 0x154 + 32 + 0x00000000 + 0xFF000000 + + + USBADR + USBADR +Device Address. +These bits correspond to the USB device address + 25 + 7 + read-write + + + USBADRA + USBADRA +Device Address Advance. Default=0. +When this bit is '0', any writes to USBADR are instantaneous. + When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. +After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. +Hardware will automatically clear this bit on the following conditions: +1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). +2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). +3) Device Reset occurs (USBADR is reset to 0). +NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. +This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. +If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), +the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. + 24 + 1 + read-write + + + + + PERIODICLISTBASE + Frame List Base Address Register + UNION_154 + 0x154 + 32 + 0x00000000 + 0xFFFFF000 + + + BASEADR + BASEADR +Base Address (Low). +These bits correspond to memory address signals [31:12], respectively. +Only used by the host controller. + 12 + 20 + read-write + + + + + ASYNCLISTADDR + Next Asynch. Address Register + UNION_158 + 0x158 + 32 + 0x00000000 + 0xFFFFFFE0 + + + ASYBASE + ASYBASE +Link Pointer Low (LPL). +These bits correspond to memory address signals [31:5], respectively. This field may only reference a +Queue Head (QH). +Only used by the host controller. + 5 + 27 + read-write + + + + + ENDPTLISTADDR + Endpoint List Address Register + UNION_158 + 0x158 + 32 + 0x00000000 + 0xFFFFF800 + + + EPBASE + EPBASE +Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. +This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). + 11 + 21 + read-write + + + + + BURSTSIZE + Programmable Burst Size Register + 0x160 + 32 + 0x00000000 + 0x0000FFFF + + + TXPBURST + TXPBURST +Programmable TX Burst Size. +Default value is determined by TXBURST bits in n_HWTXBUF. +This register represents the maximum length of a the burst in 32-bit words while moving data from system +memory to the USB bus. + 8 + 8 + read-write + + + RXPBURST + RXPBURST +Programmable RX Burst Size. +Default value is determined by TXBURST bits in n_HWRXBUF. +This register represents the maximum length of a the burst in 32-bit words while moving data from the +USB bus to system memory. + 0 + 8 + read-write + + + + + TXFILLTUNING + TX FIFO Fill Tuning Register + 0x164 + 32 + 0x00000000 + 0x003F1F7F + + + TXFIFOTHRES + TXFIFOTHRES +FIFO Burst Threshold. (Read/Write) +This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. +The minimum value is 2 and this value should be a low as possible to maximize USB performance. +A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth +where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. +This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. + 16 + 6 + read-write + + + TXSCHHEALTH + TXSCHHEALTH +Scheduler Health Counter. (Read/Write To Clear) +Table continues on the next page +This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES +before running out of time to send the packet before the next Start-Of-Frame. +This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. +Writing to this register will clear the counter and this counter will max. at 31. + 8 + 5 + read-write + + + TXSCHOH + TXSCHOH +Scheduler Overhead. (Read/Write) [Default = 0] +This register adds an additional fixed offset to the schedule time estimator described above as Tff. +As an approximation, the value chosen for this register should limit the number of back-off events captured +in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. +Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. +The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. +The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. +Default value is '08h' for OTG controller core . + 0 + 7 + read-write + + + + + ENDPTNAK + Endpoint NAK Register + 0x178 + 32 + 0x00000000 + 0xFFFFFFFF + + + EPTN + EPTN +TX Endpoint NAK - R/WC. +Each TX endpoint has 1 bit in this field. The bit is set when the +device sends a NAK handshake on a received IN token for the corresponding endpoint. +Bit [N] - Endpoint #[N], N is 0-7 + 16 + 16 + read-write + + + EPRN + EPRN +RX Endpoint NAK - R/WC. +Each RX endpoint has 1 bit in this field. The bit is set when the +device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. +Bit [N] - Endpoint #[N], N is 0-7 + 0 + 16 + read-write + + + + + ENDPTNAKEN + Endpoint NAK Enable Register + 0x17c + 32 + 0x00000000 + 0xFFFFFFFF + + + EPTNE + EPTNE +TX Endpoint NAK Enable - R/W. +Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the +corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. +Bit [N] - Endpoint #[N], N is 0-7 + 16 + 16 + read-write + + + EPRNE + EPRNE +RX Endpoint NAK Enable - R/W. +Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the +corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. +Bit [N] - Endpoint #[N], N is 0-7 + 0 + 16 + read-write + + + + + PORTSC1 + Port Status & Control + 0x184 + 32 + 0x00000000 + 0x3DFF1FFF + + + STS + STS +Serial Transceiver Select +1 Serial Interface Engine is selected +0 Parallel Interface signals is selected +Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. +When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. + 29 + 1 + read-write + + + PTW + PTW +Parallel Transceiver Width +This bit has no effect if serial interface engine is used. +0 - Select the 8-bit UTMI interface [60MHz] +1 - Select the 16-bit UTMI interface [30MHz] + 28 + 1 + read-write + + + PSPD + PSPD +Port Speed - Read Only. +This register field indicates the speed at which the port is operating. +00 - Full Speed +01 - Low Speed +10 - High Speed +11 - Undefined + 26 + 2 + read-only + + + PFSC + PFSC +Port Force Full Speed Connect - Read/Write. Default = 0b. +When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp +sequence that allows the port to identify itself as High Speed. +0 - Normal operation +1 - Forced to full speed + 24 + 1 + read-write + + + PHCD + PHCD +PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. +When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY +clock. +NOTE: The PHY clock cannot be disabled if it is being used as the system clock. +In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD +Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend +will be cleared automatically when the host initials resume. Before forcing a resume from the device, the +device controller driver must clear this bit. +In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put +into suspend mode or when no downstream device is connected. Low power suspend is completely +under the control of software. +0 - Enable PHY clock +1 - Disable PHY clock + 23 + 1 + read-write + + + WKOC + WKOC +Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. +Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. +This field is zero if Port Power(PORTSC1) is zero. + 22 + 1 + read-write + + + WKDC + WKDC +Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables +the port to be sensitive to device disconnects as wake-up events. +This field is zero if Port Power(PORTSC1) is zero or in device mode. + 21 + 1 + read-write + + + WKCN + WKCN +Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. +Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. +This field is zero if Port Power(PORTSC1) is zero or in device mode. + 20 + 1 + read-write + + + PTC + PTC +Port Test Control - Read/Write. Default = 0000b. +Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. +The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. +Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. +Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. +NOTE: Low speed operations are not supported as a peripheral device. +Any other value than zero indicates that the port is operating in test mode. +Value Specific Test +0000 - TEST_MODE_DISABLE +0001 - J_STATE +0010 - K_STATE +0011 - SE0 (host) / NAK (device) +0100 - Packet +0101 - FORCE_ENABLE_HS +0110 - FORCE_ENABLE_FS +0111 - FORCE_ENABLE_LS +1000-1111 - Reserved + 16 + 4 + read-write + + + PP + PP +Port Power (PP)-Read/Write or Read Only. +The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: +PPC +PP Operation +0 +1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. +1 +1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). +When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. +When an over-current condition is detected on a powered port and PPC is a one, +the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). +This feature is implemented in all controller cores (PPC = 1). + 12 + 1 + read-write + + + LS + LS +Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal +lines. +In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because +the port controller state machine and the port routing manage the connection of LS and FS. +In device mode, the use of linestate by the device controller driver is not necessary. +The encoding of the bits are: +Bits [11:10] Meaning +00 - SE0 +01 - K-state +10 - J-state +11 - Undefined + 10 + 2 + read-only + + + HSP + HSP +High-Speed Port - Read Only. Default = 0b. +When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the +host/device connected to the port is not in a high-speed mode. +NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. + 9 + 1 + read-only + + + PR + PR +Port Reset - Read/Write or Read Only. Default = 0b. +In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. +When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. +This bit will automatically change to zero after the reset sequence is complete. +This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. +In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. + 8 + 1 + read-write + + + SUSP + SUSP +Suspend - Read/Write or Read Only. Default = 0b. +1=Port in suspend state. 0=Port not in suspend state. +In Host Mode: Read/Write. +Port Enabled Bit and Suspend bit of this register define the port states as follows: +Bits [Port Enabled, Suspend] Port State +0x Disable +10 Enable +11 Suspend +When in suspend state, downstream propagation of data is blocked on this port, except for port reset. +The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. +In the suspend state, the port is sensitive to resume detection. +Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. +The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. +If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: Read Only. +In device mode this bit is a read only status bit. + 7 + 1 + read-write + + + FPR + FPR +Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. +In Host Mode: +Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. +When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. +This bit will automatically change to zero after the resume sequence is complete. +This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. +Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. +The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. +Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. +This field is zero if Port Power(PORTSC1) is zero in host mode. +This bit is not-EHCI compatible. +In Device mode: +After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. +The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. +The bit will be cleared when the device returns to normal operation. + Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. + 6 + 1 + read-write + + + OCC + OCC +Over-current Change-R/WC. Default=0. +This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. + 5 + 1 + read-write + + + OCA + OCA +Over-current Active-Read Only. Default 0. +This bit will automatically transition from one to zero when the over current condition is removed. +0 - This port does not have an over-current condition. +1 - This port currently has an over-current condition + 4 + 1 + read-only + + + PEC + PEC +Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. +In Host Mode: +For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or +due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). +Software clears this by writing a one to it. +This field is zero if Port Power(PORTSC1) is zero. +In Device mode: +The device port is always enabled, so this bit is always '0b'. + 3 + 1 + read-write + + + PE + PE +Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. +In Host Mode: +Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. +Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. +Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. +When the port is disabled, (0b) downstream propagation of data is blocked except for reset. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: +The device port is always enabled, so this bit is always '1b'. + 2 + 1 + read-write + + + CSC + CSC +Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. +In Host Mode: +Indicates a change has occurred in the port's Current Connect Status. +The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. +For example, the insertion status changes twice before system software has cleared the changed condition, +hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: +This bit is undefined in device controller mode. + 1 + 1 + read-write + + + CCS + CCS +Current Connect Status-Read Only. +In Host Mode: +1=Device is present on port. 0=No device is present. Default = 0. +This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: +1=Attached. 0=Not Attached. Default=0. +A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. +A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. +It does not state the device being disconnected or Suspended. + 0 + 1 + read-write + + + + + OTGSC + On-The-Go Status & control Register + 0x1a4 + 32 + 0x00000000 + 0x07070723 + + + ASVIE + ASVIE +A Session Valid Interrupt Enable - Read/Write. + 26 + 1 + read-write + + + AVVIE + AVVIE +A VBus Valid Interrupt Enable - Read/Write. +Setting this bit enables the A VBus valid interrupt. + 25 + 1 + read-write + + + IDIE + IDIE +USB ID Interrupt Enable - Read/Write. +Setting this bit enables the USB ID interrupt. + 24 + 1 + read-write + + + ASVIS + ASVIS +A Session Valid Interrupt Status - Read/Write to Clear. +This bit is set when VBus has either risen above or fallen below the A session valid threshold. +Software must write a one to clear this bit. + 18 + 1 + read-write + + + AVVIS + AVVIS +A VBus Valid Interrupt Status - Read/Write to Clear. +This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. +Software must write a one to clear this bit. + 17 + 1 + read-write + + + IDIS + IDIS +USB ID Interrupt Status - Read/Write. +This bit is set when a change on the ID input has been detected. +Software must write a one to clear this bit. + 16 + 1 + read-write + + + ASV + ASV +A Session Valid - Read Only. +Indicates VBus is above the A session valid threshold. + 10 + 1 + read-only + + + AVV + AVV +A VBus Valid - Read Only. +Indicates VBus is above the A VBus valid threshold. + 9 + 1 + read-only + + + ID + ID +USB ID - Read Only. +0 = A device, 1 = B device + 8 + 1 + read-only + + + IDPU + IDPU +ID Pullup - Read/Write +This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input +will not be sampled. + 5 + 1 + read-write + + + VC + VC +VBUS Charge - Read/Write. +Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. + 1 + 1 + read-write + + + VD + VD +VBUS_Discharge - Read/Write. +Setting this bit causes VBus to discharge through a resistor. + 0 + 1 + read-write + + + + + USBMODE + USB Device Mode Register + 0x1a8 + 32 + 0x00000000 + 0x0000001F + + + SDIS + SDIS +Stream Disable Mode. (0 - Inactive [default]; 1 - Active) +Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. +This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. +Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. +Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems +where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. +NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for +the scheduler when using this feature. +NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. + 4 + 1 + read-write + + + SLOM + SLOM +Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . +0 - Setup Lockouts On (default); +1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. + 3 + 1 + read-write + + + ES + ES +Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the +host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected +by the value of this bit because they are based upon the 32-bit word. +Bit Meaning +0 - Little Endian [Default] +1 - Big Endian + 2 + 1 + read-write + + + CM + CM +Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only +implementations. For those designs that contain both host & device capability, the controller defaults to +an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ +device controllers, this register can only be written once after reset. If it is necessary to switch modes, +software must reset the controller by writing to the RESET bit in the USBCMD register before +reprogramming this register. +For OTG controller core, reset value is '00b'. +00 - Idle [Default for combination host/device] +01 - Reserved +10 - Device Controller [Default for device only controller] +11 - Host Controller [Default for host only controller] + 0 + 2 + read-write + + + + + ENDPTSETUPSTAT + Endpoint Setup Status Register + 0x1ac + 32 + 0x00000000 + 0x0000FFFF + + + ENDPTSETUPSTAT + ENDPTSETUPSTAT +Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. +Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. +The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. +This register is only used in device mode. + 0 + 16 + read-write + + + + + ENDPTPRIME + Endpoint Prime Register + 0x1b0 + 32 + 0x00000000 + 0xFFFFFFFF + + + PETB + PETB +Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a +buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. +Software should write a one to the corresponding bit when posting a new transfer descriptor to an +endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor +from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated +endpoint(s) is (are) successfully primed. +NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD +is retired, and the dQH is updated. +PETB[N] - Endpoint #N, N is in 0..7 + 16 + 16 + read-write + + + PERB + PERB +Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. +Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. +Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. +Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. +NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD +is retired, and the dQH is updated. +PERB[N] - Endpoint #N, N is in 0..7 + 0 + 16 + read-write + + + + + ENDPTFLUSH + Endpoint Flush Register + 0x1b4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FETB + FETB +Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. +If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. +Hardware clears this register after the endpoint flush operation is successful. +FETB[N] - Endpoint #N, N is in 0..7 + 16 + 16 + read-write + + + FERB + FERB +Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. + If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. +Hardware clears this register after the endpoint flush operation is successful. +FERB[N] - Endpoint #N, N is in 0..7 + 0 + 16 + read-write + + + + + ENDPTSTAT + Endpoint Status Register + 0x1b8 + 32 + 0x00000000 + 0xFFFFFFFF + + + ETBR + ETBR +Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. +This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. +There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. +This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. +Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. +NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. +ETBR[N] - Endpoint #N, N is in 0..7 + 16 + 16 + read-only + + + ERBR + ERBR +Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective +endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a +corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the +ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB +traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the +USB DMA system, or through the ENDPTFLUSH register. +NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations +when a dTD is retired, and the dQH is updated. +ERBR[N] - Endpoint #N, N is in 0..7 + 0 + 16 + read-only + + + + + ENDPTCOMPLETE + Endpoint Complete Register + 0x1bc + 32 + 0x00000000 + 0xFFFFFFFF + + + ETCE + ETCE +Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. +If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. +ETCE[N] - Endpoint #N, N is in 0..7 + 16 + 16 + read-write + + + ERCE + ERCE +Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred +and software should read the corresponding endpoint queue to determine the transfer status. If the +corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the +USBINT . Writing one clears the corresponding bit in this register. +ERCE[N] - Endpoint #N, N is in 0..7 + 0 + 16 + read-write + + + + + 16 + 0x4 + ENDPTCTRL0,ENDPTCTRL1,ENDPTCTRL2,ENDPTCTRL3,ENDPTCTRL4,ENDPTCTRL5,ENDPTCTRL6,ENDPTCTRL7,ENDPTCTRL8,ENDPTCTRL9,ENDPTCTRL10,ENDPTCTRL11,ENDPTCTRL12,ENDPTCTRL13,ENDPTCTRL14,ENDPTCTRL15 + ENDPTCTRL[%s] + no description available + 0x1c0 + 32 + 0x00000000 + 0x00CD00CD + + + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 + read-write + + + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 + 1 + write-only + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 + read-write + + + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured +as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 + 1 + read-write + + + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 + 1 + read-write + + + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 + 1 + write-only + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 + read-write + + + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 + 1 + read-write + + + + + OTG_CTRL0 + No description available + 0x200 + 32 + 0x00000000 + 0x020B3F90 + + + OTG_WKDPDMCHG_EN + No description available + 25 + 1 + read-write + + + AUTORESUME_EN + No description available + 19 + 1 + read-write + + + OTG_VBUS_WAKEUP_EN + No description available + 17 + 1 + read-write + + + OTG_ID_WAKEUP_EN + No description available + 16 + 1 + read-write + + + OTG_VBUS_SOURCE_SEL + No description available + 13 + 1 + read-write + + + OTG_UTMI_SUSPENDM_SW + default 0 for naneng usbphy + 12 + 1 + read-write + + + OTG_UTMI_RESET_SW + default 1 for naneng usbphy + 11 + 1 + read-write + + + OTG_WAKEUP_INT_ENABLE + No description available + 10 + 1 + read-write + + + OTG_POWER_MASK + No description available + 9 + 1 + read-write + + + OTG_OVER_CUR_POL + No description available + 8 + 1 + read-write + + + OTG_OVER_CUR_DIS + No description available + 7 + 1 + read-write + + + SER_MODE_SUSPEND_EN + for naneng usbphy, only switch to serial mode when suspend + 4 + 1 + read-write + + + + + PHY_CTRL0 + No description available + 0x210 + 32 + 0x00000000 + 0x02007007 + + + GPIO_ID_SEL_N + No description available + 25 + 1 + read-write + + + ID_DIG_OVERRIDE + No description available + 14 + 1 + read-write + + + SESS_VALID_OVERRIDE + No description available + 13 + 1 + read-write + + + VBUS_VALID_OVERRIDE + No description available + 12 + 1 + read-write + + + ID_DIG_OVERRIDE_EN + No description available + 2 + 1 + read-write + + + SESS_VALID_OVERRIDE_EN + No description available + 1 + 1 + read-write + + + VBUS_VALID_OVERRIDE_EN + No description available + 0 + 1 + read-write + + + + + PHY_CTRL1 + No description available + 0x214 + 32 + 0x00000000 + 0x00100002 + + + UTMI_CFG_RST_N + No description available + 20 + 1 + read-write + + + UTMI_OTG_SUSPENDM + OTG suspend, not utmi_suspendm + 1 + 1 + read-write + + + + + TOP_STATUS + No description available + 0x220 + 32 + 0x00000000 + 0x80000000 + + + WAKEUP_INT_STATUS + No description available + 31 + 1 + read-write + + + + + PHY_STATUS + No description available + 0x224 + 32 + 0x00000000 + 0x800000F5 + + + UTMI_CLK_VALID + No description available + 31 + 1 + read-write + + + LINE_STATE + No description available + 6 + 2 + read-write + + + HOST_DISCONNECT + No description available + 5 + 1 + read-write + + + ID_DIG + No description available + 4 + 1 + read-write + + + UTMI_SESS_VALID + No description available + 2 + 1 + read-write + + + VBUS_VALID + No description available + 0 + 1 + read-write + + + + + + + SEC + SEC + SEC + 0xf3044000 + + 0x0 + 0x18 + registers + + + + SECURE_STATE + Secure state + 0x0 + 32 + 0x00000000 + 0x000300F0 + + + ALLOW_NSC + Non-secure state allow +0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter non-secure state + 17 + 1 + read-only + + + ALLOW_SEC + Secure state allow +0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter secure state + 16 + 1 + read-only + + + PMIC_FAIL + PMIC secure state one hot indicator +0: secure state is not in fail state +1: secure state is in fail state + 7 + 1 + read-write + + + PMIC_NSC + PMIC secure state one hot indicator +0: secure state is not in non-secure state +1: secure state is in non-secure state + 6 + 1 + read-write + + + PMIC_SEC + PMIC secure state one hot indicator +0: secure state is not in secure state +1: secure state is in secure state + 5 + 1 + read-write + + + PMIC_INS + PMIC secure state one hot indicator +0: secure state is not in inspect state +1: secure state is in inspect state + 4 + 1 + read-write + + + + + SECURE_STATE_CONFIG + secure state configuration + 0x4 + 32 + 0x00000000 + 0x00000009 + + + LOCK + Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset +0: not locked, register can be modified +1: register locked, write access to the register is ignored + 3 + 1 + read-write + + + ALLOW_RESTART + allow secure state restart from fail state +0: restart is not allowed, only hardware reset can recover secure state +1: software is allowed to switch to inspect state from fail state + 0 + 1 + read-write + + + + + VIOLATION_CONFIG + Security violation config + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 0 + 15 + read-write + + + + + ESCALATE_CONFIG + Escalate behavior on security event + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 0 + 15 + read-write + + + + + EVENT + Event and escalate status + 0x10 + 32 + 0x00000000 + 0xFFFF000C + + + EVENT + local event statue, each bit represents one security event + 16 + 16 + read-only + + + PMIC_ESC_NSC + PMIC is escalating non-secure event + 3 + 1 + read-only + + + PMIC_ESC_SEC + PMIC is escalting secure event + 2 + 1 + read-only + + + + + LIFECYCLE + Lifecycle + 0x14 + 32 + 0x00000000 + 0x000000FF + + + LIFECYCLE + lifecycle status, +bit7: lifecycle_debate, +bit6: lifecycle_scribe, +bit5: lifecycle_no_ret, +bit4: lifecycle_return, +bit3: lifecycle_secure, +bit2: lifecycle_nonsec, +bit1: lifecycle_create, +bit0: lifecycle_unknow + 0 + 8 + read-only + + + + + + + MON + MON + MON + 0xf3048000 + + 0x0 + 0x48 + registers + + + + 4 + 0x8 + glitch0,glitch1,clock0,clock1 + MONITOR[%s] + no description available + 0x0 + + CONTROL + Glitch and clock monitor control + 0x0 + 32 + 0x00000000 + 0x00000011 + + + ACTIVE + select glitch works in active mode or passve mode. +0: passive mode, depends on power glitch destroy DFF value +1: active mode, check glitch by DFF chain + 4 + 1 + read-write + + + ENABLE + enable glitch detector +0: detector disabled +1: detector enabled + 0 + 1 + read-write + + + + + STATUS + Glitch and clock monitor status + 0x4 + 32 + 0x00000000 + 0x00000001 + + + FLAG + flag for glitch detected, write 1 to clear this flag +0: glitch not detected +1: glitch detected + 0 + 1 + read-write + + + + + + IRQ_FLAG + No description available + 0x40 + 32 + 0x00000000 + 0x0000000F + + + FLAG + interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag +0: no monitor interrupt +1: monitor interrupt happened + 0 + 4 + read-write + + + + + IRQ_ENABLE + No description available + 0x44 + 32 + 0x00000000 + 0x0000000F + + + ENABLE + interrupt enable, each bit represents for one monitor +0: monitor interrupt disabled +1: monitor interrupt enabled + 0 + 4 + read-write + + + + + + + OTP + OTP + OTP + 0xf3050000 + + 0x0 + 0xc08 + registers + + + + 128 + 0x4 + SHADOW000,SHADOW001,SHADOW002,SHADOW003,SHADOW004,SHADOW005,SHADOW006,SHADOW007,SHADOW008,SHADOW009,SHADOW010,SHADOW011,SHADOW012,SHADOW013,SHADOW014,SHADOW015,SHADOW016,SHADOW017,SHADOW018,SHADOW019,SHADOW020,SHADOW021,SHADOW022,SHADOW023,SHADOW024,SHADOW025,SHADOW026,SHADOW027,SHADOW028,SHADOW029,SHADOW030,SHADOW031,SHADOW032,SHADOW033,SHADOW034,SHADOW035,SHADOW036,SHADOW037,SHADOW038,SHADOW039,SHADOW040,SHADOW041,SHADOW042,SHADOW043,SHADOW044,SHADOW045,SHADOW046,SHADOW047,SHADOW048,SHADOW049,SHADOW050,SHADOW051,SHADOW052,SHADOW053,SHADOW054,SHADOW055,SHADOW056,SHADOW057,SHADOW058,SHADOW059,SHADOW060,SHADOW061,SHADOW062,SHADOW063,SHADOW064,SHADOW065,SHADOW066,SHADOW067,SHADOW068,SHADOW069,SHADOW070,SHADOW071,SHADOW072,SHADOW073,SHADOW074,SHADOW075,SHADOW076,SHADOW077,SHADOW078,SHADOW079,SHADOW080,SHADOW081,SHADOW082,SHADOW083,SHADOW084,SHADOW085,SHADOW086,SHADOW087,SHADOW088,SHADOW089,SHADOW090,SHADOW091,SHADOW092,SHADOW093,SHADOW094,SHADOW095,SHADOW096,SHADOW097,SHADOW098,SHADOW099,SHADOW100,SHADOW101,SHADOW102,SHADOW103,SHADOW104,SHADOW105,SHADOW106,SHADOW107,SHADOW108,SHADOW109,SHADOW110,SHADOW111,SHADOW112,SHADOW113,SHADOW114,SHADOW115,SHADOW116,SHADOW117,SHADOW118,SHADOW119,SHADOW120,SHADOW121,SHADOW122,SHADOW123,SHADOW124,SHADOW125,SHADOW126,SHADOW127 + SHADOW[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + 8 + 0x4 + LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 + SHADOW_LOCK[%s] + no description available + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + 128 + 0x4 + FUSE000,FUSE001,FUSE002,FUSE003,FUSE004,FUSE005,FUSE006,FUSE007,FUSE008,FUSE009,FUSE010,FUSE011,FUSE012,FUSE013,FUSE014,FUSE015,FUSE016,FUSE017,FUSE018,FUSE019,FUSE020,FUSE021,FUSE022,FUSE023,FUSE024,FUSE025,FUSE026,FUSE027,FUSE028,FUSE029,FUSE030,FUSE031,FUSE032,FUSE033,FUSE034,FUSE035,FUSE036,FUSE037,FUSE038,FUSE039,FUSE040,FUSE041,FUSE042,FUSE043,FUSE044,FUSE045,FUSE046,FUSE047,FUSE048,FUSE049,FUSE050,FUSE051,FUSE052,FUSE053,FUSE054,FUSE055,FUSE056,FUSE057,FUSE058,FUSE059,FUSE060,FUSE061,FUSE062,FUSE063,FUSE064,FUSE065,FUSE066,FUSE067,FUSE068,FUSE069,FUSE070,FUSE071,FUSE072,FUSE073,FUSE074,FUSE075,FUSE076,FUSE077,FUSE078,FUSE079,FUSE080,FUSE081,FUSE082,FUSE083,FUSE084,FUSE085,FUSE086,FUSE087,FUSE088,FUSE089,FUSE090,FUSE091,FUSE092,FUSE093,FUSE094,FUSE095,FUSE096,FUSE097,FUSE098,FUSE099,FUSE100,FUSE101,FUSE102,FUSE103,FUSE104,FUSE105,FUSE106,FUSE107,FUSE108,FUSE109,FUSE110,FUSE111,FUSE112,FUSE113,FUSE114,FUSE115,FUSE116,FUSE117,FUSE118,FUSE119,FUSE120,FUSE121,FUSE122,FUSE123,FUSE124,FUSE125,FUSE126,FUSE127 + FUSE[%s] + no description available + 0x400 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + 8 + 0x4 + LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 + FUSE_LOCK[%s] + no description available + 0x600 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + UNLOCK + UNLOCK + 0x800 + 32 + 0x00000000 + 0xFFFFFFFF + + + UNLOCK + unlock word for fuse array operation +write "OPEN" to unlock fuse array, write any other value will lock write to fuse. +Please make sure 24M crystal is running and 2.5V LDO working properly + 0 + 32 + read-write + + + + + DATA + DATA + 0x804 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + data register for non-blocking access +this register hold dat read from fuse array or data to by programmed to fuse array + 0 + 32 + read-write + + + + + ADDR + ADDR + 0x808 + 32 + 0x00000000 + 0x0000007F + + + ADDR + word address to be read or write + 0 + 7 + read-write + + + + + CMD + CMD + 0x80c + 32 + 0x00000000 + 0xFFFFFFFF + + + CMD + command to access fure array +"BLOW" will update fuse word at ADDR to value hold in DATA +"READ" will fetch fuse value in at ADDR to DATA register + 0 + 32 + read-write + + + + + LOAD_REQ + LOAD Request + 0xa00 + 32 + 0x00000007 + 0x0000000F + + + REQUEST + reload request for 4 regions +bit0: region0 +bit1: region1 +bit2: region2 +bit3: region3 + 0 + 4 + read-write + + + + + LOAD_COMP + LOAD complete + 0xa04 + 32 + 0x00000007 + 0x0000000F + + + COMPLETE + reload complete sign for 4 regions +bit0: region 0 +bit1: region1 +bit2: region2 +bit3: region3 + 0 + 4 + read-write + + + + + 4 + 0x4 + LOAD_REGION0,LOAD_REGION1,LOAD_REGION2,LOAD_REGION3 + REGION[%s] + no description available + 0xa20 + 32 + 0x00000800 + 0x00007F7F + + + STOP + stop address of load region, fuse word at end address will NOT be reloaded +region0: fixed at 8 +region1: fixed at 16 +region2: fixed at 0, +region3: usrer configurable + 8 + 7 + read-write + + + START + start address of load region, fuse word at start address will be reloaded +region0: fixed at 0 +region1: fixed at 8 +region2: fixed at 16, +region3: usrer configurable + 0 + 7 + read-write + + + + + INT_FLAG + interrupt flag + 0xc00 + 32 + 0x00000000 + 0x00000007 + + + WRITE + fuse write flag, write 1 to clear +0: fuse is not written or writing +1: value in DATA register is programmed into fuse + 2 + 1 + read-write + + + READ + fuse read flag, write 1 to clear +0: fuse is not read or reading +1: fuse value is put in DATA register + 1 + 1 + read-write + + + LOAD + fuse load flag, write 1 to clear +0: fuse is not loaded or loading +1: fuse loaded + 0 + 1 + read-write + + + + + INT_EN + interrupt enable + 0xc04 + 32 + 0x00000000 + 0x00000007 + + + WRITE + fuse write interrupt enable +0: fuse write interrupt is not enable +1: fuse write interrupt is enable + 2 + 1 + read-write + + + READ + fuse read interrupt enable +0: fuse read interrupt is not enable +1: fuse read interrupt is enable + 1 + 1 + read-write + + + LOAD + fuse load interrupt enable +0: fuse load interrupt is not enable +1: fuse load interrupt is enable + 0 + 1 + read-write + + + + + + + KEYM + KEYM + KEYM + 0xf3054000 + + 0x0 + 0x50 + registers + + + + 8 + 0x4 + SFK0,SFK1,SFK2,SFK3,SFK4,SFK5,SFK6,SFK7 + SOFTMKEY[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software symmetric key +key will be scambled to 4 variants for software to use, and replicable on same chip. +scramble keys are chip different, and not replicable on different chip +must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 + 0 + 32 + read-write + + + + + 8 + 0x4 + SPK0,SPK1,SPK2,SPK3,SPK4,SPK5,SPK6,SPK7 + SOFTPKEY[%s] + no description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software asymmetric key +key is derived from scrambles of fuse private key, software input key, SRK, and system security status. +This key os read once, sencondary read will read out 0 + 0 + 32 + read-write + + + + + SEC_KEY_CTL + secure key generation + 0x40 + 32 + 0x00000000 + 0x80011117 + + + LOCK_SEC_CTL + block secure state key setting being changed + 31 + 1 + read-write + + + SK_VAL + session key valid +0: session key is all 0's and not usable +1: session key is valid + 16 + 1 + read-only + + + SMK_SEL + software symmetric key selection +0: use origin value in software symmetric key +1: use scramble version of software symmetric key + 12 + 1 + read-write + + + ZMK_SEL + batt symmetric key selection +0: use scramble version of software symmetric key +1: use origin value in software symmetric key + 8 + 1 + read-write + + + FMK_SEL + fuse symmetric key selection +0: use scramble version of fuse symmetric key +1: use alnertave scramble of fuse symmetric key + 4 + 1 + read-write + + + KEY_SEL + secure symmtric key synthesize setting, key is a XOR of following +bit0: fuse mk, 0: not selected, 1:selected +bit1: zmk from batt, 0: not selected, 1:selected +bit2: software key 0: not selected, 1:selected + 0 + 3 + read-write + + + + + NSC_KEY_CTL + non-secure key generation + 0x44 + 32 + 0x00000000 + 0x80011117 + + + LOCK_NSC_CTL + block non-secure state key setting being changed + 31 + 1 + read-write + + + SK_VAL + session key valid +0: session key is all 0's and not usable +1: session key is valid + 16 + 1 + read-only + + + SMK_SEL + software symmetric key selection +0: use scramble version of software symmetric key +1: use origin value in software symmetric key + 12 + 1 + read-write + + + ZMK_SEL + batt symmetric key selection +0: use scramble version of software symmetric key +1: use origin value in software symmetric key + 8 + 1 + read-write + + + FMK_SEL + fuse symmetric key selection +0: use scramble version of fuse symmetric key +1: use origin value in fuse symmetric key + 4 + 1 + read-write + + + KEY_SEL + non-secure symmtric key synthesize setting, key is a XOR of following +bit0: fuse mk, 0: not selected, 1:selected +bit1: zmk from batt, 0: not selected, 1:selected +bit2: software key 0: not selected, 1:selected + 0 + 3 + read-write + + + + + RNG + Random number interface behavior + 0x48 + 32 + 0x00000000 + 0x00010001 + + + BLOCK_RNG_XOR + block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset +0: RNG_XOR can be changed by software +1: RNG_XOR ignore software change from software + 16 + 1 + read-write + + + RNG_XOR + control how SFK is accepted from random number generator +0: SFK value replaced by random number input +1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG + 0 + 1 + read-write + + + + + READ_CONTROL + key read out control + 0x4c + 32 + 0x00000000 + 0x00010001 + + + BLOCK_PK_READ + asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset +0: key can be read out +1: key cannot be read out + 16 + 1 + read-write + + + BLOCK_SMK_READ + symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset +0: key can be read out +1: key cannot be read out + 0 + 1 + read-write + + + + + + + ADC0 + ADC0 + ADC16 + 0xf3080000 + + 0x0 + 0x1464 + registers + + + + 12 + 0x4 + trg0a,trg0b,trg0c,trg1a,trg1b,trg1c,trg2a,trg2b,trg2c,trg3a,trg3b,trg3c + CONFIG[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFF3F3F7F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interrupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interrupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interrupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + QUEUE_EN + preemption queue enable control + 6 + 1 + read-write + + + INTEN0 + interrupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + trg_dma_addr + No description available + 0x30 + 32 + 0x00000000 + 0xFFFFFFFC + + + TRG_DMA_ADDR + buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) + 2 + 30 + read-write + + + + + trg_sw_sta + No description available + 0x34 + 32 + 0x00000000 + 0x0000001F + + + TRG_SW_STA + SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it. + 4 + 1 + read-write + + + TRIG_SW_INDEX + which trigger for the SW trigger +0 for trig0a, 1 for trig0b… +3 for trig1a, …11 for trig3c + 0 + 4 + read-write + + + + + 16 + 0x4 + chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 + BUS_RESULT[%s] + no description available + 0x400 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + buf_cfg0 + No description available + 0x500 + 32 + 0x00000000 + 0x00000003 + + + BUS_MODE_EN + bus mode enable + 1 + 1 + read-write + + + WAIT_DIS + set to disable read waiting, get result immediately but maybe not current conversion result. + 0 + 1 + read-write + + + + + seq_cfg0 + No description available + 0x800 + 32 + 0x00000000 + 0x80000F1F + + + CYCLE + current dma write cycle bit + 31 + 1 + read-only + + + SEQ_LEN + sequence queue length, 0 for one, 0xF for 16 + 8 + 4 + read-write + + + RESTART_EN + if set together with cont_en, HW will continue process the whole queue after trigger once. +If cont_en is 0, this bit is not used + 4 + 1 + read-write + + + CONT_EN + if set, HW will continue process the queue till end(seq_len) after trigger once + 3 + 1 + read-write + + + SW_TRIG + SW trigger, pulse signal, cleared by HW one cycle later + 2 + 1 + write-only + + + SW_TRIG_EN + set to enable SW trigger + 1 + 1 + read-write + + + HW_TRIG_EN + set to enable external HW trigger, only trigger on posedge + 0 + 1 + read-write + + + + + seq_dma_addr + No description available + 0x804 + 32 + 0x00000000 + 0xFFFFFFFC + + + TAR_ADDR + dma target address, should be 4-byte aligned + 2 + 30 + read-write + + + + + seq_wr_addr + No description available + 0x808 + 32 + 0x00000000 + 0x00FFFFFF + + + SEQ_WR_POINTER + HW update this field after each dma write, it indicate the next dma write pointer. +dma write address is (tar_addr+seq_wr_pointer)*4 + 0 + 24 + read-only + + + + + seq_dma_cfg + No description available + 0x80c + 32 + 0x00000000 + 0x0FFF3FFF + + + STOP_POS + if stop_en is set, SW is responsible to update this field to the next read point, HW should not write data to this point since it's not read out by SW yet + 16 + 12 + read-write + + + DMA_RST + set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. +SW should clear all cycle bit in buffer to 0 before clear dma_rst + 13 + 1 + read-write + + + STOP_EN + set to stop dma if reach the stop_pos + 12 + 1 + read-write + + + BUF_LEN + dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 +0 for 4byte; +0xFFF for 16kbyte. + 0 + 12 + read-write + + + + + 16 + 0x4 + cfg0,cfg1,cfg2,cfg3,cfg4,cfg5,cfg6,cfg7,cfg8,cfg9,cfg10,cfg11,cfg12,cfg13,cfg14,cfg15 + SEQ_QUE[%s] + no description available + 0x810 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + seq_high_cfg + No description available + 0x850 + 32 + 0x00000000 + 0x00FFFFFF + + + STOP_POS_HIGH + No description available + 12 + 12 + read-write + + + BUF_LEN_HIGH + No description available + 0 + 12 + read-write + + + + + 16 + 0x10 + chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 + PRD_CFG[%s] + no description available + 0xc00 + + prd_cfg + No description available + 0x0 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + prd_thshd_cfg + No description available + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + prd_result + No description available + 0x8 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + + 16 + 0x4 + chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 + SAMPLE_CFG[%s] + no description available + 0x1000 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + conv_cfg1 + No description available + 0x1104 + 32 + 0x00000000 + 0x000001FF + + + CONVERT_CLOCK_NUMBER + convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider); +user can use small value to get faster conversion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. +Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC conversion(plus sample) need 25 cycles(50MHz). + 4 + 5 + read-write + + + CLOCK_DIVIDER + clock_period, N half clock cycle per half adc cycle +0 for same adc_clk and bus_clk, +1 for 1:2, +2 for 1:3, +... +15 for 1:16 +Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk + 0 + 4 + read-write + + + + + adc_cfg0 + No description available + 0x1108 + 32 + 0x00000000 + 0xA0000001 + + + SEL_SYNC_AHB + set to 1 will enable sync AHB bus, to get better bus performance. +Adc_clk must to be set to same as bus clock at this mode + 31 + 1 + read-write + + + ADC_AHB_EN + set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; + 29 + 1 + read-write + + + PORT3_REALTIME + set to enable trg queue stop other queues + 0 + 1 + read-write + + + + + int_sts + No description available + 0x1110 + 32 + 0x00000000 + 0xFFE0FFFF + + + TRIG_CMPT + interrupt for one trigger conversion complete if enabled + 31 + 1 + read-write + + + TRIG_SW_CFLCT + No description available + 30 + 1 + read-write + + + TRIG_HW_CFLCT + No description available + 29 + 1 + read-write + + + READ_CFLCT + read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel + 28 + 1 + read-write + + + SEQ_SW_CFLCT + sequence queue conflict interrupt, set if HW or SW trigger received during conversion + 27 + 1 + read-write + + + SEQ_HW_CFLCT + No description available + 26 + 1 + read-write + + + SEQ_DMAABT + dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set + 25 + 1 + read-write + + + SEQ_CMPT + the whole sequence complete interrupt + 24 + 1 + read-write + + + SEQ_CVC + one conversion complete in seq_queue if related seq_int_en is set + 23 + 1 + read-write + + + DMA_FIFO_FULL + DMA fifo full interrupt, user need to check clock frequency if it's set. + 22 + 1 + read-write + + + AHB_ERR + set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr + 21 + 1 + read-write + + + WDOG + set if one chanel watch dog event triggered + 0 + 16 + read-write + + + + + int_en + No description available + 0x1114 + 32 + 0x00000000 + 0xFFE0FFFF + + + TRIG_CMPT + interrupt for one trigger conversion complete if enabled + 31 + 1 + read-write + + + TRIG_SW_CFLCT + No description available + 30 + 1 + read-write + + + TRIG_HW_CFLCT + No description available + 29 + 1 + read-write + + + READ_CFLCT + read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel + 28 + 1 + read-write + + + SEQ_SW_CFLCT + sequence queue conflict interrupt, set if HW or SW trigger received during conversion + 27 + 1 + read-write + + + SEQ_HW_CFLCT + No description available + 26 + 1 + read-write + + + SEQ_DMAABT + dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set + 25 + 1 + read-write + + + SEQ_CMPT + the whole sequence complete interrupt + 24 + 1 + read-write + + + SEQ_CVC + one conversion complete in seq_queue if related seq_int_en is set + 23 + 1 + read-write + + + DMA_FIFO_FULL + DMA fifo full interrupt, user need to check clock frequency if it's set. + 22 + 1 + read-write + + + AHB_ERR + set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr + 21 + 1 + read-write + + + WDOG + set if one chanel watch dog event triggered + 0 + 16 + read-write + + + + + ana_ctrl0 + No description available + 0x1200 + 32 + 0x00000000 + 0x80001004 + + + MOTO_EN + "set to enable moto_soc and moto_valid. +Should use AHB clock for adc, this bit can be used avoid async output" + 31 + 1 + read-write + + + ADC_CLK_ON + set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. +MUST set clock_period to 0 or 1 for adc16 reg access + 12 + 1 + read-write + + + STARTCAL + set to start the offset calibration cycle (Active H). user need to clear it after setting it. + 2 + 1 + read-write + + + + + ana_status + No description available + 0x1210 + 32 + 0x00000000 + 0x00000080 + + + CALON + Indicates if the ADC is in calibration mode (Active H). + 7 + 1 + read-write + + + + + 34 + 0x2 + adc16_para00,adc16_para01,adc16_para02,adc16_para03,adc16_para04,adc16_para05,adc16_para06,adc16_para07,adc16_para08,adc16_para09,adc16_para10,adc16_para11,adc16_para12,adc16_para13,adc16_para14,adc16_para15,adc16_para16,adc16_para17,adc16_para18,adc16_para19,adc16_para20,adc16_para21,adc16_para22,adc16_para23,adc16_para24,adc16_para25,adc16_para26,adc16_para27,adc16_para28,adc16_para29,adc16_para30,adc16_para31,adc16_para32,adc16_para33 + ADC16_PARAMS[%s] + no description available + 0x1400 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description available + 0 + 16 + read-write + + + + + adc16_config0 + No description available + 0x1444 + 32 + 0x00000000 + 0x01F07FFF + + + REG_EN + set to enable regulator + 24 + 1 + read-write + + + BANDGAP_EN + set to enable bandgap. user should set reg_en and bandgap_en before use adc16. + 23 + 1 + read-write + + + CAL_AVG_CFG + for average the calibration result. +0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; +4- 16 loops; 5-32 loops; others reserved + 20 + 3 + read-write + + + PREEMPT_EN + set to enable preemption feature + 14 + 1 + read-write + + + CONV_PARAM + conversion parameter + 0 + 14 + read-write + + + + + adc16_config1 + No description available + 0x1460 + 32 + 0x00000000 + 0x00001F00 + + + COV_END_CNT + used for faster conversion, user can change it to get higher convert speed(but less accuracy). +should set to (21-convert_clock_number+1). + 8 + 5 + read-write + + + + + + + ACMP + ACMP + ACMP + 0xf30b0000 + + 0x0 + 0x80 + registers + + + + 4 + 0x20 + chn0,chn1,chn2,chn3 + CHANNEL[%s] + no description available + 0x0 + + cfg + Configure Register + 0x0 + 32 + 0x00000000 + 0xFF7FFFFF + + + HYST + This bitfield configure the comparator hysteresis. +00: Hysteresis level 0 +01: Hysteresis level 1 +10: Hysteresis level 2 +11: Hysteresis level 3 + 30 + 2 + read-write + + + DACEN + This bit enable the comparator internal DAC +0: DAC disabled +1: DAC enabled + 29 + 1 + read-write + + + HPMODE + This bit enable the comparator high performance mode. +0: HP mode disabled +1: HP mode enabled + 28 + 1 + read-write + + + CMPEN + This bit enable the comparator. +0: ACMP disabled +1: ACMP enabled + 27 + 1 + read-write + + + MINSEL + PIN select, from pad_ai_acmp[7:1] and dac_out + 24 + 3 + read-write + + + PINSEL + MIN select, from pad_ai_acmp[7:1] and dac_out + 20 + 3 + read-write + + + CMPOEN + This bit enable the comparator output on pad. +0: ACMP output disabled +1: ACMP output enabled + 19 + 1 + read-write + + + FLTBYPS + This bit bypass the comparator output digital filter. +0: The ACMP output need pass digital filter +1: The ACMP output digital filter is bypassed. + 18 + 1 + read-write + + + WINEN + This bit enable the comparator window mode. +0: Window mode is disabled +1: Window mode is enabled + 17 + 1 + read-write + + + OPOL + The output polarity control bit. +0: The ACMP output remain un-changed. +1: The ACMP output is inverted. + 16 + 1 + read-write + + + FLTMODE + This bitfield define the ACMP output digital filter mode: +000-bypass +100-change immediately; +101-change after filter; +110-stalbe low; +111-stable high + 13 + 3 + read-write + + + SYNCEN + This bit enable the comparator output synchronization. +0: ACMP output not synchronized with ACMP clock. +1: ACMP output synchronized with ACMP clock. + 12 + 1 + read-write + + + FLTLEN + This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. + 0 + 12 + read-write + + + + + daccfg + DAC configure register + 0x4 + 32 + 0x00000000 + 0x000000FF + + + DACCFG + 8bit DAC digital value output to analog block + 0 + 8 + read-write + + + + + sr + Status register + 0x10 + 32 + 0x00000000 + 0x00000003 + + + FEDGF + Output falling edge flag. Write 1 to clear this flag. + 1 + 1 + read-write + + + REDGF + Output rising edge flag. Write 1 to clear this flag. + 0 + 1 + read-write + + + + + irqen + Interrupt request enable register + 0x14 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag interrupt enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag interrupt enable bit. + 0 + 1 + read-write + + + + + dmaen + DMA request enable register + 0x18 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag DMA request enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag DMA request enable bit. + 0 + 1 + read-write + + + + + + + + SYSCTL + SYSCTL + SYSCTL + 0xf4000000 + + 0x0 + 0x2c00 + registers + + + + 105 + 0x4 + cpu0,cpx0,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,rsv14,rsv15,rsv16,rsv17,rsv18,rsv19,rsv20,pow_cpu0,rst_soc,rst_cpu0,rsv24,rsv25,rsv26,rsv27,rsv28,rsv29,rsv30,rsv31,clk_src_xtal,clk_src_pll0,clk_src_clk0_pll0,clk_src_clk1_pll0,clk_src_clk2_pll0,clk_src_pll1,clk_src_clk0_pll1,clk_src_clk1_pll1,clk_src_clk2_pll1,clk_src_clk3_pll1,clk_src_pll0_ref,clk_src_pll1_ref,rsv44,rsv45,rsv46,rsv47,rsv48,rsv49,rsv50,rsv51,rsv52,rsv53,rsv54,rsv55,rsv56,rsv57,rsv58,rsv59,rsv60,rsv61,rsv62,rsv63,clk_top_cpu0,clk_top_mct0,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,rsv70,rsv71,rsv72,rsv73,clk_top_tmr0,clk_top_tmr1,clk_top_tmr2,clk_top_tmr3,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_urt0,clk_top_urt1,clk_top_urt2,clk_top_urt3,clk_top_urt4,clk_top_urt5,clk_top_urt6,clk_top_urt7,clk_top_xpi0,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_ana3,clk_top_ref0,clk_top_ref1,clk_top_adc0,clk_top_adc1,clk_top_dac0,clk_top_dac1,rsv105,rsv106,rsv107,rsv108,rsv109,rsv110,rsv111,rsv112,rsv113,rsv114,rsv115,rsv116,rsv117,rsv118,rsv119,rsv120,rsv121,rsv122,rsv123,rsv124,rsv125,rsv126,rsv127,rsv128,rsv129,rsv130,rsv131,rsv132,rsv133,rsv134,rsv135,rsv136,rsv137,rsv138,rsv139,rsv140,rsv141,rsv142,rsv143,rsv144,rsv145,rsv146,rsv147,rsv148,rsv149,rsv150,rsv151,rsv152,rsv153,rsv154,rsv155,rsv156,rsv157,rsv158,rsv159,rsv160,rsv161,rsv162,rsv163,rsv164,rsv165,rsv166,rsv167,rsv168,rsv169,rsv170,rsv171,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,ahb0,lmm0,mct0,rom0,can0,can1,can2,can3,ptpc,rsv265,rsv266,rsv267,rsv268,tmr0,tmr1,tmr2,tmr3,i2c0,i2c1,i2c2,i2c3,spi0,spi1,spi2,spi3,urt0,urt1,urt2,urt3,urt4,urt5,urt6,urt7,wdg0,wdg1,mbx0,tsns,crc0,adc0,adc1,dac0,dac1,acmp,opa0,opa1,mot0,rng0,sdp0,kman,gpio,hdma,xpi0,usb0,ref0,ref1 + RESOURCE[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + 2 + 0x10 + link0,link1 + GROUP0[%s] + no description available + 0x800 + + VALUE + Group setting + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + SET + Group setting + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: add periphera into this group，periphera is needed + 0 + 32 + read-write + + + + + CLEAR + Group setting + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: delete periphera in this group，periphera is not needed + 0 + 32 + read-write + + + + + TOGGLE + Group setting + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: toggle the result that whether periphera is needed before + 0 + 32 + read-write + + + + + + 1 + 0x10 + cpu0 + AFFILIATE[%s] + no description available + 0x900 + + VALUE + Affiliate of Group + 0x0 + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0, each bit represents a group +bit0: cpu0 depends on group0 +bit1: cpu0 depends on group1 +bit2: cpu0 depends on group2 +bit3: cpu0 depends on group3 + 0 + 4 + read-write + + + + + SET + Affiliate of Group + 0x4 + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0，each bit represents a group +0: no effect +1: the group is assigned to CPU0 + 0 + 4 + read-write + + + + + CLEAR + Affiliate of Group + 0x8 + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0, each bit represents a group +0: no effect +1: the group is not assigned to CPU0 + 0 + 4 + read-write + + + + + TOGGLE + Affiliate of Group + 0xc + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0, each bit represents a group +0: no effect +1: toggle the result that whether the group is assigned to CPU0 before + 0 + 4 + read-write + + + + + + 1 + 0x10 + cpu0 + RETENTION[%s] + no description available + 0x920 + + VALUE + Retention Control + 0x0 + 32 + 0x00000000 + 0x00007FFF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +bit00: soc_mem is kept on while cpu0 stop +bit01: soc_ctx is kept on while cpu0 stop +bit02: cpu0_mem is kept on while cpu0 stop +bit03: cpu0_ctx is kept on while cpu0 stop +bit04: xtal_hold is kept on while cpu0 stop +bit05: pll0_hold is kept on while cpu0 stop +bit06: pll1_hold is kept on while cpu0 stop + 0 + 15 + read-write + + + + + SET + Retention Control + 0x4 + 32 + 0x00000000 + 0x00007FFF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +0: no effect +1: keep + 0 + 15 + read-write + + + + + CLEAR + Retention Control + 0x8 + 32 + 0x00000000 + 0x00007FFF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +0: no effect +1: no keep + 0 + 15 + read-write + + + + + TOGGLE + Retention Control + 0xc + 32 + 0x00000000 + 0x00007FFF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +0: no effect +1: toggle the result that whether the resource is kept on while CPU0 stop before + 0 + 15 + read-write + + + + + + 1 + 0x14 + cpu0 + POWER[%s] + no description available + 0x1000 + + status + Power Setting + 0x0 + 32 + 0x80000000 + 0xC0031100 + + + FLAG + flag represents power cycle happened from last clear of this bit +0: power domain did not edurance power cycle since last clear of this bit +1: power domain enduranced power cycle since last clear of this bit + 31 + 1 + read-write + + + FLAG_WAKE + flag represents wakeup power cycle happened from last clear of this bit +0: power domain did not edurance wakeup power cycle since last clear of this bit +1: power domain enduranced wakeup power cycle since last clear of this bit + 30 + 1 + read-write + + + MEM_RET_N + memory info retention control signal +0: memory enter retention mode +1: memory exit retention mode + 17 + 1 + read-only + + + MEM_RET_P + memory info retention control signal +0: memory not enterexitretention mode +1: memory enter retention mode + 16 + 1 + read-only + + + LF_DISABLE + low fanout power switch disable +0: low fanout power switches are turned on +1: low fanout power switches are truned off + 12 + 1 + read-only + + + LF_ACK + low fanout power switch feedback +0: low fanout power switches are turned on +1: low fanout power switches are truned off + 8 + 1 + read-only + + + + + lf_wait + Power Setting + 0x4 + 32 + 0x000000FF + 0x000FFFFF + + + WAIT + wait time for low fan out power switch turn on, default value is 255 +0: 0 clock cycle +1: 1 clock cycles +. . . +clock cycles count on 24MHz + 0 + 20 + read-write + + + + + off_wait + Power Setting + 0xc + 32 + 0x0000000F + 0x000FFFFF + + + WAIT + wait time for power switch turn off, default value is 15 +0: 0 clock cycle +1: 1 clock cycles +. . . +clock cycles count on 24MHz + 0 + 20 + read-write + + + + + ret_wait + Power Setting + 0x10 + 32 + 0x0000000F + 0x000FFFFF + + + WAIT + wait time for memory retention mode transition, default value is 15 +0: 0 clock cycle +1: 1 clock cycles +. . . +clock cycles count on 24MHz + 0 + 20 + read-write + + + + + + 2 + 0x10 + soc,cpu0 + RESET[%s] + no description available + 0x1400 + + control + Reset Setting + 0x0 + 32 + 0x80000000 + 0xC0000011 + + + FLAG + flag represents reset happened from last clear of this bit +0: domain did not edurance reset cycle since last clear of this bit +1: domain enduranced reset cycle since last clear of this bit + 31 + 1 + read-write + + + FLAG_WAKE + flag represents wakeup reset happened from last clear of this bit +0: domain did not edurance wakeup reset cycle since last clear of this bit +1: domain enduranced wakeup reset cycle since last clear of this bit + 30 + 1 + read-write + + + HOLD + perform reset and hold in reset, until ths bit cleared by software +0: reset is released for function +1: reset is assert and hold + 4 + 1 + read-write + + + RESET + perform reset and release imediately +0: reset is released +1 reset is asserted and will release automatically + 0 + 1 + read-write + + + + + config + Reset Setting + 0x4 + 32 + 0x00402003 + 0x00FFFFFF + + + PRE_WAIT + wait cycle numbers before assert reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 16 + 8 + read-write + + + RSTCLK_NUM + reset clock number(must be even number) +0: 0 cycle +1: 0 cycles +2: 2 cycles +3: 2 cycles +. . . +Note, clock cycle is base on 24M + 8 + 8 + read-write + + + POST_WAIT + time guard band for reset release +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 8 + read-write + + + + + counter + Reset Setting + 0xc + 32 + 0x00000000 + 0x000FFFFF + + + COUNTER + self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 20 + read-write + + + + + + 1 + 0x4 + clk_top_cpu0 + CLOCK_CPU[%s] + no description available + 0x1800 + 32 + 0x00000000 + 0xD00F07FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + SUB0_DIV + ahb bus divider, the bus clock is generated by cpu_clock/div +0: divider by 1 +1: divider by 2 +… + 16 + 4 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll1_clk2 +7:pll1_clk3 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + 32 + 0x4 + clk_top_mct0,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,rsv5,rsv6,rsv7,rsv8,clk_top_tmr0,clk_top_tmr1,clk_top_tmr2,clk_top_tmr3,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_urt0,clk_top_urt1,clk_top_urt2,clk_top_urt3,clk_top_urt4,clk_top_urt5,clk_top_urt6,clk_top_urt7,clk_top_xpi0,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_ana3,clk_top_ref0,clk_top_ref1 + CLOCK[%s] + no description available + 0x1804 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll1_clk2 +7:pll1_clk3 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + 2 + 0x4 + clk_top_adc0,clk_top_adc1 + ADCCLK[%s] + no description available + 0x1c00 + 32 + 0x00000000 + 0xD0000100 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux +0: ahb0 clock N +1: ana clock + 8 + 1 + read-write + + + + + 2 + 0x4 + clk_top_dac0,clk_top_dac1 + DACCLK[%s] + no description available + 0x1c08 + 32 + 0x00000000 + 0xD0000100 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux +0: ahb0 clock N +1: ana clock + 8 + 1 + read-write + + + + + global00 + Clock senario + 0x2000 + 32 + 0x00000000 + 0x000000FF + + + MUX + global clock override request +bit0: override to preset0 +bit1: override to preset1 +bit2: override to preset2 +bit3: override to preset3 +bit4: override to preset4 +bit5: override to preset5 +bit6: override to preset6 +bit7: override to preset7 + 0 + 8 + read-write + + + + + 4 + 0x20 + slice0,slice1,slice2,slice3 + MONITOR[%s] + no description available + 0x2400 + + control + Clock measure and monitor control + 0x0 + 32 + 0x00000000 + 0x89FFD7FF + + + VALID + result is ready for read +0: not ready +1: result is ready + 31 + 1 + read-write + + + DIV_BUSY + divider is applying new setting + 27 + 1 + read-only + + + OUTEN + enable clock output + 24 + 1 + read-write + + + DIV + output divider + 16 + 8 + read-write + + + HIGH + clock frequency higher than upper limit + 15 + 1 + read-write + + + LOW + clock frequency lower than lower limit + 14 + 1 + read-write + + + START + start measurement + 12 + 1 + read-write + + + MODE + work mode, +0: register value will be compared to measurement +1: upper and lower value will be recordered in register + 10 + 1 + read-write + + + ACCURACY + measurement accuracy, +0: resolution is 1kHz +1: resolution is 1Hz + 9 + 1 + read-write + + + REFERENCE + reference clock selection, +0: 32k +1: 24M + 8 + 1 + read-write + + + SELECTION + clock measurement selection + 0 + 8 + read-write + + + + + current + Clock measure result + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + self updating measure result + 0 + 32 + read-only + + + + + low_limit + Clock lower limit + 0x8 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + FREQUENCY + lower frequency + 0 + 32 + read-write + + + + + high_limit + Clock upper limit + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + upper frequency + 0 + 32 + read-write + + + + + + 1 + 0x400 + cpu0 + CPU[%s] + no description available + 0x2800 + + LP + CPU0 LP control + 0x0 + 32 + 0x00001000 + 0xFF013703 + + + WAKE_CNT + CPU0 wake up counter, counter satuated at 255, write 0x00 to clear + 24 + 8 + read-write + + + HALT + halt request for CPU0, +0: CPU0 will start to execute after reset or receive wakeup request +1: CPU0 will not start after reset, or wakeup after WFI + 16 + 1 + read-write + + + WAKE + CPU0 is waking up +0: CPU0 wake up not asserted +1: CPU0 wake up asserted + 13 + 1 + read-only + + + EXEC + CPU0 is executing +0: CPU0 is not executing +1: CPU0 is executing + 12 + 1 + read-only + + + WAKE_FLAG + CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit +0: CPU0 wakeup not happened +1: CPU0 wake up happened + 10 + 1 + read-write + + + SLEEP_FLAG + CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit +0: CPU0 sleep not happened +1: CPU0 sleep happened + 9 + 1 + read-write + + + RESET_FLAG + CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit +0: CPU0 reset not happened +1: CPU0 reset happened + 8 + 1 + read-write + + + MODE + Low power mode, system behavior after WFI +00: CPU clock stop after WFI +01: System enter low power mode after WFI +10: Keep running after WFI +11: reserved + 0 + 2 + read-write + + + + + LOCK + CPU0 Lock GPR + 0x4 + 32 + 0x00000000 + 0x0000FFFE + + + GPR + Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset + 2 + 14 + read-write + + + LOCK + Lock bit for CPU_LOCK + 1 + 1 + read-write + + + + + 14 + 0x4 + GPR0,GPR1,GPR2,GPR3,GPR4,GPR5,GPR6,GPR7,GPR8,GPR9,GPR10,GPR11,GPR12,GPR13 + GPR[%s] + no description available + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + 4 + 0x4 + STATUS0,STATUS1,STATUS2,STATUS3 + WAKEUP_STATUS[%s] + no description available + 0x40 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + 4 + 0x4 + ENABLE0,ENABLE1,ENABLE2,ENABLE3 + WAKEUP_ENABLE[%s] + no description available + 0x80 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + + + + IOC + IOC + IOC + 0xf4040000 + + 0x0 + 0xe40 + registers + + + + 456 + 0x8 + pa00,pa01,pa02,pa03,pa04,pa05,pa06,pa07,pa08,pa09,pa10,pa11,pa12,pa13,pa14,pa15,pa16,pa17,pa18,pa19,pa20,pa21,pa22,pa23,pa24,pa25,pa26,pa27,pa28,pa29,pa30,pa31,pb00,pb01,pb02,pb03,pb04,pb05,pb06,pb07,pb08,pb09,pb10,pb11,pb12,pb13,pb14,pb15,rsv48,rsv49,rsv50,rsv51,rsv52,rsv53,rsv54,rsv55,rsv56,rsv57,rsv58,rsv59,rsv60,rsv61,rsv62,rsv63,rsv64,rsv65,rsv66,rsv67,rsv68,rsv69,rsv70,rsv71,rsv72,rsv73,rsv74,rsv75,rsv76,rsv77,rsv78,rsv79,rsv80,rsv81,rsv82,rsv83,rsv84,rsv85,rsv86,rsv87,rsv88,rsv89,rsv90,rsv91,rsv92,rsv93,rsv94,rsv95,rsv96,rsv97,rsv98,rsv99,rsv100,rsv101,rsv102,rsv103,rsv104,rsv105,rsv106,rsv107,rsv108,rsv109,rsv110,rsv111,rsv112,rsv113,rsv114,rsv115,rsv116,rsv117,rsv118,rsv119,rsv120,rsv121,rsv122,rsv123,rsv124,rsv125,rsv126,rsv127,rsv128,rsv129,rsv130,rsv131,rsv132,rsv133,rsv134,rsv135,rsv136,rsv137,rsv138,rsv139,rsv140,rsv141,rsv142,rsv143,rsv144,rsv145,rsv146,rsv147,rsv148,rsv149,rsv150,rsv151,rsv152,rsv153,rsv154,rsv155,rsv156,rsv157,rsv158,rsv159,rsv160,rsv161,rsv162,rsv163,rsv164,rsv165,rsv166,rsv167,rsv168,rsv169,rsv170,rsv171,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,rsv256,rsv257,rsv258,rsv259,rsv260,rsv261,rsv262,rsv263,rsv264,rsv265,rsv266,rsv267,rsv268,rsv269,rsv270,rsv271,rsv272,rsv273,rsv274,rsv275,rsv276,rsv277,rsv278,rsv279,rsv280,rsv281,rsv282,rsv283,rsv284,rsv285,rsv286,rsv287,rsv288,rsv289,rsv290,rsv291,rsv292,rsv293,rsv294,rsv295,rsv296,rsv297,rsv298,rsv299,rsv300,rsv301,rsv302,rsv303,rsv304,rsv305,rsv306,rsv307,rsv308,rsv309,rsv310,rsv311,rsv312,rsv313,rsv314,rsv315,rsv316,rsv317,rsv318,rsv319,rsv320,rsv321,rsv322,rsv323,rsv324,rsv325,rsv326,rsv327,rsv328,rsv329,rsv330,rsv331,rsv332,rsv333,rsv334,rsv335,rsv336,rsv337,rsv338,rsv339,rsv340,rsv341,rsv342,rsv343,rsv344,rsv345,rsv346,rsv347,rsv348,rsv349,rsv350,rsv351,rsv352,rsv353,rsv354,rsv355,rsv356,rsv357,rsv358,rsv359,rsv360,rsv361,rsv362,rsv363,rsv364,rsv365,rsv366,rsv367,rsv368,rsv369,rsv370,rsv371,rsv372,rsv373,rsv374,rsv375,rsv376,rsv377,rsv378,rsv379,rsv380,rsv381,rsv382,rsv383,rsv384,rsv385,rsv386,rsv387,rsv388,rsv389,rsv390,rsv391,rsv392,rsv393,rsv394,rsv395,rsv396,rsv397,rsv398,rsv399,rsv400,rsv401,rsv402,rsv403,rsv404,rsv405,rsv406,rsv407,rsv408,rsv409,rsv410,rsv411,rsv412,rsv413,rsv414,rsv415,px00,px01,px02,px03,px04,px05,px06,px07,rsv424,rsv425,rsv426,rsv427,rsv428,rsv429,rsv430,rsv431,rsv432,rsv433,rsv434,rsv435,rsv436,rsv437,rsv438,rsv439,rsv440,rsv441,rsv442,rsv443,rsv444,rsv445,rsv446,rsv447,py00,py01,py02,py03,py04,py05,py06,py07 + PAD[%s] + no description available + 0x0 + + FUNC_CTL + ALT SELECT + 0x0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +... +31:ALT31 + 0 + 5 + read-write + + + + + PAD_CTL + PAD SETTINGS + 0x4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + + + + PIOC + PIOC + IOC + 0xf4118000 + + + PLLCTLV2 + PLLCTLV2 + PLLCTLV2 + 0xf40c0000 + + 0x0 + 0x200 + registers + + + + XTAL + OSC configuration + 0x0 + 32 + 0x0001FFFF + 0xB00FFFFF + + + BUSY + Busy flag +0: Oscillator is working or shutdown +1: Oscillator is changing status + 31 + 1 + read-only + + + RESPONSE + Crystal oscillator status +0: Oscillator is not stable +1: Oscillator is stable for use + 29 + 1 + read-only + + + ENABLE + Crystal oscillator enable status +0: Oscillator is off +1: Oscillator is on + 28 + 1 + read-only + + + RAMP_TIME + Rampup time of XTAL oscillator in cycles of RC24M clock +0: 0 cycle +1: 1 cycle +2: 2 cycle +1048575: 1048575 cycles + 0 + 20 + read-write + + + + + 3 + 0x80 + pll0,pll1,pll2 + PLL[%s] + no description available + 0x80 + + MFI + PLL0 multiple register + 0x0 + 32 + 0x00000010 + 0xB000007F + + + BUSY + Busy flag +0: PLL is stable or shutdown +1: PLL is changing status + 31 + 1 + read-only + + + RESPONSE + PLL status +0: PLL is not stable +1: PLL is stable for use + 29 + 1 + read-only + + + ENABLE + PLL enable status +0: PLL is off +1: PLL is on + 28 + 1 + read-only + + + MFI + loop back divider of PLL, support from 13 to 42, f=fref*(mfi + mfn/mfd) +0-15: invalid +16: divide by 16 +17: divide by17 +. . . +42: divide by 42 +43~:invalid + 0 + 7 + read-write + + + + + MFN + PLL0 fraction numerator register + 0x4 + 32 + 0x09896800 + 0x3FFFFFFF + + + MFN + Numeratorof fractional part,f=fref*(mfi + mfn/mfd). This field supports changing while running. + 0 + 30 + read-write + + + + + MFD + PLL0 fraction demoninator register + 0x8 + 32 + 0x0E4E1C00 + 0x3FFFFFFF + + + MFD + Demoninator of fraction part,f=fref*(mfi + mfn/mfd). This field should not be changed during PLL enabled. If changed, change will take efftect when PLL re-enabled. + 0 + 30 + read-write + + + + + SS_STEP + PLL0 spread spectrum step register + 0xc + 32 + 0x00000000 + 0x3FFFFFFF + + + STEP + Step of spread spectrum modulator. +This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. + 0 + 30 + read-write + + + + + SS_STOP + PLL0 spread spectrum stop register + 0x10 + 32 + 0x00000000 + 0x3FFFFFFF + + + STOP + Stop point of spread spectrum modulator +This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. + 0 + 30 + read-write + + + + + CONFIG + PLL0 confguration register + 0x14 + 32 + 0x00000000 + 0x00000101 + + + SPREAD + Enable spread spectrum function. This field supports changing during PLL running. + 8 + 1 + read-write + + + REFSEL + Select reference clock, This filed support changing while running, but application must take frequency error and jitter into consideration. And if MFN changed before reference switch, application need make sure time is enough for MFN updating. +0: XTAL24M +1: IRC24M + 0 + 1 + read-write + + + + + LOCKTIME + PLL0 lock time register + 0x18 + 32 + 0x000009C4 + 0x0000FFFF + + + LOCKTIME + Lock time of PLL in 24M clock cycles, typical value is 2500. If MFI changed during PLL startup, PLL lock time may be longer than this setting. + 0 + 16 + read-write + + + + + STEPTIME + PLL0 step time register + 0x1c + 32 + 0x000009C4 + 0x0000FFFF + + + STEPTIME + Step time for MFI on-the-fly change in 24M clock cycles, typical value is 2500. + 0 + 16 + read-write + + + + + ADVANCED + PLL0 advance configuration register + 0x20 + 32 + 0x00000000 + 0x11000000 + + + SLOW + Use slow lock flow, PLL lock expendite is disabled. This mode might be stabler. And software need config LOCKTIME field accordingly. +0: fast lock enabled, lock time is 100us +1: fast lock disabled, lock time is 400us + 28 + 1 + read-write + + + DITHER + Enable dither function + 24 + 1 + read-write + + + + + 3 + 0x4 + DIV0,DIV1,DIV2 + DIV[%s] + no description available + 0x40 + 32 + 0x00000000 + 0xB000003F + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Divider response status +0: Divider is not stable +1: Divider is stable for use + 29 + 1 + read-only + + + ENABLE + Divider enable status +0: Divider is off +1: Divider is on + 28 + 1 + read-only + + + DIV + Divider factor, divider factor is DIV/5 + 1 +0: divide by 1 +1: divide by 1.2 +2: divide by 1.4 +. . . +63: divide by 13.6 + 0 + 6 + read-write + + + + + + + + PPOR + PPOR + PPOR + 0xf4100000 + + 0x0 + 0x20 + registers + + + + RESET_FLAG + flag indicate reset source + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FLAG + reset reason of last hard reset, write 1 to clear each bit +0: brownout +1: temperature +4: debug reset +5: jtag soft reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2(not available) +19: watch dog 3(not available) +24: pmic watch dog +30: jtag ieee reset +31: software + 0 + 32 + write-only + + + + + RESET_STATUS + reset source status + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + current status of reset sources +0: brownout +1: temperature +4: debug reset +5: jtag soft reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2(not available) +19: watch dog 3(not available) +24: pmic watch dog +30: jtag ieee reset +31: software + 0 + 32 + read-only + + + + + RESET_HOLD + reset hold attribute + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + HOLD + hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status +0: brownout +1: temperature +4: debug reset +5: jtag soft reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2(not available) +19: watch dog 3(not available) +24: pmic watch dog +30: jtag ieee reset +31: software + 0 + 32 + read-write + + + + + RESET_ENABLE + reset source enable + 0xc + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + ENABLE + enable of reset sources +0: brownout +1: temperature +4: debug reset +5: jtag soft reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2(not available) +19: watch dog 3(not available) +24: pmic watch dog +30: jtag ieee reset +31: software + 0 + 32 + read-write + + + + + RESET_TYPE + reset type triggered by reset + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + TYPE + reset type of reset sources, 0 for cold reset, all system control setting cleared except debug/fuse/ioc; 1 for hot reset, keep system control setting and debug/fuse/ioc setting, only clear some subsystem +0: brownout +1: temperature +4: debug reset +5: jtag soft reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2(not available) +19: watch dog 3(not available) +24: pmic watch dog +30: jtag ieee reset +31: software + 0 + 32 + read-write + + + + + SOFTWARE_RESET + Software reset counter + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset + 0 + 32 + read-write + + + + + + + PCFG + PCFG + PMU + 0xf4104000 + + 0x0 + 0x70 + registers + + + + BANDGAP + BANGGAP control + 0x0 + 32 + 0x00101010 + 0x801F1F1F + + + VBG_TRIMMED + Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: bandgap is not trimmed +1: bandgap is trimmed + 31 + 1 + read-write + + + VBG_1P0_TRIM + Banggap 1.0V output trim value + 16 + 5 + read-write + + + VBG_P65_TRIM + Banggap 1.0V output trim value + 8 + 5 + read-write + + + VBG_P50_TRIM + Banggap 1.0V output trim value + 0 + 5 + read-write + + + + + LDO1P1 + 1V LDO config + 0x4 + 32 + 0x0000044C + 0x00000FFF + + + VOLT + LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. +700: 700mV +720: 720mV +. . . +1320:1320mV + 0 + 12 + read-write + + + + + LDO2P5 + 2.5V LDO config + 0x8 + 32 + 0x000009C4 + 0x10010FFF + + + READY + Ready flag, will set 1ms after enabled or voltage change +0: LDO is not ready for use +1: LDO is ready + 28 + 1 + read-only + + + ENABLE + LDO enable +0: turn off LDO +1: turn on LDO + 16 + 1 + read-write + + + VOLT + LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. +2125: 2125mV +2150: 2150mV +. . . +2900:2900mV + 0 + 12 + read-write + + + + + DCDC_MODE + DCDC mode select + 0x10 + 32 + 0x0001047E + 0x10070FFF + + + READY + Ready flag +0: DCDC is applying new change +1: DCDC is ready + 28 + 1 + read-only + + + MODE + DCDC work mode +XX0: turn off +001: basic mode +011: generic mode +101: automatic mode +111: expert mode + 16 + 3 + read-write + + + VOLT + DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. +600: 600mV +625: 625mV +. . . +1375:1375mV + 0 + 12 + read-write + + + + + DCDC_LPMODE + DCDC low power mode + 0x14 + 32 + 0x00000384 + 0x00000FFF + + + STBY_VOLT + DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. +600: 600mV +625: 625mV +. . . +1375:1375mV + 0 + 12 + read-write + + + + + DCDC_PROT + DCDC protection + 0x18 + 32 + 0x00000010 + 0x11018191 + + + ILIMIT_LP + over current setting for low power mode +0:250mA +1:200mA + 28 + 1 + read-write + + + OVERLOAD_LP + over current in low power mode +0: current is below setting +1: overcurrent happened in low power mode + 24 + 1 + read-only + + + POWER_LOSS_FLAG + power loss +0: input power is good +1: input power is too low + 16 + 1 + read-only + + + DISABLE_OVERVOLTAGE + output over voltage protection +0: protection enabled, DCDC will shut down is output voltage is unexpected high +1: protection disabled, DCDC continue to adjust output voltage + 15 + 1 + read-write + + + OVERVOLT_FLAG + output over voltage flag +0: output is normal +1: output is unexpected high + 8 + 1 + read-only + + + DISABLE_SHORT + disable output short circuit protection +0: short circuits protection enabled, DCDC shut down if short circuit on output detected +1: short circuit protection disabled + 7 + 1 + read-write + + + SHORT_CURRENT + short circuit current setting +0: 2.0A, +1: 1.3A + 4 + 1 + read-write + + + SHORT_FLAG + short circuit flag +0: current is within limit +1: short circuits detected + 0 + 1 + read-only + + + + + DCDC_CURRENT + DCDC current estimation + 0x1c + 32 + 0x00000000 + 0x0000811F + + + ESTI_EN + enable current measure + 15 + 1 + read-write + + + VALID + Current level valid +0: data is invalid +1: data is valid + 8 + 1 + read-only + + + LEVEL + DCDC current level, current level is num * 50mA + 0 + 5 + read-only + + + + + DCDC_ADVMODE + DCDC advance setting + 0x20 + 32 + 0x03120040 + 0x073F007F + + + EN_RCSCALE + Enable RC scale + 24 + 3 + read-write + + + DC_C + Loop C number + 20 + 2 + read-write + + + DC_R + Loop R number + 16 + 4 + read-write + + + EN_FF_DET + enable feed forward detect +0: feed forward detect is disabled +1: feed forward detect is enabled + 6 + 1 + read-write + + + EN_FF_LOOP + enable feed forward loop +0: feed forward loop is disabled +1: feed forward loop is enabled + 5 + 1 + read-write + + + EN_AUTOLP + enable auto enter low power mode +0: do not enter low power mode +1: enter low power mode if current is detected low + 4 + 1 + read-write + + + EN_DCM_EXIT + avoid over voltage +0: stay in DCM mode when voltage excess +1: change to CCM mode when voltage excess + 3 + 1 + read-write + + + EN_SKIP + enable skip on narrow pulse +0: do not skip narrow pulse +1: skip narrow pulse + 2 + 1 + read-write + + + EN_IDLE + enable skip when voltage is higher than threshold +0: do not skip +1: skip if voltage is excess + 1 + 1 + read-write + + + EN_DCM + DCM mode +0: CCM mode +1: DCM mode + 0 + 1 + read-write + + + + + DCDC_ADVPARAM + DCDC advance parameter + 0x24 + 32 + 0x00006E1C + 0x00007F7F + + + MIN_DUT + minimum duty cycle + 8 + 7 + read-write + + + MAX_DUT + maximum duty cycle + 0 + 7 + read-write + + + + + DCDC_MISC + DCDC misc parameter + 0x28 + 32 + 0x00070100 + 0x13170317 + + + EN_HYST + hysteres enable + 28 + 1 + read-write + + + HYST_SIGN + hysteres sign + 25 + 1 + read-write + + + HYST_THRS + hysteres threshold + 24 + 1 + read-write + + + RC_SCALE + Loop RC scale threshold + 20 + 1 + read-write + + + DC_FF + Loop feed forward number + 16 + 3 + read-write + + + OL_THRE + overload for threshold for lod power mode + 8 + 2 + read-write + + + OL_HYST + current hysteres range +0: 12.5mV +1: 25mV + 4 + 1 + read-write + + + DELAY + enable delay +0: delay disabled, +1: delay enabled + 2 + 1 + read-write + + + CLK_SEL + clock selection +0: select DCDC internal oscillator +1: select RC24M oscillator + 1 + 1 + read-write + + + EN_STEP + enable stepping in voltage change +0: stepping disabled, +1: steping enabled + 0 + 1 + read-write + + + + + DCDC_DEBUG + DCDC Debug + 0x2c + 32 + 0x00005DBF + 0x000FFFFF + + + UPDATE_TIME + DCDC voltage change time in 24M clock cycles, default value is 1mS + 0 + 20 + read-write + + + + + DCDC_START_TIME + DCDC ramp time + 0x30 + 32 + 0x0001193F + 0x000FFFFF + + + START_TIME + Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS + 0 + 20 + read-write + + + + + DCDC_RESUME_TIME + DCDC resume time + 0x34 + 32 + 0x00008C9F + 0x000FFFFF + + + RESUME_TIME + Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS + 0 + 20 + read-write + + + + + POWER_TRAP + SOC power trap + 0x40 + 32 + 0x00000000 + 0x80010001 + + + TRIGGERED + Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. +0: low power trap is not triggered +1: low power trap triggered + 31 + 1 + read-write + + + RETENTION + DCDC enter standby mode, which will reduce voltage for memory content retention +0: Shutdown DCDC +1: reduce DCDC voltage + 16 + 1 + read-write + + + TRAP + Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered +0: trap not enabled, pmic side low power function disabled +1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. + 0 + 1 + read-write + + + + + WAKE_CAUSE + Wake up source + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAUSE + wake up cause, each bit represents one wake up source, write 1 to clear the register bit +0: wake up source is not active during last wakeup +1: wake up source is active furing last wakeup +bit 0: pmic_enable +bit 7: UART interrupt +bit 8: TMR interrupt +bit 9: WDG interrupt +bit10: GPIO in PMIC interrupt +bit31: pin wakeup + 0 + 32 + read-write + + + + + WAKE_MASK + Wake up mask + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + MASK + mask for wake up sources, each bit represents one wakeup source +0: allow source to wake up system +1: disallow source to wakeup system +bit 0: pmic_enable +bit 7: UART interrupt +bit 8: TMR interrupt +bit 9: WDG interrupt +bit10: GPIO in PMIC interrupt +bit31: pin wakeup + 0 + 32 + read-write + + + + + SCG_CTRL + Clock gate control in PMIC + 0x4c + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + SCG + control whether clock being gated during PMIC low power flow, 2 bits for each peripheral +00,01: reserved +10: clock is always off +11: clock is always on +bit6-7:gpio +bit8-9:ioc +bit10-11: timer +bit12-13:wdog +bit14-15:uart + 0 + 32 + read-write + + + + + RC24M + RC 24M config + 0x60 + 32 + 0x00000310 + 0x8000071F + + + RC_TRIMMED + RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: RC is not trimmed +1: RC is trimmed + 31 + 1 + read-write + + + TRIM_C + Coarse trim for RC24M, bigger value means faster + 8 + 3 + read-write + + + TRIM_F + Fine trim for RC24M, bigger value means faster + 0 + 5 + read-write + + + + + RC24M_TRACK + RC 24M track mode + 0x64 + 32 + 0x00000000 + 0x00010011 + + + SEL24M + Select track reference +0: select 32K as reference +1: select 24M XTAL as reference + 16 + 1 + read-write + + + RETURN + Retrun default value when XTAL loss +0: remain last tracking value +1: switch to default value + 4 + 1 + read-write + + + TRACK + track mode +0: RC24M free running +1: track RC24M to external XTAL + 0 + 1 + read-write + + + + + TRACK_TARGET + RC 24M track target + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRE_DIV + Divider for reference source + 16 + 16 + read-write + + + TARGET + Target frequency multiplier of divided source + 0 + 16 + read-write + + + + + STATUS + RC 24M track status + 0x6c + 32 + 0x00000000 + 0x0011871F + + + SEL32K + track is using XTAL32K +0: track is not using XTAL32K +1: track is using XTAL32K + 20 + 1 + read-only + + + SEL24M + track is using XTAL24M +0: track is not using XTAL24M +1: track is using XTAL24M + 16 + 1 + read-only + + + EN_TRIM + default value takes effect +0: default value is invalid +1: default value is valid + 15 + 1 + read-only + + + TRIM_C + default coarse trim value + 8 + 3 + read-only + + + TRIM_F + default fine trim value + 0 + 5 + read-only + + + + + + + PGPR0 + PGPR0 + PGPR + 0xf4110000 + + 0x0 + 0x40 + registers + + + + PMIC_GPR00 + Generic control + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR01 + Generic control + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR02 + Generic control + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR03 + Generic control + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR04 + Generic control + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR05 + Generic control + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR06 + Generic control + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR07 + Generic control + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR08 + Generic control + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR09 + Generic control + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR10 + Generic control + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR11 + Generic control + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR12 + Generic control + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR13 + Generic control + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR14 + Generic control + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR15 + Generic control + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + + + PGPR1 + PGPR1 + PGPR + 0xf4114000 + + + PDGO + PDGO + PDGO + 0xf4134000 + + 0x0 + 0x714 + registers + + + + DGO_TURNOFF + trunoff control + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + trunoff counter, counter stops when it counts down to 0, the trunoff occurs when the counter value is 1. + 0 + 32 + write-only + + + + + DGO_RC32K_CFG + RC32K CLOCK + 0x4 + 32 + 0x00000000 + 0x80C001FF + + + IRC_TRIMMED + IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: irc is not trimmed +1: irc is trimmed + 31 + 1 + read-write + + + CAPEX7_TRIM + IRC32K bit 7 + 23 + 1 + read-write + + + CAPEX6_TRIM + IRC32K bit 6 + 22 + 1 + read-write + + + CAP_TRIM + capacitor trim bits + 0 + 9 + read-write + + + + + DGO_GPR00 + Generic control 0 + 0x600 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + DGO_GPR01 + Generic control 1 + 0x604 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + DGO_GPR02 + Generic control 2 + 0x608 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + DGO_GPR03 + Generic control 3 + 0x60c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + DGO_CTR0 + control register 0 + 0x700 + 32 + 0x00000000 + 0x00010000 + + + RETENTION + dgo register status retenion + 16 + 1 + read-write + + + + + DGO_CTR1 + control register 1 + 0x704 + 32 + 0x00000000 + 0x80010001 + + + AOTO_SYS_WAKEUP + software wakeup： 0 : wakeup once； 1：auto wakeup Continuously + 31 + 1 + read-write + + + WAKEUP_EN + permit wakeup pin or software wakeup + 16 + 1 + read-write + + + PIN_WAKEUP_STATUS + wakeup pin status + 0 + 1 + read-only + + + + + DGO_CTR2 + control register 2 + 0x708 + 32 + 0x00000000 + 0x01010000 + + + RESETN_PULLUP_DISABLE + resetn pin pull up disable + 24 + 1 + read-write + + + WAKEUP_PULLDN_DISABLE + wakeup pin pull down disable + 16 + 1 + read-write + + + + + DGO_CTR3 + control register 3 + 0x70c + 32 + 0x00000000 + 0xFFFFFFFF + + + WAKEUP_COUNTER + software wakeup counter + 0 + 32 + read-write + + + + + DGO_CTR4 + control register 4 + 0x710 + 32 + 0x00000000 + 0x00000003 + + + BANDGAP_LESS_POWER + Banggap work in power save mode, banggap function normally +0: banggap works in high performance mode +1: banggap works in power saving mode + 1 + 1 + read-write + + + BANDGAP_LP_MODE + Banggap work in low power mode, banggap function limited +0: banggap works in normal mode +1: banggap works in low power mode + 0 + 1 + read-write + + + + + + + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/SConscript b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/SConscript new file mode 100644 index 00000000000..dd355f33b20 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/SConscript @@ -0,0 +1,24 @@ +import os +import sys +Import('rtconfig') +from building import * + +#get current directory +cwd = GetCurrentDir() + +# Update include path +path = [ cwd, cwd + '/boot' ] + +# The set of source files associated with this SConscript file. +src = Split(''' + system.c + hpm_l1c_drv.c + hpm_sysctl_drv.c + hpm_clock_drv.c + hpm_otp_drv.c + boot/hpm_bootheader.c +''') + +group = DefineGroup('SoC', src, depend = [''], CPPPATH = path) + +Return ('group') diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/boot/hpm_bootheader.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/boot/hpm_bootheader.c new file mode 100644 index 00000000000..57cdf5aa2e6 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/boot/hpm_bootheader.c @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_bootheader.h" + +/* symbol exported from startup.S */ +extern uint32_t _start[]; + +/* following symbols exported from linker script */ +extern uint32_t __app_load_addr__[]; +extern uint32_t __app_offset__[]; +extern uint32_t __fw_size__[]; + +#define FW_SIZE (32768) +__attribute__ ((section(".fw_info_table"))) const fw_info_table_t fw_info = { + (uint32_t)__app_offset__, /* offset */ + (uint32_t)__fw_size__, /* size */ + 0, /* flags */ + 0, /* reserved0 */ + (uint32_t) &__app_load_addr__, /* load_addr */ + 0, /* reserved1 */ + (uint32_t) _start, /* entry_point */ + 0, /* reserved2 */ + {0}, /* hash */ + {0}, /* iv */ +}; + +__attribute__ ((section(".boot_header"))) const boot_header_t header = { + HPM_BOOTHEADER_TAG, /* tag */ + 0x10, /* version*/ + sizeof(header) + sizeof(fw_info), + 0, /* flags */ + 0, /* sw_version */ + 0, /* fuse_version */ + 1, /* fw_count */ + 0, + 0, /* sig_block_offset */ +}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/boot/hpm_bootheader.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/boot/hpm_bootheader.h new file mode 100644 index 00000000000..d7f22fd8240 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/boot/hpm_bootheader.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_BOOT_HEADER_H +#define HPM_BOOT_HEADER_H + +#include "hpm_common.h" + +#define HPM_BOOTHEADER_TAG (0xBFU) +#define HPM_BOOTHEADER_MAX_FW_COUNT (2U) + +#ifndef HPM_BOOT_FW_COUNT +#define HPM_BOOT_FW_COUNT 1 +#endif + +#if HPM_BOOT_FW_COUNT < 1 +#error "HPM_BOOT_FW_COUNT can't be less than 1" +#endif + +typedef struct { + uint32_t offset; /* 0x0: offset to boot_header start */ + uint32_t size; /* 0x4: size in bytes */ + uint32_t flags; /* 0x8: [3:0] fw type: */ + /* 0 - executable */ + /* 1 - cmd container */ + /* [11:8] - hash type */ + /* 0 - none */ + /* 1 - sha256 */ + /* 2 - sm3 */ + uint32_t reserved0; /* 0xC */ + uint32_t load_addr; /* 0x10: load address */ + uint32_t reserved1; /* 0x14 */ + uint32_t entry_point; /* 0x18: application entry */ + uint32_t reserved2; /* 0x1C */ + uint8_t hash[64]; /* 0x20: hash value */ + uint8_t iv[32]; /* 0x60: initial vector */ +} fw_info_table_t; + +typedef struct { + uint8_t tag; /* 0x0: must be '0xbf' */ + uint8_t version; /* 0x1: header version */ + uint16_t length; /* 0x2: header length, max 8KB */ + uint32_t flags; /* 0x4: [3:0] SRK set */ + /* [7:4] SRK index */ + /* [15:8] SRK_REVOKE_MASK */ + /* [19:16] Signature Type */ + /* 1: ECDSA */ + /* 2: SM2 */ + uint16_t sw_version; /* 0x8: software version */ + uint8_t fuse_version; /* 0xA: fuse version */ + uint8_t fw_count; /* 0xB: number of fw */ + uint16_t dc_block_offset; /* 0xC: device config block offset*/ + uint16_t sig_block_offset; /* 0xE: signature block offset */ + /* + * fw_info_table_t fw_info[HPM_BOOT_FW_COUNT]; [> 0x10: fw table <] + * uint32_t dc_info[]; [> <] + */ +} boot_header_t; + +#endif /* HPM_BOOT_HEADER_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_clock_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_clock_drv.c new file mode 100644 index 00000000000..18e629aefae --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_clock_drv.c @@ -0,0 +1,471 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_clock_drv.h" +#include "hpm_sysctl_drv.h" +#include "hpm_soc.h" +#include "hpm_common.h" +#include "hpm_pllctlv2_drv.h" +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/* Clock preset values */ +#define FREQ_PRESET1_OSC0_CLK0 (24000000UL) +#define FREQ_PRESET1_PLL0_CLK0 (720000000UL) +#define FREQ_PRESET1_PLL0_CLK1 (450000000UL) +#define FREQ_PRESET1_PLL0_CLK2 (300000000UL) +#define FREQ_PRESET1_PLL1_CLK0 (800000000UL) +#define FREQ_PRESET1_PLL1_CLK1 (666666666UL) +#define FREQ_PRESET1_PLL1_CLK2 (500000000UL) +#define FREQ_PRESET1_PLL1_CLK3 (266666666UL) +#define FREQ_32KHz (32768UL) +#define ADC_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->ADCCLK) +#define DAC_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->DACCLK) +#define WDG_INSTANCE_NUM (2U) +#define BUS_FREQ_MAX (200000000UL) +#define FREQ_1MHz (1000000UL) + +/* Clock On/Off definitions */ +#define CLOCK_ON (true) +#define CLOCK_OFF (false) + + +/*********************************************************************************************************************** + * Prototypes + **********************************************************************************************************************/ + +/** + * @brief Get Clock frequency for IP in common group + */ +static uint32_t get_frequency_for_ip_in_common_group(clock_node_t node); + +/** + * @brief Get Clock frequency for ADC + */ +static uint32_t get_frequency_for_adc(uint32_t clk_src_type, uint32_t instance); + +/** + * @brief Get Clock frequency for WDG + */ +static uint32_t get_frequency_for_ewdg(uint32_t instance); + +/** + * @brief Get Clock frequency for PWDG + */ +static uint32_t get_frequency_for_pewdg(void); + +/** + * @brief Turn on/off the IP clock + */ +static void switch_ip_clock(clock_name_t clock_name, bool on); + +static uint32_t get_frequency_for_cpu(void); +static uint32_t get_frequency_for_ahb(void); + + +/*********************************************************************************************************************** + * Variables + **********************************************************************************************************************/ +static const clock_node_t s_adc_clk_mux_node[] = { + clock_node_ahb, + clock_node_ana0 +}; + +static EWDG_Type *const s_wdgs[] = { HPM_EWDG0, HPM_EWDG1}; + +uint32_t hpm_core_clock; + + +/*********************************************************************************************************************** + * Codes + **********************************************************************************************************************/ +uint32_t clock_get_frequency(clock_name_t clock_name) +{ + uint32_t clk_freq = 0UL; + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + switch (clk_src_type) { + case CLK_SRC_GROUP_COMMON: + clk_freq = get_frequency_for_ip_in_common_group((clock_node_t) node_or_instance); + break; + case CLK_SRC_GROUP_ADC: + clk_freq = get_frequency_for_adc(CLK_SRC_GROUP_ADC, node_or_instance); + break; + case CLK_SRC_GROUP_EWDG: + clk_freq = get_frequency_for_ewdg(node_or_instance); + break; + case CLK_SRC_GROUP_PEWDG: + clk_freq = get_frequency_for_pewdg(); + break; + case CLK_SRC_GROUP_PMIC: + clk_freq = FREQ_PRESET1_OSC0_CLK0; + break; + case CLK_SRC_GROUP_CPU0: + clk_freq = get_frequency_for_cpu(); + break; + case CLK_SRC_GROUP_AHB: + clk_freq = get_frequency_for_ahb(); + break; + case CLK_SRC_GROUP_SRC: + clk_freq = get_frequency_for_source((clock_source_t) node_or_instance); + break; + default: + clk_freq = 0UL; + break; + } + return clk_freq; +} + +uint32_t get_frequency_for_source(clock_source_t source) +{ + uint32_t clk_freq = 0UL; + switch (source) { + case clock_source_osc0_clk0: + clk_freq = FREQ_PRESET1_OSC0_CLK0; + break; + case clock_source_pll0_clk0: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 0U); + break; + case clock_source_pll0_clk1: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 1U); + break; + case clock_source_pll0_clk2: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 2U); + break; + case clock_source_pll1_clk0: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 0U); + break; + case clock_source_pll1_clk1: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 1U); + break; + case clock_source_pll1_clk2: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 2U); + break; + case clock_source_pll1_clk3: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 3U); + break; + default: + clk_freq = 0UL; + break; + } + + return clk_freq; +} + +static uint32_t get_frequency_for_ip_in_common_group(clock_node_t node) +{ + uint32_t clk_freq = 0UL; + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(node); + + if (node_or_instance < clock_node_end) { + uint32_t clk_node = (uint32_t) node_or_instance; + + uint32_t clk_div = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[clk_node]); + clock_source_t clk_mux = (clock_source_t) SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[clk_node]); + clk_freq = get_frequency_for_source(clk_mux) / clk_div; + } + return clk_freq; +} + +static uint32_t get_frequency_for_adc(uint32_t clk_src_type, uint32_t instance) +{ + uint32_t clk_freq = 0UL; + bool is_mux_valid = false; + clock_node_t node = clock_node_end; + uint32_t adc_index = instance; + + (void) clk_src_type; + + if (adc_index < ADC_INSTANCE_NUM) { + uint32_t mux_in_reg = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[adc_index]); + if (mux_in_reg < ARRAY_SIZE(s_adc_clk_mux_node)) { + node = s_adc_clk_mux_node[mux_in_reg]; + is_mux_valid = true; + } + } + + if (is_mux_valid) { + if (node != clock_node_ahb) { + node += instance; + clk_freq = get_frequency_for_ip_in_common_group(node); + } else { + clk_freq = get_frequency_for_ahb(); + } + } + return clk_freq; +} + +static uint32_t get_frequency_for_ewdg(uint32_t instance) +{ + uint32_t freq_in_hz; + if (EWDG_CTRL0_CLK_SEL_GET(s_wdgs[instance]->CTRL0) == 0) { + freq_in_hz = get_frequency_for_ahb(); + } else { + freq_in_hz = FREQ_32KHz; + } + + return freq_in_hz; +} + +static uint32_t get_frequency_for_pewdg(void) +{ + uint32_t freq_in_hz; + if (EWDG_CTRL0_CLK_SEL_GET(HPM_PEWDG->CTRL0) == 0) { + freq_in_hz = FREQ_PRESET1_OSC0_CLK0; + } else { + freq_in_hz = FREQ_32KHz; + } + + return freq_in_hz; +} + +static uint32_t get_frequency_for_cpu(void) +{ + uint32_t mux = SYSCTL_CLOCK_CPU_MUX_GET(HPM_SYSCTL->CLOCK_CPU[0]); + uint32_t div = SYSCTL_CLOCK_CPU_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]) + 1U; + return (get_frequency_for_source(mux) / div); +} + +static uint32_t get_frequency_for_ahb(void) +{ + uint32_t div = SYSCTL_CLOCK_CPU_SUB0_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]) + 1U; + return (get_frequency_for_cpu() / div); +} + +clk_src_t clock_get_source(clock_name_t clock_name) +{ + uint8_t clk_src_group = CLK_SRC_GROUP_INVALID; + uint8_t clk_src_index = 0xFU; + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + switch (clk_src_type) { + case CLK_SRC_GROUP_COMMON: + clk_src_group = CLK_SRC_GROUP_COMMON; + clk_src_index = SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[node_or_instance]); + break; + case CLK_SRC_GROUP_ADC: + if (node_or_instance < ADC_INSTANCE_NUM) { + clk_src_group = CLK_SRC_GROUP_ADC; + clk_src_index = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[node_or_instance]); + } + break; + case CLK_SRC_GROUP_EWDG: + if (node_or_instance < WDG_INSTANCE_NUM) { + clk_src_group = CLK_SRC_GROUP_EWDG; + clk_src_index = EWDG_CTRL0_CLK_SEL_GET(s_wdgs[node_or_instance]->CTRL0); + } + break; + case CLK_SRC_GROUP_PEWDG: + clk_src_group = CLK_SRC_GROUP_PEWDG; + clk_src_index = EWDG_CTRL0_CLK_SEL_GET(HPM_PEWDG->CTRL0); + break; + case CLK_SRC_GROUP_PMIC: + clk_src_group = CLK_SRC_GROUP_COMMON; + clk_src_index = clock_source_osc0_clk0; + break; + case CLK_SRC_GROUP_CPU0: + case CLK_SRC_GROUP_AHB: + clk_src_group = CLK_SRC_GROUP_CPU0; + clk_src_index = SYSCTL_CLOCK_CPU_MUX_GET(HPM_SYSCTL->CLOCK_CPU[0]); + break; + case CLK_SRC_GROUP_SRC: + clk_src_index = (clk_src_t) node_or_instance; + break; + default: + clk_src_group = CLK_SRC_GROUP_INVALID; + break; + } + + clk_src_t clk_src; + if (clk_src_group != CLK_SRC_GROUP_INVALID) { + clk_src = MAKE_CLK_SRC(clk_src_group, clk_src_index); + } else { + clk_src = clk_src_invalid; + } + + return clk_src; +} + +uint32_t clock_get_divider(clock_name_t clock_name) +{ + uint32_t clk_divider = CLOCK_DIV_INVALID; + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + switch (clk_src_type) { + case CLK_SRC_GROUP_COMMON: + clk_divider = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[node_or_instance]); + break; + case CLK_SRC_GROUP_EWDG: + clk_divider = 1; + break; + case CLK_SRC_GROUP_PEWDG: + clk_divider = 1; + break; + case CLK_SRC_GROUP_PMIC: + clk_divider = 1; + break; + case CLK_SRC_GROUP_CPU0: + clk_divider = 1UL + SYSCTL_CLOCK_CPU_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]); + break; + case CLK_SRC_GROUP_AHB: + clk_divider = 1UL + SYSCTL_CLOCK_CPU_SUB0_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]); + break; + default: + clk_divider = CLOCK_DIV_INVALID; + break; + } + return clk_divider; +} + +hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src) +{ + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + + if ((clk_src_type != CLK_SRC_GROUP_ADC) || (node_or_instance >= ADC_INSTANCE_NUM)) { + return status_clk_invalid; + } + + if ((src < clk_adc_src_ahb0) || (src > clk_adc_src_ana1)) { + return status_clk_src_invalid; + } + + uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); + HPM_SYSCTL->ADCCLK[node_or_instance] = + (HPM_SYSCTL->ADCCLK[node_or_instance] & ~SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(clk_src_index); + + return status_success; +} + +hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint32_t div) +{ + hpm_stat_t status = status_success; + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + switch (clk_src_type) { + case CLK_SRC_GROUP_COMMON: + if ((div < 1U) || (div > 256U)) { + status = status_clk_div_invalid; + } else { + clock_source_t clk_src = GET_CLOCK_SOURCE_FROM_CLK_SRC(src); + sysctl_config_clock(HPM_SYSCTL, (clock_node_t) node_or_instance, clk_src, div); + } + break; + case CLK_SRC_GROUP_ADC: + case CLK_SRC_GROUP_EWDG: + case CLK_SRC_GROUP_PEWDG: + case CLK_SRC_GROUP_SRC: + status = status_clk_operation_unsupported; + break; + case CLK_SRC_GROUP_PMIC: + status = status_clk_fixed; + break; + case CLK_SRC_GROUP_AHB: + status = status_clk_shared_cpu0; + break; + case CLK_SRC_GROUP_CPU0: + if (node_or_instance == clock_node_cpu0) { + /* Note: the AXI and AHB BUS share the same CPU clock, once the CPU clock frequency + * changes, the AXI and AHB clock changes accordingly, here the driver ensures the + * AXI and AHB bus clock frequency is in valid range. + */ + uint32_t expected_freq = get_frequency_for_source((clock_source_t) src) / div; + uint32_t ahb_sub_div = (expected_freq + BUS_FREQ_MAX - 1U) / BUS_FREQ_MAX; + sysctl_config_cpu0_domain_clock(HPM_SYSCTL, (clock_source_t) src, div, ahb_sub_div); + } else { + status = status_clk_shared_cpu0; + } + break; + default: + status = status_clk_src_invalid; + break; + } + + return status; +} + +static void switch_ip_clock(clock_name_t clock_name, bool on) +{ + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + if (resource < sysctl_resource_end) { + uint32_t mode = on ? 1UL : 2UL; + HPM_SYSCTL->RESOURCE[resource] = + (HPM_SYSCTL->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | SYSCTL_RESOURCE_MODE_SET(mode); + } +} + + +void clock_enable(clock_name_t clock_name) +{ + switch_ip_clock(clock_name, CLOCK_ON); +} + +void clock_disable(clock_name_t clock_name) +{ + switch_ip_clock(clock_name, CLOCK_OFF); +} + +void clock_add_to_group(clock_name_t clock_name, uint32_t group) +{ + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + if (resource < sysctl_resource_end) { + sysctl_enable_group_resource(HPM_SYSCTL, group, resource, true); + } +} + +void clock_remove_from_group(clock_name_t clock_name, uint32_t group) +{ + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + if (resource < sysctl_resource_end) { + sysctl_enable_group_resource(HPM_SYSCTL, group, resource, false); + } +} + +bool clock_check_in_group(clock_name_t clock_name, uint32_t group) +{ + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + return sysctl_check_group_resource_enable(HPM_SYSCTL, group, resource); +} + +void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu) +{ + if (cpu == 0U) { + HPM_SYSCTL->AFFILIATE[cpu].SET = (1UL << group); + } +} + +void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu) +{ + if (cpu == 0U) { + HPM_SYSCTL->AFFILIATE[cpu].CLEAR = (1UL << group); + } +} + +void clock_cpu_delay_us(uint32_t us) +{ + uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; + uint64_t expected_ticks = hpm_csr_get_core_cycle() + ticks_per_us * us; + while (hpm_csr_get_core_cycle() < expected_ticks) { + } +} + +void clock_cpu_delay_ms(uint32_t ms) +{ + uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; + uint64_t expected_ticks = hpm_csr_get_core_cycle() + (uint64_t)ticks_per_us * 1000UL * ms; + while (hpm_csr_get_core_cycle() < expected_ticks) { + } +} + +void clock_update_core_clock(void) +{ + hpm_core_clock = clock_get_frequency(clock_cpu0); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_clock_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_clock_drv.h new file mode 100644 index 00000000000..d903321c4d0 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_clock_drv.h @@ -0,0 +1,307 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_CLOCK_DRV_H +#define HPM_CLOCK_DRV_H + +#include "hpm_common.h" +#include "hpm_sysctl_drv.h" +#include "hpm_csr_drv.h" + + +#define CLOCK_DIV_INVALID (~0UL) + +/** + * @brief Error codes for clock driver + */ +enum { + status_clk_div_invalid = MAKE_STATUS(status_group_clk, 0), + status_clk_src_invalid = MAKE_STATUS(status_group_clk, 1), + status_clk_invalid = MAKE_STATUS(status_group_clk, 2), + status_clk_operation_unsupported = MAKE_STATUS(status_group_clk, 3), + status_clk_shared_ahb = MAKE_STATUS(status_group_clk, 4), + status_clk_shared_axi0 = MAKE_STATUS(status_group_clk, 5), + status_clk_shared_axi1 = MAKE_STATUS(status_group_clk, 6), + status_clk_shared_axi2 = MAKE_STATUS(status_group_clk, 7), + status_clk_shared_cpu0 = MAKE_STATUS(status_group_clk, 8), + status_clk_shared_cpu1 = MAKE_STATUS(status_group_clk, 9), + status_clk_fixed = MAKE_STATUS(status_group_clk, 10), +}; + +/** + * @brief Clock source group definitions + */ +#define CLK_SRC_GROUP_COMMON (0U) +#define CLK_SRC_GROUP_ADC (1U) +#define CLK_SRC_GROUP_EWDG (3U) +#define CLK_SRC_GROUP_PMIC (4U) +#define CLK_SRC_GROUP_AHB (5U) +#define CLK_SRC_GROUP_CPU0 (9U) +#define CLK_SRC_GROUP_SRC (10U) +#define CLK_SRC_GROUP_PEWDG (11U) +#define CLK_SRC_GROUP_INVALID (15U) + +#define MAKE_CLK_SRC(src_grp, index) (((uint8_t)(src_grp)<<4) | (index)) +#define GET_CLK_SRC_GROUP(src) (((uint8_t)(src)>>4) & 0x0FU) +#define GET_CLK_SRC_INDEX(src) ((uint8_t)(src) & 0x0FU) + +#define GET_CLOCK_SOURCE_FROM_CLK_SRC(clk_src) (clock_source_t)((uint32_t)(clk_src) & 0xFU) + +/** + * @brief Clock source definitions + */ +typedef enum _clock_sources { + clk_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 0), + clk_src_pll0_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 1), + clk_src_pll0_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 2), + clk_src_pll0_clk2 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 3), + clk_src_pll1_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 4), + clk_src_pll1_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 5), + clk_src_pll1_clk2 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 6), + clk_src_pll1_clk3 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 7), + clk_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 8), + + clk_adc_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), + clk_adc_src_ana0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 1), + clk_adc_src_ana1 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 1), + + clk_wdg_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_EWDG, 0), + clk_wdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_EWDG, 1), + + clk_pwdg_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_PEWDG, 0), + clk_pwdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_PEWDG, 1), + + clk_src_invalid = MAKE_CLK_SRC(CLK_SRC_GROUP_INVALID, 15), +} clk_src_t; + + +#define RESOURCE_INVALID (0xFFFFU) +#define RESOURCE_SHARED_CPU0 (0xFFFDU) + +/* Clock NAME related Macros */ +#define MAKE_CLOCK_NAME(resource, src_type, node) (((uint32_t)(resource) << 16) | ((uint32_t)(src_type) << 8) | ((uint32_t)(node))) +#define GET_CLK_SRC_GROUP_FROM_NAME(name) (((uint32_t)(name) >> 8) & 0xFFUL) +#define GET_CLK_NODE_FROM_NAME(name) ((uint32_t)(name) & 0xFFUL) +#define GET_CLK_RESOURCE_FROM_NAME(name) ((uint32_t)(name) >> 16) + +/** + * @brief Peripheral Clock Type Description + */ +typedef enum _clock_name { + clock_cpu0 = MAKE_CLOCK_NAME(sysctl_resource_cpu0, CLK_SRC_GROUP_CPU0, clock_node_cpu0), + + clock_mchtmr0 = MAKE_CLOCK_NAME(sysctl_resource_mchtmr0, CLK_SRC_GROUP_COMMON, clock_node_mchtmr0), + clock_gptmr0 = MAKE_CLOCK_NAME(sysctl_resource_gptmr0, CLK_SRC_GROUP_COMMON, clock_node_gptmr0), + clock_gptmr1 = MAKE_CLOCK_NAME(sysctl_resource_gptmr1, CLK_SRC_GROUP_COMMON, clock_node_gptmr1), + clock_i2c0 = MAKE_CLOCK_NAME(sysctl_resource_i2c0, CLK_SRC_GROUP_COMMON, clock_node_i2c0), + clock_i2c1 = MAKE_CLOCK_NAME(sysctl_resource_i2c1, CLK_SRC_GROUP_COMMON, clock_node_i2c1), + clock_i2c2 = MAKE_CLOCK_NAME(sysctl_resource_i2c2, CLK_SRC_GROUP_COMMON, clock_node_i2c2), + clock_i2c3 = MAKE_CLOCK_NAME(sysctl_resource_i2c3, CLK_SRC_GROUP_COMMON, clock_node_i2c3), + clock_spi0 = MAKE_CLOCK_NAME(sysctl_resource_spi0, CLK_SRC_GROUP_COMMON, clock_node_spi0), + clock_spi1 = MAKE_CLOCK_NAME(sysctl_resource_spi1, CLK_SRC_GROUP_COMMON, clock_node_spi1), + clock_spi2 = MAKE_CLOCK_NAME(sysctl_resource_spi2, CLK_SRC_GROUP_COMMON, clock_node_spi2), + clock_spi3 = MAKE_CLOCK_NAME(sysctl_resource_spi3, CLK_SRC_GROUP_COMMON, clock_node_spi3), + clock_uart0 = MAKE_CLOCK_NAME(sysctl_resource_uart0, CLK_SRC_GROUP_COMMON, clock_node_uart0), + clock_uart1 = MAKE_CLOCK_NAME(sysctl_resource_uart1, CLK_SRC_GROUP_COMMON, clock_node_uart1), + clock_uart2 = MAKE_CLOCK_NAME(sysctl_resource_uart2, CLK_SRC_GROUP_COMMON, clock_node_uart2), + clock_uart3 = MAKE_CLOCK_NAME(sysctl_resource_uart3, CLK_SRC_GROUP_COMMON, clock_node_uart3), + clock_uart4 = MAKE_CLOCK_NAME(sysctl_resource_uart4, CLK_SRC_GROUP_COMMON, clock_node_uart4), + clock_xpi0 = MAKE_CLOCK_NAME(sysctl_resource_xpi0, CLK_SRC_GROUP_COMMON, clock_node_xpi0), + clock_ref0 = MAKE_CLOCK_NAME(sysctl_resource_ref0, CLK_SRC_GROUP_COMMON, clock_node_ref0), + clock_ref1 = MAKE_CLOCK_NAME(sysctl_resource_ref1, CLK_SRC_GROUP_COMMON, clock_node_ref1), + + clock_ahb = MAKE_CLOCK_NAME(RESOURCE_SHARED_CPU0, CLK_SRC_GROUP_AHB, clock_node_ahb), + + clock_watchdog0 = MAKE_CLOCK_NAME(sysctl_resource_wdg0, CLK_SRC_GROUP_EWDG, 0), + clock_watchdog1 = MAKE_CLOCK_NAME(sysctl_resource_wdg1, CLK_SRC_GROUP_EWDG, 1), + clock_pwdg = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PEWDG, 0), + + clock_lmm0 = MAKE_CLOCK_NAME(sysctl_resource_lmm0, CLK_SRC_GROUP_CPU0, 0), + + clock_mbx0 = MAKE_CLOCK_NAME(sysctl_resource_mbx0, CLK_SRC_GROUP_AHB, 0), + clock_crc0 = MAKE_CLOCK_NAME(sysctl_resource_crc0, CLK_SRC_GROUP_AHB, 1), + clock_acmp = MAKE_CLOCK_NAME(sysctl_resource_acmp, CLK_SRC_GROUP_AHB, 2), + clock_kman = MAKE_CLOCK_NAME(sysctl_resource_kman, CLK_SRC_GROUP_AHB, 8), + clock_gpio = MAKE_CLOCK_NAME(sysctl_resource_gpio, CLK_SRC_GROUP_AHB, 9), + clock_hdma = MAKE_CLOCK_NAME(sysctl_resource_hdma, CLK_SRC_GROUP_AHB, 10), + clock_rom = MAKE_CLOCK_NAME(sysctl_resource_rom0, CLK_SRC_GROUP_AHB, 11), + clock_tsns = MAKE_CLOCK_NAME(sysctl_resource_tsns, CLK_SRC_GROUP_AHB, 12), + clock_usb0 = MAKE_CLOCK_NAME(sysctl_resource_usb0, CLK_SRC_GROUP_AHB, 13), + + clock_ptmr = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 0), + clock_puart = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 1), + clock_pgpio = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 2), + + /* For ADC, there are 2-stage clock source and divider configurations */ + clock_ana0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana0), + clock_ana1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana1), + clock_adc0 = MAKE_CLOCK_NAME(sysctl_resource_adc0, CLK_SRC_GROUP_ADC, 0), + + /* For DAC, there are 2-stage clock source and divider configurations */ + clock_ana2 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana2), + clock_ana3 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana3), + + /* Clock sources */ + clk_osc0clk0 = MAKE_CLOCK_NAME(sysctl_resource_xtal, CLK_SRC_GROUP_SRC, 0), + clk_pll0clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll0, CLK_SRC_GROUP_SRC, 1), + clk_pll0clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll0, CLK_SRC_GROUP_SRC, 2), + clk_pll0clk2 = MAKE_CLOCK_NAME(sysctl_resource_clk2_pll0, CLK_SRC_GROUP_SRC, 3), + clk_pll1clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll1, CLK_SRC_GROUP_SRC, 4), + clk_pll1clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll1, CLK_SRC_GROUP_SRC, 5), + clk_pll1clk2 = MAKE_CLOCK_NAME(sysctl_resource_clk2_pll1, CLK_SRC_GROUP_SRC, 6), + clk_pll1clk3 = MAKE_CLOCK_NAME(sysctl_resource_clk3_pll1, CLK_SRC_GROUP_SRC, 7), +} clock_name_t; + +extern uint32_t hpm_core_clock; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Get specified IP frequency + * @param[in] clock_name IP clock name + * + * @return IP clock frequency in Hz + */ +uint32_t clock_get_frequency(clock_name_t clock_name); + +/** + * @brief Get Clock frequency for selected clock source + * @param [in] source clock source + * @return clock frequency for selected clock source + */ +uint32_t get_frequency_for_source(clock_source_t source); + +/** + * @brief Get the IP clock source + * Note: This API return the direct clock source + * @param [in] clock_name clock name + * @return IP clock source + */ +clk_src_t clock_get_source(clock_name_t clock_name); + +/** + * @brief Get the IP clock divider + * Note:This API return the direct clock divider + * @param [in] clock_name clock name + * @return IP clock divider + */ +uint32_t clock_get_divider(clock_name_t clock_name); + +/** + * @brief Set ADC clock source + * @param[in] clock_name ADC clock name + * @param[in] src ADC clock source + * + * @return #status_success Setting ADC clock source is successful + * #status_clk_invalid Invalid ADC clock + * #status_clk_src_invalid Invalid ADC clock source + */ +hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src); + +/** + * @brief Set DAC clock source + * @param[in] clock_name DAC clock name + * @param[in] src DAC clock source + * + * @return #status_success Setting DAC clock source is successful + * #status_clk_invalid Invalid DAC clock + * #status_clk_src_invalid Invalid DAC clock source + */ +hpm_stat_t clock_set_dac_source(clock_name_t clock_name, clk_src_t src); + +/** + * @brief Set the IP clock source and divider + * @param[in] clock_name clock name + * @param[in] src clock source + * @param[in] div clock divider, valid range (1 - 256) + * + * @return #status_success Setting Clock source and divider is successful. + * #status_clk_src_invalid clock source is invalid. + * #status_clk_fixed clock source and divider is a fixed value + * #status_clk_shared_ahb Clock is shared with the AHB clock + * #status_clk_shared_axi0 Clock is shared with the AXI0 clock + * #status_clk_shared_axi1 CLock is shared with the AXI1 clock + * #status_clk_shared_axi2 Clock is shared with the AXI2 clock + * #status_clk_shared_cpu0 Clock is shared with the CPU0 clock + * #status_clk_shared_cpu1 Clock is shared with the CPU1 clock + */ +hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint32_t div); + +/** + * @brief Enable IP clock + * @param[in] clock_name IP clock name + */ +void clock_enable(clock_name_t clock_name); + +/** + * @brief Disable IP clock + * @param[in] clock_name IP clock name + */ +void clock_disable(clock_name_t clock_name); + +/** + * @brief Add IP to specified group + * @param[in] clock_name IP clock name + * @param[in] group resource group index, valid value: 0/1/2/3 + */ +void clock_add_to_group(clock_name_t clock_name, uint32_t group); + +/** + * @brief Remove IP from specified group + * @param[in] clock_name IP clock name + * @param[in] group resource group index, valid value: 0/1/2/3 + */ +void clock_remove_from_group(clock_name_t clock_name, uint32_t group); + +/** + * @brief Check IP in specified group + * @param[in] clock_name IP clock name + * @param[in] group resource group index, valid value: 0/1/2/3 + * @return true if in group, false if not in group + */ +bool clock_check_in_group(clock_name_t clock_name, uint32_t group); + +/** + * @brief Disconnect the clock group from specified CPU + * @param[in] group clock group index, value value is 0/1/2/3 + * @param[in] cpu CPU index, valid value is 0/1 + */ +void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu); + +/** + * @brief Disconnect the clock group from specified CPU + * @param[in] group clock group index, value value is 0/1/2/3 + * @param[in] cpu CPU index, valid value is 0/1 + */ +void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu); + +/** + * @brief Delay specified microseconds + * + * @param [in] us expected delay interval in microseconds + */ +void clock_cpu_delay_us(uint32_t us); + +/** + * @brief Delay specified milliseconds + * + * @param [in] ms expected delay interval in milliseconds + */ +void clock_cpu_delay_ms(uint32_t ms); + +/** + * @brief Update the Core clock frequency + */ +void clock_update_core_clock(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_CLOCK_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_csr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_csr_regs.h new file mode 100644 index 00000000000..09c7fc113ff --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_csr_regs.h @@ -0,0 +1,4276 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_CSR_H +#define HPM_CSR_H + +/* STANDARD CRS address definition */ +#define CSR_USTATUS (0x0) +#define CSR_UIE (0x4) +#define CSR_UTVEC (0x5) +#define CSR_USCRATCH (0x40) +#define CSR_UEPC (0x41) +#define CSR_UCAUSE (0x42) +#define CSR_UTVAL (0x43) +#define CSR_UIP (0x44) +#define CSR_MSTATUS (0x300) +#define CSR_MISA (0x301) +#define CSR_MIE (0x304) +#define CSR_MTVEC (0x305) +#define CSR_MCOUNTEREN (0x306) +#define CSR_MHPMEVENT3 (0x323) +#define CSR_MHPMEVENT4 (0x324) +#define CSR_MHPMEVENT5 (0x325) +#define CSR_MHPMEVENT6 (0x326) +#define CSR_MSCRATCH (0x340) +#define CSR_MEPC (0x341) +#define CSR_MCAUSE (0x342) +#define CSR_MTVAL (0x343) +#define CSR_MIP (0x344) +#define CSR_PMPCFG0 (0x3A0) +#define CSR_PMPCFG1 (0x3A1) +#define CSR_PMPCFG2 (0x3A2) +#define CSR_PMPCFG3 (0x3A3) +#define CSR_PMPADDR0 (0x3B0) +#define CSR_PMPADDR1 (0x3B1) +#define CSR_PMPADDR2 (0x3B2) +#define CSR_PMPADDR3 (0x3B3) +#define CSR_PMPADDR4 (0x3B4) +#define CSR_PMPADDR5 (0x3B5) +#define CSR_PMPADDR6 (0x3B6) +#define CSR_PMPADDR7 (0x3B7) +#define CSR_PMPADDR8 (0x3B8) +#define CSR_PMPADDR9 (0x3B9) +#define CSR_PMPADDR10 (0x3BA) +#define CSR_PMPADDR11 (0x3BB) +#define CSR_PMPADDR12 (0x3BC) +#define CSR_PMPADDR13 (0x3BD) +#define CSR_PMPADDR14 (0x3BE) +#define CSR_PMPADDR15 (0x3BF) +#define CSR_TSELECT (0x7A0) +#define CSR_TDATA1 (0x7A1) +#define CSR_MCONTROL (0x7A1) +#define CSR_ICOUNT (0x7A1) +#define CSR_ITRIGGER (0x7A1) +#define CSR_ETRIGGER (0x7A1) +#define CSR_TDATA2 (0x7A2) +#define CSR_TDATA3 (0x7A3) +#define CSR_TEXTRA (0x7A3) +#define CSR_TINFO (0x7A4) +#define CSR_TCONTROL (0x7A5) +#define CSR_MCONTEXT (0x7A8) +#define CSR_SCONTEXT (0x7AA) +#define CSR_DCSR (0x7B0) +#define CSR_DPC (0x7B1) +#define CSR_DSCRATCH0 (0x7B2) +#define CSR_DSCRATCH1 (0x7B3) +#define CSR_MCYCLE (0xB00) +#define CSR_MINSTRET (0xB02) +#define CSR_MHPMCOUNTER3 (0xB03) +#define CSR_MHPMCOUNTER4 (0xB04) +#define CSR_MHPMCOUNTER5 (0xB05) +#define CSR_MHPMCOUNTER6 (0xB06) +#define CSR_MCYCLEH (0xB80) +#define CSR_MINSTRETH (0xB82) +#define CSR_MHPMCOUNTER3H (0xB83) +#define CSR_MHPMCOUNTER4H (0xB84) +#define CSR_MHPMCOUNTER5H (0xB85) +#define CSR_MHPMCOUNTER6H (0xB86) +#define CSR_CYCLE (0xC00) +#define CSR_CYCLEH (0xC80) +#define CSR_MVENDORID (0xF11) +#define CSR_MARCHID (0xF12) +#define CSR_MIMPID (0xF13) +#define CSR_MHARTID (0xF14) + +/* NON-STANDARD CRS address definition */ +#define CSR_MCOUNTINHIBIT (0x320) +#define CSR_MILMB (0x7C0) +#define CSR_MDLMB (0x7C1) +#define CSR_MECC_CODE (0x7C2) +#define CSR_MNVEC (0x7C3) +#define CSR_MXSTATUS (0x7C4) +#define CSR_MPFT_CTL (0x7C5) +#define CSR_MHSP_CTL (0x7C6) +#define CSR_MSP_BOUND (0x7C7) +#define CSR_MSP_BASE (0x7C8) +#define CSR_MDCAUSE (0x7C9) +#define CSR_MCACHE_CTL (0x7CA) +#define CSR_MCCTLBEGINADDR (0x7CB) +#define CSR_MCCTLCOMMAND (0x7CC) +#define CSR_MCCTLDATA (0x7CD) +#define CSR_MCOUNTERWEN (0x7CE) +#define CSR_MCOUNTERINTEN (0x7CF) +#define CSR_MMISC_CTL (0x7D0) +#define CSR_MCOUNTERMASK_M (0x7D1) +#define CSR_MCOUNTERMASK_S (0x7D2) +#define CSR_MCOUNTERMASK_U (0x7D3) +#define CSR_MCOUNTEROVF (0x7D4) +#define CSR_DEXC2DBG (0x7E0) +#define CSR_DDCAUSE (0x7E1) +#define CSR_UITB (0x800) +#define CSR_UCODE (0x801) +#define CSR_UDCAUSE (0x809) +#define CSR_UCCTLBEGINADDR (0x80B) +#define CSR_UCCTLCOMMAND (0x80C) +#define CSR_MICM_CFG (0xFC0) +#define CSR_MDCM_CFG (0xFC1) +#define CSR_MMSC_CFG (0xFC2) +#define CSR_MMSC_CFG2 (0xFC3) + +/* STANDARD CRS register bitfiled definitions */ + +/* Bitfield definition for register: USTATUS */ +/* + * UPIE (RW) + * + * UPIE holds the value of the UIE bit prior to a trap. + */ +#define CSR_USTATUS_UPIE_MASK (0x10U) +#define CSR_USTATUS_UPIE_SHIFT (4U) +#define CSR_USTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_USTATUS_UPIE_SHIFT) & CSR_USTATUS_UPIE_MASK) +#define CSR_USTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_USTATUS_UPIE_MASK) >> CSR_USTATUS_UPIE_SHIFT) + +/* + * UIE (RW) + * + * U mode interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_USTATUS_UIE_MASK (0x1U) +#define CSR_USTATUS_UIE_SHIFT (0U) +#define CSR_USTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_USTATUS_UIE_SHIFT) & CSR_USTATUS_UIE_MASK) +#define CSR_USTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_USTATUS_UIE_MASK) >> CSR_USTATUS_UIE_SHIFT) + +/* Bitfield definition for register: UIE */ +/* + * UEIE (RW) + * + * U mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_UIE_UEIE_MASK (0x100U) +#define CSR_UIE_UEIE_SHIFT (8U) +#define CSR_UIE_UEIE_SET(x) (((uint32_t)(x) << CSR_UIE_UEIE_SHIFT) & CSR_UIE_UEIE_MASK) +#define CSR_UIE_UEIE_GET(x) (((uint32_t)(x) & CSR_UIE_UEIE_MASK) >> CSR_UIE_UEIE_SHIFT) + +/* + * UTIE (RW) + * + * U mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_UIE_UTIE_MASK (0x10U) +#define CSR_UIE_UTIE_SHIFT (4U) +#define CSR_UIE_UTIE_SET(x) (((uint32_t)(x) << CSR_UIE_UTIE_SHIFT) & CSR_UIE_UTIE_MASK) +#define CSR_UIE_UTIE_GET(x) (((uint32_t)(x) & CSR_UIE_UTIE_MASK) >> CSR_UIE_UTIE_SHIFT) + +/* + * USIE (RW) + * + * U mode software interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_UIE_USIE_MASK (0x1U) +#define CSR_UIE_USIE_SHIFT (0U) +#define CSR_UIE_USIE_SET(x) (((uint32_t)(x) << CSR_UIE_USIE_SHIFT) & CSR_UIE_USIE_MASK) +#define CSR_UIE_USIE_GET(x) (((uint32_t)(x) & CSR_UIE_USIE_MASK) >> CSR_UIE_USIE_SHIFT) + +/* Bitfield definition for register: UTVEC */ +/* + * BASE_31_2 (RW) + * + * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode. + */ +#define CSR_UTVEC_BASE_31_2_MASK (0xFFFFFFFCUL) +#define CSR_UTVEC_BASE_31_2_SHIFT (2U) +#define CSR_UTVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_UTVEC_BASE_31_2_SHIFT) & CSR_UTVEC_BASE_31_2_MASK) +#define CSR_UTVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_UTVEC_BASE_31_2_MASK) >> CSR_UTVEC_BASE_31_2_SHIFT) + +/* Bitfield definition for register: USCRATCH */ +/* + * USCRATCH (RW) + * + * Scratch register storage. + */ +#define CSR_USCRATCH_USCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_USCRATCH_USCRATCH_SHIFT (0U) +#define CSR_USCRATCH_USCRATCH_SET(x) (((uint32_t)(x) << CSR_USCRATCH_USCRATCH_SHIFT) & CSR_USCRATCH_USCRATCH_MASK) +#define CSR_USCRATCH_USCRATCH_GET(x) (((uint32_t)(x) & CSR_USCRATCH_USCRATCH_MASK) >> CSR_USCRATCH_USCRATCH_SHIFT) + +/* Bitfield definition for register: UEPC */ +/* + * EPC (RW) + * + * Exception program counter. + */ +#define CSR_UEPC_EPC_MASK (0xFFFFFFFEUL) +#define CSR_UEPC_EPC_SHIFT (1U) +#define CSR_UEPC_EPC_SET(x) (((uint32_t)(x) << CSR_UEPC_EPC_SHIFT) & CSR_UEPC_EPC_MASK) +#define CSR_UEPC_EPC_GET(x) (((uint32_t)(x) & CSR_UEPC_EPC_MASK) >> CSR_UEPC_EPC_SHIFT) + +/* Bitfield definition for register: UCAUSE */ +/* + * INTERRUPT (RW) + * + * Interrupt. + */ +#define CSR_UCAUSE_INTERRUPT_MASK (0x80000000UL) +#define CSR_UCAUSE_INTERRUPT_SHIFT (31U) +#define CSR_UCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_UCAUSE_INTERRUPT_SHIFT) & CSR_UCAUSE_INTERRUPT_MASK) +#define CSR_UCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_UCAUSE_INTERRUPT_MASK) >> CSR_UCAUSE_INTERRUPT_SHIFT) + +/* + * EXCEPTION_CODE (RW) + * + * Exception Code. + * When interrupt is 1: + * 0:User software interrupt + * 4:User timer interrupt + * 8:User external interrupt + * When interrupt is 0: + * 0:Instruction address misaligned + * 1:Instruction access fault + * 2:Illegal instruction + * 3:Breakpoint + * 4:Load address misaligned + * 5:Load access fault + * 6:Store/AMO address misaligned + * 7:Store/AMO access fault + * 8:Environment call from U-mode + * 9-11:Reserved + * 12:Instruction page fault + * 13:Load page fault + * 14:Reserved + * 15:Store/AMO page fault + * 32：Stack overflow exception + * 33:Stack underflow exception + * 40-47:Reserved + */ +#define CSR_UCAUSE_EXCEPTION_CODE_MASK (0x3FFU) +#define CSR_UCAUSE_EXCEPTION_CODE_SHIFT (0U) +#define CSR_UCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_UCAUSE_EXCEPTION_CODE_SHIFT) & CSR_UCAUSE_EXCEPTION_CODE_MASK) +#define CSR_UCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_UCAUSE_EXCEPTION_CODE_MASK) >> CSR_UCAUSE_EXCEPTION_CODE_SHIFT) + +/* Bitfield definition for register: UTVAL */ +/* + * UTVAL (RW) + * + * Exception-specific information for software trap handling. + */ +#define CSR_UTVAL_UTVAL_MASK (0xFFFFFFFFUL) +#define CSR_UTVAL_UTVAL_SHIFT (0U) +#define CSR_UTVAL_UTVAL_SET(x) (((uint32_t)(x) << CSR_UTVAL_UTVAL_SHIFT) & CSR_UTVAL_UTVAL_MASK) +#define CSR_UTVAL_UTVAL_GET(x) (((uint32_t)(x) & CSR_UTVAL_UTVAL_MASK) >> CSR_UTVAL_UTVAL_SHIFT) + +/* Bitfield definition for register: UIP */ +/* + * UEIP (RW) + * + * U mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_UIP_UEIP_MASK (0x100U) +#define CSR_UIP_UEIP_SHIFT (8U) +#define CSR_UIP_UEIP_SET(x) (((uint32_t)(x) << CSR_UIP_UEIP_SHIFT) & CSR_UIP_UEIP_MASK) +#define CSR_UIP_UEIP_GET(x) (((uint32_t)(x) & CSR_UIP_UEIP_MASK) >> CSR_UIP_UEIP_SHIFT) + +/* + * UTIP (RW) + * + * U mode timer interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_UIP_UTIP_MASK (0x10U) +#define CSR_UIP_UTIP_SHIFT (4U) +#define CSR_UIP_UTIP_SET(x) (((uint32_t)(x) << CSR_UIP_UTIP_SHIFT) & CSR_UIP_UTIP_MASK) +#define CSR_UIP_UTIP_GET(x) (((uint32_t)(x) & CSR_UIP_UTIP_MASK) >> CSR_UIP_UTIP_SHIFT) + +/* + * USIP (RW) + * + * U mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_UIP_USIP_MASK (0x1U) +#define CSR_UIP_USIP_SHIFT (0U) +#define CSR_UIP_USIP_SET(x) (((uint32_t)(x) << CSR_UIP_USIP_SHIFT) & CSR_UIP_USIP_MASK) +#define CSR_UIP_USIP_GET(x) (((uint32_t)(x) & CSR_UIP_USIP_MASK) >> CSR_UIP_USIP_SHIFT) + +/* Bitfield definition for register: MSTATUS */ +/* + * SD (RO) + * + * SD summarizes whether either the FS field or XS field is dirty. + */ +#define CSR_MSTATUS_SD_MASK (0x80000000UL) +#define CSR_MSTATUS_SD_SHIFT (31U) +#define CSR_MSTATUS_SD_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SD_MASK) >> CSR_MSTATUS_SD_SHIFT) + +/* + * MXR (RW) + * + * MXR controls whether execute-only pages are readable. It has no effect when page-based virtual memory is not in effect + * 0:Execute-only pages are not readable + * 1:Execute-only pages are readable + */ +#define CSR_MSTATUS_MXR_MASK (0x80000UL) +#define CSR_MSTATUS_MXR_SHIFT (19U) +#define CSR_MSTATUS_MXR_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MXR_SHIFT) & CSR_MSTATUS_MXR_MASK) +#define CSR_MSTATUS_MXR_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MXR_MASK) >> CSR_MSTATUS_MXR_SHIFT) + +/* + * MPRV (RW) + * + * When the MPRV bit is set, the memory access privilege for load and store are specified by the MPP field. When U-mode is not available, this field is hardwired to 0. + */ +#define CSR_MSTATUS_MPRV_MASK (0x20000UL) +#define CSR_MSTATUS_MPRV_SHIFT (17U) +#define CSR_MSTATUS_MPRV_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPRV_SHIFT) & CSR_MSTATUS_MPRV_MASK) +#define CSR_MSTATUS_MPRV_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPRV_MASK) >> CSR_MSTATUS_MPRV_SHIFT) + +/* + * XS (RO) + * + * XS holds the status of the architectural states (ACE registers) of ACE instructions. The value of this field is zero if ACE extension is not configured. This field is primarily managed by software. The processor hardware assists the state managements in two regards: + * Illegal instruction exceptions are triggered when XS is Off. + * XS is updated to the Dirty state with the execution of ACE instructions when XS is not Off. Changing the setting of this field has no effect on the contents of ACE states. In particular, setting XS to Off does not destroy the states, nor does setting XS to Initial clear the contents. + * 0:Off + * 1:Initial + * 2:Clean + * 3:Dirty + */ +#define CSR_MSTATUS_XS_MASK (0x18000UL) +#define CSR_MSTATUS_XS_SHIFT (15U) +#define CSR_MSTATUS_XS_GET(x) (((uint32_t)(x) & CSR_MSTATUS_XS_MASK) >> CSR_MSTATUS_XS_SHIFT) + +/* + * FS (RW) + * + * FS holds the status of the architectural states of the floating-point unit, including the fcsr CSR and f0 – f31 floating-point data registers. The value of this field is zero and read-only if the processor does not have FPU. This field is primarily managed by software. The processor hardware assists the state + * managements in two regards: + * Attempts to access fcsr or any f register raise an illegal-instruction exception when FS is Off. + * FS is updated to the Dirty state with the execution of any instruction that updates fcsr or any f register when FS is Initial or Clean. Changing the setting of this field has no effect on the contents of the floating-point register states. In particular, setting FS to Off does not destroy the states, nor does setting FS to Initial clear the contents. + * 0:Off + * 1:Initial + * 2:Clean + * 3:Dirty + */ +#define CSR_MSTATUS_FS_MASK (0x6000U) +#define CSR_MSTATUS_FS_SHIFT (13U) +#define CSR_MSTATUS_FS_SET(x) (((uint32_t)(x) << CSR_MSTATUS_FS_SHIFT) & CSR_MSTATUS_FS_MASK) +#define CSR_MSTATUS_FS_GET(x) (((uint32_t)(x) & CSR_MSTATUS_FS_MASK) >> CSR_MSTATUS_FS_SHIFT) + +/* + * MPP (RW) + * + * MPP holds the privilege mode prior to a trap. Encoding for privilege mode is described in Table5. When U-mode is not available, this field is hardwired to 3. + */ +#define CSR_MSTATUS_MPP_MASK (0x1800U) +#define CSR_MSTATUS_MPP_SHIFT (11U) +#define CSR_MSTATUS_MPP_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPP_SHIFT) & CSR_MSTATUS_MPP_MASK) +#define CSR_MSTATUS_MPP_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPP_MASK) >> CSR_MSTATUS_MPP_SHIFT) + +/* + * MPIE (RW) + * + * MPIE holds the value of the MIE bit prior to a trap. + */ +#define CSR_MSTATUS_MPIE_MASK (0x80U) +#define CSR_MSTATUS_MPIE_SHIFT (7U) +#define CSR_MSTATUS_MPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPIE_SHIFT) & CSR_MSTATUS_MPIE_MASK) +#define CSR_MSTATUS_MPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPIE_MASK) >> CSR_MSTATUS_MPIE_SHIFT) + +/* + * UPIE (RW) + * + * UPIE holds the value of the UIE bit prior to a trap. + */ +#define CSR_MSTATUS_UPIE_MASK (0x10U) +#define CSR_MSTATUS_UPIE_SHIFT (4U) +#define CSR_MSTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_UPIE_SHIFT) & CSR_MSTATUS_UPIE_MASK) +#define CSR_MSTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_UPIE_MASK) >> CSR_MSTATUS_UPIE_SHIFT) + +/* + * MIE (RW) + * + * M mode interrupt enable bit. + * 0: Disabled + * 1: Enabled + */ +#define CSR_MSTATUS_MIE_MASK (0x8U) +#define CSR_MSTATUS_MIE_SHIFT (3U) +#define CSR_MSTATUS_MIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MIE_SHIFT) & CSR_MSTATUS_MIE_MASK) +#define CSR_MSTATUS_MIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MIE_MASK) >> CSR_MSTATUS_MIE_SHIFT) + +/* + * UIE (RW) + * + * U mode interrupt enable bit. + * 0: Disabled + * 1: Enabled + */ +#define CSR_MSTATUS_UIE_MASK (0x1U) +#define CSR_MSTATUS_UIE_SHIFT (0U) +#define CSR_MSTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_UIE_SHIFT) & CSR_MSTATUS_UIE_MASK) +#define CSR_MSTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_UIE_MASK) >> CSR_MSTATUS_UIE_SHIFT) + +/* Bitfield definition for register: MISA */ +/* + * BASE (RO) + * + * The general-purpose register width of the native base integer ISA. + * 0:Reserved + * 1:32 + * 2:64 + * 3:128 + */ +#define CSR_MISA_BASE_MASK (0xC0000000UL) +#define CSR_MISA_BASE_SHIFT (30U) +#define CSR_MISA_BASE_GET(x) (((uint32_t)(x) & CSR_MISA_BASE_MASK) >> CSR_MISA_BASE_SHIFT) + +/* + * Z (RO) + * + * Reserved + */ +#define CSR_MISA_Z_MASK (0x2000000UL) +#define CSR_MISA_Z_SHIFT (25U) +#define CSR_MISA_Z_GET(x) (((uint32_t)(x) & CSR_MISA_Z_MASK) >> CSR_MISA_Z_SHIFT) + +/* + * Y (RO) + * + * Reserved + */ +#define CSR_MISA_Y_MASK (0x1000000UL) +#define CSR_MISA_Y_SHIFT (24U) +#define CSR_MISA_Y_GET(x) (((uint32_t)(x) & CSR_MISA_Y_MASK) >> CSR_MISA_Y_SHIFT) + +/* + * X (RO) + * + * Non-standard extensions present + */ +#define CSR_MISA_X_MASK (0x800000UL) +#define CSR_MISA_X_SHIFT (23U) +#define CSR_MISA_X_GET(x) (((uint32_t)(x) & CSR_MISA_X_MASK) >> CSR_MISA_X_SHIFT) + +/* + * W (RO) + * + * Reserved + */ +#define CSR_MISA_W_MASK (0x400000UL) +#define CSR_MISA_W_SHIFT (22U) +#define CSR_MISA_W_GET(x) (((uint32_t)(x) & CSR_MISA_W_MASK) >> CSR_MISA_W_SHIFT) + +/* + * V (RO) + * + * Tentatively reserved for Vector extension + */ +#define CSR_MISA_V_MASK (0x200000UL) +#define CSR_MISA_V_SHIFT (21U) +#define CSR_MISA_V_GET(x) (((uint32_t)(x) & CSR_MISA_V_MASK) >> CSR_MISA_V_SHIFT) + +/* + * U (RO) + * + * User mode implemented + * 0:Machine + * 1:Machine + User / Machine + Supervisor + User + */ +#define CSR_MISA_U_MASK (0x100000UL) +#define CSR_MISA_U_SHIFT (20U) +#define CSR_MISA_U_GET(x) (((uint32_t)(x) & CSR_MISA_U_MASK) >> CSR_MISA_U_SHIFT) + +/* + * T (RO) + * + * Tentatively reserved for Transactional Memory extension + */ +#define CSR_MISA_T_MASK (0x80000UL) +#define CSR_MISA_T_SHIFT (19U) +#define CSR_MISA_T_GET(x) (((uint32_t)(x) & CSR_MISA_T_MASK) >> CSR_MISA_T_SHIFT) + +/* + * S (RO) + * + * Supervisor mode implemented + * 0:Machine / Machine + User + * 1:Machine + Supervisor + User + */ +#define CSR_MISA_S_MASK (0x40000UL) +#define CSR_MISA_S_SHIFT (18U) +#define CSR_MISA_S_GET(x) (((uint32_t)(x) & CSR_MISA_S_MASK) >> CSR_MISA_S_SHIFT) + +/* + * R (RO) + * + * Reserved + */ +#define CSR_MISA_R_MASK (0x20000UL) +#define CSR_MISA_R_SHIFT (17U) +#define CSR_MISA_R_GET(x) (((uint32_t)(x) & CSR_MISA_R_MASK) >> CSR_MISA_R_SHIFT) + +/* + * Q (RO) + * + * Quad-precision floating-point extension + */ +#define CSR_MISA_Q_MASK (0x10000UL) +#define CSR_MISA_Q_SHIFT (16U) +#define CSR_MISA_Q_GET(x) (((uint32_t)(x) & CSR_MISA_Q_MASK) >> CSR_MISA_Q_SHIFT) + +/* + * P (RO) + * + * Tentatively reserved for Packed-SIMD extension + */ +#define CSR_MISA_P_MASK (0x8000U) +#define CSR_MISA_P_SHIFT (15U) +#define CSR_MISA_P_GET(x) (((uint32_t)(x) & CSR_MISA_P_MASK) >> CSR_MISA_P_SHIFT) + +/* + * O (RO) + * + * Reserved + */ +#define CSR_MISA_O_MASK (0x4000U) +#define CSR_MISA_O_SHIFT (14U) +#define CSR_MISA_O_GET(x) (((uint32_t)(x) & CSR_MISA_O_MASK) >> CSR_MISA_O_SHIFT) + +/* + * N (RO) + * + * User-level interrupts supported + * 0:no + * 1:yes + */ +#define CSR_MISA_N_MASK (0x2000U) +#define CSR_MISA_N_SHIFT (13U) +#define CSR_MISA_N_GET(x) (((uint32_t)(x) & CSR_MISA_N_MASK) >> CSR_MISA_N_SHIFT) + +/* + * M (RO) + * + * Integer Multiply/Divide extension + */ +#define CSR_MISA_M_MASK (0x1000U) +#define CSR_MISA_M_SHIFT (12U) +#define CSR_MISA_M_GET(x) (((uint32_t)(x) & CSR_MISA_M_MASK) >> CSR_MISA_M_SHIFT) + +/* + * L (RO) + * + * Tentatively reserved for Decimal Floating-Point extension + */ +#define CSR_MISA_L_MASK (0x800U) +#define CSR_MISA_L_SHIFT (11U) +#define CSR_MISA_L_GET(x) (((uint32_t)(x) & CSR_MISA_L_MASK) >> CSR_MISA_L_SHIFT) + +/* + * K (RO) + * + * Reserved + */ +#define CSR_MISA_K_MASK (0x400U) +#define CSR_MISA_K_SHIFT (10U) +#define CSR_MISA_K_GET(x) (((uint32_t)(x) & CSR_MISA_K_MASK) >> CSR_MISA_K_SHIFT) + +/* + * J (RO) + * + * Tentatively reserved for Dynamically Translated Languages extension + */ +#define CSR_MISA_J_MASK (0x200U) +#define CSR_MISA_J_SHIFT (9U) +#define CSR_MISA_J_GET(x) (((uint32_t)(x) & CSR_MISA_J_MASK) >> CSR_MISA_J_SHIFT) + +/* + * I (RO) + * + * RV32I/64I/128I base ISA + */ +#define CSR_MISA_I_MASK (0x100U) +#define CSR_MISA_I_SHIFT (8U) +#define CSR_MISA_I_GET(x) (((uint32_t)(x) & CSR_MISA_I_MASK) >> CSR_MISA_I_SHIFT) + +/* + * H (RO) + * + * Reserved + */ +#define CSR_MISA_H_MASK (0x80U) +#define CSR_MISA_H_SHIFT (7U) +#define CSR_MISA_H_GET(x) (((uint32_t)(x) & CSR_MISA_H_MASK) >> CSR_MISA_H_SHIFT) + +/* + * G (RO) + * + * Additional standard extensions present + */ +#define CSR_MISA_G_MASK (0x40U) +#define CSR_MISA_G_SHIFT (6U) +#define CSR_MISA_G_GET(x) (((uint32_t)(x) & CSR_MISA_G_MASK) >> CSR_MISA_G_SHIFT) + +/* + * F (RO) + * + * Single-precision floating-point extension + * 0:none + * 1:double+single precision / single precision + */ +#define CSR_MISA_F_MASK (0x20U) +#define CSR_MISA_F_SHIFT (5U) +#define CSR_MISA_F_GET(x) (((uint32_t)(x) & CSR_MISA_F_MASK) >> CSR_MISA_F_SHIFT) + +/* + * E (RO) + * + * RV32E base ISA + */ +#define CSR_MISA_E_MASK (0x10U) +#define CSR_MISA_E_SHIFT (4U) +#define CSR_MISA_E_GET(x) (((uint32_t)(x) & CSR_MISA_E_MASK) >> CSR_MISA_E_SHIFT) + +/* + * D (RO) + * + * Double-precision floating-point extension + * 0:single precision / none + * 1:double+single precision + */ +#define CSR_MISA_D_MASK (0x8U) +#define CSR_MISA_D_SHIFT (3U) +#define CSR_MISA_D_GET(x) (((uint32_t)(x) & CSR_MISA_D_MASK) >> CSR_MISA_D_SHIFT) + +/* + * C (RO) + * + * Compressed extension + */ +#define CSR_MISA_C_MASK (0x4U) +#define CSR_MISA_C_SHIFT (2U) +#define CSR_MISA_C_GET(x) (((uint32_t)(x) & CSR_MISA_C_MASK) >> CSR_MISA_C_SHIFT) + +/* + * B (RO) + * + * Tentatively reserved for Bit operations extension + */ +#define CSR_MISA_B_MASK (0x2U) +#define CSR_MISA_B_SHIFT (1U) +#define CSR_MISA_B_GET(x) (((uint32_t)(x) & CSR_MISA_B_MASK) >> CSR_MISA_B_SHIFT) + +/* + * A (RO) + * + * Atomic extension + * 0:no + * 1:yes + */ +#define CSR_MISA_A_MASK (0x1U) +#define CSR_MISA_A_SHIFT (0U) +#define CSR_MISA_A_GET(x) (((uint32_t)(x) & CSR_MISA_A_MASK) >> CSR_MISA_A_SHIFT) + +/* Bitfield definition for register: MIE */ +/* + * PMOVI (RW) + * + * Performance monitor overflow local interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_PMOVI_MASK (0x40000UL) +#define CSR_MIE_PMOVI_SHIFT (18U) +#define CSR_MIE_PMOVI_SET(x) (((uint32_t)(x) << CSR_MIE_PMOVI_SHIFT) & CSR_MIE_PMOVI_MASK) +#define CSR_MIE_PMOVI_GET(x) (((uint32_t)(x) & CSR_MIE_PMOVI_MASK) >> CSR_MIE_PMOVI_SHIFT) + +/* + * BWEI (RW) + * + * Bus read/write transaction error local interrupt enable bit. The processor may receive bus errors on load/store instructions or cache writebacks. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_BWEI_MASK (0x20000UL) +#define CSR_MIE_BWEI_SHIFT (17U) +#define CSR_MIE_BWEI_SET(x) (((uint32_t)(x) << CSR_MIE_BWEI_SHIFT) & CSR_MIE_BWEI_MASK) +#define CSR_MIE_BWEI_GET(x) (((uint32_t)(x) & CSR_MIE_BWEI_MASK) >> CSR_MIE_BWEI_SHIFT) + +/* + * IMECCI (RW) + * + * Imprecise ECC error local interrupt enable bit. The processor may receive imprecise ECC errors on slave port accesses or cache writebacks. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_IMECCI_MASK (0x10000UL) +#define CSR_MIE_IMECCI_SHIFT (16U) +#define CSR_MIE_IMECCI_SET(x) (((uint32_t)(x) << CSR_MIE_IMECCI_SHIFT) & CSR_MIE_IMECCI_MASK) +#define CSR_MIE_IMECCI_GET(x) (((uint32_t)(x) & CSR_MIE_IMECCI_MASK) >> CSR_MIE_IMECCI_SHIFT) + +/* + * MEIE (RW) + * + * M mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_MEIE_MASK (0x800U) +#define CSR_MIE_MEIE_SHIFT (11U) +#define CSR_MIE_MEIE_SET(x) (((uint32_t)(x) << CSR_MIE_MEIE_SHIFT) & CSR_MIE_MEIE_MASK) +#define CSR_MIE_MEIE_GET(x) (((uint32_t)(x) & CSR_MIE_MEIE_MASK) >> CSR_MIE_MEIE_SHIFT) + +/* + * UEIE (RW) + * + * U mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_UEIE_MASK (0x100U) +#define CSR_MIE_UEIE_SHIFT (8U) +#define CSR_MIE_UEIE_SET(x) (((uint32_t)(x) << CSR_MIE_UEIE_SHIFT) & CSR_MIE_UEIE_MASK) +#define CSR_MIE_UEIE_GET(x) (((uint32_t)(x) & CSR_MIE_UEIE_MASK) >> CSR_MIE_UEIE_SHIFT) + +/* + * MTIE (RW) + * + * M mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_MTIE_MASK (0x80U) +#define CSR_MIE_MTIE_SHIFT (7U) +#define CSR_MIE_MTIE_SET(x) (((uint32_t)(x) << CSR_MIE_MTIE_SHIFT) & CSR_MIE_MTIE_MASK) +#define CSR_MIE_MTIE_GET(x) (((uint32_t)(x) & CSR_MIE_MTIE_MASK) >> CSR_MIE_MTIE_SHIFT) + +/* + * UTIE (RW) + * + * U mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_UTIE_MASK (0x10U) +#define CSR_MIE_UTIE_SHIFT (4U) +#define CSR_MIE_UTIE_SET(x) (((uint32_t)(x) << CSR_MIE_UTIE_SHIFT) & CSR_MIE_UTIE_MASK) +#define CSR_MIE_UTIE_GET(x) (((uint32_t)(x) & CSR_MIE_UTIE_MASK) >> CSR_MIE_UTIE_SHIFT) + +/* + * MSIE (RW) + * + * M mode software interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_MSIE_MASK (0x8U) +#define CSR_MIE_MSIE_SHIFT (3U) +#define CSR_MIE_MSIE_SET(x) (((uint32_t)(x) << CSR_MIE_MSIE_SHIFT) & CSR_MIE_MSIE_MASK) +#define CSR_MIE_MSIE_GET(x) (((uint32_t)(x) & CSR_MIE_MSIE_MASK) >> CSR_MIE_MSIE_SHIFT) + +/* + * USIE (RW) + * + * U mode software interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_USIE_MASK (0x1U) +#define CSR_MIE_USIE_SHIFT (0U) +#define CSR_MIE_USIE_SET(x) (((uint32_t)(x) << CSR_MIE_USIE_SHIFT) & CSR_MIE_USIE_MASK) +#define CSR_MIE_USIE_GET(x) (((uint32_t)(x) & CSR_MIE_USIE_MASK) >> CSR_MIE_USIE_SHIFT) + +/* Bitfield definition for register: MTVEC */ +/* + * BASE_31_2 (RW) + * + * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode + */ +#define CSR_MTVEC_BASE_31_2_MASK (0xFFFFFFFCUL) +#define CSR_MTVEC_BASE_31_2_SHIFT (2U) +#define CSR_MTVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_MTVEC_BASE_31_2_SHIFT) & CSR_MTVEC_BASE_31_2_MASK) +#define CSR_MTVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_MTVEC_BASE_31_2_MASK) >> CSR_MTVEC_BASE_31_2_SHIFT) + +/* Bitfield definition for register: MCOUNTEREN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_HPM6_MASK (0x40U) +#define CSR_MCOUNTEREN_HPM6_SHIFT (6U) +#define CSR_MCOUNTEREN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM6_SHIFT) & CSR_MCOUNTEREN_HPM6_MASK) +#define CSR_MCOUNTEREN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM6_MASK) >> CSR_MCOUNTEREN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_HPM5_MASK (0x20U) +#define CSR_MCOUNTEREN_HPM5_SHIFT (5U) +#define CSR_MCOUNTEREN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM5_SHIFT) & CSR_MCOUNTEREN_HPM5_MASK) +#define CSR_MCOUNTEREN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM5_MASK) >> CSR_MCOUNTEREN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_HPM4_MASK (0x10U) +#define CSR_MCOUNTEREN_HPM4_SHIFT (4U) +#define CSR_MCOUNTEREN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM4_SHIFT) & CSR_MCOUNTEREN_HPM4_MASK) +#define CSR_MCOUNTEREN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM4_MASK) >> CSR_MCOUNTEREN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_HPM3_MASK (0x8U) +#define CSR_MCOUNTEREN_HPM3_SHIFT (3U) +#define CSR_MCOUNTEREN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM3_SHIFT) & CSR_MCOUNTEREN_HPM3_MASK) +#define CSR_MCOUNTEREN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM3_MASK) >> CSR_MCOUNTEREN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_IR_MASK (0x4U) +#define CSR_MCOUNTEREN_IR_SHIFT (2U) +#define CSR_MCOUNTEREN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_IR_SHIFT) & CSR_MCOUNTEREN_IR_MASK) +#define CSR_MCOUNTEREN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_IR_MASK) >> CSR_MCOUNTEREN_IR_SHIFT) + +/* + * TM (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_TM_MASK (0x2U) +#define CSR_MCOUNTEREN_TM_SHIFT (1U) +#define CSR_MCOUNTEREN_TM_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_TM_SHIFT) & CSR_MCOUNTEREN_TM_MASK) +#define CSR_MCOUNTEREN_TM_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_TM_MASK) >> CSR_MCOUNTEREN_TM_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_CY_MASK (0x1U) +#define CSR_MCOUNTEREN_CY_SHIFT (0U) +#define CSR_MCOUNTEREN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_CY_SHIFT) & CSR_MCOUNTEREN_CY_MASK) +#define CSR_MCOUNTEREN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_CY_MASK) >> CSR_MCOUNTEREN_CY_SHIFT) + +/* Bitfield definition for register: MHPMEVENT3 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT3_SEL_MASK (0x1F0U) +#define CSR_MHPMEVENT3_SEL_SHIFT (4U) +#define CSR_MHPMEVENT3_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT3_SEL_SHIFT) & CSR_MHPMEVENT3_SEL_MASK) +#define CSR_MHPMEVENT3_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT3_SEL_MASK) >> CSR_MHPMEVENT3_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT3_TYPE_MASK (0xFU) +#define CSR_MHPMEVENT3_TYPE_SHIFT (0U) +#define CSR_MHPMEVENT3_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT3_TYPE_SHIFT) & CSR_MHPMEVENT3_TYPE_MASK) +#define CSR_MHPMEVENT3_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT3_TYPE_MASK) >> CSR_MHPMEVENT3_TYPE_SHIFT) + +/* Bitfield definition for register: MHPMEVENT4 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT4_SEL_MASK (0x1F0U) +#define CSR_MHPMEVENT4_SEL_SHIFT (4U) +#define CSR_MHPMEVENT4_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT4_SEL_SHIFT) & CSR_MHPMEVENT4_SEL_MASK) +#define CSR_MHPMEVENT4_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT4_SEL_MASK) >> CSR_MHPMEVENT4_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT4_TYPE_MASK (0xFU) +#define CSR_MHPMEVENT4_TYPE_SHIFT (0U) +#define CSR_MHPMEVENT4_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT4_TYPE_SHIFT) & CSR_MHPMEVENT4_TYPE_MASK) +#define CSR_MHPMEVENT4_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT4_TYPE_MASK) >> CSR_MHPMEVENT4_TYPE_SHIFT) + +/* Bitfield definition for register: MHPMEVENT5 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT5_SEL_MASK (0x1F0U) +#define CSR_MHPMEVENT5_SEL_SHIFT (4U) +#define CSR_MHPMEVENT5_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT5_SEL_SHIFT) & CSR_MHPMEVENT5_SEL_MASK) +#define CSR_MHPMEVENT5_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT5_SEL_MASK) >> CSR_MHPMEVENT5_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT5_TYPE_MASK (0xFU) +#define CSR_MHPMEVENT5_TYPE_SHIFT (0U) +#define CSR_MHPMEVENT5_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT5_TYPE_SHIFT) & CSR_MHPMEVENT5_TYPE_MASK) +#define CSR_MHPMEVENT5_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT5_TYPE_MASK) >> CSR_MHPMEVENT5_TYPE_SHIFT) + +/* Bitfield definition for register: MHPMEVENT6 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT6_SEL_MASK (0x1F0U) +#define CSR_MHPMEVENT6_SEL_SHIFT (4U) +#define CSR_MHPMEVENT6_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT6_SEL_SHIFT) & CSR_MHPMEVENT6_SEL_MASK) +#define CSR_MHPMEVENT6_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT6_SEL_MASK) >> CSR_MHPMEVENT6_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT6_TYPE_MASK (0xFU) +#define CSR_MHPMEVENT6_TYPE_SHIFT (0U) +#define CSR_MHPMEVENT6_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT6_TYPE_SHIFT) & CSR_MHPMEVENT6_TYPE_MASK) +#define CSR_MHPMEVENT6_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT6_TYPE_MASK) >> CSR_MHPMEVENT6_TYPE_SHIFT) + +/* Bitfield definition for register: MSCRATCH */ +/* + * MSCRATCH (RW) + * + * Scratch register storage. + */ +#define CSR_MSCRATCH_MSCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_MSCRATCH_MSCRATCH_SHIFT (0U) +#define CSR_MSCRATCH_MSCRATCH_SET(x) (((uint32_t)(x) << CSR_MSCRATCH_MSCRATCH_SHIFT) & CSR_MSCRATCH_MSCRATCH_MASK) +#define CSR_MSCRATCH_MSCRATCH_GET(x) (((uint32_t)(x) & CSR_MSCRATCH_MSCRATCH_MASK) >> CSR_MSCRATCH_MSCRATCH_SHIFT) + +/* Bitfield definition for register: MEPC */ +/* + * EPC (RW) + * + * Exception program counter. + */ +#define CSR_MEPC_EPC_MASK (0xFFFFFFFEUL) +#define CSR_MEPC_EPC_SHIFT (1U) +#define CSR_MEPC_EPC_SET(x) (((uint32_t)(x) << CSR_MEPC_EPC_SHIFT) & CSR_MEPC_EPC_MASK) +#define CSR_MEPC_EPC_GET(x) (((uint32_t)(x) & CSR_MEPC_EPC_MASK) >> CSR_MEPC_EPC_SHIFT) + +/* Bitfield definition for register: MCAUSE */ +/* + * INTERRUPT (RW) + * + * Interrupt + */ +#define CSR_MCAUSE_INTERRUPT_MASK (0x80000000UL) +#define CSR_MCAUSE_INTERRUPT_SHIFT (31U) +#define CSR_MCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_MCAUSE_INTERRUPT_SHIFT) & CSR_MCAUSE_INTERRUPT_MASK) +#define CSR_MCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_MCAUSE_INTERRUPT_MASK) >> CSR_MCAUSE_INTERRUPT_SHIFT) + +/* + * EXCEPTION_CODE (RW) + * + * Exception code + * When interrupt is 1, the value means: + * 0:User software interrupt + * 1:Supervisor software interrupt + * 3:Machine software interrupt + * 4:User timer interrupt + * 5:Supervisor timer interrupt + * 7:Machine timer interrupt + * 8:User external interrupt + * 9:Supervisor external interrupt + * 11:Machine external interrupt + * 16:Imprecise ECC error interrupt (slave port accesses, D-Cache evictions, and nonblocking load/stores) (M-mode) + * 17:Bus read/write transaction error interrupt (M-mode) + * 18:Performance monitor overflow interrupt (M-mode) + * 256+16:Imprecise ECC error interrupt (slave port accesses, D-Cache evictions, and nonblocking load/stores) (S-mode) + * 256+17:Bus write transaction error interrupt (S-mode) + * 256+18:Performance monitor overflow interrupt (S-mode) + * When interrupt bit is 0, the value means: + * 0:Instruction address misaligned + * 1:Instruction access fault + * 2:Illegal instruction + * 3:Breakpoint + * 4:Load address misaligned + * 5:Load access fault + * 6:Store/AMO address misaligned + * 7:Store/AMO access fault + * 8:Environment call from U-mode + * 9:Environment call from S-mode + * 11:Environment call from M-mode + * 32:Stack overflow exception + * 33:Stack underflow exception + * 40-47:Reserved + */ +#define CSR_MCAUSE_EXCEPTION_CODE_MASK (0xFFFU) +#define CSR_MCAUSE_EXCEPTION_CODE_SHIFT (0U) +#define CSR_MCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_MCAUSE_EXCEPTION_CODE_SHIFT) & CSR_MCAUSE_EXCEPTION_CODE_MASK) +#define CSR_MCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_MCAUSE_EXCEPTION_CODE_MASK) >> CSR_MCAUSE_EXCEPTION_CODE_SHIFT) + +/* Bitfield definition for register: MTVAL */ +/* + * MTVAL (RW) + * + * Exception-specific information for software trap handling. + */ +#define CSR_MTVAL_MTVAL_MASK (0xFFFFFFFFUL) +#define CSR_MTVAL_MTVAL_SHIFT (0U) +#define CSR_MTVAL_MTVAL_SET(x) (((uint32_t)(x) << CSR_MTVAL_MTVAL_SHIFT) & CSR_MTVAL_MTVAL_MASK) +#define CSR_MTVAL_MTVAL_GET(x) (((uint32_t)(x) & CSR_MTVAL_MTVAL_MASK) >> CSR_MTVAL_MTVAL_SHIFT) + +/* Bitfield definition for register: MIP */ +/* + * PMOVI (RW) + * + * Performance monitor overflow local interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_PMOVI_MASK (0x40000UL) +#define CSR_MIP_PMOVI_SHIFT (18U) +#define CSR_MIP_PMOVI_SET(x) (((uint32_t)(x) << CSR_MIP_PMOVI_SHIFT) & CSR_MIP_PMOVI_MASK) +#define CSR_MIP_PMOVI_GET(x) (((uint32_t)(x) & CSR_MIP_PMOVI_MASK) >> CSR_MIP_PMOVI_SHIFT) + +/* + * BWEI (RW) + * + * Bus read/write transaction error local interrupt pending bit. The processor may receive bus errors on load/store instructions or cache writebacks. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_BWEI_MASK (0x20000UL) +#define CSR_MIP_BWEI_SHIFT (17U) +#define CSR_MIP_BWEI_SET(x) (((uint32_t)(x) << CSR_MIP_BWEI_SHIFT) & CSR_MIP_BWEI_MASK) +#define CSR_MIP_BWEI_GET(x) (((uint32_t)(x) & CSR_MIP_BWEI_MASK) >> CSR_MIP_BWEI_SHIFT) + +/* + * IMECCI (RW) + * + * Imprecise ECC error local interrupt enable bit. The processor may receive imprecise ECC errors on slave port accesses or cache writebacks. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_IMECCI_MASK (0x10000UL) +#define CSR_MIP_IMECCI_SHIFT (16U) +#define CSR_MIP_IMECCI_SET(x) (((uint32_t)(x) << CSR_MIP_IMECCI_SHIFT) & CSR_MIP_IMECCI_MASK) +#define CSR_MIP_IMECCI_GET(x) (((uint32_t)(x) & CSR_MIP_IMECCI_MASK) >> CSR_MIP_IMECCI_SHIFT) + +/* + * MEIP (RW) + * + * M mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_MEIP_MASK (0x800U) +#define CSR_MIP_MEIP_SHIFT (11U) +#define CSR_MIP_MEIP_SET(x) (((uint32_t)(x) << CSR_MIP_MEIP_SHIFT) & CSR_MIP_MEIP_MASK) +#define CSR_MIP_MEIP_GET(x) (((uint32_t)(x) & CSR_MIP_MEIP_MASK) >> CSR_MIP_MEIP_SHIFT) + +/* + * SEIP (RW) + * + * S mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_SEIP_MASK (0x200U) +#define CSR_MIP_SEIP_SHIFT (9U) +#define CSR_MIP_SEIP_SET(x) (((uint32_t)(x) << CSR_MIP_SEIP_SHIFT) & CSR_MIP_SEIP_MASK) +#define CSR_MIP_SEIP_GET(x) (((uint32_t)(x) & CSR_MIP_SEIP_MASK) >> CSR_MIP_SEIP_SHIFT) + +/* + * UEIP (RW) + * + * U mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_UEIP_MASK (0x100U) +#define CSR_MIP_UEIP_SHIFT (8U) +#define CSR_MIP_UEIP_SET(x) (((uint32_t)(x) << CSR_MIP_UEIP_SHIFT) & CSR_MIP_UEIP_MASK) +#define CSR_MIP_UEIP_GET(x) (((uint32_t)(x) & CSR_MIP_UEIP_MASK) >> CSR_MIP_UEIP_SHIFT) + +/* + * MTIP (RW) + * + * M mode timer interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_MTIP_MASK (0x80U) +#define CSR_MIP_MTIP_SHIFT (7U) +#define CSR_MIP_MTIP_SET(x) (((uint32_t)(x) << CSR_MIP_MTIP_SHIFT) & CSR_MIP_MTIP_MASK) +#define CSR_MIP_MTIP_GET(x) (((uint32_t)(x) & CSR_MIP_MTIP_MASK) >> CSR_MIP_MTIP_SHIFT) + +/* + * STIP (RW) + * + * S mode timer interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_STIP_MASK (0x20U) +#define CSR_MIP_STIP_SHIFT (5U) +#define CSR_MIP_STIP_SET(x) (((uint32_t)(x) << CSR_MIP_STIP_SHIFT) & CSR_MIP_STIP_MASK) +#define CSR_MIP_STIP_GET(x) (((uint32_t)(x) & CSR_MIP_STIP_MASK) >> CSR_MIP_STIP_SHIFT) + +/* + * UTIP (RW) + * + * U mode timer interrupt pending bit + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_UTIP_MASK (0x10U) +#define CSR_MIP_UTIP_SHIFT (4U) +#define CSR_MIP_UTIP_SET(x) (((uint32_t)(x) << CSR_MIP_UTIP_SHIFT) & CSR_MIP_UTIP_MASK) +#define CSR_MIP_UTIP_GET(x) (((uint32_t)(x) & CSR_MIP_UTIP_MASK) >> CSR_MIP_UTIP_SHIFT) + +/* + * MSIP (RW) + * + * M mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_MSIP_MASK (0x8U) +#define CSR_MIP_MSIP_SHIFT (3U) +#define CSR_MIP_MSIP_SET(x) (((uint32_t)(x) << CSR_MIP_MSIP_SHIFT) & CSR_MIP_MSIP_MASK) +#define CSR_MIP_MSIP_GET(x) (((uint32_t)(x) & CSR_MIP_MSIP_MASK) >> CSR_MIP_MSIP_SHIFT) + +/* + * SSIP (RW) + * + * S mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_SSIP_MASK (0x2U) +#define CSR_MIP_SSIP_SHIFT (1U) +#define CSR_MIP_SSIP_SET(x) (((uint32_t)(x) << CSR_MIP_SSIP_SHIFT) & CSR_MIP_SSIP_MASK) +#define CSR_MIP_SSIP_GET(x) (((uint32_t)(x) & CSR_MIP_SSIP_MASK) >> CSR_MIP_SSIP_SHIFT) + +/* + * USIP (RW) + * + * U mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_USIP_MASK (0x1U) +#define CSR_MIP_USIP_SHIFT (0U) +#define CSR_MIP_USIP_SET(x) (((uint32_t)(x) << CSR_MIP_USIP_SHIFT) & CSR_MIP_USIP_MASK) +#define CSR_MIP_USIP_GET(x) (((uint32_t)(x) & CSR_MIP_USIP_MASK) >> CSR_MIP_USIP_SHIFT) + +/* Bitfield definition for register: PMPCFG0 */ +/* + * PMP3CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG0_PMP3CFG_MASK (0xFF000000UL) +#define CSR_PMPCFG0_PMP3CFG_SHIFT (24U) +#define CSR_PMPCFG0_PMP3CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP3CFG_SHIFT) & CSR_PMPCFG0_PMP3CFG_MASK) +#define CSR_PMPCFG0_PMP3CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP3CFG_MASK) >> CSR_PMPCFG0_PMP3CFG_SHIFT) + +/* + * PMP2CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG0_PMP2CFG_MASK (0xFF0000UL) +#define CSR_PMPCFG0_PMP2CFG_SHIFT (16U) +#define CSR_PMPCFG0_PMP2CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP2CFG_SHIFT) & CSR_PMPCFG0_PMP2CFG_MASK) +#define CSR_PMPCFG0_PMP2CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP2CFG_MASK) >> CSR_PMPCFG0_PMP2CFG_SHIFT) + +/* + * PMP1CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG0_PMP1CFG_MASK (0xFF00U) +#define CSR_PMPCFG0_PMP1CFG_SHIFT (8U) +#define CSR_PMPCFG0_PMP1CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP1CFG_SHIFT) & CSR_PMPCFG0_PMP1CFG_MASK) +#define CSR_PMPCFG0_PMP1CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP1CFG_MASK) >> CSR_PMPCFG0_PMP1CFG_SHIFT) + +/* + * PMP0CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG0_PMP0CFG_MASK (0xFFU) +#define CSR_PMPCFG0_PMP0CFG_SHIFT (0U) +#define CSR_PMPCFG0_PMP0CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP0CFG_SHIFT) & CSR_PMPCFG0_PMP0CFG_MASK) +#define CSR_PMPCFG0_PMP0CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP0CFG_MASK) >> CSR_PMPCFG0_PMP0CFG_SHIFT) + +/* Bitfield definition for register: PMPCFG1 */ +/* + * PMP7CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG1_PMP7CFG_MASK (0xFF000000UL) +#define CSR_PMPCFG1_PMP7CFG_SHIFT (24U) +#define CSR_PMPCFG1_PMP7CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP7CFG_SHIFT) & CSR_PMPCFG1_PMP7CFG_MASK) +#define CSR_PMPCFG1_PMP7CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP7CFG_MASK) >> CSR_PMPCFG1_PMP7CFG_SHIFT) + +/* + * PMP6CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG1_PMP6CFG_MASK (0xFF0000UL) +#define CSR_PMPCFG1_PMP6CFG_SHIFT (16U) +#define CSR_PMPCFG1_PMP6CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP6CFG_SHIFT) & CSR_PMPCFG1_PMP6CFG_MASK) +#define CSR_PMPCFG1_PMP6CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP6CFG_MASK) >> CSR_PMPCFG1_PMP6CFG_SHIFT) + +/* + * PMP5CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG1_PMP5CFG_MASK (0xFF00U) +#define CSR_PMPCFG1_PMP5CFG_SHIFT (8U) +#define CSR_PMPCFG1_PMP5CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP5CFG_SHIFT) & CSR_PMPCFG1_PMP5CFG_MASK) +#define CSR_PMPCFG1_PMP5CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP5CFG_MASK) >> CSR_PMPCFG1_PMP5CFG_SHIFT) + +/* + * PMP4CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG1_PMP4CFG_MASK (0xFFU) +#define CSR_PMPCFG1_PMP4CFG_SHIFT (0U) +#define CSR_PMPCFG1_PMP4CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP4CFG_SHIFT) & CSR_PMPCFG1_PMP4CFG_MASK) +#define CSR_PMPCFG1_PMP4CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP4CFG_MASK) >> CSR_PMPCFG1_PMP4CFG_SHIFT) + +/* Bitfield definition for register: PMPCFG2 */ +/* + * PMP11CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG2_PMP11CFG_MASK (0xFF000000UL) +#define CSR_PMPCFG2_PMP11CFG_SHIFT (24U) +#define CSR_PMPCFG2_PMP11CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP11CFG_SHIFT) & CSR_PMPCFG2_PMP11CFG_MASK) +#define CSR_PMPCFG2_PMP11CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP11CFG_MASK) >> CSR_PMPCFG2_PMP11CFG_SHIFT) + +/* + * PMP10CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG2_PMP10CFG_MASK (0xFF0000UL) +#define CSR_PMPCFG2_PMP10CFG_SHIFT (16U) +#define CSR_PMPCFG2_PMP10CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP10CFG_SHIFT) & CSR_PMPCFG2_PMP10CFG_MASK) +#define CSR_PMPCFG2_PMP10CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP10CFG_MASK) >> CSR_PMPCFG2_PMP10CFG_SHIFT) + +/* + * PMP9CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG2_PMP9CFG_MASK (0xFF00U) +#define CSR_PMPCFG2_PMP9CFG_SHIFT (8U) +#define CSR_PMPCFG2_PMP9CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP9CFG_SHIFT) & CSR_PMPCFG2_PMP9CFG_MASK) +#define CSR_PMPCFG2_PMP9CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP9CFG_MASK) >> CSR_PMPCFG2_PMP9CFG_SHIFT) + +/* + * PMP8CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG2_PMP8CFG_MASK (0xFFU) +#define CSR_PMPCFG2_PMP8CFG_SHIFT (0U) +#define CSR_PMPCFG2_PMP8CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP8CFG_SHIFT) & CSR_PMPCFG2_PMP8CFG_MASK) +#define CSR_PMPCFG2_PMP8CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP8CFG_MASK) >> CSR_PMPCFG2_PMP8CFG_SHIFT) + +/* Bitfield definition for register: PMPCFG3 */ +/* + * PMP15CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG3_PMP15CFG_MASK (0xFF000000UL) +#define CSR_PMPCFG3_PMP15CFG_SHIFT (24U) +#define CSR_PMPCFG3_PMP15CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP15CFG_SHIFT) & CSR_PMPCFG3_PMP15CFG_MASK) +#define CSR_PMPCFG3_PMP15CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP15CFG_MASK) >> CSR_PMPCFG3_PMP15CFG_SHIFT) + +/* + * PMP14CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG3_PMP14CFG_MASK (0xFF0000UL) +#define CSR_PMPCFG3_PMP14CFG_SHIFT (16U) +#define CSR_PMPCFG3_PMP14CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP14CFG_SHIFT) & CSR_PMPCFG3_PMP14CFG_MASK) +#define CSR_PMPCFG3_PMP14CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP14CFG_MASK) >> CSR_PMPCFG3_PMP14CFG_SHIFT) + +/* + * PMP13CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG3_PMP13CFG_MASK (0xFF00U) +#define CSR_PMPCFG3_PMP13CFG_SHIFT (8U) +#define CSR_PMPCFG3_PMP13CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP13CFG_SHIFT) & CSR_PMPCFG3_PMP13CFG_MASK) +#define CSR_PMPCFG3_PMP13CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP13CFG_MASK) >> CSR_PMPCFG3_PMP13CFG_SHIFT) + +/* + * PMP12CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG3_PMP12CFG_MASK (0xFFU) +#define CSR_PMPCFG3_PMP12CFG_SHIFT (0U) +#define CSR_PMPCFG3_PMP12CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP12CFG_SHIFT) & CSR_PMPCFG3_PMP12CFG_MASK) +#define CSR_PMPCFG3_PMP12CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP12CFG_MASK) >> CSR_PMPCFG3_PMP12CFG_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * Register Content : Match Size(Byte) + * aaaa. . . aaa0 8 + * aaaa. . . aa01 16 + * aaaa. . . a011 32 + * . . . . . . + * aa01. . . 1111 2^{XLEN} + * a011. . . 1111 2^{XLEN+1} + * 0111. . . 1111 2^{XLEN+2} + * 1111. . . 1111 2^{XLEN+3*1} + */ +#define CSR_PMPADDR0_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR0_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR0_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR0_PMPADDR_31_2_SHIFT) & CSR_PMPADDR0_PMPADDR_31_2_MASK) +#define CSR_PMPADDR0_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR0_PMPADDR_31_2_MASK) >> CSR_PMPADDR0_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR1_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR1_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR1_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR1_PMPADDR_31_2_SHIFT) & CSR_PMPADDR1_PMPADDR_31_2_MASK) +#define CSR_PMPADDR1_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR1_PMPADDR_31_2_MASK) >> CSR_PMPADDR1_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR2_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR2_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR2_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR2_PMPADDR_31_2_SHIFT) & CSR_PMPADDR2_PMPADDR_31_2_MASK) +#define CSR_PMPADDR2_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR2_PMPADDR_31_2_MASK) >> CSR_PMPADDR2_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR3_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR3_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR3_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR3_PMPADDR_31_2_SHIFT) & CSR_PMPADDR3_PMPADDR_31_2_MASK) +#define CSR_PMPADDR3_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR3_PMPADDR_31_2_MASK) >> CSR_PMPADDR3_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR4_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR4_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR4_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR4_PMPADDR_31_2_SHIFT) & CSR_PMPADDR4_PMPADDR_31_2_MASK) +#define CSR_PMPADDR4_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR4_PMPADDR_31_2_MASK) >> CSR_PMPADDR4_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR5_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR5_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR5_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR5_PMPADDR_31_2_SHIFT) & CSR_PMPADDR5_PMPADDR_31_2_MASK) +#define CSR_PMPADDR5_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR5_PMPADDR_31_2_MASK) >> CSR_PMPADDR5_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR6_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR6_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR6_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR6_PMPADDR_31_2_SHIFT) & CSR_PMPADDR6_PMPADDR_31_2_MASK) +#define CSR_PMPADDR6_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR6_PMPADDR_31_2_MASK) >> CSR_PMPADDR6_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR7_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR7_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR7_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR7_PMPADDR_31_2_SHIFT) & CSR_PMPADDR7_PMPADDR_31_2_MASK) +#define CSR_PMPADDR7_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR7_PMPADDR_31_2_MASK) >> CSR_PMPADDR7_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR8_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR8_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR8_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR8_PMPADDR_31_2_SHIFT) & CSR_PMPADDR8_PMPADDR_31_2_MASK) +#define CSR_PMPADDR8_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR8_PMPADDR_31_2_MASK) >> CSR_PMPADDR8_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR9_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR9_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR9_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR9_PMPADDR_31_2_SHIFT) & CSR_PMPADDR9_PMPADDR_31_2_MASK) +#define CSR_PMPADDR9_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR9_PMPADDR_31_2_MASK) >> CSR_PMPADDR9_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR10_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR10_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR10_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR10_PMPADDR_31_2_SHIFT) & CSR_PMPADDR10_PMPADDR_31_2_MASK) +#define CSR_PMPADDR10_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR10_PMPADDR_31_2_MASK) >> CSR_PMPADDR10_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR11_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR11_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR11_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR11_PMPADDR_31_2_SHIFT) & CSR_PMPADDR11_PMPADDR_31_2_MASK) +#define CSR_PMPADDR11_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR11_PMPADDR_31_2_MASK) >> CSR_PMPADDR11_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR12_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR12_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR12_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR12_PMPADDR_31_2_SHIFT) & CSR_PMPADDR12_PMPADDR_31_2_MASK) +#define CSR_PMPADDR12_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR12_PMPADDR_31_2_MASK) >> CSR_PMPADDR12_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR13_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR13_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR13_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR13_PMPADDR_31_2_SHIFT) & CSR_PMPADDR13_PMPADDR_31_2_MASK) +#define CSR_PMPADDR13_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR13_PMPADDR_31_2_MASK) >> CSR_PMPADDR13_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR14_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR14_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR14_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR14_PMPADDR_31_2_SHIFT) & CSR_PMPADDR14_PMPADDR_31_2_MASK) +#define CSR_PMPADDR14_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR14_PMPADDR_31_2_MASK) >> CSR_PMPADDR14_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR15_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR15_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR15_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR15_PMPADDR_31_2_SHIFT) & CSR_PMPADDR15_PMPADDR_31_2_MASK) +#define CSR_PMPADDR15_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR15_PMPADDR_31_2_MASK) >> CSR_PMPADDR15_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register: TSELECT */ +/* + * TRIGGER_INDEX (RW) + * + * This register determines which trigger is accessible through other trigger registers. + */ +#define CSR_TSELECT_TRIGGER_INDEX_MASK (0xFFFFFFFFUL) +#define CSR_TSELECT_TRIGGER_INDEX_SHIFT (0U) +#define CSR_TSELECT_TRIGGER_INDEX_SET(x) (((uint32_t)(x) << CSR_TSELECT_TRIGGER_INDEX_SHIFT) & CSR_TSELECT_TRIGGER_INDEX_MASK) +#define CSR_TSELECT_TRIGGER_INDEX_GET(x) (((uint32_t)(x) & CSR_TSELECT_TRIGGER_INDEX_MASK) >> CSR_TSELECT_TRIGGER_INDEX_SHIFT) + +/* Bitfield definition for register: TDATA1 */ +/* + * TYPE (RW) + * + * Indicates the trigger type. + * 0:The selected trigger is invalid. + * 2:The selected trigger is an address/data match trigger. + * 3:The selected trigger is an instruction count trigger + * 4:The selected trigger is an interrupt trigger. + * 5:The selected trigger is an exception trigger. + */ +#define CSR_TDATA1_TYPE_MASK (0xF0000000UL) +#define CSR_TDATA1_TYPE_SHIFT (28U) +#define CSR_TDATA1_TYPE_SET(x) (((uint32_t)(x) << CSR_TDATA1_TYPE_SHIFT) & CSR_TDATA1_TYPE_MASK) +#define CSR_TDATA1_TYPE_GET(x) (((uint32_t)(x) & CSR_TDATA1_TYPE_MASK) >> CSR_TDATA1_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_TDATA1_DMODE_MASK (0x8000000UL) +#define CSR_TDATA1_DMODE_SHIFT (27U) +#define CSR_TDATA1_DMODE_SET(x) (((uint32_t)(x) << CSR_TDATA1_DMODE_SHIFT) & CSR_TDATA1_DMODE_MASK) +#define CSR_TDATA1_DMODE_GET(x) (((uint32_t)(x) & CSR_TDATA1_DMODE_MASK) >> CSR_TDATA1_DMODE_SHIFT) + +/* + * DATA (RW) + * + * Trigger-specific data + */ +#define CSR_TDATA1_DATA_MASK (0x7FFFFFFUL) +#define CSR_TDATA1_DATA_SHIFT (0U) +#define CSR_TDATA1_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA1_DATA_SHIFT) & CSR_TDATA1_DATA_MASK) +#define CSR_TDATA1_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA1_DATA_MASK) >> CSR_TDATA1_DATA_SHIFT) + +/* Bitfield definition for register: MCONTROL */ +/* + * TYPE (RW) + * + * Indicates the trigger type. + * 0:The selected trigger is invalid. + * 2:The selected trigger is an address/data match trigger. + */ +#define CSR_MCONTROL_TYPE_MASK (0xF0000000UL) +#define CSR_MCONTROL_TYPE_SHIFT (28U) +#define CSR_MCONTROL_TYPE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_TYPE_SHIFT) & CSR_MCONTROL_TYPE_MASK) +#define CSR_MCONTROL_TYPE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_TYPE_MASK) >> CSR_MCONTROL_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_MCONTROL_DMODE_MASK (0x8000000UL) +#define CSR_MCONTROL_DMODE_SHIFT (27U) +#define CSR_MCONTROL_DMODE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_DMODE_SHIFT) & CSR_MCONTROL_DMODE_MASK) +#define CSR_MCONTROL_DMODE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_DMODE_MASK) >> CSR_MCONTROL_DMODE_SHIFT) + +/* + * MASKMAX (RO) + * + * Indicates the largest naturally aligned range supported by the hardware is 2ˆ12 bytes. + */ +#define CSR_MCONTROL_MASKMAX_MASK (0x7E00000UL) +#define CSR_MCONTROL_MASKMAX_SHIFT (21U) +#define CSR_MCONTROL_MASKMAX_GET(x) (((uint32_t)(x) & CSR_MCONTROL_MASKMAX_MASK) >> CSR_MCONTROL_MASKMAX_SHIFT) + +/* + * ACTION (RW) + * + * Setting this field to select what happens when this trigger matches. + * 0:Raise a breakpoint exception + * 1:Enter Debug Mode. (Only supported when DMODE is 1.) + */ +#define CSR_MCONTROL_ACTION_MASK (0xF000U) +#define CSR_MCONTROL_ACTION_SHIFT (12U) +#define CSR_MCONTROL_ACTION_SET(x) (((uint32_t)(x) << CSR_MCONTROL_ACTION_SHIFT) & CSR_MCONTROL_ACTION_MASK) +#define CSR_MCONTROL_ACTION_GET(x) (((uint32_t)(x) & CSR_MCONTROL_ACTION_MASK) >> CSR_MCONTROL_ACTION_SHIFT) + +/* + * CHAIN (RW) + * + * Setting this field to enable trigger chain. + * 0:When this trigger matches, the configured action is taken. + * 1:While this trigger does not match, it prevents the trigger with the next index from matching. + * If Number of Triggers is 2, this field is hardwired to 0 on trigger 1 (tselect = 1). + * If Number of Triggers is 4, this field is hardwired + * to 0 on trigger 3 (tselect = 3). + * If Number of Triggers is 8, this field is hardwired to 0 on trigger 3 and trigger 7 (tselect = 3 or 7). + */ +#define CSR_MCONTROL_CHAIN_MASK (0x800U) +#define CSR_MCONTROL_CHAIN_SHIFT (11U) +#define CSR_MCONTROL_CHAIN_SET(x) (((uint32_t)(x) << CSR_MCONTROL_CHAIN_SHIFT) & CSR_MCONTROL_CHAIN_MASK) +#define CSR_MCONTROL_CHAIN_GET(x) (((uint32_t)(x) & CSR_MCONTROL_CHAIN_MASK) >> CSR_MCONTROL_CHAIN_SHIFT) + +/* + * MATCH (RW) + * + * Setting this field to select the matching scheme. 0:Matches when the value equals tdata2. 1:Matches when the top M bits of the value match the top M bits of tdata2. M is 31 minus the index of the least-significant bit containing 0 in tdata2. + * 2:Matches when the value is greater than (unsigned) or equal to tdata2. + * 3:Matches when the value is less than (unsigned) tdata2 + */ +#define CSR_MCONTROL_MATCH_MASK (0x780U) +#define CSR_MCONTROL_MATCH_SHIFT (7U) +#define CSR_MCONTROL_MATCH_SET(x) (((uint32_t)(x) << CSR_MCONTROL_MATCH_SHIFT) & CSR_MCONTROL_MATCH_MASK) +#define CSR_MCONTROL_MATCH_GET(x) (((uint32_t)(x) & CSR_MCONTROL_MATCH_MASK) >> CSR_MCONTROL_MATCH_SHIFT) + +/* + * M (RW) + * + * Setting this field to enable this trigger in M-mode. + */ +#define CSR_MCONTROL_M_MASK (0x40U) +#define CSR_MCONTROL_M_SHIFT (6U) +#define CSR_MCONTROL_M_SET(x) (((uint32_t)(x) << CSR_MCONTROL_M_SHIFT) & CSR_MCONTROL_M_MASK) +#define CSR_MCONTROL_M_GET(x) (((uint32_t)(x) & CSR_MCONTROL_M_MASK) >> CSR_MCONTROL_M_SHIFT) + +/* + * U (RW) + * + * Setting this field to enable this trigger in U-mode. + */ +#define CSR_MCONTROL_U_MASK (0x8U) +#define CSR_MCONTROL_U_SHIFT (3U) +#define CSR_MCONTROL_U_SET(x) (((uint32_t)(x) << CSR_MCONTROL_U_SHIFT) & CSR_MCONTROL_U_MASK) +#define CSR_MCONTROL_U_GET(x) (((uint32_t)(x) & CSR_MCONTROL_U_MASK) >> CSR_MCONTROL_U_SHIFT) + +/* + * EXECUTE (RW) + * + * Setting this field to enable this trigger to compare virtual address of an instruction. + */ +#define CSR_MCONTROL_EXECUTE_MASK (0x4U) +#define CSR_MCONTROL_EXECUTE_SHIFT (2U) +#define CSR_MCONTROL_EXECUTE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_EXECUTE_SHIFT) & CSR_MCONTROL_EXECUTE_MASK) +#define CSR_MCONTROL_EXECUTE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_EXECUTE_MASK) >> CSR_MCONTROL_EXECUTE_SHIFT) + +/* + * STORE (RW) + * + * Setting this field to enable this trigger to compare virtual address of a store. + */ +#define CSR_MCONTROL_STORE_MASK (0x2U) +#define CSR_MCONTROL_STORE_SHIFT (1U) +#define CSR_MCONTROL_STORE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_STORE_SHIFT) & CSR_MCONTROL_STORE_MASK) +#define CSR_MCONTROL_STORE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_STORE_MASK) >> CSR_MCONTROL_STORE_SHIFT) + +/* + * LOAD (RW) + * + * Setting this field to enable this trigger to compare virtual address of a load. + */ +#define CSR_MCONTROL_LOAD_MASK (0x1U) +#define CSR_MCONTROL_LOAD_SHIFT (0U) +#define CSR_MCONTROL_LOAD_SET(x) (((uint32_t)(x) << CSR_MCONTROL_LOAD_SHIFT) & CSR_MCONTROL_LOAD_MASK) +#define CSR_MCONTROL_LOAD_GET(x) (((uint32_t)(x) & CSR_MCONTROL_LOAD_MASK) >> CSR_MCONTROL_LOAD_SHIFT) + +/* Bitfield definition for register: ICOUNT */ +/* + * TYPE (RW) + * + * The selected trigger is an instruction count trigger. + */ +#define CSR_ICOUNT_TYPE_MASK (0xF0000000UL) +#define CSR_ICOUNT_TYPE_SHIFT (28U) +#define CSR_ICOUNT_TYPE_SET(x) (((uint32_t)(x) << CSR_ICOUNT_TYPE_SHIFT) & CSR_ICOUNT_TYPE_MASK) +#define CSR_ICOUNT_TYPE_GET(x) (((uint32_t)(x) & CSR_ICOUNT_TYPE_MASK) >> CSR_ICOUNT_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_ICOUNT_DMODE_MASK (0x8000000UL) +#define CSR_ICOUNT_DMODE_SHIFT (27U) +#define CSR_ICOUNT_DMODE_SET(x) (((uint32_t)(x) << CSR_ICOUNT_DMODE_SHIFT) & CSR_ICOUNT_DMODE_MASK) +#define CSR_ICOUNT_DMODE_GET(x) (((uint32_t)(x) & CSR_ICOUNT_DMODE_MASK) >> CSR_ICOUNT_DMODE_SHIFT) + +/* + * COUNT (RO) + * + * This field is hardwired to 1 for single-stepping support + */ +#define CSR_ICOUNT_COUNT_MASK (0x400U) +#define CSR_ICOUNT_COUNT_SHIFT (10U) +#define CSR_ICOUNT_COUNT_GET(x) (((uint32_t)(x) & CSR_ICOUNT_COUNT_MASK) >> CSR_ICOUNT_COUNT_SHIFT) + +/* + * M (RW) + * + * Setting this field to enable this trigger in M-mode. + */ +#define CSR_ICOUNT_M_MASK (0x200U) +#define CSR_ICOUNT_M_SHIFT (9U) +#define CSR_ICOUNT_M_SET(x) (((uint32_t)(x) << CSR_ICOUNT_M_SHIFT) & CSR_ICOUNT_M_MASK) +#define CSR_ICOUNT_M_GET(x) (((uint32_t)(x) & CSR_ICOUNT_M_MASK) >> CSR_ICOUNT_M_SHIFT) + +/* + * U (RW) + * + * Setting this field to enable this trigger in U-mode. + */ +#define CSR_ICOUNT_U_MASK (0x40U) +#define CSR_ICOUNT_U_SHIFT (6U) +#define CSR_ICOUNT_U_SET(x) (((uint32_t)(x) << CSR_ICOUNT_U_SHIFT) & CSR_ICOUNT_U_MASK) +#define CSR_ICOUNT_U_GET(x) (((uint32_t)(x) & CSR_ICOUNT_U_MASK) >> CSR_ICOUNT_U_SHIFT) + +/* + * ACTION (RW) + * + * Setting this field to select what happens when this trigger matches. + * 0:Raise a breakpoint exception + * 1:Enter Debug Mode. (Only supported when DMODE is 1.) + */ +#define CSR_ICOUNT_ACTION_MASK (0x3FU) +#define CSR_ICOUNT_ACTION_SHIFT (0U) +#define CSR_ICOUNT_ACTION_SET(x) (((uint32_t)(x) << CSR_ICOUNT_ACTION_SHIFT) & CSR_ICOUNT_ACTION_MASK) +#define CSR_ICOUNT_ACTION_GET(x) (((uint32_t)(x) & CSR_ICOUNT_ACTION_MASK) >> CSR_ICOUNT_ACTION_SHIFT) + +/* Bitfield definition for register: ITRIGGER */ +/* + * TYPE (RW) + * + * The selected trigger is an interrupt trigger. + */ +#define CSR_ITRIGGER_TYPE_MASK (0xF0000000UL) +#define CSR_ITRIGGER_TYPE_SHIFT (28U) +#define CSR_ITRIGGER_TYPE_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_TYPE_SHIFT) & CSR_ITRIGGER_TYPE_MASK) +#define CSR_ITRIGGER_TYPE_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_TYPE_MASK) >> CSR_ITRIGGER_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_ITRIGGER_DMODE_MASK (0x8000000UL) +#define CSR_ITRIGGER_DMODE_SHIFT (27U) +#define CSR_ITRIGGER_DMODE_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_DMODE_SHIFT) & CSR_ITRIGGER_DMODE_MASK) +#define CSR_ITRIGGER_DMODE_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_DMODE_MASK) >> CSR_ITRIGGER_DMODE_SHIFT) + +/* + * M (RW) + * + * Setting this field to enable this trigger in M-mode. + */ +#define CSR_ITRIGGER_M_MASK (0x200U) +#define CSR_ITRIGGER_M_SHIFT (9U) +#define CSR_ITRIGGER_M_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_M_SHIFT) & CSR_ITRIGGER_M_MASK) +#define CSR_ITRIGGER_M_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_M_MASK) >> CSR_ITRIGGER_M_SHIFT) + +/* + * U (RW) + * + * Setting this field to enable this trigger in U-mode. + */ +#define CSR_ITRIGGER_U_MASK (0x40U) +#define CSR_ITRIGGER_U_SHIFT (6U) +#define CSR_ITRIGGER_U_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_U_SHIFT) & CSR_ITRIGGER_U_MASK) +#define CSR_ITRIGGER_U_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_U_MASK) >> CSR_ITRIGGER_U_SHIFT) + +/* + * ACTION (RW) + * + * Setting this field to select what happens when this trigger matches. + * 0:Raise a breakpoint exception. + * 1:Enter Debug Mode. (Only supported when DMODE is 1.) + */ +#define CSR_ITRIGGER_ACTION_MASK (0x3FU) +#define CSR_ITRIGGER_ACTION_SHIFT (0U) +#define CSR_ITRIGGER_ACTION_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_ACTION_SHIFT) & CSR_ITRIGGER_ACTION_MASK) +#define CSR_ITRIGGER_ACTION_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_ACTION_MASK) >> CSR_ITRIGGER_ACTION_SHIFT) + +/* Bitfield definition for register: ETRIGGER */ +/* + * TYPE (RW) + * + * The selected trigger is an exception trigger. + */ +#define CSR_ETRIGGER_TYPE_MASK (0xF0000000UL) +#define CSR_ETRIGGER_TYPE_SHIFT (28U) +#define CSR_ETRIGGER_TYPE_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_TYPE_SHIFT) & CSR_ETRIGGER_TYPE_MASK) +#define CSR_ETRIGGER_TYPE_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_TYPE_MASK) >> CSR_ETRIGGER_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_ETRIGGER_DMODE_MASK (0x8000000UL) +#define CSR_ETRIGGER_DMODE_SHIFT (27U) +#define CSR_ETRIGGER_DMODE_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_DMODE_SHIFT) & CSR_ETRIGGER_DMODE_MASK) +#define CSR_ETRIGGER_DMODE_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_DMODE_MASK) >> CSR_ETRIGGER_DMODE_SHIFT) + +/* + * NMI (RW) + * + * Setting this field to enable this trigger in non-maskable interrupts, regardless of the values of s, u, and m. + */ +#define CSR_ETRIGGER_NMI_MASK (0x400U) +#define CSR_ETRIGGER_NMI_SHIFT (10U) +#define CSR_ETRIGGER_NMI_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_NMI_SHIFT) & CSR_ETRIGGER_NMI_MASK) +#define CSR_ETRIGGER_NMI_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_NMI_MASK) >> CSR_ETRIGGER_NMI_SHIFT) + +/* + * M (RW) + * + * Setting this field to enable this trigger in M-mode. + */ +#define CSR_ETRIGGER_M_MASK (0x200U) +#define CSR_ETRIGGER_M_SHIFT (9U) +#define CSR_ETRIGGER_M_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_M_SHIFT) & CSR_ETRIGGER_M_MASK) +#define CSR_ETRIGGER_M_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_M_MASK) >> CSR_ETRIGGER_M_SHIFT) + +/* + * U (RW) + * + * Setting this field to enable this trigger in U-mode. + */ +#define CSR_ETRIGGER_U_MASK (0x40U) +#define CSR_ETRIGGER_U_SHIFT (6U) +#define CSR_ETRIGGER_U_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_U_SHIFT) & CSR_ETRIGGER_U_MASK) +#define CSR_ETRIGGER_U_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_U_MASK) >> CSR_ETRIGGER_U_SHIFT) + +/* + * ACTION (RW) + * + * Setting this field to select what happens when this trigger matches. + * 0:Raise a breakpoint exception + * 1:Enter Debug Mode. (Only supported when DMODE is 1.) + */ +#define CSR_ETRIGGER_ACTION_MASK (0x3FU) +#define CSR_ETRIGGER_ACTION_SHIFT (0U) +#define CSR_ETRIGGER_ACTION_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_ACTION_SHIFT) & CSR_ETRIGGER_ACTION_MASK) +#define CSR_ETRIGGER_ACTION_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_ACTION_MASK) >> CSR_ETRIGGER_ACTION_SHIFT) + +/* Bitfield definition for register: TDATA2 */ +/* + * DATA (RW) + * + * This register provides accesses to the tdata2 register of the currently selected trigger registers selected by the tselect register, and it holds trigger-specific data.. + */ +#define CSR_TDATA2_DATA_MASK (0xFFFFFFFFUL) +#define CSR_TDATA2_DATA_SHIFT (0U) +#define CSR_TDATA2_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA2_DATA_SHIFT) & CSR_TDATA2_DATA_MASK) +#define CSR_TDATA2_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA2_DATA_MASK) >> CSR_TDATA2_DATA_SHIFT) + +/* Bitfield definition for register: TDATA3 */ +/* + * DATA (RW) + * + * This register provides accesses to the tdata3 register of the currently selected trigger registers selected by the tselect register, and it holds trigger-specific data.. + */ +#define CSR_TDATA3_DATA_MASK (0xFFFFFFFFUL) +#define CSR_TDATA3_DATA_SHIFT (0U) +#define CSR_TDATA3_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA3_DATA_SHIFT) & CSR_TDATA3_DATA_MASK) +#define CSR_TDATA3_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA3_DATA_MASK) >> CSR_TDATA3_DATA_SHIFT) + +/* Bitfield definition for register: TEXTRA */ +/* + * MVALUE (RW) + * + * Data used together with MSELECT. + */ +#define CSR_TEXTRA_MVALUE_MASK (0xFC000000UL) +#define CSR_TEXTRA_MVALUE_SHIFT (26U) +#define CSR_TEXTRA_MVALUE_SET(x) (((uint32_t)(x) << CSR_TEXTRA_MVALUE_SHIFT) & CSR_TEXTRA_MVALUE_MASK) +#define CSR_TEXTRA_MVALUE_GET(x) (((uint32_t)(x) & CSR_TEXTRA_MVALUE_MASK) >> CSR_TEXTRA_MVALUE_SHIFT) + +/* + * MSELECT (RW) + * + * 0:Ignore MVALUE. + * 1:This trigger will only match if the lower bits of mcontext equal MVALUE. + */ +#define CSR_TEXTRA_MSELECT_MASK (0x2000000UL) +#define CSR_TEXTRA_MSELECT_SHIFT (25U) +#define CSR_TEXTRA_MSELECT_SET(x) (((uint32_t)(x) << CSR_TEXTRA_MSELECT_SHIFT) & CSR_TEXTRA_MSELECT_MASK) +#define CSR_TEXTRA_MSELECT_GET(x) (((uint32_t)(x) & CSR_TEXTRA_MSELECT_MASK) >> CSR_TEXTRA_MSELECT_SHIFT) + +/* + * SVALUE (RW) + * + * Data used together with SSELECT. + */ +#define CSR_TEXTRA_SVALUE_MASK (0x7FCU) +#define CSR_TEXTRA_SVALUE_SHIFT (2U) +#define CSR_TEXTRA_SVALUE_SET(x) (((uint32_t)(x) << CSR_TEXTRA_SVALUE_SHIFT) & CSR_TEXTRA_SVALUE_MASK) +#define CSR_TEXTRA_SVALUE_GET(x) (((uint32_t)(x) & CSR_TEXTRA_SVALUE_MASK) >> CSR_TEXTRA_SVALUE_SHIFT) + +/* + * SSELECT (RW) + * + * 0:Ignore MVALUE + * 1:This trigger will only match if the lower bits of scontext equal SVALUE + * 2This trigger will only match if satp.ASID equals SVALUE. + */ +#define CSR_TEXTRA_SSELECT_MASK (0x3U) +#define CSR_TEXTRA_SSELECT_SHIFT (0U) +#define CSR_TEXTRA_SSELECT_SET(x) (((uint32_t)(x) << CSR_TEXTRA_SSELECT_SHIFT) & CSR_TEXTRA_SSELECT_MASK) +#define CSR_TEXTRA_SSELECT_GET(x) (((uint32_t)(x) & CSR_TEXTRA_SSELECT_MASK) >> CSR_TEXTRA_SSELECT_SHIFT) + +/* Bitfield definition for register: TINFO */ +/* + * INFO (RO) + * + * One bit for each possible type in tdata1. Bit N corresponds to type N. If the bit is set, then that + * type is supported by the currently selected trigger. If the currently selected trigger does not exist, this field contains 1. + * 0:When this bit is set, there is no trigger at this tselect + * 1:Reserved and hardwired to 0. + * 2：When this bit is set, the selected trigger supports type of address/data match trigger + * 3:When this bit is set, the selected trigger supports type of instruction count trigger. + * 4:When this bit is set, the selected trigger supports type of interrupt trigger + * 5:When this bit is set, the selected trigger supports type of exception trigger + * 15:When this bit is set, the selected trigger exists (so enumeration shouldn’t terminate), but is not currently available. + * Others:Reserved for future use. + */ +#define CSR_TINFO_INFO_MASK (0xFFFFU) +#define CSR_TINFO_INFO_SHIFT (0U) +#define CSR_TINFO_INFO_GET(x) (((uint32_t)(x) & CSR_TINFO_INFO_MASK) >> CSR_TINFO_INFO_SHIFT) + +/* Bitfield definition for register: TCONTROL */ +/* + * MPTE (RW) + * + * M-mode previous trigger enable field. When a trap into M-mode is taken, MPTE is set to the value of MTE. + */ +#define CSR_TCONTROL_MPTE_MASK (0x80U) +#define CSR_TCONTROL_MPTE_SHIFT (7U) +#define CSR_TCONTROL_MPTE_SET(x) (((uint32_t)(x) << CSR_TCONTROL_MPTE_SHIFT) & CSR_TCONTROL_MPTE_MASK) +#define CSR_TCONTROL_MPTE_GET(x) (((uint32_t)(x) & CSR_TCONTROL_MPTE_MASK) >> CSR_TCONTROL_MPTE_SHIFT) + +/* + * MTE (RW) + * + * M-mode trigger enable field. When a trap into M-mode is taken, MTE is set to 0. When the MRET instruction is executed, MTE is set to the value of MPTE. + * 0:Triggers do not match/fire while the hart is in M-mode. + * 1:Triggers do match/fire while the hart is in M-mode. + */ +#define CSR_TCONTROL_MTE_MASK (0x8U) +#define CSR_TCONTROL_MTE_SHIFT (3U) +#define CSR_TCONTROL_MTE_SET(x) (((uint32_t)(x) << CSR_TCONTROL_MTE_SHIFT) & CSR_TCONTROL_MTE_MASK) +#define CSR_TCONTROL_MTE_GET(x) (((uint32_t)(x) & CSR_TCONTROL_MTE_MASK) >> CSR_TCONTROL_MTE_SHIFT) + +/* Bitfield definition for register: MCONTEXT */ +/* + * MCONTEXT (RW) + * + * Machine mode software can write a context number to this register, which can be used to set triggers that only fire in that specific context. + */ +#define CSR_MCONTEXT_MCONTEXT_MASK (0x3FU) +#define CSR_MCONTEXT_MCONTEXT_SHIFT (0U) +#define CSR_MCONTEXT_MCONTEXT_SET(x) (((uint32_t)(x) << CSR_MCONTEXT_MCONTEXT_SHIFT) & CSR_MCONTEXT_MCONTEXT_MASK) +#define CSR_MCONTEXT_MCONTEXT_GET(x) (((uint32_t)(x) & CSR_MCONTEXT_MCONTEXT_MASK) >> CSR_MCONTEXT_MCONTEXT_SHIFT) + +/* Bitfield definition for register: SCONTEXT */ +/* + * SCONTEXT (RW) + * + * Machine mode software can write a context number to this register, which can be used to set triggers that only fire in that specific context. + */ +#define CSR_SCONTEXT_SCONTEXT_MASK (0x1FFU) +#define CSR_SCONTEXT_SCONTEXT_SHIFT (0U) +#define CSR_SCONTEXT_SCONTEXT_SET(x) (((uint32_t)(x) << CSR_SCONTEXT_SCONTEXT_SHIFT) & CSR_SCONTEXT_SCONTEXT_MASK) +#define CSR_SCONTEXT_SCONTEXT_GET(x) (((uint32_t)(x) & CSR_SCONTEXT_SCONTEXT_MASK) >> CSR_SCONTEXT_SCONTEXT_SHIFT) + +/* Bitfield definition for register: DCSR */ +/* + * XDEBUGVER (RO) + * + * Version of the external debugger. 0 indicates that no external debugger exists and 4 indicates that the external debugger conforms to the RISC-V External Debug Support (TD003) V0.13 + */ +#define CSR_DCSR_XDEBUGVER_MASK (0xF0000000UL) +#define CSR_DCSR_XDEBUGVER_SHIFT (28U) +#define CSR_DCSR_XDEBUGVER_GET(x) (((uint32_t)(x) & CSR_DCSR_XDEBUGVER_MASK) >> CSR_DCSR_XDEBUGVER_SHIFT) + +/* + * EBREAKM (RW) + * + * This bit controls the behavior of EBREAK instructions in Machine Mode + * 0:Generate a regular breakpoint exception + * 1:Enter Debug Mode + */ +#define CSR_DCSR_EBREAKM_MASK (0x8000U) +#define CSR_DCSR_EBREAKM_SHIFT (15U) +#define CSR_DCSR_EBREAKM_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKM_SHIFT) & CSR_DCSR_EBREAKM_MASK) +#define CSR_DCSR_EBREAKM_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKM_MASK) >> CSR_DCSR_EBREAKM_SHIFT) + +/* + * EBREAKU (RW) + * + * This bit controls the behavior of EBREAK instructions in User/Application Mode + * 0:Generate a regular breakpoint exception + * 1:Enter Debug Mode + */ +#define CSR_DCSR_EBREAKU_MASK (0x1000U) +#define CSR_DCSR_EBREAKU_SHIFT (12U) +#define CSR_DCSR_EBREAKU_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKU_SHIFT) & CSR_DCSR_EBREAKU_MASK) +#define CSR_DCSR_EBREAKU_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKU_MASK) >> CSR_DCSR_EBREAKU_SHIFT) + +/* + * STEPIE (RW) + * + * This bit controls whether interrupts are enabled during single stepping + * 0:Disable interrupts during single stepping + * 1:Allow interrupts in single stepping + */ +#define CSR_DCSR_STEPIE_MASK (0x800U) +#define CSR_DCSR_STEPIE_SHIFT (11U) +#define CSR_DCSR_STEPIE_SET(x) (((uint32_t)(x) << CSR_DCSR_STEPIE_SHIFT) & CSR_DCSR_STEPIE_MASK) +#define CSR_DCSR_STEPIE_GET(x) (((uint32_t)(x) & CSR_DCSR_STEPIE_MASK) >> CSR_DCSR_STEPIE_SHIFT) + +/* + * STOPCOUNT (RW) + * + * This bit controls whether performance counters are stopped in Debug Mode. + * 0:Do not stop counters in Debug Mode + * 1:Stop counters in Debug Mode + */ +#define CSR_DCSR_STOPCOUNT_MASK (0x400U) +#define CSR_DCSR_STOPCOUNT_SHIFT (10U) +#define CSR_DCSR_STOPCOUNT_SET(x) (((uint32_t)(x) << CSR_DCSR_STOPCOUNT_SHIFT) & CSR_DCSR_STOPCOUNT_MASK) +#define CSR_DCSR_STOPCOUNT_GET(x) (((uint32_t)(x) & CSR_DCSR_STOPCOUNT_MASK) >> CSR_DCSR_STOPCOUNT_SHIFT) + +/* + * STOPTIME (RW) + * + * This bit controls whether timers are stopped in Debug Mode. The processor only drives its stoptime output pin to 1 if it is in Debug Mode and this bit is set. Integration effort is required to make timers in the platform observe this pin to really stop them. + * 0:Do not stop timers in Debug Mode + * 1:Stop timers in Debug Mode + */ +#define CSR_DCSR_STOPTIME_MASK (0x200U) +#define CSR_DCSR_STOPTIME_SHIFT (9U) +#define CSR_DCSR_STOPTIME_SET(x) (((uint32_t)(x) << CSR_DCSR_STOPTIME_SHIFT) & CSR_DCSR_STOPTIME_MASK) +#define CSR_DCSR_STOPTIME_GET(x) (((uint32_t)(x) & CSR_DCSR_STOPTIME_MASK) >> CSR_DCSR_STOPTIME_SHIFT) + +/* + * CAUSE (RO) + * + * Reason why Debug Mode was entered. When there are multiple reasons to enter Debug Mode, the priority to determine the CAUSE value will be: trigger module > EBREAK > halt-on-reset > halt request > single step. Halt requests are requests issued by the external debugger + * 0:Reserved + * 1:EBREAK + * 2:Trigger module + * 3:Halt request + * 4:Single step + * 5:Halt-on-reset + * 6-7:Reserved + */ +#define CSR_DCSR_CAUSE_MASK (0x1C0U) +#define CSR_DCSR_CAUSE_SHIFT (6U) +#define CSR_DCSR_CAUSE_GET(x) (((uint32_t)(x) & CSR_DCSR_CAUSE_MASK) >> CSR_DCSR_CAUSE_SHIFT) + +/* + * MPRVEN (RW) + * + * This bit controls whether mstatus.MPRV takes effect in Debug Mode. + * 0:MPRV in mstatus is ignored in Debug Mode. + * 1:MPRV in mstatus takes effect in Debug Mode. + */ +#define CSR_DCSR_MPRVEN_MASK (0x10U) +#define CSR_DCSR_MPRVEN_SHIFT (4U) +#define CSR_DCSR_MPRVEN_SET(x) (((uint32_t)(x) << CSR_DCSR_MPRVEN_SHIFT) & CSR_DCSR_MPRVEN_MASK) +#define CSR_DCSR_MPRVEN_GET(x) (((uint32_t)(x) & CSR_DCSR_MPRVEN_MASK) >> CSR_DCSR_MPRVEN_SHIFT) + +/* + * NMIP (RO) + * + * When this bit is set, there is a Non-Maskable-Interrupt (NMI) pending for the hart. Since an NMI can indicate a hardware error condition, reliable debugging may no longer be possible once this bit becomes set. + */ +#define CSR_DCSR_NMIP_MASK (0x8U) +#define CSR_DCSR_NMIP_SHIFT (3U) +#define CSR_DCSR_NMIP_GET(x) (((uint32_t)(x) & CSR_DCSR_NMIP_MASK) >> CSR_DCSR_NMIP_SHIFT) + +/* + * STEP (RW) + * + * This bit controls whether non-Debug Mode instruction execution is in the single step mode. When set, the hart returns to Debug Mode after a single instruction execution. If the instruction does not complete due to an exception, the hart will immediately enter Debug Mode before executing the trap handler, with appropriate exception registers set. + * 0:Single Step Mode is off + * 1:Single Step Mode is on + */ +#define CSR_DCSR_STEP_MASK (0x4U) +#define CSR_DCSR_STEP_SHIFT (2U) +#define CSR_DCSR_STEP_SET(x) (((uint32_t)(x) << CSR_DCSR_STEP_SHIFT) & CSR_DCSR_STEP_MASK) +#define CSR_DCSR_STEP_GET(x) (((uint32_t)(x) & CSR_DCSR_STEP_MASK) >> CSR_DCSR_STEP_SHIFT) + +/* + * PRV (RW) + * + * The privilege level that the hart was operating in when Debug Mode was entered. The external debugger can modify this value to change the hart’s privilege level when exiting Debug Mode. + * 0:User/Application + * 1:Supervisor + * 2:Reserved + * 3:Machine + */ +#define CSR_DCSR_PRV_MASK (0x3U) +#define CSR_DCSR_PRV_SHIFT (0U) +#define CSR_DCSR_PRV_SET(x) (((uint32_t)(x) << CSR_DCSR_PRV_SHIFT) & CSR_DCSR_PRV_MASK) +#define CSR_DCSR_PRV_GET(x) (((uint32_t)(x) & CSR_DCSR_PRV_MASK) >> CSR_DCSR_PRV_SHIFT) + +/* Bitfield definition for register: DPC */ +/* + * DPC (RW) + * + * Debug Program Counter. Bit 0 is hardwired to 0. + */ +#define CSR_DPC_DPC_MASK (0xFFFFFFFFUL) +#define CSR_DPC_DPC_SHIFT (0U) +#define CSR_DPC_DPC_SET(x) (((uint32_t)(x) << CSR_DPC_DPC_SHIFT) & CSR_DPC_DPC_MASK) +#define CSR_DPC_DPC_GET(x) (((uint32_t)(x) & CSR_DPC_DPC_MASK) >> CSR_DPC_DPC_SHIFT) + +/* Bitfield definition for register: DSCRATCH0 */ +/* + * DSCRATCH (RO) + * + * A scratch register that is reserved for use by Debug Module. + */ +#define CSR_DSCRATCH0_DSCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_DSCRATCH0_DSCRATCH_SHIFT (0U) +#define CSR_DSCRATCH0_DSCRATCH_GET(x) (((uint32_t)(x) & CSR_DSCRATCH0_DSCRATCH_MASK) >> CSR_DSCRATCH0_DSCRATCH_SHIFT) + +/* Bitfield definition for register: DSCRATCH1 */ +/* + * DSCRATCH (RO) + * + * A scratch register that is reserved for use by Debug Module. + */ +#define CSR_DSCRATCH1_DSCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_DSCRATCH1_DSCRATCH_SHIFT (0U) +#define CSR_DSCRATCH1_DSCRATCH_GET(x) (((uint32_t)(x) & CSR_DSCRATCH1_DSCRATCH_MASK) >> CSR_DSCRATCH1_DSCRATCH_SHIFT) + +/* Bitfield definition for register: MCYCLE */ +/* + * COUNTER (RW) + * + * the lower 32 bits of Machine Cycle Counter + */ +#define CSR_MCYCLE_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MCYCLE_COUNTER_SHIFT (0U) +#define CSR_MCYCLE_COUNTER_SET(x) (((uint32_t)(x) << CSR_MCYCLE_COUNTER_SHIFT) & CSR_MCYCLE_COUNTER_MASK) +#define CSR_MCYCLE_COUNTER_GET(x) (((uint32_t)(x) & CSR_MCYCLE_COUNTER_MASK) >> CSR_MCYCLE_COUNTER_SHIFT) + +/* Bitfield definition for register: MINSTRET */ +/* + * COUNTER (RW) + * + * the lower 32 bits of Machine Instruction-Retired Counter + */ +#define CSR_MINSTRET_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MINSTRET_COUNTER_SHIFT (0U) +#define CSR_MINSTRET_COUNTER_SET(x) (((uint32_t)(x) << CSR_MINSTRET_COUNTER_SHIFT) & CSR_MINSTRET_COUNTER_MASK) +#define CSR_MINSTRET_COUNTER_GET(x) (((uint32_t)(x) & CSR_MINSTRET_COUNTER_MASK) >> CSR_MINSTRET_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER3 */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent3 + */ +#define CSR_MHPMCOUNTER3_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER3_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER3_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER3_COUNTER_SHIFT) & CSR_MHPMCOUNTER3_COUNTER_MASK) +#define CSR_MHPMCOUNTER3_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER3_COUNTER_MASK) >> CSR_MHPMCOUNTER3_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER4 */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent4 + */ +#define CSR_MHPMCOUNTER4_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER4_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER4_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER4_COUNTER_SHIFT) & CSR_MHPMCOUNTER4_COUNTER_MASK) +#define CSR_MHPMCOUNTER4_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER4_COUNTER_MASK) >> CSR_MHPMCOUNTER4_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER5 */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent5 + */ +#define CSR_MHPMCOUNTER5_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER5_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER5_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER5_COUNTER_SHIFT) & CSR_MHPMCOUNTER5_COUNTER_MASK) +#define CSR_MHPMCOUNTER5_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER5_COUNTER_MASK) >> CSR_MHPMCOUNTER5_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER6 */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent6 + */ +#define CSR_MHPMCOUNTER6_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER6_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER6_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER6_COUNTER_SHIFT) & CSR_MHPMCOUNTER6_COUNTER_MASK) +#define CSR_MHPMCOUNTER6_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER6_COUNTER_MASK) >> CSR_MHPMCOUNTER6_COUNTER_SHIFT) + +/* Bitfield definition for register: MCYCLEH */ +/* + * COUNTER (RW) + * + * the higher 32 bits of Machine Cycle Counter + */ +#define CSR_MCYCLEH_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MCYCLEH_COUNTER_SHIFT (0U) +#define CSR_MCYCLEH_COUNTER_SET(x) (((uint32_t)(x) << CSR_MCYCLEH_COUNTER_SHIFT) & CSR_MCYCLEH_COUNTER_MASK) +#define CSR_MCYCLEH_COUNTER_GET(x) (((uint32_t)(x) & CSR_MCYCLEH_COUNTER_MASK) >> CSR_MCYCLEH_COUNTER_SHIFT) + +/* Bitfield definition for register: MINSTRETH */ +/* + * COUNTER (RW) + * + * the higher 32 bits of Machine Instruction-Retired Counter + */ +#define CSR_MINSTRETH_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MINSTRETH_COUNTER_SHIFT (0U) +#define CSR_MINSTRETH_COUNTER_SET(x) (((uint32_t)(x) << CSR_MINSTRETH_COUNTER_SHIFT) & CSR_MINSTRETH_COUNTER_MASK) +#define CSR_MINSTRETH_COUNTER_GET(x) (((uint32_t)(x) & CSR_MINSTRETH_COUNTER_MASK) >> CSR_MINSTRETH_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER3H */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent3 + */ +#define CSR_MHPMCOUNTER3H_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER3H_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER3H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER3H_COUNTER_SHIFT) & CSR_MHPMCOUNTER3H_COUNTER_MASK) +#define CSR_MHPMCOUNTER3H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER3H_COUNTER_MASK) >> CSR_MHPMCOUNTER3H_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER4H */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent4 + */ +#define CSR_MHPMCOUNTER4H_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER4H_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER4H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER4H_COUNTER_SHIFT) & CSR_MHPMCOUNTER4H_COUNTER_MASK) +#define CSR_MHPMCOUNTER4H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER4H_COUNTER_MASK) >> CSR_MHPMCOUNTER4H_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER5H */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent5 + */ +#define CSR_MHPMCOUNTER5H_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER5H_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER5H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER5H_COUNTER_SHIFT) & CSR_MHPMCOUNTER5H_COUNTER_MASK) +#define CSR_MHPMCOUNTER5H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER5H_COUNTER_MASK) >> CSR_MHPMCOUNTER5H_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER6H */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent6 + */ +#define CSR_MHPMCOUNTER6H_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER6H_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER6H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER6H_COUNTER_SHIFT) & CSR_MHPMCOUNTER6H_COUNTER_MASK) +#define CSR_MHPMCOUNTER6H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER6H_COUNTER_MASK) >> CSR_MHPMCOUNTER6H_COUNTER_SHIFT) + +/* Bitfield definition for register: CYCLE */ +/* + * CYCLE (RW) + * + * Cycle Counter + */ +#define CSR_CYCLE_CYCLE_MASK (0xFFFFFFFFUL) +#define CSR_CYCLE_CYCLE_SHIFT (0U) +#define CSR_CYCLE_CYCLE_SET(x) (((uint32_t)(x) << CSR_CYCLE_CYCLE_SHIFT) & CSR_CYCLE_CYCLE_MASK) +#define CSR_CYCLE_CYCLE_GET(x) (((uint32_t)(x) & CSR_CYCLE_CYCLE_MASK) >> CSR_CYCLE_CYCLE_SHIFT) + +/* Bitfield definition for register: CYCLEH */ +/* + * CYCLEH (RW) + * + * Cycle Counter Higher 32-bit + */ +#define CSR_CYCLEH_CYCLEH_MASK (0xFFFFFFFFUL) +#define CSR_CYCLEH_CYCLEH_SHIFT (0U) +#define CSR_CYCLEH_CYCLEH_SET(x) (((uint32_t)(x) << CSR_CYCLEH_CYCLEH_SHIFT) & CSR_CYCLEH_CYCLEH_MASK) +#define CSR_CYCLEH_CYCLEH_GET(x) (((uint32_t)(x) & CSR_CYCLEH_CYCLEH_MASK) >> CSR_CYCLEH_CYCLEH_SHIFT) + +/* Bitfield definition for register: MVENDORID */ +/* + * MVENDORID (RO) + * + * The manufacturer ID + */ +#define CSR_MVENDORID_MVENDORID_MASK (0xFFFFFFFFUL) +#define CSR_MVENDORID_MVENDORID_SHIFT (0U) +#define CSR_MVENDORID_MVENDORID_GET(x) (((uint32_t)(x) & CSR_MVENDORID_MVENDORID_MASK) >> CSR_MVENDORID_MVENDORID_SHIFT) + +/* Bitfield definition for register: MARCHID */ +/* + * CPU_ID (RO) + * + * CPU ID + */ +#define CSR_MARCHID_CPU_ID_MASK (0x7FFFFFFFUL) +#define CSR_MARCHID_CPU_ID_SHIFT (0U) +#define CSR_MARCHID_CPU_ID_GET(x) (((uint32_t)(x) & CSR_MARCHID_CPU_ID_MASK) >> CSR_MARCHID_CPU_ID_SHIFT) + +/* Bitfield definition for register: MIMPID */ +/* + * MAJOR (RO) + * + * Revision major + */ +#define CSR_MIMPID_MAJOR_MASK (0xFFFFFF00UL) +#define CSR_MIMPID_MAJOR_SHIFT (8U) +#define CSR_MIMPID_MAJOR_GET(x) (((uint32_t)(x) & CSR_MIMPID_MAJOR_MASK) >> CSR_MIMPID_MAJOR_SHIFT) + +/* + * MINOR (RO) + * + * Revision minor + */ +#define CSR_MIMPID_MINOR_MASK (0xF0U) +#define CSR_MIMPID_MINOR_SHIFT (4U) +#define CSR_MIMPID_MINOR_GET(x) (((uint32_t)(x) & CSR_MIMPID_MINOR_MASK) >> CSR_MIMPID_MINOR_SHIFT) + +/* + * EXTENSION (RO) + * + * Revision extension + */ +#define CSR_MIMPID_EXTENSION_MASK (0xFU) +#define CSR_MIMPID_EXTENSION_SHIFT (0U) +#define CSR_MIMPID_EXTENSION_GET(x) (((uint32_t)(x) & CSR_MIMPID_EXTENSION_MASK) >> CSR_MIMPID_EXTENSION_SHIFT) + +/* Bitfield definition for register: MHARTID */ +/* + * MHARTID (RO) + * + * Hart ID + */ +#define CSR_MHARTID_MHARTID_MASK (0xFFFFFFFFUL) +#define CSR_MHARTID_MHARTID_SHIFT (0U) +#define CSR_MHARTID_MHARTID_GET(x) (((uint32_t)(x) & CSR_MHARTID_MHARTID_MASK) >> CSR_MHARTID_MHARTID_SHIFT) + +/* NON-STANDARD CRS register bitfiled definitions */ + +/* Bitfield definition for register: MCOUNTINHIBIT */ +/* + * HPM6 (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_HPM6_MASK (0x40U) +#define CSR_MCOUNTINHIBIT_HPM6_SHIFT (6U) +#define CSR_MCOUNTINHIBIT_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM6_SHIFT) & CSR_MCOUNTINHIBIT_HPM6_MASK) +#define CSR_MCOUNTINHIBIT_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM6_MASK) >> CSR_MCOUNTINHIBIT_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_HPM5_MASK (0x20U) +#define CSR_MCOUNTINHIBIT_HPM5_SHIFT (5U) +#define CSR_MCOUNTINHIBIT_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM5_SHIFT) & CSR_MCOUNTINHIBIT_HPM5_MASK) +#define CSR_MCOUNTINHIBIT_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM5_MASK) >> CSR_MCOUNTINHIBIT_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_HPM4_MASK (0x10U) +#define CSR_MCOUNTINHIBIT_HPM4_SHIFT (4U) +#define CSR_MCOUNTINHIBIT_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM4_SHIFT) & CSR_MCOUNTINHIBIT_HPM4_MASK) +#define CSR_MCOUNTINHIBIT_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM4_MASK) >> CSR_MCOUNTINHIBIT_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_HPM3_MASK (0x8U) +#define CSR_MCOUNTINHIBIT_HPM3_SHIFT (3U) +#define CSR_MCOUNTINHIBIT_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM3_SHIFT) & CSR_MCOUNTINHIBIT_HPM3_MASK) +#define CSR_MCOUNTINHIBIT_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM3_MASK) >> CSR_MCOUNTINHIBIT_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_IR_MASK (0x4U) +#define CSR_MCOUNTINHIBIT_IR_SHIFT (2U) +#define CSR_MCOUNTINHIBIT_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_IR_SHIFT) & CSR_MCOUNTINHIBIT_IR_MASK) +#define CSR_MCOUNTINHIBIT_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_IR_MASK) >> CSR_MCOUNTINHIBIT_IR_SHIFT) + +/* + * TM (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_TM_MASK (0x2U) +#define CSR_MCOUNTINHIBIT_TM_SHIFT (1U) +#define CSR_MCOUNTINHIBIT_TM_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_TM_SHIFT) & CSR_MCOUNTINHIBIT_TM_MASK) +#define CSR_MCOUNTINHIBIT_TM_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_TM_MASK) >> CSR_MCOUNTINHIBIT_TM_SHIFT) + +/* + * CY (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_CY_MASK (0x1U) +#define CSR_MCOUNTINHIBIT_CY_SHIFT (0U) +#define CSR_MCOUNTINHIBIT_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_CY_SHIFT) & CSR_MCOUNTINHIBIT_CY_MASK) +#define CSR_MCOUNTINHIBIT_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_CY_MASK) >> CSR_MCOUNTINHIBIT_CY_SHIFT) + +/* Bitfield definition for register: MILMB */ +/* + * IBPA (RO) + * + * The base physical address of ILM. It has to be an integer multiple of the ILM size + */ +#define CSR_MILMB_IBPA_MASK (0xFFFFFC00UL) +#define CSR_MILMB_IBPA_SHIFT (10U) +#define CSR_MILMB_IBPA_GET(x) (((uint32_t)(x) & CSR_MILMB_IBPA_MASK) >> CSR_MILMB_IBPA_SHIFT) + +/* + * RWECC (RW) + * + * Controls diagnostic accesses of ECC codes of the ILM RAMs. When set, load/store to ILM reads/writes ECC codes to the mecc_code register. This bit can be set for injecting ECC errors to test the ECC handler. + * 0:Disable diagnostic accesses of ECC codes + * 1:Enable diagnostic accesses of ECC codes + */ +#define CSR_MILMB_RWECC_MASK (0x8U) +#define CSR_MILMB_RWECC_SHIFT (3U) +#define CSR_MILMB_RWECC_SET(x) (((uint32_t)(x) << CSR_MILMB_RWECC_SHIFT) & CSR_MILMB_RWECC_MASK) +#define CSR_MILMB_RWECC_GET(x) (((uint32_t)(x) & CSR_MILMB_RWECC_MASK) >> CSR_MILMB_RWECC_SHIFT) + +/* + * ECCEN (RW) + * + * Parity/ECC enable control: + * 0:Disable parity/ECC + * 1:Reserved + * 2:Generate exceptions only on uncorrectable parity/ECC errors + * 3:Generate exceptions on any type of parity/ECC errors + */ +#define CSR_MILMB_ECCEN_MASK (0x6U) +#define CSR_MILMB_ECCEN_SHIFT (1U) +#define CSR_MILMB_ECCEN_SET(x) (((uint32_t)(x) << CSR_MILMB_ECCEN_SHIFT) & CSR_MILMB_ECCEN_MASK) +#define CSR_MILMB_ECCEN_GET(x) (((uint32_t)(x) & CSR_MILMB_ECCEN_MASK) >> CSR_MILMB_ECCEN_SHIFT) + +/* + * IEN (RO) + * + * ILM enable control: + * 0:ILM is disabled + * 1:ILM is enabled + */ +#define CSR_MILMB_IEN_MASK (0x1U) +#define CSR_MILMB_IEN_SHIFT (0U) +#define CSR_MILMB_IEN_GET(x) (((uint32_t)(x) & CSR_MILMB_IEN_MASK) >> CSR_MILMB_IEN_SHIFT) + +/* Bitfield definition for register: MDLMB */ +/* + * DBPA (RO) + * + * The base physical address of DLM. It has to be an integer multiple of the DLM size + */ +#define CSR_MDLMB_DBPA_MASK (0xFFFFFC00UL) +#define CSR_MDLMB_DBPA_SHIFT (10U) +#define CSR_MDLMB_DBPA_GET(x) (((uint32_t)(x) & CSR_MDLMB_DBPA_MASK) >> CSR_MDLMB_DBPA_SHIFT) + +/* + * RWECC (RW) + * + * Controls diagnostic accesses of ECC codes of the DLM RAMs. When set, load/store to DLM reads/writes ECC codes to the mecc_code register. This bit can be set for injecting ECC errors to test the ECC handler. + * 0:Disable diagnostic accesses of ECC codes + * 1:Enable diagnostic accesses of ECC codes + */ +#define CSR_MDLMB_RWECC_MASK (0x8U) +#define CSR_MDLMB_RWECC_SHIFT (3U) +#define CSR_MDLMB_RWECC_SET(x) (((uint32_t)(x) << CSR_MDLMB_RWECC_SHIFT) & CSR_MDLMB_RWECC_MASK) +#define CSR_MDLMB_RWECC_GET(x) (((uint32_t)(x) & CSR_MDLMB_RWECC_MASK) >> CSR_MDLMB_RWECC_SHIFT) + +/* + * ECCEN (RW) + * + * Parity/ECC enable control: + * 0:Disable parity/ECC + * 1:Reserved + * 2:Generate exceptions only on uncorrectable parity/ECC errors + * 3:Generate exceptions on any type of parity/ECC errors + */ +#define CSR_MDLMB_ECCEN_MASK (0x6U) +#define CSR_MDLMB_ECCEN_SHIFT (1U) +#define CSR_MDLMB_ECCEN_SET(x) (((uint32_t)(x) << CSR_MDLMB_ECCEN_SHIFT) & CSR_MDLMB_ECCEN_MASK) +#define CSR_MDLMB_ECCEN_GET(x) (((uint32_t)(x) & CSR_MDLMB_ECCEN_MASK) >> CSR_MDLMB_ECCEN_SHIFT) + +/* + * DEN (RO) + * + * DLM enable control: + * 0:DLM is disabled + * 1:DLM is enabled + */ +#define CSR_MDLMB_DEN_MASK (0x1U) +#define CSR_MDLMB_DEN_SHIFT (0U) +#define CSR_MDLMB_DEN_GET(x) (((uint32_t)(x) & CSR_MDLMB_DEN_MASK) >> CSR_MDLMB_DEN_SHIFT) + +/* Bitfield definition for register: MECC_CODE */ +/* + * INSN (RO) + * + * Indicates if the parity/ECC error is caused by instruction fetch or data access. + * 0:Data access + * 1:Instruction fetch + */ +#define CSR_MECC_CODE_INSN_MASK (0x400000UL) +#define CSR_MECC_CODE_INSN_SHIFT (22U) +#define CSR_MECC_CODE_INSN_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_INSN_MASK) >> CSR_MECC_CODE_INSN_SHIFT) + +/* + * RAMID (RO) + * + * The ID of RAM that caused parity/ECC errors. + * This bit is updated on parity/ECC error exceptions. + * 0–1:Reserved + * 2:Tag RAM of I-Cache + * 3:Data RAM of I-Cache + * 4:Tag RAM of D-Cache + * 5:Data RAM of D-Cache + * 6:Tag RAM of TLB + * 7:Data RAM of TLB + * 8:ILM + * 9:DLM + * 10–15:Reserved + */ +#define CSR_MECC_CODE_RAMID_MASK (0x3C0000UL) +#define CSR_MECC_CODE_RAMID_SHIFT (18U) +#define CSR_MECC_CODE_RAMID_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_RAMID_MASK) >> CSR_MECC_CODE_RAMID_SHIFT) + +/* + * P (RO) + * + * Precise error. This bit is updated on parity/ECC error exceptions. + * 0:Imprecise error + * 1:Precise error + */ +#define CSR_MECC_CODE_P_MASK (0x20000UL) +#define CSR_MECC_CODE_P_SHIFT (17U) +#define CSR_MECC_CODE_P_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_P_MASK) >> CSR_MECC_CODE_P_SHIFT) + +/* + * C (RO) + * + * Correctable error. This bit is updated on parity/ECC error exceptions. + * 0:Uncorrectable error + * 1:Correctable error + */ +#define CSR_MECC_CODE_C_MASK (0x10000UL) +#define CSR_MECC_CODE_C_SHIFT (16U) +#define CSR_MECC_CODE_C_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_C_MASK) >> CSR_MECC_CODE_C_SHIFT) + +/* + * CODE (RW) + * + * This field records the ECC value on ECC error exceptions. This field is also used to read/write the ECC codes when diagnostic access of ECC codes are enabled (milmb.RWECC or mdlmb.RWECC is 1). + */ +#define CSR_MECC_CODE_CODE_MASK (0x7FU) +#define CSR_MECC_CODE_CODE_SHIFT (0U) +#define CSR_MECC_CODE_CODE_SET(x) (((uint32_t)(x) << CSR_MECC_CODE_CODE_SHIFT) & CSR_MECC_CODE_CODE_MASK) +#define CSR_MECC_CODE_CODE_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_CODE_MASK) >> CSR_MECC_CODE_CODE_SHIFT) + +/* Bitfield definition for register: MNVEC */ +/* + * MNVEC (RO) + * + * Base address of the NMI handler. Its value is the zero-extended value of the reset_vector. + */ +#define CSR_MNVEC_MNVEC_MASK (0xFFFFFFFFUL) +#define CSR_MNVEC_MNVEC_SHIFT (0U) +#define CSR_MNVEC_MNVEC_GET(x) (((uint32_t)(x) & CSR_MNVEC_MNVEC_MASK) >> CSR_MNVEC_MNVEC_SHIFT) + +/* Bitfield definition for register: MXSTATUS */ +/* + * PDME (RW) + * + * For saving previous DME state on entering a trap. This field is hardwired to 0 if data cache and data local memory are not supported. + */ +#define CSR_MXSTATUS_PDME_MASK (0x20U) +#define CSR_MXSTATUS_PDME_SHIFT (5U) +#define CSR_MXSTATUS_PDME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PDME_SHIFT) & CSR_MXSTATUS_PDME_MASK) +#define CSR_MXSTATUS_PDME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PDME_MASK) >> CSR_MXSTATUS_PDME_SHIFT) + +/* + * DME (RW) + * + * Data Machine Error flag. It indicates an exception occurred at the data cache or data local memory (DLM). Load/store accesses will bypass D-Cache when this bit is set. The exception handler should clear this bit after the machine error has been dealt with. + */ +#define CSR_MXSTATUS_DME_MASK (0x10U) +#define CSR_MXSTATUS_DME_SHIFT (4U) +#define CSR_MXSTATUS_DME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_DME_SHIFT) & CSR_MXSTATUS_DME_MASK) +#define CSR_MXSTATUS_DME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_DME_MASK) >> CSR_MXSTATUS_DME_SHIFT) + +/* + * PIME (RW) + * + * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding + * is defined as follows: + * 0: User mode + * 1: Supervisor mode + * 2: Reserved + * 3: Machine mode + */ +#define CSR_MXSTATUS_PIME_MASK (0x8U) +#define CSR_MXSTATUS_PIME_SHIFT (3U) +#define CSR_MXSTATUS_PIME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PIME_SHIFT) & CSR_MXSTATUS_PIME_MASK) +#define CSR_MXSTATUS_PIME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PIME_MASK) >> CSR_MXSTATUS_PIME_SHIFT) + +/* + * IME (RW) + * + * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding + * is defined as follows: + * 0: User mode + * 1: Supervisor mode + * 2: Reserved + * 3: Machine mode + */ +#define CSR_MXSTATUS_IME_MASK (0x4U) +#define CSR_MXSTATUS_IME_SHIFT (2U) +#define CSR_MXSTATUS_IME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_IME_SHIFT) & CSR_MXSTATUS_IME_MASK) +#define CSR_MXSTATUS_IME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_IME_MASK) >> CSR_MXSTATUS_IME_SHIFT) + +/* + * PPFT_EN (RW) + * + * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding + * is defined as follows: + * 0: User mode + * 1: Supervisor mode + * 2: Reserved + * 3: Machine mode + */ +#define CSR_MXSTATUS_PPFT_EN_MASK (0x2U) +#define CSR_MXSTATUS_PPFT_EN_SHIFT (1U) +#define CSR_MXSTATUS_PPFT_EN_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PPFT_EN_SHIFT) & CSR_MXSTATUS_PPFT_EN_MASK) +#define CSR_MXSTATUS_PPFT_EN_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PPFT_EN_MASK) >> CSR_MXSTATUS_PPFT_EN_SHIFT) + +/* + * PFT_EN (RW) + * + * Enable performance throttling. When throttling is enabled, the processor executes instructions at the performance level specified in mpft_ctl.T_LEVEL. On entering a trap: + * PPFT_EN <= PFT_EN; + * PFT_EN <= mpft_ctl.FAST_INT ? 0 :PFT_EN; + * On executing an MRET instruction: + * PFT_EN <= PPFT_EN; + * This field is hardwired to 0 if the PowerBrake feature is not supported. + */ +#define CSR_MXSTATUS_PFT_EN_MASK (0x1U) +#define CSR_MXSTATUS_PFT_EN_SHIFT (0U) +#define CSR_MXSTATUS_PFT_EN_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PFT_EN_SHIFT) & CSR_MXSTATUS_PFT_EN_MASK) +#define CSR_MXSTATUS_PFT_EN_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PFT_EN_MASK) >> CSR_MXSTATUS_PFT_EN_SHIFT) + +/* Bitfield definition for register: MPFT_CTL */ +/* + * FAST_INT (RW) + * + * Fast interrupt response. If this field is set, mxstatus.PFT_EN will be automatically cleared when the processor enters an interrupt handler. + */ +#define CSR_MPFT_CTL_FAST_INT_MASK (0x100U) +#define CSR_MPFT_CTL_FAST_INT_SHIFT (8U) +#define CSR_MPFT_CTL_FAST_INT_SET(x) (((uint32_t)(x) << CSR_MPFT_CTL_FAST_INT_SHIFT) & CSR_MPFT_CTL_FAST_INT_MASK) +#define CSR_MPFT_CTL_FAST_INT_GET(x) (((uint32_t)(x) & CSR_MPFT_CTL_FAST_INT_MASK) >> CSR_MPFT_CTL_FAST_INT_SHIFT) + +/* + * T_LEVEL (RW) + * + * Throttling Level. The processor has the highest performance at throttling level 0 and the lowest + * performance at throttling level 15. + * 0:Level 0 (the highest performance) + * 1-14:Level 1-14 + * 15:Level 15 (the lowest performance) + */ +#define CSR_MPFT_CTL_T_LEVEL_MASK (0xF0U) +#define CSR_MPFT_CTL_T_LEVEL_SHIFT (4U) +#define CSR_MPFT_CTL_T_LEVEL_SET(x) (((uint32_t)(x) << CSR_MPFT_CTL_T_LEVEL_SHIFT) & CSR_MPFT_CTL_T_LEVEL_MASK) +#define CSR_MPFT_CTL_T_LEVEL_GET(x) (((uint32_t)(x) & CSR_MPFT_CTL_T_LEVEL_MASK) >> CSR_MPFT_CTL_T_LEVEL_SHIFT) + +/* Bitfield definition for register: MHSP_CTL */ +/* + * M (RW) + * + * Enables the SP protection and recording mechanism in Machine mode + * 0:The mechanism is disabled in Machine mode. + * 1: The mechanism is enabled in Machine mode. + */ +#define CSR_MHSP_CTL_M_MASK (0x20U) +#define CSR_MHSP_CTL_M_SHIFT (5U) +#define CSR_MHSP_CTL_M_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_M_SHIFT) & CSR_MHSP_CTL_M_MASK) +#define CSR_MHSP_CTL_M_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_M_MASK) >> CSR_MHSP_CTL_M_SHIFT) + +/* + * S (RW) + * + * Enables the SP protection and recording mechanism in Supervisor mode + * 0:The mechanism is disabled in Supervisor mode + * 1:The mechanism is enabled in Supervisor mode + */ +#define CSR_MHSP_CTL_S_MASK (0x10U) +#define CSR_MHSP_CTL_S_SHIFT (4U) +#define CSR_MHSP_CTL_S_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_S_SHIFT) & CSR_MHSP_CTL_S_MASK) +#define CSR_MHSP_CTL_S_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_S_MASK) >> CSR_MHSP_CTL_S_SHIFT) + +/* + * U (RW) + * + * Enables the SP protection and recording mechanism in User mode + * 0:The mechanism is disabled in User mode + * 1:The mechanism is enabled in User mode. + */ +#define CSR_MHSP_CTL_U_MASK (0x8U) +#define CSR_MHSP_CTL_U_SHIFT (3U) +#define CSR_MHSP_CTL_U_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_U_SHIFT) & CSR_MHSP_CTL_U_MASK) +#define CSR_MHSP_CTL_U_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_U_MASK) >> CSR_MHSP_CTL_U_SHIFT) + +/* + * SCHM (RW) + * + * Selects the operating scheme of the stack protection and recording mechanism + * 0:Stack overflow/underflow detection + * 1:Top-of-stack recording + */ +#define CSR_MHSP_CTL_SCHM_MASK (0x4U) +#define CSR_MHSP_CTL_SCHM_SHIFT (2U) +#define CSR_MHSP_CTL_SCHM_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_SCHM_SHIFT) & CSR_MHSP_CTL_SCHM_MASK) +#define CSR_MHSP_CTL_SCHM_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_SCHM_MASK) >> CSR_MHSP_CTL_SCHM_SHIFT) + +/* + * UDF_EN (RW) + * + * Enable bit for the stack underflow protection mechanism. This bit will be cleared to 0 automatically by hardware when a stack protection (overflow or underflow) exception is taken. + * 0:The stack underflow protection is disabled + * 1:The stack underflow protection is enabled. + */ +#define CSR_MHSP_CTL_UDF_EN_MASK (0x2U) +#define CSR_MHSP_CTL_UDF_EN_SHIFT (1U) +#define CSR_MHSP_CTL_UDF_EN_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_UDF_EN_SHIFT) & CSR_MHSP_CTL_UDF_EN_MASK) +#define CSR_MHSP_CTL_UDF_EN_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_UDF_EN_MASK) >> CSR_MHSP_CTL_UDF_EN_SHIFT) + +/* + * OVF_EN (RW) + * + * Enable bit for the stack overflow protection and recording mechanism. This bit will be cleared to 0 automatically by hardware when a stack protection (overflow or underflow) exception is taken. + * 0:The stack overflow protection and recording mechanism are disabled. + * 1:The stack overflow protection and recording mechanism are enabled. + */ +#define CSR_MHSP_CTL_OVF_EN_MASK (0x1U) +#define CSR_MHSP_CTL_OVF_EN_SHIFT (0U) +#define CSR_MHSP_CTL_OVF_EN_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_OVF_EN_SHIFT) & CSR_MHSP_CTL_OVF_EN_MASK) +#define CSR_MHSP_CTL_OVF_EN_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_OVF_EN_MASK) >> CSR_MHSP_CTL_OVF_EN_SHIFT) + +/* Bitfield definition for register: MSP_BOUND */ +/* + * MSP_BOUND (RW) + * + * Machine SP Bound + */ +#define CSR_MSP_BOUND_MSP_BOUND_MASK (0xFFFFFFFFUL) +#define CSR_MSP_BOUND_MSP_BOUND_SHIFT (0U) +#define CSR_MSP_BOUND_MSP_BOUND_SET(x) (((uint32_t)(x) << CSR_MSP_BOUND_MSP_BOUND_SHIFT) & CSR_MSP_BOUND_MSP_BOUND_MASK) +#define CSR_MSP_BOUND_MSP_BOUND_GET(x) (((uint32_t)(x) & CSR_MSP_BOUND_MSP_BOUND_MASK) >> CSR_MSP_BOUND_MSP_BOUND_SHIFT) + +/* Bitfield definition for register: MSP_BASE */ +/* + * SP_BASE (RW) + * + * Machine SP base + */ +#define CSR_MSP_BASE_SP_BASE_MASK (0xFFFFFFFFUL) +#define CSR_MSP_BASE_SP_BASE_SHIFT (0U) +#define CSR_MSP_BASE_SP_BASE_SET(x) (((uint32_t)(x) << CSR_MSP_BASE_SP_BASE_SHIFT) & CSR_MSP_BASE_SP_BASE_MASK) +#define CSR_MSP_BASE_SP_BASE_GET(x) (((uint32_t)(x) & CSR_MSP_BASE_SP_BASE_MASK) >> CSR_MSP_BASE_SP_BASE_SHIFT) + +/* Bitfield definition for register: MDCAUSE */ +/* + * MDCAUSE (RW) + * + * This register further disambiguates causes of traps recorded in the mcause register. + * The value of MDCAUSE for precise exception: + * When mcause == 1 (Instruction access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP instruction access violation; 3:Bus error; 4:PMA empty hole access + * When mcause == 2 (Illegal instruction): + * 0:Please parse the mtval CSR; 1:FP disabled exception; 2:ACE disabled exception + * When mcause == 5 (Load access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception + * When mcause == 7 (Store access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception + * The value of MDCAUSE for imprecise exception: + * When mcause == Local Interrupt 16 or Local Interrupt 272 (16 + 256) (ECC error local interrupt) + * 0:Reserved; 1:LM slave port ECC/Parity error; 2:Imprecise store ECC/Parity error; 3:Imprecise load ECC/Parity error + * When mcause == Local Interrupt 17 or Local Interrupt 273 (17 + 256) (Bus read/write transaction error local interrupt) + * 0:Reserved; 1:Bus read error; 2:Bus write error; 3:PMP error caused by load instructions; 4:PMP error caused by store instructions; 5:PMA error caused by load instructions; 6:PMA error caused by store instructions + */ +#define CSR_MDCAUSE_MDCAUSE_MASK (0x7U) +#define CSR_MDCAUSE_MDCAUSE_SHIFT (0U) +#define CSR_MDCAUSE_MDCAUSE_SET(x) (((uint32_t)(x) << CSR_MDCAUSE_MDCAUSE_SHIFT) & CSR_MDCAUSE_MDCAUSE_MASK) +#define CSR_MDCAUSE_MDCAUSE_GET(x) (((uint32_t)(x) & CSR_MDCAUSE_MDCAUSE_MASK) >> CSR_MDCAUSE_MDCAUSE_SHIFT) + +/* Bitfield definition for register: MCACHE_CTL */ +/* + * IC_FIRST_WORD (RO) + * + * Cache miss allocation filling policy + * 0:Cache line data is returned critical (double) word first + * 1:Cache line data is returned the lowest address (double) word first + */ +#define CSR_MCACHE_CTL_IC_FIRST_WORD_MASK (0x800U) +#define CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT (11U) +#define CSR_MCACHE_CTL_IC_FIRST_WORD_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_FIRST_WORD_MASK) >> CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT) + +/* + * CCTL_SUEN (RW) + * + * Enable bit for Superuser-mode and User-mode software to access ucctlbeginaddr and ucctlcommand CSRs + * 0:Disable ucctlbeginaddr and ucctlcommand accesses in S/U mode + * 1:Enable ucctlbeginaddr and ucctlcommand accesses in S/U mode + */ +#define CSR_MCACHE_CTL_CCTL_SUEN_MASK (0x100U) +#define CSR_MCACHE_CTL_CCTL_SUEN_SHIFT (8U) +#define CSR_MCACHE_CTL_CCTL_SUEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_CCTL_SUEN_SHIFT) & CSR_MCACHE_CTL_CCTL_SUEN_MASK) +#define CSR_MCACHE_CTL_CCTL_SUEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_CCTL_SUEN_MASK) >> CSR_MCACHE_CTL_CCTL_SUEN_SHIFT) + +/* + * DC_RWECC (RW) + * + * Controls diagnostic accesses of ECC codes of the data cache RAMs. It is set to enable CCTL operations to access the ECC codes. This bit can be set for injecting ECC errors to test the ECC handler + * 0:Disable diagnostic accesses of ECC codes + * 1:Enable diagnostic accesses of ECC codes + */ +#define CSR_MCACHE_CTL_DC_RWECC_MASK (0x80U) +#define CSR_MCACHE_CTL_DC_RWECC_SHIFT (7U) +#define CSR_MCACHE_CTL_DC_RWECC_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_RWECC_SHIFT) & CSR_MCACHE_CTL_DC_RWECC_MASK) +#define CSR_MCACHE_CTL_DC_RWECC_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_RWECC_MASK) >> CSR_MCACHE_CTL_DC_RWECC_SHIFT) + +/* + * IC_RWECC (RW) + * + * Controls diagnostic accesses of ECC codes of the instruction cache RAMs. It is set to enable CCTL operations to access the ECC codes . This bit can be set for injecting ECC errors to test the ECC handler. + * 0:Disable diagnostic accesses of ECC codes + * 1:Enable diagnostic accesses of ECC codes + */ +#define CSR_MCACHE_CTL_IC_RWECC_MASK (0x40U) +#define CSR_MCACHE_CTL_IC_RWECC_SHIFT (6U) +#define CSR_MCACHE_CTL_IC_RWECC_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_RWECC_SHIFT) & CSR_MCACHE_CTL_IC_RWECC_MASK) +#define CSR_MCACHE_CTL_IC_RWECC_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_RWECC_MASK) >> CSR_MCACHE_CTL_IC_RWECC_SHIFT) + +/* + * DC_ECCEN (RW) + * + * Parity/ECC error checking enable control for the + * data cache. + * 0:Disable parity/ECC + * 1:Reserved + * 2:Generate exceptions only on uncorrectable parity/ECC errors + * 3:Generate exceptions on any type of parity/ECC errors + */ +#define CSR_MCACHE_CTL_DC_ECCEN_MASK (0x30U) +#define CSR_MCACHE_CTL_DC_ECCEN_SHIFT (4U) +#define CSR_MCACHE_CTL_DC_ECCEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_ECCEN_SHIFT) & CSR_MCACHE_CTL_DC_ECCEN_MASK) +#define CSR_MCACHE_CTL_DC_ECCEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_ECCEN_MASK) >> CSR_MCACHE_CTL_DC_ECCEN_SHIFT) + +/* + * IC_ECCEN (RW) + * + * Parity/ECC error checking enable control for the + * instruction cache + * 0:Disable parity/ECC + * 1:Reserved + * 2:Generate exceptions only on uncorrectable parity/ECC errors + * 3:Generate exceptions on any type of parity/ECC errors + */ +#define CSR_MCACHE_CTL_IC_ECCEN_MASK (0xCU) +#define CSR_MCACHE_CTL_IC_ECCEN_SHIFT (2U) +#define CSR_MCACHE_CTL_IC_ECCEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_ECCEN_SHIFT) & CSR_MCACHE_CTL_IC_ECCEN_MASK) +#define CSR_MCACHE_CTL_IC_ECCEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_ECCEN_MASK) >> CSR_MCACHE_CTL_IC_ECCEN_SHIFT) + +/* + * DC_EN (RW) + * + * Controls if the data cache is enabled or not. + * 0:D-Cache is disabled + * 1:D-Cache is enabled + */ +#define CSR_MCACHE_CTL_DC_EN_MASK (0x2U) +#define CSR_MCACHE_CTL_DC_EN_SHIFT (1U) +#define CSR_MCACHE_CTL_DC_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_EN_SHIFT) & CSR_MCACHE_CTL_DC_EN_MASK) +#define CSR_MCACHE_CTL_DC_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_EN_MASK) >> CSR_MCACHE_CTL_DC_EN_SHIFT) + +/* + * IC_EN (RW) + * + * Controls if the instruction cache is enabled or not. + * 0:I-Cache is disabled + * 1:I-Cache is enabled + */ +#define CSR_MCACHE_CTL_IC_EN_MASK (0x1U) +#define CSR_MCACHE_CTL_IC_EN_SHIFT (0U) +#define CSR_MCACHE_CTL_IC_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_EN_SHIFT) & CSR_MCACHE_CTL_IC_EN_MASK) +#define CSR_MCACHE_CTL_IC_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_EN_MASK) >> CSR_MCACHE_CTL_IC_EN_SHIFT) + +/* Bitfield definition for register: MCCTLBEGINADDR */ +/* + * VA (RW) + * + * This register holds the address information required by CCTL operations + */ +#define CSR_MCCTLBEGINADDR_VA_MASK (0xFFFFFFFFUL) +#define CSR_MCCTLBEGINADDR_VA_SHIFT (0U) +#define CSR_MCCTLBEGINADDR_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLBEGINADDR_VA_SHIFT) & CSR_MCCTLBEGINADDR_VA_MASK) +#define CSR_MCCTLBEGINADDR_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLBEGINADDR_VA_MASK) >> CSR_MCCTLBEGINADDR_VA_SHIFT) + +/* Bitfield definition for register: MCCTLCOMMAND */ +/* + * VA (RW) + * + * See CCTL Command Definition Table + */ +#define CSR_MCCTLCOMMAND_VA_MASK (0x1FU) +#define CSR_MCCTLCOMMAND_VA_SHIFT (0U) +#define CSR_MCCTLCOMMAND_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLCOMMAND_VA_SHIFT) & CSR_MCCTLCOMMAND_VA_MASK) +#define CSR_MCCTLCOMMAND_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLCOMMAND_VA_MASK) >> CSR_MCCTLCOMMAND_VA_SHIFT) + +/* Bitfield definition for register: MCCTLDATA */ +/* + * VA (RW) + * + * See CCTL Commands Which Access mcctldata Table + */ +#define CSR_MCCTLDATA_VA_MASK (0x1FU) +#define CSR_MCCTLDATA_VA_SHIFT (0U) +#define CSR_MCCTLDATA_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLDATA_VA_SHIFT) & CSR_MCCTLDATA_VA_MASK) +#define CSR_MCCTLDATA_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLDATA_VA_MASK) >> CSR_MCCTLDATA_VA_SHIFT) + +/* Bitfield definition for register: MCOUNTERWEN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_HPM6_MASK (0x40U) +#define CSR_MCOUNTERWEN_HPM6_SHIFT (6U) +#define CSR_MCOUNTERWEN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM6_SHIFT) & CSR_MCOUNTERWEN_HPM6_MASK) +#define CSR_MCOUNTERWEN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM6_MASK) >> CSR_MCOUNTERWEN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_HPM5_MASK (0x20U) +#define CSR_MCOUNTERWEN_HPM5_SHIFT (5U) +#define CSR_MCOUNTERWEN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM5_SHIFT) & CSR_MCOUNTERWEN_HPM5_MASK) +#define CSR_MCOUNTERWEN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM5_MASK) >> CSR_MCOUNTERWEN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_HPM4_MASK (0x10U) +#define CSR_MCOUNTERWEN_HPM4_SHIFT (4U) +#define CSR_MCOUNTERWEN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM4_SHIFT) & CSR_MCOUNTERWEN_HPM4_MASK) +#define CSR_MCOUNTERWEN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM4_MASK) >> CSR_MCOUNTERWEN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_HPM3_MASK (0x8U) +#define CSR_MCOUNTERWEN_HPM3_SHIFT (3U) +#define CSR_MCOUNTERWEN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM3_SHIFT) & CSR_MCOUNTERWEN_HPM3_MASK) +#define CSR_MCOUNTERWEN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM3_MASK) >> CSR_MCOUNTERWEN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_IR_MASK (0x4U) +#define CSR_MCOUNTERWEN_IR_SHIFT (2U) +#define CSR_MCOUNTERWEN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_IR_SHIFT) & CSR_MCOUNTERWEN_IR_MASK) +#define CSR_MCOUNTERWEN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_IR_MASK) >> CSR_MCOUNTERWEN_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_CY_MASK (0x1U) +#define CSR_MCOUNTERWEN_CY_SHIFT (0U) +#define CSR_MCOUNTERWEN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_CY_SHIFT) & CSR_MCOUNTERWEN_CY_MASK) +#define CSR_MCOUNTERWEN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_CY_MASK) >> CSR_MCOUNTERWEN_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTERINTEN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_HPM6_MASK (0x40U) +#define CSR_MCOUNTERINTEN_HPM6_SHIFT (6U) +#define CSR_MCOUNTERINTEN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM6_SHIFT) & CSR_MCOUNTERINTEN_HPM6_MASK) +#define CSR_MCOUNTERINTEN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM6_MASK) >> CSR_MCOUNTERINTEN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_HPM5_MASK (0x20U) +#define CSR_MCOUNTERINTEN_HPM5_SHIFT (5U) +#define CSR_MCOUNTERINTEN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM5_SHIFT) & CSR_MCOUNTERINTEN_HPM5_MASK) +#define CSR_MCOUNTERINTEN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM5_MASK) >> CSR_MCOUNTERINTEN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_HPM4_MASK (0x10U) +#define CSR_MCOUNTERINTEN_HPM4_SHIFT (4U) +#define CSR_MCOUNTERINTEN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM4_SHIFT) & CSR_MCOUNTERINTEN_HPM4_MASK) +#define CSR_MCOUNTERINTEN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM4_MASK) >> CSR_MCOUNTERINTEN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_HPM3_MASK (0x8U) +#define CSR_MCOUNTERINTEN_HPM3_SHIFT (3U) +#define CSR_MCOUNTERINTEN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM3_SHIFT) & CSR_MCOUNTERINTEN_HPM3_MASK) +#define CSR_MCOUNTERINTEN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM3_MASK) >> CSR_MCOUNTERINTEN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_IR_MASK (0x4U) +#define CSR_MCOUNTERINTEN_IR_SHIFT (2U) +#define CSR_MCOUNTERINTEN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_IR_SHIFT) & CSR_MCOUNTERINTEN_IR_MASK) +#define CSR_MCOUNTERINTEN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_IR_MASK) >> CSR_MCOUNTERINTEN_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_CY_MASK (0x1U) +#define CSR_MCOUNTERINTEN_CY_SHIFT (0U) +#define CSR_MCOUNTERINTEN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_CY_SHIFT) & CSR_MCOUNTERINTEN_CY_MASK) +#define CSR_MCOUNTERINTEN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_CY_MASK) >> CSR_MCOUNTERINTEN_CY_SHIFT) + +/* Bitfield definition for register: MMISC_CTL */ +/* + * MSA_UNA (RW) + * + * This field controls whether the load/store instructions can access misaligned memory locations without generating Address Misaligned exceptions. + * Supported instructions: LW/LH/LHU/SW/SH + * 0:Misaligned accesses generate Address Misaligned exceptions. + * 1:Misaligned accesses generate Address Misaligned exceptions. + */ +#define CSR_MMISC_CTL_MSA_UNA_MASK (0x40U) +#define CSR_MMISC_CTL_MSA_UNA_SHIFT (6U) +#define CSR_MMISC_CTL_MSA_UNA_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_MSA_UNA_SHIFT) & CSR_MMISC_CTL_MSA_UNA_MASK) +#define CSR_MMISC_CTL_MSA_UNA_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_MSA_UNA_MASK) >> CSR_MMISC_CTL_MSA_UNA_SHIFT) + +/* + * BRPE (RW) + * + * Branch prediction enable bit. This bit controls all branch prediction structures. + * 0:Disabled + * 1:Enabled + * This bit is hardwired to 0 if branch prediction structure is not supported. + */ +#define CSR_MMISC_CTL_BRPE_MASK (0x8U) +#define CSR_MMISC_CTL_BRPE_SHIFT (3U) +#define CSR_MMISC_CTL_BRPE_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_BRPE_SHIFT) & CSR_MMISC_CTL_BRPE_MASK) +#define CSR_MMISC_CTL_BRPE_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_BRPE_MASK) >> CSR_MMISC_CTL_BRPE_SHIFT) + +/* + * RVCOMPM (RW) + * + * RISC-V compatibility mode enable bit. If the compatibility mode is turned on, all specific instructions become reserved instructions + * 0:Disabled + * 1:Enabled + */ +#define CSR_MMISC_CTL_RVCOMPM_MASK (0x4U) +#define CSR_MMISC_CTL_RVCOMPM_SHIFT (2U) +#define CSR_MMISC_CTL_RVCOMPM_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_RVCOMPM_SHIFT) & CSR_MMISC_CTL_RVCOMPM_MASK) +#define CSR_MMISC_CTL_RVCOMPM_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_RVCOMPM_MASK) >> CSR_MMISC_CTL_RVCOMPM_SHIFT) + +/* + * VEC_PLIC (RW) + * + * Selects the operation mode of PLIC: + * 0:Regular mode + * 1:Vector mode + * Please note that both this bit and the vector mode enable bit (VECTORED) of the Feature Enable Register in NCEPLIC100 should be turned on for the vectored interrupt support to work correctly. This bit is hardwired to 0 if the vectored PLIC feature is not supported. + */ +#define CSR_MMISC_CTL_VEC_PLIC_MASK (0x2U) +#define CSR_MMISC_CTL_VEC_PLIC_SHIFT (1U) +#define CSR_MMISC_CTL_VEC_PLIC_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_VEC_PLIC_SHIFT) & CSR_MMISC_CTL_VEC_PLIC_MASK) +#define CSR_MMISC_CTL_VEC_PLIC_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_VEC_PLIC_MASK) >> CSR_MMISC_CTL_VEC_PLIC_SHIFT) + +/* Bitfield definition for register: MCOUNTERMASK_M */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_HPM6_MASK (0x40U) +#define CSR_MCOUNTERMASK_M_HPM6_SHIFT (6U) +#define CSR_MCOUNTERMASK_M_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM6_SHIFT) & CSR_MCOUNTERMASK_M_HPM6_MASK) +#define CSR_MCOUNTERMASK_M_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM6_MASK) >> CSR_MCOUNTERMASK_M_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_HPM5_MASK (0x20U) +#define CSR_MCOUNTERMASK_M_HPM5_SHIFT (5U) +#define CSR_MCOUNTERMASK_M_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM5_SHIFT) & CSR_MCOUNTERMASK_M_HPM5_MASK) +#define CSR_MCOUNTERMASK_M_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM5_MASK) >> CSR_MCOUNTERMASK_M_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_HPM4_MASK (0x10U) +#define CSR_MCOUNTERMASK_M_HPM4_SHIFT (4U) +#define CSR_MCOUNTERMASK_M_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM4_SHIFT) & CSR_MCOUNTERMASK_M_HPM4_MASK) +#define CSR_MCOUNTERMASK_M_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM4_MASK) >> CSR_MCOUNTERMASK_M_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_HPM3_MASK (0x8U) +#define CSR_MCOUNTERMASK_M_HPM3_SHIFT (3U) +#define CSR_MCOUNTERMASK_M_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM3_SHIFT) & CSR_MCOUNTERMASK_M_HPM3_MASK) +#define CSR_MCOUNTERMASK_M_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM3_MASK) >> CSR_MCOUNTERMASK_M_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_IR_MASK (0x4U) +#define CSR_MCOUNTERMASK_M_IR_SHIFT (2U) +#define CSR_MCOUNTERMASK_M_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_IR_SHIFT) & CSR_MCOUNTERMASK_M_IR_MASK) +#define CSR_MCOUNTERMASK_M_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_IR_MASK) >> CSR_MCOUNTERMASK_M_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_CY_MASK (0x1U) +#define CSR_MCOUNTERMASK_M_CY_SHIFT (0U) +#define CSR_MCOUNTERMASK_M_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_CY_SHIFT) & CSR_MCOUNTERMASK_M_CY_MASK) +#define CSR_MCOUNTERMASK_M_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_CY_MASK) >> CSR_MCOUNTERMASK_M_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTERMASK_S */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_HPM6_MASK (0x40U) +#define CSR_MCOUNTERMASK_S_HPM6_SHIFT (6U) +#define CSR_MCOUNTERMASK_S_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM6_SHIFT) & CSR_MCOUNTERMASK_S_HPM6_MASK) +#define CSR_MCOUNTERMASK_S_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM6_MASK) >> CSR_MCOUNTERMASK_S_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_HPM5_MASK (0x20U) +#define CSR_MCOUNTERMASK_S_HPM5_SHIFT (5U) +#define CSR_MCOUNTERMASK_S_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM5_SHIFT) & CSR_MCOUNTERMASK_S_HPM5_MASK) +#define CSR_MCOUNTERMASK_S_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM5_MASK) >> CSR_MCOUNTERMASK_S_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_HPM4_MASK (0x10U) +#define CSR_MCOUNTERMASK_S_HPM4_SHIFT (4U) +#define CSR_MCOUNTERMASK_S_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM4_SHIFT) & CSR_MCOUNTERMASK_S_HPM4_MASK) +#define CSR_MCOUNTERMASK_S_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM4_MASK) >> CSR_MCOUNTERMASK_S_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_HPM3_MASK (0x8U) +#define CSR_MCOUNTERMASK_S_HPM3_SHIFT (3U) +#define CSR_MCOUNTERMASK_S_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM3_SHIFT) & CSR_MCOUNTERMASK_S_HPM3_MASK) +#define CSR_MCOUNTERMASK_S_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM3_MASK) >> CSR_MCOUNTERMASK_S_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_IR_MASK (0x4U) +#define CSR_MCOUNTERMASK_S_IR_SHIFT (2U) +#define CSR_MCOUNTERMASK_S_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_IR_SHIFT) & CSR_MCOUNTERMASK_S_IR_MASK) +#define CSR_MCOUNTERMASK_S_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_IR_MASK) >> CSR_MCOUNTERMASK_S_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_CY_MASK (0x1U) +#define CSR_MCOUNTERMASK_S_CY_SHIFT (0U) +#define CSR_MCOUNTERMASK_S_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_CY_SHIFT) & CSR_MCOUNTERMASK_S_CY_MASK) +#define CSR_MCOUNTERMASK_S_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_CY_MASK) >> CSR_MCOUNTERMASK_S_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTERMASK_U */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_HPM6_MASK (0x40U) +#define CSR_MCOUNTERMASK_U_HPM6_SHIFT (6U) +#define CSR_MCOUNTERMASK_U_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM6_SHIFT) & CSR_MCOUNTERMASK_U_HPM6_MASK) +#define CSR_MCOUNTERMASK_U_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM6_MASK) >> CSR_MCOUNTERMASK_U_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_HPM5_MASK (0x20U) +#define CSR_MCOUNTERMASK_U_HPM5_SHIFT (5U) +#define CSR_MCOUNTERMASK_U_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM5_SHIFT) & CSR_MCOUNTERMASK_U_HPM5_MASK) +#define CSR_MCOUNTERMASK_U_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM5_MASK) >> CSR_MCOUNTERMASK_U_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_HPM4_MASK (0x10U) +#define CSR_MCOUNTERMASK_U_HPM4_SHIFT (4U) +#define CSR_MCOUNTERMASK_U_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM4_SHIFT) & CSR_MCOUNTERMASK_U_HPM4_MASK) +#define CSR_MCOUNTERMASK_U_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM4_MASK) >> CSR_MCOUNTERMASK_U_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_HPM3_MASK (0x8U) +#define CSR_MCOUNTERMASK_U_HPM3_SHIFT (3U) +#define CSR_MCOUNTERMASK_U_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM3_SHIFT) & CSR_MCOUNTERMASK_U_HPM3_MASK) +#define CSR_MCOUNTERMASK_U_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM3_MASK) >> CSR_MCOUNTERMASK_U_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_IR_MASK (0x4U) +#define CSR_MCOUNTERMASK_U_IR_SHIFT (2U) +#define CSR_MCOUNTERMASK_U_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_IR_SHIFT) & CSR_MCOUNTERMASK_U_IR_MASK) +#define CSR_MCOUNTERMASK_U_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_IR_MASK) >> CSR_MCOUNTERMASK_U_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_CY_MASK (0x1U) +#define CSR_MCOUNTERMASK_U_CY_SHIFT (0U) +#define CSR_MCOUNTERMASK_U_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_CY_SHIFT) & CSR_MCOUNTERMASK_U_CY_MASK) +#define CSR_MCOUNTERMASK_U_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_CY_MASK) >> CSR_MCOUNTERMASK_U_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTEROVF */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_HPM6_MASK (0x40U) +#define CSR_MCOUNTEROVF_HPM6_SHIFT (6U) +#define CSR_MCOUNTEROVF_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM6_SHIFT) & CSR_MCOUNTEROVF_HPM6_MASK) +#define CSR_MCOUNTEROVF_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM6_MASK) >> CSR_MCOUNTEROVF_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_HPM5_MASK (0x20U) +#define CSR_MCOUNTEROVF_HPM5_SHIFT (5U) +#define CSR_MCOUNTEROVF_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM5_SHIFT) & CSR_MCOUNTEROVF_HPM5_MASK) +#define CSR_MCOUNTEROVF_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM5_MASK) >> CSR_MCOUNTEROVF_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_HPM4_MASK (0x10U) +#define CSR_MCOUNTEROVF_HPM4_SHIFT (4U) +#define CSR_MCOUNTEROVF_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM4_SHIFT) & CSR_MCOUNTEROVF_HPM4_MASK) +#define CSR_MCOUNTEROVF_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM4_MASK) >> CSR_MCOUNTEROVF_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_HPM3_MASK (0x8U) +#define CSR_MCOUNTEROVF_HPM3_SHIFT (3U) +#define CSR_MCOUNTEROVF_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM3_SHIFT) & CSR_MCOUNTEROVF_HPM3_MASK) +#define CSR_MCOUNTEROVF_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM3_MASK) >> CSR_MCOUNTEROVF_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_IR_MASK (0x4U) +#define CSR_MCOUNTEROVF_IR_SHIFT (2U) +#define CSR_MCOUNTEROVF_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_IR_SHIFT) & CSR_MCOUNTEROVF_IR_MASK) +#define CSR_MCOUNTEROVF_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_IR_MASK) >> CSR_MCOUNTEROVF_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_CY_MASK (0x1U) +#define CSR_MCOUNTEROVF_CY_SHIFT (0U) +#define CSR_MCOUNTEROVF_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_CY_SHIFT) & CSR_MCOUNTEROVF_CY_MASK) +#define CSR_MCOUNTEROVF_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_CY_MASK) >> CSR_MCOUNTEROVF_CY_SHIFT) + +/* Bitfield definition for register: DEXC2DBG */ +/* + * PMOV (RW) + * + * Indicates whether performance counter overflow interrupts are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_PMOV_MASK (0x80000UL) +#define CSR_DEXC2DBG_PMOV_SHIFT (19U) +#define CSR_DEXC2DBG_PMOV_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_PMOV_SHIFT) & CSR_DEXC2DBG_PMOV_MASK) +#define CSR_DEXC2DBG_PMOV_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_PMOV_MASK) >> CSR_DEXC2DBG_PMOV_SHIFT) + +/* + * BWE (RW) + * + * Indicates whether Bus-write Transaction Error local interrupts are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_BWE_MASK (0x8000U) +#define CSR_DEXC2DBG_BWE_SHIFT (15U) +#define CSR_DEXC2DBG_BWE_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_BWE_SHIFT) & CSR_DEXC2DBG_BWE_MASK) +#define CSR_DEXC2DBG_BWE_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_BWE_MASK) >> CSR_DEXC2DBG_BWE_SHIFT) + +/* + * SLPECC (RW) + * + * Indicates whether local memory slave port ECC Error local interrupts are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SLPECC_MASK (0x4000U) +#define CSR_DEXC2DBG_SLPECC_SHIFT (14U) +#define CSR_DEXC2DBG_SLPECC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SLPECC_SHIFT) & CSR_DEXC2DBG_SLPECC_MASK) +#define CSR_DEXC2DBG_SLPECC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SLPECC_MASK) >> CSR_DEXC2DBG_SLPECC_SHIFT) + +/* + * ACE (RW) + * + * Indicates whether ACE-related exceptions are redirected to enter Debug Mode. This bit is present only when mmsc_cfg.ACE is set + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_ACE_MASK (0x2000U) +#define CSR_DEXC2DBG_ACE_SHIFT (13U) +#define CSR_DEXC2DBG_ACE_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_ACE_SHIFT) & CSR_DEXC2DBG_ACE_MASK) +#define CSR_DEXC2DBG_ACE_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_ACE_MASK) >> CSR_DEXC2DBG_ACE_SHIFT) + +/* + * HSP (RW) + * + * Indicates whether Stack Protection exceptions are redirected to enter Debug Mode. This bit is present only when mmsc_cfg.HSP is set. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_HSP_MASK (0x1000U) +#define CSR_DEXC2DBG_HSP_SHIFT (12U) +#define CSR_DEXC2DBG_HSP_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_HSP_SHIFT) & CSR_DEXC2DBG_HSP_MASK) +#define CSR_DEXC2DBG_HSP_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_HSP_MASK) >> CSR_DEXC2DBG_HSP_SHIFT) + +/* + * MEC (RW) + * + * Indicates whether M-mode Environment Call exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_MEC_MASK (0x800U) +#define CSR_DEXC2DBG_MEC_SHIFT (11U) +#define CSR_DEXC2DBG_MEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_MEC_SHIFT) & CSR_DEXC2DBG_MEC_MASK) +#define CSR_DEXC2DBG_MEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_MEC_MASK) >> CSR_DEXC2DBG_MEC_SHIFT) + +/* + * UEC (RW) + * + * Indicates whether U-mode Environment Call exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_UEC_MASK (0x100U) +#define CSR_DEXC2DBG_UEC_SHIFT (8U) +#define CSR_DEXC2DBG_UEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_UEC_SHIFT) & CSR_DEXC2DBG_UEC_MASK) +#define CSR_DEXC2DBG_UEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_UEC_MASK) >> CSR_DEXC2DBG_UEC_SHIFT) + +/* + * SAF (RW) + * + * Indicates whether Store Access Fault exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SAF_MASK (0x80U) +#define CSR_DEXC2DBG_SAF_SHIFT (7U) +#define CSR_DEXC2DBG_SAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SAF_SHIFT) & CSR_DEXC2DBG_SAF_MASK) +#define CSR_DEXC2DBG_SAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SAF_MASK) >> CSR_DEXC2DBG_SAF_SHIFT) + +/* + * SAM (RW) + * + * Indicates whether Store Access Misaligned exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SAM_MASK (0x40U) +#define CSR_DEXC2DBG_SAM_SHIFT (6U) +#define CSR_DEXC2DBG_SAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SAM_SHIFT) & CSR_DEXC2DBG_SAM_MASK) +#define CSR_DEXC2DBG_SAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SAM_MASK) >> CSR_DEXC2DBG_SAM_SHIFT) + +/* + * LAF (RW) + * + * Indicates whether Load Access Fault exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_LAF_MASK (0x20U) +#define CSR_DEXC2DBG_LAF_SHIFT (5U) +#define CSR_DEXC2DBG_LAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LAF_SHIFT) & CSR_DEXC2DBG_LAF_MASK) +#define CSR_DEXC2DBG_LAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LAF_MASK) >> CSR_DEXC2DBG_LAF_SHIFT) + +/* + * LAM (RW) + * + * Indicates whether Load Access Misaligned exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_LAM_MASK (0x10U) +#define CSR_DEXC2DBG_LAM_SHIFT (4U) +#define CSR_DEXC2DBG_LAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LAM_SHIFT) & CSR_DEXC2DBG_LAM_MASK) +#define CSR_DEXC2DBG_LAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LAM_MASK) >> CSR_DEXC2DBG_LAM_SHIFT) + +/* + * NMI (RW) + * + * Indicates whether Non-Maskable Interrupt + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_NMI_MASK (0x8U) +#define CSR_DEXC2DBG_NMI_SHIFT (3U) +#define CSR_DEXC2DBG_NMI_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_NMI_SHIFT) & CSR_DEXC2DBG_NMI_MASK) +#define CSR_DEXC2DBG_NMI_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_NMI_MASK) >> CSR_DEXC2DBG_NMI_SHIFT) + +/* + * II (RW) + * + * Indicates whether Illegal Instruction exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_II_MASK (0x4U) +#define CSR_DEXC2DBG_II_SHIFT (2U) +#define CSR_DEXC2DBG_II_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_II_SHIFT) & CSR_DEXC2DBG_II_MASK) +#define CSR_DEXC2DBG_II_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_II_MASK) >> CSR_DEXC2DBG_II_SHIFT) + +/* + * IAF (RW) + * + * Indicates whether Instruction Access Fault exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_IAF_MASK (0x2U) +#define CSR_DEXC2DBG_IAF_SHIFT (1U) +#define CSR_DEXC2DBG_IAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IAF_SHIFT) & CSR_DEXC2DBG_IAF_MASK) +#define CSR_DEXC2DBG_IAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IAF_MASK) >> CSR_DEXC2DBG_IAF_SHIFT) + +/* + * IAM (RW) + * + * Indicates whether Instruction Access Misaligned exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_IAM_MASK (0x1U) +#define CSR_DEXC2DBG_IAM_SHIFT (0U) +#define CSR_DEXC2DBG_IAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IAM_SHIFT) & CSR_DEXC2DBG_IAM_MASK) +#define CSR_DEXC2DBG_IAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IAM_MASK) >> CSR_DEXC2DBG_IAM_SHIFT) + +/* Bitfield definition for register: DDCAUSE */ +/* + * SUBTYPE (RO) + * + * Subtypes for main type. + * The table below lists the subtypes for DCSR.CAUSE==1 and DDCAUSE.MAINTYPE==3. + * 0:Illegal instruction + * 1:Privileged instruction + * 2:Non-existent CSR + * 3:Privilege CSR access + * 4:Read-only CSR update + */ +#define CSR_DDCAUSE_SUBTYPE_MASK (0xFF00U) +#define CSR_DDCAUSE_SUBTYPE_SHIFT (8U) +#define CSR_DDCAUSE_SUBTYPE_GET(x) (((uint32_t)(x) & CSR_DDCAUSE_SUBTYPE_MASK) >> CSR_DDCAUSE_SUBTYPE_SHIFT) + +/* + * MAINTYPE (RO) + * + * Cause for redirection to Debug Mode. + * 0:Software Breakpoint (EBREAK) + * 1:Instruction Access Misaligned (IAM) + * 2:Instruction Access Fault (IAF) + * 3:Illegal Instruction (II) + * 4:Non-Maskable Interrupt (NMI) + * 5:Load Access Misaligned (LAM) + * 6:Load Access Fault (LAF) + * 7:Store Access Misaligned (SAM) + * 8:Store Access Fault (SAF) + * 9:U-mode Environment Call (UEC) + * 10:S-mode Environment Call (SEC) + * 11:Instruction page fault + * 12:M-mode Environment Call (MEC) + * 13:Load page fault + * 14:Reserved + * 15:Store/AMO page fault + * 16:Imprecise ECC error + * 17;Bus write transaction error + * 18:Performance Counter overflow + * 19–31:Reserved + * 32:Stack overflow exception + * 33:Stack underflow exception + * 34:ACE disabled exception + * 35–39:Reserved + * 40–47:ACE exception + * ≥48:Reserved + */ +#define CSR_DDCAUSE_MAINTYPE_MASK (0xFFU) +#define CSR_DDCAUSE_MAINTYPE_SHIFT (0U) +#define CSR_DDCAUSE_MAINTYPE_GET(x) (((uint32_t)(x) & CSR_DDCAUSE_MAINTYPE_MASK) >> CSR_DDCAUSE_MAINTYPE_SHIFT) + +/* Bitfield definition for register: UITB */ +/* + * ADDR (RW) + * + * The base address of the CoDense instruction table. This field is reserved if uitb.HW == 1. + */ +#define CSR_UITB_ADDR_MASK (0xFFFFFFFCUL) +#define CSR_UITB_ADDR_SHIFT (2U) +#define CSR_UITB_ADDR_SET(x) (((uint32_t)(x) << CSR_UITB_ADDR_SHIFT) & CSR_UITB_ADDR_MASK) +#define CSR_UITB_ADDR_GET(x) (((uint32_t)(x) & CSR_UITB_ADDR_MASK) >> CSR_UITB_ADDR_SHIFT) + +/* + * HW (RO) + * + * This bit specifies if the CoDense instruction table is hardwired. + * 0:The instruction table is located in memory. uitb.ADDR should be initialized to point to the table before using the CoDense instructions. + * 1:The instruction table is hardwired. Initialization of uitb.ADDR is not needed before using the CoDense instructions. + */ +#define CSR_UITB_HW_MASK (0x1U) +#define CSR_UITB_HW_SHIFT (0U) +#define CSR_UITB_HW_GET(x) (((uint32_t)(x) & CSR_UITB_HW_MASK) >> CSR_UITB_HW_SHIFT) + +/* Bitfield definition for register: UCODE */ +/* + * OV (RW) + * + * Overflow flag. It will be set by DSP instructions with a saturated result. + * 0:A saturated result is not generated + * 1:A saturated result is generated + */ +#define CSR_UCODE_OV_MASK (0x1U) +#define CSR_UCODE_OV_SHIFT (0U) +#define CSR_UCODE_OV_SET(x) (((uint32_t)(x) << CSR_UCODE_OV_SHIFT) & CSR_UCODE_OV_MASK) +#define CSR_UCODE_OV_GET(x) (((uint32_t)(x) & CSR_UCODE_OV_MASK) >> CSR_UCODE_OV_SHIFT) + +/* Bitfield definition for register: UDCAUSE */ +/* + * UDCAUSE (RW) + * + * This register further disambiguates causes of traps recorded in the ucause register. See the list below for details. + * The value of UDCAUSE for precise exception: + * When ucause == 1 (Instruction access fault) + * 0:Reserved + * 1:ECC/Parity error + * 2:PMP instruction access violation + * 3:Bus error + * 4:PMA empty hole access + * When ucause == 2 (Illegal instruction) + * 0:Please parse the utval CSR + * 1:FP disabled exception + * 2:ACE disabled exception + * When ucause == 5 (Load access fault) + * 0:Reserved + * 1:ECC/Parity error + * 2:PMP load access violation + * 3:Bus error + * 4:Misaligned address + * 5:PMA empty hole access + * 6:PMA attribute inconsistency + * 7:PMA NAMO exception + * When ucause == 7 (Store access fault) + * 0:Reserved + * 1:ECC/Parity error + * 2:PMP store access violation + * 3:Bus error + * 4:Misaligned address + * 5:PMA empty hole access + * 6:PMA attribute inconsistency + * 7:PMA NAMO exception + */ +#define CSR_UDCAUSE_UDCAUSE_MASK (0x7U) +#define CSR_UDCAUSE_UDCAUSE_SHIFT (0U) +#define CSR_UDCAUSE_UDCAUSE_SET(x) (((uint32_t)(x) << CSR_UDCAUSE_UDCAUSE_SHIFT) & CSR_UDCAUSE_UDCAUSE_MASK) +#define CSR_UDCAUSE_UDCAUSE_GET(x) (((uint32_t)(x) & CSR_UDCAUSE_UDCAUSE_MASK) >> CSR_UDCAUSE_UDCAUSE_SHIFT) + +/* Bitfield definition for register: UCCTLBEGINADDR */ +/* + * VA (RW) + * + * It is an alias to the mcctlbeginaddr register and it is only accessible to Supervisor-mode and User-mode software when mcache_ctl.CCTL_SUEN is 1. Otherwise illegal instruction exceptions will be triggered. + */ +#define CSR_UCCTLBEGINADDR_VA_MASK (0xFFFFFFFFUL) +#define CSR_UCCTLBEGINADDR_VA_SHIFT (0U) +#define CSR_UCCTLBEGINADDR_VA_SET(x) (((uint32_t)(x) << CSR_UCCTLBEGINADDR_VA_SHIFT) & CSR_UCCTLBEGINADDR_VA_MASK) +#define CSR_UCCTLBEGINADDR_VA_GET(x) (((uint32_t)(x) & CSR_UCCTLBEGINADDR_VA_MASK) >> CSR_UCCTLBEGINADDR_VA_SHIFT) + +/* Bitfield definition for register: UCCTLCOMMAND */ +/* + * VA (RW) + * + * See User CCTL Command Definition Table + */ +#define CSR_UCCTLCOMMAND_VA_MASK (0x1FU) +#define CSR_UCCTLCOMMAND_VA_SHIFT (0U) +#define CSR_UCCTLCOMMAND_VA_SET(x) (((uint32_t)(x) << CSR_UCCTLCOMMAND_VA_SHIFT) & CSR_UCCTLCOMMAND_VA_MASK) +#define CSR_UCCTLCOMMAND_VA_GET(x) (((uint32_t)(x) & CSR_UCCTLCOMMAND_VA_MASK) >> CSR_UCCTLCOMMAND_VA_SHIFT) + +/* Bitfield definition for register: MICM_CFG */ +/* + * SETH (RO) + * + * This bit extends the ISET field. + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_SETH_MASK (0x1000000UL) +#define CSR_MICM_CFG_SETH_SHIFT (24U) +#define CSR_MICM_CFG_SETH_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_SETH_MASK) >> CSR_MICM_CFG_SETH_SHIFT) + +/* + * ILM_ECC (RO) + * + * ILM soft-error protection scheme + * 0:No parity/ECC + * 1:Parity + * 2:ECC + * 3:Reserved + * ILM is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ILM_ECC_MASK (0x600000UL) +#define CSR_MICM_CFG_ILM_ECC_SHIFT (21U) +#define CSR_MICM_CFG_ILM_ECC_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILM_ECC_MASK) >> CSR_MICM_CFG_ILM_ECC_SHIFT) + +/* + * ILMSZ (RO) + * + * ILM Size + * 0:0 Byte + * 1:1 KiB + * 2:2 KiB + * 3:4 KiB + * 4:8 KiB + * 5:16 KiB + * 6:32 KiB + * 7:64 KiB + * 8:128 KiB + * 9:256 KiB + * 10:512 KiB + * 11:1 MiB + * 12:2 MiB + * 13:4 MiB + * 14:8 MiB + * 15:16 MiB + * 16-31:Reserved + * When ILM is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ILMSZ_MASK (0xF8000UL) +#define CSR_MICM_CFG_ILMSZ_SHIFT (15U) +#define CSR_MICM_CFG_ILMSZ_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILMSZ_MASK) >> CSR_MICM_CFG_ILMSZ_SHIFT) + +/* + * ILMB (RW) + * + * Number of ILM base registers present + * 0:No ILM base register present + * 1:One ILM base register present + * 2-7:Reserved + * When ILM is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ILMB_MASK (0x7000U) +#define CSR_MICM_CFG_ILMB_SHIFT (12U) +#define CSR_MICM_CFG_ILMB_SET(x) (((uint32_t)(x) << CSR_MICM_CFG_ILMB_SHIFT) & CSR_MICM_CFG_ILMB_MASK) +#define CSR_MICM_CFG_ILMB_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILMB_MASK) >> CSR_MICM_CFG_ILMB_SHIFT) + +/* + * IC_ECC (RO) + * + * Cache soft-error protection scheme + * 0:No parity/ECC + * 1:Parity + * 2:ECC + * 3:Reserved + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_IC_ECC_MASK (0xC00U) +#define CSR_MICM_CFG_IC_ECC_SHIFT (10U) +#define CSR_MICM_CFG_IC_ECC_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_IC_ECC_MASK) >> CSR_MICM_CFG_IC_ECC_SHIFT) + +/* + * ILCK (RO) + * + * I-Cache locking support + * 0:No locking support + * 1:With locking support + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ILCK_MASK (0x200U) +#define CSR_MICM_CFG_ILCK_SHIFT (9U) +#define CSR_MICM_CFG_ILCK_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILCK_MASK) >> CSR_MICM_CFG_ILCK_SHIFT) + +/* + * ISZ (RO) + * + * Cache block (line) size + * 0:No I-Cache + * 1:8 bytes + * 2:16 bytes + * 3:32 bytes + * 4:64 bytes + * 5:128 bytes + * 6-7:Reserved + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ISZ_MASK (0x1C0U) +#define CSR_MICM_CFG_ISZ_SHIFT (6U) +#define CSR_MICM_CFG_ISZ_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ISZ_MASK) >> CSR_MICM_CFG_ISZ_SHIFT) + +/* + * IWAY (RO) + * + * Associativity of I-Cache + * 0:Direct-mapped + * 1:2-way + * 2:3-way + * 3:4-way + * 4:5-way + * 5:6-way + * 6:7-way + * 7:8-way + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_IWAY_MASK (0x38U) +#define CSR_MICM_CFG_IWAY_SHIFT (3U) +#define CSR_MICM_CFG_IWAY_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_IWAY_MASK) >> CSR_MICM_CFG_IWAY_SHIFT) + +/* + * ISET (RO) + * + * I-Cache sets (# of cache lines per way): + * When micm_cfg.SETH==0: + * 0:64 + * 1:128 + * 2:256 + * 3:512 + * 4:1024 + * 5:2048 + * 6:4096 + * 7:Reserved + * When micm_cfg.SETH==1: + * 0:32 + * 1:16 + * 2:8 + * 3-7:Reserved + */ +#define CSR_MICM_CFG_ISET_MASK (0x7U) +#define CSR_MICM_CFG_ISET_SHIFT (0U) +#define CSR_MICM_CFG_ISET_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ISET_MASK) >> CSR_MICM_CFG_ISET_SHIFT) + +/* Bitfield definition for register: MDCM_CFG */ +/* + * SETH (RO) + * + * This bit extends the DSET field. + * When data cache is not configured, this field should be ignored + */ +#define CSR_MDCM_CFG_SETH_MASK (0x1000000UL) +#define CSR_MDCM_CFG_SETH_SHIFT (24U) +#define CSR_MDCM_CFG_SETH_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_SETH_MASK) >> CSR_MDCM_CFG_SETH_SHIFT) + +/* + * DLM_ECC (RO) + * + * DLM soft-error protection scheme + * 0:No parity/ECC + * 1:Parity + * 2:ECC + * 3:Reserved + * When DLM is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DLM_ECC_MASK (0x600000UL) +#define CSR_MDCM_CFG_DLM_ECC_SHIFT (21U) +#define CSR_MDCM_CFG_DLM_ECC_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLM_ECC_MASK) >> CSR_MDCM_CFG_DLM_ECC_SHIFT) + +/* + * DLMSZ (RO) + * + * DLM Size + * 0:0 Byte + * 1:1 KiB + * 2:2 KiB + * 3:4 KiB + * 4:8 KiB + * 5:16 KiB + * 6:32 KiB + * 7:64 KiB + * 8:128 KiB + * 9:256 KiB + * 10:512 KiB + * 11:1 MiB + * 12:2 MiB + * 13:4 MiB + * 14:8 MiB + * 15:16 MiB + * 16-31:Reserved + * When ILM is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DLMSZ_MASK (0xF8000UL) +#define CSR_MDCM_CFG_DLMSZ_SHIFT (15U) +#define CSR_MDCM_CFG_DLMSZ_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLMSZ_MASK) >> CSR_MDCM_CFG_DLMSZ_SHIFT) + +/* + * DLMB (RO) + * + * Number of DLM base registers present + * 0:No DLM base register present + * 1:One DLM base register present + * 2-7:Reserved + * When DLM is not configured, this field should be ignored + */ +#define CSR_MDCM_CFG_DLMB_MASK (0x7000U) +#define CSR_MDCM_CFG_DLMB_SHIFT (12U) +#define CSR_MDCM_CFG_DLMB_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLMB_MASK) >> CSR_MDCM_CFG_DLMB_SHIFT) + +/* + * DC_ECC (RO) + * + * Cache soft-error protection scheme + * 0:No parity/ECC support + * 1:Has parity support + * 2:Has ECC support + * 3:Reserved + * When data cache is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DC_ECC_MASK (0xC00U) +#define CSR_MDCM_CFG_DC_ECC_SHIFT (10U) +#define CSR_MDCM_CFG_DC_ECC_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DC_ECC_MASK) >> CSR_MDCM_CFG_DC_ECC_SHIFT) + +/* + * DLCK (RO) + * + * D-Cache locking support + * 0:No locking support + * 1:With locking support + * When data cache is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DLCK_MASK (0x200U) +#define CSR_MDCM_CFG_DLCK_SHIFT (9U) +#define CSR_MDCM_CFG_DLCK_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLCK_MASK) >> CSR_MDCM_CFG_DLCK_SHIFT) + +/* + * DSZ (RO) + * + * Cache block (line) size + * 0:No I-Cache + * 1:8 bytes + * 2:16 bytes + * 3:32 bytes + * 4:64 bytes + * 5:128 bytes + * 6-7:Reserved + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DSZ_MASK (0x1C0U) +#define CSR_MDCM_CFG_DSZ_SHIFT (6U) +#define CSR_MDCM_CFG_DSZ_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DSZ_MASK) >> CSR_MDCM_CFG_DSZ_SHIFT) + +/* + * DWAY (RO) + * + * Associativity of D-Cache + * 0:Direct-mapped + * 1:2-way + * 2:3-way + * 3:4-way + * 4:5-way + * 5:6-way + * 6:7-way + * 7:8-way + * When data cache is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DWAY_MASK (0x38U) +#define CSR_MDCM_CFG_DWAY_SHIFT (3U) +#define CSR_MDCM_CFG_DWAY_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DWAY_MASK) >> CSR_MDCM_CFG_DWAY_SHIFT) + +/* + * DSET (RO) + * + * D-Cache sets (# of cache lines per way): + * When mdcm_cfg.SETH==0: + * 0:64 + * 1:128 + * 2:256 + * 3:512 + * 4:1024 + * 5:2048 + * 6:4096 + * 7:Reserved + * When mdcm_cfg.SETH==1: + * 0:32 + * 1:16 + * 2:8 + * 3-7:Reserved + * When data cache is not configured, this field should be ignored + */ +#define CSR_MDCM_CFG_DSET_MASK (0x7U) +#define CSR_MDCM_CFG_DSET_SHIFT (0U) +#define CSR_MDCM_CFG_DSET_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DSET_MASK) >> CSR_MDCM_CFG_DSET_SHIFT) + +/* Bitfield definition for register: MMSC_CFG */ +/* + * MSC_EXT (RO) + * + * Indicates if the mmsc_cfg2 CSR is present or not. + * 0:The mmsc_cfg2 CSR is not present. + * 1:The mmsc_cfg2 CSR is present + */ +#define CSR_MMSC_CFG_MSC_EXT_MASK (0x80000000UL) +#define CSR_MMSC_CFG_MSC_EXT_SHIFT (31U) +#define CSR_MMSC_CFG_MSC_EXT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_MSC_EXT_MASK) >> CSR_MMSC_CFG_MSC_EXT_SHIFT) + +/* + * PPMA (RO) + * + * Indicates if programmable PMA setup with PMA region CSRs is supported or not + * 0:Programmable PMA setup is not supported. + * 1:Programmable PMA setup is supported. + */ +#define CSR_MMSC_CFG_PPMA_MASK (0x40000000UL) +#define CSR_MMSC_CFG_PPMA_SHIFT (30U) +#define CSR_MMSC_CFG_PPMA_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PPMA_MASK) >> CSR_MMSC_CFG_PPMA_SHIFT) + +/* + * EDSP (RO) + * + * Indicates if the DSP extension is supported or not + * 0:The DSP extension is not supported. + * 1:The DSP extension is supported. + */ +#define CSR_MMSC_CFG_EDSP_MASK (0x20000000UL) +#define CSR_MMSC_CFG_EDSP_SHIFT (29U) +#define CSR_MMSC_CFG_EDSP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EDSP_MASK) >> CSR_MMSC_CFG_EDSP_SHIFT) + +/* + * VCCTL (RO) + * + * Indicates the version number of CCTL command operation scheme supported by an implementation + * 0:instruction cache and data cache are not configured. + * 1:instruction cache or data cache is configured. + */ +#define CSR_MMSC_CFG_VCCTL_MASK (0xC0000UL) +#define CSR_MMSC_CFG_VCCTL_SHIFT (18U) +#define CSR_MMSC_CFG_VCCTL_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_VCCTL_MASK) >> CSR_MMSC_CFG_VCCTL_SHIFT) + +/* + * EFHW (RO) + * + * Indicates the support of FLHW and FSHW instructions + * 0:FLHW and FSHW instructions are not supported + * 1:FLHW and FSHW instructions are supported. + */ +#define CSR_MMSC_CFG_EFHW_MASK (0x20000UL) +#define CSR_MMSC_CFG_EFHW_SHIFT (17U) +#define CSR_MMSC_CFG_EFHW_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EFHW_MASK) >> CSR_MMSC_CFG_EFHW_SHIFT) + +/* + * CCTLCSR (RO) + * + * Indicates the presence of CSRs for CCTL operations. + * 0:Feature of CSRs for CCTL operations is not supported. + * 1:Feature of CSRs for CCTL operations is supported. + */ +#define CSR_MMSC_CFG_CCTLCSR_MASK (0x10000UL) +#define CSR_MMSC_CFG_CCTLCSR_SHIFT (16U) +#define CSR_MMSC_CFG_CCTLCSR_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_CCTLCSR_MASK) >> CSR_MMSC_CFG_CCTLCSR_SHIFT) + +/* + * PMNDS (RO) + * + * Indicates if Andes-enhanced performance monitoring feature is present or no. + * 0:Andes-enhanced performance monitoring feature is not supported. + * 1:Andes-enhanced performance monitoring feature is supported. + */ +#define CSR_MMSC_CFG_PMNDS_MASK (0x8000U) +#define CSR_MMSC_CFG_PMNDS_SHIFT (15U) +#define CSR_MMSC_CFG_PMNDS_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PMNDS_MASK) >> CSR_MMSC_CFG_PMNDS_SHIFT) + +/* + * LMSLVP (RO) + * + * Indicates if local memory slave port is present or not. + * 0:Local memory slave port is not present. + * 1:Local memory slave port is implemented. + */ +#define CSR_MMSC_CFG_LMSLVP_MASK (0x4000U) +#define CSR_MMSC_CFG_LMSLVP_SHIFT (14U) +#define CSR_MMSC_CFG_LMSLVP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_LMSLVP_MASK) >> CSR_MMSC_CFG_LMSLVP_SHIFT) + +/* + * EV5PE (RO) + * + * Indicates whether AndeStar V5 Performance Extension is implemented or not. D45 always implements AndeStar V5 Performance Extension. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_EV5PE_MASK (0x2000U) +#define CSR_MMSC_CFG_EV5PE_SHIFT (13U) +#define CSR_MMSC_CFG_EV5PE_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EV5PE_MASK) >> CSR_MMSC_CFG_EV5PE_SHIFT) + +/* + * VPLIC (RO) + * + * Indicates whether the Andes Vectored PLIC Extension is implemented or not. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_VPLIC_MASK (0x1000U) +#define CSR_MMSC_CFG_VPLIC_SHIFT (12U) +#define CSR_MMSC_CFG_VPLIC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_VPLIC_MASK) >> CSR_MMSC_CFG_VPLIC_SHIFT) + +/* + * ACE (RO) + * + * Indicates whether the Andes StackSafe hardware stack protection extension is implemented or not. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_ACE_MASK (0x40U) +#define CSR_MMSC_CFG_ACE_SHIFT (6U) +#define CSR_MMSC_CFG_ACE_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ACE_MASK) >> CSR_MMSC_CFG_ACE_SHIFT) + +/* + * HSP (RO) + * + * Indicates whether the Andes PowerBrake (Performance Throttling) power/performance scaling extension is implemented or not. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_HSP_MASK (0x20U) +#define CSR_MMSC_CFG_HSP_SHIFT (5U) +#define CSR_MMSC_CFG_HSP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_HSP_MASK) >> CSR_MMSC_CFG_HSP_SHIFT) + +/* + * PFT (RO) + * + * Indicates whether the Andes PowerBrake (Performance Throttling) power/performance scaling extension is implemented or not + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_PFT_MASK (0x10U) +#define CSR_MMSC_CFG_PFT_SHIFT (4U) +#define CSR_MMSC_CFG_PFT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PFT_MASK) >> CSR_MMSC_CFG_PFT_SHIFT) + +/* + * ECD (RO) + * + * Indicates whether the Andes CoDense Extension is implemented or not. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_ECD_MASK (0x8U) +#define CSR_MMSC_CFG_ECD_SHIFT (3U) +#define CSR_MMSC_CFG_ECD_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ECD_MASK) >> CSR_MMSC_CFG_ECD_SHIFT) + +/* + * TLB_ECC (RO) + * + * TLB parity/ECC support configuration. + * 0:No parity/ECC + * 1:Parity + * 2:ECC + * 3:Reserved + */ +#define CSR_MMSC_CFG_TLB_ECC_MASK (0x6U) +#define CSR_MMSC_CFG_TLB_ECC_SHIFT (1U) +#define CSR_MMSC_CFG_TLB_ECC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_TLB_ECC_MASK) >> CSR_MMSC_CFG_TLB_ECC_SHIFT) + +/* + * ECC (RO) + * + * Indicates whether the parity/ECC soft-error protection is implemented or not. + * 0:Not implemented. + * 1:Implemented. + * The specific parity/ECC scheme used for each protected RAM is specified by the control bits in the following list. + * micm_cfg.IC_ECC + * micm_cfg.ILM_ECC + * mdcm_cfg.DC_ECC + * mdcm_cfg.DLM_ECC + * mmsc_cfg.TLB_ECC + */ +#define CSR_MMSC_CFG_ECC_MASK (0x1U) +#define CSR_MMSC_CFG_ECC_SHIFT (0U) +#define CSR_MMSC_CFG_ECC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ECC_MASK) >> CSR_MMSC_CFG_ECC_SHIFT) + +/* Bitfield definition for register: MMSC_CFG2 */ +/* + * FINV (RO) + * + * Indicates if scalar FPU is implemented in VPU + * 0:Scalar FPU is not implemented in VPU + * 1:Scalar FPU is implemented in VPU + */ +#define CSR_MMSC_CFG2_FINV_MASK (0x20U) +#define CSR_MMSC_CFG2_FINV_SHIFT (5U) +#define CSR_MMSC_CFG2_FINV_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_FINV_MASK) >> CSR_MMSC_CFG2_FINV_SHIFT) + +/* + * ZFH (RO) + * + * Indicates if the FP16 half-precision floating-point extension (Zfh) is supported or not. + * 0:The FP16 extension is not supported. + * 1:The FP16 extension is supported + */ +#define CSR_MMSC_CFG2_ZFH_MASK (0x2U) +#define CSR_MMSC_CFG2_ZFH_SHIFT (1U) +#define CSR_MMSC_CFG2_ZFH_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_ZFH_MASK) >> CSR_MMSC_CFG2_ZFH_SHIFT) + +/* + * BF16CVT (RO) + * + * Indicates if the BFLOAT16 conversion extension + * is supported or not. + * 0:The BFLOAT16 conversion extension is not supported + * 1:The BFLOAT16 conversion extension is supported + */ +#define CSR_MMSC_CFG2_BF16CVT_MASK (0x1U) +#define CSR_MMSC_CFG2_BF16CVT_SHIFT (0U) +#define CSR_MMSC_CFG2_BF16CVT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_BF16CVT_MASK) >> CSR_MMSC_CFG2_BF16CVT_SHIFT) + + +#endif /* HPM_CSR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_dmamux_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_dmamux_regs.h new file mode 100644 index 00000000000..b656cf1c5a1 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_dmamux_regs.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_DMAMUX_H +#define HPM_DMAMUX_H + +typedef struct { + __W uint32_t MUXCFG[32]; /* 0x0 - 0x7C: HDMA MUX0 Configuration */ +} DMAMUX_Type; + + +/* Bitfield definition for register array: MUXCFG */ +/* + * ENABLE (WO) + * + * DMA Mux Channel Enable + * Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be + * used to disable or reconfigure a DMA channel. + * 0b - DMA Mux channel is disabled + * 1b - DMA Mux channel is enabled + */ +#define DMAMUX_MUXCFG_ENABLE_MASK (0x80000000UL) +#define DMAMUX_MUXCFG_ENABLE_SHIFT (31U) +#define DMAMUX_MUXCFG_ENABLE_SET(x) (((uint32_t)(x) << DMAMUX_MUXCFG_ENABLE_SHIFT) & DMAMUX_MUXCFG_ENABLE_MASK) +#define DMAMUX_MUXCFG_ENABLE_GET(x) (((uint32_t)(x) & DMAMUX_MUXCFG_ENABLE_MASK) >> DMAMUX_MUXCFG_ENABLE_SHIFT) + +/* + * SOURCE (WO) + * + * DMA Channel Source + * Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + */ +#define DMAMUX_MUXCFG_SOURCE_MASK (0x7FU) +#define DMAMUX_MUXCFG_SOURCE_SHIFT (0U) +#define DMAMUX_MUXCFG_SOURCE_SET(x) (((uint32_t)(x) << DMAMUX_MUXCFG_SOURCE_SHIFT) & DMAMUX_MUXCFG_SOURCE_MASK) +#define DMAMUX_MUXCFG_SOURCE_GET(x) (((uint32_t)(x) & DMAMUX_MUXCFG_SOURCE_MASK) >> DMAMUX_MUXCFG_SOURCE_SHIFT) + + + +/* MUXCFG register group index macro definition */ +#define DMAMUX_MUXCFG_HDMA_MUX0 (0UL) +#define DMAMUX_MUXCFG_HDMA_MUX1 (1UL) +#define DMAMUX_MUXCFG_HDMA_MUX2 (2UL) +#define DMAMUX_MUXCFG_HDMA_MUX3 (3UL) +#define DMAMUX_MUXCFG_HDMA_MUX4 (4UL) +#define DMAMUX_MUXCFG_HDMA_MUX5 (5UL) +#define DMAMUX_MUXCFG_HDMA_MUX6 (6UL) +#define DMAMUX_MUXCFG_HDMA_MUX7 (7UL) +#define DMAMUX_MUXCFG_HDMA_MUX8 (8UL) +#define DMAMUX_MUXCFG_HDMA_MUX9 (9UL) +#define DMAMUX_MUXCFG_HDMA_MUX10 (10UL) +#define DMAMUX_MUXCFG_HDMA_MUX11 (11UL) +#define DMAMUX_MUXCFG_HDMA_MUX12 (12UL) +#define DMAMUX_MUXCFG_HDMA_MUX13 (13UL) +#define DMAMUX_MUXCFG_HDMA_MUX14 (14UL) +#define DMAMUX_MUXCFG_HDMA_MUX15 (15UL) +#define DMAMUX_MUXCFG_HDMA_MUX16 (16UL) +#define DMAMUX_MUXCFG_HDMA_MUX17 (17UL) +#define DMAMUX_MUXCFG_HDMA_MUX18 (18UL) +#define DMAMUX_MUXCFG_HDMA_MUX19 (19UL) +#define DMAMUX_MUXCFG_HDMA_MUX20 (20UL) +#define DMAMUX_MUXCFG_HDMA_MUX21 (21UL) +#define DMAMUX_MUXCFG_HDMA_MUX22 (22UL) +#define DMAMUX_MUXCFG_HDMA_MUX23 (23UL) +#define DMAMUX_MUXCFG_HDMA_MUX24 (24UL) +#define DMAMUX_MUXCFG_HDMA_MUX25 (25UL) +#define DMAMUX_MUXCFG_HDMA_MUX26 (26UL) +#define DMAMUX_MUXCFG_HDMA_MUX27 (27UL) +#define DMAMUX_MUXCFG_HDMA_MUX28 (28UL) +#define DMAMUX_MUXCFG_HDMA_MUX29 (29UL) +#define DMAMUX_MUXCFG_HDMA_MUX30 (30UL) +#define DMAMUX_MUXCFG_HDMA_MUX31 (31UL) + + +#endif /* HPM_DMAMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_dmamux_src.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_dmamux_src.h new file mode 100644 index 00000000000..90a7738d26b --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_dmamux_src.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_DMAMUX_SRC_H +#define HPM_DMAMUX_SRC_H + +/* dma mux definitions */ +#define HPM_DMA_SRC_GPTMR0_0 (0x0UL) +#define HPM_DMA_SRC_GPTMR0_1 (0x1UL) +#define HPM_DMA_SRC_GPTMR0_2 (0x2UL) +#define HPM_DMA_SRC_GPTMR0_3 (0x3UL) +#define HPM_DMA_SRC_GPTMR1_0 (0x4UL) +#define HPM_DMA_SRC_GPTMR1_1 (0x5UL) +#define HPM_DMA_SRC_GPTMR1_2 (0x6UL) +#define HPM_DMA_SRC_GPTMR1_3 (0x7UL) +#define HPM_DMA_SRC_UART0_RX (0x14UL) +#define HPM_DMA_SRC_UART0_TX (0x15UL) +#define HPM_DMA_SRC_UART1_RX (0x16UL) +#define HPM_DMA_SRC_UART1_TX (0x17UL) +#define HPM_DMA_SRC_UART2_RX (0x18UL) +#define HPM_DMA_SRC_UART2_TX (0x19UL) +#define HPM_DMA_SRC_UART3_RX (0x1AUL) +#define HPM_DMA_SRC_UART3_TX (0x1BUL) +#define HPM_DMA_SRC_I2C0 (0x24UL) +#define HPM_DMA_SRC_I2C1 (0x25UL) +#define HPM_DMA_SRC_I2C2 (0x26UL) +#define HPM_DMA_SRC_I2C3 (0x27UL) +#define HPM_DMA_SRC_SPI0_RX (0x28UL) +#define HPM_DMA_SRC_SPI0_TX (0x29UL) +#define HPM_DMA_SRC_SPI1_RX (0x2AUL) +#define HPM_DMA_SRC_SPI1_TX (0x2BUL) +#define HPM_DMA_SRC_SPI2_RX (0x2CUL) +#define HPM_DMA_SRC_SPI2_TX (0x2DUL) +#define HPM_DMA_SRC_SPI3_RX (0x2EUL) +#define HPM_DMA_SRC_SPI3_TX (0x2FUL) +#define HPM_DMA_SRC_MOT_0 (0x34UL) +#define HPM_DMA_SRC_MOT_1 (0x35UL) +#define HPM_DMA_SRC_MOT_2 (0x36UL) +#define HPM_DMA_SRC_MOT_3 (0x37UL) +#define HPM_DMA_SRC_MOT_4 (0x38UL) +#define HPM_DMA_SRC_MOT_5 (0x39UL) +#define HPM_DMA_SRC_MOT_6 (0x3AUL) +#define HPM_DMA_SRC_MOT_7 (0x3BUL) +#define HPM_DMA_SRC_XPI0_RX (0x3CUL) +#define HPM_DMA_SRC_XPI0_TX (0x3DUL) +#define HPM_DMA_SRC_ACMP0 (0x40UL) +#define HPM_DMA_SRC_ACMP1 (0x41UL) + + + +#endif /* HPM_DMAMUX_SRC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_gpiom_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_gpiom_regs.h new file mode 100644 index 00000000000..85a507cc26d --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_gpiom_regs.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_GPIOM_H +#define HPM_GPIOM_H + +typedef struct { + struct { + __RW uint32_t PIN[32]; /* 0x0 - 0x7C: GPIO mananger */ + } ASSIGN[15]; +} GPIOM_Type; + + +/* Bitfield definition for register of struct array ASSIGN: PIN00 */ +/* + * LOCK (RW) + * + * lock fields in this register, lock can only be cleared by soc reset + * 0: fields can be changed + * 1: fields locked to current value, not changeable + */ +#define GPIOM_ASSIGN_PIN_LOCK_MASK (0x80000000UL) +#define GPIOM_ASSIGN_PIN_LOCK_SHIFT (31U) +#define GPIOM_ASSIGN_PIN_LOCK_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_LOCK_SHIFT) & GPIOM_ASSIGN_PIN_LOCK_MASK) +#define GPIOM_ASSIGN_PIN_LOCK_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_LOCK_MASK) >> GPIOM_ASSIGN_PIN_LOCK_SHIFT) + +/* + * HIDE (RW) + * + * pin value visibility to gpios, + * bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 + * bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + */ +#define GPIOM_ASSIGN_PIN_HIDE_MASK (0xF00U) +#define GPIOM_ASSIGN_PIN_HIDE_SHIFT (8U) +#define GPIOM_ASSIGN_PIN_HIDE_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_HIDE_SHIFT) & GPIOM_ASSIGN_PIN_HIDE_MASK) +#define GPIOM_ASSIGN_PIN_HIDE_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_HIDE_MASK) >> GPIOM_ASSIGN_PIN_HIDE_SHIFT) + +/* + * SELECT (RW) + * + * select which gpio controls chip pin, + * 0: soc gpio0; + * 2: cpu0 fastgpio + */ +#define GPIOM_ASSIGN_PIN_SELECT_MASK (0x3U) +#define GPIOM_ASSIGN_PIN_SELECT_SHIFT (0U) +#define GPIOM_ASSIGN_PIN_SELECT_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_SELECT_SHIFT) & GPIOM_ASSIGN_PIN_SELECT_MASK) +#define GPIOM_ASSIGN_PIN_SELECT_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_SELECT_MASK) >> GPIOM_ASSIGN_PIN_SELECT_SHIFT) + + + +/* PIN register group index macro definition */ +#define GPIOM_ASSIGN_PIN_PIN00 (0UL) +#define GPIOM_ASSIGN_PIN_PIN01 (1UL) +#define GPIOM_ASSIGN_PIN_PIN02 (2UL) +#define GPIOM_ASSIGN_PIN_PIN03 (3UL) +#define GPIOM_ASSIGN_PIN_PIN04 (4UL) +#define GPIOM_ASSIGN_PIN_PIN05 (5UL) +#define GPIOM_ASSIGN_PIN_PIN06 (6UL) +#define GPIOM_ASSIGN_PIN_PIN07 (7UL) +#define GPIOM_ASSIGN_PIN_PIN08 (8UL) +#define GPIOM_ASSIGN_PIN_PIN09 (9UL) +#define GPIOM_ASSIGN_PIN_PIN10 (10UL) +#define GPIOM_ASSIGN_PIN_PIN11 (11UL) +#define GPIOM_ASSIGN_PIN_PIN12 (12UL) +#define GPIOM_ASSIGN_PIN_PIN13 (13UL) +#define GPIOM_ASSIGN_PIN_PIN14 (14UL) +#define GPIOM_ASSIGN_PIN_PIN15 (15UL) +#define GPIOM_ASSIGN_PIN_PIN16 (16UL) +#define GPIOM_ASSIGN_PIN_PIN17 (17UL) +#define GPIOM_ASSIGN_PIN_PIN18 (18UL) +#define GPIOM_ASSIGN_PIN_PIN19 (19UL) +#define GPIOM_ASSIGN_PIN_PIN20 (20UL) +#define GPIOM_ASSIGN_PIN_PIN21 (21UL) +#define GPIOM_ASSIGN_PIN_PIN22 (22UL) +#define GPIOM_ASSIGN_PIN_PIN23 (23UL) +#define GPIOM_ASSIGN_PIN_PIN24 (24UL) +#define GPIOM_ASSIGN_PIN_PIN25 (25UL) +#define GPIOM_ASSIGN_PIN_PIN26 (26UL) +#define GPIOM_ASSIGN_PIN_PIN27 (27UL) +#define GPIOM_ASSIGN_PIN_PIN28 (28UL) +#define GPIOM_ASSIGN_PIN_PIN29 (29UL) +#define GPIOM_ASSIGN_PIN_PIN30 (30UL) +#define GPIOM_ASSIGN_PIN_PIN31 (31UL) + +/* ASSIGN register group index macro definition */ +#define GPIOM_ASSIGN_GPIOA (0UL) +#define GPIOM_ASSIGN_GPIOB (1UL) +#define GPIOM_ASSIGN_GPIOX (13UL) +#define GPIOM_ASSIGN_GPIOY (14UL) + + +#endif /* HPM_GPIOM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_gpiom_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_gpiom_soc_drv.h new file mode 100644 index 00000000000..01e0f0a5cd5 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_gpiom_soc_drv.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_GPIOM_SOC_DRV_H +#define HPM_GPIOM_SOC_DRV_H + +/** + * @addtogroup gpiom_interface GPIOM driver APIs + * @{ + */ + +/* @brief gpiom control module */ +typedef enum gpiom_gpio { + gpiom_soc_gpio0 = 0, + gpiom_core0_fast = 2, +} gpiom_gpio_t; + +/** + * @} + */ + +#endif /* HPM_GPIOM_SOC_DRV_H */ + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_interrupt.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_interrupt.h new file mode 100644 index 00000000000..94375e7f0b3 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_interrupt.h @@ -0,0 +1,865 @@ +/* + * Copyright (c) 2023-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_INTERRUPT_H +#define HPM_INTERRUPT_H +#include "hpm_common.h" +#include "hpm_csr_drv.h" +#include "hpm_plic_drv.h" + +/** + * @brief INTERRUPT driver APIs + * @defgroup irq_interface INTERRUPT driver APIs + * @{ + */ + +#define M_MODE 0 /*!< Machine mode */ +#define S_MODE 1 /*!< Supervisor mode */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Machine mode API: these APIs are supposed to be called at machine mode */ + +/** + * @brief Enable global IRQ with mask + * + * @param[in] mask interrupt mask to be enabaled + */ +ATTR_ALWAYS_INLINE static inline void enable_global_irq(uint32_t mask) +{ + set_csr(CSR_MSTATUS, mask); +} + +/** + * @brief Disable global IRQ with mask and return mstatus + * + * @param[in] mask interrupt mask to be disabled + * @retval current mstatus value before irq mask is disabled + */ +ATTR_ALWAYS_INLINE static inline uint32_t disable_global_irq(uint32_t mask) +{ + return read_clear_csr(CSR_MSTATUS, mask); +} + +/** + * @brief Restore global IRQ with mask + * + * @param[in] mask interrupt mask to be restored + */ +ATTR_ALWAYS_INLINE static inline void restore_global_irq(uint32_t mask) +{ + set_csr(CSR_MSTATUS, mask); +} + +/** + * @brief Enable IRQ from interrupt controller + * + */ +ATTR_ALWAYS_INLINE static inline void enable_irq_from_intc(void) +{ + set_csr(CSR_MIE, CSR_MIE_MEIE_MASK); +} + +/** + * @brief Disable IRQ from interrupt controller + * + */ +ATTR_ALWAYS_INLINE static inline void disable_irq_from_intc(void) +{ + clear_csr(CSR_MIE, CSR_MIE_MEIE_MASK); +} + +/** + * @brief Enable machine timer IRQ + */ +ATTR_ALWAYS_INLINE static inline void enable_mchtmr_irq(void) +{ + set_csr(CSR_MIE, CSR_MIE_MTIE_MASK); +} + +/** + * @brief Disable machine timer IRQ + * + */ +ATTR_ALWAYS_INLINE static inline void disable_mchtmr_irq(void) +{ + clear_csr(CSR_MIE, CSR_MIE_MTIE_MASK); +} + +/* + * CPU Machine SWI control + * + * Machine SWI (MSIP) is connected to PLICSW irq 1. + */ +#define PLICSWI 1 + +/** + * @brief Initialize software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_init_swi(void) +{ + __plic_enable_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI); +} + + +/** + * @brief Enable software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_enable_swi(void) +{ + set_csr(CSR_MIE, CSR_MIE_MSIE_MASK); +} + + +/** + * @brief Disable software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_disable_swi(void) +{ + clear_csr(CSR_MIE, CSR_MIE_MSIE_MASK); +} + + +/** + * @brief Trigger software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_trigger_swi(void) +{ + __plic_set_irq_pending(HPM_PLICSW_BASE, PLICSWI); +} + +/** + * @brief Claim software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_claim_swi(void) +{ + __plic_claim_irq(HPM_PLICSW_BASE, 0); +} + +/** + * @brief Complete software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_complete_swi(void) +{ + __plic_complete_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI); +} + +/* + * @brief Enable IRQ for machine mode + * + * @param[in] irq Interrupt number + */ +#define intc_m_enable_irq(irq) \ + intc_enable_irq(HPM_PLIC_TARGET_M_MODE, irq) + +/* + * @brief Disable IRQ for machine mode + * + * @param[in] irq Interrupt number + */ +#define intc_m_disable_irq(irq) \ + intc_disable_irq(HPM_PLIC_TARGET_M_MODE, irq) + +#define intc_m_set_threshold(threshold) \ + intc_set_threshold(HPM_PLIC_TARGET_M_MODE, threshold) + +/* + * @brief Complete IRQ for machine mode + * + * @param[in] irq Interrupt number + */ +#define intc_m_complete_irq(irq) \ + intc_complete_irq(HPM_PLIC_TARGET_M_MODE, irq) + +/* + * @brief Claim IRQ for machine mode + * + */ +#define intc_m_claim_irq() intc_claim_irq(HPM_PLIC_TARGET_M_MODE) + +/* + * @brief Enable IRQ for machine mode with priority + * + * @param[in] irq Interrupt number + * @param[in] priority Priority of interrupt + */ +#define intc_m_enable_irq_with_priority(irq, priority) \ + do { \ + intc_set_irq_priority(irq, priority); \ + intc_m_enable_irq(irq); \ + } while (0) + +/* + * @brief Enable specific interrupt + * + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number + */ +ATTR_ALWAYS_INLINE static inline void intc_enable_irq(uint32_t target, uint32_t irq) +{ + __plic_enable_irq(HPM_PLIC_BASE, target, irq); +} + +/** + * @brief Set interrupt priority + * + * @param[in] irq Interrupt number + * @param[in] priority Priority of interrupt + */ +ATTR_ALWAYS_INLINE static inline void intc_set_irq_priority(uint32_t irq, uint32_t priority) +{ + __plic_set_irq_priority(HPM_PLIC_BASE, irq, priority); +} + +/** + * @brief Disable specific interrupt + * + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number + */ +ATTR_ALWAYS_INLINE static inline void intc_disable_irq(uint32_t target, uint32_t irq) +{ + __plic_disable_irq(HPM_PLIC_BASE, target, irq); +} + +/** + * @brief Set interrupt threshold + * + * @param[in] target Target to handle specific interrupt + * @param[in] threshold Threshold of IRQ can be serviced + */ +ATTR_ALWAYS_INLINE static inline void intc_set_threshold(uint32_t target, uint32_t threshold) +{ + __plic_set_threshold(HPM_PLIC_BASE, target, threshold); +} + +/** + * @brief Claim IRQ + * + * @param[in] target Target to handle specific interrupt + * + */ +ATTR_ALWAYS_INLINE static inline uint32_t intc_claim_irq(uint32_t target) +{ + return __plic_claim_irq(HPM_PLIC_BASE, target); +} + +/** + * @brief Complete IRQ + * + * @param[in] target Target to handle specific interrupt + * @param[in] irq Specific IRQ to be completed + * + */ +ATTR_ALWAYS_INLINE static inline void intc_complete_irq(uint32_t target, uint32_t irq) +{ + __plic_complete_irq(HPM_PLIC_BASE, target, irq); +} + +/* + * Vectored based irq install and uninstall + */ +/* Machine mode */ +extern int __vector_table[]; + +extern void default_irq_entry(void); + +/** + * @brief Install ISR for certain IRQ for ram based vector table + * + * @param[in] irq Target interrupt number + * @param[in] isr Interrupt service routine + * + */ +ATTR_ALWAYS_INLINE static inline void install_isr(uint32_t irq, uint32_t isr) +{ + __vector_table[irq] = isr; +} + +/** + * @brief Uninstall ISR for certain IRQ for ram based vector table + * + * @param[in] irq Target interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) +{ + __vector_table[irq] = (int) default_irq_entry; +} + +/* + * Inline nested irq entry/exit macros + */ +/* + * @brief Save CSR + * @param[in] r Target CSR to be saved + */ +#define SAVE_CSR(r) register long __##r = read_csr(r); + +/* + * @brief Restore macro + * + * @param[in] r Target CSR to be restored + */ +#define RESTORE_CSR(r) write_csr(r, __##r); + +#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH +#define SAVE_MXSTATUS() SAVE_CSR(CSR_MXSTATUS) +#define RESTORE_MXSTATUS() RESTORE_CSR(CSR_MXSTATUS) +#else +#define SAVE_MXSTATUS() +#define RESTORE_MXSTATUS() +#endif + +#ifdef __riscv_flen +#define SAVE_FCSR() register int __fcsr = read_fcsr(); +#define RESTORE_FCSR() write_fcsr(__fcsr); +#else +#define SAVE_FCSR() +#define RESTORE_FCSR() +#endif + +#ifdef __riscv_dsp +#define SAVE_UCODE() SAVE_CSR(CSR_UCODE) +#define RESTORE_UCODE() RESTORE_CSR(CSR_UCODE) +#else +#define SAVE_UCODE() +#define RESTORE_UCODE() +#endif + +#ifdef __riscv_flen +#if __riscv_flen == 32 +/* RV32I caller registers + MCAUSE + MEPC + MSTATUS + 20 FPU caller registers */ +#define CONTEXT_REG_NUM (4 * (16 + 4 + 20)) +#else /* __riscv_flen = 64 */ +/* RV32I caller registers + MCAUSE + MEPC + MSTATUS + 20 DFPU caller */ +#define CONTEXT_REG_NUM (4*(16 + 4 + 20*2)) +#endif + +#else +/* RV32I caller registers + MCAUSE + MEPC + MSTATUS */ +#define CONTEXT_REG_NUM (4 * (16 + 4)) +#endif + +#ifdef __riscv_flen +/* + * Save FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack + */ +#if __riscv_flen == 32 +#ifdef __ICCRISCV__ +#define SAVE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fswsp ft0, 20*4\n\ + c.fswsp ft1, 21*4 \n\ + c.fswsp ft2, 22*4 \n\ + c.fswsp ft3, 23*4 \n\ + c.fswsp ft4, 24*4 \n\ + c.fswsp ft5, 25*4 \n\ + c.fswsp ft6, 26*4 \n\ + c.fswsp ft7, 27*4 \n\ + c.fswsp fa0, 28*4 \n\ + c.fswsp fa1, 29*4 \n\ + c.fswsp fa2, 30*4 \n\ + c.fswsp fa3, 31*4 \n\ + c.fswsp fa4, 32*4 \n\ + c.fswsp fa5, 33*4 \n\ + c.fswsp fa6, 34*4 \n\ + c.fswsp fa7, 35*4 \n\ + c.fswsp ft8, 36*4 \n\ + c.fswsp ft9, 37*4 \n\ + c.fswsp ft10, 38*4 \n\ + c.fswsp ft11, 39*4 \n");\ +} + +/* + * Restore FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack + */ +#define RESTORE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.flwsp ft0, 20*4\n\ + c.flwsp ft1, 21*4 \n\ + c.flwsp ft2, 22*4 \n\ + c.flwsp ft3, 23*4 \n\ + c.flwsp ft4, 24*4 \n\ + c.flwsp ft5, 25*4 \n\ + c.flwsp ft6, 26*4 \n\ + c.flwsp ft7, 27*4 \n\ + c.flwsp fa0, 28*4 \n\ + c.flwsp fa1, 29*4 \n\ + c.flwsp fa2, 30*4 \n\ + c.flwsp fa3, 31*4 \n\ + c.flwsp fa4, 32*4 \n\ + c.flwsp fa5, 33*4 \n\ + c.flwsp fa6, 34*4 \n\ + c.flwsp fa7, 35*4 \n\ + c.flwsp ft8, 36*4 \n\ + c.flwsp ft9, 37*4 \n\ + c.flwsp ft10, 38*4 \n\ + c.flwsp ft11, 39*4 \n");\ +} +#else /* __ICCRISCV__ not defined */ +#define SAVE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fswsp ft0, 20*4(sp)\n\ + c.fswsp ft1, 21*4(sp) \n\ + c.fswsp ft2, 22*4(sp) \n\ + c.fswsp ft3, 23*4(sp) \n\ + c.fswsp ft4, 24*4(sp) \n\ + c.fswsp ft5, 25*4(sp) \n\ + c.fswsp ft6, 26*4(sp) \n\ + c.fswsp ft7, 27*4(sp) \n\ + c.fswsp fa0, 28*4(sp) \n\ + c.fswsp fa1, 29*4(sp) \n\ + c.fswsp fa2, 30*4(sp) \n\ + c.fswsp fa3, 31*4(sp) \n\ + c.fswsp fa4, 32*4(sp) \n\ + c.fswsp fa5, 33*4(sp) \n\ + c.fswsp fa6, 34*4(sp) \n\ + c.fswsp fa7, 35*4(sp) \n\ + c.fswsp ft8, 36*4(sp) \n\ + c.fswsp ft9, 37*4(sp) \n\ + c.fswsp ft10, 38*4(sp) \n\ + c.fswsp ft11, 39*4(sp) \n");\ +} + +/* + * Restore FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack + */ +#define RESTORE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.flwsp ft0, 20*4(sp)\n\ + c.flwsp ft1, 21*4(sp) \n\ + c.flwsp ft2, 22*4(sp) \n\ + c.flwsp ft3, 23*4(sp) \n\ + c.flwsp ft4, 24*4(sp) \n\ + c.flwsp ft5, 25*4(sp) \n\ + c.flwsp ft6, 26*4(sp) \n\ + c.flwsp ft7, 27*4(sp) \n\ + c.flwsp fa0, 28*4(sp) \n\ + c.flwsp fa1, 29*4(sp) \n\ + c.flwsp fa2, 30*4(sp) \n\ + c.flwsp fa3, 31*4(sp) \n\ + c.flwsp fa4, 32*4(sp) \n\ + c.flwsp fa5, 33*4(sp) \n\ + c.flwsp fa6, 34*4(sp) \n\ + c.flwsp fa7, 35*4(sp) \n\ + c.flwsp ft8, 36*4(sp) \n\ + c.flwsp ft9, 37*4(sp) \n\ + c.flwsp ft10, 38*4(sp) \n\ + c.flwsp ft11, 39*4(sp) \n");\ +} +#endif +#else /*__riscv_flen == 64*/ +#ifdef __ICCRISCV__ +#define SAVE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fsdsp ft0, 20*4\n\ + c.fsdsp ft1, 22*4 \n\ + c.fsdsp ft2, 24*4 \n\ + c.fsdsp ft3, 26*4 \n\ + c.fsdsp ft4, 28*4 \n\ + c.fsdsp ft5, 30*4 \n\ + c.fsdsp ft6, 32*4 \n\ + c.fsdsp ft7, 34*4 \n\ + c.fsdsp fa0, 36*4 \n\ + c.fsdsp fa1, 38*4 \n\ + c.fsdsp fa2, 40*4 \n\ + c.fsdsp fa3, 42*4 \n\ + c.fsdsp fa4, 44*4 \n\ + c.fsdsp fa5, 46*4 \n\ + c.fsdsp fa6, 48*4 \n\ + c.fsdsp fa7, 50*4 \n\ + c.fsdsp ft8, 52*4 \n\ + c.fsdsp ft9, 54*4 \n\ + c.fsdsp ft10, 56*4 \n\ + c.fsdsp ft11, 58*4 \n");\ +} + +/* + * Restore FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack + */ +#define RESTORE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fldsp ft0, 20*4\n\ + c.fldsp ft1, 22*4 \n\ + c.fldsp ft2, 24*4 \n\ + c.fldsp ft3, 26*4 \n\ + c.fldsp ft4, 28*4 \n\ + c.fldsp ft5, 30*4 \n\ + c.fldsp ft6, 32*4 \n\ + c.fldsp ft7, 34*4 \n\ + c.fldsp fa0, 36*4 \n\ + c.fldsp fa1, 38*4 \n\ + c.fldsp fa2, 40*4 \n\ + c.fldsp fa3, 42*4 \n\ + c.fldsp fa4, 44*4 \n\ + c.fldsp fa5, 46*4 \n\ + c.fldsp fa6, 48*4 \n\ + c.fldsp fa7, 50*4 \n\ + c.fldsp ft8, 52*4 \n\ + c.fldsp ft9, 54*4 \n\ + c.fldsp ft10, 56*4 \n\ + c.fldsp ft11, 58*4 \n");\ +} +#else +#define SAVE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fsdsp ft0, 20*4(sp)\n\ + c.fsdsp ft1, 22*4(sp) \n\ + c.fsdsp ft2, 24*4(sp) \n\ + c.fsdsp ft3, 26*4(sp) \n\ + c.fsdsp ft4, 28*4(sp) \n\ + c.fsdsp ft5, 30*4(sp) \n\ + c.fsdsp ft6, 32*4(sp) \n\ + c.fsdsp ft7, 34*4(sp) \n\ + c.fsdsp fa0, 36*4(sp) \n\ + c.fsdsp fa1, 38*4(sp) \n\ + c.fsdsp fa2, 40*4(sp) \n\ + c.fsdsp fa3, 42*4(sp) \n\ + c.fsdsp fa4, 44*4(sp) \n\ + c.fsdsp fa5, 46*4(sp) \n\ + c.fsdsp fa6, 48*4(sp) \n\ + c.fsdsp fa7, 50*4(sp) \n\ + c.fsdsp ft8, 52*4(sp) \n\ + c.fsdsp ft9, 54*4(sp) \n\ + c.fsdsp ft10, 56*4(sp) \n\ + c.fsdsp ft11, 58*4(sp) \n");\ +} + +/* + * Restore FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack + */ +#define RESTORE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fldsp ft0, 20*4(sp)\n\ + c.fldsp ft1, 22*4(sp) \n\ + c.fldsp ft2, 24*4(sp) \n\ + c.fldsp ft3, 26*4(sp) \n\ + c.fldsp ft4, 28*4(sp) \n\ + c.fldsp ft5, 30*4(sp) \n\ + c.fldsp ft6, 32*4(sp) \n\ + c.fldsp ft7, 34*4(sp) \n\ + c.fldsp fa0, 36*4(sp) \n\ + c.fldsp fa1, 38*4(sp) \n\ + c.fldsp fa2, 40*4(sp) \n\ + c.fldsp fa3, 42*4(sp) \n\ + c.fldsp fa4, 44*4(sp) \n\ + c.fldsp fa5, 46*4(sp) \n\ + c.fldsp fa6, 48*4(sp) \n\ + c.fldsp fa7, 50*4(sp) \n\ + c.fldsp ft8, 52*4(sp) \n\ + c.fldsp ft9, 54*4(sp) \n\ + c.fldsp ft10, 56*4(sp) \n\ + c.fldsp ft11, 58*4(sp) \n");\ +} +#endif +#endif +#else +#define SAVE_FPU_CONTEXT() +#define RESTORE_FPU_CONTEXT() +#endif + +#ifdef __ICCRISCV__ +/** + * @brief Save the caller registers based on the RISC-V ABI specification + */ +#define SAVE_CALLER_CONTEXT() { \ + __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\ + __asm volatile("\n\ + c.swsp ra, 0*4 \n\ + c.swsp t0, 1*4 \n\ + c.swsp t1, 2*4 \n\ + c.swsp t2, 3*4 \n\ + c.swsp s0, 4*4 \n\ + c.swsp s1, 5*4 \n\ + c.swsp a0, 6*4 \n\ + c.swsp a1, 7*4 \n\ + c.swsp a2, 8*4 \n\ + c.swsp a3, 9*4 \n\ + c.swsp a4, 10*4 \n\ + c.swsp a5, 11*4 \n\ + c.swsp a6, 12*4 \n\ + c.swsp a7, 13*4 \n\ + c.swsp s2, 14*4 \n\ + c.swsp s3, 15*4 \n\ + c.swsp t3, 16*4 \n\ + c.swsp t4, 17*4 \n\ + c.swsp t5, 18*4 \n\ + c.swsp t6, 19*4"); \ + SAVE_FPU_CONTEXT(); \ +} + +/** + * @brief Restore the caller registers based on the RISC-V ABI specification + */ +#define RESTORE_CALLER_CONTEXT() { \ + __asm volatile("\n\ + c.lwsp ra, 0*4 \n\ + c.lwsp t0, 1*4 \n\ + c.lwsp t1, 2*4 \n\ + c.lwsp t2, 3*4 \n\ + c.lwsp s0, 4*4 \n\ + c.lwsp s1, 5*4 \n\ + c.lwsp a0, 6*4 \n\ + c.lwsp a1, 7*4 \n\ + c.lwsp a2, 8*4 \n\ + c.lwsp a3, 9*4 \n\ + c.lwsp a4, 10*4 \n\ + c.lwsp a5, 11*4 \n\ + c.lwsp a6, 12*4 \n\ + c.lwsp a7, 13*4 \n\ + c.lwsp s2, 14*4 \n\ + c.lwsp s3, 15*4 \n\ + c.lwsp t3, 16*4 \n\ + c.lwsp t4, 17*4 \n\ + c.lwsp t5, 18*4 \n\ + c.lwsp t6, 19*4 \n");\ + RESTORE_FPU_CONTEXT(); \ + __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\ +} +#else +/** + * @brief Save the caller registers based on the RISC-V ABI specification + */ +#define SAVE_CALLER_CONTEXT() { \ + __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\ + __asm volatile("\n\ + c.swsp ra, 0*4(sp) \n\ + c.swsp t0, 1*4(sp) \n\ + c.swsp t1, 2*4(sp) \n\ + c.swsp t2, 3*4(sp) \n\ + c.swsp s0, 4*4(sp) \n\ + c.swsp s1, 5*4(sp) \n\ + c.swsp a0, 6*4(sp) \n\ + c.swsp a1, 7*4(sp) \n\ + c.swsp a2, 8*4(sp) \n\ + c.swsp a3, 9*4(sp) \n\ + c.swsp a4, 10*4(sp) \n\ + c.swsp a5, 11*4(sp) \n\ + c.swsp a6, 12*4(sp) \n\ + c.swsp a7, 13*4(sp) \n\ + c.swsp s2, 14*4(sp) \n\ + c.swsp s3, 15*4(sp) \n\ + c.swsp t3, 16*4(sp) \n\ + c.swsp t4, 17*4(sp) \n\ + c.swsp t5, 18*4(sp) \n\ + c.swsp t6, 19*4(sp)"); \ + SAVE_FPU_CONTEXT(); \ +} + +/** + * @brief Restore the caller registers based on the RISC-V ABI specification + */ +#define RESTORE_CALLER_CONTEXT() { \ + __asm volatile("\n\ + c.lwsp ra, 0*4(sp) \n\ + c.lwsp t0, 1*4(sp) \n\ + c.lwsp t1, 2*4(sp) \n\ + c.lwsp t2, 3*4(sp) \n\ + c.lwsp s0, 4*4(sp) \n\ + c.lwsp s1, 5*4(sp) \n\ + c.lwsp a0, 6*4(sp) \n\ + c.lwsp a1, 7*4(sp) \n\ + c.lwsp a2, 8*4(sp) \n\ + c.lwsp a3, 9*4(sp) \n\ + c.lwsp a4, 10*4(sp) \n\ + c.lwsp a5, 11*4(sp) \n\ + c.lwsp a6, 12*4(sp) \n\ + c.lwsp a7, 13*4(sp) \n\ + c.lwsp s2, 14*4(sp) \n\ + c.lwsp s3, 15*4(sp) \n\ + c.lwsp t3, 16*4(sp) \n\ + c.lwsp t4, 17*4(sp) \n\ + c.lwsp t5, 18*4(sp) \n\ + c.lwsp t6, 19*4(sp) \n");\ + RESTORE_FPU_CONTEXT(); \ + __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\ +} +#endif + +#ifdef __riscv_flen +#define SAVE_FPU_STATE() { \ + __asm volatile("frcsr s1\n"); \ +} + +#define RESTORE_FPU_STATE() { \ + __asm volatile("fscsr s1\n"); \ +} +#else +#define SAVE_FPU_STATE() +#define RESTORE_FPU_STATE() +#endif + +#ifdef __riscv_dsp +/* + * Save DSP context + * NOTE: DSP context registers are stored at word offset 41 in the stack + */ +#define SAVE_DSP_CONTEXT() { \ + __asm volatile("csrrs s0, %0, x0\n" ::"i"(CSR_UCODE):); \ +} +/* + * @brief Restore DSP context + * @note DSP context registers are stored at word offset 41 in the stack + */ +#define RESTORE_DSP_CONTEXT() {\ + __asm volatile("csrw %0, s0\n" ::"i"(CSR_UCODE):); \ +} + +#else +#define SAVE_DSP_CONTEXT() +#define RESTORE_DSP_CONTEXT() +#endif + +/* + * @brief Enter Nested IRQ Handling + * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: + * MCAUSE - word offset 16 (not used in the vectored mode) + * EPC - word offset 17 + * MSTATUS = word offset 18 + * MXSTATUS = word offset 19 + */ +#define ENTER_NESTED_IRQ_HANDLING_M() { \ + __asm volatile("\n\ + csrr s2, mepc \n\ + csrr s3, mstatus \n");\ + SAVE_FPU_STATE(); \ + SAVE_DSP_CONTEXT(); \ + __asm volatile("csrsi mstatus, 8"); \ +} + +/* + * @brief Complete IRQ Handling + */ +#define COMPLETE_IRQ_HANDLING_M(irq_num) { \ + __asm volatile("csrci mstatus, 8"); \ + __asm volatile("lui a4, 0xe4200"); \ + __asm volatile("li a3, %0" : : "i" (irq_num) :); \ + __asm volatile("sw a3, 4(a4)"); \ +} + +/* + * @brief Exit Nested IRQ Handling + * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: + * MCAUSE - word offset 16 (not used in the vectored mode) + * EPC - word offset 17 + * MSTATUS = word offset 18 + * MXSTATUS = word offset 19 + */ +#define EXIT_NESTED_IRQ_HANDLING_M() { \ + __asm volatile("\n\ + csrw mstatus, s3 \n\ + csrw mepc, s2 \n");\ + RESTORE_FPU_STATE(); \ + RESTORE_DSP_CONTEXT(); \ +} + +/* @brief Nested IRQ entry macro : Save CSRs and enable global irq. */ +#define NESTED_IRQ_ENTER() \ + SAVE_CSR(CSR_MEPC) \ + SAVE_CSR(CSR_MSTATUS) \ + SAVE_MXSTATUS() \ + SAVE_FCSR() \ + SAVE_UCODE() \ + set_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); + +/* @brief Nested IRQ exit macro : Restore CSRs */ +#define NESTED_IRQ_EXIT() \ + RESTORE_CSR(CSR_MSTATUS) \ + RESTORE_CSR(CSR_MEPC) \ + RESTORE_MXSTATUS() \ + RESTORE_FCSR() \ + RESTORE_UCODE() + +#ifdef __cplusplus +#define HPM_EXTERN_C extern "C" +#else +#define HPM_EXTERN_C +#endif + +#define ISR_NAME_M(irq_num) default_isr_##irq_num +/** + * @brief Declare an external interrupt handler for machine mode + * + * @param[in] irq_num - IRQ number index + * @param[in] isr - Application IRQ handler function pointer + */ +#ifndef USE_NONVECTOR_MODE +#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ +void isr(void) __attribute__((section(".isr_vector")));\ +HPM_EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ +void ISR_NAME_M(irq_num)(void) \ +{ \ + SAVE_CALLER_CONTEXT(); \ + ENTER_NESTED_IRQ_HANDLING_M();\ + __asm volatile("la t1, %0\n\t" : : "i" (isr) : );\ + __asm volatile("jalr t1\n");\ + COMPLETE_IRQ_HANDLING_M(irq_num);\ + EXIT_NESTED_IRQ_HANDLING_M();\ + RESTORE_CALLER_CONTEXT();\ + __asm volatile("fence io, io");\ + __asm volatile("mret\n");\ +} +#else +#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ +void isr(void) __attribute__((section(".isr_vector")));\ +HPM_EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ +void ISR_NAME_M(irq_num)(void) \ +{ \ + isr(); \ +} +#endif + + +/** + * @brief Declare machine timer interrupt handler + * + * @param[in] isr - MCHTMR IRQ handler function pointer + */ +#define SDK_DECLARE_MCHTMR_ISR(isr) \ +void isr(void) __attribute__((section(".isr_vector")));\ +HPM_EXTERN_C void mchtmr_isr(void) __attribute__((section(".isr_vector"))); \ +void mchtmr_isr(void) \ +{ \ + isr();\ +} + +/** + * @brief Declare machine software interrupt handler + * + * @param[in] isr - SWI IRQ handler function pointer + */ +#define SDK_DECLARE_SWI_ISR(isr)\ +void isr(void) __attribute__((section(".isr_vector")));\ +HPM_EXTERN_C void swi_isr(void) __attribute__((section(".isr_vector"))); \ +void swi_isr(void) \ +{ \ + isr();\ +} + + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ +#endif /* HPM_INTERRUPT_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_ioc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_ioc_regs.h new file mode 100644 index 00000000000..5913db1ed7a --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_ioc_regs.h @@ -0,0 +1,259 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_IOC_H +#define HPM_IOC_H + +typedef struct { + struct { + __RW uint32_t FUNC_CTL; /* 0x0: ALT SELECT */ + __RW uint32_t PAD_CTL; /* 0x4: PAD SETTINGS */ + } PAD[456]; +} IOC_Type; + + +/* Bitfield definition for register of struct array PAD: FUNC_CTL */ +/* + * LOOP_BACK (RW) + * + * force input on + * 0: disable + * 1: enable + */ +#define IOC_PAD_FUNC_CTL_LOOP_BACK_MASK (0x10000UL) +#define IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT (16U) +#define IOC_PAD_FUNC_CTL_LOOP_BACK_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT) & IOC_PAD_FUNC_CTL_LOOP_BACK_MASK) +#define IOC_PAD_FUNC_CTL_LOOP_BACK_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_LOOP_BACK_MASK) >> IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT) + +/* + * ANALOG (RW) + * + * select analog pin in pad + * 0: disable + * 1: enable + */ +#define IOC_PAD_FUNC_CTL_ANALOG_MASK (0x100U) +#define IOC_PAD_FUNC_CTL_ANALOG_SHIFT (8U) +#define IOC_PAD_FUNC_CTL_ANALOG_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_ANALOG_SHIFT) & IOC_PAD_FUNC_CTL_ANALOG_MASK) +#define IOC_PAD_FUNC_CTL_ANALOG_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_ANALOG_MASK) >> IOC_PAD_FUNC_CTL_ANALOG_SHIFT) + +/* + * ALT_SELECT (RW) + * + * alt select + * 0: ALT0 + * 1: ALT1 + * ... + * 31:ALT31 + */ +#define IOC_PAD_FUNC_CTL_ALT_SELECT_MASK (0x1FU) +#define IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT (0U) +#define IOC_PAD_FUNC_CTL_ALT_SELECT_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT) & IOC_PAD_FUNC_CTL_ALT_SELECT_MASK) +#define IOC_PAD_FUNC_CTL_ALT_SELECT_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_ALT_SELECT_MASK) >> IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT) + +/* Bitfield definition for register of struct array PAD: PAD_CTL */ +/* + * HYS (RW) + * + * schmitt trigger enable + * 0: disable + * 1: enable + */ +#define IOC_PAD_PAD_CTL_HYS_MASK (0x1000000UL) +#define IOC_PAD_PAD_CTL_HYS_SHIFT (24U) +#define IOC_PAD_PAD_CTL_HYS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_HYS_SHIFT) & IOC_PAD_PAD_CTL_HYS_MASK) +#define IOC_PAD_PAD_CTL_HYS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_HYS_MASK) >> IOC_PAD_PAD_CTL_HYS_SHIFT) + +/* + * PRS (RW) + * + * select pull up/down internal resistance strength: + * For pull down, only have 100 Kohm resistance + * For pull up: + * 00: 100 KOhm + * 01: 47 KOhm + * 10: 22 KOhm + * 11: 22 KOhm + */ +#define IOC_PAD_PAD_CTL_PRS_MASK (0x300000UL) +#define IOC_PAD_PAD_CTL_PRS_SHIFT (20U) +#define IOC_PAD_PAD_CTL_PRS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PRS_SHIFT) & IOC_PAD_PAD_CTL_PRS_MASK) +#define IOC_PAD_PAD_CTL_PRS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PRS_MASK) >> IOC_PAD_PAD_CTL_PRS_SHIFT) + +/* + * PS (RW) + * + * pull select + * 0: pull down + * 1: pull up + */ +#define IOC_PAD_PAD_CTL_PS_MASK (0x40000UL) +#define IOC_PAD_PAD_CTL_PS_SHIFT (18U) +#define IOC_PAD_PAD_CTL_PS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PS_SHIFT) & IOC_PAD_PAD_CTL_PS_MASK) +#define IOC_PAD_PAD_CTL_PS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PS_MASK) >> IOC_PAD_PAD_CTL_PS_SHIFT) + +/* + * PE (RW) + * + * pull enable + * 0: pull disable + * 1: pull enable + */ +#define IOC_PAD_PAD_CTL_PE_MASK (0x20000UL) +#define IOC_PAD_PAD_CTL_PE_SHIFT (17U) +#define IOC_PAD_PAD_CTL_PE_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PE_SHIFT) & IOC_PAD_PAD_CTL_PE_MASK) +#define IOC_PAD_PAD_CTL_PE_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PE_MASK) >> IOC_PAD_PAD_CTL_PE_SHIFT) + +/* + * KE (RW) + * + * keeper capability enable + * 0: keeper disable + * 1: keeper enable + */ +#define IOC_PAD_PAD_CTL_KE_MASK (0x10000UL) +#define IOC_PAD_PAD_CTL_KE_SHIFT (16U) +#define IOC_PAD_PAD_CTL_KE_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_KE_SHIFT) & IOC_PAD_PAD_CTL_KE_MASK) +#define IOC_PAD_PAD_CTL_KE_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_KE_MASK) >> IOC_PAD_PAD_CTL_KE_SHIFT) + +/* + * OD (RW) + * + * open drain + * 0: open drain disable + * 1: open drain enable + */ +#define IOC_PAD_PAD_CTL_OD_MASK (0x100U) +#define IOC_PAD_PAD_CTL_OD_SHIFT (8U) +#define IOC_PAD_PAD_CTL_OD_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_OD_SHIFT) & IOC_PAD_PAD_CTL_OD_MASK) +#define IOC_PAD_PAD_CTL_OD_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_OD_MASK) >> IOC_PAD_PAD_CTL_OD_SHIFT) + +/* + * SR (RW) + * + * slew rate + * 0: Slow slew rate + * 1: Fast slew rate + */ +#define IOC_PAD_PAD_CTL_SR_MASK (0x40U) +#define IOC_PAD_PAD_CTL_SR_SHIFT (6U) +#define IOC_PAD_PAD_CTL_SR_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_SR_SHIFT) & IOC_PAD_PAD_CTL_SR_MASK) +#define IOC_PAD_PAD_CTL_SR_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_SR_MASK) >> IOC_PAD_PAD_CTL_SR_SHIFT) + +/* + * SPD (RW) + * + * additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise + * 00: Slow frequency slew rate(50Mhz) + * 01: Medium frequency slew rate(100 Mhz) + * 10: Fast frequency slew rate(150 Mhz) + * 11: Max frequency slew rate(200Mhz) + */ +#define IOC_PAD_PAD_CTL_SPD_MASK (0x30U) +#define IOC_PAD_PAD_CTL_SPD_SHIFT (4U) +#define IOC_PAD_PAD_CTL_SPD_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_SPD_SHIFT) & IOC_PAD_PAD_CTL_SPD_MASK) +#define IOC_PAD_PAD_CTL_SPD_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_SPD_MASK) >> IOC_PAD_PAD_CTL_SPD_SHIFT) + +/* + * DS (RW) + * + * drive strength + * 1.8V Mode: + * 000: 260 Ohm + * 001: 260 Ohm + * 010: 130 Ohm + * 011: 88 Ohm + * 100: 65 Ohm + * 101: 52 Ohm + * 110: 43 Ohm + * 111: 37 Ohm + * 3.3V Mode: + * 000: 157 Ohm + * 001: 157 Ohm + * 010: 78 Ohm + * 011: 53 Ohm + * 100: 39 Ohm + * 101: 32 Ohm + * 110: 26 Ohm + * 111: 23 Ohm + */ +#define IOC_PAD_PAD_CTL_DS_MASK (0x7U) +#define IOC_PAD_PAD_CTL_DS_SHIFT (0U) +#define IOC_PAD_PAD_CTL_DS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_DS_SHIFT) & IOC_PAD_PAD_CTL_DS_MASK) +#define IOC_PAD_PAD_CTL_DS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_DS_MASK) >> IOC_PAD_PAD_CTL_DS_SHIFT) + + + +/* PAD register group index macro definition */ +#define IOC_PAD_PA00 (0UL) +#define IOC_PAD_PA01 (1UL) +#define IOC_PAD_PA02 (2UL) +#define IOC_PAD_PA03 (3UL) +#define IOC_PAD_PA04 (4UL) +#define IOC_PAD_PA05 (5UL) +#define IOC_PAD_PA06 (6UL) +#define IOC_PAD_PA07 (7UL) +#define IOC_PAD_PA08 (8UL) +#define IOC_PAD_PA09 (9UL) +#define IOC_PAD_PA10 (10UL) +#define IOC_PAD_PA11 (11UL) +#define IOC_PAD_PA12 (12UL) +#define IOC_PAD_PA13 (13UL) +#define IOC_PAD_PA14 (14UL) +#define IOC_PAD_PA15 (15UL) +#define IOC_PAD_PA16 (16UL) +#define IOC_PAD_PA17 (17UL) +#define IOC_PAD_PA18 (18UL) +#define IOC_PAD_PA19 (19UL) +#define IOC_PAD_PA20 (20UL) +#define IOC_PAD_PA21 (21UL) +#define IOC_PAD_PA22 (22UL) +#define IOC_PAD_PA23 (23UL) +#define IOC_PAD_PA24 (24UL) +#define IOC_PAD_PA25 (25UL) +#define IOC_PAD_PA26 (26UL) +#define IOC_PAD_PA27 (27UL) +#define IOC_PAD_PA28 (28UL) +#define IOC_PAD_PA29 (29UL) +#define IOC_PAD_PA30 (30UL) +#define IOC_PAD_PA31 (31UL) +#define IOC_PAD_PB00 (32UL) +#define IOC_PAD_PB01 (33UL) +#define IOC_PAD_PB02 (34UL) +#define IOC_PAD_PB03 (35UL) +#define IOC_PAD_PB04 (36UL) +#define IOC_PAD_PB05 (37UL) +#define IOC_PAD_PB06 (38UL) +#define IOC_PAD_PB07 (39UL) +#define IOC_PAD_PB08 (40UL) +#define IOC_PAD_PB09 (41UL) +#define IOC_PAD_PB10 (42UL) +#define IOC_PAD_PB11 (43UL) +#define IOC_PAD_PB12 (44UL) +#define IOC_PAD_PB13 (45UL) +#define IOC_PAD_PB14 (46UL) +#define IOC_PAD_PB15 (47UL) +#define IOC_PAD_PX00 (416UL) +#define IOC_PAD_PX01 (416UL) +#define IOC_PAD_PX02 (417UL) +#define IOC_PAD_PX03 (417UL) +#define IOC_PAD_PX04 (418UL) +#define IOC_PAD_PX05 (418UL) +#define IOC_PAD_PX06 (419UL) +#define IOC_PAD_PX07 (419UL) +#define IOC_PAD_PY00 (448UL) +#define IOC_PAD_PY01 (449UL) +#define IOC_PAD_PY02 (450UL) +#define IOC_PAD_PY03 (451UL) +#define IOC_PAD_PY04 (452UL) +#define IOC_PAD_PY05 (453UL) +#define IOC_PAD_PY06 (454UL) +#define IOC_PAD_PY07 (455UL) + + +#endif /* HPM_IOC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_iomux.h new file mode 100644 index 00000000000..5051d4ab60f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_iomux.h @@ -0,0 +1,423 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_IOMUX_H +#define HPM_IOMUX_H + +/* IOC_PA00_FUNC_CTL function mux definitions */ +#define IOC_PA00_FUNC_CTL_GPIO_A_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA00_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA00_FUNC_CTL_SYSCTL_CLK_OBS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA01_FUNC_CTL function mux definitions */ +#define IOC_PA01_FUNC_CTL_GPIO_A_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA01_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA01_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PA01_FUNC_CTL_SYSCTL_CLK_OBS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA02_FUNC_CTL function mux definitions */ +#define IOC_PA02_FUNC_CTL_GPIO_A_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA02_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA02_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA02_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA02_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PA02_FUNC_CTL_SYSCTL_CLK_OBS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA03_FUNC_CTL function mux definitions */ +#define IOC_PA03_FUNC_CTL_GPIO_A_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA03_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA03_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA03_FUNC_CTL_SPI3_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA03_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA03_FUNC_CTL_SYSCTL_CLK_OBS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA04_FUNC_CTL function mux definitions */ +#define IOC_PA04_FUNC_CTL_GPIO_A_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA04_FUNC_CTL_SPI0_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA04_FUNC_CTL_JTAG_TDO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA05_FUNC_CTL function mux definitions */ +#define IOC_PA05_FUNC_CTL_GPIO_A_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA05_FUNC_CTL_GPTMR1_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA05_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA05_FUNC_CTL_JTAG_TDI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA06_FUNC_CTL function mux definitions */ +#define IOC_PA06_FUNC_CTL_GPIO_A_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA06_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA06_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA06_FUNC_CTL_JTAG_TCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA07_FUNC_CTL function mux definitions */ +#define IOC_PA07_FUNC_CTL_GPIO_A_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA07_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA07_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA07_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA07_FUNC_CTL_JTAG_TMS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA08_FUNC_CTL function mux definitions */ +#define IOC_PA08_FUNC_CTL_GPIO_A_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA08_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA08_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA08_FUNC_CTL_SPI3_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA08_FUNC_CTL_JTAG_TRST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA09_FUNC_CTL function mux definitions */ +#define IOC_PA09_FUNC_CTL_GPIO_A_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA09_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA09_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA09_FUNC_CTL_SPI3_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA09_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA10_FUNC_CTL function mux definitions */ +#define IOC_PA10_FUNC_CTL_GPIO_A_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA10_FUNC_CTL_GPTMR0_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA10_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA10_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA10_FUNC_CTL_SPI3_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA10_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PA11_FUNC_CTL function mux definitions */ +#define IOC_PA11_FUNC_CTL_GPIO_A_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA11_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA11_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA11_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA11_FUNC_CTL_EWDG0_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA12_FUNC_CTL function mux definitions */ +#define IOC_PA12_FUNC_CTL_GPIO_A_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA12_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA12_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA12_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) + +/* IOC_PA13_FUNC_CTL function mux definitions */ +#define IOC_PA13_FUNC_CTL_GPIO_A_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA13_FUNC_CTL_GPTMR1_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA13_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA13_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA13_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA13_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) + +/* IOC_PA14_FUNC_CTL function mux definitions */ +#define IOC_PA14_FUNC_CTL_GPIO_A_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA14_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA14_FUNC_CTL_SPI3_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA14_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA14_FUNC_CTL_EWDG1_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA15_FUNC_CTL function mux definitions */ +#define IOC_PA15_FUNC_CTL_GPIO_A_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA15_FUNC_CTL_GPTMR0_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA15_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA15_FUNC_CTL_SPI3_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA15_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA15_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA16_FUNC_CTL function mux definitions */ +#define IOC_PA16_FUNC_CTL_GPIO_A_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) + +/* IOC_PA17_FUNC_CTL function mux definitions */ +#define IOC_PA17_FUNC_CTL_GPIO_A_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) + +/* IOC_PA18_FUNC_CTL function mux definitions */ +#define IOC_PA18_FUNC_CTL_GPIO_A_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA18_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) + +/* IOC_PA19_FUNC_CTL function mux definitions */ +#define IOC_PA19_FUNC_CTL_GPIO_A_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA19_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA19_FUNC_CTL_SPI1_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) + +/* IOC_PA20_FUNC_CTL function mux definitions */ +#define IOC_PA20_FUNC_CTL_GPIO_A_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA20_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) + +/* IOC_PA21_FUNC_CTL function mux definitions */ +#define IOC_PA21_FUNC_CTL_GPIO_A_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA21_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) + +/* IOC_PA22_FUNC_CTL function mux definitions */ +#define IOC_PA22_FUNC_CTL_GPIO_A_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA22_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA22_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) + +/* IOC_PA23_FUNC_CTL function mux definitions */ +#define IOC_PA23_FUNC_CTL_GPIO_A_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA23_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA23_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) + +/* IOC_PA24_FUNC_CTL function mux definitions */ +#define IOC_PA24_FUNC_CTL_GPIO_A_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA24_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA24_FUNC_CTL_SPI1_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA24_FUNC_CTL_XPI0_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PA25_FUNC_CTL function mux definitions */ +#define IOC_PA25_FUNC_CTL_GPIO_A_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA25_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA25_FUNC_CTL_SPI1_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA25_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PA26_FUNC_CTL function mux definitions */ +#define IOC_PA26_FUNC_CTL_GPIO_A_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA26_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA26_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA26_FUNC_CTL_SYSCTL_CLK_OBS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA27_FUNC_CTL function mux definitions */ +#define IOC_PA27_FUNC_CTL_GPIO_A_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA27_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA27_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA27_FUNC_CTL_SYSCTL_CLK_OBS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA28_FUNC_CTL function mux definitions */ +#define IOC_PA28_FUNC_CTL_GPIO_A_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA28_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA28_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA28_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA28_FUNC_CTL_SYSCTL_CLK_OBS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA29_FUNC_CTL function mux definitions */ +#define IOC_PA29_FUNC_CTL_GPIO_A_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA29_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA29_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA29_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA29_FUNC_CTL_SYSCTL_CLK_OBS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) +#define IOC_PA29_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) + +/* IOC_PA30_FUNC_CTL function mux definitions */ +#define IOC_PA30_FUNC_CTL_GPIO_A_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA30_FUNC_CTL_SPI1_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA30_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA30_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) +#define IOC_PA30_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) + +/* IOC_PA31_FUNC_CTL function mux definitions */ +#define IOC_PA31_FUNC_CTL_GPIO_A_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA31_FUNC_CTL_SPI1_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA31_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA31_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) + +/* IOC_PB00_FUNC_CTL function mux definitions */ +#define IOC_PB00_FUNC_CTL_GPIO_B_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB00_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB00_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PB01_FUNC_CTL function mux definitions */ +#define IOC_PB01_FUNC_CTL_GPIO_B_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB01_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB01_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PB02_FUNC_CTL function mux definitions */ +#define IOC_PB02_FUNC_CTL_GPIO_B_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB02_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB02_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB02_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB03_FUNC_CTL function mux definitions */ +#define IOC_PB03_FUNC_CTL_GPIO_B_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB03_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB03_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB03_FUNC_CTL_SPI2_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB03_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB04_FUNC_CTL function mux definitions */ +#define IOC_PB04_FUNC_CTL_GPIO_B_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB04_FUNC_CTL_SPI3_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) + +/* IOC_PB05_FUNC_CTL function mux definitions */ +#define IOC_PB05_FUNC_CTL_GPIO_B_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB05_FUNC_CTL_GPTMR1_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB05_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) + +/* IOC_PB06_FUNC_CTL function mux definitions */ +#define IOC_PB06_FUNC_CTL_GPIO_B_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB06_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB06_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) + +/* IOC_PB07_FUNC_CTL function mux definitions */ +#define IOC_PB07_FUNC_CTL_GPIO_B_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB07_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB07_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB07_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) + +/* IOC_PB08_FUNC_CTL function mux definitions */ +#define IOC_PB08_FUNC_CTL_GPIO_B_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB08_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB08_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB08_FUNC_CTL_SPI2_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB08_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB08_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) + +/* IOC_PB09_FUNC_CTL function mux definitions */ +#define IOC_PB09_FUNC_CTL_GPIO_B_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB09_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB09_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB09_FUNC_CTL_SPI2_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB09_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB09_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) + +/* IOC_PB10_FUNC_CTL function mux definitions */ +#define IOC_PB10_FUNC_CTL_GPIO_B_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB10_FUNC_CTL_GPTMR0_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB10_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB10_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB10_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB10_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB10_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) + +/* IOC_PB11_FUNC_CTL function mux definitions */ +#define IOC_PB11_FUNC_CTL_GPIO_B_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB11_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB11_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB11_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB12_FUNC_CTL function mux definitions */ +#define IOC_PB12_FUNC_CTL_GPIO_B_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB12_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB12_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB12_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) + +/* IOC_PB13_FUNC_CTL function mux definitions */ +#define IOC_PB13_FUNC_CTL_GPIO_B_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB13_FUNC_CTL_GPTMR1_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB13_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB13_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB13_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB13_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) + +/* IOC_PB14_FUNC_CTL function mux definitions */ +#define IOC_PB14_FUNC_CTL_GPIO_B_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB14_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB14_FUNC_CTL_SPI2_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) + +/* IOC_PB15_FUNC_CTL function mux definitions */ +#define IOC_PB15_FUNC_CTL_GPIO_B_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB15_FUNC_CTL_GPTMR0_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB15_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB15_FUNC_CTL_SPI2_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) + +/* IOC_PX00_FUNC_CTL function mux definitions */ +#define IOC_PX00_FUNC_CTL_GPIO_X_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX00_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX01_FUNC_CTL function mux definitions */ +#define IOC_PX01_FUNC_CTL_GPIO_X_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX01_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX02_FUNC_CTL function mux definitions */ +#define IOC_PX02_FUNC_CTL_GPIO_X_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX02_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PX02_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX03_FUNC_CTL function mux definitions */ +#define IOC_PX03_FUNC_CTL_GPIO_X_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX03_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PX03_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX04_FUNC_CTL function mux definitions */ +#define IOC_PX04_FUNC_CTL_GPIO_X_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX04_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PX04_FUNC_CTL_XPI0_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX05_FUNC_CTL function mux definitions */ +#define IOC_PX05_FUNC_CTL_GPIO_X_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX05_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PX05_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX06_FUNC_CTL function mux definitions */ +#define IOC_PX06_FUNC_CTL_GPIO_X_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX06_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PX06_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PX06_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX07_FUNC_CTL function mux definitions */ +#define IOC_PX07_FUNC_CTL_GPIO_X_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX07_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PX07_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PX07_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PY00_FUNC_CTL function mux definitions */ +#define IOC_PY00_FUNC_CTL_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY00_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) + +/* IOC_PY01_FUNC_CTL function mux definitions */ +#define IOC_PY01_FUNC_CTL_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY01_FUNC_CTL_EWDG0_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) +#define IOC_PY01_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) + +/* IOC_PY02_FUNC_CTL function mux definitions */ +#define IOC_PY02_FUNC_CTL_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY02_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PY02_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PY02_FUNC_CTL_EWDG1_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) +#define IOC_PY02_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) + +/* IOC_PY03_FUNC_CTL function mux definitions */ +#define IOC_PY03_FUNC_CTL_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY03_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PY03_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PY04_FUNC_CTL function mux definitions */ +#define IOC_PY04_FUNC_CTL_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY04_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) + +/* IOC_PY05_FUNC_CTL function mux definitions */ +#define IOC_PY05_FUNC_CTL_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY05_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY05_FUNC_CTL_EWDG0_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PY06_FUNC_CTL function mux definitions */ +#define IOC_PY06_FUNC_CTL_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY06_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PY06_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY06_FUNC_CTL_EWDG1_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PY07_FUNC_CTL function mux definitions */ +#define IOC_PY07_FUNC_CTL_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY07_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PY07_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) + + +#endif /* HPM_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_l1c_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_l1c_drv.c new file mode 100644 index 00000000000..c55600dcdcc --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_l1c_drv.c @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2021-2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_l1c_drv.h" +#include + + +#define ASSERT_ADDR_SIZE(addr, size) do { \ + assert(address % HPM_L1C_CACHELINE_SIZE == 0); \ + assert(size % HPM_L1C_CACHELINE_SIZE == 0); \ + } while (0) + +static void l1c_op(uint8_t opcode, uint32_t address, uint32_t size) +{ + register uint32_t i; + register uint32_t next_address; + register uint32_t tmp; + register uint32_t csr; + + csr = read_clear_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); + +#define CCTL_VERSION (3U << 18) + + if ((read_csr(CSR_MMSC_CFG) & CCTL_VERSION)) { + l1c_cctl_address(address); + next_address = address; + while ((next_address < (address + size)) && (next_address >= address)) { + l1c_cctl_cmd(opcode); + next_address = l1c_cctl_get_address(); + } + } else { + for (i = 0, tmp = 0; tmp < size; i++) { + l1c_cctl_address_cmd(opcode, address + i * HPM_L1C_CACHELINE_SIZE); + tmp += HPM_L1C_CACHELINE_SIZE; + } + } + + write_csr(CSR_MSTATUS, csr); +} + +void l1c_dc_enable(void) +{ + if (!l1c_dc_is_enabled()) { + clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_DC_WAROUND_MASK); + set_csr(CSR_MCACHE_CTL, +#ifdef L1C_DC_WAROUND_VALUE + HPM_MCACHE_CTL_DC_WAROUND(L1C_DC_WAROUND_VALUE) | +#endif + HPM_MCACHE_CTL_DPREF_EN_MASK + | HPM_MCACHE_CTL_DC_EN_MASK); + } +} + +void l1c_dc_disable(void) +{ + if (l1c_dc_is_enabled()) { + clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_DC_EN_MASK); + } +} + +void l1c_ic_enable(void) +{ + if (!l1c_ic_is_enabled()) { + set_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_IPREF_EN_MASK + | HPM_MCACHE_CTL_CCTL_SUEN_MASK + | HPM_MCACHE_CTL_IC_EN_MASK); + } +} + +void l1c_ic_disable(void) +{ + if (l1c_ic_is_enabled()) { + clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_IC_EN_MASK); + } +} + +void l1c_fence_i(void) +{ + __asm("fence.i"); +} + +void l1c_dc_invalidate_all(void) +{ + l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_INVAL_ALL); +} + +void l1c_dc_writeback_all(void) +{ + l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_WB_ALL); +} + +void l1c_dc_flush_all(void) +{ + l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_WBINVAL_ALL); +} + +void l1c_dc_fill_lock(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_LOCK, address, size); +} + +void l1c_dc_invalidate(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_INVAL, address, size); +} + +void l1c_dc_writeback(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_WB, address, size); +} + +void l1c_dc_flush(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_WBINVAL, address, size); +} + +void l1c_ic_invalidate(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1I_VA_INVAL, address, size); +} + +void l1c_ic_fill_lock(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1I_VA_LOCK, address, size); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_l1c_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_l1c_drv.h new file mode 100644 index 00000000000..e3034e6e831 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_l1c_drv.h @@ -0,0 +1,485 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_L1_CACHE_H +#define _HPM_L1_CACHE_H +#include "hpm_common.h" +#include "hpm_csr_drv.h" +#include "hpm_soc.h" + +/** + * + * @brief L1CACHE driver APIs + * @defgroup l1cache_interface L1CACHE driver APIs + * @{ + */ + +/* cache size is 16KB */ +#define HPM_L1C_CACHE_SIZE (uint32_t)(16 * SIZE_1KB) +#define HPM_L1C_ICACHE_SIZE (HPM_L1C_CACHE_SIZE) +#define HPM_L1C_DCACHE_SIZE (HPM_L1C_CACHE_SIZE) +/* cache line size is 32B */ +#define HPM_L1C_CACHELINE_SIZE (32) +/* cache way is 128 */ +#define HPM_L1C_CACHELINES_PER_WAY (128) + +/* mcache_ctl register */ +/* + * Controls if the instruction cache is enabled or not. + * + * 0 I-Cache is disabled + * 1 I-Cache is enabled + */ +#define HPM_MCACHE_CTL_IC_EN_SHIFT (0UL) +#define HPM_MCACHE_CTL_IC_EN_MASK (1UL << HPM_MCACHE_CTL_IC_EN_SHIFT) +#define HPM_MCACHE_CTL_IC_EN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IC_EN_SHIFT) & HPM_MCACHE_CTL_IC_EN_MASK) + +/* + * Controls if the data cache is enabled or not. + * + * 0 D-Cache is disabled + * 1 D-Cache is enabled + */ +#define HPM_MCACHE_CTL_DC_EN_SHIFT (1UL) +#define HPM_MCACHE_CTL_DC_EN_MASK (1UL << HPM_MCACHE_CTL_DC_EN_SHIFT) +#define HPM_MCACHE_CTL_DC_EN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_EN_SHIFT) & HPM_MCACHE_CTL_DC_EN_MASK) + +/* + * Parity/ECC error checking enable control for the instruction cache. + * + * 0 Disable parity/ECC + * 1 Reserved + * 2 Generate exceptions only on uncorrectable parity/ECC errors + * 3 Generate exceptions on any type of parity/ECC errors + */ +#define HPM_MCACHE_CTL_IC_ECCEN_SHIFT (0x2UL) +#define HPM_MCACHE_CTL_IC_ECCEN_MASK (0x3UL << HPM_MCACHE_CTL_IC_ECCEN_SHIFT) +#define HPM_MCACHE_CTL_IC_ECCEN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IC_ECCEN_SHIFT) & HPM_MCACHE_CTL_IC_ECCEN_MASK) + +/* + * + * Parity/ECC error checking enable control for the data cache. + * + * 0 Disable parity/ECC + * 1 Reserved + * 2 Generate exceptions only on uncorrectable parity/ECC errors + * 3 Generate exceptions on any type of parity/ECC errors + */ +#define HPM_MCACHE_CTL_DC_ECCEN_SHIFT (0x4UL) +#define HPM_MCACHE_CTL_DC_ECCEN_MASK (0x3UL << HPM_MCACHE_CTL_DC_ECCEN_SHIFT) +#define HPM_MCACHE_CTL_DC_ECCEN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_ECCEN_SHIFT) & HPM_MCACHE_CTL_DC_ECCEN_MASK) + +/* + * + * Controls diagnostic accesses of ECC codes of the instruction cache RAMs. + * It is set to enable CCTL operations to access the ECC codes. This bit + * can be set for injecting ECC errors to test the ECC handler. + * + * 0 Disable diagnostic accesses of ECC codes + * 1 Enable diagnostic accesses of ECC codes + */ +#define HPM_MCACHE_CTL_IC_RWECC_SHIFT (0x6UL) +#define HPM_MCACHE_CTL_IC_RWECC_MASK (0x1UL << HPM_MCACHE_CTL_IC_RWECC_SHIFT) +#define HPM_MCACHE_CTL_IC_RWECC(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IC_RWECC_SHIFT) & HPM_MCACHE_CTL_IC_RWECC_MASK) + +/* + * + * Controls diagnostic accesses of ECC codes of the data cache RAMs. It is + * set to enable CCTL operations to access the ECC codes. This bit can be + * set for injecting + * + * ECC errors to test the ECC handler. + * 0 Disable diagnostic accesses of ECC codes + * 1 Enable diagnostic accesses of ECC codes + */ +#define HPM_MCACHE_CTL_DC_RWECC_SHIFT (0x7UL) +#define HPM_MCACHE_CTL_DC_RWECC_MASK (0x1UL << HPM_MCACHE_CTL_DC_RWECC_SHIFT) +#define HPM_MCACHE_CTL_DC_RWECC(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_RWECC_SHIFT) & HPM_MCACHE_CTL_DC_RWECC_MASK) + +/* + * Enable bit for Superuser-mode and User-mode software to access + * ucctlbeginaddr and ucctlcommand CSRs. + * + * 0 Disable ucctlbeginaddr and ucctlcommand accesses in S/U mode + * 1 Enable ucctlbeginaddr and ucctlcommand accesses in S/U mode + */ +#define HPM_MCACHE_CTL_CCTL_SUEN_SHIFT (0x8UL) +#define HPM_MCACHE_CTL_CCTL_SUEN_MASK (0x1UL << HPM_MCACHE_CTL_CCTL_SUEN_SHIFT) +#define HPM_MCACHE_CTL_CCTL_SUEN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_CCTL_SUEN_SHIFT) & HPM_MCACHE_CTL_CCTL_SUEN_MASK) + +/* + * This bit controls hardware prefetch for instruction fetches to cacheable + * memory regions when I-Cache size is not 0. + * + * 0 Disable hardware prefetch on instruction fetches + * 1 Enable hardware prefetch on instruction fetches + */ +#define HPM_MCACHE_CTL_IPREF_EN_SHIFT (0x9UL) +#define HPM_MCACHE_CTL_IPREF_EN_MASK (0x1UL << HPM_MCACHE_CTL_IPREF_EN_SHIFT) +#define HPM_MCACHE_CTL_IPREF_EN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IPREF_EN_SHIFT) & HPM_MCACHE_CTL_IPREF_EN_MASK) + +/* + * This bit controls hardware prefetch for load/store accesses to cacheable + * memory regions when D-Cache size is not 0. + * + * 0 Disable hardware prefetch on load/store memory accesses. + * 1 Enable hardware prefetch on load/store memory accesses. + */ +#define HPM_MCACHE_CTL_DPREF_EN_SHIFT (0x10UL) +#define HPM_MCACHE_CTL_DPREF_EN_MASK (0x1UL << HPM_MCACHE_CTL_DPREF_EN_SHIFT) +#define HPM_MCACHE_CTL_DPREF_EN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DPREF_EN_SHIFT) & HPM_MCACHE_CTL_DPREF_EN_MASK) + +/* + * I-Cache miss allocation filling policy Value Meaning + * + * 0 Cache line data is returned critical (double) word first + * 1 Cache line data is returned the lowest address (double) word first + */ +#define HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT (0x11UL) +#define HPM_MCACHE_CTL_IC_FIRST_WORD_MASK (0x1UL << HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT) +#define HPM_MCACHE_CTL_IC_FIRST_WORD(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT) & HPM_MCACHE_CTL_IC_FIRST_WORD_MASK) + +/* + * D-Cache miss allocation filling policy + * + * 0 Cache line data is returned critical (double) word first + * 1 Cache line data is returned the lowest address (double) word first + */ +#define HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT (0x12UL) +#define HPM_MCACHE_CTL_DC_FIRST_WORD_MASK (0x1UL << HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT) +#define HPM_MCACHE_CTL_DC_FIRST_WORD(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT) & HPM_MCACHE_CTL_DC_FIRST_WORD_MASK) + +/* + * D-Cache Write-Around threshold + * + * 0 Disables streaming. All cacheable write misses allocate a cache line + * according to PMA settings. + * 1 Override PMA setting and do not allocate D-Cache entries after + * consecutive stores to 4 cache lines. + * 2 Override PMA setting and do not allocate D-Cache entries after + * consecutive stores to 64 cache lines. + * 3 Override PMA setting and do not allocate D-Cache entries after + * consecutive stores to 128 cache lines. + */ +#define HPM_MCACHE_CTL_DC_WAROUND_SHIFT (0x13UL) +#define HPM_MCACHE_CTL_DC_WAROUND_MASK (0x3UL << HPM_MCACHE_CTL_DC_WAROUND_SHIFT) +#define HPM_MCACHE_CTL_DC_WAROUND(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_WAROUND_SHIFT) & HPM_MCACHE_CTL_DC_WAROUND_MASK) + +/* CCTL command list */ +#define HPM_L1C_CCTL_CMD_L1D_VA_INVAL (0UL) +#define HPM_L1C_CCTL_CMD_L1D_VA_WB (1UL) +#define HPM_L1C_CCTL_CMD_L1D_VA_WBINVAL (2UL) +#define HPM_L1C_CCTL_CMD_L1D_VA_LOCK (3UL) +#define HPM_L1C_CCTL_CMD_L1D_VA_UNLOCK (4UL) +#define HPM_L1C_CCTL_CMD_L1D_WBINVAL_ALL (6UL) +#define HPM_L1C_CCTL_CMD_L1D_WB_ALL (7UL) + +#define HPM_L1C_CCTL_CMD_L1I_VA_INVAL (8UL) +#define HPM_L1C_CCTL_CMD_L1I_VA_LOCK (11UL) +#define HPM_L1C_CCTL_CMD_L1I_VA_UNLOCK (12UL) + +#define HPM_L1C_CCTL_CMD_L1D_IX_INVAL (16UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_WB (17UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_WBINVAL (18UL) + +#define HPM_L1C_CCTL_CMD_L1D_IX_RTAG (19UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_RDATA (20UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_WTAG (21UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_WDATA (22UL) + +#define HPM_L1C_CCTL_CMD_L1D_INVAL_ALL (23UL) + +#define HPM_L1C_CCTL_CMD_L1I_IX_INVAL (24UL) +#define HPM_L1C_CCTL_CMD_L1I_IX_RTAG (27UL) +#define HPM_L1C_CCTL_CMD_L1I_IX_RDATA (28UL) +#define HPM_L1C_CCTL_CMD_L1I_IX_WTAG (29UL) +#define HPM_L1C_CCTL_CMD_L1I_IX_WDATA (30UL) + +#define HPM_L1C_CCTL_CMD_SUCCESS (1UL) +#define HPM_L1C_CCTL_CMD_FAIL (0UL) + +#ifdef __cplusplus +extern "C" { +#endif +/* get cache control register value */ +__attribute__((always_inline)) static inline uint32_t l1c_get_control(void) +{ + return read_csr(CSR_MCACHE_CTL); +} + +__attribute__((always_inline)) static inline bool l1c_dc_is_enabled(void) +{ + return l1c_get_control() & HPM_MCACHE_CTL_DC_EN_MASK; +} + +__attribute__((always_inline)) static inline bool l1c_ic_is_enabled(void) +{ + return l1c_get_control() & HPM_MCACHE_CTL_IC_EN_MASK; +} + +/* mcctlbeginaddress register bitfield layout for CCTL IX type command */ +#define HPM_MCCTLBEGINADDR_OFFSET_SHIFT (2UL) +#define HPM_MCCTLBEGINADDR_OFFSET_MASK ((uint32_t) 0xF << HPM_MCCTLBEGINADDR_OFFSET_SHIFT) +#define HPM_MCCTLBEGINADDR_OFFSET(x) \ + (uint32_t)(((x) << HPM_MCCTLBEGINADDR_OFFSET_SHIFT) & HPM_MCCTLBEGINADDR_OFFSET_MASK) +#define HPM_MCCTLBEGINADDR_INDEX_SHIFT (6UL) +#define HPM_MCCTLBEGINADDR_INDEX_MASK ((uint32_t) 0x3F << HPM_MCCTLBEGINADDR_INDEX_SHIFT) +#define HPM_MCCTLBEGINADDR_INDEX(x) \ + (uint32_t)(((x) << HPM_MCCTLBEGINADDR_INDEX_SHIFT) & HPM_MCCTLBEGINADDR_INDEX_MASK) +#define HPM_MCCTLBEGINADDR_WAY_SHIFT (13UL) +#define HPM_MCCTLBEGINADDR_WAY_MASK ((uint32_t) 0x3 << HPM_MCCTLBEGINADDR_WAY_SHIFT) +#define HPM_MCCTLBEGINADDR_WAY(x) \ + (uint32_t)(((x) << HPM_MCCTLBEGINADDR_WAY_SHIFT) & HPM_MCCTLBEGINADDR_WAY_MASK) + +/* send IX command */ +__attribute__((always_inline)) static inline void l1c_cctl_address(uint32_t address) +{ + write_csr(CSR_MCCTLBEGINADDR, address); +} + +/* send command */ +__attribute__((always_inline)) static inline void l1c_cctl_cmd(uint8_t cmd) +{ + write_csr(CSR_MCCTLCOMMAND, cmd); +} + +__attribute__((always_inline)) static inline uint32_t l1c_cctl_get_address(void) +{ + return read_csr(CSR_MCCTLBEGINADDR); +} + +/* send IX command */ +__attribute__((always_inline)) static inline + void l1c_cctl_address_cmd(uint8_t cmd, uint32_t address) +{ + write_csr(CSR_MCCTLBEGINADDR, address); + write_csr(CSR_MCCTLCOMMAND, cmd); +} + +#define HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT (2UL) +#define HPM_MCCTLDATA_I_TAG_ADDRESS_MASK (uint32_t)(0XFFFFF << HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT) +#define HPM_MCCTLDATA_I_TAG_ADDRESS(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT) & HPM_MCCTLDATA_I_TAG_ADDRESS_MASK) + +#define HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT (29UL) +#define HPM_MCCTLDATA_I_TAG_LOCK_DUP_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT) +#define HPM_MCCTLDATA_I_TAG_LOCK_DUP(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT) & HPM_MCCTLDATA_I_TAG_LOCK_DUP_MASK) + +#define HPM_MCCTLDATA_I_TAG_LOCK_SHIFT (30UL) +#define HPM_MCCTLDATA_I_TAG_LOCK_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_LOCK_SHIFT) +#define HPM_MCCTLDATA_I_TAG_LOCK(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_LOCK_SHIFT) & HPM_MCCTLDATA_I_TAG_LOCK_MASK) + +#define HPM_MCCTLDATA_I_TAG_VALID_SHIFT (31UL) +#define HPM_MCCTLDATA_I_TAG_VALID_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_VALID_SHIFT) +#define HPM_MCCTLDATA_I_TAG_VALID(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_VALID_SHIFT) & HPM_MCCTLDATA_I_TAG_VALID_MASK) + +#define HPM_MCCTLDATA_D_TAG_MESI_SHIFT (0UL) +#define HPM_MCCTLDATA_D_TAG_MESI_MASK (uint32_t)(0x3 << HPM_MCCTLDATA_D_TAG_MESI_SHIFT) +#define HPM_MCCTLDATA_D_TAG_MESI(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_MESI_SHIFT) & HPM_MCCTLDATA_D_TAG_MESI_MASK) + +#define HPM_MCCTLDATA_D_TAG_LOCK_SHIFT (3UL) +#define HPM_MCCTLDATA_D_TAG_LOCK_MASK (uint32_t)(0x1 << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) +#define HPM_MCCTLDATA_D_TAG_LOCK(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) & HPM_MCCTLDATA_D_TAG_LOCK_MASK) + +#define HPM_MCCTLDATA_D_TAG_TAG_SHIFT (4UL) +#define HPM_MCCTLDATA_D_TAG_TAG_MASK (uint32_t)(0xFFFF << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) +#define HPM_MCCTLDATA_D_TAG_TAG(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_TAG_SHIFT) & HPM_MCCTLDATA_D_TAG_TAG_MASK) + +/* + * @brief Cache control command read address + * + * Send IX read tag/data cmd + * @param[in] cmd Command code + * @param[in] address Target address + * @param[in] ecc_data ECC value + * @return data read + */ +ATTR_ALWAYS_INLINE static inline + uint32_t l1c_cctl_address_cmd_read(uint8_t cmd, uint32_t address, uint32_t *ecc_data) +{ + write_csr(CSR_MCCTLBEGINADDR, address); + write_csr(CSR_MCCTLCOMMAND, cmd); + *ecc_data = read_csr(CSR_MECC_CODE); + return read_csr(CSR_MCCTLDATA); +} + +/* + * @brief Cache control command write address + * + * Send IX write tag/data cmd + * @param[in] cmd Command code + * @param[in] address Target address + * @param[in] data Data to be written + * @param[in] ecc_data ECC of data + */ +ATTR_ALWAYS_INLINE static inline + void l1c_cctl_address_cmd_write(uint8_t cmd, uint32_t address, uint32_t data, uint32_t ecc_data) +{ + write_csr(CSR_MCCTLBEGINADDR, address); + write_csr(CSR_MCCTLCOMMAND, cmd); + write_csr(CSR_MCCTLDATA, data); + write_csr(CSR_MECC_CODE, ecc_data); +} + +#define HPM_L1C_CFG_SET_SHIFT (0UL) +#define HPM_L1C_CFG_SET_MASK (uint32_t)(0x7 << HPM_L1C_CFG_SET_SHIFT) +#define HPM_L1C_CFG_WAY_SHIFT (3UL) +#define HPM_L1C_CFG_WAY_MASK (uint32_t)(0x7 << HPM_L1C_CFG_WAY_SHIFT) +#define HPM_L1C_CFG_SIZE_SHIFT (6UL) +#define HPM_L1C_CFG_SIZE_MASK (uint32_t)(0x7 << HPM_L1C_CFG_SIZE_SHIFT) +#define HPM_L1C_CFG_LOCK_SHIFT (9UL) +#define HPM_L1C_CFG_LOCK_MASK (uint32_t)(0x1 << HPM_L1C_CFG_LOCK_SHIFT) +#define HPM_L1C_CFG_ECC_SHIFT (10UL) +#define HPM_L1C_CFG_ECC_MASK (uint32_t)(0x3 << HPM_L1C_CFG_ECC_SHIFT) +#define HPM_L1C_CFG_LMB_SHIFT (12UL) +#define HPM_L1C_CFG_LMB_MASK (uint32_t)(0x7 << HPM_L1C_CFG_LMB_SHIFT) +#define HPM_L1C_CFG_LM_SIZE_SHIFT (15UL) +#define HPM_L1C_CFG_LM_SIZE_MASK (uint32_t)(0x1F << HPM_L1C_CFG_LM_SIZE_SHIFT) +#define HPM_L1C_CFG_LM_ECC_SHIFT (21UL) +#define HPM_L1C_CFG_LM_ECC_MASK (uint32_t)(0x3 << HPM_L1C_CFG_LM_ECC_SHIFT) +#define HPM_L1C_CFG_SETH_SHIFT (24UL) +#define HPM_L1C_CFG_SETH_MASK (uint32_t)(0x1 << HPM_L1C_CFG_SETH_SHIFT) + +/** + * @brief Align down based on cache line size + */ +#define HPM_L1C_CACHELINE_ALIGN_DOWN(n) ((uint32_t)(n) & ~(HPM_L1C_CACHELINE_SIZE - 1U)) + +/** + * @brief Align up based on cache line size + */ +#define HPM_L1C_CACHELINE_ALIGN_UP(n) HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)(n) + HPM_L1C_CACHELINE_SIZE - 1U) + +/** + * @brief Get I-cache configuration + * + * @return I-cache config register + */ +ATTR_ALWAYS_INLINE static inline uint32_t l1c_ic_get_config(void) +{ + return read_csr(CSR_MICM_CFG); +} + +/** + * @brief Get D-cache configuration + * + * @return D-cache config register + */ +ATTR_ALWAYS_INLINE static inline uint32_t l1c_dc_get_config(void) +{ + return read_csr(CSR_MDCM_CFG); +} + +/* + * @brief D-cache disable + */ +void l1c_dc_disable(void); + +/* + * @brief D-cache enable + */ +void l1c_dc_enable(void); + +/* + * @brief D-cache invalidate by address + * @param[in] address Start address to be invalidated + * @param[in] size Size of memory to be invalidated + */ +void l1c_dc_invalidate(uint32_t address, uint32_t size); + +/* + * @brief D-cache writeback by address + * @param[in] address Start address to be writtenback + * @param[in] size Size of memory to be writtenback + */ +void l1c_dc_writeback(uint32_t address, uint32_t size); + +/* + * @brief D-cache invalidate and writeback by address + * @param[in] address Start address to be invalidated and writtenback + * @param[in] size Size of memory to be invalidted and writtenback + */ +void l1c_dc_flush(uint32_t address, uint32_t size); + +/* + * @brief D-cache fill and lock by address + * @param[in] address Start address to be filled and locked + * @param[in] size Size of memory to be filled and locked + */ +void l1c_dc_fill_lock(uint32_t address, uint32_t size); + +/* + * @brief I-cache disable + */ +void l1c_ic_disable(void); + +/* + * @brief I-cache enable + */ +void l1c_ic_enable(void); + +/* + * @brief I-cache invalidate by address + * @param[in] address Start address to be invalidated + * @param[in] size Size of memory to be invalidated + */ +void l1c_ic_invalidate(uint32_t address, uint32_t size); + +/* + * @brief I-cache fill and lock by address + * @param[in] address Start address to be locked + * @param[in] size Size of memory to be locked + */ +void l1c_ic_fill_lock(uint32_t address, uint32_t size); + +/* + * @brief Invalidate all icache and writeback all dcache + */ +void l1c_fence_i(void); + +/* + * @brief Invalidate all d-cache + */ +void l1c_dc_invalidate_all(void); + +/* + * @brief Writeback all d-cache + */ +void l1c_dc_writeback_all(void); + +/* + * @brief Flush all d-cache + */ +void l1c_dc_flush_all(void); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* _HPM_L1_CACHE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_misc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_misc.h new file mode 100644 index 00000000000..367c61138a2 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_misc.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_MISC_H +#define HPM_MISC_H + +#define ILM_LOCAL_BASE (0x0U) +#define ILM_SIZE_IN_BYTE (0x20000U) +#define DLM_LOCAL_BASE (0x80000U) +#define DLM_SIZE_IN_BYTE (0x20000U) +#define CORE0_ILM_SYSTEM_BASE (0x1040000U) +#define CORE0_DLM_SYSTEM_BASE (0x1060000U) + +#define ADDRESS_IN_ILM(address) \ + ((ILM_LOCAL_BASE) <= (address)) && \ + ((ILM_LOCAL_BASE + ILM_SIZE_IN_BYTE) > (address)) +#define ADDRESS_IN_DLM(address) \ + ((DLM_LOCAL_BASE) <= (address)) && \ + ((DLM_LOCAL_BASE + DLM_SIZE_IN_BYTE) > (address)) +#define ADDRESS_IN_CORE0_DLM_SYSTEM(address) \ + ((CORE0_DLM_SYSTEM_BASE) <= (address)) && \ + ((CORE0_DLM_SYSTEM_BASE + DLM_SIZE_IN_BYTE) > (address)) + +#define DLM_TO_SYSTEM(address) \ + (CORE0_DLM_SYSTEM_BASE + (address) - (DLM_LOCAL_BASE)) +#define ILM_TO_SYSTEM(address) \ + (CORE0_ILM_SYSTEM_BASE + (address) - (ILM_LOCAL_BASE)) +#define SYSTEM_TO_DLM(address) \ + ((address) - CORE0_DLM_SYSTEM_BASE + (DLM_LOCAL_BASE)) + +#define HPM_CORE0 (0U) + +/* map core local memory(DLM/ILM) to system address */ +static inline uint32_t core_local_mem_to_sys_address(uint8_t core_id, uint32_t addr) +{ + (void) core_id; + return addr; +} + +/* map system address to core local memory(DLM/ILM) */ +static inline uint32_t sys_address_to_core_local_mem(uint8_t core_id, uint32_t addr) +{ + (void) core_id; + return addr; +} +#endif /* HPM_MISC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_otp_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_otp_drv.c new file mode 100644 index 00000000000..a68fc69c0e0 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_otp_drv.c @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_otp_drv.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +#define SHADOW_INDEX_IN_PMIC_OTP_END (15U) +#define OTP_UNLOCK_MAGIC_NUM (0x4E45504FUL) /*!< ASCII: OPEN */ +#define OTP_LOCK_MAGIC_NUM (~OTP_UNLOCK_MAGIC_NUM) +#define OTP_CMD_PROGRAM (0x574F4C42UL) /*!< ASCII: BLOW */ +#define OTP_CMD_READ (0x44414552UL) /*!< ASCII: READ */ + + +/*********************************************************************************************************************** + * Codes + **********************************************************************************************************************/ +void otp_init(void) +{ + +} + +void otp_deinit(void) +{ + +} + +uint32_t otp_read_from_shadow(uint32_t addr) +{ + uint32_t ret_val = 0; + if (addr < ARRAY_SIZE(HPM_OTP->SHADOW)) { + ret_val = HPM_OTP->SHADOW[addr]; + } + + return ret_val; +} + +uint32_t otp_read_from_ip(uint32_t addr) +{ + uint32_t ret_val = 0; + if (addr < ARRAY_SIZE(HPM_OTP->SHADOW)) { + ret_val = HPM_OTP->FUSE[addr]; + } + return ret_val; +} + +hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words) +{ + hpm_stat_t status = status_invalid_argument; + do { + uint32_t fuse_idx_max = ARRAY_SIZE(HPM_OTP->SHADOW); + HPM_BREAK_IF((addr >= fuse_idx_max) || (num_of_words > fuse_idx_max) || (addr + num_of_words > fuse_idx_max)); + + /* Enable 2.5V LDO for FUSE programming */ + uint32_t reg_val = (HPM_PCFG->LDO2P5 & ~PCFG_LDO2P5_VOLT_MASK) | PCFG_LDO2P5_ENABLE_MASK | PCFG_LDO2P5_VOLT_SET(2500); + HPM_PCFG->LDO2P5 = reg_val; + /* Wait until LDO is ready */ + while (!IS_HPM_BITMASK_SET(HPM_PCFG->LDO2P5, PCFG_DCDC_MODE_READY_MASK)) { + } + HPM_OTP->UNLOCK = OTP_UNLOCK_MAGIC_NUM; + for (uint32_t i = 0; i < num_of_words; i++) { + HPM_OTP->FUSE[addr++] = *src++; + } + HPM_OTP->UNLOCK = OTP_LOCK_MAGIC_NUM; + /* Disable 2.5V LDO after FUSE programming for saving power */ + HPM_PCFG->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; + status = status_success; + } while (false); + + return status; +} + +hpm_stat_t otp_reload(otp_region_t region) +{ + hpm_stat_t status = status_invalid_argument; + if ((uint32_t)region < 0x10 && (region >= otp_region0_mask)) { + HPM_OTP->LOAD_REQ = (uint32_t)region; + HPM_OTP->LOAD_COMP = (uint32_t)region; + while (!IS_HPM_BITMASK_SET(HPM_OTP->LOAD_COMP, region)) { + + } + status = status_success; + } + + return status; +} + +hpm_stat_t otp_lock_otp(uint32_t addr, otp_lock_option_t lock_option) +{ + hpm_stat_t status = status_invalid_argument; + + do { + HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW) || (lock_option > otp_lock_option_max)); + + OTP_Type *otp_base = HPM_OTP; + + uint32_t lock_reg_idx = (addr << 1) / 32; + uint32_t lock_reg_offset = (addr << 1) % 32; + + uint32_t lock_mask = ((uint32_t)lock_option) << lock_reg_offset; + + otp_base->FUSE_LOCK[lock_reg_idx] = lock_mask; + + status = status_success; + } while (false); + + return status; +} + +hpm_stat_t otp_lock_shadow(uint32_t addr, otp_lock_option_t lock_option) +{ + hpm_stat_t status = status_invalid_argument; + + do { + HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW) || (lock_option > otp_lock_option_max)); + + OTP_Type *otp_base = HPM_OTP; + + uint32_t lock_reg_idx = (addr << 1) / 32; + uint32_t lock_reg_offset = (addr << 1) % 32; + + uint32_t lock_mask = ((uint32_t)lock_option) << lock_reg_offset; + + otp_base->SHADOW_LOCK[lock_reg_idx] = lock_mask; + + status = status_success; + } while (false); + + return status; +} + +hpm_stat_t otp_set_configurable_region(uint32_t start, uint32_t num_of_words) +{ + hpm_stat_t status = status_invalid_argument; + + do { + uint32_t max_fuse_idx = ARRAY_SIZE(HPM_OTP->SHADOW); + HPM_BREAK_IF((start >= max_fuse_idx) || (num_of_words > max_fuse_idx) || ((start + num_of_words) > max_fuse_idx)); + + HPM_OTP->REGION[3] = OTP_REGION_START_SET(start) + | OTP_REGION_STOP_SET(start + num_of_words); + + status = status_success; + } while (false); + + return status; +} + +hpm_stat_t otp_write_shadow_register(uint32_t addr, uint32_t val) +{ + hpm_stat_t status = status_invalid_argument; + do { + HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW)); + + uint32_t lock_reg_idx = (addr << 1) / 32; + uint32_t lock_reg_offset = (addr << 1) % 32; + uint32_t lock_mask = 3U << lock_reg_offset; + + OTP_Type *otp_base = HPM_OTP; + otp_lock_option_t lock_opt = (otp_lock_option_t) ((otp_base->SHADOW_LOCK[lock_reg_idx] & lock_mask) + >> lock_reg_offset); + + if (lock_opt != otp_no_lock) { + status = otp_write_disallowed; + break; + } + + otp_base->SHADOW[addr] = val; + + status = status_success; + } while (false); + + return status; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_otp_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_otp_drv.h new file mode 100644 index 00000000000..b61c805a1df --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_otp_drv.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_OTP_DRV_H +#define HPM_OTP_DRV_H + +/** + * @brief OTP APIs + * @defgroup otp_interface OTP driver APIs + * @{ + */ + +#include "hpm_common.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +/** + * @brief OTP region definitions + */ +typedef enum { + otp_region0_mask = 1U, /*!< Address range: [0, 7] */ + otp_region1_mask = 2U, /*!< Address range: [8, 15] */ + otp_region2_mask = 4U, /*!< Address range: [16, 127] */ + otp_region3_mask = 8U, /*!< Address range: user defined */ +} otp_region_t; + +/** + * @brief OTP lock options + */ +typedef enum { + otp_no_lock = 0, + otp_read_only = 1, + otp_permanent_no_lock = 2, + otp_disable_access = 3, + otp_lock_option_max = otp_disable_access, +} otp_lock_option_t; + +enum { + otp_write_disallowed = MAKE_STATUS(status_group_otp, 0), +}; + +/*********************************************************************************************************************** + * Prototypes + **********************************************************************************************************************/ +#ifdef __cpluscplus +extern "C" { +#endif + +/** + * @brief Initialize OTP controller + */ +void otp_init(void); + +/** + * @brief De-initialize OTP controller + */ +void otp_deinit(void); + +/** + * @brief Read the OTP word from shadow register + * @param [in] addr OTP word index + * @retval OTP word value + */ +uint32_t otp_read_from_shadow(uint32_t addr); + +/** + * @brief Read the specified OTP word from OTP IP bus + * @param [in] addr OTP word index + * @retval OTP word value + */ +uint32_t otp_read_from_ip(uint32_t addr); + +/** + * @brief Program a word to specified OTP field + * @param [in] addr OTP word index + * @param [in] src Pointer to the data to be programmed + * @param [in] num_of_words Number of words to be programmed, only 1 is allowed + * @return API execution status + */ +hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words); + +/** + * @brief Reload a OTP region + * @param [in] region OTP region option + * @return API execution status + */ +hpm_stat_t otp_reload(otp_region_t region); + +/** + * @brief Change the Software lock permission + * @param [in] addr OTP word index + * @param [in] lock_option OTP lcok option + * @return API execution status + */ +hpm_stat_t otp_lock_otp(uint32_t addr, otp_lock_option_t lock_option); + +/** + * @brief OTP lock shadow + * @param [in] addr OTP word index + * @param [in] lock_option OTP lock option + * @return API execution status + */ +hpm_stat_t otp_lock_shadow(uint32_t addr, otp_lock_option_t lock_option); + +/** + * @brief Set the configurable region range + * @param [in] start OTP word start index + * @param [in] num_of_words Number of words in configuration region + * @retval status_out_of_range Invalid range + * @retval status_success Operation is successful + */ +hpm_stat_t otp_set_configurable_region(uint32_t start, uint32_t num_of_words); + +/** + * @return Write data to OTP shadow register + * @param [in] addr OTP word index + * @param [in] val Data to be written + * @return API execution status + */ +hpm_stat_t otp_write_shadow_register(uint32_t addr, uint32_t val); + + +#ifdef __cpluscplus +} +#endif +/** + * @} + */ + + + + +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_pcfg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_pcfg_drv.h new file mode 100644 index 00000000000..1920823cebd --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_pcfg_drv.h @@ -0,0 +1,497 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PCFG_DRV_H +#define HPM_PCFG_DRV_H + +#include "hpm_common.h" +#include "hpm_pcfg_regs.h" + +/** + * + * @brief PCFG driver APIs + * @defgroup pcfg_interface PCFG driver APIs + * @ingroup io_interfaces + * @{ + */ +#define PCFG_CLOCK_GATE_MODE_ALWAYS_ON (0x3UL) +#define PCFG_CLOCK_GATE_MODE_ALWAYS_OFF (0x2UL) + +#define PCFG_PERIPH_KEEP_CLOCK_ON(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_ON << (p)) +#define PCFG_PERIPH_KEEP_CLOCK_OFF(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_OFF << (p)) + +/* @brief PCFG irc24m reference */ +typedef enum { + pcfg_irc24m_reference_32k = 0, + pcfg_irc24m_reference_24m_xtal = 1 +} pcfg_irc24m_reference_t; + +/* @brief PCFG dcdc current limit */ +typedef enum { + pcfg_dcdc_lp_current_limit_250ma = 0, + pcfg_dcdc_lp_current_limit_200ma = 1, +} pcfg_dcdc_lp_current_limit_t; + +/* @brief PCFG dcdc current hys */ +typedef enum { + pcfg_dcdc_current_hys_12_5mv = 0, + pcfg_dcdc_current_hys_25mv = 1, +} pcfg_dcdc_current_hys_t; + +/* @brief PCFG dcdc mode */ +typedef enum { + pcfg_dcdc_mode_off = 0, + pcfg_dcdc_mode_basic = 1, + pcfg_dcdc_mode_general = 3, + pcfg_dcdc_mode_expert = 7, +} pcfg_dcdc_mode_t; + +/* @brief PCFG pmc domain peripherals */ +typedef enum { + pcfg_pmc_periph_gpio = 6, + pcfg_pmc_periph_ioc = 8, + pcfg_pmc_periph_timer = 10, + pcfg_pmc_periph_wdog = 12, + pcfg_pmc_periph_uart = 14, +} pcfg_pmc_periph_t; + +/* @brief PCFG status */ +enum { + status_pcfg_ldo_out_of_range = MAKE_STATUS(status_group_pcfg, 1), +}; + +/* @brief PCFG irc24m config */ +typedef struct { + uint32_t freq_in_hz; + pcfg_irc24m_reference_t reference; + bool return_to_default_on_xtal_loss; + bool free_run; +} pcfg_irc24m_config_t; + + +#define PCFG_CLOCK_GATE_CONTROL_MASK(module, mode) \ + ((uint32_t) (mode) << ((module) << 1)) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief check if bandgap is trimmed or not + * + * @param[in] ptr base address + * + * @retval true if bandgap is trimmed + */ +static inline bool pcfg_bandgap_is_trimmed(PCFG_Type *ptr) +{ + return ptr->BANDGAP & PCFG_BANDGAP_VBG_TRIMMED_MASK; +} + +/** + * @brief bandgap reload trim value + * + * @param[in] ptr base address + */ +static inline void pcfg_bandgap_reload_trim(PCFG_Type *ptr) +{ + ptr->BANDGAP &= ~PCFG_BANDGAP_VBG_TRIMMED_MASK; +} + +/** + * @brief turn off LDO2P5 + * + * @param[in] ptr base address + */ +static inline void pcfg_ldo2p5_turn_off(PCFG_Type *ptr) +{ + ptr->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; +} + +/** + * @brief turn on LDO 2.5V + * + * @param[in] ptr base address + */ +static inline void pcfg_ldo2p5_turn_on(PCFG_Type *ptr) +{ + ptr->LDO2P5 |= PCFG_LDO2P5_ENABLE_MASK; +} + +/** + * @brief check if LDO 2.5V is stable + * + * @param[in] ptr base address + * + * @retval true if LDO2P5 is stable + */ +static inline bool pcfg_ldo2p5_is_stable(PCFG_Type *ptr) +{ + return PCFG_LDO2P5_READY_GET(ptr->LDO2P5); +} + +/* + * @brief check if DCDC is stable or not + * @param[in] ptr base address + * @retval true if DCDC is stable + */ +static inline bool pcfg_dcdc_is_stable(PCFG_Type *ptr) +{ + return PCFG_DCDC_MODE_READY_GET(ptr->DCDC_MODE); +} + +/* + * @brief set DCDC work mode + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_set_mode(PCFG_Type *ptr, uint8_t mode) +{ + ptr->DCDC_MODE = (ptr->DCDC_MODE & ~PCFG_DCDC_MODE_MODE_MASK) | PCFG_DCDC_MODE_MODE_SET(mode); +} + +/** + * @brief set low power current limit + * + * @param[in] ptr base address + * @param[in] limit current limit at low power mode + */ +static inline void pcfg_dcdc_set_lp_current_limit(PCFG_Type *ptr, pcfg_dcdc_lp_current_limit_t limit) +{ + ptr->DCDC_PROT = (ptr->DCDC_PROT & ~(PCFG_DCDC_PROT_ILIMIT_LP_MASK | PCFG_DCDC_PROT_OVERLOAD_LP_MASK)) + | PCFG_DCDC_PROT_ILIMIT_LP_SET(limit); +} + + +/** + * @brief check if power loss flag is set + * + * @param[in] ptr base address + * + * @retval true if power loss is set + */ +static inline bool pcfg_dcdc_is_power_loss(PCFG_Type *ptr) +{ + return PCFG_DCDC_PROT_POWER_LOSS_FLAG_GET(ptr->DCDC_PROT); +} + +/** + * @brief disable over voltage protection + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_disable_over_voltage_prot(PCFG_Type *ptr) +{ + ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK; +} + +/** + * @brief enable over voltage protection + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_ensable_over_voltage_prot(PCFG_Type *ptr) +{ + ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK; +} + +/** + * @brief checkover voltage flag + * + * @param[in] ptr base address + * @retval true if flag is set + */ +static inline bool pcfg_dcdc_is_over_voltage(PCFG_Type *ptr) +{ + return PCFG_DCDC_PROT_OVERVOLT_FLAG_GET(ptr->DCDC_PROT) & PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK; +} + +/** + * @brief disable current measurement + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_disable_measure_current(PCFG_Type *ptr) +{ + ptr->DCDC_CURRENT &= ~PCFG_DCDC_CURRENT_ESTI_EN_MASK; +} + +/** + * @brief enable current measurement + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_enable_measure_current(PCFG_Type *ptr) +{ + ptr->DCDC_CURRENT |= PCFG_DCDC_CURRENT_ESTI_EN_MASK; +} + +/** + * @brief check if measured current is valid + * + * @param[in] ptr base address + * + * @retval true if measured current is valid + */ +static inline bool pcfg_dcdc_is_measure_current_valid(PCFG_Type *ptr) +{ + return ptr->DCDC_CURRENT & PCFG_DCDC_CURRENT_VALID_MASK; +} + +/** + * @brief get DCDC start time in number of 24MHz clock cycles + * + * @param[in] ptr base address + * + * @retval dcdc start time in cycles + */ +static inline uint32_t pcfg_dcdc_get_start_time_in_cycle(PCFG_Type *ptr) +{ + return PCFG_DCDC_START_TIME_START_TIME_GET(ptr->DCDC_START_TIME); +} + +/** + * @brief get DCDC resume time in number of 24MHz clock cycles + * + * @param[in] ptr base address + * + * @retval dcdc resuem time in cycles + */ +static inline uint32_t pcfg_dcdc_get_resume_time_in_cycle(PCFG_Type *ptr) +{ + return PCFG_DCDC_RESUME_TIME_RESUME_TIME_GET(ptr->DCDC_RESUME_TIME); +} + +/** + * @brief set DCDC start time in 24MHz clock cycles + * + * @param[in] ptr base address + * @param[in] cycles start time in cycles + */ +static inline void pcfg_dcdc_set_start_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) +{ + ptr->DCDC_START_TIME = PCFG_DCDC_START_TIME_START_TIME_SET(cycles); +} + +/** + * @brief set DCDC resuem time in 24MHz clock cycles + * + * @param[in] ptr base address + * @param[in] cycles resume time in cycles + */ +static inline void pcfg_dcdc_set_resume_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) +{ + ptr->DCDC_RESUME_TIME = PCFG_DCDC_RESUME_TIME_RESUME_TIME_SET(cycles); +} + +/** + * @brief set dcdc current hysteres range + * + * @param[in] ptr base address + * @param[in] range current hysteres range + */ +static inline void pcfg_dcdc_set_current_hys_range(PCFG_Type *ptr, pcfg_dcdc_current_hys_t range) +{ + ptr->DCDC_MISC = (ptr->DCDC_MISC & (~PCFG_DCDC_MISC_OL_HYST_MASK)) | PCFG_DCDC_MISC_OL_HYST_SET(range); +} + +/** + * @brief disable power trap + * + * @param[in] ptr base address + */ +static inline void pcfg_disable_power_trap(PCFG_Type *ptr) +{ + ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_TRAP_MASK; +} + +/** + * @brief enable power trap + * + * @param[in] ptr base address + */ +static inline void pcfg_enable_power_trap(PCFG_Type *ptr) +{ + ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRAP_MASK; +} + +/** + * @brief check if power trap is triggered + * + * @param[in] ptr base address + * + * @retval true if power trap is triggered + */ +static inline bool pcfg_is_power_trap_triggered(PCFG_Type *ptr) +{ + return ptr->POWER_TRAP & PCFG_POWER_TRAP_TRIGGERED_MASK; +} + +/** + * @brief clear power trap trigger flag + * + * @param[in] ptr base address + */ +static inline void pcfg_clear_power_trap_trigger_flag(PCFG_Type *ptr) +{ + ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRIGGERED_MASK; +} + +/** + * @brief disable dcdc retention + * + * @param[in] ptr base address + */ +static inline void pcfg_disable_dcdc_retention(PCFG_Type *ptr) +{ + ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_RETENTION_MASK; +} + +/** + * @brief enable dcdc retention to retain soc sram data + * + * @param[in] ptr base address + */ +static inline void pcfg_enable_dcdc_retention(PCFG_Type *ptr) +{ + ptr->POWER_TRAP |= PCFG_POWER_TRAP_RETENTION_MASK; +} + +/** + * @brief clear wakeup cause flag + * + * @param[in] ptr base address + * @param[in] mask mask of flags to be cleared + */ +static inline void pcfg_clear_wakeup_cause(PCFG_Type *ptr, uint32_t mask) +{ + ptr->WAKE_CAUSE |= mask; +} + +/** + * @brief get wakeup cause + * + * @param[in] ptr base address + * + * @retval mask of wake cause + */ +static inline uint32_t pcfg_get_wakeup_cause(PCFG_Type *ptr) +{ + return ptr->WAKE_CAUSE; +} + +/** + * @brief enable wakeup source + * + * @param[in] ptr base address + * @param[in] mask wakeup source mask + */ +static inline void pcfg_enable_wakeup_source(PCFG_Type *ptr, uint32_t mask) +{ + ptr->WAKE_MASK &= ~mask; +} + +/** + * @brief disable wakeup source + * + * @param[in] ptr base address + * @param[in] mask source to be disabled as wakeup source + */ +static inline void pcfg_disable_wakeup_source(PCFG_Type *ptr, uint32_t mask) +{ + ptr->WAKE_MASK |= mask; +} + +/** + * @brief set clock gate mode in vpmc domain + * + * @param[in] ptr base address + * @param[in] mode clock gate mode mask + */ +static inline void pcfg_set_periph_clock_mode(PCFG_Type *ptr, uint32_t mode) +{ + ptr->SCG_CTRL = mode; +} + +/** + * @brief check if irc24m is trimmed + * + * @param[in] ptr base address + * + * @retval true if it is trimmed + */ +static inline bool pcfg_irc24m_is_trimmed(PCFG_Type *ptr) +{ + return ptr->RC24M & PCFG_RC24M_RC_TRIMMED_MASK; +} + +/** + * @brief reload irc24m trim value + * + * @param[in] ptr base address + */ +static inline void pcfg_irc24m_reload_trim(PCFG_Type *ptr) +{ + ptr->RC24M &= ~PCFG_RC24M_RC_TRIMMED_MASK; +} + +/** + * @brief config irc24m track + * + * @param[in] ptr base address + * @param[in] config config data + */ +void pcfg_irc24m_config_track(PCFG_Type *ptr, pcfg_irc24m_config_t *config); + +/* + * @brief set DCDC voltage at standby mode + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_dcdc_set_lpmode_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief set output voltage of LDO 2.5V in mV + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_ldo2p5_set_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief set DCDC voltage + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_dcdc_set_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief set output voltage of LDO 1V in mV + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_ldo1p1_set_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief get current DCDC current level in mA + * + * @param[in] ptr base address + * @retval Current level at mA + */ +uint16_t pcfg_dcdc_get_current_level(PCFG_Type *ptr); + + +#ifdef __cplusplus +} +#endif +/** + * @} + */ + +#endif /* HPM_PCFG_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_pcfg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_pcfg_regs.h new file mode 100644 index 00000000000..65c022090f6 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_pcfg_regs.h @@ -0,0 +1,834 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PCFG_H +#define HPM_PCFG_H + +typedef struct { + __RW uint32_t BANDGAP; /* 0x0: BANGGAP control */ + __RW uint32_t LDO1P1; /* 0x4: 1V LDO config */ + __RW uint32_t LDO2P5; /* 0x8: 2.5V LDO config */ + __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ + __RW uint32_t DCDC_MODE; /* 0x10: DCDC mode select */ + __RW uint32_t DCDC_LPMODE; /* 0x14: DCDC low power mode */ + __RW uint32_t DCDC_PROT; /* 0x18: DCDC protection */ + __RW uint32_t DCDC_CURRENT; /* 0x1C: DCDC current estimation */ + __RW uint32_t DCDC_ADVMODE; /* 0x20: DCDC advance setting */ + __RW uint32_t DCDC_ADVPARAM; /* 0x24: DCDC advance parameter */ + __RW uint32_t DCDC_MISC; /* 0x28: DCDC misc parameter */ + __RW uint32_t DCDC_DEBUG; /* 0x2C: DCDC Debug */ + __RW uint32_t DCDC_START_TIME; /* 0x30: DCDC ramp time */ + __RW uint32_t DCDC_RESUME_TIME; /* 0x34: DCDC resume time */ + __R uint8_t RESERVED1[8]; /* 0x38 - 0x3F: Reserved */ + __RW uint32_t POWER_TRAP; /* 0x40: SOC power trap */ + __RW uint32_t WAKE_CAUSE; /* 0x44: Wake up source */ + __RW uint32_t WAKE_MASK; /* 0x48: Wake up mask */ + __RW uint32_t SCG_CTRL; /* 0x4C: Clock gate control in PMIC */ + __R uint8_t RESERVED2[16]; /* 0x50 - 0x5F: Reserved */ + __RW uint32_t RC24M; /* 0x60: RC 24M config */ + __RW uint32_t RC24M_TRACK; /* 0x64: RC 24M track mode */ + __RW uint32_t TRACK_TARGET; /* 0x68: RC 24M track target */ + __R uint32_t STATUS; /* 0x6C: RC 24M track status */ +} PCFG_Type; + + +/* Bitfield definition for register: BANDGAP */ +/* + * VBG_TRIMMED (RW) + * + * Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value + * 0: bandgap is not trimmed + * 1: bandgap is trimmed + */ +#define PCFG_BANDGAP_VBG_TRIMMED_MASK (0x80000000UL) +#define PCFG_BANDGAP_VBG_TRIMMED_SHIFT (31U) +#define PCFG_BANDGAP_VBG_TRIMMED_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_TRIMMED_SHIFT) & PCFG_BANDGAP_VBG_TRIMMED_MASK) +#define PCFG_BANDGAP_VBG_TRIMMED_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_TRIMMED_MASK) >> PCFG_BANDGAP_VBG_TRIMMED_SHIFT) + +/* + * VBG_1P0_TRIM (RW) + * + * Banggap 1.0V output trim value + */ +#define PCFG_BANDGAP_VBG_1P0_TRIM_MASK (0x1F0000UL) +#define PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT (16U) +#define PCFG_BANDGAP_VBG_1P0_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT) & PCFG_BANDGAP_VBG_1P0_TRIM_MASK) +#define PCFG_BANDGAP_VBG_1P0_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_1P0_TRIM_MASK) >> PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT) + +/* + * VBG_P65_TRIM (RW) + * + * Banggap 1.0V output trim value + */ +#define PCFG_BANDGAP_VBG_P65_TRIM_MASK (0x1F00U) +#define PCFG_BANDGAP_VBG_P65_TRIM_SHIFT (8U) +#define PCFG_BANDGAP_VBG_P65_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_P65_TRIM_SHIFT) & PCFG_BANDGAP_VBG_P65_TRIM_MASK) +#define PCFG_BANDGAP_VBG_P65_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_P65_TRIM_MASK) >> PCFG_BANDGAP_VBG_P65_TRIM_SHIFT) + +/* + * VBG_P50_TRIM (RW) + * + * Banggap 1.0V output trim value + */ +#define PCFG_BANDGAP_VBG_P50_TRIM_MASK (0x1FU) +#define PCFG_BANDGAP_VBG_P50_TRIM_SHIFT (0U) +#define PCFG_BANDGAP_VBG_P50_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) & PCFG_BANDGAP_VBG_P50_TRIM_MASK) +#define PCFG_BANDGAP_VBG_P50_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_P50_TRIM_MASK) >> PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) + +/* Bitfield definition for register: LDO1P1 */ +/* + * VOLT (RW) + * + * LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. + * 700: 700mV + * 720: 720mV + * . . . + * 1320:1320mV + */ +#define PCFG_LDO1P1_VOLT_MASK (0xFFFU) +#define PCFG_LDO1P1_VOLT_SHIFT (0U) +#define PCFG_LDO1P1_VOLT_SET(x) (((uint32_t)(x) << PCFG_LDO1P1_VOLT_SHIFT) & PCFG_LDO1P1_VOLT_MASK) +#define PCFG_LDO1P1_VOLT_GET(x) (((uint32_t)(x) & PCFG_LDO1P1_VOLT_MASK) >> PCFG_LDO1P1_VOLT_SHIFT) + +/* Bitfield definition for register: LDO2P5 */ +/* + * READY (RO) + * + * Ready flag, will set 1ms after enabled or voltage change + * 0: LDO is not ready for use + * 1: LDO is ready + */ +#define PCFG_LDO2P5_READY_MASK (0x10000000UL) +#define PCFG_LDO2P5_READY_SHIFT (28U) +#define PCFG_LDO2P5_READY_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_READY_MASK) >> PCFG_LDO2P5_READY_SHIFT) + +/* + * ENABLE (RW) + * + * LDO enable + * 0: turn off LDO + * 1: turn on LDO + */ +#define PCFG_LDO2P5_ENABLE_MASK (0x10000UL) +#define PCFG_LDO2P5_ENABLE_SHIFT (16U) +#define PCFG_LDO2P5_ENABLE_SET(x) (((uint32_t)(x) << PCFG_LDO2P5_ENABLE_SHIFT) & PCFG_LDO2P5_ENABLE_MASK) +#define PCFG_LDO2P5_ENABLE_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_ENABLE_MASK) >> PCFG_LDO2P5_ENABLE_SHIFT) + +/* + * VOLT (RW) + * + * LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. + * 2125: 2125mV + * 2150: 2150mV + * . . . + * 2900:2900mV + */ +#define PCFG_LDO2P5_VOLT_MASK (0xFFFU) +#define PCFG_LDO2P5_VOLT_SHIFT (0U) +#define PCFG_LDO2P5_VOLT_SET(x) (((uint32_t)(x) << PCFG_LDO2P5_VOLT_SHIFT) & PCFG_LDO2P5_VOLT_MASK) +#define PCFG_LDO2P5_VOLT_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_VOLT_MASK) >> PCFG_LDO2P5_VOLT_SHIFT) + +/* Bitfield definition for register: DCDC_MODE */ +/* + * READY (RO) + * + * Ready flag + * 0: DCDC is applying new change + * 1: DCDC is ready + */ +#define PCFG_DCDC_MODE_READY_MASK (0x10000000UL) +#define PCFG_DCDC_MODE_READY_SHIFT (28U) +#define PCFG_DCDC_MODE_READY_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_READY_MASK) >> PCFG_DCDC_MODE_READY_SHIFT) + +/* + * MODE (RW) + * + * DCDC work mode + * XX0: turn off + * 001: basic mode + * 011: generic mode + * 101: automatic mode + * 111: expert mode + */ +#define PCFG_DCDC_MODE_MODE_MASK (0x70000UL) +#define PCFG_DCDC_MODE_MODE_SHIFT (16U) +#define PCFG_DCDC_MODE_MODE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MODE_MODE_SHIFT) & PCFG_DCDC_MODE_MODE_MASK) +#define PCFG_DCDC_MODE_MODE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_MODE_MASK) >> PCFG_DCDC_MODE_MODE_SHIFT) + +/* + * VOLT (RW) + * + * DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. + * 600: 600mV + * 625: 625mV + * . . . + * 1375:1375mV + */ +#define PCFG_DCDC_MODE_VOLT_MASK (0xFFFU) +#define PCFG_DCDC_MODE_VOLT_SHIFT (0U) +#define PCFG_DCDC_MODE_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDC_MODE_VOLT_SHIFT) & PCFG_DCDC_MODE_VOLT_MASK) +#define PCFG_DCDC_MODE_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_VOLT_MASK) >> PCFG_DCDC_MODE_VOLT_SHIFT) + +/* Bitfield definition for register: DCDC_LPMODE */ +/* + * STBY_VOLT (RW) + * + * DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. + * 600: 600mV + * 625: 625mV + * . . . + * 1375:1375mV + */ +#define PCFG_DCDC_LPMODE_STBY_VOLT_MASK (0xFFFU) +#define PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT (0U) +#define PCFG_DCDC_LPMODE_STBY_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT) & PCFG_DCDC_LPMODE_STBY_VOLT_MASK) +#define PCFG_DCDC_LPMODE_STBY_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDC_LPMODE_STBY_VOLT_MASK) >> PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT) + +/* Bitfield definition for register: DCDC_PROT */ +/* + * ILIMIT_LP (RW) + * + * over current setting for low power mode + * 0:250mA + * 1:200mA + */ +#define PCFG_DCDC_PROT_ILIMIT_LP_MASK (0x10000000UL) +#define PCFG_DCDC_PROT_ILIMIT_LP_SHIFT (28U) +#define PCFG_DCDC_PROT_ILIMIT_LP_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) +#define PCFG_DCDC_PROT_ILIMIT_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) >> PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) + +/* + * OVERLOAD_LP (RO) + * + * over current in low power mode + * 0: current is below setting + * 1: overcurrent happened in low power mode + */ +#define PCFG_DCDC_PROT_OVERLOAD_LP_MASK (0x1000000UL) +#define PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT (24U) +#define PCFG_DCDC_PROT_OVERLOAD_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERLOAD_LP_MASK) >> PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT) + +/* + * POWER_LOSS_FLAG (RO) + * + * power loss + * 0: input power is good + * 1: input power is too low + */ +#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_MASK (0x10000UL) +#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_SHIFT (16U) +#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_POWER_LOSS_FLAG_MASK) >> PCFG_DCDC_PROT_POWER_LOSS_FLAG_SHIFT) + +/* + * DISABLE_OVERVOLTAGE (RW) + * + * output over voltage protection + * 0: protection enabled, DCDC will shut down is output voltage is unexpected high + * 1: protection disabled, DCDC continue to adjust output voltage + */ +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK (0x8000U) +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT (15U) +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT) & PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK) +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK) >> PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT) + +/* + * OVERVOLT_FLAG (RO) + * + * output over voltage flag + * 0: output is normal + * 1: output is unexpected high + */ +#define PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK (0x100U) +#define PCFG_DCDC_PROT_OVERVOLT_FLAG_SHIFT (8U) +#define PCFG_DCDC_PROT_OVERVOLT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK) >> PCFG_DCDC_PROT_OVERVOLT_FLAG_SHIFT) + +/* + * DISABLE_SHORT (RW) + * + * disable output short circuit protection + * 0: short circuits protection enabled, DCDC shut down if short circuit on output detected + * 1: short circuit protection disabled + */ +#define PCFG_DCDC_PROT_DISABLE_SHORT_MASK (0x80U) +#define PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT (7U) +#define PCFG_DCDC_PROT_DISABLE_SHORT_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT) & PCFG_DCDC_PROT_DISABLE_SHORT_MASK) +#define PCFG_DCDC_PROT_DISABLE_SHORT_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_SHORT_MASK) >> PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT) + +/* + * SHORT_CURRENT (RW) + * + * short circuit current setting + * 0: 2.0A, + * 1: 1.3A + */ +#define PCFG_DCDC_PROT_SHORT_CURRENT_MASK (0x10U) +#define PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT (4U) +#define PCFG_DCDC_PROT_SHORT_CURRENT_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT) & PCFG_DCDC_PROT_SHORT_CURRENT_MASK) +#define PCFG_DCDC_PROT_SHORT_CURRENT_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_SHORT_CURRENT_MASK) >> PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT) + +/* + * SHORT_FLAG (RO) + * + * short circuit flag + * 0: current is within limit + * 1: short circuits detected + */ +#define PCFG_DCDC_PROT_SHORT_FLAG_MASK (0x1U) +#define PCFG_DCDC_PROT_SHORT_FLAG_SHIFT (0U) +#define PCFG_DCDC_PROT_SHORT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_SHORT_FLAG_MASK) >> PCFG_DCDC_PROT_SHORT_FLAG_SHIFT) + +/* Bitfield definition for register: DCDC_CURRENT */ +/* + * ESTI_EN (RW) + * + * enable current measure + */ +#define PCFG_DCDC_CURRENT_ESTI_EN_MASK (0x8000U) +#define PCFG_DCDC_CURRENT_ESTI_EN_SHIFT (15U) +#define PCFG_DCDC_CURRENT_ESTI_EN_SET(x) (((uint32_t)(x) << PCFG_DCDC_CURRENT_ESTI_EN_SHIFT) & PCFG_DCDC_CURRENT_ESTI_EN_MASK) +#define PCFG_DCDC_CURRENT_ESTI_EN_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_ESTI_EN_MASK) >> PCFG_DCDC_CURRENT_ESTI_EN_SHIFT) + +/* + * VALID (RO) + * + * Current level valid + * 0: data is invalid + * 1: data is valid + */ +#define PCFG_DCDC_CURRENT_VALID_MASK (0x100U) +#define PCFG_DCDC_CURRENT_VALID_SHIFT (8U) +#define PCFG_DCDC_CURRENT_VALID_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_VALID_MASK) >> PCFG_DCDC_CURRENT_VALID_SHIFT) + +/* + * LEVEL (RO) + * + * DCDC current level, current level is num * 50mA + */ +#define PCFG_DCDC_CURRENT_LEVEL_MASK (0x1FU) +#define PCFG_DCDC_CURRENT_LEVEL_SHIFT (0U) +#define PCFG_DCDC_CURRENT_LEVEL_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_LEVEL_MASK) >> PCFG_DCDC_CURRENT_LEVEL_SHIFT) + +/* Bitfield definition for register: DCDC_ADVMODE */ +/* + * EN_RCSCALE (RW) + * + * Enable RC scale + */ +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK (0x7000000UL) +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT (24U) +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT) & PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK) +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK) >> PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT) + +/* + * DC_C (RW) + * + * Loop C number + */ +#define PCFG_DCDC_ADVMODE_DC_C_MASK (0x300000UL) +#define PCFG_DCDC_ADVMODE_DC_C_SHIFT (20U) +#define PCFG_DCDC_ADVMODE_DC_C_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_DC_C_SHIFT) & PCFG_DCDC_ADVMODE_DC_C_MASK) +#define PCFG_DCDC_ADVMODE_DC_C_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_DC_C_MASK) >> PCFG_DCDC_ADVMODE_DC_C_SHIFT) + +/* + * DC_R (RW) + * + * Loop R number + */ +#define PCFG_DCDC_ADVMODE_DC_R_MASK (0xF0000UL) +#define PCFG_DCDC_ADVMODE_DC_R_SHIFT (16U) +#define PCFG_DCDC_ADVMODE_DC_R_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_DC_R_SHIFT) & PCFG_DCDC_ADVMODE_DC_R_MASK) +#define PCFG_DCDC_ADVMODE_DC_R_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_DC_R_MASK) >> PCFG_DCDC_ADVMODE_DC_R_SHIFT) + +/* + * EN_FF_DET (RW) + * + * enable feed forward detect + * 0: feed forward detect is disabled + * 1: feed forward detect is enabled + */ +#define PCFG_DCDC_ADVMODE_EN_FF_DET_MASK (0x40U) +#define PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT (6U) +#define PCFG_DCDC_ADVMODE_EN_FF_DET_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT) & PCFG_DCDC_ADVMODE_EN_FF_DET_MASK) +#define PCFG_DCDC_ADVMODE_EN_FF_DET_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_FF_DET_MASK) >> PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT) + +/* + * EN_FF_LOOP (RW) + * + * enable feed forward loop + * 0: feed forward loop is disabled + * 1: feed forward loop is enabled + */ +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK (0x20U) +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT (5U) +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) >> PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) + +/* + * EN_AUTOLP (RW) + * + * enable auto enter low power mode + * 0: do not enter low power mode + * 1: enter low power mode if current is detected low + */ +#define PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK (0x10U) +#define PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT (4U) +#define PCFG_DCDC_ADVMODE_EN_AUTOLP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT) & PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK) +#define PCFG_DCDC_ADVMODE_EN_AUTOLP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK) >> PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT) + +/* + * EN_DCM_EXIT (RW) + * + * avoid over voltage + * 0: stay in DCM mode when voltage excess + * 1: change to CCM mode when voltage excess + */ +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK (0x8U) +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT (3U) +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT) & PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK) +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK) >> PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT) + +/* + * EN_SKIP (RW) + * + * enable skip on narrow pulse + * 0: do not skip narrow pulse + * 1: skip narrow pulse + */ +#define PCFG_DCDC_ADVMODE_EN_SKIP_MASK (0x4U) +#define PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT (2U) +#define PCFG_DCDC_ADVMODE_EN_SKIP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT) & PCFG_DCDC_ADVMODE_EN_SKIP_MASK) +#define PCFG_DCDC_ADVMODE_EN_SKIP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_SKIP_MASK) >> PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT) + +/* + * EN_IDLE (RW) + * + * enable skip when voltage is higher than threshold + * 0: do not skip + * 1: skip if voltage is excess + */ +#define PCFG_DCDC_ADVMODE_EN_IDLE_MASK (0x2U) +#define PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT (1U) +#define PCFG_DCDC_ADVMODE_EN_IDLE_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT) & PCFG_DCDC_ADVMODE_EN_IDLE_MASK) +#define PCFG_DCDC_ADVMODE_EN_IDLE_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_IDLE_MASK) >> PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT) + +/* + * EN_DCM (RW) + * + * DCM mode + * 0: CCM mode + * 1: DCM mode + */ +#define PCFG_DCDC_ADVMODE_EN_DCM_MASK (0x1U) +#define PCFG_DCDC_ADVMODE_EN_DCM_SHIFT (0U) +#define PCFG_DCDC_ADVMODE_EN_DCM_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_DCM_SHIFT) & PCFG_DCDC_ADVMODE_EN_DCM_MASK) +#define PCFG_DCDC_ADVMODE_EN_DCM_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_DCM_MASK) >> PCFG_DCDC_ADVMODE_EN_DCM_SHIFT) + +/* Bitfield definition for register: DCDC_ADVPARAM */ +/* + * MIN_DUT (RW) + * + * minimum duty cycle + */ +#define PCFG_DCDC_ADVPARAM_MIN_DUT_MASK (0x7F00U) +#define PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT (8U) +#define PCFG_DCDC_ADVPARAM_MIN_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT) & PCFG_DCDC_ADVPARAM_MIN_DUT_MASK) +#define PCFG_DCDC_ADVPARAM_MIN_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVPARAM_MIN_DUT_MASK) >> PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT) + +/* + * MAX_DUT (RW) + * + * maximum duty cycle + */ +#define PCFG_DCDC_ADVPARAM_MAX_DUT_MASK (0x7FU) +#define PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT (0U) +#define PCFG_DCDC_ADVPARAM_MAX_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT) & PCFG_DCDC_ADVPARAM_MAX_DUT_MASK) +#define PCFG_DCDC_ADVPARAM_MAX_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVPARAM_MAX_DUT_MASK) >> PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT) + +/* Bitfield definition for register: DCDC_MISC */ +/* + * EN_HYST (RW) + * + * hysteres enable + */ +#define PCFG_DCDC_MISC_EN_HYST_MASK (0x10000000UL) +#define PCFG_DCDC_MISC_EN_HYST_SHIFT (28U) +#define PCFG_DCDC_MISC_EN_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_EN_HYST_SHIFT) & PCFG_DCDC_MISC_EN_HYST_MASK) +#define PCFG_DCDC_MISC_EN_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_EN_HYST_MASK) >> PCFG_DCDC_MISC_EN_HYST_SHIFT) + +/* + * HYST_SIGN (RW) + * + * hysteres sign + */ +#define PCFG_DCDC_MISC_HYST_SIGN_MASK (0x2000000UL) +#define PCFG_DCDC_MISC_HYST_SIGN_SHIFT (25U) +#define PCFG_DCDC_MISC_HYST_SIGN_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_HYST_SIGN_SHIFT) & PCFG_DCDC_MISC_HYST_SIGN_MASK) +#define PCFG_DCDC_MISC_HYST_SIGN_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_HYST_SIGN_MASK) >> PCFG_DCDC_MISC_HYST_SIGN_SHIFT) + +/* + * HYST_THRS (RW) + * + * hysteres threshold + */ +#define PCFG_DCDC_MISC_HYST_THRS_MASK (0x1000000UL) +#define PCFG_DCDC_MISC_HYST_THRS_SHIFT (24U) +#define PCFG_DCDC_MISC_HYST_THRS_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_HYST_THRS_SHIFT) & PCFG_DCDC_MISC_HYST_THRS_MASK) +#define PCFG_DCDC_MISC_HYST_THRS_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_HYST_THRS_MASK) >> PCFG_DCDC_MISC_HYST_THRS_SHIFT) + +/* + * RC_SCALE (RW) + * + * Loop RC scale threshold + */ +#define PCFG_DCDC_MISC_RC_SCALE_MASK (0x100000UL) +#define PCFG_DCDC_MISC_RC_SCALE_SHIFT (20U) +#define PCFG_DCDC_MISC_RC_SCALE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_RC_SCALE_SHIFT) & PCFG_DCDC_MISC_RC_SCALE_MASK) +#define PCFG_DCDC_MISC_RC_SCALE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_RC_SCALE_MASK) >> PCFG_DCDC_MISC_RC_SCALE_SHIFT) + +/* + * DC_FF (RW) + * + * Loop feed forward number + */ +#define PCFG_DCDC_MISC_DC_FF_MASK (0x70000UL) +#define PCFG_DCDC_MISC_DC_FF_SHIFT (16U) +#define PCFG_DCDC_MISC_DC_FF_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_DC_FF_SHIFT) & PCFG_DCDC_MISC_DC_FF_MASK) +#define PCFG_DCDC_MISC_DC_FF_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_DC_FF_MASK) >> PCFG_DCDC_MISC_DC_FF_SHIFT) + +/* + * OL_THRE (RW) + * + * overload for threshold for lod power mode + */ +#define PCFG_DCDC_MISC_OL_THRE_MASK (0x300U) +#define PCFG_DCDC_MISC_OL_THRE_SHIFT (8U) +#define PCFG_DCDC_MISC_OL_THRE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_OL_THRE_SHIFT) & PCFG_DCDC_MISC_OL_THRE_MASK) +#define PCFG_DCDC_MISC_OL_THRE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_OL_THRE_MASK) >> PCFG_DCDC_MISC_OL_THRE_SHIFT) + +/* + * OL_HYST (RW) + * + * current hysteres range + * 0: 12.5mV + * 1: 25mV + */ +#define PCFG_DCDC_MISC_OL_HYST_MASK (0x10U) +#define PCFG_DCDC_MISC_OL_HYST_SHIFT (4U) +#define PCFG_DCDC_MISC_OL_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_OL_HYST_SHIFT) & PCFG_DCDC_MISC_OL_HYST_MASK) +#define PCFG_DCDC_MISC_OL_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_OL_HYST_MASK) >> PCFG_DCDC_MISC_OL_HYST_SHIFT) + +/* + * DELAY (RW) + * + * enable delay + * 0: delay disabled, + * 1: delay enabled + */ +#define PCFG_DCDC_MISC_DELAY_MASK (0x4U) +#define PCFG_DCDC_MISC_DELAY_SHIFT (2U) +#define PCFG_DCDC_MISC_DELAY_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_DELAY_SHIFT) & PCFG_DCDC_MISC_DELAY_MASK) +#define PCFG_DCDC_MISC_DELAY_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_DELAY_MASK) >> PCFG_DCDC_MISC_DELAY_SHIFT) + +/* + * CLK_SEL (RW) + * + * clock selection + * 0: select DCDC internal oscillator + * 1: select RC24M oscillator + */ +#define PCFG_DCDC_MISC_CLK_SEL_MASK (0x2U) +#define PCFG_DCDC_MISC_CLK_SEL_SHIFT (1U) +#define PCFG_DCDC_MISC_CLK_SEL_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_CLK_SEL_SHIFT) & PCFG_DCDC_MISC_CLK_SEL_MASK) +#define PCFG_DCDC_MISC_CLK_SEL_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_CLK_SEL_MASK) >> PCFG_DCDC_MISC_CLK_SEL_SHIFT) + +/* + * EN_STEP (RW) + * + * enable stepping in voltage change + * 0: stepping disabled, + * 1: steping enabled + */ +#define PCFG_DCDC_MISC_EN_STEP_MASK (0x1U) +#define PCFG_DCDC_MISC_EN_STEP_SHIFT (0U) +#define PCFG_DCDC_MISC_EN_STEP_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_EN_STEP_SHIFT) & PCFG_DCDC_MISC_EN_STEP_MASK) +#define PCFG_DCDC_MISC_EN_STEP_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_EN_STEP_MASK) >> PCFG_DCDC_MISC_EN_STEP_SHIFT) + +/* Bitfield definition for register: DCDC_DEBUG */ +/* + * UPDATE_TIME (RW) + * + * DCDC voltage change time in 24M clock cycles, default value is 1mS + */ +#define PCFG_DCDC_DEBUG_UPDATE_TIME_MASK (0xFFFFFUL) +#define PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT (0U) +#define PCFG_DCDC_DEBUG_UPDATE_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT) & PCFG_DCDC_DEBUG_UPDATE_TIME_MASK) +#define PCFG_DCDC_DEBUG_UPDATE_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_DEBUG_UPDATE_TIME_MASK) >> PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT) + +/* Bitfield definition for register: DCDC_START_TIME */ +/* + * START_TIME (RW) + * + * Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS + */ +#define PCFG_DCDC_START_TIME_START_TIME_MASK (0xFFFFFUL) +#define PCFG_DCDC_START_TIME_START_TIME_SHIFT (0U) +#define PCFG_DCDC_START_TIME_START_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_START_TIME_START_TIME_SHIFT) & PCFG_DCDC_START_TIME_START_TIME_MASK) +#define PCFG_DCDC_START_TIME_START_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_START_TIME_START_TIME_MASK) >> PCFG_DCDC_START_TIME_START_TIME_SHIFT) + +/* Bitfield definition for register: DCDC_RESUME_TIME */ +/* + * RESUME_TIME (RW) + * + * Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS + */ +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK (0xFFFFFUL) +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT (0U) +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT) & PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK) +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK) >> PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT) + +/* Bitfield definition for register: POWER_TRAP */ +/* + * TRIGGERED (RW) + * + * Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. + * 0: low power trap is not triggered + * 1: low power trap triggered + */ +#define PCFG_POWER_TRAP_TRIGGERED_MASK (0x80000000UL) +#define PCFG_POWER_TRAP_TRIGGERED_SHIFT (31U) +#define PCFG_POWER_TRAP_TRIGGERED_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_TRIGGERED_SHIFT) & PCFG_POWER_TRAP_TRIGGERED_MASK) +#define PCFG_POWER_TRAP_TRIGGERED_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_TRIGGERED_MASK) >> PCFG_POWER_TRAP_TRIGGERED_SHIFT) + +/* + * RETENTION (RW) + * + * DCDC enter standby mode, which will reduce voltage for memory content retention + * 0: Shutdown DCDC + * 1: reduce DCDC voltage + */ +#define PCFG_POWER_TRAP_RETENTION_MASK (0x10000UL) +#define PCFG_POWER_TRAP_RETENTION_SHIFT (16U) +#define PCFG_POWER_TRAP_RETENTION_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_RETENTION_SHIFT) & PCFG_POWER_TRAP_RETENTION_MASK) +#define PCFG_POWER_TRAP_RETENTION_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_RETENTION_MASK) >> PCFG_POWER_TRAP_RETENTION_SHIFT) + +/* + * TRAP (RW) + * + * Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered + * 0: trap not enabled, pmic side low power function disabled + * 1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. + */ +#define PCFG_POWER_TRAP_TRAP_MASK (0x1U) +#define PCFG_POWER_TRAP_TRAP_SHIFT (0U) +#define PCFG_POWER_TRAP_TRAP_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_TRAP_SHIFT) & PCFG_POWER_TRAP_TRAP_MASK) +#define PCFG_POWER_TRAP_TRAP_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_TRAP_MASK) >> PCFG_POWER_TRAP_TRAP_SHIFT) + +/* Bitfield definition for register: WAKE_CAUSE */ +/* + * CAUSE (RW) + * + * wake up cause, each bit represents one wake up source, write 1 to clear the register bit + * 0: wake up source is not active during last wakeup + * 1: wake up source is active furing last wakeup + * bit 0: pmic_enable + * bit 7: UART interrupt + * bit 8: TMR interrupt + * bit 9: WDG interrupt + * bit10: GPIO in PMIC interrupt + * bit31: pin wakeup + */ +#define PCFG_WAKE_CAUSE_CAUSE_MASK (0xFFFFFFFFUL) +#define PCFG_WAKE_CAUSE_CAUSE_SHIFT (0U) +#define PCFG_WAKE_CAUSE_CAUSE_SET(x) (((uint32_t)(x) << PCFG_WAKE_CAUSE_CAUSE_SHIFT) & PCFG_WAKE_CAUSE_CAUSE_MASK) +#define PCFG_WAKE_CAUSE_CAUSE_GET(x) (((uint32_t)(x) & PCFG_WAKE_CAUSE_CAUSE_MASK) >> PCFG_WAKE_CAUSE_CAUSE_SHIFT) + +/* Bitfield definition for register: WAKE_MASK */ +/* + * MASK (RW) + * + * mask for wake up sources, each bit represents one wakeup source + * 0: allow source to wake up system + * 1: disallow source to wakeup system + * bit 0: pmic_enable + * bit 7: UART interrupt + * bit 8: TMR interrupt + * bit 9: WDG interrupt + * bit10: GPIO in PMIC interrupt + * bit31: pin wakeup + */ +#define PCFG_WAKE_MASK_MASK_MASK (0xFFFFFFFFUL) +#define PCFG_WAKE_MASK_MASK_SHIFT (0U) +#define PCFG_WAKE_MASK_MASK_SET(x) (((uint32_t)(x) << PCFG_WAKE_MASK_MASK_SHIFT) & PCFG_WAKE_MASK_MASK_MASK) +#define PCFG_WAKE_MASK_MASK_GET(x) (((uint32_t)(x) & PCFG_WAKE_MASK_MASK_MASK) >> PCFG_WAKE_MASK_MASK_SHIFT) + +/* Bitfield definition for register: SCG_CTRL */ +/* + * SCG (RW) + * + * control whether clock being gated during PMIC low power flow, 2 bits for each peripheral + * 00,01: reserved + * 10: clock is always off + * 11: clock is always on + * bit6-7:gpio + * bit8-9:ioc + * bit10-11: timer + * bit12-13:wdog + * bit14-15:uart + */ +#define PCFG_SCG_CTRL_SCG_MASK (0xFFFFFFFFUL) +#define PCFG_SCG_CTRL_SCG_SHIFT (0U) +#define PCFG_SCG_CTRL_SCG_SET(x) (((uint32_t)(x) << PCFG_SCG_CTRL_SCG_SHIFT) & PCFG_SCG_CTRL_SCG_MASK) +#define PCFG_SCG_CTRL_SCG_GET(x) (((uint32_t)(x) & PCFG_SCG_CTRL_SCG_MASK) >> PCFG_SCG_CTRL_SCG_SHIFT) + +/* Bitfield definition for register: RC24M */ +/* + * RC_TRIMMED (RW) + * + * RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value + * 0: RC is not trimmed + * 1: RC is trimmed + */ +#define PCFG_RC24M_RC_TRIMMED_MASK (0x80000000UL) +#define PCFG_RC24M_RC_TRIMMED_SHIFT (31U) +#define PCFG_RC24M_RC_TRIMMED_SET(x) (((uint32_t)(x) << PCFG_RC24M_RC_TRIMMED_SHIFT) & PCFG_RC24M_RC_TRIMMED_MASK) +#define PCFG_RC24M_RC_TRIMMED_GET(x) (((uint32_t)(x) & PCFG_RC24M_RC_TRIMMED_MASK) >> PCFG_RC24M_RC_TRIMMED_SHIFT) + +/* + * TRIM_C (RW) + * + * Coarse trim for RC24M, bigger value means faster + */ +#define PCFG_RC24M_TRIM_C_MASK (0x700U) +#define PCFG_RC24M_TRIM_C_SHIFT (8U) +#define PCFG_RC24M_TRIM_C_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRIM_C_SHIFT) & PCFG_RC24M_TRIM_C_MASK) +#define PCFG_RC24M_TRIM_C_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRIM_C_MASK) >> PCFG_RC24M_TRIM_C_SHIFT) + +/* + * TRIM_F (RW) + * + * Fine trim for RC24M, bigger value means faster + */ +#define PCFG_RC24M_TRIM_F_MASK (0x1FU) +#define PCFG_RC24M_TRIM_F_SHIFT (0U) +#define PCFG_RC24M_TRIM_F_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRIM_F_SHIFT) & PCFG_RC24M_TRIM_F_MASK) +#define PCFG_RC24M_TRIM_F_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRIM_F_MASK) >> PCFG_RC24M_TRIM_F_SHIFT) + +/* Bitfield definition for register: RC24M_TRACK */ +/* + * SEL24M (RW) + * + * Select track reference + * 0: select 32K as reference + * 1: select 24M XTAL as reference + */ +#define PCFG_RC24M_TRACK_SEL24M_MASK (0x10000UL) +#define PCFG_RC24M_TRACK_SEL24M_SHIFT (16U) +#define PCFG_RC24M_TRACK_SEL24M_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_SEL24M_SHIFT) & PCFG_RC24M_TRACK_SEL24M_MASK) +#define PCFG_RC24M_TRACK_SEL24M_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_SEL24M_MASK) >> PCFG_RC24M_TRACK_SEL24M_SHIFT) + +/* + * RETURN (RW) + * + * Retrun default value when XTAL loss + * 0: remain last tracking value + * 1: switch to default value + */ +#define PCFG_RC24M_TRACK_RETURN_MASK (0x10U) +#define PCFG_RC24M_TRACK_RETURN_SHIFT (4U) +#define PCFG_RC24M_TRACK_RETURN_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_RETURN_SHIFT) & PCFG_RC24M_TRACK_RETURN_MASK) +#define PCFG_RC24M_TRACK_RETURN_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_RETURN_MASK) >> PCFG_RC24M_TRACK_RETURN_SHIFT) + +/* + * TRACK (RW) + * + * track mode + * 0: RC24M free running + * 1: track RC24M to external XTAL + */ +#define PCFG_RC24M_TRACK_TRACK_MASK (0x1U) +#define PCFG_RC24M_TRACK_TRACK_SHIFT (0U) +#define PCFG_RC24M_TRACK_TRACK_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_TRACK_SHIFT) & PCFG_RC24M_TRACK_TRACK_MASK) +#define PCFG_RC24M_TRACK_TRACK_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_TRACK_MASK) >> PCFG_RC24M_TRACK_TRACK_SHIFT) + +/* Bitfield definition for register: TRACK_TARGET */ +/* + * PRE_DIV (RW) + * + * Divider for reference source + */ +#define PCFG_TRACK_TARGET_PRE_DIV_MASK (0xFFFF0000UL) +#define PCFG_TRACK_TARGET_PRE_DIV_SHIFT (16U) +#define PCFG_TRACK_TARGET_PRE_DIV_SET(x) (((uint32_t)(x) << PCFG_TRACK_TARGET_PRE_DIV_SHIFT) & PCFG_TRACK_TARGET_PRE_DIV_MASK) +#define PCFG_TRACK_TARGET_PRE_DIV_GET(x) (((uint32_t)(x) & PCFG_TRACK_TARGET_PRE_DIV_MASK) >> PCFG_TRACK_TARGET_PRE_DIV_SHIFT) + +/* + * TARGET (RW) + * + * Target frequency multiplier of divided source + */ +#define PCFG_TRACK_TARGET_TARGET_MASK (0xFFFFU) +#define PCFG_TRACK_TARGET_TARGET_SHIFT (0U) +#define PCFG_TRACK_TARGET_TARGET_SET(x) (((uint32_t)(x) << PCFG_TRACK_TARGET_TARGET_SHIFT) & PCFG_TRACK_TARGET_TARGET_MASK) +#define PCFG_TRACK_TARGET_TARGET_GET(x) (((uint32_t)(x) & PCFG_TRACK_TARGET_TARGET_MASK) >> PCFG_TRACK_TARGET_TARGET_SHIFT) + +/* Bitfield definition for register: STATUS */ +/* + * SEL32K (RO) + * + * track is using XTAL32K + * 0: track is not using XTAL32K + * 1: track is using XTAL32K + */ +#define PCFG_STATUS_SEL32K_MASK (0x100000UL) +#define PCFG_STATUS_SEL32K_SHIFT (20U) +#define PCFG_STATUS_SEL32K_GET(x) (((uint32_t)(x) & PCFG_STATUS_SEL32K_MASK) >> PCFG_STATUS_SEL32K_SHIFT) + +/* + * SEL24M (RO) + * + * track is using XTAL24M + * 0: track is not using XTAL24M + * 1: track is using XTAL24M + */ +#define PCFG_STATUS_SEL24M_MASK (0x10000UL) +#define PCFG_STATUS_SEL24M_SHIFT (16U) +#define PCFG_STATUS_SEL24M_GET(x) (((uint32_t)(x) & PCFG_STATUS_SEL24M_MASK) >> PCFG_STATUS_SEL24M_SHIFT) + +/* + * EN_TRIM (RO) + * + * default value takes effect + * 0: default value is invalid + * 1: default value is valid + */ +#define PCFG_STATUS_EN_TRIM_MASK (0x8000U) +#define PCFG_STATUS_EN_TRIM_SHIFT (15U) +#define PCFG_STATUS_EN_TRIM_GET(x) (((uint32_t)(x) & PCFG_STATUS_EN_TRIM_MASK) >> PCFG_STATUS_EN_TRIM_SHIFT) + +/* + * TRIM_C (RO) + * + * default coarse trim value + */ +#define PCFG_STATUS_TRIM_C_MASK (0x700U) +#define PCFG_STATUS_TRIM_C_SHIFT (8U) +#define PCFG_STATUS_TRIM_C_GET(x) (((uint32_t)(x) & PCFG_STATUS_TRIM_C_MASK) >> PCFG_STATUS_TRIM_C_SHIFT) + +/* + * TRIM_F (RO) + * + * default fine trim value + */ +#define PCFG_STATUS_TRIM_F_MASK (0x1FU) +#define PCFG_STATUS_TRIM_F_SHIFT (0U) +#define PCFG_STATUS_TRIM_F_GET(x) (((uint32_t)(x) & PCFG_STATUS_TRIM_F_MASK) >> PCFG_STATUS_TRIM_F_SHIFT) + + + + +#endif /* HPM_PCFG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_pdgo_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_pdgo_regs.h new file mode 100644 index 00000000000..5f4c0feeb19 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_pdgo_regs.h @@ -0,0 +1,228 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PDGO_H +#define HPM_PDGO_H + +typedef struct { + __W uint32_t DGO_TURNOFF; /* 0x0: trunoff control */ + __RW uint32_t DGO_RC32K_CFG; /* 0x4: RC32K CLOCK */ + __R uint8_t RESERVED0[1528]; /* 0x8 - 0x5FF: Reserved */ + __RW uint32_t DGO_GPR00; /* 0x600: Generic control 0 */ + __RW uint32_t DGO_GPR01; /* 0x604: Generic control 1 */ + __RW uint32_t DGO_GPR02; /* 0x608: Generic control 2 */ + __RW uint32_t DGO_GPR03; /* 0x60C: Generic control 3 */ + __R uint8_t RESERVED1[240]; /* 0x610 - 0x6FF: Reserved */ + __RW uint32_t DGO_CTR0; /* 0x700: control register 0 */ + __RW uint32_t DGO_CTR1; /* 0x704: control register 1 */ + __RW uint32_t DGO_CTR2; /* 0x708: control register 2 */ + __RW uint32_t DGO_CTR3; /* 0x70C: control register 3 */ + __RW uint32_t DGO_CTR4; /* 0x710: control register 4 */ +} PDGO_Type; + + +/* Bitfield definition for register: DGO_TURNOFF */ +/* + * COUNTER (WO) + * + * trunoff counter, counter stops when it counts down to 0, the trunoff occurs when the counter value is 1. + */ +#define PDGO_DGO_TURNOFF_COUNTER_MASK (0xFFFFFFFFUL) +#define PDGO_DGO_TURNOFF_COUNTER_SHIFT (0U) +#define PDGO_DGO_TURNOFF_COUNTER_SET(x) (((uint32_t)(x) << PDGO_DGO_TURNOFF_COUNTER_SHIFT) & PDGO_DGO_TURNOFF_COUNTER_MASK) +#define PDGO_DGO_TURNOFF_COUNTER_GET(x) (((uint32_t)(x) & PDGO_DGO_TURNOFF_COUNTER_MASK) >> PDGO_DGO_TURNOFF_COUNTER_SHIFT) + +/* Bitfield definition for register: DGO_RC32K_CFG */ +/* + * IRC_TRIMMED (RW) + * + * IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value + * 0: irc is not trimmed + * 1: irc is trimmed + */ +#define PDGO_DGO_RC32K_CFG_IRC_TRIMMED_MASK (0x80000000UL) +#define PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SHIFT (31U) +#define PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SET(x) (((uint32_t)(x) << PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SHIFT) & PDGO_DGO_RC32K_CFG_IRC_TRIMMED_MASK) +#define PDGO_DGO_RC32K_CFG_IRC_TRIMMED_GET(x) (((uint32_t)(x) & PDGO_DGO_RC32K_CFG_IRC_TRIMMED_MASK) >> PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SHIFT) + +/* + * CAPEX7_TRIM (RW) + * + * IRC32K bit 7 + */ +#define PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_MASK (0x800000UL) +#define PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SHIFT (23U) +#define PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SET(x) (((uint32_t)(x) << PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SHIFT) & PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_MASK) +#define PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_GET(x) (((uint32_t)(x) & PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_MASK) >> PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SHIFT) + +/* + * CAPEX6_TRIM (RW) + * + * IRC32K bit 6 + */ +#define PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_MASK (0x400000UL) +#define PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SHIFT (22U) +#define PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SET(x) (((uint32_t)(x) << PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SHIFT) & PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_MASK) +#define PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_GET(x) (((uint32_t)(x) & PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_MASK) >> PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SHIFT) + +/* + * CAP_TRIM (RW) + * + * capacitor trim bits + */ +#define PDGO_DGO_RC32K_CFG_CAP_TRIM_MASK (0x1FFU) +#define PDGO_DGO_RC32K_CFG_CAP_TRIM_SHIFT (0U) +#define PDGO_DGO_RC32K_CFG_CAP_TRIM_SET(x) (((uint32_t)(x) << PDGO_DGO_RC32K_CFG_CAP_TRIM_SHIFT) & PDGO_DGO_RC32K_CFG_CAP_TRIM_MASK) +#define PDGO_DGO_RC32K_CFG_CAP_TRIM_GET(x) (((uint32_t)(x) & PDGO_DGO_RC32K_CFG_CAP_TRIM_MASK) >> PDGO_DGO_RC32K_CFG_CAP_TRIM_SHIFT) + +/* Bitfield definition for register: DGO_GPR00 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PDGO_DGO_GPR00_GPR_MASK (0xFFFFFFFFUL) +#define PDGO_DGO_GPR00_GPR_SHIFT (0U) +#define PDGO_DGO_GPR00_GPR_SET(x) (((uint32_t)(x) << PDGO_DGO_GPR00_GPR_SHIFT) & PDGO_DGO_GPR00_GPR_MASK) +#define PDGO_DGO_GPR00_GPR_GET(x) (((uint32_t)(x) & PDGO_DGO_GPR00_GPR_MASK) >> PDGO_DGO_GPR00_GPR_SHIFT) + +/* Bitfield definition for register: DGO_GPR01 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PDGO_DGO_GPR01_GPR_MASK (0xFFFFFFFFUL) +#define PDGO_DGO_GPR01_GPR_SHIFT (0U) +#define PDGO_DGO_GPR01_GPR_SET(x) (((uint32_t)(x) << PDGO_DGO_GPR01_GPR_SHIFT) & PDGO_DGO_GPR01_GPR_MASK) +#define PDGO_DGO_GPR01_GPR_GET(x) (((uint32_t)(x) & PDGO_DGO_GPR01_GPR_MASK) >> PDGO_DGO_GPR01_GPR_SHIFT) + +/* Bitfield definition for register: DGO_GPR02 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PDGO_DGO_GPR02_GPR_MASK (0xFFFFFFFFUL) +#define PDGO_DGO_GPR02_GPR_SHIFT (0U) +#define PDGO_DGO_GPR02_GPR_SET(x) (((uint32_t)(x) << PDGO_DGO_GPR02_GPR_SHIFT) & PDGO_DGO_GPR02_GPR_MASK) +#define PDGO_DGO_GPR02_GPR_GET(x) (((uint32_t)(x) & PDGO_DGO_GPR02_GPR_MASK) >> PDGO_DGO_GPR02_GPR_SHIFT) + +/* Bitfield definition for register: DGO_GPR03 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PDGO_DGO_GPR03_GPR_MASK (0xFFFFFFFFUL) +#define PDGO_DGO_GPR03_GPR_SHIFT (0U) +#define PDGO_DGO_GPR03_GPR_SET(x) (((uint32_t)(x) << PDGO_DGO_GPR03_GPR_SHIFT) & PDGO_DGO_GPR03_GPR_MASK) +#define PDGO_DGO_GPR03_GPR_GET(x) (((uint32_t)(x) & PDGO_DGO_GPR03_GPR_MASK) >> PDGO_DGO_GPR03_GPR_SHIFT) + +/* Bitfield definition for register: DGO_CTR0 */ +/* + * RETENTION (RW) + * + * dgo register status retenion + */ +#define PDGO_DGO_CTR0_RETENTION_MASK (0x10000UL) +#define PDGO_DGO_CTR0_RETENTION_SHIFT (16U) +#define PDGO_DGO_CTR0_RETENTION_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR0_RETENTION_SHIFT) & PDGO_DGO_CTR0_RETENTION_MASK) +#define PDGO_DGO_CTR0_RETENTION_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR0_RETENTION_MASK) >> PDGO_DGO_CTR0_RETENTION_SHIFT) + +/* Bitfield definition for register: DGO_CTR1 */ +/* + * AOTO_SYS_WAKEUP (RW) + * + * software wakeup： 0 : wakeup once； 1：auto wakeup Continuously + */ +#define PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK (0x80000000UL) +#define PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SHIFT (31U) +#define PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SHIFT) & PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK) +#define PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK) >> PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SHIFT) + +/* + * WAKEUP_EN (RW) + * + * permit wakeup pin or software wakeup + */ +#define PDGO_DGO_CTR1_WAKEUP_EN_MASK (0x10000UL) +#define PDGO_DGO_CTR1_WAKEUP_EN_SHIFT (16U) +#define PDGO_DGO_CTR1_WAKEUP_EN_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR1_WAKEUP_EN_SHIFT) & PDGO_DGO_CTR1_WAKEUP_EN_MASK) +#define PDGO_DGO_CTR1_WAKEUP_EN_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR1_WAKEUP_EN_MASK) >> PDGO_DGO_CTR1_WAKEUP_EN_SHIFT) + +/* + * PIN_WAKEUP_STATUS (RO) + * + * wakeup pin status + */ +#define PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_MASK (0x1U) +#define PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_SHIFT (0U) +#define PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_MASK) >> PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_SHIFT) + +/* Bitfield definition for register: DGO_CTR2 */ +/* + * RESETN_PULLUP_DISABLE (RW) + * + * resetn pin pull up disable + */ +#define PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_MASK (0x1000000UL) +#define PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SHIFT (24U) +#define PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SHIFT) & PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_MASK) +#define PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_MASK) >> PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SHIFT) + +/* + * WAKEUP_PULLDN_DISABLE (RW) + * + * wakeup pin pull down disable + */ +#define PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_MASK (0x10000UL) +#define PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SHIFT (16U) +#define PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SHIFT) & PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_MASK) +#define PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_MASK) >> PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SHIFT) + +/* Bitfield definition for register: DGO_CTR3 */ +/* + * WAKEUP_COUNTER (RW) + * + * software wakeup counter + */ +#define PDGO_DGO_CTR3_WAKEUP_COUNTER_MASK (0xFFFFFFFFUL) +#define PDGO_DGO_CTR3_WAKEUP_COUNTER_SHIFT (0U) +#define PDGO_DGO_CTR3_WAKEUP_COUNTER_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR3_WAKEUP_COUNTER_SHIFT) & PDGO_DGO_CTR3_WAKEUP_COUNTER_MASK) +#define PDGO_DGO_CTR3_WAKEUP_COUNTER_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR3_WAKEUP_COUNTER_MASK) >> PDGO_DGO_CTR3_WAKEUP_COUNTER_SHIFT) + +/* Bitfield definition for register: DGO_CTR4 */ +/* + * BANDGAP_LESS_POWER (RW) + * + * Banggap work in power save mode, banggap function normally + * 0: banggap works in high performance mode + * 1: banggap works in power saving mode + */ +#define PDGO_DGO_CTR4_BANDGAP_LESS_POWER_MASK (0x2U) +#define PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SHIFT (1U) +#define PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SHIFT) & PDGO_DGO_CTR4_BANDGAP_LESS_POWER_MASK) +#define PDGO_DGO_CTR4_BANDGAP_LESS_POWER_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR4_BANDGAP_LESS_POWER_MASK) >> PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SHIFT) + +/* + * BANDGAP_LP_MODE (RW) + * + * Banggap work in low power mode, banggap function limited + * 0: banggap works in normal mode + * 1: banggap works in low power mode + */ +#define PDGO_DGO_CTR4_BANDGAP_LP_MODE_MASK (0x1U) +#define PDGO_DGO_CTR4_BANDGAP_LP_MODE_SHIFT (0U) +#define PDGO_DGO_CTR4_BANDGAP_LP_MODE_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR4_BANDGAP_LP_MODE_SHIFT) & PDGO_DGO_CTR4_BANDGAP_LP_MODE_MASK) +#define PDGO_DGO_CTR4_BANDGAP_LP_MODE_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR4_BANDGAP_LP_MODE_MASK) >> PDGO_DGO_CTR4_BANDGAP_LP_MODE_SHIFT) + + + + +#endif /* HPM_PDGO_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_pgpr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_pgpr_regs.h new file mode 100644 index 00000000000..acf20cfecd5 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_pgpr_regs.h @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PGPR_H +#define HPM_PGPR_H + +typedef struct { + __RW uint32_t PMIC_GPR00; /* 0x0: Generic control */ + __RW uint32_t PMIC_GPR01; /* 0x4: Generic control */ + __RW uint32_t PMIC_GPR02; /* 0x8: Generic control */ + __RW uint32_t PMIC_GPR03; /* 0xC: Generic control */ + __RW uint32_t PMIC_GPR04; /* 0x10: Generic control */ + __RW uint32_t PMIC_GPR05; /* 0x14: Generic control */ + __RW uint32_t PMIC_GPR06; /* 0x18: Generic control */ + __RW uint32_t PMIC_GPR07; /* 0x1C: Generic control */ + __RW uint32_t PMIC_GPR08; /* 0x20: Generic control */ + __RW uint32_t PMIC_GPR09; /* 0x24: Generic control */ + __RW uint32_t PMIC_GPR10; /* 0x28: Generic control */ + __RW uint32_t PMIC_GPR11; /* 0x2C: Generic control */ + __RW uint32_t PMIC_GPR12; /* 0x30: Generic control */ + __RW uint32_t PMIC_GPR13; /* 0x34: Generic control */ + __RW uint32_t PMIC_GPR14; /* 0x38: Generic control */ + __RW uint32_t PMIC_GPR15; /* 0x3C: Generic control */ +} PGPR_Type; + + +/* Bitfield definition for register: PMIC_GPR00 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR00_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR00_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR00_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR00_GPR_SHIFT) & PGPR_PMIC_GPR00_GPR_MASK) +#define PGPR_PMIC_GPR00_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR00_GPR_MASK) >> PGPR_PMIC_GPR00_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR01 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR01_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR01_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR01_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR01_GPR_SHIFT) & PGPR_PMIC_GPR01_GPR_MASK) +#define PGPR_PMIC_GPR01_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR01_GPR_MASK) >> PGPR_PMIC_GPR01_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR02 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR02_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR02_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR02_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR02_GPR_SHIFT) & PGPR_PMIC_GPR02_GPR_MASK) +#define PGPR_PMIC_GPR02_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR02_GPR_MASK) >> PGPR_PMIC_GPR02_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR03 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR03_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR03_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR03_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR03_GPR_SHIFT) & PGPR_PMIC_GPR03_GPR_MASK) +#define PGPR_PMIC_GPR03_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR03_GPR_MASK) >> PGPR_PMIC_GPR03_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR04 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR04_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR04_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR04_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR04_GPR_SHIFT) & PGPR_PMIC_GPR04_GPR_MASK) +#define PGPR_PMIC_GPR04_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR04_GPR_MASK) >> PGPR_PMIC_GPR04_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR05 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR05_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR05_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR05_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR05_GPR_SHIFT) & PGPR_PMIC_GPR05_GPR_MASK) +#define PGPR_PMIC_GPR05_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR05_GPR_MASK) >> PGPR_PMIC_GPR05_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR06 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR06_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR06_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR06_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR06_GPR_SHIFT) & PGPR_PMIC_GPR06_GPR_MASK) +#define PGPR_PMIC_GPR06_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR06_GPR_MASK) >> PGPR_PMIC_GPR06_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR07 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR07_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR07_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR07_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR07_GPR_SHIFT) & PGPR_PMIC_GPR07_GPR_MASK) +#define PGPR_PMIC_GPR07_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR07_GPR_MASK) >> PGPR_PMIC_GPR07_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR08 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR08_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR08_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR08_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR08_GPR_SHIFT) & PGPR_PMIC_GPR08_GPR_MASK) +#define PGPR_PMIC_GPR08_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR08_GPR_MASK) >> PGPR_PMIC_GPR08_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR09 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR09_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR09_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR09_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR09_GPR_SHIFT) & PGPR_PMIC_GPR09_GPR_MASK) +#define PGPR_PMIC_GPR09_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR09_GPR_MASK) >> PGPR_PMIC_GPR09_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR10 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR10_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR10_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR10_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR10_GPR_SHIFT) & PGPR_PMIC_GPR10_GPR_MASK) +#define PGPR_PMIC_GPR10_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR10_GPR_MASK) >> PGPR_PMIC_GPR10_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR11 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR11_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR11_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR11_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR11_GPR_SHIFT) & PGPR_PMIC_GPR11_GPR_MASK) +#define PGPR_PMIC_GPR11_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR11_GPR_MASK) >> PGPR_PMIC_GPR11_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR12 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR12_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR12_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR12_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR12_GPR_SHIFT) & PGPR_PMIC_GPR12_GPR_MASK) +#define PGPR_PMIC_GPR12_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR12_GPR_MASK) >> PGPR_PMIC_GPR12_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR13 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR13_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR13_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR13_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR13_GPR_SHIFT) & PGPR_PMIC_GPR13_GPR_MASK) +#define PGPR_PMIC_GPR13_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR13_GPR_MASK) >> PGPR_PMIC_GPR13_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR14 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR14_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR14_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR14_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR14_GPR_SHIFT) & PGPR_PMIC_GPR14_GPR_MASK) +#define PGPR_PMIC_GPR14_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR14_GPR_MASK) >> PGPR_PMIC_GPR14_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR15 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR15_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR15_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR15_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR15_GPR_SHIFT) & PGPR_PMIC_GPR15_GPR_MASK) +#define PGPR_PMIC_GPR15_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR15_GPR_MASK) >> PGPR_PMIC_GPR15_GPR_SHIFT) + + + + +#endif /* HPM_PGPR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_plic_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_plic_drv.h new file mode 100644 index 00000000000..4c96737ece4 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_plic_drv.h @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PLIC_DRV_H +#define HPM_PLIC_DRV_H + +/** + * @brief PLIC driver APIs + * @defgroup plic_interface PLIC driver APIs + * @{ + */ + +#define HPM_PLIC_TARGET_M_MODE 0 +#define HPM_PLIC_TARGET_S_MODE 1 + +/* Feature Register */ +#define HPM_PLIC_FEATURE_OFFSET (0x00000000UL) +#define HPM_PLIC_FEATURE_VECTORED_MODE (0x2UL) +#define HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ (0x1UL) + +/* Priority Register - 32 bits per irq */ +#define HPM_PLIC_PRIORITY_OFFSET (0x00000004UL) +#define HPM_PLIC_PRIORITY_SHIFT_PER_SOURCE 2 + +/* Pending Register - 1 bit per source */ +#define HPM_PLIC_PENDING_OFFSET (0x00001000UL) +#define HPM_PLIC_PENDING_SHIFT_PER_SOURCE 0 + +#define HPM_PLIC_TRIGGER_TYPE_OFFSET (0x00001080UL) +#define HPM_PLIC_TRIGGER_TYPE_SHIFT_PER_SORUCE 1 + +/* Enable Register - 0x80 per target */ +#define HPM_PLIC_ENABLE_OFFSET (0x00002000UL) +#define HPM_PLIC_ENABLE_SHIFT_PER_TARGET 7 + +/* Priority Threshold Register - 0x1000 per target */ +#define HPM_PLIC_THRESHOLD_OFFSET (0x00200000UL) +#define HPM_PLIC_THRESHOLD_SHIFT_PER_TARGET 12 + + +/* Claim Register - 0x1000 per target */ +#define HPM_PLIC_CLAIM_OFFSET (0x00200004UL) +#define HPM_PLIC_CLAIM_SHIFT_PER_TARGET 12 + +#if !defined(__ASSEMBLER__) + +/** + * @brief Set plic feature + * + * @param[in] base PLIC base address + * @param[in] feature Specific feature to be set + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_set_feature(uint32_t base, uint32_t feature) +{ + *(volatile uint32_t *) (base + HPM_PLIC_FEATURE_OFFSET) = feature; +} + +/** + * @brief Set plic threshold + * + * @param[in] base PLIC base address + * @param[in] target Target to handle specific interrupt + * @param[in] threshold Threshold of IRQ can be serviced + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_set_threshold(uint32_t base, + uint32_t target, + uint32_t threshold) +{ + volatile uint32_t *threshold_ptr = (volatile uint32_t *) (base + + HPM_PLIC_THRESHOLD_OFFSET + + (target << HPM_PLIC_THRESHOLD_SHIFT_PER_TARGET)); + *threshold_ptr = threshold; +} + +/** + * @brief Set interrupt priority + * + * @param[in] base PLIC base address + * @param[in] irq Target interrupt number + * @param[in] priority Priority to be assigned + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_set_irq_priority(uint32_t base, + uint32_t irq, + uint32_t priority) +{ + volatile uint32_t *priority_ptr = (volatile uint32_t *) (base + + HPM_PLIC_PRIORITY_OFFSET + + ((irq - 1) << HPM_PLIC_PRIORITY_SHIFT_PER_SOURCE)); + *priority_ptr = priority; +} + +/** + * @brief Set interrupt pending bit + * + * @param[in] base PLIC base address + * @param[in] irq Target interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_set_irq_pending(uint32_t base, uint32_t irq) +{ + volatile uint32_t *current_ptr = (volatile uint32_t *) (base + + HPM_PLIC_PENDING_OFFSET + ((irq >> 5) << 2)); + *current_ptr = (1 << (irq & 0x1F)); +} + +/** + * @brief Set interrupt trigger type to edge-triggerred + * + * @param[in] base PLIC base address + * @param[in] irq Target interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_enable_irq_edge_trigger(uint32_t base, uint32_t irq) +{ + volatile uint32_t *current_ptr = (volatile uint32_t *) (base + + HPM_PLIC_TRIGGER_TYPE_OFFSET + ((irq >> 5) << 2)); + *current_ptr |= (1UL << (irq & 0x1F)); +} + +/** + * @brief Set interrupt trigger type to level-triggerred + * + * @param[in] base PLIC base address + * @param[in] irq Target interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_enable_irq_level_trigger(uint32_t base, uint32_t irq) +{ + volatile uint32_t *current_ptr = (volatile uint32_t *) (base + + HPM_PLIC_TRIGGER_TYPE_OFFSET + ((irq >> 5) << 2)); + *current_ptr &= ~(1UL << (irq & 0x1F)); +} + +/** + * @brief Enable interrupt + * + * @param[in] base PLIC base address + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number to be enabled + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_enable_irq(uint32_t base, + uint32_t target, + uint32_t irq) +{ + volatile uint32_t *current_ptr = (volatile uint32_t *) (base + + HPM_PLIC_ENABLE_OFFSET + + (target << HPM_PLIC_ENABLE_SHIFT_PER_TARGET) + + ((irq >> 5) << 2)); + uint32_t current = *current_ptr; + current = current | (1 << (irq & 0x1F)); + *current_ptr = current; +} + +/** + * @brief Disable interrupt + * + * @param[in] base PLIC base address + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number to be disabled + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_disable_irq(uint32_t base, + uint32_t target, + uint32_t irq) +{ + volatile uint32_t *current_ptr = (volatile uint32_t *) (base + + HPM_PLIC_ENABLE_OFFSET + + (target << HPM_PLIC_ENABLE_SHIFT_PER_TARGET) + + ((irq >> 5) << 2)); + uint32_t current = *current_ptr; + current = current & ~((1 << (irq & 0x1F))); + *current_ptr = current; +} + +/** + * @brief Claim interrupt + * + * @param[in] base PLIC base address + * @param[in] target Target to claim interrupt + * + */ +ATTR_ALWAYS_INLINE static inline uint32_t __plic_claim_irq(uint32_t base, uint32_t target) +{ + volatile uint32_t *claim_addr = (volatile uint32_t *) (base + + HPM_PLIC_CLAIM_OFFSET + + (target << HPM_PLIC_CLAIM_SHIFT_PER_TARGET)); + return *claim_addr; +} + +/** + * @brief Complete interrupt + * + * @param[in] base PLIC base address + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_complete_irq(uint32_t base, + uint32_t target, + uint32_t irq) +{ + volatile uint32_t *claim_addr = (volatile uint32_t *) (base + + HPM_PLIC_CLAIM_OFFSET + + (target << HPM_PLIC_CLAIM_SHIFT_PER_TARGET)); + *claim_addr = irq; +} + +#endif /* __ASSEMBLER__ */ +/** + * @} + */ +#endif /* HPM_PLIC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_pmic_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_pmic_iomux.h new file mode 100644 index 00000000000..a95ce61e50f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_pmic_iomux.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PMIC_IOMUX_H +#define HPM_PMIC_IOMUX_H + +/* PIOC_PY00_FUNC_CTL function mux definitions */ +#define IOC_PY00_FUNC_CTL_PGPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY00_FUNC_CTL_PGPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY00_FUNC_CTL_PUART_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY00_FUNC_CTL_PUART_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY00_FUNC_CTL_SOC_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY00_FUNC_CTL_SOC_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY01_FUNC_CTL function mux definitions */ +#define IOC_PY01_FUNC_CTL_PGPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY01_FUNC_CTL_PGPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY01_FUNC_CTL_PUART_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY01_FUNC_CTL_PUART_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY01_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY01_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY01_FUNC_CTL_SOC_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY01_FUNC_CTL_SOC_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY02_FUNC_CTL function mux definitions */ +#define IOC_PY02_FUNC_CTL_PGPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY02_FUNC_CTL_PGPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY02_FUNC_CTL_PUART_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY02_FUNC_CTL_PUART_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY02_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY02_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY02_FUNC_CTL_SOC_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY02_FUNC_CTL_SOC_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY03_FUNC_CTL function mux definitions */ +#define IOC_PY03_FUNC_CTL_PGPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY03_FUNC_CTL_PGPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY03_FUNC_CTL_PUART_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY03_FUNC_CTL_PUART_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY03_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY03_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY03_FUNC_CTL_SOC_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY03_FUNC_CTL_SOC_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY04_FUNC_CTL function mux definitions */ +#define IOC_PY04_FUNC_CTL_PGPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY04_FUNC_CTL_PGPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY04_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY04_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY04_FUNC_CTL_SOC_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY04_FUNC_CTL_SOC_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY05_FUNC_CTL function mux definitions */ +#define IOC_PY05_FUNC_CTL_PGPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY05_FUNC_CTL_PGPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY05_FUNC_CTL_PEWDG_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY05_FUNC_CTL_PEWDG_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY05_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY05_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY05_FUNC_CTL_SOC_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY05_FUNC_CTL_SOC_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY06_FUNC_CTL function mux definitions */ +#define IOC_PY06_FUNC_CTL_PGPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY06_FUNC_CTL_PGPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY06_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY06_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY06_FUNC_CTL_SOC_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY06_FUNC_CTL_SOC_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY07_FUNC_CTL function mux definitions */ +#define IOC_PY07_FUNC_CTL_PGPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY07_FUNC_CTL_PGPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY07_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY07_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY07_FUNC_CTL_SOC_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY07_FUNC_CTL_SOC_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + + +#endif /* HPM_PMIC_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_ppor_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_ppor_drv.h new file mode 100644 index 00000000000..bc7ee37f6ad --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_ppor_drv.h @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PPOR_DRV_H +#define HPM_PPOR_DRV_H +#include "hpm_ppor_regs.h" + +typedef enum { + ppor_reset_brownout = 1 << 0, + ppor_reset_debug = 1 << 4, + ppor_reset_wdog0 = 1 << 16, + ppor_reset_wdog1 = 1 << 17, + ppor_reset_pmic_wdog = 1 << 24, + ppor_reset_software = 1 << 31, +} ppor_reset_source_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * perform software reset in counter * (1/24Mhz) seconds + */ +static inline void ppor_sw_reset(PPOR_Type *ptr, uint32_t counter) +{ + ptr->SOFTWARE_RESET = PPOR_SOFTWARE_RESET_COUNTER_SET(counter); } + +/* + * clear enable reset source according to the given mask + */ +static inline void ppor_reset_mask_clear_source_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_ENABLE &= ~mask; +} + +/* + * set enable reset source according to the given mask + */ +static inline void ppor_reset_mask_set_source_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_ENABLE |= mask; +} + +/* + * set enable reset source + */ +static inline void ppor_reset_set_source_enable(PPOR_Type *ptr, uint32_t reset_sources) +{ + ptr->RESET_ENABLE = reset_sources; +} + +/* + * get enabled reset source + */ +static inline uint32_t ppor_reset_get_enabled_source(PPOR_Type *ptr) +{ + return ptr->RESET_ENABLE; +} + +/* + * get reset status + */ +static inline uint32_t ppor_reset_get_status(PPOR_Type *ptr) +{ + return ptr->RESET_STATUS; +} + +/* + * get reset flags + */ +static inline uint32_t ppor_reset_get_flags(PPOR_Type *ptr) +{ + return ptr->RESET_FLAG; +} + +/* + * clear reset flags + */ +static inline void ppor_reset_clear_flags(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_FLAG = mask; +} + +/* + * get reset hold + */ +static inline uint32_t ppor_reset_get_hold(PPOR_Type *ptr) +{ + return ptr->RESET_HOLD; +} + +/* + * set reset hold + */ +static inline void ppor_reset_set_hold_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_HOLD |= mask; +} + +/* + * clear reset hold + */ +static inline void ppor_reset_clear_hold_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_HOLD &= ~mask; +} + +/* + * set cold reset + */ +static inline void ppor_reset_set_cold_reset_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_TYPE &= ~mask; +} + +/* + * clear cold reset + */ +static inline void ppor_reset_clear_cold_reset_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_TYPE |= mask; +} + +/* + * set hot reset + */ +static inline void ppor_reset_set_hot_reset_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_TYPE |= mask; +} + +/* + * clear hot reset + */ +static inline void ppor_reset_clear_hot_reset_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_TYPE &= ~mask; +} + + +#ifdef __cplusplus +} +#endif +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_ppor_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_ppor_regs.h new file mode 100644 index 00000000000..32f5f6bcc61 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_ppor_regs.h @@ -0,0 +1,166 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PPOR_H +#define HPM_PPOR_H + +typedef struct { + __W uint32_t RESET_FLAG; /* 0x0: flag indicate reset source */ + __R uint32_t RESET_STATUS; /* 0x4: reset source status */ + __RW uint32_t RESET_HOLD; /* 0x8: reset hold attribute */ + __RW uint32_t RESET_ENABLE; /* 0xC: reset source enable */ + __RW uint32_t RESET_TYPE; /* 0x10: reset type triggered by reset */ + __R uint8_t RESERVED0[8]; /* 0x14 - 0x1B: Reserved */ + __RW uint32_t SOFTWARE_RESET; /* 0x1C: Software reset counter */ +} PPOR_Type; + + +/* Bitfield definition for register: RESET_FLAG */ +/* + * FLAG (W1C) + * + * reset reason of last hard reset, write 1 to clear each bit + * 0: brownout + * 1: temperature + * 4: debug reset + * 5: jtag soft reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2(not available) + * 19: watch dog 3(not available) + * 24: pmic watch dog + * 30: jtag ieee reset + * 31: software + */ +#define PPOR_RESET_FLAG_FLAG_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_FLAG_FLAG_SHIFT (0U) +#define PPOR_RESET_FLAG_FLAG_SET(x) (((uint32_t)(x) << PPOR_RESET_FLAG_FLAG_SHIFT) & PPOR_RESET_FLAG_FLAG_MASK) +#define PPOR_RESET_FLAG_FLAG_GET(x) (((uint32_t)(x) & PPOR_RESET_FLAG_FLAG_MASK) >> PPOR_RESET_FLAG_FLAG_SHIFT) + +/* Bitfield definition for register: RESET_STATUS */ +/* + * STATUS (RO) + * + * current status of reset sources + * 0: brownout + * 1: temperature + * 4: debug reset + * 5: jtag soft reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2(not available) + * 19: watch dog 3(not available) + * 24: pmic watch dog + * 30: jtag ieee reset + * 31: software + */ +#define PPOR_RESET_STATUS_STATUS_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_STATUS_STATUS_SHIFT (0U) +#define PPOR_RESET_STATUS_STATUS_GET(x) (((uint32_t)(x) & PPOR_RESET_STATUS_STATUS_MASK) >> PPOR_RESET_STATUS_STATUS_SHIFT) + +/* Bitfield definition for register: RESET_HOLD */ +/* + * HOLD (RW) + * + * hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status + * 0: brownout + * 1: temperature + * 4: debug reset + * 5: jtag soft reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2(not available) + * 19: watch dog 3(not available) + * 24: pmic watch dog + * 30: jtag ieee reset + * 31: software + */ +#define PPOR_RESET_HOLD_HOLD_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_HOLD_HOLD_SHIFT (0U) +#define PPOR_RESET_HOLD_HOLD_SET(x) (((uint32_t)(x) << PPOR_RESET_HOLD_HOLD_SHIFT) & PPOR_RESET_HOLD_HOLD_MASK) +#define PPOR_RESET_HOLD_HOLD_GET(x) (((uint32_t)(x) & PPOR_RESET_HOLD_HOLD_MASK) >> PPOR_RESET_HOLD_HOLD_SHIFT) + +/* Bitfield definition for register: RESET_ENABLE */ +/* + * ENABLE (RW) + * + * enable of reset sources + * 0: brownout + * 1: temperature + * 4: debug reset + * 5: jtag soft reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2(not available) + * 19: watch dog 3(not available) + * 24: pmic watch dog + * 30: jtag ieee reset + * 31: software + */ +#define PPOR_RESET_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_ENABLE_ENABLE_SHIFT (0U) +#define PPOR_RESET_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << PPOR_RESET_ENABLE_ENABLE_SHIFT) & PPOR_RESET_ENABLE_ENABLE_MASK) +#define PPOR_RESET_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & PPOR_RESET_ENABLE_ENABLE_MASK) >> PPOR_RESET_ENABLE_ENABLE_SHIFT) + +/* Bitfield definition for register: RESET_TYPE */ +/* + * TYPE (RW) + * + * reset type of reset sources, 0 for cold reset, all system control setting cleared except debug/fuse/ioc; 1 for hot reset, keep system control setting and debug/fuse/ioc setting, only clear some subsystem + * 0: brownout + * 1: temperature + * 4: debug reset + * 5: jtag soft reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2(not available) + * 19: watch dog 3(not available) + * 24: pmic watch dog + * 30: jtag ieee reset + * 31: software + */ +#define PPOR_RESET_TYPE_TYPE_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_TYPE_TYPE_SHIFT (0U) +#define PPOR_RESET_TYPE_TYPE_SET(x) (((uint32_t)(x) << PPOR_RESET_TYPE_TYPE_SHIFT) & PPOR_RESET_TYPE_TYPE_MASK) +#define PPOR_RESET_TYPE_TYPE_GET(x) (((uint32_t)(x) & PPOR_RESET_TYPE_TYPE_MASK) >> PPOR_RESET_TYPE_TYPE_SHIFT) + +/* Bitfield definition for register: SOFTWARE_RESET */ +/* + * COUNTER (RW) + * + * counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset + */ +#define PPOR_SOFTWARE_RESET_COUNTER_MASK (0xFFFFFFFFUL) +#define PPOR_SOFTWARE_RESET_COUNTER_SHIFT (0U) +#define PPOR_SOFTWARE_RESET_COUNTER_SET(x) (((uint32_t)(x) << PPOR_SOFTWARE_RESET_COUNTER_SHIFT) & PPOR_SOFTWARE_RESET_COUNTER_MASK) +#define PPOR_SOFTWARE_RESET_COUNTER_GET(x) (((uint32_t)(x) & PPOR_SOFTWARE_RESET_COUNTER_MASK) >> PPOR_SOFTWARE_RESET_COUNTER_SHIFT) + + + + +#endif /* HPM_PPOR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_romapi.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_romapi.h new file mode 100644 index 00000000000..34fa7447366 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_romapi.h @@ -0,0 +1,651 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_ROMAPI_H +#define HPM_ROMAPI_H + +/** + * @brief ROM APIs + * @defgroup romapi_interface ROM APIs + * @{ + */ + +#include "hpm_common.h" +#include "hpm_otp_drv.h" +#include "hpm_romapi_xpi_def.h" +#include "hpm_romapi_xpi_soc_def.h" +#include "hpm_romapi_xpi_nor_def.h" +#include "hpm_romapi_xpi_ram_def.h" +#include "hpm_soc_feature.h" + +/* XPI0 base address */ +#define HPM_XPI0_BASE (0xF3000000UL) /**< XPI0 Base address */ +/* XPI0 base pointer */ +#define HPM_XPI0 ((XPI_Type *) HPM_XPI0_BASE) /**< XPI0 Base pointer */ + + +/*********************************************************************************************************************** + * + * + * Definitions + * + * + **********************************************************************************************************************/ +/** + * @brief Enter Bootloader API argument + */ +typedef union { + uint32_t U; + struct { + uint32_t index: 8; /**< Image index */ + uint32_t peripheral: 8; /**< Boot peripheral */ + uint32_t src: 8; /**< Boot source */ + uint32_t tag: 8; /**< ROM API parameter tag, must be 0xEB */ + }; +} api_boot_arg_t; + +/*EXiP Region Parameter */ +typedef struct { + uint32_t start; /**< Start address, must be 4KB aligned */ + uint32_t len; /**< Must be 4KB aligned */ + uint8_t key[16]; /**< AES Key */ + uint8_t ctr[8]; /**< Initial Vector/Counter */ +} exip_region_param_t; + +typedef struct { + uint32_t region_start; + uint32_t region_end; + uint8_t aes_key[16]; + uint8_t nonce[8]; + uint8_t index; + bool enable; + bool valid; + bool lock; +} exip_region_context_t; + +#define API_BOOT_TAG (0xEBU) /**< ROM API parameter tag */ +#define API_BOOT_SRC_OTP (0U) /**< Boot source: OTP */ +#define API_BOOT_SRC_PRIMARY (1U) /**< Boot source: Primary */ +#define API_BOOT_SRC_SERIAL_BOOT (2U) /**< Boot source: Serial Boot */ +#define API_BOOT_SRC_ISP (3U) /**< Boot source: ISP */ +#define API_BOOT_PERIPH_AUTO (0U) /**< Boot peripheral: Auto detected */ +#define API_BOOT_PERIPH_UART (1U) /**< Boot peripheral: UART */ +#define API_BOOT_PERIPH_USBHID (2U) /**< Boot Peripheral: USB-HID */ + +/** + * @brief OTP driver interface + */ +typedef struct { + /**< OTP driver interface version */ + uint32_t version; + /**< OTP driver interface: init */ + void (*init)(void); + /**< OTP driver interface: deinit */ + void (*deinit)(void); + /**< OTP driver interface: read from shadow */ + uint32_t (*read_from_shadow)(uint32_t addr); + /**< OTP driver interface: read from ip */ + uint32_t (*read_from_ip)(uint32_t addr); + /**< OTP driver interface: program */ + hpm_stat_t (*program)(uint32_t addr, const uint32_t *src, uint32_t num_of_words); + /**< OTP driver interface: reload */ + hpm_stat_t (*reload)(otp_region_t region); + /**< OTP driver interface: lock */ + hpm_stat_t (*lock)(uint32_t addr, otp_lock_option_t lock_option); + /**< OTP driver interface: lock_shadow */ + hpm_stat_t (*lock_shadow)(uint32_t addr, otp_lock_option_t lock_option); + /**< OTP driver interface: set_configurable_region */ + hpm_stat_t (*set_configurable_region)(uint32_t start, uint32_t num_of_words); + /**< OTP driver interface: write_shadow_register */ + hpm_stat_t (*write_shadow_register)(uint32_t addr, uint32_t data); +} otp_driver_interface_t; + +/** + * @brief XPI driver interface + */ +typedef struct { + /**< XPI driver interface: version */ + uint32_t version; + /**< XPI driver interface: get default configuration */ + hpm_stat_t (*get_default_config)(xpi_config_t *xpi_config); + /**< XPI driver interface: get default device configuration */ + hpm_stat_t (*get_default_device_config)(xpi_device_config_t *dev_config); + /**< XPI driver interface: initialize the XPI using xpi_config */ + hpm_stat_t (*init)(XPI_Type *base, xpi_config_t *xpi_config); + /**< XPI driver interface: configure the AHB buffer */ + hpm_stat_t (*config_ahb_buffer)(XPI_Type *base, xpi_ahb_buffer_cfg_t *ahb_buf_cfg); + /**< XPI driver interface: configure the device */ + hpm_stat_t (*config_device)(XPI_Type *base, xpi_device_config_t *dev_cfg, xpi_channel_t channel); + /**< XPI driver interface: update instruction talbe */ + hpm_stat_t (*update_instr_table)(XPI_Type *base, const uint32_t *inst_base, uint32_t seq_idx, uint32_t num); + /**< XPI driver interface: transfer command/data using block interface */ + hpm_stat_t (*transfer_blocking)(XPI_Type *base, xpi_xfer_ctx_t *xfer); + /**< Software reset the XPI controller */ + void (*software_reset)(XPI_Type *base); + /**< XPI driver interface: Check whether IP is idle */ + bool (*is_idle)(XPI_Type *base); + /**< XPI driver interface: update delay line setting */ + void (*update_dllcr)(XPI_Type *base, + uint32_t serial_root_clk_freq, + uint32_t data_valid_time, + xpi_channel_t channel, + uint32_t dly_target); + /**< XPI driver interface: Get absolute address for APB transfer */ + hpm_stat_t + (*get_abs_apb_xfer_addr)(XPI_Type *base, xpi_xfer_channel_t channel, uint32_t in_addr, uint32_t *out_addr); +} xpi_driver_interface_t; + +/** + * @brief XPI NOR driver interface + */ +typedef struct { + /**< XPI NOR driver interface: API version */ + uint32_t version; + /**< XPI NOR driver interface: Get FLASH configuration */ + hpm_stat_t (*get_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option); + /**< XPI NOR driver interface: initialize FLASH */ + hpm_stat_t (*init)(XPI_Type *base, xpi_nor_config_t *nor_config); + /**< XPI NOR driver interface: Enable write access to FLASH */ + hpm_stat_t + (*enable_write)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + /**< XPI NOR driver interface: Get FLASH status register */ + hpm_stat_t (*get_status)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t addr, + uint16_t *out_status); + /**< XPI NOR driver interface: Wait when FLASH is still busy */ + hpm_stat_t + (*wait_busy)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + /**< XPI NOR driver interface: erase a specified FLASH region */ + hpm_stat_t (*erase)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start, + uint32_t length); + /**< XPI NOR driver interface: Erase the whole FLASH */ + hpm_stat_t (*erase_chip)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config); + /**< XPI NOR driver interface: Erase specified FLASH sector */ + hpm_stat_t + (*erase_sector)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + /**< XPI NOR driver interface: Erase specified FLASH block */ + hpm_stat_t + (*erase_block)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + /**< XPI NOR driver interface: Program data to specified FLASH address */ + hpm_stat_t (*program)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + const uint32_t *src, + uint32_t dst_addr, + uint32_t length); + /**< XPI NOR driver interface: read data from specified FLASH address */ + hpm_stat_t (*read)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t *dst, + uint32_t start, + uint32_t length); + /**< XPI NOR driver interface: program FLASH page using nonblocking interface */ + hpm_stat_t (*page_program_nonblocking)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + const uint32_t *src, + uint32_t dst_addr, + uint32_t length); + /**< XPI NOR driver interface: erase FLASH sector using nonblocking interface */ + hpm_stat_t (*erase_sector_nonblocking)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t addr); + /**< XPI NOR driver interface: erase FLASH block using nonblocking interface */ + hpm_stat_t (*erase_block_nonblocking)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t addr); + /**< XPI NOR driver interface: erase the whole FLASh using nonblocking interface */ + hpm_stat_t + (*erase_chip_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config); + + uint32_t reserved0[3]; + + /**< XPI NOR driver interface: automatically configuration flash based on the cfg_option setting */ + hpm_stat_t (*auto_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option); + + /**< XPI NOR driver interface: Get FLASH properties */ + hpm_stat_t (*get_property)(XPI_Type *base, xpi_nor_config_t *nor_cfg, uint32_t property_id, uint32_t *value); + +} xpi_nor_driver_interface_t; + +/** + * @brief EXIP driver interface + */ +typedef struct { + uint32_t version; + hpm_stat_t (*enable)(XPI_Type *base); + hpm_stat_t (*disable)(XPI_Type *base); + hpm_stat_t (*lock_reg_access)(XPI_Type *base); + hpm_stat_t (*configure_region)(XPI_Type *base, const exip_region_context_t *ctx); + + bool (*remap_config)(XPI_Type *base, uint32_t start, uint32_t len, uint32_t offset); + bool (*remap_enabled)(XPI_Type *base); + void (*remap_disable)(XPI_Type *base); + bool (*exip_region_config)(XPI_Type *base, uint32_t index, exip_region_param_t *param); + void (*exip_region_disable)(XPI_Type *base, uint32_t index); +} exip_driver_interface_t; + +/** + * @brief Bootloader API table + */ +typedef struct { + /**< Bootloader API table: version */ + const uint32_t version; + /**< Bootloader API table: copyright string address */ + const char *copyright; + /**< Bootloader API table: run_bootloader API */ + hpm_stat_t (*run_bootloader)(void *arg); + /**< Bootloader API table: otp driver interface address */ + const otp_driver_interface_t *otp_driver_if; + /**< Bootloader API table: xpi driver interface address */ + const xpi_driver_interface_t *xpi_driver_if; + /**< Bootloader API table: xpi nor driver interface address */ + const xpi_nor_driver_interface_t *xpi_nor_driver_if; + /**< Bootloader API table: xpi ram driver interface address */ + const uint32_t reserved0; + const uint32_t reserved[4]; + const exip_driver_interface_t *exip_api_if; + const uint32_t family_id; +} bootloader_api_table_t; + +/**< Bootloader API table Root */ +#define ROM_API_TABLE_ROOT ((const bootloader_api_table_t *)0x2001FF00U) + + +#ifdef __cplusplus +extern "C" { +#endif + +/*********************************************************************************************************************** + * + * + * Enter bootloader Wrapper + * + * + **********************************************************************************************************************/ + +/** + * @brief Eneter specified Boot mode + * @param [in] ctx Enter bootloader context + * @retval status_invalid Invalid parameters were deteced + */ +static inline hpm_stat_t rom_enter_bootloader(void *ctx) +{ + return ROM_API_TABLE_ROOT->run_bootloader(ctx); +} + +/*********************************************************************************************************************** + * + * + * XPI NOR Driver Wrapper + * + * + **********************************************************************************************************************/ + +/** + * @brief Get XPI NOR configuration via cfg_option + * @param [in] base XPI base address + * @param [out] nor_cfg XPI NOR configuration structure + * @param [in] cfg_option XPI NOR configuration option + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_get_config(XPI_Type *base, + xpi_nor_config_t *nor_cfg, + xpi_nor_config_option_t *cfg_option) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_config(base, nor_cfg, cfg_option); +} + +/** + * @brief Initialize XPI NOR based on nor_config + * @param [in] base XPI base address + * @param[in] nor_config XPI NOR configuration + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_init(XPI_Type *base, xpi_nor_config_t *nor_config) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->init(base, nor_config); +} + +/** + * @brief Erase specified FLASH region + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI nOR configuration + * @param[in] start Erase address start address + * @param[in] length Region size to be erased + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start, + uint32_t length) +{ + hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase(base, channel, nor_config, start, length); + fencei(); + return status; +} + +/** + * @brief Erase specified FLASH sector in blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] start Sector address + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_sector(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start) +{ + hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector(base, channel, nor_config, start); + fencei(); + return status; +} + +/** + * @brief Erase specified FLASH sector in non-blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] start Sector address + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_sector_nonblocking(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector_nonblocking(base, channel, nor_config, start); +} + +/** + * @brief Erase specified FLASH blcok in blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] start Block address + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_block(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start) +{ + hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block(base, channel, nor_config, start); + fencei(); + return status; +} + +/** + * @brief Erase specified FLASH blcok in non-blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] start Block address + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_block_nonblocking(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block_nonblocking(base, channel, nor_config, start); +} + +/** + * @brief Erase the whole FLASH in blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_chip(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip(base, channel, nor_config); +} + +/** + * @brief Erase the whole FLASH in non-blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_chip_nonblocking(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config) +{ + hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip_nonblocking(base, channel, nor_config); + fencei(); + return status; +} + +/** + * @brief Program data to specified FLASH address in blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] src data source address + * @param[in] dst_addr Destination FLASH address + * @param[in] length length of data to be programmed + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_program(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + const uint32_t *src, + uint32_t dst_addr, + uint32_t length) +{ + hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->program(base, channel, nor_config, src, dst_addr, length); + fencei(); + return status; +} + +/** + * @brief Page-Program data to specified FLASH address in non-blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] src data source address + * @param[in] dst_addr Destination FLASH address + * @param[in] length length of data to be programmed + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_page_program_nonblocking(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + const uint32_t *src, + uint32_t dst_addr, + uint32_t length) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if + ->page_program_nonblocking(base, channel, nor_config, src, dst_addr, length); +} + +/** + * @brief Read data from specified FLASH address + * @param [in] base XPI base address + * @param [in] channel XPI transfer channel + * @param [in] nor_config XPI NOR configuration + * @param [in] dst Memory start address to store the data read out from FLASH + * @param [in] start FLASH address for data read + * @param [in] length length of data to be read out + * @return API execution address + */ +static inline hpm_stat_t rom_xpi_nor_read(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t *dst, + uint32_t start, + uint32_t length) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->read(base, channel, nor_config, dst, start, length); +} + +/** + * @brief Automatically configure XPI NOR based on cfg_option + * @param [in] base XPI base address + * @param [out] config XPI NOR configuration structure + * @param [in] cfg_option XPI NOR configuration option + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_auto_config(XPI_Type *base, + xpi_nor_config_t *config, + xpi_nor_config_option_t *cfg_option) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->auto_config(base, config, cfg_option); +} + +/** + * @brief Get XPI NOR properties + * @param [in] base XPI base address + * @param [in] nor_cfg XPI NOR configuration structure + * @param [in] property_id + * @param [out] value property value retrieved by this API + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_get_property(XPI_Type *base, + xpi_nor_config_t *nor_cfg, + uint32_t property_id, + uint32_t *value) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_property(base, nor_cfg, property_id, value); +} + +/** + * @brief Return the status register value on XPI NOR FLASH + * + * @param [in] base XPI base address + * @param [in] channel XPI transfer channel + * @param [in] nor_config XPI NOR configuration + * @param [in] addr FLASH address offset + * @param [out] out_status FLASH status register value + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_get_status(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t addr, + uint16_t *out_status) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_status(base, channel, nor_config, addr, out_status); +} + +/** + * @brief Configure the XPI Address Remapping Logic + * @param [in] base XPI base address + * @param [in] start Start Address (memory mapped address) + * @param [in] len Size for the remapping region + * @param [in] offset Relative address based on parameter "start" + * @retval true is all parameters are valid + * @retval false if any parameter is invalid + */ +ATTR_RAMFUNC +static inline bool rom_xpi_nor_remap_config(XPI_Type *base, uint32_t start, uint32_t len, uint32_t offset) +{ + return ROM_API_TABLE_ROOT->exip_api_if->remap_config(base, start, len, offset); +} + +/** + * @brief Disable XPI Remapping logic + * @param [in] base XPI base address + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_remap_disable(XPI_Type *base) +{ + ROM_API_TABLE_ROOT->exip_api_if->remap_disable(base); + fencei(); +} + +/** + * @brief Check whether XPI Remapping is enabled + * @param [in] base XPI base address + * + * @retval true Remapping logic is enabled + * @retval false Remapping logic is disabled + */ +ATTR_RAMFUNC +static inline bool rom_xpi_nor_is_remap_enabled(XPI_Type *base) +{ + return ROM_API_TABLE_ROOT->exip_api_if->remap_enabled(base); +} + +/** + * @brief Configure Specified EXiP Region + * @param [in] base XPI base address + * @param [in] index EXiP Region index + * @param [in] param ExiP Region Parameter + * @retval true All parameters are valid + * @retval false Any parameter is invalid + */ +ATTR_RAMFUNC +static inline bool rom_xpi_nor_exip_region_config(XPI_Type *base, uint32_t index, exip_region_param_t *param) +{ + bool result = ROM_API_TABLE_ROOT->exip_api_if->exip_region_config(base, index, param); + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); + fencei(); + return result; +} + +/** + * @brief Disable EXiP Feature on specified EXiP Region + * @param [in] base XPI base address + * @param [in] index EXiP Region index + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_exip_region_disable(XPI_Type *base, uint32_t index) +{ + ROM_API_TABLE_ROOT->exip_api_if->exip_region_disable(base, index); + fencei(); +} + +/** + * @brief Enable global EXiP logic + * @param [in] base XPI base address + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_exip_enable(XPI_Type *base) +{ + ROM_API_TABLE_ROOT->exip_api_if->enable(base); + fencei(); +} + +/** + * @brief Disable global EXiP logic + * @param [in] base XPI base address + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_exip_disable(XPI_Type *base) +{ + ROM_API_TABLE_ROOT->exip_api_if->disable(base); + fencei(); +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + + +#endif /* HPM_ROMAPI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_romapi_xpi_soc_def.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_romapi_xpi_soc_def.h new file mode 100644 index 00000000000..ea3ba9e8f9b --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_romapi_xpi_soc_def.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_ROMAPI_XPI_SOC_DEF_H +#define HPM_ROMAPI_XPI_SOC_DEF_H + +#include "hpm_common.h" +#include "hpm_romapi_xpi_def.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +#define XPI_CLK_OUT_FREQ_OPTION_30MHz (1U) +#define XPI_CLK_OUT_FREQ_OPTION_50MHz (2U) +#define XPI_CLK_OUT_FREQ_OPTION_66MHz (3U) +#define XPI_CLK_OUT_FREQ_OPTION_80MHz (4U) +#define XPI_CLK_OUT_FREQ_OPTION_104MHz (5U) +#define XPI_CLK_OUT_FREQ_OPTION_120MHz (6U) +#define XPI_CLK_OUT_FREQ_OPTION_133MHz (7U) +#define XPI_CLK_OUT_FREQ_OPTION_166MHz (8U) +#define XPI_CLK_OUT_FREQ_OPTION_200MHz (9U) + +typedef struct { + struct { + uint8_t priority; /* Offset: 0x00 */ + uint8_t master_idx; /* Offset: 0x01 */ + uint8_t buf_size_in_dword; /* Offset: 0x02 */ + bool enable_prefetch; /* Offset: 0x03 */ + } entry[8]; +} xpi_ahb_buffer_cfg_t; + +typedef struct { + uint8_t data_pads; + xpi_channel_t channel; + xpi_io_group_t io_group; + uint8_t drive_strength; + bool enable_dqs; + bool enable_diff_clk; +} xpi_io_config_t; + +typedef enum { + xpi_freq_type_typical, + xpi_freq_type_mhz, +} clk_freq_type_t; + +typedef enum { + xpi_clk_src_auto, + xpi_clk_src_osc, + xpi_clk_src_pll0clk0, + xpi_clk_src_pll1clk0, + xpi_clk_src_pll1clk1, + xpi_clk_src_pll2clk0, + xpi_clk_src_pll2clk1, + xpi_clk_src_pll3clk0, + xpi_clk_src_pll4clk0, +} xpi_clk_src_t; + + +typedef union { + struct { + uint8_t freq; + bool enable_ddr; + xpi_clk_src_t clk_src; + clk_freq_type_t freq_type; + }; + uint32_t freq_opt; +} xpi_clk_config_t; + +typedef enum { + xpi_clock_bus, + xpi_clock_serial_root, + xpi_clock_serial, +} xpi_clock_t; + +#endif /* HPM_ROMAPI_XPI_SOC_DEF_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_ses_reg.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_ses_reg.xml new file mode 100644 index 00000000000..9e851fe9e98 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_ses_reg.xml @@ -0,0 +1,11756 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_ses_riscv_cpu_regs.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_ses_riscv_cpu_regs.xml new file mode 100644 index 00000000000..da5654d4ec5 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_ses_riscv_cpu_regs.xml @@ -0,0 +1,593 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_soc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_soc.h new file mode 100644 index 00000000000..62c4e1600e7 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_soc.h @@ -0,0 +1,353 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_SOC_H +#define HPM_SOC_H + + +/* List of external IRQs */ +#define IRQn_GPIO0_A 1 /* GPIO0_A IRQ */ +#define IRQn_GPIO0_B 2 /* GPIO0_B IRQ */ +#define IRQn_GPIO0_X 3 /* GPIO0_X IRQ */ +#define IRQn_GPIO0_Y 4 /* GPIO0_Y IRQ */ +#define IRQn_GPTMR0 5 /* GPTMR0 IRQ */ +#define IRQn_GPTMR1 6 /* GPTMR1 IRQ */ +#define IRQn_UART0 13 /* UART0 IRQ */ +#define IRQn_UART1 14 /* UART1 IRQ */ +#define IRQn_UART2 15 /* UART2 IRQ */ +#define IRQn_UART3 16 /* UART3 IRQ */ +#define IRQn_I2C0 21 /* I2C0 IRQ */ +#define IRQn_I2C1 22 /* I2C1 IRQ */ +#define IRQn_I2C2 23 /* I2C2 IRQ */ +#define IRQn_I2C3 24 /* I2C3 IRQ */ +#define IRQn_SPI0 25 /* SPI0 IRQ */ +#define IRQn_SPI1 26 /* SPI1 IRQ */ +#define IRQn_SPI2 27 /* SPI2 IRQ */ +#define IRQn_SPI3 28 /* SPI3 IRQ */ +#define IRQn_TSNS 29 /* TSNS IRQ */ +#define IRQn_MBX0A 30 /* MBX0A IRQ */ +#define IRQn_MBX0B 31 /* MBX0B IRQ */ +#define IRQn_EWDG0 32 /* EWDG0 IRQ */ +#define IRQn_EWDG1 33 /* EWDG1 IRQ */ +#define IRQn_HDMA 34 /* HDMA IRQ */ +#define IRQn_USB0 51 /* USB0 IRQ */ +#define IRQn_XPI0 52 /* XPI0 IRQ */ +#define IRQn_PSEC 54 /* PSEC IRQ */ +#define IRQn_SECMON 55 /* SECMON IRQ */ +#define IRQn_FUSE 57 /* FUSE IRQ */ +#define IRQn_ADC0 58 /* ADC0 IRQ */ +#define IRQn_ACMP_0 62 /* ACMP_0 IRQ */ +#define IRQn_ACMP_1 63 /* ACMP_1 IRQ */ +#define IRQn_SYSCTL 64 /* SYSCTL IRQ */ +#define IRQn_PGPIO 65 /* PGPIO IRQ */ +#define IRQn_PTMR 66 /* PTMR IRQ */ +#define IRQn_PUART 67 /* PUART IRQ */ +#define IRQn_PEWDG 68 /* PEWDG IRQ */ +#define IRQn_BROWNOUT 69 /* BROWNOUT IRQ */ +#define IRQn_PAD_WAKEUP 70 /* PAD_WAKEUP IRQ */ +#define IRQn_DEBUG0 71 /* DEBUG0 IRQ */ +#define IRQn_DEBUG1 72 /* DEBUG1 IRQ */ + +#include "hpm_common.h" + +#include "hpm_gpio_regs.h" +/* Address of GPIO instances */ +/* FGPIO base address */ +#define HPM_FGPIO_BASE (0xC0000UL) +/* FGPIO base pointer */ +#define HPM_FGPIO ((GPIO_Type *) HPM_FGPIO_BASE) +/* GPIO0 base address */ +#define HPM_GPIO0_BASE (0xF00D0000UL) +/* GPIO0 base pointer */ +#define HPM_GPIO0 ((GPIO_Type *) HPM_GPIO0_BASE) +/* PGPIO base address */ +#define HPM_PGPIO_BASE (0xF411C000UL) +/* PGPIO base pointer */ +#define HPM_PGPIO ((GPIO_Type *) HPM_PGPIO_BASE) + +/* Address of DM instances */ +/* DM base address */ +#define HPM_DM_BASE (0x30000000UL) + +#include "hpm_plic_regs.h" +/* Address of PLIC instances */ +/* PLIC base address */ +#define HPM_PLIC_BASE (0xE4000000UL) +/* PLIC base pointer */ +#define HPM_PLIC ((PLIC_Type *) HPM_PLIC_BASE) + +#include "hpm_mchtmr_regs.h" +/* Address of MCHTMR instances */ +/* MCHTMR base address */ +#define HPM_MCHTMR_BASE (0xE6000000UL) +/* MCHTMR base pointer */ +#define HPM_MCHTMR ((MCHTMR_Type *) HPM_MCHTMR_BASE) + +#include "hpm_plic_sw_regs.h" +/* Address of PLICSW instances */ +/* PLICSW base address */ +#define HPM_PLICSW_BASE (0xE6400000UL) +/* PLICSW base pointer */ +#define HPM_PLICSW ((PLIC_SW_Type *) HPM_PLICSW_BASE) + +#include "hpm_gptmr_regs.h" +/* Address of TMR instances */ +/* GPTMR0 base address */ +#define HPM_GPTMR0_BASE (0xF0000000UL) +/* GPTMR0 base pointer */ +#define HPM_GPTMR0 ((GPTMR_Type *) HPM_GPTMR0_BASE) +/* GPTMR1 base address */ +#define HPM_GPTMR1_BASE (0xF0004000UL) +/* GPTMR1 base pointer */ +#define HPM_GPTMR1 ((GPTMR_Type *) HPM_GPTMR1_BASE) +/* PTMR base address */ +#define HPM_PTMR_BASE (0xF4120000UL) +/* PTMR base pointer */ +#define HPM_PTMR ((GPTMR_Type *) HPM_PTMR_BASE) + +#include "hpm_uart_regs.h" +/* Address of UART instances */ +/* UART0 base address */ +#define HPM_UART0_BASE (0xF0040000UL) +/* UART0 base pointer */ +#define HPM_UART0 ((UART_Type *) HPM_UART0_BASE) +/* UART1 base address */ +#define HPM_UART1_BASE (0xF0044000UL) +/* UART1 base pointer */ +#define HPM_UART1 ((UART_Type *) HPM_UART1_BASE) +/* UART2 base address */ +#define HPM_UART2_BASE (0xF0048000UL) +/* UART2 base pointer */ +#define HPM_UART2 ((UART_Type *) HPM_UART2_BASE) +/* UART3 base address */ +#define HPM_UART3_BASE (0xF004C000UL) +/* UART3 base pointer */ +#define HPM_UART3 ((UART_Type *) HPM_UART3_BASE) +/* PUART base address */ +#define HPM_PUART_BASE (0xF4124000UL) +/* PUART base pointer */ +#define HPM_PUART ((UART_Type *) HPM_PUART_BASE) + +#include "hpm_i2c_regs.h" +/* Address of I2C instances */ +/* I2C0 base address */ +#define HPM_I2C0_BASE (0xF0060000UL) +/* I2C0 base pointer */ +#define HPM_I2C0 ((I2C_Type *) HPM_I2C0_BASE) +/* I2C1 base address */ +#define HPM_I2C1_BASE (0xF0064000UL) +/* I2C1 base pointer */ +#define HPM_I2C1 ((I2C_Type *) HPM_I2C1_BASE) +/* I2C2 base address */ +#define HPM_I2C2_BASE (0xF0068000UL) +/* I2C2 base pointer */ +#define HPM_I2C2 ((I2C_Type *) HPM_I2C2_BASE) +/* I2C3 base address */ +#define HPM_I2C3_BASE (0xF006C000UL) +/* I2C3 base pointer */ +#define HPM_I2C3 ((I2C_Type *) HPM_I2C3_BASE) + +#include "hpm_spi_regs.h" +/* Address of SPI instances */ +/* SPI0 base address */ +#define HPM_SPI0_BASE (0xF0070000UL) +/* SPI0 base pointer */ +#define HPM_SPI0 ((SPI_Type *) HPM_SPI0_BASE) +/* SPI1 base address */ +#define HPM_SPI1_BASE (0xF0074000UL) +/* SPI1 base pointer */ +#define HPM_SPI1 ((SPI_Type *) HPM_SPI1_BASE) +/* SPI2 base address */ +#define HPM_SPI2_BASE (0xF0078000UL) +/* SPI2 base pointer */ +#define HPM_SPI2 ((SPI_Type *) HPM_SPI2_BASE) +/* SPI3 base address */ +#define HPM_SPI3_BASE (0xF007C000UL) +/* SPI3 base pointer */ +#define HPM_SPI3 ((SPI_Type *) HPM_SPI3_BASE) + +#include "hpm_crc_regs.h" +/* Address of CRC instances */ +/* CRC base address */ +#define HPM_CRC_BASE (0xF0080000UL) +/* CRC base pointer */ +#define HPM_CRC ((CRC_Type *) HPM_CRC_BASE) + +#include "hpm_tsns_regs.h" +/* Address of TSNS instances */ +/* TSNS base address */ +#define HPM_TSNS_BASE (0xF0090000UL) +/* TSNS base pointer */ +#define HPM_TSNS ((TSNS_Type *) HPM_TSNS_BASE) + +#include "hpm_mbx_regs.h" +/* Address of MBX instances */ +/* MBX0A base address */ +#define HPM_MBX0A_BASE (0xF00A0000UL) +/* MBX0A base pointer */ +#define HPM_MBX0A ((MBX_Type *) HPM_MBX0A_BASE) +/* MBX0B base address */ +#define HPM_MBX0B_BASE (0xF00A4000UL) +/* MBX0B base pointer */ +#define HPM_MBX0B ((MBX_Type *) HPM_MBX0B_BASE) + +#include "hpm_ewdg_regs.h" +/* Address of EWDG instances */ +/* EWDG0 base address */ +#define HPM_EWDG0_BASE (0xF00B0000UL) +/* EWDG0 base pointer */ +#define HPM_EWDG0 ((EWDG_Type *) HPM_EWDG0_BASE) +/* EWDG1 base address */ +#define HPM_EWDG1_BASE (0xF00B4000UL) +/* EWDG1 base pointer */ +#define HPM_EWDG1 ((EWDG_Type *) HPM_EWDG1_BASE) +/* PEWDG base address */ +#define HPM_PEWDG_BASE (0xF4128000UL) +/* PEWDG base pointer */ +#define HPM_PEWDG ((EWDG_Type *) HPM_PEWDG_BASE) + +#include "hpm_dmamux_regs.h" +/* Address of DMAMUX instances */ +/* DMAMUX base address */ +#define HPM_DMAMUX_BASE (0xF00C4000UL) +/* DMAMUX base pointer */ +#define HPM_DMAMUX ((DMAMUX_Type *) HPM_DMAMUX_BASE) + +#include "hpm_dmav2_regs.h" +/* Address of DMAV2 instances */ +/* HDMA base address */ +#define HPM_HDMA_BASE (0xF00C8000UL) +/* HDMA base pointer */ +#define HPM_HDMA ((DMAV2_Type *) HPM_HDMA_BASE) + +#include "hpm_gpiom_regs.h" +/* Address of GPIOM instances */ +/* GPIOM base address */ +#define HPM_GPIOM_BASE (0xF00D8000UL) +/* GPIOM base pointer */ +#define HPM_GPIOM ((GPIOM_Type *) HPM_GPIOM_BASE) + +#include "hpm_usb_regs.h" +/* Address of USB instances */ +/* USB0 base address */ +#define HPM_USB0_BASE (0xF300C000UL) +/* USB0 base pointer */ +#define HPM_USB0 ((USB_Type *) HPM_USB0_BASE) + +/* Address of ROMC instances */ +/* ROMC base address */ +#define HPM_ROMC_BASE (0xF3014000UL) + +#include "hpm_sec_regs.h" +/* Address of SEC instances */ +/* SEC base address */ +#define HPM_SEC_BASE (0xF3044000UL) +/* SEC base pointer */ +#define HPM_SEC ((SEC_Type *) HPM_SEC_BASE) + +#include "hpm_mon_regs.h" +/* Address of MON instances */ +/* MON base address */ +#define HPM_MON_BASE (0xF3048000UL) +/* MON base pointer */ +#define HPM_MON ((MON_Type *) HPM_MON_BASE) + +#include "hpm_otp_regs.h" +/* Address of OTP instances */ +/* OTP base address */ +#define HPM_OTP_BASE (0xF3050000UL) +/* OTP base pointer */ +#define HPM_OTP ((OTP_Type *) HPM_OTP_BASE) + +#include "hpm_keym_regs.h" +/* Address of KEYM instances */ +/* KEYM base address */ +#define HPM_KEYM_BASE (0xF3054000UL) +/* KEYM base pointer */ +#define HPM_KEYM ((KEYM_Type *) HPM_KEYM_BASE) + +#include "hpm_adc16_regs.h" +/* Address of ADC16 instances */ +/* ADC0 base address */ +#define HPM_ADC0_BASE (0xF3080000UL) +/* ADC0 base pointer */ +#define HPM_ADC0 ((ADC16_Type *) HPM_ADC0_BASE) + +#include "hpm_acmp_regs.h" +/* Address of ACMP instances */ +/* ACMP base address */ +#define HPM_ACMP_BASE (0xF30B0000UL) +/* ACMP base pointer */ +#define HPM_ACMP ((ACMP_Type *) HPM_ACMP_BASE) + +#include "hpm_sysctl_regs.h" +/* Address of SYSCTL instances */ +/* SYSCTL base address */ +#define HPM_SYSCTL_BASE (0xF4000000UL) +/* SYSCTL base pointer */ +#define HPM_SYSCTL ((SYSCTL_Type *) HPM_SYSCTL_BASE) + +#include "hpm_ioc_regs.h" +/* Address of IOC instances */ +/* IOC base address */ +#define HPM_IOC_BASE (0xF4040000UL) +/* IOC base pointer */ +#define HPM_IOC ((IOC_Type *) HPM_IOC_BASE) +/* PIOC base address */ +#define HPM_PIOC_BASE (0xF4118000UL) +/* PIOC base pointer */ +#define HPM_PIOC ((IOC_Type *) HPM_PIOC_BASE) + +#include "hpm_pllctlv2_regs.h" +/* Address of PLLCTLV2 instances */ +/* PLLCTLV2 base address */ +#define HPM_PLLCTLV2_BASE (0xF40C0000UL) +/* PLLCTLV2 base pointer */ +#define HPM_PLLCTLV2 ((PLLCTLV2_Type *) HPM_PLLCTLV2_BASE) + +#include "hpm_ppor_regs.h" +/* Address of PPOR instances */ +/* PPOR base address */ +#define HPM_PPOR_BASE (0xF4100000UL) +/* PPOR base pointer */ +#define HPM_PPOR ((PPOR_Type *) HPM_PPOR_BASE) + +#include "hpm_pcfg_regs.h" +/* Address of PCFG instances */ +/* PCFG base address */ +#define HPM_PCFG_BASE (0xF4104000UL) +/* PCFG base pointer */ +#define HPM_PCFG ((PCFG_Type *) HPM_PCFG_BASE) + +#include "hpm_pgpr_regs.h" +/* Address of PGPR instances */ +/* PGPR0 base address */ +#define HPM_PGPR0_BASE (0xF4110000UL) +/* PGPR0 base pointer */ +#define HPM_PGPR0 ((PGPR_Type *) HPM_PGPR0_BASE) +/* PGPR1 base address */ +#define HPM_PGPR1_BASE (0xF4114000UL) +/* PGPR1 base pointer */ +#define HPM_PGPR1 ((PGPR_Type *) HPM_PGPR1_BASE) + +#include "hpm_pdgo_regs.h" +/* Address of PDGO instances */ +/* PDGO base address */ +#define HPM_PDGO_BASE (0xF4134000UL) +/* PDGO base pointer */ +#define HPM_PDGO ((PDGO_Type *) HPM_PDGO_BASE) + + +#include "riscv/riscv_core.h" +#include "hpm_csr_regs.h" +#include "hpm_interrupt.h" +#include "hpm_misc.h" +#include "hpm_dmamux_src.h" +#include "hpm_iomux.h" +#include "hpm_pmic_iomux.h" +#endif /* HPM_SOC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_soc_feature.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_soc_feature.h new file mode 100644 index 00000000000..825b6a60ac1 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_soc_feature.h @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_SOC_FEATURE_H +#define HPM_SOC_FEATURE_H + +#include "hpm_soc.h" +#include "hpm_soc_ip_feature.h" + +/* + * PLIC feature + */ +#define PLIC_SUPPORT_EDGE_TRIGGER (1) + +/* + * PMP/PMA Feature + */ +#define PMP_SUPPORT_PMA (0) + +/* + * I2C Section + */ +#define I2C_SOC_FIFO_SIZE (4U) +#define I2C_SOC_TRANSFER_COUNT_MAX (4096U) + +/* + * PMIC Section + */ +#define PCFG_SOC_LDO1P1_MIN_VOLTAGE_IN_MV (700U) +#define PCFG_SOC_LDO1P1_MAX_VOLTAGE_IN_MV (1320U) +#define PCFG_SOC_LDO2P5_MIN_VOLTAGE_IN_MV (2125) +#define PCFG_SOC_LDO2P5_MAX_VOLTAGE_IN_MV (2900U) +#define PCFG_SOC_DCDC_MIN_VOLTAGE_IN_MV (600U) +#define PCFG_SOC_DCDC_MAX_VOLTAGE_IN_MV (1375U) + +/* + * PLLCTL Section + */ +#define PLLCTL_SOC_PLL_MAX_COUNT (2U) +/* PLL reference clock in hz */ +#define PLLCTL_SOC_PLL_REFCLK_FREQ (24U * 1000000UL) +/* only PLL1 and PLL2 have DIV0, DIV1 */ +#define PLLCTL_SOC_PLL_HAS_DIV0(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0) +#define PLLCTL_SOC_PLL_HAS_DIV1(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0) + + +/* + * PWM Section + */ +#define PWM_SOC_PWM_MAX_COUNT (8U) +#define PWM_SOC_CMP_MAX_COUNT (24U) +#define PWM_SOC_OUTPUT_TO_PWM_MAX_COUNT (8U) + +/* + * DMA Section + */ +#define DMA_SOC_TRANSFER_WIDTH_MAX(x) (DMA_TRANSFER_WIDTH_WORD) +#define DMA_SOC_TRANSFER_PER_BURST_MAX(x) (DMA_NUM_TRANSFER_PER_BURST_128T) +#define DMA_SOC_CHANNEL_NUM (32U) +#define DMA_SOC_MAX_COUNT (1U) +#define DMA_SOC_CHN_TO_DMAMUX_CHN(x, n) (DMAMUX_MUXCFG_HDMA_MUX0 + n) +#define DMA_SOC_HAS_IDLE_FLAG (1U) + +/* + * DMAMUX Section + */ +#define DMAMUX_SOC_WRITEONLY (1U) + +/* + * USB Section + */ +#define USB_SOC_MAX_COUNT (1U) + +#define USB_SOC_DCD_QTD_NEXT_INVALID (1U) +#define USB_SOC_DCD_QHD_BUFFER_COUNT (5U) +#define USB_SOC_DCD_MAX_ENDPOINT_COUNT (16U) +#ifndef USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT +#define USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT (8U) +#endif +#define USB_SOC_DCD_MAX_QTD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U * USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT) +#define USB_SOS_DCD_MAX_QHD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U) +#define USB_SOC_DCD_DATA_RAM_ADDRESS_ALIGNMENT (2048U) + +#define USB_SOC_HCD_FRAMELIST_MAX_ELEMENTS (1024U) + +/* + * ADC Section + */ +#define ADC_SOC_IP_VERSION (3U) +#define ADC_SOC_SEQ_MAX_LEN (16U) +#define ADC_SOC_SEQ_HCFG_EN (1U) +#define ADC_SOC_MAX_TRIG_CH_LEN (4U) +#define ADC_SOC_MAX_TRIG_CH_NUM (11U) +#define ADC_SOC_DMA_ADDR_ALIGNMENT (4U) +#define ADC_SOC_CONFIG_INTEN_CHAN_BIT_SIZE (8U) +#define ADC_SOC_BUSMODE_ENABLE_CTRL_SUPPORT (1U) +#define ADC_SOC_PREEMPT_ENABLE_CTRL_SUPPORT (1U) +#define ADC_SOC_SEQ_MAX_DMA_BUFF_LEN_IN_4BYTES (16777216U) +#define ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES (48U) + +#define ADC16_SOC_PARAMS_LEN (34U) +#define ADC16_SOC_MAX_CH_NUM (15U) +#define ADC16_SOC_MAX_SAMPLE_VALUE (65535U) +#define ADC16_SOC_MAX_CONV_CLK_NUM (21U) +#define ADC_SOC_NO_HW_TRIG_SRC (1U) + +/* + * SYSCTL Section + */ +#define SYSCTL_SOC_CPU_GPR_COUNT (14U) +#define SYSCTL_SOC_MONITOR_SLICE_COUNT (4U) + +/* + * PTPC Section + */ +#define PTPC_SOC_TIMER_MAX_COUNT (2U) + +/* + * SDP Section + */ +#define SDP_REGISTER_DESCRIPTOR_COUNT (1U) +#define SDP_HAS_SM3_SUPPORT (1U) +#define SDP_HAS_SM4_SUPPORT (1U) + +/* + * SOC Privilege mdoe + */ +#define SOC_HAS_S_MODE (0U) + +/* + * UART Section + */ +#define UART_SOC_FIFO_SIZE (16U) +#define UART_SOC_OVERSAMPLE_MAX (30U) /* only support 30 oversample rate for rx idle detection */ + +/* + * SPI Section + */ +#define SPI_SOC_TRANSFER_COUNT_MAX (0xFFFFFFFFU) +#define SPI_SOC_FIFO_DEPTH (8U) + +/* + * OTP Section + */ +#define OTP_SOC_UUID_IDX (88U) +#define OTP_SOC_UUID_LEN (16U) /* in bytes */ + +/* + * PWM Section + */ +#define PWM_SOC_HRPWM_SUPPORT (0U) +#define PWM_SOC_SHADOW_TRIG_SUPPORT (0U) +#define PWM_SOC_TIMER_RESET_SUPPORT (1U) + +/* + * TRGM section + */ +#define TRGM_SOC_HAS_FILTER_SHIFT (1U) +#define TRGM_SOC_HAS_DMAMUX_EN (1U) +#define TRGM_SOC_HAS_ADC_MATRIX_SEL (1U) +#define TRGM_SOC_HAS_DAC_MATRIX_SEL (1U) +#define TRGM_SOC_HAS_POS_MATRIX_SEL (1U) + +/* + * MCAN Section + */ +#define MCAN_SOC_MAX_COUNT (0U) +#define MCAN_SOC_MSG_BUF_IN_IP (0U) +#define MCAN_SOC_MSG_BUF_IN_AHB_RAM (1U) +#define CAN_SOC_MAX_COUNT MCAN_SOC_MAX_COUNT + +/* + * EWDG Section + */ +#define EWDG_SOC_CLK_DIV_VAL_MAX (5U) +#define EWDG_SOC_OVERTIME_REG_WIDTH (16U) +#define EWDG_SOC_SUPPORT_TIMEOUT_INTERRUPT (1) +#define EWDG_TIMEOUT_INTERRUPT_REQUIRE_EDGE_TRIGGER (1) + +/* + * Sync Timer + */ +#define SYNT_SOC_HAS_TIMESTAMP (1U) + +/* + * GPIO + */ +#define GPIO_SOC_HAS_EDGE_BOTH_INTERRUPT (1U) + + +#endif /* HPM_SOC_FEATURE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_soc_ip_feature.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_soc_ip_feature.h new file mode 100644 index 00000000000..8ba2c460d08 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_soc_ip_feature.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_SOC_IP_FEATURE_H +#define HPM_SOC_IP_FEATURE_H + +/* UART related feature */ +#define HPM_IP_FEATURE_UART_RX_IDLE_DETECT 1 +#define HPM_IP_FEATURE_UART_FCRR 1 +#define HPM_IP_FEATURE_UART_RX_EN 1 +#define HPM_IP_FEATURE_UART_E00018_FIX 1 +#define HPM_IP_FEATURE_UART_9BIT_MODE 1 +#define HPM_IP_FEATURE_UART_ADDR_MATCH 1 +#define HPM_IP_FEATURE_UART_TRIG_MODE 1 +#define HPM_IP_FEATURE_UART_FINE_FIFO_THRLD 1 +#define HPM_IP_FEATURE_UART_IIR2 1 + +/* I2C related feature */ +#define HPM_IP_FEATURE_I2C_SUPPORT_RESET 1 + +/* SPI related feature */ +#define HPM_IP_FEATURE_SPI_NEW_TRANS_COUNT 1 +#define HPM_IP_FEATURE_SPI_CS_SELECT 1 +#define HPM_IP_FEATURE_SPI_SUPPORT_DIRECTIO 1 + +#endif /* HPM_SOC_IP_FEATURE_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_sysctl_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_sysctl_drv.c new file mode 100644 index 00000000000..fee1b756cde --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_sysctl_drv.c @@ -0,0 +1,290 @@ +/* + * Copyright (c) 2022-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_sysctl_drv.h" +#include "hpm_soc_feature.h" + +#define SYSCTL_RESOURCE_GROUP0 0 + +#define SYSCTL_CPU_RELEASE_KEY(cpu) (0xC0BEF1A9UL | (((cpu) & 1) << 24)) + +static inline bool sysctl_valid_cpu_index(uint8_t cpu) +{ + if (cpu != SYSCTL_CPU_CPU0) { + return false; + } + return true; +} + +hpm_stat_t sysctl_get_cpu_gpr(SYSCTL_Type *ptr, uint8_t cpu, uint32_t *data, uint32_t size) +{ + uint32_t i; + if ((!sysctl_valid_cpu_index(cpu)) || (size > ARRAY_SIZE(ptr->CPU[cpu].GPR))) { + return status_invalid_argument; + } + for (i = 0; i < size; i++) { + *(data + i) = ptr->CPU[cpu].GPR[i]; + } + return status_success; +} + +static hpm_stat_t _sysctl_cpu_get_gpr(SYSCTL_Type *ptr, uint8_t cpu, uint8_t start, uint8_t count, uint32_t *data) +{ + uint8_t i, size = ARRAY_SIZE(ptr->CPU[cpu].GPR); + if (!sysctl_valid_cpu_index(cpu) || (data == NULL) || !count || start > size || count > size || + (start + count) > size) { + return status_invalid_argument; + } + for (i = 0; i < count; i++) { + *(data + i) = ptr->CPU[cpu].GPR[start + i]; + } + return status_success; +} + +hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data) +{ + return _sysctl_cpu_get_gpr(ptr, 0, start, count, data); +} + +hpm_stat_t sysctl_cpu1_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data) +{ + return _sysctl_cpu_get_gpr(ptr, 1, start, count, data); +} + +static hpm_stat_t _sysctl_cpu_set_gpr(SYSCTL_Type *ptr, uint8_t cpu, uint8_t start, uint8_t count, const uint32_t *data) +{ + uint8_t i, size = ARRAY_SIZE(ptr->CPU[cpu].GPR); + if (!sysctl_valid_cpu_index(cpu) || (data == NULL) || !count || start > size || count > size || + (start + count) > size) { + return status_invalid_argument; + } + for (i = 0; i < count; i++) { + ptr->CPU[cpu].GPR[start + i] = *(data + i); + } + return status_success; +} + +hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock) +{ + hpm_stat_t stat = status_success; + uint16_t gpr_mask; + stat = _sysctl_cpu_set_gpr(ptr, 0, start, count, data); + if (stat != status_success) { + return stat; + } + if (lock) { + gpr_mask = ((1 << count) - 1) << start; + sysctl_cpu0_lock_gpr_with_mask(ptr, gpr_mask); + } + return stat; +} + +void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config) +{ + (void) ptr; + config->mode = monitor_work_mode_record; + config->accuracy = monitor_accuracy_1khz; + config->reference = monitor_reference_24mhz; + config->divide_by = 1; + config->high_limit = 0; + config->low_limit = 0; + config->start_measure = true; + config->enable_output = false; + config->target = monitor_target_clk_top_cpu0; +} + +void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config_t *config) +{ + ptr->MONITOR[monitor_index].CONTROL &= ~(SYSCTL_MONITOR_CONTROL_START_MASK | SYSCTL_MONITOR_CONTROL_OUTEN_MASK); + + if (config->mode == monitor_work_mode_compare) { + ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(config->high_limit); + ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(config->low_limit); + } + + ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL & + ~(SYSCTL_MONITOR_CONTROL_DIV_MASK | SYSCTL_MONITOR_CONTROL_MODE_MASK | SYSCTL_MONITOR_CONTROL_ACCURACY_MASK | + SYSCTL_MONITOR_CONTROL_REFERENCE_MASK | SYSCTL_MONITOR_CONTROL_SELECTION_MASK)) | + (SYSCTL_MONITOR_CONTROL_DIV_SET(config->divide_by - 1) | SYSCTL_MONITOR_CONTROL_MODE_SET(config->mode) | + SYSCTL_MONITOR_CONTROL_ACCURACY_SET(config->accuracy) | + SYSCTL_MONITOR_CONTROL_REFERENCE_SET(config->reference) | + SYSCTL_MONITOR_CONTROL_START_SET(config->start_measure) | + SYSCTL_MONITOR_CONTROL_OUTEN_SET(config->enable_output) | + SYSCTL_MONITOR_CONTROL_SELECTION_SET(config->target)); +} + +uint32_t sysctl_monitor_measure_frequency(SYSCTL_Type *ptr, + uint8_t monitor_index, + monitor_target_t target, + bool enable_output) +{ + uint32_t frequency = 0; + monitor_config_t monitor = { 0 }; + sysctl_monitor_get_default_config(ptr, &monitor); + monitor.target = target; + monitor.enable_output = enable_output; + sysctl_monitor_init(ptr, monitor_index, &monitor); + if (monitor_index < SYSCTL_SOC_MONITOR_SLICE_COUNT) { + frequency = sysctl_monitor_get_current_result(ptr, monitor_index); + } + return frequency; +} + +hpm_stat_t sysctl_set_cpu_entry(SYSCTL_Type *ptr, uint8_t cpu, uint32_t entry) +{ + if (!sysctl_valid_cpu_index(cpu)) { + return status_invalid_argument; + } + ptr->CPU[cpu].GPR[0] = entry; + ptr->CPU[cpu].GPR[1] = SYSCTL_CPU_RELEASE_KEY(cpu); + return status_success; +} + +hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry) +{ + return sysctl_set_cpu_entry(ptr, 0, entry); +} + +hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, + uint8_t group, + sysctl_resource_t resource, + bool enable) +{ + uint32_t index, offset; + if (resource < sysctl_resource_linkable_start) { + return status_invalid_argument; + } + + index = (resource - sysctl_resource_linkable_start) / 32; + offset = (resource - sysctl_resource_linkable_start) % 32; + switch (group) { + case SYSCTL_RESOURCE_GROUP0: + ptr->GROUP0[index].VALUE = (ptr->GROUP0[index].VALUE & ~(1UL << offset)) | (enable ? (1UL << offset) : 0); + if (enable) { + while (sysctl_resource_target_is_busy(ptr, resource)) { + ; + } + } + break; + default: + return status_invalid_argument; + } + + return status_success; +} + +bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, + uint8_t group, + sysctl_resource_t resource) +{ + uint32_t index, offset; + bool enable; + + index = (resource - sysctl_resource_linkable_start) / 32; + offset = (resource - sysctl_resource_linkable_start) % 32; + switch (group) { + case SYSCTL_RESOURCE_GROUP0: + enable = ((ptr->GROUP0[index].VALUE & (1UL << offset)) != 0) ? true : false; + break; + default: + enable = false; + break; + } + + return enable; +} + +uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index) +{ + uint32_t value; + switch (group) { + case SYSCTL_RESOURCE_GROUP0: + value = ptr->GROUP0[index].VALUE; + break; + default: + value = 0; + break; + } + return value; +} + +hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) +{ + return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, true); +} + +hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) +{ + return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, false); +} + +hpm_stat_t sysctl_update_divider(SYSCTL_Type *ptr, clock_node_t node, uint32_t divide_by) +{ + if (node >= clock_node_adc_start) { + return status_invalid_argument; + } + + ptr->CLOCK[node] = (ptr->CLOCK[node] & ~(SYSCTL_CLOCK_DIV_MASK)) | SYSCTL_CLOCK_DIV_SET(divide_by - 1); + while (sysctl_clock_target_is_busy(ptr, node)) { + } + return status_success; +} + +hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node, clock_source_t source, uint32_t divide_by) +{ + if (node >= clock_node_adc_start) { + return status_invalid_argument; + } + + if (source >= clock_source_general_source_end) { + return status_invalid_argument; + } + ptr->CLOCK[node] = (ptr->CLOCK[node] & ~(SYSCTL_CLOCK_MUX_MASK | SYSCTL_CLOCK_DIV_MASK)) | + (SYSCTL_CLOCK_MUX_SET(source) | SYSCTL_CLOCK_DIV_SET(divide_by - 1)); + while (sysctl_clock_target_is_busy(ptr, node)) { + } + return status_success; +} + +hpm_stat_t sysctl_config_cpu0_domain_clock(SYSCTL_Type *ptr, + clock_source_t source, + uint32_t cpu_div, + uint32_t ahb_sub_div) +{ + if (source >= clock_source_general_source_end) { + return status_invalid_argument; + } + + uint32_t origin_cpu_div = SYSCTL_CLOCK_CPU_DIV_GET(ptr->CLOCK_CPU[0]) + 1U; + if (origin_cpu_div == cpu_div) { + ptr->CLOCK_CPU[0] = SYSCTL_CLOCK_CPU_MUX_SET(source) | SYSCTL_CLOCK_CPU_DIV_SET(cpu_div) | SYSCTL_CLOCK_CPU_SUB0_DIV_SET(ahb_sub_div - 1); + while (sysctl_cpu_clock_any_is_busy(ptr)) { + } + } + ptr->CLOCK_CPU[0] = SYSCTL_CLOCK_CPU_MUX_SET(source) | SYSCTL_CLOCK_CPU_DIV_SET(cpu_div - 1) | SYSCTL_CLOCK_CPU_SUB0_DIV_SET(ahb_sub_div - 1); + + while (sysctl_cpu_clock_any_is_busy(ptr)) { + } + + return status_success; +} + +hpm_stat_t sysctl_set_adc_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_adc_t source) +{ + if (source >= clock_source_adc_clk_end) { + return status_invalid_argument; + } + uint32_t adc_index = (uint32_t) (node - clock_node_adc_start); + if (adc_index >= ARRAY_SIZE(ptr->ADCCLK)) { + return status_invalid_argument; + } + + ptr->ADCCLK[adc_index] = (ptr->ADCCLK[adc_index] & ~SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(source); + + return status_success; +} + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_sysctl_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_sysctl_drv.h new file mode 100644 index 00000000000..591602d8a10 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_sysctl_drv.h @@ -0,0 +1,1175 @@ +/** + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_SYSCTL_DRV_H +#define HPM_SYSCTL_DRV_H + +#include "hpm_common.h" +#include "hpm_sysctl_regs.h" + +/** + * + * @brief SYSCTL driver APIs + * @defgroup sysctl_interface SYSCTL driver APIs + * @ingroup io_interfaces + * @{ + */ + +/** + * @brief Retention domains + */typedef enum { + sysctl_retention_domain_sys = 0, + sysctl_retention_domain_cpu0 = 2, + + sysctl_retention_domain_xtal24m = 4, + sysctl_retention_domain_pll0 = 5, + sysctl_retention_domain_pll1 = 6, +} sysctl_retention_domain_t; + +/** + * @brief Clock presets + */ +typedef enum { + sysctl_preset_0 = 1 << 0, + sysctl_preset_1 = 1 << 1, + sysctl_preset_2 = 1 << 2, + sysctl_preset_3 = 1 << 3, +} sysctl_preset_t; + +/** + * @brief Reset domains + */ +typedef enum { + sysctl_reset_domain_soc = 0, + sysctl_reset_domain_cpu0, +} sysctl_reset_domain_t; + +/** + * @brief Resource + */ +typedef enum { + sysctl_resource_cpu0 = 0, + sysctl_resource_cpx0 = 1, + sysctl_resource_pow_cpu0 = 21, + sysctl_resource_rst_soc = 22, + sysctl_resource_rst_cpu0 = 23, + sysctl_resource_xtal = 32, + sysctl_resource_pll0 = 33, + sysctl_resource_clk0_pll0 = 34, + sysctl_resource_clk1_pll0 = 35, + sysctl_resource_clk2_pll0 = 36, + sysctl_resource_pll1 = 37, + sysctl_resource_clk0_pll1 = 38, + sysctl_resource_clk1_pll1 = 39, + sysctl_resource_clk2_pll1 = 40, + sysctl_resource_clk3_pll1 = 41, + sysctl_resource_pll0_ref = 42, + sysctl_resource_pll1_ref = 43, + sysctl_resource_clk_top_cpu0 = 64, + sysctl_resource_clk_top_mchtmr0 = 65, + sysctl_resource_clk_top_gptmr0 = 74, + sysctl_resource_clk_top_gptmr1 = 75, + sysctl_resource_clk_top_i2c0 = 78, + sysctl_resource_clk_top_i2c1 = 79, + sysctl_resource_clk_top_i2c2 = 80, + sysctl_resource_clk_top_i2c3 = 81, + sysctl_resource_clk_top_spi0 = 82, + sysctl_resource_clk_top_spi1 = 83, + sysctl_resource_clk_top_spi2 = 84, + sysctl_resource_clk_top_spi3 = 85, + sysctl_resource_clk_top_uart0 = 86, + sysctl_resource_clk_top_uart1 = 87, + sysctl_resource_clk_top_uart2 = 88, + sysctl_resource_clk_top_uart3 = 89, + sysctl_resource_clk_top_uart4 = 90, + sysctl_resource_clk_top_xip0 = 94, + sysctl_resource_clk_top_ana0 = 95, + sysctl_resource_clk_top_ana1 = 96, + sysctl_resource_clk_top_ana2 = 97, + sysctl_resource_clk_top_ana3 = 98, + sysctl_resource_clk_top_ref0 = 99, + sysctl_resource_clk_top_ref1 = 100, + sysctl_resource_clk_top_adc0 = 101, + + sysctl_resource_linkable_start = 256, + sysctl_resource_ahb0 = 256, + sysctl_resource_lmm0 = 257, + sysctl_resource_mchtmr0 = 258, + sysctl_resource_rom0 = 259, + sysctl_resource_ptpc = 264, + sysctl_resource_gptmr0 = 269, + sysctl_resource_gptmr1 = 270, + sysctl_resource_i2c0 = 273, + sysctl_resource_i2c1 = 274, + sysctl_resource_i2c2 = 275, + sysctl_resource_i2c3 = 276, + sysctl_resource_spi0 = 277, + sysctl_resource_spi1 = 278, + sysctl_resource_spi2 = 279, + sysctl_resource_spi3 = 280, + sysctl_resource_uart0 = 281, + sysctl_resource_uart1 = 282, + sysctl_resource_uart2 = 283, + sysctl_resource_uart3 = 284, + sysctl_resource_uart4 = 285, + sysctl_resource_wdg0 = 289, + sysctl_resource_wdg1 = 290, + sysctl_resource_mbx0 = 291, + sysctl_resource_tsns = 292, + sysctl_resource_crc0 = 293, + sysctl_resource_adc0 = 294, + sysctl_resource_acmp = 298, + sysctl_resource_kman = 304, + sysctl_resource_gpio = 305, + sysctl_resource_hdma = 306, + sysctl_resource_xpi0 = 307, + sysctl_resource_usb0 = 308, + sysctl_resource_ref0 = 309, + sysctl_resource_ref1 = 310, + sysctl_resource_linkable_end, + sysctl_resource_end = sysctl_resource_linkable_end, +} sysctl_resource_t; + +/** + * @brief Resource modes + */ +typedef enum { + sysctl_resource_mode_auto = 0, /*!< Resource clock is automatically managed by system request */ + sysctl_resource_mode_force_on, /*!< Force the resource clock on */ + sysctl_resource_mode_force_off, /*!< Force the resource clock off */ +} sysctl_resource_mode_t; + +/** + * @brief Clock nodes + */ +typedef enum { + clock_node_mchtmr0 = SYSCTL_CLOCK_CLK_TOP_MCT0, + clock_node_gptmr0 = SYSCTL_CLOCK_CLK_TOP_TMR0, + clock_node_gptmr1 = SYSCTL_CLOCK_CLK_TOP_TMR1, + clock_node_i2c0 = SYSCTL_CLOCK_CLK_TOP_I2C0, + clock_node_i2c1 = SYSCTL_CLOCK_CLK_TOP_I2C1, + clock_node_i2c2 = SYSCTL_CLOCK_CLK_TOP_I2C2, + clock_node_i2c3 = SYSCTL_CLOCK_CLK_TOP_I2C3, + clock_node_spi0 = SYSCTL_CLOCK_CLK_TOP_SPI0, + clock_node_spi1 = SYSCTL_CLOCK_CLK_TOP_SPI1, + clock_node_spi2 = SYSCTL_CLOCK_CLK_TOP_SPI2, + clock_node_spi3 = SYSCTL_CLOCK_CLK_TOP_SPI3, + clock_node_uart0 = SYSCTL_CLOCK_CLK_TOP_URT0, + clock_node_uart1 = SYSCTL_CLOCK_CLK_TOP_URT1, + clock_node_uart2 = SYSCTL_CLOCK_CLK_TOP_URT2, + clock_node_uart3 = SYSCTL_CLOCK_CLK_TOP_URT3, + clock_node_uart4 = SYSCTL_CLOCK_CLK_TOP_URT4, + clock_node_xpi0 = SYSCTL_CLOCK_CLK_TOP_XPI0, + clock_node_ana0 = SYSCTL_CLOCK_CLK_TOP_ANA0, + clock_node_ana1 = SYSCTL_CLOCK_CLK_TOP_ANA1, + clock_node_ana2 = SYSCTL_CLOCK_CLK_TOP_ANA2, + clock_node_ana3 = SYSCTL_CLOCK_CLK_TOP_ANA3, + clock_node_ref0 = SYSCTL_CLOCK_CLK_TOP_REF0, + clock_node_ref1 = SYSCTL_CLOCK_CLK_TOP_REF1, + + clock_node_adc_start, + clock_node_adc0 = clock_node_adc_start, + clock_node_adc1, + + clock_node_dac_start, + clock_node_dac0 = clock_node_dac_start, + clock_node_dac1, + clock_node_end, + + clock_node_core_start = 0xfc, + clock_node_cpu0 = clock_node_core_start, + clock_node_axi, + clock_node_ahb, +} clock_node_t; + +/** + * @brief General clock sources + */ +typedef enum { + clock_source_osc0_clk0 = 0, + clock_source_pll0_clk0 = 1, + clock_source_pll0_clk1 = 2, + clock_source_pll0_clk2 = 3, + clock_source_pll1_clk0 = 4, + clock_source_pll1_clk1 = 5, + clock_source_pll1_clk2 = 6, + clock_source_pll1_clk3 = 7, + clock_source_general_source_end, +} clock_source_t; + +/** + * @brief ADC/I2S clock sources + */ +typedef enum { + clock_source_adc_ana_clock = 0, + clock_source_adc_ahb_clock = 1, + clock_source_adc_clk_end, +} clock_source_adc_t; + +/** + * @brief CPU low power mode + */ +typedef enum { + cpu_lp_mode_gate_cpu_clock = 0, + cpu_lp_mode_trigger_system_lp = 0x1, + cpu_lp_mode_ungate_cpu_clock = 0x2, +} cpu_lp_mode_t; + +/** + * @brief Monitor targets + */ +typedef enum { + monitor_target_clk_32k = 1, + monitor_target_clk_irc24m = 2, + monitor_target_clk_xtal_24m = 3, + monitor_target_clk_usb0_phy = 4, + monitor_target_clk0_osc0 = 20, + monitor_target_clk0_pll0 = 21, + monitor_target_clk0_pll1 = 22, + monitor_target_clk0_pll2 = 23, + monitor_target_clk1_pll0 = 24, + monitor_target_clk1_pll1 = 25, + monitor_target_clk1_pll2 = 26, + monitor_target_clk1_pll3 = 27, + monitor_target_clk_top_cpu0 = 128, + monitor_target_clk_top_mchtmr0 = 129, + monitor_target_clk_top_gptmr0 = 138, + monitor_target_clk_top_gptmr1 = 139, + monitor_target_clk_top_i2c0 = 142, + monitor_target_clk_top_i2c1 = 143, + monitor_target_clk_top_i2c2 = 144, + monitor_target_clk_top_i2c3 = 145, + monitor_target_clk_top_spi0 = 146, + monitor_target_clk_top_spi1 = 147, + monitor_target_clk_top_spi2 = 148, + monitor_target_clk_top_spi3 = 149, + monitor_target_clk_top_uart0 = 150, + monitor_target_clk_top_uart1 = 151, + monitor_target_clk_top_uart2 = 152, + monitor_target_clk_top_uart3 = 153, + monitor_target_clk_top_uart4 = 154, + monitor_target_clk_top_xpi0 = 158, + monitor_target_clk_top_ana0 = 159, + monitor_target_clk_top_ana1 = 160, + monitor_target_clk_top_ana2 = 161, + monitor_target_clk_top_ana3 = 162, + monitor_target_clk_top_ref0 = 163, + monitor_target_clk_top_ref1 = 164, +} monitor_target_t; + +/** + * @brief Monitor work mode + */ +typedef enum { + monitor_work_mode_compare = 0, + monitor_work_mode_record = 1, +} monitor_work_mode_t; + +/** + * @brief Monitor accuracy + */ +typedef enum { + monitor_accuracy_1khz = 0, + monitor_accuracy_1hz = 1, +} monitor_accuracy_t; + +/** + * @brief Monitor reference clock source + */ +typedef enum { + monitor_reference_32khz = 0, + monitor_reference_24mhz = 1, +} monitor_reference_t; + +typedef enum { + cpu_event_flag_mask_reset = SYSCTL_CPU_LP_RESET_FLAG_MASK, + cpu_event_flag_mask_sleep = SYSCTL_CPU_LP_SLEEP_FLAG_MASK, + cpu_event_flag_mask_wake = SYSCTL_CPU_LP_WAKE_FLAG_MASK, + cpu_event_flag_mask_all = SYSCTL_CPU_LP_RESET_FLAG_MASK | SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK, +} cpu_event_flag_mask_t; + +/** + * @brief Monitor config + */ +typedef struct monitor_config { + uint8_t divide_by; /**< Divider to be used for OBS output to pads */ + monitor_work_mode_t mode; /**< Monitor work mode */ + monitor_accuracy_t accuracy; /**< Monitor reference accuracy */ + monitor_reference_t reference; /**< Monitor reference clock source */ + monitor_target_t target; /**< Monitor target */ + bool start_measure; /**< Start flag */ + bool enable_output; /**< Enable output to pads if true */ + uint32_t high_limit; /**< Maximum frequency at compare mode */ + uint32_t low_limit; /**< Minimum frequency at compare mode */ +} monitor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Check if monitor result is valid + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * + * @return true if it is valid + */ +static inline bool sysctl_monitor_result_is_valid(SYSCTL_Type *ptr, uint8_t monitor_index) +{ + return SYSCTL_MONITOR_CONTROL_VALID_GET(ptr->MONITOR[monitor_index].CONTROL); +} + +/** + * @brief Get target monitor instance result + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @return value of monitor result measured + */ +static inline uint32_t sysctl_monitor_get_current_result(SYSCTL_Type *ptr, uint8_t monitor_index) +{ + while (!sysctl_monitor_result_is_valid(ptr, monitor_index)) { + } + return ptr->MONITOR[monitor_index].CURRENT; +} + +/** + * @brief Set work mode for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] mode monitor_work_mode_compare, monitor_work_mode_record + */ +static inline void sysctl_monitor_set_work_mode(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_work_mode_t mode) +{ + ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL & ~SYSCTL_MONITOR_CONTROL_MODE_MASK) | + (SYSCTL_MONITOR_CONTROL_MODE_SET(mode)); +} + +/** + * @brief Set minimum frequency for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] limit measurement low limit + */ +static inline hpm_stat_t sysctl_monitor_set_limit_low(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit) +{ + if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { + return status_invalid_argument; + } + ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit); + return status_success; +} + +/** + * @brief Set maximum frequency for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] limit measurement high limit + */ +static inline hpm_stat_t sysctl_monitor_set_limit_high(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit) +{ + if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { + return status_invalid_argument; + } + ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit); + return status_success; +} + +/** + * @brief Set frequency limit for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] limit_high measurement high limit + * @param[in] limit_low measurement low limit + */ +static inline hpm_stat_t sysctl_monitor_set_limit(SYSCTL_Type *ptr, + uint8_t monitor_index, + uint32_t limit_high, + uint32_t limit_low) +{ + if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { + return status_invalid_argument; + } + ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit_high); + ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit_low); + return status_success; +} + +/** + * @brief Get maximum frequency for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @return current high limit value + */ +static inline uint32_t sysctl_monitor_get_limit_high(SYSCTL_Type *ptr, uint32_t monitor_index) +{ + return SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(ptr->MONITOR[monitor_index].HIGH_LIMIT); +} + +/** + * @brief Get minimum frequency for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @return current low limit value + */ +static inline uint32_t sysctl_monitor_get_limit_low(SYSCTL_Type *ptr, uint32_t monitor_index) +{ + return SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(ptr->MONITOR[monitor_index].LOW_LIMIT); +} + +/** + * @brief Measure specific target frequency + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] target monitor target to be measured + * @param[in] enable_output enable clock obs output + * @return frequency of monitor target measured + */ +uint32_t sysctl_monitor_measure_frequency(SYSCTL_Type *ptr, + uint8_t monitor_index, + monitor_target_t target, + bool enable_output); + +/** + * @brief Link current CPU core its own group + * + * Once it is linked, peripherals state in that group will keep on as long as this core is not in low power mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index to enable its own affiliated group + */ +static inline void sysctl_set_enable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + ptr->AFFILIATE[cpu_index].SET = 1 << cpu_index; +} + +/** + * @brief Unlink current CPU core with its own group + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index to enable its own affiliated group + */ +static inline void sysctl_set_disable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + ptr->AFFILIATE[cpu_index].CLEAR = 1 << cpu_index; +} + +/** + * @brief Check if any resource is busy + * + * @param[in] ptr SYSCTL_Type base address + * @return true if any resource is busy + */ +static inline bool sysctl_resource_any_is_busy(SYSCTL_Type *ptr) +{ + return ptr->RESOURCE[0] & SYSCTL_RESOURCE_GLB_BUSY_MASK; +} + +/** + * @brief Check if specific target is busy + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource target resource index + * @return true if target resource is busy + */ +static inline bool sysctl_resource_target_is_busy(SYSCTL_Type *ptr, sysctl_resource_t resource) +{ + return ptr->RESOURCE[resource] & SYSCTL_RESOURCE_LOC_BUSY_MASK; +} + +/** + * @brief Set target mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource target resource index + * @param[in] mode target resource mode + */ +static inline void sysctl_resource_target_set_mode(SYSCTL_Type *ptr, + sysctl_resource_t resource, + sysctl_resource_mode_t mode) +{ + ptr->RESOURCE[resource] = + (ptr->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | + SYSCTL_RESOURCE_MODE_SET(mode); +} + +/** + * @brief Get target mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource target resource index + * @return target resource mode + */ +static inline uint8_t sysctl_resource_target_get_mode(SYSCTL_Type *ptr, + sysctl_resource_t resource) +{ + return SYSCTL_RESOURCE_MODE_GET(ptr->RESOURCE[resource]); +} + +/** + * @brief Disable resource retention when specific CPU enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index + * @param[in] mask bit mask to clear + */ +static inline void sysctl_clear_cpu_lp_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask) +{ + ptr->RETENTION[cpu_index].CLEAR = mask; +} + +/** + * @brief Disable resource retention when CPU0 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mask bit mask to clear + */ +static inline void sysctl_clear_cpu0_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask) +{ + sysctl_clear_cpu_lp_retention_with_mask(ptr, 0, mask); +} + +/** + * @brief Enable resource retention when specific CPU enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index + * @param[in] mask bit mask to set + */ +static inline void sysctl_set_cpu_lp_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask) +{ + ptr->RETENTION[cpu_index].SET = mask; +} + +/** + * @brief Enable resource retention when CPU0 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mask bit mask to set + */ +static inline void sysctl_set_cpu0_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask) +{ + sysctl_set_cpu_lp_retention_with_mask(ptr, 0, mask); +} + +/** + * @brief Enable resource retention when CPU1 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mask bit mask to set + */ +static inline void sysctl_set_cpu1_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask) +{ + sysctl_set_cpu_lp_retention_with_mask(ptr, 1, mask); +} + +/** + * @brief Enable resource retention when specific CPU enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index + * @param[in] value value to be set + */ +static inline void sysctl_set_cpu_lp_retention(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t value) +{ + ptr->RETENTION[cpu_index].VALUE = value; +} + +/** + * @brief Enable resource retention when CPU0 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] value value to be set + */ +static inline void sysctl_set_cpu0_lp_retention(SYSCTL_Type *ptr, uint32_t value) +{ + sysctl_set_cpu_lp_retention(ptr, 0, value); +} + +/** + * @brief Retain target domain for specific CPU + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] domain target domain power to be retained + * @param[in] retain_mem set true to retain memory/register of target domain + */ +static inline void sysctl_set_cpu_lp_retain_domain(SYSCTL_Type *ptr, + uint8_t cpu_index, + sysctl_retention_domain_t domain, + bool retain_mem) +{ + uint8_t set_mask = 0x1; + if (domain < sysctl_retention_domain_xtal24m) { + set_mask = retain_mem ? 0x3 : 0x1; + } + ptr->RETENTION[cpu_index].SET = (set_mask << domain); +} + +/** + * @brief Retain target domain for specific CPU0 + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain power to be retained + * @param[in] retain_mem set true to retain memory/register of target domain + */ +static inline void sysctl_set_cpu0_lp_retain_domain(SYSCTL_Type *ptr, + sysctl_retention_domain_t domain, + bool retain_mem) +{ + sysctl_set_cpu_lp_retain_domain(ptr, 0, domain, retain_mem); +} + +/** + * @brief Check if cpu clock is busy + * + * @param[in] ptr SYSCTL_Type base address + * @return true if any clock is busy + */ +static inline bool sysctl_cpu_clock_any_is_busy(SYSCTL_Type *ptr) +{ + return ptr->CLOCK_CPU[0] & SYSCTL_CLOCK_CPU_GLB_BUSY_MASK; +} + +/** + * @brief Check if any clock is busy + * + * @param[in] ptr SYSCTL_Type base address + * @return true if any clock is busy + */ +static inline bool sysctl_clock_any_is_busy(SYSCTL_Type *ptr) +{ + return ptr->CLOCK[0] & SYSCTL_CLOCK_GLB_BUSY_MASK; +} + +/** + * @brief Check if target clock is busy + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] clock target clock + * @return true if target clock is busy + */ +static inline bool sysctl_clock_target_is_busy(SYSCTL_Type *ptr, clock_node_t clock) +{ + return ptr->CLOCK[clock] & SYSCTL_CLOCK_LOC_BUSY_MASK; +} + +/** + * @brief Preserve clock setting for certain node + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] clock target clock + */ +static inline void sysctl_clock_preserve_settings(SYSCTL_Type *ptr, clock_node_t clock) +{ + ptr->CLOCK[clock] |= SYSCTL_CLOCK_PRESERVE_MASK; +} + +/** + * @brief Unpreserve clock setting for certain node + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] clock target clock + */ +static inline void sysctl_clock_unpreserve_settings(SYSCTL_Type *ptr, clock_node_t clock) +{ + ptr->CLOCK[clock] &= ~SYSCTL_CLOCK_PRESERVE_MASK; +} + +/** + * @brief Set clock preset + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] preset preset + */ +static inline void sysctl_clock_set_preset(SYSCTL_Type *ptr, sysctl_preset_t preset) +{ + ptr->GLOBAL00 = (ptr->GLOBAL00 & ~SYSCTL_GLOBAL00_MUX_MASK) | SYSCTL_GLOBAL00_MUX_SET(preset); +} + +/** + * @brief Check if target reset domain wakeup status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + * @return true if target domain was taken wakeup reset + */ +static inline bool sysctl_reset_check_target_domain_wakeup_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; +} + +/** + * @brief Clear target reset domain wakeup status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + */ +static inline void sysctl_reset_clear_target_domain_wakeup_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; +} + +/** + * @brief Clear target reset domain reset status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + * @return true if target domain was taken reset + */ +static inline bool sysctl_reset_check_target_domain_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_MASK; +} + +/** + * @brief Clear target reset domain reset status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + */ +static inline void sysctl_reset_clear_target_domain_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK; +} + +/** + * @brief Clear target reset domain for all reset status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + */ +static inline void sysctl_reset_clear_target_domain_all_flags(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK | SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; +} + +/** + * @brief Get target CPU wakeup source status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] status_index wakeup status index 0 - 7 + * @return wakeup source status mask + */ +static inline uint32_t sysctl_get_wakeup_source_status(SYSCTL_Type *ptr, uint8_t cpu_index, uint8_t status_index) +{ + return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index]; +} + +/** + * @brief Get target CPU0 wakeup source status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] status_index wakeup status index 0 - 7 + * @return wakeup source status mask + */ +static inline uint32_t sysctl_get_cpu0_wakeup_source_status(SYSCTL_Type *ptr, uint8_t status_index) +{ + return sysctl_get_wakeup_source_status(ptr, 0, status_index); +} + +/** + * @brief Check wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] status_index wakeup status index 0 - 7 + * @param[in] mask expected status mask + * @return wakeup status according to given bit mask + */ +static inline uint32_t sysctl_check_wakeup_source_status_with_mask(SYSCTL_Type *ptr, + uint8_t cpu_index, + uint8_t status_index, + uint32_t mask) +{ + return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index] & mask; +} + +/** + * @brief Check CPU0 wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] status_index wakeup status index 0 - 7 + * @param[in] mask expected status mask + * @return wakeup status according to given bit mask + */ +static inline uint32_t sysctl_check_cpu0_wakeup_source_status_with_mask(SYSCTL_Type *ptr, + uint8_t status_index, + uint32_t mask) +{ + return sysctl_check_wakeup_source_status_with_mask(ptr, 0, status_index, mask); +} + +/** + * @brief Enable wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void sysctl_enable_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t cpu_index, + uint8_t enable_index, + uint32_t mask) +{ + ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] |= mask; +} + +/** + * @brief Enable CPU0 wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void sysctl_enable_cpu0_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t enable_index, + uint32_t mask) +{ + ptr->CPU[0].WAKEUP_ENABLE[enable_index] |= mask; +} + +/** + * @brief Disable wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void sysctl_disable_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t cpu_index, + uint8_t enable_index, + uint32_t mask) +{ + ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] &= ~mask; +} + +/** + * @brief Disable CPU0 wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void sysctl_disable_cpu0_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t enable_index, + uint32_t mask) +{ + sysctl_disable_wakeup_source_with_mask(ptr, 0, enable_index, mask); +} + +/** + * @brief Disable wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] irq_num irq number to be set as wakeup source + */ +static inline void sysctl_disable_wakeup_source_with_irq(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t irq_num) +{ + ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num >> 2] &= ~(1UL << (irq_num % 32)); +} + +/** + * @brief Disable CPU0 wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] irq_num irq number to be disabled as wakeup source + */ +static inline void sysctl_disable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr, + uint16_t irq_num) +{ + sysctl_disable_wakeup_source_with_irq(ptr, 0, irq_num); +} + + +/** + * @brief Enable wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] irq_num irq number to be set as wakeup source + */ +static inline void sysctl_enable_wakeup_source_with_irq(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t irq_num) +{ + ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num / 32] |= 1UL << (irq_num & 0x1F); +} + +/** + * @brief Enable CPU0 wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] irq_num irq number to be set as wakeup source + */ +static inline void sysctl_enable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr, uint16_t irq_num) +{ + sysctl_enable_wakeup_source_with_irq(ptr, 0, irq_num); +} + +/** + * @brief Lock CPU gpr with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] gpr_mask bit mask of gpr registers to be locked + */ +static inline void sysctl_cpu_lock_gpr_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t gpr_mask) +{ + ptr->CPU[cpu_index].LOCK |= SYSCTL_CPU_LOCK_GPR_SET(gpr_mask); +} + + +/** + * @brief Lock CPU0 gpr with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] gpr_mask bit mask of gpr registers to be locked + */ +static inline void sysctl_cpu0_lock_gpr_with_mask(SYSCTL_Type *ptr, uint16_t gpr_mask) +{ + sysctl_cpu_lock_gpr_with_mask(ptr, 0, gpr_mask); +} + +/** + * @brief Lock CPU lock + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + */ +static inline void sysctl_cpu_lock(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + ptr->CPU[cpu_index].LOCK |= SYSCTL_CPU_LOCK_LOCK_MASK; +} + +/** + * @brief Lock CPU0 lock + * + * @param[in] ptr SYSCTL_Type base address + */ +static inline void sysctl_cpu0_lock(SYSCTL_Type *ptr) +{ + sysctl_cpu_lock(ptr, 0); +} + +/** + * @brief Set CPU low power mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] mode target mode to set + */ +static inline void sysctl_set_cpu_lp_mode(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_lp_mode_t mode) +{ + ptr->CPU[cpu_index].LP = (ptr->CPU[cpu_index].LP & ~(SYSCTL_CPU_LP_MODE_MASK)) | (mode); +} + +/** + * @brief Set CPU0 low power mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mode target mode to set + */ +static inline void sysctl_set_cpu0_lp_mode(SYSCTL_Type *ptr, cpu_lp_mode_t mode) +{ + sysctl_set_cpu_lp_mode(ptr, 0, mode); +} + +/** + * @brief Clear CPU event flags + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] flags flag mask to be cleared + */ +static inline void sysctl_clear_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_event_flag_mask_t flags) +{ + ptr->CPU[cpu_index].LP |= ((SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK) & flags); +} + +/** + * @brief Clear CPU0 event flags + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] flags flag mask to be cleared + */ +static inline void sysctl_clear_cpu0_flags(SYSCTL_Type *ptr, cpu_event_flag_mask_t flags) +{ + sysctl_clear_cpu_flags(ptr, 0, flags); +} + +/** + * @brief Get CPU event flags + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @retval event flag mask + */ +static inline uint32_t sysctl_get_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + return ptr->CPU[cpu_index].LP & (SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK); +} + +/** + * @brief Get CPU0 event flags + * + * @param[in] ptr SYSCTL_Type base address + * @retval event flag mask + */ +static inline uint32_t sysctl_get_cpu0_flags(SYSCTL_Type *ptr) +{ + return sysctl_get_cpu_flags(ptr, 0); +} + +/** + * @brief Config lock + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] node clock node to be configured + * @param[in] source clock source to be used + * @param[in] divide_by clock frequency divider + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node, clock_source_t source, uint32_t divide_by); + +/** + * @brief Configure CPU domain clock + * @param ptr SYSCTL base address + * @param source clock source to be used + * @param cpu_div CPU divider + * @param ahb_sub_div AHB BUS divider based on divided CPU clock + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_config_cpu0_domain_clock(SYSCTL_Type *ptr, clock_source_t source, uint32_t cpu_div, uint32_t ahb_sub_div); + +/** + * @brief Set ADC clock mux + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] node clock node to be configured + * @param[in] source clock source to be used + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_set_adc_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_adc_t source); + + +/** + * @brief Enable group resource + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] group target group to be modified + * @param[in] resource target resource to be added/removed from group + * @param[in] enable set true to add resource, remove otherwise + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t resource, bool enable); + +/** + * @brief Check group resource enable status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] group target group to be checked + * @param[in] resource target resource to be checked from group + * @return enable true if resource enable, false if resource disable + */ +bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t resource); + +/** + * @brief Get group resource value + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] group target group to be getted + * @param[in] index target group index + * @return group index value + */ +uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index); + +/** + * @brief Add resource to CPU0 + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource resource to be added to CPU0 + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource); + +/** + * @brief Remove resource from CPU0 + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource Resource to be removed to CPU0 + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource); + +/** + * @brief Get default monitor config + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] config Monitor config structure pointer + */ +void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config); + +/** + * @brief Initialize Monitor + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index Monitor instance to be initialized + * @param[in] config Monitor config structure pointer + */ +void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config_t *config); + +/** + * @brief Save data to GPU0 GPR starting from given index + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] start Starting GPR index + * @param[in] count Number of GPR registers to set + * @param[in] data Pointer to data buffer + * @param[in] lock Set true to lock written GPR registers after setting + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock); + +/** + * @brief Get data saved from GPU0 GPR starting from given index + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] start Starting GPR index + * @param[in] count Number of GPR registers to set + * @param[out] data Pointer of buffer to save data + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data); + +/** + * @brief Set entry point on CPU0 wakeup + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] entry Entry address for CPU0 on its wakeup + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry); + + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_SYSCTL_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_sysctl_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_sysctl_regs.h new file mode 100644 index 00000000000..45bcc44d311 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/hpm_sysctl_regs.h @@ -0,0 +1,1271 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_SYSCTL_H +#define HPM_SYSCTL_H + +typedef struct { + __RW uint32_t RESOURCE[311]; /* 0x0 - 0x4D8: Resource control register for cpu0_core */ + __R uint8_t RESERVED0[804]; /* 0x4DC - 0x7FF: Reserved */ + struct { + __RW uint32_t VALUE; /* 0x800: Group setting */ + __RW uint32_t SET; /* 0x804: Group setting */ + __RW uint32_t CLEAR; /* 0x808: Group setting */ + __RW uint32_t TOGGLE; /* 0x80C: Group setting */ + } GROUP0[2]; + __R uint8_t RESERVED1[224]; /* 0x820 - 0x8FF: Reserved */ + struct { + __RW uint32_t VALUE; /* 0x900: Affiliate of Group */ + __RW uint32_t SET; /* 0x904: Affiliate of Group */ + __RW uint32_t CLEAR; /* 0x908: Affiliate of Group */ + __RW uint32_t TOGGLE; /* 0x90C: Affiliate of Group */ + } AFFILIATE[1]; + __R uint8_t RESERVED2[16]; /* 0x910 - 0x91F: Reserved */ + struct { + __RW uint32_t VALUE; /* 0x920: Retention Control */ + __RW uint32_t SET; /* 0x924: Retention Control */ + __RW uint32_t CLEAR; /* 0x928: Retention Control */ + __RW uint32_t TOGGLE; /* 0x92C: Retention Control */ + } RETENTION[1]; + __R uint8_t RESERVED3[1744]; /* 0x930 - 0xFFF: Reserved */ + struct { + __RW uint32_t STATUS; /* 0x1000: Power Setting */ + __RW uint32_t LF_WAIT; /* 0x1004: Power Setting */ + __R uint8_t RESERVED0[4]; /* 0x1008 - 0x100B: Reserved */ + __RW uint32_t OFF_WAIT; /* 0x100C: Power Setting */ + __RW uint32_t RET_WAIT; /* 0x1010: Power Setting */ + } POWER[1]; + __R uint8_t RESERVED4[1004]; /* 0x1014 - 0x13FF: Reserved */ + struct { + __RW uint32_t CONTROL; /* 0x1400: Reset Setting */ + __RW uint32_t CONFIG; /* 0x1404: Reset Setting */ + __R uint8_t RESERVED0[4]; /* 0x1408 - 0x140B: Reserved */ + __RW uint32_t COUNTER; /* 0x140C: Reset Setting */ + } RESET[2]; + __R uint8_t RESERVED5[992]; /* 0x1420 - 0x17FF: Reserved */ + __RW uint32_t CLOCK_CPU[1]; /* 0x1800: Clock setting */ + __RW uint32_t CLOCK[36]; /* 0x1804 - 0x1890: Clock setting */ + __R uint8_t RESERVED6[876]; /* 0x1894 - 0x1BFF: Reserved */ + __RW uint32_t ADCCLK[2]; /* 0x1C00 - 0x1C04: Clock setting */ + __RW uint32_t DACCLK[2]; /* 0x1C08 - 0x1C0C: Clock setting */ + __R uint8_t RESERVED7[1008]; /* 0x1C10 - 0x1FFF: Reserved */ + __RW uint32_t GLOBAL00; /* 0x2000: Clock senario */ + __R uint8_t RESERVED8[1020]; /* 0x2004 - 0x23FF: Reserved */ + struct { + __RW uint32_t CONTROL; /* 0x2400: Clock measure and monitor control */ + __R uint32_t CURRENT; /* 0x2404: Clock measure result */ + __RW uint32_t LOW_LIMIT; /* 0x2408: Clock lower limit */ + __RW uint32_t HIGH_LIMIT; /* 0x240C: Clock upper limit */ + __R uint8_t RESERVED0[16]; /* 0x2410 - 0x241F: Reserved */ + } MONITOR[4]; + __R uint8_t RESERVED9[896]; /* 0x2480 - 0x27FF: Reserved */ + struct { + __RW uint32_t LP; /* 0x2800: CPU0 LP control */ + __RW uint32_t LOCK; /* 0x2804: CPU0 Lock GPR */ + __RW uint32_t GPR[14]; /* 0x2808 - 0x283C: CPU0 GPR0 */ + __R uint32_t WAKEUP_STATUS[4]; /* 0x2840 - 0x284C: CPU0 wakeup IRQ status */ + __R uint8_t RESERVED0[48]; /* 0x2850 - 0x287F: Reserved */ + __RW uint32_t WAKEUP_ENABLE[4]; /* 0x2880 - 0x288C: CPU0 wakeup IRQ enable */ + __R uint8_t RESERVED1[880]; /* 0x2890 - 0x2BFF: Reserved */ + } CPU[1]; +} SYSCTL_Type; + + +/* Bitfield definition for register array: RESOURCE */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any nodes + * 1: any of nodes is changing status + */ +#define SYSCTL_RESOURCE_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_RESOURCE_GLB_BUSY_SHIFT (31U) +#define SYSCTL_RESOURCE_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_GLB_BUSY_MASK) >> SYSCTL_RESOURCE_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: no change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_RESOURCE_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_RESOURCE_LOC_BUSY_SHIFT (30U) +#define SYSCTL_RESOURCE_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_LOC_BUSY_MASK) >> SYSCTL_RESOURCE_LOC_BUSY_SHIFT) + +/* + * MODE (RW) + * + * resource work mode + * 0:auto turn on and off as system required(recommended) + * 1:always on + * 2:always off + * 3:reserved + */ +#define SYSCTL_RESOURCE_MODE_MASK (0x3U) +#define SYSCTL_RESOURCE_MODE_SHIFT (0U) +#define SYSCTL_RESOURCE_MODE_SET(x) (((uint32_t)(x) << SYSCTL_RESOURCE_MODE_SHIFT) & SYSCTL_RESOURCE_MODE_MASK) +#define SYSCTL_RESOURCE_MODE_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_MODE_MASK) >> SYSCTL_RESOURCE_MODE_SHIFT) + +/* Bitfield definition for register of struct array GROUP0: VALUE */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: peripheral is not needed + * 1: periphera is needed + */ +#define SYSCTL_GROUP0_VALUE_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP0_VALUE_LINK_SHIFT (0U) +#define SYSCTL_GROUP0_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_VALUE_LINK_SHIFT) & SYSCTL_GROUP0_VALUE_LINK_MASK) +#define SYSCTL_GROUP0_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_VALUE_LINK_MASK) >> SYSCTL_GROUP0_VALUE_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP0: SET */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: no effect + * 1: add periphera into this group，periphera is needed + */ +#define SYSCTL_GROUP0_SET_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP0_SET_LINK_SHIFT (0U) +#define SYSCTL_GROUP0_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_SET_LINK_SHIFT) & SYSCTL_GROUP0_SET_LINK_MASK) +#define SYSCTL_GROUP0_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_SET_LINK_MASK) >> SYSCTL_GROUP0_SET_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP0: CLEAR */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: no effect + * 1: delete periphera in this group，periphera is not needed + */ +#define SYSCTL_GROUP0_CLEAR_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP0_CLEAR_LINK_SHIFT (0U) +#define SYSCTL_GROUP0_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_CLEAR_LINK_SHIFT) & SYSCTL_GROUP0_CLEAR_LINK_MASK) +#define SYSCTL_GROUP0_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_CLEAR_LINK_MASK) >> SYSCTL_GROUP0_CLEAR_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP0: TOGGLE */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: no effect + * 1: toggle the result that whether periphera is needed before + */ +#define SYSCTL_GROUP0_TOGGLE_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP0_TOGGLE_LINK_SHIFT (0U) +#define SYSCTL_GROUP0_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) +#define SYSCTL_GROUP0_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) >> SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) + +/* Bitfield definition for register of struct array AFFILIATE: VALUE */ +/* + * LINK (RW) + * + * Affiliate groups of cpu0, each bit represents a group + * bit0: cpu0 depends on group0 + * bit1: cpu0 depends on group1 + * bit2: cpu0 depends on group2 + * bit3: cpu0 depends on group3 + */ +#define SYSCTL_AFFILIATE_VALUE_LINK_MASK (0xFU) +#define SYSCTL_AFFILIATE_VALUE_LINK_SHIFT (0U) +#define SYSCTL_AFFILIATE_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) +#define SYSCTL_AFFILIATE_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) >> SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) + +/* Bitfield definition for register of struct array AFFILIATE: SET */ +/* + * LINK (RW) + * + * Affiliate groups of cpu0，each bit represents a group + * 0: no effect + * 1: the group is assigned to CPU0 + */ +#define SYSCTL_AFFILIATE_SET_LINK_MASK (0xFU) +#define SYSCTL_AFFILIATE_SET_LINK_SHIFT (0U) +#define SYSCTL_AFFILIATE_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_SET_LINK_SHIFT) & SYSCTL_AFFILIATE_SET_LINK_MASK) +#define SYSCTL_AFFILIATE_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_SET_LINK_MASK) >> SYSCTL_AFFILIATE_SET_LINK_SHIFT) + +/* Bitfield definition for register of struct array AFFILIATE: CLEAR */ +/* + * LINK (RW) + * + * Affiliate groups of cpu0, each bit represents a group + * 0: no effect + * 1: the group is not assigned to CPU0 + */ +#define SYSCTL_AFFILIATE_CLEAR_LINK_MASK (0xFU) +#define SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT (0U) +#define SYSCTL_AFFILIATE_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) +#define SYSCTL_AFFILIATE_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) >> SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) + +/* Bitfield definition for register of struct array AFFILIATE: TOGGLE */ +/* + * LINK (RW) + * + * Affiliate groups of cpu0, each bit represents a group + * 0: no effect + * 1: toggle the result that whether the group is assigned to CPU0 before + */ +#define SYSCTL_AFFILIATE_TOGGLE_LINK_MASK (0xFU) +#define SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT (0U) +#define SYSCTL_AFFILIATE_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) +#define SYSCTL_AFFILIATE_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) >> SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) + +/* Bitfield definition for register of struct array RETENTION: VALUE */ +/* + * LINK (RW) + * + * retention setting while CPU0 enter stop mode, each bit represents a resource + * bit00: soc_mem is kept on while cpu0 stop + * bit01: soc_ctx is kept on while cpu0 stop + * bit02: cpu0_mem is kept on while cpu0 stop + * bit03: cpu0_ctx is kept on while cpu0 stop + * bit04: xtal_hold is kept on while cpu0 stop + * bit05: pll0_hold is kept on while cpu0 stop + * bit06: pll1_hold is kept on while cpu0 stop + */ +#define SYSCTL_RETENTION_VALUE_LINK_MASK (0x7FFFU) +#define SYSCTL_RETENTION_VALUE_LINK_SHIFT (0U) +#define SYSCTL_RETENTION_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_VALUE_LINK_SHIFT) & SYSCTL_RETENTION_VALUE_LINK_MASK) +#define SYSCTL_RETENTION_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_VALUE_LINK_MASK) >> SYSCTL_RETENTION_VALUE_LINK_SHIFT) + +/* Bitfield definition for register of struct array RETENTION: SET */ +/* + * LINK (RW) + * + * retention setting while CPU0 enter stop mode, each bit represents a resource + * 0: no effect + * 1: keep + */ +#define SYSCTL_RETENTION_SET_LINK_MASK (0x7FFFU) +#define SYSCTL_RETENTION_SET_LINK_SHIFT (0U) +#define SYSCTL_RETENTION_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_SET_LINK_SHIFT) & SYSCTL_RETENTION_SET_LINK_MASK) +#define SYSCTL_RETENTION_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_SET_LINK_MASK) >> SYSCTL_RETENTION_SET_LINK_SHIFT) + +/* Bitfield definition for register of struct array RETENTION: CLEAR */ +/* + * LINK (RW) + * + * retention setting while CPU0 enter stop mode, each bit represents a resource + * 0: no effect + * 1: no keep + */ +#define SYSCTL_RETENTION_CLEAR_LINK_MASK (0x7FFFU) +#define SYSCTL_RETENTION_CLEAR_LINK_SHIFT (0U) +#define SYSCTL_RETENTION_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_CLEAR_LINK_SHIFT) & SYSCTL_RETENTION_CLEAR_LINK_MASK) +#define SYSCTL_RETENTION_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_CLEAR_LINK_MASK) >> SYSCTL_RETENTION_CLEAR_LINK_SHIFT) + +/* Bitfield definition for register of struct array RETENTION: TOGGLE */ +/* + * LINK (RW) + * + * retention setting while CPU0 enter stop mode, each bit represents a resource + * 0: no effect + * 1: toggle the result that whether the resource is kept on while CPU0 stop before + */ +#define SYSCTL_RETENTION_TOGGLE_LINK_MASK (0x7FFFU) +#define SYSCTL_RETENTION_TOGGLE_LINK_SHIFT (0U) +#define SYSCTL_RETENTION_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) +#define SYSCTL_RETENTION_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) >> SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) + +/* Bitfield definition for register of struct array POWER: STATUS */ +/* + * FLAG (RW) + * + * flag represents power cycle happened from last clear of this bit + * 0: power domain did not edurance power cycle since last clear of this bit + * 1: power domain enduranced power cycle since last clear of this bit + */ +#define SYSCTL_POWER_STATUS_FLAG_MASK (0x80000000UL) +#define SYSCTL_POWER_STATUS_FLAG_SHIFT (31U) +#define SYSCTL_POWER_STATUS_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_SHIFT) & SYSCTL_POWER_STATUS_FLAG_MASK) +#define SYSCTL_POWER_STATUS_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_MASK) >> SYSCTL_POWER_STATUS_FLAG_SHIFT) + +/* + * FLAG_WAKE (RW) + * + * flag represents wakeup power cycle happened from last clear of this bit + * 0: power domain did not edurance wakeup power cycle since last clear of this bit + * 1: power domain enduranced wakeup power cycle since last clear of this bit + */ +#define SYSCTL_POWER_STATUS_FLAG_WAKE_MASK (0x40000000UL) +#define SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT (30U) +#define SYSCTL_POWER_STATUS_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) +#define SYSCTL_POWER_STATUS_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) >> SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) + +/* + * MEM_RET_N (RO) + * + * memory info retention control signal + * 0: memory enter retention mode + * 1: memory exit retention mode + */ +#define SYSCTL_POWER_STATUS_MEM_RET_N_MASK (0x20000UL) +#define SYSCTL_POWER_STATUS_MEM_RET_N_SHIFT (17U) +#define SYSCTL_POWER_STATUS_MEM_RET_N_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_MEM_RET_N_MASK) >> SYSCTL_POWER_STATUS_MEM_RET_N_SHIFT) + +/* + * MEM_RET_P (RO) + * + * memory info retention control signal + * 0: memory not enterexitretention mode + * 1: memory enter retention mode + */ +#define SYSCTL_POWER_STATUS_MEM_RET_P_MASK (0x10000UL) +#define SYSCTL_POWER_STATUS_MEM_RET_P_SHIFT (16U) +#define SYSCTL_POWER_STATUS_MEM_RET_P_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_MEM_RET_P_MASK) >> SYSCTL_POWER_STATUS_MEM_RET_P_SHIFT) + +/* + * LF_DISABLE (RO) + * + * low fanout power switch disable + * 0: low fanout power switches are turned on + * 1: low fanout power switches are truned off + */ +#define SYSCTL_POWER_STATUS_LF_DISABLE_MASK (0x1000U) +#define SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT (12U) +#define SYSCTL_POWER_STATUS_LF_DISABLE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_DISABLE_MASK) >> SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT) + +/* + * LF_ACK (RO) + * + * low fanout power switch feedback + * 0: low fanout power switches are turned on + * 1: low fanout power switches are truned off + */ +#define SYSCTL_POWER_STATUS_LF_ACK_MASK (0x100U) +#define SYSCTL_POWER_STATUS_LF_ACK_SHIFT (8U) +#define SYSCTL_POWER_STATUS_LF_ACK_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_ACK_MASK) >> SYSCTL_POWER_STATUS_LF_ACK_SHIFT) + +/* Bitfield definition for register of struct array POWER: LF_WAIT */ +/* + * WAIT (RW) + * + * wait time for low fan out power switch turn on, default value is 255 + * 0: 0 clock cycle + * 1: 1 clock cycles + * . . . + * clock cycles count on 24MHz + */ +#define SYSCTL_POWER_LF_WAIT_WAIT_MASK (0xFFFFFUL) +#define SYSCTL_POWER_LF_WAIT_WAIT_SHIFT (0U) +#define SYSCTL_POWER_LF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) +#define SYSCTL_POWER_LF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) >> SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) + +/* Bitfield definition for register of struct array POWER: OFF_WAIT */ +/* + * WAIT (RW) + * + * wait time for power switch turn off, default value is 15 + * 0: 0 clock cycle + * 1: 1 clock cycles + * . . . + * clock cycles count on 24MHz + */ +#define SYSCTL_POWER_OFF_WAIT_WAIT_MASK (0xFFFFFUL) +#define SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT (0U) +#define SYSCTL_POWER_OFF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) +#define SYSCTL_POWER_OFF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) >> SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) + +/* Bitfield definition for register of struct array POWER: RET_WAIT */ +/* + * WAIT (RW) + * + * wait time for memory retention mode transition, default value is 15 + * 0: 0 clock cycle + * 1: 1 clock cycles + * . . . + * clock cycles count on 24MHz + */ +#define SYSCTL_POWER_RET_WAIT_WAIT_MASK (0xFFFFFUL) +#define SYSCTL_POWER_RET_WAIT_WAIT_SHIFT (0U) +#define SYSCTL_POWER_RET_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_RET_WAIT_WAIT_SHIFT) & SYSCTL_POWER_RET_WAIT_WAIT_MASK) +#define SYSCTL_POWER_RET_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_RET_WAIT_WAIT_MASK) >> SYSCTL_POWER_RET_WAIT_WAIT_SHIFT) + +/* Bitfield definition for register of struct array RESET: CONTROL */ +/* + * FLAG (RW) + * + * flag represents reset happened from last clear of this bit + * 0: domain did not edurance reset cycle since last clear of this bit + * 1: domain enduranced reset cycle since last clear of this bit + */ +#define SYSCTL_RESET_CONTROL_FLAG_MASK (0x80000000UL) +#define SYSCTL_RESET_CONTROL_FLAG_SHIFT (31U) +#define SYSCTL_RESET_CONTROL_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_MASK) +#define SYSCTL_RESET_CONTROL_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_MASK) >> SYSCTL_RESET_CONTROL_FLAG_SHIFT) + +/* + * FLAG_WAKE (RW) + * + * flag represents wakeup reset happened from last clear of this bit + * 0: domain did not edurance wakeup reset cycle since last clear of this bit + * 1: domain enduranced wakeup reset cycle since last clear of this bit + */ +#define SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK (0x40000000UL) +#define SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT (30U) +#define SYSCTL_RESET_CONTROL_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) +#define SYSCTL_RESET_CONTROL_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) >> SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) + +/* + * HOLD (RW) + * + * perform reset and hold in reset, until ths bit cleared by software + * 0: reset is released for function + * 1: reset is assert and hold + */ +#define SYSCTL_RESET_CONTROL_HOLD_MASK (0x10U) +#define SYSCTL_RESET_CONTROL_HOLD_SHIFT (4U) +#define SYSCTL_RESET_CONTROL_HOLD_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_HOLD_SHIFT) & SYSCTL_RESET_CONTROL_HOLD_MASK) +#define SYSCTL_RESET_CONTROL_HOLD_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_HOLD_MASK) >> SYSCTL_RESET_CONTROL_HOLD_SHIFT) + +/* + * RESET (RW) + * + * perform reset and release imediately + * 0: reset is released + * 1 reset is asserted and will release automatically + */ +#define SYSCTL_RESET_CONTROL_RESET_MASK (0x1U) +#define SYSCTL_RESET_CONTROL_RESET_SHIFT (0U) +#define SYSCTL_RESET_CONTROL_RESET_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_RESET_SHIFT) & SYSCTL_RESET_CONTROL_RESET_MASK) +#define SYSCTL_RESET_CONTROL_RESET_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_RESET_MASK) >> SYSCTL_RESET_CONTROL_RESET_SHIFT) + +/* Bitfield definition for register of struct array RESET: CONFIG */ +/* + * PRE_WAIT (RW) + * + * wait cycle numbers before assert reset + * 0: wait 0 cycle + * 1: wait 1 cycles + * . . . + * Note, clock cycle is base on 24M + */ +#define SYSCTL_RESET_CONFIG_PRE_WAIT_MASK (0xFF0000UL) +#define SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT (16U) +#define SYSCTL_RESET_CONFIG_PRE_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) +#define SYSCTL_RESET_CONFIG_PRE_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) >> SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) + +/* + * RSTCLK_NUM (RW) + * + * reset clock number(must be even number) + * 0: 0 cycle + * 1: 0 cycles + * 2: 2 cycles + * 3: 2 cycles + * . . . + * Note, clock cycle is base on 24M + */ +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK (0xFF00U) +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT (8U) +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) >> SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) + +/* + * POST_WAIT (RW) + * + * time guard band for reset release + * 0: wait 0 cycle + * 1: wait 1 cycles + * . . . + * Note, clock cycle is base on 24M + */ +#define SYSCTL_RESET_CONFIG_POST_WAIT_MASK (0xFFU) +#define SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT (0U) +#define SYSCTL_RESET_CONFIG_POST_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) +#define SYSCTL_RESET_CONFIG_POST_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) >> SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) + +/* Bitfield definition for register of struct array RESET: COUNTER */ +/* + * COUNTER (RW) + * + * self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset + * 0: wait 0 cycle + * 1: wait 1 cycles + * . . . + * Note, clock cycle is base on 24M + */ +#define SYSCTL_RESET_COUNTER_COUNTER_MASK (0xFFFFFUL) +#define SYSCTL_RESET_COUNTER_COUNTER_SHIFT (0U) +#define SYSCTL_RESET_COUNTER_COUNTER_SET(x) (((uint32_t)(x) << SYSCTL_RESET_COUNTER_COUNTER_SHIFT) & SYSCTL_RESET_COUNTER_COUNTER_MASK) +#define SYSCTL_RESET_COUNTER_COUNTER_GET(x) (((uint32_t)(x) & SYSCTL_RESET_COUNTER_COUNTER_MASK) >> SYSCTL_RESET_COUNTER_COUNTER_SHIFT) + +/* Bitfield definition for register array: CLOCK_CPU */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any clock + * 1: any of nodes is changing status + */ +#define SYSCTL_CLOCK_CPU_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_CLOCK_CPU_GLB_BUSY_SHIFT (31U) +#define SYSCTL_CLOCK_CPU_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_GLB_BUSY_MASK) >> SYSCTL_CLOCK_CPU_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: a change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_CLOCK_CPU_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_CLOCK_CPU_LOC_BUSY_SHIFT (30U) +#define SYSCTL_CLOCK_CPU_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_LOC_BUSY_MASK) >> SYSCTL_CLOCK_CPU_LOC_BUSY_SHIFT) + +/* + * PRESERVE (RW) + * + * preserve function against global select + * 0: select global clock setting + * 1: not select global clock setting + */ +#define SYSCTL_CLOCK_CPU_PRESERVE_MASK (0x10000000UL) +#define SYSCTL_CLOCK_CPU_PRESERVE_SHIFT (28U) +#define SYSCTL_CLOCK_CPU_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_PRESERVE_SHIFT) & SYSCTL_CLOCK_CPU_PRESERVE_MASK) +#define SYSCTL_CLOCK_CPU_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_PRESERVE_MASK) >> SYSCTL_CLOCK_CPU_PRESERVE_SHIFT) + +/* + * SUB0_DIV (RW) + * + * ahb bus divider, the bus clock is generated by cpu_clock/div + * 0: divider by 1 + * 1: divider by 2 + * … + */ +#define SYSCTL_CLOCK_CPU_SUB0_DIV_MASK (0xF0000UL) +#define SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT (16U) +#define SYSCTL_CLOCK_CPU_SUB0_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT) & SYSCTL_CLOCK_CPU_SUB0_DIV_MASK) +#define SYSCTL_CLOCK_CPU_SUB0_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_SUB0_DIV_MASK) >> SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT) + +/* + * MUX (RW) + * + * current mux in clock component + * 0:osc0_clk0 + * 1:pll0_clk0 + * 2:pll0_clk1 + * 3:pll0_clk2 + * 4:pll1_clk0 + * 5:pll1_clk1 + * 6:pll1_clk2 + * 7:pll1_clk3 + */ +#define SYSCTL_CLOCK_CPU_MUX_MASK (0x700U) +#define SYSCTL_CLOCK_CPU_MUX_SHIFT (8U) +#define SYSCTL_CLOCK_CPU_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_MUX_SHIFT) & SYSCTL_CLOCK_CPU_MUX_MASK) +#define SYSCTL_CLOCK_CPU_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_MUX_MASK) >> SYSCTL_CLOCK_CPU_MUX_SHIFT) + +/* + * DIV (RW) + * + * clock divider + * 0: divider by 1 + * 1: divider by 2 + * 2: divider by 3 + * . . . + * 255: divider by 256 + */ +#define SYSCTL_CLOCK_CPU_DIV_MASK (0xFFU) +#define SYSCTL_CLOCK_CPU_DIV_SHIFT (0U) +#define SYSCTL_CLOCK_CPU_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_DIV_SHIFT) & SYSCTL_CLOCK_CPU_DIV_MASK) +#define SYSCTL_CLOCK_CPU_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_DIV_MASK) >> SYSCTL_CLOCK_CPU_DIV_SHIFT) + +/* Bitfield definition for register array: CLOCK */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any clock + * 1: any of nodes is changing status + */ +#define SYSCTL_CLOCK_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_CLOCK_GLB_BUSY_SHIFT (31U) +#define SYSCTL_CLOCK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_GLB_BUSY_MASK) >> SYSCTL_CLOCK_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: a change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_CLOCK_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_CLOCK_LOC_BUSY_SHIFT (30U) +#define SYSCTL_CLOCK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_LOC_BUSY_MASK) >> SYSCTL_CLOCK_LOC_BUSY_SHIFT) + +/* + * PRESERVE (RW) + * + * preserve function against global select + * 0: select global clock setting + * 1: not select global clock setting + */ +#define SYSCTL_CLOCK_PRESERVE_MASK (0x10000000UL) +#define SYSCTL_CLOCK_PRESERVE_SHIFT (28U) +#define SYSCTL_CLOCK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_PRESERVE_SHIFT) & SYSCTL_CLOCK_PRESERVE_MASK) +#define SYSCTL_CLOCK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_PRESERVE_MASK) >> SYSCTL_CLOCK_PRESERVE_SHIFT) + +/* + * MUX (RW) + * + * current mux in clock component + * 0:osc0_clk0 + * 1:pll0_clk0 + * 2:pll0_clk1 + * 3:pll0_clk2 + * 4:pll1_clk0 + * 5:pll1_clk1 + * 6:pll1_clk2 + * 7:pll1_clk3 + */ +#define SYSCTL_CLOCK_MUX_MASK (0x700U) +#define SYSCTL_CLOCK_MUX_SHIFT (8U) +#define SYSCTL_CLOCK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_MUX_SHIFT) & SYSCTL_CLOCK_MUX_MASK) +#define SYSCTL_CLOCK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_MUX_MASK) >> SYSCTL_CLOCK_MUX_SHIFT) + +/* + * DIV (RW) + * + * clock divider + * 0: divider by 1 + * 1: divider by 2 + * 2: divider by 3 + * . . . + * 255: divider by 256 + */ +#define SYSCTL_CLOCK_DIV_MASK (0xFFU) +#define SYSCTL_CLOCK_DIV_SHIFT (0U) +#define SYSCTL_CLOCK_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_DIV_SHIFT) & SYSCTL_CLOCK_DIV_MASK) +#define SYSCTL_CLOCK_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_DIV_MASK) >> SYSCTL_CLOCK_DIV_SHIFT) + +/* Bitfield definition for register array: ADCCLK */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any clock + * 1: any of nodes is changing status + */ +#define SYSCTL_ADCCLK_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_ADCCLK_GLB_BUSY_SHIFT (31U) +#define SYSCTL_ADCCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_GLB_BUSY_MASK) >> SYSCTL_ADCCLK_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: a change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_ADCCLK_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_ADCCLK_LOC_BUSY_SHIFT (30U) +#define SYSCTL_ADCCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_LOC_BUSY_MASK) >> SYSCTL_ADCCLK_LOC_BUSY_SHIFT) + +/* + * PRESERVE (RW) + * + * preserve function against global select + * 0: select global clock setting + * 1: not select global clock setting + */ +#define SYSCTL_ADCCLK_PRESERVE_MASK (0x10000000UL) +#define SYSCTL_ADCCLK_PRESERVE_SHIFT (28U) +#define SYSCTL_ADCCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_PRESERVE_SHIFT) & SYSCTL_ADCCLK_PRESERVE_MASK) +#define SYSCTL_ADCCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_PRESERVE_MASK) >> SYSCTL_ADCCLK_PRESERVE_SHIFT) + +/* + * MUX (RW) + * + * current mux + * 0: ahb0 clock N + * 1: ana clock + */ +#define SYSCTL_ADCCLK_MUX_MASK (0x100U) +#define SYSCTL_ADCCLK_MUX_SHIFT (8U) +#define SYSCTL_ADCCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_MUX_SHIFT) & SYSCTL_ADCCLK_MUX_MASK) +#define SYSCTL_ADCCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_MUX_MASK) >> SYSCTL_ADCCLK_MUX_SHIFT) + +/* Bitfield definition for register array: DACCLK */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any clock + * 1: any of nodes is changing status + */ +#define SYSCTL_DACCLK_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_DACCLK_GLB_BUSY_SHIFT (31U) +#define SYSCTL_DACCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_GLB_BUSY_MASK) >> SYSCTL_DACCLK_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: a change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_DACCLK_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_DACCLK_LOC_BUSY_SHIFT (30U) +#define SYSCTL_DACCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_LOC_BUSY_MASK) >> SYSCTL_DACCLK_LOC_BUSY_SHIFT) + +/* + * PRESERVE (RW) + * + * preserve function against global select + * 0: select global clock setting + * 1: not select global clock setting + */ +#define SYSCTL_DACCLK_PRESERVE_MASK (0x10000000UL) +#define SYSCTL_DACCLK_PRESERVE_SHIFT (28U) +#define SYSCTL_DACCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_DACCLK_PRESERVE_SHIFT) & SYSCTL_DACCLK_PRESERVE_MASK) +#define SYSCTL_DACCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_PRESERVE_MASK) >> SYSCTL_DACCLK_PRESERVE_SHIFT) + +/* + * MUX (RW) + * + * current mux + * 0: ahb0 clock N + * 1: ana clock + */ +#define SYSCTL_DACCLK_MUX_MASK (0x100U) +#define SYSCTL_DACCLK_MUX_SHIFT (8U) +#define SYSCTL_DACCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_DACCLK_MUX_SHIFT) & SYSCTL_DACCLK_MUX_MASK) +#define SYSCTL_DACCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_MUX_MASK) >> SYSCTL_DACCLK_MUX_SHIFT) + +/* Bitfield definition for register: GLOBAL00 */ +/* + * MUX (RW) + * + * global clock override request + * bit0: override to preset0 + * bit1: override to preset1 + * bit2: override to preset2 + * bit3: override to preset3 + * bit4: override to preset4 + * bit5: override to preset5 + * bit6: override to preset6 + * bit7: override to preset7 + */ +#define SYSCTL_GLOBAL00_MUX_MASK (0xFFU) +#define SYSCTL_GLOBAL00_MUX_SHIFT (0U) +#define SYSCTL_GLOBAL00_MUX_SET(x) (((uint32_t)(x) << SYSCTL_GLOBAL00_MUX_SHIFT) & SYSCTL_GLOBAL00_MUX_MASK) +#define SYSCTL_GLOBAL00_MUX_GET(x) (((uint32_t)(x) & SYSCTL_GLOBAL00_MUX_MASK) >> SYSCTL_GLOBAL00_MUX_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: CONTROL */ +/* + * VALID (RW) + * + * result is ready for read + * 0: not ready + * 1: result is ready + */ +#define SYSCTL_MONITOR_CONTROL_VALID_MASK (0x80000000UL) +#define SYSCTL_MONITOR_CONTROL_VALID_SHIFT (31U) +#define SYSCTL_MONITOR_CONTROL_VALID_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_VALID_SHIFT) & SYSCTL_MONITOR_CONTROL_VALID_MASK) +#define SYSCTL_MONITOR_CONTROL_VALID_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_VALID_MASK) >> SYSCTL_MONITOR_CONTROL_VALID_SHIFT) + +/* + * DIV_BUSY (RO) + * + * divider is applying new setting + */ +#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK (0x8000000UL) +#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT (27U) +#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT) + +/* + * OUTEN (RW) + * + * enable clock output + */ +#define SYSCTL_MONITOR_CONTROL_OUTEN_MASK (0x1000000UL) +#define SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT (24U) +#define SYSCTL_MONITOR_CONTROL_OUTEN_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) +#define SYSCTL_MONITOR_CONTROL_OUTEN_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) >> SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) + +/* + * DIV (RW) + * + * output divider + */ +#define SYSCTL_MONITOR_CONTROL_DIV_MASK (0xFF0000UL) +#define SYSCTL_MONITOR_CONTROL_DIV_SHIFT (16U) +#define SYSCTL_MONITOR_CONTROL_DIV_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_DIV_SHIFT) & SYSCTL_MONITOR_CONTROL_DIV_MASK) +#define SYSCTL_MONITOR_CONTROL_DIV_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_SHIFT) + +/* + * HIGH (RW) + * + * clock frequency higher than upper limit + */ +#define SYSCTL_MONITOR_CONTROL_HIGH_MASK (0x8000U) +#define SYSCTL_MONITOR_CONTROL_HIGH_SHIFT (15U) +#define SYSCTL_MONITOR_CONTROL_HIGH_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) +#define SYSCTL_MONITOR_CONTROL_HIGH_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) >> SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) + +/* + * LOW (RW) + * + * clock frequency lower than lower limit + */ +#define SYSCTL_MONITOR_CONTROL_LOW_MASK (0x4000U) +#define SYSCTL_MONITOR_CONTROL_LOW_SHIFT (14U) +#define SYSCTL_MONITOR_CONTROL_LOW_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_LOW_SHIFT) & SYSCTL_MONITOR_CONTROL_LOW_MASK) +#define SYSCTL_MONITOR_CONTROL_LOW_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_LOW_MASK) >> SYSCTL_MONITOR_CONTROL_LOW_SHIFT) + +/* + * START (RW) + * + * start measurement + */ +#define SYSCTL_MONITOR_CONTROL_START_MASK (0x1000U) +#define SYSCTL_MONITOR_CONTROL_START_SHIFT (12U) +#define SYSCTL_MONITOR_CONTROL_START_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_START_SHIFT) & SYSCTL_MONITOR_CONTROL_START_MASK) +#define SYSCTL_MONITOR_CONTROL_START_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_START_MASK) >> SYSCTL_MONITOR_CONTROL_START_SHIFT) + +/* + * MODE (RW) + * + * work mode, + * 0: register value will be compared to measurement + * 1: upper and lower value will be recordered in register + */ +#define SYSCTL_MONITOR_CONTROL_MODE_MASK (0x400U) +#define SYSCTL_MONITOR_CONTROL_MODE_SHIFT (10U) +#define SYSCTL_MONITOR_CONTROL_MODE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_MODE_SHIFT) & SYSCTL_MONITOR_CONTROL_MODE_MASK) +#define SYSCTL_MONITOR_CONTROL_MODE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_MODE_MASK) >> SYSCTL_MONITOR_CONTROL_MODE_SHIFT) + +/* + * ACCURACY (RW) + * + * measurement accuracy, + * 0: resolution is 1kHz + * 1: resolution is 1Hz + */ +#define SYSCTL_MONITOR_CONTROL_ACCURACY_MASK (0x200U) +#define SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT (9U) +#define SYSCTL_MONITOR_CONTROL_ACCURACY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) +#define SYSCTL_MONITOR_CONTROL_ACCURACY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) >> SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) + +/* + * REFERENCE (RW) + * + * reference clock selection, + * 0: 32k + * 1: 24M + */ +#define SYSCTL_MONITOR_CONTROL_REFERENCE_MASK (0x100U) +#define SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT (8U) +#define SYSCTL_MONITOR_CONTROL_REFERENCE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) +#define SYSCTL_MONITOR_CONTROL_REFERENCE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) >> SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) + +/* + * SELECTION (RW) + * + * clock measurement selection + */ +#define SYSCTL_MONITOR_CONTROL_SELECTION_MASK (0xFFU) +#define SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT (0U) +#define SYSCTL_MONITOR_CONTROL_SELECTION_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) +#define SYSCTL_MONITOR_CONTROL_SELECTION_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) >> SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: CURRENT */ +/* + * FREQUENCY (RO) + * + * self updating measure result + */ +#define SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK (0xFFFFFFFFUL) +#define SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT (0U) +#define SYSCTL_MONITOR_CURRENT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK) >> SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: LOW_LIMIT */ +/* + * FREQUENCY (RW) + * + * lower frequency + */ +#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL) +#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT (0U) +#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) +#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: HIGH_LIMIT */ +/* + * FREQUENCY (RW) + * + * upper frequency + */ +#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL) +#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT (0U) +#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) +#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) + +/* Bitfield definition for register of struct array CPU: LP */ +/* + * WAKE_CNT (RW) + * + * CPU0 wake up counter, counter satuated at 255, write 0x00 to clear + */ +#define SYSCTL_CPU_LP_WAKE_CNT_MASK (0xFF000000UL) +#define SYSCTL_CPU_LP_WAKE_CNT_SHIFT (24U) +#define SYSCTL_CPU_LP_WAKE_CNT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_CNT_SHIFT) & SYSCTL_CPU_LP_WAKE_CNT_MASK) +#define SYSCTL_CPU_LP_WAKE_CNT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_CNT_MASK) >> SYSCTL_CPU_LP_WAKE_CNT_SHIFT) + +/* + * HALT (RW) + * + * halt request for CPU0, + * 0: CPU0 will start to execute after reset or receive wakeup request + * 1: CPU0 will not start after reset, or wakeup after WFI + */ +#define SYSCTL_CPU_LP_HALT_MASK (0x10000UL) +#define SYSCTL_CPU_LP_HALT_SHIFT (16U) +#define SYSCTL_CPU_LP_HALT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_HALT_SHIFT) & SYSCTL_CPU_LP_HALT_MASK) +#define SYSCTL_CPU_LP_HALT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_HALT_MASK) >> SYSCTL_CPU_LP_HALT_SHIFT) + +/* + * WAKE (RO) + * + * CPU0 is waking up + * 0: CPU0 wake up not asserted + * 1: CPU0 wake up asserted + */ +#define SYSCTL_CPU_LP_WAKE_MASK (0x2000U) +#define SYSCTL_CPU_LP_WAKE_SHIFT (13U) +#define SYSCTL_CPU_LP_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_MASK) >> SYSCTL_CPU_LP_WAKE_SHIFT) + +/* + * EXEC (RO) + * + * CPU0 is executing + * 0: CPU0 is not executing + * 1: CPU0 is executing + */ +#define SYSCTL_CPU_LP_EXEC_MASK (0x1000U) +#define SYSCTL_CPU_LP_EXEC_SHIFT (12U) +#define SYSCTL_CPU_LP_EXEC_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_EXEC_MASK) >> SYSCTL_CPU_LP_EXEC_SHIFT) + +/* + * WAKE_FLAG (RW) + * + * CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit + * 0: CPU0 wakeup not happened + * 1: CPU0 wake up happened + */ +#define SYSCTL_CPU_LP_WAKE_FLAG_MASK (0x400U) +#define SYSCTL_CPU_LP_WAKE_FLAG_SHIFT (10U) +#define SYSCTL_CPU_LP_WAKE_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) +#define SYSCTL_CPU_LP_WAKE_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) >> SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) + +/* + * SLEEP_FLAG (RW) + * + * CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit + * 0: CPU0 sleep not happened + * 1: CPU0 sleep happened + */ +#define SYSCTL_CPU_LP_SLEEP_FLAG_MASK (0x200U) +#define SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT (9U) +#define SYSCTL_CPU_LP_SLEEP_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) +#define SYSCTL_CPU_LP_SLEEP_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) >> SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) + +/* + * RESET_FLAG (RW) + * + * CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit + * 0: CPU0 reset not happened + * 1: CPU0 reset happened + */ +#define SYSCTL_CPU_LP_RESET_FLAG_MASK (0x100U) +#define SYSCTL_CPU_LP_RESET_FLAG_SHIFT (8U) +#define SYSCTL_CPU_LP_RESET_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_RESET_FLAG_SHIFT) & SYSCTL_CPU_LP_RESET_FLAG_MASK) +#define SYSCTL_CPU_LP_RESET_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_RESET_FLAG_MASK) >> SYSCTL_CPU_LP_RESET_FLAG_SHIFT) + +/* + * MODE (RW) + * + * Low power mode, system behavior after WFI + * 00: CPU clock stop after WFI + * 01: System enter low power mode after WFI + * 10: Keep running after WFI + * 11: reserved + */ +#define SYSCTL_CPU_LP_MODE_MASK (0x3U) +#define SYSCTL_CPU_LP_MODE_SHIFT (0U) +#define SYSCTL_CPU_LP_MODE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_MODE_SHIFT) & SYSCTL_CPU_LP_MODE_MASK) +#define SYSCTL_CPU_LP_MODE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_MODE_MASK) >> SYSCTL_CPU_LP_MODE_SHIFT) + +/* Bitfield definition for register of struct array CPU: LOCK */ +/* + * GPR (RW) + * + * Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset + */ +#define SYSCTL_CPU_LOCK_GPR_MASK (0xFFFCU) +#define SYSCTL_CPU_LOCK_GPR_SHIFT (2U) +#define SYSCTL_CPU_LOCK_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_GPR_SHIFT) & SYSCTL_CPU_LOCK_GPR_MASK) +#define SYSCTL_CPU_LOCK_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_GPR_MASK) >> SYSCTL_CPU_LOCK_GPR_SHIFT) + +/* + * LOCK (RW) + * + * Lock bit for CPU_LOCK + */ +#define SYSCTL_CPU_LOCK_LOCK_MASK (0x2U) +#define SYSCTL_CPU_LOCK_LOCK_SHIFT (1U) +#define SYSCTL_CPU_LOCK_LOCK_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_LOCK_SHIFT) & SYSCTL_CPU_LOCK_LOCK_MASK) +#define SYSCTL_CPU_LOCK_LOCK_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_LOCK_MASK) >> SYSCTL_CPU_LOCK_LOCK_SHIFT) + +/* Bitfield definition for register of struct array CPU: GPR0 */ +/* + * GPR (RW) + * + * register for software to handle resume, can save resume address or status + */ +#define SYSCTL_CPU_GPR_GPR_MASK (0xFFFFFFFFUL) +#define SYSCTL_CPU_GPR_GPR_SHIFT (0U) +#define SYSCTL_CPU_GPR_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_GPR_GPR_SHIFT) & SYSCTL_CPU_GPR_GPR_MASK) +#define SYSCTL_CPU_GPR_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_GPR_GPR_MASK) >> SYSCTL_CPU_GPR_GPR_SHIFT) + +/* Bitfield definition for register of struct array CPU: STATUS0 */ +/* + * STATUS (RO) + * + * IRQ values + */ +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK (0xFFFFFFFFUL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT (0U) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK) >> SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT) + +/* Bitfield definition for register of struct array CPU: ENABLE0 */ +/* + * ENABLE (RW) + * + * IRQ wakeup enable + */ +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT (0U) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) >> SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) + + + +/* RESOURCE register group index macro definition */ +#define SYSCTL_RESOURCE_CPU0 (0UL) +#define SYSCTL_RESOURCE_CPX0 (1UL) +#define SYSCTL_RESOURCE_POW_CPU0 (21UL) +#define SYSCTL_RESOURCE_RST_SOC (22UL) +#define SYSCTL_RESOURCE_RST_CPU0 (23UL) +#define SYSCTL_RESOURCE_CLK_SRC_XTAL (32UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL0 (33UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL0 (34UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL0 (35UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK2_PLL0 (36UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL1 (37UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL1 (38UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL1 (39UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK2_PLL1 (40UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK3_PLL1 (41UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL0_REF (42UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL1_REF (43UL) +#define SYSCTL_RESOURCE_CLK_TOP_CPU0 (64UL) +#define SYSCTL_RESOURCE_CLK_TOP_MCT0 (65UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN0 (66UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN1 (67UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN2 (68UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN3 (69UL) +#define SYSCTL_RESOURCE_CLK_TOP_TMR0 (74UL) +#define SYSCTL_RESOURCE_CLK_TOP_TMR1 (75UL) +#define SYSCTL_RESOURCE_CLK_TOP_TMR2 (76UL) +#define SYSCTL_RESOURCE_CLK_TOP_TMR3 (77UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2C0 (78UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2C1 (79UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2C2 (80UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2C3 (81UL) +#define SYSCTL_RESOURCE_CLK_TOP_SPI0 (82UL) +#define SYSCTL_RESOURCE_CLK_TOP_SPI1 (83UL) +#define SYSCTL_RESOURCE_CLK_TOP_SPI2 (84UL) +#define SYSCTL_RESOURCE_CLK_TOP_SPI3 (85UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT0 (86UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT1 (87UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT2 (88UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT3 (89UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT4 (90UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT5 (91UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT6 (92UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT7 (93UL) +#define SYSCTL_RESOURCE_CLK_TOP_XPI0 (94UL) +#define SYSCTL_RESOURCE_CLK_TOP_ANA0 (95UL) +#define SYSCTL_RESOURCE_CLK_TOP_ANA1 (96UL) +#define SYSCTL_RESOURCE_CLK_TOP_ANA2 (97UL) +#define SYSCTL_RESOURCE_CLK_TOP_ANA3 (98UL) +#define SYSCTL_RESOURCE_CLK_TOP_REF0 (99UL) +#define SYSCTL_RESOURCE_CLK_TOP_REF1 (100UL) +#define SYSCTL_RESOURCE_CLK_TOP_ADC0 (101UL) +#define SYSCTL_RESOURCE_CLK_TOP_ADC1 (102UL) +#define SYSCTL_RESOURCE_CLK_TOP_DAC0 (103UL) +#define SYSCTL_RESOURCE_CLK_TOP_DAC1 (104UL) +#define SYSCTL_RESOURCE_AHB0 (256UL) +#define SYSCTL_RESOURCE_LMM0 (257UL) +#define SYSCTL_RESOURCE_MCT0 (258UL) +#define SYSCTL_RESOURCE_ROM0 (259UL) +#define SYSCTL_RESOURCE_CAN0 (260UL) +#define SYSCTL_RESOURCE_CAN1 (261UL) +#define SYSCTL_RESOURCE_CAN2 (262UL) +#define SYSCTL_RESOURCE_CAN3 (263UL) +#define SYSCTL_RESOURCE_PTPC (264UL) +#define SYSCTL_RESOURCE_TMR0 (269UL) +#define SYSCTL_RESOURCE_TMR1 (270UL) +#define SYSCTL_RESOURCE_TMR2 (271UL) +#define SYSCTL_RESOURCE_TMR3 (272UL) +#define SYSCTL_RESOURCE_I2C0 (273UL) +#define SYSCTL_RESOURCE_I2C1 (274UL) +#define SYSCTL_RESOURCE_I2C2 (275UL) +#define SYSCTL_RESOURCE_I2C3 (276UL) +#define SYSCTL_RESOURCE_SPI0 (277UL) +#define SYSCTL_RESOURCE_SPI1 (278UL) +#define SYSCTL_RESOURCE_SPI2 (279UL) +#define SYSCTL_RESOURCE_SPI3 (280UL) +#define SYSCTL_RESOURCE_URT0 (281UL) +#define SYSCTL_RESOURCE_URT1 (282UL) +#define SYSCTL_RESOURCE_URT2 (283UL) +#define SYSCTL_RESOURCE_URT3 (284UL) +#define SYSCTL_RESOURCE_URT4 (285UL) +#define SYSCTL_RESOURCE_URT5 (286UL) +#define SYSCTL_RESOURCE_URT6 (287UL) +#define SYSCTL_RESOURCE_URT7 (288UL) +#define SYSCTL_RESOURCE_WDG0 (289UL) +#define SYSCTL_RESOURCE_WDG1 (290UL) +#define SYSCTL_RESOURCE_MBX0 (291UL) +#define SYSCTL_RESOURCE_TSNS (292UL) +#define SYSCTL_RESOURCE_CRC0 (293UL) +#define SYSCTL_RESOURCE_ADC0 (294UL) +#define SYSCTL_RESOURCE_ADC1 (295UL) +#define SYSCTL_RESOURCE_DAC0 (296UL) +#define SYSCTL_RESOURCE_DAC1 (297UL) +#define SYSCTL_RESOURCE_ACMP (298UL) +#define SYSCTL_RESOURCE_OPA0 (299UL) +#define SYSCTL_RESOURCE_OPA1 (300UL) +#define SYSCTL_RESOURCE_MOT0 (301UL) +#define SYSCTL_RESOURCE_RNG0 (302UL) +#define SYSCTL_RESOURCE_SDP0 (303UL) +#define SYSCTL_RESOURCE_KMAN (304UL) +#define SYSCTL_RESOURCE_GPIO (305UL) +#define SYSCTL_RESOURCE_HDMA (306UL) +#define SYSCTL_RESOURCE_XPI0 (307UL) +#define SYSCTL_RESOURCE_USB0 (308UL) +#define SYSCTL_RESOURCE_REF0 (309UL) +#define SYSCTL_RESOURCE_REF1 (310UL) + +/* GROUP0 register group index macro definition */ +#define SYSCTL_GROUP0_LINK0 (0UL) +#define SYSCTL_GROUP0_LINK1 (1UL) + +/* AFFILIATE register group index macro definition */ +#define SYSCTL_AFFILIATE_CPU0 (0UL) + +/* RETENTION register group index macro definition */ +#define SYSCTL_RETENTION_CPU0 (0UL) + +/* POWER register group index macro definition */ +#define SYSCTL_POWER_CPU0 (0UL) + +/* RESET register group index macro definition */ +#define SYSCTL_RESET_SOC (0UL) +#define SYSCTL_RESET_CPU0 (1UL) + +/* CLOCK_CPU register group index macro definition */ +#define SYSCTL_CLOCK_CPU_CLK_TOP_CPU0 (0UL) + +/* CLOCK register group index macro definition */ +#define SYSCTL_CLOCK_CLK_TOP_MCT0 (0UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN0 (1UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN1 (2UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN2 (3UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN3 (4UL) +#define SYSCTL_CLOCK_CLK_TOP_TMR0 (9UL) +#define SYSCTL_CLOCK_CLK_TOP_TMR1 (10UL) +#define SYSCTL_CLOCK_CLK_TOP_TMR2 (11UL) +#define SYSCTL_CLOCK_CLK_TOP_TMR3 (12UL) +#define SYSCTL_CLOCK_CLK_TOP_I2C0 (13UL) +#define SYSCTL_CLOCK_CLK_TOP_I2C1 (14UL) +#define SYSCTL_CLOCK_CLK_TOP_I2C2 (15UL) +#define SYSCTL_CLOCK_CLK_TOP_I2C3 (16UL) +#define SYSCTL_CLOCK_CLK_TOP_SPI0 (17UL) +#define SYSCTL_CLOCK_CLK_TOP_SPI1 (18UL) +#define SYSCTL_CLOCK_CLK_TOP_SPI2 (19UL) +#define SYSCTL_CLOCK_CLK_TOP_SPI3 (20UL) +#define SYSCTL_CLOCK_CLK_TOP_URT0 (21UL) +#define SYSCTL_CLOCK_CLK_TOP_URT1 (22UL) +#define SYSCTL_CLOCK_CLK_TOP_URT2 (23UL) +#define SYSCTL_CLOCK_CLK_TOP_URT3 (24UL) +#define SYSCTL_CLOCK_CLK_TOP_URT4 (25UL) +#define SYSCTL_CLOCK_CLK_TOP_URT5 (26UL) +#define SYSCTL_CLOCK_CLK_TOP_URT6 (27UL) +#define SYSCTL_CLOCK_CLK_TOP_URT7 (28UL) +#define SYSCTL_CLOCK_CLK_TOP_XPI0 (29UL) +#define SYSCTL_CLOCK_CLK_TOP_ANA0 (30UL) +#define SYSCTL_CLOCK_CLK_TOP_ANA1 (31UL) +#define SYSCTL_CLOCK_CLK_TOP_ANA2 (32UL) +#define SYSCTL_CLOCK_CLK_TOP_ANA3 (33UL) +#define SYSCTL_CLOCK_CLK_TOP_REF0 (34UL) +#define SYSCTL_CLOCK_CLK_TOP_REF1 (35UL) + +/* ADCCLK register group index macro definition */ +#define SYSCTL_ADCCLK_CLK_TOP_ADC0 (0UL) +#define SYSCTL_ADCCLK_CLK_TOP_ADC1 (1UL) + +/* DACCLK register group index macro definition */ +#define SYSCTL_DACCLK_CLK_TOP_DAC0 (0UL) +#define SYSCTL_DACCLK_CLK_TOP_DAC1 (1UL) + +/* MONITOR register group index macro definition */ +#define SYSCTL_MONITOR_SLICE0 (0UL) +#define SYSCTL_MONITOR_SLICE1 (1UL) +#define SYSCTL_MONITOR_SLICE2 (2UL) +#define SYSCTL_MONITOR_SLICE3 (3UL) + +/* GPR register group index macro definition */ +#define SYSCTL_CPU_GPR_GPR0 (0UL) +#define SYSCTL_CPU_GPR_GPR1 (1UL) +#define SYSCTL_CPU_GPR_GPR2 (2UL) +#define SYSCTL_CPU_GPR_GPR3 (3UL) +#define SYSCTL_CPU_GPR_GPR4 (4UL) +#define SYSCTL_CPU_GPR_GPR5 (5UL) +#define SYSCTL_CPU_GPR_GPR6 (6UL) +#define SYSCTL_CPU_GPR_GPR7 (7UL) +#define SYSCTL_CPU_GPR_GPR8 (8UL) +#define SYSCTL_CPU_GPR_GPR9 (9UL) +#define SYSCTL_CPU_GPR_GPR10 (10UL) +#define SYSCTL_CPU_GPR_GPR11 (11UL) +#define SYSCTL_CPU_GPR_GPR12 (12UL) +#define SYSCTL_CPU_GPR_GPR13 (13UL) + +/* WAKEUP_STATUS register group index macro definition */ +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS0 (0UL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS1 (1UL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS2 (2UL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS3 (3UL) + +/* WAKEUP_ENABLE register group index macro definition */ +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE0 (0UL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE1 (1UL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE2 (2UL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE3 (3UL) + +/* CPU register group index macro definition */ +#define SYSCTL_CPU_CPU0 (0UL) + + +#endif /* HPM_SYSCTL_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/soc_modules.list b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/soc_modules.list new file mode 100644 index 00000000000..30100a8a071 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/soc_modules.list @@ -0,0 +1,37 @@ +# +# Copyright (c) 2024 HPMicro +# +# SPDX-License-Identifier: BSD-3-Clause +# + +HPMSOC_HAS_HPMSDK_GPIO=y +HPMSOC_HAS_HPMSDK_PLIC=y +HPMSOC_HAS_HPMSDK_MCHTMR=y +HPMSOC_HAS_HPMSDK_PLICSW=y +HPMSOC_HAS_HPMSDK_GPTMR=y +HPMSOC_HAS_HPMSDK_UART=y +HPMSOC_HAS_HPMSDK_I2C=y +HPMSOC_HAS_HPMSDK_SPI=y +HPMSOC_HAS_HPMSDK_CRC=y +HPMSOC_HAS_HPMSDK_TSNS=y +HPMSOC_HAS_HPMSDK_MBX=y +HPMSOC_HAS_HPMSDK_EWDG=y +HPMSOC_HAS_HPMSDK_DMAMUX=y +HPMSOC_HAS_HPMSDK_DMAV2=y +HPMSOC_HAS_HPMSDK_GPIOM=y +HPMSOC_HAS_HPMSDK_USB=y +HPMSOC_HAS_HPMSDK_SEC=y +HPMSOC_HAS_HPMSDK_MON=y +HPMSOC_HAS_HPMSDK_OTP=y +HPMSOC_HAS_HPMSDK_KEYM=y +HPMSOC_HAS_HPMSDK_ADC16=y +HPMSOC_HAS_HPMSDK_ACMP=y +HPMSOC_HAS_HPMSDK_SYSCTL=y +HPMSOC_HAS_HPMSDK_IOC=y +HPMSOC_HAS_HPMSDK_PLLCTLV2=y +HPMSOC_HAS_HPMSDK_PPOR=y +HPMSOC_HAS_HPMSDK_PCFG=y +HPMSOC_HAS_HPMSDK_PGPR=y +HPMSOC_HAS_HPMSDK_PDGO=y +HPMSOC_HAS_HPMSDK_PMP=y + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/system.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/system.c new file mode 100644 index 00000000000..a0fb6800e94 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/system.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" + +#ifndef CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP +#define CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP 0 +#endif + +void enable_plic_feature(void) +{ + uint32_t plic_feature = 0; +#ifndef USE_NONVECTOR_MODE + /* enabled vector mode and preemptive priority interrupt */ + plic_feature |= HPM_PLIC_FEATURE_VECTORED_MODE; +#endif +#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) + /* enabled preemptive priority interrupt */ + plic_feature |= HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ; +#endif + __plic_set_feature(HPM_PLIC_BASE, plic_feature); +} + +__attribute__((weak)) void system_init(void) +{ +#ifndef CONFIG_NOT_ENALBE_ACCESS_TO_CYCLE_CSR + uint32_t mcounteren = read_csr(CSR_MCOUNTEREN); + write_csr(CSR_MCOUNTEREN, mcounteren | 1); /* Enable MCYCLE */ +#endif + +#ifdef USE_S_MODE_IRQ + disable_global_irq(CSR_MSTATUS_MIE_MASK | CSR_MSTATUS_SIE_MASK); +#else + disable_global_irq(CSR_MSTATUS_MIE_MASK); +#endif + + disable_irq_from_intc(); +#ifdef USE_S_MODE_IRQ + disable_s_irq_from_intc(); +#endif + + enable_plic_feature(); + enable_irq_from_intc(); + +#ifdef USE_S_MODE_IRQ + delegate_irq(CSR_MIDELEG_SEI_MASK | CSR_MIDELEG_SSI_MASK | CSR_MIDELEG_STI_MASK); + enable_s_irq_from_intc(); +#if !CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP + enable_global_irq(CSR_MSTATUS_MIE_MASK | CSR_MSTATUS_SIE_MASK); +#endif +#else +#if !CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP + enable_global_irq(CSR_MSTATUS_MIE_MASK); +#endif +#endif +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/toolchains/gcc/flash.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/toolchains/gcc/flash.ld new file mode 100644 index 00000000000..a162a7430b9 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/toolchains/gcc/flash.ld @@ -0,0 +1,250 @@ +/* + * Copyright (c) 2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = _stack_size; +HEAP_SIZE = _heap_size; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80003000, LENGTH = _flash_size - 0x3000 + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K + AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + KEEP(*(.vector_s_table)) + KEEP(*(.isr_s_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + /* RT-Thread related sections - Start */ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + . = ALIGN(8); + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + *(.fast.*) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > ILM + + .bss (NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > DLM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > DLM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > DLM + + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > DLM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > DLM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/toolchains/gcc/flash_uf2.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/toolchains/gcc/flash_uf2.ld new file mode 100644 index 00000000000..872b399c2e5 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/toolchains/gcc/flash_uf2.ld @@ -0,0 +1,251 @@ +/* + * Copyright (c) 2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = _stack_size; +HEAP_SIZE = _heap_size; +UF2_BOOTLOADER_RESERVED_LENGTH = DEFINED(_uf2_bl_length) ? _uf2_bl_length : 0x20000; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH, LENGTH = _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K + AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k +} + +SECTIONS +{ + .start : { + KEEP(*(.uf2_signature)) + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + KEEP(*(.vector_s_table)) + KEEP(*(.isr_s_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)): { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + /* RT-Thread related sections - Start */ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + . = ALIGN(8); + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + *(.fast.*) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > ILM + + .bss (NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > DLM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > DLM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > DLM + + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > DLM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > DLM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/toolchains/gcc/flash_xip.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/toolchains/gcc/flash_xip.ld new file mode 100644 index 00000000000..22e8126d342 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/toolchains/gcc/flash_xip.ld @@ -0,0 +1,271 @@ +/* + * Copyright (c) 2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = _stack_size; +HEAP_SIZE = _heap_size; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = _flash_size + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K + AHB_SRAM (w) : ORIGIN = 0xf0400000, LENGTH = 32K +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + KEEP(*(.vector_s_table)) + KEEP(*(.isr_s_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + /* RT-Thread related sections - Start */ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + . = ALIGN(8); + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + *(.tdata) + *(.tdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + *(.fast.*) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > ILM + + .bss (NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > DLM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > DLM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > DLM + + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > DLM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > DLM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/toolchains/gcc/initfini.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/toolchains/gcc/initfini.c new file mode 100644 index 00000000000..7d2b85799c8 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/toolchains/gcc/initfini.c @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2021-2022 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#ifndef USE_LIBC_INITFINI +#define USE_LIBC_INITFINI 0 +#endif + +#if USE_LIBC_INITFINI + +/* + * The _init() and _fini() will be called respectively when use __libc_init_array() + * and __libc_fnit_array() in libc.a to perform constructor and destructor handling. + * The dummy versions of these functions should be provided. + */ +void _init(void) +{ +} + +void _fini(void) +{ +} + +#else + +/* These magic symbols are provided by the linker. */ +extern void (*__preinit_array_start[])(void) __attribute__((weak)); +extern void (*__preinit_array_end[])(void) __attribute__((weak)); +extern void (*__init_array_start[])(void) __attribute__((weak)); +extern void (*__init_array_end[])(void) __attribute__((weak)); + +/* + * The __libc_init_array()/__libc_fnit_array() function is used to do global + * constructor/destructor and can NOT be compilied to generate the code coverage + * data. We have the function attribute to be 'no_profile_instrument_function' + * to prevent been instrumented for coverage analysis when GCOV=1 is applied. + */ +/* Iterate over all the init routines. */ +void __libc_init_array(void) __attribute__((no_profile_instrument_function)); +void __libc_init_array(void) +{ + uint32_t count; + uint32_t i; + + count = __preinit_array_end - __preinit_array_start; + for (i = 0; i < count; i++) { + __preinit_array_start[i](); + } + + count = __init_array_end - __init_array_start; + for (i = 0; i < count; i++) { + __init_array_start[i](); + } +} + +extern void (*__fini_array_start[])(void) __attribute__((weak)); +extern void (*__fini_array_end[])(void) __attribute__((weak)); + +/* Run all the cleanup routines. */ +void __libc_fini_array(void) __attribute__((no_profile_instrument_function)); +void __libc_fini_array(void) +{ + uint32_t count; + uint32_t i; + + count = __fini_array_end - __fini_array_start; + for (i = count; i > 0; i--) { + __fini_array_start[i - 1](); + } +} + +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/toolchains/gcc/ram.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/toolchains/gcc/ram.ld new file mode 100644 index 00000000000..7fa7529685d --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/toolchains/gcc/ram.ld @@ -0,0 +1,247 @@ +/* + * Copyright (c) 2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = _stack_size; +HEAP_SIZE = _heap_size; + +MEMORY +{ + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K + AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > ILM + + .vectors : { + . = ALIGN(8); + KEEP(*(.isr_vector)) + KEEP(*(.vector_table)) + KEEP(*(.isr_s_vector)) + KEEP(*(.vector_s_table)) + . = ALIGN(8); + } > ILM + + .rel : { + KEEP(*(.rel*)) + } > ILM + + .text : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + /* RT-Thread related sections - Start */ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + . = ALIGN(8); + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + } > ILM + + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + *(.fast.*) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > ILM + + .bss (NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > DLM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > DLM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > DLM + + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > DLM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > DLM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + __last_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); + ASSERT(((__fw_size__ <= LENGTH(ILM)) && (__last_addr__ <= (ORIGIN(ILM) + LENGTH(ILM)))), "****** FAILED! ILM has not enough space! ******") +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/toolchains/gcc/start.S b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/toolchains/gcc/start.S new file mode 100644 index 00000000000..a13b7d98415 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/toolchains/gcc/start.S @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2021-2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_csr_regs.h" + + .section .start, "ax" + + .global _start + .type _start,@function + +_start: + /* Initialize global pointer */ + .option push + .option norelax + la gp, __global_pointer$ + la tp, __thread_pointer$ + .option pop + + /* reset mstatus to 0*/ + csrrw x0, mstatus, x0 + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + +#ifdef INIT_EXT_RAM_FOR_DATA + la t0, _stack_safe + mv sp, t0 + call _init_ext_ram +#endif + + /* Initialize stack pointer */ + la t0, _stack + mv sp, t0 + +#ifdef CONFIG_NOT_ENABLE_ICACHE + call l1c_ic_disable +#else + call l1c_ic_enable +#endif +#ifdef CONFIG_NOT_ENABLE_DCACHE + call l1c_dc_invalidate_all + call l1c_dc_disable +#else + call l1c_dc_enable + call l1c_dc_invalidate_all +#endif + + /* + * Initialize LMA/VMA sections. + * Relocation for any sections that need to be copied from LMA to VMA. + */ + call c_startup + +#if defined(__SES_RISCV) + /* Initialize the heap */ + la a0, __heap_start__ + la a1, __heap_end__ + sub a1, a1, a0 + la t1, __SEGGER_RTL_init_heap + jalr t1 +#endif + + /* Do global constructors */ + call __libc_init_array + +#ifndef NO_CLEANUP_AT_START + /* clean up */ + call _clean_up +#endif + +#ifdef __nds_execit + /* Initialize EXEC.IT table */ + la t0, _ITB_BASE_ + csrw uitb, t0 +#endif + +#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS + #define HANDLER_TRAP freertos_risc_v_trap_handler + #define HANDLER_S_TRAP freertos_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 +#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III + #define HANDLER_TRAP ucos_risc_v_trap_handler + #define HANDLER_S_TRAP ucos_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 +#elif defined(CONFIG_THREADX) && CONFIG_THREADX + #define HANDLER_TRAP tx_risc_v_trap_handler + #define HANDLER_S_TRAP tx_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 + +#elif defined(CONFIG_RTTHREAD) && CONFIG_RTTHREAD + #define HANDLER_TRAP rtt_risc_v_trap_handler + #define HANDLER_S_TRAP rtt_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 + +#else + #define HANDLER_TRAP irq_handler_trap + #define HANDLER_S_TRAP irq_handler_s_trap +#endif + +#ifndef USE_NONVECTOR_MODE + /* Initial machine trap-vector Base */ + la t0, __vector_table + csrw mtvec, t0 + +#if defined (USE_S_MODE_IRQ) + la t0, __vector_s_table + csrw stvec, t0 +#endif + /* Enable vectored external PLIC interrupt */ + csrsi CSR_MMISC_CTL, 2 +#else + /* Initial machine trap-vector Base */ + la t0, HANDLER_TRAP + csrw mtvec, t0 +#if defined (USE_S_MODE_IRQ) + la t0, HANDLER_S_TRAP + csrw stvec, t0 +#endif + + /* Disable vectored external PLIC interrupt */ + csrci CSR_MMISC_CTL, 2 +#endif + + /* System reset handler */ + call reset_handler + + /* Infinite loop, if returned accidentally */ +1: j 1b + + .weak exit +exit: +1: j 1b + + .section .isr_vector, "ax" + .weak nmi_handler +nmi_handler: +1: j 1b + +#include "../vectors.h" diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/toolchains/reset.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/toolchains/reset.c new file mode 100644 index 00000000000..6a130f67550 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/toolchains/reset.c @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2022-2024 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" +#include "hpm_interrupt.h" + + +extern void system_init(void); + +#ifndef MAIN_ENTRY +#define MAIN_ENTRY main +#endif +extern int MAIN_ENTRY(void); + +__attribute__((weak)) void _clean_up(void) +{ + /* clean up plic, it will help while debugging */ + disable_irq_from_intc(); + intc_m_set_threshold(0); + for (uint32_t irq = 0; irq < 128; irq++) { + intc_m_complete_irq(irq); + } + /* clear any bits left in plic enable register */ + for (uint32_t i = 0; i < 4; i++) { + *(volatile uint32_t *)(HPM_PLIC_BASE + HPM_PLIC_ENABLE_OFFSET + (i << 2)) = 0; + } +} + +__attribute__((weak)) void c_startup(void) +{ + uint32_t i, size; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __tdata_start__[], __tdata_end__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + extern uint8_t __data_load_addr__[], __tdata_load_addr__[]; + extern uint8_t __fast_load_addr__[], __noncacheable_init_load_addr__[]; + +#if defined(FLASH_XIP) || defined(FLASH_UF2) + extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; + size = __vector_ram_end__ - __vector_ram_start__; + for (i = 0; i < size; i++) { + *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); + } +#endif + + /* bss section */ + size = __bss_end__ - __bss_start__; + for (i = 0; i < size; i++) { + *(__bss_start__ + i) = 0; + } + + /* noncacheable bss section */ + size = __noncacheable_bss_end__ - __noncacheable_bss_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_bss_start__ + i) = 0; + } + + /* data section LMA: etext */ + size = __data_end__ - __data_start__; + for (i = 0; i < size; i++) { + *(__data_start__ + i) = *(__data_load_addr__ + i); + } + + /* ramfunc section LMA: etext + data length */ + size = __ramfunc_end__ - __ramfunc_start__; + for (i = 0; i < size; i++) { + *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i); + } + + /* tdata section LMA: etext + data length + ramfunc length */ + size = __tdata_end__ - __tdata_start__; + for (i = 0; i < size; i++) { + *(__tdata_start__ + i) = *(__tdata_load_addr__ + i); + } + + /* noncacheable init section LMA: etext + data length + ramfunc legnth + tdata length*/ + size = __noncacheable_init_end__ - __noncacheable_init_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); + } +} + +__attribute__((weak)) int main(void) +{ + while (1) { + ; + } +} + +__attribute__((weak)) void reset_handler(void) +{ + fencei(); + + /* Call platform specific hardware initialization */ + system_init(); + + /* Entry function */ + MAIN_ENTRY(); +} + +/* + * When compiling C++ code with static objects, the compiler inserts + * a call to __cxa_atexit() with __dso_handle as one of the arguments. + * The dummy versions of these symbols should be provided. + */ +__attribute__((weak)) void __cxa_atexit(void (*arg1)(void *), void *arg2, void *arg3) +{ + (void) arg1; + (void) arg2; + (void) arg3; +} + +#if (!defined(__SEGGER_RTL_VERSION) || defined(__riscv_xandes)) && !defined(__ICCRISCV__) +void *__dso_handle = (void *) &__dso_handle; +#endif + +__attribute__((weak)) void _init(void) +{ +} + + +#ifdef __ICCRISCV__ +int __low_level_init(void) +{ +#ifdef IAR_MANUAL_COPY /* Enable this code snippet if the .isr_vector and .vector_table need to be copied to RAM manually */ +#pragma section = ".isr_vector" +#pragma section = ".isr_vector_init" +#pragma section = ".vector_table" +#pragma section = ".vector_table_init" + /* Initialize section .isr_vector, section .vector_table */ + uint8_t *__isr_vector_ram_start = __section_begin(".isr_vector"); + uint32_t __isr_vector_ram_size = __section_size(".isr_vector"); + uint8_t *__isr_vector_rom_start = __section_begin(".isr_vector_init"); + + for (uint32_t i = 0; i < __isr_vector_ram_size; i++) { + __isr_vector_ram_start[i] = __isr_vector_rom_start[i]; + } + + uint8_t *__vector_table_ram_start = __section_begin(".vector_table"); + uint32_t __vector_table_ram_size = __section_size(".vector_table"); + uint8_t *__vector_rom_start = __section_begin(".vector_table_init"); + + for (uint32_t i = 0; i < __vector_table_ram_size; i++) { + __vector_table_ram_start[i] = __vector_rom_start[i]; + } +#endif + + return 1; +} +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/toolchains/trap.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/toolchains/trap.c new file mode 100644 index 00000000000..9c084c3af17 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/toolchains/trap.c @@ -0,0 +1,191 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_soc.h" + +#ifdef __ICCRISCV__ +#pragma language = extended +#endif + +/********************** MCAUSE exception types **************************************/ +#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) /* !< Instruction Address misaligned */ +#define MCAUSE_INSTR_ACCESS_FAULT (1U) /* !< Instruction access fault */ +#define MCAUSE_ILLEGAL_INSTR (2U) /* !< Illegal instruction */ +#define MCAUSE_BREAKPOINT (3U) /* !< Breakpoint */ +#define MCAUSE_LOAD_ADDR_MISALIGNED (4U) /* !< Load address misaligned */ +#define MCAUSE_LOAD_ACCESS_FAULT (5U) /* !< Load access fault */ +#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U) /* !< Store/AMO address misaligned */ +#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U) /* !< Store/AMO access fault */ +#define MCAUSE_ECALL_FROM_USER_MODE (8U) /* !< Environment call from User mode */ +#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U) /* !< Environment call from Supervisor mode */ +#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U) /* !< Environment call from machine mode */ +#define MCAUSE_INSTR_PAGE_FAULT (12U) /* !< Instruction page fault */ +#define MCAUSE_LOAD_PAGE_FAULT (13) /* !< Load page fault */ +#define MCAUSE_STORE_AMO_PAGE_FAULT (15U) /* !< Store/AMO page fault */ + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +__attribute__((weak)) void mchtmr_isr(void) +{ +} + +__attribute__((weak)) void swi_isr(void) +{ +} + +__attribute__((weak)) void syscall_handler(long n, long a0, long a1, long a2, long a3) +{ + (void) n; + (void) a0; + (void) a1; + (void) a2; + (void) a3; +} + +__attribute__((weak)) long exception_handler(long cause, long epc) +{ + switch (cause) { + case MCAUSE_INSTR_ADDR_MISALIGNED: + break; + case MCAUSE_INSTR_ACCESS_FAULT: + break; + case MCAUSE_ILLEGAL_INSTR: + break; + case MCAUSE_BREAKPOINT: + break; + case MCAUSE_LOAD_ADDR_MISALIGNED: + break; + case MCAUSE_LOAD_ACCESS_FAULT: + break; + case MCAUSE_STORE_AMO_ADDR_MISALIGNED: + break; + case MCAUSE_STORE_AMO_ACCESS_FAULT: + break; + case MCAUSE_ECALL_FROM_USER_MODE: + break; + case MCAUSE_ECALL_FROM_SUPERVISOR_MODE: + break; + case MCAUSE_ECALL_FROM_MACHINE_MODE: + break; + case MCAUSE_INSTR_PAGE_FAULT: + break; + case MCAUSE_LOAD_PAGE_FAULT: + break; + case MCAUSE_STORE_AMO_PAGE_FAULT: + break; + default: + break; + } + /* Unhandled Trap */ + return epc; +} + +#if !defined(CONFIG_FREERTOS) && !defined(CONFIG_UCOS_III) && !defined(CONFIG_THREADX) && !defined(CONFIG_RTTHREAD) +HPM_ATTR_MACHINE_INTERRUPT void irq_handler_trap(void); +#define IRQ_HANDLER_TRAP_AS_ISR 1 +#else +void irq_handler_trap(void) __attribute__ ((section(".isr_vector"))); +#endif + +#if defined(__ICCRISCV__) && (IRQ_HANDLER_TRAP_AS_ISR == 1) +extern int __vector_table[]; +HPM_ATTR_MACHINE_INTERRUPT +#endif +void irq_handler_trap(void) +{ + long mcause = read_csr(CSR_MCAUSE); + long mepc = read_csr(CSR_MEPC); + long mstatus = read_csr(CSR_MSTATUS); +#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH + long mxstatus = read_csr(CSR_MXSTATUS); +#endif +#ifdef __riscv_dsp + int ucode = read_csr(CSR_UCODE); +#endif +#ifdef __riscv_flen + int fcsr = read_fcsr(); +#endif + + /* clobbers list for ecall */ +#ifdef __riscv_32e + __asm volatile("" : : : "t0", "a0", "a1", "a2", "a3"); +#else + __asm volatile("" : : : "a7", "a0", "a1", "a2", "a3"); +#endif + + /* Do your trap handling */ + if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_TIMER)) { + /* Machine timer interrupt */ + mchtmr_isr(); + } +#ifdef USE_NONVECTOR_MODE + else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_EXT)) { + + typedef void(*isr_func_t)(void); + + /* Machine-level interrupt from PLIC */ + uint32_t irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); + if (irq_index) { + /* Workaround: irq number returned by __plic_claim_irq might be 0, which is caused by plic. So skip invalid irq_index as a workaround */ +#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) + enable_global_irq(CSR_MSTATUS_MIE_MASK); +#endif + ((isr_func_t)__vector_table[irq_index])(); + __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index); + } + } +#endif + + else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_SOFT)) { + /* Machine SWI interrupt */ + intc_m_claim_swi(); + swi_isr(); + intc_m_complete_swi(); + } else if (!(mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == MCAUSE_ECALL_FROM_MACHINE_MODE)) { + /* Machine Syscal call */ + __asm volatile( + "mv a4, a3\n" + "mv a3, a2\n" + "mv a2, a1\n" + "mv a1, a0\n" + #ifdef __riscv_32e + "mv a0, t0\n" + #else + "mv a0, a7\n" + #endif + "jalr %0\n" + : : "r"(syscall_handler) : "a4" + ); + mepc += 4; + } else { + mepc = exception_handler(mcause, mepc); + } + + /* Restore CSR */ + write_csr(CSR_MSTATUS, mstatus); + write_csr(CSR_MEPC, mepc); +#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH + write_csr(CSR_MXSTATUS, mxstatus); +#endif +#ifdef __riscv_dsp + write_csr(CSR_UCODE, ucode); +#endif +#ifdef __riscv_flen + write_fcsr(fcsr); +#endif +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/toolchains/vectors.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/toolchains/vectors.h new file mode 100644 index 00000000000..8ad46b79ece --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5301/toolchains/vectors.h @@ -0,0 +1,271 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifdef __IAR_SYSTEMS_ASM__ + +IRQ_HANDLER macro + dc32 default_isr_\1 + endm + +IRQ_DEFAULT_HANDLER macro + PUBWEAK default_isr_\1 +default_isr_\1 + j default_irq_handler + endm + + SECTION `.isr_vector`:CODE:ROOT(9) + PUBWEAK default_irq_handler +default_irq_handler + j default_irq_handler + IRQ_DEFAULT_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_DEFAULT_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_DEFAULT_HANDLER 3 /* GPIO0_X IRQ handler */ + IRQ_DEFAULT_HANDLER 4 /* GPIO0_Y IRQ handler */ + IRQ_DEFAULT_HANDLER 5 /* GPTMR0 IRQ handler */ + IRQ_DEFAULT_HANDLER 6 /* GPTMR1 IRQ handler */ + IRQ_DEFAULT_HANDLER 7 /* Reserved */ + IRQ_DEFAULT_HANDLER 8 /* Reserved */ + IRQ_DEFAULT_HANDLER 9 /* Reserved */ + IRQ_DEFAULT_HANDLER 10 /* Reserved */ + IRQ_DEFAULT_HANDLER 11 /* Reserved */ + IRQ_DEFAULT_HANDLER 12 /* Reserved */ + IRQ_DEFAULT_HANDLER 13 /* UART0 IRQ handler */ + IRQ_DEFAULT_HANDLER 14 /* UART1 IRQ handler */ + IRQ_DEFAULT_HANDLER 15 /* UART2 IRQ handler */ + IRQ_DEFAULT_HANDLER 16 /* UART3 IRQ handler */ + IRQ_DEFAULT_HANDLER 17 /* Reserved */ + IRQ_DEFAULT_HANDLER 18 /* Reserved */ + IRQ_DEFAULT_HANDLER 19 /* Reserved */ + IRQ_DEFAULT_HANDLER 20 /* Reserved */ + IRQ_DEFAULT_HANDLER 21 /* I2C0 IRQ handler */ + IRQ_DEFAULT_HANDLER 22 /* I2C1 IRQ handler */ + IRQ_DEFAULT_HANDLER 23 /* I2C2 IRQ handler */ + IRQ_DEFAULT_HANDLER 24 /* I2C3 IRQ handler */ + IRQ_DEFAULT_HANDLER 25 /* SPI0 IRQ handler */ + IRQ_DEFAULT_HANDLER 26 /* SPI1 IRQ handler */ + IRQ_DEFAULT_HANDLER 27 /* SPI2 IRQ handler */ + IRQ_DEFAULT_HANDLER 28 /* SPI3 IRQ handler */ + IRQ_DEFAULT_HANDLER 29 /* TSNS IRQ handler */ + IRQ_DEFAULT_HANDLER 30 /* MBX0A IRQ handler */ + IRQ_DEFAULT_HANDLER 31 /* MBX0B IRQ handler */ + IRQ_DEFAULT_HANDLER 32 /* EWDG0 IRQ handler */ + IRQ_DEFAULT_HANDLER 33 /* EWDG1 IRQ handler */ + IRQ_DEFAULT_HANDLER 34 /* HDMA IRQ handler */ + IRQ_DEFAULT_HANDLER 35 /* Reserved */ + IRQ_DEFAULT_HANDLER 36 /* Reserved */ + IRQ_DEFAULT_HANDLER 37 /* Reserved */ + IRQ_DEFAULT_HANDLER 38 /* Reserved */ + IRQ_DEFAULT_HANDLER 39 /* Reserved */ + IRQ_DEFAULT_HANDLER 40 /* Reserved */ + IRQ_DEFAULT_HANDLER 41 /* Reserved */ + IRQ_DEFAULT_HANDLER 42 /* Reserved */ + IRQ_DEFAULT_HANDLER 43 /* Reserved */ + IRQ_DEFAULT_HANDLER 44 /* Reserved */ + IRQ_DEFAULT_HANDLER 45 /* Reserved */ + IRQ_DEFAULT_HANDLER 46 /* Reserved */ + IRQ_DEFAULT_HANDLER 47 /* Reserved */ + IRQ_DEFAULT_HANDLER 48 /* Reserved */ + IRQ_DEFAULT_HANDLER 49 /* Reserved */ + IRQ_DEFAULT_HANDLER 50 /* Reserved */ + IRQ_DEFAULT_HANDLER 51 /* USB0 IRQ handler */ + IRQ_DEFAULT_HANDLER 52 /* XPI0 IRQ handler */ + IRQ_DEFAULT_HANDLER 53 /* Reserved */ + IRQ_DEFAULT_HANDLER 54 /* PSEC IRQ handler */ + IRQ_DEFAULT_HANDLER 55 /* SECMON IRQ handler */ + IRQ_DEFAULT_HANDLER 56 /* Reserved */ + IRQ_DEFAULT_HANDLER 57 /* FUSE IRQ handler */ + IRQ_DEFAULT_HANDLER 58 /* ADC0 IRQ handler */ + IRQ_DEFAULT_HANDLER 59 /* Reserved */ + IRQ_DEFAULT_HANDLER 60 /* Reserved */ + IRQ_DEFAULT_HANDLER 61 /* Reserved */ + IRQ_DEFAULT_HANDLER 62 /* ACMP_0 IRQ handler */ + IRQ_DEFAULT_HANDLER 63 /* ACMP_1 IRQ handler */ + IRQ_DEFAULT_HANDLER 64 /* SYSCTL IRQ handler */ + IRQ_DEFAULT_HANDLER 65 /* PGPIO IRQ handler */ + IRQ_DEFAULT_HANDLER 66 /* PTMR IRQ handler */ + IRQ_DEFAULT_HANDLER 67 /* PUART IRQ handler */ + IRQ_DEFAULT_HANDLER 68 /* PEWDG IRQ handler */ + IRQ_DEFAULT_HANDLER 69 /* BROWNOUT IRQ handler */ + IRQ_DEFAULT_HANDLER 70 /* PAD_WAKEUP IRQ handler */ + IRQ_DEFAULT_HANDLER 71 /* DEBUG0 IRQ handler */ + IRQ_DEFAULT_HANDLER 72 /* DEBUG1 IRQ handler */ + + EXTERN irq_handler_trap + SECTION `.vector_table`:CODE:ROOT(9) + PUBLIC __vector_table + DATA + +__vector_table + dc32 irq_handler_trap + IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_HANDLER 3 /* GPIO0_X IRQ handler */ + IRQ_HANDLER 4 /* GPIO0_Y IRQ handler */ + IRQ_HANDLER 5 /* GPTMR0 IRQ handler */ + IRQ_HANDLER 6 /* GPTMR1 IRQ handler */ + IRQ_HANDLER 7 /* Reserved */ + IRQ_HANDLER 8 /* Reserved */ + IRQ_HANDLER 9 /* Reserved */ + IRQ_HANDLER 10 /* Reserved */ + IRQ_HANDLER 11 /* Reserved */ + IRQ_HANDLER 12 /* Reserved */ + IRQ_HANDLER 13 /* UART0 IRQ handler */ + IRQ_HANDLER 14 /* UART1 IRQ handler */ + IRQ_HANDLER 15 /* UART2 IRQ handler */ + IRQ_HANDLER 16 /* UART3 IRQ handler */ + IRQ_HANDLER 17 /* Reserved */ + IRQ_HANDLER 18 /* Reserved */ + IRQ_HANDLER 19 /* Reserved */ + IRQ_HANDLER 20 /* Reserved */ + IRQ_HANDLER 21 /* I2C0 IRQ handler */ + IRQ_HANDLER 22 /* I2C1 IRQ handler */ + IRQ_HANDLER 23 /* I2C2 IRQ handler */ + IRQ_HANDLER 24 /* I2C3 IRQ handler */ + IRQ_HANDLER 25 /* SPI0 IRQ handler */ + IRQ_HANDLER 26 /* SPI1 IRQ handler */ + IRQ_HANDLER 27 /* SPI2 IRQ handler */ + IRQ_HANDLER 28 /* SPI3 IRQ handler */ + IRQ_HANDLER 29 /* TSNS IRQ handler */ + IRQ_HANDLER 30 /* MBX0A IRQ handler */ + IRQ_HANDLER 31 /* MBX0B IRQ handler */ + IRQ_HANDLER 32 /* EWDG0 IRQ handler */ + IRQ_HANDLER 33 /* EWDG1 IRQ handler */ + IRQ_HANDLER 34 /* HDMA IRQ handler */ + IRQ_HANDLER 35 /* Reserved */ + IRQ_HANDLER 36 /* Reserved */ + IRQ_HANDLER 37 /* Reserved */ + IRQ_HANDLER 38 /* Reserved */ + IRQ_HANDLER 39 /* Reserved */ + IRQ_HANDLER 40 /* Reserved */ + IRQ_HANDLER 41 /* Reserved */ + IRQ_HANDLER 42 /* Reserved */ + IRQ_HANDLER 43 /* Reserved */ + IRQ_HANDLER 44 /* Reserved */ + IRQ_HANDLER 45 /* Reserved */ + IRQ_HANDLER 46 /* Reserved */ + IRQ_HANDLER 47 /* Reserved */ + IRQ_HANDLER 48 /* Reserved */ + IRQ_HANDLER 49 /* Reserved */ + IRQ_HANDLER 50 /* Reserved */ + IRQ_HANDLER 51 /* USB0 IRQ handler */ + IRQ_HANDLER 52 /* XPI0 IRQ handler */ + IRQ_HANDLER 53 /* Reserved */ + IRQ_HANDLER 54 /* PSEC IRQ handler */ + IRQ_HANDLER 55 /* SECMON IRQ handler */ + IRQ_HANDLER 56 /* Reserved */ + IRQ_HANDLER 57 /* FUSE IRQ handler */ + IRQ_HANDLER 58 /* ADC0 IRQ handler */ + IRQ_HANDLER 59 /* Reserved */ + IRQ_HANDLER 60 /* Reserved */ + IRQ_HANDLER 61 /* Reserved */ + IRQ_HANDLER 62 /* ACMP_0 IRQ handler */ + IRQ_HANDLER 63 /* ACMP_1 IRQ handler */ + IRQ_HANDLER 64 /* SYSCTL IRQ handler */ + IRQ_HANDLER 65 /* PGPIO IRQ handler */ + IRQ_HANDLER 66 /* PTMR IRQ handler */ + IRQ_HANDLER 67 /* PUART IRQ handler */ + IRQ_HANDLER 68 /* PEWDG IRQ handler */ + IRQ_HANDLER 69 /* BROWNOUT IRQ handler */ + IRQ_HANDLER 70 /* PAD_WAKEUP IRQ handler */ + IRQ_HANDLER 71 /* DEBUG0 IRQ handler */ + IRQ_HANDLER 72 /* DEBUG1 IRQ handler */ + +#else + +.global default_irq_handler +.weak default_irq_handler +.align 2 +default_irq_handler: +1: j 1b + +.macro IRQ_HANDLER irq + .weak default_isr_\irq + .set default_isr_\irq, default_irq_handler + .long default_isr_\irq +.endm + +.section .vector_table, "a" +.global __vector_table +.align 9 + +__vector_table: + .weak default_isr_trap + .set default_isr_trap, irq_handler_trap + .long default_isr_trap + IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_HANDLER 3 /* GPIO0_X IRQ handler */ + IRQ_HANDLER 4 /* GPIO0_Y IRQ handler */ + IRQ_HANDLER 5 /* GPTMR0 IRQ handler */ + IRQ_HANDLER 6 /* GPTMR1 IRQ handler */ + IRQ_HANDLER 7 /* Reserved */ + IRQ_HANDLER 8 /* Reserved */ + IRQ_HANDLER 9 /* Reserved */ + IRQ_HANDLER 10 /* Reserved */ + IRQ_HANDLER 11 /* Reserved */ + IRQ_HANDLER 12 /* Reserved */ + IRQ_HANDLER 13 /* UART0 IRQ handler */ + IRQ_HANDLER 14 /* UART1 IRQ handler */ + IRQ_HANDLER 15 /* UART2 IRQ handler */ + IRQ_HANDLER 16 /* UART3 IRQ handler */ + IRQ_HANDLER 17 /* Reserved */ + IRQ_HANDLER 18 /* Reserved */ + IRQ_HANDLER 19 /* Reserved */ + IRQ_HANDLER 20 /* Reserved */ + IRQ_HANDLER 21 /* I2C0 IRQ handler */ + IRQ_HANDLER 22 /* I2C1 IRQ handler */ + IRQ_HANDLER 23 /* I2C2 IRQ handler */ + IRQ_HANDLER 24 /* I2C3 IRQ handler */ + IRQ_HANDLER 25 /* SPI0 IRQ handler */ + IRQ_HANDLER 26 /* SPI1 IRQ handler */ + IRQ_HANDLER 27 /* SPI2 IRQ handler */ + IRQ_HANDLER 28 /* SPI3 IRQ handler */ + IRQ_HANDLER 29 /* TSNS IRQ handler */ + IRQ_HANDLER 30 /* MBX0A IRQ handler */ + IRQ_HANDLER 31 /* MBX0B IRQ handler */ + IRQ_HANDLER 32 /* EWDG0 IRQ handler */ + IRQ_HANDLER 33 /* EWDG1 IRQ handler */ + IRQ_HANDLER 34 /* HDMA IRQ handler */ + IRQ_HANDLER 35 /* Reserved */ + IRQ_HANDLER 36 /* Reserved */ + IRQ_HANDLER 37 /* Reserved */ + IRQ_HANDLER 38 /* Reserved */ + IRQ_HANDLER 39 /* Reserved */ + IRQ_HANDLER 40 /* Reserved */ + IRQ_HANDLER 41 /* Reserved */ + IRQ_HANDLER 42 /* Reserved */ + IRQ_HANDLER 43 /* Reserved */ + IRQ_HANDLER 44 /* Reserved */ + IRQ_HANDLER 45 /* Reserved */ + IRQ_HANDLER 46 /* Reserved */ + IRQ_HANDLER 47 /* Reserved */ + IRQ_HANDLER 48 /* Reserved */ + IRQ_HANDLER 49 /* Reserved */ + IRQ_HANDLER 50 /* Reserved */ + IRQ_HANDLER 51 /* USB0 IRQ handler */ + IRQ_HANDLER 52 /* XPI0 IRQ handler */ + IRQ_HANDLER 53 /* Reserved */ + IRQ_HANDLER 54 /* PSEC IRQ handler */ + IRQ_HANDLER 55 /* SECMON IRQ handler */ + IRQ_HANDLER 56 /* Reserved */ + IRQ_HANDLER 57 /* FUSE IRQ handler */ + IRQ_HANDLER 58 /* ADC0 IRQ handler */ + IRQ_HANDLER 59 /* Reserved */ + IRQ_HANDLER 60 /* Reserved */ + IRQ_HANDLER 61 /* Reserved */ + IRQ_HANDLER 62 /* ACMP_0 IRQ handler */ + IRQ_HANDLER 63 /* ACMP_1 IRQ handler */ + IRQ_HANDLER 64 /* SYSCTL IRQ handler */ + IRQ_HANDLER 65 /* PGPIO IRQ handler */ + IRQ_HANDLER 66 /* PTMR IRQ handler */ + IRQ_HANDLER 67 /* PUART IRQ handler */ + IRQ_HANDLER 68 /* PEWDG IRQ handler */ + IRQ_HANDLER 69 /* BROWNOUT IRQ handler */ + IRQ_HANDLER 70 /* PAD_WAKEUP IRQ handler */ + IRQ_HANDLER 71 /* DEBUG0 IRQ handler */ + IRQ_HANDLER 72 /* DEBUG1 IRQ handler */ + +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/HPM5361_svd.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/HPM5361_svd.xml new file mode 100644 index 00000000000..3ded9db278c --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/HPM5361_svd.xml @@ -0,0 +1,29190 @@ + + + HPMICRO + HPM5361 + HPM5300 + 1.0 + HPM5300 device + + /* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + + + other + r0p0 + little + false + true + true + 7 + false + + + + 8 + 32 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + + + FGPIO + FGPIO + GPIO + 0xc0000 + + 0x0 + 0x8f0 + registers + + + + 15 + 0x10 + gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy + DI[%s] + no description available + 0x0 + + VALUE + GPIO input value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-only + + + + + + 15 + 0x10 + gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy + DO[%s] + no description available + 0x100 + + VALUE + GPIO output value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + SET + GPIO output set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + CLEAR + GPIO output clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + TOGGLE + GPIO output toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + + 15 + 0x10 + gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy + OE[%s] + no description available + 0x200 + + VALUE + GPIO direction value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + SET + GPIO direction set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + CLEAR + GPIO direction clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + TOGGLE + GPIO direction toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + + 15 + 0x10 + gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy + IF[%s] + no description available + 0x300 + + VALUE + GPIO interrupt flag value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + write-only + + + + + + 15 + 0x10 + gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy + IE[%s] + no description available + 0x400 + + VALUE + GPIO interrupt enable value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + SET + GPIO interrupt enable set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + CLEAR + GPIO interrupt enable clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + TOGGLE + GPIO interrupt enable toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + + 15 + 0x10 + gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy + PL[%s] + no description available + 0x500 + + VALUE + GPIO interrupt polarity value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + SET + GPIO interrupt polarity set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + CLEAR + GPIO interrupt polarity clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + TOGGLE + GPIO interrupt polarity toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + + 15 + 0x10 + gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy + TP[%s] + no description available + 0x600 + + VALUE + GPIO interrupt type value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + SET + GPIO interrupt type set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + CLEAR + GPIO interrupt type clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TOGGLE + GPIO interrupt type toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + + 15 + 0x10 + gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy + AS[%s] + no description available + 0x700 + + VALUE + GPIO interrupt asynchronous value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + SET + GPIO interrupt asynchronous set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + CLEAR + GPIO interrupt asynchronous clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + TOGGLE + GPIO interrupt asynchronous toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + + 15 + 0x10 + gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy + PD[%s] + no description available + 0x800 + + VALUE + GPIO dual edge interrupt enable value + 0x0 + 32 + 0x00000000 + 0x00000001 + + + IRQ_DUAL + GPIO dual edge interrupt enable +0: single edge interrupt +1: dual edge interrupt enable + 0 + 1 + read-write + + + + + SET + GPIO dual edge interrupt enable set + 0x4 + 32 + 0x00000000 + 0x00000001 + + + IRQ_DUAL + GPIO dual edge interrupt enable set +0: keep original edge interrupt type +1: dual edge interrupt enable + 0 + 1 + read-write + + + + + CLEAR + GPIO dual edge interrupt enable clear + 0x8 + 32 + 0x00000000 + 0x00000001 + + + IRQ_DUAL + GPIO dual edge interrupt enable clear +0: keep original edge interrupt type +1: single edge interrupt enable + 0 + 1 + read-write + + + + + TOGGLE + GPIO dual edge interrupt enable toggle + 0xc + 32 + 0x00000000 + 0x00000001 + + + IRQ_DUAL + GPIO dual edge interrupt enable toggle +0: keep original edge interrupt type +1: change original edge interrupt type to another one. + 0 + 1 + read-write + + + + + + + + GPIO0 + GPIO0 + GPIO + 0xf00d0000 + + + PGPIO + PGPIO + GPIO + 0xf411c000 + + + PLIC + PLIC + PLIC + 0xe4000000 + + 0x0 + 0x201000 + registers + + + + feature + Feature enable register + 0x0 + 32 + 0x00000000 + 0x00000003 + + + VECTORED + Vector mode enable +0: Disabled +1: Enabled + 1 + 1 + read-write + + + PREEMPT + Preemptive priority interrupt enable +0: Disabled +1: Enabled + 0 + 1 + read-write + + + + + 127 + 0x4 + PRIORITY1,PRIORITY2,PRIORITY3,PRIORITY4,PRIORITY5,PRIORITY6,PRIORITY7,PRIORITY8,PRIORITY9,PRIORITY10,PRIORITY11,PRIORITY12,PRIORITY13,PRIORITY14,PRIORITY15,PRIORITY16,PRIORITY17,PRIORITY18,PRIORITY19,PRIORITY20,PRIORITY21,PRIORITY22,PRIORITY23,PRIORITY24,PRIORITY25,PRIORITY26,PRIORITY27,PRIORITY28,PRIORITY29,PRIORITY30,PRIORITY31,PRIORITY32,PRIORITY33,PRIORITY34,PRIORITY35,PRIORITY36,PRIORITY37,PRIORITY38,PRIORITY39,PRIORITY40,PRIORITY41,PRIORITY42,PRIORITY43,PRIORITY44,PRIORITY45,PRIORITY46,PRIORITY47,PRIORITY48,PRIORITY49,PRIORITY50,PRIORITY51,PRIORITY52,PRIORITY53,PRIORITY54,PRIORITY55,PRIORITY56,PRIORITY57,PRIORITY58,PRIORITY59,PRIORITY60,PRIORITY61,PRIORITY62,PRIORITY63,PRIORITY64,PRIORITY65,PRIORITY66,PRIORITY67,PRIORITY68,PRIORITY69,PRIORITY70,PRIORITY71,PRIORITY72,PRIORITY73,PRIORITY74,PRIORITY75,PRIORITY76,PRIORITY77,PRIORITY78,PRIORITY79,PRIORITY80,PRIORITY81,PRIORITY82,PRIORITY83,PRIORITY84,PRIORITY85,PRIORITY86,PRIORITY87,PRIORITY88,PRIORITY89,PRIORITY90,PRIORITY91,PRIORITY92,PRIORITY93,PRIORITY94,PRIORITY95,PRIORITY96,PRIORITY97,PRIORITY98,PRIORITY99,PRIORITY100,PRIORITY101,PRIORITY102,PRIORITY103,PRIORITY104,PRIORITY105,PRIORITY106,PRIORITY107,PRIORITY108,PRIORITY109,PRIORITY110,PRIORITY111,PRIORITY112,PRIORITY113,PRIORITY114,PRIORITY115,PRIORITY116,PRIORITY117,PRIORITY118,PRIORITY119,PRIORITY120,PRIORITY121,PRIORITY122,PRIORITY123,PRIORITY124,PRIORITY125,PRIORITY126,PRIORITY127 + PRIORITY[%s] + no description available + 0x4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + 4 + 0x4 + PENDING0,PENDING1,PENDING2,PENDING3 + PENDING[%s] + no description available + 0x1000 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + 4 + 0x4 + TRIGGER0,TRIGGER1,TRIGGER2,TRIGGER3 + TRIGGER[%s] + no description available + 0x1080 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. +0: Level-triggered interrupt +1: Edge-triggered interrupt + 0 + 32 + read-only + + + + + NUMBER + Number of supported interrupt sources and targets + 0x1100 + 32 + 0xFFFFFFFF + + + NUM_TARGET + The number of supported targets + 16 + 16 + read-only + + + NUM_INTERRUPT + The number of supported interrupt sources + 0 + 16 + read-only + + + + + INFO + Version and the maximum priority + 0x1104 + 32 + 0xFFFFFFFF + + + MAX_PRIORITY + The maximum priority supported + 16 + 16 + read-only + + + VERSION + The version of the PLIC design + 0 + 16 + read-only + + + + + 1 + 0x80 + target0 + TARGETINT[%s] + no description available + 0x2000 + + 4 + 0x4 + INTEN0,INTEN1,INTEN2,INTEN3 + INTEN[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + + 1 + 0x1000 + target0 + TARGETCONFIG[%s] + no description available + 0x200000 + + THRESHOLD + Target0 priority threshold + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + THRESHOLD + Interrupt priority threshold. + 0 + 32 + read-write + + + + + CLAIM + Target claim and complete + 0x4 + 32 + 0x00000000 + 0x000003FF + + + INTERRUPT_ID + On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). + 0 + 10 + read-write + + + + + PPS + Preempted priority stack + 0x400 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY_PREEMPTED + Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. + 0 + 32 + read-write + + + + + + + + MCHTMR + MCHTMR + MCHTMR + 0xe6000000 + + 0x0 + 0x10 + registers + + + + MTIME + Machine Time + 0x0 + 64 + 0x0000000000020210 + 0xFFFFFFFFFFFFFFFF + + + MTIME + Machine time + 0 + 64 + read-write + + + + + MTIMECMP + Machine Time Compare + 0x8 + 64 + 0x0000000000020210 + 0xFFFFFFFFFFFFFFFF + + + MTIMECMP + Machine time compare + 0 + 64 + read-write + + + + + + + PLICSW + PLICSW + PLIC_SW + 0xe6400000 + + 0x1000 + 0x1ff008 + registers + + + + PENDING + Pending status + 0x1000 + 32 + 0x00000000 + 0x00000002 + + + INTERRUPT + writing 1 to trigger software interrupt + 1 + 1 + read-write + + + + + INTEN + Interrupt enable + 0x2000 + 32 + 0x00000000 + 0x00000001 + + + INTERRUPT + enable software interrupt + 0 + 1 + read-write + + + + + CLAIM + Claim and complete. + 0x200004 + 32 + 0x00000000 + 0x00000001 + + + INTERRUPT_ID + On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). + 0 + 1 + read-write + + + + + + + GPTMR0 + GPTMR0 + TMR + 0xf0000000 + + 0x0 + 0x20c + registers + + + + 4 + 0x40 + ch0,ch1,ch2,ch3 + CHANNEL[%s] + no description available + 0x0 + + CR + Control Register + 0x0 + 32 + 0x00000000 + 0x80007FFF + + + CNTUPT + 1- update counter to new value as CNTUPTVAL +This bit will be auto cleared after 1 cycle + 31 + 1 + write-only + + + CNTRST + 1- reset counter + 14 + 1 + read-write + + + SYNCFLW + 1- enable this channel to reset counter to reload(RLD) together with its previous channel. +This bit is not valid for channel 0. + 13 + 1 + read-write + + + SYNCIFEN + 1- SYNCI is valid on its falling edge + 12 + 1 + read-write + + + SYNCIREN + 1- SYNCI is valid on its rising edge + 11 + 1 + read-write + + + CEN + 1- counter enable + 10 + 1 + read-write + + + CMPINIT + Output compare initial poliarity +1- The channel output initial level is high +0- The channel output initial level is low +User should set this bit before set CMPEN to 1. + 9 + 1 + read-write + + + CMPEN + 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. + 8 + 1 + read-write + + + DMASEL + select one of DMA request: +00- CMP0 flag +01- CMP1 flag +10- Input signal toggle captured +11- RLD flag, counter reload; + 6 + 2 + read-write + + + DMAEN + 1- enable dma + 5 + 1 + read-write + + + SWSYNCIEN + 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set + 4 + 1 + read-write + + + DBGPAUSE + 1- counter will pause if chip is in debug mode + 3 + 1 + read-write + + + CAPMODE + This bitfield define the input capture mode +100: width measure mode, timer will calculate the input signal period and duty cycle +011: capture at both rising edge and falling edge +010: capture at falling edge +001: capture at rising edge +000: No capture + 0 + 3 + read-write + + + + + 2 + 0x4 + CMP0,CMP1 + CMP[%s] + no description available + 0x4 + 32 + 0xFFFFFFF0 + 0xFFFFFFFF + + + CMP + compare value 0 + 0 + 32 + read-write + + + + + RLD + Reload register + 0xc + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + RLD + reload value + 0 + 32 + read-write + + + + + CNTUPTVAL + Counter update value register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTUPTVAL + counter will be set to this value when software write cntupt bit in CR + 0 + 32 + read-write + + + + + CAPPOS + Capture rising edge register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPOS + This register contains the counter value captured at input signal rising edge + 0 + 32 + read-only + + + + + CAPNEG + Capture falling edge register + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + This register contains the counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPPRD + PWM period measure register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPRD + This register contains the input signal period when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CAPDTY + PWM duty cycle measure register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + MEAS_HIGH + This register contains the input signal duty cycle when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CNT + Counter + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + 32 bit counter value + 0 + 32 + read-only + + + + + + SR + Status register + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH3CMP1F + channel 3 compare value 1 match flag + 15 + 1 + write-only + + + CH3CMP0F + channel 3 compare value 1 match flag + 14 + 1 + write-only + + + CH3CAPF + channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 13 + 1 + write-only + + + CH3RLDF + channel 3 counter reload flag + 12 + 1 + write-only + + + CH2CMP1F + channel 2 compare value 1 match flag + 11 + 1 + write-only + + + CH2CMP0F + channel 2 compare value 1 match flag + 10 + 1 + write-only + + + CH2CAPF + channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 9 + 1 + write-only + + + CH2RLDF + channel 2 counter reload flag + 8 + 1 + write-only + + + CH1CMP1F + channel 1 compare value 1 match flag + 7 + 1 + write-only + + + CH1CMP0F + channel 1 compare value 1 match flag + 6 + 1 + write-only + + + CH1CAPF + channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 5 + 1 + write-only + + + CH1RLDF + channel 1 counter reload flag + 4 + 1 + write-only + + + CH0CMP1F + channel 1 compare value 1 match flag + 3 + 1 + write-only + + + CH0CMP0F + channel 1 compare value 1 match flag + 2 + 1 + write-only + + + CH0CAPF + channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 1 + 1 + write-only + + + CH0RLDF + channel 1 counter reload flag + 0 + 1 + write-only + + + + + IRQEN + Interrupt request enable register + 0x204 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH3CMP1EN + 1- generate interrupt request when ch3cmp1f flag is set + 15 + 1 + read-write + + + CH3CMP0EN + 1- generate interrupt request when ch3cmp0f flag is set + 14 + 1 + read-write + + + CH3CAPEN + 1- generate interrupt request when ch3capf flag is set + 13 + 1 + read-write + + + CH3RLDEN + 1- generate interrupt request when ch3rldf flag is set + 12 + 1 + read-write + + + CH2CMP1EN + 1- generate interrupt request when ch2cmp1f flag is set + 11 + 1 + read-write + + + CH2CMP0EN + 1- generate interrupt request when ch2cmp0f flag is set + 10 + 1 + read-write + + + CH2CAPEN + 1- generate interrupt request when ch2capf flag is set + 9 + 1 + read-write + + + CH2RLDEN + 1- generate interrupt request when ch2rldf flag is set + 8 + 1 + read-write + + + CH1CMP1EN + 1- generate interrupt request when ch1cmp1f flag is set + 7 + 1 + read-write + + + CH1CMP0EN + 1- generate interrupt request when ch1cmp0f flag is set + 6 + 1 + read-write + + + CH1CAPEN + 1- generate interrupt request when ch1capf flag is set + 5 + 1 + read-write + + + CH1RLDEN + 1- generate interrupt request when ch1rldf flag is set + 4 + 1 + read-write + + + CH0CMP1EN + 1- generate interrupt request when ch0cmp1f flag is set + 3 + 1 + read-write + + + CH0CMP0EN + 1- generate interrupt request when ch0cmp0f flag is set + 2 + 1 + read-write + + + CH0CAPEN + 1- generate interrupt request when ch0capf flag is set + 1 + 1 + read-write + + + CH0RLDEN + 1- generate interrupt request when ch0rldf flag is set + 0 + 1 + read-write + + + + + GCR + Global control register + 0x208 + 32 + 0x00000000 + 0x0000000F + + + SWSYNCT + set this bitfield to trigger software counter sync event + 0 + 4 + read-write + + + + + + + GPTMR1 + GPTMR1 + TMR + 0xf0004000 + + + GPTMR2 + GPTMR2 + TMR + 0xf0008000 + + + GPTMR3 + GPTMR3 + TMR + 0xf000c000 + + + PTMR + PTMR + TMR + 0xf4120000 + + + UART0 + UART0 + UART + 0xf0040000 + + 0x4 + 0x3c + registers + + + + IDLE_CFG + Idle Configuration Register + 0x4 + 32 + 0x00000000 + 0x03FF0BFF + + + TX_IDLE_COND + IDLE Detection Condition +0 - Treat as idle if TX pin is logic one +1 - Treat as idle if UART state machine state is idle + 25 + 1 + read-write + + + TX_IDLE_EN + UART TX Idle Detect Enable +0 - Disable +1 - Enable + 24 + 1 + read-write + + + TX_IDLE_THR + Threshold for UART transmit Idle detection (in terms of bits) + 16 + 8 + read-write + + + RXEN + UART receive enable. +0 - hold RX input to high, avoide wrong data input when config pinmux +1 - bypass RX input from PIN +software should set it after config pinmux + 11 + 1 + read-write + + + RX_IDLE_COND + IDLE Detection Condition +0 - Treat as idle if RX pin is logic one +1 - Treat as idle if UART state machine state is idle + 9 + 1 + read-write + + + RX_IDLE_EN + UART Idle Detect Enable +0 - Disable +1 - Enable +it should be enabled if enable address match feature + 8 + 1 + read-write + + + RX_IDLE_THR + Threshold for UART Receive Idle detection (in terms of bits) + 0 + 8 + read-write + + + + + ADDR_CFG + address match config register + 0x8 + 32 + 0x00000000 + 0x001FFFFF + + + TXEN_9BIT + set to use 9bit mode for transmitter, +will set the MSB for the first character as address flag, keep 0 for others. + 20 + 1 + read-write + + + RXEN_ADDR_MSB + set to use MSB as address flag at receiver(actually this is done by software set correct MSB in addr0/addr1). +Clr to use first character as address. +Only needed if enable address match feature + 19 + 1 + read-write + + + RXEN_9BIT + set to use 9bit mode for receiver, only valid if rxen_addr_msb is set + 18 + 1 + read-write + + + A1_EN + enable addr1 compare for the first character. +If a1_en OR a0_en, then do not receive data if address not match. +If ~a1_en AND ~a0_en, the receive all data like before. +NOTE: should set idle_tmout_en if enable address match feature + 17 + 1 + read-write + + + A0_EN + enable addr0 compare for the first character + 16 + 1 + read-write + + + ADDR1 + address 1 fileld. +in 9bit mode, this is the full address byte. +For other mode(8/7/6/5bit), MSB should be set for address flag. +If want address==0 to be matched at 8bit mode, should set addr1=0x80 + 8 + 8 + read-write + + + ADDR0 + address 0 field. + 0 + 8 + read-write + + + + + IIR2 + Interrupt Identification Register2 + 0xc + 32 + 0x00000001 + 0xF80000CF + + + RXIDLE_FLAG + UART RX IDLE Flag, assert after rxd high and then rx idle timeout, write one clear +0 - UART RX is busy +1 - UART RX is idle + 31 + 1 + write-only + + + TXIDLE_FLAG + UART TX IDLE Flag, assert after txd high and then tx idle timeout, write one clear +0 - UART TX is busy +1 - UART TX is idle + 30 + 1 + write-only + + + ADDR_MATCH + address match irq status, assert if either address match(and enabled). Write one clear +NOTE: the address byte may not moved by DMA at this point. +User can wait next addr_match_idle irq for the whole data include address + 29 + 1 + write-only + + + ADDR_MATCH_IDLE + address match and idle irq status, assert at rx bus idle if address match event triggered. +Write one clear; + 28 + 1 + write-only + + + DATA_LOST + assert if data lost before address match status, write one clear; +It will not assert if no address match occurs + 27 + 1 + write-only + + + FIFOED + FIFOs enabled +These two bits are 1 when bit 0 of the FIFO Control +Register (FIFOE) is set to 1. + 6 + 2 + read-only + + + INTRID + Interrupt ID, see IIR2 for detail decoding + 0 + 4 + read-only + + + + + Cfg + Configuration Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + FIFOSIZE + The depth of RXFIFO and TXFIFO +0: 16-byte FIFO +1: 32-byte FIFO +2: 64-byte FIFO +3: 128-byte FIFO + 0 + 2 + read-only + + + + + OSCR + Over Sample Control Register + 0x14 + 32 + 0x00000010 + 0x0000001F + + + OSC + Over-sample control +The value must be an even number; any odd value +writes to this field will be converted to an even value. +OSC=0: reserved +OSC<=8: The over-sample ratio is 8 +8 < OSC< 32: The over sample ratio is OSC + 0 + 5 + read-write + + + + + FCRR + FIFO Control Register config + 0x18 + 32 + 0x00000000 + 0x008F0FFF + + + FIFOT4EN + set to use new 4bit fifo threshold(TFIFOT4 and RFIFOT4) +clr to use 2bit(TFIFOT and RFIFOT) + 23 + 1 + read-write + + + TFIFOT4 + txfifo threshold(0 for 1byte, 0xF for 16bytes), uart will send tx_dma_req when data in fifo is less than threshold. + 16 + 4 + read-write + + + RFIFOT4 + rxfifo threshold(0 for 1byte, 0xF for 16bytes). +Uart will send rx_dma_req if data in fifo reachs the threshold, also will set the rxdata irq if enabled + 8 + 4 + read-write + + + RFIFOT + Receiver FIFO trigger level + 6 + 2 + read-write + + + TFIFOT + Transmitter FIFO trigger level + 4 + 2 + read-write + + + DMAE + DMA enable +0: Disable +1: Enable + 3 + 1 + read-write + + + TFIFORST + Transmitter FIFO reset +Write 1 to clear all bytes in the TXFIFO and resets its +counter. The Transmitter Shift Register is not cleared. +This bit will automatically be cleared. + 2 + 1 + write-only + + + RFIFORST + Receiver FIFO reset +Write 1 to clear all bytes in the RXFIFO and resets its +counter. The Receiver Shift Register is not cleared. +This bit will automatically be cleared. + 1 + 1 + write-only + + + FIFOE + FIFO enable +Write 1 to enable both the transmitter and receiver +FIFOs. +The FIFOs are reset when the value of this bit toggles. + 0 + 1 + read-write + + + + + MOTO_CFG + moto system control register + 0x1c + 32 + 0x00000000 + 0x8000FFF0 + + + SWTRG + software trigger. User should avoid use sw/hw trigger at same time, otherwise result unknown. +Hardware auto reset. + 31 + 1 + write-only + + + TXSTP_BITS + if TXSTOP_INSERT is enabled, the STOP bits to be inserted between each byte. 0 for 1 bit; 0xFF for 256bits + 8 + 8 + read-write + + + HWTRG_EN + set to enable hardware trigger(trigger from moto is shared by other UART) + 7 + 1 + read-write + + + TRG_MODE + set to enable trigger mode. +software should push needed data into txbuffer frist, uart will not start transmission at this time. +User should send trigger signal(by hw or sw), uart will send all data in txfifo till empty +NOTE: the hw_trigger should be pulse signal from trig mux. + 6 + 1 + read-write + + + TRG_CLR_RFIFO + set to enable the feature that, clear rxfifo at tx trigger(sw or hw), avoid unexpected data in rxfifo. + 5 + 1 + read-write + + + TXSTOP_INSERT + set to insert STOP bits between each tx byte till tx fifo empty. +NOTE: there will be no 1.5/2 STOP bits if enabled this feature, LCR.STB should be set to 0 if this bit is set + 4 + 1 + read-write + + + + + RBR + Receiver Buffer Register (when DLAB = 0) + UNION_20 + 0x20 + 32 + 0x00000000 + 0x000000FF + + + RBR + Receive data read port + 0 + 8 + read-only + + + + + THR + Transmitter Holding Register (when DLAB = 0) + UNION_20 + 0x20 + 32 + 0x00000000 + 0x000000FF + + + THR + Transmit data write port + 0 + 8 + write-only + + + + + DLL + Divisor Latch LSB (when DLAB = 1) + UNION_20 + 0x20 + 32 + 0x00000001 + 0x000000FF + + + DLL + Least significant byte of the Divisor Latch + 0 + 8 + read-write + + + + + IER + Interrupt Enable Register (when DLAB = 0) + UNION_24 + 0x24 + 32 + 0x00000000 + 0xF800000F + + + ERXIDLE + Enable Receive Idle interrupt +0 - Disable Idle interrupt +1 - Enable Idle interrupt + 31 + 1 + read-write + + + ETXIDLE + enable transmit idle interrupt + 30 + 1 + read-write + + + EADDRM + enable ADDR_MATCH interrupt + 29 + 1 + read-write + + + EADDRM_IDLE + enable ADDR_MATCH_IDLE interrupt + 28 + 1 + read-write + + + EDATLOST + enable DATA_LOST interrupt + 27 + 1 + read-write + + + EMSI + Enable modem status interrupt +The interrupt asserts when the status of one of the +following occurs: +The status of modem_rin, modem_dcdn, +modem_dsrn or modem_ctsn (If the auto-cts mode is +disabled) has been changed. +If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), +modem_ctsn would be used to control the transmitter. + 3 + 1 + read-write + + + ELSI + Enable receiver line status interrupt + 2 + 1 + read-write + + + ETHEI + Enable transmitter holding register interrupt + 1 + 1 + read-write + + + ERBI + Enable received data available interrupt and the +character timeout interrupt +0: Disable +1: Enable + 0 + 1 + read-write + + + + + DLM + Divisor Latch MSB (when DLAB = 1) + UNION_24 + 0x24 + 32 + 0x00000000 + 0x000000FF + + + DLM + Most significant byte of the Divisor Latch + 0 + 8 + read-write + + + + + IIR + Interrupt Identification Register + UNION_28 + 0x28 + 32 + 0x00000001 + 0x800000CF + + + RXIDLE_FLAG + UART IDLE Flag +0 - UART is busy +1 - UART is idle +NOTE: when write one to clear this bit, avoid changging FCR register since it's same address as IIR + 31 + 1 + write-only + + + FIFOED + FIFOs enabled +These two bits are 1 when bit 0 of the FIFO Control +Register (FIFOE) is set to 1. + 6 + 2 + read-only + + + INTRID + Interrupt ID, see IIR2 for detail decoding + 0 + 4 + read-only + + + + + FCR + FIFO Control Register + UNION_28 + 0x28 + 32 + 0x00000000 + 0x000000FF + + + RFIFOT + Receiver FIFO trigger level + 6 + 2 + write-only + + + TFIFOT + Transmitter FIFO trigger level + 4 + 2 + write-only + + + DMAE + DMA enable +0: Disable +1: Enable + 3 + 1 + write-only + + + TFIFORST + Transmitter FIFO reset +Write 1 to clear all bytes in the TXFIFO and resets its +counter. The Transmitter Shift Register is not cleared. +This bit will automatically be cleared. + 2 + 1 + write-only + + + RFIFORST + Receiver FIFO reset +Write 1 to clear all bytes in the RXFIFO and resets its +counter. The Receiver Shift Register is not cleared. +This bit will automatically be cleared. + 1 + 1 + write-only + + + FIFOE + FIFO enable +Write 1 to enable both the transmitter and receiver +FIFOs. +The FIFOs are reset when the value of this bit toggles. + 0 + 1 + write-only + + + + + LCR + Line Control Register + 0x2c + 32 + 0x00000000 + 0x000000FF + + + DLAB + Divisor latch access bit + 7 + 1 + read-write + + + BC + Break control + 6 + 1 + read-write + + + SPS + Stick parity +1: Parity bit is constant 0 or 1, depending on bit4 (EPS). +0: Disable the sticky bit parity. + 5 + 1 + read-write + + + EPS + Even parity select +1: Even parity (an even number of logic-1 is in the data +and parity bits) +0: Old parity. + 4 + 1 + read-write + + + PEN + Parity enable +When this bit is set, a parity bit is generated in +transmitted data before the first STOP bit and the parity +bit would be checked for the received data. + 3 + 1 + read-write + + + STB + Number of STOP bits +0: 1 bits +1: The number of STOP bit is based on the WLS setting +When WLS = 0, STOP bit is 1.5 bits +When WLS = 1, 2, 3, STOP bit is 2 bits + 2 + 1 + read-write + + + WLS + Word length setting +0: 5 bits +1: 6 bits +2: 7 bits +3: 8 bits + 0 + 2 + read-write + + + + + MCR + Modem Control Register ( + 0x30 + 32 + 0x00000000 + 0x00000032 + + + AFE + Auto flow control enable +0: Disable +1: The auto-CTS and auto-RTS setting is based on the +RTS bit setting: +When RTS = 0, auto-CTS only +When RTS = 1, auto-CTS and auto-RTS + 5 + 1 + read-write + + + LOOP + Enable loopback mode +0: Disable +1: Enable + 4 + 1 + read-write + + + RTS + Request to send +This bit controls the modem_rtsn output. +0: The modem_rtsn output signal will be driven HIGH +1: The modem_rtsn output signal will be driven LOW + 1 + 1 + read-write + + + + + LSR + Line Status Register + 0x34 + 32 + 0x00000000 + 0xC01F1FFF + + + RXIDLE + rxidle after timeout, clear after rx idle condition not match + 31 + 1 + read-only + + + TXIDLE + txidle after timeout, clear after tx idle condition not match + 30 + 1 + read-only + + + RFIFO_NUM + data bytes in rxfifo not read + 16 + 5 + read-only + + + TFIFO_NUM + data bytes in txfifo not sent + 8 + 5 + read-only + + + ERRF + Error in RXFIFO +In the FIFO mode, this bit is set when there is at least +one parity error, framing error, or line break +associated with data in the RXFIFO. It is cleared when +this register is read and there is no more error for the +rest of data in the RXFIFO. + 7 + 1 + read-only + + + TEMT + Transmitter empty +This bit is 1 when the THR (TXFIFO in the FIFO +mode) and the Transmitter Shift Register (TSR) are +both empty. Otherwise, it is zero. + 6 + 1 + read-only + + + THRE + Transmitter Holding Register empty +This bit is 1 when the THR (TXFIFO in the FIFO +mode) is empty. Otherwise, it is zero. +If the THRE interrupt is enabled, an interrupt is +triggered when THRE becomes 1. + 5 + 1 + read-only + + + LBREAK + Line break +This bit is set when the uart_sin input signal was held +LOWfor longer than the time for a full-word +transmission. A full-word transmission is the +transmission of the START, data, parity, and STOP +bits. It is cleared when this register is read. +In the FIFO mode, this bit indicates the line break for +the received data at the top of the RXFIFO. + 4 + 1 + read-only + + + FE + Framing error +This bit is set when the received STOP bit is not +HIGH. It is cleared when this register is read. +In the FIFO mode, this bit indicates the framing error +for the received data at the top of the RXFIFO. + 3 + 1 + read-only + + + PE + Parity error +This bit is set when the received parity does not match +with the parity selected in the LCR[5:4]. It is cleared +when this register is read. +In the FIFO mode, this bit indicates the parity error +for the received data at the top of the RXFIFO. + 2 + 1 + read-only + + + OE + Overrun error +This bit indicates that data in the Receiver Buffer +Register (RBR) is overrun. + 1 + 1 + read-only + + + DR + Data ready. +This bit is set when there are incoming received data +in the Receiver Buffer Register (RBR). It is cleared +when all of the received data are read. + 0 + 1 + read-only + + + + + MSR + Modem Status Register + 0x38 + 32 + 0x00000000 + 0x00000011 + + + CTS + Clear to send +0: The modem_ctsn input signal is HIGH. +1: The modem_ctsn input signal is LOW. + 4 + 1 + read-only + + + DCTS + Delta clear to send +This bit is set when the state of the modem_ctsn input +signal has been changed since the last time this +register is read. + 0 + 1 + read-only + + + + + GPR + GPR Register + 0x3c + 32 + 0x00000000 + 0x000000FF + + + DATA + A one-byte storage register + 0 + 8 + read-write + + + + + + + UART1 + UART1 + UART + 0xf0044000 + + + UART2 + UART2 + UART + 0xf0048000 + + + UART3 + UART3 + UART + 0xf004c000 + + + UART4 + UART4 + UART + 0xf0050000 + + + UART5 + UART5 + UART + 0xf0054000 + + + UART6 + UART6 + UART + 0xf0058000 + + + UART7 + UART7 + UART + 0xf005c000 + + + PUART + PUART + UART + 0xf4124000 + + + I2C0 + I2C0 + I2C + 0xf0060000 + + 0x4 + 0x30 + registers + + + + Cfg + Configuration Register + 0x10 + 32 + 0x00000001 + 0xFFFFFFFF + + + FIFOSIZE + FIFO Size: +0: 2 bytes +1: 4 bytes +2: 8 bytes +3: 16 bytes + 0 + 2 + read-only + + + + + IntEn + Interrupt Enable Register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMPL + Set to enable the Completion Interrupt. +Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. +Slave: interrupts when a transaction addressing the controller is completed. + 9 + 1 + read-write + + + BYTERECV + Set to enable the Byte Receive Interrupt. +Interrupts when a byte of data is received +Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually. + 8 + 1 + read-write + + + BYTETRANS + Set to enable the Byte Transmit Interrupt. +Interrupts when a byte of data is transmitted. + 7 + 1 + read-write + + + START + Set to enable the START Condition Interrupt. +Interrupts when a START condition/repeated START condition is detected. + 6 + 1 + read-write + + + STOP + Set to enable the STOP Condition Interrupt +Interrupts when a STOP condition is detected. + 5 + 1 + read-write + + + ARBLOSE + Set to enable the Arbitration Lose Interrupt. +Master: interrupts when the controller loses the bus arbitration +Slave: not available in this mode. + 4 + 1 + read-write + + + ADDRHIT + Set to enable the Address Hit Interrupt. +Master: interrupts when the addressed slave returned an ACK. +Slave: interrupts when the controller is addressed. + 3 + 1 + read-write + + + FIFOHALF + Set to enable the FIFO Half Interrupt. +Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. +Transmitter: Interrupts when the FIFO is half-empty, i.e. there is <= 1/2 entries in the FIFO. +This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered. + 2 + 1 + read-write + + + FIFOFULL + Set to enable the FIFO Full Interrupt. +Interrupts when the FIFO is full. + 1 + 1 + read-write + + + FIFOEMPTY + Set to enabled the FIFO Empty Interrupt +Interrupts when the FIFO is empty. + 0 + 1 + read-write + + + + + Status + Status Register + 0x18 + 32 + 0x00000001 + 0xFFFFFFFF + + + LINESDA + Indicates the current status of the SDA line on the bus +1: high +0: low + 14 + 1 + read-only + + + LINESCL + Indicates the current status of the SCL line on the bus +1: high +0: low + 13 + 1 + read-only + + + GENCALL + Indicates that the address of the current transaction is a general call address: +1: General call +0: Not general call + 12 + 1 + read-only + + + BUSBUSY + Indicates that the bus is busy +The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus +1: Busy +0: Not busy + 11 + 1 + read-only + + + ACK + Indicates the type of the last received/transmitted acknowledgement bit: +1: ACK +0: NACK + 10 + 1 + read-only + + + CMPL + Transaction Completion +Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration +Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked. + 9 + 1 + write-only + + + BYTERECV + Indicates that a byte of data has been received. + 8 + 1 + write-only + + + BYTETRANS + Indicates that a byte of data has been transmitted. + 7 + 1 + write-only + + + START + Indicates that a START Condition or a repeated START condition has been transmitted/received. + 6 + 1 + write-only + + + STOP + Indicates that a STOP Condition has been transmitted/received. + 5 + 1 + write-only + + + ARBLOSE + Indicates that the controller has lost the bus arbitration. + 4 + 1 + write-only + + + ADDRHIT + Master: indicates that a slave has responded to the transaction. +Slave: indicates that a transaction is targeting the controller (including the General Call). + 3 + 1 + write-only + + + FIFOHALF + Transmitter: Indicates that the FIFO is half-empty. + 2 + 1 + read-only + + + FIFOFULL + Indicates that the FIFO is full. + 1 + 1 + read-only + + + FIFOEMPTY + Indicates that the FIFO is empty. + 0 + 1 + read-only + + + + + Addr + Address Register + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + The slave address. +For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid + 0 + 10 + read-write + + + + + Data + Data Register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + Write this register to put one byte of data to the FIFO. +Read this register to get one byte of data from the FIFO. + 0 + 8 + read-write + + + + + Ctrl + Control Register + 0x24 + 32 + 0x00905E00 + 0xFFFFFFFF + + + DATACNT_HIGH + Data counts in bytes. +Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. +Slave: the meaning of DataCnt depends on the DMA mode: +If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. +If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. + 24 + 8 + read-write + + + RESET_LEN + reset clock cycles. the clock high/low time is defined by Setup.T_SCLHi, 50% duty cycle. + 20 + 4 + read-write + + + RESET_HOLD_SCKIN + set to hold input clock to high when reset is active + 14 + 1 + read-write + + + RESET_ON + set to send reset signals(just toggle clock bus defined by reset_len). +this register is clered when reset is end, can't be cleared by software + 13 + 1 + read-write + + + PHASE_START + Enable this bit to send a START condition at the beginning of transaction. +Master mode only. + 12 + 1 + read-write + + + PHASE_ADDR + Enable this bit to send the address after START condition. +Master mode only. + 11 + 1 + read-write + + + PHASE_DATA + Enable this bit to send the data after Address phase. +Master mode only. + 10 + 1 + read-write + + + PHASE_STOP + Enable this bit to send a STOP condition at the end of a transaction. +Master mode only. + 9 + 1 + read-write + + + DIR + Transaction direction +Master: Set this bit to determine the direction for the next transaction. +0: Transmitter +1: Receiver +Slave: The direction of the last received transaction. +0: Receiver +1: Transmitter + 8 + 1 + read-write + + + DATACNT + Data counts in bytes. +Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. +Slave: the meaning of DataCnt depends on the DMA mode: +If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. +If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. + 0 + 8 + read-write + + + + + Cmd + Command Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMD + Write this register with the following values to perform the corresponding actions: +0x0: no action +0x1: issue a data transaction (Master only) +0x2: respond with an ACK to the received byte +0x3: respond with a NACK to the received byte +0x4: clear the FIFO +0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) +When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. +Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled. + 0 + 3 + read-write + + + + + Setup + Setup Register + 0x2c + 32 + 0x05252100 + 0xFFFFFFFF + + + T_SUDAT + T_SUDAT defines the data setup time before releasing the SCL. +Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) +tpclk = PCLK period +TPM = The multiplier value in Timing Parameter Multiplier Register + 24 + 5 + read-write + + + T_SP + T_SP defines the pulse width of spikes that must be suppressed by the input filter. +Pulse width = T_SP * tpclk* (TPM+1) + 21 + 3 + read-write + + + T_HDDAT + T_HDDAT defines the data hold time after SCL goes LOW +Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) + 16 + 5 + read-write + + + T_SCLRADIO + The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. +SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) +1: ratio = 2 +0: ratio = 1 +This field is only valid when the controller is in the master mode. + 13 + 1 + read-write + + + T_SCLHI + The HIGH period of generated SCL clock is defined by T_SCLHi. +SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) +The T_SCLHi value must be greater than T_SP and T_HDDAT values. +This field is only valid when the controller is in the master mode. + 4 + 9 + read-write + + + DMAEN + Enable the direct memory access mode data transfer. +1: Enable +0: Disable + 3 + 1 + read-write + + + MASTER + Configure this device as a master or a slave. +1: Master mode +0: Slave mode + 2 + 1 + read-write + + + ADDRESSING + I2C addressing mode: +1: 10-bit addressing mode +0: 7-bit addressing mode + 1 + 1 + read-write + + + IICEN + Enable the I2C controller. +1: Enable +0: Disable + 0 + 1 + read-write + + + + + TPM + I2C Timing Paramater Multiplier + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + TPM + A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). + 0 + 5 + read-write + + + + + + + I2C1 + I2C1 + I2C + 0xf0064000 + + + I2C2 + I2C2 + I2C + 0xf0068000 + + + I2C3 + I2C3 + I2C + 0xf006c000 + + + SPI0 + SPI0 + SPI + 0xf0070000 + + 0x4 + 0x7c + registers + + + + wr_trans_cnt + Transfer count for write data + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + WRTRANCNT + Transfer count for write data +WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). +WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. +The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. +For TransMode 0, WrTranCnt must be equal to RdTranCnt. + 0 + 32 + read-write + + + + + rd_trans_cnt + Transfer count for read data + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RDTRANCNT + Transfer count for read data +RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). +RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. +The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. +For TransMode 0, WrTranCnt must equal RdTranCnt. + 0 + 32 + read-write + + + + + TransFmt + Transfer Format Register + 0x10 + 32 + 0x00020780 + 0xFFFF1F9F + + + ADDRLEN + Address length in bytes +0x0: 1 byte +0x1: 2 bytes +0x2: 3 bytes +0x3: 4 bytes + 16 + 2 + read-write + + + DATALEN + The length of each data unit in bits +The actual bit number of a data unit is (DataLen + 1) + 8 + 5 + read-write + + + DATAMERGE + Enable Data Merge mode, which does automatic data split on write and data coalescing on read. +This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. +When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed. + 7 + 1 + read-write + + + MOSIBIDIR + Bi-directional MOSI in regular (single) mode +0x0: MOSI is uni-directional signal in regular mode. +0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two + 4 + 1 + read-write + + + LSB + Transfer data with the least significant bit first +0x0: Most significant bit first +0x1: Least significant bit first + 3 + 1 + read-write + + + SLVMODE + SPI Master/Slave mode selection +0x0: Master mode +0x1: Slave mode + 2 + 1 + read-write + + + CPOL + SPI Clock Polarity +0x0: SCLK is LOW in the idle states +0x1: SCLK is HIGH in the idle states + 1 + 1 + read-write + + + CPHA + SPI Clock Phase +0x0: Sampling data at odd SCLK edges +0x1: Sampling data at even SCLK edges + 0 + 1 + read-write + + + + + DirectIO + Direct IO Control Register + 0x14 + 32 + 0x00003100 + 0x013F3F3F + + + DIRECTIOEN + Enable Direct IO +0x0: Disable +0x1: Enable + 24 + 1 + read-write + + + HOLD_OE + Output enable for the SPI Flash hold signal + 21 + 1 + read-write + + + WP_OE + Output enable for the SPI Flash write protect signal + 20 + 1 + read-write + + + MISO_OE + Output enable fo the SPI MISO signal + 19 + 1 + read-write + + + MOSI_OE + Output enable for the SPI MOSI signal + 18 + 1 + read-write + + + SCLK_OE + Output enable for the SPI SCLK signal + 17 + 1 + read-write + + + CS_OE + Output enable for SPI CS (chip select) signal + 16 + 1 + read-write + + + HOLD_O + Output value for the SPI Flash hold signal + 13 + 1 + read-write + + + WP_O + Output value for the SPI Flash write protect signal + 12 + 1 + read-write + + + MISO_O + Output value for the SPI MISO signal + 11 + 1 + read-write + + + MOSI_O + Output value for the SPI MOSI signal + 10 + 1 + read-write + + + SCLK_O + Output value for the SPI SCLK signal + 9 + 1 + read-write + + + CS_O + Output value for the SPI CS (chip select) signal + 8 + 1 + read-write + + + HOLD_I + Status of the SPI Flash hold signal + 5 + 1 + read-only + + + WP_I + Status of the SPI Flash write protect signal + 4 + 1 + read-only + + + MISO_I + Status of the SPI MISO signal + 3 + 1 + read-only + + + MOSI_I + Status of the SPI MOSI signal + 2 + 1 + read-only + + + SCLK_I + Status of the SPI SCLK signal + 1 + 1 + read-only + + + CS_I + Status of the SPI CS (chip select) signal + 0 + 1 + read-only + + + + + TransCtrl + Transfer Control Register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + SLVDATAONLY + Data-only mode (slave mode only) +0x0: Disable the data-only mode +0x1: Enable the data-only mode +Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0. + 31 + 1 + read-write + + + CMDEN + SPI command phase enable (Master mode only) +0x0: Disable the command phase +0x1: Enable the command phase + 30 + 1 + read-write + + + ADDREN + SPI address phase enable (Master mode only) +0x0: Disable the address phase +0x1: Enable the address phase + 29 + 1 + read-write + + + ADDRFMT + SPI address phase format (Master mode only) +0x0: Address phase is the regular (single) mode +0x1: The format of the address phase is the same as the data phase (DualQuad). + 28 + 1 + read-write + + + TRANSMODE + Transfer mode +The transfer sequence could be +0x0: Write and read at the same time +0x1: Write only +0x2: Read only +0x3: Write, Read +0x4: Read, Write +0x5: Write, Dummy, Read +0x6: Read, Dummy, Write +0x7: None Data (must enable CmdEn or AddrEn in master mode) +0x8: Dummy, Write +0x9: Dummy, Read +0xa~0xf: Reserved + 24 + 4 + read-write + + + DUALQUAD + SPI data phase format +0x0: Regular (Single) mode +0x1: Dual I/O mode +0x2: Quad I/O mode +0x3: Reserved + 22 + 2 + read-write + + + TOKENEN + Token transfer enable (Master mode only) +Append a one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. +0x0: Disable the one-byte special token +0x1: Enable the one-byte special token + 21 + 1 + read-write + + + WRTRANCNT + Transfer count for write data +WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). +WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. +The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. +For TransMode 0, WrTranCnt must be equal to RdTranCnt. + 12 + 9 + read-write + + + TOKENVALUE + Token value (Master mode only) +The value of the one-byte special token following the address phase for SPI read transfers. +0x0: token value = 0x00 +0x1: token value = 0x69 + 11 + 1 + read-write + + + DUMMYCNT + Dummy data count. The actual dummy count is (DummyCnt +1). +The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) +The Data pins are put into the high impedance during the dummy data phase. +DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases. + 9 + 2 + read-write + + + RDTRANCNT + Transfer count for read data +RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). +RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. +The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. +For TransMode 0, WrTranCnt must equal RdTranCnt. + 0 + 9 + read-write + + + + + Cmd + Command Register + 0x24 + 32 + 0x00000000 + 0x000000FF + + + CMD + SPI Command + 0 + 8 + read-write + + + + + Addr + Address Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + SPI Address +(Master mode only) + 0 + 32 + read-write + + + + + Data + Data Register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + Data to transmit or the received data +For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. +For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. +The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. +If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset. + 0 + 32 + read-write + + + + + Ctrl + Control Register + 0x30 + 32 + 0x00000000 + 0x0FFFFF1F + + + CS_EN + No description available + 24 + 4 + read-write + + + TXTHRES + Transmit (TX) FIFO Threshold +The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold. + 16 + 8 + read-write + + + RXTHRES + Receive (RX) FIFO Threshold +The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold. + 8 + 8 + read-write + + + TXDMAEN + TX DMA enable + 4 + 1 + read-write + + + RXDMAEN + RX DMA enable + 3 + 1 + read-write + + + TXFIFORST + Transmit FIFO reset +Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. + 2 + 1 + read-write + + + RXFIFORST + Receive FIFO reset +Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. + 1 + 1 + read-write + + + SPIRST + SPI reset +Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. + 0 + 1 + read-write + + + + + Status + Status Register + 0x34 + 32 + 0x00000000 + 0x33FFFF01 + + + TXNUM_7_6 + Number of valid entries in the Transmit FIFO + 28 + 2 + read-only + + + RXNUM_7_6 + Number of valid entries in the Receive FIFO + 24 + 2 + read-only + + + TXFULL + Transmit FIFO Full flag + 23 + 1 + read-only + + + TXEMPTY + Transmit FIFO Empty flag + 22 + 1 + read-only + + + TXNUM_5_0 + Number of valid entries in the Transmit FIFO + 16 + 6 + read-only + + + RXFULL + Receive FIFO Full flag + 15 + 1 + read-only + + + RXEMPTY + Receive FIFO Empty flag + 14 + 1 + read-only + + + RXNUM_5_0 + Number of valid entries in the Receive FIFO + 8 + 6 + read-only + + + SPIACTIVE + SPI register programming is in progress. +In master mode, SPIActive becomes 1 after the SPI command register is written and becomes 0 after the transfer is finished. +In slave mode, SPIActive becomes 1 after the SPI CS signal is asserted and becomes 0 after the SPI CS signal is deasserted. +Note that due to clock synchronization, it may take at most two spi_clock cycles for SPIActive to change when the corresponding condition happens. +Note this bit stays 0 when Direct IO Control or the memory-mapped interface is used. + 0 + 1 + read-only + + + + + IntrEn + Interrupt Enable Register + 0x38 + 32 + 0x00000000 + 0x0000003F + + + SLVCMDEN + Enable the Slave Command Interrupt. +Control whether interrupts are triggered whenever slave commands are received. +(Slave mode only) + 5 + 1 + read-write + + + ENDINTEN + Enable the End of SPI Transfer interrupt. +Control whether interrupts are triggered when SPI transfers end. +(In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.) + 4 + 1 + read-write + + + TXFIFOINTEN + Enable the SPI Transmit FIFO Threshold interrupt. +Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold. + 3 + 1 + read-write + + + RXFIFOINTEN + Enable the SPI Receive FIFO Threshold interrupt. +Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold. + 2 + 1 + read-write + + + TXFIFOURINTEN + Enable the SPI Transmit FIFO Underrun interrupt. +Control whether interrupts are triggered when the Transmit FIFO run out of data. +(Slave mode only) + 1 + 1 + read-write + + + RXFIFOORINTEN + Enable the SPI Receive FIFO Overrun interrupt. +Control whether interrupts are triggered when the Receive FIFO overflows. +(Slave mode only) + 0 + 1 + read-write + + + + + IntrSt + Interrupt Status Register + 0x3c + 32 + 0x00000000 + 0x0000003F + + + SLVCMDINT + Slave Command Interrupt. +This bit is set when Slave Command interrupts occur. +(Slave mode only) + 5 + 1 + write-only + + + ENDINT + End of SPI Transfer interrupt. +This bit is set when End of SPI Transfer interrupts occur. + 4 + 1 + write-only + + + TXFIFOINT + TX FIFO Threshold interrupt. +This bit is set when TX FIFO Threshold interrupts occur. + 3 + 1 + write-only + + + RXFIFOINT + RX FIFO Threshold interrupt. +This bit is set when RX FIFO Threshold interrupts occur. + 2 + 1 + write-only + + + TXFIFOURINT + TX FIFO Underrun interrupt. +This bit is set when TX FIFO Underrun interrupts occur. +(Slave mode only) + 1 + 1 + write-only + + + RXFIFOORINT + RX FIFO Overrun interrupt. +This bit is set when RX FIFO Overrun interrupts occur. +(Slave mode only) + 0 + 1 + write-only + + + + + Timing + Interface Timing Register + 0x40 + 32 + 0x00000000 + 0x00003FFF + + + CS2SCLK + The minimum time between the edges of SPI CS and the edges of SCLK. +SCLK_period * (CS2SCLK + 1) / 2 + 12 + 2 + read-write + + + CSHT + The minimum time that SPI CS should stay HIGH. +SCLK_period * (CSHT + 1) / 2 + 8 + 4 + read-write + + + SCLK_DIV + The clock frequency ratio between the clock source and SPI interface SCLK. +SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) +The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency. + 0 + 8 + read-write + + + + + SlvSt + Slave Status Register + 0x60 + 32 + 0x00000000 + 0x0007FFFF + + + UNDERRUN + Data underrun occurs in the last transaction + 18 + 1 + write-only + + + OVERRUN + Data overrun occurs in the last transaction + 17 + 1 + read-write + + + READY + Set this bit to indicate that the ATCSPI200 is ready for data transaction. +When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0. + 16 + 1 + read-write + + + USR_STATUS + User defined status flags + 0 + 16 + read-write + + + + + SlvDataCnt + Slave Data Count Register + 0x64 + 32 + 0x00000000 + 0x03FF03FF + + + WCNT + Slave transmitted data count + 16 + 10 + read-only + + + RCNT + Slave received data count + 0 + 10 + read-only + + + + + SlvDataWCnt + WCnt + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + No description available + 0 + 32 + read-only + + + + + SlvDataRCnt + RCnt + 0x6c + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + No description available + 0 + 32 + read-only + + + + + Config + Configuration Register + 0x7c + 32 + 0x00004311 + 0x000043FF + + + SLAVE + Support for SPI Slave mode + 14 + 1 + read-only + + + QUADSPI + Support for Quad I/O SPI + 9 + 1 + read-only + + + DUALSPI + Support for Dual I/O SPI + 8 + 1 + read-only + + + TXFIFOSIZE + Depth of TX FIFO +0x0: 2 words +0x1: 4 words +0x2: 8 words +0x3: 16 words +0x4: 32 words +0x5: 64 words +0x6: 128 words + 4 + 4 + read-only + + + RXFIFOSIZE + Depth of RX FIFO +0x0: 2 words +0x1: 4 words +0x2: 8 words +0x3: 16 words +0x4: 32 words +0x5: 64 words +0x6: 128 words + 0 + 4 + read-only + + + + + + + SPI1 + SPI1 + SPI + 0xf0074000 + + + SPI2 + SPI2 + SPI + 0xf0078000 + + + SPI3 + SPI3 + SPI + 0xf007c000 + + + CRC + CRC + CRC + 0xf0080000 + + 0x0 + 0x200 + registers + + + + 8 + 0x40 + 0,1,2,3,4,5,6,7 + CHN[%s] + no description available + 0x0 + + pre_set + &index0 pre set for crc setting + 0x0 + 32 + 0x00000000 + 0x000000FF + + + PRE_SET + 0: no pre set +1: CRC32 +2: CRC32-AUTOSAR +3: CRC16-CCITT +4: CRC16-XMODEM +5: CRC16-MODBUS +1: CRC32 +2: CRC32-autosar +3: CRC16-ccitt +4: CRC16-xmodem +5: CRC16-modbus +6: crc16_dnp +7: crc16_x25 +8: crc16_usb +9: crc16_maxim +10: crc16_ibm +11: crc8_maxim +12: crc8_rohc +13: crc8_itu +14: crc8 +15: crc5_usb + 0 + 8 + read-write + + + + + clr + chn&index0 clear crc result and setting + 0x4 + 32 + 0x00000000 + 0x00000001 + + + CLR + write 1 to clr crc setting and result for its channel. +always read 0. + 0 + 1 + read-write + + + + + poly + chn&index0 poly + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + POLY + poly setting + 0 + 32 + read-write + + + + + init_data + chn&index0 init_data + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + INIT_DATA + initial data of CRC + 0 + 32 + read-write + + + + + xorout + chn&index0 xorout + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + XOROUT + XOR for CRC result + 0 + 32 + read-write + + + + + misc_setting + chn&index0 misc_setting + 0x14 + 32 + 0x00000000 + 0x0101013F + + + BYTE_REV + 0: no wrap input byte order +1: wrap input byte order + 24 + 1 + read-write + + + REV_OUT + 0: no wrap output bit order +1: wrap output bit order + 16 + 1 + read-write + + + REV_IN + 0: no wrap input bit order +1: wrap input bit order + 8 + 1 + read-write + + + POLY_WIDTH + crc data length + 0 + 6 + read-write + + + + + data + chn&index0 data + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + data for crc + 0 + 32 + read-write + + + + + result + chn&index0 result + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + RESULT + crc result + 0 + 32 + read-write + + + + + + + + TSNS + TSNS + TSNS + 0xf0090000 + + 0x0 + 0x3c + registers + + + + T + Temperature + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Signed number of temperature in 256 x celsius degree + 0 + 32 + read-only + + + + + TMAX + Maximum Temperature + 0x4 + 32 + 0xFF800000 + 0xFFFFFFFF + + + T + maximum temperature ever found + 0 + 32 + read-only + + + + + TMIN + Minimum Temperature + 0x8 + 32 + 0x007FFFFF + 0xFFFFFFFF + + + T + minimum temperature ever found + 0 + 32 + read-only + + + + + AGE + Sample age + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + AGE + age of T register in 24MHz clock cycles + 0 + 32 + read-only + + + + + STATUS + Status + 0x10 + 32 + 0x00000000 + 0x80000001 + + + VALID + indicate value in T is valid or not +0: not valid +1:valid + 31 + 1 + read-only + + + TRIGGER + Software trigger for sensing in trigger mode, trigger will be ignored if in sensing or other mode + 0 + 1 + write-only + + + + + CONFIG + Configuration + 0x14 + 32 + 0x00600300 + 0xC3FF0713 + + + IRQ_EN + Enable interrupt + 31 + 1 + read-write + + + RST_EN + Enable reset + 30 + 1 + read-write + + + COMPARE_MIN_EN + Enable compare for minimum temperature + 25 + 1 + read-write + + + COMPARE_MAX_EN + Enable compare for maximum temperature + 24 + 1 + read-write + + + SPEED + cycles of a progressive step in 24M clock, valid from 24-255, default 96 +24: 24 cycle for a step +25: 25 cycle for a step +26: 26 cycle for a step +... +255: 255 cycle for a step + 16 + 8 + read-write + + + AVERAGE + Average time, default in 3 +0: measure and return +1: twice and average +2: 4 times and average +. . . +7: 128 times and average + 8 + 3 + read-write + + + CONTINUOUS + continuous mode that keep sampling temperature peridically +0: trigger mode +1: continuous mode + 4 + 1 + read-write + + + ASYNC + Acynchronous mode, this mode can work without clock, only available function ios compare to certain ADC value +0: active mode +1: Async mode + 1 + 1 + read-write + + + ENABLE + Enable temperature +0: disable, temperature sensor is shut down +1: enable. Temperature sensor enabled + 0 + 1 + read-write + + + + + VALIDITY + Sample validity + 0x18 + 32 + 0x016E3600 + 0xFFFFFFFF + + + VALIDITY + time for temperature values to expire in 24M clock cycles + 0 + 32 + read-write + + + + + FLAG + Temperature flag + 0x1c + 32 + 0x00000000 + 0x00330001 + + + RECORD_MIN_CLR + Clear minimum recorder of temerature, write 1 to clear + 21 + 1 + read-write + + + RECORD_MAX_CLR + Clear maximum recorder of temerature, write 1 to clear + 20 + 1 + read-write + + + UNDER_TEMP + Clear under temperature status, write 1 to clear + 17 + 1 + read-write + + + OVER_TEMP + Clear over temperature status, write 1 to clear + 16 + 1 + read-write + + + IRQ + IRQ flag, write 1 to clear + 0 + 1 + read-write + + + + + UPPER_LIM_IRQ + Maximum temperature to interrupt + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Maximum temperature for compare + 0 + 32 + read-write + + + + + LOWER_LIM_IRQ + Minimum temperature to interrupt + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Minimum temperature for compare + 0 + 32 + read-write + + + + + UPPER_LIM_RST + Maximum temperature to reset + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Maximum temperature for compare + 0 + 32 + read-write + + + + + LOWER_LIM_RST + Minimum temperature to reset + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Minimum temperature for compare + 0 + 32 + read-write + + + + + ASYNC + Configuration in asynchronous mode + 0x30 + 32 + 0x00000000 + 0x010107FF + + + ASYNC_TYPE + Compare hotter than or colder than in asynchoronous mode +0: hotter than +1: colder than + 24 + 1 + read-write + + + POLARITY + Polarity of internal comparator + 16 + 1 + read-write + + + VALUE + Value of async mode to compare + 0 + 11 + read-write + + + + + ADVAN + Advance configuration + 0x38 + 32 + 0x00000000 + 0x03010003 + + + ASYNC_IRQ + interrupt status of asynchronous mode + 25 + 1 + read-only + + + ACTIVE_IRQ + interrupt status of active mode + 24 + 1 + read-only + + + SAMPLING + temperature sampling is working + 16 + 1 + read-only + + + NEG_ONLY + use negative compare polarity only + 1 + 1 + read-write + + + POS_ONLY + use positive compare polarity only + 0 + 1 + read-write + + + + + + + MBX0A + MBX0A + MBX + 0xf00a0000 + + 0x0 + 0x24 + registers + + + + CR + Command Registers + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXRESET + Reset TX Fifo and word. + 31 + 1 + read-write + + + BARCTL + Bus Access Response Control, when bit 15:14= +00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. + 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. +10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. +11: reserved. + 14 + 2 + read-write + + + BEIE + Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. +1, enable the bus access error interrupt. +0, disable the bus access error interrupt. + 8 + 1 + read-write + + + TFMAIE + TX FIFO message available interrupt enable. +1, enable the TX FIFO massage available interrupt. +0, disable the TX FIFO message available interrupt. + 7 + 1 + read-write + + + TFMEIE + TX FIFO message empty interrupt enable. +1, enable the TX FIFO massage empty interrupt. +0, disable the TX FIFO message empty interrupt. + 6 + 1 + read-write + + + RFMAIE + RX FIFO message available interrupt enable. +1, enable the RX FIFO massage available interrupt. +0, disable the RX FIFO message available interrupt. + 5 + 1 + read-write + + + RFMFIE + RX fifo message full interrupt enable. +1, enable the RX fifo message full interrupt. +0, disable the RX fifo message full interrupt. + 4 + 1 + read-write + + + TWMEIE + TX word message empty interrupt enable. +1, enable the TX word massage empty interrupt. +0, disable the TX word message empty interrupt. + 1 + 1 + read-write + + + RWMVIE + RX word message valid interrupt enable. +1, enable the RX word massage valid interrupt. +0, disable the RX word message valid interrupt. + 0 + 1 + read-write + + + + + SR + Status Registers + 0x4 + 32 + 0x000000E2 + 0xFFFF3FFF + + + RFVC + RX FIFO valid message count + 20 + 4 + read-only + + + TFEC + TX FIFO empty message word count + 16 + 4 + read-only + + + ERRRE + bus Error for read when rx word message are still invalid, this bit is W1C bit. +1, read from word message when the word message are still invalid will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 13 + 1 + write-only + + + EWTRF + bus Error for write when tx word message are still valid, this bit is W1C bit. +1, write to word message when the word message are still valid will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 12 + 1 + write-only + + + ERRFE + bus Error for read when rx fifo empty, this bit is W1C bit. +1, read from a empty rx fifo will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 11 + 1 + write-only + + + EWTFF + bus Error for write when tx fifo full, this bit is W1C bit. +1, write to a fulled tx fifo will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 10 + 1 + write-only + + + EAIVA + bus Error for Accessing Invalid Address; this bit is W1C bit. +1, read and write to invalid address in the bus of this block, will set this bit. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 9 + 1 + write-only + + + EW2RO + bus Error for Write to Read Only address; this bit is W1C bit. +1, write to read only address happened in the bus of this block. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 8 + 1 + write-only + + + TFMA + TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. +1, TXFIFO message buffer has slot available +0, no slot available (fifo full) + 7 + 1 + read-write + + + TFME + TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. +1, no any message data in TXFIFO from other core. +0, there are some data in the 4x32 TX FIFO from other core yet. + 6 + 1 + read-write + + + RFMA + RX FIFO Message Available, available data in the 4x32 TX FIFO message buffer to the other core, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, no any data in the 4x32 TXFIFO message buffer. +0, there are some data in the the 4x32 TXFIFO message buffer already. + 5 + 1 + read-only + + + RFMF + RX FIFO Message Full, message from other core; will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, the other core had written 4x32 message in the RXFIFO. +0, no 4x32 RX FIFO message from other core yet. + 4 + 1 + read-only + + + TWME + TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, means this core had write word message to TXREG. +0, means no valid word message in the TXREG yet. + 1 + 1 + read-only + + + RWMV + RX word message valid, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, the other core had written word message in the RXREG. +0, no valid word message yet in the RXREG. + 0 + 1 + read-only + + + + + TXREG + Transmit word message to other core. + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXREG + Transmit word message to other core. + 0 + 32 + write-only + + + + + RXREG + Receive word message from other core. + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + RXREG + Receive word message from other core. + 0 + 32 + read-only + + + + + 1 + 0x4 + TXFIFO0 + TXWRD[%s] + no description available + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXFIFO + TXFIFO for sending message to other core, FIFO size, 4x32 +can write one of the word address to push data to the FIFO; +can also use 4x32 burst write from 0x010 to push 4 words to the FIFO. + 0 + 32 + write-only + + + + + 1 + 0x4 + RXFIFO0 + RXWRD[%s] + no description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXFIFO + RXFIFO for receiving message from other core, FIFO size, 4x32 +can read one of the word address to pop data to the FIFO; +can also use 4x32 burst read from 0x020 to read 4 words from the FIFO. + 0 + 32 + read-only + + + + + + + MBX0B + MBX0B + MBX + 0xf00a4000 + + + EWDG0 + EWDG0 + EWDG + 0xf00b0000 + + 0x0 + 0x28 + registers + + + + CTRL0 + wdog ctrl register 0 +Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits + 0x0 + 32 + 0x00000000 + 0x2FE2F03F + + + CLK_SEL + clock select +0：bus clock +1：ext clock + 29 + 1 + read-write + + + DIV_VALUE + clock divider, the clock divider works as 2 ^ div_value for wdt counter + 25 + 3 + read-write + + + WIN_EN + window mode enable + 24 + 1 + read-write + + + WIN_LOWER + Once window mode is opened, the lower counter value to refresh wdt +00: 4/8 overtime value +01: 5/8 of overtime value +10: 6/8 of overtime value +11: 7/8 of overtime value + 22 + 2 + read-write + + + CFG_LOCK + The register is locked and unlock is needed before re-config registers +Once the lock mechanism takes effect, the CTRL0, CTRL1, timeout int register, timeout rst register, needs unlock before re-config them. +The register update needs to be finished in the required period defined by UPD_OT_TIME register + 21 + 1 + read-write + + + OT_SELF_CLEAR + overtime reset can be self released after 32 function cycles + 17 + 1 + read-write + + + REF_OT_REQ + If refresh event has to be limited into a period after refresh unlocked. +Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter + 15 + 1 + read-write + + + WIN_UPPER + The upper threshold of window value +The window period upper limit is: lower_limit + (overtime_rst_value / 16) * upper_reg_value +If this register value is zero, then no upper level limitation + 12 + 3 + read-write + + + REF_LOCK + WDT refresh has to be unlocked firstly once refresh lock is enable. + 5 + 1 + read-write + + + REF_UNLOCK_MEC + Unlock refresh mechanism +00: the required unlock password is the same with refresh_psd_register +01: the required unlock password is a ring shift left value of refresh_psd_register +10: the required unlock password is always 16'h55AA, no matter what refresh_psd_register is +11: the required unlock password is a LSFR result of refresh_psd_register, the characteristic polynomial is X^15 + 1 + 3 + 2 + read-write + + + EN_DBG + WTD enable or not in debug mode + 2 + 1 + read-write + + + EN_LP + WDT enable or not in low power mode +2'b00: wdt is halted once in low power mode +2'b01: wdt will work with 1/4 normal clock freq in low power mode +2'b10: wdt will work with 1/2 normal clock freq in low power mode +2'b11: wdt will work with normal clock freq in low power mode + 0 + 2 + read-write + + + + + CTRL1 + wdog ctrl register 1 +Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits + 0x4 + 32 + 0x00000000 + 0x00F300FC + + + REF_FAIL_RST_EN + Refresh violation will trigger an reset. +These event will be taken as a refresh violation: +1) Not refresh in the window once window mode is enabled +2) Not unlock refresh firstly if unlock is required +3) Not refresh in the required time after unlock, once refresh unlock overtime is enabled. +4) Not write the required word to refresh wdt. + 23 + 1 + read-write + + + REF_FAIL_INT_EN + Refresh violation will trigger an interrupt + 22 + 1 + read-write + + + UNL_REF_FAIL_RST_EN + Refresh unlock fail will trigger a reset + 21 + 1 + read-write + + + UNL_REF_FAIL_INT_EN + Refresh unlock fail will trigger a interrupt + 20 + 1 + read-write + + + OT_RST_EN + WDT overtime will generate a reset + 17 + 1 + read-write + + + OT_INT_EN + WDT can generate an interrupt warning before timeout + 16 + 1 + read-write + + + CTL_VIO_RST_EN + Ctrl update violation will trigger a reset +The violation event is to try updating the locked register before unlock them + 7 + 1 + read-write + + + CTL_VIO_INT_EN + Ctrl update violation will trigger a interrupt + 6 + 1 + read-write + + + UNL_CTL_FAIL_RST_EN + Unlock register update failure will trigger a reset + 5 + 1 + read-write + + + UNL_CTL_FAIL_INT_EN + Unlock register update failure will trigger a interrupt + 4 + 1 + read-write + + + PARITY_FAIL_RST_EN + Parity error will trigger a reset +A parity check is required once writing to ctrl0 and ctrl1 register. The result should be zero by modular two addition of all bits + 3 + 1 + read-write + + + PARITY_FAIL_INT_EN + Parity error will trigger a interrupt + 2 + 1 + read-write + + + + + OT_INT_VAL + wdog timeout interrupt counter value + 0x8 + 32 + 0x00000000 + 0x0000FFFF + + + OT_INT_VAL + WDT timeout interrupt value + 0 + 16 + read-write + + + + + OT_RST_VAL + wdog timeout reset counter value + 0xc + 32 + 0x00000000 + 0x0000FFFF + + + OT_RST_VAL + WDT timeout reset value + 0 + 16 + read-write + + + + + WDT_REFRESH_REG + wdog refresh register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + WDT_REFRESH_REG + Write this register by 32'h5A45_524F to refresh wdog +Note: Reading this register can read back wdt real time counter value, while it is only used by debug purpose + 0 + 32 + write-only + + + + + WDT_STATUS + wdog status register + 0x14 + 32 + 0x00000000 + 0x0000007F + + + PARITY_ERROR + parity error +Write one to clear the bit + 6 + 1 + read-write + + + OT_RST + Timeout happens, a reset will happen once enable bit set +This bit can be cleared only by refreshing wdt or reset + 5 + 1 + read-only + + + OT_INT + Timeout happens, a interrupt will happen once enable bit set +This bit can be cleared only by refreshing wdt or reset + 4 + 1 + read-only + + + CTL_UNL_FAIL + Unlock ctrl reg update protection fail +Write one to clear the bit + 3 + 1 + read-write + + + CTL_VIO + Violate register update protection mechanism +Write one to clear the bit + 2 + 1 + read-write + + + REF_UNL_FAIL + Refresh unlock fail +Write one to clear the bit + 1 + 1 + read-write + + + REF_VIO + Refresh fail +Write one to clear the bit + 0 + 1 + read-write + + + + + CFG_PROT + ctrl register protection register + 0x18 + 32 + 0x00000000 + 0x000FFFFF + + + UPD_OT_TIME + The period in which register update has to be in after unlock +The required period is less than： 128 * 2 ^ UPD_OT_TIME * bus_clock_cycle + 16 + 4 + read-write + + + UPD_PSD + The password of unlocking register update + 0 + 16 + read-write + + + + + REF_PROT + refresh protection register + 0x1c + 32 + 0x00000000 + 0x0000FFFF + + + REF_UNL_PSD + The password to unlock refreshing + 0 + 16 + read-write + + + + + WDT_EN + Wdog enable + 0x20 + 32 + 0x00000000 + 0x00000001 + + + WDOG_EN + Wdog is enabled, the re-written of this register is impacted by enable lock function + 0 + 1 + read-write + + + + + REF_TIME + Refresh period value + 0x24 + 32 + 0x00000000 + 0x0000FFFF + + + REFRESH_PERIOD + The refresh period after refresh unlocked +Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter + 0 + 16 + read-write + + + + + + + EWDG1 + EWDG1 + EWDG + 0xf00b4000 + + + PEWDG + PEWDG + EWDG + 0xf4128000 + + + DMAMUX + DMAMUX + DMAMUX + 0xf00c4000 + + 0x0 + 0x80 + registers + + + + 32 + 0x4 + HDMA_MUX0,HDMA_MUX1,HDMA_MUX2,HDMA_MUX3,HDMA_MUX4,HDMA_MUX5,HDMA_MUX6,HDMA_MUX7,HDMA_MUX8,HDMA_MUX9,HDMA_MUX10,HDMA_MUX11,HDMA_MUX12,HDMA_MUX13,HDMA_MUX14,HDMA_MUX15,HDMA_MUX16,HDMA_MUX17,HDMA_MUX18,HDMA_MUX19,HDMA_MUX20,HDMA_MUX21,HDMA_MUX22,HDMA_MUX23,HDMA_MUX24,HDMA_MUX25,HDMA_MUX26,HDMA_MUX27,HDMA_MUX28,HDMA_MUX29,HDMA_MUX30,HDMA_MUX31 + MUXCFG[%s] + no description available + 0x0 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + write-only + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + write-only + + + + + + + HDMA + HDMA + DMAV2 + 0xf00c8000 + + 0x4 + 0x43c + registers + + + + IDMisc + ID Misc + 0x4 + 32 + 0x00000000 + 0x0000FF00 + + + DMASTATE + DMA state machine +localparam ST_IDLE = 3'b000; +localparam ST_READ = 3'b001; +localparam ST_READ_ACK = 3'b010; +localparam ST_WRITE = 3'b011; +localparam ST_WRITE_ACK = 3'b100; +localparam ST_LL = 3'b101; +localparam ST_END = 3'b110; +localparam ST_END_WAIT = 3'b111; + 13 + 3 + read-only + + + CURCHAN + current channel in used + 8 + 5 + read-only + + + + + DMACfg + DMAC Configuration Register + 0x10 + 32 + 0x00000000 + 0xC3FFFFFF + + + CHAINXFR + Chain transfer +0x0: Chain transfer is not configured +0x1: Chain transfer is configured + 31 + 1 + read-only + + + REQSYNC + DMA request synchronization. +The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, +which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. +0x0: Request synchronization is not configured +0x1: Request synchronization is configured + 30 + 1 + read-only + + + DATAWIDTH + AXI bus data width +0x0: 32 bits +0x1: 64 bits +0x2: 128 bits +0x3: 256 bits + 24 + 2 + read-only + + + ADDRWIDTH + AXI bus address width +0x18: 24 bits +0x19: 25 bits +... +0x40: 64 bits +Others: Invalid + 17 + 7 + read-only + + + CORENUM + DMA core number +0x0: 1 core +0x1: 2 cores + 16 + 1 + read-only + + + BUSNUM + AXI bus interface number +0x0: 1 AXI bus +0x1: 2 AXI busses + 15 + 1 + read-only + + + REQNUM + Request/acknowledge pair number +0x0: 0 pair +0x1: 1 pair +0x2: 2 pairs +... +0x10: 16 pairs + 10 + 5 + read-only + + + FIFODEPTH + FIFO depth +0x4: 4 entries +0x8: 8 entries +0x10: 16 entries +0x20: 32 entries +Others: Invalid + 4 + 6 + read-only + + + CHANNELNUM + Channel number +0x1: 1 channel +0x2: 2 channels +... +0x8: 8 channels +Others: Invalid + 0 + 4 + read-only + + + + + DMACtrl + DMAC Control Register + 0x14 + 32 + 0x00000000 + 0x00000001 + + + RESET + Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. +Note: The software reset may cause the in-completion of AXI transaction. + 0 + 1 + write-only + + + + + ChAbort + Channel Abort Register + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + CHABORT + Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. +Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) + 0 + 32 + write-only + + + + + INTHALFSTS + Harlf Complete Interrupt Status + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + STS + half transfer done irq status + 0 + 32 + read-write + + + + + INTTCSTS + Trans Complete Interrupt Status Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + STS + The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. +0x0: Channel n has no terminal count status +0x1: Channel n has terminal count status + 0 + 32 + write-only + + + + + INTABORTSTS + Abort Interrupt Status Register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + STS + The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. +0x0: Channel n has no abort status +0x1: Channel n has abort status + 0 + 32 + write-only + + + + + INTERRSTS + Error Interrupt Status Register + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + STS + The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: +- Bus error +- Unaligned address +- Unaligned transfer width +- Reserved configuration +0x0: Channel n has no error status +0x1: Channel n has error status + 0 + 32 + write-only + + + + + ChEN + Channel Enable Register + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + CHEN + Alias of the Enable field of all ChnCtrl registers + 0 + 32 + read-only + + + + + 32 + 0x20 + ch0,ch1,ch2,ch3,ch4,ch5,ch6,ch7,ch8,ch9,ch10,ch11,ch12,ch13,ch14,ch15,ch16,ch17,ch18,ch19,ch20,ch21,ch22,ch23,ch24,ch25,ch26,ch27,ch28,ch29,ch30,ch31 + CHCTRL[%s] + no description available + 0x40 + + Ctrl + Channel &index0 Control Register + 0x0 + 32 + 0x00000000 + 0xFFFFF01F + + + INFINITELOOP + set to loop current config infinitely + 31 + 1 + read-write + + + HANDSHAKEOPT + 0: one request to transfer one burst +1: one request to transfer all the data defined in ch_tts + 30 + 1 + read-write + + + PRIORITY + Channel priority level +0x0: Lower priority +0x1: Higher priority + 29 + 1 + read-write + + + BURSTOPT + set to change burst_size definition + 28 + 1 + read-write + + + SRCBURSTSIZE + Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. +The burst transfer byte number is (SrcBurstSize * SrcWidth). +0x0: 1 transfer +0x1: 2 transfers +0x2: 4 transfers +0x3: 8 transfers +0x4: 16 transfers +0x5: 32 transfers +0x6: 64 transfers +0x7: 128 transfers +0x8: 256 transfers +0x9:512 transfers +0xa: 1024 transfers +0xb - 0xf: Reserved, setting this field with a reserved value triggers the error exception + 24 + 4 + read-write + + + SRCWIDTH + Source transfer width +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception + 21 + 3 + read-write + + + DSTWIDTH + Destination transfer width. +Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; +otherwise the error event will be triggered. +For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. +See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception + 18 + 3 + read-write + + + SRCMODE + Source DMA handshake mode +0x0: Normal mode +0x1: Handshake mode +Normal mode is enabled and started by software set Enable bit; +Handshake mode is enabled by software set Enable bit, started by hardware dma request from DMAMUX block + 17 + 1 + read-write + + + DSTMODE + Destination DMA handshake mode +0x0: Normal mode +0x1: Handshake mode +the difference bewteen Source/Destination handshake mode is: +the dma block will response hardware request after read in Source handshake mode; +the dma block will response hardware request after write in Destination handshake mode; +NOTE: can't set SrcMode and DstMode at same time, otherwise result unknown. + 16 + 1 + read-write + + + SRCADDRCTRL + Source address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 14 + 2 + read-write + + + DSTADDRCTRL + Destination address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 12 + 2 + read-write + + + INTHALFCNTMASK + Channel half interrupt mask +0x0: Allow the half interrupt to be triggered +0x1: Disable the half interrupt + 4 + 1 + read-write + + + INTABTMASK + Channel abort interrupt mask +0x0: Allow the abort interrupt to be triggered +0x1: Disable the abort interrupt + 3 + 1 + read-write + + + INTERRMASK + Channel error interrupt mask +0x0: Allow the error interrupt to be triggered +0x1: Disable the error interrupt + 2 + 1 + read-write + + + INTTCMASK + Channel terminal count interrupt mask +0x0: Allow the terminal count interrupt to be triggered +0x1: Disable the terminal count interrupt + 1 + 1 + read-write + + + ENABLE + Channel enable bit +0x0: Disable +0x1: Enable + 0 + 1 + read-write + + + + + TranSize + Channel &index0Transfer Size Register + 0x4 + 32 + 0x00000000 + 0x0FFFFFFF + + + TRANSIZE + Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. +If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + 0 + 28 + read-write + + + + + SrcAddr + Channel &index0 Source Address Low Part Register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SRCADDRL + Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + 0 + 32 + read-write + + + + + ChanReqCtrl + Channel &index0 DMA Request Control Register + 0xc + 32 + 0x00000000 + 0x1F1F0000 + + + SRCREQSEL + Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + 24 + 5 + read-write + + + DSTREQSEL + Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + 16 + 5 + read-write + + + + + DstAddr + Channel &index0 Destination Address Low Part Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + DSTADDRL + Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + 0 + 32 + read-write + + + + + LLPointer + Channel &index0 Linked List Pointer Low Part Register + 0x18 + 32 + 0x00000000 + 0xFFFFFFF8 + + + LLPOINTERL + Low part of the pointer to the next descriptor. The pointer must be double word aligned. + 3 + 29 + read-write + + + + + + + + GPIOM + GPIOM + GPIOM + 0xf00d8000 + + 0x0 + 0x780 + registers + + + + 15 + 0x80 + gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy + ASSIGN[%s] + no description available + 0x0 + + 32 + 0x4 + PIN00,PIN01,PIN02,PIN03,PIN04,PIN05,PIN06,PIN07,PIN08,PIN09,PIN10,PIN11,PIN12,PIN13,PIN14,PIN15,PIN16,PIN17,PIN18,PIN19,PIN20,PIN21,PIN22,PIN23,PIN24,PIN25,PIN26,PIN27,PIN28,PIN29,PIN30,PIN31 + PIN[%s] + no description available + 0x0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +2: cpu0 fastgpio + 0 + 2 + read-write + + + + + + + + MCAN0 + MCAN0 + MCAN + 0xf0280000 + + 0x4 + 0x408 + registers + + + + ENDN + endian register + 0x4 + 32 + 0x87654321 + 0xFFFFFFFF + + + EVT + Endianness Test Value +The endianness test value is 0x87654321. + 0 + 32 + read-only + + + + + DBTP + data bit timing and prescaler, writeable when CCCR.CCE and CCCR.INT are set + 0xc + 32 + 0x00000A33 + 0x009F1FFF + + + TDC + transmitter delay compensation enable +0= Transmitter Delay Compensation disabled +1= Transmitter Delay Compensation enabled + 23 + 1 + read-write + + + DBRP + Data Bit Rate Prescaler +The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. +When TDC = ‘1’, the range is limited to 0,1. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + 16 + 5 + read-write + + + DTSEG1 + Data time segment before sample point +Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. + 8 + 5 + read-write + + + DTSEG2 + Data time segment after sample point +Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. + 4 + 4 + read-write + + + DSJW + Data (Re)Synchronization Jump Width +Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + 0 + 4 + read-write + + + + + TEST + test register + 0x10 + 32 + 0x00000000 + 0x003F3FF0 + + + SVAL + Started Valid +0= Value of TXBNS not valid +1= Value of TXBNS valid + 21 + 1 + read-only + + + TXBNS + Tx Buffer Number Started +Tx Buffer number of message whose transmission was started last. Valid when SVAL is set. Valid values are 0 to 31. + 16 + 5 + read-only + + + PVAL + Prepared Valid +0= Value of TXBNP not valid +1= Value of TXBNP valid + 13 + 1 + read-only + + + TXBNP + Tx Buffer Number Prepared +Tx Buffer number of message that is ready for transmission. Valid when PVAL is set.Valid values are 0 to 31. + 8 + 5 + read-only + + + RX + Receive Pin +Monitors the actual value of pin m_can_rx +0= The CAN bus is dominant (m_can_rx = ‘0’) +1= The CAN bus is recessive (m_can_rx = ‘1’) + 7 + 1 + read-only + + + TX + Control of Transmit Pin +00 Reset value, m_can_tx controlled by the CAN Core, updated at the end of the CAN bit time +01 Sample Point can be monitored at pin m_can_tx +10 Dominant (‘0’) level at pin m_can_tx +11 Recessive (‘1’) at pin m_can_tx + 5 + 2 + read-write + + + LBCK + Loop Back Mode +0= Reset value, Loop Back Mode is disabled +1= Loop Back Mode is enabled + 4 + 1 + read-write + + + + + RWD + ram watchdog + 0x14 + 32 + 0x00000000 + 0x0000FFFF + + + WDV + Watchdog Value +Actual Message RAM Watchdog Counter Value. + 8 + 8 + read-only + + + WDC + Watchdog Configuration +Start value of the Message RAM Watchdog Counter. With the reset value of “00” the counter is disabled. + 0 + 8 + read-write + + + + + CCCR + CC control register + 0x18 + 32 + 0x00000001 + 0x0000FFFF + + + NISO + Non ISO Operation +If this bit is set, the M_CAN uses the CAN FD frame format as specified by the Bosch CAN FD +Specification V1.0. +0= CAN FD frame format according to ISO 11898-1:2015 +1= CAN FD frame format according to Bosch CAN FD Specification V1.0 +Note: When the generic parameter iso_only_g is set to ‘1’ in hardware synthesis, this bit becomes reserved and is read as ‘0’. The M_CAN always operates with the CAN FD frame format according to ISO 11898-1:2015. + 15 + 1 + read-write + + + TXP + Transmit Pause +If this bit is set, the M_CAN pauses for two CAN bit times before starting the next transmission after +itself has successfully transmitted a frame (see Section 3.5). +0= Transmit pause disabled +1= Transmit pause enabled + 14 + 1 + read-write + + + EFBI + Edge Filtering during Bus Integration +0= Edge filtering disabled +1= Two consecutive dominant tq required to detect an edge for hard synchronization + 13 + 1 + read-write + + + PXHD + Protocol Exception Handling Disable +0= Protocol exception handling enabled +1= Protocol exception handling disabled +Note: When protocol exception handling is disabled, the M_CAN will transmit an error frame when it detects a protocol exception condition. + 12 + 1 + read-write + + + WMM + Wide Message Marker +Enables the use of 16-bit Wide Message Markers. When 16-bit Wide Message Markers are used (WMM = ‘1’), 16-bit internal timestamping is disabled for the Tx Event FIFO. +0= 8-bit Message Marker used +1= 16-bit Message Marker used, replacing 16-bit timestamps in Tx Event FIFO + 11 + 1 + read-write + + + UTSU + Use Timestamping Unit +When UTSU is set, 16-bit Wide Message Markers are also enabled regardless of the value of WMM. +0= Internal time stamping +1= External time stamping by TSU +Note: When generic parameter connected_tsu_g = ‘0’, there is no TSU connected to the M_CAN. +In this case bit UTSU is fixed to zero by synthesis. + 10 + 1 + read-write + + + BRSE + Bit Rate Switch Enable +0= Bit rate switching for transmissions disabled +1= Bit rate switching for transmissions enabled +Note: When CAN FD operation is disabled FDOE = ‘0’, BRSE is not evaluated. + 9 + 1 + read-write + + + FDOE + FD Operation Enable +0= FD operation disabled +1= FD operation enabled + 8 + 1 + read-write + + + TEST + Test Mode Enable +0= Normal operation, register TEST holds reset values +1= Test Mode, write access to register TEST enabled + 7 + 1 + read-write + + + DAR + Disable Automatic Retransmission +0= Automatic retransmission of messages not transmitted successfully enabled +1= Automatic retransmission disabled + 6 + 1 + read-write + + + MON + Bus Monitoring Mode +Bit MON can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. +0= Bus Monitoring Mode is disabled +1= Bus Monitoring Mode is enabled + 5 + 1 + read-write + + + CSR + Clock Stop Request +0= No clock stop is requested +1= Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle. + 4 + 1 + read-write + + + CSA + Clock Stop Acknowledge +0= No clock stop acknowledged +1= M_CAN may be set in power down by stopping m_can_hclk and m_can_cclk + 3 + 1 + read-only + + + ASM + Restricted Operation Mode +Bit ASM can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. For a description of the Restricted Operation Mode see Section 3.1.5. +0= Normal CAN operation +1= Restricted Operation Mode active + 2 + 1 + read-write + + + CCE + Configuration Change Enable +0= The CPU has no write access to the protected configuration registers +1= The CPU has write access to the protected configuration registers (while CCCR.INIT = ‘1’) + 1 + 1 + read-write + + + INIT + Initialization +0= Normal Operation +1= Initialization is started + 0 + 1 + read-write + + + + + NBTP + nominal bit timing and prescaler register + 0x1c + 32 + 0x06000A03 + 0xFFFFFF7F + + + NSJW + Nominal (Re)Synchronization Jump Width +Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + 25 + 7 + read-write + + + NBRP + Nominal Bit Rate Prescaler +The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is +such that one more than the value programmed here is used. + 16 + 9 + read-write + + + NTSEG1 + Nominal Time segment before sample point +Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. + 8 + 8 + read-write + + + NTSEG2 + Nominal Time segment after sample point +Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. + 0 + 7 + read-write + + + + + TSCC + timestamp counter configuration + 0x20 + 32 + 0x00000000 + 0x000F0003 + + + TCP + Timestamp Counter Prescaler +Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1…16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + 16 + 4 + read-write + + + TSS + timestamp Select +00= Timestamp counter value always 0x0000 +01= Timestamp counter value incremented according to TCP +10= External timestamp counter value used +11= Same as “00” + 0 + 2 + read-write + + + + + TSCV + timestamp counter value + 0x24 + 32 + 0x00000000 + 0x0000FFFF + + + TSC + Timestamp Counter +The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx).When TSCC.TSS = “01”, the Timestamp Counter is incremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. +A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = “10”, TSC reflects the external Timestamp Counter value. A write access has no impact. + 0 + 16 + read-only + + + + + TOCC + timeout counter configuration + 0x28 + 32 + 0xFFFF0000 + 0xFFFF0007 + + + TOP + Timeout Period +Start value of the Timeout Counter (down-counter). Configures the Timeout Period. + 16 + 16 + read-write + + + TOS + Timeout Select +When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. +When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. +00= Continuous operation +01= Timeout controlled by Tx Event FIFO +10= Timeout controlled by Rx FIFO 0 +11= Timeout controlled by Rx FIFO 1 + 1 + 2 + read-write + + + RP + Enable Timeout Counter +0= Timeout Counter disabled +1= Timeout Counter enabled + 0 + 1 + read-write + + + + + TOCV + timeout counter value + 0x2c + 32 + 0x0000FFFF + 0x0000FFFF + + + TOC + Timeout Counter +The Timeout Counter is decremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. +When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. +Note: Byte access: when TOCC.TOS = “00，writing one of the register bytes 3/2/1/0 will preset the Timeout Counter. + 0 + 16 + read-only + + + + + ECR + error counter register + 0x40 + 32 + 0x00000000 + 0x00FFFFFF + + + CEL + CAN Error Logging +The counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. +The counter is also incremented when the Bus_Off limit is reached. It is not incremented when only RP is set without changing REC. The increment of CEL follows after the increment of REC or TEC. +The counter is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. +Note: Byte access: Reading byte 2 will reset CEL to zero, reading bytes 3/1/0 has no impact. + 16 + 8 + read-only + + + RP + Receive Error Passive +0= The Receive Error Counter is below the error passive level of 128 +1= The Receive Error Counter has reached the error passive level of 128 + 15 + 1 + read-only + + + REC + Receive Error Counter +Actual state of the Receive Error Counter, values between 0 and 127 + 8 + 7 + read-only + + + TEC + Transmit Error Counter +Actual state of the Transmit Error Counter, values between 0 and 255 +Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented. + 0 + 8 + read-only + + + + + PSR + protocol status register + 0x44 + 32 + 0x00000707 + 0x007F7FFF + + + TDCV + Transmitter Delay Compensation Value +Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. +The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. + 16 + 7 + read-only + + + PXE + Protocol Exception Event +0= No protocol exception event occurred since last read access +1= Protocol exception event occurred +Note: Byte access: Reading byte 0 will reset PXE, reading bytes 3/2/1 has no impact. + 14 + 1 + read-only + + + RFDF + Received a CAN FD Message +This bit is set independent of acceptance filtering. +0= Since this bit was reset by the CPU, no CAN FD message has been received +1= Message in CAN FD format with FDF flag set has been received +Note: Byte access: Reading byte 0 will reset RFDF, reading bytes 3/2/1 has no impact. + 13 + 1 + read-only + + + RBRS + BRS flag of last received CAN FD Message +This bit is set together with RFDF, independent of acceptance filtering. +0= Last received CAN FD message did not have its BRS flag set +1= Last received CAN FD message had its BRS flag set +Note: Byte access: Reading byte 0 will reset RBRS, reading bytes 3/2/1 has no impact. + 12 + 1 + read-only + + + RESI + ESI flag of last received CAN FD Message +This bit is set together with RFDF, independent of acceptance filtering. +0= Last received CAN FD message did not have its ESI flag set +1= Last received CAN FD message had its ESI flag set +Note: Byte access: Reading byte 0 will reset RESI, reading bytes 3/2/1 has no impact. + 11 + 1 + read-only + + + DLEC + Data Phase Last Error Code +Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set.Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with +its BRS flag set has been transferred (reception or transmission) without error. +Note: Byte access: Reading byte 0 will set DLEC to “111”, reading bytes 3/2/1 has no impact. + 8 + 3 + read-only + + + BO + Bus_Off Status +0= The M_CAN is not Bus_Off +1= The M_CAN is in Bus_Off state + 7 + 1 + read-only + + + EW + Warning Status +0= Both error counters are below the Error_Warning limit of 96 +1= At least one of error counter has reached the Error_Warning limit of 96 + 6 + 1 + read-only + + + EP + Error Passive +0= The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected +1= The M_CAN is in the Error_Passive state + 5 + 1 + read-only + + + ACT + Activity +Monitors the module’s CAN communication state. +00= Synchronizing - node is synchronizing on CAN communication +01= Idle - node is neither receiver nor transmitter +10= Receiver - node is operating as receiver +11= Transmitter - node is operating as transmitter +Note: ACT is set to “00” by a Protocol Exception Event. + 3 + 2 + read-only + + + LEC + Last Error Code +The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to ‘0’when a message has been transferred (reception or transmission) without error. +0= No Error: No error occurred since LEC has been reset by successful reception or transmission. +1= Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. +2= Form Error: A fixed format part of a received frame has the wrong format. +3= AckError: The message transmitted by the M_CAN was not acknowledged by another node. +4= Bit1Error: During the transmission of a message (with the exception of the arbitration field), +the device wanted to send a recessive level (bit of logical value ‘1’), but the monitored bus +value was dominant. +5= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value‘0’), but the monitored bus value was recessive. + During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at +dominant or continuously disturbed). +6= CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. +7= NoChange: Any read access to the Protocol Status Register re-initializes the LEC to ‘7’. When the LEC shows the value ‘7’, no CAN bus event was detected since the last CPU read access to the Protocol Status Register. +Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error. +Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord,stopping all bus activities. + Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. +At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, +enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences. +Note: Byte access: Reading byte 0 will set LEC to “111”, reading bytes 3/2/1 has no impact. + 0 + 3 + read-only + + + + + TDCR + transmitter delay compensation + 0x48 + 32 + 0x00000000 + 0x00007F7F + + + TDCO + Transmitter Delay Compensation SSP Offset +Offset value defining the distance between the measured delay from m_can_tx to m_can_rx and the secondary sample point. Valid values are 0 to 127 mtq. + 8 + 7 + read-write + + + TDCF + Transmitter Delay Compensation Filter Window Length +Defines the minimum value for the SSP position, dominant edges on m_can_rx that would result in an earlier SSP position are ignored for transmitter delay measurement. +The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq. + 0 + 7 + read-write + + + + + IR + interrupt register + 0x50 + 32 + 0x00000000 + 0x3FFFFFFF + + + ARA + Access to Reserved Address +0= No access to reserved address occurred +1= Access to reserved address occurred + 29 + 1 + read-write + + + PED + Protocol Error in Data Phase (Data Bit Time is used) +0= No protocol error in data phase +1= Protocol error in data phase detected (PSR.DLEC ≠ 0,7) + 28 + 1 + read-write + + + PEA + Protocol Error in Arbitration Phase (Nominal Bit Time is used) +0= No protocol error in arbitration phase +1= Protocol error in arbitration phase detected (PSR.LEC ≠ 0,7) + 27 + 1 + read-write + + + WDI + Watchdog Interrupt +0= No Message RAM Watchdog event occurred +1= Message RAM Watchdog event due to missing READY + 26 + 1 + read-write + + + BO + Bus_Off Status +0= Bus_Off status unchanged +1= Bus_Off status changed + 25 + 1 + read-write + + + EW + Warning Status +0= Error_Warning status unchanged +1= Error_Warning status changed + 24 + 1 + read-write + + + EP + Error Passive +0= Error_Passive status unchanged +1= Error_Passive status changed + 23 + 1 + read-write + + + ELO + Error Logging Overflow +0= CAN Error Logging Counter did not overflow +1= Overflow of CAN Error Logging Counter occurred + 22 + 1 + read-write + + + BEU + Bit Error Uncorrected +Message RAM bit error detected, uncorrected. Controlled by input signal m_can_aeim_berr[1] generated by an optional external parity / ECC logic attached to the Message RAM. +An uncorrected Message RAM bit error sets CCCR.INIT to ‘1’. This is done to avoid transmission of corrupted data. +0= No bit error detected when reading from Message RAM +1= Bit error detected, uncorrected (e.g. parity logic) + 21 + 1 + read-write + + + BEC + Bit Error Corrected +Message RAM bit error detected and corrected. Controlled by input signal m_can_aeim_berr[0] generated by an optional external parity / ECC logic attached to the Message RAM. +0= No bit error detected when reading from Message RAM +1= Bit error detected and corrected (e.g. ECC) + 20 + 1 + read-write + + + DRX + Message stored to Dedicated Rx Buffer +The flag is set whenever a received message has been stored into a dedicated Rx Buffer. +0= No Rx Buffer updated +1= At least one received message stored into an Rx Buffer + 19 + 1 + read-write + + + TOO + Timeout Occurred +0= No timeout +1= Timeout reached + 18 + 1 + read-write + + + MRAF + Message RAM Access Failure +The flag is set, when the Rx Handler +.has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message +storage is aborted and the Rx Handler starts processing of the following message. +.was not able to write a message to the Message RAM. In this case message storage is aborted. +In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. +The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the +M_CAN is switched into Restricted Operation Mode (see Section 3.1.5). To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM. +0= No Message RAM access failure occurred +1= Message RAM access failure occurred + 17 + 1 + read-write + + + TSW + Timestamp Wraparound +0= No timestamp counter wrap-around +1= Timestamp counter wrapped around + 16 + 1 + read-write + + + TEFL + Tx Event FIFO Element Lost +0= No Tx Event FIFO element lost +1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero + 15 + 1 + read-write + + + TEFF + Tx Event FIFO Full +0= Tx Event FIFO not full +1= Tx Event FIFO full + 14 + 1 + read-write + + + TEFW + Tx Event FIFO Watermark Reached +0= Tx Event FIFO fill level below watermark +1= Tx Event FIFO fill level reached watermark + 13 + 1 + read-write + + + TEFN + Tx Event FIFO New Entry +0= Tx Event FIFO unchanged +1= Tx Handler wrote Tx Event FIFO element + 12 + 1 + read-write + + + TFE + Tx FIFO Empty +0= Tx FIFO non-empty +1= Tx FIFO empty + 11 + 1 + read-write + + + TCF + Transmission Cancellation Finished +0= No transmission cancellation finished +1= Transmission cancellation finished + 10 + 1 + read-write + + + TC + Transmission Completed +0= No transmission completed +1= Transmission completed + 9 + 1 + read-write + + + HPM + High Priority Message +0= No high priority message received +1= High priority message received + 8 + 1 + read-write + + + RF1L + Rx FIFO 1 Message Lost +0= No Rx FIFO 1 message lost +1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero + 7 + 1 + read-write + + + RF1F + Rx FIFO 1 Full +0= Rx FIFO 1 not full +1= Rx FIFO 1 full + 6 + 1 + read-write + + + RF1W + Rx FIFO 1 Watermark Reached +0= Rx FIFO 1 fill level below watermark +1= Rx FIFO 1 fill level reached watermark + 5 + 1 + read-write + + + RF1N + Rx FIFO 1 New Message +0= No new message written to Rx FIFO 1 +1= New message written to Rx FIFO 1 + 4 + 1 + read-write + + + RF0L + Rx FIFO 0 Message Lost +0= No Rx FIFO 0 message lost +1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero + 3 + 1 + read-write + + + RF0F + Rx FIFO 0 Full +0= Rx FIFO 0 not full +1= Rx FIFO 0 full + 2 + 1 + read-write + + + RF0W + Rx FIFO 0 Watermark Reached +0= Rx FIFO 0 fill level below watermark +1= Rx FIFO 0 fill level reached watermark + 1 + 1 + read-write + + + RF0N + Rx FIFO 0 New Message +0= No new message written to Rx FIFO 0 +1= New message written to Rx FIFO 0 + 0 + 1 + read-write + + + + + IE + interrupt enable + 0x54 + 32 + 0x00000000 + 0x3FFFFFFF + + + ARAE + Access to Reserved Address Enable + 29 + 1 + read-write + + + PEDE + Protocol Error in Data Phase Enable + 28 + 1 + read-write + + + PEAE + Protocol Error in Arbitration Phase Enable + 27 + 1 + read-write + + + WDIE + Watchdog Interrupt Enable + 26 + 1 + read-write + + + BOE + Bus_Off Status Interrupt Enable + 25 + 1 + read-write + + + EWE + Warning Status Interrupt Enable + 24 + 1 + read-write + + + EPE + Error Passive Interrupt Enable + 23 + 1 + read-write + + + ELOE + Error Logging Overflow Interrupt Enable + 22 + 1 + read-write + + + BEUE + Bit Error Uncorrected Interrupt Enable + 21 + 1 + read-write + + + BECE + Bit Error Corrected Interrupt Enable + 20 + 1 + read-write + + + DRXE + Message stored to Dedicated Rx Buffer Interrupt Enable + 19 + 1 + read-write + + + TOOE + Timeout Occurred Interrupt Enable + 18 + 1 + read-write + + + MRAFE + Message RAM Access Failure Interrupt Enable + 17 + 1 + read-write + + + TSWE + Timestamp Wraparound Interrupt Enable + 16 + 1 + read-write + + + TEFLE + Tx Event FIFO Event Lost Interrupt Enable + 15 + 1 + read-write + + + TEFFE + Tx Event FIFO Full Interrupt Enable + 14 + 1 + read-write + + + TEFWE + Tx Event FIFO Watermark Reached Interrupt Enable + 13 + 1 + read-write + + + TEFNE + Tx Event FIFO New Entry Interrupt Enable + 12 + 1 + read-write + + + TFEE + Tx FIFO Empty Interrupt Enable + 11 + 1 + read-write + + + TCFE + Transmission Cancellation Finished Interrupt Enable + 10 + 1 + read-write + + + TCE + Transmission Completed Interrupt Enable + 9 + 1 + read-write + + + HPME + High Priority Message Interrupt Enable + 8 + 1 + read-write + + + RF1LE + Rx FIFO 1 Message Lost Interrupt Enable + 7 + 1 + read-write + + + RF1FE + Rx FIFO 1 Full Interrupt Enable + 6 + 1 + read-write + + + RF1WE + Rx FIFO 1 Watermark Reached Interrupt Enable + 5 + 1 + read-write + + + RF1NE + Rx FIFO 1 New Message Interrupt Enable + 4 + 1 + read-write + + + RF0LE + Rx FIFO 0 Message Lost Interrupt Enable + 3 + 1 + read-write + + + RF0FE + Rx FIFO 0 Full Interrupt Enable + 2 + 1 + read-write + + + RF0WE + Rx FIFO 0 Watermark Reached Interrupt Enable + 1 + 1 + read-write + + + RF0NE + Rx FIFO 0 New Message Interrupt Enable + 0 + 1 + read-write + + + + + ILS + interrupt line select + 0x58 + 32 + 0x00000000 + 0x3FFFFFFF + + + ARAL + Access to Reserved Address Line + 29 + 1 + read-write + + + PEDL + Protocol Error in Data Phase Line + 28 + 1 + read-write + + + PEAL + Protocol Error in Arbitration Phase Line + 27 + 1 + read-write + + + WDIL + Watchdog Interrupt Line + 26 + 1 + read-write + + + BOL + Bus_Off Status Interrupt Line + 25 + 1 + read-write + + + EWL + Warning Status Interrupt Line + 24 + 1 + read-write + + + EPL + Error Passive Interrupt Line + 23 + 1 + read-write + + + ELOL + Error Logging Overflow Interrupt Line + 22 + 1 + read-write + + + BEUL + Bit Error Uncorrected Interrupt Line + 21 + 1 + read-write + + + BECL + Bit Error Corrected Interrupt Line + 20 + 1 + read-write + + + DRXL + Message stored to Dedicated Rx Buffer Interrupt Line + 19 + 1 + read-write + + + TOOL + Timeout Occurred Interrupt Line + 18 + 1 + read-write + + + MRAFL + Message RAM Access Failure Interrupt Line + 17 + 1 + read-write + + + TSWL + Timestamp Wraparound Interrupt Line + 16 + 1 + read-write + + + TEFLL + Tx Event FIFO Event Lost Interrupt Line + 15 + 1 + read-write + + + TEFFL + Tx Event FIFO Full Interrupt Line + 14 + 1 + read-write + + + TEFWL + Tx Event FIFO Watermark Reached Interrupt Line + 13 + 1 + read-write + + + TEFNL + Tx Event FIFO New Entry Interrupt Line + 12 + 1 + read-write + + + TFEL + Tx FIFO Empty Interrupt Line + 11 + 1 + read-write + + + TCFL + Transmission Cancellation Finished Interrupt Line + 10 + 1 + read-write + + + TCL + Transmission Completed Interrupt Line + 9 + 1 + read-write + + + HPML + High Priority Message Interrupt Line + 8 + 1 + read-write + + + RF1LL + Rx FIFO 1 Message Lost Interrupt Line + 7 + 1 + read-write + + + RF1FL + Rx FIFO 1 Full Interrupt Line + 6 + 1 + read-write + + + RF1WL + Rx FIFO 1 Watermark Reached Interrupt Line + 5 + 1 + read-write + + + RF1NL + Rx FIFO 1 New Message Interrupt Line + 4 + 1 + read-write + + + RF0LL + Rx FIFO 0 Message Lost Interrupt Line + 3 + 1 + read-write + + + RF0FL + Rx FIFO 0 Full Interrupt Line + 2 + 1 + read-write + + + RF0WL + Rx FIFO 0 Watermark Reached Interrupt Line + 1 + 1 + read-write + + + RF0NL + Rx FIFO 0 New Message Interrupt Line + 0 + 1 + read-write + + + + + ILE + interrupt line enable + 0x5c + 32 + 0x00000000 + 0x00000003 + + + EINT1 + Enable Interrupt Line 1 +0= Interrupt line m_can_int1 disabled +1= Interrupt line m_can_int1 enabled + 1 + 1 + read-write + + + EINT0 + Enable Interrupt Line 0 +0= Interrupt line m_can_int0 disabled +1= Interrupt line m_can_int0 enabled + 0 + 1 + read-write + + + + + GFC + global filter configuration + 0x80 + 32 + 0x00000000 + 0x0000003F + + + ANFS + Accept Non-matching Frames Standard +Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. +00= Accept in Rx FIFO 0 +01= Accept in Rx FIFO 1 +10= Reject +11= Reject + 4 + 2 + read-write + + + ANFE + Accept Non-matching Frames Extended +Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. +00= Accept in Rx FIFO 0 +01= Accept in Rx FIFO 1 +10= Reject +11= Reject + 2 + 2 + read-write + + + RRFS + Reject Remote Frames Standard +0= Filter remote frames with 11-bit standard IDs +1= Reject all remote frames with 11-bit standard IDs + 1 + 1 + read-write + + + RRFE + Reject Remote Frames Extended +0= Filter remote frames with 29-bit extended IDs +1= Reject all remote frames with 29-bit extended IDs + 0 + 1 + read-write + + + + + SIDFC + standard ID filter configuration + 0x84 + 32 + 0x00000000 + 0x00FFFFFC + + + LSS + List Size Standard +0= No standard Message ID filter +1-128= Number of standard Message ID filter elements +>128= Values greater than 128 are interpreted as 128 + 16 + 8 + read-write + + + FLSSA + Filter List Standard Start Address +Start address of standard Message ID filter list (32-bit word address) + 2 + 14 + read-write + + + + + XIDFC + extended ID filter configuration + 0x88 + 32 + 0x00000000 + 0x007FFFFC + + + LSE + List Size Extended +0= No extended Message ID filter +1-64= Number of extended Message ID filter elements +>64= Values greater than 64 are interpreted as 64 + 16 + 7 + read-write + + + FLESA + Filter List Extended Start Address +Start address of extended Message ID filter list (32-bit word address). + 2 + 14 + read-write + + + + + XIDAM + extended id and mask + 0x90 + 32 + 0x1FFFFFFF + 0x1FFFFFFF + + + EIDM + Extended ID Mask +For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. + Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active. + 0 + 29 + read-write + + + + + HPMS + high priority message status + 0x94 + 32 + 0x00000000 + 0x0000FFFF + + + FLST + Filter List +Indicates the filter list of the matching filter element. +0= Standard Filter List +1= Extended Filter List + 15 + 1 + read-only + + + FIDX + Filter Index +Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1. + 8 + 7 + read-only + + + MSI + Message Storage Indicator +00= No FIFO selected +01= FIFO message lost +10= Message stored in FIFO 0 +11= Message stored in FIFO 1 + 6 + 2 + read-only + + + BIDX + Buffer Index +Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = ‘1’. + 0 + 6 + read-only + + + + + NDAT1 + new data1 + 0x98 + 32 + 0x00000000 + 0xFFFFFFFF + + + ND1 + New Data[31:0] +The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. +The flags remain set until the Host clears them.A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. +0= Rx Buffer not updated +1= Rx Buffer updated from new message + 0 + 32 + read-write + + + + + NDAT2 + new data2 + 0x9c + 32 + 0x00000000 + 0xFFFFFFFF + + + ND2 + New Data[63:32] +The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. +The flags remain set until the Host clears them. A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. +0= Rx Buffer not updated +1= Rx Buffer updated from new message + 0 + 32 + read-write + + + + + RXF0C + rx fifo 0 configuration + 0xa0 + 32 + 0x00000000 + 0xFF7FFFFC + + + F0OM + FIFO 0 Operation Mode +FIFO 0 can be operated in blocking or in overwrite mode (see Section 3.4.2). +0= FIFO 0 blocking mode +1= FIFO 0 overwrite mode + 31 + 1 + read-write + + + F0WM + Rx FIFO 0 Watermark +0= Watermark interrupt disabled +1-64= Level for Rx FIFO 0 watermark interrupt (IR.RF0W) +>64= Watermark interrupt disabled + 24 + 7 + read-write + + + F0S + Rx FIFO 0 Size +0= No Rx FIFO 0 +1-64= Number of Rx FIFO 0 elements +>64= Values greater than 64 are interpreted as 64 +The Rx FIFO 0 elements are indexed from 0 to F0S-1 + 16 + 7 + read-write + + + F0SA + Rx FIFO 0 Start Address +Start address of Rx FIFO 0 in Message RAM (32-bit word address) + 2 + 14 + read-write + + + + + RXF0S + rx fifo 0 status + 0xa4 + 32 + 0x00000000 + 0x033F3F7F + + + RF0L + Rx FIFO 0 Message Lost +This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset. +0= No Rx FIFO 0 message lost +1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero +Note: Overwriting the oldest message when RXF0C.F0OM = ‘1’ will not set this flag. + 25 + 1 + read-only + + + F0F + Rx FIFO 0 Full +0= Rx FIFO 0 not full +1= Rx FIFO 0 full + 24 + 1 + read-only + + + F0PI + Rx FIFO 0 Put Index +Rx FIFO 0 write index pointer, range 0 to 63. + 16 + 6 + read-only + + + F0GI + Rx FIFO 0 Get Index +Rx FIFO 0 read index pointer, range 0 to 63. + 8 + 6 + read-only + + + F0FL + Rx FIFO 0 Fill Level +Number of elements stored in Rx FIFO 0, range 0 to 64. + 0 + 7 + read-only + + + + + RXF0A + rx fifo0 acknowledge + 0xa8 + 32 + 0x00000000 + 0x0000003F + + + F0AI + Rx FIFO 0 Acknowledge Index +After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. +This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. + 0 + 6 + read-write + + + + + RXBC + rx buffer configuration + 0xac + 32 + 0x00000000 + 0x0000FFFC + + + RBSA + Rx Buffer Start Address +Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address).Also used to reference debug messages A,B,C. + 2 + 14 + read-write + + + + + RXF1C + rx fifo1 configuration + 0xb0 + 32 + 0x00000000 + 0xFF7FFFFC + + + F1OM + FIFO 1 Operation Mode +FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2). +0= FIFO 1 blocking mode +1= FIFO 1 overwrite mode + 31 + 1 + read-write + + + F1WM + Rx FIFO 1 Watermark +0= Watermark interrupt disabled +1-64= Level for Rx FIFO 1 watermark interrupt (IR.RF1W) +>64= Watermark interrupt disabled + 24 + 7 + read-write + + + F1S + Rx FIFO 1 Size +0= No Rx FIFO 1 +1-64= Number of Rx FIFO 1 elements +>64= Values greater than 64 are interpreted as 64 +The Rx FIFO 1 elements are indexed from 0 to F1S - 1 + 16 + 7 + read-write + + + F1SA + Rx FIFO 1 Start Address +Start address of Rx FIFO 1 in Message RAM (32-bit word address) + 2 + 14 + read-write + + + + + RXF1S + rx fifo1 status + 0xb4 + 32 + 0x00000000 + 0xC33F3F7F + + + DMS + Debug Message Status +00= Idle state, wait for reception of debug messages, DMA request is cleared +01= Debug message A received +10= Debug messages A, B received +11= Debug messages A, B, C received, DMA request is set + 30 + 2 + read-only + + + RF1L + Rx FIFO 1 Message Lost +This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset. +0= No Rx FIFO 1 message lost +1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero +Note: Overwriting the oldest message when RXF1C.F1OM = ‘1’ will not set this flag. + 25 + 1 + read-only + + + F1F + Rx FIFO 1 Full +0= Rx FIFO 1 not full +1= Rx FIFO 1 full + 24 + 1 + read-only + + + F1PI + Rx FIFO 1 Put Index +Rx FIFO 1 write index pointer, range 0 to 63. + 16 + 6 + read-only + + + F1GI + Rx FIFO 1 Get Index +Rx FIFO 1 read index pointer, range 0 to 63. + 8 + 6 + read-only + + + F1FL + Rx FIFO 1 Fill Level +Number of elements stored in Rx FIFO 1, range 0 to 64. + 0 + 7 + read-only + + + + + RXF1A + rx fifo 1 acknowledge + 0xb8 + 32 + 0x00000000 + 0x0000003F + + + F1AI + Rx FIFO 1 Acknowledge Index +After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. +This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. + 0 + 6 + read-write + + + + + RXESC + rx buffer/fifo element size configuration + 0xbc + 32 + 0x00000000 + 0x00000777 + + + RBDS + Rx Buffer Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field + 8 + 3 + read-write + + + F1DS + Rx FIFO 1 Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field + 4 + 3 + read-write + + + F0DS + Rx FIFO 0 Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field +Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, +only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame’s data field is ignored. + 0 + 3 + read-write + + + + + TXBC + tx buffer configuration + 0xc0 + 32 + 0x00000000 + 0x7F3FFFFC + + + TFQM + Tx FIFO/Queue Mode +0= Tx FIFO operation +1= Tx Queue operation + 30 + 1 + read-write + + + TFQS + Transmit FIFO/Queue Size +0= No Tx FIFO/Queue +1-32= Number of Tx Buffers used for Tx FIFO/Queue +>32= Values greater than 32 are interpreted as 32 + 24 + 6 + read-write + + + NDTB + Number of Dedicated Transmit Buffers +0= No Dedicated Tx Buffers +1-32= Number of Dedicated Tx Buffers +>32= Values greater than 32 are interpreted as 32 + 16 + 6 + read-write + + + TBSA + Tx Buffers Start Address +Start address of Tx Buffers section in Message RAM (32-bit word address, see Figure 2). +Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers. + 2 + 14 + read-write + + + + + TXFQS + tx fifo/queue status + 0xc4 + 32 + 0x00000000 + 0x003F1F3F + + + TFQF + Tx FIFO/Queue Full +0= Tx FIFO/Queue not full +1= Tx FIFO/Queue full + 21 + 1 + read-only + + + TFQPI + Tx FIFO/Queue Put Index +Tx FIFO/Queue write index pointer, range 0 to 31. + 16 + 5 + read-only + + + TFGI + Tx FIFO Get Index +Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured +(TXBC.TFQM = ‘1’). + 8 + 5 + read-only + + + TFFL + Tx FIFO Free Level +Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = ‘1’) +Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with +the first dedicated Tx Buffers. +Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO. + 0 + 6 + read-only + + + + + TXESC + tx buffer element size configuration + 0xc8 + 32 + 0x00000000 + 0x00000007 + + + TBDS + Tx Buffer Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field +Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TXESC.TBDS, the bytes not defined by the Tx Buffer are transmitted as “0xCC” (padding bytes). + 0 + 3 + read-write + + + + + TXBRP + tx buffer request pending + 0xcc + 32 + 0x00000000 + 0xFFFFFFFF + + + TRP + Transmission Request Pending +Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR.The bits are reset after a requested transmission has completed or has been cancelled via register +TXBCR. +TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan (see Section 3.5, Tx Handling) is started to check for the pending Tx request with the +highest priority (Tx Buffer with lowest Message ID). +A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, +this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. +After a cancellation has been requested, a finished cancellation is signalled via TXBCF +? after successful transmission together with the corresponding TXBTO bit +? when the transmission has not yet been started at the point of cancellation +? when the transmission has been aborted due to lost arbitration +? when an error occurred during frame transmission +In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. +0= No transmission request pending +1= Transmission request pending +Note: TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding TXBRP bit is reset. + 0 + 32 + read-only + + + + + TXBAR + tx buffer add request + 0xd0 + 32 + 0x00000000 + 0xFFFFFFFF + + + AR + Add Request +Each Tx Buffer has its own Add Request bit. Writing a ‘1’ will set the corresponding Add Request bit; writing a ‘0’ has no impact. This enables the Host to set transmission requests for multiple Tx +Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. +When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. +0= No transmission request added +1= Transmission requested added +Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding TXBRP bit already set), this add request is ignored. + 0 + 32 + read-write + + + + + TXBCR + tx buffer cancellation request + 0xd4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CR + Cancellation Request +Each Tx Buffer has its own Cancellation Request bit. Writing a ‘1’ will set the corresponding Cancellation Request bit; writing a ‘0’ has no impact. +This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. +0= No cancellation pending +1= Cancellation pending + 0 + 32 + read-write + + + + + TXBTO + tx buffer transmission occurred + 0xd8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TO + Transmission Occurred +Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. +0= No transmission occurred +1= Transmission occurred + 0 + 32 + read-only + + + + + TXBCF + tx buffer cancellation finished + 0xdc + 32 + 0x00000000 + 0xFFFFFFFF + + + CF + Cancellation Finished +Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. +In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. +0= No transmit buffer cancellation +1= Transmit buffer cancellation finished + 0 + 32 + read-only + + + + + TXBTIE + tx buffer transmission interrupt enable + 0xe0 + 32 + 0x00000000 + 0xFFFFFFFF + + + TIE + Transmission Interrupt Enable +Each Tx Buffer has its own Transmission Interrupt Enable bit. +0= Transmission interrupt disabled +1= Transmission interrupt enable + 0 + 32 + read-write + + + + + TXBCIE + tx buffer cancellation finished interrupt enable + 0xe4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CFIE + Cancellation Finished Interrupt Enable +Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. +0= Cancellation finished interrupt disabled +1= Cancellation finished interrupt enabled + 0 + 32 + read-write + + + + + TXEFC + tx event fifo configuration + 0xf0 + 32 + 0x00000000 + 0x3F3FFFFC + + + EFWM + Event FIFO Watermark +0= Watermark interrupt disabled +1-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW) +>32= Watermark interrupt disabled + 24 + 6 + read-write + + + EFS + Event FIFO Size +0= Tx Event FIFO disabled +1-32= Number of Tx Event FIFO elements +>32= Values greater than 32 are interpreted as 32 +The Tx Event FIFO elements are indexed from 0 to EFS - 1 + 16 + 6 + read-write + + + EFSA + Event FIFO Start Address +Start address of Tx Event FIFO in Message RAM (32-bit word address) + 2 + 14 + read-write + + + + + TXEFS + tx event fifo status + 0xf4 + 32 + 0x00000000 + 0x031F1F3F + + + TEFL + Tx Event FIFO Element Lost +This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset. +0= No Tx Event FIFO element lost +1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. + 25 + 1 + read-only + + + EFF + Event FIFO Full +0= Tx Event FIFO not full +1= Tx Event FIFO full + 24 + 1 + read-only + + + EFPI + Event FIFO Put Index +Tx Event FIFO write index pointer, range 0 to 31. + 16 + 5 + read-only + + + EFGI + Event FIFO Get Index +Tx Event FIFO read index pointer, range 0 to 31. + 8 + 5 + read-only + + + EFFL + Event FIFO Fill Level +Number of elements stored in Tx Event FIFO, range 0 to 32. + 0 + 6 + read-only + + + + + TXEFA + tx event fifo acknowledge + 0xf8 + 32 + 0x00000000 + 0x0000001F + + + EFAI + Event FIFO Acknowledge Index +After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get +Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL. + 0 + 5 + read-write + + + + + 16 + 0x4 + TS_SEL0,TS_SEL1,TS_SEL2,TS_SEL3,TS_SEL4,TS_SEL5,TS_SEL6,TS_SEL7,TS_SEL8,TS_SEL9,TS_SEL10,TS_SEL11,TS_SEL12,TS_SEL13,TS_SEL14,TS_SEL15 + TS_SEL[%s] + no description available + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + TS + Timestamp Word TS +default can save 16 timestamps with 32bit; +if ts64_en is set, then work at 64bit mode, can save 8 timestamps with 01/23/45…. + 0 + 32 + read-only + + + + + CREL + core release register + 0x240 + 32 + 0x00000000 + 0xFFFFFFFF + + + REL + Core Release +One digit, BCD-coded + 28 + 4 + read-only + + + STEP + Step of Core Release +One digit, BCD-coded. + 24 + 4 + read-only + + + SUBSTEP + Sub-step of Core Release +One digit, BCD-coded + 20 + 4 + read-only + + + YEAR + Timestamp Year +One digit, BCD-coded. This field is set by generic parameter on +synthesis. + 16 + 4 + read-only + + + MON + Timestamp Month +Two digits, BCD-coded. This field is set by generic parameter +on synthesis. + 8 + 8 + read-only + + + DAY + Timestamp Day +Two digits, BCD-coded. This field is set by generic parameter +on synthesis. + 0 + 8 + read-only + + + + + TSCFG + timestamp configuration + 0x244 + 32 + 0x00000000 + 0x0000FF0F + + + TBPRE + Timebase Prescaler +0x00 to 0xFF +The value by which the oscillator frequency is divided for +generating the timebase counter clock. Valid values for the +Timebase Prescaler are 0 to 255. The actual interpretation by +the hardware of this value is such that one more than the value +programmed here is used. Affects only the TSU internal +timebase. When the internal timebase is excluded by synthesis, +TBPRE[7:0] is fixed to 0x00, the Timestamp Prescaler is not +used. + 8 + 8 + read-write + + + EN64 + set to use 64bit timestamp. +when enabled, tsu can save up to 8 different timestamps, TS(k) and TS(k+1) are used for one 64bit timestamp, k is 0~7. +TSP can be used to select different one + 3 + 1 + read-write + + + SCP + Select Capturing Position +0: Capture Timestamp at EOF +1: Capture Timestamp at SOF + 2 + 1 + read-write + + + TBCS + Timebase Counter Select +When the internal timebase is excluded by synthesis, TBCS is +fixed to ‘1’. +0: Timestamp value captured from internal timebase counter, + ATB.TB[31:0] is the internal timbase counter +1: Timestamp value captured from input tsu_tbin[31:0],ATB.TB[31:0] is tsu_tbin[31:0] + 1 + 1 + read-write + + + TSUE + Timestamp Unit Enable +0: TSU disabled +1: TSU enabled + 0 + 1 + read-write + + + + + TSS1 + timestamp status1 + 0x248 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSL + Timestamp Lost +Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when the timestamp stored in the related Timestamp register was overwritten before it was read. +Reading a Timestamp register resets the related bit. + 16 + 16 + read-only + + + TSN + Timestamp New +Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when a timestamp was stored in the related +Timestamp register. Reading a Timestamp register resets the related bit. + 0 + 16 + read-only + + + + + TSS2 + timestamp status2 + 0x24c + 32 + 0x00000000 + 0x0000000F + + + TSP + Timestamp Pointer +The Timestamp Pointer is incremented by one each time a timestamp is captured. From its maximum value (3, 7, or 15 +depending on number_ts_g), it is incremented to 0. +Value also signalled on output m_can_tsp[3:0]. + 0 + 4 + read-only + + + + + ATB + actual timebase + 0x250 + 32 + 0x00000000 + 0xFFFFFFFF + + + TB + timebase for timestamp generation 31-0 + 0 + 32 + read-only + + + + + ATBH + actual timebase high + 0x254 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBH + timebase for timestamp generation 63-32 + 0 + 32 + read-only + + + + + GLB_CTL + global control + 0x400 + 32 + 0x00000000 + 0xE0000003 + + + M_CAN_STBY + m_can standby control + 31 + 1 + read-write + + + STBY_CLR_EN + m_can standby clear control +0:controlled by software by standby bit[bit31] +1:auto clear standby by hardware when rx data is 0 + 30 + 1 + read-write + + + STBY_POL + standby polarity selection + 29 + 1 + read-write + + + TSU_TBIN_SEL + external timestamp select. each CAN block has 4 timestamp input, this register is used to select one of them as timestame if TSCFG.TBCS is set to 1 + 0 + 2 + read-write + + + + + GLB_STATUS + global status + 0x404 + 32 + 0x00000000 + 0x0000000C + + + M_CAN_INT1 + m_can interrupt status1 + 3 + 1 + read-only + + + M_CAN_INT0 + m_can interrupt status0 + 2 + 1 + read-only + + + + + + + MCAN1 + MCAN1 + MCAN + 0xf0284000 + + + MCAN2 + MCAN2 + MCAN + 0xf0288000 + + + MCAN3 + MCAN3 + MCAN + 0xf028c000 + + + PTPC + PTPC + PTPC + 0xf02fc000 + + 0x0 + 0x3004 + registers + + + + 2 + 0x1000 + 0,1 + PTPC[%s] + no description available + 0x0 + + Ctrl0 + Control Register 0 + 0x0 + 32 + 0x00000000 + 0x000003FF + + + SUBSEC_DIGITAL_ROLLOVER + Format for ns counter rollover, +1-digital, overflow time 1000000000/0x3B9ACA00 +0-binary, overflow time 0x7FFFFFFF + 9 + 1 + read-write + + + CAPT_SNAP_KEEP + set will keep capture snap till software read capt_snapl. +If this bit is set, software should read capt_snaph first to avoid wrong result. +If this bit is cleared, capture result will be updated at each capture event + 8 + 1 + read-write + + + CAPT_SNAP_POS_EN + set will use posege of input capture signal to latch timestamp value + 7 + 1 + read-write + + + CAPT_SNAP_NEG_EN + No description available + 6 + 1 + read-write + + + COMP_EN + set to enable compare, will be cleared by HW when compare event triggered + 4 + 1 + read-write + + + UPDATE_TIMER + update timer with +/- ts_updt, pulse, clear after set + 3 + 1 + write-only + + + INIT_TIMER + initial timer with ts_updt, pulse, clear after set + 2 + 1 + write-only + + + FINE_COARSE_SEL + 0: coarse update, ns counter add ss_incr[7:0] each clk +1: fine update, ns counter add ss_incr[7:0] each time addend counter overflow + 1 + 1 + read-write + + + TIMER_ENABLE + No description available + 0 + 1 + read-write + + + + + ctrl1 + Control Register 1 + 0x4 + 32 + 0x00000000 + 0x000000FF + + + SS_INCR + constant value used to add ns counter; +such as for 50MHz timer clock, set it to 8'd20 + 0 + 8 + read-write + + + + + timeh + timestamp high + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMESTAMP_HIGH + No description available + 0 + 32 + read-only + + + + + timel + timestamp low + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMESTAMP_LOW + No description available + 0 + 32 + read-only + + + + + ts_updth + timestamp update high + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + SEC_UPDATE + together with ts_updtl, used to initial or update timestamp + 0 + 32 + read-write + + + + + ts_updtl + timestamp update low + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADD_SUB + 1 for sub; 0 for add, used only at update + 31 + 1 + read-write + + + NS_UPDATE + No description available + 0 + 31 + read-write + + + + + addend + No description available + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDEND + used in fine update mode only + 0 + 32 + read-write + + + + + tarh + No description available + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + TARGET_TIME_HIGH + used for generate compare signal if enabled + 0 + 32 + read-write + + + + + tarl + No description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + TARGET_TIME_LOW + No description available + 0 + 32 + read-write + + + + + pps_ctrl + No description available + 0x2c + 32 + 0x00000000 + 0x0000000F + + + PPS_CTRL + No description available + 0 + 4 + read-write + + + + + capt_snaph + No description available + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPT_SNAP_HIGH + take snapshot for input capture signal, at pos or neg or both; +the result can be kept or updated at each event according to cfg0.bit8 + 0 + 32 + read-only + + + + + capt_snapl + No description available + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPT_SNAP_LOW + No description available + 0 + 32 + read-write + + + + + + time_sel + No description available + 0x2000 + 32 + 0x00000000 + 0x0000000F + + + CAN3_TIME_SEL + No description available + 3 + 1 + read-write + + + CAN2_TIME_SEL + No description available + 2 + 1 + read-write + + + CAN1_TIME_SEL + No description available + 1 + 1 + read-write + + + CAN0_TIME_SEL + set to use ptpc1 for canx +clr to use ptpc0 for canx + 0 + 1 + read-write + + + + + int_sts + No description available + 0x2004 + 32 + 0x00000000 + 0x00070007 + + + COMP_INT_STS1 + No description available + 18 + 1 + write-only + + + CAPTURE_INT_STS1 + No description available + 17 + 1 + write-only + + + PPS_INT_STS1 + No description available + 16 + 1 + write-only + + + COMP_INT_STS0 + No description available + 2 + 1 + write-only + + + CAPTURE_INT_STS0 + No description available + 1 + 1 + write-only + + + PPS_INT_STS0 + No description available + 0 + 1 + write-only + + + + + int_en + No description available + 0x2008 + 32 + 0x00000000 + 0x00070007 + + + COMP_INT_STS1 + No description available + 18 + 1 + read-write + + + CAPTURE_INT_STS1 + No description available + 17 + 1 + read-write + + + PPS_INT_STS1 + No description available + 16 + 1 + read-write + + + COMP_INT_STS0 + No description available + 2 + 1 + read-write + + + CAPTURE_INT_STS0 + No description available + 1 + 1 + read-write + + + PPS_INT_STS0 + No description available + 0 + 1 + read-write + + + + + ptpc_can_ts_sel + No description available + 0x3000 + 32 + 0x00000000 + 0xFFFFFF00 + + + TSU_TBIN3_SEL + No description available + 26 + 6 + read-write + + + TSU_TBIN2_SEL + No description available + 20 + 6 + read-write + + + TSU_TBIN1_SEL + No description available + 14 + 6 + read-write + + + TSU_TBIN0_SEL + No description available + 8 + 6 + read-write + + + + + + + QEI0 + QEI0 + QEIV2 + 0xf0300000 + + 0x0 + 0x298 + registers + + + + cr + Control register + 0x0 + 32 + 0x00000000 + 0x807FFF7F + + + READ + 1- load phcnt, zcnt, spdcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 + 31 + 1 + write-only + + + ZCNTCFG + 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 +0- zcnt will increment or decrement when Z input assert + 22 + 1 + read-write + + + PHCALIZ + 1- phcnt will set to phidx when Z input assert(for abz digital signsl) + 21 + 1 + read-write + + + Z_ONLY_EN + 1- phcnt will set to phidx when Z input assert(for xy analog signal and digital z, also need set phcaliz) + 20 + 1 + read-write + + + H2FDIR0 + No description available + 19 + 1 + read-write + + + H2FDIR1 + No description available + 18 + 1 + read-write + + + H2RDIR0 + No description available + 17 + 1 + read-write + + + H2RDIR1 + No description available + 16 + 1 + read-write + + + PAUSEPOS + 1- pause position output valid when PAUSE assert + 15 + 1 + read-write + + + PAUSESPD + 1- pause spdcnt when PAUSE assert + 14 + 1 + read-write + + + PAUSEPH + 1- pause phcnt when PAUSE assert + 13 + 1 + read-write + + + PAUSEZ + 1- pause zcnt when PAUSE assert + 12 + 1 + read-write + + + HFDIR0 + 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction) + 11 + 1 + read-write + + + HFDIR1 + 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction) + 10 + 1 + read-write + + + HRDIR0 + 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction) + 9 + 1 + read-write + + + HRDIR1 + 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction) + 8 + 1 + read-write + + + FAULTPOS + No description available + 6 + 1 + read-write + + + SNAPEN + 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert + 5 + 1 + read-write + + + RSTCNT + 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx + 4 + 1 + read-write + + + RD_SEL + define the width/counter value(affect width_match, width_match2, width_cur, timer_cur, width_read, timer_read, +width_snap0,width_snap1, timer_snap0, timer_snap1) +0 : same as hpm1000/500/500s; +1: use width for position; use timer for angle + 3 + 1 + read-write + + + ENCTYP + 000-abz; 001-pd; 010-ud; 011-UVW(hal) +100-single A; 101-single sin; 110: sin&cos + 0 + 3 + read-write + + + + + phcfg + Phase configure register + 0x4 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + PHMAX + maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax + 0 + 32 + read-write + + + + + wdgcfg + Watchdog configure register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + WDGEN + 1- enable wdog counter + 31 + 1 + read-write + + + WDOG_CFG + define as stop if phase_cnt change is less than it +if 0, then each change of phase_cnt will clear wdog counter; +if 2, then phase_cnt change larger than 2 will clear wdog counter + 28 + 3 + read-write + + + WDGTO + watch dog timeout value + 0 + 28 + read-write + + + + + phidx + Phase index register + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + PHIDX + phcnt reset value, phcnt will reset to phidx when phcaliz set to 1 + 0 + 32 + read-write + + + + + trgoen + Tigger output enable register + 0x10 + 32 + 0x00000000 + 0xFFFC0000 + + + WDGFEN + 1- enable trigger output when wdg flag set + 31 + 1 + read-write + + + HOMEFEN + 1- enable trigger output when homef flag set + 30 + 1 + read-write + + + POSCMPFEN + 1- enable trigger output when poscmpf flag set + 29 + 1 + read-write + + + ZPHFEN + 1- enable trigger output when zphf flag set + 28 + 1 + read-write + + + ZMISSFEN + No description available + 27 + 1 + read-write + + + WIDTHTMFEN + No description available + 26 + 1 + read-write + + + POS2CMPFEN + No description available + 25 + 1 + read-write + + + DIRCHGFEN + No description available + 24 + 1 + read-write + + + CYCLE0FEN + No description available + 23 + 1 + read-write + + + CYCLE1FEN + No description available + 22 + 1 + read-write + + + PULSE0FEN + No description available + 21 + 1 + read-write + + + PULSE1FEN + No description available + 20 + 1 + read-write + + + HOME2FEN + No description available + 19 + 1 + read-write + + + FAULTFEN + No description available + 18 + 1 + read-write + + + + + readen + Read event enable register + 0x14 + 32 + 0x00000000 + 0xFFFC0000 + + + WDGFEN + 1- load counters to their read registers when wdg flag set + 31 + 1 + read-write + + + HOMEFEN + 1- load counters to their read registers when homef flag set + 30 + 1 + read-write + + + POSCMPFEN + 1- load counters to their read registers when poscmpf flag set + 29 + 1 + read-write + + + ZPHFEN + 1- load counters to their read registers when zphf flag set + 28 + 1 + read-write + + + ZMISSFEN + No description available + 27 + 1 + read-write + + + WIDTHTMFEN + No description available + 26 + 1 + read-write + + + POS2CMPFEN + No description available + 25 + 1 + read-write + + + DIRCHGFEN + No description available + 24 + 1 + read-write + + + CYCLE0FEN + No description available + 23 + 1 + read-write + + + CYCLE1FEN + No description available + 22 + 1 + read-write + + + PULSE0FEN + No description available + 21 + 1 + read-write + + + PULSE1FEN + No description available + 20 + 1 + read-write + + + HOME2FEN + No description available + 19 + 1 + read-write + + + FAULTFEN + No description available + 18 + 1 + read-write + + + + + zcmp + Z comparator + 0x18 + 32 + 0x80000000 + 0xFFFFFFFF + + + ZCMP + zcnt postion compare value + 0 + 32 + read-write + + + + + phcmp + Phase comparator + 0x1c + 32 + 0x80000000 + 0xFFFFFFFF + + + PHCMP + phcnt position compare value + 0 + 32 + read-write + + + + + spdcmp + Speed comparator + 0x20 + 32 + 0x80000000 + 0xFFFFFFFF + + + SPDCMP + spdcnt position compare value + 0 + 32 + read-write + + + + + dmaen + DMA request enable register + 0x24 + 32 + 0x00000000 + 0xFFFC0000 + + + WDGFEN + 1- generate dma request when wdg flag set + 31 + 1 + read-write + + + HOMEFEN + 1- generate dma request when homef flag set + 30 + 1 + read-write + + + POSCMPFEN + 1- generate dma request when poscmpf flag set + 29 + 1 + read-write + + + ZPHFEN + 1- generate dma request when zphf flag set + 28 + 1 + read-write + + + ZMISSFEN + No description available + 27 + 1 + read-write + + + WIDTHTMFEN + No description available + 26 + 1 + read-write + + + POS2CMPFEN + No description available + 25 + 1 + read-write + + + DIRCHGFEN + No description available + 24 + 1 + read-write + + + CYCLE0FEN + No description available + 23 + 1 + read-write + + + CYCLE1FEN + No description available + 22 + 1 + read-write + + + PULSE0FEN + No description available + 21 + 1 + read-write + + + PULSE1FEN + No description available + 20 + 1 + read-write + + + HOME2FEN + No description available + 19 + 1 + read-write + + + FAULTFEN + No description available + 18 + 1 + read-write + + + + + sr + Status register + 0x28 + 32 + 0x00000000 + 0xFFFC0000 + + + WDGF + watchdog flag + 31 + 1 + read-write + + + HOMEF + home flag + 30 + 1 + read-write + + + POSCMPF + postion compare match flag + 29 + 1 + read-write + + + ZPHF + z input flag + 28 + 1 + read-write + + + ZMISSF + No description available + 27 + 1 + read-write + + + WIDTHTMF + No description available + 26 + 1 + read-write + + + POS2CMPF + No description available + 25 + 1 + read-write + + + DIRCHGF + No description available + 24 + 1 + read-write + + + CYCLE0F + No description available + 23 + 1 + read-write + + + CYCLE1F + No description available + 22 + 1 + read-write + + + PULSE0F + No description available + 21 + 1 + read-write + + + PULSE1F + No description available + 20 + 1 + read-write + + + HOME2F + No description available + 19 + 1 + read-write + + + FAULTF + No description available + 18 + 1 + read-write + + + + + irqen + Interrupt request register + 0x2c + 32 + 0x00000000 + 0xFFFC0000 + + + WDGIE + 1- generate interrupt when wdg flag set + 31 + 1 + read-write + + + HOMEIE + 1- generate interrupt when homef flag set + 30 + 1 + read-write + + + POSCMPIE + 1- generate interrupt when poscmpf flag set + 29 + 1 + read-write + + + ZPHIE + 1- generate interrupt when zphf flag set + 28 + 1 + read-write + + + ZMISSE + No description available + 27 + 1 + read-write + + + WIDTHTME + No description available + 26 + 1 + read-write + + + POS2CMPE + No description available + 25 + 1 + read-write + + + DIRCHGE + No description available + 24 + 1 + read-write + + + CYCLE0E + No description available + 23 + 1 + read-write + + + CYCLE1E + No description available + 22 + 1 + read-write + + + PULSE0E + No description available + 21 + 1 + read-write + + + PULSE1E + No description available + 20 + 1 + read-write + + + HOME2E + No description available + 19 + 1 + read-write + + + FAULTE + No description available + 18 + 1 + read-write + + + + + 4 + 0x10 + current,read,snap0,snap1 + COUNT[%s] + no description available + 0x30 + + z + Z counter + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + ZCNT + zcnt value + 0 + 32 + read-write + + + + + ph + Phase counter + 0x4 + 32 + 0x00000000 + 0x461FFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 30 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 26 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 25 + 1 + read-only + + + PHCNT + phcnt value + 0 + 21 + read-only + + + + + spd + Speed counter + 0x8 + 32 + 0x00000000 + 0xEFFFFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 31 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 30 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 29 + 1 + read-write + + + SPDCNT + spdcnt value + 0 + 28 + read-only + + + + + tmr + Timer counter + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + TMRCNT + 32 bit free run timer + 0 + 32 + read-only + + + + + + zcmp2 + Z comparator + 0x80 + 32 + 0x80000000 + 0xFFFFFFFF + + + ZCMP2 + No description available + 0 + 32 + read-write + + + + + phcmp2 + Phase comparator + 0x84 + 32 + 0x80000000 + 0xFFFFFFFF + + + PHCMP2 + No description available + 0 + 32 + read-write + + + + + spdcmp2 + Speed comparator + 0x88 + 32 + 0x80000000 + 0xFFFFFFFF + + + SPDCMP2 + No description available + 0 + 32 + read-write + + + + + match_cfg + No description available + 0x8c + 32 + 0x00000000 + 0xFE00FE00 + + + ZCMPDIS + 1- postion compare not include zcnt + 31 + 1 + read-write + + + DIRCMPDIS + 1- postion compare not include rotation direction + 30 + 1 + read-write + + + DIRCMP + 0- position compare need positive rotation +1- position compare need negative rotation + 29 + 1 + read-write + + + SPDCMPDIS + No description available + 28 + 1 + read-write + + + PHASE_MATCH_DIS + No description available + 27 + 1 + read-write + + + POS_MATCH_DIR + No description available + 26 + 1 + read-write + + + POS_MATCH_OPT + No description available + 25 + 1 + read-write + + + ZCMP2DIS + No description available + 15 + 1 + read-write + + + DIRCMP2DIS + No description available + 14 + 1 + read-write + + + DIRCMP2 + No description available + 13 + 1 + read-write + + + SPDCMP2DIS + No description available + 12 + 1 + read-write + + + PHASE_MATCH_DIS2 + No description available + 11 + 1 + read-write + + + POS_MATCH2_DIR + No description available + 10 + 1 + read-write + + + POS_MATCH2_OPT + No description available + 9 + 1 + read-write + + + + + 6 + 0x4 + filt_cfg_a,filt_cfg_b,filt_cfg_z,filt_cfg_h,filt_cfg_h2,filt_cfg_f + FILT_CFG[%s] + no description available + 0x90 + 32 + 0x00001000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stable low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + qei_cfg + qei config register + 0x100 + 32 + 0x00000000 + 0x0000103F + + + SPEED_DIR_CHG_EN + clear counter if detect direction change + 12 + 1 + read-write + + + UVW_POS_OPT0 + set to output next area position for QEO use; +clr to output exact point position for MMC use + 5 + 1 + read-write + + + NEGEDGE_EN + bit4: negedge enable +bit3: posedge enable +bit2: W in hal enable +bit1: signal b(or V in hal) enable +bit0: signal a(or U in hal) enable +such as: +01001: use posedge A +11010: use both edge of signal B +11111: use both edge of all HAL siganls + 4 + 1 + read-write + + + POSIDGE_EN + No description available + 3 + 1 + read-write + + + SIGZ_EN + No description available + 2 + 1 + read-write + + + SIGB_EN + No description available + 1 + 1 + read-write + + + SIGA_EN + No description available + 0 + 1 + read-write + + + + + pulse0_num + pulse0_num + 0x110 + 32 + 0x00000000 + 0xFFFFFFFF + + + PULSE0_NUM + for speed detection, will count the cycle number for configed pulse_num + 0 + 32 + read-write + + + + + pulse1_num + pulse1_num + 0x114 + 32 + 0x00000000 + 0xFFFFFFFF + + + PULSE1_NUM + No description available + 0 + 32 + read-write + + + + + cycle0_cnt + cycle0_cnt + 0x118 + 32 + 0x00000000 + 0xFFFFFFFF + + + CYCLE0_CNT + No description available + 0 + 32 + read-only + + + + + cycle0pulse_cnt + cycle0pulse_cnt + 0x11c + 32 + 0x00000000 + 0xFFFFFFFF + + + CYCLE0PULSE_CNT + No description available + 0 + 32 + read-only + + + + + cycle1_cnt + cycle1_cnt + 0x120 + 32 + 0x00000000 + 0xFFFFFFFF + + + CYCLE1_CNT + No description available + 0 + 32 + read-only + + + + + cycle1pulse_cnt + cycle1pulse_cnt + 0x124 + 32 + 0x00000000 + 0xFFFFFFFF + + + CYCLE1PULSE_CNT + No description available + 0 + 32 + read-only + + + + + cycle0_snap0 + cycle0_snap0 + 0x128 + 32 + 0x00000000 + 0xFFFFFFFF + + + CYCLE0_SNAP0 + No description available + 0 + 32 + read-only + + + + + cycle0_snap1 + cycle0_snap1 + 0x12c + 32 + 0x00000000 + 0xFFFFFFFF + + + CYCLE0_SNAP1 + No description available + 0 + 32 + read-only + + + + + cycle1_snap0 + cycle1_snap0 + 0x130 + 32 + 0x00000000 + 0xFFFFFFFF + + + CYCLE1_SNAP0 + No description available + 0 + 32 + read-only + + + + + cycle1_snap1 + cycle1_snap1 + 0x134 + 32 + 0x00000000 + 0xFFFFFFFF + + + CYCLE1_SNAP1 + No description available + 0 + 32 + read-only + + + + + cycle0_num + cycle0_num + 0x140 + 32 + 0x00000000 + 0xFFFFFFFF + + + CYCLE0_NUM + No description available + 0 + 32 + read-write + + + + + cycle1_num + cycle1_num + 0x144 + 32 + 0x00000000 + 0xFFFFFFFF + + + CYCLE1_NUM + No description available + 0 + 32 + read-write + + + + + pulse0_cnt + pulse0_cnt + 0x148 + 32 + 0x00000000 + 0xFFFFFFFF + + + PULSE0_CNT + No description available + 0 + 32 + read-only + + + + + pulse0cycle_cnt + pulse0cycle_cnt + 0x14c + 32 + 0x00000000 + 0xFFFFFFFF + + + PULSE0CYCLE_CNT + No description available + 0 + 32 + read-only + + + + + pulse1_cnt + pulse1_cnt + 0x150 + 32 + 0x00000000 + 0xFFFFFFFF + + + PULSE1_CNT + No description available + 0 + 32 + read-only + + + + + pulse1cycle_cnt + pulse1cycle_cnt + 0x154 + 32 + 0x00000000 + 0xFFFFFFFF + + + PULSE1CYCLE_CNT + No description available + 0 + 32 + read-only + + + + + pulse0_snap0 + pulse0_snap0 + 0x158 + 32 + 0x00000000 + 0xFFFFFFFF + + + PULSE0_SNAP0 + No description available + 0 + 32 + read-only + + + + + pulse0cycle_snap0 + pulse0cycle_snap0 + 0x15c + 32 + 0x00000000 + 0xFFFFFFFF + + + PULSE0CYCLE_SNAP0 + No description available + 0 + 32 + read-only + + + + + pulse0_snap1 + pulse0_snap1 + 0x160 + 32 + 0x00000000 + 0xFFFFFFFF + + + PULSE0_SNAP1 + No description available + 0 + 32 + read-only + + + + + pulse0cycle_snap1 + pulse0cycle_snap1 + 0x164 + 32 + 0x00000000 + 0xFFFFFFFF + + + PULSE0CYCLE_SNAP1 + No description available + 0 + 32 + read-only + + + + + pulse1_snap0 + pulse1_snap0 + 0x168 + 32 + 0x00000000 + 0xFFFFFFFF + + + PULSE1_SNAP0 + No description available + 0 + 32 + read-only + + + + + pulse1cycle_snap0 + pulse1cycle_snap0 + 0x16c + 32 + 0x00000000 + 0xFFFFFFFF + + + PULSE1CYCLE_SNAP0 + No description available + 0 + 32 + read-only + + + + + pulse1_snap1 + pulse1_snap1 + 0x170 + 32 + 0x00000000 + 0xFFFFFFFF + + + PULSE1_SNAP1 + No description available + 0 + 32 + read-only + + + + + pulse1cycle_snap1 + pulse1cycle_snap1 + 0x174 + 32 + 0x00000000 + 0xFFFFFFFF + + + PULSE1CYCLE_SNAP1 + No description available + 0 + 32 + read-only + + + + + adcx_cfg0 + adcx_cfg0 + 0x200 + 32 + 0x00000000 + 0x0000019F + + + X_ADCSEL + No description available + 8 + 1 + read-write + + + X_ADC_ENABLE + No description available + 7 + 1 + read-write + + + X_CHAN + No description available + 0 + 5 + read-write + + + + + adcx_cfg1 + adcx_cfg1 + 0x204 + 32 + 0x00004000 + 0xFFFFFFFF + + + X_PARAM1 + No description available + 16 + 16 + read-write + + + X_PARAM0 + No description available + 0 + 16 + read-write + + + + + adcx_cfg2 + adcx_cfg2 + 0x208 + 32 + 0x80000000 + 0xFFFFFFFF + + + X_OFFSET + No description available + 0 + 32 + read-write + + + + + adcy_cfg0 + adcy_cfg0 + 0x210 + 32 + 0x00000000 + 0x0000019F + + + Y_ADCSEL + No description available + 8 + 1 + read-write + + + Y_ADC_ENABLE + No description available + 7 + 1 + read-write + + + Y_CHAN + No description available + 0 + 5 + read-write + + + + + adcy_cfg1 + adcy_cfg1 + 0x214 + 32 + 0x40000000 + 0xFFFFFFFF + + + Y_PARAM1 + No description available + 16 + 16 + read-write + + + Y_PARAM0 + No description available + 0 + 16 + read-write + + + + + adcy_cfg2 + adcy_cfg2 + 0x218 + 32 + 0x80000000 + 0xFFFFFFFF + + + Y_OFFSET + No description available + 0 + 32 + read-write + + + + + cal_cfg + cal_cfg + 0x220 + 32 + 0x00000100 + 0x00FFFFFF + + + XY_DELAY + valid x/y delay, larger than this delay will be treated as invalid data. +Default 1.25us@200MHz; max 80ms; + 0 + 24 + read-write + + + + + phase_param + phase_param + 0x230 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + PHASE_PARAM + No description available + 0 + 32 + read-write + + + + + angle_adj + angle_adj + 0x234 + 32 + 0x00000000 + 0xFFFFFFFF + + + ANGLE_ADJ + No description available + 0 + 32 + read-write + + + + + pos_threshold + pos_threshold + 0x238 + 32 + 0x80000000 + 0xFFFFFFFF + + + POS_THRESHOLD + No description available + 0 + 32 + read-write + + + + + 6 + 0x4 + uvw_pos0,uvw_pos1,uvw_pos2,uvw_pos3,uvw_pos4,uvw_pos5 + UVW_POS[%s] + no description available + 0x240 + 32 + 0x00000000 + 0xFFFFFFFF + + + UVW_POS0 + No description available + 0 + 32 + read-write + + + + + 6 + 0x4 + uvw_pos0_cfg,uvw_pos1_cfg,uvw_pos2_cfg,uvw_pos3_cfg,uvw_pos4_cfg,uvw_pos5_cfg + UVW_POS_CFG[%s] + no description available + 0x258 + 32 + 0x00000000 + 0x0000007F + + + POS_EN + No description available + 6 + 1 + read-write + + + U_POS_SEL + No description available + 4 + 2 + read-write + + + V_POS_SEL + No description available + 2 + 2 + read-write + + + W_POS_SEL + No description available + 0 + 2 + read-write + + + + + phase_cnt + phase_cnt + 0x280 + 32 + 0x00000000 + 0xFFFFFFFF + + + PHASE_CNT + No description available + 0 + 32 + read-write + + + + + phase_update + phase_update + 0x284 + 32 + 0x00000000 + 0xFFFFFFFF + + + INC + set to add value to phase_cnt + 31 + 1 + write-only + + + DEC + set to minus value from phase_cnt(set inc and dec same time willl act inc) + 30 + 1 + write-only + + + VALUE + value to be added or minus from phase_cnt. only valid when inc or dec is set in one 32bit write operation + 0 + 30 + write-only + + + + + position + position + 0x288 + 32 + 0x00000000 + 0xFFFFFFFF + + + POSITION + No description available + 0 + 32 + read-write + + + + + position_update + position_update + 0x28c + 32 + 0x00000000 + 0xFFFFFFFF + + + INC + set to add value to position + 31 + 1 + write-only + + + DEC + set to minus value from position(set inc and dec same time willl act inc) + 30 + 1 + write-only + + + VALUE + value to be added or minus from position. only valid when inc or dec is set in one 32bit write operation + 0 + 30 + write-only + + + + + angle + No description available + 0x290 + 32 + 0x00000000 + 0xFFFFFFFF + + + ANGLE + No description available + 0 + 32 + read-only + + + + + pos_timeout + pos_timeout + 0x294 + 32 + 0x7FFFFFFF + 0xFFFFFFFF + + + ENABLE + enable position timeout feature, if timeout, send valid again + 31 + 1 + read-write + + + TIMEOUT + postion timeout value + 0 + 31 + read-write + + + + + + + QEI1 + QEI1 + QEIV2 + 0xf0304000 + + + QEO0 + QEO0 + QEO + 0xf0308000 + + 0x0 + 0x114 + registers + + + + WAVE_mode + analog waves mode + 0x0 + 32 + 0x00000000 + 0xFFFFFFF3 + + + WAVE2_ABOVE_MAX_LIMIT + wave2 above max limit mode. +0: output 0xffff. +1: output 0x0. +2: output as level_max_limit2.level0_max_limit + 30 + 2 + read-write + + + WAVE2_HIGH_AREA1_LIMIT + wave2 high area1 limit mode. +0: output 0xffff. +1: output as level_max_limit2.level0_max_limit + 29 + 1 + read-write + + + WAVE2_HIGH_AREA0_LIMIT + wave2 high area0 limit mode. +0: output 0xffff. +1: output as level_max_limit2.level0_max_limit + 28 + 1 + read-write + + + WAVE2_LOW_AREA1_LIMIT + wave2 low area1 limit mode. +0: output 0. +1: output as level_min_limit2.level1_min_limit + 27 + 1 + read-write + + + WAVE2_LOW_AREA0_LIMIT + wave2 low area0 limit mode. +0: output 0. +1: output as level_min_limit2.level1_min_limit + 26 + 1 + read-write + + + WAVE2_BELOW_MIN_LIMIT + wave2 below min limit mode. +0: output 0. +1: output 0xffff. +2: output as level_min_limit2.level1_min_limit + 24 + 2 + read-write + + + WAVE1_ABOVE_MAX_LIMIT + wave1 above max limit mode. +0: output 0xffff. +1: output 0x0. +2: output as level_max_limit1.level0_max_limit + 22 + 2 + read-write + + + WAVE1_HIGH_AREA1_LIMIT + wave1 high area1 limit mode. +0: output 0xffff. +1: output as level_max_limit1.level0_max_limit + 21 + 1 + read-write + + + WAVE1_HIGH_AREA0_LIMIT + wave1 high area0 limit mode. +0: output 0xffff. +1: output as level_max_limit1.level0_max_limit + 20 + 1 + read-write + + + WAVE1_LOW_AREA1_LIMIT + wave1 low area1 limit mode. +0: output 0. +1: output as level_min_limit1.level1_min_limit + 19 + 1 + read-write + + + WAVE1_LOW_AREA0_LIMIT + wave1 low area0 limit mode. +0: output 0. +1: output as level_min_limit1.level1_min_limit + 18 + 1 + read-write + + + WAVE1_BELOW_MIN_LIMIT + wave1 below min limit mode. +0: output 0. +1: output 0xffff. +2: output as level_min_limit1.level1_min_limit + 16 + 2 + read-write + + + WAVE0_ABOVE_MAX_LIMIT + wave0 above max limit mode. +0: output 0xffff. +1: output 0x0. +2: output as level_max_limit0.level0_max_limit + 14 + 2 + read-write + + + WAVE0_HIGH_AREA1_LIMIT + wave0 high area1 limit mode. +0: output 0xffff. +1: output as level_max_limit0.level0_max_limit + 13 + 1 + read-write + + + WAVE0_HIGH_AREA0_LIMIT + wave0 high area0 limit mode. +0: output 0xffff. +1: output as level_max_limit0.level0_max_limit + 12 + 1 + read-write + + + WAVE0_LOW_AREA1_LIMIT + wave0 low area1 limit mode. +0: output 0. +1: output as level_min_limit0.level1_min_limit + 11 + 1 + read-write + + + WAVE0_LOW_AREA0_LIMIT + wave0 low area0 limit mode. +0: output 0. +1: output as level_min_limit0.level1_min_limit + 10 + 1 + read-write + + + WAVE0_BELOW_MIN_LIMIT + wave0 below min limit mode. +0: output 0. +1: output 0xffff. +2: output as level_min_limit0.level1_min_limit + 8 + 2 + read-write + + + SADDLE_TYPE + saddle type seclect; +0:standard saddle. +1: triple-cos saddle. + 7 + 1 + read-write + + + EN_WAVE2_VD_VQ_INJECT + wave2 VdVq inject enable. +0: disable VdVq inject. +1: enable VdVq inject. + 6 + 1 + read-write + + + EN_WAVE1_VD_VQ_INJECT + wave1 VdVq inject enable. +0: disable VdVq inject. +1: enable VdVq inject. + 5 + 1 + read-write + + + EN_WAVE0_VD_VQ_INJECT + wave0 VdVq inject enable. +0: disable VdVq inject. +1: enable VdVq inject. + 4 + 1 + read-write + + + WAVES_OUTPUT_TYPE + wave0/1/2 output mode. +0: cosine wave. +1: saddle wave. +2. abs cosine wave. +3. saw wave + 0 + 2 + read-write + + + + + WAVE_resolution + resolution of wave0/1/2 + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINES + wave0/1/2 resolution + 0 + 32 + read-write + + + + + 3 + 0x4 + wave0,wave1,wave2 + WAVE_PHASE_SHIFT[%s] + no description available + 0x8 + 32 + 0x00000000 + 0x0000FFFF + + + VAL + wave0 phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^16) period + 0 + 16 + read-write + + + + + 3 + 0x4 + wave0,wave1,wave2 + WAVE_VD_VQ_INJECT[%s] + no description available + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + VQ_VAL + Vq inject value + 16 + 16 + read-write + + + VD_VAL + Vd inject value + 0 + 16 + read-write + + + + + WAVE_vd_vq_load + load wave0/1/2 vd vq value + 0x20 + 32 + 0x00000000 + 0x00000001 + + + LOAD + load wave0/1/2 vd vq value. always read 0 +0: vd vq keep previous value. +1: load wave0/1/2 vd vq value at sametime. + 0 + 1 + write-only + + + + + 3 + 0x4 + wave0,wave1,wave2 + WAVE_AMPLITUDE[%s] + no description available + 0x24 + 32 + 0x00000000 + 0x0001FFFF + + + EN_SCAL + enable wave amplitude scaling. 0: disable; 1: enable + 16 + 1 + read-write + + + AMP_VAL + amplitude scaling value. bit15-12 are integer part value. bit11-0 are fraction value. + 0 + 16 + read-write + + + + + 3 + 0x4 + wave0,wave1,wave2 + WAVE_MID_POINT[%s] + no description available + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + wave0 output middle point, use this value as 32 bit signed value. bit 31 is signed bit. bit30-27 is integer part value. bit26-0 is fraction value. + 0 + 32 + read-write + + + + + 3 + 0x8 + wave0,wave1,wave2 + WAVE_LIMIT[%s] + no description available + 0x3c + + min + wave0 low area limit value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + LIMIT1 + low area limit level1 + 16 + 16 + read-write + + + LIMIT0 + low area limit level0 + 0 + 16 + read-write + + + + + max + wave0 high area limit value + 0x4 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + LIMIT1 + high area limit level1 + 16 + 16 + read-write + + + LIMIT0 + high area limit level0 + 0 + 16 + read-write + + + + + + 3 + 0x4 + wave0,wave1,wave2 + WAVE_DEADZONE_SHIFT[%s] + no description available + 0x54 + 32 + 0x00000000 + 0x0000FFFF + + + VAL + wave0 deadzone shifter value + 0 + 16 + read-write + + + + + ABZ_mode + wave_a/b/z output mode + 0x60 + 32 + 0x00000000 + 0x11111333 + + + REVERSE_EDGE_TYPE + pulse reverse wave，reverse edge point: +0: between pulse's posedge and negedge, min period dedicated by the num line_width +1: edge change point flow pulse's negedge. + 28 + 1 + read-write + + + EN_WDOG + enable abz wdog: +0: disable abz wdog. +1: enable abz wdog. + 24 + 1 + read-write + + + Z_POLARITY + wave_z polarity. +0: normal output. +1: invert normal output + 20 + 1 + read-write + + + B_POLARITY + wave_b polarity. +0: normal output. +1: invert normal output + 16 + 1 + read-write + + + A_POLARITY + wave_a polarity. +0: normal output. +1: invert normal output + 12 + 1 + read-write + + + Z_TYPE + wave_z type: +0: zero pulse and output high at both wave_a and wave_b are high. mantain about 25% period. +1: zero pulse output high about 75% period. start from 0 to 75% period. +2: zero pulse output high about 100% period. +3: wave_z output as tree-phase wave same as wave_a/wave_b + 8 + 2 + read-write + + + B_TYPE + wave_b type: +0: Two-phase orthogonality wave_b. +1: reverse wave of pulse/reverse type. +2: down wave of up/down type. +3: Three-phase orthogonality wave_b. + 4 + 2 + read-write + + + A_TYPE + wave_a type: +0: Two-phase orthogonality wave_a. +1: pulse wave of pulse/reverse type. +2: up wave of up/down type. +3: Three-phase orthogonality wave_a. + 0 + 2 + read-write + + + + + ABZ_resolution + resolution of wave_a/b/z + 0x64 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINES + wave_a/b/z resolution + 0 + 32 + read-write + + + + + 3 + 0x4 + a,b,z + ABZ_PHASE_SHIFT[%s] + no description available + 0x68 + 32 + 0x00000000 + 0x0000FFFF + + + VAL + wave_a phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^16) period. + 0 + 16 + read-write + + + + + ABZ_line_width + Two-phase orthogonality wave 1/4 period + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINE + the num of system clk by 1/4 period when using as Two-phase orthogonality. + 0 + 32 + read-write + + + + + ABZ_wdog_width + wdog width of qeo + 0x78 + 32 + 0x00000000 + 0xFFFFFFFF + + + WIDTH + wave will step 1/4 line to reminder user QEO still in controlled if QEO has no any toggle after the num of wdog_width sys clk. + 0 + 32 + read-write + + + + + ABZ_postion_sync + sync abz owned postion + 0x7c + 32 + 0x00000000 + 0x00000001 + + + POSTION + load next valid postion into abz owned postion. always read 0 +0: sync abz owned postion with next valid postion. +1: not sync. + 0 + 1 + write-only + + + + + PWM_mode + pwm mode + 0x80 + 32 + 0x00000000 + 0xFFFF031F + + + PWM7_SAFETY + PWM safety mode phase table + 30 + 2 + read-write + + + PWM6_SAFETY + PWM safety mode phase table + 28 + 2 + read-write + + + PWM5_SAFETY + PWM safety mode phase table + 26 + 2 + read-write + + + PWM4_SAFETY + PWM safety mode phase table + 24 + 2 + read-write + + + PWM3_SAFETY + PWM safety mode phase table + 22 + 2 + read-write + + + PWM2_SAFETY + PWM safety mode phase table + 20 + 2 + read-write + + + PWM1_SAFETY + PWM safety mode phase table + 18 + 2 + read-write + + + PWM0_SAFETY + PWM safety mode phase table + 16 + 2 + read-write + + + PWM_ENTER_SAFETY_MODE + PWM enter safety mode +0: not enter +1: enter + 9 + 1 + read-write + + + PWM_SAFETY_BYPASS + PWM safety mode bypass +0: not bypass +1: bypass + 8 + 1 + read-write + + + REVISE_UP_DN + exchange PWM pairs’ output +0: not exchange. +1: exchange. + 4 + 1 + read-write + + + PHASE_NUM + pwm force phase number. + 0 + 4 + read-write + + + + + PWM_resolution + resolution of pwm + 0x84 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINES + pwm resolution + 0 + 32 + read-write + + + + + 4 + 0x4 + a,b,c,d + PWM_PHASE_SHIFT[%s] + no description available + 0x88 + 32 + 0x00000000 + 0x0000FFFF + + + VAL + pwm_a phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^16) period + 0 + 16 + read-write + + + + + 24 + 0x4 + posedge0,posedge1,posedge2,posedge3,posedge4,posedge5,posedge6,posedge7,posedge8,posedge9,posedge10,posedge11,negedge0,negedge1,negedge2,negedge3,negedge4,negedge5,negedge6,negedge7,negedge8,negedge9,negedge10,negedge11 + PWM_PHASE_TABLE[%s] + no description available + 0x98 + 32 + 0x00000000 + 0x0000FFFF + + + PWM7 + pwm phase table value + 14 + 2 + read-write + + + PWM6 + pwm phase table value + 12 + 2 + read-write + + + PWM5 + pwm phase table value + 10 + 2 + read-write + + + PWM4 + pwm phase table value + 8 + 2 + read-write + + + PWM3 + pwm phase table value + 6 + 2 + read-write + + + PWM2 + pwm phase table value + 4 + 2 + read-write + + + PWM1 + pwm phase table value + 2 + 2 + read-write + + + PWM0 + pwm phase table value + 0 + 2 + read-write + + + + + PWM_postion_software + softwave inject postion + 0xf8 + 32 + 0x00000000 + 0xFFFFFFFF + + + POSTION_SOFTWAVE + softwave inject postion + 0 + 32 + read-write + + + + + PWM_postion_sel + select softwave inject postion + 0xfc + 32 + 0x00000000 + 0x00000001 + + + POSTION_SEL + enable softwave inject postion. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + PWM_status + qeo status + 0x100 + 32 + 0x00000000 + 0xFFFF0001 + + + PWM_FOURCE + qeo_pwm_force observe + 16 + 16 + read-only + + + PWM_SAFETY + pwm_fault status + 0 + 1 + read-only + + + + + PWM_debug0 + qeo debug 0 + 0x104 + 32 + 0x00000000 + 0xFFFFFFFF + + + WAVE1 + wave1 observe + 16 + 16 + read-only + + + WAVE0 + wave0 observe + 0 + 16 + read-only + + + + + PWM_debug1 + qeo debug 1 + 0x108 + 32 + 0x00000000 + 0x1111FFFF + + + QEO_FINISH + qeo finish observe + 28 + 1 + read-only + + + WAVE_Z + wave_z observe + 24 + 1 + read-only + + + WAVE_B + wave_b observe + 20 + 1 + read-only + + + WAVE_A + wave_a observe + 16 + 1 + read-only + + + WAVE2 + wave2 observe + 0 + 16 + read-only + + + + + PWM_debug2 + qeo debug 2 + 0x10c + 32 + 0x00000000 + 0xFFFFFFFF + + + ABZ_OWN_POSTION + abz_own_postion observe + 0 + 32 + read-only + + + + + PWM_debug3 + qeo debug 3 + 0x110 + 32 + 0x00000000 + 0xFFFFFFFF + + + ABZ_OWN_POSTION + abz_own_postion observe + 0 + 32 + read-only + + + + + + + QEO1 + QEO1 + QEO + 0xf030c000 + + + MMC0 + MMC0 + MMC + 0xf0310000 + + 0x0 + 0x334 + registers + + + + CR + Control Register + 0x0 + 32 + 0x00000000 + 0xBFFFFFFF + + + SFTRST + Software reset, high active. When write 1 ,all internal logical will be reset. +0b - No action +1b - All MMC internal registers are forced into their reset state. Interface registers are not affected. + 31 + 1 + read-write + + + INI_BR0_POS_REQ + Auto clear. Only effective in open_loop mode. + 29 + 1 + read-write + + + INI_BR1_POS_REQ + Auto clear. Only effective in open_loop mode. + 28 + 1 + read-write + + + FRCACCELZERO + Zeroise the accelerator calculation. + 27 + 1 + read-write + + + MS_COEF_EN + Multiple Coefficients Enable + 26 + 1 + read-write + + + INI_DELTA_POS_TRG_TYPE + 0: Time Stamp in the configuration +1: Risedge of In Trg[0] +2: Risedge of In Trg[1] +3: Risedge of out trg[0] +4: Risedge of out trg[1] +5: triggered by self position trigger +6: triggered by self speed trigger +Otherser: no function + 23 + 3 + read-write + + + INI_POS_TRG_TYPE + 0: Time Stamp in the configuration +1: Risedge of In Trg[0] +2: Risedge of In Trg[1] +3: Risedge of out trg[0] +4: Risedge of out trg[1] +5: triggered by self position trigger +6: triggered by self speed trigger +Otherser: no function + 20 + 3 + read-write + + + INI_DELTA_POS_CMD_MSK + 1: change +0: won't change +bit 3: for delta accel +bit 2: for delta speed +bit 1: for delta revolution +bit 0: for delta position + 16 + 4 + read-write + + + INI_DELTA_POS_REQ + 1: Command to reload the delta pos. Auto clear +0: + 15 + 1 + read-write + + + OPEN_LOOP_MODE + 1: in open loop mode +0: not in open loop mode + 14 + 1 + read-write + + + POS_TYPE + 1: 32-bit for rev+pos, with each element occupying 16 bits +0: 32-bit for rev, and 32 bit for pos +When CR[MANUAL_IO]==1, +1: means that the INI_POS is acting as INI_POS cmds +0: means that the INI_POS is simulating the input of iposition and itimestamp + 13 + 1 + read-write + + + INI_POS_CMD_MSK + 1: change +0: won't change +bit 3: for accel +bit 2: for speed +bit 1: for revolution +bit 0: for position + 9 + 4 + read-write + + + INI_POS_REQ + 1: Command to reload the positions. Auto clear +0: + 8 + 1 + read-write + + + INI_COEFS_CMD_MSK + 1: change +0: won't change +bit 2: for ACOEF +bit 1: for ICOEF +bit 0: for PCOEF + 5 + 3 + read-write + + + INI_COEFS_CMD + 1: Command to reload the coefs. Auto clear +0: + 4 + 1 + read-write + + + SHADOW_RD_REQ + 1: Shadow Request for read of tracking parameters. Auto clear +0: + 3 + 1 + read-write + + + ADJOP + 1: use the input iposition whenever a new iposition comes, and force the predicted output stop at the boundaries. +0: Continuous tracking mode, without any boundary check + 2 + 1 + read-write + + + DISCRETETRC + 1: Discrete position input +0: Continuous position input + 1 + 1 + read-write + + + MOD_EN + Module Enable + 0 + 1 + read-write + + + + + STA + Status Register + 0x4 + 32 + 0x00000020 + 0xF00007F7 + + + ERR_ID + Tracking ERR_ID + 28 + 4 + read-only + + + SPEED_TRG_VALID + W1C + 10 + 1 + write-only + + + POS_TRG_VALID + W1C + 9 + 1 + write-only + + + INI_DELTA_POS_REQ_CMD_DONE + W1C + 8 + 1 + write-only + + + INI_BR0_POS_REQ_CMD_DONE + W1C + 7 + 1 + write-only + + + INI_BR1_POS_REQ_CMD_DONE + W1C + 6 + 1 + write-only + + + IDLE + Tracking Module in Idle status + 5 + 1 + read-only + + + OOSYNC + Tracking module out-of sync. W1C + 4 + 1 + write-only + + + INI_POS_REQ_CMD_DONE + W1C + 2 + 1 + write-only + + + INI_COEFS_CMD_DONE + W1C + 1 + 1 + write-only + + + SHADOW_RD_DONE + Shadow ready for read. Auto cleared by setting CR[SHADOW_RD_REQ] as 1 + 0 + 1 + read-only + + + + + INT_EN + Interrupt Enable Register + 0x8 + 32 + 0x00000000 + 0x000007D7 + + + SPEED_TRG_VLD_IE + Interrupt Enable for SPEED_TRG_VALID + 10 + 1 + read-write + + + POS_TRG_VLD_IE + Interrupt Enable for POS_TRG_VALID + 9 + 1 + read-write + + + INI_DELTA_POS_REQ_CMD_DONE_IE + Interrupt Enable for INI_DELTA_POS_REQ_CMD_DONE + 8 + 1 + read-write + + + INI_BR0_POS_REQ_CMD_DONE_IE + Interrupt Enable for INI_BR0_POS_REQ_CMD_DONE + 7 + 1 + read-write + + + INI_BR1_POS_REQ_CMD_DONE_IE + Interrupt Enable for INI_BR1_POS_REQ_CMD_DONE + 6 + 1 + read-write + + + OOSYNC_IE + Interrupt Enable for OOSYNC + 4 + 1 + read-write + + + INI_POS_REQ_CMD_DONE_IE + Interrupt Enable for INI_POS_REQ_CMD_DONE + 2 + 1 + read-write + + + INI_COEFS_CMD_DONE_IE + Interrupt Enable for INI_COEFS_CMD_DONE + 1 + 1 + read-write + + + SHADOW_RD_DONE_IE + Interrupt Enable for SHADOW_RD_DONE + 0 + 1 + read-write + + + + + SYSCLK_FREQ + System Clock Frequency Register + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + system clock frequency, ufix<32, 0> + 0 + 32 + read-write + + + + + SYSCLK_PERIOD + System Clock Period Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + round( the value of clock period * (2^24)*(2^20) ), ufix<32, 0> + 0 + 32 + read-write + + + + + OOSYNC_THETA_THR + Position Out-Of-Sync Threshold Regster + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the threshold of theta difference between actual and prediction for out-of-sync determination，ufix<32, 32> + 0 + 32 + read-write + + + + + DiscreteCfg0 + Discrete Mode Configuration 0 Register + 0x18 + 32 + 0x00000000 + 0x000FFFFF + + + POSMAX + Max ID Of Lines. For example-1, for 512 lines, it is 511. ufix<32, 0> + 0 + 20 + read-write + + + + + DiscreteCfg1 + Discrete Mode Configuration 1 Register + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + INV_POSMAX + discrete mode: ufix<32, 0> of 1/(Number Of Lines) +continuous mode: the max delta for tracking from the last received position, ufix<32, 32> + 0 + 32 + read-write + + + + + ContCfg0 + Continuous Mode Configuration 0 Register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + HALF_CIRC_THETA + the theta for cal the clockwise or anticlockwise rotation between two adjacent inputs, ufix<32, 32> + 0 + 32 + read-write + + + + + INI_POS_TIME + The destined timestamp register for position initialization + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + indicate the time to change the values. +0: instant change + 0 + 32 + read-write + + + + + INI_POS + The destined position register for position initialization + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value； +continuous mode: ufix<32, 32> + 0 + 32 + read-write + + + + + INI_REV + The destined revolution register for position initialization + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value； +continuous mode: ufix<32, 0> + 0 + 32 + read-write + + + + + INI_SPEED + The destined speed register for position initialization + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value; +continuous mode: fix<32, 19> + 0 + 32 + read-write + + + + + INI_ACCEL + The destined accelerator register for position initialization + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value +continuous mode: fix<32, 19> + 0 + 32 + read-write + + + + + INI_COEF_TIME + The destined timestamp register for coefficients initialization + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + indicate the time to change the values. +0: instant change + 0 + 32 + read-write + + + + + INI_PCOEF + The destined coefficient P register for coefficients initialization + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value, fix<32, 15> + 0 + 32 + read-write + + + + + INI_ICOEF + The destined coefficient I register for coefficients initialization + 0x40 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value, fix<32, 21> + 0 + 32 + read-write + + + + + INI_ACOEF + The destined coefficient A register for coefficients initialization + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value, fix<32, 19> + 0 + 32 + read-write + + + + + ESTM_TIM + The timestamp register for internal estimation + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + ESTM_POS + The position register for the internal estimation + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + ESTM_REV + The revolution register for the internal estimation + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + ESTM_SPEED + The speed register for the internal estimation + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + ESTM_ACCEL + The accelerator register for theinternal estimation + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + CUR_PCOEF + The coefficient P register for the internal estimation + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + CUR_ICOEF + The coefficient I register for the internal estimation + 0x60 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + CUR_ACOEF + The coefficient A register for the internal estimation + 0x64 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + INI_DELTA_POS_TIME + The destined timestamp register for delta position initialization + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + indicate the time to change the values. +0: instant change + 0 + 32 + read-write + + + + + INI_DELTA_POS + The destined delta position register for delta position initialization + 0x6c + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value +continuous mode: ufix <32, 32> + 0 + 32 + read-write + + + + + INI_DELTA_REV + The destined delta revolution register for delta position initialization + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value +continuous mode: fix<32, 0> + 0 + 32 + read-write + + + + + INI_DELTA_SPEED + The destined delta speed register for delta position initialization + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value； +continuous mode: fix<32, 19> + 0 + 32 + read-write + + + + + INI_DELTA_ACCEL + The destined delta accelerator register for delta position initialization + 0x78 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value +continuous mode: fix<32, 19> + 0 + 32 + read-write + + + + + pos_trg_cfg + Tracking Configuration pos trigger cfg + 0x80 + 32 + 0x00000000 + 0x00000003 + + + EDGE + 0: (rising edge) pos inc greater than, 1: (falling edge) pos dec less than + 1 + 1 + read-write + + + EN + 1-trigger valid; 0-Trigger not valid" + 0 + 1 + read-write + + + + + pos_trg_pos_thr + Tracking Configuration position threshold + 0x84 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + For pos out trigger (pos). +ufix<32, 32> + 0 + 32 + read-write + + + + + pos_trg_rev_thr + Tracking Configuration revolution threshold + 0x88 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + For pos out trigger (rev) +fix<32, 0> + 0 + 32 + read-write + + + + + speed_trg_cfg + Tracking Configuration speed trigger cfg + 0x8c + 32 + 0x00000000 + 0x00000007 + + + COMP_TYPE + 1: Use abs value for comparion. 0: Use the speed with direction info (so not the abs value) + 2 + 1 + read-write + + + EDGE + 0: (rising edge) speed inc greater than, 1: (falling edge) speed dec less than + 1 + 1 + read-write + + + EN + 1-trigger valid; 0-Trigger not valid +Normally it means either the max pos speed, or the min negative speed. + 0 + 1 + read-write + + + + + speed_trg_thr + Tracking Configuration speed threshold + 0x90 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + For speed trigger. +continuous mode: fix<32, 19> + 0 + 32 + read-write + + + + + 3 + 0x14 + 0,1,2 + COEF_TRG_CFG[%s] + no description available + 0xa0 + + err_thr + Tracking Configuration coef trigger cfg&index0 + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + ErrThr0: Error Threshold 0, (abs(tracking error)>= will choose the coefs as below) +Note: ErrThr0>ErrThr1>ErrThr2 +ufix<31, 28> + 0 + 32 + read-write + + + + + P + Tracking Configuration coef trigger cfg&index0 P + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + P0_Coef, fix<32, 15> + 0 + 32 + read-write + + + + + I + Tracking Configuration coef trigger cfg&index0 I + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + I0_Coef, fix<32, 21> + 0 + 32 + read-write + + + + + A + Tracking Configuration coef trigger cfg&index0 A + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + A0_Coef，fix<32, 19> + 0 + 32 + read-write + + + + + TIME + Tracking Configuration coef trigger cfg&index0 time + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + CoefTime0: Time Stayed using this coefs (counted in input samples). Ideal value of tracing cycles should +1. ufix<32,0> + 0 + 32 + read-write + + + + + + 2 + 0x100 + 0,1 + BR[%s] + no description available + 0x100 + + BR_CTRL + Prediction Control Register + 0x0 + 32 + 0x00000000 + 0x63BDFFB7 + + + SPEED_TRG_VALID_IE + Interrupt Enable for SPEED_TRG_VALID + 30 + 1 + read-write + + + POS_TRG_VALID_IE + Interrupt Enable for POS_TRG_VALID + 29 + 1 + read-write + + + INI_POS_TRG_TYPE + 0: Time Stamp in the configuration +1: Risedge of In Trg[0] +2: Risedge of In Trg[1] +3: Risedge of out trg[0] +4: Risedge of out trg[1] +5: Risedge of self pos trigger +6: Risedge of self speed trigger +Others: no function + 23 + 3 + read-write + + + INI_POS_CMD_MSK + 1: change +0: won't change +bit 3: for accel +bit 2: for speed +bit 1: for revolution +bit 0: for position + 18 + 4 + read-write + + + INI_DELTA_POS_TRG_TYPE + 0: Time Stamp in the configuration +1: Risedge of In Trg[0] +2: Risedge of In Trg[1] +3: Risedge of out trg[0] +4: Risedge of out trg[1] +5: Risedge of self pos trigger +6: Risedge of self speed trigger +Others: no function + 14 + 3 + read-write + + + INI_DELTA_POS_DONE_IE + Interrupt Enable for INI_DELTA_POS_DONE + 13 + 1 + read-write + + + INI_DELTA_POS_CMD_MSK + 1: change +0: won't change +bit 3: for delta accel +bit 2: for delta speed +bit 1: for delta revolution +bit 0: for delta position + 9 + 4 + read-write + + + INI_DELTA_POS_REQ + 1: Command to reload the delta pos. Auto clear +0: + 8 + 1 + read-write + + + OPEN_LOOP_MODE + 1: in open loop mode +0: not in open loop mode + 7 + 1 + read-write + + + PRED_MODE + 1:continuously repeat pred, +0:cal the pred based on a definite time-stamp offset, +2:programed one-shot prediction mode + 4 + 2 + read-write + + + NF_TRG_TYPE + 1. Each non-first trigger by external trigger pin +0. Each non-first trigger by the timer + 2 + 1 + read-write + + + F_TRG_TYPE + 1. First trigger by external trigger pin +0. First trigger by the timer +When in CR[MANUAL_IO]=1 mode, it is the prediction trigger + 1 + 1 + read-write + + + BR_EN + Branch Enable + 0 + 1 + read-write + + + + + BR_TIMEOFF + Prediction Timing Offset Register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + ufix<32, 0> time offset incycles from the trigger time + 0 + 32 + read-write + + + + + BR_TRG_PERIOD + Prediction Triggering Period Offset Register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + uifx<32, 0>, time offset incycles between each trigger time + 0 + 32 + read-write + + + + + BR_TRG_F_TIME + Prediction Triggering First Offset Register + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + uifx<32, 0> the time for the first trigger + 0 + 32 + read-write + + + + + BR_ST + Prediction Status Register + 0x10 + 32 + 0x00000000 + 0x0000076F + + + OPEN_LOOP_ST + 1：in open loop mode +0：in closed loop mode + 10 + 1 + read-only + + + SPEED_TRG_VLD + 1：self speed trigger event found +0：self speed trigger event not found yet + 9 + 1 + write-only + + + POS_TRG_VLD + 1：self position trigger event found +0：self position trigger event not found yet + 8 + 1 + write-only + + + INI_DELTA_POS_DONE + 1: the initialization of delta position command is done +0: the initialization of delta position command is not done + 6 + 1 + write-only + + + IDLE + 1: The prediction module is idle. +0: The prediction module is not idle. + 5 + 1 + read-only + + + ERR_ID + The module's error ID output + 0 + 4 + read-only + + + + + BR_TRG_pos_cfg + Prediction Configuration postion trigger cfg + 0x40 + 32 + 0x00000000 + 0x00000003 + + + EDGE + bit1: 0: (rising edge) pos inc greater than, 1: (falling edge) pos dec less than + 1 + 1 + read-write + + + EN + 1-trigger valid; 0-Trigger not valid + 0 + 1 + read-write + + + + + BR_TRG_pos_thr + Prediction Configuration postion threshold + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + For pos out trigger (pos). +ufix<32, 32> + 0 + 32 + read-write + + + + + BR_TRG_rev_thr + Prediction Configuration revolutiom threshold + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + For pos out trigger (rev) +ufix<32, 0> + 0 + 32 + read-write + + + + + BR_TRG_speed_cfg + Prediction Configuration speed trigger cfg + 0x4c + 32 + 0x00000000 + 0x00000007 + + + COMP_TYPE + Use abs value for comparion. 0: Use the speed with direction info (so not the abs value) + 2 + 1 + read-write + + + EDGE_SEL + 0: (rising edge) speed inc greater than, 1: (falling edge) speed dec less than + 1 + 1 + read-write + + + EN + 1-trigger valid; 0-Trigger not valid +Normally it means either the max pos speed, or the min negative speed. + 0 + 1 + read-write + + + + + BR_TRG_speed_thr + Prediction Configuration speed threshold + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + For speed trigger. +continuous mode: fix<32, 19> + 0 + 32 + read-write + + + + + BR_INI_POS_TIME + Initialization timestamp for open-loop mode + 0xc0 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + indicate the time to change the values. +0: instant change + 0 + 32 + read-write + + + + + BR_INI_POS + Initialization position for open-loop mode + 0xc4 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value +ufix<32, 32> + 0 + 32 + read-write + + + + + BR_INI_REV + Initialization revolution for open-loop mode + 0xc8 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value +ufix<32, 0> + 0 + 32 + read-write + + + + + BR_INI_SPEED + Initialization speed for open-loop mode + 0xcc + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value +fix<32, 19> + 0 + 32 + read-write + + + + + BR_INI_ACCEL + Initialization acceleration for open-loop mode + 0xd0 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value +continuous mode: fix<32, 19> + 0 + 32 + read-write + + + + + BR_INI_DELTA_POS_TIME + Initialization timestamp for delta mode in prediction mode + 0xd4 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + indicate the time to change the values. +0: instant change + 0 + 32 + read-write + + + + + BR_INI_DELTA_POS + Initialization delta position for delta mode in prediction mode + 0xd8 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value +continuous mode: ufix<32, 32> + 0 + 32 + read-write + + + + + BR_INI_DELTA_REV + Initialization delta revolution for delta mode in prediction mode + 0xdc + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value +continuous mode: fix<32, 0> + 0 + 32 + read-write + + + + + BR_INI_DELTA_SPEED + Initialization delta speed for delta mode in prediction mode + 0xe0 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value +continuous mode: fix<32, 19> + 0 + 32 + read-write + + + + + BR_INI_DELTA_ACCEL + Initialization delta acceleration for delta mode in prediction mode + 0xe4 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value +continuous mode: fix<32, 19> + 0 + 32 + read-write + + + + + BR_CUR_POS_TIME + Monitor of the output timestamp + 0xec + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + BR_CUR_POS + Monitor of the output position + 0xf0 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + BR_CUR_REV + Monitor of the output revolution + 0xf4 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + BR_CUR_SPEED + Monitor of the output speed + 0xf8 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + BR_CUR_ACCEL + Monitor of the output acceleration + 0xfc + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + + BK0_TIMESTAMP + Monitor of the just received input timestamp for tracing logic + 0x300 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + BK0_POSITION + Monitor of the just received input position for tracing logic + 0x304 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + BK0_REVOLUTION + Monitor of the just received input revolution for tracing logic + 0x308 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + BK0_SPEED + Monitor of the just received input speed for tracing logic + 0x30c + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + BK0_ACCELERATOR + Monitor of the just received input acceleration for tracing logic + 0x310 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + BK1_TIMESTAMP + Monitor of the previous received input timestamp for tracing logic + 0x320 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + BK1_POSITION + Monitor of the previous received input position for tracing logic + 0x324 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + BK1_REVOLUTION + Monitor of the previous received input revolution for tracing logic + 0x328 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + BK1_SPEED + Monitor of the previous received input speed for tracing logic + 0x32c + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + BK1_ACCELERATOR + Monitor of the previous received input acceleration for tracing logic + 0x330 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + + + MMC1 + MMC1 + MMC + 0xf0314000 + + + PWM0 + PWM0 + PWM + 0xf0318000 + + 0x0 + 0x290 + registers + + + + unlk + Shadow registers unlock register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHUNLK + write 0xB0382607 to unlock the shadow registers of register offset from 0x04 to 0x78, +otherwise the shadow registers can not be written. + 0 + 32 + read-write + + + + + sta + Counter start register + UNION_STA + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + XSTA + pwm timer counter extended start point, should back to this value after reach xrld + 28 + 4 + read-write + + + STA + pwm timer counter start value + sta/rld will be loaded from shadow register to work register at main counter reload time, or software write unlk.shunlk + 4 + 24 + read-write + + + + + rld + Counter reload register + UNION_RLD + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + XRLD + timeout counter extended reload point, counter will reload to xsta after reach this point + 28 + 4 + read-write + + + RLD + pwm timer counter reload value + 4 + 24 + read-write + + + + + 24 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 + CMP[%s] + no description available + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, +and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + frcmd + Force output mode register + 0x78 + 32 + 0x00000000 + 0x0000FFFF + + + FRCMD + 2bit for each PWM output channel (0-7); +00: force output 0 +01: force output 1 +10: output highz +11: no force + 0 + 16 + read-write + + + + + shlk + Shadow registers lock register + 0x7c + 32 + 0x00000000 + 0x80000000 + + + SHLK + write 1 to lock all shawdow register, write access is not permitted + 31 + 1 + read-write + + + + + 24 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 + CHCFG[%s] + no description available + 0x80 + 32 + 0x00000000 + 0xFFFF0003 + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + + + gcr + Global control register + 0xf0 + 32 + 0x00000000 + 0xFDFFFFEF + + + FAULTI3EN + 1- enable the internal fault input 3 + 31 + 1 + read-write + + + FAULTI2EN + 1- enable the internal fault input 2 + 30 + 1 + read-write + + + FAULTI1EN + 1- enable the internal fault input 1 + 29 + 1 + read-write + + + FAULTI0EN + 1- enable the internal fault input 0 + 28 + 1 + read-write + + + DEBUGFAULT + 1- enable debug mode output protection + 27 + 1 + read-write + + + FRCPOL + polarity of input pwm_force, +1- active low +0- active high + 26 + 1 + read-write + + + HWSHDWEDG + When hardware event is selected as shawdow register effective time and the select comparator is configured as input capture mode. +This bit assign its which edge is used as compare shadow register hardware load event. +1- Falling edge +0- Rising edge + 24 + 1 + read-write + + + CMPSHDWSEL + This bitfield select one of the comparators as hardware event time to load comparator shadow registers + 19 + 5 + read-write + + + FAULTRECEDG + When hardware load is selected as output fault recover trigger and the selected channel is capture mode. +This bit assign its effective edge of fault recover trigger. +1- Falling edge +0- Rising edge + 18 + 1 + read-write + + + FAULTRECHWSEL + Selec one of the 24 comparators as fault output recover trigger. + 13 + 5 + read-write + + + FAULTE1EN + 1- enable the external fault input 1 + 12 + 1 + read-write + + + FAULTE0EN + 1- enable the external fault input 0 + 11 + 1 + read-write + + + FAULTEXPOL + external fault polarity +1-active low +0-active high + 9 + 2 + read-write + + + RLDSYNCEN + 1- pwm timer counter reset to reload value (rld) by synci is enabled + 8 + 1 + read-write + + + CEN + 1- enable the pwm timer counter +0- stop the pwm timer counter + 7 + 1 + read-write + + + FAULTCLR + 1- Write 1 to clear the fault condition. The output will recover if FAULTRECTIME is set to 2b'11. +User should write 1 to this bit after the active FAULT signal de-assert and before it re-assert again. + 6 + 1 + read-write + + + XRLDSYNCEN + 1- pwm timer extended counter (xcnt) reset to extended reload value (xrld) by synci is enabled + 5 + 1 + read-write + + + TIMERRESET + set to clear current timer(total 28bit, main counter and tmout_count ). Auto clear + 3 + 1 + read-write + + + FRCTIME + This bit field select the force effective time +00: force immediately +01: force at main counter reload time +10: force at FRCSYNCI +11: no force + 1 + 2 + write-only + + + SWFRC + 1- write 1 to enable software force, if the frcsrcsel is set to 0, force will take effect + 0 + 1 + read-write + + + + + shcr + Shadow register control register + 0xf4 + 32 + 0x00000000 + 0x00001FFF + + + FRCSHDWSEL + This bitfield select one of the comparators as hardware event time to load FRCMD shadow registers + 8 + 5 + read-write + + + CNTSHDWSEL + This bitfield select one of the comparators as hardware event time to load the counter related shadow registers (STA and RLD) + 3 + 5 + read-write + + + CNTSHDWUPT + This bitfield select when the counter related shadow registers (STA and RLD) will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 1 + 2 + read-write + + + SHLKEN + 1- enable shadow registers lock feature, +0- disable shadow registers lock, shlk bit will always be 0 + 0 + 1 + read-write + + + + + 24 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 + CAPPOS[%s] + no description available + 0x100 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + cnt + Counter + 0x170 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCNT + current extended counter value + 28 + 4 + read-only + + + CNT + current clock counter value + 4 + 24 + read-only + + + + + 24 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 + CAPNEG[%s] + no description available + 0x180 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + cntcopy + Counter copy + 0x1f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCNT + current extended counter value + 28 + 4 + read-only + + + CNT + current clock counter value + 4 + 24 + read-only + + + + + 8 + 0x4 + 0,1,2,3,4,5,6,7 + PWMCFG[%s] + no description available + 0x200 + 32 + 0x00000000 + 0x1FFFFFFF + + + OEN + PWM output enable +1- output is enabled +0- output is disabled + 28 + 1 + read-write + + + FRCSHDWUPT + This bitfield select when the FRCMD shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 26 + 2 + read-write + + + FAULTMODE + This bitfield defines the PWM output status when fault condition happen +00: force output 0 +01: force output 1 +1x: output highz + 24 + 2 + read-write + + + FAULTRECTIME + This bitfield select when to recover PWM output after fault condition removed. +00: immediately +01: after pwm timer counter reload time +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after software write faultclr bit in GCR register + 22 + 2 + read-write + + + FRCSRCSEL + Select sources for force output +0- force output is enabled when FRCI assert +1- force output is enabled by software write swfrc to 1 + 21 + 1 + read-write + + + PAIR + 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. +0- PWM output is in indepandent mode. + 20 + 1 + read-write + + + DEADAREA + This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. +Note: user should configure pair bit and this bitfield before PWM output is enabled. + 0 + 20 + read-write + + + + + sr + Status register + 0x220 + 32 + 0x00000000 + 0x0FFFFFFF + + + FAULTF + fault condition flag + 27 + 1 + write-only + + + XRLDF + extended reload flag, this flag set when xcnt count to xrld value or when SYNCI assert + 26 + 1 + write-only + + + HALFRLDF + half reload flag, this flag set when cnt count to rld/2 + 25 + 1 + write-only + + + RLDF + reload flag, this flag set when cnt count to rld value or when SYNCI assert + 24 + 1 + write-only + + + CMPFX + comparator output compare or input capture flag + 0 + 24 + write-only + + + + + irqen + Interrupt request enable register + 0x224 + 32 + 0x00000000 + 0x0FFFFFFF + + + FAULTIRQE + fault condition interrupt enable + 27 + 1 + read-write + + + XRLDIRQE + extended reload flag interrupt enable + 26 + 1 + read-write + + + HALFRLDIRQE + half reload flag interrupt enable + 25 + 1 + read-write + + + RLDIRQE + reload flag interrupt enable + 24 + 1 + read-write + + + CMPIRQEX + comparator output compare or input capture flag interrupt enable + 0 + 24 + read-write + + + + + dmaen + DMA request enable register + 0x22c + 32 + 0x00000000 + 0x0FFFFFFF + + + FAULTEN + fault condition DMA request enable + 27 + 1 + read-write + + + XRLDEN + extended reload flag DMA request enable + 26 + 1 + read-write + + + HALFRLDEN + half reload flag DMA request enable + 25 + 1 + read-write + + + RLDEN + reload flag DMA request enable + 24 + 1 + read-write + + + CMPENX + comparator output compare or input capture flag DMA request enable + 0 + 24 + read-write + + + + + 24 + 0x4 + cmpcfg0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 + CMPCFG[%s] + no description available + 0x230 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + + + + + PWM1 + PWM1 + PWM + 0xf031c000 + + + RDC + RDC + RDC + 0xf0320000 + + 0x0 + 0xf0 + registers + + + + rdc_ctl + rdc control + 0x0 + 32 + 0x00000000 + 0x003FF077 + + + TS_SEL + Time stamp selection for accumulation +0: end of accumulation +1: start of accumulation +2: center of accumulation + 20 + 2 + read-write + + + ACC_LEN + Accumulate time, support on the fly change +0：1 cycle +1：2 cycles +… +255: 256 cycles + 12 + 8 + read-write + + + RECTIFY_SEL + Select reference point of rectify signal +0: 0 phase of internal exciting signal +1: 90 phase of internal exciting signal +2: 180 phase of internal exciting signal +3: 270 phase of internal exciting signal +4: use value on external pin +5: use invert value on external pin + 4 + 3 + read-write + + + ACC_EN + Enable rdc accumulate +0: rdc disable +1: rdc enable + 2 + 1 + read-write + + + EXC_START + Write 1 start excite signal, always read 0 +0: no effect +1: start excite signal + 1 + 1 + read-write + + + EXC_EN + Enable rdc excite signal +0: rdc disable +1: rdc enable + 0 + 1 + read-write + + + + + acc_i + accumulate result of i_channel + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + ACC + accumulate result of i_channel, this is a signed number + 0 + 32 + read-only + + + + + acc_q + accumulate result of q_channel + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + ACC + accumulate result of q_channel, this is a signed number + 0 + 32 + read-only + + + + + in_ctl + input channel selection + 0xc + 32 + 0x00000000 + 0x0011F11F + + + PORT_Q_SEL + Input port selection for q_channel, +0:sel port0 +1:sel port1 + 20 + 1 + read-write + + + CH_Q_SEL + Input channel selection for q_channel +0: channel 0 selected +1: channel 1 selected +… +31: channel 31 selected + 12 + 5 + read-write + + + PORT_I_SEL + Input port selection for i_channel, +0:sel port0 +1:sel port1 + 8 + 1 + read-write + + + CH_I_SEL + Input channel selection for i_channel +0: channel 0 selected +1: channel 1 selected +… +31: channel 31 selected + 0 + 5 + read-write + + + + + out_ctl + output channel selection + 0x10 + 32 + 0x00000000 + 0x00001F1F + + + CH_Q_SEL + Output channel selection for q_channel + 8 + 5 + read-write + + + CH_I_SEL + Output channel selection for i_channel + 0 + 5 + read-write + + + + + exc_timming + excitation signal timming setting + 0x34 + 32 + 0x000400C8 + 0x01FFFFFF + + + SWAP + Swap output of PWM and DAC +0: disable swap +1: swap output + 24 + 1 + read-write + + + PWM_PRD + Pwm period in samples， +0：1 sample period +1: 2 sample period +... +15: 16 sample period + 20 + 4 + read-write + + + SMP_NUM + Number of sample every excitation period +0: 4 point +1: 8 point +… +8: 1024 point + 16 + 4 + read-write + + + SMP_RATE + The period for excitation sample in clock cycle， +0: not allowed +1: 1 cycle +2: 2 cycles +… +65535 : 65535 cycles + 0 + 16 + read-write + + + + + exc_scaling + amplitude scaling for excitation + 0x38 + 32 + 0x00000011 + 0x000000FF + + + AMP_EXP + Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp + 4 + 4 + read-write + + + AMP_MAN + Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp + 0 + 4 + read-write + + + + + exc_offset + amplitude offset setting + 0x3c + 32 + 0x00800000 + 0x00FFFFFF + + + AMP_OFFSET + Offset for excitation + 0 + 24 + read-write + + + + + pwm_scaling + amplitude scaling for excitation + 0x40 + 32 + 0x00000111 + 0x000031FF + + + N_POL + Polarity of exc_n signal +0: high active +1: low active + 13 + 1 + read-write + + + P_POL + Polarity of exc_p signal +0: high active +1: low active + 12 + 1 + read-write + + + DITHER + Enable dither of pwm +0: disable +1: enable + 8 + 1 + read-write + + + AMP_EXP + Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp + 4 + 4 + read-write + + + AMP_MAN + Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp + 0 + 4 + read-write + + + + + pwm_offset + amplitude offset setting + 0x44 + 32 + 0x00000064 + 0x00FFFFFF + + + AMP_OFFSET + Offset for excitation + 0 + 24 + read-write + + + + + trig_out0_cfg + Configuration for trigger out 0 in clock cycle + 0x48 + 32 + 0x00100019 + 0x001FFFFF + + + ENABLE + Enable trigger out0 +0: disable +1: enable + 20 + 1 + read-write + + + LEAD_TIM + Lead time for trigger out0 from center of low level , this is a signed value +… +2: 2 cycle befor center of low level +1: 1 cycle before center of low level +0: center of low level +-1: 1cycle after center of low level +-2: 2cycle after center of low level + 0 + 20 + read-write + + + + + trig_out1_cfg + Configuration for trigger out 1 in clock cycle + 0x4c + 32 + 0x0010004B + 0x001FFFFF + + + ENABLE + Enable trigger out1 +0: disable +1: enable + 20 + 1 + read-write + + + LEAD_TIM + Lead time for trigger out0 from center of hight level , this is a signed value +… +2: 2 cycle befor center of hight level +1: 1 cycle before center of hight level +0: center of hight level +-1: 1cycle after center of hight level +-2: 2cycle after center of hight level + 0 + 20 + read-write + + + + + pwm_dz + pwm dead zone control in clock cycle + 0x50 + 32 + 0x00000000 + 0x0000FFFF + + + DZ_N + Exc_n dead zone in clock cycle before swap +0: no dead zone +1: 1 cycle dead zone +2: 2 cycle dead zone +… + 8 + 8 + read-write + + + DZ_P + Exc_p dead zone in clock cycle before swap +0: no dead zone +1: 1 cycle dead zone +2: 2 cycle dead zone +… + 0 + 8 + read-write + + + + + sync_out_ctrl + synchronize output signal control + 0x54 + 32 + 0x00000000 + 0xFFFF0033 + + + PWM_OUT_DLY + Delay bettween the delyed trigger and the first pwm pulse in clock cycle +1: 1 cycle +2: 2 cycle +… + 16 + 16 + read-only + + + MIN2TRIG_EN + Enable trigger out from the min point of exciting signal +1: enable +0: disable + 5 + 1 + read-write + + + MAX2TRIG_EN + Enable trigger out from the max point of exciting signal +1: enable +0: disable + 4 + 1 + read-write + + + SYNC_OUT_SEL + Select output synchornize signal +0: 0 phase of internal exciting signal +1: 90 phase of internal exciting signal +2: 180 phase of internal exciting signal +3: 270 phase of internal exciting signal + 0 + 2 + read-write + + + + + exc_sync_dly + trigger in delay timming in soc bus cycle + 0x58 + 32 + 0x01000001 + 0x01FFFFFF + + + DISABLE + Disable hardware trigger input +0: enable +1: disable + 24 + 1 + read-write + + + DELAY + Trigger in delay timming in bus cycle from rising edge of trigger signal +0: 1 cycle +1: 2 cycle +… +0xffffff: 2^24 cycle + 0 + 24 + read-write + + + + + max_i + max value of i_channel + 0x70 + 32 + 0x00000000 + 0xFFFFFF01 + + + MAX + Max value of i_channel, write clear + 8 + 24 + read-write + + + VALID + Max value valid, write clear +0: max value is not valid +1: max value is valid + 0 + 1 + read-write + + + + + min_i + min value of i_channel + 0x74 + 32 + 0x00000000 + 0xFFFFFF01 + + + MIN + Min value of i_channel, write clear + 8 + 24 + read-write + + + VALID + Min value valid, write clear +0: min value is not valid +1: min value is valid + 0 + 1 + read-write + + + + + max_q + max value of q_channel + 0x78 + 32 + 0x00000000 + 0xFFFFFF01 + + + MAX + Max value of q_channel, write clear + 8 + 24 + read-write + + + VALID + Max value valid, write clear +0: max value is not valid +1: max value is valid + 0 + 1 + read-write + + + + + min_q + min value of q_channel + 0x7c + 32 + 0x00000000 + 0xFFFFFF01 + + + MIN + Min value of q_channel, write clear + 8 + 24 + read-write + + + VALID + Min value valid, write clear +0: min value is not valid +1: min value is valid + 0 + 1 + read-write + + + + + thrs_i + the offset setting for edge detection of the i_channel + 0x80 + 32 + 0x00000000 + 0xFFFFFF00 + + + THRS + The offset setting for edge detection of the i_channel, signed number +… +2: the offset is 0x800000+2 +1: the offset is 0x800000+1 +0: the offset is 0x800000 +-1: the offset is 0x800000-1 +-2: the offset is 0x800000-2 +… + 8 + 24 + read-write + + + + + thrs_q + the offset setting for edge detection of the q_channel + 0x84 + 32 + 0x00000000 + 0xFFFFFF00 + + + THRS + The offset setting for edge detection of the q_channel, signed number +… +2: the offset is 0x800000+2 +1: the offset is 0x800000+1 +0: the offset is 0x800000 +-1: the offset is 0x800000-1 +-2: the offset is 0x800000-2 +… + 8 + 24 + read-write + + + + + edg_det_ctl + the control for edge detection + 0x88 + 32 + 0x00000080 + 0x000003F7 + + + HOLD + The minimum edge distance in sample +0:1 sample +1:2 sample +2:3 samples +… +63:64 samples + 4 + 6 + read-write + + + FILTER + The continuous positive or negative number for edge detection +0: 1 +1: 2 +… +7: 8 + 0 + 3 + read-write + + + + + acc_scaling + scaling for accumulation result + 0x8c + 32 + 0x00000000 + 0x0000010F + + + TOXIC_LK + Toxic accumulation data be removed control +1: enable +0: disable + 8 + 1 + read-write + + + ACC_SHIFT + Accumulation value shift control, this is a sign number. +0: {acc[39],acc[38:8]} +1: {acc[39],acc[37:7]} +2: {acc[39],acc[36:6]} +… +7: {acc[39],acc[31:1]} +8: {acc[39],acc[30:0]} +9: acc/2^9 +10: acc/2^10 +… +15:acc/2^15 + 0 + 4 + read-write + + + + + exc_period + period of excitation + 0x90 + 32 + 0x00001770 + 0xFFFFFFFF + + + EXC_PERIOD + The num in clock cycle for period of excitation +0: invalid value +1:1 cycle +2:2 cycles +… + 0 + 32 + read-write + + + + + sync_delay_i + delay setting in clock cycle for synchronous signal + 0xa0 + 32 + 0x00000008 + 0xFFFFFFFF + + + DELAY + Delay in clock cycle for synchronous signal, the value shoud less than half of exc_period.exc_period. +0: invalid value +1: 1 cycles +2: 2 cycles +... + 0 + 32 + read-write + + + + + rise_delay_i + delay in clock cycle between excitation synchrnous signal and rising edge of i_channel data + 0xa8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RISE_DELAY + Delay value on rising edge of i_channel data +0: 1 cycle +1: 2 cycles +… + 0 + 32 + read-only + + + + + fall_delay_i + delay in clock cycle between excitation synchrnous signal and falling edge of i_channel data + 0xac + 32 + 0x00000000 + 0xFFFFFFFF + + + FALL_DELAY + Delay value on falling edge of i_channel data +0: 1 cycle +1: 2 cycles +… + 0 + 32 + read-only + + + + + sample_rise_i + sample value on rising edge of rectify signal + 0xb0 + 32 + 0x00000000 + 0xFFFFFF00 + + + VALUE + sample value on rising edge of rectify signal + 8 + 24 + read-only + + + + + sample_fall_i + sample value on falling edge of rectify signal + 0xb4 + 32 + 0x00000000 + 0xFFFFFF00 + + + VALUE + sample value on falling edge of rectify signal + 8 + 24 + read-only + + + + + acc_cnt_i + number of accumulation + 0xb8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNT_NEG + sample number during the negtive of rectify signal +1: 1 +2: 2 +… + 16 + 16 + read-only + + + CNT_POS + sample number during the positive of rectify signal +1: 1 +2: 2 +… + 0 + 16 + read-only + + + + + sign_cnt_i + sample counter of opposite sign with rectify signal + 0xbc + 32 + 0x00000000 + 0xFFFFFFFF + + + CNT_NEG + Positive sample counter during negative rectify signal + 16 + 16 + read-only + + + CNT_POS + Negative sample counter during positive rectify signal + 0 + 16 + read-only + + + + + sync_delay_q + delay setting in clock cycle for synchronous signal + 0xc0 + 32 + 0x00000008 + 0xFFFFFFFF + + + DELAY + Delay in clock cycle for synchronous signal, the value shoud less than half of exc_period.exc_period. +0: invalid value +1: 1 cycles +2: 2 cycles +... + 0 + 32 + read-write + + + + + rise_delay_q + delay in clock cycle between excitation synchrnous signal and rising edge of q_channel data + 0xc8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RISE_DELAY + Delay value on rising edge of q_channel data +0: 1 cycle +1: 2 cycles +… + 0 + 32 + read-only + + + + + fall_delay_q + delay in clock cycle between excitation synchrnous signal and falling edge of q_channel data + 0xcc + 32 + 0x00000000 + 0xFFFFFFFF + + + FALL_DELAY + Delay value on falling edge of q_channel data +0: 1 cycle +1: 2 cycles +… + 0 + 32 + read-only + + + + + sample_rise_q + sample value on rising edge of rectify signal + 0xd0 + 32 + 0x00000000 + 0xFFFFFF00 + + + VALUE + sample value on rising edge of rectify signal + 8 + 24 + read-only + + + + + sample_fall_q + sample value on falling edge of rectify signal + 0xd4 + 32 + 0x00000000 + 0xFFFFFF00 + + + VALUE + sample value on falling edge of rectify signal + 8 + 24 + read-only + + + + + acc_cnt_q + number of accumulation + 0xd8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNT_NEG + sample number during the negtive of rectify signal +1: 1 +2: 2 +… + 16 + 16 + read-only + + + CNT_POS + sample number during the positive of rectify signal +1: 1 +2: 2 +… + 0 + 16 + read-only + + + + + sign_cnt_q + sample counter of opposite sign with rectify signal + 0xdc + 32 + 0x00000000 + 0xFFFFFFFF + + + CNT_NEG + Positive sample counter during negative rectify signal + 16 + 16 + read-only + + + CNT_POS + Negative sample counter during positive rectify signal + 0 + 16 + read-only + + + + + amp_max + the maximum of acc amplitude + 0xe0 + 32 + 0x01000000 + 0xFFFFFFFF + + + MAX + the maximum of acc amplitude + 0 + 32 + read-write + + + + + amp_min + the minimum of acc amplitude + 0xe4 + 32 + 0x00400000 + 0xFFFFFFFF + + + MIN + the minimum of acc amplitude + 0 + 32 + read-write + + + + + int_en + the interrupt mask control + 0xe8 + 32 + 0x00000000 + 0x8000FFFF + + + INT_EN + enable interrupt output + 31 + 1 + read-write + + + ACC_VLD_I_EN + i_channel accumulate valid interrupt enable for i_channel + 15 + 1 + read-write + + + ACC_VLD_Q_EN + q_channel accumulate valid interrupt enable for i_channel + 14 + 1 + read-write + + + RISING_DELAY_I_EN + i_channel delayed rectify signal rising edge interrupt enable + 13 + 1 + read-write + + + FALLING_DELAY_I_EN + i_channel delayed rectify signal falling edge interrupt enable + 12 + 1 + read-write + + + RISING_DELAY_Q_EN + q_channel delayed rectify signal rising edge interrupt enable + 11 + 1 + read-write + + + FALLING_DELAY_Q_EN + q_channel delayed rectify signal falling edge interrupt enable + 10 + 1 + read-write + + + SAMPLE_RISING_I_EN + i_channel rising edge interrupt enable + 9 + 1 + read-write + + + SAMPLE_FALLING_I_EN + i_channel falling edge interrupt enable + 8 + 1 + read-write + + + SAMPLE_RISING_Q_EN + q_channel rising edge interrupt enable + 7 + 1 + read-write + + + SAMPLE_FALLING_Q_EN + q_channel falling edge interrupt enable + 6 + 1 + read-write + + + ACC_VLD_I_OVH_EN + i_channel accumulate overflow interrupt enable + 5 + 1 + read-write + + + ACC_VLD_Q_OVH_EN + q_channel accumulate overflow interrupt enable + 4 + 1 + read-write + + + ACC_VLD_I_OVL_EN + i_channel accumulate underflow interrupt enable + 3 + 1 + read-write + + + ACC_VLD_Q_OVL_EN + q_channel accumulate underflow interrupt enable + 2 + 1 + read-write + + + ACC_AMP_OVH_EN + accumulate ample overflow interrupt enable + 1 + 1 + read-write + + + ACC_AMP_OVL_EN + accumulate ample underflow interrupt enable + 0 + 1 + read-write + + + + + adc_int_state + the interrupt state + 0xec + 32 + 0x00000000 + 0x0000FFFF + + + ACC_VLD_I_STA + i_channel accumulate valid interrupt status for i_channel + 15 + 1 + write-only + + + ACC_VLD_Q_STA + q_channel accumulate valid interrupt status for i_channel + 14 + 1 + write-only + + + RISING_DELAY_I_STA + i_channel delayed rectify signal rising edge interrupt status + 13 + 1 + write-only + + + FALLING_DELAY_I_STA + i_channel delayed rectify signal falling edge interrupt status + 12 + 1 + write-only + + + RISING_DELAY_Q_STA + q_channel delayed rectify signal rising edge interrupt status + 11 + 1 + write-only + + + FALLING_DELAY_Q_STA + q_channel delayed rectify signal falling edge interrupt status + 10 + 1 + write-only + + + SAMPLE_RISING_I_STA + i_channel rising edge interrupt status + 9 + 1 + write-only + + + SAMPLE_FALLING_I_STA + i_channel falling edge interrupt status + 8 + 1 + write-only + + + SAMPLE_RISING_Q_STA + q_channel rising edge interrupt status + 7 + 1 + write-only + + + SAMPLE_FALLING_Q_STA + q_channel falling edge interrupt status + 6 + 1 + write-only + + + ACC_VLD_I_OVH_STA + i_channel accumulate overflow interrupt status + 5 + 1 + write-only + + + ACC_VLD_Q_OVH_STA + q_channel accumulate overflow interrupt status + 4 + 1 + write-only + + + ACC_VLD_I_OVL_STA + i_channel accumulate underflow interrupt status + 3 + 1 + write-only + + + ACC_VLD_Q_OVL_STA + q_channel accumulate underflow interrupt status + 2 + 1 + write-only + + + ACC_AMP_OVH_STA + accumulate ample overflow interrupt status + 1 + 1 + write-only + + + ACC_AMP_OVL_STA + accumulate ample underflow interrupt status + 0 + 1 + write-only + + + + + + + PLB + PLB + PLB + 0xf0324000 + + 0x0 + 0x480 + registers + + + + 4 + 0x20 + 0,1,2,3 + TYPE_A[%s] + no description available + 0x0 + + 4 + 0x4 + 0,1,2,3 + LOOKUP_TABLE[%s] + no description available + 0x0 + 32 + 0x00000000 + 0x0000FFFF + + + LOOKUP_TABLE + using 4 bit trig_in as lookup index. software can program this register as trig_in's true table. + 0 + 16 + read-write + + + + + sw_inject + TYPE A CHN&index0 software inject + 0x10 + 32 + 0x00000000 + 0x0000000F + + + SW_INJECT + software can inject value to TYPEA's output + 0 + 4 + read-write + + + + + + 4 + 0x20 + 0,1,2,3 + TYPE_B[%s] + no description available + 0x400 + + 2 + 0x4 + 0,1 + LUT[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOOKUP_TABLE + lut0 and lut1 union as 64bit, consider each 4bit as one slice. then, total 16 slice. slice0 as bit3:0, slice1 as bit7:4...etc. using 4bit trig in as index of slice. the operate sel in data unit of type B channle is decided by which slice value choosed by trig_in + 0 + 32 + read-write + + + + + 4 + 0x4 + 0,1,2,3 + CMP[%s] + no description available + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP_VALUE + cmp value, using as data unit operation + 0 + 32 + read-write + + + + + mode + TYPE B CHN&index0 mode ctrl + 0x18 + 32 + 0x00000000 + 0x0001FFFF + + + OPT_SEL + operation selection in data unit. + 16 + 1 + read-write + + + OUT3_SEL + trig out 3 output type in current channel + 12 + 4 + read-write + + + OUT2_SEL + trig out 2 output type in current channel + 8 + 4 + read-write + + + OUT1_SEL + trig out 1 output type in current channel + 4 + 4 + read-write + + + OUT0_SEL + trig out 0 output type in current channel + 0 + 4 + read-write + + + + + sw_inject + TYPE B CHN&index0 software inject + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + SOFTWARE_INJECT + data unit value can be changed if program this register + 0 + 32 + read-write + + + + + + + + SYNT + SYNT + SYNT + 0xf0328000 + + 0x0 + 0x30 + registers + + + + gcr + Global control register + 0x0 + 32 + 0x00000000 + 0xF0000037 + + + TIMESTAMP_INC_NEW + set to increase the timesamp with new value, auto clr + 31 + 1 + write-only + + + TIMESTAMP_DEC_NEW + set to decrease the timesamp with new value, auto clr + 30 + 1 + write-only + + + TIMESTAMP_SET_NEW + set the timesamp to new value, auto clr + 29 + 1 + write-only + + + TIMESTAMP_RESET + reset timesamp to 0, auto clr + 28 + 1 + write-only + + + TIMESTAMP_DEBUG_EN + set to enable cpu_debug_mode to stop the timesamp + 5 + 1 + read-write + + + TIMESTAMP_ENABLE + set to enable the timesamp , clr to stop + 4 + 1 + read-write + + + COUNTER_DEBUG_EN + set to enable cpu_debug_mode to stop the counter + 2 + 1 + read-write + + + CRST + 1- Reset counter + 1 + 1 + read-write + + + CEN + 1- Enable counter + 0 + 1 + read-write + + + + + rld + Counter reload register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RLD + counter reload value + 0 + 32 + read-write + + + + + timestamp_new + timestamp new value register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + VALUE + new value for timesamp , can be used as set/inc/dec + 0 + 32 + read-write + + + + + cnt + Counter + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + CNT + counter + 0 + 32 + read-only + + + + + timestamp_sav + timestamp trig save value + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + VALUE + use the trigger to save timesamp here + 0 + 32 + read-only + + + + + timestamp_cur + timestamp read value + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + VALUE + current timesamp value + 0 + 32 + read-only + + + + + 4 + 0x4 + 0,1,2,3 + CMP[%s] + no description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + comparator value, the output will assert when counter count to this value + 0 + 32 + read-write + + + + + + + SEI + SEI + SEI + 0xf032c000 + + 0x0 + 0x3a80 + registers + + + + 2 + 0x400 + 0,1 + CTRL[%s] + no description available + 0x0 + + ENGINE_CTRL + Engine control register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + WATCH + Enable watch dog +0: Watch dog disabled +1: Watch dog enabled + 24 + 1 + read-write + + + ARMING + Wait for trigger before excuting +0: Execute on enable +1: Wait trigger before exection after enabled + 16 + 1 + read-write + + + EXCEPT + Explain timout as exception +0: when timeout, pointer move to next instruction +1: when timeout, pointer jump to timeout vector + 8 + 1 + read-write + + + REWIND + Rewind execution pointer +0: run +1: clean status and rewind + 4 + 1 + read-write + + + ENABLE + Enable +0: disable +1: enable + 0 + 1 + read-write + + + + + ENGINE_PTR_CFG + Pointer configuration register + 0x4 + 32 + 0x00000000 + 0xFF1FFFFF + + + DAT_CDM + Select DATA register to receive CDM bit in BiSSC slave mode +0: ignore +1: command +2: data register 2 +3: data register 3 +... +29:data register 29 +30: value 0 when send, ignore in receive +31: value1 when send, ignore in receive + 24 + 5 + read-write + + + DAT_BASE + Bias for data register access, if calculated index bigger than 32, index will wrap around +0: real data index +1: access index is 1 greater than instruction address +2: access index is 2 greater than instruction address +... +31: access index is 31 greater than instruction address + 16 + 5 + read-write + + + POINTER_WDOG + Pointer to the instruction that the program starts executing after the instruction timeout. The timeout is WDOG_TIME + 8 + 8 + read-write + + + POINTER_INIT + Initial execute pointer + 0 + 8 + read-write + + + + + ENGINE_WDG_CFG + Watch dog configuration register + 0x8 + 32 + 0x00000000 + 0x0000FFFF + + + WDOG_TIME + Time out count for each instruction, counter in bit time. + 0 + 16 + read-write + + + + + ENGINE_EXE_STA + Execution status + 0x10 + 32 + 0x00000000 + 0x00110101 + + + TRIGERED + Execution has been triggered +0: Execution not triggered +1: Execution triggered + 20 + 1 + read-only + + + ARMED + Waiting for trigger for execution +0: Not in waiting status +1: In waiting status + 16 + 1 + read-only + + + EXPIRE + Watchdog timer expired +0: Not expired +1: Expired + 8 + 1 + read-only + + + STALL + Program finished +0: Program is executing +1: Program finished + 0 + 1 + read-only + + + + + ENGINE_EXE_PTR + Execution pointer + 0x14 + 32 + 0x00000000 + 0x1F1F00FF + + + HALT_CNT + Halt count in halt instrution + 24 + 5 + read-only + + + BIT_CNT + Bit count in send and receive instruction execution + 16 + 5 + read-only + + + POINTER + Current program pointer + 0 + 8 + read-only + + + + + ENGINE_EXE_INST + Execution instruction + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + INST + Current instruction + 0 + 32 + read-only + + + + + ENGINE_WDG_STA + Watch dog status + 0x1c + 32 + 0x00000000 + 0x0000FFFF + + + WDOG_CNT + Current watch dog counter value + 0 + 16 + read-only + + + + + XCVR_CTRL + Transceiver control register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRISMP + Tipple sampe +0: sample 1 time for data transition +1: sample 3 times in receive and result in 2oo3 + 12 + 1 + read-write + + + PAR_CLR + Clear parity error, this is a self clear bit +0: no effect +1: clear parity error + 8 + 1 + write-only + + + RESTART + Restart tranceiver, this is a self clear bit +0: no effect +1: reset tranceiver + 4 + 1 + write-only + + + MODE + Tranceiver mode +0: synchronous maaster +1: synchronous slave +2: asynchronous mode +3: asynchronous mode + 0 + 2 + read-write + + + + + XCVR_TYPE_CFG + Transceiver configuration register + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + WAIT_LEN + Number of extra stop bit for asynchronous mode +0: 1 bit +1: 2 bit +... +255: 256 bit + 24 + 8 + read-write + + + DATA_LEN + Number of data bit for asynchronous mode +0: 1 bit +1: 2 bit +... +31: 32 bit + 16 + 5 + read-write + + + PAR_POL + Polarity of parity for asynchronous mode +0: even +1: odd + 9 + 1 + read-write + + + PAR_EN + enable parity check for asynchronous mode +0: disable +1: enable + 8 + 1 + read-write + + + DA_IDLEZ + Idle state driver of data line +0: output +1: high-Z + 3 + 1 + read-write + + + CK_IDLEZ + Idle state driver of clock line +0: output +1: high-Z + 2 + 1 + read-write + + + DA_IDLEV + Idle state value of data line +0: data'0' +1: data'1' + 1 + 1 + read-write + + + CK_IDLEV + Idle state value of clock line +0: data'0' +1: data'1' + 0 + 1 + read-write + + + + + XCVR_BAUD_CFG + Transceiver baud rate register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + SYNC_POINT + Baud synchronous time, minmum bit time + 16 + 16 + read-write + + + BAUD_DIV + Baud rate, bit time in system clock cycle + 0 + 16 + read-write + + + + + XCVR_DATA_CFG + Transceiver data timing configuration + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + TXD_POINT + data transmit point in system clcok cycle + 16 + 16 + read-write + + + RXD_POINT + data receive point in system clcok cycle + 0 + 16 + read-write + + + + + XCVR_CLK_CFG + Transceiver clock timing configuration + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + CK1_POINT + clock point 1 in system clcok cycle + 16 + 16 + read-write + + + CK0_POINT + clock point 0 in system clcok cycle + 0 + 16 + read-write + + + + + XCVR_PIN + Transceiver pin status + 0x38 + 32 + 0x00000000 + 0x07070707 + + + OE_CK + CK drive state +0: input +1: output + 26 + 1 + read-only + + + DI_CK + CK state +0: data 0 +1: data 1 + 25 + 1 + read-only + + + DO_CK + CK output +0: data 0 +1: data 1 + 24 + 1 + read-only + + + OE_RX + RX drive state +0: input +1: output + 18 + 1 + read-only + + + DI_RX + RX state +0: data 0 +1: data 1 + 17 + 1 + read-only + + + DO_RX + RX output +0: data 0 +1: data 1 + 16 + 1 + read-only + + + OE_DE + DE drive state +0: input +1: output + 10 + 1 + read-only + + + DI_DE + DE state +0: data 0 +1: data 1 + 9 + 1 + read-only + + + DO_DE + DE output +0: data 0 +1: data 1 + 8 + 1 + read-only + + + OE_TX + TX drive state +0: input +1: output + 2 + 1 + read-only + + + DI_TX + TX state +0: data 0 +1: data 1 + 1 + 1 + read-only + + + DO_TX + TX output +0: data 0 +1: data 1 + 0 + 1 + read-only + + + + + XCVR_STATE + FSM of asynchronous + 0x3c + 32 + 0x00000000 + 0x07070000 + + + RECV_STATE + FSM of asynchronous receive + 24 + 3 + read-only + + + SEND_STATE + FSM of asynchronous transmit + 16 + 3 + read-only + + + + + TRG_IN_CFG + Trigger input configuration + 0x40 + 32 + 0x00000000 + 0x00878787 + + + PRD_EN + Enable period trigger (tigger 2) +0: periodical trigger disabled +1: periodical trigger enabled + 23 + 1 + read-write + + + SYNC_SEL + Synchronize sigal selection (tigger 2) +0: trigger in 0 +1: trigger in 1 +... +7: trigger in 7 + 16 + 3 + read-write + + + IN1_EN + Enable trigger 1 +0: disable trigger 1 +1: enable trigger 1 + 15 + 1 + read-write + + + IN1_SEL + Trigger 1 sigal selection +0: trigger in 0 +1: trigger in 1 +... +7: trigger in 7 + 8 + 3 + read-write + + + IN0_EN + Enable trigger 0 +0: disable trigger 1 +1: enable trigger 1 + 7 + 1 + read-write + + + IN0_SEL + Trigger 0 sigal selection +0: trigger in 0 +1: trigger in 1 +... +7: trigger in 7 + 0 + 3 + read-write + + + + + TRG_SW + Software trigger + 0x44 + 32 + 0x00000000 + 0x00000001 + + + SOFT + Software trigger (tigger 3). this bit is self-clear +0: trigger source disabled +1: trigger source enabled + 0 + 1 + write-only + + + + + TRG_PRD_CFG + Period trigger configuration + 0x48 + 32 + 0x00000000 + 0xFFFF0001 + + + ARMING + Wait for trigger synchronous before trigger +0: Trigger directly +1: Wait trigger source before period trigger + 16 + 1 + read-write + + + SYNC + Synchronous +0: Not synchronous +1: Synchronous every trigger source + 0 + 1 + read-write + + + + + TRG_PRD + Trigger period + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + PERIOD + Trigger period + 0 + 32 + read-write + + + + + TRG_OUT_CFG + Trigger output configuration + 0x50 + 32 + 0x00000000 + 0x87878787 + + + OUT3_EN + Enable trigger 3 +0: disable trigger 3 +1: enable trigger 3 + 31 + 1 + read-write + + + OUT3_SEL + Trigger 3 sigal selection +0: trigger out 0 +1: trigger out 1 +... +7: trigger out 7 + 24 + 3 + read-write + + + OUT2_EN + Enable trigger 2 +0: disable trigger 2 +1: enable trigger 2 + 23 + 1 + read-write + + + OUT2_SEL + Trigger 2 sigal selection +0: trigger out 0 +1: trigger out 1 +... +7: trigger out 7 + 16 + 3 + read-write + + + OUT1_EN + Enable trigger 1 +0: disable trigger 1 +1: enable trigger 1 + 15 + 1 + read-write + + + OUT1_SEL + Trigger 1 sigal selection +0: trigger out 0 +1: trigger out 1 +... +7: trigger out 7 + 8 + 3 + read-write + + + OUT0_EN + Enable trigger 0 +0: disable trigger 1 +1: enable trigger 1 + 7 + 1 + read-write + + + OUT0_SEL + Trigger 0 sigal selection +0: trigger out 0 +1: trigger out 1 +... +7: trigger out 7 + 0 + 3 + read-write + + + + + TRG_PRD_STS + Period trigger status + 0x60 + 32 + 0x00000000 + 0x00110000 + + + TRIGERED + Period has been triggered +0: Not triggered +1: Triggered + 20 + 1 + read-only + + + ARMED + Waiting for trigger +0: Not in waiting status +1: In waiting status + 16 + 1 + read-only + + + + + TRG_PRD_CNT + Period trigger counter + 0x64 + 32 + 0x00000000 + 0xFFFFFFFF + + + PERIOD_CNT + Trigger period counter + 0 + 32 + read-only + + + + + 4 + 0x4 + 0,1,2,3 + TRG_TABLE_CMD[%s] + no description available + 0x80 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMD_TRIGGER0 + Trigger command + 0 + 32 + read-write + + + + + 4 + 0x4 + 0,1,2,3 + TRG_TABLE_TIME[%s] + no description available + 0xa0 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRIGGER0_TIME + Trigger time + 0 + 32 + read-only + + + + + CMD_MODE + command register mode + 0xc0 + 32 + 0x00000000 + 0xE0FFCFFF + + + WLEN + word length +0: 1 bit +1: 2 bit +... +31: 32 bit + 16 + 5 + read-write + + + WORDER + word order +0: sample as bit order +1: different from bit order + 11 + 1 + read-write + + + BORDER + bit order +0: LSB first +1: MSB first + 10 + 1 + read-write + + + SIGNED + Signed +0: unsigned value +1: signed value + 9 + 1 + read-write + + + REWIND + Write 1 to rewind read/write pointer, this is a self clear bit + 8 + 1 + write-only + + + MODE + Data mode(CMD register only support data mode) +0: data mode +1: check mode +2: CRC mode + 0 + 2 + read-write + + + + + CMD_IDX + command register configuration + 0xc4 + 32 + 0x00000000 + 0xFFFFFFFF + + + LAST_BIT + Last bit index for tranceive + 24 + 5 + read-write + + + FIRST_BIT + First bit index for tranceive + 16 + 5 + read-write + + + MAX_BIT + Highest bit index + 8 + 5 + read-write + + + MIN_BIT + Lowest bit index + 0 + 5 + read-write + + + + + CMD_CMD + command + 0xe0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + DATA + 0 + 32 + read-write + + + + + CMD_SET + command bit set register + 0xe4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA_SET + DATA bit set + 0 + 32 + read-write + + + + + CMD_CLR + command bit clear register + 0xe8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA_CLR + DATA bit clear + 0 + 32 + read-write + + + + + CMD_INV + command bit invert register + 0xec + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA_TGL + DATA bit toggle + 0 + 32 + read-write + + + + + CMD_IN + Commad input + 0xf0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA_IN + Commad input + 0 + 32 + read-only + + + + + CMD_OUT + Command output + 0xf4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA_OUT + Command output + 0 + 32 + read-only + + + + + CMD_STS + Command status + 0xf8 + 32 + 0x00000000 + 0xE0FFFFFF + + + WORD_IDX + Word index + 16 + 5 + read-only + + + WORD_CNT + Word counter + 8 + 5 + read-only + + + BIT_IDX + Bit index + 0 + 5 + read-only + + + + + 8 + 0x20 + 0,1,2,3,4,5,6,7 + CMD_CMD_TABLE[%s] + no description available + 0x100 + + MIN + command start value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMD_MIN + minimum command value + 0 + 32 + read-write + + + + + MAX + command end value + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMD_MAX + maximum command value + 0 + 32 + read-write + + + + + MSK + command compare bit enable + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMD_MASK + compare mask + 0 + 32 + read-write + + + + + PTA + command pointer 0 - 3 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + PTR3 + pointer3 + 24 + 8 + read-write + + + PTR2 + pointer2 + 16 + 8 + read-write + + + PTR1 + pointer1 + 8 + 8 + read-write + + + PTR0 + pointer0 + 0 + 8 + read-write + + + + + PTB + command pointer 4 - 7 + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + PTR7 + pointer7 + 24 + 8 + read-write + + + PTR6 + pointer6 + 16 + 8 + read-write + + + PTR5 + pointer5 + 8 + 8 + read-write + + + PTR4 + pointer4 + 0 + 8 + read-write + + + + + + 4 + 0x20 + 0,1,2,3 + CMD_LATCH[%s] + no description available + 0x200 + + 4 + 0x4 + 0_1,1_2,2_3,3_0 + TRAN[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFF0F3FF7 + + + POINTER + pointer + 24 + 8 + read-write + + + CFG_TM + timeout +0: high +1: low +2: rise +3: fall + 16 + 2 + read-write + + + CFG_TXD + data send +0: high +1: low +2: rise +3: fall + 12 + 2 + read-write + + + CFG_CLK + clock +0: high +1: low +2: rise +3: fall + 10 + 2 + read-write + + + CFG_PTR + pointer +0: match +1: not match +2:entry +3:leave + 8 + 2 + read-write + + + OV_TM + override timeout check + 4 + 1 + read-write + + + OV_TXD + override TX data check + 2 + 1 + read-write + + + OV_CLK + override clock check + 1 + 1 + read-write + + + OV_PTR + override pointer check + 0 + 1 + read-write + + + + + CFG + Latch configuration + 0x10 + 32 + 0x00000000 + 0x8700FFFF + + + EN + Enable latch +0: disable +1: enable + 31 + 1 + read-write + + + SELECT + Output select +0: state0-state1 +1: state1-state2 +2: state2-state3 +3: state3-state0 + 24 + 3 + read-write + + + DELAY + Delay in system clock cycle, for state transition + 0 + 16 + read-write + + + + + TIME + Latch time + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + LAT_TIME + Latch time + 0 + 32 + read-only + + + + + STS + Latch status + 0x1c + 32 + 0x00000000 + 0x0700FFFF + + + STATE + State + 24 + 3 + read-only + + + LAT_CNT + Latch counter + 0 + 16 + read-only + + + + + + POS_SMP_EN + Sample selection register + 0x280 + 32 + 0x00000000 + 0xFFFFFFFF + + + ACC_EN + Position include acceleration + 31 + 1 + read-write + + + ACC_SEL + Data register for acceleration transfer + 24 + 5 + read-write + + + SPD_EN + Position include speed + 23 + 1 + read-write + + + SPD_SEL + Data register for speed transfer + 16 + 5 + read-write + + + REV_EN + Position include revolution + 15 + 1 + read-write + + + REV_SEL + Data register for revolution transfer + 8 + 5 + read-write + + + POS_EN + Position include position + 7 + 1 + read-write + + + POS_SEL + Data register for position transfer + 0 + 5 + read-write + + + + + POS_SMP_CFG + Sample configuration + 0x284 + 32 + 0x00000000 + 0x0103FFFF + + + ONCE + Sample one time +0: Sample during windows time +1: Close sample window after first sample + 24 + 1 + read-write + + + LAT_SEL + Latch selection +0: latch 0 +1: latch 1 +2: latch 2 +3: latch 3 + 16 + 2 + read-write + + + WINDOW + Sample window, in clock cycle + 0 + 16 + read-write + + + + + POS_SMP_DAT + Sample data + 0x288 + 32 + 0x00000000 + 0xFFFFFFFF + + + DAT_SEL + Data register sampled, each bit represent a data register + 0 + 32 + read-write + + + + + POS_SMP_POS + Sample override position + 0x290 + 32 + 0x00000000 + 0xFFFFFFFF + + + POS + Sample override position + 0 + 32 + read-write + + + + + POS_SMP_REV + Sample override revolution + 0x294 + 32 + 0x00000000 + 0xFFFFFFFF + + + REV + Sample override revolution + 0 + 32 + read-write + + + + + POS_SMP_SPD + Sample override speed + 0x298 + 32 + 0x00000000 + 0xFFFFFFFF + + + SPD + Sample override speed + 0 + 32 + read-write + + + + + POS_SMP_ACC + Sample override accelerate + 0x29c + 32 + 0x00000000 + 0xFFFFFFFF + + + ACC + Sample override accelerate + 0 + 32 + read-write + + + + + POS_UPD_EN + Update configuration + 0x2a0 + 32 + 0x00000000 + 0xFFFFFFFF + + + ACC_EN + Position include acceleration + 31 + 1 + read-write + + + ACC_SEL + Data register for acceleration transfer + 24 + 5 + read-write + + + SPD_EN + Position include speed + 23 + 1 + read-write + + + SPD_SEL + Data register for speed transfer + 16 + 5 + read-write + + + REV_EN + Position include revolution + 15 + 1 + read-write + + + REV_SEL + Data register for revolution transfer + 8 + 5 + read-write + + + POS_EN + Position include position + 7 + 1 + read-write + + + POS_SEL + Data register for position transfer + 0 + 5 + read-write + + + + + POS_UPD_CFG + Update configuration + 0x2a4 + 32 + 0x00000000 + 0x81030000 + + + TIME_OVRD + Use override time +0: use time sample from motor group +1: use override time + 31 + 1 + read-write + + + ONERR + Sample one time +0: Sample during windows time +1: Close sample window after first sample + 24 + 1 + read-write + + + LAT_SEL + Latch selection +0: latch 0 +1: latch 1 +2: latch 2 +3: latch 3 + 16 + 2 + read-write + + + + + POS_UPD_DAT + Update data + 0x2a8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DAT_SEL + Data register sampled, each bit represent a data register + 0 + 32 + read-write + + + + + POS_UPD_TIME + Update overide time + 0x2ac + 32 + 0x00000000 + 0xFFFFFFFF + + + TIME + Update override time + 0 + 32 + read-write + + + + + POS_UPD_POS + Update override position + 0x2b0 + 32 + 0x00000000 + 0xFFFFFFFF + + + POS + Update override position + 0 + 32 + read-write + + + + + POS_UPD_REV + Update override revolution + 0x2b4 + 32 + 0x00000000 + 0xFFFFFFFF + + + REV + Update override revolution + 0 + 32 + read-write + + + + + POS_UPD_SPD + Update override speed + 0x2b8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SPD + Update override speed + 0 + 32 + read-write + + + + + POS_UPD_ACC + Update override accelerate + 0x2bc + 32 + 0x00000000 + 0xFFFFFFFF + + + ACC + Update override accelerate + 0 + 32 + read-write + + + + + POS_SMP_VAL + Sample valid + 0x2c0 + 32 + 0x00000000 + 0x80808080 + + + ACC + Position include acceleration + 31 + 1 + read-only + + + SPD + Position include speed + 23 + 1 + read-only + + + REV + Position include revolution + 15 + 1 + read-only + + + POS + Position include position + 7 + 1 + read-only + + + + + POS_SMP_STS + Sample status + 0x2c4 + 32 + 0x00000000 + 0x0100FFFF + + + OCCUR + Sample occured +0: Sample not happened +1: Sample occured + 24 + 1 + read-only + + + WIN_CNT + Sample window counter + 0 + 16 + read-only + + + + + POS_TIME_IN + input time + 0x2cc + 32 + 0x00000000 + 0xFFFFFFFF + + + TIME + input time + 0 + 32 + read-only + + + + + POS_POS_IN + Input position + 0x2d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + POS + Input position + 0 + 32 + read-only + + + + + POS_REV_IN + Input revolution + 0x2d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + REV + Input revolution + 0 + 32 + read-only + + + + + POS_SPD_IN + Input speed + 0x2d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SPD + Input speed + 0 + 32 + read-only + + + + + POS_ACC_IN + Input accelerate + 0x2dc + 32 + 0x00000000 + 0xFFFFFFFF + + + ACC + Input accelerate + 0 + 32 + read-only + + + + + POS_UPD_STS + Update status + 0x2e4 + 32 + 0x00000000 + 0x01000000 + + + UPD_ERR + Update error +0: data receive normally +1: data receive error + 24 + 1 + read-only + + + + + IRQ_INT_EN + Interrupt Enable + 0x300 + 32 + 0x00000000 + 0xFF1F3FF7 + + + TRG_ERR3 + Trigger3 failed + 31 + 1 + read-write + + + TRG_ERR2 + Trigger2 failed + 30 + 1 + read-write + + + TRG_ERR1 + Trigger1 failed + 29 + 1 + read-write + + + TRG_ERR0 + Trigger0 failed + 28 + 1 + read-write + + + TRIGER3 + Trigger3 + 27 + 1 + read-write + + + TRIGER2 + Trigger2 + 26 + 1 + read-write + + + TRIGER1 + Trigger1 + 25 + 1 + read-write + + + TRIGER0 + Trigger0 + 24 + 1 + read-write + + + SMP_ERR + Sample error + 20 + 1 + read-write + + + LATCH3 + Latch3 + 19 + 1 + read-write + + + LATCH2 + Latch2 + 18 + 1 + read-write + + + LATCH1 + Latch1 + 17 + 1 + read-write + + + LATCH0 + Latch0 + 16 + 1 + read-write + + + TIMEOUT + Timeout + 13 + 1 + read-write + + + TRX_ERR + Transfer error + 12 + 1 + read-write + + + INSTR1_END + Instruction 1 end + 11 + 1 + read-write + + + INSTR0_END + Instruction 0 end + 10 + 1 + read-write + + + PTR1_END + Pointer 1 end + 9 + 1 + read-write + + + PTR0_END + Pointer 0 end + 8 + 1 + read-write + + + INSTR1_ST + Instruction 1 start + 7 + 1 + read-write + + + INSTR0_ST + Instruction 0 start + 6 + 1 + read-write + + + PTR1_ST + Pointer 1 start + 5 + 1 + read-write + + + PTR0_ST + Pointer 0 start + 4 + 1 + read-write + + + WDOG + Watch dog + 2 + 1 + read-write + + + EXCEPT + Exception + 1 + 1 + read-write + + + STALL + Stall + 0 + 1 + read-write + + + + + IRQ_INT_FLAG + Interrupt flag + 0x304 + 32 + 0x00000000 + 0xFF1F3FF7 + + + TRG_ERR3 + Trigger3 failed + 31 + 1 + write-only + + + TRG_ERR2 + Trigger2 failed + 30 + 1 + write-only + + + TRG_ERR1 + Trigger1 failed + 29 + 1 + write-only + + + TRG_ERR0 + Trigger0 failed + 28 + 1 + write-only + + + TRIGER3 + Trigger3 + 27 + 1 + write-only + + + TRIGER2 + Trigger2 + 26 + 1 + write-only + + + TRIGER1 + Trigger1 + 25 + 1 + write-only + + + TRIGER0 + Trigger0 + 24 + 1 + write-only + + + SMP_ERR + Sample error + 20 + 1 + write-only + + + LATCH3 + Latch3 + 19 + 1 + write-only + + + LATCH2 + Latch2 + 18 + 1 + write-only + + + LATCH1 + Latch1 + 17 + 1 + write-only + + + LATCH0 + Latch0 + 16 + 1 + write-only + + + TIMEOUT + Timeout + 13 + 1 + write-only + + + TRX_ERR + Transfer error + 12 + 1 + write-only + + + INSTR1_END + Instruction 1 end + 11 + 1 + write-only + + + INSTR0_END + Instruction 0 end + 10 + 1 + write-only + + + PTR1_END + Pointer 1 end + 9 + 1 + write-only + + + PTR0_END + Pointer 0 end + 8 + 1 + write-only + + + INSTR1_ST + Instruction 1 start + 7 + 1 + write-only + + + INSTR0_ST + Instruction 0 start + 6 + 1 + write-only + + + PTR1_ST + Pointer 1 start + 5 + 1 + write-only + + + PTR0_ST + Pointer 0 start + 4 + 1 + write-only + + + WDOG + Watch dog + 2 + 1 + write-only + + + EXCEPT + Exception + 1 + 1 + write-only + + + STALL + Stall + 0 + 1 + write-only + + + + + IRQ_INT_STS + Interrupt status + 0x308 + 32 + 0x00000000 + 0xFF1F3FF7 + + + TRG_ERR3 + Trigger3 failed + 31 + 1 + read-only + + + TRG_ERR2 + Trigger2 failed + 30 + 1 + read-only + + + TRG_ERR1 + Trigger1 failed + 29 + 1 + read-only + + + TRG_ERR0 + Trigger0 failed + 28 + 1 + read-only + + + TRIGER3 + Trigger3 + 27 + 1 + read-only + + + TRIGER2 + Trigger2 + 26 + 1 + read-only + + + TRIGER1 + Trigger1 + 25 + 1 + read-only + + + TRIGER0 + Trigger0 + 24 + 1 + read-only + + + SMP_ERR + Sample error + 20 + 1 + read-only + + + LATCH3 + Latch3 + 19 + 1 + read-only + + + LATCH2 + Latch2 + 18 + 1 + read-only + + + LATCH1 + Latch1 + 17 + 1 + read-only + + + LATCH0 + Latch0 + 16 + 1 + read-only + + + TIMEOUT + Timeout + 13 + 1 + read-only + + + TRX_ERR + Transfer error + 12 + 1 + read-only + + + INSTR1_END + Instruction 1 end + 11 + 1 + read-only + + + INSTR0_END + Instruction 0 end + 10 + 1 + read-only + + + PTR1_END + Pointer 1 end + 9 + 1 + read-only + + + PTR0_END + Pointer 0 end + 8 + 1 + read-only + + + INSTR1_ST + Instruction 1 start + 7 + 1 + read-only + + + INSTR0_ST + Instruction 0 start + 6 + 1 + read-only + + + PTR1_ST + Pointer 1 start + 5 + 1 + read-only + + + PTR0_ST + Pointer 0 start + 4 + 1 + read-only + + + WDOG + Watch dog + 2 + 1 + read-only + + + EXCEPT + Exception + 1 + 1 + read-only + + + STALL + Stall + 0 + 1 + read-only + + + + + IRQ_POINTER0 + Match pointer 0 + 0x310 + 32 + 0x00000000 + 0x000000FF + + + POINTER + Match pointer 0 + 0 + 8 + read-write + + + + + IRQ_POINTER1 + Match pointer 1 + 0x314 + 32 + 0x00000000 + 0x000000FF + + + POINTER + Match pointer 1 + 0 + 8 + read-write + + + + + IRQ_INSTR0 + Match instruction 0 + 0x318 + 32 + 0x00000000 + 0xFFFFFFFF + + + INSTR + Match instruction 0 + 0 + 32 + read-write + + + + + IRQ_INSTR1 + Match instruction 1 + 0x31c + 32 + 0x00000000 + 0xFFFFFFFF + + + INSTR + Match instruction 1 + 0 + 32 + read-write + + + + + + 64 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63 + INSTR[%s] + no description available + 0x3400 + 32 + 0x00000000 + 0xFFFFFFFF + + + OP + operation +0: halt +1: jump +2: send with timeout check +3: send without timout check +4: wait with timeout check +5: wait without timout check +6: receive with timeout check +7: receive without timout check + 26 + 3 + read-write + + + CK + clock +0: low +1: rise-fall +2: fall-rise +3: high + 24 + 2 + read-write + + + CRC + CRC register +0: don't calculate CRC +1: do not set this value +2: data register 2 +3: data register 3 +... +29: data register 29 +30: value 0 when send, wait 0 in receive +31: value1 when send, wait 1 in receive + 16 + 5 + read-write + + + DAT + DATA register +0: ignore data +1: command +2: data register 2 +3: data register 3 +... +29: data register 29 +30: value 0 when send, wait 0 in receive +31: value1 when send, wait 1 in receive + 8 + 5 + read-write + + + OPR + [1] When OP is 0, this area is the halt time in baudrate, 0 represents infinite time. +[2] When OP is 1, this area is the the pointer to the command table. +OPR[4]=1, OPR[3:0] value is CMD_TABLE instruct pointer; +OPR[4]=0, OPR[3:0]=0 is INIT_POINTER; +OPR[4]=0, OPR[3:0]=1 is WDG_POINTER. +[3] When OP is 2-7, this area is the data length as fellow: +0: 1 bit +1: 2 bit + ... +31: 32 bit + 0 + 5 + read-write + + + + + 10 + 0x40 + 0,1,2,3,4,5,6,7,8,9 + DAT[%s] + no description available + 0x3800 + + MODE + No description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CRC_LEN + CRC length +0: 1 bit +1: 2 bit +... +31: 32 bit + 24 + 5 + read-write + + + WLEN + word length +0: 1 bit +1: 2 bit +... +31: 32 bit + 16 + 5 + read-write + + + CRC_SHIFT + CRC shift mode, this mode is used to perform repeat code check +0: CRC +1: shift mode + 13 + 1 + read-write + + + CRC_INV + CRC invert +0: use CRC +1: use inverted CRC + 12 + 1 + read-write + + + WORDER + word order +0: sample as bit order +1: different from bit order + 11 + 1 + read-write + + + BORDER + bit order +0: LSB first +1: MSB first + 10 + 1 + read-write + + + SIGNED + Signed +0: unsigned value +1: signed value + 9 + 1 + read-write + + + REWIND + Write 1 to rewind read/write pointer, this is a self clear bit + 8 + 1 + read-write + + + MODE + Data mode +0: data mode +1: check mode +2: CRC mode + 0 + 2 + read-write + + + + + IDX + Data register bit index + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + LAST_BIT + Last bit index for tranceive + 24 + 5 + read-write + + + FIRST_BIT + First bit index for tranceive + 16 + 5 + read-write + + + MAX_BIT + Highest bit index + 8 + 5 + read-write + + + MIN_BIT + Lowest bit index + 0 + 5 + read-write + + + + + GOLD + Gold data for data check + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + GOLD_VALUE + Gold value for check mode + 0 + 32 + read-write + + + + + CRCINIT + CRC calculation initial vector + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + CRC_INIT + CRC initial value + 0 + 32 + read-write + + + + + CRCPOLY + CRC calculation polynomial + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + CRC_POLY + CRC polymonial + 0 + 32 + read-write + + + + + DATA + Data value + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + DATA + 0 + 32 + read-write + + + + + SET + Data bit set + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA_SET + DATA bit set + 0 + 32 + read-write + + + + + CLR + Data bit clear + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA_CLR + DATA bit clear + 0 + 32 + read-write + + + + + INV + Data bit invert + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA_INV + DATA bit toggle + 0 + 32 + read-write + + + + + IN + Data input + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA_IN + Data input + 0 + 32 + read-only + + + + + OUT + Data output + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA_OUT + Data output + 0 + 32 + read-only + + + + + STS + Data status + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + CRC_IDX + CRC index + 24 + 5 + read-only + + + WORD_IDX + Word index + 16 + 5 + read-only + + + WORD_CNT + Word counter + 8 + 5 + read-only + + + BIT_IDX + Bit index + 0 + 5 + read-only + + + + + + + + TRGM0 + TRGM0 + TRGM + 0xf033c000 + + 0x0 + 0x634 + registers + + + + 28 + 0x4 + PWM0_IN0,PWM0_IN1,PWM0_IN2,PWM0_IN3,PWM0_IN4,PWM0_IN5,PWM0_IN6,PWM0_IN7,PWM1_IN0,PWM1_IN1,PWM1_IN2,PWM1_IN3,PWM1_IN4,PWM1_IN5,PWM1_IN6,PWM1_IN7,MOTO_GPIO_IN0,MOTO_GPIO_IN1,MOTO_GPIO_IN2,MOTO_GPIO_IN3,MOTO_GPIO_IN4,MOTO_GPIO_IN5,MOTO_GPIO_IN6,MOTO_GPIO_IN7,PWM0_FAULT0,PWM0_FAULT1,PWM1_FAULT0,PWM1_FAULT1 + FILTCFG[%s] + no description available + 0x0 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN_SHIFT + No description available + 9 + 3 + read-write + + + FILTLEN_BASE + This bitfields defines the filter counter length. + 0 + 9 + read-write + + + + + 137 + 0x4 + MOT2OPAMP0_0,MOT2OPAMP0_1,MOT2OPAMP0_2,MOT2OPAMP0_3,MOT2OPAMP0_4,MOT2OPAMP0_5,MOT2OPAMP0_6,MOT2OPAMP0_7,MOT2OPAMP1_0,MOT2OPAMP1_1,MOT2OPAMP1_2,MOT2OPAMP1_3,MOT2OPAMP1_4,MOT2OPAMP1_5,MOT2OPAMP1_6,MOT2OPAMP1_7,GPTMR0_IN2,GPTMR0_IN3,GPTMR0_SYNCI,GPTMR1_IN2,GPTMR1_IN3,GPTMR1_SYNCI,GPTMR2_IN2,GPTMR2_IN3,GPTMR2_SYNCI,GPTMR3_IN2,GPTMR3_IN3,GPTMR3_SYNCI,CMP0_WIN,CMP1_WIN,DAC0_BUFTRG,DAC1_BUFTRG,ADC0_STRGI,ADC1_STRGI,ADCx_PTRGI0A,ADCx_PTRGI0B,ADCx_PTRGI0C,ADCx_PTRGI1A,ADCx_PTRGI1B,ADCx_PTRGI1C,ADCx_PTRGI2A,ADCx_PTRGI2B,ADCx_PTRGI2C,ADCx_PTRGI3A,ADCx_PTRGI3B,ADCx_PTRGI3C,CAN_PTPC0_CAP,CAN_PTPC1_CAP,QEO0_TRIG_IN0,QEO0_TRIG_IN1,QEO1_TRIG_IN0,QEO1_TRIG_IN1,SEI_TRIG_IN0,SEI_TRIG_IN1,SEI_TRIG_IN2,SEI_TRIG_IN3,SEI_TRIG_IN4,SEI_TRIG_IN5,SEI_TRIG_IN6,SEI_TRIG_IN7,MMC0_TRIG_IN0,MMC0_TRIG_IN1,MMC1_TRIG_IN0,MMC1_TRIG_IN1,PLB_IN_00,PLB_IN_01,PLB_IN_02,PLB_IN_03,PLB_IN_04,PLB_IN_05,PLB_IN_06,PLB_IN_07,PLB_IN_08,PLB_IN_09,PLB_IN_10,PLB_IN_11,PLB_IN_12,PLB_IN_13,PLB_IN_14,PLB_IN_15,PLB_IN_16,PLB_IN_17,PLB_IN_18,PLB_IN_19,PLB_IN_20,PLB_IN_21,PLB_IN_22,PLB_IN_23,PLB_IN_24,PLB_IN_25,PLB_IN_26,PLB_IN_27,PLB_IN_28,PLB_IN_29,PLB_IN_30,PLB_IN_31,MOT_GPIO0,MOT_GPIO1,MOT_GPIO2,MOT_GPIO3,MOT_GPIO4,MOT_GPIO5,MOT_GPIO6,MOT_GPIO7,PWM_IN8,PWM_IN9,PWM_IN10,PWM_IN11,PWM_IN12,PWM_IN13,PWM_IN14,PWM_IN15,PWM0_FRCI,PWM0_FRCSYNCI,PWM0_SYNCI,PWM0_SHRLDSYNCI,PWM0_FAULTI0,PWM0_FAULTI1,PWM1_FRCI,PWM1_FRCSYNCI,PWM1_SYNCI,PWM1_SHRLDSYNCI,PWM1_FAULTI0,PWM1_FAULTI1,RDC_TRIG_IN0,RDC_TRIG_IN1,SYNCTIMER_TRIG,QEI0_TRIG_IN,QEI1_TRIG_IN,QEI0_PAUSE,QEI1_PAUSE,UART_TRIG0,UART_TRIG1,TRGM_IRQ0,TRGM_IRQ1,TRGM_DMA0,TRGM_DMA1 + TRGOCFG[%s] + no description available + 0x100 + 32 + 0x00000000 + 0x00000E7F + + + OUTINV + 1- Invert the output + 11 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 10 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 9 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + 8 + 0x4 + 0,1,2,3,4,5,6,7 + DMACFG[%s] + no description available + 0x400 + 32 + 0x00000000 + 0x8000003F + + + DMAMUX_EN + No description available + 31 + 1 + read-write + + + DMASRCSEL + This field selects one of the DMA requests as the DMA request output. + 0 + 6 + read-write + + + + + GCR + General Control Register + 0x500 + 32 + 0x00000000 + 0x000000FF + + + TRGOPEN + The bitfield enable the TRGM outputs. + 0 + 8 + read-write + + + + + ADC_MATRIX_SEL + adc matrix select register + 0x510 + 32 + 0x00000000 + 0xFFFFFFFF + + + QEI1_ADC1_SEL + 0-adc0; 1-adc1; 2-rdc_adc0; 3-rdc_adc1; +bit7 is used to invert adc_value; +others reserved + 24 + 8 + read-write + + + QEI1_ADC0_SEL + No description available + 16 + 8 + read-write + + + QEI0_ADC1_SEL + No description available + 8 + 8 + read-write + + + QEI0_ADC0_SEL + No description available + 0 + 8 + read-write + + + + + DAC_MATRIX_SEL + dac matrix select register + 0x514 + 32 + 0x00000000 + 0xFFFFFFFF + + + DAC1_DAC_SEL + 0-qeo0_dac0; 1-qeo0_dac1; 2-qeo0_dac2; +3-qeo1_dac0; 4-qeo1_dac1; 5-qeo1_dac2; +6-rdc_dac0; 7-rdc_dac1; +bit7 is used to invert dac_value; +others reserved + 24 + 8 + read-write + + + DAC0_DAC_SEL + No description available + 16 + 8 + read-write + + + ACMP1_DAC_SEL + No description available + 8 + 8 + read-write + + + ACMP0_DAC_SEL + No description available + 0 + 8 + read-write + + + + + POS_MATRIX_SEL0 + position matrix select register0 + 0x518 + 32 + 0x00000000 + 0xFFFFFFFF + + + MMC1_POSIN_SEL + 0-sei_pos_out0; 1-sei_pos_out1; +2-qei0_pos; 3-qei1_pos; +4-mmc0_pos_out0; 5-mmc0_pos_out1; +6-mmc1_pos_out0; 7-mmc1_pos_out1; +bit7 is used to invert position value; + others reserved + 24 + 8 + read-write + + + MMC0_POSIN_SEL + No description available + 16 + 8 + read-write + + + SEI_POSIN1_SEL + No description available + 8 + 8 + read-write + + + SEI_POSIN0_SEL + No description available + 0 + 8 + read-write + + + + + POS_MATRIX_SEL1 + position matrix select register1 + 0x51c + 32 + 0x00000000 + 0x0000FFFF + + + QEO1_POS_SEL + No description available + 8 + 8 + read-write + + + QEO0_POS_SEL + No description available + 0 + 8 + read-write + + + + + 4 + 0x4 + 0,1,2,3 + TRGM_IN[%s] + no description available + 0x600 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRGM_IN + mmc1_trig_out[1:0], mmc0_trig_out[1:0],sync_pulse[3:0],moto_gpio_in_sync[7:0],//31:16 + gtmr3_to_motor_sync[1:0],gtmr2_to_motor_sync[1:0],gtmr1_to_motor_sync[1:0],gtmr0_to_motor_sync[1:0], //15:8 + acmp_out_sync[1:0],can2mot_event_sync[1:0],usb0_sof_tog_sync,pwm_debug,1'b1,1'b0 //7:0 + 0 + 32 + read-only + + + + + 5 + 0x4 + 0,1,2,3,4 + TRGM_OUT[%s] + no description available + 0x620 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRGM_OUT + motor_to_opamp0[7:0] = trig_mux_out[7:0]; +motor_to_opamp1[7:0] = trig_mux_out[15:8]; +motor_to_gtmr0_capt[1:0] = trig_mux_out[17:16]; +motor_to_gtmr0_sync = trig_mux_out[18]; +motor_to_gtmr1_capt[1:0] = trig_mux_out[20:19]; +motor_to_gtmr1_sync = trig_mux_out[21]; +motor_to_gtmr2_capt[1:0] = trig_mux_out[23:22]; +motor_to_gtmr2_sync = trig_mux_out[24]; +motor_to_gtmr3_capt[1:0] = trig_mux_out[26:25]; +motor_to_gtmr3_sync = trig_mux_out[27]; +acmp_window[1:0] = trig_mux_out[29:28]; +dac0_buf_trigger = trig_mux_out[30]; +dac1_buf_trigger = trig_mux_out[31]; +dac0_step_trigger[3:0] = {trig_mux_out[24:22],trig_mux_out[30]};//use same buf_trig, and gtmr2 +dac1_step_trigger[3:0] = {trig_mux_out[27:25],trig_mux_out[31]}; //use same buf_trig, and gtmr3 + 0 + 32 + read-only + + + + + + + USB0 + USB0 + USB + 0xf300c000 + + 0x80 + 0x1a8 + registers + + + + GPTIMER0LD + General Purpose Timer #0 Load Register + 0x80 + 32 + 0x00000000 + 0x00FFFFFF + + + GPTLD + GPTLD +General Purpose Timer Load Value +These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. +This value represents the time in microseconds minus 1 for the timer duration. +Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. +NOTE: Max value is 0xFFFFFF or 16.777215 seconds. + 0 + 24 + read-write + + + + + GPTIMER0CTRL + General Purpose Timer #0 Controller Register + 0x84 + 32 + 0x00000000 + 0xC1FFFFFF + + + GPTRUN + GPTRUN +General Purpose Timer Run +GPTCNT bits are not effected when setting or clearing this bit. +0 - Stop counting +1 - Run + 31 + 1 + read-write + + + GPTRST + GPTRST +General Purpose Timer Reset +0 - No action +1 - Load counter value from GPTLD bits in n_GPTIMER0LD + 30 + 1 + write-only + + + GPTMODE + GPTMODE +General Purpose Timer Mode +In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is +reset by software; +In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the +counter value from GPTLD bits to start again. +0 - One Shot Mode +1 - Repeat Mode + 24 + 1 + read-write + + + GPTCNT + GPTCNT +General Purpose Timer Counter. +This field is the count value of the countdown timer. + 0 + 24 + read-only + + + + + GPTIMER1LD + General Purpose Timer #1 Load Register + 0x88 + 32 + 0x00000000 + 0x00FFFFFF + + + GPTLD + GPTLD +General Purpose Timer Load Value +These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. +This value represents the time in microseconds minus 1 for the timer duration. +Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. +NOTE: Max value is 0xFFFFFF or 16.777215 seconds. + 0 + 24 + read-write + + + + + GPTIMER1CTRL + General Purpose Timer #1 Controller Register + 0x8c + 32 + 0x00000000 + 0xC1FFFFFF + + + GPTRUN + GPTRUN +General Purpose Timer Run +GPTCNT bits are not effected when setting or clearing this bit. +0 - Stop counting +1 - Run + 31 + 1 + read-write + + + GPTRST + GPTRST +General Purpose Timer Reset +0 - No action +1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD + 30 + 1 + write-only + + + GPTMODE + GPTMODE +General Purpose Timer Mode +In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is +reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and +automatically reload the counter value from GPTLD bits to start again. +0 - One Shot Mode +1 - Repeat Mode + 24 + 1 + read-write + + + GPTCNT + GPTCNT +General Purpose Timer Counter. +This field is the count value of the countdown timer. + 0 + 24 + read-only + + + + + SBUSCFG + System Bus Config Register + 0x90 + 32 + 0x00000000 + 0x00000007 + + + AHBBRST + AHBBRST +AHB master interface Burst configuration +These bits control AHB master transfer type sequence (or priority). +NOTE: This register overrides n_BURSTSIZE register when its value is not zero. +000 - Incremental burst of unspecified length only +001 - INCR4 burst, then single transfer +010 - INCR8 burst, INCR4 burst, then single transfer +011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer +100 - Reserved, don't use +101 - INCR4 burst, then incremental burst of unspecified length +110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length +111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length + 0 + 3 + read-write + + + + + USBCMD + USB Command Register + 0x140 + 32 + 0x00080000 + 0x00FFFB7F + + + ITC + ITC +Interrupt Threshold Control -Read/Write. +The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. +ITC contains the maximum interrupt interval measured in micro-frames. Valid values are +shown below. +Value Maximum Interrupt Interval +00000000 - Immediate (no threshold) +00000001 - 1 micro-frame +00000010 - 2 micro-frames +00000100 - 4 micro-frames +00001000 - 8 micro-frames +00010000 - 16 micro-frames +00100000 - 32 micro-frames +01000000 - 64 micro-frames + 16 + 8 + read-write + + + FS_2 + FS_2 +Frame List Size - (Read/Write or Read Only). [host mode only] +This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. +This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. +NOTE: This field is made up from USBCMD bits 15, 3 and 2. +Value Meaning +0b000 - 1024 elements (4096 bytes) Default value +0b001 - 512 elements (2048 bytes) +0b010 - 256 elements (1024 bytes) +0b011 - 128 elements (512 bytes) +0b100 - 64 elements (256 bytes) +0b101 - 32 elements (128 bytes) +0b110 - 16 elements (64 bytes) +0b111 - 8 elements (32 bytes) + 15 + 1 + read-write + + + ATDTW + ATDTW +Add dTD TripWire - Read/Write. [device mode only] +This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's +linked list. This bit is set and cleared by software. +This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD +to a primed endpoint may go unrecognized. + 14 + 1 + read-write + + + SUTW + SUTW +Setup TripWire - Read/Write. [device mode only] +This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. +If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then +there is a hazard when new setup data arrives while the DCD is copying the setup data payload +from the QH for a previous setup packet. This bit is set and cleared by software. +This bit would also be cleared by hardware when a hazard detected. + 13 + 1 + read-write + + + PRM + Asynchronous Schedule start- Write only， host mode only。 +this bit is used to notify hostcontroller to start async schedule immediately. + 12 + 1 + write-only + + + ASPE + ASPE +Asynchronous Schedule Park Mode Enable - Read/Write. +If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. +Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. +When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. +NOTE: ASPE bit reset value: '0b' for OTG controller . + 11 + 1 + read-write + + + ASP + ASP +Asynchronous Schedule Park Mode Count - Read/Write. +If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. +It contains a count of the number of successive transactions the host controller is allowed to +execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. +Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. +This field is set to 3h in all controller core. + 8 + 2 + read-write + + + IAA + IAA +Interrupt on Async Advance Doorbell - Read/Write. +This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. +When the host controller has evicted all appropriate cached schedule states, +it sets the Interrupt on Async Advance status bit in the USBSTS register. +If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. +The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. +Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. +This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. + 6 + 1 + read-write + + + ASE + ASE +Asynchronous Schedule Enable - Read/Write. Default 0b. +This bit controls whether the host controller skips processing the Asynchronous Schedule. +Only the host controller uses this bit. +Values Meaning +0 - Do not process the Asynchronous Schedule. +1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. + 5 + 1 + read-write + + + PSE + PSE +Periodic Schedule Enable- Read/Write. Default 0b. +This bit controls whether the host controller skips processing the Periodic Schedule. +Only the host controller uses this bit. +Values Meaning +0 - Do not process the Periodic Schedule +1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. + 4 + 1 + read-write + + + FS_1 + FS_1 +See description at bit 15 + 2 + 2 + read-write + + + RST + RST +Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. +This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. +Host operation mode: +When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. +Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. +Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. +Attempting to reset an actively running host controller will result in undefined behavior. +Device operation mode: +When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. +Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. +In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. + 1 + 1 + read-write + + + RS + RS +Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. +Host operation mode: +When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. +When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. +The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. +Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). +Device operation mode: +Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. +This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. +Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. + 0 + 1 + read-write + + + + + USBSTS + USB Status Register + 0x144 + 32 + 0x00000000 + 0x030DF1FF + + + TI1 + TI1 +General Purpose Timer Interrupt 1(GPTINT1)--R/WC. +This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this +bit will clear it. + 25 + 1 + read-write + + + TI0 + TI0 +General Purpose Timer Interrupt 0(GPTINT0)--R/WC. +This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this +bit clears it. + 24 + 1 + read-write + + + UPI + USB Host Periodic Interrupt – RWC. Default = 0b. +This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction +where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. +This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. +A short packet is when the actual number of bytes received was less than expected. +This bit is not used by the device controller and will always be zero. + 19 + 1 + read-write + + + UAI + USB Host Asynchronous Interrupt – RWC. Default = 0b. +This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction +where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. +This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. +A short packet is when the actual number of bytes received was less than expected. +This bit is not used by the device controller and will always be zero + 18 + 1 + read-write + + + NAKI + NAKI +NAK Interrupt Bit--RO. +This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and +corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware +when all Enabled TX/RX Endpoint NAK bits are cleared. + 16 + 1 + read-only + + + AS + AS +Asynchronous Schedule Status - Read Only. +This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. +The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. +When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). +Only used in the host operation mode. + 15 + 1 + read-only + + + PS + PS +Periodic Schedule Status - Read Only. +This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. +The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. +When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). +Only used in the host operation mode. + 14 + 1 + read-only + + + RCL + RCL +Reclamation - Read Only. +This is a read-only status bit used to detect an empty asynchronous schedule. +Only used in the host operation mode. + 13 + 1 + read-only + + + HCH + HCH +HCHaIted - Read Only. +This bit is a zero whenever the Run/Stop bit is a one. + The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, + either by software or by the Controller hardware (for example, an internal error). +Only used in the host operation mode. +Default value is '0b' for OTG core . +This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE +register. +NOTE: HCH bit reset value: '0b' for OTG controller core . + 12 + 1 + read-only + + + SLI + SLI +DCSuspend - R/WC. +When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. +Only used in device operation mode. + 8 + 1 + read-write + + + SRI + SRI +SOF Received - R/WC. +When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. +When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. +Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. +Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. +In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. +Software writes a 1 to this bit to clear it. + 7 + 1 + read-write + + + URI + URI +USB Reset Received - R/WC. +When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. +Software can write a 1 to this bit to clear the USB Reset Received status bit. +Only used in device operation mode. + 6 + 1 + read-write + + + AAI + AAI +Interrupt on Async Advance - R/WC. +System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule +by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. +Only used in host operation mode. + 5 + 1 + read-write + + + SEI + System Error – RWC. Default = 0b. +In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. +In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) + 4 + 1 + read-write + + + FRI + FRI +Frame List Rollover - R/WC. +The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to +zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the +frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the +Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host +Controller sets this bit to a one every time FHINDEX [12] toggles. +Only used in host operation mode. + 3 + 1 + read-write + + + PCI + PCI +Port Change Detect - R/WC. +The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, +or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. +The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. +When the port controller exits the full or high-speed operation states due to Reset or Suspend events, +the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. + 2 + 1 + read-write + + + UEI + UEI +USB Error Interrupt (USBERRINT) - R/WC. +When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. +This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. + 1 + 1 + read-write + + + UI + UI +USB Interrupt (USBINT) - R/WC. +This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB +transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. +This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when +the actual number of bytes received was less than the expected number of bytes. + 0 + 1 + read-write + + + + + USBINTR + Interrupt Enable Register + 0x148 + 32 + 0x00000000 + 0x030D01FF + + + TIE1 + TIE1 +General Purpose Timer #1 Interrupt Enable +When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. + 25 + 1 + read-write + + + TIE0 + TIE0 +General Purpose Timer #0 Interrupt Enable +When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. + 24 + 1 + read-write + + + UPIE + UPIE +USB Host Periodic Interrupt Enable +When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an +interrupt at the next interrupt threshold. + 19 + 1 + read-write + + + UAIE + UAIE +USB Host Asynchronous Interrupt Enable +When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an +interrupt at the next interrupt threshold. + 18 + 1 + read-write + + + NAKE + NAKE +NAK Interrupt Enable +When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. + 16 + 1 + read-only + + + SLE + SLE +Sleep Interrupt Enable +When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. +Only used in device operation mode. + 8 + 1 + read-write + + + SRE + SRE +SOF Received Interrupt Enable +When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. + 7 + 1 + read-write + + + URE + URE +USB Reset Interrupt Enable +When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in device operation mode. + 6 + 1 + read-write + + + AAE + AAE +Async Advance Interrupt Enable +When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in host operation mode. + 5 + 1 + read-write + + + SEE + SEE +System Error Interrupt Enable +When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in host operation mode. + 4 + 1 + read-write + + + FRE + FRE +Frame List Rollover Interrupt Enable +When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in host operation mode. + 3 + 1 + read-write + + + PCE + PCE +Port Change Detect Interrupt Enable +When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. + 2 + 1 + read-write + + + UEE + UEE +USB Error Interrupt Enable +When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. + 1 + 1 + read-write + + + UE + UE +USB Interrupt Enable +When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. + 0 + 1 + read-write + + + + + FRINDEX + USB Frame Index Register + 0x14c + 32 + 0x00000000 + 0x00003FFF + + + FRINDEX + FRINDEX +Frame Index. +The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. +This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. +The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. +USBCMD [Frame List Size] Number Elements N +In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. +In either mode bits 2:0 indicate the current microframe. +The bit field values description below is represented as (Frame List Size) Number Elements N. +00000000000000 - (1024) 12 +00000000000001 - (512) 11 +00000000000010 - (256) 10 +00000000000011 - (128) 9 +00000000000100 - (64) 8 +00000000000101 - (32) 7 +00000000000110 - (16) 6 +00000000000111 - (8) 5 + 0 + 14 + read-write + + + + + DEVICEADDR + Device Address Register + UNION_154 + 0x154 + 32 + 0x00000000 + 0xFF000000 + + + USBADR + USBADR +Device Address. +These bits correspond to the USB device address + 25 + 7 + read-write + + + USBADRA + USBADRA +Device Address Advance. Default=0. +When this bit is '0', any writes to USBADR are instantaneous. + When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. +After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. +Hardware will automatically clear this bit on the following conditions: +1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). +2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). +3) Device Reset occurs (USBADR is reset to 0). +NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. +This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. +If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), +the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. + 24 + 1 + read-write + + + + + PERIODICLISTBASE + Frame List Base Address Register + UNION_154 + 0x154 + 32 + 0x00000000 + 0xFFFFF000 + + + BASEADR + BASEADR +Base Address (Low). +These bits correspond to memory address signals [31:12], respectively. +Only used by the host controller. + 12 + 20 + read-write + + + + + ASYNCLISTADDR + Next Asynch. Address Register + UNION_158 + 0x158 + 32 + 0x00000000 + 0xFFFFFFE0 + + + ASYBASE + ASYBASE +Link Pointer Low (LPL). +These bits correspond to memory address signals [31:5], respectively. This field may only reference a +Queue Head (QH). +Only used by the host controller. + 5 + 27 + read-write + + + + + ENDPTLISTADDR + Endpoint List Address Register + UNION_158 + 0x158 + 32 + 0x00000000 + 0xFFFFF800 + + + EPBASE + EPBASE +Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. +This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). + 11 + 21 + read-write + + + + + BURSTSIZE + Programmable Burst Size Register + 0x160 + 32 + 0x00000000 + 0x0000FFFF + + + TXPBURST + TXPBURST +Programmable TX Burst Size. +Default value is determined by TXBURST bits in n_HWTXBUF. +This register represents the maximum length of a the burst in 32-bit words while moving data from system +memory to the USB bus. + 8 + 8 + read-write + + + RXPBURST + RXPBURST +Programmable RX Burst Size. +Default value is determined by TXBURST bits in n_HWRXBUF. +This register represents the maximum length of a the burst in 32-bit words while moving data from the +USB bus to system memory. + 0 + 8 + read-write + + + + + TXFILLTUNING + TX FIFO Fill Tuning Register + 0x164 + 32 + 0x00000000 + 0x003F1F7F + + + TXFIFOTHRES + TXFIFOTHRES +FIFO Burst Threshold. (Read/Write) +This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. +The minimum value is 2 and this value should be a low as possible to maximize USB performance. +A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth +where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. +This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. + 16 + 6 + read-write + + + TXSCHHEALTH + TXSCHHEALTH +Scheduler Health Counter. (Read/Write To Clear) +Table continues on the next page +This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES +before running out of time to send the packet before the next Start-Of-Frame. +This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. +Writing to this register will clear the counter and this counter will max. at 31. + 8 + 5 + read-write + + + TXSCHOH + TXSCHOH +Scheduler Overhead. (Read/Write) [Default = 0] +This register adds an additional fixed offset to the schedule time estimator described above as Tff. +As an approximation, the value chosen for this register should limit the number of back-off events captured +in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. +Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. +The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. +The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. +Default value is '08h' for OTG controller core . + 0 + 7 + read-write + + + + + ENDPTNAK + Endpoint NAK Register + 0x178 + 32 + 0x00000000 + 0xFFFFFFFF + + + EPTN + EPTN +TX Endpoint NAK - R/WC. +Each TX endpoint has 1 bit in this field. The bit is set when the +device sends a NAK handshake on a received IN token for the corresponding endpoint. +Bit [N] - Endpoint #[N], N is 0-7 + 16 + 16 + read-write + + + EPRN + EPRN +RX Endpoint NAK - R/WC. +Each RX endpoint has 1 bit in this field. The bit is set when the +device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. +Bit [N] - Endpoint #[N], N is 0-7 + 0 + 16 + read-write + + + + + ENDPTNAKEN + Endpoint NAK Enable Register + 0x17c + 32 + 0x00000000 + 0xFFFFFFFF + + + EPTNE + EPTNE +TX Endpoint NAK Enable - R/W. +Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the +corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. +Bit [N] - Endpoint #[N], N is 0-7 + 16 + 16 + read-write + + + EPRNE + EPRNE +RX Endpoint NAK Enable - R/W. +Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the +corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. +Bit [N] - Endpoint #[N], N is 0-7 + 0 + 16 + read-write + + + + + PORTSC1 + Port Status & Control + 0x184 + 32 + 0x00000000 + 0x3DFF1FFF + + + STS + STS +Serial Transceiver Select +1 Serial Interface Engine is selected +0 Parallel Interface signals is selected +Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. +When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. + 29 + 1 + read-write + + + PTW + PTW +Parallel Transceiver Width +This bit has no effect if serial interface engine is used. +0 - Select the 8-bit UTMI interface [60MHz] +1 - Select the 16-bit UTMI interface [30MHz] + 28 + 1 + read-write + + + PSPD + PSPD +Port Speed - Read Only. +This register field indicates the speed at which the port is operating. +00 - Full Speed +01 - Low Speed +10 - High Speed +11 - Undefined + 26 + 2 + read-only + + + PFSC + PFSC +Port Force Full Speed Connect - Read/Write. Default = 0b. +When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp +sequence that allows the port to identify itself as High Speed. +0 - Normal operation +1 - Forced to full speed + 24 + 1 + read-write + + + PHCD + PHCD +PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. +When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY +clock. +NOTE: The PHY clock cannot be disabled if it is being used as the system clock. +In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD +Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend +will be cleared automatically when the host initials resume. Before forcing a resume from the device, the +device controller driver must clear this bit. +In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put +into suspend mode or when no downstream device is connected. Low power suspend is completely +under the control of software. +0 - Enable PHY clock +1 - Disable PHY clock + 23 + 1 + read-write + + + WKOC + WKOC +Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. +Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. +This field is zero if Port Power(PORTSC1) is zero. + 22 + 1 + read-write + + + WKDC + WKDC +Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables +the port to be sensitive to device disconnects as wake-up events. +This field is zero if Port Power(PORTSC1) is zero or in device mode. + 21 + 1 + read-write + + + WKCN + WKCN +Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. +Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. +This field is zero if Port Power(PORTSC1) is zero or in device mode. + 20 + 1 + read-write + + + PTC + PTC +Port Test Control - Read/Write. Default = 0000b. +Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. +The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. +Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. +Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. +NOTE: Low speed operations are not supported as a peripheral device. +Any other value than zero indicates that the port is operating in test mode. +Value Specific Test +0000 - TEST_MODE_DISABLE +0001 - J_STATE +0010 - K_STATE +0011 - SE0 (host) / NAK (device) +0100 - Packet +0101 - FORCE_ENABLE_HS +0110 - FORCE_ENABLE_FS +0111 - FORCE_ENABLE_LS +1000-1111 - Reserved + 16 + 4 + read-write + + + PP + PP +Port Power (PP)-Read/Write or Read Only. +The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: +PPC +PP Operation +0 +1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. +1 +1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). +When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. +When an over-current condition is detected on a powered port and PPC is a one, +the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). +This feature is implemented in all controller cores (PPC = 1). + 12 + 1 + read-write + + + LS + LS +Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal +lines. +In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because +the port controller state machine and the port routing manage the connection of LS and FS. +In device mode, the use of linestate by the device controller driver is not necessary. +The encoding of the bits are: +Bits [11:10] Meaning +00 - SE0 +01 - K-state +10 - J-state +11 - Undefined + 10 + 2 + read-only + + + HSP + HSP +High-Speed Port - Read Only. Default = 0b. +When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the +host/device connected to the port is not in a high-speed mode. +NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. + 9 + 1 + read-only + + + PR + PR +Port Reset - Read/Write or Read Only. Default = 0b. +In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. +When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. +This bit will automatically change to zero after the reset sequence is complete. +This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. +In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. + 8 + 1 + read-write + + + SUSP + SUSP +Suspend - Read/Write or Read Only. Default = 0b. +1=Port in suspend state. 0=Port not in suspend state. +In Host Mode: Read/Write. +Port Enabled Bit and Suspend bit of this register define the port states as follows: +Bits [Port Enabled, Suspend] Port State +0x Disable +10 Enable +11 Suspend +When in suspend state, downstream propagation of data is blocked on this port, except for port reset. +The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. +In the suspend state, the port is sensitive to resume detection. +Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. +The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. +If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: Read Only. +In device mode this bit is a read only status bit. + 7 + 1 + read-write + + + FPR + FPR +Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. +In Host Mode: +Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. +When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. +This bit will automatically change to zero after the resume sequence is complete. +This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. +Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. +The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. +Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. +This field is zero if Port Power(PORTSC1) is zero in host mode. +This bit is not-EHCI compatible. +In Device mode: +After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. +The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. +The bit will be cleared when the device returns to normal operation. + Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. + 6 + 1 + read-write + + + OCC + OCC +Over-current Change-R/WC. Default=0. +This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. + 5 + 1 + read-write + + + OCA + OCA +Over-current Active-Read Only. Default 0. +This bit will automatically transition from one to zero when the over current condition is removed. +0 - This port does not have an over-current condition. +1 - This port currently has an over-current condition + 4 + 1 + read-only + + + PEC + PEC +Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. +In Host Mode: +For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or +due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). +Software clears this by writing a one to it. +This field is zero if Port Power(PORTSC1) is zero. +In Device mode: +The device port is always enabled, so this bit is always '0b'. + 3 + 1 + read-write + + + PE + PE +Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. +In Host Mode: +Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. +Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. +Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. +When the port is disabled, (0b) downstream propagation of data is blocked except for reset. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: +The device port is always enabled, so this bit is always '1b'. + 2 + 1 + read-write + + + CSC + CSC +Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. +In Host Mode: +Indicates a change has occurred in the port's Current Connect Status. +The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. +For example, the insertion status changes twice before system software has cleared the changed condition, +hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: +This bit is undefined in device controller mode. + 1 + 1 + read-write + + + CCS + CCS +Current Connect Status-Read Only. +In Host Mode: +1=Device is present on port. 0=No device is present. Default = 0. +This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: +1=Attached. 0=Not Attached. Default=0. +A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. +A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. +It does not state the device being disconnected or Suspended. + 0 + 1 + read-write + + + + + OTGSC + On-The-Go Status & control Register + 0x1a4 + 32 + 0x00000000 + 0x07070723 + + + ASVIE + ASVIE +A Session Valid Interrupt Enable - Read/Write. + 26 + 1 + read-write + + + AVVIE + AVVIE +A VBus Valid Interrupt Enable - Read/Write. +Setting this bit enables the A VBus valid interrupt. + 25 + 1 + read-write + + + IDIE + IDIE +USB ID Interrupt Enable - Read/Write. +Setting this bit enables the USB ID interrupt. + 24 + 1 + read-write + + + ASVIS + ASVIS +A Session Valid Interrupt Status - Read/Write to Clear. +This bit is set when VBus has either risen above or fallen below the A session valid threshold. +Software must write a one to clear this bit. + 18 + 1 + read-write + + + AVVIS + AVVIS +A VBus Valid Interrupt Status - Read/Write to Clear. +This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. +Software must write a one to clear this bit. + 17 + 1 + read-write + + + IDIS + IDIS +USB ID Interrupt Status - Read/Write. +This bit is set when a change on the ID input has been detected. +Software must write a one to clear this bit. + 16 + 1 + read-write + + + ASV + ASV +A Session Valid - Read Only. +Indicates VBus is above the A session valid threshold. + 10 + 1 + read-only + + + AVV + AVV +A VBus Valid - Read Only. +Indicates VBus is above the A VBus valid threshold. + 9 + 1 + read-only + + + ID + ID +USB ID - Read Only. +0 = A device, 1 = B device + 8 + 1 + read-only + + + IDPU + IDPU +ID Pullup - Read/Write +This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input +will not be sampled. + 5 + 1 + read-write + + + VC + VC +VBUS Charge - Read/Write. +Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. + 1 + 1 + read-write + + + VD + VD +VBUS_Discharge - Read/Write. +Setting this bit causes VBus to discharge through a resistor. + 0 + 1 + read-write + + + + + USBMODE + USB Device Mode Register + 0x1a8 + 32 + 0x00000000 + 0x0000001F + + + SDIS + SDIS +Stream Disable Mode. (0 - Inactive [default]; 1 - Active) +Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. +This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. +Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. +Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems +where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. +NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for +the scheduler when using this feature. +NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. + 4 + 1 + read-write + + + SLOM + SLOM +Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . +0 - Setup Lockouts On (default); +1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. + 3 + 1 + read-write + + + ES + ES +Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the +host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected +by the value of this bit because they are based upon the 32-bit word. +Bit Meaning +0 - Little Endian [Default] +1 - Big Endian + 2 + 1 + read-write + + + CM + CM +Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only +implementations. For those designs that contain both host & device capability, the controller defaults to +an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ +device controllers, this register can only be written once after reset. If it is necessary to switch modes, +software must reset the controller by writing to the RESET bit in the USBCMD register before +reprogramming this register. +For OTG controller core, reset value is '00b'. +00 - Idle [Default for combination host/device] +01 - Reserved +10 - Device Controller [Default for device only controller] +11 - Host Controller [Default for host only controller] + 0 + 2 + read-write + + + + + ENDPTSETUPSTAT + Endpoint Setup Status Register + 0x1ac + 32 + 0x00000000 + 0x0000FFFF + + + ENDPTSETUPSTAT + ENDPTSETUPSTAT +Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. +Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. +The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. +This register is only used in device mode. + 0 + 16 + read-write + + + + + ENDPTPRIME + Endpoint Prime Register + 0x1b0 + 32 + 0x00000000 + 0xFFFFFFFF + + + PETB + PETB +Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a +buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. +Software should write a one to the corresponding bit when posting a new transfer descriptor to an +endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor +from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated +endpoint(s) is (are) successfully primed. +NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD +is retired, and the dQH is updated. +PETB[N] - Endpoint #N, N is in 0..7 + 16 + 16 + read-write + + + PERB + PERB +Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. +Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. +Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. +Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. +NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD +is retired, and the dQH is updated. +PERB[N] - Endpoint #N, N is in 0..7 + 0 + 16 + read-write + + + + + ENDPTFLUSH + Endpoint Flush Register + 0x1b4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FETB + FETB +Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. +If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. +Hardware clears this register after the endpoint flush operation is successful. +FETB[N] - Endpoint #N, N is in 0..7 + 16 + 16 + read-write + + + FERB + FERB +Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. + If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. +Hardware clears this register after the endpoint flush operation is successful. +FERB[N] - Endpoint #N, N is in 0..7 + 0 + 16 + read-write + + + + + ENDPTSTAT + Endpoint Status Register + 0x1b8 + 32 + 0x00000000 + 0xFFFFFFFF + + + ETBR + ETBR +Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. +This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. +There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. +This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. +Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. +NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. +ETBR[N] - Endpoint #N, N is in 0..7 + 16 + 16 + read-only + + + ERBR + ERBR +Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective +endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a +corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the +ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB +traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the +USB DMA system, or through the ENDPTFLUSH register. +NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations +when a dTD is retired, and the dQH is updated. +ERBR[N] - Endpoint #N, N is in 0..7 + 0 + 16 + read-only + + + + + ENDPTCOMPLETE + Endpoint Complete Register + 0x1bc + 32 + 0x00000000 + 0xFFFFFFFF + + + ETCE + ETCE +Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. +If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. +ETCE[N] - Endpoint #N, N is in 0..7 + 16 + 16 + read-write + + + ERCE + ERCE +Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred +and software should read the corresponding endpoint queue to determine the transfer status. If the +corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the +USBINT . Writing one clears the corresponding bit in this register. +ERCE[N] - Endpoint #N, N is in 0..7 + 0 + 16 + read-write + + + + + 16 + 0x4 + ENDPTCTRL0,ENDPTCTRL1,ENDPTCTRL2,ENDPTCTRL3,ENDPTCTRL4,ENDPTCTRL5,ENDPTCTRL6,ENDPTCTRL7,ENDPTCTRL8,ENDPTCTRL9,ENDPTCTRL10,ENDPTCTRL11,ENDPTCTRL12,ENDPTCTRL13,ENDPTCTRL14,ENDPTCTRL15 + ENDPTCTRL[%s] + no description available + 0x1c0 + 32 + 0x00000000 + 0x00CD00CD + + + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 + read-write + + + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 + 1 + write-only + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 + read-write + + + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured +as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 + 1 + read-write + + + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 + 1 + read-write + + + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 + 1 + write-only + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 + read-write + + + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 + 1 + read-write + + + + + OTG_CTRL0 + No description available + 0x200 + 32 + 0x00000000 + 0x020B3F90 + + + OTG_WKDPDMCHG_EN + No description available + 25 + 1 + read-write + + + AUTORESUME_EN + No description available + 19 + 1 + read-write + + + OTG_VBUS_WAKEUP_EN + No description available + 17 + 1 + read-write + + + OTG_ID_WAKEUP_EN + No description available + 16 + 1 + read-write + + + OTG_VBUS_SOURCE_SEL + No description available + 13 + 1 + read-write + + + OTG_UTMI_SUSPENDM_SW + default 0 for naneng usbphy + 12 + 1 + read-write + + + OTG_UTMI_RESET_SW + default 1 for naneng usbphy + 11 + 1 + read-write + + + OTG_WAKEUP_INT_ENABLE + No description available + 10 + 1 + read-write + + + OTG_POWER_MASK + No description available + 9 + 1 + read-write + + + OTG_OVER_CUR_POL + No description available + 8 + 1 + read-write + + + OTG_OVER_CUR_DIS + No description available + 7 + 1 + read-write + + + SER_MODE_SUSPEND_EN + for naneng usbphy, only switch to serial mode when suspend + 4 + 1 + read-write + + + + + PHY_CTRL0 + No description available + 0x210 + 32 + 0x00000000 + 0x02007007 + + + GPIO_ID_SEL_N + No description available + 25 + 1 + read-write + + + ID_DIG_OVERRIDE + No description available + 14 + 1 + read-write + + + SESS_VALID_OVERRIDE + No description available + 13 + 1 + read-write + + + VBUS_VALID_OVERRIDE + No description available + 12 + 1 + read-write + + + ID_DIG_OVERRIDE_EN + No description available + 2 + 1 + read-write + + + SESS_VALID_OVERRIDE_EN + No description available + 1 + 1 + read-write + + + VBUS_VALID_OVERRIDE_EN + No description available + 0 + 1 + read-write + + + + + PHY_CTRL1 + No description available + 0x214 + 32 + 0x00000000 + 0x00100002 + + + UTMI_CFG_RST_N + No description available + 20 + 1 + read-write + + + UTMI_OTG_SUSPENDM + OTG suspend, not utmi_suspendm + 1 + 1 + read-write + + + + + TOP_STATUS + No description available + 0x220 + 32 + 0x00000000 + 0x80000000 + + + WAKEUP_INT_STATUS + No description available + 31 + 1 + read-write + + + + + PHY_STATUS + No description available + 0x224 + 32 + 0x00000000 + 0x800000F5 + + + UTMI_CLK_VALID + No description available + 31 + 1 + read-write + + + LINE_STATE + No description available + 6 + 2 + read-write + + + HOST_DISCONNECT + No description available + 5 + 1 + read-write + + + ID_DIG + No description available + 4 + 1 + read-write + + + UTMI_SESS_VALID + No description available + 2 + 1 + read-write + + + VBUS_VALID + No description available + 0 + 1 + read-write + + + + + + + SDP + SDP + SDP + 0xf3040000 + + 0x0 + 0x60 + registers + + + + SDPCR + SDP control register + 0x0 + 32 + 0x30000000 + 0xFFFE0101 + + + SFTRST + soft reset. +Write 1 then 0, to reset the SDP block. + 31 + 1 + read-write + + + CLKGAT + Clock Gate for the SDP main logic. +Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block. + 30 + 1 + read-write + + + CIPDIS + Cipher Disable, read the info, whether the CIPHER features is besing disable in this chip or not. +1, Cipher is disabled in this chip. +0, Cipher is enabled in this chip. + 29 + 1 + read-only + + + HASDIS + HASH Disable, read the info, whether the HASH features is besing disable in this chip or not. +1, HASH is disabled in this chip. +0, HASH is enabled in this chip. + 28 + 1 + read-only + + + CIPHEN + Cipher Enablement, controlled by SW. +1, Cipher is Enabled. +0, Cipher is Disabled. + 23 + 1 + read-write + + + HASHEN + HASH Enablement, controlled by SW. +1, HASH is Enabled. +0, HASH is Disabled. + 22 + 1 + read-write + + + MCPEN + Memory Copy Enablement, controlled by SW. +1, Memory copy is Enabled. +0, Memory copy is Disabled. + 21 + 1 + read-write + + + CONFEN + Constant Fill to memory, controlled by SW. +1, Constant fill is Enabled. +0, Constant fill is Disabled. + 20 + 1 + read-write + + + DCRPDI + Decryption Disable bit, Write to 1 to disable the decryption. + 19 + 1 + read-write + + + TSTPKT0IRQ + Test purpose for interrupt when Packet counter reachs "0", but CHAIN=1 in the current packet. + 17 + 1 + read-write + + + RDSCEN + when set to "1", the 1st data packet descriptor loacted in the register(CMDPTR, NPKTPTR, ...) +when set to "0", the 1st data packet descriptor loacted in the memeory(pointed by CMDPTR) + 8 + 1 + read-write + + + INTEN + Interrupt Enablement, controlled by SW. +1, SDP interrupt is enabled. +0, SDP interrupt is disabled. + 0 + 1 + read-write + + + + + MODCTRL + Mod control register. + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + AESALG + AES algorithem selection. +0x0 = AES 128; +0x1 = AES 256; +0x8 = SM4； +Others, reserved. + 28 + 4 + read-write + + + AESMOD + AES mode selection. +0x0 = ECB; +0x1 = CBC; +Others, reserved. + 24 + 4 + read-write + + + AESKS + AES Key Selection. +These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following: +0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key. +0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. +.... +0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key. +0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. +0x20: kman_sk0[127:0] from the key manager for AES128; AES256 will use kman_sk0[255:0] as AES key. +0x21: kman_sk0[255:128] from the key manager for AES128; not valid for AES256. +0x22: kman_sk1[127:0] from the key manager for AES128; AES256 will use kman_sk1[255:0] as AES key. +0x23: kman_sk1[255:128] from the key manager for AES128; not valid for AES256. +0x24: kman_sk2[127:0] from the key manager for AES128; AES256 will use kman_sk2[255:0] as AES key. +0x25: kman_sk2[255:128] from the key manager for AES128; not valid for AES256. +0x26: kman_sk3[127:0] from the key manager for AES128; AES256 will use kman_sk3[255:0] as AES key. +0x27: kman_sk3[255:128] from the key manager for AES128; not valid for AES256. +0x30: exip0_key[127:0] from OTP for AES128; AES256 will use exip0_key[255:0] as AES key. +0x31: exip0_key[255:128] from OTP for AES128; not valid for AES256. +0x32: exip1_key[127:0] from OTP for AES128; AES256 will use exip1_key[255:0] as AES key. +0x33: exip1_key[255:128] from OTP for AES128; not valid for AES256. +Other values, reserved. + 18 + 6 + read-write + + + AESDIR + AES direction +1x1, AES Decryption +1x0, AES Encryption. + 16 + 1 + read-write + + + HASALG + HASH Algorithem selection. +0x0 SHA1 — +0x1 CRC32 — +0x2 SHA256 — + 12 + 4 + read-write + + + CRCEN + CRC enable. +1x1, CRC is enabled. +1x0, CRC is disabled. + 11 + 1 + read-write + + + HASCHK + HASH Check Enable Bit. +1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers; +1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result. +For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words. + 10 + 1 + read-write + + + HASOUT + When hashing is enabled, this bit controls the input or output data of the AES engine is hashed. +0 INPUT HASH +1 OUTPUT HASH + 9 + 1 + read-write + + + DINSWP + Decide whether the SDP byteswaps the input data (big-endian data); +When all bits are set, the data is assumed to be in the big-endian format + 4 + 2 + read-write + + + DOUTSWP + Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format + 2 + 2 + read-write + + + KEYSWP + Decide whether the SDP byteswaps the Key (big-endian data). +When all bits are set, the data is assumed to be in the big-endian format + 0 + 2 + read-write + + + + + PKTCNT + packet counter registers. + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTVAL + This read-only field shows the current (instantaneous) value of the packet counter + 16 + 8 + read-only + + + CNTINCR + The value written to this field is added to the spacket count. + 0 + 8 + read-write + + + + + STA + Status Registers + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + TAG + packet tag. + 24 + 8 + read-only + + + IRQ + interrupt Request, requested when error happen, or when packet processing done, packet counter reach to zero. + 23 + 1 + write-only + + + CHN1PKT0 + the chain buffer "chain" bit is "1", while packet counter is "0", now, waiting for new buffer data. + 20 + 1 + write-only + + + AESBSY + AES Busy + 19 + 1 + read-only + + + HASBSY + Hashing Busy + 18 + 1 + read-only + + + PKTCNT0 + Packet Counter registers reachs to ZERO now. + 17 + 1 + write-only + + + PKTDON + Packet processing done, will trigger this itnerrrupt when the "PKTINT" bit set in the packet control word. + 16 + 1 + write-only + + + ERRSET + Working mode setup error. + 5 + 1 + write-only + + + ERRPKT + Packet head access error, or status update error. + 4 + 1 + write-only + + + ERRSRC + Source Buffer Access Error + 3 + 1 + write-only + + + ERRDST + Destination Buffer Error + 2 + 1 + write-only + + + ERRHAS + Hashing Check Error + 1 + 1 + write-only + + + ERRCHAIN + buffer chain error happen when packet's CHAIN bit=0, but the Packet counter is still not zero. + 0 + 1 + write-only + + + + + KEYADDR + Key Address + 0x10 + 32 + 0x00000040 + 0xFFFFFFFF + + + INDEX + To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. +Key index pointer. The valid indices are 0-[number_keys]. +In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses. + 16 + 8 + read-write + + + SUBWRD + Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field +increments; To write a key, the software must first write the desired key index/subword to this register. + 0 + 2 + read-write + + + + + KEYDAT + Key Data + 0x14 + 32 + 0x00000030 + 0xFFFFFFFF + + + KEYDAT + This register provides the write access to the key/key subword specified by the key index register. +Writing this location updates the selected subword for the key located at the index +specified by the key index register. The write also triggers the SUBWORD field of the +KEY register to increment to the next higher word in the key + 0 + 32 + read-write + + + + + 4 + 0x4 + CIPHIV0,CIPHIV1,CIPHIV2,CIPHIV3 + CIPHIV[%s] + no description available + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + CIPHIV + cipher initialization vector. + 0 + 32 + read-write + + + + + 8 + 0x4 + HASWRD0,HASWRD1,HASWRD2,HASWRD3,HASWRD4,HASWRD5,HASWRD6,HASWRD7 + HASWRD[%s] + no description available + 0x28 + 32 + 0x00000030 + 0xFFFFFFFF + + + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + 0 + 32 + read-write + + + + + CMDPTR + Command Pointer + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMDPTR + current command addresses the register points to the multiword +descriptor that is to be executed (or is currently being executed) + 0 + 32 + read-write + + + + + NPKTPTR + Next Packet Address Pointer + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + NPKTPTR + Next Packet Address Pointer + 0 + 32 + read-write + + + + + PKTCTL + Packet Control Registers + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTTAG + packet tag + 24 + 8 + read-write + + + CIPHIV + Load Initial Vector for the AES in this packet. + 6 + 1 + read-write + + + HASFNL + Hash Termination packet + 5 + 1 + read-write + + + HASINI + Hash Initialization packat + 4 + 1 + read-write + + + CHAIN + whether the next command pointer register must be loaded into the channel's current descriptor +pointer. + 3 + 1 + read-write + + + DCRSEMA + whether the channel's semaphore must be decremented at the end of the current operation. +When the semaphore reaches a value of zero, no more operations are issued from the channel. + 2 + 1 + read-write + + + PKTINT + Reflects whether the channel must issue an interrupt upon the completion of the packet + 1 + 1 + read-write + + + + + PKTSRC + Packet Memory Source Address + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTSRC + Packet Memory Source Address + 0 + 32 + read-write + + + + + PKTDST + Packet Memory Destination Address + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTDST + Packet Memory Destination Address + 0 + 32 + read-write + + + + + PKTBUF + Packet buffer size. + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTBUF + No description available + 0 + 32 + read-write + + + + + + + SEC + SEC + SEC + 0xf3044000 + + 0x0 + 0x18 + registers + + + + SECURE_STATE + Secure state + 0x0 + 32 + 0x00000000 + 0x000300F0 + + + ALLOW_NSC + Non-secure state allow +0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter non-secure state + 17 + 1 + read-only + + + ALLOW_SEC + Secure state allow +0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter secure state + 16 + 1 + read-only + + + PMIC_FAIL + PMIC secure state one hot indicator +0: secure state is not in fail state +1: secure state is in fail state + 7 + 1 + read-write + + + PMIC_NSC + PMIC secure state one hot indicator +0: secure state is not in non-secure state +1: secure state is in non-secure state + 6 + 1 + read-write + + + PMIC_SEC + PMIC secure state one hot indicator +0: secure state is not in secure state +1: secure state is in secure state + 5 + 1 + read-write + + + PMIC_INS + PMIC secure state one hot indicator +0: secure state is not in inspect state +1: secure state is in inspect state + 4 + 1 + read-write + + + + + SECURE_STATE_CONFIG + secure state configuration + 0x4 + 32 + 0x00000000 + 0x00000009 + + + LOCK + Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset +0: not locked, register can be modified +1: register locked, write access to the register is ignored + 3 + 1 + read-write + + + ALLOW_RESTART + allow secure state restart from fail state +0: restart is not allowed, only hardware reset can recover secure state +1: software is allowed to switch to inspect state from fail state + 0 + 1 + read-write + + + + + VIOLATION_CONFIG + Security violation config + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 0 + 15 + read-write + + + + + ESCALATE_CONFIG + Escalate behavior on security event + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 0 + 15 + read-write + + + + + EVENT + Event and escalate status + 0x10 + 32 + 0x00000000 + 0xFFFF000C + + + EVENT + local event statue, each bit represents one security event + 16 + 16 + read-only + + + PMIC_ESC_NSC + PMIC is escalating non-secure event + 3 + 1 + read-only + + + PMIC_ESC_SEC + PMIC is escalting secure event + 2 + 1 + read-only + + + + + LIFECYCLE + Lifecycle + 0x14 + 32 + 0x00000000 + 0x000000FF + + + LIFECYCLE + lifecycle status, +bit7: lifecycle_debate, +bit6: lifecycle_scribe, +bit5: lifecycle_no_ret, +bit4: lifecycle_return, +bit3: lifecycle_secure, +bit2: lifecycle_nonsec, +bit1: lifecycle_create, +bit0: lifecycle_unknow + 0 + 8 + read-only + + + + + + + MON + MON + MON + 0xf3048000 + + 0x0 + 0x48 + registers + + + + 4 + 0x8 + glitch0,glitch1,clock0,clock1 + MONITOR[%s] + no description available + 0x0 + + CONTROL + Glitch and clock monitor control + 0x0 + 32 + 0x00000000 + 0x00000011 + + + ACTIVE + select glitch works in active mode or passve mode. +0: passive mode, depends on power glitch destroy DFF value +1: active mode, check glitch by DFF chain + 4 + 1 + read-write + + + ENABLE + enable glitch detector +0: detector disabled +1: detector enabled + 0 + 1 + read-write + + + + + STATUS + Glitch and clock monitor status + 0x4 + 32 + 0x00000000 + 0x00000001 + + + FLAG + flag for glitch detected, write 1 to clear this flag +0: glitch not detected +1: glitch detected + 0 + 1 + read-write + + + + + + IRQ_FLAG + No description available + 0x40 + 32 + 0x00000000 + 0x0000000F + + + FLAG + interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag +0: no monitor interrupt +1: monitor interrupt happened + 0 + 4 + read-write + + + + + IRQ_ENABLE + No description available + 0x44 + 32 + 0x00000000 + 0x0000000F + + + ENABLE + interrupt enable, each bit represents for one monitor +0: monitor interrupt disabled +1: monitor interrupt enabled + 0 + 4 + read-write + + + + + + + RNG + RNG + RNG + 0xf304c000 + + 0x0 + 0x40 + registers + + + + CMD + Command Register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SFTRST + Soft Reset, Perform a software reset of the RNG This bit is self-clearing. +0 Do not perform a software reset. +1 Software reset + 6 + 1 + read-write + + + CLRERR + Clear the Error, clear the errors in the ESR register and the RNG interrupt. This bit is self-clearing. +0 Do not clear the errors and the interrupt. +1 Clear the errors and the interrupt. + 5 + 1 + read-write + + + CLRINT + Clear the Interrupt, clear the RNG interrupt if an error is not present. This bit is self-clearing. +0 Do not clear the interrupt. +1 Clear the interrupt + 4 + 1 + read-write + + + GENSD + Generate Seed, when both ST and GS triggered, ST first and GS next. + 1 + 1 + read-write + + + SLFCHK + Self Test, when both ST and GS triggered, ST first and GS next. + 0 + 1 + read-write + + + + + CTRL + Control Register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + MIRQERR + Mask Interrupt Request for Error + 6 + 1 + read-write + + + MIRQDN + Mask Interrupt Request for Done Event, asks the interrupts generated upon the completion of the seed and self-test modes. The status of these jobs can be viewed by: +• Reading the STA and viewing the seed done and the self-test done bits (STA[SDN, STDN]). +• Viewing the RNG_CMD for the generate-seed or the self-test bits (CMD[GS,ST]) being set, indicating that the operation is still taking place. + 5 + 1 + read-write + + + AUTRSD + Auto Reseed + 4 + 1 + read-write + + + FUFMOD + FIFO underflow response mode +00 Return all zeros and set the ESR[FUFE]. +01 Return all zeros and set the ESR[FUFE]. +10 Generate the bus transfer error +11 Generate the interrupt and return all zeros (overrides the CTRL[MASKERR]). + 0 + 2 + read-write + + + + + STA + Status Register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SCPF + Self Check Pass Fail + 21 + 3 + read-only + + + FUNCERR + Error was detected, check ESR register for details + 16 + 1 + read-only + + + FSIZE + Fifo Size, it is 5 in this design. + 12 + 4 + read-only + + + FRNNU + Fifo Level, Indicates the number of random words currently in the output FIFO + 8 + 4 + read-only + + + NSDDN + New seed done. + 6 + 1 + read-only + + + FSDDN + 1st Seed done +When "1", Indicates that the RNG generated the first seed. + 5 + 1 + read-only + + + SCDN + Self Check Done +Indicates whether Self Test is done or not. Can be cleared by the hardware reset or a new self test is +initiated by setting the CMD[ST]. +0 Self test not completed +1 Completed a self test since the last reset. + 4 + 1 + read-only + + + RSDREQ + Reseed needed +Indicates that the RNG needs to be reseeded. This is done by setting the CMD[GS], or +automatically if the CTRL[ARS] is set. + 3 + 1 + read-only + + + IDLE + Idle, the RNG is in the idle mode, and internal clocks are disabled, in this mode, access to the FIFO is allowed. Once the FIFO is empty, the RNGB fills the FIFO and then enters idle mode again. + 2 + 1 + read-only + + + BUSY + when 1, means the RNG engine is busy for seeding or random number generation, self test and so on. + 1 + 1 + read-only + + + + + ERR + Error Registers + 0xc + 32 + 0x00000000 + 0xFFFFFF3F + + + FUFE + FIFO access error(underflow) + 5 + 1 + read-only + + + SCKERR + Self-test error +Indicates that the RNG failed the most recent self test. This bit is sticky and can only be reset by a +hardware reset or by writing 1 to the CMD[CE] + 3 + 1 + read-only + + + + + FO2B + FIFO out to bus/cpu + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2B + SW read the FIFO output. + 0 + 32 + read-only + + + + + 8 + 0x4 + FO2S0,FO2S1,FO2S2,FO2S3,FO2S4,FO2S5,FO2S6,FO2S7 + R2SK[%s] + no description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2S0 + FIFO out to KMAN, will be SDP engine key. + 0 + 32 + read-only + + + + + + + OTP + OTP + OTP + 0xf3050000 + + 0x0 + 0xc08 + registers + + + + 128 + 0x4 + SHADOW000,SHADOW001,SHADOW002,SHADOW003,SHADOW004,SHADOW005,SHADOW006,SHADOW007,SHADOW008,SHADOW009,SHADOW010,SHADOW011,SHADOW012,SHADOW013,SHADOW014,SHADOW015,SHADOW016,SHADOW017,SHADOW018,SHADOW019,SHADOW020,SHADOW021,SHADOW022,SHADOW023,SHADOW024,SHADOW025,SHADOW026,SHADOW027,SHADOW028,SHADOW029,SHADOW030,SHADOW031,SHADOW032,SHADOW033,SHADOW034,SHADOW035,SHADOW036,SHADOW037,SHADOW038,SHADOW039,SHADOW040,SHADOW041,SHADOW042,SHADOW043,SHADOW044,SHADOW045,SHADOW046,SHADOW047,SHADOW048,SHADOW049,SHADOW050,SHADOW051,SHADOW052,SHADOW053,SHADOW054,SHADOW055,SHADOW056,SHADOW057,SHADOW058,SHADOW059,SHADOW060,SHADOW061,SHADOW062,SHADOW063,SHADOW064,SHADOW065,SHADOW066,SHADOW067,SHADOW068,SHADOW069,SHADOW070,SHADOW071,SHADOW072,SHADOW073,SHADOW074,SHADOW075,SHADOW076,SHADOW077,SHADOW078,SHADOW079,SHADOW080,SHADOW081,SHADOW082,SHADOW083,SHADOW084,SHADOW085,SHADOW086,SHADOW087,SHADOW088,SHADOW089,SHADOW090,SHADOW091,SHADOW092,SHADOW093,SHADOW094,SHADOW095,SHADOW096,SHADOW097,SHADOW098,SHADOW099,SHADOW100,SHADOW101,SHADOW102,SHADOW103,SHADOW104,SHADOW105,SHADOW106,SHADOW107,SHADOW108,SHADOW109,SHADOW110,SHADOW111,SHADOW112,SHADOW113,SHADOW114,SHADOW115,SHADOW116,SHADOW117,SHADOW118,SHADOW119,SHADOW120,SHADOW121,SHADOW122,SHADOW123,SHADOW124,SHADOW125,SHADOW126,SHADOW127 + SHADOW[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + 8 + 0x4 + LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 + SHADOW_LOCK[%s] + no description available + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + 128 + 0x4 + FUSE000,FUSE001,FUSE002,FUSE003,FUSE004,FUSE005,FUSE006,FUSE007,FUSE008,FUSE009,FUSE010,FUSE011,FUSE012,FUSE013,FUSE014,FUSE015,FUSE016,FUSE017,FUSE018,FUSE019,FUSE020,FUSE021,FUSE022,FUSE023,FUSE024,FUSE025,FUSE026,FUSE027,FUSE028,FUSE029,FUSE030,FUSE031,FUSE032,FUSE033,FUSE034,FUSE035,FUSE036,FUSE037,FUSE038,FUSE039,FUSE040,FUSE041,FUSE042,FUSE043,FUSE044,FUSE045,FUSE046,FUSE047,FUSE048,FUSE049,FUSE050,FUSE051,FUSE052,FUSE053,FUSE054,FUSE055,FUSE056,FUSE057,FUSE058,FUSE059,FUSE060,FUSE061,FUSE062,FUSE063,FUSE064,FUSE065,FUSE066,FUSE067,FUSE068,FUSE069,FUSE070,FUSE071,FUSE072,FUSE073,FUSE074,FUSE075,FUSE076,FUSE077,FUSE078,FUSE079,FUSE080,FUSE081,FUSE082,FUSE083,FUSE084,FUSE085,FUSE086,FUSE087,FUSE088,FUSE089,FUSE090,FUSE091,FUSE092,FUSE093,FUSE094,FUSE095,FUSE096,FUSE097,FUSE098,FUSE099,FUSE100,FUSE101,FUSE102,FUSE103,FUSE104,FUSE105,FUSE106,FUSE107,FUSE108,FUSE109,FUSE110,FUSE111,FUSE112,FUSE113,FUSE114,FUSE115,FUSE116,FUSE117,FUSE118,FUSE119,FUSE120,FUSE121,FUSE122,FUSE123,FUSE124,FUSE125,FUSE126,FUSE127 + FUSE[%s] + no description available + 0x400 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + 8 + 0x4 + LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 + FUSE_LOCK[%s] + no description available + 0x600 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + UNLOCK + UNLOCK + 0x800 + 32 + 0x00000000 + 0xFFFFFFFF + + + UNLOCK + unlock word for fuse array operation +write "OPEN" to unlock fuse array, write any other value will lock write to fuse. +Please make sure 24M crystal is running and 2.5V LDO working properly + 0 + 32 + read-write + + + + + DATA + DATA + 0x804 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + data register for non-blocking access +this register hold dat read from fuse array or data to by programmed to fuse array + 0 + 32 + read-write + + + + + ADDR + ADDR + 0x808 + 32 + 0x00000000 + 0x0000007F + + + ADDR + word address to be read or write + 0 + 7 + read-write + + + + + CMD + CMD + 0x80c + 32 + 0x00000000 + 0xFFFFFFFF + + + CMD + command to access fure array +"BLOW" will update fuse word at ADDR to value hold in DATA +"READ" will fetch fuse value in at ADDR to DATA register + 0 + 32 + read-write + + + + + LOAD_REQ + LOAD Request + 0xa00 + 32 + 0x00000007 + 0x0000000F + + + REQUEST + reload request for 4 regions +bit0: region0 +bit1: region1 +bit2: region2 +bit3: region3 + 0 + 4 + read-write + + + + + LOAD_COMP + LOAD complete + 0xa04 + 32 + 0x00000007 + 0x0000000F + + + COMPLETE + reload complete sign for 4 regions +bit0: region 0 +bit1: region1 +bit2: region2 +bit3: region3 + 0 + 4 + read-write + + + + + 4 + 0x4 + LOAD_REGION0,LOAD_REGION1,LOAD_REGION2,LOAD_REGION3 + REGION[%s] + no description available + 0xa20 + 32 + 0x00000800 + 0x00007F7F + + + STOP + stop address of load region, fuse word at end address will NOT be reloaded +region0: fixed at 8 +region1: fixed at 16 +region2: fixed at 0, +region3: usrer configurable + 8 + 7 + read-write + + + START + start address of load region, fuse word at start address will be reloaded +region0: fixed at 0 +region1: fixed at 8 +region2: fixed at 16, +region3: usrer configurable + 0 + 7 + read-write + + + + + INT_FLAG + interrupt flag + 0xc00 + 32 + 0x00000000 + 0x00000007 + + + WRITE + fuse write flag, write 1 to clear +0: fuse is not written or writing +1: value in DATA register is programmed into fuse + 2 + 1 + read-write + + + READ + fuse read flag, write 1 to clear +0: fuse is not read or reading +1: fuse value is put in DATA register + 1 + 1 + read-write + + + LOAD + fuse load flag, write 1 to clear +0: fuse is not loaded or loading +1: fuse loaded + 0 + 1 + read-write + + + + + INT_EN + interrupt enable + 0xc04 + 32 + 0x00000000 + 0x00000007 + + + WRITE + fuse write interrupt enable +0: fuse write interrupt is not enable +1: fuse write interrupt is enable + 2 + 1 + read-write + + + READ + fuse read interrupt enable +0: fuse read interrupt is not enable +1: fuse read interrupt is enable + 1 + 1 + read-write + + + LOAD + fuse load interrupt enable +0: fuse load interrupt is not enable +1: fuse load interrupt is enable + 0 + 1 + read-write + + + + + + + KEYM + KEYM + KEYM + 0xf3054000 + + 0x0 + 0x50 + registers + + + + 8 + 0x4 + SFK0,SFK1,SFK2,SFK3,SFK4,SFK5,SFK6,SFK7 + SOFTMKEY[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software symmetric key +key will be scambled to 4 variants for software to use, and replicable on same chip. +scramble keys are chip different, and not replicable on different chip +must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 + 0 + 32 + read-write + + + + + 8 + 0x4 + SPK0,SPK1,SPK2,SPK3,SPK4,SPK5,SPK6,SPK7 + SOFTPKEY[%s] + no description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software asymmetric key +key is derived from scrambles of fuse private key, software input key, SRK, and system security status. +This key os read once, sencondary read will read out 0 + 0 + 32 + read-write + + + + + SEC_KEY_CTL + secure key generation + 0x40 + 32 + 0x00000000 + 0x80011117 + + + LOCK_SEC_CTL + block secure state key setting being changed + 31 + 1 + read-write + + + SK_VAL + session key valid +0: session key is all 0's and not usable +1: session key is valid + 16 + 1 + read-only + + + SMK_SEL + software symmetric key selection +0: use origin value in software symmetric key +1: use scramble version of software symmetric key + 12 + 1 + read-write + + + ZMK_SEL + batt symmetric key selection +0: use scramble version of software symmetric key +1: use origin value in software symmetric key + 8 + 1 + read-write + + + FMK_SEL + fuse symmetric key selection +0: use scramble version of fuse symmetric key +1: use alnertave scramble of fuse symmetric key + 4 + 1 + read-write + + + KEY_SEL + secure symmtric key synthesize setting, key is a XOR of following +bit0: fuse mk, 0: not selected, 1:selected +bit1: zmk from batt, 0: not selected, 1:selected +bit2: software key 0: not selected, 1:selected + 0 + 3 + read-write + + + + + NSC_KEY_CTL + non-secure key generation + 0x44 + 32 + 0x00000000 + 0x80011117 + + + LOCK_NSC_CTL + block non-secure state key setting being changed + 31 + 1 + read-write + + + SK_VAL + session key valid +0: session key is all 0's and not usable +1: session key is valid + 16 + 1 + read-only + + + SMK_SEL + software symmetric key selection +0: use scramble version of software symmetric key +1: use origin value in software symmetric key + 12 + 1 + read-write + + + ZMK_SEL + batt symmetric key selection +0: use scramble version of software symmetric key +1: use origin value in software symmetric key + 8 + 1 + read-write + + + FMK_SEL + fuse symmetric key selection +0: use scramble version of fuse symmetric key +1: use origin value in fuse symmetric key + 4 + 1 + read-write + + + KEY_SEL + non-secure symmtric key synthesize setting, key is a XOR of following +bit0: fuse mk, 0: not selected, 1:selected +bit1: zmk from batt, 0: not selected, 1:selected +bit2: software key 0: not selected, 1:selected + 0 + 3 + read-write + + + + + RNG + Random number interface behavior + 0x48 + 32 + 0x00000000 + 0x00010001 + + + BLOCK_RNG_XOR + block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset +0: RNG_XOR can be changed by software +1: RNG_XOR ignore software change from software + 16 + 1 + read-write + + + RNG_XOR + control how SFK is accepted from random number generator +0: SFK value replaced by random number input +1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG + 0 + 1 + read-write + + + + + READ_CONTROL + key read out control + 0x4c + 32 + 0x00000000 + 0x00010001 + + + BLOCK_PK_READ + asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset +0: key can be read out +1: key cannot be read out + 16 + 1 + read-write + + + BLOCK_SMK_READ + symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset +0: key can be read out +1: key cannot be read out + 0 + 1 + read-write + + + + + + + ADC0 + ADC0 + ADC16 + 0xf3080000 + + 0x0 + 0x1464 + registers + + + + 12 + 0x4 + trg0a,trg0b,trg0c,trg1a,trg1b,trg1c,trg2a,trg2b,trg2c,trg3a,trg3b,trg3c + CONFIG[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFF3F3F7F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interrupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interrupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interrupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + QUEUE_EN + preemption queue enable control + 6 + 1 + read-write + + + INTEN0 + interrupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + trg_dma_addr + No description available + 0x30 + 32 + 0x00000000 + 0xFFFFFFFC + + + TRG_DMA_ADDR + buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) + 2 + 30 + read-write + + + + + trg_sw_sta + No description available + 0x34 + 32 + 0x00000000 + 0x0000001F + + + TRG_SW_STA + SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it. + 4 + 1 + read-write + + + TRIG_SW_INDEX + which trigger for the SW trigger +0 for trig0a, 1 for trig0b… +3 for trig1a, …11 for trig3c + 0 + 4 + read-write + + + + + 16 + 0x4 + chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 + BUS_RESULT[%s] + no description available + 0x400 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + buf_cfg0 + No description available + 0x500 + 32 + 0x00000000 + 0x00000003 + + + BUS_MODE_EN + bus mode enable + 1 + 1 + read-write + + + WAIT_DIS + set to disable read waiting, get result immediately but maybe not current conversion result. + 0 + 1 + read-write + + + + + seq_cfg0 + No description available + 0x800 + 32 + 0x00000000 + 0x80000F1F + + + CYCLE + current dma write cycle bit + 31 + 1 + read-only + + + SEQ_LEN + sequence queue length, 0 for one, 0xF for 16 + 8 + 4 + read-write + + + RESTART_EN + if set together with cont_en, HW will continue process the whole queue after trigger once. +If cont_en is 0, this bit is not used + 4 + 1 + read-write + + + CONT_EN + if set, HW will continue process the queue till end(seq_len) after trigger once + 3 + 1 + read-write + + + SW_TRIG + SW trigger, pulse signal, cleared by HW one cycle later + 2 + 1 + write-only + + + SW_TRIG_EN + set to enable SW trigger + 1 + 1 + read-write + + + HW_TRIG_EN + set to enable external HW trigger, only trigger on posedge + 0 + 1 + read-write + + + + + seq_dma_addr + No description available + 0x804 + 32 + 0x00000000 + 0xFFFFFFFC + + + TAR_ADDR + dma target address, should be 4-byte aligned + 2 + 30 + read-write + + + + + seq_wr_addr + No description available + 0x808 + 32 + 0x00000000 + 0x00FFFFFF + + + SEQ_WR_POINTER + HW update this field after each dma write, it indicate the next dma write pointer. +dma write address is (tar_addr+seq_wr_pointer)*4 + 0 + 24 + read-only + + + + + seq_dma_cfg + No description available + 0x80c + 32 + 0x00000000 + 0x0FFF3FFF + + + STOP_POS + if stop_en is set, SW is responsible to update this field to the next read point, HW should not write data to this point since it's not read out by SW yet + 16 + 12 + read-write + + + DMA_RST + set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. +SW should clear all cycle bit in buffer to 0 before clear dma_rst + 13 + 1 + read-write + + + STOP_EN + set to stop dma if reach the stop_pos + 12 + 1 + read-write + + + BUF_LEN + dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 +0 for 4byte; +0xFFF for 16kbyte. + 0 + 12 + read-write + + + + + 16 + 0x4 + cfg0,cfg1,cfg2,cfg3,cfg4,cfg5,cfg6,cfg7,cfg8,cfg9,cfg10,cfg11,cfg12,cfg13,cfg14,cfg15 + SEQ_QUE[%s] + no description available + 0x810 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + seq_high_cfg + No description available + 0x850 + 32 + 0x00000000 + 0x00FFFFFF + + + STOP_POS_HIGH + No description available + 12 + 12 + read-write + + + BUF_LEN_HIGH + No description available + 0 + 12 + read-write + + + + + 16 + 0x10 + chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 + PRD_CFG[%s] + no description available + 0xc00 + + prd_cfg + No description available + 0x0 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + prd_thshd_cfg + No description available + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + prd_result + No description available + 0x8 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + + 16 + 0x4 + chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 + SAMPLE_CFG[%s] + no description available + 0x1000 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + conv_cfg1 + No description available + 0x1104 + 32 + 0x00000000 + 0x000001FF + + + CONVERT_CLOCK_NUMBER + convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider); +user can use small value to get faster conversion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. +Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC conversion(plus sample) need 25 cycles(50MHz). + 4 + 5 + read-write + + + CLOCK_DIVIDER + clock_period, N half clock cycle per half adc cycle +0 for same adc_clk and bus_clk, +1 for 1:2, +2 for 1:3, +... +15 for 1:16 +Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk + 0 + 4 + read-write + + + + + adc_cfg0 + No description available + 0x1108 + 32 + 0x00000000 + 0xA0000001 + + + SEL_SYNC_AHB + set to 1 will enable sync AHB bus, to get better bus performance. +Adc_clk must to be set to same as bus clock at this mode + 31 + 1 + read-write + + + ADC_AHB_EN + set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; + 29 + 1 + read-write + + + PORT3_REALTIME + set to enable trg queue stop other queues + 0 + 1 + read-write + + + + + int_sts + No description available + 0x1110 + 32 + 0x00000000 + 0xFFE0FFFF + + + TRIG_CMPT + interrupt for one trigger conversion complete if enabled + 31 + 1 + read-write + + + TRIG_SW_CFLCT + No description available + 30 + 1 + read-write + + + TRIG_HW_CFLCT + No description available + 29 + 1 + read-write + + + READ_CFLCT + read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel + 28 + 1 + read-write + + + SEQ_SW_CFLCT + sequence queue conflict interrupt, set if HW or SW trigger received during conversion + 27 + 1 + read-write + + + SEQ_HW_CFLCT + No description available + 26 + 1 + read-write + + + SEQ_DMAABT + dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set + 25 + 1 + read-write + + + SEQ_CMPT + the whole sequence complete interrupt + 24 + 1 + read-write + + + SEQ_CVC + one conversion complete in seq_queue if related seq_int_en is set + 23 + 1 + read-write + + + DMA_FIFO_FULL + DMA fifo full interrupt, user need to check clock frequency if it's set. + 22 + 1 + read-write + + + AHB_ERR + set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr + 21 + 1 + read-write + + + WDOG + set if one chanel watch dog event triggered + 0 + 16 + read-write + + + + + int_en + No description available + 0x1114 + 32 + 0x00000000 + 0xFFE0FFFF + + + TRIG_CMPT + interrupt for one trigger conversion complete if enabled + 31 + 1 + read-write + + + TRIG_SW_CFLCT + No description available + 30 + 1 + read-write + + + TRIG_HW_CFLCT + No description available + 29 + 1 + read-write + + + READ_CFLCT + read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel + 28 + 1 + read-write + + + SEQ_SW_CFLCT + sequence queue conflict interrupt, set if HW or SW trigger received during conversion + 27 + 1 + read-write + + + SEQ_HW_CFLCT + No description available + 26 + 1 + read-write + + + SEQ_DMAABT + dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set + 25 + 1 + read-write + + + SEQ_CMPT + the whole sequence complete interrupt + 24 + 1 + read-write + + + SEQ_CVC + one conversion complete in seq_queue if related seq_int_en is set + 23 + 1 + read-write + + + DMA_FIFO_FULL + DMA fifo full interrupt, user need to check clock frequency if it's set. + 22 + 1 + read-write + + + AHB_ERR + set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr + 21 + 1 + read-write + + + WDOG + set if one chanel watch dog event triggered + 0 + 16 + read-write + + + + + ana_ctrl0 + No description available + 0x1200 + 32 + 0x00000000 + 0x80001004 + + + MOTO_EN + "set to enable moto_soc and moto_valid. +Should use AHB clock for adc, this bit can be used avoid async output" + 31 + 1 + read-write + + + ADC_CLK_ON + set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. +MUST set clock_period to 0 or 1 for adc16 reg access + 12 + 1 + read-write + + + STARTCAL + set to start the offset calibration cycle (Active H). user need to clear it after setting it. + 2 + 1 + read-write + + + + + ana_status + No description available + 0x1210 + 32 + 0x00000000 + 0x00000080 + + + CALON + Indicates if the ADC is in calibration mode (Active H). + 7 + 1 + read-write + + + + + 34 + 0x2 + adc16_para00,adc16_para01,adc16_para02,adc16_para03,adc16_para04,adc16_para05,adc16_para06,adc16_para07,adc16_para08,adc16_para09,adc16_para10,adc16_para11,adc16_para12,adc16_para13,adc16_para14,adc16_para15,adc16_para16,adc16_para17,adc16_para18,adc16_para19,adc16_para20,adc16_para21,adc16_para22,adc16_para23,adc16_para24,adc16_para25,adc16_para26,adc16_para27,adc16_para28,adc16_para29,adc16_para30,adc16_para31,adc16_para32,adc16_para33 + ADC16_PARAMS[%s] + no description available + 0x1400 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description available + 0 + 16 + read-write + + + + + adc16_config0 + No description available + 0x1444 + 32 + 0x00000000 + 0x01F07FFF + + + REG_EN + set to enable regulator + 24 + 1 + read-write + + + BANDGAP_EN + set to enable bandgap. user should set reg_en and bandgap_en before use adc16. + 23 + 1 + read-write + + + CAL_AVG_CFG + for average the calibration result. +0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; +4- 16 loops; 5-32 loops; others reserved + 20 + 3 + read-write + + + PREEMPT_EN + set to enable preemption feature + 14 + 1 + read-write + + + CONV_PARAM + conversion parameter + 0 + 14 + read-write + + + + + adc16_config1 + No description available + 0x1460 + 32 + 0x00000000 + 0x00001F00 + + + COV_END_CNT + used for faster conversion, user can change it to get higher convert speed(but less accuracy). +should set to (21-convert_clock_number+1). + 8 + 5 + read-write + + + + + + + ADC1 + ADC1 + ADC16 + 0xf3084000 + + + DAC0 + DAC0 + DAC + 0xf3090000 + + 0x0 + 0x4c + registers + + + + cfg0 + No description available + 0x0 + 32 + 0x00000000 + 0x0FFF03FF + + + SW_DAC_DATA + dac data used in direct mode(dac_mode==2'b10) + 16 + 12 + write-only + + + DMA_AHB_EN + set to enable internal DMA, it will read one burst if enough space in FIFO. +Should only be used in buffer mode. + 9 + 1 + write-only + + + SYNC_MODE + 1: sync dac clock and ahb clock. + all HW trigger signals are pulse in sync mode, can get faster response; +0: async dac clock and ahb_clock + all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock) + 8 + 1 + write-only + + + TRIG_MODE + 0: single mode, one trigger pulse will send one 12bit data to DAC analog; +1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data. + 7 + 1 + write-only + + + HW_TRIG_EN + set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode + 6 + 1 + write-only + + + DAC_MODE + 00: direct mode, DAC output the fixed configured data(from sw_dac_data) +01: step mode, DAC output from start_point to end point, with configured step, can step up or step down +10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; +11: trigger mode, DAC output from external trigger signals +Note: +Trigger mode is not supported in hpm63xx and hpm62xx families. + 4 + 2 + write-only + + + BUF_DATA_MODE + data structure for buffer mode, +0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. +1: each 32-bit data contains 1 point, b11:0 for first + 3 + 1 + write-only + + + HBURST_CFG + DAC support following fixed burst only +000-SINGLE; 011-INCR4; 101: INCR8 +others are reserved + 0 + 3 + write-only + + + + + cfg1 + No description available + 0x4 + 32 + 0x00010000 + 0x0007FFFF + + + ANA_CLK_EN + set to enable analog clock(divided by ana_div_cfg) +need to be set in direct mode and trigger mode + 18 + 1 + read-write + + + ANA_DIV_CFG + clock divider config for ana_clk to dac analog; +00: div2 +01: div4 +10: div6 +11: div8 + 16 + 2 + read-write + + + DIV_CFG + step mode and buffer mode: + defines how many clk_dac cycles to change data to analog, should configured to less than 1MHz data rate. +Direct mode and trigger mode: + defines how many clk_dac cycles to accpet the input data, dac will not accept new written data or trigger data before the clock cycles passed. should configured to less than 1MHz. +Note: +For direct mode and trigger mode, this config is not supported in hpm63xx and hpm62xx families. + 0 + 16 + read-write + + + + + cfg2 + No description available + 0x8 + 32 + 0x00000000 + 0x000000FF + + + DMA_RST1 + set to reset dma read pointer to buf1_start_addr; +if set both dma_rst0&dma_rst1, will set to buf0_start_addr +user can set fifo_clr bit when use dma_rst* + 7 + 1 + write-only + + + DMA_RST0 + set to reset dma read pointer to buf0_start_addr + 6 + 1 + write-only + + + FIFO_CLR + set to clear FIFO content(set both read/write pointer to 0) + 5 + 1 + write-only + + + BUF_SW_TRIG + software trigger for buffer mode, +W1C in single mode. +RW in continual mode + 4 + 1 + read-write + + + STEP_SW_TRIG3 + No description available + 3 + 1 + read-write + + + STEP_SW_TRIG2 + No description available + 2 + 1 + read-write + + + STEP_SW_TRIG1 + No description available + 1 + 1 + read-write + + + STEP_SW_TRIG0 + software trigger0 for step mode, +W1C in single mode. +RW in continual mode + 0 + 1 + read-write + + + + + 4 + 0x4 + step0,step1,step2,step3 + STEP_CFG[%s] + no description available + 0x10 + 32 + 0x00000000 + 0x3FFFFFFF + + + ROUND_MODE + 0: stop at end point; +1: reload start point, step again + 29 + 1 + read-write + + + UP_DOWN + 0 for up, 1 for down + 28 + 1 + read-write + + + END_POINT + No description available + 16 + 12 + read-write + + + STEP_NUM + output data change step_num each DAC clock cycle. +Ex: if step_num=3, output data sequence is 0,3,6,9 +NOTE: user should make sure end_point can be reached if step_num is not 1 +if step_num is 0, output data will always at start point + 12 + 4 + read-write + + + START_POINT + No description available + 0 + 12 + read-write + + + + + 2 + 0x4 + buf0,buf1 + BUF_ADDR[%s] + no description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFD + + + BUF_START_ADDR + buffer start address, should be 4-byte aligned +AHB burst can't cross 1K-byte boundary, user should config the address/length/burst to avoid such issue. + 2 + 30 + read-write + + + BUF_STOP + set to stop read point at end of bufffer0 + 0 + 1 + read-write + + + + + buf_length + No description available + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + BUF1_LEN + buffer length, 1 indicate one 32bit date, 256K-byte max for one buffer + 16 + 16 + read-write + + + BUF0_LEN + No description available + 0 + 16 + read-write + + + + + irq_sts + No description available + 0x30 + 32 + 0x00000000 + 0x0000001F + + + STEP_CMPT + No description available + 4 + 1 + write-only + + + AHB_ERROR + set if hresp==2'b01(ERROR) + 3 + 1 + write-only + + + FIFO_EMPTY + No description available + 2 + 1 + write-only + + + BUF1_CMPT + No description available + 1 + 1 + write-only + + + BUF0_CMPT + No description available + 0 + 1 + write-only + + + + + irq_en + No description available + 0x34 + 32 + 0x00000000 + 0x0000001F + + + STEP_CMPT + No description available + 4 + 1 + read-write + + + AHB_ERROR + No description available + 3 + 1 + read-write + + + FIFO_EMPTY + No description available + 2 + 1 + read-write + + + BUF1_CMPT + No description available + 1 + 1 + read-write + + + BUF0_CMPT + No description available + 0 + 1 + read-write + + + + + dma_en + No description available + 0x38 + 32 + 0x00000000 + 0x00000013 + + + STEP_CMPT + No description available + 4 + 1 + read-write + + + BUF1_CMPT + No description available + 1 + 1 + read-write + + + BUF0_CMPT + No description available + 0 + 1 + read-write + + + + + ana_cfg0 + No description available + 0x40 + 32 + 0x00000030 + 0x000001FF + + + DAC12BIT_LP_MODE + No description available + 8 + 1 + read-write + + + DAC_CONFIG + No description available + 4 + 4 + read-write + + + CALI_DELTA_V_CFG + No description available + 2 + 2 + read-write + + + BYPASS_CALI_GM + No description available + 1 + 1 + read-write + + + DAC12BIT_EN + No description available + 0 + 1 + read-write + + + + + cfg0_bak + No description available + 0x44 + 32 + 0x00000000 + 0x0FFF03FF + + + SW_DAC_DATA + dac data used in direct mode(dac_mode==2'b10) + 16 + 12 + read-write + + + DMA_AHB_EN + set to enable internal DMA, it will read one burst if enough space in FIFO. +Should only be used in buffer mode. + 9 + 1 + read-write + + + SYNC_MODE + 1: sync dac clock and ahb clock. + all HW trigger signals are pulse in sync mode, can get faster response; +0: async dac clock and ahb_clock + all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock) + 8 + 1 + read-write + + + TRIG_MODE + 0: single mode, one trigger pulse will send one 12bit data to DAC analog; +1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data. + 7 + 1 + read-write + + + HW_TRIG_EN + set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode + 6 + 1 + read-write + + + DAC_MODE + 00: direct mode, DAC output the fixed configured data(from sw_dac_data) +01: step mode, DAC output from start_point to end point, with configured step, can step up or step down +10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; + 4 + 2 + read-write + + + BUF_DATA_MODE + data structure for buffer mode, +0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. +1: each 32-bit data contains 1 point, b11:0 for first + 3 + 1 + read-write + + + HBURST_CFG + DAC support following fixed burst only +000-SINGLE; 011-INCR4; 101: INCR8 +others are reserved + 0 + 3 + read-write + + + + + status0 + No description available + 0x48 + 32 + 0x00000000 + 0x00FFFF80 + + + CUR_BUF_OFFSET + No description available + 8 + 16 + read-write + + + CUR_BUF_INDEX + No description available + 7 + 1 + read-write + + + + + + + DAC1 + DAC1 + DAC + 0xf3094000 + + + OPAMP0 + OPAMP0 + OPAMP + 0xf30a0000 + + 0x0 + 0x90 + registers + + + + ctrl0 + control reg + 0x0 + 32 + 0x00000000 + 0x0407FFFF + + + EN_LV + No description available + 26 + 1 + read-write + + + VIM_SEL + No description available + 16 + 3 + read-write + + + MODE + No description available + 11 + 5 + read-write + + + GAIN_SEL + No description available + 8 + 3 + read-write + + + DISABLE_PM_CAP + No description available + 7 + 1 + read-write + + + MILLER_SEL + No description available + 4 + 3 + read-write + + + VBYPASS + No description available + 3 + 1 + read-write + + + VIP_SEL + No description available + 0 + 3 + read-write + + + + + status + status reg + 0x4 + 32 + 0x00000000 + 0x0FFF0000 + + + TRIG_CONFLICT + if more than one hardware trigger is set, will put all trigger input here; +write any value to clear + 20 + 8 + read-write + + + PRESET_ACT + 1 for preset active; one of cur_preset is selected for OPAMP; +0 for no preset, OPAMP use cfg0 parameters + 19 + 1 + read-only + + + CUR_PRESET + current selected preset + 16 + 3 + read-only + + + + + ctrl1 + control reg1 + 0x8 + 32 + 0x00000000 + 0x80000007 + + + SW_PRESET + set to use preset defined by sw_sel. +NOTE: when set, the hardware trigger will not be used + 31 + 1 + read-write + + + SW_SEL + No description available + 0 + 3 + read-write + + + + + 8 + 0x10 + preset0,preset1,preset2,preset3,preset4,preset5,preset6,preset7 + CFG[%s] + no description available + 0x10 + + cfg0 + No description available + 0x0 + 32 + 0x00000000 + 0x0F000707 + + + DISABLE_PM_CAP + No description available + 27 + 1 + read-write + + + MILLER_SEL + No description available + 24 + 3 + read-write + + + VIM_SEL + No description available + 8 + 3 + read-write + + + VIP_SEL + No description available + 0 + 3 + read-write + + + + + cfg1 + No description available + 0x4 + 32 + 0x00000000 + 0xE00000FF + + + HW_TRIG_EN + set to enable hardware trigger from moto system. +NOTE: when sw_preset is enabled, this bit will not take effert + 31 + 1 + read-write + + + EN_LV + No description available + 30 + 1 + read-write + + + VBYPASS_LV + No description available + 29 + 1 + read-write + + + MODE + No description available + 3 + 5 + read-write + + + GAIN_SEL + No description available + 0 + 3 + read-write + + + + + cfg2 + No description available + 0x8 + 32 + 0x00000000 + 0x07000000 + + + CHANNEL + No description available + 24 + 3 + read-write + + + + + + + + OPAMP1 + OPAMP1 + OPAMP + 0xf30a4000 + + + ACMP + ACMP + ACMP + 0xf30b0000 + + 0x0 + 0x80 + registers + + + + 4 + 0x20 + chn0,chn1,chn2,chn3 + CHANNEL[%s] + no description available + 0x0 + + cfg + Configure Register + 0x0 + 32 + 0x00000000 + 0xFF7FFFFF + + + HYST + This bitfield configure the comparator hysteresis. +00: Hysteresis level 0 +01: Hysteresis level 1 +10: Hysteresis level 2 +11: Hysteresis level 3 + 30 + 2 + read-write + + + DACEN + This bit enable the comparator internal DAC +0: DAC disabled +1: DAC enabled + 29 + 1 + read-write + + + HPMODE + This bit enable the comparator high performance mode. +0: HP mode disabled +1: HP mode enabled + 28 + 1 + read-write + + + CMPEN + This bit enable the comparator. +0: ACMP disabled +1: ACMP enabled + 27 + 1 + read-write + + + MINSEL + PIN select, from pad_ai_acmp[7:1] and dac_out + 24 + 3 + read-write + + + PINSEL + MIN select, from pad_ai_acmp[7:1] and dac_out + 20 + 3 + read-write + + + CMPOEN + This bit enable the comparator output on pad. +0: ACMP output disabled +1: ACMP output enabled + 19 + 1 + read-write + + + FLTBYPS + This bit bypass the comparator output digital filter. +0: The ACMP output need pass digital filter +1: The ACMP output digital filter is bypassed. + 18 + 1 + read-write + + + WINEN + This bit enable the comparator window mode. +0: Window mode is disabled +1: Window mode is enabled + 17 + 1 + read-write + + + OPOL + The output polarity control bit. +0: The ACMP output remain un-changed. +1: The ACMP output is inverted. + 16 + 1 + read-write + + + FLTMODE + This bitfield define the ACMP output digital filter mode: +000-bypass +100-change immediately; +101-change after filter; +110-stalbe low; +111-stable high + 13 + 3 + read-write + + + SYNCEN + This bit enable the comparator output synchronization. +0: ACMP output not synchronized with ACMP clock. +1: ACMP output synchronized with ACMP clock. + 12 + 1 + read-write + + + FLTLEN + This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. + 0 + 12 + read-write + + + + + daccfg + DAC configure register + 0x4 + 32 + 0x00000000 + 0x000000FF + + + DACCFG + 8bit DAC digital value output to analog block + 0 + 8 + read-write + + + + + sr + Status register + 0x10 + 32 + 0x00000000 + 0x00000003 + + + FEDGF + Output falling edge flag. Write 1 to clear this flag. + 1 + 1 + read-write + + + REDGF + Output rising edge flag. Write 1 to clear this flag. + 0 + 1 + read-write + + + + + irqen + Interrupt request enable register + 0x14 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag interrupt enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag interrupt enable bit. + 0 + 1 + read-write + + + + + dmaen + DMA request enable register + 0x18 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag DMA request enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag DMA request enable bit. + 0 + 1 + read-write + + + + + + + + SYSCTL + SYSCTL + SYSCTL + 0xf4000000 + + 0x0 + 0x2c00 + registers + + + + 105 + 0x4 + cpu0,cpx0,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,rsv14,rsv15,rsv16,rsv17,rsv18,rsv19,rsv20,pow_cpu0,rst_soc,rst_cpu0,rsv24,rsv25,rsv26,rsv27,rsv28,rsv29,rsv30,rsv31,clk_src_xtal,clk_src_pll0,clk_src_clk0_pll0,clk_src_clk1_pll0,clk_src_clk2_pll0,clk_src_pll1,clk_src_clk0_pll1,clk_src_clk1_pll1,clk_src_clk2_pll1,clk_src_clk3_pll1,clk_src_pll0_ref,clk_src_pll1_ref,rsv44,rsv45,rsv46,rsv47,rsv48,rsv49,rsv50,rsv51,rsv52,rsv53,rsv54,rsv55,rsv56,rsv57,rsv58,rsv59,rsv60,rsv61,rsv62,rsv63,clk_top_cpu0,clk_top_mct0,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,rsv70,rsv71,rsv72,rsv73,clk_top_tmr0,clk_top_tmr1,clk_top_tmr2,clk_top_tmr3,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_urt0,clk_top_urt1,clk_top_urt2,clk_top_urt3,clk_top_urt4,clk_top_urt5,clk_top_urt6,clk_top_urt7,clk_top_xpi0,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_ana3,clk_top_ref0,clk_top_ref1,clk_top_adc0,clk_top_adc1,clk_top_dac0,clk_top_dac1,rsv105,rsv106,rsv107,rsv108,rsv109,rsv110,rsv111,rsv112,rsv113,rsv114,rsv115,rsv116,rsv117,rsv118,rsv119,rsv120,rsv121,rsv122,rsv123,rsv124,rsv125,rsv126,rsv127,rsv128,rsv129,rsv130,rsv131,rsv132,rsv133,rsv134,rsv135,rsv136,rsv137,rsv138,rsv139,rsv140,rsv141,rsv142,rsv143,rsv144,rsv145,rsv146,rsv147,rsv148,rsv149,rsv150,rsv151,rsv152,rsv153,rsv154,rsv155,rsv156,rsv157,rsv158,rsv159,rsv160,rsv161,rsv162,rsv163,rsv164,rsv165,rsv166,rsv167,rsv168,rsv169,rsv170,rsv171,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,ahb0,lmm0,mct0,rom0,can0,can1,can2,can3,ptpc,rsv265,rsv266,rsv267,rsv268,tmr0,tmr1,tmr2,tmr3,i2c0,i2c1,i2c2,i2c3,spi0,spi1,spi2,spi3,urt0,urt1,urt2,urt3,urt4,urt5,urt6,urt7,wdg0,wdg1,mbx0,tsns,crc0,adc0,adc1,dac0,dac1,acmp,opa0,opa1,mot0,rng0,sdp0,kman,gpio,hdma,xpi0,usb0,ref0,ref1 + RESOURCE[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + 2 + 0x10 + link0,link1 + GROUP0[%s] + no description available + 0x800 + + VALUE + Group setting + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + SET + Group setting + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: add periphera into this group，periphera is needed + 0 + 32 + read-write + + + + + CLEAR + Group setting + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: delete periphera in this group，periphera is not needed + 0 + 32 + read-write + + + + + TOGGLE + Group setting + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: toggle the result that whether periphera is needed before + 0 + 32 + read-write + + + + + + 1 + 0x10 + cpu0 + AFFILIATE[%s] + no description available + 0x900 + + VALUE + Affiliate of Group + 0x0 + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0, each bit represents a group +bit0: cpu0 depends on group0 +bit1: cpu0 depends on group1 +bit2: cpu0 depends on group2 +bit3: cpu0 depends on group3 + 0 + 4 + read-write + + + + + SET + Affiliate of Group + 0x4 + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0，each bit represents a group +0: no effect +1: the group is assigned to CPU0 + 0 + 4 + read-write + + + + + CLEAR + Affiliate of Group + 0x8 + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0, each bit represents a group +0: no effect +1: the group is not assigned to CPU0 + 0 + 4 + read-write + + + + + TOGGLE + Affiliate of Group + 0xc + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0, each bit represents a group +0: no effect +1: toggle the result that whether the group is assigned to CPU0 before + 0 + 4 + read-write + + + + + + 1 + 0x10 + cpu0 + RETENTION[%s] + no description available + 0x920 + + VALUE + Retention Control + 0x0 + 32 + 0x00000000 + 0x00007FFF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +bit00: soc_mem is kept on while cpu0 stop +bit01: soc_ctx is kept on while cpu0 stop +bit02: cpu0_mem is kept on while cpu0 stop +bit03: cpu0_ctx is kept on while cpu0 stop +bit04: xtal_hold is kept on while cpu0 stop +bit05: pll0_hold is kept on while cpu0 stop +bit06: pll1_hold is kept on while cpu0 stop + 0 + 15 + read-write + + + + + SET + Retention Control + 0x4 + 32 + 0x00000000 + 0x00007FFF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +0: no effect +1: keep + 0 + 15 + read-write + + + + + CLEAR + Retention Control + 0x8 + 32 + 0x00000000 + 0x00007FFF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +0: no effect +1: no keep + 0 + 15 + read-write + + + + + TOGGLE + Retention Control + 0xc + 32 + 0x00000000 + 0x00007FFF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +0: no effect +1: toggle the result that whether the resource is kept on while CPU0 stop before + 0 + 15 + read-write + + + + + + 1 + 0x14 + cpu0 + POWER[%s] + no description available + 0x1000 + + status + Power Setting + 0x0 + 32 + 0x80000000 + 0xC0031100 + + + FLAG + flag represents power cycle happened from last clear of this bit +0: power domain did not edurance power cycle since last clear of this bit +1: power domain enduranced power cycle since last clear of this bit + 31 + 1 + read-write + + + FLAG_WAKE + flag represents wakeup power cycle happened from last clear of this bit +0: power domain did not edurance wakeup power cycle since last clear of this bit +1: power domain enduranced wakeup power cycle since last clear of this bit + 30 + 1 + read-write + + + MEM_RET_N + memory info retention control signal +0: memory enter retention mode +1: memory exit retention mode + 17 + 1 + read-only + + + MEM_RET_P + memory info retention control signal +0: memory not enterexitretention mode +1: memory enter retention mode + 16 + 1 + read-only + + + LF_DISABLE + low fanout power switch disable +0: low fanout power switches are turned on +1: low fanout power switches are truned off + 12 + 1 + read-only + + + LF_ACK + low fanout power switch feedback +0: low fanout power switches are turned on +1: low fanout power switches are truned off + 8 + 1 + read-only + + + + + lf_wait + Power Setting + 0x4 + 32 + 0x000000FF + 0x000FFFFF + + + WAIT + wait time for low fan out power switch turn on, default value is 255 +0: 0 clock cycle +1: 1 clock cycles +. . . +clock cycles count on 24MHz + 0 + 20 + read-write + + + + + off_wait + Power Setting + 0xc + 32 + 0x0000000F + 0x000FFFFF + + + WAIT + wait time for power switch turn off, default value is 15 +0: 0 clock cycle +1: 1 clock cycles +. . . +clock cycles count on 24MHz + 0 + 20 + read-write + + + + + ret_wait + Power Setting + 0x10 + 32 + 0x0000000F + 0x000FFFFF + + + WAIT + wait time for memory retention mode transition, default value is 15 +0: 0 clock cycle +1: 1 clock cycles +. . . +clock cycles count on 24MHz + 0 + 20 + read-write + + + + + + 2 + 0x10 + soc,cpu0 + RESET[%s] + no description available + 0x1400 + + control + Reset Setting + 0x0 + 32 + 0x80000000 + 0xC0000011 + + + FLAG + flag represents reset happened from last clear of this bit +0: domain did not edurance reset cycle since last clear of this bit +1: domain enduranced reset cycle since last clear of this bit + 31 + 1 + read-write + + + FLAG_WAKE + flag represents wakeup reset happened from last clear of this bit +0: domain did not edurance wakeup reset cycle since last clear of this bit +1: domain enduranced wakeup reset cycle since last clear of this bit + 30 + 1 + read-write + + + HOLD + perform reset and hold in reset, until ths bit cleared by software +0: reset is released for function +1: reset is assert and hold + 4 + 1 + read-write + + + RESET + perform reset and release imediately +0: reset is released +1 reset is asserted and will release automatically + 0 + 1 + read-write + + + + + config + Reset Setting + 0x4 + 32 + 0x00402003 + 0x00FFFFFF + + + PRE_WAIT + wait cycle numbers before assert reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 16 + 8 + read-write + + + RSTCLK_NUM + reset clock number(must be even number) +0: 0 cycle +1: 0 cycles +2: 2 cycles +3: 2 cycles +. . . +Note, clock cycle is base on 24M + 8 + 8 + read-write + + + POST_WAIT + time guard band for reset release +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 8 + read-write + + + + + counter + Reset Setting + 0xc + 32 + 0x00000000 + 0x000FFFFF + + + COUNTER + self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 20 + read-write + + + + + + 1 + 0x4 + clk_top_cpu0 + CLOCK_CPU[%s] + no description available + 0x1800 + 32 + 0x00000000 + 0xD00F07FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + SUB0_DIV + ahb bus divider, the bus clock is generated by cpu_clock/div +0: divider by 1 +1: divider by 2 +… + 16 + 4 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll1_clk2 +7:pll1_clk3 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + 32 + 0x4 + clk_top_mct0,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,rsv5,rsv6,rsv7,rsv8,clk_top_tmr0,clk_top_tmr1,clk_top_tmr2,clk_top_tmr3,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_urt0,clk_top_urt1,clk_top_urt2,clk_top_urt3,clk_top_urt4,clk_top_urt5,clk_top_urt6,clk_top_urt7,clk_top_xpi0,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_ana3,clk_top_ref0,clk_top_ref1 + CLOCK[%s] + no description available + 0x1804 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll1_clk2 +7:pll1_clk3 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + 2 + 0x4 + clk_top_adc0,clk_top_adc1 + ADCCLK[%s] + no description available + 0x1c00 + 32 + 0x00000000 + 0xD0000100 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux +0: ahb0 clock N +1: ana clock + 8 + 1 + read-write + + + + + 2 + 0x4 + clk_top_dac0,clk_top_dac1 + DACCLK[%s] + no description available + 0x1c08 + 32 + 0x00000000 + 0xD0000100 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux +0: ahb0 clock N +1: ana clock + 8 + 1 + read-write + + + + + global00 + Clock senario + 0x2000 + 32 + 0x00000000 + 0x000000FF + + + MUX + global clock override request +bit0: override to preset0 +bit1: override to preset1 +bit2: override to preset2 +bit3: override to preset3 +bit4: override to preset4 +bit5: override to preset5 +bit6: override to preset6 +bit7: override to preset7 + 0 + 8 + read-write + + + + + 4 + 0x20 + slice0,slice1,slice2,slice3 + MONITOR[%s] + no description available + 0x2400 + + control + Clock measure and monitor control + 0x0 + 32 + 0x00000000 + 0x89FFD7FF + + + VALID + result is ready for read +0: not ready +1: result is ready + 31 + 1 + read-write + + + DIV_BUSY + divider is applying new setting + 27 + 1 + read-only + + + OUTEN + enable clock output + 24 + 1 + read-write + + + DIV + output divider + 16 + 8 + read-write + + + HIGH + clock frequency higher than upper limit + 15 + 1 + read-write + + + LOW + clock frequency lower than lower limit + 14 + 1 + read-write + + + START + start measurement + 12 + 1 + read-write + + + MODE + work mode, +0: register value will be compared to measurement +1: upper and lower value will be recordered in register + 10 + 1 + read-write + + + ACCURACY + measurement accuracy, +0: resolution is 1kHz +1: resolution is 1Hz + 9 + 1 + read-write + + + REFERENCE + reference clock selection, +0: 32k +1: 24M + 8 + 1 + read-write + + + SELECTION + clock measurement selection + 0 + 8 + read-write + + + + + current + Clock measure result + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + self updating measure result + 0 + 32 + read-only + + + + + low_limit + Clock lower limit + 0x8 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + FREQUENCY + lower frequency + 0 + 32 + read-write + + + + + high_limit + Clock upper limit + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + upper frequency + 0 + 32 + read-write + + + + + + 1 + 0x400 + cpu0 + CPU[%s] + no description available + 0x2800 + + LP + CPU0 LP control + 0x0 + 32 + 0x00001000 + 0xFF013703 + + + WAKE_CNT + CPU0 wake up counter, counter satuated at 255, write 0x00 to clear + 24 + 8 + read-write + + + HALT + halt request for CPU0, +0: CPU0 will start to execute after reset or receive wakeup request +1: CPU0 will not start after reset, or wakeup after WFI + 16 + 1 + read-write + + + WAKE + CPU0 is waking up +0: CPU0 wake up not asserted +1: CPU0 wake up asserted + 13 + 1 + read-only + + + EXEC + CPU0 is executing +0: CPU0 is not executing +1: CPU0 is executing + 12 + 1 + read-only + + + WAKE_FLAG + CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit +0: CPU0 wakeup not happened +1: CPU0 wake up happened + 10 + 1 + read-write + + + SLEEP_FLAG + CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit +0: CPU0 sleep not happened +1: CPU0 sleep happened + 9 + 1 + read-write + + + RESET_FLAG + CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit +0: CPU0 reset not happened +1: CPU0 reset happened + 8 + 1 + read-write + + + MODE + Low power mode, system behavior after WFI +00: CPU clock stop after WFI +01: System enter low power mode after WFI +10: Keep running after WFI +11: reserved + 0 + 2 + read-write + + + + + LOCK + CPU0 Lock GPR + 0x4 + 32 + 0x00000000 + 0x0000FFFE + + + GPR + Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset + 2 + 14 + read-write + + + LOCK + Lock bit for CPU_LOCK + 1 + 1 + read-write + + + + + 14 + 0x4 + GPR0,GPR1,GPR2,GPR3,GPR4,GPR5,GPR6,GPR7,GPR8,GPR9,GPR10,GPR11,GPR12,GPR13 + GPR[%s] + no description available + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + 4 + 0x4 + STATUS0,STATUS1,STATUS2,STATUS3 + WAKEUP_STATUS[%s] + no description available + 0x40 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + 4 + 0x4 + ENABLE0,ENABLE1,ENABLE2,ENABLE3 + WAKEUP_ENABLE[%s] + no description available + 0x80 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + + + + IOC + IOC + IOC + 0xf4040000 + + 0x0 + 0xe40 + registers + + + + 456 + 0x8 + pa00,pa01,pa02,pa03,pa04,pa05,pa06,pa07,pa08,pa09,pa10,pa11,pa12,pa13,pa14,pa15,pa16,pa17,pa18,pa19,pa20,pa21,pa22,pa23,pa24,pa25,pa26,pa27,pa28,pa29,pa30,pa31,pb00,pb01,pb02,pb03,pb04,pb05,pb06,pb07,pb08,pb09,pb10,pb11,pb12,pb13,pb14,pb15,rsv48,rsv49,rsv50,rsv51,rsv52,rsv53,rsv54,rsv55,rsv56,rsv57,rsv58,rsv59,rsv60,rsv61,rsv62,rsv63,rsv64,rsv65,rsv66,rsv67,rsv68,rsv69,rsv70,rsv71,rsv72,rsv73,rsv74,rsv75,rsv76,rsv77,rsv78,rsv79,rsv80,rsv81,rsv82,rsv83,rsv84,rsv85,rsv86,rsv87,rsv88,rsv89,rsv90,rsv91,rsv92,rsv93,rsv94,rsv95,rsv96,rsv97,rsv98,rsv99,rsv100,rsv101,rsv102,rsv103,rsv104,rsv105,rsv106,rsv107,rsv108,rsv109,rsv110,rsv111,rsv112,rsv113,rsv114,rsv115,rsv116,rsv117,rsv118,rsv119,rsv120,rsv121,rsv122,rsv123,rsv124,rsv125,rsv126,rsv127,rsv128,rsv129,rsv130,rsv131,rsv132,rsv133,rsv134,rsv135,rsv136,rsv137,rsv138,rsv139,rsv140,rsv141,rsv142,rsv143,rsv144,rsv145,rsv146,rsv147,rsv148,rsv149,rsv150,rsv151,rsv152,rsv153,rsv154,rsv155,rsv156,rsv157,rsv158,rsv159,rsv160,rsv161,rsv162,rsv163,rsv164,rsv165,rsv166,rsv167,rsv168,rsv169,rsv170,rsv171,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,rsv256,rsv257,rsv258,rsv259,rsv260,rsv261,rsv262,rsv263,rsv264,rsv265,rsv266,rsv267,rsv268,rsv269,rsv270,rsv271,rsv272,rsv273,rsv274,rsv275,rsv276,rsv277,rsv278,rsv279,rsv280,rsv281,rsv282,rsv283,rsv284,rsv285,rsv286,rsv287,rsv288,rsv289,rsv290,rsv291,rsv292,rsv293,rsv294,rsv295,rsv296,rsv297,rsv298,rsv299,rsv300,rsv301,rsv302,rsv303,rsv304,rsv305,rsv306,rsv307,rsv308,rsv309,rsv310,rsv311,rsv312,rsv313,rsv314,rsv315,rsv316,rsv317,rsv318,rsv319,rsv320,rsv321,rsv322,rsv323,rsv324,rsv325,rsv326,rsv327,rsv328,rsv329,rsv330,rsv331,rsv332,rsv333,rsv334,rsv335,rsv336,rsv337,rsv338,rsv339,rsv340,rsv341,rsv342,rsv343,rsv344,rsv345,rsv346,rsv347,rsv348,rsv349,rsv350,rsv351,rsv352,rsv353,rsv354,rsv355,rsv356,rsv357,rsv358,rsv359,rsv360,rsv361,rsv362,rsv363,rsv364,rsv365,rsv366,rsv367,rsv368,rsv369,rsv370,rsv371,rsv372,rsv373,rsv374,rsv375,rsv376,rsv377,rsv378,rsv379,rsv380,rsv381,rsv382,rsv383,rsv384,rsv385,rsv386,rsv387,rsv388,rsv389,rsv390,rsv391,rsv392,rsv393,rsv394,rsv395,rsv396,rsv397,rsv398,rsv399,rsv400,rsv401,rsv402,rsv403,rsv404,rsv405,rsv406,rsv407,rsv408,rsv409,rsv410,rsv411,rsv412,rsv413,rsv414,rsv415,px00,px01,px02,px03,px04,px05,px06,px07,rsv424,rsv425,rsv426,rsv427,rsv428,rsv429,rsv430,rsv431,rsv432,rsv433,rsv434,rsv435,rsv436,rsv437,rsv438,rsv439,rsv440,rsv441,rsv442,rsv443,rsv444,rsv445,rsv446,rsv447,py00,py01,py02,py03,py04,py05,py06,py07 + PAD[%s] + no description available + 0x0 + + FUNC_CTL + ALT SELECT + 0x0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +... +31:ALT31 + 0 + 5 + read-write + + + + + PAD_CTL + PAD SETTINGS + 0x4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + + + + PIOC + PIOC + IOC + 0xf4118000 + + + PLLCTLV2 + PLLCTLV2 + PLLCTLV2 + 0xf40c0000 + + 0x0 + 0x200 + registers + + + + XTAL + OSC configuration + 0x0 + 32 + 0x0001FFFF + 0xB00FFFFF + + + BUSY + Busy flag +0: Oscillator is working or shutdown +1: Oscillator is changing status + 31 + 1 + read-only + + + RESPONSE + Crystal oscillator status +0: Oscillator is not stable +1: Oscillator is stable for use + 29 + 1 + read-only + + + ENABLE + Crystal oscillator enable status +0: Oscillator is off +1: Oscillator is on + 28 + 1 + read-only + + + RAMP_TIME + Rampup time of XTAL oscillator in cycles of RC24M clock +0: 0 cycle +1: 1 cycle +2: 2 cycle +1048575: 1048575 cycles + 0 + 20 + read-write + + + + + 3 + 0x80 + pll0,pll1,pll2 + PLL[%s] + no description available + 0x80 + + MFI + PLL0 multiple register + 0x0 + 32 + 0x00000010 + 0xB000007F + + + BUSY + Busy flag +0: PLL is stable or shutdown +1: PLL is changing status + 31 + 1 + read-only + + + RESPONSE + PLL status +0: PLL is not stable +1: PLL is stable for use + 29 + 1 + read-only + + + ENABLE + PLL enable status +0: PLL is off +1: PLL is on + 28 + 1 + read-only + + + MFI + loop back divider of PLL, support from 13 to 42, f=fref*(mfi + mfn/mfd) +0-15: invalid +16: divide by 16 +17: divide by17 +. . . +42: divide by 42 +43~:invalid + 0 + 7 + read-write + + + + + MFN + PLL0 fraction numerator register + 0x4 + 32 + 0x09896800 + 0x3FFFFFFF + + + MFN + Numeratorof fractional part,f=fref*(mfi + mfn/mfd). This field supports changing while running. + 0 + 30 + read-write + + + + + MFD + PLL0 fraction demoninator register + 0x8 + 32 + 0x0E4E1C00 + 0x3FFFFFFF + + + MFD + Demoninator of fraction part,f=fref*(mfi + mfn/mfd). This field should not be changed during PLL enabled. If changed, change will take efftect when PLL re-enabled. + 0 + 30 + read-write + + + + + SS_STEP + PLL0 spread spectrum step register + 0xc + 32 + 0x00000000 + 0x3FFFFFFF + + + STEP + Step of spread spectrum modulator. +This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. + 0 + 30 + read-write + + + + + SS_STOP + PLL0 spread spectrum stop register + 0x10 + 32 + 0x00000000 + 0x3FFFFFFF + + + STOP + Stop point of spread spectrum modulator +This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. + 0 + 30 + read-write + + + + + CONFIG + PLL0 confguration register + 0x14 + 32 + 0x00000000 + 0x00000101 + + + SPREAD + Enable spread spectrum function. This field supports changing during PLL running. + 8 + 1 + read-write + + + REFSEL + Select reference clock, This filed support changing while running, but application must take frequency error and jitter into consideration. And if MFN changed before reference switch, application need make sure time is enough for MFN updating. +0: XTAL24M +1: IRC24M + 0 + 1 + read-write + + + + + LOCKTIME + PLL0 lock time register + 0x18 + 32 + 0x000009C4 + 0x0000FFFF + + + LOCKTIME + Lock time of PLL in 24M clock cycles, typical value is 2500. If MFI changed during PLL startup, PLL lock time may be longer than this setting. + 0 + 16 + read-write + + + + + STEPTIME + PLL0 step time register + 0x1c + 32 + 0x000009C4 + 0x0000FFFF + + + STEPTIME + Step time for MFI on-the-fly change in 24M clock cycles, typical value is 2500. + 0 + 16 + read-write + + + + + ADVANCED + PLL0 advance configuration register + 0x20 + 32 + 0x00000000 + 0x11000000 + + + SLOW + Use slow lock flow, PLL lock expendite is disabled. This mode might be stabler. And software need config LOCKTIME field accordingly. +0: fast lock enabled, lock time is 100us +1: fast lock disabled, lock time is 400us + 28 + 1 + read-write + + + DITHER + Enable dither function + 24 + 1 + read-write + + + + + 3 + 0x4 + DIV0,DIV1,DIV2 + DIV[%s] + no description available + 0x40 + 32 + 0x00000000 + 0xB000003F + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Divider response status +0: Divider is not stable +1: Divider is stable for use + 29 + 1 + read-only + + + ENABLE + Divider enable status +0: Divider is off +1: Divider is on + 28 + 1 + read-only + + + DIV + Divider factor, divider factor is DIV/5 + 1 +0: divide by 1 +1: divide by 1.2 +2: divide by 1.4 +. . . +63: divide by 13.6 + 0 + 6 + read-write + + + + + + + + PPOR + PPOR + PPOR + 0xf4100000 + + 0x0 + 0x20 + registers + + + + RESET_FLAG + flag indicate reset source + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FLAG + reset reason of last hard reset, write 1 to clear each bit +0: brownout +1: temperature +4: debug reset +5: jtag soft reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2(not available) +19: watch dog 3(not available) +24: pmic watch dog +30: jtag ieee reset +31: software + 0 + 32 + write-only + + + + + RESET_STATUS + reset source status + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + current status of reset sources +0: brownout +1: temperature +4: debug reset +5: jtag soft reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2(not available) +19: watch dog 3(not available) +24: pmic watch dog +30: jtag ieee reset +31: software + 0 + 32 + read-only + + + + + RESET_HOLD + reset hold attribute + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + HOLD + hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status +0: brownout +1: temperature +4: debug reset +5: jtag soft reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2(not available) +19: watch dog 3(not available) +24: pmic watch dog +30: jtag ieee reset +31: software + 0 + 32 + read-write + + + + + RESET_ENABLE + reset source enable + 0xc + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + ENABLE + enable of reset sources +0: brownout +1: temperature +4: debug reset +5: jtag soft reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2(not available) +19: watch dog 3(not available) +24: pmic watch dog +30: jtag ieee reset +31: software + 0 + 32 + read-write + + + + + RESET_TYPE + reset type triggered by reset + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + TYPE + reset type of reset sources, 0 for cold reset, all system control setting cleared except debug/fuse/ioc; 1 for hot reset, keep system control setting and debug/fuse/ioc setting, only clear some subsystem +0: brownout +1: temperature +4: debug reset +5: jtag soft reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2(not available) +19: watch dog 3(not available) +24: pmic watch dog +30: jtag ieee reset +31: software + 0 + 32 + read-write + + + + + SOFTWARE_RESET + Software reset counter + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset + 0 + 32 + read-write + + + + + + + PCFG + PCFG + PMU + 0xf4104000 + + 0x0 + 0x70 + registers + + + + BANDGAP + BANGGAP control + 0x0 + 32 + 0x00101010 + 0x801F1F1F + + + VBG_TRIMMED + Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: bandgap is not trimmed +1: bandgap is trimmed + 31 + 1 + read-write + + + VBG_1P0_TRIM + Banggap 1.0V output trim value + 16 + 5 + read-write + + + VBG_P65_TRIM + Banggap 1.0V output trim value + 8 + 5 + read-write + + + VBG_P50_TRIM + Banggap 1.0V output trim value + 0 + 5 + read-write + + + + + LDO1P1 + 1V LDO config + 0x4 + 32 + 0x0000044C + 0x00000FFF + + + VOLT + LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. +700: 700mV +720: 720mV +. . . +1320:1320mV + 0 + 12 + read-write + + + + + LDO2P5 + 2.5V LDO config + 0x8 + 32 + 0x000009C4 + 0x10010FFF + + + READY + Ready flag, will set 1ms after enabled or voltage change +0: LDO is not ready for use +1: LDO is ready + 28 + 1 + read-only + + + ENABLE + LDO enable +0: turn off LDO +1: turn on LDO + 16 + 1 + read-write + + + VOLT + LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. +2125: 2125mV +2150: 2150mV +. . . +2900:2900mV + 0 + 12 + read-write + + + + + DCDC_MODE + DCDC mode select + 0x10 + 32 + 0x0001047E + 0x10070FFF + + + READY + Ready flag +0: DCDC is applying new change +1: DCDC is ready + 28 + 1 + read-only + + + MODE + DCDC work mode +XX0: turn off +001: basic mode +011: generic mode +101: automatic mode +111: expert mode + 16 + 3 + read-write + + + VOLT + DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. +600: 600mV +625: 625mV +. . . +1375:1375mV + 0 + 12 + read-write + + + + + DCDC_LPMODE + DCDC low power mode + 0x14 + 32 + 0x00000384 + 0x00000FFF + + + STBY_VOLT + DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. +600: 600mV +625: 625mV +. . . +1375:1375mV + 0 + 12 + read-write + + + + + DCDC_PROT + DCDC protection + 0x18 + 32 + 0x00000010 + 0x11018191 + + + ILIMIT_LP + over current setting for low power mode +0:250mA +1:200mA + 28 + 1 + read-write + + + OVERLOAD_LP + over current in low power mode +0: current is below setting +1: overcurrent happened in low power mode + 24 + 1 + read-only + + + POWER_LOSS_FLAG + power loss +0: input power is good +1: input power is too low + 16 + 1 + read-only + + + DISABLE_OVERVOLTAGE + output over voltage protection +0: protection enabled, DCDC will shut down is output voltage is unexpected high +1: protection disabled, DCDC continue to adjust output voltage + 15 + 1 + read-write + + + OVERVOLT_FLAG + output over voltage flag +0: output is normal +1: output is unexpected high + 8 + 1 + read-only + + + DISABLE_SHORT + disable output short circuit protection +0: short circuits protection enabled, DCDC shut down if short circuit on output detected +1: short circuit protection disabled + 7 + 1 + read-write + + + SHORT_CURRENT + short circuit current setting +0: 2.0A, +1: 1.3A + 4 + 1 + read-write + + + SHORT_FLAG + short circuit flag +0: current is within limit +1: short circuits detected + 0 + 1 + read-only + + + + + DCDC_CURRENT + DCDC current estimation + 0x1c + 32 + 0x00000000 + 0x0000811F + + + ESTI_EN + enable current measure + 15 + 1 + read-write + + + VALID + Current level valid +0: data is invalid +1: data is valid + 8 + 1 + read-only + + + LEVEL + DCDC current level, current level is num * 50mA + 0 + 5 + read-only + + + + + DCDC_ADVMODE + DCDC advance setting + 0x20 + 32 + 0x03120040 + 0x073F007F + + + EN_RCSCALE + Enable RC scale + 24 + 3 + read-write + + + DC_C + Loop C number + 20 + 2 + read-write + + + DC_R + Loop R number + 16 + 4 + read-write + + + EN_FF_DET + enable feed forward detect +0: feed forward detect is disabled +1: feed forward detect is enabled + 6 + 1 + read-write + + + EN_FF_LOOP + enable feed forward loop +0: feed forward loop is disabled +1: feed forward loop is enabled + 5 + 1 + read-write + + + EN_AUTOLP + enable auto enter low power mode +0: do not enter low power mode +1: enter low power mode if current is detected low + 4 + 1 + read-write + + + EN_DCM_EXIT + avoid over voltage +0: stay in DCM mode when voltage excess +1: change to CCM mode when voltage excess + 3 + 1 + read-write + + + EN_SKIP + enable skip on narrow pulse +0: do not skip narrow pulse +1: skip narrow pulse + 2 + 1 + read-write + + + EN_IDLE + enable skip when voltage is higher than threshold +0: do not skip +1: skip if voltage is excess + 1 + 1 + read-write + + + EN_DCM + DCM mode +0: CCM mode +1: DCM mode + 0 + 1 + read-write + + + + + DCDC_ADVPARAM + DCDC advance parameter + 0x24 + 32 + 0x00006E1C + 0x00007F7F + + + MIN_DUT + minimum duty cycle + 8 + 7 + read-write + + + MAX_DUT + maximum duty cycle + 0 + 7 + read-write + + + + + DCDC_MISC + DCDC misc parameter + 0x28 + 32 + 0x00070100 + 0x13170317 + + + EN_HYST + hysteres enable + 28 + 1 + read-write + + + HYST_SIGN + hysteres sign + 25 + 1 + read-write + + + HYST_THRS + hysteres threshold + 24 + 1 + read-write + + + RC_SCALE + Loop RC scale threshold + 20 + 1 + read-write + + + DC_FF + Loop feed forward number + 16 + 3 + read-write + + + OL_THRE + overload for threshold for lod power mode + 8 + 2 + read-write + + + OL_HYST + current hysteres range +0: 12.5mV +1: 25mV + 4 + 1 + read-write + + + DELAY + enable delay +0: delay disabled, +1: delay enabled + 2 + 1 + read-write + + + CLK_SEL + clock selection +0: select DCDC internal oscillator +1: select RC24M oscillator + 1 + 1 + read-write + + + EN_STEP + enable stepping in voltage change +0: stepping disabled, +1: steping enabled + 0 + 1 + read-write + + + + + DCDC_DEBUG + DCDC Debug + 0x2c + 32 + 0x00005DBF + 0x000FFFFF + + + UPDATE_TIME + DCDC voltage change time in 24M clock cycles, default value is 1mS + 0 + 20 + read-write + + + + + DCDC_START_TIME + DCDC ramp time + 0x30 + 32 + 0x0001193F + 0x000FFFFF + + + START_TIME + Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS + 0 + 20 + read-write + + + + + DCDC_RESUME_TIME + DCDC resume time + 0x34 + 32 + 0x00008C9F + 0x000FFFFF + + + RESUME_TIME + Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS + 0 + 20 + read-write + + + + + POWER_TRAP + SOC power trap + 0x40 + 32 + 0x00000000 + 0x80010001 + + + TRIGGERED + Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. +0: low power trap is not triggered +1: low power trap triggered + 31 + 1 + read-write + + + RETENTION + DCDC enter standby mode, which will reduce voltage for memory content retention +0: Shutdown DCDC +1: reduce DCDC voltage + 16 + 1 + read-write + + + TRAP + Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered +0: trap not enabled, pmic side low power function disabled +1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. + 0 + 1 + read-write + + + + + WAKE_CAUSE + Wake up source + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAUSE + wake up cause, each bit represents one wake up source, write 1 to clear the register bit +0: wake up source is not active during last wakeup +1: wake up source is active furing last wakeup +bit 0: pmic_enable +bit 7: UART interrupt +bit 8: TMR interrupt +bit 9: WDG interrupt +bit10: GPIO in PMIC interrupt +bit31: pin wakeup + 0 + 32 + read-write + + + + + WAKE_MASK + Wake up mask + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + MASK + mask for wake up sources, each bit represents one wakeup source +0: allow source to wake up system +1: disallow source to wakeup system +bit 0: pmic_enable +bit 7: UART interrupt +bit 8: TMR interrupt +bit 9: WDG interrupt +bit10: GPIO in PMIC interrupt +bit31: pin wakeup + 0 + 32 + read-write + + + + + SCG_CTRL + Clock gate control in PMIC + 0x4c + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + SCG + control whether clock being gated during PMIC low power flow, 2 bits for each peripheral +00,01: reserved +10: clock is always off +11: clock is always on +bit6-7:gpio +bit8-9:ioc +bit10-11: timer +bit12-13:wdog +bit14-15:uart + 0 + 32 + read-write + + + + + RC24M + RC 24M config + 0x60 + 32 + 0x00000310 + 0x8000071F + + + RC_TRIMMED + RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: RC is not trimmed +1: RC is trimmed + 31 + 1 + read-write + + + TRIM_C + Coarse trim for RC24M, bigger value means faster + 8 + 3 + read-write + + + TRIM_F + Fine trim for RC24M, bigger value means faster + 0 + 5 + read-write + + + + + RC24M_TRACK + RC 24M track mode + 0x64 + 32 + 0x00000000 + 0x00010011 + + + SEL24M + Select track reference +0: select 32K as reference +1: select 24M XTAL as reference + 16 + 1 + read-write + + + RETURN + Retrun default value when XTAL loss +0: remain last tracking value +1: switch to default value + 4 + 1 + read-write + + + TRACK + track mode +0: RC24M free running +1: track RC24M to external XTAL + 0 + 1 + read-write + + + + + TRACK_TARGET + RC 24M track target + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRE_DIV + Divider for reference source + 16 + 16 + read-write + + + TARGET + Target frequency multiplier of divided source + 0 + 16 + read-write + + + + + STATUS + RC 24M track status + 0x6c + 32 + 0x00000000 + 0x0011871F + + + SEL32K + track is using XTAL32K +0: track is not using XTAL32K +1: track is using XTAL32K + 20 + 1 + read-only + + + SEL24M + track is using XTAL24M +0: track is not using XTAL24M +1: track is using XTAL24M + 16 + 1 + read-only + + + EN_TRIM + default value takes effect +0: default value is invalid +1: default value is valid + 15 + 1 + read-only + + + TRIM_C + default coarse trim value + 8 + 3 + read-only + + + TRIM_F + default fine trim value + 0 + 5 + read-only + + + + + + + PGPR0 + PGPR0 + PGPR + 0xf4110000 + + 0x0 + 0x40 + registers + + + + PMIC_GPR00 + Generic control + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR01 + Generic control + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR02 + Generic control + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR03 + Generic control + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR04 + Generic control + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR05 + Generic control + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR06 + Generic control + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR07 + Generic control + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR08 + Generic control + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR09 + Generic control + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR10 + Generic control + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR11 + Generic control + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR12 + Generic control + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR13 + Generic control + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR14 + Generic control + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR15 + Generic control + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + + + PGPR1 + PGPR1 + PGPR + 0xf4114000 + + + PDGO + PDGO + PDGO + 0xf4134000 + + 0x0 + 0x714 + registers + + + + DGO_TURNOFF + trunoff control + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + trunoff counter, counter stops when it counts down to 0, the trunoff occurs when the counter value is 1. + 0 + 32 + write-only + + + + + DGO_RC32K_CFG + RC32K CLOCK + 0x4 + 32 + 0x00000000 + 0x80C001FF + + + IRC_TRIMMED + IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: irc is not trimmed +1: irc is trimmed + 31 + 1 + read-write + + + CAPEX7_TRIM + IRC32K bit 7 + 23 + 1 + read-write + + + CAPEX6_TRIM + IRC32K bit 6 + 22 + 1 + read-write + + + CAP_TRIM + capacitor trim bits + 0 + 9 + read-write + + + + + DGO_GPR00 + Generic control 0 + 0x600 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + DGO_GPR01 + Generic control 1 + 0x604 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + DGO_GPR02 + Generic control 2 + 0x608 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + DGO_GPR03 + Generic control 3 + 0x60c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + DGO_CTR0 + control register 0 + 0x700 + 32 + 0x00000000 + 0x00010000 + + + RETENTION + dgo register status retenion + 16 + 1 + read-write + + + + + DGO_CTR1 + control register 1 + 0x704 + 32 + 0x00000000 + 0x80010001 + + + AOTO_SYS_WAKEUP + software wakeup： 0 : wakeup once； 1：auto wakeup Continuously + 31 + 1 + read-write + + + WAKEUP_EN + permit wakeup pin or software wakeup + 16 + 1 + read-write + + + PIN_WAKEUP_STATUS + wakeup pin status + 0 + 1 + read-only + + + + + DGO_CTR2 + control register 2 + 0x708 + 32 + 0x00000000 + 0x01010000 + + + RESETN_PULLUP_DISABLE + resetn pin pull up disable + 24 + 1 + read-write + + + WAKEUP_PULLDN_DISABLE + wakeup pin pull down disable + 16 + 1 + read-write + + + + + DGO_CTR3 + control register 3 + 0x70c + 32 + 0x00000000 + 0xFFFFFFFF + + + WAKEUP_COUNTER + software wakeup counter + 0 + 32 + read-write + + + + + DGO_CTR4 + control register 4 + 0x710 + 32 + 0x00000000 + 0x00000003 + + + BANDGAP_LESS_POWER + Banggap work in power save mode, banggap function normally +0: banggap works in high performance mode +1: banggap works in power saving mode + 1 + 1 + read-write + + + BANDGAP_LP_MODE + Banggap work in low power mode, banggap function limited +0: banggap works in normal mode +1: banggap works in low power mode + 0 + 1 + read-write + + + + + + + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/SConscript b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/SConscript new file mode 100644 index 00000000000..dd355f33b20 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/SConscript @@ -0,0 +1,24 @@ +import os +import sys +Import('rtconfig') +from building import * + +#get current directory +cwd = GetCurrentDir() + +# Update include path +path = [ cwd, cwd + '/boot' ] + +# The set of source files associated with this SConscript file. +src = Split(''' + system.c + hpm_l1c_drv.c + hpm_sysctl_drv.c + hpm_clock_drv.c + hpm_otp_drv.c + boot/hpm_bootheader.c +''') + +group = DefineGroup('SoC', src, depend = [''], CPPPATH = path) + +Return ('group') diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/boot/hpm_bootheader.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/boot/hpm_bootheader.c new file mode 100644 index 00000000000..57cdf5aa2e6 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/boot/hpm_bootheader.c @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_bootheader.h" + +/* symbol exported from startup.S */ +extern uint32_t _start[]; + +/* following symbols exported from linker script */ +extern uint32_t __app_load_addr__[]; +extern uint32_t __app_offset__[]; +extern uint32_t __fw_size__[]; + +#define FW_SIZE (32768) +__attribute__ ((section(".fw_info_table"))) const fw_info_table_t fw_info = { + (uint32_t)__app_offset__, /* offset */ + (uint32_t)__fw_size__, /* size */ + 0, /* flags */ + 0, /* reserved0 */ + (uint32_t) &__app_load_addr__, /* load_addr */ + 0, /* reserved1 */ + (uint32_t) _start, /* entry_point */ + 0, /* reserved2 */ + {0}, /* hash */ + {0}, /* iv */ +}; + +__attribute__ ((section(".boot_header"))) const boot_header_t header = { + HPM_BOOTHEADER_TAG, /* tag */ + 0x10, /* version*/ + sizeof(header) + sizeof(fw_info), + 0, /* flags */ + 0, /* sw_version */ + 0, /* fuse_version */ + 1, /* fw_count */ + 0, + 0, /* sig_block_offset */ +}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/boot/hpm_bootheader.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/boot/hpm_bootheader.h new file mode 100644 index 00000000000..d7f22fd8240 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/boot/hpm_bootheader.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_BOOT_HEADER_H +#define HPM_BOOT_HEADER_H + +#include "hpm_common.h" + +#define HPM_BOOTHEADER_TAG (0xBFU) +#define HPM_BOOTHEADER_MAX_FW_COUNT (2U) + +#ifndef HPM_BOOT_FW_COUNT +#define HPM_BOOT_FW_COUNT 1 +#endif + +#if HPM_BOOT_FW_COUNT < 1 +#error "HPM_BOOT_FW_COUNT can't be less than 1" +#endif + +typedef struct { + uint32_t offset; /* 0x0: offset to boot_header start */ + uint32_t size; /* 0x4: size in bytes */ + uint32_t flags; /* 0x8: [3:0] fw type: */ + /* 0 - executable */ + /* 1 - cmd container */ + /* [11:8] - hash type */ + /* 0 - none */ + /* 1 - sha256 */ + /* 2 - sm3 */ + uint32_t reserved0; /* 0xC */ + uint32_t load_addr; /* 0x10: load address */ + uint32_t reserved1; /* 0x14 */ + uint32_t entry_point; /* 0x18: application entry */ + uint32_t reserved2; /* 0x1C */ + uint8_t hash[64]; /* 0x20: hash value */ + uint8_t iv[32]; /* 0x60: initial vector */ +} fw_info_table_t; + +typedef struct { + uint8_t tag; /* 0x0: must be '0xbf' */ + uint8_t version; /* 0x1: header version */ + uint16_t length; /* 0x2: header length, max 8KB */ + uint32_t flags; /* 0x4: [3:0] SRK set */ + /* [7:4] SRK index */ + /* [15:8] SRK_REVOKE_MASK */ + /* [19:16] Signature Type */ + /* 1: ECDSA */ + /* 2: SM2 */ + uint16_t sw_version; /* 0x8: software version */ + uint8_t fuse_version; /* 0xA: fuse version */ + uint8_t fw_count; /* 0xB: number of fw */ + uint16_t dc_block_offset; /* 0xC: device config block offset*/ + uint16_t sig_block_offset; /* 0xE: signature block offset */ + /* + * fw_info_table_t fw_info[HPM_BOOT_FW_COUNT]; [> 0x10: fw table <] + * uint32_t dc_info[]; [> <] + */ +} boot_header_t; + +#endif /* HPM_BOOT_HEADER_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_clock_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_clock_drv.c new file mode 100644 index 00000000000..b0c7268ff2d --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_clock_drv.c @@ -0,0 +1,536 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_clock_drv.h" +#include "hpm_sysctl_drv.h" +#include "hpm_soc.h" +#include "hpm_common.h" +#include "hpm_pllctlv2_drv.h" +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/* Clock preset values */ +#define FREQ_PRESET1_OSC0_CLK0 (24000000UL) +#define FREQ_PRESET1_PLL0_CLK0 (720000000UL) +#define FREQ_PRESET1_PLL0_CLK1 (600000000UL) +#define FREQ_PRESET1_PLL0_CLK2 (400000000UL) +#define FREQ_PRESET1_PLL1_CLK0 (800000000UL) +#define FREQ_PRESET1_PLL1_CLK1 (666000000UL) +#define FREQ_PRESET1_PLL1_CLK2 (500000000UL) +#define FREQ_PRESET1_PLL1_CLK3 (266000000UL) +#define FREQ_32KHz (32768UL) +#define ADC_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->ADCCLK) +#define DAC_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->DACCLK) +#define WDG_INSTANCE_NUM (2U) +#define BUS_FREQ_MAX (200000000UL) +#define FREQ_1MHz (1000000UL) + +/* Clock On/Off definitions */ +#define CLOCK_ON (true) +#define CLOCK_OFF (false) + + +/*********************************************************************************************************************** + * Prototypes + **********************************************************************************************************************/ + +/** + * @brief Get Clock frequency for IP in common group + */ +static uint32_t get_frequency_for_ip_in_common_group(clock_node_t node); + +/** + * @brief Get Clock frequency for ADC + */ +static uint32_t get_frequency_for_adc(uint32_t clk_src_type, uint32_t instance); + +/** + * @brief Get Clock frequency for DAC + */ +static uint32_t get_frequency_for_dac(uint32_t instance); + +/** + * @brief Get Clock frequency for WDG + */ +static uint32_t get_frequency_for_ewdg(uint32_t instance); + +/** + * @brief Get Clock frequency for PWDG + */ +static uint32_t get_frequency_for_pewdg(void); + +/** + * @brief Turn on/off the IP clock + */ +static void switch_ip_clock(clock_name_t clock_name, bool on); + +static uint32_t get_frequency_for_cpu(void); +static uint32_t get_frequency_for_ahb(void); + + +/*********************************************************************************************************************** + * Variables + **********************************************************************************************************************/ +static const clock_node_t s_adc_clk_mux_node[] = { + clock_node_ahb, + clock_node_ana0 +}; + +static const clock_node_t s_dac_clk_mux_node[] = { + clock_node_ahb, + clock_node_ana2 +}; + +static EWDG_Type *const s_wdgs[] = { HPM_EWDG0, HPM_EWDG1}; + +uint32_t hpm_core_clock; + + +/*********************************************************************************************************************** + * Codes + **********************************************************************************************************************/ +uint32_t clock_get_frequency(clock_name_t clock_name) +{ + uint32_t clk_freq = 0UL; + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + switch (clk_src_type) { + case CLK_SRC_GROUP_COMMON: + clk_freq = get_frequency_for_ip_in_common_group((clock_node_t) node_or_instance); + break; + case CLK_SRC_GROUP_ADC: + clk_freq = get_frequency_for_adc(CLK_SRC_GROUP_ADC, node_or_instance); + break; + case CLK_SRC_GROUP_DAC: + clk_freq = get_frequency_for_dac(node_or_instance); + break; + case CLK_SRC_GROUP_EWDG: + clk_freq = get_frequency_for_ewdg(node_or_instance); + break; + case CLK_SRC_GROUP_PEWDG: + clk_freq = get_frequency_for_pewdg(); + break; + case CLK_SRC_GROUP_PMIC: + clk_freq = FREQ_PRESET1_OSC0_CLK0; + break; + case CLK_SRC_GROUP_CPU0: + clk_freq = get_frequency_for_cpu(); + break; + case CLK_SRC_GROUP_AHB: + clk_freq = get_frequency_for_ahb(); + break; + case CLK_SRC_GROUP_SRC: + clk_freq = get_frequency_for_source((clock_source_t) node_or_instance); + break; + default: + clk_freq = 0UL; + break; + } + return clk_freq; +} + +uint32_t get_frequency_for_source(clock_source_t source) +{ + uint32_t clk_freq = 0UL; + switch (source) { + case clock_source_osc0_clk0: + clk_freq = FREQ_PRESET1_OSC0_CLK0; + break; + case clock_source_pll0_clk0: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 0U); + break; + case clock_source_pll0_clk1: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 1U); + break; + case clock_source_pll0_clk2: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 2U); + break; + case clock_source_pll1_clk0: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 0U); + break; + case clock_source_pll1_clk1: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 1U); + break; + case clock_source_pll1_clk2: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 2U); + break; + case clock_source_pll1_clk3: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 3U); + break; + default: + clk_freq = 0UL; + break; + } + + return clk_freq; +} + +static uint32_t get_frequency_for_ip_in_common_group(clock_node_t node) +{ + uint32_t clk_freq = 0UL; + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(node); + + if (node_or_instance < clock_node_end) { + uint32_t clk_node = (uint32_t) node_or_instance; + + uint32_t clk_div = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[clk_node]); + clock_source_t clk_mux = (clock_source_t) SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[clk_node]); + clk_freq = get_frequency_for_source(clk_mux) / clk_div; + } + return clk_freq; +} + +static uint32_t get_frequency_for_adc(uint32_t clk_src_type, uint32_t instance) +{ + uint32_t clk_freq = 0UL; + bool is_mux_valid = false; + clock_node_t node = clock_node_end; + uint32_t adc_index = instance; + + (void) clk_src_type; + + if (adc_index < ADC_INSTANCE_NUM) { + uint32_t mux_in_reg = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[adc_index]); + if (mux_in_reg < ARRAY_SIZE(s_adc_clk_mux_node)) { + node = s_adc_clk_mux_node[mux_in_reg]; + is_mux_valid = true; + } + } + + if (is_mux_valid) { + if (node != clock_node_ahb) { + node += instance; + clk_freq = get_frequency_for_ip_in_common_group(node); + } else { + clk_freq = get_frequency_for_ahb(); + } + } + return clk_freq; +} + +static uint32_t get_frequency_for_dac(uint32_t instance) +{ + uint32_t clk_freq = 0UL; + bool is_mux_valid = false; + clock_node_t node = clock_node_end; + if (instance < DAC_INSTANCE_NUM) { + uint32_t mux_in_reg = SYSCTL_DACCLK_MUX_GET(HPM_SYSCTL->DACCLK[instance]); + if (mux_in_reg < ARRAY_SIZE(s_dac_clk_mux_node)) { + node = s_dac_clk_mux_node[mux_in_reg]; + is_mux_valid = true; + } + } + + if (is_mux_valid) { + if (node == clock_node_ahb) { + clk_freq = get_frequency_for_ahb(); + } else { + node += instance; + clk_freq = get_frequency_for_ip_in_common_group(node); + } + } + + return clk_freq; +} + +static uint32_t get_frequency_for_ewdg(uint32_t instance) +{ + uint32_t freq_in_hz; + if (EWDG_CTRL0_CLK_SEL_GET(s_wdgs[instance]->CTRL0) == 0) { + freq_in_hz = get_frequency_for_ahb(); + } else { + freq_in_hz = FREQ_32KHz; + } + + return freq_in_hz; +} + +static uint32_t get_frequency_for_pewdg(void) +{ + uint32_t freq_in_hz; + if (EWDG_CTRL0_CLK_SEL_GET(HPM_PEWDG->CTRL0) == 0) { + freq_in_hz = FREQ_PRESET1_OSC0_CLK0; + } else { + freq_in_hz = FREQ_32KHz; + } + + return freq_in_hz; +} + +static uint32_t get_frequency_for_cpu(void) +{ + uint32_t mux = SYSCTL_CLOCK_CPU_MUX_GET(HPM_SYSCTL->CLOCK_CPU[0]); + uint32_t div = SYSCTL_CLOCK_CPU_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]) + 1U; + return (get_frequency_for_source(mux) / div); +} + +static uint32_t get_frequency_for_ahb(void) +{ + uint32_t div = SYSCTL_CLOCK_CPU_SUB0_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]) + 1U; + return (get_frequency_for_cpu() / div); +} + +clk_src_t clock_get_source(clock_name_t clock_name) +{ + uint8_t clk_src_group = CLK_SRC_GROUP_INVALID; + uint8_t clk_src_index = 0xFU; + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + switch (clk_src_type) { + case CLK_SRC_GROUP_COMMON: + clk_src_group = CLK_SRC_GROUP_COMMON; + clk_src_index = SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[node_or_instance]); + break; + case CLK_SRC_GROUP_ADC: + if (node_or_instance < ADC_INSTANCE_NUM) { + clk_src_group = CLK_SRC_GROUP_ADC; + clk_src_index = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[node_or_instance]); + } + break; + case CLK_SRC_GROUP_DAC: + if (node_or_instance < DAC_INSTANCE_NUM) { + clk_src_group = CLK_SRC_GROUP_DAC; + clk_src_index = SYSCTL_DACCLK_MUX_GET(HPM_SYSCTL->DACCLK[node_or_instance]); + } + break; + case CLK_SRC_GROUP_EWDG: + if (node_or_instance < WDG_INSTANCE_NUM) { + clk_src_group = CLK_SRC_GROUP_EWDG; + clk_src_index = EWDG_CTRL0_CLK_SEL_GET(s_wdgs[node_or_instance]->CTRL0); + } + break; + case CLK_SRC_GROUP_PEWDG: + clk_src_group = CLK_SRC_GROUP_PEWDG; + clk_src_index = EWDG_CTRL0_CLK_SEL_GET(HPM_PEWDG->CTRL0); + break; + case CLK_SRC_GROUP_PMIC: + clk_src_group = CLK_SRC_GROUP_COMMON; + clk_src_index = clock_source_osc0_clk0; + break; + case CLK_SRC_GROUP_CPU0: + case CLK_SRC_GROUP_AHB: + clk_src_group = CLK_SRC_GROUP_CPU0; + clk_src_index = SYSCTL_CLOCK_CPU_MUX_GET(HPM_SYSCTL->CLOCK_CPU[0]); + break; + case CLK_SRC_GROUP_SRC: + clk_src_index = (clk_src_t) node_or_instance; + break; + default: + clk_src_group = CLK_SRC_GROUP_INVALID; + break; + } + + clk_src_t clk_src; + if (clk_src_group != CLK_SRC_GROUP_INVALID) { + clk_src = MAKE_CLK_SRC(clk_src_group, clk_src_index); + } else { + clk_src = clk_src_invalid; + } + + return clk_src; +} + +uint32_t clock_get_divider(clock_name_t clock_name) +{ + uint32_t clk_divider = CLOCK_DIV_INVALID; + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + switch (clk_src_type) { + case CLK_SRC_GROUP_COMMON: + clk_divider = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[node_or_instance]); + break; + case CLK_SRC_GROUP_EWDG: + clk_divider = 1; + break; + case CLK_SRC_GROUP_PEWDG: + clk_divider = 1; + break; + case CLK_SRC_GROUP_PMIC: + clk_divider = 1; + break; + case CLK_SRC_GROUP_CPU0: + clk_divider = 1UL + SYSCTL_CLOCK_CPU_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]); + break; + case CLK_SRC_GROUP_AHB: + clk_divider = 1UL + SYSCTL_CLOCK_CPU_SUB0_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]); + break; + default: + clk_divider = CLOCK_DIV_INVALID; + break; + } + return clk_divider; +} + +hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src) +{ + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + + if ((clk_src_type != CLK_SRC_GROUP_ADC) || (node_or_instance >= ADC_INSTANCE_NUM)) { + return status_clk_invalid; + } + + if ((src < clk_adc_src_ahb0) || (src > clk_adc_src_ana1)) { + return status_clk_src_invalid; + } + + uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); + HPM_SYSCTL->ADCCLK[node_or_instance] = + (HPM_SYSCTL->ADCCLK[node_or_instance] & ~SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(clk_src_index); + + return status_success; +} + +hpm_stat_t clock_set_dac_source(clock_name_t clock_name, clk_src_t src) +{ + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + + if ((clk_src_type != CLK_SRC_GROUP_DAC) || (node_or_instance >= DAC_INSTANCE_NUM)) { + return status_clk_invalid; + } + + if ((src < clk_dac_src_ahb0) || (src > clk_dac_src_ana3)) { + return status_clk_src_invalid; + } + + uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); + HPM_SYSCTL->DACCLK[node_or_instance] = + (HPM_SYSCTL->DACCLK[node_or_instance] & ~SYSCTL_DACCLK_MUX_MASK) | SYSCTL_DACCLK_MUX_SET(clk_src_index); + + return status_success; +} + +hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint32_t div) +{ + hpm_stat_t status = status_success; + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + switch (clk_src_type) { + case CLK_SRC_GROUP_COMMON: + if ((div < 1U) || (div > 256U)) { + status = status_clk_div_invalid; + } else { + clock_source_t clk_src = GET_CLOCK_SOURCE_FROM_CLK_SRC(src); + sysctl_config_clock(HPM_SYSCTL, (clock_node_t) node_or_instance, clk_src, div); + } + break; + case CLK_SRC_GROUP_ADC: + case CLK_SRC_GROUP_DAC: + case CLK_SRC_GROUP_EWDG: + case CLK_SRC_GROUP_PEWDG: + case CLK_SRC_GROUP_SRC: + status = status_clk_operation_unsupported; + break; + case CLK_SRC_GROUP_PMIC: + status = status_clk_fixed; + break; + case CLK_SRC_GROUP_AHB: + status = status_clk_shared_cpu0; + break; + case CLK_SRC_GROUP_CPU0: + if (node_or_instance == clock_node_cpu0) { + /* Note: the AXI and AHB BUS share the same CPU clock, once the CPU clock frequency + * changes, the AXI and AHB clock changes accordingly, here the driver ensures the + * AXI and AHB bus clock frequency is in valid range. + */ + uint32_t expected_freq = get_frequency_for_source((clock_source_t) src) / div; + uint32_t ahb_sub_div = (expected_freq + BUS_FREQ_MAX - 1U) / BUS_FREQ_MAX; + sysctl_config_cpu0_domain_clock(HPM_SYSCTL, (clock_source_t) src, div, ahb_sub_div); + } else { + status = status_clk_shared_cpu0; + } + break; + default: + status = status_clk_src_invalid; + break; + } + + return status; +} + +static void switch_ip_clock(clock_name_t clock_name, bool on) +{ + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + if (resource < sysctl_resource_end) { + uint32_t mode = on ? 1UL : 2UL; + HPM_SYSCTL->RESOURCE[resource] = + (HPM_SYSCTL->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | SYSCTL_RESOURCE_MODE_SET(mode); + } +} + + +void clock_enable(clock_name_t clock_name) +{ + switch_ip_clock(clock_name, CLOCK_ON); +} + +void clock_disable(clock_name_t clock_name) +{ + switch_ip_clock(clock_name, CLOCK_OFF); +} + +void clock_add_to_group(clock_name_t clock_name, uint32_t group) +{ + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + if (resource < sysctl_resource_end) { + sysctl_enable_group_resource(HPM_SYSCTL, group, resource, true); + } +} + +void clock_remove_from_group(clock_name_t clock_name, uint32_t group) +{ + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + if (resource < sysctl_resource_end) { + sysctl_enable_group_resource(HPM_SYSCTL, group, resource, false); + } +} + +bool clock_check_in_group(clock_name_t clock_name, uint32_t group) +{ + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + return sysctl_check_group_resource_enable(HPM_SYSCTL, group, resource); +} + +void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu) +{ + if (cpu == 0U) { + HPM_SYSCTL->AFFILIATE[cpu].SET = (1UL << group); + } +} + +void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu) +{ + if (cpu == 0U) { + HPM_SYSCTL->AFFILIATE[cpu].CLEAR = (1UL << group); + } +} + +void clock_cpu_delay_us(uint32_t us) +{ + uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; + uint64_t expected_ticks = hpm_csr_get_core_cycle() + ticks_per_us * us; + while (hpm_csr_get_core_cycle() < expected_ticks) { + } +} + +void clock_cpu_delay_ms(uint32_t ms) +{ + uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; + uint64_t expected_ticks = hpm_csr_get_core_cycle() + (uint64_t)ticks_per_us * 1000UL * ms; + while (hpm_csr_get_core_cycle() < expected_ticks) { + } +} + +void clock_update_core_clock(void) +{ + hpm_core_clock = clock_get_frequency(clock_cpu0); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_clock_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_clock_drv.h new file mode 100644 index 00000000000..8e3d3819790 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_clock_drv.h @@ -0,0 +1,330 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_CLOCK_DRV_H +#define HPM_CLOCK_DRV_H + +#include "hpm_common.h" +#include "hpm_sysctl_drv.h" +#include "hpm_csr_drv.h" + + +#define CLOCK_DIV_INVALID (~0UL) + +/** + * @brief Error codes for clock driver + */ +enum { + status_clk_div_invalid = MAKE_STATUS(status_group_clk, 0), + status_clk_src_invalid = MAKE_STATUS(status_group_clk, 1), + status_clk_invalid = MAKE_STATUS(status_group_clk, 2), + status_clk_operation_unsupported = MAKE_STATUS(status_group_clk, 3), + status_clk_shared_ahb = MAKE_STATUS(status_group_clk, 4), + status_clk_shared_axi0 = MAKE_STATUS(status_group_clk, 5), + status_clk_shared_axi1 = MAKE_STATUS(status_group_clk, 6), + status_clk_shared_axi2 = MAKE_STATUS(status_group_clk, 7), + status_clk_shared_cpu0 = MAKE_STATUS(status_group_clk, 8), + status_clk_shared_cpu1 = MAKE_STATUS(status_group_clk, 9), + status_clk_fixed = MAKE_STATUS(status_group_clk, 10), +}; + +/** + * @brief Clock source group definitions + */ +#define CLK_SRC_GROUP_COMMON (0U) +#define CLK_SRC_GROUP_ADC (1U) +#define CLK_SRC_GROUP_EWDG (3U) +#define CLK_SRC_GROUP_PMIC (4U) +#define CLK_SRC_GROUP_AHB (5U) +#define CLK_SRC_GROUP_DAC (7U) +#define CLK_SRC_GROUP_CPU0 (9U) +#define CLK_SRC_GROUP_SRC (10U) +#define CLK_SRC_GROUP_PEWDG (11U) +#define CLK_SRC_GROUP_INVALID (15U) + +#define MAKE_CLK_SRC(src_grp, index) (((uint8_t)(src_grp)<<4) | (index)) +#define GET_CLK_SRC_GROUP(src) (((uint8_t)(src)>>4) & 0x0FU) +#define GET_CLK_SRC_INDEX(src) ((uint8_t)(src) & 0x0FU) + +#define GET_CLOCK_SOURCE_FROM_CLK_SRC(clk_src) (clock_source_t)((uint32_t)(clk_src) & 0xFU) + +/** + * @brief Clock source definitions + */ +typedef enum _clock_sources { + clk_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 0), + clk_src_pll0_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 1), + clk_src_pll0_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 2), + clk_src_pll0_clk2 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 3), + clk_src_pll1_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 4), + clk_src_pll1_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 5), + clk_src_pll1_clk2 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 6), + clk_src_pll1_clk3 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 7), + clk_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 8), + + clk_adc_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), + clk_adc_src_ana0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 1), + clk_adc_src_ana1 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 1), + + clk_dac_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 0), + clk_dac_src_ana2 = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 1), + clk_dac_src_ana3 = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 1), + + clk_wdg_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_EWDG, 0), + clk_wdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_EWDG, 1), + + clk_pwdg_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_PEWDG, 0), + clk_pwdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_PEWDG, 1), + + clk_src_invalid = MAKE_CLK_SRC(CLK_SRC_GROUP_INVALID, 15), +} clk_src_t; + + +#define RESOURCE_INVALID (0xFFFFU) +#define RESOURCE_SHARED_CPU0 (0xFFFDU) + +/* Clock NAME related Macros */ +#define MAKE_CLOCK_NAME(resource, src_type, node) (((uint32_t)(resource) << 16) | ((uint32_t)(src_type) << 8) | ((uint32_t)(node))) +#define GET_CLK_SRC_GROUP_FROM_NAME(name) (((uint32_t)(name) >> 8) & 0xFFUL) +#define GET_CLK_NODE_FROM_NAME(name) ((uint32_t)(name) & 0xFFUL) +#define GET_CLK_RESOURCE_FROM_NAME(name) ((uint32_t)(name) >> 16) + +/** + * @brief Peripheral Clock Type Description + */ +typedef enum _clock_name { + clock_cpu0 = MAKE_CLOCK_NAME(sysctl_resource_cpu0, CLK_SRC_GROUP_CPU0, clock_node_cpu0), + + clock_mchtmr0 = MAKE_CLOCK_NAME(sysctl_resource_mchtmr0, CLK_SRC_GROUP_COMMON, clock_node_mchtmr0), + clock_can0 = MAKE_CLOCK_NAME(sysctl_resource_can0, CLK_SRC_GROUP_COMMON, clock_node_can0), + clock_can1 = MAKE_CLOCK_NAME(sysctl_resource_can1, CLK_SRC_GROUP_COMMON, clock_node_can1), + clock_can2 = MAKE_CLOCK_NAME(sysctl_resource_can2, CLK_SRC_GROUP_COMMON, clock_node_can2), + clock_can3 = MAKE_CLOCK_NAME(sysctl_resource_can3, CLK_SRC_GROUP_COMMON, clock_node_can3), + clock_gptmr0 = MAKE_CLOCK_NAME(sysctl_resource_gptmr0, CLK_SRC_GROUP_COMMON, clock_node_gptmr0), + clock_gptmr1 = MAKE_CLOCK_NAME(sysctl_resource_gptmr1, CLK_SRC_GROUP_COMMON, clock_node_gptmr1), + clock_gptmr2 = MAKE_CLOCK_NAME(sysctl_resource_gptmr2, CLK_SRC_GROUP_COMMON, clock_node_gptmr2), + clock_gptmr3 = MAKE_CLOCK_NAME(sysctl_resource_gptmr3, CLK_SRC_GROUP_COMMON, clock_node_gptmr3), + clock_i2c0 = MAKE_CLOCK_NAME(sysctl_resource_i2c0, CLK_SRC_GROUP_COMMON, clock_node_i2c0), + clock_i2c1 = MAKE_CLOCK_NAME(sysctl_resource_i2c1, CLK_SRC_GROUP_COMMON, clock_node_i2c1), + clock_i2c2 = MAKE_CLOCK_NAME(sysctl_resource_i2c2, CLK_SRC_GROUP_COMMON, clock_node_i2c2), + clock_i2c3 = MAKE_CLOCK_NAME(sysctl_resource_i2c3, CLK_SRC_GROUP_COMMON, clock_node_i2c3), + clock_spi0 = MAKE_CLOCK_NAME(sysctl_resource_spi0, CLK_SRC_GROUP_COMMON, clock_node_spi0), + clock_spi1 = MAKE_CLOCK_NAME(sysctl_resource_spi1, CLK_SRC_GROUP_COMMON, clock_node_spi1), + clock_spi2 = MAKE_CLOCK_NAME(sysctl_resource_spi2, CLK_SRC_GROUP_COMMON, clock_node_spi2), + clock_spi3 = MAKE_CLOCK_NAME(sysctl_resource_spi3, CLK_SRC_GROUP_COMMON, clock_node_spi3), + clock_uart0 = MAKE_CLOCK_NAME(sysctl_resource_uart0, CLK_SRC_GROUP_COMMON, clock_node_uart0), + clock_uart1 = MAKE_CLOCK_NAME(sysctl_resource_uart1, CLK_SRC_GROUP_COMMON, clock_node_uart1), + clock_uart2 = MAKE_CLOCK_NAME(sysctl_resource_uart2, CLK_SRC_GROUP_COMMON, clock_node_uart2), + clock_uart3 = MAKE_CLOCK_NAME(sysctl_resource_uart3, CLK_SRC_GROUP_COMMON, clock_node_uart3), + clock_uart4 = MAKE_CLOCK_NAME(sysctl_resource_uart4, CLK_SRC_GROUP_COMMON, clock_node_uart4), + clock_uart5 = MAKE_CLOCK_NAME(sysctl_resource_uart5, CLK_SRC_GROUP_COMMON, clock_node_uart5), + clock_uart6 = MAKE_CLOCK_NAME(sysctl_resource_uart6, CLK_SRC_GROUP_COMMON, clock_node_uart6), + clock_uart7 = MAKE_CLOCK_NAME(sysctl_resource_uart7, CLK_SRC_GROUP_COMMON, clock_node_uart7), + clock_xpi0 = MAKE_CLOCK_NAME(sysctl_resource_xpi0, CLK_SRC_GROUP_COMMON, clock_node_xpi0), + clock_ref0 = MAKE_CLOCK_NAME(sysctl_resource_ref0, CLK_SRC_GROUP_COMMON, clock_node_ref0), + clock_ref1 = MAKE_CLOCK_NAME(sysctl_resource_ref1, CLK_SRC_GROUP_COMMON, clock_node_ref1), + + clock_ahb = MAKE_CLOCK_NAME(RESOURCE_SHARED_CPU0, CLK_SRC_GROUP_AHB, clock_node_ahb), + + clock_watchdog0 = MAKE_CLOCK_NAME(sysctl_resource_wdg0, CLK_SRC_GROUP_EWDG, 0), + clock_watchdog1 = MAKE_CLOCK_NAME(sysctl_resource_wdg1, CLK_SRC_GROUP_EWDG, 1), + clock_pwdg = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PEWDG, 0), + + clock_lmm0 = MAKE_CLOCK_NAME(sysctl_resource_lmm0, CLK_SRC_GROUP_CPU0, 0), + + clock_mbx0 = MAKE_CLOCK_NAME(sysctl_resource_mbx0, CLK_SRC_GROUP_AHB, 0), + clock_crc0 = MAKE_CLOCK_NAME(sysctl_resource_crc0, CLK_SRC_GROUP_AHB, 1), + clock_acmp = MAKE_CLOCK_NAME(sysctl_resource_acmp, CLK_SRC_GROUP_AHB, 2), + clock_opa0 = MAKE_CLOCK_NAME(sysctl_resource_opa0, CLK_SRC_GROUP_AHB, 3), + clock_opa1 = MAKE_CLOCK_NAME(sysctl_resource_opa1, CLK_SRC_GROUP_AHB, 4), + clock_mot0 = MAKE_CLOCK_NAME(sysctl_resource_mot0, CLK_SRC_GROUP_AHB, 5), + clock_rng = MAKE_CLOCK_NAME(sysctl_resource_rng0, CLK_SRC_GROUP_AHB, 6), + clock_sdp = MAKE_CLOCK_NAME(sysctl_resource_sdp0, CLK_SRC_GROUP_AHB, 7), + clock_kman = MAKE_CLOCK_NAME(sysctl_resource_kman, CLK_SRC_GROUP_AHB, 8), + clock_gpio = MAKE_CLOCK_NAME(sysctl_resource_gpio, CLK_SRC_GROUP_AHB, 9), + clock_hdma = MAKE_CLOCK_NAME(sysctl_resource_hdma, CLK_SRC_GROUP_AHB, 10), + clock_rom = MAKE_CLOCK_NAME(sysctl_resource_rom0, CLK_SRC_GROUP_AHB, 11), + clock_tsns = MAKE_CLOCK_NAME(sysctl_resource_tsns, CLK_SRC_GROUP_AHB, 12), + clock_usb0 = MAKE_CLOCK_NAME(sysctl_resource_usb0, CLK_SRC_GROUP_AHB, 13), + clock_ptpc = MAKE_CLOCK_NAME(sysctl_resource_ptpc, CLK_SRC_GROUP_AHB, 14), + + clock_ptmr = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 0), + clock_puart = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 1), + clock_pgpio = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 2), + + /* For ADC, there are 2-stage clock source and divider configurations */ + clock_ana0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana0), + clock_ana1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana1), + clock_adc0 = MAKE_CLOCK_NAME(sysctl_resource_adc0, CLK_SRC_GROUP_ADC, 0), + clock_adc1 = MAKE_CLOCK_NAME(sysctl_resource_adc1, CLK_SRC_GROUP_ADC, 1), + + /* For DAC, there are 2-stage clock source and divider configurations */ + clock_ana2 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana2), + clock_ana3 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana3), + clock_dac0 = MAKE_CLOCK_NAME(sysctl_resource_dac0, CLK_SRC_GROUP_DAC, 0), + clock_dac1 = MAKE_CLOCK_NAME(sysctl_resource_dac1, CLK_SRC_GROUP_DAC, 1), + + /* Clock sources */ + clk_osc0clk0 = MAKE_CLOCK_NAME(sysctl_resource_xtal, CLK_SRC_GROUP_SRC, 0), + clk_pll0clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll0, CLK_SRC_GROUP_SRC, 1), + clk_pll0clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll0, CLK_SRC_GROUP_SRC, 2), + clk_pll0clk2 = MAKE_CLOCK_NAME(sysctl_resource_clk2_pll0, CLK_SRC_GROUP_SRC, 3), + clk_pll1clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll1, CLK_SRC_GROUP_SRC, 4), + clk_pll1clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll1, CLK_SRC_GROUP_SRC, 5), + clk_pll1clk2 = MAKE_CLOCK_NAME(sysctl_resource_clk2_pll1, CLK_SRC_GROUP_SRC, 6), + clk_pll1clk3 = MAKE_CLOCK_NAME(sysctl_resource_clk3_pll1, CLK_SRC_GROUP_SRC, 7), +} clock_name_t; + +extern uint32_t hpm_core_clock; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Get specified IP frequency + * @param[in] clock_name IP clock name + * + * @return IP clock frequency in Hz + */ +uint32_t clock_get_frequency(clock_name_t clock_name); + +/** + * @brief Get Clock frequency for selected clock source + * @param [in] source clock source + * @return clock frequency for selected clock source + */ +uint32_t get_frequency_for_source(clock_source_t source); + +/** + * @brief Get the IP clock source + * Note: This API return the direct clock source + * @param [in] clock_name clock name + * @return IP clock source + */ +clk_src_t clock_get_source(clock_name_t clock_name); + +/** + * @brief Get the IP clock divider + * Note:This API return the direct clock divider + * @param [in] clock_name clock name + * @return IP clock divider + */ +uint32_t clock_get_divider(clock_name_t clock_name); + +/** + * @brief Set ADC clock source + * @param[in] clock_name ADC clock name + * @param[in] src ADC clock source + * + * @return #status_success Setting ADC clock source is successful + * #status_clk_invalid Invalid ADC clock + * #status_clk_src_invalid Invalid ADC clock source + */ +hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src); + +/** + * @brief Set DAC clock source + * @param[in] clock_name DAC clock name + * @param[in] src DAC clock source + * + * @return #status_success Setting DAC clock source is successful + * #status_clk_invalid Invalid DAC clock + * #status_clk_src_invalid Invalid DAC clock source + */ +hpm_stat_t clock_set_dac_source(clock_name_t clock_name, clk_src_t src); + +/** + * @brief Set the IP clock source and divider + * @param[in] clock_name clock name + * @param[in] src clock source + * @param[in] div clock divider, valid range (1 - 256) + * + * @return #status_success Setting Clock source and divider is successful. + * #status_clk_src_invalid clock source is invalid. + * #status_clk_fixed clock source and divider is a fixed value + * #status_clk_shared_ahb Clock is shared with the AHB clock + * #status_clk_shared_axi0 Clock is shared with the AXI0 clock + * #status_clk_shared_axi1 CLock is shared with the AXI1 clock + * #status_clk_shared_axi2 Clock is shared with the AXI2 clock + * #status_clk_shared_cpu0 Clock is shared with the CPU0 clock + * #status_clk_shared_cpu1 Clock is shared with the CPU1 clock + */ +hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint32_t div); + +/** + * @brief Enable IP clock + * @param[in] clock_name IP clock name + */ +void clock_enable(clock_name_t clock_name); + +/** + * @brief Disable IP clock + * @param[in] clock_name IP clock name + */ +void clock_disable(clock_name_t clock_name); + +/** + * @brief Add IP to specified group + * @param[in] clock_name IP clock name + * @param[in] group resource group index, valid value: 0/1/2/3 + */ +void clock_add_to_group(clock_name_t clock_name, uint32_t group); + +/** + * @brief Remove IP from specified group + * @param[in] clock_name IP clock name + * @param[in] group resource group index, valid value: 0/1/2/3 + */ +void clock_remove_from_group(clock_name_t clock_name, uint32_t group); + +/** + * @brief Check IP in specified group + * @param[in] clock_name IP clock name + * @param[in] group resource group index, valid value: 0/1/2/3 + * @return true if in group, false if not in group + */ +bool clock_check_in_group(clock_name_t clock_name, uint32_t group); + +/** + * @brief Disconnect the clock group from specified CPU + * @param[in] group clock group index, value value is 0/1/2/3 + * @param[in] cpu CPU index, valid value is 0/1 + */ +void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu); + +/** + * @brief Disconnect the clock group from specified CPU + * @param[in] group clock group index, value value is 0/1/2/3 + * @param[in] cpu CPU index, valid value is 0/1 + */ +void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu); + +/** + * @brief Delay specified microseconds + * + * @param [in] us expected delay interval in microseconds + */ +void clock_cpu_delay_us(uint32_t us); + +/** + * @brief Delay specified milliseconds + * + * @param [in] ms expected delay interval in milliseconds + */ +void clock_cpu_delay_ms(uint32_t ms); + +/** + * @brief Update the Core clock frequency + */ +void clock_update_core_clock(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_CLOCK_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_csr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_csr_regs.h new file mode 100644 index 00000000000..09c7fc113ff --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_csr_regs.h @@ -0,0 +1,4276 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_CSR_H +#define HPM_CSR_H + +/* STANDARD CRS address definition */ +#define CSR_USTATUS (0x0) +#define CSR_UIE (0x4) +#define CSR_UTVEC (0x5) +#define CSR_USCRATCH (0x40) +#define CSR_UEPC (0x41) +#define CSR_UCAUSE (0x42) +#define CSR_UTVAL (0x43) +#define CSR_UIP (0x44) +#define CSR_MSTATUS (0x300) +#define CSR_MISA (0x301) +#define CSR_MIE (0x304) +#define CSR_MTVEC (0x305) +#define CSR_MCOUNTEREN (0x306) +#define CSR_MHPMEVENT3 (0x323) +#define CSR_MHPMEVENT4 (0x324) +#define CSR_MHPMEVENT5 (0x325) +#define CSR_MHPMEVENT6 (0x326) +#define CSR_MSCRATCH (0x340) +#define CSR_MEPC (0x341) +#define CSR_MCAUSE (0x342) +#define CSR_MTVAL (0x343) +#define CSR_MIP (0x344) +#define CSR_PMPCFG0 (0x3A0) +#define CSR_PMPCFG1 (0x3A1) +#define CSR_PMPCFG2 (0x3A2) +#define CSR_PMPCFG3 (0x3A3) +#define CSR_PMPADDR0 (0x3B0) +#define CSR_PMPADDR1 (0x3B1) +#define CSR_PMPADDR2 (0x3B2) +#define CSR_PMPADDR3 (0x3B3) +#define CSR_PMPADDR4 (0x3B4) +#define CSR_PMPADDR5 (0x3B5) +#define CSR_PMPADDR6 (0x3B6) +#define CSR_PMPADDR7 (0x3B7) +#define CSR_PMPADDR8 (0x3B8) +#define CSR_PMPADDR9 (0x3B9) +#define CSR_PMPADDR10 (0x3BA) +#define CSR_PMPADDR11 (0x3BB) +#define CSR_PMPADDR12 (0x3BC) +#define CSR_PMPADDR13 (0x3BD) +#define CSR_PMPADDR14 (0x3BE) +#define CSR_PMPADDR15 (0x3BF) +#define CSR_TSELECT (0x7A0) +#define CSR_TDATA1 (0x7A1) +#define CSR_MCONTROL (0x7A1) +#define CSR_ICOUNT (0x7A1) +#define CSR_ITRIGGER (0x7A1) +#define CSR_ETRIGGER (0x7A1) +#define CSR_TDATA2 (0x7A2) +#define CSR_TDATA3 (0x7A3) +#define CSR_TEXTRA (0x7A3) +#define CSR_TINFO (0x7A4) +#define CSR_TCONTROL (0x7A5) +#define CSR_MCONTEXT (0x7A8) +#define CSR_SCONTEXT (0x7AA) +#define CSR_DCSR (0x7B0) +#define CSR_DPC (0x7B1) +#define CSR_DSCRATCH0 (0x7B2) +#define CSR_DSCRATCH1 (0x7B3) +#define CSR_MCYCLE (0xB00) +#define CSR_MINSTRET (0xB02) +#define CSR_MHPMCOUNTER3 (0xB03) +#define CSR_MHPMCOUNTER4 (0xB04) +#define CSR_MHPMCOUNTER5 (0xB05) +#define CSR_MHPMCOUNTER6 (0xB06) +#define CSR_MCYCLEH (0xB80) +#define CSR_MINSTRETH (0xB82) +#define CSR_MHPMCOUNTER3H (0xB83) +#define CSR_MHPMCOUNTER4H (0xB84) +#define CSR_MHPMCOUNTER5H (0xB85) +#define CSR_MHPMCOUNTER6H (0xB86) +#define CSR_CYCLE (0xC00) +#define CSR_CYCLEH (0xC80) +#define CSR_MVENDORID (0xF11) +#define CSR_MARCHID (0xF12) +#define CSR_MIMPID (0xF13) +#define CSR_MHARTID (0xF14) + +/* NON-STANDARD CRS address definition */ +#define CSR_MCOUNTINHIBIT (0x320) +#define CSR_MILMB (0x7C0) +#define CSR_MDLMB (0x7C1) +#define CSR_MECC_CODE (0x7C2) +#define CSR_MNVEC (0x7C3) +#define CSR_MXSTATUS (0x7C4) +#define CSR_MPFT_CTL (0x7C5) +#define CSR_MHSP_CTL (0x7C6) +#define CSR_MSP_BOUND (0x7C7) +#define CSR_MSP_BASE (0x7C8) +#define CSR_MDCAUSE (0x7C9) +#define CSR_MCACHE_CTL (0x7CA) +#define CSR_MCCTLBEGINADDR (0x7CB) +#define CSR_MCCTLCOMMAND (0x7CC) +#define CSR_MCCTLDATA (0x7CD) +#define CSR_MCOUNTERWEN (0x7CE) +#define CSR_MCOUNTERINTEN (0x7CF) +#define CSR_MMISC_CTL (0x7D0) +#define CSR_MCOUNTERMASK_M (0x7D1) +#define CSR_MCOUNTERMASK_S (0x7D2) +#define CSR_MCOUNTERMASK_U (0x7D3) +#define CSR_MCOUNTEROVF (0x7D4) +#define CSR_DEXC2DBG (0x7E0) +#define CSR_DDCAUSE (0x7E1) +#define CSR_UITB (0x800) +#define CSR_UCODE (0x801) +#define CSR_UDCAUSE (0x809) +#define CSR_UCCTLBEGINADDR (0x80B) +#define CSR_UCCTLCOMMAND (0x80C) +#define CSR_MICM_CFG (0xFC0) +#define CSR_MDCM_CFG (0xFC1) +#define CSR_MMSC_CFG (0xFC2) +#define CSR_MMSC_CFG2 (0xFC3) + +/* STANDARD CRS register bitfiled definitions */ + +/* Bitfield definition for register: USTATUS */ +/* + * UPIE (RW) + * + * UPIE holds the value of the UIE bit prior to a trap. + */ +#define CSR_USTATUS_UPIE_MASK (0x10U) +#define CSR_USTATUS_UPIE_SHIFT (4U) +#define CSR_USTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_USTATUS_UPIE_SHIFT) & CSR_USTATUS_UPIE_MASK) +#define CSR_USTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_USTATUS_UPIE_MASK) >> CSR_USTATUS_UPIE_SHIFT) + +/* + * UIE (RW) + * + * U mode interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_USTATUS_UIE_MASK (0x1U) +#define CSR_USTATUS_UIE_SHIFT (0U) +#define CSR_USTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_USTATUS_UIE_SHIFT) & CSR_USTATUS_UIE_MASK) +#define CSR_USTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_USTATUS_UIE_MASK) >> CSR_USTATUS_UIE_SHIFT) + +/* Bitfield definition for register: UIE */ +/* + * UEIE (RW) + * + * U mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_UIE_UEIE_MASK (0x100U) +#define CSR_UIE_UEIE_SHIFT (8U) +#define CSR_UIE_UEIE_SET(x) (((uint32_t)(x) << CSR_UIE_UEIE_SHIFT) & CSR_UIE_UEIE_MASK) +#define CSR_UIE_UEIE_GET(x) (((uint32_t)(x) & CSR_UIE_UEIE_MASK) >> CSR_UIE_UEIE_SHIFT) + +/* + * UTIE (RW) + * + * U mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_UIE_UTIE_MASK (0x10U) +#define CSR_UIE_UTIE_SHIFT (4U) +#define CSR_UIE_UTIE_SET(x) (((uint32_t)(x) << CSR_UIE_UTIE_SHIFT) & CSR_UIE_UTIE_MASK) +#define CSR_UIE_UTIE_GET(x) (((uint32_t)(x) & CSR_UIE_UTIE_MASK) >> CSR_UIE_UTIE_SHIFT) + +/* + * USIE (RW) + * + * U mode software interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_UIE_USIE_MASK (0x1U) +#define CSR_UIE_USIE_SHIFT (0U) +#define CSR_UIE_USIE_SET(x) (((uint32_t)(x) << CSR_UIE_USIE_SHIFT) & CSR_UIE_USIE_MASK) +#define CSR_UIE_USIE_GET(x) (((uint32_t)(x) & CSR_UIE_USIE_MASK) >> CSR_UIE_USIE_SHIFT) + +/* Bitfield definition for register: UTVEC */ +/* + * BASE_31_2 (RW) + * + * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode. + */ +#define CSR_UTVEC_BASE_31_2_MASK (0xFFFFFFFCUL) +#define CSR_UTVEC_BASE_31_2_SHIFT (2U) +#define CSR_UTVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_UTVEC_BASE_31_2_SHIFT) & CSR_UTVEC_BASE_31_2_MASK) +#define CSR_UTVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_UTVEC_BASE_31_2_MASK) >> CSR_UTVEC_BASE_31_2_SHIFT) + +/* Bitfield definition for register: USCRATCH */ +/* + * USCRATCH (RW) + * + * Scratch register storage. + */ +#define CSR_USCRATCH_USCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_USCRATCH_USCRATCH_SHIFT (0U) +#define CSR_USCRATCH_USCRATCH_SET(x) (((uint32_t)(x) << CSR_USCRATCH_USCRATCH_SHIFT) & CSR_USCRATCH_USCRATCH_MASK) +#define CSR_USCRATCH_USCRATCH_GET(x) (((uint32_t)(x) & CSR_USCRATCH_USCRATCH_MASK) >> CSR_USCRATCH_USCRATCH_SHIFT) + +/* Bitfield definition for register: UEPC */ +/* + * EPC (RW) + * + * Exception program counter. + */ +#define CSR_UEPC_EPC_MASK (0xFFFFFFFEUL) +#define CSR_UEPC_EPC_SHIFT (1U) +#define CSR_UEPC_EPC_SET(x) (((uint32_t)(x) << CSR_UEPC_EPC_SHIFT) & CSR_UEPC_EPC_MASK) +#define CSR_UEPC_EPC_GET(x) (((uint32_t)(x) & CSR_UEPC_EPC_MASK) >> CSR_UEPC_EPC_SHIFT) + +/* Bitfield definition for register: UCAUSE */ +/* + * INTERRUPT (RW) + * + * Interrupt. + */ +#define CSR_UCAUSE_INTERRUPT_MASK (0x80000000UL) +#define CSR_UCAUSE_INTERRUPT_SHIFT (31U) +#define CSR_UCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_UCAUSE_INTERRUPT_SHIFT) & CSR_UCAUSE_INTERRUPT_MASK) +#define CSR_UCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_UCAUSE_INTERRUPT_MASK) >> CSR_UCAUSE_INTERRUPT_SHIFT) + +/* + * EXCEPTION_CODE (RW) + * + * Exception Code. + * When interrupt is 1: + * 0:User software interrupt + * 4:User timer interrupt + * 8:User external interrupt + * When interrupt is 0: + * 0:Instruction address misaligned + * 1:Instruction access fault + * 2:Illegal instruction + * 3:Breakpoint + * 4:Load address misaligned + * 5:Load access fault + * 6:Store/AMO address misaligned + * 7:Store/AMO access fault + * 8:Environment call from U-mode + * 9-11:Reserved + * 12:Instruction page fault + * 13:Load page fault + * 14:Reserved + * 15:Store/AMO page fault + * 32：Stack overflow exception + * 33:Stack underflow exception + * 40-47:Reserved + */ +#define CSR_UCAUSE_EXCEPTION_CODE_MASK (0x3FFU) +#define CSR_UCAUSE_EXCEPTION_CODE_SHIFT (0U) +#define CSR_UCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_UCAUSE_EXCEPTION_CODE_SHIFT) & CSR_UCAUSE_EXCEPTION_CODE_MASK) +#define CSR_UCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_UCAUSE_EXCEPTION_CODE_MASK) >> CSR_UCAUSE_EXCEPTION_CODE_SHIFT) + +/* Bitfield definition for register: UTVAL */ +/* + * UTVAL (RW) + * + * Exception-specific information for software trap handling. + */ +#define CSR_UTVAL_UTVAL_MASK (0xFFFFFFFFUL) +#define CSR_UTVAL_UTVAL_SHIFT (0U) +#define CSR_UTVAL_UTVAL_SET(x) (((uint32_t)(x) << CSR_UTVAL_UTVAL_SHIFT) & CSR_UTVAL_UTVAL_MASK) +#define CSR_UTVAL_UTVAL_GET(x) (((uint32_t)(x) & CSR_UTVAL_UTVAL_MASK) >> CSR_UTVAL_UTVAL_SHIFT) + +/* Bitfield definition for register: UIP */ +/* + * UEIP (RW) + * + * U mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_UIP_UEIP_MASK (0x100U) +#define CSR_UIP_UEIP_SHIFT (8U) +#define CSR_UIP_UEIP_SET(x) (((uint32_t)(x) << CSR_UIP_UEIP_SHIFT) & CSR_UIP_UEIP_MASK) +#define CSR_UIP_UEIP_GET(x) (((uint32_t)(x) & CSR_UIP_UEIP_MASK) >> CSR_UIP_UEIP_SHIFT) + +/* + * UTIP (RW) + * + * U mode timer interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_UIP_UTIP_MASK (0x10U) +#define CSR_UIP_UTIP_SHIFT (4U) +#define CSR_UIP_UTIP_SET(x) (((uint32_t)(x) << CSR_UIP_UTIP_SHIFT) & CSR_UIP_UTIP_MASK) +#define CSR_UIP_UTIP_GET(x) (((uint32_t)(x) & CSR_UIP_UTIP_MASK) >> CSR_UIP_UTIP_SHIFT) + +/* + * USIP (RW) + * + * U mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_UIP_USIP_MASK (0x1U) +#define CSR_UIP_USIP_SHIFT (0U) +#define CSR_UIP_USIP_SET(x) (((uint32_t)(x) << CSR_UIP_USIP_SHIFT) & CSR_UIP_USIP_MASK) +#define CSR_UIP_USIP_GET(x) (((uint32_t)(x) & CSR_UIP_USIP_MASK) >> CSR_UIP_USIP_SHIFT) + +/* Bitfield definition for register: MSTATUS */ +/* + * SD (RO) + * + * SD summarizes whether either the FS field or XS field is dirty. + */ +#define CSR_MSTATUS_SD_MASK (0x80000000UL) +#define CSR_MSTATUS_SD_SHIFT (31U) +#define CSR_MSTATUS_SD_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SD_MASK) >> CSR_MSTATUS_SD_SHIFT) + +/* + * MXR (RW) + * + * MXR controls whether execute-only pages are readable. It has no effect when page-based virtual memory is not in effect + * 0:Execute-only pages are not readable + * 1:Execute-only pages are readable + */ +#define CSR_MSTATUS_MXR_MASK (0x80000UL) +#define CSR_MSTATUS_MXR_SHIFT (19U) +#define CSR_MSTATUS_MXR_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MXR_SHIFT) & CSR_MSTATUS_MXR_MASK) +#define CSR_MSTATUS_MXR_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MXR_MASK) >> CSR_MSTATUS_MXR_SHIFT) + +/* + * MPRV (RW) + * + * When the MPRV bit is set, the memory access privilege for load and store are specified by the MPP field. When U-mode is not available, this field is hardwired to 0. + */ +#define CSR_MSTATUS_MPRV_MASK (0x20000UL) +#define CSR_MSTATUS_MPRV_SHIFT (17U) +#define CSR_MSTATUS_MPRV_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPRV_SHIFT) & CSR_MSTATUS_MPRV_MASK) +#define CSR_MSTATUS_MPRV_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPRV_MASK) >> CSR_MSTATUS_MPRV_SHIFT) + +/* + * XS (RO) + * + * XS holds the status of the architectural states (ACE registers) of ACE instructions. The value of this field is zero if ACE extension is not configured. This field is primarily managed by software. The processor hardware assists the state managements in two regards: + * Illegal instruction exceptions are triggered when XS is Off. + * XS is updated to the Dirty state with the execution of ACE instructions when XS is not Off. Changing the setting of this field has no effect on the contents of ACE states. In particular, setting XS to Off does not destroy the states, nor does setting XS to Initial clear the contents. + * 0:Off + * 1:Initial + * 2:Clean + * 3:Dirty + */ +#define CSR_MSTATUS_XS_MASK (0x18000UL) +#define CSR_MSTATUS_XS_SHIFT (15U) +#define CSR_MSTATUS_XS_GET(x) (((uint32_t)(x) & CSR_MSTATUS_XS_MASK) >> CSR_MSTATUS_XS_SHIFT) + +/* + * FS (RW) + * + * FS holds the status of the architectural states of the floating-point unit, including the fcsr CSR and f0 – f31 floating-point data registers. The value of this field is zero and read-only if the processor does not have FPU. This field is primarily managed by software. The processor hardware assists the state + * managements in two regards: + * Attempts to access fcsr or any f register raise an illegal-instruction exception when FS is Off. + * FS is updated to the Dirty state with the execution of any instruction that updates fcsr or any f register when FS is Initial or Clean. Changing the setting of this field has no effect on the contents of the floating-point register states. In particular, setting FS to Off does not destroy the states, nor does setting FS to Initial clear the contents. + * 0:Off + * 1:Initial + * 2:Clean + * 3:Dirty + */ +#define CSR_MSTATUS_FS_MASK (0x6000U) +#define CSR_MSTATUS_FS_SHIFT (13U) +#define CSR_MSTATUS_FS_SET(x) (((uint32_t)(x) << CSR_MSTATUS_FS_SHIFT) & CSR_MSTATUS_FS_MASK) +#define CSR_MSTATUS_FS_GET(x) (((uint32_t)(x) & CSR_MSTATUS_FS_MASK) >> CSR_MSTATUS_FS_SHIFT) + +/* + * MPP (RW) + * + * MPP holds the privilege mode prior to a trap. Encoding for privilege mode is described in Table5. When U-mode is not available, this field is hardwired to 3. + */ +#define CSR_MSTATUS_MPP_MASK (0x1800U) +#define CSR_MSTATUS_MPP_SHIFT (11U) +#define CSR_MSTATUS_MPP_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPP_SHIFT) & CSR_MSTATUS_MPP_MASK) +#define CSR_MSTATUS_MPP_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPP_MASK) >> CSR_MSTATUS_MPP_SHIFT) + +/* + * MPIE (RW) + * + * MPIE holds the value of the MIE bit prior to a trap. + */ +#define CSR_MSTATUS_MPIE_MASK (0x80U) +#define CSR_MSTATUS_MPIE_SHIFT (7U) +#define CSR_MSTATUS_MPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPIE_SHIFT) & CSR_MSTATUS_MPIE_MASK) +#define CSR_MSTATUS_MPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPIE_MASK) >> CSR_MSTATUS_MPIE_SHIFT) + +/* + * UPIE (RW) + * + * UPIE holds the value of the UIE bit prior to a trap. + */ +#define CSR_MSTATUS_UPIE_MASK (0x10U) +#define CSR_MSTATUS_UPIE_SHIFT (4U) +#define CSR_MSTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_UPIE_SHIFT) & CSR_MSTATUS_UPIE_MASK) +#define CSR_MSTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_UPIE_MASK) >> CSR_MSTATUS_UPIE_SHIFT) + +/* + * MIE (RW) + * + * M mode interrupt enable bit. + * 0: Disabled + * 1: Enabled + */ +#define CSR_MSTATUS_MIE_MASK (0x8U) +#define CSR_MSTATUS_MIE_SHIFT (3U) +#define CSR_MSTATUS_MIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MIE_SHIFT) & CSR_MSTATUS_MIE_MASK) +#define CSR_MSTATUS_MIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MIE_MASK) >> CSR_MSTATUS_MIE_SHIFT) + +/* + * UIE (RW) + * + * U mode interrupt enable bit. + * 0: Disabled + * 1: Enabled + */ +#define CSR_MSTATUS_UIE_MASK (0x1U) +#define CSR_MSTATUS_UIE_SHIFT (0U) +#define CSR_MSTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_UIE_SHIFT) & CSR_MSTATUS_UIE_MASK) +#define CSR_MSTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_UIE_MASK) >> CSR_MSTATUS_UIE_SHIFT) + +/* Bitfield definition for register: MISA */ +/* + * BASE (RO) + * + * The general-purpose register width of the native base integer ISA. + * 0:Reserved + * 1:32 + * 2:64 + * 3:128 + */ +#define CSR_MISA_BASE_MASK (0xC0000000UL) +#define CSR_MISA_BASE_SHIFT (30U) +#define CSR_MISA_BASE_GET(x) (((uint32_t)(x) & CSR_MISA_BASE_MASK) >> CSR_MISA_BASE_SHIFT) + +/* + * Z (RO) + * + * Reserved + */ +#define CSR_MISA_Z_MASK (0x2000000UL) +#define CSR_MISA_Z_SHIFT (25U) +#define CSR_MISA_Z_GET(x) (((uint32_t)(x) & CSR_MISA_Z_MASK) >> CSR_MISA_Z_SHIFT) + +/* + * Y (RO) + * + * Reserved + */ +#define CSR_MISA_Y_MASK (0x1000000UL) +#define CSR_MISA_Y_SHIFT (24U) +#define CSR_MISA_Y_GET(x) (((uint32_t)(x) & CSR_MISA_Y_MASK) >> CSR_MISA_Y_SHIFT) + +/* + * X (RO) + * + * Non-standard extensions present + */ +#define CSR_MISA_X_MASK (0x800000UL) +#define CSR_MISA_X_SHIFT (23U) +#define CSR_MISA_X_GET(x) (((uint32_t)(x) & CSR_MISA_X_MASK) >> CSR_MISA_X_SHIFT) + +/* + * W (RO) + * + * Reserved + */ +#define CSR_MISA_W_MASK (0x400000UL) +#define CSR_MISA_W_SHIFT (22U) +#define CSR_MISA_W_GET(x) (((uint32_t)(x) & CSR_MISA_W_MASK) >> CSR_MISA_W_SHIFT) + +/* + * V (RO) + * + * Tentatively reserved for Vector extension + */ +#define CSR_MISA_V_MASK (0x200000UL) +#define CSR_MISA_V_SHIFT (21U) +#define CSR_MISA_V_GET(x) (((uint32_t)(x) & CSR_MISA_V_MASK) >> CSR_MISA_V_SHIFT) + +/* + * U (RO) + * + * User mode implemented + * 0:Machine + * 1:Machine + User / Machine + Supervisor + User + */ +#define CSR_MISA_U_MASK (0x100000UL) +#define CSR_MISA_U_SHIFT (20U) +#define CSR_MISA_U_GET(x) (((uint32_t)(x) & CSR_MISA_U_MASK) >> CSR_MISA_U_SHIFT) + +/* + * T (RO) + * + * Tentatively reserved for Transactional Memory extension + */ +#define CSR_MISA_T_MASK (0x80000UL) +#define CSR_MISA_T_SHIFT (19U) +#define CSR_MISA_T_GET(x) (((uint32_t)(x) & CSR_MISA_T_MASK) >> CSR_MISA_T_SHIFT) + +/* + * S (RO) + * + * Supervisor mode implemented + * 0:Machine / Machine + User + * 1:Machine + Supervisor + User + */ +#define CSR_MISA_S_MASK (0x40000UL) +#define CSR_MISA_S_SHIFT (18U) +#define CSR_MISA_S_GET(x) (((uint32_t)(x) & CSR_MISA_S_MASK) >> CSR_MISA_S_SHIFT) + +/* + * R (RO) + * + * Reserved + */ +#define CSR_MISA_R_MASK (0x20000UL) +#define CSR_MISA_R_SHIFT (17U) +#define CSR_MISA_R_GET(x) (((uint32_t)(x) & CSR_MISA_R_MASK) >> CSR_MISA_R_SHIFT) + +/* + * Q (RO) + * + * Quad-precision floating-point extension + */ +#define CSR_MISA_Q_MASK (0x10000UL) +#define CSR_MISA_Q_SHIFT (16U) +#define CSR_MISA_Q_GET(x) (((uint32_t)(x) & CSR_MISA_Q_MASK) >> CSR_MISA_Q_SHIFT) + +/* + * P (RO) + * + * Tentatively reserved for Packed-SIMD extension + */ +#define CSR_MISA_P_MASK (0x8000U) +#define CSR_MISA_P_SHIFT (15U) +#define CSR_MISA_P_GET(x) (((uint32_t)(x) & CSR_MISA_P_MASK) >> CSR_MISA_P_SHIFT) + +/* + * O (RO) + * + * Reserved + */ +#define CSR_MISA_O_MASK (0x4000U) +#define CSR_MISA_O_SHIFT (14U) +#define CSR_MISA_O_GET(x) (((uint32_t)(x) & CSR_MISA_O_MASK) >> CSR_MISA_O_SHIFT) + +/* + * N (RO) + * + * User-level interrupts supported + * 0:no + * 1:yes + */ +#define CSR_MISA_N_MASK (0x2000U) +#define CSR_MISA_N_SHIFT (13U) +#define CSR_MISA_N_GET(x) (((uint32_t)(x) & CSR_MISA_N_MASK) >> CSR_MISA_N_SHIFT) + +/* + * M (RO) + * + * Integer Multiply/Divide extension + */ +#define CSR_MISA_M_MASK (0x1000U) +#define CSR_MISA_M_SHIFT (12U) +#define CSR_MISA_M_GET(x) (((uint32_t)(x) & CSR_MISA_M_MASK) >> CSR_MISA_M_SHIFT) + +/* + * L (RO) + * + * Tentatively reserved for Decimal Floating-Point extension + */ +#define CSR_MISA_L_MASK (0x800U) +#define CSR_MISA_L_SHIFT (11U) +#define CSR_MISA_L_GET(x) (((uint32_t)(x) & CSR_MISA_L_MASK) >> CSR_MISA_L_SHIFT) + +/* + * K (RO) + * + * Reserved + */ +#define CSR_MISA_K_MASK (0x400U) +#define CSR_MISA_K_SHIFT (10U) +#define CSR_MISA_K_GET(x) (((uint32_t)(x) & CSR_MISA_K_MASK) >> CSR_MISA_K_SHIFT) + +/* + * J (RO) + * + * Tentatively reserved for Dynamically Translated Languages extension + */ +#define CSR_MISA_J_MASK (0x200U) +#define CSR_MISA_J_SHIFT (9U) +#define CSR_MISA_J_GET(x) (((uint32_t)(x) & CSR_MISA_J_MASK) >> CSR_MISA_J_SHIFT) + +/* + * I (RO) + * + * RV32I/64I/128I base ISA + */ +#define CSR_MISA_I_MASK (0x100U) +#define CSR_MISA_I_SHIFT (8U) +#define CSR_MISA_I_GET(x) (((uint32_t)(x) & CSR_MISA_I_MASK) >> CSR_MISA_I_SHIFT) + +/* + * H (RO) + * + * Reserved + */ +#define CSR_MISA_H_MASK (0x80U) +#define CSR_MISA_H_SHIFT (7U) +#define CSR_MISA_H_GET(x) (((uint32_t)(x) & CSR_MISA_H_MASK) >> CSR_MISA_H_SHIFT) + +/* + * G (RO) + * + * Additional standard extensions present + */ +#define CSR_MISA_G_MASK (0x40U) +#define CSR_MISA_G_SHIFT (6U) +#define CSR_MISA_G_GET(x) (((uint32_t)(x) & CSR_MISA_G_MASK) >> CSR_MISA_G_SHIFT) + +/* + * F (RO) + * + * Single-precision floating-point extension + * 0:none + * 1:double+single precision / single precision + */ +#define CSR_MISA_F_MASK (0x20U) +#define CSR_MISA_F_SHIFT (5U) +#define CSR_MISA_F_GET(x) (((uint32_t)(x) & CSR_MISA_F_MASK) >> CSR_MISA_F_SHIFT) + +/* + * E (RO) + * + * RV32E base ISA + */ +#define CSR_MISA_E_MASK (0x10U) +#define CSR_MISA_E_SHIFT (4U) +#define CSR_MISA_E_GET(x) (((uint32_t)(x) & CSR_MISA_E_MASK) >> CSR_MISA_E_SHIFT) + +/* + * D (RO) + * + * Double-precision floating-point extension + * 0:single precision / none + * 1:double+single precision + */ +#define CSR_MISA_D_MASK (0x8U) +#define CSR_MISA_D_SHIFT (3U) +#define CSR_MISA_D_GET(x) (((uint32_t)(x) & CSR_MISA_D_MASK) >> CSR_MISA_D_SHIFT) + +/* + * C (RO) + * + * Compressed extension + */ +#define CSR_MISA_C_MASK (0x4U) +#define CSR_MISA_C_SHIFT (2U) +#define CSR_MISA_C_GET(x) (((uint32_t)(x) & CSR_MISA_C_MASK) >> CSR_MISA_C_SHIFT) + +/* + * B (RO) + * + * Tentatively reserved for Bit operations extension + */ +#define CSR_MISA_B_MASK (0x2U) +#define CSR_MISA_B_SHIFT (1U) +#define CSR_MISA_B_GET(x) (((uint32_t)(x) & CSR_MISA_B_MASK) >> CSR_MISA_B_SHIFT) + +/* + * A (RO) + * + * Atomic extension + * 0:no + * 1:yes + */ +#define CSR_MISA_A_MASK (0x1U) +#define CSR_MISA_A_SHIFT (0U) +#define CSR_MISA_A_GET(x) (((uint32_t)(x) & CSR_MISA_A_MASK) >> CSR_MISA_A_SHIFT) + +/* Bitfield definition for register: MIE */ +/* + * PMOVI (RW) + * + * Performance monitor overflow local interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_PMOVI_MASK (0x40000UL) +#define CSR_MIE_PMOVI_SHIFT (18U) +#define CSR_MIE_PMOVI_SET(x) (((uint32_t)(x) << CSR_MIE_PMOVI_SHIFT) & CSR_MIE_PMOVI_MASK) +#define CSR_MIE_PMOVI_GET(x) (((uint32_t)(x) & CSR_MIE_PMOVI_MASK) >> CSR_MIE_PMOVI_SHIFT) + +/* + * BWEI (RW) + * + * Bus read/write transaction error local interrupt enable bit. The processor may receive bus errors on load/store instructions or cache writebacks. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_BWEI_MASK (0x20000UL) +#define CSR_MIE_BWEI_SHIFT (17U) +#define CSR_MIE_BWEI_SET(x) (((uint32_t)(x) << CSR_MIE_BWEI_SHIFT) & CSR_MIE_BWEI_MASK) +#define CSR_MIE_BWEI_GET(x) (((uint32_t)(x) & CSR_MIE_BWEI_MASK) >> CSR_MIE_BWEI_SHIFT) + +/* + * IMECCI (RW) + * + * Imprecise ECC error local interrupt enable bit. The processor may receive imprecise ECC errors on slave port accesses or cache writebacks. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_IMECCI_MASK (0x10000UL) +#define CSR_MIE_IMECCI_SHIFT (16U) +#define CSR_MIE_IMECCI_SET(x) (((uint32_t)(x) << CSR_MIE_IMECCI_SHIFT) & CSR_MIE_IMECCI_MASK) +#define CSR_MIE_IMECCI_GET(x) (((uint32_t)(x) & CSR_MIE_IMECCI_MASK) >> CSR_MIE_IMECCI_SHIFT) + +/* + * MEIE (RW) + * + * M mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_MEIE_MASK (0x800U) +#define CSR_MIE_MEIE_SHIFT (11U) +#define CSR_MIE_MEIE_SET(x) (((uint32_t)(x) << CSR_MIE_MEIE_SHIFT) & CSR_MIE_MEIE_MASK) +#define CSR_MIE_MEIE_GET(x) (((uint32_t)(x) & CSR_MIE_MEIE_MASK) >> CSR_MIE_MEIE_SHIFT) + +/* + * UEIE (RW) + * + * U mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_UEIE_MASK (0x100U) +#define CSR_MIE_UEIE_SHIFT (8U) +#define CSR_MIE_UEIE_SET(x) (((uint32_t)(x) << CSR_MIE_UEIE_SHIFT) & CSR_MIE_UEIE_MASK) +#define CSR_MIE_UEIE_GET(x) (((uint32_t)(x) & CSR_MIE_UEIE_MASK) >> CSR_MIE_UEIE_SHIFT) + +/* + * MTIE (RW) + * + * M mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_MTIE_MASK (0x80U) +#define CSR_MIE_MTIE_SHIFT (7U) +#define CSR_MIE_MTIE_SET(x) (((uint32_t)(x) << CSR_MIE_MTIE_SHIFT) & CSR_MIE_MTIE_MASK) +#define CSR_MIE_MTIE_GET(x) (((uint32_t)(x) & CSR_MIE_MTIE_MASK) >> CSR_MIE_MTIE_SHIFT) + +/* + * UTIE (RW) + * + * U mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_UTIE_MASK (0x10U) +#define CSR_MIE_UTIE_SHIFT (4U) +#define CSR_MIE_UTIE_SET(x) (((uint32_t)(x) << CSR_MIE_UTIE_SHIFT) & CSR_MIE_UTIE_MASK) +#define CSR_MIE_UTIE_GET(x) (((uint32_t)(x) & CSR_MIE_UTIE_MASK) >> CSR_MIE_UTIE_SHIFT) + +/* + * MSIE (RW) + * + * M mode software interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_MSIE_MASK (0x8U) +#define CSR_MIE_MSIE_SHIFT (3U) +#define CSR_MIE_MSIE_SET(x) (((uint32_t)(x) << CSR_MIE_MSIE_SHIFT) & CSR_MIE_MSIE_MASK) +#define CSR_MIE_MSIE_GET(x) (((uint32_t)(x) & CSR_MIE_MSIE_MASK) >> CSR_MIE_MSIE_SHIFT) + +/* + * USIE (RW) + * + * U mode software interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_USIE_MASK (0x1U) +#define CSR_MIE_USIE_SHIFT (0U) +#define CSR_MIE_USIE_SET(x) (((uint32_t)(x) << CSR_MIE_USIE_SHIFT) & CSR_MIE_USIE_MASK) +#define CSR_MIE_USIE_GET(x) (((uint32_t)(x) & CSR_MIE_USIE_MASK) >> CSR_MIE_USIE_SHIFT) + +/* Bitfield definition for register: MTVEC */ +/* + * BASE_31_2 (RW) + * + * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode + */ +#define CSR_MTVEC_BASE_31_2_MASK (0xFFFFFFFCUL) +#define CSR_MTVEC_BASE_31_2_SHIFT (2U) +#define CSR_MTVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_MTVEC_BASE_31_2_SHIFT) & CSR_MTVEC_BASE_31_2_MASK) +#define CSR_MTVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_MTVEC_BASE_31_2_MASK) >> CSR_MTVEC_BASE_31_2_SHIFT) + +/* Bitfield definition for register: MCOUNTEREN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_HPM6_MASK (0x40U) +#define CSR_MCOUNTEREN_HPM6_SHIFT (6U) +#define CSR_MCOUNTEREN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM6_SHIFT) & CSR_MCOUNTEREN_HPM6_MASK) +#define CSR_MCOUNTEREN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM6_MASK) >> CSR_MCOUNTEREN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_HPM5_MASK (0x20U) +#define CSR_MCOUNTEREN_HPM5_SHIFT (5U) +#define CSR_MCOUNTEREN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM5_SHIFT) & CSR_MCOUNTEREN_HPM5_MASK) +#define CSR_MCOUNTEREN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM5_MASK) >> CSR_MCOUNTEREN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_HPM4_MASK (0x10U) +#define CSR_MCOUNTEREN_HPM4_SHIFT (4U) +#define CSR_MCOUNTEREN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM4_SHIFT) & CSR_MCOUNTEREN_HPM4_MASK) +#define CSR_MCOUNTEREN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM4_MASK) >> CSR_MCOUNTEREN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_HPM3_MASK (0x8U) +#define CSR_MCOUNTEREN_HPM3_SHIFT (3U) +#define CSR_MCOUNTEREN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM3_SHIFT) & CSR_MCOUNTEREN_HPM3_MASK) +#define CSR_MCOUNTEREN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM3_MASK) >> CSR_MCOUNTEREN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_IR_MASK (0x4U) +#define CSR_MCOUNTEREN_IR_SHIFT (2U) +#define CSR_MCOUNTEREN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_IR_SHIFT) & CSR_MCOUNTEREN_IR_MASK) +#define CSR_MCOUNTEREN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_IR_MASK) >> CSR_MCOUNTEREN_IR_SHIFT) + +/* + * TM (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_TM_MASK (0x2U) +#define CSR_MCOUNTEREN_TM_SHIFT (1U) +#define CSR_MCOUNTEREN_TM_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_TM_SHIFT) & CSR_MCOUNTEREN_TM_MASK) +#define CSR_MCOUNTEREN_TM_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_TM_MASK) >> CSR_MCOUNTEREN_TM_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_CY_MASK (0x1U) +#define CSR_MCOUNTEREN_CY_SHIFT (0U) +#define CSR_MCOUNTEREN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_CY_SHIFT) & CSR_MCOUNTEREN_CY_MASK) +#define CSR_MCOUNTEREN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_CY_MASK) >> CSR_MCOUNTEREN_CY_SHIFT) + +/* Bitfield definition for register: MHPMEVENT3 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT3_SEL_MASK (0x1F0U) +#define CSR_MHPMEVENT3_SEL_SHIFT (4U) +#define CSR_MHPMEVENT3_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT3_SEL_SHIFT) & CSR_MHPMEVENT3_SEL_MASK) +#define CSR_MHPMEVENT3_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT3_SEL_MASK) >> CSR_MHPMEVENT3_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT3_TYPE_MASK (0xFU) +#define CSR_MHPMEVENT3_TYPE_SHIFT (0U) +#define CSR_MHPMEVENT3_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT3_TYPE_SHIFT) & CSR_MHPMEVENT3_TYPE_MASK) +#define CSR_MHPMEVENT3_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT3_TYPE_MASK) >> CSR_MHPMEVENT3_TYPE_SHIFT) + +/* Bitfield definition for register: MHPMEVENT4 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT4_SEL_MASK (0x1F0U) +#define CSR_MHPMEVENT4_SEL_SHIFT (4U) +#define CSR_MHPMEVENT4_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT4_SEL_SHIFT) & CSR_MHPMEVENT4_SEL_MASK) +#define CSR_MHPMEVENT4_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT4_SEL_MASK) >> CSR_MHPMEVENT4_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT4_TYPE_MASK (0xFU) +#define CSR_MHPMEVENT4_TYPE_SHIFT (0U) +#define CSR_MHPMEVENT4_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT4_TYPE_SHIFT) & CSR_MHPMEVENT4_TYPE_MASK) +#define CSR_MHPMEVENT4_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT4_TYPE_MASK) >> CSR_MHPMEVENT4_TYPE_SHIFT) + +/* Bitfield definition for register: MHPMEVENT5 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT5_SEL_MASK (0x1F0U) +#define CSR_MHPMEVENT5_SEL_SHIFT (4U) +#define CSR_MHPMEVENT5_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT5_SEL_SHIFT) & CSR_MHPMEVENT5_SEL_MASK) +#define CSR_MHPMEVENT5_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT5_SEL_MASK) >> CSR_MHPMEVENT5_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT5_TYPE_MASK (0xFU) +#define CSR_MHPMEVENT5_TYPE_SHIFT (0U) +#define CSR_MHPMEVENT5_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT5_TYPE_SHIFT) & CSR_MHPMEVENT5_TYPE_MASK) +#define CSR_MHPMEVENT5_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT5_TYPE_MASK) >> CSR_MHPMEVENT5_TYPE_SHIFT) + +/* Bitfield definition for register: MHPMEVENT6 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT6_SEL_MASK (0x1F0U) +#define CSR_MHPMEVENT6_SEL_SHIFT (4U) +#define CSR_MHPMEVENT6_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT6_SEL_SHIFT) & CSR_MHPMEVENT6_SEL_MASK) +#define CSR_MHPMEVENT6_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT6_SEL_MASK) >> CSR_MHPMEVENT6_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT6_TYPE_MASK (0xFU) +#define CSR_MHPMEVENT6_TYPE_SHIFT (0U) +#define CSR_MHPMEVENT6_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT6_TYPE_SHIFT) & CSR_MHPMEVENT6_TYPE_MASK) +#define CSR_MHPMEVENT6_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT6_TYPE_MASK) >> CSR_MHPMEVENT6_TYPE_SHIFT) + +/* Bitfield definition for register: MSCRATCH */ +/* + * MSCRATCH (RW) + * + * Scratch register storage. + */ +#define CSR_MSCRATCH_MSCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_MSCRATCH_MSCRATCH_SHIFT (0U) +#define CSR_MSCRATCH_MSCRATCH_SET(x) (((uint32_t)(x) << CSR_MSCRATCH_MSCRATCH_SHIFT) & CSR_MSCRATCH_MSCRATCH_MASK) +#define CSR_MSCRATCH_MSCRATCH_GET(x) (((uint32_t)(x) & CSR_MSCRATCH_MSCRATCH_MASK) >> CSR_MSCRATCH_MSCRATCH_SHIFT) + +/* Bitfield definition for register: MEPC */ +/* + * EPC (RW) + * + * Exception program counter. + */ +#define CSR_MEPC_EPC_MASK (0xFFFFFFFEUL) +#define CSR_MEPC_EPC_SHIFT (1U) +#define CSR_MEPC_EPC_SET(x) (((uint32_t)(x) << CSR_MEPC_EPC_SHIFT) & CSR_MEPC_EPC_MASK) +#define CSR_MEPC_EPC_GET(x) (((uint32_t)(x) & CSR_MEPC_EPC_MASK) >> CSR_MEPC_EPC_SHIFT) + +/* Bitfield definition for register: MCAUSE */ +/* + * INTERRUPT (RW) + * + * Interrupt + */ +#define CSR_MCAUSE_INTERRUPT_MASK (0x80000000UL) +#define CSR_MCAUSE_INTERRUPT_SHIFT (31U) +#define CSR_MCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_MCAUSE_INTERRUPT_SHIFT) & CSR_MCAUSE_INTERRUPT_MASK) +#define CSR_MCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_MCAUSE_INTERRUPT_MASK) >> CSR_MCAUSE_INTERRUPT_SHIFT) + +/* + * EXCEPTION_CODE (RW) + * + * Exception code + * When interrupt is 1, the value means: + * 0:User software interrupt + * 1:Supervisor software interrupt + * 3:Machine software interrupt + * 4:User timer interrupt + * 5:Supervisor timer interrupt + * 7:Machine timer interrupt + * 8:User external interrupt + * 9:Supervisor external interrupt + * 11:Machine external interrupt + * 16:Imprecise ECC error interrupt (slave port accesses, D-Cache evictions, and nonblocking load/stores) (M-mode) + * 17:Bus read/write transaction error interrupt (M-mode) + * 18:Performance monitor overflow interrupt (M-mode) + * 256+16:Imprecise ECC error interrupt (slave port accesses, D-Cache evictions, and nonblocking load/stores) (S-mode) + * 256+17:Bus write transaction error interrupt (S-mode) + * 256+18:Performance monitor overflow interrupt (S-mode) + * When interrupt bit is 0, the value means: + * 0:Instruction address misaligned + * 1:Instruction access fault + * 2:Illegal instruction + * 3:Breakpoint + * 4:Load address misaligned + * 5:Load access fault + * 6:Store/AMO address misaligned + * 7:Store/AMO access fault + * 8:Environment call from U-mode + * 9:Environment call from S-mode + * 11:Environment call from M-mode + * 32:Stack overflow exception + * 33:Stack underflow exception + * 40-47:Reserved + */ +#define CSR_MCAUSE_EXCEPTION_CODE_MASK (0xFFFU) +#define CSR_MCAUSE_EXCEPTION_CODE_SHIFT (0U) +#define CSR_MCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_MCAUSE_EXCEPTION_CODE_SHIFT) & CSR_MCAUSE_EXCEPTION_CODE_MASK) +#define CSR_MCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_MCAUSE_EXCEPTION_CODE_MASK) >> CSR_MCAUSE_EXCEPTION_CODE_SHIFT) + +/* Bitfield definition for register: MTVAL */ +/* + * MTVAL (RW) + * + * Exception-specific information for software trap handling. + */ +#define CSR_MTVAL_MTVAL_MASK (0xFFFFFFFFUL) +#define CSR_MTVAL_MTVAL_SHIFT (0U) +#define CSR_MTVAL_MTVAL_SET(x) (((uint32_t)(x) << CSR_MTVAL_MTVAL_SHIFT) & CSR_MTVAL_MTVAL_MASK) +#define CSR_MTVAL_MTVAL_GET(x) (((uint32_t)(x) & CSR_MTVAL_MTVAL_MASK) >> CSR_MTVAL_MTVAL_SHIFT) + +/* Bitfield definition for register: MIP */ +/* + * PMOVI (RW) + * + * Performance monitor overflow local interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_PMOVI_MASK (0x40000UL) +#define CSR_MIP_PMOVI_SHIFT (18U) +#define CSR_MIP_PMOVI_SET(x) (((uint32_t)(x) << CSR_MIP_PMOVI_SHIFT) & CSR_MIP_PMOVI_MASK) +#define CSR_MIP_PMOVI_GET(x) (((uint32_t)(x) & CSR_MIP_PMOVI_MASK) >> CSR_MIP_PMOVI_SHIFT) + +/* + * BWEI (RW) + * + * Bus read/write transaction error local interrupt pending bit. The processor may receive bus errors on load/store instructions or cache writebacks. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_BWEI_MASK (0x20000UL) +#define CSR_MIP_BWEI_SHIFT (17U) +#define CSR_MIP_BWEI_SET(x) (((uint32_t)(x) << CSR_MIP_BWEI_SHIFT) & CSR_MIP_BWEI_MASK) +#define CSR_MIP_BWEI_GET(x) (((uint32_t)(x) & CSR_MIP_BWEI_MASK) >> CSR_MIP_BWEI_SHIFT) + +/* + * IMECCI (RW) + * + * Imprecise ECC error local interrupt enable bit. The processor may receive imprecise ECC errors on slave port accesses or cache writebacks. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_IMECCI_MASK (0x10000UL) +#define CSR_MIP_IMECCI_SHIFT (16U) +#define CSR_MIP_IMECCI_SET(x) (((uint32_t)(x) << CSR_MIP_IMECCI_SHIFT) & CSR_MIP_IMECCI_MASK) +#define CSR_MIP_IMECCI_GET(x) (((uint32_t)(x) & CSR_MIP_IMECCI_MASK) >> CSR_MIP_IMECCI_SHIFT) + +/* + * MEIP (RW) + * + * M mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_MEIP_MASK (0x800U) +#define CSR_MIP_MEIP_SHIFT (11U) +#define CSR_MIP_MEIP_SET(x) (((uint32_t)(x) << CSR_MIP_MEIP_SHIFT) & CSR_MIP_MEIP_MASK) +#define CSR_MIP_MEIP_GET(x) (((uint32_t)(x) & CSR_MIP_MEIP_MASK) >> CSR_MIP_MEIP_SHIFT) + +/* + * SEIP (RW) + * + * S mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_SEIP_MASK (0x200U) +#define CSR_MIP_SEIP_SHIFT (9U) +#define CSR_MIP_SEIP_SET(x) (((uint32_t)(x) << CSR_MIP_SEIP_SHIFT) & CSR_MIP_SEIP_MASK) +#define CSR_MIP_SEIP_GET(x) (((uint32_t)(x) & CSR_MIP_SEIP_MASK) >> CSR_MIP_SEIP_SHIFT) + +/* + * UEIP (RW) + * + * U mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_UEIP_MASK (0x100U) +#define CSR_MIP_UEIP_SHIFT (8U) +#define CSR_MIP_UEIP_SET(x) (((uint32_t)(x) << CSR_MIP_UEIP_SHIFT) & CSR_MIP_UEIP_MASK) +#define CSR_MIP_UEIP_GET(x) (((uint32_t)(x) & CSR_MIP_UEIP_MASK) >> CSR_MIP_UEIP_SHIFT) + +/* + * MTIP (RW) + * + * M mode timer interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_MTIP_MASK (0x80U) +#define CSR_MIP_MTIP_SHIFT (7U) +#define CSR_MIP_MTIP_SET(x) (((uint32_t)(x) << CSR_MIP_MTIP_SHIFT) & CSR_MIP_MTIP_MASK) +#define CSR_MIP_MTIP_GET(x) (((uint32_t)(x) & CSR_MIP_MTIP_MASK) >> CSR_MIP_MTIP_SHIFT) + +/* + * STIP (RW) + * + * S mode timer interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_STIP_MASK (0x20U) +#define CSR_MIP_STIP_SHIFT (5U) +#define CSR_MIP_STIP_SET(x) (((uint32_t)(x) << CSR_MIP_STIP_SHIFT) & CSR_MIP_STIP_MASK) +#define CSR_MIP_STIP_GET(x) (((uint32_t)(x) & CSR_MIP_STIP_MASK) >> CSR_MIP_STIP_SHIFT) + +/* + * UTIP (RW) + * + * U mode timer interrupt pending bit + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_UTIP_MASK (0x10U) +#define CSR_MIP_UTIP_SHIFT (4U) +#define CSR_MIP_UTIP_SET(x) (((uint32_t)(x) << CSR_MIP_UTIP_SHIFT) & CSR_MIP_UTIP_MASK) +#define CSR_MIP_UTIP_GET(x) (((uint32_t)(x) & CSR_MIP_UTIP_MASK) >> CSR_MIP_UTIP_SHIFT) + +/* + * MSIP (RW) + * + * M mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_MSIP_MASK (0x8U) +#define CSR_MIP_MSIP_SHIFT (3U) +#define CSR_MIP_MSIP_SET(x) (((uint32_t)(x) << CSR_MIP_MSIP_SHIFT) & CSR_MIP_MSIP_MASK) +#define CSR_MIP_MSIP_GET(x) (((uint32_t)(x) & CSR_MIP_MSIP_MASK) >> CSR_MIP_MSIP_SHIFT) + +/* + * SSIP (RW) + * + * S mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_SSIP_MASK (0x2U) +#define CSR_MIP_SSIP_SHIFT (1U) +#define CSR_MIP_SSIP_SET(x) (((uint32_t)(x) << CSR_MIP_SSIP_SHIFT) & CSR_MIP_SSIP_MASK) +#define CSR_MIP_SSIP_GET(x) (((uint32_t)(x) & CSR_MIP_SSIP_MASK) >> CSR_MIP_SSIP_SHIFT) + +/* + * USIP (RW) + * + * U mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_USIP_MASK (0x1U) +#define CSR_MIP_USIP_SHIFT (0U) +#define CSR_MIP_USIP_SET(x) (((uint32_t)(x) << CSR_MIP_USIP_SHIFT) & CSR_MIP_USIP_MASK) +#define CSR_MIP_USIP_GET(x) (((uint32_t)(x) & CSR_MIP_USIP_MASK) >> CSR_MIP_USIP_SHIFT) + +/* Bitfield definition for register: PMPCFG0 */ +/* + * PMP3CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG0_PMP3CFG_MASK (0xFF000000UL) +#define CSR_PMPCFG0_PMP3CFG_SHIFT (24U) +#define CSR_PMPCFG0_PMP3CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP3CFG_SHIFT) & CSR_PMPCFG0_PMP3CFG_MASK) +#define CSR_PMPCFG0_PMP3CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP3CFG_MASK) >> CSR_PMPCFG0_PMP3CFG_SHIFT) + +/* + * PMP2CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG0_PMP2CFG_MASK (0xFF0000UL) +#define CSR_PMPCFG0_PMP2CFG_SHIFT (16U) +#define CSR_PMPCFG0_PMP2CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP2CFG_SHIFT) & CSR_PMPCFG0_PMP2CFG_MASK) +#define CSR_PMPCFG0_PMP2CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP2CFG_MASK) >> CSR_PMPCFG0_PMP2CFG_SHIFT) + +/* + * PMP1CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG0_PMP1CFG_MASK (0xFF00U) +#define CSR_PMPCFG0_PMP1CFG_SHIFT (8U) +#define CSR_PMPCFG0_PMP1CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP1CFG_SHIFT) & CSR_PMPCFG0_PMP1CFG_MASK) +#define CSR_PMPCFG0_PMP1CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP1CFG_MASK) >> CSR_PMPCFG0_PMP1CFG_SHIFT) + +/* + * PMP0CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG0_PMP0CFG_MASK (0xFFU) +#define CSR_PMPCFG0_PMP0CFG_SHIFT (0U) +#define CSR_PMPCFG0_PMP0CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP0CFG_SHIFT) & CSR_PMPCFG0_PMP0CFG_MASK) +#define CSR_PMPCFG0_PMP0CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP0CFG_MASK) >> CSR_PMPCFG0_PMP0CFG_SHIFT) + +/* Bitfield definition for register: PMPCFG1 */ +/* + * PMP7CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG1_PMP7CFG_MASK (0xFF000000UL) +#define CSR_PMPCFG1_PMP7CFG_SHIFT (24U) +#define CSR_PMPCFG1_PMP7CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP7CFG_SHIFT) & CSR_PMPCFG1_PMP7CFG_MASK) +#define CSR_PMPCFG1_PMP7CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP7CFG_MASK) >> CSR_PMPCFG1_PMP7CFG_SHIFT) + +/* + * PMP6CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG1_PMP6CFG_MASK (0xFF0000UL) +#define CSR_PMPCFG1_PMP6CFG_SHIFT (16U) +#define CSR_PMPCFG1_PMP6CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP6CFG_SHIFT) & CSR_PMPCFG1_PMP6CFG_MASK) +#define CSR_PMPCFG1_PMP6CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP6CFG_MASK) >> CSR_PMPCFG1_PMP6CFG_SHIFT) + +/* + * PMP5CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG1_PMP5CFG_MASK (0xFF00U) +#define CSR_PMPCFG1_PMP5CFG_SHIFT (8U) +#define CSR_PMPCFG1_PMP5CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP5CFG_SHIFT) & CSR_PMPCFG1_PMP5CFG_MASK) +#define CSR_PMPCFG1_PMP5CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP5CFG_MASK) >> CSR_PMPCFG1_PMP5CFG_SHIFT) + +/* + * PMP4CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG1_PMP4CFG_MASK (0xFFU) +#define CSR_PMPCFG1_PMP4CFG_SHIFT (0U) +#define CSR_PMPCFG1_PMP4CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP4CFG_SHIFT) & CSR_PMPCFG1_PMP4CFG_MASK) +#define CSR_PMPCFG1_PMP4CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP4CFG_MASK) >> CSR_PMPCFG1_PMP4CFG_SHIFT) + +/* Bitfield definition for register: PMPCFG2 */ +/* + * PMP11CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG2_PMP11CFG_MASK (0xFF000000UL) +#define CSR_PMPCFG2_PMP11CFG_SHIFT (24U) +#define CSR_PMPCFG2_PMP11CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP11CFG_SHIFT) & CSR_PMPCFG2_PMP11CFG_MASK) +#define CSR_PMPCFG2_PMP11CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP11CFG_MASK) >> CSR_PMPCFG2_PMP11CFG_SHIFT) + +/* + * PMP10CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG2_PMP10CFG_MASK (0xFF0000UL) +#define CSR_PMPCFG2_PMP10CFG_SHIFT (16U) +#define CSR_PMPCFG2_PMP10CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP10CFG_SHIFT) & CSR_PMPCFG2_PMP10CFG_MASK) +#define CSR_PMPCFG2_PMP10CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP10CFG_MASK) >> CSR_PMPCFG2_PMP10CFG_SHIFT) + +/* + * PMP9CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG2_PMP9CFG_MASK (0xFF00U) +#define CSR_PMPCFG2_PMP9CFG_SHIFT (8U) +#define CSR_PMPCFG2_PMP9CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP9CFG_SHIFT) & CSR_PMPCFG2_PMP9CFG_MASK) +#define CSR_PMPCFG2_PMP9CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP9CFG_MASK) >> CSR_PMPCFG2_PMP9CFG_SHIFT) + +/* + * PMP8CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG2_PMP8CFG_MASK (0xFFU) +#define CSR_PMPCFG2_PMP8CFG_SHIFT (0U) +#define CSR_PMPCFG2_PMP8CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP8CFG_SHIFT) & CSR_PMPCFG2_PMP8CFG_MASK) +#define CSR_PMPCFG2_PMP8CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP8CFG_MASK) >> CSR_PMPCFG2_PMP8CFG_SHIFT) + +/* Bitfield definition for register: PMPCFG3 */ +/* + * PMP15CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG3_PMP15CFG_MASK (0xFF000000UL) +#define CSR_PMPCFG3_PMP15CFG_SHIFT (24U) +#define CSR_PMPCFG3_PMP15CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP15CFG_SHIFT) & CSR_PMPCFG3_PMP15CFG_MASK) +#define CSR_PMPCFG3_PMP15CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP15CFG_MASK) >> CSR_PMPCFG3_PMP15CFG_SHIFT) + +/* + * PMP14CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG3_PMP14CFG_MASK (0xFF0000UL) +#define CSR_PMPCFG3_PMP14CFG_SHIFT (16U) +#define CSR_PMPCFG3_PMP14CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP14CFG_SHIFT) & CSR_PMPCFG3_PMP14CFG_MASK) +#define CSR_PMPCFG3_PMP14CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP14CFG_MASK) >> CSR_PMPCFG3_PMP14CFG_SHIFT) + +/* + * PMP13CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG3_PMP13CFG_MASK (0xFF00U) +#define CSR_PMPCFG3_PMP13CFG_SHIFT (8U) +#define CSR_PMPCFG3_PMP13CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP13CFG_SHIFT) & CSR_PMPCFG3_PMP13CFG_MASK) +#define CSR_PMPCFG3_PMP13CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP13CFG_MASK) >> CSR_PMPCFG3_PMP13CFG_SHIFT) + +/* + * PMP12CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG3_PMP12CFG_MASK (0xFFU) +#define CSR_PMPCFG3_PMP12CFG_SHIFT (0U) +#define CSR_PMPCFG3_PMP12CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP12CFG_SHIFT) & CSR_PMPCFG3_PMP12CFG_MASK) +#define CSR_PMPCFG3_PMP12CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP12CFG_MASK) >> CSR_PMPCFG3_PMP12CFG_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * Register Content : Match Size(Byte) + * aaaa. . . aaa0 8 + * aaaa. . . aa01 16 + * aaaa. . . a011 32 + * . . . . . . + * aa01. . . 1111 2^{XLEN} + * a011. . . 1111 2^{XLEN+1} + * 0111. . . 1111 2^{XLEN+2} + * 1111. . . 1111 2^{XLEN+3*1} + */ +#define CSR_PMPADDR0_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR0_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR0_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR0_PMPADDR_31_2_SHIFT) & CSR_PMPADDR0_PMPADDR_31_2_MASK) +#define CSR_PMPADDR0_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR0_PMPADDR_31_2_MASK) >> CSR_PMPADDR0_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR1_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR1_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR1_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR1_PMPADDR_31_2_SHIFT) & CSR_PMPADDR1_PMPADDR_31_2_MASK) +#define CSR_PMPADDR1_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR1_PMPADDR_31_2_MASK) >> CSR_PMPADDR1_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR2_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR2_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR2_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR2_PMPADDR_31_2_SHIFT) & CSR_PMPADDR2_PMPADDR_31_2_MASK) +#define CSR_PMPADDR2_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR2_PMPADDR_31_2_MASK) >> CSR_PMPADDR2_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR3_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR3_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR3_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR3_PMPADDR_31_2_SHIFT) & CSR_PMPADDR3_PMPADDR_31_2_MASK) +#define CSR_PMPADDR3_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR3_PMPADDR_31_2_MASK) >> CSR_PMPADDR3_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR4_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR4_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR4_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR4_PMPADDR_31_2_SHIFT) & CSR_PMPADDR4_PMPADDR_31_2_MASK) +#define CSR_PMPADDR4_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR4_PMPADDR_31_2_MASK) >> CSR_PMPADDR4_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR5_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR5_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR5_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR5_PMPADDR_31_2_SHIFT) & CSR_PMPADDR5_PMPADDR_31_2_MASK) +#define CSR_PMPADDR5_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR5_PMPADDR_31_2_MASK) >> CSR_PMPADDR5_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR6_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR6_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR6_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR6_PMPADDR_31_2_SHIFT) & CSR_PMPADDR6_PMPADDR_31_2_MASK) +#define CSR_PMPADDR6_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR6_PMPADDR_31_2_MASK) >> CSR_PMPADDR6_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR7_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR7_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR7_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR7_PMPADDR_31_2_SHIFT) & CSR_PMPADDR7_PMPADDR_31_2_MASK) +#define CSR_PMPADDR7_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR7_PMPADDR_31_2_MASK) >> CSR_PMPADDR7_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR8_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR8_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR8_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR8_PMPADDR_31_2_SHIFT) & CSR_PMPADDR8_PMPADDR_31_2_MASK) +#define CSR_PMPADDR8_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR8_PMPADDR_31_2_MASK) >> CSR_PMPADDR8_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR9_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR9_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR9_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR9_PMPADDR_31_2_SHIFT) & CSR_PMPADDR9_PMPADDR_31_2_MASK) +#define CSR_PMPADDR9_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR9_PMPADDR_31_2_MASK) >> CSR_PMPADDR9_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR10_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR10_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR10_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR10_PMPADDR_31_2_SHIFT) & CSR_PMPADDR10_PMPADDR_31_2_MASK) +#define CSR_PMPADDR10_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR10_PMPADDR_31_2_MASK) >> CSR_PMPADDR10_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR11_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR11_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR11_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR11_PMPADDR_31_2_SHIFT) & CSR_PMPADDR11_PMPADDR_31_2_MASK) +#define CSR_PMPADDR11_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR11_PMPADDR_31_2_MASK) >> CSR_PMPADDR11_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR12_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR12_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR12_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR12_PMPADDR_31_2_SHIFT) & CSR_PMPADDR12_PMPADDR_31_2_MASK) +#define CSR_PMPADDR12_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR12_PMPADDR_31_2_MASK) >> CSR_PMPADDR12_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR13_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR13_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR13_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR13_PMPADDR_31_2_SHIFT) & CSR_PMPADDR13_PMPADDR_31_2_MASK) +#define CSR_PMPADDR13_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR13_PMPADDR_31_2_MASK) >> CSR_PMPADDR13_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR14_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR14_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR14_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR14_PMPADDR_31_2_SHIFT) & CSR_PMPADDR14_PMPADDR_31_2_MASK) +#define CSR_PMPADDR14_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR14_PMPADDR_31_2_MASK) >> CSR_PMPADDR14_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR15_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR15_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR15_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR15_PMPADDR_31_2_SHIFT) & CSR_PMPADDR15_PMPADDR_31_2_MASK) +#define CSR_PMPADDR15_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR15_PMPADDR_31_2_MASK) >> CSR_PMPADDR15_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register: TSELECT */ +/* + * TRIGGER_INDEX (RW) + * + * This register determines which trigger is accessible through other trigger registers. + */ +#define CSR_TSELECT_TRIGGER_INDEX_MASK (0xFFFFFFFFUL) +#define CSR_TSELECT_TRIGGER_INDEX_SHIFT (0U) +#define CSR_TSELECT_TRIGGER_INDEX_SET(x) (((uint32_t)(x) << CSR_TSELECT_TRIGGER_INDEX_SHIFT) & CSR_TSELECT_TRIGGER_INDEX_MASK) +#define CSR_TSELECT_TRIGGER_INDEX_GET(x) (((uint32_t)(x) & CSR_TSELECT_TRIGGER_INDEX_MASK) >> CSR_TSELECT_TRIGGER_INDEX_SHIFT) + +/* Bitfield definition for register: TDATA1 */ +/* + * TYPE (RW) + * + * Indicates the trigger type. + * 0:The selected trigger is invalid. + * 2:The selected trigger is an address/data match trigger. + * 3:The selected trigger is an instruction count trigger + * 4:The selected trigger is an interrupt trigger. + * 5:The selected trigger is an exception trigger. + */ +#define CSR_TDATA1_TYPE_MASK (0xF0000000UL) +#define CSR_TDATA1_TYPE_SHIFT (28U) +#define CSR_TDATA1_TYPE_SET(x) (((uint32_t)(x) << CSR_TDATA1_TYPE_SHIFT) & CSR_TDATA1_TYPE_MASK) +#define CSR_TDATA1_TYPE_GET(x) (((uint32_t)(x) & CSR_TDATA1_TYPE_MASK) >> CSR_TDATA1_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_TDATA1_DMODE_MASK (0x8000000UL) +#define CSR_TDATA1_DMODE_SHIFT (27U) +#define CSR_TDATA1_DMODE_SET(x) (((uint32_t)(x) << CSR_TDATA1_DMODE_SHIFT) & CSR_TDATA1_DMODE_MASK) +#define CSR_TDATA1_DMODE_GET(x) (((uint32_t)(x) & CSR_TDATA1_DMODE_MASK) >> CSR_TDATA1_DMODE_SHIFT) + +/* + * DATA (RW) + * + * Trigger-specific data + */ +#define CSR_TDATA1_DATA_MASK (0x7FFFFFFUL) +#define CSR_TDATA1_DATA_SHIFT (0U) +#define CSR_TDATA1_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA1_DATA_SHIFT) & CSR_TDATA1_DATA_MASK) +#define CSR_TDATA1_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA1_DATA_MASK) >> CSR_TDATA1_DATA_SHIFT) + +/* Bitfield definition for register: MCONTROL */ +/* + * TYPE (RW) + * + * Indicates the trigger type. + * 0:The selected trigger is invalid. + * 2:The selected trigger is an address/data match trigger. + */ +#define CSR_MCONTROL_TYPE_MASK (0xF0000000UL) +#define CSR_MCONTROL_TYPE_SHIFT (28U) +#define CSR_MCONTROL_TYPE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_TYPE_SHIFT) & CSR_MCONTROL_TYPE_MASK) +#define CSR_MCONTROL_TYPE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_TYPE_MASK) >> CSR_MCONTROL_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_MCONTROL_DMODE_MASK (0x8000000UL) +#define CSR_MCONTROL_DMODE_SHIFT (27U) +#define CSR_MCONTROL_DMODE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_DMODE_SHIFT) & CSR_MCONTROL_DMODE_MASK) +#define CSR_MCONTROL_DMODE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_DMODE_MASK) >> CSR_MCONTROL_DMODE_SHIFT) + +/* + * MASKMAX (RO) + * + * Indicates the largest naturally aligned range supported by the hardware is 2ˆ12 bytes. + */ +#define CSR_MCONTROL_MASKMAX_MASK (0x7E00000UL) +#define CSR_MCONTROL_MASKMAX_SHIFT (21U) +#define CSR_MCONTROL_MASKMAX_GET(x) (((uint32_t)(x) & CSR_MCONTROL_MASKMAX_MASK) >> CSR_MCONTROL_MASKMAX_SHIFT) + +/* + * ACTION (RW) + * + * Setting this field to select what happens when this trigger matches. + * 0:Raise a breakpoint exception + * 1:Enter Debug Mode. (Only supported when DMODE is 1.) + */ +#define CSR_MCONTROL_ACTION_MASK (0xF000U) +#define CSR_MCONTROL_ACTION_SHIFT (12U) +#define CSR_MCONTROL_ACTION_SET(x) (((uint32_t)(x) << CSR_MCONTROL_ACTION_SHIFT) & CSR_MCONTROL_ACTION_MASK) +#define CSR_MCONTROL_ACTION_GET(x) (((uint32_t)(x) & CSR_MCONTROL_ACTION_MASK) >> CSR_MCONTROL_ACTION_SHIFT) + +/* + * CHAIN (RW) + * + * Setting this field to enable trigger chain. + * 0:When this trigger matches, the configured action is taken. + * 1:While this trigger does not match, it prevents the trigger with the next index from matching. + * If Number of Triggers is 2, this field is hardwired to 0 on trigger 1 (tselect = 1). + * If Number of Triggers is 4, this field is hardwired + * to 0 on trigger 3 (tselect = 3). + * If Number of Triggers is 8, this field is hardwired to 0 on trigger 3 and trigger 7 (tselect = 3 or 7). + */ +#define CSR_MCONTROL_CHAIN_MASK (0x800U) +#define CSR_MCONTROL_CHAIN_SHIFT (11U) +#define CSR_MCONTROL_CHAIN_SET(x) (((uint32_t)(x) << CSR_MCONTROL_CHAIN_SHIFT) & CSR_MCONTROL_CHAIN_MASK) +#define CSR_MCONTROL_CHAIN_GET(x) (((uint32_t)(x) & CSR_MCONTROL_CHAIN_MASK) >> CSR_MCONTROL_CHAIN_SHIFT) + +/* + * MATCH (RW) + * + * Setting this field to select the matching scheme. 0:Matches when the value equals tdata2. 1:Matches when the top M bits of the value match the top M bits of tdata2. M is 31 minus the index of the least-significant bit containing 0 in tdata2. + * 2:Matches when the value is greater than (unsigned) or equal to tdata2. + * 3:Matches when the value is less than (unsigned) tdata2 + */ +#define CSR_MCONTROL_MATCH_MASK (0x780U) +#define CSR_MCONTROL_MATCH_SHIFT (7U) +#define CSR_MCONTROL_MATCH_SET(x) (((uint32_t)(x) << CSR_MCONTROL_MATCH_SHIFT) & CSR_MCONTROL_MATCH_MASK) +#define CSR_MCONTROL_MATCH_GET(x) (((uint32_t)(x) & CSR_MCONTROL_MATCH_MASK) >> CSR_MCONTROL_MATCH_SHIFT) + +/* + * M (RW) + * + * Setting this field to enable this trigger in M-mode. + */ +#define CSR_MCONTROL_M_MASK (0x40U) +#define CSR_MCONTROL_M_SHIFT (6U) +#define CSR_MCONTROL_M_SET(x) (((uint32_t)(x) << CSR_MCONTROL_M_SHIFT) & CSR_MCONTROL_M_MASK) +#define CSR_MCONTROL_M_GET(x) (((uint32_t)(x) & CSR_MCONTROL_M_MASK) >> CSR_MCONTROL_M_SHIFT) + +/* + * U (RW) + * + * Setting this field to enable this trigger in U-mode. + */ +#define CSR_MCONTROL_U_MASK (0x8U) +#define CSR_MCONTROL_U_SHIFT (3U) +#define CSR_MCONTROL_U_SET(x) (((uint32_t)(x) << CSR_MCONTROL_U_SHIFT) & CSR_MCONTROL_U_MASK) +#define CSR_MCONTROL_U_GET(x) (((uint32_t)(x) & CSR_MCONTROL_U_MASK) >> CSR_MCONTROL_U_SHIFT) + +/* + * EXECUTE (RW) + * + * Setting this field to enable this trigger to compare virtual address of an instruction. + */ +#define CSR_MCONTROL_EXECUTE_MASK (0x4U) +#define CSR_MCONTROL_EXECUTE_SHIFT (2U) +#define CSR_MCONTROL_EXECUTE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_EXECUTE_SHIFT) & CSR_MCONTROL_EXECUTE_MASK) +#define CSR_MCONTROL_EXECUTE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_EXECUTE_MASK) >> CSR_MCONTROL_EXECUTE_SHIFT) + +/* + * STORE (RW) + * + * Setting this field to enable this trigger to compare virtual address of a store. + */ +#define CSR_MCONTROL_STORE_MASK (0x2U) +#define CSR_MCONTROL_STORE_SHIFT (1U) +#define CSR_MCONTROL_STORE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_STORE_SHIFT) & CSR_MCONTROL_STORE_MASK) +#define CSR_MCONTROL_STORE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_STORE_MASK) >> CSR_MCONTROL_STORE_SHIFT) + +/* + * LOAD (RW) + * + * Setting this field to enable this trigger to compare virtual address of a load. + */ +#define CSR_MCONTROL_LOAD_MASK (0x1U) +#define CSR_MCONTROL_LOAD_SHIFT (0U) +#define CSR_MCONTROL_LOAD_SET(x) (((uint32_t)(x) << CSR_MCONTROL_LOAD_SHIFT) & CSR_MCONTROL_LOAD_MASK) +#define CSR_MCONTROL_LOAD_GET(x) (((uint32_t)(x) & CSR_MCONTROL_LOAD_MASK) >> CSR_MCONTROL_LOAD_SHIFT) + +/* Bitfield definition for register: ICOUNT */ +/* + * TYPE (RW) + * + * The selected trigger is an instruction count trigger. + */ +#define CSR_ICOUNT_TYPE_MASK (0xF0000000UL) +#define CSR_ICOUNT_TYPE_SHIFT (28U) +#define CSR_ICOUNT_TYPE_SET(x) (((uint32_t)(x) << CSR_ICOUNT_TYPE_SHIFT) & CSR_ICOUNT_TYPE_MASK) +#define CSR_ICOUNT_TYPE_GET(x) (((uint32_t)(x) & CSR_ICOUNT_TYPE_MASK) >> CSR_ICOUNT_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_ICOUNT_DMODE_MASK (0x8000000UL) +#define CSR_ICOUNT_DMODE_SHIFT (27U) +#define CSR_ICOUNT_DMODE_SET(x) (((uint32_t)(x) << CSR_ICOUNT_DMODE_SHIFT) & CSR_ICOUNT_DMODE_MASK) +#define CSR_ICOUNT_DMODE_GET(x) (((uint32_t)(x) & CSR_ICOUNT_DMODE_MASK) >> CSR_ICOUNT_DMODE_SHIFT) + +/* + * COUNT (RO) + * + * This field is hardwired to 1 for single-stepping support + */ +#define CSR_ICOUNT_COUNT_MASK (0x400U) +#define CSR_ICOUNT_COUNT_SHIFT (10U) +#define CSR_ICOUNT_COUNT_GET(x) (((uint32_t)(x) & CSR_ICOUNT_COUNT_MASK) >> CSR_ICOUNT_COUNT_SHIFT) + +/* + * M (RW) + * + * Setting this field to enable this trigger in M-mode. + */ +#define CSR_ICOUNT_M_MASK (0x200U) +#define CSR_ICOUNT_M_SHIFT (9U) +#define CSR_ICOUNT_M_SET(x) (((uint32_t)(x) << CSR_ICOUNT_M_SHIFT) & CSR_ICOUNT_M_MASK) +#define CSR_ICOUNT_M_GET(x) (((uint32_t)(x) & CSR_ICOUNT_M_MASK) >> CSR_ICOUNT_M_SHIFT) + +/* + * U (RW) + * + * Setting this field to enable this trigger in U-mode. + */ +#define CSR_ICOUNT_U_MASK (0x40U) +#define CSR_ICOUNT_U_SHIFT (6U) +#define CSR_ICOUNT_U_SET(x) (((uint32_t)(x) << CSR_ICOUNT_U_SHIFT) & CSR_ICOUNT_U_MASK) +#define CSR_ICOUNT_U_GET(x) (((uint32_t)(x) & CSR_ICOUNT_U_MASK) >> CSR_ICOUNT_U_SHIFT) + +/* + * ACTION (RW) + * + * Setting this field to select what happens when this trigger matches. + * 0:Raise a breakpoint exception + * 1:Enter Debug Mode. (Only supported when DMODE is 1.) + */ +#define CSR_ICOUNT_ACTION_MASK (0x3FU) +#define CSR_ICOUNT_ACTION_SHIFT (0U) +#define CSR_ICOUNT_ACTION_SET(x) (((uint32_t)(x) << CSR_ICOUNT_ACTION_SHIFT) & CSR_ICOUNT_ACTION_MASK) +#define CSR_ICOUNT_ACTION_GET(x) (((uint32_t)(x) & CSR_ICOUNT_ACTION_MASK) >> CSR_ICOUNT_ACTION_SHIFT) + +/* Bitfield definition for register: ITRIGGER */ +/* + * TYPE (RW) + * + * The selected trigger is an interrupt trigger. + */ +#define CSR_ITRIGGER_TYPE_MASK (0xF0000000UL) +#define CSR_ITRIGGER_TYPE_SHIFT (28U) +#define CSR_ITRIGGER_TYPE_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_TYPE_SHIFT) & CSR_ITRIGGER_TYPE_MASK) +#define CSR_ITRIGGER_TYPE_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_TYPE_MASK) >> CSR_ITRIGGER_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_ITRIGGER_DMODE_MASK (0x8000000UL) +#define CSR_ITRIGGER_DMODE_SHIFT (27U) +#define CSR_ITRIGGER_DMODE_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_DMODE_SHIFT) & CSR_ITRIGGER_DMODE_MASK) +#define CSR_ITRIGGER_DMODE_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_DMODE_MASK) >> CSR_ITRIGGER_DMODE_SHIFT) + +/* + * M (RW) + * + * Setting this field to enable this trigger in M-mode. + */ +#define CSR_ITRIGGER_M_MASK (0x200U) +#define CSR_ITRIGGER_M_SHIFT (9U) +#define CSR_ITRIGGER_M_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_M_SHIFT) & CSR_ITRIGGER_M_MASK) +#define CSR_ITRIGGER_M_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_M_MASK) >> CSR_ITRIGGER_M_SHIFT) + +/* + * U (RW) + * + * Setting this field to enable this trigger in U-mode. + */ +#define CSR_ITRIGGER_U_MASK (0x40U) +#define CSR_ITRIGGER_U_SHIFT (6U) +#define CSR_ITRIGGER_U_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_U_SHIFT) & CSR_ITRIGGER_U_MASK) +#define CSR_ITRIGGER_U_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_U_MASK) >> CSR_ITRIGGER_U_SHIFT) + +/* + * ACTION (RW) + * + * Setting this field to select what happens when this trigger matches. + * 0:Raise a breakpoint exception. + * 1:Enter Debug Mode. (Only supported when DMODE is 1.) + */ +#define CSR_ITRIGGER_ACTION_MASK (0x3FU) +#define CSR_ITRIGGER_ACTION_SHIFT (0U) +#define CSR_ITRIGGER_ACTION_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_ACTION_SHIFT) & CSR_ITRIGGER_ACTION_MASK) +#define CSR_ITRIGGER_ACTION_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_ACTION_MASK) >> CSR_ITRIGGER_ACTION_SHIFT) + +/* Bitfield definition for register: ETRIGGER */ +/* + * TYPE (RW) + * + * The selected trigger is an exception trigger. + */ +#define CSR_ETRIGGER_TYPE_MASK (0xF0000000UL) +#define CSR_ETRIGGER_TYPE_SHIFT (28U) +#define CSR_ETRIGGER_TYPE_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_TYPE_SHIFT) & CSR_ETRIGGER_TYPE_MASK) +#define CSR_ETRIGGER_TYPE_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_TYPE_MASK) >> CSR_ETRIGGER_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_ETRIGGER_DMODE_MASK (0x8000000UL) +#define CSR_ETRIGGER_DMODE_SHIFT (27U) +#define CSR_ETRIGGER_DMODE_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_DMODE_SHIFT) & CSR_ETRIGGER_DMODE_MASK) +#define CSR_ETRIGGER_DMODE_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_DMODE_MASK) >> CSR_ETRIGGER_DMODE_SHIFT) + +/* + * NMI (RW) + * + * Setting this field to enable this trigger in non-maskable interrupts, regardless of the values of s, u, and m. + */ +#define CSR_ETRIGGER_NMI_MASK (0x400U) +#define CSR_ETRIGGER_NMI_SHIFT (10U) +#define CSR_ETRIGGER_NMI_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_NMI_SHIFT) & CSR_ETRIGGER_NMI_MASK) +#define CSR_ETRIGGER_NMI_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_NMI_MASK) >> CSR_ETRIGGER_NMI_SHIFT) + +/* + * M (RW) + * + * Setting this field to enable this trigger in M-mode. + */ +#define CSR_ETRIGGER_M_MASK (0x200U) +#define CSR_ETRIGGER_M_SHIFT (9U) +#define CSR_ETRIGGER_M_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_M_SHIFT) & CSR_ETRIGGER_M_MASK) +#define CSR_ETRIGGER_M_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_M_MASK) >> CSR_ETRIGGER_M_SHIFT) + +/* + * U (RW) + * + * Setting this field to enable this trigger in U-mode. + */ +#define CSR_ETRIGGER_U_MASK (0x40U) +#define CSR_ETRIGGER_U_SHIFT (6U) +#define CSR_ETRIGGER_U_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_U_SHIFT) & CSR_ETRIGGER_U_MASK) +#define CSR_ETRIGGER_U_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_U_MASK) >> CSR_ETRIGGER_U_SHIFT) + +/* + * ACTION (RW) + * + * Setting this field to select what happens when this trigger matches. + * 0:Raise a breakpoint exception + * 1:Enter Debug Mode. (Only supported when DMODE is 1.) + */ +#define CSR_ETRIGGER_ACTION_MASK (0x3FU) +#define CSR_ETRIGGER_ACTION_SHIFT (0U) +#define CSR_ETRIGGER_ACTION_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_ACTION_SHIFT) & CSR_ETRIGGER_ACTION_MASK) +#define CSR_ETRIGGER_ACTION_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_ACTION_MASK) >> CSR_ETRIGGER_ACTION_SHIFT) + +/* Bitfield definition for register: TDATA2 */ +/* + * DATA (RW) + * + * This register provides accesses to the tdata2 register of the currently selected trigger registers selected by the tselect register, and it holds trigger-specific data.. + */ +#define CSR_TDATA2_DATA_MASK (0xFFFFFFFFUL) +#define CSR_TDATA2_DATA_SHIFT (0U) +#define CSR_TDATA2_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA2_DATA_SHIFT) & CSR_TDATA2_DATA_MASK) +#define CSR_TDATA2_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA2_DATA_MASK) >> CSR_TDATA2_DATA_SHIFT) + +/* Bitfield definition for register: TDATA3 */ +/* + * DATA (RW) + * + * This register provides accesses to the tdata3 register of the currently selected trigger registers selected by the tselect register, and it holds trigger-specific data.. + */ +#define CSR_TDATA3_DATA_MASK (0xFFFFFFFFUL) +#define CSR_TDATA3_DATA_SHIFT (0U) +#define CSR_TDATA3_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA3_DATA_SHIFT) & CSR_TDATA3_DATA_MASK) +#define CSR_TDATA3_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA3_DATA_MASK) >> CSR_TDATA3_DATA_SHIFT) + +/* Bitfield definition for register: TEXTRA */ +/* + * MVALUE (RW) + * + * Data used together with MSELECT. + */ +#define CSR_TEXTRA_MVALUE_MASK (0xFC000000UL) +#define CSR_TEXTRA_MVALUE_SHIFT (26U) +#define CSR_TEXTRA_MVALUE_SET(x) (((uint32_t)(x) << CSR_TEXTRA_MVALUE_SHIFT) & CSR_TEXTRA_MVALUE_MASK) +#define CSR_TEXTRA_MVALUE_GET(x) (((uint32_t)(x) & CSR_TEXTRA_MVALUE_MASK) >> CSR_TEXTRA_MVALUE_SHIFT) + +/* + * MSELECT (RW) + * + * 0:Ignore MVALUE. + * 1:This trigger will only match if the lower bits of mcontext equal MVALUE. + */ +#define CSR_TEXTRA_MSELECT_MASK (0x2000000UL) +#define CSR_TEXTRA_MSELECT_SHIFT (25U) +#define CSR_TEXTRA_MSELECT_SET(x) (((uint32_t)(x) << CSR_TEXTRA_MSELECT_SHIFT) & CSR_TEXTRA_MSELECT_MASK) +#define CSR_TEXTRA_MSELECT_GET(x) (((uint32_t)(x) & CSR_TEXTRA_MSELECT_MASK) >> CSR_TEXTRA_MSELECT_SHIFT) + +/* + * SVALUE (RW) + * + * Data used together with SSELECT. + */ +#define CSR_TEXTRA_SVALUE_MASK (0x7FCU) +#define CSR_TEXTRA_SVALUE_SHIFT (2U) +#define CSR_TEXTRA_SVALUE_SET(x) (((uint32_t)(x) << CSR_TEXTRA_SVALUE_SHIFT) & CSR_TEXTRA_SVALUE_MASK) +#define CSR_TEXTRA_SVALUE_GET(x) (((uint32_t)(x) & CSR_TEXTRA_SVALUE_MASK) >> CSR_TEXTRA_SVALUE_SHIFT) + +/* + * SSELECT (RW) + * + * 0:Ignore MVALUE + * 1:This trigger will only match if the lower bits of scontext equal SVALUE + * 2This trigger will only match if satp.ASID equals SVALUE. + */ +#define CSR_TEXTRA_SSELECT_MASK (0x3U) +#define CSR_TEXTRA_SSELECT_SHIFT (0U) +#define CSR_TEXTRA_SSELECT_SET(x) (((uint32_t)(x) << CSR_TEXTRA_SSELECT_SHIFT) & CSR_TEXTRA_SSELECT_MASK) +#define CSR_TEXTRA_SSELECT_GET(x) (((uint32_t)(x) & CSR_TEXTRA_SSELECT_MASK) >> CSR_TEXTRA_SSELECT_SHIFT) + +/* Bitfield definition for register: TINFO */ +/* + * INFO (RO) + * + * One bit for each possible type in tdata1. Bit N corresponds to type N. If the bit is set, then that + * type is supported by the currently selected trigger. If the currently selected trigger does not exist, this field contains 1. + * 0:When this bit is set, there is no trigger at this tselect + * 1:Reserved and hardwired to 0. + * 2：When this bit is set, the selected trigger supports type of address/data match trigger + * 3:When this bit is set, the selected trigger supports type of instruction count trigger. + * 4:When this bit is set, the selected trigger supports type of interrupt trigger + * 5:When this bit is set, the selected trigger supports type of exception trigger + * 15:When this bit is set, the selected trigger exists (so enumeration shouldn’t terminate), but is not currently available. + * Others:Reserved for future use. + */ +#define CSR_TINFO_INFO_MASK (0xFFFFU) +#define CSR_TINFO_INFO_SHIFT (0U) +#define CSR_TINFO_INFO_GET(x) (((uint32_t)(x) & CSR_TINFO_INFO_MASK) >> CSR_TINFO_INFO_SHIFT) + +/* Bitfield definition for register: TCONTROL */ +/* + * MPTE (RW) + * + * M-mode previous trigger enable field. When a trap into M-mode is taken, MPTE is set to the value of MTE. + */ +#define CSR_TCONTROL_MPTE_MASK (0x80U) +#define CSR_TCONTROL_MPTE_SHIFT (7U) +#define CSR_TCONTROL_MPTE_SET(x) (((uint32_t)(x) << CSR_TCONTROL_MPTE_SHIFT) & CSR_TCONTROL_MPTE_MASK) +#define CSR_TCONTROL_MPTE_GET(x) (((uint32_t)(x) & CSR_TCONTROL_MPTE_MASK) >> CSR_TCONTROL_MPTE_SHIFT) + +/* + * MTE (RW) + * + * M-mode trigger enable field. When a trap into M-mode is taken, MTE is set to 0. When the MRET instruction is executed, MTE is set to the value of MPTE. + * 0:Triggers do not match/fire while the hart is in M-mode. + * 1:Triggers do match/fire while the hart is in M-mode. + */ +#define CSR_TCONTROL_MTE_MASK (0x8U) +#define CSR_TCONTROL_MTE_SHIFT (3U) +#define CSR_TCONTROL_MTE_SET(x) (((uint32_t)(x) << CSR_TCONTROL_MTE_SHIFT) & CSR_TCONTROL_MTE_MASK) +#define CSR_TCONTROL_MTE_GET(x) (((uint32_t)(x) & CSR_TCONTROL_MTE_MASK) >> CSR_TCONTROL_MTE_SHIFT) + +/* Bitfield definition for register: MCONTEXT */ +/* + * MCONTEXT (RW) + * + * Machine mode software can write a context number to this register, which can be used to set triggers that only fire in that specific context. + */ +#define CSR_MCONTEXT_MCONTEXT_MASK (0x3FU) +#define CSR_MCONTEXT_MCONTEXT_SHIFT (0U) +#define CSR_MCONTEXT_MCONTEXT_SET(x) (((uint32_t)(x) << CSR_MCONTEXT_MCONTEXT_SHIFT) & CSR_MCONTEXT_MCONTEXT_MASK) +#define CSR_MCONTEXT_MCONTEXT_GET(x) (((uint32_t)(x) & CSR_MCONTEXT_MCONTEXT_MASK) >> CSR_MCONTEXT_MCONTEXT_SHIFT) + +/* Bitfield definition for register: SCONTEXT */ +/* + * SCONTEXT (RW) + * + * Machine mode software can write a context number to this register, which can be used to set triggers that only fire in that specific context. + */ +#define CSR_SCONTEXT_SCONTEXT_MASK (0x1FFU) +#define CSR_SCONTEXT_SCONTEXT_SHIFT (0U) +#define CSR_SCONTEXT_SCONTEXT_SET(x) (((uint32_t)(x) << CSR_SCONTEXT_SCONTEXT_SHIFT) & CSR_SCONTEXT_SCONTEXT_MASK) +#define CSR_SCONTEXT_SCONTEXT_GET(x) (((uint32_t)(x) & CSR_SCONTEXT_SCONTEXT_MASK) >> CSR_SCONTEXT_SCONTEXT_SHIFT) + +/* Bitfield definition for register: DCSR */ +/* + * XDEBUGVER (RO) + * + * Version of the external debugger. 0 indicates that no external debugger exists and 4 indicates that the external debugger conforms to the RISC-V External Debug Support (TD003) V0.13 + */ +#define CSR_DCSR_XDEBUGVER_MASK (0xF0000000UL) +#define CSR_DCSR_XDEBUGVER_SHIFT (28U) +#define CSR_DCSR_XDEBUGVER_GET(x) (((uint32_t)(x) & CSR_DCSR_XDEBUGVER_MASK) >> CSR_DCSR_XDEBUGVER_SHIFT) + +/* + * EBREAKM (RW) + * + * This bit controls the behavior of EBREAK instructions in Machine Mode + * 0:Generate a regular breakpoint exception + * 1:Enter Debug Mode + */ +#define CSR_DCSR_EBREAKM_MASK (0x8000U) +#define CSR_DCSR_EBREAKM_SHIFT (15U) +#define CSR_DCSR_EBREAKM_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKM_SHIFT) & CSR_DCSR_EBREAKM_MASK) +#define CSR_DCSR_EBREAKM_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKM_MASK) >> CSR_DCSR_EBREAKM_SHIFT) + +/* + * EBREAKU (RW) + * + * This bit controls the behavior of EBREAK instructions in User/Application Mode + * 0:Generate a regular breakpoint exception + * 1:Enter Debug Mode + */ +#define CSR_DCSR_EBREAKU_MASK (0x1000U) +#define CSR_DCSR_EBREAKU_SHIFT (12U) +#define CSR_DCSR_EBREAKU_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKU_SHIFT) & CSR_DCSR_EBREAKU_MASK) +#define CSR_DCSR_EBREAKU_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKU_MASK) >> CSR_DCSR_EBREAKU_SHIFT) + +/* + * STEPIE (RW) + * + * This bit controls whether interrupts are enabled during single stepping + * 0:Disable interrupts during single stepping + * 1:Allow interrupts in single stepping + */ +#define CSR_DCSR_STEPIE_MASK (0x800U) +#define CSR_DCSR_STEPIE_SHIFT (11U) +#define CSR_DCSR_STEPIE_SET(x) (((uint32_t)(x) << CSR_DCSR_STEPIE_SHIFT) & CSR_DCSR_STEPIE_MASK) +#define CSR_DCSR_STEPIE_GET(x) (((uint32_t)(x) & CSR_DCSR_STEPIE_MASK) >> CSR_DCSR_STEPIE_SHIFT) + +/* + * STOPCOUNT (RW) + * + * This bit controls whether performance counters are stopped in Debug Mode. + * 0:Do not stop counters in Debug Mode + * 1:Stop counters in Debug Mode + */ +#define CSR_DCSR_STOPCOUNT_MASK (0x400U) +#define CSR_DCSR_STOPCOUNT_SHIFT (10U) +#define CSR_DCSR_STOPCOUNT_SET(x) (((uint32_t)(x) << CSR_DCSR_STOPCOUNT_SHIFT) & CSR_DCSR_STOPCOUNT_MASK) +#define CSR_DCSR_STOPCOUNT_GET(x) (((uint32_t)(x) & CSR_DCSR_STOPCOUNT_MASK) >> CSR_DCSR_STOPCOUNT_SHIFT) + +/* + * STOPTIME (RW) + * + * This bit controls whether timers are stopped in Debug Mode. The processor only drives its stoptime output pin to 1 if it is in Debug Mode and this bit is set. Integration effort is required to make timers in the platform observe this pin to really stop them. + * 0:Do not stop timers in Debug Mode + * 1:Stop timers in Debug Mode + */ +#define CSR_DCSR_STOPTIME_MASK (0x200U) +#define CSR_DCSR_STOPTIME_SHIFT (9U) +#define CSR_DCSR_STOPTIME_SET(x) (((uint32_t)(x) << CSR_DCSR_STOPTIME_SHIFT) & CSR_DCSR_STOPTIME_MASK) +#define CSR_DCSR_STOPTIME_GET(x) (((uint32_t)(x) & CSR_DCSR_STOPTIME_MASK) >> CSR_DCSR_STOPTIME_SHIFT) + +/* + * CAUSE (RO) + * + * Reason why Debug Mode was entered. When there are multiple reasons to enter Debug Mode, the priority to determine the CAUSE value will be: trigger module > EBREAK > halt-on-reset > halt request > single step. Halt requests are requests issued by the external debugger + * 0:Reserved + * 1:EBREAK + * 2:Trigger module + * 3:Halt request + * 4:Single step + * 5:Halt-on-reset + * 6-7:Reserved + */ +#define CSR_DCSR_CAUSE_MASK (0x1C0U) +#define CSR_DCSR_CAUSE_SHIFT (6U) +#define CSR_DCSR_CAUSE_GET(x) (((uint32_t)(x) & CSR_DCSR_CAUSE_MASK) >> CSR_DCSR_CAUSE_SHIFT) + +/* + * MPRVEN (RW) + * + * This bit controls whether mstatus.MPRV takes effect in Debug Mode. + * 0:MPRV in mstatus is ignored in Debug Mode. + * 1:MPRV in mstatus takes effect in Debug Mode. + */ +#define CSR_DCSR_MPRVEN_MASK (0x10U) +#define CSR_DCSR_MPRVEN_SHIFT (4U) +#define CSR_DCSR_MPRVEN_SET(x) (((uint32_t)(x) << CSR_DCSR_MPRVEN_SHIFT) & CSR_DCSR_MPRVEN_MASK) +#define CSR_DCSR_MPRVEN_GET(x) (((uint32_t)(x) & CSR_DCSR_MPRVEN_MASK) >> CSR_DCSR_MPRVEN_SHIFT) + +/* + * NMIP (RO) + * + * When this bit is set, there is a Non-Maskable-Interrupt (NMI) pending for the hart. Since an NMI can indicate a hardware error condition, reliable debugging may no longer be possible once this bit becomes set. + */ +#define CSR_DCSR_NMIP_MASK (0x8U) +#define CSR_DCSR_NMIP_SHIFT (3U) +#define CSR_DCSR_NMIP_GET(x) (((uint32_t)(x) & CSR_DCSR_NMIP_MASK) >> CSR_DCSR_NMIP_SHIFT) + +/* + * STEP (RW) + * + * This bit controls whether non-Debug Mode instruction execution is in the single step mode. When set, the hart returns to Debug Mode after a single instruction execution. If the instruction does not complete due to an exception, the hart will immediately enter Debug Mode before executing the trap handler, with appropriate exception registers set. + * 0:Single Step Mode is off + * 1:Single Step Mode is on + */ +#define CSR_DCSR_STEP_MASK (0x4U) +#define CSR_DCSR_STEP_SHIFT (2U) +#define CSR_DCSR_STEP_SET(x) (((uint32_t)(x) << CSR_DCSR_STEP_SHIFT) & CSR_DCSR_STEP_MASK) +#define CSR_DCSR_STEP_GET(x) (((uint32_t)(x) & CSR_DCSR_STEP_MASK) >> CSR_DCSR_STEP_SHIFT) + +/* + * PRV (RW) + * + * The privilege level that the hart was operating in when Debug Mode was entered. The external debugger can modify this value to change the hart’s privilege level when exiting Debug Mode. + * 0:User/Application + * 1:Supervisor + * 2:Reserved + * 3:Machine + */ +#define CSR_DCSR_PRV_MASK (0x3U) +#define CSR_DCSR_PRV_SHIFT (0U) +#define CSR_DCSR_PRV_SET(x) (((uint32_t)(x) << CSR_DCSR_PRV_SHIFT) & CSR_DCSR_PRV_MASK) +#define CSR_DCSR_PRV_GET(x) (((uint32_t)(x) & CSR_DCSR_PRV_MASK) >> CSR_DCSR_PRV_SHIFT) + +/* Bitfield definition for register: DPC */ +/* + * DPC (RW) + * + * Debug Program Counter. Bit 0 is hardwired to 0. + */ +#define CSR_DPC_DPC_MASK (0xFFFFFFFFUL) +#define CSR_DPC_DPC_SHIFT (0U) +#define CSR_DPC_DPC_SET(x) (((uint32_t)(x) << CSR_DPC_DPC_SHIFT) & CSR_DPC_DPC_MASK) +#define CSR_DPC_DPC_GET(x) (((uint32_t)(x) & CSR_DPC_DPC_MASK) >> CSR_DPC_DPC_SHIFT) + +/* Bitfield definition for register: DSCRATCH0 */ +/* + * DSCRATCH (RO) + * + * A scratch register that is reserved for use by Debug Module. + */ +#define CSR_DSCRATCH0_DSCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_DSCRATCH0_DSCRATCH_SHIFT (0U) +#define CSR_DSCRATCH0_DSCRATCH_GET(x) (((uint32_t)(x) & CSR_DSCRATCH0_DSCRATCH_MASK) >> CSR_DSCRATCH0_DSCRATCH_SHIFT) + +/* Bitfield definition for register: DSCRATCH1 */ +/* + * DSCRATCH (RO) + * + * A scratch register that is reserved for use by Debug Module. + */ +#define CSR_DSCRATCH1_DSCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_DSCRATCH1_DSCRATCH_SHIFT (0U) +#define CSR_DSCRATCH1_DSCRATCH_GET(x) (((uint32_t)(x) & CSR_DSCRATCH1_DSCRATCH_MASK) >> CSR_DSCRATCH1_DSCRATCH_SHIFT) + +/* Bitfield definition for register: MCYCLE */ +/* + * COUNTER (RW) + * + * the lower 32 bits of Machine Cycle Counter + */ +#define CSR_MCYCLE_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MCYCLE_COUNTER_SHIFT (0U) +#define CSR_MCYCLE_COUNTER_SET(x) (((uint32_t)(x) << CSR_MCYCLE_COUNTER_SHIFT) & CSR_MCYCLE_COUNTER_MASK) +#define CSR_MCYCLE_COUNTER_GET(x) (((uint32_t)(x) & CSR_MCYCLE_COUNTER_MASK) >> CSR_MCYCLE_COUNTER_SHIFT) + +/* Bitfield definition for register: MINSTRET */ +/* + * COUNTER (RW) + * + * the lower 32 bits of Machine Instruction-Retired Counter + */ +#define CSR_MINSTRET_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MINSTRET_COUNTER_SHIFT (0U) +#define CSR_MINSTRET_COUNTER_SET(x) (((uint32_t)(x) << CSR_MINSTRET_COUNTER_SHIFT) & CSR_MINSTRET_COUNTER_MASK) +#define CSR_MINSTRET_COUNTER_GET(x) (((uint32_t)(x) & CSR_MINSTRET_COUNTER_MASK) >> CSR_MINSTRET_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER3 */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent3 + */ +#define CSR_MHPMCOUNTER3_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER3_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER3_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER3_COUNTER_SHIFT) & CSR_MHPMCOUNTER3_COUNTER_MASK) +#define CSR_MHPMCOUNTER3_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER3_COUNTER_MASK) >> CSR_MHPMCOUNTER3_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER4 */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent4 + */ +#define CSR_MHPMCOUNTER4_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER4_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER4_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER4_COUNTER_SHIFT) & CSR_MHPMCOUNTER4_COUNTER_MASK) +#define CSR_MHPMCOUNTER4_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER4_COUNTER_MASK) >> CSR_MHPMCOUNTER4_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER5 */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent5 + */ +#define CSR_MHPMCOUNTER5_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER5_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER5_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER5_COUNTER_SHIFT) & CSR_MHPMCOUNTER5_COUNTER_MASK) +#define CSR_MHPMCOUNTER5_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER5_COUNTER_MASK) >> CSR_MHPMCOUNTER5_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER6 */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent6 + */ +#define CSR_MHPMCOUNTER6_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER6_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER6_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER6_COUNTER_SHIFT) & CSR_MHPMCOUNTER6_COUNTER_MASK) +#define CSR_MHPMCOUNTER6_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER6_COUNTER_MASK) >> CSR_MHPMCOUNTER6_COUNTER_SHIFT) + +/* Bitfield definition for register: MCYCLEH */ +/* + * COUNTER (RW) + * + * the higher 32 bits of Machine Cycle Counter + */ +#define CSR_MCYCLEH_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MCYCLEH_COUNTER_SHIFT (0U) +#define CSR_MCYCLEH_COUNTER_SET(x) (((uint32_t)(x) << CSR_MCYCLEH_COUNTER_SHIFT) & CSR_MCYCLEH_COUNTER_MASK) +#define CSR_MCYCLEH_COUNTER_GET(x) (((uint32_t)(x) & CSR_MCYCLEH_COUNTER_MASK) >> CSR_MCYCLEH_COUNTER_SHIFT) + +/* Bitfield definition for register: MINSTRETH */ +/* + * COUNTER (RW) + * + * the higher 32 bits of Machine Instruction-Retired Counter + */ +#define CSR_MINSTRETH_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MINSTRETH_COUNTER_SHIFT (0U) +#define CSR_MINSTRETH_COUNTER_SET(x) (((uint32_t)(x) << CSR_MINSTRETH_COUNTER_SHIFT) & CSR_MINSTRETH_COUNTER_MASK) +#define CSR_MINSTRETH_COUNTER_GET(x) (((uint32_t)(x) & CSR_MINSTRETH_COUNTER_MASK) >> CSR_MINSTRETH_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER3H */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent3 + */ +#define CSR_MHPMCOUNTER3H_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER3H_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER3H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER3H_COUNTER_SHIFT) & CSR_MHPMCOUNTER3H_COUNTER_MASK) +#define CSR_MHPMCOUNTER3H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER3H_COUNTER_MASK) >> CSR_MHPMCOUNTER3H_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER4H */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent4 + */ +#define CSR_MHPMCOUNTER4H_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER4H_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER4H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER4H_COUNTER_SHIFT) & CSR_MHPMCOUNTER4H_COUNTER_MASK) +#define CSR_MHPMCOUNTER4H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER4H_COUNTER_MASK) >> CSR_MHPMCOUNTER4H_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER5H */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent5 + */ +#define CSR_MHPMCOUNTER5H_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER5H_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER5H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER5H_COUNTER_SHIFT) & CSR_MHPMCOUNTER5H_COUNTER_MASK) +#define CSR_MHPMCOUNTER5H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER5H_COUNTER_MASK) >> CSR_MHPMCOUNTER5H_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER6H */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent6 + */ +#define CSR_MHPMCOUNTER6H_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER6H_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER6H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER6H_COUNTER_SHIFT) & CSR_MHPMCOUNTER6H_COUNTER_MASK) +#define CSR_MHPMCOUNTER6H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER6H_COUNTER_MASK) >> CSR_MHPMCOUNTER6H_COUNTER_SHIFT) + +/* Bitfield definition for register: CYCLE */ +/* + * CYCLE (RW) + * + * Cycle Counter + */ +#define CSR_CYCLE_CYCLE_MASK (0xFFFFFFFFUL) +#define CSR_CYCLE_CYCLE_SHIFT (0U) +#define CSR_CYCLE_CYCLE_SET(x) (((uint32_t)(x) << CSR_CYCLE_CYCLE_SHIFT) & CSR_CYCLE_CYCLE_MASK) +#define CSR_CYCLE_CYCLE_GET(x) (((uint32_t)(x) & CSR_CYCLE_CYCLE_MASK) >> CSR_CYCLE_CYCLE_SHIFT) + +/* Bitfield definition for register: CYCLEH */ +/* + * CYCLEH (RW) + * + * Cycle Counter Higher 32-bit + */ +#define CSR_CYCLEH_CYCLEH_MASK (0xFFFFFFFFUL) +#define CSR_CYCLEH_CYCLEH_SHIFT (0U) +#define CSR_CYCLEH_CYCLEH_SET(x) (((uint32_t)(x) << CSR_CYCLEH_CYCLEH_SHIFT) & CSR_CYCLEH_CYCLEH_MASK) +#define CSR_CYCLEH_CYCLEH_GET(x) (((uint32_t)(x) & CSR_CYCLEH_CYCLEH_MASK) >> CSR_CYCLEH_CYCLEH_SHIFT) + +/* Bitfield definition for register: MVENDORID */ +/* + * MVENDORID (RO) + * + * The manufacturer ID + */ +#define CSR_MVENDORID_MVENDORID_MASK (0xFFFFFFFFUL) +#define CSR_MVENDORID_MVENDORID_SHIFT (0U) +#define CSR_MVENDORID_MVENDORID_GET(x) (((uint32_t)(x) & CSR_MVENDORID_MVENDORID_MASK) >> CSR_MVENDORID_MVENDORID_SHIFT) + +/* Bitfield definition for register: MARCHID */ +/* + * CPU_ID (RO) + * + * CPU ID + */ +#define CSR_MARCHID_CPU_ID_MASK (0x7FFFFFFFUL) +#define CSR_MARCHID_CPU_ID_SHIFT (0U) +#define CSR_MARCHID_CPU_ID_GET(x) (((uint32_t)(x) & CSR_MARCHID_CPU_ID_MASK) >> CSR_MARCHID_CPU_ID_SHIFT) + +/* Bitfield definition for register: MIMPID */ +/* + * MAJOR (RO) + * + * Revision major + */ +#define CSR_MIMPID_MAJOR_MASK (0xFFFFFF00UL) +#define CSR_MIMPID_MAJOR_SHIFT (8U) +#define CSR_MIMPID_MAJOR_GET(x) (((uint32_t)(x) & CSR_MIMPID_MAJOR_MASK) >> CSR_MIMPID_MAJOR_SHIFT) + +/* + * MINOR (RO) + * + * Revision minor + */ +#define CSR_MIMPID_MINOR_MASK (0xF0U) +#define CSR_MIMPID_MINOR_SHIFT (4U) +#define CSR_MIMPID_MINOR_GET(x) (((uint32_t)(x) & CSR_MIMPID_MINOR_MASK) >> CSR_MIMPID_MINOR_SHIFT) + +/* + * EXTENSION (RO) + * + * Revision extension + */ +#define CSR_MIMPID_EXTENSION_MASK (0xFU) +#define CSR_MIMPID_EXTENSION_SHIFT (0U) +#define CSR_MIMPID_EXTENSION_GET(x) (((uint32_t)(x) & CSR_MIMPID_EXTENSION_MASK) >> CSR_MIMPID_EXTENSION_SHIFT) + +/* Bitfield definition for register: MHARTID */ +/* + * MHARTID (RO) + * + * Hart ID + */ +#define CSR_MHARTID_MHARTID_MASK (0xFFFFFFFFUL) +#define CSR_MHARTID_MHARTID_SHIFT (0U) +#define CSR_MHARTID_MHARTID_GET(x) (((uint32_t)(x) & CSR_MHARTID_MHARTID_MASK) >> CSR_MHARTID_MHARTID_SHIFT) + +/* NON-STANDARD CRS register bitfiled definitions */ + +/* Bitfield definition for register: MCOUNTINHIBIT */ +/* + * HPM6 (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_HPM6_MASK (0x40U) +#define CSR_MCOUNTINHIBIT_HPM6_SHIFT (6U) +#define CSR_MCOUNTINHIBIT_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM6_SHIFT) & CSR_MCOUNTINHIBIT_HPM6_MASK) +#define CSR_MCOUNTINHIBIT_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM6_MASK) >> CSR_MCOUNTINHIBIT_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_HPM5_MASK (0x20U) +#define CSR_MCOUNTINHIBIT_HPM5_SHIFT (5U) +#define CSR_MCOUNTINHIBIT_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM5_SHIFT) & CSR_MCOUNTINHIBIT_HPM5_MASK) +#define CSR_MCOUNTINHIBIT_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM5_MASK) >> CSR_MCOUNTINHIBIT_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_HPM4_MASK (0x10U) +#define CSR_MCOUNTINHIBIT_HPM4_SHIFT (4U) +#define CSR_MCOUNTINHIBIT_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM4_SHIFT) & CSR_MCOUNTINHIBIT_HPM4_MASK) +#define CSR_MCOUNTINHIBIT_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM4_MASK) >> CSR_MCOUNTINHIBIT_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_HPM3_MASK (0x8U) +#define CSR_MCOUNTINHIBIT_HPM3_SHIFT (3U) +#define CSR_MCOUNTINHIBIT_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM3_SHIFT) & CSR_MCOUNTINHIBIT_HPM3_MASK) +#define CSR_MCOUNTINHIBIT_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM3_MASK) >> CSR_MCOUNTINHIBIT_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_IR_MASK (0x4U) +#define CSR_MCOUNTINHIBIT_IR_SHIFT (2U) +#define CSR_MCOUNTINHIBIT_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_IR_SHIFT) & CSR_MCOUNTINHIBIT_IR_MASK) +#define CSR_MCOUNTINHIBIT_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_IR_MASK) >> CSR_MCOUNTINHIBIT_IR_SHIFT) + +/* + * TM (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_TM_MASK (0x2U) +#define CSR_MCOUNTINHIBIT_TM_SHIFT (1U) +#define CSR_MCOUNTINHIBIT_TM_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_TM_SHIFT) & CSR_MCOUNTINHIBIT_TM_MASK) +#define CSR_MCOUNTINHIBIT_TM_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_TM_MASK) >> CSR_MCOUNTINHIBIT_TM_SHIFT) + +/* + * CY (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_CY_MASK (0x1U) +#define CSR_MCOUNTINHIBIT_CY_SHIFT (0U) +#define CSR_MCOUNTINHIBIT_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_CY_SHIFT) & CSR_MCOUNTINHIBIT_CY_MASK) +#define CSR_MCOUNTINHIBIT_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_CY_MASK) >> CSR_MCOUNTINHIBIT_CY_SHIFT) + +/* Bitfield definition for register: MILMB */ +/* + * IBPA (RO) + * + * The base physical address of ILM. It has to be an integer multiple of the ILM size + */ +#define CSR_MILMB_IBPA_MASK (0xFFFFFC00UL) +#define CSR_MILMB_IBPA_SHIFT (10U) +#define CSR_MILMB_IBPA_GET(x) (((uint32_t)(x) & CSR_MILMB_IBPA_MASK) >> CSR_MILMB_IBPA_SHIFT) + +/* + * RWECC (RW) + * + * Controls diagnostic accesses of ECC codes of the ILM RAMs. When set, load/store to ILM reads/writes ECC codes to the mecc_code register. This bit can be set for injecting ECC errors to test the ECC handler. + * 0:Disable diagnostic accesses of ECC codes + * 1:Enable diagnostic accesses of ECC codes + */ +#define CSR_MILMB_RWECC_MASK (0x8U) +#define CSR_MILMB_RWECC_SHIFT (3U) +#define CSR_MILMB_RWECC_SET(x) (((uint32_t)(x) << CSR_MILMB_RWECC_SHIFT) & CSR_MILMB_RWECC_MASK) +#define CSR_MILMB_RWECC_GET(x) (((uint32_t)(x) & CSR_MILMB_RWECC_MASK) >> CSR_MILMB_RWECC_SHIFT) + +/* + * ECCEN (RW) + * + * Parity/ECC enable control: + * 0:Disable parity/ECC + * 1:Reserved + * 2:Generate exceptions only on uncorrectable parity/ECC errors + * 3:Generate exceptions on any type of parity/ECC errors + */ +#define CSR_MILMB_ECCEN_MASK (0x6U) +#define CSR_MILMB_ECCEN_SHIFT (1U) +#define CSR_MILMB_ECCEN_SET(x) (((uint32_t)(x) << CSR_MILMB_ECCEN_SHIFT) & CSR_MILMB_ECCEN_MASK) +#define CSR_MILMB_ECCEN_GET(x) (((uint32_t)(x) & CSR_MILMB_ECCEN_MASK) >> CSR_MILMB_ECCEN_SHIFT) + +/* + * IEN (RO) + * + * ILM enable control: + * 0:ILM is disabled + * 1:ILM is enabled + */ +#define CSR_MILMB_IEN_MASK (0x1U) +#define CSR_MILMB_IEN_SHIFT (0U) +#define CSR_MILMB_IEN_GET(x) (((uint32_t)(x) & CSR_MILMB_IEN_MASK) >> CSR_MILMB_IEN_SHIFT) + +/* Bitfield definition for register: MDLMB */ +/* + * DBPA (RO) + * + * The base physical address of DLM. It has to be an integer multiple of the DLM size + */ +#define CSR_MDLMB_DBPA_MASK (0xFFFFFC00UL) +#define CSR_MDLMB_DBPA_SHIFT (10U) +#define CSR_MDLMB_DBPA_GET(x) (((uint32_t)(x) & CSR_MDLMB_DBPA_MASK) >> CSR_MDLMB_DBPA_SHIFT) + +/* + * RWECC (RW) + * + * Controls diagnostic accesses of ECC codes of the DLM RAMs. When set, load/store to DLM reads/writes ECC codes to the mecc_code register. This bit can be set for injecting ECC errors to test the ECC handler. + * 0:Disable diagnostic accesses of ECC codes + * 1:Enable diagnostic accesses of ECC codes + */ +#define CSR_MDLMB_RWECC_MASK (0x8U) +#define CSR_MDLMB_RWECC_SHIFT (3U) +#define CSR_MDLMB_RWECC_SET(x) (((uint32_t)(x) << CSR_MDLMB_RWECC_SHIFT) & CSR_MDLMB_RWECC_MASK) +#define CSR_MDLMB_RWECC_GET(x) (((uint32_t)(x) & CSR_MDLMB_RWECC_MASK) >> CSR_MDLMB_RWECC_SHIFT) + +/* + * ECCEN (RW) + * + * Parity/ECC enable control: + * 0:Disable parity/ECC + * 1:Reserved + * 2:Generate exceptions only on uncorrectable parity/ECC errors + * 3:Generate exceptions on any type of parity/ECC errors + */ +#define CSR_MDLMB_ECCEN_MASK (0x6U) +#define CSR_MDLMB_ECCEN_SHIFT (1U) +#define CSR_MDLMB_ECCEN_SET(x) (((uint32_t)(x) << CSR_MDLMB_ECCEN_SHIFT) & CSR_MDLMB_ECCEN_MASK) +#define CSR_MDLMB_ECCEN_GET(x) (((uint32_t)(x) & CSR_MDLMB_ECCEN_MASK) >> CSR_MDLMB_ECCEN_SHIFT) + +/* + * DEN (RO) + * + * DLM enable control: + * 0:DLM is disabled + * 1:DLM is enabled + */ +#define CSR_MDLMB_DEN_MASK (0x1U) +#define CSR_MDLMB_DEN_SHIFT (0U) +#define CSR_MDLMB_DEN_GET(x) (((uint32_t)(x) & CSR_MDLMB_DEN_MASK) >> CSR_MDLMB_DEN_SHIFT) + +/* Bitfield definition for register: MECC_CODE */ +/* + * INSN (RO) + * + * Indicates if the parity/ECC error is caused by instruction fetch or data access. + * 0:Data access + * 1:Instruction fetch + */ +#define CSR_MECC_CODE_INSN_MASK (0x400000UL) +#define CSR_MECC_CODE_INSN_SHIFT (22U) +#define CSR_MECC_CODE_INSN_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_INSN_MASK) >> CSR_MECC_CODE_INSN_SHIFT) + +/* + * RAMID (RO) + * + * The ID of RAM that caused parity/ECC errors. + * This bit is updated on parity/ECC error exceptions. + * 0–1:Reserved + * 2:Tag RAM of I-Cache + * 3:Data RAM of I-Cache + * 4:Tag RAM of D-Cache + * 5:Data RAM of D-Cache + * 6:Tag RAM of TLB + * 7:Data RAM of TLB + * 8:ILM + * 9:DLM + * 10–15:Reserved + */ +#define CSR_MECC_CODE_RAMID_MASK (0x3C0000UL) +#define CSR_MECC_CODE_RAMID_SHIFT (18U) +#define CSR_MECC_CODE_RAMID_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_RAMID_MASK) >> CSR_MECC_CODE_RAMID_SHIFT) + +/* + * P (RO) + * + * Precise error. This bit is updated on parity/ECC error exceptions. + * 0:Imprecise error + * 1:Precise error + */ +#define CSR_MECC_CODE_P_MASK (0x20000UL) +#define CSR_MECC_CODE_P_SHIFT (17U) +#define CSR_MECC_CODE_P_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_P_MASK) >> CSR_MECC_CODE_P_SHIFT) + +/* + * C (RO) + * + * Correctable error. This bit is updated on parity/ECC error exceptions. + * 0:Uncorrectable error + * 1:Correctable error + */ +#define CSR_MECC_CODE_C_MASK (0x10000UL) +#define CSR_MECC_CODE_C_SHIFT (16U) +#define CSR_MECC_CODE_C_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_C_MASK) >> CSR_MECC_CODE_C_SHIFT) + +/* + * CODE (RW) + * + * This field records the ECC value on ECC error exceptions. This field is also used to read/write the ECC codes when diagnostic access of ECC codes are enabled (milmb.RWECC or mdlmb.RWECC is 1). + */ +#define CSR_MECC_CODE_CODE_MASK (0x7FU) +#define CSR_MECC_CODE_CODE_SHIFT (0U) +#define CSR_MECC_CODE_CODE_SET(x) (((uint32_t)(x) << CSR_MECC_CODE_CODE_SHIFT) & CSR_MECC_CODE_CODE_MASK) +#define CSR_MECC_CODE_CODE_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_CODE_MASK) >> CSR_MECC_CODE_CODE_SHIFT) + +/* Bitfield definition for register: MNVEC */ +/* + * MNVEC (RO) + * + * Base address of the NMI handler. Its value is the zero-extended value of the reset_vector. + */ +#define CSR_MNVEC_MNVEC_MASK (0xFFFFFFFFUL) +#define CSR_MNVEC_MNVEC_SHIFT (0U) +#define CSR_MNVEC_MNVEC_GET(x) (((uint32_t)(x) & CSR_MNVEC_MNVEC_MASK) >> CSR_MNVEC_MNVEC_SHIFT) + +/* Bitfield definition for register: MXSTATUS */ +/* + * PDME (RW) + * + * For saving previous DME state on entering a trap. This field is hardwired to 0 if data cache and data local memory are not supported. + */ +#define CSR_MXSTATUS_PDME_MASK (0x20U) +#define CSR_MXSTATUS_PDME_SHIFT (5U) +#define CSR_MXSTATUS_PDME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PDME_SHIFT) & CSR_MXSTATUS_PDME_MASK) +#define CSR_MXSTATUS_PDME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PDME_MASK) >> CSR_MXSTATUS_PDME_SHIFT) + +/* + * DME (RW) + * + * Data Machine Error flag. It indicates an exception occurred at the data cache or data local memory (DLM). Load/store accesses will bypass D-Cache when this bit is set. The exception handler should clear this bit after the machine error has been dealt with. + */ +#define CSR_MXSTATUS_DME_MASK (0x10U) +#define CSR_MXSTATUS_DME_SHIFT (4U) +#define CSR_MXSTATUS_DME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_DME_SHIFT) & CSR_MXSTATUS_DME_MASK) +#define CSR_MXSTATUS_DME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_DME_MASK) >> CSR_MXSTATUS_DME_SHIFT) + +/* + * PIME (RW) + * + * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding + * is defined as follows: + * 0: User mode + * 1: Supervisor mode + * 2: Reserved + * 3: Machine mode + */ +#define CSR_MXSTATUS_PIME_MASK (0x8U) +#define CSR_MXSTATUS_PIME_SHIFT (3U) +#define CSR_MXSTATUS_PIME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PIME_SHIFT) & CSR_MXSTATUS_PIME_MASK) +#define CSR_MXSTATUS_PIME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PIME_MASK) >> CSR_MXSTATUS_PIME_SHIFT) + +/* + * IME (RW) + * + * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding + * is defined as follows: + * 0: User mode + * 1: Supervisor mode + * 2: Reserved + * 3: Machine mode + */ +#define CSR_MXSTATUS_IME_MASK (0x4U) +#define CSR_MXSTATUS_IME_SHIFT (2U) +#define CSR_MXSTATUS_IME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_IME_SHIFT) & CSR_MXSTATUS_IME_MASK) +#define CSR_MXSTATUS_IME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_IME_MASK) >> CSR_MXSTATUS_IME_SHIFT) + +/* + * PPFT_EN (RW) + * + * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding + * is defined as follows: + * 0: User mode + * 1: Supervisor mode + * 2: Reserved + * 3: Machine mode + */ +#define CSR_MXSTATUS_PPFT_EN_MASK (0x2U) +#define CSR_MXSTATUS_PPFT_EN_SHIFT (1U) +#define CSR_MXSTATUS_PPFT_EN_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PPFT_EN_SHIFT) & CSR_MXSTATUS_PPFT_EN_MASK) +#define CSR_MXSTATUS_PPFT_EN_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PPFT_EN_MASK) >> CSR_MXSTATUS_PPFT_EN_SHIFT) + +/* + * PFT_EN (RW) + * + * Enable performance throttling. When throttling is enabled, the processor executes instructions at the performance level specified in mpft_ctl.T_LEVEL. On entering a trap: + * PPFT_EN <= PFT_EN; + * PFT_EN <= mpft_ctl.FAST_INT ? 0 :PFT_EN; + * On executing an MRET instruction: + * PFT_EN <= PPFT_EN; + * This field is hardwired to 0 if the PowerBrake feature is not supported. + */ +#define CSR_MXSTATUS_PFT_EN_MASK (0x1U) +#define CSR_MXSTATUS_PFT_EN_SHIFT (0U) +#define CSR_MXSTATUS_PFT_EN_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PFT_EN_SHIFT) & CSR_MXSTATUS_PFT_EN_MASK) +#define CSR_MXSTATUS_PFT_EN_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PFT_EN_MASK) >> CSR_MXSTATUS_PFT_EN_SHIFT) + +/* Bitfield definition for register: MPFT_CTL */ +/* + * FAST_INT (RW) + * + * Fast interrupt response. If this field is set, mxstatus.PFT_EN will be automatically cleared when the processor enters an interrupt handler. + */ +#define CSR_MPFT_CTL_FAST_INT_MASK (0x100U) +#define CSR_MPFT_CTL_FAST_INT_SHIFT (8U) +#define CSR_MPFT_CTL_FAST_INT_SET(x) (((uint32_t)(x) << CSR_MPFT_CTL_FAST_INT_SHIFT) & CSR_MPFT_CTL_FAST_INT_MASK) +#define CSR_MPFT_CTL_FAST_INT_GET(x) (((uint32_t)(x) & CSR_MPFT_CTL_FAST_INT_MASK) >> CSR_MPFT_CTL_FAST_INT_SHIFT) + +/* + * T_LEVEL (RW) + * + * Throttling Level. The processor has the highest performance at throttling level 0 and the lowest + * performance at throttling level 15. + * 0:Level 0 (the highest performance) + * 1-14:Level 1-14 + * 15:Level 15 (the lowest performance) + */ +#define CSR_MPFT_CTL_T_LEVEL_MASK (0xF0U) +#define CSR_MPFT_CTL_T_LEVEL_SHIFT (4U) +#define CSR_MPFT_CTL_T_LEVEL_SET(x) (((uint32_t)(x) << CSR_MPFT_CTL_T_LEVEL_SHIFT) & CSR_MPFT_CTL_T_LEVEL_MASK) +#define CSR_MPFT_CTL_T_LEVEL_GET(x) (((uint32_t)(x) & CSR_MPFT_CTL_T_LEVEL_MASK) >> CSR_MPFT_CTL_T_LEVEL_SHIFT) + +/* Bitfield definition for register: MHSP_CTL */ +/* + * M (RW) + * + * Enables the SP protection and recording mechanism in Machine mode + * 0:The mechanism is disabled in Machine mode. + * 1: The mechanism is enabled in Machine mode. + */ +#define CSR_MHSP_CTL_M_MASK (0x20U) +#define CSR_MHSP_CTL_M_SHIFT (5U) +#define CSR_MHSP_CTL_M_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_M_SHIFT) & CSR_MHSP_CTL_M_MASK) +#define CSR_MHSP_CTL_M_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_M_MASK) >> CSR_MHSP_CTL_M_SHIFT) + +/* + * S (RW) + * + * Enables the SP protection and recording mechanism in Supervisor mode + * 0:The mechanism is disabled in Supervisor mode + * 1:The mechanism is enabled in Supervisor mode + */ +#define CSR_MHSP_CTL_S_MASK (0x10U) +#define CSR_MHSP_CTL_S_SHIFT (4U) +#define CSR_MHSP_CTL_S_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_S_SHIFT) & CSR_MHSP_CTL_S_MASK) +#define CSR_MHSP_CTL_S_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_S_MASK) >> CSR_MHSP_CTL_S_SHIFT) + +/* + * U (RW) + * + * Enables the SP protection and recording mechanism in User mode + * 0:The mechanism is disabled in User mode + * 1:The mechanism is enabled in User mode. + */ +#define CSR_MHSP_CTL_U_MASK (0x8U) +#define CSR_MHSP_CTL_U_SHIFT (3U) +#define CSR_MHSP_CTL_U_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_U_SHIFT) & CSR_MHSP_CTL_U_MASK) +#define CSR_MHSP_CTL_U_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_U_MASK) >> CSR_MHSP_CTL_U_SHIFT) + +/* + * SCHM (RW) + * + * Selects the operating scheme of the stack protection and recording mechanism + * 0:Stack overflow/underflow detection + * 1:Top-of-stack recording + */ +#define CSR_MHSP_CTL_SCHM_MASK (0x4U) +#define CSR_MHSP_CTL_SCHM_SHIFT (2U) +#define CSR_MHSP_CTL_SCHM_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_SCHM_SHIFT) & CSR_MHSP_CTL_SCHM_MASK) +#define CSR_MHSP_CTL_SCHM_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_SCHM_MASK) >> CSR_MHSP_CTL_SCHM_SHIFT) + +/* + * UDF_EN (RW) + * + * Enable bit for the stack underflow protection mechanism. This bit will be cleared to 0 automatically by hardware when a stack protection (overflow or underflow) exception is taken. + * 0:The stack underflow protection is disabled + * 1:The stack underflow protection is enabled. + */ +#define CSR_MHSP_CTL_UDF_EN_MASK (0x2U) +#define CSR_MHSP_CTL_UDF_EN_SHIFT (1U) +#define CSR_MHSP_CTL_UDF_EN_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_UDF_EN_SHIFT) & CSR_MHSP_CTL_UDF_EN_MASK) +#define CSR_MHSP_CTL_UDF_EN_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_UDF_EN_MASK) >> CSR_MHSP_CTL_UDF_EN_SHIFT) + +/* + * OVF_EN (RW) + * + * Enable bit for the stack overflow protection and recording mechanism. This bit will be cleared to 0 automatically by hardware when a stack protection (overflow or underflow) exception is taken. + * 0:The stack overflow protection and recording mechanism are disabled. + * 1:The stack overflow protection and recording mechanism are enabled. + */ +#define CSR_MHSP_CTL_OVF_EN_MASK (0x1U) +#define CSR_MHSP_CTL_OVF_EN_SHIFT (0U) +#define CSR_MHSP_CTL_OVF_EN_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_OVF_EN_SHIFT) & CSR_MHSP_CTL_OVF_EN_MASK) +#define CSR_MHSP_CTL_OVF_EN_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_OVF_EN_MASK) >> CSR_MHSP_CTL_OVF_EN_SHIFT) + +/* Bitfield definition for register: MSP_BOUND */ +/* + * MSP_BOUND (RW) + * + * Machine SP Bound + */ +#define CSR_MSP_BOUND_MSP_BOUND_MASK (0xFFFFFFFFUL) +#define CSR_MSP_BOUND_MSP_BOUND_SHIFT (0U) +#define CSR_MSP_BOUND_MSP_BOUND_SET(x) (((uint32_t)(x) << CSR_MSP_BOUND_MSP_BOUND_SHIFT) & CSR_MSP_BOUND_MSP_BOUND_MASK) +#define CSR_MSP_BOUND_MSP_BOUND_GET(x) (((uint32_t)(x) & CSR_MSP_BOUND_MSP_BOUND_MASK) >> CSR_MSP_BOUND_MSP_BOUND_SHIFT) + +/* Bitfield definition for register: MSP_BASE */ +/* + * SP_BASE (RW) + * + * Machine SP base + */ +#define CSR_MSP_BASE_SP_BASE_MASK (0xFFFFFFFFUL) +#define CSR_MSP_BASE_SP_BASE_SHIFT (0U) +#define CSR_MSP_BASE_SP_BASE_SET(x) (((uint32_t)(x) << CSR_MSP_BASE_SP_BASE_SHIFT) & CSR_MSP_BASE_SP_BASE_MASK) +#define CSR_MSP_BASE_SP_BASE_GET(x) (((uint32_t)(x) & CSR_MSP_BASE_SP_BASE_MASK) >> CSR_MSP_BASE_SP_BASE_SHIFT) + +/* Bitfield definition for register: MDCAUSE */ +/* + * MDCAUSE (RW) + * + * This register further disambiguates causes of traps recorded in the mcause register. + * The value of MDCAUSE for precise exception: + * When mcause == 1 (Instruction access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP instruction access violation; 3:Bus error; 4:PMA empty hole access + * When mcause == 2 (Illegal instruction): + * 0:Please parse the mtval CSR; 1:FP disabled exception; 2:ACE disabled exception + * When mcause == 5 (Load access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception + * When mcause == 7 (Store access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception + * The value of MDCAUSE for imprecise exception: + * When mcause == Local Interrupt 16 or Local Interrupt 272 (16 + 256) (ECC error local interrupt) + * 0:Reserved; 1:LM slave port ECC/Parity error; 2:Imprecise store ECC/Parity error; 3:Imprecise load ECC/Parity error + * When mcause == Local Interrupt 17 or Local Interrupt 273 (17 + 256) (Bus read/write transaction error local interrupt) + * 0:Reserved; 1:Bus read error; 2:Bus write error; 3:PMP error caused by load instructions; 4:PMP error caused by store instructions; 5:PMA error caused by load instructions; 6:PMA error caused by store instructions + */ +#define CSR_MDCAUSE_MDCAUSE_MASK (0x7U) +#define CSR_MDCAUSE_MDCAUSE_SHIFT (0U) +#define CSR_MDCAUSE_MDCAUSE_SET(x) (((uint32_t)(x) << CSR_MDCAUSE_MDCAUSE_SHIFT) & CSR_MDCAUSE_MDCAUSE_MASK) +#define CSR_MDCAUSE_MDCAUSE_GET(x) (((uint32_t)(x) & CSR_MDCAUSE_MDCAUSE_MASK) >> CSR_MDCAUSE_MDCAUSE_SHIFT) + +/* Bitfield definition for register: MCACHE_CTL */ +/* + * IC_FIRST_WORD (RO) + * + * Cache miss allocation filling policy + * 0:Cache line data is returned critical (double) word first + * 1:Cache line data is returned the lowest address (double) word first + */ +#define CSR_MCACHE_CTL_IC_FIRST_WORD_MASK (0x800U) +#define CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT (11U) +#define CSR_MCACHE_CTL_IC_FIRST_WORD_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_FIRST_WORD_MASK) >> CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT) + +/* + * CCTL_SUEN (RW) + * + * Enable bit for Superuser-mode and User-mode software to access ucctlbeginaddr and ucctlcommand CSRs + * 0:Disable ucctlbeginaddr and ucctlcommand accesses in S/U mode + * 1:Enable ucctlbeginaddr and ucctlcommand accesses in S/U mode + */ +#define CSR_MCACHE_CTL_CCTL_SUEN_MASK (0x100U) +#define CSR_MCACHE_CTL_CCTL_SUEN_SHIFT (8U) +#define CSR_MCACHE_CTL_CCTL_SUEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_CCTL_SUEN_SHIFT) & CSR_MCACHE_CTL_CCTL_SUEN_MASK) +#define CSR_MCACHE_CTL_CCTL_SUEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_CCTL_SUEN_MASK) >> CSR_MCACHE_CTL_CCTL_SUEN_SHIFT) + +/* + * DC_RWECC (RW) + * + * Controls diagnostic accesses of ECC codes of the data cache RAMs. It is set to enable CCTL operations to access the ECC codes. This bit can be set for injecting ECC errors to test the ECC handler + * 0:Disable diagnostic accesses of ECC codes + * 1:Enable diagnostic accesses of ECC codes + */ +#define CSR_MCACHE_CTL_DC_RWECC_MASK (0x80U) +#define CSR_MCACHE_CTL_DC_RWECC_SHIFT (7U) +#define CSR_MCACHE_CTL_DC_RWECC_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_RWECC_SHIFT) & CSR_MCACHE_CTL_DC_RWECC_MASK) +#define CSR_MCACHE_CTL_DC_RWECC_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_RWECC_MASK) >> CSR_MCACHE_CTL_DC_RWECC_SHIFT) + +/* + * IC_RWECC (RW) + * + * Controls diagnostic accesses of ECC codes of the instruction cache RAMs. It is set to enable CCTL operations to access the ECC codes . This bit can be set for injecting ECC errors to test the ECC handler. + * 0:Disable diagnostic accesses of ECC codes + * 1:Enable diagnostic accesses of ECC codes + */ +#define CSR_MCACHE_CTL_IC_RWECC_MASK (0x40U) +#define CSR_MCACHE_CTL_IC_RWECC_SHIFT (6U) +#define CSR_MCACHE_CTL_IC_RWECC_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_RWECC_SHIFT) & CSR_MCACHE_CTL_IC_RWECC_MASK) +#define CSR_MCACHE_CTL_IC_RWECC_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_RWECC_MASK) >> CSR_MCACHE_CTL_IC_RWECC_SHIFT) + +/* + * DC_ECCEN (RW) + * + * Parity/ECC error checking enable control for the + * data cache. + * 0:Disable parity/ECC + * 1:Reserved + * 2:Generate exceptions only on uncorrectable parity/ECC errors + * 3:Generate exceptions on any type of parity/ECC errors + */ +#define CSR_MCACHE_CTL_DC_ECCEN_MASK (0x30U) +#define CSR_MCACHE_CTL_DC_ECCEN_SHIFT (4U) +#define CSR_MCACHE_CTL_DC_ECCEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_ECCEN_SHIFT) & CSR_MCACHE_CTL_DC_ECCEN_MASK) +#define CSR_MCACHE_CTL_DC_ECCEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_ECCEN_MASK) >> CSR_MCACHE_CTL_DC_ECCEN_SHIFT) + +/* + * IC_ECCEN (RW) + * + * Parity/ECC error checking enable control for the + * instruction cache + * 0:Disable parity/ECC + * 1:Reserved + * 2:Generate exceptions only on uncorrectable parity/ECC errors + * 3:Generate exceptions on any type of parity/ECC errors + */ +#define CSR_MCACHE_CTL_IC_ECCEN_MASK (0xCU) +#define CSR_MCACHE_CTL_IC_ECCEN_SHIFT (2U) +#define CSR_MCACHE_CTL_IC_ECCEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_ECCEN_SHIFT) & CSR_MCACHE_CTL_IC_ECCEN_MASK) +#define CSR_MCACHE_CTL_IC_ECCEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_ECCEN_MASK) >> CSR_MCACHE_CTL_IC_ECCEN_SHIFT) + +/* + * DC_EN (RW) + * + * Controls if the data cache is enabled or not. + * 0:D-Cache is disabled + * 1:D-Cache is enabled + */ +#define CSR_MCACHE_CTL_DC_EN_MASK (0x2U) +#define CSR_MCACHE_CTL_DC_EN_SHIFT (1U) +#define CSR_MCACHE_CTL_DC_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_EN_SHIFT) & CSR_MCACHE_CTL_DC_EN_MASK) +#define CSR_MCACHE_CTL_DC_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_EN_MASK) >> CSR_MCACHE_CTL_DC_EN_SHIFT) + +/* + * IC_EN (RW) + * + * Controls if the instruction cache is enabled or not. + * 0:I-Cache is disabled + * 1:I-Cache is enabled + */ +#define CSR_MCACHE_CTL_IC_EN_MASK (0x1U) +#define CSR_MCACHE_CTL_IC_EN_SHIFT (0U) +#define CSR_MCACHE_CTL_IC_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_EN_SHIFT) & CSR_MCACHE_CTL_IC_EN_MASK) +#define CSR_MCACHE_CTL_IC_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_EN_MASK) >> CSR_MCACHE_CTL_IC_EN_SHIFT) + +/* Bitfield definition for register: MCCTLBEGINADDR */ +/* + * VA (RW) + * + * This register holds the address information required by CCTL operations + */ +#define CSR_MCCTLBEGINADDR_VA_MASK (0xFFFFFFFFUL) +#define CSR_MCCTLBEGINADDR_VA_SHIFT (0U) +#define CSR_MCCTLBEGINADDR_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLBEGINADDR_VA_SHIFT) & CSR_MCCTLBEGINADDR_VA_MASK) +#define CSR_MCCTLBEGINADDR_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLBEGINADDR_VA_MASK) >> CSR_MCCTLBEGINADDR_VA_SHIFT) + +/* Bitfield definition for register: MCCTLCOMMAND */ +/* + * VA (RW) + * + * See CCTL Command Definition Table + */ +#define CSR_MCCTLCOMMAND_VA_MASK (0x1FU) +#define CSR_MCCTLCOMMAND_VA_SHIFT (0U) +#define CSR_MCCTLCOMMAND_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLCOMMAND_VA_SHIFT) & CSR_MCCTLCOMMAND_VA_MASK) +#define CSR_MCCTLCOMMAND_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLCOMMAND_VA_MASK) >> CSR_MCCTLCOMMAND_VA_SHIFT) + +/* Bitfield definition for register: MCCTLDATA */ +/* + * VA (RW) + * + * See CCTL Commands Which Access mcctldata Table + */ +#define CSR_MCCTLDATA_VA_MASK (0x1FU) +#define CSR_MCCTLDATA_VA_SHIFT (0U) +#define CSR_MCCTLDATA_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLDATA_VA_SHIFT) & CSR_MCCTLDATA_VA_MASK) +#define CSR_MCCTLDATA_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLDATA_VA_MASK) >> CSR_MCCTLDATA_VA_SHIFT) + +/* Bitfield definition for register: MCOUNTERWEN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_HPM6_MASK (0x40U) +#define CSR_MCOUNTERWEN_HPM6_SHIFT (6U) +#define CSR_MCOUNTERWEN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM6_SHIFT) & CSR_MCOUNTERWEN_HPM6_MASK) +#define CSR_MCOUNTERWEN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM6_MASK) >> CSR_MCOUNTERWEN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_HPM5_MASK (0x20U) +#define CSR_MCOUNTERWEN_HPM5_SHIFT (5U) +#define CSR_MCOUNTERWEN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM5_SHIFT) & CSR_MCOUNTERWEN_HPM5_MASK) +#define CSR_MCOUNTERWEN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM5_MASK) >> CSR_MCOUNTERWEN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_HPM4_MASK (0x10U) +#define CSR_MCOUNTERWEN_HPM4_SHIFT (4U) +#define CSR_MCOUNTERWEN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM4_SHIFT) & CSR_MCOUNTERWEN_HPM4_MASK) +#define CSR_MCOUNTERWEN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM4_MASK) >> CSR_MCOUNTERWEN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_HPM3_MASK (0x8U) +#define CSR_MCOUNTERWEN_HPM3_SHIFT (3U) +#define CSR_MCOUNTERWEN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM3_SHIFT) & CSR_MCOUNTERWEN_HPM3_MASK) +#define CSR_MCOUNTERWEN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM3_MASK) >> CSR_MCOUNTERWEN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_IR_MASK (0x4U) +#define CSR_MCOUNTERWEN_IR_SHIFT (2U) +#define CSR_MCOUNTERWEN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_IR_SHIFT) & CSR_MCOUNTERWEN_IR_MASK) +#define CSR_MCOUNTERWEN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_IR_MASK) >> CSR_MCOUNTERWEN_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_CY_MASK (0x1U) +#define CSR_MCOUNTERWEN_CY_SHIFT (0U) +#define CSR_MCOUNTERWEN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_CY_SHIFT) & CSR_MCOUNTERWEN_CY_MASK) +#define CSR_MCOUNTERWEN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_CY_MASK) >> CSR_MCOUNTERWEN_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTERINTEN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_HPM6_MASK (0x40U) +#define CSR_MCOUNTERINTEN_HPM6_SHIFT (6U) +#define CSR_MCOUNTERINTEN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM6_SHIFT) & CSR_MCOUNTERINTEN_HPM6_MASK) +#define CSR_MCOUNTERINTEN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM6_MASK) >> CSR_MCOUNTERINTEN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_HPM5_MASK (0x20U) +#define CSR_MCOUNTERINTEN_HPM5_SHIFT (5U) +#define CSR_MCOUNTERINTEN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM5_SHIFT) & CSR_MCOUNTERINTEN_HPM5_MASK) +#define CSR_MCOUNTERINTEN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM5_MASK) >> CSR_MCOUNTERINTEN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_HPM4_MASK (0x10U) +#define CSR_MCOUNTERINTEN_HPM4_SHIFT (4U) +#define CSR_MCOUNTERINTEN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM4_SHIFT) & CSR_MCOUNTERINTEN_HPM4_MASK) +#define CSR_MCOUNTERINTEN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM4_MASK) >> CSR_MCOUNTERINTEN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_HPM3_MASK (0x8U) +#define CSR_MCOUNTERINTEN_HPM3_SHIFT (3U) +#define CSR_MCOUNTERINTEN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM3_SHIFT) & CSR_MCOUNTERINTEN_HPM3_MASK) +#define CSR_MCOUNTERINTEN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM3_MASK) >> CSR_MCOUNTERINTEN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_IR_MASK (0x4U) +#define CSR_MCOUNTERINTEN_IR_SHIFT (2U) +#define CSR_MCOUNTERINTEN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_IR_SHIFT) & CSR_MCOUNTERINTEN_IR_MASK) +#define CSR_MCOUNTERINTEN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_IR_MASK) >> CSR_MCOUNTERINTEN_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_CY_MASK (0x1U) +#define CSR_MCOUNTERINTEN_CY_SHIFT (0U) +#define CSR_MCOUNTERINTEN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_CY_SHIFT) & CSR_MCOUNTERINTEN_CY_MASK) +#define CSR_MCOUNTERINTEN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_CY_MASK) >> CSR_MCOUNTERINTEN_CY_SHIFT) + +/* Bitfield definition for register: MMISC_CTL */ +/* + * MSA_UNA (RW) + * + * This field controls whether the load/store instructions can access misaligned memory locations without generating Address Misaligned exceptions. + * Supported instructions: LW/LH/LHU/SW/SH + * 0:Misaligned accesses generate Address Misaligned exceptions. + * 1:Misaligned accesses generate Address Misaligned exceptions. + */ +#define CSR_MMISC_CTL_MSA_UNA_MASK (0x40U) +#define CSR_MMISC_CTL_MSA_UNA_SHIFT (6U) +#define CSR_MMISC_CTL_MSA_UNA_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_MSA_UNA_SHIFT) & CSR_MMISC_CTL_MSA_UNA_MASK) +#define CSR_MMISC_CTL_MSA_UNA_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_MSA_UNA_MASK) >> CSR_MMISC_CTL_MSA_UNA_SHIFT) + +/* + * BRPE (RW) + * + * Branch prediction enable bit. This bit controls all branch prediction structures. + * 0:Disabled + * 1:Enabled + * This bit is hardwired to 0 if branch prediction structure is not supported. + */ +#define CSR_MMISC_CTL_BRPE_MASK (0x8U) +#define CSR_MMISC_CTL_BRPE_SHIFT (3U) +#define CSR_MMISC_CTL_BRPE_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_BRPE_SHIFT) & CSR_MMISC_CTL_BRPE_MASK) +#define CSR_MMISC_CTL_BRPE_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_BRPE_MASK) >> CSR_MMISC_CTL_BRPE_SHIFT) + +/* + * RVCOMPM (RW) + * + * RISC-V compatibility mode enable bit. If the compatibility mode is turned on, all specific instructions become reserved instructions + * 0:Disabled + * 1:Enabled + */ +#define CSR_MMISC_CTL_RVCOMPM_MASK (0x4U) +#define CSR_MMISC_CTL_RVCOMPM_SHIFT (2U) +#define CSR_MMISC_CTL_RVCOMPM_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_RVCOMPM_SHIFT) & CSR_MMISC_CTL_RVCOMPM_MASK) +#define CSR_MMISC_CTL_RVCOMPM_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_RVCOMPM_MASK) >> CSR_MMISC_CTL_RVCOMPM_SHIFT) + +/* + * VEC_PLIC (RW) + * + * Selects the operation mode of PLIC: + * 0:Regular mode + * 1:Vector mode + * Please note that both this bit and the vector mode enable bit (VECTORED) of the Feature Enable Register in NCEPLIC100 should be turned on for the vectored interrupt support to work correctly. This bit is hardwired to 0 if the vectored PLIC feature is not supported. + */ +#define CSR_MMISC_CTL_VEC_PLIC_MASK (0x2U) +#define CSR_MMISC_CTL_VEC_PLIC_SHIFT (1U) +#define CSR_MMISC_CTL_VEC_PLIC_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_VEC_PLIC_SHIFT) & CSR_MMISC_CTL_VEC_PLIC_MASK) +#define CSR_MMISC_CTL_VEC_PLIC_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_VEC_PLIC_MASK) >> CSR_MMISC_CTL_VEC_PLIC_SHIFT) + +/* Bitfield definition for register: MCOUNTERMASK_M */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_HPM6_MASK (0x40U) +#define CSR_MCOUNTERMASK_M_HPM6_SHIFT (6U) +#define CSR_MCOUNTERMASK_M_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM6_SHIFT) & CSR_MCOUNTERMASK_M_HPM6_MASK) +#define CSR_MCOUNTERMASK_M_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM6_MASK) >> CSR_MCOUNTERMASK_M_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_HPM5_MASK (0x20U) +#define CSR_MCOUNTERMASK_M_HPM5_SHIFT (5U) +#define CSR_MCOUNTERMASK_M_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM5_SHIFT) & CSR_MCOUNTERMASK_M_HPM5_MASK) +#define CSR_MCOUNTERMASK_M_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM5_MASK) >> CSR_MCOUNTERMASK_M_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_HPM4_MASK (0x10U) +#define CSR_MCOUNTERMASK_M_HPM4_SHIFT (4U) +#define CSR_MCOUNTERMASK_M_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM4_SHIFT) & CSR_MCOUNTERMASK_M_HPM4_MASK) +#define CSR_MCOUNTERMASK_M_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM4_MASK) >> CSR_MCOUNTERMASK_M_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_HPM3_MASK (0x8U) +#define CSR_MCOUNTERMASK_M_HPM3_SHIFT (3U) +#define CSR_MCOUNTERMASK_M_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM3_SHIFT) & CSR_MCOUNTERMASK_M_HPM3_MASK) +#define CSR_MCOUNTERMASK_M_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM3_MASK) >> CSR_MCOUNTERMASK_M_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_IR_MASK (0x4U) +#define CSR_MCOUNTERMASK_M_IR_SHIFT (2U) +#define CSR_MCOUNTERMASK_M_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_IR_SHIFT) & CSR_MCOUNTERMASK_M_IR_MASK) +#define CSR_MCOUNTERMASK_M_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_IR_MASK) >> CSR_MCOUNTERMASK_M_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_CY_MASK (0x1U) +#define CSR_MCOUNTERMASK_M_CY_SHIFT (0U) +#define CSR_MCOUNTERMASK_M_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_CY_SHIFT) & CSR_MCOUNTERMASK_M_CY_MASK) +#define CSR_MCOUNTERMASK_M_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_CY_MASK) >> CSR_MCOUNTERMASK_M_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTERMASK_S */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_HPM6_MASK (0x40U) +#define CSR_MCOUNTERMASK_S_HPM6_SHIFT (6U) +#define CSR_MCOUNTERMASK_S_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM6_SHIFT) & CSR_MCOUNTERMASK_S_HPM6_MASK) +#define CSR_MCOUNTERMASK_S_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM6_MASK) >> CSR_MCOUNTERMASK_S_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_HPM5_MASK (0x20U) +#define CSR_MCOUNTERMASK_S_HPM5_SHIFT (5U) +#define CSR_MCOUNTERMASK_S_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM5_SHIFT) & CSR_MCOUNTERMASK_S_HPM5_MASK) +#define CSR_MCOUNTERMASK_S_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM5_MASK) >> CSR_MCOUNTERMASK_S_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_HPM4_MASK (0x10U) +#define CSR_MCOUNTERMASK_S_HPM4_SHIFT (4U) +#define CSR_MCOUNTERMASK_S_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM4_SHIFT) & CSR_MCOUNTERMASK_S_HPM4_MASK) +#define CSR_MCOUNTERMASK_S_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM4_MASK) >> CSR_MCOUNTERMASK_S_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_HPM3_MASK (0x8U) +#define CSR_MCOUNTERMASK_S_HPM3_SHIFT (3U) +#define CSR_MCOUNTERMASK_S_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM3_SHIFT) & CSR_MCOUNTERMASK_S_HPM3_MASK) +#define CSR_MCOUNTERMASK_S_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM3_MASK) >> CSR_MCOUNTERMASK_S_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_IR_MASK (0x4U) +#define CSR_MCOUNTERMASK_S_IR_SHIFT (2U) +#define CSR_MCOUNTERMASK_S_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_IR_SHIFT) & CSR_MCOUNTERMASK_S_IR_MASK) +#define CSR_MCOUNTERMASK_S_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_IR_MASK) >> CSR_MCOUNTERMASK_S_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_CY_MASK (0x1U) +#define CSR_MCOUNTERMASK_S_CY_SHIFT (0U) +#define CSR_MCOUNTERMASK_S_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_CY_SHIFT) & CSR_MCOUNTERMASK_S_CY_MASK) +#define CSR_MCOUNTERMASK_S_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_CY_MASK) >> CSR_MCOUNTERMASK_S_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTERMASK_U */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_HPM6_MASK (0x40U) +#define CSR_MCOUNTERMASK_U_HPM6_SHIFT (6U) +#define CSR_MCOUNTERMASK_U_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM6_SHIFT) & CSR_MCOUNTERMASK_U_HPM6_MASK) +#define CSR_MCOUNTERMASK_U_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM6_MASK) >> CSR_MCOUNTERMASK_U_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_HPM5_MASK (0x20U) +#define CSR_MCOUNTERMASK_U_HPM5_SHIFT (5U) +#define CSR_MCOUNTERMASK_U_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM5_SHIFT) & CSR_MCOUNTERMASK_U_HPM5_MASK) +#define CSR_MCOUNTERMASK_U_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM5_MASK) >> CSR_MCOUNTERMASK_U_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_HPM4_MASK (0x10U) +#define CSR_MCOUNTERMASK_U_HPM4_SHIFT (4U) +#define CSR_MCOUNTERMASK_U_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM4_SHIFT) & CSR_MCOUNTERMASK_U_HPM4_MASK) +#define CSR_MCOUNTERMASK_U_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM4_MASK) >> CSR_MCOUNTERMASK_U_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_HPM3_MASK (0x8U) +#define CSR_MCOUNTERMASK_U_HPM3_SHIFT (3U) +#define CSR_MCOUNTERMASK_U_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM3_SHIFT) & CSR_MCOUNTERMASK_U_HPM3_MASK) +#define CSR_MCOUNTERMASK_U_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM3_MASK) >> CSR_MCOUNTERMASK_U_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_IR_MASK (0x4U) +#define CSR_MCOUNTERMASK_U_IR_SHIFT (2U) +#define CSR_MCOUNTERMASK_U_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_IR_SHIFT) & CSR_MCOUNTERMASK_U_IR_MASK) +#define CSR_MCOUNTERMASK_U_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_IR_MASK) >> CSR_MCOUNTERMASK_U_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_CY_MASK (0x1U) +#define CSR_MCOUNTERMASK_U_CY_SHIFT (0U) +#define CSR_MCOUNTERMASK_U_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_CY_SHIFT) & CSR_MCOUNTERMASK_U_CY_MASK) +#define CSR_MCOUNTERMASK_U_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_CY_MASK) >> CSR_MCOUNTERMASK_U_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTEROVF */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_HPM6_MASK (0x40U) +#define CSR_MCOUNTEROVF_HPM6_SHIFT (6U) +#define CSR_MCOUNTEROVF_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM6_SHIFT) & CSR_MCOUNTEROVF_HPM6_MASK) +#define CSR_MCOUNTEROVF_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM6_MASK) >> CSR_MCOUNTEROVF_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_HPM5_MASK (0x20U) +#define CSR_MCOUNTEROVF_HPM5_SHIFT (5U) +#define CSR_MCOUNTEROVF_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM5_SHIFT) & CSR_MCOUNTEROVF_HPM5_MASK) +#define CSR_MCOUNTEROVF_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM5_MASK) >> CSR_MCOUNTEROVF_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_HPM4_MASK (0x10U) +#define CSR_MCOUNTEROVF_HPM4_SHIFT (4U) +#define CSR_MCOUNTEROVF_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM4_SHIFT) & CSR_MCOUNTEROVF_HPM4_MASK) +#define CSR_MCOUNTEROVF_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM4_MASK) >> CSR_MCOUNTEROVF_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_HPM3_MASK (0x8U) +#define CSR_MCOUNTEROVF_HPM3_SHIFT (3U) +#define CSR_MCOUNTEROVF_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM3_SHIFT) & CSR_MCOUNTEROVF_HPM3_MASK) +#define CSR_MCOUNTEROVF_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM3_MASK) >> CSR_MCOUNTEROVF_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_IR_MASK (0x4U) +#define CSR_MCOUNTEROVF_IR_SHIFT (2U) +#define CSR_MCOUNTEROVF_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_IR_SHIFT) & CSR_MCOUNTEROVF_IR_MASK) +#define CSR_MCOUNTEROVF_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_IR_MASK) >> CSR_MCOUNTEROVF_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_CY_MASK (0x1U) +#define CSR_MCOUNTEROVF_CY_SHIFT (0U) +#define CSR_MCOUNTEROVF_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_CY_SHIFT) & CSR_MCOUNTEROVF_CY_MASK) +#define CSR_MCOUNTEROVF_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_CY_MASK) >> CSR_MCOUNTEROVF_CY_SHIFT) + +/* Bitfield definition for register: DEXC2DBG */ +/* + * PMOV (RW) + * + * Indicates whether performance counter overflow interrupts are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_PMOV_MASK (0x80000UL) +#define CSR_DEXC2DBG_PMOV_SHIFT (19U) +#define CSR_DEXC2DBG_PMOV_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_PMOV_SHIFT) & CSR_DEXC2DBG_PMOV_MASK) +#define CSR_DEXC2DBG_PMOV_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_PMOV_MASK) >> CSR_DEXC2DBG_PMOV_SHIFT) + +/* + * BWE (RW) + * + * Indicates whether Bus-write Transaction Error local interrupts are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_BWE_MASK (0x8000U) +#define CSR_DEXC2DBG_BWE_SHIFT (15U) +#define CSR_DEXC2DBG_BWE_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_BWE_SHIFT) & CSR_DEXC2DBG_BWE_MASK) +#define CSR_DEXC2DBG_BWE_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_BWE_MASK) >> CSR_DEXC2DBG_BWE_SHIFT) + +/* + * SLPECC (RW) + * + * Indicates whether local memory slave port ECC Error local interrupts are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SLPECC_MASK (0x4000U) +#define CSR_DEXC2DBG_SLPECC_SHIFT (14U) +#define CSR_DEXC2DBG_SLPECC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SLPECC_SHIFT) & CSR_DEXC2DBG_SLPECC_MASK) +#define CSR_DEXC2DBG_SLPECC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SLPECC_MASK) >> CSR_DEXC2DBG_SLPECC_SHIFT) + +/* + * ACE (RW) + * + * Indicates whether ACE-related exceptions are redirected to enter Debug Mode. This bit is present only when mmsc_cfg.ACE is set + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_ACE_MASK (0x2000U) +#define CSR_DEXC2DBG_ACE_SHIFT (13U) +#define CSR_DEXC2DBG_ACE_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_ACE_SHIFT) & CSR_DEXC2DBG_ACE_MASK) +#define CSR_DEXC2DBG_ACE_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_ACE_MASK) >> CSR_DEXC2DBG_ACE_SHIFT) + +/* + * HSP (RW) + * + * Indicates whether Stack Protection exceptions are redirected to enter Debug Mode. This bit is present only when mmsc_cfg.HSP is set. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_HSP_MASK (0x1000U) +#define CSR_DEXC2DBG_HSP_SHIFT (12U) +#define CSR_DEXC2DBG_HSP_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_HSP_SHIFT) & CSR_DEXC2DBG_HSP_MASK) +#define CSR_DEXC2DBG_HSP_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_HSP_MASK) >> CSR_DEXC2DBG_HSP_SHIFT) + +/* + * MEC (RW) + * + * Indicates whether M-mode Environment Call exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_MEC_MASK (0x800U) +#define CSR_DEXC2DBG_MEC_SHIFT (11U) +#define CSR_DEXC2DBG_MEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_MEC_SHIFT) & CSR_DEXC2DBG_MEC_MASK) +#define CSR_DEXC2DBG_MEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_MEC_MASK) >> CSR_DEXC2DBG_MEC_SHIFT) + +/* + * UEC (RW) + * + * Indicates whether U-mode Environment Call exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_UEC_MASK (0x100U) +#define CSR_DEXC2DBG_UEC_SHIFT (8U) +#define CSR_DEXC2DBG_UEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_UEC_SHIFT) & CSR_DEXC2DBG_UEC_MASK) +#define CSR_DEXC2DBG_UEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_UEC_MASK) >> CSR_DEXC2DBG_UEC_SHIFT) + +/* + * SAF (RW) + * + * Indicates whether Store Access Fault exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SAF_MASK (0x80U) +#define CSR_DEXC2DBG_SAF_SHIFT (7U) +#define CSR_DEXC2DBG_SAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SAF_SHIFT) & CSR_DEXC2DBG_SAF_MASK) +#define CSR_DEXC2DBG_SAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SAF_MASK) >> CSR_DEXC2DBG_SAF_SHIFT) + +/* + * SAM (RW) + * + * Indicates whether Store Access Misaligned exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SAM_MASK (0x40U) +#define CSR_DEXC2DBG_SAM_SHIFT (6U) +#define CSR_DEXC2DBG_SAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SAM_SHIFT) & CSR_DEXC2DBG_SAM_MASK) +#define CSR_DEXC2DBG_SAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SAM_MASK) >> CSR_DEXC2DBG_SAM_SHIFT) + +/* + * LAF (RW) + * + * Indicates whether Load Access Fault exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_LAF_MASK (0x20U) +#define CSR_DEXC2DBG_LAF_SHIFT (5U) +#define CSR_DEXC2DBG_LAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LAF_SHIFT) & CSR_DEXC2DBG_LAF_MASK) +#define CSR_DEXC2DBG_LAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LAF_MASK) >> CSR_DEXC2DBG_LAF_SHIFT) + +/* + * LAM (RW) + * + * Indicates whether Load Access Misaligned exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_LAM_MASK (0x10U) +#define CSR_DEXC2DBG_LAM_SHIFT (4U) +#define CSR_DEXC2DBG_LAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LAM_SHIFT) & CSR_DEXC2DBG_LAM_MASK) +#define CSR_DEXC2DBG_LAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LAM_MASK) >> CSR_DEXC2DBG_LAM_SHIFT) + +/* + * NMI (RW) + * + * Indicates whether Non-Maskable Interrupt + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_NMI_MASK (0x8U) +#define CSR_DEXC2DBG_NMI_SHIFT (3U) +#define CSR_DEXC2DBG_NMI_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_NMI_SHIFT) & CSR_DEXC2DBG_NMI_MASK) +#define CSR_DEXC2DBG_NMI_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_NMI_MASK) >> CSR_DEXC2DBG_NMI_SHIFT) + +/* + * II (RW) + * + * Indicates whether Illegal Instruction exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_II_MASK (0x4U) +#define CSR_DEXC2DBG_II_SHIFT (2U) +#define CSR_DEXC2DBG_II_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_II_SHIFT) & CSR_DEXC2DBG_II_MASK) +#define CSR_DEXC2DBG_II_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_II_MASK) >> CSR_DEXC2DBG_II_SHIFT) + +/* + * IAF (RW) + * + * Indicates whether Instruction Access Fault exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_IAF_MASK (0x2U) +#define CSR_DEXC2DBG_IAF_SHIFT (1U) +#define CSR_DEXC2DBG_IAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IAF_SHIFT) & CSR_DEXC2DBG_IAF_MASK) +#define CSR_DEXC2DBG_IAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IAF_MASK) >> CSR_DEXC2DBG_IAF_SHIFT) + +/* + * IAM (RW) + * + * Indicates whether Instruction Access Misaligned exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_IAM_MASK (0x1U) +#define CSR_DEXC2DBG_IAM_SHIFT (0U) +#define CSR_DEXC2DBG_IAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IAM_SHIFT) & CSR_DEXC2DBG_IAM_MASK) +#define CSR_DEXC2DBG_IAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IAM_MASK) >> CSR_DEXC2DBG_IAM_SHIFT) + +/* Bitfield definition for register: DDCAUSE */ +/* + * SUBTYPE (RO) + * + * Subtypes for main type. + * The table below lists the subtypes for DCSR.CAUSE==1 and DDCAUSE.MAINTYPE==3. + * 0:Illegal instruction + * 1:Privileged instruction + * 2:Non-existent CSR + * 3:Privilege CSR access + * 4:Read-only CSR update + */ +#define CSR_DDCAUSE_SUBTYPE_MASK (0xFF00U) +#define CSR_DDCAUSE_SUBTYPE_SHIFT (8U) +#define CSR_DDCAUSE_SUBTYPE_GET(x) (((uint32_t)(x) & CSR_DDCAUSE_SUBTYPE_MASK) >> CSR_DDCAUSE_SUBTYPE_SHIFT) + +/* + * MAINTYPE (RO) + * + * Cause for redirection to Debug Mode. + * 0:Software Breakpoint (EBREAK) + * 1:Instruction Access Misaligned (IAM) + * 2:Instruction Access Fault (IAF) + * 3:Illegal Instruction (II) + * 4:Non-Maskable Interrupt (NMI) + * 5:Load Access Misaligned (LAM) + * 6:Load Access Fault (LAF) + * 7:Store Access Misaligned (SAM) + * 8:Store Access Fault (SAF) + * 9:U-mode Environment Call (UEC) + * 10:S-mode Environment Call (SEC) + * 11:Instruction page fault + * 12:M-mode Environment Call (MEC) + * 13:Load page fault + * 14:Reserved + * 15:Store/AMO page fault + * 16:Imprecise ECC error + * 17;Bus write transaction error + * 18:Performance Counter overflow + * 19–31:Reserved + * 32:Stack overflow exception + * 33:Stack underflow exception + * 34:ACE disabled exception + * 35–39:Reserved + * 40–47:ACE exception + * ≥48:Reserved + */ +#define CSR_DDCAUSE_MAINTYPE_MASK (0xFFU) +#define CSR_DDCAUSE_MAINTYPE_SHIFT (0U) +#define CSR_DDCAUSE_MAINTYPE_GET(x) (((uint32_t)(x) & CSR_DDCAUSE_MAINTYPE_MASK) >> CSR_DDCAUSE_MAINTYPE_SHIFT) + +/* Bitfield definition for register: UITB */ +/* + * ADDR (RW) + * + * The base address of the CoDense instruction table. This field is reserved if uitb.HW == 1. + */ +#define CSR_UITB_ADDR_MASK (0xFFFFFFFCUL) +#define CSR_UITB_ADDR_SHIFT (2U) +#define CSR_UITB_ADDR_SET(x) (((uint32_t)(x) << CSR_UITB_ADDR_SHIFT) & CSR_UITB_ADDR_MASK) +#define CSR_UITB_ADDR_GET(x) (((uint32_t)(x) & CSR_UITB_ADDR_MASK) >> CSR_UITB_ADDR_SHIFT) + +/* + * HW (RO) + * + * This bit specifies if the CoDense instruction table is hardwired. + * 0:The instruction table is located in memory. uitb.ADDR should be initialized to point to the table before using the CoDense instructions. + * 1:The instruction table is hardwired. Initialization of uitb.ADDR is not needed before using the CoDense instructions. + */ +#define CSR_UITB_HW_MASK (0x1U) +#define CSR_UITB_HW_SHIFT (0U) +#define CSR_UITB_HW_GET(x) (((uint32_t)(x) & CSR_UITB_HW_MASK) >> CSR_UITB_HW_SHIFT) + +/* Bitfield definition for register: UCODE */ +/* + * OV (RW) + * + * Overflow flag. It will be set by DSP instructions with a saturated result. + * 0:A saturated result is not generated + * 1:A saturated result is generated + */ +#define CSR_UCODE_OV_MASK (0x1U) +#define CSR_UCODE_OV_SHIFT (0U) +#define CSR_UCODE_OV_SET(x) (((uint32_t)(x) << CSR_UCODE_OV_SHIFT) & CSR_UCODE_OV_MASK) +#define CSR_UCODE_OV_GET(x) (((uint32_t)(x) & CSR_UCODE_OV_MASK) >> CSR_UCODE_OV_SHIFT) + +/* Bitfield definition for register: UDCAUSE */ +/* + * UDCAUSE (RW) + * + * This register further disambiguates causes of traps recorded in the ucause register. See the list below for details. + * The value of UDCAUSE for precise exception: + * When ucause == 1 (Instruction access fault) + * 0:Reserved + * 1:ECC/Parity error + * 2:PMP instruction access violation + * 3:Bus error + * 4:PMA empty hole access + * When ucause == 2 (Illegal instruction) + * 0:Please parse the utval CSR + * 1:FP disabled exception + * 2:ACE disabled exception + * When ucause == 5 (Load access fault) + * 0:Reserved + * 1:ECC/Parity error + * 2:PMP load access violation + * 3:Bus error + * 4:Misaligned address + * 5:PMA empty hole access + * 6:PMA attribute inconsistency + * 7:PMA NAMO exception + * When ucause == 7 (Store access fault) + * 0:Reserved + * 1:ECC/Parity error + * 2:PMP store access violation + * 3:Bus error + * 4:Misaligned address + * 5:PMA empty hole access + * 6:PMA attribute inconsistency + * 7:PMA NAMO exception + */ +#define CSR_UDCAUSE_UDCAUSE_MASK (0x7U) +#define CSR_UDCAUSE_UDCAUSE_SHIFT (0U) +#define CSR_UDCAUSE_UDCAUSE_SET(x) (((uint32_t)(x) << CSR_UDCAUSE_UDCAUSE_SHIFT) & CSR_UDCAUSE_UDCAUSE_MASK) +#define CSR_UDCAUSE_UDCAUSE_GET(x) (((uint32_t)(x) & CSR_UDCAUSE_UDCAUSE_MASK) >> CSR_UDCAUSE_UDCAUSE_SHIFT) + +/* Bitfield definition for register: UCCTLBEGINADDR */ +/* + * VA (RW) + * + * It is an alias to the mcctlbeginaddr register and it is only accessible to Supervisor-mode and User-mode software when mcache_ctl.CCTL_SUEN is 1. Otherwise illegal instruction exceptions will be triggered. + */ +#define CSR_UCCTLBEGINADDR_VA_MASK (0xFFFFFFFFUL) +#define CSR_UCCTLBEGINADDR_VA_SHIFT (0U) +#define CSR_UCCTLBEGINADDR_VA_SET(x) (((uint32_t)(x) << CSR_UCCTLBEGINADDR_VA_SHIFT) & CSR_UCCTLBEGINADDR_VA_MASK) +#define CSR_UCCTLBEGINADDR_VA_GET(x) (((uint32_t)(x) & CSR_UCCTLBEGINADDR_VA_MASK) >> CSR_UCCTLBEGINADDR_VA_SHIFT) + +/* Bitfield definition for register: UCCTLCOMMAND */ +/* + * VA (RW) + * + * See User CCTL Command Definition Table + */ +#define CSR_UCCTLCOMMAND_VA_MASK (0x1FU) +#define CSR_UCCTLCOMMAND_VA_SHIFT (0U) +#define CSR_UCCTLCOMMAND_VA_SET(x) (((uint32_t)(x) << CSR_UCCTLCOMMAND_VA_SHIFT) & CSR_UCCTLCOMMAND_VA_MASK) +#define CSR_UCCTLCOMMAND_VA_GET(x) (((uint32_t)(x) & CSR_UCCTLCOMMAND_VA_MASK) >> CSR_UCCTLCOMMAND_VA_SHIFT) + +/* Bitfield definition for register: MICM_CFG */ +/* + * SETH (RO) + * + * This bit extends the ISET field. + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_SETH_MASK (0x1000000UL) +#define CSR_MICM_CFG_SETH_SHIFT (24U) +#define CSR_MICM_CFG_SETH_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_SETH_MASK) >> CSR_MICM_CFG_SETH_SHIFT) + +/* + * ILM_ECC (RO) + * + * ILM soft-error protection scheme + * 0:No parity/ECC + * 1:Parity + * 2:ECC + * 3:Reserved + * ILM is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ILM_ECC_MASK (0x600000UL) +#define CSR_MICM_CFG_ILM_ECC_SHIFT (21U) +#define CSR_MICM_CFG_ILM_ECC_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILM_ECC_MASK) >> CSR_MICM_CFG_ILM_ECC_SHIFT) + +/* + * ILMSZ (RO) + * + * ILM Size + * 0:0 Byte + * 1:1 KiB + * 2:2 KiB + * 3:4 KiB + * 4:8 KiB + * 5:16 KiB + * 6:32 KiB + * 7:64 KiB + * 8:128 KiB + * 9:256 KiB + * 10:512 KiB + * 11:1 MiB + * 12:2 MiB + * 13:4 MiB + * 14:8 MiB + * 15:16 MiB + * 16-31:Reserved + * When ILM is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ILMSZ_MASK (0xF8000UL) +#define CSR_MICM_CFG_ILMSZ_SHIFT (15U) +#define CSR_MICM_CFG_ILMSZ_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILMSZ_MASK) >> CSR_MICM_CFG_ILMSZ_SHIFT) + +/* + * ILMB (RW) + * + * Number of ILM base registers present + * 0:No ILM base register present + * 1:One ILM base register present + * 2-7:Reserved + * When ILM is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ILMB_MASK (0x7000U) +#define CSR_MICM_CFG_ILMB_SHIFT (12U) +#define CSR_MICM_CFG_ILMB_SET(x) (((uint32_t)(x) << CSR_MICM_CFG_ILMB_SHIFT) & CSR_MICM_CFG_ILMB_MASK) +#define CSR_MICM_CFG_ILMB_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILMB_MASK) >> CSR_MICM_CFG_ILMB_SHIFT) + +/* + * IC_ECC (RO) + * + * Cache soft-error protection scheme + * 0:No parity/ECC + * 1:Parity + * 2:ECC + * 3:Reserved + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_IC_ECC_MASK (0xC00U) +#define CSR_MICM_CFG_IC_ECC_SHIFT (10U) +#define CSR_MICM_CFG_IC_ECC_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_IC_ECC_MASK) >> CSR_MICM_CFG_IC_ECC_SHIFT) + +/* + * ILCK (RO) + * + * I-Cache locking support + * 0:No locking support + * 1:With locking support + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ILCK_MASK (0x200U) +#define CSR_MICM_CFG_ILCK_SHIFT (9U) +#define CSR_MICM_CFG_ILCK_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILCK_MASK) >> CSR_MICM_CFG_ILCK_SHIFT) + +/* + * ISZ (RO) + * + * Cache block (line) size + * 0:No I-Cache + * 1:8 bytes + * 2:16 bytes + * 3:32 bytes + * 4:64 bytes + * 5:128 bytes + * 6-7:Reserved + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ISZ_MASK (0x1C0U) +#define CSR_MICM_CFG_ISZ_SHIFT (6U) +#define CSR_MICM_CFG_ISZ_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ISZ_MASK) >> CSR_MICM_CFG_ISZ_SHIFT) + +/* + * IWAY (RO) + * + * Associativity of I-Cache + * 0:Direct-mapped + * 1:2-way + * 2:3-way + * 3:4-way + * 4:5-way + * 5:6-way + * 6:7-way + * 7:8-way + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_IWAY_MASK (0x38U) +#define CSR_MICM_CFG_IWAY_SHIFT (3U) +#define CSR_MICM_CFG_IWAY_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_IWAY_MASK) >> CSR_MICM_CFG_IWAY_SHIFT) + +/* + * ISET (RO) + * + * I-Cache sets (# of cache lines per way): + * When micm_cfg.SETH==0: + * 0:64 + * 1:128 + * 2:256 + * 3:512 + * 4:1024 + * 5:2048 + * 6:4096 + * 7:Reserved + * When micm_cfg.SETH==1: + * 0:32 + * 1:16 + * 2:8 + * 3-7:Reserved + */ +#define CSR_MICM_CFG_ISET_MASK (0x7U) +#define CSR_MICM_CFG_ISET_SHIFT (0U) +#define CSR_MICM_CFG_ISET_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ISET_MASK) >> CSR_MICM_CFG_ISET_SHIFT) + +/* Bitfield definition for register: MDCM_CFG */ +/* + * SETH (RO) + * + * This bit extends the DSET field. + * When data cache is not configured, this field should be ignored + */ +#define CSR_MDCM_CFG_SETH_MASK (0x1000000UL) +#define CSR_MDCM_CFG_SETH_SHIFT (24U) +#define CSR_MDCM_CFG_SETH_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_SETH_MASK) >> CSR_MDCM_CFG_SETH_SHIFT) + +/* + * DLM_ECC (RO) + * + * DLM soft-error protection scheme + * 0:No parity/ECC + * 1:Parity + * 2:ECC + * 3:Reserved + * When DLM is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DLM_ECC_MASK (0x600000UL) +#define CSR_MDCM_CFG_DLM_ECC_SHIFT (21U) +#define CSR_MDCM_CFG_DLM_ECC_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLM_ECC_MASK) >> CSR_MDCM_CFG_DLM_ECC_SHIFT) + +/* + * DLMSZ (RO) + * + * DLM Size + * 0:0 Byte + * 1:1 KiB + * 2:2 KiB + * 3:4 KiB + * 4:8 KiB + * 5:16 KiB + * 6:32 KiB + * 7:64 KiB + * 8:128 KiB + * 9:256 KiB + * 10:512 KiB + * 11:1 MiB + * 12:2 MiB + * 13:4 MiB + * 14:8 MiB + * 15:16 MiB + * 16-31:Reserved + * When ILM is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DLMSZ_MASK (0xF8000UL) +#define CSR_MDCM_CFG_DLMSZ_SHIFT (15U) +#define CSR_MDCM_CFG_DLMSZ_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLMSZ_MASK) >> CSR_MDCM_CFG_DLMSZ_SHIFT) + +/* + * DLMB (RO) + * + * Number of DLM base registers present + * 0:No DLM base register present + * 1:One DLM base register present + * 2-7:Reserved + * When DLM is not configured, this field should be ignored + */ +#define CSR_MDCM_CFG_DLMB_MASK (0x7000U) +#define CSR_MDCM_CFG_DLMB_SHIFT (12U) +#define CSR_MDCM_CFG_DLMB_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLMB_MASK) >> CSR_MDCM_CFG_DLMB_SHIFT) + +/* + * DC_ECC (RO) + * + * Cache soft-error protection scheme + * 0:No parity/ECC support + * 1:Has parity support + * 2:Has ECC support + * 3:Reserved + * When data cache is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DC_ECC_MASK (0xC00U) +#define CSR_MDCM_CFG_DC_ECC_SHIFT (10U) +#define CSR_MDCM_CFG_DC_ECC_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DC_ECC_MASK) >> CSR_MDCM_CFG_DC_ECC_SHIFT) + +/* + * DLCK (RO) + * + * D-Cache locking support + * 0:No locking support + * 1:With locking support + * When data cache is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DLCK_MASK (0x200U) +#define CSR_MDCM_CFG_DLCK_SHIFT (9U) +#define CSR_MDCM_CFG_DLCK_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLCK_MASK) >> CSR_MDCM_CFG_DLCK_SHIFT) + +/* + * DSZ (RO) + * + * Cache block (line) size + * 0:No I-Cache + * 1:8 bytes + * 2:16 bytes + * 3:32 bytes + * 4:64 bytes + * 5:128 bytes + * 6-7:Reserved + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DSZ_MASK (0x1C0U) +#define CSR_MDCM_CFG_DSZ_SHIFT (6U) +#define CSR_MDCM_CFG_DSZ_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DSZ_MASK) >> CSR_MDCM_CFG_DSZ_SHIFT) + +/* + * DWAY (RO) + * + * Associativity of D-Cache + * 0:Direct-mapped + * 1:2-way + * 2:3-way + * 3:4-way + * 4:5-way + * 5:6-way + * 6:7-way + * 7:8-way + * When data cache is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DWAY_MASK (0x38U) +#define CSR_MDCM_CFG_DWAY_SHIFT (3U) +#define CSR_MDCM_CFG_DWAY_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DWAY_MASK) >> CSR_MDCM_CFG_DWAY_SHIFT) + +/* + * DSET (RO) + * + * D-Cache sets (# of cache lines per way): + * When mdcm_cfg.SETH==0: + * 0:64 + * 1:128 + * 2:256 + * 3:512 + * 4:1024 + * 5:2048 + * 6:4096 + * 7:Reserved + * When mdcm_cfg.SETH==1: + * 0:32 + * 1:16 + * 2:8 + * 3-7:Reserved + * When data cache is not configured, this field should be ignored + */ +#define CSR_MDCM_CFG_DSET_MASK (0x7U) +#define CSR_MDCM_CFG_DSET_SHIFT (0U) +#define CSR_MDCM_CFG_DSET_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DSET_MASK) >> CSR_MDCM_CFG_DSET_SHIFT) + +/* Bitfield definition for register: MMSC_CFG */ +/* + * MSC_EXT (RO) + * + * Indicates if the mmsc_cfg2 CSR is present or not. + * 0:The mmsc_cfg2 CSR is not present. + * 1:The mmsc_cfg2 CSR is present + */ +#define CSR_MMSC_CFG_MSC_EXT_MASK (0x80000000UL) +#define CSR_MMSC_CFG_MSC_EXT_SHIFT (31U) +#define CSR_MMSC_CFG_MSC_EXT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_MSC_EXT_MASK) >> CSR_MMSC_CFG_MSC_EXT_SHIFT) + +/* + * PPMA (RO) + * + * Indicates if programmable PMA setup with PMA region CSRs is supported or not + * 0:Programmable PMA setup is not supported. + * 1:Programmable PMA setup is supported. + */ +#define CSR_MMSC_CFG_PPMA_MASK (0x40000000UL) +#define CSR_MMSC_CFG_PPMA_SHIFT (30U) +#define CSR_MMSC_CFG_PPMA_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PPMA_MASK) >> CSR_MMSC_CFG_PPMA_SHIFT) + +/* + * EDSP (RO) + * + * Indicates if the DSP extension is supported or not + * 0:The DSP extension is not supported. + * 1:The DSP extension is supported. + */ +#define CSR_MMSC_CFG_EDSP_MASK (0x20000000UL) +#define CSR_MMSC_CFG_EDSP_SHIFT (29U) +#define CSR_MMSC_CFG_EDSP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EDSP_MASK) >> CSR_MMSC_CFG_EDSP_SHIFT) + +/* + * VCCTL (RO) + * + * Indicates the version number of CCTL command operation scheme supported by an implementation + * 0:instruction cache and data cache are not configured. + * 1:instruction cache or data cache is configured. + */ +#define CSR_MMSC_CFG_VCCTL_MASK (0xC0000UL) +#define CSR_MMSC_CFG_VCCTL_SHIFT (18U) +#define CSR_MMSC_CFG_VCCTL_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_VCCTL_MASK) >> CSR_MMSC_CFG_VCCTL_SHIFT) + +/* + * EFHW (RO) + * + * Indicates the support of FLHW and FSHW instructions + * 0:FLHW and FSHW instructions are not supported + * 1:FLHW and FSHW instructions are supported. + */ +#define CSR_MMSC_CFG_EFHW_MASK (0x20000UL) +#define CSR_MMSC_CFG_EFHW_SHIFT (17U) +#define CSR_MMSC_CFG_EFHW_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EFHW_MASK) >> CSR_MMSC_CFG_EFHW_SHIFT) + +/* + * CCTLCSR (RO) + * + * Indicates the presence of CSRs for CCTL operations. + * 0:Feature of CSRs for CCTL operations is not supported. + * 1:Feature of CSRs for CCTL operations is supported. + */ +#define CSR_MMSC_CFG_CCTLCSR_MASK (0x10000UL) +#define CSR_MMSC_CFG_CCTLCSR_SHIFT (16U) +#define CSR_MMSC_CFG_CCTLCSR_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_CCTLCSR_MASK) >> CSR_MMSC_CFG_CCTLCSR_SHIFT) + +/* + * PMNDS (RO) + * + * Indicates if Andes-enhanced performance monitoring feature is present or no. + * 0:Andes-enhanced performance monitoring feature is not supported. + * 1:Andes-enhanced performance monitoring feature is supported. + */ +#define CSR_MMSC_CFG_PMNDS_MASK (0x8000U) +#define CSR_MMSC_CFG_PMNDS_SHIFT (15U) +#define CSR_MMSC_CFG_PMNDS_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PMNDS_MASK) >> CSR_MMSC_CFG_PMNDS_SHIFT) + +/* + * LMSLVP (RO) + * + * Indicates if local memory slave port is present or not. + * 0:Local memory slave port is not present. + * 1:Local memory slave port is implemented. + */ +#define CSR_MMSC_CFG_LMSLVP_MASK (0x4000U) +#define CSR_MMSC_CFG_LMSLVP_SHIFT (14U) +#define CSR_MMSC_CFG_LMSLVP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_LMSLVP_MASK) >> CSR_MMSC_CFG_LMSLVP_SHIFT) + +/* + * EV5PE (RO) + * + * Indicates whether AndeStar V5 Performance Extension is implemented or not. D45 always implements AndeStar V5 Performance Extension. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_EV5PE_MASK (0x2000U) +#define CSR_MMSC_CFG_EV5PE_SHIFT (13U) +#define CSR_MMSC_CFG_EV5PE_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EV5PE_MASK) >> CSR_MMSC_CFG_EV5PE_SHIFT) + +/* + * VPLIC (RO) + * + * Indicates whether the Andes Vectored PLIC Extension is implemented or not. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_VPLIC_MASK (0x1000U) +#define CSR_MMSC_CFG_VPLIC_SHIFT (12U) +#define CSR_MMSC_CFG_VPLIC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_VPLIC_MASK) >> CSR_MMSC_CFG_VPLIC_SHIFT) + +/* + * ACE (RO) + * + * Indicates whether the Andes StackSafe hardware stack protection extension is implemented or not. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_ACE_MASK (0x40U) +#define CSR_MMSC_CFG_ACE_SHIFT (6U) +#define CSR_MMSC_CFG_ACE_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ACE_MASK) >> CSR_MMSC_CFG_ACE_SHIFT) + +/* + * HSP (RO) + * + * Indicates whether the Andes PowerBrake (Performance Throttling) power/performance scaling extension is implemented or not. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_HSP_MASK (0x20U) +#define CSR_MMSC_CFG_HSP_SHIFT (5U) +#define CSR_MMSC_CFG_HSP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_HSP_MASK) >> CSR_MMSC_CFG_HSP_SHIFT) + +/* + * PFT (RO) + * + * Indicates whether the Andes PowerBrake (Performance Throttling) power/performance scaling extension is implemented or not + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_PFT_MASK (0x10U) +#define CSR_MMSC_CFG_PFT_SHIFT (4U) +#define CSR_MMSC_CFG_PFT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PFT_MASK) >> CSR_MMSC_CFG_PFT_SHIFT) + +/* + * ECD (RO) + * + * Indicates whether the Andes CoDense Extension is implemented or not. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_ECD_MASK (0x8U) +#define CSR_MMSC_CFG_ECD_SHIFT (3U) +#define CSR_MMSC_CFG_ECD_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ECD_MASK) >> CSR_MMSC_CFG_ECD_SHIFT) + +/* + * TLB_ECC (RO) + * + * TLB parity/ECC support configuration. + * 0:No parity/ECC + * 1:Parity + * 2:ECC + * 3:Reserved + */ +#define CSR_MMSC_CFG_TLB_ECC_MASK (0x6U) +#define CSR_MMSC_CFG_TLB_ECC_SHIFT (1U) +#define CSR_MMSC_CFG_TLB_ECC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_TLB_ECC_MASK) >> CSR_MMSC_CFG_TLB_ECC_SHIFT) + +/* + * ECC (RO) + * + * Indicates whether the parity/ECC soft-error protection is implemented or not. + * 0:Not implemented. + * 1:Implemented. + * The specific parity/ECC scheme used for each protected RAM is specified by the control bits in the following list. + * micm_cfg.IC_ECC + * micm_cfg.ILM_ECC + * mdcm_cfg.DC_ECC + * mdcm_cfg.DLM_ECC + * mmsc_cfg.TLB_ECC + */ +#define CSR_MMSC_CFG_ECC_MASK (0x1U) +#define CSR_MMSC_CFG_ECC_SHIFT (0U) +#define CSR_MMSC_CFG_ECC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ECC_MASK) >> CSR_MMSC_CFG_ECC_SHIFT) + +/* Bitfield definition for register: MMSC_CFG2 */ +/* + * FINV (RO) + * + * Indicates if scalar FPU is implemented in VPU + * 0:Scalar FPU is not implemented in VPU + * 1:Scalar FPU is implemented in VPU + */ +#define CSR_MMSC_CFG2_FINV_MASK (0x20U) +#define CSR_MMSC_CFG2_FINV_SHIFT (5U) +#define CSR_MMSC_CFG2_FINV_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_FINV_MASK) >> CSR_MMSC_CFG2_FINV_SHIFT) + +/* + * ZFH (RO) + * + * Indicates if the FP16 half-precision floating-point extension (Zfh) is supported or not. + * 0:The FP16 extension is not supported. + * 1:The FP16 extension is supported + */ +#define CSR_MMSC_CFG2_ZFH_MASK (0x2U) +#define CSR_MMSC_CFG2_ZFH_SHIFT (1U) +#define CSR_MMSC_CFG2_ZFH_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_ZFH_MASK) >> CSR_MMSC_CFG2_ZFH_SHIFT) + +/* + * BF16CVT (RO) + * + * Indicates if the BFLOAT16 conversion extension + * is supported or not. + * 0:The BFLOAT16 conversion extension is not supported + * 1:The BFLOAT16 conversion extension is supported + */ +#define CSR_MMSC_CFG2_BF16CVT_MASK (0x1U) +#define CSR_MMSC_CFG2_BF16CVT_SHIFT (0U) +#define CSR_MMSC_CFG2_BF16CVT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_BF16CVT_MASK) >> CSR_MMSC_CFG2_BF16CVT_SHIFT) + + +#endif /* HPM_CSR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_dmamux_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_dmamux_regs.h new file mode 100644 index 00000000000..b656cf1c5a1 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_dmamux_regs.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_DMAMUX_H +#define HPM_DMAMUX_H + +typedef struct { + __W uint32_t MUXCFG[32]; /* 0x0 - 0x7C: HDMA MUX0 Configuration */ +} DMAMUX_Type; + + +/* Bitfield definition for register array: MUXCFG */ +/* + * ENABLE (WO) + * + * DMA Mux Channel Enable + * Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be + * used to disable or reconfigure a DMA channel. + * 0b - DMA Mux channel is disabled + * 1b - DMA Mux channel is enabled + */ +#define DMAMUX_MUXCFG_ENABLE_MASK (0x80000000UL) +#define DMAMUX_MUXCFG_ENABLE_SHIFT (31U) +#define DMAMUX_MUXCFG_ENABLE_SET(x) (((uint32_t)(x) << DMAMUX_MUXCFG_ENABLE_SHIFT) & DMAMUX_MUXCFG_ENABLE_MASK) +#define DMAMUX_MUXCFG_ENABLE_GET(x) (((uint32_t)(x) & DMAMUX_MUXCFG_ENABLE_MASK) >> DMAMUX_MUXCFG_ENABLE_SHIFT) + +/* + * SOURCE (WO) + * + * DMA Channel Source + * Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + */ +#define DMAMUX_MUXCFG_SOURCE_MASK (0x7FU) +#define DMAMUX_MUXCFG_SOURCE_SHIFT (0U) +#define DMAMUX_MUXCFG_SOURCE_SET(x) (((uint32_t)(x) << DMAMUX_MUXCFG_SOURCE_SHIFT) & DMAMUX_MUXCFG_SOURCE_MASK) +#define DMAMUX_MUXCFG_SOURCE_GET(x) (((uint32_t)(x) & DMAMUX_MUXCFG_SOURCE_MASK) >> DMAMUX_MUXCFG_SOURCE_SHIFT) + + + +/* MUXCFG register group index macro definition */ +#define DMAMUX_MUXCFG_HDMA_MUX0 (0UL) +#define DMAMUX_MUXCFG_HDMA_MUX1 (1UL) +#define DMAMUX_MUXCFG_HDMA_MUX2 (2UL) +#define DMAMUX_MUXCFG_HDMA_MUX3 (3UL) +#define DMAMUX_MUXCFG_HDMA_MUX4 (4UL) +#define DMAMUX_MUXCFG_HDMA_MUX5 (5UL) +#define DMAMUX_MUXCFG_HDMA_MUX6 (6UL) +#define DMAMUX_MUXCFG_HDMA_MUX7 (7UL) +#define DMAMUX_MUXCFG_HDMA_MUX8 (8UL) +#define DMAMUX_MUXCFG_HDMA_MUX9 (9UL) +#define DMAMUX_MUXCFG_HDMA_MUX10 (10UL) +#define DMAMUX_MUXCFG_HDMA_MUX11 (11UL) +#define DMAMUX_MUXCFG_HDMA_MUX12 (12UL) +#define DMAMUX_MUXCFG_HDMA_MUX13 (13UL) +#define DMAMUX_MUXCFG_HDMA_MUX14 (14UL) +#define DMAMUX_MUXCFG_HDMA_MUX15 (15UL) +#define DMAMUX_MUXCFG_HDMA_MUX16 (16UL) +#define DMAMUX_MUXCFG_HDMA_MUX17 (17UL) +#define DMAMUX_MUXCFG_HDMA_MUX18 (18UL) +#define DMAMUX_MUXCFG_HDMA_MUX19 (19UL) +#define DMAMUX_MUXCFG_HDMA_MUX20 (20UL) +#define DMAMUX_MUXCFG_HDMA_MUX21 (21UL) +#define DMAMUX_MUXCFG_HDMA_MUX22 (22UL) +#define DMAMUX_MUXCFG_HDMA_MUX23 (23UL) +#define DMAMUX_MUXCFG_HDMA_MUX24 (24UL) +#define DMAMUX_MUXCFG_HDMA_MUX25 (25UL) +#define DMAMUX_MUXCFG_HDMA_MUX26 (26UL) +#define DMAMUX_MUXCFG_HDMA_MUX27 (27UL) +#define DMAMUX_MUXCFG_HDMA_MUX28 (28UL) +#define DMAMUX_MUXCFG_HDMA_MUX29 (29UL) +#define DMAMUX_MUXCFG_HDMA_MUX30 (30UL) +#define DMAMUX_MUXCFG_HDMA_MUX31 (31UL) + + +#endif /* HPM_DMAMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_dmamux_src.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_dmamux_src.h new file mode 100644 index 00000000000..285bf648e26 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_dmamux_src.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_DMAMUX_SRC_H +#define HPM_DMAMUX_SRC_H + +/* dma mux definitions */ +#define HPM_DMA_SRC_GPTMR0_0 (0x0UL) +#define HPM_DMA_SRC_GPTMR0_1 (0x1UL) +#define HPM_DMA_SRC_GPTMR0_2 (0x2UL) +#define HPM_DMA_SRC_GPTMR0_3 (0x3UL) +#define HPM_DMA_SRC_GPTMR1_0 (0x4UL) +#define HPM_DMA_SRC_GPTMR1_1 (0x5UL) +#define HPM_DMA_SRC_GPTMR1_2 (0x6UL) +#define HPM_DMA_SRC_GPTMR1_3 (0x7UL) +#define HPM_DMA_SRC_GPTMR2_0 (0x8UL) +#define HPM_DMA_SRC_GPTMR2_1 (0x9UL) +#define HPM_DMA_SRC_GPTMR2_2 (0xAUL) +#define HPM_DMA_SRC_GPTMR2_3 (0xBUL) +#define HPM_DMA_SRC_GPTMR3_0 (0xCUL) +#define HPM_DMA_SRC_GPTMR3_1 (0xDUL) +#define HPM_DMA_SRC_GPTMR3_2 (0xEUL) +#define HPM_DMA_SRC_GPTMR3_3 (0xFUL) +#define HPM_DMA_SRC_UART0_RX (0x14UL) +#define HPM_DMA_SRC_UART0_TX (0x15UL) +#define HPM_DMA_SRC_UART1_RX (0x16UL) +#define HPM_DMA_SRC_UART1_TX (0x17UL) +#define HPM_DMA_SRC_UART2_RX (0x18UL) +#define HPM_DMA_SRC_UART2_TX (0x19UL) +#define HPM_DMA_SRC_UART3_RX (0x1AUL) +#define HPM_DMA_SRC_UART3_TX (0x1BUL) +#define HPM_DMA_SRC_UART4_RX (0x1CUL) +#define HPM_DMA_SRC_UART4_TX (0x1DUL) +#define HPM_DMA_SRC_UART5_RX (0x1EUL) +#define HPM_DMA_SRC_UART5_TX (0x1FUL) +#define HPM_DMA_SRC_UART6_RX (0x20UL) +#define HPM_DMA_SRC_UART6_TX (0x21UL) +#define HPM_DMA_SRC_UART7_RX (0x22UL) +#define HPM_DMA_SRC_UART7_TX (0x23UL) +#define HPM_DMA_SRC_I2C0 (0x24UL) +#define HPM_DMA_SRC_I2C1 (0x25UL) +#define HPM_DMA_SRC_I2C2 (0x26UL) +#define HPM_DMA_SRC_I2C3 (0x27UL) +#define HPM_DMA_SRC_SPI0_RX (0x28UL) +#define HPM_DMA_SRC_SPI0_TX (0x29UL) +#define HPM_DMA_SRC_SPI1_RX (0x2AUL) +#define HPM_DMA_SRC_SPI1_TX (0x2BUL) +#define HPM_DMA_SRC_SPI2_RX (0x2CUL) +#define HPM_DMA_SRC_SPI2_TX (0x2DUL) +#define HPM_DMA_SRC_SPI3_RX (0x2EUL) +#define HPM_DMA_SRC_SPI3_TX (0x2FUL) +#define HPM_DMA_SRC_MCAN0 (0x30UL) +#define HPM_DMA_SRC_MCAN1 (0x31UL) +#define HPM_DMA_SRC_MCAN2 (0x32UL) +#define HPM_DMA_SRC_MCAN3 (0x33UL) +#define HPM_DMA_SRC_MOT_0 (0x34UL) +#define HPM_DMA_SRC_MOT_1 (0x35UL) +#define HPM_DMA_SRC_MOT_2 (0x36UL) +#define HPM_DMA_SRC_MOT_3 (0x37UL) +#define HPM_DMA_SRC_MOT_4 (0x38UL) +#define HPM_DMA_SRC_MOT_5 (0x39UL) +#define HPM_DMA_SRC_MOT_6 (0x3AUL) +#define HPM_DMA_SRC_MOT_7 (0x3BUL) +#define HPM_DMA_SRC_XPI0_RX (0x3CUL) +#define HPM_DMA_SRC_XPI0_TX (0x3DUL) +#define HPM_DMA_SRC_DAC0 (0x3EUL) +#define HPM_DMA_SRC_DAC1 (0x3FUL) +#define HPM_DMA_SRC_ACMP0 (0x40UL) +#define HPM_DMA_SRC_ACMP1 (0x41UL) + + + +#endif /* HPM_DMAMUX_SRC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_gpiom_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_gpiom_regs.h new file mode 100644 index 00000000000..85a507cc26d --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_gpiom_regs.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_GPIOM_H +#define HPM_GPIOM_H + +typedef struct { + struct { + __RW uint32_t PIN[32]; /* 0x0 - 0x7C: GPIO mananger */ + } ASSIGN[15]; +} GPIOM_Type; + + +/* Bitfield definition for register of struct array ASSIGN: PIN00 */ +/* + * LOCK (RW) + * + * lock fields in this register, lock can only be cleared by soc reset + * 0: fields can be changed + * 1: fields locked to current value, not changeable + */ +#define GPIOM_ASSIGN_PIN_LOCK_MASK (0x80000000UL) +#define GPIOM_ASSIGN_PIN_LOCK_SHIFT (31U) +#define GPIOM_ASSIGN_PIN_LOCK_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_LOCK_SHIFT) & GPIOM_ASSIGN_PIN_LOCK_MASK) +#define GPIOM_ASSIGN_PIN_LOCK_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_LOCK_MASK) >> GPIOM_ASSIGN_PIN_LOCK_SHIFT) + +/* + * HIDE (RW) + * + * pin value visibility to gpios, + * bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 + * bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + */ +#define GPIOM_ASSIGN_PIN_HIDE_MASK (0xF00U) +#define GPIOM_ASSIGN_PIN_HIDE_SHIFT (8U) +#define GPIOM_ASSIGN_PIN_HIDE_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_HIDE_SHIFT) & GPIOM_ASSIGN_PIN_HIDE_MASK) +#define GPIOM_ASSIGN_PIN_HIDE_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_HIDE_MASK) >> GPIOM_ASSIGN_PIN_HIDE_SHIFT) + +/* + * SELECT (RW) + * + * select which gpio controls chip pin, + * 0: soc gpio0; + * 2: cpu0 fastgpio + */ +#define GPIOM_ASSIGN_PIN_SELECT_MASK (0x3U) +#define GPIOM_ASSIGN_PIN_SELECT_SHIFT (0U) +#define GPIOM_ASSIGN_PIN_SELECT_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_SELECT_SHIFT) & GPIOM_ASSIGN_PIN_SELECT_MASK) +#define GPIOM_ASSIGN_PIN_SELECT_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_SELECT_MASK) >> GPIOM_ASSIGN_PIN_SELECT_SHIFT) + + + +/* PIN register group index macro definition */ +#define GPIOM_ASSIGN_PIN_PIN00 (0UL) +#define GPIOM_ASSIGN_PIN_PIN01 (1UL) +#define GPIOM_ASSIGN_PIN_PIN02 (2UL) +#define GPIOM_ASSIGN_PIN_PIN03 (3UL) +#define GPIOM_ASSIGN_PIN_PIN04 (4UL) +#define GPIOM_ASSIGN_PIN_PIN05 (5UL) +#define GPIOM_ASSIGN_PIN_PIN06 (6UL) +#define GPIOM_ASSIGN_PIN_PIN07 (7UL) +#define GPIOM_ASSIGN_PIN_PIN08 (8UL) +#define GPIOM_ASSIGN_PIN_PIN09 (9UL) +#define GPIOM_ASSIGN_PIN_PIN10 (10UL) +#define GPIOM_ASSIGN_PIN_PIN11 (11UL) +#define GPIOM_ASSIGN_PIN_PIN12 (12UL) +#define GPIOM_ASSIGN_PIN_PIN13 (13UL) +#define GPIOM_ASSIGN_PIN_PIN14 (14UL) +#define GPIOM_ASSIGN_PIN_PIN15 (15UL) +#define GPIOM_ASSIGN_PIN_PIN16 (16UL) +#define GPIOM_ASSIGN_PIN_PIN17 (17UL) +#define GPIOM_ASSIGN_PIN_PIN18 (18UL) +#define GPIOM_ASSIGN_PIN_PIN19 (19UL) +#define GPIOM_ASSIGN_PIN_PIN20 (20UL) +#define GPIOM_ASSIGN_PIN_PIN21 (21UL) +#define GPIOM_ASSIGN_PIN_PIN22 (22UL) +#define GPIOM_ASSIGN_PIN_PIN23 (23UL) +#define GPIOM_ASSIGN_PIN_PIN24 (24UL) +#define GPIOM_ASSIGN_PIN_PIN25 (25UL) +#define GPIOM_ASSIGN_PIN_PIN26 (26UL) +#define GPIOM_ASSIGN_PIN_PIN27 (27UL) +#define GPIOM_ASSIGN_PIN_PIN28 (28UL) +#define GPIOM_ASSIGN_PIN_PIN29 (29UL) +#define GPIOM_ASSIGN_PIN_PIN30 (30UL) +#define GPIOM_ASSIGN_PIN_PIN31 (31UL) + +/* ASSIGN register group index macro definition */ +#define GPIOM_ASSIGN_GPIOA (0UL) +#define GPIOM_ASSIGN_GPIOB (1UL) +#define GPIOM_ASSIGN_GPIOX (13UL) +#define GPIOM_ASSIGN_GPIOY (14UL) + + +#endif /* HPM_GPIOM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_gpiom_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_gpiom_soc_drv.h new file mode 100644 index 00000000000..01e0f0a5cd5 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_gpiom_soc_drv.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_GPIOM_SOC_DRV_H +#define HPM_GPIOM_SOC_DRV_H + +/** + * @addtogroup gpiom_interface GPIOM driver APIs + * @{ + */ + +/* @brief gpiom control module */ +typedef enum gpiom_gpio { + gpiom_soc_gpio0 = 0, + gpiom_core0_fast = 2, +} gpiom_gpio_t; + +/** + * @} + */ + +#endif /* HPM_GPIOM_SOC_DRV_H */ + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_interrupt.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_interrupt.h new file mode 100644 index 00000000000..81a657ddf17 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_interrupt.h @@ -0,0 +1,865 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_INTERRUPT_H +#define HPM_INTERRUPT_H +#include "hpm_common.h" +#include "hpm_csr_drv.h" +#include "hpm_plic_drv.h" + +/** + * @brief INTERRUPT driver APIs + * @defgroup irq_interface INTERRUPT driver APIs + * @{ + */ + +#define M_MODE 0 /*!< Machine mode */ +#define S_MODE 1 /*!< Supervisor mode */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Machine mode API: these APIs are supposed to be called at machine mode */ + +/** + * @brief Enable global IRQ with mask + * + * @param[in] mask interrupt mask to be enabaled + */ +ATTR_ALWAYS_INLINE static inline void enable_global_irq(uint32_t mask) +{ + set_csr(CSR_MSTATUS, mask); +} + +/** + * @brief Disable global IRQ with mask and return mstatus + * + * @param[in] mask interrupt mask to be disabled + * @retval current mstatus value before irq mask is disabled + */ +ATTR_ALWAYS_INLINE static inline uint32_t disable_global_irq(uint32_t mask) +{ + return read_clear_csr(CSR_MSTATUS, mask); +} + +/** + * @brief Restore global IRQ with mask + * + * @param[in] mask interrupt mask to be restored + */ +ATTR_ALWAYS_INLINE static inline void restore_global_irq(uint32_t mask) +{ + set_csr(CSR_MSTATUS, mask); +} + +/** + * @brief Enable IRQ from interrupt controller + * + */ +ATTR_ALWAYS_INLINE static inline void enable_irq_from_intc(void) +{ + set_csr(CSR_MIE, CSR_MIE_MEIE_MASK); +} + +/** + * @brief Disable IRQ from interrupt controller + * + */ +ATTR_ALWAYS_INLINE static inline void disable_irq_from_intc(void) +{ + clear_csr(CSR_MIE, CSR_MIE_MEIE_MASK); +} + +/** + * @brief Enable machine timer IRQ + */ +ATTR_ALWAYS_INLINE static inline void enable_mchtmr_irq(void) +{ + set_csr(CSR_MIE, CSR_MIE_MTIE_MASK); +} + +/** + * @brief Disable machine timer IRQ + * + */ +ATTR_ALWAYS_INLINE static inline void disable_mchtmr_irq(void) +{ + clear_csr(CSR_MIE, CSR_MIE_MTIE_MASK); +} + +/* + * CPU Machine SWI control + * + * Machine SWI (MSIP) is connected to PLICSW irq 1. + */ +#define PLICSWI 1 + +/** + * @brief Initialize software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_init_swi(void) +{ + __plic_enable_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI); +} + + +/** + * @brief Enable software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_enable_swi(void) +{ + set_csr(CSR_MIE, CSR_MIE_MSIE_MASK); +} + + +/** + * @brief Disable software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_disable_swi(void) +{ + clear_csr(CSR_MIE, CSR_MIE_MSIE_MASK); +} + + +/** + * @brief Trigger software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_trigger_swi(void) +{ + __plic_set_irq_pending(HPM_PLICSW_BASE, PLICSWI); +} + +/** + * @brief Claim software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_claim_swi(void) +{ + __plic_claim_irq(HPM_PLICSW_BASE, 0); +} + +/** + * @brief Complete software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_complete_swi(void) +{ + __plic_complete_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI); +} + +/* + * @brief Enable IRQ for machine mode + * + * @param[in] irq Interrupt number + */ +#define intc_m_enable_irq(irq) \ + intc_enable_irq(HPM_PLIC_TARGET_M_MODE, irq) + +/* + * @brief Disable IRQ for machine mode + * + * @param[in] irq Interrupt number + */ +#define intc_m_disable_irq(irq) \ + intc_disable_irq(HPM_PLIC_TARGET_M_MODE, irq) + +#define intc_m_set_threshold(threshold) \ + intc_set_threshold(HPM_PLIC_TARGET_M_MODE, threshold) + +/* + * @brief Complete IRQ for machine mode + * + * @param[in] irq Interrupt number + */ +#define intc_m_complete_irq(irq) \ + intc_complete_irq(HPM_PLIC_TARGET_M_MODE, irq) + +/* + * @brief Claim IRQ for machine mode + * + */ +#define intc_m_claim_irq() intc_claim_irq(HPM_PLIC_TARGET_M_MODE) + +/* + * @brief Enable IRQ for machine mode with priority + * + * @param[in] irq Interrupt number + * @param[in] priority Priority of interrupt + */ +#define intc_m_enable_irq_with_priority(irq, priority) \ + do { \ + intc_set_irq_priority(irq, priority); \ + intc_m_enable_irq(irq); \ + } while (0) + +/* + * @brief Enable specific interrupt + * + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number + */ +ATTR_ALWAYS_INLINE static inline void intc_enable_irq(uint32_t target, uint32_t irq) +{ + __plic_enable_irq(HPM_PLIC_BASE, target, irq); +} + +/** + * @brief Set interrupt priority + * + * @param[in] irq Interrupt number + * @param[in] priority Priority of interrupt + */ +ATTR_ALWAYS_INLINE static inline void intc_set_irq_priority(uint32_t irq, uint32_t priority) +{ + __plic_set_irq_priority(HPM_PLIC_BASE, irq, priority); +} + +/** + * @brief Disable specific interrupt + * + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number + */ +ATTR_ALWAYS_INLINE static inline void intc_disable_irq(uint32_t target, uint32_t irq) +{ + __plic_disable_irq(HPM_PLIC_BASE, target, irq); +} + +/** + * @brief Set interrupt threshold + * + * @param[in] target Target to handle specific interrupt + * @param[in] threshold Threshold of IRQ can be serviced + */ +ATTR_ALWAYS_INLINE static inline void intc_set_threshold(uint32_t target, uint32_t threshold) +{ + __plic_set_threshold(HPM_PLIC_BASE, target, threshold); +} + +/** + * @brief Claim IRQ + * + * @param[in] target Target to handle specific interrupt + * + */ +ATTR_ALWAYS_INLINE static inline uint32_t intc_claim_irq(uint32_t target) +{ + return __plic_claim_irq(HPM_PLIC_BASE, target); +} + +/** + * @brief Complete IRQ + * + * @param[in] target Target to handle specific interrupt + * @param[in] irq Specific IRQ to be completed + * + */ +ATTR_ALWAYS_INLINE static inline void intc_complete_irq(uint32_t target, uint32_t irq) +{ + __plic_complete_irq(HPM_PLIC_BASE, target, irq); +} + +/* + * Vectored based irq install and uninstall + */ +/* Machine mode */ +extern int __vector_table[]; + +extern void default_irq_entry(void); + +/** + * @brief Install ISR for certain IRQ for ram based vector table + * + * @param[in] irq Target interrupt number + * @param[in] isr Interrupt service routine + * + */ +ATTR_ALWAYS_INLINE static inline void install_isr(uint32_t irq, uint32_t isr) +{ + __vector_table[irq] = isr; +} + +/** + * @brief Uninstall ISR for certain IRQ for ram based vector table + * + * @param[in] irq Target interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) +{ + __vector_table[irq] = (int) default_irq_entry; +} + +/* + * Inline nested irq entry/exit macros + */ +/* + * @brief Save CSR + * @param[in] r Target CSR to be saved + */ +#define SAVE_CSR(r) register long __##r = read_csr(r); + +/* + * @brief Restore macro + * + * @param[in] r Target CSR to be restored + */ +#define RESTORE_CSR(r) write_csr(r, __##r); + +#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH +#define SAVE_MXSTATUS() SAVE_CSR(CSR_MXSTATUS) +#define RESTORE_MXSTATUS() RESTORE_CSR(CSR_MXSTATUS) +#else +#define SAVE_MXSTATUS() +#define RESTORE_MXSTATUS() +#endif + +#ifdef __riscv_flen +#define SAVE_FCSR() register int __fcsr = read_fcsr(); +#define RESTORE_FCSR() write_fcsr(__fcsr); +#else +#define SAVE_FCSR() +#define RESTORE_FCSR() +#endif + +#ifdef __riscv_dsp +#define SAVE_UCODE() SAVE_CSR(CSR_UCODE) +#define RESTORE_UCODE() RESTORE_CSR(CSR_UCODE) +#else +#define SAVE_UCODE() +#define RESTORE_UCODE() +#endif + +#ifdef __riscv_flen +#if __riscv_flen == 32 +/* RV32I caller registers + MCAUSE + MEPC + MSTATUS + 20 FPU caller registers */ +#define CONTEXT_REG_NUM (4 * (16 + 4 + 20)) +#else /* __riscv_flen = 64 */ +/* RV32I caller registers + MCAUSE + MEPC + MSTATUS + 20 DFPU caller */ +#define CONTEXT_REG_NUM (4*(16 + 4 + 20*2)) +#endif + +#else +/* RV32I caller registers + MCAUSE + MEPC + MSTATUS */ +#define CONTEXT_REG_NUM (4 * (16 + 4)) +#endif + +#ifdef __riscv_flen +/* + * Save FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack + */ +#if __riscv_flen == 32 +#ifdef __ICCRISCV__ +#define SAVE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fswsp ft0, 20*4\n\ + c.fswsp ft1, 21*4 \n\ + c.fswsp ft2, 22*4 \n\ + c.fswsp ft3, 23*4 \n\ + c.fswsp ft4, 24*4 \n\ + c.fswsp ft5, 25*4 \n\ + c.fswsp ft6, 26*4 \n\ + c.fswsp ft7, 27*4 \n\ + c.fswsp fa0, 28*4 \n\ + c.fswsp fa1, 29*4 \n\ + c.fswsp fa2, 30*4 \n\ + c.fswsp fa3, 31*4 \n\ + c.fswsp fa4, 32*4 \n\ + c.fswsp fa5, 33*4 \n\ + c.fswsp fa6, 34*4 \n\ + c.fswsp fa7, 35*4 \n\ + c.fswsp ft8, 36*4 \n\ + c.fswsp ft9, 37*4 \n\ + c.fswsp ft10, 38*4 \n\ + c.fswsp ft11, 39*4 \n");\ +} + +/* + * Restore FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack + */ +#define RESTORE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.flwsp ft0, 20*4\n\ + c.flwsp ft1, 21*4 \n\ + c.flwsp ft2, 22*4 \n\ + c.flwsp ft3, 23*4 \n\ + c.flwsp ft4, 24*4 \n\ + c.flwsp ft5, 25*4 \n\ + c.flwsp ft6, 26*4 \n\ + c.flwsp ft7, 27*4 \n\ + c.flwsp fa0, 28*4 \n\ + c.flwsp fa1, 29*4 \n\ + c.flwsp fa2, 30*4 \n\ + c.flwsp fa3, 31*4 \n\ + c.flwsp fa4, 32*4 \n\ + c.flwsp fa5, 33*4 \n\ + c.flwsp fa6, 34*4 \n\ + c.flwsp fa7, 35*4 \n\ + c.flwsp ft8, 36*4 \n\ + c.flwsp ft9, 37*4 \n\ + c.flwsp ft10, 38*4 \n\ + c.flwsp ft11, 39*4 \n");\ +} +#else /* __ICCRISCV__ not defined */ +#define SAVE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fswsp ft0, 20*4(sp)\n\ + c.fswsp ft1, 21*4(sp) \n\ + c.fswsp ft2, 22*4(sp) \n\ + c.fswsp ft3, 23*4(sp) \n\ + c.fswsp ft4, 24*4(sp) \n\ + c.fswsp ft5, 25*4(sp) \n\ + c.fswsp ft6, 26*4(sp) \n\ + c.fswsp ft7, 27*4(sp) \n\ + c.fswsp fa0, 28*4(sp) \n\ + c.fswsp fa1, 29*4(sp) \n\ + c.fswsp fa2, 30*4(sp) \n\ + c.fswsp fa3, 31*4(sp) \n\ + c.fswsp fa4, 32*4(sp) \n\ + c.fswsp fa5, 33*4(sp) \n\ + c.fswsp fa6, 34*4(sp) \n\ + c.fswsp fa7, 35*4(sp) \n\ + c.fswsp ft8, 36*4(sp) \n\ + c.fswsp ft9, 37*4(sp) \n\ + c.fswsp ft10, 38*4(sp) \n\ + c.fswsp ft11, 39*4(sp) \n");\ +} + +/* + * Restore FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack + */ +#define RESTORE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.flwsp ft0, 20*4(sp)\n\ + c.flwsp ft1, 21*4(sp) \n\ + c.flwsp ft2, 22*4(sp) \n\ + c.flwsp ft3, 23*4(sp) \n\ + c.flwsp ft4, 24*4(sp) \n\ + c.flwsp ft5, 25*4(sp) \n\ + c.flwsp ft6, 26*4(sp) \n\ + c.flwsp ft7, 27*4(sp) \n\ + c.flwsp fa0, 28*4(sp) \n\ + c.flwsp fa1, 29*4(sp) \n\ + c.flwsp fa2, 30*4(sp) \n\ + c.flwsp fa3, 31*4(sp) \n\ + c.flwsp fa4, 32*4(sp) \n\ + c.flwsp fa5, 33*4(sp) \n\ + c.flwsp fa6, 34*4(sp) \n\ + c.flwsp fa7, 35*4(sp) \n\ + c.flwsp ft8, 36*4(sp) \n\ + c.flwsp ft9, 37*4(sp) \n\ + c.flwsp ft10, 38*4(sp) \n\ + c.flwsp ft11, 39*4(sp) \n");\ +} +#endif +#else /*__riscv_flen == 64*/ +#ifdef __ICCRISCV__ +#define SAVE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fsdsp ft0, 20*4\n\ + c.fsdsp ft1, 22*4 \n\ + c.fsdsp ft2, 24*4 \n\ + c.fsdsp ft3, 26*4 \n\ + c.fsdsp ft4, 28*4 \n\ + c.fsdsp ft5, 30*4 \n\ + c.fsdsp ft6, 32*4 \n\ + c.fsdsp ft7, 34*4 \n\ + c.fsdsp fa0, 36*4 \n\ + c.fsdsp fa1, 38*4 \n\ + c.fsdsp fa2, 40*4 \n\ + c.fsdsp fa3, 42*4 \n\ + c.fsdsp fa4, 44*4 \n\ + c.fsdsp fa5, 46*4 \n\ + c.fsdsp fa6, 48*4 \n\ + c.fsdsp fa7, 50*4 \n\ + c.fsdsp ft8, 52*4 \n\ + c.fsdsp ft9, 54*4 \n\ + c.fsdsp ft10, 56*4 \n\ + c.fsdsp ft11, 58*4 \n");\ +} + +/* + * Restore FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack + */ +#define RESTORE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fldsp ft0, 20*4\n\ + c.fldsp ft1, 22*4 \n\ + c.fldsp ft2, 24*4 \n\ + c.fldsp ft3, 26*4 \n\ + c.fldsp ft4, 28*4 \n\ + c.fldsp ft5, 30*4 \n\ + c.fldsp ft6, 32*4 \n\ + c.fldsp ft7, 34*4 \n\ + c.fldsp fa0, 36*4 \n\ + c.fldsp fa1, 38*4 \n\ + c.fldsp fa2, 40*4 \n\ + c.fldsp fa3, 42*4 \n\ + c.fldsp fa4, 44*4 \n\ + c.fldsp fa5, 46*4 \n\ + c.fldsp fa6, 48*4 \n\ + c.fldsp fa7, 50*4 \n\ + c.fldsp ft8, 52*4 \n\ + c.fldsp ft9, 54*4 \n\ + c.fldsp ft10, 56*4 \n\ + c.fldsp ft11, 58*4 \n");\ +} +#else +#define SAVE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fsdsp ft0, 20*4(sp)\n\ + c.fsdsp ft1, 22*4(sp) \n\ + c.fsdsp ft2, 24*4(sp) \n\ + c.fsdsp ft3, 26*4(sp) \n\ + c.fsdsp ft4, 28*4(sp) \n\ + c.fsdsp ft5, 30*4(sp) \n\ + c.fsdsp ft6, 32*4(sp) \n\ + c.fsdsp ft7, 34*4(sp) \n\ + c.fsdsp fa0, 36*4(sp) \n\ + c.fsdsp fa1, 38*4(sp) \n\ + c.fsdsp fa2, 40*4(sp) \n\ + c.fsdsp fa3, 42*4(sp) \n\ + c.fsdsp fa4, 44*4(sp) \n\ + c.fsdsp fa5, 46*4(sp) \n\ + c.fsdsp fa6, 48*4(sp) \n\ + c.fsdsp fa7, 50*4(sp) \n\ + c.fsdsp ft8, 52*4(sp) \n\ + c.fsdsp ft9, 54*4(sp) \n\ + c.fsdsp ft10, 56*4(sp) \n\ + c.fsdsp ft11, 58*4(sp) \n");\ +} + +/* + * Restore FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack + */ +#define RESTORE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fldsp ft0, 20*4(sp)\n\ + c.fldsp ft1, 22*4(sp) \n\ + c.fldsp ft2, 24*4(sp) \n\ + c.fldsp ft3, 26*4(sp) \n\ + c.fldsp ft4, 28*4(sp) \n\ + c.fldsp ft5, 30*4(sp) \n\ + c.fldsp ft6, 32*4(sp) \n\ + c.fldsp ft7, 34*4(sp) \n\ + c.fldsp fa0, 36*4(sp) \n\ + c.fldsp fa1, 38*4(sp) \n\ + c.fldsp fa2, 40*4(sp) \n\ + c.fldsp fa3, 42*4(sp) \n\ + c.fldsp fa4, 44*4(sp) \n\ + c.fldsp fa5, 46*4(sp) \n\ + c.fldsp fa6, 48*4(sp) \n\ + c.fldsp fa7, 50*4(sp) \n\ + c.fldsp ft8, 52*4(sp) \n\ + c.fldsp ft9, 54*4(sp) \n\ + c.fldsp ft10, 56*4(sp) \n\ + c.fldsp ft11, 58*4(sp) \n");\ +} +#endif +#endif +#else +#define SAVE_FPU_CONTEXT() +#define RESTORE_FPU_CONTEXT() +#endif + +#ifdef __ICCRISCV__ +/** + * @brief Save the caller registers based on the RISC-V ABI specification + */ +#define SAVE_CALLER_CONTEXT() { \ + __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\ + __asm volatile("\n\ + c.swsp ra, 0*4 \n\ + c.swsp t0, 1*4 \n\ + c.swsp t1, 2*4 \n\ + c.swsp t2, 3*4 \n\ + c.swsp s0, 4*4 \n\ + c.swsp s1, 5*4 \n\ + c.swsp a0, 6*4 \n\ + c.swsp a1, 7*4 \n\ + c.swsp a2, 8*4 \n\ + c.swsp a3, 9*4 \n\ + c.swsp a4, 10*4 \n\ + c.swsp a5, 11*4 \n\ + c.swsp a6, 12*4 \n\ + c.swsp a7, 13*4 \n\ + c.swsp s2, 14*4 \n\ + c.swsp s3, 15*4 \n\ + c.swsp t3, 16*4 \n\ + c.swsp t4, 17*4 \n\ + c.swsp t5, 18*4 \n\ + c.swsp t6, 19*4"); \ + SAVE_FPU_CONTEXT(); \ +} + +/** + * @brief Restore the caller registers based on the RISC-V ABI specification + */ +#define RESTORE_CALLER_CONTEXT() { \ + __asm volatile("\n\ + c.lwsp ra, 0*4 \n\ + c.lwsp t0, 1*4 \n\ + c.lwsp t1, 2*4 \n\ + c.lwsp t2, 3*4 \n\ + c.lwsp s0, 4*4 \n\ + c.lwsp s1, 5*4 \n\ + c.lwsp a0, 6*4 \n\ + c.lwsp a1, 7*4 \n\ + c.lwsp a2, 8*4 \n\ + c.lwsp a3, 9*4 \n\ + c.lwsp a4, 10*4 \n\ + c.lwsp a5, 11*4 \n\ + c.lwsp a6, 12*4 \n\ + c.lwsp a7, 13*4 \n\ + c.lwsp s2, 14*4 \n\ + c.lwsp s3, 15*4 \n\ + c.lwsp t3, 16*4 \n\ + c.lwsp t4, 17*4 \n\ + c.lwsp t5, 18*4 \n\ + c.lwsp t6, 19*4 \n");\ + RESTORE_FPU_CONTEXT(); \ + __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\ +} +#else +/** + * @brief Save the caller registers based on the RISC-V ABI specification + */ +#define SAVE_CALLER_CONTEXT() { \ + __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\ + __asm volatile("\n\ + c.swsp ra, 0*4(sp) \n\ + c.swsp t0, 1*4(sp) \n\ + c.swsp t1, 2*4(sp) \n\ + c.swsp t2, 3*4(sp) \n\ + c.swsp s0, 4*4(sp) \n\ + c.swsp s1, 5*4(sp) \n\ + c.swsp a0, 6*4(sp) \n\ + c.swsp a1, 7*4(sp) \n\ + c.swsp a2, 8*4(sp) \n\ + c.swsp a3, 9*4(sp) \n\ + c.swsp a4, 10*4(sp) \n\ + c.swsp a5, 11*4(sp) \n\ + c.swsp a6, 12*4(sp) \n\ + c.swsp a7, 13*4(sp) \n\ + c.swsp s2, 14*4(sp) \n\ + c.swsp s3, 15*4(sp) \n\ + c.swsp t3, 16*4(sp) \n\ + c.swsp t4, 17*4(sp) \n\ + c.swsp t5, 18*4(sp) \n\ + c.swsp t6, 19*4(sp)"); \ + SAVE_FPU_CONTEXT(); \ +} + +/** + * @brief Restore the caller registers based on the RISC-V ABI specification + */ +#define RESTORE_CALLER_CONTEXT() { \ + __asm volatile("\n\ + c.lwsp ra, 0*4(sp) \n\ + c.lwsp t0, 1*4(sp) \n\ + c.lwsp t1, 2*4(sp) \n\ + c.lwsp t2, 3*4(sp) \n\ + c.lwsp s0, 4*4(sp) \n\ + c.lwsp s1, 5*4(sp) \n\ + c.lwsp a0, 6*4(sp) \n\ + c.lwsp a1, 7*4(sp) \n\ + c.lwsp a2, 8*4(sp) \n\ + c.lwsp a3, 9*4(sp) \n\ + c.lwsp a4, 10*4(sp) \n\ + c.lwsp a5, 11*4(sp) \n\ + c.lwsp a6, 12*4(sp) \n\ + c.lwsp a7, 13*4(sp) \n\ + c.lwsp s2, 14*4(sp) \n\ + c.lwsp s3, 15*4(sp) \n\ + c.lwsp t3, 16*4(sp) \n\ + c.lwsp t4, 17*4(sp) \n\ + c.lwsp t5, 18*4(sp) \n\ + c.lwsp t6, 19*4(sp) \n");\ + RESTORE_FPU_CONTEXT(); \ + __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\ +} +#endif + +#ifdef __riscv_flen +#define SAVE_FPU_STATE() { \ + __asm volatile("frcsr s1\n"); \ +} + +#define RESTORE_FPU_STATE() { \ + __asm volatile("fscsr s1\n"); \ +} +#else +#define SAVE_FPU_STATE() +#define RESTORE_FPU_STATE() +#endif + +#ifdef __riscv_dsp +/* + * Save DSP context + * NOTE: DSP context registers are stored at word offset 41 in the stack + */ +#define SAVE_DSP_CONTEXT() { \ + __asm volatile("csrrs s0, %0, x0\n" ::"i"(CSR_UCODE):); \ +} +/* + * @brief Restore DSP context + * @note DSP context registers are stored at word offset 41 in the stack + */ +#define RESTORE_DSP_CONTEXT() {\ + __asm volatile("csrw %0, s0\n" ::"i"(CSR_UCODE):); \ +} + +#else +#define SAVE_DSP_CONTEXT() +#define RESTORE_DSP_CONTEXT() +#endif + +/* + * @brief Enter Nested IRQ Handling + * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: + * MCAUSE - word offset 16 (not used in the vectored mode) + * EPC - word offset 17 + * MSTATUS = word offset 18 + * MXSTATUS = word offset 19 + */ +#define ENTER_NESTED_IRQ_HANDLING_M() { \ + __asm volatile("\n\ + csrr s2, mepc \n\ + csrr s3, mstatus \n");\ + SAVE_FPU_STATE(); \ + SAVE_DSP_CONTEXT(); \ + __asm volatile("csrsi mstatus, 8"); \ +} + +/* + * @brief Complete IRQ Handling + */ +#define COMPLETE_IRQ_HANDLING_M(irq_num) { \ + __asm volatile("csrci mstatus, 8"); \ + __asm volatile("lui a4, 0xe4200"); \ + __asm volatile("li a3, %0" : : "i" (irq_num) :); \ + __asm volatile("sw a3, 4(a4)"); \ +} + +/* + * @brief Exit Nested IRQ Handling + * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: + * MCAUSE - word offset 16 (not used in the vectored mode) + * EPC - word offset 17 + * MSTATUS = word offset 18 + * MXSTATUS = word offset 19 + */ +#define EXIT_NESTED_IRQ_HANDLING_M() { \ + __asm volatile("\n\ + csrw mstatus, s3 \n\ + csrw mepc, s2 \n");\ + RESTORE_FPU_STATE(); \ + RESTORE_DSP_CONTEXT(); \ +} + +/* @brief Nested IRQ entry macro : Save CSRs and enable global irq. */ +#define NESTED_IRQ_ENTER() \ + SAVE_CSR(CSR_MEPC) \ + SAVE_CSR(CSR_MSTATUS) \ + SAVE_MXSTATUS() \ + SAVE_FCSR() \ + SAVE_UCODE() \ + set_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); + +/* @brief Nested IRQ exit macro : Restore CSRs */ +#define NESTED_IRQ_EXIT() \ + RESTORE_CSR(CSR_MSTATUS) \ + RESTORE_CSR(CSR_MEPC) \ + RESTORE_MXSTATUS() \ + RESTORE_FCSR() \ + RESTORE_UCODE() + +#ifdef __cplusplus +#define HPM_EXTERN_C extern "C" +#else +#define HPM_EXTERN_C +#endif + +#define ISR_NAME_M(irq_num) default_isr_##irq_num +/** + * @brief Declare an external interrupt handler for machine mode + * + * @param[in] irq_num - IRQ number index + * @param[in] isr - Application IRQ handler function pointer + */ +#ifndef USE_NONVECTOR_MODE +#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ +void isr(void) __attribute__((section(".isr_vector")));\ +HPM_EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ +void ISR_NAME_M(irq_num)(void) \ +{ \ + SAVE_CALLER_CONTEXT(); \ + ENTER_NESTED_IRQ_HANDLING_M();\ + __asm volatile("la t1, %0\n\t" : : "i" (isr) : );\ + __asm volatile("jalr t1\n");\ + COMPLETE_IRQ_HANDLING_M(irq_num);\ + EXIT_NESTED_IRQ_HANDLING_M();\ + RESTORE_CALLER_CONTEXT();\ + __asm volatile("fence io, io");\ + __asm volatile("mret\n");\ +} +#else +#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ +void isr(void) __attribute__((section(".isr_vector")));\ +HPM_EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ +void ISR_NAME_M(irq_num)(void) \ +{ \ + isr(); \ +} +#endif + + +/** + * @brief Declare machine timer interrupt handler + * + * @param[in] isr - MCHTMR IRQ handler function pointer + */ +#define SDK_DECLARE_MCHTMR_ISR(isr) \ +void isr(void) __attribute__((section(".isr_vector")));\ +HPM_EXTERN_C void mchtmr_isr(void) __attribute__((section(".isr_vector"))); \ +void mchtmr_isr(void) \ +{ \ + isr();\ +} + +/** + * @brief Declare machine software interrupt handler + * + * @param[in] isr - SWI IRQ handler function pointer + */ +#define SDK_DECLARE_SWI_ISR(isr)\ +void isr(void) __attribute__((section(".isr_vector")));\ +HPM_EXTERN_C void swi_isr(void) __attribute__((section(".isr_vector"))); \ +void swi_isr(void) \ +{ \ + isr();\ +} + + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ +#endif /* HPM_INTERRUPT_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_ioc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_ioc_regs.h new file mode 100644 index 00000000000..5913db1ed7a --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_ioc_regs.h @@ -0,0 +1,259 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_IOC_H +#define HPM_IOC_H + +typedef struct { + struct { + __RW uint32_t FUNC_CTL; /* 0x0: ALT SELECT */ + __RW uint32_t PAD_CTL; /* 0x4: PAD SETTINGS */ + } PAD[456]; +} IOC_Type; + + +/* Bitfield definition for register of struct array PAD: FUNC_CTL */ +/* + * LOOP_BACK (RW) + * + * force input on + * 0: disable + * 1: enable + */ +#define IOC_PAD_FUNC_CTL_LOOP_BACK_MASK (0x10000UL) +#define IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT (16U) +#define IOC_PAD_FUNC_CTL_LOOP_BACK_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT) & IOC_PAD_FUNC_CTL_LOOP_BACK_MASK) +#define IOC_PAD_FUNC_CTL_LOOP_BACK_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_LOOP_BACK_MASK) >> IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT) + +/* + * ANALOG (RW) + * + * select analog pin in pad + * 0: disable + * 1: enable + */ +#define IOC_PAD_FUNC_CTL_ANALOG_MASK (0x100U) +#define IOC_PAD_FUNC_CTL_ANALOG_SHIFT (8U) +#define IOC_PAD_FUNC_CTL_ANALOG_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_ANALOG_SHIFT) & IOC_PAD_FUNC_CTL_ANALOG_MASK) +#define IOC_PAD_FUNC_CTL_ANALOG_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_ANALOG_MASK) >> IOC_PAD_FUNC_CTL_ANALOG_SHIFT) + +/* + * ALT_SELECT (RW) + * + * alt select + * 0: ALT0 + * 1: ALT1 + * ... + * 31:ALT31 + */ +#define IOC_PAD_FUNC_CTL_ALT_SELECT_MASK (0x1FU) +#define IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT (0U) +#define IOC_PAD_FUNC_CTL_ALT_SELECT_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT) & IOC_PAD_FUNC_CTL_ALT_SELECT_MASK) +#define IOC_PAD_FUNC_CTL_ALT_SELECT_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_ALT_SELECT_MASK) >> IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT) + +/* Bitfield definition for register of struct array PAD: PAD_CTL */ +/* + * HYS (RW) + * + * schmitt trigger enable + * 0: disable + * 1: enable + */ +#define IOC_PAD_PAD_CTL_HYS_MASK (0x1000000UL) +#define IOC_PAD_PAD_CTL_HYS_SHIFT (24U) +#define IOC_PAD_PAD_CTL_HYS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_HYS_SHIFT) & IOC_PAD_PAD_CTL_HYS_MASK) +#define IOC_PAD_PAD_CTL_HYS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_HYS_MASK) >> IOC_PAD_PAD_CTL_HYS_SHIFT) + +/* + * PRS (RW) + * + * select pull up/down internal resistance strength: + * For pull down, only have 100 Kohm resistance + * For pull up: + * 00: 100 KOhm + * 01: 47 KOhm + * 10: 22 KOhm + * 11: 22 KOhm + */ +#define IOC_PAD_PAD_CTL_PRS_MASK (0x300000UL) +#define IOC_PAD_PAD_CTL_PRS_SHIFT (20U) +#define IOC_PAD_PAD_CTL_PRS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PRS_SHIFT) & IOC_PAD_PAD_CTL_PRS_MASK) +#define IOC_PAD_PAD_CTL_PRS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PRS_MASK) >> IOC_PAD_PAD_CTL_PRS_SHIFT) + +/* + * PS (RW) + * + * pull select + * 0: pull down + * 1: pull up + */ +#define IOC_PAD_PAD_CTL_PS_MASK (0x40000UL) +#define IOC_PAD_PAD_CTL_PS_SHIFT (18U) +#define IOC_PAD_PAD_CTL_PS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PS_SHIFT) & IOC_PAD_PAD_CTL_PS_MASK) +#define IOC_PAD_PAD_CTL_PS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PS_MASK) >> IOC_PAD_PAD_CTL_PS_SHIFT) + +/* + * PE (RW) + * + * pull enable + * 0: pull disable + * 1: pull enable + */ +#define IOC_PAD_PAD_CTL_PE_MASK (0x20000UL) +#define IOC_PAD_PAD_CTL_PE_SHIFT (17U) +#define IOC_PAD_PAD_CTL_PE_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PE_SHIFT) & IOC_PAD_PAD_CTL_PE_MASK) +#define IOC_PAD_PAD_CTL_PE_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PE_MASK) >> IOC_PAD_PAD_CTL_PE_SHIFT) + +/* + * KE (RW) + * + * keeper capability enable + * 0: keeper disable + * 1: keeper enable + */ +#define IOC_PAD_PAD_CTL_KE_MASK (0x10000UL) +#define IOC_PAD_PAD_CTL_KE_SHIFT (16U) +#define IOC_PAD_PAD_CTL_KE_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_KE_SHIFT) & IOC_PAD_PAD_CTL_KE_MASK) +#define IOC_PAD_PAD_CTL_KE_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_KE_MASK) >> IOC_PAD_PAD_CTL_KE_SHIFT) + +/* + * OD (RW) + * + * open drain + * 0: open drain disable + * 1: open drain enable + */ +#define IOC_PAD_PAD_CTL_OD_MASK (0x100U) +#define IOC_PAD_PAD_CTL_OD_SHIFT (8U) +#define IOC_PAD_PAD_CTL_OD_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_OD_SHIFT) & IOC_PAD_PAD_CTL_OD_MASK) +#define IOC_PAD_PAD_CTL_OD_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_OD_MASK) >> IOC_PAD_PAD_CTL_OD_SHIFT) + +/* + * SR (RW) + * + * slew rate + * 0: Slow slew rate + * 1: Fast slew rate + */ +#define IOC_PAD_PAD_CTL_SR_MASK (0x40U) +#define IOC_PAD_PAD_CTL_SR_SHIFT (6U) +#define IOC_PAD_PAD_CTL_SR_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_SR_SHIFT) & IOC_PAD_PAD_CTL_SR_MASK) +#define IOC_PAD_PAD_CTL_SR_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_SR_MASK) >> IOC_PAD_PAD_CTL_SR_SHIFT) + +/* + * SPD (RW) + * + * additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise + * 00: Slow frequency slew rate(50Mhz) + * 01: Medium frequency slew rate(100 Mhz) + * 10: Fast frequency slew rate(150 Mhz) + * 11: Max frequency slew rate(200Mhz) + */ +#define IOC_PAD_PAD_CTL_SPD_MASK (0x30U) +#define IOC_PAD_PAD_CTL_SPD_SHIFT (4U) +#define IOC_PAD_PAD_CTL_SPD_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_SPD_SHIFT) & IOC_PAD_PAD_CTL_SPD_MASK) +#define IOC_PAD_PAD_CTL_SPD_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_SPD_MASK) >> IOC_PAD_PAD_CTL_SPD_SHIFT) + +/* + * DS (RW) + * + * drive strength + * 1.8V Mode: + * 000: 260 Ohm + * 001: 260 Ohm + * 010: 130 Ohm + * 011: 88 Ohm + * 100: 65 Ohm + * 101: 52 Ohm + * 110: 43 Ohm + * 111: 37 Ohm + * 3.3V Mode: + * 000: 157 Ohm + * 001: 157 Ohm + * 010: 78 Ohm + * 011: 53 Ohm + * 100: 39 Ohm + * 101: 32 Ohm + * 110: 26 Ohm + * 111: 23 Ohm + */ +#define IOC_PAD_PAD_CTL_DS_MASK (0x7U) +#define IOC_PAD_PAD_CTL_DS_SHIFT (0U) +#define IOC_PAD_PAD_CTL_DS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_DS_SHIFT) & IOC_PAD_PAD_CTL_DS_MASK) +#define IOC_PAD_PAD_CTL_DS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_DS_MASK) >> IOC_PAD_PAD_CTL_DS_SHIFT) + + + +/* PAD register group index macro definition */ +#define IOC_PAD_PA00 (0UL) +#define IOC_PAD_PA01 (1UL) +#define IOC_PAD_PA02 (2UL) +#define IOC_PAD_PA03 (3UL) +#define IOC_PAD_PA04 (4UL) +#define IOC_PAD_PA05 (5UL) +#define IOC_PAD_PA06 (6UL) +#define IOC_PAD_PA07 (7UL) +#define IOC_PAD_PA08 (8UL) +#define IOC_PAD_PA09 (9UL) +#define IOC_PAD_PA10 (10UL) +#define IOC_PAD_PA11 (11UL) +#define IOC_PAD_PA12 (12UL) +#define IOC_PAD_PA13 (13UL) +#define IOC_PAD_PA14 (14UL) +#define IOC_PAD_PA15 (15UL) +#define IOC_PAD_PA16 (16UL) +#define IOC_PAD_PA17 (17UL) +#define IOC_PAD_PA18 (18UL) +#define IOC_PAD_PA19 (19UL) +#define IOC_PAD_PA20 (20UL) +#define IOC_PAD_PA21 (21UL) +#define IOC_PAD_PA22 (22UL) +#define IOC_PAD_PA23 (23UL) +#define IOC_PAD_PA24 (24UL) +#define IOC_PAD_PA25 (25UL) +#define IOC_PAD_PA26 (26UL) +#define IOC_PAD_PA27 (27UL) +#define IOC_PAD_PA28 (28UL) +#define IOC_PAD_PA29 (29UL) +#define IOC_PAD_PA30 (30UL) +#define IOC_PAD_PA31 (31UL) +#define IOC_PAD_PB00 (32UL) +#define IOC_PAD_PB01 (33UL) +#define IOC_PAD_PB02 (34UL) +#define IOC_PAD_PB03 (35UL) +#define IOC_PAD_PB04 (36UL) +#define IOC_PAD_PB05 (37UL) +#define IOC_PAD_PB06 (38UL) +#define IOC_PAD_PB07 (39UL) +#define IOC_PAD_PB08 (40UL) +#define IOC_PAD_PB09 (41UL) +#define IOC_PAD_PB10 (42UL) +#define IOC_PAD_PB11 (43UL) +#define IOC_PAD_PB12 (44UL) +#define IOC_PAD_PB13 (45UL) +#define IOC_PAD_PB14 (46UL) +#define IOC_PAD_PB15 (47UL) +#define IOC_PAD_PX00 (416UL) +#define IOC_PAD_PX01 (416UL) +#define IOC_PAD_PX02 (417UL) +#define IOC_PAD_PX03 (417UL) +#define IOC_PAD_PX04 (418UL) +#define IOC_PAD_PX05 (418UL) +#define IOC_PAD_PX06 (419UL) +#define IOC_PAD_PX07 (419UL) +#define IOC_PAD_PY00 (448UL) +#define IOC_PAD_PY01 (449UL) +#define IOC_PAD_PY02 (450UL) +#define IOC_PAD_PY03 (451UL) +#define IOC_PAD_PY04 (452UL) +#define IOC_PAD_PY05 (453UL) +#define IOC_PAD_PY06 (454UL) +#define IOC_PAD_PY07 (455UL) + + +#endif /* HPM_IOC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_iomux.h new file mode 100644 index 00000000000..34efe492b21 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_iomux.h @@ -0,0 +1,777 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_IOMUX_H +#define HPM_IOMUX_H + +/* IOC_PA00_FUNC_CTL function mux definitions */ +#define IOC_PA00_FUNC_CTL_GPIO_A_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA00_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA00_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA00_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA00_FUNC_CTL_TRGM0_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA00_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PA00_FUNC_CTL_SYSCTL_CLK_OBS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA01_FUNC_CTL function mux definitions */ +#define IOC_PA01_FUNC_CTL_GPIO_A_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA01_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA01_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA01_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA01_FUNC_CTL_TRGM0_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA01_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PA01_FUNC_CTL_SYSCTL_CLK_OBS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA02_FUNC_CTL function mux definitions */ +#define IOC_PA02_FUNC_CTL_GPIO_A_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA02_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA02_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA02_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA02_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA02_FUNC_CTL_TRGM0_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA02_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PA02_FUNC_CTL_QEI1_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA02_FUNC_CTL_SYSCTL_CLK_OBS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA03_FUNC_CTL function mux definitions */ +#define IOC_PA03_FUNC_CTL_GPIO_A_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA03_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA03_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA03_FUNC_CTL_SPI3_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA03_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA03_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA03_FUNC_CTL_TRGM0_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA03_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PA03_FUNC_CTL_QEI1_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA03_FUNC_CTL_SYSCTL_CLK_OBS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA04_FUNC_CTL function mux definitions */ +#define IOC_PA04_FUNC_CTL_GPIO_A_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA04_FUNC_CTL_SPI0_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA04_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA04_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA04_FUNC_CTL_TRGM0_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA04_FUNC_CTL_RDC0_EXC_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PA04_FUNC_CTL_QEI1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA04_FUNC_CTL_QEO1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PA04_FUNC_CTL_SEI1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) +#define IOC_PA04_FUNC_CTL_JTAG_TDO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA05_FUNC_CTL function mux definitions */ +#define IOC_PA05_FUNC_CTL_GPIO_A_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA05_FUNC_CTL_GPTMR1_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA05_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA05_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA05_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA05_FUNC_CTL_TRGM0_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA05_FUNC_CTL_RDC0_EXC_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PA05_FUNC_CTL_QEI1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA05_FUNC_CTL_QEO1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PA05_FUNC_CTL_SEI1_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) +#define IOC_PA05_FUNC_CTL_JTAG_TDI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA06_FUNC_CTL function mux definitions */ +#define IOC_PA06_FUNC_CTL_GPIO_A_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA06_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA06_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA06_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA06_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA06_FUNC_CTL_TRGM0_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA06_FUNC_CTL_QEI1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA06_FUNC_CTL_QEO1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PA06_FUNC_CTL_SEI1_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) +#define IOC_PA06_FUNC_CTL_JTAG_TCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA07_FUNC_CTL function mux definitions */ +#define IOC_PA07_FUNC_CTL_GPIO_A_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA07_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA07_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA07_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA07_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA07_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA07_FUNC_CTL_TRGM0_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA07_FUNC_CTL_QEI1_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA07_FUNC_CTL_SEI1_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) +#define IOC_PA07_FUNC_CTL_JTAG_TMS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA08_FUNC_CTL function mux definitions */ +#define IOC_PA08_FUNC_CTL_GPIO_A_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA08_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA08_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA08_FUNC_CTL_SPI3_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA08_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA08_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA08_FUNC_CTL_JTAG_TRST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA09_FUNC_CTL function mux definitions */ +#define IOC_PA09_FUNC_CTL_GPIO_A_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA09_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA09_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA09_FUNC_CTL_SPI3_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA09_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA09_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA09_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA10_FUNC_CTL function mux definitions */ +#define IOC_PA10_FUNC_CTL_GPIO_A_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA10_FUNC_CTL_GPTMR0_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA10_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA10_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA10_FUNC_CTL_SPI3_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA10_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA10_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA10_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA10_FUNC_CTL_QEI1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA10_FUNC_CTL_QEO0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PA10_FUNC_CTL_SEI1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA11_FUNC_CTL function mux definitions */ +#define IOC_PA11_FUNC_CTL_GPIO_A_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA11_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA11_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA11_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA11_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA11_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA11_FUNC_CTL_QEI1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA11_FUNC_CTL_QEO0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PA11_FUNC_CTL_SEI1_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) +#define IOC_PA11_FUNC_CTL_EWDG0_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA12_FUNC_CTL function mux definitions */ +#define IOC_PA12_FUNC_CTL_GPIO_A_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA12_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA12_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA12_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA12_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA12_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA12_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA12_FUNC_CTL_RDC0_EXC_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PA12_FUNC_CTL_QEI1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA12_FUNC_CTL_QEO0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PA12_FUNC_CTL_SEI1_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA13_FUNC_CTL function mux definitions */ +#define IOC_PA13_FUNC_CTL_GPIO_A_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA13_FUNC_CTL_GPTMR1_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA13_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA13_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA13_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA13_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA13_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA13_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA13_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA13_FUNC_CTL_RDC0_EXC_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PA13_FUNC_CTL_QEI1_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA13_FUNC_CTL_SEI1_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA14_FUNC_CTL function mux definitions */ +#define IOC_PA14_FUNC_CTL_GPIO_A_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA14_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA14_FUNC_CTL_SPI3_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA14_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA14_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA14_FUNC_CTL_QEI1_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA14_FUNC_CTL_EWDG1_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA15_FUNC_CTL function mux definitions */ +#define IOC_PA15_FUNC_CTL_GPIO_A_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA15_FUNC_CTL_GPTMR0_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA15_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA15_FUNC_CTL_SPI3_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA15_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA15_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA15_FUNC_CTL_QEI1_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA15_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA16_FUNC_CTL function mux definitions */ +#define IOC_PA16_FUNC_CTL_GPIO_A_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA16_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA16_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA16_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA16_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA16_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA16_FUNC_CTL_TRGM0_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA16_FUNC_CTL_QEO0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PA16_FUNC_CTL_SEI1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA17_FUNC_CTL function mux definitions */ +#define IOC_PA17_FUNC_CTL_GPIO_A_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA17_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA17_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA17_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA17_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA17_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA17_FUNC_CTL_TRGM0_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA17_FUNC_CTL_QEO0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PA17_FUNC_CTL_SEI1_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA18_FUNC_CTL function mux definitions */ +#define IOC_PA18_FUNC_CTL_GPIO_A_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA18_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA18_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA18_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA18_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA18_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA18_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA18_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA18_FUNC_CTL_TRGM0_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA18_FUNC_CTL_QEO0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PA18_FUNC_CTL_SEI1_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA19_FUNC_CTL function mux definitions */ +#define IOC_PA19_FUNC_CTL_GPIO_A_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA19_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA19_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA19_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA19_FUNC_CTL_SPI1_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA19_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA19_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA19_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA19_FUNC_CTL_TRGM0_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA19_FUNC_CTL_SEI1_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA20_FUNC_CTL function mux definitions */ +#define IOC_PA20_FUNC_CTL_GPIO_A_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA20_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA20_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA20_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA20_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA20_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA20_FUNC_CTL_TRGM0_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA20_FUNC_CTL_QEI0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA20_FUNC_CTL_QEO0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PA20_FUNC_CTL_SEI0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA21_FUNC_CTL function mux definitions */ +#define IOC_PA21_FUNC_CTL_GPIO_A_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA21_FUNC_CTL_GPTMR3_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA21_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA21_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA21_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA21_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA21_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA21_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA21_FUNC_CTL_TRGM0_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA21_FUNC_CTL_QEI0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA21_FUNC_CTL_QEO0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PA21_FUNC_CTL_SEI0_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA22_FUNC_CTL function mux definitions */ +#define IOC_PA22_FUNC_CTL_GPIO_A_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA22_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA22_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA22_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA22_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA22_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA22_FUNC_CTL_TRGM0_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA22_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PA22_FUNC_CTL_QEI0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA22_FUNC_CTL_QEO0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PA22_FUNC_CTL_SEI0_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA23_FUNC_CTL function mux definitions */ +#define IOC_PA23_FUNC_CTL_GPIO_A_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA23_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA23_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA23_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA23_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA23_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA23_FUNC_CTL_TRGM0_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA23_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PA23_FUNC_CTL_QEI0_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA23_FUNC_CTL_SEI0_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA24_FUNC_CTL function mux definitions */ +#define IOC_PA24_FUNC_CTL_GPIO_A_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA24_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA24_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA24_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA24_FUNC_CTL_SPI1_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA24_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA24_FUNC_CTL_XPI0_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA24_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA24_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA24_FUNC_CTL_TRGM0_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA24_FUNC_CTL_QEI0_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PA25_FUNC_CTL function mux definitions */ +#define IOC_PA25_FUNC_CTL_GPIO_A_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA25_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA25_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA25_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA25_FUNC_CTL_SPI1_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA25_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA25_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA25_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA25_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA25_FUNC_CTL_TRGM0_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA25_FUNC_CTL_QEI0_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PA26_FUNC_CTL function mux definitions */ +#define IOC_PA26_FUNC_CTL_GPIO_A_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA26_FUNC_CTL_GPTMR2_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA26_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA26_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA26_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA26_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA26_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA26_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA26_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA26_FUNC_CTL_TRGM0_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA26_FUNC_CTL_QEI0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA26_FUNC_CTL_QEO0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PA26_FUNC_CTL_SEI0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) +#define IOC_PA26_FUNC_CTL_SYSCTL_CLK_OBS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA27_FUNC_CTL function mux definitions */ +#define IOC_PA27_FUNC_CTL_GPIO_A_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA27_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA27_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA27_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA27_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA27_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA27_FUNC_CTL_TRGM0_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA27_FUNC_CTL_QEI0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA27_FUNC_CTL_QEO0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PA27_FUNC_CTL_SEI0_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) +#define IOC_PA27_FUNC_CTL_SYSCTL_CLK_OBS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA28_FUNC_CTL function mux definitions */ +#define IOC_PA28_FUNC_CTL_GPIO_A_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA28_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA28_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA28_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA28_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA28_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA28_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA28_FUNC_CTL_TRGM0_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA28_FUNC_CTL_RDC0_EXC_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PA28_FUNC_CTL_QEI0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA28_FUNC_CTL_QEO0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PA28_FUNC_CTL_SEI0_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) +#define IOC_PA28_FUNC_CTL_SYSCTL_CLK_OBS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA29_FUNC_CTL function mux definitions */ +#define IOC_PA29_FUNC_CTL_GPIO_A_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA29_FUNC_CTL_GPTMR3_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA29_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA29_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA29_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA29_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA29_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA29_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA29_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA29_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA29_FUNC_CTL_TRGM0_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA29_FUNC_CTL_RDC0_EXC_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PA29_FUNC_CTL_QEI0_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA29_FUNC_CTL_SEI0_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) +#define IOC_PA29_FUNC_CTL_SYSCTL_CLK_OBS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) +#define IOC_PA29_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) + +/* IOC_PA30_FUNC_CTL function mux definitions */ +#define IOC_PA30_FUNC_CTL_GPIO_A_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA30_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA30_FUNC_CTL_SPI1_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA30_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA30_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA30_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA30_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA30_FUNC_CTL_TRGM0_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA30_FUNC_CTL_QEI0_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA30_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) +#define IOC_PA30_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) + +/* IOC_PA31_FUNC_CTL function mux definitions */ +#define IOC_PA31_FUNC_CTL_GPIO_A_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA31_FUNC_CTL_GPTMR2_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA31_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA31_FUNC_CTL_SPI1_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA31_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA31_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA31_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA31_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA31_FUNC_CTL_TRGM0_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA31_FUNC_CTL_QEI0_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA31_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) + +/* IOC_PB00_FUNC_CTL function mux definitions */ +#define IOC_PB00_FUNC_CTL_GPIO_B_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB00_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB00_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB00_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB00_FUNC_CTL_TRGM0_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PB00_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PB01_FUNC_CTL function mux definitions */ +#define IOC_PB01_FUNC_CTL_GPIO_B_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB01_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB01_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB01_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB01_FUNC_CTL_TRGM0_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PB01_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PB02_FUNC_CTL function mux definitions */ +#define IOC_PB02_FUNC_CTL_GPIO_B_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB02_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB02_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB02_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB02_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB02_FUNC_CTL_TRGM0_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PB02_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PB03_FUNC_CTL function mux definitions */ +#define IOC_PB03_FUNC_CTL_GPIO_B_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB03_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB03_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB03_FUNC_CTL_SPI2_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB03_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB03_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB03_FUNC_CTL_TRGM0_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PB03_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PB04_FUNC_CTL function mux definitions */ +#define IOC_PB04_FUNC_CTL_GPIO_B_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB04_FUNC_CTL_SPI3_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB04_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB04_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB04_FUNC_CTL_TRGM0_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PB04_FUNC_CTL_QEI1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB04_FUNC_CTL_QEO1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PB04_FUNC_CTL_SEI0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PB05_FUNC_CTL function mux definitions */ +#define IOC_PB05_FUNC_CTL_GPIO_B_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB05_FUNC_CTL_GPTMR1_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB05_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB05_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB05_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB05_FUNC_CTL_TRGM0_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PB05_FUNC_CTL_QEI1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB05_FUNC_CTL_QEO1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PB05_FUNC_CTL_SEI0_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PB06_FUNC_CTL function mux definitions */ +#define IOC_PB06_FUNC_CTL_GPIO_B_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB06_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB06_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB06_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB06_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB06_FUNC_CTL_TRGM0_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PB06_FUNC_CTL_RDC0_EXC_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PB06_FUNC_CTL_QEI1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB06_FUNC_CTL_QEO1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PB06_FUNC_CTL_SEI0_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PB07_FUNC_CTL function mux definitions */ +#define IOC_PB07_FUNC_CTL_GPIO_B_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB07_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB07_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB07_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB07_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB07_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB07_FUNC_CTL_TRGM0_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PB07_FUNC_CTL_RDC0_EXC_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PB07_FUNC_CTL_QEI1_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB07_FUNC_CTL_SEI0_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PB08_FUNC_CTL function mux definitions */ +#define IOC_PB08_FUNC_CTL_GPIO_B_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB08_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB08_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB08_FUNC_CTL_SPI2_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB08_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB08_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB08_FUNC_CTL_QEI1_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB08_FUNC_CTL_QEO1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PB08_FUNC_CTL_SEI1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) +#define IOC_PB08_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) + +/* IOC_PB09_FUNC_CTL function mux definitions */ +#define IOC_PB09_FUNC_CTL_GPIO_B_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB09_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB09_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB09_FUNC_CTL_SPI2_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB09_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB09_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB09_FUNC_CTL_QEI1_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB09_FUNC_CTL_QEO1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PB09_FUNC_CTL_SEI1_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) +#define IOC_PB09_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) + +/* IOC_PB10_FUNC_CTL function mux definitions */ +#define IOC_PB10_FUNC_CTL_GPIO_B_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB10_FUNC_CTL_GPTMR0_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB10_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB10_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB10_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB10_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB10_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB10_FUNC_CTL_QEI0_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB10_FUNC_CTL_QEO1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PB10_FUNC_CTL_SEI1_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) +#define IOC_PB10_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) + +/* IOC_PB11_FUNC_CTL function mux definitions */ +#define IOC_PB11_FUNC_CTL_GPIO_B_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB11_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB11_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB11_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB11_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB11_FUNC_CTL_QEI0_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB11_FUNC_CTL_SEI1_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PB12_FUNC_CTL function mux definitions */ +#define IOC_PB12_FUNC_CTL_GPIO_B_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB12_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB12_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB12_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB12_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB12_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB12_FUNC_CTL_TRGM0_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PB12_FUNC_CTL_QEI0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB12_FUNC_CTL_QEO1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PB12_FUNC_CTL_SEI0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PB13_FUNC_CTL function mux definitions */ +#define IOC_PB13_FUNC_CTL_GPIO_B_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB13_FUNC_CTL_GPTMR1_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB13_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB13_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB13_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB13_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB13_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB13_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB13_FUNC_CTL_TRGM0_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PB13_FUNC_CTL_QEI0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB13_FUNC_CTL_QEO1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PB13_FUNC_CTL_SEI0_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PB14_FUNC_CTL function mux definitions */ +#define IOC_PB14_FUNC_CTL_GPIO_B_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB14_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB14_FUNC_CTL_SPI2_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB14_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB14_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB14_FUNC_CTL_TRGM0_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PB14_FUNC_CTL_RDC0_EXC_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PB14_FUNC_CTL_QEI0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB14_FUNC_CTL_QEO1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PB14_FUNC_CTL_SEI0_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PB15_FUNC_CTL function mux definitions */ +#define IOC_PB15_FUNC_CTL_GPIO_B_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB15_FUNC_CTL_GPTMR0_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB15_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB15_FUNC_CTL_SPI2_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB15_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB15_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB15_FUNC_CTL_TRGM0_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PB15_FUNC_CTL_RDC0_EXC_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PB15_FUNC_CTL_QEI0_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB15_FUNC_CTL_SEI0_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PX00_FUNC_CTL function mux definitions */ +#define IOC_PX00_FUNC_CTL_GPIO_X_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX00_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PX00_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PX00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PX00_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX01_FUNC_CTL function mux definitions */ +#define IOC_PX01_FUNC_CTL_GPIO_X_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX01_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PX01_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PX01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PX01_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX02_FUNC_CTL function mux definitions */ +#define IOC_PX02_FUNC_CTL_GPIO_X_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX02_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PX02_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PX02_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PX02_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PX02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PX02_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX03_FUNC_CTL function mux definitions */ +#define IOC_PX03_FUNC_CTL_GPIO_X_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX03_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PX03_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PX03_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PX03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PX03_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX04_FUNC_CTL function mux definitions */ +#define IOC_PX04_FUNC_CTL_GPIO_X_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX04_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PX04_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PX04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PX04_FUNC_CTL_XPI0_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX05_FUNC_CTL function mux definitions */ +#define IOC_PX05_FUNC_CTL_GPIO_X_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX05_FUNC_CTL_GPTMR2_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PX05_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PX05_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PX05_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PX05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PX05_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX06_FUNC_CTL function mux definitions */ +#define IOC_PX06_FUNC_CTL_GPIO_X_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX06_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PX06_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PX06_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PX06_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PX06_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX07_FUNC_CTL function mux definitions */ +#define IOC_PX07_FUNC_CTL_GPIO_X_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX07_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PX07_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PX07_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PX07_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PX07_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PY00_FUNC_CTL function mux definitions */ +#define IOC_PY00_FUNC_CTL_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY00_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY00_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY00_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PY00_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PY00_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PY00_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) + +/* IOC_PY01_FUNC_CTL function mux definitions */ +#define IOC_PY01_FUNC_CTL_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY01_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY01_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY01_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PY01_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PY01_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PY01_FUNC_CTL_EWDG0_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) +#define IOC_PY01_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) + +/* IOC_PY02_FUNC_CTL function mux definitions */ +#define IOC_PY02_FUNC_CTL_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY02_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY02_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PY02_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY02_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PY02_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PY02_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PY02_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PY02_FUNC_CTL_EWDG1_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) +#define IOC_PY02_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) + +/* IOC_PY03_FUNC_CTL function mux definitions */ +#define IOC_PY03_FUNC_CTL_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY03_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY03_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PY03_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY03_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PY03_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PY03_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PY03_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PY04_FUNC_CTL function mux definitions */ +#define IOC_PY04_FUNC_CTL_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY04_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY04_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY04_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PY04_FUNC_CTL_TRGM0_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PY05_FUNC_CTL function mux definitions */ +#define IOC_PY05_FUNC_CTL_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY05_FUNC_CTL_GPTMR3_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY05_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY05_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY05_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PY05_FUNC_CTL_TRGM0_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PY05_FUNC_CTL_EWDG0_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PY06_FUNC_CTL function mux definitions */ +#define IOC_PY06_FUNC_CTL_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY06_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY06_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PY06_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY06_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PY06_FUNC_CTL_TRGM0_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PY06_FUNC_CTL_EWDG1_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PY07_FUNC_CTL function mux definitions */ +#define IOC_PY07_FUNC_CTL_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY07_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY07_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PY07_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY07_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PY07_FUNC_CTL_TRGM0_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + + +#endif /* HPM_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_l1c_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_l1c_drv.c new file mode 100644 index 00000000000..c55600dcdcc --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_l1c_drv.c @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2021-2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_l1c_drv.h" +#include + + +#define ASSERT_ADDR_SIZE(addr, size) do { \ + assert(address % HPM_L1C_CACHELINE_SIZE == 0); \ + assert(size % HPM_L1C_CACHELINE_SIZE == 0); \ + } while (0) + +static void l1c_op(uint8_t opcode, uint32_t address, uint32_t size) +{ + register uint32_t i; + register uint32_t next_address; + register uint32_t tmp; + register uint32_t csr; + + csr = read_clear_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); + +#define CCTL_VERSION (3U << 18) + + if ((read_csr(CSR_MMSC_CFG) & CCTL_VERSION)) { + l1c_cctl_address(address); + next_address = address; + while ((next_address < (address + size)) && (next_address >= address)) { + l1c_cctl_cmd(opcode); + next_address = l1c_cctl_get_address(); + } + } else { + for (i = 0, tmp = 0; tmp < size; i++) { + l1c_cctl_address_cmd(opcode, address + i * HPM_L1C_CACHELINE_SIZE); + tmp += HPM_L1C_CACHELINE_SIZE; + } + } + + write_csr(CSR_MSTATUS, csr); +} + +void l1c_dc_enable(void) +{ + if (!l1c_dc_is_enabled()) { + clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_DC_WAROUND_MASK); + set_csr(CSR_MCACHE_CTL, +#ifdef L1C_DC_WAROUND_VALUE + HPM_MCACHE_CTL_DC_WAROUND(L1C_DC_WAROUND_VALUE) | +#endif + HPM_MCACHE_CTL_DPREF_EN_MASK + | HPM_MCACHE_CTL_DC_EN_MASK); + } +} + +void l1c_dc_disable(void) +{ + if (l1c_dc_is_enabled()) { + clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_DC_EN_MASK); + } +} + +void l1c_ic_enable(void) +{ + if (!l1c_ic_is_enabled()) { + set_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_IPREF_EN_MASK + | HPM_MCACHE_CTL_CCTL_SUEN_MASK + | HPM_MCACHE_CTL_IC_EN_MASK); + } +} + +void l1c_ic_disable(void) +{ + if (l1c_ic_is_enabled()) { + clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_IC_EN_MASK); + } +} + +void l1c_fence_i(void) +{ + __asm("fence.i"); +} + +void l1c_dc_invalidate_all(void) +{ + l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_INVAL_ALL); +} + +void l1c_dc_writeback_all(void) +{ + l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_WB_ALL); +} + +void l1c_dc_flush_all(void) +{ + l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_WBINVAL_ALL); +} + +void l1c_dc_fill_lock(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_LOCK, address, size); +} + +void l1c_dc_invalidate(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_INVAL, address, size); +} + +void l1c_dc_writeback(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_WB, address, size); +} + +void l1c_dc_flush(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_WBINVAL, address, size); +} + +void l1c_ic_invalidate(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1I_VA_INVAL, address, size); +} + +void l1c_ic_fill_lock(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1I_VA_LOCK, address, size); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_l1c_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_l1c_drv.h new file mode 100644 index 00000000000..e3034e6e831 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_l1c_drv.h @@ -0,0 +1,485 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_L1_CACHE_H +#define _HPM_L1_CACHE_H +#include "hpm_common.h" +#include "hpm_csr_drv.h" +#include "hpm_soc.h" + +/** + * + * @brief L1CACHE driver APIs + * @defgroup l1cache_interface L1CACHE driver APIs + * @{ + */ + +/* cache size is 16KB */ +#define HPM_L1C_CACHE_SIZE (uint32_t)(16 * SIZE_1KB) +#define HPM_L1C_ICACHE_SIZE (HPM_L1C_CACHE_SIZE) +#define HPM_L1C_DCACHE_SIZE (HPM_L1C_CACHE_SIZE) +/* cache line size is 32B */ +#define HPM_L1C_CACHELINE_SIZE (32) +/* cache way is 128 */ +#define HPM_L1C_CACHELINES_PER_WAY (128) + +/* mcache_ctl register */ +/* + * Controls if the instruction cache is enabled or not. + * + * 0 I-Cache is disabled + * 1 I-Cache is enabled + */ +#define HPM_MCACHE_CTL_IC_EN_SHIFT (0UL) +#define HPM_MCACHE_CTL_IC_EN_MASK (1UL << HPM_MCACHE_CTL_IC_EN_SHIFT) +#define HPM_MCACHE_CTL_IC_EN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IC_EN_SHIFT) & HPM_MCACHE_CTL_IC_EN_MASK) + +/* + * Controls if the data cache is enabled or not. + * + * 0 D-Cache is disabled + * 1 D-Cache is enabled + */ +#define HPM_MCACHE_CTL_DC_EN_SHIFT (1UL) +#define HPM_MCACHE_CTL_DC_EN_MASK (1UL << HPM_MCACHE_CTL_DC_EN_SHIFT) +#define HPM_MCACHE_CTL_DC_EN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_EN_SHIFT) & HPM_MCACHE_CTL_DC_EN_MASK) + +/* + * Parity/ECC error checking enable control for the instruction cache. + * + * 0 Disable parity/ECC + * 1 Reserved + * 2 Generate exceptions only on uncorrectable parity/ECC errors + * 3 Generate exceptions on any type of parity/ECC errors + */ +#define HPM_MCACHE_CTL_IC_ECCEN_SHIFT (0x2UL) +#define HPM_MCACHE_CTL_IC_ECCEN_MASK (0x3UL << HPM_MCACHE_CTL_IC_ECCEN_SHIFT) +#define HPM_MCACHE_CTL_IC_ECCEN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IC_ECCEN_SHIFT) & HPM_MCACHE_CTL_IC_ECCEN_MASK) + +/* + * + * Parity/ECC error checking enable control for the data cache. + * + * 0 Disable parity/ECC + * 1 Reserved + * 2 Generate exceptions only on uncorrectable parity/ECC errors + * 3 Generate exceptions on any type of parity/ECC errors + */ +#define HPM_MCACHE_CTL_DC_ECCEN_SHIFT (0x4UL) +#define HPM_MCACHE_CTL_DC_ECCEN_MASK (0x3UL << HPM_MCACHE_CTL_DC_ECCEN_SHIFT) +#define HPM_MCACHE_CTL_DC_ECCEN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_ECCEN_SHIFT) & HPM_MCACHE_CTL_DC_ECCEN_MASK) + +/* + * + * Controls diagnostic accesses of ECC codes of the instruction cache RAMs. + * It is set to enable CCTL operations to access the ECC codes. This bit + * can be set for injecting ECC errors to test the ECC handler. + * + * 0 Disable diagnostic accesses of ECC codes + * 1 Enable diagnostic accesses of ECC codes + */ +#define HPM_MCACHE_CTL_IC_RWECC_SHIFT (0x6UL) +#define HPM_MCACHE_CTL_IC_RWECC_MASK (0x1UL << HPM_MCACHE_CTL_IC_RWECC_SHIFT) +#define HPM_MCACHE_CTL_IC_RWECC(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IC_RWECC_SHIFT) & HPM_MCACHE_CTL_IC_RWECC_MASK) + +/* + * + * Controls diagnostic accesses of ECC codes of the data cache RAMs. It is + * set to enable CCTL operations to access the ECC codes. This bit can be + * set for injecting + * + * ECC errors to test the ECC handler. + * 0 Disable diagnostic accesses of ECC codes + * 1 Enable diagnostic accesses of ECC codes + */ +#define HPM_MCACHE_CTL_DC_RWECC_SHIFT (0x7UL) +#define HPM_MCACHE_CTL_DC_RWECC_MASK (0x1UL << HPM_MCACHE_CTL_DC_RWECC_SHIFT) +#define HPM_MCACHE_CTL_DC_RWECC(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_RWECC_SHIFT) & HPM_MCACHE_CTL_DC_RWECC_MASK) + +/* + * Enable bit for Superuser-mode and User-mode software to access + * ucctlbeginaddr and ucctlcommand CSRs. + * + * 0 Disable ucctlbeginaddr and ucctlcommand accesses in S/U mode + * 1 Enable ucctlbeginaddr and ucctlcommand accesses in S/U mode + */ +#define HPM_MCACHE_CTL_CCTL_SUEN_SHIFT (0x8UL) +#define HPM_MCACHE_CTL_CCTL_SUEN_MASK (0x1UL << HPM_MCACHE_CTL_CCTL_SUEN_SHIFT) +#define HPM_MCACHE_CTL_CCTL_SUEN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_CCTL_SUEN_SHIFT) & HPM_MCACHE_CTL_CCTL_SUEN_MASK) + +/* + * This bit controls hardware prefetch for instruction fetches to cacheable + * memory regions when I-Cache size is not 0. + * + * 0 Disable hardware prefetch on instruction fetches + * 1 Enable hardware prefetch on instruction fetches + */ +#define HPM_MCACHE_CTL_IPREF_EN_SHIFT (0x9UL) +#define HPM_MCACHE_CTL_IPREF_EN_MASK (0x1UL << HPM_MCACHE_CTL_IPREF_EN_SHIFT) +#define HPM_MCACHE_CTL_IPREF_EN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IPREF_EN_SHIFT) & HPM_MCACHE_CTL_IPREF_EN_MASK) + +/* + * This bit controls hardware prefetch for load/store accesses to cacheable + * memory regions when D-Cache size is not 0. + * + * 0 Disable hardware prefetch on load/store memory accesses. + * 1 Enable hardware prefetch on load/store memory accesses. + */ +#define HPM_MCACHE_CTL_DPREF_EN_SHIFT (0x10UL) +#define HPM_MCACHE_CTL_DPREF_EN_MASK (0x1UL << HPM_MCACHE_CTL_DPREF_EN_SHIFT) +#define HPM_MCACHE_CTL_DPREF_EN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DPREF_EN_SHIFT) & HPM_MCACHE_CTL_DPREF_EN_MASK) + +/* + * I-Cache miss allocation filling policy Value Meaning + * + * 0 Cache line data is returned critical (double) word first + * 1 Cache line data is returned the lowest address (double) word first + */ +#define HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT (0x11UL) +#define HPM_MCACHE_CTL_IC_FIRST_WORD_MASK (0x1UL << HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT) +#define HPM_MCACHE_CTL_IC_FIRST_WORD(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT) & HPM_MCACHE_CTL_IC_FIRST_WORD_MASK) + +/* + * D-Cache miss allocation filling policy + * + * 0 Cache line data is returned critical (double) word first + * 1 Cache line data is returned the lowest address (double) word first + */ +#define HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT (0x12UL) +#define HPM_MCACHE_CTL_DC_FIRST_WORD_MASK (0x1UL << HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT) +#define HPM_MCACHE_CTL_DC_FIRST_WORD(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT) & HPM_MCACHE_CTL_DC_FIRST_WORD_MASK) + +/* + * D-Cache Write-Around threshold + * + * 0 Disables streaming. All cacheable write misses allocate a cache line + * according to PMA settings. + * 1 Override PMA setting and do not allocate D-Cache entries after + * consecutive stores to 4 cache lines. + * 2 Override PMA setting and do not allocate D-Cache entries after + * consecutive stores to 64 cache lines. + * 3 Override PMA setting and do not allocate D-Cache entries after + * consecutive stores to 128 cache lines. + */ +#define HPM_MCACHE_CTL_DC_WAROUND_SHIFT (0x13UL) +#define HPM_MCACHE_CTL_DC_WAROUND_MASK (0x3UL << HPM_MCACHE_CTL_DC_WAROUND_SHIFT) +#define HPM_MCACHE_CTL_DC_WAROUND(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_WAROUND_SHIFT) & HPM_MCACHE_CTL_DC_WAROUND_MASK) + +/* CCTL command list */ +#define HPM_L1C_CCTL_CMD_L1D_VA_INVAL (0UL) +#define HPM_L1C_CCTL_CMD_L1D_VA_WB (1UL) +#define HPM_L1C_CCTL_CMD_L1D_VA_WBINVAL (2UL) +#define HPM_L1C_CCTL_CMD_L1D_VA_LOCK (3UL) +#define HPM_L1C_CCTL_CMD_L1D_VA_UNLOCK (4UL) +#define HPM_L1C_CCTL_CMD_L1D_WBINVAL_ALL (6UL) +#define HPM_L1C_CCTL_CMD_L1D_WB_ALL (7UL) + +#define HPM_L1C_CCTL_CMD_L1I_VA_INVAL (8UL) +#define HPM_L1C_CCTL_CMD_L1I_VA_LOCK (11UL) +#define HPM_L1C_CCTL_CMD_L1I_VA_UNLOCK (12UL) + +#define HPM_L1C_CCTL_CMD_L1D_IX_INVAL (16UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_WB (17UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_WBINVAL (18UL) + +#define HPM_L1C_CCTL_CMD_L1D_IX_RTAG (19UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_RDATA (20UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_WTAG (21UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_WDATA (22UL) + +#define HPM_L1C_CCTL_CMD_L1D_INVAL_ALL (23UL) + +#define HPM_L1C_CCTL_CMD_L1I_IX_INVAL (24UL) +#define HPM_L1C_CCTL_CMD_L1I_IX_RTAG (27UL) +#define HPM_L1C_CCTL_CMD_L1I_IX_RDATA (28UL) +#define HPM_L1C_CCTL_CMD_L1I_IX_WTAG (29UL) +#define HPM_L1C_CCTL_CMD_L1I_IX_WDATA (30UL) + +#define HPM_L1C_CCTL_CMD_SUCCESS (1UL) +#define HPM_L1C_CCTL_CMD_FAIL (0UL) + +#ifdef __cplusplus +extern "C" { +#endif +/* get cache control register value */ +__attribute__((always_inline)) static inline uint32_t l1c_get_control(void) +{ + return read_csr(CSR_MCACHE_CTL); +} + +__attribute__((always_inline)) static inline bool l1c_dc_is_enabled(void) +{ + return l1c_get_control() & HPM_MCACHE_CTL_DC_EN_MASK; +} + +__attribute__((always_inline)) static inline bool l1c_ic_is_enabled(void) +{ + return l1c_get_control() & HPM_MCACHE_CTL_IC_EN_MASK; +} + +/* mcctlbeginaddress register bitfield layout for CCTL IX type command */ +#define HPM_MCCTLBEGINADDR_OFFSET_SHIFT (2UL) +#define HPM_MCCTLBEGINADDR_OFFSET_MASK ((uint32_t) 0xF << HPM_MCCTLBEGINADDR_OFFSET_SHIFT) +#define HPM_MCCTLBEGINADDR_OFFSET(x) \ + (uint32_t)(((x) << HPM_MCCTLBEGINADDR_OFFSET_SHIFT) & HPM_MCCTLBEGINADDR_OFFSET_MASK) +#define HPM_MCCTLBEGINADDR_INDEX_SHIFT (6UL) +#define HPM_MCCTLBEGINADDR_INDEX_MASK ((uint32_t) 0x3F << HPM_MCCTLBEGINADDR_INDEX_SHIFT) +#define HPM_MCCTLBEGINADDR_INDEX(x) \ + (uint32_t)(((x) << HPM_MCCTLBEGINADDR_INDEX_SHIFT) & HPM_MCCTLBEGINADDR_INDEX_MASK) +#define HPM_MCCTLBEGINADDR_WAY_SHIFT (13UL) +#define HPM_MCCTLBEGINADDR_WAY_MASK ((uint32_t) 0x3 << HPM_MCCTLBEGINADDR_WAY_SHIFT) +#define HPM_MCCTLBEGINADDR_WAY(x) \ + (uint32_t)(((x) << HPM_MCCTLBEGINADDR_WAY_SHIFT) & HPM_MCCTLBEGINADDR_WAY_MASK) + +/* send IX command */ +__attribute__((always_inline)) static inline void l1c_cctl_address(uint32_t address) +{ + write_csr(CSR_MCCTLBEGINADDR, address); +} + +/* send command */ +__attribute__((always_inline)) static inline void l1c_cctl_cmd(uint8_t cmd) +{ + write_csr(CSR_MCCTLCOMMAND, cmd); +} + +__attribute__((always_inline)) static inline uint32_t l1c_cctl_get_address(void) +{ + return read_csr(CSR_MCCTLBEGINADDR); +} + +/* send IX command */ +__attribute__((always_inline)) static inline + void l1c_cctl_address_cmd(uint8_t cmd, uint32_t address) +{ + write_csr(CSR_MCCTLBEGINADDR, address); + write_csr(CSR_MCCTLCOMMAND, cmd); +} + +#define HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT (2UL) +#define HPM_MCCTLDATA_I_TAG_ADDRESS_MASK (uint32_t)(0XFFFFF << HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT) +#define HPM_MCCTLDATA_I_TAG_ADDRESS(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT) & HPM_MCCTLDATA_I_TAG_ADDRESS_MASK) + +#define HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT (29UL) +#define HPM_MCCTLDATA_I_TAG_LOCK_DUP_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT) +#define HPM_MCCTLDATA_I_TAG_LOCK_DUP(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT) & HPM_MCCTLDATA_I_TAG_LOCK_DUP_MASK) + +#define HPM_MCCTLDATA_I_TAG_LOCK_SHIFT (30UL) +#define HPM_MCCTLDATA_I_TAG_LOCK_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_LOCK_SHIFT) +#define HPM_MCCTLDATA_I_TAG_LOCK(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_LOCK_SHIFT) & HPM_MCCTLDATA_I_TAG_LOCK_MASK) + +#define HPM_MCCTLDATA_I_TAG_VALID_SHIFT (31UL) +#define HPM_MCCTLDATA_I_TAG_VALID_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_VALID_SHIFT) +#define HPM_MCCTLDATA_I_TAG_VALID(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_VALID_SHIFT) & HPM_MCCTLDATA_I_TAG_VALID_MASK) + +#define HPM_MCCTLDATA_D_TAG_MESI_SHIFT (0UL) +#define HPM_MCCTLDATA_D_TAG_MESI_MASK (uint32_t)(0x3 << HPM_MCCTLDATA_D_TAG_MESI_SHIFT) +#define HPM_MCCTLDATA_D_TAG_MESI(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_MESI_SHIFT) & HPM_MCCTLDATA_D_TAG_MESI_MASK) + +#define HPM_MCCTLDATA_D_TAG_LOCK_SHIFT (3UL) +#define HPM_MCCTLDATA_D_TAG_LOCK_MASK (uint32_t)(0x1 << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) +#define HPM_MCCTLDATA_D_TAG_LOCK(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) & HPM_MCCTLDATA_D_TAG_LOCK_MASK) + +#define HPM_MCCTLDATA_D_TAG_TAG_SHIFT (4UL) +#define HPM_MCCTLDATA_D_TAG_TAG_MASK (uint32_t)(0xFFFF << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) +#define HPM_MCCTLDATA_D_TAG_TAG(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_TAG_SHIFT) & HPM_MCCTLDATA_D_TAG_TAG_MASK) + +/* + * @brief Cache control command read address + * + * Send IX read tag/data cmd + * @param[in] cmd Command code + * @param[in] address Target address + * @param[in] ecc_data ECC value + * @return data read + */ +ATTR_ALWAYS_INLINE static inline + uint32_t l1c_cctl_address_cmd_read(uint8_t cmd, uint32_t address, uint32_t *ecc_data) +{ + write_csr(CSR_MCCTLBEGINADDR, address); + write_csr(CSR_MCCTLCOMMAND, cmd); + *ecc_data = read_csr(CSR_MECC_CODE); + return read_csr(CSR_MCCTLDATA); +} + +/* + * @brief Cache control command write address + * + * Send IX write tag/data cmd + * @param[in] cmd Command code + * @param[in] address Target address + * @param[in] data Data to be written + * @param[in] ecc_data ECC of data + */ +ATTR_ALWAYS_INLINE static inline + void l1c_cctl_address_cmd_write(uint8_t cmd, uint32_t address, uint32_t data, uint32_t ecc_data) +{ + write_csr(CSR_MCCTLBEGINADDR, address); + write_csr(CSR_MCCTLCOMMAND, cmd); + write_csr(CSR_MCCTLDATA, data); + write_csr(CSR_MECC_CODE, ecc_data); +} + +#define HPM_L1C_CFG_SET_SHIFT (0UL) +#define HPM_L1C_CFG_SET_MASK (uint32_t)(0x7 << HPM_L1C_CFG_SET_SHIFT) +#define HPM_L1C_CFG_WAY_SHIFT (3UL) +#define HPM_L1C_CFG_WAY_MASK (uint32_t)(0x7 << HPM_L1C_CFG_WAY_SHIFT) +#define HPM_L1C_CFG_SIZE_SHIFT (6UL) +#define HPM_L1C_CFG_SIZE_MASK (uint32_t)(0x7 << HPM_L1C_CFG_SIZE_SHIFT) +#define HPM_L1C_CFG_LOCK_SHIFT (9UL) +#define HPM_L1C_CFG_LOCK_MASK (uint32_t)(0x1 << HPM_L1C_CFG_LOCK_SHIFT) +#define HPM_L1C_CFG_ECC_SHIFT (10UL) +#define HPM_L1C_CFG_ECC_MASK (uint32_t)(0x3 << HPM_L1C_CFG_ECC_SHIFT) +#define HPM_L1C_CFG_LMB_SHIFT (12UL) +#define HPM_L1C_CFG_LMB_MASK (uint32_t)(0x7 << HPM_L1C_CFG_LMB_SHIFT) +#define HPM_L1C_CFG_LM_SIZE_SHIFT (15UL) +#define HPM_L1C_CFG_LM_SIZE_MASK (uint32_t)(0x1F << HPM_L1C_CFG_LM_SIZE_SHIFT) +#define HPM_L1C_CFG_LM_ECC_SHIFT (21UL) +#define HPM_L1C_CFG_LM_ECC_MASK (uint32_t)(0x3 << HPM_L1C_CFG_LM_ECC_SHIFT) +#define HPM_L1C_CFG_SETH_SHIFT (24UL) +#define HPM_L1C_CFG_SETH_MASK (uint32_t)(0x1 << HPM_L1C_CFG_SETH_SHIFT) + +/** + * @brief Align down based on cache line size + */ +#define HPM_L1C_CACHELINE_ALIGN_DOWN(n) ((uint32_t)(n) & ~(HPM_L1C_CACHELINE_SIZE - 1U)) + +/** + * @brief Align up based on cache line size + */ +#define HPM_L1C_CACHELINE_ALIGN_UP(n) HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)(n) + HPM_L1C_CACHELINE_SIZE - 1U) + +/** + * @brief Get I-cache configuration + * + * @return I-cache config register + */ +ATTR_ALWAYS_INLINE static inline uint32_t l1c_ic_get_config(void) +{ + return read_csr(CSR_MICM_CFG); +} + +/** + * @brief Get D-cache configuration + * + * @return D-cache config register + */ +ATTR_ALWAYS_INLINE static inline uint32_t l1c_dc_get_config(void) +{ + return read_csr(CSR_MDCM_CFG); +} + +/* + * @brief D-cache disable + */ +void l1c_dc_disable(void); + +/* + * @brief D-cache enable + */ +void l1c_dc_enable(void); + +/* + * @brief D-cache invalidate by address + * @param[in] address Start address to be invalidated + * @param[in] size Size of memory to be invalidated + */ +void l1c_dc_invalidate(uint32_t address, uint32_t size); + +/* + * @brief D-cache writeback by address + * @param[in] address Start address to be writtenback + * @param[in] size Size of memory to be writtenback + */ +void l1c_dc_writeback(uint32_t address, uint32_t size); + +/* + * @brief D-cache invalidate and writeback by address + * @param[in] address Start address to be invalidated and writtenback + * @param[in] size Size of memory to be invalidted and writtenback + */ +void l1c_dc_flush(uint32_t address, uint32_t size); + +/* + * @brief D-cache fill and lock by address + * @param[in] address Start address to be filled and locked + * @param[in] size Size of memory to be filled and locked + */ +void l1c_dc_fill_lock(uint32_t address, uint32_t size); + +/* + * @brief I-cache disable + */ +void l1c_ic_disable(void); + +/* + * @brief I-cache enable + */ +void l1c_ic_enable(void); + +/* + * @brief I-cache invalidate by address + * @param[in] address Start address to be invalidated + * @param[in] size Size of memory to be invalidated + */ +void l1c_ic_invalidate(uint32_t address, uint32_t size); + +/* + * @brief I-cache fill and lock by address + * @param[in] address Start address to be locked + * @param[in] size Size of memory to be locked + */ +void l1c_ic_fill_lock(uint32_t address, uint32_t size); + +/* + * @brief Invalidate all icache and writeback all dcache + */ +void l1c_fence_i(void); + +/* + * @brief Invalidate all d-cache + */ +void l1c_dc_invalidate_all(void); + +/* + * @brief Writeback all d-cache + */ +void l1c_dc_writeback_all(void); + +/* + * @brief Flush all d-cache + */ +void l1c_dc_flush_all(void); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* _HPM_L1_CACHE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_mcan_soc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_mcan_soc.h new file mode 100644 index 00000000000..41fd0fd5ae5 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_mcan_soc.h @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_MCAN_SOC_H +#define HPM_MCAN_SOC_H + +#include +#include "hpm_mcan_regs.h" +#include "hpm_soc.h" + +#define MCAN_SOC_TSU_SRC_TWO_STAGES (1U) + +#define HPM_MCAN_EXT_TBSEL_NUM (4U) +#define HPM_MCAN_TBSEL_BASE (0xF02FF000UL) +#define HPM_MCAN_TBSEL (*(volatile uint32_t *)HPM_MCAN_TBSEL_BASE) +#define HPM_MCAN_TBSEL_BITWDITH (6U) +#define HPM_MCAN_TBSEL_MASK ((1UL << HPM_MCAN_TBSEL_BITWDITH) - 1UL) +#define HPM_MCAN_TBSEL0_SHIFT (8U) + +/** + * @brief MCAN MSG BUF base address (AHB_RAM) + */ +#define MCAN_MSG_BUF_BASE (0xF0400000UL) +#define MCAN_MSG_BUF_SIZE_IN_WORDS (640U) +#define MCAN_IP_SLOT_SIZE (0x4000U) + +/** + * @brief TSU External Timebase Sources + */ +#define MCAN_TSU_EXT_TIMEBASE_SRC_MIN (0U) +#define MCAN_TSU_EXT_TIMEBASE_SRC_TBSEL_0 (MCAN_TSU_EXT_TIMEBASE_SRC_MIN) +#define MCAN_TSU_EXT_TIMEBASE_SRC_TBSEL_1 (1U) +#define MCAN_TSU_EXT_TIMEBASE_SRC_TBSEL_2 (2U) +#define MCAN_TSU_EXT_TIMEBASE_SRC_TBSEL_3 (3U) +#define MCAN_TSU_EXT_TIMEBASE_SRC_MAX (MCAN_TSU_EXT_TIMEBASE_SRC_TBSEL_3) + +/** + * @brief MCAN TSU timebase option for each External Timebase + */ +#define MCAN_TSU_TBSEL_PTPC0 (0x20) +#define MCAN_TSU_TBSEL_MCAN0 (0x00) +#define MCAN_TSU_TBSEL_MCAN1 (0x01) +#define MCAN_TSU_TBSEL_MCAN2 (0x02) +#define MCAN_TSU_TBSEL_MCAN3 (0x03) + + +#ifdef __cpluspus +extern "C" { +#endif + +/** + * @brief Set External Timebase Source for MCAN TSU + * @param [in] ptr MCAN base + * @param [in] src External Timebase source + */ +static inline void mcan_set_tsu_ext_timebase_src(MCAN_Type *ptr, uint8_t src) +{ + if (src < HPM_MCAN_EXT_TBSEL_NUM) { + ptr->GLB_CTL = (ptr->GLB_CTL & ~MCAN_GLB_CTL_TSU_TBIN_SEL_MASK) | MCAN_GLB_CTL_TSU_TBIN_SEL_SET(src); + } +} + +/** + * @brief Set the Source for specified external timebase + * + * @param [in] ptr MCAN base + * @param [in] ext_tbsel External TBSEL index + * @param [in] tbsel_option Timebase source selection + */ +static inline void mcan_set_tsu_tbsel_option(MCAN_Type *ptr, uint8_t ext_tbsel, uint8_t tbsel_option) +{ + (void) ptr; + if (ext_tbsel < HPM_MCAN_EXT_TBSEL_NUM) { + uint32_t tbsel_shift = (ext_tbsel * HPM_MCAN_TBSEL_BITWDITH) + HPM_MCAN_TBSEL0_SHIFT; + uint32_t tbsel_mask = HPM_MCAN_TBSEL_MASK << tbsel_shift; + HPM_MCAN_TBSEL = (HPM_MCAN_TBSEL & ~tbsel_mask) | (((uint32_t)tbsel_option << tbsel_shift) & tbsel_mask); + } +} + +/** + * @brief Enable Standby Pin for MCAN + * @param [in] ptr MCAN base + */ +static inline void mcan_enable_standby_pin(MCAN_Type *ptr) +{ + ptr->GLB_CTL |= MCAN_GLB_CTL_M_CAN_STBY_MASK; +} + +/** + * @brief Disable Standby pin for MCAN + * @param [in] ptr MCAN base + */ +static inline void mcan_disable_standby_pin(MCAN_Type *ptr) +{ + ptr->GLB_CTL &= ~MCAN_GLB_CTL_M_CAN_STBY_MASK; +} + +/** + * @brief Get RAM base for MCAN + * @param [in] ptr MCAN base + * @return RAM base for MCAN + */ +static inline uint32_t mcan_get_ram_base(MCAN_Type *ptr) +{ + (void) ptr; + return MCAN_MSG_BUF_BASE; +} + +/** + * @brief Get the MCAN RAM offset in the dedicated/shared RAM for + * @param [in] ptr MCAN base + * @return RAM offset for MCAN + */ +static inline uint32_t mcan_get_ram_offset(MCAN_Type *ptr) +{ + uint32_t index = ((uint32_t) ptr - HPM_MCAN0_BASE) / MCAN_IP_SLOT_SIZE; + + return (index * MCAN_MSG_BUF_SIZE_IN_WORDS * sizeof(uint32_t)); +} + +/** + * @brief Get MCAN RAM size + * @param [in] ptr MCAN base + * @return RAM size in bytes + */ +static inline uint32_t mcan_get_ram_size(MCAN_Type *ptr) +{ + (void) ptr; + return (MCAN_MSG_BUF_SIZE_IN_WORDS * sizeof(uint32_t)); +} + +#ifdef __cpluspus +} +#endif + +#endif /* HPM_MCAN_SOC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_misc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_misc.h new file mode 100644 index 00000000000..367c61138a2 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_misc.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_MISC_H +#define HPM_MISC_H + +#define ILM_LOCAL_BASE (0x0U) +#define ILM_SIZE_IN_BYTE (0x20000U) +#define DLM_LOCAL_BASE (0x80000U) +#define DLM_SIZE_IN_BYTE (0x20000U) +#define CORE0_ILM_SYSTEM_BASE (0x1040000U) +#define CORE0_DLM_SYSTEM_BASE (0x1060000U) + +#define ADDRESS_IN_ILM(address) \ + ((ILM_LOCAL_BASE) <= (address)) && \ + ((ILM_LOCAL_BASE + ILM_SIZE_IN_BYTE) > (address)) +#define ADDRESS_IN_DLM(address) \ + ((DLM_LOCAL_BASE) <= (address)) && \ + ((DLM_LOCAL_BASE + DLM_SIZE_IN_BYTE) > (address)) +#define ADDRESS_IN_CORE0_DLM_SYSTEM(address) \ + ((CORE0_DLM_SYSTEM_BASE) <= (address)) && \ + ((CORE0_DLM_SYSTEM_BASE + DLM_SIZE_IN_BYTE) > (address)) + +#define DLM_TO_SYSTEM(address) \ + (CORE0_DLM_SYSTEM_BASE + (address) - (DLM_LOCAL_BASE)) +#define ILM_TO_SYSTEM(address) \ + (CORE0_ILM_SYSTEM_BASE + (address) - (ILM_LOCAL_BASE)) +#define SYSTEM_TO_DLM(address) \ + ((address) - CORE0_DLM_SYSTEM_BASE + (DLM_LOCAL_BASE)) + +#define HPM_CORE0 (0U) + +/* map core local memory(DLM/ILM) to system address */ +static inline uint32_t core_local_mem_to_sys_address(uint8_t core_id, uint32_t addr) +{ + (void) core_id; + return addr; +} + +/* map system address to core local memory(DLM/ILM) */ +static inline uint32_t sys_address_to_core_local_mem(uint8_t core_id, uint32_t addr) +{ + (void) core_id; + return addr; +} +#endif /* HPM_MISC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_otp_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_otp_drv.c new file mode 100644 index 00000000000..a68fc69c0e0 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_otp_drv.c @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_otp_drv.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +#define SHADOW_INDEX_IN_PMIC_OTP_END (15U) +#define OTP_UNLOCK_MAGIC_NUM (0x4E45504FUL) /*!< ASCII: OPEN */ +#define OTP_LOCK_MAGIC_NUM (~OTP_UNLOCK_MAGIC_NUM) +#define OTP_CMD_PROGRAM (0x574F4C42UL) /*!< ASCII: BLOW */ +#define OTP_CMD_READ (0x44414552UL) /*!< ASCII: READ */ + + +/*********************************************************************************************************************** + * Codes + **********************************************************************************************************************/ +void otp_init(void) +{ + +} + +void otp_deinit(void) +{ + +} + +uint32_t otp_read_from_shadow(uint32_t addr) +{ + uint32_t ret_val = 0; + if (addr < ARRAY_SIZE(HPM_OTP->SHADOW)) { + ret_val = HPM_OTP->SHADOW[addr]; + } + + return ret_val; +} + +uint32_t otp_read_from_ip(uint32_t addr) +{ + uint32_t ret_val = 0; + if (addr < ARRAY_SIZE(HPM_OTP->SHADOW)) { + ret_val = HPM_OTP->FUSE[addr]; + } + return ret_val; +} + +hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words) +{ + hpm_stat_t status = status_invalid_argument; + do { + uint32_t fuse_idx_max = ARRAY_SIZE(HPM_OTP->SHADOW); + HPM_BREAK_IF((addr >= fuse_idx_max) || (num_of_words > fuse_idx_max) || (addr + num_of_words > fuse_idx_max)); + + /* Enable 2.5V LDO for FUSE programming */ + uint32_t reg_val = (HPM_PCFG->LDO2P5 & ~PCFG_LDO2P5_VOLT_MASK) | PCFG_LDO2P5_ENABLE_MASK | PCFG_LDO2P5_VOLT_SET(2500); + HPM_PCFG->LDO2P5 = reg_val; + /* Wait until LDO is ready */ + while (!IS_HPM_BITMASK_SET(HPM_PCFG->LDO2P5, PCFG_DCDC_MODE_READY_MASK)) { + } + HPM_OTP->UNLOCK = OTP_UNLOCK_MAGIC_NUM; + for (uint32_t i = 0; i < num_of_words; i++) { + HPM_OTP->FUSE[addr++] = *src++; + } + HPM_OTP->UNLOCK = OTP_LOCK_MAGIC_NUM; + /* Disable 2.5V LDO after FUSE programming for saving power */ + HPM_PCFG->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; + status = status_success; + } while (false); + + return status; +} + +hpm_stat_t otp_reload(otp_region_t region) +{ + hpm_stat_t status = status_invalid_argument; + if ((uint32_t)region < 0x10 && (region >= otp_region0_mask)) { + HPM_OTP->LOAD_REQ = (uint32_t)region; + HPM_OTP->LOAD_COMP = (uint32_t)region; + while (!IS_HPM_BITMASK_SET(HPM_OTP->LOAD_COMP, region)) { + + } + status = status_success; + } + + return status; +} + +hpm_stat_t otp_lock_otp(uint32_t addr, otp_lock_option_t lock_option) +{ + hpm_stat_t status = status_invalid_argument; + + do { + HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW) || (lock_option > otp_lock_option_max)); + + OTP_Type *otp_base = HPM_OTP; + + uint32_t lock_reg_idx = (addr << 1) / 32; + uint32_t lock_reg_offset = (addr << 1) % 32; + + uint32_t lock_mask = ((uint32_t)lock_option) << lock_reg_offset; + + otp_base->FUSE_LOCK[lock_reg_idx] = lock_mask; + + status = status_success; + } while (false); + + return status; +} + +hpm_stat_t otp_lock_shadow(uint32_t addr, otp_lock_option_t lock_option) +{ + hpm_stat_t status = status_invalid_argument; + + do { + HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW) || (lock_option > otp_lock_option_max)); + + OTP_Type *otp_base = HPM_OTP; + + uint32_t lock_reg_idx = (addr << 1) / 32; + uint32_t lock_reg_offset = (addr << 1) % 32; + + uint32_t lock_mask = ((uint32_t)lock_option) << lock_reg_offset; + + otp_base->SHADOW_LOCK[lock_reg_idx] = lock_mask; + + status = status_success; + } while (false); + + return status; +} + +hpm_stat_t otp_set_configurable_region(uint32_t start, uint32_t num_of_words) +{ + hpm_stat_t status = status_invalid_argument; + + do { + uint32_t max_fuse_idx = ARRAY_SIZE(HPM_OTP->SHADOW); + HPM_BREAK_IF((start >= max_fuse_idx) || (num_of_words > max_fuse_idx) || ((start + num_of_words) > max_fuse_idx)); + + HPM_OTP->REGION[3] = OTP_REGION_START_SET(start) + | OTP_REGION_STOP_SET(start + num_of_words); + + status = status_success; + } while (false); + + return status; +} + +hpm_stat_t otp_write_shadow_register(uint32_t addr, uint32_t val) +{ + hpm_stat_t status = status_invalid_argument; + do { + HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW)); + + uint32_t lock_reg_idx = (addr << 1) / 32; + uint32_t lock_reg_offset = (addr << 1) % 32; + uint32_t lock_mask = 3U << lock_reg_offset; + + OTP_Type *otp_base = HPM_OTP; + otp_lock_option_t lock_opt = (otp_lock_option_t) ((otp_base->SHADOW_LOCK[lock_reg_idx] & lock_mask) + >> lock_reg_offset); + + if (lock_opt != otp_no_lock) { + status = otp_write_disallowed; + break; + } + + otp_base->SHADOW[addr] = val; + + status = status_success; + } while (false); + + return status; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_otp_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_otp_drv.h new file mode 100644 index 00000000000..b61c805a1df --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_otp_drv.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_OTP_DRV_H +#define HPM_OTP_DRV_H + +/** + * @brief OTP APIs + * @defgroup otp_interface OTP driver APIs + * @{ + */ + +#include "hpm_common.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +/** + * @brief OTP region definitions + */ +typedef enum { + otp_region0_mask = 1U, /*!< Address range: [0, 7] */ + otp_region1_mask = 2U, /*!< Address range: [8, 15] */ + otp_region2_mask = 4U, /*!< Address range: [16, 127] */ + otp_region3_mask = 8U, /*!< Address range: user defined */ +} otp_region_t; + +/** + * @brief OTP lock options + */ +typedef enum { + otp_no_lock = 0, + otp_read_only = 1, + otp_permanent_no_lock = 2, + otp_disable_access = 3, + otp_lock_option_max = otp_disable_access, +} otp_lock_option_t; + +enum { + otp_write_disallowed = MAKE_STATUS(status_group_otp, 0), +}; + +/*********************************************************************************************************************** + * Prototypes + **********************************************************************************************************************/ +#ifdef __cpluscplus +extern "C" { +#endif + +/** + * @brief Initialize OTP controller + */ +void otp_init(void); + +/** + * @brief De-initialize OTP controller + */ +void otp_deinit(void); + +/** + * @brief Read the OTP word from shadow register + * @param [in] addr OTP word index + * @retval OTP word value + */ +uint32_t otp_read_from_shadow(uint32_t addr); + +/** + * @brief Read the specified OTP word from OTP IP bus + * @param [in] addr OTP word index + * @retval OTP word value + */ +uint32_t otp_read_from_ip(uint32_t addr); + +/** + * @brief Program a word to specified OTP field + * @param [in] addr OTP word index + * @param [in] src Pointer to the data to be programmed + * @param [in] num_of_words Number of words to be programmed, only 1 is allowed + * @return API execution status + */ +hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words); + +/** + * @brief Reload a OTP region + * @param [in] region OTP region option + * @return API execution status + */ +hpm_stat_t otp_reload(otp_region_t region); + +/** + * @brief Change the Software lock permission + * @param [in] addr OTP word index + * @param [in] lock_option OTP lcok option + * @return API execution status + */ +hpm_stat_t otp_lock_otp(uint32_t addr, otp_lock_option_t lock_option); + +/** + * @brief OTP lock shadow + * @param [in] addr OTP word index + * @param [in] lock_option OTP lock option + * @return API execution status + */ +hpm_stat_t otp_lock_shadow(uint32_t addr, otp_lock_option_t lock_option); + +/** + * @brief Set the configurable region range + * @param [in] start OTP word start index + * @param [in] num_of_words Number of words in configuration region + * @retval status_out_of_range Invalid range + * @retval status_success Operation is successful + */ +hpm_stat_t otp_set_configurable_region(uint32_t start, uint32_t num_of_words); + +/** + * @return Write data to OTP shadow register + * @param [in] addr OTP word index + * @param [in] val Data to be written + * @return API execution status + */ +hpm_stat_t otp_write_shadow_register(uint32_t addr, uint32_t val); + + +#ifdef __cpluscplus +} +#endif +/** + * @} + */ + + + + +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_pcfg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_pcfg_drv.h new file mode 100644 index 00000000000..1920823cebd --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_pcfg_drv.h @@ -0,0 +1,497 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PCFG_DRV_H +#define HPM_PCFG_DRV_H + +#include "hpm_common.h" +#include "hpm_pcfg_regs.h" + +/** + * + * @brief PCFG driver APIs + * @defgroup pcfg_interface PCFG driver APIs + * @ingroup io_interfaces + * @{ + */ +#define PCFG_CLOCK_GATE_MODE_ALWAYS_ON (0x3UL) +#define PCFG_CLOCK_GATE_MODE_ALWAYS_OFF (0x2UL) + +#define PCFG_PERIPH_KEEP_CLOCK_ON(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_ON << (p)) +#define PCFG_PERIPH_KEEP_CLOCK_OFF(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_OFF << (p)) + +/* @brief PCFG irc24m reference */ +typedef enum { + pcfg_irc24m_reference_32k = 0, + pcfg_irc24m_reference_24m_xtal = 1 +} pcfg_irc24m_reference_t; + +/* @brief PCFG dcdc current limit */ +typedef enum { + pcfg_dcdc_lp_current_limit_250ma = 0, + pcfg_dcdc_lp_current_limit_200ma = 1, +} pcfg_dcdc_lp_current_limit_t; + +/* @brief PCFG dcdc current hys */ +typedef enum { + pcfg_dcdc_current_hys_12_5mv = 0, + pcfg_dcdc_current_hys_25mv = 1, +} pcfg_dcdc_current_hys_t; + +/* @brief PCFG dcdc mode */ +typedef enum { + pcfg_dcdc_mode_off = 0, + pcfg_dcdc_mode_basic = 1, + pcfg_dcdc_mode_general = 3, + pcfg_dcdc_mode_expert = 7, +} pcfg_dcdc_mode_t; + +/* @brief PCFG pmc domain peripherals */ +typedef enum { + pcfg_pmc_periph_gpio = 6, + pcfg_pmc_periph_ioc = 8, + pcfg_pmc_periph_timer = 10, + pcfg_pmc_periph_wdog = 12, + pcfg_pmc_periph_uart = 14, +} pcfg_pmc_periph_t; + +/* @brief PCFG status */ +enum { + status_pcfg_ldo_out_of_range = MAKE_STATUS(status_group_pcfg, 1), +}; + +/* @brief PCFG irc24m config */ +typedef struct { + uint32_t freq_in_hz; + pcfg_irc24m_reference_t reference; + bool return_to_default_on_xtal_loss; + bool free_run; +} pcfg_irc24m_config_t; + + +#define PCFG_CLOCK_GATE_CONTROL_MASK(module, mode) \ + ((uint32_t) (mode) << ((module) << 1)) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief check if bandgap is trimmed or not + * + * @param[in] ptr base address + * + * @retval true if bandgap is trimmed + */ +static inline bool pcfg_bandgap_is_trimmed(PCFG_Type *ptr) +{ + return ptr->BANDGAP & PCFG_BANDGAP_VBG_TRIMMED_MASK; +} + +/** + * @brief bandgap reload trim value + * + * @param[in] ptr base address + */ +static inline void pcfg_bandgap_reload_trim(PCFG_Type *ptr) +{ + ptr->BANDGAP &= ~PCFG_BANDGAP_VBG_TRIMMED_MASK; +} + +/** + * @brief turn off LDO2P5 + * + * @param[in] ptr base address + */ +static inline void pcfg_ldo2p5_turn_off(PCFG_Type *ptr) +{ + ptr->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; +} + +/** + * @brief turn on LDO 2.5V + * + * @param[in] ptr base address + */ +static inline void pcfg_ldo2p5_turn_on(PCFG_Type *ptr) +{ + ptr->LDO2P5 |= PCFG_LDO2P5_ENABLE_MASK; +} + +/** + * @brief check if LDO 2.5V is stable + * + * @param[in] ptr base address + * + * @retval true if LDO2P5 is stable + */ +static inline bool pcfg_ldo2p5_is_stable(PCFG_Type *ptr) +{ + return PCFG_LDO2P5_READY_GET(ptr->LDO2P5); +} + +/* + * @brief check if DCDC is stable or not + * @param[in] ptr base address + * @retval true if DCDC is stable + */ +static inline bool pcfg_dcdc_is_stable(PCFG_Type *ptr) +{ + return PCFG_DCDC_MODE_READY_GET(ptr->DCDC_MODE); +} + +/* + * @brief set DCDC work mode + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_set_mode(PCFG_Type *ptr, uint8_t mode) +{ + ptr->DCDC_MODE = (ptr->DCDC_MODE & ~PCFG_DCDC_MODE_MODE_MASK) | PCFG_DCDC_MODE_MODE_SET(mode); +} + +/** + * @brief set low power current limit + * + * @param[in] ptr base address + * @param[in] limit current limit at low power mode + */ +static inline void pcfg_dcdc_set_lp_current_limit(PCFG_Type *ptr, pcfg_dcdc_lp_current_limit_t limit) +{ + ptr->DCDC_PROT = (ptr->DCDC_PROT & ~(PCFG_DCDC_PROT_ILIMIT_LP_MASK | PCFG_DCDC_PROT_OVERLOAD_LP_MASK)) + | PCFG_DCDC_PROT_ILIMIT_LP_SET(limit); +} + + +/** + * @brief check if power loss flag is set + * + * @param[in] ptr base address + * + * @retval true if power loss is set + */ +static inline bool pcfg_dcdc_is_power_loss(PCFG_Type *ptr) +{ + return PCFG_DCDC_PROT_POWER_LOSS_FLAG_GET(ptr->DCDC_PROT); +} + +/** + * @brief disable over voltage protection + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_disable_over_voltage_prot(PCFG_Type *ptr) +{ + ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK; +} + +/** + * @brief enable over voltage protection + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_ensable_over_voltage_prot(PCFG_Type *ptr) +{ + ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK; +} + +/** + * @brief checkover voltage flag + * + * @param[in] ptr base address + * @retval true if flag is set + */ +static inline bool pcfg_dcdc_is_over_voltage(PCFG_Type *ptr) +{ + return PCFG_DCDC_PROT_OVERVOLT_FLAG_GET(ptr->DCDC_PROT) & PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK; +} + +/** + * @brief disable current measurement + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_disable_measure_current(PCFG_Type *ptr) +{ + ptr->DCDC_CURRENT &= ~PCFG_DCDC_CURRENT_ESTI_EN_MASK; +} + +/** + * @brief enable current measurement + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_enable_measure_current(PCFG_Type *ptr) +{ + ptr->DCDC_CURRENT |= PCFG_DCDC_CURRENT_ESTI_EN_MASK; +} + +/** + * @brief check if measured current is valid + * + * @param[in] ptr base address + * + * @retval true if measured current is valid + */ +static inline bool pcfg_dcdc_is_measure_current_valid(PCFG_Type *ptr) +{ + return ptr->DCDC_CURRENT & PCFG_DCDC_CURRENT_VALID_MASK; +} + +/** + * @brief get DCDC start time in number of 24MHz clock cycles + * + * @param[in] ptr base address + * + * @retval dcdc start time in cycles + */ +static inline uint32_t pcfg_dcdc_get_start_time_in_cycle(PCFG_Type *ptr) +{ + return PCFG_DCDC_START_TIME_START_TIME_GET(ptr->DCDC_START_TIME); +} + +/** + * @brief get DCDC resume time in number of 24MHz clock cycles + * + * @param[in] ptr base address + * + * @retval dcdc resuem time in cycles + */ +static inline uint32_t pcfg_dcdc_get_resume_time_in_cycle(PCFG_Type *ptr) +{ + return PCFG_DCDC_RESUME_TIME_RESUME_TIME_GET(ptr->DCDC_RESUME_TIME); +} + +/** + * @brief set DCDC start time in 24MHz clock cycles + * + * @param[in] ptr base address + * @param[in] cycles start time in cycles + */ +static inline void pcfg_dcdc_set_start_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) +{ + ptr->DCDC_START_TIME = PCFG_DCDC_START_TIME_START_TIME_SET(cycles); +} + +/** + * @brief set DCDC resuem time in 24MHz clock cycles + * + * @param[in] ptr base address + * @param[in] cycles resume time in cycles + */ +static inline void pcfg_dcdc_set_resume_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) +{ + ptr->DCDC_RESUME_TIME = PCFG_DCDC_RESUME_TIME_RESUME_TIME_SET(cycles); +} + +/** + * @brief set dcdc current hysteres range + * + * @param[in] ptr base address + * @param[in] range current hysteres range + */ +static inline void pcfg_dcdc_set_current_hys_range(PCFG_Type *ptr, pcfg_dcdc_current_hys_t range) +{ + ptr->DCDC_MISC = (ptr->DCDC_MISC & (~PCFG_DCDC_MISC_OL_HYST_MASK)) | PCFG_DCDC_MISC_OL_HYST_SET(range); +} + +/** + * @brief disable power trap + * + * @param[in] ptr base address + */ +static inline void pcfg_disable_power_trap(PCFG_Type *ptr) +{ + ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_TRAP_MASK; +} + +/** + * @brief enable power trap + * + * @param[in] ptr base address + */ +static inline void pcfg_enable_power_trap(PCFG_Type *ptr) +{ + ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRAP_MASK; +} + +/** + * @brief check if power trap is triggered + * + * @param[in] ptr base address + * + * @retval true if power trap is triggered + */ +static inline bool pcfg_is_power_trap_triggered(PCFG_Type *ptr) +{ + return ptr->POWER_TRAP & PCFG_POWER_TRAP_TRIGGERED_MASK; +} + +/** + * @brief clear power trap trigger flag + * + * @param[in] ptr base address + */ +static inline void pcfg_clear_power_trap_trigger_flag(PCFG_Type *ptr) +{ + ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRIGGERED_MASK; +} + +/** + * @brief disable dcdc retention + * + * @param[in] ptr base address + */ +static inline void pcfg_disable_dcdc_retention(PCFG_Type *ptr) +{ + ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_RETENTION_MASK; +} + +/** + * @brief enable dcdc retention to retain soc sram data + * + * @param[in] ptr base address + */ +static inline void pcfg_enable_dcdc_retention(PCFG_Type *ptr) +{ + ptr->POWER_TRAP |= PCFG_POWER_TRAP_RETENTION_MASK; +} + +/** + * @brief clear wakeup cause flag + * + * @param[in] ptr base address + * @param[in] mask mask of flags to be cleared + */ +static inline void pcfg_clear_wakeup_cause(PCFG_Type *ptr, uint32_t mask) +{ + ptr->WAKE_CAUSE |= mask; +} + +/** + * @brief get wakeup cause + * + * @param[in] ptr base address + * + * @retval mask of wake cause + */ +static inline uint32_t pcfg_get_wakeup_cause(PCFG_Type *ptr) +{ + return ptr->WAKE_CAUSE; +} + +/** + * @brief enable wakeup source + * + * @param[in] ptr base address + * @param[in] mask wakeup source mask + */ +static inline void pcfg_enable_wakeup_source(PCFG_Type *ptr, uint32_t mask) +{ + ptr->WAKE_MASK &= ~mask; +} + +/** + * @brief disable wakeup source + * + * @param[in] ptr base address + * @param[in] mask source to be disabled as wakeup source + */ +static inline void pcfg_disable_wakeup_source(PCFG_Type *ptr, uint32_t mask) +{ + ptr->WAKE_MASK |= mask; +} + +/** + * @brief set clock gate mode in vpmc domain + * + * @param[in] ptr base address + * @param[in] mode clock gate mode mask + */ +static inline void pcfg_set_periph_clock_mode(PCFG_Type *ptr, uint32_t mode) +{ + ptr->SCG_CTRL = mode; +} + +/** + * @brief check if irc24m is trimmed + * + * @param[in] ptr base address + * + * @retval true if it is trimmed + */ +static inline bool pcfg_irc24m_is_trimmed(PCFG_Type *ptr) +{ + return ptr->RC24M & PCFG_RC24M_RC_TRIMMED_MASK; +} + +/** + * @brief reload irc24m trim value + * + * @param[in] ptr base address + */ +static inline void pcfg_irc24m_reload_trim(PCFG_Type *ptr) +{ + ptr->RC24M &= ~PCFG_RC24M_RC_TRIMMED_MASK; +} + +/** + * @brief config irc24m track + * + * @param[in] ptr base address + * @param[in] config config data + */ +void pcfg_irc24m_config_track(PCFG_Type *ptr, pcfg_irc24m_config_t *config); + +/* + * @brief set DCDC voltage at standby mode + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_dcdc_set_lpmode_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief set output voltage of LDO 2.5V in mV + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_ldo2p5_set_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief set DCDC voltage + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_dcdc_set_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief set output voltage of LDO 1V in mV + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_ldo1p1_set_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief get current DCDC current level in mA + * + * @param[in] ptr base address + * @retval Current level at mA + */ +uint16_t pcfg_dcdc_get_current_level(PCFG_Type *ptr); + + +#ifdef __cplusplus +} +#endif +/** + * @} + */ + +#endif /* HPM_PCFG_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_pcfg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_pcfg_regs.h new file mode 100644 index 00000000000..65c022090f6 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_pcfg_regs.h @@ -0,0 +1,834 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PCFG_H +#define HPM_PCFG_H + +typedef struct { + __RW uint32_t BANDGAP; /* 0x0: BANGGAP control */ + __RW uint32_t LDO1P1; /* 0x4: 1V LDO config */ + __RW uint32_t LDO2P5; /* 0x8: 2.5V LDO config */ + __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ + __RW uint32_t DCDC_MODE; /* 0x10: DCDC mode select */ + __RW uint32_t DCDC_LPMODE; /* 0x14: DCDC low power mode */ + __RW uint32_t DCDC_PROT; /* 0x18: DCDC protection */ + __RW uint32_t DCDC_CURRENT; /* 0x1C: DCDC current estimation */ + __RW uint32_t DCDC_ADVMODE; /* 0x20: DCDC advance setting */ + __RW uint32_t DCDC_ADVPARAM; /* 0x24: DCDC advance parameter */ + __RW uint32_t DCDC_MISC; /* 0x28: DCDC misc parameter */ + __RW uint32_t DCDC_DEBUG; /* 0x2C: DCDC Debug */ + __RW uint32_t DCDC_START_TIME; /* 0x30: DCDC ramp time */ + __RW uint32_t DCDC_RESUME_TIME; /* 0x34: DCDC resume time */ + __R uint8_t RESERVED1[8]; /* 0x38 - 0x3F: Reserved */ + __RW uint32_t POWER_TRAP; /* 0x40: SOC power trap */ + __RW uint32_t WAKE_CAUSE; /* 0x44: Wake up source */ + __RW uint32_t WAKE_MASK; /* 0x48: Wake up mask */ + __RW uint32_t SCG_CTRL; /* 0x4C: Clock gate control in PMIC */ + __R uint8_t RESERVED2[16]; /* 0x50 - 0x5F: Reserved */ + __RW uint32_t RC24M; /* 0x60: RC 24M config */ + __RW uint32_t RC24M_TRACK; /* 0x64: RC 24M track mode */ + __RW uint32_t TRACK_TARGET; /* 0x68: RC 24M track target */ + __R uint32_t STATUS; /* 0x6C: RC 24M track status */ +} PCFG_Type; + + +/* Bitfield definition for register: BANDGAP */ +/* + * VBG_TRIMMED (RW) + * + * Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value + * 0: bandgap is not trimmed + * 1: bandgap is trimmed + */ +#define PCFG_BANDGAP_VBG_TRIMMED_MASK (0x80000000UL) +#define PCFG_BANDGAP_VBG_TRIMMED_SHIFT (31U) +#define PCFG_BANDGAP_VBG_TRIMMED_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_TRIMMED_SHIFT) & PCFG_BANDGAP_VBG_TRIMMED_MASK) +#define PCFG_BANDGAP_VBG_TRIMMED_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_TRIMMED_MASK) >> PCFG_BANDGAP_VBG_TRIMMED_SHIFT) + +/* + * VBG_1P0_TRIM (RW) + * + * Banggap 1.0V output trim value + */ +#define PCFG_BANDGAP_VBG_1P0_TRIM_MASK (0x1F0000UL) +#define PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT (16U) +#define PCFG_BANDGAP_VBG_1P0_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT) & PCFG_BANDGAP_VBG_1P0_TRIM_MASK) +#define PCFG_BANDGAP_VBG_1P0_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_1P0_TRIM_MASK) >> PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT) + +/* + * VBG_P65_TRIM (RW) + * + * Banggap 1.0V output trim value + */ +#define PCFG_BANDGAP_VBG_P65_TRIM_MASK (0x1F00U) +#define PCFG_BANDGAP_VBG_P65_TRIM_SHIFT (8U) +#define PCFG_BANDGAP_VBG_P65_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_P65_TRIM_SHIFT) & PCFG_BANDGAP_VBG_P65_TRIM_MASK) +#define PCFG_BANDGAP_VBG_P65_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_P65_TRIM_MASK) >> PCFG_BANDGAP_VBG_P65_TRIM_SHIFT) + +/* + * VBG_P50_TRIM (RW) + * + * Banggap 1.0V output trim value + */ +#define PCFG_BANDGAP_VBG_P50_TRIM_MASK (0x1FU) +#define PCFG_BANDGAP_VBG_P50_TRIM_SHIFT (0U) +#define PCFG_BANDGAP_VBG_P50_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) & PCFG_BANDGAP_VBG_P50_TRIM_MASK) +#define PCFG_BANDGAP_VBG_P50_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_P50_TRIM_MASK) >> PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) + +/* Bitfield definition for register: LDO1P1 */ +/* + * VOLT (RW) + * + * LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. + * 700: 700mV + * 720: 720mV + * . . . + * 1320:1320mV + */ +#define PCFG_LDO1P1_VOLT_MASK (0xFFFU) +#define PCFG_LDO1P1_VOLT_SHIFT (0U) +#define PCFG_LDO1P1_VOLT_SET(x) (((uint32_t)(x) << PCFG_LDO1P1_VOLT_SHIFT) & PCFG_LDO1P1_VOLT_MASK) +#define PCFG_LDO1P1_VOLT_GET(x) (((uint32_t)(x) & PCFG_LDO1P1_VOLT_MASK) >> PCFG_LDO1P1_VOLT_SHIFT) + +/* Bitfield definition for register: LDO2P5 */ +/* + * READY (RO) + * + * Ready flag, will set 1ms after enabled or voltage change + * 0: LDO is not ready for use + * 1: LDO is ready + */ +#define PCFG_LDO2P5_READY_MASK (0x10000000UL) +#define PCFG_LDO2P5_READY_SHIFT (28U) +#define PCFG_LDO2P5_READY_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_READY_MASK) >> PCFG_LDO2P5_READY_SHIFT) + +/* + * ENABLE (RW) + * + * LDO enable + * 0: turn off LDO + * 1: turn on LDO + */ +#define PCFG_LDO2P5_ENABLE_MASK (0x10000UL) +#define PCFG_LDO2P5_ENABLE_SHIFT (16U) +#define PCFG_LDO2P5_ENABLE_SET(x) (((uint32_t)(x) << PCFG_LDO2P5_ENABLE_SHIFT) & PCFG_LDO2P5_ENABLE_MASK) +#define PCFG_LDO2P5_ENABLE_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_ENABLE_MASK) >> PCFG_LDO2P5_ENABLE_SHIFT) + +/* + * VOLT (RW) + * + * LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. + * 2125: 2125mV + * 2150: 2150mV + * . . . + * 2900:2900mV + */ +#define PCFG_LDO2P5_VOLT_MASK (0xFFFU) +#define PCFG_LDO2P5_VOLT_SHIFT (0U) +#define PCFG_LDO2P5_VOLT_SET(x) (((uint32_t)(x) << PCFG_LDO2P5_VOLT_SHIFT) & PCFG_LDO2P5_VOLT_MASK) +#define PCFG_LDO2P5_VOLT_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_VOLT_MASK) >> PCFG_LDO2P5_VOLT_SHIFT) + +/* Bitfield definition for register: DCDC_MODE */ +/* + * READY (RO) + * + * Ready flag + * 0: DCDC is applying new change + * 1: DCDC is ready + */ +#define PCFG_DCDC_MODE_READY_MASK (0x10000000UL) +#define PCFG_DCDC_MODE_READY_SHIFT (28U) +#define PCFG_DCDC_MODE_READY_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_READY_MASK) >> PCFG_DCDC_MODE_READY_SHIFT) + +/* + * MODE (RW) + * + * DCDC work mode + * XX0: turn off + * 001: basic mode + * 011: generic mode + * 101: automatic mode + * 111: expert mode + */ +#define PCFG_DCDC_MODE_MODE_MASK (0x70000UL) +#define PCFG_DCDC_MODE_MODE_SHIFT (16U) +#define PCFG_DCDC_MODE_MODE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MODE_MODE_SHIFT) & PCFG_DCDC_MODE_MODE_MASK) +#define PCFG_DCDC_MODE_MODE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_MODE_MASK) >> PCFG_DCDC_MODE_MODE_SHIFT) + +/* + * VOLT (RW) + * + * DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. + * 600: 600mV + * 625: 625mV + * . . . + * 1375:1375mV + */ +#define PCFG_DCDC_MODE_VOLT_MASK (0xFFFU) +#define PCFG_DCDC_MODE_VOLT_SHIFT (0U) +#define PCFG_DCDC_MODE_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDC_MODE_VOLT_SHIFT) & PCFG_DCDC_MODE_VOLT_MASK) +#define PCFG_DCDC_MODE_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_VOLT_MASK) >> PCFG_DCDC_MODE_VOLT_SHIFT) + +/* Bitfield definition for register: DCDC_LPMODE */ +/* + * STBY_VOLT (RW) + * + * DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. + * 600: 600mV + * 625: 625mV + * . . . + * 1375:1375mV + */ +#define PCFG_DCDC_LPMODE_STBY_VOLT_MASK (0xFFFU) +#define PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT (0U) +#define PCFG_DCDC_LPMODE_STBY_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT) & PCFG_DCDC_LPMODE_STBY_VOLT_MASK) +#define PCFG_DCDC_LPMODE_STBY_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDC_LPMODE_STBY_VOLT_MASK) >> PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT) + +/* Bitfield definition for register: DCDC_PROT */ +/* + * ILIMIT_LP (RW) + * + * over current setting for low power mode + * 0:250mA + * 1:200mA + */ +#define PCFG_DCDC_PROT_ILIMIT_LP_MASK (0x10000000UL) +#define PCFG_DCDC_PROT_ILIMIT_LP_SHIFT (28U) +#define PCFG_DCDC_PROT_ILIMIT_LP_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) +#define PCFG_DCDC_PROT_ILIMIT_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) >> PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) + +/* + * OVERLOAD_LP (RO) + * + * over current in low power mode + * 0: current is below setting + * 1: overcurrent happened in low power mode + */ +#define PCFG_DCDC_PROT_OVERLOAD_LP_MASK (0x1000000UL) +#define PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT (24U) +#define PCFG_DCDC_PROT_OVERLOAD_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERLOAD_LP_MASK) >> PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT) + +/* + * POWER_LOSS_FLAG (RO) + * + * power loss + * 0: input power is good + * 1: input power is too low + */ +#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_MASK (0x10000UL) +#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_SHIFT (16U) +#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_POWER_LOSS_FLAG_MASK) >> PCFG_DCDC_PROT_POWER_LOSS_FLAG_SHIFT) + +/* + * DISABLE_OVERVOLTAGE (RW) + * + * output over voltage protection + * 0: protection enabled, DCDC will shut down is output voltage is unexpected high + * 1: protection disabled, DCDC continue to adjust output voltage + */ +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK (0x8000U) +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT (15U) +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT) & PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK) +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK) >> PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT) + +/* + * OVERVOLT_FLAG (RO) + * + * output over voltage flag + * 0: output is normal + * 1: output is unexpected high + */ +#define PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK (0x100U) +#define PCFG_DCDC_PROT_OVERVOLT_FLAG_SHIFT (8U) +#define PCFG_DCDC_PROT_OVERVOLT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK) >> PCFG_DCDC_PROT_OVERVOLT_FLAG_SHIFT) + +/* + * DISABLE_SHORT (RW) + * + * disable output short circuit protection + * 0: short circuits protection enabled, DCDC shut down if short circuit on output detected + * 1: short circuit protection disabled + */ +#define PCFG_DCDC_PROT_DISABLE_SHORT_MASK (0x80U) +#define PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT (7U) +#define PCFG_DCDC_PROT_DISABLE_SHORT_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT) & PCFG_DCDC_PROT_DISABLE_SHORT_MASK) +#define PCFG_DCDC_PROT_DISABLE_SHORT_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_SHORT_MASK) >> PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT) + +/* + * SHORT_CURRENT (RW) + * + * short circuit current setting + * 0: 2.0A, + * 1: 1.3A + */ +#define PCFG_DCDC_PROT_SHORT_CURRENT_MASK (0x10U) +#define PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT (4U) +#define PCFG_DCDC_PROT_SHORT_CURRENT_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT) & PCFG_DCDC_PROT_SHORT_CURRENT_MASK) +#define PCFG_DCDC_PROT_SHORT_CURRENT_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_SHORT_CURRENT_MASK) >> PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT) + +/* + * SHORT_FLAG (RO) + * + * short circuit flag + * 0: current is within limit + * 1: short circuits detected + */ +#define PCFG_DCDC_PROT_SHORT_FLAG_MASK (0x1U) +#define PCFG_DCDC_PROT_SHORT_FLAG_SHIFT (0U) +#define PCFG_DCDC_PROT_SHORT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_SHORT_FLAG_MASK) >> PCFG_DCDC_PROT_SHORT_FLAG_SHIFT) + +/* Bitfield definition for register: DCDC_CURRENT */ +/* + * ESTI_EN (RW) + * + * enable current measure + */ +#define PCFG_DCDC_CURRENT_ESTI_EN_MASK (0x8000U) +#define PCFG_DCDC_CURRENT_ESTI_EN_SHIFT (15U) +#define PCFG_DCDC_CURRENT_ESTI_EN_SET(x) (((uint32_t)(x) << PCFG_DCDC_CURRENT_ESTI_EN_SHIFT) & PCFG_DCDC_CURRENT_ESTI_EN_MASK) +#define PCFG_DCDC_CURRENT_ESTI_EN_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_ESTI_EN_MASK) >> PCFG_DCDC_CURRENT_ESTI_EN_SHIFT) + +/* + * VALID (RO) + * + * Current level valid + * 0: data is invalid + * 1: data is valid + */ +#define PCFG_DCDC_CURRENT_VALID_MASK (0x100U) +#define PCFG_DCDC_CURRENT_VALID_SHIFT (8U) +#define PCFG_DCDC_CURRENT_VALID_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_VALID_MASK) >> PCFG_DCDC_CURRENT_VALID_SHIFT) + +/* + * LEVEL (RO) + * + * DCDC current level, current level is num * 50mA + */ +#define PCFG_DCDC_CURRENT_LEVEL_MASK (0x1FU) +#define PCFG_DCDC_CURRENT_LEVEL_SHIFT (0U) +#define PCFG_DCDC_CURRENT_LEVEL_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_LEVEL_MASK) >> PCFG_DCDC_CURRENT_LEVEL_SHIFT) + +/* Bitfield definition for register: DCDC_ADVMODE */ +/* + * EN_RCSCALE (RW) + * + * Enable RC scale + */ +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK (0x7000000UL) +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT (24U) +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT) & PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK) +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK) >> PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT) + +/* + * DC_C (RW) + * + * Loop C number + */ +#define PCFG_DCDC_ADVMODE_DC_C_MASK (0x300000UL) +#define PCFG_DCDC_ADVMODE_DC_C_SHIFT (20U) +#define PCFG_DCDC_ADVMODE_DC_C_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_DC_C_SHIFT) & PCFG_DCDC_ADVMODE_DC_C_MASK) +#define PCFG_DCDC_ADVMODE_DC_C_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_DC_C_MASK) >> PCFG_DCDC_ADVMODE_DC_C_SHIFT) + +/* + * DC_R (RW) + * + * Loop R number + */ +#define PCFG_DCDC_ADVMODE_DC_R_MASK (0xF0000UL) +#define PCFG_DCDC_ADVMODE_DC_R_SHIFT (16U) +#define PCFG_DCDC_ADVMODE_DC_R_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_DC_R_SHIFT) & PCFG_DCDC_ADVMODE_DC_R_MASK) +#define PCFG_DCDC_ADVMODE_DC_R_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_DC_R_MASK) >> PCFG_DCDC_ADVMODE_DC_R_SHIFT) + +/* + * EN_FF_DET (RW) + * + * enable feed forward detect + * 0: feed forward detect is disabled + * 1: feed forward detect is enabled + */ +#define PCFG_DCDC_ADVMODE_EN_FF_DET_MASK (0x40U) +#define PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT (6U) +#define PCFG_DCDC_ADVMODE_EN_FF_DET_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT) & PCFG_DCDC_ADVMODE_EN_FF_DET_MASK) +#define PCFG_DCDC_ADVMODE_EN_FF_DET_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_FF_DET_MASK) >> PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT) + +/* + * EN_FF_LOOP (RW) + * + * enable feed forward loop + * 0: feed forward loop is disabled + * 1: feed forward loop is enabled + */ +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK (0x20U) +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT (5U) +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) >> PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) + +/* + * EN_AUTOLP (RW) + * + * enable auto enter low power mode + * 0: do not enter low power mode + * 1: enter low power mode if current is detected low + */ +#define PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK (0x10U) +#define PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT (4U) +#define PCFG_DCDC_ADVMODE_EN_AUTOLP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT) & PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK) +#define PCFG_DCDC_ADVMODE_EN_AUTOLP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK) >> PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT) + +/* + * EN_DCM_EXIT (RW) + * + * avoid over voltage + * 0: stay in DCM mode when voltage excess + * 1: change to CCM mode when voltage excess + */ +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK (0x8U) +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT (3U) +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT) & PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK) +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK) >> PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT) + +/* + * EN_SKIP (RW) + * + * enable skip on narrow pulse + * 0: do not skip narrow pulse + * 1: skip narrow pulse + */ +#define PCFG_DCDC_ADVMODE_EN_SKIP_MASK (0x4U) +#define PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT (2U) +#define PCFG_DCDC_ADVMODE_EN_SKIP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT) & PCFG_DCDC_ADVMODE_EN_SKIP_MASK) +#define PCFG_DCDC_ADVMODE_EN_SKIP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_SKIP_MASK) >> PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT) + +/* + * EN_IDLE (RW) + * + * enable skip when voltage is higher than threshold + * 0: do not skip + * 1: skip if voltage is excess + */ +#define PCFG_DCDC_ADVMODE_EN_IDLE_MASK (0x2U) +#define PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT (1U) +#define PCFG_DCDC_ADVMODE_EN_IDLE_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT) & PCFG_DCDC_ADVMODE_EN_IDLE_MASK) +#define PCFG_DCDC_ADVMODE_EN_IDLE_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_IDLE_MASK) >> PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT) + +/* + * EN_DCM (RW) + * + * DCM mode + * 0: CCM mode + * 1: DCM mode + */ +#define PCFG_DCDC_ADVMODE_EN_DCM_MASK (0x1U) +#define PCFG_DCDC_ADVMODE_EN_DCM_SHIFT (0U) +#define PCFG_DCDC_ADVMODE_EN_DCM_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_DCM_SHIFT) & PCFG_DCDC_ADVMODE_EN_DCM_MASK) +#define PCFG_DCDC_ADVMODE_EN_DCM_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_DCM_MASK) >> PCFG_DCDC_ADVMODE_EN_DCM_SHIFT) + +/* Bitfield definition for register: DCDC_ADVPARAM */ +/* + * MIN_DUT (RW) + * + * minimum duty cycle + */ +#define PCFG_DCDC_ADVPARAM_MIN_DUT_MASK (0x7F00U) +#define PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT (8U) +#define PCFG_DCDC_ADVPARAM_MIN_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT) & PCFG_DCDC_ADVPARAM_MIN_DUT_MASK) +#define PCFG_DCDC_ADVPARAM_MIN_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVPARAM_MIN_DUT_MASK) >> PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT) + +/* + * MAX_DUT (RW) + * + * maximum duty cycle + */ +#define PCFG_DCDC_ADVPARAM_MAX_DUT_MASK (0x7FU) +#define PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT (0U) +#define PCFG_DCDC_ADVPARAM_MAX_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT) & PCFG_DCDC_ADVPARAM_MAX_DUT_MASK) +#define PCFG_DCDC_ADVPARAM_MAX_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVPARAM_MAX_DUT_MASK) >> PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT) + +/* Bitfield definition for register: DCDC_MISC */ +/* + * EN_HYST (RW) + * + * hysteres enable + */ +#define PCFG_DCDC_MISC_EN_HYST_MASK (0x10000000UL) +#define PCFG_DCDC_MISC_EN_HYST_SHIFT (28U) +#define PCFG_DCDC_MISC_EN_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_EN_HYST_SHIFT) & PCFG_DCDC_MISC_EN_HYST_MASK) +#define PCFG_DCDC_MISC_EN_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_EN_HYST_MASK) >> PCFG_DCDC_MISC_EN_HYST_SHIFT) + +/* + * HYST_SIGN (RW) + * + * hysteres sign + */ +#define PCFG_DCDC_MISC_HYST_SIGN_MASK (0x2000000UL) +#define PCFG_DCDC_MISC_HYST_SIGN_SHIFT (25U) +#define PCFG_DCDC_MISC_HYST_SIGN_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_HYST_SIGN_SHIFT) & PCFG_DCDC_MISC_HYST_SIGN_MASK) +#define PCFG_DCDC_MISC_HYST_SIGN_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_HYST_SIGN_MASK) >> PCFG_DCDC_MISC_HYST_SIGN_SHIFT) + +/* + * HYST_THRS (RW) + * + * hysteres threshold + */ +#define PCFG_DCDC_MISC_HYST_THRS_MASK (0x1000000UL) +#define PCFG_DCDC_MISC_HYST_THRS_SHIFT (24U) +#define PCFG_DCDC_MISC_HYST_THRS_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_HYST_THRS_SHIFT) & PCFG_DCDC_MISC_HYST_THRS_MASK) +#define PCFG_DCDC_MISC_HYST_THRS_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_HYST_THRS_MASK) >> PCFG_DCDC_MISC_HYST_THRS_SHIFT) + +/* + * RC_SCALE (RW) + * + * Loop RC scale threshold + */ +#define PCFG_DCDC_MISC_RC_SCALE_MASK (0x100000UL) +#define PCFG_DCDC_MISC_RC_SCALE_SHIFT (20U) +#define PCFG_DCDC_MISC_RC_SCALE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_RC_SCALE_SHIFT) & PCFG_DCDC_MISC_RC_SCALE_MASK) +#define PCFG_DCDC_MISC_RC_SCALE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_RC_SCALE_MASK) >> PCFG_DCDC_MISC_RC_SCALE_SHIFT) + +/* + * DC_FF (RW) + * + * Loop feed forward number + */ +#define PCFG_DCDC_MISC_DC_FF_MASK (0x70000UL) +#define PCFG_DCDC_MISC_DC_FF_SHIFT (16U) +#define PCFG_DCDC_MISC_DC_FF_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_DC_FF_SHIFT) & PCFG_DCDC_MISC_DC_FF_MASK) +#define PCFG_DCDC_MISC_DC_FF_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_DC_FF_MASK) >> PCFG_DCDC_MISC_DC_FF_SHIFT) + +/* + * OL_THRE (RW) + * + * overload for threshold for lod power mode + */ +#define PCFG_DCDC_MISC_OL_THRE_MASK (0x300U) +#define PCFG_DCDC_MISC_OL_THRE_SHIFT (8U) +#define PCFG_DCDC_MISC_OL_THRE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_OL_THRE_SHIFT) & PCFG_DCDC_MISC_OL_THRE_MASK) +#define PCFG_DCDC_MISC_OL_THRE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_OL_THRE_MASK) >> PCFG_DCDC_MISC_OL_THRE_SHIFT) + +/* + * OL_HYST (RW) + * + * current hysteres range + * 0: 12.5mV + * 1: 25mV + */ +#define PCFG_DCDC_MISC_OL_HYST_MASK (0x10U) +#define PCFG_DCDC_MISC_OL_HYST_SHIFT (4U) +#define PCFG_DCDC_MISC_OL_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_OL_HYST_SHIFT) & PCFG_DCDC_MISC_OL_HYST_MASK) +#define PCFG_DCDC_MISC_OL_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_OL_HYST_MASK) >> PCFG_DCDC_MISC_OL_HYST_SHIFT) + +/* + * DELAY (RW) + * + * enable delay + * 0: delay disabled, + * 1: delay enabled + */ +#define PCFG_DCDC_MISC_DELAY_MASK (0x4U) +#define PCFG_DCDC_MISC_DELAY_SHIFT (2U) +#define PCFG_DCDC_MISC_DELAY_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_DELAY_SHIFT) & PCFG_DCDC_MISC_DELAY_MASK) +#define PCFG_DCDC_MISC_DELAY_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_DELAY_MASK) >> PCFG_DCDC_MISC_DELAY_SHIFT) + +/* + * CLK_SEL (RW) + * + * clock selection + * 0: select DCDC internal oscillator + * 1: select RC24M oscillator + */ +#define PCFG_DCDC_MISC_CLK_SEL_MASK (0x2U) +#define PCFG_DCDC_MISC_CLK_SEL_SHIFT (1U) +#define PCFG_DCDC_MISC_CLK_SEL_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_CLK_SEL_SHIFT) & PCFG_DCDC_MISC_CLK_SEL_MASK) +#define PCFG_DCDC_MISC_CLK_SEL_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_CLK_SEL_MASK) >> PCFG_DCDC_MISC_CLK_SEL_SHIFT) + +/* + * EN_STEP (RW) + * + * enable stepping in voltage change + * 0: stepping disabled, + * 1: steping enabled + */ +#define PCFG_DCDC_MISC_EN_STEP_MASK (0x1U) +#define PCFG_DCDC_MISC_EN_STEP_SHIFT (0U) +#define PCFG_DCDC_MISC_EN_STEP_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_EN_STEP_SHIFT) & PCFG_DCDC_MISC_EN_STEP_MASK) +#define PCFG_DCDC_MISC_EN_STEP_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_EN_STEP_MASK) >> PCFG_DCDC_MISC_EN_STEP_SHIFT) + +/* Bitfield definition for register: DCDC_DEBUG */ +/* + * UPDATE_TIME (RW) + * + * DCDC voltage change time in 24M clock cycles, default value is 1mS + */ +#define PCFG_DCDC_DEBUG_UPDATE_TIME_MASK (0xFFFFFUL) +#define PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT (0U) +#define PCFG_DCDC_DEBUG_UPDATE_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT) & PCFG_DCDC_DEBUG_UPDATE_TIME_MASK) +#define PCFG_DCDC_DEBUG_UPDATE_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_DEBUG_UPDATE_TIME_MASK) >> PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT) + +/* Bitfield definition for register: DCDC_START_TIME */ +/* + * START_TIME (RW) + * + * Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS + */ +#define PCFG_DCDC_START_TIME_START_TIME_MASK (0xFFFFFUL) +#define PCFG_DCDC_START_TIME_START_TIME_SHIFT (0U) +#define PCFG_DCDC_START_TIME_START_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_START_TIME_START_TIME_SHIFT) & PCFG_DCDC_START_TIME_START_TIME_MASK) +#define PCFG_DCDC_START_TIME_START_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_START_TIME_START_TIME_MASK) >> PCFG_DCDC_START_TIME_START_TIME_SHIFT) + +/* Bitfield definition for register: DCDC_RESUME_TIME */ +/* + * RESUME_TIME (RW) + * + * Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS + */ +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK (0xFFFFFUL) +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT (0U) +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT) & PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK) +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK) >> PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT) + +/* Bitfield definition for register: POWER_TRAP */ +/* + * TRIGGERED (RW) + * + * Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. + * 0: low power trap is not triggered + * 1: low power trap triggered + */ +#define PCFG_POWER_TRAP_TRIGGERED_MASK (0x80000000UL) +#define PCFG_POWER_TRAP_TRIGGERED_SHIFT (31U) +#define PCFG_POWER_TRAP_TRIGGERED_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_TRIGGERED_SHIFT) & PCFG_POWER_TRAP_TRIGGERED_MASK) +#define PCFG_POWER_TRAP_TRIGGERED_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_TRIGGERED_MASK) >> PCFG_POWER_TRAP_TRIGGERED_SHIFT) + +/* + * RETENTION (RW) + * + * DCDC enter standby mode, which will reduce voltage for memory content retention + * 0: Shutdown DCDC + * 1: reduce DCDC voltage + */ +#define PCFG_POWER_TRAP_RETENTION_MASK (0x10000UL) +#define PCFG_POWER_TRAP_RETENTION_SHIFT (16U) +#define PCFG_POWER_TRAP_RETENTION_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_RETENTION_SHIFT) & PCFG_POWER_TRAP_RETENTION_MASK) +#define PCFG_POWER_TRAP_RETENTION_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_RETENTION_MASK) >> PCFG_POWER_TRAP_RETENTION_SHIFT) + +/* + * TRAP (RW) + * + * Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered + * 0: trap not enabled, pmic side low power function disabled + * 1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. + */ +#define PCFG_POWER_TRAP_TRAP_MASK (0x1U) +#define PCFG_POWER_TRAP_TRAP_SHIFT (0U) +#define PCFG_POWER_TRAP_TRAP_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_TRAP_SHIFT) & PCFG_POWER_TRAP_TRAP_MASK) +#define PCFG_POWER_TRAP_TRAP_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_TRAP_MASK) >> PCFG_POWER_TRAP_TRAP_SHIFT) + +/* Bitfield definition for register: WAKE_CAUSE */ +/* + * CAUSE (RW) + * + * wake up cause, each bit represents one wake up source, write 1 to clear the register bit + * 0: wake up source is not active during last wakeup + * 1: wake up source is active furing last wakeup + * bit 0: pmic_enable + * bit 7: UART interrupt + * bit 8: TMR interrupt + * bit 9: WDG interrupt + * bit10: GPIO in PMIC interrupt + * bit31: pin wakeup + */ +#define PCFG_WAKE_CAUSE_CAUSE_MASK (0xFFFFFFFFUL) +#define PCFG_WAKE_CAUSE_CAUSE_SHIFT (0U) +#define PCFG_WAKE_CAUSE_CAUSE_SET(x) (((uint32_t)(x) << PCFG_WAKE_CAUSE_CAUSE_SHIFT) & PCFG_WAKE_CAUSE_CAUSE_MASK) +#define PCFG_WAKE_CAUSE_CAUSE_GET(x) (((uint32_t)(x) & PCFG_WAKE_CAUSE_CAUSE_MASK) >> PCFG_WAKE_CAUSE_CAUSE_SHIFT) + +/* Bitfield definition for register: WAKE_MASK */ +/* + * MASK (RW) + * + * mask for wake up sources, each bit represents one wakeup source + * 0: allow source to wake up system + * 1: disallow source to wakeup system + * bit 0: pmic_enable + * bit 7: UART interrupt + * bit 8: TMR interrupt + * bit 9: WDG interrupt + * bit10: GPIO in PMIC interrupt + * bit31: pin wakeup + */ +#define PCFG_WAKE_MASK_MASK_MASK (0xFFFFFFFFUL) +#define PCFG_WAKE_MASK_MASK_SHIFT (0U) +#define PCFG_WAKE_MASK_MASK_SET(x) (((uint32_t)(x) << PCFG_WAKE_MASK_MASK_SHIFT) & PCFG_WAKE_MASK_MASK_MASK) +#define PCFG_WAKE_MASK_MASK_GET(x) (((uint32_t)(x) & PCFG_WAKE_MASK_MASK_MASK) >> PCFG_WAKE_MASK_MASK_SHIFT) + +/* Bitfield definition for register: SCG_CTRL */ +/* + * SCG (RW) + * + * control whether clock being gated during PMIC low power flow, 2 bits for each peripheral + * 00,01: reserved + * 10: clock is always off + * 11: clock is always on + * bit6-7:gpio + * bit8-9:ioc + * bit10-11: timer + * bit12-13:wdog + * bit14-15:uart + */ +#define PCFG_SCG_CTRL_SCG_MASK (0xFFFFFFFFUL) +#define PCFG_SCG_CTRL_SCG_SHIFT (0U) +#define PCFG_SCG_CTRL_SCG_SET(x) (((uint32_t)(x) << PCFG_SCG_CTRL_SCG_SHIFT) & PCFG_SCG_CTRL_SCG_MASK) +#define PCFG_SCG_CTRL_SCG_GET(x) (((uint32_t)(x) & PCFG_SCG_CTRL_SCG_MASK) >> PCFG_SCG_CTRL_SCG_SHIFT) + +/* Bitfield definition for register: RC24M */ +/* + * RC_TRIMMED (RW) + * + * RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value + * 0: RC is not trimmed + * 1: RC is trimmed + */ +#define PCFG_RC24M_RC_TRIMMED_MASK (0x80000000UL) +#define PCFG_RC24M_RC_TRIMMED_SHIFT (31U) +#define PCFG_RC24M_RC_TRIMMED_SET(x) (((uint32_t)(x) << PCFG_RC24M_RC_TRIMMED_SHIFT) & PCFG_RC24M_RC_TRIMMED_MASK) +#define PCFG_RC24M_RC_TRIMMED_GET(x) (((uint32_t)(x) & PCFG_RC24M_RC_TRIMMED_MASK) >> PCFG_RC24M_RC_TRIMMED_SHIFT) + +/* + * TRIM_C (RW) + * + * Coarse trim for RC24M, bigger value means faster + */ +#define PCFG_RC24M_TRIM_C_MASK (0x700U) +#define PCFG_RC24M_TRIM_C_SHIFT (8U) +#define PCFG_RC24M_TRIM_C_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRIM_C_SHIFT) & PCFG_RC24M_TRIM_C_MASK) +#define PCFG_RC24M_TRIM_C_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRIM_C_MASK) >> PCFG_RC24M_TRIM_C_SHIFT) + +/* + * TRIM_F (RW) + * + * Fine trim for RC24M, bigger value means faster + */ +#define PCFG_RC24M_TRIM_F_MASK (0x1FU) +#define PCFG_RC24M_TRIM_F_SHIFT (0U) +#define PCFG_RC24M_TRIM_F_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRIM_F_SHIFT) & PCFG_RC24M_TRIM_F_MASK) +#define PCFG_RC24M_TRIM_F_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRIM_F_MASK) >> PCFG_RC24M_TRIM_F_SHIFT) + +/* Bitfield definition for register: RC24M_TRACK */ +/* + * SEL24M (RW) + * + * Select track reference + * 0: select 32K as reference + * 1: select 24M XTAL as reference + */ +#define PCFG_RC24M_TRACK_SEL24M_MASK (0x10000UL) +#define PCFG_RC24M_TRACK_SEL24M_SHIFT (16U) +#define PCFG_RC24M_TRACK_SEL24M_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_SEL24M_SHIFT) & PCFG_RC24M_TRACK_SEL24M_MASK) +#define PCFG_RC24M_TRACK_SEL24M_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_SEL24M_MASK) >> PCFG_RC24M_TRACK_SEL24M_SHIFT) + +/* + * RETURN (RW) + * + * Retrun default value when XTAL loss + * 0: remain last tracking value + * 1: switch to default value + */ +#define PCFG_RC24M_TRACK_RETURN_MASK (0x10U) +#define PCFG_RC24M_TRACK_RETURN_SHIFT (4U) +#define PCFG_RC24M_TRACK_RETURN_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_RETURN_SHIFT) & PCFG_RC24M_TRACK_RETURN_MASK) +#define PCFG_RC24M_TRACK_RETURN_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_RETURN_MASK) >> PCFG_RC24M_TRACK_RETURN_SHIFT) + +/* + * TRACK (RW) + * + * track mode + * 0: RC24M free running + * 1: track RC24M to external XTAL + */ +#define PCFG_RC24M_TRACK_TRACK_MASK (0x1U) +#define PCFG_RC24M_TRACK_TRACK_SHIFT (0U) +#define PCFG_RC24M_TRACK_TRACK_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_TRACK_SHIFT) & PCFG_RC24M_TRACK_TRACK_MASK) +#define PCFG_RC24M_TRACK_TRACK_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_TRACK_MASK) >> PCFG_RC24M_TRACK_TRACK_SHIFT) + +/* Bitfield definition for register: TRACK_TARGET */ +/* + * PRE_DIV (RW) + * + * Divider for reference source + */ +#define PCFG_TRACK_TARGET_PRE_DIV_MASK (0xFFFF0000UL) +#define PCFG_TRACK_TARGET_PRE_DIV_SHIFT (16U) +#define PCFG_TRACK_TARGET_PRE_DIV_SET(x) (((uint32_t)(x) << PCFG_TRACK_TARGET_PRE_DIV_SHIFT) & PCFG_TRACK_TARGET_PRE_DIV_MASK) +#define PCFG_TRACK_TARGET_PRE_DIV_GET(x) (((uint32_t)(x) & PCFG_TRACK_TARGET_PRE_DIV_MASK) >> PCFG_TRACK_TARGET_PRE_DIV_SHIFT) + +/* + * TARGET (RW) + * + * Target frequency multiplier of divided source + */ +#define PCFG_TRACK_TARGET_TARGET_MASK (0xFFFFU) +#define PCFG_TRACK_TARGET_TARGET_SHIFT (0U) +#define PCFG_TRACK_TARGET_TARGET_SET(x) (((uint32_t)(x) << PCFG_TRACK_TARGET_TARGET_SHIFT) & PCFG_TRACK_TARGET_TARGET_MASK) +#define PCFG_TRACK_TARGET_TARGET_GET(x) (((uint32_t)(x) & PCFG_TRACK_TARGET_TARGET_MASK) >> PCFG_TRACK_TARGET_TARGET_SHIFT) + +/* Bitfield definition for register: STATUS */ +/* + * SEL32K (RO) + * + * track is using XTAL32K + * 0: track is not using XTAL32K + * 1: track is using XTAL32K + */ +#define PCFG_STATUS_SEL32K_MASK (0x100000UL) +#define PCFG_STATUS_SEL32K_SHIFT (20U) +#define PCFG_STATUS_SEL32K_GET(x) (((uint32_t)(x) & PCFG_STATUS_SEL32K_MASK) >> PCFG_STATUS_SEL32K_SHIFT) + +/* + * SEL24M (RO) + * + * track is using XTAL24M + * 0: track is not using XTAL24M + * 1: track is using XTAL24M + */ +#define PCFG_STATUS_SEL24M_MASK (0x10000UL) +#define PCFG_STATUS_SEL24M_SHIFT (16U) +#define PCFG_STATUS_SEL24M_GET(x) (((uint32_t)(x) & PCFG_STATUS_SEL24M_MASK) >> PCFG_STATUS_SEL24M_SHIFT) + +/* + * EN_TRIM (RO) + * + * default value takes effect + * 0: default value is invalid + * 1: default value is valid + */ +#define PCFG_STATUS_EN_TRIM_MASK (0x8000U) +#define PCFG_STATUS_EN_TRIM_SHIFT (15U) +#define PCFG_STATUS_EN_TRIM_GET(x) (((uint32_t)(x) & PCFG_STATUS_EN_TRIM_MASK) >> PCFG_STATUS_EN_TRIM_SHIFT) + +/* + * TRIM_C (RO) + * + * default coarse trim value + */ +#define PCFG_STATUS_TRIM_C_MASK (0x700U) +#define PCFG_STATUS_TRIM_C_SHIFT (8U) +#define PCFG_STATUS_TRIM_C_GET(x) (((uint32_t)(x) & PCFG_STATUS_TRIM_C_MASK) >> PCFG_STATUS_TRIM_C_SHIFT) + +/* + * TRIM_F (RO) + * + * default fine trim value + */ +#define PCFG_STATUS_TRIM_F_MASK (0x1FU) +#define PCFG_STATUS_TRIM_F_SHIFT (0U) +#define PCFG_STATUS_TRIM_F_GET(x) (((uint32_t)(x) & PCFG_STATUS_TRIM_F_MASK) >> PCFG_STATUS_TRIM_F_SHIFT) + + + + +#endif /* HPM_PCFG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_pdgo_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_pdgo_regs.h new file mode 100644 index 00000000000..5f4c0feeb19 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_pdgo_regs.h @@ -0,0 +1,228 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PDGO_H +#define HPM_PDGO_H + +typedef struct { + __W uint32_t DGO_TURNOFF; /* 0x0: trunoff control */ + __RW uint32_t DGO_RC32K_CFG; /* 0x4: RC32K CLOCK */ + __R uint8_t RESERVED0[1528]; /* 0x8 - 0x5FF: Reserved */ + __RW uint32_t DGO_GPR00; /* 0x600: Generic control 0 */ + __RW uint32_t DGO_GPR01; /* 0x604: Generic control 1 */ + __RW uint32_t DGO_GPR02; /* 0x608: Generic control 2 */ + __RW uint32_t DGO_GPR03; /* 0x60C: Generic control 3 */ + __R uint8_t RESERVED1[240]; /* 0x610 - 0x6FF: Reserved */ + __RW uint32_t DGO_CTR0; /* 0x700: control register 0 */ + __RW uint32_t DGO_CTR1; /* 0x704: control register 1 */ + __RW uint32_t DGO_CTR2; /* 0x708: control register 2 */ + __RW uint32_t DGO_CTR3; /* 0x70C: control register 3 */ + __RW uint32_t DGO_CTR4; /* 0x710: control register 4 */ +} PDGO_Type; + + +/* Bitfield definition for register: DGO_TURNOFF */ +/* + * COUNTER (WO) + * + * trunoff counter, counter stops when it counts down to 0, the trunoff occurs when the counter value is 1. + */ +#define PDGO_DGO_TURNOFF_COUNTER_MASK (0xFFFFFFFFUL) +#define PDGO_DGO_TURNOFF_COUNTER_SHIFT (0U) +#define PDGO_DGO_TURNOFF_COUNTER_SET(x) (((uint32_t)(x) << PDGO_DGO_TURNOFF_COUNTER_SHIFT) & PDGO_DGO_TURNOFF_COUNTER_MASK) +#define PDGO_DGO_TURNOFF_COUNTER_GET(x) (((uint32_t)(x) & PDGO_DGO_TURNOFF_COUNTER_MASK) >> PDGO_DGO_TURNOFF_COUNTER_SHIFT) + +/* Bitfield definition for register: DGO_RC32K_CFG */ +/* + * IRC_TRIMMED (RW) + * + * IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value + * 0: irc is not trimmed + * 1: irc is trimmed + */ +#define PDGO_DGO_RC32K_CFG_IRC_TRIMMED_MASK (0x80000000UL) +#define PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SHIFT (31U) +#define PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SET(x) (((uint32_t)(x) << PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SHIFT) & PDGO_DGO_RC32K_CFG_IRC_TRIMMED_MASK) +#define PDGO_DGO_RC32K_CFG_IRC_TRIMMED_GET(x) (((uint32_t)(x) & PDGO_DGO_RC32K_CFG_IRC_TRIMMED_MASK) >> PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SHIFT) + +/* + * CAPEX7_TRIM (RW) + * + * IRC32K bit 7 + */ +#define PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_MASK (0x800000UL) +#define PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SHIFT (23U) +#define PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SET(x) (((uint32_t)(x) << PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SHIFT) & PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_MASK) +#define PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_GET(x) (((uint32_t)(x) & PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_MASK) >> PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SHIFT) + +/* + * CAPEX6_TRIM (RW) + * + * IRC32K bit 6 + */ +#define PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_MASK (0x400000UL) +#define PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SHIFT (22U) +#define PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SET(x) (((uint32_t)(x) << PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SHIFT) & PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_MASK) +#define PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_GET(x) (((uint32_t)(x) & PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_MASK) >> PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SHIFT) + +/* + * CAP_TRIM (RW) + * + * capacitor trim bits + */ +#define PDGO_DGO_RC32K_CFG_CAP_TRIM_MASK (0x1FFU) +#define PDGO_DGO_RC32K_CFG_CAP_TRIM_SHIFT (0U) +#define PDGO_DGO_RC32K_CFG_CAP_TRIM_SET(x) (((uint32_t)(x) << PDGO_DGO_RC32K_CFG_CAP_TRIM_SHIFT) & PDGO_DGO_RC32K_CFG_CAP_TRIM_MASK) +#define PDGO_DGO_RC32K_CFG_CAP_TRIM_GET(x) (((uint32_t)(x) & PDGO_DGO_RC32K_CFG_CAP_TRIM_MASK) >> PDGO_DGO_RC32K_CFG_CAP_TRIM_SHIFT) + +/* Bitfield definition for register: DGO_GPR00 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PDGO_DGO_GPR00_GPR_MASK (0xFFFFFFFFUL) +#define PDGO_DGO_GPR00_GPR_SHIFT (0U) +#define PDGO_DGO_GPR00_GPR_SET(x) (((uint32_t)(x) << PDGO_DGO_GPR00_GPR_SHIFT) & PDGO_DGO_GPR00_GPR_MASK) +#define PDGO_DGO_GPR00_GPR_GET(x) (((uint32_t)(x) & PDGO_DGO_GPR00_GPR_MASK) >> PDGO_DGO_GPR00_GPR_SHIFT) + +/* Bitfield definition for register: DGO_GPR01 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PDGO_DGO_GPR01_GPR_MASK (0xFFFFFFFFUL) +#define PDGO_DGO_GPR01_GPR_SHIFT (0U) +#define PDGO_DGO_GPR01_GPR_SET(x) (((uint32_t)(x) << PDGO_DGO_GPR01_GPR_SHIFT) & PDGO_DGO_GPR01_GPR_MASK) +#define PDGO_DGO_GPR01_GPR_GET(x) (((uint32_t)(x) & PDGO_DGO_GPR01_GPR_MASK) >> PDGO_DGO_GPR01_GPR_SHIFT) + +/* Bitfield definition for register: DGO_GPR02 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PDGO_DGO_GPR02_GPR_MASK (0xFFFFFFFFUL) +#define PDGO_DGO_GPR02_GPR_SHIFT (0U) +#define PDGO_DGO_GPR02_GPR_SET(x) (((uint32_t)(x) << PDGO_DGO_GPR02_GPR_SHIFT) & PDGO_DGO_GPR02_GPR_MASK) +#define PDGO_DGO_GPR02_GPR_GET(x) (((uint32_t)(x) & PDGO_DGO_GPR02_GPR_MASK) >> PDGO_DGO_GPR02_GPR_SHIFT) + +/* Bitfield definition for register: DGO_GPR03 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PDGO_DGO_GPR03_GPR_MASK (0xFFFFFFFFUL) +#define PDGO_DGO_GPR03_GPR_SHIFT (0U) +#define PDGO_DGO_GPR03_GPR_SET(x) (((uint32_t)(x) << PDGO_DGO_GPR03_GPR_SHIFT) & PDGO_DGO_GPR03_GPR_MASK) +#define PDGO_DGO_GPR03_GPR_GET(x) (((uint32_t)(x) & PDGO_DGO_GPR03_GPR_MASK) >> PDGO_DGO_GPR03_GPR_SHIFT) + +/* Bitfield definition for register: DGO_CTR0 */ +/* + * RETENTION (RW) + * + * dgo register status retenion + */ +#define PDGO_DGO_CTR0_RETENTION_MASK (0x10000UL) +#define PDGO_DGO_CTR0_RETENTION_SHIFT (16U) +#define PDGO_DGO_CTR0_RETENTION_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR0_RETENTION_SHIFT) & PDGO_DGO_CTR0_RETENTION_MASK) +#define PDGO_DGO_CTR0_RETENTION_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR0_RETENTION_MASK) >> PDGO_DGO_CTR0_RETENTION_SHIFT) + +/* Bitfield definition for register: DGO_CTR1 */ +/* + * AOTO_SYS_WAKEUP (RW) + * + * software wakeup： 0 : wakeup once； 1：auto wakeup Continuously + */ +#define PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK (0x80000000UL) +#define PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SHIFT (31U) +#define PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SHIFT) & PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK) +#define PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK) >> PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SHIFT) + +/* + * WAKEUP_EN (RW) + * + * permit wakeup pin or software wakeup + */ +#define PDGO_DGO_CTR1_WAKEUP_EN_MASK (0x10000UL) +#define PDGO_DGO_CTR1_WAKEUP_EN_SHIFT (16U) +#define PDGO_DGO_CTR1_WAKEUP_EN_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR1_WAKEUP_EN_SHIFT) & PDGO_DGO_CTR1_WAKEUP_EN_MASK) +#define PDGO_DGO_CTR1_WAKEUP_EN_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR1_WAKEUP_EN_MASK) >> PDGO_DGO_CTR1_WAKEUP_EN_SHIFT) + +/* + * PIN_WAKEUP_STATUS (RO) + * + * wakeup pin status + */ +#define PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_MASK (0x1U) +#define PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_SHIFT (0U) +#define PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_MASK) >> PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_SHIFT) + +/* Bitfield definition for register: DGO_CTR2 */ +/* + * RESETN_PULLUP_DISABLE (RW) + * + * resetn pin pull up disable + */ +#define PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_MASK (0x1000000UL) +#define PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SHIFT (24U) +#define PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SHIFT) & PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_MASK) +#define PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_MASK) >> PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SHIFT) + +/* + * WAKEUP_PULLDN_DISABLE (RW) + * + * wakeup pin pull down disable + */ +#define PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_MASK (0x10000UL) +#define PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SHIFT (16U) +#define PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SHIFT) & PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_MASK) +#define PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_MASK) >> PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SHIFT) + +/* Bitfield definition for register: DGO_CTR3 */ +/* + * WAKEUP_COUNTER (RW) + * + * software wakeup counter + */ +#define PDGO_DGO_CTR3_WAKEUP_COUNTER_MASK (0xFFFFFFFFUL) +#define PDGO_DGO_CTR3_WAKEUP_COUNTER_SHIFT (0U) +#define PDGO_DGO_CTR3_WAKEUP_COUNTER_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR3_WAKEUP_COUNTER_SHIFT) & PDGO_DGO_CTR3_WAKEUP_COUNTER_MASK) +#define PDGO_DGO_CTR3_WAKEUP_COUNTER_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR3_WAKEUP_COUNTER_MASK) >> PDGO_DGO_CTR3_WAKEUP_COUNTER_SHIFT) + +/* Bitfield definition for register: DGO_CTR4 */ +/* + * BANDGAP_LESS_POWER (RW) + * + * Banggap work in power save mode, banggap function normally + * 0: banggap works in high performance mode + * 1: banggap works in power saving mode + */ +#define PDGO_DGO_CTR4_BANDGAP_LESS_POWER_MASK (0x2U) +#define PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SHIFT (1U) +#define PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SHIFT) & PDGO_DGO_CTR4_BANDGAP_LESS_POWER_MASK) +#define PDGO_DGO_CTR4_BANDGAP_LESS_POWER_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR4_BANDGAP_LESS_POWER_MASK) >> PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SHIFT) + +/* + * BANDGAP_LP_MODE (RW) + * + * Banggap work in low power mode, banggap function limited + * 0: banggap works in normal mode + * 1: banggap works in low power mode + */ +#define PDGO_DGO_CTR4_BANDGAP_LP_MODE_MASK (0x1U) +#define PDGO_DGO_CTR4_BANDGAP_LP_MODE_SHIFT (0U) +#define PDGO_DGO_CTR4_BANDGAP_LP_MODE_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR4_BANDGAP_LP_MODE_SHIFT) & PDGO_DGO_CTR4_BANDGAP_LP_MODE_MASK) +#define PDGO_DGO_CTR4_BANDGAP_LP_MODE_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR4_BANDGAP_LP_MODE_MASK) >> PDGO_DGO_CTR4_BANDGAP_LP_MODE_SHIFT) + + + + +#endif /* HPM_PDGO_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_pgpr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_pgpr_regs.h new file mode 100644 index 00000000000..acf20cfecd5 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_pgpr_regs.h @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PGPR_H +#define HPM_PGPR_H + +typedef struct { + __RW uint32_t PMIC_GPR00; /* 0x0: Generic control */ + __RW uint32_t PMIC_GPR01; /* 0x4: Generic control */ + __RW uint32_t PMIC_GPR02; /* 0x8: Generic control */ + __RW uint32_t PMIC_GPR03; /* 0xC: Generic control */ + __RW uint32_t PMIC_GPR04; /* 0x10: Generic control */ + __RW uint32_t PMIC_GPR05; /* 0x14: Generic control */ + __RW uint32_t PMIC_GPR06; /* 0x18: Generic control */ + __RW uint32_t PMIC_GPR07; /* 0x1C: Generic control */ + __RW uint32_t PMIC_GPR08; /* 0x20: Generic control */ + __RW uint32_t PMIC_GPR09; /* 0x24: Generic control */ + __RW uint32_t PMIC_GPR10; /* 0x28: Generic control */ + __RW uint32_t PMIC_GPR11; /* 0x2C: Generic control */ + __RW uint32_t PMIC_GPR12; /* 0x30: Generic control */ + __RW uint32_t PMIC_GPR13; /* 0x34: Generic control */ + __RW uint32_t PMIC_GPR14; /* 0x38: Generic control */ + __RW uint32_t PMIC_GPR15; /* 0x3C: Generic control */ +} PGPR_Type; + + +/* Bitfield definition for register: PMIC_GPR00 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR00_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR00_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR00_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR00_GPR_SHIFT) & PGPR_PMIC_GPR00_GPR_MASK) +#define PGPR_PMIC_GPR00_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR00_GPR_MASK) >> PGPR_PMIC_GPR00_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR01 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR01_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR01_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR01_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR01_GPR_SHIFT) & PGPR_PMIC_GPR01_GPR_MASK) +#define PGPR_PMIC_GPR01_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR01_GPR_MASK) >> PGPR_PMIC_GPR01_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR02 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR02_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR02_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR02_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR02_GPR_SHIFT) & PGPR_PMIC_GPR02_GPR_MASK) +#define PGPR_PMIC_GPR02_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR02_GPR_MASK) >> PGPR_PMIC_GPR02_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR03 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR03_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR03_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR03_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR03_GPR_SHIFT) & PGPR_PMIC_GPR03_GPR_MASK) +#define PGPR_PMIC_GPR03_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR03_GPR_MASK) >> PGPR_PMIC_GPR03_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR04 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR04_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR04_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR04_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR04_GPR_SHIFT) & PGPR_PMIC_GPR04_GPR_MASK) +#define PGPR_PMIC_GPR04_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR04_GPR_MASK) >> PGPR_PMIC_GPR04_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR05 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR05_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR05_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR05_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR05_GPR_SHIFT) & PGPR_PMIC_GPR05_GPR_MASK) +#define PGPR_PMIC_GPR05_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR05_GPR_MASK) >> PGPR_PMIC_GPR05_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR06 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR06_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR06_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR06_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR06_GPR_SHIFT) & PGPR_PMIC_GPR06_GPR_MASK) +#define PGPR_PMIC_GPR06_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR06_GPR_MASK) >> PGPR_PMIC_GPR06_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR07 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR07_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR07_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR07_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR07_GPR_SHIFT) & PGPR_PMIC_GPR07_GPR_MASK) +#define PGPR_PMIC_GPR07_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR07_GPR_MASK) >> PGPR_PMIC_GPR07_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR08 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR08_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR08_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR08_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR08_GPR_SHIFT) & PGPR_PMIC_GPR08_GPR_MASK) +#define PGPR_PMIC_GPR08_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR08_GPR_MASK) >> PGPR_PMIC_GPR08_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR09 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR09_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR09_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR09_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR09_GPR_SHIFT) & PGPR_PMIC_GPR09_GPR_MASK) +#define PGPR_PMIC_GPR09_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR09_GPR_MASK) >> PGPR_PMIC_GPR09_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR10 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR10_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR10_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR10_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR10_GPR_SHIFT) & PGPR_PMIC_GPR10_GPR_MASK) +#define PGPR_PMIC_GPR10_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR10_GPR_MASK) >> PGPR_PMIC_GPR10_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR11 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR11_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR11_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR11_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR11_GPR_SHIFT) & PGPR_PMIC_GPR11_GPR_MASK) +#define PGPR_PMIC_GPR11_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR11_GPR_MASK) >> PGPR_PMIC_GPR11_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR12 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR12_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR12_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR12_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR12_GPR_SHIFT) & PGPR_PMIC_GPR12_GPR_MASK) +#define PGPR_PMIC_GPR12_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR12_GPR_MASK) >> PGPR_PMIC_GPR12_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR13 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR13_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR13_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR13_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR13_GPR_SHIFT) & PGPR_PMIC_GPR13_GPR_MASK) +#define PGPR_PMIC_GPR13_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR13_GPR_MASK) >> PGPR_PMIC_GPR13_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR14 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR14_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR14_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR14_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR14_GPR_SHIFT) & PGPR_PMIC_GPR14_GPR_MASK) +#define PGPR_PMIC_GPR14_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR14_GPR_MASK) >> PGPR_PMIC_GPR14_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR15 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR15_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR15_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR15_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR15_GPR_SHIFT) & PGPR_PMIC_GPR15_GPR_MASK) +#define PGPR_PMIC_GPR15_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR15_GPR_MASK) >> PGPR_PMIC_GPR15_GPR_SHIFT) + + + + +#endif /* HPM_PGPR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_plic_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_plic_drv.h new file mode 100644 index 00000000000..4c96737ece4 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_plic_drv.h @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PLIC_DRV_H +#define HPM_PLIC_DRV_H + +/** + * @brief PLIC driver APIs + * @defgroup plic_interface PLIC driver APIs + * @{ + */ + +#define HPM_PLIC_TARGET_M_MODE 0 +#define HPM_PLIC_TARGET_S_MODE 1 + +/* Feature Register */ +#define HPM_PLIC_FEATURE_OFFSET (0x00000000UL) +#define HPM_PLIC_FEATURE_VECTORED_MODE (0x2UL) +#define HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ (0x1UL) + +/* Priority Register - 32 bits per irq */ +#define HPM_PLIC_PRIORITY_OFFSET (0x00000004UL) +#define HPM_PLIC_PRIORITY_SHIFT_PER_SOURCE 2 + +/* Pending Register - 1 bit per source */ +#define HPM_PLIC_PENDING_OFFSET (0x00001000UL) +#define HPM_PLIC_PENDING_SHIFT_PER_SOURCE 0 + +#define HPM_PLIC_TRIGGER_TYPE_OFFSET (0x00001080UL) +#define HPM_PLIC_TRIGGER_TYPE_SHIFT_PER_SORUCE 1 + +/* Enable Register - 0x80 per target */ +#define HPM_PLIC_ENABLE_OFFSET (0x00002000UL) +#define HPM_PLIC_ENABLE_SHIFT_PER_TARGET 7 + +/* Priority Threshold Register - 0x1000 per target */ +#define HPM_PLIC_THRESHOLD_OFFSET (0x00200000UL) +#define HPM_PLIC_THRESHOLD_SHIFT_PER_TARGET 12 + + +/* Claim Register - 0x1000 per target */ +#define HPM_PLIC_CLAIM_OFFSET (0x00200004UL) +#define HPM_PLIC_CLAIM_SHIFT_PER_TARGET 12 + +#if !defined(__ASSEMBLER__) + +/** + * @brief Set plic feature + * + * @param[in] base PLIC base address + * @param[in] feature Specific feature to be set + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_set_feature(uint32_t base, uint32_t feature) +{ + *(volatile uint32_t *) (base + HPM_PLIC_FEATURE_OFFSET) = feature; +} + +/** + * @brief Set plic threshold + * + * @param[in] base PLIC base address + * @param[in] target Target to handle specific interrupt + * @param[in] threshold Threshold of IRQ can be serviced + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_set_threshold(uint32_t base, + uint32_t target, + uint32_t threshold) +{ + volatile uint32_t *threshold_ptr = (volatile uint32_t *) (base + + HPM_PLIC_THRESHOLD_OFFSET + + (target << HPM_PLIC_THRESHOLD_SHIFT_PER_TARGET)); + *threshold_ptr = threshold; +} + +/** + * @brief Set interrupt priority + * + * @param[in] base PLIC base address + * @param[in] irq Target interrupt number + * @param[in] priority Priority to be assigned + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_set_irq_priority(uint32_t base, + uint32_t irq, + uint32_t priority) +{ + volatile uint32_t *priority_ptr = (volatile uint32_t *) (base + + HPM_PLIC_PRIORITY_OFFSET + + ((irq - 1) << HPM_PLIC_PRIORITY_SHIFT_PER_SOURCE)); + *priority_ptr = priority; +} + +/** + * @brief Set interrupt pending bit + * + * @param[in] base PLIC base address + * @param[in] irq Target interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_set_irq_pending(uint32_t base, uint32_t irq) +{ + volatile uint32_t *current_ptr = (volatile uint32_t *) (base + + HPM_PLIC_PENDING_OFFSET + ((irq >> 5) << 2)); + *current_ptr = (1 << (irq & 0x1F)); +} + +/** + * @brief Set interrupt trigger type to edge-triggerred + * + * @param[in] base PLIC base address + * @param[in] irq Target interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_enable_irq_edge_trigger(uint32_t base, uint32_t irq) +{ + volatile uint32_t *current_ptr = (volatile uint32_t *) (base + + HPM_PLIC_TRIGGER_TYPE_OFFSET + ((irq >> 5) << 2)); + *current_ptr |= (1UL << (irq & 0x1F)); +} + +/** + * @brief Set interrupt trigger type to level-triggerred + * + * @param[in] base PLIC base address + * @param[in] irq Target interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_enable_irq_level_trigger(uint32_t base, uint32_t irq) +{ + volatile uint32_t *current_ptr = (volatile uint32_t *) (base + + HPM_PLIC_TRIGGER_TYPE_OFFSET + ((irq >> 5) << 2)); + *current_ptr &= ~(1UL << (irq & 0x1F)); +} + +/** + * @brief Enable interrupt + * + * @param[in] base PLIC base address + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number to be enabled + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_enable_irq(uint32_t base, + uint32_t target, + uint32_t irq) +{ + volatile uint32_t *current_ptr = (volatile uint32_t *) (base + + HPM_PLIC_ENABLE_OFFSET + + (target << HPM_PLIC_ENABLE_SHIFT_PER_TARGET) + + ((irq >> 5) << 2)); + uint32_t current = *current_ptr; + current = current | (1 << (irq & 0x1F)); + *current_ptr = current; +} + +/** + * @brief Disable interrupt + * + * @param[in] base PLIC base address + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number to be disabled + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_disable_irq(uint32_t base, + uint32_t target, + uint32_t irq) +{ + volatile uint32_t *current_ptr = (volatile uint32_t *) (base + + HPM_PLIC_ENABLE_OFFSET + + (target << HPM_PLIC_ENABLE_SHIFT_PER_TARGET) + + ((irq >> 5) << 2)); + uint32_t current = *current_ptr; + current = current & ~((1 << (irq & 0x1F))); + *current_ptr = current; +} + +/** + * @brief Claim interrupt + * + * @param[in] base PLIC base address + * @param[in] target Target to claim interrupt + * + */ +ATTR_ALWAYS_INLINE static inline uint32_t __plic_claim_irq(uint32_t base, uint32_t target) +{ + volatile uint32_t *claim_addr = (volatile uint32_t *) (base + + HPM_PLIC_CLAIM_OFFSET + + (target << HPM_PLIC_CLAIM_SHIFT_PER_TARGET)); + return *claim_addr; +} + +/** + * @brief Complete interrupt + * + * @param[in] base PLIC base address + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_complete_irq(uint32_t base, + uint32_t target, + uint32_t irq) +{ + volatile uint32_t *claim_addr = (volatile uint32_t *) (base + + HPM_PLIC_CLAIM_OFFSET + + (target << HPM_PLIC_CLAIM_SHIFT_PER_TARGET)); + *claim_addr = irq; +} + +#endif /* __ASSEMBLER__ */ +/** + * @} + */ +#endif /* HPM_PLIC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_pmic_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_pmic_iomux.h new file mode 100644 index 00000000000..a95ce61e50f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_pmic_iomux.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PMIC_IOMUX_H +#define HPM_PMIC_IOMUX_H + +/* PIOC_PY00_FUNC_CTL function mux definitions */ +#define IOC_PY00_FUNC_CTL_PGPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY00_FUNC_CTL_PGPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY00_FUNC_CTL_PUART_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY00_FUNC_CTL_PUART_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY00_FUNC_CTL_SOC_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY00_FUNC_CTL_SOC_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY01_FUNC_CTL function mux definitions */ +#define IOC_PY01_FUNC_CTL_PGPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY01_FUNC_CTL_PGPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY01_FUNC_CTL_PUART_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY01_FUNC_CTL_PUART_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY01_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY01_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY01_FUNC_CTL_SOC_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY01_FUNC_CTL_SOC_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY02_FUNC_CTL function mux definitions */ +#define IOC_PY02_FUNC_CTL_PGPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY02_FUNC_CTL_PGPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY02_FUNC_CTL_PUART_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY02_FUNC_CTL_PUART_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY02_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY02_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY02_FUNC_CTL_SOC_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY02_FUNC_CTL_SOC_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY03_FUNC_CTL function mux definitions */ +#define IOC_PY03_FUNC_CTL_PGPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY03_FUNC_CTL_PGPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY03_FUNC_CTL_PUART_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY03_FUNC_CTL_PUART_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY03_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY03_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY03_FUNC_CTL_SOC_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY03_FUNC_CTL_SOC_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY04_FUNC_CTL function mux definitions */ +#define IOC_PY04_FUNC_CTL_PGPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY04_FUNC_CTL_PGPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY04_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY04_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY04_FUNC_CTL_SOC_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY04_FUNC_CTL_SOC_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY05_FUNC_CTL function mux definitions */ +#define IOC_PY05_FUNC_CTL_PGPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY05_FUNC_CTL_PGPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY05_FUNC_CTL_PEWDG_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY05_FUNC_CTL_PEWDG_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY05_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY05_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY05_FUNC_CTL_SOC_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY05_FUNC_CTL_SOC_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY06_FUNC_CTL function mux definitions */ +#define IOC_PY06_FUNC_CTL_PGPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY06_FUNC_CTL_PGPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY06_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY06_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY06_FUNC_CTL_SOC_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY06_FUNC_CTL_SOC_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY07_FUNC_CTL function mux definitions */ +#define IOC_PY07_FUNC_CTL_PGPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY07_FUNC_CTL_PGPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY07_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY07_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY07_FUNC_CTL_SOC_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY07_FUNC_CTL_SOC_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + + +#endif /* HPM_PMIC_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_ppor_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_ppor_drv.h new file mode 100644 index 00000000000..bc7ee37f6ad --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_ppor_drv.h @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PPOR_DRV_H +#define HPM_PPOR_DRV_H +#include "hpm_ppor_regs.h" + +typedef enum { + ppor_reset_brownout = 1 << 0, + ppor_reset_debug = 1 << 4, + ppor_reset_wdog0 = 1 << 16, + ppor_reset_wdog1 = 1 << 17, + ppor_reset_pmic_wdog = 1 << 24, + ppor_reset_software = 1 << 31, +} ppor_reset_source_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * perform software reset in counter * (1/24Mhz) seconds + */ +static inline void ppor_sw_reset(PPOR_Type *ptr, uint32_t counter) +{ + ptr->SOFTWARE_RESET = PPOR_SOFTWARE_RESET_COUNTER_SET(counter); } + +/* + * clear enable reset source according to the given mask + */ +static inline void ppor_reset_mask_clear_source_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_ENABLE &= ~mask; +} + +/* + * set enable reset source according to the given mask + */ +static inline void ppor_reset_mask_set_source_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_ENABLE |= mask; +} + +/* + * set enable reset source + */ +static inline void ppor_reset_set_source_enable(PPOR_Type *ptr, uint32_t reset_sources) +{ + ptr->RESET_ENABLE = reset_sources; +} + +/* + * get enabled reset source + */ +static inline uint32_t ppor_reset_get_enabled_source(PPOR_Type *ptr) +{ + return ptr->RESET_ENABLE; +} + +/* + * get reset status + */ +static inline uint32_t ppor_reset_get_status(PPOR_Type *ptr) +{ + return ptr->RESET_STATUS; +} + +/* + * get reset flags + */ +static inline uint32_t ppor_reset_get_flags(PPOR_Type *ptr) +{ + return ptr->RESET_FLAG; +} + +/* + * clear reset flags + */ +static inline void ppor_reset_clear_flags(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_FLAG = mask; +} + +/* + * get reset hold + */ +static inline uint32_t ppor_reset_get_hold(PPOR_Type *ptr) +{ + return ptr->RESET_HOLD; +} + +/* + * set reset hold + */ +static inline void ppor_reset_set_hold_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_HOLD |= mask; +} + +/* + * clear reset hold + */ +static inline void ppor_reset_clear_hold_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_HOLD &= ~mask; +} + +/* + * set cold reset + */ +static inline void ppor_reset_set_cold_reset_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_TYPE &= ~mask; +} + +/* + * clear cold reset + */ +static inline void ppor_reset_clear_cold_reset_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_TYPE |= mask; +} + +/* + * set hot reset + */ +static inline void ppor_reset_set_hot_reset_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_TYPE |= mask; +} + +/* + * clear hot reset + */ +static inline void ppor_reset_clear_hot_reset_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_TYPE &= ~mask; +} + + +#ifdef __cplusplus +} +#endif +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_ppor_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_ppor_regs.h new file mode 100644 index 00000000000..32f5f6bcc61 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_ppor_regs.h @@ -0,0 +1,166 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PPOR_H +#define HPM_PPOR_H + +typedef struct { + __W uint32_t RESET_FLAG; /* 0x0: flag indicate reset source */ + __R uint32_t RESET_STATUS; /* 0x4: reset source status */ + __RW uint32_t RESET_HOLD; /* 0x8: reset hold attribute */ + __RW uint32_t RESET_ENABLE; /* 0xC: reset source enable */ + __RW uint32_t RESET_TYPE; /* 0x10: reset type triggered by reset */ + __R uint8_t RESERVED0[8]; /* 0x14 - 0x1B: Reserved */ + __RW uint32_t SOFTWARE_RESET; /* 0x1C: Software reset counter */ +} PPOR_Type; + + +/* Bitfield definition for register: RESET_FLAG */ +/* + * FLAG (W1C) + * + * reset reason of last hard reset, write 1 to clear each bit + * 0: brownout + * 1: temperature + * 4: debug reset + * 5: jtag soft reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2(not available) + * 19: watch dog 3(not available) + * 24: pmic watch dog + * 30: jtag ieee reset + * 31: software + */ +#define PPOR_RESET_FLAG_FLAG_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_FLAG_FLAG_SHIFT (0U) +#define PPOR_RESET_FLAG_FLAG_SET(x) (((uint32_t)(x) << PPOR_RESET_FLAG_FLAG_SHIFT) & PPOR_RESET_FLAG_FLAG_MASK) +#define PPOR_RESET_FLAG_FLAG_GET(x) (((uint32_t)(x) & PPOR_RESET_FLAG_FLAG_MASK) >> PPOR_RESET_FLAG_FLAG_SHIFT) + +/* Bitfield definition for register: RESET_STATUS */ +/* + * STATUS (RO) + * + * current status of reset sources + * 0: brownout + * 1: temperature + * 4: debug reset + * 5: jtag soft reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2(not available) + * 19: watch dog 3(not available) + * 24: pmic watch dog + * 30: jtag ieee reset + * 31: software + */ +#define PPOR_RESET_STATUS_STATUS_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_STATUS_STATUS_SHIFT (0U) +#define PPOR_RESET_STATUS_STATUS_GET(x) (((uint32_t)(x) & PPOR_RESET_STATUS_STATUS_MASK) >> PPOR_RESET_STATUS_STATUS_SHIFT) + +/* Bitfield definition for register: RESET_HOLD */ +/* + * HOLD (RW) + * + * hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status + * 0: brownout + * 1: temperature + * 4: debug reset + * 5: jtag soft reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2(not available) + * 19: watch dog 3(not available) + * 24: pmic watch dog + * 30: jtag ieee reset + * 31: software + */ +#define PPOR_RESET_HOLD_HOLD_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_HOLD_HOLD_SHIFT (0U) +#define PPOR_RESET_HOLD_HOLD_SET(x) (((uint32_t)(x) << PPOR_RESET_HOLD_HOLD_SHIFT) & PPOR_RESET_HOLD_HOLD_MASK) +#define PPOR_RESET_HOLD_HOLD_GET(x) (((uint32_t)(x) & PPOR_RESET_HOLD_HOLD_MASK) >> PPOR_RESET_HOLD_HOLD_SHIFT) + +/* Bitfield definition for register: RESET_ENABLE */ +/* + * ENABLE (RW) + * + * enable of reset sources + * 0: brownout + * 1: temperature + * 4: debug reset + * 5: jtag soft reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2(not available) + * 19: watch dog 3(not available) + * 24: pmic watch dog + * 30: jtag ieee reset + * 31: software + */ +#define PPOR_RESET_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_ENABLE_ENABLE_SHIFT (0U) +#define PPOR_RESET_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << PPOR_RESET_ENABLE_ENABLE_SHIFT) & PPOR_RESET_ENABLE_ENABLE_MASK) +#define PPOR_RESET_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & PPOR_RESET_ENABLE_ENABLE_MASK) >> PPOR_RESET_ENABLE_ENABLE_SHIFT) + +/* Bitfield definition for register: RESET_TYPE */ +/* + * TYPE (RW) + * + * reset type of reset sources, 0 for cold reset, all system control setting cleared except debug/fuse/ioc; 1 for hot reset, keep system control setting and debug/fuse/ioc setting, only clear some subsystem + * 0: brownout + * 1: temperature + * 4: debug reset + * 5: jtag soft reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2(not available) + * 19: watch dog 3(not available) + * 24: pmic watch dog + * 30: jtag ieee reset + * 31: software + */ +#define PPOR_RESET_TYPE_TYPE_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_TYPE_TYPE_SHIFT (0U) +#define PPOR_RESET_TYPE_TYPE_SET(x) (((uint32_t)(x) << PPOR_RESET_TYPE_TYPE_SHIFT) & PPOR_RESET_TYPE_TYPE_MASK) +#define PPOR_RESET_TYPE_TYPE_GET(x) (((uint32_t)(x) & PPOR_RESET_TYPE_TYPE_MASK) >> PPOR_RESET_TYPE_TYPE_SHIFT) + +/* Bitfield definition for register: SOFTWARE_RESET */ +/* + * COUNTER (RW) + * + * counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset + */ +#define PPOR_SOFTWARE_RESET_COUNTER_MASK (0xFFFFFFFFUL) +#define PPOR_SOFTWARE_RESET_COUNTER_SHIFT (0U) +#define PPOR_SOFTWARE_RESET_COUNTER_SET(x) (((uint32_t)(x) << PPOR_SOFTWARE_RESET_COUNTER_SHIFT) & PPOR_SOFTWARE_RESET_COUNTER_MASK) +#define PPOR_SOFTWARE_RESET_COUNTER_GET(x) (((uint32_t)(x) & PPOR_SOFTWARE_RESET_COUNTER_MASK) >> PPOR_SOFTWARE_RESET_COUNTER_SHIFT) + + + + +#endif /* HPM_PPOR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_romapi.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_romapi.h new file mode 100644 index 00000000000..c93f04dc914 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_romapi.h @@ -0,0 +1,938 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_ROMAPI_H +#define HPM_ROMAPI_H + +/** + * @brief ROM APIs + * @defgroup romapi_interface ROM APIs + * @{ + */ + +#include "hpm_common.h" +#include "hpm_otp_drv.h" +#include "hpm_romapi_xpi_def.h" +#include "hpm_romapi_xpi_soc_def.h" +#include "hpm_romapi_xpi_nor_def.h" +#include "hpm_romapi_xpi_ram_def.h" +#include "hpm_sdp_drv.h" + +/* XPI0 base address */ +#define HPM_XPI0_BASE (0xF3000000UL) /**< XPI0 Base address */ +/* XPI0 base pointer */ +#define HPM_XPI0 ((XPI_Type *) HPM_XPI0_BASE) /**< XPI0 Base pointer */ + + +/*********************************************************************************************************************** + * + * + * Definitions + * + * + **********************************************************************************************************************/ +/** + * @brief Enter Bootloader API argument + */ +typedef union { + uint32_t U; + struct { + uint32_t index: 8; /**< Image index */ + uint32_t peripheral: 8; /**< Boot peripheral */ + uint32_t src: 8; /**< Boot source */ + uint32_t tag: 8; /**< ROM API parameter tag, must be 0xEB */ + }; +} api_boot_arg_t; + +/*EXiP Region Parameter */ +typedef struct { + uint32_t start; /**< Start address, must be 4KB aligned */ + uint32_t len; /**< Must be 4KB aligned */ + uint8_t key[16]; /**< AES Key */ + uint8_t ctr[8]; /**< Initial Vector/Counter */ +} exip_region_param_t; + +typedef struct { + uint32_t region_start; + uint32_t region_end; + uint8_t aes_key[16]; + uint8_t nonce[8]; + uint8_t index; + bool enable; + bool valid; + bool lock; +} exip_region_context_t; + +#define API_BOOT_TAG (0xEBU) /**< ROM API parameter tag */ +#define API_BOOT_SRC_OTP (0U) /**< Boot source: OTP */ +#define API_BOOT_SRC_PRIMARY (1U) /**< Boot source: Primary */ +#define API_BOOT_SRC_SERIAL_BOOT (2U) /**< Boot source: Serial Boot */ +#define API_BOOT_SRC_ISP (3U) /**< Boot source: ISP */ +#define API_BOOT_PERIPH_AUTO (0U) /**< Boot peripheral: Auto detected */ +#define API_BOOT_PERIPH_UART (1U) /**< Boot peripheral: UART */ +#define API_BOOT_PERIPH_USBHID (2U) /**< Boot Peripheral: USB-HID */ + +/** + * @brief OTP driver interface + */ +typedef struct { + /**< OTP driver interface version */ + uint32_t version; + /**< OTP driver interface: init */ + void (*init)(void); + /**< OTP driver interface: deinit */ + void (*deinit)(void); + /**< OTP driver interface: read from shadow */ + uint32_t (*read_from_shadow)(uint32_t addr); + /**< OTP driver interface: read from ip */ + uint32_t (*read_from_ip)(uint32_t addr); + /**< OTP driver interface: program */ + hpm_stat_t (*program)(uint32_t addr, const uint32_t *src, uint32_t num_of_words); + /**< OTP driver interface: reload */ + hpm_stat_t (*reload)(otp_region_t region); + /**< OTP driver interface: lock */ + hpm_stat_t (*lock)(uint32_t addr, otp_lock_option_t lock_option); + /**< OTP driver interface: lock_shadow */ + hpm_stat_t (*lock_shadow)(uint32_t addr, otp_lock_option_t lock_option); + /**< OTP driver interface: set_configurable_region */ + hpm_stat_t (*set_configurable_region)(uint32_t start, uint32_t num_of_words); + /**< OTP driver interface: write_shadow_register */ + hpm_stat_t (*write_shadow_register)(uint32_t addr, uint32_t data); +} otp_driver_interface_t; + +/** + * @brief XPI driver interface + */ +typedef struct { + /**< XPI driver interface: version */ + uint32_t version; + /**< XPI driver interface: get default configuration */ + hpm_stat_t (*get_default_config)(xpi_config_t *xpi_config); + /**< XPI driver interface: get default device configuration */ + hpm_stat_t (*get_default_device_config)(xpi_device_config_t *dev_config); + /**< XPI driver interface: initialize the XPI using xpi_config */ + hpm_stat_t (*init)(XPI_Type *base, xpi_config_t *xpi_config); + /**< XPI driver interface: configure the AHB buffer */ + hpm_stat_t (*config_ahb_buffer)(XPI_Type *base, xpi_ahb_buffer_cfg_t *ahb_buf_cfg); + /**< XPI driver interface: configure the device */ + hpm_stat_t (*config_device)(XPI_Type *base, xpi_device_config_t *dev_cfg, xpi_channel_t channel); + /**< XPI driver interface: update instruction talbe */ + hpm_stat_t (*update_instr_table)(XPI_Type *base, const uint32_t *inst_base, uint32_t seq_idx, uint32_t num); + /**< XPI driver interface: transfer command/data using block interface */ + hpm_stat_t (*transfer_blocking)(XPI_Type *base, xpi_xfer_ctx_t *xfer); + /**< Software reset the XPI controller */ + void (*software_reset)(XPI_Type *base); + /**< XPI driver interface: Check whether IP is idle */ + bool (*is_idle)(XPI_Type *base); + /**< XPI driver interface: update delay line setting */ + void (*update_dllcr)(XPI_Type *base, + uint32_t serial_root_clk_freq, + uint32_t data_valid_time, + xpi_channel_t channel, + uint32_t dly_target); + /**< XPI driver interface: Get absolute address for APB transfer */ + hpm_stat_t + (*get_abs_apb_xfer_addr)(XPI_Type *base, xpi_xfer_channel_t channel, uint32_t in_addr, uint32_t *out_addr); +} xpi_driver_interface_t; + +/** + * @brief XPI NOR driver interface + */ +typedef struct { + /**< XPI NOR driver interface: API version */ + uint32_t version; + /**< XPI NOR driver interface: Get FLASH configuration */ + hpm_stat_t (*get_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option); + /**< XPI NOR driver interface: initialize FLASH */ + hpm_stat_t (*init)(XPI_Type *base, xpi_nor_config_t *nor_config); + /**< XPI NOR driver interface: Enable write access to FLASH */ + hpm_stat_t + (*enable_write)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + /**< XPI NOR driver interface: Get FLASH status register */ + hpm_stat_t (*get_status)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t addr, + uint16_t *out_status); + /**< XPI NOR driver interface: Wait when FLASH is still busy */ + hpm_stat_t + (*wait_busy)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + /**< XPI NOR driver interface: erase a specified FLASH region */ + hpm_stat_t (*erase)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start, + uint32_t length); + /**< XPI NOR driver interface: Erase the whole FLASH */ + hpm_stat_t (*erase_chip)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config); + /**< XPI NOR driver interface: Erase specified FLASH sector */ + hpm_stat_t + (*erase_sector)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + /**< XPI NOR driver interface: Erase specified FLASH block */ + hpm_stat_t + (*erase_block)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + /**< XPI NOR driver interface: Program data to specified FLASH address */ + hpm_stat_t (*program)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + const uint32_t *src, + uint32_t dst_addr, + uint32_t length); + /**< XPI NOR driver interface: read data from specified FLASH address */ + hpm_stat_t (*read)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t *dst, + uint32_t start, + uint32_t length); + /**< XPI NOR driver interface: program FLASH page using nonblocking interface */ + hpm_stat_t (*page_program_nonblocking)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + const uint32_t *src, + uint32_t dst_addr, + uint32_t length); + /**< XPI NOR driver interface: erase FLASH sector using nonblocking interface */ + hpm_stat_t (*erase_sector_nonblocking)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t addr); + /**< XPI NOR driver interface: erase FLASH block using nonblocking interface */ + hpm_stat_t (*erase_block_nonblocking)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t addr); + /**< XPI NOR driver interface: erase the whole FLASh using nonblocking interface */ + hpm_stat_t + (*erase_chip_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config); + + uint32_t reserved0[3]; + + /**< XPI NOR driver interface: automatically configuration flash based on the cfg_option setting */ + hpm_stat_t (*auto_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option); + + /**< XPI NOR driver interface: Get FLASH properties */ + hpm_stat_t (*get_property)(XPI_Type *base, xpi_nor_config_t *nor_cfg, uint32_t property_id, uint32_t *value); + +} xpi_nor_driver_interface_t; + +/** + * @brief EXIP driver interface + */ +typedef struct { + uint32_t version; + hpm_stat_t (*enable)(XPI_Type *base); + hpm_stat_t (*disable)(XPI_Type *base); + hpm_stat_t (*lock_reg_access)(XPI_Type *base); + hpm_stat_t (*configure_region)(XPI_Type *base, const exip_region_context_t *ctx); + + bool (*remap_config)(XPI_Type *base, uint32_t start, uint32_t len, uint32_t offset); + bool (*remap_enabled)(XPI_Type *base); + void (*remap_disable)(XPI_Type *base); + bool (*exip_region_config)(XPI_Type *base, uint32_t index, exip_region_param_t *param); + void (*exip_region_disable)(XPI_Type *base, uint32_t index); +} exip_driver_interface_t; + +/** + * @brief SDP API interface + */ +typedef struct { + /**< SDP API interface: API version */ + uint32_t version; + /**< SDP API interface: Initialize IP */ + hpm_stat_t (*sdp_ip_init)(void); + /**< SDP API interface: Deinitialize IP */ + hpm_stat_t (*sdp_ip_deinit)(void); + /**< SDP API interface: Set AES key */ + hpm_stat_t (*aes_set_key)(sdp_aes_ctx_t *aes_ctx, const uint8_t *key, sdp_aes_key_bits_t keybits, uint32_t key_idx); + /**< SDP API interface: AES ECB crypto operation */ + hpm_stat_t (*aes_crypt_ecb)(sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t len, const uint8_t *in, uint8_t *out); + /**< SDP API interface: AES CBC crypto operation */ + hpm_stat_t (*aes_crypt_cbc)(sdp_aes_ctx_t *aes_ctx, + sdp_aes_op_t op, + uint32_t length, + uint8_t iv[16], + const uint8_t *input, + uint8_t *output); + /**< SDP API interface: AES CTR crypto operation */ + hpm_stat_t + (*aes_crypt_ctr)(sdp_aes_ctx_t *aes_ctx, uint8_t *nonce_ctr, uint8_t *input, uint8_t *output, uint32_t length); + /**< SDP API interface: AES CCM encryption */ + hpm_stat_t (*aes_ccm_gen_enc)(sdp_aes_ctx_t *aes_ctx, + uint32_t input_len, + const uint8_t *nonce, + uint32_t nonce_len, + const uint8_t *aad, + uint32_t aad_len, + const uint8_t *input, + uint8_t *output, + uint8_t *tag, + uint32_t tag_len); + /**< SDP API interface: AES CCM Decrypt and verify */ + hpm_stat_t (*aes_ccm_dec_verify)(sdp_aes_ctx_t *aes_ctx, + uint32_t input_len, + const uint8_t *nonce, + uint32_t nonce_len, + const uint8_t *aad, + uint32_t aad_len, + const uint8_t *input, + uint8_t *output, + const uint8_t *tag, + uint32_t tag_len); + /**< SDP API interface: memcpy */ + hpm_stat_t (*memcpy)(sdp_dma_ctx_t *dma_ctx, void *dst, const void *src, uint32_t length); + /**< SDP API interface: memset */ + hpm_stat_t (*memset)(sdp_dma_ctx_t *dma_ctx, void *dst, uint8_t pattern, uint32_t length); + /**< SDP API interface: HASH initialization */ + hpm_stat_t (*hash_init)(sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg); + /**< SDP API interface: HASH update */ + hpm_stat_t (*hash_update)(sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length); + /**< SDP API interface: HASH finish */ + hpm_stat_t (*hash_finish)(sdp_hash_ctx_t *hash_ctx, uint8_t *digest); + /**< SDP API interface: Set SM4 Key */ + hpm_stat_t (*sm4_set_key)(sdp_sm4_ctx_t *sm4_ctx, const uint8_t *key, sdp_sm4_key_bits_t keybits, uint32_t key_idx); + /**< SDP API interface: SM4 Crypto ECB mode */ + hpm_stat_t (*sm4_crypt_ecb)(sdp_sm4_ctx_t *sm4_ctx, sdp_sm4_op_t op, uint32_t len, const uint8_t *in, uint8_t *out); + /**< SDP API Interface: SM4 Crypto CBC mode*/ + hpm_stat_t (*sm4_crypt_cbc)(sdp_sm4_ctx_t *sm4_ctx, + sdp_sm4_op_t op, + uint32_t length, + uint8_t iv[16], + const uint8_t *input, + uint8_t *output); + /**< SDP API Interface: SM4 CTR mode */ + hpm_stat_t + (*sm4_crypt_ctr)(sdp_sm4_ctx_t *sm4_ctx, uint8_t *nonce_ctr, uint8_t *input, uint8_t *output, uint32_t length); + /**< SDP API Interface: SM4 CCM Encryption */ + hpm_stat_t (*sm4_ccm_gen_enc)(sdp_sm4_ctx_t *sm4_ctx, + uint32_t input_len, + const uint8_t *nonce, + uint32_t nonce_len, + const uint8_t *aad, + uint32_t aad_len, + const uint8_t *input, + uint8_t *output, + uint8_t *tag, + uint32_t tag_len); + /**< SDP API Interface: SM4 CCM Decrypt and Verify */ + hpm_stat_t (*sm4_ccm_dec_verify)(sdp_sm4_ctx_t *sm4_ctx, + uint32_t input_len, + const uint8_t *nonce, + uint32_t nonce_len, + const uint8_t *aad, + uint32_t aad_len, + const uint8_t *input, + uint8_t *output, + const uint8_t *tag, + uint32_t tag_len); +} sdp_driver_interface_t; + +/** + * @brief Bootloader API table + */ +typedef struct { + /**< Bootloader API table: version */ + const uint32_t version; + /**< Bootloader API table: copyright string address */ + const char *copyright; + /**< Bootloader API table: run_bootloader API */ + hpm_stat_t (*run_bootloader)(void *arg); + /**< Bootloader API table: otp driver interface address */ + const otp_driver_interface_t *otp_driver_if; + /**< Bootloader API table: xpi driver interface address */ + const xpi_driver_interface_t *xpi_driver_if; + /**< Bootloader API table: xpi nor driver interface address */ + const xpi_nor_driver_interface_t *xpi_nor_driver_if; + /**< Bootloader API table: xpi ram driver interface address */ + const uint32_t reserved0; + /**< Bootloader API table: sdp driver interface address */ + const sdp_driver_interface_t *sdp_driver_if; + const uint32_t reserved1[3]; + const exip_driver_interface_t *exip_api_if; + const uint32_t family_id; +} bootloader_api_table_t; + +/**< Bootloader API table Root */ +#define ROM_API_TABLE_ROOT ((const bootloader_api_table_t *)0x2001FF00U) + + +#ifdef __cplusplus +extern "C" { +#endif + +/*********************************************************************************************************************** + * + * + * Enter bootloader Wrapper + * + * + **********************************************************************************************************************/ + +/** + * @brief Eneter specified Boot mode + * @param [in] ctx Enter bootloader context + * @retval status_invalid Invalid parameters were deteced + */ +static inline hpm_stat_t rom_enter_bootloader(void *ctx) +{ + return ROM_API_TABLE_ROOT->run_bootloader(ctx); +} + +/*********************************************************************************************************************** + * + * + * XPI NOR Driver Wrapper + * + * + **********************************************************************************************************************/ + +/** + * @brief Get XPI NOR configuration via cfg_option + * @param [in] base XPI base address + * @param [out] nor_cfg XPI NOR configuration structure + * @param [in] cfg_option XPI NOR configuration option + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_get_config(XPI_Type *base, + xpi_nor_config_t *nor_cfg, + xpi_nor_config_option_t *cfg_option) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_config(base, nor_cfg, cfg_option); +} + +/** + * @brief Initialize XPI NOR based on nor_config + * @param [in] base XPI base address + * @param[in] nor_config XPI NOR configuration + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_init(XPI_Type *base, xpi_nor_config_t *nor_config) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->init(base, nor_config); +} + +/** + * @brief Erase specified FLASH region + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI nOR configuration + * @param[in] start Erase address start address + * @param[in] length Region size to be erased + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start, + uint32_t length) +{ + hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase(base, channel, nor_config, start, length); + fencei(); + return status; +} + +/** + * @brief Erase specified FLASH sector in blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] start Sector address + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_sector(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start) +{ + hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector(base, channel, nor_config, start); + fencei(); + return status; +} + +/** + * @brief Erase specified FLASH sector in non-blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] start Sector address + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_sector_nonblocking(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector_nonblocking(base, channel, nor_config, start); +} + +/** + * @brief Erase specified FLASH blcok in blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] start Block address + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_block(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start) +{ + hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block(base, channel, nor_config, start); + fencei(); + return status; +} + +/** + * @brief Erase specified FLASH blcok in non-blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] start Block address + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_block_nonblocking(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block_nonblocking(base, channel, nor_config, start); +} + +/** + * @brief Erase the whole FLASH in blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_chip(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip(base, channel, nor_config); +} + +/** + * @brief Erase the whole FLASH in non-blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_chip_nonblocking(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config) +{ + hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip_nonblocking(base, channel, nor_config); + fencei(); + return status; +} + +/** + * @brief Program data to specified FLASH address in blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] src data source address + * @param[in] dst_addr Destination FLASH address + * @param[in] length length of data to be programmed + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_program(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + const uint32_t *src, + uint32_t dst_addr, + uint32_t length) +{ + hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->program(base, channel, nor_config, src, dst_addr, length); + fencei(); + return status; +} + +/** + * @brief Page-Program data to specified FLASH address in non-blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] src data source address + * @param[in] dst_addr Destination FLASH address + * @param[in] length length of data to be programmed + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_page_program_nonblocking(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + const uint32_t *src, + uint32_t dst_addr, + uint32_t length) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if + ->page_program_nonblocking(base, channel, nor_config, src, dst_addr, length); +} + +/** + * @brief Read data from specified FLASH address + * @param [in] base XPI base address + * @param [in] channel XPI transfer channel + * @param [in] nor_config XPI NOR configuration + * @param [in] dst Memory start address to store the data read out from FLASH + * @param [in] start FLASH address for data read + * @param [in] length length of data to be read out + * @return API execution address + */ +static inline hpm_stat_t rom_xpi_nor_read(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t *dst, + uint32_t start, + uint32_t length) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->read(base, channel, nor_config, dst, start, length); +} + +/** + * @brief Automatically configure XPI NOR based on cfg_option + * @param [in] base XPI base address + * @param [out] config XPI NOR configuration structure + * @param [in] cfg_option XPI NOR configuration option + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_auto_config(XPI_Type *base, + xpi_nor_config_t *config, + xpi_nor_config_option_t *cfg_option) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->auto_config(base, config, cfg_option); +} + +/** + * @brief Get XPI NOR properties + * @param [in] base XPI base address + * @param [in] nor_cfg XPI NOR configuration structure + * @param [in] property_id + * @param [out] value property value retrieved by this API + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_get_property(XPI_Type *base, + xpi_nor_config_t *nor_cfg, + uint32_t property_id, + uint32_t *value) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_property(base, nor_cfg, property_id, value); +} + +/** + * @brief Return the status register value on XPI NOR FLASH + * + * @param [in] base XPI base address + * @param [in] channel XPI transfer channel + * @param [in] nor_config XPI NOR configuration + * @param [in] addr FLASH address offset + * @param [out] out_status FLASH status register value + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_get_status(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t addr, + uint16_t *out_status) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_status(base, channel, nor_config, addr, out_status); +} + +/** + * @brief Configure the XPI Address Remapping Logic + * @param [in] base XPI base address + * @param [in] start Start Address (memory mapped address) + * @param [in] len Size for the remapping region + * @param [in] offset Relative address based on parameter "start" + * @retval true is all parameters are valid + * @retval false if any parameter is invalid + */ +ATTR_RAMFUNC +static inline bool rom_xpi_nor_remap_config(XPI_Type *base, uint32_t start, uint32_t len, uint32_t offset) +{ + return ROM_API_TABLE_ROOT->exip_api_if->remap_config(base, start, len, offset); +} + +/** + * @brief Disable XPI Remapping logic + * @param [in] base XPI base address + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_remap_disable(XPI_Type *base) +{ + ROM_API_TABLE_ROOT->exip_api_if->remap_disable(base); + fencei(); +} + +/** + * @brief Check whether XPI Remapping is enabled + * @param [in] base XPI base address + * + * @retval true Remapping logic is enabled + * @retval false Remapping logic is disabled + */ +ATTR_RAMFUNC +static inline bool rom_xpi_nor_is_remap_enabled(XPI_Type *base) +{ + return ROM_API_TABLE_ROOT->exip_api_if->remap_enabled(base); +} + +/** + * @brief Configure Specified EXiP Region + * @param [in] base XPI base address + * @param [in] index EXiP Region index + * @param [in] param ExiP Region Parameter + * @retval true All parameters are valid + * @retval false Any parameter is invalid + */ +ATTR_RAMFUNC +static inline bool rom_xpi_nor_exip_region_config(XPI_Type *base, uint32_t index, exip_region_param_t *param) +{ + bool result = ROM_API_TABLE_ROOT->exip_api_if->exip_region_config(base, index, param); + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); + fencei(); + return result; +} + +/** + * @brief Disable EXiP Feature on specified EXiP Region + * @param [in] base XPI base address + * @param [in] index EXiP Region index + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_exip_region_disable(XPI_Type *base, uint32_t index) +{ + ROM_API_TABLE_ROOT->exip_api_if->exip_region_disable(base, index); + fencei(); +} + +/** + * @brief Enable global EXiP logic + * @param [in] base XPI base address + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_exip_enable(XPI_Type *base) +{ + ROM_API_TABLE_ROOT->exip_api_if->enable(base); + fencei(); +} + +/** + * @brief Disable global EXiP logic + * @param [in] base XPI base address + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_exip_disable(XPI_Type *base) +{ + ROM_API_TABLE_ROOT->exip_api_if->disable(base); + fencei(); +} + +/*********************************************************************************************************************** + * + * + * SDP Driver Wrapper + * + * + **********************************************************************************************************************/ +/** + * @brief Initialize SDP IP + */ +static inline void rom_sdp_init(void) +{ + ROM_API_TABLE_ROOT->sdp_driver_if->sdp_ip_init(); +} + +/** + * @brief De-initialize SDP IP + */ +static inline void rom_sdp_deinit(void) +{ + ROM_API_TABLE_ROOT->sdp_driver_if->sdp_ip_deinit(); +} + +/** + * @brief Set AES key to SDP + * @param [in] aes_ctx AES context + * @param [in] key AES key buffer + * @param [in] key_bits AES key-bit option + * @param[in] key_idx AES key index + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_aes_set_key(sdp_aes_ctx_t *aes_ctx, + const uint8_t *key, + sdp_aes_key_bits_t key_bits, + uint32_t key_idx) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->aes_set_key(aes_ctx, key, key_bits, key_idx); +} + +/** + * @brief SDP AES ECB crypto operation(Encrypt or Decrypt) + * @param [in] aes_ctx AES context + * @param [in] op AES operation: encrypt or decrypt + * @param [in] len Data length for AES encryption/decryption + * @param [in] in Input data + * @param [out] out Output data + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_aes_crypt_ecb(sdp_aes_ctx_t *aes_ctx, + sdp_aes_op_t op, + uint32_t len, + const uint8_t *in, + uint8_t *out) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->aes_crypt_ecb(aes_ctx, op, len, in, out); +} + +/** + * @brief SDP AES CBC crypto operation(Encrypt or Decrypt) + * @param [in] aes_ctx AES context + * @param [in] op AES operation: encrypt or decrypt + * @param [in] length Data length for AES encryption/decryption + * @param [in] iv Initial vector/nonce + * @param [in] in Input data + * @param [out] out Output data + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_aes_crypt_cbc(sdp_aes_ctx_t *aes_ctx, + sdp_aes_op_t op, + uint32_t length, + uint8_t iv[16], + const uint8_t *in, + uint8_t *out) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->aes_crypt_cbc(aes_ctx, op, length, iv, in, out); +} + +/** + * @brief Set SM4 key to SDP + * @param [in] sm4_ctx SM4 context + * @param [in] key SM4 key buffer + * @param [in] key_bits SM4 key-bit option + * @param[in] key_idx SM4 key index + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_sm4_set_key(sdp_sm4_ctx_t *sm4_ctx, + const uint8_t *key, + sdp_sm4_key_bits_t key_bits, + uint32_t key_idx) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->sm4_set_key(sm4_ctx, key, key_bits, key_idx); +} + +/** + * @brief SDP SM4 ECB crypto operation(Encrypt or Decrypt) + * @param [in] sm4_ctx SM4 context + * @param [in] op SM4 operation: encrypt or decrypt + * @param [in] len Data length for SM4 encryption/decryption + * @param [in] in Input data + * @param [out] out Output data + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_sm4_crypt_ecb(sdp_sm4_ctx_t *sm4_ctx, + sdp_sm4_op_t op, + uint32_t len, + const uint8_t *in, + uint8_t *out) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->sm4_crypt_ecb(sm4_ctx, op, len, in, out); +} + +/** + * @brief SDP SM4 CBC crypto operation(Encrypt or Decrypt) + * @param [in] sm4_ctx SM4 context + * @param [in] op SM4 operation: encrypt or decrypt + * @param [in] length Data length for SM4 encryption/decryption + * @param [in] iv Initial vector/nonce + * @param [in] in Input data + * @param [out] out Output data + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_sm4_crypt_cbc(sdp_sm4_ctx_t *sm4_ctx, + sdp_sm4_op_t op, + uint32_t length, + uint8_t iv[16], + const uint8_t *in, + uint8_t *out) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->sm4_crypt_cbc(sm4_ctx, op, length, iv, in, out); +} + +/** + * @brief HASH initialization + * @param [in] hash_ctx HASH context + * @param [in] alg HASH algorithm + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_hash_init(sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->hash_init(hash_ctx, alg); +} + +/** + * @brief HASH Update + * @param [in] hash_ctx HASH context + * @param [in] data Data for HASH operation + * @param [in] length of the data for HASH operation + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_hash_update(sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->hash_update(hash_ctx, data, length); +} + +/** + * @brief HASH finialize + * @param [in] hash_ctx HASH context + * @param [out] digest the output digest + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_hash_finish(sdp_hash_ctx_t *hash_ctx, uint8_t *digest) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->hash_finish(hash_ctx, digest); +} + +/** + * @brief SDP memcpy operation + * @param [in] dma_ctx DMA context + * @param [out] dst Destination address for memcpy + * @param [in] src Source address for memcpy + * @param [in] length Size of data for memcpy operation + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_memcpy(sdp_dma_ctx_t *dma_ctx, void *dst, const void *src, uint32_t length) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->memcpy(dma_ctx, dst, src, length); +} + +/** + * @brief SDP memset operation + * @param [in] dma_ctx DMA context + * @param [out] dst Destination address for memset + * @param [in] pattern pattern for memset + * @param [in] length Size of data for memset operation + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_memset(sdp_dma_ctx_t *dma_ctx, void *dst, uint8_t pattern, uint32_t length) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->memset(dma_ctx, dst, pattern, length); +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + + +#endif /* HPM_ROMAPI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_romapi_xpi_soc_def.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_romapi_xpi_soc_def.h new file mode 100644 index 00000000000..ea3ba9e8f9b --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_romapi_xpi_soc_def.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_ROMAPI_XPI_SOC_DEF_H +#define HPM_ROMAPI_XPI_SOC_DEF_H + +#include "hpm_common.h" +#include "hpm_romapi_xpi_def.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +#define XPI_CLK_OUT_FREQ_OPTION_30MHz (1U) +#define XPI_CLK_OUT_FREQ_OPTION_50MHz (2U) +#define XPI_CLK_OUT_FREQ_OPTION_66MHz (3U) +#define XPI_CLK_OUT_FREQ_OPTION_80MHz (4U) +#define XPI_CLK_OUT_FREQ_OPTION_104MHz (5U) +#define XPI_CLK_OUT_FREQ_OPTION_120MHz (6U) +#define XPI_CLK_OUT_FREQ_OPTION_133MHz (7U) +#define XPI_CLK_OUT_FREQ_OPTION_166MHz (8U) +#define XPI_CLK_OUT_FREQ_OPTION_200MHz (9U) + +typedef struct { + struct { + uint8_t priority; /* Offset: 0x00 */ + uint8_t master_idx; /* Offset: 0x01 */ + uint8_t buf_size_in_dword; /* Offset: 0x02 */ + bool enable_prefetch; /* Offset: 0x03 */ + } entry[8]; +} xpi_ahb_buffer_cfg_t; + +typedef struct { + uint8_t data_pads; + xpi_channel_t channel; + xpi_io_group_t io_group; + uint8_t drive_strength; + bool enable_dqs; + bool enable_diff_clk; +} xpi_io_config_t; + +typedef enum { + xpi_freq_type_typical, + xpi_freq_type_mhz, +} clk_freq_type_t; + +typedef enum { + xpi_clk_src_auto, + xpi_clk_src_osc, + xpi_clk_src_pll0clk0, + xpi_clk_src_pll1clk0, + xpi_clk_src_pll1clk1, + xpi_clk_src_pll2clk0, + xpi_clk_src_pll2clk1, + xpi_clk_src_pll3clk0, + xpi_clk_src_pll4clk0, +} xpi_clk_src_t; + + +typedef union { + struct { + uint8_t freq; + bool enable_ddr; + xpi_clk_src_t clk_src; + clk_freq_type_t freq_type; + }; + uint32_t freq_opt; +} xpi_clk_config_t; + +typedef enum { + xpi_clock_bus, + xpi_clock_serial_root, + xpi_clock_serial, +} xpi_clock_t; + +#endif /* HPM_ROMAPI_XPI_SOC_DEF_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_ses_reg.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_ses_reg.xml new file mode 100644 index 00000000000..07a48cbddb1 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_ses_reg.xml @@ -0,0 +1,23685 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_ses_riscv_cpu_regs.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_ses_riscv_cpu_regs.xml new file mode 100644 index 00000000000..da5654d4ec5 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_ses_riscv_cpu_regs.xml @@ -0,0 +1,593 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_soc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_soc.h new file mode 100644 index 00000000000..309c9eda3e2 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_soc.h @@ -0,0 +1,550 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_SOC_H +#define HPM_SOC_H + + +/* List of external IRQs */ +#define IRQn_GPIO0_A 1 /* GPIO0_A IRQ */ +#define IRQn_GPIO0_B 2 /* GPIO0_B IRQ */ +#define IRQn_GPIO0_X 3 /* GPIO0_X IRQ */ +#define IRQn_GPIO0_Y 4 /* GPIO0_Y IRQ */ +#define IRQn_GPTMR0 5 /* GPTMR0 IRQ */ +#define IRQn_GPTMR1 6 /* GPTMR1 IRQ */ +#define IRQn_GPTMR2 7 /* GPTMR2 IRQ */ +#define IRQn_GPTMR3 8 /* GPTMR3 IRQ */ +#define IRQn_UART0 13 /* UART0 IRQ */ +#define IRQn_UART1 14 /* UART1 IRQ */ +#define IRQn_UART2 15 /* UART2 IRQ */ +#define IRQn_UART3 16 /* UART3 IRQ */ +#define IRQn_UART4 17 /* UART4 IRQ */ +#define IRQn_UART5 18 /* UART5 IRQ */ +#define IRQn_UART6 19 /* UART6 IRQ */ +#define IRQn_UART7 20 /* UART7 IRQ */ +#define IRQn_I2C0 21 /* I2C0 IRQ */ +#define IRQn_I2C1 22 /* I2C1 IRQ */ +#define IRQn_I2C2 23 /* I2C2 IRQ */ +#define IRQn_I2C3 24 /* I2C3 IRQ */ +#define IRQn_SPI0 25 /* SPI0 IRQ */ +#define IRQn_SPI1 26 /* SPI1 IRQ */ +#define IRQn_SPI2 27 /* SPI2 IRQ */ +#define IRQn_SPI3 28 /* SPI3 IRQ */ +#define IRQn_TSNS 29 /* TSNS IRQ */ +#define IRQn_MBX0A 30 /* MBX0A IRQ */ +#define IRQn_MBX0B 31 /* MBX0B IRQ */ +#define IRQn_EWDG0 32 /* EWDG0 IRQ */ +#define IRQn_EWDG1 33 /* EWDG1 IRQ */ +#define IRQn_HDMA 34 /* HDMA IRQ */ +#define IRQn_MCAN0 35 /* MCAN0 IRQ */ +#define IRQn_MCAN1 36 /* MCAN1 IRQ */ +#define IRQn_MCAN2 37 /* MCAN2 IRQ */ +#define IRQn_MCAN3 38 /* MCAN3 IRQ */ +#define IRQn_PTPC 39 /* PTPC IRQ */ +#define IRQn_PWM0 40 /* PWM0 IRQ */ +#define IRQn_QEI0 41 /* QEI0 IRQ */ +#define IRQn_SEI0 42 /* SEI0 IRQ */ +#define IRQn_MMC0 43 /* MMC0 IRQ */ +#define IRQn_TRGMUX0 44 /* TRGMUX0 IRQ */ +#define IRQn_PWM1 45 /* PWM1 IRQ */ +#define IRQn_QEI1 46 /* QEI1 IRQ */ +#define IRQn_SEI1 47 /* SEI1 IRQ */ +#define IRQn_MMC1 48 /* MMC1 IRQ */ +#define IRQn_TRGMUX1 49 /* TRGMUX1 IRQ */ +#define IRQn_RDC 50 /* RDC IRQ */ +#define IRQn_USB0 51 /* USB0 IRQ */ +#define IRQn_XPI0 52 /* XPI0 IRQ */ +#define IRQn_SDP 53 /* SDP IRQ */ +#define IRQn_PSEC 54 /* PSEC IRQ */ +#define IRQn_SECMON 55 /* SECMON IRQ */ +#define IRQn_RNG 56 /* RNG IRQ */ +#define IRQn_FUSE 57 /* FUSE IRQ */ +#define IRQn_ADC0 58 /* ADC0 IRQ */ +#define IRQn_ADC1 59 /* ADC1 IRQ */ +#define IRQn_DAC0 60 /* DAC0 IRQ */ +#define IRQn_DAC1 61 /* DAC1 IRQ */ +#define IRQn_ACMP_0 62 /* ACMP_0 IRQ */ +#define IRQn_ACMP_1 63 /* ACMP_1 IRQ */ +#define IRQn_SYSCTL 64 /* SYSCTL IRQ */ +#define IRQn_PGPIO 65 /* PGPIO IRQ */ +#define IRQn_PTMR 66 /* PTMR IRQ */ +#define IRQn_PUART 67 /* PUART IRQ */ +#define IRQn_PEWDG 68 /* PEWDG IRQ */ +#define IRQn_BROWNOUT 69 /* BROWNOUT IRQ */ +#define IRQn_PAD_WAKEUP 70 /* PAD_WAKEUP IRQ */ +#define IRQn_DEBUG0 71 /* DEBUG0 IRQ */ +#define IRQn_DEBUG1 72 /* DEBUG1 IRQ */ + +#include "hpm_common.h" + +#include "hpm_gpio_regs.h" +/* Address of GPIO instances */ +/* FGPIO base address */ +#define HPM_FGPIO_BASE (0xC0000UL) +/* FGPIO base pointer */ +#define HPM_FGPIO ((GPIO_Type *) HPM_FGPIO_BASE) +/* GPIO0 base address */ +#define HPM_GPIO0_BASE (0xF00D0000UL) +/* GPIO0 base pointer */ +#define HPM_GPIO0 ((GPIO_Type *) HPM_GPIO0_BASE) +/* PGPIO base address */ +#define HPM_PGPIO_BASE (0xF411C000UL) +/* PGPIO base pointer */ +#define HPM_PGPIO ((GPIO_Type *) HPM_PGPIO_BASE) + +/* Address of DM instances */ +/* DM base address */ +#define HPM_DM_BASE (0x30000000UL) + +#include "hpm_plic_regs.h" +/* Address of PLIC instances */ +/* PLIC base address */ +#define HPM_PLIC_BASE (0xE4000000UL) +/* PLIC base pointer */ +#define HPM_PLIC ((PLIC_Type *) HPM_PLIC_BASE) + +#include "hpm_mchtmr_regs.h" +/* Address of MCHTMR instances */ +/* MCHTMR base address */ +#define HPM_MCHTMR_BASE (0xE6000000UL) +/* MCHTMR base pointer */ +#define HPM_MCHTMR ((MCHTMR_Type *) HPM_MCHTMR_BASE) + +#include "hpm_plic_sw_regs.h" +/* Address of PLICSW instances */ +/* PLICSW base address */ +#define HPM_PLICSW_BASE (0xE6400000UL) +/* PLICSW base pointer */ +#define HPM_PLICSW ((PLIC_SW_Type *) HPM_PLICSW_BASE) + +#include "hpm_gptmr_regs.h" +/* Address of TMR instances */ +/* GPTMR0 base address */ +#define HPM_GPTMR0_BASE (0xF0000000UL) +/* GPTMR0 base pointer */ +#define HPM_GPTMR0 ((GPTMR_Type *) HPM_GPTMR0_BASE) +/* GPTMR1 base address */ +#define HPM_GPTMR1_BASE (0xF0004000UL) +/* GPTMR1 base pointer */ +#define HPM_GPTMR1 ((GPTMR_Type *) HPM_GPTMR1_BASE) +/* GPTMR2 base address */ +#define HPM_GPTMR2_BASE (0xF0008000UL) +/* GPTMR2 base pointer */ +#define HPM_GPTMR2 ((GPTMR_Type *) HPM_GPTMR2_BASE) +/* GPTMR3 base address */ +#define HPM_GPTMR3_BASE (0xF000C000UL) +/* GPTMR3 base pointer */ +#define HPM_GPTMR3 ((GPTMR_Type *) HPM_GPTMR3_BASE) +/* PTMR base address */ +#define HPM_PTMR_BASE (0xF4120000UL) +/* PTMR base pointer */ +#define HPM_PTMR ((GPTMR_Type *) HPM_PTMR_BASE) + +#include "hpm_uart_regs.h" +/* Address of UART instances */ +/* UART0 base address */ +#define HPM_UART0_BASE (0xF0040000UL) +/* UART0 base pointer */ +#define HPM_UART0 ((UART_Type *) HPM_UART0_BASE) +/* UART1 base address */ +#define HPM_UART1_BASE (0xF0044000UL) +/* UART1 base pointer */ +#define HPM_UART1 ((UART_Type *) HPM_UART1_BASE) +/* UART2 base address */ +#define HPM_UART2_BASE (0xF0048000UL) +/* UART2 base pointer */ +#define HPM_UART2 ((UART_Type *) HPM_UART2_BASE) +/* UART3 base address */ +#define HPM_UART3_BASE (0xF004C000UL) +/* UART3 base pointer */ +#define HPM_UART3 ((UART_Type *) HPM_UART3_BASE) +/* UART4 base address */ +#define HPM_UART4_BASE (0xF0050000UL) +/* UART4 base pointer */ +#define HPM_UART4 ((UART_Type *) HPM_UART4_BASE) +/* UART5 base address */ +#define HPM_UART5_BASE (0xF0054000UL) +/* UART5 base pointer */ +#define HPM_UART5 ((UART_Type *) HPM_UART5_BASE) +/* UART6 base address */ +#define HPM_UART6_BASE (0xF0058000UL) +/* UART6 base pointer */ +#define HPM_UART6 ((UART_Type *) HPM_UART6_BASE) +/* UART7 base address */ +#define HPM_UART7_BASE (0xF005C000UL) +/* UART7 base pointer */ +#define HPM_UART7 ((UART_Type *) HPM_UART7_BASE) +/* PUART base address */ +#define HPM_PUART_BASE (0xF4124000UL) +/* PUART base pointer */ +#define HPM_PUART ((UART_Type *) HPM_PUART_BASE) + +#include "hpm_i2c_regs.h" +/* Address of I2C instances */ +/* I2C0 base address */ +#define HPM_I2C0_BASE (0xF0060000UL) +/* I2C0 base pointer */ +#define HPM_I2C0 ((I2C_Type *) HPM_I2C0_BASE) +/* I2C1 base address */ +#define HPM_I2C1_BASE (0xF0064000UL) +/* I2C1 base pointer */ +#define HPM_I2C1 ((I2C_Type *) HPM_I2C1_BASE) +/* I2C2 base address */ +#define HPM_I2C2_BASE (0xF0068000UL) +/* I2C2 base pointer */ +#define HPM_I2C2 ((I2C_Type *) HPM_I2C2_BASE) +/* I2C3 base address */ +#define HPM_I2C3_BASE (0xF006C000UL) +/* I2C3 base pointer */ +#define HPM_I2C3 ((I2C_Type *) HPM_I2C3_BASE) + +#include "hpm_spi_regs.h" +/* Address of SPI instances */ +/* SPI0 base address */ +#define HPM_SPI0_BASE (0xF0070000UL) +/* SPI0 base pointer */ +#define HPM_SPI0 ((SPI_Type *) HPM_SPI0_BASE) +/* SPI1 base address */ +#define HPM_SPI1_BASE (0xF0074000UL) +/* SPI1 base pointer */ +#define HPM_SPI1 ((SPI_Type *) HPM_SPI1_BASE) +/* SPI2 base address */ +#define HPM_SPI2_BASE (0xF0078000UL) +/* SPI2 base pointer */ +#define HPM_SPI2 ((SPI_Type *) HPM_SPI2_BASE) +/* SPI3 base address */ +#define HPM_SPI3_BASE (0xF007C000UL) +/* SPI3 base pointer */ +#define HPM_SPI3 ((SPI_Type *) HPM_SPI3_BASE) + +#include "hpm_crc_regs.h" +/* Address of CRC instances */ +/* CRC base address */ +#define HPM_CRC_BASE (0xF0080000UL) +/* CRC base pointer */ +#define HPM_CRC ((CRC_Type *) HPM_CRC_BASE) + +#include "hpm_tsns_regs.h" +/* Address of TSNS instances */ +/* TSNS base address */ +#define HPM_TSNS_BASE (0xF0090000UL) +/* TSNS base pointer */ +#define HPM_TSNS ((TSNS_Type *) HPM_TSNS_BASE) + +#include "hpm_mbx_regs.h" +/* Address of MBX instances */ +/* MBX0A base address */ +#define HPM_MBX0A_BASE (0xF00A0000UL) +/* MBX0A base pointer */ +#define HPM_MBX0A ((MBX_Type *) HPM_MBX0A_BASE) +/* MBX0B base address */ +#define HPM_MBX0B_BASE (0xF00A4000UL) +/* MBX0B base pointer */ +#define HPM_MBX0B ((MBX_Type *) HPM_MBX0B_BASE) + +#include "hpm_ewdg_regs.h" +/* Address of EWDG instances */ +/* EWDG0 base address */ +#define HPM_EWDG0_BASE (0xF00B0000UL) +/* EWDG0 base pointer */ +#define HPM_EWDG0 ((EWDG_Type *) HPM_EWDG0_BASE) +/* EWDG1 base address */ +#define HPM_EWDG1_BASE (0xF00B4000UL) +/* EWDG1 base pointer */ +#define HPM_EWDG1 ((EWDG_Type *) HPM_EWDG1_BASE) +/* PEWDG base address */ +#define HPM_PEWDG_BASE (0xF4128000UL) +/* PEWDG base pointer */ +#define HPM_PEWDG ((EWDG_Type *) HPM_PEWDG_BASE) + +#include "hpm_dmamux_regs.h" +/* Address of DMAMUX instances */ +/* DMAMUX base address */ +#define HPM_DMAMUX_BASE (0xF00C4000UL) +/* DMAMUX base pointer */ +#define HPM_DMAMUX ((DMAMUX_Type *) HPM_DMAMUX_BASE) + +#include "hpm_dmav2_regs.h" +/* Address of DMAV2 instances */ +/* HDMA base address */ +#define HPM_HDMA_BASE (0xF00C8000UL) +/* HDMA base pointer */ +#define HPM_HDMA ((DMAV2_Type *) HPM_HDMA_BASE) + +#include "hpm_gpiom_regs.h" +/* Address of GPIOM instances */ +/* GPIOM base address */ +#define HPM_GPIOM_BASE (0xF00D8000UL) +/* GPIOM base pointer */ +#define HPM_GPIOM ((GPIOM_Type *) HPM_GPIOM_BASE) + +#include "hpm_mcan_regs.h" +/* Address of MCAN instances */ +/* MCAN0 base address */ +#define HPM_MCAN0_BASE (0xF0280000UL) +/* MCAN0 base pointer */ +#define HPM_MCAN0 ((MCAN_Type *) HPM_MCAN0_BASE) +/* MCAN1 base address */ +#define HPM_MCAN1_BASE (0xF0284000UL) +/* MCAN1 base pointer */ +#define HPM_MCAN1 ((MCAN_Type *) HPM_MCAN1_BASE) +/* MCAN2 base address */ +#define HPM_MCAN2_BASE (0xF0288000UL) +/* MCAN2 base pointer */ +#define HPM_MCAN2 ((MCAN_Type *) HPM_MCAN2_BASE) +/* MCAN3 base address */ +#define HPM_MCAN3_BASE (0xF028C000UL) +/* MCAN3 base pointer */ +#define HPM_MCAN3 ((MCAN_Type *) HPM_MCAN3_BASE) + +#include "hpm_ptpc_regs.h" +/* Address of PTPC instances */ +/* PTPC base address */ +#define HPM_PTPC_BASE (0xF02FC000UL) +/* PTPC base pointer */ +#define HPM_PTPC ((PTPC_Type *) HPM_PTPC_BASE) + +#include "hpm_qeiv2_regs.h" +/* Address of QEIV2 instances */ +/* QEI0 base address */ +#define HPM_QEI0_BASE (0xF0300000UL) +/* QEI0 base pointer */ +#define HPM_QEI0 ((QEIV2_Type *) HPM_QEI0_BASE) +/* QEI1 base address */ +#define HPM_QEI1_BASE (0xF0304000UL) +/* QEI1 base pointer */ +#define HPM_QEI1 ((QEIV2_Type *) HPM_QEI1_BASE) + +#include "hpm_qeo_regs.h" +/* Address of QEO instances */ +/* QEO0 base address */ +#define HPM_QEO0_BASE (0xF0308000UL) +/* QEO0 base pointer */ +#define HPM_QEO0 ((QEO_Type *) HPM_QEO0_BASE) +/* QEO1 base address */ +#define HPM_QEO1_BASE (0xF030C000UL) +/* QEO1 base pointer */ +#define HPM_QEO1 ((QEO_Type *) HPM_QEO1_BASE) + +#include "hpm_mmc_regs.h" +/* Address of MMC instances */ +/* MMC0 base address */ +#define HPM_MMC0_BASE (0xF0310000UL) +/* MMC0 base pointer */ +#define HPM_MMC0 ((MMC_Type *) HPM_MMC0_BASE) +/* MMC1 base address */ +#define HPM_MMC1_BASE (0xF0314000UL) +/* MMC1 base pointer */ +#define HPM_MMC1 ((MMC_Type *) HPM_MMC1_BASE) + +#include "hpm_pwm_regs.h" +/* Address of PWM instances */ +/* PWM0 base address */ +#define HPM_PWM0_BASE (0xF0318000UL) +/* PWM0 base pointer */ +#define HPM_PWM0 ((PWM_Type *) HPM_PWM0_BASE) +/* PWM1 base address */ +#define HPM_PWM1_BASE (0xF031C000UL) +/* PWM1 base pointer */ +#define HPM_PWM1 ((PWM_Type *) HPM_PWM1_BASE) + +#include "hpm_rdc_regs.h" +/* Address of RDC instances */ +/* RDC base address */ +#define HPM_RDC_BASE (0xF0320000UL) +/* RDC base pointer */ +#define HPM_RDC ((RDC_Type *) HPM_RDC_BASE) + +#include "hpm_plb_regs.h" +/* Address of PLB instances */ +/* PLB base address */ +#define HPM_PLB_BASE (0xF0324000UL) +/* PLB base pointer */ +#define HPM_PLB ((PLB_Type *) HPM_PLB_BASE) + +#include "hpm_synt_regs.h" +/* Address of SYNT instances */ +/* SYNT base address */ +#define HPM_SYNT_BASE (0xF0328000UL) +/* SYNT base pointer */ +#define HPM_SYNT ((SYNT_Type *) HPM_SYNT_BASE) + +#include "hpm_sei_regs.h" +/* Address of SEI instances */ +/* SEI base address */ +#define HPM_SEI_BASE (0xF032C000UL) +/* SEI base pointer */ +#define HPM_SEI ((SEI_Type *) HPM_SEI_BASE) + +#include "hpm_trgm_regs.h" +/* Address of TRGM instances */ +/* TRGM0 base address */ +#define HPM_TRGM0_BASE (0xF033C000UL) +/* TRGM0 base pointer */ +#define HPM_TRGM0 ((TRGM_Type *) HPM_TRGM0_BASE) + +#include "hpm_usb_regs.h" +/* Address of USB instances */ +/* USB0 base address */ +#define HPM_USB0_BASE (0xF300C000UL) +/* USB0 base pointer */ +#define HPM_USB0 ((USB_Type *) HPM_USB0_BASE) + +/* Address of ROMC instances */ +/* ROMC base address */ +#define HPM_ROMC_BASE (0xF3014000UL) + +#include "hpm_sdp_regs.h" +/* Address of SDP instances */ +/* SDP base address */ +#define HPM_SDP_BASE (0xF3040000UL) +/* SDP base pointer */ +#define HPM_SDP ((SDP_Type *) HPM_SDP_BASE) + +#include "hpm_sec_regs.h" +/* Address of SEC instances */ +/* SEC base address */ +#define HPM_SEC_BASE (0xF3044000UL) +/* SEC base pointer */ +#define HPM_SEC ((SEC_Type *) HPM_SEC_BASE) + +#include "hpm_mon_regs.h" +/* Address of MON instances */ +/* MON base address */ +#define HPM_MON_BASE (0xF3048000UL) +/* MON base pointer */ +#define HPM_MON ((MON_Type *) HPM_MON_BASE) + +#include "hpm_rng_regs.h" +/* Address of RNG instances */ +/* RNG base address */ +#define HPM_RNG_BASE (0xF304C000UL) +/* RNG base pointer */ +#define HPM_RNG ((RNG_Type *) HPM_RNG_BASE) + +#include "hpm_otp_regs.h" +/* Address of OTP instances */ +/* OTP base address */ +#define HPM_OTP_BASE (0xF3050000UL) +/* OTP base pointer */ +#define HPM_OTP ((OTP_Type *) HPM_OTP_BASE) + +#include "hpm_keym_regs.h" +/* Address of KEYM instances */ +/* KEYM base address */ +#define HPM_KEYM_BASE (0xF3054000UL) +/* KEYM base pointer */ +#define HPM_KEYM ((KEYM_Type *) HPM_KEYM_BASE) + +#include "hpm_adc16_regs.h" +/* Address of ADC16 instances */ +/* ADC0 base address */ +#define HPM_ADC0_BASE (0xF3080000UL) +/* ADC0 base pointer */ +#define HPM_ADC0 ((ADC16_Type *) HPM_ADC0_BASE) +/* ADC1 base address */ +#define HPM_ADC1_BASE (0xF3084000UL) +/* ADC1 base pointer */ +#define HPM_ADC1 ((ADC16_Type *) HPM_ADC1_BASE) + +#include "hpm_dac_regs.h" +/* Address of DAC instances */ +/* DAC0 base address */ +#define HPM_DAC0_BASE (0xF3090000UL) +/* DAC0 base pointer */ +#define HPM_DAC0 ((DAC_Type *) HPM_DAC0_BASE) +/* DAC1 base address */ +#define HPM_DAC1_BASE (0xF3094000UL) +/* DAC1 base pointer */ +#define HPM_DAC1 ((DAC_Type *) HPM_DAC1_BASE) + +#include "hpm_opamp_regs.h" +/* Address of OPAMP instances */ +/* OPAMP0 base address */ +#define HPM_OPAMP0_BASE (0xF30A0000UL) +/* OPAMP0 base pointer */ +#define HPM_OPAMP0 ((OPAMP_Type *) HPM_OPAMP0_BASE) +/* OPAMP1 base address */ +#define HPM_OPAMP1_BASE (0xF30A4000UL) +/* OPAMP1 base pointer */ +#define HPM_OPAMP1 ((OPAMP_Type *) HPM_OPAMP1_BASE) + +#include "hpm_acmp_regs.h" +/* Address of ACMP instances */ +/* ACMP base address */ +#define HPM_ACMP_BASE (0xF30B0000UL) +/* ACMP base pointer */ +#define HPM_ACMP ((ACMP_Type *) HPM_ACMP_BASE) + +#include "hpm_sysctl_regs.h" +/* Address of SYSCTL instances */ +/* SYSCTL base address */ +#define HPM_SYSCTL_BASE (0xF4000000UL) +/* SYSCTL base pointer */ +#define HPM_SYSCTL ((SYSCTL_Type *) HPM_SYSCTL_BASE) + +#include "hpm_ioc_regs.h" +/* Address of IOC instances */ +/* IOC base address */ +#define HPM_IOC_BASE (0xF4040000UL) +/* IOC base pointer */ +#define HPM_IOC ((IOC_Type *) HPM_IOC_BASE) +/* PIOC base address */ +#define HPM_PIOC_BASE (0xF4118000UL) +/* PIOC base pointer */ +#define HPM_PIOC ((IOC_Type *) HPM_PIOC_BASE) + +#include "hpm_pllctlv2_regs.h" +/* Address of PLLCTLV2 instances */ +/* PLLCTLV2 base address */ +#define HPM_PLLCTLV2_BASE (0xF40C0000UL) +/* PLLCTLV2 base pointer */ +#define HPM_PLLCTLV2 ((PLLCTLV2_Type *) HPM_PLLCTLV2_BASE) + +#include "hpm_ppor_regs.h" +/* Address of PPOR instances */ +/* PPOR base address */ +#define HPM_PPOR_BASE (0xF4100000UL) +/* PPOR base pointer */ +#define HPM_PPOR ((PPOR_Type *) HPM_PPOR_BASE) + +#include "hpm_pcfg_regs.h" +/* Address of PCFG instances */ +/* PCFG base address */ +#define HPM_PCFG_BASE (0xF4104000UL) +/* PCFG base pointer */ +#define HPM_PCFG ((PCFG_Type *) HPM_PCFG_BASE) + +#include "hpm_pgpr_regs.h" +/* Address of PGPR instances */ +/* PGPR0 base address */ +#define HPM_PGPR0_BASE (0xF4110000UL) +/* PGPR0 base pointer */ +#define HPM_PGPR0 ((PGPR_Type *) HPM_PGPR0_BASE) +/* PGPR1 base address */ +#define HPM_PGPR1_BASE (0xF4114000UL) +/* PGPR1 base pointer */ +#define HPM_PGPR1 ((PGPR_Type *) HPM_PGPR1_BASE) + +#include "hpm_pdgo_regs.h" +/* Address of PDGO instances */ +/* PDGO base address */ +#define HPM_PDGO_BASE (0xF4134000UL) +/* PDGO base pointer */ +#define HPM_PDGO ((PDGO_Type *) HPM_PDGO_BASE) + + +#include "riscv/riscv_core.h" +#include "hpm_csr_regs.h" +#include "hpm_interrupt.h" +#include "hpm_misc.h" +#include "hpm_dmamux_src.h" +#include "hpm_trgmmux_src.h" +#include "hpm_iomux.h" +#include "hpm_pmic_iomux.h" +#endif /* HPM_SOC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_soc_feature.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_soc_feature.h new file mode 100644 index 00000000000..4429a376a56 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_soc_feature.h @@ -0,0 +1,207 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_SOC_FEATURE_H +#define HPM_SOC_FEATURE_H + +#include "hpm_soc.h" +#include "hpm_soc_ip_feature.h" + +/* + * PLIC feature + */ +#define PLIC_SUPPORT_EDGE_TRIGGER (1) + +/* + * PMP/PMA Feature + */ +#define PMP_SUPPORT_PMA (0) + +/* + * I2C Section + */ +#define I2C_SOC_FIFO_SIZE (4U) +#define I2C_SOC_TRANSFER_COUNT_MAX (4096U) + +/* + * PMIC Section + */ +#define PCFG_SOC_LDO1P1_MIN_VOLTAGE_IN_MV (700U) +#define PCFG_SOC_LDO1P1_MAX_VOLTAGE_IN_MV (1320U) +#define PCFG_SOC_LDO2P5_MIN_VOLTAGE_IN_MV (2125) +#define PCFG_SOC_LDO2P5_MAX_VOLTAGE_IN_MV (2900U) +#define PCFG_SOC_DCDC_MIN_VOLTAGE_IN_MV (600U) +#define PCFG_SOC_DCDC_MAX_VOLTAGE_IN_MV (1375U) + +/* + * PLLCTL Section + */ +#define PLLCTL_SOC_PLL_MAX_COUNT (2U) +/* PLL reference clock in hz */ +#define PLLCTL_SOC_PLL_REFCLK_FREQ (24U * 1000000UL) +/* only PLL1 and PLL2 have DIV0, DIV1 */ +#define PLLCTL_SOC_PLL_HAS_DIV0(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0) +#define PLLCTL_SOC_PLL_HAS_DIV1(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0) + + +/* + * PWM Section + */ +#define PWM_SOC_PWM_MAX_COUNT (8U) +#define PWM_SOC_CMP_MAX_COUNT (24U) +#define PWM_SOC_OUTPUT_TO_PWM_MAX_COUNT (8U) + +/* + * DMA Section + */ +#define DMA_SOC_TRANSFER_WIDTH_MAX(x) (DMA_TRANSFER_WIDTH_WORD) +#define DMA_SOC_TRANSFER_PER_BURST_MAX(x) (DMA_NUM_TRANSFER_PER_BURST_128T) +#define DMA_SOC_CHANNEL_NUM (32U) +#define DMA_SOC_MAX_COUNT (1U) +#define DMA_SOC_CHN_TO_DMAMUX_CHN(x, n) (DMAMUX_MUXCFG_HDMA_MUX0 + n) +#define DMA_SOC_HAS_IDLE_FLAG (1U) + +/* + * DMAMUX Section + */ +#define DMAMUX_SOC_WRITEONLY (1U) + +/* + * USB Section + */ +#define USB_SOC_MAX_COUNT (1U) + +#define USB_SOC_DCD_QTD_NEXT_INVALID (1U) +#define USB_SOC_DCD_QHD_BUFFER_COUNT (5U) +#define USB_SOC_DCD_MAX_ENDPOINT_COUNT (16U) +#ifndef USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT +#define USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT (8U) +#endif +#define USB_SOC_DCD_MAX_QTD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U * USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT) +#define USB_SOS_DCD_MAX_QHD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U) +#define USB_SOC_DCD_DATA_RAM_ADDRESS_ALIGNMENT (2048U) + +#define USB_SOC_HCD_FRAMELIST_MAX_ELEMENTS (1024U) + +/* + * ADC Section + */ +#define ADC_SOC_IP_VERSION (3U) +#define ADC_SOC_SEQ_MAX_LEN (16U) +#define ADC_SOC_SEQ_HCFG_EN (1U) +#define ADC_SOC_MAX_TRIG_CH_LEN (4U) +#define ADC_SOC_MAX_TRIG_CH_NUM (11U) +#define ADC_SOC_DMA_ADDR_ALIGNMENT (4U) +#define ADC_SOC_CONFIG_INTEN_CHAN_BIT_SIZE (8U) +#define ADC_SOC_BUSMODE_ENABLE_CTRL_SUPPORT (1U) +#define ADC_SOC_PREEMPT_ENABLE_CTRL_SUPPORT (1U) +#define ADC_SOC_SEQ_MAX_DMA_BUFF_LEN_IN_4BYTES (16777216U) +#define ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES (48U) + +#define ADC16_SOC_PARAMS_LEN (34U) +#define ADC16_SOC_MAX_CH_NUM (15U) +#define ADC16_SOC_MAX_SAMPLE_VALUE (65535U) +#define ADC16_SOC_MAX_CONV_CLK_NUM (21U) + +/* + * SYSCTL Section + */ +#define SYSCTL_SOC_CPU_GPR_COUNT (14U) +#define SYSCTL_SOC_MONITOR_SLICE_COUNT (4U) + +/* + * PTPC Section + */ +#define PTPC_SOC_TIMER_MAX_COUNT (2U) + +/* + * SDP Section + */ +#define SDP_REGISTER_DESCRIPTOR_COUNT (1U) +#define SDP_HAS_SM3_SUPPORT (1U) +#define SDP_HAS_SM4_SUPPORT (1U) + +/* + * SOC Privilege mdoe + */ +#define SOC_HAS_S_MODE (0U) + +/* + * DAC Section + */ +#define DAC_SOC_BUFF_ALIGNED_SIZE (32U) +#define DAC_SOC_MAX_DATA (4095U) +#define DAC_SOC_MAX_BUFF_COUNT (65536U) +#define DAC_SOC_MAX_OUTPUT_FREQ (1000000UL) + +/* + * UART Section + */ +#define UART_SOC_FIFO_SIZE (16U) +#define UART_SOC_OVERSAMPLE_MAX (30U) /* only support 30 oversample rate for rx idle detection */ + +/* + * SPI Section + */ +#define SPI_SOC_TRANSFER_COUNT_MAX (0xFFFFFFFFU) +#define SPI_SOC_FIFO_DEPTH (8U) + +/* + * OTP Section + */ +#define OTP_SOC_UUID_IDX (88U) +#define OTP_SOC_UUID_LEN (16U) /* in bytes */ + +/* + * PWM Section + */ +#define PWM_SOC_HRPWM_SUPPORT (0U) +#define PWM_SOC_SHADOW_TRIG_SUPPORT (0U) +#define PWM_SOC_TIMER_RESET_SUPPORT (1U) + +/* + * TRGM section + */ +#define TRGM_SOC_HAS_FILTER_SHIFT (1U) +#define TRGM_SOC_HAS_DMAMUX_EN (1U) +#define TRGM_SOC_HAS_ADC_MATRIX_SEL (1U) +#define TRGM_SOC_HAS_DAC_MATRIX_SEL (1U) +#define TRGM_SOC_HAS_POS_MATRIX_SEL (1U) + +/* + * MCAN Section + */ +#define MCAN_SOC_MAX_COUNT (4U) +#define MCAN_SOC_MSG_BUF_IN_IP (0U) +#define MCAN_SOC_MSG_BUF_IN_AHB_RAM (1U) +#define CAN_SOC_MAX_COUNT MCAN_SOC_MAX_COUNT + +/* + * EWDG Section + */ +#define EWDG_SOC_CLK_DIV_VAL_MAX (5U) +#define EWDG_SOC_OVERTIME_REG_WIDTH (16U) +#define EWDG_SOC_SUPPORT_TIMEOUT_INTERRUPT (1) +#define EWDG_TIMEOUT_INTERRUPT_REQUIRE_EDGE_TRIGGER (1) + +/* + * Sync Timer + */ +#define SYNT_SOC_HAS_TIMESTAMP (1U) + +/* + * GPIO + */ +#define GPIO_SOC_HAS_EDGE_BOTH_INTERRUPT (1U) + +/** + * OPAMP + */ +#define OPAMP_SOC_HAS_MAX_PRESET_CHN_NUM (7U) + + +#endif /* HPM_SOC_FEATURE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_soc_ip_feature.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_soc_ip_feature.h new file mode 100644 index 00000000000..7ed9fc596e1 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_soc_ip_feature.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_SOC_IP_FEATURE_H +#define HPM_SOC_IP_FEATURE_H + +/* UART related feature */ +#define HPM_IP_FEATURE_UART_RX_IDLE_DETECT 1 +#define HPM_IP_FEATURE_UART_FCRR 1 +#define HPM_IP_FEATURE_UART_RX_EN 1 +#define HPM_IP_FEATURE_UART_E00018_FIX 1 +#define HPM_IP_FEATURE_UART_9BIT_MODE 1 +#define HPM_IP_FEATURE_UART_ADDR_MATCH 1 +#define HPM_IP_FEATURE_UART_TRIG_MODE 1 +#define HPM_IP_FEATURE_UART_FINE_FIFO_THRLD 1 +#define HPM_IP_FEATURE_UART_IIR2 1 + +/* I2C related feature */ +#define HPM_IP_FEATURE_I2C_SUPPORT_RESET 1 + +/* SPI related feature */ +#define HPM_IP_FEATURE_SPI_NEW_TRANS_COUNT 1 +#define HPM_IP_FEATURE_SPI_CS_SELECT 1 +#define HPM_IP_FEATURE_SPI_SUPPORT_DIRECTIO 1 + +/* PWM related feature */ +#define HPM_IP_FEATURE_PWM_COUNTER_RESET 1 + +#endif /* HPM_SOC_IP_FEATURE_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_sysctl_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_sysctl_drv.c new file mode 100644 index 00000000000..ba5a53acbf3 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_sysctl_drv.c @@ -0,0 +1,304 @@ +/* + * Copyright (c) 2022-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_sysctl_drv.h" +#include "hpm_soc_feature.h" + +#define SYSCTL_RESOURCE_GROUP0 0 + +#define SYSCTL_CPU_RELEASE_KEY(cpu) (0xC0BEF1A9UL | (((cpu) & 1) << 24)) + +static inline bool sysctl_valid_cpu_index(uint8_t cpu) +{ + if (cpu != SYSCTL_CPU_CPU0) { + return false; + } + return true; +} + +hpm_stat_t sysctl_get_cpu_gpr(SYSCTL_Type *ptr, uint8_t cpu, uint32_t *data, uint32_t size) +{ + uint32_t i; + if ((!sysctl_valid_cpu_index(cpu)) || (size > ARRAY_SIZE(ptr->CPU[cpu].GPR))) { + return status_invalid_argument; + } + for (i = 0; i < size; i++) { + *(data + i) = ptr->CPU[cpu].GPR[i]; + } + return status_success; +} + +static hpm_stat_t _sysctl_cpu_get_gpr(SYSCTL_Type *ptr, uint8_t cpu, uint8_t start, uint8_t count, uint32_t *data) +{ + uint8_t i, size = ARRAY_SIZE(ptr->CPU[cpu].GPR); + if (!sysctl_valid_cpu_index(cpu) || (data == NULL) || !count || start > size || count > size || + (start + count) > size) { + return status_invalid_argument; + } + for (i = 0; i < count; i++) { + *(data + i) = ptr->CPU[cpu].GPR[start + i]; + } + return status_success; +} + +hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data) +{ + return _sysctl_cpu_get_gpr(ptr, 0, start, count, data); +} + +hpm_stat_t sysctl_cpu1_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data) +{ + return _sysctl_cpu_get_gpr(ptr, 1, start, count, data); +} + +static hpm_stat_t _sysctl_cpu_set_gpr(SYSCTL_Type *ptr, uint8_t cpu, uint8_t start, uint8_t count, const uint32_t *data) +{ + uint8_t i, size = ARRAY_SIZE(ptr->CPU[cpu].GPR); + if (!sysctl_valid_cpu_index(cpu) || (data == NULL) || !count || start > size || count > size || + (start + count) > size) { + return status_invalid_argument; + } + for (i = 0; i < count; i++) { + ptr->CPU[cpu].GPR[start + i] = *(data + i); + } + return status_success; +} + +hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock) +{ + hpm_stat_t stat = status_success; + uint16_t gpr_mask; + stat = _sysctl_cpu_set_gpr(ptr, 0, start, count, data); + if (stat != status_success) { + return stat; + } + if (lock) { + gpr_mask = ((1 << count) - 1) << start; + sysctl_cpu0_lock_gpr_with_mask(ptr, gpr_mask); + } + return stat; +} + +void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config) +{ + (void) ptr; + config->mode = monitor_work_mode_record; + config->accuracy = monitor_accuracy_1khz; + config->reference = monitor_reference_24mhz; + config->divide_by = 1; + config->high_limit = 0; + config->low_limit = 0; + config->start_measure = true; + config->enable_output = false; + config->target = monitor_target_clk_top_cpu0; +} + +void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config_t *config) +{ + ptr->MONITOR[monitor_index].CONTROL &= ~(SYSCTL_MONITOR_CONTROL_START_MASK | SYSCTL_MONITOR_CONTROL_OUTEN_MASK); + + if (config->mode == monitor_work_mode_compare) { + ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(config->high_limit); + ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(config->low_limit); + } + + ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL & + ~(SYSCTL_MONITOR_CONTROL_DIV_MASK | SYSCTL_MONITOR_CONTROL_MODE_MASK | SYSCTL_MONITOR_CONTROL_ACCURACY_MASK | + SYSCTL_MONITOR_CONTROL_REFERENCE_MASK | SYSCTL_MONITOR_CONTROL_SELECTION_MASK)) | + (SYSCTL_MONITOR_CONTROL_DIV_SET(config->divide_by - 1) | SYSCTL_MONITOR_CONTROL_MODE_SET(config->mode) | + SYSCTL_MONITOR_CONTROL_ACCURACY_SET(config->accuracy) | + SYSCTL_MONITOR_CONTROL_REFERENCE_SET(config->reference) | + SYSCTL_MONITOR_CONTROL_START_SET(config->start_measure) | + SYSCTL_MONITOR_CONTROL_OUTEN_SET(config->enable_output) | + SYSCTL_MONITOR_CONTROL_SELECTION_SET(config->target)); +} + +uint32_t sysctl_monitor_measure_frequency(SYSCTL_Type *ptr, + uint8_t monitor_index, + monitor_target_t target, + bool enable_output) +{ + uint32_t frequency = 0; + monitor_config_t monitor = { 0 }; + sysctl_monitor_get_default_config(ptr, &monitor); + monitor.target = target; + monitor.enable_output = enable_output; + sysctl_monitor_init(ptr, monitor_index, &monitor); + if (monitor_index < SYSCTL_SOC_MONITOR_SLICE_COUNT) { + frequency = sysctl_monitor_get_current_result(ptr, monitor_index); + } + return frequency; +} + +hpm_stat_t sysctl_set_cpu_entry(SYSCTL_Type *ptr, uint8_t cpu, uint32_t entry) +{ + if (!sysctl_valid_cpu_index(cpu)) { + return status_invalid_argument; + } + ptr->CPU[cpu].GPR[0] = entry; + ptr->CPU[cpu].GPR[1] = SYSCTL_CPU_RELEASE_KEY(cpu); + return status_success; +} + +hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry) +{ + return sysctl_set_cpu_entry(ptr, 0, entry); +} + +hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, + uint8_t group, + sysctl_resource_t resource, + bool enable) +{ + uint32_t index, offset; + if (resource < sysctl_resource_linkable_start) { + return status_invalid_argument; + } + + index = (resource - sysctl_resource_linkable_start) / 32; + offset = (resource - sysctl_resource_linkable_start) % 32; + switch (group) { + case SYSCTL_RESOURCE_GROUP0: + ptr->GROUP0[index].VALUE = (ptr->GROUP0[index].VALUE & ~(1UL << offset)) | (enable ? (1UL << offset) : 0); + if (enable) { + while (sysctl_resource_target_is_busy(ptr, resource)) { + ; + } + } + break; + default: + return status_invalid_argument; + } + + return status_success; +} + +bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, + uint8_t group, + sysctl_resource_t resource) +{ + uint32_t index, offset; + bool enable; + + index = (resource - sysctl_resource_linkable_start) / 32; + offset = (resource - sysctl_resource_linkable_start) % 32; + switch (group) { + case SYSCTL_RESOURCE_GROUP0: + enable = ((ptr->GROUP0[index].VALUE & (1UL << offset)) != 0) ? true : false; + break; + default: + enable = false; + break; + } + + return enable; +} + +uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index) +{ + uint32_t value; + switch (group) { + case SYSCTL_RESOURCE_GROUP0: + value = ptr->GROUP0[index].VALUE; + break; + default: + value = 0; + break; + } + return value; +} + +hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) +{ + return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, true); +} + +hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) +{ + return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, false); +} + +hpm_stat_t sysctl_update_divider(SYSCTL_Type *ptr, clock_node_t node, uint32_t divide_by) +{ + if (node >= clock_node_adc_start) { + return status_invalid_argument; + } + + ptr->CLOCK[node] = (ptr->CLOCK[node] & ~(SYSCTL_CLOCK_DIV_MASK)) | SYSCTL_CLOCK_DIV_SET(divide_by - 1); + while (sysctl_clock_target_is_busy(ptr, node)) { + } + return status_success; +} + +hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node, clock_source_t source, uint32_t divide_by) +{ + if (node >= clock_node_adc_start) { + return status_invalid_argument; + } + + if (source >= clock_source_general_source_end) { + return status_invalid_argument; + } + ptr->CLOCK[node] = (ptr->CLOCK[node] & ~(SYSCTL_CLOCK_MUX_MASK | SYSCTL_CLOCK_DIV_MASK)) | + (SYSCTL_CLOCK_MUX_SET(source) | SYSCTL_CLOCK_DIV_SET(divide_by - 1)); + while (sysctl_clock_target_is_busy(ptr, node)) { + } + return status_success; +} + +hpm_stat_t sysctl_config_cpu0_domain_clock(SYSCTL_Type *ptr, + clock_source_t source, + uint32_t cpu_div, + uint32_t ahb_sub_div) +{ + if (source >= clock_source_general_source_end) { + return status_invalid_argument; + } + + uint32_t origin_cpu_div = SYSCTL_CLOCK_CPU_DIV_GET(ptr->CLOCK_CPU[0]) + 1U; + if (origin_cpu_div == cpu_div) { + ptr->CLOCK_CPU[0] = SYSCTL_CLOCK_CPU_MUX_SET(source) | SYSCTL_CLOCK_CPU_DIV_SET(cpu_div) | SYSCTL_CLOCK_CPU_SUB0_DIV_SET(ahb_sub_div - 1); + while (sysctl_cpu_clock_any_is_busy(ptr)) { + } + } + ptr->CLOCK_CPU[0] = SYSCTL_CLOCK_CPU_MUX_SET(source) | SYSCTL_CLOCK_CPU_DIV_SET(cpu_div - 1) | SYSCTL_CLOCK_CPU_SUB0_DIV_SET(ahb_sub_div - 1); + + while (sysctl_cpu_clock_any_is_busy(ptr)) { + } + + return status_success; +} + +hpm_stat_t sysctl_set_adc_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_adc_t source) +{ + if (source >= clock_source_adc_clk_end) { + return status_invalid_argument; + } + uint32_t adc_index = (uint32_t) (node - clock_node_adc_start); + if (adc_index >= ARRAY_SIZE(ptr->ADCCLK)) { + return status_invalid_argument; + } + + ptr->ADCCLK[adc_index] = (ptr->ADCCLK[adc_index] & ~SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(source); + + return status_success; +} + +hpm_stat_t sysctl_set_dac_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_dac_t source) +{ + if (source >= clock_source_dac_clk_end) { + return status_invalid_argument; + } + uint32_t dac_index = (uint32_t) (node - clock_node_dac_start); + if (dac_index >= ARRAY_SIZE(ptr->DACCLK)) { + return status_invalid_argument; + } + + ptr->DACCLK[dac_index] = (ptr->DACCLK[dac_index] & ~SYSCTL_DACCLK_MUX_MASK) | SYSCTL_DACCLK_MUX_SET(source); + + return status_success; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_sysctl_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_sysctl_drv.h new file mode 100644 index 00000000000..b591746c954 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_sysctl_drv.h @@ -0,0 +1,1254 @@ +/** + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_SYSCTL_DRV_H +#define HPM_SYSCTL_DRV_H + +#include "hpm_common.h" +#include "hpm_sysctl_regs.h" + +/** + * + * @brief SYSCTL driver APIs + * @defgroup sysctl_interface SYSCTL driver APIs + * @ingroup io_interfaces + * @{ + */ + +/** + * @brief Retention domains + */typedef enum { + sysctl_retention_domain_sys = 0, + sysctl_retention_domain_cpu0 = 2, + + sysctl_retention_domain_xtal24m = 4, + sysctl_retention_domain_pll0 = 5, + sysctl_retention_domain_pll1 = 6, +} sysctl_retention_domain_t; + +/** + * @brief Clock presets + */ +typedef enum { + sysctl_preset_0 = 1 << 0, + sysctl_preset_1 = 1 << 1, + sysctl_preset_2 = 1 << 2, + sysctl_preset_3 = 1 << 3, +} sysctl_preset_t; + +/** + * @brief Reset domains + */ +typedef enum { + sysctl_reset_domain_soc = 0, + sysctl_reset_domain_cpu0, +} sysctl_reset_domain_t; + +/** + * @brief Resource + */ +typedef enum { + sysctl_resource_cpu0 = 0, + sysctl_resource_cpx0 = 1, + sysctl_resource_pow_cpu0 = 21, + sysctl_resource_rst_soc = 22, + sysctl_resource_rst_cpu0 = 23, + sysctl_resource_xtal = 32, + sysctl_resource_pll0 = 33, + sysctl_resource_clk0_pll0 = 34, + sysctl_resource_clk1_pll0 = 35, + sysctl_resource_clk2_pll0 = 36, + sysctl_resource_pll1 = 37, + sysctl_resource_clk0_pll1 = 38, + sysctl_resource_clk1_pll1 = 39, + sysctl_resource_clk2_pll1 = 40, + sysctl_resource_clk3_pll1 = 41, + sysctl_resource_pll0_ref = 42, + sysctl_resource_pll1_ref = 43, + sysctl_resource_clk_top_cpu0 = 64, + sysctl_resource_clk_top_mchtmr0 = 65, + sysctl_resource_clk_top_can0 = 66, + sysctl_resource_clk_top_can1 = 67, + sysctl_resource_clk_top_can2 = 68, + sysctl_resource_clk_top_can3 = 69, + sysctl_resource_clk_top_lin0 = 70, + sysctl_resource_clk_top_lin1 = 71, + sysctl_resource_clk_top_lin2 = 72, + sysctl_resource_clk_top_lin3 = 73, + sysctl_resource_clk_top_gptmr0 = 74, + sysctl_resource_clk_top_gptmr1 = 75, + sysctl_resource_clk_top_gptmr2 = 76, + sysctl_resource_clk_top_gptmr3 = 77, + sysctl_resource_clk_top_i2c0 = 78, + sysctl_resource_clk_top_i2c1 = 79, + sysctl_resource_clk_top_i2c2 = 80, + sysctl_resource_clk_top_i2c3 = 81, + sysctl_resource_clk_top_spi0 = 82, + sysctl_resource_clk_top_spi1 = 83, + sysctl_resource_clk_top_spi2 = 84, + sysctl_resource_clk_top_spi3 = 85, + sysctl_resource_clk_top_uart0 = 86, + sysctl_resource_clk_top_uart1 = 87, + sysctl_resource_clk_top_uart2 = 88, + sysctl_resource_clk_top_uart3 = 89, + sysctl_resource_clk_top_uart4 = 90, + sysctl_resource_clk_top_uart5 = 91, + sysctl_resource_clk_top_uart6 = 92, + sysctl_resource_clk_top_uart7 = 93, + sysctl_resource_clk_top_xip0 = 94, + sysctl_resource_clk_top_ana0 = 95, + sysctl_resource_clk_top_ana1 = 96, + sysctl_resource_clk_top_ana2 = 97, + sysctl_resource_clk_top_ana3 = 98, + sysctl_resource_clk_top_ref0 = 99, + sysctl_resource_clk_top_ref1 = 100, + sysctl_resource_clk_top_adc0 = 101, + sysctl_resource_clk_top_adc1 = 102, + sysctl_resource_clk_top_dac0 = 103, + sysctl_resource_clk_top_dac1 = 104, + + sysctl_resource_linkable_start = 256, + sysctl_resource_ahb0 = 256, + sysctl_resource_lmm0 = 257, + sysctl_resource_mchtmr0 = 258, + sysctl_resource_rom0 = 259, + sysctl_resource_can0 = 260, + sysctl_resource_can1 = 261, + sysctl_resource_can2 = 262, + sysctl_resource_can3 = 263, + sysctl_resource_ptpc = 264, + sysctl_resource_lin0 = 265, + sysctl_resource_lin1 = 266, + sysctl_resource_lin2 = 267, + sysctl_resource_lin3 = 268, + sysctl_resource_gptmr0 = 269, + sysctl_resource_gptmr1 = 270, + sysctl_resource_gptmr2 = 271, + sysctl_resource_gptmr3 = 272, + sysctl_resource_i2c0 = 273, + sysctl_resource_i2c1 = 274, + sysctl_resource_i2c2 = 275, + sysctl_resource_i2c3 = 276, + sysctl_resource_spi0 = 277, + sysctl_resource_spi1 = 278, + sysctl_resource_spi2 = 279, + sysctl_resource_spi3 = 280, + sysctl_resource_uart0 = 281, + sysctl_resource_uart1 = 282, + sysctl_resource_uart2 = 283, + sysctl_resource_uart3 = 284, + sysctl_resource_uart4 = 285, + sysctl_resource_uart5 = 286, + sysctl_resource_uart6 = 287, + sysctl_resource_uart7 = 288, + sysctl_resource_wdg0 = 289, + sysctl_resource_wdg1 = 290, + sysctl_resource_mbx0 = 291, + sysctl_resource_tsns = 292, + sysctl_resource_crc0 = 293, + sysctl_resource_adc0 = 294, + sysctl_resource_adc1 = 295, + sysctl_resource_dac0 = 296, + sysctl_resource_dac1 = 297, + sysctl_resource_acmp = 298, + sysctl_resource_opa0 = 299, + sysctl_resource_opa1 = 300, + sysctl_resource_mot0 = 301, + sysctl_resource_rng0 = 302, + sysctl_resource_sdp0 = 303, + sysctl_resource_kman = 304, + sysctl_resource_gpio = 305, + sysctl_resource_hdma = 306, + sysctl_resource_xpi0 = 307, + sysctl_resource_usb0 = 308, + sysctl_resource_ref0 = 309, + sysctl_resource_ref1 = 310, + sysctl_resource_linkable_end, + sysctl_resource_end = sysctl_resource_linkable_end, +} sysctl_resource_t; + +/** + * @brief Resource modes + */ +typedef enum { + sysctl_resource_mode_auto = 0, /*!< Resource clock is automatically managed by system request */ + sysctl_resource_mode_force_on, /*!< Force the resource clock on */ + sysctl_resource_mode_force_off, /*!< Force the resource clock off */ +} sysctl_resource_mode_t; + +/** + * @brief Clock nodes + */ +typedef enum { + clock_node_mchtmr0 = SYSCTL_CLOCK_CLK_TOP_MCT0, + clock_node_can0 = SYSCTL_CLOCK_CLK_TOP_CAN0, + clock_node_can1 = SYSCTL_CLOCK_CLK_TOP_CAN1, + clock_node_can2 = SYSCTL_CLOCK_CLK_TOP_CAN2, + clock_node_can3 = SYSCTL_CLOCK_CLK_TOP_CAN3, + clock_node_gptmr0 = SYSCTL_CLOCK_CLK_TOP_TMR0, + clock_node_gptmr1 = SYSCTL_CLOCK_CLK_TOP_TMR1, + clock_node_gptmr2 = SYSCTL_CLOCK_CLK_TOP_TMR2, + clock_node_gptmr3 = SYSCTL_CLOCK_CLK_TOP_TMR3, + clock_node_i2c0 = SYSCTL_CLOCK_CLK_TOP_I2C0, + clock_node_i2c1 = SYSCTL_CLOCK_CLK_TOP_I2C1, + clock_node_i2c2 = SYSCTL_CLOCK_CLK_TOP_I2C2, + clock_node_i2c3 = SYSCTL_CLOCK_CLK_TOP_I2C3, + clock_node_spi0 = SYSCTL_CLOCK_CLK_TOP_SPI0, + clock_node_spi1 = SYSCTL_CLOCK_CLK_TOP_SPI1, + clock_node_spi2 = SYSCTL_CLOCK_CLK_TOP_SPI2, + clock_node_spi3 = SYSCTL_CLOCK_CLK_TOP_SPI3, + clock_node_uart0 = SYSCTL_CLOCK_CLK_TOP_URT0, + clock_node_uart1 = SYSCTL_CLOCK_CLK_TOP_URT1, + clock_node_uart2 = SYSCTL_CLOCK_CLK_TOP_URT2, + clock_node_uart3 = SYSCTL_CLOCK_CLK_TOP_URT3, + clock_node_uart4 = SYSCTL_CLOCK_CLK_TOP_URT4, + clock_node_uart5 = SYSCTL_CLOCK_CLK_TOP_URT5, + clock_node_uart6 = SYSCTL_CLOCK_CLK_TOP_URT6, + clock_node_uart7 = SYSCTL_CLOCK_CLK_TOP_URT7, + clock_node_xpi0 = SYSCTL_CLOCK_CLK_TOP_XPI0, + clock_node_ana0 = SYSCTL_CLOCK_CLK_TOP_ANA0, + clock_node_ana1 = SYSCTL_CLOCK_CLK_TOP_ANA1, + clock_node_ana2 = SYSCTL_CLOCK_CLK_TOP_ANA2, + clock_node_ana3 = SYSCTL_CLOCK_CLK_TOP_ANA3, + clock_node_ref0 = SYSCTL_CLOCK_CLK_TOP_REF0, + clock_node_ref1 = SYSCTL_CLOCK_CLK_TOP_REF1, + + clock_node_adc_start, + clock_node_adc0 = clock_node_adc_start, + clock_node_adc1, + + clock_node_dac_start, + clock_node_dac0 = clock_node_dac_start, + clock_node_dac1, + clock_node_end, + + clock_node_core_start = 0xfc, + clock_node_cpu0 = clock_node_core_start, + clock_node_axi, + clock_node_ahb, +} clock_node_t; + +/** + * @brief General clock sources + */ +typedef enum { + clock_source_osc0_clk0 = 0, + clock_source_pll0_clk0 = 1, + clock_source_pll0_clk1 = 2, + clock_source_pll0_clk2 = 3, + clock_source_pll1_clk0 = 4, + clock_source_pll1_clk1 = 5, + clock_source_pll1_clk2 = 6, + clock_source_pll1_clk3 = 7, + clock_source_general_source_end, +} clock_source_t; + +/** + * @brief ADC/I2S clock sources + */ +typedef enum { + clock_source_adc_ana_clock = 0, + clock_source_adc_ahb_clock = 1, + clock_source_adc_clk_end, +} clock_source_adc_t; + +/** + * @brief DAC clock sources + */ +typedef enum { + clock_source_dac_ana_clock = 0, + clock_source_dac_ahb_clock = 1, + clock_source_dac_clk_end, +} clock_source_dac_t; + +/** + * @brief CPU low power mode + */ +typedef enum { + cpu_lp_mode_gate_cpu_clock = 0, + cpu_lp_mode_trigger_system_lp = 0x1, + cpu_lp_mode_ungate_cpu_clock = 0x2, +} cpu_lp_mode_t; + +/** + * @brief Monitor targets + */ +typedef enum { + monitor_target_clk_32k = 1, + monitor_target_clk_irc24m = 2, + monitor_target_clk_xtal_24m = 3, + monitor_target_clk_usb0_phy = 4, + monitor_target_clk0_osc0 = 20, + monitor_target_clk0_pll0 = 21, + monitor_target_clk0_pll1 = 22, + monitor_target_clk0_pll2 = 23, + monitor_target_clk1_pll0 = 24, + monitor_target_clk1_pll1 = 25, + monitor_target_clk1_pll2 = 26, + monitor_target_clk1_pll3 = 27, + monitor_target_clk_top_cpu0 = 128, + monitor_target_clk_top_mchtmr0 = 129, + monitor_target_clk_top_can0 = 130, + monitor_target_clk_top_can1 = 131, + monitor_target_clk_top_can2 = 132, + monitor_target_clk_top_can3 = 133, + monitor_target_clk_top_lin0 = 134, + monitor_target_clk_top_lin1 = 135, + monitor_target_clk_top_lin2 = 136, + monitor_target_clk_top_lin3 = 137, + monitor_target_clk_top_gptmr0 = 138, + monitor_target_clk_top_gptmr1 = 139, + monitor_target_clk_top_gptmr2 = 140, + monitor_target_clk_top_gptmr3 = 141, + monitor_target_clk_top_i2c0 = 142, + monitor_target_clk_top_i2c1 = 143, + monitor_target_clk_top_i2c2 = 144, + monitor_target_clk_top_i2c3 = 145, + monitor_target_clk_top_spi0 = 146, + monitor_target_clk_top_spi1 = 147, + monitor_target_clk_top_spi2 = 148, + monitor_target_clk_top_spi3 = 149, + monitor_target_clk_top_uart0 = 150, + monitor_target_clk_top_uart1 = 151, + monitor_target_clk_top_uart2 = 152, + monitor_target_clk_top_uart3 = 153, + monitor_target_clk_top_uart4 = 154, + monitor_target_clk_top_uart5 = 155, + monitor_target_clk_top_uart6 = 156, + monitor_target_clk_top_uart7 = 157, + monitor_target_clk_top_xpi0 = 158, + monitor_target_clk_top_ana0 = 159, + monitor_target_clk_top_ana1 = 160, + monitor_target_clk_top_ana2 = 161, + monitor_target_clk_top_ana3 = 162, + monitor_target_clk_top_ref0 = 163, + monitor_target_clk_top_ref1 = 164, +} monitor_target_t; + +/** + * @brief Monitor work mode + */ +typedef enum { + monitor_work_mode_compare = 0, + monitor_work_mode_record = 1, +} monitor_work_mode_t; + +/** + * @brief Monitor accuracy + */ +typedef enum { + monitor_accuracy_1khz = 0, + monitor_accuracy_1hz = 1, +} monitor_accuracy_t; + +/** + * @brief Monitor reference clock source + */ +typedef enum { + monitor_reference_32khz = 0, + monitor_reference_24mhz = 1, +} monitor_reference_t; + +typedef enum { + cpu_event_flag_mask_reset = SYSCTL_CPU_LP_RESET_FLAG_MASK, + cpu_event_flag_mask_sleep = SYSCTL_CPU_LP_SLEEP_FLAG_MASK, + cpu_event_flag_mask_wake = SYSCTL_CPU_LP_WAKE_FLAG_MASK, + cpu_event_flag_mask_all = SYSCTL_CPU_LP_RESET_FLAG_MASK | SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK, +} cpu_event_flag_mask_t; + +/** + * @brief Monitor config + */ +typedef struct monitor_config { + uint8_t divide_by; /**< Divider to be used for OBS output to pads */ + monitor_work_mode_t mode; /**< Monitor work mode */ + monitor_accuracy_t accuracy; /**< Monitor reference accuracy */ + monitor_reference_t reference; /**< Monitor reference clock source */ + monitor_target_t target; /**< Monitor target */ + bool start_measure; /**< Start flag */ + bool enable_output; /**< Enable output to pads if true */ + uint32_t high_limit; /**< Maximum frequency at compare mode */ + uint32_t low_limit; /**< Minimum frequency at compare mode */ +} monitor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Check if monitor result is valid + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * + * @return true if it is valid + */ +static inline bool sysctl_monitor_result_is_valid(SYSCTL_Type *ptr, uint8_t monitor_index) +{ + return SYSCTL_MONITOR_CONTROL_VALID_GET(ptr->MONITOR[monitor_index].CONTROL); +} + +/** + * @brief Get target monitor instance result + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @return value of monitor result measured + */ +static inline uint32_t sysctl_monitor_get_current_result(SYSCTL_Type *ptr, uint8_t monitor_index) +{ + while (!sysctl_monitor_result_is_valid(ptr, monitor_index)) { + } + return ptr->MONITOR[monitor_index].CURRENT; +} + +/** + * @brief Set work mode for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] mode monitor_work_mode_compare, monitor_work_mode_record + */ +static inline void sysctl_monitor_set_work_mode(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_work_mode_t mode) +{ + ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL & ~SYSCTL_MONITOR_CONTROL_MODE_MASK) | + (SYSCTL_MONITOR_CONTROL_MODE_SET(mode)); +} + +/** + * @brief Set minimum frequency for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] limit measurement low limit + */ +static inline hpm_stat_t sysctl_monitor_set_limit_low(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit) +{ + if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { + return status_invalid_argument; + } + ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit); + return status_success; +} + +/** + * @brief Set maximum frequency for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] limit measurement high limit + */ +static inline hpm_stat_t sysctl_monitor_set_limit_high(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit) +{ + if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { + return status_invalid_argument; + } + ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit); + return status_success; +} + +/** + * @brief Set frequency limit for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] limit_high measurement high limit + * @param[in] limit_low measurement low limit + */ +static inline hpm_stat_t sysctl_monitor_set_limit(SYSCTL_Type *ptr, + uint8_t monitor_index, + uint32_t limit_high, + uint32_t limit_low) +{ + if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { + return status_invalid_argument; + } + ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit_high); + ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit_low); + return status_success; +} + +/** + * @brief Get maximum frequency for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @return current high limit value + */ +static inline uint32_t sysctl_monitor_get_limit_high(SYSCTL_Type *ptr, uint32_t monitor_index) +{ + return SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(ptr->MONITOR[monitor_index].HIGH_LIMIT); +} + +/** + * @brief Get minimum frequency for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @return current low limit value + */ +static inline uint32_t sysctl_monitor_get_limit_low(SYSCTL_Type *ptr, uint32_t monitor_index) +{ + return SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(ptr->MONITOR[monitor_index].LOW_LIMIT); +} + +/** + * @brief Measure specific target frequency + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] target monitor target to be measured + * @param[in] enable_output enable clock obs output + * @return frequency of monitor target measured + */ +uint32_t sysctl_monitor_measure_frequency(SYSCTL_Type *ptr, + uint8_t monitor_index, + monitor_target_t target, + bool enable_output); + +/** + * @brief Link current CPU core its own group + * + * Once it is linked, peripherals state in that group will keep on as long as this core is not in low power mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index to enable its own affiliated group + */ +static inline void sysctl_set_enable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + ptr->AFFILIATE[cpu_index].SET = 1 << cpu_index; +} + +/** + * @brief Unlink current CPU core with its own group + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index to enable its own affiliated group + */ +static inline void sysctl_set_disable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + ptr->AFFILIATE[cpu_index].CLEAR = 1 << cpu_index; +} + +/** + * @brief Check if any resource is busy + * + * @param[in] ptr SYSCTL_Type base address + * @return true if any resource is busy + */ +static inline bool sysctl_resource_any_is_busy(SYSCTL_Type *ptr) +{ + return ptr->RESOURCE[0] & SYSCTL_RESOURCE_GLB_BUSY_MASK; +} + +/** + * @brief Check if specific target is busy + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource target resource index + * @return true if target resource is busy + */ +static inline bool sysctl_resource_target_is_busy(SYSCTL_Type *ptr, sysctl_resource_t resource) +{ + return ptr->RESOURCE[resource] & SYSCTL_RESOURCE_LOC_BUSY_MASK; +} + +/** + * @brief Set target mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource target resource index + * @param[in] mode target resource mode + */ +static inline void sysctl_resource_target_set_mode(SYSCTL_Type *ptr, + sysctl_resource_t resource, + sysctl_resource_mode_t mode) +{ + ptr->RESOURCE[resource] = + (ptr->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | + SYSCTL_RESOURCE_MODE_SET(mode); +} + +/** + * @brief Get target mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource target resource index + * @return target resource mode + */ +static inline uint8_t sysctl_resource_target_get_mode(SYSCTL_Type *ptr, + sysctl_resource_t resource) +{ + return SYSCTL_RESOURCE_MODE_GET(ptr->RESOURCE[resource]); +} + +/** + * @brief Disable resource retention when specific CPU enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index + * @param[in] mask bit mask to clear + */ +static inline void sysctl_clear_cpu_lp_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask) +{ + ptr->RETENTION[cpu_index].CLEAR = mask; +} + +/** + * @brief Disable resource retention when CPU0 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mask bit mask to clear + */ +static inline void sysctl_clear_cpu0_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask) +{ + sysctl_clear_cpu_lp_retention_with_mask(ptr, 0, mask); +} + +/** + * @brief Enable resource retention when specific CPU enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index + * @param[in] mask bit mask to set + */ +static inline void sysctl_set_cpu_lp_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask) +{ + ptr->RETENTION[cpu_index].SET = mask; +} + +/** + * @brief Enable resource retention when CPU0 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mask bit mask to set + */ +static inline void sysctl_set_cpu0_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask) +{ + sysctl_set_cpu_lp_retention_with_mask(ptr, 0, mask); +} + +/** + * @brief Enable resource retention when CPU1 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mask bit mask to set + */ +static inline void sysctl_set_cpu1_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask) +{ + sysctl_set_cpu_lp_retention_with_mask(ptr, 1, mask); +} + +/** + * @brief Enable resource retention when specific CPU enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index + * @param[in] value value to be set + */ +static inline void sysctl_set_cpu_lp_retention(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t value) +{ + ptr->RETENTION[cpu_index].VALUE = value; +} + +/** + * @brief Enable resource retention when CPU0 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] value value to be set + */ +static inline void sysctl_set_cpu0_lp_retention(SYSCTL_Type *ptr, uint32_t value) +{ + sysctl_set_cpu_lp_retention(ptr, 0, value); +} + +/** + * @brief Retain target domain for specific CPU + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] domain target domain power to be retained + * @param[in] retain_mem set true to retain memory/register of target domain + */ +static inline void sysctl_set_cpu_lp_retain_domain(SYSCTL_Type *ptr, + uint8_t cpu_index, + sysctl_retention_domain_t domain, + bool retain_mem) +{ + uint8_t set_mask = 0x1; + if (domain < sysctl_retention_domain_xtal24m) { + set_mask = retain_mem ? 0x3 : 0x1; + } + ptr->RETENTION[cpu_index].SET = (set_mask << domain); +} + +/** + * @brief Retain target domain for specific CPU0 + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain power to be retained + * @param[in] retain_mem set true to retain memory/register of target domain + */ +static inline void sysctl_set_cpu0_lp_retain_domain(SYSCTL_Type *ptr, + sysctl_retention_domain_t domain, + bool retain_mem) +{ + sysctl_set_cpu_lp_retain_domain(ptr, 0, domain, retain_mem); +} + +/** + * @brief Check if cpu clock is busy + * + * @param[in] ptr SYSCTL_Type base address + * @return true if any clock is busy + */ +static inline bool sysctl_cpu_clock_any_is_busy(SYSCTL_Type *ptr) +{ + return ptr->CLOCK_CPU[0] & SYSCTL_CLOCK_CPU_GLB_BUSY_MASK; +} + +/** + * @brief Check if any clock is busy + * + * @param[in] ptr SYSCTL_Type base address + * @return true if any clock is busy + */ +static inline bool sysctl_clock_any_is_busy(SYSCTL_Type *ptr) +{ + return ptr->CLOCK[0] & SYSCTL_CLOCK_GLB_BUSY_MASK; +} + +/** + * @brief Check if target clock is busy + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] clock target clock + * @return true if target clock is busy + */ +static inline bool sysctl_clock_target_is_busy(SYSCTL_Type *ptr, clock_node_t clock) +{ + return ptr->CLOCK[clock] & SYSCTL_CLOCK_LOC_BUSY_MASK; +} + +/** + * @brief Preserve clock setting for certain node + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] clock target clock + */ +static inline void sysctl_clock_preserve_settings(SYSCTL_Type *ptr, clock_node_t clock) +{ + ptr->CLOCK[clock] |= SYSCTL_CLOCK_PRESERVE_MASK; +} + +/** + * @brief Unpreserve clock setting for certain node + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] clock target clock + */ +static inline void sysctl_clock_unpreserve_settings(SYSCTL_Type *ptr, clock_node_t clock) +{ + ptr->CLOCK[clock] &= ~SYSCTL_CLOCK_PRESERVE_MASK; +} + +/** + * @brief Set clock preset + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] preset preset + */ +static inline void sysctl_clock_set_preset(SYSCTL_Type *ptr, sysctl_preset_t preset) +{ + ptr->GLOBAL00 = (ptr->GLOBAL00 & ~SYSCTL_GLOBAL00_MUX_MASK) | SYSCTL_GLOBAL00_MUX_SET(preset); +} + +/** + * @brief Check if target reset domain wakeup status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + * @return true if target domain was taken wakeup reset + */ +static inline bool sysctl_reset_check_target_domain_wakeup_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; +} + +/** + * @brief Clear target reset domain wakeup status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + */ +static inline void sysctl_reset_clear_target_domain_wakeup_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; +} + +/** + * @brief Clear target reset domain reset status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + * @return true if target domain was taken reset + */ +static inline bool sysctl_reset_check_target_domain_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_MASK; +} + +/** + * @brief Clear target reset domain reset status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + */ +static inline void sysctl_reset_clear_target_domain_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK; +} + +/** + * @brief Clear target reset domain for all reset status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + */ +static inline void sysctl_reset_clear_target_domain_all_flags(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK | SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; +} + +/** + * @brief Get target CPU wakeup source status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] status_index wakeup status index 0 - 7 + * @return wakeup source status mask + */ +static inline uint32_t sysctl_get_wakeup_source_status(SYSCTL_Type *ptr, uint8_t cpu_index, uint8_t status_index) +{ + return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index]; +} + +/** + * @brief Get target CPU0 wakeup source status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] status_index wakeup status index 0 - 7 + * @return wakeup source status mask + */ +static inline uint32_t sysctl_get_cpu0_wakeup_source_status(SYSCTL_Type *ptr, uint8_t status_index) +{ + return sysctl_get_wakeup_source_status(ptr, 0, status_index); +} + +/** + * @brief Check wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] status_index wakeup status index 0 - 7 + * @param[in] mask expected status mask + * @return wakeup status according to given bit mask + */ +static inline uint32_t sysctl_check_wakeup_source_status_with_mask(SYSCTL_Type *ptr, + uint8_t cpu_index, + uint8_t status_index, + uint32_t mask) +{ + return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index] & mask; +} + +/** + * @brief Check CPU0 wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] status_index wakeup status index 0 - 7 + * @param[in] mask expected status mask + * @return wakeup status according to given bit mask + */ +static inline uint32_t sysctl_check_cpu0_wakeup_source_status_with_mask(SYSCTL_Type *ptr, + uint8_t status_index, + uint32_t mask) +{ + return sysctl_check_wakeup_source_status_with_mask(ptr, 0, status_index, mask); +} + +/** + * @brief Enable wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void sysctl_enable_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t cpu_index, + uint8_t enable_index, + uint32_t mask) +{ + ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] |= mask; +} + +/** + * @brief Enable CPU0 wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void sysctl_enable_cpu0_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t enable_index, + uint32_t mask) +{ + ptr->CPU[0].WAKEUP_ENABLE[enable_index] |= mask; +} + +/** + * @brief Disable wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void sysctl_disable_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t cpu_index, + uint8_t enable_index, + uint32_t mask) +{ + ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] &= ~mask; +} + +/** + * @brief Disable CPU0 wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void sysctl_disable_cpu0_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t enable_index, + uint32_t mask) +{ + sysctl_disable_wakeup_source_with_mask(ptr, 0, enable_index, mask); +} + +/** + * @brief Disable wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] irq_num irq number to be set as wakeup source + */ +static inline void sysctl_disable_wakeup_source_with_irq(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t irq_num) +{ + ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num >> 2] &= ~(1UL << (irq_num % 32)); +} + +/** + * @brief Disable CPU0 wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] irq_num irq number to be disabled as wakeup source + */ +static inline void sysctl_disable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr, + uint16_t irq_num) +{ + sysctl_disable_wakeup_source_with_irq(ptr, 0, irq_num); +} + + +/** + * @brief Enable wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] irq_num irq number to be set as wakeup source + */ +static inline void sysctl_enable_wakeup_source_with_irq(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t irq_num) +{ + ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num / 32] |= 1UL << (irq_num & 0x1F); +} + +/** + * @brief Enable CPU0 wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] irq_num irq number to be set as wakeup source + */ +static inline void sysctl_enable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr, uint16_t irq_num) +{ + sysctl_enable_wakeup_source_with_irq(ptr, 0, irq_num); +} + +/** + * @brief Lock CPU gpr with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] gpr_mask bit mask of gpr registers to be locked + */ +static inline void sysctl_cpu_lock_gpr_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t gpr_mask) +{ + ptr->CPU[cpu_index].LOCK |= SYSCTL_CPU_LOCK_GPR_SET(gpr_mask); +} + + +/** + * @brief Lock CPU0 gpr with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] gpr_mask bit mask of gpr registers to be locked + */ +static inline void sysctl_cpu0_lock_gpr_with_mask(SYSCTL_Type *ptr, uint16_t gpr_mask) +{ + sysctl_cpu_lock_gpr_with_mask(ptr, 0, gpr_mask); +} + +/** + * @brief Lock CPU lock + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + */ +static inline void sysctl_cpu_lock(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + ptr->CPU[cpu_index].LOCK |= SYSCTL_CPU_LOCK_LOCK_MASK; +} + +/** + * @brief Lock CPU0 lock + * + * @param[in] ptr SYSCTL_Type base address + */ +static inline void sysctl_cpu0_lock(SYSCTL_Type *ptr) +{ + sysctl_cpu_lock(ptr, 0); +} + +/** + * @brief Set CPU low power mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] mode target mode to set + */ +static inline void sysctl_set_cpu_lp_mode(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_lp_mode_t mode) +{ + ptr->CPU[cpu_index].LP = (ptr->CPU[cpu_index].LP & ~(SYSCTL_CPU_LP_MODE_MASK)) | (mode); +} + +/** + * @brief Set CPU0 low power mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mode target mode to set + */ +static inline void sysctl_set_cpu0_lp_mode(SYSCTL_Type *ptr, cpu_lp_mode_t mode) +{ + sysctl_set_cpu_lp_mode(ptr, 0, mode); +} + +/** + * @brief Clear CPU event flags + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] flags flag mask to be cleared + */ +static inline void sysctl_clear_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_event_flag_mask_t flags) +{ + ptr->CPU[cpu_index].LP |= ((SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK) & flags); +} + +/** + * @brief Clear CPU0 event flags + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] flags flag mask to be cleared + */ +static inline void sysctl_clear_cpu0_flags(SYSCTL_Type *ptr, cpu_event_flag_mask_t flags) +{ + sysctl_clear_cpu_flags(ptr, 0, flags); +} + +/** + * @brief Get CPU event flags + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @retval event flag mask + */ +static inline uint32_t sysctl_get_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + return ptr->CPU[cpu_index].LP & (SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK); +} + +/** + * @brief Get CPU0 event flags + * + * @param[in] ptr SYSCTL_Type base address + * @retval event flag mask + */ +static inline uint32_t sysctl_get_cpu0_flags(SYSCTL_Type *ptr) +{ + return sysctl_get_cpu_flags(ptr, 0); +} + +/** + * @brief Config lock + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] node clock node to be configured + * @param[in] source clock source to be used + * @param[in] divide_by clock frequency divider + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node, clock_source_t source, uint32_t divide_by); + +/** + * @brief Configure CPU domain clock + * @param ptr SYSCTL base address + * @param source clock source to be used + * @param cpu_div CPU divider + * @param ahb_sub_div AHB BUS divider based on divided CPU clock + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_config_cpu0_domain_clock(SYSCTL_Type *ptr, clock_source_t source, uint32_t cpu_div, uint32_t ahb_sub_div); + +/** + * @brief Set ADC clock mux + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] node clock node to be configured + * @param[in] source clock source to be used + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_set_adc_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_adc_t source); + + +/** + * @brief Set DAC clock mux + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] node clock node to be configured + * @param[in] source clock source to be used + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_set_dac_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_dac_t source); + + +/** + * @brief Enable group resource + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] group target group to be modified + * @param[in] resource target resource to be added/removed from group + * @param[in] enable set true to add resource, remove otherwise + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t resource, bool enable); + +/** + * @brief Check group resource enable status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] group target group to be checked + * @param[in] resource target resource to be checked from group + * @return enable true if resource enable, false if resource disable + */ +bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t resource); + +/** + * @brief Get group resource value + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] group target group to be getted + * @param[in] index target group index + * @return group index value + */ +uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index); + +/** + * @brief Add resource to CPU0 + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource resource to be added to CPU0 + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource); + +/** + * @brief Remove resource from CPU0 + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource Resource to be removed to CPU0 + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource); + +/** + * @brief Get default monitor config + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] config Monitor config structure pointer + */ +void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config); + +/** + * @brief Initialize Monitor + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index Monitor instance to be initialized + * @param[in] config Monitor config structure pointer + */ +void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config_t *config); + +/** + * @brief Save data to GPU0 GPR starting from given index + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] start Starting GPR index + * @param[in] count Number of GPR registers to set + * @param[in] data Pointer to data buffer + * @param[in] lock Set true to lock written GPR registers after setting + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock); + +/** + * @brief Get data saved from GPU0 GPR starting from given index + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] start Starting GPR index + * @param[in] count Number of GPR registers to set + * @param[out] data Pointer of buffer to save data + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data); + +/** + * @brief Set entry point on CPU0 wakeup + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] entry Entry address for CPU0 on its wakeup + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry); + + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_SYSCTL_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_sysctl_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_sysctl_regs.h new file mode 100644 index 00000000000..45bcc44d311 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_sysctl_regs.h @@ -0,0 +1,1271 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_SYSCTL_H +#define HPM_SYSCTL_H + +typedef struct { + __RW uint32_t RESOURCE[311]; /* 0x0 - 0x4D8: Resource control register for cpu0_core */ + __R uint8_t RESERVED0[804]; /* 0x4DC - 0x7FF: Reserved */ + struct { + __RW uint32_t VALUE; /* 0x800: Group setting */ + __RW uint32_t SET; /* 0x804: Group setting */ + __RW uint32_t CLEAR; /* 0x808: Group setting */ + __RW uint32_t TOGGLE; /* 0x80C: Group setting */ + } GROUP0[2]; + __R uint8_t RESERVED1[224]; /* 0x820 - 0x8FF: Reserved */ + struct { + __RW uint32_t VALUE; /* 0x900: Affiliate of Group */ + __RW uint32_t SET; /* 0x904: Affiliate of Group */ + __RW uint32_t CLEAR; /* 0x908: Affiliate of Group */ + __RW uint32_t TOGGLE; /* 0x90C: Affiliate of Group */ + } AFFILIATE[1]; + __R uint8_t RESERVED2[16]; /* 0x910 - 0x91F: Reserved */ + struct { + __RW uint32_t VALUE; /* 0x920: Retention Control */ + __RW uint32_t SET; /* 0x924: Retention Control */ + __RW uint32_t CLEAR; /* 0x928: Retention Control */ + __RW uint32_t TOGGLE; /* 0x92C: Retention Control */ + } RETENTION[1]; + __R uint8_t RESERVED3[1744]; /* 0x930 - 0xFFF: Reserved */ + struct { + __RW uint32_t STATUS; /* 0x1000: Power Setting */ + __RW uint32_t LF_WAIT; /* 0x1004: Power Setting */ + __R uint8_t RESERVED0[4]; /* 0x1008 - 0x100B: Reserved */ + __RW uint32_t OFF_WAIT; /* 0x100C: Power Setting */ + __RW uint32_t RET_WAIT; /* 0x1010: Power Setting */ + } POWER[1]; + __R uint8_t RESERVED4[1004]; /* 0x1014 - 0x13FF: Reserved */ + struct { + __RW uint32_t CONTROL; /* 0x1400: Reset Setting */ + __RW uint32_t CONFIG; /* 0x1404: Reset Setting */ + __R uint8_t RESERVED0[4]; /* 0x1408 - 0x140B: Reserved */ + __RW uint32_t COUNTER; /* 0x140C: Reset Setting */ + } RESET[2]; + __R uint8_t RESERVED5[992]; /* 0x1420 - 0x17FF: Reserved */ + __RW uint32_t CLOCK_CPU[1]; /* 0x1800: Clock setting */ + __RW uint32_t CLOCK[36]; /* 0x1804 - 0x1890: Clock setting */ + __R uint8_t RESERVED6[876]; /* 0x1894 - 0x1BFF: Reserved */ + __RW uint32_t ADCCLK[2]; /* 0x1C00 - 0x1C04: Clock setting */ + __RW uint32_t DACCLK[2]; /* 0x1C08 - 0x1C0C: Clock setting */ + __R uint8_t RESERVED7[1008]; /* 0x1C10 - 0x1FFF: Reserved */ + __RW uint32_t GLOBAL00; /* 0x2000: Clock senario */ + __R uint8_t RESERVED8[1020]; /* 0x2004 - 0x23FF: Reserved */ + struct { + __RW uint32_t CONTROL; /* 0x2400: Clock measure and monitor control */ + __R uint32_t CURRENT; /* 0x2404: Clock measure result */ + __RW uint32_t LOW_LIMIT; /* 0x2408: Clock lower limit */ + __RW uint32_t HIGH_LIMIT; /* 0x240C: Clock upper limit */ + __R uint8_t RESERVED0[16]; /* 0x2410 - 0x241F: Reserved */ + } MONITOR[4]; + __R uint8_t RESERVED9[896]; /* 0x2480 - 0x27FF: Reserved */ + struct { + __RW uint32_t LP; /* 0x2800: CPU0 LP control */ + __RW uint32_t LOCK; /* 0x2804: CPU0 Lock GPR */ + __RW uint32_t GPR[14]; /* 0x2808 - 0x283C: CPU0 GPR0 */ + __R uint32_t WAKEUP_STATUS[4]; /* 0x2840 - 0x284C: CPU0 wakeup IRQ status */ + __R uint8_t RESERVED0[48]; /* 0x2850 - 0x287F: Reserved */ + __RW uint32_t WAKEUP_ENABLE[4]; /* 0x2880 - 0x288C: CPU0 wakeup IRQ enable */ + __R uint8_t RESERVED1[880]; /* 0x2890 - 0x2BFF: Reserved */ + } CPU[1]; +} SYSCTL_Type; + + +/* Bitfield definition for register array: RESOURCE */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any nodes + * 1: any of nodes is changing status + */ +#define SYSCTL_RESOURCE_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_RESOURCE_GLB_BUSY_SHIFT (31U) +#define SYSCTL_RESOURCE_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_GLB_BUSY_MASK) >> SYSCTL_RESOURCE_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: no change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_RESOURCE_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_RESOURCE_LOC_BUSY_SHIFT (30U) +#define SYSCTL_RESOURCE_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_LOC_BUSY_MASK) >> SYSCTL_RESOURCE_LOC_BUSY_SHIFT) + +/* + * MODE (RW) + * + * resource work mode + * 0:auto turn on and off as system required(recommended) + * 1:always on + * 2:always off + * 3:reserved + */ +#define SYSCTL_RESOURCE_MODE_MASK (0x3U) +#define SYSCTL_RESOURCE_MODE_SHIFT (0U) +#define SYSCTL_RESOURCE_MODE_SET(x) (((uint32_t)(x) << SYSCTL_RESOURCE_MODE_SHIFT) & SYSCTL_RESOURCE_MODE_MASK) +#define SYSCTL_RESOURCE_MODE_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_MODE_MASK) >> SYSCTL_RESOURCE_MODE_SHIFT) + +/* Bitfield definition for register of struct array GROUP0: VALUE */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: peripheral is not needed + * 1: periphera is needed + */ +#define SYSCTL_GROUP0_VALUE_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP0_VALUE_LINK_SHIFT (0U) +#define SYSCTL_GROUP0_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_VALUE_LINK_SHIFT) & SYSCTL_GROUP0_VALUE_LINK_MASK) +#define SYSCTL_GROUP0_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_VALUE_LINK_MASK) >> SYSCTL_GROUP0_VALUE_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP0: SET */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: no effect + * 1: add periphera into this group，periphera is needed + */ +#define SYSCTL_GROUP0_SET_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP0_SET_LINK_SHIFT (0U) +#define SYSCTL_GROUP0_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_SET_LINK_SHIFT) & SYSCTL_GROUP0_SET_LINK_MASK) +#define SYSCTL_GROUP0_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_SET_LINK_MASK) >> SYSCTL_GROUP0_SET_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP0: CLEAR */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: no effect + * 1: delete periphera in this group，periphera is not needed + */ +#define SYSCTL_GROUP0_CLEAR_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP0_CLEAR_LINK_SHIFT (0U) +#define SYSCTL_GROUP0_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_CLEAR_LINK_SHIFT) & SYSCTL_GROUP0_CLEAR_LINK_MASK) +#define SYSCTL_GROUP0_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_CLEAR_LINK_MASK) >> SYSCTL_GROUP0_CLEAR_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP0: TOGGLE */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: no effect + * 1: toggle the result that whether periphera is needed before + */ +#define SYSCTL_GROUP0_TOGGLE_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP0_TOGGLE_LINK_SHIFT (0U) +#define SYSCTL_GROUP0_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) +#define SYSCTL_GROUP0_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) >> SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) + +/* Bitfield definition for register of struct array AFFILIATE: VALUE */ +/* + * LINK (RW) + * + * Affiliate groups of cpu0, each bit represents a group + * bit0: cpu0 depends on group0 + * bit1: cpu0 depends on group1 + * bit2: cpu0 depends on group2 + * bit3: cpu0 depends on group3 + */ +#define SYSCTL_AFFILIATE_VALUE_LINK_MASK (0xFU) +#define SYSCTL_AFFILIATE_VALUE_LINK_SHIFT (0U) +#define SYSCTL_AFFILIATE_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) +#define SYSCTL_AFFILIATE_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) >> SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) + +/* Bitfield definition for register of struct array AFFILIATE: SET */ +/* + * LINK (RW) + * + * Affiliate groups of cpu0，each bit represents a group + * 0: no effect + * 1: the group is assigned to CPU0 + */ +#define SYSCTL_AFFILIATE_SET_LINK_MASK (0xFU) +#define SYSCTL_AFFILIATE_SET_LINK_SHIFT (0U) +#define SYSCTL_AFFILIATE_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_SET_LINK_SHIFT) & SYSCTL_AFFILIATE_SET_LINK_MASK) +#define SYSCTL_AFFILIATE_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_SET_LINK_MASK) >> SYSCTL_AFFILIATE_SET_LINK_SHIFT) + +/* Bitfield definition for register of struct array AFFILIATE: CLEAR */ +/* + * LINK (RW) + * + * Affiliate groups of cpu0, each bit represents a group + * 0: no effect + * 1: the group is not assigned to CPU0 + */ +#define SYSCTL_AFFILIATE_CLEAR_LINK_MASK (0xFU) +#define SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT (0U) +#define SYSCTL_AFFILIATE_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) +#define SYSCTL_AFFILIATE_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) >> SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) + +/* Bitfield definition for register of struct array AFFILIATE: TOGGLE */ +/* + * LINK (RW) + * + * Affiliate groups of cpu0, each bit represents a group + * 0: no effect + * 1: toggle the result that whether the group is assigned to CPU0 before + */ +#define SYSCTL_AFFILIATE_TOGGLE_LINK_MASK (0xFU) +#define SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT (0U) +#define SYSCTL_AFFILIATE_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) +#define SYSCTL_AFFILIATE_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) >> SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) + +/* Bitfield definition for register of struct array RETENTION: VALUE */ +/* + * LINK (RW) + * + * retention setting while CPU0 enter stop mode, each bit represents a resource + * bit00: soc_mem is kept on while cpu0 stop + * bit01: soc_ctx is kept on while cpu0 stop + * bit02: cpu0_mem is kept on while cpu0 stop + * bit03: cpu0_ctx is kept on while cpu0 stop + * bit04: xtal_hold is kept on while cpu0 stop + * bit05: pll0_hold is kept on while cpu0 stop + * bit06: pll1_hold is kept on while cpu0 stop + */ +#define SYSCTL_RETENTION_VALUE_LINK_MASK (0x7FFFU) +#define SYSCTL_RETENTION_VALUE_LINK_SHIFT (0U) +#define SYSCTL_RETENTION_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_VALUE_LINK_SHIFT) & SYSCTL_RETENTION_VALUE_LINK_MASK) +#define SYSCTL_RETENTION_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_VALUE_LINK_MASK) >> SYSCTL_RETENTION_VALUE_LINK_SHIFT) + +/* Bitfield definition for register of struct array RETENTION: SET */ +/* + * LINK (RW) + * + * retention setting while CPU0 enter stop mode, each bit represents a resource + * 0: no effect + * 1: keep + */ +#define SYSCTL_RETENTION_SET_LINK_MASK (0x7FFFU) +#define SYSCTL_RETENTION_SET_LINK_SHIFT (0U) +#define SYSCTL_RETENTION_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_SET_LINK_SHIFT) & SYSCTL_RETENTION_SET_LINK_MASK) +#define SYSCTL_RETENTION_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_SET_LINK_MASK) >> SYSCTL_RETENTION_SET_LINK_SHIFT) + +/* Bitfield definition for register of struct array RETENTION: CLEAR */ +/* + * LINK (RW) + * + * retention setting while CPU0 enter stop mode, each bit represents a resource + * 0: no effect + * 1: no keep + */ +#define SYSCTL_RETENTION_CLEAR_LINK_MASK (0x7FFFU) +#define SYSCTL_RETENTION_CLEAR_LINK_SHIFT (0U) +#define SYSCTL_RETENTION_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_CLEAR_LINK_SHIFT) & SYSCTL_RETENTION_CLEAR_LINK_MASK) +#define SYSCTL_RETENTION_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_CLEAR_LINK_MASK) >> SYSCTL_RETENTION_CLEAR_LINK_SHIFT) + +/* Bitfield definition for register of struct array RETENTION: TOGGLE */ +/* + * LINK (RW) + * + * retention setting while CPU0 enter stop mode, each bit represents a resource + * 0: no effect + * 1: toggle the result that whether the resource is kept on while CPU0 stop before + */ +#define SYSCTL_RETENTION_TOGGLE_LINK_MASK (0x7FFFU) +#define SYSCTL_RETENTION_TOGGLE_LINK_SHIFT (0U) +#define SYSCTL_RETENTION_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) +#define SYSCTL_RETENTION_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) >> SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) + +/* Bitfield definition for register of struct array POWER: STATUS */ +/* + * FLAG (RW) + * + * flag represents power cycle happened from last clear of this bit + * 0: power domain did not edurance power cycle since last clear of this bit + * 1: power domain enduranced power cycle since last clear of this bit + */ +#define SYSCTL_POWER_STATUS_FLAG_MASK (0x80000000UL) +#define SYSCTL_POWER_STATUS_FLAG_SHIFT (31U) +#define SYSCTL_POWER_STATUS_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_SHIFT) & SYSCTL_POWER_STATUS_FLAG_MASK) +#define SYSCTL_POWER_STATUS_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_MASK) >> SYSCTL_POWER_STATUS_FLAG_SHIFT) + +/* + * FLAG_WAKE (RW) + * + * flag represents wakeup power cycle happened from last clear of this bit + * 0: power domain did not edurance wakeup power cycle since last clear of this bit + * 1: power domain enduranced wakeup power cycle since last clear of this bit + */ +#define SYSCTL_POWER_STATUS_FLAG_WAKE_MASK (0x40000000UL) +#define SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT (30U) +#define SYSCTL_POWER_STATUS_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) +#define SYSCTL_POWER_STATUS_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) >> SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) + +/* + * MEM_RET_N (RO) + * + * memory info retention control signal + * 0: memory enter retention mode + * 1: memory exit retention mode + */ +#define SYSCTL_POWER_STATUS_MEM_RET_N_MASK (0x20000UL) +#define SYSCTL_POWER_STATUS_MEM_RET_N_SHIFT (17U) +#define SYSCTL_POWER_STATUS_MEM_RET_N_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_MEM_RET_N_MASK) >> SYSCTL_POWER_STATUS_MEM_RET_N_SHIFT) + +/* + * MEM_RET_P (RO) + * + * memory info retention control signal + * 0: memory not enterexitretention mode + * 1: memory enter retention mode + */ +#define SYSCTL_POWER_STATUS_MEM_RET_P_MASK (0x10000UL) +#define SYSCTL_POWER_STATUS_MEM_RET_P_SHIFT (16U) +#define SYSCTL_POWER_STATUS_MEM_RET_P_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_MEM_RET_P_MASK) >> SYSCTL_POWER_STATUS_MEM_RET_P_SHIFT) + +/* + * LF_DISABLE (RO) + * + * low fanout power switch disable + * 0: low fanout power switches are turned on + * 1: low fanout power switches are truned off + */ +#define SYSCTL_POWER_STATUS_LF_DISABLE_MASK (0x1000U) +#define SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT (12U) +#define SYSCTL_POWER_STATUS_LF_DISABLE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_DISABLE_MASK) >> SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT) + +/* + * LF_ACK (RO) + * + * low fanout power switch feedback + * 0: low fanout power switches are turned on + * 1: low fanout power switches are truned off + */ +#define SYSCTL_POWER_STATUS_LF_ACK_MASK (0x100U) +#define SYSCTL_POWER_STATUS_LF_ACK_SHIFT (8U) +#define SYSCTL_POWER_STATUS_LF_ACK_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_ACK_MASK) >> SYSCTL_POWER_STATUS_LF_ACK_SHIFT) + +/* Bitfield definition for register of struct array POWER: LF_WAIT */ +/* + * WAIT (RW) + * + * wait time for low fan out power switch turn on, default value is 255 + * 0: 0 clock cycle + * 1: 1 clock cycles + * . . . + * clock cycles count on 24MHz + */ +#define SYSCTL_POWER_LF_WAIT_WAIT_MASK (0xFFFFFUL) +#define SYSCTL_POWER_LF_WAIT_WAIT_SHIFT (0U) +#define SYSCTL_POWER_LF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) +#define SYSCTL_POWER_LF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) >> SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) + +/* Bitfield definition for register of struct array POWER: OFF_WAIT */ +/* + * WAIT (RW) + * + * wait time for power switch turn off, default value is 15 + * 0: 0 clock cycle + * 1: 1 clock cycles + * . . . + * clock cycles count on 24MHz + */ +#define SYSCTL_POWER_OFF_WAIT_WAIT_MASK (0xFFFFFUL) +#define SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT (0U) +#define SYSCTL_POWER_OFF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) +#define SYSCTL_POWER_OFF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) >> SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) + +/* Bitfield definition for register of struct array POWER: RET_WAIT */ +/* + * WAIT (RW) + * + * wait time for memory retention mode transition, default value is 15 + * 0: 0 clock cycle + * 1: 1 clock cycles + * . . . + * clock cycles count on 24MHz + */ +#define SYSCTL_POWER_RET_WAIT_WAIT_MASK (0xFFFFFUL) +#define SYSCTL_POWER_RET_WAIT_WAIT_SHIFT (0U) +#define SYSCTL_POWER_RET_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_RET_WAIT_WAIT_SHIFT) & SYSCTL_POWER_RET_WAIT_WAIT_MASK) +#define SYSCTL_POWER_RET_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_RET_WAIT_WAIT_MASK) >> SYSCTL_POWER_RET_WAIT_WAIT_SHIFT) + +/* Bitfield definition for register of struct array RESET: CONTROL */ +/* + * FLAG (RW) + * + * flag represents reset happened from last clear of this bit + * 0: domain did not edurance reset cycle since last clear of this bit + * 1: domain enduranced reset cycle since last clear of this bit + */ +#define SYSCTL_RESET_CONTROL_FLAG_MASK (0x80000000UL) +#define SYSCTL_RESET_CONTROL_FLAG_SHIFT (31U) +#define SYSCTL_RESET_CONTROL_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_MASK) +#define SYSCTL_RESET_CONTROL_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_MASK) >> SYSCTL_RESET_CONTROL_FLAG_SHIFT) + +/* + * FLAG_WAKE (RW) + * + * flag represents wakeup reset happened from last clear of this bit + * 0: domain did not edurance wakeup reset cycle since last clear of this bit + * 1: domain enduranced wakeup reset cycle since last clear of this bit + */ +#define SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK (0x40000000UL) +#define SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT (30U) +#define SYSCTL_RESET_CONTROL_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) +#define SYSCTL_RESET_CONTROL_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) >> SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) + +/* + * HOLD (RW) + * + * perform reset and hold in reset, until ths bit cleared by software + * 0: reset is released for function + * 1: reset is assert and hold + */ +#define SYSCTL_RESET_CONTROL_HOLD_MASK (0x10U) +#define SYSCTL_RESET_CONTROL_HOLD_SHIFT (4U) +#define SYSCTL_RESET_CONTROL_HOLD_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_HOLD_SHIFT) & SYSCTL_RESET_CONTROL_HOLD_MASK) +#define SYSCTL_RESET_CONTROL_HOLD_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_HOLD_MASK) >> SYSCTL_RESET_CONTROL_HOLD_SHIFT) + +/* + * RESET (RW) + * + * perform reset and release imediately + * 0: reset is released + * 1 reset is asserted and will release automatically + */ +#define SYSCTL_RESET_CONTROL_RESET_MASK (0x1U) +#define SYSCTL_RESET_CONTROL_RESET_SHIFT (0U) +#define SYSCTL_RESET_CONTROL_RESET_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_RESET_SHIFT) & SYSCTL_RESET_CONTROL_RESET_MASK) +#define SYSCTL_RESET_CONTROL_RESET_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_RESET_MASK) >> SYSCTL_RESET_CONTROL_RESET_SHIFT) + +/* Bitfield definition for register of struct array RESET: CONFIG */ +/* + * PRE_WAIT (RW) + * + * wait cycle numbers before assert reset + * 0: wait 0 cycle + * 1: wait 1 cycles + * . . . + * Note, clock cycle is base on 24M + */ +#define SYSCTL_RESET_CONFIG_PRE_WAIT_MASK (0xFF0000UL) +#define SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT (16U) +#define SYSCTL_RESET_CONFIG_PRE_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) +#define SYSCTL_RESET_CONFIG_PRE_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) >> SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) + +/* + * RSTCLK_NUM (RW) + * + * reset clock number(must be even number) + * 0: 0 cycle + * 1: 0 cycles + * 2: 2 cycles + * 3: 2 cycles + * . . . + * Note, clock cycle is base on 24M + */ +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK (0xFF00U) +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT (8U) +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) >> SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) + +/* + * POST_WAIT (RW) + * + * time guard band for reset release + * 0: wait 0 cycle + * 1: wait 1 cycles + * . . . + * Note, clock cycle is base on 24M + */ +#define SYSCTL_RESET_CONFIG_POST_WAIT_MASK (0xFFU) +#define SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT (0U) +#define SYSCTL_RESET_CONFIG_POST_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) +#define SYSCTL_RESET_CONFIG_POST_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) >> SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) + +/* Bitfield definition for register of struct array RESET: COUNTER */ +/* + * COUNTER (RW) + * + * self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset + * 0: wait 0 cycle + * 1: wait 1 cycles + * . . . + * Note, clock cycle is base on 24M + */ +#define SYSCTL_RESET_COUNTER_COUNTER_MASK (0xFFFFFUL) +#define SYSCTL_RESET_COUNTER_COUNTER_SHIFT (0U) +#define SYSCTL_RESET_COUNTER_COUNTER_SET(x) (((uint32_t)(x) << SYSCTL_RESET_COUNTER_COUNTER_SHIFT) & SYSCTL_RESET_COUNTER_COUNTER_MASK) +#define SYSCTL_RESET_COUNTER_COUNTER_GET(x) (((uint32_t)(x) & SYSCTL_RESET_COUNTER_COUNTER_MASK) >> SYSCTL_RESET_COUNTER_COUNTER_SHIFT) + +/* Bitfield definition for register array: CLOCK_CPU */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any clock + * 1: any of nodes is changing status + */ +#define SYSCTL_CLOCK_CPU_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_CLOCK_CPU_GLB_BUSY_SHIFT (31U) +#define SYSCTL_CLOCK_CPU_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_GLB_BUSY_MASK) >> SYSCTL_CLOCK_CPU_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: a change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_CLOCK_CPU_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_CLOCK_CPU_LOC_BUSY_SHIFT (30U) +#define SYSCTL_CLOCK_CPU_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_LOC_BUSY_MASK) >> SYSCTL_CLOCK_CPU_LOC_BUSY_SHIFT) + +/* + * PRESERVE (RW) + * + * preserve function against global select + * 0: select global clock setting + * 1: not select global clock setting + */ +#define SYSCTL_CLOCK_CPU_PRESERVE_MASK (0x10000000UL) +#define SYSCTL_CLOCK_CPU_PRESERVE_SHIFT (28U) +#define SYSCTL_CLOCK_CPU_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_PRESERVE_SHIFT) & SYSCTL_CLOCK_CPU_PRESERVE_MASK) +#define SYSCTL_CLOCK_CPU_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_PRESERVE_MASK) >> SYSCTL_CLOCK_CPU_PRESERVE_SHIFT) + +/* + * SUB0_DIV (RW) + * + * ahb bus divider, the bus clock is generated by cpu_clock/div + * 0: divider by 1 + * 1: divider by 2 + * … + */ +#define SYSCTL_CLOCK_CPU_SUB0_DIV_MASK (0xF0000UL) +#define SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT (16U) +#define SYSCTL_CLOCK_CPU_SUB0_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT) & SYSCTL_CLOCK_CPU_SUB0_DIV_MASK) +#define SYSCTL_CLOCK_CPU_SUB0_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_SUB0_DIV_MASK) >> SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT) + +/* + * MUX (RW) + * + * current mux in clock component + * 0:osc0_clk0 + * 1:pll0_clk0 + * 2:pll0_clk1 + * 3:pll0_clk2 + * 4:pll1_clk0 + * 5:pll1_clk1 + * 6:pll1_clk2 + * 7:pll1_clk3 + */ +#define SYSCTL_CLOCK_CPU_MUX_MASK (0x700U) +#define SYSCTL_CLOCK_CPU_MUX_SHIFT (8U) +#define SYSCTL_CLOCK_CPU_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_MUX_SHIFT) & SYSCTL_CLOCK_CPU_MUX_MASK) +#define SYSCTL_CLOCK_CPU_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_MUX_MASK) >> SYSCTL_CLOCK_CPU_MUX_SHIFT) + +/* + * DIV (RW) + * + * clock divider + * 0: divider by 1 + * 1: divider by 2 + * 2: divider by 3 + * . . . + * 255: divider by 256 + */ +#define SYSCTL_CLOCK_CPU_DIV_MASK (0xFFU) +#define SYSCTL_CLOCK_CPU_DIV_SHIFT (0U) +#define SYSCTL_CLOCK_CPU_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_DIV_SHIFT) & SYSCTL_CLOCK_CPU_DIV_MASK) +#define SYSCTL_CLOCK_CPU_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_DIV_MASK) >> SYSCTL_CLOCK_CPU_DIV_SHIFT) + +/* Bitfield definition for register array: CLOCK */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any clock + * 1: any of nodes is changing status + */ +#define SYSCTL_CLOCK_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_CLOCK_GLB_BUSY_SHIFT (31U) +#define SYSCTL_CLOCK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_GLB_BUSY_MASK) >> SYSCTL_CLOCK_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: a change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_CLOCK_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_CLOCK_LOC_BUSY_SHIFT (30U) +#define SYSCTL_CLOCK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_LOC_BUSY_MASK) >> SYSCTL_CLOCK_LOC_BUSY_SHIFT) + +/* + * PRESERVE (RW) + * + * preserve function against global select + * 0: select global clock setting + * 1: not select global clock setting + */ +#define SYSCTL_CLOCK_PRESERVE_MASK (0x10000000UL) +#define SYSCTL_CLOCK_PRESERVE_SHIFT (28U) +#define SYSCTL_CLOCK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_PRESERVE_SHIFT) & SYSCTL_CLOCK_PRESERVE_MASK) +#define SYSCTL_CLOCK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_PRESERVE_MASK) >> SYSCTL_CLOCK_PRESERVE_SHIFT) + +/* + * MUX (RW) + * + * current mux in clock component + * 0:osc0_clk0 + * 1:pll0_clk0 + * 2:pll0_clk1 + * 3:pll0_clk2 + * 4:pll1_clk0 + * 5:pll1_clk1 + * 6:pll1_clk2 + * 7:pll1_clk3 + */ +#define SYSCTL_CLOCK_MUX_MASK (0x700U) +#define SYSCTL_CLOCK_MUX_SHIFT (8U) +#define SYSCTL_CLOCK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_MUX_SHIFT) & SYSCTL_CLOCK_MUX_MASK) +#define SYSCTL_CLOCK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_MUX_MASK) >> SYSCTL_CLOCK_MUX_SHIFT) + +/* + * DIV (RW) + * + * clock divider + * 0: divider by 1 + * 1: divider by 2 + * 2: divider by 3 + * . . . + * 255: divider by 256 + */ +#define SYSCTL_CLOCK_DIV_MASK (0xFFU) +#define SYSCTL_CLOCK_DIV_SHIFT (0U) +#define SYSCTL_CLOCK_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_DIV_SHIFT) & SYSCTL_CLOCK_DIV_MASK) +#define SYSCTL_CLOCK_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_DIV_MASK) >> SYSCTL_CLOCK_DIV_SHIFT) + +/* Bitfield definition for register array: ADCCLK */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any clock + * 1: any of nodes is changing status + */ +#define SYSCTL_ADCCLK_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_ADCCLK_GLB_BUSY_SHIFT (31U) +#define SYSCTL_ADCCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_GLB_BUSY_MASK) >> SYSCTL_ADCCLK_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: a change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_ADCCLK_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_ADCCLK_LOC_BUSY_SHIFT (30U) +#define SYSCTL_ADCCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_LOC_BUSY_MASK) >> SYSCTL_ADCCLK_LOC_BUSY_SHIFT) + +/* + * PRESERVE (RW) + * + * preserve function against global select + * 0: select global clock setting + * 1: not select global clock setting + */ +#define SYSCTL_ADCCLK_PRESERVE_MASK (0x10000000UL) +#define SYSCTL_ADCCLK_PRESERVE_SHIFT (28U) +#define SYSCTL_ADCCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_PRESERVE_SHIFT) & SYSCTL_ADCCLK_PRESERVE_MASK) +#define SYSCTL_ADCCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_PRESERVE_MASK) >> SYSCTL_ADCCLK_PRESERVE_SHIFT) + +/* + * MUX (RW) + * + * current mux + * 0: ahb0 clock N + * 1: ana clock + */ +#define SYSCTL_ADCCLK_MUX_MASK (0x100U) +#define SYSCTL_ADCCLK_MUX_SHIFT (8U) +#define SYSCTL_ADCCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_MUX_SHIFT) & SYSCTL_ADCCLK_MUX_MASK) +#define SYSCTL_ADCCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_MUX_MASK) >> SYSCTL_ADCCLK_MUX_SHIFT) + +/* Bitfield definition for register array: DACCLK */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any clock + * 1: any of nodes is changing status + */ +#define SYSCTL_DACCLK_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_DACCLK_GLB_BUSY_SHIFT (31U) +#define SYSCTL_DACCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_GLB_BUSY_MASK) >> SYSCTL_DACCLK_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: a change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_DACCLK_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_DACCLK_LOC_BUSY_SHIFT (30U) +#define SYSCTL_DACCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_LOC_BUSY_MASK) >> SYSCTL_DACCLK_LOC_BUSY_SHIFT) + +/* + * PRESERVE (RW) + * + * preserve function against global select + * 0: select global clock setting + * 1: not select global clock setting + */ +#define SYSCTL_DACCLK_PRESERVE_MASK (0x10000000UL) +#define SYSCTL_DACCLK_PRESERVE_SHIFT (28U) +#define SYSCTL_DACCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_DACCLK_PRESERVE_SHIFT) & SYSCTL_DACCLK_PRESERVE_MASK) +#define SYSCTL_DACCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_PRESERVE_MASK) >> SYSCTL_DACCLK_PRESERVE_SHIFT) + +/* + * MUX (RW) + * + * current mux + * 0: ahb0 clock N + * 1: ana clock + */ +#define SYSCTL_DACCLK_MUX_MASK (0x100U) +#define SYSCTL_DACCLK_MUX_SHIFT (8U) +#define SYSCTL_DACCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_DACCLK_MUX_SHIFT) & SYSCTL_DACCLK_MUX_MASK) +#define SYSCTL_DACCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_MUX_MASK) >> SYSCTL_DACCLK_MUX_SHIFT) + +/* Bitfield definition for register: GLOBAL00 */ +/* + * MUX (RW) + * + * global clock override request + * bit0: override to preset0 + * bit1: override to preset1 + * bit2: override to preset2 + * bit3: override to preset3 + * bit4: override to preset4 + * bit5: override to preset5 + * bit6: override to preset6 + * bit7: override to preset7 + */ +#define SYSCTL_GLOBAL00_MUX_MASK (0xFFU) +#define SYSCTL_GLOBAL00_MUX_SHIFT (0U) +#define SYSCTL_GLOBAL00_MUX_SET(x) (((uint32_t)(x) << SYSCTL_GLOBAL00_MUX_SHIFT) & SYSCTL_GLOBAL00_MUX_MASK) +#define SYSCTL_GLOBAL00_MUX_GET(x) (((uint32_t)(x) & SYSCTL_GLOBAL00_MUX_MASK) >> SYSCTL_GLOBAL00_MUX_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: CONTROL */ +/* + * VALID (RW) + * + * result is ready for read + * 0: not ready + * 1: result is ready + */ +#define SYSCTL_MONITOR_CONTROL_VALID_MASK (0x80000000UL) +#define SYSCTL_MONITOR_CONTROL_VALID_SHIFT (31U) +#define SYSCTL_MONITOR_CONTROL_VALID_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_VALID_SHIFT) & SYSCTL_MONITOR_CONTROL_VALID_MASK) +#define SYSCTL_MONITOR_CONTROL_VALID_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_VALID_MASK) >> SYSCTL_MONITOR_CONTROL_VALID_SHIFT) + +/* + * DIV_BUSY (RO) + * + * divider is applying new setting + */ +#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK (0x8000000UL) +#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT (27U) +#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT) + +/* + * OUTEN (RW) + * + * enable clock output + */ +#define SYSCTL_MONITOR_CONTROL_OUTEN_MASK (0x1000000UL) +#define SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT (24U) +#define SYSCTL_MONITOR_CONTROL_OUTEN_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) +#define SYSCTL_MONITOR_CONTROL_OUTEN_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) >> SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) + +/* + * DIV (RW) + * + * output divider + */ +#define SYSCTL_MONITOR_CONTROL_DIV_MASK (0xFF0000UL) +#define SYSCTL_MONITOR_CONTROL_DIV_SHIFT (16U) +#define SYSCTL_MONITOR_CONTROL_DIV_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_DIV_SHIFT) & SYSCTL_MONITOR_CONTROL_DIV_MASK) +#define SYSCTL_MONITOR_CONTROL_DIV_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_SHIFT) + +/* + * HIGH (RW) + * + * clock frequency higher than upper limit + */ +#define SYSCTL_MONITOR_CONTROL_HIGH_MASK (0x8000U) +#define SYSCTL_MONITOR_CONTROL_HIGH_SHIFT (15U) +#define SYSCTL_MONITOR_CONTROL_HIGH_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) +#define SYSCTL_MONITOR_CONTROL_HIGH_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) >> SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) + +/* + * LOW (RW) + * + * clock frequency lower than lower limit + */ +#define SYSCTL_MONITOR_CONTROL_LOW_MASK (0x4000U) +#define SYSCTL_MONITOR_CONTROL_LOW_SHIFT (14U) +#define SYSCTL_MONITOR_CONTROL_LOW_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_LOW_SHIFT) & SYSCTL_MONITOR_CONTROL_LOW_MASK) +#define SYSCTL_MONITOR_CONTROL_LOW_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_LOW_MASK) >> SYSCTL_MONITOR_CONTROL_LOW_SHIFT) + +/* + * START (RW) + * + * start measurement + */ +#define SYSCTL_MONITOR_CONTROL_START_MASK (0x1000U) +#define SYSCTL_MONITOR_CONTROL_START_SHIFT (12U) +#define SYSCTL_MONITOR_CONTROL_START_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_START_SHIFT) & SYSCTL_MONITOR_CONTROL_START_MASK) +#define SYSCTL_MONITOR_CONTROL_START_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_START_MASK) >> SYSCTL_MONITOR_CONTROL_START_SHIFT) + +/* + * MODE (RW) + * + * work mode, + * 0: register value will be compared to measurement + * 1: upper and lower value will be recordered in register + */ +#define SYSCTL_MONITOR_CONTROL_MODE_MASK (0x400U) +#define SYSCTL_MONITOR_CONTROL_MODE_SHIFT (10U) +#define SYSCTL_MONITOR_CONTROL_MODE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_MODE_SHIFT) & SYSCTL_MONITOR_CONTROL_MODE_MASK) +#define SYSCTL_MONITOR_CONTROL_MODE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_MODE_MASK) >> SYSCTL_MONITOR_CONTROL_MODE_SHIFT) + +/* + * ACCURACY (RW) + * + * measurement accuracy, + * 0: resolution is 1kHz + * 1: resolution is 1Hz + */ +#define SYSCTL_MONITOR_CONTROL_ACCURACY_MASK (0x200U) +#define SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT (9U) +#define SYSCTL_MONITOR_CONTROL_ACCURACY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) +#define SYSCTL_MONITOR_CONTROL_ACCURACY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) >> SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) + +/* + * REFERENCE (RW) + * + * reference clock selection, + * 0: 32k + * 1: 24M + */ +#define SYSCTL_MONITOR_CONTROL_REFERENCE_MASK (0x100U) +#define SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT (8U) +#define SYSCTL_MONITOR_CONTROL_REFERENCE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) +#define SYSCTL_MONITOR_CONTROL_REFERENCE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) >> SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) + +/* + * SELECTION (RW) + * + * clock measurement selection + */ +#define SYSCTL_MONITOR_CONTROL_SELECTION_MASK (0xFFU) +#define SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT (0U) +#define SYSCTL_MONITOR_CONTROL_SELECTION_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) +#define SYSCTL_MONITOR_CONTROL_SELECTION_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) >> SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: CURRENT */ +/* + * FREQUENCY (RO) + * + * self updating measure result + */ +#define SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK (0xFFFFFFFFUL) +#define SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT (0U) +#define SYSCTL_MONITOR_CURRENT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK) >> SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: LOW_LIMIT */ +/* + * FREQUENCY (RW) + * + * lower frequency + */ +#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL) +#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT (0U) +#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) +#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: HIGH_LIMIT */ +/* + * FREQUENCY (RW) + * + * upper frequency + */ +#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL) +#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT (0U) +#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) +#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) + +/* Bitfield definition for register of struct array CPU: LP */ +/* + * WAKE_CNT (RW) + * + * CPU0 wake up counter, counter satuated at 255, write 0x00 to clear + */ +#define SYSCTL_CPU_LP_WAKE_CNT_MASK (0xFF000000UL) +#define SYSCTL_CPU_LP_WAKE_CNT_SHIFT (24U) +#define SYSCTL_CPU_LP_WAKE_CNT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_CNT_SHIFT) & SYSCTL_CPU_LP_WAKE_CNT_MASK) +#define SYSCTL_CPU_LP_WAKE_CNT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_CNT_MASK) >> SYSCTL_CPU_LP_WAKE_CNT_SHIFT) + +/* + * HALT (RW) + * + * halt request for CPU0, + * 0: CPU0 will start to execute after reset or receive wakeup request + * 1: CPU0 will not start after reset, or wakeup after WFI + */ +#define SYSCTL_CPU_LP_HALT_MASK (0x10000UL) +#define SYSCTL_CPU_LP_HALT_SHIFT (16U) +#define SYSCTL_CPU_LP_HALT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_HALT_SHIFT) & SYSCTL_CPU_LP_HALT_MASK) +#define SYSCTL_CPU_LP_HALT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_HALT_MASK) >> SYSCTL_CPU_LP_HALT_SHIFT) + +/* + * WAKE (RO) + * + * CPU0 is waking up + * 0: CPU0 wake up not asserted + * 1: CPU0 wake up asserted + */ +#define SYSCTL_CPU_LP_WAKE_MASK (0x2000U) +#define SYSCTL_CPU_LP_WAKE_SHIFT (13U) +#define SYSCTL_CPU_LP_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_MASK) >> SYSCTL_CPU_LP_WAKE_SHIFT) + +/* + * EXEC (RO) + * + * CPU0 is executing + * 0: CPU0 is not executing + * 1: CPU0 is executing + */ +#define SYSCTL_CPU_LP_EXEC_MASK (0x1000U) +#define SYSCTL_CPU_LP_EXEC_SHIFT (12U) +#define SYSCTL_CPU_LP_EXEC_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_EXEC_MASK) >> SYSCTL_CPU_LP_EXEC_SHIFT) + +/* + * WAKE_FLAG (RW) + * + * CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit + * 0: CPU0 wakeup not happened + * 1: CPU0 wake up happened + */ +#define SYSCTL_CPU_LP_WAKE_FLAG_MASK (0x400U) +#define SYSCTL_CPU_LP_WAKE_FLAG_SHIFT (10U) +#define SYSCTL_CPU_LP_WAKE_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) +#define SYSCTL_CPU_LP_WAKE_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) >> SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) + +/* + * SLEEP_FLAG (RW) + * + * CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit + * 0: CPU0 sleep not happened + * 1: CPU0 sleep happened + */ +#define SYSCTL_CPU_LP_SLEEP_FLAG_MASK (0x200U) +#define SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT (9U) +#define SYSCTL_CPU_LP_SLEEP_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) +#define SYSCTL_CPU_LP_SLEEP_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) >> SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) + +/* + * RESET_FLAG (RW) + * + * CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit + * 0: CPU0 reset not happened + * 1: CPU0 reset happened + */ +#define SYSCTL_CPU_LP_RESET_FLAG_MASK (0x100U) +#define SYSCTL_CPU_LP_RESET_FLAG_SHIFT (8U) +#define SYSCTL_CPU_LP_RESET_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_RESET_FLAG_SHIFT) & SYSCTL_CPU_LP_RESET_FLAG_MASK) +#define SYSCTL_CPU_LP_RESET_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_RESET_FLAG_MASK) >> SYSCTL_CPU_LP_RESET_FLAG_SHIFT) + +/* + * MODE (RW) + * + * Low power mode, system behavior after WFI + * 00: CPU clock stop after WFI + * 01: System enter low power mode after WFI + * 10: Keep running after WFI + * 11: reserved + */ +#define SYSCTL_CPU_LP_MODE_MASK (0x3U) +#define SYSCTL_CPU_LP_MODE_SHIFT (0U) +#define SYSCTL_CPU_LP_MODE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_MODE_SHIFT) & SYSCTL_CPU_LP_MODE_MASK) +#define SYSCTL_CPU_LP_MODE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_MODE_MASK) >> SYSCTL_CPU_LP_MODE_SHIFT) + +/* Bitfield definition for register of struct array CPU: LOCK */ +/* + * GPR (RW) + * + * Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset + */ +#define SYSCTL_CPU_LOCK_GPR_MASK (0xFFFCU) +#define SYSCTL_CPU_LOCK_GPR_SHIFT (2U) +#define SYSCTL_CPU_LOCK_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_GPR_SHIFT) & SYSCTL_CPU_LOCK_GPR_MASK) +#define SYSCTL_CPU_LOCK_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_GPR_MASK) >> SYSCTL_CPU_LOCK_GPR_SHIFT) + +/* + * LOCK (RW) + * + * Lock bit for CPU_LOCK + */ +#define SYSCTL_CPU_LOCK_LOCK_MASK (0x2U) +#define SYSCTL_CPU_LOCK_LOCK_SHIFT (1U) +#define SYSCTL_CPU_LOCK_LOCK_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_LOCK_SHIFT) & SYSCTL_CPU_LOCK_LOCK_MASK) +#define SYSCTL_CPU_LOCK_LOCK_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_LOCK_MASK) >> SYSCTL_CPU_LOCK_LOCK_SHIFT) + +/* Bitfield definition for register of struct array CPU: GPR0 */ +/* + * GPR (RW) + * + * register for software to handle resume, can save resume address or status + */ +#define SYSCTL_CPU_GPR_GPR_MASK (0xFFFFFFFFUL) +#define SYSCTL_CPU_GPR_GPR_SHIFT (0U) +#define SYSCTL_CPU_GPR_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_GPR_GPR_SHIFT) & SYSCTL_CPU_GPR_GPR_MASK) +#define SYSCTL_CPU_GPR_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_GPR_GPR_MASK) >> SYSCTL_CPU_GPR_GPR_SHIFT) + +/* Bitfield definition for register of struct array CPU: STATUS0 */ +/* + * STATUS (RO) + * + * IRQ values + */ +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK (0xFFFFFFFFUL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT (0U) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK) >> SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT) + +/* Bitfield definition for register of struct array CPU: ENABLE0 */ +/* + * ENABLE (RW) + * + * IRQ wakeup enable + */ +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT (0U) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) >> SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) + + + +/* RESOURCE register group index macro definition */ +#define SYSCTL_RESOURCE_CPU0 (0UL) +#define SYSCTL_RESOURCE_CPX0 (1UL) +#define SYSCTL_RESOURCE_POW_CPU0 (21UL) +#define SYSCTL_RESOURCE_RST_SOC (22UL) +#define SYSCTL_RESOURCE_RST_CPU0 (23UL) +#define SYSCTL_RESOURCE_CLK_SRC_XTAL (32UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL0 (33UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL0 (34UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL0 (35UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK2_PLL0 (36UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL1 (37UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL1 (38UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL1 (39UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK2_PLL1 (40UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK3_PLL1 (41UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL0_REF (42UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL1_REF (43UL) +#define SYSCTL_RESOURCE_CLK_TOP_CPU0 (64UL) +#define SYSCTL_RESOURCE_CLK_TOP_MCT0 (65UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN0 (66UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN1 (67UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN2 (68UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN3 (69UL) +#define SYSCTL_RESOURCE_CLK_TOP_TMR0 (74UL) +#define SYSCTL_RESOURCE_CLK_TOP_TMR1 (75UL) +#define SYSCTL_RESOURCE_CLK_TOP_TMR2 (76UL) +#define SYSCTL_RESOURCE_CLK_TOP_TMR3 (77UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2C0 (78UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2C1 (79UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2C2 (80UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2C3 (81UL) +#define SYSCTL_RESOURCE_CLK_TOP_SPI0 (82UL) +#define SYSCTL_RESOURCE_CLK_TOP_SPI1 (83UL) +#define SYSCTL_RESOURCE_CLK_TOP_SPI2 (84UL) +#define SYSCTL_RESOURCE_CLK_TOP_SPI3 (85UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT0 (86UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT1 (87UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT2 (88UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT3 (89UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT4 (90UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT5 (91UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT6 (92UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT7 (93UL) +#define SYSCTL_RESOURCE_CLK_TOP_XPI0 (94UL) +#define SYSCTL_RESOURCE_CLK_TOP_ANA0 (95UL) +#define SYSCTL_RESOURCE_CLK_TOP_ANA1 (96UL) +#define SYSCTL_RESOURCE_CLK_TOP_ANA2 (97UL) +#define SYSCTL_RESOURCE_CLK_TOP_ANA3 (98UL) +#define SYSCTL_RESOURCE_CLK_TOP_REF0 (99UL) +#define SYSCTL_RESOURCE_CLK_TOP_REF1 (100UL) +#define SYSCTL_RESOURCE_CLK_TOP_ADC0 (101UL) +#define SYSCTL_RESOURCE_CLK_TOP_ADC1 (102UL) +#define SYSCTL_RESOURCE_CLK_TOP_DAC0 (103UL) +#define SYSCTL_RESOURCE_CLK_TOP_DAC1 (104UL) +#define SYSCTL_RESOURCE_AHB0 (256UL) +#define SYSCTL_RESOURCE_LMM0 (257UL) +#define SYSCTL_RESOURCE_MCT0 (258UL) +#define SYSCTL_RESOURCE_ROM0 (259UL) +#define SYSCTL_RESOURCE_CAN0 (260UL) +#define SYSCTL_RESOURCE_CAN1 (261UL) +#define SYSCTL_RESOURCE_CAN2 (262UL) +#define SYSCTL_RESOURCE_CAN3 (263UL) +#define SYSCTL_RESOURCE_PTPC (264UL) +#define SYSCTL_RESOURCE_TMR0 (269UL) +#define SYSCTL_RESOURCE_TMR1 (270UL) +#define SYSCTL_RESOURCE_TMR2 (271UL) +#define SYSCTL_RESOURCE_TMR3 (272UL) +#define SYSCTL_RESOURCE_I2C0 (273UL) +#define SYSCTL_RESOURCE_I2C1 (274UL) +#define SYSCTL_RESOURCE_I2C2 (275UL) +#define SYSCTL_RESOURCE_I2C3 (276UL) +#define SYSCTL_RESOURCE_SPI0 (277UL) +#define SYSCTL_RESOURCE_SPI1 (278UL) +#define SYSCTL_RESOURCE_SPI2 (279UL) +#define SYSCTL_RESOURCE_SPI3 (280UL) +#define SYSCTL_RESOURCE_URT0 (281UL) +#define SYSCTL_RESOURCE_URT1 (282UL) +#define SYSCTL_RESOURCE_URT2 (283UL) +#define SYSCTL_RESOURCE_URT3 (284UL) +#define SYSCTL_RESOURCE_URT4 (285UL) +#define SYSCTL_RESOURCE_URT5 (286UL) +#define SYSCTL_RESOURCE_URT6 (287UL) +#define SYSCTL_RESOURCE_URT7 (288UL) +#define SYSCTL_RESOURCE_WDG0 (289UL) +#define SYSCTL_RESOURCE_WDG1 (290UL) +#define SYSCTL_RESOURCE_MBX0 (291UL) +#define SYSCTL_RESOURCE_TSNS (292UL) +#define SYSCTL_RESOURCE_CRC0 (293UL) +#define SYSCTL_RESOURCE_ADC0 (294UL) +#define SYSCTL_RESOURCE_ADC1 (295UL) +#define SYSCTL_RESOURCE_DAC0 (296UL) +#define SYSCTL_RESOURCE_DAC1 (297UL) +#define SYSCTL_RESOURCE_ACMP (298UL) +#define SYSCTL_RESOURCE_OPA0 (299UL) +#define SYSCTL_RESOURCE_OPA1 (300UL) +#define SYSCTL_RESOURCE_MOT0 (301UL) +#define SYSCTL_RESOURCE_RNG0 (302UL) +#define SYSCTL_RESOURCE_SDP0 (303UL) +#define SYSCTL_RESOURCE_KMAN (304UL) +#define SYSCTL_RESOURCE_GPIO (305UL) +#define SYSCTL_RESOURCE_HDMA (306UL) +#define SYSCTL_RESOURCE_XPI0 (307UL) +#define SYSCTL_RESOURCE_USB0 (308UL) +#define SYSCTL_RESOURCE_REF0 (309UL) +#define SYSCTL_RESOURCE_REF1 (310UL) + +/* GROUP0 register group index macro definition */ +#define SYSCTL_GROUP0_LINK0 (0UL) +#define SYSCTL_GROUP0_LINK1 (1UL) + +/* AFFILIATE register group index macro definition */ +#define SYSCTL_AFFILIATE_CPU0 (0UL) + +/* RETENTION register group index macro definition */ +#define SYSCTL_RETENTION_CPU0 (0UL) + +/* POWER register group index macro definition */ +#define SYSCTL_POWER_CPU0 (0UL) + +/* RESET register group index macro definition */ +#define SYSCTL_RESET_SOC (0UL) +#define SYSCTL_RESET_CPU0 (1UL) + +/* CLOCK_CPU register group index macro definition */ +#define SYSCTL_CLOCK_CPU_CLK_TOP_CPU0 (0UL) + +/* CLOCK register group index macro definition */ +#define SYSCTL_CLOCK_CLK_TOP_MCT0 (0UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN0 (1UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN1 (2UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN2 (3UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN3 (4UL) +#define SYSCTL_CLOCK_CLK_TOP_TMR0 (9UL) +#define SYSCTL_CLOCK_CLK_TOP_TMR1 (10UL) +#define SYSCTL_CLOCK_CLK_TOP_TMR2 (11UL) +#define SYSCTL_CLOCK_CLK_TOP_TMR3 (12UL) +#define SYSCTL_CLOCK_CLK_TOP_I2C0 (13UL) +#define SYSCTL_CLOCK_CLK_TOP_I2C1 (14UL) +#define SYSCTL_CLOCK_CLK_TOP_I2C2 (15UL) +#define SYSCTL_CLOCK_CLK_TOP_I2C3 (16UL) +#define SYSCTL_CLOCK_CLK_TOP_SPI0 (17UL) +#define SYSCTL_CLOCK_CLK_TOP_SPI1 (18UL) +#define SYSCTL_CLOCK_CLK_TOP_SPI2 (19UL) +#define SYSCTL_CLOCK_CLK_TOP_SPI3 (20UL) +#define SYSCTL_CLOCK_CLK_TOP_URT0 (21UL) +#define SYSCTL_CLOCK_CLK_TOP_URT1 (22UL) +#define SYSCTL_CLOCK_CLK_TOP_URT2 (23UL) +#define SYSCTL_CLOCK_CLK_TOP_URT3 (24UL) +#define SYSCTL_CLOCK_CLK_TOP_URT4 (25UL) +#define SYSCTL_CLOCK_CLK_TOP_URT5 (26UL) +#define SYSCTL_CLOCK_CLK_TOP_URT6 (27UL) +#define SYSCTL_CLOCK_CLK_TOP_URT7 (28UL) +#define SYSCTL_CLOCK_CLK_TOP_XPI0 (29UL) +#define SYSCTL_CLOCK_CLK_TOP_ANA0 (30UL) +#define SYSCTL_CLOCK_CLK_TOP_ANA1 (31UL) +#define SYSCTL_CLOCK_CLK_TOP_ANA2 (32UL) +#define SYSCTL_CLOCK_CLK_TOP_ANA3 (33UL) +#define SYSCTL_CLOCK_CLK_TOP_REF0 (34UL) +#define SYSCTL_CLOCK_CLK_TOP_REF1 (35UL) + +/* ADCCLK register group index macro definition */ +#define SYSCTL_ADCCLK_CLK_TOP_ADC0 (0UL) +#define SYSCTL_ADCCLK_CLK_TOP_ADC1 (1UL) + +/* DACCLK register group index macro definition */ +#define SYSCTL_DACCLK_CLK_TOP_DAC0 (0UL) +#define SYSCTL_DACCLK_CLK_TOP_DAC1 (1UL) + +/* MONITOR register group index macro definition */ +#define SYSCTL_MONITOR_SLICE0 (0UL) +#define SYSCTL_MONITOR_SLICE1 (1UL) +#define SYSCTL_MONITOR_SLICE2 (2UL) +#define SYSCTL_MONITOR_SLICE3 (3UL) + +/* GPR register group index macro definition */ +#define SYSCTL_CPU_GPR_GPR0 (0UL) +#define SYSCTL_CPU_GPR_GPR1 (1UL) +#define SYSCTL_CPU_GPR_GPR2 (2UL) +#define SYSCTL_CPU_GPR_GPR3 (3UL) +#define SYSCTL_CPU_GPR_GPR4 (4UL) +#define SYSCTL_CPU_GPR_GPR5 (5UL) +#define SYSCTL_CPU_GPR_GPR6 (6UL) +#define SYSCTL_CPU_GPR_GPR7 (7UL) +#define SYSCTL_CPU_GPR_GPR8 (8UL) +#define SYSCTL_CPU_GPR_GPR9 (9UL) +#define SYSCTL_CPU_GPR_GPR10 (10UL) +#define SYSCTL_CPU_GPR_GPR11 (11UL) +#define SYSCTL_CPU_GPR_GPR12 (12UL) +#define SYSCTL_CPU_GPR_GPR13 (13UL) + +/* WAKEUP_STATUS register group index macro definition */ +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS0 (0UL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS1 (1UL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS2 (2UL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS3 (3UL) + +/* WAKEUP_ENABLE register group index macro definition */ +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE0 (0UL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE1 (1UL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE2 (2UL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE3 (3UL) + +/* CPU register group index macro definition */ +#define SYSCTL_CPU_CPU0 (0UL) + + +#endif /* HPM_SYSCTL_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_trgm_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_trgm_regs.h new file mode 100644 index 00000000000..4d712e28520 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_trgm_regs.h @@ -0,0 +1,535 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_TRGM_H +#define HPM_TRGM_H + +typedef struct { + __RW uint32_t FILTCFG[28]; /* 0x0 - 0x6C: Filter configure register */ + __R uint8_t RESERVED0[144]; /* 0x70 - 0xFF: Reserved */ + __RW uint32_t TRGOCFG[137]; /* 0x100 - 0x320: Trigger manager output configure register */ + __R uint8_t RESERVED1[220]; /* 0x324 - 0x3FF: Reserved */ + __RW uint32_t DMACFG[8]; /* 0x400 - 0x41C: DMA request configure register */ + __R uint8_t RESERVED2[224]; /* 0x420 - 0x4FF: Reserved */ + __RW uint32_t GCR; /* 0x500: General Control Register */ + __R uint8_t RESERVED3[12]; /* 0x504 - 0x50F: Reserved */ + __RW uint32_t ADC_MATRIX_SEL; /* 0x510: adc matrix select register */ + __RW uint32_t DAC_MATRIX_SEL; /* 0x514: dac matrix select register */ + __RW uint32_t POS_MATRIX_SEL0; /* 0x518: position matrix select register0 */ + __RW uint32_t POS_MATRIX_SEL1; /* 0x51C: position matrix select register1 */ + __R uint8_t RESERVED4[224]; /* 0x520 - 0x5FF: Reserved */ + __R uint32_t TRGM_IN[4]; /* 0x600 - 0x60C: trigmux input read register0 */ + __R uint8_t RESERVED5[16]; /* 0x610 - 0x61F: Reserved */ + __R uint32_t TRGM_OUT[5]; /* 0x620 - 0x630: trigmux output read register0 */ +} TRGM_Type; + + +/* Bitfield definition for register array: FILTCFG */ +/* + * OUTINV (RW) + * + * 1- Filter will invert the output + * 0- Filter will not invert the output + */ +#define TRGM_FILTCFG_OUTINV_MASK (0x10000UL) +#define TRGM_FILTCFG_OUTINV_SHIFT (16U) +#define TRGM_FILTCFG_OUTINV_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_OUTINV_SHIFT) & TRGM_FILTCFG_OUTINV_MASK) +#define TRGM_FILTCFG_OUTINV_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_OUTINV_MASK) >> TRGM_FILTCFG_OUTINV_SHIFT) + +/* + * MODE (RW) + * + * This bitfields defines the filter mode + * 000-bypass; + * 100-rapid change mode; + * 101-delay filter mode; + * 110-stalbe low mode; + * 111-stable high mode + */ +#define TRGM_FILTCFG_MODE_MASK (0xE000U) +#define TRGM_FILTCFG_MODE_SHIFT (13U) +#define TRGM_FILTCFG_MODE_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_MODE_SHIFT) & TRGM_FILTCFG_MODE_MASK) +#define TRGM_FILTCFG_MODE_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_MODE_MASK) >> TRGM_FILTCFG_MODE_SHIFT) + +/* + * SYNCEN (RW) + * + * set to enable sychronization input signal with TRGM clock + */ +#define TRGM_FILTCFG_SYNCEN_MASK (0x1000U) +#define TRGM_FILTCFG_SYNCEN_SHIFT (12U) +#define TRGM_FILTCFG_SYNCEN_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_SYNCEN_SHIFT) & TRGM_FILTCFG_SYNCEN_MASK) +#define TRGM_FILTCFG_SYNCEN_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_SYNCEN_MASK) >> TRGM_FILTCFG_SYNCEN_SHIFT) + +/* + * FILTLEN_SHIFT (RW) + * + */ +#define TRGM_FILTCFG_FILTLEN_SHIFT_MASK (0xE00U) +#define TRGM_FILTCFG_FILTLEN_SHIFT_SHIFT (9U) +#define TRGM_FILTCFG_FILTLEN_SHIFT_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_FILTLEN_SHIFT_SHIFT) & TRGM_FILTCFG_FILTLEN_SHIFT_MASK) +#define TRGM_FILTCFG_FILTLEN_SHIFT_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_FILTLEN_SHIFT_MASK) >> TRGM_FILTCFG_FILTLEN_SHIFT_SHIFT) + +/* + * FILTLEN_BASE (RW) + * + * This bitfields defines the filter counter length. + */ +#define TRGM_FILTCFG_FILTLEN_BASE_MASK (0x1FFU) +#define TRGM_FILTCFG_FILTLEN_BASE_SHIFT (0U) +#define TRGM_FILTCFG_FILTLEN_BASE_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_FILTLEN_BASE_SHIFT) & TRGM_FILTCFG_FILTLEN_BASE_MASK) +#define TRGM_FILTCFG_FILTLEN_BASE_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_FILTLEN_BASE_MASK) >> TRGM_FILTCFG_FILTLEN_BASE_SHIFT) + +/* Bitfield definition for register array: TRGOCFG */ +/* + * OUTINV (RW) + * + * 1- Invert the output + */ +#define TRGM_TRGOCFG_OUTINV_MASK (0x800U) +#define TRGM_TRGOCFG_OUTINV_SHIFT (11U) +#define TRGM_TRGOCFG_OUTINV_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_OUTINV_SHIFT) & TRGM_TRGOCFG_OUTINV_MASK) +#define TRGM_TRGOCFG_OUTINV_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_OUTINV_MASK) >> TRGM_TRGOCFG_OUTINV_SHIFT) + +/* + * FEDG2PEN (RW) + * + * 1- The selected input signal falling edge will be convert to an pulse on output. + */ +#define TRGM_TRGOCFG_FEDG2PEN_MASK (0x400U) +#define TRGM_TRGOCFG_FEDG2PEN_SHIFT (10U) +#define TRGM_TRGOCFG_FEDG2PEN_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_FEDG2PEN_SHIFT) & TRGM_TRGOCFG_FEDG2PEN_MASK) +#define TRGM_TRGOCFG_FEDG2PEN_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_FEDG2PEN_MASK) >> TRGM_TRGOCFG_FEDG2PEN_SHIFT) + +/* + * REDG2PEN (RW) + * + * 1- The selected input signal rising edge will be convert to an pulse on output. + */ +#define TRGM_TRGOCFG_REDG2PEN_MASK (0x200U) +#define TRGM_TRGOCFG_REDG2PEN_SHIFT (9U) +#define TRGM_TRGOCFG_REDG2PEN_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_REDG2PEN_SHIFT) & TRGM_TRGOCFG_REDG2PEN_MASK) +#define TRGM_TRGOCFG_REDG2PEN_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_REDG2PEN_MASK) >> TRGM_TRGOCFG_REDG2PEN_SHIFT) + +/* + * TRIGOSEL (RW) + * + * This bitfield selects one of the TRGM inputs as output. + */ +#define TRGM_TRGOCFG_TRIGOSEL_MASK (0x7FU) +#define TRGM_TRGOCFG_TRIGOSEL_SHIFT (0U) +#define TRGM_TRGOCFG_TRIGOSEL_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_TRIGOSEL_SHIFT) & TRGM_TRGOCFG_TRIGOSEL_MASK) +#define TRGM_TRGOCFG_TRIGOSEL_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_TRIGOSEL_MASK) >> TRGM_TRGOCFG_TRIGOSEL_SHIFT) + +/* Bitfield definition for register array: DMACFG */ +/* + * DMAMUX_EN (RW) + * + */ +#define TRGM_DMACFG_DMAMUX_EN_MASK (0x80000000UL) +#define TRGM_DMACFG_DMAMUX_EN_SHIFT (31U) +#define TRGM_DMACFG_DMAMUX_EN_SET(x) (((uint32_t)(x) << TRGM_DMACFG_DMAMUX_EN_SHIFT) & TRGM_DMACFG_DMAMUX_EN_MASK) +#define TRGM_DMACFG_DMAMUX_EN_GET(x) (((uint32_t)(x) & TRGM_DMACFG_DMAMUX_EN_MASK) >> TRGM_DMACFG_DMAMUX_EN_SHIFT) + +/* + * DMASRCSEL (RW) + * + * This field selects one of the DMA requests as the DMA request output. + */ +#define TRGM_DMACFG_DMASRCSEL_MASK (0x3FU) +#define TRGM_DMACFG_DMASRCSEL_SHIFT (0U) +#define TRGM_DMACFG_DMASRCSEL_SET(x) (((uint32_t)(x) << TRGM_DMACFG_DMASRCSEL_SHIFT) & TRGM_DMACFG_DMASRCSEL_MASK) +#define TRGM_DMACFG_DMASRCSEL_GET(x) (((uint32_t)(x) & TRGM_DMACFG_DMASRCSEL_MASK) >> TRGM_DMACFG_DMASRCSEL_SHIFT) + +/* Bitfield definition for register: GCR */ +/* + * TRGOPEN (RW) + * + * The bitfield enable the TRGM outputs. + */ +#define TRGM_GCR_TRGOPEN_MASK (0xFFU) +#define TRGM_GCR_TRGOPEN_SHIFT (0U) +#define TRGM_GCR_TRGOPEN_SET(x) (((uint32_t)(x) << TRGM_GCR_TRGOPEN_SHIFT) & TRGM_GCR_TRGOPEN_MASK) +#define TRGM_GCR_TRGOPEN_GET(x) (((uint32_t)(x) & TRGM_GCR_TRGOPEN_MASK) >> TRGM_GCR_TRGOPEN_SHIFT) + +/* Bitfield definition for register: ADC_MATRIX_SEL */ +/* + * QEI1_ADC1_SEL (RW) + * + * 0-adc0; 1-adc1; 2-rdc_adc0; 3-rdc_adc1; + * bit7 is used to invert adc_value; + * others reserved + */ +#define TRGM_ADC_MATRIX_SEL_QEI1_ADC1_SEL_MASK (0xFF000000UL) +#define TRGM_ADC_MATRIX_SEL_QEI1_ADC1_SEL_SHIFT (24U) +#define TRGM_ADC_MATRIX_SEL_QEI1_ADC1_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL_QEI1_ADC1_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL_QEI1_ADC1_SEL_MASK) +#define TRGM_ADC_MATRIX_SEL_QEI1_ADC1_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL_QEI1_ADC1_SEL_MASK) >> TRGM_ADC_MATRIX_SEL_QEI1_ADC1_SEL_SHIFT) + +/* + * QEI1_ADC0_SEL (RW) + * + */ +#define TRGM_ADC_MATRIX_SEL_QEI1_ADC0_SEL_MASK (0xFF0000UL) +#define TRGM_ADC_MATRIX_SEL_QEI1_ADC0_SEL_SHIFT (16U) +#define TRGM_ADC_MATRIX_SEL_QEI1_ADC0_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL_QEI1_ADC0_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL_QEI1_ADC0_SEL_MASK) +#define TRGM_ADC_MATRIX_SEL_QEI1_ADC0_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL_QEI1_ADC0_SEL_MASK) >> TRGM_ADC_MATRIX_SEL_QEI1_ADC0_SEL_SHIFT) + +/* + * QEI0_ADC1_SEL (RW) + * + */ +#define TRGM_ADC_MATRIX_SEL_QEI0_ADC1_SEL_MASK (0xFF00U) +#define TRGM_ADC_MATRIX_SEL_QEI0_ADC1_SEL_SHIFT (8U) +#define TRGM_ADC_MATRIX_SEL_QEI0_ADC1_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL_QEI0_ADC1_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL_QEI0_ADC1_SEL_MASK) +#define TRGM_ADC_MATRIX_SEL_QEI0_ADC1_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL_QEI0_ADC1_SEL_MASK) >> TRGM_ADC_MATRIX_SEL_QEI0_ADC1_SEL_SHIFT) + +/* + * QEI0_ADC0_SEL (RW) + * + */ +#define TRGM_ADC_MATRIX_SEL_QEI0_ADC0_SEL_MASK (0xFFU) +#define TRGM_ADC_MATRIX_SEL_QEI0_ADC0_SEL_SHIFT (0U) +#define TRGM_ADC_MATRIX_SEL_QEI0_ADC0_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL_QEI0_ADC0_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL_QEI0_ADC0_SEL_MASK) +#define TRGM_ADC_MATRIX_SEL_QEI0_ADC0_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL_QEI0_ADC0_SEL_MASK) >> TRGM_ADC_MATRIX_SEL_QEI0_ADC0_SEL_SHIFT) + +/* Bitfield definition for register: DAC_MATRIX_SEL */ +/* + * DAC1_DAC_SEL (RW) + * + * 0-qeo0_dac0; 1-qeo0_dac1; 2-qeo0_dac2; + * 3-qeo1_dac0; 4-qeo1_dac1; 5-qeo1_dac2; + * 6-rdc_dac0; 7-rdc_dac1; + * bit7 is used to invert dac_value; + * others reserved + */ +#define TRGM_DAC_MATRIX_SEL_DAC1_DAC_SEL_MASK (0xFF000000UL) +#define TRGM_DAC_MATRIX_SEL_DAC1_DAC_SEL_SHIFT (24U) +#define TRGM_DAC_MATRIX_SEL_DAC1_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL_DAC1_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL_DAC1_DAC_SEL_MASK) +#define TRGM_DAC_MATRIX_SEL_DAC1_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL_DAC1_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL_DAC1_DAC_SEL_SHIFT) + +/* + * DAC0_DAC_SEL (RW) + * + */ +#define TRGM_DAC_MATRIX_SEL_DAC0_DAC_SEL_MASK (0xFF0000UL) +#define TRGM_DAC_MATRIX_SEL_DAC0_DAC_SEL_SHIFT (16U) +#define TRGM_DAC_MATRIX_SEL_DAC0_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL_DAC0_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL_DAC0_DAC_SEL_MASK) +#define TRGM_DAC_MATRIX_SEL_DAC0_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL_DAC0_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL_DAC0_DAC_SEL_SHIFT) + +/* + * ACMP1_DAC_SEL (RW) + * + */ +#define TRGM_DAC_MATRIX_SEL_ACMP1_DAC_SEL_MASK (0xFF00U) +#define TRGM_DAC_MATRIX_SEL_ACMP1_DAC_SEL_SHIFT (8U) +#define TRGM_DAC_MATRIX_SEL_ACMP1_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL_ACMP1_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL_ACMP1_DAC_SEL_MASK) +#define TRGM_DAC_MATRIX_SEL_ACMP1_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL_ACMP1_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL_ACMP1_DAC_SEL_SHIFT) + +/* + * ACMP0_DAC_SEL (RW) + * + */ +#define TRGM_DAC_MATRIX_SEL_ACMP0_DAC_SEL_MASK (0xFFU) +#define TRGM_DAC_MATRIX_SEL_ACMP0_DAC_SEL_SHIFT (0U) +#define TRGM_DAC_MATRIX_SEL_ACMP0_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL_ACMP0_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL_ACMP0_DAC_SEL_MASK) +#define TRGM_DAC_MATRIX_SEL_ACMP0_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL_ACMP0_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL_ACMP0_DAC_SEL_SHIFT) + +/* Bitfield definition for register: POS_MATRIX_SEL0 */ +/* + * MMC1_POSIN_SEL (RW) + * + * 0-sei_pos_out0; 1-sei_pos_out1; + * 2-qei0_pos; 3-qei1_pos; + * 4-mmc0_pos_out0; 5-mmc0_pos_out1; + * 6-mmc1_pos_out0; 7-mmc1_pos_out1; + * bit7 is used to invert position value; + * others reserved + */ +#define TRGM_POS_MATRIX_SEL0_MMC1_POSIN_SEL_MASK (0xFF000000UL) +#define TRGM_POS_MATRIX_SEL0_MMC1_POSIN_SEL_SHIFT (24U) +#define TRGM_POS_MATRIX_SEL0_MMC1_POSIN_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL0_MMC1_POSIN_SEL_SHIFT) & TRGM_POS_MATRIX_SEL0_MMC1_POSIN_SEL_MASK) +#define TRGM_POS_MATRIX_SEL0_MMC1_POSIN_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL0_MMC1_POSIN_SEL_MASK) >> TRGM_POS_MATRIX_SEL0_MMC1_POSIN_SEL_SHIFT) + +/* + * MMC0_POSIN_SEL (RW) + * + */ +#define TRGM_POS_MATRIX_SEL0_MMC0_POSIN_SEL_MASK (0xFF0000UL) +#define TRGM_POS_MATRIX_SEL0_MMC0_POSIN_SEL_SHIFT (16U) +#define TRGM_POS_MATRIX_SEL0_MMC0_POSIN_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL0_MMC0_POSIN_SEL_SHIFT) & TRGM_POS_MATRIX_SEL0_MMC0_POSIN_SEL_MASK) +#define TRGM_POS_MATRIX_SEL0_MMC0_POSIN_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL0_MMC0_POSIN_SEL_MASK) >> TRGM_POS_MATRIX_SEL0_MMC0_POSIN_SEL_SHIFT) + +/* + * SEI_POSIN1_SEL (RW) + * + */ +#define TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_MASK (0xFF00U) +#define TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_SHIFT (8U) +#define TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_SHIFT) & TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_MASK) +#define TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_MASK) >> TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_SHIFT) + +/* + * SEI_POSIN0_SEL (RW) + * + */ +#define TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_MASK (0xFFU) +#define TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_SHIFT (0U) +#define TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_SHIFT) & TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_MASK) +#define TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_MASK) >> TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_SHIFT) + +/* Bitfield definition for register: POS_MATRIX_SEL1 */ +/* + * QEO1_POS_SEL (RW) + * + */ +#define TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_MASK (0xFF00U) +#define TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_SHIFT (8U) +#define TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_SHIFT) & TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_MASK) +#define TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_MASK) >> TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_SHIFT) + +/* + * QEO0_POS_SEL (RW) + * + */ +#define TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_MASK (0xFFU) +#define TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_SHIFT (0U) +#define TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_SHIFT) & TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_MASK) +#define TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_MASK) >> TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_SHIFT) + +/* Bitfield definition for register array: TRGM_IN */ +/* + * TRGM_IN (RO) + * + * mmc1_trig_out[1:0], mmc0_trig_out[1:0],sync_pulse[3:0],moto_gpio_in_sync[7:0],//31:16 + * gtmr3_to_motor_sync[1:0],gtmr2_to_motor_sync[1:0],gtmr1_to_motor_sync[1:0],gtmr0_to_motor_sync[1:0], //15:8 + * acmp_out_sync[1:0],can2mot_event_sync[1:0],usb0_sof_tog_sync,pwm_debug,1'b1,1'b0 //7:0 + */ +#define TRGM_TRGM_IN_TRGM_IN_MASK (0xFFFFFFFFUL) +#define TRGM_TRGM_IN_TRGM_IN_SHIFT (0U) +#define TRGM_TRGM_IN_TRGM_IN_GET(x) (((uint32_t)(x) & TRGM_TRGM_IN_TRGM_IN_MASK) >> TRGM_TRGM_IN_TRGM_IN_SHIFT) + +/* Bitfield definition for register array: TRGM_OUT */ +/* + * TRGM_OUT (RO) + * + * motor_to_opamp0[7:0] = trig_mux_out[7:0]; + * motor_to_opamp1[7:0] = trig_mux_out[15:8]; + * motor_to_gtmr0_capt[1:0] = trig_mux_out[17:16]; + * motor_to_gtmr0_sync = trig_mux_out[18]; + * motor_to_gtmr1_capt[1:0] = trig_mux_out[20:19]; + * motor_to_gtmr1_sync = trig_mux_out[21]; + * motor_to_gtmr2_capt[1:0] = trig_mux_out[23:22]; + * motor_to_gtmr2_sync = trig_mux_out[24]; + * motor_to_gtmr3_capt[1:0] = trig_mux_out[26:25]; + * motor_to_gtmr3_sync = trig_mux_out[27]; + * acmp_window[1:0] = trig_mux_out[29:28]; + * dac0_buf_trigger = trig_mux_out[30]; + * dac1_buf_trigger = trig_mux_out[31]; + * dac0_step_trigger[3:0] = {trig_mux_out[24:22],trig_mux_out[30]};//use same buf_trig, and gtmr2 + * dac1_step_trigger[3:0] = {trig_mux_out[27:25],trig_mux_out[31]}; //use same buf_trig, and gtmr3 + */ +#define TRGM_TRGM_OUT_TRGM_OUT_MASK (0xFFFFFFFFUL) +#define TRGM_TRGM_OUT_TRGM_OUT_SHIFT (0U) +#define TRGM_TRGM_OUT_TRGM_OUT_GET(x) (((uint32_t)(x) & TRGM_TRGM_OUT_TRGM_OUT_MASK) >> TRGM_TRGM_OUT_TRGM_OUT_SHIFT) + + + +/* FILTCFG register group index macro definition */ +#define TRGM_FILTCFG_PWM0_IN0 (0UL) +#define TRGM_FILTCFG_PWM0_IN1 (1UL) +#define TRGM_FILTCFG_PWM0_IN2 (2UL) +#define TRGM_FILTCFG_PWM0_IN3 (3UL) +#define TRGM_FILTCFG_PWM0_IN4 (4UL) +#define TRGM_FILTCFG_PWM0_IN5 (5UL) +#define TRGM_FILTCFG_PWM0_IN6 (6UL) +#define TRGM_FILTCFG_PWM0_IN7 (7UL) +#define TRGM_FILTCFG_PWM1_IN0 (8UL) +#define TRGM_FILTCFG_PWM1_IN1 (9UL) +#define TRGM_FILTCFG_PWM1_IN2 (10UL) +#define TRGM_FILTCFG_PWM1_IN3 (11UL) +#define TRGM_FILTCFG_PWM1_IN4 (12UL) +#define TRGM_FILTCFG_PWM1_IN5 (13UL) +#define TRGM_FILTCFG_PWM1_IN6 (14UL) +#define TRGM_FILTCFG_PWM1_IN7 (15UL) +#define TRGM_FILTCFG_MOTO_GPIO_IN0 (16UL) +#define TRGM_FILTCFG_MOTO_GPIO_IN1 (17UL) +#define TRGM_FILTCFG_MOTO_GPIO_IN2 (18UL) +#define TRGM_FILTCFG_MOTO_GPIO_IN3 (19UL) +#define TRGM_FILTCFG_MOTO_GPIO_IN4 (20UL) +#define TRGM_FILTCFG_MOTO_GPIO_IN5 (21UL) +#define TRGM_FILTCFG_MOTO_GPIO_IN6 (22UL) +#define TRGM_FILTCFG_MOTO_GPIO_IN7 (23UL) +#define TRGM_FILTCFG_PWM0_FAULT0 (24UL) +#define TRGM_FILTCFG_PWM0_FAULT1 (25UL) +#define TRGM_FILTCFG_PWM1_FAULT0 (26UL) +#define TRGM_FILTCFG_PWM1_FAULT1 (27UL) + +/* TRGOCFG register group index macro definition */ +#define TRGM_TRGOCFG_MOT2OPAMP0_0 (0UL) +#define TRGM_TRGOCFG_MOT2OPAMP0_1 (1UL) +#define TRGM_TRGOCFG_MOT2OPAMP0_2 (2UL) +#define TRGM_TRGOCFG_MOT2OPAMP0_3 (3UL) +#define TRGM_TRGOCFG_MOT2OPAMP0_4 (4UL) +#define TRGM_TRGOCFG_MOT2OPAMP0_5 (5UL) +#define TRGM_TRGOCFG_MOT2OPAMP0_6 (6UL) +#define TRGM_TRGOCFG_MOT2OPAMP0_7 (7UL) +#define TRGM_TRGOCFG_MOT2OPAMP1_0 (8UL) +#define TRGM_TRGOCFG_MOT2OPAMP1_1 (9UL) +#define TRGM_TRGOCFG_MOT2OPAMP1_2 (10UL) +#define TRGM_TRGOCFG_MOT2OPAMP1_3 (11UL) +#define TRGM_TRGOCFG_MOT2OPAMP1_4 (12UL) +#define TRGM_TRGOCFG_MOT2OPAMP1_5 (13UL) +#define TRGM_TRGOCFG_MOT2OPAMP1_6 (14UL) +#define TRGM_TRGOCFG_MOT2OPAMP1_7 (15UL) +#define TRGM_TRGOCFG_GPTMR0_IN2 (16UL) +#define TRGM_TRGOCFG_GPTMR0_IN3 (17UL) +#define TRGM_TRGOCFG_GPTMR0_SYNCI (18UL) +#define TRGM_TRGOCFG_GPTMR1_IN2 (19UL) +#define TRGM_TRGOCFG_GPTMR1_IN3 (20UL) +#define TRGM_TRGOCFG_GPTMR1_SYNCI (21UL) +#define TRGM_TRGOCFG_GPTMR2_IN2 (22UL) +#define TRGM_TRGOCFG_GPTMR2_IN3 (23UL) +#define TRGM_TRGOCFG_GPTMR2_SYNCI (24UL) +#define TRGM_TRGOCFG_GPTMR3_IN2 (25UL) +#define TRGM_TRGOCFG_GPTMR3_IN3 (26UL) +#define TRGM_TRGOCFG_GPTMR3_SYNCI (27UL) +#define TRGM_TRGOCFG_CMP0_WIN (28UL) +#define TRGM_TRGOCFG_CMP1_WIN (29UL) +#define TRGM_TRGOCFG_DAC0_BUFTRG (30UL) +#define TRGM_TRGOCFG_DAC1_BUFTRG (31UL) +#define TRGM_TRGOCFG_ADC0_STRGI (32UL) +#define TRGM_TRGOCFG_ADC1_STRGI (33UL) +#define TRGM_TRGOCFG_ADCX_PTRGI0A (34UL) +#define TRGM_TRGOCFG_ADCX_PTRGI0B (35UL) +#define TRGM_TRGOCFG_ADCX_PTRGI0C (36UL) +#define TRGM_TRGOCFG_ADCX_PTRGI1A (37UL) +#define TRGM_TRGOCFG_ADCX_PTRGI1B (38UL) +#define TRGM_TRGOCFG_ADCX_PTRGI1C (39UL) +#define TRGM_TRGOCFG_ADCX_PTRGI2A (40UL) +#define TRGM_TRGOCFG_ADCX_PTRGI2B (41UL) +#define TRGM_TRGOCFG_ADCX_PTRGI2C (42UL) +#define TRGM_TRGOCFG_ADCX_PTRGI3A (43UL) +#define TRGM_TRGOCFG_ADCX_PTRGI3B (44UL) +#define TRGM_TRGOCFG_ADCX_PTRGI3C (45UL) +#define TRGM_TRGOCFG_CAN_PTPC0_CAP (46UL) +#define TRGM_TRGOCFG_CAN_PTPC1_CAP (47UL) +#define TRGM_TRGOCFG_QEO0_TRIG_IN0 (48UL) +#define TRGM_TRGOCFG_QEO0_TRIG_IN1 (49UL) +#define TRGM_TRGOCFG_QEO1_TRIG_IN0 (50UL) +#define TRGM_TRGOCFG_QEO1_TRIG_IN1 (51UL) +#define TRGM_TRGOCFG_SEI_TRIG_IN0 (52UL) +#define TRGM_TRGOCFG_SEI_TRIG_IN1 (53UL) +#define TRGM_TRGOCFG_SEI_TRIG_IN2 (54UL) +#define TRGM_TRGOCFG_SEI_TRIG_IN3 (55UL) +#define TRGM_TRGOCFG_SEI_TRIG_IN4 (56UL) +#define TRGM_TRGOCFG_SEI_TRIG_IN5 (57UL) +#define TRGM_TRGOCFG_SEI_TRIG_IN6 (58UL) +#define TRGM_TRGOCFG_SEI_TRIG_IN7 (59UL) +#define TRGM_TRGOCFG_MMC0_TRIG_IN0 (60UL) +#define TRGM_TRGOCFG_MMC0_TRIG_IN1 (61UL) +#define TRGM_TRGOCFG_MMC1_TRIG_IN0 (62UL) +#define TRGM_TRGOCFG_MMC1_TRIG_IN1 (63UL) +#define TRGM_TRGOCFG_PLB_IN_00 (64UL) +#define TRGM_TRGOCFG_PLB_IN_01 (65UL) +#define TRGM_TRGOCFG_PLB_IN_02 (66UL) +#define TRGM_TRGOCFG_PLB_IN_03 (67UL) +#define TRGM_TRGOCFG_PLB_IN_04 (68UL) +#define TRGM_TRGOCFG_PLB_IN_05 (69UL) +#define TRGM_TRGOCFG_PLB_IN_06 (70UL) +#define TRGM_TRGOCFG_PLB_IN_07 (71UL) +#define TRGM_TRGOCFG_PLB_IN_08 (72UL) +#define TRGM_TRGOCFG_PLB_IN_09 (73UL) +#define TRGM_TRGOCFG_PLB_IN_10 (74UL) +#define TRGM_TRGOCFG_PLB_IN_11 (75UL) +#define TRGM_TRGOCFG_PLB_IN_12 (76UL) +#define TRGM_TRGOCFG_PLB_IN_13 (77UL) +#define TRGM_TRGOCFG_PLB_IN_14 (78UL) +#define TRGM_TRGOCFG_PLB_IN_15 (79UL) +#define TRGM_TRGOCFG_PLB_IN_16 (80UL) +#define TRGM_TRGOCFG_PLB_IN_17 (81UL) +#define TRGM_TRGOCFG_PLB_IN_18 (82UL) +#define TRGM_TRGOCFG_PLB_IN_19 (83UL) +#define TRGM_TRGOCFG_PLB_IN_20 (84UL) +#define TRGM_TRGOCFG_PLB_IN_21 (85UL) +#define TRGM_TRGOCFG_PLB_IN_22 (86UL) +#define TRGM_TRGOCFG_PLB_IN_23 (87UL) +#define TRGM_TRGOCFG_PLB_IN_24 (88UL) +#define TRGM_TRGOCFG_PLB_IN_25 (89UL) +#define TRGM_TRGOCFG_PLB_IN_26 (90UL) +#define TRGM_TRGOCFG_PLB_IN_27 (91UL) +#define TRGM_TRGOCFG_PLB_IN_28 (92UL) +#define TRGM_TRGOCFG_PLB_IN_29 (93UL) +#define TRGM_TRGOCFG_PLB_IN_30 (94UL) +#define TRGM_TRGOCFG_PLB_IN_31 (95UL) +#define TRGM_TRGOCFG_MOT_GPIO0 (96UL) +#define TRGM_TRGOCFG_MOT_GPIO1 (97UL) +#define TRGM_TRGOCFG_MOT_GPIO2 (98UL) +#define TRGM_TRGOCFG_MOT_GPIO3 (99UL) +#define TRGM_TRGOCFG_MOT_GPIO4 (100UL) +#define TRGM_TRGOCFG_MOT_GPIO5 (101UL) +#define TRGM_TRGOCFG_MOT_GPIO6 (102UL) +#define TRGM_TRGOCFG_MOT_GPIO7 (103UL) +#define TRGM_TRGOCFG_PWM_IN8 (104UL) +#define TRGM_TRGOCFG_PWM_IN9 (105UL) +#define TRGM_TRGOCFG_PWM_IN10 (106UL) +#define TRGM_TRGOCFG_PWM_IN11 (107UL) +#define TRGM_TRGOCFG_PWM_IN12 (108UL) +#define TRGM_TRGOCFG_PWM_IN13 (109UL) +#define TRGM_TRGOCFG_PWM_IN14 (110UL) +#define TRGM_TRGOCFG_PWM_IN15 (111UL) +#define TRGM_TRGOCFG_PWM0_FRCI (112UL) +#define TRGM_TRGOCFG_PWM0_FRCSYNCI (113UL) +#define TRGM_TRGOCFG_PWM0_SYNCI (114UL) +#define TRGM_TRGOCFG_PWM0_SHRLDSYNCI (115UL) +#define TRGM_TRGOCFG_PWM0_FAULTI0 (116UL) +#define TRGM_TRGOCFG_PWM0_FAULTI1 (117UL) +#define TRGM_TRGOCFG_PWM1_FRCI (118UL) +#define TRGM_TRGOCFG_PWM1_FRCSYNCI (119UL) +#define TRGM_TRGOCFG_PWM1_SYNCI (120UL) +#define TRGM_TRGOCFG_PWM1_SHRLDSYNCI (121UL) +#define TRGM_TRGOCFG_PWM1_FAULTI0 (122UL) +#define TRGM_TRGOCFG_PWM1_FAULTI1 (123UL) +#define TRGM_TRGOCFG_RDC_TRIG_IN0 (124UL) +#define TRGM_TRGOCFG_RDC_TRIG_IN1 (125UL) +#define TRGM_TRGOCFG_SYNCTIMER_TRIG (126UL) +#define TRGM_TRGOCFG_QEI0_TRIG_IN (127UL) +#define TRGM_TRGOCFG_QEI1_TRIG_IN (128UL) +#define TRGM_TRGOCFG_QEI0_PAUSE (129UL) +#define TRGM_TRGOCFG_QEI1_PAUSE (130UL) +#define TRGM_TRGOCFG_UART_TRIG0 (131UL) +#define TRGM_TRGOCFG_UART_TRIG1 (132UL) +#define TRGM_TRGOCFG_TRGM_IRQ0 (133UL) +#define TRGM_TRGOCFG_TRGM_IRQ1 (134UL) +#define TRGM_TRGOCFG_TRGM_DMA0 (135UL) +#define TRGM_TRGOCFG_TRGM_DMA1 (136UL) + +/* DMACFG register group index macro definition */ +#define TRGM_DMACFG_0 (0UL) +#define TRGM_DMACFG_1 (1UL) +#define TRGM_DMACFG_2 (2UL) +#define TRGM_DMACFG_3 (3UL) +#define TRGM_DMACFG_4 (4UL) +#define TRGM_DMACFG_5 (5UL) +#define TRGM_DMACFG_6 (6UL) +#define TRGM_DMACFG_7 (7UL) + +/* TRGM_IN register group index macro definition */ +#define TRGM_TRGM_IN_0 (0UL) +#define TRGM_TRGM_IN_1 (1UL) +#define TRGM_TRGM_IN_2 (2UL) +#define TRGM_TRGM_IN_3 (3UL) + +/* TRGM_OUT register group index macro definition */ +#define TRGM_TRGM_OUT_0 (0UL) +#define TRGM_TRGM_OUT_1 (1UL) +#define TRGM_TRGM_OUT_2 (2UL) +#define TRGM_TRGM_OUT_3 (3UL) +#define TRGM_TRGM_OUT_4 (4UL) + + +#endif /* HPM_TRGM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_trgm_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_trgm_soc_drv.h new file mode 100644 index 00000000000..29143932dc9 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_trgm_soc_drv.h @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2021-2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_TRGM_SOC_DRV_H +#define HPM_TRGM_SOC_DRV_H + +#include "hpm_soc.h" +#include "hpm_trgm_regs.h" + +typedef enum { + trgm_adc_matrix_output_to_qei0_adc0 = 0, + trgm_adc_matrix_output_to_qei0_adc1 = 1, + trgm_adc_matrix_output_to_qei1_adc0 = 2, + trgm_adc_matrix_output_to_qei1_adc1 = 3, +} trgm_adc_matrix_out_t; + +typedef enum { + trgm_adc_matrix_in_from_adc0 = 0, + trgm_adc_matrix_in_from_adc1 = 1, + trgm_adc_matrix_in_from_rdc_adc0 = 2, + trgm_adc_matrix_in_from_rdc_adc1 = 3, +} trgm_adc_matrix_in_t; + +typedef enum { + trgm_dac_matrix_output_to_acmp0 = 0, + trgm_dac_matrix_output_to_acmp1 = 1, + trgm_dac_matrix_output_to_dac0 = 2, + trgm_dac_matrix_output_to_dac1 = 3, +} trgm_dac_matrix_out_t; + +typedef enum { + trgm_dac_matrix_in_from_qeo0_dac0 = 0, + trgm_dac_matrix_in_from_qeo0_dac1 = 1, + trgm_dac_matrix_in_from_qeo0_dac2 = 2, + trgm_dac_matrix_in_from_qeo1_dac0 = 3, + trgm_dac_matrix_in_from_qeo1_dac1 = 4, + trgm_dac_matrix_in_from_qeo1_dac2 = 5, + trgm_dac_matrix_in_from_rdc_dac0 = 6, + trgm_dac_matrix_in_from_rdc_dac1 = 7, +} trgm_dac_matrix_in_t; + +typedef enum { + trgm_pos_matrix_output_to_sei_pos0 = 0, + trgm_pos_matrix_output_to_sei_pos1 = 1, + trgm_pos_matrix_output_to_mmc0 = 2, + trgm_pos_matrix_output_to_mmc1 = 3, + trgm_pos_matrix_output_to_qeo0 = 4, + trgm_pos_matrix_output_to_qeo1 = 5, +} trgm_pos_matrix_out_t; + +typedef enum { + trgm_pos_matrix_in_from_sei_pos0 = 0, + trgm_pos_matrix_in_from_sei_pos1 = 1, + trgm_pos_matrix_in_from_qei0 = 2, + trgm_pos_matrix_in_from_qei1 = 3, + trgm_pos_matrix_in_from_mmc0_pos0 = 4, + trgm_pos_matrix_in_from_mmc0_pos1 = 5, + trgm_pos_matrix_in_from_mmc1_pos0 = 6, + trgm_pos_matrix_in_from_mmc1_pos1 = 7, +} trgm_pos_matrix_in_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +static inline void trgm_adc_matrix_config(TRGM_Type *ptr, trgm_adc_matrix_out_t consumer, trgm_adc_matrix_in_t src, bool inv_val) +{ + if (inv_val) { + ptr->ADC_MATRIX_SEL |= 0x80 << consumer * 8U; + } else { + ptr->ADC_MATRIX_SEL &= ~(0x80 << consumer * 8U); + } + ptr->ADC_MATRIX_SEL &= ~(0x7f << consumer * 8U); + ptr->ADC_MATRIX_SEL |= src << consumer * 8U; +} + +static inline void trgm_dac_matrix_config(TRGM_Type *ptr, trgm_dac_matrix_out_t consumer, trgm_dac_matrix_in_t src, bool inv_val) +{ + if (inv_val) { + ptr->DAC_MATRIX_SEL |= 0x80 << consumer * 8U; + } else { + ptr->DAC_MATRIX_SEL &= ~(0x80 << consumer * 8U); + } + ptr->DAC_MATRIX_SEL &= ~(0x7f << consumer * 8U); + ptr->DAC_MATRIX_SEL |= src << consumer * 8U; +} + +static inline void trgm_pos_matrix_config(TRGM_Type *ptr, trgm_pos_matrix_out_t consumer, trgm_pos_matrix_in_t src, bool inv_val) +{ + uint8_t index = consumer / 4U; + uint8_t offset = (consumer % 4U) * 8U; + + if (index == 0) { + if (inv_val) { + ptr->POS_MATRIX_SEL0 |= 0x80 << offset; + } else { + ptr->POS_MATRIX_SEL0 &= ~(0x80 << offset); + } + ptr->POS_MATRIX_SEL0 &= ~(0x7f << offset); + ptr->POS_MATRIX_SEL0 |= src << offset; + } else if (index == 1) { + if (inv_val) { + ptr->POS_MATRIX_SEL1 |= 0x80 << offset; + } else { + ptr->POS_MATRIX_SEL1 &= ~(0x80 << offset); + } + ptr->POS_MATRIX_SEL1 &= ~(0x7f << offset); + ptr->POS_MATRIX_SEL1 |= src << offset; + } +} + +#if defined(__cplusplus) +} +#endif + +#endif /* HPM_TRGM_SOC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_trgmmux_src.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_trgmmux_src.h new file mode 100644 index 00000000000..42eed680bb5 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_trgmmux_src.h @@ -0,0 +1,377 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_TRGMMUX_SRC_H +#define HPM_TRGMMUX_SRC_H + +/* trgm0_input mux definitions */ +#define HPM_TRGM0_INPUT_SRC_VSS (0x0UL) +#define HPM_TRGM0_INPUT_SRC_VDD (0x1UL) +#define HPM_TRGM0_INPUT_SRC_DEBUG_FLAG (0x2UL) +#define HPM_TRGM0_INPUT_SRC_USB0_SOF (0x3UL) +#define HPM_TRGM0_INPUT_SRC_PTPC_CMP0 (0x4UL) +#define HPM_TRGM0_INPUT_SRC_PTPC_CMP1 (0x5UL) +#define HPM_TRGM0_INPUT_SRC_CMP0_OUT (0x6UL) +#define HPM_TRGM0_INPUT_SRC_CMP1_OUT (0x7UL) +#define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT2 (0x8UL) +#define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT3 (0x9UL) +#define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT2 (0xAUL) +#define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT3 (0xBUL) +#define HPM_TRGM0_INPUT_SRC_GPTMR2_OUT2 (0xCUL) +#define HPM_TRGM0_INPUT_SRC_GPTMR2_OUT3 (0xDUL) +#define HPM_TRGM0_INPUT_SRC_GPTMR3_OUT2 (0xEUL) +#define HPM_TRGM0_INPUT_SRC_GPTMR3_OUT3 (0xFUL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P0 (0x10UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P1 (0x11UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P2 (0x12UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P3 (0x13UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P4 (0x14UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P5 (0x15UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P6 (0x16UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P7 (0x17UL) +#define HPM_TRGM0_INPUT_SRC_SYNT0_CH0 (0x18UL) +#define HPM_TRGM0_INPUT_SRC_SYNT0_CH1 (0x19UL) +#define HPM_TRGM0_INPUT_SRC_SYNT0_CH2 (0x1AUL) +#define HPM_TRGM0_INPUT_SRC_SYNT0_CH3 (0x1BUL) +#define HPM_TRGM0_INPUT_SRC_MMC0_TRGO_0 (0x1CUL) +#define HPM_TRGM0_INPUT_SRC_MMC0_TRGO_1 (0x1DUL) +#define HPM_TRGM0_INPUT_SRC_MMC1_TRGO_0 (0x1EUL) +#define HPM_TRGM0_INPUT_SRC_MMC1_TRGO_1 (0x1FUL) +#define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_0 (0x20UL) +#define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_1 (0x21UL) +#define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_2 (0x22UL) +#define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_3 (0x23UL) +#define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_4 (0x24UL) +#define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_5 (0x25UL) +#define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_6 (0x26UL) +#define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_7 (0x27UL) +#define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_0 (0x28UL) +#define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_1 (0x29UL) +#define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_2 (0x2AUL) +#define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_3 (0x2BUL) +#define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_4 (0x2CUL) +#define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_5 (0x2DUL) +#define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_6 (0x2EUL) +#define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_7 (0x2FUL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH8REF (0x30UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH9REF (0x31UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH10REF (0x32UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH11REF (0x33UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH12REF (0x34UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH13REF (0x35UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH14REF (0x36UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH15REF (0x37UL) +#define HPM_TRGM0_INPUT_SRC_PWM1_CH8REF (0x38UL) +#define HPM_TRGM0_INPUT_SRC_PWM1_CH9REF (0x39UL) +#define HPM_TRGM0_INPUT_SRC_PWM1_CH10REF (0x3AUL) +#define HPM_TRGM0_INPUT_SRC_PWM1_CH11REF (0x3BUL) +#define HPM_TRGM0_INPUT_SRC_PWM1_CH12REF (0x3CUL) +#define HPM_TRGM0_INPUT_SRC_PWM1_CH13REF (0x3DUL) +#define HPM_TRGM0_INPUT_SRC_PWM1_CH14REF (0x3EUL) +#define HPM_TRGM0_INPUT_SRC_PWM1_CH15REF (0x3FUL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT00 (0x40UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT01 (0x41UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT02 (0x42UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT03 (0x43UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT04 (0x44UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT05 (0x45UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT06 (0x46UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT07 (0x47UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT08 (0x48UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT09 (0x49UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT10 (0x4AUL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT11 (0x4BUL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT12 (0x4CUL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT13 (0x4DUL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT14 (0x4EUL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT15 (0x4FUL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT16 (0x50UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT17 (0x51UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT18 (0x52UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT19 (0x53UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT20 (0x54UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT21 (0x55UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT22 (0x56UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT23 (0x57UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT24 (0x58UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT25 (0x59UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT26 (0x5AUL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT27 (0x5BUL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT28 (0x5CUL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT29 (0x5DUL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT30 (0x5EUL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT31 (0x5FUL) +#define HPM_TRGM0_INPUT_SRC_RDC_TRGO_0 (0x60UL) +#define HPM_TRGM0_INPUT_SRC_RDC_TRGO_1 (0x61UL) +#define HPM_TRGM0_INPUT_SRC_QEI1_TRGO (0x62UL) +#define HPM_TRGM0_INPUT_SRC_QEI0_TRGO (0x63UL) +#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_0 (0x64UL) +#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_1 (0x65UL) +#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_2 (0x66UL) +#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_3 (0x67UL) +#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_4 (0x68UL) +#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_5 (0x69UL) +#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_6 (0x6AUL) +#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_7 (0x6BUL) +#define HPM_TRGM0_INPUT_SRC_PWM0_FAULT0 (0x6CUL) +#define HPM_TRGM0_INPUT_SRC_PWM0_FAULT1 (0x6DUL) +#define HPM_TRGM0_INPUT_SRC_PWM1_FAULT0 (0x6EUL) +#define HPM_TRGM0_INPUT_SRC_PWM1_FAULT1 (0x6FUL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN0 (0x70UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN1 (0x71UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN2 (0x72UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN3 (0x73UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN4 (0x74UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN5 (0x75UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN6 (0x76UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN7 (0x77UL) +#define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN0 (0x78UL) +#define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN1 (0x79UL) +#define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN2 (0x7AUL) +#define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN3 (0x7BUL) +#define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN4 (0x7CUL) +#define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN5 (0x7DUL) +#define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN6 (0x7EUL) +#define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN7 (0x7FUL) + +/* trgm0_output mux definitions */ +#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_0 (0x0UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_1 (0x1UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_2 (0x2UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_3 (0x3UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_4 (0x4UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_5 (0x5UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_6 (0x6UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_7 (0x7UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_0 (0x8UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_1 (0x9UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_2 (0xAUL) +#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_3 (0xBUL) +#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_4 (0xCUL) +#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_5 (0xDUL) +#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_6 (0xEUL) +#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_7 (0xFUL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN2 (0x10UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN3 (0x11UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_SYNCI (0x12UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN2 (0x13UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN3 (0x14UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR1_SYNCI (0x15UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR2_IN2 (0x16UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR2_IN3 (0x17UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR2_SYNCI (0x18UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR3_IN2 (0x19UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR3_IN3 (0x1AUL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR3_SYNCI (0x1BUL) +#define HPM_TRGM0_OUTPUT_SRC_CMP0_WIN (0x1CUL) +#define HPM_TRGM0_OUTPUT_SRC_CMP1_WIN (0x1DUL) +#define HPM_TRGM0_OUTPUT_SRC_DAC0_BUFTRG (0x1EUL) +#define HPM_TRGM0_OUTPUT_SRC_DAC1_BUFTRG (0x1FUL) +#define HPM_TRGM0_OUTPUT_SRC_ADC0_STRGI (0x20UL) +#define HPM_TRGM0_OUTPUT_SRC_ADC1_STRGI (0x21UL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A (0x22UL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0B (0x23UL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0C (0x24UL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI1A (0x25UL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI1B (0x26UL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI1C (0x27UL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI2A (0x28UL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI2B (0x29UL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI2C (0x2AUL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI3A (0x2BUL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI3B (0x2CUL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI3C (0x2DUL) +#define HPM_TRGM0_OUTPUT_SRC_MCAN_PTPC0_CAP (0x2EUL) +#define HPM_TRGM0_OUTPUT_SRC_MCAN_PTPC1_CAP (0x2FUL) +#define HPM_TRGM0_OUTPUT_SRC_QEO0_TRIG_IN0 (0x30UL) +#define HPM_TRGM0_OUTPUT_SRC_QEO0_TRIG_IN1 (0x31UL) +#define HPM_TRGM0_OUTPUT_SRC_QEO1_TRIG_IN0 (0x32UL) +#define HPM_TRGM0_OUTPUT_SRC_QEO1_TRIG_IN1 (0x33UL) +#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN0 (0x34UL) +#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN1 (0x35UL) +#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN2 (0x36UL) +#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN3 (0x37UL) +#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN4 (0x38UL) +#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN5 (0x39UL) +#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN6 (0x3AUL) +#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN7 (0x3BUL) +#define HPM_TRGM0_OUTPUT_SRC_MMC0_TRIG_IN0 (0x3CUL) +#define HPM_TRGM0_OUTPUT_SRC_MMC0_TRIG_IN1 (0x3DUL) +#define HPM_TRGM0_OUTPUT_SRC_MMC1_TRIG_IN0 (0x3EUL) +#define HPM_TRGM0_OUTPUT_SRC_MMC1_TRIG_IN1 (0x3FUL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_00 (0x40UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_01 (0x41UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_02 (0x42UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_03 (0x43UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_04 (0x44UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_05 (0x45UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_06 (0x46UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_07 (0x47UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_08 (0x48UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_09 (0x49UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_10 (0x4AUL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_11 (0x4BUL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_12 (0x4CUL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_13 (0x4DUL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_14 (0x4EUL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_15 (0x4FUL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_16 (0x50UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_17 (0x51UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_18 (0x52UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_19 (0x53UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_20 (0x54UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_21 (0x55UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_22 (0x56UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_23 (0x57UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_24 (0x58UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_25 (0x59UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_26 (0x5AUL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_27 (0x5BUL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_28 (0x5CUL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_29 (0x5DUL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_30 (0x5EUL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_31 (0x5FUL) +#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO0 (0x60UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO1 (0x61UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO2 (0x62UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO3 (0x63UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO4 (0x64UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO5 (0x65UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO6 (0x66UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO7 (0x67UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM_IN8 (0x68UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM_IN9 (0x69UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM_IN10 (0x6AUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM_IN11 (0x6BUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM_IN12 (0x6CUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM_IN13 (0x6DUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM_IN14 (0x6EUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM_IN15 (0x6FUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCI (0x70UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCSYNCI (0x71UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_SYNCI (0x72UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_SHRLDSYNCI (0x73UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI0 (0x74UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI1 (0x75UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM1_FRCI (0x76UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM1_FRCSYNCI (0x77UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM1_SYNCI (0x78UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM1_SHRLDSYNCI (0x79UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM1_FAULTI0 (0x7AUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM1_FAULTI1 (0x7BUL) +#define HPM_TRGM0_OUTPUT_SRC_RDC_TRIG_IN0 (0x7CUL) +#define HPM_TRGM0_OUTPUT_SRC_RDC_TRIG_IN1 (0x7DUL) +#define HPM_TRGM0_OUTPUT_SRC_SYNCTIMER_TRIG (0x7EUL) +#define HPM_TRGM0_OUTPUT_SRC_QEI0_TRIG_IN (0x7FUL) +#define HPM_TRGM0_OUTPUT_SRC_QEI1_TRIG_IN (0x80UL) +#define HPM_TRGM0_OUTPUT_SRC_QEI0_PAUSE (0x81UL) +#define HPM_TRGM0_OUTPUT_SRC_QEI1_PAUSE (0x82UL) +#define HPM_TRGM0_OUTPUT_SRC_UART_TRIG0 (0x83UL) +#define HPM_TRGM0_OUTPUT_SRC_UART_TRIG1 (0x84UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM_IRQ0 (0x85UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM_IRQ1 (0x86UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM_DMA0 (0x87UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM_DMA1 (0x88UL) + +/* trgm0_filter mux definitions */ +#define HPM_TRGM0_FILTER_SRC_PWM0_IN0 (0x0UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN1 (0x1UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN2 (0x2UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN3 (0x3UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN4 (0x4UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN5 (0x5UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN6 (0x6UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN7 (0x7UL) +#define HPM_TRGM0_FILTER_SRC_PWM1_IN0 (0x8UL) +#define HPM_TRGM0_FILTER_SRC_PWM1_IN1 (0x9UL) +#define HPM_TRGM0_FILTER_SRC_PWM1_IN2 (0xAUL) +#define HPM_TRGM0_FILTER_SRC_PWM1_IN3 (0xBUL) +#define HPM_TRGM0_FILTER_SRC_PWM1_IN4 (0xCUL) +#define HPM_TRGM0_FILTER_SRC_PWM1_IN5 (0xDUL) +#define HPM_TRGM0_FILTER_SRC_PWM1_IN6 (0xEUL) +#define HPM_TRGM0_FILTER_SRC_PWM1_IN7 (0xFUL) +#define HPM_TRGM0_FILTER_SRC_TRGM_IN0 (0x10UL) +#define HPM_TRGM0_FILTER_SRC_TRGM_IN1 (0x11UL) +#define HPM_TRGM0_FILTER_SRC_TRGM_IN2 (0x12UL) +#define HPM_TRGM0_FILTER_SRC_TRGM_IN3 (0x13UL) +#define HPM_TRGM0_FILTER_SRC_TRGM_IN4 (0x14UL) +#define HPM_TRGM0_FILTER_SRC_TRGM_IN5 (0x15UL) +#define HPM_TRGM0_FILTER_SRC_TRGM_IN6 (0x16UL) +#define HPM_TRGM0_FILTER_SRC_TRGM_IN7 (0x17UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_FAULT0 (0x18UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_FAULT1 (0x19UL) +#define HPM_TRGM0_FILTER_SRC_PWM1_FAULT0 (0x1AUL) +#define HPM_TRGM0_FILTER_SRC_PWM1_FAULT1 (0x1BUL) + +/* trgm0_dma mux definitions */ +#define HPM_TRGM0_DMA_SRC_PWM0_CMP0 (0x0UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP1 (0x1UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP2 (0x2UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP3 (0x3UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP4 (0x4UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP5 (0x5UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP6 (0x6UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP7 (0x7UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP8 (0x8UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP9 (0x9UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP10 (0xAUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP11 (0xBUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP12 (0xCUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP13 (0xDUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP14 (0xEUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP15 (0xFUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP16 (0x10UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP17 (0x11UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP18 (0x12UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP19 (0x13UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP20 (0x14UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP21 (0x15UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP22 (0x16UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP23 (0x17UL) +#define HPM_TRGM0_DMA_SRC_PWM0_RLD (0x18UL) +#define HPM_TRGM0_DMA_SRC_PWM0_HALFRLD (0x19UL) +#define HPM_TRGM0_DMA_SRC_PWM0_XRLD (0x1AUL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP0 (0x1BUL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP1 (0x1CUL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP2 (0x1DUL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP3 (0x1EUL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP4 (0x1FUL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP5 (0x20UL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP6 (0x21UL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP7 (0x22UL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP8 (0x23UL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP9 (0x24UL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP10 (0x25UL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP11 (0x26UL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP12 (0x27UL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP13 (0x28UL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP14 (0x29UL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP15 (0x2AUL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP16 (0x2BUL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP17 (0x2CUL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP18 (0x2DUL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP19 (0x2EUL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP20 (0x2FUL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP21 (0x30UL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP22 (0x31UL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP23 (0x32UL) +#define HPM_TRGM0_DMA_SRC_PWM1_RLD (0x33UL) +#define HPM_TRGM0_DMA_SRC_PWM1_HALFRLD (0x34UL) +#define HPM_TRGM0_DMA_SRC_PWM1_XRLD (0x35UL) +#define HPM_TRGM0_DMA_SRC_QEI0 (0x36UL) +#define HPM_TRGM0_DMA_SRC_QEI1 (0x37UL) +#define HPM_TRGM0_DMA_SRC_MMC0 (0x38UL) +#define HPM_TRGM0_DMA_SRC_MMC1 (0x39UL) +#define HPM_TRGM0_DMA_SRC_SEI0 (0x3AUL) +#define HPM_TRGM0_DMA_SRC_SEI1 (0x3BUL) +#define HPM_TRGM0_DMA_SRC_TRGM0 (0x3CUL) +#define HPM_TRGM0_DMA_SRC_TRGM1 (0x3DUL) + + + +#endif /* HPM_TRGMMUX_SRC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/soc_modules.list b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/soc_modules.list new file mode 100644 index 00000000000..6370a0e6bbb --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/soc_modules.list @@ -0,0 +1,52 @@ +# +# Copyright (c) 2024 HPMicro +# +# SPDX-License-Identifier: BSD-3-Clause +# + +HPMSOC_HAS_HPMSDK_GPIO=y +HPMSOC_HAS_HPMSDK_PLIC=y +HPMSOC_HAS_HPMSDK_MCHTMR=y +HPMSOC_HAS_HPMSDK_PLICSW=y +HPMSOC_HAS_HPMSDK_GPTMR=y +HPMSOC_HAS_HPMSDK_UART=y +HPMSOC_HAS_HPMSDK_I2C=y +HPMSOC_HAS_HPMSDK_SPI=y +HPMSOC_HAS_HPMSDK_CRC=y +HPMSOC_HAS_HPMSDK_TSNS=y +HPMSOC_HAS_HPMSDK_MBX=y +HPMSOC_HAS_HPMSDK_EWDG=y +HPMSOC_HAS_HPMSDK_DMAMUX=y +HPMSOC_HAS_HPMSDK_DMAV2=y +HPMSOC_HAS_HPMSDK_GPIOM=y +HPMSOC_HAS_HPMSDK_MCAN=y +HPMSOC_HAS_HPMSDK_PTPC=y +HPMSOC_HAS_HPMSDK_QEIV2=y +HPMSOC_HAS_HPMSDK_QEO=y +HPMSOC_HAS_HPMSDK_MMC=y +HPMSOC_HAS_HPMSDK_PWM=y +HPMSOC_HAS_HPMSDK_RDC=y +HPMSOC_HAS_HPMSDK_PLB=y +HPMSOC_HAS_HPMSDK_SYNT=y +HPMSOC_HAS_HPMSDK_SEI=y +HPMSOC_HAS_HPMSDK_TRGM=y +HPMSOC_HAS_HPMSDK_USB=y +HPMSOC_HAS_HPMSDK_SDP=y +HPMSOC_HAS_HPMSDK_SEC=y +HPMSOC_HAS_HPMSDK_MON=y +HPMSOC_HAS_HPMSDK_RNG=y +HPMSOC_HAS_HPMSDK_OTP=y +HPMSOC_HAS_HPMSDK_KEYM=y +HPMSOC_HAS_HPMSDK_ADC16=y +HPMSOC_HAS_HPMSDK_DAC=y +HPMSOC_HAS_HPMSDK_OPAMP=y +HPMSOC_HAS_HPMSDK_ACMP=y +HPMSOC_HAS_HPMSDK_SYSCTL=y +HPMSOC_HAS_HPMSDK_IOC=y +HPMSOC_HAS_HPMSDK_PLLCTLV2=y +HPMSOC_HAS_HPMSDK_PPOR=y +HPMSOC_HAS_HPMSDK_PCFG=y +HPMSOC_HAS_HPMSDK_PGPR=y +HPMSOC_HAS_HPMSDK_PDGO=y +HPMSOC_HAS_HPMSDK_PMP=y + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/system.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/system.c new file mode 100644 index 00000000000..a0fb6800e94 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/system.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" + +#ifndef CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP +#define CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP 0 +#endif + +void enable_plic_feature(void) +{ + uint32_t plic_feature = 0; +#ifndef USE_NONVECTOR_MODE + /* enabled vector mode and preemptive priority interrupt */ + plic_feature |= HPM_PLIC_FEATURE_VECTORED_MODE; +#endif +#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) + /* enabled preemptive priority interrupt */ + plic_feature |= HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ; +#endif + __plic_set_feature(HPM_PLIC_BASE, plic_feature); +} + +__attribute__((weak)) void system_init(void) +{ +#ifndef CONFIG_NOT_ENALBE_ACCESS_TO_CYCLE_CSR + uint32_t mcounteren = read_csr(CSR_MCOUNTEREN); + write_csr(CSR_MCOUNTEREN, mcounteren | 1); /* Enable MCYCLE */ +#endif + +#ifdef USE_S_MODE_IRQ + disable_global_irq(CSR_MSTATUS_MIE_MASK | CSR_MSTATUS_SIE_MASK); +#else + disable_global_irq(CSR_MSTATUS_MIE_MASK); +#endif + + disable_irq_from_intc(); +#ifdef USE_S_MODE_IRQ + disable_s_irq_from_intc(); +#endif + + enable_plic_feature(); + enable_irq_from_intc(); + +#ifdef USE_S_MODE_IRQ + delegate_irq(CSR_MIDELEG_SEI_MASK | CSR_MIDELEG_SSI_MASK | CSR_MIDELEG_STI_MASK); + enable_s_irq_from_intc(); +#if !CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP + enable_global_irq(CSR_MSTATUS_MIE_MASK | CSR_MSTATUS_SIE_MASK); +#endif +#else +#if !CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP + enable_global_irq(CSR_MSTATUS_MIE_MASK); +#endif +#endif +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/flash.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/flash.ld new file mode 100644 index 00000000000..a162a7430b9 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/flash.ld @@ -0,0 +1,250 @@ +/* + * Copyright (c) 2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = _stack_size; +HEAP_SIZE = _heap_size; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80003000, LENGTH = _flash_size - 0x3000 + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K + AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + KEEP(*(.vector_s_table)) + KEEP(*(.isr_s_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + /* RT-Thread related sections - Start */ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + . = ALIGN(8); + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + *(.fast.*) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > ILM + + .bss (NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > DLM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > DLM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > DLM + + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > DLM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > DLM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/flash_uf2.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/flash_uf2.ld new file mode 100644 index 00000000000..872b399c2e5 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/flash_uf2.ld @@ -0,0 +1,251 @@ +/* + * Copyright (c) 2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = _stack_size; +HEAP_SIZE = _heap_size; +UF2_BOOTLOADER_RESERVED_LENGTH = DEFINED(_uf2_bl_length) ? _uf2_bl_length : 0x20000; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH, LENGTH = _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K + AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k +} + +SECTIONS +{ + .start : { + KEEP(*(.uf2_signature)) + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + KEEP(*(.vector_s_table)) + KEEP(*(.isr_s_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)): { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + /* RT-Thread related sections - Start */ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + . = ALIGN(8); + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + *(.fast.*) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > ILM + + .bss (NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > DLM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > DLM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > DLM + + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > DLM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > DLM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/flash_xip.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/flash_xip.ld new file mode 100644 index 00000000000..22e8126d342 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/flash_xip.ld @@ -0,0 +1,271 @@ +/* + * Copyright (c) 2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = _stack_size; +HEAP_SIZE = _heap_size; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = _flash_size + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K + AHB_SRAM (w) : ORIGIN = 0xf0400000, LENGTH = 32K +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + KEEP(*(.vector_s_table)) + KEEP(*(.isr_s_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + /* RT-Thread related sections - Start */ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + . = ALIGN(8); + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + *(.tdata) + *(.tdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + *(.fast.*) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > ILM + + .bss (NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > DLM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > DLM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > DLM + + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > DLM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > DLM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/initfini.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/initfini.c new file mode 100644 index 00000000000..7d2b85799c8 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/initfini.c @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2021-2022 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#ifndef USE_LIBC_INITFINI +#define USE_LIBC_INITFINI 0 +#endif + +#if USE_LIBC_INITFINI + +/* + * The _init() and _fini() will be called respectively when use __libc_init_array() + * and __libc_fnit_array() in libc.a to perform constructor and destructor handling. + * The dummy versions of these functions should be provided. + */ +void _init(void) +{ +} + +void _fini(void) +{ +} + +#else + +/* These magic symbols are provided by the linker. */ +extern void (*__preinit_array_start[])(void) __attribute__((weak)); +extern void (*__preinit_array_end[])(void) __attribute__((weak)); +extern void (*__init_array_start[])(void) __attribute__((weak)); +extern void (*__init_array_end[])(void) __attribute__((weak)); + +/* + * The __libc_init_array()/__libc_fnit_array() function is used to do global + * constructor/destructor and can NOT be compilied to generate the code coverage + * data. We have the function attribute to be 'no_profile_instrument_function' + * to prevent been instrumented for coverage analysis when GCOV=1 is applied. + */ +/* Iterate over all the init routines. */ +void __libc_init_array(void) __attribute__((no_profile_instrument_function)); +void __libc_init_array(void) +{ + uint32_t count; + uint32_t i; + + count = __preinit_array_end - __preinit_array_start; + for (i = 0; i < count; i++) { + __preinit_array_start[i](); + } + + count = __init_array_end - __init_array_start; + for (i = 0; i < count; i++) { + __init_array_start[i](); + } +} + +extern void (*__fini_array_start[])(void) __attribute__((weak)); +extern void (*__fini_array_end[])(void) __attribute__((weak)); + +/* Run all the cleanup routines. */ +void __libc_fini_array(void) __attribute__((no_profile_instrument_function)); +void __libc_fini_array(void) +{ + uint32_t count; + uint32_t i; + + count = __fini_array_end - __fini_array_start; + for (i = count; i > 0; i--) { + __fini_array_start[i - 1](); + } +} + +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/ram.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/ram.ld new file mode 100644 index 00000000000..7fa7529685d --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/ram.ld @@ -0,0 +1,247 @@ +/* + * Copyright (c) 2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = _stack_size; +HEAP_SIZE = _heap_size; + +MEMORY +{ + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K + AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > ILM + + .vectors : { + . = ALIGN(8); + KEEP(*(.isr_vector)) + KEEP(*(.vector_table)) + KEEP(*(.isr_s_vector)) + KEEP(*(.vector_s_table)) + . = ALIGN(8); + } > ILM + + .rel : { + KEEP(*(.rel*)) + } > ILM + + .text : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + /* RT-Thread related sections - Start */ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + . = ALIGN(8); + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + } > ILM + + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + *(.fast.*) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > ILM + + .bss (NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > DLM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > DLM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > DLM + + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > DLM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > DLM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + __last_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); + ASSERT(((__fw_size__ <= LENGTH(ILM)) && (__last_addr__ <= (ORIGIN(ILM) + LENGTH(ILM)))), "****** FAILED! ILM has not enough space! ******") +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/start.S b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/start.S new file mode 100644 index 00000000000..a13b7d98415 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/start.S @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2021-2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_csr_regs.h" + + .section .start, "ax" + + .global _start + .type _start,@function + +_start: + /* Initialize global pointer */ + .option push + .option norelax + la gp, __global_pointer$ + la tp, __thread_pointer$ + .option pop + + /* reset mstatus to 0*/ + csrrw x0, mstatus, x0 + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + +#ifdef INIT_EXT_RAM_FOR_DATA + la t0, _stack_safe + mv sp, t0 + call _init_ext_ram +#endif + + /* Initialize stack pointer */ + la t0, _stack + mv sp, t0 + +#ifdef CONFIG_NOT_ENABLE_ICACHE + call l1c_ic_disable +#else + call l1c_ic_enable +#endif +#ifdef CONFIG_NOT_ENABLE_DCACHE + call l1c_dc_invalidate_all + call l1c_dc_disable +#else + call l1c_dc_enable + call l1c_dc_invalidate_all +#endif + + /* + * Initialize LMA/VMA sections. + * Relocation for any sections that need to be copied from LMA to VMA. + */ + call c_startup + +#if defined(__SES_RISCV) + /* Initialize the heap */ + la a0, __heap_start__ + la a1, __heap_end__ + sub a1, a1, a0 + la t1, __SEGGER_RTL_init_heap + jalr t1 +#endif + + /* Do global constructors */ + call __libc_init_array + +#ifndef NO_CLEANUP_AT_START + /* clean up */ + call _clean_up +#endif + +#ifdef __nds_execit + /* Initialize EXEC.IT table */ + la t0, _ITB_BASE_ + csrw uitb, t0 +#endif + +#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS + #define HANDLER_TRAP freertos_risc_v_trap_handler + #define HANDLER_S_TRAP freertos_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 +#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III + #define HANDLER_TRAP ucos_risc_v_trap_handler + #define HANDLER_S_TRAP ucos_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 +#elif defined(CONFIG_THREADX) && CONFIG_THREADX + #define HANDLER_TRAP tx_risc_v_trap_handler + #define HANDLER_S_TRAP tx_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 + +#elif defined(CONFIG_RTTHREAD) && CONFIG_RTTHREAD + #define HANDLER_TRAP rtt_risc_v_trap_handler + #define HANDLER_S_TRAP rtt_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 + +#else + #define HANDLER_TRAP irq_handler_trap + #define HANDLER_S_TRAP irq_handler_s_trap +#endif + +#ifndef USE_NONVECTOR_MODE + /* Initial machine trap-vector Base */ + la t0, __vector_table + csrw mtvec, t0 + +#if defined (USE_S_MODE_IRQ) + la t0, __vector_s_table + csrw stvec, t0 +#endif + /* Enable vectored external PLIC interrupt */ + csrsi CSR_MMISC_CTL, 2 +#else + /* Initial machine trap-vector Base */ + la t0, HANDLER_TRAP + csrw mtvec, t0 +#if defined (USE_S_MODE_IRQ) + la t0, HANDLER_S_TRAP + csrw stvec, t0 +#endif + + /* Disable vectored external PLIC interrupt */ + csrci CSR_MMISC_CTL, 2 +#endif + + /* System reset handler */ + call reset_handler + + /* Infinite loop, if returned accidentally */ +1: j 1b + + .weak exit +exit: +1: j 1b + + .section .isr_vector, "ax" + .weak nmi_handler +nmi_handler: +1: j 1b + +#include "../vectors.h" diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/reset.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/reset.c new file mode 100644 index 00000000000..8301c2ec2cf --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/reset.c @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2022-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" +#include "hpm_interrupt.h" + + +extern void system_init(void); + +#ifndef MAIN_ENTRY +#define MAIN_ENTRY main +#endif +extern int MAIN_ENTRY(void); + +__attribute__((weak)) void _clean_up(void) +{ + /* clean up plic, it will help while debugging */ + disable_irq_from_intc(); + intc_m_set_threshold(0); + for (uint32_t irq = 0; irq < 128; irq++) { + intc_m_complete_irq(irq); + } + /* clear any bits left in plic enable register */ + for (uint32_t i = 0; i < 4; i++) { + *(volatile uint32_t *)(HPM_PLIC_BASE + HPM_PLIC_ENABLE_OFFSET + (i << 2)) = 0; + } +} + +__attribute__((weak)) void c_startup(void) +{ + uint32_t i, size; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __tdata_start__[], __tdata_end__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + extern uint8_t __data_load_addr__[], __tdata_load_addr__[]; + extern uint8_t __fast_load_addr__[], __noncacheable_init_load_addr__[]; + +#if defined(FLASH_XIP) || defined(FLASH_UF2) + extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; + size = __vector_ram_end__ - __vector_ram_start__; + for (i = 0; i < size; i++) { + *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); + } +#endif + + /* bss section */ + size = __bss_end__ - __bss_start__; + for (i = 0; i < size; i++) { + *(__bss_start__ + i) = 0; + } + + /* noncacheable bss section */ + size = __noncacheable_bss_end__ - __noncacheable_bss_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_bss_start__ + i) = 0; + } + + /* data section LMA: etext */ + size = __data_end__ - __data_start__; + for (i = 0; i < size; i++) { + *(__data_start__ + i) = *(__data_load_addr__ + i); + } + + /* ramfunc section LMA: etext + data length */ + size = __ramfunc_end__ - __ramfunc_start__; + for (i = 0; i < size; i++) { + *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i); + } + + /* tdata section LMA: etext + data length + ramfunc length */ + size = __tdata_end__ - __tdata_start__; + for (i = 0; i < size; i++) { + *(__tdata_start__ + i) = *(__tdata_load_addr__ + i); + } + + /* noncacheable init section LMA: etext + data length + ramfunc legnth + tdata length*/ + size = __noncacheable_init_end__ - __noncacheable_init_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); + } +} + +__attribute__((weak)) int main(void) +{ + while (1) { + ; + } +} + +__attribute__((weak)) void reset_handler(void) +{ + fencei(); + + /* Call platform specific hardware initialization */ + system_init(); + + /* Entry function */ + MAIN_ENTRY(); +} + +/* + * When compiling C++ code with static objects, the compiler inserts + * a call to __cxa_atexit() with __dso_handle as one of the arguments. + * The dummy versions of these symbols should be provided. + */ +__attribute__((weak)) void __cxa_atexit(void (*arg1)(void *), void *arg2, void *arg3) +{ + (void) arg1; + (void) arg2; + (void) arg3; +} + +#if (!defined(__SEGGER_RTL_VERSION) || defined(__riscv_xandes)) && !defined(__ICCRISCV__) +void *__dso_handle = (void *) &__dso_handle; +#endif + +__attribute__((weak)) void _init(void) +{ +} + + +#ifdef __ICCRISCV__ +int __low_level_init(void) +{ +#ifdef IAR_MANUAL_COPY /* Enable this code snippet if the .isr_vector and .vector_table need to be copied to RAM manually */ +#pragma section = ".isr_vector" +#pragma section = ".isr_vector_init" +#pragma section = ".vector_table" +#pragma section = ".vector_table_init" + /* Initialize section .isr_vector, section .vector_table */ + uint8_t *__isr_vector_ram_start = __section_begin(".isr_vector"); + uint32_t __isr_vector_ram_size = __section_size(".isr_vector"); + uint8_t *__isr_vector_rom_start = __section_begin(".isr_vector_init"); + + for (uint32_t i = 0; i < __isr_vector_ram_size; i++) { + __isr_vector_ram_start[i] = __isr_vector_rom_start[i]; + } + + uint8_t *__vector_table_ram_start = __section_begin(".vector_table"); + uint32_t __vector_table_ram_size = __section_size(".vector_table"); + uint8_t *__vector_rom_start = __section_begin(".vector_table_init"); + + for (uint32_t i = 0; i < __vector_table_ram_size; i++) { + __vector_table_ram_start[i] = __vector_rom_start[i]; + } +#endif + + return 1; +} +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/trap.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/trap.c new file mode 100644 index 00000000000..66e5dd580f9 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/trap.c @@ -0,0 +1,191 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_soc.h" + +#ifdef __ICCRISCV__ +#pragma language = extended +#endif + +/********************** MCAUSE exception types **************************************/ +#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) /* !< Instruction Address misaligned */ +#define MCAUSE_INSTR_ACCESS_FAULT (1U) /* !< Instruction access fault */ +#define MCAUSE_ILLEGAL_INSTR (2U) /* !< Illegal instruction */ +#define MCAUSE_BREAKPOINT (3U) /* !< Breakpoint */ +#define MCAUSE_LOAD_ADDR_MISALIGNED (4U) /* !< Load address misaligned */ +#define MCAUSE_LOAD_ACCESS_FAULT (5U) /* !< Load access fault */ +#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U) /* !< Store/AMO address misaligned */ +#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U) /* !< Store/AMO access fault */ +#define MCAUSE_ECALL_FROM_USER_MODE (8U) /* !< Environment call from User mode */ +#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U) /* !< Environment call from Supervisor mode */ +#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U) /* !< Environment call from machine mode */ +#define MCAUSE_INSTR_PAGE_FAULT (12U) /* !< Instruction page fault */ +#define MCAUSE_LOAD_PAGE_FAULT (13) /* !< Load page fault */ +#define MCAUSE_STORE_AMO_PAGE_FAULT (15U) /* !< Store/AMO page fault */ + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +__attribute__((weak)) void mchtmr_isr(void) +{ +} + +__attribute__((weak)) void swi_isr(void) +{ +} + +__attribute__((weak)) void syscall_handler(long n, long a0, long a1, long a2, long a3) +{ + (void) n; + (void) a0; + (void) a1; + (void) a2; + (void) a3; +} + +__attribute__((weak)) long exception_handler(long cause, long epc) +{ + switch (cause) { + case MCAUSE_INSTR_ADDR_MISALIGNED: + break; + case MCAUSE_INSTR_ACCESS_FAULT: + break; + case MCAUSE_ILLEGAL_INSTR: + break; + case MCAUSE_BREAKPOINT: + break; + case MCAUSE_LOAD_ADDR_MISALIGNED: + break; + case MCAUSE_LOAD_ACCESS_FAULT: + break; + case MCAUSE_STORE_AMO_ADDR_MISALIGNED: + break; + case MCAUSE_STORE_AMO_ACCESS_FAULT: + break; + case MCAUSE_ECALL_FROM_USER_MODE: + break; + case MCAUSE_ECALL_FROM_SUPERVISOR_MODE: + break; + case MCAUSE_ECALL_FROM_MACHINE_MODE: + break; + case MCAUSE_INSTR_PAGE_FAULT: + break; + case MCAUSE_LOAD_PAGE_FAULT: + break; + case MCAUSE_STORE_AMO_PAGE_FAULT: + break; + default: + break; + } + /* Unhandled Trap */ + return epc; +} + +#if !defined(CONFIG_FREERTOS) && !defined(CONFIG_UCOS_III) && !defined(CONFIG_THREADX) && !defined(CONFIG_RTTHREAD) +HPM_ATTR_MACHINE_INTERRUPT void irq_handler_trap(void); +#define IRQ_HANDLER_TRAP_AS_ISR 1 +#else +void irq_handler_trap(void) __attribute__ ((section(".isr_vector"))); +#endif + +#if defined(__ICCRISCV__) && (IRQ_HANDLER_TRAP_AS_ISR == 1) +extern int __vector_table[]; +HPM_ATTR_MACHINE_INTERRUPT +#endif +void irq_handler_trap(void) +{ + long mcause = read_csr(CSR_MCAUSE); + long mepc = read_csr(CSR_MEPC); + long mstatus = read_csr(CSR_MSTATUS); +#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH + long mxstatus = read_csr(CSR_MXSTATUS); +#endif +#ifdef __riscv_dsp + int ucode = read_csr(CSR_UCODE); +#endif +#ifdef __riscv_flen + int fcsr = read_fcsr(); +#endif + + /* clobbers list for ecall */ +#ifdef __riscv_32e + __asm volatile("" : : : "t0", "a0", "a1", "a2", "a3"); +#else + __asm volatile("" : : : "a7", "a0", "a1", "a2", "a3"); +#endif + + /* Do your trap handling */ + if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_TIMER)) { + /* Machine timer interrupt */ + mchtmr_isr(); + } +#ifdef USE_NONVECTOR_MODE + else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_EXT)) { + + typedef void(*isr_func_t)(void); + + /* Machine-level interrupt from PLIC */ + uint32_t irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); + if (irq_index) { + /* Workaround: irq number returned by __plic_claim_irq might be 0, which is caused by plic. So skip invalid irq_index as a workaround */ +#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) + enable_global_irq(CSR_MSTATUS_MIE_MASK); +#endif + ((isr_func_t)__vector_table[irq_index])(); + __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index); + } + } +#endif + + else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_SOFT)) { + /* Machine SWI interrupt */ + intc_m_claim_swi(); + swi_isr(); + intc_m_complete_swi(); + } else if (!(mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == MCAUSE_ECALL_FROM_MACHINE_MODE)) { + /* Machine Syscal call */ + __asm volatile( + "mv a4, a3\n" + "mv a3, a2\n" + "mv a2, a1\n" + "mv a1, a0\n" + #ifdef __riscv_32e + "mv a0, t0\n" + #else + "mv a0, a7\n" + #endif + "jalr %0\n" + : : "r"(syscall_handler) : "a4" + ); + mepc += 4; + } else { + mepc = exception_handler(mcause, mepc); + } + + /* Restore CSR */ + write_csr(CSR_MSTATUS, mstatus); + write_csr(CSR_MEPC, mepc); +#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH + write_csr(CSR_MXSTATUS, mxstatus); +#endif +#ifdef __riscv_dsp + write_csr(CSR_UCODE, ucode); +#endif +#ifdef __riscv_flen + write_fcsr(fcsr); +#endif +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/vectors.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/vectors.h new file mode 100644 index 00000000000..f140c369474 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/vectors.h @@ -0,0 +1,271 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifdef __IAR_SYSTEMS_ASM__ + +IRQ_HANDLER macro + dc32 default_isr_\1 + endm + +IRQ_DEFAULT_HANDLER macro + PUBWEAK default_isr_\1 +default_isr_\1 + j default_irq_handler + endm + + SECTION `.isr_vector`:CODE:ROOT(9) + PUBWEAK default_irq_handler +default_irq_handler + j default_irq_handler + IRQ_DEFAULT_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_DEFAULT_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_DEFAULT_HANDLER 3 /* GPIO0_X IRQ handler */ + IRQ_DEFAULT_HANDLER 4 /* GPIO0_Y IRQ handler */ + IRQ_DEFAULT_HANDLER 5 /* GPTMR0 IRQ handler */ + IRQ_DEFAULT_HANDLER 6 /* GPTMR1 IRQ handler */ + IRQ_DEFAULT_HANDLER 7 /* GPTMR2 IRQ handler */ + IRQ_DEFAULT_HANDLER 8 /* GPTMR3 IRQ handler */ + IRQ_DEFAULT_HANDLER 9 /* Reserved */ + IRQ_DEFAULT_HANDLER 10 /* Reserved */ + IRQ_DEFAULT_HANDLER 11 /* Reserved */ + IRQ_DEFAULT_HANDLER 12 /* Reserved */ + IRQ_DEFAULT_HANDLER 13 /* UART0 IRQ handler */ + IRQ_DEFAULT_HANDLER 14 /* UART1 IRQ handler */ + IRQ_DEFAULT_HANDLER 15 /* UART2 IRQ handler */ + IRQ_DEFAULT_HANDLER 16 /* UART3 IRQ handler */ + IRQ_DEFAULT_HANDLER 17 /* UART4 IRQ handler */ + IRQ_DEFAULT_HANDLER 18 /* UART5 IRQ handler */ + IRQ_DEFAULT_HANDLER 19 /* UART6 IRQ handler */ + IRQ_DEFAULT_HANDLER 20 /* UART7 IRQ handler */ + IRQ_DEFAULT_HANDLER 21 /* I2C0 IRQ handler */ + IRQ_DEFAULT_HANDLER 22 /* I2C1 IRQ handler */ + IRQ_DEFAULT_HANDLER 23 /* I2C2 IRQ handler */ + IRQ_DEFAULT_HANDLER 24 /* I2C3 IRQ handler */ + IRQ_DEFAULT_HANDLER 25 /* SPI0 IRQ handler */ + IRQ_DEFAULT_HANDLER 26 /* SPI1 IRQ handler */ + IRQ_DEFAULT_HANDLER 27 /* SPI2 IRQ handler */ + IRQ_DEFAULT_HANDLER 28 /* SPI3 IRQ handler */ + IRQ_DEFAULT_HANDLER 29 /* TSNS IRQ handler */ + IRQ_DEFAULT_HANDLER 30 /* MBX0A IRQ handler */ + IRQ_DEFAULT_HANDLER 31 /* MBX0B IRQ handler */ + IRQ_DEFAULT_HANDLER 32 /* EWDG0 IRQ handler */ + IRQ_DEFAULT_HANDLER 33 /* EWDG1 IRQ handler */ + IRQ_DEFAULT_HANDLER 34 /* HDMA IRQ handler */ + IRQ_DEFAULT_HANDLER 35 /* MCAN0 IRQ handler */ + IRQ_DEFAULT_HANDLER 36 /* MCAN1 IRQ handler */ + IRQ_DEFAULT_HANDLER 37 /* MCAN2 IRQ handler */ + IRQ_DEFAULT_HANDLER 38 /* MCAN3 IRQ handler */ + IRQ_DEFAULT_HANDLER 39 /* PTPC IRQ handler */ + IRQ_DEFAULT_HANDLER 40 /* PWM0 IRQ handler */ + IRQ_DEFAULT_HANDLER 41 /* QEI0 IRQ handler */ + IRQ_DEFAULT_HANDLER 42 /* SEI0 IRQ handler */ + IRQ_DEFAULT_HANDLER 43 /* MMC0 IRQ handler */ + IRQ_DEFAULT_HANDLER 44 /* TRGMUX0 IRQ handler */ + IRQ_DEFAULT_HANDLER 45 /* PWM1 IRQ handler */ + IRQ_DEFAULT_HANDLER 46 /* QEI1 IRQ handler */ + IRQ_DEFAULT_HANDLER 47 /* SEI1 IRQ handler */ + IRQ_DEFAULT_HANDLER 48 /* MMC1 IRQ handler */ + IRQ_DEFAULT_HANDLER 49 /* TRGMUX1 IRQ handler */ + IRQ_DEFAULT_HANDLER 50 /* RDC IRQ handler */ + IRQ_DEFAULT_HANDLER 51 /* USB0 IRQ handler */ + IRQ_DEFAULT_HANDLER 52 /* XPI0 IRQ handler */ + IRQ_DEFAULT_HANDLER 53 /* SDP IRQ handler */ + IRQ_DEFAULT_HANDLER 54 /* PSEC IRQ handler */ + IRQ_DEFAULT_HANDLER 55 /* SECMON IRQ handler */ + IRQ_DEFAULT_HANDLER 56 /* RNG IRQ handler */ + IRQ_DEFAULT_HANDLER 57 /* FUSE IRQ handler */ + IRQ_DEFAULT_HANDLER 58 /* ADC0 IRQ handler */ + IRQ_DEFAULT_HANDLER 59 /* ADC1 IRQ handler */ + IRQ_DEFAULT_HANDLER 60 /* DAC0 IRQ handler */ + IRQ_DEFAULT_HANDLER 61 /* DAC1 IRQ handler */ + IRQ_DEFAULT_HANDLER 62 /* ACMP_0 IRQ handler */ + IRQ_DEFAULT_HANDLER 63 /* ACMP_1 IRQ handler */ + IRQ_DEFAULT_HANDLER 64 /* SYSCTL IRQ handler */ + IRQ_DEFAULT_HANDLER 65 /* PGPIO IRQ handler */ + IRQ_DEFAULT_HANDLER 66 /* PTMR IRQ handler */ + IRQ_DEFAULT_HANDLER 67 /* PUART IRQ handler */ + IRQ_DEFAULT_HANDLER 68 /* PEWDG IRQ handler */ + IRQ_DEFAULT_HANDLER 69 /* BROWNOUT IRQ handler */ + IRQ_DEFAULT_HANDLER 70 /* PAD_WAKEUP IRQ handler */ + IRQ_DEFAULT_HANDLER 71 /* DEBUG0 IRQ handler */ + IRQ_DEFAULT_HANDLER 72 /* DEBUG1 IRQ handler */ + + EXTERN irq_handler_trap + SECTION `.vector_table`:CODE:ROOT(9) + PUBLIC __vector_table + DATA + +__vector_table + dc32 irq_handler_trap + IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_HANDLER 3 /* GPIO0_X IRQ handler */ + IRQ_HANDLER 4 /* GPIO0_Y IRQ handler */ + IRQ_HANDLER 5 /* GPTMR0 IRQ handler */ + IRQ_HANDLER 6 /* GPTMR1 IRQ handler */ + IRQ_HANDLER 7 /* GPTMR2 IRQ handler */ + IRQ_HANDLER 8 /* GPTMR3 IRQ handler */ + IRQ_HANDLER 9 /* Reserved */ + IRQ_HANDLER 10 /* Reserved */ + IRQ_HANDLER 11 /* Reserved */ + IRQ_HANDLER 12 /* Reserved */ + IRQ_HANDLER 13 /* UART0 IRQ handler */ + IRQ_HANDLER 14 /* UART1 IRQ handler */ + IRQ_HANDLER 15 /* UART2 IRQ handler */ + IRQ_HANDLER 16 /* UART3 IRQ handler */ + IRQ_HANDLER 17 /* UART4 IRQ handler */ + IRQ_HANDLER 18 /* UART5 IRQ handler */ + IRQ_HANDLER 19 /* UART6 IRQ handler */ + IRQ_HANDLER 20 /* UART7 IRQ handler */ + IRQ_HANDLER 21 /* I2C0 IRQ handler */ + IRQ_HANDLER 22 /* I2C1 IRQ handler */ + IRQ_HANDLER 23 /* I2C2 IRQ handler */ + IRQ_HANDLER 24 /* I2C3 IRQ handler */ + IRQ_HANDLER 25 /* SPI0 IRQ handler */ + IRQ_HANDLER 26 /* SPI1 IRQ handler */ + IRQ_HANDLER 27 /* SPI2 IRQ handler */ + IRQ_HANDLER 28 /* SPI3 IRQ handler */ + IRQ_HANDLER 29 /* TSNS IRQ handler */ + IRQ_HANDLER 30 /* MBX0A IRQ handler */ + IRQ_HANDLER 31 /* MBX0B IRQ handler */ + IRQ_HANDLER 32 /* EWDG0 IRQ handler */ + IRQ_HANDLER 33 /* EWDG1 IRQ handler */ + IRQ_HANDLER 34 /* HDMA IRQ handler */ + IRQ_HANDLER 35 /* MCAN0 IRQ handler */ + IRQ_HANDLER 36 /* MCAN1 IRQ handler */ + IRQ_HANDLER 37 /* MCAN2 IRQ handler */ + IRQ_HANDLER 38 /* MCAN3 IRQ handler */ + IRQ_HANDLER 39 /* PTPC IRQ handler */ + IRQ_HANDLER 40 /* PWM0 IRQ handler */ + IRQ_HANDLER 41 /* QEI0 IRQ handler */ + IRQ_HANDLER 42 /* SEI0 IRQ handler */ + IRQ_HANDLER 43 /* MMC0 IRQ handler */ + IRQ_HANDLER 44 /* TRGMUX0 IRQ handler */ + IRQ_HANDLER 45 /* PWM1 IRQ handler */ + IRQ_HANDLER 46 /* QEI1 IRQ handler */ + IRQ_HANDLER 47 /* SEI1 IRQ handler */ + IRQ_HANDLER 48 /* MMC1 IRQ handler */ + IRQ_HANDLER 49 /* TRGMUX1 IRQ handler */ + IRQ_HANDLER 50 /* RDC IRQ handler */ + IRQ_HANDLER 51 /* USB0 IRQ handler */ + IRQ_HANDLER 52 /* XPI0 IRQ handler */ + IRQ_HANDLER 53 /* SDP IRQ handler */ + IRQ_HANDLER 54 /* PSEC IRQ handler */ + IRQ_HANDLER 55 /* SECMON IRQ handler */ + IRQ_HANDLER 56 /* RNG IRQ handler */ + IRQ_HANDLER 57 /* FUSE IRQ handler */ + IRQ_HANDLER 58 /* ADC0 IRQ handler */ + IRQ_HANDLER 59 /* ADC1 IRQ handler */ + IRQ_HANDLER 60 /* DAC0 IRQ handler */ + IRQ_HANDLER 61 /* DAC1 IRQ handler */ + IRQ_HANDLER 62 /* ACMP_0 IRQ handler */ + IRQ_HANDLER 63 /* ACMP_1 IRQ handler */ + IRQ_HANDLER 64 /* SYSCTL IRQ handler */ + IRQ_HANDLER 65 /* PGPIO IRQ handler */ + IRQ_HANDLER 66 /* PTMR IRQ handler */ + IRQ_HANDLER 67 /* PUART IRQ handler */ + IRQ_HANDLER 68 /* PEWDG IRQ handler */ + IRQ_HANDLER 69 /* BROWNOUT IRQ handler */ + IRQ_HANDLER 70 /* PAD_WAKEUP IRQ handler */ + IRQ_HANDLER 71 /* DEBUG0 IRQ handler */ + IRQ_HANDLER 72 /* DEBUG1 IRQ handler */ + +#else + +.global default_irq_handler +.weak default_irq_handler +.align 2 +default_irq_handler: +1: j 1b + +.macro IRQ_HANDLER irq + .weak default_isr_\irq + .set default_isr_\irq, default_irq_handler + .long default_isr_\irq +.endm + +.section .vector_table, "a" +.global __vector_table +.align 9 + +__vector_table: + .weak default_isr_trap + .set default_isr_trap, irq_handler_trap + .long default_isr_trap + IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_HANDLER 3 /* GPIO0_X IRQ handler */ + IRQ_HANDLER 4 /* GPIO0_Y IRQ handler */ + IRQ_HANDLER 5 /* GPTMR0 IRQ handler */ + IRQ_HANDLER 6 /* GPTMR1 IRQ handler */ + IRQ_HANDLER 7 /* GPTMR2 IRQ handler */ + IRQ_HANDLER 8 /* GPTMR3 IRQ handler */ + IRQ_HANDLER 9 /* Reserved */ + IRQ_HANDLER 10 /* Reserved */ + IRQ_HANDLER 11 /* Reserved */ + IRQ_HANDLER 12 /* Reserved */ + IRQ_HANDLER 13 /* UART0 IRQ handler */ + IRQ_HANDLER 14 /* UART1 IRQ handler */ + IRQ_HANDLER 15 /* UART2 IRQ handler */ + IRQ_HANDLER 16 /* UART3 IRQ handler */ + IRQ_HANDLER 17 /* UART4 IRQ handler */ + IRQ_HANDLER 18 /* UART5 IRQ handler */ + IRQ_HANDLER 19 /* UART6 IRQ handler */ + IRQ_HANDLER 20 /* UART7 IRQ handler */ + IRQ_HANDLER 21 /* I2C0 IRQ handler */ + IRQ_HANDLER 22 /* I2C1 IRQ handler */ + IRQ_HANDLER 23 /* I2C2 IRQ handler */ + IRQ_HANDLER 24 /* I2C3 IRQ handler */ + IRQ_HANDLER 25 /* SPI0 IRQ handler */ + IRQ_HANDLER 26 /* SPI1 IRQ handler */ + IRQ_HANDLER 27 /* SPI2 IRQ handler */ + IRQ_HANDLER 28 /* SPI3 IRQ handler */ + IRQ_HANDLER 29 /* TSNS IRQ handler */ + IRQ_HANDLER 30 /* MBX0A IRQ handler */ + IRQ_HANDLER 31 /* MBX0B IRQ handler */ + IRQ_HANDLER 32 /* EWDG0 IRQ handler */ + IRQ_HANDLER 33 /* EWDG1 IRQ handler */ + IRQ_HANDLER 34 /* HDMA IRQ handler */ + IRQ_HANDLER 35 /* MCAN0 IRQ handler */ + IRQ_HANDLER 36 /* MCAN1 IRQ handler */ + IRQ_HANDLER 37 /* MCAN2 IRQ handler */ + IRQ_HANDLER 38 /* MCAN3 IRQ handler */ + IRQ_HANDLER 39 /* PTPC IRQ handler */ + IRQ_HANDLER 40 /* PWM0 IRQ handler */ + IRQ_HANDLER 41 /* QEI0 IRQ handler */ + IRQ_HANDLER 42 /* SEI0 IRQ handler */ + IRQ_HANDLER 43 /* MMC0 IRQ handler */ + IRQ_HANDLER 44 /* TRGMUX0 IRQ handler */ + IRQ_HANDLER 45 /* PWM1 IRQ handler */ + IRQ_HANDLER 46 /* QEI1 IRQ handler */ + IRQ_HANDLER 47 /* SEI1 IRQ handler */ + IRQ_HANDLER 48 /* MMC1 IRQ handler */ + IRQ_HANDLER 49 /* TRGMUX1 IRQ handler */ + IRQ_HANDLER 50 /* RDC IRQ handler */ + IRQ_HANDLER 51 /* USB0 IRQ handler */ + IRQ_HANDLER 52 /* XPI0 IRQ handler */ + IRQ_HANDLER 53 /* SDP IRQ handler */ + IRQ_HANDLER 54 /* PSEC IRQ handler */ + IRQ_HANDLER 55 /* SECMON IRQ handler */ + IRQ_HANDLER 56 /* RNG IRQ handler */ + IRQ_HANDLER 57 /* FUSE IRQ handler */ + IRQ_HANDLER 58 /* ADC0 IRQ handler */ + IRQ_HANDLER 59 /* ADC1 IRQ handler */ + IRQ_HANDLER 60 /* DAC0 IRQ handler */ + IRQ_HANDLER 61 /* DAC1 IRQ handler */ + IRQ_HANDLER 62 /* ACMP_0 IRQ handler */ + IRQ_HANDLER 63 /* ACMP_1 IRQ handler */ + IRQ_HANDLER 64 /* SYSCTL IRQ handler */ + IRQ_HANDLER 65 /* PGPIO IRQ handler */ + IRQ_HANDLER 66 /* PTMR IRQ handler */ + IRQ_HANDLER 67 /* PUART IRQ handler */ + IRQ_HANDLER 68 /* PEWDG IRQ handler */ + IRQ_HANDLER 69 /* BROWNOUT IRQ handler */ + IRQ_HANDLER 70 /* PAD_WAKEUP IRQ handler */ + IRQ_HANDLER 71 /* DEBUG0 IRQ handler */ + IRQ_HANDLER 72 /* DEBUG1 IRQ handler */ + +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/HPM6280_svd.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/HPM6280_svd.xml new file mode 100644 index 00000000000..8965f644b8b --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/HPM6280_svd.xml @@ -0,0 +1,23366 @@ + + + HPMICRO + HPM6280 + HPM6200 + 1.0 + HPM6200 device + + /* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + + + other + r0p0 + little + false + true + true + 7 + false + + + + 8 + 32 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + + + FGPIO + FGPIO + GPIO + 0xc0000 + + 0x0 + 0x824 + registers + + + + 16 + 0x10 + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + DI[%s] + no description available + 0x0 + + VALUE + GPIO input value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-only + + + + + + 16 + 0x10 + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + DO[%s] + no description available + 0x100 + + VALUE + GPIO output value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + SET + GPIO output set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + CLEAR + GPIO output clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + TOGGLE + GPIO output toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + + 16 + 0x10 + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + OE[%s] + no description available + 0x200 + + VALUE + GPIO direction value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + SET + GPIO direction set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + CLEAR + GPIO direction clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + TOGGLE + GPIO direction toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + + 16 + 0x10 + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + IF[%s] + no description available + 0x300 + + VALUE + GPIO interrupt flag value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + write-only + + + + + + 16 + 0x10 + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + IE[%s] + no description available + 0x400 + + VALUE + GPIO interrupt enable value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + SET + GPIO interrupt enable set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + CLEAR + GPIO interrupt enable clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + TOGGLE + GPIO interrupt enable toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + + 16 + 0x10 + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + PL[%s] + no description available + 0x500 + + VALUE + GPIO interrupt polarity value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + SET + GPIO interrupt polarity set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + CLEAR + GPIO interrupt polarity clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + TOGGLE + GPIO interrupt polarity toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + + 16 + 0x10 + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + TP[%s] + no description available + 0x600 + + VALUE + GPIO interrupt type value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + SET + GPIO interrupt type set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + CLEAR + GPIO interrupt type clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TOGGLE + GPIO interrupt type toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + + 16 + 0x10 + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + AS[%s] + no description available + 0x700 + + VALUE + GPIO interrupt asynchronous value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + SET + GPIO interrupt asynchronous set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + CLEAR + GPIO interrupt asynchronous clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + TOGGLE + GPIO interrupt asynchronous toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + + + + GPIO0 + GPIO0 + GPIO + 0xf0000000 + + + GPIO1 + GPIO1 + GPIO + 0xf0004000 + + + PGPIO + PGPIO + GPIO + 0xf40dc000 + + + BGPIO + BGPIO + GPIO + 0xf5014000 + + + PLIC + PLIC + PLIC + 0xe4000000 + + 0x0 + 0x202000 + registers + + + + feature + Feature enable register + 0x0 + 32 + 0x00000000 + 0x00000003 + + + VECTORED + Vector mode enable +0: Disabled +1: Enabled + 1 + 1 + read-write + + + PREEMPT + Preemptive priority interrupt enable +0: Disabled +1: Enabled + 0 + 1 + read-write + + + + + 127 + 0x4 + PRIORITY1,PRIORITY2,PRIORITY3,PRIORITY4,PRIORITY5,PRIORITY6,PRIORITY7,PRIORITY8,PRIORITY9,PRIORITY10,PRIORITY11,PRIORITY12,PRIORITY13,PRIORITY14,PRIORITY15,PRIORITY16,PRIORITY17,PRIORITY18,PRIORITY19,PRIORITY20,PRIORITY21,PRIORITY22,PRIORITY23,PRIORITY24,PRIORITY25,PRIORITY26,PRIORITY27,PRIORITY28,PRIORITY29,PRIORITY30,PRIORITY31,PRIORITY32,PRIORITY33,PRIORITY34,PRIORITY35,PRIORITY36,PRIORITY37,PRIORITY38,PRIORITY39,PRIORITY40,PRIORITY41,PRIORITY42,PRIORITY43,PRIORITY44,PRIORITY45,PRIORITY46,PRIORITY47,PRIORITY48,PRIORITY49,PRIORITY50,PRIORITY51,PRIORITY52,PRIORITY53,PRIORITY54,PRIORITY55,PRIORITY56,PRIORITY57,PRIORITY58,PRIORITY59,PRIORITY60,PRIORITY61,PRIORITY62,PRIORITY63,PRIORITY64,PRIORITY65,PRIORITY66,PRIORITY67,PRIORITY68,PRIORITY69,PRIORITY70,PRIORITY71,PRIORITY72,PRIORITY73,PRIORITY74,PRIORITY75,PRIORITY76,PRIORITY77,PRIORITY78,PRIORITY79,PRIORITY80,PRIORITY81,PRIORITY82,PRIORITY83,PRIORITY84,PRIORITY85,PRIORITY86,PRIORITY87,PRIORITY88,PRIORITY89,PRIORITY90,PRIORITY91,PRIORITY92,PRIORITY93,PRIORITY94,PRIORITY95,PRIORITY96,PRIORITY97,PRIORITY98,PRIORITY99,PRIORITY100,PRIORITY101,PRIORITY102,PRIORITY103,PRIORITY104,PRIORITY105,PRIORITY106,PRIORITY107,PRIORITY108,PRIORITY109,PRIORITY110,PRIORITY111,PRIORITY112,PRIORITY113,PRIORITY114,PRIORITY115,PRIORITY116,PRIORITY117,PRIORITY118,PRIORITY119,PRIORITY120,PRIORITY121,PRIORITY122,PRIORITY123,PRIORITY124,PRIORITY125,PRIORITY126,PRIORITY127 + PRIORITY[%s] + no description available + 0x4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + 4 + 0x4 + PENDING0,PENDING1,PENDING2,PENDING3 + PENDING[%s] + no description available + 0x1000 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + 4 + 0x4 + TRIGGER0,TRIGGER1,TRIGGER2,TRIGGER3 + TRIGGER[%s] + no description available + 0x1080 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. +0: Level-triggered interrupt +1: Edge-triggered interrupt + 0 + 32 + read-only + + + + + NUMBER + Number of supported interrupt sources and targets + 0x1100 + 32 + 0xFFFFFFFF + + + NUM_TARGET + The number of supported targets + 16 + 16 + read-only + + + NUM_INTERRUPT + The number of supported interrupt sources + 0 + 16 + read-only + + + + + INFO + Version and the maximum priority + 0x1104 + 32 + 0xFFFFFFFF + + + MAX_PRIORITY + The maximum priority supported + 16 + 16 + read-only + + + VERSION + The version of the PLIC design + 0 + 16 + read-only + + + + + 2 + 0x80 + target0,target1 + TARGETINT[%s] + no description available + 0x2000 + + 4 + 0x4 + INTEN0,INTEN1,INTEN2,INTEN3 + INTEN[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + + 2 + 0x1000 + target0,target1 + TARGETCONFIG[%s] + no description available + 0x200000 + + THRESHOLD + Target0 priority threshold + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + THRESHOLD + Interrupt priority threshold. + 0 + 32 + read-write + + + + + CLAIM + Target claim and complete + 0x4 + 32 + 0x00000000 + 0x000003FF + + + INTERRUPT_ID + On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). + 0 + 10 + read-write + + + + + PPS + Preempted priority stack + 0x400 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY_PREEMPTED + Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. + 0 + 32 + read-write + + + + + + + + MCHTMR + MCHTMR + MCHTMR + 0xe6000000 + + 0x0 + 0x10 + registers + + + + MTIME + Machine Time + 0x0 + 64 + 0x0000000000020210 + 0xFFFFFFFFFFFFFFFF + + + MTIME + Machine time + 0 + 64 + read-write + + + + + MTIMECMP + Machine Time Compare + 0x8 + 64 + 0x0000000000020210 + 0xFFFFFFFFFFFFFFFF + + + MTIMECMP + Machine time compare + 0 + 64 + read-write + + + + + + + PLICSW + PLICSW + PLIC_SW + 0xe6400000 + + 0x1000 + 0x1ff008 + registers + + + + PENDING + Pending status + 0x1000 + 32 + 0x00000000 + 0x00000002 + + + INTERRUPT + writing 1 to trigger software interrupt + 1 + 1 + read-write + + + + + INTEN + Interrupt enable + 0x2000 + 32 + 0x00000000 + 0x00000001 + + + INTERRUPT + enable software interrupt + 0 + 1 + read-write + + + + + CLAIM + Claim and complete. + 0x200004 + 32 + 0x00000000 + 0x00000001 + + + INTERRUPT_ID + On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). + 0 + 1 + read-write + + + + + + + GPIOM + GPIOM + GPIOM + 0xf0008000 + + 0x0 + 0x800 + registers + + + + 16 + 0x80 + gpioa,gpiob,gpioc,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + ASSIGN[%s] + no description available + 0x0 + + 32 + 0x4 + PIN00,PIN01,PIN02,PIN03,PIN04,PIN05,PIN06,PIN07,PIN08,PIN09,PIN10,PIN11,PIN12,PIN13,PIN14,PIN15,PIN16,PIN17,PIN18,PIN19,PIN20,PIN21,PIN22,PIN23,PIN24,PIN25,PIN26,PIN27,PIN28,PIN29,PIN30,PIN31 + PIN[%s] + no description available + 0x0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + + + + ADC0 + ADC0 + ADC16 + 0xf0010000 + + 0x0 + 0x1464 + registers + + + + 12 + 0x4 + trg0a,trg0b,trg0c,trg1a,trg1b,trg1c,trg2a,trg2b,trg2c,trg3a,trg3b,trg3c + CONFIG[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFF3F3F7F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interrupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interrupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interrupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + QUEUE_EN + preemption queue enable control + 6 + 1 + read-write + + + INTEN0 + interrupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + trg_dma_addr + No description available + 0x30 + 32 + 0x00000000 + 0xFFFFFFFC + + + TRG_DMA_ADDR + buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) + 2 + 30 + read-write + + + + + trg_sw_sta + No description available + 0x34 + 32 + 0x00000000 + 0x0000001F + + + TRG_SW_STA + SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it. + 4 + 1 + read-write + + + TRIG_SW_INDEX + which trigger for the SW trigger +0 for trig0a, 1 for trig0b… +3 for trig1a, …11 for trig3c + 0 + 4 + read-write + + + + + 16 + 0x4 + chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 + BUS_RESULT[%s] + no description available + 0x400 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + buf_cfg0 + No description available + 0x500 + 32 + 0x00000000 + 0x00000001 + + + WAIT_DIS + set to disable read waiting, get result immediately but maybe not current conversion result. + 0 + 1 + read-write + + + + + seq_cfg0 + No description available + 0x800 + 32 + 0x00000000 + 0x80000F1F + + + CYCLE + current dma write cycle bit + 31 + 1 + read-only + + + SEQ_LEN + sequence queue length, 0 for one, 0xF for 16 + 8 + 4 + read-write + + + RESTART_EN + if set together with cont_en, HW will continue process the whole queue after trigger once. +If cont_en is 0, this bit is not used + 4 + 1 + read-write + + + CONT_EN + if set, HW will continue process the queue till end(seq_len) after trigger once + 3 + 1 + read-write + + + SW_TRIG + SW trigger, pulse signal, cleared by HW one cycle later + 2 + 1 + write-only + + + SW_TRIG_EN + set to enable SW trigger + 1 + 1 + read-write + + + HW_TRIG_EN + set to enable external HW trigger, only trigger on posedge + 0 + 1 + read-write + + + + + seq_dma_addr + No description available + 0x804 + 32 + 0x00000000 + 0xFFFFFFFC + + + TAR_ADDR + dma target address, should be 4-byte aligned + 2 + 30 + read-write + + + + + seq_dma_cfg + No description available + 0x80c + 32 + 0x00000000 + 0x0FFF3FFF + + + STOP_POS + if stop_en is set, SW is responsible to update this field to the next read point, HW should not write data to this point since it's not read out by SW yet + 16 + 12 + read-write + + + DMA_RST + set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. +SW should clear all cycle bit in buffer to 0 before clear dma_rst + 13 + 1 + read-write + + + STOP_EN + set to stop dma if reach the stop_pos + 12 + 1 + read-write + + + BUF_LEN + dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 +0 for 4byte; +0xFFF for 16kbyte. + 0 + 12 + read-write + + + + + 16 + 0x4 + cfg0,cfg1,cfg2,cfg3,cfg4,cfg5,cfg6,cfg7,cfg8,cfg9,cfg10,cfg11,cfg12,cfg13,cfg14,cfg15 + SEQ_QUE[%s] + no description available + 0x810 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + 16 + 0x10 + chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 + PRD_CFG[%s] + no description available + 0xc00 + + prd_cfg + No description available + 0x0 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + prd_thshd_cfg + No description available + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + prd_result + No description available + 0x8 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + + 16 + 0x4 + chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 + SAMPLE_CFG[%s] + no description available + 0x1000 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + conv_cfg1 + No description available + 0x1104 + 32 + 0x00000000 + 0x000001FF + + + CONVERT_CLOCK_NUMBER + convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider); +user can use small value to get faster conversion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. +Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC conversion(plus sample) need 25 cycles(50MHz). + 4 + 5 + read-write + + + CLOCK_DIVIDER + clock_period, N half clock cycle per half adc cycle +0 for same adc_clk and bus_clk, +1 for 1:2, +2 for 1:3, +... +15 for 1:16 +Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk + 0 + 4 + read-write + + + + + adc_cfg0 + No description available + 0x1108 + 32 + 0x00000000 + 0xA0000001 + + + SEL_SYNC_AHB + set to 1 will enable sync AHB bus, to get better bus performance. +Adc_clk must to be set to same as bus clock at this mode + 31 + 1 + read-write + + + ADC_AHB_EN + set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; + 29 + 1 + read-write + + + PORT3_REALTIME + set to enable trg queue stop other queues + 0 + 1 + read-write + + + + + int_sts + No description available + 0x1110 + 32 + 0x00000000 + 0xFFE0FFFF + + + TRIG_CMPT + interrupt for one trigger conversion complete if enabled + 31 + 1 + read-write + + + TRIG_SW_CFLCT + No description available + 30 + 1 + read-write + + + TRIG_HW_CFLCT + No description available + 29 + 1 + read-write + + + READ_CFLCT + read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel + 28 + 1 + read-write + + + SEQ_SW_CFLCT + sequence queue conflict interrupt, set if HW or SW trigger received during conversion + 27 + 1 + read-write + + + SEQ_HW_CFLCT + No description available + 26 + 1 + read-write + + + SEQ_DMAABT + dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set + 25 + 1 + read-write + + + SEQ_CMPT + the whole sequence complete interrupt + 24 + 1 + read-write + + + SEQ_CVC + one conversion complete in seq_queue if related seq_int_en is set + 23 + 1 + read-write + + + DMA_FIFO_FULL + DMA fifo full interrupt, user need to check clock frequency if it's set. + 22 + 1 + read-write + + + AHB_ERR + set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr + 21 + 1 + read-write + + + WDOG + set if one chanel watch dog event triggered + 0 + 16 + read-write + + + + + int_en + No description available + 0x1114 + 32 + 0x00000000 + 0xFFE0FFFF + + + TRIG_CMPT + interrupt for one trigger conversion complete if enabled + 31 + 1 + read-write + + + TRIG_SW_CFLCT + No description available + 30 + 1 + read-write + + + TRIG_HW_CFLCT + No description available + 29 + 1 + read-write + + + READ_CFLCT + read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel + 28 + 1 + read-write + + + SEQ_SW_CFLCT + sequence queue conflict interrupt, set if HW or SW trigger received during conversion + 27 + 1 + read-write + + + SEQ_HW_CFLCT + No description available + 26 + 1 + read-write + + + SEQ_DMAABT + dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set + 25 + 1 + read-write + + + SEQ_CMPT + the whole sequence complete interrupt + 24 + 1 + read-write + + + SEQ_CVC + one conversion complete in seq_queue if related seq_int_en is set + 23 + 1 + read-write + + + DMA_FIFO_FULL + DMA fifo full interrupt, user need to check clock frequency if it's set. + 22 + 1 + read-write + + + AHB_ERR + set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr + 21 + 1 + read-write + + + WDOG + set if one chanel watch dog event triggered + 0 + 16 + read-write + + + + + ana_ctrl0 + No description available + 0x1200 + 32 + 0x00000000 + 0x00001004 + + + ADC_CLK_ON + set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. +MUST set clock_period to 0 or 1 for adc16 reg access + 12 + 1 + read-write + + + STARTCAL + set to start the offset calibration cycle (Active H). user need to clear it after setting it. + 2 + 1 + read-write + + + + + ana_status + No description available + 0x1210 + 32 + 0x00000000 + 0x00000080 + + + CALON + Indicates if the ADC is in calibration mode (Active H). + 7 + 1 + read-write + + + + + 34 + 0x2 + adc16_para00,adc16_para01,adc16_para02,adc16_para03,adc16_para04,adc16_para05,adc16_para06,adc16_para07,adc16_para08,adc16_para09,adc16_para10,adc16_para11,adc16_para12,adc16_para13,adc16_para14,adc16_para15,adc16_para16,adc16_para17,adc16_para18,adc16_para19,adc16_para20,adc16_para21,adc16_para22,adc16_para23,adc16_para24,adc16_para25,adc16_para26,adc16_para27,adc16_para28,adc16_para29,adc16_para30,adc16_para31,adc16_para32,adc16_para33 + ADC16_PARAMS[%s] + no description available + 0x1400 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description available + 0 + 16 + read-write + + + + + adc16_config0 + No description available + 0x1444 + 32 + 0x00000000 + 0x01F07FFF + + + REG_EN + set to enable regulator + 24 + 1 + read-write + + + BANDGAP_EN + set to enable bandgap. user should set reg_en and bandgap_en before use adc16. + 23 + 1 + read-write + + + CAL_AVG_CFG + for average the calibration result. +0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; +4- 16 loops; 5-32 loops; others reserved + 20 + 3 + read-write + + + PREEMPT_EN + set to enable preemption feature + 14 + 1 + read-write + + + CONV_PARAM + conversion parameter + 0 + 14 + read-write + + + + + adc16_config1 + No description available + 0x1460 + 32 + 0x00000000 + 0x00001F00 + + + COV_END_CNT + used for faster conversion, user can change it to get higher convert speed(but less accuracy). +should set to (21-convert_clock_number+1). + 8 + 5 + read-write + + + + + + + ADC1 + ADC1 + ADC16 + 0xf0014000 + + + ADC2 + ADC2 + ADC16 + 0xf0018000 + + + SDM + SDM + SDM + 0xf001c000 + + 0x0 + 0x110 + registers + + + + CTRL + SDM control register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFE + + + SFTRST + software reset the module if asserted to be1’b1. + 31 + 1 + read-write + + + CHMD + Channel Rcv mode +Bits[2:0] for Ch0. +Bits[5:3] for Ch1 +Bits[8:6] for Ch2 +Bits[11:9] for Ch3 +3'b000: Capture at posedge of MCLK +3'b001: Capture at both posedge and negedge of MCLK +3'b010: Manchestor Mode +3'b011: Capture at negedge of MCLK +3'b100: Capture at every other posedge of MCLK +3'b101: Capture at every other negedge of MCLK +Others: Undefined + 14 + 12 + read-write + + + SYNC_MCLK + Asserted to double sync the mclk input pin before its usage inside the module + 10 + 4 + read-write + + + SYNC_MDAT + Asserted to double sync the mdat input pin before its usage inside the module + 6 + 4 + read-write + + + CH_EN + Channel Enable + 2 + 4 + read-write + + + IE + Interrupt Enable + 1 + 1 + read-write + + + + + INT_EN + Interrupt enable register. + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH3DRY + Ch3 Data Ready interrupt enable. + 7 + 1 + read-write + + + CH2DRY + Ch2 Data Ready interrupt enable + 6 + 1 + read-write + + + CH1DRY + Ch1 Data Ready interrupt enable + 5 + 1 + read-write + + + CH0DRY + Ch0 Data Ready interrupt enable + 4 + 1 + read-write + + + CH3ERR + Ch3 Error interrupt enable. + 3 + 1 + read-write + + + CH2ERR + Ch2 Error interrupt enable + 2 + 1 + read-write + + + CH1ERR + Ch1 Error interrupt enable + 1 + 1 + read-write + + + CH0ERR + Ch0 Error interrupt enable + 0 + 1 + read-write + + + + + STATUS + Status Registers + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH3DRY + Ch3 Data Ready. +De-assert this bit by reading the data (or data fifo) registers. + 7 + 1 + read-only + + + CH2DRY + Ch2 Data Ready + 6 + 1 + read-only + + + CH1DRY + Ch1 Data Ready + 5 + 1 + read-only + + + CH0DRY + Ch0 Data Ready + 4 + 1 + read-only + + + CH3ERR + Ch3 Error. +ORed together by channel related error signals and corresponding error interrupt enable signals. +De-assert this bit by write-1-clear the corresponding error status bits in the channel status registers. + 3 + 1 + read-only + + + CH2ERR + Ch2 Error + 2 + 1 + read-only + + + CH1ERR + Ch1 Error + 1 + 1 + read-only + + + CH0ERR + Ch0 Error + 0 + 1 + read-only + + + + + 4 + 0x40 + 0,1,2,3 + CH[%s] + no description available + 0x10 + + SDFIFOCTRL + Data FIFO Path Control Register + 0x0 + 32 + 0x00000000 + 0xFFFF01F4 + + + GATE_SAMPLES + The number-1-3 of input PDM bit samples to be gated when CIC_GATE_EN=1. Max 255. So the minimum gated samples is 4 samples when GATE_SAMPLES=0. + 16 + 8 + read-write + + + THRSH + FIFO threshold (0,..,16) (fillings > threshold, then gen int) + 4 + 5 + read-write + + + D_RDY_INT_EN + FIFO data ready interrupt enable + 2 + 1 + read-write + + + + + SDCTRLP + Data Path Control Primary Register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + MANCH_THR + Manchester Decoding threshold. 3/4 of PERIOD_MCLK[7:0] + 25 + 7 + read-write + + + WDOG_THR + Watch dog threshold for channel failure of CLK halting + 17 + 8 + read-write + + + AF_IE + Acknowledge feedback interrupt enable + 16 + 1 + read-write + + + DFFOVIE + Ch Data FIFO overflow interrupt enable + 15 + 1 + read-write + + + DSATIE + Ch CIC Data Saturation Interrupt Enable + 14 + 1 + read-write + + + DRIE + Ch Data Ready Interrupt Enable + 13 + 1 + read-write + + + SYNCSEL + Select the PWM SYNC Source + 7 + 6 + read-write + + + FFSYNCCLREN + Auto clear FIFO when a new SDSYNC event is found. Only valid when WTSYNCEN=1 + 6 + 1 + read-write + + + WTSYNACLR + 1: Asserted to Auto clear WTSYNFLG when the SDFFINT is gen +0: WTSYNFLG should be cleared manually by WTSYNMCLR + 5 + 1 + read-write + + + WTSYNMCLR + 1: Manually clear WTSYNFLG. Auto-clear. + 4 + 1 + read-write + + + WTSYNCEN + 1: Start to store data only after PWM SYNC event +0: Start to store data whenever enabled + 3 + 1 + read-write + + + D32 + 1:32 bit data +0:16 bit data + 2 + 1 + read-write + + + DR_OPT + 1: Use Data FIFO Ready as data ready when fifo fillings are greater than the threshold +0: Use Data Reg Ready as data ready + 1 + 1 + read-write + + + EN + Data Path Enable + 0 + 1 + read-write + + + + + SDCTRLE + Data Path Control Extra Register + 0x8 + 32 + 0x00000000 + 0xFE77FFFF + + + CIC_GATE_TYPE + 1: the gate cycle is determined by SDFIFOCTRLn[GATE_SAMPLES]. +0: the gate cycle is determined by the CIC decimation counter, and the minimal gated off PDM bits are determined by SDFIFOCTRLn[GATE_SAMPLES], and at the same time, to keep alignment with normal PCM sampling time. + 31 + 1 + read-write + + + CIC_GATE_POL + 1: When mask signal is 1, pause the CIC stage at he rising edge of mask signal. +0: When mask signal is 0, pause the CIC stage at he falling edge of mask signal. + 30 + 1 + read-write + + + CIC_GATE_SEL + Select the mask signal for CIC gate signal. + 26 + 4 + read-write + + + CIC_GATE_EN + 1: the CIC stage can be paused by the mask input. +0: the CIC stage won't be paused by the mask input. + 25 + 1 + read-write + + + TIMESTAMP_TYPE + 1. Use the time (when the data is calculated out) - delta_time_of_filter_span as the timestamp. +0: Use the time when the data is calculated out. + 22 + 1 + read-write + + + DFIFO_S_T + 1: the output of SDFIFO is data and timestamp interleaved. First is data. +0: the output of SDFIFO is data only + 21 + 1 + read-write + + + DATA_S_T + "1: the read output of SData is data and timestamp interleaved. First is data. +0: the read output of SData is data only" + 20 + 1 + read-write + + + SGD_ORDR + CIC order +0: SYNC1 +1: SYNC2 +2: SYNC3 +3: FAST_SYNC + 17 + 2 + read-write + + + PWMSYNC + Asserted to double sync the PWM trigger signal + 16 + 1 + read-write + + + CIC_SCL + CIC shift control + 11 + 4 + read-write + + + CIC_DEC_RATIO + CIC decimation ratio. 0 means div-by-256 + 3 + 8 + read-write + + + IGN_INI_SAMPLES + NotZero: Don't store the first samples that are not accurate +Zero: Store all samples + 0 + 3 + read-write + + + + + SDST + Data Path Status + 0xc + 32 + 0x00000000 + 0xFF8033FF + + + PERIOD_MCLK + maxim of mclk spacing in cycles, using edges of mclk signal. In manchester coding mode, it is just the period of MCLK. In other modes, it is almost the half period. + 23 + 8 + read-only + + + SDATA_D0_T1 + 1: next readout is timestamp +0: next readout is data + 13 + 1 + read-only + + + SDFIFO_D0_T1 + 1: next readout is timestamp +0: next readout is data + 12 + 1 + read-only + + + FIFO_DR + FIFO data ready + 9 + 1 + write-only + + + AF + Achnowledge flag + 8 + 1 + write-only + + + DOV_ERR + Data FIFO Overflow Error. Error flag. + 7 + 1 + write-only + + + DSAT_ERR + CIC out Data saturation err. Error flag. + 6 + 1 + write-only + + + WTSYNFLG + Wait-for-sync event found + 5 + 1 + read-only + + + FILL + Data FIFO Fillings + 0 + 5 + read-only + + + + + SDATA + Data + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + Data + 0 + 32 + read-only + + + + + SDFIFO + FIFO Data + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + FIFO Data + 0 + 32 + read-only + + + + + SCAMP + instant Amplitude Results + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + instant Amplitude Results + 0 + 16 + read-only + + + + + SCHTL + Amplitude Threshold for High Limit + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + Amplitude Threshold for High Limit + 0 + 16 + read-write + + + + + SCHTLZ + Amplitude Threshold for zero crossing + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + Amplitude Threshold for zero crossing + 0 + 16 + read-write + + + + + SCLLT + Amplitude Threshold for low limit + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + Amplitude Threshold for low limit + 0 + 16 + read-write + + + + + SCCTRL + Amplitude Path Control + 0x28 + 32 + 0x00000000 + 0xFFFC01FF + + + HZ_EN + Zero Crossing Enable + 23 + 1 + read-write + + + MF_IE + Module failure Interrupt enable + 22 + 1 + read-write + + + HL_IE + HLT Interrupt Enable + 21 + 1 + read-write + + + LL_IE + LLT interrupt Enable + 20 + 1 + read-write + + + SGD_ORDR + CIC order +0: SYNC1 +1: SYNC2 +2: SYNC3 +3: FAST_SYNC + 18 + 2 + read-write + + + CIC_DEC_RATIO + CIC decimation ratio. 0 means div-by-32 + 4 + 5 + read-write + + + IGN_INI_SAMPLES + NotZero: Ignore the first samples that are not accurate +Zero: Use all samples + 1 + 3 + read-write + + + EN + Amplitude Path Enable + 0 + 1 + read-write + + + + + SCST + Amplitude Path Status + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + HZ + Amplitude rising above HZ event found. + 3 + 1 + write-only + + + MF + power modulator Failure found. MCLK not found. Error flag. + 2 + 1 + write-only + + + CMPH + HLT out of range. Error flag. + 1 + 1 + write-only + + + CMPL + LLT out of range. Error flag. + 0 + 1 + write-only + + + + + + + + ACMP + ACMP + ACMP + 0xf0020000 + + 0x0 + 0x80 + registers + + + + 4 + 0x20 + chn0,chn1,chn2,chn3 + CHANNEL[%s] + no description available + 0x0 + + cfg + Configure Register + 0x0 + 32 + 0x00000000 + 0xFF7FFFFF + + + HYST + This bitfield configure the comparator hysteresis. +00: Hysteresis level 0 +01: Hysteresis level 1 +10: Hysteresis level 2 +11: Hysteresis level 3 + 30 + 2 + read-write + + + DACEN + This bit enable the comparator internal DAC +0: DAC disabled +1: DAC enabled + 29 + 1 + read-write + + + HPMODE + This bit enable the comparator high performance mode. +0: HP mode disabled +1: HP mode enabled + 28 + 1 + read-write + + + CMPEN + This bit enable the comparator. +0: ACMP disabled +1: ACMP enabled + 27 + 1 + read-write + + + MINSEL + PIN select, from pad_ai_acmp[7:1] and dac_out + 24 + 3 + read-write + + + PINSEL + MIN select, from pad_ai_acmp[7:1] and dac_out + 20 + 3 + read-write + + + CMPOEN + This bit enable the comparator output on pad. +0: ACMP output disabled +1: ACMP output enabled + 19 + 1 + read-write + + + FLTBYPS + This bit bypass the comparator output digital filter. +0: The ACMP output need pass digital filter +1: The ACMP output digital filter is bypassed. + 18 + 1 + read-write + + + WINEN + This bit enable the comparator window mode. +0: Window mode is disabled +1: Window mode is enabled + 17 + 1 + read-write + + + OPOL + The output polarity control bit. +0: The ACMP output remain un-changed. +1: The ACMP output is inverted. + 16 + 1 + read-write + + + FLTMODE + This bitfield define the ACMP output digital filter mode: +000-bypass +100-change immediately; +101-change after filter; +110-stalbe low; +111-stable high + 13 + 3 + read-write + + + SYNCEN + This bit enable the comparator output synchronization. +0: ACMP output not synchronized with ACMP clock. +1: ACMP output synchronized with ACMP clock. + 12 + 1 + read-write + + + FLTLEN + This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. + 0 + 12 + read-write + + + + + daccfg + DAC configure register + 0x4 + 32 + 0x00000000 + 0x000000FF + + + DACCFG + 8bit DAC digital value output to analog block + 0 + 8 + read-write + + + + + sr + Status register + 0x10 + 32 + 0x00000000 + 0x00000003 + + + FEDGF + Output falling edge flag. Write 1 to clear this flag. + 1 + 1 + read-write + + + REDGF + Output rising edge flag. Write 1 to clear this flag. + 0 + 1 + read-write + + + + + irqen + Interrupt request enable register + 0x14 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag interrupt enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag interrupt enable bit. + 0 + 1 + read-write + + + + + dmaen + DMA request enable register + 0x18 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag DMA request enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag DMA request enable bit. + 0 + 1 + read-write + + + + + + + + DAC0 + DAC0 + DAC + 0xf0024000 + + 0x0 + 0x4c + registers + + + + cfg0 + No description available + 0x0 + 32 + 0x00000000 + 0x0FFF03FF + + + SW_DAC_DATA + dac data used in direct mode(dac_mode==2'b10) + 16 + 12 + write-only + + + DMA_AHB_EN + set to enable internal DMA, it will read one burst if enough space in FIFO. +Should only be used in buffer mode. + 9 + 1 + write-only + + + SYNC_MODE + 1: sync dac clock and ahb clock. + all HW trigger signals are pulse in sync mode, can get faster response; +0: async dac clock and ahb_clock + all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock) + 8 + 1 + write-only + + + TRIG_MODE + 0: single mode, one trigger pulse will send one 12bit data to DAC analog; +1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data. + 7 + 1 + write-only + + + HW_TRIG_EN + set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode + 6 + 1 + write-only + + + DAC_MODE + 00: direct mode, DAC output the fixed configured data(from sw_dac_data) +01: step mode, DAC output from start_point to end point, with configured step, can step up or step down +10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; +11: trigger mode, DAC output from external trigger signals +Note: +Trigger mode is not supported in hpm63xx and hpm62xx families. + 4 + 2 + write-only + + + BUF_DATA_MODE + data structure for buffer mode, +0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. +1: each 32-bit data contains 1 point, b11:0 for first + 3 + 1 + write-only + + + HBURST_CFG + DAC support following fixed burst only +000-SINGLE; 011-INCR4; 101: INCR8 +others are reserved + 0 + 3 + write-only + + + + + cfg1 + No description available + 0x4 + 32 + 0x00010000 + 0x0007FFFF + + + ANA_CLK_EN + set to enable analog clock(divided by ana_div_cfg) +need to be set in direct mode and trigger mode + 18 + 1 + read-write + + + ANA_DIV_CFG + clock divider config for ana_clk to dac analog; +00: div2 +01: div4 +10: div6 +11: div8 + 16 + 2 + read-write + + + DIV_CFG + step mode and buffer mode: + defines how many clk_dac cycles to change data to analog, should configured to less than 1MHz data rate. +Direct mode and trigger mode: + defines how many clk_dac cycles to accpet the input data, dac will not accept new written data or trigger data before the clock cycles passed. should configured to less than 1MHz. +Note: +For direct mode and trigger mode, this config is not supported in hpm63xx and hpm62xx families. + 0 + 16 + read-write + + + + + cfg2 + No description available + 0x8 + 32 + 0x00000000 + 0x000000FF + + + DMA_RST1 + set to reset dma read pointer to buf1_start_addr; +if set both dma_rst0&dma_rst1, will set to buf0_start_addr +user can set fifo_clr bit when use dma_rst* + 7 + 1 + write-only + + + DMA_RST0 + set to reset dma read pointer to buf0_start_addr + 6 + 1 + write-only + + + FIFO_CLR + set to clear FIFO content(set both read/write pointer to 0) + 5 + 1 + write-only + + + BUF_SW_TRIG + software trigger for buffer mode, +W1C in single mode. +RW in continual mode + 4 + 1 + read-write + + + STEP_SW_TRIG3 + No description available + 3 + 1 + read-write + + + STEP_SW_TRIG2 + No description available + 2 + 1 + read-write + + + STEP_SW_TRIG1 + No description available + 1 + 1 + read-write + + + STEP_SW_TRIG0 + software trigger0 for step mode, +W1C in single mode. +RW in continual mode + 0 + 1 + read-write + + + + + 4 + 0x4 + step0,step1,step2,step3 + STEP_CFG[%s] + no description available + 0x10 + 32 + 0x00000000 + 0x3FFFFFFF + + + ROUND_MODE + 0: stop at end point; +1: reload start point, step again + 29 + 1 + read-write + + + UP_DOWN + 0 for up, 1 for down + 28 + 1 + read-write + + + END_POINT + No description available + 16 + 12 + read-write + + + STEP_NUM + output data change step_num each DAC clock cycle. +Ex: if step_num=3, output data sequence is 0,3,6,9 +NOTE: user should make sure end_point can be reached if step_num is not 1 +if step_num is 0, output data will always at start point + 12 + 4 + read-write + + + START_POINT + No description available + 0 + 12 + read-write + + + + + 2 + 0x4 + buf0,buf1 + BUF_ADDR[%s] + no description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFD + + + BUF_START_ADDR + buffer start address, should be 4-byte aligned +AHB burst can't cross 1K-byte boundary, user should config the address/length/burst to avoid such issue. + 2 + 30 + read-write + + + BUF_STOP + set to stop read point at end of bufffer0 + 0 + 1 + read-write + + + + + buf_length + No description available + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + BUF1_LEN + buffer length, 1 indicate one 32bit date, 256K-byte max for one buffer + 16 + 16 + read-write + + + BUF0_LEN + No description available + 0 + 16 + read-write + + + + + irq_sts + No description available + 0x30 + 32 + 0x00000000 + 0x0000001F + + + STEP_CMPT + No description available + 4 + 1 + write-only + + + AHB_ERROR + set if hresp==2'b01(ERROR) + 3 + 1 + write-only + + + FIFO_EMPTY + No description available + 2 + 1 + write-only + + + BUF1_CMPT + No description available + 1 + 1 + write-only + + + BUF0_CMPT + No description available + 0 + 1 + write-only + + + + + irq_en + No description available + 0x34 + 32 + 0x00000000 + 0x0000001F + + + STEP_CMPT + No description available + 4 + 1 + read-write + + + AHB_ERROR + No description available + 3 + 1 + read-write + + + FIFO_EMPTY + No description available + 2 + 1 + read-write + + + BUF1_CMPT + No description available + 1 + 1 + read-write + + + BUF0_CMPT + No description available + 0 + 1 + read-write + + + + + dma_en + No description available + 0x38 + 32 + 0x00000000 + 0x00000013 + + + STEP_CMPT + No description available + 4 + 1 + read-write + + + BUF1_CMPT + No description available + 1 + 1 + read-write + + + BUF0_CMPT + No description available + 0 + 1 + read-write + + + + + ana_cfg0 + No description available + 0x40 + 32 + 0x00000030 + 0x000001FF + + + DAC12BIT_LP_MODE + No description available + 8 + 1 + read-write + + + DAC_CONFIG + No description available + 4 + 4 + read-write + + + CALI_DELTA_V_CFG + No description available + 2 + 2 + read-write + + + BYPASS_CALI_GM + No description available + 1 + 1 + read-write + + + DAC12BIT_EN + No description available + 0 + 1 + read-write + + + + + cfg0_bak + No description available + 0x44 + 32 + 0x00000000 + 0x0FFF03FF + + + SW_DAC_DATA + dac data used in direct mode(dac_mode==2'b10) + 16 + 12 + read-write + + + DMA_AHB_EN + set to enable internal DMA, it will read one burst if enough space in FIFO. +Should only be used in buffer mode. + 9 + 1 + read-write + + + SYNC_MODE + 1: sync dac clock and ahb clock. + all HW trigger signals are pulse in sync mode, can get faster response; +0: async dac clock and ahb_clock + all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock) + 8 + 1 + read-write + + + TRIG_MODE + 0: single mode, one trigger pulse will send one 12bit data to DAC analog; +1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data. + 7 + 1 + read-write + + + HW_TRIG_EN + set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode + 6 + 1 + read-write + + + DAC_MODE + 00: direct mode, DAC output the fixed configured data(from sw_dac_data) +01: step mode, DAC output from start_point to end point, with configured step, can step up or step down +10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; + 4 + 2 + read-write + + + BUF_DATA_MODE + data structure for buffer mode, +0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. +1: each 32-bit data contains 1 point, b11:0 for first + 3 + 1 + read-write + + + HBURST_CFG + DAC support following fixed burst only +000-SINGLE; 011-INCR4; 101: INCR8 +others are reserved + 0 + 3 + read-write + + + + + status0 + No description available + 0x48 + 32 + 0x00000000 + 0x00FFFF80 + + + CUR_BUF_OFFSET + No description available + 8 + 16 + read-write + + + CUR_BUF_INDEX + No description available + 7 + 1 + read-write + + + + + + + DAC1 + DAC1 + DAC + 0xf0028000 + + + SPI0 + SPI0 + SPI + 0xf0030000 + + 0x10 + 0x70 + registers + + + + TransFmt + Transfer Format Register + 0x10 + 32 + 0x00020780 + 0xFFFF1F9F + + + ADDRLEN + Address length in bytes +0x0: 1 byte +0x1: 2 bytes +0x2: 3 bytes +0x3: 4 bytes + 16 + 2 + read-write + + + DATALEN + The length of each data unit in bits +The actual bit number of a data unit is (DataLen + 1) + 8 + 5 + read-write + + + DATAMERGE + Enable Data Merge mode, which does automatic data split on write and data coalescing on read. +This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. +When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed. + 7 + 1 + read-write + + + MOSIBIDIR + Bi-directional MOSI in regular (single) mode +0x0: MOSI is uni-directional signal in regular mode. +0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two + 4 + 1 + read-write + + + LSB + Transfer data with the least significant bit first +0x0: Most significant bit first +0x1: Least significant bit first + 3 + 1 + read-write + + + SLVMODE + SPI Master/Slave mode selection +0x0: Master mode +0x1: Slave mode + 2 + 1 + read-write + + + CPOL + SPI Clock Polarity +0x0: SCLK is LOW in the idle states +0x1: SCLK is HIGH in the idle states + 1 + 1 + read-write + + + CPHA + SPI Clock Phase +0x0: Sampling data at odd SCLK edges +0x1: Sampling data at even SCLK edges + 0 + 1 + read-write + + + + + TransCtrl + Transfer Control Register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + SLVDATAONLY + Data-only mode (slave mode only) +0x0: Disable the data-only mode +0x1: Enable the data-only mode +Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0. + 31 + 1 + read-write + + + CMDEN + SPI command phase enable (Master mode only) +0x0: Disable the command phase +0x1: Enable the command phase + 30 + 1 + read-write + + + ADDREN + SPI address phase enable (Master mode only) +0x0: Disable the address phase +0x1: Enable the address phase + 29 + 1 + read-write + + + ADDRFMT + SPI address phase format (Master mode only) +0x0: Address phase is the regular (single) mode +0x1: The format of the address phase is the same as the data phase (DualQuad). + 28 + 1 + read-write + + + TRANSMODE + Transfer mode +The transfer sequence could be +0x0: Write and read at the same time +0x1: Write only +0x2: Read only +0x3: Write, Read +0x4: Read, Write +0x5: Write, Dummy, Read +0x6: Read, Dummy, Write +0x7: None Data (must enable CmdEn or AddrEn in master mode) +0x8: Dummy, Write +0x9: Dummy, Read +0xa~0xf: Reserved + 24 + 4 + read-write + + + DUALQUAD + SPI data phase format +0x0: Regular (Single) mode +0x1: Dual I/O mode +0x2: Quad I/O mode +0x3: Reserved + 22 + 2 + read-write + + + TOKENEN + Token transfer enable (Master mode only) +Append a one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. +0x0: Disable the one-byte special token +0x1: Enable the one-byte special token + 21 + 1 + read-write + + + WRTRANCNT + Transfer count for write data +WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). +WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. +The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. +For TransMode 0, WrTranCnt must be equal to RdTranCnt. + 12 + 9 + read-write + + + TOKENVALUE + Token value (Master mode only) +The value of the one-byte special token following the address phase for SPI read transfers. +0x0: token value = 0x00 +0x1: token value = 0x69 + 11 + 1 + read-write + + + DUMMYCNT + Dummy data count. The actual dummy count is (DummyCnt +1). +The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) +The Data pins are put into the high impedance during the dummy data phase. +DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases. + 9 + 2 + read-write + + + RDTRANCNT + Transfer count for read data +RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). +RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. +The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. +For TransMode 0, WrTranCnt must equal RdTranCnt. + 0 + 9 + read-write + + + + + Cmd + Command Register + 0x24 + 32 + 0x00000000 + 0x000000FF + + + CMD + SPI Command + 0 + 8 + read-write + + + + + Addr + Address Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + SPI Address +(Master mode only) + 0 + 32 + read-write + + + + + Data + Data Register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + Data to transmit or the received data +For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. +For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. +The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. +If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset. + 0 + 32 + read-write + + + + + Ctrl + Control Register + 0x30 + 32 + 0x00000000 + 0x00FFFF1F + + + TXTHRES + Transmit (TX) FIFO Threshold +The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold. + 16 + 8 + read-write + + + RXTHRES + Receive (RX) FIFO Threshold +The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold. + 8 + 8 + read-write + + + TXDMAEN + TX DMA enable + 4 + 1 + read-write + + + RXDMAEN + RX DMA enable + 3 + 1 + read-write + + + TXFIFORST + Transmit FIFO reset +Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. + 2 + 1 + read-write + + + RXFIFORST + Receive FIFO reset +Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. + 1 + 1 + read-write + + + SPIRST + SPI reset +Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. + 0 + 1 + read-write + + + + + Status + Status Register + 0x34 + 32 + 0x00000000 + 0x33FFFF01 + + + TXNUM_7_6 + Number of valid entries in the Transmit FIFO + 28 + 2 + read-only + + + RXNUM_7_6 + Number of valid entries in the Receive FIFO + 24 + 2 + read-only + + + TXFULL + Transmit FIFO Full flag + 23 + 1 + read-only + + + TXEMPTY + Transmit FIFO Empty flag + 22 + 1 + read-only + + + TXNUM_5_0 + Number of valid entries in the Transmit FIFO + 16 + 6 + read-only + + + RXFULL + Receive FIFO Full flag + 15 + 1 + read-only + + + RXEMPTY + Receive FIFO Empty flag + 14 + 1 + read-only + + + RXNUM_5_0 + Number of valid entries in the Receive FIFO + 8 + 6 + read-only + + + SPIACTIVE + SPI register programming is in progress. +In master mode, SPIActive becomes 1 after the SPI command register is written and becomes 0 after the transfer is finished. +In slave mode, SPIActive becomes 1 after the SPI CS signal is asserted and becomes 0 after the SPI CS signal is deasserted. +Note that due to clock synchronization, it may take at most two spi_clock cycles for SPIActive to change when the corresponding condition happens. +Note this bit stays 0 when Direct IO Control or the memory-mapped interface is used. + 0 + 1 + read-only + + + + + IntrEn + Interrupt Enable Register + 0x38 + 32 + 0x00000000 + 0x0000003F + + + SLVCMDEN + Enable the Slave Command Interrupt. +Control whether interrupts are triggered whenever slave commands are received. +(Slave mode only) + 5 + 1 + read-write + + + ENDINTEN + Enable the End of SPI Transfer interrupt. +Control whether interrupts are triggered when SPI transfers end. +(In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.) + 4 + 1 + read-write + + + TXFIFOINTEN + Enable the SPI Transmit FIFO Threshold interrupt. +Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold. + 3 + 1 + read-write + + + RXFIFOINTEN + Enable the SPI Receive FIFO Threshold interrupt. +Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold. + 2 + 1 + read-write + + + TXFIFOURINTEN + Enable the SPI Transmit FIFO Underrun interrupt. +Control whether interrupts are triggered when the Transmit FIFO run out of data. +(Slave mode only) + 1 + 1 + read-write + + + RXFIFOORINTEN + Enable the SPI Receive FIFO Overrun interrupt. +Control whether interrupts are triggered when the Receive FIFO overflows. +(Slave mode only) + 0 + 1 + read-write + + + + + IntrSt + Interrupt Status Register + 0x3c + 32 + 0x00000000 + 0x0000003F + + + SLVCMDINT + Slave Command Interrupt. +This bit is set when Slave Command interrupts occur. +(Slave mode only) + 5 + 1 + write-only + + + ENDINT + End of SPI Transfer interrupt. +This bit is set when End of SPI Transfer interrupts occur. + 4 + 1 + write-only + + + TXFIFOINT + TX FIFO Threshold interrupt. +This bit is set when TX FIFO Threshold interrupts occur. + 3 + 1 + write-only + + + RXFIFOINT + RX FIFO Threshold interrupt. +This bit is set when RX FIFO Threshold interrupts occur. + 2 + 1 + write-only + + + TXFIFOURINT + TX FIFO Underrun interrupt. +This bit is set when TX FIFO Underrun interrupts occur. +(Slave mode only) + 1 + 1 + write-only + + + RXFIFOORINT + RX FIFO Overrun interrupt. +This bit is set when RX FIFO Overrun interrupts occur. +(Slave mode only) + 0 + 1 + write-only + + + + + Timing + Interface Timing Register + 0x40 + 32 + 0x00000000 + 0x00003FFF + + + CS2SCLK + The minimum time between the edges of SPI CS and the edges of SCLK. +SCLK_period * (CS2SCLK + 1) / 2 + 12 + 2 + read-write + + + CSHT + The minimum time that SPI CS should stay HIGH. +SCLK_period * (CSHT + 1) / 2 + 8 + 4 + read-write + + + SCLK_DIV + The clock frequency ratio between the clock source and SPI interface SCLK. +SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) +The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency. + 0 + 8 + read-write + + + + + SlvSt + Slave Status Register + 0x60 + 32 + 0x00000000 + 0x0007FFFF + + + UNDERRUN + Data underrun occurs in the last transaction + 18 + 1 + write-only + + + OVERRUN + Data overrun occurs in the last transaction + 17 + 1 + read-write + + + READY + Set this bit to indicate that the ATCSPI200 is ready for data transaction. +When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0. + 16 + 1 + read-write + + + USR_STATUS + User defined status flags + 0 + 16 + read-write + + + + + SlvDataCnt + Slave Data Count Register + 0x64 + 32 + 0x00000000 + 0x03FF03FF + + + WCNT + Slave transmitted data count + 16 + 10 + read-only + + + RCNT + Slave received data count + 0 + 10 + read-only + + + + + Config + Configuration Register + 0x7c + 32 + 0x00004311 + 0x000043FF + + + SLAVE + Support for SPI Slave mode + 14 + 1 + read-only + + + QUADSPI + Support for Quad I/O SPI + 9 + 1 + read-only + + + DUALSPI + Support for Dual I/O SPI + 8 + 1 + read-only + + + TXFIFOSIZE + Depth of TX FIFO +0x0: 2 words +0x1: 4 words +0x2: 8 words +0x3: 16 words +0x4: 32 words +0x5: 64 words +0x6: 128 words + 4 + 4 + read-only + + + RXFIFOSIZE + Depth of RX FIFO +0x0: 2 words +0x1: 4 words +0x2: 8 words +0x3: 16 words +0x4: 32 words +0x5: 64 words +0x6: 128 words + 0 + 4 + read-only + + + + + + + SPI1 + SPI1 + SPI + 0xf0034000 + + + SPI2 + SPI2 + SPI + 0xf0038000 + + + SPI3 + SPI3 + SPI + 0xf003c000 + + + UART0 + UART0 + UART + 0xf0040000 + + 0x4 + 0x3c + registers + + + + IDLE_CFG + Idle Configuration Register + 0x4 + 32 + 0x00000000 + 0x000003FF + + + RX_IDLE_COND + IDLE Detection Condition +0 - Treat as idle if RX pin is logic one +1 - Treat as idle if UART state machine state is idle + 9 + 1 + read-write + + + RX_IDLE_EN + UART Idle Detect Enable +0 - Disable +1 - Enable +it should be enabled if enable address match feature + 8 + 1 + read-write + + + RX_IDLE_THR + Threshold for UART Receive Idle detection (in terms of bits) + 0 + 8 + read-write + + + + + Cfg + Configuration Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + FIFOSIZE + The depth of RXFIFO and TXFIFO +0: 16-byte FIFO +1: 32-byte FIFO +2: 64-byte FIFO +3: 128-byte FIFO + 0 + 2 + read-only + + + + + OSCR + Over Sample Control Register + 0x14 + 32 + 0x00000010 + 0x0000001F + + + OSC + Over-sample control +The value must be an even number; any odd value +writes to this field will be converted to an even value. +OSC=0: reserved +OSC<=8: The over-sample ratio is 8 +8 < OSC< 32: The over sample ratio is OSC + 0 + 5 + read-write + + + + + RBR + Receiver Buffer Register (when DLAB = 0) + UNION_20 + 0x20 + 32 + 0x00000000 + 0x000000FF + + + RBR + Receive data read port + 0 + 8 + read-only + + + + + THR + Transmitter Holding Register (when DLAB = 0) + UNION_20 + 0x20 + 32 + 0x00000000 + 0x000000FF + + + THR + Transmit data write port + 0 + 8 + write-only + + + + + DLL + Divisor Latch LSB (when DLAB = 1) + UNION_20 + 0x20 + 32 + 0x00000001 + 0x000000FF + + + DLL + Least significant byte of the Divisor Latch + 0 + 8 + read-write + + + + + IER + Interrupt Enable Register (when DLAB = 0) + UNION_24 + 0x24 + 32 + 0x00000000 + 0x8000000F + + + ERXIDLE + Enable Receive Idle interrupt +0 - Disable Idle interrupt +1 - Enable Idle interrupt + 31 + 1 + read-write + + + EMSI + Enable modem status interrupt +The interrupt asserts when the status of one of the +following occurs: +The status of modem_rin, modem_dcdn, +modem_dsrn or modem_ctsn (If the auto-cts mode is +disabled) has been changed. +If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), +modem_ctsn would be used to control the transmitter. + 3 + 1 + read-write + + + ELSI + Enable receiver line status interrupt + 2 + 1 + read-write + + + ETHEI + Enable transmitter holding register interrupt + 1 + 1 + read-write + + + ERBI + Enable received data available interrupt and the +character timeout interrupt +0: Disable +1: Enable + 0 + 1 + read-write + + + + + DLM + Divisor Latch MSB (when DLAB = 1) + UNION_24 + 0x24 + 32 + 0x00000000 + 0x000000FF + + + DLM + Most significant byte of the Divisor Latch + 0 + 8 + read-write + + + + + IIR + Interrupt Identification Register + UNION_28 + 0x28 + 32 + 0x00000001 + 0x800000CF + + + RXIDLE_FLAG + UART IDLE Flag +0 - UART is busy +1 - UART is idle +NOTE: when write one to clear this bit, avoid changging FCR register since it's same address as IIR + 31 + 1 + write-only + + + FIFOED + FIFOs enabled +These two bits are 1 when bit 0 of the FIFO Control +Register (FIFOE) is set to 1. + 6 + 2 + read-only + + + INTRID + Interrupt ID, see IIR2 for detail decoding + 0 + 4 + read-only + + + + + FCR + FIFO Control Register + UNION_28 + 0x28 + 32 + 0x00000000 + 0x000000FF + + + RFIFOT + Receiver FIFO trigger level + 6 + 2 + write-only + + + TFIFOT + Transmitter FIFO trigger level + 4 + 2 + write-only + + + DMAE + DMA enable +0: Disable +1: Enable + 3 + 1 + write-only + + + TFIFORST + Transmitter FIFO reset +Write 1 to clear all bytes in the TXFIFO and resets its +counter. The Transmitter Shift Register is not cleared. +This bit will automatically be cleared. + 2 + 1 + write-only + + + RFIFORST + Receiver FIFO reset +Write 1 to clear all bytes in the RXFIFO and resets its +counter. The Receiver Shift Register is not cleared. +This bit will automatically be cleared. + 1 + 1 + write-only + + + FIFOE + FIFO enable +Write 1 to enable both the transmitter and receiver +FIFOs. +The FIFOs are reset when the value of this bit toggles. + 0 + 1 + write-only + + + + + LCR + Line Control Register + 0x2c + 32 + 0x00000000 + 0x000000FF + + + DLAB + Divisor latch access bit + 7 + 1 + read-write + + + BC + Break control + 6 + 1 + read-write + + + SPS + Stick parity +1: Parity bit is constant 0 or 1, depending on bit4 (EPS). +0: Disable the sticky bit parity. + 5 + 1 + read-write + + + EPS + Even parity select +1: Even parity (an even number of logic-1 is in the data +and parity bits) +0: Old parity. + 4 + 1 + read-write + + + PEN + Parity enable +When this bit is set, a parity bit is generated in +transmitted data before the first STOP bit and the parity +bit would be checked for the received data. + 3 + 1 + read-write + + + STB + Number of STOP bits +0: 1 bits +1: The number of STOP bit is based on the WLS setting +When WLS = 0, STOP bit is 1.5 bits +When WLS = 1, 2, 3, STOP bit is 2 bits + 2 + 1 + read-write + + + WLS + Word length setting +0: 5 bits +1: 6 bits +2: 7 bits +3: 8 bits + 0 + 2 + read-write + + + + + MCR + Modem Control Register ( + 0x30 + 32 + 0x00000000 + 0x00000032 + + + AFE + Auto flow control enable +0: Disable +1: The auto-CTS and auto-RTS setting is based on the +RTS bit setting: +When RTS = 0, auto-CTS only +When RTS = 1, auto-CTS and auto-RTS + 5 + 1 + read-write + + + LOOP + Enable loopback mode +0: Disable +1: Enable + 4 + 1 + read-write + + + RTS + Request to send +This bit controls the modem_rtsn output. +0: The modem_rtsn output signal will be driven HIGH +1: The modem_rtsn output signal will be driven LOW + 1 + 1 + read-write + + + + + LSR + Line Status Register + 0x34 + 32 + 0x00000000 + 0x000000FF + + + ERRF + Error in RXFIFO +In the FIFO mode, this bit is set when there is at least +one parity error, framing error, or line break +associated with data in the RXFIFO. It is cleared when +this register is read and there is no more error for the +rest of data in the RXFIFO. + 7 + 1 + read-only + + + TEMT + Transmitter empty +This bit is 1 when the THR (TXFIFO in the FIFO +mode) and the Transmitter Shift Register (TSR) are +both empty. Otherwise, it is zero. + 6 + 1 + read-only + + + THRE + Transmitter Holding Register empty +This bit is 1 when the THR (TXFIFO in the FIFO +mode) is empty. Otherwise, it is zero. +If the THRE interrupt is enabled, an interrupt is +triggered when THRE becomes 1. + 5 + 1 + read-only + + + LBREAK + Line break +This bit is set when the uart_sin input signal was held +LOWfor longer than the time for a full-word +transmission. A full-word transmission is the +transmission of the START, data, parity, and STOP +bits. It is cleared when this register is read. +In the FIFO mode, this bit indicates the line break for +the received data at the top of the RXFIFO. + 4 + 1 + read-only + + + FE + Framing error +This bit is set when the received STOP bit is not +HIGH. It is cleared when this register is read. +In the FIFO mode, this bit indicates the framing error +for the received data at the top of the RXFIFO. + 3 + 1 + read-only + + + PE + Parity error +This bit is set when the received parity does not match +with the parity selected in the LCR[5:4]. It is cleared +when this register is read. +In the FIFO mode, this bit indicates the parity error +for the received data at the top of the RXFIFO. + 2 + 1 + read-only + + + OE + Overrun error +This bit indicates that data in the Receiver Buffer +Register (RBR) is overrun. + 1 + 1 + read-only + + + DR + Data ready. +This bit is set when there are incoming received data +in the Receiver Buffer Register (RBR). It is cleared +when all of the received data are read. + 0 + 1 + read-only + + + + + MSR + Modem Status Register + 0x38 + 32 + 0x00000000 + 0x00000011 + + + CTS + Clear to send +0: The modem_ctsn input signal is HIGH. +1: The modem_ctsn input signal is LOW. + 4 + 1 + read-only + + + DCTS + Delta clear to send +This bit is set when the state of the modem_ctsn input +signal has been changed since the last time this +register is read. + 0 + 1 + read-only + + + + + GPR + GPR Register + 0x3c + 32 + 0x00000000 + 0x000000FF + + + DATA + A one-byte storage register + 0 + 8 + read-write + + + + + + + UART1 + UART1 + UART + 0xf0044000 + + + UART2 + UART2 + UART + 0xf0048000 + + + UART3 + UART3 + UART + 0xf004c000 + + + UART4 + UART4 + UART + 0xf0050000 + + + UART5 + UART5 + UART + 0xf0054000 + + + UART6 + UART6 + UART + 0xf0058000 + + + UART7 + UART7 + UART + 0xf005c000 + + + PUART + PUART + UART + 0xf40e4000 + + + MCAN0 + MCAN0 + MCAN + 0xf0080000 + + 0x4 + 0x29fc + registers + + + + ENDN + endian register + 0x4 + 32 + 0x87654321 + 0xFFFFFFFF + + + EVT + Endianness Test Value +The endianness test value is 0x87654321. + 0 + 32 + read-only + + + + + DBTP + data bit timing and prescaler, writeable when CCCR.CCE and CCCR.INT are set + 0xc + 32 + 0x00000A33 + 0x009F1FFF + + + TDC + transmitter delay compensation enable +0= Transmitter Delay Compensation disabled +1= Transmitter Delay Compensation enabled + 23 + 1 + read-write + + + DBRP + Data Bit Rate Prescaler +The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. +When TDC = ‘1’, the range is limited to 0,1. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + 16 + 5 + read-write + + + DTSEG1 + Data time segment before sample point +Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. + 8 + 5 + read-write + + + DTSEG2 + Data time segment after sample point +Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. + 4 + 4 + read-write + + + DSJW + Data (Re)Synchronization Jump Width +Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + 0 + 4 + read-write + + + + + TEST + test register + 0x10 + 32 + 0x00000000 + 0x003F3FF0 + + + SVAL + Started Valid +0= Value of TXBNS not valid +1= Value of TXBNS valid + 21 + 1 + read-only + + + TXBNS + Tx Buffer Number Started +Tx Buffer number of message whose transmission was started last. Valid when SVAL is set. Valid values are 0 to 31. + 16 + 5 + read-only + + + PVAL + Prepared Valid +0= Value of TXBNP not valid +1= Value of TXBNP valid + 13 + 1 + read-only + + + TXBNP + Tx Buffer Number Prepared +Tx Buffer number of message that is ready for transmission. Valid when PVAL is set.Valid values are 0 to 31. + 8 + 5 + read-only + + + RX + Receive Pin +Monitors the actual value of pin m_can_rx +0= The CAN bus is dominant (m_can_rx = ‘0’) +1= The CAN bus is recessive (m_can_rx = ‘1’) + 7 + 1 + read-only + + + TX + Control of Transmit Pin +00 Reset value, m_can_tx controlled by the CAN Core, updated at the end of the CAN bit time +01 Sample Point can be monitored at pin m_can_tx +10 Dominant (‘0’) level at pin m_can_tx +11 Recessive (‘1’) at pin m_can_tx + 5 + 2 + read-write + + + LBCK + Loop Back Mode +0= Reset value, Loop Back Mode is disabled +1= Loop Back Mode is enabled + 4 + 1 + read-write + + + + + RWD + ram watchdog + 0x14 + 32 + 0x00000000 + 0x0000FFFF + + + WDV + Watchdog Value +Actual Message RAM Watchdog Counter Value. + 8 + 8 + read-only + + + WDC + Watchdog Configuration +Start value of the Message RAM Watchdog Counter. With the reset value of “00” the counter is disabled. + 0 + 8 + read-write + + + + + CCCR + CC control register + 0x18 + 32 + 0x00000001 + 0x0000FFFF + + + NISO + Non ISO Operation +If this bit is set, the M_CAN uses the CAN FD frame format as specified by the Bosch CAN FD +Specification V1.0. +0= CAN FD frame format according to ISO 11898-1:2015 +1= CAN FD frame format according to Bosch CAN FD Specification V1.0 +Note: When the generic parameter iso_only_g is set to ‘1’ in hardware synthesis, this bit becomes reserved and is read as ‘0’. The M_CAN always operates with the CAN FD frame format according to ISO 11898-1:2015. + 15 + 1 + read-write + + + TXP + Transmit Pause +If this bit is set, the M_CAN pauses for two CAN bit times before starting the next transmission after +itself has successfully transmitted a frame (see Section 3.5). +0= Transmit pause disabled +1= Transmit pause enabled + 14 + 1 + read-write + + + EFBI + Edge Filtering during Bus Integration +0= Edge filtering disabled +1= Two consecutive dominant tq required to detect an edge for hard synchronization + 13 + 1 + read-write + + + PXHD + Protocol Exception Handling Disable +0= Protocol exception handling enabled +1= Protocol exception handling disabled +Note: When protocol exception handling is disabled, the M_CAN will transmit an error frame when it detects a protocol exception condition. + 12 + 1 + read-write + + + WMM + Wide Message Marker +Enables the use of 16-bit Wide Message Markers. When 16-bit Wide Message Markers are used (WMM = ‘1’), 16-bit internal timestamping is disabled for the Tx Event FIFO. +0= 8-bit Message Marker used +1= 16-bit Message Marker used, replacing 16-bit timestamps in Tx Event FIFO + 11 + 1 + read-write + + + UTSU + Use Timestamping Unit +When UTSU is set, 16-bit Wide Message Markers are also enabled regardless of the value of WMM. +0= Internal time stamping +1= External time stamping by TSU +Note: When generic parameter connected_tsu_g = ‘0’, there is no TSU connected to the M_CAN. +In this case bit UTSU is fixed to zero by synthesis. + 10 + 1 + read-write + + + BRSE + Bit Rate Switch Enable +0= Bit rate switching for transmissions disabled +1= Bit rate switching for transmissions enabled +Note: When CAN FD operation is disabled FDOE = ‘0’, BRSE is not evaluated. + 9 + 1 + read-write + + + FDOE + FD Operation Enable +0= FD operation disabled +1= FD operation enabled + 8 + 1 + read-write + + + TEST + Test Mode Enable +0= Normal operation, register TEST holds reset values +1= Test Mode, write access to register TEST enabled + 7 + 1 + read-write + + + DAR + Disable Automatic Retransmission +0= Automatic retransmission of messages not transmitted successfully enabled +1= Automatic retransmission disabled + 6 + 1 + read-write + + + MON + Bus Monitoring Mode +Bit MON can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. +0= Bus Monitoring Mode is disabled +1= Bus Monitoring Mode is enabled + 5 + 1 + read-write + + + CSR + Clock Stop Request +0= No clock stop is requested +1= Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle. + 4 + 1 + read-write + + + CSA + Clock Stop Acknowledge +0= No clock stop acknowledged +1= M_CAN may be set in power down by stopping m_can_hclk and m_can_cclk + 3 + 1 + read-only + + + ASM + Restricted Operation Mode +Bit ASM can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. For a description of the Restricted Operation Mode see Section 3.1.5. +0= Normal CAN operation +1= Restricted Operation Mode active + 2 + 1 + read-write + + + CCE + Configuration Change Enable +0= The CPU has no write access to the protected configuration registers +1= The CPU has write access to the protected configuration registers (while CCCR.INIT = ‘1’) + 1 + 1 + read-write + + + INIT + Initialization +0= Normal Operation +1= Initialization is started + 0 + 1 + read-write + + + + + NBTP + nominal bit timing and prescaler register + 0x1c + 32 + 0x06000A03 + 0xFFFFFF7F + + + NSJW + Nominal (Re)Synchronization Jump Width +Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + 25 + 7 + read-write + + + NBRP + Nominal Bit Rate Prescaler +The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is +such that one more than the value programmed here is used. + 16 + 9 + read-write + + + NTSEG1 + Nominal Time segment before sample point +Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. + 8 + 8 + read-write + + + NTSEG2 + Nominal Time segment after sample point +Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. + 0 + 7 + read-write + + + + + TSCC + timestamp counter configuration + 0x20 + 32 + 0x00000000 + 0x000F0003 + + + TCP + Timestamp Counter Prescaler +Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1…16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + 16 + 4 + read-write + + + TSS + timestamp Select +00= Timestamp counter value always 0x0000 +01= Timestamp counter value incremented according to TCP +10= External timestamp counter value used +11= Same as “00” + 0 + 2 + read-write + + + + + TSCV + timestamp counter value + 0x24 + 32 + 0x00000000 + 0x0000FFFF + + + TSC + Timestamp Counter +The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx).When TSCC.TSS = “01”, the Timestamp Counter is incremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. +A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = “10”, TSC reflects the external Timestamp Counter value. A write access has no impact. + 0 + 16 + read-only + + + + + TOCC + timeout counter configuration + 0x28 + 32 + 0xFFFF0000 + 0xFFFF0007 + + + TOP + Timeout Period +Start value of the Timeout Counter (down-counter). Configures the Timeout Period. + 16 + 16 + read-write + + + TOS + Timeout Select +When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. +When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. +00= Continuous operation +01= Timeout controlled by Tx Event FIFO +10= Timeout controlled by Rx FIFO 0 +11= Timeout controlled by Rx FIFO 1 + 1 + 2 + read-write + + + RP + Enable Timeout Counter +0= Timeout Counter disabled +1= Timeout Counter enabled + 0 + 1 + read-write + + + + + TOCV + timeout counter value + 0x2c + 32 + 0x0000FFFF + 0x0000FFFF + + + TOC + Timeout Counter +The Timeout Counter is decremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. +When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. +Note: Byte access: when TOCC.TOS = “00，writing one of the register bytes 3/2/1/0 will preset the Timeout Counter. + 0 + 16 + read-only + + + + + ECR + error counter register + 0x40 + 32 + 0x00000000 + 0x00FFFFFF + + + CEL + CAN Error Logging +The counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. +The counter is also incremented when the Bus_Off limit is reached. It is not incremented when only RP is set without changing REC. The increment of CEL follows after the increment of REC or TEC. +The counter is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. +Note: Byte access: Reading byte 2 will reset CEL to zero, reading bytes 3/1/0 has no impact. + 16 + 8 + read-only + + + RP + Receive Error Passive +0= The Receive Error Counter is below the error passive level of 128 +1= The Receive Error Counter has reached the error passive level of 128 + 15 + 1 + read-only + + + REC + Receive Error Counter +Actual state of the Receive Error Counter, values between 0 and 127 + 8 + 7 + read-only + + + TEC + Transmit Error Counter +Actual state of the Transmit Error Counter, values between 0 and 255 +Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented. + 0 + 8 + read-only + + + + + PSR + protocol status register + 0x44 + 32 + 0x00000707 + 0x007F7FFF + + + TDCV + Transmitter Delay Compensation Value +Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. +The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. + 16 + 7 + read-only + + + PXE + Protocol Exception Event +0= No protocol exception event occurred since last read access +1= Protocol exception event occurred +Note: Byte access: Reading byte 0 will reset PXE, reading bytes 3/2/1 has no impact. + 14 + 1 + read-only + + + RFDF + Received a CAN FD Message +This bit is set independent of acceptance filtering. +0= Since this bit was reset by the CPU, no CAN FD message has been received +1= Message in CAN FD format with FDF flag set has been received +Note: Byte access: Reading byte 0 will reset RFDF, reading bytes 3/2/1 has no impact. + 13 + 1 + read-only + + + RBRS + BRS flag of last received CAN FD Message +This bit is set together with RFDF, independent of acceptance filtering. +0= Last received CAN FD message did not have its BRS flag set +1= Last received CAN FD message had its BRS flag set +Note: Byte access: Reading byte 0 will reset RBRS, reading bytes 3/2/1 has no impact. + 12 + 1 + read-only + + + RESI + ESI flag of last received CAN FD Message +This bit is set together with RFDF, independent of acceptance filtering. +0= Last received CAN FD message did not have its ESI flag set +1= Last received CAN FD message had its ESI flag set +Note: Byte access: Reading byte 0 will reset RESI, reading bytes 3/2/1 has no impact. + 11 + 1 + read-only + + + DLEC + Data Phase Last Error Code +Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set.Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with +its BRS flag set has been transferred (reception or transmission) without error. +Note: Byte access: Reading byte 0 will set DLEC to “111”, reading bytes 3/2/1 has no impact. + 8 + 3 + read-only + + + BO + Bus_Off Status +0= The M_CAN is not Bus_Off +1= The M_CAN is in Bus_Off state + 7 + 1 + read-only + + + EW + Warning Status +0= Both error counters are below the Error_Warning limit of 96 +1= At least one of error counter has reached the Error_Warning limit of 96 + 6 + 1 + read-only + + + EP + Error Passive +0= The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected +1= The M_CAN is in the Error_Passive state + 5 + 1 + read-only + + + ACT + Activity +Monitors the module’s CAN communication state. +00= Synchronizing - node is synchronizing on CAN communication +01= Idle - node is neither receiver nor transmitter +10= Receiver - node is operating as receiver +11= Transmitter - node is operating as transmitter +Note: ACT is set to “00” by a Protocol Exception Event. + 3 + 2 + read-only + + + LEC + Last Error Code +The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to ‘0’when a message has been transferred (reception or transmission) without error. +0= No Error: No error occurred since LEC has been reset by successful reception or transmission. +1= Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. +2= Form Error: A fixed format part of a received frame has the wrong format. +3= AckError: The message transmitted by the M_CAN was not acknowledged by another node. +4= Bit1Error: During the transmission of a message (with the exception of the arbitration field), +the device wanted to send a recessive level (bit of logical value ‘1’), but the monitored bus +value was dominant. +5= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value‘0’), but the monitored bus value was recessive. + During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at +dominant or continuously disturbed). +6= CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. +7= NoChange: Any read access to the Protocol Status Register re-initializes the LEC to ‘7’. When the LEC shows the value ‘7’, no CAN bus event was detected since the last CPU read access to the Protocol Status Register. +Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error. +Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord,stopping all bus activities. + Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. +At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, +enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences. +Note: Byte access: Reading byte 0 will set LEC to “111”, reading bytes 3/2/1 has no impact. + 0 + 3 + read-only + + + + + TDCR + transmitter delay compensation + 0x48 + 32 + 0x00000000 + 0x00007F7F + + + TDCO + Transmitter Delay Compensation SSP Offset +Offset value defining the distance between the measured delay from m_can_tx to m_can_rx and the secondary sample point. Valid values are 0 to 127 mtq. + 8 + 7 + read-write + + + TDCF + Transmitter Delay Compensation Filter Window Length +Defines the minimum value for the SSP position, dominant edges on m_can_rx that would result in an earlier SSP position are ignored for transmitter delay measurement. +The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq. + 0 + 7 + read-write + + + + + IR + interrupt register + 0x50 + 32 + 0x00000000 + 0x3FFFFFFF + + + ARA + Access to Reserved Address +0= No access to reserved address occurred +1= Access to reserved address occurred + 29 + 1 + read-write + + + PED + Protocol Error in Data Phase (Data Bit Time is used) +0= No protocol error in data phase +1= Protocol error in data phase detected (PSR.DLEC ≠ 0,7) + 28 + 1 + read-write + + + PEA + Protocol Error in Arbitration Phase (Nominal Bit Time is used) +0= No protocol error in arbitration phase +1= Protocol error in arbitration phase detected (PSR.LEC ≠ 0,7) + 27 + 1 + read-write + + + WDI + Watchdog Interrupt +0= No Message RAM Watchdog event occurred +1= Message RAM Watchdog event due to missing READY + 26 + 1 + read-write + + + BO + Bus_Off Status +0= Bus_Off status unchanged +1= Bus_Off status changed + 25 + 1 + read-write + + + EW + Warning Status +0= Error_Warning status unchanged +1= Error_Warning status changed + 24 + 1 + read-write + + + EP + Error Passive +0= Error_Passive status unchanged +1= Error_Passive status changed + 23 + 1 + read-write + + + ELO + Error Logging Overflow +0= CAN Error Logging Counter did not overflow +1= Overflow of CAN Error Logging Counter occurred + 22 + 1 + read-write + + + BEU + Bit Error Uncorrected +Message RAM bit error detected, uncorrected. Controlled by input signal m_can_aeim_berr[1] generated by an optional external parity / ECC logic attached to the Message RAM. +An uncorrected Message RAM bit error sets CCCR.INIT to ‘1’. This is done to avoid transmission of corrupted data. +0= No bit error detected when reading from Message RAM +1= Bit error detected, uncorrected (e.g. parity logic) + 21 + 1 + read-write + + + BEC + Bit Error Corrected +Message RAM bit error detected and corrected. Controlled by input signal m_can_aeim_berr[0] generated by an optional external parity / ECC logic attached to the Message RAM. +0= No bit error detected when reading from Message RAM +1= Bit error detected and corrected (e.g. ECC) + 20 + 1 + read-write + + + DRX + Message stored to Dedicated Rx Buffer +The flag is set whenever a received message has been stored into a dedicated Rx Buffer. +0= No Rx Buffer updated +1= At least one received message stored into an Rx Buffer + 19 + 1 + read-write + + + TOO + Timeout Occurred +0= No timeout +1= Timeout reached + 18 + 1 + read-write + + + MRAF + Message RAM Access Failure +The flag is set, when the Rx Handler +.has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message +storage is aborted and the Rx Handler starts processing of the following message. +.was not able to write a message to the Message RAM. In this case message storage is aborted. +In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. +The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the +M_CAN is switched into Restricted Operation Mode (see Section 3.1.5). To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM. +0= No Message RAM access failure occurred +1= Message RAM access failure occurred + 17 + 1 + read-write + + + TSW + Timestamp Wraparound +0= No timestamp counter wrap-around +1= Timestamp counter wrapped around + 16 + 1 + read-write + + + TEFL + Tx Event FIFO Element Lost +0= No Tx Event FIFO element lost +1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero + 15 + 1 + read-write + + + TEFF + Tx Event FIFO Full +0= Tx Event FIFO not full +1= Tx Event FIFO full + 14 + 1 + read-write + + + TEFW + Tx Event FIFO Watermark Reached +0= Tx Event FIFO fill level below watermark +1= Tx Event FIFO fill level reached watermark + 13 + 1 + read-write + + + TEFN + Tx Event FIFO New Entry +0= Tx Event FIFO unchanged +1= Tx Handler wrote Tx Event FIFO element + 12 + 1 + read-write + + + TFE + Tx FIFO Empty +0= Tx FIFO non-empty +1= Tx FIFO empty + 11 + 1 + read-write + + + TCF + Transmission Cancellation Finished +0= No transmission cancellation finished +1= Transmission cancellation finished + 10 + 1 + read-write + + + TC + Transmission Completed +0= No transmission completed +1= Transmission completed + 9 + 1 + read-write + + + HPM + High Priority Message +0= No high priority message received +1= High priority message received + 8 + 1 + read-write + + + RF1L + Rx FIFO 1 Message Lost +0= No Rx FIFO 1 message lost +1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero + 7 + 1 + read-write + + + RF1F + Rx FIFO 1 Full +0= Rx FIFO 1 not full +1= Rx FIFO 1 full + 6 + 1 + read-write + + + RF1W + Rx FIFO 1 Watermark Reached +0= Rx FIFO 1 fill level below watermark +1= Rx FIFO 1 fill level reached watermark + 5 + 1 + read-write + + + RF1N + Rx FIFO 1 New Message +0= No new message written to Rx FIFO 1 +1= New message written to Rx FIFO 1 + 4 + 1 + read-write + + + RF0L + Rx FIFO 0 Message Lost +0= No Rx FIFO 0 message lost +1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero + 3 + 1 + read-write + + + RF0F + Rx FIFO 0 Full +0= Rx FIFO 0 not full +1= Rx FIFO 0 full + 2 + 1 + read-write + + + RF0W + Rx FIFO 0 Watermark Reached +0= Rx FIFO 0 fill level below watermark +1= Rx FIFO 0 fill level reached watermark + 1 + 1 + read-write + + + RF0N + Rx FIFO 0 New Message +0= No new message written to Rx FIFO 0 +1= New message written to Rx FIFO 0 + 0 + 1 + read-write + + + + + IE + interrupt enable + 0x54 + 32 + 0x00000000 + 0x3FFFFFFF + + + ARAE + Access to Reserved Address Enable + 29 + 1 + read-write + + + PEDE + Protocol Error in Data Phase Enable + 28 + 1 + read-write + + + PEAE + Protocol Error in Arbitration Phase Enable + 27 + 1 + read-write + + + WDIE + Watchdog Interrupt Enable + 26 + 1 + read-write + + + BOE + Bus_Off Status Interrupt Enable + 25 + 1 + read-write + + + EWE + Warning Status Interrupt Enable + 24 + 1 + read-write + + + EPE + Error Passive Interrupt Enable + 23 + 1 + read-write + + + ELOE + Error Logging Overflow Interrupt Enable + 22 + 1 + read-write + + + BEUE + Bit Error Uncorrected Interrupt Enable + 21 + 1 + read-write + + + BECE + Bit Error Corrected Interrupt Enable + 20 + 1 + read-write + + + DRXE + Message stored to Dedicated Rx Buffer Interrupt Enable + 19 + 1 + read-write + + + TOOE + Timeout Occurred Interrupt Enable + 18 + 1 + read-write + + + MRAFE + Message RAM Access Failure Interrupt Enable + 17 + 1 + read-write + + + TSWE + Timestamp Wraparound Interrupt Enable + 16 + 1 + read-write + + + TEFLE + Tx Event FIFO Event Lost Interrupt Enable + 15 + 1 + read-write + + + TEFFE + Tx Event FIFO Full Interrupt Enable + 14 + 1 + read-write + + + TEFWE + Tx Event FIFO Watermark Reached Interrupt Enable + 13 + 1 + read-write + + + TEFNE + Tx Event FIFO New Entry Interrupt Enable + 12 + 1 + read-write + + + TFEE + Tx FIFO Empty Interrupt Enable + 11 + 1 + read-write + + + TCFE + Transmission Cancellation Finished Interrupt Enable + 10 + 1 + read-write + + + TCE + Transmission Completed Interrupt Enable + 9 + 1 + read-write + + + HPME + High Priority Message Interrupt Enable + 8 + 1 + read-write + + + RF1LE + Rx FIFO 1 Message Lost Interrupt Enable + 7 + 1 + read-write + + + RF1FE + Rx FIFO 1 Full Interrupt Enable + 6 + 1 + read-write + + + RF1WE + Rx FIFO 1 Watermark Reached Interrupt Enable + 5 + 1 + read-write + + + RF1NE + Rx FIFO 1 New Message Interrupt Enable + 4 + 1 + read-write + + + RF0LE + Rx FIFO 0 Message Lost Interrupt Enable + 3 + 1 + read-write + + + RF0FE + Rx FIFO 0 Full Interrupt Enable + 2 + 1 + read-write + + + RF0WE + Rx FIFO 0 Watermark Reached Interrupt Enable + 1 + 1 + read-write + + + RF0NE + Rx FIFO 0 New Message Interrupt Enable + 0 + 1 + read-write + + + + + ILS + interrupt line select + 0x58 + 32 + 0x00000000 + 0x3FFFFFFF + + + ARAL + Access to Reserved Address Line + 29 + 1 + read-write + + + PEDL + Protocol Error in Data Phase Line + 28 + 1 + read-write + + + PEAL + Protocol Error in Arbitration Phase Line + 27 + 1 + read-write + + + WDIL + Watchdog Interrupt Line + 26 + 1 + read-write + + + BOL + Bus_Off Status Interrupt Line + 25 + 1 + read-write + + + EWL + Warning Status Interrupt Line + 24 + 1 + read-write + + + EPL + Error Passive Interrupt Line + 23 + 1 + read-write + + + ELOL + Error Logging Overflow Interrupt Line + 22 + 1 + read-write + + + BEUL + Bit Error Uncorrected Interrupt Line + 21 + 1 + read-write + + + BECL + Bit Error Corrected Interrupt Line + 20 + 1 + read-write + + + DRXL + Message stored to Dedicated Rx Buffer Interrupt Line + 19 + 1 + read-write + + + TOOL + Timeout Occurred Interrupt Line + 18 + 1 + read-write + + + MRAFL + Message RAM Access Failure Interrupt Line + 17 + 1 + read-write + + + TSWL + Timestamp Wraparound Interrupt Line + 16 + 1 + read-write + + + TEFLL + Tx Event FIFO Event Lost Interrupt Line + 15 + 1 + read-write + + + TEFFL + Tx Event FIFO Full Interrupt Line + 14 + 1 + read-write + + + TEFWL + Tx Event FIFO Watermark Reached Interrupt Line + 13 + 1 + read-write + + + TEFNL + Tx Event FIFO New Entry Interrupt Line + 12 + 1 + read-write + + + TFEL + Tx FIFO Empty Interrupt Line + 11 + 1 + read-write + + + TCFL + Transmission Cancellation Finished Interrupt Line + 10 + 1 + read-write + + + TCL + Transmission Completed Interrupt Line + 9 + 1 + read-write + + + HPML + High Priority Message Interrupt Line + 8 + 1 + read-write + + + RF1LL + Rx FIFO 1 Message Lost Interrupt Line + 7 + 1 + read-write + + + RF1FL + Rx FIFO 1 Full Interrupt Line + 6 + 1 + read-write + + + RF1WL + Rx FIFO 1 Watermark Reached Interrupt Line + 5 + 1 + read-write + + + RF1NL + Rx FIFO 1 New Message Interrupt Line + 4 + 1 + read-write + + + RF0LL + Rx FIFO 0 Message Lost Interrupt Line + 3 + 1 + read-write + + + RF0FL + Rx FIFO 0 Full Interrupt Line + 2 + 1 + read-write + + + RF0WL + Rx FIFO 0 Watermark Reached Interrupt Line + 1 + 1 + read-write + + + RF0NL + Rx FIFO 0 New Message Interrupt Line + 0 + 1 + read-write + + + + + ILE + interrupt line enable + 0x5c + 32 + 0x00000000 + 0x00000003 + + + EINT1 + Enable Interrupt Line 1 +0= Interrupt line m_can_int1 disabled +1= Interrupt line m_can_int1 enabled + 1 + 1 + read-write + + + EINT0 + Enable Interrupt Line 0 +0= Interrupt line m_can_int0 disabled +1= Interrupt line m_can_int0 enabled + 0 + 1 + read-write + + + + + GFC + global filter configuration + 0x80 + 32 + 0x00000000 + 0x0000003F + + + ANFS + Accept Non-matching Frames Standard +Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. +00= Accept in Rx FIFO 0 +01= Accept in Rx FIFO 1 +10= Reject +11= Reject + 4 + 2 + read-write + + + ANFE + Accept Non-matching Frames Extended +Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. +00= Accept in Rx FIFO 0 +01= Accept in Rx FIFO 1 +10= Reject +11= Reject + 2 + 2 + read-write + + + RRFS + Reject Remote Frames Standard +0= Filter remote frames with 11-bit standard IDs +1= Reject all remote frames with 11-bit standard IDs + 1 + 1 + read-write + + + RRFE + Reject Remote Frames Extended +0= Filter remote frames with 29-bit extended IDs +1= Reject all remote frames with 29-bit extended IDs + 0 + 1 + read-write + + + + + SIDFC + standard ID filter configuration + 0x84 + 32 + 0x00000000 + 0x00FFFFFC + + + LSS + List Size Standard +0= No standard Message ID filter +1-128= Number of standard Message ID filter elements +>128= Values greater than 128 are interpreted as 128 + 16 + 8 + read-write + + + FLSSA + Filter List Standard Start Address +Start address of standard Message ID filter list (32-bit word address) + 2 + 14 + read-write + + + + + XIDFC + extended ID filter configuration + 0x88 + 32 + 0x00000000 + 0x007FFFFC + + + LSE + List Size Extended +0= No extended Message ID filter +1-64= Number of extended Message ID filter elements +>64= Values greater than 64 are interpreted as 64 + 16 + 7 + read-write + + + FLESA + Filter List Extended Start Address +Start address of extended Message ID filter list (32-bit word address). + 2 + 14 + read-write + + + + + XIDAM + extended id and mask + 0x90 + 32 + 0x1FFFFFFF + 0x1FFFFFFF + + + EIDM + Extended ID Mask +For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. + Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active. + 0 + 29 + read-write + + + + + HPMS + high priority message status + 0x94 + 32 + 0x00000000 + 0x0000FFFF + + + FLST + Filter List +Indicates the filter list of the matching filter element. +0= Standard Filter List +1= Extended Filter List + 15 + 1 + read-only + + + FIDX + Filter Index +Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1. + 8 + 7 + read-only + + + MSI + Message Storage Indicator +00= No FIFO selected +01= FIFO message lost +10= Message stored in FIFO 0 +11= Message stored in FIFO 1 + 6 + 2 + read-only + + + BIDX + Buffer Index +Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = ‘1’. + 0 + 6 + read-only + + + + + NDAT1 + new data1 + 0x98 + 32 + 0x00000000 + 0xFFFFFFFF + + + ND1 + New Data[31:0] +The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. +The flags remain set until the Host clears them.A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. +0= Rx Buffer not updated +1= Rx Buffer updated from new message + 0 + 32 + read-write + + + + + NDAT2 + new data2 + 0x9c + 32 + 0x00000000 + 0xFFFFFFFF + + + ND2 + New Data[63:32] +The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. +The flags remain set until the Host clears them. A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. +0= Rx Buffer not updated +1= Rx Buffer updated from new message + 0 + 32 + read-write + + + + + RXF0C + rx fifo 0 configuration + 0xa0 + 32 + 0x00000000 + 0xFF7FFFFC + + + F0OM + FIFO 0 Operation Mode +FIFO 0 can be operated in blocking or in overwrite mode (see Section 3.4.2). +0= FIFO 0 blocking mode +1= FIFO 0 overwrite mode + 31 + 1 + read-write + + + F0WM + Rx FIFO 0 Watermark +0= Watermark interrupt disabled +1-64= Level for Rx FIFO 0 watermark interrupt (IR.RF0W) +>64= Watermark interrupt disabled + 24 + 7 + read-write + + + F0S + Rx FIFO 0 Size +0= No Rx FIFO 0 +1-64= Number of Rx FIFO 0 elements +>64= Values greater than 64 are interpreted as 64 +The Rx FIFO 0 elements are indexed from 0 to F0S-1 + 16 + 7 + read-write + + + F0SA + Rx FIFO 0 Start Address +Start address of Rx FIFO 0 in Message RAM (32-bit word address) + 2 + 14 + read-write + + + + + RXF0S + rx fifo 0 status + 0xa4 + 32 + 0x00000000 + 0x033F3F7F + + + RF0L + Rx FIFO 0 Message Lost +This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset. +0= No Rx FIFO 0 message lost +1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero +Note: Overwriting the oldest message when RXF0C.F0OM = ‘1’ will not set this flag. + 25 + 1 + read-only + + + F0F + Rx FIFO 0 Full +0= Rx FIFO 0 not full +1= Rx FIFO 0 full + 24 + 1 + read-only + + + F0PI + Rx FIFO 0 Put Index +Rx FIFO 0 write index pointer, range 0 to 63. + 16 + 6 + read-only + + + F0GI + Rx FIFO 0 Get Index +Rx FIFO 0 read index pointer, range 0 to 63. + 8 + 6 + read-only + + + F0FL + Rx FIFO 0 Fill Level +Number of elements stored in Rx FIFO 0, range 0 to 64. + 0 + 7 + read-only + + + + + RXF0A + rx fifo0 acknowledge + 0xa8 + 32 + 0x00000000 + 0x0000003F + + + F0AI + Rx FIFO 0 Acknowledge Index +After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. +This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. + 0 + 6 + read-write + + + + + RXBC + rx buffer configuration + 0xac + 32 + 0x00000000 + 0x0000FFFC + + + RBSA + Rx Buffer Start Address +Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address).Also used to reference debug messages A,B,C. + 2 + 14 + read-write + + + + + RXF1C + rx fifo1 configuration + 0xb0 + 32 + 0x00000000 + 0xFF7FFFFC + + + F1OM + FIFO 1 Operation Mode +FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2). +0= FIFO 1 blocking mode +1= FIFO 1 overwrite mode + 31 + 1 + read-write + + + F1WM + Rx FIFO 1 Watermark +0= Watermark interrupt disabled +1-64= Level for Rx FIFO 1 watermark interrupt (IR.RF1W) +>64= Watermark interrupt disabled + 24 + 7 + read-write + + + F1S + Rx FIFO 1 Size +0= No Rx FIFO 1 +1-64= Number of Rx FIFO 1 elements +>64= Values greater than 64 are interpreted as 64 +The Rx FIFO 1 elements are indexed from 0 to F1S - 1 + 16 + 7 + read-write + + + F1SA + Rx FIFO 1 Start Address +Start address of Rx FIFO 1 in Message RAM (32-bit word address) + 2 + 14 + read-write + + + + + RXF1S + rx fifo1 status + 0xb4 + 32 + 0x00000000 + 0xC33F3F7F + + + DMS + Debug Message Status +00= Idle state, wait for reception of debug messages, DMA request is cleared +01= Debug message A received +10= Debug messages A, B received +11= Debug messages A, B, C received, DMA request is set + 30 + 2 + read-only + + + RF1L + Rx FIFO 1 Message Lost +This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset. +0= No Rx FIFO 1 message lost +1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero +Note: Overwriting the oldest message when RXF1C.F1OM = ‘1’ will not set this flag. + 25 + 1 + read-only + + + F1F + Rx FIFO 1 Full +0= Rx FIFO 1 not full +1= Rx FIFO 1 full + 24 + 1 + read-only + + + F1PI + Rx FIFO 1 Put Index +Rx FIFO 1 write index pointer, range 0 to 63. + 16 + 6 + read-only + + + F1GI + Rx FIFO 1 Get Index +Rx FIFO 1 read index pointer, range 0 to 63. + 8 + 6 + read-only + + + F1FL + Rx FIFO 1 Fill Level +Number of elements stored in Rx FIFO 1, range 0 to 64. + 0 + 7 + read-only + + + + + RXF1A + rx fifo 1 acknowledge + 0xb8 + 32 + 0x00000000 + 0x0000003F + + + F1AI + Rx FIFO 1 Acknowledge Index +After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. +This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. + 0 + 6 + read-write + + + + + RXESC + rx buffer/fifo element size configuration + 0xbc + 32 + 0x00000000 + 0x00000777 + + + RBDS + Rx Buffer Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field + 8 + 3 + read-write + + + F1DS + Rx FIFO 1 Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field + 4 + 3 + read-write + + + F0DS + Rx FIFO 0 Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field +Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, +only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame’s data field is ignored. + 0 + 3 + read-write + + + + + TXBC + tx buffer configuration + 0xc0 + 32 + 0x00000000 + 0x7F3FFFFC + + + TFQM + Tx FIFO/Queue Mode +0= Tx FIFO operation +1= Tx Queue operation + 30 + 1 + read-write + + + TFQS + Transmit FIFO/Queue Size +0= No Tx FIFO/Queue +1-32= Number of Tx Buffers used for Tx FIFO/Queue +>32= Values greater than 32 are interpreted as 32 + 24 + 6 + read-write + + + NDTB + Number of Dedicated Transmit Buffers +0= No Dedicated Tx Buffers +1-32= Number of Dedicated Tx Buffers +>32= Values greater than 32 are interpreted as 32 + 16 + 6 + read-write + + + TBSA + Tx Buffers Start Address +Start address of Tx Buffers section in Message RAM (32-bit word address, see Figure 2). +Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers. + 2 + 14 + read-write + + + + + TXFQS + tx fifo/queue status + 0xc4 + 32 + 0x00000000 + 0x003F1F3F + + + TFQF + Tx FIFO/Queue Full +0= Tx FIFO/Queue not full +1= Tx FIFO/Queue full + 21 + 1 + read-only + + + TFQPI + Tx FIFO/Queue Put Index +Tx FIFO/Queue write index pointer, range 0 to 31. + 16 + 5 + read-only + + + TFGI + Tx FIFO Get Index +Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured +(TXBC.TFQM = ‘1’). + 8 + 5 + read-only + + + TFFL + Tx FIFO Free Level +Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = ‘1’) +Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with +the first dedicated Tx Buffers. +Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO. + 0 + 6 + read-only + + + + + TXESC + tx buffer element size configuration + 0xc8 + 32 + 0x00000000 + 0x00000007 + + + TBDS + Tx Buffer Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field +Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TXESC.TBDS, the bytes not defined by the Tx Buffer are transmitted as “0xCC” (padding bytes). + 0 + 3 + read-write + + + + + TXBRP + tx buffer request pending + 0xcc + 32 + 0x00000000 + 0xFFFFFFFF + + + TRP + Transmission Request Pending +Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR.The bits are reset after a requested transmission has completed or has been cancelled via register +TXBCR. +TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan (see Section 3.5, Tx Handling) is started to check for the pending Tx request with the +highest priority (Tx Buffer with lowest Message ID). +A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, +this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. +After a cancellation has been requested, a finished cancellation is signalled via TXBCF +? after successful transmission together with the corresponding TXBTO bit +? when the transmission has not yet been started at the point of cancellation +? when the transmission has been aborted due to lost arbitration +? when an error occurred during frame transmission +In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. +0= No transmission request pending +1= Transmission request pending +Note: TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding TXBRP bit is reset. + 0 + 32 + read-only + + + + + TXBAR + tx buffer add request + 0xd0 + 32 + 0x00000000 + 0xFFFFFFFF + + + AR + Add Request +Each Tx Buffer has its own Add Request bit. Writing a ‘1’ will set the corresponding Add Request bit; writing a ‘0’ has no impact. This enables the Host to set transmission requests for multiple Tx +Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. +When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. +0= No transmission request added +1= Transmission requested added +Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding TXBRP bit already set), this add request is ignored. + 0 + 32 + read-write + + + + + TXBCR + tx buffer cancellation request + 0xd4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CR + Cancellation Request +Each Tx Buffer has its own Cancellation Request bit. Writing a ‘1’ will set the corresponding Cancellation Request bit; writing a ‘0’ has no impact. +This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. +0= No cancellation pending +1= Cancellation pending + 0 + 32 + read-write + + + + + TXBTO + tx buffer transmission occurred + 0xd8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TO + Transmission Occurred +Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. +0= No transmission occurred +1= Transmission occurred + 0 + 32 + read-only + + + + + TXBCF + tx buffer cancellation finished + 0xdc + 32 + 0x00000000 + 0xFFFFFFFF + + + CF + Cancellation Finished +Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. +In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. +0= No transmit buffer cancellation +1= Transmit buffer cancellation finished + 0 + 32 + read-only + + + + + TXBTIE + tx buffer transmission interrupt enable + 0xe0 + 32 + 0x00000000 + 0xFFFFFFFF + + + TIE + Transmission Interrupt Enable +Each Tx Buffer has its own Transmission Interrupt Enable bit. +0= Transmission interrupt disabled +1= Transmission interrupt enable + 0 + 32 + read-write + + + + + TXBCIE + tx buffer cancellation finished interrupt enable + 0xe4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CFIE + Cancellation Finished Interrupt Enable +Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. +0= Cancellation finished interrupt disabled +1= Cancellation finished interrupt enabled + 0 + 32 + read-write + + + + + TXEFC + tx event fifo configuration + 0xf0 + 32 + 0x00000000 + 0x3F3FFFFC + + + EFWM + Event FIFO Watermark +0= Watermark interrupt disabled +1-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW) +>32= Watermark interrupt disabled + 24 + 6 + read-write + + + EFS + Event FIFO Size +0= Tx Event FIFO disabled +1-32= Number of Tx Event FIFO elements +>32= Values greater than 32 are interpreted as 32 +The Tx Event FIFO elements are indexed from 0 to EFS - 1 + 16 + 6 + read-write + + + EFSA + Event FIFO Start Address +Start address of Tx Event FIFO in Message RAM (32-bit word address) + 2 + 14 + read-write + + + + + TXEFS + tx event fifo status + 0xf4 + 32 + 0x00000000 + 0x031F1F3F + + + TEFL + Tx Event FIFO Element Lost +This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset. +0= No Tx Event FIFO element lost +1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. + 25 + 1 + read-only + + + EFF + Event FIFO Full +0= Tx Event FIFO not full +1= Tx Event FIFO full + 24 + 1 + read-only + + + EFPI + Event FIFO Put Index +Tx Event FIFO write index pointer, range 0 to 31. + 16 + 5 + read-only + + + EFGI + Event FIFO Get Index +Tx Event FIFO read index pointer, range 0 to 31. + 8 + 5 + read-only + + + EFFL + Event FIFO Fill Level +Number of elements stored in Tx Event FIFO, range 0 to 32. + 0 + 6 + read-only + + + + + TXEFA + tx event fifo acknowledge + 0xf8 + 32 + 0x00000000 + 0x0000001F + + + EFAI + Event FIFO Acknowledge Index +After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get +Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL. + 0 + 5 + read-write + + + + + 16 + 0x4 + TS_SEL0,TS_SEL1,TS_SEL2,TS_SEL3,TS_SEL4,TS_SEL5,TS_SEL6,TS_SEL7,TS_SEL8,TS_SEL9,TS_SEL10,TS_SEL11,TS_SEL12,TS_SEL13,TS_SEL14,TS_SEL15 + TS_SEL[%s] + no description available + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + TS + Timestamp Word TS +default can save 16 timestamps with 32bit; +if ts64_en is set, then work at 64bit mode, can save 8 timestamps with 01/23/45…. + 0 + 32 + read-only + + + + + CREL + core release register + 0x240 + 32 + 0x00000000 + 0xFFFFFFFF + + + REL + Core Release +One digit, BCD-coded + 28 + 4 + read-only + + + STEP + Step of Core Release +One digit, BCD-coded. + 24 + 4 + read-only + + + SUBSTEP + Sub-step of Core Release +One digit, BCD-coded + 20 + 4 + read-only + + + YEAR + Timestamp Year +One digit, BCD-coded. This field is set by generic parameter on +synthesis. + 16 + 4 + read-only + + + MON + Timestamp Month +Two digits, BCD-coded. This field is set by generic parameter +on synthesis. + 8 + 8 + read-only + + + DAY + Timestamp Day +Two digits, BCD-coded. This field is set by generic parameter +on synthesis. + 0 + 8 + read-only + + + + + TSCFG + timestamp configuration + 0x244 + 32 + 0x00000000 + 0x0000FF0F + + + TBPRE + Timebase Prescaler +0x00 to 0xFF +The value by which the oscillator frequency is divided for +generating the timebase counter clock. Valid values for the +Timebase Prescaler are 0 to 255. The actual interpretation by +the hardware of this value is such that one more than the value +programmed here is used. Affects only the TSU internal +timebase. When the internal timebase is excluded by synthesis, +TBPRE[7:0] is fixed to 0x00, the Timestamp Prescaler is not +used. + 8 + 8 + read-write + + + EN64 + set to use 64bit timestamp. +when enabled, tsu can save up to 8 different timestamps, TS(k) and TS(k+1) are used for one 64bit timestamp, k is 0~7. +TSP can be used to select different one + 3 + 1 + read-write + + + SCP + Select Capturing Position +0: Capture Timestamp at EOF +1: Capture Timestamp at SOF + 2 + 1 + read-write + + + TBCS + Timebase Counter Select +When the internal timebase is excluded by synthesis, TBCS is +fixed to ‘1’. +0: Timestamp value captured from internal timebase counter, + ATB.TB[31:0] is the internal timbase counter +1: Timestamp value captured from input tsu_tbin[31:0],ATB.TB[31:0] is tsu_tbin[31:0] + 1 + 1 + read-write + + + TSUE + Timestamp Unit Enable +0: TSU disabled +1: TSU enabled + 0 + 1 + read-write + + + + + TSS1 + timestamp status1 + 0x248 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSL + Timestamp Lost +Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when the timestamp stored in the related Timestamp register was overwritten before it was read. +Reading a Timestamp register resets the related bit. + 16 + 16 + read-only + + + TSN + Timestamp New +Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when a timestamp was stored in the related +Timestamp register. Reading a Timestamp register resets the related bit. + 0 + 16 + read-only + + + + + TSS2 + timestamp status2 + 0x24c + 32 + 0x00000000 + 0x0000000F + + + TSP + Timestamp Pointer +The Timestamp Pointer is incremented by one each time a timestamp is captured. From its maximum value (3, 7, or 15 +depending on number_ts_g), it is incremented to 0. +Value also signalled on output m_can_tsp[3:0]. + 0 + 4 + read-only + + + + + ATB + actual timebase + 0x250 + 32 + 0x00000000 + 0xFFFFFFFF + + + TB + timebase for timestamp generation 31-0 + 0 + 32 + read-only + + + + + ATBH + actual timebase high + 0x254 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBH + timebase for timestamp generation 63-32 + 0 + 32 + read-only + + + + + GLB_CTL + global control + 0x400 + 32 + 0x00000000 + 0xE0000003 + + + M_CAN_STBY + m_can standby control + 31 + 1 + read-write + + + STBY_CLR_EN + m_can standby clear control +0:controlled by software by standby bit[bit31] +1:auto clear standby by hardware when rx data is 0 + 30 + 1 + read-write + + + STBY_POL + standby polarity selection + 29 + 1 + read-write + + + TSU_TBIN_SEL + external timestamp select. each CAN block has 4 timestamp input, this register is used to select one of them as timestame if TSCFG.TBCS is set to 1 + 0 + 2 + read-write + + + + + GLB_STATUS + global status + 0x404 + 32 + 0x00000000 + 0x0000000C + + + M_CAN_INT1 + m_can interrupt status1 + 3 + 1 + read-only + + + M_CAN_INT0 + m_can interrupt status0 + 2 + 1 + read-only + + + + + 640 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255,256,257,258,259,260,261,262,263,264,265,266,267,268,269,270,271,272,273,274,275,276,277,278,279,280,281,282,283,284,285,286,287,288,289,290,291,292,293,294,295,296,297,298,299,300,301,302,303,304,305,306,307,308,309,310,311,312,313,314,315,316,317,318,319,320,321,322,323,324,325,326,327,328,329,330,331,332,333,334,335,336,337,338,339,340,341,342,343,344,345,346,347,348,349,350,351,352,353,354,355,356,357,358,359,360,361,362,363,364,365,366,367,368,369,370,371,372,373,374,375,376,377,378,379,380,381,382,383,384,385,386,387,388,389,390,391,392,393,394,395,396,397,398,399,400,401,402,403,404,405,406,407,408,409,410,411,412,413,414,415,416,417,418,419,420,421,422,423,424,425,426,427,428,429,430,431,432,433,434,435,436,437,438,439,440,441,442,443,444,445,446,447,448,449,450,451,452,453,454,455,456,457,458,459,460,461,462,463,464,465,466,467,468,469,470,471,472,473,474,475,476,477,478,479,480,481,482,483,484,485,486,487,488,489,490,491,492,493,494,495,496,497,498,499,500,501,502,503,504,505,506,507,508,509,510,511,512,513,514,515,516,517,518,519,520,521,522,523,524,525,526,527,528,529,530,531,532,533,534,535,536,537,538,539,540,541,542,543,544,545,546,547,548,549,550,551,552,553,554,555,556,557,558,559,560,561,562,563,564,565,566,567,568,569,570,571,572,573,574,575,576,577,578,579,580,581,582,583,584,585,586,587,588,589,590,591,592,593,594,595,596,597,598,599,600,601,602,603,604,605,606,607,608,609,610,611,612,613,614,615,616,617,618,619,620,621,622,623,624,625,626,627,628,629,630,631,632,633,634,635,636,637,638,639 + MESSAGE_BUFF[%s] + no description available + 0x2000 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + + + MCAN1 + MCAN1 + MCAN + 0xf0084000 + + + MCAN2 + MCAN2 + MCAN + 0xf0088000 + + + MCAN3 + MCAN3 + MCAN + 0xf008c000 + + + WDG0 + WDG0 + WDOG + 0xf0090000 + + 0x10 + 0x10 + registers + + + + CTRL + Control Register + 0x10 + 32 + 0x00000000 + 0x000007FF + + + RSTTIME + The time interval of the reset stage: +0: Clock period x 2^7 +1: Clock period x 2^8 +2: Clock period x 2^9 +3: Clock period x 2^10 +4: Clock period x 2^11 +5: Clock period x 2^12 +6: Clock period x 2^13 +7: Clock period x 2^14 + 8 + 3 + read-write + + + INTTIME + The timer interval of the interrupt stage: +0: Clock period x 2^6 +1: Clock period x 2^8 +2: Clock period x 2^10 +3: Clock period x 2^11 +4: Clock period x 2^12 +5: Clock period x 2^13 +6: Clock period x 2^14 +7: Clock period x 2^15 +8: Clock period x 2^17 +9: Clock period x 2^19 +10: Clock period x 2^21 +11: Clock period x 2^23 +12: Clock period x 2^25 +13: Clock period x 2^27 +14: Clock period x 2^29 +15: Clock period x 2^31 + 4 + 4 + read-write + + + RSTEN + Enable or disable the watchdog reset +0: Disable +1: Enable + 3 + 1 + read-write + + + INTEN + Enable or disable the watchdog interrupt +0: Disable +1: Enable + 2 + 1 + read-write + + + CLKSEL + Clock source of timer: +0: EXTCLK +1: PCLK + 1 + 1 + read-write + + + EN + Enable or disable the watchdog timer +0: Disable +1: Enable + 0 + 1 + read-write + + + + + Restart + Restart Register + 0x14 + 32 + 0x00000000 + 0x0000FFFF + + + RESTART + Write the magic number +ATCWDT200_RESTART_NUM to restart the +watchdog timer. + 0 + 16 + write-only + + + + + WrEn + Write Protection Register + 0x18 + 32 + 0x00000000 + 0x0000FFFF + + + WEN + Write the magic code to disable the write +protection of the Control Register and the +Restart Register. + 0 + 16 + write-only + + + + + St + Status Register + 0x1c + 32 + 0x00000000 + 0x00000001 + + + INTEXPIRED + The status of the watchdog interrupt timer +0: timer is not expired yet +1: timer is expired + 0 + 1 + write-only + + + + + + + WDG1 + WDG1 + WDOG + 0xf0094000 + + + PWDG + PWDG + WDOG + 0xf40e8000 + + + MBX0A + MBX0A + MBX + 0xf00a0000 + + 0x0 + 0x24 + registers + + + + CR + Command Registers + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXRESET + Reset TX Fifo and word. + 31 + 1 + read-write + + + BARCTL + Bus Access Response Control, when bit 15:14= +00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. + 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. +10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. +11: reserved. + 14 + 2 + read-write + + + BEIE + Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. +1, enable the bus access error interrupt. +0, disable the bus access error interrupt. + 8 + 1 + read-write + + + TFMAIE + TX FIFO message available interrupt enable. +1, enable the TX FIFO massage available interrupt. +0, disable the TX FIFO message available interrupt. + 7 + 1 + read-write + + + TFMEIE + TX FIFO message empty interrupt enable. +1, enable the TX FIFO massage empty interrupt. +0, disable the TX FIFO message empty interrupt. + 6 + 1 + read-write + + + RFMAIE + RX FIFO message available interrupt enable. +1, enable the RX FIFO massage available interrupt. +0, disable the RX FIFO message available interrupt. + 5 + 1 + read-write + + + RFMFIE + RX fifo message full interrupt enable. +1, enable the RX fifo message full interrupt. +0, disable the RX fifo message full interrupt. + 4 + 1 + read-write + + + TWMEIE + TX word message empty interrupt enable. +1, enable the TX word massage empty interrupt. +0, disable the TX word message empty interrupt. + 1 + 1 + read-write + + + RWMVIE + RX word message valid interrupt enable. +1, enable the RX word massage valid interrupt. +0, disable the RX word message valid interrupt. + 0 + 1 + read-write + + + + + SR + Status Registers + 0x4 + 32 + 0x000000E2 + 0xFFFF3FFF + + + RFVC + RX FIFO valid message count + 20 + 4 + read-only + + + TFEC + TX FIFO empty message word count + 16 + 4 + read-only + + + ERRRE + bus Error for read when rx word message are still invalid, this bit is W1C bit. +1, read from word message when the word message are still invalid will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 13 + 1 + write-only + + + EWTRF + bus Error for write when tx word message are still valid, this bit is W1C bit. +1, write to word message when the word message are still valid will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 12 + 1 + write-only + + + ERRFE + bus Error for read when rx fifo empty, this bit is W1C bit. +1, read from a empty rx fifo will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 11 + 1 + write-only + + + EWTFF + bus Error for write when tx fifo full, this bit is W1C bit. +1, write to a fulled tx fifo will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 10 + 1 + write-only + + + EAIVA + bus Error for Accessing Invalid Address; this bit is W1C bit. +1, read and write to invalid address in the bus of this block, will set this bit. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 9 + 1 + write-only + + + EW2RO + bus Error for Write to Read Only address; this bit is W1C bit. +1, write to read only address happened in the bus of this block. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 8 + 1 + write-only + + + TFMA + TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. +1, TXFIFO message buffer has slot available +0, no slot available (fifo full) + 7 + 1 + read-write + + + TFME + TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. +1, no any message data in TXFIFO from other core. +0, there are some data in the 4x32 TX FIFO from other core yet. + 6 + 1 + read-write + + + RFMA + RX FIFO Message Available, available data in the 4x32 TX FIFO message buffer to the other core, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, no any data in the 4x32 TXFIFO message buffer. +0, there are some data in the the 4x32 TXFIFO message buffer already. + 5 + 1 + read-only + + + RFMF + RX FIFO Message Full, message from other core; will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, the other core had written 4x32 message in the RXFIFO. +0, no 4x32 RX FIFO message from other core yet. + 4 + 1 + read-only + + + TWME + TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, means this core had write word message to TXREG. +0, means no valid word message in the TXREG yet. + 1 + 1 + read-only + + + RWMV + RX word message valid, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, the other core had written word message in the RXREG. +0, no valid word message yet in the RXREG. + 0 + 1 + read-only + + + + + TXREG + Transmit word message to other core. + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXREG + Transmit word message to other core. + 0 + 32 + write-only + + + + + RXREG + Receive word message from other core. + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + RXREG + Receive word message from other core. + 0 + 32 + read-only + + + + + 1 + 0x4 + TXFIFO0 + TXWRD[%s] + no description available + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXFIFO + TXFIFO for sending message to other core, FIFO size, 4x32 +can write one of the word address to push data to the FIFO; +can also use 4x32 burst write from 0x010 to push 4 words to the FIFO. + 0 + 32 + write-only + + + + + 1 + 0x4 + RXFIFO0 + RXWRD[%s] + no description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXFIFO + RXFIFO for receiving message from other core, FIFO size, 4x32 +can read one of the word address to pop data to the FIFO; +can also use 4x32 burst read from 0x020 to read 4 words from the FIFO. + 0 + 32 + read-only + + + + + + + MBX0B + MBX0B + MBX + 0xf00a4000 + + + MBX1A + MBX1A + MBX + 0xf00a8000 + + + MBX1B + MBX1B + MBX + 0xf00ac000 + + + PTPC + PTPC + PTPC + 0xf00b0000 + + 0x0 + 0x3004 + registers + + + + 2 + 0x1000 + 0,1 + PTPC[%s] + no description available + 0x0 + + Ctrl0 + Control Register 0 + 0x0 + 32 + 0x00000000 + 0x000003FF + + + SUBSEC_DIGITAL_ROLLOVER + Format for ns counter rollover, +1-digital, overflow time 1000000000/0x3B9ACA00 +0-binary, overflow time 0x7FFFFFFF + 9 + 1 + read-write + + + CAPT_SNAP_KEEP + set will keep capture snap till software read capt_snapl. +If this bit is set, software should read capt_snaph first to avoid wrong result. +If this bit is cleared, capture result will be updated at each capture event + 8 + 1 + read-write + + + CAPT_SNAP_POS_EN + set will use posege of input capture signal to latch timestamp value + 7 + 1 + read-write + + + CAPT_SNAP_NEG_EN + No description available + 6 + 1 + read-write + + + COMP_EN + set to enable compare, will be cleared by HW when compare event triggered + 4 + 1 + read-write + + + UPDATE_TIMER + update timer with +/- ts_updt, pulse, clear after set + 3 + 1 + write-only + + + INIT_TIMER + initial timer with ts_updt, pulse, clear after set + 2 + 1 + write-only + + + FINE_COARSE_SEL + 0: coarse update, ns counter add ss_incr[7:0] each clk +1: fine update, ns counter add ss_incr[7:0] each time addend counter overflow + 1 + 1 + read-write + + + TIMER_ENABLE + No description available + 0 + 1 + read-write + + + + + ctrl1 + Control Register 1 + 0x4 + 32 + 0x00000000 + 0x000000FF + + + SS_INCR + constant value used to add ns counter; +such as for 50MHz timer clock, set it to 8'd20 + 0 + 8 + read-write + + + + + timeh + timestamp high + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMESTAMP_HIGH + No description available + 0 + 32 + read-only + + + + + timel + timestamp low + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMESTAMP_LOW + No description available + 0 + 32 + read-only + + + + + ts_updth + timestamp update high + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + SEC_UPDATE + together with ts_updtl, used to initial or update timestamp + 0 + 32 + read-write + + + + + ts_updtl + timestamp update low + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADD_SUB + 1 for sub; 0 for add, used only at update + 31 + 1 + read-write + + + NS_UPDATE + No description available + 0 + 31 + read-write + + + + + addend + No description available + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDEND + used in fine update mode only + 0 + 32 + read-write + + + + + tarh + No description available + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + TARGET_TIME_HIGH + used for generate compare signal if enabled + 0 + 32 + read-write + + + + + tarl + No description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + TARGET_TIME_LOW + No description available + 0 + 32 + read-write + + + + + pps_ctrl + No description available + 0x2c + 32 + 0x00000000 + 0x0000000F + + + PPS_CTRL + No description available + 0 + 4 + read-write + + + + + capt_snaph + No description available + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPT_SNAP_HIGH + take snapshot for input capture signal, at pos or neg or both; +the result can be kept or updated at each event according to cfg0.bit8 + 0 + 32 + read-only + + + + + capt_snapl + No description available + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPT_SNAP_LOW + No description available + 0 + 32 + read-write + + + + + + time_sel + No description available + 0x2000 + 32 + 0x00000000 + 0x0000000F + + + CAN3_TIME_SEL + No description available + 3 + 1 + read-write + + + CAN2_TIME_SEL + No description available + 2 + 1 + read-write + + + CAN1_TIME_SEL + No description available + 1 + 1 + read-write + + + CAN0_TIME_SEL + set to use ptpc1 for canx +clr to use ptpc0 for canx + 0 + 1 + read-write + + + + + int_sts + No description available + 0x2004 + 32 + 0x00000000 + 0x00070007 + + + COMP_INT_STS1 + No description available + 18 + 1 + write-only + + + CAPTURE_INT_STS1 + No description available + 17 + 1 + write-only + + + PPS_INT_STS1 + No description available + 16 + 1 + write-only + + + COMP_INT_STS0 + No description available + 2 + 1 + write-only + + + CAPTURE_INT_STS0 + No description available + 1 + 1 + write-only + + + PPS_INT_STS0 + No description available + 0 + 1 + write-only + + + + + int_en + No description available + 0x2008 + 32 + 0x00000000 + 0x00070007 + + + COMP_INT_STS1 + No description available + 18 + 1 + read-write + + + CAPTURE_INT_STS1 + No description available + 17 + 1 + read-write + + + PPS_INT_STS1 + No description available + 16 + 1 + read-write + + + COMP_INT_STS0 + No description available + 2 + 1 + read-write + + + CAPTURE_INT_STS0 + No description available + 1 + 1 + read-write + + + PPS_INT_STS0 + No description available + 0 + 1 + read-write + + + + + ptpc_can_ts_sel + No description available + 0x3000 + 32 + 0x00000000 + 0xFFFFFF00 + + + TSU_TBIN3_SEL + No description available + 26 + 6 + read-write + + + TSU_TBIN2_SEL + No description available + 20 + 6 + read-write + + + TSU_TBIN1_SEL + No description available + 14 + 6 + read-write + + + TSU_TBIN0_SEL + No description available + 8 + 6 + read-write + + + + + + + CRC + CRC + CRC + 0xf00b8000 + + 0x0 + 0x200 + registers + + + + 8 + 0x40 + 0,1,2,3,4,5,6,7 + CHN[%s] + no description available + 0x0 + + pre_set + &index0 pre set for crc setting + 0x0 + 32 + 0x00000000 + 0x000000FF + + + PRE_SET + 0: no pre set +1: CRC32 +2: CRC32-AUTOSAR +3: CRC16-CCITT +4: CRC16-XMODEM +5: CRC16-MODBUS +1: CRC32 +2: CRC32-autosar +3: CRC16-ccitt +4: CRC16-xmodem +5: CRC16-modbus +6: crc16_dnp +7: crc16_x25 +8: crc16_usb +9: crc16_maxim +10: crc16_ibm +11: crc8_maxim +12: crc8_rohc +13: crc8_itu +14: crc8 +15: crc5_usb + 0 + 8 + read-write + + + + + clr + chn&index0 clear crc result and setting + 0x4 + 32 + 0x00000000 + 0x00000001 + + + CLR + write 1 to clr crc setting and result for its channel. +always read 0. + 0 + 1 + read-write + + + + + poly + chn&index0 poly + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + POLY + poly setting + 0 + 32 + read-write + + + + + init_data + chn&index0 init_data + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + INIT_DATA + initial data of CRC + 0 + 32 + read-write + + + + + xorout + chn&index0 xorout + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + XOROUT + XOR for CRC result + 0 + 32 + read-write + + + + + misc_setting + chn&index0 misc_setting + 0x14 + 32 + 0x00000000 + 0x0101013F + + + BYTE_REV + 0: no wrap input byte order +1: wrap input byte order + 24 + 1 + read-write + + + REV_OUT + 0: no wrap output bit order +1: wrap output bit order + 16 + 1 + read-write + + + REV_IN + 0: no wrap input bit order +1: wrap input bit order + 8 + 1 + read-write + + + POLY_WIDTH + crc data length + 0 + 6 + read-write + + + + + data + chn&index0 data + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + data for crc + 0 + 32 + read-write + + + + + result + chn&index0 result + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + RESULT + crc result + 0 + 32 + read-write + + + + + + + + DMAMUX + DMAMUX + DMAMUX + 0xf00c0000 + + 0x0 + 0x40 + registers + + + + 16 + 0x4 + HDMA_MUX0,HDMA_MUX1,HDMA_MUX2,HDMA_MUX3,HDMA_MUX4,HDMA_MUX5,HDMA_MUX6,HDMA_MUX7,XDMA_MUX0,XDMA_MUX1,XDMA_MUX2,XDMA_MUX3,XDMA_MUX4,XDMA_MUX5,XDMA_MUX6,XDMA_MUX7 + MUXCFG[%s] + no description available + 0x0 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + + + HDMA + HDMA + DMA + 0xf00c4000 + + 0x4 + 0x13c + registers + + + + IDMisc + ID Misc + 0x4 + 32 + 0x00000000 + 0x00008000 + + + IDLE_FLAG + DMA Idle Flag +0 - DMA is busy +1 - DMA is dile + 15 + 1 + read-only + + + + + DMACfg + DMAC Configuration Register + 0x10 + 32 + 0x00000000 + 0xC3FFFFFF + + + CHAINXFR + Chain transfer +0x0: Chain transfer is not configured +0x1: Chain transfer is configured + 31 + 1 + read-only + + + REQSYNC + DMA request synchronization. The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. +0x0: Request synchronization is not configured +0x1: Request synchronization is configured + 30 + 1 + read-only + + + DATAWIDTH + AXI bus data width +0x0: 32 bits +0x1: 64 bits +0x2: 128 bits +0x3: 256 bits + 24 + 2 + read-only + + + ADDRWIDTH + AXI bus address width +0x18: 24 bits +0x19: 25 bits +... +0x40: 64 bits +Others: Invalid + 17 + 7 + read-only + + + CORENUM + DMA core number +0x0: 1 core +0x1: 2 cores + 16 + 1 + read-only + + + BUSNUM + AXI bus interface number +0x0: 1 AXI bus +0x1: 2 AXI busses + 15 + 1 + read-only + + + REQNUM + Request/acknowledge pair number +0x0: 0 pair +0x1: 1 pair +0x2: 2 pairs +... +0x10: 16 pairs + 10 + 5 + read-only + + + FIFODEPTH + FIFO depth +0x4: 4 entries +0x8: 8 entries +0x10: 16 entries +0x20: 32 entries +Others: Invalid + 4 + 6 + read-only + + + CHANNELNUM + Channel number +0x1: 1 channel +0x2: 2 channels +... +0x8: 8 channels +Others: Invalid + 0 + 4 + read-only + + + + + DMACtrl + DMAC Control Register + 0x20 + 32 + 0x00000000 + 0x00000001 + + + RESET + Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. +Note: The software reset may cause the in-completion of AXI transaction. + 0 + 1 + write-only + + + + + ChAbort + Channel Abort Register + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + CHABORT + Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) + 0 + 32 + write-only + + + + + IntStatus + Interrupt Status Register + 0x30 + 32 + 0x00000000 + 0x00FFFFFF + + + TC + The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. +0x0: Channel n has no terminal count status +0x1: Channel n has terminal count status + 16 + 8 + write-only + + + ABORT + The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. +0x0: Channel n has no abort status +0x1: Channel n has abort status + 8 + 8 + write-only + + + ERROR + The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: +- Bus error +- Unaligned address +- Unaligned transfer width +- Reserved configuration +0x0: Channel n has no error status +0x1: Channel n has error status + 0 + 8 + write-only + + + + + ChEN + Channel Enable Register + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + CHEN + Alias of the Enable field of all ChnCtrl registers + 0 + 32 + read-only + + + + + 8 + 0x20 + ch0,ch1,ch2,ch3,ch4,ch5,ch6,ch7 + CHCTRL[%s] + no description available + 0x40 + + Ctrl + Channel n Control Register + 0x0 + 32 + 0x00000000 + 0xEFFFFFFF + + + SRCBUSINFIDX + Bus interface index that source data is read from +0x0: Data is read from bus interface 0 +0x1: Data is read from bus interface + 31 + 1 + read-write + + + DSTBUSINFIDX + Bus interface index that destination data is written to +0x0: Data is written to bus interface 0 +0x1: Data is written to bus interface 1 + 30 + 1 + read-write + + + PRIORITY + Channel priority level +0x0: Lower priority +0x1: Higher priority + 29 + 1 + read-write + + + SRCBURSTSIZE + Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. +The burst transfer byte number is (SrcBurstSize * SrcWidth). +0x0: 1 transfer +0x1: 2 transfers +0x2: 4 transfers +0x3: 8 transfers +0x4: 16 transfers +0x5: 32 transfers +0x6: 64 transfers +0x7: 128 transfers +0x8: 256 transfers +0x9:512 transfers +0xa: 1024 transfers +0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 + 24 + 4 + read-write + + + SRCWIDTH + Source transfer width +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 + 21 + 3 + read-write + + + DSTWIDTH + Destination transfer width. +Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. +See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 + 18 + 3 + read-write + + + SRCMODE + Source DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 17 + 1 + read-write + + + DSTMODE + Destination DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 16 + 1 + read-write + + + SRCADDRCTRL + Source address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 14 + 2 + read-write + + + DSTADDRCTRL + Destination address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 12 + 2 + read-write + + + SRCREQSEL + Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + 8 + 4 + read-write + + + DSTREQSEL + Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + 4 + 4 + read-write + + + INTABTMASK + Channel abort interrupt mask +0x0: Allow the abort interrupt to be triggered +0x1: Disable the abort interrupt + 3 + 1 + read-write + + + INTERRMASK + Channel error interrupt mask +0x0: Allow the error interrupt to be triggered +0x1: Disable the error interrupt + 2 + 1 + read-write + + + INTTCMASK + Channel terminal count interrupt mask +0x0: Allow the terminal count interrupt to be triggered +0x1: Disable the terminal count interrupt + 1 + 1 + read-write + + + ENABLE + Channel enable bit +0x0: Disable +0x1: Enable + 0 + 1 + read-write + + + + + TranSize + Channel n Transfer Size Register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRANSIZE + Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. +If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + 0 + 32 + read-write + + + + + SrcAddr + Channel n Source Address Low Part Register + 0x8 + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRL + Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + 0 + 32 + read-write + + + + + SrcAddrH + Channel n Source Address High Part Register + 0xc + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRH + High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + DstAddr + Channel n Destination Address Low Part Register + 0x10 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRL + Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + 0 + 32 + read-write + + + + + DstAddrH + Channel n Destination Address High Part Register + 0x14 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRH + High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + LLPointer + Channel n Linked List Pointer Low Part Register + 0x18 + 32 + 0x00000000 + 0xFFFFFFF9 + + + LLPOINTERL + Low part of the pointer to the next descriptor. The pointer must be double word aligned. + 3 + 29 + read-write + + + LLDBUSINFIDX + Bus interface index that the next descriptor is read from +0x0: The next descriptor is read from bus interface 0 + 0 + 1 + read-write + + + + + LLPointerH + Channel n Linked List Pointer High Part Register + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + LLPOINTERH + High part of the pointer to the next descriptor. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + + + + XDMA + XDMA + DMA + 0xf3048000 + + + RNG + RNG + RNG + 0xf00c8000 + + 0x0 + 0x40 + registers + + + + CMD + Command Register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SFTRST + Soft Reset, Perform a software reset of the RNG This bit is self-clearing. +0 Do not perform a software reset. +1 Software reset + 6 + 1 + read-write + + + CLRERR + Clear the Error, clear the errors in the ESR register and the RNG interrupt. This bit is self-clearing. +0 Do not clear the errors and the interrupt. +1 Clear the errors and the interrupt. + 5 + 1 + read-write + + + CLRINT + Clear the Interrupt, clear the RNG interrupt if an error is not present. This bit is self-clearing. +0 Do not clear the interrupt. +1 Clear the interrupt + 4 + 1 + read-write + + + GENSD + Generate Seed, when both ST and GS triggered, ST first and GS next. + 1 + 1 + read-write + + + SLFCHK + Self Test, when both ST and GS triggered, ST first and GS next. + 0 + 1 + read-write + + + + + CTRL + Control Register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + MIRQERR + Mask Interrupt Request for Error + 6 + 1 + read-write + + + MIRQDN + Mask Interrupt Request for Done Event, asks the interrupts generated upon the completion of the seed and self-test modes. The status of these jobs can be viewed by: +• Reading the STA and viewing the seed done and the self-test done bits (STA[SDN, STDN]). +• Viewing the RNG_CMD for the generate-seed or the self-test bits (CMD[GS,ST]) being set, indicating that the operation is still taking place. + 5 + 1 + read-write + + + AUTRSD + Auto Reseed + 4 + 1 + read-write + + + FUFMOD + FIFO underflow response mode +00 Return all zeros and set the ESR[FUFE]. +01 Return all zeros and set the ESR[FUFE]. +10 Generate the bus transfer error +11 Generate the interrupt and return all zeros (overrides the CTRL[MASKERR]). + 0 + 2 + read-write + + + + + STA + Status Register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SCPF + Self Check Pass Fail + 21 + 3 + read-only + + + FUNCERR + Error was detected, check ESR register for details + 16 + 1 + read-only + + + FSIZE + Fifo Size, it is 5 in this design. + 12 + 4 + read-only + + + FRNNU + Fifo Level, Indicates the number of random words currently in the output FIFO + 8 + 4 + read-only + + + NSDDN + New seed done. + 6 + 1 + read-only + + + FSDDN + 1st Seed done +When "1", Indicates that the RNG generated the first seed. + 5 + 1 + read-only + + + SCDN + Self Check Done +Indicates whether Self Test is done or not. Can be cleared by the hardware reset or a new self test is +initiated by setting the CMD[ST]. +0 Self test not completed +1 Completed a self test since the last reset. + 4 + 1 + read-only + + + RSDREQ + Reseed needed +Indicates that the RNG needs to be reseeded. This is done by setting the CMD[GS], or +automatically if the CTRL[ARS] is set. + 3 + 1 + read-only + + + IDLE + Idle, the RNG is in the idle mode, and internal clocks are disabled, in this mode, access to the FIFO is allowed. Once the FIFO is empty, the RNGB fills the FIFO and then enters idle mode again. + 2 + 1 + read-only + + + BUSY + when 1, means the RNG engine is busy for seeding or random number generation, self test and so on. + 1 + 1 + read-only + + + + + ERR + Error Registers + 0xc + 32 + 0x00000000 + 0xFFFFFF3F + + + FUFE + FIFO access error(underflow) + 5 + 1 + read-only + + + SCKERR + Self-test error +Indicates that the RNG failed the most recent self test. This bit is sticky and can only be reset by a +hardware reset or by writing 1 to the CMD[CE] + 3 + 1 + read-only + + + + + FO2B + FIFO out to bus/cpu + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2B + SW read the FIFO output. + 0 + 32 + read-only + + + + + 8 + 0x4 + FO2S0,FO2S1,FO2S2,FO2S3,FO2S4,FO2S5,FO2S6,FO2S7 + R2SK[%s] + no description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2S0 + FIFO out to KMAN, will be SDP engine key. + 0 + 32 + read-only + + + + + + + KEYM + KEYM + KEYM + 0xf00cc000 + + 0x0 + 0x50 + registers + + + + 8 + 0x4 + SFK0,SFK1,SFK2,SFK3,SFK4,SFK5,SFK6,SFK7 + SOFTMKEY[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software symmetric key +key will be scambled to 4 variants for software to use, and replicable on same chip. +scramble keys are chip different, and not replicable on different chip +must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 + 0 + 32 + read-write + + + + + 8 + 0x4 + SPK0,SPK1,SPK2,SPK3,SPK4,SPK5,SPK6,SPK7 + SOFTPKEY[%s] + no description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software asymmetric key +key is derived from scrambles of fuse private key, software input key, SRK, and system security status. +This key os read once, sencondary read will read out 0 + 0 + 32 + read-write + + + + + SEC_KEY_CTL + secure key generation + 0x40 + 32 + 0x00000000 + 0x80011117 + + + LOCK_SEC_CTL + block secure state key setting being changed + 31 + 1 + read-write + + + SK_VAL + session key valid +0: session key is all 0's and not usable +1: session key is valid + 16 + 1 + read-only + + + SMK_SEL + software symmetric key selection +0: use origin value in software symmetric key +1: use scramble version of software symmetric key + 12 + 1 + read-write + + + ZMK_SEL + batt symmetric key selection +0: use scramble version of software symmetric key +1: use origin value in software symmetric key + 8 + 1 + read-write + + + FMK_SEL + fuse symmetric key selection +0: use scramble version of fuse symmetric key +1: use alnertave scramble of fuse symmetric key + 4 + 1 + read-write + + + KEY_SEL + secure symmtric key synthesize setting, key is a XOR of following +bit0: fuse mk, 0: not selected, 1:selected +bit1: zmk from batt, 0: not selected, 1:selected +bit2: software key 0: not selected, 1:selected + 0 + 3 + read-write + + + + + NSC_KEY_CTL + non-secure key generation + 0x44 + 32 + 0x00000000 + 0x80011117 + + + LOCK_NSC_CTL + block non-secure state key setting being changed + 31 + 1 + read-write + + + SK_VAL + session key valid +0: session key is all 0's and not usable +1: session key is valid + 16 + 1 + read-only + + + SMK_SEL + software symmetric key selection +0: use scramble version of software symmetric key +1: use origin value in software symmetric key + 12 + 1 + read-write + + + ZMK_SEL + batt symmetric key selection +0: use scramble version of software symmetric key +1: use origin value in software symmetric key + 8 + 1 + read-write + + + FMK_SEL + fuse symmetric key selection +0: use scramble version of fuse symmetric key +1: use origin value in fuse symmetric key + 4 + 1 + read-write + + + KEY_SEL + non-secure symmtric key synthesize setting, key is a XOR of following +bit0: fuse mk, 0: not selected, 1:selected +bit1: zmk from batt, 0: not selected, 1:selected +bit2: software key 0: not selected, 1:selected + 0 + 3 + read-write + + + + + RNG + Random number interface behavior + 0x48 + 32 + 0x00000000 + 0x00010001 + + + BLOCK_RNG_XOR + block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset +0: RNG_XOR can be changed by software +1: RNG_XOR ignore software change from software + 16 + 1 + read-write + + + RNG_XOR + control how SFK is accepted from random number generator +0: SFK value replaced by random number input +1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG + 0 + 1 + read-write + + + + + READ_CONTROL + key read out control + 0x4c + 32 + 0x00000000 + 0x00010001 + + + BLOCK_PK_READ + asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset +0: key can be read out +1: key cannot be read out + 16 + 1 + read-write + + + BLOCK_SMK_READ + symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset +0: key can be read out +1: key cannot be read out + 0 + 1 + read-write + + + + + + + PWM0 + PWM0 + PWM + 0xf0200000 + + 0x0 + 0x424 + registers + + + + unlk + Shadow registers unlock register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHUNLK + write 0xB0382607 to unlock the shadow registers of register offset from 0x04 to 0x78, +otherwise the shadow registers can not be written. + 0 + 32 + read-write + + + + + sta + Counter start register + UNION_STA + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + XSTA + pwm timer counter extended start point, should back to this value after reach xrld + 28 + 4 + read-write + + + STA + pwm timer counter start value + sta/rld will be loaded from shadow register to work register at main counter reload time, or software write unlk.shunlk + 4 + 24 + read-write + + + + + sta_hrpwm + Counter start register + UNION_STA + 0x4 + 32 + 0x00000000 + 0xFFFFFF00 + + + STA + No description available + 8 + 24 + read-write + + + + + rld + Counter reload register + UNION_RLD + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + XRLD + timeout counter extended reload point, counter will reload to xsta after reach this point + 28 + 4 + read-write + + + RLD + pwm timer counter reload value + 4 + 24 + read-write + + + + + rld_hrpwm + Counter reload register + UNION_RLD + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RLD + No description available + 8 + 24 + read-write + + + RLD_HR + pwm timer counter reload value at high resolution, only exist if hwpwm is enabled. + 0 + 8 + read-write + + + + + 16 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + CMP[%s] + no description available + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, +and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + 16 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + CMP_HRPWM[%s] + no description available + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + No description available + 8 + 24 + read-write + + + CMP_HR + high resolution compare value + 0 + 8 + read-write + + + + + frcmd + Force output mode register + 0x78 + 32 + 0x00000000 + 0x0000FFFF + + + FRCMD + 2bit for each PWM output channel (0-7); +00: force output 0 +01: force output 1 +10: output highz +11: no force + 0 + 16 + read-write + + + + + shlk + Shadow registers lock register + 0x7c + 32 + 0x00000000 + 0x80000000 + + + SHLK + write 1 to lock all shawdow register, write access is not permitted + 31 + 1 + read-write + + + + + 16 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + CHCFG[%s] + no description available + 0x80 + 32 + 0x00000000 + 0xFFFF0003 + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + + + gcr + Global control register + 0xf0 + 32 + 0x00000000 + 0xFDFFFFFF + + + FAULTI3EN + 1- enable the internal fault input 3 + 31 + 1 + read-write + + + FAULTI2EN + 1- enable the internal fault input 2 + 30 + 1 + read-write + + + FAULTI1EN + 1- enable the internal fault input 1 + 29 + 1 + read-write + + + FAULTI0EN + 1- enable the internal fault input 0 + 28 + 1 + read-write + + + DEBUGFAULT + 1- enable debug mode output protection + 27 + 1 + read-write + + + FRCPOL + polarity of input pwm_force, +1- active low +0- active high + 26 + 1 + read-write + + + HWSHDWEDG + When hardware event is selected as shawdow register effective time and the select comparator is configured as input capture mode. +This bit assign its which edge is used as compare shadow register hardware load event. +1- Falling edge +0- Rising edge + 24 + 1 + read-write + + + CMPSHDWSEL + This bitfield select one of the comparators as hardware event time to load comparator shadow registers + 19 + 5 + read-write + + + FAULTRECEDG + When hardware load is selected as output fault recover trigger and the selected channel is capture mode. +This bit assign its effective edge of fault recover trigger. +1- Falling edge +0- Rising edge + 18 + 1 + read-write + + + FAULTRECHWSEL + Selec one of the 24 comparators as fault output recover trigger. + 13 + 5 + read-write + + + FAULTE1EN + 1- enable the external fault input 1 + 12 + 1 + read-write + + + FAULTE0EN + 1- enable the external fault input 0 + 11 + 1 + read-write + + + FAULTEXPOL + external fault polarity +1-active low +0-active high + 9 + 2 + read-write + + + RLDSYNCEN + 1- pwm timer counter reset to reload value (rld) by synci is enabled + 8 + 1 + read-write + + + CEN + 1- enable the pwm timer counter +0- stop the pwm timer counter + 7 + 1 + read-write + + + FAULTCLR + 1- Write 1 to clear the fault condition. The output will recover if FAULTRECTIME is set to 2b'11. +User should write 1 to this bit after the active FAULT signal de-assert and before it re-assert again. + 6 + 1 + read-write + + + XRLDSYNCEN + 1- pwm timer extended counter (xcnt) reset to extended reload value (xrld) by synci is enabled + 5 + 1 + read-write + + + HR_PWM_EN + set to enable high resolution pwm, trig_cmp, start/reload register will have different definition. + 4 + 1 + read-write + + + TIMERRESET + set to clear current timer(total 28bit, main counter and tmout_count ). Auto clear + 3 + 1 + read-write + + + FRCTIME + This bit field select the force effective time +00: force immediately +01: force at main counter reload time +10: force at FRCSYNCI +11: no force + 1 + 2 + write-only + + + SWFRC + 1- write 1 to enable software force, if the frcsrcsel is set to 0, force will take effect + 0 + 1 + read-write + + + + + shcr + Shadow register control register + 0xf4 + 32 + 0x00000000 + 0x0000FFFF + + + CNT_UPDATE_RELOAD + set to update counter working register at reload point, clear to use cnt_update_time as old version. + 15 + 1 + read-write + + + CNT_UPDATE_EDGE + 0 for posedge; 1 for negedge if hardware trigger time is selected for update_time, and selected channel is capture mode, for counter shadow registers + 14 + 1 + read-write + + + FORCE_UPDATE_EDGE + 0 for posedge; 1 for negedge if hardware trigger time is selected for update_time, and selected channel is capture mode, for FRCMD shadow registers + 13 + 1 + read-write + + + FRCSHDWSEL + This bitfield select one of the comparators as hardware event time to load FRCMD shadow registers + 8 + 5 + read-write + + + CNTSHDWSEL + This bitfield select one of the comparators as hardware event time to load the counter related shadow registers (STA and RLD) + 3 + 5 + read-write + + + CNTSHDWUPT + This bitfield select when the counter related shadow registers (STA and RLD) will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 1 + 2 + read-write + + + SHLKEN + 1- enable shadow registers lock feature, +0- disable shadow registers lock, shlk bit will always be 0 + 0 + 1 + read-write + + + + + 16 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + CAPPOS[%s] + no description available + 0x100 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + cnt + Counter + 0x170 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCNT + current extended counter value + 28 + 4 + read-only + + + CNT + current clock counter value + 4 + 24 + read-only + + + + + 16 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + CAPNEG[%s] + no description available + 0x180 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + cntcopy + Counter copy + 0x1f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCNT + current extended counter value + 28 + 4 + read-only + + + CNT + current clock counter value + 4 + 24 + read-only + + + + + 8 + 0x4 + 0,1,2,3,4,5,6,7 + PWMCFG[%s] + no description available + 0x200 + 32 + 0x00000000 + 0x3FFFFFFF + + + HR_UPDATE_MODE + 0: update the hr value for the first edge at reload point; +1: update the hr value for the first edge at the last edge; +all others will be updated at previous edge +for pair mode, only pwm_cfg 0/2/4/6 are used + 29 + 1 + read-write + + + OEN + PWM output enable +1- output is enabled +0- output is disabled + 28 + 1 + read-write + + + FRCSHDWUPT + This bitfield select when the FRCMD shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 26 + 2 + read-write + + + FAULTMODE + This bitfield defines the PWM output status when fault condition happen +00: force output 0 +01: force output 1 +1x: output highz + 24 + 2 + read-write + + + FAULTRECTIME + This bitfield select when to recover PWM output after fault condition removed. +00: immediately +01: after pwm timer counter reload time +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after software write faultclr bit in GCR register + 22 + 2 + read-write + + + FRCSRCSEL + Select sources for force output +0- force output is enabled when FRCI assert +1- force output is enabled by software write swfrc to 1 + 21 + 1 + read-write + + + PAIR + 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. +0- PWM output is in indepandent mode. + 20 + 1 + read-write + + + DEADAREA + This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. +Note: user should configure pair bit and this bitfield before PWM output is enabled. + 0 + 20 + read-write + + + + + sr + Status register + 0x220 + 32 + 0x00000000 + 0x0FFFFFFF + + + FAULTF + fault condition flag + 27 + 1 + write-only + + + XRLDF + extended reload flag, this flag set when xcnt count to xrld value or when SYNCI assert + 26 + 1 + write-only + + + HALFRLDF + half reload flag, this flag set when cnt count to rld/2 + 25 + 1 + write-only + + + RLDF + reload flag, this flag set when cnt count to rld value or when SYNCI assert + 24 + 1 + write-only + + + CMPFX + comparator output compare or input capture flag + 0 + 24 + write-only + + + + + irqen + Interrupt request enable register + 0x224 + 32 + 0x00000000 + 0x0FFFFFFF + + + FAULTIRQE + fault condition interrupt enable + 27 + 1 + read-write + + + XRLDIRQE + extended reload flag interrupt enable + 26 + 1 + read-write + + + HALFRLDIRQE + half reload flag interrupt enable + 25 + 1 + read-write + + + RLDIRQE + reload flag interrupt enable + 24 + 1 + read-write + + + CMPIRQEX + comparator output compare or input capture flag interrupt enable + 0 + 24 + read-write + + + + + dmaen + DMA request enable register + 0x22c + 32 + 0x00000000 + 0x0FFFFFFF + + + FAULTEN + fault condition DMA request enable + 27 + 1 + read-write + + + XRLDEN + extended reload flag DMA request enable + 26 + 1 + read-write + + + HALFRLDEN + half reload flag DMA request enable + 25 + 1 + read-write + + + RLDEN + reload flag DMA request enable + 24 + 1 + read-write + + + CMPENX + comparator output compare or input capture flag DMA request enable + 0 + 24 + read-write + + + + + 16 + 0x4 + cmpcfg0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + CMPCFG[%s] + no description available + 0x230 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + + + 8 + 0x4 + 0,1,2,3,4,5,6,7 + ANASTS[%s] + no description available + 0x400 + 32 + 0x00000000 + 0x80000000 + + + CALON + calibration status. +will be set by hardware after setting cal_start. +cleared after calibration finished + 31 + 1 + read-only + + + + + hrpwm_cfg + hrpwm config register + 0x420 + 32 + 0x00000000 + 0x000000FF + + + CAL_START + calibration start. +software setting this bit to start calibration process. +each bit for one channel. + 0 + 8 + write-only + + + + + + + PWM1 + PWM1 + PWM + 0xf0210000 + + + PWM2 + PWM2 + PWM + 0xf0220000 + + + PWM3 + PWM3 + PWM + 0xf0230000 + + + HALL0 + HALL0 + HALL + 0xf0204000 + + 0x0 + 0x88 + registers + + + + cr + Control Register + 0x0 + 32 + 0x00000000 + 0x8001083F + + + READ + 1- load ucnt, vcnt, wcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 + 31 + 1 + write-only + + + SNAPEN + 1- load ucnt, vcnt, wcnt and tmrcnt into their snap registers when snapi input assert + 11 + 1 + read-write + + + RSTCNT + set to reset all counter and related snapshots + 4 + 1 + read-write + + + + + phcfg + Phase configure register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DLYSEL + This bit select delay start time: +1- start counting delay after pre-trigger +0- start counting delay after u,v,w toggle + 31 + 1 + read-write + + + DLYCNT + delay clock cycles number + 0 + 24 + read-write + + + + + wdgcfg + Watchdog configure register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + WDGEN + 1- enable wdog counter + 31 + 1 + read-write + + + WDGTO + watch dog timeout value + 0 + 31 + read-write + + + + + uvwcfg + U,V,W configure register + 0xc + 32 + 0x00000000 + 0x07FFFFFF + + + PRECNT + the clock cycle number which the pre flag will set before the next uvw transition + 0 + 24 + read-write + + + + + trgoen + Trigger output enable register + 0x10 + 32 + 0x00000000 + 0xFFE00000 + + + WDGEN + 1- enable trigger output when wdg flag set + 31 + 1 + read-write + + + PHUPTEN + 1- enable trigger output when phupt flag set + 30 + 1 + read-write + + + PHPREEN + 1- enable trigger output when phpre flag set + 29 + 1 + read-write + + + PHDLYEN + 1- enable trigger output when phdly flag set + 28 + 1 + read-write + + + UFEN + 1- enable trigger output when u flag set + 23 + 1 + read-write + + + VFEN + 1- enable trigger output when v flag set + 22 + 1 + read-write + + + WFEN + 1- enable trigger output when w flag set + 21 + 1 + read-write + + + + + readen + Read event enable register + 0x14 + 32 + 0x00000000 + 0xFFE00000 + + + WDGEN + 1- load counters to their read registers when wdg flag set + 31 + 1 + read-write + + + PHUPTEN + 1- load counters to their read registers when phupt flag set + 30 + 1 + read-write + + + PHPREEN + 1- load counters to their read registers when phpre flag set + 29 + 1 + read-write + + + PHDLYEN + 1- load counters to their read registers when phdly flag set + 28 + 1 + read-write + + + UFEN + 1- load counters to their read registers when u flag set + 23 + 1 + read-write + + + VFEN + 1- load counters to their read registers when v flag set + 22 + 1 + read-write + + + WFEN + 1- load counters to their read registers when w flag set + 21 + 1 + read-write + + + + + dmaen + DMA enable register + 0x24 + 32 + 0x00000000 + 0xFFE00000 + + + WDGEN + 1- generate dma request when wdg flag set + 31 + 1 + read-write + + + PHUPTEN + 1- generate dma request when phupt flag set + 30 + 1 + read-write + + + PHPREEN + 1- generate dma request when phpre flag set + 29 + 1 + read-write + + + PHDLYEN + 1- generate dma request when phdly flag set + 28 + 1 + read-write + + + UFEN + 1- generate dma request when u flag set + 23 + 1 + read-write + + + VFEN + 1- generate dma request when v flag set + 22 + 1 + read-write + + + WFEN + 1- generate dma request when w flag set + 21 + 1 + read-write + + + + + sr + Status register + 0x28 + 32 + 0x00000000 + 0xFFE00000 + + + WDGF + watchdog count timeout flag + 31 + 1 + read-write + + + PHUPTF + phase update flag, will set when any of u, v, w signal toggle + 30 + 1 + read-write + + + PHPREF + phase update pre flag, will set PRECNT cycles before any of u, v, w signal toggle + 29 + 1 + read-write + + + PHDLYF + phase update delay flag, will set DLYCNT cycles after any of u, v, w signal toggle or after the phpre flag depands on DLYSEL setting + 28 + 1 + read-write + + + UF + u flag, will set when u signal toggle + 23 + 1 + read-write + + + VF + v flag, will set when v signal toggle + 22 + 1 + read-write + + + WF + w flag, will set when w signal toggle + 21 + 1 + read-write + + + + + irqen + Interrupt request enable register + 0x2c + 32 + 0x00000000 + 0xFFE00000 + + + WDGIE + 1- generate interrupt request when wdg flag set + 31 + 1 + read-write + + + PHUPTIE + 1- generate interrupt request when phupt flag set + 30 + 1 + read-write + + + PHPREIE + 1- generate interrupt request when phpre flag set + 29 + 1 + read-write + + + PHDLYIE + 1- generate interrupt request when phdly flag set + 28 + 1 + read-write + + + UFIE + 1- generate interrupt request when u flag set + 23 + 1 + read-write + + + VFIE + 1- generate interrupt request when v flag set + 22 + 1 + read-write + + + WFIE + 1- generate interrupt request when w flag set + 21 + 1 + read-write + + + + + 4 + 0x10 + current,read,snap0,snap1 + COUNT[%s] + no description available + 0x30 + + w + W counter + 0x0 + 32 + 0x00000000 + 0x0FFFFFFF + + + WCNT + wcnt counter + 0 + 28 + read-only + + + + + v + V counter + 0x4 + 32 + 0x00000000 + 0xCFFFFFFF + + + VCNT + vcnt counter + 0 + 28 + read-only + + + + + u + U counter + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 31 + 1 + read-only + + + USTAT + this bit indicate U state + 30 + 1 + read-only + + + VSTAT + this bit indicate V state + 29 + 1 + read-only + + + WSTAT + this bit indicate W state + 28 + 1 + read-only + + + UCNT + ucnt counter + 0 + 28 + read-only + + + + + tmr + Timer counter + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMER + 32 bit free run timer + 0 + 32 + read-only + + + + + + 3 + 0x8 + u,v,w + HIS[%s] + no description available + 0x70 + + his0 + history register 0 + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + UHIS0 + copy of ucnt when u signal transition from 0 to 1 + 0 + 32 + read-only + + + + + his1 + history register 1 + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + UHIS1 + copy of ucnt when u signal transition from 1 to 0 + 0 + 32 + read-only + + + + + + + + HALL1 + HALL1 + HALL + 0xf0214000 + + + HALL2 + HALL2 + HALL + 0xf0224000 + + + HALL3 + HALL3 + HALL + 0xf0234000 + + + QEI0 + QEI0 + QEI + 0xf0208000 + + 0x0 + 0x80 + registers + + + + cr + Control register + 0x0 + 32 + 0x00000000 + 0x80077F3F + + + READ + 1- load phcnt, zcnt, spdcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 + 31 + 1 + write-only + + + HRSTSPD + 1- reset spdcnt when H assert + 18 + 1 + read-write + + + HRSTPH + 1- reset phcnt when H assert + 17 + 1 + read-write + + + HRSTZ + 1- reset zcnt when H assert + 16 + 1 + read-write + + + PAUSESPD + 1- pause spdcnt when PAUSE assert + 14 + 1 + read-write + + + PAUSEPH + 1- pause phcnt when PAUSE assert + 13 + 1 + read-write + + + PAUSEZ + 1- pause zcnt when PAUSE assert + 12 + 1 + read-write + + + HRDIR1 + 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction) + 11 + 1 + read-write + + + HRDIR0 + 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction) + 10 + 1 + read-write + + + HFDIR1 + 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction) + 9 + 1 + read-write + + + HFDIR0 + 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction) + 8 + 1 + read-write + + + SNAPEN + 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert + 5 + 1 + read-write + + + RSTCNT + 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx + 4 + 1 + read-write + + + ENCTYP + 00-abz; 01-pd; 10-ud; 11-reserved + 0 + 2 + read-write + + + + + phcfg + Phase configure register + 0x4 + 32 + 0x00000000 + 0x007FFFFF + + + ZCNTCFG + 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 +0- zcnt will increment or decrement when Z input assert + 22 + 1 + read-write + + + PHCALIZ + 1- phcnt will set to phidx when Z input assert + 21 + 1 + read-write + + + PHMAX + maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax + 0 + 21 + read-write + + + + + wdgcfg + Watchdog configure register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + WDGEN + 1- enable wdog counter + 31 + 1 + read-write + + + WDGTO + watch dog timeout value + 0 + 31 + read-write + + + + + phidx + Phase index register + 0xc + 32 + 0x00000000 + 0x001FFFFF + + + PHIDX + phcnt reset value, phcnt will reset to phidx when phcaliz set to 1 + 0 + 21 + read-write + + + + + trgoen + Tigger output enable register + 0x10 + 32 + 0x00000000 + 0xF0000000 + + + WDGFEN + 1- enable trigger output when wdg flag set + 31 + 1 + read-write + + + HOMEFEN + 1- enable trigger output when homef flag set + 30 + 1 + read-write + + + POSCMPFEN + 1- enable trigger output when poscmpf flag set + 29 + 1 + read-write + + + ZPHFEN + 1- enable trigger output when zphf flag set + 28 + 1 + read-write + + + + + readen + Read event enable register + 0x14 + 32 + 0x00000000 + 0xF0000000 + + + WDGFEN + 1- load counters to their read registers when wdg flag set + 31 + 1 + read-write + + + HOMEFEN + 1- load counters to their read registers when homef flag set + 30 + 1 + read-write + + + POSCMPFEN + 1- load counters to their read registers when poscmpf flag set + 29 + 1 + read-write + + + ZPHFEN + 1- load counters to their read registers when zphf flag set + 28 + 1 + read-write + + + + + zcmp + Z comparator + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + ZCMP + zcnt postion compare value + 0 + 32 + read-write + + + + + phcmp + Phase comparator + 0x1c + 32 + 0x00000000 + 0xE01FFFFF + + + ZCMPDIS + 1- postion compare not include zcnt + 31 + 1 + read-write + + + DIRCMPDIS + 1- postion compare not include rotation direction + 30 + 1 + read-write + + + DIRCMP + 0- position compare need positive rotation +1- position compare need negative rotation + 29 + 1 + read-write + + + PHCMP + phcnt position compare value + 0 + 21 + read-write + + + + + spdcmp + Speed comparator + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + SPDCMP + spdcnt position compare value + 0 + 32 + read-write + + + + + dmaen + DMA request enable register + 0x24 + 32 + 0x00000000 + 0xF0000000 + + + WDGFEN + 1- generate dma request when wdg flag set + 31 + 1 + read-write + + + HOMEFEN + 1- generate dma request when homef flag set + 30 + 1 + read-write + + + POSCMPFEN + 1- generate dma request when poscmpf flag set + 29 + 1 + read-write + + + ZPHFEN + 1- generate dma request when zphf flag set + 28 + 1 + read-write + + + + + sr + Status register + 0x28 + 32 + 0x00000000 + 0xF0000000 + + + WDGF + watchdog flag + 31 + 1 + read-write + + + HOMEF + home flag + 30 + 1 + read-write + + + POSCMPF + postion compare match flag + 29 + 1 + read-write + + + ZPHF + z input flag + 28 + 1 + read-write + + + + + irqen + Interrupt request register + 0x2c + 32 + 0x00000000 + 0xF0000000 + + + WDGIE + 1- generate interrupt when wdg flag set + 31 + 1 + read-write + + + HOMEIE + 1- generate interrupt when homef flag set + 30 + 1 + read-write + + + POSCMPIE + 1- generate interrupt when poscmpf flag set + 29 + 1 + read-write + + + ZPHIE + 1- generate interrupt when zphf flag set + 28 + 1 + read-write + + + + + 4 + 0x10 + current,read,snap0,snap1 + COUNT[%s] + no description available + 0x30 + + z + Z counter + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + ZCNT + zcnt value + 0 + 32 + read-write + + + + + ph + Phase counter + 0x4 + 32 + 0x00000000 + 0x461FFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 30 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 26 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 25 + 1 + read-only + + + PHCNT + phcnt value + 0 + 21 + read-only + + + + + spd + Speed counter + 0x8 + 32 + 0x00000000 + 0xEFFFFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 31 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 30 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 29 + 1 + read-write + + + SPDCNT + spdcnt value + 0 + 28 + read-only + + + + + tmr + Timer counter + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + TMRCNT + 32 bit free run timer + 0 + 32 + read-only + + + + + + 4 + 0x4 + spdhis0,spdhis1,spdhis2,spdhis3 + SPDHIS[%s] + no description available + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + SPDHIS0 + copy of spdcnt, load from spdcnt after any transition from a = low, b = low + 0 + 32 + read-only + + + + + + + QEI1 + QEI1 + QEI + 0xf0218000 + + + QEI2 + QEI2 + QEI + 0xf0228000 + + + QEI3 + QEI3 + QEI + 0xf0238000 + + + TRGM0 + TRGM0 + TRGM + 0xf020c000 + + 0x0 + 0x404 + registers + + + + 20 + 0x4 + PWM_IN0,PWM_IN1,PWM_IN2,PWM_IN3,PWM_IN4,PWM_IN5,PWM_IN6,PWM_IN7,TRGM_IN0,TRGM_IN1,TRGM_IN2,TRGM_IN3,TRGM_IN4,TRGM_IN5,TRGM_IN6,TRGM_IN7,TRGM_IN8,TRGM_IN9,TRGM_IN10,TRGM_IN11 + FILTCFG[%s] + no description available + 0x0 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + 67 + 0x4 + TRGM_OUT0,TRGM_OUT1,TRGM_OUT2,TRGM_OUT3,TRGM_OUT4,TRGM_OUT5,TRGM_OUT6,TRGM_OUT7,TRGM_OUT8,TRGM_OUT9,TRGM_OUT10,TRGM_OUT11,TRGM_OUTX0,TRGM_OUTX1,PWM_SYNCI,PWM_FRCI,PWM_FRCSYNCI,PWM_SHRLDSYNCI,PWM_FAULTI0,PWM_FAULTI1,PWM_FAULTI2,PWM_FAULTI3,PWM_IN8,PWM_IN9,PWM_IN10,PWM_IN11,PWM_IN12,PWM_IN13,PWM_IN14,PWM_IN15,PLA_IN0,PLA_IN1,PLA_IN2,PLA_IN3,PLA_IN4,PLA_IN5,PLA_IN6,PLA_IN7,QEI_A,QEI_B,QEI_Z,QEI_H,QEI_PAUSE,QEI_SNAPI,HALL_U,HALL_V,HALL_W,HALL_SNAPI,ADC0_STRGI,ADC1_STRGI,ADC2_STRGI,rsv51,ADCx_PTRGI0A,ADCx_PTRGI0B,ADCx_PTRGI0C,GPTMRa_SYNCI,GPTMRa_IN2,GPTMRa_IN3,DAC_BUF_TRIG,DAC0_STEP_TRIG,DAC1_STEP_TRIG,CMPx_WIN,CAN_PTPC0_CAP,CAN_PTPC1_CAP,SDFM_EVT0,SDFM_EVT1,SDFM_EVT2,SDFM_EVT3 + TRGOCFG[%s] + no description available + 0x100 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + 4 + 0x4 + 0,1,2,3 + DMACFG[%s] + no description available + 0x300 + 32 + 0x00000000 + 0x0000001F + + + DMASRCSEL + This field selects one of the DMA requests as the DMA request output. + 0 + 5 + read-write + + + + + GCR + General Control Register + 0x400 + 32 + 0x00000000 + 0x00000FFF + + + TRGOPEN + The bitfield enable the TRGM outputs. + 0 + 12 + read-write + + + + + + + TRGM1 + TRGM1 + TRGM + 0xf021c000 + + + TRGM2 + TRGM2 + TRGM + 0xf022c000 + + + TRGM3 + TRGM3 + TRGM + 0xf023c000 + + + PLA0 + PLA0 + PLA + 0xf020e000 + + 0x0 + 0x420 + registers + + + + 8 + 0x70 + 0,1,2,3,4,5,6,7 + CHN[%s] + no description available + 0x0 + + 8 + 0x4 + AOI_16to8_00,AOI_16to8_01,AOI_16to8_02,AOI_16to8_03,AOI_16to8_04,AOI_16to8_05,AOI_16to8_06,AOI_16to8_07 + AOI_16TO8[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + AOI_8to7_00_01 + CHN&index0 AOI_16to8_00_01 OR logic cfg + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_8TO7_01_7 + select value for AOI_8to7_01_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 30 + 2 + read-write + + + AOI_8TO7_01_6 + select value for AOI_8to7_01_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 28 + 2 + read-write + + + AOI_8TO7_01_5 + select value for AOI_8to7_01_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 26 + 2 + read-write + + + AOI_8TO7_01_4 + select value for AOI_8to7_01_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 24 + 2 + read-write + + + AOI_8TO7_01_3 + select value for AOI_8to7_01_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 22 + 2 + read-write + + + AOI_8TO7_01_2 + select value for AOI_8to7_01_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 20 + 2 + read-write + + + AOI_8TO7_01_1 + select value for AOI_8to7_01_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 18 + 2 + read-write + + + AOI_8TO7_01_0 + select value for AOI_8to7_01_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 16 + 2 + read-write + + + AOI_8TO7_00_7 + select value for AOI_8to7_00_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_00_6 + select value for AOI_8to7_00_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_00_5 + select value for AOI_8to7_00_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_00_4 + select value for AOI_8to7_00_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_00_3 + select value for AOI_8to7_00_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_00_2 + select value for AOI_8to7_00_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_00_1 + select value for AOI_8to7_00_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_00_0 + select value for AOI_8to7_00_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + AOI_8to7_02_03 + CHN&index0 AOI_16to8_02_03 OR logic cfg + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_8TO7_03_7 + select value for AOI_8to7_03_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 30 + 2 + read-write + + + AOI_8TO7_03_6 + select value for AOI_8to7_03_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 28 + 2 + read-write + + + AOI_8TO7_03_5 + select value for AOI_8to7_03_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 26 + 2 + read-write + + + AOI_8TO7_03_4 + select value for AOI_8to7_03_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 24 + 2 + read-write + + + AOI_8TO7_03_3 + select value for AOI_8to7_03_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 22 + 2 + read-write + + + AOI_8TO7_03_2 + select value for AOI_8to7_03_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 20 + 2 + read-write + + + AOI_8TO7_03_1 + select value for AOI_8to7_03_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 18 + 2 + read-write + + + AOI_8TO7_03_0 + select value for AOI_8to7_03_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 16 + 2 + read-write + + + AOI_8TO7_02_7 + select value for AOI_8to7_02_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_02_6 + select value for AOI_8to7_02_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_02_5 + select value for AOI_8to7_02_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_02_4 + select value for AOI_8to7_02_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_02_3 + select value for AOI_8to7_02_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_02_2 + select value for AOI_8to7_02_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_02_1 + select value for AOI_8to7_02_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_02_0 + select value for AOI_8to7_02_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + AOI_8to7_04_05 + CHN&index0 AOI_16to8_04_05 OR logic cfg + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_8TO7_05_7 + select value for AOI_8to7_05_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 30 + 2 + read-write + + + AOI_8TO7_05_6 + select value for AOI_8to7_05_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 28 + 2 + read-write + + + AOI_8TO7_05_5 + select value for AOI_8to7_05_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 26 + 2 + read-write + + + AOI_8TO7_05_4 + select value for AOI_8to7_05_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 24 + 2 + read-write + + + AOI_8TO7_05_3 + select value for AOI_8to7_05_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 22 + 2 + read-write + + + AOI_8TO7_05_2 + select value for AOI_8to7_05_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 20 + 2 + read-write + + + AOI_8TO7_05_1 + select value for AOI_8to7_05_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 18 + 2 + read-write + + + AOI_8TO7_05_0 + select value for AOI_8to7_05_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 16 + 2 + read-write + + + AOI_8TO7_04_7 + select value for AOI_8to7_04_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_04_6 + select value for AOI_8to7_04_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_04_5 + select value for AOI_8to7_04_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_04_4 + select value for AOI_8to7_04_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_04_3 + select value for AOI_8to7_04_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_04_2 + select value for AOI_8to7_04_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_04_1 + select value for AOI_8to7_04_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_04_0 + select value for AOI_8to7_04_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + AOI_8to7_06 + CHN&index0 AOI_16to8_06 OR logic cfg + 0x2c + 32 + 0x00000000 + 0x0000FFFF + + + AOI_8TO7_06_7 + select value for AOI_8to7_06_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_06_6 + select value for AOI_8to7_06_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_06_5 + select value for AOI_8to7_06_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_06_4 + select value for AOI_8to7_06_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_06_3 + select value for AOI_8to7_06_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_06_2 + select value for AOI_8to7_06_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_06_1 + select value for AOI_8to7_06_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_06_0 + select value for AOI_8to7_06_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + 8 + 0x4 + SECOND_FILTER_0,SECOND_FILTER_1,SECOND_FILTER_2,SECOND_FILTER_3,SECOND_FILTER_4,SECOND_FILTER_5,SECOND_FILTER_6,SECOND_FILTER_7 + FILTER_2ND[%s] + no description available + 0x30 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + 7 + 0x4 + THIRD_FILTER_0,THIRD_FILTER_1,THIRD_FILTER_2,THIRD_FILTER_3,THIRD_FILTER_4,THIRD_FILTER_5,THIRD_FILTER_6 + FILTER_3RD[%s] + no description available + 0x50 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CFG_FF + CHN&index0 cfg ff + 0x6c + 32 + 0x00000000 + 0x0003001F + + + OSC_LOOP_CLAMP_VALUE + osc loop clamp value when osc ring active. +0: clamp 0. +1: clamp 1. + 17 + 1 + read-write + + + DIS_OSC_LOOP_CLAMP + disable osc loop clamp. +0: enable osc loop clamp when osc ring active. +1: disable or clean current osc loop clamp. + 16 + 1 + read-write + + + SEL_ADDER_MINUS + 0: select adder when cfg_adder_minus active. +1: select minus when cfg_adder_minus active. + 4 + 1 + read-write + + + SEL_CLK_SOURCE + cfg_ff clock source. +0: system clock. +1: use 3rd_filter_2 as clock. + 3 + 1 + read-write + + + SEL_CFG_FF_TYPE + cfg_ff type. +0: DFF. +1: 3rd_filter_0. +2: dual-edge DFF. +3: Trigger FF. +4: JK FF. +5. latch. +6: full adder/minus. + 0 + 3 + read-write + + + + + + 8 + 0x4 + FRIST_FILTER_PLA_IN_0,FRIST_FILTER_PLA_IN_1,FRIST_FILTER_PLA_IN_2,FRIST_FILTER_PLA_IN_3,FRIST_FILTER_PLA_IN_4,FRIST_FILTER_PLA_IN_5,FRIST_FILTER_PLA_IN_6,FRIST_FILTER_PLA_IN_7 + FILTER_1ST_PLA_IN[%s] + no description available + 0x3c0 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + 9 + 0x4 + FRIST_FILTER_PLA_IN_0,FRIST_FILTER_PLA_OUT_0,FRIST_FILTER_PLA_OUT_1,FRIST_FILTER_PLA_OUT_2,FRIST_FILTER_PLA_OUT_3,FRIST_FILTER_PLA_OUT_4,FRIST_FILTER_PLA_OUT_5,FRIST_FILTER_PLA_OUT_6,FRIST_FILTER_PLA_OUT_7 + FILTER_1ST_PLA_OUT[%s] + no description available + 0x3e0 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + 8 + 0x4 + CFG_ACTIVE_CHN0,CFG_ACTIVE_CHN1,CFG_ACTIVE_CHN2,CFG_ACTIVE_CHN3,CFG_ACTIVE_CHN4,CFG_ACTIVE_CHN5,CFG_ACTIVE_CHN6,CFG_ACTIVE_CHN7 + CHN_CFG_ACTIVE[%s] + no description available + 0x400 + 32 + 0x00000000 + 0x0000FFFF + + + CFG_ACTIVE + write 0xF00D to enable all setting. Otherwire, all setting inactive. + 0 + 16 + read-write + + + + + + + PLA1 + PLA1 + PLA + 0xf021e000 + + + SYNT + SYNT + SYNT + 0xf0240000 + + 0x0 + 0x30 + registers + + + + gcr + Global control register + 0x0 + 32 + 0x00000000 + 0x00000003 + + + CRST + 1- Reset counter + 1 + 1 + read-write + + + CEN + 1- Enable counter + 0 + 1 + read-write + + + + + rld + Counter reload register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RLD + counter reload value + 0 + 32 + read-write + + + + + cnt + Counter + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + CNT + counter + 0 + 32 + read-only + + + + + 4 + 0x4 + 0,1,2,3 + CMP[%s] + no description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + comparator value, the output will assert when counter count to this value + 0 + 32 + read-write + + + + + + + USB0 + USB0 + USB + 0xf2020000 + + 0x80 + 0x1a8 + registers + + + + GPTIMER0LD + General Purpose Timer #0 Load Register + 0x80 + 32 + 0x00000000 + 0x00FFFFFF + + + GPTLD + GPTLD +General Purpose Timer Load Value +These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. +This value represents the time in microseconds minus 1 for the timer duration. +Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. +NOTE: Max value is 0xFFFFFF or 16.777215 seconds. + 0 + 24 + read-write + + + + + GPTIMER0CTRL + General Purpose Timer #0 Controller Register + 0x84 + 32 + 0x00000000 + 0xC1FFFFFF + + + GPTRUN + GPTRUN +General Purpose Timer Run +GPTCNT bits are not effected when setting or clearing this bit. +0 - Stop counting +1 - Run + 31 + 1 + read-write + + + GPTRST + GPTRST +General Purpose Timer Reset +0 - No action +1 - Load counter value from GPTLD bits in n_GPTIMER0LD + 30 + 1 + write-only + + + GPTMODE + GPTMODE +General Purpose Timer Mode +In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is +reset by software; +In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the +counter value from GPTLD bits to start again. +0 - One Shot Mode +1 - Repeat Mode + 24 + 1 + read-write + + + GPTCNT + GPTCNT +General Purpose Timer Counter. +This field is the count value of the countdown timer. + 0 + 24 + read-only + + + + + GPTIMER1LD + General Purpose Timer #1 Load Register + 0x88 + 32 + 0x00000000 + 0x00FFFFFF + + + GPTLD + GPTLD +General Purpose Timer Load Value +These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. +This value represents the time in microseconds minus 1 for the timer duration. +Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. +NOTE: Max value is 0xFFFFFF or 16.777215 seconds. + 0 + 24 + read-write + + + + + GPTIMER1CTRL + General Purpose Timer #1 Controller Register + 0x8c + 32 + 0x00000000 + 0xC1FFFFFF + + + GPTRUN + GPTRUN +General Purpose Timer Run +GPTCNT bits are not effected when setting or clearing this bit. +0 - Stop counting +1 - Run + 31 + 1 + read-write + + + GPTRST + GPTRST +General Purpose Timer Reset +0 - No action +1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD + 30 + 1 + write-only + + + GPTMODE + GPTMODE +General Purpose Timer Mode +In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is +reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and +automatically reload the counter value from GPTLD bits to start again. +0 - One Shot Mode +1 - Repeat Mode + 24 + 1 + read-write + + + GPTCNT + GPTCNT +General Purpose Timer Counter. +This field is the count value of the countdown timer. + 0 + 24 + read-only + + + + + SBUSCFG + System Bus Config Register + 0x90 + 32 + 0x00000000 + 0x00000007 + + + AHBBRST + AHBBRST +AHB master interface Burst configuration +These bits control AHB master transfer type sequence (or priority). +NOTE: This register overrides n_BURSTSIZE register when its value is not zero. +000 - Incremental burst of unspecified length only +001 - INCR4 burst, then single transfer +010 - INCR8 burst, INCR4 burst, then single transfer +011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer +100 - Reserved, don't use +101 - INCR4 burst, then incremental burst of unspecified length +110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length +111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length + 0 + 3 + read-write + + + + + USBCMD + USB Command Register + 0x140 + 32 + 0x00080000 + 0x00FFEB7F + + + ITC + ITC +Interrupt Threshold Control -Read/Write. +The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. +ITC contains the maximum interrupt interval measured in micro-frames. Valid values are +shown below. +Value Maximum Interrupt Interval +00000000 - Immediate (no threshold) +00000001 - 1 micro-frame +00000010 - 2 micro-frames +00000100 - 4 micro-frames +00001000 - 8 micro-frames +00010000 - 16 micro-frames +00100000 - 32 micro-frames +01000000 - 64 micro-frames + 16 + 8 + read-write + + + FS_2 + FS_2 +Frame List Size - (Read/Write or Read Only). [host mode only] +This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. +This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. +NOTE: This field is made up from USBCMD bits 15, 3 and 2. +Value Meaning +0b000 - 1024 elements (4096 bytes) Default value +0b001 - 512 elements (2048 bytes) +0b010 - 256 elements (1024 bytes) +0b011 - 128 elements (512 bytes) +0b100 - 64 elements (256 bytes) +0b101 - 32 elements (128 bytes) +0b110 - 16 elements (64 bytes) +0b111 - 8 elements (32 bytes) + 15 + 1 + read-write + + + ATDTW + ATDTW +Add dTD TripWire - Read/Write. [device mode only] +This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's +linked list. This bit is set and cleared by software. +This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD +to a primed endpoint may go unrecognized. + 14 + 1 + read-write + + + SUTW + SUTW +Setup TripWire - Read/Write. [device mode only] +This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. +If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then +there is a hazard when new setup data arrives while the DCD is copying the setup data payload +from the QH for a previous setup packet. This bit is set and cleared by software. +This bit would also be cleared by hardware when a hazard detected. + 13 + 1 + read-write + + + ASPE + ASPE +Asynchronous Schedule Park Mode Enable - Read/Write. +If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. +Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. +When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. +NOTE: ASPE bit reset value: '0b' for OTG controller . + 11 + 1 + read-write + + + ASP + ASP +Asynchronous Schedule Park Mode Count - Read/Write. +If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. +It contains a count of the number of successive transactions the host controller is allowed to +execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. +Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. +This field is set to 3h in all controller core. + 8 + 2 + read-write + + + IAA + IAA +Interrupt on Async Advance Doorbell - Read/Write. +This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. +When the host controller has evicted all appropriate cached schedule states, +it sets the Interrupt on Async Advance status bit in the USBSTS register. +If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. +The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. +Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. +This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. + 6 + 1 + read-write + + + ASE + ASE +Asynchronous Schedule Enable - Read/Write. Default 0b. +This bit controls whether the host controller skips processing the Asynchronous Schedule. +Only the host controller uses this bit. +Values Meaning +0 - Do not process the Asynchronous Schedule. +1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. + 5 + 1 + read-write + + + PSE + PSE +Periodic Schedule Enable- Read/Write. Default 0b. +This bit controls whether the host controller skips processing the Periodic Schedule. +Only the host controller uses this bit. +Values Meaning +0 - Do not process the Periodic Schedule +1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. + 4 + 1 + read-write + + + FS_1 + FS_1 +See description at bit 15 + 2 + 2 + read-write + + + RST + RST +Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. +This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. +Host operation mode: +When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. +Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. +Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. +Attempting to reset an actively running host controller will result in undefined behavior. +Device operation mode: +When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. +Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. +In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. + 1 + 1 + read-write + + + RS + RS +Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. +Host operation mode: +When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. +When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. +The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. +Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). +Device operation mode: +Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. +This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. +Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. + 0 + 1 + read-write + + + + + USBSTS + USB Status Register + 0x144 + 32 + 0x00000000 + 0x030DF1FF + + + TI1 + TI1 +General Purpose Timer Interrupt 1(GPTINT1)--R/WC. +This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this +bit will clear it. + 25 + 1 + read-write + + + TI0 + TI0 +General Purpose Timer Interrupt 0(GPTINT0)--R/WC. +This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this +bit clears it. + 24 + 1 + read-write + + + UPI + USB Host Periodic Interrupt – RWC. Default = 0b. +This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction +where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. +This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. +A short packet is when the actual number of bytes received was less than expected. +This bit is not used by the device controller and will always be zero. + 19 + 1 + read-write + + + UAI + USB Host Asynchronous Interrupt – RWC. Default = 0b. +This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction +where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. +This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. +A short packet is when the actual number of bytes received was less than expected. +This bit is not used by the device controller and will always be zero + 18 + 1 + read-write + + + NAKI + NAKI +NAK Interrupt Bit--RO. +This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and +corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware +when all Enabled TX/RX Endpoint NAK bits are cleared. + 16 + 1 + read-only + + + AS + AS +Asynchronous Schedule Status - Read Only. +This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. +The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. +When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). +Only used in the host operation mode. + 15 + 1 + read-only + + + PS + PS +Periodic Schedule Status - Read Only. +This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. +The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. +When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). +Only used in the host operation mode. + 14 + 1 + read-only + + + RCL + RCL +Reclamation - Read Only. +This is a read-only status bit used to detect an empty asynchronous schedule. +Only used in the host operation mode. + 13 + 1 + read-only + + + HCH + HCH +HCHaIted - Read Only. +This bit is a zero whenever the Run/Stop bit is a one. + The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, + either by software or by the Controller hardware (for example, an internal error). +Only used in the host operation mode. +Default value is '0b' for OTG core . +This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE +register. +NOTE: HCH bit reset value: '0b' for OTG controller core . + 12 + 1 + read-only + + + SLI + SLI +DCSuspend - R/WC. +When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. +Only used in device operation mode. + 8 + 1 + read-write + + + SRI + SRI +SOF Received - R/WC. +When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. +When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. +Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. +Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. +In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. +Software writes a 1 to this bit to clear it. + 7 + 1 + read-write + + + URI + URI +USB Reset Received - R/WC. +When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. +Software can write a 1 to this bit to clear the USB Reset Received status bit. +Only used in device operation mode. + 6 + 1 + read-write + + + AAI + AAI +Interrupt on Async Advance - R/WC. +System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule +by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. +Only used in host operation mode. + 5 + 1 + read-write + + + SEI + System Error – RWC. Default = 0b. +In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. +In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) + 4 + 1 + read-write + + + FRI + FRI +Frame List Rollover - R/WC. +The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to +zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the +frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the +Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host +Controller sets this bit to a one every time FHINDEX [12] toggles. +Only used in host operation mode. + 3 + 1 + read-write + + + PCI + PCI +Port Change Detect - R/WC. +The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, +or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. +The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. +When the port controller exits the full or high-speed operation states due to Reset or Suspend events, +the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. + 2 + 1 + read-write + + + UEI + UEI +USB Error Interrupt (USBERRINT) - R/WC. +When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. +This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. + 1 + 1 + read-write + + + UI + UI +USB Interrupt (USBINT) - R/WC. +This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB +transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. +This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when +the actual number of bytes received was less than the expected number of bytes. + 0 + 1 + read-write + + + + + USBINTR + Interrupt Enable Register + 0x148 + 32 + 0x00000000 + 0x030D01FF + + + TIE1 + TIE1 +General Purpose Timer #1 Interrupt Enable +When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. + 25 + 1 + read-write + + + TIE0 + TIE0 +General Purpose Timer #0 Interrupt Enable +When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. + 24 + 1 + read-write + + + UPIE + UPIE +USB Host Periodic Interrupt Enable +When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an +interrupt at the next interrupt threshold. + 19 + 1 + read-write + + + UAIE + UAIE +USB Host Asynchronous Interrupt Enable +When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an +interrupt at the next interrupt threshold. + 18 + 1 + read-write + + + NAKE + NAKE +NAK Interrupt Enable +When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. + 16 + 1 + read-only + + + SLE + SLE +Sleep Interrupt Enable +When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. +Only used in device operation mode. + 8 + 1 + read-write + + + SRE + SRE +SOF Received Interrupt Enable +When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. + 7 + 1 + read-write + + + URE + URE +USB Reset Interrupt Enable +When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in device operation mode. + 6 + 1 + read-write + + + AAE + AAE +Async Advance Interrupt Enable +When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in host operation mode. + 5 + 1 + read-write + + + SEE + SEE +System Error Interrupt Enable +When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in host operation mode. + 4 + 1 + read-write + + + FRE + FRE +Frame List Rollover Interrupt Enable +When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in host operation mode. + 3 + 1 + read-write + + + PCE + PCE +Port Change Detect Interrupt Enable +When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. + 2 + 1 + read-write + + + UEE + UEE +USB Error Interrupt Enable +When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. + 1 + 1 + read-write + + + UE + UE +USB Interrupt Enable +When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. + 0 + 1 + read-write + + + + + FRINDEX + USB Frame Index Register + 0x14c + 32 + 0x00000000 + 0x00003FFF + + + FRINDEX + FRINDEX +Frame Index. +The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. +This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. +The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. +USBCMD [Frame List Size] Number Elements N +In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. +In either mode bits 2:0 indicate the current microframe. +The bit field values description below is represented as (Frame List Size) Number Elements N. +00000000000000 - (1024) 12 +00000000000001 - (512) 11 +00000000000010 - (256) 10 +00000000000011 - (128) 9 +00000000000100 - (64) 8 +00000000000101 - (32) 7 +00000000000110 - (16) 6 +00000000000111 - (8) 5 + 0 + 14 + read-write + + + + + DEVICEADDR + Device Address Register + UNION_154 + 0x154 + 32 + 0x00000000 + 0xFF000000 + + + USBADR + USBADR +Device Address. +These bits correspond to the USB device address + 25 + 7 + read-write + + + USBADRA + USBADRA +Device Address Advance. Default=0. +When this bit is '0', any writes to USBADR are instantaneous. + When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. +After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. +Hardware will automatically clear this bit on the following conditions: +1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). +2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). +3) Device Reset occurs (USBADR is reset to 0). +NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. +This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. +If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), +the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. + 24 + 1 + read-write + + + + + PERIODICLISTBASE + Frame List Base Address Register + UNION_154 + 0x154 + 32 + 0x00000000 + 0xFFFFF000 + + + BASEADR + BASEADR +Base Address (Low). +These bits correspond to memory address signals [31:12], respectively. +Only used by the host controller. + 12 + 20 + read-write + + + + + ASYNCLISTADDR + Next Asynch. Address Register + UNION_158 + 0x158 + 32 + 0x00000000 + 0xFFFFFFE0 + + + ASYBASE + ASYBASE +Link Pointer Low (LPL). +These bits correspond to memory address signals [31:5], respectively. This field may only reference a +Queue Head (QH). +Only used by the host controller. + 5 + 27 + read-write + + + + + ENDPTLISTADDR + Endpoint List Address Register + UNION_158 + 0x158 + 32 + 0x00000000 + 0xFFFFF800 + + + EPBASE + EPBASE +Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. +This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). + 11 + 21 + read-write + + + + + BURSTSIZE + Programmable Burst Size Register + 0x160 + 32 + 0x00000000 + 0x0000FFFF + + + TXPBURST + TXPBURST +Programmable TX Burst Size. +Default value is determined by TXBURST bits in n_HWTXBUF. +This register represents the maximum length of a the burst in 32-bit words while moving data from system +memory to the USB bus. + 8 + 8 + read-write + + + RXPBURST + RXPBURST +Programmable RX Burst Size. +Default value is determined by TXBURST bits in n_HWRXBUF. +This register represents the maximum length of a the burst in 32-bit words while moving data from the +USB bus to system memory. + 0 + 8 + read-write + + + + + TXFILLTUNING + TX FIFO Fill Tuning Register + 0x164 + 32 + 0x00000000 + 0x003F1F7F + + + TXFIFOTHRES + TXFIFOTHRES +FIFO Burst Threshold. (Read/Write) +This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. +The minimum value is 2 and this value should be a low as possible to maximize USB performance. +A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth +where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. +This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. + 16 + 6 + read-write + + + TXSCHHEALTH + TXSCHHEALTH +Scheduler Health Counter. (Read/Write To Clear) +Table continues on the next page +This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES +before running out of time to send the packet before the next Start-Of-Frame. +This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. +Writing to this register will clear the counter and this counter will max. at 31. + 8 + 5 + read-write + + + TXSCHOH + TXSCHOH +Scheduler Overhead. (Read/Write) [Default = 0] +This register adds an additional fixed offset to the schedule time estimator described above as Tff. +As an approximation, the value chosen for this register should limit the number of back-off events captured +in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. +Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. +The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. +The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. +Default value is '08h' for OTG controller core . + 0 + 7 + read-write + + + + + ENDPTNAK + Endpoint NAK Register + 0x178 + 32 + 0x00000000 + 0xFFFFFFFF + + + EPTN + EPTN +TX Endpoint NAK - R/WC. +Each TX endpoint has 1 bit in this field. The bit is set when the +device sends a NAK handshake on a received IN token for the corresponding endpoint. +Bit [N] - Endpoint #[N], N is 0-7 + 16 + 16 + read-write + + + EPRN + EPRN +RX Endpoint NAK - R/WC. +Each RX endpoint has 1 bit in this field. The bit is set when the +device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. +Bit [N] - Endpoint #[N], N is 0-7 + 0 + 16 + read-write + + + + + ENDPTNAKEN + Endpoint NAK Enable Register + 0x17c + 32 + 0x00000000 + 0xFFFFFFFF + + + EPTNE + EPTNE +TX Endpoint NAK Enable - R/W. +Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the +corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. +Bit [N] - Endpoint #[N], N is 0-7 + 16 + 16 + read-write + + + EPRNE + EPRNE +RX Endpoint NAK Enable - R/W. +Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the +corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. +Bit [N] - Endpoint #[N], N is 0-7 + 0 + 16 + read-write + + + + + PORTSC1 + Port Status & Control + 0x184 + 32 + 0x00000000 + 0x3DFF1FFF + + + STS + STS +Serial Transceiver Select +1 Serial Interface Engine is selected +0 Parallel Interface signals is selected +Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. +When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. + 29 + 1 + read-write + + + PTW + PTW +Parallel Transceiver Width +This bit has no effect if serial interface engine is used. +0 - Select the 8-bit UTMI interface [60MHz] +1 - Select the 16-bit UTMI interface [30MHz] + 28 + 1 + read-write + + + PSPD + PSPD +Port Speed - Read Only. +This register field indicates the speed at which the port is operating. +00 - Full Speed +01 - Low Speed +10 - High Speed +11 - Undefined + 26 + 2 + read-only + + + PFSC + PFSC +Port Force Full Speed Connect - Read/Write. Default = 0b. +When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp +sequence that allows the port to identify itself as High Speed. +0 - Normal operation +1 - Forced to full speed + 24 + 1 + read-write + + + PHCD + PHCD +PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. +When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY +clock. +NOTE: The PHY clock cannot be disabled if it is being used as the system clock. +In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD +Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend +will be cleared automatically when the host initials resume. Before forcing a resume from the device, the +device controller driver must clear this bit. +In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put +into suspend mode or when no downstream device is connected. Low power suspend is completely +under the control of software. +0 - Enable PHY clock +1 - Disable PHY clock + 23 + 1 + read-write + + + WKOC + WKOC +Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. +Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. +This field is zero if Port Power(PORTSC1) is zero. + 22 + 1 + read-write + + + WKDC + WKDC +Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables +the port to be sensitive to device disconnects as wake-up events. +This field is zero if Port Power(PORTSC1) is zero or in device mode. + 21 + 1 + read-write + + + WKCN + WKCN +Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. +Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. +This field is zero if Port Power(PORTSC1) is zero or in device mode. + 20 + 1 + read-write + + + PTC + PTC +Port Test Control - Read/Write. Default = 0000b. +Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. +The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. +Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. +Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. +NOTE: Low speed operations are not supported as a peripheral device. +Any other value than zero indicates that the port is operating in test mode. +Value Specific Test +0000 - TEST_MODE_DISABLE +0001 - J_STATE +0010 - K_STATE +0011 - SE0 (host) / NAK (device) +0100 - Packet +0101 - FORCE_ENABLE_HS +0110 - FORCE_ENABLE_FS +0111 - FORCE_ENABLE_LS +1000-1111 - Reserved + 16 + 4 + read-write + + + PP + PP +Port Power (PP)-Read/Write or Read Only. +The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: +PPC +PP Operation +0 +1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. +1 +1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). +When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. +When an over-current condition is detected on a powered port and PPC is a one, +the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). +This feature is implemented in all controller cores (PPC = 1). + 12 + 1 + read-write + + + LS + LS +Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal +lines. +In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because +the port controller state machine and the port routing manage the connection of LS and FS. +In device mode, the use of linestate by the device controller driver is not necessary. +The encoding of the bits are: +Bits [11:10] Meaning +00 - SE0 +01 - K-state +10 - J-state +11 - Undefined + 10 + 2 + read-only + + + HSP + HSP +High-Speed Port - Read Only. Default = 0b. +When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the +host/device connected to the port is not in a high-speed mode. +NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. + 9 + 1 + read-only + + + PR + PR +Port Reset - Read/Write or Read Only. Default = 0b. +In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. +When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. +This bit will automatically change to zero after the reset sequence is complete. +This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. +In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. + 8 + 1 + read-write + + + SUSP + SUSP +Suspend - Read/Write or Read Only. Default = 0b. +1=Port in suspend state. 0=Port not in suspend state. +In Host Mode: Read/Write. +Port Enabled Bit and Suspend bit of this register define the port states as follows: +Bits [Port Enabled, Suspend] Port State +0x Disable +10 Enable +11 Suspend +When in suspend state, downstream propagation of data is blocked on this port, except for port reset. +The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. +In the suspend state, the port is sensitive to resume detection. +Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. +The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. +If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: Read Only. +In device mode this bit is a read only status bit. + 7 + 1 + read-write + + + FPR + FPR +Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. +In Host Mode: +Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. +When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. +This bit will automatically change to zero after the resume sequence is complete. +This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. +Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. +The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. +Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. +This field is zero if Port Power(PORTSC1) is zero in host mode. +This bit is not-EHCI compatible. +In Device mode: +After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. +The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. +The bit will be cleared when the device returns to normal operation. + Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. + 6 + 1 + read-write + + + OCC + OCC +Over-current Change-R/WC. Default=0. +This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. + 5 + 1 + read-write + + + OCA + OCA +Over-current Active-Read Only. Default 0. +This bit will automatically transition from one to zero when the over current condition is removed. +0 - This port does not have an over-current condition. +1 - This port currently has an over-current condition + 4 + 1 + read-only + + + PEC + PEC +Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. +In Host Mode: +For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or +due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). +Software clears this by writing a one to it. +This field is zero if Port Power(PORTSC1) is zero. +In Device mode: +The device port is always enabled, so this bit is always '0b'. + 3 + 1 + read-write + + + PE + PE +Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. +In Host Mode: +Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. +Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. +Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. +When the port is disabled, (0b) downstream propagation of data is blocked except for reset. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: +The device port is always enabled, so this bit is always '1b'. + 2 + 1 + read-write + + + CSC + CSC +Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. +In Host Mode: +Indicates a change has occurred in the port's Current Connect Status. +The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. +For example, the insertion status changes twice before system software has cleared the changed condition, +hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: +This bit is undefined in device controller mode. + 1 + 1 + read-write + + + CCS + CCS +Current Connect Status-Read Only. +In Host Mode: +1=Device is present on port. 0=No device is present. Default = 0. +This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: +1=Attached. 0=Not Attached. Default=0. +A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. +A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. +It does not state the device being disconnected or Suspended. + 0 + 1 + read-write + + + + + OTGSC + On-The-Go Status & control Register + 0x1a4 + 32 + 0x00000000 + 0x07070723 + + + ASVIE + ASVIE +A Session Valid Interrupt Enable - Read/Write. + 26 + 1 + read-write + + + AVVIE + AVVIE +A VBus Valid Interrupt Enable - Read/Write. +Setting this bit enables the A VBus valid interrupt. + 25 + 1 + read-write + + + IDIE + IDIE +USB ID Interrupt Enable - Read/Write. +Setting this bit enables the USB ID interrupt. + 24 + 1 + read-write + + + ASVIS + ASVIS +A Session Valid Interrupt Status - Read/Write to Clear. +This bit is set when VBus has either risen above or fallen below the A session valid threshold. +Software must write a one to clear this bit. + 18 + 1 + read-write + + + AVVIS + AVVIS +A VBus Valid Interrupt Status - Read/Write to Clear. +This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. +Software must write a one to clear this bit. + 17 + 1 + read-write + + + IDIS + IDIS +USB ID Interrupt Status - Read/Write. +This bit is set when a change on the ID input has been detected. +Software must write a one to clear this bit. + 16 + 1 + read-write + + + ASV + ASV +A Session Valid - Read Only. +Indicates VBus is above the A session valid threshold. + 10 + 1 + read-only + + + AVV + AVV +A VBus Valid - Read Only. +Indicates VBus is above the A VBus valid threshold. + 9 + 1 + read-only + + + ID + ID +USB ID - Read Only. +0 = A device, 1 = B device + 8 + 1 + read-only + + + IDPU + IDPU +ID Pullup - Read/Write +This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input +will not be sampled. + 5 + 1 + read-write + + + VC + VC +VBUS Charge - Read/Write. +Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. + 1 + 1 + read-write + + + VD + VD +VBUS_Discharge - Read/Write. +Setting this bit causes VBus to discharge through a resistor. + 0 + 1 + read-write + + + + + USBMODE + USB Device Mode Register + 0x1a8 + 32 + 0x00000000 + 0x0000001F + + + SDIS + SDIS +Stream Disable Mode. (0 - Inactive [default]; 1 - Active) +Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. +This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. +Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. +Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems +where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. +NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for +the scheduler when using this feature. +NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. + 4 + 1 + read-write + + + SLOM + SLOM +Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . +0 - Setup Lockouts On (default); +1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. + 3 + 1 + read-write + + + ES + ES +Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the +host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected +by the value of this bit because they are based upon the 32-bit word. +Bit Meaning +0 - Little Endian [Default] +1 - Big Endian + 2 + 1 + read-write + + + CM + CM +Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only +implementations. For those designs that contain both host & device capability, the controller defaults to +an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ +device controllers, this register can only be written once after reset. If it is necessary to switch modes, +software must reset the controller by writing to the RESET bit in the USBCMD register before +reprogramming this register. +For OTG controller core, reset value is '00b'. +00 - Idle [Default for combination host/device] +01 - Reserved +10 - Device Controller [Default for device only controller] +11 - Host Controller [Default for host only controller] + 0 + 2 + read-write + + + + + ENDPTSETUPSTAT + Endpoint Setup Status Register + 0x1ac + 32 + 0x00000000 + 0x0000FFFF + + + ENDPTSETUPSTAT + ENDPTSETUPSTAT +Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. +Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. +The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. +This register is only used in device mode. + 0 + 16 + read-write + + + + + ENDPTPRIME + Endpoint Prime Register + 0x1b0 + 32 + 0x00000000 + 0xFFFFFFFF + + + PETB + PETB +Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a +buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. +Software should write a one to the corresponding bit when posting a new transfer descriptor to an +endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor +from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated +endpoint(s) is (are) successfully primed. +NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD +is retired, and the dQH is updated. +PETB[N] - Endpoint #N, N is in 0..7 + 16 + 16 + read-write + + + PERB + PERB +Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. +Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. +Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. +Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. +NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD +is retired, and the dQH is updated. +PERB[N] - Endpoint #N, N is in 0..7 + 0 + 16 + read-write + + + + + ENDPTFLUSH + Endpoint Flush Register + 0x1b4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FETB + FETB +Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. +If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. +Hardware clears this register after the endpoint flush operation is successful. +FETB[N] - Endpoint #N, N is in 0..7 + 16 + 16 + read-write + + + FERB + FERB +Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. + If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. +Hardware clears this register after the endpoint flush operation is successful. +FERB[N] - Endpoint #N, N is in 0..7 + 0 + 16 + read-write + + + + + ENDPTSTAT + Endpoint Status Register + 0x1b8 + 32 + 0x00000000 + 0xFFFFFFFF + + + ETBR + ETBR +Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. +This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. +There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. +This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. +Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. +NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. +ETBR[N] - Endpoint #N, N is in 0..7 + 16 + 16 + read-only + + + ERBR + ERBR +Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective +endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a +corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the +ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB +traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the +USB DMA system, or through the ENDPTFLUSH register. +NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations +when a dTD is retired, and the dQH is updated. +ERBR[N] - Endpoint #N, N is in 0..7 + 0 + 16 + read-only + + + + + ENDPTCOMPLETE + Endpoint Complete Register + 0x1bc + 32 + 0x00000000 + 0xFFFFFFFF + + + ETCE + ETCE +Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. +If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. +ETCE[N] - Endpoint #N, N is in 0..7 + 16 + 16 + read-write + + + ERCE + ERCE +Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred +and software should read the corresponding endpoint queue to determine the transfer status. If the +corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the +USBINT . Writing one clears the corresponding bit in this register. +ERCE[N] - Endpoint #N, N is in 0..7 + 0 + 16 + read-write + + + + + 8 + 0x4 + ENDPTCTRL0,ENDPTCTRL1,ENDPTCTRL2,ENDPTCTRL3,ENDPTCTRL4,ENDPTCTRL5,ENDPTCTRL6,ENDPTCTRL7 + ENDPTCTRL[%s] + no description available + 0x1c0 + 32 + 0x00000000 + 0x00CD00CD + + + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 + read-write + + + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 + 1 + write-only + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 + read-write + + + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured +as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 + 1 + read-write + + + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 + 1 + read-write + + + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 + 1 + write-only + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 + read-write + + + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 + 1 + read-write + + + + + OTG_CTRL0 + No description available + 0x200 + 32 + 0x00000000 + 0x020B3F90 + + + OTG_WKDPDMCHG_EN + No description available + 25 + 1 + read-write + + + AUTORESUME_EN + No description available + 19 + 1 + read-write + + + OTG_VBUS_WAKEUP_EN + No description available + 17 + 1 + read-write + + + OTG_ID_WAKEUP_EN + No description available + 16 + 1 + read-write + + + OTG_VBUS_SOURCE_SEL + No description available + 13 + 1 + read-write + + + OTG_UTMI_SUSPENDM_SW + default 0 for naneng usbphy + 12 + 1 + read-write + + + OTG_UTMI_RESET_SW + default 1 for naneng usbphy + 11 + 1 + read-write + + + OTG_WAKEUP_INT_ENABLE + No description available + 10 + 1 + read-write + + + OTG_POWER_MASK + No description available + 9 + 1 + read-write + + + OTG_OVER_CUR_POL + No description available + 8 + 1 + read-write + + + OTG_OVER_CUR_DIS + No description available + 7 + 1 + read-write + + + SER_MODE_SUSPEND_EN + for naneng usbphy, only switch to serial mode when suspend + 4 + 1 + read-write + + + + + PHY_CTRL0 + No description available + 0x210 + 32 + 0x00000000 + 0x02007007 + + + GPIO_ID_SEL_N + No description available + 25 + 1 + read-write + + + ID_DIG_OVERRIDE + No description available + 14 + 1 + read-write + + + SESS_VALID_OVERRIDE + No description available + 13 + 1 + read-write + + + VBUS_VALID_OVERRIDE + No description available + 12 + 1 + read-write + + + ID_DIG_OVERRIDE_EN + No description available + 2 + 1 + read-write + + + SESS_VALID_OVERRIDE_EN + No description available + 1 + 1 + read-write + + + VBUS_VALID_OVERRIDE_EN + No description available + 0 + 1 + read-write + + + + + PHY_CTRL1 + No description available + 0x214 + 32 + 0x00000000 + 0x00100002 + + + UTMI_CFG_RST_N + No description available + 20 + 1 + read-write + + + UTMI_OTG_SUSPENDM + OTG suspend, not utmi_suspendm + 1 + 1 + read-write + + + + + TOP_STATUS + No description available + 0x220 + 32 + 0x00000000 + 0x80000000 + + + WAKEUP_INT_STATUS + No description available + 31 + 1 + read-write + + + + + PHY_STATUS + No description available + 0x224 + 32 + 0x00000000 + 0x800000F5 + + + UTMI_CLK_VALID + No description available + 31 + 1 + read-write + + + LINE_STATE + No description available + 6 + 2 + read-write + + + HOST_DISCONNECT + No description available + 5 + 1 + read-write + + + ID_DIG + No description available + 4 + 1 + read-write + + + UTMI_SESS_VALID + No description available + 2 + 1 + read-write + + + VBUS_VALID + No description available + 0 + 1 + read-write + + + + + + + GPTMR0 + GPTMR0 + TMR + 0xf3000000 + + 0x0 + 0x20c + registers + + + + 4 + 0x40 + ch0,ch1,ch2,ch3 + CHANNEL[%s] + no description available + 0x0 + + CR + Control Register + 0x0 + 32 + 0x00000000 + 0x80007FFF + + + CNTUPT + 1- update counter to new value as CNTUPTVAL +This bit will be auto cleared after 1 cycle + 31 + 1 + write-only + + + CNTRST + 1- reset counter + 14 + 1 + read-write + + + SYNCFLW + 1- enable this channel to reset counter to reload(RLD) together with its previous channel. +This bit is not valid for channel 0. + 13 + 1 + read-write + + + SYNCIFEN + 1- SYNCI is valid on its falling edge + 12 + 1 + read-write + + + SYNCIREN + 1- SYNCI is valid on its rising edge + 11 + 1 + read-write + + + CEN + 1- counter enable + 10 + 1 + read-write + + + CMPINIT + Output compare initial poliarity +1- The channel output initial level is high +0- The channel output initial level is low +User should set this bit before set CMPEN to 1. + 9 + 1 + read-write + + + CMPEN + 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. + 8 + 1 + read-write + + + DMASEL + select one of DMA request: +00- CMP0 flag +01- CMP1 flag +10- Input signal toggle captured +11- RLD flag, counter reload; + 6 + 2 + read-write + + + DMAEN + 1- enable dma + 5 + 1 + read-write + + + SWSYNCIEN + 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set + 4 + 1 + read-write + + + DBGPAUSE + 1- counter will pause if chip is in debug mode + 3 + 1 + read-write + + + CAPMODE + This bitfield define the input capture mode +100: width measure mode, timer will calculate the input signal period and duty cycle +011: capture at both rising edge and falling edge +010: capture at falling edge +001: capture at rising edge +000: No capture + 0 + 3 + read-write + + + + + 2 + 0x4 + CMP0,CMP1 + CMP[%s] + no description available + 0x4 + 32 + 0xFFFFFFF0 + 0xFFFFFFFF + + + CMP + compare value 0 + 0 + 32 + read-write + + + + + RLD + Reload register + 0xc + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + RLD + reload value + 0 + 32 + read-write + + + + + CNTUPTVAL + Counter update value register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTUPTVAL + counter will be set to this value when software write cntupt bit in CR + 0 + 32 + read-write + + + + + CAPPOS + Capture rising edge register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPOS + This register contains the counter value captured at input signal rising edge + 0 + 32 + read-only + + + + + CAPNEG + Capture falling edge register + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + This register contains the counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPPRD + PWM period measure register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPRD + This register contains the input signal period when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CAPDTY + PWM duty cycle measure register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + MEAS_HIGH + This register contains the input signal duty cycle when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CNT + Counter + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + 32 bit counter value + 0 + 32 + read-only + + + + + + SR + Status register + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH3CMP1F + channel 3 compare value 1 match flag + 15 + 1 + write-only + + + CH3CMP0F + channel 3 compare value 1 match flag + 14 + 1 + write-only + + + CH3CAPF + channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 13 + 1 + write-only + + + CH3RLDF + channel 3 counter reload flag + 12 + 1 + write-only + + + CH2CMP1F + channel 2 compare value 1 match flag + 11 + 1 + write-only + + + CH2CMP0F + channel 2 compare value 1 match flag + 10 + 1 + write-only + + + CH2CAPF + channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 9 + 1 + write-only + + + CH2RLDF + channel 2 counter reload flag + 8 + 1 + write-only + + + CH1CMP1F + channel 1 compare value 1 match flag + 7 + 1 + write-only + + + CH1CMP0F + channel 1 compare value 1 match flag + 6 + 1 + write-only + + + CH1CAPF + channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 5 + 1 + write-only + + + CH1RLDF + channel 1 counter reload flag + 4 + 1 + write-only + + + CH0CMP1F + channel 1 compare value 1 match flag + 3 + 1 + write-only + + + CH0CMP0F + channel 1 compare value 1 match flag + 2 + 1 + write-only + + + CH0CAPF + channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 1 + 1 + write-only + + + CH0RLDF + channel 1 counter reload flag + 0 + 1 + write-only + + + + + IRQEN + Interrupt request enable register + 0x204 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH3CMP1EN + 1- generate interrupt request when ch3cmp1f flag is set + 15 + 1 + read-write + + + CH3CMP0EN + 1- generate interrupt request when ch3cmp0f flag is set + 14 + 1 + read-write + + + CH3CAPEN + 1- generate interrupt request when ch3capf flag is set + 13 + 1 + read-write + + + CH3RLDEN + 1- generate interrupt request when ch3rldf flag is set + 12 + 1 + read-write + + + CH2CMP1EN + 1- generate interrupt request when ch2cmp1f flag is set + 11 + 1 + read-write + + + CH2CMP0EN + 1- generate interrupt request when ch2cmp0f flag is set + 10 + 1 + read-write + + + CH2CAPEN + 1- generate interrupt request when ch2capf flag is set + 9 + 1 + read-write + + + CH2RLDEN + 1- generate interrupt request when ch2rldf flag is set + 8 + 1 + read-write + + + CH1CMP1EN + 1- generate interrupt request when ch1cmp1f flag is set + 7 + 1 + read-write + + + CH1CMP0EN + 1- generate interrupt request when ch1cmp0f flag is set + 6 + 1 + read-write + + + CH1CAPEN + 1- generate interrupt request when ch1capf flag is set + 5 + 1 + read-write + + + CH1RLDEN + 1- generate interrupt request when ch1rldf flag is set + 4 + 1 + read-write + + + CH0CMP1EN + 1- generate interrupt request when ch0cmp1f flag is set + 3 + 1 + read-write + + + CH0CMP0EN + 1- generate interrupt request when ch0cmp0f flag is set + 2 + 1 + read-write + + + CH0CAPEN + 1- generate interrupt request when ch0capf flag is set + 1 + 1 + read-write + + + CH0RLDEN + 1- generate interrupt request when ch0rldf flag is set + 0 + 1 + read-write + + + + + GCR + Global control register + 0x208 + 32 + 0x00000000 + 0x0000000F + + + SWSYNCT + set this bitfield to trigger software counter sync event + 0 + 4 + read-write + + + + + + + GPTMR1 + GPTMR1 + TMR + 0xf3004000 + + + GPTMR2 + GPTMR2 + TMR + 0xf3008000 + + + GPTMR3 + GPTMR3 + TMR + 0xf300c000 + + + PTMR + PTMR + TMR + 0xf40e0000 + + + I2C0 + I2C0 + I2C + 0xf3020000 + + 0x4 + 0x30 + registers + + + + Cfg + Configuration Register + 0x10 + 32 + 0x00000001 + 0xFFFFFFFF + + + FIFOSIZE + FIFO Size: +0: 2 bytes +1: 4 bytes +2: 8 bytes +3: 16 bytes + 0 + 2 + read-only + + + + + IntEn + Interrupt Enable Register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMPL + Set to enable the Completion Interrupt. +Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. +Slave: interrupts when a transaction addressing the controller is completed. + 9 + 1 + read-write + + + BYTERECV + Set to enable the Byte Receive Interrupt. +Interrupts when a byte of data is received +Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually. + 8 + 1 + read-write + + + BYTETRANS + Set to enable the Byte Transmit Interrupt. +Interrupts when a byte of data is transmitted. + 7 + 1 + read-write + + + START + Set to enable the START Condition Interrupt. +Interrupts when a START condition/repeated START condition is detected. + 6 + 1 + read-write + + + STOP + Set to enable the STOP Condition Interrupt +Interrupts when a STOP condition is detected. + 5 + 1 + read-write + + + ARBLOSE + Set to enable the Arbitration Lose Interrupt. +Master: interrupts when the controller loses the bus arbitration +Slave: not available in this mode. + 4 + 1 + read-write + + + ADDRHIT + Set to enable the Address Hit Interrupt. +Master: interrupts when the addressed slave returned an ACK. +Slave: interrupts when the controller is addressed. + 3 + 1 + read-write + + + FIFOHALF + Set to enable the FIFO Half Interrupt. +Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. +Transmitter: Interrupts when the FIFO is half-empty, i.e. there is <= 1/2 entries in the FIFO. +This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered. + 2 + 1 + read-write + + + FIFOFULL + Set to enable the FIFO Full Interrupt. +Interrupts when the FIFO is full. + 1 + 1 + read-write + + + FIFOEMPTY + Set to enabled the FIFO Empty Interrupt +Interrupts when the FIFO is empty. + 0 + 1 + read-write + + + + + Status + Status Register + 0x18 + 32 + 0x00000001 + 0xFFFFFFFF + + + LINESDA + Indicates the current status of the SDA line on the bus +1: high +0: low + 14 + 1 + read-only + + + LINESCL + Indicates the current status of the SCL line on the bus +1: high +0: low + 13 + 1 + read-only + + + GENCALL + Indicates that the address of the current transaction is a general call address: +1: General call +0: Not general call + 12 + 1 + read-only + + + BUSBUSY + Indicates that the bus is busy +The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus +1: Busy +0: Not busy + 11 + 1 + read-only + + + ACK + Indicates the type of the last received/transmitted acknowledgement bit: +1: ACK +0: NACK + 10 + 1 + read-only + + + CMPL + Transaction Completion +Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration +Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked. + 9 + 1 + write-only + + + BYTERECV + Indicates that a byte of data has been received. + 8 + 1 + write-only + + + BYTETRANS + Indicates that a byte of data has been transmitted. + 7 + 1 + write-only + + + START + Indicates that a START Condition or a repeated START condition has been transmitted/received. + 6 + 1 + write-only + + + STOP + Indicates that a STOP Condition has been transmitted/received. + 5 + 1 + write-only + + + ARBLOSE + Indicates that the controller has lost the bus arbitration. + 4 + 1 + write-only + + + ADDRHIT + Master: indicates that a slave has responded to the transaction. +Slave: indicates that a transaction is targeting the controller (including the General Call). + 3 + 1 + write-only + + + FIFOHALF + Transmitter: Indicates that the FIFO is half-empty. + 2 + 1 + read-only + + + FIFOFULL + Indicates that the FIFO is full. + 1 + 1 + read-only + + + FIFOEMPTY + Indicates that the FIFO is empty. + 0 + 1 + read-only + + + + + Addr + Address Register + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + The slave address. +For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid + 0 + 10 + read-write + + + + + Data + Data Register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + Write this register to put one byte of data to the FIFO. +Read this register to get one byte of data from the FIFO. + 0 + 8 + read-write + + + + + Ctrl + Control Register + 0x24 + 32 + 0x00001E00 + 0x000F9FFF + + + PHASE_START + Enable this bit to send a START condition at the beginning of transaction. +Master mode only. + 12 + 1 + read-write + + + PHASE_ADDR + Enable this bit to send the address after START condition. +Master mode only. + 11 + 1 + read-write + + + PHASE_DATA + Enable this bit to send the data after Address phase. +Master mode only. + 10 + 1 + read-write + + + PHASE_STOP + Enable this bit to send a STOP condition at the end of a transaction. +Master mode only. + 9 + 1 + read-write + + + DIR + Transaction direction +Master: Set this bit to determine the direction for the next transaction. +0: Transmitter +1: Receiver +Slave: The direction of the last received transaction. +0: Receiver +1: Transmitter + 8 + 1 + read-write + + + DATACNT + Data counts in bytes. +Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. +Slave: the meaning of DataCnt depends on the DMA mode: +If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. +If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. + 0 + 8 + read-write + + + + + Cmd + Command Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMD + Write this register with the following values to perform the corresponding actions: +0x0: no action +0x1: issue a data transaction (Master only) +0x2: respond with an ACK to the received byte +0x3: respond with a NACK to the received byte +0x4: clear the FIFO +0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) +When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. +Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled. + 0 + 3 + read-write + + + + + Setup + Setup Register + 0x2c + 32 + 0x05252100 + 0xFFFFFFFF + + + T_SUDAT + T_SUDAT defines the data setup time before releasing the SCL. +Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) +tpclk = PCLK period +TPM = The multiplier value in Timing Parameter Multiplier Register + 24 + 5 + read-write + + + T_SP + T_SP defines the pulse width of spikes that must be suppressed by the input filter. +Pulse width = T_SP * tpclk* (TPM+1) + 21 + 3 + read-write + + + T_HDDAT + T_HDDAT defines the data hold time after SCL goes LOW +Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) + 16 + 5 + read-write + + + T_SCLRADIO + The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. +SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) +1: ratio = 2 +0: ratio = 1 +This field is only valid when the controller is in the master mode. + 13 + 1 + read-write + + + T_SCLHI + The HIGH period of generated SCL clock is defined by T_SCLHi. +SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) +The T_SCLHi value must be greater than T_SP and T_HDDAT values. +This field is only valid when the controller is in the master mode. + 4 + 9 + read-write + + + DMAEN + Enable the direct memory access mode data transfer. +1: Enable +0: Disable + 3 + 1 + read-write + + + MASTER + Configure this device as a master or a slave. +1: Master mode +0: Slave mode + 2 + 1 + read-write + + + ADDRESSING + I2C addressing mode: +1: 10-bit addressing mode +0: 7-bit addressing mode + 1 + 1 + read-write + + + IICEN + Enable the I2C controller. +1: Enable +0: Disable + 0 + 1 + read-write + + + + + TPM + I2C Timing Paramater Multiplier + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + TPM + A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). + 0 + 5 + read-write + + + + + + + I2C1 + I2C1 + I2C + 0xf3024000 + + + I2C2 + I2C2 + I2C + 0xf3028000 + + + I2C3 + I2C3 + I2C + 0xf302c000 + + + LIN0 + LIN0 + LIN + 0xf3030000 + + 0x0 + 0x40 + registers + + + + 8 + 0x4 + data_byte0,data_byte1,data_byte2,data_byte3,data_byte4,data_byte5,data_byte6,data_byte7 + DATABYTE[%s] + no description available + 0x0 + 32 + 0x00000000 + 0x000000FF + + + DATA_BYTE + data byte + 0 + 8 + read-write + + + + + control + control register + 0x20 + 32 + 0x00000000 + 0x000000FF + + + STOP + slave only. Write 1 when the Host determin do not response to the data request according to a unkown ID + 7 + 1 + write-only + + + SLEEP + The bit is used by the LIN core to determine whether the LIN bus is in sleep mode or not. Set this bit after sending or receiving a Sleep Mode frame or if a bus idle timeout interrupt is requested or if after a wakeup request there is no response from the master and a timeout is signaled. The bit will be automatically reset by the LIN core. + 6 + 1 + read-write + + + TRANSMIT + 1: transmit operation 0: receive operation + 5 + 1 + read-write + + + DATA_ACK + slave only. Write 1 after handling a data request interrupt + 4 + 1 + read-write + + + RESET_INT + write 1 to reset the int bit in the status register and the interrupt request output of LIN + 3 + 1 + write-only + + + RESET_ERROR + assert 1 to reset the error bits in status register and error register. A read access to this bit delivers always the value 0 + 2 + 1 + write-only + + + WAKEUP_REQ + wakeup request. Assert to terminate the Sleep mode of the LIN bus. The bit will be reset by core + 1 + 1 + read-write + + + START_REQ + master only. Set by host controller of a LIN master to start the LIN transmission. The core will reset the bit after the transmission is finished or an error is occurred + 0 + 1 + read-write + + + + + state + state register + 0x24 + 32 + 0x00000000 + 0x000000FF + + + LIN_ACTIVE + The bit indicates whether the LIN bus is active or not + 7 + 1 + read-only + + + BUS_IDLE_TV + slave only. This bit is set by LIN core if bit sleep is not set and no bus activity is detected for 4s + 6 + 1 + read-only + + + ABORTED + slave only. This bit is set by LIN core slave if a transmission is aborted after the bneginning of the data field due to a timeout or bit error. + 5 + 1 + read-only + + + DATA_REQ + slave only. Sets after receiving the identifier and requests an interrupt to the host controller. + 4 + 1 + read-only + + + INT + set when request an interrupt. Reset by reset_int + 3 + 1 + read-only + + + ERROR + set when detecte an error, clear by reset_error + 2 + 1 + read-only + + + WAKEUP + set when transmitting a wakeup signal or when received a wakeup signal. Clear when reset_error bit is 1 + 1 + 1 + read-only + + + COMPLETE + set after a transmission has been successful finished and it will reset at the start of a transmission. + 0 + 1 + read-only + + + + + error + error register + 0x28 + 32 + 0x00000000 + 0x0000000F + + + PARITY_ERROR + slave only. identifier parity error + 3 + 1 + read-only + + + TIMEOUT + timeout error. The master detects a timeout error if it is expecting data from the bus but no slave does respond. The slave detects a timeout error if it is requesting a data acknowledge to the host controller. The slave detects a timeout if it has transmitted a wakeup signal and it detects no sync field within 150ms + 2 + 1 + read-only + + + CHK_ERROR + checksum error + 1 + 1 + read-only + + + BIT_ERROR + bit error + 0 + 1 + read-only + + + + + data_len + data lenth register + 0x2c + 32 + 0x00000000 + 0x0000008F + + + ENH_CHECK + 1:enhence check mode + 7 + 1 + read-write + + + DATA_LENGTH + data length + 0 + 4 + read-write + + + + + baudrate_ctl_low + baudrate control low register + 0x30 + 32 + 0x00000000 + 0x000000FF + + + BT_DIV_LOW + bit div register 7:0 + 0 + 8 + read-write + + + + + bardrate_ctl_high + baudrate control high register + 0x34 + 32 + 0x00000000 + 0x000000FF + + + PRESCL + prescl register + 6 + 2 + read-write + + + BT_MUL + bt_mul register + 1 + 5 + read-write + + + BT_DIV_HIGH + bit div register 8 + 0 + 1 + read-write + + + + + id + id register + 0x38 + 32 + 0x00000000 + 0x0000003F + + + ID + id register + 0 + 6 + read-write + + + + + tv + timeout control register + 0x3c + 32 + 0x00000040 + 0x000000CF + + + INITIAL_MODE + initial_mode + 7 + 1 + read-write + + + MASTER_MODE + master_mode + 6 + 1 + read-write + + + BUS_INACTIVITY_TIME + slave only. LIN bus idle timeout register： 00-4s 01-6s 10-8s 11-10s + 2 + 2 + read-write + + + WUP_REPEAT_TIME + slave only. wakeup repeat interval time 00-180ms 01-200ms 10-220ms 11-240ms + 0 + 2 + read-write + + + + + + + LIN1 + LIN1 + LIN + 0xf3034000 + + + LIN2 + LIN2 + LIN + 0xf3038000 + + + LIN3 + LIN3 + LIN + 0xf303c000 + + + SDP + SDP + SDP + 0xf304c000 + + 0x0 + 0x60 + registers + + + + SDPCR + SDP control register + 0x0 + 32 + 0x30000000 + 0xFFFE0101 + + + SFTRST + soft reset. +Write 1 then 0, to reset the SDP block. + 31 + 1 + read-write + + + CLKGAT + Clock Gate for the SDP main logic. +Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block. + 30 + 1 + read-write + + + CIPDIS + Cipher Disable, read the info, whether the CIPHER features is besing disable in this chip or not. +1, Cipher is disabled in this chip. +0, Cipher is enabled in this chip. + 29 + 1 + read-only + + + HASDIS + HASH Disable, read the info, whether the HASH features is besing disable in this chip or not. +1, HASH is disabled in this chip. +0, HASH is enabled in this chip. + 28 + 1 + read-only + + + CIPHEN + Cipher Enablement, controlled by SW. +1, Cipher is Enabled. +0, Cipher is Disabled. + 23 + 1 + read-write + + + HASHEN + HASH Enablement, controlled by SW. +1, HASH is Enabled. +0, HASH is Disabled. + 22 + 1 + read-write + + + MCPEN + Memory Copy Enablement, controlled by SW. +1, Memory copy is Enabled. +0, Memory copy is Disabled. + 21 + 1 + read-write + + + CONFEN + Constant Fill to memory, controlled by SW. +1, Constant fill is Enabled. +0, Constant fill is Disabled. + 20 + 1 + read-write + + + DCRPDI + Decryption Disable bit, Write to 1 to disable the decryption. + 19 + 1 + read-write + + + TSTPKT0IRQ + Test purpose for interrupt when Packet counter reachs "0", but CHAIN=1 in the current packet. + 17 + 1 + read-write + + + RDSCEN + when set to "1", the 1st data packet descriptor loacted in the register(CMDPTR, NPKTPTR, ...) +when set to "0", the 1st data packet descriptor loacted in the memeory(pointed by CMDPTR) + 8 + 1 + read-write + + + INTEN + Interrupt Enablement, controlled by SW. +1, SDP interrupt is enabled. +0, SDP interrupt is disabled. + 0 + 1 + read-write + + + + + MODCTRL + Mod control register. + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + AESALG + AES algorithem selection. +0x0 = AES 128; +0x1 = AES 256; +0x8 = SM4； +Others, reserved. + 28 + 4 + read-write + + + AESMOD + AES mode selection. +0x0 = ECB; +0x1 = CBC; +Others, reserved. + 24 + 4 + read-write + + + AESKS + AES Key Selection. +These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following: +0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key. +0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. +.... +0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key. +0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. +0x20: kman_sk0[127:0] from the key manager for AES128; AES256 will use kman_sk0[255:0] as AES key. +0x21: kman_sk0[255:128] from the key manager for AES128; not valid for AES256. +0x22: kman_sk1[127:0] from the key manager for AES128; AES256 will use kman_sk1[255:0] as AES key. +0x23: kman_sk1[255:128] from the key manager for AES128; not valid for AES256. +0x24: kman_sk2[127:0] from the key manager for AES128; AES256 will use kman_sk2[255:0] as AES key. +0x25: kman_sk2[255:128] from the key manager for AES128; not valid for AES256. +0x26: kman_sk3[127:0] from the key manager for AES128; AES256 will use kman_sk3[255:0] as AES key. +0x27: kman_sk3[255:128] from the key manager for AES128; not valid for AES256. +0x30: exip0_key[127:0] from OTP for AES128; AES256 will use exip0_key[255:0] as AES key. +0x31: exip0_key[255:128] from OTP for AES128; not valid for AES256. +0x32: exip1_key[127:0] from OTP for AES128; AES256 will use exip1_key[255:0] as AES key. +0x33: exip1_key[255:128] from OTP for AES128; not valid for AES256. +Other values, reserved. + 18 + 6 + read-write + + + AESDIR + AES direction +1x1, AES Decryption +1x0, AES Encryption. + 16 + 1 + read-write + + + HASALG + HASH Algorithem selection. +0x0 SHA1 — +0x1 CRC32 — +0x2 SHA256 — + 12 + 4 + read-write + + + CRCEN + CRC enable. +1x1, CRC is enabled. +1x0, CRC is disabled. + 11 + 1 + read-write + + + HASCHK + HASH Check Enable Bit. +1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers; +1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result. +For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words. + 10 + 1 + read-write + + + HASOUT + When hashing is enabled, this bit controls the input or output data of the AES engine is hashed. +0 INPUT HASH +1 OUTPUT HASH + 9 + 1 + read-write + + + DINSWP + Decide whether the SDP byteswaps the input data (big-endian data); +When all bits are set, the data is assumed to be in the big-endian format + 4 + 2 + read-write + + + DOUTSWP + Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format + 2 + 2 + read-write + + + KEYSWP + Decide whether the SDP byteswaps the Key (big-endian data). +When all bits are set, the data is assumed to be in the big-endian format + 0 + 2 + read-write + + + + + PKTCNT + packet counter registers. + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTVAL + This read-only field shows the current (instantaneous) value of the packet counter + 16 + 8 + read-only + + + CNTINCR + The value written to this field is added to the spacket count. + 0 + 8 + read-write + + + + + STA + Status Registers + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + TAG + packet tag. + 24 + 8 + read-only + + + IRQ + interrupt Request, requested when error happen, or when packet processing done, packet counter reach to zero. + 23 + 1 + write-only + + + CHN1PKT0 + the chain buffer "chain" bit is "1", while packet counter is "0", now, waiting for new buffer data. + 20 + 1 + write-only + + + AESBSY + AES Busy + 19 + 1 + read-only + + + HASBSY + Hashing Busy + 18 + 1 + read-only + + + PKTCNT0 + Packet Counter registers reachs to ZERO now. + 17 + 1 + write-only + + + PKTDON + Packet processing done, will trigger this itnerrrupt when the "PKTINT" bit set in the packet control word. + 16 + 1 + write-only + + + ERRSET + Working mode setup error. + 5 + 1 + write-only + + + ERRPKT + Packet head access error, or status update error. + 4 + 1 + write-only + + + ERRSRC + Source Buffer Access Error + 3 + 1 + write-only + + + ERRDST + Destination Buffer Error + 2 + 1 + write-only + + + ERRHAS + Hashing Check Error + 1 + 1 + write-only + + + ERRCHAIN + buffer chain error happen when packet's CHAIN bit=0, but the Packet counter is still not zero. + 0 + 1 + write-only + + + + + KEYADDR + Key Address + 0x10 + 32 + 0x00000040 + 0xFFFFFFFF + + + INDEX + To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. +Key index pointer. The valid indices are 0-[number_keys]. +In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses. + 16 + 8 + read-write + + + SUBWRD + Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field +increments; To write a key, the software must first write the desired key index/subword to this register. + 0 + 2 + read-write + + + + + KEYDAT + Key Data + 0x14 + 32 + 0x00000030 + 0xFFFFFFFF + + + KEYDAT + This register provides the write access to the key/key subword specified by the key index register. +Writing this location updates the selected subword for the key located at the index +specified by the key index register. The write also triggers the SUBWORD field of the +KEY register to increment to the next higher word in the key + 0 + 32 + read-write + + + + + 4 + 0x4 + CIPHIV0,CIPHIV1,CIPHIV2,CIPHIV3 + CIPHIV[%s] + no description available + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + CIPHIV + cipher initialization vector. + 0 + 32 + read-write + + + + + 8 + 0x4 + HASWRD0,HASWRD1,HASWRD2,HASWRD3,HASWRD4,HASWRD5,HASWRD6,HASWRD7 + HASWRD[%s] + no description available + 0x28 + 32 + 0x00000030 + 0xFFFFFFFF + + + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + 0 + 32 + read-write + + + + + CMDPTR + Command Pointer + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMDPTR + current command addresses the register points to the multiword +descriptor that is to be executed (or is currently being executed) + 0 + 32 + read-write + + + + + NPKTPTR + Next Packet Address Pointer + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + NPKTPTR + Next Packet Address Pointer + 0 + 32 + read-write + + + + + PKTCTL + Packet Control Registers + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTTAG + packet tag + 24 + 8 + read-write + + + CIPHIV + Load Initial Vector for the AES in this packet. + 6 + 1 + read-write + + + HASFNL + Hash Termination packet + 5 + 1 + read-write + + + HASINI + Hash Initialization packat + 4 + 1 + read-write + + + CHAIN + whether the next command pointer register must be loaded into the channel's current descriptor +pointer. + 3 + 1 + read-write + + + DCRSEMA + whether the channel's semaphore must be decremented at the end of the current operation. +When the semaphore reaches a value of zero, no more operations are issued from the channel. + 2 + 1 + read-write + + + PKTINT + Reflects whether the channel must issue an interrupt upon the completion of the packet + 1 + 1 + read-write + + + + + PKTSRC + Packet Memory Source Address + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTSRC + Packet Memory Source Address + 0 + 32 + read-write + + + + + PKTDST + Packet Memory Destination Address + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTDST + Packet Memory Destination Address + 0 + 32 + read-write + + + + + PKTBUF + Packet buffer size. + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTBUF + No description available + 0 + 32 + read-write + + + + + + + SYSCTL + SYSCTL + SYSCTL + 0xf4000000 + + 0x0 + 0x3000 + registers + + + + 134 + 0x4 + cpu0,cpx0,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,cpu1,cpx1,rsv10,rsv11,rsv12,rsv13,rsv14,rsv15,rsv16,rsv17,rsv18,rsv19,rsv20,pow_cpu0,pow_cpu1,rst_soc,rst_cpu0,rst_cpu1,rsv26,rsv27,rsv28,rsv29,rsv30,rsv31,clk_src_xtal,clk_src_pll0,clk_src_clk0_pll0,clk_src_clk1_pll0,clk_src_clk2_pll0,clk_src_pll1,clk_src_clk0_pll1,clk_src_clk1_pll1,clk_src_pll2,clk_src_clk0_pll2,clk_src_clk1_pll2,clk_src_pll0_ref,clk_src_pll1_ref,clk_src_pll2_ref,rsv46,rsv47,rsv48,rsv49,rsv50,rsv51,rsv52,rsv53,rsv54,rsv55,rsv56,rsv57,rsv58,rsv59,rsv60,rsv61,rsv62,rsv63,clk_top_cpu0,clk_top_mct0,clk_top_mct1,clk_top_xpi0,clk_top_tmr0,clk_top_tmr1,clk_top_tmr2,clk_top_tmr3,clk_top_urt0,clk_top_urt1,clk_top_urt2,clk_top_urt3,clk_top_urt4,clk_top_urt5,clk_top_urt6,clk_top_urt7,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,clk_top_ptpc,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_ana3,clk_top_ana4,clk_top_ref0,clk_top_ref1,clk_top_lin0,clk_top_lin1,clk_top_lin2,clk_top_lin3,rsv104,rsv105,rsv106,rsv107,rsv108,rsv109,rsv110,rsv111,rsv112,rsv113,rsv114,rsv115,rsv116,rsv117,rsv118,rsv119,rsv120,rsv121,rsv122,rsv123,rsv124,rsv125,rsv126,rsv127,clk_top_adc0,clk_top_adc1,clk_top_adc2,clk_top_dac0,clk_top_dac1,rsv133,rsv134,rsv135,rsv136,rsv137,rsv138,rsv139,rsv140,rsv141,rsv142,rsv143,rsv144,rsv145,rsv146,rsv147,rsv148,rsv149,rsv150,rsv151,rsv152,rsv153,rsv154,rsv155,rsv156,rsv157,rsv158,rsv159,rsv160,rsv161,rsv162,rsv163,rsv164,rsv165,rsv166,rsv167,rsv168,rsv169,rsv170,rsv171,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,ahbp,axis,axic,lmm0,mct0,lmm1,mct1,rom0,ram0,i2c0,i2c1,i2c2,i2c3,tmr0,tmr1,tmr2,tmr3,gpio,adc0,adc1,adc2,dac0,dac1,acmp,spi0,spi1,spi2,spi3,sdm0,urt0,urt1,urt2,urt3,urt4,urt5,urt6,urt7,lin0,lin1,lin2,lin3,ptpc,can0,can1,can2,can3,wdg0,wdg1,mbx0,mbx1,crc0,mot0,mot1,mot2,mot3,msyn,xpi0,hdma,xdma,kman,sdp0,rng0,tsns,usb0,ref0,ref1 + RESOURCE[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + 3 + 0x10 + link0,link1,link2 + GROUP0[%s] + no description available + 0x800 + + VALUE + Group setting + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + SET + Group setting + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: add periphera into this group，periphera is needed + 0 + 32 + read-write + + + + + CLEAR + Group setting + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: delete periphera in this group，periphera is not needed + 0 + 32 + read-write + + + + + TOGGLE + Group setting + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: toggle the result that whether periphera is needed before + 0 + 32 + read-write + + + + + + 3 + 0x10 + link0,link1,link2 + GROUP1[%s] + no description available + 0x840 + + VALUE + Group setting + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + SET + Group setting + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: add periphera into this group，periphera is needed + 0 + 32 + read-write + + + + + CLEAR + Group setting + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: delete periphera in this group，periphera is not needed + 0 + 32 + read-write + + + + + TOGGLE + Group setting + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: toggle the result that whether periphera is needed before + 0 + 32 + read-write + + + + + + 2 + 0x10 + cpu0,cpu1 + AFFILIATE[%s] + no description available + 0x900 + + VALUE + Affiliate of Group + 0x0 + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0, each bit represents a group +bit0: cpu0 depends on group0 +bit1: cpu0 depends on group1 +bit2: cpu0 depends on group2 +bit3: cpu0 depends on group3 + 0 + 4 + read-write + + + + + SET + Affiliate of Group + 0x4 + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0，each bit represents a group +0: no effect +1: the group is assigned to CPU0 + 0 + 4 + read-write + + + + + CLEAR + Affiliate of Group + 0x8 + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0, each bit represents a group +0: no effect +1: the group is not assigned to CPU0 + 0 + 4 + read-write + + + + + TOGGLE + Affiliate of Group + 0xc + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0, each bit represents a group +0: no effect +1: toggle the result that whether the group is assigned to CPU0 before + 0 + 4 + read-write + + + + + + 2 + 0x10 + cpu0,cpu1 + RETENTION[%s] + no description available + 0x920 + + VALUE + Retention Control + 0x0 + 32 + 0x00000000 + 0x000003FF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +bit00: soc_mem is kept on while cpu0 stop +bit01: soc_ctx is kept on while cpu0 stop +bit02: cpu0_mem is kept on while cpu0 stop +bit03: cpu0_ctx is kept on while cpu0 stop +bit04: cpu1_mem is kept on while cpu0 stop +bit05: cpu1_ctx is kept on while cpu0 stop +bit06: xtal_hold is kept on while cpu0 stop +bit07: pll0_hold is kept on while cpu0 stop +bit08: pll1_hold is kept on while cpu0 stop +bit09: pll2_hold is kept on while cpu0 stop + 0 + 10 + read-write + + + + + SET + Retention Control + 0x4 + 32 + 0x00000000 + 0x000003FF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +0: no effect +1: keep + 0 + 10 + read-write + + + + + CLEAR + Retention Control + 0x8 + 32 + 0x00000000 + 0x000003FF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +0: no effect +1: no keep + 0 + 10 + read-write + + + + + TOGGLE + Retention Control + 0xc + 32 + 0x00000000 + 0x000003FF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +0: no effect +1: toggle the result that whether the resource is kept on while CPU0 stop before + 0 + 10 + read-write + + + + + + 2 + 0x10 + cpu0,cpu1 + POWER[%s] + no description available + 0x1000 + + status + Power Setting + 0x0 + 32 + 0x80000000 + 0xC0001100 + + + FLAG + flag represents power cycle happened from last clear of this bit +0: power domain did not edurance power cycle since last clear of this bit +1: power domain enduranced power cycle since last clear of this bit + 31 + 1 + read-write + + + FLAG_WAKE + flag represents wakeup power cycle happened from last clear of this bit +0: power domain did not edurance wakeup power cycle since last clear of this bit +1: power domain enduranced wakeup power cycle since last clear of this bit + 30 + 1 + read-write + + + LF_DISABLE + low fanout power switch disable +0: low fanout power switches are turned on +1: low fanout power switches are truned off + 12 + 1 + read-only + + + LF_ACK + low fanout power switch feedback +0: low fanout power switches are turned on +1: low fanout power switches are truned off + 8 + 1 + read-only + + + + + lf_wait + Power Setting + 0x4 + 32 + 0x00000255 + 0x000FFFFF + + + WAIT + wait time for low fan out power switch turn on, default value is 255 +0: 0 clock cycle +1: 1 clock cycles +. . . +clock cycles count on 24MHz + 0 + 20 + read-write + + + + + off_wait + Power Setting + 0xc + 32 + 0x00000015 + 0x000FFFFF + + + WAIT + wait time for power switch turn off, default value is 15 +0: 0 clock cycle +1: 1 clock cycles +. . . +clock cycles count on 24MHz + 0 + 20 + read-write + + + + + + 3 + 0x10 + soc,cpu0,cpu1 + RESET[%s] + no description available + 0x1400 + + control + Reset Setting + 0x0 + 32 + 0x80000000 + 0xC0000011 + + + FLAG + flag represents reset happened from last clear of this bit +0: domain did not edurance reset cycle since last clear of this bit +1: domain enduranced reset cycle since last clear of this bit + 31 + 1 + read-write + + + FLAG_WAKE + flag represents wakeup reset happened from last clear of this bit +0: domain did not edurance wakeup reset cycle since last clear of this bit +1: domain enduranced wakeup reset cycle since last clear of this bit + 30 + 1 + read-write + + + HOLD + perform reset and hold in reset, until ths bit cleared by software +0: reset is released for function +1: reset is assert and hold + 4 + 1 + read-write + + + RESET + perform reset and release imediately +0: reset is released +1 reset is asserted and will release automatically + 0 + 1 + read-write + + + + + config + Reset Setting + 0x4 + 32 + 0x00643203 + 0x00FFFFFF + + + PRE_WAIT + wait cycle numbers before assert reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 16 + 8 + read-write + + + RSTCLK_NUM + reset clock number(must be even number) +0: 0 cycle +1: 0 cycles +2: 2 cycles +3: 2 cycles +. . . +Note, clock cycle is base on 24M + 8 + 8 + read-write + + + POST_WAIT + time guard band for reset release +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 8 + read-write + + + + + counter + Reset Setting + 0xc + 32 + 0x00000003 + 0x000FFFFF + + + COUNTER + self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 20 + read-write + + + + + + 1 + 0x4 + clk_top_cpu0 + CLOCK_CPU[%s] + no description available + 0x1800 + 32 + 0x00000000 + 0xD0FF07FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + SUB1_DIV + ahb bus divider, the bus clock is generated by cpu_clock/div +0: divider by 1 +1: divider by 2 +… + 20 + 4 + read-write + + + SUB0_DIV + axi bus divider, the bus clock is generated by cpu_clock/div +0: divider by 1 +1: divider by 2 +… + 16 + 4 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + 39 + 0x4 + clk_top_mct0,clk_top_mct1,clk_top_xpi0,clk_top_tmr0,clk_top_tmr1,clk_top_tmr2,clk_top_tmr3,clk_top_urt0,clk_top_urt1,clk_top_urt2,clk_top_urt3,clk_top_urt4,clk_top_urt5,clk_top_urt6,clk_top_urt7,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,clk_top_ptpc,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_ana3,clk_top_ana4,clk_top_ref0,clk_top_ref1,clk_top_lin0,clk_top_lin1,clk_top_lin2,clk_top_lin3 + CLOCK[%s] + no description available + 0x1804 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + 3 + 0x4 + clk_top_adc0,clk_top_adc1,clk_top_adc2 + ADCCLK[%s] + no description available + 0x1c00 + 32 + 0x00000000 + 0xD0000100 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux +0: ana clock +1: ahb clock + 8 + 1 + read-write + + + + + 2 + 0x4 + clk_top_dac0,clk_top_dac1 + DACCLK[%s] + no description available + 0x1c0c + 32 + 0x00000000 + 0xD0000100 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux +0: ana clock +1: ahb clock + 8 + 1 + read-write + + + + + global00 + Clock senario + 0x2000 + 32 + 0x00000000 + 0x0000000F + + + MUX + global clock override request +bit0: override to preset0 +bit1: override to preset1 +bit2: override to preset2 +bit3: override to preset3 + 0 + 4 + read-write + + + + + 4 + 0x20 + slice0,slice1,slice2,slice3 + MONITOR[%s] + no description available + 0x2400 + + control + Clock measure and monitor control + 0x0 + 32 + 0x00000000 + 0x89FFD7FF + + + VALID + result is ready for read +0: not ready +1: result is ready + 31 + 1 + read-write + + + DIV_BUSY + divider is applying new setting + 27 + 1 + read-only + + + OUTEN + enable clock output + 24 + 1 + read-write + + + DIV + output divider + 16 + 8 + read-write + + + HIGH + clock frequency higher than upper limit + 15 + 1 + read-write + + + LOW + clock frequency lower than lower limit + 14 + 1 + read-write + + + START + start measurement + 12 + 1 + read-write + + + MODE + work mode, +0: register value will be compared to measurement +1: upper and lower value will be recordered in register + 10 + 1 + read-write + + + ACCURACY + measurement accuracy, +0: resolution is 1kHz +1: resolution is 1Hz + 9 + 1 + read-write + + + REFERENCE + reference clock selection, +0: 32k +1: 24M + 8 + 1 + read-write + + + SELECTION + clock measurement selection + 0: clk_32k + 1: clk_irc24m + 2: clk_xtal_24m + 3: clk_usb0_phy + 8: clk0_osc0 + 9: clk0_pll0 + 10: clk1_pll0 + 11: clk2_pll0 + 12: clk0_pll1 + 13: clk1_pll1 + 14: clk0_pll2 + 15: clk1_pll2 +128: clk_top_cpu0 +129: clk_top_mct0 +130: clk_top_mct1 +131: clk_top_xpi0 +132: clk_top_tmr0 +133: clk_top_tmr1 +134: clk_top_tmr2 +135: clk_top_tmr3 +136: clk_top_urt0 +137: clk_top_urt1 +138: clk_top_urt2 +139: clk_top_urt3 +140: clk_top_urt4 +141: clk_top_urt5 +142: clk_top_urt6 +143: clk_top_urt7 +144: clk_top_i2c0 +145: clk_top_i2c1 +146: clk_top_i2c2 +147: clk_top_i2c3 +148: clk_top_spi0 +149: clk_top_spi1 +150: clk_top_spi2 +151: clk_top_spi3 +152: clk_top_can0 +153: clk_top_can1 +154: clk_top_can2 +155: clk_top_can3 +156: clk_top_ptpc +157: clk_top_ana0 +158: clk_top_ana1 +159: clk_top_ana2 +160: clk_top_ana3 +161: clk_top_ana4 +162: clk_top_ref0 +163: clk_top_ref1 +164: clk_top_lin0 +165: clk_top_lin1 +166: clk_top_lin2 +167: clk_top_lin3 + 0 + 8 + read-write + + + + + current + Clock measure result + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + self updating measure result + 0 + 32 + read-only + + + + + low_limit + Clock lower limit + 0x8 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + FREQUENCY + lower frequency + 0 + 32 + read-write + + + + + high_limit + Clock upper limit + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + upper frequency + 0 + 32 + read-write + + + + + + 2 + 0x400 + cpu0,cpu1 + CPU[%s] + no description available + 0x2800 + + LP + CPU0 LP control + 0x0 + 32 + 0x00001000 + 0xFF013703 + + + WAKE_CNT + CPU0 wake up counter, counter satuated at 255, write 0x00 to clear + 24 + 8 + read-write + + + HALT + halt request for CPU0, +0: CPU0 will start to execute after reset or receive wakeup request +1: CPU0 will not start after reset, or wakeup after WFI + 16 + 1 + read-write + + + WAKE + CPU0 is waking up +0: CPU0 wake up not asserted +1: CPU0 wake up asserted + 13 + 1 + read-only + + + EXEC + CPU0 is executing +0: CPU0 is not executing +1: CPU0 is executing + 12 + 1 + read-only + + + WAKE_FLAG + CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit +0: CPU0 wakeup not happened +1: CPU0 wake up happened + 10 + 1 + read-write + + + SLEEP_FLAG + CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit +0: CPU0 sleep not happened +1: CPU0 sleep happened + 9 + 1 + read-write + + + RESET_FLAG + CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit +0: CPU0 reset not happened +1: CPU0 reset happened + 8 + 1 + read-write + + + MODE + Low power mode, system behavior after WFI +00: CPU clock stop after WFI +01: System enter low power mode after WFI +10: Keep running after WFI +11: reserved + 0 + 2 + read-write + + + + + LOCK + CPU0 Lock GPR + 0x4 + 32 + 0x00000002 + 0x0000FFFE + + + GPR + Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset + 2 + 14 + read-write + + + LOCK + Lock bit for CPU_LOCK + 1 + 1 + read-write + + + + + 14 + 0x4 + GPR0,GPR1,GPR2,GPR3,GPR4,GPR5,GPR6,GPR7,GPR8,GPR9,GPR10,GPR11,GPR12,GPR13 + GPR[%s] + no description available + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + 4 + 0x4 + STATUS0,STATUS1,STATUS2,STATUS3 + WAKEUP_STATUS[%s] + no description available + 0x40 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + 4 + 0x4 + ENABLE0,ENABLE1,ENABLE2,ENABLE3 + WAKEUP_ENABLE[%s] + no description available + 0x80 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + + + + IOC + IOC + IOC + 0xf4040000 + + 0x0 + 0xf40 + registers + + + + 488 + 0x8 + pa00,pa01,pa02,pa03,pa04,pa05,pa06,pa07,pa08,pa09,pa10,pa11,pa12,pa13,pa14,pa15,pa16,pa17,pa18,pa19,pa20,pa21,pa22,pa23,pa24,pa25,pa26,pa27,pa28,pa29,pa30,pa31,pb00,pb01,pb02,pb03,pb04,pb05,pb06,pb07,pb08,pb09,pb10,pb11,pb12,pb13,pb14,pb15,pb16,pb17,pb18,pb19,pb20,pb21,pb22,pb23,pb24,pb25,pb26,pb27,pb28,pb29,pb30,pb31,pc00,pc01,pc02,pc03,pc04,pc05,pc06,pc07,pc08,pc09,pc10,pc11,pc12,pc13,pc14,pc15,pc16,pc17,pc18,pc19,pc20,pc21,pc22,pc23,pc24,pc25,pc26,pc27,rsv92,rsv93,rsv94,rsv95,rsv96,rsv97,rsv98,rsv99,rsv100,rsv101,rsv102,rsv103,rsv104,rsv105,rsv106,rsv107,rsv108,rsv109,rsv110,rsv111,rsv112,rsv113,rsv114,rsv115,rsv116,rsv117,rsv118,rsv119,rsv120,rsv121,rsv122,rsv123,rsv124,rsv125,rsv126,rsv127,rsv128,rsv129,rsv130,rsv131,rsv132,rsv133,rsv134,rsv135,rsv136,rsv137,rsv138,rsv139,rsv140,rsv141,rsv142,rsv143,rsv144,rsv145,rsv146,rsv147,rsv148,rsv149,rsv150,rsv151,rsv152,rsv153,rsv154,rsv155,rsv156,rsv157,rsv158,rsv159,rsv160,rsv161,rsv162,rsv163,rsv164,rsv165,rsv166,rsv167,rsv168,rsv169,rsv170,rsv171,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,rsv256,rsv257,rsv258,rsv259,rsv260,rsv261,rsv262,rsv263,rsv264,rsv265,rsv266,rsv267,rsv268,rsv269,rsv270,rsv271,rsv272,rsv273,rsv274,rsv275,rsv276,rsv277,rsv278,rsv279,rsv280,rsv281,rsv282,rsv283,rsv284,rsv285,rsv286,rsv287,rsv288,rsv289,rsv290,rsv291,rsv292,rsv293,rsv294,rsv295,rsv296,rsv297,rsv298,rsv299,rsv300,rsv301,rsv302,rsv303,rsv304,rsv305,rsv306,rsv307,rsv308,rsv309,rsv310,rsv311,rsv312,rsv313,rsv314,rsv315,rsv316,rsv317,rsv318,rsv319,rsv320,rsv321,rsv322,rsv323,rsv324,rsv325,rsv326,rsv327,rsv328,rsv329,rsv330,rsv331,rsv332,rsv333,rsv334,rsv335,rsv336,rsv337,rsv338,rsv339,rsv340,rsv341,rsv342,rsv343,rsv344,rsv345,rsv346,rsv347,rsv348,rsv349,rsv350,rsv351,rsv352,rsv353,rsv354,rsv355,rsv356,rsv357,rsv358,rsv359,rsv360,rsv361,rsv362,rsv363,rsv364,rsv365,rsv366,rsv367,rsv368,rsv369,rsv370,rsv371,rsv372,rsv373,rsv374,rsv375,rsv376,rsv377,rsv378,rsv379,rsv380,rsv381,rsv382,rsv383,rsv384,rsv385,rsv386,rsv387,rsv388,rsv389,rsv390,rsv391,rsv392,rsv393,rsv394,rsv395,rsv396,rsv397,rsv398,rsv399,rsv400,rsv401,rsv402,rsv403,rsv404,rsv405,rsv406,rsv407,rsv408,rsv409,rsv410,rsv411,rsv412,rsv413,rsv414,rsv415,px00,px01,px02,px03,px04,px05,px06,px07,rsv424,rsv425,rsv426,rsv427,rsv428,rsv429,rsv430,rsv431,rsv432,rsv433,rsv434,rsv435,rsv436,rsv437,rsv438,rsv439,rsv440,rsv441,rsv442,rsv443,rsv444,rsv445,rsv446,rsv447,py00,py01,py02,py03,py04,py05,py06,py07,rsv456,rsv457,rsv458,rsv459,rsv460,rsv461,rsv462,rsv463,rsv464,rsv465,rsv466,rsv467,rsv468,rsv469,rsv470,rsv471,rsv472,rsv473,rsv474,rsv475,rsv476,rsv477,rsv478,rsv479,pz00,pz01,pz02,pz03,pz04,pz05,pz06,pz07 + PAD[%s] + no description available + 0x0 + + FUNC_CTL + ALT SELECT + 0x0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_CTL + PAD SETTINGS + 0x4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + + + + PIOC + PIOC + IOC + 0xf40d8000 + + + BIOC + BIOC + IOC + 0xf5010000 + + + OTPSHW + OTPSHW + OTP + 0xf4080000 + + 0x0 + 0xc08 + registers + + + + 128 + 0x4 + SHADOW000,SHADOW001,SHADOW002,SHADOW003,SHADOW004,SHADOW005,SHADOW006,SHADOW007,SHADOW008,SHADOW009,SHADOW010,SHADOW011,SHADOW012,SHADOW013,SHADOW014,SHADOW015,SHADOW016,SHADOW017,SHADOW018,SHADOW019,SHADOW020,SHADOW021,SHADOW022,SHADOW023,SHADOW024,SHADOW025,SHADOW026,SHADOW027,SHADOW028,SHADOW029,SHADOW030,SHADOW031,SHADOW032,SHADOW033,SHADOW034,SHADOW035,SHADOW036,SHADOW037,SHADOW038,SHADOW039,SHADOW040,SHADOW041,SHADOW042,SHADOW043,SHADOW044,SHADOW045,SHADOW046,SHADOW047,SHADOW048,SHADOW049,SHADOW050,SHADOW051,SHADOW052,SHADOW053,SHADOW054,SHADOW055,SHADOW056,SHADOW057,SHADOW058,SHADOW059,SHADOW060,SHADOW061,SHADOW062,SHADOW063,SHADOW064,SHADOW065,SHADOW066,SHADOW067,SHADOW068,SHADOW069,SHADOW070,SHADOW071,SHADOW072,SHADOW073,SHADOW074,SHADOW075,SHADOW076,SHADOW077,SHADOW078,SHADOW079,SHADOW080,SHADOW081,SHADOW082,SHADOW083,SHADOW084,SHADOW085,SHADOW086,SHADOW087,SHADOW088,SHADOW089,SHADOW090,SHADOW091,SHADOW092,SHADOW093,SHADOW094,SHADOW095,SHADOW096,SHADOW097,SHADOW098,SHADOW099,SHADOW100,SHADOW101,SHADOW102,SHADOW103,SHADOW104,SHADOW105,SHADOW106,SHADOW107,SHADOW108,SHADOW109,SHADOW110,SHADOW111,SHADOW112,SHADOW113,SHADOW114,SHADOW115,SHADOW116,SHADOW117,SHADOW118,SHADOW119,SHADOW120,SHADOW121,SHADOW122,SHADOW123,SHADOW124,SHADOW125,SHADOW126,SHADOW127 + SHADOW[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + 8 + 0x4 + LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 + SHADOW_LOCK[%s] + no description available + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + 128 + 0x4 + FUSE000,FUSE001,FUSE002,FUSE003,FUSE004,FUSE005,FUSE006,FUSE007,FUSE008,FUSE009,FUSE010,FUSE011,FUSE012,FUSE013,FUSE014,FUSE015,FUSE016,FUSE017,FUSE018,FUSE019,FUSE020,FUSE021,FUSE022,FUSE023,FUSE024,FUSE025,FUSE026,FUSE027,FUSE028,FUSE029,FUSE030,FUSE031,FUSE032,FUSE033,FUSE034,FUSE035,FUSE036,FUSE037,FUSE038,FUSE039,FUSE040,FUSE041,FUSE042,FUSE043,FUSE044,FUSE045,FUSE046,FUSE047,FUSE048,FUSE049,FUSE050,FUSE051,FUSE052,FUSE053,FUSE054,FUSE055,FUSE056,FUSE057,FUSE058,FUSE059,FUSE060,FUSE061,FUSE062,FUSE063,FUSE064,FUSE065,FUSE066,FUSE067,FUSE068,FUSE069,FUSE070,FUSE071,FUSE072,FUSE073,FUSE074,FUSE075,FUSE076,FUSE077,FUSE078,FUSE079,FUSE080,FUSE081,FUSE082,FUSE083,FUSE084,FUSE085,FUSE086,FUSE087,FUSE088,FUSE089,FUSE090,FUSE091,FUSE092,FUSE093,FUSE094,FUSE095,FUSE096,FUSE097,FUSE098,FUSE099,FUSE100,FUSE101,FUSE102,FUSE103,FUSE104,FUSE105,FUSE106,FUSE107,FUSE108,FUSE109,FUSE110,FUSE111,FUSE112,FUSE113,FUSE114,FUSE115,FUSE116,FUSE117,FUSE118,FUSE119,FUSE120,FUSE121,FUSE122,FUSE123,FUSE124,FUSE125,FUSE126,FUSE127 + FUSE[%s] + no description available + 0x400 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + 8 + 0x4 + LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 + FUSE_LOCK[%s] + no description available + 0x600 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + UNLOCK + UNLOCK + 0x800 + 32 + 0x00000000 + 0xFFFFFFFF + + + UNLOCK + unlock word for fuse array operation +write "OPEN" to unlock fuse array, write any other value will lock write to fuse. +Please make sure 24M crystal is running and 2.5V LDO working properly + 0 + 32 + read-write + + + + + DATA + DATA + 0x804 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + data register for non-blocking access +this register hold dat read from fuse array or data to by programmed to fuse array + 0 + 32 + read-write + + + + + ADDR + ADDR + 0x808 + 32 + 0x00000000 + 0x0000007F + + + ADDR + word address to be read or write + 0 + 7 + read-write + + + + + CMD + CMD + 0x80c + 32 + 0x00000000 + 0xFFFFFFFF + + + CMD + command to access fure array +"BLOW" will update fuse word at ADDR to value hold in DATA +"READ" will fetch fuse value in at ADDR to DATA register + 0 + 32 + read-write + + + + + LOAD_REQ + LOAD Request + 0xa00 + 32 + 0x00000007 + 0x0000000F + + + REQUEST + reload request for 4 regions +bit0: region0 +bit1: region1 +bit2: region2 +bit3: region3 + 0 + 4 + read-write + + + + + LOAD_COMP + LOAD complete + 0xa04 + 32 + 0x00000007 + 0x0000000F + + + COMPLETE + reload complete sign for 4 regions +bit0: region 0 +bit1: region1 +bit2: region2 +bit3: region3 + 0 + 4 + read-write + + + + + 4 + 0x4 + LOAD_REGION0,LOAD_REGION1,LOAD_REGION2,LOAD_REGION3 + REGION[%s] + no description available + 0xa20 + 32 + 0x00000800 + 0x00007F7F + + + STOP + stop address of load region, fuse word at end address will NOT be reloaded +region0: fixed at 8 +region1: fixed at 16 +region2: fixed at 0, +region3: usrer configurable + 8 + 7 + read-write + + + START + start address of load region, fuse word at start address will be reloaded +region0: fixed at 0 +region1: fixed at 8 +region2: fixed at 16, +region3: usrer configurable + 0 + 7 + read-write + + + + + INT_FLAG + interrupt flag + 0xc00 + 32 + 0x00000000 + 0x00000007 + + + WRITE + fuse write flag, write 1 to clear +0: fuse is not written or writing +1: value in DATA register is programmed into fuse + 2 + 1 + read-write + + + READ + fuse read flag, write 1 to clear +0: fuse is not read or reading +1: fuse value is put in DATA register + 1 + 1 + read-write + + + LOAD + fuse load flag, write 1 to clear +0: fuse is not loaded or loading +1: fuse loaded + 0 + 1 + read-write + + + + + INT_EN + interrupt enable + 0xc04 + 32 + 0x00000000 + 0x00000007 + + + WRITE + fuse write interrupt enable +0: fuse write interrupt is not enable +1: fuse write interrupt is enable + 2 + 1 + read-write + + + READ + fuse read interrupt enable +0: fuse read interrupt is not enable +1: fuse read interrupt is enable + 1 + 1 + read-write + + + LOAD + fuse load interrupt enable +0: fuse load interrupt is not enable +1: fuse load interrupt is enable + 0 + 1 + read-write + + + + + + + OTP + OTP + OTP + 0xf40c8000 + + + PPOR + PPOR + PPOR + 0xf40c0000 + + 0x0 + 0x20 + registers + + + + RESET_FLAG + flag indicate reset source + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FLAG + reset reason of last hard reset, write 1 to clear each bit +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + write-only + + + + + RESET_STATUS + reset source status + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + current status of reset sources +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + read-write + + + + + RESET_HOLD + reset hold attribute + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + read-write + + + + + RESET_ENABLE + reset source enable + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + enable of reset sources +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + read-write + + + + + RESET_HOT + reset type triggered by reset + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + TYPE + reset type of reset sources, 0 for cold/warm reset, all system control setting cleared including clock, ioc; 1 for hot reset, system control, ioc setting kept, peripheral setting cleared. +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + read-write + + + + + RESET_COLD + reset type attribute + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + FLAG + perform cold or warm reset of chip, 0 for warm reset, fuse value and debug connection preserved; 1 for cold reset, fuse value reloaded and debug connection corrupted. This bit is ignored when hot reset selected +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + read-write + + + + + SOFTWARE_RESET + Software reset counter + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset + 0 + 32 + read-write + + + + + + + PCFG + PCFG + PMU + 0xf40c4000 + + 0x0 + 0x70 + registers + + + + BANDGAP + BANGGAP control + 0x0 + 32 + 0x00101010 + 0x831F1F1F + + + VBG_TRIMMED + Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: bandgap is not trimmed +1: bandgap is trimmed + 31 + 1 + read-write + + + LOWPOWER_MODE + Banggap work in low power mode, banggap function limited +0: banggap works in normal mode +1: banggap works in low power mode + 25 + 1 + read-write + + + POWER_SAVE + Banggap work in power save mode, banggap function normally +0: banggap works in high performance mode +1: banggap works in power saving mode + 24 + 1 + read-write + + + VBG_1P0_TRIM + Banggap 1.0V output trim value + 16 + 5 + read-write + + + VBG_P65_TRIM + Banggap 1.0V output trim value + 8 + 5 + read-write + + + VBG_P50_TRIM + Banggap 1.0V output trim value + 0 + 5 + read-write + + + + + LDO1P1 + 1V LDO config + 0x4 + 32 + 0x0000044C + 0x00000FFF + + + VOLT + LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. +700: 700mV +720: 720mV +. . . +1320:1320mV + 0 + 12 + read-write + + + + + LDO2P5 + 2.5V LDO config + 0x8 + 32 + 0x000009C4 + 0x10010FFF + + + READY + Ready flag, will set 1ms after enabled or voltage change +0: LDO is not ready for use +1: LDO is ready + 28 + 1 + read-only + + + ENABLE + LDO enable +0: turn off LDO +1: turn on LDO + 16 + 1 + read-write + + + VOLT + LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. +2125: 2125mV +2150: 2150mV +. . . +2900:2900mV + 0 + 12 + read-write + + + + + DCDC_MODE + DCDC mode select + 0x10 + 32 + 0x0001047E + 0x10070FFF + + + READY + Ready flag +0: DCDC is applying new change +1: DCDC is ready + 28 + 1 + read-only + + + MODE + DCDC work mode +XX0: turn off +001: basic mode +011: generic mode +101: automatic mode +111: expert mode + 16 + 3 + read-write + + + VOLT + DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. +600: 600mV +625: 625mV +. . . +1375:1375mV + 0 + 12 + read-write + + + + + DCDC_LPMODE + DCDC low power mode + 0x14 + 32 + 0x00000384 + 0x00000FFF + + + STBY_VOLT + DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. +600: 600mV +625: 625mV +. . . +1375:1375mV + 0 + 12 + read-write + + + + + DCDC_PROT + DCDC protection + 0x18 + 32 + 0x00000010 + 0x11818191 + + + ILIMIT_LP + over current setting for low power mode +0:250mA +1:200mA + 28 + 1 + read-write + + + OVERLOAD_LP + over current in low power mode +0: current is below setting +1: overcurrent happened in low power mode + 24 + 1 + read-only + + + DISABLE_POWER_LOSS + disable power loss protection +0: power loss protection enabled, DCDC shuts down when power loss +1: power loss protection disabled, DCDC try working after power voltage drop + 23 + 1 + read-write + + + POWER_LOSS_FLAG + power loss +0: input power is good +1: input power is too low + 16 + 1 + read-only + + + DISABLE_OVERVOLTAGE + output over voltage protection +0: protection enabled, DCDC will shut down is output voltage is unexpected high +1: protection disabled, DCDC continue to adjust output voltage + 15 + 1 + read-write + + + OVERVOLT_FLAG + output over voltage flag +0: output is normal +1: output is unexpected high + 8 + 1 + read-only + + + DISABLE_SHORT + disable output short circuit protection +0: short circuits protection enabled, DCDC shut down if short circuit on output detected +1: short circuit protection disabled + 7 + 1 + read-write + + + SHORT_CURRENT + short circuit current setting +0: 2.0A, +1: 1.3A + 4 + 1 + read-write + + + SHORT_FLAG + short circuit flag +0: current is within limit +1: short circuits detected + 0 + 1 + read-only + + + + + DCDC_CURRENT + DCDC current estimation + 0x1c + 32 + 0x00000000 + 0x0000811F + + + ESTI_EN + enable current measure + 15 + 1 + read-write + + + VALID + Current level valid +0: data is invalid +1: data is valid + 8 + 1 + read-only + + + LEVEL + DCDC current level, current level is num * 50mA + 0 + 5 + read-only + + + + + DCDC_ADVMODE + DCDC advance setting + 0x20 + 32 + 0x03120040 + 0x073F006F + + + EN_RCSCALE + Enable RC scale + 24 + 3 + read-write + + + DC_C + Loop C number + 20 + 2 + read-write + + + DC_R + Loop R number + 16 + 4 + read-write + + + EN_FF_DET + enable feed forward detect +0: feed forward detect is disabled +1: feed forward detect is enabled + 6 + 1 + read-write + + + EN_FF_LOOP + enable feed forward loop +0: feed forward loop is disabled +1: feed forward loop is enabled + 5 + 1 + read-write + + + EN_DCM_EXIT + avoid over voltage +0: stay in DCM mode when voltage excess +1: change to CCM mode when voltage excess + 3 + 1 + read-write + + + EN_SKIP + enable skip on narrow pulse +0: do not skip narrow pulse +1: skip narrow pulse + 2 + 1 + read-write + + + EN_IDLE + enable skip when voltage is higher than threshold +0: do not skip +1: skip if voltage is excess + 1 + 1 + read-write + + + EN_DCM + DCM mode +0: CCM mode +1: DCM mode + 0 + 1 + read-write + + + + + DCDC_ADVPARAM + DCDC advance parameter + 0x24 + 32 + 0x00006E1C + 0x00007F7F + + + MIN_DUT + minimum duty cycle + 8 + 7 + read-write + + + MAX_DUT + maximum duty cycle + 0 + 7 + read-write + + + + + DCDC_MISC + DCDC misc parameter + 0x28 + 32 + 0x00070100 + 0x13170317 + + + EN_HYST + hysteres enable + 28 + 1 + read-write + + + HYST_SIGN + hysteres sign + 25 + 1 + read-write + + + HYST_THRS + hysteres threshold + 24 + 1 + read-write + + + RC_SCALE + Loop RC scale threshold + 20 + 1 + read-write + + + DC_FF + Loop feed forward number + 16 + 3 + read-write + + + OL_THRE + overload for threshold for lod power mode + 8 + 2 + read-write + + + OL_HYST + current hysteres range +0: 12.5mV +1: 25mV + 4 + 1 + read-write + + + DELAY + enable delay +0: delay disabled, +1: delay enabled + 2 + 1 + read-write + + + CLK_SEL + clock selection +0: select DCDC internal oscillator +1: select RC24M oscillator + 1 + 1 + read-write + + + EN_STEP + enable stepping in voltage change +0: stepping disabled, +1: steping enabled + 0 + 1 + read-write + + + + + DCDC_DEBUG + DCDC Debug + 0x2c + 32 + 0x00005DBF + 0x000FFFFF + + + UPDATE_TIME + DCDC voltage change time in 24M clock cycles, default value is 1mS + 0 + 20 + read-write + + + + + DCDC_START_TIME + DCDC ramp time + 0x30 + 32 + 0x0001193F + 0x000FFFFF + + + START_TIME + Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS + 0 + 20 + read-write + + + + + DCDC_RESUME_TIME + DCDC resume time + 0x34 + 32 + 0x00008C9F + 0x000FFFFF + + + RESUME_TIME + Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS + 0 + 20 + read-write + + + + + POWER_TRAP + SOC power trap + 0x40 + 32 + 0x00000000 + 0x80010001 + + + TRIGGERED + Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. +0: low power trap is not triggered +1: low power trap triggered + 31 + 1 + read-write + + + RETENTION + DCDC enter standby mode, which will reduce voltage for memory content retention +0: Shutdown DCDC +1: reduce DCDC voltage + 16 + 1 + read-write + + + TRAP + Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered +0: trap not enabled, pmic side low power function disabled +1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. + 0 + 1 + read-write + + + + + WAKE_CAUSE + Wake up source + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAUSE + wake up cause, each bit represents one wake up source, write 1 to clear the register bit +0: wake up source is not active during last wakeup +1: wake up source is active furing last wakeup +bit 0: pmic_enable +bit 1: debug wakeup +bit 4: fuse interrupt +bit 7: UART interrupt +bit 8: TMR interrupt +bit 9: WDG interrupt +bit10: GPIO in PMIC interrupt +bit11: Security monitor interrupt +bit12: Security in PMIC event +bit16: Security violation in BATT +bit17: GPIO in BATT interrupt +bit18: BATT Button interrupt +bit19: RTC alarm interrupt + 0 + 32 + read-write + + + + + WAKE_MASK + Wake up mask + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + MASK + mask for wake up sources, each bit represents one wakeup source +0: allow source to wake up system +1: disallow source to wakeup system +bit 0: pmic_enable +bit 1: debug wakeup +bit 4: fuse interrupt +bit 7: UART interrupt +bit 8: TMR interrupt +bit 9: WDG interrupt +bit10: GPIO in PMIC interrupt +bit11: Security monitor interrupt +bit12: Security in PMIC event +bit16: Security violation in BATT +bit17: GPIO in BATT interrupt +bit18: BATT Button interrupt +bit19: RTC alarm interrupt + 0 + 32 + read-write + + + + + SCG_CTRL + Clock gate control in PMIC + 0x4c + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + SCG + control whether clock being gated during PMIC low power flow, 2 bits for each peripheral +00,01: reserved +10: clock is always off +11: clock is always on +bit0-1: fuse +bit6-7:gpio +bit8-9:ioc +bit10-11: timer +bit12-13:wdog +bit14-15:uart +bit16-17:debug + 0 + 32 + read-write + + + + + DEBUG_STOP + Debug stop config + 0x50 + 32 + 0x00000001 + 0x00000003 + + + CPU1 + Stop peripheral when CPU1 enter debug mode +0: peripheral keep running when CPU1 in debug mode +1: peripheral enter debug mode when CPU1 enter debug + 1 + 1 + read-write + + + CPU0 + Stop peripheral when CPU0 enter debug mode +0: peripheral keep running when CPU0 in debug mode +1: peripheral enter debug mode when CPU0 enter debug + 0 + 1 + read-write + + + + + RC24M + RC 24M config + 0x60 + 32 + 0x00000310 + 0x8000071F + + + RC_TRIMMED + RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: RC is not trimmed +1: RC is trimmed + 31 + 1 + read-write + + + TRIM_C + Coarse trim for RC24M, bigger value means faster + 8 + 3 + read-write + + + TRIM_F + Fine trim for RC24M, bigger value means faster + 0 + 5 + read-write + + + + + RC24M_TRACK + RC 24M track mode + 0x64 + 32 + 0x00000000 + 0x00010011 + + + SEL24M + Select track reference +0: select 32K as reference +1: select 24M XTAL as reference + 16 + 1 + read-write + + + RETURN + Retrun default value when XTAL loss +0: remain last tracking value +1: switch to default value + 4 + 1 + read-write + + + TRACK + track mode +0: RC24M free running +1: track RC24M to external XTAL + 0 + 1 + read-write + + + + + TRACK_TARGET + RC 24M track target + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRE_DIV + Divider for reference source + 16 + 16 + read-write + + + TARGET + Target frequency multiplier of divided source + 0 + 16 + read-write + + + + + STATUS + RC 24M track status + 0x6c + 32 + 0x00000000 + 0x0011871F + + + SEL32K + track is using XTAL32K +0: track is not using XTAL32K +1: track is using XTAL32K + 20 + 1 + read-only + + + SEL24M + track is using XTAL24M +0: track is not using XTAL24M +1: track is using XTAL24M + 16 + 1 + read-only + + + EN_TRIM + default value takes effect +0: default value is invalid +1: default value is valid + 15 + 1 + read-only + + + TRIM_C + default coarse trim value + 8 + 3 + read-only + + + TRIM_F + default fine trim value + 0 + 5 + read-only + + + + + + + PSEC + PSEC + PSEC + 0xf40cc000 + + 0x0 + 0x18 + registers + + + + SECURE_STATE + Secure state + 0x0 + 32 + 0x00000000 + 0x000300F0 + + + ALLOW_NSC + Non-secure state allow +0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter non-secure state + 17 + 1 + read-only + + + ALLOW_SEC + Secure state allow +0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter secure state + 16 + 1 + read-only + + + PMIC_FAIL + PMIC secure state one hot indicator +0: secure state is not in fail state +1: secure state is in fail state + 7 + 1 + read-write + + + PMIC_NSC + PMIC secure state one hot indicator +0: secure state is not in non-secure state +1: secure state is in non-secure state + 6 + 1 + read-write + + + PMIC_SEC + PMIC secure state one hot indicator +0: secure state is not in secure state +1: secure state is in secure state + 5 + 1 + read-write + + + PMIC_INS + PMIC secure state one hot indicator +0: secure state is not in inspect state +1: secure state is in inspect state + 4 + 1 + read-write + + + + + SECURE_STATE_CONFIG + secure state configuration + 0x4 + 32 + 0x00000000 + 0x00000009 + + + LOCK + Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset +0: not locked, register can be modified +1: register locked, write access to the register is ignored + 3 + 1 + read-write + + + ALLOW_RESTART + allow secure state restart from fail state +0: restart is not allowed, only hardware reset can recover secure state +1: software is allowed to switch to inspect state from fail state + 0 + 1 + read-write + + + + + VIOLATION_CONFIG + Security violation config + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 0 + 15 + read-write + + + + + ESCALATE_CONFIG + Escalate behavior on security event + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 0 + 15 + read-write + + + + + EVENT + Event and escalate status + 0x10 + 32 + 0x00000000 + 0xFFFF000C + + + EVENT + local event statue, each bit represents one security event + 16 + 16 + read-only + + + PMIC_ESC_NSC + PMIC is escalating non-secure event + 3 + 1 + read-only + + + PMIC_ESC_SEC + PMIC is escalting secure event + 2 + 1 + read-only + + + + + LIFECYCLE + Lifecycle + 0x14 + 32 + 0x00000000 + 0x000000FF + + + LIFECYCLE + lifecycle status, +bit7: lifecycle_debate, +bit6: lifecycle_scribe, +bit5: lifecycle_no_ret, +bit4: lifecycle_return, +bit3: lifecycle_secure, +bit2: lifecycle_nonsec, +bit1: lifecycle_create, +bit0: lifecycle_unknow + 0 + 8 + read-only + + + + + + + PMON + PMON + PMON + 0xf40d0000 + + 0x0 + 0x48 + registers + + + + 4 + 0x8 + glitch0,glitch1,clock0,clock1 + MONITOR[%s] + no description available + 0x0 + + CONTROL + Glitch and clock monitor control + 0x0 + 32 + 0x00000000 + 0x00000011 + + + ACTIVE + select glitch works in active mode or passve mode. +0: passive mode, depends on power glitch destroy DFF value +1: active mode, check glitch by DFF chain + 4 + 1 + read-write + + + ENABLE + enable glitch detector +0: detector disabled +1: detector enabled + 0 + 1 + read-write + + + + + STATUS + Glitch and clock monitor status + 0x4 + 32 + 0x00000000 + 0x00000001 + + + FLAG + flag for glitch detected, write 1 to clear this flag +0: glitch not detected +1: glitch detected + 0 + 1 + read-write + + + + + + IRQ_FLAG + No description available + 0x40 + 32 + 0x00000000 + 0x0000000F + + + FLAG + interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag +0: no monitor interrupt +1: monitor interrupt happened + 0 + 4 + read-write + + + + + IRQ_ENABLE + No description available + 0x44 + 32 + 0x00000000 + 0x0000000F + + + ENABLE + interrupt enable, each bit represents for one monitor +0: monitor interrupt disabled +1: monitor interrupt enabled + 0 + 4 + read-write + + + + + + + PGPR + PGPR + PGPR + 0xf40d4000 + + 0x0 + 0x40 + registers + + + + PMIC_GPR00 + Generic control + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR01 + Generic control + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR02 + Generic control + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR03 + Generic control + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR04 + Generic control + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR05 + Generic control + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR06 + Generic control + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR07 + Generic control + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR08 + Generic control + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR09 + Generic control + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR10 + Generic control + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR11 + Generic control + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR12 + Generic control + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR13 + Generic control + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR14 + Generic control + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR15 + Generic control + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + + + PLLCTLV2 + PLLCTLV2 + PLLCTLV2 + 0xf4100000 + + 0x0 + 0x200 + registers + + + + XTAL + OSC configuration + 0x0 + 32 + 0x0001FFFF + 0xB00FFFFF + + + BUSY + Busy flag +0: Oscillator is working or shutdown +1: Oscillator is changing status + 31 + 1 + read-only + + + RESPONSE + Crystal oscillator status +0: Oscillator is not stable +1: Oscillator is stable for use + 29 + 1 + read-only + + + ENABLE + Crystal oscillator enable status +0: Oscillator is off +1: Oscillator is on + 28 + 1 + read-only + + + RAMP_TIME + Rampup time of XTAL oscillator in cycles of RC24M clock +0: 0 cycle +1: 1 cycle +2: 2 cycle +1048575: 1048575 cycles + 0 + 20 + read-write + + + + + 3 + 0x80 + pll0,pll1,pll2 + PLL[%s] + no description available + 0x80 + + MFI + PLL0 multiple register + 0x0 + 32 + 0x00000010 + 0xB000007F + + + BUSY + Busy flag +0: PLL is stable or shutdown +1: PLL is changing status + 31 + 1 + read-only + + + RESPONSE + PLL status +0: PLL is not stable +1: PLL is stable for use + 29 + 1 + read-only + + + ENABLE + PLL enable status +0: PLL is off +1: PLL is on + 28 + 1 + read-only + + + MFI + loop back divider of PLL, support from 13 to 42, f=fref*(mfi + mfn/mfd) +0-15: invalid +16: divide by 16 +17: divide by17 +. . . +42: divide by 42 +43~:invalid + 0 + 7 + read-write + + + + + MFN + PLL0 fraction numerator register + 0x4 + 32 + 0x09896800 + 0x3FFFFFFF + + + MFN + Numeratorof fractional part,f=fref*(mfi + mfn/mfd). This field supports changing while running. + 0 + 30 + read-write + + + + + MFD + PLL0 fraction demoninator register + 0x8 + 32 + 0x0E4E1C00 + 0x3FFFFFFF + + + MFD + Demoninator of fraction part,f=fref*(mfi + mfn/mfd). This field should not be changed during PLL enabled. If changed, change will take efftect when PLL re-enabled. + 0 + 30 + read-write + + + + + SS_STEP + PLL0 spread spectrum step register + 0xc + 32 + 0x00000000 + 0x3FFFFFFF + + + STEP + Step of spread spectrum modulator. +This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. + 0 + 30 + read-write + + + + + SS_STOP + PLL0 spread spectrum stop register + 0x10 + 32 + 0x00000000 + 0x3FFFFFFF + + + STOP + Stop point of spread spectrum modulator +This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. + 0 + 30 + read-write + + + + + CONFIG + PLL0 confguration register + 0x14 + 32 + 0x00000000 + 0x00000101 + + + SPREAD + Enable spread spectrum function. This field supports changing during PLL running. + 8 + 1 + read-write + + + REFSEL + Select reference clock, This filed support changing while running, but application must take frequency error and jitter into consideration. And if MFN changed before reference switch, application need make sure time is enough for MFN updating. +0: XTAL24M +1: IRC24M + 0 + 1 + read-write + + + + + LOCKTIME + PLL0 lock time register + 0x18 + 32 + 0x000009C4 + 0x0000FFFF + + + LOCKTIME + Lock time of PLL in 24M clock cycles, typical value is 2500. If MFI changed during PLL startup, PLL lock time may be longer than this setting. + 0 + 16 + read-write + + + + + STEPTIME + PLL0 step time register + 0x1c + 32 + 0x000009C4 + 0x0000FFFF + + + STEPTIME + Step time for MFI on-the-fly change in 24M clock cycles, typical value is 2500. + 0 + 16 + read-write + + + + + ADVANCED + PLL0 advance configuration register + 0x20 + 32 + 0x00000000 + 0x11000000 + + + SLOW + Use slow lock flow, PLL lock expendite is disabled. This mode might be stabler. And software need config LOCKTIME field accordingly. +0: fast lock enabled, lock time is 100us +1: fast lock disabled, lock time is 400us + 28 + 1 + read-write + + + DITHER + Enable dither function + 24 + 1 + read-write + + + + + 3 + 0x4 + DIV0,DIV1,DIV2 + DIV[%s] + no description available + 0x40 + 32 + 0x00000000 + 0xB000003F + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Divider response status +0: Divider is not stable +1: Divider is stable for use + 29 + 1 + read-only + + + ENABLE + Divider enable status +0: Divider is off +1: Divider is on + 28 + 1 + read-only + + + DIV + Divider factor, divider factor is DIV/5 + 1 +0: divide by 1 +1: divide by 1.2 +2: divide by 1.4 +. . . +63: divide by 13.6 + 0 + 6 + read-write + + + + + + + + TSNS + TSNS + TSNS + 0xf4104000 + + 0x0 + 0x3c + registers + + + + T + Temperature + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Signed number of temperature in 256 x celsius degree + 0 + 32 + read-only + + + + + TMAX + Maximum Temperature + 0x4 + 32 + 0xFF800000 + 0xFFFFFFFF + + + T + maximum temperature ever found + 0 + 32 + read-only + + + + + TMIN + Minimum Temperature + 0x8 + 32 + 0x007FFFFF + 0xFFFFFFFF + + + T + minimum temperature ever found + 0 + 32 + read-only + + + + + AGE + Sample age + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + AGE + age of T register in 24MHz clock cycles + 0 + 32 + read-only + + + + + STATUS + Status + 0x10 + 32 + 0x00000000 + 0x80000001 + + + VALID + indicate value in T is valid or not +0: not valid +1:valid + 31 + 1 + read-only + + + TRIGGER + Software trigger for sensing in trigger mode, trigger will be ignored if in sensing or other mode + 0 + 1 + write-only + + + + + CONFIG + Configuration + 0x14 + 32 + 0x00600300 + 0xC3FF0713 + + + IRQ_EN + Enable interrupt + 31 + 1 + read-write + + + RST_EN + Enable reset + 30 + 1 + read-write + + + COMPARE_MIN_EN + Enable compare for minimum temperature + 25 + 1 + read-write + + + COMPARE_MAX_EN + Enable compare for maximum temperature + 24 + 1 + read-write + + + SPEED + cycles of a progressive step in 24M clock, valid from 24-255, default 96 +24: 24 cycle for a step +25: 25 cycle for a step +26: 26 cycle for a step +... +255: 255 cycle for a step + 16 + 8 + read-write + + + AVERAGE + Average time, default in 3 +0: measure and return +1: twice and average +2: 4 times and average +. . . +7: 128 times and average + 8 + 3 + read-write + + + CONTINUOUS + continuous mode that keep sampling temperature peridically +0: trigger mode +1: continuous mode + 4 + 1 + read-write + + + ASYNC + Acynchronous mode, this mode can work without clock, only available function ios compare to certain ADC value +0: active mode +1: Async mode + 1 + 1 + read-write + + + ENABLE + Enable temperature +0: disable, temperature sensor is shut down +1: enable. Temperature sensor enabled + 0 + 1 + read-write + + + + + VALIDITY + Sample validity + 0x18 + 32 + 0x016E3600 + 0xFFFFFFFF + + + VALIDITY + time for temperature values to expire in 24M clock cycles + 0 + 32 + read-write + + + + + FLAG + Temperature flag + 0x1c + 32 + 0x00000000 + 0x00330001 + + + RECORD_MIN_CLR + Clear minimum recorder of temerature, write 1 to clear + 21 + 1 + read-write + + + RECORD_MAX_CLR + Clear maximum recorder of temerature, write 1 to clear + 20 + 1 + read-write + + + UNDER_TEMP + Clear under temperature status, write 1 to clear + 17 + 1 + read-write + + + OVER_TEMP + Clear over temperature status, write 1 to clear + 16 + 1 + read-write + + + IRQ + IRQ flag, write 1 to clear + 0 + 1 + read-write + + + + + UPPER_LIM_IRQ + Maximum temperature to interrupt + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Maximum temperature for compare + 0 + 32 + read-write + + + + + LOWER_LIM_IRQ + Minimum temperature to interrupt + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Minimum temperature for compare + 0 + 32 + read-write + + + + + UPPER_LIM_RST + Maximum temperature to reset + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Maximum temperature for compare + 0 + 32 + read-write + + + + + LOWER_LIM_RST + Minimum temperature to reset + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Minimum temperature for compare + 0 + 32 + read-write + + + + + ASYNC + Configuration in asynchronous mode + 0x30 + 32 + 0x00000000 + 0x010107FF + + + ASYNC_TYPE + Compare hotter than or colder than in asynchoronous mode +0: hotter than +1: colder than + 24 + 1 + read-write + + + POLARITY + Polarity of internal comparator + 16 + 1 + read-write + + + VALUE + Value of async mode to compare + 0 + 11 + read-write + + + + + ADVAN + Advance configuration + 0x38 + 32 + 0x00000000 + 0x03010003 + + + ASYNC_IRQ + interrupt status of asynchronous mode + 25 + 1 + read-only + + + ACTIVE_IRQ + interrupt status of active mode + 24 + 1 + read-only + + + SAMPLING + temperature sampling is working + 16 + 1 + read-only + + + NEG_ONLY + use negative compare polarity only + 1 + 1 + read-write + + + POS_ONLY + use positive compare polarity only + 0 + 1 + read-write + + + + + + + BACC + BACC + BACC + 0xf5000000 + + 0x0 + 0x10 + registers + + + + CONFIG + Access timing for access + 0x0 + 32 + 0x00000000 + 0x3000FFFF + + + FAST_WRITE + Use fast write +0: Write normally +1: boost write + 29 + 1 + read-write + + + FAST_READ + Use fast read +0: Read normally +1: boost read + 28 + 1 + read-write + + + TIMING + Time in APB clock cycles, for battery timing penerate + 0 + 16 + read-write + + + + + PRE_TIME + Timing gap before rising edge + 0x8 + 32 + 0x00000000 + 0x000FFFFF + + + PRE_RATIO + Ratio of guard band before rising edge +0: 0 +1: 1/32768 of low level width +2: 1/16384 of low level width +14: 1/4 of low level width +15: 1/2 of low level width + 16 + 4 + read-write + + + PRE_OFFSET + guard band before rising edge +this value will be added to ratio number + 0 + 16 + read-write + + + + + POST_TIME + Timing gap after rising edge + 0xc + 32 + 0x00000000 + 0x000FFFFF + + + POST_RATIO + Ratio of guard band after rising edge +0: 0 +1: 1/32768 of high level width +2: 1/16384 of high level width +14: 1/4 of high level width +15: 1/2 of high level width + 16 + 4 + read-write + + + POST_OFFSET + guard band after rising edge +this value will be added to ratio number + 0 + 16 + read-write + + + + + + + BPOR + BPOR + BPOR + 0xf5004000 + + 0x0 + 0x10 + registers + + + + POR_CAUSE + Power on cause + 0x0 + 32 + 0x00000000 + 0x0000001F + + + CAUSE + Power on cause, each bit represnts one cause, write 1 to clear each bit +bit0: wakeup button +bit1: security violation +bit2: RTC alarm 0 +bit3: RTC alarm 1 +bit4: GPIO + 0 + 5 + read-write + + + + + POR_SELECT + Power on select + 0x4 + 32 + 0x00000000 + 0x0000001F + + + SELECT + Power on cause select, each bit represnts one cause, value 1 enables corresponding cause +bit0: wakeup button +bit1: security violation +bit2: RTC alarm 0 +bit3: RTC alarm 1 +bit4: GPIO + 0 + 5 + read-write + + + + + POR_CONFIG + Power on reset config + 0x8 + 32 + 0x00000000 + 0x00000001 + + + RETENTION + retention battery domain setting +0: battery reset on reset pin reset happen +1: battery domain retention when reset pin reset happen + 0 + 1 + read-write + + + + + POR_CONTROL + Power down control + 0xc + 32 + 0x00000000 + 0x0000FFFF + + + COUNTER + Chip power down counter, counter decreasing if value is not 0, power down of chip happens on counter value is 1 + 0 + 16 + read-write + + + + + + + BCFG + BCFG + TRIM + 0xf5008000 + + 0x0 + 0x14 + registers + + + + VBG_CFG + Bandgap config + 0x0 + 32 + 0x00000000 + 0x831F1F1F + + + VBG_TRIMMED + Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: bandgap is not trimmed +1: bandgap is trimmed + 31 + 1 + read-write + + + LP_MODE + Bandgap works in low power mode +0: not in low power mode +1: bandgap work in low power mode + 25 + 1 + read-write + + + POWER_SAVE + Bandgap works in power save mode +0: not in power save mode +1: bandgap work in power save mode + 24 + 1 + read-write + + + VBG_1P0 + Bandgap 1.0V output trim + 16 + 5 + read-write + + + VBG_P65 + Bandgap 0.65V output trim + 8 + 5 + read-write + + + VBG_P50 + Bandgap 0.50V output trim + 0 + 5 + read-write + + + + + IRC32K_CFG + On-chip 32k oscillator config + 0x8 + 32 + 0x00000000 + 0x80C001FF + + + IRC_TRIMMED + IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: irc is not trimmed +1: irc is trimmed + 31 + 1 + read-write + + + CAPEX7_TRIM + IRC32K bit 7 + 23 + 1 + read-write + + + CAPEX6_TRIM + IRC32K bit 6 + 22 + 1 + read-write + + + CAP_TRIM + capacitor trim bits + 0 + 9 + read-write + + + + + XTAL32K_CFG + XTAL 32K config + 0xc + 32 + 0x00000000 + 0x00001313 + + + HYST_EN + crystal 32k hysteres enable + 12 + 1 + read-write + + + GMSEL + crystal 32k gm selection + 8 + 2 + read-write + + + CFG + crystal 32k config + 4 + 1 + read-write + + + AMP + crystal 32k amplifier + 0 + 2 + read-write + + + + + CLK_CFG + Clock config + 0x10 + 32 + 0x00000000 + 0x10010010 + + + XTAL_SEL + crystal selected + 28 + 1 + read-only + + + KEEP_IRC + force irc32k run + 16 + 1 + read-write + + + FORCE_XTAL + force switch to crystal + 4 + 1 + read-write + + + + + + + BUTN + BUTN + BUTN + 0xf500c000 + + 0x0 + 0xc + registers + + + + BTN_STATUS + Button status + 0x0 + 32 + 0x00000000 + 0x77770FFF + + + XWCLICK + wake button click status when power button held, write 1 to clear flag +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 28 + 3 + read-write + + + WCLICK + wake button click status, write 1 to clear flag +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 24 + 3 + read-write + + + XPCLICK + power button click status when wake button held, write 1 to clear flag +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 20 + 3 + read-write + + + PCLICK + power button click status, write 1 to clear flag +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 16 + 3 + read-write + + + DBTN + Dual button press status, write 1 to clear flag +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 8 + 4 + read-write + + + WBTN + Wake button press status, write 1 to clear flag +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 4 + 4 + read-write + + + PBTN + Power button press status, write 1 to clear flag +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 0 + 4 + read-write + + + + + BTN_IRQ_MASK + Button interrupt mask + 0x4 + 32 + 0x00000000 + 0x77770FFF + + + XWCLICK + wake button click status when power button held interrupt enable +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 28 + 3 + read-write + + + WCLICK + wake button click interrupt enable +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 24 + 3 + read-write + + + XPCLICK + power button click status when wake button held interrupt enable +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 20 + 3 + read-write + + + PCLICK + power button click interrupt enable +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 16 + 3 + read-write + + + DBTN + Dual button press interrupt enable +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 8 + 4 + read-write + + + WBTN + Wake button press interrupt enable +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 4 + 4 + read-write + + + PBTN + Power button press interrupt enable +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 0 + 4 + read-write + + + + + LED_INTENSE + Debounce setting + 0x8 + 32 + 0x00000000 + 0x000F000F + + + RLED + Rbutton brightness 0 + 16 + 4 + read-write + + + PLED + Pbutton brightness 0 + 0 + 4 + read-write + + + + + + + BGPR + BGPR + BGPR + 0xf5018000 + + 0x0 + 0x20 + registers + + + + 8 + 0x4 + 0,1,2,3,4,5,6,7 + GPR[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + Generic control + 0 + 32 + read-write + + + + + + + BSEC + BSEC + BSEC + 0xf5040000 + + 0x0 + 0x14 + registers + + + + SECURE_STATE + Secure state + 0x0 + 32 + 0x00000000 + 0x0003000F + + + ALLOW_NSC + Non-secure state allow +0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter non-secure state + 17 + 1 + read-only + + + ALLOW_SEC + Secure state allow +0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter secure state + 16 + 1 + read-only + + + BATT_FAIL + BATT secure state one hot indicator +0: secure state is not in fail state +1: secure state is in fail state + 3 + 1 + read-write + + + BATT_NSC + BATT secure state one hot indicator +0: secure state is not in non-secure state +1: secure state is in non-secure state + 2 + 1 + read-write + + + BATT_SEC + BATT secure state one hot indicator +0: secure state is not in secure state +1: secure state is in secure state + 1 + 1 + read-write + + + BATT_INS + BATT secure state one hot indicator +0: secure state is not in inspect state +1: secure state is in inspect state + 0 + 1 + read-write + + + + + SECURE_STATE_CONFIG + secure state configuration + 0x4 + 32 + 0x00000000 + 0x00000009 + + + LOCK + Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset +0: not locked, register can be modified +1: register locked, write access to the register is ignored + 3 + 1 + read-write + + + ALLOW_RESTART + allow secure state restart from fail state +0: restart is not allowed, only hardware reset can recover secure state +1: software is allowed to switch to inspect state from fail state + 0 + 1 + read-write + + + + + VIOLATION_CONFIG + Security violation config + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 0 + 15 + read-write + + + + + ESCALATE_CONFIG + Escalate behavior on security event + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 0 + 15 + read-write + + + + + EVENT + Event and escalate status + 0x10 + 32 + 0x00000000 + 0xFFFF0003 + + + EVENT + local event statue, each bit represents one security event + 16 + 16 + read-only + + + BATT_ESC_NSC + BATT is escalating non-secure event + 1 + 1 + read-only + + + BATT_ESC_SEC + BATT is escalting ssecure event + 0 + 1 + read-only + + + + + + + RTC + RTC + RTC + 0xf5044000 + + 0x0 + 0x28 + registers + + + + SECOND + Second counter + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SECOND + second counter + 0 + 32 + read-write + + + + + SUBSEC + Sub-second counter + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SUBSEC + sub second counter + 0 + 32 + read-only + + + + + SEC_SNAP + Second counter snap shot + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SEC_SNAP + second snap shot, write to take snap shot + 0 + 32 + read-write + + + + + SUB_SNAP + Sub-second counter snap shot + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + SUB_SNAP + sub second snap shot, write to take snap shot + 0 + 32 + read-write + + + + + ALARM0 + RTC alarm0 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + ALARM + Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC + 0 + 32 + read-write + + + + + ALARM0_INC + Alarm0 incremental + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + INCREASE + adder when ARLAM0 happen, helps to create periodical alarm + 0 + 32 + read-write + + + + + ALARM1 + RTC alarm1 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + ALARM + Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC + 0 + 32 + read-write + + + + + ALARM1_INC + Alarm1 incremental + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + INCREASE + adder when ARLAM0 happen, helps to create periodical alarm + 0 + 32 + read-write + + + + + ALARM_FLAG + RTC alarm flag + 0x20 + 32 + 0x00000000 + 0x00000003 + + + ALARM1 + alarm1 happen + 1 + 1 + read-write + + + ALARM0 + alarm0 happen + 0 + 1 + read-write + + + + + ALARM_EN + RTC alarm enable + 0x24 + 32 + 0x00000000 + 0x00000003 + + + ENABLE1 + alarm1 mask +0: alarm1 disabled +1: alarm1 enabled + 1 + 1 + read-write + + + ENABLE0 + alarm0 mask +0: alarm0 disabled +1: alarm0 enabled + 0 + 1 + read-write + + + + + + + BKEY + BKEY + BKEY + 0xf5048000 + + 0x0 + 0x4c + registers + + + + 2 + 0x20 + 0,1 + KEY[%s] + no description available + 0x0 + + 8 + 0x4 + 0,1,2,3,4,5,6,7 + DATA[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + + 2 + 0x4 + KEY0,KEY1 + ECC[%s] + no description available + 0x40 + 32 + 0x00000000 + 0xC000FFFF + + + WLOCK + write lock to key0 +0: write enable +1: write ignored + 31 + 1 + read-write + + + RLOCK + read lock to key0 +0: key read enable +1: key always read as 0 + 30 + 1 + read-write + + + ECC + Parity check bits for key0 + 0 + 16 + read-write + + + + + SELECT + Key selection + 0x48 + 32 + 0x00000000 + 0x00000001 + + + SELECT + select key, key0 treated as secure key, in non-scure mode, only key1 can be selected +0: select key0 in secure mode, key1 in non-secure mode +1: select key1 in secure or nonsecure mode + 0 + 1 + read-write + + + + + + + BMON + BMON + BMON + 0xf504c000 + + 0x0 + 0x20 + registers + + + + 2 + 0x10 + glitch0,clock0 + MONITOR[%s] + no description available + 0x0 + + CONTROL + Glitch and clock monitor control + 0x0 + 32 + 0x00000000 + 0x00000011 + + + ACTIVE + select glitch works in active mode or passve mode. +0: passive mode, depends on power glitch destroy DFF value +1: active mode, check glitch by DFF chain + 4 + 1 + read-write + + + ENABLE + enable glitch detector +0: detector disabled +1: detector enabled + 0 + 1 + read-write + + + + + STATUS + Glitch and clock monitor status + 0x4 + 32 + 0x00000000 + 0x00000001 + + + FLAG + flag for glitch detected, write 1 to clear this flag +0: glitch not detected +1: glitch detected + 0 + 1 + read-write + + + + + + + + TAMP + TAMP + TAMP + 0xf5050000 + + 0x0 + 0x88 + registers + + + + 4 + 0x10 + tamp0,tamp1,tamp2,tamp3 + TAMP[%s] + no description available + 0x0 + + CONTROL + Tamper n control + 0x0 + 32 + 0x00000000 + 0x801F03F7 + + + LOCK + lock tamper setting +0: tamper setting can be changed +1: tamper setting will last to next battery domain power cycle + 31 + 1 + read-write + + + BYPASS + bypass tamper violation filter +0: filter applied +1: filter not used + 20 + 1 + read-write + + + FILTER + filter length +0: 1 cycle +1: 2 cycle +15: 65526 cycle + 16 + 4 + read-write + + + VALUE + pin value for passive tamper + 8 + 2 + read-write + + + SPEED + tamper speed selection, (2^SPEED) changes per second +0: 1 shift per second +1: 2 shifts per second +. . . +15: 32768 shifts per second + 4 + 4 + read-write + + + RECOVER + tamper will recover itself if tamper LFSR goes wrong +0: tamper will not recover +1: tamper will recover + 2 + 1 + read-write + + + ACTIVE + select active or passive tamper +0: passive tamper +1: active tamper + 1 + 1 + read-write + + + ENABLE + enable tamper +0: tamper disableed +1: tamper enabled + 0 + 1 + read-write + + + + + POLY + Tamper n Polynomial of LFSR + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + POLY + tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" + 0 + 32 + read-write + + + + + LFSR + Tamper n LFSR shift register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + LFSR + LFSR for active tamper, write only register, always read 0 + 0 + 32 + write-only + + + + + + TAMP_FLAG + Tamper flag + 0x80 + 32 + 0x00000000 + 0x00000FFF + + + FLAG + tamper flag, each bit represents one tamper pin, write 1 to clear the flag +Note, clear can only be cleared when tamper disappeared + 0 + 12 + read-write + + + + + IRQ_EN + Tamper interrupt enable + 0x84 + 32 + 0x00000000 + 0x80000FFF + + + LOCK + lock bit for IRQ enable +0: enable bits can be changed +1: enable bits hold until next battery domain power cycle + 31 + 1 + read-write + + + IRQ_EN + interrupt enable, each bit represents one tamper pin +0: interrupt disabled +1: interrupt enabled + 0 + 12 + read-write + + + + + + + MONO + MONO + MONO + 0xf5054000 + + 0x0 + 0x8 + registers + + + + MONOL + Low part of monotonic counter + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + low part of monotonica counter, write to this counter will cause counter increase by 1 + 0 + 32 + read-write + + + + + MONOH + High part of monotonic counter + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + EPOCH + Fuse value for high part of monotonica + 16 + 16 + read-write + + + COUNTER + high part of monotonica counter, write to this counter will cause counter increase by 1 if low part overflow + 0 + 16 + read-write + + + + + + + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_batt_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_batt_iomux.h index ed18058f0eb..9978a0fcaaf 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_batt_iomux.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_batt_iomux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -9,51 +9,81 @@ #ifndef HPM_BATT_IOMUX_H #define HPM_BATT_IOMUX_H -/* IOC_PZ00_FUNC_CTL function mux definitions */ -#define IOC_PZ00_FUNC_CTL_BGPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ00_FUNC_CTL_BATT_PWR_ON IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ00_FUNC_CTL_BATT_TAMPER_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ00_FUNC_CTL_SOC_GPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PZ01_FUNC_CTL function mux definitions */ -#define IOC_PZ01_FUNC_CTL_BGPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ01_FUNC_CTL_BATT_RESETN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ01_FUNC_CTL_BATT_TAMPER_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ01_FUNC_CTL_SOC_GPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PZ02_FUNC_CTL function mux definitions */ -#define IOC_PZ02_FUNC_CTL_BGPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ02_FUNC_CTL_BATT_PBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ02_FUNC_CTL_BATT_TAMPER_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ02_FUNC_CTL_SOC_GPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PZ03_FUNC_CTL function mux definitions */ -#define IOC_PZ03_FUNC_CTL_BGPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ03_FUNC_CTL_BATT_WBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ03_FUNC_CTL_BATT_TAMPER_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ03_FUNC_CTL_SOC_GPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PZ04_FUNC_CTL function mux definitions */ -#define IOC_PZ04_FUNC_CTL_BGPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ04_FUNC_CTL_BATT_PLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ04_FUNC_CTL_BATT_TAMPER_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ04_FUNC_CTL_SOC_GPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PZ05_FUNC_CTL function mux definitions */ -#define IOC_PZ05_FUNC_CTL_BGPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ05_FUNC_CTL_BATT_WLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ05_FUNC_CTL_BATT_TAMPER_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ05_FUNC_CTL_SOC_GPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PZ06_FUNC_CTL function mux definitions */ -#define IOC_PZ06_FUNC_CTL_BGPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ06_FUNC_CTL_BATT_TAMPER_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ06_FUNC_CTL_SOC_GPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PZ07_FUNC_CTL function mux definitions */ -#define IOC_PZ07_FUNC_CTL_BGPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ07_FUNC_CTL_BATT_TAMPER_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ07_FUNC_CTL_SOC_GPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +/* BIOC_PZ00_FUNC_CTL function mux definitions */ +#define IOC_PZ00_FUNC_CTL_BGPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ00_FUNC_CTL_BGPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ00_FUNC_CTL_BATT_PWR_ON IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ00_FUNC_CTL_BATT_PWR_ON IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ00_FUNC_CTL_BATT_TAMPER_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ00_FUNC_CTL_BATT_TAMPER_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ00_FUNC_CTL_SOC_GPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ00_FUNC_CTL_SOC_GPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ01_FUNC_CTL function mux definitions */ +#define IOC_PZ01_FUNC_CTL_BGPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ01_FUNC_CTL_BGPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ01_FUNC_CTL_BATT_RESETN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ01_FUNC_CTL_BATT_RESETN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ01_FUNC_CTL_BATT_TAMPER_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ01_FUNC_CTL_BATT_TAMPER_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ01_FUNC_CTL_SOC_GPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ01_FUNC_CTL_SOC_GPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ02_FUNC_CTL function mux definitions */ +#define IOC_PZ02_FUNC_CTL_BGPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ02_FUNC_CTL_BGPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ02_FUNC_CTL_BATT_PBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ02_FUNC_CTL_BATT_PBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ02_FUNC_CTL_BATT_TAMPER_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ02_FUNC_CTL_BATT_TAMPER_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ02_FUNC_CTL_SOC_GPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ02_FUNC_CTL_SOC_GPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ03_FUNC_CTL function mux definitions */ +#define IOC_PZ03_FUNC_CTL_BGPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ03_FUNC_CTL_BGPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ03_FUNC_CTL_BATT_WBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ03_FUNC_CTL_BATT_WBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ03_FUNC_CTL_BATT_TAMPER_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ03_FUNC_CTL_BATT_TAMPER_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ03_FUNC_CTL_SOC_GPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ03_FUNC_CTL_SOC_GPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ04_FUNC_CTL function mux definitions */ +#define IOC_PZ04_FUNC_CTL_BGPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ04_FUNC_CTL_BGPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ04_FUNC_CTL_BATT_PLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ04_FUNC_CTL_BATT_PLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ04_FUNC_CTL_BATT_TAMPER_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ04_FUNC_CTL_BATT_TAMPER_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ04_FUNC_CTL_SOC_GPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ04_FUNC_CTL_SOC_GPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ05_FUNC_CTL function mux definitions */ +#define IOC_PZ05_FUNC_CTL_BGPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ05_FUNC_CTL_BGPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ05_FUNC_CTL_BATT_WLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ05_FUNC_CTL_BATT_WLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ05_FUNC_CTL_BATT_TAMPER_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ05_FUNC_CTL_BATT_TAMPER_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ05_FUNC_CTL_SOC_GPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ05_FUNC_CTL_SOC_GPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ06_FUNC_CTL function mux definitions */ +#define IOC_PZ06_FUNC_CTL_BGPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ06_FUNC_CTL_BGPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ06_FUNC_CTL_BATT_TAMPER_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ06_FUNC_CTL_BATT_TAMPER_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ06_FUNC_CTL_SOC_GPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ06_FUNC_CTL_SOC_GPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ07_FUNC_CTL function mux definitions */ +#define IOC_PZ07_FUNC_CTL_BGPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ07_FUNC_CTL_BGPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ07_FUNC_CTL_BATT_TAMPER_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ07_FUNC_CTL_BATT_TAMPER_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ07_FUNC_CTL_SOC_GPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ07_FUNC_CTL_SOC_GPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #endif /* HPM_BATT_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_bcfg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_bcfg_regs.h index 50cbd1b455a..56355a5e012 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_bcfg_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_bcfg_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_bgpr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_bgpr_regs.h index 46bb7beb07b..9d81aab19cf 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_bgpr_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_bgpr_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -10,106 +10,32 @@ #define HPM_BGPR_H typedef struct { - __RW uint32_t BATT_GPR0; /* 0x0: Generic control */ - __RW uint32_t BATT_GPR1; /* 0x4: Generic control */ - __RW uint32_t BATT_GPR2; /* 0x8: Generic control */ - __RW uint32_t BATT_GPR3; /* 0xC: Generic control */ - __RW uint32_t BATT_GPR4; /* 0x10: Generic control */ - __RW uint32_t BATT_GPR5; /* 0x14: Generic control */ - __RW uint32_t BATT_GPR6; /* 0x18: Generic control */ - __RW uint32_t BATT_GPR7; /* 0x1C: Generic control */ + __RW uint32_t GPR[8]; /* 0x0 - 0x1C: Generic control */ } BGPR_Type; -/* Bitfield definition for register: BATT_GPR0 */ +/* Bitfield definition for register array: GPR */ /* - * GPR (RW) + * DATA (RW) * * Generic control */ -#define BGPR_BATT_GPR0_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR0_GPR_SHIFT (0U) -#define BGPR_BATT_GPR0_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR0_GPR_SHIFT) & BGPR_BATT_GPR0_GPR_MASK) -#define BGPR_BATT_GPR0_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR0_GPR_MASK) >> BGPR_BATT_GPR0_GPR_SHIFT) +#define BGPR_GPR_DATA_MASK (0xFFFFFFFFUL) +#define BGPR_GPR_DATA_SHIFT (0U) +#define BGPR_GPR_DATA_SET(x) (((uint32_t)(x) << BGPR_GPR_DATA_SHIFT) & BGPR_GPR_DATA_MASK) +#define BGPR_GPR_DATA_GET(x) (((uint32_t)(x) & BGPR_GPR_DATA_MASK) >> BGPR_GPR_DATA_SHIFT) -/* Bitfield definition for register: BATT_GPR1 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR1_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR1_GPR_SHIFT (0U) -#define BGPR_BATT_GPR1_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR1_GPR_SHIFT) & BGPR_BATT_GPR1_GPR_MASK) -#define BGPR_BATT_GPR1_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR1_GPR_MASK) >> BGPR_BATT_GPR1_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR2 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR2_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR2_GPR_SHIFT (0U) -#define BGPR_BATT_GPR2_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR2_GPR_SHIFT) & BGPR_BATT_GPR2_GPR_MASK) -#define BGPR_BATT_GPR2_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR2_GPR_MASK) >> BGPR_BATT_GPR2_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR3 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR3_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR3_GPR_SHIFT (0U) -#define BGPR_BATT_GPR3_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR3_GPR_SHIFT) & BGPR_BATT_GPR3_GPR_MASK) -#define BGPR_BATT_GPR3_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR3_GPR_MASK) >> BGPR_BATT_GPR3_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR4 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR4_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR4_GPR_SHIFT (0U) -#define BGPR_BATT_GPR4_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR4_GPR_SHIFT) & BGPR_BATT_GPR4_GPR_MASK) -#define BGPR_BATT_GPR4_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR4_GPR_MASK) >> BGPR_BATT_GPR4_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR5 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR5_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR5_GPR_SHIFT (0U) -#define BGPR_BATT_GPR5_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR5_GPR_SHIFT) & BGPR_BATT_GPR5_GPR_MASK) -#define BGPR_BATT_GPR5_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR5_GPR_MASK) >> BGPR_BATT_GPR5_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR6 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR6_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR6_GPR_SHIFT (0U) -#define BGPR_BATT_GPR6_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR6_GPR_SHIFT) & BGPR_BATT_GPR6_GPR_MASK) -#define BGPR_BATT_GPR6_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR6_GPR_MASK) >> BGPR_BATT_GPR6_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR7 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR7_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR7_GPR_SHIFT (0U) -#define BGPR_BATT_GPR7_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR7_GPR_SHIFT) & BGPR_BATT_GPR7_GPR_MASK) -#define BGPR_BATT_GPR7_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR7_GPR_MASK) >> BGPR_BATT_GPR7_GPR_SHIFT) +/* GPR register group index macro definition */ +#define BGPR_GPR_0 (0UL) +#define BGPR_GPR_1 (1UL) +#define BGPR_GPR_2 (2UL) +#define BGPR_GPR_3 (3UL) +#define BGPR_GPR_4 (4UL) +#define BGPR_GPR_5 (5UL) +#define BGPR_GPR_6 (6UL) +#define BGPR_GPR_7 (7UL) #endif /* HPM_BGPR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_bpor_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_bpor_regs.h index 32147d05a2f..4f48a15578d 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_bpor_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_bpor_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_clock_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_clock_drv.c index e4e9ee440c4..62f0100d33b 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_clock_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_clock_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023 HPMicro + * Copyright (c) 2022-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -20,8 +20,8 @@ #define FREQ_PRESET1_PLL1_CLK2 (250000000UL) #define FREQ_PRESET1_PLL1_CLK0 (480000000UL) #define FREQ_PRESET1_PLL1_CLK1 (320000000UL) -#define FREQ_PRESET1_PLL2_CLK0 (5160960000UL) -#define FREQ_PRESET1_PLL2_CLK1 (4515840000UL) +#define FREQ_PRESET1_PLL2_CLK0 (516096000UL) +#define FREQ_PRESET1_PLL2_CLK1 (451584000UL) #define FREQ_32KHz (32768UL) #define ADC_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->ADCCLK) #define DAC_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->DACCLK) @@ -60,6 +60,11 @@ static uint32_t get_frequency_for_dac(uint32_t instance); */ static uint32_t get_frequency_for_wdg(uint32_t instance); +/** + * @brief Get Clock frequency for PWDG + */ +static uint32_t get_frequency_for_pwdg(void); + /** * @brief Turn on/off the IP clock */ @@ -105,6 +110,9 @@ uint32_t clock_get_frequency(clock_name_t clock_name) case CLK_SRC_GROUP_WDG: clk_freq = get_frequency_for_wdg(node_or_instance); break; + case CLK_SRC_GROUP_PWDG: + clk_freq = get_frequency_for_pwdg(); + break; case CLK_SRC_GROUP_PMIC: clk_freq = FREQ_PRESET1_OSC0_CLK0; break; @@ -236,7 +244,7 @@ static uint32_t get_frequency_for_wdg(uint32_t instance) uint32_t freq_in_hz; /* EXT clock is chosen */ if (WDG_CTRL_CLKSEL_GET(s_wdgs[instance]->CTRL) == 0) { - freq_in_hz = get_frequency_for_cpu(); + freq_in_hz = get_frequency_for_ahb(); } /* PCLK is chosen */ else { @@ -246,6 +254,18 @@ static uint32_t get_frequency_for_wdg(uint32_t instance) return freq_in_hz; } +static uint32_t get_frequency_for_pwdg(void) +{ + uint32_t freq_in_hz; + if (WDG_CTRL_CLKSEL_GET(HPM_PWDG->CTRL) == 0) { + freq_in_hz = FREQ_PRESET1_OSC0_CLK0; + } else { + freq_in_hz = FREQ_32KHz; + } + + return freq_in_hz; +} + static uint32_t get_frequency_for_cpu(void) { uint32_t mux = SYSCTL_CLOCK_CPU_MUX_GET(HPM_SYSCTL->CLOCK_CPU[0]); @@ -282,12 +302,22 @@ clk_src_t clock_get_source(clock_name_t clock_name) clk_src_index = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[node_or_instance]); } break; + case CLK_SRC_GROUP_DAC: + if (node_or_instance < DAC_INSTANCE_NUM) { + clk_src_group = CLK_SRC_GROUP_DAC; + clk_src_index = SYSCTL_DACCLK_MUX_GET(HPM_SYSCTL->DACCLK[node_or_instance]); + } + break; case CLK_SRC_GROUP_WDG: if (node_or_instance < WDG_INSTANCE_NUM) { clk_src_group = CLK_SRC_GROUP_WDG; - clk_src_index = (WDG_CTRL_CLKSEL_GET(s_wdgs[node_or_instance]->CTRL) == 0); + clk_src_index = WDG_CTRL_CLKSEL_GET(s_wdgs[node_or_instance]->CTRL); } break; + case CLK_SRC_GROUP_PWDG: + clk_src_group = CLK_SRC_GROUP_PWDG; + clk_src_index = WDG_CTRL_CLKSEL_GET(HPM_PWDG->CTRL); + break; case CLK_SRC_GROUP_PMIC: clk_src_group = CLK_SRC_GROUP_COMMON; clk_src_index = clock_source_osc0_clk0; @@ -316,6 +346,42 @@ clk_src_t clock_get_source(clock_name_t clock_name) return clk_src; } +uint32_t clock_get_divider(clock_name_t clock_name) +{ + uint32_t clk_divider = CLOCK_DIV_INVALID; + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + switch (clk_src_type) { + case CLK_SRC_GROUP_COMMON: + clk_divider = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[node_or_instance]); + break; + case CLK_SRC_GROUP_WDG: + if (node_or_instance < WDG_INSTANCE_NUM) { + clk_divider = 1UL; + } + break; + case CLK_SRC_GROUP_PWDG: + clk_divider = 1UL; + break; + case CLK_SRC_GROUP_PMIC: + clk_divider = 1UL; + break; + case CLK_SRC_GROUP_CPU0: + clk_divider = 1UL + SYSCTL_CLOCK_CPU_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]); + break; + case CLK_SRC_GROUP_AHB: + clk_divider = 1UL + SYSCTL_CLOCK_CPU_SUB1_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]); + break; + case CLK_SRC_GROUP_AXI: + clk_divider = 1UL + SYSCTL_CLOCK_CPU_SUB0_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]); + break; + default: + clk_divider = CLOCK_DIV_INVALID; + break; + } + return clk_divider; +} + hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src) { uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); @@ -325,13 +391,13 @@ hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src) return status_clk_invalid; } - if ((src <= clk_adc_src_ahb0) || (src >= clk_adc_src_ana2)) { + if ((src < clk_adc_src_ana0) || (src > clk_adc_src_ahb0)) { return status_clk_src_invalid; } uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); HPM_SYSCTL->ADCCLK[node_or_instance] = - (HPM_SYSCTL->ADCCLK[node_or_instance] & SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(clk_src_index); + (HPM_SYSCTL->ADCCLK[node_or_instance] & ~SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(clk_src_index); return status_success; } @@ -351,7 +417,7 @@ hpm_stat_t clock_set_dac_source(clock_name_t clock_name, clk_src_t src) uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); HPM_SYSCTL->DACCLK[node_or_instance] = - (HPM_SYSCTL->DACCLK[node_or_instance] & SYSCTL_DACCLK_MUX_MASK) | SYSCTL_DACCLK_MUX_SET(clk_src_index); + (HPM_SYSCTL->DACCLK[node_or_instance] & ~SYSCTL_DACCLK_MUX_MASK) | SYSCTL_DACCLK_MUX_SET(clk_src_index); return status_success; } @@ -366,22 +432,16 @@ hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint if ((div < 1U) || (div > 256U)) { status = status_clk_div_invalid; } else { - sysctl_config_clock(HPM_SYSCTL, (clock_node_t) node_or_instance, (clock_source_t) src, div); + clock_source_t clk_src = GET_CLOCK_SOURCE_FROM_CLK_SRC(src); + sysctl_config_clock(HPM_SYSCTL, (clock_node_t) node_or_instance, clk_src, div); } break; case CLK_SRC_GROUP_ADC: - status = status_clk_operation_unsupported; - break; + case CLK_SRC_GROUP_DAC: case CLK_SRC_GROUP_WDG: - if (node_or_instance < WDG_INSTANCE_NUM) { - if (src == clk_wdg_src_ahb0) { - s_wdgs[node_or_instance]->CTRL &= ~WDG_CTRL_CLKSEL_MASK; - } else if (src == clk_wdg_src_osc32k) { - s_wdgs[node_or_instance]->CTRL |= WDG_CTRL_CLKSEL_MASK; - } else { - status = status_clk_src_invalid; - } - } + case CLK_SRC_GROUP_PWDG: + case CLK_SRC_GROUP_SRC: + status = status_clk_operation_unsupported; break; case CLK_SRC_GROUP_PMIC: status = status_clk_fixed; @@ -406,9 +466,6 @@ hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint status = status_clk_shared_cpu0; } break; - case CLK_SRC_GROUP_SRC: - status = status_clk_operation_unsupported; - break; default: status = status_clk_src_invalid; break; @@ -417,7 +474,7 @@ hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint return status; } -void switch_ip_clock(clock_name_t clock_name, bool on) +static void switch_ip_clock(clock_name_t clock_name, bool on) { uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); @@ -444,8 +501,6 @@ void clock_add_to_group(clock_name_t clock_name, uint32_t group) if (resource < sysctl_resource_end) { sysctl_enable_group_resource(HPM_SYSCTL, group, resource, true); - } else if (resource == RESOURCE_SHARED_PTPC) { - sysctl_enable_group_resource(HPM_SYSCTL, group, sysctl_resource_ptpc, true); } } @@ -455,11 +510,16 @@ void clock_remove_from_group(clock_name_t clock_name, uint32_t group) if (resource < sysctl_resource_end) { sysctl_enable_group_resource(HPM_SYSCTL, group, resource, false); - } else if (resource == RESOURCE_SHARED_PTPC) { - sysctl_enable_group_resource(HPM_SYSCTL, group, sysctl_resource_ptpc, false); } } +bool clock_check_in_group(clock_name_t clock_name, uint32_t group) +{ + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + return sysctl_check_group_resource_enable(HPM_SYSCTL, group, resource); +} + void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu) { if (cpu < 2U) { diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_clock_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_clock_drv.h index dbfcc718f5e..506d2f71095 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_clock_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_clock_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023 HPMicro + * Copyright (c) 2022-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -11,6 +11,7 @@ #include "hpm_sysctl_drv.h" #include "hpm_csr_drv.h" +#define CLOCK_DIV_INVALID (~0UL) /** * @brief Error codes for clock driver @@ -44,12 +45,15 @@ enum { #define CLK_SRC_GROUP_DAC (7U) #define CLK_SRC_GROUP_CPU0 (9U) #define CLK_SRC_GROUP_SRC (10U) +#define CLK_SRC_GROUP_PWDG (11U) #define CLK_SRC_GROUP_INVALID (15U) #define MAKE_CLK_SRC(src_grp, index) (((uint8_t)(src_grp)<<4) | (index)) #define GET_CLK_SRC_GROUP(src) (((uint8_t)(src)>>4) & 0x0FU) #define GET_CLK_SRC_INDEX(src) ((uint8_t)(src) & 0x0FU) +#define GET_CLOCK_SOURCE_FROM_CLK_SRC(clk_src) (clock_source_t)((uint32_t)(clk_src) & 0xFU) + /** * @brief Clock source definitions */ @@ -64,23 +68,26 @@ typedef enum _clock_sources { clk_src_pll2_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 7), clk_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 8), - clk_adc_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), - clk_adc_src_ana0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 1), - clk_adc_src_ana1 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 2), - clk_adc_src_ana2 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 3), + clk_adc_src_ana0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), + clk_adc_src_ana1 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), + clk_adc_src_ana2 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), + clk_adc_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 1), clk_dac_src_ana3 = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 0), + clk_dac_src_ana4 = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 0), clk_dac_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 1), clk_wdg_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_WDG, 0), clk_wdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_WDG, 1), + clk_pwdg_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_PWDG, 0), + clk_pwdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_PWDG, 1), + clk_src_invalid = MAKE_CLK_SRC(CLK_SRC_GROUP_INVALID, 15), } clk_src_t; #define RESOURCE_INVALID (0xFFFFU) -#define RESOURCE_SHARED_PTPC (0xFFFEU) #define RESOURCE_SHARED_CPU0 (0xFFFDU) /* Clock NAME related Macros */ @@ -135,11 +142,11 @@ typedef enum _clock_name { clock_ptpc = MAKE_CLOCK_NAME(sysctl_resource_ptpc, CLK_SRC_GROUP_COMMON, clock_node_ptpc), clock_ref0 = MAKE_CLOCK_NAME(sysctl_resource_ref0, CLK_SRC_GROUP_COMMON, clock_node_ref0), - clock_ref1 = MAKE_CLOCK_NAME(sysctl_resource_ref1, CLK_SRC_GROUP_COMMON, clock_node_ref0), + clock_ref1 = MAKE_CLOCK_NAME(sysctl_resource_ref1, CLK_SRC_GROUP_COMMON, clock_node_ref1), clock_watchdog0 = MAKE_CLOCK_NAME(sysctl_resource_wdg0, CLK_SRC_GROUP_WDG, 0), clock_watchdog1 = MAKE_CLOCK_NAME(sysctl_resource_wdg1, CLK_SRC_GROUP_WDG, 1), clock_puart = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 0), - clock_pwdg = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 1), + clock_pwdg = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PWDG, 0), clock_sdp = MAKE_CLOCK_NAME(sysctl_resource_sdp0, CLK_SRC_GROUP_AXI, 0), clock_xdma = MAKE_CLOCK_NAME(sysctl_resource_dma1, CLK_SRC_GROUP_AXI, 1), clock_rom = MAKE_CLOCK_NAME(sysctl_resource_rom0, CLK_SRC_GROUP_AXI, 2), @@ -158,6 +165,7 @@ typedef enum _clock_name { clock_acmp = MAKE_CLOCK_NAME(sysctl_resource_acmp, CLK_SRC_GROUP_AHB, 10), clock_msyn = MAKE_CLOCK_NAME(sysctl_resource_msyn, CLK_SRC_GROUP_AHB, 11), clock_sdm0 = MAKE_CLOCK_NAME(sysctl_resource_sdm0, CLK_SRC_GROUP_AHB, 13), + clock_mbx1 = MAKE_CLOCK_NAME(sysctl_resource_mbx1, CLK_SRC_GROUP_AHB, 14), clock_lmm0 = MAKE_CLOCK_NAME(sysctl_resource_lmm0, CLK_SRC_GROUP_CPU0, 0), clock_lmm1 = MAKE_CLOCK_NAME(sysctl_resource_lmm1, CLK_SRC_GROUP_CPU0, 1), clock_tsns = MAKE_CLOCK_NAME(sysctl_resource_tsns, CLK_SRC_GROUP_CPU0, 2), @@ -178,14 +186,14 @@ typedef enum _clock_name { clock_dac1 = MAKE_CLOCK_NAME(sysctl_resource_dac1, CLK_SRC_GROUP_DAC, 1), /* Clock sources */ - clk_osc0clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 0), - clk_pll0clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 1), - clk_pll0clk1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 2), - clk_pll0clk2 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 3), - clk_pll1clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 4), - clk_pll1clk1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 5), - clk_pll2clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 6), - clk_pll2clk1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 7), + clk_osc0clk0 = MAKE_CLOCK_NAME(sysctl_resource_xtal, CLK_SRC_GROUP_SRC, 0), + clk_pll0clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll0, CLK_SRC_GROUP_SRC, 1), + clk_pll0clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll0, CLK_SRC_GROUP_SRC, 2), + clk_pll0clk2 = MAKE_CLOCK_NAME(sysctl_resource_clk2_pll0, CLK_SRC_GROUP_SRC, 3), + clk_pll1clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll1, CLK_SRC_GROUP_SRC, 4), + clk_pll1clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll1, CLK_SRC_GROUP_SRC, 5), + clk_pll2clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll2, CLK_SRC_GROUP_SRC, 6), + clk_pll2clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll2, CLK_SRC_GROUP_SRC, 7), } clock_name_t; extern uint32_t hpm_core_clock; @@ -217,6 +225,14 @@ uint32_t get_frequency_for_source(clock_source_t source); */ clk_src_t clock_get_source(clock_name_t clock_name); +/** + * @brief Get the IP clock divider + * Note:This API return the direct clock divider + * @param [in] clock_name clock name + * @return IP clock divider + */ +uint32_t clock_get_divider(clock_name_t clock_name); + /** * @brief Set ADC clock source * @param[in] clock_name ADC clock name @@ -283,6 +299,14 @@ void clock_add_to_group(clock_name_t clock_name, uint32_t group); */ void clock_remove_from_group(clock_name_t clock_name, uint32_t group); +/** + * @brief Check IP in specified group + * @param[in] clock_name IP clock name + * @param[in] group resource group index, valid value: 0/1/2/3 + * @return true if in group, false if not in group + */ +bool clock_check_in_group(clock_name_t clock_name, uint32_t group); + /** * @brief Disconnect the clock group from specified CPU * @param[in] group clock group index, value value is 0/1/2/3 diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_csr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_csr_regs.h index cc29018e112..5f43b12bd1a 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_csr_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_csr_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_dmamux_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_dmamux_regs.h index 640355344e8..e7f67339ea4 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_dmamux_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_dmamux_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_dmamux_src.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_dmamux_src.h index b444f371ec8..c2a15b87f6f 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_dmamux_src.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_dmamux_src.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_gpiom_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_gpiom_regs.h index 22bff319b2a..5c3eaf6f18f 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_gpiom_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_gpiom_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_gpiom_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_gpiom_soc_drv.h index efeeaa312ea..92d909f9537 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_gpiom_soc_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_gpiom_soc_drv.h @@ -14,7 +14,7 @@ */ /* @brief gpiom control module */ -typedef enum hpm6300_gpiom_gpio { +typedef enum gpiom_gpio { gpiom_soc_gpio0 = 0, gpiom_soc_gpio1 = 1, gpiom_core0_fast = 2, diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_interrupt.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_interrupt.h index 22859a6ee41..810971e255f 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_interrupt.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_interrupt.h @@ -7,8 +7,8 @@ #ifndef HPM_INTERRUPT_H #define HPM_INTERRUPT_H -#include "riscv/riscv_core.h" #include "hpm_common.h" +#include "hpm_csr_drv.h" #include "hpm_plic_drv.h" /** @@ -40,7 +40,7 @@ ATTR_ALWAYS_INLINE static inline void enable_global_irq(uint32_t mask) * @brief Disable global IRQ with mask and return mstatus * * @param[in] mask interrupt mask to be disabled - * @retval current mstatus value before irq disabled + * @retval current mstatus value before irq mask is disabled */ ATTR_ALWAYS_INLINE static inline uint32_t disable_global_irq(uint32_t mask) { @@ -137,7 +137,7 @@ ATTR_ALWAYS_INLINE static inline uint32_t disable_s_global_irq(uint32_t mask) } /** - * @brief Restore global IRQ with mask + * @brief Restore global IRQ with mask for supervisor mode * * @param[in] mask interrupt mask to be restored */ @@ -564,6 +564,59 @@ ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack */ #if __riscv_flen == 32 +#ifdef __ICCRISCV__ +#define SAVE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fswsp ft0, 20*4\n\ + c.fswsp ft1, 21*4 \n\ + c.fswsp ft2, 22*4 \n\ + c.fswsp ft3, 23*4 \n\ + c.fswsp ft4, 24*4 \n\ + c.fswsp ft5, 25*4 \n\ + c.fswsp ft6, 26*4 \n\ + c.fswsp ft7, 27*4 \n\ + c.fswsp fa0, 28*4 \n\ + c.fswsp fa1, 29*4 \n\ + c.fswsp fa2, 30*4 \n\ + c.fswsp fa3, 31*4 \n\ + c.fswsp fa4, 32*4 \n\ + c.fswsp fa5, 33*4 \n\ + c.fswsp fa6, 34*4 \n\ + c.fswsp fa7, 35*4 \n\ + c.fswsp ft8, 36*4 \n\ + c.fswsp ft9, 37*4 \n\ + c.fswsp ft10, 38*4 \n\ + c.fswsp ft11, 39*4 \n");\ +} + +/* + * Restore FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack + */ +#define RESTORE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.flwsp ft0, 20*4\n\ + c.flwsp ft1, 21*4 \n\ + c.flwsp ft2, 22*4 \n\ + c.flwsp ft3, 23*4 \n\ + c.flwsp ft4, 24*4 \n\ + c.flwsp ft5, 25*4 \n\ + c.flwsp ft6, 26*4 \n\ + c.flwsp ft7, 27*4 \n\ + c.flwsp fa0, 28*4 \n\ + c.flwsp fa1, 29*4 \n\ + c.flwsp fa2, 30*4 \n\ + c.flwsp fa3, 31*4 \n\ + c.flwsp fa4, 32*4 \n\ + c.flwsp fa5, 33*4 \n\ + c.flwsp fa6, 34*4 \n\ + c.flwsp fa7, 35*4 \n\ + c.flwsp ft8, 36*4 \n\ + c.flwsp ft9, 37*4 \n\ + c.flwsp ft10, 38*4 \n\ + c.flwsp ft11, 39*4 \n");\ +} +#else /* __ICCRISCV__ not defined */ #define SAVE_FPU_CONTEXT() { \ __asm volatile("\n\ c.fswsp ft0, 20*4(sp)\n\ @@ -615,6 +668,60 @@ ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) c.flwsp ft10, 38*4(sp) \n\ c.flwsp ft11, 39*4(sp) \n");\ } +#endif +#else /*__riscv_flen == 64*/ +#ifdef __ICCRISCV__ +#define SAVE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fsdsp ft0, 20*4\n\ + c.fsdsp ft1, 22*4 \n\ + c.fsdsp ft2, 24*4 \n\ + c.fsdsp ft3, 26*4 \n\ + c.fsdsp ft4, 28*4 \n\ + c.fsdsp ft5, 30*4 \n\ + c.fsdsp ft6, 32*4 \n\ + c.fsdsp ft7, 34*4 \n\ + c.fsdsp fa0, 36*4 \n\ + c.fsdsp fa1, 38*4 \n\ + c.fsdsp fa2, 40*4 \n\ + c.fsdsp fa3, 42*4 \n\ + c.fsdsp fa4, 44*4 \n\ + c.fsdsp fa5, 46*4 \n\ + c.fsdsp fa6, 48*4 \n\ + c.fsdsp fa7, 50*4 \n\ + c.fsdsp ft8, 52*4 \n\ + c.fsdsp ft9, 54*4 \n\ + c.fsdsp ft10, 56*4 \n\ + c.fsdsp ft11, 58*4 \n");\ +} + +/* + * Restore FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack + */ +#define RESTORE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fldsp ft0, 20*4\n\ + c.fldsp ft1, 22*4 \n\ + c.fldsp ft2, 24*4 \n\ + c.fldsp ft3, 26*4 \n\ + c.fldsp ft4, 28*4 \n\ + c.fldsp ft5, 30*4 \n\ + c.fldsp ft6, 32*4 \n\ + c.fldsp ft7, 34*4 \n\ + c.fldsp fa0, 36*4 \n\ + c.fldsp fa1, 38*4 \n\ + c.fldsp fa2, 40*4 \n\ + c.fldsp fa3, 42*4 \n\ + c.fldsp fa4, 44*4 \n\ + c.fldsp fa5, 46*4 \n\ + c.fldsp fa6, 48*4 \n\ + c.fldsp fa7, 50*4 \n\ + c.fldsp ft8, 52*4 \n\ + c.fldsp ft9, 54*4 \n\ + c.fldsp ft10, 56*4 \n\ + c.fldsp ft11, 58*4 \n");\ +} #else /*__riscv_flen == 64*/ #define SAVE_FPU_CONTEXT() { \ __asm volatile("\n\ @@ -668,11 +775,71 @@ ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) c.fldsp ft11, 58*4(sp) \n");\ } #endif +#endif #else #define SAVE_FPU_CONTEXT() #define RESTORE_FPU_CONTEXT() #endif +#ifdef __ICCRISCV__ +/** + * @brief Save the caller registers based on the RISC-V ABI specification + */ +#define SAVE_CALLER_CONTEXT() { \ + __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\ + __asm volatile("\n\ + c.swsp ra, 0*4 \n\ + c.swsp t0, 1*4 \n\ + c.swsp t1, 2*4 \n\ + c.swsp t2, 3*4 \n\ + c.swsp s0, 4*4 \n\ + c.swsp s1, 5*4 \n\ + c.swsp a0, 6*4 \n\ + c.swsp a1, 7*4 \n\ + c.swsp a2, 8*4 \n\ + c.swsp a3, 9*4 \n\ + c.swsp a4, 10*4 \n\ + c.swsp a5, 11*4 \n\ + c.swsp a6, 12*4 \n\ + c.swsp a7, 13*4 \n\ + c.swsp s2, 14*4 \n\ + c.swsp s3, 15*4 \n\ + c.swsp t3, 16*4 \n\ + c.swsp t4, 17*4 \n\ + c.swsp t5, 18*4 \n\ + c.swsp t6, 19*4"); \ + SAVE_FPU_CONTEXT(); \ +} + +/** + * @brief Restore the caller registers based on the RISC-V ABI specification + */ +#define RESTORE_CALLER_CONTEXT() { \ + __asm volatile("\n\ + c.lwsp ra, 0*4 \n\ + c.lwsp t0, 1*4 \n\ + c.lwsp t1, 2*4 \n\ + c.lwsp t2, 3*4 \n\ + c.lwsp s0, 4*4 \n\ + c.lwsp s1, 5*4 \n\ + c.lwsp a0, 6*4 \n\ + c.lwsp a1, 7*4 \n\ + c.lwsp a2, 8*4 \n\ + c.lwsp a3, 9*4 \n\ + c.lwsp a4, 10*4 \n\ + c.lwsp a5, 11*4 \n\ + c.lwsp a6, 12*4 \n\ + c.lwsp a7, 13*4 \n\ + c.lwsp s2, 14*4 \n\ + c.lwsp s3, 15*4 \n\ + c.lwsp t3, 16*4 \n\ + c.lwsp t4, 17*4 \n\ + c.lwsp t5, 18*4 \n\ + c.lwsp t6, 19*4 \n");\ + RESTORE_FPU_CONTEXT(); \ + __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\ +} +#else /** * @brief Save the caller registers based on the RISC-V ABI specification */ @@ -730,14 +897,15 @@ ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) RESTORE_FPU_CONTEXT(); \ __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\ } +#endif #ifdef __riscv_flen #define SAVE_FPU_STATE() { \ - __asm volatile("frsr s1\n"); \ + __asm volatile("frcsr s1\n"); \ } #define RESTORE_FPU_STATE() { \ - __asm volatile("fssr s1\n"); \ + __asm volatile("fscsr s1\n"); \ } #else #define SAVE_FPU_STATE() @@ -750,14 +918,14 @@ ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) * NOTE: DSP context registers are stored at word offset 41 in the stack */ #define SAVE_DSP_CONTEXT() { \ - __asm volatile("rdov s0\n"); \ + __asm volatile("csrrs s0, %0, x0\n" ::"i"(CSR_UCODE):); \ } /* * @brief Restore DSP context * @note DSP context registers are stored at word offset 41 in the stack */ #define RESTORE_DSP_CONTEXT() {\ - __asm volatile("csrw ucode, s0\n"); \ + __asm volatile("csrw %0, s0\n" ::"i"(CSR_UCODE):); \ } #else @@ -779,25 +947,17 @@ ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) csrr s3, mstatus \n");\ SAVE_FPU_STATE(); \ SAVE_DSP_CONTEXT(); \ - __asm volatile ("\n\ - c.li a5, 8\n\ - csrs mstatus, a5\n"); \ + __asm volatile("csrsi mstatus, 8"); \ } /* * @brief Complete IRQ Handling */ #define COMPLETE_IRQ_HANDLING_M(irq_num) { \ - __asm volatile("\n\ - lui a5, 0x1\n\ - addi a5, a5, -2048\n\ - csrc mie, a5\n"); \ - __asm volatile("\n\ - lui a4, 0xe4200\n");\ + __asm volatile("csrci mstatus, 8"); \ + __asm volatile("lui a4, 0xe4200"); \ __asm volatile("li a3, %0" : : "i" (irq_num) :); \ - __asm volatile("sw a3, 4(a4)\n\ - fence io, io\n"); \ - __asm volatile("csrs mie, a5"); \ + __asm volatile("sw a3, 4(a4)"); \ } /* @@ -823,24 +983,15 @@ ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) csrr s3, sstatus \n");\ SAVE_FPU_STATE(); \ SAVE_DSP_CONTEXT(); \ - __asm volatile ("\n\ - c.li a5, 8\n\ - csrs sstatus, a5\n"); \ + __asm volatile("csrsi sstatus, 2"); \ } #define COMPLETE_IRQ_HANDLING_S(irq_num) {\ - __asm volatile("\n\ - lui a5, 0x1\n\ - addi a5, a5, -2048\n\ - csrc sie, a5\n"); \ - __asm volatile("\n\ - lui a4, 0xe4201\n");\ + __asm volatile("csrci sstatus, 2"); \ + __asm volatile("lui a4, 0xe4201"); \ __asm volatile("li a3, %0" : : "i" (irq_num) :); \ - __asm volatile("sw a3, 4(a4)\n\ - fence io, io\n"); \ - __asm volatile("csrs sie, a5"); \ + __asm volatile("sw a3, 4(a4)"); \ } - /* * @brief Exit Nested IRQ Handling at supervisor mode * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: @@ -873,18 +1024,6 @@ ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) RESTORE_FCSR() \ RESTORE_UCODE() -/* - * @brief Nested IRQ exit macro : Restore CSRs - * @param[in] irq Target interrupt number - */ -#define NESTED_VPLIC_COMPLETE_INTERRUPT(irq) \ -do { \ - clear_csr(CSR_MIE, CSR_MIP_MEIP_MASK); \ - __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq); \ - __asm volatile("fence io, io"); \ - set_csr(CSR_MIE, CSR_MIP_MEIP_MASK); \ -} while (0) - #ifdef __cplusplus #define EXTERN_C extern "C" #else @@ -913,6 +1052,7 @@ void ISR_NAME_M(irq_num)(void) \ COMPLETE_IRQ_HANDLING_M(irq_num);\ EXIT_NESTED_IRQ_HANDLING_M();\ RESTORE_CALLER_CONTEXT();\ + __asm volatile("fence io, io");\ __asm volatile("mret\n");\ } @@ -933,6 +1073,7 @@ void ISR_NAME_S(irq_num)(void) {\ COMPLETE_IRQ_HANDLING_S(irq_num);\ EXIT_NESTED_IRQ_HANDLING_S();\ RESTORE_CALLER_CONTEXT();\ + __asm volatile("fence io, io");\ __asm volatile("sret\n");\ } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ioc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ioc_regs.h index cf272e6f794..7bac3840655 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ioc_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ioc_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_iomux.h index 223f5145c09..8b8ab423802 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_iomux.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_iomux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -13,7 +13,7 @@ #define IOC_PA00_FUNC_CTL_GPIO_A_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PA00_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PA00_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA00_FUNC_CTL_CAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA00_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PA00_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PA00_FUNC_CTL_SDM0_CLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) @@ -21,7 +21,7 @@ #define IOC_PA01_FUNC_CTL_GPIO_A_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PA01_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PA01_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA01_FUNC_CTL_CAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA01_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PA01_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PA01_FUNC_CTL_SDM0_DAT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) @@ -29,7 +29,7 @@ #define IOC_PA02_FUNC_CTL_GPIO_A_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PA02_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PA02_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA02_FUNC_CTL_CAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA02_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PA02_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PA02_FUNC_CTL_SDM0_CLK_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) @@ -37,7 +37,7 @@ #define IOC_PA03_FUNC_CTL_GPIO_A_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PA03_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PA03_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA03_FUNC_CTL_CAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA03_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PA03_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PA03_FUNC_CTL_SDM0_DAT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) @@ -46,7 +46,7 @@ #define IOC_PA04_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PA04_FUNC_CTL_SPI3_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PA04_FUNC_CTL_LIN3_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA04_FUNC_CTL_CAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA04_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PA04_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PA04_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PA04_FUNC_CTL_SDM0_CLK_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) @@ -56,7 +56,7 @@ #define IOC_PA05_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PA05_FUNC_CTL_SPI3_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PA05_FUNC_CTL_LIN2_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA05_FUNC_CTL_CAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA05_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PA05_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PA05_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PA05_FUNC_CTL_SDM0_DAT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) @@ -92,7 +92,7 @@ #define IOC_PA08_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PA08_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PA08_FUNC_CTL_LIN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA08_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA08_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PA08_FUNC_CTL_XPI0_CB_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) /* IOC_PA09_FUNC_CTL function mux definitions */ @@ -102,7 +102,7 @@ #define IOC_PA09_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PA09_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PA09_FUNC_CTL_LIN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA09_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA09_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PA09_FUNC_CTL_XPI0_CB_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) /* IOC_PA10_FUNC_CTL function mux definitions */ @@ -112,7 +112,7 @@ #define IOC_PA10_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PA10_FUNC_CTL_SPI0_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PA10_FUNC_CTL_LIN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA10_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA10_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PA10_FUNC_CTL_XPI0_CB_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PA10_FUNC_CTL_PWM3_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) @@ -122,7 +122,7 @@ #define IOC_PA11_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PA11_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PA11_FUNC_CTL_LIN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA11_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA11_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PA11_FUNC_CTL_XPI0_CB_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PA11_FUNC_CTL_PWM3_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) @@ -143,7 +143,7 @@ #define IOC_PA13_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PA13_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PA13_FUNC_CTL_LIN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA13_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA13_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PA13_FUNC_CTL_XPI0_CB_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PA13_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PA13_FUNC_CTL_TRGM3_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) @@ -154,7 +154,7 @@ #define IOC_PA14_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PA14_FUNC_CTL_SPI0_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PA14_FUNC_CTL_LIN1_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA14_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA14_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PA14_FUNC_CTL_XPI0_CB_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PA14_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PA14_FUNC_CTL_TRGM3_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) @@ -165,7 +165,7 @@ #define IOC_PA15_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PA15_FUNC_CTL_SPI0_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PA15_FUNC_CTL_LIN0_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA15_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA15_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PA15_FUNC_CTL_XPI0_CB_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PA15_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PA15_FUNC_CTL_TRGM3_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) @@ -175,7 +175,7 @@ #define IOC_PA16_FUNC_CTL_GPIO_A_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PA16_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PA16_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA16_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA16_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PA16_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PA16_FUNC_CTL_TRGM3_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PA16_FUNC_CTL_SYSCTL_CLK_OBS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) @@ -184,7 +184,7 @@ #define IOC_PA17_FUNC_CTL_GPIO_A_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PA17_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PA17_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA17_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA17_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PA17_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PA17_FUNC_CTL_TRGM3_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PA17_FUNC_CTL_SYSCTL_CLK_OBS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) @@ -193,7 +193,7 @@ #define IOC_PA18_FUNC_CTL_GPIO_A_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PA18_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PA18_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA18_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA18_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PA18_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PA18_FUNC_CTL_TRGM3_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PA18_FUNC_CTL_SYSCTL_CLK_OBS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) @@ -222,7 +222,7 @@ #define IOC_PA21_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PA21_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PA21_FUNC_CTL_LIN2_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA21_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA21_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PA21_FUNC_CTL_TRGM1_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PA21_FUNC_CTL_PWM3_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) @@ -233,7 +233,7 @@ #define IOC_PA22_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PA22_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PA22_FUNC_CTL_LIN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA22_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA22_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PA22_FUNC_CTL_TRGM1_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PA22_FUNC_CTL_PWM3_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) @@ -243,7 +243,7 @@ #define IOC_PA23_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PA23_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PA23_FUNC_CTL_LIN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA23_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA23_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PA23_FUNC_CTL_TRGM1_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PA23_FUNC_CTL_PWM3_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) @@ -254,7 +254,7 @@ #define IOC_PA24_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PA24_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PA24_FUNC_CTL_LIN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA24_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA24_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PA24_FUNC_CTL_TRGM1_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PA24_FUNC_CTL_PWM3_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) @@ -264,7 +264,7 @@ #define IOC_PA25_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PA25_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PA25_FUNC_CTL_LIN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA25_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA25_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PA25_FUNC_CTL_TRGM1_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PA25_FUNC_CTL_PWM3_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) @@ -275,7 +275,7 @@ #define IOC_PA26_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PA26_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PA26_FUNC_CTL_LIN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA26_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA26_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PA26_FUNC_CTL_TRGM1_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PA26_FUNC_CTL_PWM3_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) @@ -300,7 +300,7 @@ #define IOC_PA29_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PA29_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PA29_FUNC_CTL_LIN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA29_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA29_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PA29_FUNC_CTL_TRGM1_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PA29_FUNC_CTL_TRGM3_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) @@ -309,7 +309,7 @@ #define IOC_PA30_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PA30_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PA30_FUNC_CTL_LIN1_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA30_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA30_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PA30_FUNC_CTL_TRGM1_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PA30_FUNC_CTL_TRGM3_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) @@ -318,7 +318,7 @@ #define IOC_PA31_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PA31_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PA31_FUNC_CTL_LIN0_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA31_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA31_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PA31_FUNC_CTL_TRGM1_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PA31_FUNC_CTL_TRGM3_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) @@ -326,7 +326,7 @@ #define IOC_PB00_FUNC_CTL_GPIO_B_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB00_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB00_FUNC_CTL_SPI0_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB00_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB00_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PB00_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PB00_FUNC_CTL_TRGM3_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) @@ -355,7 +355,7 @@ #define IOC_PB04_FUNC_CTL_GPIO_B_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB04_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB04_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB04_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB04_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PB04_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PB04_FUNC_CTL_TRGM3_P_8 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) @@ -363,14 +363,14 @@ #define IOC_PB05_FUNC_CTL_GPIO_B_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB05_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB05_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB05_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB05_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PB05_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PB05_FUNC_CTL_TRGM3_P_9 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) /* IOC_PB06_FUNC_CTL function mux definitions */ #define IOC_PB06_FUNC_CTL_GPIO_B_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB06_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB06_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB06_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PB06_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PB06_FUNC_CTL_TRGM3_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) @@ -378,7 +378,7 @@ #define IOC_PB07_FUNC_CTL_GPIO_B_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB07_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB07_FUNC_CTL_SPI1_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB07_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB07_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PB07_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PB07_FUNC_CTL_TRGM3_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) @@ -386,14 +386,14 @@ #define IOC_PB08_FUNC_CTL_GPIO_B_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB08_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB08_FUNC_CTL_SPI1_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB08_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB08_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PB08_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) /* IOC_PB09_FUNC_CTL function mux definitions */ #define IOC_PB09_FUNC_CTL_GPIO_B_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB09_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB09_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB09_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB09_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PB09_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) /* IOC_PB10_FUNC_CTL function mux definitions */ @@ -413,7 +413,7 @@ #define IOC_PB12_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB12_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PB12_FUNC_CTL_LIN3_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PB12_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB12_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PB12_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PB12_FUNC_CTL_TRGM2_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) @@ -422,7 +422,7 @@ #define IOC_PB13_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB13_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PB13_FUNC_CTL_LIN2_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PB13_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB13_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PB13_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PB13_FUNC_CTL_TRGM2_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) @@ -432,7 +432,7 @@ #define IOC_PB14_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PB14_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PB14_FUNC_CTL_LIN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PB14_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB14_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PB14_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PB14_FUNC_CTL_TRGM2_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) @@ -441,7 +441,7 @@ #define IOC_PB15_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PB15_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PB15_FUNC_CTL_LIN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PB15_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB15_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PB15_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PB15_FUNC_CTL_TRGM2_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) @@ -468,7 +468,7 @@ #define IOC_PB18_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PB18_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PB18_FUNC_CTL_LIN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PB18_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB18_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PB18_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PB18_FUNC_CTL_TRGM2_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) @@ -478,7 +478,7 @@ #define IOC_PB19_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PB19_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PB19_FUNC_CTL_LIN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PB19_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB19_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PB19_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PB19_FUNC_CTL_TRGM2_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) @@ -489,7 +489,7 @@ #define IOC_PB20_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PB20_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PB20_FUNC_CTL_LIN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PB20_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB20_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PB20_FUNC_CTL_TRGM0_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PB20_FUNC_CTL_TRGM2_P_8 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) @@ -499,7 +499,7 @@ #define IOC_PB21_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PB21_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PB21_FUNC_CTL_LIN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PB21_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB21_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PB21_FUNC_CTL_TRGM0_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PB21_FUNC_CTL_TRGM2_P_9 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) @@ -509,7 +509,7 @@ #define IOC_PB22_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB22_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PB22_FUNC_CTL_LIN1_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PB22_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB22_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PB22_FUNC_CTL_TRGM0_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PB22_FUNC_CTL_TRGM2_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PB22_FUNC_CTL_SDM0_CLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) @@ -521,7 +521,7 @@ #define IOC_PB23_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB23_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PB23_FUNC_CTL_LIN0_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PB23_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB23_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PB23_FUNC_CTL_TRGM0_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PB23_FUNC_CTL_TRGM2_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PB23_FUNC_CTL_SDM0_DAT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) @@ -574,7 +574,7 @@ #define IOC_PB29_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB29_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PB29_FUNC_CTL_LIN2_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PB29_FUNC_CTL_CAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB29_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PB29_FUNC_CTL_TRGM0_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PB29_FUNC_CTL_PWM2_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PB29_FUNC_CTL_SDM0_DAT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) @@ -585,7 +585,7 @@ #define IOC_PB30_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PB30_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PB30_FUNC_CTL_LIN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PB30_FUNC_CTL_CAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB30_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PB30_FUNC_CTL_TRGM0_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PB30_FUNC_CTL_PWM2_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) @@ -594,7 +594,7 @@ #define IOC_PB31_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PB31_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PB31_FUNC_CTL_LIN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PB31_FUNC_CTL_CAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB31_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PB31_FUNC_CTL_TRGM0_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PB31_FUNC_CTL_PWM2_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) @@ -604,7 +604,7 @@ #define IOC_PC00_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PC00_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PC00_FUNC_CTL_LIN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PC00_FUNC_CTL_CAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC00_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PC00_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PC00_FUNC_CTL_TRGM2_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PC00_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) @@ -614,7 +614,7 @@ #define IOC_PC01_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PC01_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PC01_FUNC_CTL_LIN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PC01_FUNC_CTL_CAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC01_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PC01_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PC01_FUNC_CTL_TRGM2_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PC01_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) @@ -625,7 +625,7 @@ #define IOC_PC02_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PC02_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PC02_FUNC_CTL_LIN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PC02_FUNC_CTL_CAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC02_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PC02_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PC02_FUNC_CTL_TRGM2_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PC02_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) @@ -689,7 +689,7 @@ #define IOC_PC09_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) #define IOC_PC09_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PC09_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC09_FUNC_CTL_CAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC09_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PC09_FUNC_CTL_PWM2_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) /* IOC_PC10_FUNC_CTL function mux definitions */ @@ -697,14 +697,14 @@ #define IOC_PC10_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) #define IOC_PC10_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PC10_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC10_FUNC_CTL_CAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC10_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) /* IOC_PC11_FUNC_CTL function mux definitions */ #define IOC_PC11_FUNC_CTL_GPIO_C_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC11_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) #define IOC_PC11_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PC11_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC11_FUNC_CTL_CAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC11_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) /* IOC_PC12_FUNC_CTL function mux definitions */ #define IOC_PC12_FUNC_CTL_GPIO_C_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -712,7 +712,7 @@ #define IOC_PC12_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PC12_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PC12_FUNC_CTL_LIN3_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PC12_FUNC_CTL_CAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC12_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) /* IOC_PC13_FUNC_CTL function mux definitions */ #define IOC_PC13_FUNC_CTL_GPIO_C_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -720,7 +720,7 @@ #define IOC_PC13_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PC13_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PC13_FUNC_CTL_LIN2_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PC13_FUNC_CTL_CAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC13_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PC13_FUNC_CTL_ACMP_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) /* IOC_PC14_FUNC_CTL function mux definitions */ @@ -729,7 +729,7 @@ #define IOC_PC14_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PC14_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PC14_FUNC_CTL_LIN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PC14_FUNC_CTL_CAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PC14_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) /* IOC_PC15_FUNC_CTL function mux definitions */ @@ -858,14 +858,14 @@ #define IOC_PY00_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PY00_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PY00_FUNC_CTL_LIN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PY00_FUNC_CTL_CAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY00_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) /* IOC_PY01_FUNC_CTL function mux definitions */ #define IOC_PY01_FUNC_CTL_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PY01_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PY01_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PY01_FUNC_CTL_LIN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PY01_FUNC_CTL_CAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY01_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) /* IOC_PY02_FUNC_CTL function mux definitions */ #define IOC_PY02_FUNC_CTL_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -885,7 +885,7 @@ #define IOC_PY04_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PY04_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PY04_FUNC_CTL_LIN0_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PY04_FUNC_CTL_CAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY04_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PY04_FUNC_CTL_WDG0_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) /* IOC_PY05_FUNC_CTL function mux definitions */ @@ -893,7 +893,7 @@ #define IOC_PY05_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PY05_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PY05_FUNC_CTL_LIN1_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PY05_FUNC_CTL_CAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY05_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PY05_FUNC_CTL_WDG1_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) /* IOC_PY06_FUNC_CTL function mux definitions */ @@ -911,36 +911,36 @@ /* IOC_PZ00_FUNC_CTL function mux definitions */ #define IOC_PZ00_FUNC_CTL_GPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PZ00_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ00_FUNC_CTL_CAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PZ00_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) /* IOC_PZ01_FUNC_CTL function mux definitions */ #define IOC_PZ01_FUNC_CTL_GPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PZ01_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ01_FUNC_CTL_CAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PZ01_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) /* IOC_PZ02_FUNC_CTL function mux definitions */ #define IOC_PZ02_FUNC_CTL_GPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PZ02_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PZ02_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PZ02_FUNC_CTL_CAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PZ02_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) /* IOC_PZ03_FUNC_CTL function mux definitions */ #define IOC_PZ03_FUNC_CTL_GPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PZ03_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PZ03_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PZ03_FUNC_CTL_CAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PZ03_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) /* IOC_PZ04_FUNC_CTL function mux definitions */ #define IOC_PZ04_FUNC_CTL_GPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PZ04_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PZ04_FUNC_CTL_LIN3_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PZ04_FUNC_CTL_CAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PZ04_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) /* IOC_PZ05_FUNC_CTL function mux definitions */ #define IOC_PZ05_FUNC_CTL_GPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PZ05_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PZ05_FUNC_CTL_LIN2_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PZ05_FUNC_CTL_CAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PZ05_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) /* IOC_PZ06_FUNC_CTL function mux definitions */ #define IOC_PZ06_FUNC_CTL_GPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_l1c_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_l1c_drv.h index e328193a072..1f1a21639a2 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_l1c_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_l1c_drv.h @@ -7,8 +7,8 @@ #ifndef _HPM_L1_CACHE_H #define _HPM_L1_CACHE_H -#include "riscv/riscv_core.h" #include "hpm_common.h" +#include "hpm_csr_drv.h" #include "hpm_soc.h" /** diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_mcan_soc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_mcan_soc.h index db03cea0ae7..09d88371a74 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_mcan_soc.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_mcan_soc.h @@ -19,8 +19,8 @@ #define MCAN_TSU_EXT_TIMEBASE_SRC_MCAN1 (1U) #define MCAN_TSU_EXT_TIMEBASE_SRC_MCAN2 (2U) #define MCAN_TSU_EXT_TIMEBASE_SRC_MCAN3 (3U) -#define MCAN_TSU_EXT_TIMEBASE_SRC_PTP (4U) -#define MCAN_TSU_EXT_TIMEBASE_SRC_MAX (MCAN_TSU_EXT_TIMEBASE_SRC_PTP) +#define MCAN_TSU_EXT_TIMEBASE_SRC_PTPC (4U) +#define MCAN_TSU_EXT_TIMEBASE_SRC_MAX (MCAN_TSU_EXT_TIMEBASE_SRC_PTPC) #ifdef __cpluspus extern "C" { @@ -71,6 +71,7 @@ static inline uint32_t mcan_get_ram_base(MCAN_Type *ptr) */ static inline uint32_t mcan_get_ram_offset(MCAN_Type *ptr) { + (void) ptr; return 0U; } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_misc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_misc.h index 9875958d954..802c37691b3 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_misc.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_misc.h @@ -27,12 +27,14 @@ /* map core local memory(DLM/ILM) to system address */ static inline uint32_t core_local_mem_to_sys_address(uint8_t core_id, uint32_t addr) { + (void) core_id; return addr; } /* map system address to core local memory(DLM/ILM) */ static inline uint32_t sys_address_to_core_local_mem(uint8_t core_id, uint32_t addr) { + (void) core_id; return addr; } #endif /* HPM_MISC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_otp_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_otp_drv.h index 8c9559a9861..b61c805a1df 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_otp_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_otp_drv.h @@ -118,7 +118,7 @@ hpm_stat_t otp_set_configurable_region(uint32_t start, uint32_t num_of_words); /** * @return Write data to OTP shadow register * @param [in] addr OTP word index - * @param [val] val Data to be written + * @param [in] val Data to be written * @return API execution status */ hpm_stat_t otp_write_shadow_register(uint32_t addr, uint32_t val); diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_pcfg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_pcfg_drv.h index e99e0837a59..c5f8de4b942 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_pcfg_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_pcfg_drv.h @@ -20,11 +20,9 @@ */ #define PCFG_CLOCK_GATE_MODE_ALWAYS_ON (0x3UL) #define PCFG_CLOCK_GATE_MODE_ALWAYS_OFF (0x2UL) -#define PCFG_CLOCK_GATE_MODE_ALWAYS_FOLLOW_FLOW (0x1UL) #define PCFG_PERIPH_KEEP_CLOCK_ON(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_ON << (p)) #define PCFG_PERIPH_KEEP_CLOCK_OFF(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_OFF << (p)) -#define PCFG_PERIPH_SET_CLOCK_AUTO(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_FOLLOW_FLOW << (p)) /* @brief PCFG irc24m reference */ typedef enum { @@ -153,26 +151,6 @@ static inline void pcfg_bandgap_reload_trim(PCFG_Type *ptr) ptr->BANDGAP &= ~PCFG_BANDGAP_VBG_TRIMMED_MASK; } -/** - * @brief turn off LDO 1V - * - * @param[in] ptr base address - */ -static inline void pcfg_ldo1p1_turn_off(PCFG_Type *ptr) -{ - ptr->LDO1P1 &= ~PCFG_LDO1P1_ENABLE_MASK; -} - -/** - * @brief turn of LDO 1V - * - * @param[in] ptr base address - */ -static inline void pcfg_ldo1p1_turn_on(PCFG_Type *ptr) -{ - ptr->LDO1P1 |= PCFG_LDO1P1_ENABLE_MASK; -} - /** * @brief turn off LDO2P5 * @@ -229,12 +207,12 @@ static inline void pcfg_dcdc_set_mode(PCFG_Type *ptr, uint8_t mode) * * @param[in] ptr base address * @param[in] limit current limit at low power mode - * @param[in] over_limit set to true means current is greater than limit + * @param[in] over_limit unused parameter, will be discarded */ static inline void pcfg_dcdc_set_lp_current_limit(PCFG_Type *ptr, pcfg_dcdc_lp_current_limit_t limit, bool over_limit) { - ptr->DCDC_PROT = (ptr->DCDC_PROT & ~(PCFG_DCDC_PROT_ILIMIT_LP_MASK | PCFG_DCDC_PROT_OVERLOAD_LP_MASK)) - | PCFG_DCDC_PROT_ILIMIT_LP_SET(limit) | PCFG_DCDC_PROT_OVERLOAD_LP_SET(over_limit); + (void) over_limit; + ptr->DCDC_PROT = (ptr->DCDC_PROT & ~PCFG_DCDC_PROT_ILIMIT_LP_MASK) | PCFG_DCDC_PROT_ILIMIT_LP_SET(limit); } /** diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_pcfg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_pcfg_regs.h index b454667b375..55bc385a454 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_pcfg_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_pcfg_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -106,18 +106,6 @@ typedef struct { #define PCFG_BANDGAP_VBG_P50_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_P50_TRIM_MASK) >> PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) /* Bitfield definition for register: LDO1P1 */ -/* - * ENABLE (RW) - * - * LDO enable - * 0: turn off LDO - * 1: turn on LDO - */ -#define PCFG_LDO1P1_ENABLE_MASK (0x10000UL) -#define PCFG_LDO1P1_ENABLE_SHIFT (16U) -#define PCFG_LDO1P1_ENABLE_SET(x) (((uint32_t)(x) << PCFG_LDO1P1_ENABLE_SHIFT) & PCFG_LDO1P1_ENABLE_MASK) -#define PCFG_LDO1P1_ENABLE_GET(x) (((uint32_t)(x) & PCFG_LDO1P1_ENABLE_MASK) >> PCFG_LDO1P1_ENABLE_SHIFT) - /* * VOLT (RW) * @@ -186,7 +174,7 @@ typedef struct { * MODE (RW) * * DCDC work mode - * XX0: trun off + * XX0: turn off * 001: basic mode * 011: generic mode * 101: automatic mode @@ -240,7 +228,7 @@ typedef struct { #define PCFG_DCDC_PROT_ILIMIT_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) >> PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) /* - * OVERLOAD_LP (RW) + * OVERLOAD_LP (RO) * * over current in low power mode * 0: current is below setting @@ -248,7 +236,6 @@ typedef struct { */ #define PCFG_DCDC_PROT_OVERLOAD_LP_MASK (0x1000000UL) #define PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT (24U) -#define PCFG_DCDC_PROT_OVERLOAD_LP_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT) & PCFG_DCDC_PROT_OVERLOAD_LP_MASK) #define PCFG_DCDC_PROT_OVERLOAD_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERLOAD_LP_MASK) >> PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT) /* @@ -277,7 +264,7 @@ typedef struct { /* * DISABLE_OVERVOLTAGE (RW) * - * ouput over voltage protection + * output over voltage protection * 0: protection enabled, DCDC will shut down is output voltage is unexpected high * 1: protection disabled, DCDC continue to adjust output voltage */ @@ -301,7 +288,7 @@ typedef struct { * DISABLE_SHORT (RW) * * disable output short circuit protection - * 0: short circuits protection enabled, DCDC shut down if short circuit on ouput detected + * 0: short circuits protection enabled, DCDC shut down if short circuit on output detected * 1: short circuit protection disabled */ #define PCFG_DCDC_PROT_DISABLE_SHORT_MASK (0x80U) @@ -418,18 +405,6 @@ typedef struct { #define PCFG_DCDC_ADVMODE_EN_FF_LOOP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) #define PCFG_DCDC_ADVMODE_EN_FF_LOOP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) >> PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) -/* - * EN_AUTOLP (RW) - * - * enable auto enter low power mode - * 0: do not enter low power mode - * 1: enter low power mode if current is detected low - */ -#define PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK (0x10U) -#define PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT (4U) -#define PCFG_DCDC_ADVMODE_EN_AUTOLP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT) & PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK) -#define PCFG_DCDC_ADVMODE_EN_AUTOLP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK) >> PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT) - /* * EN_DCM_EXIT (RW) * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_pgpr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_pgpr_regs.h index 0369149bdd6..acf20cfecd5 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_pgpr_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_pgpr_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_pmic_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_pmic_iomux.h index b611842ecb5..48bcf5ee53a 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_pmic_iomux.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_pmic_iomux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -9,53 +9,85 @@ #ifndef HPM_PMIC_IOMUX_H #define HPM_PMIC_IOMUX_H -/* IOC_PY00_FUNC_CTL function mux definitions */ -#define IOC_PY00_FUNC_CTL_PGPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY00_FUNC_CTL_JTAG_TDO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY00_FUNC_CTL_SOC_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PY01_FUNC_CTL function mux definitions */ -#define IOC_PY01_FUNC_CTL_PGPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY01_FUNC_CTL_JTAG_TDI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY01_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY01_FUNC_CTL_SOC_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PY02_FUNC_CTL function mux definitions */ -#define IOC_PY02_FUNC_CTL_PGPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY02_FUNC_CTL_JTAG_TCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY02_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY02_FUNC_CTL_SOC_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PY03_FUNC_CTL function mux definitions */ -#define IOC_PY03_FUNC_CTL_PGPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY03_FUNC_CTL_JTAG_TMS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY03_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY03_FUNC_CTL_SOC_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PY04_FUNC_CTL function mux definitions */ -#define IOC_PY04_FUNC_CTL_PGPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY04_FUNC_CTL_JTAG_TRST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY04_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY04_FUNC_CTL_SOC_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PY05_FUNC_CTL function mux definitions */ -#define IOC_PY05_FUNC_CTL_PGPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY05_FUNC_CTL_WDOG_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY05_FUNC_CTL_PTMR_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY05_FUNC_CTL_SOC_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PY06_FUNC_CTL function mux definitions */ -#define IOC_PY06_FUNC_CTL_PGPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY06_FUNC_CTL_UART_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY06_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY06_FUNC_CTL_SOC_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PY07_FUNC_CTL function mux definitions */ -#define IOC_PY07_FUNC_CTL_PGPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY07_FUNC_CTL_UART_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY07_FUNC_CTL_PTMR_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY07_FUNC_CTL_SOC_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +/* PIOC_PY00_FUNC_CTL function mux definitions */ +#define IOC_PY00_FUNC_CTL_PGPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY00_FUNC_CTL_PGPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY00_FUNC_CTL_JTAG_TDO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY00_FUNC_CTL_JTAG_TDO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY00_FUNC_CTL_SOC_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY00_FUNC_CTL_SOC_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY01_FUNC_CTL function mux definitions */ +#define IOC_PY01_FUNC_CTL_PGPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY01_FUNC_CTL_PGPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY01_FUNC_CTL_JTAG_TDI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY01_FUNC_CTL_JTAG_TDI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY01_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY01_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY01_FUNC_CTL_SOC_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY01_FUNC_CTL_SOC_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY02_FUNC_CTL function mux definitions */ +#define IOC_PY02_FUNC_CTL_PGPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY02_FUNC_CTL_PGPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY02_FUNC_CTL_JTAG_TCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY02_FUNC_CTL_JTAG_TCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY02_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY02_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY02_FUNC_CTL_SOC_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY02_FUNC_CTL_SOC_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY03_FUNC_CTL function mux definitions */ +#define IOC_PY03_FUNC_CTL_PGPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY03_FUNC_CTL_PGPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY03_FUNC_CTL_JTAG_TMS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY03_FUNC_CTL_JTAG_TMS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY03_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY03_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY03_FUNC_CTL_SOC_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY03_FUNC_CTL_SOC_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY04_FUNC_CTL function mux definitions */ +#define IOC_PY04_FUNC_CTL_PGPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY04_FUNC_CTL_PGPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY04_FUNC_CTL_JTAG_TRST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY04_FUNC_CTL_JTAG_TRST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY04_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY04_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY04_FUNC_CTL_SOC_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY04_FUNC_CTL_SOC_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY05_FUNC_CTL function mux definitions */ +#define IOC_PY05_FUNC_CTL_PGPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY05_FUNC_CTL_PGPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY05_FUNC_CTL_WDOG_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY05_FUNC_CTL_WDOG_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY05_FUNC_CTL_PTMR_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY05_FUNC_CTL_PTMR_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY05_FUNC_CTL_SOC_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY05_FUNC_CTL_SOC_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY06_FUNC_CTL function mux definitions */ +#define IOC_PY06_FUNC_CTL_PGPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY06_FUNC_CTL_PGPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY06_FUNC_CTL_UART_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY06_FUNC_CTL_UART_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY06_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY06_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY06_FUNC_CTL_SOC_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY06_FUNC_CTL_SOC_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY07_FUNC_CTL function mux definitions */ +#define IOC_PY07_FUNC_CTL_PGPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY07_FUNC_CTL_PGPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY07_FUNC_CTL_UART_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY07_FUNC_CTL_UART_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY07_FUNC_CTL_PTMR_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY07_FUNC_CTL_PTMR_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY07_FUNC_CTL_SOC_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY07_FUNC_CTL_SOC_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #endif /* HPM_PMIC_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ppor_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ppor_drv.h index b1eb6e6ac53..687508cc684 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ppor_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ppor_drv.h @@ -11,15 +11,7 @@ typedef enum { ppor_reset_brownout = 1 << 0, - ppor_reset_temperature = 1 << 1, - ppor_reset_pin = 1 << 2, ppor_reset_debug = 1 << 4, - ppor_reset_security_violation = 1 << 5, - ppor_reset_jtag = 1 << 6, - ppor_reset_cpu0_lockup = 1 << 8, - ppor_reset_cpu1_lockup = 1 << 9, - ppor_reset_cpu0_request = 1 << 10, - ppor_reset_cpu1_request = 1 << 11, ppor_reset_wdog0 = 1 << 16, ppor_reset_wdog1 = 1 << 17, ppor_reset_wdog2 = 1 << 18, @@ -92,7 +84,31 @@ static inline uint32_t ppor_reset_get_flags(PPOR_Type *ptr) */ static inline void ppor_reset_clear_flags(PPOR_Type *ptr, uint32_t mask) { - ptr->RESET_FLAG |= mask; + ptr->RESET_FLAG = mask; +} + +/* + * get reset hold + */ +static inline uint32_t ppor_reset_get_hold(PPOR_Type *ptr) +{ + return ptr->RESET_HOLD; +} + +/* + * set reset hold + */ +static inline void ppor_reset_set_hold_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_HOLD |= mask; +} + +/* + * clear reset hold + */ +static inline void ppor_reset_clear_hold_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_HOLD &= ~mask; } /* @@ -100,7 +116,7 @@ static inline void ppor_reset_clear_flags(PPOR_Type *ptr, uint32_t mask) */ static inline void ppor_reset_set_cold_reset_enable(PPOR_Type *ptr, uint32_t mask) { - ptr->RESET_COLD = mask; + ptr->RESET_COLD |= mask; } /* @@ -116,7 +132,7 @@ static inline void ppor_reset_clear_cold_reset_enable(PPOR_Type *ptr, uint32_t m */ static inline void ppor_reset_set_hot_reset_enable(PPOR_Type *ptr, uint32_t mask) { - ptr->RESET_HOT = mask; + ptr->RESET_HOT |= mask; } /* diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ppor_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ppor_regs.h index 21cb6fc2370..7ce378b07da 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ppor_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ppor_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_romapi.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_romapi.h index 849508c575b..81c8b5d2c60 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_romapi.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_romapi.h @@ -326,7 +326,7 @@ typedef struct { /**< Bootloader API table: copyright string address */ const char *copyright; /**< Bootloader API table: run_bootloader API */ - const hpm_stat_t (*run_bootloader)(void *arg); + hpm_stat_t (*run_bootloader)(void *arg); /**< Bootloader API table: otp driver interface address */ const otp_driver_interface_t *otp_driver_if; /**< Bootloader API table: xpi driver interface address */ @@ -382,9 +382,13 @@ static inline void rom_xpi_nor_api_setup(void) 0x300027f3, 0xf6b36719, 0xe68100e7, 0x90738fd9, 0x80823007, }; if (ROM_API_TABLE_ROOT->version == 0x56010000UL) { - typedef void (*api_setup_entry_t)(void); - api_setup_entry_t entry = (api_setup_entry_t) &s_setup_code[0]; - entry(); + typedef union { + void (*callback)(void); + const uint32_t *buffer; + } api_setup_entry_t; + volatile api_setup_entry_t entry; + entry.buffer = &s_setup_code[0]; + entry.callback(); } } @@ -732,7 +736,7 @@ static inline bool rom_xpi_nor_exip_region_config(XPI_Type *base, uint32_t index /** * @brief Disable EXiP Feature on specified EXiP Region - * @@param [in] base XPI base address + * @param [in] base XPI base address * @param [in] index EXiP Region index */ ATTR_RAMFUNC @@ -752,7 +756,7 @@ static inline void rom_xpi_nor_exip_region_disable(XPI_Type *base, uint32_t inde /** * @brief Enable global EXiP logic - * @@param [in] base XPI base address + * @param [in] base XPI base address */ ATTR_RAMFUNC static inline void rom_xpi_nor_exip_enable(XPI_Type *base) @@ -769,7 +773,7 @@ static inline void rom_xpi_nor_exip_enable(XPI_Type *base) /** * @brief Disable global EXiP logic - * @@param [in] base XPI base address + * @param [in] base XPI base address */ ATTR_RAMFUNC static inline void rom_xpi_nor_exip_disable(XPI_Type *base) diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ses_reg.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ses_reg.xml index ce9cb93e723..294950547ef 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ses_reg.xml +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ses_reg.xml @@ -4461,6 +4461,26 @@ + + + + + + + + + + + + + + + + + + + + @@ -4501,6 +4521,126 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -4541,6 +4681,126 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -4581,6 +4841,126 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -4813,9 +5193,6 @@ - - - @@ -5133,7 +5510,6 @@ - @@ -5148,7 +5524,7 @@ - + @@ -5162,7 +5538,7 @@ - + @@ -5274,7 +5650,6 @@ - @@ -5516,9 +5891,6 @@ - - - @@ -5836,7 +6208,6 @@ - @@ -5851,7 +6222,7 @@ - + @@ -5865,7 +6236,7 @@ - + @@ -5977,7 +6348,6 @@ - @@ -6219,9 +6589,6 @@ - - - @@ -6539,7 +6906,6 @@ - @@ -6554,7 +6920,7 @@ - + @@ -6568,7 +6934,7 @@ - + @@ -6680,7 +7046,6 @@ - @@ -6694,7 +7059,6 @@ - @@ -6702,7 +7066,6 @@ - @@ -6713,7 +7076,6 @@ - @@ -6724,11 +7086,9 @@ - + - - @@ -6747,18 +7107,23 @@ - + + + + + + + - - - + + @@ -6773,46 +7138,37 @@ - - - - - - - - + - - @@ -6831,18 +7187,23 @@ - + + + + + + + - - - + + @@ -6857,46 +7218,37 @@ - - - - - - - - + - - @@ -6915,18 +7267,23 @@ - + + + + + + + - - - + + @@ -6941,46 +7298,37 @@ - - - - - - - - + - - @@ -6999,18 +7347,23 @@ - + + + + + + + - - - + + @@ -7025,35 +7378,28 @@ - - - - - - - @@ -7398,7 +7744,6 @@ - @@ -7491,7 +7836,6 @@ - @@ -7584,7 +7928,6 @@ - @@ -7677,7 +8020,6 @@ - @@ -7775,7 +8117,6 @@ - @@ -7841,6 +8182,9 @@ + + + @@ -7849,7 +8193,6 @@ - @@ -7915,6 +8258,9 @@ + + + @@ -7923,7 +8269,6 @@ - @@ -7989,6 +8334,9 @@ + + + @@ -7997,7 +8345,6 @@ - @@ -8063,6 +8410,9 @@ + + + @@ -8071,7 +8421,6 @@ - @@ -8137,6 +8486,9 @@ + + + @@ -8145,7 +8497,6 @@ - @@ -8211,6 +8562,9 @@ + + + @@ -8219,7 +8573,6 @@ - @@ -8285,6 +8638,9 @@ + + + @@ -8293,7 +8649,6 @@ - @@ -8359,6 +8714,9 @@ + + + @@ -8367,7 +8725,6 @@ - @@ -8433,6 +8790,9 @@ + + + @@ -8821,7 +9181,7 @@ - + @@ -11135,7 +11495,7 @@ - + @@ -13449,7 +13809,7 @@ - + @@ -15763,7 +16123,7 @@ - + @@ -17750,20 +18110,16 @@ - - - - @@ -17776,7 +18132,6 @@ - @@ -17796,20 +18151,16 @@ - - - - @@ -17822,7 +18173,6 @@ - @@ -17842,20 +18192,16 @@ - - - - @@ -17868,7 +18214,6 @@ - @@ -17888,20 +18233,16 @@ - - - - @@ -17914,7 +18255,6 @@ - @@ -17937,7 +18277,6 @@ - @@ -17983,7 +18322,6 @@ - @@ -18046,6 +18384,12 @@ + + + + + + @@ -19033,48 +19377,33 @@ - - - - - - - - - - - - - - - @@ -19185,7 +19514,6 @@ - @@ -19193,7 +19521,6 @@ - @@ -19295,54 +19622,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -19407,38 +19686,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -19446,196 +19693,84 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -19717,34 +19852,9 @@ - - - - - - - - - - - - - - - - - - - - - - - - - @@ -19794,34 +19904,9 @@ - - - - - - - - - - - - - - - - - - - - - - - - - @@ -19928,145 +20013,81 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -20103,7 +20124,6 @@ - @@ -20111,7 +20131,6 @@ - @@ -20213,54 +20232,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -20325,38 +20296,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -20364,196 +20303,84 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -20635,34 +20462,9 @@ - - - - - - - - - - - - - - - - - - - - - - - - - @@ -20712,34 +20514,9 @@ - - - - - - - - - - - - - - - - - - - - - - - - - @@ -20846,145 +20623,81 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -21021,7 +20734,6 @@ - @@ -21029,7 +20741,6 @@ - @@ -21131,54 +20842,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -21243,38 +20906,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -21282,196 +20913,84 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -21553,34 +21072,9 @@ - - - - - - - - - - - - - - - - - - - - - - - - - @@ -21630,34 +21124,9 @@ - - - - - - - - - - - - - - - - - - - - - - - - - @@ -21764,145 +21233,81 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -21939,7 +21344,6 @@ - @@ -21947,7 +21351,6 @@ - @@ -22049,54 +21452,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -22161,38 +21516,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -22200,196 +21523,84 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -22471,34 +21682,9 @@ - - - - - - - - - - - - - - - - - - - - - - - - - @@ -22548,34 +21734,9 @@ - - - - - - - - - - - - - - - - - - - - - - - - - @@ -22682,145 +21843,81 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -22853,16 +21950,11 @@ - - - - - @@ -22870,7 +21962,6 @@ - @@ -22878,10 +21969,6 @@ - - - - @@ -22891,10 +21978,6 @@ - - - - @@ -22904,10 +21987,6 @@ - - - - @@ -22917,10 +21996,6 @@ - - - - @@ -22930,10 +22005,6 @@ - - - - @@ -22942,8 +22013,6 @@ - - @@ -22960,8 +22029,6 @@ - - @@ -22978,8 +22045,6 @@ - - @@ -22996,8 +22061,6 @@ - - @@ -23032,16 +22095,11 @@ - - - - - @@ -23049,7 +22107,6 @@ - @@ -23057,10 +22114,6 @@ - - - - @@ -23070,10 +22123,6 @@ - - - - @@ -23083,10 +22132,6 @@ - - - - @@ -23096,10 +22141,6 @@ - - - - @@ -23109,10 +22150,6 @@ - - - - @@ -23121,8 +22158,6 @@ - - @@ -23139,8 +22174,6 @@ - - @@ -23157,8 +22190,6 @@ - - @@ -23175,8 +22206,6 @@ - - @@ -23211,16 +22240,11 @@ - - - - - @@ -23228,7 +22252,6 @@ - @@ -23236,10 +22259,6 @@ - - - - @@ -23249,10 +22268,6 @@ - - - - @@ -23262,10 +22277,6 @@ - - - - @@ -23275,10 +22286,6 @@ - - - - @@ -23288,10 +22295,6 @@ - - - - @@ -23300,8 +22303,6 @@ - - @@ -23318,8 +22319,6 @@ - - @@ -23336,8 +22335,6 @@ - - @@ -23354,8 +22351,6 @@ - - @@ -23390,16 +22385,11 @@ - - - - - @@ -23407,7 +22397,6 @@ - @@ -23415,10 +22404,6 @@ - - - - @@ -23428,10 +22413,6 @@ - - - - @@ -23441,10 +22422,6 @@ - - - - @@ -23454,10 +22431,6 @@ - - - - @@ -23467,10 +22440,6 @@ - - - - @@ -23479,8 +22448,6 @@ - - @@ -23497,8 +22464,6 @@ - - @@ -23515,8 +22480,6 @@ - - @@ -23533,8 +22496,6 @@ - - @@ -23581,7 +22542,6 @@ - @@ -23738,7 +22698,6 @@ - @@ -23895,7 +22854,6 @@ - @@ -24052,7 +23010,6 @@ - @@ -33252,12 +32209,12 @@ - - + + - - + + @@ -33303,23 +32260,23 @@ - + - - + + - - + + - - + + - - + + @@ -33443,7 +32400,6 @@ - @@ -33486,7 +32442,6 @@ - @@ -33529,7 +32484,6 @@ - @@ -33572,7 +32526,6 @@ - @@ -33614,7 +32567,6 @@ - @@ -33633,7 +32585,6 @@ - @@ -33658,7 +32609,6 @@ - @@ -33701,7 +32651,6 @@ - @@ -33744,7 +32693,6 @@ - @@ -33787,7 +32735,6 @@ - @@ -33829,7 +32776,6 @@ - @@ -33848,7 +32794,6 @@ - @@ -33873,7 +32818,6 @@ - @@ -33916,7 +32860,6 @@ - @@ -33959,7 +32902,6 @@ - @@ -34002,7 +32944,6 @@ - @@ -34044,7 +32985,6 @@ - @@ -34063,7 +33003,6 @@ - @@ -34088,7 +33027,6 @@ - @@ -34131,7 +33069,6 @@ - @@ -34174,7 +33111,6 @@ - @@ -34217,7 +33153,6 @@ - @@ -34259,7 +33194,6 @@ - @@ -34278,7 +33212,6 @@ - @@ -34303,7 +33236,6 @@ - @@ -34346,7 +33278,6 @@ - @@ -34389,7 +33320,6 @@ - @@ -34432,7 +33362,6 @@ - @@ -34474,7 +33403,6 @@ - @@ -34493,7 +33421,6 @@ - @@ -34517,11 +33444,9 @@ - - @@ -34534,7 +33459,6 @@ - @@ -34552,15 +33476,12 @@ - - - @@ -34569,15 +33490,12 @@ - - - @@ -34586,17 +33504,14 @@ - - - @@ -34609,7 +33524,6 @@ - @@ -34627,15 +33541,12 @@ - - - @@ -34644,15 +33555,12 @@ - - - @@ -34661,17 +33569,14 @@ - - - @@ -34684,7 +33589,6 @@ - @@ -34702,15 +33606,12 @@ - - - @@ -34719,15 +33620,12 @@ - - - @@ -34736,17 +33634,14 @@ - - - @@ -34759,7 +33654,6 @@ - @@ -34777,15 +33671,12 @@ - - - @@ -34794,15 +33685,12 @@ - - - @@ -34811,7 +33699,6 @@ - @@ -35113,13 +34000,11 @@ - - @@ -35128,36 +34013,27 @@ - - - - - - - - - @@ -35166,9 +34042,7 @@ - - @@ -35218,14 +34092,12 @@ - - @@ -43989,7 +42861,6 @@ - @@ -44027,7 +42898,6 @@ - @@ -44319,6 +43189,12 @@ + + + + + + @@ -44363,6 +43239,12 @@ + + + + + + @@ -44427,6 +43309,21 @@ + + + + + + + + + + + + + + + @@ -44493,29 +43390,29 @@ - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + @@ -44744,4 +43641,4 @@ - \ No newline at end of file + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ses_riscv_cpu_regs.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ses_riscv_cpu_regs.xml index de6e896482d..9e30fbc73a7 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ses_riscv_cpu_regs.xml +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ses_riscv_cpu_regs.xml @@ -767,4 +767,4 @@ - \ No newline at end of file + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_soc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_soc.h index ea9c0a00cb9..217fc4ac941 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_soc.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_soc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -11,99 +11,99 @@ /* List of external IRQs */ -#define IRQn_GPIO0_A 1 /* GPIO0_A IRQ */ -#define IRQn_GPIO0_B 2 /* GPIO0_B IRQ */ -#define IRQn_GPIO0_C 3 /* GPIO0_C IRQ */ -#define IRQn_GPIO0_D 4 /* GPIO0_D IRQ */ -#define IRQn_GPIO0_X 5 /* GPIO0_X IRQ */ -#define IRQn_GPIO0_Y 6 /* GPIO0_Y IRQ */ -#define IRQn_GPIO0_Z 7 /* GPIO0_Z IRQ */ -#define IRQn_GPIO1_A 8 /* GPIO1_A IRQ */ -#define IRQn_GPIO1_B 9 /* GPIO1_B IRQ */ -#define IRQn_GPIO1_C 10 /* GPIO1_C IRQ */ -#define IRQn_GPIO1_D 11 /* GPIO1_D IRQ */ -#define IRQn_GPIO1_X 12 /* GPIO1_X IRQ */ -#define IRQn_GPIO1_Y 13 /* GPIO1_Y IRQ */ -#define IRQn_GPIO1_Z 14 /* GPIO1_Z IRQ */ -#define IRQn_ADC0 15 /* ADC0 IRQ */ -#define IRQn_ADC1 16 /* ADC1 IRQ */ -#define IRQn_ADC2 17 /* ADC2 IRQ */ -#define IRQn_SDFM 18 /* SDFM IRQ */ -#define IRQn_DAC0 19 /* DAC0 IRQ */ -#define IRQn_DAC1 20 /* DAC1 IRQ */ -#define IRQn_ACMP_0 21 /* ACMP[0] IRQ */ -#define IRQn_ACMP_1 22 /* ACMP[1] IRQ */ -#define IRQn_ACMP_2 23 /* ACMP[2] IRQ */ -#define IRQn_ACMP_3 24 /* ACMP[3] IRQ */ -#define IRQn_SPI0 25 /* SPI0 IRQ */ -#define IRQn_SPI1 26 /* SPI1 IRQ */ -#define IRQn_SPI2 27 /* SPI2 IRQ */ -#define IRQn_SPI3 28 /* SPI3 IRQ */ -#define IRQn_UART0 29 /* UART0 IRQ */ -#define IRQn_UART1 30 /* UART1 IRQ */ -#define IRQn_UART2 31 /* UART2 IRQ */ -#define IRQn_UART3 32 /* UART3 IRQ */ -#define IRQn_UART4 33 /* UART4 IRQ */ -#define IRQn_UART5 34 /* UART5 IRQ */ -#define IRQn_UART6 35 /* UART6 IRQ */ -#define IRQn_UART7 36 /* UART7 IRQ */ -#define IRQn_CAN0 37 /* CAN0 IRQ */ -#define IRQn_CAN1 38 /* CAN1 IRQ */ -#define IRQn_CAN2 39 /* CAN2 IRQ */ -#define IRQn_CAN3 40 /* CAN3 IRQ */ -#define IRQn_PTPC 41 /* PTPC IRQ */ -#define IRQn_WDG0 42 /* WDG0 IRQ */ -#define IRQn_WDG1 43 /* WDG1 IRQ */ -#define IRQn_TSNS 44 /* TSNS IRQ */ -#define IRQn_MBX0A 45 /* MBX0A IRQ */ -#define IRQn_MBX0B 46 /* MBX0B IRQ */ -#define IRQn_MBX1A 47 /* MBX1A IRQ */ -#define IRQn_MBX1B 48 /* MBX1B IRQ */ -#define IRQn_GPTMR0 49 /* GPTMR0 IRQ */ -#define IRQn_GPTMR1 50 /* GPTMR1 IRQ */ -#define IRQn_GPTMR2 51 /* GPTMR2 IRQ */ -#define IRQn_GPTMR3 52 /* GPTMR3 IRQ */ -#define IRQn_I2C0 53 /* I2C0 IRQ */ -#define IRQn_I2C1 54 /* I2C1 IRQ */ -#define IRQn_I2C2 55 /* I2C2 IRQ */ -#define IRQn_I2C3 56 /* I2C3 IRQ */ -#define IRQn_PWM0 57 /* PWM0 IRQ */ -#define IRQn_HALL0 58 /* HALL0 IRQ */ -#define IRQn_QEI0 59 /* QEI0 IRQ */ -#define IRQn_PWM1 60 /* PWM1 IRQ */ -#define IRQn_HALL1 61 /* HALL1 IRQ */ -#define IRQn_QEI1 62 /* QEI1 IRQ */ -#define IRQn_PWM2 63 /* PWM2 IRQ */ -#define IRQn_HALL2 64 /* HALL2 IRQ */ -#define IRQn_QEI2 65 /* QEI2 IRQ */ -#define IRQn_PWM3 66 /* PWM3 IRQ */ -#define IRQn_HALL3 67 /* HALL3 IRQ */ -#define IRQn_QEI3 68 /* QEI3 IRQ */ -#define IRQn_SDP 69 /* SDP IRQ */ -#define IRQn_XPI0 70 /* XPI0 IRQ */ -#define IRQn_XDMA 71 /* XDMA IRQ */ -#define IRQn_HDMA 72 /* HDMA IRQ */ -#define IRQn_RNG 73 /* RNG IRQ */ -#define IRQn_USB0 74 /* USB0 IRQ */ -#define IRQn_PSEC 75 /* PSEC IRQ */ -#define IRQn_PGPIO 76 /* PGPIO IRQ */ -#define IRQn_PWDG 77 /* PWDG IRQ */ -#define IRQn_PTMR 78 /* PTMR IRQ */ -#define IRQn_PUART 79 /* PUART IRQ */ -#define IRQn_FUSE 80 /* FUSE IRQ */ -#define IRQn_SECMON 81 /* SECMON IRQ */ -#define IRQn_RTC 82 /* RTC IRQ */ -#define IRQn_BUTN 83 /* BUTN IRQ */ -#define IRQn_BGPIO 84 /* BGPIO IRQ */ -#define IRQn_BVIO 85 /* BVIO IRQ */ -#define IRQn_BROWNOUT 86 /* BROWNOUT IRQ */ -#define IRQn_SYSCTL 87 /* SYSCTL IRQ */ -#define IRQn_DEBUG_0 88 /* DEBUG[0] IRQ */ -#define IRQn_DEBUG_1 89 /* DEBUG[1] IRQ */ -#define IRQn_LIN0 90 /* LIN0 IRQ */ -#define IRQn_LIN1 91 /* LIN1 IRQ */ -#define IRQn_LIN2 92 /* LIN2 IRQ */ -#define IRQn_LIN3 93 /* LIN3 IRQ */ +#define IRQn_GPIO0_A 1 /* GPIO0_A IRQ */ +#define IRQn_GPIO0_B 2 /* GPIO0_B IRQ */ +#define IRQn_GPIO0_C 3 /* GPIO0_C IRQ */ +#define IRQn_GPIO0_D 4 /* GPIO0_D IRQ */ +#define IRQn_GPIO0_X 5 /* GPIO0_X IRQ */ +#define IRQn_GPIO0_Y 6 /* GPIO0_Y IRQ */ +#define IRQn_GPIO0_Z 7 /* GPIO0_Z IRQ */ +#define IRQn_GPIO1_A 8 /* GPIO1_A IRQ */ +#define IRQn_GPIO1_B 9 /* GPIO1_B IRQ */ +#define IRQn_GPIO1_C 10 /* GPIO1_C IRQ */ +#define IRQn_GPIO1_D 11 /* GPIO1_D IRQ */ +#define IRQn_GPIO1_X 12 /* GPIO1_X IRQ */ +#define IRQn_GPIO1_Y 13 /* GPIO1_Y IRQ */ +#define IRQn_GPIO1_Z 14 /* GPIO1_Z IRQ */ +#define IRQn_ADC0 15 /* ADC0 IRQ */ +#define IRQn_ADC1 16 /* ADC1 IRQ */ +#define IRQn_ADC2 17 /* ADC2 IRQ */ +#define IRQn_SDFM 18 /* SDFM IRQ */ +#define IRQn_DAC0 19 /* DAC0 IRQ */ +#define IRQn_DAC1 20 /* DAC1 IRQ */ +#define IRQn_ACMP_0 21 /* ACMP[0] IRQ */ +#define IRQn_ACMP_1 22 /* ACMP[1] IRQ */ +#define IRQn_ACMP_2 23 /* ACMP[2] IRQ */ +#define IRQn_ACMP_3 24 /* ACMP[3] IRQ */ +#define IRQn_SPI0 25 /* SPI0 IRQ */ +#define IRQn_SPI1 26 /* SPI1 IRQ */ +#define IRQn_SPI2 27 /* SPI2 IRQ */ +#define IRQn_SPI3 28 /* SPI3 IRQ */ +#define IRQn_UART0 29 /* UART0 IRQ */ +#define IRQn_UART1 30 /* UART1 IRQ */ +#define IRQn_UART2 31 /* UART2 IRQ */ +#define IRQn_UART3 32 /* UART3 IRQ */ +#define IRQn_UART4 33 /* UART4 IRQ */ +#define IRQn_UART5 34 /* UART5 IRQ */ +#define IRQn_UART6 35 /* UART6 IRQ */ +#define IRQn_UART7 36 /* UART7 IRQ */ +#define IRQn_MCAN0 37 /* MCAN0 IRQ */ +#define IRQn_MCAN1 38 /* MCAN1 IRQ */ +#define IRQn_MCAN2 39 /* MCAN2 IRQ */ +#define IRQn_MCAN3 40 /* MCAN3 IRQ */ +#define IRQn_PTPC 41 /* PTPC IRQ */ +#define IRQn_WDG0 42 /* WDG0 IRQ */ +#define IRQn_WDG1 43 /* WDG1 IRQ */ +#define IRQn_TSNS 44 /* TSNS IRQ */ +#define IRQn_MBX0A 45 /* MBX0A IRQ */ +#define IRQn_MBX0B 46 /* MBX0B IRQ */ +#define IRQn_MBX1A 47 /* MBX1A IRQ */ +#define IRQn_MBX1B 48 /* MBX1B IRQ */ +#define IRQn_GPTMR0 49 /* GPTMR0 IRQ */ +#define IRQn_GPTMR1 50 /* GPTMR1 IRQ */ +#define IRQn_GPTMR2 51 /* GPTMR2 IRQ */ +#define IRQn_GPTMR3 52 /* GPTMR3 IRQ */ +#define IRQn_I2C0 53 /* I2C0 IRQ */ +#define IRQn_I2C1 54 /* I2C1 IRQ */ +#define IRQn_I2C2 55 /* I2C2 IRQ */ +#define IRQn_I2C3 56 /* I2C3 IRQ */ +#define IRQn_PWM0 57 /* PWM0 IRQ */ +#define IRQn_HALL0 58 /* HALL0 IRQ */ +#define IRQn_QEI0 59 /* QEI0 IRQ */ +#define IRQn_PWM1 60 /* PWM1 IRQ */ +#define IRQn_HALL1 61 /* HALL1 IRQ */ +#define IRQn_QEI1 62 /* QEI1 IRQ */ +#define IRQn_PWM2 63 /* PWM2 IRQ */ +#define IRQn_HALL2 64 /* HALL2 IRQ */ +#define IRQn_QEI2 65 /* QEI2 IRQ */ +#define IRQn_PWM3 66 /* PWM3 IRQ */ +#define IRQn_HALL3 67 /* HALL3 IRQ */ +#define IRQn_QEI3 68 /* QEI3 IRQ */ +#define IRQn_SDP 69 /* SDP IRQ */ +#define IRQn_XPI0 70 /* XPI0 IRQ */ +#define IRQn_XDMA 71 /* XDMA IRQ */ +#define IRQn_HDMA 72 /* HDMA IRQ */ +#define IRQn_RNG 73 /* RNG IRQ */ +#define IRQn_USB0 74 /* USB0 IRQ */ +#define IRQn_PSEC 75 /* PSEC IRQ */ +#define IRQn_PGPIO 76 /* PGPIO IRQ */ +#define IRQn_PWDG 77 /* PWDG IRQ */ +#define IRQn_PTMR 78 /* PTMR IRQ */ +#define IRQn_PUART 79 /* PUART IRQ */ +#define IRQn_FUSE 80 /* FUSE IRQ */ +#define IRQn_SECMON 81 /* SECMON IRQ */ +#define IRQn_RTC 82 /* RTC IRQ */ +#define IRQn_BUTN 83 /* BUTN IRQ */ +#define IRQn_BGPIO 84 /* BGPIO IRQ */ +#define IRQn_BVIO 85 /* BVIO IRQ */ +#define IRQn_BROWNOUT 86 /* BROWNOUT IRQ */ +#define IRQn_SYSCTL 87 /* SYSCTL IRQ */ +#define IRQn_DEBUG_0 88 /* DEBUG[0] IRQ */ +#define IRQn_DEBUG_1 89 /* DEBUG[1] IRQ */ +#define IRQn_LIN0 90 /* LIN0 IRQ */ +#define IRQn_LIN1 91 /* LIN1 IRQ */ +#define IRQn_LIN2 92 /* LIN2 IRQ */ +#define IRQn_LIN3 93 /* LIN3 IRQ */ #include "hpm_common.h" @@ -134,10 +134,6 @@ /* DM base address */ #define HPM_DM_BASE (0x30000000UL) -/* Address of XBUS_SOC instances */ -/* GPV_SOC base address */ -#define HPM_GPV_SOC_BASE (0x30100000UL) - #include "hpm_plic_regs.h" /* Address of PLIC instances */ /* PLIC base address */ @@ -457,10 +453,6 @@ /* SYNT base pointer */ #define HPM_SYNT ((SYNT_Type *) HPM_SYNT_BASE) -/* Address of PLA_X2 instances */ -/* PLA_X2 base address */ -#define HPM_PLA_X2_BASE (0xF024E000UL) - #include "hpm_usb_regs.h" /* Address of USB instances */ /* USB0 base address */ @@ -622,9 +614,12 @@ /* TSNS base pointer */ #define HPM_TSNS ((TSNS_Type *) HPM_TSNS_BASE) +#include "hpm_bacc_regs.h" /* Address of BACC instances */ /* BACC base address */ #define HPM_BACC_BASE (0xF5000000UL) +/* BACC base pointer */ +#define HPM_BACC ((BACC_Type *) HPM_BACC_BASE) #include "hpm_bpor_regs.h" /* Address of BPOR instances */ @@ -706,4 +701,4 @@ #include "hpm_iomux.h" #include "hpm_pmic_iomux.h" #include "hpm_batt_iomux.h" -#endif /* HPM_SOC_H */ \ No newline at end of file +#endif /* HPM_SOC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_soc_feature.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_soc_feature.h index 4b3ce8b3622..5200ab32855 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_soc_feature.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_soc_feature.h @@ -9,12 +9,12 @@ #define HPM_SOC_FEATURE_H #include "hpm_soc.h" +#include "hpm_soc_ip_feature.h" /* * UART section */ #define UART_SOC_FIFO_SIZE (16U) -#define UART_SOC_HAS_RXLINE_IDLE_DETECTION (1U) /* * I2C Section @@ -55,7 +55,6 @@ */ #define DMA_SOC_TRANSFER_WIDTH_MAX(x) (((x) == HPM_XDMA) ? DMA_TRANSFER_WIDTH_DOUBLE_WORD : DMA_TRANSFER_WIDTH_WORD) #define DMA_SOC_TRANSFER_PER_BURST_MAX(x) (((x) == HPM_XDMA) ? DMA_NUM_TRANSFER_PER_BURST_1024T : DMA_NUM_TRANSFER_PER_BURST_128T) -#define DMA_SOC_BUS_NUM (1U) #define DMA_SOC_CHANNEL_NUM (8U) #define DMA_SOC_MAX_COUNT (2U) #define DMA_SOC_CHN_TO_DMAMUX_CHN(x, n) (((x) == HPM_XDMA) ? (DMAMUX_MUXCFG_XDMA_MUX0 + n) : (DMAMUX_MUXCFG_HDMA_MUX0 + n)) @@ -81,24 +80,20 @@ #define USB_SOC_DCD_QTD_NEXT_INVALID (1U) #define USB_SOC_DCD_QHD_BUFFER_COUNT (5U) -#define USB_SOC_DCD_QTD_ALIGNMENT (32U) -#define USB_SOC_DCD_QHD_ALIGNMENT (64U) #define USB_SOC_DCD_MAX_ENDPOINT_COUNT (8U) -#define USB_SOC_DCD_MAX_QTD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U) +#ifndef USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT +#define USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT (8U) +#endif +#define USB_SOC_DCD_MAX_QTD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U * USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT) #define USB_SOS_DCD_MAX_QHD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U) #define USB_SOC_DCD_DATA_RAM_ADDRESS_ALIGNMENT (2048U) -#define USB_SOC_HCD_QTD_BUFFER_COUNT (5U) -#define USB_SOC_HCD_QTD_ALIGNMENT (32U) -#define USB_SOC_HCD_QHD_ALIGNMENT (32U) -#define USB_SOC_HCD_MAX_ENDPOINT_COUNT (8U) -#define USB_SOC_HCD_MAX_XFER_ENDPOINT_COUNT (USB_SOC_HCD_MAX_ENDPOINT_COUNT * 2U) #define USB_SOC_HCD_FRAMELIST_MAX_ELEMENTS (1024U) -#define USB_SOC_HCD_DATA_RAM_ADDRESS_ALIGNMENT (4096U) /* * ADC Section */ +#define ADC_SOC_IP_VERSION (1U) #define ADC_SOC_SEQ_MAX_LEN (16U) #define ADC_SOC_MAX_TRIG_CH_LEN (4U) #define ADC_SOC_MAX_TRIG_CH_NUM (11U) @@ -170,10 +165,4 @@ #define PWM_SOC_SHADOW_TRIG_SUPPORT (1U) #define PWM_SOC_TIMER_RESET_SUPPORT (1U) -/** - * IOC Section - * - */ -#define IOC_SOC_PAD_MAX (487) - #endif /* HPM_SOC_FEATURE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_soc_ip_feature.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_soc_ip_feature.h new file mode 100644 index 00000000000..bc97a6413b7 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_soc_ip_feature.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_SOC_IP_FEATURE_H +#define HPM_SOC_IP_FEATURE_H + +/* UART related feature */ +#define HPM_IP_FEATURE_UART_RX_IDLE_DETECT 1 + +/* PWM related feature */ +#define HPM_IP_FEATURE_PWM_COUNTER_RESET 1 +#define HPM_IP_FEATURE_PWM_HRPWM 1 + +#endif /* HPM_SOC_IP_FEATURE_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_drv.c index ffc21973f77..7e2d2cf73d5 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_drv.c @@ -102,6 +102,7 @@ hpm_stat_t sysctl_cpu1_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, u void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config) { + (void) ptr; config->mode = monitor_work_mode_record; config->accuracy = monitor_accuracy_1khz; config->reference = monitor_reference_24mhz; @@ -113,16 +114,16 @@ void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *confi config->target = monitor_target_clk_top_cpu0; } -void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t slice, monitor_config_t *config) +void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config_t *config) { - ptr->MONITOR[slice].CONTROL &= ~(SYSCTL_MONITOR_CONTROL_START_MASK | SYSCTL_MONITOR_CONTROL_OUTEN_MASK); + ptr->MONITOR[monitor_index].CONTROL &= ~(SYSCTL_MONITOR_CONTROL_START_MASK | SYSCTL_MONITOR_CONTROL_OUTEN_MASK); if (config->mode == monitor_work_mode_compare) { - ptr->MONITOR[slice].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(config->high_limit); - ptr->MONITOR[slice].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(config->low_limit); + ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(config->high_limit); + ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(config->low_limit); } - ptr->MONITOR[slice].CONTROL = (ptr->MONITOR[slice].CONTROL & + ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL & ~(SYSCTL_MONITOR_CONTROL_DIV_MASK | SYSCTL_MONITOR_CONTROL_MODE_MASK | SYSCTL_MONITOR_CONTROL_ACCURACY_MASK | SYSCTL_MONITOR_CONTROL_REFERENCE_MASK | SYSCTL_MONITOR_CONTROL_SELECTION_MASK)) | (SYSCTL_MONITOR_CONTROL_DIV_SET(config->divide_by - 1) | SYSCTL_MONITOR_CONTROL_MODE_SET(config->mode) | @@ -172,22 +173,32 @@ hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry) hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, uint8_t group, - sysctl_resource_t linkable_resource, + sysctl_resource_t resource, bool enable) { uint32_t index, offset; - if (linkable_resource < sysctl_resource_linkable_start) { + if (resource < sysctl_resource_linkable_start) { return status_invalid_argument; } - index = (linkable_resource - sysctl_resource_linkable_start) / 32; - offset = (linkable_resource - sysctl_resource_linkable_start) % 32; + index = (resource - sysctl_resource_linkable_start) / 32; + offset = (resource - sysctl_resource_linkable_start) % 32; switch (group) { case SYSCTL_RESOURCE_GROUP0: ptr->GROUP0[index].VALUE = (ptr->GROUP0[index].VALUE & ~(1UL << offset)) | (enable ? (1UL << offset) : 0); + if (enable) { + while (sysctl_resource_target_is_busy(ptr, resource)) { + ; + } + } break; case SYSCTL_RESOURCE_GROUP1: ptr->GROUP1[index].VALUE = (ptr->GROUP1[index].VALUE & ~(1UL << offset)) | (enable ? (1UL << offset) : 0); + if (enable) { + while (sysctl_resource_target_is_busy(ptr, resource)) { + ; + } + } break; default: return status_invalid_argument; @@ -196,6 +207,47 @@ hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, return status_success; } +bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, + uint8_t group, + sysctl_resource_t resource) +{ + uint32_t index, offset; + bool enable; + + index = (resource - sysctl_resource_linkable_start) / 32; + offset = (resource - sysctl_resource_linkable_start) % 32; + switch (group) { + case SYSCTL_RESOURCE_GROUP0: + enable = ((ptr->GROUP0[index].VALUE & (1UL << offset)) != 0) ? true : false; + break; + case SYSCTL_RESOURCE_GROUP1: + enable = ((ptr->GROUP1[index].VALUE & (1UL << offset)) != 0) ? true : false; + break; + default: + enable = false; + break; + } + + return enable; +} + +uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index) +{ + uint32_t value; + switch (group) { + case SYSCTL_RESOURCE_GROUP0: + value = ptr->GROUP0[index].VALUE; + break; + case SYSCTL_RESOURCE_GROUP1: + value = ptr->GROUP1[index].VALUE; + break; + default: + value = 0; + break; + } + return value; +} + hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) { return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, true); @@ -216,9 +268,8 @@ hpm_stat_t sysctl_remove_resource_from_cpu1(SYSCTL_Type *ptr, sysctl_resource_t return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP1, resource, false); } -hpm_stat_t sysctl_update_divider(SYSCTL_Type *ptr, clock_node_t node_index, uint32_t divide_by) +hpm_stat_t sysctl_update_divider(SYSCTL_Type *ptr, clock_node_t node, uint32_t divide_by) { - uint32_t node = (uint32_t) node_index; if (node >= clock_node_adc_start) { return status_invalid_argument; } @@ -229,9 +280,8 @@ hpm_stat_t sysctl_update_divider(SYSCTL_Type *ptr, clock_node_t node_index, uint return status_success; } -hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node_index, clock_source_t source, uint32_t divide_by) +hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node, clock_source_t source, uint32_t divide_by) { - uint32_t node = (uint32_t) node_index; if (node >= clock_node_adc_start) { return status_invalid_argument; } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_drv.h index 77b317159eb..15348b3c186 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_drv.h @@ -1,5 +1,5 @@ /** - * Copyright (c) 2022-2023 HPMicro + * Copyright (c) 2022-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -613,6 +613,19 @@ static inline void sysctl_resource_target_set_mode(SYSCTL_Type *ptr, SYSCTL_RESOURCE_MODE_SET(mode); } +/** + * @brief Get target mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource target resource index + * @return target resource mode + */ +static inline uint8_t sysctl_resource_target_get_mode(SYSCTL_Type *ptr, + sysctl_resource_t resource) +{ + return SYSCTL_RESOURCE_MODE_GET(ptr->RESOURCE[resource]); +} + /** * @brief Disable resource retention when specific CPU enters stop mode * @@ -792,11 +805,33 @@ static inline bool sysctl_clock_any_is_busy(SYSCTL_Type *ptr) * @param[in] clock target clock * @return true if target clock is busy */ -static inline bool sysctl_clock_target_is_busy(SYSCTL_Type *ptr, uint32_t clock) +static inline bool sysctl_clock_target_is_busy(SYSCTL_Type *ptr, clock_node_t clock) { return ptr->CLOCK[clock] & SYSCTL_CLOCK_LOC_BUSY_MASK; } +/** + * @brief Preserve clock setting for certain node + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] clock target clock + */ +static inline void sysctl_clock_preserve_settings(SYSCTL_Type *ptr, clock_node_t clock) +{ + ptr->CLOCK[clock] |= SYSCTL_CLOCK_PRESERVE_MASK; +} + +/** + * @brief Unpreserve clock setting for certain node + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] clock target clock + */ +static inline void sysctl_clock_unpreserve_settings(SYSCTL_Type *ptr, clock_node_t clock) +{ + ptr->CLOCK[clock] &= ~SYSCTL_CLOCK_PRESERVE_MASK; +} + /** * @brief Set clock preset * @@ -1385,6 +1420,27 @@ hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t resource, bool enable); + +/** + * @brief Check group resource enable status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] group target group to be checked + * @param[in] resource target resource to be checked from group + * @return enable true if resource enable, false if resource disable + */ +bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t resource); + +/** + * @brief Get group resource value + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] group target group to be getted + * @param[in] index target group index + * @return group index value + */ +uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index); + /** * @brief Add resource to CPU0 * @@ -1439,7 +1495,7 @@ void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *confi void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config_t *config); /** - * @brief Save data to GPU0 GPR starting from given index + * @brief Save data to CPU0 GPR starting from given index * * @param[in] ptr SYSCTL_Type base address * @param[in] start Starting GPR index @@ -1451,7 +1507,7 @@ void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock); /** - * @brief Get data saved from GPU0 GPR starting from given index + * @brief Get data saved from CPU0 GPR starting from given index * * @param[in] ptr SYSCTL_Type base address * @param[in] start Starting GPR index diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_regs.h index 35ed3a3f6ec..0a8b810cb9b 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -33,10 +33,10 @@ typedef struct { __RW uint32_t TOGGLE; /* 0x90C: Affiliate of Group */ } AFFILIATE[2]; struct { - __RW uint32_t VALUE; /* 0x920: Retention Contol */ - __RW uint32_t SET; /* 0x924: Retention Contol */ - __RW uint32_t CLEAR; /* 0x928: Retention Contol */ - __RW uint32_t TOGGLE; /* 0x92C: Retention Contol */ + __RW uint32_t VALUE; /* 0x920: Retention Control */ + __RW uint32_t SET; /* 0x924: Retention Control */ + __RW uint32_t CLEAR; /* 0x928: Retention Control */ + __RW uint32_t TOGGLE; /* 0x92C: Retention Control */ } RETENTION[2]; __R uint8_t RESERVED3[1728]; /* 0x940 - 0xFFF: Reserved */ struct { @@ -455,7 +455,7 @@ typedef struct { * * perform reset and release imediately * 0: reset is released - * 1 reset is asserted and will release automaticly + * 1 reset is asserted and will release automatically */ #define SYSCTL_RESET_CONTROL_RESET_MASK (0x1U) #define SYSCTL_RESET_CONTROL_RESET_SHIFT (0U) @@ -892,7 +892,7 @@ typedef struct { /* * REFERENCE (RW) * - * refrence clock selection, + * reference clock selection, * 0: 32k * 1: 24M */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_trgm_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_trgm_regs.h index 3d210012666..a3796d28c9d 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_trgm_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_trgm_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_trgmmux_src.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_trgmmux_src.h index 4c0194a6747..2379fe38099 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_trgmmux_src.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_trgmmux_src.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -731,4 +731,4 @@ -#endif /* HPM_TRGMMUX_SRC_H */ \ No newline at end of file +#endif /* HPM_TRGMMUX_SRC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/soc_modules.list b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/soc_modules.list index 92980486828..b72d68e0496 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/soc_modules.list +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/soc_modules.list @@ -1,40 +1,61 @@ -# Copyright (c) 2023 HPMicro +# +# Copyright (c) 2024 HPMicro +# # SPDX-License-Identifier: BSD-3-Clause # -# In this file, all modules available on this part are listed -CONFIG_HAS_HPMSDK_UART=y -CONFIG_HAS_HPMSDK_FEMC=n -CONFIG_HAS_HPMSDK_SDP=y -CONFIG_HAS_HPMSDK_I2C=y -CONFIG_HAS_HPMSDK_PMP=y -CONFIG_HAS_HPMSDK_RNG=y -CONFIG_HAS_HPMSDK_GPIO=y -CONFIG_HAS_HPMSDK_SPI=y -CONFIG_HAS_HPMSDK_WDG=y -CONFIG_HAS_HPMSDK_DMA=y -CONFIG_HAS_HPMSDK_GPTMR=y -CONFIG_HAS_HPMSDK_PWM=y -CONFIG_HAS_HPMSDK_PLLCTLV2=y -CONFIG_HAS_HPMSDK_USB=y -CONFIG_HAS_HPMSDK_RTC=y -CONFIG_HAS_HPMSDK_ACMP=y -CONFIG_HAS_HPMSDK_I2S=n -CONFIG_HAS_HPMSDK_DAO=n -CONFIG_HAS_HPMSDK_PDM=n -CONFIG_HAS_HPMSDK_VAD=n -CONFIG_HAS_HPMSDK_MCAN=y -CONFIG_HAS_HPMSDK_ENET=n -CONFIG_HAS_HPMSDK_SDXC=n -CONFIG_HAS_HPMSDK_ADC16=y -CONFIG_HAS_HPMSDK_PCFG=y -CONFIG_HAS_HPMSDK_PMU=y -CONFIG_HAS_HPMSDK_PTPC=y -CONFIG_HAS_HPMSDK_MCHTMR=y -CONFIG_HAS_HPMSDK_FFA=n -CONFIG_HAS_HPMSDK_TSNS=y -CONFIG_HAS_HPMSDK_DAC=y -CONFIG_HAS_HPMSDK_CRC=y -CONFIG_HAS_HPMSDK_PLA=y -CONFIG_HAS_HPMSDK_SDM=y -CONFIG_HAS_HPMSDK_LIN=y +HPMSOC_HAS_HPMSDK_MULTICORE=y +HPMSOC_HAS_HPMSDK_GPIO=y +HPMSOC_HAS_HPMSDK_PLIC=y +HPMSOC_HAS_HPMSDK_MCHTMR=y +HPMSOC_HAS_HPMSDK_PLICSW=y +HPMSOC_HAS_HPMSDK_GPIOM=y +HPMSOC_HAS_HPMSDK_ADC16=y +HPMSOC_HAS_HPMSDK_SDM=y +HPMSOC_HAS_HPMSDK_ACMP=y +HPMSOC_HAS_HPMSDK_DAC=y +HPMSOC_HAS_HPMSDK_SPI=y +HPMSOC_HAS_HPMSDK_UART=y +HPMSOC_HAS_HPMSDK_MCAN=y +HPMSOC_HAS_HPMSDK_WDG=y +HPMSOC_HAS_HPMSDK_MBX=y +HPMSOC_HAS_HPMSDK_PTPC=y +HPMSOC_HAS_HPMSDK_CRC=y +HPMSOC_HAS_HPMSDK_DMAMUX=y +HPMSOC_HAS_HPMSDK_DMA=y +HPMSOC_HAS_HPMSDK_RNG=y +HPMSOC_HAS_HPMSDK_KEYM=y +HPMSOC_HAS_HPMSDK_PWM=y +HPMSOC_HAS_HPMSDK_HALL=y +HPMSOC_HAS_HPMSDK_QEI=y +HPMSOC_HAS_HPMSDK_TRGM=y +HPMSOC_HAS_HPMSDK_PLA=y +HPMSOC_HAS_HPMSDK_SYNT=y +HPMSOC_HAS_HPMSDK_USB=y +HPMSOC_HAS_HPMSDK_GPTMR=y +HPMSOC_HAS_HPMSDK_I2C=y +HPMSOC_HAS_HPMSDK_LIN=y +HPMSOC_HAS_HPMSDK_SDP=y +HPMSOC_HAS_HPMSDK_SYSCTL=y +HPMSOC_HAS_HPMSDK_IOC=y +HPMSOC_HAS_HPMSDK_OTP=y +HPMSOC_HAS_HPMSDK_PPOR=y +HPMSOC_HAS_HPMSDK_PCFG=y +HPMSOC_HAS_HPMSDK_PSEC=y +HPMSOC_HAS_HPMSDK_PMON=y +HPMSOC_HAS_HPMSDK_PGPR=y +HPMSOC_HAS_HPMSDK_PLLCTLV2=y +HPMSOC_HAS_HPMSDK_TSNS=y +HPMSOC_HAS_HPMSDK_BACC=y +HPMSOC_HAS_HPMSDK_BPOR=y +HPMSOC_HAS_HPMSDK_BCFG=y +HPMSOC_HAS_HPMSDK_BUTN=y +HPMSOC_HAS_HPMSDK_BGPR=y +HPMSOC_HAS_HPMSDK_BSEC=y +HPMSOC_HAS_HPMSDK_RTC=y +HPMSOC_HAS_HPMSDK_BKEY=y +HPMSOC_HAS_HPMSDK_BMON=y +HPMSOC_HAS_HPMSDK_TAMP=y +HPMSOC_HAS_HPMSDK_MONO=y +HPMSOC_HAS_HPMSDK_PMP=y + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/system.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/system.c index 3f742ad69ad..a0fb6800e94 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/system.c +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/system.c @@ -60,12 +60,4 @@ __attribute__((weak)) void system_init(void) enable_global_irq(CSR_MSTATUS_MIE_MASK); #endif #endif - -#ifndef CONFIG_NOT_ENABLE_ICACHE - l1c_ic_enable(); -#endif -#ifndef CONFIG_NOT_ENABLE_DCACHE - l1c_dc_enable(); - l1c_dc_invalidate_all(); -#endif } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash.ld index 7dee6bf34fb..8bf67d66740 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash.ld +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash.ld @@ -5,8 +5,8 @@ ENTRY(_start) -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; +STACK_SIZE = _stack_size; +HEAP_SIZE = _heap_size; MEMORY { @@ -26,7 +26,19 @@ SECTIONS KEEP(*(.start)) } > XPI0 - .text : { + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + KEEP(*(.vector_s_table)) + KEEP(*(.isr_s_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { . = ALIGN(8); *(.text) *(.text*) @@ -45,36 +57,51 @@ SECTIONS KEEP (*(.init)) KEEP (*(.fini)) - . = ALIGN(8); - } > XPI0 - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - /* section information for usbh class */ - .usbh_class_info : { - . = ALIGN(4); + /* section information for usbh class */ + . = ALIGN(8); __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; + + /* RT-Thread related sections - Start */ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ . = ALIGN(8); } > XPI0 + .rel : { + KEEP(*(.rel*)) + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - .vectors ORIGIN(ILM) : AT(etext) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .data : AT(etext + __vector_ram_end__ - __vector_ram_start__) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -82,8 +109,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -127,12 +152,14 @@ SECTIONS PROVIDE (edata = .); } > AXI_SRAM - .fast : AT(etext + __vector_ram_end__ - __vector_ram_start__ + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); - __ramfunc_start__ = .; + PROVIDE(__ramfunc_start__ = .); *(.fast) + *(.fast.*) . = ALIGN(8); - __ramfunc_end__ = .; + PROVIDE(__ramfunc_end__ = .); } > ILM .bss (NOLOAD) : { @@ -140,11 +167,9 @@ SECTIONS __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -152,13 +177,37 @@ SECTIONS __bss_end__ = .; } > AXI_SRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > AXI_SRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > AXI_SRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > AXI_SRAM - .noncacheable.init : AT(etext + __vector_ram_end__ - __vector_ram_start__ + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -208,5 +257,6 @@ SECTIONS __share_mem_start__ = ORIGIN(SHARE_RAM); __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - ASSERT((STACK_SIZE + HEAP_SIZE) <= 128K, "stack and heap total size larger than 128k") + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash_uf2.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash_uf2.ld index 393656ec2f9..9162402299c 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash_uf2.ld +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash_uf2.ld @@ -5,8 +5,8 @@ ENTRY(_start) -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; +STACK_SIZE = _stack_size; +HEAP_SIZE = _heap_size; UF2_BOOTLOADER_RESERVED_LENGTH = DEFINED(_uf2_bl_length) ? _uf2_bl_length : 0x20000; MEMORY @@ -27,7 +27,19 @@ SECTIONS KEEP(*(.start)) } > XPI0 - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__): { + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + KEEP(*(.vector_s_table)) + KEEP(*(.isr_s_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)): { . = ALIGN(8); *(.text) *(.text*) @@ -46,39 +58,51 @@ SECTIONS KEEP (*(.init)) KEEP (*(.fini)) - . = ALIGN(8); - } > XPI0 - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - /* section information for usbh class */ - .usbh_class_info : { - . = ALIGN(4); + /* section information for usbh class */ + . = ALIGN(8); __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; + + /* RT-Thread related sections - Start */ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ . = ALIGN(8); } > XPI0 + .rel : { + KEEP(*(.rel*)) + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - KEEP(*(.vector_s_table)) - KEEP(*(.isr_s_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .data : AT(etext) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -86,8 +110,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -131,12 +153,14 @@ SECTIONS PROVIDE (edata = .); } > AXI_SRAM - .fast : AT(etext + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); - __ramfunc_start__ = .; + PROVIDE(__ramfunc_start__ = .); *(.fast) + *(.fast.*) . = ALIGN(8); - __ramfunc_end__ = .; + PROVIDE(__ramfunc_end__ = .); } > ILM .bss (NOLOAD) : { @@ -144,11 +168,9 @@ SECTIONS __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -156,13 +178,37 @@ SECTIONS __bss_end__ = .; } > AXI_SRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > AXI_SRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > AXI_SRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -212,5 +258,6 @@ SECTIONS __share_mem_start__ = ORIGIN(SHARE_RAM); __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - ASSERT((STACK_SIZE + HEAP_SIZE) <= 128K, "stack and heap total size larger than 128k") + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash_xip.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash_xip.ld index cdc8b12f888..5795881df9b 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash_xip.ld +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash_xip.ld @@ -5,8 +5,8 @@ ENTRY(_start) -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; +STACK_SIZE = _stack_size; +HEAP_SIZE = _heap_size; MEMORY { @@ -25,6 +25,7 @@ __app_load_addr__ = ORIGIN(XPI0) + 0x3000; __boot_header_length__ = __boot_header_end__ - __boot_header_start__; __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + SECTIONS { .nor_cfg_option __nor_cfg_option_load_addr__ : { @@ -44,7 +45,19 @@ SECTIONS KEEP(*(.start)) } > XPI0 - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__): { + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + KEEP(*(.vector_s_table)) + KEEP(*(.isr_s_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { . = ALIGN(8); *(.text) *(.text*) @@ -63,39 +76,51 @@ SECTIONS KEEP (*(.init)) KEEP (*(.fini)) - . = ALIGN(8); - } > XPI0 - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - /* section information for usbh class */ - .usbh_class_info : { - . = ALIGN(4); + /* section information for usbh class */ + . = ALIGN(8); __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; + + /* RT-Thread related sections - Start */ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ . = ALIGN(8); } > XPI0 + .rel : { + KEEP(*(.rel*)) + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - KEEP(*(.vector_s_table)) - KEEP(*(.isr_s_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .data : AT(etext) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -148,25 +173,24 @@ SECTIONS PROVIDE (edata = .); } > AXI_SRAM - .fast : AT(etext + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); - __ramfunc_start__ = .; + PROVIDE(__ramfunc_start__ = .); *(.fast) + *(.fast.*) . = ALIGN(8); - __ramfunc_end__ = .; + PROVIDE(__ramfunc_end__ = .); } > ILM - __fw_size__ = __ramfunc_end__ - __ramfunc_start__ + __data_end__ - __data_start__ + etext - __app_load_addr__; .bss (NOLOAD) : { . = ALIGN(8); __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -174,13 +198,37 @@ SECTIONS __bss_end__ = .; } > AXI_SRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > AXI_SRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > AXI_SRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -230,5 +278,6 @@ SECTIONS __share_mem_start__ = ORIGIN(SHARE_RAM); __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - ASSERT((STACK_SIZE + HEAP_SIZE) <= 128K, "stack and heap total size larger than 128k") + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/ram.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/ram.ld index 3fa899eae54..3abd1db3322 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/ram.ld +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/ram.ld @@ -5,8 +5,8 @@ ENTRY(_start) -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; +STACK_SIZE = _stack_size; +HEAP_SIZE = _heap_size; MEMORY { @@ -64,13 +64,40 @@ SECTIONS KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; + /* RT-Thread related sections - Start */ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + . = ALIGN(8); PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); } > ILM - .data : AT(etext) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -78,8 +105,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -124,10 +149,12 @@ SECTIONS PROVIDE (edata = .); } > AXI_SRAM - .fast : AT(etext + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) + *(.fast.*) . = ALIGN(8); PROVIDE(__ramfunc_end__ = .); } > ILM @@ -137,11 +164,9 @@ SECTIONS __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -149,13 +174,37 @@ SECTIONS __bss_end__ = .; } > AXI_SRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > AXI_SRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > AXI_SRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -195,6 +244,7 @@ SECTIONS . = ALIGN(8); __stack_base__ = .; . += STACK_SIZE; + . = ALIGN(8); PROVIDE (_stack = .); PROVIDE (_stack_safe = .); } > DLM @@ -204,5 +254,7 @@ SECTIONS __share_mem_start__ = ORIGIN(SHARE_RAM); __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - ASSERT((STACK_SIZE + HEAP_SIZE) <= 128K, "stack and heap total size larger than 128k") + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + __last_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); + ASSERT(((__fw_size__ <= LENGTH(ILM)) && (__last_addr__ <= (ORIGIN(ILM) + LENGTH(ILM)))), "****** FAILED! ILM has not enough space! ******") } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/ram_core1.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/ram_core1.ld index 4417aac7b40..e2e86655ba1 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/ram_core1.ld +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/ram_core1.ld @@ -5,14 +5,14 @@ ENTRY(_start) -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; +STACK_SIZE = _stack_size; +HEAP_SIZE = _heap_size; MEMORY { ILM (wx) : ORIGIN = 0x00020000, LENGTH = 128K DLM (w) : ORIGIN = 0x000A0000, LENGTH = 96K - NONCACHEABLE_RAM (w) : ORIGIN = 0x000B8000, LENGTH = 32K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x000B8000, LENGTH = 32K SHARE_RAM (w) : ORIGIN = 0x010BC000, LENGTH = 16K } @@ -27,6 +27,8 @@ SECTIONS . = ALIGN(8); KEEP(*(.isr_vector)) KEEP(*(.vector_table)) + KEEP(*(.isr_s_vector)) + KEEP(*(.vector_s_table)) . = ALIGN(8); } > ILM @@ -60,13 +62,40 @@ SECTIONS KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; + /* RT-Thread related sections - Start */ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + . = ALIGN(8); PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); } > ILM - .data : AT(etext) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -74,8 +103,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -120,10 +147,12 @@ SECTIONS PROVIDE (edata = .); } > DLM - .fast : AT(etext + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) + *(.fast.*) . = ALIGN(8); PROVIDE(__ramfunc_end__ = .); } > ILM @@ -133,11 +162,9 @@ SECTIONS __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -145,13 +172,37 @@ SECTIONS __bss_end__ = .; } > DLM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > DLM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > DLM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > DLM - .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -197,5 +248,7 @@ SECTIONS __share_mem_start__ = ORIGIN(SHARE_RAM); __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - ASSERT((STACK_SIZE + HEAP_SIZE) <= 256K, "stack and heap total size larger than 256k") + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + __last_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); + ASSERT(((__fw_size__ <= LENGTH(ILM)) && (__last_addr__ <= (ORIGIN(ILM) + LENGTH(ILM)))), "****** FAILED! ILM has not enough space! ******") } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/start.S b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/start.S index a321897e75c..79d7a638ba3 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/start.S +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/start.S @@ -16,6 +16,7 @@ _start: .option push .option norelax la gp, __global_pointer$ + la tp, __thread_pointer$ .option pop /* reset mstatus to 0*/ @@ -34,6 +35,19 @@ _start: la t0, _stack mv sp, t0 +#ifdef CONFIG_NOT_ENABLE_ICACHE + call l1c_ic_disable +#else + call l1c_ic_enable +#endif +#ifdef CONFIG_NOT_ENABLE_DCACHE + call l1c_dc_invalidate_all + call l1c_dc_disable +#else + call l1c_dc_enable + call l1c_dc_invalidate_all +#endif + /* * Initialize LMA/VMA sections. * Relocation for any sections that need to be copied from LMA to VMA. @@ -81,6 +95,14 @@ _start: /* Use mscratch to store isr level */ csrw mscratch, 0 + +#elif defined(CONFIG_RTTHREAD) && CONFIG_RTTHREAD + #define HANDLER_TRAP rtt_risc_v_trap_handler + #define HANDLER_S_TRAP rtt_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 + #else #define HANDLER_TRAP irq_handler_trap #define HANDLER_S_TRAP irq_handler_s_trap diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/reset.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/reset.c index 626e5dec166..9fb2135db6a 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/reset.c +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/reset.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,6 +12,10 @@ extern void system_init(void); +#ifndef MAIN_ENTRY +#define MAIN_ENTRY main +#endif +extern int MAIN_ENTRY(void); __attribute__((weak)) void _clean_up(void) { @@ -30,6 +34,15 @@ __attribute__((weak)) void _clean_up(void) __attribute__((weak)) void c_startup(void) { uint32_t i, size; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __tdata_start__[], __tdata_end__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + extern uint8_t __data_load_addr__[], __tdata_load_addr__[]; + extern uint8_t __fast_load_addr__[], __noncacheable_init_load_addr__[]; + #if defined(FLASH_XIP) || defined(FLASH_UF2) extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; size = __vector_ram_end__ - __vector_ram_start__; @@ -38,13 +51,6 @@ __attribute__((weak)) void c_startup(void) } #endif - extern uint8_t __etext[]; - extern uint8_t __bss_start__[], __bss_end__[]; - extern uint8_t __data_start__[], __data_end__[]; - extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; - extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; - extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; - /* bss section */ size = __bss_end__ - __bss_start__; for (i = 0; i < size; i++) { @@ -60,19 +66,25 @@ __attribute__((weak)) void c_startup(void) /* data section LMA: etext */ size = __data_end__ - __data_start__; for (i = 0; i < size; i++) { - *(__data_start__ + i) = *(__etext + i); + *(__data_start__ + i) = *(__data_load_addr__ + i); } /* ramfunc section LMA: etext + data length */ size = __ramfunc_end__ - __ramfunc_start__; for (i = 0; i < size; i++) { - *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __data_start__) + i); + *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i); } - /* noncacheable init section LMA: etext + data length + ramfunc legnth */ + /* tdata section LMA: etext + data length + ramfunc length */ + size = __tdata_end__ - __tdata_start__; + for (i = 0; i < size; i++) { + *(__tdata_start__ + i) = *(__tdata_load_addr__ + i); + } + + /* noncacheable init section LMA: etext + data length + ramfunc legnth + tdata length*/ size = __noncacheable_init_end__ - __noncacheable_init_start__; for (i = 0; i < size; i++) { - *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __data_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); + *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); } } @@ -85,14 +97,13 @@ __attribute__((weak)) int main(void) __attribute__((weak)) void reset_handler(void) { - l1c_dc_disable(); - l1c_dc_invalidate_all(); + fencei(); /* Call platform specific hardware initialization */ system_init(); /* Entry function */ - main(); + MAIN_ENTRY(); } /* @@ -102,12 +113,46 @@ __attribute__((weak)) void reset_handler(void) */ __attribute__((weak)) void __cxa_atexit(void (*arg1)(void *), void *arg2, void *arg3) { + (void) arg1; + (void) arg2; + (void) arg3; } -#if !defined(__SEGGER_RTL_VERSION) || defined(__riscv_xandes) +#if (!defined(__SEGGER_RTL_VERSION) || defined(__riscv_xandes)) && !defined(__ICCRISCV__) void *__dso_handle = (void *) &__dso_handle; #endif __attribute__((weak)) void _init(void) { } + + +#ifdef __ICCRISCV__ +int __low_level_init(void) +{ +#ifdef IAR_MANUAL_COPY /* Enable this code snippet if the .isr_vector and .vector_table need to be copied to RAM manually */ +#pragma section = ".isr_vector" +#pragma section = ".isr_vector_init" +#pragma section = ".vector_table" +#pragma section = ".vector_table_init" + /* Initialize section .isr_vector, section .vector_table */ + uint8_t *__isr_vector_ram_start = __section_begin(".isr_vector"); + uint32_t __isr_vector_ram_size = __section_size(".isr_vector"); + uint8_t *__isr_vector_rom_start = __section_begin(".isr_vector_init"); + + for (uint32_t i = 0; i < __isr_vector_ram_size; i++) { + __isr_vector_ram_start[i] = __isr_vector_rom_start[i]; + } + + uint8_t *__vector_table_ram_start = __section_begin(".vector_table"); + uint32_t __vector_table_ram_size = __section_size(".vector_table"); + uint8_t *__vector_rom_start = __section_begin(".vector_table_init"); + + for (uint32_t i = 0; i < __vector_table_ram_size; i++) { + __vector_table_ram_start[i] = __vector_rom_start[i]; + } +#endif + + return 1; +} +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash.icf deleted file mode 100644 index 068eed7c42b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash.icf +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region XPI0 = [from 0x80000000 + 0x3000, size _flash_size - 0x3000]; /* XPI0 */ -define region ILM = [from 0x00000000 size 128k]; /* ILM */ -define region DLM = [from 0x00080000 size 128k]; /* DLM */ -define region NONCACHEABLE_RAM = [from 0x01080000 size 128k]; -define region AXI_SRAM = [from 0x010A0000 size 112k]; -define region SHARE_RAM = [from 0x010BC000 size 16k]; -define region AHB_SRAM = [from 0xF0300000 size 32k]; - -assert (__STACKSIZE__ + __HEAPSIZE__) <= 128k with error "stack and heap total size larger than 128k"; - -/* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -/* Initialization */ -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors, block vectors_s }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place at start of XPI0 with fixed order { symbol _start }; -place at start of ILM with fixed order { block vectors, block vectors_s }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { - section .fast, section .fast.* // "ramfunc" section - }; -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash_uf2.icf deleted file mode 100644 index 043a144210a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash_uf2.icf +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -/* Regions */ -define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */ -define region ILM = [from 0x00000000 size 128k]; /* ILM */ -define region DLM = [from 0x00080000 size 128k]; /* DLM */ -define region NONCACHEABLE_RAM = [from 0x01080000 size 128k]; -define region AXI_SRAM = [from 0x010A0000 size 112k]; -define region SHARE_RAM = [from 0x010BC000 size 16k]; -define region AHB_SRAM = [from 0xF0300000 size 32k]; - -assert (__STACKSIZE__ + __HEAPSIZE__) <= 128k with error "stack and heap total size larger than 128k"; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -/* Initialization */ -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors, block vectors_s }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place at start of XPI0 with fixed order { section .uf2_signature }; -place in XPI0 with fixed order { symbol _start }; -place at start of ILM with fixed order { block vectors, block vectors_s }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .uf2_signature }; -keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash_xip.icf deleted file mode 100644 index f252f2a4efd..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash_xip.icf +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region NOR_CFG_OPTION = [ from 0x80000400 size 0xc00 ]; -define region BOOT_HEADER = [ from 0x80001000 size 0x2000 ]; -define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ -define region ILM = [from 0x00000000 size 128k]; /* ILM */ -define region DLM = [from 0x00080000 size 128k]; /* DLM */ -define region NONCACHEABLE_RAM = [from 0x01080000 size 128k]; -define region AXI_SRAM = [from 0x010A0000 size 112k]; -define region SHARE_RAM = [from 0x010BC000 size 16k]; -define region AHB_SRAM = [from 0xF0300000 size 32k]; - -assert (__STACKSIZE__ + __HEAPSIZE__) <= 128k with error "stack and heap total size larger than 128k"; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; -define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; -define exported symbol __app_load_addr__ = start of region XPI0; -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size of block boot_header; -define exported symbol __fw_size__ = 0x1000; - -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -/* Initialization */ -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors, block vectors_s }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER with fixed order { block boot_header }; -place at start of XPI0 with fixed order { symbol _start }; -place at start of ILM with fixed order { block vectors, block vectors_s }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; -keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/ram.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/ram.icf deleted file mode 100644 index c41b4ef3f5b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/ram.icf +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region ILM = [from 0x00000000 size 128k]; /* ILM */ -define region DLM = [from 0x00080000 size 128k]; /* DLM */ -define region NONCACHEABLE_RAM = [from 0x01080000 size 128k]; -define region AXI_SRAM = [from 0x010A0000 size 112k]; -define region SHARE_RAM = [from 0x010BC000 size 16k]; -define region AHB_SRAM = [from 0xF0300000 size 32k]; - -assert (__STACKSIZE__ + __HEAPSIZE__) <= 128k with error "stack and heap total size larger than 128k"; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -/* Initialization */ -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -/* Placement */ -place at start of ILM { symbol _start }; -place in ILM { block vectors, block vectors_s }; // Vector table section -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in ILM with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) // It is intended placing RO here - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/ram_core1.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/ram_core1.icf deleted file mode 100644 index d9d916b3597..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/ram_core1.icf +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region ILM = [from 0x00020000 size 128k]; /* ILM */ -define region DLM = [from 0x000A0000 size 96k]; /* DLM */ -define region NONCACHEABLE_RAM = [from 0x000B8000 size 32k]; /* AXI SRAM1 */ -define region SHARE_RAM = [from 0x010BC000 size 16k]; - -assert (__STACKSIZE__ + __HEAPSIZE__) <= 256k with error "stack and heap total size larger than 256k"; - -/* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block cherryusb_usbh_class_info { section .usbh_class_info }; -define block framebuffer { section .framebuffer }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; - -define exported symbol _stack = end of block stack + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -/* Initialization */ -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -/* Placement */ -place at start of ILM { symbol _start }; -place in ILM { block vectors }; // Vector table section -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in ILM with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in DLM { block cherryusb_usbh_class_info }; -place in DLM { block framebuffer }; -place in DLM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in DLM { section .fast_ram}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/startup.s b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/startup.s deleted file mode 100644 index a88a10bc912..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/startup.s +++ /dev/null @@ -1,392 +0,0 @@ -/********************************************************************* -* SEGGER Microcontroller GmbH * -* The Embedded Experts * -********************************************************************** -* * -* (c) 2014 - 2021 SEGGER Microcontroller GmbH * -* * -* www.segger.com Support: support@segger.com * -* * -********************************************************************** -* * -* All rights reserved. * -* * -* Redistribution and use in source and binary forms, with or * -* without modification, are permitted provided that the following * -* condition is met: * -* * -* - Redistributions of source code must retain the above copyright * -* notice, this condition and the following disclaimer. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * -* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * -* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * -* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * -* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * -* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * -* DAMAGE. * -* * -********************************************************************** - --------------------------- END-OF-HEADER ----------------------------- - -File : SEGGER_RISCV_crt0.s -Purpose : Generic runtime init startup code for RISC-V CPUs. - Designed to work with the SEGGER linker to produce - smallest possible executables. - - This file does not normally require any customization. - -Additional information: - Preprocessor Definitions - FULL_LIBRARY - If defined then - - argc, argv are set up by calling SEGGER_SEMIHOST_GetArgs(). - - the exit symbol is defined and executes on return from main. - - the exit symbol calls destructors, atexit functions and then - calls SEGGER_SEMIHOST_Exit(). - - If not defined then - - argc and argv are not valid (main is assumed to not take parameters) - - the exit symbol is defined, executes on return from main and - halts in a loop. -*/ - -#include "hpm_csr_regs.h" - -/********************************************************************* -* -* Defines, configurable -* -********************************************************************** -*/ -#ifndef APP_ENTRY_POINT - #define APP_ENTRY_POINT reset_handler -#endif - -#ifndef ARGSSPACE - #define ARGSSPACE 128 -#endif - -/********************************************************************* -* -* Macros -* -********************************************************************** -*/ -// -// Declare a label as function symbol (without switching sections) -// -.macro MARK_FUNC Name - .global \Name - .type \Name, function -\Name: -.endm - -// -// Declare a regular function. -// Functions from the startup are placed in the init section. -// -.macro START_FUNC Name - .section .init.\Name, "ax" - .global \Name -#if __riscv_compressed - .balign 2 -#else - .balign 4 -#endif - .type \Name, function -\Name: -.endm - -// -// Declare a weak function -// -.macro WEAK_FUNC Name - .section .init.\Name, "ax", %progbits - .global \Name - .weak \Name -#if __riscv_compressed - .balign 2 -#else - .balign 4 -#endif - .type \Name, function -\Name: -.endm - -// -// Mark the end of a function and calculate its size -// -.macro END_FUNC name - .size \name,.-\name -.endm - -/********************************************************************* -* -* Externals -* -********************************************************************** -*/ - .extern APP_ENTRY_POINT // typically main - -/********************************************************************* -* -* Global functions -* -********************************************************************** -*/ -/********************************************************************* -* -* _start -* -* Function description -* Entry point for the startup code. -* Usually called by the reset handler. -* Performs all initialisation, based on the entries in the -* linker-generated init table, then calls main(). -* It is device independent, so there should not be any need for an -* end-user to modify it. -* -* Additional information -* At this point, the stack pointer should already have been -* initialized -* - by hardware (such as on Cortex-M), -* - by the device-specific reset handler, -* - or by the debugger (such as for RAM Code). -*/ -#undef L -#define L(label) .L_start_##label - -START_FUNC _start - .option push - .option norelax - lui gp, %hi(__global_pointer$) - addi gp, gp, %lo(__global_pointer$) - lui tp, %hi(__thread_pointer$) - addi tp, tp, %lo(__thread_pointer$) - .option pop - - csrw mstatus, zero - csrw mcause, zero - -#ifdef __riscv_flen - /* Enable FPU */ - li t0, CSR_MSTATUS_FS_MASK - csrrs t0, mstatus, t0 - - /* Initialize FCSR */ - fscsr zero -#endif - - lui t0, %hi(__stack_end__) - addi sp, t0, %lo(__stack_end__) - -#ifndef __NO_SYSTEM_INIT - // - // Call _init - // - call _init -#endif - // - // Call linker init functions which in turn performs the following: - // * Perform segment init - // * Perform heap init (if used) - // * Call constructors of global Objects (if any exist) - // - la s0, __SEGGER_init_table__ // Set table pointer to start of initialization table -L(RunInit): - lw a0, (s0) // Get next initialization function from table - add s0, s0, 4 // Increment table pointer to point to function arguments - jalr a0 // Call initialization function - j L(RunInit) - // -MARK_FUNC __SEGGER_init_done - // - // Time to call main(), the application entry point. - // - -#ifndef NO_CLEANUP_AT_START - /* clean up */ - call _clean_up -#endif - -#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS - #define HANDLER_TRAP freertos_risc_v_trap_handler - #define HANDLER_S_TRAP freertos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III - #define HANDLER_TRAP ucos_risc_v_trap_handler - #define HANDLER_S_TRAP ucos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_THREADX) && CONFIG_THREADX - #define HANDLER_TRAP tx_risc_v_trap_handler - #define HANDLER_S_TRAP tx_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#else - #define HANDLER_TRAP irq_handler_trap - #define HANDLER_S_TRAP irq_handler_s_trap -#endif - -#if !defined(USE_NONVECTOR_MODE) - /* Initial machine trap-vector Base */ - la t0, __vector_table - csrw mtvec, t0 - -#if defined (USE_S_MODE_IRQ) - la t0, __vector_s_table - csrw stvec, t0 -#endif - /* Enable vectored external PLIC interrupt */ - csrsi CSR_MMISC_CTL, 2 -#else - /* Initial machine trap-vector Base */ - la t0, HANDLER_TRAP - csrw mtvec, t0 -#if defined (USE_S_MODE_IRQ) - la t0, HANDLER_S_TRAP - csrw stvec, t0 -#endif - - /* Disable vectored external PLIC interrupt */ - csrci CSR_MMISC_CTL, 2 -#endif - -MARK_FUNC start -#ifndef FULL_LIBRARY - // - // In a real embedded application ("Free-standing environment"), - // main() does not get any arguments, - // which means it is not necessary to init a0 and a1. - // - call APP_ENTRY_POINT - tail exit - -END_FUNC _start - // - // end of _start - // Fall-through to exit if main ever returns. - // -MARK_FUNC exit - // - // In a free-standing environment, if returned from application: - // Loop forever. - // - j . - .size exit,.-exit -#else - // - // In a hosted environment, - // we need to load a0 and a1 with argc and argv, in order to handle - // the command line arguments. - // This is required for some programs running under control of a - // debugger, such as automated tests. - // - li a0, ARGSSPACE - la a1, args - call debug_getargs - li a0, ARGSSPACE - la a1, args - - call APP_ENTRY_POINT // Call to application entry point (usually main()) - call exit // Call exit function - j . // If we unexpectedly return from exit, hang. -END_FUNC _start -#endif - -#ifdef FULL_LIBRARY - li a0, ARGSSPACE - la a1, args - call debug_getargs - li a0, ARGSSPACE - la a1, args -#else - li a0, 0 - li a1, 0 -#endif - - call APP_ENTRY_POINT - tail exit - -END_FUNC _start - - // -#ifdef FULL_LIBRARY -/********************************************************************* -* -* exit -* -* Function description -* Exit of the system. -* Called on return from application entry point or explicit call -* to exit. -* -* Additional information -* In a hosted environment exit gracefully, by -* saving the return value, -* calling destructurs of global objects, -* calling registered atexit functions, -* and notifying the host/debugger. -*/ -#undef L -#define L(label) .L_exit_##label - -WEAK_FUNC exit - mv s1, a0 // Save the exit parameter/return result - // - // Call destructors - // - la s0, __dtors_start__ -L(Loop): - la t0, __dtors_end__ - beq s0, t0, L(End) - lw t1, 0(s0) - addi s0, s0, 4 - jalr t1 - j L(Loop) -L(End): - // - // Call atexit functions - // - call _execute_at_exit_fns - // - // Call debug_exit with return result/exit parameter - // - mv a0, s1 - call debug_exit - // - // If execution is not terminated, loop forever - // -L(ExitLoop): - j L(ExitLoop) // Loop forever. -END_FUNC exit -#endif - -#ifdef FULL_LIBRARY - .bss -args: - .space ARGSSPACE - .size args, .-args - .type args, %object -#endif - - .section .isr_vector, "ax" - .weak nmi_handler -nmi_handler: -1: j 1b - -#include "../vectors.h" - -/*************************** End of file ****************************/ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/trap.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/trap.c index 4a38669a365..3df45f565c8 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/trap.c +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -8,6 +8,10 @@ #include "hpm_common.h" #include "hpm_soc.h" +#ifdef __ICCRISCV__ +#pragma language = extended +#endif + /********************** MCAUSE exception types **************************************/ #define MCAUSE_INSTR_ADDR_MISALIGNED (0U) /* !< Instruction Address misaligned */ #define MCAUSE_INSTR_ACCESS_FAULT (1U) /* !< Instruction access fault */ @@ -46,6 +50,11 @@ __attribute__((weak)) void swi_isr(void) __attribute__((weak)) void syscall_handler(long n, long a0, long a1, long a2, long a3) { + (void) n; + (void) a0; + (void) a1; + (void) a2; + (void) a3; } __attribute__((weak)) long exception_handler(long cause, long epc) @@ -88,6 +97,7 @@ __attribute__((weak)) long exception_handler(long cause, long epc) __attribute__((weak)) long exception_s_handler(long cause, long epc) { + (void) cause; return epc; } @@ -99,11 +109,17 @@ __attribute__((weak)) void mchtmr_s_isr(void) { } -#if !defined(CONFIG_FREERTOS) && !defined(CONFIG_UCOS_III) && !defined(CONFIG_THREADX) -void irq_handler_trap(void) __attribute__ ((section(".isr_vector"), interrupt("machine"), aligned(4))); +#if !defined(CONFIG_FREERTOS) && !defined(CONFIG_UCOS_III) && !defined(CONFIG_THREADX) && !defined(CONFIG_RTTHREAD) +HPM_ATTR_MACHINE_INTERRUPT void irq_handler_trap(void); +#define IRQ_HANDLER_TRAP_AS_ISR 1 #else void irq_handler_trap(void) __attribute__ ((section(".isr_vector"))); #endif + +#if defined(__ICCRISCV__) && (IRQ_HANDLER_TRAP_AS_ISR == 1) +extern int __vector_table[]; +HPM_ATTR_MACHINE_INTERRUPT +#endif void irq_handler_trap(void) { long mcause = read_csr(CSR_MCAUSE); @@ -146,11 +162,13 @@ void irq_handler_trap(void) ((isr_func_t)__vector_table[irq_index])(); __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index); } + } #endif else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_SOFT)) { /* Machine SWI interrupt */ + intc_m_claim_swi(); swi_isr(); intc_m_complete_swi(); } else if (!(mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == MCAUSE_ECALL_FROM_MACHINE_MODE)) { @@ -187,11 +205,18 @@ void irq_handler_trap(void) #endif } -#ifndef CONFIG_FREERTOS -void irq_handler_s_trap(void) __attribute__ ((section(".isr_s_vector"), interrupt("supervisor"), aligned(4))); + +#if !defined(CONFIG_FREERTOS) && !defined(CONFIG_UCOS_III) && !defined(CONFIG_THREADX) +HPM_ATTR_SUPERVISOR_INTERRUPT void irq_handler_s_trap(void); +#define IRQ_HANDLER_TRAP_AS_ISR 1 #else void irq_handler_s_trap(void) __attribute__ ((section(".isr_s_vector"))); #endif + +#if defined(__ICCRISCV__) && (IRQ_HANDLER_TRAP_AS_ISR == 1) +extern int __vector_s_table[]; +HPM_ATTR_SUPERVISOR_INTERRUPT +#endif void irq_handler_s_trap(void) { long scause = read_csr(CSR_SCAUSE); diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/vectors.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/vectors.h index e48c61d0fd5..e548d0a0469 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/vectors.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/vectors.h @@ -1,9 +1,222 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ +#ifdef __IAR_SYSTEMS_ASM__ + +IRQ_HANDLER macro + dc32 default_isr_\1 + endm + +IRQ_DEFAULT_HANDLER macro + PUBWEAK default_isr_\1 +default_isr_\1 + j default_irq_handler + endm + + SECTION `.isr_vector`:CODE:ROOT(9) + PUBWEAK default_irq_handler +default_irq_handler + j default_irq_handler + IRQ_DEFAULT_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_DEFAULT_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_DEFAULT_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_DEFAULT_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_DEFAULT_HANDLER 5 /* GPIO0_X IRQ handler */ + IRQ_DEFAULT_HANDLER 6 /* GPIO0_Y IRQ handler */ + IRQ_DEFAULT_HANDLER 7 /* GPIO0_Z IRQ handler */ + IRQ_DEFAULT_HANDLER 8 /* GPIO1_A IRQ handler */ + IRQ_DEFAULT_HANDLER 9 /* GPIO1_B IRQ handler */ + IRQ_DEFAULT_HANDLER 10 /* GPIO1_C IRQ handler */ + IRQ_DEFAULT_HANDLER 11 /* GPIO1_D IRQ handler */ + IRQ_DEFAULT_HANDLER 12 /* GPIO1_X IRQ handler */ + IRQ_DEFAULT_HANDLER 13 /* GPIO1_Y IRQ handler */ + IRQ_DEFAULT_HANDLER 14 /* GPIO1_Z IRQ handler */ + IRQ_DEFAULT_HANDLER 15 /* ADC0 IRQ handler */ + IRQ_DEFAULT_HANDLER 16 /* ADC1 IRQ handler */ + IRQ_DEFAULT_HANDLER 17 /* ADC2 IRQ handler */ + IRQ_DEFAULT_HANDLER 18 /* SDFM IRQ handler */ + IRQ_DEFAULT_HANDLER 19 /* DAC0 IRQ handler */ + IRQ_DEFAULT_HANDLER 20 /* DAC1 IRQ handler */ + IRQ_DEFAULT_HANDLER 21 /* ACMP[0] IRQ handler */ + IRQ_DEFAULT_HANDLER 22 /* ACMP[1] IRQ handler */ + IRQ_DEFAULT_HANDLER 23 /* ACMP[2] IRQ handler */ + IRQ_DEFAULT_HANDLER 24 /* ACMP[3] IRQ handler */ + IRQ_DEFAULT_HANDLER 25 /* SPI0 IRQ handler */ + IRQ_DEFAULT_HANDLER 26 /* SPI1 IRQ handler */ + IRQ_DEFAULT_HANDLER 27 /* SPI2 IRQ handler */ + IRQ_DEFAULT_HANDLER 28 /* SPI3 IRQ handler */ + IRQ_DEFAULT_HANDLER 29 /* UART0 IRQ handler */ + IRQ_DEFAULT_HANDLER 30 /* UART1 IRQ handler */ + IRQ_DEFAULT_HANDLER 31 /* UART2 IRQ handler */ + IRQ_DEFAULT_HANDLER 32 /* UART3 IRQ handler */ + IRQ_DEFAULT_HANDLER 33 /* UART4 IRQ handler */ + IRQ_DEFAULT_HANDLER 34 /* UART5 IRQ handler */ + IRQ_DEFAULT_HANDLER 35 /* UART6 IRQ handler */ + IRQ_DEFAULT_HANDLER 36 /* UART7 IRQ handler */ + IRQ_DEFAULT_HANDLER 37 /* MCAN0 IRQ handler */ + IRQ_DEFAULT_HANDLER 38 /* MCAN1 IRQ handler */ + IRQ_DEFAULT_HANDLER 39 /* MCAN2 IRQ handler */ + IRQ_DEFAULT_HANDLER 40 /* MCAN3 IRQ handler */ + IRQ_DEFAULT_HANDLER 41 /* PTPC IRQ handler */ + IRQ_DEFAULT_HANDLER 42 /* WDG0 IRQ handler */ + IRQ_DEFAULT_HANDLER 43 /* WDG1 IRQ handler */ + IRQ_DEFAULT_HANDLER 44 /* TSNS IRQ handler */ + IRQ_DEFAULT_HANDLER 45 /* MBX0A IRQ handler */ + IRQ_DEFAULT_HANDLER 46 /* MBX0B IRQ handler */ + IRQ_DEFAULT_HANDLER 47 /* MBX1A IRQ handler */ + IRQ_DEFAULT_HANDLER 48 /* MBX1B IRQ handler */ + IRQ_DEFAULT_HANDLER 49 /* GPTMR0 IRQ handler */ + IRQ_DEFAULT_HANDLER 50 /* GPTMR1 IRQ handler */ + IRQ_DEFAULT_HANDLER 51 /* GPTMR2 IRQ handler */ + IRQ_DEFAULT_HANDLER 52 /* GPTMR3 IRQ handler */ + IRQ_DEFAULT_HANDLER 53 /* I2C0 IRQ handler */ + IRQ_DEFAULT_HANDLER 54 /* I2C1 IRQ handler */ + IRQ_DEFAULT_HANDLER 55 /* I2C2 IRQ handler */ + IRQ_DEFAULT_HANDLER 56 /* I2C3 IRQ handler */ + IRQ_DEFAULT_HANDLER 57 /* PWM0 IRQ handler */ + IRQ_DEFAULT_HANDLER 58 /* HALL0 IRQ handler */ + IRQ_DEFAULT_HANDLER 59 /* QEI0 IRQ handler */ + IRQ_DEFAULT_HANDLER 60 /* PWM1 IRQ handler */ + IRQ_DEFAULT_HANDLER 61 /* HALL1 IRQ handler */ + IRQ_DEFAULT_HANDLER 62 /* QEI1 IRQ handler */ + IRQ_DEFAULT_HANDLER 63 /* PWM2 IRQ handler */ + IRQ_DEFAULT_HANDLER 64 /* HALL2 IRQ handler */ + IRQ_DEFAULT_HANDLER 65 /* QEI2 IRQ handler */ + IRQ_DEFAULT_HANDLER 66 /* PWM3 IRQ handler */ + IRQ_DEFAULT_HANDLER 67 /* HALL3 IRQ handler */ + IRQ_DEFAULT_HANDLER 68 /* QEI3 IRQ handler */ + IRQ_DEFAULT_HANDLER 69 /* SDP IRQ handler */ + IRQ_DEFAULT_HANDLER 70 /* XPI0 IRQ handler */ + IRQ_DEFAULT_HANDLER 71 /* XDMA IRQ handler */ + IRQ_DEFAULT_HANDLER 72 /* HDMA IRQ handler */ + IRQ_DEFAULT_HANDLER 73 /* RNG IRQ handler */ + IRQ_DEFAULT_HANDLER 74 /* USB0 IRQ handler */ + IRQ_DEFAULT_HANDLER 75 /* PSEC IRQ handler */ + IRQ_DEFAULT_HANDLER 76 /* PGPIO IRQ handler */ + IRQ_DEFAULT_HANDLER 77 /* PWDG IRQ handler */ + IRQ_DEFAULT_HANDLER 78 /* PTMR IRQ handler */ + IRQ_DEFAULT_HANDLER 79 /* PUART IRQ handler */ + IRQ_DEFAULT_HANDLER 80 /* FUSE IRQ handler */ + IRQ_DEFAULT_HANDLER 81 /* SECMON IRQ handler */ + IRQ_DEFAULT_HANDLER 82 /* RTC IRQ handler */ + IRQ_DEFAULT_HANDLER 83 /* BUTN IRQ handler */ + IRQ_DEFAULT_HANDLER 84 /* BGPIO IRQ handler */ + IRQ_DEFAULT_HANDLER 85 /* BVIO IRQ handler */ + IRQ_DEFAULT_HANDLER 86 /* BROWNOUT IRQ handler */ + IRQ_DEFAULT_HANDLER 87 /* SYSCTL IRQ handler */ + IRQ_DEFAULT_HANDLER 88 /* DEBUG[0] IRQ handler */ + IRQ_DEFAULT_HANDLER 89 /* DEBUG[1] IRQ handler */ + IRQ_DEFAULT_HANDLER 90 /* LIN0 IRQ handler */ + IRQ_DEFAULT_HANDLER 91 /* LIN1 IRQ handler */ + IRQ_DEFAULT_HANDLER 92 /* LIN2 IRQ handler */ + IRQ_DEFAULT_HANDLER 93 /* LIN3 IRQ handler */ + + EXTERN irq_handler_trap + SECTION `.vector_table`:CODE:ROOT(9) + PUBLIC __vector_table + DATA + +__vector_table + dc32 irq_handler_trap + IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_HANDLER 5 /* GPIO0_X IRQ handler */ + IRQ_HANDLER 6 /* GPIO0_Y IRQ handler */ + IRQ_HANDLER 7 /* GPIO0_Z IRQ handler */ + IRQ_HANDLER 8 /* GPIO1_A IRQ handler */ + IRQ_HANDLER 9 /* GPIO1_B IRQ handler */ + IRQ_HANDLER 10 /* GPIO1_C IRQ handler */ + IRQ_HANDLER 11 /* GPIO1_D IRQ handler */ + IRQ_HANDLER 12 /* GPIO1_X IRQ handler */ + IRQ_HANDLER 13 /* GPIO1_Y IRQ handler */ + IRQ_HANDLER 14 /* GPIO1_Z IRQ handler */ + IRQ_HANDLER 15 /* ADC0 IRQ handler */ + IRQ_HANDLER 16 /* ADC1 IRQ handler */ + IRQ_HANDLER 17 /* ADC2 IRQ handler */ + IRQ_HANDLER 18 /* SDFM IRQ handler */ + IRQ_HANDLER 19 /* DAC0 IRQ handler */ + IRQ_HANDLER 20 /* DAC1 IRQ handler */ + IRQ_HANDLER 21 /* ACMP[0] IRQ handler */ + IRQ_HANDLER 22 /* ACMP[1] IRQ handler */ + IRQ_HANDLER 23 /* ACMP[2] IRQ handler */ + IRQ_HANDLER 24 /* ACMP[3] IRQ handler */ + IRQ_HANDLER 25 /* SPI0 IRQ handler */ + IRQ_HANDLER 26 /* SPI1 IRQ handler */ + IRQ_HANDLER 27 /* SPI2 IRQ handler */ + IRQ_HANDLER 28 /* SPI3 IRQ handler */ + IRQ_HANDLER 29 /* UART0 IRQ handler */ + IRQ_HANDLER 30 /* UART1 IRQ handler */ + IRQ_HANDLER 31 /* UART2 IRQ handler */ + IRQ_HANDLER 32 /* UART3 IRQ handler */ + IRQ_HANDLER 33 /* UART4 IRQ handler */ + IRQ_HANDLER 34 /* UART5 IRQ handler */ + IRQ_HANDLER 35 /* UART6 IRQ handler */ + IRQ_HANDLER 36 /* UART7 IRQ handler */ + IRQ_HANDLER 37 /* MCAN0 IRQ handler */ + IRQ_HANDLER 38 /* MCAN1 IRQ handler */ + IRQ_HANDLER 39 /* MCAN2 IRQ handler */ + IRQ_HANDLER 40 /* MCAN3 IRQ handler */ + IRQ_HANDLER 41 /* PTPC IRQ handler */ + IRQ_HANDLER 42 /* WDG0 IRQ handler */ + IRQ_HANDLER 43 /* WDG1 IRQ handler */ + IRQ_HANDLER 44 /* TSNS IRQ handler */ + IRQ_HANDLER 45 /* MBX0A IRQ handler */ + IRQ_HANDLER 46 /* MBX0B IRQ handler */ + IRQ_HANDLER 47 /* MBX1A IRQ handler */ + IRQ_HANDLER 48 /* MBX1B IRQ handler */ + IRQ_HANDLER 49 /* GPTMR0 IRQ handler */ + IRQ_HANDLER 50 /* GPTMR1 IRQ handler */ + IRQ_HANDLER 51 /* GPTMR2 IRQ handler */ + IRQ_HANDLER 52 /* GPTMR3 IRQ handler */ + IRQ_HANDLER 53 /* I2C0 IRQ handler */ + IRQ_HANDLER 54 /* I2C1 IRQ handler */ + IRQ_HANDLER 55 /* I2C2 IRQ handler */ + IRQ_HANDLER 56 /* I2C3 IRQ handler */ + IRQ_HANDLER 57 /* PWM0 IRQ handler */ + IRQ_HANDLER 58 /* HALL0 IRQ handler */ + IRQ_HANDLER 59 /* QEI0 IRQ handler */ + IRQ_HANDLER 60 /* PWM1 IRQ handler */ + IRQ_HANDLER 61 /* HALL1 IRQ handler */ + IRQ_HANDLER 62 /* QEI1 IRQ handler */ + IRQ_HANDLER 63 /* PWM2 IRQ handler */ + IRQ_HANDLER 64 /* HALL2 IRQ handler */ + IRQ_HANDLER 65 /* QEI2 IRQ handler */ + IRQ_HANDLER 66 /* PWM3 IRQ handler */ + IRQ_HANDLER 67 /* HALL3 IRQ handler */ + IRQ_HANDLER 68 /* QEI3 IRQ handler */ + IRQ_HANDLER 69 /* SDP IRQ handler */ + IRQ_HANDLER 70 /* XPI0 IRQ handler */ + IRQ_HANDLER 71 /* XDMA IRQ handler */ + IRQ_HANDLER 72 /* HDMA IRQ handler */ + IRQ_HANDLER 73 /* RNG IRQ handler */ + IRQ_HANDLER 74 /* USB0 IRQ handler */ + IRQ_HANDLER 75 /* PSEC IRQ handler */ + IRQ_HANDLER 76 /* PGPIO IRQ handler */ + IRQ_HANDLER 77 /* PWDG IRQ handler */ + IRQ_HANDLER 78 /* PTMR IRQ handler */ + IRQ_HANDLER 79 /* PUART IRQ handler */ + IRQ_HANDLER 80 /* FUSE IRQ handler */ + IRQ_HANDLER 81 /* SECMON IRQ handler */ + IRQ_HANDLER 82 /* RTC IRQ handler */ + IRQ_HANDLER 83 /* BUTN IRQ handler */ + IRQ_HANDLER 84 /* BGPIO IRQ handler */ + IRQ_HANDLER 85 /* BVIO IRQ handler */ + IRQ_HANDLER 86 /* BROWNOUT IRQ handler */ + IRQ_HANDLER 87 /* SYSCTL IRQ handler */ + IRQ_HANDLER 88 /* DEBUG[0] IRQ handler */ + IRQ_HANDLER 89 /* DEBUG[1] IRQ handler */ + IRQ_HANDLER 90 /* LIN0 IRQ handler */ + IRQ_HANDLER 91 /* LIN1 IRQ handler */ + IRQ_HANDLER 92 /* LIN2 IRQ handler */ + IRQ_HANDLER 93 /* LIN3 IRQ handler */ + +#else + .global default_irq_handler .weak default_irq_handler .align 2 @@ -60,10 +273,10 @@ IRQ_HANDLER 34 /* UART5 IRQ handler */ IRQ_HANDLER 35 /* UART6 IRQ handler */ IRQ_HANDLER 36 /* UART7 IRQ handler */ - IRQ_HANDLER 37 /* CAN0 IRQ handler */ - IRQ_HANDLER 38 /* CAN1 IRQ handler */ - IRQ_HANDLER 39 /* CAN2 IRQ handler */ - IRQ_HANDLER 40 /* CAN3 IRQ handler */ + IRQ_HANDLER 37 /* MCAN0 IRQ handler */ + IRQ_HANDLER 38 /* MCAN1 IRQ handler */ + IRQ_HANDLER 39 /* MCAN2 IRQ handler */ + IRQ_HANDLER 40 /* MCAN3 IRQ handler */ IRQ_HANDLER 41 /* PTPC IRQ handler */ IRQ_HANDLER 42 /* WDG0 IRQ handler */ IRQ_HANDLER 43 /* WDG1 IRQ handler */ @@ -118,6 +331,220 @@ IRQ_HANDLER 92 /* LIN2 IRQ handler */ IRQ_HANDLER 93 /* LIN3 IRQ handler */ +#endif + +#ifdef __IAR_SYSTEMS_ASM__ + +IRQ_S_HANDLER macro + dc32 default_isr_s_\1 + endm + +IRQ_DEFAULT_S_HANDLER macro + PUBWEAK default_isr_s_\1 +default_isr_s_\1 + j default_irq_s_handler + endm + + SECTION `.isr_s_vector`:CODE:ROOT(9) + PUBWEAK default_irq_s_handler +default_irq_s_handler + j default_irq_s_handler + IRQ_DEFAULT_S_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_DEFAULT_S_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_DEFAULT_S_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_DEFAULT_S_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_DEFAULT_S_HANDLER 5 /* GPIO0_X IRQ handler */ + IRQ_DEFAULT_S_HANDLER 6 /* GPIO0_Y IRQ handler */ + IRQ_DEFAULT_S_HANDLER 7 /* GPIO0_Z IRQ handler */ + IRQ_DEFAULT_S_HANDLER 8 /* GPIO1_A IRQ handler */ + IRQ_DEFAULT_S_HANDLER 9 /* GPIO1_B IRQ handler */ + IRQ_DEFAULT_S_HANDLER 10 /* GPIO1_C IRQ handler */ + IRQ_DEFAULT_S_HANDLER 11 /* GPIO1_D IRQ handler */ + IRQ_DEFAULT_S_HANDLER 12 /* GPIO1_X IRQ handler */ + IRQ_DEFAULT_S_HANDLER 13 /* GPIO1_Y IRQ handler */ + IRQ_DEFAULT_S_HANDLER 14 /* GPIO1_Z IRQ handler */ + IRQ_DEFAULT_S_HANDLER 15 /* ADC0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 16 /* ADC1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 17 /* ADC2 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 18 /* SDFM IRQ handler */ + IRQ_DEFAULT_S_HANDLER 19 /* DAC0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 20 /* DAC1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 21 /* ACMP[0] IRQ handler */ + IRQ_DEFAULT_S_HANDLER 22 /* ACMP[1] IRQ handler */ + IRQ_DEFAULT_S_HANDLER 23 /* ACMP[2] IRQ handler */ + IRQ_DEFAULT_S_HANDLER 24 /* ACMP[3] IRQ handler */ + IRQ_DEFAULT_S_HANDLER 25 /* SPI0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 26 /* SPI1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 27 /* SPI2 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 28 /* SPI3 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 29 /* UART0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 30 /* UART1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 31 /* UART2 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 32 /* UART3 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 33 /* UART4 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 34 /* UART5 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 35 /* UART6 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 36 /* UART7 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 37 /* MCAN0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 38 /* MCAN1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 39 /* MCAN2 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 40 /* MCAN3 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 41 /* PTPC IRQ handler */ + IRQ_DEFAULT_S_HANDLER 42 /* WDG0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 43 /* WDG1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 44 /* TSNS IRQ handler */ + IRQ_DEFAULT_S_HANDLER 45 /* MBX0A IRQ handler */ + IRQ_DEFAULT_S_HANDLER 46 /* MBX0B IRQ handler */ + IRQ_DEFAULT_S_HANDLER 47 /* MBX1A IRQ handler */ + IRQ_DEFAULT_S_HANDLER 48 /* MBX1B IRQ handler */ + IRQ_DEFAULT_S_HANDLER 49 /* GPTMR0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 50 /* GPTMR1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 51 /* GPTMR2 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 52 /* GPTMR3 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 53 /* I2C0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 54 /* I2C1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 55 /* I2C2 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 56 /* I2C3 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 57 /* PWM0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 58 /* HALL0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 59 /* QEI0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 60 /* PWM1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 61 /* HALL1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 62 /* QEI1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 63 /* PWM2 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 64 /* HALL2 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 65 /* QEI2 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 66 /* PWM3 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 67 /* HALL3 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 68 /* QEI3 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 69 /* SDP IRQ handler */ + IRQ_DEFAULT_S_HANDLER 70 /* XPI0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 71 /* XDMA IRQ handler */ + IRQ_DEFAULT_S_HANDLER 72 /* HDMA IRQ handler */ + IRQ_DEFAULT_S_HANDLER 73 /* RNG IRQ handler */ + IRQ_DEFAULT_S_HANDLER 74 /* USB0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 75 /* PSEC IRQ handler */ + IRQ_DEFAULT_S_HANDLER 76 /* PGPIO IRQ handler */ + IRQ_DEFAULT_S_HANDLER 77 /* PWDG IRQ handler */ + IRQ_DEFAULT_S_HANDLER 78 /* PTMR IRQ handler */ + IRQ_DEFAULT_S_HANDLER 79 /* PUART IRQ handler */ + IRQ_DEFAULT_S_HANDLER 80 /* FUSE IRQ handler */ + IRQ_DEFAULT_S_HANDLER 81 /* SECMON IRQ handler */ + IRQ_DEFAULT_S_HANDLER 82 /* RTC IRQ handler */ + IRQ_DEFAULT_S_HANDLER 83 /* BUTN IRQ handler */ + IRQ_DEFAULT_S_HANDLER 84 /* BGPIO IRQ handler */ + IRQ_DEFAULT_S_HANDLER 85 /* BVIO IRQ handler */ + IRQ_DEFAULT_S_HANDLER 86 /* BROWNOUT IRQ handler */ + IRQ_DEFAULT_S_HANDLER 87 /* SYSCTL IRQ handler */ + IRQ_DEFAULT_S_HANDLER 88 /* DEBUG[0] IRQ handler */ + IRQ_DEFAULT_S_HANDLER 89 /* DEBUG[1] IRQ handler */ + IRQ_DEFAULT_S_HANDLER 90 /* LIN0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 91 /* LIN1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 92 /* LIN2 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 93 /* LIN3 IRQ handler */ + + EXTERN irq_handler_s_trap + SECTION `.vector_s_table`:CODE:ROOT(9) + PUBLIC __vector_s_table + DATA + +__vector_s_table + dc32 irq_handler_s_trap + IRQ_S_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_S_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_S_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_S_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_S_HANDLER 5 /* GPIO0_X IRQ handler */ + IRQ_S_HANDLER 6 /* GPIO0_Y IRQ handler */ + IRQ_S_HANDLER 7 /* GPIO0_Z IRQ handler */ + IRQ_S_HANDLER 8 /* GPIO1_A IRQ handler */ + IRQ_S_HANDLER 9 /* GPIO1_B IRQ handler */ + IRQ_S_HANDLER 10 /* GPIO1_C IRQ handler */ + IRQ_S_HANDLER 11 /* GPIO1_D IRQ handler */ + IRQ_S_HANDLER 12 /* GPIO1_X IRQ handler */ + IRQ_S_HANDLER 13 /* GPIO1_Y IRQ handler */ + IRQ_S_HANDLER 14 /* GPIO1_Z IRQ handler */ + IRQ_S_HANDLER 15 /* ADC0 IRQ handler */ + IRQ_S_HANDLER 16 /* ADC1 IRQ handler */ + IRQ_S_HANDLER 17 /* ADC2 IRQ handler */ + IRQ_S_HANDLER 18 /* SDFM IRQ handler */ + IRQ_S_HANDLER 19 /* DAC0 IRQ handler */ + IRQ_S_HANDLER 20 /* DAC1 IRQ handler */ + IRQ_S_HANDLER 21 /* ACMP[0] IRQ handler */ + IRQ_S_HANDLER 22 /* ACMP[1] IRQ handler */ + IRQ_S_HANDLER 23 /* ACMP[2] IRQ handler */ + IRQ_S_HANDLER 24 /* ACMP[3] IRQ handler */ + IRQ_S_HANDLER 25 /* SPI0 IRQ handler */ + IRQ_S_HANDLER 26 /* SPI1 IRQ handler */ + IRQ_S_HANDLER 27 /* SPI2 IRQ handler */ + IRQ_S_HANDLER 28 /* SPI3 IRQ handler */ + IRQ_S_HANDLER 29 /* UART0 IRQ handler */ + IRQ_S_HANDLER 30 /* UART1 IRQ handler */ + IRQ_S_HANDLER 31 /* UART2 IRQ handler */ + IRQ_S_HANDLER 32 /* UART3 IRQ handler */ + IRQ_S_HANDLER 33 /* UART4 IRQ handler */ + IRQ_S_HANDLER 34 /* UART5 IRQ handler */ + IRQ_S_HANDLER 35 /* UART6 IRQ handler */ + IRQ_S_HANDLER 36 /* UART7 IRQ handler */ + IRQ_S_HANDLER 37 /* MCAN0 IRQ handler */ + IRQ_S_HANDLER 38 /* MCAN1 IRQ handler */ + IRQ_S_HANDLER 39 /* MCAN2 IRQ handler */ + IRQ_S_HANDLER 40 /* MCAN3 IRQ handler */ + IRQ_S_HANDLER 41 /* PTPC IRQ handler */ + IRQ_S_HANDLER 42 /* WDG0 IRQ handler */ + IRQ_S_HANDLER 43 /* WDG1 IRQ handler */ + IRQ_S_HANDLER 44 /* TSNS IRQ handler */ + IRQ_S_HANDLER 45 /* MBX0A IRQ handler */ + IRQ_S_HANDLER 46 /* MBX0B IRQ handler */ + IRQ_S_HANDLER 47 /* MBX1A IRQ handler */ + IRQ_S_HANDLER 48 /* MBX1B IRQ handler */ + IRQ_S_HANDLER 49 /* GPTMR0 IRQ handler */ + IRQ_S_HANDLER 50 /* GPTMR1 IRQ handler */ + IRQ_S_HANDLER 51 /* GPTMR2 IRQ handler */ + IRQ_S_HANDLER 52 /* GPTMR3 IRQ handler */ + IRQ_S_HANDLER 53 /* I2C0 IRQ handler */ + IRQ_S_HANDLER 54 /* I2C1 IRQ handler */ + IRQ_S_HANDLER 55 /* I2C2 IRQ handler */ + IRQ_S_HANDLER 56 /* I2C3 IRQ handler */ + IRQ_S_HANDLER 57 /* PWM0 IRQ handler */ + IRQ_S_HANDLER 58 /* HALL0 IRQ handler */ + IRQ_S_HANDLER 59 /* QEI0 IRQ handler */ + IRQ_S_HANDLER 60 /* PWM1 IRQ handler */ + IRQ_S_HANDLER 61 /* HALL1 IRQ handler */ + IRQ_S_HANDLER 62 /* QEI1 IRQ handler */ + IRQ_S_HANDLER 63 /* PWM2 IRQ handler */ + IRQ_S_HANDLER 64 /* HALL2 IRQ handler */ + IRQ_S_HANDLER 65 /* QEI2 IRQ handler */ + IRQ_S_HANDLER 66 /* PWM3 IRQ handler */ + IRQ_S_HANDLER 67 /* HALL3 IRQ handler */ + IRQ_S_HANDLER 68 /* QEI3 IRQ handler */ + IRQ_S_HANDLER 69 /* SDP IRQ handler */ + IRQ_S_HANDLER 70 /* XPI0 IRQ handler */ + IRQ_S_HANDLER 71 /* XDMA IRQ handler */ + IRQ_S_HANDLER 72 /* HDMA IRQ handler */ + IRQ_S_HANDLER 73 /* RNG IRQ handler */ + IRQ_S_HANDLER 74 /* USB0 IRQ handler */ + IRQ_S_HANDLER 75 /* PSEC IRQ handler */ + IRQ_S_HANDLER 76 /* PGPIO IRQ handler */ + IRQ_S_HANDLER 77 /* PWDG IRQ handler */ + IRQ_S_HANDLER 78 /* PTMR IRQ handler */ + IRQ_S_HANDLER 79 /* PUART IRQ handler */ + IRQ_S_HANDLER 80 /* FUSE IRQ handler */ + IRQ_S_HANDLER 81 /* SECMON IRQ handler */ + IRQ_S_HANDLER 82 /* RTC IRQ handler */ + IRQ_S_HANDLER 83 /* BUTN IRQ handler */ + IRQ_S_HANDLER 84 /* BGPIO IRQ handler */ + IRQ_S_HANDLER 85 /* BVIO IRQ handler */ + IRQ_S_HANDLER 86 /* BROWNOUT IRQ handler */ + IRQ_S_HANDLER 87 /* SYSCTL IRQ handler */ + IRQ_S_HANDLER 88 /* DEBUG[0] IRQ handler */ + IRQ_S_HANDLER 89 /* DEBUG[1] IRQ handler */ + IRQ_S_HANDLER 90 /* LIN0 IRQ handler */ + IRQ_S_HANDLER 91 /* LIN1 IRQ handler */ + IRQ_S_HANDLER 92 /* LIN2 IRQ handler */ + IRQ_S_HANDLER 93 /* LIN3 IRQ handler */ + +#else .global default_irq_s_handler .weak default_irq_s_handler @@ -175,10 +602,10 @@ IRQ_S_HANDLER 34 /* UART5 IRQ handler */ IRQ_S_HANDLER 35 /* UART6 IRQ handler */ IRQ_S_HANDLER 36 /* UART7 IRQ handler */ - IRQ_S_HANDLER 37 /* CAN0 IRQ handler */ - IRQ_S_HANDLER 38 /* CAN1 IRQ handler */ - IRQ_S_HANDLER 39 /* CAN2 IRQ handler */ - IRQ_S_HANDLER 40 /* CAN3 IRQ handler */ + IRQ_S_HANDLER 37 /* MCAN0 IRQ handler */ + IRQ_S_HANDLER 38 /* MCAN1 IRQ handler */ + IRQ_S_HANDLER 39 /* MCAN2 IRQ handler */ + IRQ_S_HANDLER 40 /* MCAN3 IRQ handler */ IRQ_S_HANDLER 41 /* PTPC IRQ handler */ IRQ_S_HANDLER 42 /* WDG0 IRQ handler */ IRQ_S_HANDLER 43 /* WDG1 IRQ handler */ @@ -232,3 +659,5 @@ IRQ_S_HANDLER 91 /* LIN1 IRQ handler */ IRQ_S_HANDLER 92 /* LIN2 IRQ handler */ IRQ_S_HANDLER 93 /* LIN3 IRQ handler */ + +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/HPM6360_svd.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/HPM6360_svd.xml new file mode 100644 index 00000000000..ad79c4503ea --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/HPM6360_svd.xml @@ -0,0 +1,30387 @@ + + + HPMICRO + HPM6360 + HPM6300 + 1.0 + HPM6300 device + + /* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + + + other + r0p0 + little + false + true + true + 7 + false + + + + 8 + 32 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + + + FGPIO + FGPIO + GPIO + 0xc0000 + + 0x0 + 0x824 + registers + + + + 16 + 0x10 + gpioa,gpiob,gpioc,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + DI[%s] + no description available + 0x0 + + VALUE + GPIO input value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-only + + + + + + 16 + 0x10 + gpioa,gpiob,gpioc,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + DO[%s] + no description available + 0x100 + + VALUE + GPIO output value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + SET + GPIO output set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + CLEAR + GPIO output clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + TOGGLE + GPIO output toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + + 16 + 0x10 + gpioa,gpiob,gpioc,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + OE[%s] + no description available + 0x200 + + VALUE + GPIO direction value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + SET + GPIO direction set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + CLEAR + GPIO direction clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + TOGGLE + GPIO direction toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + + 16 + 0x10 + gpioa,gpiob,gpioc,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + IF[%s] + no description available + 0x300 + + VALUE + GPIO interrupt flag value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + write-only + + + + + + 16 + 0x10 + gpioa,gpiob,gpioc,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + IE[%s] + no description available + 0x400 + + VALUE + GPIO interrupt enable value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + SET + GPIO interrupt enable set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + CLEAR + GPIO interrupt enable clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + TOGGLE + GPIO interrupt enable toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + + 16 + 0x10 + gpioa,gpiob,gpioc,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + PL[%s] + no description available + 0x500 + + VALUE + GPIO interrupt polarity value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + SET + GPIO interrupt polarity set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + CLEAR + GPIO interrupt polarity clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + TOGGLE + GPIO interrupt polarity toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + + 16 + 0x10 + gpioa,gpiob,gpioc,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + TP[%s] + no description available + 0x600 + + VALUE + GPIO interrupt type value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + SET + GPIO interrupt type set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + CLEAR + GPIO interrupt type clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TOGGLE + GPIO interrupt type toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + + 16 + 0x10 + gpioa,gpiob,gpioc,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + AS[%s] + no description available + 0x700 + + VALUE + GPIO interrupt asynchronous value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + SET + GPIO interrupt asynchronous set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + CLEAR + GPIO interrupt asynchronous clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + TOGGLE + GPIO interrupt asynchronous toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + + + + GPIO0 + GPIO0 + GPIO + 0xf0000000 + + + PGPIO + PGPIO + GPIO + 0xf40dc000 + + + BGPIO + BGPIO + GPIO + 0xf5014000 + + + PLIC + PLIC + PLIC + 0xe4000000 + + 0x0 + 0x202000 + registers + + + + feature + Feature enable register + 0x0 + 32 + 0x00000000 + 0x00000003 + + + VECTORED + Vector mode enable +0: Disabled +1: Enabled + 1 + 1 + read-write + + + PREEMPT + Preemptive priority interrupt enable +0: Disabled +1: Enabled + 0 + 1 + read-write + + + + + 127 + 0x4 + PRIORITY1,PRIORITY2,PRIORITY3,PRIORITY4,PRIORITY5,PRIORITY6,PRIORITY7,PRIORITY8,PRIORITY9,PRIORITY10,PRIORITY11,PRIORITY12,PRIORITY13,PRIORITY14,PRIORITY15,PRIORITY16,PRIORITY17,PRIORITY18,PRIORITY19,PRIORITY20,PRIORITY21,PRIORITY22,PRIORITY23,PRIORITY24,PRIORITY25,PRIORITY26,PRIORITY27,PRIORITY28,PRIORITY29,PRIORITY30,PRIORITY31,PRIORITY32,PRIORITY33,PRIORITY34,PRIORITY35,PRIORITY36,PRIORITY37,PRIORITY38,PRIORITY39,PRIORITY40,PRIORITY41,PRIORITY42,PRIORITY43,PRIORITY44,PRIORITY45,PRIORITY46,PRIORITY47,PRIORITY48,PRIORITY49,PRIORITY50,PRIORITY51,PRIORITY52,PRIORITY53,PRIORITY54,PRIORITY55,PRIORITY56,PRIORITY57,PRIORITY58,PRIORITY59,PRIORITY60,PRIORITY61,PRIORITY62,PRIORITY63,PRIORITY64,PRIORITY65,PRIORITY66,PRIORITY67,PRIORITY68,PRIORITY69,PRIORITY70,PRIORITY71,PRIORITY72,PRIORITY73,PRIORITY74,PRIORITY75,PRIORITY76,PRIORITY77,PRIORITY78,PRIORITY79,PRIORITY80,PRIORITY81,PRIORITY82,PRIORITY83,PRIORITY84,PRIORITY85,PRIORITY86,PRIORITY87,PRIORITY88,PRIORITY89,PRIORITY90,PRIORITY91,PRIORITY92,PRIORITY93,PRIORITY94,PRIORITY95,PRIORITY96,PRIORITY97,PRIORITY98,PRIORITY99,PRIORITY100,PRIORITY101,PRIORITY102,PRIORITY103,PRIORITY104,PRIORITY105,PRIORITY106,PRIORITY107,PRIORITY108,PRIORITY109,PRIORITY110,PRIORITY111,PRIORITY112,PRIORITY113,PRIORITY114,PRIORITY115,PRIORITY116,PRIORITY117,PRIORITY118,PRIORITY119,PRIORITY120,PRIORITY121,PRIORITY122,PRIORITY123,PRIORITY124,PRIORITY125,PRIORITY126,PRIORITY127 + PRIORITY[%s] + no description available + 0x4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + 4 + 0x4 + PENDING0,PENDING1,PENDING2,PENDING3 + PENDING[%s] + no description available + 0x1000 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + 4 + 0x4 + TRIGGER0,TRIGGER1,TRIGGER2,TRIGGER3 + TRIGGER[%s] + no description available + 0x1080 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. +0: Level-triggered interrupt +1: Edge-triggered interrupt + 0 + 32 + read-only + + + + + NUMBER + Number of supported interrupt sources and targets + 0x1100 + 32 + 0xFFFFFFFF + + + NUM_TARGET + The number of supported targets + 16 + 16 + read-only + + + NUM_INTERRUPT + The number of supported interrupt sources + 0 + 16 + read-only + + + + + INFO + Version and the maximum priority + 0x1104 + 32 + 0xFFFFFFFF + + + MAX_PRIORITY + The maximum priority supported + 16 + 16 + read-only + + + VERSION + The version of the PLIC design + 0 + 16 + read-only + + + + + 2 + 0x80 + target0,target1 + TARGETINT[%s] + no description available + 0x2000 + + 4 + 0x4 + INTEN0,INTEN1,INTEN2,INTEN3 + INTEN[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + + 2 + 0x1000 + target0,target1 + TARGETCONFIG[%s] + no description available + 0x200000 + + THRESHOLD + Target0 priority threshold + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + THRESHOLD + Interrupt priority threshold. + 0 + 32 + read-write + + + + + CLAIM + Target claim and complete + 0x4 + 32 + 0x00000000 + 0x000003FF + + + INTERRUPT_ID + On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). + 0 + 10 + read-write + + + + + PPS + Preempted priority stack + 0x400 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY_PREEMPTED + Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. + 0 + 32 + read-write + + + + + + + + MCHTMR + MCHTMR + MCHTMR + 0xe6000000 + + 0x0 + 0x10 + registers + + + + MTIME + Machine Time + 0x0 + 64 + 0x0000000000020210 + 0xFFFFFFFFFFFFFFFF + + + MTIME + Machine time + 0 + 64 + read-write + + + + + MTIMECMP + Machine Time Compare + 0x8 + 64 + 0x0000000000020210 + 0xFFFFFFFFFFFFFFFF + + + MTIMECMP + Machine time compare + 0 + 64 + read-write + + + + + + + PLICSW + PLICSW + PLIC_SW + 0xe6400000 + + 0x1000 + 0x1ff008 + registers + + + + PENDING + Pending status + 0x1000 + 32 + 0x00000000 + 0x00000002 + + + INTERRUPT + writing 1 to trigger software interrupt + 1 + 1 + read-write + + + + + INTEN + Interrupt enable + 0x2000 + 32 + 0x00000000 + 0x00000001 + + + INTERRUPT + enable software interrupt + 0 + 1 + read-write + + + + + CLAIM + Claim and complete. + 0x200004 + 32 + 0x00000000 + 0x00000001 + + + INTERRUPT_ID + On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). + 0 + 1 + read-write + + + + + + + GPIOM + GPIOM + GPIOM + 0xf0008000 + + 0x0 + 0x800 + registers + + + + 16 + 0x80 + gpioa,gpiob,gpioc,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + ASSIGN[%s] + no description available + 0x0 + + 32 + 0x4 + PIN00,PIN01,PIN02,PIN03,PIN04,PIN05,PIN06,PIN07,PIN08,PIN09,PIN10,PIN11,PIN12,PIN13,PIN14,PIN15,PIN16,PIN17,PIN18,PIN19,PIN20,PIN21,PIN22,PIN23,PIN24,PIN25,PIN26,PIN27,PIN28,PIN29,PIN30,PIN31 + PIN[%s] + no description available + 0x0 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + + + + ADC0 + ADC0 + ADC16 + 0xf0010000 + + 0x0 + 0x1464 + registers + + + + 12 + 0x4 + trg0a,trg0b,trg0c,trg1a,trg1b,trg1c,trg2a,trg2b,trg2c,trg3a,trg3b,trg3c + CONFIG[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFF3F3F7F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interrupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interrupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interrupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + QUEUE_EN + preemption queue enable control + 6 + 1 + read-write + + + INTEN0 + interrupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + trg_dma_addr + No description available + 0x30 + 32 + 0x00000000 + 0xFFFFFFFC + + + TRG_DMA_ADDR + buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) + 2 + 30 + read-write + + + + + trg_sw_sta + No description available + 0x34 + 32 + 0x00000000 + 0x0000001F + + + TRG_SW_STA + SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it. + 4 + 1 + read-write + + + TRIG_SW_INDEX + which trigger for the SW trigger +0 for trig0a, 1 for trig0b… +3 for trig1a, …11 for trig3c + 0 + 4 + read-write + + + + + 16 + 0x4 + chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 + BUS_RESULT[%s] + no description available + 0x400 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + buf_cfg0 + No description available + 0x500 + 32 + 0x00000000 + 0x00000001 + + + WAIT_DIS + set to disable read waiting, get result immediately but maybe not current conversion result. + 0 + 1 + read-write + + + + + seq_cfg0 + No description available + 0x800 + 32 + 0x00000000 + 0x80000F1F + + + CYCLE + current dma write cycle bit + 31 + 1 + read-only + + + SEQ_LEN + sequence queue length, 0 for one, 0xF for 16 + 8 + 4 + read-write + + + RESTART_EN + if set together with cont_en, HW will continue process the whole queue after trigger once. +If cont_en is 0, this bit is not used + 4 + 1 + read-write + + + CONT_EN + if set, HW will continue process the queue till end(seq_len) after trigger once + 3 + 1 + read-write + + + SW_TRIG + SW trigger, pulse signal, cleared by HW one cycle later + 2 + 1 + write-only + + + SW_TRIG_EN + set to enable SW trigger + 1 + 1 + read-write + + + HW_TRIG_EN + set to enable external HW trigger, only trigger on posedge + 0 + 1 + read-write + + + + + seq_dma_addr + No description available + 0x804 + 32 + 0x00000000 + 0xFFFFFFFC + + + TAR_ADDR + dma target address, should be 4-byte aligned + 2 + 30 + read-write + + + + + seq_dma_cfg + No description available + 0x80c + 32 + 0x00000000 + 0x0FFF3FFF + + + STOP_POS + if stop_en is set, SW is responsible to update this field to the next read point, HW should not write data to this point since it's not read out by SW yet + 16 + 12 + read-write + + + DMA_RST + set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. +SW should clear all cycle bit in buffer to 0 before clear dma_rst + 13 + 1 + read-write + + + STOP_EN + set to stop dma if reach the stop_pos + 12 + 1 + read-write + + + BUF_LEN + dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 +0 for 4byte; +0xFFF for 16kbyte. + 0 + 12 + read-write + + + + + 16 + 0x4 + cfg0,cfg1,cfg2,cfg3,cfg4,cfg5,cfg6,cfg7,cfg8,cfg9,cfg10,cfg11,cfg12,cfg13,cfg14,cfg15 + SEQ_QUE[%s] + no description available + 0x810 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + 16 + 0x10 + chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 + PRD_CFG[%s] + no description available + 0xc00 + + prd_cfg + No description available + 0x0 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + prd_thshd_cfg + No description available + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + prd_result + No description available + 0x8 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + + 16 + 0x4 + chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 + SAMPLE_CFG[%s] + no description available + 0x1000 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + conv_cfg1 + No description available + 0x1104 + 32 + 0x00000000 + 0x000001FF + + + CONVERT_CLOCK_NUMBER + convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider); +user can use small value to get faster conversion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. +Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC conversion(plus sample) need 25 cycles(50MHz). + 4 + 5 + read-write + + + CLOCK_DIVIDER + clock_period, N half clock cycle per half adc cycle +0 for same adc_clk and bus_clk, +1 for 1:2, +2 for 1:3, +... +15 for 1:16 +Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk + 0 + 4 + read-write + + + + + adc_cfg0 + No description available + 0x1108 + 32 + 0x00000000 + 0xA0000001 + + + SEL_SYNC_AHB + set to 1 will enable sync AHB bus, to get better bus performance. +Adc_clk must to be set to same as bus clock at this mode + 31 + 1 + read-write + + + ADC_AHB_EN + set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; + 29 + 1 + read-write + + + PORT3_REALTIME + set to enable trg queue stop other queues + 0 + 1 + read-write + + + + + int_sts + No description available + 0x1110 + 32 + 0x00000000 + 0xFFE0FFFF + + + TRIG_CMPT + interrupt for one trigger conversion complete if enabled + 31 + 1 + read-write + + + TRIG_SW_CFLCT + No description available + 30 + 1 + read-write + + + TRIG_HW_CFLCT + No description available + 29 + 1 + read-write + + + READ_CFLCT + read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel + 28 + 1 + read-write + + + SEQ_SW_CFLCT + sequence queue conflict interrupt, set if HW or SW trigger received during conversion + 27 + 1 + read-write + + + SEQ_HW_CFLCT + No description available + 26 + 1 + read-write + + + SEQ_DMAABT + dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set + 25 + 1 + read-write + + + SEQ_CMPT + the whole sequence complete interrupt + 24 + 1 + read-write + + + SEQ_CVC + one conversion complete in seq_queue if related seq_int_en is set + 23 + 1 + read-write + + + DMA_FIFO_FULL + DMA fifo full interrupt, user need to check clock frequency if it's set. + 22 + 1 + read-write + + + AHB_ERR + set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr + 21 + 1 + read-write + + + WDOG + set if one chanel watch dog event triggered + 0 + 16 + read-write + + + + + int_en + No description available + 0x1114 + 32 + 0x00000000 + 0xFFE0FFFF + + + TRIG_CMPT + interrupt for one trigger conversion complete if enabled + 31 + 1 + read-write + + + TRIG_SW_CFLCT + No description available + 30 + 1 + read-write + + + TRIG_HW_CFLCT + No description available + 29 + 1 + read-write + + + READ_CFLCT + read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel + 28 + 1 + read-write + + + SEQ_SW_CFLCT + sequence queue conflict interrupt, set if HW or SW trigger received during conversion + 27 + 1 + read-write + + + SEQ_HW_CFLCT + No description available + 26 + 1 + read-write + + + SEQ_DMAABT + dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set + 25 + 1 + read-write + + + SEQ_CMPT + the whole sequence complete interrupt + 24 + 1 + read-write + + + SEQ_CVC + one conversion complete in seq_queue if related seq_int_en is set + 23 + 1 + read-write + + + DMA_FIFO_FULL + DMA fifo full interrupt, user need to check clock frequency if it's set. + 22 + 1 + read-write + + + AHB_ERR + set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr + 21 + 1 + read-write + + + WDOG + set if one chanel watch dog event triggered + 0 + 16 + read-write + + + + + ana_ctrl0 + No description available + 0x1200 + 32 + 0x00000000 + 0x00001004 + + + ADC_CLK_ON + set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. +MUST set clock_period to 0 or 1 for adc16 reg access + 12 + 1 + read-write + + + STARTCAL + set to start the offset calibration cycle (Active H). user need to clear it after setting it. + 2 + 1 + read-write + + + + + ana_status + No description available + 0x1210 + 32 + 0x00000000 + 0x00000080 + + + CALON + Indicates if the ADC is in calibration mode (Active H). + 7 + 1 + read-write + + + + + 34 + 0x2 + adc16_para00,adc16_para01,adc16_para02,adc16_para03,adc16_para04,adc16_para05,adc16_para06,adc16_para07,adc16_para08,adc16_para09,adc16_para10,adc16_para11,adc16_para12,adc16_para13,adc16_para14,adc16_para15,adc16_para16,adc16_para17,adc16_para18,adc16_para19,adc16_para20,adc16_para21,adc16_para22,adc16_para23,adc16_para24,adc16_para25,adc16_para26,adc16_para27,adc16_para28,adc16_para29,adc16_para30,adc16_para31,adc16_para32,adc16_para33 + ADC16_PARAMS[%s] + no description available + 0x1400 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description available + 0 + 16 + read-write + + + + + adc16_config0 + No description available + 0x1444 + 32 + 0x00000000 + 0x01F07FFF + + + REG_EN + set to enable regulator + 24 + 1 + read-write + + + BANDGAP_EN + set to enable bandgap. user should set reg_en and bandgap_en before use adc16. + 23 + 1 + read-write + + + CAL_AVG_CFG + for average the calibration result. +0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; +4- 16 loops; 5-32 loops; others reserved + 20 + 3 + read-write + + + PREEMPT_EN + set to enable preemption feature + 14 + 1 + read-write + + + CONV_PARAM + conversion parameter + 0 + 14 + read-write + + + + + adc16_config1 + No description available + 0x1460 + 32 + 0x00000000 + 0x00001F00 + + + COV_END_CNT + used for faster conversion, user can change it to get higher convert speed(but less accuracy). +should set to (21-convert_clock_number+1). + 8 + 5 + read-write + + + + + + + ADC1 + ADC1 + ADC16 + 0xf0014000 + + + ADC2 + ADC2 + ADC16 + 0xf0018000 + + + ACMP + ACMP + ACMP + 0xf0020000 + + 0x0 + 0x80 + registers + + + + 4 + 0x20 + chn0,chn1,chn2,chn3 + CHANNEL[%s] + no description available + 0x0 + + cfg + Configure Register + 0x0 + 32 + 0x00000000 + 0xFF7FFFFF + + + HYST + This bitfield configure the comparator hysteresis. +00: Hysteresis level 0 +01: Hysteresis level 1 +10: Hysteresis level 2 +11: Hysteresis level 3 + 30 + 2 + read-write + + + DACEN + This bit enable the comparator internal DAC +0: DAC disabled +1: DAC enabled + 29 + 1 + read-write + + + HPMODE + This bit enable the comparator high performance mode. +0: HP mode disabled +1: HP mode enabled + 28 + 1 + read-write + + + CMPEN + This bit enable the comparator. +0: ACMP disabled +1: ACMP enabled + 27 + 1 + read-write + + + MINSEL + PIN select, from pad_ai_acmp[7:1] and dac_out + 24 + 3 + read-write + + + PINSEL + MIN select, from pad_ai_acmp[7:1] and dac_out + 20 + 3 + read-write + + + CMPOEN + This bit enable the comparator output on pad. +0: ACMP output disabled +1: ACMP output enabled + 19 + 1 + read-write + + + FLTBYPS + This bit bypass the comparator output digital filter. +0: The ACMP output need pass digital filter +1: The ACMP output digital filter is bypassed. + 18 + 1 + read-write + + + WINEN + This bit enable the comparator window mode. +0: Window mode is disabled +1: Window mode is enabled + 17 + 1 + read-write + + + OPOL + The output polarity control bit. +0: The ACMP output remain un-changed. +1: The ACMP output is inverted. + 16 + 1 + read-write + + + FLTMODE + This bitfield define the ACMP output digital filter mode: +000-bypass +100-change immediately; +101-change after filter; +110-stalbe low; +111-stable high + 13 + 3 + read-write + + + SYNCEN + This bit enable the comparator output synchronization. +0: ACMP output not synchronized with ACMP clock. +1: ACMP output synchronized with ACMP clock. + 12 + 1 + read-write + + + FLTLEN + This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. + 0 + 12 + read-write + + + + + daccfg + DAC configure register + 0x4 + 32 + 0x00000000 + 0x000000FF + + + DACCFG + 8bit DAC digital value output to analog block + 0 + 8 + read-write + + + + + sr + Status register + 0x10 + 32 + 0x00000000 + 0x00000003 + + + FEDGF + Output falling edge flag. Write 1 to clear this flag. + 1 + 1 + read-write + + + REDGF + Output rising edge flag. Write 1 to clear this flag. + 0 + 1 + read-write + + + + + irqen + Interrupt request enable register + 0x14 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag interrupt enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag interrupt enable bit. + 0 + 1 + read-write + + + + + dmaen + DMA request enable register + 0x18 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag DMA request enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag DMA request enable bit. + 0 + 1 + read-write + + + + + + + + DAC + DAC + DAC + 0xf0024000 + + 0x0 + 0x4c + registers + + + + cfg0 + No description available + 0x0 + 32 + 0x00000000 + 0x0FFF03FF + + + SW_DAC_DATA + dac data used in direct mode(dac_mode==2'b10) + 16 + 12 + write-only + + + DMA_AHB_EN + set to enable internal DMA, it will read one burst if enough space in FIFO. +Should only be used in buffer mode. + 9 + 1 + write-only + + + SYNC_MODE + 1: sync dac clock and ahb clock. + all HW trigger signals are pulse in sync mode, can get faster response; +0: async dac clock and ahb_clock + all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock) + 8 + 1 + write-only + + + TRIG_MODE + 0: single mode, one trigger pulse will send one 12bit data to DAC analog; +1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data. + 7 + 1 + write-only + + + HW_TRIG_EN + set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode + 6 + 1 + write-only + + + DAC_MODE + 00: direct mode, DAC output the fixed configured data(from sw_dac_data) +01: step mode, DAC output from start_point to end point, with configured step, can step up or step down +10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; +11: trigger mode, DAC output from external trigger signals +Note: +Trigger mode is not supported in hpm63xx and hpm62xx families. + 4 + 2 + write-only + + + BUF_DATA_MODE + data structure for buffer mode, +0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. +1: each 32-bit data contains 1 point, b11:0 for first + 3 + 1 + write-only + + + HBURST_CFG + DAC support following fixed burst only +000-SINGLE; 011-INCR4; 101: INCR8 +others are reserved + 0 + 3 + write-only + + + + + cfg1 + No description available + 0x4 + 32 + 0x00010000 + 0x0007FFFF + + + ANA_CLK_EN + set to enable analog clock(divided by ana_div_cfg) +need to be set in direct mode and trigger mode + 18 + 1 + read-write + + + ANA_DIV_CFG + clock divider config for ana_clk to dac analog; +00: div2 +01: div4 +10: div6 +11: div8 + 16 + 2 + read-write + + + DIV_CFG + step mode and buffer mode: + defines how many clk_dac cycles to change data to analog, should configured to less than 1MHz data rate. +Direct mode and trigger mode: + defines how many clk_dac cycles to accpet the input data, dac will not accept new written data or trigger data before the clock cycles passed. should configured to less than 1MHz. +Note: +For direct mode and trigger mode, this config is not supported in hpm63xx and hpm62xx families. + 0 + 16 + read-write + + + + + cfg2 + No description available + 0x8 + 32 + 0x00000000 + 0x000000FF + + + DMA_RST1 + set to reset dma read pointer to buf1_start_addr; +if set both dma_rst0&dma_rst1, will set to buf0_start_addr +user can set fifo_clr bit when use dma_rst* + 7 + 1 + write-only + + + DMA_RST0 + set to reset dma read pointer to buf0_start_addr + 6 + 1 + write-only + + + FIFO_CLR + set to clear FIFO content(set both read/write pointer to 0) + 5 + 1 + write-only + + + BUF_SW_TRIG + software trigger for buffer mode, +W1C in single mode. +RW in continual mode + 4 + 1 + read-write + + + STEP_SW_TRIG3 + No description available + 3 + 1 + read-write + + + STEP_SW_TRIG2 + No description available + 2 + 1 + read-write + + + STEP_SW_TRIG1 + No description available + 1 + 1 + read-write + + + STEP_SW_TRIG0 + software trigger0 for step mode, +W1C in single mode. +RW in continual mode + 0 + 1 + read-write + + + + + 4 + 0x4 + step0,step1,step2,step3 + STEP_CFG[%s] + no description available + 0x10 + 32 + 0x00000000 + 0x3FFFFFFF + + + ROUND_MODE + 0: stop at end point; +1: reload start point, step again + 29 + 1 + read-write + + + UP_DOWN + 0 for up, 1 for down + 28 + 1 + read-write + + + END_POINT + No description available + 16 + 12 + read-write + + + STEP_NUM + output data change step_num each DAC clock cycle. +Ex: if step_num=3, output data sequence is 0,3,6,9 +NOTE: user should make sure end_point can be reached if step_num is not 1 +if step_num is 0, output data will always at start point + 12 + 4 + read-write + + + START_POINT + No description available + 0 + 12 + read-write + + + + + 2 + 0x4 + buf0,buf1 + BUF_ADDR[%s] + no description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFD + + + BUF_START_ADDR + buffer start address, should be 4-byte aligned +AHB burst can't cross 1K-byte boundary, user should config the address/length/burst to avoid such issue. + 2 + 30 + read-write + + + BUF_STOP + set to stop read point at end of bufffer0 + 0 + 1 + read-write + + + + + buf_length + No description available + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + BUF1_LEN + buffer length, 1 indicate one 32bit date, 256K-byte max for one buffer + 16 + 16 + read-write + + + BUF0_LEN + No description available + 0 + 16 + read-write + + + + + irq_sts + No description available + 0x30 + 32 + 0x00000000 + 0x0000000F + + + AHB_ERROR + set if hresp==2'b01(ERROR) + 3 + 1 + write-only + + + FIFO_EMPTY + No description available + 2 + 1 + write-only + + + BUF1_CMPT + No description available + 1 + 1 + write-only + + + BUF0_CMPT + No description available + 0 + 1 + write-only + + + + + irq_en + No description available + 0x34 + 32 + 0x00000000 + 0x0000001F + + + STEP_CMPT + No description available + 4 + 1 + read-write + + + AHB_ERROR + No description available + 3 + 1 + read-write + + + FIFO_EMPTY + No description available + 2 + 1 + read-write + + + BUF1_CMPT + No description available + 1 + 1 + read-write + + + BUF0_CMPT + No description available + 0 + 1 + read-write + + + + + dma_en + No description available + 0x38 + 32 + 0x00000000 + 0x00000003 + + + BUF1_CMPT + No description available + 1 + 1 + read-write + + + BUF0_CMPT + No description available + 0 + 1 + read-write + + + + + ana_cfg0 + No description available + 0x40 + 32 + 0x00000030 + 0x000001FF + + + DAC12BIT_LP_MODE + No description available + 8 + 1 + read-write + + + DAC_CONFIG + No description available + 4 + 4 + read-write + + + CALI_DELTA_V_CFG + No description available + 2 + 2 + read-write + + + BYPASS_CALI_GM + No description available + 1 + 1 + read-write + + + DAC12BIT_EN + No description available + 0 + 1 + read-write + + + + + cfg0_bak + No description available + 0x44 + 32 + 0x00000000 + 0x0FFF03FF + + + SW_DAC_DATA + dac data used in direct mode(dac_mode==2'b10) + 16 + 12 + read-write + + + DMA_AHB_EN + set to enable internal DMA, it will read one burst if enough space in FIFO. +Should only be used in buffer mode. + 9 + 1 + read-write + + + SYNC_MODE + 1: sync dac clock and ahb clock. + all HW trigger signals are pulse in sync mode, can get faster response; +0: async dac clock and ahb_clock + all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock) + 8 + 1 + read-write + + + TRIG_MODE + 0: single mode, one trigger pulse will send one 12bit data to DAC analog; +1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data. + 7 + 1 + read-write + + + HW_TRIG_EN + set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode + 6 + 1 + read-write + + + DAC_MODE + 00: direct mode, DAC output the fixed configured data(from sw_dac_data) +01: step mode, DAC output from start_point to end point, with configured step, can step up or step down +10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; + 4 + 2 + read-write + + + BUF_DATA_MODE + data structure for buffer mode, +0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. +1: each 32-bit data contains 1 point, b11:0 for first + 3 + 1 + read-write + + + HBURST_CFG + DAC support following fixed burst only +000-SINGLE; 011-INCR4; 101: INCR8 +others are reserved + 0 + 3 + read-write + + + + + status0 + No description available + 0x48 + 32 + 0x00000000 + 0x00FFFF80 + + + CUR_BUF_OFFSET + No description available + 8 + 16 + read-write + + + CUR_BUF_INDEX + No description available + 7 + 1 + read-write + + + + + + + SPI0 + SPI0 + SPI + 0xf0030000 + + 0x10 + 0x70 + registers + + + + TransFmt + Transfer Format Register + 0x10 + 32 + 0x00020780 + 0xFFFF1F9F + + + ADDRLEN + Address length in bytes +0x0: 1 byte +0x1: 2 bytes +0x2: 3 bytes +0x3: 4 bytes + 16 + 2 + read-write + + + DATALEN + The length of each data unit in bits +The actual bit number of a data unit is (DataLen + 1) + 8 + 5 + read-write + + + DATAMERGE + Enable Data Merge mode, which does automatic data split on write and data coalescing on read. +This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. +When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed. + 7 + 1 + read-write + + + MOSIBIDIR + Bi-directional MOSI in regular (single) mode +0x0: MOSI is uni-directional signal in regular mode. +0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two + 4 + 1 + read-write + + + LSB + Transfer data with the least significant bit first +0x0: Most significant bit first +0x1: Least significant bit first + 3 + 1 + read-write + + + SLVMODE + SPI Master/Slave mode selection +0x0: Master mode +0x1: Slave mode + 2 + 1 + read-write + + + CPOL + SPI Clock Polarity +0x0: SCLK is LOW in the idle states +0x1: SCLK is HIGH in the idle states + 1 + 1 + read-write + + + CPHA + SPI Clock Phase +0x0: Sampling data at odd SCLK edges +0x1: Sampling data at even SCLK edges + 0 + 1 + read-write + + + + + TransCtrl + Transfer Control Register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + SLVDATAONLY + Data-only mode (slave mode only) +0x0: Disable the data-only mode +0x1: Enable the data-only mode +Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0. + 31 + 1 + read-write + + + CMDEN + SPI command phase enable (Master mode only) +0x0: Disable the command phase +0x1: Enable the command phase + 30 + 1 + read-write + + + ADDREN + SPI address phase enable (Master mode only) +0x0: Disable the address phase +0x1: Enable the address phase + 29 + 1 + read-write + + + ADDRFMT + SPI address phase format (Master mode only) +0x0: Address phase is the regular (single) mode +0x1: The format of the address phase is the same as the data phase (DualQuad). + 28 + 1 + read-write + + + TRANSMODE + Transfer mode +The transfer sequence could be +0x0: Write and read at the same time +0x1: Write only +0x2: Read only +0x3: Write, Read +0x4: Read, Write +0x5: Write, Dummy, Read +0x6: Read, Dummy, Write +0x7: None Data (must enable CmdEn or AddrEn in master mode) +0x8: Dummy, Write +0x9: Dummy, Read +0xa~0xf: Reserved + 24 + 4 + read-write + + + DUALQUAD + SPI data phase format +0x0: Regular (Single) mode +0x1: Dual I/O mode +0x2: Quad I/O mode +0x3: Reserved + 22 + 2 + read-write + + + TOKENEN + Token transfer enable (Master mode only) +Append a one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. +0x0: Disable the one-byte special token +0x1: Enable the one-byte special token + 21 + 1 + read-write + + + WRTRANCNT + Transfer count for write data +WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). +WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. +The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. +For TransMode 0, WrTranCnt must be equal to RdTranCnt. + 12 + 9 + read-write + + + TOKENVALUE + Token value (Master mode only) +The value of the one-byte special token following the address phase for SPI read transfers. +0x0: token value = 0x00 +0x1: token value = 0x69 + 11 + 1 + read-write + + + DUMMYCNT + Dummy data count. The actual dummy count is (DummyCnt +1). +The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) +The Data pins are put into the high impedance during the dummy data phase. +DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases. + 9 + 2 + read-write + + + RDTRANCNT + Transfer count for read data +RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). +RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. +The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. +For TransMode 0, WrTranCnt must equal RdTranCnt. + 0 + 9 + read-write + + + + + Cmd + Command Register + 0x24 + 32 + 0x00000000 + 0x000000FF + + + CMD + SPI Command + 0 + 8 + read-write + + + + + Addr + Address Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + SPI Address +(Master mode only) + 0 + 32 + read-write + + + + + Data + Data Register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + Data to transmit or the received data +For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. +For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. +The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. +If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset. + 0 + 32 + read-write + + + + + Ctrl + Control Register + 0x30 + 32 + 0x00000000 + 0x00FFFF1F + + + TXTHRES + Transmit (TX) FIFO Threshold +The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold. + 16 + 8 + read-write + + + RXTHRES + Receive (RX) FIFO Threshold +The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold. + 8 + 8 + read-write + + + TXDMAEN + TX DMA enable + 4 + 1 + read-write + + + RXDMAEN + RX DMA enable + 3 + 1 + read-write + + + TXFIFORST + Transmit FIFO reset +Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. + 2 + 1 + read-write + + + RXFIFORST + Receive FIFO reset +Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. + 1 + 1 + read-write + + + SPIRST + SPI reset +Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. + 0 + 1 + read-write + + + + + Status + Status Register + 0x34 + 32 + 0x00000000 + 0x33FFFF01 + + + TXNUM_7_6 + Number of valid entries in the Transmit FIFO + 28 + 2 + read-only + + + RXNUM_7_6 + Number of valid entries in the Receive FIFO + 24 + 2 + read-only + + + TXFULL + Transmit FIFO Full flag + 23 + 1 + read-only + + + TXEMPTY + Transmit FIFO Empty flag + 22 + 1 + read-only + + + TXNUM_5_0 + Number of valid entries in the Transmit FIFO + 16 + 6 + read-only + + + RXFULL + Receive FIFO Full flag + 15 + 1 + read-only + + + RXEMPTY + Receive FIFO Empty flag + 14 + 1 + read-only + + + RXNUM_5_0 + Number of valid entries in the Receive FIFO + 8 + 6 + read-only + + + SPIACTIVE + SPI register programming is in progress. +In master mode, SPIActive becomes 1 after the SPI command register is written and becomes 0 after the transfer is finished. +In slave mode, SPIActive becomes 1 after the SPI CS signal is asserted and becomes 0 after the SPI CS signal is deasserted. +Note that due to clock synchronization, it may take at most two spi_clock cycles for SPIActive to change when the corresponding condition happens. +Note this bit stays 0 when Direct IO Control or the memory-mapped interface is used. + 0 + 1 + read-only + + + + + IntrEn + Interrupt Enable Register + 0x38 + 32 + 0x00000000 + 0x0000003F + + + SLVCMDEN + Enable the Slave Command Interrupt. +Control whether interrupts are triggered whenever slave commands are received. +(Slave mode only) + 5 + 1 + read-write + + + ENDINTEN + Enable the End of SPI Transfer interrupt. +Control whether interrupts are triggered when SPI transfers end. +(In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.) + 4 + 1 + read-write + + + TXFIFOINTEN + Enable the SPI Transmit FIFO Threshold interrupt. +Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold. + 3 + 1 + read-write + + + RXFIFOINTEN + Enable the SPI Receive FIFO Threshold interrupt. +Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold. + 2 + 1 + read-write + + + TXFIFOURINTEN + Enable the SPI Transmit FIFO Underrun interrupt. +Control whether interrupts are triggered when the Transmit FIFO run out of data. +(Slave mode only) + 1 + 1 + read-write + + + RXFIFOORINTEN + Enable the SPI Receive FIFO Overrun interrupt. +Control whether interrupts are triggered when the Receive FIFO overflows. +(Slave mode only) + 0 + 1 + read-write + + + + + IntrSt + Interrupt Status Register + 0x3c + 32 + 0x00000000 + 0x0000003F + + + SLVCMDINT + Slave Command Interrupt. +This bit is set when Slave Command interrupts occur. +(Slave mode only) + 5 + 1 + write-only + + + ENDINT + End of SPI Transfer interrupt. +This bit is set when End of SPI Transfer interrupts occur. + 4 + 1 + write-only + + + TXFIFOINT + TX FIFO Threshold interrupt. +This bit is set when TX FIFO Threshold interrupts occur. + 3 + 1 + write-only + + + RXFIFOINT + RX FIFO Threshold interrupt. +This bit is set when RX FIFO Threshold interrupts occur. + 2 + 1 + write-only + + + TXFIFOURINT + TX FIFO Underrun interrupt. +This bit is set when TX FIFO Underrun interrupts occur. +(Slave mode only) + 1 + 1 + write-only + + + RXFIFOORINT + RX FIFO Overrun interrupt. +This bit is set when RX FIFO Overrun interrupts occur. +(Slave mode only) + 0 + 1 + write-only + + + + + Timing + Interface Timing Register + 0x40 + 32 + 0x00000000 + 0x00003FFF + + + CS2SCLK + The minimum time between the edges of SPI CS and the edges of SCLK. +SCLK_period * (CS2SCLK + 1) / 2 + 12 + 2 + read-write + + + CSHT + The minimum time that SPI CS should stay HIGH. +SCLK_period * (CSHT + 1) / 2 + 8 + 4 + read-write + + + SCLK_DIV + The clock frequency ratio between the clock source and SPI interface SCLK. +SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) +The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency. + 0 + 8 + read-write + + + + + SlvSt + Slave Status Register + 0x60 + 32 + 0x00000000 + 0x0007FFFF + + + UNDERRUN + Data underrun occurs in the last transaction + 18 + 1 + write-only + + + OVERRUN + Data overrun occurs in the last transaction + 17 + 1 + read-write + + + READY + Set this bit to indicate that the ATCSPI200 is ready for data transaction. +When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0. + 16 + 1 + read-write + + + USR_STATUS + User defined status flags + 0 + 16 + read-write + + + + + SlvDataCnt + Slave Data Count Register + 0x64 + 32 + 0x00000000 + 0x03FF03FF + + + WCNT + Slave transmitted data count + 16 + 10 + read-only + + + RCNT + Slave received data count + 0 + 10 + read-only + + + + + Config + Configuration Register + 0x7c + 32 + 0x00004311 + 0x000043FF + + + SLAVE + Support for SPI Slave mode + 14 + 1 + read-only + + + QUADSPI + Support for Quad I/O SPI + 9 + 1 + read-only + + + DUALSPI + Support for Dual I/O SPI + 8 + 1 + read-only + + + TXFIFOSIZE + Depth of TX FIFO +0x0: 2 words +0x1: 4 words +0x2: 8 words +0x3: 16 words +0x4: 32 words +0x5: 64 words +0x6: 128 words + 4 + 4 + read-only + + + RXFIFOSIZE + Depth of RX FIFO +0x0: 2 words +0x1: 4 words +0x2: 8 words +0x3: 16 words +0x4: 32 words +0x5: 64 words +0x6: 128 words + 0 + 4 + read-only + + + + + + + SPI1 + SPI1 + SPI + 0xf0034000 + + + SPI2 + SPI2 + SPI + 0xf0038000 + + + SPI3 + SPI3 + SPI + 0xf003c000 + + + UART0 + UART0 + UART + 0xf0040000 + + 0x10 + 0x30 + registers + + + + Cfg + Configuration Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + FIFOSIZE + The depth of RXFIFO and TXFIFO +0: 16-byte FIFO +1: 32-byte FIFO +2: 64-byte FIFO +3: 128-byte FIFO + 0 + 2 + read-only + + + + + OSCR + Over Sample Control Register + 0x14 + 32 + 0x00000010 + 0x0000001F + + + OSC + Over-sample control +The value must be an even number; any odd value +writes to this field will be converted to an even value. +OSC=0: reserved +OSC<=8: The over-sample ratio is 8 +8 < OSC< 32: The over sample ratio is OSC + 0 + 5 + read-write + + + + + RBR + Receiver Buffer Register (when DLAB = 0) + UNION_20 + 0x20 + 32 + 0x00000000 + 0x000000FF + + + RBR + Receive data read port + 0 + 8 + read-only + + + + + THR + Transmitter Holding Register (when DLAB = 0) + UNION_20 + 0x20 + 32 + 0x00000000 + 0x000000FF + + + THR + Transmit data write port + 0 + 8 + write-only + + + + + DLL + Divisor Latch LSB (when DLAB = 1) + UNION_20 + 0x20 + 32 + 0x00000001 + 0x000000FF + + + DLL + Least significant byte of the Divisor Latch + 0 + 8 + read-write + + + + + IER + Interrupt Enable Register (when DLAB = 0) + UNION_24 + 0x24 + 32 + 0x00000000 + 0x0000000F + + + EMSI + Enable modem status interrupt +The interrupt asserts when the status of one of the +following occurs: +The status of modem_rin, modem_dcdn, +modem_dsrn or modem_ctsn (If the auto-cts mode is +disabled) has been changed. +If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), +modem_ctsn would be used to control the transmitter. + 3 + 1 + read-write + + + ELSI + Enable receiver line status interrupt + 2 + 1 + read-write + + + ETHEI + Enable transmitter holding register interrupt + 1 + 1 + read-write + + + ERBI + Enable received data available interrupt and the +character timeout interrupt +0: Disable +1: Enable + 0 + 1 + read-write + + + + + DLM + Divisor Latch MSB (when DLAB = 1) + UNION_24 + 0x24 + 32 + 0x00000000 + 0x000000FF + + + DLM + Most significant byte of the Divisor Latch + 0 + 8 + read-write + + + + + IIR + Interrupt Identification Register + UNION_28 + 0x28 + 32 + 0x00000001 + 0x000000CF + + + FIFOED + FIFOs enabled +These two bits are 1 when bit 0 of the FIFO Control +Register (FIFOE) is set to 1. + 6 + 2 + read-only + + + INTRID + Interrupt ID, see IIR2 for detail decoding + 0 + 4 + read-only + + + + + FCR + FIFO Control Register + UNION_28 + 0x28 + 32 + 0x00000000 + 0x000000FF + + + RFIFOT + Receiver FIFO trigger level + 6 + 2 + write-only + + + TFIFOT + Transmitter FIFO trigger level + 4 + 2 + write-only + + + DMAE + DMA enable +0: Disable +1: Enable + 3 + 1 + write-only + + + TFIFORST + Transmitter FIFO reset +Write 1 to clear all bytes in the TXFIFO and resets its +counter. The Transmitter Shift Register is not cleared. +This bit will automatically be cleared. + 2 + 1 + write-only + + + RFIFORST + Receiver FIFO reset +Write 1 to clear all bytes in the RXFIFO and resets its +counter. The Receiver Shift Register is not cleared. +This bit will automatically be cleared. + 1 + 1 + write-only + + + FIFOE + FIFO enable +Write 1 to enable both the transmitter and receiver +FIFOs. +The FIFOs are reset when the value of this bit toggles. + 0 + 1 + write-only + + + + + LCR + Line Control Register + 0x2c + 32 + 0x00000000 + 0x000000FF + + + DLAB + Divisor latch access bit + 7 + 1 + read-write + + + BC + Break control + 6 + 1 + read-write + + + SPS + Stick parity +1: Parity bit is constant 0 or 1, depending on bit4 (EPS). +0: Disable the sticky bit parity. + 5 + 1 + read-write + + + EPS + Even parity select +1: Even parity (an even number of logic-1 is in the data +and parity bits) +0: Old parity. + 4 + 1 + read-write + + + PEN + Parity enable +When this bit is set, a parity bit is generated in +transmitted data before the first STOP bit and the parity +bit would be checked for the received data. + 3 + 1 + read-write + + + STB + Number of STOP bits +0: 1 bits +1: The number of STOP bit is based on the WLS setting +When WLS = 0, STOP bit is 1.5 bits +When WLS = 1, 2, 3, STOP bit is 2 bits + 2 + 1 + read-write + + + WLS + Word length setting +0: 5 bits +1: 6 bits +2: 7 bits +3: 8 bits + 0 + 2 + read-write + + + + + MCR + Modem Control Register ( + 0x30 + 32 + 0x00000000 + 0x00000032 + + + AFE + Auto flow control enable +0: Disable +1: The auto-CTS and auto-RTS setting is based on the +RTS bit setting: +When RTS = 0, auto-CTS only +When RTS = 1, auto-CTS and auto-RTS + 5 + 1 + read-write + + + LOOP + Enable loopback mode +0: Disable +1: Enable + 4 + 1 + read-write + + + RTS + Request to send +This bit controls the modem_rtsn output. +0: The modem_rtsn output signal will be driven HIGH +1: The modem_rtsn output signal will be driven LOW + 1 + 1 + read-write + + + + + LSR + Line Status Register + 0x34 + 32 + 0x00000000 + 0x000000FF + + + ERRF + Error in RXFIFO +In the FIFO mode, this bit is set when there is at least +one parity error, framing error, or line break +associated with data in the RXFIFO. It is cleared when +this register is read and there is no more error for the +rest of data in the RXFIFO. + 7 + 1 + read-only + + + TEMT + Transmitter empty +This bit is 1 when the THR (TXFIFO in the FIFO +mode) and the Transmitter Shift Register (TSR) are +both empty. Otherwise, it is zero. + 6 + 1 + read-only + + + THRE + Transmitter Holding Register empty +This bit is 1 when the THR (TXFIFO in the FIFO +mode) is empty. Otherwise, it is zero. +If the THRE interrupt is enabled, an interrupt is +triggered when THRE becomes 1. + 5 + 1 + read-only + + + LBREAK + Line break +This bit is set when the uart_sin input signal was held +LOWfor longer than the time for a full-word +transmission. A full-word transmission is the +transmission of the START, data, parity, and STOP +bits. It is cleared when this register is read. +In the FIFO mode, this bit indicates the line break for +the received data at the top of the RXFIFO. + 4 + 1 + read-only + + + FE + Framing error +This bit is set when the received STOP bit is not +HIGH. It is cleared when this register is read. +In the FIFO mode, this bit indicates the framing error +for the received data at the top of the RXFIFO. + 3 + 1 + read-only + + + PE + Parity error +This bit is set when the received parity does not match +with the parity selected in the LCR[5:4]. It is cleared +when this register is read. +In the FIFO mode, this bit indicates the parity error +for the received data at the top of the RXFIFO. + 2 + 1 + read-only + + + OE + Overrun error +This bit indicates that data in the Receiver Buffer +Register (RBR) is overrun. + 1 + 1 + read-only + + + DR + Data ready. +This bit is set when there are incoming received data +in the Receiver Buffer Register (RBR). It is cleared +when all of the received data are read. + 0 + 1 + read-only + + + + + MSR + Modem Status Register + 0x38 + 32 + 0x00000000 + 0x00000011 + + + CTS + Clear to send +0: The modem_ctsn input signal is HIGH. +1: The modem_ctsn input signal is LOW. + 4 + 1 + read-only + + + DCTS + Delta clear to send +This bit is set when the state of the modem_ctsn input +signal has been changed since the last time this +register is read. + 0 + 1 + read-only + + + + + GPR + GPR Register + 0x3c + 32 + 0x00000000 + 0x000000FF + + + DATA + A one-byte storage register + 0 + 8 + read-write + + + + + + + UART1 + UART1 + UART + 0xf0044000 + + + UART2 + UART2 + UART + 0xf0048000 + + + UART3 + UART3 + UART + 0xf004c000 + + + UART4 + UART4 + UART + 0xf0050000 + + + UART5 + UART5 + UART + 0xf0054000 + + + UART6 + UART6 + UART + 0xf0058000 + + + UART7 + UART7 + UART + 0xf005c000 + + + PUART + PUART + UART + 0xf40e4000 + + + CAN0 + CAN0 + CAN + 0xf0080000 + + 0x0 + 0xca + registers + + + + 20 + 0x4 + buf0,buf1,buf2,buf3,buf4,buf5,buf6,buf7,buf8,buf9,buf10,buf11,buf12,buf13,buf14,buf15,buf16,buf17,buf18,buf19 + RBUF[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + 18 + 0x4 + buf0,buf1,buf2,buf3,buf4,buf5,buf6,buf7,buf8,buf9,buf10,buf11,buf12,buf13,buf14,buf15,buf16,buf17 + TBUF[%s] + no description available + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + 2 + 0x4 + wrd0,wrd1 + TTS[%s] + no description available + 0x98 + 32 + 0x00000000 + 0xFFFFFFFF + + + TTS_WRD0 + transmission time stamp, word 0, LSB 32bit + 0 + 32 + read-only + + + + + CMD_STA_CMD_CTRL + config, status, command and control bits + 0xa0 + 32 + 0x00900080 + 0xFBF3FFFF + + + SACK + Self-ACKnowledge +0 – no self-ACK +1 – self-ACK when LBME=1 + 31 + 1 + read-write + + + ROM + Receive buffer Overflow Mode +In case of a full RBUF when a new message is received, then ROM selects the following: +1 – The new message will not be stored. +0 – The oldest message will be overwritten. + 30 + 1 + read-write + + + ROV + Receive buffer OVerflow +1 – Overflow. At least one message is lost. +0 – No Overflow. +ROV is cleared by setting RREL=1. + 29 + 1 + read-only + + + RREL + Receive buffer RELease +The host controller has read the actual RB slot and releases it. Afterwards the CAN-CTRL +core points to the next RB slot. RSTAT gets updated. +1 – Release: The host has read the RB. +0 – No release + 28 + 1 + read-write + + + RBALL + Receive Buffer stores ALL data frames +0 – normal operation +1 – RB stores correct data frames as well as data frames with error + 27 + 1 + read-write + + + RSTAT + Receive buffer STATus +00 - empty +01 - > empty and < almost full (AFWL) +10 -  almost full (programmable threshold by AFWL) but not full and no overflow +11 - full (stays set in case of overflow – for overflow signaling see ROV) + 24 + 2 + read-only + + + FD_ISO + CAN FD ISO mode +0 - Bosch CAN FD (non-ISO) mode +1 - ISO CAN FD mode (ISO 11898-1:2015) +ISO CAN FD mode has a different CRC initialization value and an additional stuff bit count. +Both modes are incompatible and must not be mixed in one CAN network. +This bit has no impact to CAN 2.0B. +This bit is only writeable if RESET=1. + 23 + 1 + read-write + + + TSNEXT + Transmit buffer Secondary NEXT +0 - no action +1 - STB slot filled, select next slot. +After all frame bytes are written to the TBUF registers, the host controller has to set +TSNEXT to signal that this slot has been filled. Then the CAN-CTRL core connects the TBUF +registers to the next slot. Once a slot is marked as filled a transmission can be started +using TSONE or TSALL. +It is possible to set TSNEXT and TSONE or TSALL together in one write access. +TSNEXT has to be set by the host controller and is automatically reset by the CAN-CTRL +core immediately after it was set. +Setting TSNEXT is meaningless if TBSEL=0. In this case TSNEXT is ignored and +automatically cleared. It does not do any harm. +If all slots of the STB are filled, TSNEXT stays set until a slot becomes free. +TSNEXT has no meaning in TTCAN mode and is fixed to 0. + 22 + 1 + read-write + + + TSMODE + Transmit buffer Secondary operation MODE +0 - FIFO mode +1 - priority decision mode +In FIFO mode frames are transmitted in the order in that they are written into the STB. +In priority decision mode the frame with the highest priority in the STB is automatically +transmitted first. The ID of a frame is used for the priority decision. A lower ID means a +higher priority of a frame. A frame in the PTB has always the highest priority regardless of +the ID. +TSMODE shall be switched only if the STB if empty + 21 + 1 + read-write + + + TTTBM + TTCAN Transmit Buffer Mode +If TTEN=0 then TTTBM is ignored, otherwise the following is valid: +0 - separate PTB and STB, behavior defined by TSMODE +1 - full TTCAN support: buffer slots selectable by TBPTR and TTPTR +For event-driven CAN communication (TTEN=0), the system provides PTB and STB and +the behavior of the STB is defined by TSMODE. Then TTTBM is ignored. +For time-triggered CAN communication (TTEN=1) with full support of all features including +time-triggered transmissions, TTTBM=1 needs to be chosen. Then the all TB slots are +addressable using TTPTR and TBPTR. +For time-triggered CAN communication (TTEN=1) with only support of reception timestamps, TTTBM=0 can be chosen. Then the transmit buffer acts as in event-driven mode +and the behavior can be selected by TSMODE. +TTTBM shall be switched only if the TBUF is empty. + 20 + 1 + read-write + + + TSSTAT + Transmission Secondary STATus bits +If TTEN=0 or TTTBM=0: +00 – STB is empty +01 – STB is less than or equal to half full +10 – STB is more than half full +11 – STB is full +If the STB is disabled using STB_DISABLE, then TSSTAT=00. +If TTEN=1 and TTTBM=1: +00 – PTB and STB are empty +01 – PTB and STB are not empty and not full +11 – PTB and STB are full + 16 + 2 + read-only + + + TBSEL + Transmit Buffer Select +Selects the transmit buffer to be loaded with a message. Use the TBUF registers for +access. TBSEL needs to be stable all the time the TBUF registers are written and when +TSNEXT is set. +0 - PTB (high-priority buffer) +1 - STB +The bit will be reset to the hardware reset value if (TTEN=1 and TTTBM=1) + 15 + 1 + read-write + + + LOM + Listen Only Mode +0 - Disabled +1 - Enabled +LOM cannot be set if TPE, TSONE or TSALL is set. No transmission can be started if LOM +is enabled and LBME is disabled. +LOM=1 and LBME=0 disables all transmissions. +LOM=1 and LBME=1 disables the ACK for received frames and error frames, but enables +the transmission of own frames. + 14 + 1 + read-write + + + STBY + Transceiver Standby Mode +0 - Disabled +1 - Enabled +This register bit is connected to the output signal stby which can be used to control a +standby mode of a transceiver. +STBY cannot be set to 1 if TPE=1, TSONE=1 or TSALL=1. +If the host sets STBY to 0 then the host needs to wait for the time required by the +transceiver to start up before the host requests a new transmission. + 13 + 1 + read-write + + + TPE + Transmit Primary Enable +1 - Transmission enable for the message in the high-priority PTB +0 - No transmission for the PTB +If TPE is set, the message from the PTB will be transmitted at the next possible transmit +position. A started transmission from the STB will be completed before, but pending new +messages are delayed until the PTB message has been transmitted. +TPE stays set until the message has been transmitted successfully or it is aborted using +TPA. +The host controller can set TPE to 1 but can not reset it to 0. This would only be possible +using TPA and aborting the message. +The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and +LBME=0) or (TTEN=1 and TTTBM=1). + 12 + 1 + read-write + + + TPA + Transmit Primary Abort +1 – Aborts a transmission from PTB which has been requested by TPE=1 but not +started yet. (The data bytes of the message remains in the PTB.) +0 – no abort +The bit has to be set by the host controller and will be reset by CAN-CTRL. Setting TPA +automatically de-asserts TPE. +The host controller can set TPA to 1 but can not reset it to 0. +During the short time while the CAN-CTRL core resets the bit, it cannot be set by the +host. +The bit will be reset to the hardware reset value if RESET=1 or (TTEN=1 and TTTBM=1). +TPA should not be set simultaneously with TPE. + 11 + 1 + read-write + + + TSONE + Transmit Secondary ONE frame +1 – Transmission enable of one in the STB. In FIFO mode this is the oldest message +and in priority mode this is the one with the highest priority. +TSONE in priority mode is difficult to handle, because it is not always clear which +message will be transmitted if new messages are written to the STB meanwhile. +The controller starts the transmission as soon as the bus becomes vacant and +no request of the PTB (bit TPE) is pending. +0 – No transmission for the STB. +TSONE stays set until the message has been transmitted successfully or it is aborted +using TSA. +The host controller can set TSONE to 1 but can not reset it to 0. This would only be +possible using TSA and aborting the message. +The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and +LBME=0) or (TTEN=1 and TTTBM=1). + 10 + 1 + read-write + + + TSALL + Transmit Secondary ALL frames +1 – Transmission enable of all messages in the STB. +The controller starts the transmission as soon as the bus becomes vacant and +no request of the PTB (bit TPE) is pending. +0 – No transmission for the STB. +TSALL stays set until all messages have been transmitted successfully or they are aborted +using TSA. +The host controller can set TSALL to 1 but can not reset it to 0. This would only be +possible using TSA and aborting the messages. +The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and +LBME=0) or (TTEN=1 and TTTBM=1). +If during a transmission the STB is loaded with a new frame then the new frame will be +transmitted too. In other words: a transmission initiated by TSALL is finished when the +STB becomes empty. + 9 + 1 + read-write + + + TSA + Transmit Secondary Abort +1 – Aborts a transmission from STB which has been requested but not started yet. +For a TSONE transmission, only one frame is aborted while for a TSALL +Transmission, all frames are aborted. +One or all message slots will be released which updates TSSTAT. +All aborted messages are lost because they are not accessible any more. +If in priority mode a TSONE transmission is aborted, then it is not clear which +frame will be aborted if new frames are written to the STB meanwhile. +0 – no abort +The bit has to be set by the host controller and will be reset by CAN-CTRL. Setting TSA,automatically de-asserts TSONE or TSALL respectively. +The host controller can set TSA to 1 but can not reset it to 0. +The bit will be reset to the hardware reset value if RESET=1. +TSA should not be set simultaneously with TSONE or TSALL. + 8 + 1 + read-write + + + RESET + RESET request bit +1 - The host controller performs a local reset of CAN-CTRL. +0 - no local reset of CAN-CTRLThe some register (e.g for node configuration) can only be modified if RESET=1. +Bit RESET forces several components to a reset state. +RESET is automatically set if the node enters “bus off” state. +Note that a CAN node will participate in CAN communication after RESET is switched to 0after 11 CAN bit times. +This delay is required by the CAN standard (bus idle time).If RESET is set to 1 and immediately set to 0, then it takes some time until RESET can beread as 0 and becomes inactive. +The reason is clock domain crossing from host to CAN clockdomain. RESET is held active as long as needed depending on the relation between host andCAN clock. + 7 + 1 + read-write + + + LBME + Loop Back Mode, External +0 - Disabled +1 - EnabledLBME should not be enabled while a transmission is active + 6 + 1 + read-write + + + LBMI + Loop Back Mode, Internal +0 - Disabled1 - EnabledLBMI should not be enabled while a transmission is active. + 5 + 1 + read-write + + + TPSS + Transmission Primary Single Shot mode for PTB +0 - Disabled +1 - Enabled + 4 + 1 + read-write + + + TSSS + Transmission Secondary Single Shot mode for STB +0 - Disabled +1 - Enabled + 3 + 1 + read-write + + + RACTIVE + Reception ACTIVE (Receive Status bit) +1 - The controller is currently receiving a frame. +0 - No receive activity. + 2 + 1 + read-only + + + TACTIVE + Transmission ACTIVE (Transmit Status bit) +1 - The controller is currently transmitting a frame. +0 - No transmit activity. + 1 + 1 + read-only + + + BUSOFF + Bus Off (Bus Status bit) +1 - The controller status is “bus off”. +0 - The controller status is “bus on”. +Writing a 1 to BUSOFF will reset TECNT and RECNT. This should be done only for debugging. +See Chapter 3.9.10.6 for details. + 0 + 1 + read-write + + + + + RTIE + Receive and Transmit Interrupt Enable Register RTIE + 0xa4 + 8 + 0xFE + 0xFF + + + RIE + Receive Interrupt Enable +0 – Disabled, 1 – Enabled + 7 + 1 + read-write + + + ROIE + RB Overrun Interrupt Enable +0 – Disabled, 1 – Enabled + 6 + 1 + read-write + + + RFIE + RB Full Interrupt Enable +0 – Disabled, 1 – Enabled + 5 + 1 + read-write + + + RAFIE + RB Almost Full Interrupt Enable +0 – Disabled, 1 – Enabled + 4 + 1 + read-write + + + TPIE + Transmission Primary Interrupt Enable +0 – Disabled, 1 – Enabled + 3 + 1 + read-write + + + TSIE + Transmission Secondary Interrupt Enable +0 – Disabled, 1 – Enabled + 2 + 1 + read-write + + + EIE + Error Interrupt Enable +0 – Disabled, 1 – Enabled + 1 + 1 + read-write + + + TSFF + If TTEN=0 or TTTBM=0: Transmit Secondary buffer Full Flag +1 - The STB is filled with the maximal number of messages. +0 - The STB is not filled with the maximal number of messages. +If the STB is disabled using STB_DISABLE, then TSFF=0. +If TTEN=1 and TTTBM=1: Transmit buffer Slot Full Flag +1 - The buffer slot selected by TBPTR is filled. +0 - The buffer slot selected by TBPTR is empty. + 0 + 1 + read-only + + + + + RTIF + Receive and Transmit Interrupt Flag Register RTIF (0xa5) + 0xa5 + 8 + 0x00 + 0xFF + + + RIF + Receive Interrupt Flag +1 - Data or a remote frame has been received and is available in the receive buffer. +0 - No frame has been received. + 7 + 1 + write-only + + + ROIF + RB Overrun Interrupt Flag +1 - At least one received message has been overwritten in the RB. +0 - No RB overwritten. +In case of an overrun both ROIF and RFIF will be set. + 6 + 1 + write-only + + + RFIF + RB Full Interrupt Flag +1 - All RBs are full. If no RB will be released until the next valid message is received, +the oldest message will be lost. +0 - The RB FIFO is not full. + 5 + 1 + write-only + + + RAFIF + RB Almost Full Interrupt Flag +1 - number of filled RB slots >= AFWL_i +0 - number of filled RB slots < AFWL_i + 4 + 1 + write-only + + + TPIF + Transmission Primary Interrupt Flag +1 - The requested transmission of the PTB has been successfully completed. +0 - No transmission of the PTB has been completed. +In TTCAN mode, TPIF will never be set. Then only TSIF is valid. + 3 + 1 + write-only + + + TSIF + Transmission Secondary Interrupt Flag +1 - The requested transmission of the STB has been successfully completed. +0 - No transmission of the STB has been completed successfully. +In TTCAN mode TSIF will signal all successful transmissions, regardless of storage location of +the message. + 2 + 1 + write-only + + + EIF + Error Interrupt Flag +1 - The border of the error warning limit has been crossed in either direction, +or the BUSOFF bit has been changed in either direction. +0 - There has been no change. + 1 + 1 + write-only + + + AIF + Abort Interrupt Flag +1 - After setting TPA or TSA the appropriated message(s) have been aborted. +It is recommended to not set both TPA and TSA simultaneously because both +source AIF. +0 - No abort has been executed. +The AIF does not have an associated enable register. + 0 + 1 + write-only + + + + + ERRINT + ERRor INTerrupt Enable and Flag Register ERRINT + 0xa6 + 8 + 0x00 + 0xFF + + + EWARN + Error WARNing limit reached +1 - One of the error counters RECNT or TECNT is equal or bigger than EWL0 - The values in both counters are less than EWL. + 7 + 1 + read-only + + + EPASS + Error Passive mode active +0 - not active (node is error active) +1 - active (node is error passive) + 6 + 1 + read-only + + + EPIE + Error Passive Interrupt Enable + 5 + 1 + read-write + + + EPIF + Error Passive Interrupt Flag. EPIF will be activated if the error status changes from error +active to error passive or vice versa and if this interrupt is enabled. + 4 + 1 + write-only + + + ALIE + Arbitration Lost Interrupt Enable + 3 + 1 + read-write + + + ALIF + Arbitration Lost Interrupt Flag + 2 + 1 + write-only + + + BEIE + Bus Error Interrupt Enable + 1 + 1 + read-write + + + BEIF + Bus Error Interrupt Flag + 0 + 1 + write-only + + + + + LIMIT + Warning Limits Register LIMIT + 0xa7 + 8 + 0x1B + 0xFF + + + AFWL + receive buffer Almost Full Warning Limit +AFWL defines the internal warning limit AFWL_i with being the number of availableRB slots. +AFWL_i is compared to the number of filled RB slots and triggers RAFIF if equal. Thevalid range of . +AFWL = 0 is meaningless and automatically treated as 0x1. (Note that AFWL is meant in this rule and not AFWL_i.) +AFWL_i > nRB is meaningless and automatically treated as nRB. +AFWL_i = nRB is a valid value, but note that RFIF also exists. + 4 + 4 + read-write + + + EWL + Programmable Error Warning Limit = (EWL+1)*8. Possible Limit values: 8, 16, … 128. +The value of EWL controls EIF. + 0 + 4 + read-write + + + + + S_PRESC + Bit Timing Register(Slow Speed) + 0xa8 + 32 + 0x01020203 + 0xFF7F7FFF + + + S_PRESC + Prescaler (slow speed) +The prescaler divides the system clock to get the time quanta clock tq_clk.Valid range PRESC=[0x00, 0xff] results in divider values 1 to 256. + 24 + 8 + read-write + + + S_SJW + Synchronization Jump Width (slow speed) +The Synchronization Jump Width is the maximum time forshortening or lengthening the Bit Time for resynchronization, where TQ is a timequanta. + 16 + 7 + read-write + + + S_SEG_2 + Bit Timing Segment 2 (slow speed) +Time after the sample point. + 8 + 7 + read-write + + + S_SEG_1 + Bit Timing Segment 1 (slow speed) +The sample point will be set to after start of bit time. + 0 + 8 + read-write + + + + + F_PRESC + Bit Timing Register(Fast Speed) + 0xac + 32 + 0x01020203 + 0xFF0F0F0F + + + F_PRESC + Prescaler (fast speed) +The prescaler divides the system clock to get the time quanta clock tq_clk.Valid range PRESC=[0x00, 0xff] results in divider values 1 to 256. + 24 + 8 + read-write + + + F_SJW + Synchronization Jump Width (fast speed) +The Synchronization Jump Width is the maximum time forshortening or lengthening the Bit Time for resynchronization, where TQ is a timequanta. + 16 + 4 + read-write + + + F_SEG_2 + Bit Timing Segment 2 (fast speed) +Time after the sample point + 8 + 4 + read-write + + + F_SEG_1 + Bit Timing Segment 1 (fast speed) +The sample point will be set to after start of bit time. + 0 + 4 + read-write + + + + + EALCAP + Error and Arbitration Lost Capture Register EALCAP + 0xb0 + 8 + 0x00 + 0xFF + + + KOER + Kind Of ERror (Error code) +000 - no error +001 - BIT ERROR +010 - FORM ERROR +011 - STUFF ERROR +100 - ACKNOWLEDGEMENT ERROR +101 - CRC ERROR +110 - OTHER ERROR(dominant bits after own error flag, received active Error Flag too long,dominant bit during Passive-Error-Flag after ACK error) +111 - not used +KOER is updated with each new error. Therefore it stays untouched when frames aresuccessfully transmitted or received. + 5 + 3 + read-only + + + ALC + Arbitration Lost Capture (bit position in the frame where the arbitration has been lost) + 0 + 5 + read-only + + + + + TDC + Transmitter Delay Compensation Register TDC + 0xb1 + 8 + 0x00 + 0xFF + + + TDCEN + Transmitter Delay Compensation ENable +TDC will be activated during the data phase of a CAN FD frame if BRS is active if TDCEN=1. + 7 + 1 + read-write + + + SSPOFF + Secondary Sample Point OFFset +The transmitter delay plus SSPOFF defines the time of the secondary sample point for TDC. +SSPOFF is given as a number of TQ. + 0 + 7 + read-write + + + + + RECNT + Error Counter Registers RECNT + 0xb2 + 8 + 0x00 + 0xFF + + + RECNT + Receive Error CouNT (number of errors during reception) +RECNT is incremented and decremented as defined in the CAN specification. +RECNT does not overflow. +If TXB=1, then the error counters are frozen. + 0 + 8 + read-only + + + + + TECNT + Error Counter Registers TECNT + 0xb3 + 8 + 0x00 + 0xFF + + + TECNT + Transmit Error CouNT (number of errors during transmission) +TECNT is incremented and decremented as defined in the CAN specification. +In case of the “bus off state” TECNT may overflow. +If TXB=1, then the error counters are frozen. + 0 + 8 + read-only + + + + + ACFCTRL + Acceptance Filter Control Register ACFCTRL + 0xb4 + 8 + 0x00 + 0x2F + + + SELMASK + SELect acceptance MASK +0 - Registers ACF_x point to acceptance code +1 - Registers ACF_x point to acceptance mask. +ACFADR selects one specific acceptance filter. + 5 + 1 + read-write + + + ACFADR + acceptance filter address +ACFADR points to a specific acceptance filter. +The selected filter is accessible using theregisters ACF_x. +Bit SELMASK selects between acceptance code and mask for theselected acceptance filter. +A value of ACFADR>ACF_NUMBER-1 is meaningless and automatically treated as value ACF_NUMBER-1. +ACF_NUMBER = 16. + 0 + 4 + read-write + + + + + TIMECFG + CiA 603 Time-Stamping TIMECFG + 0xb5 + 8 + 0x00 + 0x03 + + + TIMEPOS + TIME-stamping POSition +0 – SOF1 – EOF (see Chapter 7)TIMEPOS can only be changed if TIMEEN=0, but it is possible to modify TIMPOS withthe same write access that sets TIMEEN=1. + 1 + 1 + read-write + + + TIMEEN + TIME-stamping ENable +0 – disabled +1 – enabled + 0 + 1 + read-write + + + + + ACF_EN + Acceptance Filter Enable ACF_EN + 0xb6 + 16 + 0x0000 + 0xFFFF + + + ACF_EN + Acceptance filter Enable +1 - acceptance filter enabled +0 - acceptance filter disable +Each acceptance filter (AMASK / ACODE) can be individually enabled or disabled. +Disabled filters reject a message. Only enabled filters can accept a message if the +appropriate AMASK / ACODE configuration matches. + 0 + 16 + read-write + + + + + ACF + Acceptance CODE ACODE or ACMASK + 0xb8 + 32 + 0x00000000 + 0x7FFFFFFF + + + AIDEE + Acceptance mask IDE bit check enable +1 - acceptance filter accepts either standard or extended as defined by AIDE +0 - acceptance filter accepts both standard or extended frames +Only filter 0 is affected by the power-on reset. All other filters stay uninitialized. + 30 + 1 + read-write + + + AIDE + Acceptance mask IDE bit value +If AIDEE=1 then: +1 - acceptance filter accepts only extended frames +0 - acceptance filter accepts only standard frames +Only filter 0 is affected by the power-on reset. All other filters stay uninitialized. + 29 + 1 + read-write + + + CODE_MASK + Acceptance CODE +1 - ACC bit value to compare with ID bit of the received message +0 - ACC bit value to compare with ID bit of the received message +ACODE_x(10:0) will be used for extended frames. +ACODE_x(28:0) will be used for extended frames. +Only filter 0 is affected by the power-on reset. +Acceptance MASK(if SELMASK ==1 ) +1 - acceptance check for these bits of receive identifier disabled +0 - acceptance check for these bits of receive identifier enable +AMASK_x(10:0) will be used for extended frames. +AMASK_x(28:0) will be used for extended frames. +Disabled bits result in accepting the message. Therefore the default configuration after +reset for filter 0 accepts all messages. +Only filter 0 is affected by the power-on reset. + 0 + 29 + read-write + + + + + VER + Version Information VER + 0xbc + 16 + 0x0000 + 0xFFFF + + + VERSION + Version of CAN-CTRL, given as decimal value. VER_1 holds the major version and +VER_0 the minor version.Example: version 5x16N00S00 is represented by VER_1=5 and VER_0=16 + 0 + 16 + read-write + + + + + TBSLOT + TTCAN: TB Slot Pointer TBSLOT + 0xbe + 8 + 0x00 + 0xFF + + + TBE + set TB slot to “Empty” +1 - slot selected by TBPTR shall be marked as “empty” +0 - no actionTBE is automatically reset to 0 as soon as the slot is marked as empty and TSFF=0. +If atransmission from this slot is active, then TBE stays set as long as either the transmission completes or after a transmission error or arbitration loss the + transmissionis not active any more. +If both TBF and TBE are set, then TBE wins + 7 + 1 + read-write + + + TBF + set TB slot to “Filled” +1 - slot selected by TBPTR shall be marked as “filled” +0 - no actionTBF is automatically reset to 0 as soon as the slot is marked as filled and TSFF=1. +If both TBF and TBE are set, then TBE wins. + 6 + 1 + read-write + + + TBPTR + Pointer to a TB message slot. +0x00 - Pointer to the PTB +others - Pointer to a slot in the STB +The message slot pointed to by TBPTR is readable / writable using the TBUF registers. +Write access is only possible if TSFF=0. +Setting TBF to 1 marks the selected slot asfilled and setting TBE to 1 marks the selected slot as empty. +TBSEL and TSNEXT are unused in TTCAN mode and have no meaning. +TBPTR can only point to buffer slots, that exist in the hardware. +Unusable bits ofTBPTR are fixed to 0. +TBPTR is limited to the PTB and 63 STB slots. + More slots cannot be used in TTCANmode.If TBPTR is too big and points to a slot that is not available, then TBF and TBE arereset automatically and no action takes place. + 0 + 6 + read-write + + + + + TTCFG + TTCAN: Time Trigger Configuration TTCFG + 0xbf + 8 + 0x00 + 0xFF + + + WTIE + Watch Trigger Interrupt Enable + 7 + 1 + read-write + + + WTIF + Watch Trigger Interrupt Flag +WTIF will be set if the cycle count reaches the limited defined by TT_WTRIG and WTIE is set. + 6 + 1 + read-write + + + TEIF + Trigger Error Interrupt Flag +The conditions when TEIF will be set, are defined in Chapter 6.4. There is no bit toenable or disable the handling of TEIF + 5 + 1 + read-write + + + TTIE + Time Trigger Interrupt Enable +If TTIE is set, then TTIF will be set if the cycle time is equal to the trigger timeTT_TRIG. + 4 + 1 + read-write + + + TTIF + Time Trigger Interrupt Flag +TTIF will be set if TTIE is set and the cycle time is equal to the trigger time TT_TRIG. +Writing a one to TTIF resets it. Writing a zero has no impact.TTIF will be set only once. +If TT_TRIG gets not updated, then TTIF will be not setagain in the next basic cycle. + 3 + 1 + read-write + + + T_PRESC + TTCAN Timer PRESCaler +00b - 1 +01b - 2 +10b - 4 +11b - 8 +The TTCAN time base is a CAN bittime defined by S_PRES, S_SEG_1 and S_SEG_2.With T_PRESC an additional prescaling factor of 1, 2, 4 or 8 is defined. +T_PRESC can only be modified if TTEN=0, but it is possible to modify T_PRESC and setTTEN simultaneously with one write access. + 1 + 2 + read-write + + + TTEN + Time Trigger Enable +1 - TTCAN enabled, timer is running0 - disabled + 0 + 1 + read-write + + + + + REF_MSG + TTCAN: Reference Message REF_MSG + 0xc0 + 32 + 0x00000000 + 0x9FFFFFFF + + + REF_IDE + REFerence message IDE bit. + 31 + 1 + read-write + + + REF_MSG + REFerence message IDentifier. +If REF_IDE is +1 - REF_ID(28:0) is valid (extended ID) +0 - REF_ID(10:0) is valid (standard ID) +REF_ID is used in TTCAN mode to detect a reference message. This holds for time +slaves (reception) as well as for the time master (transmission). If the reference +message is detected and there are no errors, then the Sync_Mark of this frame will +become the Ref_Mark. +REF_ID(2:0) is not tested and therefore the appropriate register bits are forced to 0. +These bits are used for up to 8 potential time masters. +CAN-CTRL recognizes the reference message only by ID. The payload is not tested. +Additional note: A time master will transmit a reference message in the same way as a +normal frame. REF_ID is intended for detection of a successful transmission of a +reference message. + 0 + 29 + read-write + + + + + TRIG_CFG + TTCAN: Trigger Configuration TRIG_CFG + 0xc4 + 16 + 0x0000 + 0xF73F + + + TEW + Transmit Enable Window +For a single shot transmit trigger there is a time of up to 16 ticks of the cycle time +where the frame is allowed to start. TWE+1 defines the number of ticks. +TEW=0 is a valid setting and shortens the transmit enable window to 1 tick + 12 + 4 + read-write + + + TTYPE + Trigger Type +000b - Immediate Trigger for immediate transmission +001b - Time Trigger for receive triggers +010b - Single Shot Transmit Trigger for exclusive time windows +011b - Transmit Start Trigger for merged arbitrating time windows +100b - Transmit Stop Trigger for merged arbitrating time windows +others - no action +The time of the trigger is defined by TT_TRIG. TTPTR selects the TB slot for the +transmit triggers. See Chapter 6.4 for more details. + 8 + 3 + read-write + + + TTPTR + Transmit Trigger TB slot Pointer +If TTPTR is too big and points to a slot that is not available, then TEIF is set and no +new trigger can be activated after a write access to TT_TRIG_1. +If TTPTR points to an empty slot, then TEIF will be set at the moment, when the +trigger time is reached. + 0 + 6 + read-write + + + + + TT_TRIG + TTCAN: Trigger Time TT_TRIG + 0xc6 + 16 + 0x0000 + 0xFFFF + + + TT_TRIG + Trigger Time +TT_TRIG(15:0) defines the cycle time for a trigger. +For a transmission trigger theearliest point of transmission of the SOF of the appropriate frame will be TT_TRIG+1. + 0 + 16 + read-write + + + + + TT_WTRIG + TTCAN: Watch Trigger Time TT_WTRIG + 0xc8 + 16 + 0x0000 + 0xFFFF + + + TT_WTRIG + Watch Trigger Time +TT_WTRIG(15:0) defines the cycle time for a watch trigger. The initial watch trigger isthe maximum cycle time 0xffff. + 0 + 16 + read-write + + + + + + + CAN1 + CAN1 + CAN + 0xf0084000 + + + WDG0 + WDG0 + WDOG + 0xf0090000 + + 0x10 + 0x10 + registers + + + + CTRL + Control Register + 0x10 + 32 + 0x00000000 + 0x000007FF + + + RSTTIME + The time interval of the reset stage: +0: Clock period x 2^7 +1: Clock period x 2^8 +2: Clock period x 2^9 +3: Clock period x 2^10 +4: Clock period x 2^11 +5: Clock period x 2^12 +6: Clock period x 2^13 +7: Clock period x 2^14 + 8 + 3 + read-write + + + INTTIME + The timer interval of the interrupt stage: +0: Clock period x 2^6 +1: Clock period x 2^8 +2: Clock period x 2^10 +3: Clock period x 2^11 +4: Clock period x 2^12 +5: Clock period x 2^13 +6: Clock period x 2^14 +7: Clock period x 2^15 +8: Clock period x 2^17 +9: Clock period x 2^19 +10: Clock period x 2^21 +11: Clock period x 2^23 +12: Clock period x 2^25 +13: Clock period x 2^27 +14: Clock period x 2^29 +15: Clock period x 2^31 + 4 + 4 + read-write + + + RSTEN + Enable or disable the watchdog reset +0: Disable +1: Enable + 3 + 1 + read-write + + + INTEN + Enable or disable the watchdog interrupt +0: Disable +1: Enable + 2 + 1 + read-write + + + CLKSEL + Clock source of timer: +0: EXTCLK +1: PCLK + 1 + 1 + read-write + + + EN + Enable or disable the watchdog timer +0: Disable +1: Enable + 0 + 1 + read-write + + + + + Restart + Restart Register + 0x14 + 32 + 0x00000000 + 0x0000FFFF + + + RESTART + Write the magic number +ATCWDT200_RESTART_NUM to restart the +watchdog timer. + 0 + 16 + write-only + + + + + WrEn + Write Protection Register + 0x18 + 32 + 0x00000000 + 0x0000FFFF + + + WEN + Write the magic code to disable the write +protection of the Control Register and the +Restart Register. + 0 + 16 + write-only + + + + + St + Status Register + 0x1c + 32 + 0x00000000 + 0x00000001 + + + INTEXPIRED + The status of the watchdog interrupt timer +0: timer is not expired yet +1: timer is expired + 0 + 1 + write-only + + + + + + + WDG1 + WDG1 + WDOG + 0xf0094000 + + + PWDG + PWDG + WDOG + 0xf40e8000 + + + MBX0A + MBX0A + MBX + 0xf00a0000 + + 0x0 + 0x24 + registers + + + + CR + Command Registers + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXRESET + Reset TX Fifo and word. + 31 + 1 + read-write + + + BARCTL + Bus Access Response Control, when bit 15:14= +00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. + 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. +10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. +11: reserved. + 14 + 2 + read-write + + + BEIE + Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. +1, enable the bus access error interrupt. +0, disable the bus access error interrupt. + 8 + 1 + read-write + + + TFMAIE + TX FIFO message available interrupt enable. +1, enable the TX FIFO massage available interrupt. +0, disable the TX FIFO message available interrupt. + 7 + 1 + read-write + + + TFMEIE + TX FIFO message empty interrupt enable. +1, enable the TX FIFO massage empty interrupt. +0, disable the TX FIFO message empty interrupt. + 6 + 1 + read-write + + + RFMAIE + RX FIFO message available interrupt enable. +1, enable the RX FIFO massage available interrupt. +0, disable the RX FIFO message available interrupt. + 5 + 1 + read-write + + + RFMFIE + RX fifo message full interrupt enable. +1, enable the RX fifo message full interrupt. +0, disable the RX fifo message full interrupt. + 4 + 1 + read-write + + + TWMEIE + TX word message empty interrupt enable. +1, enable the TX word massage empty interrupt. +0, disable the TX word message empty interrupt. + 1 + 1 + read-write + + + RWMVIE + RX word message valid interrupt enable. +1, enable the RX word massage valid interrupt. +0, disable the RX word message valid interrupt. + 0 + 1 + read-write + + + + + SR + Status Registers + 0x4 + 32 + 0x000000E2 + 0xFFFF3FFF + + + RFVC + RX FIFO valid message count + 20 + 4 + read-only + + + TFEC + TX FIFO empty message word count + 16 + 4 + read-only + + + ERRRE + bus Error for read when rx word message are still invalid, this bit is W1C bit. +1, read from word message when the word message are still invalid will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 13 + 1 + write-only + + + EWTRF + bus Error for write when tx word message are still valid, this bit is W1C bit. +1, write to word message when the word message are still valid will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 12 + 1 + write-only + + + ERRFE + bus Error for read when rx fifo empty, this bit is W1C bit. +1, read from a empty rx fifo will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 11 + 1 + write-only + + + EWTFF + bus Error for write when tx fifo full, this bit is W1C bit. +1, write to a fulled tx fifo will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 10 + 1 + write-only + + + EAIVA + bus Error for Accessing Invalid Address; this bit is W1C bit. +1, read and write to invalid address in the bus of this block, will set this bit. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 9 + 1 + write-only + + + EW2RO + bus Error for Write to Read Only address; this bit is W1C bit. +1, write to read only address happened in the bus of this block. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 8 + 1 + write-only + + + TFMA + TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. +1, TXFIFO message buffer has slot available +0, no slot available (fifo full) + 7 + 1 + read-write + + + TFME + TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. +1, no any message data in TXFIFO from other core. +0, there are some data in the 4x32 TX FIFO from other core yet. + 6 + 1 + read-write + + + RFMA + RX FIFO Message Available, available data in the 4x32 TX FIFO message buffer to the other core, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, no any data in the 4x32 TXFIFO message buffer. +0, there are some data in the the 4x32 TXFIFO message buffer already. + 5 + 1 + read-only + + + RFMF + RX FIFO Message Full, message from other core; will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, the other core had written 4x32 message in the RXFIFO. +0, no 4x32 RX FIFO message from other core yet. + 4 + 1 + read-only + + + TWME + TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, means this core had write word message to TXREG. +0, means no valid word message in the TXREG yet. + 1 + 1 + read-only + + + RWMV + RX word message valid, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, the other core had written word message in the RXREG. +0, no valid word message yet in the RXREG. + 0 + 1 + read-only + + + + + TXREG + Transmit word message to other core. + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXREG + Transmit word message to other core. + 0 + 32 + write-only + + + + + RXREG + Receive word message from other core. + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + RXREG + Receive word message from other core. + 0 + 32 + read-only + + + + + 1 + 0x4 + TXFIFO0 + TXWRD[%s] + no description available + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXFIFO + TXFIFO for sending message to other core, FIFO size, 4x32 +can write one of the word address to push data to the FIFO; +can also use 4x32 burst write from 0x010 to push 4 words to the FIFO. + 0 + 32 + write-only + + + + + 1 + 0x4 + RXFIFO0 + RXWRD[%s] + no description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXFIFO + RXFIFO for receiving message from other core, FIFO size, 4x32 +can read one of the word address to pop data to the FIFO; +can also use 4x32 burst read from 0x020 to read 4 words from the FIFO. + 0 + 32 + read-only + + + + + + + MBX0B + MBX0B + MBX + 0xf00a4000 + + + PTPC + PTPC + PTPC + 0xf00b0000 + + 0x0 + 0x3004 + registers + + + + 2 + 0x1000 + 0,1 + PTPC[%s] + no description available + 0x0 + + Ctrl0 + Control Register 0 + 0x0 + 32 + 0x00000000 + 0x000003FF + + + SUBSEC_DIGITAL_ROLLOVER + Format for ns counter rollover, +1-digital, overflow time 1000000000/0x3B9ACA00 +0-binary, overflow time 0x7FFFFFFF + 9 + 1 + read-write + + + CAPT_SNAP_KEEP + set will keep capture snap till software read capt_snapl. +If this bit is set, software should read capt_snaph first to avoid wrong result. +If this bit is cleared, capture result will be updated at each capture event + 8 + 1 + read-write + + + CAPT_SNAP_POS_EN + set will use posege of input capture signal to latch timestamp value + 7 + 1 + read-write + + + CAPT_SNAP_NEG_EN + No description available + 6 + 1 + read-write + + + COMP_EN + set to enable compare, will be cleared by HW when compare event triggered + 4 + 1 + read-write + + + UPDATE_TIMER + update timer with +/- ts_updt, pulse, clear after set + 3 + 1 + write-only + + + INIT_TIMER + initial timer with ts_updt, pulse, clear after set + 2 + 1 + write-only + + + FINE_COARSE_SEL + 0: coarse update, ns counter add ss_incr[7:0] each clk +1: fine update, ns counter add ss_incr[7:0] each time addend counter overflow + 1 + 1 + read-write + + + TIMER_ENABLE + No description available + 0 + 1 + read-write + + + + + ctrl1 + Control Register 1 + 0x4 + 32 + 0x00000000 + 0x000000FF + + + SS_INCR + constant value used to add ns counter; +such as for 50MHz timer clock, set it to 8'd20 + 0 + 8 + read-write + + + + + timeh + timestamp high + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMESTAMP_HIGH + No description available + 0 + 32 + read-only + + + + + timel + timestamp low + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMESTAMP_LOW + No description available + 0 + 32 + read-only + + + + + ts_updth + timestamp update high + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + SEC_UPDATE + together with ts_updtl, used to initial or update timestamp + 0 + 32 + read-write + + + + + ts_updtl + timestamp update low + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADD_SUB + 1 for sub; 0 for add, used only at update + 31 + 1 + read-write + + + NS_UPDATE + No description available + 0 + 31 + read-write + + + + + addend + No description available + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDEND + used in fine update mode only + 0 + 32 + read-write + + + + + tarh + No description available + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + TARGET_TIME_HIGH + used for generate compare signal if enabled + 0 + 32 + read-write + + + + + tarl + No description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + TARGET_TIME_LOW + No description available + 0 + 32 + read-write + + + + + pps_ctrl + No description available + 0x2c + 32 + 0x00000000 + 0x0000000F + + + PPS_CTRL + No description available + 0 + 4 + read-write + + + + + capt_snaph + No description available + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPT_SNAP_HIGH + take snapshot for input capture signal, at pos or neg or both; +the result can be kept or updated at each event according to cfg0.bit8 + 0 + 32 + read-only + + + + + capt_snapl + No description available + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPT_SNAP_LOW + No description available + 0 + 32 + read-write + + + + + + time_sel + No description available + 0x2000 + 32 + 0x00000000 + 0x0000000F + + + CAN3_TIME_SEL + No description available + 3 + 1 + read-write + + + CAN2_TIME_SEL + No description available + 2 + 1 + read-write + + + CAN1_TIME_SEL + No description available + 1 + 1 + read-write + + + CAN0_TIME_SEL + set to use ptpc1 for canx +clr to use ptpc0 for canx + 0 + 1 + read-write + + + + + int_sts + No description available + 0x2004 + 32 + 0x00000000 + 0x00070007 + + + COMP_INT_STS1 + No description available + 18 + 1 + write-only + + + CAPTURE_INT_STS1 + No description available + 17 + 1 + write-only + + + PPS_INT_STS1 + No description available + 16 + 1 + write-only + + + COMP_INT_STS0 + No description available + 2 + 1 + write-only + + + CAPTURE_INT_STS0 + No description available + 1 + 1 + write-only + + + PPS_INT_STS0 + No description available + 0 + 1 + write-only + + + + + int_en + No description available + 0x2008 + 32 + 0x00000000 + 0x00070007 + + + COMP_INT_STS1 + No description available + 18 + 1 + read-write + + + CAPTURE_INT_STS1 + No description available + 17 + 1 + read-write + + + PPS_INT_STS1 + No description available + 16 + 1 + read-write + + + COMP_INT_STS0 + No description available + 2 + 1 + read-write + + + CAPTURE_INT_STS0 + No description available + 1 + 1 + read-write + + + PPS_INT_STS0 + No description available + 0 + 1 + read-write + + + + + ptpc_can_ts_sel + No description available + 0x3000 + 32 + 0x00000000 + 0xFFFFFF00 + + + TSU_TBIN3_SEL + No description available + 26 + 6 + read-write + + + TSU_TBIN2_SEL + No description available + 20 + 6 + read-write + + + TSU_TBIN1_SEL + No description available + 14 + 6 + read-write + + + TSU_TBIN0_SEL + No description available + 8 + 6 + read-write + + + + + + + DMAMUX + DMAMUX + DMAMUX + 0xf00c0000 + + 0x0 + 0x40 + registers + + + + 16 + 0x4 + HDMA_MUX0,HDMA_MUX1,HDMA_MUX2,HDMA_MUX3,HDMA_MUX4,HDMA_MUX5,HDMA_MUX6,HDMA_MUX7,XDMA_MUX0,XDMA_MUX1,XDMA_MUX2,XDMA_MUX3,XDMA_MUX4,XDMA_MUX5,XDMA_MUX6,XDMA_MUX7 + MUXCFG[%s] + no description available + 0x0 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + + + HDMA + HDMA + DMA + 0xf00c4000 + + 0x10 + 0x130 + registers + + + + DMACfg + DMAC Configuration Register + 0x10 + 32 + 0x00000000 + 0xC3FFFFFF + + + CHAINXFR + Chain transfer +0x0: Chain transfer is not configured +0x1: Chain transfer is configured + 31 + 1 + read-only + + + REQSYNC + DMA request synchronization. The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. +0x0: Request synchronization is not configured +0x1: Request synchronization is configured + 30 + 1 + read-only + + + DATAWIDTH + AXI bus data width +0x0: 32 bits +0x1: 64 bits +0x2: 128 bits +0x3: 256 bits + 24 + 2 + read-only + + + ADDRWIDTH + AXI bus address width +0x18: 24 bits +0x19: 25 bits +... +0x40: 64 bits +Others: Invalid + 17 + 7 + read-only + + + CORENUM + DMA core number +0x0: 1 core +0x1: 2 cores + 16 + 1 + read-only + + + BUSNUM + AXI bus interface number +0x0: 1 AXI bus +0x1: 2 AXI busses + 15 + 1 + read-only + + + REQNUM + Request/acknowledge pair number +0x0: 0 pair +0x1: 1 pair +0x2: 2 pairs +... +0x10: 16 pairs + 10 + 5 + read-only + + + FIFODEPTH + FIFO depth +0x4: 4 entries +0x8: 8 entries +0x10: 16 entries +0x20: 32 entries +Others: Invalid + 4 + 6 + read-only + + + CHANNELNUM + Channel number +0x1: 1 channel +0x2: 2 channels +... +0x8: 8 channels +Others: Invalid + 0 + 4 + read-only + + + + + DMACtrl + DMAC Control Register + 0x20 + 32 + 0x00000000 + 0x00000001 + + + RESET + Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. +Note: The software reset may cause the in-completion of AXI transaction. + 0 + 1 + write-only + + + + + ChAbort + Channel Abort Register + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + CHABORT + Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) + 0 + 32 + write-only + + + + + IntStatus + Interrupt Status Register + 0x30 + 32 + 0x00000000 + 0x00FFFFFF + + + TC + The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. +0x0: Channel n has no terminal count status +0x1: Channel n has terminal count status + 16 + 8 + write-only + + + ABORT + The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. +0x0: Channel n has no abort status +0x1: Channel n has abort status + 8 + 8 + write-only + + + ERROR + The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: +- Bus error +- Unaligned address +- Unaligned transfer width +- Reserved configuration +0x0: Channel n has no error status +0x1: Channel n has error status + 0 + 8 + write-only + + + + + ChEN + Channel Enable Register + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + CHEN + Alias of the Enable field of all ChnCtrl registers + 0 + 32 + read-only + + + + + 8 + 0x20 + ch0,ch1,ch2,ch3,ch4,ch5,ch6,ch7 + CHCTRL[%s] + no description available + 0x40 + + Ctrl + Channel n Control Register + 0x0 + 32 + 0x00000000 + 0xEFFFFFFF + + + SRCBUSINFIDX + Bus interface index that source data is read from +0x0: Data is read from bus interface 0 +0x1: Data is read from bus interface + 31 + 1 + read-write + + + DSTBUSINFIDX + Bus interface index that destination data is written to +0x0: Data is written to bus interface 0 +0x1: Data is written to bus interface 1 + 30 + 1 + read-write + + + PRIORITY + Channel priority level +0x0: Lower priority +0x1: Higher priority + 29 + 1 + read-write + + + SRCBURSTSIZE + Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. +The burst transfer byte number is (SrcBurstSize * SrcWidth). +0x0: 1 transfer +0x1: 2 transfers +0x2: 4 transfers +0x3: 8 transfers +0x4: 16 transfers +0x5: 32 transfers +0x6: 64 transfers +0x7: 128 transfers +0x8: 256 transfers +0x9:512 transfers +0xa: 1024 transfers +0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 + 24 + 4 + read-write + + + SRCWIDTH + Source transfer width +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 + 21 + 3 + read-write + + + DSTWIDTH + Destination transfer width. +Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. +See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 + 18 + 3 + read-write + + + SRCMODE + Source DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 17 + 1 + read-write + + + DSTMODE + Destination DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 16 + 1 + read-write + + + SRCADDRCTRL + Source address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 14 + 2 + read-write + + + DSTADDRCTRL + Destination address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 12 + 2 + read-write + + + SRCREQSEL + Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + 8 + 4 + read-write + + + DSTREQSEL + Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + 4 + 4 + read-write + + + INTABTMASK + Channel abort interrupt mask +0x0: Allow the abort interrupt to be triggered +0x1: Disable the abort interrupt + 3 + 1 + read-write + + + INTERRMASK + Channel error interrupt mask +0x0: Allow the error interrupt to be triggered +0x1: Disable the error interrupt + 2 + 1 + read-write + + + INTTCMASK + Channel terminal count interrupt mask +0x0: Allow the terminal count interrupt to be triggered +0x1: Disable the terminal count interrupt + 1 + 1 + read-write + + + ENABLE + Channel enable bit +0x0: Disable +0x1: Enable + 0 + 1 + read-write + + + + + TranSize + Channel n Transfer Size Register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRANSIZE + Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. +If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + 0 + 32 + read-write + + + + + SrcAddr + Channel n Source Address Low Part Register + 0x8 + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRL + Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + 0 + 32 + read-write + + + + + SrcAddrH + Channel n Source Address High Part Register + 0xc + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRH + High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + DstAddr + Channel n Destination Address Low Part Register + 0x10 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRL + Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + 0 + 32 + read-write + + + + + DstAddrH + Channel n Destination Address High Part Register + 0x14 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRH + High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + LLPointer + Channel n Linked List Pointer Low Part Register + 0x18 + 32 + 0x00000000 + 0xFFFFFFF9 + + + LLPOINTERL + Low part of the pointer to the next descriptor. The pointer must be double word aligned. + 3 + 29 + read-write + + + LLDBUSINFIDX + Bus interface index that the next descriptor is read from +0x0: The next descriptor is read from bus interface 0 + 0 + 1 + read-write + + + + + LLPointerH + Channel n Linked List Pointer High Part Register + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + LLPOINTERH + High part of the pointer to the next descriptor. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + + + + XDMA + XDMA + DMA + 0xf3048000 + + + RNG + RNG + RNG + 0xf00c8000 + + 0x0 + 0x40 + registers + + + + CMD + Command Register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SFTRST + Soft Reset, Perform a software reset of the RNG This bit is self-clearing. +0 Do not perform a software reset. +1 Software reset + 6 + 1 + read-write + + + CLRERR + Clear the Error, clear the errors in the ESR register and the RNG interrupt. This bit is self-clearing. +0 Do not clear the errors and the interrupt. +1 Clear the errors and the interrupt. + 5 + 1 + read-write + + + CLRINT + Clear the Interrupt, clear the RNG interrupt if an error is not present. This bit is self-clearing. +0 Do not clear the interrupt. +1 Clear the interrupt + 4 + 1 + read-write + + + GENSD + Generate Seed, when both ST and GS triggered, ST first and GS next. + 1 + 1 + read-write + + + SLFCHK + Self Test, when both ST and GS triggered, ST first and GS next. + 0 + 1 + read-write + + + + + CTRL + Control Register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + MIRQERR + Mask Interrupt Request for Error + 6 + 1 + read-write + + + MIRQDN + Mask Interrupt Request for Done Event, asks the interrupts generated upon the completion of the seed and self-test modes. The status of these jobs can be viewed by: +• Reading the STA and viewing the seed done and the self-test done bits (STA[SDN, STDN]). +• Viewing the RNG_CMD for the generate-seed or the self-test bits (CMD[GS,ST]) being set, indicating that the operation is still taking place. + 5 + 1 + read-write + + + AUTRSD + Auto Reseed + 4 + 1 + read-write + + + FUFMOD + FIFO underflow response mode +00 Return all zeros and set the ESR[FUFE]. +01 Return all zeros and set the ESR[FUFE]. +10 Generate the bus transfer error +11 Generate the interrupt and return all zeros (overrides the CTRL[MASKERR]). + 0 + 2 + read-write + + + + + STA + Status Register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SCPF + Self Check Pass Fail + 21 + 3 + read-only + + + FUNCERR + Error was detected, check ESR register for details + 16 + 1 + read-only + + + FSIZE + Fifo Size, it is 5 in this design. + 12 + 4 + read-only + + + FRNNU + Fifo Level, Indicates the number of random words currently in the output FIFO + 8 + 4 + read-only + + + NSDDN + New seed done. + 6 + 1 + read-only + + + FSDDN + 1st Seed done +When "1", Indicates that the RNG generated the first seed. + 5 + 1 + read-only + + + SCDN + Self Check Done +Indicates whether Self Test is done or not. Can be cleared by the hardware reset or a new self test is +initiated by setting the CMD[ST]. +0 Self test not completed +1 Completed a self test since the last reset. + 4 + 1 + read-only + + + RSDREQ + Reseed needed +Indicates that the RNG needs to be reseeded. This is done by setting the CMD[GS], or +automatically if the CTRL[ARS] is set. + 3 + 1 + read-only + + + IDLE + Idle, the RNG is in the idle mode, and internal clocks are disabled, in this mode, access to the FIFO is allowed. Once the FIFO is empty, the RNGB fills the FIFO and then enters idle mode again. + 2 + 1 + read-only + + + BUSY + when 1, means the RNG engine is busy for seeding or random number generation, self test and so on. + 1 + 1 + read-only + + + + + ERR + Error Registers + 0xc + 32 + 0x00000000 + 0xFFFFFF3F + + + FUFE + FIFO access error(underflow) + 5 + 1 + read-only + + + SCKERR + Self-test error +Indicates that the RNG failed the most recent self test. This bit is sticky and can only be reset by a +hardware reset or by writing 1 to the CMD[CE] + 3 + 1 + read-only + + + + + FO2B + FIFO out to bus/cpu + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2B + SW read the FIFO output. + 0 + 32 + read-only + + + + + 8 + 0x4 + FO2S0,FO2S1,FO2S2,FO2S3,FO2S4,FO2S5,FO2S6,FO2S7 + R2SK[%s] + no description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2S0 + FIFO out to KMAN, will be SDP engine key. + 0 + 32 + read-only + + + + + + + KEYM + KEYM + KEYM + 0xf00cc000 + + 0x0 + 0x50 + registers + + + + 8 + 0x4 + SFK0,SFK1,SFK2,SFK3,SFK4,SFK5,SFK6,SFK7 + SOFTMKEY[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software symmetric key +key will be scambled to 4 variants for software to use, and replicable on same chip. +scramble keys are chip different, and not replicable on different chip +must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 + 0 + 32 + read-write + + + + + 8 + 0x4 + SPK0,SPK1,SPK2,SPK3,SPK4,SPK5,SPK6,SPK7 + SOFTPKEY[%s] + no description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software asymmetric key +key is derived from scrambles of fuse private key, software input key, SRK, and system security status. +This key os read once, sencondary read will read out 0 + 0 + 32 + read-write + + + + + SEC_KEY_CTL + secure key generation + 0x40 + 32 + 0x00000000 + 0x80011117 + + + LOCK_SEC_CTL + block secure state key setting being changed + 31 + 1 + read-write + + + SK_VAL + session key valid +0: session key is all 0's and not usable +1: session key is valid + 16 + 1 + read-only + + + SMK_SEL + software symmetric key selection +0: use origin value in software symmetric key +1: use scramble version of software symmetric key + 12 + 1 + read-write + + + ZMK_SEL + batt symmetric key selection +0: use scramble version of software symmetric key +1: use origin value in software symmetric key + 8 + 1 + read-write + + + FMK_SEL + fuse symmetric key selection +0: use scramble version of fuse symmetric key +1: use alnertave scramble of fuse symmetric key + 4 + 1 + read-write + + + KEY_SEL + secure symmtric key synthesize setting, key is a XOR of following +bit0: fuse mk, 0: not selected, 1:selected +bit1: zmk from batt, 0: not selected, 1:selected +bit2: software key 0: not selected, 1:selected + 0 + 3 + read-write + + + + + NSC_KEY_CTL + non-secure key generation + 0x44 + 32 + 0x00000000 + 0x80011117 + + + LOCK_NSC_CTL + block non-secure state key setting being changed + 31 + 1 + read-write + + + SK_VAL + session key valid +0: session key is all 0's and not usable +1: session key is valid + 16 + 1 + read-only + + + SMK_SEL + software symmetric key selection +0: use scramble version of software symmetric key +1: use origin value in software symmetric key + 12 + 1 + read-write + + + ZMK_SEL + batt symmetric key selection +0: use scramble version of software symmetric key +1: use origin value in software symmetric key + 8 + 1 + read-write + + + FMK_SEL + fuse symmetric key selection +0: use scramble version of fuse symmetric key +1: use origin value in fuse symmetric key + 4 + 1 + read-write + + + KEY_SEL + non-secure symmtric key synthesize setting, key is a XOR of following +bit0: fuse mk, 0: not selected, 1:selected +bit1: zmk from batt, 0: not selected, 1:selected +bit2: software key 0: not selected, 1:selected + 0 + 3 + read-write + + + + + RNG + Random number interface behavior + 0x48 + 32 + 0x00000000 + 0x00010001 + + + BLOCK_RNG_XOR + block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset +0: RNG_XOR can be changed by software +1: RNG_XOR ignore software change from software + 16 + 1 + read-write + + + RNG_XOR + control how SFK is accepted from random number generator +0: SFK value replaced by random number input +1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG + 0 + 1 + read-write + + + + + READ_CONTROL + key read out control + 0x4c + 32 + 0x00000000 + 0x00010001 + + + BLOCK_PK_READ + asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset +0: key can be read out +1: key cannot be read out + 16 + 1 + read-write + + + BLOCK_SMK_READ + symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset +0: key can be read out +1: key cannot be read out + 0 + 1 + read-write + + + + + + + I2S0 + I2S0 + I2S + 0xf0100000 + + 0x0 + 0x80 + registers + + + + CTRL + Control Register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SFTRST_RX + software reset the RX module if asserted to be 1'b1. Self-clear. + 18 + 1 + read-write + + + SFTRST_TX + software reset the TX module if asserted to be 1'b1. Self-clear. + 17 + 1 + read-write + + + SFTRST_CLKGEN + software reset the CLK GEN module if asserted to be 1'b1. Self-clear. + 16 + 1 + read-write + + + TXDNIE + TX buffer data needed interrupt enable +0: TXE interrupt masked +1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. + 15 + 1 + read-write + + + RXDAIE + RX buffer data available interrupt enable +0: RXNE interrupt masked +1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. + 14 + 1 + read-write + + + ERRIE + Error interrupt enable +This bit controls the generation of an interrupt when an error condition (UD, OV) occurs. +0: Error interrupt is masked +1: Error interrupt is enabled + 13 + 1 + read-write + + + TX_DMA_EN + Asserted to use DMA, else to use interrupt + 12 + 1 + read-write + + + RX_DMA_EN + Asserted to use DMA, else to use interrupt + 11 + 1 + read-write + + + TXFIFOCLR + Self-clear + 10 + 1 + read-write + + + RXFIFOCLR + Self-clear + 9 + 1 + read-write + + + TX_EN + enable for each TX data pad + 5 + 4 + read-write + + + RX_EN + enable for each RX data pad + 1 + 4 + read-write + + + I2S_EN + enable for the module + 0 + 1 + read-write + + + + + RFIFO_FILLINGS + Rx FIFO Filling Level + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RX3 + RX3 fifo fillings + 24 + 8 + read-only + + + RX2 + RX2 fifo fillings + 16 + 8 + read-only + + + RX1 + RX1 fifo fillings + 8 + 8 + read-only + + + RX0 + RX0 fifo fillings + 0 + 8 + read-only + + + + + TFIFO_FILLINGS + Tx FIFO Filling Level + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TX3 + TX3 fifo fillings + 24 + 8 + read-only + + + TX2 + TX2 fifo fillings + 16 + 8 + read-only + + + TX1 + TX1 fifo fillings + 8 + 8 + read-only + + + TX0 + TX0 fifo fillings + 0 + 8 + read-only + + + + + FIFO_THRESH + TX/RX FIFO Threshold setting. + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + TX + TX fifo threshold to trigger STA[tx_dn]. When tx fifo filling is smaller than or equal to the threshold, assert the tx_dn flag. + 8 + 8 + read-write + + + RX + RX fifo threshold to trigger STA[rx_da]. When rx fifo filling is greater than or equal to the threshold, assert the rx_da flag. + 0 + 8 + read-write + + + + + STA + Status Registers + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + TX_UD + Asserted when tx fifo is underflow. Should be ANDed with CTRL[tx_en] the for correct value. Write 1 to any of these 4 bits will clear the underflow error. + 13 + 4 + write-only + + + RX_OV + Asserted when rx fifo is overflow. Write 1 to any of these 4 bits will clear the overflow error. + 9 + 4 + write-only + + + TX_DN + Asserted when tx fifo data are needed. + 5 + 4 + read-only + + + RX_DA + Asserted when rx fifo data are available. + 1 + 4 + read-only + + + + + 4 + 0x4 + DATA0,DATA1,DATA2,DATA3 + RXD[%s] + no description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + D + No description available + 0 + 32 + read-only + + + + + 4 + 0x4 + DATA0,DATA1,DATA2,DATA3 + TXD[%s] + no description available + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + D + No description available + 0 + 32 + write-only + + + + + CFGR + Configruation Regsiters + 0x50 + 32 + 0x40000000 + 0xFFFFFFFF + + + BCLK_GATEOFF + Gate off the bclk. Asserted to gate-off the BCLK. + 30 + 1 + read-write + + + BCLK_DIV + Linear prescaler to generate BCLK from MCLK. +BCLK_DIV [8:0] = 0: BCLK=No CLK. +BCLK_DIV [8:0] = 1: BCLK=MCLK/1 +BCLK_DIV [8:0] = n: BCLK=MCLK/(n). +Note: These bits should be configured when the I2S is disabled. It is used only when the I2S is in master mode. + 21 + 9 + read-write + + + INV_BCLK_OUT + Invert the BCLK before sending it out to pad. Only valid in BCLK master mode + 20 + 1 + read-write + + + INV_BCLK_IN + Invert the BCLK pad input before using it internally. Only valid in BCLK slave mode + 19 + 1 + read-write + + + INV_FCLK_OUT + Invert the FCLK before sending it out to pad. Only valid in FCLK master mode + 18 + 1 + read-write + + + INV_FCLK_IN + Invert the FCLK pad input before using it internally. Only valid in FCLK slave mode + 17 + 1 + read-write + + + INV_MCLK_OUT + Invert the MCLK before sending it out to pad. Only valid in MCLK master mode + 16 + 1 + read-write + + + INV_MCLK_IN + Invert the MCLK pad input before using it internally. Only valid in MCLK slave mode + 15 + 1 + read-write + + + BCLK_SEL_OP + asserted to use external clk source + 14 + 1 + read-write + + + FCLK_SEL_OP + asserted to use external clk source + 13 + 1 + read-write + + + MCK_SEL_OP + asserted to use external clk source + 12 + 1 + read-write + + + FRAME_EDGE + The start edge of a frame +0: Falling edge indicates a new frame (Just like standard I2S Philips standard) +1: Rising edge indicates a new frame + 11 + 1 + read-write + + + CH_MAX + CH_MAX[4:0] s the number of channels supported in TDM mode. When not in TDM mode, it must be set as 2. +It must be an even number, so CH_MAX[0] is always 0. +5'h2: 2 channels +5'h4: 4 channels +... +5‘h10: 16 channels (max) + 6 + 5 + read-write + + + TDM_EN + TDM mode +0: not TDM mode +1: TDM mode + 5 + 1 + read-write + + + STD + I2S standard selection +00: I2S Philips standard. +01: MSB justified standard (left justified) +10: LSB justified standard (right justified) +11: PCM standard +Note: For correct operation, these bits should be configured when the I2S is disabled. + 3 + 2 + read-write + + + DATSIZ + Data length to be transferred +00: 16-bit data length +01: 24-bit data length +10: 32-bit data length +11: Not allowed +Note: For correct operation, these bits should be configured when the I2S is disabled. + 1 + 2 + read-write + + + CHSIZ + Channel length (number of bits per audio channel) +0: 16-bit wide +1: 32-bit wide +The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. +Note: For correct operation, this bit should be configured when the I2S is disabled. + 0 + 1 + read-write + + + + + MISC_CFGR + Misc configuration Registers + 0x58 + 32 + 0x00042000 + 0xFFFFEC01 + + + MCLK_GATEOFF + Gate off the mclk. This mclk is the output of a glitch prone mux, so every time to switch the mclk, the gate off clock should be asserted at first. After the clock is switched, de-assert this bit to ungate off the mclk. + 13 + 1 + read-write + + + MCLKOE + Master clock output to pad enable +0: Master clock output is disabled +1: Master clock output is enabled +Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. + 0 + 1 + read-write + + + + + 4 + 0x4 + DATA0,DATA1,DATA2,DATA3 + RXDSLOT[%s] + no description available + 0x60 + 32 + 0x0000FFFF + 0x0000FFFF + + + EN + No description available + 0 + 16 + read-write + + + + + 4 + 0x4 + DATA0,DATA1,DATA2,DATA3 + TXDSLOT[%s] + no description available + 0x70 + 32 + 0x0000FFFF + 0x0000FFFF + + + EN + No description available + 0 + 16 + read-write + + + + + + + I2S1 + I2S1 + I2S + 0xf0104000 + + + DAO + DAO + DAO + 0xf0110000 + + 0x0 + 0x1c + registers + + + + CTRL + Control Register + 0x0 + 32 + 0x00000000 + 0x000200FF + + + HPF_EN + Whether HPF is enabled. This HPF is used to filter out the DC part. + 17 + 1 + read-write + + + MONO + Asserted to let the left and right channel output the same value. + 7 + 1 + read-write + + + RIGHT_EN + Asserted to enable the right channel + 6 + 1 + read-write + + + LEFT_EN + Asserted to enable the left channel + 5 + 1 + read-write + + + REMAP + 1: Use remap pwm version. The remap version is a version that one pwm output is tied to zero when the input pcm signal is positive or negative +0: Don't use remap pwm version + 4 + 1 + read-write + + + INVERT + all the outputs are inverted before sending to pad + 3 + 1 + read-write + + + FALSE_LEVEL + the pad output in False run mode, or when the module is disabled +0: all low +1: all high +2: P-high, N-low +3. output is not enabled + 1 + 2 + read-write + + + FALSE_RUN + the module continues to consume data, but all the pads are constant, thus no audio out + 0 + 1 + read-write + + + + + CMD + Command Register + 0x8 + 32 + 0x00000000 + 0x00000003 + + + SFTRST + Self-clear + 1 + 1 + read-write + + + RUN + Enable this module to run. + 0 + 1 + read-write + + + + + RX_CFGR + Configuration Register + 0xc + 32 + 0x00000000 + 0x000007C0 + + + CH_MAX + CH_MAX[3:0] is the number if channels supported in TDM mode. When not in TDM mode, it must be set as 2. +It must be an even number, so CH_MAX[0] is always 0. +4'h2: 2 channels +4'h4: 4 channels +etc + 6 + 5 + read-write + + + + + RXSLT + RX Slot Control Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + EN + Slot enable for the channels. + 0 + 32 + read-write + + + + + HPF_MA + HPF A Coef Register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + COEF + Composite value of coef A of the Order-1 HPF + 0 + 32 + read-write + + + + + HPF_B + HPF B Coef Register + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + COEF + coef B of the Order-1 HPF + 0 + 32 + read-write + + + + + + + PDM + PDM + PDM + 0xf0114000 + + 0x0 + 0x34 + registers + + + + CTRL + Control Register + 0x0 + 32 + 0x00000000 + 0x809FF7FF + + + SFTRST + software reset the module. Self-clear. + 31 + 1 + read-write + + + SOF_FEDGE + asserted if the falling edge of the ref fclk from DAO is the start of a new frame. This is used to to align DAO feedback signal. + 23 + 1 + read-write + + + USE_COEF_RAM + Asserted to use Coef RAM instead of Coef ROM + 20 + 1 + read-write + + + FILT_CRX_ERR_IE + data accessed out of boundary error interruput enable. The error happens when the module cannot calculate the enough number of data in time. + 19 + 1 + read-write + + + OFIFO_OVFL_ERR_IE + output fifo overflow error interrupt enable + 18 + 1 + read-write + + + CIC_OVLD_ERR_IE + CIC overload error interrupt enable + 17 + 1 + read-write + + + CIC_SAT_ERR_IE + Error interrupt enable +This bit controls the generation of an interrupt when an error condition (CIC saturation) occurs. +0: Error interrupt is masked +1: Error interrupt is enabled + 16 + 1 + read-write + + + DEC_AFT_CIC + decimation rate after CIC. Now it is forced to be 3. + 12 + 4 + read-write + + + CAPT_DLY + Capture cycle delay>=0, should be less than PDM_CLK_HFDIV + 7 + 4 + read-write + + + PDM_CLK_HFDIV + The clock divider will work at least 4. +0: div-by-2, +1: div-by-4 +. . . +n: div-by-2*(n+1) + 3 + 4 + read-write + + + PDM_CLK_DIV_BYPASS + asserted to bypass the pdm clock divider + 2 + 1 + read-write + + + PDM_CLK_OE + pdm_clk_output_en + 1 + 1 + read-write + + + HPF_EN + pdm high pass filter enable. This order-1 HPF only applies to the PDM mic data. + 0 + 1 + read-write + + + + + CH_CTRL + Channel Control Register + 0x4 + 32 + 0x00000000 + 0x00FF03FF + + + CH_POL + Asserted to select PDM_CLK high level captured, otherwise to select PDM_CLK low level captured. + 16 + 8 + read-write + + + CH_EN + Asserted to enable the channel. +Ch8 & 9 are refs. +Ch0-7 are pdm mics. + 0 + 10 + read-write + + + + + ST + Status Register + 0x8 + 32 + 0x00000000 + 0x0000000F + + + FILT_CRX_ERR + data accessed out of boundary error + 3 + 1 + write-only + + + OFIFO_OVFL_ERR + output fifo overflow error. The reason may be sampling frequency mismatch, either fast or slow. + 2 + 1 + write-only + + + CIC_OVLD_ERR + CIC overload error. write 1 clear + 1 + 1 + write-only + + + CIC_SAT_ERR + CIC saturation. Write 1 clear + 0 + 1 + write-only + + + + + CH_CFG + Channel Configuration Register + 0xc + 32 + 0x00000000 + 0x000FFFFF + + + CH9_TYPE + No description available + 18 + 2 + read-write + + + CH8_TYPE + No description available + 16 + 2 + read-write + + + CH7_TYPE + No description available + 14 + 2 + read-write + + + CH6_TYPE + No description available + 12 + 2 + read-write + + + CH5_TYPE + No description available + 10 + 2 + read-write + + + CH4_TYPE + No description available + 8 + 2 + read-write + + + CH3_TYPE + No description available + 6 + 2 + read-write + + + CH2_TYPE + No description available + 4 + 2 + read-write + + + CH1_TYPE + No description available + 2 + 2 + read-write + + + CH0_TYPE + Type of Channel 0 +2'b00: dec-by-3 wiith filter type0 (CIC Compenstation+norm filter) +2'b01: dec-by-3 with filter type 1 (No CIC compenstation, only norm filter) + 0 + 2 + read-write + + + + + CIC_CFG + CIC configuration register + 0x10 + 32 + 0x00000000 + 0x0000FFFF + + + POST_SCALE + the shift value after CIC results. + 10 + 6 + read-write + + + SGD + Sigma_delta_order[1:0] +2'b00: 7 +2'b01: 6 +2'b10: 5 +Others: unused + 8 + 2 + read-write + + + CIC_DEC_RATIO + CIC decimation factor + 0 + 8 + read-write + + + + + CTRL_INBUF + In Buf Control Register + 0x14 + 32 + 0x00000000 + 0x3FFFFFFF + + + MAX_PTR + The buf size-1 for each channel + 22 + 8 + read-write + + + PITCH + The spacing between starting address of adjacent channels + 11 + 11 + read-write + + + START_ADDR + The starting address of channel 0 in filter data buffer + 0 + 11 + read-write + + + + + CTRL_FILT0 + Filter 0 Control Register + 0x18 + 32 + 0x00000000 + 0x0000FFFF + + + COEF_LEN_M0 + Coef length of filter type 2'b00 in coef memory + 8 + 8 + read-write + + + COEF_START_ADDR + Starting address of Coef of filter type 2'b00 in coef memory + 0 + 8 + read-write + + + + + CTRL_FILT1 + Filter 1 Control Register + 0x1c + 32 + 0x00000000 + 0x0000FFFF + + + COEF_LEN_M1 + Coef length of filter type 2'b01 in coef memory + 8 + 8 + read-write + + + COEF_START_ADDR + Starting address of Coef of filter type 2'b01 in coef memory + 0 + 8 + read-write + + + + + RUN + Run Register + 0x20 + 32 + 0x00000000 + 0x00000001 + + + PDM_EN + Asserted to enable the module + 0 + 1 + read-write + + + + + MEMAddr + Memory Access Address + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + 0--0x0FFFFFFF: COEF_RAM +0x10000000--0x1FFFFFFF: DATA_RAM + 0 + 32 + read-write + + + + + MEMData + Memory Access Data + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + The data write-to/read-from buffer + 0 + 32 + read-write + + + + + HPF_MA + HPF A Coef Register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + COEF + Composite value of coef A of the Order-1 HPF + 0 + 32 + read-write + + + + + HPF_B + HPF B Coef Register + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + COEF + coef B of the Order-1 HPF + 0 + 32 + read-write + + + + + + + PWM0 + PWM0 + PWM + 0xf0200000 + + 0x0 + 0x290 + registers + + + + unlk + Shadow registers unlock register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHUNLK + write 0xB0382607 to unlock the shadow registers of register offset from 0x04 to 0x78, +otherwise the shadow registers can not be written. + 0 + 32 + read-write + + + + + sta + Counter start register + UNION_STA + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + XSTA + pwm timer counter extended start point, should back to this value after reach xrld + 28 + 4 + read-write + + + STA + pwm timer counter start value + sta/rld will be loaded from shadow register to work register at main counter reload time, or software write unlk.shunlk + 4 + 24 + read-write + + + + + rld + Counter reload register + UNION_RLD + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + XRLD + timeout counter extended reload point, counter will reload to xsta after reach this point + 28 + 4 + read-write + + + RLD + pwm timer counter reload value + 4 + 24 + read-write + + + + + 24 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 + CMP[%s] + no description available + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, +and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + frcmd + Force output mode register + 0x78 + 32 + 0x00000000 + 0x0000FFFF + + + FRCMD + 2bit for each PWM output channel (0-7); +00: force output 0 +01: force output 1 +10: output highz +11: no force + 0 + 16 + read-write + + + + + shlk + Shadow registers lock register + 0x7c + 32 + 0x00000000 + 0x80000000 + + + SHLK + write 1 to lock all shawdow register, write access is not permitted + 31 + 1 + read-write + + + + + 24 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 + CHCFG[%s] + no description available + 0x80 + 32 + 0x00000000 + 0xFFFF0003 + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + + + gcr + Global control register + 0xf0 + 32 + 0x00000000 + 0xFDFFFFEF + + + FAULTI3EN + 1- enable the internal fault input 3 + 31 + 1 + read-write + + + FAULTI2EN + 1- enable the internal fault input 2 + 30 + 1 + read-write + + + FAULTI1EN + 1- enable the internal fault input 1 + 29 + 1 + read-write + + + FAULTI0EN + 1- enable the internal fault input 0 + 28 + 1 + read-write + + + DEBUGFAULT + 1- enable debug mode output protection + 27 + 1 + read-write + + + FRCPOL + polarity of input pwm_force, +1- active low +0- active high + 26 + 1 + read-write + + + HWSHDWEDG + When hardware event is selected as shawdow register effective time and the select comparator is configured as input capture mode. +This bit assign its which edge is used as compare shadow register hardware load event. +1- Falling edge +0- Rising edge + 24 + 1 + read-write + + + CMPSHDWSEL + This bitfield select one of the comparators as hardware event time to load comparator shadow registers + 19 + 5 + read-write + + + FAULTRECEDG + When hardware load is selected as output fault recover trigger and the selected channel is capture mode. +This bit assign its effective edge of fault recover trigger. +1- Falling edge +0- Rising edge + 18 + 1 + read-write + + + FAULTRECHWSEL + Selec one of the 24 comparators as fault output recover trigger. + 13 + 5 + read-write + + + FAULTE1EN + 1- enable the external fault input 1 + 12 + 1 + read-write + + + FAULTE0EN + 1- enable the external fault input 0 + 11 + 1 + read-write + + + FAULTEXPOL + external fault polarity +1-active low +0-active high + 9 + 2 + read-write + + + RLDSYNCEN + 1- pwm timer counter reset to reload value (rld) by synci is enabled + 8 + 1 + read-write + + + CEN + 1- enable the pwm timer counter +0- stop the pwm timer counter + 7 + 1 + read-write + + + FAULTCLR + 1- Write 1 to clear the fault condition. The output will recover if FAULTRECTIME is set to 2b'11. +User should write 1 to this bit after the active FAULT signal de-assert and before it re-assert again. + 6 + 1 + read-write + + + XRLDSYNCEN + 1- pwm timer extended counter (xcnt) reset to extended reload value (xrld) by synci is enabled + 5 + 1 + read-write + + + TIMERRESET + set to clear current timer(total 28bit, main counter and tmout_count ). Auto clear + 3 + 1 + read-write + + + FRCTIME + This bit field select the force effective time +00: force immediately +01: force at main counter reload time +10: force at FRCSYNCI +11: no force + 1 + 2 + write-only + + + SWFRC + 1- write 1 to enable software force, if the frcsrcsel is set to 0, force will take effect + 0 + 1 + read-write + + + + + shcr + Shadow register control register + 0xf4 + 32 + 0x00000000 + 0x00001FFF + + + FRCSHDWSEL + This bitfield select one of the comparators as hardware event time to load FRCMD shadow registers + 8 + 5 + read-write + + + CNTSHDWSEL + This bitfield select one of the comparators as hardware event time to load the counter related shadow registers (STA and RLD) + 3 + 5 + read-write + + + CNTSHDWUPT + This bitfield select when the counter related shadow registers (STA and RLD) will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 1 + 2 + read-write + + + SHLKEN + 1- enable shadow registers lock feature, +0- disable shadow registers lock, shlk bit will always be 0 + 0 + 1 + read-write + + + + + 24 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 + CAPPOS[%s] + no description available + 0x100 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + cnt + Counter + 0x170 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCNT + current extended counter value + 28 + 4 + read-only + + + CNT + current clock counter value + 4 + 24 + read-only + + + + + 24 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 + CAPNEG[%s] + no description available + 0x180 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + cntcopy + Counter copy + 0x1f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCNT + current extended counter value + 28 + 4 + read-only + + + CNT + current clock counter value + 4 + 24 + read-only + + + + + 8 + 0x4 + 0,1,2,3,4,5,6,7 + PWMCFG[%s] + no description available + 0x200 + 32 + 0x00000000 + 0x1FFFFFFF + + + OEN + PWM output enable +1- output is enabled +0- output is disabled + 28 + 1 + read-write + + + FRCSHDWUPT + This bitfield select when the FRCMD shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 26 + 2 + read-write + + + FAULTMODE + This bitfield defines the PWM output status when fault condition happen +00: force output 0 +01: force output 1 +1x: output highz + 24 + 2 + read-write + + + FAULTRECTIME + This bitfield select when to recover PWM output after fault condition removed. +00: immediately +01: after pwm timer counter reload time +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after software write faultclr bit in GCR register + 22 + 2 + read-write + + + FRCSRCSEL + Select sources for force output +0- force output is enabled when FRCI assert +1- force output is enabled by software write swfrc to 1 + 21 + 1 + read-write + + + PAIR + 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. +0- PWM output is in indepandent mode. + 20 + 1 + read-write + + + DEADAREA + This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. +Note: user should configure pair bit and this bitfield before PWM output is enabled. + 0 + 20 + read-write + + + + + sr + Status register + 0x220 + 32 + 0x00000000 + 0x0FFFFFFF + + + FAULTF + fault condition flag + 27 + 1 + write-only + + + XRLDF + extended reload flag, this flag set when xcnt count to xrld value or when SYNCI assert + 26 + 1 + write-only + + + HALFRLDF + half reload flag, this flag set when cnt count to rld/2 + 25 + 1 + write-only + + + RLDF + reload flag, this flag set when cnt count to rld value or when SYNCI assert + 24 + 1 + write-only + + + CMPFX + comparator output compare or input capture flag + 0 + 24 + write-only + + + + + irqen + Interrupt request enable register + 0x224 + 32 + 0x00000000 + 0x0FFFFFFF + + + FAULTIRQE + fault condition interrupt enable + 27 + 1 + read-write + + + XRLDIRQE + extended reload flag interrupt enable + 26 + 1 + read-write + + + HALFRLDIRQE + half reload flag interrupt enable + 25 + 1 + read-write + + + RLDIRQE + reload flag interrupt enable + 24 + 1 + read-write + + + CMPIRQEX + comparator output compare or input capture flag interrupt enable + 0 + 24 + read-write + + + + + dmaen + DMA request enable register + 0x22c + 32 + 0x00000000 + 0x0FFFFFFF + + + FAULTEN + fault condition DMA request enable + 27 + 1 + read-write + + + XRLDEN + extended reload flag DMA request enable + 26 + 1 + read-write + + + HALFRLDEN + half reload flag DMA request enable + 25 + 1 + read-write + + + RLDEN + reload flag DMA request enable + 24 + 1 + read-write + + + CMPENX + comparator output compare or input capture flag DMA request enable + 0 + 24 + read-write + + + + + 24 + 0x4 + cmpcfg0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 + CMPCFG[%s] + no description available + 0x230 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + + + + + PWM1 + PWM1 + PWM + 0xf0210000 + + + HALL0 + HALL0 + HALL + 0xf0204000 + + 0x0 + 0x88 + registers + + + + cr + Control Register + 0x0 + 32 + 0x00000000 + 0x8001083F + + + READ + 1- load ucnt, vcnt, wcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 + 31 + 1 + write-only + + + SNAPEN + 1- load ucnt, vcnt, wcnt and tmrcnt into their snap registers when snapi input assert + 11 + 1 + read-write + + + RSTCNT + set to reset all counter and related snapshots + 4 + 1 + read-write + + + + + phcfg + Phase configure register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DLYSEL + This bit select delay start time: +1- start counting delay after pre-trigger +0- start counting delay after u,v,w toggle + 31 + 1 + read-write + + + DLYCNT + delay clock cycles number + 0 + 24 + read-write + + + + + wdgcfg + Watchdog configure register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + WDGEN + 1- enable wdog counter + 31 + 1 + read-write + + + WDGTO + watch dog timeout value + 0 + 31 + read-write + + + + + uvwcfg + U,V,W configure register + 0xc + 32 + 0x00000000 + 0x07FFFFFF + + + PRECNT + the clock cycle number which the pre flag will set before the next uvw transition + 0 + 24 + read-write + + + + + trgoen + Trigger output enable register + 0x10 + 32 + 0x00000000 + 0xFFE00000 + + + WDGEN + 1- enable trigger output when wdg flag set + 31 + 1 + read-write + + + PHUPTEN + 1- enable trigger output when phupt flag set + 30 + 1 + read-write + + + PHPREEN + 1- enable trigger output when phpre flag set + 29 + 1 + read-write + + + PHDLYEN + 1- enable trigger output when phdly flag set + 28 + 1 + read-write + + + UFEN + 1- enable trigger output when u flag set + 23 + 1 + read-write + + + VFEN + 1- enable trigger output when v flag set + 22 + 1 + read-write + + + WFEN + 1- enable trigger output when w flag set + 21 + 1 + read-write + + + + + readen + Read event enable register + 0x14 + 32 + 0x00000000 + 0xFFE00000 + + + WDGEN + 1- load counters to their read registers when wdg flag set + 31 + 1 + read-write + + + PHUPTEN + 1- load counters to their read registers when phupt flag set + 30 + 1 + read-write + + + PHPREEN + 1- load counters to their read registers when phpre flag set + 29 + 1 + read-write + + + PHDLYEN + 1- load counters to their read registers when phdly flag set + 28 + 1 + read-write + + + UFEN + 1- load counters to their read registers when u flag set + 23 + 1 + read-write + + + VFEN + 1- load counters to their read registers when v flag set + 22 + 1 + read-write + + + WFEN + 1- load counters to their read registers when w flag set + 21 + 1 + read-write + + + + + dmaen + DMA enable register + 0x24 + 32 + 0x00000000 + 0xFFE00000 + + + WDGEN + 1- generate dma request when wdg flag set + 31 + 1 + read-write + + + PHUPTEN + 1- generate dma request when phupt flag set + 30 + 1 + read-write + + + PHPREEN + 1- generate dma request when phpre flag set + 29 + 1 + read-write + + + PHDLYEN + 1- generate dma request when phdly flag set + 28 + 1 + read-write + + + UFEN + 1- generate dma request when u flag set + 23 + 1 + read-write + + + VFEN + 1- generate dma request when v flag set + 22 + 1 + read-write + + + WFEN + 1- generate dma request when w flag set + 21 + 1 + read-write + + + + + sr + Status register + 0x28 + 32 + 0x00000000 + 0xFFE00000 + + + WDGF + watchdog count timeout flag + 31 + 1 + read-write + + + PHUPTF + phase update flag, will set when any of u, v, w signal toggle + 30 + 1 + read-write + + + PHPREF + phase update pre flag, will set PRECNT cycles before any of u, v, w signal toggle + 29 + 1 + read-write + + + PHDLYF + phase update delay flag, will set DLYCNT cycles after any of u, v, w signal toggle or after the phpre flag depands on DLYSEL setting + 28 + 1 + read-write + + + UF + u flag, will set when u signal toggle + 23 + 1 + read-write + + + VF + v flag, will set when v signal toggle + 22 + 1 + read-write + + + WF + w flag, will set when w signal toggle + 21 + 1 + read-write + + + + + irqen + Interrupt request enable register + 0x2c + 32 + 0x00000000 + 0xFFE00000 + + + WDGIE + 1- generate interrupt request when wdg flag set + 31 + 1 + read-write + + + PHUPTIE + 1- generate interrupt request when phupt flag set + 30 + 1 + read-write + + + PHPREIE + 1- generate interrupt request when phpre flag set + 29 + 1 + read-write + + + PHDLYIE + 1- generate interrupt request when phdly flag set + 28 + 1 + read-write + + + UFIE + 1- generate interrupt request when u flag set + 23 + 1 + read-write + + + VFIE + 1- generate interrupt request when v flag set + 22 + 1 + read-write + + + WFIE + 1- generate interrupt request when w flag set + 21 + 1 + read-write + + + + + 4 + 0x10 + current,read,snap0,snap1 + COUNT[%s] + no description available + 0x30 + + w + W counter + 0x0 + 32 + 0x00000000 + 0x0FFFFFFF + + + WCNT + wcnt counter + 0 + 28 + read-only + + + + + v + V counter + 0x4 + 32 + 0x00000000 + 0xCFFFFFFF + + + VCNT + vcnt counter + 0 + 28 + read-only + + + + + u + U counter + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 31 + 1 + read-only + + + USTAT + this bit indicate U state + 30 + 1 + read-only + + + VSTAT + this bit indicate V state + 29 + 1 + read-only + + + WSTAT + this bit indicate W state + 28 + 1 + read-only + + + UCNT + ucnt counter + 0 + 28 + read-only + + + + + tmr + Timer counter + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMER + 32 bit free run timer + 0 + 32 + read-only + + + + + + 3 + 0x8 + u,v,w + HIS[%s] + no description available + 0x70 + + his0 + history register 0 + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + UHIS0 + copy of ucnt when u signal transition from 0 to 1 + 0 + 32 + read-only + + + + + his1 + history register 1 + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + UHIS1 + copy of ucnt when u signal transition from 1 to 0 + 0 + 32 + read-only + + + + + + + + HALL1 + HALL1 + HALL + 0xf0214000 + + + QEI0 + QEI0 + QEI + 0xf0208000 + + 0x0 + 0x80 + registers + + + + cr + Control register + 0x0 + 32 + 0x00000000 + 0x80077F3F + + + READ + 1- load phcnt, zcnt, spdcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 + 31 + 1 + write-only + + + HRSTSPD + 1- reset spdcnt when H assert + 18 + 1 + read-write + + + HRSTPH + 1- reset phcnt when H assert + 17 + 1 + read-write + + + HRSTZ + 1- reset zcnt when H assert + 16 + 1 + read-write + + + PAUSESPD + 1- pause spdcnt when PAUSE assert + 14 + 1 + read-write + + + PAUSEPH + 1- pause phcnt when PAUSE assert + 13 + 1 + read-write + + + PAUSEZ + 1- pause zcnt when PAUSE assert + 12 + 1 + read-write + + + HRDIR1 + 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction) + 11 + 1 + read-write + + + HRDIR0 + 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction) + 10 + 1 + read-write + + + HFDIR1 + 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction) + 9 + 1 + read-write + + + HFDIR0 + 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction) + 8 + 1 + read-write + + + SNAPEN + 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert + 5 + 1 + read-write + + + RSTCNT + 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx + 4 + 1 + read-write + + + ENCTYP + 00-abz; 01-pd; 10-ud; 11-reserved + 0 + 2 + read-write + + + + + phcfg + Phase configure register + 0x4 + 32 + 0x00000000 + 0x007FFFFF + + + ZCNTCFG + 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 +0- zcnt will increment or decrement when Z input assert + 22 + 1 + read-write + + + PHCALIZ + 1- phcnt will set to phidx when Z input assert + 21 + 1 + read-write + + + PHMAX + maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax + 0 + 21 + read-write + + + + + wdgcfg + Watchdog configure register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + WDGEN + 1- enable wdog counter + 31 + 1 + read-write + + + WDGTO + watch dog timeout value + 0 + 31 + read-write + + + + + phidx + Phase index register + 0xc + 32 + 0x00000000 + 0x001FFFFF + + + PHIDX + phcnt reset value, phcnt will reset to phidx when phcaliz set to 1 + 0 + 21 + read-write + + + + + trgoen + Tigger output enable register + 0x10 + 32 + 0x00000000 + 0xF0000000 + + + WDGFEN + 1- enable trigger output when wdg flag set + 31 + 1 + read-write + + + HOMEFEN + 1- enable trigger output when homef flag set + 30 + 1 + read-write + + + POSCMPFEN + 1- enable trigger output when poscmpf flag set + 29 + 1 + read-write + + + ZPHFEN + 1- enable trigger output when zphf flag set + 28 + 1 + read-write + + + + + readen + Read event enable register + 0x14 + 32 + 0x00000000 + 0xF0000000 + + + WDGFEN + 1- load counters to their read registers when wdg flag set + 31 + 1 + read-write + + + HOMEFEN + 1- load counters to their read registers when homef flag set + 30 + 1 + read-write + + + POSCMPFEN + 1- load counters to their read registers when poscmpf flag set + 29 + 1 + read-write + + + ZPHFEN + 1- load counters to their read registers when zphf flag set + 28 + 1 + read-write + + + + + zcmp + Z comparator + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + ZCMP + zcnt postion compare value + 0 + 32 + read-write + + + + + phcmp + Phase comparator + 0x1c + 32 + 0x00000000 + 0xE01FFFFF + + + ZCMPDIS + 1- postion compare not include zcnt + 31 + 1 + read-write + + + DIRCMPDIS + 1- postion compare not include rotation direction + 30 + 1 + read-write + + + DIRCMP + 0- position compare need positive rotation +1- position compare need negative rotation + 29 + 1 + read-write + + + PHCMP + phcnt position compare value + 0 + 21 + read-write + + + + + spdcmp + Speed comparator + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + SPDCMP + spdcnt position compare value + 0 + 32 + read-write + + + + + dmaen + DMA request enable register + 0x24 + 32 + 0x00000000 + 0xF0000000 + + + WDGFEN + 1- generate dma request when wdg flag set + 31 + 1 + read-write + + + HOMEFEN + 1- generate dma request when homef flag set + 30 + 1 + read-write + + + POSCMPFEN + 1- generate dma request when poscmpf flag set + 29 + 1 + read-write + + + ZPHFEN + 1- generate dma request when zphf flag set + 28 + 1 + read-write + + + + + sr + Status register + 0x28 + 32 + 0x00000000 + 0xF0000000 + + + WDGF + watchdog flag + 31 + 1 + read-write + + + HOMEF + home flag + 30 + 1 + read-write + + + POSCMPF + postion compare match flag + 29 + 1 + read-write + + + ZPHF + z input flag + 28 + 1 + read-write + + + + + irqen + Interrupt request register + 0x2c + 32 + 0x00000000 + 0xF0000000 + + + WDGIE + 1- generate interrupt when wdg flag set + 31 + 1 + read-write + + + HOMEIE + 1- generate interrupt when homef flag set + 30 + 1 + read-write + + + POSCMPIE + 1- generate interrupt when poscmpf flag set + 29 + 1 + read-write + + + ZPHIE + 1- generate interrupt when zphf flag set + 28 + 1 + read-write + + + + + 4 + 0x10 + current,read,snap0,snap1 + COUNT[%s] + no description available + 0x30 + + z + Z counter + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + ZCNT + zcnt value + 0 + 32 + read-write + + + + + ph + Phase counter + 0x4 + 32 + 0x00000000 + 0x461FFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 30 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 26 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 25 + 1 + read-only + + + PHCNT + phcnt value + 0 + 21 + read-only + + + + + spd + Speed counter + 0x8 + 32 + 0x00000000 + 0xEFFFFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 31 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 30 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 29 + 1 + read-write + + + SPDCNT + spdcnt value + 0 + 28 + read-only + + + + + tmr + Timer counter + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + TMRCNT + 32 bit free run timer + 0 + 32 + read-only + + + + + + 4 + 0x4 + spdhis0,spdhis1,spdhis2,spdhis3 + SPDHIS[%s] + no description available + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + SPDHIS0 + copy of spdcnt, load from spdcnt after any transition from a = low, b = low + 0 + 32 + read-only + + + + + + + QEI1 + QEI1 + QEI + 0xf0218000 + + + TRGM0 + TRGM0 + TRGM + 0xf020c000 + + 0x0 + 0x404 + registers + + + + 20 + 0x4 + PWM_IN0,PWM_IN1,PWM_IN2,PWM_IN3,PWM_IN4,PWM_IN5,PWM_IN6,PWM_IN7,TRGM_IN0,TRGM_IN1,TRGM_IN2,TRGM_IN3,TRGM_IN4,TRGM_IN5,TRGM_IN6,TRGM_IN7,TRGM_IN8,TRGM_IN9,TRGM_IN10,TRGM_IN11 + FILTCFG[%s] + no description available + 0x0 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + 64 + 0x4 + TRGM_OUT0,TRGM_OUT1,TRGM_OUT2,TRGM_OUT3,TRGM_OUT4,TRGM_OUT5,TRGM_OUT6,TRGM_OUT7,TRGM_OUT8,TRGM_OUT9,TRGM_OUT10,TRGM_OUT11,TRGM_OUTX0,TRGM_OUTX1,PWM_SYNCI,PWM_FRCI,PWM_FRCSYNCI,PWM_SHRLDSYNCI,PWM_FAULTI0,PWM_FAULTI1,PWM_FAULTI2,PWM_FAULTI3,PWM_IN8,PWM_IN9,PWM_IN10,PWM_IN11,PWM_IN12,PWM_IN13,PWM_IN14,PWM_IN15,PWM_IN16,PWM_IN17,PWM_IN18,PWM_IN19,PWM_IN20,PWM_IN21,PWM_IN22,PWM_IN23,QEI_A,QEI_B,QEI_Z,QEI_H,QEI_PAUSE,QEI_SNAPI,HALL_U,HALL_V,HALL_W,HALL_SNAPI,ADC0_STRGI,ADC1_STRGI,ADC2_STRGI,ADC3_STRGI,ADCx_PTRGI0A,ADCx_PTRGI0B,ADCx_PTRGI0C,GPTMRa_SYNCI,GPTMRa_IN2,GPTMRa_IN3,GPTMRb_SYNCI,GPTMRb_IN2,GPTMRb_IN3,CMPx_WIN,CAN_PTPC0_CAP,CAN_PTPC1_CAP + TRGOCFG[%s] + no description available + 0x100 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + 4 + 0x4 + 0,1,2,3 + DMACFG[%s] + no description available + 0x200 + 32 + 0x00000000 + 0x0000001F + + + DMASRCSEL + This field selects one of the DMA requests as the DMA request output. + 0 + 5 + read-write + + + + + GCR + General Control Register + 0x400 + 32 + 0x00000000 + 0x00000FFF + + + TRGOPEN + The bitfield enable the TRGM outputs. + 0 + 12 + read-write + + + + + + + TRGM1 + TRGM1 + TRGM + 0xf021c000 + + + SYNT + SYNT + SYNT + 0xf0240000 + + 0x0 + 0x30 + registers + + + + gcr + Global control register + 0x0 + 32 + 0x00000000 + 0x00000003 + + + CRST + 1- Reset counter + 1 + 1 + read-write + + + CEN + 1- Enable counter + 0 + 1 + read-write + + + + + rld + Counter reload register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RLD + counter reload value + 0 + 32 + read-write + + + + + cnt + Counter + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + CNT + counter + 0 + 32 + read-only + + + + + 4 + 0x4 + 0,1,2,3 + CMP[%s] + no description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + comparator value, the output will assert when counter count to this value + 0 + 32 + read-write + + + + + + + ENET0 + ENET0 + ENET + 0xf2000000 + + 0x0 + 0x3028 + registers + + + + MACCFG + MAC Configuration Register + 0x0 + 32 + 0x00000000 + 0x7FFFFFFF + + + SARC + Source Address Insertion or Replacement Control + This field controls the source address insertion or replacement for all transmitted frames. Bit 30 specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits [29:28]: +- 2'b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field generation. +- 2'b10: - If Bit 30 is set to 0, the MAC inserts the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, the MAC inserts the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. +- 2'b11: - If Bit 30 is set to 0, the MAC replaces the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, the MAC replaces the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. Note: - Changes to this field take effect only on the start of a frame. If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, that is, the current frame does not use the updated value. - These bits are reserved and RO when the Enable SA, VLAN, and CRC Insertion on TX feature is not selected during core configuration. + 28 + 3 + read-write + + + TWOKPE + IEEE 802.3as Support for 2K Packets + When set, the MAC considers all frames, with up to 2,000 bytes length, as normal packets. When Bit 20 (JE) is not set, the MAC considers all received frames of size more than 2K bytes as Giant frames. When this bit is reset and Bit 20 (JE) is not set, the MAC considers all received frames of size more than 1,518 bytes (1,522 bytes for tagged) as Giant frames. When Bit 20 is set, setting this bit has no effect on Giant Frame status. + 27 + 1 + read-write + + + SFTERR + SMII Force Transmit Error + When set, this bit indicates to the PHY to force a transmit error in the SMII frame being transmitted. This bit is reserved if the SMII PHY port is not selected during core configuration. + 26 + 1 + read-write + + + CST + CRC Stripping for Type Frames + When this bit is set, the last 4 bytes (FCS) of all frames of Ether type (Length/Type field greater than or equal to 1,536) are stripped and dropped before forwarding the frame to the application. This function is not valid when the IP Checksum Engine (Type 1) is enabled in the MAC receiver. This function is valid when Type 2 Checksum Offload Engine is enabled. + 25 + 1 + read-write + + + TC + Transmit Configuration in RGMII, SGMII, or SMII + When set, this bit enables the transmission of duplex mode, link speed, and link up or down information to the PHY in the RGMII, SMII, or SGMII port. When this bit is reset, no such information is driven to the PHY. This bit is reserved (and RO) if the RGMII, SMII, or SGMII PHY port is not selected during core configuration. + 24 + 1 + read-write + + + WD + Watchdog Disable + When this bit is set, the MAC disables the watchdog timer on the receiver. The MAC can receive frames of up to 16,383 bytes. + 23 + 1 + read-write + + + JD + Jabber Disable + When this bit is set, the MAC disables the jabber timer on the transmitter. The MAC can transfer frames of up to 16,383 bytes. When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission. + 22 + 1 + read-write + + + BE + Frame Burst Enable + When this bit is set, the MAC allows frame bursting during transmission in the GMII half-duplex mode. This bit is reserved (and RO) in the 10/100 Mbps only or full-duplex-only configurations. + 21 + 1 + read-write + + + JE + Jumbo Frame Enable + When this bit is set, the MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status. + 20 + 1 + read-write + + + IFG + Inter-Frame Gap + These bits control the minimum IFG between frames during transmission. +- 000: 96 bit times +- 001: 88 bit times +- 010: 80 bit times - ... +- 111: 40 bit times In the half-duplex mode, the minimum IFG can be configured only for 64 bit times (IFG = 100). Lower values are not considered. In the 1000-Mbps mode, the minimum IFG supported is 64 bit times (and above) in the GMAC-CORE configuration and 80 bit times (and above) in other configurations. When a JAM pattern is being transmitted because of backpressure activation, the MAC does not consider the minimum IFG. + 17 + 3 + read-write + + + DCRS + Disable Carrier Sense During Transmission + When set high, this bit makes the MAC transmitter ignore the (G)MII CRS signal during frame transmission in the half-duplex mode. This request results in no errors generated because of Loss of Carrier or No Carrier during such transmission. When this bit is low, the MAC transmitter generates such errors because of Carrier Sense and can even abort the transmissions. + 16 + 1 + read-write + + + PS + Port Select + This bit selects the Ethernet line speed. +- 0: For 1000 Mbps operations +- 1: For 10 or 100 Mbps operations In 10 or 100 Mbps operations, this bit, along with FES bit, selects the exact line speed. In the 10/100 Mbps-only (always 1) or 1000 Mbps-only (always 0) configurations, this bit is read-only with the appropriate value. In default 10/100/1000 Mbps configuration, this bit is R_W. The mac_portselect_o or mac_speed_o[1] signal reflects the value of this bit. + 15 + 1 + read-write + + + FES + Speed + This bit selects the speed in the MII, RMII, SMII, RGMII, SGMII, or RevMII interface: +- 0: 10 Mbps +- 1: 100 Mbps This bit is reserved (RO) by default and is enabled only when the parameter SPEED_SELECT = Enabled. This bit generates link speed encoding when Bit 24 (TC) is set in the RGMII, SMII, or SGMII mode. This bit is always enabled for RGMII, SGMII, SMII, or RevMII interface. In configurations with RGMII, SGMII, SMII, or RevMII interface, this bit is driven as an output signal (mac_speed_o[0]) to reflect the value of this bit in the mac_speed_o signal. In configurations with RMII, MII, or GMII interface, you can optionally drive this bit as an output signal (mac_speed_o[0]) to reflect its value in the mac_speed_o signal. + 14 + 1 + read-write + + + DO + Disable Receive Own + When this bit is set, the MAC disables the reception of frames when the phy_txen_o is asserted in the half-duplex mode. When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting. This bit is not applicable if the MAC is operating in the full-duplex mode. This bit is reserved (RO with default value) if the MAC is configured for the full-duplex-only operation. + 13 + 1 + read-write + + + LM + Loopback Mode + When this bit is set, the MAC operates in the loopback mode at GMII or MII. The (G)MII Receive clock input (clk_rx_i) is required for the loopback to work properly, because the Transmit clock is not looped-back internally. + 12 + 1 + read-write + + + DM + Duplex Mode + When this bit is set, the MAC operates in the full-duplex mode where it can transmit and receive simultaneously. + 11 + 1 + read-write + + + IPC + Checksum Offload +When this bit is set, the MAC calculates the 16-bit one’s complement of the one’s complement sum of all received Ethernet frame payloads. It also checks whether the IPv4 Header checksum (assumed to be bytes 25–26 or 29–30 (VLAN-tagged) of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word. The MAC also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the IPv4 header) and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected). When this bit is reset, this function is disabled. When Type 2 COE is selected, this bit, when set, enables the IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking. + 10 + 1 + read-write + + + DR + Disable Retry +When this bit is set, the MAC attempts only one transmission. When a collision occurs on the GMII or MII interface, the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset, the MAC attempts retries based on the settings of the BL field (Bits [6:5]). + 9 + 1 + read-write + + + LUD + Link Up or Down + This bit indicates whether the link is up or down during the transmission of configuration in the RGMII, SGMII, or SMII interface: +- 0: Link Down +- 1: Link Up + 8 + 1 + read-write + + + ACS + Automatic Pad or CRC Stripping + When this bit is set, the MAC strips the Pad or FCS field on the incoming frames only if the value of the length field is less than 1,536 bytes. All received frames with length field greater than or equal to 1,536 bytes are passed to the application without stripping the Pad or FCS field. When this bit is reset, the MAC passes all incoming frames, without modifying them, to the Host. + 7 + 1 + read-write + + + BL + Back-Off Limit + The Back-Off limit determines the random integer number (r) of slot time delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only in the half-duplex mode and is reserved (RO) in the full-duplex-only configuration. +- 00: k= min (n, 10) +- 01: k = min (n, 8) +- 10: k = min (n, 4) +- 11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0 ≤ r < 2k + 5 + 2 + read-write + + + DC + Deferral Check + When this bit is set, the deferral check function is enabled in the MAC. The MAC issues a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status, when the transmit state machine is deferred for more than 24,288 bit times in the 10 or 100 Mbps mode. If the MAC is configured for 1000 Mbps operation or if the Jumbo frame mode is enabled in the 10 or 100 Mbps mode, the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, but it is prevented because of an active carrier sense signal (CRS) on GMII or MII. The defer time is not cumulative. For example, if the transmitter defers for 10,000 bit times because the CRS signal is active and then the CRS signal becomes inactive, the transmitter transmits and collision happens. Because of collision, the transmitter needs to back off and then defer again after back off completion. In such a scenario, the deferral timer is reset to 0 and it is restarted. + 4 + 1 + read-write + + + TE + Transmitter Enable + When this bit is set, the transmit state machine of the MAC is enabled for transmission on the GMII or MII. When this bit is reset, the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and does not transmit any further frames. + 3 + 1 + read-write + + + RE + Receiver Enable + When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the GMII or MII. When this bit is reset, the MAC receive state machine is disabled after the completion of the reception of the current frame, and does not receive any further frames from the GMII or MII. + 2 + 1 + read-write + + + PRELEN + Preamble Length for Transmit frames + These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode. +- 2'b00: 7 bytes of preamble +- 2'b01: 5 bytes of preamble +- 2'b10: 3 bytes of preamble +- 2'b11: Reserved + 0 + 2 + read-write + + + + + MACFF + MAC Frame Filter + 0x4 + 32 + 0x00000000 + 0x803087FF + + + RA + Receive All + When this bit is set, the MAC Receiver module passes all received frames, irrespective of whether they pass the address filter or not, to the Application. The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, the Receiver module passes only those frames to the Application that pass the SA or DA address filter. + 31 + 1 + read-write + + + DNTU + Drop non-TCP/UDP over IP Frames + When set, this bit enables the MAC to drop the non-TCP or UDP over IP frames. The MAC forward only those frames that are processed by the Layer 4 filter. When reset, this bit enables the MAC to forward all non-TCP or UDP over IP frames. + 21 + 1 + read-write + + + IPFE + Layer 3 and Layer 4 Filter Enable + When set, this bit enables the MAC to drop frames that do not match the enabled Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for matching, this bit does not have any effect. When reset, the MAC forwards all frames irrespective of the match status of the Layer 3 and Layer 4 fields. + 20 + 1 + read-write + + + VTFE + VLAN Tag Filter Enable + When set, this bit enables the MAC to drop VLAN tagged frames that do not match the VLAN Tag comparison. When reset, the MAC forwards all frames irrespective of the match status of the VLAN Tag. + 15 + 1 + read-write + + + HPF + Hash or Perfect Filter + When this bit is set, it configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by the HMC or HUC bits. When this bit is low and the HUC or HMC bit is set, the frame is passed only if it matches the Hash filter. + 10 + 1 + read-write + + + SAF + Source Address Filter Enable + When this bit is set, the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison fails, the MAC drops the frame. When this bit is reset, the MAC forwards the received frame to the application with updated SAF bit of the Rx Status depending on the SA address comparison. + 9 + 1 + read-write + + + SAIF + SA Inverse Filtering +When this bit is set, the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter. When this bit is reset, frames whose SA does not match the SA registers are marked as failing the SA Address filter. + 8 + 1 + read-write + + + PCF + Pass Control Frames + These bits control the forwarding of all control frames (including unicast and multicast Pause frames). +- 00: MAC filters all control frames from reaching the application. +- 01: MAC forwards all control frames except Pause frames to application even if they fail the Address filter. +- 10: MAC forwards all control frames to application even if they fail the Address Filter. +- 11: MAC forwards control frames that pass the Address Filter. The following conditions should be true for the Pause frames processing: - Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register 6 (Flow Control Register) to 1. - Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register 6 (Flow Control Register) is set. - Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001. Note: This field should be set to 01 only when the Condition 1 is true, that is, the MAC is programmed to operate in the full-duplex mode and the RFE bit is enabled. Otherwise, the Pause frame filtering may be inconsistent. When Condition 1 is false, the Pause frames are considered as generic control frames. Therefore, to pass all control frames (including Pause frames) when the full-duplex mode and flow control is not enabled, you should set the PCF field to 10 or 11 (as required by the application). + 6 + 2 + read-write + + + DBF + Disable Broadcast Frames + When this bit is set, the AFM module blocks all incoming broadcast frames. In addition, it overrides all other filter settings. When this bit is reset, the AFM module passes all received broadcast frames. + 5 + 1 + read-write + + + PM + Pass All Multicast +When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. When reset, filtering of multicast frame depends on HMC bit. + 4 + 1 + read-write + + + DAIF + DA Inverse Filtering + When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. When reset, normal filtering of frames is performed. + 3 + 1 + read-write + + + HMC + Hash Multicast +When set, the MAC performs destination address filtering of received multicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers. + 2 + 1 + read-write + + + HUC + Hash Unicast + When set, the MAC performs destination address filtering of unicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers. + 1 + 1 + read-write + + + PR + Promiscuous Mode +When this bit is set, the Address Filter module passes all incoming frames irrespective of the destination or source address. The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR is set. + 0 + 1 + read-write + + + + + HASH_H + Hash Table High Register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + HTH + Hash Table High + This field contains the upper 32 bits of the Hash table. + 0 + 32 + read-write + + + + + HASH_L + Hash Table Low Register + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + HTL + Hash Table Low + This field contains the lower 32 bits of the Hash table. + 0 + 32 + read-write + + + + + GMII_ADDR + GMII Address Register + 0x10 + 32 + 0x00000000 + 0x0000FFFF + + + PA + Physical Layer Address + This field indicates which of the 32 possible PHY devices are being accessed. For RevMII, this field gives the PHY Address of the RevMII module. + 11 + 5 + read-write + + + GR + GMII Register + These bits select the desired GMII register in the selected PHY device. For RevMII, these bits select the desired CSR register in the RevMII Registers set. + 6 + 5 + read-write + + + CR + CSR Clock Range + The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design. The CSR clock corresponding to different GMAC configurations is given in Table 9-2 on page 564. The suggested range of CSR clock frequency applicable for each value (when Bit[5] = 0) ensures that the MDC clock is approximately between the frequency range 1.0 MHz–2.5 MHz. +- 0000: The CSR clock frequency is 60–100 MHz and the MDC clock frequency is CSR clock/42. +- 0001: The CSR clock frequency is 100–150 MHz and the MDC clock frequency is CSR clock/62. +- 0010: The CSR clock frequency is 20–35 MHz and the MDC clock frequency is CSR clock/16. +- 0011: The CSR clock frequency is 35–60 MHz and the MDC clock frequency is CSR clock/26. +- 0100: The CSR clock frequency is 150–250 MHz and the MDC clock frequency is CSR clock/102. +- 0101: The CSR clock frequency is 250–300 MHz and the MDC clock is CSR clock/124. +- 0110, 0111: Reserved When Bit 5 is set, you can achieve higher frequency of the MDC clock than the frequency limit of 2.5 MHz (specified in the IEEE Std 802.3) and program a clock divider of lower value. For example, when CSR clock is of 100 MHz frequency and you program these bits as 1010, then the resultant MDC clock is of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. Program the following values only if the interfacing chips support faster MDC clocks. +- 1000: CSR clock/4 +- 1001: CSR clock/6 +- 1010: CSR clock/8 +- 1011: CSR clock/10 +- 1100: CSR clock/12 +- 1101: CSR clock/14 +- 1110: CSR clock/16 +- 1111: CSR clock/18 These bits are not used for accessing RevMII. These bits are read-only if the RevMII interface is selected as single PHY interface. + 2 + 4 + read-write + + + GW + GMII Write + When set, this bit indicates to the PHY or RevMII that this is a Write operation using the GMII Data register. If this bit is not set, it indicates that this is a Read operation, that is, placing the data in the GMII Data register. + 1 + 1 + read-write + + + GB + GMII Busy + This bit should read logic 0 before writing to Register 4 and Register 5. During a PHY or RevMII register access, the software sets this bit to 1’b1 to indicate that a Read or Write access is in progress. Register 5 is invalid until this bit is cleared by the MAC. Therefore, Register 5 (GMII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. Similarly for a read operation, the contents of Register 5 are not valid until this bit is cleared. The subsequent read or write operation should happen only after the previous operation is complete. Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed, there is no change in the functionality of this bit even when the PHY is not present. + 0 + 1 + read-write + + + + + GMII_DATA + GMII Data Register + 0x14 + 32 + 0x00000000 + 0x0000FFFF + + + GD + GMII Data + This field contains the 16-bit data value read from the PHY or RevMII after a Management Read operation or the 16-bit data value to be written to the PHY or RevMII before a Management Write operation. + 0 + 16 + read-write + + + + + FLOWCTRL + Flow Control Register + 0x18 + 32 + 0x00000000 + 0xFFFF00BF + + + PT + Pause Time + This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the (G)MII clock domain, then consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain. + 16 + 16 + read-write + + + DZPQ + Disable Zero-Quanta Pause + When this bit is set, it disables the automatic generation of the Zero-Quanta Pause frames on the de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i/mti_flowctrl_i). When this bit is reset, normal operation with automatic Zero-Quanta Pause frame generation is enabled. + 7 + 1 + read-write + + + PLT + Pause Low Threshold + This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause frame. The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = 100H (256 slot-times), and PLT = 01, then a second Pause frame is automatically transmitted if the mti_flowctrl_i signal is asserted at 228 (256 – 28) slot times after the first Pause frame is transmitted. The following list provides the threshold values for different values: +- 00: The threshold is Pause time minus 4 slot times (PT – 4 slot times). +- 01: The threshold is Pause time minus 28 slot times (PT – 28 slot times). +- 10: The threshold is Pause time minus 144 slot times (PT – 144 slot times). +- 11: The threshold is Pause time minus 256 slot times (PT – 256 slot times). The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the GMII or MII interface. + 4 + 2 + read-write + + + UP + Unicast Pause Frame Detect A pause frame is processed when it has the unique multicast address specified in the IEEE Std 802.3. When this bit is set, the MAC can also detect Pause frames with unicast address of the station. This unicast address should be as specified in the MAC Address0 High Register and MAC Address0 Low Register. When this bit is reset, the MAC only detects Pause frames with unique multicast address. + 3 + 1 + read-write + + + RFE + Receive Flow Control Enable + When this bit is set, the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause) time. When this bit is reset, the decode function of the Pause frame is disabled. + 2 + 1 + read-write + + + TFE + Transmit Flow Control Enable +In the full-duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC does not transmit any Pause frames. In the half-duplex mode, when this bit is set, the MAC enables the backpressure operation. When this bit is reset, the backpressure feature is disabled. + 1 + 1 + read-write + + + FCB_BPA + Flow Control Busy or Backpressure Activate + This bit initiates a Pause frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set. In the full-duplex mode, this bit should be read as 1'b0 before writing to the Flow Control register. To initiate a Pause frame, the Application must set this bit to 1'b1. During a transfer of the Control Frame, this bit continues to be set to signify that a frame transmission is in progress. After the completion of Pause frame transmission, the MAC resets this bit to 1'b0. The Flow Control register should not be written to until this bit is cleared. In the half-duplex mode, when this bit is set (and TFE is set), then backpressure is asserted by the MAC. During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. This control register bit is logically ORed with the mti_flowctrl_i input signal for the backpressure function. When the MAC is configured for the full-duplex mode, the BPA is automatically disabled. + 0 + 1 + read-write + + + + + VLAN_TAG + VLAN Tag Register + 0x1c + 32 + 0x00000000 + 0x000FFFFF + + + VTHM + VLAN Tag Hash Table Match Enable + When set, the most significant four bits of the VLAN tag’s CRC are used to index the content of Register 354 (VLAN Hash Table Register). A value of 1 in the VLAN Hash Table register, corresponding to the index, indicates that the frame matched the VLAN hash table. When Bit 16 (ETV) is set, the CRC of the 12-bit VLAN Identifier (VID) is used for comparison whereas when ETV is reset, the CRC of the 16-bit VLAN tag is used for comparison. When reset, the VLAN Hash Match operation is not performed. + 19 + 1 + read-write + + + ESVL + Enable S-VLAN + When this bit is set, the MAC transmitter and receiver also consider the S-VLAN (Type = 0x88A8) frames as valid VLAN tagged frames. + 18 + 1 + read-write + + + VTIM + VLAN Tag Inverse Match Enable +When set, this bit enables the VLAN Tag inverse matching. The frames that do not have matching VLAN Tag are marked as matched. When reset, this bit enables the VLAN Tag perfect matching. The frames with matched VLAN Tag are marked as matched. + 17 + 1 + read-write + + + ETV + Enable 12-Bit VLAN Tag Comparison + When this bit is set, a 12-bit VLAN identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag. Bits [11:0] of VLAN tag are compared with the corresponding field in the received VLAN-tagged frame. Similarly, when enabled, only 12 bits of the VLAN tag in the received frame are used for hash-based VLAN filtering. When this bit is reset, all 16 bits of the 15th and 16th bytes of the received VLAN frame are used for comparison and VLAN hash filtering. + 16 + 1 + read-write + + + VL + VLAN Tag Identifier for Receive Frames + This field contains the 802.1Q VLAN tag to identify the VLAN frames and is compared to the 15th and 16th bytes of the frames being received for VLAN frames. The following list describes the bits of this field: - Bits [15:13]: User Priority - Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) - Bits[11:0]: VLAN tag’s VLAN Identifier (VID) field When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison. If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and 16th bytes for VLAN tag comparison, and declares all frames with a Type field value of 0x8100 or 0x88a8 as VLAN frames. + 0 + 16 + read-write + + + + + RWKFRMFILT + Remote Wake-Up Frame Filter Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + WKUPFRMFILT + This is the address through which the application writes or reads the remote wake-up frame filter registers (wkupfmfilter_reg). The wkupfmfilter_reg register is a pointer to eight wkupfmfilter_reg registers. The wkupfmfilter_reg register is loaded by sequentially loading the eight register values. Eight sequential writes to this address (0x0028) write all wkupfmfilter_reg registers. Similarly, eight sequential reads from this address (0x0028) read all wkupfmfilter_reg registers + 0 + 32 + read-write + + + + + PMT_CSR + PMT Control and Status Register + 0x2c + 32 + 0x00000000 + 0x9F000267 + + + RWKFILTRST + Remote Wake-Up Frame Filter Register Pointer Reset +When this bit is set, it resets the remote wake-up frame filter register pointer to 3’b000. It is automatically cleared after 1 clock cycle. + 31 + 1 + read-write + + + RWKPTR + Remote Wake-up FIFO Pointer +This field gives the current value (0 to 31) of the Remote Wake-up Frame filter register pointer. When the value of this pointer is equal to 7, 15, 23 or 31, the contents of the Remote Wake-up Frame Filter Register are transferred to the clk_rx_i domain when a write occurs to that register. The maximum value of the pointer is 7, 15, 23 and 31 respectively depending on the number of Remote Wakeup Filters selected during configuration. + 24 + 5 + read-write + + + GLBLUCAST + Global Unicast +When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a remote wake-up frame. + 9 + 1 + read-write + + + RWKPRCVD + Remote Wake-Up Frame Received +When set, this bit indicates the power management event is generated because of the reception of a remote wake-up frame. This bit is cleared by a Read into this register. + 6 + 1 + read-write + + + MGKPRCVD + Magic Packet Received +When set, this bit indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared by a Read into this register. + 5 + 1 + read-write + + + RWKPKTEN + Remote Wake-Up Frame Enable +When set, enables generation of a power management event because of remote wake-up frame reception. + 2 + 1 + read-write + + + MGKPKTEN + Magic Packet Enable +When set, enables generation of a power management event because of magic packet reception. + 1 + 1 + read-write + + + PWRDWN + Power Down +When set, the MAC receiver drops all received frames until it receives the expected magic packet or remote wake-up frame. This bit is then self-cleared and the power-down mode is disabled. The Software can also clear this bit before the expected magic packet or remote wake-up frame is received. The frames, received by the MAC after this bit is cleared, are forwarded to the application. This bit must only be set when the Magic Packet Enable, Global Unicast, or Remote Wake-Up Frame Enable bit is set high. Note: You can gate-off the CSR clock during the power-down mode. However, when the CSR clock is gated-off, you cannot perform any read or write operations on this register. Therefore, the Software cannot clear this bit. + 0 + 1 + read-write + + + + + LPI_CSR + LPI Control and Status Register + 0x30 + 32 + 0x00000000 + 0x000F030F + + + LPITXA + LPI TX Automate +This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the transmit side. This bit is not functional in the GMAC-CORE configuration in which the Tx clock gating is done during the LPI mode. If the LPITXA and LPIEN bits are set to 1, the MAC enters the LPI mode only after all outstanding frames (in the core) and pending frames (in the application interface) have been transmitted. The MAC comes out of the LPI mode when the application sends any frame for transmission or the application issues a TX FIFO Flush command. In addition, the MAC automatically clears the LPIEN bit when it exits the LPI state. If TX FIFO Flush is set in Bit 20 of Register 6 (Operation Mode Register), when the MAC is in the LPI mode, the MAC exits the LPI mode. When this bit is 0, the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode. + 19 + 1 + read-write + + + PLSEN + PHY Link Status Enable +This bit enables the link status received on the RGMII, SGMII, or SMII receive paths to be used for activating the LPI LS TIMER. When set, the MAC uses the link-status bits of Register 54 (SGMII/RGMII/SMII Control and Status Register) and Bit 17 (PLS) for the LPI LS Timer trigger. When cleared, the MAC ignores the link-status bits of Register 54 and takes only the PLS bit. This bit is RO and reserved if you have not selected the RGMII, SGMII, or SMII PHY interface. + 18 + 1 + read-write + + + PLS + PHY Link Status +This bit indicates the link status of the PHY. The MAC Transmitter asserts the LPI pattern only when the link status is up (okay) at least for the time indicated by the LPI LS TIMER. When set, the link is considered to be okay (up) and when reset, the link is considered to be down. + 17 + 1 + read-write + + + LPIEN + LPI Enable +When set, this bit instructs the MAC Transmitter to enter the LPI state. When reset, this bit instructs the MAC to exit the LPI state and resume normal transmission. This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission. + 16 + 1 + read-write + + + RLPIST + Receive LPI State +When set, this bit indicates that the MAC is receiving the LPI pattern on the GMII or MII interface. + 9 + 1 + read-write + + + TLPIST + Transmit LPI State +When set, this bit indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface. + 8 + 1 + read-write + + + RLPIEX + Receive LPI Exit +When set, this bit indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the normal reception. This bit is cleared by a read into this register. Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. + 3 + 1 + read-write + + + RLPIEN + Receive LPI Entry +When set, this bit indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register. Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. + 2 + 1 + read-write + + + TLPIEX + Transmit LPI Exit +When set, this bit indicates that the MAC transmitter has exited the LPI state after the user has cleared the LPIEN bit and the LPI TW Timer has expired. This bit is cleared by a read into this register. + 1 + 1 + read-write + + + TLPIEN + Transmit LPI Entry + When set, this bit indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register. + 0 + 1 + read-write + + + + + LPI_TCR + LPI Timers Control Register + 0x34 + 32 + 0x00000000 + 0x03FFFFFF + + + LST + LPI LS TIMER +This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count. The default value of the LPI LS Timer is 1000 (1 sec) as defined in the IEEE standard. + 16 + 10 + read-write + + + TWT + LPI TW TIMER +This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission. The TLPIEX status bit is set after the expiry of this timer. + 0 + 16 + read-write + + + + + INTR_STATUS + Interrupt Status Register + 0x38 + 32 + 0x00000000 + 0x00000EFF + + + GPIIS + GPI Interrupt Status +When the GPIO feature is enabled, this bit is set when any active event (LL or LH) occurs on the GPIS field (Bits [3:0]) of Register 56 (General Purpose IO Register) and the corresponding GPIE bit is enabled. This bit is cleared on reading lane 0 (GPIS) of Register 56 (General Purpose IO Register). When the GPIO feature is not enabled, this bit is reserved. + 11 + 1 + read-only + + + LPIIS + LPI Interrupt Status +When the Energy Efficient Ethernet feature is enabled, this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. This bit is cleared on reading Bit 0 of Register 12 (LPI Control and Status Register). In all other modes, this bit is reserved. + 10 + 1 + read-only + + + TSIS + Timestamp Interrupt Status +When the Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true: - The system time value equals or exceeds the value specified in the Target Time High and Low registers. - There is an overflow in the seconds register. - The Auxiliary snapshot trigger is asserted. This bit is cleared on reading Bit 0 of Register 458 (Timestamp Status Register). + 9 + 1 + read-only + + + MMCRXIPIS + MMC Receive Checksum Offload Interrupt Status +This bit is set high when an interrupt is generated in the MMC Receive Checksum Offload Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. + 7 + 1 + read-only + + + MMCTXIS + MMC Transmit Interrupt Status +This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. + 6 + 1 + read-only + + + MMCRXIS + MMC Receive Interrupt Status +This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. + 5 + 1 + read-only + + + MMCIS + MMC Interrupt Status +This bit is set high when any of the Bits [7:5] is set high and cleared only when all of these bits are low. + 4 + 1 + read-only + + + PMTIS + PMT Interrupt Status +This bit is set when a magic packet or remote wake-up frame is received in the power-down mode (see Bits 5 and 6 in the PMT Control and Status Register). This bit is cleared when both Bits[6:5] are cleared because of a read operation to the PMT Control and Status register. + 3 + 1 + read-only + + + PCSANCIS + PCS Auto-Negotiation Complete +This bit is set when the Auto-negotiation is completed in the TBI, RTBI, or SGMII PHY interface (Bit 5 in Register 49 (AN Status Register)). This bit is cleared when you perform a read operation to the AN Status register. + 2 + 1 + read-only + + + PCSLCHGIS + PCS Link Status Changed +This bit is set because of any change in Link Status in the TBI, RTBI, or SGMII PHY interface (Bit 2 in Register 49 (AN Status Register)). This bit is cleared when you perform a read operation on the AN Status register. + 1 + 1 + read-only + + + RGSMIIIS + RGMII or SMII Interrupt Status +This bit is set because of any change in value of the Link Status of RGMII or SMII interface (Bit 3 in Register 54 (SGMII/RGMII/SMII Control and Status Register)). This bit is cleared when you perform a read operation on the SGMII/RGMII/SMII Control and Status Register. + 0 + 1 + read-only + + + + + INTR_MASK + Interrupt Mask Register + 0x3c + 32 + 0x00000000 + 0x0000060F + + + LPIIM + LPI Interrupt Mask +When set, this bit disables the assertion of the interrupt signal because of the setting of the LPI Interrupt Status bit in Register 14 (Interrupt Status Register). + 10 + 1 + read-write + + + TSIM + Timestamp Interrupt Mask + When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Register 14 (Interrupt Status Register). + 9 + 1 + read-write + + + PMTIM + PMT Interrupt Mask + When set, this bit disables the assertion of the interrupt signal because of the setting of PMT Interrupt Status bit in Register 14 (Interrupt Status Register). + 3 + 1 + read-write + + + PCSANCIM + PCS AN Completion Interrupt Mask +When set, this bit disables the assertion of the interrupt signal because of the setting of PCS Auto-negotiation complete bit in Register 14 (Interrupt Status Register). + 2 + 1 + read-write + + + PCSLCHGIM + PCS Link Status Interrupt Mask +When set, this bit disables the assertion of the interrupt signal because of the setting of the PCS Link-status changed bit in Register 14 (Interrupt Status Register). + 1 + 1 + read-write + + + RGSMIIIM + RGMII or SMII Interrupt Mask +When set, this bit disables the assertion of the interrupt signal because of the setting of the RGMII or SMII Interrupt Status bit in Register 14 (Interrupt Status Register). + 0 + 1 + read-write + + + + + MAC_ADDR_0_HIGH + MAC Address 0 High Register + 0x40 + 32 + 0x00000000 + 0x8000FFFF + + + AE + Address Enable + This bit is RO. The bit value is fixed at 1. + 31 + 1 + read-only + + + ADDRHI + MAC Address0 [47:32] + This field contains the upper 16 bits (47:32) of the first 6-byte MAC address. The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. + 0 + 16 + read-write + + + + + MAC_ADDR_0_LOW + MAC Address 0 Low Register + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDRLO + MAC Address0 [31:0] + This field contains the lower 32 bits of the first 6-byte MAC address. This is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. + 0 + 32 + read-write + + + + + 4 + 0x8 + 1,2,3,4 + MAC_ADDR[%s] + no description available + 0x48 + + HIGH + MAC Address High Register + 0x0 + 32 + 0x00000000 + 0xFF00FFFF + + + AE + Address Enable +When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. + 31 + 1 + read-write + + + SA + Source Address +When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received frame. + 30 + 1 + read-write + + + MBC + Mask Byte Control +These bits are mask control bits for comparison of each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows: - Bit 29: Register 18[15:8] - Bit 28: Register 18[7:0] - Bit 27: Register 19[31:24] - ... - Bit 24: Register 19[7:0] You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. + 24 + 6 + read-write + + + ADDRHI + MAC Address1 [47:32] +This field contains the upper 16 bits (47:32) of the second 6-byte MAC address. + 0 + 16 + read-write + + + + + LOW + MAC Address Low Register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDRLO + MAC Address1 [31:0] +This field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process. + 0 + 32 + read-write + + + + + + XMII_CSR + SGMII/RGMII/SMII Control and Status Register + 0xd8 + 32 + 0x00000000 + 0x0000003F + + + FALSCARDET + False Carrier Detected + This bit indicates whether the SMII PHY detected false carrier (1'b1). This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. + 5 + 1 + read-write + + + JABTO + Jabber Timeout + This bit indicates whether there is jabber timeout error (1'b1) in the received frame. This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. + 4 + 1 + read-write + + + LNKSTS + Link Status + This bit indicates whether the link between the local PHY and the remote PHY is up or down. It gives the status of the link between the SGMII of MAC and the SGMII of the local PHY. The status bits are received from the local PHY during ANEG betweent he MAC and PHY on the SGMII link. + 3 + 1 + read-write + + + LNKSPEED + Link Speed + This bit indicates the current speed of the link: +- 00: 2.5 MHz +- 01: 25 MHz +- 10: 125 MHz Bit 2 is reserved when the MAC is configured for the SMII PHY interface. + 1 + 2 + read-write + + + LNKMOD + Link Mode + This bit indicates the current mode of operation of the link: +- 1’b0: Half-duplex mode +- 1’b1: Full-duplex mode + 0 + 1 + read-write + + + + + WDOG_WTO + Watchdog Timeout Register + 0xdc + 32 + 0x00000000 + 0x00013FFF + + + PWE + Programmable Watchdog Enable + When this bit is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, the WTO field (Bits[13:0]) is used as watchdog timeout for a received frame. When this bit is cleared, the watchdog timeout for a received frame is controlled by the setting of Bit 23 (WD) and Bit 20 (JE) in Register 0 (MAC Configuration Register). + 16 + 1 + read-write + + + WTO + Watchdog Timeout +When Bit 16 (PWE) is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, this field is used as watchdog timeout for a received frame. If the length of a received frame exceeds the value of this field, such frame is terminated and declared as an error frame. Note: When Bit 16 (PWE) is set, the value in this field should be more than 1,522 (0x05F2). Otherwise, the IEEE Std 802.3-specified valid tagged frames are declared as error frames and are dropped. + 0 + 14 + read-write + + + + + mmc_cntrl + MMC Control establishes the operating mode of MMC. + 0x100 + 32 + 0x00000000 + 0x0000013F + + + UCDBC + Update MMC Counters for Dropped Broadcast Frames +When set, the MAC updates all related MMC Counters for Broadcast frames that are dropped because of the setting of Bit 5 (DBF) of Register 1 (MAC Frame Filter). When reset, the MMC Counters are not updated for dropped Broadcast frames. + 8 + 1 + read-write + + + CNTPRSTLVL + Full-Half Preset +When this bit is low and Bit 4 is set, all MMC counters get preset to almost-half value. All octet counters get preset to 0x7FFF_F800 (half +- 2KBytes) and all frame-counters gets preset to 0x7FFF_FFF0 (half +- 16). When this bit is high and Bit 4 is set, all MMC counters get preset to almost-full value. All octet counters get preset to 0xFFFF_F800 (full +- 2KBytes) and all frame-counters gets preset to 0xFFFF_FFF0 (full +- 16). For 16-bit counters, the almost-half preset values are 0x7800 and 0x7FF0 for the respective octet and frame counters. Similarly, the almost-full preset values for the 16-bit counters are 0xF800 and 0xFFF0. + 5 + 1 + read-write + + + CNTPRST + Counters Preset +When this bit is set, all counters are initialized or preset to almost full or almost half according to Bit 5. This bit is cleared automatically after 1 clock cycle. This bit, along with Bit 5, is useful for debugging and testing the assertion of interrupts because of MMC counter becoming half-full or full. + 4 + 1 + read-write + + + CNTFREEZ + MMC Counter Freeze +When this bit is set, it freezes all MMC counters to their current value. Until this bit is reset to 0, no MMC counter is updated because of any transmitted or received frame. If any MMC counter is read with the Reset on Read bit set, then that counter is also cleared in this mode. + 3 + 1 + read-write + + + RSTONRD + Reset on Read +When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset). The counters are cleared when the least significant byte lane (Bits[7:0]) is read. + 2 + 1 + read-write + + + CNTSTOPRO + Counter Stop Rollover +When this bit is set, the counter does not roll over to zero after reaching the maximum value. + 1 + 1 + read-write + + + CNTRST + Counters Reset +When this bit is set, all counters are reset. This bit is cleared automatically after 1 clock cycle + 0 + 1 + read-write + + + + + mmc_intr_rx + MMC Receive Interrupt maintains the interrupt generated from all +of the receive statistic counters. + 0x104 + 32 + 0x00000000 + 0x03FFFFFF + + + RXCTRLFIS + MMC Receive Control Frame Counter Interrupt Status +This bit is set when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. + 25 + 1 + read-write + + + RXRCVERRFIS + MMC Receive Error Frame Counter Interrupt Status +This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value. + 24 + 1 + read-write + + + RXWDOGFIS + MMC Receive Watchdog Error Frame Counter Interrupt Status +This bit is set when the rxwatchdog error counter reaches half of the maximum value or the maximum value. + 23 + 1 + read-write + + + RXVLANGBFIS + MMC Receive VLAN Good Bad Frame Counter Interrupt Status +This bit is set when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. + 22 + 1 + read-write + + + RXFOVFIS + MMC Receive FIFO Overflow Frame Counter Interrupt Status +This bit is set when the rxfifooverflow counter reaches half of the maximum value or the maximum value. + 21 + 1 + read-write + + + RXPAUSFIS + MMC Receive Pause Frame Counter Interrupt Status +This bit is set when the rxpauseframes counter reaches half of the maximum value or the maximum value. + 20 + 1 + read-write + + + RXORANGEFIS + MMC Receive Out Of Range Error Frame Counter Interrupt Status. +This bit is set when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. + 19 + 1 + read-write + + + RXLENERFIS + MMC Receive Length Error Frame Counter Interrupt Status +This bit is set when the rxlengtherror counter reaches half of the maximum value or the maximum value. + 18 + 1 + read-write + + + RXUCGFIS + MMC Receive Unicast Good Frame Counter Interrupt Status +This bit is set when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. + 17 + 1 + read-write + + + RX1024TMAXOCTGBFIS + MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status. +This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. + 16 + 1 + read-write + + + RX512T1023OCTGBFIS + MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. + 15 + 1 + read-write + + + RX256T511OCTGBFIS + MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. + 14 + 1 + read-write + + + RX128T255OCTGBFIS + MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. + 13 + 1 + read-write + + + RX65T127OCTGBFIS + MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. + 12 + 1 + read-write + + + RX64OCTGBFIS + MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value. + 11 + 1 + read-write + + + RXOSIZEGFIS + MMC Receive Oversize Good Frame Counter Interrupt Status +This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value. + 10 + 1 + read-write + + + RXUSIZEGFIS + MMC Receive Undersize Good Frame Counter Interrupt Status +This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value. + 9 + 1 + read-write + + + RXJABERFIS + MMC Receive Jabber Error Frame Counter Interrupt Status +This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value. + 8 + 1 + read-write + + + RXRUNTFIS + MMC Receive Runt Frame Counter Interrupt Status +This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value. + 7 + 1 + read-write + + + RXALGNERFIS + MMC Receive Alignment Error Frame Counter Interrupt Status +This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value. + 6 + 1 + read-write + + + RXCRCERFIS + MMC Receive CRC Error Frame Counter Interrupt Status +This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value. + 5 + 1 + read-write + + + RXMCGFIS + MMC Receive Multicast Good Frame Counter Interrupt Status +This bit is set when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. + 4 + 1 + read-write + + + RXBCGFIS + MMC Receive Broadcast Good Frame Counter Interrupt Status +This bit is set when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. + 3 + 1 + read-write + + + RXGOCTIS + MMC Receive Good Octet Counter Interrupt Status +This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. + 2 + 1 + read-write + + + RXGBOCTIS + MMC Receive Good Bad Octet Counter Interrupt Status +This bit is set when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. + 1 + 1 + read-write + + + RXGBFRMIS + MMC Receive Good Bad Frame Counter Interrupt Status +This bit is set when the rxframecount_gb counter reaches half of the maximum value or the maximum value. + 0 + 1 + read-write + + + + + mmc_intr_tx + MMC Transmit Interrupt maintains the interrupt generated from all +of the transmit statistic counters + 0x108 + 32 + 0x00000000 + 0x03FFFFFF + + + TXOSIZEGFIS + MMC Transmit Oversize Good Frame Counter Interrupt Status +This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value. + 25 + 1 + read-write + + + TXVLANGFIS + MMC Transmit VLAN Good Frame Counter Interrupt Status +This bit is set when the txvlanframes_g counter reaches half of the maximum value or the maximum value. + 24 + 1 + read-write + + + TXPAUSFIS + MMC Transmit Pause Frame Counter Interrupt Status +This bit is set when the txpauseframeserror counter reaches half of the maximum value or the maximum value. + 23 + 1 + read-write + + + TXEXDEFFIS + MMC Transmit Excessive Deferral Frame Counter Interrupt Status +This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value. + 22 + 1 + read-write + + + TXGFRMIS + MMC Transmit Good Frame Counter Interrupt Status +This bit is set when the txframecount_g counter reaches half of the maximum value or the maximum value. + 21 + 1 + read-write + + + TXGOCTIS + MMC Transmit Good Octet Counter Interrupt Status +This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value. + 20 + 1 + read-write + + + TXCARERFIS + MMC Transmit Carrier Error Frame Counter Interrupt Status +This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value. + 19 + 1 + read-write + + + TXEXCOLFIS + MMC Transmit Excessive Collision Frame Counter Interrupt Status +This bit is set when the txexesscol counter reaches half of the maximum value or the maximum value. + 18 + 1 + read-write + + + TXLATCOLFIS + MMC Transmit Late Collision Frame Counter Interrupt Status +This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value. + 17 + 1 + read-write + + + TXDEFFIS + MMC Transmit Deferred Frame Counter Interrupt Status +This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value. + 16 + 1 + read-write + + + TXMCOLGFIS + MMC Transmit Multiple Collision Good Frame Counter Interrupt Status +This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value. + 15 + 1 + read-write + + + TXSCOLGFIS + MMC Transmit Single Collision Good Frame Counter Interrupt Status +This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value. + 14 + 1 + read-write + + + TXUFLOWERFIS + MMC Transmit Underflow Error Frame Counter Interrupt Status +This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value. + 13 + 1 + read-write + + + TXBCGBFIS + MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status +This bit is set when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. + 12 + 1 + read-write + + + TXMCGBFIS + MMC Transmit Multicast Good Bad Frame Counter Interrupt Status +The bit is set when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. + 11 + 1 + read-write + + + TXUCGBFIS + MMC Transmit Unicast Good Bad Frame Counter Interrupt Status +This bit is set when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. + 10 + 1 + read-write + + + TX1024TMAXOCTGBFIS + MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status +This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. + 9 + 1 + read-write + + + TX512T1023OCTGBFIS + MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. + 8 + 1 + read-write + + + TX256T511OCTGBFIS + MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. + 7 + 1 + read-write + + + TX128T255OCTGBFIS + MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. + 6 + 1 + read-write + + + TX65T127OCTGBFIS + MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the tx65to127octets_gb counter reaches half the maximum value, and also when it reaches the maximum value. + 5 + 1 + read-write + + + TX64OCTGBFIS + MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value. + 4 + 1 + read-write + + + TXMCGFIS + MMC Transmit Multicast Good Frame Counter Interrupt Status +This bit is set when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. + 3 + 1 + read-write + + + TXBCGFIS + MMC Transmit Broadcast Good Frame Counter Interrupt Status +This bit is set when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. + 2 + 1 + read-write + + + TXGBFRMIS + MMC Transmit Good Bad Frame Counter Interrupt Status +This bit is set when the txframecount_gb counter reaches half of the maximum value or the maximum value. + 1 + 1 + read-write + + + TXGBOCTIS + MMC Transmit Good Bad Octet Counter Interrupt Status +This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. + 0 + 1 + read-write + + + + + mmc_intr_mask_rx + MMC Receive Interrupt mask maintains the mask for the interrupt +generated from all of the receive statistic counters + 0x10c + 32 + 0x00000000 + 0x03FFFFFE + + + RXCTRLFIM + MMC Receive Control Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. + 25 + 1 + read-write + + + RXRCVERRFIM + MMC Receive Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value. + 24 + 1 + read-write + + + RXWDOGFIM + MMC Receive Watchdog Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value. + 23 + 1 + read-write + + + RXVLANGBFIM + MMC Receive VLAN Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. + 22 + 1 + read-write + + + RXFOVFIM + MMC Receive FIFO Overflow Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value. + 21 + 1 + read-write + + + RXPAUSFIM + MMC Receive Pause Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxpauseframes counter reaches half of the maximum value or the maximum value. + 20 + 1 + read-write + + + RXORANGEFIM + MMC Receive Out Of Range Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. + 19 + 1 + read-write + + + RXLENERFIM + MMC Receive Length Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value. + 18 + 1 + read-write + + + RXUCGFIM + MMC Receive Unicast Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. + 17 + 1 + read-write + + + RX1024TMAXOCTGBFIM + MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask. +Setting this bit masks the interrupt when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. + 16 + 1 + read-write + + + RX512T1023OCTGBFIM + MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. + 15 + 1 + read-write + + + RX256T511OCTGBFIM + MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. + 14 + 1 + read-write + + + RX128T255OCTGBFIM + MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. + 13 + 1 + read-write + + + RX65T127OCTGBFIM + MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. + 12 + 1 + read-write + + + RX64OCTGBFIM + MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value. + 11 + 1 + read-write + + + RXOSIZEGFIM + MMC Receive Oversize Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value. + 10 + 1 + read-write + + + RXUSIZEGFIM + MMC Receive Undersize Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value. + 9 + 1 + read-write + + + RXJABERFIM + MMC Receive Jabber Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value. + 8 + 1 + read-write + + + RXRUNTFIM + MMC Receive Runt Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value. + 7 + 1 + read-write + + + RXALGNERFIM + MMC Receive Alignment Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value. + 6 + 1 + read-write + + + RXCRCERFIM + MMC Receive CRC Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value. + 5 + 1 + read-write + + + RXMCGFIM + MMC Receive Multicast Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. + 4 + 1 + read-write + + + RXBCGFIM + MMC Receive Broadcast Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. + 3 + 1 + read-write + + + RXGOCTIM + MMC Receive Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. + 2 + 1 + read-write + + + RXGBOCTIM + MMC Receive Good Bad Octet Counter Interrupt Mask. +Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. + 1 + 1 + read-write + + + + + mmc_intr_mask_tx + MMC Transmit Interrupt Mask + 0x110 + 32 + 0x00000000 + 0x03FFFFFF + + + TXOSIZEGFIM + MMC Transmit Oversize Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value. + 25 + 1 + read-write + + + TXVLANGFIM + MMC Transmit VLAN Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txvlanframes_g counter reaches half of the maximum value or the maximum value. + 24 + 1 + read-write + + + TXPAUSFIM + MMC Transmit Pause Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txpauseframes counter reaches half of the maximum value or the maximum value. + 23 + 1 + read-write + + + TXEXDEFFIM + MMC Transmit Excessive Deferral Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value. + 22 + 1 + read-write + + + TXGFRMIM + MMC Transmit Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txframecount_g counter reaches half of the maximum value or the maximum value. + 21 + 1 + read-write + + + TXGOCTIM + MMC Transmit Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value. + 20 + 1 + read-write + + + TXCARERFIM + MMC Transmit Carrier Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value. + 19 + 1 + read-write + + + TXEXCOLFIM + MMC Transmit Excessive Collision Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value. + 18 + 1 + read-write + + + TXLATCOLFIM + MMC Transmit Late Collision Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value. + 17 + 1 + read-write + + + TXDEFFIM + MMC Transmit Deferred Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value. + 16 + 1 + read-write + + + TXMCOLGFIM + MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value. + 15 + 1 + read-write + + + TXSCOLGFIM + MMC Transmit Single Collision Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value. + 14 + 1 + read-write + + + TXUFLOWERFIM + MMC Transmit Underflow Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value. + 13 + 1 + read-write + + + TXBCGBFIM + MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. + 12 + 1 + read-write + + + TXMCGBFIM + MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. + 11 + 1 + read-write + + + TXUCGBFIM + MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. + 10 + 1 + read-write + + + TX1024TMAXOCTGBFIM + MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. + 9 + 1 + read-write + + + TX512T1023OCTGBFIM + MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. + 8 + 1 + read-write + + + TX256T511OCTGBFIM + MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. + 7 + 1 + read-write + + + TX128T255OCTGBFIM + MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. + 6 + 1 + read-write + + + TX65T127OCTGBFIM + MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value. + 5 + 1 + read-write + + + TX64OCTGBFIM + MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value. + 4 + 1 + read-write + + + TXMCGFIM + MMC Transmit Multicast Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. + 3 + 1 + read-write + + + TXBCGFIM + MMC Transmit Broadcast Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. + 2 + 1 + read-write + + + TXGBFRMIM + MMC Transmit Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txframecount_gb counter reaches half of the maximum value or the maximum value. + 1 + 1 + read-write + + + TXGBOCTIM + MMC Transmit Good Bad Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. + 0 + 1 + read-write + + + + + txoctetcount_gb + Number of bytes transmitted, exclusive of preamble and retried +bytes, in good and bad frames. + 0x114 + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes transmitted, exclusive of preamble and retried bytes, in good and bad frames. + 0 + 32 + read-write + + + + + txframecount_gb + Number of good and bad frames transmitted, exclusive of retried +frames. + 0x118 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted, exclusive of retried frames. + 0 + 32 + read-write + + + + + txbroadcastframes_g + Number of good broadcast frames transmitted + 0x11c + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good broadcast frames transmitted. + 0 + 32 + read-write + + + + + txmlticastframes_g + Number of good multicast frames transmitted + 0x120 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good multicast frames transmitted. + 0 + 32 + read-write + + + + + tx64octets_gb + Number of good and bad frames transmitted with length 64 bytes, +exclusive of preamble and retried frames. + 0x124 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted with length 64 bytes, exclusive of preamble and retried frames. + 0 + 32 + read-write + + + + + tx65to127octets_gb + Number of good and bad frames transmitted with length between +65 and 127 (inclusive) bytes, exclusive of preamble and retried +frames. + 0x128 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 32 + read-write + + + + + tx128to255octets_gb + Number of good and bad frames transmitted with length between +128 and 255 (inclusive) bytes, exclusive of preamble and retried +frames. + 0x12c + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted with length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 32 + read-write + + + + + tx256to511octets_gb + Number of good and bad frames transmitted with length between +256 and 511 (inclusive) bytes, exclusive of preamble and retried +frames. + 0x130 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted with length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 32 + read-write + + + + + tx512to1023octets_gb + Number of good and bad frames transmitted with length between +512 and 1,023 (inclusive) bytes, exclusive of preamble and retried +frames. + 0x134 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 32 + read-write + + + + + tx1024tomaxoctets_gb + Number of good and bad frames transmitted with length between +1,024 and maxsize (inclusive) bytes, exclusive of preamble and +retried frames. + 0x138 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 32 + read-write + + + + + rxframecount_gb + Number of good and bad frames received + 0x180 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames received. + 0 + 32 + read-write + + + + + mmc_ipc_intr_mask_rx + MMC IPC Receive Checksum Offload Interrupt Mask maintains +the mask for the interrupt generated from the receive IPC statistic +counters. + 0x200 + 32 + 0x00000000 + 0x3FFF3FFF + + + RXICMPEROIM + MMC Receive ICMP Error Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. + 29 + 1 + read-write + + + RXICMPGOIM + MMC Receive ICMP Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. + 28 + 1 + read-write + + + RXTCPEROIM + MMC Receive TCP Error Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. + 27 + 1 + read-write + + + RXTCPGOIM + MMC Receive TCP Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value. + 26 + 1 + read-write + + + RXUDPEROIM + MMC Receive UDP Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. + 25 + 1 + read-write + + + RXUDPGOIM + MMC Receive IPV6 No Payload Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. + 24 + 1 + read-write + + + RXIPV6NOPAYOIM + MMC Receive IPV6 Header Error Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. + 23 + 1 + read-write + + + RXIPV6HEROIM + MMC Receive IPV6 Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. + 22 + 1 + read-write + + + RXIPV6GOIM + MMC Receive IPV6 Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. + 21 + 1 + read-write + + + RXIPV4UDSBLOIM + MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. + 20 + 1 + read-write + + + RXIPV4FRAGOIM + MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. + 19 + 1 + read-write + + + RXIPV4NOPAYOIM + MMC Receive IPV4 No Payload Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. + 18 + 1 + read-write + + + RXIPV4HEROIM + MMC Receive IPV4 Header Error Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. + 17 + 1 + read-write + + + RXIPV4GOIM + MMC Receive IPV4 Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. + 16 + 1 + read-write + + + RXICMPERFIM + MMC Receive ICMP Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. + 13 + 1 + read-write + + + RXICMPGFIM + MMC Receive ICMP Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. + 12 + 1 + read-write + + + RXTCPERFIM + MMC Receive TCP Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. + 11 + 1 + read-write + + + RXTCPGFIM + MMC Receive TCP Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. + 10 + 1 + read-write + + + RXUDPERFIM + MMC Receive UDP Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. + 9 + 1 + read-write + + + RXUDPGFIM + MMC Receive UDP Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. + 8 + 1 + read-write + + + RXIPV6NOPAYFIM + MMC Receive IPV6 No Payload Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. + 7 + 1 + read-write + + + RXIPV6HERFIM + MMC Receive IPV6 Header Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. + 6 + 1 + read-write + + + RXIPV6GFIM + MMC Receive IPV6 Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. + 5 + 1 + read-write + + + RXIPV4UDSBLFIM + MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. + 4 + 1 + read-write + + + RXIPV4FRAGFIM + MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. + 3 + 1 + read-write + + + RXIPV4NOPAYFIM + MMC Receive IPV4 No Payload Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. + 2 + 1 + read-write + + + RXIPV4HERFIM + MMC Receive IPV4 Header Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. + 1 + 1 + read-write + + + RXIPV4GFIM + MMC Receive IPV4 Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. + 0 + 1 + read-write + + + + + mmc_ipc_intr_rx + MMC Receive Checksum Offload Interrupt maintains the interrupt +that the receive IPC statistic counters generate. See Table 4-25 +for further detail. + 0x208 + 32 + 0x00000000 + 0x3FFF3FFF + + + RXICMPEROIS + MMC Receive ICMP Error Octet Counter Interrupt Status +This bit is set when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. + 29 + 1 + read-write + + + RXICMPGOIS + MMC Receive ICMP Good Octet Counter Interrupt Status +This bit is set when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. + 28 + 1 + read-write + + + RXTCPEROIS + MMC Receive TCP Error Octet Counter Interrupt Status +This bit is set when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. + 27 + 1 + read-write + + + RXTCPGOIS + MMC Receive TCP Good Octet Counter Interrupt Status +This bit is set when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value + 26 + 1 + read-write + + + RXUDPEROIS + MMC Receive UDP Error Octet Counter Interrupt Status +This bit is set when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. + 25 + 1 + read-write + + + RXUDPGOIS + MMC Receive UDP Good Octet Counter Interrupt Status +This bit is set when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. + 24 + 1 + read-write + + + RXIPV6NOPAYOIS + MMC Receive IPV6 No Payload Octet Counter Interrupt Status +This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. + 23 + 1 + read-write + + + RXIPV6HEROIS + MMC Receive IPV6 Header Error Octet Counter Interrupt Status +This bit is set when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. + 22 + 1 + read-write + + + RXIPV6GOIS + MMC Receive IPV6 Good Octet Counter Interrupt Status +This bit is set when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. + 21 + 1 + read-write + + + RXIPV4UDSBLOIS + MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status +This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. + 20 + 1 + read-write + + + RXIPV4FRAGOIS + MMC Receive IPV4 Fragmented Octet Counter Interrupt Status +This bit is set when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. + 19 + 1 + read-write + + + RXIPV4NOPAYOIS + MMC Receive IPV4 No Payload Octet Counter Interrupt Status +This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. + 18 + 1 + read-write + + + RXIPV4HEROIS + MMC Receive IPV4 Header Error Octet Counter Interrupt Status +This bit is set when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. + 17 + 1 + read-write + + + RXIPV4GOIS + MMC Receive IPV4 Good Octet Counter Interrupt Status +This bit is set when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. + 16 + 1 + read-write + + + RXICMPERFIS + MMC Receive ICMP Error Frame Counter Interrupt Status +This bit is set when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. + 13 + 1 + read-write + + + RXICMPGFIS + MMC Receive ICMP Good Frame Counter Interrupt Status +This bit is set when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. + 12 + 1 + read-write + + + RXTCPERFIS + MMC Receive TCP Error Frame Counter Interrupt Status +This bit is set when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. + 11 + 1 + read-write + + + RXTCPGFIS + MMC Receive TCP Good Frame Counter Interrupt Status +This bit is set when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. + 10 + 1 + read-write + + + RXUDPERFIS + MMC Receive UDP Error Frame Counter Interrupt Status +This bit is set when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. + 9 + 1 + read-write + + + RXUDPGFIS + MMC Receive UDP Good Frame Counter Interrupt Status +This bit is set when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. + 8 + 1 + read-write + + + RXIPV6NOPAYFIS + MMC Receive IPV6 No Payload Frame Counter Interrupt Status +This bit is set when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. + 7 + 1 + read-write + + + RXIPV6HERFIS + MMC Receive IPV6 Header Error Frame Counter Interrupt Status +This bit is set when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. + 6 + 1 + read-write + + + RXIPV6GFIS + MMC Receive IPV6 Good Frame Counter Interrupt Status +This bit is set when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. + 5 + 1 + read-write + + + RXIPV4UDSBLFIS + MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status +This bit is set when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. + 4 + 1 + read-write + + + RXIPV4FRAGFIS + MMC Receive IPV4 Fragmented Frame Counter Interrupt Status +This bit is set when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. + 3 + 1 + read-write + + + RXIPV4NOPAYFIS + MMC Receive IPV4 No Payload Frame Counter Interrupt Status +This bit is set when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. + 2 + 1 + read-write + + + RXIPV4HERFIS + MMC Receive IPV4 Header Error Frame Counter Interrupt Status +This bit is set when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. + 1 + 1 + read-write + + + RXIPV4GFIS + MMC Receive IPV4 Good Frame Counter Interrupt Status +This bit is set when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. + 0 + 1 + read-write + + + + + rxipv4_gd_fms + Number of good IPv4 datagrams received with the TCP, UDP, or +ICMP payload + 0x210 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload + 0 + 32 + read-write + + + + + 1 + 0x20 + 0 + L3_L4_CFG[%s] + no description available + 0x400 + + L3_L4_CTRL + Layer 3 and Layer 4 Control Register + 0x0 + 32 + 0x00000000 + 0x003DFFFD + + + L4DPIM0 + Layer 4 Destination Port Inverse Match Enable + When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. + 21 + 1 + read-write + + + L4DPM0 + Layer 4 Destination Port Match Enable + When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching. + 20 + 1 + read-write + + + L4SPIM0 + Layer 4 Source Port Inverse Match Enable +When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. + 19 + 1 + read-write + + + L4SPM0 + Layer 4 Source Port Match Enable +When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. + 18 + 1 + read-write + + + L4PEN0 + Layer 4 Protocol Enable +When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. + 16 + 1 + read-write + + + L3HDBM0 + Layer 3 IP DA Higher Bits Match + IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - ... +- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - … +- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. + 11 + 5 + read-write + + + L3HSBM0 + Layer 3 IP SA Higher Bits Match + IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - ... +- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. + 6 + 5 + read-write + + + L3DAIM0 + Layer 3 IP DA Inverse Match Enable +When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. + 5 + 1 + read-write + + + L3DAM0 + Layer 3 IP DA Match Enable +When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. + 4 + 1 + read-write + + + L3SAIM0 + Layer 3 IP SA Inverse Match Enable +When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. + 3 + 1 + read-write + + + L3SAM0 + Layer 3 IP SA Match Enable +When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. + 2 + 1 + read-write + + + L3PEN0 + Layer 3 Protocol Enable + When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. + 0 + 1 + read-write + + + + + L4_Addr + Layer 4 Address Register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + L4DP0 + Layer 4 Destination Port Number Field +When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. + 16 + 16 + read-write + + + L4SP0 + Layer 4 Source Port Number Field + When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. + 0 + 16 + read-write + + + + + L3_Addr_0 + Layer 3 Address 0 Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A00 + Layer 3 Address 0 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Source Address field in the IPv4 frames. + 0 + 32 + read-write + + + + + L3_Addr_1 + Layer 3 Address 1 Register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A10 + Layer 3 Address 1 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. + 0 + 32 + read-write + + + + + L3_Addr_2 + Layer 3 Address 2 Register + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A20 + Layer 3 Address 2 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. + 0 + 32 + read-write + + + + + L3_Addr_3 + Layer 3 Address 3 Register + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A30 + Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. + 0 + 32 + read-write + + + + + + VLAN_TAG_INC_RPL + VLAN Tag Inclusion or Replacement Register + 0x584 + 32 + 0x00000000 + 0x000FFFFF + + + CSVL + C-VLAN or S-VLAN + When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted frames. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the transmitted frames. + 19 + 1 + read-write + + + VLP + VLAN Priority Control +When this bit is set, the control Bits [17:16] are used for VLAN deletion, insertion, or replacement. When this bit is reset, the mti_vlan_ctrl_i control input is used, and Bits [17:16] are ignored. + 18 + 1 + read-write + + + VLC + VLAN Tag Control in Transmit Frames +- 2’b00: No VLAN tag deletion, insertion, or replacement +- 2’b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted frames with VLAN tags. +- 2’b10: VLAN tag insertion The MAC inserts VLT in bytes 15 and 16 of the frame after inserting the Type value (0x8100/0x88a8) in bytes 13 and 14. This operation is performed on all transmitted frames, irrespective of whether they already have a VLAN tag. +- 2’b11: VLAN tag replacement The MAC replaces VLT in bytes 15 and 16 of all VLAN-type transmitted frames (Bytes 13 and 14 are 0x8100/0x88a8). Note: Changes to this field take effect only on the start of a frame. If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, that is, the current frame does not use the updated value. + 16 + 2 + read-write + + + VLT + VLAN Tag for Transmit Frames + This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. Bits[15:13] are the User Priority, Bit 12 is the CFI/DEI, and Bits[11:0] are the VLAN tag’s VID field. + 0 + 16 + read-write + + + + + VLAN_HASH + VLAN Hash Table Register + 0x588 + 32 + 0x00000000 + 0x0000FFFF + + + VLHT + VLAN Hash Table + This field contains the 16-bit VLAN Hash Table. + 0 + 16 + read-write + + + + + TS_CTRL + Timestamp Control Register + 0x700 + 32 + 0x00000000 + 0x1F07FF3F + + + ATSEN3 + Auxiliary Snapshot 3 Enable +This field controls capturing the Auxiliary Snapshot Trigger 3. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[3] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than four. + 28 + 1 + read-write + + + ATSEN2 + Auxiliary Snapshot 2 Enable +This field controls capturing the Auxiliary Snapshot Trigger 2. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[2] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than three. + 27 + 1 + read-write + + + ATSEN1 + Auxiliary Snapshot 1 Enable +This field controls capturing the Auxiliary Snapshot Trigger 1. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[1] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than two. + 26 + 1 + read-write + + + ATSEN0 + Auxiliary Snapshot 0 Enable +This field controls capturing the Auxiliary Snapshot Trigger 0. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled. When this bit is reset, the events on this input are ignored. + 25 + 1 + read-write + + + ATSFC + Auxiliary Snapshot FIFO Clear +When set, it resets the pointers of the Auxiliary Snapshot FIFO. This bit is cleared when the pointers are reset and the FIFO is empty. When this bit is high, auxiliary snapshots get stored in the FIFO. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration. + 24 + 1 + read-write + + + TSENMACADDR + Enable MAC address for PTP Frame Filtering +When set, the DA MAC address (that matches any MAC Address register) is used to filter the PTP frames when PTP is directly sent over Ethernet. + 18 + 1 + read-write + + + SNAPTYPSEL + Select PTP packets for Taking Snapshots + These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken. + 16 + 2 + read-write + + + TSMSTRENA + Enable Snapshot for Messages Relevant to Master +When set, the snapshot is taken only for the messages relevant to the master node. Otherwise, the snapshot is taken for the messages relevant to the slave node. + 15 + 1 + read-write + + + TSEVNTENA + Enable Timestamp Snapshot for Event Messages +When set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). When reset, the snapshot is taken for all messages except Announce, Management, and Signaling. + 14 + 1 + read-write + + + TSIPV4ENA + Enable Processing of PTP Frames Sent over IPv4-UDP + When set, the MAC receiver processes the PTP packets encapsulated in UDP over IPv4 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv4 packets. This bit is set by default. + 13 + 1 + read-write + + + TSIPV6ENA + Enable Processing of PTP Frames Sent over IPv6-UDP +When set, the MAC receiver processes PTP packets encapsulated in UDP over IPv6 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv6 packets. + 12 + 1 + read-write + + + TSIPENA + Enable Processing of PTP over Ethernet Frames +When set, the MAC receiver processes the PTP packets encapsulated directly in the Ethernet frames. When this bit is clear, the MAC ignores the PTP over Ethernet packets + 11 + 1 + read-write + + + TSVER2ENA + Enable PTP packet Processing for Version 2 Format +When set, the PTP packets are processed using the 1588 version 2 format. Otherwise, the PTP packets are processed using the version 1 format. + 10 + 1 + read-write + + + TSCTRLSSR + Timestamp Digital or Binary Rollover Control +When set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. When reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and the value of this bit. + 9 + 1 + read-write + + + TSENALL + Enable Timestamp for All Frames +When set, the timestamp snapshot is enabled for all frames received by the MAC. + 8 + 1 + read-write + + + TSADDREG + Addend Reg Update +When set, the content of the Timestamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. This register bit should be zero before setting it. + 5 + 1 + read-write + + + TSTRIG + Timestamp Interrupt Trigger Enable +When set, the timestamp interrupt is generated when the System Time becomes greater than the value written in the Target Time register. This bit is reset after the generation of the Timestamp Trigger Interrupt. + 4 + 1 + read-write + + + TSUPDT + Timestamp Update +When set, the system time is updated (added or subtracted) with the value specified in Register 452 (System Time – Seconds Update Register) and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. This bit is reset when the update is completed in hardware. The “Timestamp Higher Word” register (if enabled during core configuration) is not updated. + 3 + 1 + read-write + + + TSINIT + Timestamp Initialize +When set, the system time is initialized (overwritten) with the value specified in the Register 452 (System Time – Seconds Update Register) and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. This bit is reset when the initialization is complete. The “Timestamp Higher Word” register (if enabled during core configuration) can only be initialized. + 2 + 1 + read-write + + + TSCFUPDT + Timestamp Fine or Coarse Update +When set, this bit indicates that the system times update should be done using the fine update method. When reset, it indicates the system timestamp update should be done using the Coarse method. + 1 + 1 + read-write + + + TSENA + Timestamp Enable +When set, the timestamp is added for the transmit and receive frames. When disabled, timestamp is not added for the transmit and receive frames and the Timestamp Generator is also suspended. You need to initialize the Timestamp (system time) after enabling this mode. On the receive side, the MAC processes the 1588 frames only if this bit is set. + 0 + 1 + read-write + + + + + SUB_SEC_INCR + Sub-Second Increment Register + 0x704 + 32 + 0x00000000 + 0x000000FF + + + SSINC + Sub-second Increment Value +The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register. For example, when PTP clock is 50 MHz (period is 20 ns), you should program 20 (0x14) when the System Time- Nanoseconds register has an accuracy of 1 ns [Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register)]. When TSCTRLSSR is clear, the Nanoseconds register has a resolution of ~0.465ns. In this case, you should program a value of 43 (0x2B) that is derived by 20ns/0.465. + 0 + 8 + read-write + + + + + SYST_SEC + System Time - Seconds Register + 0x708 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSS + Timestamp Second + The value in this field indicates the current value in seconds of the System Time maintained by the MAC. + 0 + 32 + read-only + + + + + SYST_NSEC + System Time - Nanoseconds Register + 0x70c + 32 + 0x00000000 + 0x7FFFFFFF + + + TSSS + Timestamp Sub Seconds + The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the maximum value is 0x3B9A_C9FF, after which it rolls-over to zero. + 0 + 31 + read-only + + + + + SYST_SEC_UPD + System Time - Seconds Update Register + 0x710 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSS + Timestamp Second + The value in this field indicates the time in seconds to be initialized or added to the system time. + 0 + 32 + read-write + + + + + SYST_NSEC_UPD + System Time - Nanoseconds Update Register + 0x714 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDSUB + Add or Subtract Time + When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register. + 31 + 1 + read-write + + + TSSS + Timestamp Sub Seconds +The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF. + 0 + 31 + read-write + + + + + TS_ADDEND + Timestamp Addend Register + 0x718 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSAR + Timestamp Addend Register +This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization. + 0 + 32 + read-write + + + + + TGTTM_SEC + Target Time Seconds Register + 0x71c + 32 + 0x00000000 + 0xFFFFFFFF + + + TSTR + Target Time Seconds Register + This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [6:5] of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). + 0 + 32 + read-write + + + + + TGTTM_NSEC + Target Time Nanoseconds Register + 0x720 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRGTBUSY + Target Time Register Busy + The MAC sets this bit when the PPSCMD field (Bit [3:0]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD field to 010 or 011, instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. This bit is reserved when the Enable Flexible Pulse-Per-Second Output feature is not selected. + 31 + 1 + read-write + + + TTSLO + Target Timestamp Low Register +This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL0 field (Bits [6:5]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. + 0 + 31 + read-write + + + + + SYSTM_H_SEC + System Time - Higher Word Seconds Register + 0x724 + 32 + 0x00000000 + 0x0000FFFF + + + TSHWR + Timestamp Higher Word Register +This field contains the most significant 16-bits of the timestamp seconds value. This register is optional and can be selected using the Enable IEEE 1588 Higher Word Register option during core configuration. The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register. + 0 + 16 + read-write + + + + + TS_STATUS + Timestamp Status Register + 0x728 + 32 + 0x00000000 + 0x3F0F03FF + + + ATSNS + Number of Auxiliary Timestamp Snapshots +This field indicates the number of Snapshots available in the FIFO. A value equal to the selected depth of FIFO (4, 8, or 16) indicates that the Auxiliary Snapshot FIFO is full. These bits are cleared (to 00000) when the Auxiliary snapshot FIFO clear bit is set. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. + 25 + 5 + read-only + + + ATSSTM + Auxiliary Timestamp Snapshot Trigger Missed + This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set. This indicates that the latest snapshot is not stored in the FIFO. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. + 24 + 1 + read-only + + + ATSSTN + Auxiliary Timestamp Snapshot Trigger Identifier +These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. When more than one bit is set at the same time, it means that corresponding auxiliary triggers were sampled at the same clock. These bits are applicable only if the number of Auxiliary snapshots is more than one. One bit is assigned for each trigger as shown in the following list: - Bit 16: Auxiliary trigger 0 - Bit 17: Auxiliary trigger 1 - Bit 18: Auxiliary trigger 2 - Bit 19: Auxiliary trigger 3 The software can read this register to find the triggers that are set when the timestamp is taken. + 16 + 4 + read-only + + + TSTRGTERR3 + Timestamp Target Time Error +This bit is set when the target time, being programmed in Register 496 and Register 497, is already elapsed. This bit is cleared when read by the application. + 9 + 1 + read-only + + + TSTARGT3 + Timestamp Target Time Reached for Target Time PPS3 +When set, this bit indicates that the value of system time is greater than or equal to the value specified in Register 496 (PPS3 Target Time High Register) and Register 497 (PPS3 Target Time Low Register). + 8 + 1 + read-only + + + TSTRGTERR2 + No description available + 7 + 1 + read-only + + + TSTARGT2 + No description available + 6 + 1 + read-only + + + TSTRGTERR1 + No description available + 5 + 1 + read-only + + + TSTARGT1 + No description available + 4 + 1 + read-only + + + TSTRGTERR + No description available + 3 + 1 + read-only + + + AUXTSTRIG + No description available + 2 + 1 + read-only + + + TSTARGT + No description available + 1 + 1 + read-only + + + TSSOVF + No description available + 0 + 1 + read-only + + + + + PPS_CTRL + PPS Control Register + 0x72c + 32 + 0x00000000 + 0x6767777F + + + TRGTMODSEL3 + Target Time Register Mode for PPS3 Output +This field indicates the Target Time registers (register 496 and 497) mode for PPS3 output signal. This field is similar to the TRGTMODSEL0 field. + 29 + 2 + read-write + + + PPSCMD3 + Flexible PPS3 Output Control +This field controls the flexible PPS3 output (ptp_pps_o[3]) signal. This field is similar to PPSCMD0[2:0] in functionality. + 24 + 3 + read-write + + + TRGTMODSEL2 + Target Time Register Mode for PPS2 Output +This field indicates the Target Time registers (register 488 and 489) mode for PPS2 output signal. This field is similar to the TRGTMODSEL0 field. + 21 + 2 + read-write + + + PPSCMD2 + Flexible PPS2 Output Control +This field controls the flexible PPS2 output (ptp_pps_o[2]) signal. This field is similar to PPSCMD0[2:0] in functionality. + 16 + 3 + read-write + + + TRGTMODSEL1 + Target Time Register Mode for PPS1 Output +This field indicates the Target Time registers (register 480 and 481) mode for PPS1 output signal. This field is similar to the TRGTMODSEL0 field. + 13 + 2 + read-write + + + PPSEN1 + Flexible PPS1 Output Mode Enable +When set high, Bits[10:8] function as PPSCMD. + 12 + 1 + read-write + + + PPSCMD1 + Flexible PPS1 Output Control +This field controls the flexible PPS1 output (ptp_pps_o[1]) signal. This field is similar to PPSCMD0[2:0] in functionality. + 8 + 3 + read-write + + + TRGTMODSEL0 + Target Time Register Mode for PPS0 Output + This field indicates the Target Time registers (register 455 and 456) mode for PPS0 output signal: +- 00: Indicates that the Target Time registers are programmed only for generating the interrupt event. +- 01: Reserved +- 10: Indicates that the Target Time registers are programmed for generating the interrupt event and starting or stopping the generation of the PPS0 output signal. +- 11: Indicates that the Target Time registers are programmed only for starting or stopping the generation of the PPS0 output signal. No interrupt is asserted. + 5 + 2 + read-write + + + PPSEN0 + Flexible PPS Output Mode Enable +When set low, Bits [3:0] function as PPSCTRL (backward compatible). When set high, Bits[3:0] function as PPSCMD. + 4 + 1 + read-write + + + PPSCTRLCMD0 + PPSCTRL0: PPS0 Output Frequency Control +This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. The default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width clk_ptp_i) every second. For other values of PPSCTRL, the PPS output becomes a generated clock of following frequencies: +- 0001: The binary rollover is 2 Hz, and the digital rollover is 1 Hz. +- 0010: The binary rollover is 4 Hz, and the digital rollover is 2 Hz. +- 0011: The binary rollover is 8 Hz, and the digital rollover is 4 Hz. +- 0100: The binary rollover is 16 Hz, and the digital rollover is 8 Hz. - ... +- 1111: The binary rollover is 32.768 KHz, and the digital rollover is 16.384 KHz. Note: In the binary rollover mode, the PPS output (ptp_pps_o) has a duty cycle of 50 percent with these frequencies. In the digital rollover mode, the PPS output frequency is an average number. The actual clock is of different frequency that gets synchronized every second. For example: - When PPSCTRL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high period of 463 ms - When PPSCTRL = 0010, the PPS (2 Hz) is a sequence of: - One clock of 50 percent duty cycle and 537 ms period - Second clock of 463 ms period (268 ms low and 195 ms high) - When PPSCTRL = 0011, the PPS (4 Hz) is a sequence of: - Three clocks of 50 percent duty cycle and 268 ms period - Fourth clock of 195 ms period (134 ms low and 61 ms high) +PPSCMD0: Flexible PPS0 Output Control +0000: No Command +0001: START Single Pulse +This command generates single pulse rising at the start point defined in +Target Time Registers and of a duration defined +in the PPS0 Width Register. +0010: START Pulse Train +This command generates the train of pulses rising at the start point +defined in the Target Time Registers and of a duration defined in the +PPS0 Width Register and repeated at interval defined in the PPS +Interval Register. By default, the PPS pulse train is free-running unless +stopped by ‘STOP Pulse train at time’ or ‘STOP Pulse Train +immediately’ commands. +0011: Cancel START +This command cancels the START Single Pulse and START Pulse Train +commands if the system time has not crossed the programmed start +time. +0100: STOP Pulse train at time +This command stops the train of pulses initiated by the START Pulse +Train command (PPSCMD = 0010) after the time programmed in the +Target Time registers elapses. +0101: STOP Pulse Train immediately +This command immediately stops the train of pulses initiated by the +START Pulse Train command (PPSCMD = 0010). +0110: Cancel STOP Pulse train +This command cancels the STOP pulse train at time command if the +programmed stop time has not elapsed. The PPS pulse train becomes +free-running on the successful execution of this command. +0111-1111: Reserved +Note: These bits get cleared automatically + 0 + 4 + read-write + + + + + AUX_TS_NSEC + Auxiliary Timestamp - Nanoseconds Register + 0x730 + 32 + 0x00000000 + 0x7FFFFFFF + + + AUXTSLO + Contains the lower 31 bits (nano-seconds field) of the auxiliary timestamp. + 0 + 31 + read-only + + + + + AUX_TS_SEC + Auxiliary Timestamp - Seconds Register + 0x734 + 32 + 0x00000000 + 0xFFFFFFFF + + + AUXTSHI + Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. + 0 + 32 + read-only + + + + + PPS0_INTERVAL + PPS0 Interval Register + 0x760 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPSINT + PPS0 Output Signal Interval +These bits store the interval between the rising edges of PPS0 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS0 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. + 0 + 32 + read-write + + + + + PPS0_WIDTH + PPS0 Width Register + 0x764 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPSWIDTH + PPS0 Output Signal Width +These bits store the width between the rising edge and corresponding falling edge of the PPS0 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS0 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. + 0 + 32 + read-write + + + + + 3 + 0x20 + 1,2,3 + PPS[%s] + no description available + 0x780 + + TGTTM_SEC + PPS Target Time Seconds Register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSTRH1 + PPS1 Target Time Seconds Register +This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [14:13], TRGTMODSEL1, of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). + 0 + 32 + read-write + + + + + TGTTM_NSEC + PPS Target Time Nanoseconds Register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRGTBUSY1 + PPS1 Target Time Register Busy +The MAC sets this bit when the PPSCMD1 field (Bits [10:8]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. + 31 + 1 + read-write + + + TTSL1 + Target Time Low for PPS1 Register +This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL1 field (Bits [14:13]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. + 0 + 31 + read-write + + + + + INTERVAL + PPS Interval Register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPSINT + PPS1 Output Signal Interval +These bits store the interval between the rising edges of PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS1 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. + 0 + 32 + read-write + + + + + WIDTH + PPS Width Register + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + PPSWIDTH + PPS1 Output Signal Width +These bits store the width between the rising edge and corresponding falling edge of the PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS1 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. + 0 + 32 + read-write + + + + + + DMA_BUS_MODE + Bus Mode Register + 0x1000 + 32 + 0x00000000 + 0xBFFFFFFF + + + RIB + Rebuild INCRx Burst +When this bit is set high and the AHB master gets an EBT (Retry, Split, or Losing bus grant), the AHB master interface rebuilds the pending beats of any burst transfer initiated with INCRx. The AHB master interface rebuilds the beats with a combination of specified bursts with INCRx and SINGLE. By default, the AHB master interface rebuilds pending beats of an EBT with an unspecified (INCR) burst. + 31 + 1 + read-write + + + PRWG + Channel Priority +Weights This field sets the priority weights for Channel 0 during the round-robin arbitration between the DMA channels for the system bus. +- 00: The priority weight is 1. +- 01: The priority weight is 2. +- 10: The priority weight is 3. +- 11: The priority weight is 4. This field is present in all DWC_gmac configurations except GMAC-AXI when you select the AV feature. Otherwise, this field is reserved and read-only (RO). + 28 + 2 + read-write + + + TXPR + Transmit Priority +When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus. In the GMAC-AXI configuration, this bit is reserved and read-only (RO). + 27 + 1 + read-write + + + MB + Mixed Burst +When this bit is set high and the FB bit is low, the AHB master interface starts all bursts of length more than 16 with INCR (undefined burst), whereas it reverts to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less. + 26 + 1 + read-write + + + AAL + Address-Aligned Beats +When this bit is set high and the FB bit is equal to 1, the AHB or AXI interface generates all bursts aligned to the start address LS bits. If the FB bit is equal to 0, the first burst (accessing the start address of data buffer) is not aligned, but subsequent bursts are aligned to the address. + 25 + 1 + read-write + + + PBLX8 + PBLx8 Mode +When set high, this bit multiplies the programmed PBL value (Bits [22:17] and Bits[13:8]) eight times. Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. + 24 + 1 + read-write + + + USP + Use Separate PBL +When set high, this bit configures the Rx DMA to use the value configured in Bits [22:17] as PBL. The PBL value in Bits [13:8] is applicable only to the Tx DMA operations. When reset to low, the PBL value in Bits [13:8] is applicable for both DMA engines. + 23 + 1 + read-write + + + RPBL + Rx DMA PBL +This field indicates the maximum number of beats to be transferred in one Rx DMA transaction. This is the maximum value that is used in a single block Read or Write. The Rx DMA always attempts to burst as specified in the RPBL bit each time it starts a Burst transfer on the host bus. You can program RPBL with values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. This field is valid and applicable only when USP is set high. + 17 + 6 + read-write + + + FB + Fixed Burst + This bit controls whether the AHB or AXI master interface performs fixed burst transfers or not. When set, the AHB interface uses only SINGLE, INCR4, INCR8, or INCR16 during start of the normal burst transfers. When reset, the AHB or AXI interface uses SINGLE and INCR burst transfer operations. + 16 + 1 + read-write + + + PR + Priority Ratio + These bits control the priority ratio in the weighted round-robin arbitration between the Rx DMA and Tx DMA. These bits are valid only when Bit 1 (DA) is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 (TXPR) is reset or set. +- 00: The Priority Ratio is 1:1. +- 01: The Priority Ratio is 2:1. +- 10: The Priority Ratio is 3:1. +- 11: The Priority Ratio is 4:1. + 14 + 2 + read-write + + + PBL + Programmable Burst Length +These bits indicate the maximum number of beats to be transferred in one DMA transaction. This is the maximum value that is used in a single block Read or Write. The DMA always attempts to burst as specified in PBL each time it starts a Burst transfer on the host bus. PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. When USP is set high, this PBL value is applicable only for Tx DMA transactions. If the number of beats to be transferred is more than 32, then perform the following steps: 1. Set the PBLx8 mode. 2. Set the PBL. + 8 + 6 + read-write + + + ATDS + Alternate Descriptor Size +When set, the size of the alternate descriptor (described in “Alternate or Enhanced Descriptors” on page 545) increases to 32 bytes (8 DWORDS). This is required when the Advanced Timestamp feature or the IPC Full Checksum Offload Engine (Type 2) is enabled in the receiver. The enhanced descriptor is not required if the Advanced Timestamp and IPC Full Checksum Offload Engine (Type 2) features are not enabled. In such case, you can use the 16 bytes descriptor to save 4 bytes of memory. This bit is present only when you select the Alternate Descriptor feature and any one of the following features during core configuration: - Advanced Timestamp feature - IPC Full Checksum Offload Engine (Type 2) feature Otherwise, this bit is reserved and is read-only. When reset, the descriptor size reverts back to 4 DWORDs (16 bytes). + 7 + 1 + read-write + + + DSL + Descriptor Skip Length +This bit specifies the number of Word, Dword, or Lword (depending on the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors. The address skipping starts from the end of current descriptor to the start of next descriptor. When the DSL value is equal to zero, the descriptor table is taken as contiguous by the DMA in Ring mode. + 2 + 5 + read-write + + + DA + DMA Arbitration Scheme +This bit specifies the arbitration scheme between the transmit and receive paths of Channel 0. +- 0: Weighted round-robin with Rx:Tx or Tx:Rx The priority between the paths is according to the priority specified in Bits [15:14] (PR) and priority weights specified in Bit 27 (TXPR). +- 1: Fixed priority The transmit path has priority over receive path when Bit 27 (TXPR) is set. Otherwise, receive path has priority over the transmit path. + 1 + 1 + read-write + + + SWR + Software Reset + When this bit is set, the MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after the reset operation is complete in all of the DWC_gmac clock domains. Before reprogramming any register of the DWC_gmac, you should read a zero (0) value in this bit. Note: - The Software reset function is driven only by this bit. Bit 0 of Register 64 (Channel 1 Bus Mode Register) or Register 128 (Channel 2 Bus Mode Register) has no impact on the Software reset function. - The reset operation is completed only when all resets in all active clock domains are de-asserted. Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for the software reset completion. The time to complete the software reset operation depends on the frequency of the slowest active clock. + 0 + 1 + read-write + + + + + DMA_TX_POLL_DEMAND + Transmit Poll Demand Register + 0x1004 + 32 + 0x00000000 + 0xFFFFFFFF + + + TPD + Transmit Poll Demand +When these bits are written with any value, the DMA reads the current descriptor to which the Register 18 (Current Host Transmit Descriptor Register) is pointing. If that descriptor is not available (owned by the Host), the transmission returns to the Suspend state and Bit 2 (TU) of Register 5 (Status Register) is asserted. If the descriptor is available, the transmission resumes. + 0 + 32 + read-write + + + + + DMA_RX_POLL_DEMAND + Receive Poll Demand Register + 0x1008 + 32 + 0x00000000 + 0xFFFFFFFF + + + RPD + Receive Poll Demand +When these bits are written with any value, the DMA reads the current descriptor to which the Register 19 (Current Host Receive Descriptor Register) is pointing. If that descriptor is not available (owned by the Host), the reception returns to the Suspended state and Bit 7 (RU) of Register 5 (Status Register) is asserted. If the descriptor is available, the Rx DMA returns to the active state. + 0 + 32 + read-write + + + + + DMA_RX_DESC_LIST_ADDR + Receive Descriptor List Address Register + 0x100c + 32 + 0x00000000 + 0xFFFFFFFF + + + RDESLA + Start of Receive List +This field contains the base address of the first descriptor in the Receive Descriptor list. The LSB bits (1:0, 2:0, or 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). + 0 + 32 + read-write + + + + + DMA_TX_DESC_LIST_ADDR + Transmit Descriptor List Address Register + 0x1010 + 32 + 0x00000000 + 0xFFFFFFFF + + + TDESLA + Start of Transmit List +This field contains the base address of the first descriptor in the Transmit Descriptor list. The LSB bits (1:0, 2:0, 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and are internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). + 0 + 32 + read-write + + + + + DMA_STATUS + Status Register + 0x1014 + 32 + 0x00000000 + 0x7FFFE7FF + + + GLPII + GLPII: GMAC LPI Interrupt (for Channel 0) +This bit indicates an interrupt event in the LPI logic of the MAC. To reset this bit to 1'b0, the software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source. Note: GLPII status is given only in Channel 0 DMA register and is applicable only when the Energy Efficient Ethernet feature is enabled. Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. -or- GTMSI: GMAC TMS Interrupt (for Channel 1 and Channel 2) This bit indicates an interrupt event in the traffic manager and scheduler logic of DWC_gmac. To reset this bit, the software must read the corresponding registers (Channel Status Register) to get the exact cause of the interrupt and clear its source. Note: GTMSI status is given only in Channel 1 and Channel 2 DMA register when the AV feature is enabled and corresponding additional transmit channels are present. Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. + 30 + 1 + read-write + + + TTI + Timestamp Trigger Interrupt +This bit indicates an interrupt event in the Timestamp Generator block of the DWC_gmac. The software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source to reset this bit to 1'b0. When this bit is high, the interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high. This bit is applicable only when the IEEE 1588 Timestamp feature is enabled. Otherwise, this bit is reserved. + 29 + 1 + read-write + + + GPI + GMAC PMT Interrupt +This bit indicates an interrupt event in the PMT module of the DWC_gmac. The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1’b0. The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. This bit is applicable only when the Power Management feature is enabled. Otherwise, this bit is reserved. Note: The GPI and pmt_intr_o interrupts are generated in different clock domains. + 28 + 1 + read-write + + + GMI + GMAC MMC Interrupt + This bit reflects an interrupt event in the MMC module of the DWC_gmac. The software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear the source of interrupt to make this bit as 1’b0. The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. This bit is applicable only when the MAC Management Counters (MMC) are enabled. Otherwise, this bit is reserved. + 27 + 1 + read-write + + + GLI + GMAC Line Interface Interrupt +When set, this bit reflects any of the following interrupt events in the DWC_gmac interfaces (if present and enabled in your configuration): - PCS (TBI, RTBI, or SGMII): Link change or auto-negotiation complete event - SMII or RGMII: Link change event - General Purpose Input Status (GPIS): Any LL or LH event on the gpi_i input ports To identify the exact cause of the interrupt, the software must first read Bit 11 and Bits[2:0] of Register 14 (Interrupt Status Register) and then to clear the source of interrupt (which also clears the GLI interrupt), read any of the following corresponding registers: - PCS (TBI, RTBI, or SGMII): Register 49 (AN Status Register) - SMII or RGMII: Register 54 (SGMII/RGMII/SMII Control and Status Register) - General Purpose Input (GPI): Register 56 (General Purpose IO Register) The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. + 26 + 1 + read-write + + + EB + Error Bits +This field indicates the type of error that caused a Bus Error, for example, error response on the AHB or AXI interface. This field is valid only when Bit 13 (FBI) is set. This field does not generate an interrupt. +- 0 0 0: Error during Rx DMA Write Data Transfer +- 0 1 1: Error during Tx DMA Read Data Transfer +- 1 0 0: Error during Rx DMA Descriptor Write Access +- 1 0 1: Error during Tx DMA Descriptor Write Access +- 1 1 0: Error during Rx DMA Descriptor Read Access +- 1 1 1: Error during Tx DMA Descriptor Read Access Note: 001 and 010 are reserved. + 23 + 3 + read-write + + + TS + Transmit Process State +This field indicates the Transmit DMA FSM state. This field does not generate an interrupt. +- 3’b000: Stopped; Reset or Stop Transmit Command issued +- 3’b001: Running; Fetching Transmit Transfer Descriptor +- 3’b010: Running; Waiting for status +- 3’b011: Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO) +- 3’b100: TIME_STAMP write state +- 3’b101: Reserved for future use +- 3’b110: Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow +- 3’b111: Running; Closing Transmit Descriptor + 20 + 3 + read-write + + + RS + Receive Process State +This field indicates the Receive DMA FSM state. This field does not generate an interrupt. +- 3’b000: Stopped: Reset or Stop Receive Command issued +- 3’b001: Running: Fetching Receive Transfer Descriptor +- 3’b010: Reserved for future use +- 3’b011: Running: Waiting for receive packet +- 3’b100: Suspended: Receive Descriptor Unavailable +- 3’b101: Running: Closing Receive Descriptor +- 3’b110: TIME_STAMP write state +- 3’b111: Running: Transferring the receive packet data from receive buffer to host memory + 17 + 3 + read-write + + + NIS + Normal Interrupt Summary +Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register): - Register 5[0]: Transmit Interrupt - Register 5[2]: Transmit Buffer Unavailable - Register 5[6]: Receive Interrupt - Register 5[14]: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt enable is set in Register 7) affect the Normal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes NIS to be set, is cleared. + 16 + 1 + read-write + + + AIS + Abnormal Interrupt Summary +Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register): - Register 5[1]: Transmit Process Stopped - Register 5[3]: Transmit Jabber Timeout - Register 5[4]: Receive FIFO Overflow - Register 5[5]: Transmit Underflow - Register 5[7]: Receive Buffer Unavailable - Register 5[8]: Receive Process Stopped - Register 5[9]: Receive Watchdog Timeout - Register 5[10]: Early Transmit Interrupt - Register 5[13]: Fatal Bus Error Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes AIS to be set, is cleared. + 15 + 1 + read-write + + + ERI + Early Receive Interrupt +This bit indicates that the DMA filled the first data buffer of the packet. This bit is cleared when the software writes 1 to this bit or Bit 6 (RI) of this register is set (whichever occurs earlier). + 14 + 1 + read-write + + + FBI + Fatal Bus Error Interrupt +This bit indicates that a bus error occurred, as described in Bits [25:23]. When this bit is set, the corresponding DMA engine disables all of its bus accesses. + 13 + 1 + read-write + + + ETI + Early Transmit Interrupt +This bit indicates that the frame to be transmitted is fully transferred to the MTL Transmit FIFO. + 10 + 1 + read-write + + + RWT + Receive Watchdog Timeout +When set, this bit indicates that the Receive Watchdog Timer expired while receiving the current frame and the current frame is truncated after the watchdog timeout. + 9 + 1 + read-write + + + RPS + Receive Process Stopped +This bit is asserted when the Receive Process enters the Stopped state. + 8 + 1 + read-write + + + RU + Receive Buffer Unavailable +This bit indicates that the host owns the Next Descriptor in the Receive List and the DMA cannot acquire it. The Receive Process is suspended. To resume processing Receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, the Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor is owned by the DMA. + 7 + 1 + read-write + + + RI + Receive Interrupt +This bit indicates that the frame reception is complete. When reception is complete, the Bit 31 of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor, and the specific frame status information is updated in the descriptor. The reception remains in the Running state. + 6 + 1 + read-write + + + UNF + Transmit Underflow +This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set. + 5 + 1 + read-write + + + OVF + Receive Overflow +This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to the application, the overflow status is set in RDES0[11]. + 4 + 1 + read-write + + + TJT + Transmit Jabber Timeout +This bit indicates that the Transmit Jabber Timer expired, which happens when the frame size exceeds 2,048 (10,240 bytes when the Jumbo frame is enabled). When the Jabber Timeout occurs, the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert. + 3 + 1 + read-write + + + TU + Transmit Buffer Unavailable +This bit indicates that the host owns the Next Descriptor in the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing Transmit descriptors, the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command. + 2 + 1 + read-write + + + TPS + Transmit Process Stopped +This bit is set when the transmission is stopped. + 1 + 1 + read-write + + + TI + Transmit Interrupt +This bit indicates that the frame transmission is complete. When transmission is complete, Bit 31 (OWN) of TDES0 is reset, and the specific frame status information is updated in the descriptor. + 0 + 1 + read-write + + + + + DMA_OP_MODE + Operation Mode Register + 0x1018 + 32 + 0x00000000 + 0x13F1FFFE + + + DT + Disable Dropping of TCP/IP Checksum Error Frames +When this bit is set, the MAC does not drop the frames which only have errors detected by the Receive Checksum Offload engine. Such frames do not have any errors (including FCS error) in the Ethernet frame received by the MAC but have errors only in the encapsulated payload. When this bit is reset, all error frames are dropped if the FEF bit is reset. If the IPC Full Checksum Offload Engine (Type 2) is disabled, this bit is reserved (RO with value 1'b0). + 28 + 1 + read-write + + + RSF + Receive Store and Forward +When this bit is set, the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it, ignoring the RTC bits. When this bit is reset, the Rx FIFO operates in the cut-through mode, subject to the threshold specified by the RTC bits. + 25 + 1 + read-write + + + DFF + Disable Flushing of Received Frames +When this bit is set, the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers as it does normally when this bit is reset. (See “Receive Process Suspended” on page 83.) + 24 + 1 + read-write + + + RFA_2 + MSB of Threshold for Activating Flow Control +If the DWC_gmac is configured for an Rx FIFO size of 8 KB or more, this bit (when set) provides additional threshold levels for activating the flow control in both half-duplex and full-duplex modes. This bit (as Most Significant Bit), along with the RFA (Bits [10:9]), gives the following thresholds for activating flow control: +- 100: Full minus 5 KB, that is, FULL — 5 KB +- 101: Full minus 6 KB, that is, FULL — 6 KB +- 110: Full minus 7 KB, that is, FULL — 7 KB +- 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. + 23 + 1 + read-write + + + RFD_2 + MSB of Threshold for Deactivating Flow Control +If the DWC_gmac is configured for Rx FIFO size of 8 KB or more, this bit (when set) provides additional threshold levels for deactivating the flow control in both half-duplex and full-duplex modes. This bit (as Most Significant Bit) along with the RFD (Bits [12:11]) gives the following thresholds for deactivating flow control: +- 100: Full minus 5 KB, that is, FULL — 5 KB +- 101: Full minus 6 KB, that is, FULL — 6 KB +- 110: Full minus 7 KB, that is, FULL — 7 KB +- 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. + 22 + 1 + read-write + + + TSF + Transmit Store and Forward +When this bit is set, transmission starts when a full frame resides in the MTL Transmit FIFO. When this bit is set, the TTC values specified in Bits [16:14] are ignored. This bit should be changed only when the transmission is stopped. + 21 + 1 + read-write + + + FTF + Flush Transmit FIFO +When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flushed. This bit is cleared internally when the flushing operation is complete. The Operation Mode register should not be written to until this bit is cleared. The data which is already accepted by the MAC transmitter is not flushed. It is scheduled for transmission and results in underflow and runt frame transmission. + 20 + 1 + read-write + + + TTC + Transmit Threshold Control +These bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are also transmitted. These bits are used only when Bit 21 (TSF) is reset. +- 000: 64 +- 001: 128 +- 010: 192 +- 011: 256 +- 100: 40 +- 101: 32 +- 110: 24 +- 111: 16 + 14 + 3 + read-write + + + ST + Start or Stop Transmission Command +When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. Descriptor acquisition is attempted either from the current position in the list, which is the Transmit List Base Address set by Register 4 (Transmit Descriptor List Address Register), or from the position retained when transmission was stopped previously. If the DMA does not own the current descriptor, transmission enters the Suspended state and Bit 2 (Transmit Buffer Unavailable) of Register 5 (Status Register) is set. The Start Transmission command is effective only when transmission is stopped. If the command is issued before setting Register 4 (Transmit Descriptor List Address Register), then the DMA behavior is unpredictable. When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current frame. The Next Descriptor position in the Transmit List is saved, and it becomes the current position when transmission is restarted. To change the list address, you need to program Register 4 (Transmit Descriptor List Address Register) with a new value when this bit is reset. The new value is considered when this bit is set again. The stop transmission command is effective only when the transmission of the current frame is complete or the transmission is in the Suspended state. + 13 + 1 + read-write + + + RFD + Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (Fill-level of Rx FIFO) at which the flow control is de-asserted after activation. +- 00: Full minus 1 KB, that is, FULL — 1 KB +- 01: Full minus 2 KB, that is, FULL — 2 KB +- 10: Full minus 3 KB, that is, FULL — 3 KB +- 11: Full minus 4 KB, that is, FULL — 4 KB The de-assertion is effective only after flow control is asserted. If the Rx FIFO is 8 KB or more, an additional Bit (RFD_2) is used for more threshold levels as described in Bit 22. These bits are reserved and read-only when the Rx FIFO depth is less than 4 KB. + 11 + 2 + read-write + + + RFA + Threshold for Activating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (Fill level of Rx FIFO) at which the flow control is activated. +- 00: Full minus 1 KB, that is, FULL—1KB. +- 01: Full minus 2 KB, that is, FULL—2KB. +- 10: Full minus 3 KB, that is, FULL—3KB. +- 11: Full minus 4 KB, that is, FULL—4KB. These values are applicable only to Rx FIFOs of 4 KB or more and when Bit 8 (EFC) is set high. If the Rx FIFO is 8 KB or more, an additional Bit (RFA_2) is used for more threshold levels as described in Bit 23. These bits are reserved and read-only when the depth of Rx FIFO is less than 4 KB. Note: When FIFO size is exactly 4 KB, although the DWC_gmac allows you to program the value of these bits to 11, the software should not program these bits to 2'b11. The value 2'b11 means flow control on FIFO empty condition + 9 + 2 + read-write + + + EFC + Enable HW Flow Control +When this bit is set, the flow control signal operation based on the fill-level of Rx FIFO is enabled. When reset, the flow control operation is disabled. This bit is not used (reserved and always reset) when the Rx FIFO is less than 4 KB. + 8 + 1 + read-write + + + FEF + Forward Error Frames +When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or overflow). However, if the start byte (write) pointer of a frame is already transferred to the read controller side (in Threshold mode), then the frame is not dropped. In the GMAC-MTL configuration in which the Frame Length FIFO is also enabled during core configuration, the Rx FIFO drops the error frames if that frame's start byte is not transferred (output) on the ARI bus. When the FEF bit is set, all frames except runt error frames are forwarded to the DMA. If the Bit 25 (RSF) is set and the Rx FIFO overflows when a partial frame is written, then the frame is dropped irrespective of the FEF bit setting. However, if the Bit 25 (RSF) is reset and the Rx FIFO overflows when a partial frame is written, then a partial frame may be forwarded to the DMA. Note: When FEF bit is reset, the giant frames are dropped if the giant frame status is given in Rx Status (in Table 8-6 or Table 8-23) in the following configurations: - The IP checksum engine (Type 1) and full checksum offload engine (Type 2) are not selected. - The advanced timestamp feature is not selected but the extended status is selected. The extended status is available with the following features: - L3-L4 filter in GMAC-CORE or GMAC-MTL configurations - Full checksum offload engine (Type 2) with enhanced descriptor format in the GMAC-DMA, GMAC-AHB, or GMAC-AXI configurations. + 7 + 1 + read-write + + + FUF + Forward Undersized Good Frames +When set, the Rx FIFO forwards Undersized frames (that is, frames with no Error and length less than 64 bytes) including pad-bytes and CRC. When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a frame is already transferred because of the lower value of Receive Threshold, for example, RTC = 01. + 6 + 1 + read-write + + + DGF + Drop Giant Frames +When set, the MAC drops the received giant frames in the Rx FIFO, that is, frames that are larger than the computed giant frame limit. When reset, the MAC does not drop the giant frames in the Rx FIFO. Note: This bit is available in the following configurations in which the giant frame status is not provided in Rx status and giant frames are not dropped by default: - Configurations in which IP Checksum Offload (Type 1) is selected in Rx - Configurations in which the IPC Full Checksum Offload Engine (Type 2) is selected in Rx with normal descriptor format - Configurations in which the Advanced Timestamp feature is selected In all other configurations, this bit is not used (reserved and always reset). + 5 + 1 + read-write + + + RTC + Receive Threshold Control +These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. In addition, full frames with length less than the threshold are automatically transferred. The value of 11 is not applicable if the configured Receive FIFO size is 128 bytes. These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1. +- 00: 64 +- 01: 32 +- 10: 96 +- 11: 128 + 3 + 2 + read-write + + + OSF + Operate on Second Frame +When this bit is set, it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained. + 2 + 1 + read-write + + + SR + Start or Stop Receive +When this bit is set, the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames. The descriptor acquisition is attempted from the current position in the list, which is the address set by the Register 3 (Receive Descriptor List Address Register) or the position retained when the Receive process was previously stopped. If the DMA does not own the descriptor, reception is suspended and Bit 7 (Receive Buffer Unavailable) of Register 5 (Status Register) is set. The Start Receive command is effective only when the reception has stopped. If the command is issued before setting Register 3 (Receive Descriptor List Address Register), the DMA behavior is unpredictable. When this bit is cleared, the Rx DMA operation is stopped after the transfer of the current frame. The next descriptor position in the Receive list is saved and becomes the current position after the Receive process is restarted. The Stop Receive command is effective only when the Receive process is in either the Running (waiting for receive packet) or in the Suspended state. + 1 + 1 + read-write + + + + + DMA_INTR_EN + Interrupt Enable Register + 0x101c + 32 + 0x00000000 + 0x0001E7FF + + + NIE + Normal Interrupt Summary Enable +When this bit is set, normal interrupt summary is enabled. When this bit is reset, normal interrupt summary is disabled. This bit enables the following interrupts in Register 5 (Status Register): - Register 5[0]: Transmit Interrupt - Register 5[2]: Transmit Buffer Unavailable - Register 5[6]: Receive Interrupt - Register 5[14]: Early Receive Interrupt + 16 + 1 + read-write + + + AIE + Abnormal Interrupt Summary Enable +When this bit is set, abnormal interrupt summary is enabled. When this bit is reset, the abnormal interrupt summary is disabled. This bit enables the following interrupts in Register 5 (Status Register): - Register 5[1]: Transmit Process Stopped - Register 5[3]: Transmit Jabber Timeout - Register 5[4]: Receive Overflow - Register 5[5]: Transmit Underflow - Register 5[7]: Receive Buffer Unavailable - Register 5[8]: Receive Process Stopped - Register 5[9]: Receive Watchdog Timeout - Register 5[10]: Early Transmit Interrupt - Register 5[13]: Fatal Bus Error + 15 + 1 + read-write + + + ERE + Early Receive Interrupt Enable +When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Early Receive Interrupt is enabled. When this bit is reset, the Early Receive Interrupt is disabled. + 14 + 1 + read-write + + + FBE + Fatal Bus Error Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Fatal Bus Error Interrupt is enabled. When this bit is reset, the Fatal Bus Error Enable Interrupt is disabled. + 13 + 1 + read-write + + + ETE + Early Transmit Interrupt Enable +When this bit is set with an Abnormal Interrupt Summary Enable (Bit 15), the Early Transmit Interrupt is enabled. When this bit is reset, the Early Transmit Interrupt is disabled. + 10 + 1 + read-write + + + RWE + Receive Watchdog Timeout Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, the Receive Watchdog Timeout Interrupt is disabled. + 9 + 1 + read-write + + + RSE + Receive Stopped Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped Interrupt is disabled. + 8 + 1 + read-write + + + RUE + Receive Buffer Unavailable Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled. + 7 + 1 + read-write + + + RIE + Receive Interrupt Enable +When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Receive Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled. + 6 + 1 + read-write + + + UNE + Underflow Interrupt Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Underflow Interrupt is enabled. When this bit is reset, the Underflow Interrupt is disabled. + 5 + 1 + read-write + + + OVE + Overflow Interrupt Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Overflow Interrupt is enabled. When this bit is reset, the Overflow Interrupt is disabled. + 4 + 1 + read-write + + + TJE + Transmit Jabber Timeout Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, the Transmit Jabber Timeout Interrupt is disabled. + 3 + 1 + read-write + + + TUE + Transmit Buffer Unavailable Enable +When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled. + 2 + 1 + read-write + + + TSE + Transmit Stopped Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmission Stopped Interrupt is enabled. When this bit is reset, the Transmission Stopped Interrupt is disabled. + 1 + 1 + read-write + + + TIE + Transmit Interrupt Enable +When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Interrupt is enabled. When this bit is reset, the Transmit Interrupt is disabled. + 0 + 1 + read-write + + + + + DMA_MISS_OVF_CNT + Missed Frame And Buffer Overflow Counter Register + 0x1020 + 32 + 0x00000000 + 0x1FFFFFFF + + + ONFCNTOVF + Overflow Bit for FIFO Overflow Counter +This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows, that is, the Rx FIFO overflows with the overflow frame counter at maximum value. In such a scenario, the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened. + 28 + 1 + read-write + + + OVFFRMCNT + Overflow Frame Counter +This field indicates the number of frames missed by the application. This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read with mci_be_i[2] at 1’b1. + 17 + 11 + read-write + + + MISCNTOVF + Overflow Bit for Missed Frame Counter +This bit is set every time Missed Frame Counter (Bits[15:0]) overflows, that is, the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value. In such a scenario, the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened. + 16 + 1 + read-write + + + MISFRMCNT + Missed Frame Counter +This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with mci_be_i[0] at 1’b1. + 0 + 16 + read-write + + + + + DMA_RX_INTR_WDOG + Receive Interrupt Watchdog Timer Register + 0x1024 + 32 + 0x00000000 + 0x000000FF + + + RIWT + RI Watchdog Timer Count +This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer of a frame for which the RI status bit is not set because of the setting in the corresponding descriptor RDES1[31]. When the watchdog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame. + 0 + 8 + read-write + + + + + DMA_AXI_MODE + AXI Bus Mode Register + 0x1028 + 32 + 0x00000000 + 0xC0FF30FF + + + EN_LPI + Enable Low Power Interface (LPI) +When set to 1, this bit enables the LPI mode supported by the GMAC-AXI configuration and accepts the LPI request from the AXI System Clock controller. When set to 0, this bit disables the LPI mode and always denies the LPI request from the AXI System Clock controller. + 31 + 1 + read-write + + + LPI_XIT_FRM + Unlock on Magic Packet or Remote Wake-Up Frame +When set to 1, this bit enables the GMAC-AXI to come out of the LPI mode only when the magic packet or remote wake-up frame is received. When set to 0, this bit enables the GMAC-AXI to come out of LPI mode when any frame is received. + 30 + 1 + read-write + + + WR_OSR_LMT + AXI Maximum Write Outstanding Request Limit +This value limits the maximum outstanding request on the AXI write interface. Maximum outstanding requests = WR_OSR_LMT+1 Note: - Bit 22 is reserved if AXI_GM_MAX_WR_REQUESTS = 4. - Bit 23 bit is reserved if AXI_GM_MAX_WR_REQUESTS != 16. + 20 + 4 + read-write + + + RD_OSR_LMT + AXI Maximum Read Outstanding Request Limit +This value limits the maximum outstanding request on the AXI read interface. Maximum outstanding requests = RD_OSR_LMT+1 Note: - Bit 18 is reserved if AXI_GM_MAX_RD_REQUESTS = 4. - Bit 19 is reserved if AXI_GM_MAX_RD_REQUESTS != 16. + 16 + 4 + read-write + + + ONEKBBE + 1 KB Boundary Crossing Enable for the GMAC-AXI Master +When set, the GMAC-AXI master performs burst transfers that do not cross 1 KB boundary. When reset, the GMAC-AXI master performs burst transfers that do not cross 4 KB boundary. + 13 + 1 + read-write + + + AXI_AAL + Address-Aligned Beats +This bit is read-only bit and reflects the Bit 25 (AAL) of Register 0 (Bus Mode Register). When this bit is set to 1, the GMAC-AXI performs address-aligned burst transfers on both read and write channels. + 12 + 1 + read-write + + + BLEN256 + AXI Burst Length 256 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 256 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 256. Otherwise, this bit is reserved and is read-only (RO). + 7 + 1 + read-write + + + BLEN128 + AXI Burst Length 128 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 128 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 128 or more. Otherwise, this bit is reserved and is read-only (RO). + 6 + 1 + read-write + + + BLEN64 + AXI Burst Length 64 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 64 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 64 or more. Otherwise, this bit is reserved and is read-only (RO). + 5 + 1 + read-write + + + BLEN32 + AXI Burst Length 32 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 32 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 32 or more. Otherwise, this bit is reserved and is read-only (RO). + 4 + 1 + read-write + + + BLEN16 + AXI Burst Length 16 +When this bit is set to 1 or UNDEF is set to 1, the GMAC-AXI is allowed to select a burst length of 16 on the AXI master interface. + 3 + 1 + read-write + + + BLEN8 + AXI Burst Length 8 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 8 on the AXI master interface. Setting this bit has no effect when UNDEF is set to 1. + 2 + 1 + read-write + + + BLEN4 + AXI Burst Length 4 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 4 on the AXI master interface. Setting this bit has no effect when UNDEF is set to 1. + 1 + 1 + read-write + + + UNDEF + AXI Undefined Burst Length +This bit is read-only bit and indicates the complement (invert) value of Bit 16 (FB) in Register 0 (Bus Mode Register). - When this bit is set to 1, the GMAC-AXI is allowed to perform any burst length equal to or below the maximum allowed burst length programmed in Bits[7:3]. - When this bit is set to 0, the GMAC-AXI is allowed to perform only fixed burst lengths as indicated by BLEN256, BLEN128, BLEN64, BLEN32, BLEN16, BLEN8, or BLEN4, or a burst length of 1. If UNDEF is set and none of the BLEN bits is set, then GMAC-AXI is allowed to perform a burst length of 16. + 0 + 1 + read-write + + + + + DMA_BUS_STATUS + AHB or AXI Status Register + 0x102c + 32 + 0x00000000 + 0x00000003 + + + AXIRDSTS + AXI Master Read Channel Status +When high, it indicates that AXI master's read channel is active and transferring data. + 1 + 1 + read-write + + + AXWHSTS + AXI Master Write Channel or AHB Master Status +When high, it indicates that AXI master's write channel is active and transferring data in the GMAC-AXI configuration. In the GMAC-AHB configuration, it indicates that the AHB master interface FSMs are in the non-idle state. + 0 + 1 + read-write + + + + + DMA_CURR_HOST_TX_DESC + Current Host Transmit Descriptor Register + 0x1048 + 32 + 0x00000000 + 0xFFFFFFFF + + + CURTDESAPTR + Host Transmit Descriptor Address Pointer +Cleared on Reset. Pointer updated by the DMA during operation. + 0 + 32 + read-write + + + + + DMA_CURR_HOST_RX_DESC + Current Host Receive Descriptor Register + 0x104c + 32 + 0x00000000 + 0xFFFFFFFF + + + CURRDESAPTR + Host Receive Descriptor Address Pointer +Cleared on Reset. Pointer updated by the DMA during operation. + 0 + 32 + read-write + + + + + DMA_CURR_HOST_TX_BUF + Current Host Transmit Buffer Address Register + 0x1050 + 32 + 0x00000000 + 0xFFFFFFFF + + + CURTBUFAPTR + Host Transmit Buffer Address Pointer +Cleared on Reset. Pointer updated by the DMA during operation. + 0 + 32 + read-write + + + + + DMA_CURR_HOST_RX_BUF + Current Host Receive Buffer Address Register + 0x1054 + 32 + 0x00000000 + 0xFFFFFFFF + + + CURRBUFAPTR + Host Receive Buffer Address Pointer +Cleared on Reset. Pointer updated by the DMA during operation. + 0 + 32 + read-write + + + + + CTRL2 + Control Register 1 + 0x3008 + 32 + 0x00000000 + 0x2008F000 + + + ENET0_LPI_IRQ_EN + lowpower interrupt enable, for internal use only, user should use core registers for enable/disable interrupt + 29 + 1 + read-write + + + ENET0_REFCLK_OE + set to enable output 50MHz clock to rmii phy. +User should set it if use soc internal clock as refclk + 19 + 1 + read-write + + + ENET0_PHY_INF_SEL + PHY mode select +000MII; 001RGMII; 100RMII; +should be set before config IOMUX, otherwise may cause glitch for RGMII + 13 + 3 + read-write + + + ENET0_FLOWCTRL + flow control request + 12 + 1 + read-write + + + + + + + NTMR0 + NTMR0 + TMR + 0xf2010000 + + 0x0 + 0x20c + registers + + + + 4 + 0x40 + ch0,ch1,ch2,ch3 + CHANNEL[%s] + no description available + 0x0 + + CR + Control Register + 0x0 + 32 + 0x00000000 + 0x80007FFF + + + CNTUPT + 1- update counter to new value as CNTUPTVAL +This bit will be auto cleared after 1 cycle + 31 + 1 + write-only + + + CNTRST + 1- reset counter + 14 + 1 + read-write + + + SYNCFLW + 1- enable this channel to reset counter to reload(RLD) together with its previous channel. +This bit is not valid for channel 0. + 13 + 1 + read-write + + + SYNCIFEN + 1- SYNCI is valid on its falling edge + 12 + 1 + read-write + + + SYNCIREN + 1- SYNCI is valid on its rising edge + 11 + 1 + read-write + + + CEN + 1- counter enable + 10 + 1 + read-write + + + CMPINIT + Output compare initial poliarity +1- The channel output initial level is high +0- The channel output initial level is low +User should set this bit before set CMPEN to 1. + 9 + 1 + read-write + + + CMPEN + 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. + 8 + 1 + read-write + + + DMASEL + select one of DMA request: +00- CMP0 flag +01- CMP1 flag +10- Input signal toggle captured +11- RLD flag, counter reload; + 6 + 2 + read-write + + + DMAEN + 1- enable dma + 5 + 1 + read-write + + + SWSYNCIEN + 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set + 4 + 1 + read-write + + + DBGPAUSE + 1- counter will pause if chip is in debug mode + 3 + 1 + read-write + + + CAPMODE + This bitfield define the input capture mode +100: width measure mode, timer will calculate the input signal period and duty cycle +011: capture at both rising edge and falling edge +010: capture at falling edge +001: capture at rising edge +000: No capture + 0 + 3 + read-write + + + + + 2 + 0x4 + CMP0,CMP1 + CMP[%s] + no description available + 0x4 + 32 + 0xFFFFFFF0 + 0xFFFFFFFF + + + CMP + compare value 0 + 0 + 32 + read-write + + + + + RLD + Reload register + 0xc + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + RLD + reload value + 0 + 32 + read-write + + + + + CNTUPTVAL + Counter update value register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTUPTVAL + counter will be set to this value when software write cntupt bit in CR + 0 + 32 + read-write + + + + + CAPPOS + Capture rising edge register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPOS + This register contains the counter value captured at input signal rising edge + 0 + 32 + read-only + + + + + CAPNEG + Capture falling edge register + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + This register contains the counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPPRD + PWM period measure register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPRD + This register contains the input signal period when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CAPDTY + PWM duty cycle measure register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + MEAS_HIGH + This register contains the input signal duty cycle when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CNT + Counter + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + 32 bit counter value + 0 + 32 + read-only + + + + + + SR + Status register + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH3CMP1F + channel 3 compare value 1 match flag + 15 + 1 + write-only + + + CH3CMP0F + channel 3 compare value 1 match flag + 14 + 1 + write-only + + + CH3CAPF + channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 13 + 1 + write-only + + + CH3RLDF + channel 3 counter reload flag + 12 + 1 + write-only + + + CH2CMP1F + channel 2 compare value 1 match flag + 11 + 1 + write-only + + + CH2CMP0F + channel 2 compare value 1 match flag + 10 + 1 + write-only + + + CH2CAPF + channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 9 + 1 + write-only + + + CH2RLDF + channel 2 counter reload flag + 8 + 1 + write-only + + + CH1CMP1F + channel 1 compare value 1 match flag + 7 + 1 + write-only + + + CH1CMP0F + channel 1 compare value 1 match flag + 6 + 1 + write-only + + + CH1CAPF + channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 5 + 1 + write-only + + + CH1RLDF + channel 1 counter reload flag + 4 + 1 + write-only + + + CH0CMP1F + channel 1 compare value 1 match flag + 3 + 1 + write-only + + + CH0CMP0F + channel 1 compare value 1 match flag + 2 + 1 + write-only + + + CH0CAPF + channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 1 + 1 + write-only + + + CH0RLDF + channel 1 counter reload flag + 0 + 1 + write-only + + + + + IRQEN + Interrupt request enable register + 0x204 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH3CMP1EN + 1- generate interrupt request when ch3cmp1f flag is set + 15 + 1 + read-write + + + CH3CMP0EN + 1- generate interrupt request when ch3cmp0f flag is set + 14 + 1 + read-write + + + CH3CAPEN + 1- generate interrupt request when ch3capf flag is set + 13 + 1 + read-write + + + CH3RLDEN + 1- generate interrupt request when ch3rldf flag is set + 12 + 1 + read-write + + + CH2CMP1EN + 1- generate interrupt request when ch2cmp1f flag is set + 11 + 1 + read-write + + + CH2CMP0EN + 1- generate interrupt request when ch2cmp0f flag is set + 10 + 1 + read-write + + + CH2CAPEN + 1- generate interrupt request when ch2capf flag is set + 9 + 1 + read-write + + + CH2RLDEN + 1- generate interrupt request when ch2rldf flag is set + 8 + 1 + read-write + + + CH1CMP1EN + 1- generate interrupt request when ch1cmp1f flag is set + 7 + 1 + read-write + + + CH1CMP0EN + 1- generate interrupt request when ch1cmp0f flag is set + 6 + 1 + read-write + + + CH1CAPEN + 1- generate interrupt request when ch1capf flag is set + 5 + 1 + read-write + + + CH1RLDEN + 1- generate interrupt request when ch1rldf flag is set + 4 + 1 + read-write + + + CH0CMP1EN + 1- generate interrupt request when ch0cmp1f flag is set + 3 + 1 + read-write + + + CH0CMP0EN + 1- generate interrupt request when ch0cmp0f flag is set + 2 + 1 + read-write + + + CH0CAPEN + 1- generate interrupt request when ch0capf flag is set + 1 + 1 + read-write + + + CH0RLDEN + 1- generate interrupt request when ch0rldf flag is set + 0 + 1 + read-write + + + + + GCR + Global control register + 0x208 + 32 + 0x00000000 + 0x0000000F + + + SWSYNCT + set this bitfield to trigger software counter sync event + 0 + 4 + read-write + + + + + + + GPTMR0 + GPTMR0 + TMR + 0xf3000000 + + + GPTMR1 + GPTMR1 + TMR + 0xf3004000 + + + GPTMR2 + GPTMR2 + TMR + 0xf3008000 + + + GPTMR3 + GPTMR3 + TMR + 0xf300c000 + + + PTMR + PTMR + TMR + 0xf40e0000 + + + USB0 + USB0 + USB + 0xf2020000 + + 0x80 + 0x1a8 + registers + + + + GPTIMER0LD + General Purpose Timer #0 Load Register + 0x80 + 32 + 0x00000000 + 0x00FFFFFF + + + GPTLD + GPTLD +General Purpose Timer Load Value +These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. +This value represents the time in microseconds minus 1 for the timer duration. +Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. +NOTE: Max value is 0xFFFFFF or 16.777215 seconds. + 0 + 24 + read-write + + + + + GPTIMER0CTRL + General Purpose Timer #0 Controller Register + 0x84 + 32 + 0x00000000 + 0xC1FFFFFF + + + GPTRUN + GPTRUN +General Purpose Timer Run +GPTCNT bits are not effected when setting or clearing this bit. +0 - Stop counting +1 - Run + 31 + 1 + read-write + + + GPTRST + GPTRST +General Purpose Timer Reset +0 - No action +1 - Load counter value from GPTLD bits in n_GPTIMER0LD + 30 + 1 + write-only + + + GPTMODE + GPTMODE +General Purpose Timer Mode +In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is +reset by software; +In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the +counter value from GPTLD bits to start again. +0 - One Shot Mode +1 - Repeat Mode + 24 + 1 + read-write + + + GPTCNT + GPTCNT +General Purpose Timer Counter. +This field is the count value of the countdown timer. + 0 + 24 + read-only + + + + + GPTIMER1LD + General Purpose Timer #1 Load Register + 0x88 + 32 + 0x00000000 + 0x00FFFFFF + + + GPTLD + GPTLD +General Purpose Timer Load Value +These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. +This value represents the time in microseconds minus 1 for the timer duration. +Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. +NOTE: Max value is 0xFFFFFF or 16.777215 seconds. + 0 + 24 + read-write + + + + + GPTIMER1CTRL + General Purpose Timer #1 Controller Register + 0x8c + 32 + 0x00000000 + 0xC1FFFFFF + + + GPTRUN + GPTRUN +General Purpose Timer Run +GPTCNT bits are not effected when setting or clearing this bit. +0 - Stop counting +1 - Run + 31 + 1 + read-write + + + GPTRST + GPTRST +General Purpose Timer Reset +0 - No action +1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD + 30 + 1 + write-only + + + GPTMODE + GPTMODE +General Purpose Timer Mode +In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is +reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and +automatically reload the counter value from GPTLD bits to start again. +0 - One Shot Mode +1 - Repeat Mode + 24 + 1 + read-write + + + GPTCNT + GPTCNT +General Purpose Timer Counter. +This field is the count value of the countdown timer. + 0 + 24 + read-only + + + + + SBUSCFG + System Bus Config Register + 0x90 + 32 + 0x00000000 + 0x00000007 + + + AHBBRST + AHBBRST +AHB master interface Burst configuration +These bits control AHB master transfer type sequence (or priority). +NOTE: This register overrides n_BURSTSIZE register when its value is not zero. +000 - Incremental burst of unspecified length only +001 - INCR4 burst, then single transfer +010 - INCR8 burst, INCR4 burst, then single transfer +011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer +100 - Reserved, don't use +101 - INCR4 burst, then incremental burst of unspecified length +110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length +111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length + 0 + 3 + read-write + + + + + USBCMD + USB Command Register + 0x140 + 32 + 0x00080000 + 0x00FFEB7F + + + ITC + ITC +Interrupt Threshold Control -Read/Write. +The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. +ITC contains the maximum interrupt interval measured in micro-frames. Valid values are +shown below. +Value Maximum Interrupt Interval +00000000 - Immediate (no threshold) +00000001 - 1 micro-frame +00000010 - 2 micro-frames +00000100 - 4 micro-frames +00001000 - 8 micro-frames +00010000 - 16 micro-frames +00100000 - 32 micro-frames +01000000 - 64 micro-frames + 16 + 8 + read-write + + + FS_2 + FS_2 +Frame List Size - (Read/Write or Read Only). [host mode only] +This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. +This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. +NOTE: This field is made up from USBCMD bits 15, 3 and 2. +Value Meaning +0b000 - 1024 elements (4096 bytes) Default value +0b001 - 512 elements (2048 bytes) +0b010 - 256 elements (1024 bytes) +0b011 - 128 elements (512 bytes) +0b100 - 64 elements (256 bytes) +0b101 - 32 elements (128 bytes) +0b110 - 16 elements (64 bytes) +0b111 - 8 elements (32 bytes) + 15 + 1 + read-write + + + ATDTW + ATDTW +Add dTD TripWire - Read/Write. [device mode only] +This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's +linked list. This bit is set and cleared by software. +This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD +to a primed endpoint may go unrecognized. + 14 + 1 + read-write + + + SUTW + SUTW +Setup TripWire - Read/Write. [device mode only] +This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. +If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then +there is a hazard when new setup data arrives while the DCD is copying the setup data payload +from the QH for a previous setup packet. This bit is set and cleared by software. +This bit would also be cleared by hardware when a hazard detected. + 13 + 1 + read-write + + + ASPE + ASPE +Asynchronous Schedule Park Mode Enable - Read/Write. +If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. +Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. +When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. +NOTE: ASPE bit reset value: '0b' for OTG controller . + 11 + 1 + read-write + + + ASP + ASP +Asynchronous Schedule Park Mode Count - Read/Write. +If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. +It contains a count of the number of successive transactions the host controller is allowed to +execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. +Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. +This field is set to 3h in all controller core. + 8 + 2 + read-write + + + IAA + IAA +Interrupt on Async Advance Doorbell - Read/Write. +This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. +When the host controller has evicted all appropriate cached schedule states, +it sets the Interrupt on Async Advance status bit in the USBSTS register. +If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. +The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. +Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. +This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. + 6 + 1 + read-write + + + ASE + ASE +Asynchronous Schedule Enable - Read/Write. Default 0b. +This bit controls whether the host controller skips processing the Asynchronous Schedule. +Only the host controller uses this bit. +Values Meaning +0 - Do not process the Asynchronous Schedule. +1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. + 5 + 1 + read-write + + + PSE + PSE +Periodic Schedule Enable- Read/Write. Default 0b. +This bit controls whether the host controller skips processing the Periodic Schedule. +Only the host controller uses this bit. +Values Meaning +0 - Do not process the Periodic Schedule +1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. + 4 + 1 + read-write + + + FS_1 + FS_1 +See description at bit 15 + 2 + 2 + read-write + + + RST + RST +Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. +This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. +Host operation mode: +When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. +Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. +Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. +Attempting to reset an actively running host controller will result in undefined behavior. +Device operation mode: +When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. +Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. +In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. + 1 + 1 + read-write + + + RS + RS +Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. +Host operation mode: +When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. +When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. +The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. +Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). +Device operation mode: +Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. +This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. +Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. + 0 + 1 + read-write + + + + + USBSTS + USB Status Register + 0x144 + 32 + 0x00000000 + 0x030DF1FF + + + TI1 + TI1 +General Purpose Timer Interrupt 1(GPTINT1)--R/WC. +This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this +bit will clear it. + 25 + 1 + read-write + + + TI0 + TI0 +General Purpose Timer Interrupt 0(GPTINT0)--R/WC. +This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this +bit clears it. + 24 + 1 + read-write + + + UPI + USB Host Periodic Interrupt – RWC. Default = 0b. +This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction +where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. +This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. +A short packet is when the actual number of bytes received was less than expected. +This bit is not used by the device controller and will always be zero. + 19 + 1 + read-write + + + UAI + USB Host Asynchronous Interrupt – RWC. Default = 0b. +This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction +where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. +This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. +A short packet is when the actual number of bytes received was less than expected. +This bit is not used by the device controller and will always be zero + 18 + 1 + read-write + + + NAKI + NAKI +NAK Interrupt Bit--RO. +This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and +corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware +when all Enabled TX/RX Endpoint NAK bits are cleared. + 16 + 1 + read-only + + + AS + AS +Asynchronous Schedule Status - Read Only. +This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. +The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. +When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). +Only used in the host operation mode. + 15 + 1 + read-only + + + PS + PS +Periodic Schedule Status - Read Only. +This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. +The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. +When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). +Only used in the host operation mode. + 14 + 1 + read-only + + + RCL + RCL +Reclamation - Read Only. +This is a read-only status bit used to detect an empty asynchronous schedule. +Only used in the host operation mode. + 13 + 1 + read-only + + + HCH + HCH +HCHaIted - Read Only. +This bit is a zero whenever the Run/Stop bit is a one. + The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, + either by software or by the Controller hardware (for example, an internal error). +Only used in the host operation mode. +Default value is '0b' for OTG core . +This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE +register. +NOTE: HCH bit reset value: '0b' for OTG controller core . + 12 + 1 + read-only + + + SLI + SLI +DCSuspend - R/WC. +When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. +Only used in device operation mode. + 8 + 1 + read-write + + + SRI + SRI +SOF Received - R/WC. +When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. +When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. +Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. +Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. +In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. +Software writes a 1 to this bit to clear it. + 7 + 1 + read-write + + + URI + URI +USB Reset Received - R/WC. +When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. +Software can write a 1 to this bit to clear the USB Reset Received status bit. +Only used in device operation mode. + 6 + 1 + read-write + + + AAI + AAI +Interrupt on Async Advance - R/WC. +System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule +by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. +Only used in host operation mode. + 5 + 1 + read-write + + + SEI + System Error – RWC. Default = 0b. +In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. +In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) + 4 + 1 + read-write + + + FRI + FRI +Frame List Rollover - R/WC. +The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to +zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the +frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the +Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host +Controller sets this bit to a one every time FHINDEX [12] toggles. +Only used in host operation mode. + 3 + 1 + read-write + + + PCI + PCI +Port Change Detect - R/WC. +The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, +or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. +The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. +When the port controller exits the full or high-speed operation states due to Reset or Suspend events, +the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. + 2 + 1 + read-write + + + UEI + UEI +USB Error Interrupt (USBERRINT) - R/WC. +When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. +This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. + 1 + 1 + read-write + + + UI + UI +USB Interrupt (USBINT) - R/WC. +This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB +transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. +This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when +the actual number of bytes received was less than the expected number of bytes. + 0 + 1 + read-write + + + + + USBINTR + Interrupt Enable Register + 0x148 + 32 + 0x00000000 + 0x030D01FF + + + TIE1 + TIE1 +General Purpose Timer #1 Interrupt Enable +When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. + 25 + 1 + read-write + + + TIE0 + TIE0 +General Purpose Timer #0 Interrupt Enable +When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. + 24 + 1 + read-write + + + UPIE + UPIE +USB Host Periodic Interrupt Enable +When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an +interrupt at the next interrupt threshold. + 19 + 1 + read-write + + + UAIE + UAIE +USB Host Asynchronous Interrupt Enable +When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an +interrupt at the next interrupt threshold. + 18 + 1 + read-write + + + NAKE + NAKE +NAK Interrupt Enable +When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. + 16 + 1 + read-only + + + SLE + SLE +Sleep Interrupt Enable +When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. +Only used in device operation mode. + 8 + 1 + read-write + + + SRE + SRE +SOF Received Interrupt Enable +When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. + 7 + 1 + read-write + + + URE + URE +USB Reset Interrupt Enable +When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in device operation mode. + 6 + 1 + read-write + + + AAE + AAE +Async Advance Interrupt Enable +When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in host operation mode. + 5 + 1 + read-write + + + SEE + SEE +System Error Interrupt Enable +When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in host operation mode. + 4 + 1 + read-write + + + FRE + FRE +Frame List Rollover Interrupt Enable +When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in host operation mode. + 3 + 1 + read-write + + + PCE + PCE +Port Change Detect Interrupt Enable +When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. + 2 + 1 + read-write + + + UEE + UEE +USB Error Interrupt Enable +When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. + 1 + 1 + read-write + + + UE + UE +USB Interrupt Enable +When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. + 0 + 1 + read-write + + + + + FRINDEX + USB Frame Index Register + 0x14c + 32 + 0x00000000 + 0x00003FFF + + + FRINDEX + FRINDEX +Frame Index. +The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. +This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. +The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. +USBCMD [Frame List Size] Number Elements N +In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. +In either mode bits 2:0 indicate the current microframe. +The bit field values description below is represented as (Frame List Size) Number Elements N. +00000000000000 - (1024) 12 +00000000000001 - (512) 11 +00000000000010 - (256) 10 +00000000000011 - (128) 9 +00000000000100 - (64) 8 +00000000000101 - (32) 7 +00000000000110 - (16) 6 +00000000000111 - (8) 5 + 0 + 14 + read-write + + + + + DEVICEADDR + Device Address Register + UNION_154 + 0x154 + 32 + 0x00000000 + 0xFF000000 + + + USBADR + USBADR +Device Address. +These bits correspond to the USB device address + 25 + 7 + read-write + + + USBADRA + USBADRA +Device Address Advance. Default=0. +When this bit is '0', any writes to USBADR are instantaneous. + When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. +After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. +Hardware will automatically clear this bit on the following conditions: +1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). +2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). +3) Device Reset occurs (USBADR is reset to 0). +NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. +This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. +If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), +the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. + 24 + 1 + read-write + + + + + PERIODICLISTBASE + Frame List Base Address Register + UNION_154 + 0x154 + 32 + 0x00000000 + 0xFFFFF000 + + + BASEADR + BASEADR +Base Address (Low). +These bits correspond to memory address signals [31:12], respectively. +Only used by the host controller. + 12 + 20 + read-write + + + + + ASYNCLISTADDR + Next Asynch. Address Register + UNION_158 + 0x158 + 32 + 0x00000000 + 0xFFFFFFE0 + + + ASYBASE + ASYBASE +Link Pointer Low (LPL). +These bits correspond to memory address signals [31:5], respectively. This field may only reference a +Queue Head (QH). +Only used by the host controller. + 5 + 27 + read-write + + + + + ENDPTLISTADDR + Endpoint List Address Register + UNION_158 + 0x158 + 32 + 0x00000000 + 0xFFFFF800 + + + EPBASE + EPBASE +Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. +This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). + 11 + 21 + read-write + + + + + BURSTSIZE + Programmable Burst Size Register + 0x160 + 32 + 0x00000000 + 0x0000FFFF + + + TXPBURST + TXPBURST +Programmable TX Burst Size. +Default value is determined by TXBURST bits in n_HWTXBUF. +This register represents the maximum length of a the burst in 32-bit words while moving data from system +memory to the USB bus. + 8 + 8 + read-write + + + RXPBURST + RXPBURST +Programmable RX Burst Size. +Default value is determined by TXBURST bits in n_HWRXBUF. +This register represents the maximum length of a the burst in 32-bit words while moving data from the +USB bus to system memory. + 0 + 8 + read-write + + + + + TXFILLTUNING + TX FIFO Fill Tuning Register + 0x164 + 32 + 0x00000000 + 0x003F1F7F + + + TXFIFOTHRES + TXFIFOTHRES +FIFO Burst Threshold. (Read/Write) +This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. +The minimum value is 2 and this value should be a low as possible to maximize USB performance. +A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth +where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. +This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. + 16 + 6 + read-write + + + TXSCHHEALTH + TXSCHHEALTH +Scheduler Health Counter. (Read/Write To Clear) +Table continues on the next page +This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES +before running out of time to send the packet before the next Start-Of-Frame. +This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. +Writing to this register will clear the counter and this counter will max. at 31. + 8 + 5 + read-write + + + TXSCHOH + TXSCHOH +Scheduler Overhead. (Read/Write) [Default = 0] +This register adds an additional fixed offset to the schedule time estimator described above as Tff. +As an approximation, the value chosen for this register should limit the number of back-off events captured +in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. +Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. +The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. +The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. +Default value is '08h' for OTG controller core . + 0 + 7 + read-write + + + + + ENDPTNAK + Endpoint NAK Register + 0x178 + 32 + 0x00000000 + 0xFFFFFFFF + + + EPTN + EPTN +TX Endpoint NAK - R/WC. +Each TX endpoint has 1 bit in this field. The bit is set when the +device sends a NAK handshake on a received IN token for the corresponding endpoint. +Bit [N] - Endpoint #[N], N is 0-7 + 16 + 16 + read-write + + + EPRN + EPRN +RX Endpoint NAK - R/WC. +Each RX endpoint has 1 bit in this field. The bit is set when the +device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. +Bit [N] - Endpoint #[N], N is 0-7 + 0 + 16 + read-write + + + + + ENDPTNAKEN + Endpoint NAK Enable Register + 0x17c + 32 + 0x00000000 + 0xFFFFFFFF + + + EPTNE + EPTNE +TX Endpoint NAK Enable - R/W. +Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the +corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. +Bit [N] - Endpoint #[N], N is 0-7 + 16 + 16 + read-write + + + EPRNE + EPRNE +RX Endpoint NAK Enable - R/W. +Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the +corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. +Bit [N] - Endpoint #[N], N is 0-7 + 0 + 16 + read-write + + + + + PORTSC1 + Port Status & Control + 0x184 + 32 + 0x00000000 + 0x3DFF1FFF + + + STS + STS +Serial Transceiver Select +1 Serial Interface Engine is selected +0 Parallel Interface signals is selected +Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. +When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. + 29 + 1 + read-write + + + PTW + PTW +Parallel Transceiver Width +This bit has no effect if serial interface engine is used. +0 - Select the 8-bit UTMI interface [60MHz] +1 - Select the 16-bit UTMI interface [30MHz] + 28 + 1 + read-write + + + PSPD + PSPD +Port Speed - Read Only. +This register field indicates the speed at which the port is operating. +00 - Full Speed +01 - Low Speed +10 - High Speed +11 - Undefined + 26 + 2 + read-only + + + PFSC + PFSC +Port Force Full Speed Connect - Read/Write. Default = 0b. +When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp +sequence that allows the port to identify itself as High Speed. +0 - Normal operation +1 - Forced to full speed + 24 + 1 + read-write + + + PHCD + PHCD +PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. +When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY +clock. +NOTE: The PHY clock cannot be disabled if it is being used as the system clock. +In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD +Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend +will be cleared automatically when the host initials resume. Before forcing a resume from the device, the +device controller driver must clear this bit. +In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put +into suspend mode or when no downstream device is connected. Low power suspend is completely +under the control of software. +0 - Enable PHY clock +1 - Disable PHY clock + 23 + 1 + read-write + + + WKOC + WKOC +Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. +Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. +This field is zero if Port Power(PORTSC1) is zero. + 22 + 1 + read-write + + + WKDC + WKDC +Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables +the port to be sensitive to device disconnects as wake-up events. +This field is zero if Port Power(PORTSC1) is zero or in device mode. + 21 + 1 + read-write + + + WKCN + WKCN +Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. +Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. +This field is zero if Port Power(PORTSC1) is zero or in device mode. + 20 + 1 + read-write + + + PTC + PTC +Port Test Control - Read/Write. Default = 0000b. +Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. +The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. +Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. +Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. +NOTE: Low speed operations are not supported as a peripheral device. +Any other value than zero indicates that the port is operating in test mode. +Value Specific Test +0000 - TEST_MODE_DISABLE +0001 - J_STATE +0010 - K_STATE +0011 - SE0 (host) / NAK (device) +0100 - Packet +0101 - FORCE_ENABLE_HS +0110 - FORCE_ENABLE_FS +0111 - FORCE_ENABLE_LS +1000-1111 - Reserved + 16 + 4 + read-write + + + PP + PP +Port Power (PP)-Read/Write or Read Only. +The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: +PPC +PP Operation +0 +1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. +1 +1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). +When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. +When an over-current condition is detected on a powered port and PPC is a one, +the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). +This feature is implemented in all controller cores (PPC = 1). + 12 + 1 + read-write + + + LS + LS +Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal +lines. +In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because +the port controller state machine and the port routing manage the connection of LS and FS. +In device mode, the use of linestate by the device controller driver is not necessary. +The encoding of the bits are: +Bits [11:10] Meaning +00 - SE0 +01 - K-state +10 - J-state +11 - Undefined + 10 + 2 + read-only + + + HSP + HSP +High-Speed Port - Read Only. Default = 0b. +When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the +host/device connected to the port is not in a high-speed mode. +NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. + 9 + 1 + read-only + + + PR + PR +Port Reset - Read/Write or Read Only. Default = 0b. +In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. +When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. +This bit will automatically change to zero after the reset sequence is complete. +This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. +In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. + 8 + 1 + read-write + + + SUSP + SUSP +Suspend - Read/Write or Read Only. Default = 0b. +1=Port in suspend state. 0=Port not in suspend state. +In Host Mode: Read/Write. +Port Enabled Bit and Suspend bit of this register define the port states as follows: +Bits [Port Enabled, Suspend] Port State +0x Disable +10 Enable +11 Suspend +When in suspend state, downstream propagation of data is blocked on this port, except for port reset. +The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. +In the suspend state, the port is sensitive to resume detection. +Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. +The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. +If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: Read Only. +In device mode this bit is a read only status bit. + 7 + 1 + read-write + + + FPR + FPR +Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. +In Host Mode: +Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. +When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. +This bit will automatically change to zero after the resume sequence is complete. +This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. +Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. +The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. +Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. +This field is zero if Port Power(PORTSC1) is zero in host mode. +This bit is not-EHCI compatible. +In Device mode: +After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. +The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. +The bit will be cleared when the device returns to normal operation. + Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. + 6 + 1 + read-write + + + OCC + OCC +Over-current Change-R/WC. Default=0. +This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. + 5 + 1 + read-write + + + OCA + OCA +Over-current Active-Read Only. Default 0. +This bit will automatically transition from one to zero when the over current condition is removed. +0 - This port does not have an over-current condition. +1 - This port currently has an over-current condition + 4 + 1 + read-only + + + PEC + PEC +Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. +In Host Mode: +For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or +due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). +Software clears this by writing a one to it. +This field is zero if Port Power(PORTSC1) is zero. +In Device mode: +The device port is always enabled, so this bit is always '0b'. + 3 + 1 + read-write + + + PE + PE +Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. +In Host Mode: +Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. +Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. +Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. +When the port is disabled, (0b) downstream propagation of data is blocked except for reset. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: +The device port is always enabled, so this bit is always '1b'. + 2 + 1 + read-write + + + CSC + CSC +Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. +In Host Mode: +Indicates a change has occurred in the port's Current Connect Status. +The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. +For example, the insertion status changes twice before system software has cleared the changed condition, +hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: +This bit is undefined in device controller mode. + 1 + 1 + read-write + + + CCS + CCS +Current Connect Status-Read Only. +In Host Mode: +1=Device is present on port. 0=No device is present. Default = 0. +This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: +1=Attached. 0=Not Attached. Default=0. +A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. +A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. +It does not state the device being disconnected or Suspended. + 0 + 1 + read-write + + + + + OTGSC + On-The-Go Status & control Register + 0x1a4 + 32 + 0x00000000 + 0x07070723 + + + ASVIE + ASVIE +A Session Valid Interrupt Enable - Read/Write. + 26 + 1 + read-write + + + AVVIE + AVVIE +A VBus Valid Interrupt Enable - Read/Write. +Setting this bit enables the A VBus valid interrupt. + 25 + 1 + read-write + + + IDIE + IDIE +USB ID Interrupt Enable - Read/Write. +Setting this bit enables the USB ID interrupt. + 24 + 1 + read-write + + + ASVIS + ASVIS +A Session Valid Interrupt Status - Read/Write to Clear. +This bit is set when VBus has either risen above or fallen below the A session valid threshold. +Software must write a one to clear this bit. + 18 + 1 + read-write + + + AVVIS + AVVIS +A VBus Valid Interrupt Status - Read/Write to Clear. +This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. +Software must write a one to clear this bit. + 17 + 1 + read-write + + + IDIS + IDIS +USB ID Interrupt Status - Read/Write. +This bit is set when a change on the ID input has been detected. +Software must write a one to clear this bit. + 16 + 1 + read-write + + + ASV + ASV +A Session Valid - Read Only. +Indicates VBus is above the A session valid threshold. + 10 + 1 + read-only + + + AVV + AVV +A VBus Valid - Read Only. +Indicates VBus is above the A VBus valid threshold. + 9 + 1 + read-only + + + ID + ID +USB ID - Read Only. +0 = A device, 1 = B device + 8 + 1 + read-only + + + IDPU + IDPU +ID Pullup - Read/Write +This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input +will not be sampled. + 5 + 1 + read-write + + + VC + VC +VBUS Charge - Read/Write. +Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. + 1 + 1 + read-write + + + VD + VD +VBUS_Discharge - Read/Write. +Setting this bit causes VBus to discharge through a resistor. + 0 + 1 + read-write + + + + + USBMODE + USB Device Mode Register + 0x1a8 + 32 + 0x00000000 + 0x0000001F + + + SDIS + SDIS +Stream Disable Mode. (0 - Inactive [default]; 1 - Active) +Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. +This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. +Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. +Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems +where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. +NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for +the scheduler when using this feature. +NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. + 4 + 1 + read-write + + + SLOM + SLOM +Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . +0 - Setup Lockouts On (default); +1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. + 3 + 1 + read-write + + + ES + ES +Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the +host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected +by the value of this bit because they are based upon the 32-bit word. +Bit Meaning +0 - Little Endian [Default] +1 - Big Endian + 2 + 1 + read-write + + + CM + CM +Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only +implementations. For those designs that contain both host & device capability, the controller defaults to +an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ +device controllers, this register can only be written once after reset. If it is necessary to switch modes, +software must reset the controller by writing to the RESET bit in the USBCMD register before +reprogramming this register. +For OTG controller core, reset value is '00b'. +00 - Idle [Default for combination host/device] +01 - Reserved +10 - Device Controller [Default for device only controller] +11 - Host Controller [Default for host only controller] + 0 + 2 + read-write + + + + + ENDPTSETUPSTAT + Endpoint Setup Status Register + 0x1ac + 32 + 0x00000000 + 0x0000FFFF + + + ENDPTSETUPSTAT + ENDPTSETUPSTAT +Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. +Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. +The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. +This register is only used in device mode. + 0 + 16 + read-write + + + + + ENDPTPRIME + Endpoint Prime Register + 0x1b0 + 32 + 0x00000000 + 0xFFFFFFFF + + + PETB + PETB +Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a +buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. +Software should write a one to the corresponding bit when posting a new transfer descriptor to an +endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor +from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated +endpoint(s) is (are) successfully primed. +NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD +is retired, and the dQH is updated. +PETB[N] - Endpoint #N, N is in 0..7 + 16 + 16 + read-write + + + PERB + PERB +Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. +Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. +Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. +Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. +NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD +is retired, and the dQH is updated. +PERB[N] - Endpoint #N, N is in 0..7 + 0 + 16 + read-write + + + + + ENDPTFLUSH + Endpoint Flush Register + 0x1b4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FETB + FETB +Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. +If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. +Hardware clears this register after the endpoint flush operation is successful. +FETB[N] - Endpoint #N, N is in 0..7 + 16 + 16 + read-write + + + FERB + FERB +Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. + If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. +Hardware clears this register after the endpoint flush operation is successful. +FERB[N] - Endpoint #N, N is in 0..7 + 0 + 16 + read-write + + + + + ENDPTSTAT + Endpoint Status Register + 0x1b8 + 32 + 0x00000000 + 0xFFFFFFFF + + + ETBR + ETBR +Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. +This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. +There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. +This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. +Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. +NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. +ETBR[N] - Endpoint #N, N is in 0..7 + 16 + 16 + read-only + + + ERBR + ERBR +Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective +endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a +corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the +ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB +traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the +USB DMA system, or through the ENDPTFLUSH register. +NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations +when a dTD is retired, and the dQH is updated. +ERBR[N] - Endpoint #N, N is in 0..7 + 0 + 16 + read-only + + + + + ENDPTCOMPLETE + Endpoint Complete Register + 0x1bc + 32 + 0x00000000 + 0xFFFFFFFF + + + ETCE + ETCE +Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. +If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. +ETCE[N] - Endpoint #N, N is in 0..7 + 16 + 16 + read-write + + + ERCE + ERCE +Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred +and software should read the corresponding endpoint queue to determine the transfer status. If the +corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the +USBINT . Writing one clears the corresponding bit in this register. +ERCE[N] - Endpoint #N, N is in 0..7 + 0 + 16 + read-write + + + + + 8 + 0x4 + ENDPTCTRL0,ENDPTCTRL1,ENDPTCTRL2,ENDPTCTRL3,ENDPTCTRL4,ENDPTCTRL5,ENDPTCTRL6,ENDPTCTRL7 + ENDPTCTRL[%s] + no description available + 0x1c0 + 32 + 0x00000000 + 0x00CD00CD + + + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 + read-write + + + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 + 1 + write-only + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 + read-write + + + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured +as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 + 1 + read-write + + + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 + 1 + read-write + + + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 + 1 + write-only + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 + read-write + + + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 + 1 + read-write + + + + + OTG_CTRL0 + No description available + 0x200 + 32 + 0x00000000 + 0x020B3F90 + + + OTG_WKDPDMCHG_EN + No description available + 25 + 1 + read-write + + + AUTORESUME_EN + No description available + 19 + 1 + read-write + + + OTG_VBUS_WAKEUP_EN + No description available + 17 + 1 + read-write + + + OTG_ID_WAKEUP_EN + No description available + 16 + 1 + read-write + + + OTG_VBUS_SOURCE_SEL + No description available + 13 + 1 + read-write + + + OTG_UTMI_SUSPENDM_SW + default 0 for naneng usbphy + 12 + 1 + read-write + + + OTG_UTMI_RESET_SW + default 1 for naneng usbphy + 11 + 1 + read-write + + + OTG_WAKEUP_INT_ENABLE + No description available + 10 + 1 + read-write + + + OTG_POWER_MASK + No description available + 9 + 1 + read-write + + + OTG_OVER_CUR_POL + No description available + 8 + 1 + read-write + + + OTG_OVER_CUR_DIS + No description available + 7 + 1 + read-write + + + SER_MODE_SUSPEND_EN + for naneng usbphy, only switch to serial mode when suspend + 4 + 1 + read-write + + + + + PHY_CTRL0 + No description available + 0x210 + 32 + 0x00000000 + 0x02007007 + + + GPIO_ID_SEL_N + No description available + 25 + 1 + read-write + + + ID_DIG_OVERRIDE + No description available + 14 + 1 + read-write + + + SESS_VALID_OVERRIDE + No description available + 13 + 1 + read-write + + + VBUS_VALID_OVERRIDE + No description available + 12 + 1 + read-write + + + ID_DIG_OVERRIDE_EN + No description available + 2 + 1 + read-write + + + SESS_VALID_OVERRIDE_EN + No description available + 1 + 1 + read-write + + + VBUS_VALID_OVERRIDE_EN + No description available + 0 + 1 + read-write + + + + + PHY_CTRL1 + No description available + 0x214 + 32 + 0x00000000 + 0x00100002 + + + UTMI_CFG_RST_N + No description available + 20 + 1 + read-write + + + UTMI_OTG_SUSPENDM + OTG suspend, not utmi_suspendm + 1 + 1 + read-write + + + + + TOP_STATUS + No description available + 0x220 + 32 + 0x00000000 + 0x80000000 + + + WAKEUP_INT_STATUS + No description available + 31 + 1 + read-write + + + + + PHY_STATUS + No description available + 0x224 + 32 + 0x00000000 + 0x800000F5 + + + UTMI_CLK_VALID + No description available + 31 + 1 + read-write + + + LINE_STATE + No description available + 6 + 2 + read-write + + + HOST_DISCONNECT + No description available + 5 + 1 + read-write + + + ID_DIG + No description available + 4 + 1 + read-write + + + UTMI_SESS_VALID + No description available + 2 + 1 + read-write + + + VBUS_VALID + No description available + 0 + 1 + read-write + + + + + + + SDXC0 + SDXC0 + SDXC + 0xf2030000 + + 0x0 + 0x3008 + registers + + + + SDMASA + No description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + BLOCKCNT_SDMASA + 32-bit Block Count (SDMA System Address) +- SDMA System Address (Host Version 4 Enable = 0): This register contains the system memory address for an SDMA transfer in the 32-bit addressing mode. +When the Host Controller stops an SDMA transfer, this register points to the system address of the next contiguous data position. +It can be accessed only if no transaction is executing. Reading this register during data transfers may +return an invalid value. +- 32-bit Block Count (Host Version 4 Enable = 1): From the Host Controller Version 4.10 specification, this register is redefined as 32-bit Block Count. +The Host Controller decrements the block count of this register for every block transfer and the data transfer stops when the count reaches zero. +This register must be accessed when no transaction is executing. Reading this register during data transfers may return invalid value. +Following are the values for BLOCKCNT_SDMASA: +- 0xFFFF_FFFF: 4G - 1 Block +- +- 0x0000_0002: 2 Blocks +- 0x0000_0001: 1 Block +- 0x0000_0000: Stop Count +Note: +- For Host Version 4 Enable = 0, the Host driver does not program the system address in this register while operating in ADMA mode. +The system address must be programmed in the ADMA System Address register. +- For Host Version 4 Enable = 0, the Host driver programs a non-zero 32-bit block count value in this register when Auto CMD23 is enabled for non-DMA and ADMA modes. +Auto CMD23 cannot be used with SDMA. +- This register must be programmed with a non-zero value for data transfer if the 32-bit Block count register is used instead of the 16-bit Block count register. + 0 + 32 + read-write + + + + + BLK_ATTR + No description available + 0x4 + 32 + 0x00020210 + 0xFFFF7FFF + + + BLOCK_CNT + 16-bit Block Count +- If the Host Version 4 Enable bit is set 0 or the 16-bit Block Count register is set to non-zero, the 16-bit Block Count register is selected. +- If the Host Version 4 Enable bit is set 1 and the 16-bit Block Count register is set to zero, the 32-bit Block Count register is selected. +Following are the values for BLOCK_CNT: +- 0x0: Stop Count +- 0x1: 1 Block +- 0x2: 2 Blocks +- . +- 0xFFFF: 65535 Blocks +Note: For Host Version 4 Enable = 0, this register must be set to 0000h before programming the 32-bit block count register when Auto CMD23 is enabled for non-DMA and ADMA modes. + 16 + 16 + read-write + + + SDMA_BUF_BDARY + SDMA Buffer Boundary +These bits specify the size of contiguous buffer in system memory. +The SDMA transfer waits at every boundary specified by these fields and the Host Controller generates the DMA interrupt to request the Host Driver to update the SDMA System Address register. +Values: +- 0x0 (BYTES_4K): 4K bytes SDMA Buffer Boundary +- 0x1 (BYTES_8K): 8K bytes SDMA Buffer Boundary +- 0x2 (BYTES_16K): 16K bytes SDMA Buffer Boundary +- 0x3 (BYTES_32K): 32K bytes SDMA Buffer Boundary +- 0x4 (BYTES_64K): 64K bytes SDMA Buffer Boundary +- 0x5 (BYTES_128K): 128K bytes SDMA Buffer Boundary +- 0x6 (BYTES_256K): 256K bytes SDMA Buffer Boundary +- 0x7 (BYTES_512K): 512K bytes SDMA Buffer Boundary + 12 + 3 + read-write + + + XFER_BLOCK_SIZE + Transfer Block Size +These bits specify the block size of data transfers. In case of memory, it is set to 512 bytes. It can be accessed only if no transaction is executing. +Read operations during transfers may return an invalid value, and write operations are ignored. Following are the values for XFER_BLOCK_SIZE: +- 0x1: 1 byte +- 0x2: 2 bytes +- 0x3: 3 bytes +- . +- 0x1FF: 511 byte +- 0x200: 512 byt es +- . +- 0x800: 2048 bytes +Note: This register must be programmed with a non-zero value for data transfer. + 0 + 12 + read-write + + + + + CMD_ARG + No description available + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + ARGUMNET + Command Argument +These bits specify the SD/eMMC command argument that is specified in bits 39-8 of the Command format. + 0 + 32 + read-write + + + + + CMD_XFER + No description available + 0xc + 32 + 0x00000000 + 0x3FFF01FF + + + CMD_INDEX + Command Index +These bits are set to the command number that is specified in bits 45-40 of the Command Format. + 24 + 6 + read-write + + + CMD_TYPE + Command Type +These bits indicate the command type. +Note: While issuing Abort CMD using CMD12/CMD52 or reset CMD using CMD0/CMD52, CMD_TYPE field shall be set to 0x3. +Values: +0x3 (ABORT_CMD): Abort +0x2 (RESUME_CMD): Resume +0x1 (SUSPEND_CMD): Suspend +0x0 (NORMAL_CMD): Normal + 22 + 2 + read-write + + + DATA_PRESENT_SEL + Data Present Select +This bit is set to 1 to indicate that data is present and that the data is transferred using the DAT line. This bit is set to 0 in the following instances: +Command using the CMD line +Command with no data transfer but using busy signal on the DAT[0] line +Resume Command +Values: +0x0 (NO_DATA): No Data Present +0x1 (DATA): Data Present + 21 + 1 + read-write + + + CMD_IDX_CHK_ENABLE + Command Index Check Enable +This bit enables the Host Controller to check the index field in the response to verify if it has the same value as the command index. +If the value is not the same, it is reported as a Command Index error. +Note: +Index Check enable must be set to 0 for the command with no response, R2 response, R3 response and R4 response. +For the tuning command, this bit must always be set to enable the index check. +Values: +0x0 (DISABLED): Disable +0x1 (ENABLED): Enable + 20 + 1 + read-write + + + CMD_CRC_CHK_ENABLE + Command CRC Check Enable +This bit enables the Host Controller to check the CRC field in the response. If an error is detected, it is reported as a Command CRC error. +Note: +CRC Check enable must be set to 0 for the command with no response, R3 response, and R4 response. +For the tuning command, this bit must always be set to 1 to enable the CRC check. +Values: +0x0 (DISABLED): Disable +0x1 (ENABLED): Enable + 19 + 1 + read-write + + + SUB_CMD_FLAG + Sub Command Flag +This bit distinguishes between a main command and a sub command. +Values: +0x0 (MAIN): Main Command +0x1 (SUB): Sub Command + 18 + 1 + read-write + + + RESP_TYPE_SELECT + Response Type Select +This bit indicates the type of response expected from the card. +Values: +0x0 (NO_RESP): No Response +0x1 (RESP_LEN_136): Response Length 136 +0x2 (RESP_LEN_48): Response Length 48 +0x3 (RESP_LEN_48B): Response Length 48; Check Busy after response + 16 + 2 + read-write + + + RESP_INT_DISABLE + Response Interrupt Disable +The Host Controller supports response check function to avoid overhead of response error check by the Host driver. +Response types of only R1 and R5 can be checked by the Controller. +If Host Driver checks the response error, set this bit to 0 and wait for Command Complete Interrupt and then check the response register. +If the Host Controller checks the response error, set this bit to 1 and set the Response Error Check Enable bit to 1. +The Command Complete Interrupt is disabled by this bit regardless of the Command Complete Signal Enable. +Note: During tuning (when the Execute Tuning bit in the Host Control2 register is set), the Command Complete Interrupt is not generated irrespective of the Response Interrupt Disable setting. +Values: +- 0x0 (ENABLED): Response Interrupt is enabled +- 0x1 (DISABLED): Response Interrupt is disabled + 8 + 1 + read-write + + + RESP_ERR_CHK_ENABLE + Response Error Check Enable +The Host Controller supports response check function to avoid overhead of response error check by Host driver. Response types of only R1 and R5 can be checked by the Controller. +If the Host Controller checks the response error, set this bit to 1 and set Response Interrupt Disable to 1. If an error is detected, the Response Error interrupt is generated in the Error Interrupt Status register. +Note: +- Response error check must not be enabled for any response type other than R1 and R5. +- Response check must not be enabled for the tuning command. +Values: +- 0x0 (DISABLED): Response Error Check is disabled +- 0x1 (ENABLED): Response Error Check is enabled + 7 + 1 + read-write + + + RESP_TYPE + Response Type R1/R5 +This bit selects either R1 or R5 as a response type when the Response Error Check is selected. +Error statuses checked in R1: +OUT_OF_RANGE +ADDRESS_ERROR +BLOCK_LEN_ERROR +WP_VIOLATION +CARD_IS_LOCKED +COM_CRC_ERROR +CARD_ECC_FAILED +CC_ERROR +ERROR +Response Flags checked in R5: +COM_CRC_ERROR +ERROR +FUNCTION_NUMBER +OUT_OF_RANGE +Values: +0x0 (RESP_R1): R1 (Memory) +0x1 (RESP_R5): R5 (SDIO) + 6 + 1 + read-write + + + MULTI_BLK_SEL + Multi/Single Block Select +This bit is set when issuing multiple-block transfer commands using the DAT line. If this bit is set to 0, it is not necessary to set the Block Count register. +Values: +0x0 (SINGLE): Single Block +0x1 (MULTI): Multiple Block + 5 + 1 + read-write + + + DATA_XFER_DIR + Data Transfer Direction Select +This bit defines the direction of DAT line data transfers. +This bit is set to 1 by the Host Driver to transfer data from the SD/eMMC card to the Host Controller and it is set to 0 for all other commands. +Values: +0x1 (READ): Read (Card to Host) +0x0 (WRITE): Write (Host to Card) + 4 + 1 + read-write + + + AUTO_CMD_ENABLE + Auto Command Enable +This field determines use of Auto Command functions. +Note: In SDIO, this field must be set as 00b (Auto Command Disabled). +Values: +0x0 (AUTO_CMD_DISABLED): Auto Command Disabled +0x1 (AUTO_CMD12_ENABLED): Auto CMD12 Enable +0x2 (AUTO_CMD23_ENABLED): Auto CMD23 Enable +0x3 (AUTO_CMD_AUTO_SEL): Auto CMD Auto Sel + 2 + 2 + read-write + + + BLOCK_COUNT_ENABLE + Block Count Enable +This bit is used to enable the Block Count register, which is relevant for multiple block transfers. +If this bit is set to 0, the Block Count register is disabled, which is useful in executing an infinite transfer. +The Host Driver must set this bit to 0 when ADMA is used. +Values: +0x1 (ENABLED): Enable +0x0 (DISABLED): Disable + 1 + 1 + read-write + + + DMA_ENABLE + DMA Enable +This bit enables the DMA functionality. If this bit is set to 1, a DMA operation begins when the Host Driver writes to the Command register. +You can select one of the DMA modes by using DMA Select in the Host Control 1 register. +Values: +0x1 (ENABLED): DMA Data transfer +0x0 (DISABLED): No data transfer or Non-DMA data transfer + 0 + 1 + read-write + + + + + 4 + 0x4 + RESP01,RESP23,RESP45,RESP67 + RESP[%s] + no description available + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESP01 + Command Response +These bits reflect 39-8 bits of SD/eMMC Response Field. +Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP[RESP67] register. + 0 + 32 + read-only + + + + + BUF_DATA + No description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + BUF_DATA + Buffer Data +These bits enable access to the Host Controller packet buffer. + 0 + 32 + read-write + + + + + PSTATE + No description available + 0x24 + 32 + 0x00000000 + 0x19FF0FFF + + + SUB_CMD_STAT + Sub Command Status +This bit is used to distinguish between a main command and a sub command status. +Values: +0x0 (FALSE): Main Command Status +0x1 (TRUE): Sub Command Status + 28 + 1 + read-only + + + CMD_ISSUE_ERR + Command Not Issued by Error +This bit is set if a command cannot be issued after setting the command register due to an error except the Auto CMD12 error. +Values: +0x0 (FALSE): No error for issuing a command +0x1 (TRUE): Command cannot be issued + 27 + 1 + read-only + + + CMD_LINE_LVL + Command-Line Signal Level +This bit is used to check the CMD line level to recover from errors and for debugging. These bits reflect the value of the sd_cmd_in signal. + 24 + 1 + read-only + + + DAT_3_0 + DAT[3:0] Line Signal Level +This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (lower nibble) signal. + 20 + 4 + read-only + + + WR_PROTECT_SW_LVL + Write Protect Switch Pin Level +This bit is supported only for memory and combo cards. This bit reflects the synchronized value of the card_write_prot signal. +Values: +0x0 (FALSE): Write protected +0x1 (TRUE): Write enabled + 19 + 1 + read-only + + + CARD_DETECT_PIN_LEVEL + Card Detect Pin Level +This bit reflects the inverse synchronized value of the card_detect_n signal. +Values: +0x0 (FALSE): No card present +0x1 (TRUE): Card Present + 18 + 1 + read-only + + + CARD_STABLE + Card Stable +This bit indicates the stability of the Card Detect Pin Level. A card is not detected if this bit is set to 1 and the value of the CARD_INSERTED bit is 0. +Values: +0x0 (FALSE): Reset or Debouncing +0x1 (TRUE): No Card or Inserted + 17 + 1 + read-only + + + CARD_INSERTED + Card Inserted +This bit indicates whether a card has been inserted. The Host Controller debounces this signal so that Host Driver need not wait for it to stabilize. +Values: +0x0 (FALSE): Reset, Debouncing, or No card +0x1 (TRUE): Card Inserted + 16 + 1 + read-only + + + BUF_RD_ENABLE + Buffer Read Enable +This bit is used for non-DMA transfers. This bit is set if valid data exists in the Host buffer. +Values: +0x0 (DISABLED): Read disable +0x1 (ENABLED): Read enable + 11 + 1 + read-only + + + BUF_WR_ENABLE + Buffer Write Enable +This bit is used for non-DMA transfers. This bit is set if space is available for writing data. +Values: +0x0 (DISABLED): Write disable +0x1 (ENABLED): Write enable + 10 + 1 + read-only + + + RD_XFER_ACTIVE + Read Transfer Active +This bit indicates whether a read transfer is active for SD/eMMC mode. +Values: +0x0 (INACTIVE): No valid data +0x1 (ACTIVE): Transferring data + 9 + 1 + read-only + + + WR_XFER_ACTIVE + Write Transfer Active +This status indicates whether a write transfer is active for SD/eMMC mode. +Values: +0x0 (INACTIVE): No valid data +0x1 (ACTIVE): Transferring data + 8 + 1 + read-only + + + DAT_7_4 + DAT[7:4] Line Signal Level +This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (upper nibble) signal. + 4 + 4 + read-only + + + RE_TUNE_REQ + Re-Tuning Request +SDXC does not generate retuning request. The software must maintain the Retuning timer. + 3 + 1 + read-only + + + DAT_LINE_ACTIVE + DAT Line Active ( +This bit indicates whether one of the DAT lines on the SD/eMMC bus is in use. +In the case of read transactions, this bit indicates whether a read transfer is executing on the SD/eMMC bus. +In the case of write transactions, this bit indicates whether a write transfer is executing on the SD/eMMC bus. +For a command with busy, this status indicates whether the command executing busy is executing on an SD or eMMC bus. +Values: +0x0 (INACTIVE): DAT Line Inactive +0x1 (ACTIVE): DAT Line Active + 2 + 1 + read-only + + + DAT_INHIBIT + Command Inhibit (DAT) +This bit is generated if either DAT line active or Read transfer active is set to 1. +If this bit is set to 0, it indicates that the Host Controller can issue subsequent SD/eMMC commands. +Values: +0x0 (READY): Can issue command which used DAT line +0x1 (NOT_READY): Cannot issue command which used DAT line + 1 + 1 + read-only + + + CMD_INHIBIT + Command Inhibit (CMD) +This bit indicates the following : +If this bit is set to 0, it indicates that the CMD line is not in use and the Host controller can issue an SD/eMMC command using the CMD line. +This bit is set when the command register is written. This bit is cleared when the command response is received. +This bit is not cleared by the response of auto CMD12/23 but cleared by the response of read/write command. +Values: +0x0 (READY): Host Controller is ready to issue a command +0x1 (NOT_READY): Host Controller is not ready to issue a command + 0 + 1 + read-only + + + + + PROT_CTRL + No description available + 0x28 + 32 + 0x00000000 + 0x070F0F3E + + + CARD_REMOVAL + Wakeup Event Enable on SD Card Removal +This bit enables wakeup event through Card Removal assertion in the Normal Interrupt Status register. +For the SDIO card, Wake Up Support (FN_WUS) in the Card Information Structure (CIS) register does not affect this bit. +Values: +0x0 (DISABLED): Disable +0x1 (ENABLED): Enable + 26 + 1 + read-write + + + CARD_INSERT + Wakeup Event Enable on SD Card Insertion +This bit enables wakeup event through Card Insertion assertion in the Normal Interrupt Status register. +FN_WUS (Wake Up Support) in CIS does not affect this bit. +Values: +0x0 (DISABLED): Disable +0x1 (ENABLED): Enable + 25 + 1 + read-write + + + CARD_INT + Wakeup Event Enable on Card Interrupt +This bit enables wakeup event through a Card Interrupt assertion in the Normal Interrupt Status register. +This bit can be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1. +Values: +0x0 (DISABLED): Disable +0x1 (ENABLED): Enable + 24 + 1 + read-write + + + INT_AT_BGAP + Interrupt At Block Gap +This bit is valid only in the 4-bit mode of an SDIO card and is used to select a sample point in the interrupt cycle. +Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. +Values: +0x0 (DISABLE): Disabled +0x1 (ENABLE): Enabled + 19 + 1 + read-write + + + RD_WAIT_CTRL + Read Wait Control +This bit is used to enable the read wait protocol to stop read data using DAT[2] line if the card supports read wait. +Otherwise, the Host Controller has to stop the card clock to hold the read data. In UHS-II mode, Read Wait is disabled. +Values: +0x0 (DISABLE): Disable Read Wait Control +0x1 (ENABLE): Enable Read Wait Control + 18 + 1 + read-write + + + CONTINUE_REQ + Continue Request +This bit is used to restart the transaction, which was stopped using the Stop At Block Gap Request. +The Host Controller automatically clears this bit when the transaction restarts. +If stop at block gap request is set to 1, any write to this bit is ignored. +Values: +0x0 (NO_AFFECT): No Affect +0x1 (RESTART): Restart + 17 + 1 + read-write + + + STOP_BG_REQ + Stop At Block Gap Request +This bit is used to stop executing read and write transactions at the next block gap for non-DMA, SDMA, and ADMA transfers. +Values: +0x0 (XFER): Transfer +0x1 (STOP): Stop + 16 + 1 + read-write + + + SD_BUS_VOL_VDD1 + SD Bus Voltage Select for VDD1/eMMC Bus Voltage Select for VDD +These bits enable the Host Driver to select the voltage level for an SD/eMMC card. +Before setting this register, the Host Driver checks the Voltage Support bits in the Capabilities register. +If an unsupported voltage is selected, the Host System does not supply the SD Bus voltage. +The value set in this field is available on the SDXC output signal (sd_vdd1_sel), which is used by the voltage switching circuitry. +SD Bus Voltage Select options: +0x7 : 3.3V(Typical) +0x6 : 3.0V(Typical) +0x5 : 1.8V(Typical) for Embedded +0x4 : 0x0 - Reserved +eMMC Bus Voltage Select options: +0x7 : 3.3V(Typical) +0x6 : 1.8V(Typical) +0x5 : 1.2V(Typical) +0x4 : 0x0 - Reserved +Values: +0x7 (V_3_3): 3.3V (Typ.) +0x6 (V_3_0): 3.0V (Typ.) +0x5 (V_1_8): 1.8V (Typ.) for Embedded +0x4 (RSVD4): Reserved +0x3 (RSVD3): Reserved +0x2 (RSVD2): Reserved +0x1 (RSVD1): Reserved +0x0 (RSVD0): Reserved + 9 + 3 + read-write + + + SD_BUS_PWR_VDD1 + SD Bus Power for VDD1 +This bit enables VDD1 power of the card. +This setting is available on the sd_vdd1_on output of SDXC so that it can be used to control the VDD1 power supply of the card. +Before setting this bit, the SD Host Driver sets the SD Bus Voltage Select bit. If the Host Controller detects a No Card state, this bit is cleared. +In SD mode, if this bit is cleared, the Host Controller stops the SD Clock by clearing the SD_CLK_EN bit in the SYS_CTRL register. +Values: +0x0 (OFF): Power off +0x1 (ON): Power on + 8 + 1 + read-write + + + EXT_DAT_XFER + Extended Data Transfer Width +This bit controls 8-bit bus width mode of embedded device. +Values: +0x1 (EIGHT_BIT): 8-bit Bus Width +0x0 (DEFAULT): Bus Width is selected by the Data Transfer Width + 5 + 1 + read-write + + + DMA_SEL + DMA Select +This field is used to select the DMA type. +When Host Version 4 Enable is 1 in Host Control 2 register: +0x0 : SDMA is selected +0x1 : Reserved +0x2 : ADMA2 is selected +0x3 : ADMA2 or ADMA3 is selected +When Host Version 4 Enable is 0 in Host Control 2 register: +0x0 : SDMA is selected +0x1 : Reserved +0x2 : 32-bit Address ADMA2 is selected +0x3 : 64-bit Address ADMA2 is selected +Values: +0x0 (SDMA): SDMA is selected +0x1 (RSVD_BIT): Reserved +0x2 (ADMA2): ADMA2 is selected +0x3 (ADMA2_3): ADMA2 or ADMA3 is selected + 3 + 2 + read-write + + + HIGH_SPEED_EN + High Speed Enable +this bit is used to determine the selection of preset value for High Speed mode. +Before setting this bit, the Host Driver checks the High Speed Support in the Capabilities register. +Note: SDXC always outputs the sd_cmd_out and sd_dat_out lines at the rising edge of cclk_tx clock irrespective of this bit. +Values: +0x1 (HIGH_SPEED): High Speed mode +0x0 (NORMAL_SPEED): Normal Speed mode + 2 + 1 + read-write + + + DAT_XFER_WIDTH + Data Transfer Width +For SD/eMMC mode,this bit selects the data transfer width of the Host Controller. +The Host Driver sets it to match the data width of the SD/eMMC card. In UHS-II mode, this bit is irrelevant. +Values: +0x1 (FOUR_BIT): 4-bit mode +0x0 (ONE_BIT): 1-bit mode + 1 + 1 + read-write + + + + + SYS_CTRL + No description available + 0x2c + 32 + 0x00000000 + 0x070FFFEF + + + SW_RST_DAT + Software Reset For DAT line +This bit is used in SD/eMMC mode and it resets only a part of the data circuit and the DMA circuit is also reset. +The following registers and bits are cleared by this bit: +Buffer Data Port register +-Buffer is cleared and initialized. +Present state register +-Buffer Read Enable +-Buffer Write Enable +-Read Transfer Active +-Write Transfer Active +-DAT Line Active +-Command Inhibit (DAT) +Block Gap Control register +-Continue Request +-Stop At Block Gap Request +Normal Interrupt status register +-Buffer Read Ready +-Buffer Write Ready +-DMA Interrupt +-Block Gap Event +-Transfer Complete +In UHS-II mode, this bit shall be set to 0 +Values: +0x0 (FALSE): Work +0x1 (TRUE): Reset + 26 + 1 + read-write + + + SW_RST_CMD + Software Reset For CMD line +This bit resets only a part of the command circuit to be able to issue a command. +It bit is also used to initialize a UHS-II command circuit. +This reset is effective only for a command issuing circuit (including response error statuses related to Command Inhibit (CMD) control) and does not affect the data transfer circuit. +Host Controller can continue data transfer even after this reset is executed while handling subcommand-response errors. +The following registers and bits are cleared by this bit: +Present State register : Command Inhibit (CMD) bit +Normal Interrupt Status register : Command Complete bit +Error Interrupt Status : Response error statuses related to Command Inhibit (CMD) bit +Values: +0x0 (FALSE): Work +0x1 (TRUE): Reset + 25 + 1 + read-write + + + SW_RST_ALL + Software Reset For All +This reset affects the entire Host Controller except for the card detection circuit. +During its initialization, the Host Driver sets this bit to 1 to reset the Host Controller. +All registers are reset except the capabilities register. +If this bit is set to 1, the Host Driver must issue reset command and reinitialize the card. +Values: +0x0 (FALSE): Work +0x1 (TRUE): Reset + 24 + 1 + read-write + + + TOUT_CNT + Data Timeout Counter Value. +This value determines the interval by which DAT line timeouts are detected. +The Timeout clock frequency is generated by dividing the base clock TMCLK value by this value. +When setting this register, prevent inadvertent timeout events by clearing the Data Timeout Error Status Enable (in the Error Interrupt Status Enable register). +The values for these bits are: +0xF : Reserved +0xE : TMCLK x 2^27 +......... +0x1 : TMCLK x 2^14 +0x0 : TMCLK x 2^13 +Note: During a boot operating in an eMMC mode, an application must configure the boot data timeout value (approximately 1 sec) in this bit. + 16 + 4 + read-write + + + FREQ_SEL + SDCLK/RCLK Frequency Select +These bits are used to select the frequency of the SDCLK signal. +These bits depend on setting of Preset Value Enable in the Host Control 2 register. +If Preset Value Enable = 0, these bits are set by the Host Driver. +If Preset Value Enable = 1, these bits are automatically set to a value specified in one of the Preset Value register. +The value is reflected on the lower 8-bit of the card_clk_freq_selsignal. +10-bit Divided Clock Mode: +0x3FF : 1/2046 Divided clock +.......... +N : 1/2N Divided Clock +.......... +0x002 : 1/4 Divided Clock +0x001 : 1/2 Divided Clock +0x000 : Base clock (10MHz - 255 MHz) +Programmable Clock Mode : Enables the Host System to select a fine grain SD clock frequency: +0x3FF : Base clock * M /1024 +.......... +N-1 : Base clock * M /N +.......... +0x002 : Base clock * M /3 +0x001 : Base clock * M /2 +0x000 : Base clock * M + 8 + 8 + read-write + + + UPPER_FREQ_SEL + These bits specify the upper 2 bits of 10-bit SDCLK/RCLK Frequency Select control. +The value is reflected on the upper 2 bits of the card_clk_freq_sel signal. + 6 + 2 + read-write + + + CLK_GEN_SELECT + Clock Generator Select +This bit is used to select the clock generator mode in SDCLK/RCLK Frequency Select. +If Preset Value Enable = 0, this bit is set by the Host Driver. +If Preset Value Enable = 1, this bit is automatically set to a value specified in one of the Preset Value registers. +The value is reflected on the card_clk_gen_sel signal. +Values: +0x0 (FALSE): Divided Clock Mode +0x1 (TRUE): Programmable Clock Mode + 5 + 1 + read-write + + + PLL_ENABLE + PLL Enable +This bit is used to activate the PLL (applicable when Host Version 4 Enable = 1). +When Host Version 4 Enable = 0, INTERNAL_CLK_EN bit may be used to activate PLL. The value is reflected on the card_clk_en signal. +Note: If this bit is not used to to active the PLL when Host Version 4 Enable = 1, it is recommended to set this bit to '1' . +Values: +0x0 (FALSE): PLL is in low power mode +0x1 (TRUE): PLL is enabled + 3 + 1 + read-write + + + SD_CLK_EN + SD/eMMC Clock Enable +This bit stops the SDCLK or RCLK when set to 0. +The SDCLK/RCLK Frequency Select bit can be changed when this bit is set to 0. +The value is reflected on the clk2card_on pin. +Values: +0x0 (FALSE): Disable providing SDCLK/RCLK +0x1 (TRUE): Enable providing SDCLK/RCLK + 2 + 1 + read-write + + + INTERNAL_CLK_STABLE + Internal Clock Stable +This bit enables the Host Driver to check the clock stability twice after the Internal Clock Enable bit is set and after the PLL Enable bit is set. +This bit reflects the synchronized value of the intclk_stable signal after the Internal Clock Enable bit is set to 1, +and also reflects the synchronized value of the card_clk_stable signal after the PLL Enable bit is set to 1. +Values: +0x0 (FALSE): Not Ready +0x1 (TRUE): Ready + 1 + 1 + read-write + + + INTERNAL_CLK_EN + Internal Clock Enable +This bit is set to 0 when the Host Driver is not using the Host Controller or the Host Controller awaits a wakeup interrupt. +The Host Controller must stop its internal clock to enter a very low power state. +However, registers can still be read and written to. The value is reflected on the intclk_en signal. +Note: If this bit is not used to control the internal clock (base clock and master clock), it is recommended to set this bit to '1' . +Values: +0x0 (FALSE): Stop +0x1 (TRUE): Oscillate + 0 + 1 + read-write + + + + + INT_STAT + No description available + 0x30 + 32 + 0x00000000 + 0x1FFFF1FF + + + BOOT_ACK_ERR + Boot Acknowledgment Error +This bit is set when there is a timeout for boot acknowledgement or when detecting boot ack status having a value other than 010. This is applicable only when boot acknowledgement is expected in eMMC mode. +In SD/UHS-II mode, this bit is irrelevant. + 28 + 1 + read-write + + + RESP_ERR + Response Error +Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. +If Response Error Check Enable is set to 1 in the Transfer Mode register, Host Controller Checks R1 or R5 response. If an error is detected in a response, this bit is set to 1.This is applicable in SD/eMMC mode. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 27 + 1 + read-write + + + TUNING_ERR + Tuning Error +This bit is set when an unrecoverable error is detected in a tuning circuit except during the tuning procedure +(occurrence of an error during tuning procedure is indicated by Sampling Clock Select in the Host Control 2 register). +By detecting Tuning Error, Host Driver needs to abort a command executing and perform tuning. +To reset tuning circuit, Sampling Clock Select is set to 0 before executing tuning procedure. +The Tuning Error is higher priority than the other error interrupts generated during data transfer. +By detecting Tuning Error, the Host Driver must discard data transferred by a current read/write command and retry data transfer after the Host Controller retrieved from the tuning circuit error. +This is applicable in SD/eMMC mode. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 26 + 1 + read-write + + + ADMA_ERR + ADMA Error +This bit is set when the Host Controller detects error during ADMA-based data transfer. The error could be due to following reasons: +Error response received from System bus (Master I/F) +ADMA3,ADMA2 Descriptors invalid +CQE Task or Transfer descriptors invalid +When the error occurs, the state of the ADMA is saved in the ADMA Error Status register. +In eMMC CQE mode: +The Host Controller generates this Interrupt when it detects an invalid descriptor data (Valid=0) at the ST_FDS state. +ADMA Error State in the ADMA Error Status indicates that an error has occurred in ST_FDS state. +The Host Driver may find that Valid bit is not set at the error descriptor. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 25 + 1 + read-write + + + AUTO_CMD_ERR + Auto CMD Error +This error status is used by Auto CMD12 and Auto CMD23 in SD/eMMC mode. +This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1. +D07 is effective in case of Auto CMD12. Auto CMD Error Status register is valid while this bit is set to 1 and may be cleared by clearing of this bit. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 24 + 1 + read-write + + + CUR_LMT_ERR + Current Limit Error +By setting the SD Bus Power bit in the Power Control register, the Host Controller is requested to supply power for the SD Bus. +If the Host Controller supports the Current Limit function, it can be protected from an illegal card by stopping power supply to the card in which case this bit indicates a failure status. +A reading of 1 for this bit means that the Host Controller is not supplying power to the SD card due to some failure. +A reading of 0 for this bit means that the Host Controller is supplying power and no error has occurred. +The Host Controller may require some sampling time to detect the current limit. +SDXC Host Controller does not support this function, this bit is always set to 0. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Power Fail + 23 + 1 + read-write + + + DATA_END_BIT_ERR + Data End Bit Error +This error occurs in SD/eMMC mode either when detecting 0 at the end bit position of read data that uses the DAT line or at the end bit position of the CRC status. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 22 + 1 + read-write + + + DATA_CRC_ERR + Data CRC Error +This error occurs in SD/eMMC mode when detecting CRC error when transferring read data which uses the DAT line, +when detecting the Write CRC status having a value of other than 010 or when write CRC status timeout. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 21 + 1 + read-write + + + DATA_TOUT_ERR + Data Timeout Error +This bit is set in SD/eMMC mode when detecting one of the following timeout conditions: +Busy timeout for R1b, R5b type +Busy timeout after Write CRC status +Write CRC Status timeout +Read Data timeout +Values: +0x0 (FALSE): No error +0x1 (TRUE): Time out + 20 + 1 + read-write + + + CMD_IDX_ERR + Command Index Error +This bit is set if a Command Index error occurs in the command respons in SD/eMMC mode. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 19 + 1 + read-write + + + CMD_END_BIT_ERR + Command End Bit Error +This bit is set when detecting that the end bit of a command response is 0 in SD/eMMC mode. +Values: +0x0 (FALSE): No error +0x1 (TRUE): End Bit error generated + 18 + 1 + read-write + + + CMD_CRC_ERR + Command CRC Error +Command CRC Error is generated in SD/eMMC mode for following two cases. +If a response is returned and the Command Timeout Error is set to 0 (indicating no timeout), this bit is set to 1 when detecting a CRC error in the command response. +The Host Controller detects a CMD line conflict by monitoring the CMD line when a command is issued. +If the Host Controller drives the CMD line to 1 level, +but detects 0 level on the CMD line at the next SD clock edge, then the Host Controller aborts the command (stop driving CMD line) and set this bit to 1. +The Command Timeout Error is also set to 1 to distinguish a CMD line conflict. +Values: +0x0 (FALSE): No error +0x1 (TRUE): CRC error generated + 17 + 1 + read-write + + + CMD_TOUT_ERR + Command Timeout Error +In SD/eMMC Mode,this bit is set only if no response is returned within 64 SD clock cycles from the end bit of the command. +If the Host Controller detects a CMD line conflict, along with Command CRC Error bit, this bit is set to 1, without waiting for 64 SD/eMMC card clock cycles. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Time out + 16 + 1 + read-write + + + ERR_INTERRUPT + Error Interrupt +If any of the bits in the Error Interrupt Status register are set, then this bit is set. +Values: +0x0 (FALSE): No Error +0x1 (TRUE): Error + 15 + 1 + read-only + + + CQE_EVENT + Command Queuing Event +This status is set if Command Queuing/Crypto related event has occurred in eMMC/SD mode. Read CQHCI's CQIS/CRNQIS register for more details. +Values: +0x0 (FALSE): No Event +0x1 (TRUE): Command Queuing Event is detected + 14 + 1 + read-write + + + FX_EVENT + FX Event +This status is set when R[14] of response register is set to 1 and Response Type R1/R5 is set to 0 in Transfer Mode register. This interrupt is used with response check function. +Values: +0x0 (FALSE): No Event +0x1 (TRUE): FX Event is detected + 13 + 1 + read-only + + + RE_TUNE_EVENT + Re-tuning Event +This bit is set if the Re-Tuning Request changes from 0 to 1. Re-Tuning request is not supported. + 12 + 1 + read-only + + + CARD_INTERRUPT + Card Interrupt +This bit reflects the synchronized value of: +DAT[1] Interrupt Input for SD Mode +DAT[2] Interrupt Input for UHS-II Mode +Values: +0x0 (FALSE): No Card Interrupt +0x1 (TRUE): Generate Card Interrupt + 8 + 1 + read-only + + + CARD_REMOVAL + Card Removal +This bit is set if the Card Inserted in the Present State register changes from 1 to 0. +Values: +0x0 (FALSE): Card state stable or Debouncing +0x1 (TRUE): Card Removed + 7 + 1 + read-write + + + CARD_INSERTION + Card Insertion +This bit is set if the Card Inserted in the Present State register changes from 0 to 1. +Values: +0x0 (FALSE): Card state stable or Debouncing +0x1 (TRUE): Card Inserted + 6 + 1 + read-write + + + BUF_RD_READY + Buffer Read Ready +This bit is set if the Buffer Read Enable changes from 0 to 1. +Values: +0x0 (FALSE): Not ready to read buffer +0x1 (TRUE): Ready to read buffer + 5 + 1 + read-write + + + BUF_WR_READY + Buffer Write Ready +This bit is set if the Buffer Write Enable changes from 0 to 1. +Values: +0x0 (FALSE): Not ready to write buffer +0x1 (TRUE): Ready to write buffer + 4 + 1 + read-write + + + DMA_INTERRUPT + DMA Interrupt +This bit is set if the Host Controller detects the SDMA Buffer Boundary during transfer. +In case of ADMA, by setting the Int field in the descriptor table, the Host controller generates this interrupt. +This interrupt is not generated after a Transfer Complete. +Values: +0x0 (FALSE): No DMA Interrupt +0x1 (TRUE): DMA Interrupt is generated + 3 + 1 + read-write + + + BGAP_EVENT + Block Gap Event +This bit is set when both read/write transaction is stopped at block gap due to a Stop at Block Gap Request. +Values: +0x0 (FALSE): No Block Gap Event +0x1 (TRUE): Transaction stopped at block gap + 2 + 1 + read-write + + + XFER_COMPLETE + Transfer Complete +This bit is set when a read/write transfer and a command with status busy is completed. +Values: +0x0 (FALSE): Not complete +0x1 (TRUE): Command execution is completed + 1 + 1 + read-write + + + CMD_COMPLETE + Command Complete +In an SD/eMMC Mode, this bit is set when the end bit of a response except for Auto CMD12 and Auto CMD23. +This interrupt is not generated when the Response Interrupt Disable in Transfer Mode Register is set to 1. +Values: +0x0 (FALSE): No command complete +0x1 (TRUE): Command Complete + 0 + 1 + read-write + + + + + INT_STAT_EN + No description available + 0x34 + 32 + 0x00000000 + 0x1FFF71FF + + + BOOT_ACK_ERR_STAT_EN + Boot Acknowledgment Error (eMMC Mode only) +Setting this bit to 1 enables setting of Boot Acknowledgment Error in Error Interrupt Status register (INT_STAT). +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 28 + 1 + read-write + + + RESP_ERR_STAT_EN + Response Error Status Enable (SD Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 27 + 1 + read-write + + + TUNING_ERR_STAT_EN + Tuning Error Status Enable (UHS-I Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 26 + 1 + read-write + + + ADMA_ERR_STAT_EN + ADMA Error Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 25 + 1 + read-write + + + AUTO_CMD_ERR_STAT_EN + Auto CMD Error Status Enable (SD/eMMC Mode only). +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 24 + 1 + read-write + + + CUR_LMT_ERR_STAT_EN + Current Limit Error Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 23 + 1 + read-write + + + DATA_END_BIT_ERR_STAT_EN + Data End Bit Error Status Enable (SD/eMMC Mode only). +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 22 + 1 + read-write + + + DATA_CRC_ERR_STAT_EN + Data CRC Error Status Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 21 + 1 + read-write + + + DATA_TOUT_ERR_STAT_EN + Data Timeout Error Status Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 20 + 1 + read-write + + + CMD_IDX_ERR_STAT_EN + Command Index Error Status Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 19 + 1 + read-write + + + CMD_END_BIT_ERR_STAT_EN + Command End Bit Error Status Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 18 + 1 + read-write + + + CMD_CRC_ERR_STAT_EN + Command CRC Error Status Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 17 + 1 + read-write + + + CMD_TOUT_ERR_STAT_EN + Command Timeout Error Status Enable (SD/eMMC Mode only). +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 16 + 1 + read-write + + + CQE_EVENT_STAT_EN + CQE Event Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 14 + 1 + read-write + + + FX_EVENT_STAT_EN + FX Event Status Enable +This bit is added from Version 4.10. +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 13 + 1 + read-write + + + RE_TUNE_EVENT_STAT_EN + Re-Tuning Event (UHS-I only) Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 12 + 1 + read-write + + + CARD_INTERRUPT_STAT_EN + Card Interrupt Status Enable +If this bit is set to 0, the Host Controller clears the interrupt request to the System. +The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. +The Host Driver may clear the Card Interrupt Status Enable before servicing the Card Interrupt and may set this bit again after all interrupt requests from the card are cleared to prevent inadvertent interrupts. +By setting this bit to 0, interrupt input must be masked by implementation so that the interrupt input is not affected by external signal in any state (for example, floating). +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 8 + 1 + read-write + + + CARD_REMOVAL_STAT_EN + Card Removal Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 7 + 1 + read-write + + + CARD_INSERTION_STAT_EN + Card Insertion Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 6 + 1 + read-write + + + BUF_RD_READY_STAT_EN + Buffer Read Ready Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 5 + 1 + read-write + + + BUF_WR_READY_STAT_EN + Buffer Write Ready Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 4 + 1 + read-write + + + DMA_INTERRUPT_STAT_EN + DMA Interrupt Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 3 + 1 + read-write + + + BGAP_EVENT_STAT_EN + Block Gap Event Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 2 + 1 + read-write + + + XFER_COMPLETE_STAT_EN + Transfer Complete Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 1 + 1 + read-write + + + CMD_COMPLETE_STAT_EN + Command Complete Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 0 + 1 + read-write + + + + + INT_SIGNAL_EN + No description available + 0x38 + 32 + 0x00000000 + 0x1FFF71FF + + + BOOT_ACK_ERR_SIGNAL_EN + Boot Acknowledgment Error (eMMC Mode only). +Setting this bit to 1 enables generating interrupt signal when Boot Acknowledgment Error in Error Interrupt Status register is set. +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 28 + 1 + read-write + + + RESP_ERR_SIGNAL_EN + Response Error Signal Enable (SD Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 27 + 1 + read-write + + + TUNING_ERR_SIGNAL_EN + Tuning Error Signal Enable (UHS-I Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 26 + 1 + read-write + + + ADMA_ERR_SIGNAL_EN + ADMA Error Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 25 + 1 + read-write + + + AUTO_CMD_ERR_SIGNAL_EN + Auto CMD Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 24 + 1 + read-write + + + CUR_LMT_ERR_SIGNAL_EN + Current Limit Error Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 23 + 1 + read-write + + + DATA_END_BIT_ERR_SIGNAL_EN + Data End Bit Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 22 + 1 + read-write + + + DATA_CRC_ERR_SIGNAL_EN + Data CRC Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 21 + 1 + read-write + + + DATA_TOUT_ERR_SIGNAL_EN + Data Timeout Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 20 + 1 + read-write + + + CMD_IDX_ERR_SIGNAL_EN + Command Index Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 19 + 1 + read-write + + + CMD_END_BIT_ERR_SIGNAL_EN + Command End Bit Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 18 + 1 + read-write + + + CMD_CRC_ERR_SIGNAL_EN + Command CRC Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 17 + 1 + read-write + + + CMD_TOUT_ERR_SIGNAL_EN + Command Timeout Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 16 + 1 + read-write + + + CQE_EVENT_SIGNAL_EN + Command Queuing Engine Event Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 14 + 1 + read-write + + + FX_EVENT_SIGNAL_EN + FX Event Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 13 + 1 + read-write + + + RE_TUNE_EVENT_SIGNAL_EN + Re-Tuning Event (UHS-I only) Signal Enable. +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 12 + 1 + read-write + + + CARD_INTERRUPT_SIGNAL_EN + Card Interrupt Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 8 + 1 + read-write + + + CARD_REMOVAL_SIGNAL_EN + Card Removal Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 7 + 1 + read-write + + + CARD_INSERTION_SIGNAL_EN + Card Insertion Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 6 + 1 + read-write + + + BUF_RD_READY_SIGNAL_EN + Buffer Read Ready Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 5 + 1 + read-write + + + BUF_WR_READY_SIGNAL_EN + Buffer Write Ready Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 4 + 1 + read-write + + + DMA_INTERRUPT_SIGNAL_EN + DMA Interrupt Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 3 + 1 + read-write + + + BGAP_EVENT_SIGNAL_EN + Block Gap Event Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 2 + 1 + read-write + + + XFER_COMPLETE_SIGNAL_EN + Transfer Complete Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 1 + 1 + read-write + + + CMD_COMPLETE_SIGNAL_EN + Command Complete Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 0 + 1 + read-write + + + + + AC_HOST_CTRL + No description available + 0x3c + 32 + 0x00000000 + 0xDCCF00BF + + + PRESET_VAL_ENABLE + Preset Value Enable +This bit enables automatic selection of SDCLK frequency and Driver strength Preset Value registers. +When Preset Value Enable is set, SDCLK frequency generation (Frequency Select and Clock Generator Select) and the driver strength selection are performed by the controller. +These values are selected from set of Preset Value registers based on selected speed mode. +Values: +0x0 (FALSE): SDCLK and Driver Strength are controlled by Host Driver +0x1 (TRUE): Automatic Selection by Preset Value are Enabled + 31 + 1 + read-write + + + ASYNC_INT_ENABLE + Asynchronous Interrupt Enable +This bit can be set if a card supports asynchronous interrupts and Asynchronous Interrupt Support is set to 1 in the Capabilities register. +Values: +0x0 (FALSE): Disabled +0x1 (TRUE): Enabled + 30 + 1 + read-write + + + HOST_VER4_ENABLE + Host Version 4 Enable +This bit selects either Version 3.00 compatible mode or Version 4 mode. +Functions of following fields are modified for Host Version 4 mode: +SDMA Address: SDMA uses ADMA System Address (05Fh-058h) instead of SDMA System Address register (003h-000h) +ADMA2/ADMA3 selection: ADMA3 is selected by DMA select in Host Control 1 register +64-bit ADMA Descriptor Size: 128-bit descriptor is used instead of 96-bit descriptor when 64-bit Addressing is set to 1 +Selection of 32-bit/64-bit System Addressing: Either 32-bit or 64-bit system addressing is selected by 64-bit Addressing bit in this register +32-bit Block Count: SDMA System Address register (003h-000h) is modified to 32-bit Block Count register +Note: It is recommended not to program ADMA3 Integrated Descriptor Address registers, +UHS-II registers and Command Queuing registers (if applicable) while operating in Host version less than 4 mode (Host Version 4 Enable = 0). +Values: +0x0 (FALSE): Version 3.00 compatible mode +0x1 (TRUE): Version 4 mode + 28 + 1 + read-write + + + CMD23_ENABLE + CMD23 Enable +If the card supports CMD23, this bit is set to 1. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3 data transfer. +Values: +0x0 (FALSE): Auto CMD23 is disabled +0x1 (TRUE): Auto CMD23 is enabled + 27 + 1 + read-write + + + ADMA2_LEN_MODE + ADMA2 Length Mode +This bit selects ADMA2 Length mode to be either 16-bit or 26-bit. +Values: +0x0 (FALSE): 16-bit Data Length Mode +0x1 (TRUE): 26-bit Data Length Mode + 26 + 1 + read-write + + + SAMPLE_CLK_SEL + Sampling Clock Select +This bit is used by the Host Controller to select the sampling clock in SD/eMMC mode to receive CMD and DAT. +This bit is set by the tuning procedure and is valid after the completion of tuning (when Execute Tuning is cleared). +Setting this bit to 1 means that tuning is completed successfully and setting this bit to 0 means that tuning has failed. +The value is reflected on the sample_cclk_sel pin. +Values: +0x0 (FALSE): Fixed clock is used to sample data +0x1 (TRUE): Tuned clock is used to sample data + 23 + 1 + read-write + + + EXEC_TUNING + Execute Tuning +This bit is set to 1 to start the tuning procedure in UHS-I/eMMC speed modes and this bit is automatically cleared when tuning procedure is completed. +Values: +0x0 (FALSE): Not Tuned or Tuning completed +0x1 (TRUE): Execute Tuning + 22 + 1 + read-write + + + SIGNALING_EN + 1.8V Signaling Enable +This bit controls voltage regulator for I/O cell in UHS-I/eMMC speed modes. +Setting this bit from 0 to 1 starts changing the signal voltage from 3.3V to 1.8V. +Host Controller clears this bit if switching to 1.8 signaling fails. The value is reflected on the uhs1_swvolt_en pin. +Note: This bit must be set for all UHS-I speed modes (SDR12/SDR25/SDR50/SDR104/DDR50). +Values: +0x0 (V_3_3): 3.3V Signalling +0x1 (V_1_8): 1.8V Signalling + 19 + 1 + read-write + + + UHS_MODE_SEL + UHS Mode/eMMC Speed Mode Select +These bits are used to select UHS mode in the SD mode of operation. In eMMC mode, these bits are used to select eMMC Speed mode. +UHS Mode (SD/UHS-II mode only): +0x0 (SDR12): SDR12/Legacy +0x1 (SDR25): SDR25/High Speed SDR +0x2 (SDR50): SDR50 +0x3 (SDR104): SDR104/HS200 +0x4 (DDR50): DDR50/High Speed DDR +0x5 (RSVD5): Reserved +0x6 (RSVD6): Reserved +0x7 (UHS2): UHS-II/HS400 +eMMC Speed Mode (eMMC mode only): +0x0: Legacy +0x1: High Speed SDR +0x2: Reserved +0x3: HS200 +0x4: High Speed DDR +0x5: Reserved +0x6: Reserved +0x7: HS400 + 16 + 3 + read-write + + + CMD_NOT_ISSUED_AUTO_CMD12 + Command Not Issued By Auto CMD12 Error +If this bit is set to 1, CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register. +This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. +Values: +0x1 (TRUE): Not Issued +0x0 (FALSE): No Error + 7 + 1 + read-only + + + AUTO_CMD_RESP_ERR + Auto CMD Response Error +This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or CMD13. +This status is ignored if any bit between D00 to D04 is set to 1. +Values: +0x1 (TRUE): Error +0x0 (FALSE): No Error + 5 + 1 + read-only + + + AUTO_CMD_IDX_ERR + Auto CMD Index Error +This bit is set if the command index error occurs in response to a command. +Values: +0x1 (TRUE): Error +0x0 (FALSE): No Error + 4 + 1 + read-only + + + AUTO_CMD_EBIT_ERR + Auto CMD End Bit Error +This bit is set when detecting that the end bit of command response is 0. +Values: +0x1 (TRUE): End Bit Error Generated +0x0 (FALSE): No Error + 3 + 1 + read-only + + + AUTO_CMD_CRC_ERR + Auto CMD CRC Error +This bit is set when detecting a CRC error in the command response. +Values: +0x1 (TRUE): CRC Error Generated +0x0 (FALSE): No Error + 2 + 1 + read-only + + + AUTO_CMD_TOUT_ERR + Auto CMD Timeout Error +This bit is set if no response is returned with 64 SDCLK cycles from the end bit of the command. +If this bit is set to 1, error status bits (D04-D01) are meaningless. +Values: +0x1 (TRUE): Time out +0x0 (FALSE): No Error + 1 + 1 + read-only + + + AUTO_CMD12_NOT_EXEC + Auto CMD12 Not Executed +If multiple memory block data transfer is not started due to a command error, this bit is not set because it is not necessary to issue an Auto CMD12. +Setting this bit to 1 means that the Host Controller cannot issue Auto CMD12 to stop multiple memory block data transfer, due to some error. + If this bit is set to 1, error status bits (D04-D01) is meaningless. +This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. +Values: +0x1 (TRUE): Not Executed +0x0 (FALSE): Executed + 0 + 1 + read-only + + + + + CAPABILITIES1 + No description available + 0x40 + 32 + 0x00000000 + 0xE7EFFFBF + + + SLOT_TYPE_R + Slot Type +These bits indicate usage of a slot by a specific Host System. +Values: +0x0 (REMOVABLE_SLOT): Removable Card Slot +0x1 (EMBEDDED_SLOT): Embedded Slot for one Device +0x2 (SHARED_SLOT): Shared Bus Slot (SD mode) +0x3 (UHS2_EMBEDDED_SLOT): UHS-II Multiple Embedded Devices + 30 + 2 + read-only + + + ASYNC_INT_SUPPORT + Asynchronous Interrupt Support (SD Mode only) +Values: +0x0 (FALSE): Asynchronous Interrupt Not Supported +0x1 (TRUE): Asynchronous Interrupt Supported + 29 + 1 + read-only + + + VOLT_18 + Voltage Support for 1.8V +Values: +0x0 (FALSE): 1.8V Not Supported +0x1 (TRUE): 1.8V Supported + 26 + 1 + read-only + + + VOLT_30 + Voltage Support for SD 3.0V or Embedded 1.2V +Values: +0x0 (FALSE): SD 3.0V or Embedded 1.2V Not Supported +0x1 (TRUE): SD 3.0V or Embedded Supported + 25 + 1 + read-only + + + VOLT_33 + Voltage Support for 3.3V +Values: +0x0 (FALSE): 3.3V Not Supported +0x1 (TRUE): 3.3V Supported + 24 + 1 + read-only + + + SUS_RES_SUPPORT + Suspense/Resume Support +This bit indicates whether the Host Controller supports Suspend/Resume functionality. +If this bit is 0, the Host Driver does not issue either Suspend or Resume commands because the Suspend and Resume mechanism is not supported. +Values: +0x0 (FALSE): Not Supported +0x1 (TRUE): Supported + 23 + 1 + read-only + + + SDMA_SUPPORT + SDMA Support +This bit indicates whether the Host Controller is capable of using SDMA to transfer data between the system memory and the Host Controller directly. +Values: +0x0 (FALSE): SDMA not Supported +0x1 (TRUE): SDMA Supported + 22 + 1 + read-only + + + HIGH_SPEED_SUPPORT + High Speed Support +This bit indicates whether the Host Controller and the Host System supports High Speed mode and they can supply the SD Clock frequency from 25 MHz to 50 MHz. +Values: +0x0 (FALSE): High Speed not Supported +0x1 (TRUE): High Speed Supported + 21 + 1 + read-only + + + ADMA2_SUPPORT + ADMA2 Support +This bit indicates whether the Host Controller is capable of using ADMA2. +Values: +0x0 (FALSE): ADMA2 not Supported +0x1 (TRUE): ADMA2 Supported + 19 + 1 + read-only + + + EMBEDDED_8_BIT + 8-bit Support for Embedded Device +This bit indicates whether the Host Controller is capable of using an 8-bit bus width mode. This bit is not effective when the Slot Type is set to 10b. +Values: +0x0 (FALSE): 8-bit Bus Width not Supported +0x1 (TRUE): 8-bit Bus Width Supported + 18 + 1 + read-only + + + MAX_BLK_LEN + Maximum Block Length +This bit indicates the maximum block size that the Host driver can read and write to the buffer in the Host Controller. +The buffer transfers this block size without wait cycles. The transfer block length is always 512 bytes for the SD Memory irrespective of this bit +Values: +0x0 (ZERO): 512 Byte +0x1 (ONE): 1024 Byte +0x2 (TWO): 2048 Byte +0x3 (THREE): Reserved + 16 + 2 + read-only + + + BASE_CLK_FREQ + Base Clock Frequency for SD clock +These bits indicate the base (maximum) clock frequency for the SD Clock. The definition of these bits depend on the Host Controller Version. +6-Bit Base Clock Frequency: This mode is supported by the Host Controller version 1.00 and 2.00. +The upper 2 bits are not effective and are always 0. The unit values are 1 MHz. The supported clock range is 10 MHz to 63 MHz. +-0x00 : Get information through another method +-0x01 : 1 MHz +-0x02 : 2 MHz +-............. +-0x3F : 63 MHz +-0x40-0xFF : Not Supported +8-Bit Base Clock Frequency: This mode is supported by the Host Controller version 3.00. The unit values are 1 MHz. The supported clock range is 10 MHz to 255 MHz. +-0x00 : Get information through another method +-0x01 : 1 MHz +-0x02 : 2 MHz +-............ +-0xFF : 255 MHz +If the frequency is 16.5 MHz, the larger value is set to 0001001b (17 MHz) because the Host Driver uses this value to calculate the clock divider value and it does not exceed the upper limit of the SD Clock frequency. +If these bits are all 0, the Host system has to get information using a different method. + 8 + 8 + read-only + + + TOUT_CLK_UNIT + Timeout Clock Unit +This bit shows the unit of base clock frequency used to detect Data TImeout Error. +Values: +0x0 (KHZ): KHz +0x1 (MHZ): MHz + 7 + 1 + read-only + + + TOUT_CLK_FREQ + Timeout Clock Frequency +This bit shows the base clock frequency used to detect Data Timeout Error. The Timeout Clock unit defines the unit of timeout clock frequency. It can be KHz or MHz. +0x00 : Get information through another method +0x01 : 1KHz / 1MHz +0x02 : 2KHz / 2MHz +0x03 : 3KHz / 3MHz + ........... +0x3F : 63KHz / 63MHz + 0 + 6 + read-only + + + + + CAPABILITIES2 + No description available + 0x44 + 32 + 0x00000000 + 0x18FFEF7F + + + VDD2_18V_SUPPORT + 1.8V VDD2 Support +This bit indicates support of VDD2 for the Host System. +0x0 (FALSE): 1.8V VDD2 is not Supported +0x1 (TRUE): 1.8V VDD2 is Supported + 28 + 1 + read-only + + + ADMA3_SUPPORT + ADMA3 Support +This bit indicates whether the Host Controller is capable of using ADMA3. +Values: +0x0 (FALSE): ADMA3 not Supported +0x1 (TRUE): ADMA3 Supported + 27 + 1 + read-only + + + CLK_MUL + Clock Multiplier +These bits indicate the clock multiplier of the programmable clock generator. Setting these bits to 0 means that the Host Controller does not support a programmable clock generator. +0x0: Clock Multiplier is not Supported +0x1: Clock Multiplier M = 2 +0x2: Clock Multiplier M = 3 + ......... +0xFF: Clock Multiplier M = 256 + 16 + 8 + read-only + + + RE_TUNING_MODES + Re-Tuning Modes (UHS-I only) +These bits select the re-tuning method and limit the maximum data length. +Values: +0x0 (MODE1): Timer +0x1 (MODE2): Timer and Re-Tuning Request (Not supported) +0x2 (MODE3): Auto Re-Tuning (for transfer) +0x3 (RSVD_MODE): Reserved + 14 + 2 + read-only + + + USE_TUNING_SDR50 + Use Tuning for SDR50 (UHS-I only) +Values: +0x0 (ZERO): SDR50 does not require tuning +0x1 (ONE): SDR50 requires tuning + 13 + 1 + read-only + + + RETUNE_CNT + Timer Count for Re-Tuning (UHS-I only) +0x0: Re-Tuning Timer disabled +0x1: 1 seconds +0x2: 2 seconds +0x3: 4 seconds + ........ +0xB: 1024 seconds +0xC: Reserved +0xD: Reserved +0xE: Reserved +0xF: Get information from other source + 8 + 4 + read-only + + + DRV_TYPED + Driver Type D Support (UHS-I only) +This bit indicates support of Driver Type D for 1.8 Signaling. +Values: +0x0 (FALSE): Driver Type D is not supported +0x1 (TRUE): Driver Type D is supported + 6 + 1 + read-only + + + DRV_TYPEC + Driver Type C Support (UHS-I only) +This bit indicates support of Driver Type C for 1.8 Signaling. +Values: +0x0 (FALSE): Driver Type C is not supported +0x1 (TRUE): Driver Type C is supported + 5 + 1 + read-only + + + DRV_TYPEA + Driver Type A Support (UHS-I only) +This bit indicates support of Driver Type A for 1.8 Signaling. +Values: +0x0 (FALSE): Driver Type A is not supported +0x1 (TRUE): Driver Type A is supported + 4 + 1 + read-only + + + UHS2_SUPPORT + UHS-II Support (UHS-II only) +This bit indicates whether Host Controller supports UHS-II. +Values: +0x0 (FALSE): UHS-II is not supported +0x1 (TRUE): UHS-II is supported + 3 + 1 + read-only + + + DDR50_SUPPORT + DDR50 Support (UHS-I only) +Values: +0x0 (FALSE): DDR50 is not supported +0x1 (TRUE): DDR50 is supported + 2 + 1 + read-only + + + SDR104_SUPPORT + SDR104 Support (UHS-I only) +This bit mentions that SDR104 requires tuning. +Values: +0x0 (FALSE): SDR104 is not supported +0x1 (TRUE): SDR104 is supported + 1 + 1 + read-only + + + SDR50_SUPPORT + SDR50 Support (UHS-I only) +This bit indicates that SDR50 is supported. The bit 13 (USE_TUNING_SDR50) indicates whether SDR50 requires tuning or not. +Values: +0x0 (FALSE): SDR50 is not supported +0x1 (TRUE): SDR50 is supported + 0 + 1 + read-only + + + + + CURR_CAPABILITIES1 + No description available + 0x48 + 32 + 0x00000000 + 0x00FFFFFF + + + MAX_CUR_18V + Maximum Current for 1.8V +This bit specifies the Maximum Current for 1.8V VDD1 power supply for the card. +0: Get information through another method +1: 4mA +2: 8mA +3: 13mA +....... +255: 1020mA + 16 + 8 + read-only + + + MAX_CUR_30V + Maximum Current for 3.0V +This bit specifies the Maximum Current for 3.0V VDD1 power supply for the card. +0: Get information through another method +1: 4mA +2: 8mA +3: 13mA +....... +255: 1020mA + 8 + 8 + read-only + + + MAX_CUR_33V + Maximum Current for 3.3V +This bit specifies the Maximum Current for 3.3V VDD1 power supply for the card. +0: Get information through another method +1: 4mA +2: 8mA +3: 13mA +....... +255: 1020mA + 0 + 8 + read-only + + + + + CURR_CAPABILITIES2 + No description available + 0x4c + 32 + 0x00000000 + 0x000000FF + + + MAX_CUR_VDD2_18V + Maximum Current for 1.8V VDD2 +This bit specifies the Maximum Current for 1.8V VDD2 power supply for the UHS-II card. +0: Get information through another method +1: 4mA +2: 8mA +3: 13mA +....... +255: 1020mA + 0 + 8 + read-only + + + + + FORCE_EVENT + No description available + 0x50 + 32 + 0x00000000 + 0x1FFF00BF + + + FORCE_BOOT_ACK_ERR + Force Event for Boot Ack error +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Boot ack Error Status is set + 28 + 1 + write-only + + + FORCE_RESP_ERR + Force Event for Response Error (SD Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Response Error Status is set + 27 + 1 + write-only + + + FORCE_TUNING_ERR + Force Event for Tuning Error (UHS-I Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Tuning Error Status is set + 26 + 1 + write-only + + + FORCE_ADMA_ERR + Force Event for ADMA Error +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): ADMA Error Status is set + 25 + 1 + write-only + + + FORCE_AUTO_CMD_ERR + Force Event for Auto CMD Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Auto CMD Error Status is set + 24 + 1 + write-only + + + FORCE_CUR_LMT_ERR + Force Event for Current Limit Error +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Current Limit Error Status is set + 23 + 1 + write-only + + + FORCE_DATA_END_BIT_ERR + Force Event for Data End Bit Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Data End Bit Error Status is set + 22 + 1 + write-only + + + FORCE_DATA_CRC_ERR + Force Event for Data CRC Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Data CRC Error Status is set + 21 + 1 + write-only + + + FORCE_DATA_TOUT_ERR + Force Event for Data Timeout Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Data Timeout Error Status is set + 20 + 1 + write-only + + + FORCE_CMD_IDX_ERR + Force Event for Command Index Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Command Index Error Status is set + 19 + 1 + write-only + + + FORCE_CMD_END_BIT_ERR + Force Event for Command End Bit Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Command End Bit Error Status is set + 18 + 1 + write-only + + + FORCE_CMD_CRC_ERR + Force Event for Command CRC Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Command CRC Error Status is set + 17 + 1 + write-only + + + FORCE_CMD_TOUT_ERR + Force Event for Command Timeout Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Command Timeout Error Status is set + 16 + 1 + write-only + + + FORCE_CMD_NOT_ISSUED_AUTO_CMD12 + Force Event for Command Not Issued By Auto CMD12 Error +Values: +0x1 (TRUE): Command Not Issued By Auto CMD12 Error Status is set +0x0 (FALSE): Not Affected + 7 + 1 + write-only + + + FORCE_AUTO_CMD_RESP_ERR + Force Event for Auto CMD Response Error +Values: +0x1 (TRUE): Auto CMD Response Error Status is set +0x0 (FALSE): Not Affected + 5 + 1 + write-only + + + FORCE_AUTO_CMD_IDX_ERR + Force Event for Auto CMD Index Error +Values: +0x1 (TRUE): Auto CMD Index Error Status is set +0x0 (FALSE): Not Affected + 4 + 1 + write-only + + + FORCE_AUTO_CMD_EBIT_ERR + Force Event for Auto CMD End Bit Error +Values: +0x1 (TRUE): Auto CMD End Bit Error Status is set +0x0 (FALSE): Not Affected + 3 + 1 + write-only + + + FORCE_AUTO_CMD_CRC_ERR + Force Event for Auto CMD CRC Error +Values: +0x1 (TRUE): Auto CMD CRC Error Status is set +0x0 (FALSE): Not Affected + 2 + 1 + write-only + + + FORCE_AUTO_CMD_TOUT_ERR + Force Event for Auto CMD Timeout Error +Values: +0x1 (TRUE): Auto CMD Timeout Error Status is set +0x0 (FALSE): Not Affected + 1 + 1 + write-only + + + FORCE_AUTO_CMD12_NOT_EXEC + Force Event for Auto CMD12 Not Executed +Values: +0x1 (TRUE): Auto CMD12 Not Executed Status is set +0x0 (FALSE): Not Affected + 0 + 1 + write-only + + + + + ADMA_ERR_STAT + No description available + 0x54 + 32 + 0x00000000 + 0x00000007 + + + ADMA_LEN_ERR + ADMA Length Mismatch Error States +This error occurs in the following instances: +While the Block Count Enable is being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length +When the total data length cannot be divided by the block length +Values: +0x0 (NO_ERR): No Error +0x1 (ERROR): Error + 2 + 1 + read-only + + + ADMA_ERR_STATES + ADMA Error States +These bits indicate the state of ADMA when an error occurs during ADMA data transfer. +Values: +0x0 (ST_STOP): Stop DMA - SYS_ADR register points to a location next to the error descriptor +0x1 (ST_FDS): Fetch Descriptor - SYS_ADR register points to the error descriptor +0x2 (UNUSED): Never set this state +0x3 (ST_TFR): Transfer Data - SYS_ADR register points to a location next to the error descriptor + 0 + 2 + read-only + + + + + ADMA_SYS_ADDR + No description available + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADMA_SA + ADMA System Address +These bits indicate the lower 32 bits of the ADMA system address. +SDMA: If Host Version 4 Enable is set to 1, this register stores the system address of the data location +ADMA2: This register stores the byte address of the executing command of the descriptor table +ADMA3: This register is set by ADMA3. ADMA2 increments the address of this register that points to the next line, every time a Descriptor line is fetched. + 0 + 32 + read-write + + + + + 9 + 0x2 + INIT,DS,HS,SDR12,SDR25,SDR50,SDR104,DDR50,rsv8,rsv9,UHS2 + PRESET[%s] + no description available + 0x60 + 16 + 0x0000 + 0x07FF + + + CLK_GEN_SEL_VAL + Clock Generator Select Value +This bit is effective when the Host Controller supports a programmable clock generator. +Values: +0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator +0x1 (PROG): Programmable Clock Generator + 10 + 1 + read-only + + + FREQ_SEL_VAL + SDCLK/RCLK Frequency Select Value +10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. + 0 + 10 + read-only + + + + + ADMA_ID_ADDR + No description available + 0x78 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADMA_ID_ADDR + ADMA Integrated Descriptor Address +These bits indicate the lower 32-bit of the ADMA Integrated Descriptor address. +The start address of Integrated Descriptor is set to these register bits. +The ADMA3 fetches one Descriptor Address and increments these bits to indicate the next Descriptor address. + 0 + 32 + read-write + + + + + P_EMBEDDED_CNTRL + No description available + 0xe6 + 16 + 0x0000 + 0x0FFF + + + REG_OFFSET_ADDR + Offset Address of Embedded Control register. + 0 + 12 + read-only + + + + + P_VENDOR_SPECIFIC_AREA + No description available + 0xe8 + 16 + 0x0000 + 0x0FFF + + + REG_OFFSET_ADDR + Base offset Address for Vendor-Specific registers. + 0 + 12 + read-only + + + + + P_VENDOR2_SPECIFIC_AREA + No description available + 0xea + 16 + 0x0000 + 0xFFFF + + + REG_OFFSET_ADDR + Base offset Address for Command Queuing registers. + 0 + 16 + read-only + + + + + SLOT_INTR_STATUS + No description available + 0xfc + 16 + 0x0000 + 0x00FF + + + INTR_SLOT + Interrupt signal for each Slot +These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot. +A maximum of 8 slots can be defined. If one interrupt signal is associated with multiple slots, the Host Driver can identify the interrupt that is generated by reading these bits. + By a power on reset or by setting Software Reset For All bit, the interrupt signals are de-asserted and this status reads 00h. +Bit 00: Slot 1 +Bit 01: Slot 2 +Bit 02: Slot 3 +.......... +.......... +Bit 07: Slot 8 +Note: MSHC Host Controller support single card slot. This register shall always return 0. + 0 + 8 + read-only + + + + + CQVER + No description available + 0x180 + 32 + 0x00000000 + 0x00000FFF + + + EMMC_VER_MAHOR + This bit indicates the eMMC major version (1st digit left of decimal point) in BCD format. + 8 + 4 + read-only + + + EMMC_VER_MINOR + This bit indicates the eMMC minor version (1st digit right of decimal point) in BCD format. + 4 + 4 + read-only + + + EMMC_VER_SUFFIX + This bit indicates the eMMC version suffix (2nd digit right of decimal point) in BCD format. + 0 + 4 + read-only + + + + + CQCAP + No description available + 0x184 + 32 + 0x00000000 + 0x1000F3FF + + + CRYPTO_SUPPORT + Crypto Support +This bit indicates whether the Host Controller supports cryptographic operations. +Values: +0x0 (FALSE): Crypto not Supported +0x1 (TRUE): Crypto Supported + 28 + 1 + read-only + + + ITCFMUL + Internal Timer Clock Frequency Multiplier (ITCFMUL) +This field indicates the frequency of the clock used for interrupt coalescing timer and for determining the SQS +polling period. See ITCFVAL definition for details. Values 0x5 to 0xF are reserved. +Values: +0x0 (CLK_1KHz): 1KHz clock +0x1 (CLK_10KHz): 10KHz clock +0x2 (CLK_100KHz): 100KHz clock +0x3 (CLK_1MHz): 1MHz clock +0x4 (CLK_10MHz): 10MHz clock + 12 + 4 + read-only + + + ITCFVAL + Internal Timer Clock Frequency Value (ITCFVAL) +This field scales the frequency of the timer clock provided by ITCFMUL. The Final clock frequency of actual timer clock is calculated as ITCFVAL* ITCFMUL. + 0 + 10 + read-only + + + + + CQCFG + No description available + 0x188 + 32 + 0x00000000 + 0x00001101 + + + DCMD_EN + This bit indicates to the hardware whether the Task +Descriptor in slot #31 of the TDL is a data transfer descriptor or a direct-command descriptor. CQE uses this bit when a task is issued in slot #31, to determine how to decode the Task Descriptor. +Values: +0x1 (SLOT31_DCMD_ENABLE): Task descriptor in slot #31 is a DCMD Task Descriptor +0x0 (SLOT31_DCMD_DISABLE): Task descriptor in slot #31 is a data Transfer Task Descriptor + 12 + 1 + read-write + + + TASK_DESC_SIZE + Bit Value Description +This bit indicates the size of task descriptor used in host memory. This bit can only be configured when Command Queuing Enable bit is 0 (command queuing is disabled). +Values: +0x1 (TASK_DESC_128b): Task descriptor size is 128 bits +0x0 (TASK_DESC_64b): Task descriptor size is 64 bit + 8 + 1 + read-write + + + CQ_EN + No description available + 0 + 1 + read-write + + + + + CQCTL + No description available + 0x18c + 32 + 0x00000000 + 0x00000101 + + + CLR_ALL_TASKS + Clear all tasks +This bit can only be written when the controller is halted. This bit does not clear tasks in the device. The software has to use the CMDQ_TASK_MGMT command to clear device's queue. +Values: +0x1 (CLEAR_ALL_TASKS): Clears all the tasks in the controller +0x0 (NO_EFFECT): Programming 0 has no effect + 8 + 1 + read-write + + + HALT + Halt request and resume +Values: +0x1 (HALT_CQE): Software writes 1 to this bit when it wants to acquire software control over the eMMC bus and to disable CQE from issuing command on the bus. +For example, issuing a Discard Task command (CMDQ_TASK_MGMT). +When the software writes 1, CQE completes the ongoing task (if any in progress). +After the task is completed and the CQE is in idle state, CQE does not issue new commands and indicates to the software by setting this bit to 1. +The software can poll on this bit until it is set to 1 and only then send commands on the eMMC bus. +0x0 (RESUME_CQE): Software writes 0 to this bit to exit from the halt state and resume CQE activity + 0 + 1 + read-write + + + + + CQIS + No description available + 0x190 + 32 + 0x00000000 + 0x0000000F + + + TCL + Task cleared interrupt +This status bit is asserted (if CQISE.TCL_STE=1) when a task clear operation is completed by CQE. +The completed task clear operation is either an individual task clear (by writing CQTCLR) or clearing of all tasks (by writing CQCTL). +A value of 1 clears this status bit. +Values: +0x1 (SET): TCL Interrupt is set +0x0 (NOTSET): TCL Interrupt is not set + 3 + 1 + read-write + + + RED + Response error detected interrupt +This status bit is asserted (if CQISE.RED_STE=1) when a response is received with an error bit set in the device status +field. Configure the CQRMEM register to identify device status bit fields that may trigger an interrupt and that are masked. +A value of 1 clears this status bit. +Values: +0x1 (SET): RED Interrupt is set +0x0 (NOTSET): RED Interrupt is not set + 2 + 1 + read-write + + + TCC + Task complete interrupt +This status bit is asserted (if CQISE.TCC_STE=1) when at least one of the following conditions are met: +A task is completed and the INT bit is set in its Task Descriptor +Interrupt caused by Interrupt Coalescing logic due to timeout +Interrupt Coalescing logic reached the configured threshold +A value of 1 clears this status bit + 1 + 1 + read-write + + + HAC + Halt complete interrupt +This status bit is asserted (only if CQISE.HAC_STE=1) when halt bit in the CQCTL register transitions from 0 to 1 indicating that the host controller has completed its current ongoing task and has entered halt state. +A value of 1 clears this status bit. +Values: +0x1 (SET): HAC Interrupt is set +0x0 (NOTSET): HAC Interrupt is not set + 0 + 1 + read-write + + + + + CQISE + No description available + 0x194 + 32 + 0x00000000 + 0x0000000F + + + TCL_STE + Task cleared interrupt status enable +Values: +0x1 (INT_STS_ENABLE): CQIS.TCL is set when its interrupt condition is active +0x0 (INT_STS_DISABLE): CQIS.TCL is disabled + 3 + 1 + read-write + + + RED_STE + Response error detected interrupt status enable +Values: +0x1 (INT_STS_ENABLE): CQIS.RED is set when its interrupt condition is active +0x0 (INT_STS_DISABLE): CQIS.RED is disabled + 2 + 1 + read-write + + + TCC_STE + Task complete interrupt status enable +Values: +0x1 (INT_STS_ENABLE): CQIS.TCC is set when its interrupt condition is active +0x0 (INT_STS_DISABLE): CQIS.TCC is disabled + 1 + 1 + read-write + + + HAC_STE + Halt complete interrupt status enable +Values: +0x1 (INT_STS_ENABLE): CQIS.HAC is set when its interrupt condition is active +0x0 (INT_STS_DISABLE): CQIS.HAC is disabled + 0 + 1 + read-write + + + + + CQISGE + No description available + 0x198 + 32 + 0x00000000 + 0x0000000F + + + TCL_SGE + Task cleared interrupt signal enable +Values: +0x1 (INT_SIG_ENABLE): CQIS.TCL interrupt signal generation is active +0x0 (INT_SIG_DISABLE): CQIS.TCL interrupt signal generation is disabled + 3 + 1 + read-write + + + RED_SGE + Response error detected interrupt signal enable +Values: +0x1 (INT_SIG_ENABLE): CQIS.RED interrupt signal generation is active +0x0 (INT_SIG_DISABLE): CQIS.RED interrupt signal generation is disabled + 2 + 1 + read-write + + + TCC_SGE + Task complete interrupt signal enable +Values: +0x1 (INT_SIG_ENABLE): CQIS.TCC interrupt signal generation is active +0x0 (INT_SIG_DISABLE): CQIS.TCC interrupt signal generation is disabled + 1 + 1 + read-write + + + HAC_SGE + Halt complete interrupt signal enable +Values: +0x1 (INT_SIG_ENABLE): CQIS.HAC interrupt signal generation is active +0x0 (INT_SIG_DISABLE): CQIS.HAC interrupt signal generation is disabled + 0 + 1 + read-write + + + + + CQIC + No description available + 0x19c + 32 + 0x00000000 + 0x80119FFF + + + INTC_EN + Interrupt Coalescing Enable Bit +Values: +0x1 (ENABLE_INT_COALESCING): Interrupt coalescing mechanism is active. Interrupts are counted and timed, and coalesced interrupts are generated +0x0 (DISABLE_INT_COALESCING): Interrupt coalescing mechanism is disabled (Default) + 31 + 1 + read-write + + + INTC_STAT + Interrupt Coalescing Status Bit +This bit indicates to the software whether any tasks (with INT=0) have completed and counted towards interrupt +coalescing (that is, this is set if and only if INTC counter > 0). +Values: +0x1 (INTC_ATLEAST1_COMP): At least one INT0 task completion has been counted (INTC counter > 0) +0x0 (INTC_NO_TASK_COMP): INT0 Task completions have not occurred since last counter reset (INTC counter == 0) + 20 + 1 + read-only + + + INTC_RST + Counter and Timer Reset +When host driver writes 1, the interrupt coalescing timer and counter are reset. +Values: +0x1 (ASSERT_INTC_RESET): Interrupt coalescing timer and counter are reset +0x0 (NO_EFFECT): No Effect + 16 + 1 + write-only + + + INTC_TH_WEN + Interrupt Coalescing Counter Threshold Write Enable +When software writes 1 to this bit, the value INTC_TH is updated with the contents written on the same cycle. +Values: +0x1 (WEN_SET): Sets INTC_TH_WEN +0x0 (WEN_CLR): Clears INTC_TH_WEN + 15 + 1 + write-only + + + INTC_TH + Interrupt Coalescing Counter Threshold filed +Software uses this field to configure the number of task completions (only tasks with INT=0 in the Task Descriptor), which are required in order to generate an interrupt. +Counter Operation: As data transfer tasks with INT=0 complete, they are counted by CQE. +The counter is reset by software during the interrupt service routine. +The counter stops counting when it reaches the value configured in INTC_TH, and generates interrupt. +0x0: Interrupt coalescing feature disabled +0x1: Interrupt coalescing interrupt generated after 1 task when INT=0 completes +0x2: Interrupt coalescing interrupt generated after 2 tasks when INT=0 completes +........ +0x1f: Interrupt coalescing interrupt generated after 31 tasks when INT=0 completes +To write to this field, the INTC_TH_WEN bit must be set during the same write operation. + 8 + 5 + write-only + + + TOUT_VAL_WEN + When software writes 1 to this bit, the value TOUT_VAL is updated with the contents written on the same cycle. +Values: +0x1 (WEN_SET): Sets TOUT_VAL_WEN +0x0 (WEN_CLR): clears TOUT_VAL_WEN + 7 + 1 + write-only + + + TOUT_VAL + Interrupt Coalescing Timeout Value +Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt. +Timer Operation: The timer is reset by software during the interrupt service routine. +It starts running when the first data transfer task with INT=0 is completed, after the timer was reset. +When the timer reaches the value configured in ICTOVAL field, it generates an interrupt and stops. +The timer's unit is equal to 1024 clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. +0x0: Timer is disabled. Timeout-based interrupt is not generated +0x1: Timeout on 01x1024 cycles of timer clock frequency +0x2: Timeout on 02x1024 cycles of timer clock frequency +........ +0x7f: Timeout on 127x1024 cycles of timer clock frequency +In order to write to this field, the TOUT_VAL_WEN bit must +be set at the same write operation. + 0 + 7 + read-write + + + + + CQTDLBA + No description available + 0x1a0 + 32 + 0x00000000 + 0xFFFFFFFF + + + TDLBA + This register stores the LSB bits (31:0) of the byte address of the head of the Task Descriptor List in system memory. +The size of the task descriptor list is 32 * (Task Descriptor size + Transfer Descriptor size) as configured by the host driver. +This address is set on 1 KB boundary. The lower 10 bits of this register are set to 0 by the software and are ignored by CQE + 0 + 32 + read-write + + + + + CQTDBR + No description available + 0x1a8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DBR + The software configures TDLBA and TDLBAU, and enable +CQE in CQCFG before using this register. +Writing 1 to bit n of this register triggers CQE to start processing the task encoded in slot n of the TDL. +Writing 0 by the software does not have any impact on the hardware, and does not change the value of the register bit. +CQE always processes tasks according to the order submitted to the list by CQTDBR write transactions. +CQE processes Data Transfer tasks by reading the Task Descriptor and sending QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) commands to +the device. CQE processes DCMD tasks (in slot #31, when enabled) by reading the Task Descriptor, and generating the command encoded by its index and argument. +The corresponding bit is cleared to 0 by CQE in one of the following events: +A task execution is completed (with success or error). +The task is cleared using CQTCLR register. +All tasks are cleared using CQCTL register. +CQE is disabled using CQCFG register. +Software may initiate multiple tasks at the same time (batch submission) by writing 1 to multiple bits of this register in the same transaction. +In the case of batch submission, CQE processes the tasks in order of the task index, starting with the lowest index. +If one or more tasks in the batch are marked with QBR, the ordering of execution is based on said processing order. + 0 + 32 + read-write + + + + + CQTCN + No description available + 0x1ac + 32 + 0x00000000 + 0xFFFFFFFF + + + TCN + Task Completion Notification +Each of the 32 bits are bit mapped to the 32 tasks. +Bit-N(1): Task-N has completed execution (with success or errors) +Bit-N(0): Task-N has not completed, could be pending or not submitted. +On task completion, software may read this register to know tasks that have completed. After reading this register, +software may clear the relevant bit fields by writing 1 to the corresponding bits. + 0 + 32 + read-write + + + + + CQDQS + No description available + 0x1b0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DQS + Device Queue Status +Each of the 32 bits are bit mapped to the 32 tasks. +Bit-N(1): Device has marked task N as ready for execution +Bit-N(0): Task-N is not ready for execution. This task could be pending in device or not submitted. +Host controller updates this register with response of the Device Queue Status command. + 0 + 32 + read-write + + + + + CQDPT + No description available + 0x1b4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DPT + Device-Pending Tasks +Each of the 32 bits are bit mapped to the 32 tasks. +Bit-N(1): Task-N has been successfully queued into the device and is awaiting execution +Bit-N(0): Task-N is not yet queued. +Bit n of this register is set if and only if QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) were sent for this specific task and if this task has not been executed. +The controller sets this bit after receiving a successful response for CMD45. CQE clears this bit after the task has completed execution. +Software reads this register in the task-discard procedure to determine if the task is queued in the device + 0 + 32 + read-write + + + + + CQTCLR + No description available + 0x1b8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TCLR + Writing 1 to bit n of this register orders CQE to clear a task that the software has previously issued. +This bit can only be written when CQE is in Halt state as indicated in CQCFG register Halt bit. +When software writes 1 to a bit in this register, CQE updates the value to 1, and starts clearing the data structures related to the task. +CQE clears the bit fields (sets a value of 0) in CQTCLR and in CQTDBR once the clear operation is complete. +Software must poll on the CQTCLR until it is leared to verify that a clear operation was done. + 0 + 32 + read-write + + + + + CQSSC1 + No description available + 0x1c0 + 32 + 0x00000000 + 0x000FFFFF + + + SQSCMD_BLK_CNT + This field indicates when SQS CMD is sent while data transfer is in progress. +A value of 'n' indicates that CQE sends status command on the CMD line, during the transfer of data block BLOCK_CNTn, on the data lines, where BLOCK_CNT is the number of blocks in the current transaction. +0x0: SEND_QUEUE_STATUS (CMD13) command is not sent during the transaction. Instead, it is sent only when the data lines are idle. +0x1: SEND_QUEUE_STATUS command is to be sent during the last block of the transaction. +0x2: SEND_QUEUE_STATUS command when last 2 blocks are pending. +0x3: SEND_QUEUE_STATUS command when last 3 blocks are pending. +........ +0xf: SEND_QUEUE_STATUS command when last 15 blocks are pending. +Should be programmed only when CQCFG.CQ_EN is 0 + 16 + 4 + read-write + + + SQSCMD_IDLE_TMR + This field configures the polling period to be used when using periodic SEND_QUEUE_STATUS (CMD13) polling. +Periodic polling is used when tasks are pending in the device, but no data transfer is in progress. +When a SEND_QUEUE_STATUS response indicates that no task is ready for execution, CQE counts the configured time until it issues the next SEND_QUEUE_STATUS. +Timer units are clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. +The minimum value is 0001h (1 clock period) and the maximum value is FFFFh (65535 clock periods). +For example, a CQCAP field value of 0 indicates a 19.2 MHz clock frequency (period = 52.08 ns). +If the setting in CQSSC1.CIT is 1000h, the calculated polling period is 4096*52.08 ns= 213.33 us. +Should be programmed only when CQCFG.CQ_EN is '0' + 0 + 16 + read-write + + + + + CQSSC2 + No description available + 0x1c4 + 32 + 0x00000000 + 0x0000FFFF + + + SQSCMD_RCA + This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_STATUS (CMD13) command argument. +CQE copies this field to bits 31:16 of the argument when transmitting SEND_ QUEUE_STATUS (CMD13) command. + 0 + 16 + read-write + + + + + CQCRDCT + No description available + 0x1c8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DCMD_RESP + This register contains the response of the command generated by the last direct command (DCMD) task that was sent. +Contents of this register are valid only after bit 31 of CQTDBR register is cleared by the controller. + 0 + 32 + read-only + + + + + CQRMEM + No description available + 0x1d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESP_ERR_MASK + The bits of this field are bit mapped to the device response. +This bit is used as an interrupt mask on the device status filed that is received in R1/R1b responses. +1: When a R1/R1b response is received, with a bit i in the device status set, a RED interrupt is generated. +0: When a R1/R1b response is received, bit i in the device status is ignored. +The reset value of this register is set to trigger an interrupt on all "Error" type bits in the device status. +Note: Responses to CMD13 (SQS) encode the QSR so that they are ignored by this logic. + 0 + 32 + read-write + + + + + CQTERRI + No description available + 0x1d4 + 32 + 0x00000000 + 0x1F3F9F3F + + + TRANS_ERR_TASKID + This field captures the ID of the task that was executed and whose data transfer has errors. + 24 + 5 + read-only + + + TRANS_ERR_CMD_INDX + This field captures the index of the command that was executed and whose data transfer has errors. + 16 + 6 + read-only + + + RESP_ERR_FIELDS_VALID + This bit is updated when an error is detected while a command transaction was in progress. +Values: +0x1 (SET): Response-related error is detected. Check contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX fields +0x0 (NOT_SET): Ignore contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX + 15 + 1 + read-only + + + RESP_ERR_TASKID + This field captures the ID of the task which was executed on the command line when the error occurred. + 8 + 5 + read-only + + + RESP_ERR_CMD_INDX + This field captures the index of the command that was executed on the command line when the error occurred + 0 + 6 + read-only + + + + + CQCRI + No description available + 0x1d8 + 32 + 0x00000000 + 0x0000003F + + + CMD_RESP_INDX + Last Command Response index +This field stores the index of the last received command response. Controller updates the value every time a command response is received + 0 + 6 + read-only + + + + + CQCRA + No description available + 0x1dc + 32 + 0x00000000 + 0xFFFFFFFF + + + CMD_RESP_ARG + Last Command Response argument +This field stores the argument of the last received command response. Controller updates the value every time a command response is received. + 0 + 32 + read-only + + + + + MSHC_VER_ID + No description available + 0x500 + 32 + 0x00000000 + 0xFFFFFFFF + + + VER_ID + No description available + 0 + 32 + read-only + + + + + MSHC_VER_TYPE + No description available + 0x504 + 32 + 0x00000000 + 0xFFFFFFFF + + + VER_TYPE + No description available + 0 + 32 + read-only + + + + + EMMC_BOOT_CTRL + No description available + 0x52c + 32 + 0x00000000 + 0xF181070F + + + BOOT_TOUT_CNT + Boot Ack Timeout Counter Value. +This value determines the interval by which boot ack timeout (50 ms) is detected when boot ack is expected during boot operation. +0xF : Reserved +0xE : TMCLK x 2^27 + ............ +0x1 : TMCLK x 2^14 +0x0 : TMCLK x 2^13 + 28 + 4 + read-write + + + BOOT_ACK_ENABLE + Boot Acknowledge Enable +When this bit set, SDXC checks for boot acknowledge start pattern of 0-1-0 during boot operation. This bit is applicable for both mandatory and alternate boot mode. +Values: +0x1 (TRUE): Boot Ack enable +0x0 (FALSE): Boot Ack disable + 24 + 1 + read-write + + + VALIDATE_BOOT + Validate Mandatory Boot Enable bit +This bit is used to validate the MAN_BOOT_EN bit. +Values: +0x1 (TRUE): Validate Mandatory boot enable bit +0x0 (FALSE): Ignore Mandatory boot Enable bit + 23 + 1 + write-only + + + MAN_BOOT_EN + Mandatory Boot Enable +This bit is used to initiate the mandatory boot operation. The application sets this bit along with VALIDATE_BOOT bit. +Writing 0 is ignored. The SDXC clears this bit after the boot transfer is completed or terminated. +Values: +0x1 (MAN_BOOT_EN): Mandatory boot enable +0x0 (MAN_BOOT_DIS): Mandatory boot disable + 16 + 1 + read-write + + + CQE_PREFETCH_DISABLE + Enable or Disable CQE's PREFETCH feature +This field allows Software to disable CQE's data prefetch feature when set to 1. +Values: +0x0 (PREFETCH_ENABLE): CQE can Prefetch data for sucessive WRITE transfers and pipeline sucessive READ transfers +0x1 (PREFETCH_DISABLE): Prefetch for WRITE and Pipeline for READ are disabled + 10 + 1 + read-write + + + CQE_ALGO_SEL + Scheduler algorithm selected for execution +This bit selects the Algorithm used for selecting one of the many ready tasks for execution. +Values: +0x0 (PRI_REORDER_PLUS_FCFS): Priority based reordering with FCFS to resolve equal priority tasks +0x1 (FCFS_ONLY): First come First serve, in the order of DBR rings + 9 + 1 + read-write + + + ENH_STROBE_ENABLE + Enhanced Strobe Enable +This bit instructs SDXC to sample the CMD line using data strobe for HS400 mode. +Values: +0x1 (ENH_STB_FOR_CMD): CMD line is sampled using data strobe for HS400 mode +0x0 (NO_STB_FOR_CMD): CMD line is sampled using cclk_rx for HS400 mode + 8 + 1 + read-write + + + EMMC_RST_N_OE + Output Enable control for EMMC Device Reset signal PAD +control. +This field drived sd_rst_n_oe output of SDXC +Values: +0x1 (ENABLE): sd_rst_n_oe is 1 +0x0 (DISABLE): sd_rst_n_oe is 0 + 3 + 1 + read-write + + + EMMC_RST_N + EMMC Device Reset signal control. +This register field controls the sd_rst_n output of SDXC +Values: +0x1 (RST_DEASSERT): Reset to eMMC device is deasserted +0x0 (RST_ASSERT): Reset to eMMC device asserted (active low) + 2 + 1 + read-write + + + DISABLE_DATA_CRC_CHK + Disable Data CRC Check +This bit controls masking of CRC16 error for Card Write in eMMC mode. +This is useful in bus testing (CMD19) for an eMMC device. In bus testing, an eMMC card does not send CRC status for a block, +which may generate CRC error. This CRC error can be masked using this bit during bus testing. +Values: +0x1 (DISABLE): DATA CRC check is disabled +0x0 (ENABLE): DATA CRC check is enabled + 1 + 1 + read-write + + + CARD_IS_EMMC + eMMC Card present +This bit indicates the type of card connected. An application program this bit based on the card connected to SDXC. +Values: +0x1 (EMMC_CARD): Card connected to SDXC is an eMMC card +0x0 (NON_EMMC_CARD): Card connected to SDXCis a non-eMMC card + 0 + 1 + read-write + + + + + AUTO_TUNING_CTRL + No description available + 0x540 + 32 + 0x00000000 + 0x7F1F0F1F + + + SWIN_TH_VAL + Sampling window threshold value setting +The maximum value that can be set here depends on the length of delayline used for tuning. A delayLine with 32 taps +can use values from 0x0 to 0x1F. +This field is valid only when SWIN_TH_EN is '1'. Should be programmed only when SAMPLE_CLK_SEL is '0' +0x0 : Threshold values is 0x1, windows of length 1 tap and above can be selected as sampling window. +0x1 : Threshold values is 0x2, windows of length 2 taps and above can be selected as sampling window. +0x2 : Threshold values is 0x1, windows of length 3 taps and above can be selected as sampling window. +........ +0x1F : Threshold values is 0x1, windows of length 32 taps and above can be selected as sampling window. + 24 + 7 + read-write + + + POST_CHANGE_DLY + Time taken for phase switching and stable clock output. +Specifies the maximum time (in terms of cclk cycles) that the delay line can take to switch its output phase after a change in tuning_cclk_sel or autotuning_cclk_sel. +Values: +0x0 (LATENCY_LT_1): Less than 1-cycle latency +0x1 (LATENCY_LT_2): Less than 2-cycle latency +0x2 (LATENCY_LT_3): Less than 3-cycle latency +0x3 (LATENCY_LT_4): Less than 4-cycle latency + 19 + 2 + read-write + + + PRE_CHANGE_DLY + Maximum Latency specification between cclk_tx and cclk_rx. +Values: +0x0 (LATENCY_LT_1): Less than 1-cycle latency +0x1 (LATENCY_LT_2): Less than 2-cycle latency +0x2 (LATENCY_LT_3): Less than 3-cycle latency +0x3 (LATENCY_LT_4): Less than 4-cycle latency + 17 + 2 + read-write + + + TUNE_CLK_STOP_EN + Clock stopping control for Tuning and auto-tuning circuit. +When enabled, clock gate control output of SDXC (clk2card_on) is pulled low before changing phase select codes on tuning_cclk_sel and autotuning_cclk_sel. +This effectively stops the Device/Card clock, cclk_rx and also drift_cclk_rx. Changing phase code when clocks are stopped ensures glitch free phase switching. + Set this bit to 0 if the PHY or delayline can guarantee glitch free switching. +Values: +0x1 (ENABLE_CLK_STOPPING): Clocks stopped during phase code change +0x0 (DISABLE_CLK_STOPPING): Clocks not stopped. PHY ensures glitch free phase switching + 16 + 1 + read-write + + + WIN_EDGE_SEL + This field sets the phase for Left and Right edges for drift monitoring. [Left edge offset + Right edge offset] must not be less than total taps of delayLine. +0x0: User selection disabled. Tuning calculated edges are used. +0x1: Right edge Phase is center + 2 stages, Left edge Phase is center - 2 stages. +0x2: Right edge Phase is center + 3 stages, Left edge Phase is center - 3 stagess +... +0xF: Right edge Phase is center + 16 stages, Left edge Phase is center - 16 stages. + 8 + 4 + read-write + + + SW_TUNE_EN + This fields enables software-managed tuning flow. +Values: +0x1 (SW_TUNING_ENABLE): Software-managed tuning enabled. AUTO_TUNING_STAT.CENTER_PH_CODE Field is now writable. +0x0 (SW_TUNING_DISABLE): Software-managed tuning disabled + 4 + 1 + read-write + + + RPT_TUNE_ERR + Framing errors are not generated when executing tuning. +This debug bit allows users to report these errors. +Values: +0x1 (DEBUG_ERRORS): Debug mode for reporting framing errors +0x0 (ERRORS_DISABLED): Default mode where as per SDXC no errors are reported. + 3 + 1 + read-write + + + SWIN_TH_EN + Sampling window Threshold enable +Selects the tuning mode +Field should be programmed only when SAMPLE_CLK_SEL is '0' +Values: +0x1 (THRESHOLD_MODE): Tuning engine selects the first complete sampling window that meets the threshold +set by SWIN_TH_VAL field +0x0 (LARGEST_WIN_MODE): Tuning engine sweeps all taps and settles at the largest window + 2 + 1 + read-write + + + CI_SEL + Selects the interval when the corrected center phase select code can be driven on tuning_cclk_sel output. +Values: +0x0 (WHEN_IN_BLK_GAP): Driven in block gap interval +0x1 (WHEN_IN_IDLE): Driven at the end of the transfer + 1 + 1 + read-write + + + AT_EN + Setting this bit enables Auto tuning engine. This bit is enabled by default when core is configured with mode3 retuning support. +Clear this bit to 0 when core is configured to have Mode3 re-tuning but SW wishes to disable mode3 retuning. +This field should be programmed only when SYS_CTRL.SD_CLK_EN is 0. +Values: +0x1 (AT_ENABLE): AutoTuning is enabled +0x0 (AT_DISABLE): AutoTuning is disabled + 0 + 1 + read-write + + + + + AUTO_TUNING_STAT + No description available + 0x544 + 32 + 0x00000000 + 0x00FFFFFF + + + L_EDGE_PH_CODE + Left Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Left edge of sampling window. + 16 + 8 + read-only + + + R_EDGE_PH_CODE + Right Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Right edge of sampling window. + 8 + 8 + read-only + + + CENTER_PH_CODE + Centered Phase code. Reading this field returns the current value on tuning_cclk_sel output. Setting AUTO_TUNING_CTRL.SW_TUNE_EN enables software to write to this field and its contents are reflected on tuning_cclk_sel + 0 + 8 + read-write + + + + + MISC_CTRL0 + No description available + 0x3000 + 32 + 0x00000000 + 0x10020FFF + + + CARDCLK_INV_EN + set to invert card_clk, for slow speed card to meet 5ns setup timing. +May cause glitch on clock, should be set before enable clk(in core cfg) + 28 + 1 + read-write + + + PAD_CLK_SEL_B + set to use internal clock directly, may have timing issue; +clr to use clock loopback from pad. + 17 + 1 + read-write + + + FREQ_SEL_SW_EN + set to use FREQ_SEL_SW as card clock divider; +clear to use core logic as clock divider. + 11 + 1 + read-write + + + TMCLK_EN + set to force enable tmclk; +clear to use core signal intclk_en to control it + 10 + 1 + read-write + + + FREQ_SEL_SW + software card clock divider, it will be used only when FREQ_SEL_SW_EN is set + 0 + 10 + read-write + + + + + MISC_CTRL1 + No description available + 0x3004 + 32 + 0x00000000 + 0xB0000000 + + + CARD_ACTIVE + SW write 1 to start card clock delay counter(delay time is configed by CARD_ACTIVE_PERIOD_SEL). +When counter finished, this bit will be cleared by hardware. +Write 1 when this bit is 1 will cause unknown result(actually no use except write at exact finish time) + 31 + 1 + read-write + + + CARD_ACTIVE_PERIOD_SEL + card clock delay config. +00 for 100 cycle; 01 for 74 cycle; 10 for 128 cycle; 11 for 256 cycle + 28 + 2 + read-write + + + + + + + I2C0 + I2C0 + I2C + 0xf3020000 + + 0x4 + 0x30 + registers + + + + Cfg + Configuration Register + 0x10 + 32 + 0x00000001 + 0xFFFFFFFF + + + FIFOSIZE + FIFO Size: +0: 2 bytes +1: 4 bytes +2: 8 bytes +3: 16 bytes + 0 + 2 + read-only + + + + + IntEn + Interrupt Enable Register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMPL + Set to enable the Completion Interrupt. +Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. +Slave: interrupts when a transaction addressing the controller is completed. + 9 + 1 + read-write + + + BYTERECV + Set to enable the Byte Receive Interrupt. +Interrupts when a byte of data is received +Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually. + 8 + 1 + read-write + + + BYTETRANS + Set to enable the Byte Transmit Interrupt. +Interrupts when a byte of data is transmitted. + 7 + 1 + read-write + + + START + Set to enable the START Condition Interrupt. +Interrupts when a START condition/repeated START condition is detected. + 6 + 1 + read-write + + + STOP + Set to enable the STOP Condition Interrupt +Interrupts when a STOP condition is detected. + 5 + 1 + read-write + + + ARBLOSE + Set to enable the Arbitration Lose Interrupt. +Master: interrupts when the controller loses the bus arbitration +Slave: not available in this mode. + 4 + 1 + read-write + + + ADDRHIT + Set to enable the Address Hit Interrupt. +Master: interrupts when the addressed slave returned an ACK. +Slave: interrupts when the controller is addressed. + 3 + 1 + read-write + + + FIFOHALF + Set to enable the FIFO Half Interrupt. +Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. +Transmitter: Interrupts when the FIFO is half-empty, i.e. there is <= 1/2 entries in the FIFO. +This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered. + 2 + 1 + read-write + + + FIFOFULL + Set to enable the FIFO Full Interrupt. +Interrupts when the FIFO is full. + 1 + 1 + read-write + + + FIFOEMPTY + Set to enabled the FIFO Empty Interrupt +Interrupts when the FIFO is empty. + 0 + 1 + read-write + + + + + Status + Status Register + 0x18 + 32 + 0x00000001 + 0xFFFFFFFF + + + LINESDA + Indicates the current status of the SDA line on the bus +1: high +0: low + 14 + 1 + read-only + + + LINESCL + Indicates the current status of the SCL line on the bus +1: high +0: low + 13 + 1 + read-only + + + GENCALL + Indicates that the address of the current transaction is a general call address: +1: General call +0: Not general call + 12 + 1 + read-only + + + BUSBUSY + Indicates that the bus is busy +The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus +1: Busy +0: Not busy + 11 + 1 + read-only + + + ACK + Indicates the type of the last received/transmitted acknowledgement bit: +1: ACK +0: NACK + 10 + 1 + read-only + + + CMPL + Transaction Completion +Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration +Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked. + 9 + 1 + write-only + + + BYTERECV + Indicates that a byte of data has been received. + 8 + 1 + write-only + + + BYTETRANS + Indicates that a byte of data has been transmitted. + 7 + 1 + write-only + + + START + Indicates that a START Condition or a repeated START condition has been transmitted/received. + 6 + 1 + write-only + + + STOP + Indicates that a STOP Condition has been transmitted/received. + 5 + 1 + write-only + + + ARBLOSE + Indicates that the controller has lost the bus arbitration. + 4 + 1 + write-only + + + ADDRHIT + Master: indicates that a slave has responded to the transaction. +Slave: indicates that a transaction is targeting the controller (including the General Call). + 3 + 1 + write-only + + + FIFOHALF + Transmitter: Indicates that the FIFO is half-empty. + 2 + 1 + read-only + + + FIFOFULL + Indicates that the FIFO is full. + 1 + 1 + read-only + + + FIFOEMPTY + Indicates that the FIFO is empty. + 0 + 1 + read-only + + + + + Addr + Address Register + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + The slave address. +For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid + 0 + 10 + read-write + + + + + Data + Data Register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + Write this register to put one byte of data to the FIFO. +Read this register to get one byte of data from the FIFO. + 0 + 8 + read-write + + + + + Ctrl + Control Register + 0x24 + 32 + 0x00001E00 + 0x000F9FFF + + + PHASE_START + Enable this bit to send a START condition at the beginning of transaction. +Master mode only. + 12 + 1 + read-write + + + PHASE_ADDR + Enable this bit to send the address after START condition. +Master mode only. + 11 + 1 + read-write + + + PHASE_DATA + Enable this bit to send the data after Address phase. +Master mode only. + 10 + 1 + read-write + + + PHASE_STOP + Enable this bit to send a STOP condition at the end of a transaction. +Master mode only. + 9 + 1 + read-write + + + DIR + Transaction direction +Master: Set this bit to determine the direction for the next transaction. +0: Transmitter +1: Receiver +Slave: The direction of the last received transaction. +0: Receiver +1: Transmitter + 8 + 1 + read-write + + + DATACNT + Data counts in bytes. +Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. +Slave: the meaning of DataCnt depends on the DMA mode: +If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. +If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. + 0 + 8 + read-write + + + + + Cmd + Command Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMD + Write this register with the following values to perform the corresponding actions: +0x0: no action +0x1: issue a data transaction (Master only) +0x2: respond with an ACK to the received byte +0x3: respond with a NACK to the received byte +0x4: clear the FIFO +0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) +When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. +Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled. + 0 + 3 + read-write + + + + + Setup + Setup Register + 0x2c + 32 + 0x05252100 + 0xFFFFFFFF + + + T_SUDAT + T_SUDAT defines the data setup time before releasing the SCL. +Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) +tpclk = PCLK period +TPM = The multiplier value in Timing Parameter Multiplier Register + 24 + 5 + read-write + + + T_SP + T_SP defines the pulse width of spikes that must be suppressed by the input filter. +Pulse width = T_SP * tpclk* (TPM+1) + 21 + 3 + read-write + + + T_HDDAT + T_HDDAT defines the data hold time after SCL goes LOW +Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) + 16 + 5 + read-write + + + T_SCLRADIO + The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. +SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) +1: ratio = 2 +0: ratio = 1 +This field is only valid when the controller is in the master mode. + 13 + 1 + read-write + + + T_SCLHI + The HIGH period of generated SCL clock is defined by T_SCLHi. +SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) +The T_SCLHi value must be greater than T_SP and T_HDDAT values. +This field is only valid when the controller is in the master mode. + 4 + 9 + read-write + + + DMAEN + Enable the direct memory access mode data transfer. +1: Enable +0: Disable + 3 + 1 + read-write + + + MASTER + Configure this device as a master or a slave. +1: Master mode +0: Slave mode + 2 + 1 + read-write + + + ADDRESSING + I2C addressing mode: +1: 10-bit addressing mode +0: 7-bit addressing mode + 1 + 1 + read-write + + + IICEN + Enable the I2C controller. +1: Enable +0: Disable + 0 + 1 + read-write + + + + + TPM + I2C Timing Paramater Multiplier + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + TPM + A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). + 0 + 5 + read-write + + + + + + + I2C1 + I2C1 + I2C + 0xf3024000 + + + I2C2 + I2C2 + I2C + 0xf3028000 + + + I2C3 + I2C3 + I2C + 0xf302c000 + + + SDP + SDP + SDP + 0xf304c000 + + 0x0 + 0x60 + registers + + + + SDPCR + SDP control register + 0x0 + 32 + 0x30000000 + 0xFFFE0101 + + + SFTRST + soft reset. +Write 1 then 0, to reset the SDP block. + 31 + 1 + read-write + + + CLKGAT + Clock Gate for the SDP main logic. +Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block. + 30 + 1 + read-write + + + CIPDIS + Cipher Disable, read the info, whether the CIPHER features is besing disable in this chip or not. +1, Cipher is disabled in this chip. +0, Cipher is enabled in this chip. + 29 + 1 + read-only + + + HASDIS + HASH Disable, read the info, whether the HASH features is besing disable in this chip or not. +1, HASH is disabled in this chip. +0, HASH is enabled in this chip. + 28 + 1 + read-only + + + CIPHEN + Cipher Enablement, controlled by SW. +1, Cipher is Enabled. +0, Cipher is Disabled. + 23 + 1 + read-write + + + HASHEN + HASH Enablement, controlled by SW. +1, HASH is Enabled. +0, HASH is Disabled. + 22 + 1 + read-write + + + MCPEN + Memory Copy Enablement, controlled by SW. +1, Memory copy is Enabled. +0, Memory copy is Disabled. + 21 + 1 + read-write + + + CONFEN + Constant Fill to memory, controlled by SW. +1, Constant fill is Enabled. +0, Constant fill is Disabled. + 20 + 1 + read-write + + + DCRPDI + Decryption Disable bit, Write to 1 to disable the decryption. + 19 + 1 + read-write + + + TSTPKT0IRQ + Test purpose for interrupt when Packet counter reachs "0", but CHAIN=1 in the current packet. + 17 + 1 + read-write + + + RDSCEN + when set to "1", the 1st data packet descriptor loacted in the register(CMDPTR, NPKTPTR, ...) +when set to "0", the 1st data packet descriptor loacted in the memeory(pointed by CMDPTR) + 8 + 1 + read-write + + + INTEN + Interrupt Enablement, controlled by SW. +1, SDP interrupt is enabled. +0, SDP interrupt is disabled. + 0 + 1 + read-write + + + + + MODCTRL + Mod control register. + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + AESALG + AES algorithem selection. +0x0 = AES 128; +0x1 = AES 256; +0x8 = SM4； +Others, reserved. + 28 + 4 + read-write + + + AESMOD + AES mode selection. +0x0 = ECB; +0x1 = CBC; +Others, reserved. + 24 + 4 + read-write + + + AESKS + AES Key Selection. +These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following: +0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key. +0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. +.... +0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key. +0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. +0x20: kman_sk0[127:0] from the key manager for AES128; AES256 will use kman_sk0[255:0] as AES key. +0x21: kman_sk0[255:128] from the key manager for AES128; not valid for AES256. +0x22: kman_sk1[127:0] from the key manager for AES128; AES256 will use kman_sk1[255:0] as AES key. +0x23: kman_sk1[255:128] from the key manager for AES128; not valid for AES256. +0x24: kman_sk2[127:0] from the key manager for AES128; AES256 will use kman_sk2[255:0] as AES key. +0x25: kman_sk2[255:128] from the key manager for AES128; not valid for AES256. +0x26: kman_sk3[127:0] from the key manager for AES128; AES256 will use kman_sk3[255:0] as AES key. +0x27: kman_sk3[255:128] from the key manager for AES128; not valid for AES256. +0x30: exip0_key[127:0] from OTP for AES128; AES256 will use exip0_key[255:0] as AES key. +0x31: exip0_key[255:128] from OTP for AES128; not valid for AES256. +0x32: exip1_key[127:0] from OTP for AES128; AES256 will use exip1_key[255:0] as AES key. +0x33: exip1_key[255:128] from OTP for AES128; not valid for AES256. +Other values, reserved. + 18 + 6 + read-write + + + AESDIR + AES direction +1x1, AES Decryption +1x0, AES Encryption. + 16 + 1 + read-write + + + HASALG + HASH Algorithem selection. +0x0 SHA1 — +0x1 CRC32 — +0x2 SHA256 — + 12 + 4 + read-write + + + CRCEN + CRC enable. +1x1, CRC is enabled. +1x0, CRC is disabled. + 11 + 1 + read-write + + + HASCHK + HASH Check Enable Bit. +1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers; +1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result. +For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words. + 10 + 1 + read-write + + + HASOUT + When hashing is enabled, this bit controls the input or output data of the AES engine is hashed. +0 INPUT HASH +1 OUTPUT HASH + 9 + 1 + read-write + + + DINSWP + Decide whether the SDP byteswaps the input data (big-endian data); +When all bits are set, the data is assumed to be in the big-endian format + 4 + 2 + read-write + + + DOUTSWP + Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format + 2 + 2 + read-write + + + KEYSWP + Decide whether the SDP byteswaps the Key (big-endian data). +When all bits are set, the data is assumed to be in the big-endian format + 0 + 2 + read-write + + + + + PKTCNT + packet counter registers. + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTVAL + This read-only field shows the current (instantaneous) value of the packet counter + 16 + 8 + read-only + + + CNTINCR + The value written to this field is added to the spacket count. + 0 + 8 + read-write + + + + + STA + Status Registers + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + TAG + packet tag. + 24 + 8 + read-only + + + IRQ + interrupt Request, requested when error happen, or when packet processing done, packet counter reach to zero. + 23 + 1 + write-only + + + CHN1PKT0 + the chain buffer "chain" bit is "1", while packet counter is "0", now, waiting for new buffer data. + 20 + 1 + write-only + + + AESBSY + AES Busy + 19 + 1 + read-only + + + HASBSY + Hashing Busy + 18 + 1 + read-only + + + PKTCNT0 + Packet Counter registers reachs to ZERO now. + 17 + 1 + write-only + + + PKTDON + Packet processing done, will trigger this itnerrrupt when the "PKTINT" bit set in the packet control word. + 16 + 1 + write-only + + + ERRSET + Working mode setup error. + 5 + 1 + write-only + + + ERRPKT + Packet head access error, or status update error. + 4 + 1 + write-only + + + ERRSRC + Source Buffer Access Error + 3 + 1 + write-only + + + ERRDST + Destination Buffer Error + 2 + 1 + write-only + + + ERRHAS + Hashing Check Error + 1 + 1 + write-only + + + ERRCHAIN + buffer chain error happen when packet's CHAIN bit=0, but the Packet counter is still not zero. + 0 + 1 + write-only + + + + + KEYADDR + Key Address + 0x10 + 32 + 0x00000040 + 0xFFFFFFFF + + + INDEX + To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. +Key index pointer. The valid indices are 0-[number_keys]. +In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses. + 16 + 8 + read-write + + + SUBWRD + Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field +increments; To write a key, the software must first write the desired key index/subword to this register. + 0 + 2 + read-write + + + + + KEYDAT + Key Data + 0x14 + 32 + 0x00000030 + 0xFFFFFFFF + + + KEYDAT + This register provides the write access to the key/key subword specified by the key index register. +Writing this location updates the selected subword for the key located at the index +specified by the key index register. The write also triggers the SUBWORD field of the +KEY register to increment to the next higher word in the key + 0 + 32 + read-write + + + + + 4 + 0x4 + CIPHIV0,CIPHIV1,CIPHIV2,CIPHIV3 + CIPHIV[%s] + no description available + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + CIPHIV + cipher initialization vector. + 0 + 32 + read-write + + + + + 8 + 0x4 + HASWRD0,HASWRD1,HASWRD2,HASWRD3,HASWRD4,HASWRD5,HASWRD6,HASWRD7 + HASWRD[%s] + no description available + 0x28 + 32 + 0x00000030 + 0xFFFFFFFF + + + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + 0 + 32 + read-write + + + + + CMDPTR + Command Pointer + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMDPTR + current command addresses the register points to the multiword +descriptor that is to be executed (or is currently being executed) + 0 + 32 + read-write + + + + + NPKTPTR + Next Packet Address Pointer + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + NPKTPTR + Next Packet Address Pointer + 0 + 32 + read-write + + + + + PKTCTL + Packet Control Registers + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTTAG + packet tag + 24 + 8 + read-write + + + CIPHIV + Load Initial Vector for the AES in this packet. + 6 + 1 + read-write + + + HASFNL + Hash Termination packet + 5 + 1 + read-write + + + HASINI + Hash Initialization packat + 4 + 1 + read-write + + + CHAIN + whether the next command pointer register must be loaded into the channel's current descriptor +pointer. + 3 + 1 + read-write + + + DCRSEMA + whether the channel's semaphore must be decremented at the end of the current operation. +When the semaphore reaches a value of zero, no more operations are issued from the channel. + 2 + 1 + read-write + + + PKTINT + Reflects whether the channel must issue an interrupt upon the completion of the packet + 1 + 1 + read-write + + + + + PKTSRC + Packet Memory Source Address + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTSRC + Packet Memory Source Address + 0 + 32 + read-write + + + + + PKTDST + Packet Memory Destination Address + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTDST + Packet Memory Destination Address + 0 + 32 + read-write + + + + + PKTBUF + Packet buffer size. + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTBUF + No description available + 0 + 32 + read-write + + + + + + + FEMC + FEMC + FEMC + 0xf3050000 + + 0x0 + 0x154 + registers + + + + CTRL + Control Register + 0x0 + 32 + 0x00000000 + 0x1FFF0007 + + + BTO + Bus timeout cycles +AXI Bus timeout cycle is as following (255*(2^BTO)): +00000b - 255*1 +00001-11110b - 255*2 - 255*2^30 +11111b - 255*2^31 + 24 + 5 + read-write + + + CTO + Command Execution timeout cycles +When Command Execution time exceed this timeout cycles, IPCMDERR or AXICMDERR interrupt is +generated. When CTO is set to zero, timeout cycle is 256*1024 cycle. otherwisee timeout cycle is +CTO*1024 cycle. + 16 + 8 + read-write + + + DQS + DQS (read strobe) mode +0b - Dummy read strobe loopbacked internally +1b - Dummy read strobe loopbacked from DQS pad + 2 + 1 + read-write + + + DIS + Module Disable +0b - Module enabled +1b - Module disabled + 1 + 1 + read-write + + + RST + Software Reset +Reset all internal logic in SEMC except configuration register + 0 + 1 + read-write + + + + + IOCTRL + IO Mux Control Register + 0x4 + 32 + 0x00000000 + 0x000000F0 + + + IO_CSX + IO_CSX output selection +0001b - SDRAM CS1 +0110b - SRAM CE# + 4 + 4 + read-write + + + + + BMW0 + Bus (AXI) Weight Control Register 0 + 0x8 + 32 + 0x00000000 + 0x00FFFFFF + + + RWS + Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is +same as current executing command with read/write operation switch. + 16 + 8 + read-write + + + SH + Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is +same as current executing command without read/write operation switch. + 8 + 8 + read-write + + + AGE + Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is +multiplied by WAGE to get weight score. + 4 + 4 + read-write + + + QOS + Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator +for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS +is multiplied by WQOS to get weight score. + 0 + 4 + read-write + + + + + BMW1 + Bus (AXI) Weight Control Register 1 + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + BR + Weight of Bank Rotation. This weight score is valid when queue command's bank is not same as current +executing command. + 24 + 8 + read-write + + + RWS + Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is +same as current executing command with read/write operation switch. + 16 + 8 + read-write + + + PH + Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is +same as current executing command without read/write operation switch. + 8 + 8 + read-write + + + AGE + Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is +multiplied by WAGE to get weight score. + 4 + 4 + read-write + + + QOS + Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator +for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS +is multiplied by WQOS to get weight score. + 0 + 4 + read-write + + + + + 3 + 0x4 + BASE0,BASE1,rsv2,rsv3,rsv4,rsv5,BASE6 + BR[%s] + no description available + 0x10 + 32 + 0x00000000 + 0xFFFFF03F + + + BASE + Base Address +This field determines high position 20 bits of SoC level Base Address. SoC level Base Address low +position 12 bits are all zero. + 12 + 20 + read-write + + + SIZE + Memory size +00000b - 4KB +00001b - 8KB +00010b - 16KB +00011b - 32KB +00100b - 64KB +00101b - 128KB +00110b - 256KB +00111b - 512KB +01000b - 1MB +01001b - 2MB +01010b - 4MB +01011b - 8MB +01100b - 16MB +01101b - 32MB +01110b - 64MB +01111b - 128MB +10000b - 256MB +10001b - 512MB +10010b - 1GB +10011b - 2GB +10100-11111b - 4GB + 1 + 5 + read-write + + + VLD + Valid + 0 + 1 + read-write + + + + + INTEN + Interrupt Enable Register + 0x38 + 32 + 0x00000000 + 0x0000000F + + + AXIBUSERR + AXI BUS error interrupt enable +0b - Interrupt is disabled +1b - Interrupt is enabled + 3 + 1 + read-write + + + AXICMDERR + AXI command error interrupt enable +0b - Interrupt is disabled +1b - Interrupt is enabled + 2 + 1 + read-write + + + IPCMDERR + IP command error interrupt enable +0b - Interrupt is disabled +1b - Interrupt is enabled + 1 + 1 + read-write + + + IPCMDDONE + IP command done interrupt enable +0b - Interrupt is disabled +1b - Interrupt is enabled + 0 + 1 + read-write + + + + + INTR + Interrupt Status Register + 0x3c + 32 + 0x00000000 + 0x0000000F + + + AXIBUSERR + AXI bus error interrupt +AXI Bus error interrupt is generated in following cases: +• AXI address is invalid +• AXI 8-bit or 16-bit WRAP write/read + 3 + 1 + write-only + + + AXICMDERR + AXI command error interrupt +AXI command error interrupt is generated when AXI command execution timeout. + 2 + 1 + write-only + + + IPCMDERR + IP command error done interrupt +IP command error interrupt is generated in following case: +• IP Command Address target invalid device space +• IP Command Code unsupported +• IP Command triggered when previous command + 1 + 1 + write-only + + + IPCMDDONE + IP command normal done interrupt + 0 + 1 + write-only + + + + + SDRCTRL0 + SDRAM Control Register 0 + 0x40 + 32 + 0x00000000 + 0x00004FFB + + + BANK2 + 2 Bank selection bit +0b - SDRAM device has 4 banks. +1b - SDRAM device has 2 banks. + 14 + 1 + read-write + + + CAS + CAS Latency +00b - 1 +01b - 1 +10b - 2 +11b - 3 + 10 + 2 + read-write + + + COL + Column address bit number +00b - 12 bit +01b - 11 bit +10b - 10 bit +11b - 9 bit + 8 + 2 + read-write + + + COL8 + Column 8 selection bit +0b - Column address bit number is decided by COL field. +1b - Column address bit number is 8. COL field is ignored. + 7 + 1 + read-write + + + BURSTLEN + Burst Length +000b - 1 +001b - 2 +010b - 4 +011b - 8 +100b - 8 +101b - 8 +110b - 8 +111b - 8 + 4 + 3 + read-write + + + HIGHBAND + high band select +0: use data[15:0] for 16bit SDRAM; +1: use data[31:16] for 16bit SDRAM; +only used when Port Size is 16bit(PORTSZ=01b) + 3 + 1 + read-write + + + PORTSZ + Port Size +00b - 8bit +01b - 16bit +10b - 32bit + 0 + 2 + read-write + + + + + SDRCTRL1 + SDRAM Control Register 1 + 0x44 + 32 + 0x00000000 + 0x00FFFFFF + + + ACT2PRE + ACT to Precharge minimum time +It is promised ACT2PRE+1 clock cycles delay between ACTIVE command to PRECHARGE/PRECHARGE_ALL command. + 20 + 4 + read-write + + + CKEOFF + CKE OFF minimum time +It is promised clock suspend last at leat CKEOFF+1 clock cycles. + 16 + 4 + read-write + + + WRC + Write recovery time +It is promised WRC+1 clock cycles delay between WRITE command to PRECHARGE/PRECHARGE_ALL command. This could help to meet tWR timing requirement by SDRAM device. + 13 + 3 + read-write + + + RFRC + Refresh recovery time +It is promised RFRC+1 clock cycles delay between REFRESH command to ACTIVE command. Thiscould help to meet tRFC timing requirement by SDRAM device. + 8 + 5 + read-write + + + ACT2RW + ACT to Read/Write wait time +It is promised ACT2RW+1 clock cycles delay between ACTIVE command to READ/WRITE command.This could help to meet tRCD timing requirement by SDRAM device. + 4 + 4 + read-write + + + PRE2ACT + PRECHARGE to ACT/Refresh wait time +It is promised PRE2ACT+1 clock cycles delay between PRECHARGE/PRECHARGE_ALL commandto ACTIVE/REFRESH command. This could help to meet tRP timing requirement by SDRAM device. + 0 + 4 + read-write + + + + + SDRCTRL2 + SDRAM Control Register 2 + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + ITO + SDRAM Idle timeout +It closes all opened pages if the SDRAM idle time lasts more than idle timeout period. SDRAM is +considered idle when there is no AXI Bus transfer and no SDRAM command pending. +00000000b - IDLE timeout period is 256*Prescale period. +00000001-11111111b - IDLE timeout period is ITO*Prescale period. + 24 + 8 + read-write + + + ACT2ACT + ACT to ACT wait time +It is promised ACT2ACT+1 clock cycles delay between ACTIVE command to ACTIVE command. This +could help to meet tRRD timing requirement by SDRAM device. + 16 + 8 + read-write + + + REF2REF + Refresh to Refresh wait time +It is promised REF2REF+1 clock cycles delay between REFRESH command to REFRESH command. +This could help to meet tRFC timing requirement by SDRAM device. + 8 + 8 + read-write + + + SRRC + Self Refresh Recovery time +It is promised SRRC+1 clock cycles delay between Self-REFRESH command to any command. + 0 + 8 + read-write + + + + + SDRCTRL3 + SDRAM Control Register 3 + 0x4c + 32 + 0x00000000 + 0xFFFFFF0F + + + UT + Refresh urgent threshold +Internal refresh request is generated on every Refresh period. Before internal request timer count up to +urgent request threshold, the refresh request is considered as normal refresh request. Normal refresh +request is handled in lower priority than any pending AXI command or IP command to SDRAM device. +When internal request timer count up to this urgent threshold, refresh request is considered as urgent +refresh request. Urgent refresh request is handled in higher priority than any pending AXI command or IP +command to SDRAM device. +NOTE: When urgent threshold is no less than refresh period, refresh request is always considered as +urgent refresh request. +Refresh urgent threshold is as follwoing: +00000000b - 256*Prescaler period +00000001-11111111b - UT*Prescaler period + 24 + 8 + read-write + + + RT + Refresh timer period +Refresh timer period is as following: +00000000b - 256*Prescaler period +00000001-11111111b - RT*Prescaler period + 16 + 8 + read-write + + + PRESCALE + Prescaler timer period +Prescaler timer period is as following: +00000000b - 256*16 clock cycles +00000001-11111111b - PRESCALE*16 clock cycles + 8 + 8 + read-write + + + REBL + Refresh burst length +It could send multiple Auto-Refresh command in one burst when REBL is set to non-zero. The +number of Auto-Refresh command cycle sent to all SDRAM device in one refresh period is as following. +000b - 1 +001b - 2 +010b - 3 +011b - 4 +100b - 5 +101b - 6 +110b - 7 +111b - 8 + 1 + 3 + read-write + + + REN + Refresh enable + 0 + 1 + read-write + + + + + SRCTRL0 + SRAM control register 0 + 0x70 + 32 + 0x00000000 + 0x00000F01 + + + ADVH + ADV hold state +0b - ADV is high during address hold state +1b - ADV is low during address hold state + 11 + 1 + read-write + + + ADVP + ADV polarity +0b - ADV is active low +1b - ADV is active high + 10 + 1 + read-write + + + ADM + address data mode +00b - address and data MUX mode +11b - address and data non-MUX mode + 8 + 2 + read-write + + + PORTSZ + port size +0b - 8bit +1b - 16bit + 0 + 1 + read-write + + + + + SRCTRL1 + SRAM control register 1 + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + OEH + OE high time, is OEH+1 clock cycles + 28 + 4 + read-write + + + OEL + OE low time, is OEL+1 clock cycles + 24 + 4 + read-write + + + WEH + WE high time, is WEH+1 clock cycles + 20 + 4 + read-write + + + WEL + WE low time, is WEL+1 clock cycles + 16 + 4 + read-write + + + AH + Address hold time, is AH+1 clock cycles + 12 + 4 + read-write + + + AS + Address setup time, is AS+1 clock cycles + 8 + 4 + read-write + + + CEH + Chip enable hold time, is CEH+1 clock cycles + 4 + 4 + read-write + + + CES + Chip enable setup time, is CES+1 clock cycles + 0 + 4 + read-write + + + + + SADDR + IP Command Control Register 0 + 0x90 + 32 + 0x00000000 + 0xFFFFFFFF + + + SA + Slave address + 0 + 32 + read-write + + + + + DATSZ + IP Command Control Register 1 + 0x94 + 32 + 0x00000000 + 0x00000007 + + + DATSZ + Data Size in Byte +When IP command is not a write/read operation, DATSZ field would be ignored. +000b - 4 +001b - 1 +010b - 2 +011b - 3 +100b - 4 +101b - 4 +110b - 4 +111b - 4 + 0 + 3 + read-write + + + + + BYTEMSK + IP Command Control Register 2 + 0x98 + 32 + 0x00000000 + 0x0000000F + + + BM3 + Byte Mask for Byte 3 (IPTXD bit 31:24) +0b - Byte Unmasked +1b - Byte Masked + 3 + 1 + read-write + + + BM2 + Byte Mask for Byte 2 (IPTXD bit 23:16) +0b - Byte Unmasked +1b - Byte Masked + 2 + 1 + read-write + + + BM1 + Byte Mask for Byte 1 (IPTXD bit 15:8) +0b - Byte Unmasked +1b - Byte Masked + 1 + 1 + read-write + + + BM0 + Byte Mask for Byte 0 (IPTXD bit 7:0) +0b - Byte Unmasked +1b - Byte Masked + 0 + 1 + read-write + + + + + IPCMD + IP Command Register + 0x9c + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + This field should be written with 0x5AA5 when trigging an IP command for all device types. The memory +device is selected by BRx settings and IPCR0 registers. + 16 + 16 + write-only + + + CMD + SDRAM Commands: +• 0x8: READ +• 0x9: WRITE +• 0xA: MODESET +• 0xB: ACTIVE +• 0xC: AUTO REFRESH +• 0xD: SELF REFRESH +• 0xE: PRECHARGE +• 0xF: PRECHARGE ALL +• Others: RSVD +NOTE: SELF REFRESH is sent to all SDRAM devices because they shared same CLK pin. + 0 + 16 + read-write + + + + + IPTX + TX DATA Register + 0xa0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DAT + Data + 0 + 32 + read-write + + + + + IPRX + RX DATA Register + 0xb0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DAT + Data + 0 + 32 + read-write + + + + + STAT0 + Status Register 0 + 0xc0 + 32 + 0x00000000 + 0x00000001 + + + IDLE + Indicating whether it is in IDLE state. +When IDLE=1, it is in IDLE state. There is no pending AXI command in internal queue and no +pending device access. + 0 + 1 + read-only + + + + + DLYCFG + Delay Line Config Register + 0x150 + 32 + 0x00000000 + 0x0000203F + + + OE + delay clock output enable, should be set after setting DLYEN and DLYSEL + 13 + 1 + read-write + + + DLYSEL + delay line select, 0 for 1 cell, 31 for all 32 cells + 1 + 5 + read-write + + + DLYEN + delay line enable + 0 + 1 + read-write + + + + + + + FFA + FFA + FFA + 0xf3058000 + + 0x0 + 0x48 + registers + + + + CTRL + No description available + 0x0 + 32 + 0x00000000 + 0x80000001 + + + SFTRST + software reset the module if asserted to be 1. +EN is only active after this bit is zero. + 31 + 1 + read-write + + + EN + Asserted to enable the module + 0 + 1 + read-write + + + + + STATUS + No description available + 0x4 + 32 + 0x00000000 + 0x000000FF + + + FIR_OV + FIR Overflow err + 7 + 1 + write-only + + + FFT_OV + FFT Overflow Err + 6 + 1 + write-only + + + WR_ERR + AXI Data Write Error + 5 + 1 + write-only + + + RD_NXT_ERR + AXI Read Bus Error for NXT DATA + 4 + 1 + write-only + + + RD_ERR + AXI Data Read Error + 3 + 1 + write-only + + + NXT_CMD_RD_DONE + Indicate that next command sequence is already read into the module. + 1 + 1 + write-only + + + OP_CMD_DONE + Indicate that operation cmd is done, and data are available in system memory. + 0 + 1 + write-only + + + + + INT_EN + No description available + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + WRSV1 + Reserved + 8 + 24 + read-write + + + FIR_OV + FIR Overflow err + 7 + 1 + read-write + + + FFT_OV + FFT Overflow Err + 6 + 1 + read-write + + + WR_ERR + Enable Data Write Error interrupt + 5 + 1 + read-write + + + RD_NXT_ERR + Enable Read Bus Error for NXT DATA interrupt + 4 + 1 + read-write + + + RD_ERR + Enable Data Read Error interrupt + 3 + 1 + read-write + + + NXT_CMD_RD_DONE + Indicate that next command sequence is already read into the module. + 1 + 1 + read-write + + + OP_CMD_DONE + Indicate that operation cmd is done, and data are available in system memory. + 0 + 1 + read-write + + + + + OP_CTRL + No description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + NXT_ADDR + The address for the next command. +It will be processed after CUR_CMD is executed and done.. + 2 + 30 + read-write + + + NXT_EN + Whether NXT_CMD is enabled. +Asserted to enable the NXT_CMD when CUR_CMD is done, or CUR_CMD is not enabled.. + 1 + 1 + read-write + + + EN + Whether CUR_CMD is enabled. +Asserted to enable the CUR_CMD + 0 + 1 + read-write + + + + + OP_CMD + No description available + 0x24 + 32 + 0x00000000 + 0x01FFFEFF + + + CONJ_C + asserted to have conjuate value for coefs in computation + 24 + 1 + read-write + + + CMD + The Command Used: +0: FIR +2: FFT +Others: Reserved + 18 + 6 + read-write + + + OUTD_TYPE + Output data type: +0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 +4:complex sp float 5: real sp float + 15 + 3 + read-write + + + COEF_TYPE + Coef data type (used for FIR): +0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 +4:complex sp float 5: real sp float + 12 + 3 + read-write + + + IND_TYPE + Input data type: +0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 +4:complex sp float 5: real sp float + 9 + 3 + read-write + + + NXT_CMD_LEN + The length of nxt commands in 32-bit words + 0 + 8 + read-write + + + + + OP_REG0 + No description available + UNION_28 + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + CT + Contents + 0 + 32 + read-write + + + + + OP_FIR_MISC + No description available + UNION_28 + 0x28 + 32 + 0x00000000 + 0x00003FFF + + + FIR_COEF_TAPS + Length of FIR coefs （max 256） + 0 + 14 + read-write + + + + + OP_FFT_MISC + No description available + UNION_28 + 0x28 + 32 + 0x00000000 + 0x000007FF + + + FFT_LEN + FFT length +0:8, +..., +n:2^(3+n) + 7 + 4 + read-write + + + IFFT + Asserted to indicate IFFT + 6 + 1 + read-write + + + TMP_BLK + Memory block for indata. Should be assigned as 1 + 2 + 2 + read-write + + + IND_BLK + Memory block for indata. Should be assigned as 0 + 0 + 2 + read-write + + + + + OP_REG1 + No description available + UNION_2C + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + CT + Contents + 0 + 32 + read-write + + + + + OP_FIR_MISC1 + No description available + UNION_2C + 0x2c + 32 + 0x00000000 + 0x003FFFFF + + + OUTD_MEM_BLK + Should be assigned as 0 + 20 + 2 + read-write + + + COEF_MEM_BLK + Should be assigned as 1 + 18 + 2 + read-write + + + IND_MEM_BLK + Should be assigned as 2 + 16 + 2 + read-write + + + FIR_DATA_TAPS + The input data data length + 0 + 16 + read-write + + + + + OP_REG2 + No description available + UNION_30 + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + CT + Contents + 0 + 32 + read-write + + + + + OP_FFT_INRBUF + No description available + UNION_30 + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOC + The input (real) data buffer pointer + 0 + 32 + read-write + + + + + OP_REG3 + No description available + UNION_34 + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + CT + Contents + 0 + 32 + read-write + + + + + OP_FIR_INBUF + No description available + UNION_34 + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOC + The input data buffer pointer + 0 + 32 + read-write + + + + + OP_REG4 + No description available + UNION_38 + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + CT + Contents + 0 + 32 + read-write + + + + + OP_FIR_COEFBUF + No description available + UNION_38 + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOC + The coef buf pointer + 0 + 32 + read-write + + + + + OP_FFT_OUTRBUF + No description available + UNION_38 + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOC + The output (real) data buffer pointer + 0 + 32 + read-write + + + + + OP_REG5 + No description available + UNION_3C + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + CT + Contents + 0 + 32 + read-write + + + + + OP_FIR_OUTBUF + No description available + UNION_3C + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + LOC + The output data buffer pointer. The length of the output buffer should be （FIR_DATA_TAPS - FIR_COEF_TAPS + 1） + 0 + 32 + read-write + + + + + OP_REG6 + No description available + 0x40 + 32 + 0x00000000 + 0xFFFFFFFF + + + CT + Contents + 0 + 32 + read-write + + + + + OP_REG7 + No description available + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + CT + Contents + 0 + 32 + read-write + + + + + + + SYSCTL + SYSCTL + SYSCTL + 0xf4000000 + + 0x0 + 0x2c00 + registers + + + + 127 + 0x4 + cpu0,cpx0,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,rsv14,rsv15,rsv16,rsv17,rsv18,rsv19,rsv20,pow_cpu0,rst_soc,rst_cpu0,rsv24,rsv25,rsv26,rsv27,rsv28,rsv29,rsv30,rsv31,clk_src_xtal,clk_src_pll0,clk_src_clk0_pll0,clk_src_clk1_pll0,clk_src_clk2_pll0,clk_src_pll1,clk_src_clk0_pll1,clk_src_clk1_pll1,clk_src_pll2,clk_src_clk0_pll2,clk_src_clk1_pll2,clk_src_pll0_ref,clk_src_pll1_ref,clk_src_pll2_ref,rsv46,rsv47,rsv48,rsv49,rsv50,rsv51,rsv52,rsv53,rsv54,rsv55,rsv56,rsv57,rsv58,rsv59,rsv60,rsv61,rsv62,rsv63,clk_top_cpu0,clk_top_mct0,clk_top_femc,clk_top_xpi0,clk_top_xpi1,clk_top_tmr0,clk_top_tmr1,clk_top_tmr2,clk_top_tmr3,clk_top_urt0,clk_top_urt1,clk_top_urt2,clk_top_urt3,clk_top_urt4,clk_top_urt5,clk_top_urt6,clk_top_urt7,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_can0,clk_top_can1,clk_top_ptpc,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_ana3,clk_top_aud0,clk_top_aud1,clk_top_eth0,clk_top_ptp0,clk_top_ref0,clk_top_ref1,clk_top_ntm0,clk_top_sdc0,rsv104,rsv105,rsv106,rsv107,rsv108,rsv109,rsv110,rsv111,rsv112,rsv113,rsv114,rsv115,rsv116,rsv117,rsv118,rsv119,rsv120,rsv121,rsv122,rsv123,rsv124,rsv125,rsv126,rsv127,clk_top_adc0,clk_top_adc1,clk_top_adc2,clk_top_dac0,clk_top_i2s0,clk_top_i2s1,rsv134,rsv135,rsv136,rsv137,rsv138,rsv139,rsv140,rsv141,rsv142,rsv143,rsv144,rsv145,rsv146,rsv147,rsv148,rsv149,rsv150,rsv151,rsv152,rsv153,rsv154,rsv155,rsv156,rsv157,rsv158,rsv159,rsv160,rsv161,rsv162,rsv163,rsv164,rsv165,rsv166,rsv167,rsv168,rsv169,rsv170,rsv171,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,ahbp,axis,axic,femc,rom0,lmm0,ram0,mct0,xpi0,xpi1,sdp0,rng0,kman,dma0,dma1,ffa0,gpio,mbx0,wdg0,wdg1,tsns,tmr0,tmr1,tmr2,tmr3,urt0,urt1,urt2,urt3,urt4,urt5,urt6,urt7,i2c0,i2c1,i2c2,i2c3,spi0,spi1,spi2,spi3,can0,can1,ptpc,adc0,adc1,adc2,dac0,acmp,i2s0,i2s1,pdm0,dao,msyn,mot0,mot1,eth0,ntm0,sdc0,usb0,ref0,ref1 + RESOURCE[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + 2 + 0x10 + link0,link1 + GROUP0[%s] + no description available + 0x800 + + VALUE + Group setting + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + SET + Group setting + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: add periphera into this group，periphera is needed + 0 + 32 + read-write + + + + + CLEAR + Group setting + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: delete periphera in this group，periphera is not needed + 0 + 32 + read-write + + + + + TOGGLE + Group setting + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: toggle the result that whether periphera is needed before + 0 + 32 + read-write + + + + + + 1 + 0x10 + cpu0 + AFFILIATE[%s] + no description available + 0x900 + + VALUE + Affiliate of Group + 0x0 + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0, each bit represents a group +bit0: cpu0 depends on group0 +bit1: cpu0 depends on group1 +bit2: cpu0 depends on group2 +bit3: cpu0 depends on group3 + 0 + 4 + read-write + + + + + SET + Affiliate of Group + 0x4 + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0，each bit represents a group +0: no effect +1: the group is assigned to CPU0 + 0 + 4 + read-write + + + + + CLEAR + Affiliate of Group + 0x8 + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0, each bit represents a group +0: no effect +1: the group is not assigned to CPU0 + 0 + 4 + read-write + + + + + TOGGLE + Affiliate of Group + 0xc + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0, each bit represents a group +0: no effect +1: toggle the result that whether the group is assigned to CPU0 before + 0 + 4 + read-write + + + + + + 1 + 0x10 + cpu0 + RETENTION[%s] + no description available + 0x920 + + VALUE + Retention Control + 0x0 + 32 + 0x00000000 + 0x000000FF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +bit00: soc_mem is kept on while cpu stop, +bit01: soc_ctx is kept on while cpu stop, +bit02: cpu0_mem is kept on while cpu stop, +bit03: cpu0_ctx is kept on while cpu stop, +bit04: xtal_hold is kept on while cpu stop, +bit05: pll0_hold is kept on while cpu stop, +bit06: pll1_hold is kept on while cpu stop, +bit07: pll2_hold is kept on while cpu stop, + 0 + 8 + read-write + + + + + SET + Retention Control + 0x4 + 32 + 0x00000000 + 0x000000FF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +0: no effect +1: keep + 0 + 8 + read-write + + + + + CLEAR + Retention Control + 0x8 + 32 + 0x00000000 + 0x000000FF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +0: no effect +1: no keep + 0 + 8 + read-write + + + + + TOGGLE + Retention Control + 0xc + 32 + 0x00000000 + 0x000000FF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +0: no effect +1: toggle the result that whether the resource is kept on while CPU0 stop before + 0 + 8 + read-write + + + + + + 1 + 0x10 + cpu0 + POWER[%s] + no description available + 0x1000 + + status + Power Setting + 0x0 + 32 + 0x80000000 + 0xC0001100 + + + FLAG + flag represents power cycle happened from last clear of this bit +0: power domain did not edurance power cycle since last clear of this bit +1: power domain enduranced power cycle since last clear of this bit + 31 + 1 + read-write + + + FLAG_WAKE + flag represents wakeup power cycle happened from last clear of this bit +0: power domain did not edurance wakeup power cycle since last clear of this bit +1: power domain enduranced wakeup power cycle since last clear of this bit + 30 + 1 + read-write + + + LF_DISABLE + low fanout power switch disable +0: low fanout power switches are turned on +1: low fanout power switches are truned off + 12 + 1 + read-only + + + LF_ACK + low fanout power switch feedback +0: low fanout power switches are turned on +1: low fanout power switches are truned off + 8 + 1 + read-only + + + + + lf_wait + Power Setting + 0x4 + 32 + 0x00000255 + 0x000FFFFF + + + WAIT + wait time for low fan out power switch turn on, default value is 255 +0: 0 clock cycle +1: 1 clock cycles +. . . +clock cycles count on 24MHz + 0 + 20 + read-write + + + + + off_wait + Power Setting + 0xc + 32 + 0x00000015 + 0x000FFFFF + + + WAIT + wait time for power switch turn off, default value is 15 +0: 0 clock cycle +1: 1 clock cycles +. . . +clock cycles count on 24MHz + 0 + 20 + read-write + + + + + + 2 + 0x10 + soc,cpu0 + RESET[%s] + no description available + 0x1400 + + control + Reset Setting + 0x0 + 32 + 0x80000000 + 0xC0000011 + + + FLAG + flag represents reset happened from last clear of this bit +0: domain did not edurance reset cycle since last clear of this bit +1: domain enduranced reset cycle since last clear of this bit + 31 + 1 + read-write + + + FLAG_WAKE + flag represents wakeup reset happened from last clear of this bit +0: domain did not edurance wakeup reset cycle since last clear of this bit +1: domain enduranced wakeup reset cycle since last clear of this bit + 30 + 1 + read-write + + + HOLD + perform reset and hold in reset, until ths bit cleared by software +0: reset is released for function +1: reset is assert and hold + 4 + 1 + read-write + + + RESET + perform reset and release imediately +0: reset is released +1 reset is asserted and will release automatically + 0 + 1 + read-write + + + + + config + Reset Setting + 0x4 + 32 + 0x00643203 + 0x00FFFFFF + + + PRE_WAIT + wait cycle numbers before assert reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 16 + 8 + read-write + + + RSTCLK_NUM + reset clock number(must be even number) +0: 0 cycle +1: 0 cycles +2: 2 cycles +3: 2 cycles +. . . +Note, clock cycle is base on 24M + 8 + 8 + read-write + + + POST_WAIT + time guard band for reset release +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 8 + read-write + + + + + counter + Reset Setting + 0xc + 32 + 0x00000003 + 0x000FFFFF + + + COUNTER + self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 20 + read-write + + + + + + 1 + 0x4 + clk_top_cpu0 + CLOCK_CPU[%s] + no description available + 0x1800 + 32 + 0x00000000 + 0xD0FF0FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + SUB1_DIV + ahb bus divider, the bus clock is generated by cpu_clock/div +0: divider by 1 +1: divider by 2 +… + 20 + 4 + read-write + + + SUB0_DIV + axi bus divider, the bus clock is generated by cpu_clock/div +0: divider by 1 +1: divider by 2 +… + 16 + 4 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + 39 + 0x4 + clk_top_mct0,clk_top_femc,clk_top_xpi0,clk_top_xpi1,clk_top_tmr0,clk_top_tmr1,clk_top_tmr2,clk_top_tmr3,clk_top_urt0,clk_top_urt1,clk_top_urt2,clk_top_urt3,clk_top_urt4,clk_top_urt5,clk_top_urt6,clk_top_urt7,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_can0,clk_top_can1,clk_top_ptpc,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_ana3,clk_top_aud0,clk_top_aud1,clk_top_eth0,clk_top_ptp0,clk_top_ref0,clk_top_ref1,clk_top_ntm0,clk_top_sdc0 + CLOCK[%s] + no description available + 0x1804 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + 3 + 0x4 + clk_top_adc0,clk_top_adc1,clk_top_adc2 + ADCCLK[%s] + no description available + 0x1c00 + 32 + 0x00000000 + 0xD0000100 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux +0: ana clock +1: ahb clock + 8 + 1 + read-write + + + + + 1 + 0x4 + clk_top_dac0 + DACCLK[%s] + no description available + 0x1c0c + 32 + 0x00000000 + 0xD0000100 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux +0: ana clock +1: ahb clock + 8 + 1 + read-write + + + + + 2 + 0x4 + clk_top_i2s0,clk_top_i2s1 + I2SCLK[%s] + no description available + 0x1c10 + 32 + 0x00000000 + 0xD0000100 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux +0: aud clock 0 +1: aud clock 1 + 8 + 1 + read-write + + + + + global00 + Clock senario + 0x2000 + 32 + 0x00000000 + 0x0000000F + + + MUX + global clock override request +bit0: override to preset0 +bit1: override to preset1 +bit2: override to preset2 +bit3: override to preset3 + 0 + 4 + read-write + + + + + 4 + 0x20 + slice0,slice1,slice2,slice3 + MONITOR[%s] + no description available + 0x2400 + + control + Clock measure and monitor control + 0x0 + 32 + 0x00000000 + 0x89FFD7FF + + + VALID + result is ready for read +0: not ready +1: result is ready + 31 + 1 + read-write + + + DIV_BUSY + divider is applying new setting + 27 + 1 + read-only + + + OUTEN + enable clock output + 24 + 1 + read-write + + + DIV + output divider + 16 + 8 + read-write + + + HIGH + clock frequency higher than upper limit + 15 + 1 + read-write + + + LOW + clock frequency lower than lower limit + 14 + 1 + read-write + + + START + start measurement + 12 + 1 + read-write + + + MODE + work mode, +0: register value will be compared to measurement +1: upper and lower value will be recordered in register + 10 + 1 + read-write + + + ACCURACY + measurement accuracy, +0: resolution is 1kHz +1: resolution is 1Hz + 9 + 1 + read-write + + + REFERENCE + reference clock selection, +0: 32k +1: 24M + 8 + 1 + read-write + + + SELECTION + clock measurement selection + 0 + 8 + read-write + + + + + current + Clock measure result + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + self updating measure result + 0 + 32 + read-only + + + + + low_limit + Clock lower limit + 0x8 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + FREQUENCY + lower frequency + 0 + 32 + read-write + + + + + high_limit + Clock upper limit + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + upper frequency + 0 + 32 + read-write + + + + + + 1 + 0x400 + cpu0 + CPU[%s] + no description available + 0x2800 + + LP + CPU0 LP control + 0x0 + 32 + 0x00001000 + 0xFF013703 + + + WAKE_CNT + CPU0 wake up counter, counter satuated at 255, write 0x00 to clear + 24 + 8 + read-write + + + HALT + halt request for CPU0, +0: CPU0 will start to execute after reset or receive wakeup request +1: CPU0 will not start after reset, or wakeup after WFI + 16 + 1 + read-write + + + WAKE + CPU0 is waking up +0: CPU0 wake up not asserted +1: CPU0 wake up asserted + 13 + 1 + read-only + + + EXEC + CPU0 is executing +0: CPU0 is not executing +1: CPU0 is executing + 12 + 1 + read-only + + + WAKE_FLAG + CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit +0: CPU0 wakeup not happened +1: CPU0 wake up happened + 10 + 1 + read-write + + + SLEEP_FLAG + CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit +0: CPU0 sleep not happened +1: CPU0 sleep happened + 9 + 1 + read-write + + + RESET_FLAG + CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit +0: CPU0 reset not happened +1: CPU0 reset happened + 8 + 1 + read-write + + + MODE + Low power mode, system behavior after WFI +00: CPU clock stop after WFI +01: System enter low power mode after WFI +10: Keep running after WFI +11: reserved + 0 + 2 + read-write + + + + + LOCK + CPU0 Lock GPR + 0x4 + 32 + 0x00000002 + 0x0000FFFE + + + GPR + Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset + 2 + 14 + read-write + + + LOCK + Lock bit for CPU_LOCK + 1 + 1 + read-write + + + + + 14 + 0x4 + GPR0,GPR1,GPR2,GPR3,GPR4,GPR5,GPR6,GPR7,GPR8,GPR9,GPR10,GPR11,GPR12,GPR13 + GPR[%s] + no description available + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + 4 + 0x4 + STATUS0,STATUS1,STATUS2,STATUS3 + WAKEUP_STATUS[%s] + no description available + 0x40 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + 4 + 0x4 + ENABLE0,ENABLE1,ENABLE2,ENABLE3 + WAKEUP_ENABLE[%s] + no description available + 0x80 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + + + + IOC + IOC + IOC + 0xf4040000 + + 0x0 + 0xf40 + registers + + + + 488 + 0x8 + pa00,pa01,pa02,pa03,pa04,pa05,pa06,pa07,pa08,pa09,pa10,pa11,pa12,pa13,pa14,pa15,pa16,pa17,pa18,pa19,pa20,pa21,pa22,pa23,pa24,pa25,pa26,pa27,pa28,pa29,pa30,pa31,pb00,pb01,pb02,pb03,pb04,pb05,pb06,pb07,pb08,pb09,pb10,pb11,pb12,pb13,pb14,pb15,pb16,pb17,pb18,pb19,pb20,pb21,pb22,pb23,pb24,pb25,pb26,pb27,pb28,pb29,pb30,pb31,pc00,pc01,pc02,pc03,pc04,pc05,pc06,pc07,pc08,pc09,pc10,pc11,pc12,pc13,pc14,pc15,pc16,pc17,pc18,pc19,pc20,pc21,pc22,pc23,pc24,pc25,pc26,pc27,rsv92,rsv93,rsv94,rsv95,rsv96,rsv97,rsv98,rsv99,rsv100,rsv101,rsv102,rsv103,rsv104,rsv105,rsv106,rsv107,rsv108,rsv109,rsv110,rsv111,rsv112,rsv113,rsv114,rsv115,rsv116,rsv117,rsv118,rsv119,rsv120,rsv121,rsv122,rsv123,rsv124,rsv125,rsv126,rsv127,rsv128,rsv129,rsv130,rsv131,rsv132,rsv133,rsv134,rsv135,rsv136,rsv137,rsv138,rsv139,rsv140,rsv141,rsv142,rsv143,rsv144,rsv145,rsv146,rsv147,rsv148,rsv149,rsv150,rsv151,rsv152,rsv153,rsv154,rsv155,rsv156,rsv157,rsv158,rsv159,rsv160,rsv161,rsv162,rsv163,rsv164,rsv165,rsv166,rsv167,rsv168,rsv169,rsv170,rsv171,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,rsv256,rsv257,rsv258,rsv259,rsv260,rsv261,rsv262,rsv263,rsv264,rsv265,rsv266,rsv267,rsv268,rsv269,rsv270,rsv271,rsv272,rsv273,rsv274,rsv275,rsv276,rsv277,rsv278,rsv279,rsv280,rsv281,rsv282,rsv283,rsv284,rsv285,rsv286,rsv287,rsv288,rsv289,rsv290,rsv291,rsv292,rsv293,rsv294,rsv295,rsv296,rsv297,rsv298,rsv299,rsv300,rsv301,rsv302,rsv303,rsv304,rsv305,rsv306,rsv307,rsv308,rsv309,rsv310,rsv311,rsv312,rsv313,rsv314,rsv315,rsv316,rsv317,rsv318,rsv319,rsv320,rsv321,rsv322,rsv323,rsv324,rsv325,rsv326,rsv327,rsv328,rsv329,rsv330,rsv331,rsv332,rsv333,rsv334,rsv335,rsv336,rsv337,rsv338,rsv339,rsv340,rsv341,rsv342,rsv343,rsv344,rsv345,rsv346,rsv347,rsv348,rsv349,rsv350,rsv351,rsv352,rsv353,rsv354,rsv355,rsv356,rsv357,rsv358,rsv359,rsv360,rsv361,rsv362,rsv363,rsv364,rsv365,rsv366,rsv367,rsv368,rsv369,rsv370,rsv371,rsv372,rsv373,rsv374,rsv375,rsv376,rsv377,rsv378,rsv379,rsv380,rsv381,rsv382,rsv383,rsv384,rsv385,rsv386,rsv387,rsv388,rsv389,rsv390,rsv391,rsv392,rsv393,rsv394,rsv395,rsv396,rsv397,rsv398,rsv399,rsv400,rsv401,rsv402,rsv403,rsv404,rsv405,rsv406,rsv407,rsv408,rsv409,rsv410,rsv411,rsv412,rsv413,rsv414,rsv415,px00,px01,px02,px03,px04,px05,px06,px07,rsv424,rsv425,rsv426,rsv427,rsv428,rsv429,rsv430,rsv431,rsv432,rsv433,rsv434,rsv435,rsv436,rsv437,rsv438,rsv439,rsv440,rsv441,rsv442,rsv443,rsv444,rsv445,rsv446,rsv447,py00,py01,py02,py03,py04,py05,py06,py07,rsv456,rsv457,rsv458,rsv459,rsv460,rsv461,rsv462,rsv463,rsv464,rsv465,rsv466,rsv467,rsv468,rsv469,rsv470,rsv471,rsv472,rsv473,rsv474,rsv475,rsv476,rsv477,rsv478,rsv479,pz00,pz01,pz02,pz03,pz04,pz05,pz06,pz07 + PAD[%s] + no description available + 0x0 + + FUNC_CTL + ALT SELECT + 0x0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_CTL + PAD SETTINGS + 0x4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + + + + PIOC + PIOC + IOC + 0xf40d8000 + + + BIOC + BIOC + IOC + 0xf5010000 + + + OTPSHW + OTPSHW + OTP + 0xf4080000 + + 0x0 + 0xc08 + registers + + + + 128 + 0x4 + SHADOW000,SHADOW001,SHADOW002,SHADOW003,SHADOW004,SHADOW005,SHADOW006,SHADOW007,SHADOW008,SHADOW009,SHADOW010,SHADOW011,SHADOW012,SHADOW013,SHADOW014,SHADOW015,SHADOW016,SHADOW017,SHADOW018,SHADOW019,SHADOW020,SHADOW021,SHADOW022,SHADOW023,SHADOW024,SHADOW025,SHADOW026,SHADOW027,SHADOW028,SHADOW029,SHADOW030,SHADOW031,SHADOW032,SHADOW033,SHADOW034,SHADOW035,SHADOW036,SHADOW037,SHADOW038,SHADOW039,SHADOW040,SHADOW041,SHADOW042,SHADOW043,SHADOW044,SHADOW045,SHADOW046,SHADOW047,SHADOW048,SHADOW049,SHADOW050,SHADOW051,SHADOW052,SHADOW053,SHADOW054,SHADOW055,SHADOW056,SHADOW057,SHADOW058,SHADOW059,SHADOW060,SHADOW061,SHADOW062,SHADOW063,SHADOW064,SHADOW065,SHADOW066,SHADOW067,SHADOW068,SHADOW069,SHADOW070,SHADOW071,SHADOW072,SHADOW073,SHADOW074,SHADOW075,SHADOW076,SHADOW077,SHADOW078,SHADOW079,SHADOW080,SHADOW081,SHADOW082,SHADOW083,SHADOW084,SHADOW085,SHADOW086,SHADOW087,SHADOW088,SHADOW089,SHADOW090,SHADOW091,SHADOW092,SHADOW093,SHADOW094,SHADOW095,SHADOW096,SHADOW097,SHADOW098,SHADOW099,SHADOW100,SHADOW101,SHADOW102,SHADOW103,SHADOW104,SHADOW105,SHADOW106,SHADOW107,SHADOW108,SHADOW109,SHADOW110,SHADOW111,SHADOW112,SHADOW113,SHADOW114,SHADOW115,SHADOW116,SHADOW117,SHADOW118,SHADOW119,SHADOW120,SHADOW121,SHADOW122,SHADOW123,SHADOW124,SHADOW125,SHADOW126,SHADOW127 + SHADOW[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + 8 + 0x4 + LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 + SHADOW_LOCK[%s] + no description available + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + 128 + 0x4 + FUSE000,FUSE001,FUSE002,FUSE003,FUSE004,FUSE005,FUSE006,FUSE007,FUSE008,FUSE009,FUSE010,FUSE011,FUSE012,FUSE013,FUSE014,FUSE015,FUSE016,FUSE017,FUSE018,FUSE019,FUSE020,FUSE021,FUSE022,FUSE023,FUSE024,FUSE025,FUSE026,FUSE027,FUSE028,FUSE029,FUSE030,FUSE031,FUSE032,FUSE033,FUSE034,FUSE035,FUSE036,FUSE037,FUSE038,FUSE039,FUSE040,FUSE041,FUSE042,FUSE043,FUSE044,FUSE045,FUSE046,FUSE047,FUSE048,FUSE049,FUSE050,FUSE051,FUSE052,FUSE053,FUSE054,FUSE055,FUSE056,FUSE057,FUSE058,FUSE059,FUSE060,FUSE061,FUSE062,FUSE063,FUSE064,FUSE065,FUSE066,FUSE067,FUSE068,FUSE069,FUSE070,FUSE071,FUSE072,FUSE073,FUSE074,FUSE075,FUSE076,FUSE077,FUSE078,FUSE079,FUSE080,FUSE081,FUSE082,FUSE083,FUSE084,FUSE085,FUSE086,FUSE087,FUSE088,FUSE089,FUSE090,FUSE091,FUSE092,FUSE093,FUSE094,FUSE095,FUSE096,FUSE097,FUSE098,FUSE099,FUSE100,FUSE101,FUSE102,FUSE103,FUSE104,FUSE105,FUSE106,FUSE107,FUSE108,FUSE109,FUSE110,FUSE111,FUSE112,FUSE113,FUSE114,FUSE115,FUSE116,FUSE117,FUSE118,FUSE119,FUSE120,FUSE121,FUSE122,FUSE123,FUSE124,FUSE125,FUSE126,FUSE127 + FUSE[%s] + no description available + 0x400 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + 8 + 0x4 + LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 + FUSE_LOCK[%s] + no description available + 0x600 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + UNLOCK + UNLOCK + 0x800 + 32 + 0x00000000 + 0xFFFFFFFF + + + UNLOCK + unlock word for fuse array operation +write "OPEN" to unlock fuse array, write any other value will lock write to fuse. +Please make sure 24M crystal is running and 2.5V LDO working properly + 0 + 32 + read-write + + + + + DATA + DATA + 0x804 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + data register for non-blocking access +this register hold dat read from fuse array or data to by programmed to fuse array + 0 + 32 + read-write + + + + + ADDR + ADDR + 0x808 + 32 + 0x00000000 + 0x0000007F + + + ADDR + word address to be read or write + 0 + 7 + read-write + + + + + CMD + CMD + 0x80c + 32 + 0x00000000 + 0xFFFFFFFF + + + CMD + command to access fure array +"BLOW" will update fuse word at ADDR to value hold in DATA +"READ" will fetch fuse value in at ADDR to DATA register + 0 + 32 + read-write + + + + + LOAD_REQ + LOAD Request + 0xa00 + 32 + 0x00000007 + 0x0000000F + + + REQUEST + reload request for 4 regions +bit0: region0 +bit1: region1 +bit2: region2 +bit3: region3 + 0 + 4 + read-write + + + + + LOAD_COMP + LOAD complete + 0xa04 + 32 + 0x00000007 + 0x0000000F + + + COMPLETE + reload complete sign for 4 regions +bit0: region 0 +bit1: region1 +bit2: region2 +bit3: region3 + 0 + 4 + read-write + + + + + 4 + 0x4 + LOAD_REGION0,LOAD_REGION1,LOAD_REGION2,LOAD_REGION3 + REGION[%s] + no description available + 0xa20 + 32 + 0x00000800 + 0x00007F7F + + + STOP + stop address of load region, fuse word at end address will NOT be reloaded +region0: fixed at 8 +region1: fixed at 16 +region2: fixed at 0, +region3: usrer configurable + 8 + 7 + read-write + + + START + start address of load region, fuse word at start address will be reloaded +region0: fixed at 0 +region1: fixed at 8 +region2: fixed at 16, +region3: usrer configurable + 0 + 7 + read-write + + + + + INT_FLAG + interrupt flag + 0xc00 + 32 + 0x00000000 + 0x00000007 + + + WRITE + fuse write flag, write 1 to clear +0: fuse is not written or writing +1: value in DATA register is programmed into fuse + 2 + 1 + read-write + + + READ + fuse read flag, write 1 to clear +0: fuse is not read or reading +1: fuse value is put in DATA register + 1 + 1 + read-write + + + LOAD + fuse load flag, write 1 to clear +0: fuse is not loaded or loading +1: fuse loaded + 0 + 1 + read-write + + + + + INT_EN + interrupt enable + 0xc04 + 32 + 0x00000000 + 0x00000007 + + + WRITE + fuse write interrupt enable +0: fuse write interrupt is not enable +1: fuse write interrupt is enable + 2 + 1 + read-write + + + READ + fuse read interrupt enable +0: fuse read interrupt is not enable +1: fuse read interrupt is enable + 1 + 1 + read-write + + + LOAD + fuse load interrupt enable +0: fuse load interrupt is not enable +1: fuse load interrupt is enable + 0 + 1 + read-write + + + + + + + OTP + OTP + OTP + 0xf40c8000 + + + PPOR + PPOR + PPOR + 0xf40c0000 + + 0x0 + 0x20 + registers + + + + RESET_FLAG + flag indicate reset source + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FLAG + reset reason of last hard reset, write 1 to clear each bit +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + write-only + + + + + RESET_STATUS + reset source status + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + current status of reset sources +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + read-write + + + + + RESET_HOLD + reset hold attribute + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + read-write + + + + + RESET_ENABLE + reset source enable + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + enable of reset sources +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + read-write + + + + + RESET_HOT + reset type triggered by reset + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + TYPE + reset type of reset sources, 0 for cold/warm reset, all system control setting cleared including clock, ioc; 1 for hot reset, system control, ioc setting kept, peripheral setting cleared. +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + read-write + + + + + RESET_COLD + reset type attribute + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + FLAG + perform cold or warm reset of chip, 0 for warm reset, fuse value and debug connection preserved; 1 for cold reset, fuse value reloaded and debug connection corrupted. This bit is ignored when hot reset selected +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + read-write + + + + + SOFTWARE_RESET + Software reset counter + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset + 0 + 32 + read-write + + + + + + + PCFG + PCFG + PMU + 0xf40c4000 + + 0x0 + 0x70 + registers + + + + BANDGAP + BANGGAP control + 0x0 + 32 + 0x00101010 + 0x831F1F1F + + + VBG_TRIMMED + Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: bandgap is not trimmed +1: bandgap is trimmed + 31 + 1 + read-write + + + LOWPOWER_MODE + Banggap work in low power mode, banggap function limited +0: banggap works in normal mode +1: banggap works in low power mode + 25 + 1 + read-write + + + POWER_SAVE + Banggap work in power save mode, banggap function normally +0: banggap works in high performance mode +1: banggap works in power saving mode + 24 + 1 + read-write + + + VBG_1P0_TRIM + Banggap 1.0V output trim value + 16 + 5 + read-write + + + VBG_P65_TRIM + Banggap 1.0V output trim value + 8 + 5 + read-write + + + VBG_P50_TRIM + Banggap 1.0V output trim value + 0 + 5 + read-write + + + + + LDO1P1 + 1V LDO config + 0x4 + 32 + 0x0000044C + 0x00000FFF + + + VOLT + LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. +700: 700mV +720: 720mV +. . . +1320:1320mV + 0 + 12 + read-write + + + + + LDO2P5 + 2.5V LDO config + 0x8 + 32 + 0x000009C4 + 0x10010FFF + + + READY + Ready flag, will set 1ms after enabled or voltage change +0: LDO is not ready for use +1: LDO is ready + 28 + 1 + read-only + + + ENABLE + LDO enable +0: turn off LDO +1: turn on LDO + 16 + 1 + read-write + + + VOLT + LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. +2125: 2125mV +2150: 2150mV +. . . +2900:2900mV + 0 + 12 + read-write + + + + + DCDC_MODE + DCDC mode select + 0x10 + 32 + 0x00B010B0 + 0x10070FFF + + + READY + Ready flag +0: DCDC is applying new change +1: DCDC is ready + 28 + 1 + read-only + + + MODE + DCDC work mode +XX0: turn off +001: basic mode +011: generic mode +101: automatic mode +111: expert mode + 16 + 3 + read-write + + + VOLT + DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. +600: 600mV +625: 625mV +. . . +1375:1375mV + 0 + 12 + read-write + + + + + DCDC_LPMODE + DCDC low power mode + 0x14 + 32 + 0x00B010B0 + 0x00000FFF + + + STBY_VOLT + DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. +600: 600mV +625: 625mV +. . . +1375:1375mV + 0 + 12 + read-write + + + + + DCDC_PROT + DCDC protection + 0x18 + 32 + 0x00000000 + 0x11818191 + + + ILIMIT_LP + over current setting for low power mode +0:250mA +1:200mA + 28 + 1 + read-write + + + OVERLOAD_LP + over current in low power mode +0: current is below setting +1: overcurrent happened in low power mode + 24 + 1 + read-only + + + DISABLE_POWER_LOSS + disable power loss protection +0: power loss protection enabled, DCDC shuts down when power loss +1: power loss protection disabled, DCDC try working after power voltage drop + 23 + 1 + read-write + + + POWER_LOSS_FLAG + power loss +0: input power is good +1: input power is too low + 16 + 1 + read-only + + + DISABLE_OVERVOLTAGE + output over voltage protection +0: protection enabled, DCDC will shut down is output voltage is unexpected high +1: protection disabled, DCDC continue to adjust output voltage + 15 + 1 + read-write + + + OVERVOLT_FLAG + output over voltage flag +0: output is normal +1: output is unexpected high + 8 + 1 + read-only + + + DISABLE_SHORT + disable output short circuit protection +0: short circuits protection enabled, DCDC shut down if short circuit on output detected +1: short circuit protection disabled + 7 + 1 + read-write + + + SHORT_CURRENT + short circuit current setting +0: 2.0A, +1: 1.3A + 4 + 1 + read-write + + + SHORT_FLAG + short circuit flag +0: current is within limit +1: short circuits detected + 0 + 1 + read-only + + + + + DCDC_CURRENT + DCDC current estimation + 0x1c + 32 + 0x00000000 + 0x0000811F + + + ESTI_EN + enable current measure + 15 + 1 + read-write + + + VALID + Current level valid +0: data is invalid +1: data is valid + 8 + 1 + read-only + + + LEVEL + DCDC current level, current level is num * 50mA + 0 + 5 + read-only + + + + + DCDC_ADVMODE + DCDC advance setting + 0x20 + 32 + 0x00EF1C6E + 0x073F006F + + + EN_RCSCALE + Enable RC scale + 24 + 3 + read-write + + + DC_C + Loop C number + 20 + 2 + read-write + + + DC_R + Loop R number + 16 + 4 + read-write + + + EN_FF_DET + enable feed forward detect +0: feed forward detect is disabled +1: feed forward detect is enabled + 6 + 1 + read-write + + + EN_FF_LOOP + enable feed forward loop +0: feed forward loop is disabled +1: feed forward loop is enabled + 5 + 1 + read-write + + + EN_DCM_EXIT + avoid over voltage +0: stay in DCM mode when voltage excess +1: change to CCM mode when voltage excess + 3 + 1 + read-write + + + EN_SKIP + enable skip on narrow pulse +0: do not skip narrow pulse +1: skip narrow pulse + 2 + 1 + read-write + + + EN_IDLE + enable skip when voltage is higher than threshold +0: do not skip +1: skip if voltage is excess + 1 + 1 + read-write + + + EN_DCM + DCM mode +0: CCM mode +1: DCM mode + 0 + 1 + read-write + + + + + DCDC_ADVPARAM + DCDC advance parameter + 0x24 + 32 + 0x00EF1C6E + 0x00007F7F + + + MIN_DUT + minimum duty cycle + 8 + 7 + read-write + + + MAX_DUT + maximum duty cycle + 0 + 7 + read-write + + + + + DCDC_MISC + DCDC misc parameter + 0x28 + 32 + 0x00070100 + 0x13170317 + + + EN_HYST + hysteres enable + 28 + 1 + read-write + + + HYST_SIGN + hysteres sign + 25 + 1 + read-write + + + HYST_THRS + hysteres threshold + 24 + 1 + read-write + + + RC_SCALE + Loop RC scale threshold + 20 + 1 + read-write + + + DC_FF + Loop feed forward number + 16 + 3 + read-write + + + OL_THRE + overload for threshold for lod power mode + 8 + 2 + read-write + + + OL_HYST + current hysteres range +0: 12.5mV +1: 25mV + 4 + 1 + read-write + + + DELAY + enable delay +0: delay disabled, +1: delay enabled + 2 + 1 + read-write + + + CLK_SEL + clock selection +0: select DCDC internal oscillator +1: select RC24M oscillator + 1 + 1 + read-write + + + EN_STEP + enable stepping in voltage change +0: stepping disabled, +1: steping enabled + 0 + 1 + read-write + + + + + DCDC_DEBUG + DCDC Debug + 0x2c + 32 + 0x00005DBF + 0x000FFFFF + + + UPDATE_TIME + DCDC voltage change time in 24M clock cycles, default value is 1mS + 0 + 20 + read-write + + + + + DCDC_START_TIME + DCDC ramp time + 0x30 + 32 + 0x0001193F + 0x000FFFFF + + + START_TIME + Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS + 0 + 20 + read-write + + + + + DCDC_RESUME_TIME + DCDC resume time + 0x34 + 32 + 0x00008C9F + 0x000FFFFF + + + RESUME_TIME + Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS + 0 + 20 + read-write + + + + + POWER_TRAP + SOC power trap + 0x40 + 32 + 0x00000000 + 0x80010001 + + + TRIGGERED + Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. +0: low power trap is not triggered +1: low power trap triggered + 31 + 1 + read-write + + + RETENTION + DCDC enter standby mode, which will reduce voltage for memory content retention +0: Shutdown DCDC +1: reduce DCDC voltage + 16 + 1 + read-write + + + TRAP + Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered +0: trap not enabled, pmic side low power function disabled +1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. + 0 + 1 + read-write + + + + + WAKE_CAUSE + Wake up source + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAUSE + wake up cause, each bit represents one wake up source, write 1 to clear the register bit +0: wake up source is not active during last wakeup +1: wake up source is active furing last wakeup +bit 0: pmic_enable +bit 1: debug wakeup +bit 4: fuse interrupt +bit 7: UART interrupt +bit 8: TMR interrupt +bit 9: WDG interrupt +bit10: GPIO in PMIC interrupt +bit11: Security monitor interrupt +bit12: Security in PMIC event +bit16: Security violation in BATT +bit17: GPIO in BATT interrupt +bit18: BATT Button interrupt +bit19: RTC alarm interrupt + 0 + 32 + read-write + + + + + WAKE_MASK + Wake up mask + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + MASK + mask for wake up sources, each bit represents one wakeup source +0: allow source to wake up system +1: disallow source to wakeup system +bit 0: pmic_enable +bit 1: debug wakeup +bit 4: fuse interrupt +bit 7: UART interrupt +bit 8: TMR interrupt +bit 9: WDG interrupt +bit10: GPIO in PMIC interrupt +bit11: Security monitor interrupt +bit12: Security in PMIC event +bit16: Security violation in BATT +bit17: GPIO in BATT interrupt +bit18: BATT Button interrupt +bit19: RTC alarm interrupt + 0 + 32 + read-write + + + + + SCG_CTRL + Clock gate control in PMIC + 0x4c + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + SCG + control whether clock being gated during PMIC low power flow, 2 bits for each peripheral +00,01: reserved +10: clock is always off +11: clock is always on +bit0-1: fuse +bit2-3: sram +bit4-5: vad +bit6-7:gpio +bit8-9:ioc +bit10-11: timer +bit12-13:wdog +bit14-15:uart +bit16-17:debug + 0 + 32 + read-write + + + + + DEBUG_STOP + Debug stop config + 0x50 + 32 + 0x00000001 + 0x00000003 + + + CPU1 + Stop peripheral when CPU1 enter debug mode +0: peripheral keep running when CPU1 in debug mode +1: peripheral enter debug mode when CPU1 enter debug + 1 + 1 + read-write + + + CPU0 + Stop peripheral when CPU0 enter debug mode +0: peripheral keep running when CPU0 in debug mode +1: peripheral enter debug mode when CPU0 enter debug + 0 + 1 + read-write + + + + + RC24M + RC 24M config + 0x60 + 32 + 0x00000316 + 0x8000071F + + + RC_TRIMMED + RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: RC is not trimmed +1: RC is trimmed + 31 + 1 + read-write + + + TRIM_C + Coarse trim for RC24M, bigger value means faster + 8 + 3 + read-write + + + TRIM_F + Fine trim for RC24M, bigger value means faster + 0 + 5 + read-write + + + + + RC24M_TRACK + RC 24M track mode + 0x64 + 32 + 0x00000000 + 0x00010011 + + + SEL24M + Select track reference +0: select 32K as reference +1: select 24M XTAL as reference + 16 + 1 + read-write + + + RETURN + Retrun default value when XTAL loss +0: remain last tracking value +1: switch to default value + 4 + 1 + read-write + + + TRACK + track mode +0: RC24M free running +1: track RC24M to external XTAL + 0 + 1 + read-write + + + + + TRACK_TARGET + RC 24M track target + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRE_DIV + Divider for reference source + 16 + 16 + read-write + + + TARGET + Target frequency multiplier of divided source + 0 + 16 + read-write + + + + + STATUS + RC 24M track status + 0x6c + 32 + 0x00000000 + 0x0011871F + + + SEL32K + track is using XTAL32K +0: track is not using XTAL32K +1: track is using XTAL32K + 20 + 1 + read-only + + + SEL24M + track is using XTAL24M +0: track is not using XTAL24M +1: track is using XTAL24M + 16 + 1 + read-only + + + EN_TRIM + default value takes effect +0: default value is invalid +1: default value is valid + 15 + 1 + read-only + + + TRIM_C + default coarse trim value + 8 + 3 + read-only + + + TRIM_F + default fine trim value + 0 + 5 + read-only + + + + + + + PSEC + PSEC + PSEC + 0xf40cc000 + + 0x0 + 0x18 + registers + + + + SECURE_STATE + Secure state + 0x0 + 32 + 0x00000000 + 0x000300F0 + + + ALLOW_NSC + Non-secure state allow +0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter non-secure state + 17 + 1 + read-only + + + ALLOW_SEC + Secure state allow +0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter secure state + 16 + 1 + read-only + + + PMIC_FAIL + PMIC secure state one hot indicator +0: secure state is not in fail state +1: secure state is in fail state + 7 + 1 + read-write + + + PMIC_NSC + PMIC secure state one hot indicator +0: secure state is not in non-secure state +1: secure state is in non-secure state + 6 + 1 + read-write + + + PMIC_SEC + PMIC secure state one hot indicator +0: secure state is not in secure state +1: secure state is in secure state + 5 + 1 + read-write + + + PMIC_INS + PMIC secure state one hot indicator +0: secure state is not in inspect state +1: secure state is in inspect state + 4 + 1 + read-write + + + + + SECURE_STATE_CONFIG + secure state configuration + 0x4 + 32 + 0x00000000 + 0x00000009 + + + LOCK + Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset +0: not locked, register can be modified +1: register locked, write access to the register is ignored + 3 + 1 + read-write + + + ALLOW_RESTART + allow secure state restart from fail state +0: restart is not allowed, only hardware reset can recover secure state +1: software is allowed to switch to inspect state from fail state + 0 + 1 + read-write + + + + + VIOLATION_CONFIG + Security violation config + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 0 + 15 + read-write + + + + + ESCALATE_CONFIG + Escalate behavior on security event + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 0 + 15 + read-write + + + + + EVENT + Event and escalate status + 0x10 + 32 + 0x00000000 + 0xFFFF000C + + + EVENT + local event statue, each bit represents one security event + 16 + 16 + read-only + + + PMIC_ESC_NSC + PMIC is escalating non-secure event + 3 + 1 + read-only + + + PMIC_ESC_SEC + PMIC is escalting secure event + 2 + 1 + read-only + + + + + LIFECYCLE + Lifecycle + 0x14 + 32 + 0x00000000 + 0x000000FF + + + LIFECYCLE + lifecycle status, +bit7: lifecycle_debate, +bit6: lifecycle_scribe, +bit5: lifecycle_no_ret, +bit4: lifecycle_return, +bit3: lifecycle_secure, +bit2: lifecycle_nonsec, +bit1: lifecycle_create, +bit0: lifecycle_unknow + 0 + 8 + read-only + + + + + + + PMON + PMON + PMON + 0xf40d0000 + + 0x0 + 0x48 + registers + + + + 4 + 0x8 + glitch0,glitch1,clock0,clock1 + MONITOR[%s] + no description available + 0x0 + + CONTROL + Glitch and clock monitor control + 0x0 + 32 + 0x00000000 + 0x00000011 + + + ACTIVE + select glitch works in active mode or passve mode. +0: passive mode, depends on power glitch destroy DFF value +1: active mode, check glitch by DFF chain + 4 + 1 + read-write + + + ENABLE + enable glitch detector +0: detector disabled +1: detector enabled + 0 + 1 + read-write + + + + + STATUS + Glitch and clock monitor status + 0x4 + 32 + 0x00000000 + 0x00000001 + + + FLAG + flag for glitch detected, write 1 to clear this flag +0: glitch not detected +1: glitch detected + 0 + 1 + read-write + + + + + + IRQ_FLAG + No description available + 0x40 + 32 + 0x00000000 + 0x0000000F + + + FLAG + interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag +0: no monitor interrupt +1: monitor interrupt happened + 0 + 4 + read-write + + + + + IRQ_ENABLE + No description available + 0x44 + 32 + 0x00000000 + 0x0000000F + + + ENABLE + interrupt enable, each bit represents for one monitor +0: monitor interrupt disabled +1: monitor interrupt enabled + 0 + 4 + read-write + + + + + + + PGPR + PGPR + PGPR + 0xf40d4000 + + 0x0 + 0x40 + registers + + + + PMIC_GPR00 + Generic control + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR01 + Generic control + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR02 + Generic control + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR03 + Generic control + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR04 + Generic control + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR05 + Generic control + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR06 + Generic control + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR07 + Generic control + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR08 + Generic control + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR09 + Generic control + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR10 + Generic control + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR11 + Generic control + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR12 + Generic control + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR13 + Generic control + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR14 + Generic control + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR15 + Generic control + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + + + PLLCTLV2 + PLLCTLV2 + PLLCTLV2 + 0xf4100000 + + 0x0 + 0x200 + registers + + + + XTAL + OSC configuration + 0x0 + 32 + 0x0001FFFF + 0xB00FFFFF + + + BUSY + Busy flag +0: Oscillator is working or shutdown +1: Oscillator is changing status + 31 + 1 + read-only + + + RESPONSE + Crystal oscillator status +0: Oscillator is not stable +1: Oscillator is stable for use + 29 + 1 + read-only + + + ENABLE + Crystal oscillator enable status +0: Oscillator is off +1: Oscillator is on + 28 + 1 + read-only + + + RAMP_TIME + Rampup time of XTAL oscillator in cycles of RC24M clock +0: 0 cycle +1: 1 cycle +2: 2 cycle +1048575: 1048575 cycles + 0 + 20 + read-write + + + + + 3 + 0x80 + pll0,pll1,pll2 + PLL[%s] + no description available + 0x80 + + MFI + PLL0 multiple register + 0x0 + 32 + 0x00000010 + 0xB000007F + + + BUSY + Busy flag +0: PLL is stable or shutdown +1: PLL is changing status + 31 + 1 + read-only + + + RESPONSE + PLL status +0: PLL is not stable +1: PLL is stable for use + 29 + 1 + read-only + + + ENABLE + PLL enable status +0: PLL is off +1: PLL is on + 28 + 1 + read-only + + + MFI + loop back divider of PLL, support from 13 to 42, f=fref*(mfi + mfn/mfd) +0-15: invalid +16: divide by 16 +17: divide by17 +. . . +42: divide by 42 +43~:invalid + 0 + 7 + read-write + + + + + MFN + PLL0 fraction numerator register + 0x4 + 32 + 0x09896800 + 0x3FFFFFFF + + + MFN + Numeratorof fractional part,f=fref*(mfi + mfn/mfd). This field supports changing while running. + 0 + 30 + read-write + + + + + MFD + PLL0 fraction demoninator register + 0x8 + 32 + 0x0E4E1C00 + 0x3FFFFFFF + + + MFD + Demoninator of fraction part,f=fref*(mfi + mfn/mfd). This field should not be changed during PLL enabled. If changed, change will take efftect when PLL re-enabled. + 0 + 30 + read-write + + + + + SS_STEP + PLL0 spread spectrum step register + 0xc + 32 + 0x00000000 + 0x3FFFFFFF + + + STEP + Step of spread spectrum modulator. +This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. + 0 + 30 + read-write + + + + + SS_STOP + PLL0 spread spectrum stop register + 0x10 + 32 + 0x00000000 + 0x3FFFFFFF + + + STOP + Stop point of spread spectrum modulator +This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. + 0 + 30 + read-write + + + + + CONFIG + PLL0 confguration register + 0x14 + 32 + 0x00000000 + 0x00000101 + + + SPREAD + Enable spread spectrum function. This field supports changing during PLL running. + 8 + 1 + read-write + + + REFSEL + Select reference clock, This filed support changing while running, but application must take frequency error and jitter into consideration. And if MFN changed before reference switch, application need make sure time is enough for MFN updating. +0: XTAL24M +1: IRC24M + 0 + 1 + read-write + + + + + LOCKTIME + PLL0 lock time register + 0x18 + 32 + 0x000009C4 + 0x0000FFFF + + + LOCKTIME + Lock time of PLL in 24M clock cycles, typical value is 2500. If MFI changed during PLL startup, PLL lock time may be longer than this setting. + 0 + 16 + read-write + + + + + STEPTIME + PLL0 step time register + 0x1c + 32 + 0x000009C4 + 0x0000FFFF + + + STEPTIME + Step time for MFI on-the-fly change in 24M clock cycles, typical value is 2500. + 0 + 16 + read-write + + + + + ADVANCED + PLL0 advance configuration register + 0x20 + 32 + 0x00000000 + 0x11000000 + + + SLOW + Use slow lock flow, PLL lock expendite is disabled. This mode might be stabler. And software need config LOCKTIME field accordingly. +0: fast lock enabled, lock time is 100us +1: fast lock disabled, lock time is 400us + 28 + 1 + read-write + + + DITHER + Enable dither function + 24 + 1 + read-write + + + + + 3 + 0x4 + DIV0,DIV1,DIV2 + DIV[%s] + no description available + 0x40 + 32 + 0x00000000 + 0xB000003F + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Divider response status +0: Divider is not stable +1: Divider is stable for use + 29 + 1 + read-only + + + ENABLE + Divider enable status +0: Divider is off +1: Divider is on + 28 + 1 + read-only + + + DIV + Divider factor, divider factor is DIV/5 + 1 +0: divide by 1 +1: divide by 1.2 +2: divide by 1.4 +. . . +63: divide by 13.6 + 0 + 6 + read-write + + + + + + + + TSNS + TSNS + TSNS + 0xf4104000 + + 0x0 + 0x3c + registers + + + + T + Temperature + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Signed number of temperature in 256 x celsius degree + 0 + 32 + read-only + + + + + TMAX + Maximum Temperature + 0x4 + 32 + 0xFF800000 + 0xFFFFFFFF + + + T + maximum temperature ever found + 0 + 32 + read-only + + + + + TMIN + Minimum Temperature + 0x8 + 32 + 0x007FFFFF + 0xFFFFFFFF + + + T + minimum temperature ever found + 0 + 32 + read-only + + + + + AGE + Sample age + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + AGE + age of T register in 24MHz clock cycles + 0 + 32 + read-only + + + + + STATUS + Status + 0x10 + 32 + 0x00000000 + 0x80000001 + + + VALID + indicate value in T is valid or not +0: not valid +1:valid + 31 + 1 + read-only + + + TRIGGER + Software trigger for sensing in trigger mode, trigger will be ignored if in sensing or other mode + 0 + 1 + write-only + + + + + CONFIG + Configuration + 0x14 + 32 + 0x00600300 + 0xC3FF0713 + + + IRQ_EN + Enable interrupt + 31 + 1 + read-write + + + RST_EN + Enable reset + 30 + 1 + read-write + + + COMPARE_MIN_EN + Enable compare for minimum temperature + 25 + 1 + read-write + + + COMPARE_MAX_EN + Enable compare for maximum temperature + 24 + 1 + read-write + + + SPEED + cycles of a progressive step in 24M clock, valid from 24-255, default 96 +24: 24 cycle for a step +25: 25 cycle for a step +26: 26 cycle for a step +... +255: 255 cycle for a step + 16 + 8 + read-write + + + AVERAGE + Average time, default in 3 +0: measure and return +1: twice and average +2: 4 times and average +. . . +7: 128 times and average + 8 + 3 + read-write + + + CONTINUOUS + continuous mode that keep sampling temperature peridically +0: trigger mode +1: continuous mode + 4 + 1 + read-write + + + ASYNC + Acynchronous mode, this mode can work without clock, only available function ios compare to certain ADC value +0: active mode +1: Async mode + 1 + 1 + read-write + + + ENABLE + Enable temperature +0: disable, temperature sensor is shut down +1: enable. Temperature sensor enabled + 0 + 1 + read-write + + + + + VALIDITY + Sample validity + 0x18 + 32 + 0x016E3600 + 0xFFFFFFFF + + + VALIDITY + time for temperature values to expire in 24M clock cycles + 0 + 32 + read-write + + + + + FLAG + Temperature flag + 0x1c + 32 + 0x00000000 + 0x00330001 + + + RECORD_MIN_CLR + Clear minimum recorder of temerature, write 1 to clear + 21 + 1 + read-write + + + RECORD_MAX_CLR + Clear maximum recorder of temerature, write 1 to clear + 20 + 1 + read-write + + + UNDER_TEMP + Clear under temperature status, write 1 to clear + 17 + 1 + read-write + + + OVER_TEMP + Clear over temperature status, write 1 to clear + 16 + 1 + read-write + + + IRQ + IRQ flag, write 1 to clear + 0 + 1 + read-write + + + + + UPPER_LIM_IRQ + Maximum temperature to interrupt + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Maximum temperature for compare + 0 + 32 + read-write + + + + + LOWER_LIM_IRQ + Minimum temperature to interrupt + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Minimum temperature for compare + 0 + 32 + read-write + + + + + UPPER_LIM_RST + Maximum temperature to reset + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Maximum temperature for compare + 0 + 32 + read-write + + + + + LOWER_LIM_RST + Minimum temperature to reset + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Minimum temperature for compare + 0 + 32 + read-write + + + + + ASYNC + Configuration in asynchronous mode + 0x30 + 32 + 0x00000000 + 0x010107FF + + + ASYNC_TYPE + Compare hotter than or colder than in asynchoronous mode +0: hotter than +1: colder than + 24 + 1 + read-write + + + POLARITY + Polarity of internal comparator + 16 + 1 + read-write + + + VALUE + Value of async mode to compare + 0 + 11 + read-write + + + + + ADVAN + Advance configuration + 0x38 + 32 + 0x00000000 + 0x03010003 + + + ASYNC_IRQ + interrupt status of asynchronous mode + 25 + 1 + read-only + + + ACTIVE_IRQ + interrupt status of active mode + 24 + 1 + read-only + + + SAMPLING + temperature sampling is working + 16 + 1 + read-only + + + NEG_ONLY + use negative compare polarity only + 1 + 1 + read-write + + + POS_ONLY + use positive compare polarity only + 0 + 1 + read-write + + + + + + + BACC + BACC + BACC + 0xf5000000 + + 0x0 + 0x10 + registers + + + + CONFIG + Access timing for access + 0x0 + 32 + 0x00000000 + 0x3000FFFF + + + FAST_WRITE + Use fast write +0: Write normally +1: boost write + 29 + 1 + read-write + + + FAST_READ + Use fast read +0: Read normally +1: boost read + 28 + 1 + read-write + + + TIMING + Time in APB clock cycles, for battery timing penerate + 0 + 16 + read-write + + + + + PRE_TIME + Timing gap before rising edge + 0x8 + 32 + 0x00000000 + 0x000FFFFF + + + PRE_RATIO + Ratio of guard band before rising edge +0: 0 +1: 1/32768 of low level width +2: 1/16384 of low level width +14: 1/4 of low level width +15: 1/2 of low level width + 16 + 4 + read-write + + + PRE_OFFSET + guard band before rising edge +this value will be added to ratio number + 0 + 16 + read-write + + + + + POST_TIME + Timing gap after rising edge + 0xc + 32 + 0x00000000 + 0x000FFFFF + + + POST_RATIO + Ratio of guard band after rising edge +0: 0 +1: 1/32768 of high level width +2: 1/16384 of high level width +14: 1/4 of high level width +15: 1/2 of high level width + 16 + 4 + read-write + + + POST_OFFSET + guard band after rising edge +this value will be added to ratio number + 0 + 16 + read-write + + + + + + + BPOR + BPOR + BPOR + 0xf5004000 + + 0x0 + 0x10 + registers + + + + POR_CAUSE + Power on cause + 0x0 + 32 + 0x00000000 + 0x0000001F + + + CAUSE + Power on cause, each bit represnts one cause, write 1 to clear each bit +bit0: wakeup button +bit1: security violation +bit2: RTC alarm 0 +bit3: RTC alarm 1 +bit4: GPIO + 0 + 5 + read-write + + + + + POR_SELECT + Power on select + 0x4 + 32 + 0x00000000 + 0x0000001F + + + SELECT + Power on cause select, each bit represnts one cause, value 1 enables corresponding cause +bit0: wakeup button +bit1: security violation +bit2: RTC alarm 0 +bit3: RTC alarm 1 +bit4: GPIO + 0 + 5 + read-write + + + + + POR_CONFIG + Power on reset config + 0x8 + 32 + 0x00000000 + 0x00000001 + + + RETENTION + retention battery domain setting +0: battery reset on reset pin reset happen +1: battery domain retention when reset pin reset happen + 0 + 1 + read-write + + + + + POR_CONTROL + Power down control + 0xc + 32 + 0x00000000 + 0x0000FFFF + + + COUNTER + Chip power down counter, counter decreasing if value is not 0, power down of chip happens on counter value is 1 + 0 + 16 + read-write + + + + + + + BCFG + BCFG + TRIM + 0xf5008000 + + 0x0 + 0x14 + registers + + + + VBG_CFG + Bandgap config + 0x0 + 32 + 0x00000000 + 0x831F1F1F + + + VBG_TRIMMED + Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: bandgap is not trimmed +1: bandgap is trimmed + 31 + 1 + read-write + + + LP_MODE + Bandgap works in low power mode +0: not in low power mode +1: bandgap work in low power mode + 25 + 1 + read-write + + + POWER_SAVE + Bandgap works in power save mode +0: not in power save mode +1: bandgap work in power save mode + 24 + 1 + read-write + + + VBG_1P0 + Bandgap 1.0V output trim + 16 + 5 + read-write + + + VBG_P65 + Bandgap 0.65V output trim + 8 + 5 + read-write + + + VBG_P50 + Bandgap 0.50V output trim + 0 + 5 + read-write + + + + + IRC32K_CFG + On-chip 32k oscillator config + 0x8 + 32 + 0x00000000 + 0x80C001FF + + + IRC_TRIMMED + IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: irc is not trimmed +1: irc is trimmed + 31 + 1 + read-write + + + CAPEX7_TRIM + IRC32K bit 7 + 23 + 1 + read-write + + + CAPEX6_TRIM + IRC32K bit 6 + 22 + 1 + read-write + + + CAP_TRIM + capacitor trim bits + 0 + 9 + read-write + + + + + XTAL32K_CFG + XTAL 32K config + 0xc + 32 + 0x00000000 + 0x00001313 + + + HYST_EN + crystal 32k hysteres enable + 12 + 1 + read-write + + + GMSEL + crystal 32k gm selection + 8 + 2 + read-write + + + CFG + crystal 32k config + 4 + 1 + read-write + + + AMP + crystal 32k amplifier + 0 + 2 + read-write + + + + + CLK_CFG + Clock config + 0x10 + 32 + 0x00000000 + 0x10010010 + + + XTAL_SEL + crystal selected + 28 + 1 + read-only + + + KEEP_IRC + force irc32k run + 16 + 1 + read-write + + + FORCE_XTAL + force switch to crystal + 4 + 1 + read-write + + + + + + + BUTN + BUTN + BUTN + 0xf500c000 + + 0x0 + 0xc + registers + + + + BTN_STATUS + Button status + 0x0 + 32 + 0x00000000 + 0x77770FFF + + + XWCLICK + wake button click status when power button held, write 1 to clear flag +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 28 + 3 + read-write + + + WCLICK + wake button click status, write 1 to clear flag +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 24 + 3 + read-write + + + XPCLICK + power button click status when wake button held, write 1 to clear flag +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 20 + 3 + read-write + + + PCLICK + power button click status, write 1 to clear flag +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 16 + 3 + read-write + + + DBTN + Dual button press status, write 1 to clear flag +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 8 + 4 + read-write + + + WBTN + Wake button press status, write 1 to clear flag +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 4 + 4 + read-write + + + PBTN + Power button press status, write 1 to clear flag +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 0 + 4 + read-write + + + + + BTN_IRQ_MASK + Button interrupt mask + 0x4 + 32 + 0x00000000 + 0x77770FFF + + + XWCLICK + wake button click status when power button held interrupt enable +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 28 + 3 + read-write + + + WCLICK + wake button click interrupt enable +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 24 + 3 + read-write + + + XPCLICK + power button click status when wake button held interrupt enable +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 20 + 3 + read-write + + + PCLICK + power button click interrupt enable +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 16 + 3 + read-write + + + DBTN + Dual button press interrupt enable +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 8 + 4 + read-write + + + WBTN + Wake button press interrupt enable +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 4 + 4 + read-write + + + PBTN + Power button press interrupt enable +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 0 + 4 + read-write + + + + + LED_INTENSE + Debounce setting + 0x8 + 32 + 0x00000000 + 0x000F000F + + + RLED + Rbutton brightness 0 + 16 + 4 + read-write + + + PLED + Pbutton brightness 0 + 0 + 4 + read-write + + + + + + + BGPR + BGPR + BGPR + 0xf5018000 + + 0x0 + 0x20 + registers + + + + 8 + 0x4 + 0,1,2,3,4,5,6,7 + GPR[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + Generic control + 0 + 32 + read-write + + + + + + + BSEC + BSEC + BSEC + 0xf5040000 + + 0x0 + 0x14 + registers + + + + SECURE_STATE + Secure state + 0x0 + 32 + 0x00000000 + 0x0003000F + + + ALLOW_NSC + Non-secure state allow +0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter non-secure state + 17 + 1 + read-only + + + ALLOW_SEC + Secure state allow +0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter secure state + 16 + 1 + read-only + + + BATT_FAIL + BATT secure state one hot indicator +0: secure state is not in fail state +1: secure state is in fail state + 3 + 1 + read-write + + + BATT_NSC + BATT secure state one hot indicator +0: secure state is not in non-secure state +1: secure state is in non-secure state + 2 + 1 + read-write + + + BATT_SEC + BATT secure state one hot indicator +0: secure state is not in secure state +1: secure state is in secure state + 1 + 1 + read-write + + + BATT_INS + BATT secure state one hot indicator +0: secure state is not in inspect state +1: secure state is in inspect state + 0 + 1 + read-write + + + + + SECURE_STATE_CONFIG + secure state configuration + 0x4 + 32 + 0x00000000 + 0x00000009 + + + LOCK + Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset +0: not locked, register can be modified +1: register locked, write access to the register is ignored + 3 + 1 + read-write + + + ALLOW_RESTART + allow secure state restart from fail state +0: restart is not allowed, only hardware reset can recover secure state +1: software is allowed to switch to inspect state from fail state + 0 + 1 + read-write + + + + + VIOLATION_CONFIG + Security violation config + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 0 + 15 + read-write + + + + + ESCALATE_CONFIG + Escalate behavior on security event + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 0 + 15 + read-write + + + + + EVENT + Event and escalate status + 0x10 + 32 + 0x00000000 + 0xFFFF0003 + + + EVENT + local event statue, each bit represents one security event + 16 + 16 + read-only + + + BATT_ESC_NSC + BATT is escalating non-secure event + 1 + 1 + read-only + + + BATT_ESC_SEC + BATT is escalting ssecure event + 0 + 1 + read-only + + + + + + + RTC + RTC + RTC + 0xf5044000 + + 0x0 + 0x28 + registers + + + + SECOND + Second counter + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SECOND + second counter + 0 + 32 + read-write + + + + + SUBSEC + Sub-second counter + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SUBSEC + sub second counter + 0 + 32 + read-only + + + + + SEC_SNAP + Second counter snap shot + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SEC_SNAP + second snap shot, write to take snap shot + 0 + 32 + read-write + + + + + SUB_SNAP + Sub-second counter snap shot + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + SUB_SNAP + sub second snap shot, write to take snap shot + 0 + 32 + read-write + + + + + ALARM0 + RTC alarm0 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + ALARM + Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC + 0 + 32 + read-write + + + + + ALARM0_INC + Alarm0 incremental + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + INCREASE + adder when ARLAM0 happen, helps to create periodical alarm + 0 + 32 + read-write + + + + + ALARM1 + RTC alarm1 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + ALARM + Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC + 0 + 32 + read-write + + + + + ALARM1_INC + Alarm1 incremental + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + INCREASE + adder when ARLAM0 happen, helps to create periodical alarm + 0 + 32 + read-write + + + + + ALARM_FLAG + RTC alarm flag + 0x20 + 32 + 0x00000000 + 0x00000003 + + + ALARM1 + alarm1 happen + 1 + 1 + read-write + + + ALARM0 + alarm0 happen + 0 + 1 + read-write + + + + + ALARM_EN + RTC alarm enable + 0x24 + 32 + 0x00000000 + 0x00000003 + + + ENABLE1 + alarm1 mask +0: alarm1 disabled +1: alarm1 enabled + 1 + 1 + read-write + + + ENABLE0 + alarm0 mask +0: alarm0 disabled +1: alarm0 enabled + 0 + 1 + read-write + + + + + + + BKEY + BKEY + BKEY + 0xf5048000 + + 0x0 + 0x4c + registers + + + + 2 + 0x20 + 0,1 + KEY[%s] + no description available + 0x0 + + 8 + 0x4 + 0,1,2,3,4,5,6,7 + DATA[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + + 2 + 0x4 + KEY0,KEY1 + ECC[%s] + no description available + 0x40 + 32 + 0x00000000 + 0xC000FFFF + + + WLOCK + write lock to key0 +0: write enable +1: write ignored + 31 + 1 + read-write + + + RLOCK + read lock to key0 +0: key read enable +1: key always read as 0 + 30 + 1 + read-write + + + ECC + Parity check bits for key0 + 0 + 16 + read-write + + + + + SELECT + Key selection + 0x48 + 32 + 0x00000000 + 0x00000001 + + + SELECT + select key, key0 treated as secure key, in non-scure mode, only key1 can be selected +0: select key0 in secure mode, key1 in non-secure mode +1: select key1 in secure or nonsecure mode + 0 + 1 + read-write + + + + + + + BMON + BMON + BMON + 0xf504c000 + + 0x0 + 0x20 + registers + + + + 2 + 0x10 + glitch0,clock0 + MONITOR[%s] + no description available + 0x0 + + CONTROL + Glitch and clock monitor control + 0x0 + 32 + 0x00000000 + 0x00000011 + + + ACTIVE + select glitch works in active mode or passve mode. +0: passive mode, depends on power glitch destroy DFF value +1: active mode, check glitch by DFF chain + 4 + 1 + read-write + + + ENABLE + enable glitch detector +0: detector disabled +1: detector enabled + 0 + 1 + read-write + + + + + STATUS + Glitch and clock monitor status + 0x4 + 32 + 0x00000000 + 0x00000001 + + + FLAG + flag for glitch detected, write 1 to clear this flag +0: glitch not detected +1: glitch detected + 0 + 1 + read-write + + + + + + + + TAMP + TAMP + TAMP + 0xf5050000 + + 0x0 + 0x88 + registers + + + + 4 + 0x10 + tamp0,tamp1,tamp2,tamp3 + TAMP[%s] + no description available + 0x0 + + CONTROL + Tamper n control + 0x0 + 32 + 0x00000000 + 0x801F03F7 + + + LOCK + lock tamper setting +0: tamper setting can be changed +1: tamper setting will last to next battery domain power cycle + 31 + 1 + read-write + + + BYPASS + bypass tamper violation filter +0: filter applied +1: filter not used + 20 + 1 + read-write + + + FILTER + filter length +0: 1 cycle +1: 2 cycle +15: 65526 cycle + 16 + 4 + read-write + + + VALUE + pin value for passive tamper + 8 + 2 + read-write + + + SPEED + tamper speed selection, (2^SPEED) changes per second +0: 1 shift per second +1: 2 shifts per second +. . . +15: 32768 shifts per second + 4 + 4 + read-write + + + RECOVER + tamper will recover itself if tamper LFSR goes wrong +0: tamper will not recover +1: tamper will recover + 2 + 1 + read-write + + + ACTIVE + select active or passive tamper +0: passive tamper +1: active tamper + 1 + 1 + read-write + + + ENABLE + enable tamper +0: tamper disableed +1: tamper enabled + 0 + 1 + read-write + + + + + POLY + Tamper n Polynomial of LFSR + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + POLY + tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" + 0 + 32 + read-write + + + + + LFSR + Tamper n LFSR shift register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + LFSR + LFSR for active tamper, write only register, always read 0 + 0 + 32 + write-only + + + + + + TAMP_FLAG + Tamper flag + 0x80 + 32 + 0x00000000 + 0x00000FFF + + + FLAG + tamper flag, each bit represents one tamper pin, write 1 to clear the flag +Note, clear can only be cleared when tamper disappeared + 0 + 12 + read-write + + + + + IRQ_EN + Tamper interrupt enable + 0x84 + 32 + 0x00000000 + 0x80000FFF + + + LOCK + lock bit for IRQ enable +0: enable bits can be changed +1: enable bits hold until next battery domain power cycle + 31 + 1 + read-write + + + IRQ_EN + interrupt enable, each bit represents one tamper pin +0: interrupt disabled +1: interrupt enabled + 0 + 12 + read-write + + + + + + + MONO + MONO + MONO + 0xf5054000 + + 0x0 + 0x8 + registers + + + + MONOL + Low part of monotonic counter + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + low part of monotonica counter, write to this counter will cause counter increase by 1 + 0 + 32 + read-write + + + + + MONOH + High part of monotonic counter + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + EPOCH + Fuse value for high part of monotonica + 16 + 16 + read-write + + + COUNTER + high part of monotonica counter, write to this counter will cause counter increase by 1 if low part overflow + 0 + 16 + read-write + + + + + + + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_batt_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_batt_iomux.h index a85b8eb003e..42236137ac5 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_batt_iomux.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_batt_iomux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -9,51 +9,81 @@ #ifndef HPM_BATT_IOMUX_H #define HPM_BATT_IOMUX_H -/* IOC_PZ00_FUNC_CTL function mux definitions */ -#define IOC_PZ00_FUNC_CTL_BGPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ00_FUNC_CTL_PWR_ON IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ00_FUNC_CTL_TAMP_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ00_FUNC_CTL_SOC_PZ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PZ01_FUNC_CTL function mux definitions */ -#define IOC_PZ01_FUNC_CTL_BGPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ01_FUNC_CTL_RESETN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ01_FUNC_CTL_TAMP_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ01_FUNC_CTL_SOC_PZ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PZ02_FUNC_CTL function mux definitions */ -#define IOC_PZ02_FUNC_CTL_BGPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ02_FUNC_CTL_PBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ02_FUNC_CTL_TAMP_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ02_FUNC_CTL_SOC_PZ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PZ03_FUNC_CTL function mux definitions */ -#define IOC_PZ03_FUNC_CTL_BGPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ03_FUNC_CTL_WBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ03_FUNC_CTL_TAMP_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ03_FUNC_CTL_SOC_PZ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PZ04_FUNC_CTL function mux definitions */ -#define IOC_PZ04_FUNC_CTL_BGPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ04_FUNC_CTL_PLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ04_FUNC_CTL_TAMP_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ04_FUNC_CTL_SOC_PZ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PZ05_FUNC_CTL function mux definitions */ -#define IOC_PZ05_FUNC_CTL_BGPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ05_FUNC_CTL_WLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ05_FUNC_CTL_TAMP_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ05_FUNC_CTL_SOC_PZ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PZ06_FUNC_CTL function mux definitions */ -#define IOC_PZ06_FUNC_CTL_BGPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ06_FUNC_CTL_TAMP_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ06_FUNC_CTL_SOC_PZ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PZ07_FUNC_CTL function mux definitions */ -#define IOC_PZ07_FUNC_CTL_BGPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ07_FUNC_CTL_TAMP_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ07_FUNC_CTL_SOC_PZ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +/* BIOC_PZ00_FUNC_CTL function mux definitions */ +#define IOC_PZ00_FUNC_CTL_BGPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ00_FUNC_CTL_BGPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ00_FUNC_CTL_PWR_ON IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ00_FUNC_CTL_PWR_ON IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ00_FUNC_CTL_TAMP_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ00_FUNC_CTL_TAMP_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ00_FUNC_CTL_SOC_PZ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ00_FUNC_CTL_SOC_PZ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ01_FUNC_CTL function mux definitions */ +#define IOC_PZ01_FUNC_CTL_BGPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ01_FUNC_CTL_BGPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ01_FUNC_CTL_RESETN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ01_FUNC_CTL_RESETN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ01_FUNC_CTL_TAMP_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ01_FUNC_CTL_TAMP_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ01_FUNC_CTL_SOC_PZ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ01_FUNC_CTL_SOC_PZ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ02_FUNC_CTL function mux definitions */ +#define IOC_PZ02_FUNC_CTL_BGPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ02_FUNC_CTL_BGPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ02_FUNC_CTL_PBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ02_FUNC_CTL_PBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ02_FUNC_CTL_TAMP_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ02_FUNC_CTL_TAMP_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ02_FUNC_CTL_SOC_PZ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ02_FUNC_CTL_SOC_PZ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ03_FUNC_CTL function mux definitions */ +#define IOC_PZ03_FUNC_CTL_BGPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ03_FUNC_CTL_BGPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ03_FUNC_CTL_WBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ03_FUNC_CTL_WBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ03_FUNC_CTL_TAMP_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ03_FUNC_CTL_TAMP_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ03_FUNC_CTL_SOC_PZ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ03_FUNC_CTL_SOC_PZ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ04_FUNC_CTL function mux definitions */ +#define IOC_PZ04_FUNC_CTL_BGPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ04_FUNC_CTL_BGPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ04_FUNC_CTL_PLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ04_FUNC_CTL_PLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ04_FUNC_CTL_TAMP_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ04_FUNC_CTL_TAMP_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ04_FUNC_CTL_SOC_PZ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ04_FUNC_CTL_SOC_PZ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ05_FUNC_CTL function mux definitions */ +#define IOC_PZ05_FUNC_CTL_BGPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ05_FUNC_CTL_BGPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ05_FUNC_CTL_WLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ05_FUNC_CTL_WLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ05_FUNC_CTL_TAMP_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ05_FUNC_CTL_TAMP_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ05_FUNC_CTL_SOC_PZ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ05_FUNC_CTL_SOC_PZ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ06_FUNC_CTL function mux definitions */ +#define IOC_PZ06_FUNC_CTL_BGPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ06_FUNC_CTL_BGPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ06_FUNC_CTL_TAMP_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ06_FUNC_CTL_TAMP_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ06_FUNC_CTL_SOC_PZ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ06_FUNC_CTL_SOC_PZ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ07_FUNC_CTL function mux definitions */ +#define IOC_PZ07_FUNC_CTL_BGPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ07_FUNC_CTL_BGPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ07_FUNC_CTL_TAMP_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ07_FUNC_CTL_TAMP_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ07_FUNC_CTL_SOC_PZ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ07_FUNC_CTL_SOC_PZ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #endif /* HPM_BATT_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_bcfg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_bcfg_regs.h index 50cbd1b455a..56355a5e012 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_bcfg_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_bcfg_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_bgpr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_bgpr_regs.h index 46bb7beb07b..9d81aab19cf 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_bgpr_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_bgpr_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -10,106 +10,32 @@ #define HPM_BGPR_H typedef struct { - __RW uint32_t BATT_GPR0; /* 0x0: Generic control */ - __RW uint32_t BATT_GPR1; /* 0x4: Generic control */ - __RW uint32_t BATT_GPR2; /* 0x8: Generic control */ - __RW uint32_t BATT_GPR3; /* 0xC: Generic control */ - __RW uint32_t BATT_GPR4; /* 0x10: Generic control */ - __RW uint32_t BATT_GPR5; /* 0x14: Generic control */ - __RW uint32_t BATT_GPR6; /* 0x18: Generic control */ - __RW uint32_t BATT_GPR7; /* 0x1C: Generic control */ + __RW uint32_t GPR[8]; /* 0x0 - 0x1C: Generic control */ } BGPR_Type; -/* Bitfield definition for register: BATT_GPR0 */ +/* Bitfield definition for register array: GPR */ /* - * GPR (RW) + * DATA (RW) * * Generic control */ -#define BGPR_BATT_GPR0_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR0_GPR_SHIFT (0U) -#define BGPR_BATT_GPR0_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR0_GPR_SHIFT) & BGPR_BATT_GPR0_GPR_MASK) -#define BGPR_BATT_GPR0_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR0_GPR_MASK) >> BGPR_BATT_GPR0_GPR_SHIFT) +#define BGPR_GPR_DATA_MASK (0xFFFFFFFFUL) +#define BGPR_GPR_DATA_SHIFT (0U) +#define BGPR_GPR_DATA_SET(x) (((uint32_t)(x) << BGPR_GPR_DATA_SHIFT) & BGPR_GPR_DATA_MASK) +#define BGPR_GPR_DATA_GET(x) (((uint32_t)(x) & BGPR_GPR_DATA_MASK) >> BGPR_GPR_DATA_SHIFT) -/* Bitfield definition for register: BATT_GPR1 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR1_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR1_GPR_SHIFT (0U) -#define BGPR_BATT_GPR1_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR1_GPR_SHIFT) & BGPR_BATT_GPR1_GPR_MASK) -#define BGPR_BATT_GPR1_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR1_GPR_MASK) >> BGPR_BATT_GPR1_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR2 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR2_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR2_GPR_SHIFT (0U) -#define BGPR_BATT_GPR2_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR2_GPR_SHIFT) & BGPR_BATT_GPR2_GPR_MASK) -#define BGPR_BATT_GPR2_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR2_GPR_MASK) >> BGPR_BATT_GPR2_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR3 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR3_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR3_GPR_SHIFT (0U) -#define BGPR_BATT_GPR3_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR3_GPR_SHIFT) & BGPR_BATT_GPR3_GPR_MASK) -#define BGPR_BATT_GPR3_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR3_GPR_MASK) >> BGPR_BATT_GPR3_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR4 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR4_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR4_GPR_SHIFT (0U) -#define BGPR_BATT_GPR4_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR4_GPR_SHIFT) & BGPR_BATT_GPR4_GPR_MASK) -#define BGPR_BATT_GPR4_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR4_GPR_MASK) >> BGPR_BATT_GPR4_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR5 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR5_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR5_GPR_SHIFT (0U) -#define BGPR_BATT_GPR5_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR5_GPR_SHIFT) & BGPR_BATT_GPR5_GPR_MASK) -#define BGPR_BATT_GPR5_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR5_GPR_MASK) >> BGPR_BATT_GPR5_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR6 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR6_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR6_GPR_SHIFT (0U) -#define BGPR_BATT_GPR6_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR6_GPR_SHIFT) & BGPR_BATT_GPR6_GPR_MASK) -#define BGPR_BATT_GPR6_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR6_GPR_MASK) >> BGPR_BATT_GPR6_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR7 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR7_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR7_GPR_SHIFT (0U) -#define BGPR_BATT_GPR7_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR7_GPR_SHIFT) & BGPR_BATT_GPR7_GPR_MASK) -#define BGPR_BATT_GPR7_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR7_GPR_MASK) >> BGPR_BATT_GPR7_GPR_SHIFT) +/* GPR register group index macro definition */ +#define BGPR_GPR_0 (0UL) +#define BGPR_GPR_1 (1UL) +#define BGPR_GPR_2 (2UL) +#define BGPR_GPR_3 (3UL) +#define BGPR_GPR_4 (4UL) +#define BGPR_GPR_5 (5UL) +#define BGPR_GPR_6 (6UL) +#define BGPR_GPR_7 (7UL) #endif /* HPM_BGPR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_bpor_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_bpor_regs.h index 32147d05a2f..4f48a15578d 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_bpor_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_bpor_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.c index f800e4ac59b..25c654665ed 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -21,8 +21,8 @@ #define FREQ_PRESET1_PLL1_CLK2 (250000000UL) #define FREQ_PRESET1_PLL1_CLK0 (480000000UL) #define FREQ_PRESET1_PLL1_CLK1 (320000000UL) -#define FREQ_PRESET1_PLL2_CLK0 (5160960000UL) -#define FREQ_PRESET1_PLL2_CLK1 (4515840000UL) +#define FREQ_PRESET1_PLL2_CLK0 (516096000UL) +#define FREQ_PRESET1_PLL2_CLK1 (451584000UL) #define FREQ_32KHz (32768UL) #define ADC_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->ADCCLK) #define DAC_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->DACCLK) @@ -61,6 +61,11 @@ static uint32_t get_frequency_for_dac(uint32_t instance); */ static uint32_t get_frequency_for_wdg(uint32_t instance); +/** + * @brief Get Clock frequency for PWDG + */ +static uint32_t get_frequency_for_pwdg(void); + /** * @brief Turn on/off the IP clock */ @@ -118,6 +123,9 @@ uint32_t clock_get_frequency(clock_name_t clock_name) case CLK_SRC_GROUP_WDG: clk_freq = get_frequency_for_wdg(node_or_instance); break; + case CLK_SRC_GROUP_PWDG: + clk_freq = get_frequency_for_pwdg(); + break; case CLK_SRC_GROUP_PMIC: clk_freq = FREQ_PRESET1_OSC0_CLK0; break; @@ -219,7 +227,11 @@ static uint32_t get_frequency_for_i2s_or_adc(uint32_t clk_src_type, uint32_t ins } if (is_mux_valid) { - clk_freq = get_frequency_for_ip_in_common_group(node); + if (node == clock_node_ahb) { + clk_freq = get_frequency_for_ahb(); + } else { + clk_freq = get_frequency_for_ip_in_common_group(node); + } } return clk_freq; } @@ -251,7 +263,7 @@ static uint32_t get_frequency_for_wdg(uint32_t instance) uint32_t freq_in_hz; /* EXT clock is chosen */ if (WDG_CTRL_CLKSEL_GET(s_wdgs[instance]->CTRL) == 0) { - freq_in_hz = get_frequency_for_cpu(); + freq_in_hz = get_frequency_for_ahb(); } /* PCLK is chosen */ else { @@ -261,6 +273,18 @@ static uint32_t get_frequency_for_wdg(uint32_t instance) return freq_in_hz; } +static uint32_t get_frequency_for_pwdg(void) +{ + uint32_t freq_in_hz; + if (WDG_CTRL_CLKSEL_GET(HPM_PWDG->CTRL) == 0) { + freq_in_hz = FREQ_PRESET1_OSC0_CLK0; + } else { + freq_in_hz = FREQ_32KHz; + } + + return freq_in_hz; +} + static uint32_t get_frequency_for_cpu(void) { uint32_t mux = SYSCTL_CLOCK_CPU_MUX_GET(HPM_SYSCTL->CLOCK_CPU[0]); @@ -297,6 +321,12 @@ clk_src_t clock_get_source(clock_name_t clock_name) clk_src_index = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[node_or_instance]); } break; + case CLK_SRC_GROUP_DAC: + if (node_or_instance < DAC_INSTANCE_NUM) { + clk_src_group = CLK_SRC_GROUP_DAC; + clk_src_index = SYSCTL_DACCLK_MUX_GET(HPM_SYSCTL->DACCLK[node_or_instance]); + } + break; case CLK_SRC_GROUP_I2S: if (node_or_instance < I2S_INSTANCE_NUM) { clk_src_group = CLK_SRC_GROUP_I2S; @@ -306,9 +336,13 @@ clk_src_t clock_get_source(clock_name_t clock_name) case CLK_SRC_GROUP_WDG: if (node_or_instance < WDG_INSTANCE_NUM) { clk_src_group = CLK_SRC_GROUP_WDG; - clk_src_index = (WDG_CTRL_CLKSEL_GET(s_wdgs[node_or_instance]->CTRL) == 0); + clk_src_index = WDG_CTRL_CLKSEL_GET(s_wdgs[node_or_instance]->CTRL); } break; + case CLK_SRC_GROUP_PWDG: + clk_src_group = CLK_SRC_GROUP_PWDG; + clk_src_index = WDG_CTRL_CLKSEL_GET(HPM_PWDG->CTRL); + break; case CLK_SRC_GROUP_PMIC: clk_src_group = CLK_SRC_GROUP_COMMON; clk_src_index = clock_source_osc0_clk0; @@ -337,6 +371,42 @@ clk_src_t clock_get_source(clock_name_t clock_name) return clk_src; } +uint32_t clock_get_divider(clock_name_t clock_name) +{ + uint32_t clk_divider = CLOCK_DIV_INVALID; + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + switch (clk_src_type) { + case CLK_SRC_GROUP_COMMON: + clk_divider = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[node_or_instance]); + break; + case CLK_SRC_GROUP_WDG: + if (node_or_instance < WDG_INSTANCE_NUM) { + clk_divider = 1UL; + } + break; + case CLK_SRC_GROUP_PWDG: + clk_divider = 1UL; + break; + case CLK_SRC_GROUP_PMIC: + clk_divider = 1UL; + break; + case CLK_SRC_GROUP_CPU0: + clk_divider = 1UL + SYSCTL_CLOCK_CPU_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]); + break; + case CLK_SRC_GROUP_AHB: + clk_divider = 1UL + SYSCTL_CLOCK_CPU_SUB1_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]); + break; + case CLK_SRC_GROUP_AXI: + clk_divider = 1UL + SYSCTL_CLOCK_CPU_SUB0_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]); + break; + default: + clk_divider = CLOCK_DIV_INVALID; + break; + } + return clk_divider; +} + hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src) { uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); @@ -346,7 +416,7 @@ hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src) return status_clk_invalid; } - if ((src != clk_adc_src_ahb) && (src != clk_adc_src_ana)) { + if ((src < clk_adc_src_ana0) || (src > clk_adc_src_ahb0)) { return status_clk_src_invalid; } @@ -366,7 +436,7 @@ hpm_stat_t clock_set_dac_source(clock_name_t clock_name, clk_src_t src) return status_clk_invalid; } - if ((src != clk_dac_src_ana) || (src != clk_dac_src_ahb)) { + if ((src < clk_dac_src_ana3) || (src > clk_dac_src_ahb0)) { return status_clk_src_invalid; } @@ -412,21 +482,12 @@ hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint } break; case CLK_SRC_GROUP_ADC: - status = status_clk_operation_unsupported; - break; + case CLK_SRC_GROUP_DAC: case CLK_SRC_GROUP_I2S: - status = status_clk_operation_unsupported; - break; case CLK_SRC_GROUP_WDG: - if (node_or_instance < WDG_INSTANCE_NUM) { - if (src == clk_wdg_src_ahb0) { - s_wdgs[node_or_instance]->CTRL &= ~WDG_CTRL_CLKSEL_MASK; - } else if (src == clk_wdg_src_osc32k) { - s_wdgs[node_or_instance]->CTRL |= WDG_CTRL_CLKSEL_MASK; - } else { - status = status_clk_src_invalid; - } - } + case CLK_SRC_GROUP_PWDG: + case CLK_SRC_GROUP_SRC: + status = status_clk_operation_unsupported; break; case CLK_SRC_GROUP_PMIC: status = status_clk_fixed; @@ -452,9 +513,6 @@ hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint status = status_clk_shared_cpu0; } break; - case CLK_SRC_GROUP_SRC: - status = status_clk_operation_unsupported; - break; default: status = status_clk_src_invalid; break; @@ -463,7 +521,7 @@ hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint return status; } -void switch_ip_clock(clock_name_t clock_name, bool on) +static void switch_ip_clock(clock_name_t clock_name, bool on) { uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); @@ -507,6 +565,19 @@ void clock_remove_from_group(clock_name_t clock_name, uint32_t group) } } +bool clock_check_in_group(clock_name_t clock_name, uint32_t group) +{ + bool added = false; + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + if (resource < sysctl_resource_end) { + added = sysctl_check_group_resource_enable(HPM_SYSCTL, group, resource); + } else if (resource == RESOURCE_SHARED_PTPC) { + added = sysctl_check_group_resource_enable(HPM_SYSCTL, group, sysctl_resource_ptpc); + } + return added; +} + void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu) { if (cpu < 2U) { diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.h index b0bada18b28..c9f3be01089 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -11,6 +11,7 @@ #include "hpm_sysctl_drv.h" #include "hpm_csr_drv.h" +#define CLOCK_DIV_INVALID (~0UL) /** * @brief Error codes for clock driver @@ -45,6 +46,7 @@ enum { #define CLK_SRC_GROUP_DAC (7U) #define CLK_SRC_GROUP_CPU0 (9U) #define CLK_SRC_GROUP_SRC (10U) +#define CLK_SRC_GROUP_PWDG (11U) #define CLK_SRC_GROUP_INVALID (15U) #define MAKE_CLK_SRC(src_grp, index) (((uint8_t)(src_grp)<<4) | (index)) @@ -65,11 +67,13 @@ typedef enum _clock_sources { clk_src_pll2_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 7), clk_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 8), - clk_adc_src_ana = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), - clk_adc_src_ahb = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 1), + clk_adc_src_ana0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), + clk_adc_src_ana1 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), + clk_adc_src_ana2 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), + clk_adc_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 1), - clk_dac_src_ana = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 0), - clk_dac_src_ahb = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 1), + clk_dac_src_ana3 = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 0), + clk_dac_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 1), clk_i2s_src_aud0 = MAKE_CLK_SRC(CLK_SRC_GROUP_I2S, 0), clk_i2s_src_aud1 = MAKE_CLK_SRC(CLK_SRC_GROUP_I2S, 1), @@ -77,6 +81,9 @@ typedef enum _clock_sources { clk_wdg_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_WDG, 0), clk_wdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_WDG, 1), + clk_pwdg_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_PWDG, 0), + clk_pwdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_PWDG, 1), + clk_src_invalid = MAKE_CLK_SRC(CLK_SRC_GROUP_INVALID, 15), } clk_src_t; @@ -135,11 +142,11 @@ typedef enum _clock_name { clock_ptpc = MAKE_CLOCK_NAME(sysctl_resource_ptpc, CLK_SRC_GROUP_COMMON, clock_node_ptpc), clock_ptp0 = MAKE_CLOCK_NAME(RESOURCE_SHARED_PTPC, CLK_SRC_GROUP_COMMON, clock_node_ptp0), clock_ref0 = MAKE_CLOCK_NAME(sysctl_resource_ref0, CLK_SRC_GROUP_COMMON, clock_node_ref0), - clock_ref1 = MAKE_CLOCK_NAME(sysctl_resource_ref1, CLK_SRC_GROUP_COMMON, clock_node_ref0), + clock_ref1 = MAKE_CLOCK_NAME(sysctl_resource_ref1, CLK_SRC_GROUP_COMMON, clock_node_ref1), clock_watchdog0 = MAKE_CLOCK_NAME(sysctl_resource_wdg0, CLK_SRC_GROUP_WDG, 0), clock_watchdog1 = MAKE_CLOCK_NAME(sysctl_resource_wdg1, CLK_SRC_GROUP_WDG, 1), clock_puart = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 0), - clock_pwdg = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 1), + clock_pwdg = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PWDG, 0), clock_eth0 = MAKE_CLOCK_NAME(sysctl_resource_eth0, CLK_SRC_GROUP_COMMON, clock_node_eth0), clock_sdp = MAKE_CLOCK_NAME(sysctl_resource_sdp0, CLK_SRC_GROUP_AXI, 0), clock_xdma = MAKE_CLOCK_NAME(sysctl_resource_dma1, CLK_SRC_GROUP_AXI, 1), @@ -154,8 +161,8 @@ typedef enum _clock_name { clock_mot0 = MAKE_CLOCK_NAME(sysctl_resource_mot0, CLK_SRC_GROUP_AHB, 6), clock_mot1 = MAKE_CLOCK_NAME(sysctl_resource_mot1, CLK_SRC_GROUP_AHB, 7), clock_acmp = MAKE_CLOCK_NAME(sysctl_resource_acmp, CLK_SRC_GROUP_AHB, 10), - clock_pdm = MAKE_CLOCK_NAME(sysctl_resource_i2spdm0, CLK_SRC_GROUP_AHB, 11), - clock_dao = MAKE_CLOCK_NAME(sysctl_resource_i2sdao, CLK_SRC_GROUP_AHB, 12), + clock_pdm = MAKE_CLOCK_NAME(sysctl_resource_i2spdm0, CLK_SRC_GROUP_I2S, 0), + clock_dao = MAKE_CLOCK_NAME(sysctl_resource_i2sdao, CLK_SRC_GROUP_I2S, 1), clock_msyn = MAKE_CLOCK_NAME(sysctl_resource_msyn, CLK_SRC_GROUP_AHB, 13), clock_ffa0 = MAKE_CLOCK_NAME(sysctl_resource_ffa0, CLK_SRC_GROUP_AHB, 14), clock_lmm0 = MAKE_CLOCK_NAME(sysctl_resource_lmm0, CLK_SRC_GROUP_CPU0, 0), @@ -182,7 +189,7 @@ typedef enum _clock_name { /* Clock sources */ clk_osc0clk0 = MAKE_CLOCK_NAME(sysctl_resource_xtal, CLK_SRC_GROUP_SRC, 0), - clk_pll0clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll1, CLK_SRC_GROUP_SRC, 1), + clk_pll0clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll0, CLK_SRC_GROUP_SRC, 1), clk_pll0clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll0, CLK_SRC_GROUP_SRC, 2), clk_pll0clk2 = MAKE_CLOCK_NAME(sysctl_resource_clk2_pll0, CLK_SRC_GROUP_SRC, 3), clk_pll1clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll1, CLK_SRC_GROUP_SRC, 4), @@ -219,6 +226,14 @@ uint32_t get_frequency_for_source(clock_source_t source); */ clk_src_t clock_get_source(clock_name_t clock_name); +/** + * @brief Get the IP clock divider + * Note:This API return the direct clock divider + * @param [in] clock_name clock name + * @return IP clock divider + */ +uint32_t clock_get_divider(clock_name_t clock_name); + /** * @brief Set ADC clock source * @param[in] clock_name ADC clock name @@ -296,6 +311,14 @@ void clock_add_to_group(clock_name_t clock_name, uint32_t group); */ void clock_remove_from_group(clock_name_t clock_name, uint32_t group); +/** + * @brief Check IP in specified group + * @param[in] clock_name IP clock name + * @param[in] group resource group index, valid value: 0/1/2/3 + * @return true if in group, false if not in group + */ +bool clock_check_in_group(clock_name_t clock_name, uint32_t group); + /** * @brief Disconnect the clock group from specified CPU * @param[in] group clock group index, value value is 0/1/2/3 diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_csr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_csr_regs.h index cc29018e112..5f43b12bd1a 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_csr_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_csr_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_dmamux_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_dmamux_regs.h index 640355344e8..e7f67339ea4 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_dmamux_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_dmamux_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_dmamux_src.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_dmamux_src.h index 3ded193a055..b0ed97d8e5f 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_dmamux_src.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_dmamux_src.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_enet_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_enet_soc_drv.h index c85abfc8ec9..688c6970c16 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_enet_soc_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_enet_soc_drv.h @@ -55,6 +55,9 @@ static inline hpm_stat_t enet_disable_lpi_interrupt(ENET_Type *ptr) static inline hpm_stat_t enet_rgmii_set_clock_delay(ENET_Type *ptr, uint8_t tx_delay, uint8_t rx_delay) { + (void) ptr; + (void) tx_delay; + (void) rx_delay; hpm_stat_t stat = status_fail; return stat; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_gpiom_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_gpiom_regs.h index 414dca8ee17..b7bc4e72702 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_gpiom_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_gpiom_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_gpiom_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_gpiom_soc_drv.h index 1377f27d619..be5605892a4 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_gpiom_soc_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_gpiom_soc_drv.h @@ -14,7 +14,7 @@ */ /* @brief gpiom control module */ -typedef enum hpm6300_gpiom_gpio { +typedef enum gpiom_gpio { gpiom_soc_gpio0 = 0, gpiom_core0_fast = 1, } gpiom_gpio_t; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_interrupt.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_interrupt.h index e2305ab7ed8..810971e255f 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_interrupt.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_interrupt.h @@ -7,8 +7,8 @@ #ifndef HPM_INTERRUPT_H #define HPM_INTERRUPT_H -#include "riscv/riscv_core.h" #include "hpm_common.h" +#include "hpm_csr_drv.h" #include "hpm_plic_drv.h" /** @@ -37,10 +37,10 @@ ATTR_ALWAYS_INLINE static inline void enable_global_irq(uint32_t mask) } /** - * @brief Disable global IRQ with mask return mstatus + * @brief Disable global IRQ with mask and return mstatus * * @param[in] mask interrupt mask to be disabled - * @retval current mstatus value before irq disabled + * @retval current mstatus value before irq mask is disabled */ ATTR_ALWAYS_INLINE static inline uint32_t disable_global_irq(uint32_t mask) { @@ -146,7 +146,6 @@ ATTR_ALWAYS_INLINE static inline void restore_s_global_irq(uint32_t mask) set_csr(CSR_SSTATUS, mask); } - /** * @brief Disable IRQ from interrupt controller for supervisor mode * @@ -565,6 +564,59 @@ ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack */ #if __riscv_flen == 32 +#ifdef __ICCRISCV__ +#define SAVE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fswsp ft0, 20*4\n\ + c.fswsp ft1, 21*4 \n\ + c.fswsp ft2, 22*4 \n\ + c.fswsp ft3, 23*4 \n\ + c.fswsp ft4, 24*4 \n\ + c.fswsp ft5, 25*4 \n\ + c.fswsp ft6, 26*4 \n\ + c.fswsp ft7, 27*4 \n\ + c.fswsp fa0, 28*4 \n\ + c.fswsp fa1, 29*4 \n\ + c.fswsp fa2, 30*4 \n\ + c.fswsp fa3, 31*4 \n\ + c.fswsp fa4, 32*4 \n\ + c.fswsp fa5, 33*4 \n\ + c.fswsp fa6, 34*4 \n\ + c.fswsp fa7, 35*4 \n\ + c.fswsp ft8, 36*4 \n\ + c.fswsp ft9, 37*4 \n\ + c.fswsp ft10, 38*4 \n\ + c.fswsp ft11, 39*4 \n");\ +} + +/* + * Restore FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack + */ +#define RESTORE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.flwsp ft0, 20*4\n\ + c.flwsp ft1, 21*4 \n\ + c.flwsp ft2, 22*4 \n\ + c.flwsp ft3, 23*4 \n\ + c.flwsp ft4, 24*4 \n\ + c.flwsp ft5, 25*4 \n\ + c.flwsp ft6, 26*4 \n\ + c.flwsp ft7, 27*4 \n\ + c.flwsp fa0, 28*4 \n\ + c.flwsp fa1, 29*4 \n\ + c.flwsp fa2, 30*4 \n\ + c.flwsp fa3, 31*4 \n\ + c.flwsp fa4, 32*4 \n\ + c.flwsp fa5, 33*4 \n\ + c.flwsp fa6, 34*4 \n\ + c.flwsp fa7, 35*4 \n\ + c.flwsp ft8, 36*4 \n\ + c.flwsp ft9, 37*4 \n\ + c.flwsp ft10, 38*4 \n\ + c.flwsp ft11, 39*4 \n");\ +} +#else /* __ICCRISCV__ not defined */ #define SAVE_FPU_CONTEXT() { \ __asm volatile("\n\ c.fswsp ft0, 20*4(sp)\n\ @@ -616,6 +668,60 @@ ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) c.flwsp ft10, 38*4(sp) \n\ c.flwsp ft11, 39*4(sp) \n");\ } +#endif +#else /*__riscv_flen == 64*/ +#ifdef __ICCRISCV__ +#define SAVE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fsdsp ft0, 20*4\n\ + c.fsdsp ft1, 22*4 \n\ + c.fsdsp ft2, 24*4 \n\ + c.fsdsp ft3, 26*4 \n\ + c.fsdsp ft4, 28*4 \n\ + c.fsdsp ft5, 30*4 \n\ + c.fsdsp ft6, 32*4 \n\ + c.fsdsp ft7, 34*4 \n\ + c.fsdsp fa0, 36*4 \n\ + c.fsdsp fa1, 38*4 \n\ + c.fsdsp fa2, 40*4 \n\ + c.fsdsp fa3, 42*4 \n\ + c.fsdsp fa4, 44*4 \n\ + c.fsdsp fa5, 46*4 \n\ + c.fsdsp fa6, 48*4 \n\ + c.fsdsp fa7, 50*4 \n\ + c.fsdsp ft8, 52*4 \n\ + c.fsdsp ft9, 54*4 \n\ + c.fsdsp ft10, 56*4 \n\ + c.fsdsp ft11, 58*4 \n");\ +} + +/* + * Restore FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack + */ +#define RESTORE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fldsp ft0, 20*4\n\ + c.fldsp ft1, 22*4 \n\ + c.fldsp ft2, 24*4 \n\ + c.fldsp ft3, 26*4 \n\ + c.fldsp ft4, 28*4 \n\ + c.fldsp ft5, 30*4 \n\ + c.fldsp ft6, 32*4 \n\ + c.fldsp ft7, 34*4 \n\ + c.fldsp fa0, 36*4 \n\ + c.fldsp fa1, 38*4 \n\ + c.fldsp fa2, 40*4 \n\ + c.fldsp fa3, 42*4 \n\ + c.fldsp fa4, 44*4 \n\ + c.fldsp fa5, 46*4 \n\ + c.fldsp fa6, 48*4 \n\ + c.fldsp fa7, 50*4 \n\ + c.fldsp ft8, 52*4 \n\ + c.fldsp ft9, 54*4 \n\ + c.fldsp ft10, 56*4 \n\ + c.fldsp ft11, 58*4 \n");\ +} #else /*__riscv_flen == 64*/ #define SAVE_FPU_CONTEXT() { \ __asm volatile("\n\ @@ -669,11 +775,71 @@ ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) c.fldsp ft11, 58*4(sp) \n");\ } #endif +#endif #else #define SAVE_FPU_CONTEXT() #define RESTORE_FPU_CONTEXT() #endif +#ifdef __ICCRISCV__ +/** + * @brief Save the caller registers based on the RISC-V ABI specification + */ +#define SAVE_CALLER_CONTEXT() { \ + __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\ + __asm volatile("\n\ + c.swsp ra, 0*4 \n\ + c.swsp t0, 1*4 \n\ + c.swsp t1, 2*4 \n\ + c.swsp t2, 3*4 \n\ + c.swsp s0, 4*4 \n\ + c.swsp s1, 5*4 \n\ + c.swsp a0, 6*4 \n\ + c.swsp a1, 7*4 \n\ + c.swsp a2, 8*4 \n\ + c.swsp a3, 9*4 \n\ + c.swsp a4, 10*4 \n\ + c.swsp a5, 11*4 \n\ + c.swsp a6, 12*4 \n\ + c.swsp a7, 13*4 \n\ + c.swsp s2, 14*4 \n\ + c.swsp s3, 15*4 \n\ + c.swsp t3, 16*4 \n\ + c.swsp t4, 17*4 \n\ + c.swsp t5, 18*4 \n\ + c.swsp t6, 19*4"); \ + SAVE_FPU_CONTEXT(); \ +} + +/** + * @brief Restore the caller registers based on the RISC-V ABI specification + */ +#define RESTORE_CALLER_CONTEXT() { \ + __asm volatile("\n\ + c.lwsp ra, 0*4 \n\ + c.lwsp t0, 1*4 \n\ + c.lwsp t1, 2*4 \n\ + c.lwsp t2, 3*4 \n\ + c.lwsp s0, 4*4 \n\ + c.lwsp s1, 5*4 \n\ + c.lwsp a0, 6*4 \n\ + c.lwsp a1, 7*4 \n\ + c.lwsp a2, 8*4 \n\ + c.lwsp a3, 9*4 \n\ + c.lwsp a4, 10*4 \n\ + c.lwsp a5, 11*4 \n\ + c.lwsp a6, 12*4 \n\ + c.lwsp a7, 13*4 \n\ + c.lwsp s2, 14*4 \n\ + c.lwsp s3, 15*4 \n\ + c.lwsp t3, 16*4 \n\ + c.lwsp t4, 17*4 \n\ + c.lwsp t5, 18*4 \n\ + c.lwsp t6, 19*4 \n");\ + RESTORE_FPU_CONTEXT(); \ + __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\ +} +#else /** * @brief Save the caller registers based on the RISC-V ABI specification */ @@ -731,14 +897,15 @@ ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) RESTORE_FPU_CONTEXT(); \ __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\ } +#endif #ifdef __riscv_flen #define SAVE_FPU_STATE() { \ - __asm volatile("frsr s1\n"); \ + __asm volatile("frcsr s1\n"); \ } #define RESTORE_FPU_STATE() { \ - __asm volatile("fssr s1\n"); \ + __asm volatile("fscsr s1\n"); \ } #else #define SAVE_FPU_STATE() @@ -751,14 +918,14 @@ ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) * NOTE: DSP context registers are stored at word offset 41 in the stack */ #define SAVE_DSP_CONTEXT() { \ - __asm volatile("rdov s0\n"); \ + __asm volatile("csrrs s0, %0, x0\n" ::"i"(CSR_UCODE):); \ } /* * @brief Restore DSP context * @note DSP context registers are stored at word offset 41 in the stack */ #define RESTORE_DSP_CONTEXT() {\ - __asm volatile("csrw ucode, s0\n"); \ + __asm volatile("csrw %0, s0\n" ::"i"(CSR_UCODE):); \ } #else @@ -780,25 +947,17 @@ ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) csrr s3, mstatus \n");\ SAVE_FPU_STATE(); \ SAVE_DSP_CONTEXT(); \ - __asm volatile ("\n\ - c.li a5, 8\n\ - csrs mstatus, a5\n"); \ + __asm volatile("csrsi mstatus, 8"); \ } /* * @brief Complete IRQ Handling */ #define COMPLETE_IRQ_HANDLING_M(irq_num) { \ - __asm volatile("\n\ - lui a5, 0x1\n\ - addi a5, a5, -2048\n\ - csrc mie, a5\n"); \ - __asm volatile("\n\ - lui a4, 0xe4200\n");\ + __asm volatile("csrci mstatus, 8"); \ + __asm volatile("lui a4, 0xe4200"); \ __asm volatile("li a3, %0" : : "i" (irq_num) :); \ - __asm volatile("sw a3, 4(a4)\n\ - fence io, io\n"); \ - __asm volatile("csrs mie, a5"); \ + __asm volatile("sw a3, 4(a4)"); \ } /* @@ -824,24 +983,15 @@ ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) csrr s3, sstatus \n");\ SAVE_FPU_STATE(); \ SAVE_DSP_CONTEXT(); \ - __asm volatile ("\n\ - c.li a5, 8\n\ - csrs sstatus, a5\n"); \ + __asm volatile("csrsi sstatus, 2"); \ } #define COMPLETE_IRQ_HANDLING_S(irq_num) {\ - __asm volatile("\n\ - lui a5, 0x1\n\ - addi a5, a5, -2048\n\ - csrc sie, a5\n"); \ - __asm volatile("\n\ - lui a4, 0xe4201\n");\ + __asm volatile("csrci sstatus, 2"); \ + __asm volatile("lui a4, 0xe4201"); \ __asm volatile("li a3, %0" : : "i" (irq_num) :); \ - __asm volatile("sw a3, 4(a4)\n\ - fence io, io\n"); \ - __asm volatile("csrs sie, a5"); \ + __asm volatile("sw a3, 4(a4)"); \ } - /* * @brief Exit Nested IRQ Handling at supervisor mode * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: @@ -874,18 +1024,6 @@ ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) RESTORE_FCSR() \ RESTORE_UCODE() -/* - * @brief Nested IRQ exit macro : Restore CSRs - * @param[in] irq Target interrupt number - */ -#define NESTED_VPLIC_COMPLETE_INTERRUPT(irq) \ -do { \ - clear_csr(CSR_MIE, CSR_MIP_MEIP_MASK); \ - __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq); \ - __asm volatile("fence io, io"); \ - set_csr(CSR_MIE, CSR_MIP_MEIP_MASK); \ -} while (0) - #ifdef __cplusplus #define EXTERN_C extern "C" #else @@ -914,6 +1052,7 @@ void ISR_NAME_M(irq_num)(void) \ COMPLETE_IRQ_HANDLING_M(irq_num);\ EXIT_NESTED_IRQ_HANDLING_M();\ RESTORE_CALLER_CONTEXT();\ + __asm volatile("fence io, io");\ __asm volatile("mret\n");\ } @@ -934,6 +1073,7 @@ void ISR_NAME_S(irq_num)(void) {\ COMPLETE_IRQ_HANDLING_S(irq_num);\ EXIT_NESTED_IRQ_HANDLING_S();\ RESTORE_CALLER_CONTEXT();\ + __asm volatile("fence io, io");\ __asm volatile("sret\n");\ } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ioc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ioc_regs.h index cf272e6f794..7bac3840655 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ioc_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ioc_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_iomux.h index b2f71da5d0f..1a02f60cd65 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_iomux.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_iomux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_l1c_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_l1c_drv.h index e328193a072..1f1a21639a2 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_l1c_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_l1c_drv.h @@ -7,8 +7,8 @@ #ifndef _HPM_L1_CACHE_H #define _HPM_L1_CACHE_H -#include "riscv/riscv_core.h" #include "hpm_common.h" +#include "hpm_csr_drv.h" #include "hpm_soc.h" /** diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_misc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_misc.h index d4ff0c66711..e81a74fa29f 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_misc.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_misc.h @@ -40,12 +40,14 @@ /* map core local memory(DLM/ILM) to system address */ static inline uint32_t core_local_mem_to_sys_address(uint8_t core_id, uint32_t addr) { + (void) core_id; return addr; } /* map system address to core local memory(DLM/ILM) */ static inline uint32_t sys_address_to_core_local_mem(uint8_t core_id, uint32_t addr) { + (void) core_id; return addr; } #endif /* HPM_MISC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_otp_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_otp_drv.h index 8c9559a9861..b61c805a1df 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_otp_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_otp_drv.h @@ -118,7 +118,7 @@ hpm_stat_t otp_set_configurable_region(uint32_t start, uint32_t num_of_words); /** * @return Write data to OTP shadow register * @param [in] addr OTP word index - * @param [val] val Data to be written + * @param [in] val Data to be written * @return API execution status */ hpm_stat_t otp_write_shadow_register(uint32_t addr, uint32_t val); diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pcfg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pcfg_drv.h index e99e0837a59..c5f8de4b942 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pcfg_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pcfg_drv.h @@ -20,11 +20,9 @@ */ #define PCFG_CLOCK_GATE_MODE_ALWAYS_ON (0x3UL) #define PCFG_CLOCK_GATE_MODE_ALWAYS_OFF (0x2UL) -#define PCFG_CLOCK_GATE_MODE_ALWAYS_FOLLOW_FLOW (0x1UL) #define PCFG_PERIPH_KEEP_CLOCK_ON(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_ON << (p)) #define PCFG_PERIPH_KEEP_CLOCK_OFF(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_OFF << (p)) -#define PCFG_PERIPH_SET_CLOCK_AUTO(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_FOLLOW_FLOW << (p)) /* @brief PCFG irc24m reference */ typedef enum { @@ -153,26 +151,6 @@ static inline void pcfg_bandgap_reload_trim(PCFG_Type *ptr) ptr->BANDGAP &= ~PCFG_BANDGAP_VBG_TRIMMED_MASK; } -/** - * @brief turn off LDO 1V - * - * @param[in] ptr base address - */ -static inline void pcfg_ldo1p1_turn_off(PCFG_Type *ptr) -{ - ptr->LDO1P1 &= ~PCFG_LDO1P1_ENABLE_MASK; -} - -/** - * @brief turn of LDO 1V - * - * @param[in] ptr base address - */ -static inline void pcfg_ldo1p1_turn_on(PCFG_Type *ptr) -{ - ptr->LDO1P1 |= PCFG_LDO1P1_ENABLE_MASK; -} - /** * @brief turn off LDO2P5 * @@ -229,12 +207,12 @@ static inline void pcfg_dcdc_set_mode(PCFG_Type *ptr, uint8_t mode) * * @param[in] ptr base address * @param[in] limit current limit at low power mode - * @param[in] over_limit set to true means current is greater than limit + * @param[in] over_limit unused parameter, will be discarded */ static inline void pcfg_dcdc_set_lp_current_limit(PCFG_Type *ptr, pcfg_dcdc_lp_current_limit_t limit, bool over_limit) { - ptr->DCDC_PROT = (ptr->DCDC_PROT & ~(PCFG_DCDC_PROT_ILIMIT_LP_MASK | PCFG_DCDC_PROT_OVERLOAD_LP_MASK)) - | PCFG_DCDC_PROT_ILIMIT_LP_SET(limit) | PCFG_DCDC_PROT_OVERLOAD_LP_SET(over_limit); + (void) over_limit; + ptr->DCDC_PROT = (ptr->DCDC_PROT & ~PCFG_DCDC_PROT_ILIMIT_LP_MASK) | PCFG_DCDC_PROT_ILIMIT_LP_SET(limit); } /** diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pcfg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pcfg_regs.h index b05080feacc..cfc5f1eba37 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pcfg_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pcfg_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -106,18 +106,6 @@ typedef struct { #define PCFG_BANDGAP_VBG_P50_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_P50_TRIM_MASK) >> PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) /* Bitfield definition for register: LDO1P1 */ -/* - * ENABLE (RW) - * - * LDO enable - * 0: turn off LDO - * 1: turn on LDO - */ -#define PCFG_LDO1P1_ENABLE_MASK (0x10000UL) -#define PCFG_LDO1P1_ENABLE_SHIFT (16U) -#define PCFG_LDO1P1_ENABLE_SET(x) (((uint32_t)(x) << PCFG_LDO1P1_ENABLE_SHIFT) & PCFG_LDO1P1_ENABLE_MASK) -#define PCFG_LDO1P1_ENABLE_GET(x) (((uint32_t)(x) & PCFG_LDO1P1_ENABLE_MASK) >> PCFG_LDO1P1_ENABLE_SHIFT) - /* * VOLT (RW) * @@ -186,7 +174,7 @@ typedef struct { * MODE (RW) * * DCDC work mode - * XX0: trun off + * XX0: turn off * 001: basic mode * 011: generic mode * 101: automatic mode @@ -240,7 +228,7 @@ typedef struct { #define PCFG_DCDC_PROT_ILIMIT_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) >> PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) /* - * OVERLOAD_LP (RW) + * OVERLOAD_LP (RO) * * over current in low power mode * 0: current is below setting @@ -248,7 +236,6 @@ typedef struct { */ #define PCFG_DCDC_PROT_OVERLOAD_LP_MASK (0x1000000UL) #define PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT (24U) -#define PCFG_DCDC_PROT_OVERLOAD_LP_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT) & PCFG_DCDC_PROT_OVERLOAD_LP_MASK) #define PCFG_DCDC_PROT_OVERLOAD_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERLOAD_LP_MASK) >> PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT) /* @@ -277,7 +264,7 @@ typedef struct { /* * DISABLE_OVERVOLTAGE (RW) * - * ouput over voltage protection + * output over voltage protection * 0: protection enabled, DCDC will shut down is output voltage is unexpected high * 1: protection disabled, DCDC continue to adjust output voltage */ @@ -301,7 +288,7 @@ typedef struct { * DISABLE_SHORT (RW) * * disable output short circuit protection - * 0: short circuits protection enabled, DCDC shut down if short circuit on ouput detected + * 0: short circuits protection enabled, DCDC shut down if short circuit on output detected * 1: short circuit protection disabled */ #define PCFG_DCDC_PROT_DISABLE_SHORT_MASK (0x80U) @@ -418,18 +405,6 @@ typedef struct { #define PCFG_DCDC_ADVMODE_EN_FF_LOOP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) #define PCFG_DCDC_ADVMODE_EN_FF_LOOP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) >> PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) -/* - * EN_AUTOLP (RW) - * - * enable auto enter low power mode - * 0: do not enter low power mode - * 1: enter low power mode if current is detected low - */ -#define PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK (0x10U) -#define PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT (4U) -#define PCFG_DCDC_ADVMODE_EN_AUTOLP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT) & PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK) -#define PCFG_DCDC_ADVMODE_EN_AUTOLP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK) >> PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT) - /* * EN_DCM_EXIT (RW) * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pgpr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pgpr_regs.h index 0369149bdd6..acf20cfecd5 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pgpr_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pgpr_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pmic_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pmic_iomux.h index 8990b9849e6..5bd62a86bfa 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pmic_iomux.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pmic_iomux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -9,53 +9,85 @@ #ifndef HPM_PMIC_IOMUX_H #define HPM_PMIC_IOMUX_H -/* IOC_PY00_FUNC_CTL function mux definitions */ -#define IOC_PY00_FUNC_CTL_PGPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY00_FUNC_CTL_JTAG_TDO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY00_FUNC_CTL_SOC_PY_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PY01_FUNC_CTL function mux definitions */ -#define IOC_PY01_FUNC_CTL_PGPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY01_FUNC_CTL_JTAG_TDI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY01_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY01_FUNC_CTL_SOC_PY_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PY02_FUNC_CTL function mux definitions */ -#define IOC_PY02_FUNC_CTL_PGPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY02_FUNC_CTL_JTAG_TCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY02_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY02_FUNC_CTL_SOC_PY_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PY03_FUNC_CTL function mux definitions */ -#define IOC_PY03_FUNC_CTL_PGPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY03_FUNC_CTL_JTAG_TMS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY03_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY03_FUNC_CTL_SOC_PY_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PY04_FUNC_CTL function mux definitions */ -#define IOC_PY04_FUNC_CTL_PGPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY04_FUNC_CTL_JTAG_TRST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY04_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY04_FUNC_CTL_SOC_PY_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PY05_FUNC_CTL function mux definitions */ -#define IOC_PY05_FUNC_CTL_PGPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY05_FUNC_CTL_PWDG_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY05_FUNC_CTL_PTMR_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY05_FUNC_CTL_SOC_PY_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PY06_FUNC_CTL function mux definitions */ -#define IOC_PY06_FUNC_CTL_PGPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY06_FUNC_CTL_PUART_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY06_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY06_FUNC_CTL_SOC_PY_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PY07_FUNC_CTL function mux definitions */ -#define IOC_PY07_FUNC_CTL_PGPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY07_FUNC_CTL_PUART_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY07_FUNC_CTL_PTMR_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY07_FUNC_CTL_SOC_PY_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +/* PIOC_PY00_FUNC_CTL function mux definitions */ +#define IOC_PY00_FUNC_CTL_PGPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY00_FUNC_CTL_PGPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY00_FUNC_CTL_JTAG_TDO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY00_FUNC_CTL_JTAG_TDO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY00_FUNC_CTL_SOC_PY_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY00_FUNC_CTL_SOC_PY_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY01_FUNC_CTL function mux definitions */ +#define IOC_PY01_FUNC_CTL_PGPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY01_FUNC_CTL_PGPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY01_FUNC_CTL_JTAG_TDI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY01_FUNC_CTL_JTAG_TDI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY01_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY01_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY01_FUNC_CTL_SOC_PY_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY01_FUNC_CTL_SOC_PY_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY02_FUNC_CTL function mux definitions */ +#define IOC_PY02_FUNC_CTL_PGPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY02_FUNC_CTL_PGPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY02_FUNC_CTL_JTAG_TCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY02_FUNC_CTL_JTAG_TCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY02_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY02_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY02_FUNC_CTL_SOC_PY_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY02_FUNC_CTL_SOC_PY_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY03_FUNC_CTL function mux definitions */ +#define IOC_PY03_FUNC_CTL_PGPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY03_FUNC_CTL_PGPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY03_FUNC_CTL_JTAG_TMS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY03_FUNC_CTL_JTAG_TMS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY03_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY03_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY03_FUNC_CTL_SOC_PY_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY03_FUNC_CTL_SOC_PY_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY04_FUNC_CTL function mux definitions */ +#define IOC_PY04_FUNC_CTL_PGPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY04_FUNC_CTL_PGPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY04_FUNC_CTL_JTAG_TRST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY04_FUNC_CTL_JTAG_TRST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY04_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY04_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY04_FUNC_CTL_SOC_PY_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY04_FUNC_CTL_SOC_PY_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY05_FUNC_CTL function mux definitions */ +#define IOC_PY05_FUNC_CTL_PGPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY05_FUNC_CTL_PGPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY05_FUNC_CTL_PWDG_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY05_FUNC_CTL_PWDG_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY05_FUNC_CTL_PTMR_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY05_FUNC_CTL_PTMR_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY05_FUNC_CTL_SOC_PY_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY05_FUNC_CTL_SOC_PY_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY06_FUNC_CTL function mux definitions */ +#define IOC_PY06_FUNC_CTL_PGPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY06_FUNC_CTL_PGPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY06_FUNC_CTL_PUART_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY06_FUNC_CTL_PUART_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY06_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY06_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY06_FUNC_CTL_SOC_PY_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY06_FUNC_CTL_SOC_PY_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY07_FUNC_CTL function mux definitions */ +#define IOC_PY07_FUNC_CTL_PGPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY07_FUNC_CTL_PGPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY07_FUNC_CTL_PUART_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY07_FUNC_CTL_PUART_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY07_FUNC_CTL_PTMR_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY07_FUNC_CTL_PTMR_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY07_FUNC_CTL_SOC_PY_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY07_FUNC_CTL_SOC_PY_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #endif /* HPM_PMIC_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ppor_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ppor_drv.h index b1eb6e6ac53..687508cc684 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ppor_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ppor_drv.h @@ -11,15 +11,7 @@ typedef enum { ppor_reset_brownout = 1 << 0, - ppor_reset_temperature = 1 << 1, - ppor_reset_pin = 1 << 2, ppor_reset_debug = 1 << 4, - ppor_reset_security_violation = 1 << 5, - ppor_reset_jtag = 1 << 6, - ppor_reset_cpu0_lockup = 1 << 8, - ppor_reset_cpu1_lockup = 1 << 9, - ppor_reset_cpu0_request = 1 << 10, - ppor_reset_cpu1_request = 1 << 11, ppor_reset_wdog0 = 1 << 16, ppor_reset_wdog1 = 1 << 17, ppor_reset_wdog2 = 1 << 18, @@ -92,7 +84,31 @@ static inline uint32_t ppor_reset_get_flags(PPOR_Type *ptr) */ static inline void ppor_reset_clear_flags(PPOR_Type *ptr, uint32_t mask) { - ptr->RESET_FLAG |= mask; + ptr->RESET_FLAG = mask; +} + +/* + * get reset hold + */ +static inline uint32_t ppor_reset_get_hold(PPOR_Type *ptr) +{ + return ptr->RESET_HOLD; +} + +/* + * set reset hold + */ +static inline void ppor_reset_set_hold_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_HOLD |= mask; +} + +/* + * clear reset hold + */ +static inline void ppor_reset_clear_hold_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_HOLD &= ~mask; } /* @@ -100,7 +116,7 @@ static inline void ppor_reset_clear_flags(PPOR_Type *ptr, uint32_t mask) */ static inline void ppor_reset_set_cold_reset_enable(PPOR_Type *ptr, uint32_t mask) { - ptr->RESET_COLD = mask; + ptr->RESET_COLD |= mask; } /* @@ -116,7 +132,7 @@ static inline void ppor_reset_clear_cold_reset_enable(PPOR_Type *ptr, uint32_t m */ static inline void ppor_reset_set_hot_reset_enable(PPOR_Type *ptr, uint32_t mask) { - ptr->RESET_HOT = mask; + ptr->RESET_HOT |= mask; } /* diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ppor_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ppor_regs.h index 21cb6fc2370..7ce378b07da 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ppor_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ppor_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_romapi.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_romapi.h index 05edd7fd573..d814cc27647 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_romapi.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_romapi.h @@ -344,7 +344,7 @@ typedef struct { /**< Bootloader API table: copyright string address */ const char *copyright; /**< Bootloader API table: run_bootloader API */ - const hpm_stat_t (*run_bootloader)(void *arg); + hpm_stat_t (*run_bootloader)(void *arg); /**< Bootloader API table: otp driver interface address */ const otp_driver_interface_t *otp_driver_if; /**< Bootloader API table: xpi driver interface address */ @@ -748,7 +748,7 @@ static inline bool rom_xpi_nor_exip_region_config(XPI_Type *base, uint32_t index /** * @brief Disable EXiP Feature on specified EXiP Region - * @@param [in] base XPI base address + * @param [in] base XPI base address * @param [in] index EXiP Region index */ ATTR_RAMFUNC @@ -768,7 +768,7 @@ static inline void rom_xpi_nor_exip_region_disable(XPI_Type *base, uint32_t inde /** * @brief Enable global EXiP logic - * @@param [in] base XPI base address + * @param [in] base XPI base address */ ATTR_RAMFUNC static inline void rom_xpi_nor_exip_enable(XPI_Type *base) @@ -785,7 +785,7 @@ static inline void rom_xpi_nor_exip_enable(XPI_Type *base) /** * @brief Disable global EXiP logic - * @@param [in] base XPI base address + * @param [in] base XPI base address */ ATTR_RAMFUNC static inline void rom_xpi_nor_exip_disable(XPI_Type *base) @@ -1065,6 +1065,7 @@ static inline hpm_stat_t rom_sm4_crypt_ecb(sm4_context_t *ctx, uint32_t mode, ui * @param [in] ctx SM4 context * @param [in] mode SM4 operation: 1 - ENCRYPT, 0 - DECRYPT * @param [in] length Data length for SM4 encryption/decryption + * @param [in] iv The initial vector for SM4 CBC crypto operation * @param [in] input Input data * @param [out] output Output data * @return API execution status diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sdxc_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sdxc_soc_drv.h index 76d3dc52fe7..fb321b14239 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sdxc_soc_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sdxc_soc_drv.h @@ -33,8 +33,9 @@ static inline void sdxc_disable_freq_selection(SDXC_Type *base) static inline void sdxc_set_clock_divider(SDXC_Type *base, uint32_t div) { - base->MISC_CTRL0 = (base->MISC_CTRL0 & ~SDXC_MISC_CTRL0_FREQ_SEL_SW_MASK) | SDXC_MISC_CTRL0_FREQ_SEL_SW_SET(div - 1U) | - SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK; + base->MISC_CTRL0 = + (base->MISC_CTRL0 & ~SDXC_MISC_CTRL0_FREQ_SEL_SW_MASK) | SDXC_MISC_CTRL0_FREQ_SEL_SW_SET(div - 1U) | + SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK; } static inline uint32_t sdxc_get_clock_divider(SDXC_Type *base) @@ -84,6 +85,39 @@ static inline void sdxc_set_cardclk_delay_chain(SDXC_Type *base, uint32_t number SDXC_MISC_CTRL1_CARDCLK_DLYSEL_SET(number_of_delaycells); } +/** + * @brief Set SDXC data strobe delay chain + * @param [in] base SDXC base + * @param [in] num_of_delaycells Number of delay cells for Data strobe + */ +static inline void sdxc_set_data_strobe_delay(SDXC_Type *base, uint8_t num_of_delaycells) +{ + base->MISC_CTRL1 = (base->MISC_CTRL1 & ~SDXC_MISC_CTRL1_STROBE_DLYSEL_MASK) | + SDXC_MISC_CTRL1_STROBE_DLYSEL_SET(num_of_delaycells); +} + +static inline uint32_t sdxc_get_default_strobe_delay(SDXC_Type *base) +{ + (void) base; + return 0; +} + +static inline uint32_t sdxc_get_default_cardclk_delay_chain(SDXC_Type *base, uint32_t clock_freq) +{ + (void) base; + uint32_t num_delaycells = 3; + if (clock_freq <= 52000000) { + num_delaycells = 26; + } + return num_delaycells; +} + +static inline bool sdxc_is_ddr50_supported(SDXC_Type *base) +{ + (void) base; + return false; +} + #if defined(__cplusplus) } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ses_reg.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ses_reg.xml index ee67d133ae0..dce9f675356 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ses_reg.xml +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ses_reg.xml @@ -2821,6 +2821,26 @@ + + + + + + + + + + + + + + + + + + + + @@ -2861,6 +2881,126 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -2901,6 +3041,126 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -2941,6 +3201,126 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -3173,9 +3553,6 @@ - - - @@ -3493,7 +3870,6 @@ - @@ -3508,7 +3884,7 @@ - + @@ -3522,7 +3898,7 @@ - + @@ -3634,7 +4010,6 @@ - @@ -3876,9 +4251,6 @@ - - - @@ -4196,7 +4568,6 @@ - @@ -4211,7 +4582,7 @@ - + @@ -4225,7 +4596,7 @@ - + @@ -4337,7 +4708,6 @@ - @@ -4579,9 +4949,6 @@ - - - @@ -4899,7 +5266,6 @@ - @@ -4914,7 +5280,7 @@ - + @@ -4928,7 +5294,7 @@ - + @@ -5040,7 +5406,6 @@ - @@ -5240,7 +5605,6 @@ - @@ -5254,7 +5618,6 @@ - @@ -5282,7 +5645,6 @@ - @@ -5375,7 +5737,6 @@ - @@ -5468,7 +5829,6 @@ - @@ -5561,7 +5921,6 @@ - @@ -5654,7 +6013,6 @@ - @@ -5718,10 +6076,12 @@ + + + - @@ -5785,10 +6145,12 @@ + + + - @@ -5852,10 +6214,12 @@ + + + - @@ -5919,10 +6283,12 @@ + + + - @@ -5986,10 +6352,12 @@ + + + - @@ -6053,10 +6421,12 @@ + + + - @@ -6120,10 +6490,12 @@ + + + - @@ -6187,10 +6559,12 @@ + + + - @@ -6254,6 +6628,9 @@ + + + @@ -6833,20 +7210,16 @@ - - - - @@ -6859,7 +7232,6 @@ - @@ -6879,20 +7251,16 @@ - - - - @@ -6905,7 +7273,6 @@ - @@ -6928,7 +7295,6 @@ - @@ -6974,7 +7340,6 @@ - @@ -7037,6 +7402,12 @@ + + + + + + @@ -7800,48 +8171,33 @@ - - - - - - - - - - - - - - - @@ -7947,7 +8303,6 @@ - @@ -7975,17 +8330,14 @@ - - - @@ -8012,7 +8364,6 @@ - @@ -8032,10 +8383,7 @@ - - - @@ -8065,7 +8413,6 @@ - @@ -8093,17 +8440,14 @@ - - - @@ -8130,7 +8474,6 @@ - @@ -8150,10 +8493,7 @@ - - - @@ -8288,12 +8628,10 @@ - - @@ -8446,196 +8784,124 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -8740,7 +9006,6 @@ - @@ -8817,7 +9082,6 @@ - @@ -8916,145 +9180,121 @@ - - - - - - - - - - - - - - - - - - - - - - - - @@ -9064,12 +9304,10 @@ - - @@ -9222,196 +9460,124 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -9516,7 +9682,6 @@ - @@ -9593,7 +9758,6 @@ - @@ -9692,160 +9856,131 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -9853,7 +9988,6 @@ - @@ -9861,10 +9995,6 @@ - - - - @@ -9874,10 +10004,6 @@ - - - - @@ -9887,10 +10013,6 @@ - - - - @@ -9900,10 +10022,6 @@ - - - - @@ -9913,10 +10031,6 @@ - - - - @@ -9925,8 +10039,6 @@ - - @@ -9943,8 +10055,6 @@ - - @@ -9961,8 +10071,6 @@ - - @@ -9979,8 +10087,6 @@ - - @@ -10015,16 +10121,11 @@ - - - - - @@ -10032,7 +10133,6 @@ - @@ -10040,10 +10140,6 @@ - - - - @@ -10053,10 +10149,6 @@ - - - - @@ -10066,10 +10158,6 @@ - - - - @@ -10079,10 +10167,6 @@ - - - - @@ -10092,10 +10176,6 @@ - - - - @@ -10104,8 +10184,6 @@ - - @@ -10122,8 +10200,6 @@ - - @@ -10140,8 +10216,6 @@ - - @@ -10158,8 +10232,6 @@ - - @@ -10206,7 +10278,6 @@ - @@ -10363,7 +10434,6 @@ - @@ -11997,54 +12067,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -12316,11 +12338,16 @@ + + + + + + - @@ -12363,7 +12390,6 @@ - @@ -12406,7 +12432,6 @@ - @@ -12449,7 +12474,6 @@ - @@ -12491,7 +12515,6 @@ - @@ -12510,7 +12533,6 @@ - @@ -12535,7 +12557,6 @@ - @@ -12578,7 +12599,6 @@ - @@ -12621,7 +12641,6 @@ - @@ -12664,7 +12683,6 @@ - @@ -12706,7 +12724,6 @@ - @@ -12725,7 +12742,6 @@ - @@ -12750,7 +12766,6 @@ - @@ -12793,7 +12808,6 @@ - @@ -12836,7 +12850,6 @@ - @@ -12879,7 +12892,6 @@ - @@ -12921,7 +12933,6 @@ - @@ -12940,7 +12951,6 @@ - @@ -12965,7 +12975,6 @@ - @@ -13008,7 +13017,6 @@ - @@ -13051,7 +13059,6 @@ - @@ -13094,7 +13101,6 @@ - @@ -13136,7 +13142,6 @@ - @@ -13155,7 +13160,6 @@ - @@ -13180,7 +13184,6 @@ - @@ -13223,7 +13226,6 @@ - @@ -13266,7 +13268,6 @@ - @@ -13309,7 +13310,6 @@ - @@ -13351,7 +13351,6 @@ - @@ -13370,7 +13369,6 @@ - @@ -13395,7 +13393,6 @@ - @@ -13438,7 +13435,6 @@ - @@ -13481,7 +13477,6 @@ - @@ -13524,7 +13519,6 @@ - @@ -13566,7 +13560,6 @@ - @@ -13585,7 +13578,6 @@ - @@ -13705,12 +13697,12 @@ - - + + - - + + @@ -13756,23 +13748,23 @@ - + - - + + - - + + - - + + - - + + @@ -14299,12 +14291,6 @@ - - - - - - @@ -14349,11 +14335,9 @@ - - @@ -14366,7 +14350,6 @@ - @@ -14384,15 +14367,12 @@ - - - @@ -14401,15 +14381,12 @@ - - - @@ -14418,17 +14395,14 @@ - - - @@ -14441,7 +14415,6 @@ - @@ -14459,15 +14432,12 @@ - - - @@ -14476,15 +14446,12 @@ - - - @@ -14493,17 +14460,14 @@ - - - @@ -14516,7 +14480,6 @@ - @@ -14534,15 +14497,12 @@ - - - @@ -14551,15 +14511,12 @@ - - - @@ -14568,17 +14525,14 @@ - - - @@ -14591,7 +14545,6 @@ - @@ -14609,15 +14562,12 @@ - - - @@ -14626,15 +14576,12 @@ - - - @@ -14643,7 +14590,6 @@ - @@ -14653,13 +14599,11 @@ - - @@ -14668,36 +14612,27 @@ - - - - - - - - - @@ -14706,9 +14641,7 @@ - - @@ -14758,14 +14691,12 @@ - - @@ -14908,17 +14839,14 @@ - - - @@ -14929,7 +14857,6 @@ - @@ -14955,7 +14882,6 @@ - @@ -23547,7 +23473,6 @@ - @@ -23585,7 +23510,6 @@ - @@ -23877,6 +23801,12 @@ + + + + + + @@ -23921,6 +23851,12 @@ + + + + + + @@ -23985,6 +23921,21 @@ + + + + + + + + + + + + + + + @@ -24051,29 +24002,29 @@ - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + @@ -24302,4 +24253,4 @@ - \ No newline at end of file + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ses_riscv_cpu_regs.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ses_riscv_cpu_regs.xml index de6e896482d..9e30fbc73a7 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ses_riscv_cpu_regs.xml +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ses_riscv_cpu_regs.xml @@ -767,4 +767,4 @@ - \ No newline at end of file + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_soc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_soc.h index 1ce68568072..fc35bd7850d 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_soc.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_soc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -11,84 +11,84 @@ /* List of external IRQs */ -#define IRQn_GPIO0_A 1 /* GPIO0_A IRQ */ -#define IRQn_GPIO0_B 2 /* GPIO0_B IRQ */ -#define IRQn_GPIO0_C 3 /* GPIO0_C IRQ */ -#define IRQn_GPIO0_D 4 /* GPIO0_D IRQ */ -#define IRQn_GPIO0_X 5 /* GPIO0_X IRQ */ -#define IRQn_GPIO0_Y 6 /* GPIO0_Y IRQ */ -#define IRQn_GPIO0_Z 7 /* GPIO0_Z IRQ */ -#define IRQn_ADC0 8 /* ADC0 IRQ */ -#define IRQn_ADC1 9 /* ADC1 IRQ */ -#define IRQn_ADC2 10 /* ADC2 IRQ */ -#define IRQn_DAC 11 /* DAC IRQ */ -#define IRQn_ACMP_0 12 /* ACMP[0] IRQ */ -#define IRQn_ACMP_1 13 /* ACMP[1] IRQ */ -#define IRQn_SPI0 14 /* SPI0 IRQ */ -#define IRQn_SPI1 15 /* SPI1 IRQ */ -#define IRQn_SPI2 16 /* SPI2 IRQ */ -#define IRQn_SPI3 17 /* SPI3 IRQ */ -#define IRQn_UART0 18 /* UART0 IRQ */ -#define IRQn_UART1 19 /* UART1 IRQ */ -#define IRQn_UART2 20 /* UART2 IRQ */ -#define IRQn_UART3 21 /* UART3 IRQ */ -#define IRQn_UART4 22 /* UART4 IRQ */ -#define IRQn_UART5 23 /* UART5 IRQ */ -#define IRQn_UART6 24 /* UART6 IRQ */ -#define IRQn_UART7 25 /* UART7 IRQ */ -#define IRQn_CAN0 26 /* CAN0 IRQ */ -#define IRQn_CAN1 27 /* CAN1 IRQ */ -#define IRQn_PTPC 28 /* PTPC IRQ */ -#define IRQn_WDG0 29 /* WDG0 IRQ */ -#define IRQn_WDG1 30 /* WDG1 IRQ */ -#define IRQn_TSNS 31 /* TSNS IRQ */ -#define IRQn_MBX0A 32 /* MBX0A IRQ */ -#define IRQn_MBX0B 33 /* MBX0B IRQ */ -#define IRQn_GPTMR0 34 /* GPTMR0 IRQ */ -#define IRQn_GPTMR1 35 /* GPTMR1 IRQ */ -#define IRQn_GPTMR2 36 /* GPTMR2 IRQ */ -#define IRQn_GPTMR3 37 /* GPTMR3 IRQ */ -#define IRQn_I2C0 38 /* I2C0 IRQ */ -#define IRQn_I2C1 39 /* I2C1 IRQ */ -#define IRQn_I2C2 40 /* I2C2 IRQ */ -#define IRQn_I2C3 41 /* I2C3 IRQ */ -#define IRQn_PWM0 42 /* PWM0 IRQ */ -#define IRQn_HALL0 43 /* HALL0 IRQ */ -#define IRQn_QEI0 44 /* QEI0 IRQ */ -#define IRQn_PWM1 45 /* PWM1 IRQ */ -#define IRQn_HALL1 46 /* HALL1 IRQ */ -#define IRQn_QEI1 47 /* QEI1 IRQ */ -#define IRQn_SDP 48 /* SDP IRQ */ -#define IRQn_XPI0 49 /* XPI0 IRQ */ -#define IRQn_XPI1 50 /* XPI1 IRQ */ -#define IRQn_XDMA 51 /* XDMA IRQ */ -#define IRQn_HDMA 52 /* HDMA IRQ */ -#define IRQn_FEMC 53 /* FEMC IRQ */ -#define IRQn_RNG 54 /* RNG IRQ */ -#define IRQn_I2S0 55 /* I2S0 IRQ */ -#define IRQn_I2S1 56 /* I2S1 IRQ */ -#define IRQn_DAO 57 /* DAO IRQ */ -#define IRQn_PDM 58 /* PDM IRQ */ -#define IRQn_FFA 59 /* FFA IRQ */ -#define IRQn_NTMR0 60 /* NTMR0 IRQ */ -#define IRQn_USB0 61 /* USB0 IRQ */ -#define IRQn_ENET0 62 /* ENET0 IRQ */ -#define IRQn_SDXC0 63 /* SDXC0 IRQ */ -#define IRQn_PSEC 64 /* PSEC IRQ */ -#define IRQn_PGPIO 65 /* PGPIO IRQ */ -#define IRQn_PWDG 66 /* PWDG IRQ */ -#define IRQn_PTMR 67 /* PTMR IRQ */ -#define IRQn_PUART 68 /* PUART IRQ */ -#define IRQn_FUSE 69 /* FUSE IRQ */ -#define IRQn_SECMON 70 /* SECMON IRQ */ -#define IRQn_RTC 71 /* RTC IRQ */ -#define IRQn_BUTN 72 /* BUTN IRQ */ -#define IRQn_BGPIO 73 /* BGPIO IRQ */ -#define IRQn_BVIO 74 /* BVIO IRQ */ -#define IRQn_BROWNOUT 75 /* BROWNOUT IRQ */ -#define IRQn_SYSCTL 76 /* SYSCTL IRQ */ -#define IRQn_DEBUG_0 77 /* DEBUG[0] IRQ */ -#define IRQn_DEBUG_1 78 /* DEBUG[1] IRQ */ +#define IRQn_GPIO0_A 1 /* GPIO0_A IRQ */ +#define IRQn_GPIO0_B 2 /* GPIO0_B IRQ */ +#define IRQn_GPIO0_C 3 /* GPIO0_C IRQ */ +#define IRQn_GPIO0_D 4 /* GPIO0_D IRQ */ +#define IRQn_GPIO0_X 5 /* GPIO0_X IRQ */ +#define IRQn_GPIO0_Y 6 /* GPIO0_Y IRQ */ +#define IRQn_GPIO0_Z 7 /* GPIO0_Z IRQ */ +#define IRQn_ADC0 8 /* ADC0 IRQ */ +#define IRQn_ADC1 9 /* ADC1 IRQ */ +#define IRQn_ADC2 10 /* ADC2 IRQ */ +#define IRQn_DAC 11 /* DAC IRQ */ +#define IRQn_ACMP_0 12 /* ACMP[0] IRQ */ +#define IRQn_ACMP_1 13 /* ACMP[1] IRQ */ +#define IRQn_SPI0 14 /* SPI0 IRQ */ +#define IRQn_SPI1 15 /* SPI1 IRQ */ +#define IRQn_SPI2 16 /* SPI2 IRQ */ +#define IRQn_SPI3 17 /* SPI3 IRQ */ +#define IRQn_UART0 18 /* UART0 IRQ */ +#define IRQn_UART1 19 /* UART1 IRQ */ +#define IRQn_UART2 20 /* UART2 IRQ */ +#define IRQn_UART3 21 /* UART3 IRQ */ +#define IRQn_UART4 22 /* UART4 IRQ */ +#define IRQn_UART5 23 /* UART5 IRQ */ +#define IRQn_UART6 24 /* UART6 IRQ */ +#define IRQn_UART7 25 /* UART7 IRQ */ +#define IRQn_CAN0 26 /* CAN0 IRQ */ +#define IRQn_CAN1 27 /* CAN1 IRQ */ +#define IRQn_PTPC 28 /* PTPC IRQ */ +#define IRQn_WDG0 29 /* WDG0 IRQ */ +#define IRQn_WDG1 30 /* WDG1 IRQ */ +#define IRQn_TSNS 31 /* TSNS IRQ */ +#define IRQn_MBX0A 32 /* MBX0A IRQ */ +#define IRQn_MBX0B 33 /* MBX0B IRQ */ +#define IRQn_GPTMR0 34 /* GPTMR0 IRQ */ +#define IRQn_GPTMR1 35 /* GPTMR1 IRQ */ +#define IRQn_GPTMR2 36 /* GPTMR2 IRQ */ +#define IRQn_GPTMR3 37 /* GPTMR3 IRQ */ +#define IRQn_I2C0 38 /* I2C0 IRQ */ +#define IRQn_I2C1 39 /* I2C1 IRQ */ +#define IRQn_I2C2 40 /* I2C2 IRQ */ +#define IRQn_I2C3 41 /* I2C3 IRQ */ +#define IRQn_PWM0 42 /* PWM0 IRQ */ +#define IRQn_HALL0 43 /* HALL0 IRQ */ +#define IRQn_QEI0 44 /* QEI0 IRQ */ +#define IRQn_PWM1 45 /* PWM1 IRQ */ +#define IRQn_HALL1 46 /* HALL1 IRQ */ +#define IRQn_QEI1 47 /* QEI1 IRQ */ +#define IRQn_SDP 48 /* SDP IRQ */ +#define IRQn_XPI0 49 /* XPI0 IRQ */ +#define IRQn_XPI1 50 /* XPI1 IRQ */ +#define IRQn_XDMA 51 /* XDMA IRQ */ +#define IRQn_HDMA 52 /* HDMA IRQ */ +#define IRQn_FEMC 53 /* FEMC IRQ */ +#define IRQn_RNG 54 /* RNG IRQ */ +#define IRQn_I2S0 55 /* I2S0 IRQ */ +#define IRQn_I2S1 56 /* I2S1 IRQ */ +#define IRQn_DAO 57 /* DAO IRQ */ +#define IRQn_PDM 58 /* PDM IRQ */ +#define IRQn_FFA 59 /* FFA IRQ */ +#define IRQn_NTMR0 60 /* NTMR0 IRQ */ +#define IRQn_USB0 61 /* USB0 IRQ */ +#define IRQn_ENET0 62 /* ENET0 IRQ */ +#define IRQn_SDXC0 63 /* SDXC0 IRQ */ +#define IRQn_PSEC 64 /* PSEC IRQ */ +#define IRQn_PGPIO 65 /* PGPIO IRQ */ +#define IRQn_PWDG 66 /* PWDG IRQ */ +#define IRQn_PTMR 67 /* PTMR IRQ */ +#define IRQn_PUART 68 /* PUART IRQ */ +#define IRQn_FUSE 69 /* FUSE IRQ */ +#define IRQn_SECMON 70 /* SECMON IRQ */ +#define IRQn_RTC 71 /* RTC IRQ */ +#define IRQn_BUTN 72 /* BUTN IRQ */ +#define IRQn_BGPIO 73 /* BGPIO IRQ */ +#define IRQn_BVIO 74 /* BVIO IRQ */ +#define IRQn_BROWNOUT 75 /* BROWNOUT IRQ */ +#define IRQn_SYSCTL 76 /* SYSCTL IRQ */ +#define IRQn_DEBUG_0 77 /* DEBUG[0] IRQ */ +#define IRQn_DEBUG_1 78 /* DEBUG[1] IRQ */ #include "hpm_common.h" @@ -556,9 +556,12 @@ /* TSNS base pointer */ #define HPM_TSNS ((TSNS_Type *) HPM_TSNS_BASE) +#include "hpm_bacc_regs.h" /* Address of BACC instances */ /* BACC base address */ #define HPM_BACC_BASE (0xF5000000UL) +/* BACC base pointer */ +#define HPM_BACC ((BACC_Type *) HPM_BACC_BASE) #include "hpm_bpor_regs.h" /* Address of BPOR instances */ @@ -640,4 +643,4 @@ #include "hpm_iomux.h" #include "hpm_pmic_iomux.h" #include "hpm_batt_iomux.h" -#endif /* HPM_SOC_H */ \ No newline at end of file +#endif /* HPM_SOC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_soc_feature.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_soc_feature.h index cec19fe25b2..2719595a4eb 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_soc_feature.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_soc_feature.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -9,6 +9,7 @@ #define HPM_SOC_FEATURE_H #include "hpm_soc.h" +#include "hpm_soc_ip_feature.h" /* * I2C Section @@ -63,7 +64,6 @@ */ #define DMA_SOC_TRANSFER_WIDTH_MAX(x) (((x) == HPM_XDMA) ? DMA_TRANSFER_WIDTH_DOUBLE_WORD : DMA_TRANSFER_WIDTH_WORD) #define DMA_SOC_TRANSFER_PER_BURST_MAX(x) (((x) == HPM_XDMA) ? DMA_NUM_TRANSFER_PER_BURST_1024T : DMA_NUM_TRANSFER_PER_BURST_128T) -#define DMA_SOC_BUS_NUM (1U) #define DMA_SOC_CHANNEL_NUM (8U) #define DMA_SOC_MAX_COUNT (2U) #define DMA_SOC_CHN_TO_DMAMUX_CHN(x, n) (((x) == HPM_XDMA) ? (DMAMUX_MUXCFG_XDMA_MUX0 + n) : (DMAMUX_MUXCFG_HDMA_MUX0 + n)) @@ -88,18 +88,15 @@ #define USB_SOC_DCD_QTD_NEXT_INVALID (1U) #define USB_SOC_DCD_QHD_BUFFER_COUNT (5U) -#define USB_SOC_DCD_QTD_ALIGNMENT (32U) -#define USB_SOC_DCD_QHD_ALIGNMENT (64U) #define USB_SOC_DCD_MAX_ENDPOINT_COUNT (8U) -#define USB_SOC_DCD_MAX_QTD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U) +#ifndef USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT +#define USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT (8U) +#endif +#define USB_SOC_DCD_MAX_QTD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U * USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT) #define USB_SOS_DCD_MAX_QHD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U) #define USB_SOC_DCD_DATA_RAM_ADDRESS_ALIGNMENT (2048U) -#define USB_SOC_HCD_QTD_BUFFER_COUNT (5U) -#define USB_SOC_HCD_QTD_ALIGNMENT (32U) -#define USB_SOC_HCD_QHD_ALIGNMENT (32U) #define USB_SOC_HCD_FRAMELIST_MAX_ELEMENTS (1024U) -#define USB_SOC_HCD_DATA_RAM_ADDRESS_ALIGNMENT (4096U) /* * ENET Section @@ -117,6 +114,7 @@ /* * ADC Section */ +#define ADC_SOC_IP_VERSION (1U) #define ADC_SOC_SEQ_MAX_LEN (16U) #define ADC_SOC_MAX_TRIG_CH_LEN (4U) #define ADC_SOC_MAX_TRIG_CH_NUM (11U) @@ -197,6 +195,9 @@ /* * OTP Section */ +#define OTP_SOC_MAC0_IDX (65U) +#define OTP_SOC_MAC0_LEN (6U) /* in bytes */ + #define OTP_SOC_UUID_IDX (88U) #define OTP_SOC_UUID_LEN (16U) /* in bytes */ @@ -208,10 +209,4 @@ #define PWM_SOC_SHADOW_TRIG_SUPPORT (0U) #define PWM_SOC_TIMER_RESET_SUPPORT (1U) -/** - * IOC Section - * - */ -#define IOC_SOC_PAD_MAX (487) - #endif /* HPM_SOC_FEATURE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_soc_ip_feature.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_soc_ip_feature.h new file mode 100644 index 00000000000..410acf83beb --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_soc_ip_feature.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_SOC_IP_FEATURE_H +#define HPM_SOC_IP_FEATURE_H + +/* PWM related feature */ +#define HPM_IP_FEATURE_PWM_COUNTER_RESET 1 + +#endif /* HPM_SOC_IP_FEATURE_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.c index d03e8a864f0..48fb57bc6aa 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.c @@ -9,7 +9,6 @@ #include "hpm_soc_feature.h" #define SYSCTL_RESOURCE_GROUP0 0 -#define SYSCTL_RESOURCE_GROUP1 1 #define SYSCTL_CPU_RELEASE_KEY(cpu) (0xC0BEF1A9UL | ((cpu & 1) << 24)) @@ -86,6 +85,7 @@ hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, u void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config) { + (void) ptr; config->mode = monitor_work_mode_record; config->accuracy = monitor_accuracy_1khz; config->reference = monitor_reference_24mhz; @@ -97,16 +97,16 @@ void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *confi config->target = monitor_target_clk_top_cpu0; } -void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t slice, monitor_config_t *config) +void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config_t *config) { - ptr->MONITOR[slice].CONTROL &= ~(SYSCTL_MONITOR_CONTROL_START_MASK | SYSCTL_MONITOR_CONTROL_OUTEN_MASK); + ptr->MONITOR[monitor_index].CONTROL &= ~(SYSCTL_MONITOR_CONTROL_START_MASK | SYSCTL_MONITOR_CONTROL_OUTEN_MASK); if (config->mode == monitor_work_mode_compare) { - ptr->MONITOR[slice].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(config->high_limit); - ptr->MONITOR[slice].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(config->low_limit); + ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(config->high_limit); + ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(config->low_limit); } - ptr->MONITOR[slice].CONTROL = (ptr->MONITOR[slice].CONTROL & + ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL & ~(SYSCTL_MONITOR_CONTROL_DIV_MASK | SYSCTL_MONITOR_CONTROL_MODE_MASK | SYSCTL_MONITOR_CONTROL_ACCURACY_MASK | SYSCTL_MONITOR_CONTROL_REFERENCE_MASK | SYSCTL_MONITOR_CONTROL_SELECTION_MASK)) | (SYSCTL_MONITOR_CONTROL_DIV_SET(config->divide_by - 1) | SYSCTL_MONITOR_CONTROL_MODE_SET(config->mode) | @@ -148,18 +148,23 @@ hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry) } hpm_stat_t -sysctl_enable_group_resource(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t linkable_resource, bool enable) +sysctl_enable_group_resource(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t resource, bool enable) { uint32_t index, offset; - if (linkable_resource < sysctl_resource_linkable_start) { + if (resource < sysctl_resource_linkable_start) { return status_invalid_argument; } - index = (linkable_resource - sysctl_resource_linkable_start) / 32; - offset = (linkable_resource - sysctl_resource_linkable_start) % 32; + index = (resource - sysctl_resource_linkable_start) / 32; + offset = (resource - sysctl_resource_linkable_start) % 32; switch (group) { case SYSCTL_RESOURCE_GROUP0: ptr->GROUP0[index].VALUE = (ptr->GROUP0[index].VALUE & ~(1UL << offset)) | (enable ? (1UL << offset) : 0); + if (enable) { + while (sysctl_resource_target_is_busy(ptr, resource)) { + ; + } + } break; default: return status_invalid_argument; @@ -168,6 +173,41 @@ sysctl_enable_group_resource(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t return status_success; } +bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, + uint8_t group, + sysctl_resource_t resource) +{ + uint32_t index, offset; + bool enable; + + index = (resource - sysctl_resource_linkable_start) / 32; + offset = (resource - sysctl_resource_linkable_start) % 32; + switch (group) { + case SYSCTL_RESOURCE_GROUP0: + enable = ((ptr->GROUP0[index].VALUE & (1UL << offset)) != 0) ? true : false; + break; + default: + enable = false; + break; + } + + return enable; +} + +uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index) +{ + uint32_t value; + switch (group) { + case SYSCTL_RESOURCE_GROUP0: + value = ptr->GROUP0[index].VALUE; + break; + default: + value = 0; + break; + } + return value; +} + hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) { return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, true); @@ -204,9 +244,8 @@ hpm_stat_t sysctl_set_adc_i2s_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clo return status_success; } -hpm_stat_t sysctl_update_divider(SYSCTL_Type *ptr, clock_node_t node_index, uint32_t divide_by) +hpm_stat_t sysctl_update_divider(SYSCTL_Type *ptr, clock_node_t node, uint32_t divide_by) { - uint32_t node = (uint32_t) node_index; if (node >= clock_node_adc_i2s_start) { return status_invalid_argument; } @@ -216,9 +255,8 @@ hpm_stat_t sysctl_update_divider(SYSCTL_Type *ptr, clock_node_t node_index, uint return status_success; } -hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node_index, clock_source_t source, uint32_t divide_by) +hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node, clock_source_t source, uint32_t divide_by) { - uint32_t node = (uint32_t) node_index; if (node >= clock_node_adc_i2s_start) { return status_invalid_argument; } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.h index 22416c7dc37..cfd36d5f49e 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.h @@ -1,5 +1,5 @@ /** - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -624,10 +624,26 @@ static inline bool sysctl_resource_target_is_busy(SYSCTL_Type *ptr, sysctl_resou * @param[in] resource target resource index * @param[in] mode target resource mode */ -static inline void -sysctl_resource_target_set_mode(SYSCTL_Type *ptr, sysctl_resource_t resource, sysctl_resource_mode_t mode) +static inline void sysctl_resource_target_set_mode(SYSCTL_Type *ptr, + sysctl_resource_t resource, + sysctl_resource_mode_t mode) +{ + ptr->RESOURCE[resource] = + (ptr->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | + SYSCTL_RESOURCE_MODE_SET(mode); +} + +/** + * @brief Get target mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource target resource index + * @return target resource mode + */ +static inline uint8_t sysctl_resource_target_get_mode(SYSCTL_Type *ptr, + sysctl_resource_t resource) { - ptr->RESOURCE[resource] = (ptr->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | SYSCTL_RESOURCE_MODE_SET(mode); + return SYSCTL_RESOURCE_MODE_GET(ptr->RESOURCE[resource]); } /** @@ -776,11 +792,33 @@ static inline bool sysctl_clock_any_is_busy(SYSCTL_Type *ptr) * @param[in] clock target clock * @return true if target clock is busy */ -static inline bool sysctl_clock_target_is_busy(SYSCTL_Type *ptr, uint32_t clock) +static inline bool sysctl_clock_target_is_busy(SYSCTL_Type *ptr, clock_node_t clock) { return ptr->CLOCK[clock] & SYSCTL_CLOCK_LOC_BUSY_MASK; } +/** + * @brief Preserve clock setting for certain node + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] clock target clock + */ +static inline void sysctl_clock_preserve_settings(SYSCTL_Type *ptr, clock_node_t clock) +{ + ptr->CLOCK[clock] |= SYSCTL_CLOCK_PRESERVE_MASK; +} + +/** + * @brief Unpreserve clock setting for certain node + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] clock target clock + */ +static inline void sysctl_clock_unpreserve_settings(SYSCTL_Type *ptr, clock_node_t clock) +{ + ptr->CLOCK[clock] &= ~SYSCTL_CLOCK_PRESERVE_MASK; +} + /** * @brief Set clock preset * @@ -1172,6 +1210,27 @@ hpm_stat_t sysctl_set_adc_i2s_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clo * @return status_success if everything is okay */ hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t resource, bool enable); + +/** + * @brief Check group resource enable status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] group target group to be checked + * @param[in] resource target resource to be checked from group + * @return enable true if resource enable, false if resource disable + */ +bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t resource); + +/** + * @brief Get group resource value + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] group target group to be getted + * @param[in] index target group index + * @return group index value + */ +uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index); + /** * @brief Add resource to CPU0 * @@ -1208,7 +1267,7 @@ void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *confi void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config_t *config); /** - * @brief Save data to GPU0 GPR starting from given index + * @brief Save data to CPU0 GPR starting from given index * * @param[in] ptr SYSCTL_Type base address * @param[in] start Starting GPR index @@ -1220,7 +1279,7 @@ void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock); /** - * @brief Get data saved from GPU0 GPR starting from given index + * @brief Get data saved from CPU0 GPR starting from given index * * @param[in] ptr SYSCTL_Type base address * @param[in] start Starting GPR index diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_regs.h index 6e9f31b3bdf..89091acfb0f 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -27,10 +27,10 @@ typedef struct { } AFFILIATE[1]; __R uint8_t RESERVED2[16]; /* 0x910 - 0x91F: Reserved */ struct { - __RW uint32_t VALUE; /* 0x920: Retention Contol */ - __RW uint32_t SET; /* 0x924: Retention Contol */ - __RW uint32_t CLEAR; /* 0x928: Retention Contol */ - __RW uint32_t TOGGLE; /* 0x92C: Retention Contol */ + __RW uint32_t VALUE; /* 0x920: Retention Control */ + __RW uint32_t SET; /* 0x924: Retention Control */ + __RW uint32_t CLEAR; /* 0x928: Retention Control */ + __RW uint32_t TOGGLE; /* 0x92C: Retention Control */ } RETENTION[1]; __R uint8_t RESERVED3[1744]; /* 0x930 - 0xFFF: Reserved */ struct { @@ -396,7 +396,7 @@ typedef struct { * * perform reset and release imediately * 0: reset is released - * 1 reset is asserted and will release automaticly + * 1 reset is asserted and will release automatically */ #define SYSCTL_RESET_CONTROL_RESET_MASK (0x1U) #define SYSCTL_RESET_CONTROL_RESET_SHIFT (0U) @@ -880,7 +880,7 @@ typedef struct { /* * REFERENCE (RW) * - * refrence clock selection, + * reference clock selection, * 0: 32k * 1: 24M */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_trgm_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_trgm_regs.h index e737a08c7b4..6f996212bb6 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_trgm_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_trgm_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_trgmmux_src.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_trgmmux_src.h index d5a723d17ad..6854b7aadf7 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_trgmmux_src.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_trgmmux_src.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -60,8 +60,6 @@ #define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT3 (0x33UL) #define HPM_TRGM0_INPUT_SRC_CMP0_OUT (0x34UL) #define HPM_TRGM0_INPUT_SRC_CMP1_OUT (0x35UL) -#define HPM_TRGM0_INPUT_SRC_CMP2_OUT (0x36UL) -#define HPM_TRGM0_INPUT_SRC_CMP3_OUT (0x37UL) #define HPM_TRGM0_INPUT_SRC_DEBUG_FLAG (0x38UL) /* trgm1_input mux definitions */ @@ -115,8 +113,6 @@ #define HPM_TRGM1_INPUT_SRC_GPTMR3_OUT3 (0x33UL) #define HPM_TRGM1_INPUT_SRC_CMP0_OUT (0x34UL) #define HPM_TRGM1_INPUT_SRC_CMP1_OUT (0x35UL) -#define HPM_TRGM1_INPUT_SRC_CMP2_OUT (0x36UL) -#define HPM_TRGM1_INPUT_SRC_CMP3_OUT (0x37UL) #define HPM_TRGM1_INPUT_SRC_DEBUG_FLAG (0x38UL) /* trgm0_output mux definitions */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/soc_modules.list b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/soc_modules.list index 4c1e15a065e..3b645a18c9b 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/soc_modules.list +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/soc_modules.list @@ -1,36 +1,63 @@ -# Copyright (c) 2022 HPMicro +# +# Copyright (c) 2024 HPMicro +# # SPDX-License-Identifier: BSD-3-Clause # -# In this file, all modules available on this part are listed -CONFIG_HAS_HPMSDK_UART=y -CONFIG_HAS_HPMSDK_FEMC=y -CONFIG_HAS_HPMSDK_SDP=y -CONFIG_HAS_HPMSDK_I2C=y -CONFIG_HAS_HPMSDK_PMP=y -CONFIG_HAS_HPMSDK_RNG=y -CONFIG_HAS_HPMSDK_GPIO=y -CONFIG_HAS_HPMSDK_SPI=y -CONFIG_HAS_HPMSDK_WDG=y -CONFIG_HAS_HPMSDK_DMA=y -CONFIG_HAS_HPMSDK_GPTMR=y -CONFIG_HAS_HPMSDK_PWM=y -CONFIG_HAS_HPMSDK_PLLCTLV2=y -CONFIG_HAS_HPMSDK_USB=y -CONFIG_HAS_HPMSDK_RTC=y -CONFIG_HAS_HPMSDK_ACMP=y -CONFIG_HAS_HPMSDK_I2S=y -CONFIG_HAS_HPMSDK_DAO=y -CONFIG_HAS_HPMSDK_PDM=y -CONFIG_HAS_HPMSDK_VAD=y -CONFIG_HAS_HPMSDK_CAN=y -CONFIG_HAS_HPMSDK_ENET=y -CONFIG_HAS_HPMSDK_SDXC=y -CONFIG_HAS_HPMSDK_ADC16=y -CONFIG_HAS_HPMSDK_PCFG=y -CONFIG_HAS_HPMSDK_PTPC=y -CONFIG_HAS_HPMSDK_MCHTMR=y -CONFIG_HAS_HPMSDK_FFA=y -CONFIG_HAS_HPMSDK_TSNS=y -CONFIG_HAS_HPMSDK_DAC=y +HPMSOC_HAS_HPMSDK_GPIO=y +HPMSOC_HAS_HPMSDK_PLIC=y +HPMSOC_HAS_HPMSDK_MCHTMR=y +HPMSOC_HAS_HPMSDK_PLICSW=y +HPMSOC_HAS_HPMSDK_GPIOM=y +HPMSOC_HAS_HPMSDK_ADC16=y +HPMSOC_HAS_HPMSDK_ACMP=y +HPMSOC_HAS_HPMSDK_DAC=y +HPMSOC_HAS_HPMSDK_SPI=y +HPMSOC_HAS_HPMSDK_UART=y +HPMSOC_HAS_HPMSDK_CAN=y +HPMSOC_HAS_HPMSDK_WDG=y +HPMSOC_HAS_HPMSDK_MBX=y +HPMSOC_HAS_HPMSDK_PTPC=y +HPMSOC_HAS_HPMSDK_DMAMUX=y +HPMSOC_HAS_HPMSDK_DMA=y +HPMSOC_HAS_HPMSDK_RNG=y +HPMSOC_HAS_HPMSDK_KEYM=y +HPMSOC_HAS_HPMSDK_I2S=y +HPMSOC_HAS_HPMSDK_DAO=y +HPMSOC_HAS_HPMSDK_PDM=y +HPMSOC_HAS_HPMSDK_PWM=y +HPMSOC_HAS_HPMSDK_HALL=y +HPMSOC_HAS_HPMSDK_QEI=y +HPMSOC_HAS_HPMSDK_TRGM=y +HPMSOC_HAS_HPMSDK_SYNT=y +HPMSOC_HAS_HPMSDK_ENET=y +HPMSOC_HAS_HPMSDK_GPTMR=y +HPMSOC_HAS_HPMSDK_USB=y +HPMSOC_HAS_HPMSDK_SDXC=y +HPMSOC_HAS_HPMSDK_I2C=y +HPMSOC_HAS_HPMSDK_SDP=y +HPMSOC_HAS_HPMSDK_FEMC=y +HPMSOC_HAS_HPMSDK_FFA=y +HPMSOC_HAS_HPMSDK_SYSCTL=y +HPMSOC_HAS_HPMSDK_IOC=y +HPMSOC_HAS_HPMSDK_OTP=y +HPMSOC_HAS_HPMSDK_PPOR=y +HPMSOC_HAS_HPMSDK_PCFG=y +HPMSOC_HAS_HPMSDK_PSEC=y +HPMSOC_HAS_HPMSDK_PMON=y +HPMSOC_HAS_HPMSDK_PGPR=y +HPMSOC_HAS_HPMSDK_PLLCTLV2=y +HPMSOC_HAS_HPMSDK_TSNS=y +HPMSOC_HAS_HPMSDK_BACC=y +HPMSOC_HAS_HPMSDK_BPOR=y +HPMSOC_HAS_HPMSDK_BCFG=y +HPMSOC_HAS_HPMSDK_BUTN=y +HPMSOC_HAS_HPMSDK_BGPR=y +HPMSOC_HAS_HPMSDK_BSEC=y +HPMSOC_HAS_HPMSDK_RTC=y +HPMSOC_HAS_HPMSDK_BKEY=y +HPMSOC_HAS_HPMSDK_BMON=y +HPMSOC_HAS_HPMSDK_TAMP=y +HPMSOC_HAS_HPMSDK_MONO=y +HPMSOC_HAS_HPMSDK_PMP=y diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/system.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/system.c index 3f742ad69ad..a0fb6800e94 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/system.c +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/system.c @@ -60,12 +60,4 @@ __attribute__((weak)) void system_init(void) enable_global_irq(CSR_MSTATUS_MIE_MASK); #endif #endif - -#ifndef CONFIG_NOT_ENABLE_ICACHE - l1c_ic_enable(); -#endif -#ifndef CONFIG_NOT_ENABLE_DCACHE - l1c_dc_enable(); - l1c_dc_invalidate_all(); -#endif } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash.ld index 53680819fb6..25578516a1c 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash.ld +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash.ld @@ -5,8 +5,8 @@ ENTRY(_start) -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; +STACK_SIZE = _stack_size; +HEAP_SIZE = _heap_size; MEMORY { @@ -25,7 +25,19 @@ SECTIONS KEEP(*(.start)) } > XPI0 - .text : { + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + KEEP(*(.vector_s_table)) + KEEP(*(.isr_s_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { . = ALIGN(8); *(.text) *(.text*) @@ -44,36 +56,51 @@ SECTIONS KEEP (*(.init)) KEEP (*(.fini)) - . = ALIGN(8); - } > XPI0 - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - /* section information for usbh class */ - .usbh_class_info : { - . = ALIGN(4); + /* section information for usbh class */ + . = ALIGN(8); __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; + + /* RT-Thread related sections - Start */ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ . = ALIGN(8); } > XPI0 + .rel : { + KEEP(*(.rel*)) + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - .vectors ORIGIN(ILM) : AT(etext) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .data : AT(etext + __vector_ram_end__ - __vector_ram_start__) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -81,8 +108,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -126,12 +151,14 @@ SECTIONS PROVIDE (edata = .); } > AXI_SRAM - .fast : AT(etext + __vector_ram_end__ - __vector_ram_start__ + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); - __ramfunc_start__ = .; + PROVIDE(__ramfunc_start__ = .); *(.fast) + *(.fast.*) . = ALIGN(8); - __ramfunc_end__ = .; + PROVIDE(__ramfunc_end__ = .); } > ILM .bss (NOLOAD) : { @@ -139,11 +166,9 @@ SECTIONS __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -151,13 +176,37 @@ SECTIONS __bss_end__ = .; } > AXI_SRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > AXI_SRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > AXI_SRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > AXI_SRAM - .noncacheable.init : AT(etext + __vector_ram_end__ - __vector_ram_start__ + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -201,5 +250,6 @@ SECTIONS __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); - ASSERT((STACK_SIZE + HEAP_SIZE) <= 128K, "stack and heap total size larger than 128k") + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_uf2.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_uf2.ld index 8b78e8ec141..ffe0e6a018e 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_uf2.ld +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_uf2.ld @@ -5,8 +5,8 @@ ENTRY(_start) -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; +STACK_SIZE = _stack_size; +HEAP_SIZE = _heap_size; UF2_BOOTLOADER_RESERVED_LENGTH = DEFINED(_uf2_bl_length) ? _uf2_bl_length : 0x20000; MEMORY @@ -27,7 +27,19 @@ SECTIONS KEEP(*(.start)) } > XPI0 - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__): { + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + KEEP(*(.vector_s_table)) + KEEP(*(.isr_s_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)): { . = ALIGN(8); *(.text) *(.text*) @@ -46,39 +58,51 @@ SECTIONS KEEP (*(.init)) KEEP (*(.fini)) - . = ALIGN(8); - } > XPI0 - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - /* section information for usbh class */ - .usbh_class_info : { - . = ALIGN(4); + /* section information for usbh class */ + . = ALIGN(8); __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; + + /* RT-Thread related sections - Start */ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ . = ALIGN(8); } > XPI0 + .rel : { + KEEP(*(.rel*)) + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - KEEP(*(.vector_s_table)) - KEEP(*(.isr_s_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .data : AT(etext) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -86,8 +110,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -131,12 +153,14 @@ SECTIONS PROVIDE (edata = .); } > SDRAM - .fast : AT(etext + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); - __ramfunc_start__ = .; + PROVIDE(__ramfunc_start__ = .); *(.fast) + *(.fast.*) . = ALIGN(8); - __ramfunc_end__ = .; + PROVIDE(__ramfunc_end__ = .); } > ILM .bss (NOLOAD) : { @@ -144,11 +168,9 @@ SECTIONS __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -156,13 +178,37 @@ SECTIONS __bss_end__ = .; } > SDRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > SDRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > SDRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > SDRAM - .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -205,4 +251,7 @@ SECTIONS __noncacheable_start__ = ORIGIN(SDRAM_NONCACHEABLE); __noncacheable_end__ = ORIGIN(SDRAM_NONCACHEABLE) + LENGTH(SDRAM_NONCACHEABLE); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_xip.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_xip.ld index 7d957c29726..7ca16981fcc 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_xip.ld +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_xip.ld @@ -5,8 +5,8 @@ ENTRY(_start) -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; +STACK_SIZE = _stack_size; +HEAP_SIZE = _heap_size; MEMORY { @@ -44,7 +44,19 @@ SECTIONS KEEP(*(.start)) } > XPI0 - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + KEEP(*(.vector_s_table)) + KEEP(*(.isr_s_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { . = ALIGN(8); *(.text) *(.text*) @@ -63,39 +75,51 @@ SECTIONS KEEP (*(.init)) KEEP (*(.fini)) - . = ALIGN(8); - } > XPI0 - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - /* section information for usbh class */ - .usbh_class_info : { - . = ALIGN(4); + /* section information for usbh class */ + . = ALIGN(8); __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; + + /* RT-Thread related sections - Start */ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ . = ALIGN(8); } > XPI0 + .rel : { + KEEP(*(.rel*)) + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - KEEP(*(.vector_s_table)) - KEEP(*(.isr_s_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .data : AT(etext) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -103,8 +127,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -142,31 +164,31 @@ SECTIONS KEEP(*(SORT(.dtors.*))) KEEP(*(.dtors)) . = ALIGN(8); + __data_end__ = .; PROVIDE (__edata = .); PROVIDE (_edata = .); PROVIDE (edata = .); } > SDRAM - .fast : AT(etext + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); - __ramfunc_start__ = .; + PROVIDE(__ramfunc_start__ = .); *(.fast) + *(.fast.*) . = ALIGN(8); - __ramfunc_end__ = .; + PROVIDE(__ramfunc_end__ = .); } > ILM - __fw_size__ = __ramfunc_end__ - __ramfunc_start__ + __data_end__ - __data_start__ + etext - __app_load_addr__; .bss (NOLOAD) : { . = ALIGN(8); __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -174,13 +196,37 @@ SECTIONS __bss_end__ = .; } > SDRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > SDRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > SDRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > SDRAM - .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -223,4 +269,7 @@ SECTIONS __noncacheable_start__ = ORIGIN(SDRAM_NONCACHEABLE); __noncacheable_end__ = ORIGIN(SDRAM_NONCACHEABLE) + LENGTH(SDRAM_NONCACHEABLE); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_uf2.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_uf2.ld index f2cce578a9a..621ae72a78a 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_uf2.ld +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_uf2.ld @@ -5,8 +5,8 @@ ENTRY(_start) -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; +STACK_SIZE = _stack_size; +HEAP_SIZE = _heap_size; UF2_BOOTLOADER_RESERVED_LENGTH = DEFINED(_uf2_bl_length) ? _uf2_bl_length : 0x20000; MEMORY @@ -26,7 +26,19 @@ SECTIONS KEEP(*(.start)) } > XPI0 - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__): { + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + KEEP(*(.vector_s_table)) + KEEP(*(.isr_s_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)): { . = ALIGN(8); *(.text) *(.text*) @@ -45,39 +57,51 @@ SECTIONS KEEP (*(.init)) KEEP (*(.fini)) - . = ALIGN(8); - } > XPI0 - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - /* section information for usbh class */ - .usbh_class_info : { - . = ALIGN(4); + /* section information for usbh class */ + . = ALIGN(8); __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; + + /* RT-Thread related sections - Start */ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ . = ALIGN(8); } > XPI0 + .rel : { + KEEP(*(.rel*)) + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - KEEP(*(.vector_s_table)) - KEEP(*(.isr_s_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .data : AT(etext) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -85,8 +109,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -130,12 +152,14 @@ SECTIONS PROVIDE (edata = .); } > AXI_SRAM - .fast : AT(etext + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); - __ramfunc_start__ = .; + PROVIDE(__ramfunc_start__ = .); *(.fast) + *(.fast.*) . = ALIGN(8); - __ramfunc_end__ = .; + PROVIDE(__ramfunc_end__ = .); } > ILM .bss (NOLOAD) : { @@ -143,11 +167,9 @@ SECTIONS __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -155,13 +177,37 @@ SECTIONS __bss_end__ = .; } > AXI_SRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > AXI_SRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > AXI_SRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -205,5 +251,6 @@ SECTIONS __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); - ASSERT((STACK_SIZE + HEAP_SIZE) <= 128K, "stack and heap total size larger than 128k") + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_xip.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_xip.ld index 412c1d320ce..470eeecdbb4 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_xip.ld +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_xip.ld @@ -5,8 +5,8 @@ ENTRY(_start) -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; +STACK_SIZE = _stack_size; +HEAP_SIZE = _heap_size; MEMORY { @@ -24,6 +24,7 @@ __app_load_addr__ = ORIGIN(XPI0) + 0x3000; __boot_header_length__ = __boot_header_end__ - __boot_header_start__; __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + SECTIONS { .nor_cfg_option __nor_cfg_option_load_addr__ : { @@ -43,7 +44,19 @@ SECTIONS KEEP(*(.start)) } > XPI0 - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__): { + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + KEEP(*(.vector_s_table)) + KEEP(*(.isr_s_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { . = ALIGN(8); *(.text) *(.text*) @@ -62,39 +75,51 @@ SECTIONS KEEP (*(.init)) KEEP (*(.fini)) - . = ALIGN(8); - } > XPI0 - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - /* section information for usbh class */ - .usbh_class_info : { - . = ALIGN(4); + /* section information for usbh class */ + . = ALIGN(8); __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; + + /* RT-Thread related sections - Start */ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ . = ALIGN(8); } > XPI0 + .rel : { + KEEP(*(.rel*)) + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - KEEP(*(.vector_s_table)) - KEEP(*(.isr_s_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .data : AT(etext) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -102,8 +127,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -147,25 +170,24 @@ SECTIONS PROVIDE (edata = .); } > AXI_SRAM - .fast : AT(etext + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); - __ramfunc_start__ = .; + PROVIDE(__ramfunc_start__ = .); *(.fast) + *(.fast.*) . = ALIGN(8); - __ramfunc_end__ = .; + PROVIDE(__ramfunc_end__ = .); } > ILM - __fw_size__ = __ramfunc_end__ - __ramfunc_start__ + __data_end__ - __data_start__ + etext - __app_load_addr__; .bss (NOLOAD) : { . = ALIGN(8); __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -173,13 +195,37 @@ SECTIONS __bss_end__ = .; } > AXI_SRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > AXI_SRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > AXI_SRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -223,5 +269,6 @@ SECTIONS __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); - ASSERT((STACK_SIZE + HEAP_SIZE) <= 128K, "stack and heap total size larger than 128k") + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/ram.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/ram.ld index 0aec08c67b0..1fd88372b0b 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/ram.ld +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/ram.ld @@ -5,8 +5,8 @@ ENTRY(_start) -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; +STACK_SIZE = _stack_size; +HEAP_SIZE = _heap_size; MEMORY { @@ -58,19 +58,45 @@ SECTIONS KEEP (*(.fini)) /* section information for usbh class */ - . = ALIGN(4); + . = ALIGN(8); __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; - . = ALIGN(8); + /* RT-Thread related sections - Start */ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + . = ALIGN(8); PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); } > ILM - .data : AT(etext) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -78,8 +104,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -124,10 +148,12 @@ SECTIONS PROVIDE (edata = .); } > AXI_SRAM - .fast : AT(etext + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) + *(.fast.*) . = ALIGN(8); PROVIDE(__ramfunc_end__ = .); } > ILM @@ -137,11 +163,9 @@ SECTIONS __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -149,13 +173,37 @@ SECTIONS __bss_end__ = .; } > AXI_SRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > AXI_SRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > AXI_SRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -191,6 +239,7 @@ SECTIONS . = ALIGN(8); __stack_base__ = .; . += STACK_SIZE; + . = ALIGN(8); PROVIDE (_stack = .); PROVIDE (_stack_safe = .); } > DLM @@ -198,5 +247,7 @@ SECTIONS __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); - ASSERT((STACK_SIZE + HEAP_SIZE) <= 128K, "stack and heap total size larger than 128k") + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + __last_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); + ASSERT(((__fw_size__ <= LENGTH(ILM)) && (__last_addr__ <= (ORIGIN(ILM) + LENGTH(ILM)))), "****** FAILED! ILM has not enough space! ******") } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/start.S b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/start.S index a862981d75f..23f410a43eb 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/start.S +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/start.S @@ -16,6 +16,7 @@ _start: .option push .option norelax la gp, __global_pointer$ + la tp, __thread_pointer$ .option pop /* reset mstatus to 0*/ @@ -40,6 +41,19 @@ _start: la t0, _stack mv sp, t0 +#ifdef CONFIG_NOT_ENABLE_ICACHE + call l1c_ic_disable +#else + call l1c_ic_enable +#endif +#ifdef CONFIG_NOT_ENABLE_DCACHE + call l1c_dc_invalidate_all + call l1c_dc_disable +#else + call l1c_dc_enable + call l1c_dc_invalidate_all +#endif + /* * Initialize LMA/VMA sections. * Relocation for any sections that need to be copied from LMA to VMA. @@ -87,6 +101,14 @@ _start: /* Use mscratch to store isr level */ csrw mscratch, 0 + +#elif defined(CONFIG_RTTHREAD) && CONFIG_RTTHREAD + #define HANDLER_TRAP rtt_risc_v_trap_handler + #define HANDLER_S_TRAP rtt_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 + #else #define HANDLER_TRAP irq_handler_trap #define HANDLER_S_TRAP irq_handler_s_trap diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/reset.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/reset.c index 626e5dec166..9fb2135db6a 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/reset.c +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/reset.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,6 +12,10 @@ extern void system_init(void); +#ifndef MAIN_ENTRY +#define MAIN_ENTRY main +#endif +extern int MAIN_ENTRY(void); __attribute__((weak)) void _clean_up(void) { @@ -30,6 +34,15 @@ __attribute__((weak)) void _clean_up(void) __attribute__((weak)) void c_startup(void) { uint32_t i, size; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __tdata_start__[], __tdata_end__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + extern uint8_t __data_load_addr__[], __tdata_load_addr__[]; + extern uint8_t __fast_load_addr__[], __noncacheable_init_load_addr__[]; + #if defined(FLASH_XIP) || defined(FLASH_UF2) extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; size = __vector_ram_end__ - __vector_ram_start__; @@ -38,13 +51,6 @@ __attribute__((weak)) void c_startup(void) } #endif - extern uint8_t __etext[]; - extern uint8_t __bss_start__[], __bss_end__[]; - extern uint8_t __data_start__[], __data_end__[]; - extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; - extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; - extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; - /* bss section */ size = __bss_end__ - __bss_start__; for (i = 0; i < size; i++) { @@ -60,19 +66,25 @@ __attribute__((weak)) void c_startup(void) /* data section LMA: etext */ size = __data_end__ - __data_start__; for (i = 0; i < size; i++) { - *(__data_start__ + i) = *(__etext + i); + *(__data_start__ + i) = *(__data_load_addr__ + i); } /* ramfunc section LMA: etext + data length */ size = __ramfunc_end__ - __ramfunc_start__; for (i = 0; i < size; i++) { - *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __data_start__) + i); + *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i); } - /* noncacheable init section LMA: etext + data length + ramfunc legnth */ + /* tdata section LMA: etext + data length + ramfunc length */ + size = __tdata_end__ - __tdata_start__; + for (i = 0; i < size; i++) { + *(__tdata_start__ + i) = *(__tdata_load_addr__ + i); + } + + /* noncacheable init section LMA: etext + data length + ramfunc legnth + tdata length*/ size = __noncacheable_init_end__ - __noncacheable_init_start__; for (i = 0; i < size; i++) { - *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __data_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); + *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); } } @@ -85,14 +97,13 @@ __attribute__((weak)) int main(void) __attribute__((weak)) void reset_handler(void) { - l1c_dc_disable(); - l1c_dc_invalidate_all(); + fencei(); /* Call platform specific hardware initialization */ system_init(); /* Entry function */ - main(); + MAIN_ENTRY(); } /* @@ -102,12 +113,46 @@ __attribute__((weak)) void reset_handler(void) */ __attribute__((weak)) void __cxa_atexit(void (*arg1)(void *), void *arg2, void *arg3) { + (void) arg1; + (void) arg2; + (void) arg3; } -#if !defined(__SEGGER_RTL_VERSION) || defined(__riscv_xandes) +#if (!defined(__SEGGER_RTL_VERSION) || defined(__riscv_xandes)) && !defined(__ICCRISCV__) void *__dso_handle = (void *) &__dso_handle; #endif __attribute__((weak)) void _init(void) { } + + +#ifdef __ICCRISCV__ +int __low_level_init(void) +{ +#ifdef IAR_MANUAL_COPY /* Enable this code snippet if the .isr_vector and .vector_table need to be copied to RAM manually */ +#pragma section = ".isr_vector" +#pragma section = ".isr_vector_init" +#pragma section = ".vector_table" +#pragma section = ".vector_table_init" + /* Initialize section .isr_vector, section .vector_table */ + uint8_t *__isr_vector_ram_start = __section_begin(".isr_vector"); + uint32_t __isr_vector_ram_size = __section_size(".isr_vector"); + uint8_t *__isr_vector_rom_start = __section_begin(".isr_vector_init"); + + for (uint32_t i = 0; i < __isr_vector_ram_size; i++) { + __isr_vector_ram_start[i] = __isr_vector_rom_start[i]; + } + + uint8_t *__vector_table_ram_start = __section_begin(".vector_table"); + uint32_t __vector_table_ram_size = __section_size(".vector_table"); + uint8_t *__vector_rom_start = __section_begin(".vector_table_init"); + + for (uint32_t i = 0; i < __vector_table_ram_size; i++) { + __vector_table_ram_start[i] = __vector_rom_start[i]; + } +#endif + + return 1; +} +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash.icf deleted file mode 100644 index 49c9d960d25..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash.icf +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region XPI0 = [from 0x80000000 + 0x3000, size _flash_size - 0x3000]; /* XPI0 */ -define region ILM = [from 0x00000000 size 128k]; /* ILM */ -define region DLM = [from 0x00080000 size 128k]; /* DLM */ -define region AXI_SRAM = [from 0x01080000 size 256k]; -define region NONCACHEABLE_RAM = [from 0x010C0000 size 256k]; -define region AHB_SRAM = [from 0xF0300000 size 32k]; - -assert (__STACKSIZE__ + __HEAPSIZE__) <= 128k with error "stack and heap total size larger than 128k"; - -/* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -/* Initialization */ -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors, block vectors_s }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place at start of XPI0 with fixed order { symbol _start }; -place at start of ILM with fixed order { block vectors, block vectors_s }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { - section .fast, section .fast.* // "ramfunc" section - }; -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_uf2.icf deleted file mode 100644 index 3375a1f678d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_uf2.icf +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -/* Regions */ -define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; -define region ILM = [from 0x00000000 size 128k]; /* ILM */ -define region DLM = [from 0x00080000 size 128k]; /* DLM */ -define region AXI_SRAM = [from 0x01080000 size 512k]; -define region SDRAM = [from 0x40000000 size _extram_size - 4M]; -define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M]; -define region AHB_SRAM = [from 0xF0300000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -/* Initialization */ -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors, block vectors_s }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place at start of XPI0 with fixed order { section .uf2_signature }; -place in XPI0 with fixed order { symbol _start }; -place at start of ILM with fixed order { block vectors, block vectors_s }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in SDRAM { block cherryusb_usbh_class_info }; -place in SDRAM { block framebuffer }; -place in AXI_SRAM then SDRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram}; // Fast access memory -place in SDRAM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .uf2_signature }; -keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_xip.icf deleted file mode 100644 index 4ece100f24d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_xip.icf +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region NOR_CFG_OPTION = [ from 0x80000400 size 0xc00 ]; -define region BOOT_HEADER = [ from 0x80001000 size 0x2000 ]; -define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ -define region ILM = [from 0x00000000 size 128k]; /* ILM */ -define region DLM = [from 0x00080000 size 128k]; /* DLM */ -define region AXI_SRAM = [from 0x01080000 size 512k]; -define region SDRAM = [from 0x40000000 size _extram_size - 4M]; -define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M]; -define region AHB_SRAM = [from 0xF0300000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; -define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; -define exported symbol __app_load_addr__ = start of region XPI0; -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size of block boot_header; -define exported symbol __fw_size__ = 0x1000; - -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -/* Initialization */ -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors, block vectors_s }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER with fixed order { block boot_header }; -place at start of XPI0 with fixed order { symbol _start }; -place at start of ILM with fixed order { block vectors, block vectors_s }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in SDRAM { block cherryusb_usbh_class_info }; -place in SDRAM { block framebuffer }; -place in AXI_SRAM then SDRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram}; // Fast access memory -place in SDRAM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; -keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_uf2.icf deleted file mode 100644 index bdac6a9b9f2..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_uf2.icf +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -/* Regions */ -define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */ -define region ILM = [from 0x00000000 size 128k]; /* ILM */ -define region DLM = [from 0x00080000 size 128k]; /* DLM */ -define region AXI_SRAM = [from 0x01080000 size 256k]; -define region NONCACHEABLE_RAM = [from 0x010C0000 size 256k]; -define region AHB_SRAM = [from 0xF0300000 size 32k]; - -assert (__STACKSIZE__ + __HEAPSIZE__) <= 128k with error "stack and heap total size larger than 128k"; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -/* Initialization */ -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors, block vectors_s }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place at start of XPI0 with fixed order { section .uf2_signature }; -place in XPI0 with fixed order { symbol _start }; -place at start of ILM with fixed order { block vectors, block vectors_s }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .uf2_signature }; -keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_xip.icf deleted file mode 100644 index 6a7fa6d0091..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_xip.icf +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region NOR_CFG_OPTION = [ from 0x80000400 size 0xc00 ]; -define region BOOT_HEADER = [ from 0x80001000 size 0x2000 ]; -define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ -define region ILM = [from 0x00000000 size 128k]; /* ILM */ -define region DLM = [from 0x00080000 size 128k]; /* DLM */ -define region AXI_SRAM = [from 0x01080000 size 256k]; -define region NONCACHEABLE_RAM = [from 0x010C0000 size 256k]; -define region AHB_SRAM = [from 0xF0300000 size 32k]; - -assert (__STACKSIZE__ + __HEAPSIZE__) <= 128k with error "stack and heap total size larger than 128k"; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; -define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; -define exported symbol __app_load_addr__ = start of region XPI0; -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size of block boot_header; -define exported symbol __fw_size__ = 0x1000; - -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -/* Initialization */ -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors, block vectors_s }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER with fixed order { block boot_header }; -place at start of XPI0 with fixed order { symbol _start }; -place at start of ILM with fixed order { block vectors, block vectors_s }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; -keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/ram.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/ram.icf deleted file mode 100644 index 1b5d3d7af6e..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/ram.icf +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region ILM = [from 0x00000000 size 128k]; /* ILM */ -define region DLM = [from 0x00080000 size 128k]; /* DLM */ -define region AXI_SRAM = [from 0x01080000 size 256k]; -define region NONCACHEABLE_RAM = [from 0x010C0000 size 256k]; -define region AHB_SRAM = [from 0xF0300000 size 32k]; - -assert (__STACKSIZE__ + __HEAPSIZE__) <= 128k with error "stack and heap total size larger than 128k"; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -/* Initialization */ -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -/* Placement */ -place at start of ILM { symbol _start }; -place in ILM { block vectors, block vectors_s }; // Vector table section -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in ILM with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) // It is intended placing RO here - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/startup.s b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/startup.s deleted file mode 100644 index 523086e6028..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/startup.s +++ /dev/null @@ -1,398 +0,0 @@ -/********************************************************************* -* SEGGER Microcontroller GmbH * -* The Embedded Experts * -********************************************************************** -* * -* (c) 2014 - 2021 SEGGER Microcontroller GmbH * -* * -* www.segger.com Support: support@segger.com * -* * -********************************************************************** -* * -* All rights reserved. * -* * -* Redistribution and use in source and binary forms, with or * -* without modification, are permitted provided that the following * -* condition is met: * -* * -* - Redistributions of source code must retain the above copyright * -* notice, this condition and the following disclaimer. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * -* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * -* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * -* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * -* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * -* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * -* DAMAGE. * -* * -********************************************************************** - --------------------------- END-OF-HEADER ----------------------------- - -File : SEGGER_RISCV_crt0.s -Purpose : Generic runtime init startup code for RISC-V CPUs. - Designed to work with the SEGGER linker to produce - smallest possible executables. - - This file does not normally require any customization. - -Additional information: - Preprocessor Definitions - FULL_LIBRARY - If defined then - - argc, argv are set up by calling SEGGER_SEMIHOST_GetArgs(). - - the exit symbol is defined and executes on return from main. - - the exit symbol calls destructors, atexit functions and then - calls SEGGER_SEMIHOST_Exit(). - - If not defined then - - argc and argv are not valid (main is assumed to not take parameters) - - the exit symbol is defined, executes on return from main and - halts in a loop. -*/ - -#include "hpm_csr_regs.h" - -/********************************************************************* -* -* Defines, configurable -* -********************************************************************** -*/ -#ifndef APP_ENTRY_POINT - #define APP_ENTRY_POINT reset_handler -#endif - -#ifndef ARGSSPACE - #define ARGSSPACE 128 -#endif - -/********************************************************************* -* -* Macros -* -********************************************************************** -*/ -// -// Declare a label as function symbol (without switching sections) -// -.macro MARK_FUNC Name - .global \Name - .type \Name, function -\Name: -.endm - -// -// Declare a regular function. -// Functions from the startup are placed in the init section. -// -.macro START_FUNC Name - .section .init.\Name, "ax" - .global \Name -#if __riscv_compressed - .balign 2 -#else - .balign 4 -#endif - .type \Name, function -\Name: -.endm - -// -// Declare a weak function -// -.macro WEAK_FUNC Name - .section .init.\Name, "ax", %progbits - .global \Name - .weak \Name -#if __riscv_compressed - .balign 2 -#else - .balign 4 -#endif - .type \Name, function -\Name: -.endm - -// -// Mark the end of a function and calculate its size -// -.macro END_FUNC name - .size \name,.-\name -.endm - -/********************************************************************* -* -* Externals -* -********************************************************************** -*/ - .extern APP_ENTRY_POINT // typically main - -/********************************************************************* -* -* Global functions -* -********************************************************************** -*/ -/********************************************************************* -* -* _start -* -* Function description -* Entry point for the startup code. -* Usually called by the reset handler. -* Performs all initialisation, based on the entries in the -* linker-generated init table, then calls main(). -* It is device independent, so there should not be any need for an -* end-user to modify it. -* -* Additional information -* At this point, the stack pointer should already have been -* initialized -* - by hardware (such as on Cortex-M), -* - by the device-specific reset handler, -* - or by the debugger (such as for RAM Code). -*/ -#undef L -#define L(label) .L_start_##label - -START_FUNC _start - .option push - .option norelax - lui gp, %hi(__global_pointer$) - addi gp, gp, %lo(__global_pointer$) - lui tp, %hi(__thread_pointer$) - addi tp, tp, %lo(__thread_pointer$) - .option pop - - csrw mstatus, zero - csrw mcause, zero - -#ifdef __riscv_flen - /* Enable FPU */ - li t0, CSR_MSTATUS_FS_MASK - csrrs t0, mstatus, t0 - - /* Initialize FCSR */ - fscsr zero -#endif - -#ifdef INIT_EXT_RAM_FOR_DATA - la t0, _stack_safe - mv sp, t0 - call _init_ext_ram -#endif - - lui t0, %hi(__stack_end__) - addi sp, t0, %lo(__stack_end__) - -#ifndef __NO_SYSTEM_INIT - // - // Call _init - // - call _init -#endif - // - // Call linker init functions which in turn performs the following: - // * Perform segment init - // * Perform heap init (if used) - // * Call constructors of global Objects (if any exist) - // - la s0, __SEGGER_init_table__ // Set table pointer to start of initialization table -L(RunInit): - lw a0, (s0) // Get next initialization function from table - add s0, s0, 4 // Increment table pointer to point to function arguments - jalr a0 // Call initialization function - j L(RunInit) - // -MARK_FUNC __SEGGER_init_done - // - // Time to call main(), the application entry point. - // - -#ifndef NO_CLEANUP_AT_START - /* clean up */ - call _clean_up -#endif - -#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS - #define HANDLER_TRAP freertos_risc_v_trap_handler - #define HANDLER_S_TRAP freertos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III - #define HANDLER_TRAP ucos_risc_v_trap_handler - #define HANDLER_S_TRAP ucos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_THREADX) && CONFIG_THREADX - #define HANDLER_TRAP tx_risc_v_trap_handler - #define HANDLER_S_TRAP tx_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#else - #define HANDLER_TRAP irq_handler_trap - #define HANDLER_S_TRAP irq_handler_s_trap -#endif - -#if !defined(USE_NONVECTOR_MODE) - /* Initial machine trap-vector Base */ - la t0, __vector_table - csrw mtvec, t0 - -#if defined (USE_S_MODE_IRQ) - la t0, __vector_s_table - csrw stvec, t0 -#endif - /* Enable vectored external PLIC interrupt */ - csrsi CSR_MMISC_CTL, 2 -#else - /* Initial machine trap-vector Base */ - la t0, HANDLER_TRAP - csrw mtvec, t0 -#if defined (USE_S_MODE_IRQ) - la t0, HANDLER_S_TRAP - csrw stvec, t0 -#endif - - /* Disable vectored external PLIC interrupt */ - csrci CSR_MMISC_CTL, 2 -#endif - -MARK_FUNC start -#ifndef FULL_LIBRARY - // - // In a real embedded application ("Free-standing environment"), - // main() does not get any arguments, - // which means it is not necessary to init a0 and a1. - // - call APP_ENTRY_POINT - tail exit - -END_FUNC _start - // - // end of _start - // Fall-through to exit if main ever returns. - // -MARK_FUNC exit - // - // In a free-standing environment, if returned from application: - // Loop forever. - // - j . - .size exit,.-exit -#else - // - // In a hosted environment, - // we need to load a0 and a1 with argc and argv, in order to handle - // the command line arguments. - // This is required for some programs running under control of a - // debugger, such as automated tests. - // - li a0, ARGSSPACE - la a1, args - call debug_getargs - li a0, ARGSSPACE - la a1, args - - call APP_ENTRY_POINT // Call to application entry point (usually main()) - call exit // Call exit function - j . // If we unexpectedly return from exit, hang. -END_FUNC _start -#endif - -#ifdef FULL_LIBRARY - li a0, ARGSSPACE - la a1, args - call debug_getargs - li a0, ARGSSPACE - la a1, args -#else - li a0, 0 - li a1, 0 -#endif - - call APP_ENTRY_POINT - tail exit - -END_FUNC _start - - // -#ifdef FULL_LIBRARY -/********************************************************************* -* -* exit -* -* Function description -* Exit of the system. -* Called on return from application entry point or explicit call -* to exit. -* -* Additional information -* In a hosted environment exit gracefully, by -* saving the return value, -* calling destructurs of global objects, -* calling registered atexit functions, -* and notifying the host/debugger. -*/ -#undef L -#define L(label) .L_exit_##label - -WEAK_FUNC exit - mv s1, a0 // Save the exit parameter/return result - // - // Call destructors - // - la s0, __dtors_start__ -L(Loop): - la t0, __dtors_end__ - beq s0, t0, L(End) - lw t1, 0(s0) - addi s0, s0, 4 - jalr t1 - j L(Loop) -L(End): - // - // Call atexit functions - // - call _execute_at_exit_fns - // - // Call debug_exit with return result/exit parameter - // - mv a0, s1 - call debug_exit - // - // If execution is not terminated, loop forever - // -L(ExitLoop): - j L(ExitLoop) // Loop forever. -END_FUNC exit -#endif - -#ifdef FULL_LIBRARY - .bss -args: - .space ARGSSPACE - .size args, .-args - .type args, %object -#endif - - .section .isr_vector, "ax" - .weak nmi_handler -nmi_handler: -1: j 1b - -#include "../vectors.h" - -/*************************** End of file ****************************/ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/trap.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/trap.c index 4a38669a365..3df45f565c8 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/trap.c +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -8,6 +8,10 @@ #include "hpm_common.h" #include "hpm_soc.h" +#ifdef __ICCRISCV__ +#pragma language = extended +#endif + /********************** MCAUSE exception types **************************************/ #define MCAUSE_INSTR_ADDR_MISALIGNED (0U) /* !< Instruction Address misaligned */ #define MCAUSE_INSTR_ACCESS_FAULT (1U) /* !< Instruction access fault */ @@ -46,6 +50,11 @@ __attribute__((weak)) void swi_isr(void) __attribute__((weak)) void syscall_handler(long n, long a0, long a1, long a2, long a3) { + (void) n; + (void) a0; + (void) a1; + (void) a2; + (void) a3; } __attribute__((weak)) long exception_handler(long cause, long epc) @@ -88,6 +97,7 @@ __attribute__((weak)) long exception_handler(long cause, long epc) __attribute__((weak)) long exception_s_handler(long cause, long epc) { + (void) cause; return epc; } @@ -99,11 +109,17 @@ __attribute__((weak)) void mchtmr_s_isr(void) { } -#if !defined(CONFIG_FREERTOS) && !defined(CONFIG_UCOS_III) && !defined(CONFIG_THREADX) -void irq_handler_trap(void) __attribute__ ((section(".isr_vector"), interrupt("machine"), aligned(4))); +#if !defined(CONFIG_FREERTOS) && !defined(CONFIG_UCOS_III) && !defined(CONFIG_THREADX) && !defined(CONFIG_RTTHREAD) +HPM_ATTR_MACHINE_INTERRUPT void irq_handler_trap(void); +#define IRQ_HANDLER_TRAP_AS_ISR 1 #else void irq_handler_trap(void) __attribute__ ((section(".isr_vector"))); #endif + +#if defined(__ICCRISCV__) && (IRQ_HANDLER_TRAP_AS_ISR == 1) +extern int __vector_table[]; +HPM_ATTR_MACHINE_INTERRUPT +#endif void irq_handler_trap(void) { long mcause = read_csr(CSR_MCAUSE); @@ -146,11 +162,13 @@ void irq_handler_trap(void) ((isr_func_t)__vector_table[irq_index])(); __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index); } + } #endif else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_SOFT)) { /* Machine SWI interrupt */ + intc_m_claim_swi(); swi_isr(); intc_m_complete_swi(); } else if (!(mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == MCAUSE_ECALL_FROM_MACHINE_MODE)) { @@ -187,11 +205,18 @@ void irq_handler_trap(void) #endif } -#ifndef CONFIG_FREERTOS -void irq_handler_s_trap(void) __attribute__ ((section(".isr_s_vector"), interrupt("supervisor"), aligned(4))); + +#if !defined(CONFIG_FREERTOS) && !defined(CONFIG_UCOS_III) && !defined(CONFIG_THREADX) +HPM_ATTR_SUPERVISOR_INTERRUPT void irq_handler_s_trap(void); +#define IRQ_HANDLER_TRAP_AS_ISR 1 #else void irq_handler_s_trap(void) __attribute__ ((section(".isr_s_vector"))); #endif + +#if defined(__ICCRISCV__) && (IRQ_HANDLER_TRAP_AS_ISR == 1) +extern int __vector_s_table[]; +HPM_ATTR_SUPERVISOR_INTERRUPT +#endif void irq_handler_s_trap(void) { long scause = read_csr(CSR_SCAUSE); diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/vectors.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/vectors.h index 27938d76efb..103da589bd9 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/vectors.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/vectors.h @@ -1,9 +1,192 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ +#ifdef __IAR_SYSTEMS_ASM__ + +IRQ_HANDLER macro + dc32 default_isr_\1 + endm + +IRQ_DEFAULT_HANDLER macro + PUBWEAK default_isr_\1 +default_isr_\1 + j default_irq_handler + endm + + SECTION `.isr_vector`:CODE:ROOT(9) + PUBWEAK default_irq_handler +default_irq_handler + j default_irq_handler + IRQ_DEFAULT_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_DEFAULT_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_DEFAULT_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_DEFAULT_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_DEFAULT_HANDLER 5 /* GPIO0_X IRQ handler */ + IRQ_DEFAULT_HANDLER 6 /* GPIO0_Y IRQ handler */ + IRQ_DEFAULT_HANDLER 7 /* GPIO0_Z IRQ handler */ + IRQ_DEFAULT_HANDLER 8 /* ADC0 IRQ handler */ + IRQ_DEFAULT_HANDLER 9 /* ADC1 IRQ handler */ + IRQ_DEFAULT_HANDLER 10 /* ADC2 IRQ handler */ + IRQ_DEFAULT_HANDLER 11 /* DAC IRQ handler */ + IRQ_DEFAULT_HANDLER 12 /* ACMP[0] IRQ handler */ + IRQ_DEFAULT_HANDLER 13 /* ACMP[1] IRQ handler */ + IRQ_DEFAULT_HANDLER 14 /* SPI0 IRQ handler */ + IRQ_DEFAULT_HANDLER 15 /* SPI1 IRQ handler */ + IRQ_DEFAULT_HANDLER 16 /* SPI2 IRQ handler */ + IRQ_DEFAULT_HANDLER 17 /* SPI3 IRQ handler */ + IRQ_DEFAULT_HANDLER 18 /* UART0 IRQ handler */ + IRQ_DEFAULT_HANDLER 19 /* UART1 IRQ handler */ + IRQ_DEFAULT_HANDLER 20 /* UART2 IRQ handler */ + IRQ_DEFAULT_HANDLER 21 /* UART3 IRQ handler */ + IRQ_DEFAULT_HANDLER 22 /* UART4 IRQ handler */ + IRQ_DEFAULT_HANDLER 23 /* UART5 IRQ handler */ + IRQ_DEFAULT_HANDLER 24 /* UART6 IRQ handler */ + IRQ_DEFAULT_HANDLER 25 /* UART7 IRQ handler */ + IRQ_DEFAULT_HANDLER 26 /* CAN0 IRQ handler */ + IRQ_DEFAULT_HANDLER 27 /* CAN1 IRQ handler */ + IRQ_DEFAULT_HANDLER 28 /* PTPC IRQ handler */ + IRQ_DEFAULT_HANDLER 29 /* WDG0 IRQ handler */ + IRQ_DEFAULT_HANDLER 30 /* WDG1 IRQ handler */ + IRQ_DEFAULT_HANDLER 31 /* TSNS IRQ handler */ + IRQ_DEFAULT_HANDLER 32 /* MBX0A IRQ handler */ + IRQ_DEFAULT_HANDLER 33 /* MBX0B IRQ handler */ + IRQ_DEFAULT_HANDLER 34 /* GPTMR0 IRQ handler */ + IRQ_DEFAULT_HANDLER 35 /* GPTMR1 IRQ handler */ + IRQ_DEFAULT_HANDLER 36 /* GPTMR2 IRQ handler */ + IRQ_DEFAULT_HANDLER 37 /* GPTMR3 IRQ handler */ + IRQ_DEFAULT_HANDLER 38 /* I2C0 IRQ handler */ + IRQ_DEFAULT_HANDLER 39 /* I2C1 IRQ handler */ + IRQ_DEFAULT_HANDLER 40 /* I2C2 IRQ handler */ + IRQ_DEFAULT_HANDLER 41 /* I2C3 IRQ handler */ + IRQ_DEFAULT_HANDLER 42 /* PWM0 IRQ handler */ + IRQ_DEFAULT_HANDLER 43 /* HALL0 IRQ handler */ + IRQ_DEFAULT_HANDLER 44 /* QEI0 IRQ handler */ + IRQ_DEFAULT_HANDLER 45 /* PWM1 IRQ handler */ + IRQ_DEFAULT_HANDLER 46 /* HALL1 IRQ handler */ + IRQ_DEFAULT_HANDLER 47 /* QEI1 IRQ handler */ + IRQ_DEFAULT_HANDLER 48 /* SDP IRQ handler */ + IRQ_DEFAULT_HANDLER 49 /* XPI0 IRQ handler */ + IRQ_DEFAULT_HANDLER 50 /* XPI1 IRQ handler */ + IRQ_DEFAULT_HANDLER 51 /* XDMA IRQ handler */ + IRQ_DEFAULT_HANDLER 52 /* HDMA IRQ handler */ + IRQ_DEFAULT_HANDLER 53 /* FEMC IRQ handler */ + IRQ_DEFAULT_HANDLER 54 /* RNG IRQ handler */ + IRQ_DEFAULT_HANDLER 55 /* I2S0 IRQ handler */ + IRQ_DEFAULT_HANDLER 56 /* I2S1 IRQ handler */ + IRQ_DEFAULT_HANDLER 57 /* DAO IRQ handler */ + IRQ_DEFAULT_HANDLER 58 /* PDM IRQ handler */ + IRQ_DEFAULT_HANDLER 59 /* FFA IRQ handler */ + IRQ_DEFAULT_HANDLER 60 /* NTMR0 IRQ handler */ + IRQ_DEFAULT_HANDLER 61 /* USB0 IRQ handler */ + IRQ_DEFAULT_HANDLER 62 /* ENET0 IRQ handler */ + IRQ_DEFAULT_HANDLER 63 /* SDXC0 IRQ handler */ + IRQ_DEFAULT_HANDLER 64 /* PSEC IRQ handler */ + IRQ_DEFAULT_HANDLER 65 /* PGPIO IRQ handler */ + IRQ_DEFAULT_HANDLER 66 /* PWDG IRQ handler */ + IRQ_DEFAULT_HANDLER 67 /* PTMR IRQ handler */ + IRQ_DEFAULT_HANDLER 68 /* PUART IRQ handler */ + IRQ_DEFAULT_HANDLER 69 /* FUSE IRQ handler */ + IRQ_DEFAULT_HANDLER 70 /* SECMON IRQ handler */ + IRQ_DEFAULT_HANDLER 71 /* RTC IRQ handler */ + IRQ_DEFAULT_HANDLER 72 /* BUTN IRQ handler */ + IRQ_DEFAULT_HANDLER 73 /* BGPIO IRQ handler */ + IRQ_DEFAULT_HANDLER 74 /* BVIO IRQ handler */ + IRQ_DEFAULT_HANDLER 75 /* BROWNOUT IRQ handler */ + IRQ_DEFAULT_HANDLER 76 /* SYSCTL IRQ handler */ + IRQ_DEFAULT_HANDLER 77 /* DEBUG[0] IRQ handler */ + IRQ_DEFAULT_HANDLER 78 /* DEBUG[1] IRQ handler */ + + EXTERN irq_handler_trap + SECTION `.vector_table`:CODE:ROOT(9) + PUBLIC __vector_table + DATA + +__vector_table + dc32 irq_handler_trap + IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_HANDLER 5 /* GPIO0_X IRQ handler */ + IRQ_HANDLER 6 /* GPIO0_Y IRQ handler */ + IRQ_HANDLER 7 /* GPIO0_Z IRQ handler */ + IRQ_HANDLER 8 /* ADC0 IRQ handler */ + IRQ_HANDLER 9 /* ADC1 IRQ handler */ + IRQ_HANDLER 10 /* ADC2 IRQ handler */ + IRQ_HANDLER 11 /* DAC IRQ handler */ + IRQ_HANDLER 12 /* ACMP[0] IRQ handler */ + IRQ_HANDLER 13 /* ACMP[1] IRQ handler */ + IRQ_HANDLER 14 /* SPI0 IRQ handler */ + IRQ_HANDLER 15 /* SPI1 IRQ handler */ + IRQ_HANDLER 16 /* SPI2 IRQ handler */ + IRQ_HANDLER 17 /* SPI3 IRQ handler */ + IRQ_HANDLER 18 /* UART0 IRQ handler */ + IRQ_HANDLER 19 /* UART1 IRQ handler */ + IRQ_HANDLER 20 /* UART2 IRQ handler */ + IRQ_HANDLER 21 /* UART3 IRQ handler */ + IRQ_HANDLER 22 /* UART4 IRQ handler */ + IRQ_HANDLER 23 /* UART5 IRQ handler */ + IRQ_HANDLER 24 /* UART6 IRQ handler */ + IRQ_HANDLER 25 /* UART7 IRQ handler */ + IRQ_HANDLER 26 /* CAN0 IRQ handler */ + IRQ_HANDLER 27 /* CAN1 IRQ handler */ + IRQ_HANDLER 28 /* PTPC IRQ handler */ + IRQ_HANDLER 29 /* WDG0 IRQ handler */ + IRQ_HANDLER 30 /* WDG1 IRQ handler */ + IRQ_HANDLER 31 /* TSNS IRQ handler */ + IRQ_HANDLER 32 /* MBX0A IRQ handler */ + IRQ_HANDLER 33 /* MBX0B IRQ handler */ + IRQ_HANDLER 34 /* GPTMR0 IRQ handler */ + IRQ_HANDLER 35 /* GPTMR1 IRQ handler */ + IRQ_HANDLER 36 /* GPTMR2 IRQ handler */ + IRQ_HANDLER 37 /* GPTMR3 IRQ handler */ + IRQ_HANDLER 38 /* I2C0 IRQ handler */ + IRQ_HANDLER 39 /* I2C1 IRQ handler */ + IRQ_HANDLER 40 /* I2C2 IRQ handler */ + IRQ_HANDLER 41 /* I2C3 IRQ handler */ + IRQ_HANDLER 42 /* PWM0 IRQ handler */ + IRQ_HANDLER 43 /* HALL0 IRQ handler */ + IRQ_HANDLER 44 /* QEI0 IRQ handler */ + IRQ_HANDLER 45 /* PWM1 IRQ handler */ + IRQ_HANDLER 46 /* HALL1 IRQ handler */ + IRQ_HANDLER 47 /* QEI1 IRQ handler */ + IRQ_HANDLER 48 /* SDP IRQ handler */ + IRQ_HANDLER 49 /* XPI0 IRQ handler */ + IRQ_HANDLER 50 /* XPI1 IRQ handler */ + IRQ_HANDLER 51 /* XDMA IRQ handler */ + IRQ_HANDLER 52 /* HDMA IRQ handler */ + IRQ_HANDLER 53 /* FEMC IRQ handler */ + IRQ_HANDLER 54 /* RNG IRQ handler */ + IRQ_HANDLER 55 /* I2S0 IRQ handler */ + IRQ_HANDLER 56 /* I2S1 IRQ handler */ + IRQ_HANDLER 57 /* DAO IRQ handler */ + IRQ_HANDLER 58 /* PDM IRQ handler */ + IRQ_HANDLER 59 /* FFA IRQ handler */ + IRQ_HANDLER 60 /* NTMR0 IRQ handler */ + IRQ_HANDLER 61 /* USB0 IRQ handler */ + IRQ_HANDLER 62 /* ENET0 IRQ handler */ + IRQ_HANDLER 63 /* SDXC0 IRQ handler */ + IRQ_HANDLER 64 /* PSEC IRQ handler */ + IRQ_HANDLER 65 /* PGPIO IRQ handler */ + IRQ_HANDLER 66 /* PWDG IRQ handler */ + IRQ_HANDLER 67 /* PTMR IRQ handler */ + IRQ_HANDLER 68 /* PUART IRQ handler */ + IRQ_HANDLER 69 /* FUSE IRQ handler */ + IRQ_HANDLER 70 /* SECMON IRQ handler */ + IRQ_HANDLER 71 /* RTC IRQ handler */ + IRQ_HANDLER 72 /* BUTN IRQ handler */ + IRQ_HANDLER 73 /* BGPIO IRQ handler */ + IRQ_HANDLER 74 /* BVIO IRQ handler */ + IRQ_HANDLER 75 /* BROWNOUT IRQ handler */ + IRQ_HANDLER 76 /* SYSCTL IRQ handler */ + IRQ_HANDLER 77 /* DEBUG[0] IRQ handler */ + IRQ_HANDLER 78 /* DEBUG[1] IRQ handler */ + +#else + .global default_irq_handler .weak default_irq_handler .align 2 @@ -103,6 +286,190 @@ IRQ_HANDLER 77 /* DEBUG[0] IRQ handler */ IRQ_HANDLER 78 /* DEBUG[1] IRQ handler */ +#endif + +#ifdef __IAR_SYSTEMS_ASM__ + +IRQ_S_HANDLER macro + dc32 default_isr_s_\1 + endm + +IRQ_DEFAULT_S_HANDLER macro + PUBWEAK default_isr_s_\1 +default_isr_s_\1 + j default_irq_s_handler + endm + + SECTION `.isr_s_vector`:CODE:ROOT(9) + PUBWEAK default_irq_s_handler +default_irq_s_handler + j default_irq_s_handler + IRQ_DEFAULT_S_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_DEFAULT_S_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_DEFAULT_S_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_DEFAULT_S_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_DEFAULT_S_HANDLER 5 /* GPIO0_X IRQ handler */ + IRQ_DEFAULT_S_HANDLER 6 /* GPIO0_Y IRQ handler */ + IRQ_DEFAULT_S_HANDLER 7 /* GPIO0_Z IRQ handler */ + IRQ_DEFAULT_S_HANDLER 8 /* ADC0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 9 /* ADC1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 10 /* ADC2 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 11 /* DAC IRQ handler */ + IRQ_DEFAULT_S_HANDLER 12 /* ACMP[0] IRQ handler */ + IRQ_DEFAULT_S_HANDLER 13 /* ACMP[1] IRQ handler */ + IRQ_DEFAULT_S_HANDLER 14 /* SPI0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 15 /* SPI1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 16 /* SPI2 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 17 /* SPI3 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 18 /* UART0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 19 /* UART1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 20 /* UART2 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 21 /* UART3 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 22 /* UART4 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 23 /* UART5 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 24 /* UART6 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 25 /* UART7 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 26 /* CAN0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 27 /* CAN1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 28 /* PTPC IRQ handler */ + IRQ_DEFAULT_S_HANDLER 29 /* WDG0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 30 /* WDG1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 31 /* TSNS IRQ handler */ + IRQ_DEFAULT_S_HANDLER 32 /* MBX0A IRQ handler */ + IRQ_DEFAULT_S_HANDLER 33 /* MBX0B IRQ handler */ + IRQ_DEFAULT_S_HANDLER 34 /* GPTMR0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 35 /* GPTMR1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 36 /* GPTMR2 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 37 /* GPTMR3 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 38 /* I2C0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 39 /* I2C1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 40 /* I2C2 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 41 /* I2C3 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 42 /* PWM0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 43 /* HALL0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 44 /* QEI0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 45 /* PWM1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 46 /* HALL1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 47 /* QEI1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 48 /* SDP IRQ handler */ + IRQ_DEFAULT_S_HANDLER 49 /* XPI0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 50 /* XPI1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 51 /* XDMA IRQ handler */ + IRQ_DEFAULT_S_HANDLER 52 /* HDMA IRQ handler */ + IRQ_DEFAULT_S_HANDLER 53 /* FEMC IRQ handler */ + IRQ_DEFAULT_S_HANDLER 54 /* RNG IRQ handler */ + IRQ_DEFAULT_S_HANDLER 55 /* I2S0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 56 /* I2S1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 57 /* DAO IRQ handler */ + IRQ_DEFAULT_S_HANDLER 58 /* PDM IRQ handler */ + IRQ_DEFAULT_S_HANDLER 59 /* FFA IRQ handler */ + IRQ_DEFAULT_S_HANDLER 60 /* NTMR0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 61 /* USB0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 62 /* ENET0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 63 /* SDXC0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 64 /* PSEC IRQ handler */ + IRQ_DEFAULT_S_HANDLER 65 /* PGPIO IRQ handler */ + IRQ_DEFAULT_S_HANDLER 66 /* PWDG IRQ handler */ + IRQ_DEFAULT_S_HANDLER 67 /* PTMR IRQ handler */ + IRQ_DEFAULT_S_HANDLER 68 /* PUART IRQ handler */ + IRQ_DEFAULT_S_HANDLER 69 /* FUSE IRQ handler */ + IRQ_DEFAULT_S_HANDLER 70 /* SECMON IRQ handler */ + IRQ_DEFAULT_S_HANDLER 71 /* RTC IRQ handler */ + IRQ_DEFAULT_S_HANDLER 72 /* BUTN IRQ handler */ + IRQ_DEFAULT_S_HANDLER 73 /* BGPIO IRQ handler */ + IRQ_DEFAULT_S_HANDLER 74 /* BVIO IRQ handler */ + IRQ_DEFAULT_S_HANDLER 75 /* BROWNOUT IRQ handler */ + IRQ_DEFAULT_S_HANDLER 76 /* SYSCTL IRQ handler */ + IRQ_DEFAULT_S_HANDLER 77 /* DEBUG[0] IRQ handler */ + IRQ_DEFAULT_S_HANDLER 78 /* DEBUG[1] IRQ handler */ + + EXTERN irq_handler_s_trap + SECTION `.vector_s_table`:CODE:ROOT(9) + PUBLIC __vector_s_table + DATA + +__vector_s_table + dc32 irq_handler_s_trap + IRQ_S_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_S_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_S_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_S_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_S_HANDLER 5 /* GPIO0_X IRQ handler */ + IRQ_S_HANDLER 6 /* GPIO0_Y IRQ handler */ + IRQ_S_HANDLER 7 /* GPIO0_Z IRQ handler */ + IRQ_S_HANDLER 8 /* ADC0 IRQ handler */ + IRQ_S_HANDLER 9 /* ADC1 IRQ handler */ + IRQ_S_HANDLER 10 /* ADC2 IRQ handler */ + IRQ_S_HANDLER 11 /* DAC IRQ handler */ + IRQ_S_HANDLER 12 /* ACMP[0] IRQ handler */ + IRQ_S_HANDLER 13 /* ACMP[1] IRQ handler */ + IRQ_S_HANDLER 14 /* SPI0 IRQ handler */ + IRQ_S_HANDLER 15 /* SPI1 IRQ handler */ + IRQ_S_HANDLER 16 /* SPI2 IRQ handler */ + IRQ_S_HANDLER 17 /* SPI3 IRQ handler */ + IRQ_S_HANDLER 18 /* UART0 IRQ handler */ + IRQ_S_HANDLER 19 /* UART1 IRQ handler */ + IRQ_S_HANDLER 20 /* UART2 IRQ handler */ + IRQ_S_HANDLER 21 /* UART3 IRQ handler */ + IRQ_S_HANDLER 22 /* UART4 IRQ handler */ + IRQ_S_HANDLER 23 /* UART5 IRQ handler */ + IRQ_S_HANDLER 24 /* UART6 IRQ handler */ + IRQ_S_HANDLER 25 /* UART7 IRQ handler */ + IRQ_S_HANDLER 26 /* CAN0 IRQ handler */ + IRQ_S_HANDLER 27 /* CAN1 IRQ handler */ + IRQ_S_HANDLER 28 /* PTPC IRQ handler */ + IRQ_S_HANDLER 29 /* WDG0 IRQ handler */ + IRQ_S_HANDLER 30 /* WDG1 IRQ handler */ + IRQ_S_HANDLER 31 /* TSNS IRQ handler */ + IRQ_S_HANDLER 32 /* MBX0A IRQ handler */ + IRQ_S_HANDLER 33 /* MBX0B IRQ handler */ + IRQ_S_HANDLER 34 /* GPTMR0 IRQ handler */ + IRQ_S_HANDLER 35 /* GPTMR1 IRQ handler */ + IRQ_S_HANDLER 36 /* GPTMR2 IRQ handler */ + IRQ_S_HANDLER 37 /* GPTMR3 IRQ handler */ + IRQ_S_HANDLER 38 /* I2C0 IRQ handler */ + IRQ_S_HANDLER 39 /* I2C1 IRQ handler */ + IRQ_S_HANDLER 40 /* I2C2 IRQ handler */ + IRQ_S_HANDLER 41 /* I2C3 IRQ handler */ + IRQ_S_HANDLER 42 /* PWM0 IRQ handler */ + IRQ_S_HANDLER 43 /* HALL0 IRQ handler */ + IRQ_S_HANDLER 44 /* QEI0 IRQ handler */ + IRQ_S_HANDLER 45 /* PWM1 IRQ handler */ + IRQ_S_HANDLER 46 /* HALL1 IRQ handler */ + IRQ_S_HANDLER 47 /* QEI1 IRQ handler */ + IRQ_S_HANDLER 48 /* SDP IRQ handler */ + IRQ_S_HANDLER 49 /* XPI0 IRQ handler */ + IRQ_S_HANDLER 50 /* XPI1 IRQ handler */ + IRQ_S_HANDLER 51 /* XDMA IRQ handler */ + IRQ_S_HANDLER 52 /* HDMA IRQ handler */ + IRQ_S_HANDLER 53 /* FEMC IRQ handler */ + IRQ_S_HANDLER 54 /* RNG IRQ handler */ + IRQ_S_HANDLER 55 /* I2S0 IRQ handler */ + IRQ_S_HANDLER 56 /* I2S1 IRQ handler */ + IRQ_S_HANDLER 57 /* DAO IRQ handler */ + IRQ_S_HANDLER 58 /* PDM IRQ handler */ + IRQ_S_HANDLER 59 /* FFA IRQ handler */ + IRQ_S_HANDLER 60 /* NTMR0 IRQ handler */ + IRQ_S_HANDLER 61 /* USB0 IRQ handler */ + IRQ_S_HANDLER 62 /* ENET0 IRQ handler */ + IRQ_S_HANDLER 63 /* SDXC0 IRQ handler */ + IRQ_S_HANDLER 64 /* PSEC IRQ handler */ + IRQ_S_HANDLER 65 /* PGPIO IRQ handler */ + IRQ_S_HANDLER 66 /* PWDG IRQ handler */ + IRQ_S_HANDLER 67 /* PTMR IRQ handler */ + IRQ_S_HANDLER 68 /* PUART IRQ handler */ + IRQ_S_HANDLER 69 /* FUSE IRQ handler */ + IRQ_S_HANDLER 70 /* SECMON IRQ handler */ + IRQ_S_HANDLER 71 /* RTC IRQ handler */ + IRQ_S_HANDLER 72 /* BUTN IRQ handler */ + IRQ_S_HANDLER 73 /* BGPIO IRQ handler */ + IRQ_S_HANDLER 74 /* BVIO IRQ handler */ + IRQ_S_HANDLER 75 /* BROWNOUT IRQ handler */ + IRQ_S_HANDLER 76 /* SYSCTL IRQ handler */ + IRQ_S_HANDLER 77 /* DEBUG[0] IRQ handler */ + IRQ_S_HANDLER 78 /* DEBUG[1] IRQ handler */ + +#else .global default_irq_s_handler .weak default_irq_s_handler @@ -202,3 +569,5 @@ IRQ_S_HANDLER 76 /* SYSCTL IRQ handler */ IRQ_S_HANDLER 77 /* DEBUG[0] IRQ handler */ IRQ_S_HANDLER 78 /* DEBUG[1] IRQ handler */ + +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/HPM6750_svd.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/HPM6750_svd.xml new file mode 100644 index 00000000000..b0936956b06 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/HPM6750_svd.xml @@ -0,0 +1,33758 @@ + + + HPMICRO + HPM6750 + HPM6700/HPM6400 + 1.0 + HPM6700/HPM6400 device + + /* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + + + other + r0p0 + little + false + true + true + 7 + false + + + + 8 + 32 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + + + FGPIO + FGPIO + GPIO + 0xc0000 + + 0x0 + 0x824 + registers + + + + 16 + 0x10 + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + DI[%s] + no description available + 0x0 + + VALUE + GPIO input value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-only + + + + + + 16 + 0x10 + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + DO[%s] + no description available + 0x100 + + VALUE + GPIO output value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + SET + GPIO output set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + CLEAR + GPIO output clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + TOGGLE + GPIO output toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + + 16 + 0x10 + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + OE[%s] + no description available + 0x200 + + VALUE + GPIO direction value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + SET + GPIO direction set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + CLEAR + GPIO direction clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + TOGGLE + GPIO direction toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + + 16 + 0x10 + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + IF[%s] + no description available + 0x300 + + VALUE + GPIO interrupt flag value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + write-only + + + + + + 16 + 0x10 + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + IE[%s] + no description available + 0x400 + + VALUE + GPIO interrupt enable value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + SET + GPIO interrupt enable set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + CLEAR + GPIO interrupt enable clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + TOGGLE + GPIO interrupt enable toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + + 16 + 0x10 + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + PL[%s] + no description available + 0x500 + + VALUE + GPIO interrupt polarity value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + SET + GPIO interrupt polarity set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + CLEAR + GPIO interrupt polarity clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + TOGGLE + GPIO interrupt polarity toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + + 16 + 0x10 + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + TP[%s] + no description available + 0x600 + + VALUE + GPIO interrupt type value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + SET + GPIO interrupt type set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + CLEAR + GPIO interrupt type clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TOGGLE + GPIO interrupt type toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + + 16 + 0x10 + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + AS[%s] + no description available + 0x700 + + VALUE + GPIO interrupt asynchronous value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + SET + GPIO interrupt asynchronous set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + CLEAR + GPIO interrupt asynchronous clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + TOGGLE + GPIO interrupt asynchronous toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + + + + GPIO0 + GPIO0 + GPIO + 0xf0000000 + + + GPIO1 + GPIO1 + GPIO + 0xf0004000 + + + PGPIO + PGPIO + GPIO + 0xf40dc000 + + + BGPIO + BGPIO + GPIO + 0xf5014000 + + + PLIC + PLIC + PLIC + 0xe4000000 + + 0x0 + 0x202000 + registers + + + + feature + Feature enable register + 0x0 + 32 + 0x00000000 + 0x00000003 + + + VECTORED + Vector mode enable +0: Disabled +1: Enabled + 1 + 1 + read-write + + + PREEMPT + Preemptive priority interrupt enable +0: Disabled +1: Enabled + 0 + 1 + read-write + + + + + 127 + 0x4 + PRIORITY1,PRIORITY2,PRIORITY3,PRIORITY4,PRIORITY5,PRIORITY6,PRIORITY7,PRIORITY8,PRIORITY9,PRIORITY10,PRIORITY11,PRIORITY12,PRIORITY13,PRIORITY14,PRIORITY15,PRIORITY16,PRIORITY17,PRIORITY18,PRIORITY19,PRIORITY20,PRIORITY21,PRIORITY22,PRIORITY23,PRIORITY24,PRIORITY25,PRIORITY26,PRIORITY27,PRIORITY28,PRIORITY29,PRIORITY30,PRIORITY31,PRIORITY32,PRIORITY33,PRIORITY34,PRIORITY35,PRIORITY36,PRIORITY37,PRIORITY38,PRIORITY39,PRIORITY40,PRIORITY41,PRIORITY42,PRIORITY43,PRIORITY44,PRIORITY45,PRIORITY46,PRIORITY47,PRIORITY48,PRIORITY49,PRIORITY50,PRIORITY51,PRIORITY52,PRIORITY53,PRIORITY54,PRIORITY55,PRIORITY56,PRIORITY57,PRIORITY58,PRIORITY59,PRIORITY60,PRIORITY61,PRIORITY62,PRIORITY63,PRIORITY64,PRIORITY65,PRIORITY66,PRIORITY67,PRIORITY68,PRIORITY69,PRIORITY70,PRIORITY71,PRIORITY72,PRIORITY73,PRIORITY74,PRIORITY75,PRIORITY76,PRIORITY77,PRIORITY78,PRIORITY79,PRIORITY80,PRIORITY81,PRIORITY82,PRIORITY83,PRIORITY84,PRIORITY85,PRIORITY86,PRIORITY87,PRIORITY88,PRIORITY89,PRIORITY90,PRIORITY91,PRIORITY92,PRIORITY93,PRIORITY94,PRIORITY95,PRIORITY96,PRIORITY97,PRIORITY98,PRIORITY99,PRIORITY100,PRIORITY101,PRIORITY102,PRIORITY103,PRIORITY104,PRIORITY105,PRIORITY106,PRIORITY107,PRIORITY108,PRIORITY109,PRIORITY110,PRIORITY111,PRIORITY112,PRIORITY113,PRIORITY114,PRIORITY115,PRIORITY116,PRIORITY117,PRIORITY118,PRIORITY119,PRIORITY120,PRIORITY121,PRIORITY122,PRIORITY123,PRIORITY124,PRIORITY125,PRIORITY126,PRIORITY127 + PRIORITY[%s] + no description available + 0x4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + 4 + 0x4 + PENDING0,PENDING1,PENDING2,PENDING3 + PENDING[%s] + no description available + 0x1000 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + 4 + 0x4 + TRIGGER0,TRIGGER1,TRIGGER2,TRIGGER3 + TRIGGER[%s] + no description available + 0x1080 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. +0: Level-triggered interrupt +1: Edge-triggered interrupt + 0 + 32 + read-only + + + + + NUMBER + Number of supported interrupt sources and targets + 0x1100 + 32 + 0xFFFFFFFF + + + NUM_TARGET + The number of supported targets + 16 + 16 + read-only + + + NUM_INTERRUPT + The number of supported interrupt sources + 0 + 16 + read-only + + + + + INFO + Version and the maximum priority + 0x1104 + 32 + 0xFFFFFFFF + + + MAX_PRIORITY + The maximum priority supported + 16 + 16 + read-only + + + VERSION + The version of the PLIC design + 0 + 16 + read-only + + + + + 2 + 0x80 + target0,target1 + TARGETINT[%s] + no description available + 0x2000 + + 4 + 0x4 + INTEN0,INTEN1,INTEN2,INTEN3 + INTEN[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + + 2 + 0x1000 + target0,target1 + TARGETCONFIG[%s] + no description available + 0x200000 + + THRESHOLD + Target0 priority threshold + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + THRESHOLD + Interrupt priority threshold. + 0 + 32 + read-write + + + + + CLAIM + Target claim and complete + 0x4 + 32 + 0x00000000 + 0x000003FF + + + INTERRUPT_ID + On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). + 0 + 10 + read-write + + + + + PPS + Preempted priority stack + 0x400 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY_PREEMPTED + Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. + 0 + 32 + read-write + + + + + + + + MCHTMR + MCHTMR + MCHTMR + 0xe6000000 + + 0x0 + 0x10 + registers + + + + MTIME + Machine Time + 0x0 + 64 + 0x0000000000020210 + 0xFFFFFFFFFFFFFFFF + + + MTIME + Machine time + 0 + 64 + read-write + + + + + MTIMECMP + Machine Time Compare + 0x8 + 64 + 0x0000000000020210 + 0xFFFFFFFFFFFFFFFF + + + MTIMECMP + Machine time compare + 0 + 64 + read-write + + + + + + + PLICSW + PLICSW + PLIC_SW + 0xe6400000 + + 0x1000 + 0x1ff008 + registers + + + + PENDING + Pending status + 0x1000 + 32 + 0x00000000 + 0x00000002 + + + INTERRUPT + writing 1 to trigger software interrupt + 1 + 1 + read-write + + + + + INTEN + Interrupt enable + 0x2000 + 32 + 0x00000000 + 0x00000001 + + + INTERRUPT + enable software interrupt + 0 + 1 + read-write + + + + + CLAIM + Claim and complete. + 0x200004 + 32 + 0x00000000 + 0x00000001 + + + INTERRUPT_ID + On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). + 0 + 1 + read-write + + + + + + + GPIOM + GPIOM + GPIOM + 0xf0008000 + + 0x0 + 0x800 + registers + + + + 16 + 0x80 + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + ASSIGN[%s] + no description available + 0x0 + + 32 + 0x4 + PIN00,PIN01,PIN02,PIN03,PIN04,PIN05,PIN06,PIN07,PIN08,PIN09,PIN10,PIN11,PIN12,PIN13,PIN14,PIN15,PIN16,PIN17,PIN18,PIN19,PIN20,PIN21,PIN22,PIN23,PIN24,PIN25,PIN26,PIN27,PIN28,PIN29,PIN30,PIN31 + PIN[%s] + no description available + 0x0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + + + + ADC0 + ADC0 + ADC12 + 0xf0010000 + + 0x0 + 0x1214 + registers + + + + 12 + 0x4 + trg0a,trg0b,trg0c,trg1a,trg1b,trg1c,trg2a,trg2b,trg2c,trg3a,trg3b,trg3c + CONFIG[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFF3F3F3F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interrupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interrupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interrupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + INTEN0 + interrupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + trg_dma_addr + No description available + 0x30 + 32 + 0x00000000 + 0xFFFFFFFC + + + TRG_DMA_ADDR + buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) + 2 + 30 + read-write + + + + + trg_sw_sta + No description available + 0x34 + 32 + 0x00000000 + 0x0000001F + + + TRG_SW_STA + SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it. + 4 + 1 + read-write + + + TRIG_SW_INDEX + which trigger for the SW trigger +0 for trig0a, 1 for trig0b… +3 for trig1a, …11 for trig3c + 0 + 4 + read-write + + + + + 19 + 0x4 + chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15,chn16,chn17,chn18 + BUS_RESULT[%s] + no description available + 0x400 + 32 + 0x00000000 + 0x0001FFF0 + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 4 + 12 + read-only + + + + + buf_cfg0 + No description available + 0x500 + 32 + 0x00000000 + 0x00000001 + + + WAIT_DIS + set to disable read waiting, get result immediately but maybe not current conversion result. + 0 + 1 + read-write + + + + + seq_cfg0 + No description available + 0x800 + 32 + 0x00000000 + 0x80000F1F + + + CYCLE + current dma write cycle bit + 31 + 1 + read-only + + + SEQ_LEN + sequence queue length, 0 for one, 0xF for 16 + 8 + 4 + read-write + + + RESTART_EN + if set together with cont_en, HW will continue process the whole queue after trigger once. +If cont_en is 0, this bit is not used + 4 + 1 + read-write + + + CONT_EN + if set, HW will continue process the queue till end(seq_len) after trigger once + 3 + 1 + read-write + + + SW_TRIG + SW trigger, pulse signal, cleared by HW one cycle later + 2 + 1 + write-only + + + SW_TRIG_EN + set to enable SW trigger + 1 + 1 + read-write + + + HW_TRIG_EN + set to enable external HW trigger, only trigger on posedge + 0 + 1 + read-write + + + + + seq_dma_addr + No description available + 0x804 + 32 + 0x00000000 + 0xFFFFFFFC + + + TAR_ADDR + dma target address, should be 4-byte aligned + 2 + 30 + read-write + + + + + seq_wr_addr + No description available + 0x808 + 32 + 0x00000000 + 0x00000FFF + + + SEQ_WR_POINTER + HW update this field after each dma write, it indicate the next dma write pointer. +dma write address is (tar_addr+seq_wr_pointer)*4 + 0 + 12 + read-only + + + + + seq_dma_cfg + No description available + 0x80c + 32 + 0x00000000 + 0x0FFF3FFF + + + STOP_POS + if stop_en is set, SW is responsible to update this field to the next read point, HW should not write data to this point since it's not read out by SW yet + 16 + 12 + read-write + + + DMA_RST + set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. +SW should clear all cycle bit in buffer to 0 before clear dma_rst + 13 + 1 + read-write + + + STOP_EN + set to stop dma if reach the stop_pos + 12 + 1 + read-write + + + BUF_LEN + dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 +0 for 4byte; +0xFFF for 16kbyte. + 0 + 12 + read-write + + + + + 16 + 0x4 + cfg0,cfg1,cfg2,cfg3,cfg4,cfg5,cfg6,cfg7,cfg8,cfg9,cfg10,cfg11,cfg12,cfg13,cfg14,cfg15 + SEQ_QUE[%s] + no description available + 0x810 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + 19 + 0x10 + chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15,chn16,chn17,chn18 + PRD_CFG[%s] + no description available + 0xc00 + + prd_cfg + No description available + 0x0 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + prd_thshd_cfg + No description available + 0x4 + 32 + 0x00000000 + 0xFFF0FFF0 + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 20 + 12 + read-write + + + THSHDL + threshold low + 4 + 12 + read-write + + + + + prd_result + No description available + 0x8 + 32 + 0x00000000 + 0x0000FFF0 + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 4 + 12 + read-only + + + + + + 19 + 0x4 + chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15,chn16,chn17,chn18 + SAMPLE_CFG[%s] + no description available + 0x1000 + 32 + 0x00000000 + 0x00001FFF + + + DIFF_SEL + set to 1 to select differential channel + 12 + 1 + read-write + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample_clock_number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + conv_cfg1 + No description available + 0x1104 + 32 + 0x00000000 + 0x000001FF + + + CONVERT_CLOCK_NUMBER + convert clock numbers, set to 13 (0xD) for 12bit mode, which means convert need 14 adc clock cycles(based on clock after divider); +set to 11 for 10bit mode; set to 9 for 8bit mode; set to 7 or 6bit mode; +Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 13 for 12bit mode, clock_divder to 2, then each ADC conversion(plus sample) need 18(14 convert, 4 sample) cycles(66MHz). + 4 + 5 + read-write + + + CLOCK_DIVIDER + clock_period, N half clock cycle per half adc cycle +0 for same adc_clk and bus_clk, +1 for 1:2, +2 for 1:3, +... +15 for 1:16 +Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk + 0 + 4 + read-write + + + + + adc_cfg0 + No description available + 0x1108 + 32 + 0x00000000 + 0xA0000000 + + + SEL_SYNC_AHB + set to 1 will enable sync AHB bus, to get better bus performance. +Adc_clk must to be set to same as bus clock at this mode + 31 + 1 + read-write + + + ADC_AHB_EN + set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; + 29 + 1 + read-write + + + + + int_sts + No description available + 0x1110 + 32 + 0x00000000 + 0xFFE7FFFF + + + TRIG_CMPT + interrupt for one trigger conversion complete if enabled + 31 + 1 + read-write + + + TRIG_SW_CFLCT + No description available + 30 + 1 + read-write + + + TRIG_HW_CFLCT + No description available + 29 + 1 + read-write + + + READ_CFLCT + read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel + 28 + 1 + read-write + + + SEQ_SW_CFLCT + sequence queue conflict interrupt, set if HW or SW trigger received during conversion + 27 + 1 + read-write + + + SEQ_HW_CFLCT + No description available + 26 + 1 + read-write + + + SEQ_DMAABT + dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set + 25 + 1 + read-write + + + SEQ_CMPT + the whole sequence complete interrupt + 24 + 1 + read-write + + + SEQ_CVC + one conversion complete in seq_queue if related seq_int_en is set + 23 + 1 + read-write + + + DMA_FIFO_FULL + No description available + 22 + 1 + read-write + + + AHB_ERR + set if got hresp=1 + 21 + 1 + read-write + + + WDOG + set if one chanel watch dog event triggered + 0 + 19 + read-write + + + + + int_en + No description available + 0x1114 + 32 + 0x00000000 + 0xFFE7FFFF + + + TRIG_CMPT + interrupt for one trigger conversion complete if enabled + 31 + 1 + read-write + + + TRIG_SW_CFLCT + No description available + 30 + 1 + read-write + + + TRIG_HW_CFLCT + No description available + 29 + 1 + read-write + + + READ_CFLCT + read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel + 28 + 1 + read-write + + + SEQ_SW_CFLCT + sequence queue conflict interrupt, set if HW or SW trigger received during conversion + 27 + 1 + read-write + + + SEQ_HW_CFLCT + No description available + 26 + 1 + read-write + + + SEQ_DMAABT + dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set + 25 + 1 + read-write + + + SEQ_CMPT + the whole sequence complete interrupt + 24 + 1 + read-write + + + SEQ_CVC + one conversion complete in seq_queue if related seq_int_en is set + 23 + 1 + read-write + + + DMA_FIFO_FULL + DMA fifo full interrupt, user need to check clock frequency if it's set. + 22 + 1 + read-write + + + AHB_ERR + set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr + 21 + 1 + read-write + + + WDOG + set if one chanel watch dog event triggered + 0 + 19 + read-write + + + + + ana_ctrl0 + No description available + 0x1200 + 32 + 0x00000000 + 0x7F7F487E + + + CAL_VAL_DIFF + calibration value for differential mode + 24 + 7 + read-write + + + CAL_VAL_SE + calibration value for single-end mode + 16 + 7 + read-write + + + REARM_EN + set will insert one adc cycle rearm before sample, user need to increase one to sample_clock_number + 14 + 1 + read-write + + + SELRANGE_LDO + Defines the range for the LDO reference (vdd_soc) +selrange_ldo = 0: LDO reference dvdd or vref_ldo in range [0.81;0.99] +selrange_ldo = 1: LDO reference dvdd or vref_ldo in range [0.99;1.21] + 11 + 1 + read-write + + + ENLDO + set to enable adc LDO, need at least 20us for LDO to be stable. + 6 + 1 + read-write + + + ENADC + set to enable adc analog function. user need set it after LDO stable, or wait at least 20us after setting enldo, then set this bit. + 5 + 1 + read-write + + + RESETADC + set to 1 to reset adc analog; default high. + 4 + 1 + read-write + + + RESETCAL + set to 1 to reset calibration logic; default high. + 3 + 1 + read-write + + + STARTCAL + set to start the offset calibration cycle (Active H). user need to clear it after setting it. + 2 + 1 + read-write + + + LOADCAL + Signal that loads the offset calibration word into the internal registers (Active H) + 1 + 1 + read-write + + + + + ana_ctrl1 + No description available + 0x1204 + 32 + 0x00000000 + 0x000000C0 + + + SELRES + 11-12bit +10-10bit +01-8bit +00-6bit + 6 + 2 + read-write + + + + + ana_status + No description available + 0x1210 + 32 + 0x00000000 + 0x000000FF + + + CALON + Indicates if the ADC is in calibration mode (Active H). + 7 + 1 + read-write + + + CAL_OUT + No description available + 0 + 7 + read-write + + + + + + + ADC1 + ADC1 + ADC12 + 0xf0014000 + + + ADC2 + ADC2 + ADC12 + 0xf0018000 + + + ADC3 + ADC3 + ADC16 + 0xf001c000 + + 0x0 + 0x1464 + registers + + + + 12 + 0x4 + trg0a,trg0b,trg0c,trg1a,trg1b,trg1c,trg2a,trg2b,trg2c,trg3a,trg3b,trg3c + CONFIG[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFF3F3F3F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interrupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interrupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interrupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + INTEN0 + interrupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + trg_dma_addr + No description available + 0x30 + 32 + 0x00000000 + 0xFFFFFFFC + + + TRG_DMA_ADDR + buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) + 2 + 30 + read-write + + + + + trg_sw_sta + No description available + 0x34 + 32 + 0x00000000 + 0x0000001F + + + TRG_SW_STA + SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it. + 4 + 1 + read-write + + + TRIG_SW_INDEX + which trigger for the SW trigger +0 for trig0a, 1 for trig0b… +3 for trig1a, …11 for trig3c + 0 + 4 + read-write + + + + + 8 + 0x4 + chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7 + BUS_RESULT[%s] + no description available + 0x400 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + buf_cfg0 + No description available + 0x500 + 32 + 0x00000000 + 0x00000001 + + + WAIT_DIS + set to disable read waiting, get result immediately but maybe not current conversion result. + 0 + 1 + read-write + + + + + seq_cfg0 + No description available + 0x800 + 32 + 0x00000000 + 0x80000F1F + + + CYCLE + current dma write cycle bit + 31 + 1 + read-only + + + SEQ_LEN + sequence queue length, 0 for one, 0xF for 16 + 8 + 4 + read-write + + + RESTART_EN + if set together with cont_en, HW will continue process the whole queue after trigger once. +If cont_en is 0, this bit is not used + 4 + 1 + read-write + + + CONT_EN + if set, HW will continue process the queue till end(seq_len) after trigger once + 3 + 1 + read-write + + + SW_TRIG + SW trigger, pulse signal, cleared by HW one cycle later + 2 + 1 + write-only + + + SW_TRIG_EN + set to enable SW trigger + 1 + 1 + read-write + + + HW_TRIG_EN + set to enable external HW trigger, only trigger on posedge + 0 + 1 + read-write + + + + + seq_dma_addr + No description available + 0x804 + 32 + 0x00000000 + 0xFFFFFFFC + + + TAR_ADDR + dma target address, should be 4-byte aligned + 2 + 30 + read-write + + + + + seq_dma_cfg + No description available + 0x80c + 32 + 0x00000000 + 0x0FFF3FFF + + + STOP_POS + if stop_en is set, SW is responsible to update this field to the next read point, HW should not write data to this point since it's not read out by SW yet + 16 + 12 + read-write + + + DMA_RST + set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. +SW should clear all cycle bit in buffer to 0 before clear dma_rst + 13 + 1 + read-write + + + STOP_EN + set to stop dma if reach the stop_pos + 12 + 1 + read-write + + + BUF_LEN + dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 +0 for 4byte; +0xFFF for 16kbyte. + 0 + 12 + read-write + + + + + 16 + 0x4 + cfg0,cfg1,cfg2,cfg3,cfg4,cfg5,cfg6,cfg7,cfg8,cfg9,cfg10,cfg11,cfg12,cfg13,cfg14,cfg15 + SEQ_QUE[%s] + no description available + 0x810 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + 8 + 0x10 + chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7 + PRD_CFG[%s] + no description available + 0xc00 + + prd_cfg + No description available + 0x0 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + prd_thshd_cfg + No description available + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + prd_result + No description available + 0x8 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + + 8 + 0x4 + chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7 + SAMPLE_CFG[%s] + no description available + 0x1000 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + conv_cfg1 + No description available + 0x1104 + 32 + 0x00000000 + 0x000001FF + + + CONVERT_CLOCK_NUMBER + convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider); +user can use small value to get faster conversion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. +Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC conversion(plus sample) need 25 cycles(50MHz). + 4 + 5 + read-write + + + CLOCK_DIVIDER + clock_period, N half clock cycle per half adc cycle +0 for same adc_clk and bus_clk, +1 for 1:2, +2 for 1:3, +... +15 for 1:16 +Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk + 0 + 4 + read-write + + + + + adc_cfg0 + No description available + 0x1108 + 32 + 0x00000000 + 0xA0000001 + + + SEL_SYNC_AHB + set to 1 will enable sync AHB bus, to get better bus performance. +Adc_clk must to be set to same as bus clock at this mode + 31 + 1 + read-write + + + ADC_AHB_EN + set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; + 29 + 1 + read-write + + + PORT3_REALTIME + set to enable trg queue stop other queues + 0 + 1 + read-write + + + + + int_sts + No description available + 0x1110 + 32 + 0x00000000 + 0xFFE0FFFF + + + TRIG_CMPT + interrupt for one trigger conversion complete if enabled + 31 + 1 + read-write + + + TRIG_SW_CFLCT + No description available + 30 + 1 + read-write + + + TRIG_HW_CFLCT + No description available + 29 + 1 + read-write + + + READ_CFLCT + read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel + 28 + 1 + read-write + + + SEQ_SW_CFLCT + sequence queue conflict interrupt, set if HW or SW trigger received during conversion + 27 + 1 + read-write + + + SEQ_HW_CFLCT + No description available + 26 + 1 + read-write + + + SEQ_DMAABT + dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set + 25 + 1 + read-write + + + SEQ_CMPT + the whole sequence complete interrupt + 24 + 1 + read-write + + + SEQ_CVC + one conversion complete in seq_queue if related seq_int_en is set + 23 + 1 + read-write + + + DMA_FIFO_FULL + DMA fifo full interrupt, user need to check clock frequency if it's set. + 22 + 1 + read-write + + + AHB_ERR + set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr + 21 + 1 + read-write + + + WDOG + set if one chanel watch dog event triggered + 0 + 16 + read-write + + + + + int_en + No description available + 0x1114 + 32 + 0x00000000 + 0xFFE0FFFF + + + TRIG_CMPT + interrupt for one trigger conversion complete if enabled + 31 + 1 + read-write + + + TRIG_SW_CFLCT + No description available + 30 + 1 + read-write + + + TRIG_HW_CFLCT + No description available + 29 + 1 + read-write + + + READ_CFLCT + read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel + 28 + 1 + read-write + + + SEQ_SW_CFLCT + sequence queue conflict interrupt, set if HW or SW trigger received during conversion + 27 + 1 + read-write + + + SEQ_HW_CFLCT + No description available + 26 + 1 + read-write + + + SEQ_DMAABT + dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set + 25 + 1 + read-write + + + SEQ_CMPT + the whole sequence complete interrupt + 24 + 1 + read-write + + + SEQ_CVC + one conversion complete in seq_queue if related seq_int_en is set + 23 + 1 + read-write + + + DMA_FIFO_FULL + DMA fifo full interrupt, user need to check clock frequency if it's set. + 22 + 1 + read-write + + + AHB_ERR + set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr + 21 + 1 + read-write + + + WDOG + set if one chanel watch dog event triggered + 0 + 16 + read-write + + + + + ana_ctrl0 + No description available + 0x1200 + 32 + 0x00000000 + 0x00001004 + + + ADC_CLK_ON + set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. +MUST set clock_period to 0 or 1 for adc16 reg access + 12 + 1 + read-write + + + STARTCAL + set to start the offset calibration cycle (Active H). user need to clear it after setting it. + 2 + 1 + read-write + + + + + ana_status + No description available + 0x1210 + 32 + 0x00000000 + 0x00000080 + + + CALON + Indicates if the ADC is in calibration mode (Active H). + 7 + 1 + read-write + + + + + 34 + 0x2 + adc16_para00,adc16_para01,adc16_para02,adc16_para03,adc16_para04,adc16_para05,adc16_para06,adc16_para07,adc16_para08,adc16_para09,adc16_para10,adc16_para11,adc16_para12,adc16_para13,adc16_para14,adc16_para15,adc16_para16,adc16_para17,adc16_para18,adc16_para19,adc16_para20,adc16_para21,adc16_para22,adc16_para23,adc16_para24,adc16_para25,adc16_para26,adc16_para27,adc16_para28,adc16_para29,adc16_para30,adc16_para31,adc16_para32,adc16_para33 + ADC16_PARAMS[%s] + no description available + 0x1400 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description available + 0 + 16 + read-write + + + + + adc16_config0 + No description available + 0x1444 + 32 + 0x00000000 + 0x03F07FFF + + + TEMPSNS_EN + set to enable temp sensor + 25 + 1 + read-write + + + REG_EN + set to enable regulator + 24 + 1 + read-write + + + BANDGAP_EN + set to enable bandgap. user should set reg_en and bandgap_en before use adc16. + 23 + 1 + read-write + + + CAL_AVG_CFG + for average the calibration result. +0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; +4- 16 loops; 5-32 loops; others reserved + 20 + 3 + read-write + + + PREEMPT_EN + set to enable preemption feature + 14 + 1 + read-write + + + CONV_PARAM + conversion parameter + 0 + 14 + read-write + + + + + adc16_config1 + No description available + 0x1460 + 32 + 0x00000000 + 0x00001F00 + + + COV_END_CNT + used for faster conversion, user can change it to get higher convert speed(but less accuracy). +should set to (21-convert_clock_number+1). + 8 + 5 + read-write + + + + + + + ACMP + ACMP + ACMP + 0xf0020000 + + 0x0 + 0x80 + registers + + + + 4 + 0x20 + chn0,chn1,chn2,chn3 + CHANNEL[%s] + no description available + 0x0 + + cfg + Configure Register + 0x0 + 32 + 0x00000000 + 0xFF7FFFFF + + + HYST + This bitfield configure the comparator hysteresis. +00: Hysteresis level 0 +01: Hysteresis level 1 +10: Hysteresis level 2 +11: Hysteresis level 3 + 30 + 2 + read-write + + + DACEN + This bit enable the comparator internal DAC +0: DAC disabled +1: DAC enabled + 29 + 1 + read-write + + + HPMODE + This bit enable the comparator high performance mode. +0: HP mode disabled +1: HP mode enabled + 28 + 1 + read-write + + + CMPEN + This bit enable the comparator. +0: ACMP disabled +1: ACMP enabled + 27 + 1 + read-write + + + MINSEL + PIN select, from pad_ai_acmp[7:1] and dac_out + 24 + 3 + read-write + + + PINSEL + MIN select, from pad_ai_acmp[7:1] and dac_out + 20 + 3 + read-write + + + CMPOEN + This bit enable the comparator output on pad. +0: ACMP output disabled +1: ACMP output enabled + 19 + 1 + read-write + + + FLTBYPS + This bit bypass the comparator output digital filter. +0: The ACMP output need pass digital filter +1: The ACMP output digital filter is bypassed. + 18 + 1 + read-write + + + WINEN + This bit enable the comparator window mode. +0: Window mode is disabled +1: Window mode is enabled + 17 + 1 + read-write + + + OPOL + The output polarity control bit. +0: The ACMP output remain un-changed. +1: The ACMP output is inverted. + 16 + 1 + read-write + + + FLTMODE + This bitfield define the ACMP output digital filter mode: +000-bypass +100-change immediately; +101-change after filter; +110-stalbe low; +111-stable high + 13 + 3 + read-write + + + SYNCEN + This bit enable the comparator output synchronization. +0: ACMP output not synchronized with ACMP clock. +1: ACMP output synchronized with ACMP clock. + 12 + 1 + read-write + + + FLTLEN + This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. + 0 + 12 + read-write + + + + + daccfg + DAC configure register + 0x4 + 32 + 0x00000000 + 0x000000FF + + + DACCFG + 8bit DAC digital value output to analog block + 0 + 8 + read-write + + + + + sr + Status register + 0x10 + 32 + 0x00000000 + 0x00000003 + + + FEDGF + Output falling edge flag. Write 1 to clear this flag. + 1 + 1 + read-write + + + REDGF + Output rising edge flag. Write 1 to clear this flag. + 0 + 1 + read-write + + + + + irqen + Interrupt request enable register + 0x14 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag interrupt enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag interrupt enable bit. + 0 + 1 + read-write + + + + + dmaen + DMA request enable register + 0x18 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag DMA request enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag DMA request enable bit. + 0 + 1 + read-write + + + + + + + + SPI0 + SPI0 + SPI + 0xf0030000 + + 0x10 + 0x70 + registers + + + + TransFmt + Transfer Format Register + 0x10 + 32 + 0x00020780 + 0xFFFF1F9F + + + ADDRLEN + Address length in bytes +0x0: 1 byte +0x1: 2 bytes +0x2: 3 bytes +0x3: 4 bytes + 16 + 2 + read-write + + + DATALEN + The length of each data unit in bits +The actual bit number of a data unit is (DataLen + 1) + 8 + 5 + read-write + + + DATAMERGE + Enable Data Merge mode, which does automatic data split on write and data coalescing on read. +This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. +When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed. + 7 + 1 + read-write + + + MOSIBIDIR + Bi-directional MOSI in regular (single) mode +0x0: MOSI is uni-directional signal in regular mode. +0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two + 4 + 1 + read-write + + + LSB + Transfer data with the least significant bit first +0x0: Most significant bit first +0x1: Least significant bit first + 3 + 1 + read-write + + + SLVMODE + SPI Master/Slave mode selection +0x0: Master mode +0x1: Slave mode + 2 + 1 + read-write + + + CPOL + SPI Clock Polarity +0x0: SCLK is LOW in the idle states +0x1: SCLK is HIGH in the idle states + 1 + 1 + read-write + + + CPHA + SPI Clock Phase +0x0: Sampling data at odd SCLK edges +0x1: Sampling data at even SCLK edges + 0 + 1 + read-write + + + + + TransCtrl + Transfer Control Register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + SLVDATAONLY + Data-only mode (slave mode only) +0x0: Disable the data-only mode +0x1: Enable the data-only mode +Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0. + 31 + 1 + read-write + + + CMDEN + SPI command phase enable (Master mode only) +0x0: Disable the command phase +0x1: Enable the command phase + 30 + 1 + read-write + + + ADDREN + SPI address phase enable (Master mode only) +0x0: Disable the address phase +0x1: Enable the address phase + 29 + 1 + read-write + + + ADDRFMT + SPI address phase format (Master mode only) +0x0: Address phase is the regular (single) mode +0x1: The format of the address phase is the same as the data phase (DualQuad). + 28 + 1 + read-write + + + TRANSMODE + Transfer mode +The transfer sequence could be +0x0: Write and read at the same time +0x1: Write only +0x2: Read only +0x3: Write, Read +0x4: Read, Write +0x5: Write, Dummy, Read +0x6: Read, Dummy, Write +0x7: None Data (must enable CmdEn or AddrEn in master mode) +0x8: Dummy, Write +0x9: Dummy, Read +0xa~0xf: Reserved + 24 + 4 + read-write + + + DUALQUAD + SPI data phase format +0x0: Regular (Single) mode +0x1: Dual I/O mode +0x2: Quad I/O mode +0x3: Reserved + 22 + 2 + read-write + + + TOKENEN + Token transfer enable (Master mode only) +Append a one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. +0x0: Disable the one-byte special token +0x1: Enable the one-byte special token + 21 + 1 + read-write + + + WRTRANCNT + Transfer count for write data +WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). +WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. +The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. +For TransMode 0, WrTranCnt must be equal to RdTranCnt. + 12 + 9 + read-write + + + TOKENVALUE + Token value (Master mode only) +The value of the one-byte special token following the address phase for SPI read transfers. +0x0: token value = 0x00 +0x1: token value = 0x69 + 11 + 1 + read-write + + + DUMMYCNT + Dummy data count. The actual dummy count is (DummyCnt +1). +The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) +The Data pins are put into the high impedance during the dummy data phase. +DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases. + 9 + 2 + read-write + + + RDTRANCNT + Transfer count for read data +RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). +RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. +The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. +For TransMode 0, WrTranCnt must equal RdTranCnt. + 0 + 9 + read-write + + + + + Cmd + Command Register + 0x24 + 32 + 0x00000000 + 0x000000FF + + + CMD + SPI Command + 0 + 8 + read-write + + + + + Addr + Address Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + SPI Address +(Master mode only) + 0 + 32 + read-write + + + + + Data + Data Register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + Data to transmit or the received data +For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. +For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. +The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. +If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset. + 0 + 32 + read-write + + + + + Ctrl + Control Register + 0x30 + 32 + 0x00000000 + 0x00FFFF1F + + + TXTHRES + Transmit (TX) FIFO Threshold +The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold. + 16 + 8 + read-write + + + RXTHRES + Receive (RX) FIFO Threshold +The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold. + 8 + 8 + read-write + + + TXDMAEN + TX DMA enable + 4 + 1 + read-write + + + RXDMAEN + RX DMA enable + 3 + 1 + read-write + + + TXFIFORST + Transmit FIFO reset +Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. + 2 + 1 + read-write + + + RXFIFORST + Receive FIFO reset +Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. + 1 + 1 + read-write + + + SPIRST + SPI reset +Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. + 0 + 1 + read-write + + + + + Status + Status Register + 0x34 + 32 + 0x00000000 + 0x33FFFF01 + + + TXNUM_7_6 + Number of valid entries in the Transmit FIFO + 28 + 2 + read-only + + + RXNUM_7_6 + Number of valid entries in the Receive FIFO + 24 + 2 + read-only + + + TXFULL + Transmit FIFO Full flag + 23 + 1 + read-only + + + TXEMPTY + Transmit FIFO Empty flag + 22 + 1 + read-only + + + TXNUM_5_0 + Number of valid entries in the Transmit FIFO + 16 + 6 + read-only + + + RXFULL + Receive FIFO Full flag + 15 + 1 + read-only + + + RXEMPTY + Receive FIFO Empty flag + 14 + 1 + read-only + + + RXNUM_5_0 + Number of valid entries in the Receive FIFO + 8 + 6 + read-only + + + SPIACTIVE + SPI register programming is in progress. +In master mode, SPIActive becomes 1 after the SPI command register is written and becomes 0 after the transfer is finished. +In slave mode, SPIActive becomes 1 after the SPI CS signal is asserted and becomes 0 after the SPI CS signal is deasserted. +Note that due to clock synchronization, it may take at most two spi_clock cycles for SPIActive to change when the corresponding condition happens. +Note this bit stays 0 when Direct IO Control or the memory-mapped interface is used. + 0 + 1 + read-only + + + + + IntrEn + Interrupt Enable Register + 0x38 + 32 + 0x00000000 + 0x0000003F + + + SLVCMDEN + Enable the Slave Command Interrupt. +Control whether interrupts are triggered whenever slave commands are received. +(Slave mode only) + 5 + 1 + read-write + + + ENDINTEN + Enable the End of SPI Transfer interrupt. +Control whether interrupts are triggered when SPI transfers end. +(In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.) + 4 + 1 + read-write + + + TXFIFOINTEN + Enable the SPI Transmit FIFO Threshold interrupt. +Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold. + 3 + 1 + read-write + + + RXFIFOINTEN + Enable the SPI Receive FIFO Threshold interrupt. +Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold. + 2 + 1 + read-write + + + TXFIFOURINTEN + Enable the SPI Transmit FIFO Underrun interrupt. +Control whether interrupts are triggered when the Transmit FIFO run out of data. +(Slave mode only) + 1 + 1 + read-write + + + RXFIFOORINTEN + Enable the SPI Receive FIFO Overrun interrupt. +Control whether interrupts are triggered when the Receive FIFO overflows. +(Slave mode only) + 0 + 1 + read-write + + + + + IntrSt + Interrupt Status Register + 0x3c + 32 + 0x00000000 + 0x0000003F + + + SLVCMDINT + Slave Command Interrupt. +This bit is set when Slave Command interrupts occur. +(Slave mode only) + 5 + 1 + write-only + + + ENDINT + End of SPI Transfer interrupt. +This bit is set when End of SPI Transfer interrupts occur. + 4 + 1 + write-only + + + TXFIFOINT + TX FIFO Threshold interrupt. +This bit is set when TX FIFO Threshold interrupts occur. + 3 + 1 + write-only + + + RXFIFOINT + RX FIFO Threshold interrupt. +This bit is set when RX FIFO Threshold interrupts occur. + 2 + 1 + write-only + + + TXFIFOURINT + TX FIFO Underrun interrupt. +This bit is set when TX FIFO Underrun interrupts occur. +(Slave mode only) + 1 + 1 + write-only + + + RXFIFOORINT + RX FIFO Overrun interrupt. +This bit is set when RX FIFO Overrun interrupts occur. +(Slave mode only) + 0 + 1 + write-only + + + + + Timing + Interface Timing Register + 0x40 + 32 + 0x00000000 + 0x00003FFF + + + CS2SCLK + The minimum time between the edges of SPI CS and the edges of SCLK. +SCLK_period * (CS2SCLK + 1) / 2 + 12 + 2 + read-write + + + CSHT + The minimum time that SPI CS should stay HIGH. +SCLK_period * (CSHT + 1) / 2 + 8 + 4 + read-write + + + SCLK_DIV + The clock frequency ratio between the clock source and SPI interface SCLK. +SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) +The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency. + 0 + 8 + read-write + + + + + SlvSt + Slave Status Register + 0x60 + 32 + 0x00000000 + 0x0007FFFF + + + UNDERRUN + Data underrun occurs in the last transaction + 18 + 1 + write-only + + + OVERRUN + Data overrun occurs in the last transaction + 17 + 1 + read-write + + + READY + Set this bit to indicate that the ATCSPI200 is ready for data transaction. +When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0. + 16 + 1 + read-write + + + USR_STATUS + User defined status flags + 0 + 16 + read-write + + + + + SlvDataCnt + Slave Data Count Register + 0x64 + 32 + 0x00000000 + 0x03FF03FF + + + WCNT + Slave transmitted data count + 16 + 10 + read-only + + + RCNT + Slave received data count + 0 + 10 + read-only + + + + + Config + Configuration Register + 0x7c + 32 + 0x00004311 + 0x000043FF + + + SLAVE + Support for SPI Slave mode + 14 + 1 + read-only + + + QUADSPI + Support for Quad I/O SPI + 9 + 1 + read-only + + + DUALSPI + Support for Dual I/O SPI + 8 + 1 + read-only + + + TXFIFOSIZE + Depth of TX FIFO +0x0: 2 words +0x1: 4 words +0x2: 8 words +0x3: 16 words +0x4: 32 words +0x5: 64 words +0x6: 128 words + 4 + 4 + read-only + + + RXFIFOSIZE + Depth of RX FIFO +0x0: 2 words +0x1: 4 words +0x2: 8 words +0x3: 16 words +0x4: 32 words +0x5: 64 words +0x6: 128 words + 0 + 4 + read-only + + + + + + + SPI1 + SPI1 + SPI + 0xf0034000 + + + SPI2 + SPI2 + SPI + 0xf0038000 + + + SPI3 + SPI3 + SPI + 0xf003c000 + + + UART0 + UART0 + UART + 0xf0040000 + + 0x10 + 0x30 + registers + + + + Cfg + Configuration Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + FIFOSIZE + The depth of RXFIFO and TXFIFO +0: 16-byte FIFO +1: 32-byte FIFO +2: 64-byte FIFO +3: 128-byte FIFO + 0 + 2 + read-only + + + + + OSCR + Over Sample Control Register + 0x14 + 32 + 0x00000010 + 0x0000001F + + + OSC + Over-sample control +The value must be an even number; any odd value +writes to this field will be converted to an even value. +OSC=0: reserved +OSC<=8: The over-sample ratio is 8 +8 < OSC< 32: The over sample ratio is OSC + 0 + 5 + read-write + + + + + RBR + Receiver Buffer Register (when DLAB = 0) + UNION_20 + 0x20 + 32 + 0x00000000 + 0x000000FF + + + RBR + Receive data read port + 0 + 8 + read-only + + + + + THR + Transmitter Holding Register (when DLAB = 0) + UNION_20 + 0x20 + 32 + 0x00000000 + 0x000000FF + + + THR + Transmit data write port + 0 + 8 + write-only + + + + + DLL + Divisor Latch LSB (when DLAB = 1) + UNION_20 + 0x20 + 32 + 0x00000001 + 0x000000FF + + + DLL + Least significant byte of the Divisor Latch + 0 + 8 + read-write + + + + + IER + Interrupt Enable Register (when DLAB = 0) + UNION_24 + 0x24 + 32 + 0x00000000 + 0x0000000F + + + EMSI + Enable modem status interrupt +The interrupt asserts when the status of one of the +following occurs: +The status of modem_rin, modem_dcdn, +modem_dsrn or modem_ctsn (If the auto-cts mode is +disabled) has been changed. +If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), +modem_ctsn would be used to control the transmitter. + 3 + 1 + read-write + + + ELSI + Enable receiver line status interrupt + 2 + 1 + read-write + + + ETHEI + Enable transmitter holding register interrupt + 1 + 1 + read-write + + + ERBI + Enable received data available interrupt and the +character timeout interrupt +0: Disable +1: Enable + 0 + 1 + read-write + + + + + DLM + Divisor Latch MSB (when DLAB = 1) + UNION_24 + 0x24 + 32 + 0x00000000 + 0x000000FF + + + DLM + Most significant byte of the Divisor Latch + 0 + 8 + read-write + + + + + IIR + Interrupt Identification Register + UNION_28 + 0x28 + 32 + 0x00000001 + 0x000000CF + + + FIFOED + FIFOs enabled +These two bits are 1 when bit 0 of the FIFO Control +Register (FIFOE) is set to 1. + 6 + 2 + read-only + + + INTRID + Interrupt ID, see IIR2 for detail decoding + 0 + 4 + read-only + + + + + FCR + FIFO Control Register + UNION_28 + 0x28 + 32 + 0x00000000 + 0x000000FF + + + RFIFOT + Receiver FIFO trigger level + 6 + 2 + write-only + + + TFIFOT + Transmitter FIFO trigger level + 4 + 2 + write-only + + + DMAE + DMA enable +0: Disable +1: Enable + 3 + 1 + write-only + + + TFIFORST + Transmitter FIFO reset +Write 1 to clear all bytes in the TXFIFO and resets its +counter. The Transmitter Shift Register is not cleared. +This bit will automatically be cleared. + 2 + 1 + write-only + + + RFIFORST + Receiver FIFO reset +Write 1 to clear all bytes in the RXFIFO and resets its +counter. The Receiver Shift Register is not cleared. +This bit will automatically be cleared. + 1 + 1 + write-only + + + FIFOE + FIFO enable +Write 1 to enable both the transmitter and receiver +FIFOs. +The FIFOs are reset when the value of this bit toggles. + 0 + 1 + write-only + + + + + LCR + Line Control Register + 0x2c + 32 + 0x00000000 + 0x000000FF + + + DLAB + Divisor latch access bit + 7 + 1 + read-write + + + BC + Break control + 6 + 1 + read-write + + + SPS + Stick parity +1: Parity bit is constant 0 or 1, depending on bit4 (EPS). +0: Disable the sticky bit parity. + 5 + 1 + read-write + + + EPS + Even parity select +1: Even parity (an even number of logic-1 is in the data +and parity bits) +0: Old parity. + 4 + 1 + read-write + + + PEN + Parity enable +When this bit is set, a parity bit is generated in +transmitted data before the first STOP bit and the parity +bit would be checked for the received data. + 3 + 1 + read-write + + + STB + Number of STOP bits +0: 1 bits +1: The number of STOP bit is based on the WLS setting +When WLS = 0, STOP bit is 1.5 bits +When WLS = 1, 2, 3, STOP bit is 2 bits + 2 + 1 + read-write + + + WLS + Word length setting +0: 5 bits +1: 6 bits +2: 7 bits +3: 8 bits + 0 + 2 + read-write + + + + + MCR + Modem Control Register ( + 0x30 + 32 + 0x00000000 + 0x00000032 + + + AFE + Auto flow control enable +0: Disable +1: The auto-CTS and auto-RTS setting is based on the +RTS bit setting: +When RTS = 0, auto-CTS only +When RTS = 1, auto-CTS and auto-RTS + 5 + 1 + read-write + + + LOOP + Enable loopback mode +0: Disable +1: Enable + 4 + 1 + read-write + + + RTS + Request to send +This bit controls the modem_rtsn output. +0: The modem_rtsn output signal will be driven HIGH +1: The modem_rtsn output signal will be driven LOW + 1 + 1 + read-write + + + + + LSR + Line Status Register + 0x34 + 32 + 0x00000000 + 0x000000FF + + + ERRF + Error in RXFIFO +In the FIFO mode, this bit is set when there is at least +one parity error, framing error, or line break +associated with data in the RXFIFO. It is cleared when +this register is read and there is no more error for the +rest of data in the RXFIFO. + 7 + 1 + read-only + + + TEMT + Transmitter empty +This bit is 1 when the THR (TXFIFO in the FIFO +mode) and the Transmitter Shift Register (TSR) are +both empty. Otherwise, it is zero. + 6 + 1 + read-only + + + THRE + Transmitter Holding Register empty +This bit is 1 when the THR (TXFIFO in the FIFO +mode) is empty. Otherwise, it is zero. +If the THRE interrupt is enabled, an interrupt is +triggered when THRE becomes 1. + 5 + 1 + read-only + + + LBREAK + Line break +This bit is set when the uart_sin input signal was held +LOWfor longer than the time for a full-word +transmission. A full-word transmission is the +transmission of the START, data, parity, and STOP +bits. It is cleared when this register is read. +In the FIFO mode, this bit indicates the line break for +the received data at the top of the RXFIFO. + 4 + 1 + read-only + + + FE + Framing error +This bit is set when the received STOP bit is not +HIGH. It is cleared when this register is read. +In the FIFO mode, this bit indicates the framing error +for the received data at the top of the RXFIFO. + 3 + 1 + read-only + + + PE + Parity error +This bit is set when the received parity does not match +with the parity selected in the LCR[5:4]. It is cleared +when this register is read. +In the FIFO mode, this bit indicates the parity error +for the received data at the top of the RXFIFO. + 2 + 1 + read-only + + + OE + Overrun error +This bit indicates that data in the Receiver Buffer +Register (RBR) is overrun. + 1 + 1 + read-only + + + DR + Data ready. +This bit is set when there are incoming received data +in the Receiver Buffer Register (RBR). It is cleared +when all of the received data are read. + 0 + 1 + read-only + + + + + MSR + Modem Status Register + 0x38 + 32 + 0x00000000 + 0x00000011 + + + CTS + Clear to send +0: The modem_ctsn input signal is HIGH. +1: The modem_ctsn input signal is LOW. + 4 + 1 + read-only + + + DCTS + Delta clear to send +This bit is set when the state of the modem_ctsn input +signal has been changed since the last time this +register is read. + 0 + 1 + read-only + + + + + GPR + GPR Register + 0x3c + 32 + 0x00000000 + 0x000000FF + + + DATA + A one-byte storage register + 0 + 8 + read-write + + + + + + + UART1 + UART1 + UART + 0xf0044000 + + + UART2 + UART2 + UART + 0xf0048000 + + + UART3 + UART3 + UART + 0xf004c000 + + + UART4 + UART4 + UART + 0xf0050000 + + + UART5 + UART5 + UART + 0xf0054000 + + + UART6 + UART6 + UART + 0xf0058000 + + + UART7 + UART7 + UART + 0xf005c000 + + + UART8 + UART8 + UART + 0xf0060000 + + + UART9 + UART9 + UART + 0xf0064000 + + + UART10 + UART10 + UART + 0xf0068000 + + + UART11 + UART11 + UART + 0xf006c000 + + + UART12 + UART12 + UART + 0xf0070000 + + + UART13 + UART13 + UART + 0xf0074000 + + + UART14 + UART14 + UART + 0xf0078000 + + + UART15 + UART15 + UART + 0xf007c000 + + + PUART + PUART + UART + 0xf40e4000 + + + CAN0 + CAN0 + CAN + 0xf0080000 + + 0x0 + 0xca + registers + + + + 20 + 0x4 + buf0,buf1,buf2,buf3,buf4,buf5,buf6,buf7,buf8,buf9,buf10,buf11,buf12,buf13,buf14,buf15,buf16,buf17,buf18,buf19 + RBUF[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + 18 + 0x4 + buf0,buf1,buf2,buf3,buf4,buf5,buf6,buf7,buf8,buf9,buf10,buf11,buf12,buf13,buf14,buf15,buf16,buf17 + TBUF[%s] + no description available + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + 2 + 0x4 + wrd0,wrd1 + TTS[%s] + no description available + 0x98 + 32 + 0x00000000 + 0xFFFFFFFF + + + TTS_WRD0 + transmission time stamp, word 0, LSB 32bit + 0 + 32 + read-only + + + + + CMD_STA_CMD_CTRL + config, status, command and control bits + 0xa0 + 32 + 0x00900080 + 0xFBF3FFFF + + + SACK + Self-ACKnowledge +0 – no self-ACK +1 – self-ACK when LBME=1 + 31 + 1 + read-write + + + ROM + Receive buffer Overflow Mode +In case of a full RBUF when a new message is received, then ROM selects the following: +1 – The new message will not be stored. +0 – The oldest message will be overwritten. + 30 + 1 + read-write + + + ROV + Receive buffer OVerflow +1 – Overflow. At least one message is lost. +0 – No Overflow. +ROV is cleared by setting RREL=1. + 29 + 1 + read-only + + + RREL + Receive buffer RELease +The host controller has read the actual RB slot and releases it. Afterwards the CAN-CTRL +core points to the next RB slot. RSTAT gets updated. +1 – Release: The host has read the RB. +0 – No release + 28 + 1 + read-write + + + RBALL + Receive Buffer stores ALL data frames +0 – normal operation +1 – RB stores correct data frames as well as data frames with error + 27 + 1 + read-write + + + RSTAT + Receive buffer STATus +00 - empty +01 - > empty and < almost full (AFWL) +10 -  almost full (programmable threshold by AFWL) but not full and no overflow +11 - full (stays set in case of overflow – for overflow signaling see ROV) + 24 + 2 + read-only + + + FD_ISO + CAN FD ISO mode +0 - Bosch CAN FD (non-ISO) mode +1 - ISO CAN FD mode (ISO 11898-1:2015) +ISO CAN FD mode has a different CRC initialization value and an additional stuff bit count. +Both modes are incompatible and must not be mixed in one CAN network. +This bit has no impact to CAN 2.0B. +This bit is only writeable if RESET=1. + 23 + 1 + read-write + + + TSNEXT + Transmit buffer Secondary NEXT +0 - no action +1 - STB slot filled, select next slot. +After all frame bytes are written to the TBUF registers, the host controller has to set +TSNEXT to signal that this slot has been filled. Then the CAN-CTRL core connects the TBUF +registers to the next slot. Once a slot is marked as filled a transmission can be started +using TSONE or TSALL. +It is possible to set TSNEXT and TSONE or TSALL together in one write access. +TSNEXT has to be set by the host controller and is automatically reset by the CAN-CTRL +core immediately after it was set. +Setting TSNEXT is meaningless if TBSEL=0. In this case TSNEXT is ignored and +automatically cleared. It does not do any harm. +If all slots of the STB are filled, TSNEXT stays set until a slot becomes free. +TSNEXT has no meaning in TTCAN mode and is fixed to 0. + 22 + 1 + read-write + + + TSMODE + Transmit buffer Secondary operation MODE +0 - FIFO mode +1 - priority decision mode +In FIFO mode frames are transmitted in the order in that they are written into the STB. +In priority decision mode the frame with the highest priority in the STB is automatically +transmitted first. The ID of a frame is used for the priority decision. A lower ID means a +higher priority of a frame. A frame in the PTB has always the highest priority regardless of +the ID. +TSMODE shall be switched only if the STB if empty + 21 + 1 + read-write + + + TTTBM + TTCAN Transmit Buffer Mode +If TTEN=0 then TTTBM is ignored, otherwise the following is valid: +0 - separate PTB and STB, behavior defined by TSMODE +1 - full TTCAN support: buffer slots selectable by TBPTR and TTPTR +For event-driven CAN communication (TTEN=0), the system provides PTB and STB and +the behavior of the STB is defined by TSMODE. Then TTTBM is ignored. +For time-triggered CAN communication (TTEN=1) with full support of all features including +time-triggered transmissions, TTTBM=1 needs to be chosen. Then the all TB slots are +addressable using TTPTR and TBPTR. +For time-triggered CAN communication (TTEN=1) with only support of reception timestamps, TTTBM=0 can be chosen. Then the transmit buffer acts as in event-driven mode +and the behavior can be selected by TSMODE. +TTTBM shall be switched only if the TBUF is empty. + 20 + 1 + read-write + + + TSSTAT + Transmission Secondary STATus bits +If TTEN=0 or TTTBM=0: +00 – STB is empty +01 – STB is less than or equal to half full +10 – STB is more than half full +11 – STB is full +If the STB is disabled using STB_DISABLE, then TSSTAT=00. +If TTEN=1 and TTTBM=1: +00 – PTB and STB are empty +01 – PTB and STB are not empty and not full +11 – PTB and STB are full + 16 + 2 + read-only + + + TBSEL + Transmit Buffer Select +Selects the transmit buffer to be loaded with a message. Use the TBUF registers for +access. TBSEL needs to be stable all the time the TBUF registers are written and when +TSNEXT is set. +0 - PTB (high-priority buffer) +1 - STB +The bit will be reset to the hardware reset value if (TTEN=1 and TTTBM=1) + 15 + 1 + read-write + + + LOM + Listen Only Mode +0 - Disabled +1 - Enabled +LOM cannot be set if TPE, TSONE or TSALL is set. No transmission can be started if LOM +is enabled and LBME is disabled. +LOM=1 and LBME=0 disables all transmissions. +LOM=1 and LBME=1 disables the ACK for received frames and error frames, but enables +the transmission of own frames. + 14 + 1 + read-write + + + STBY + Transceiver Standby Mode +0 - Disabled +1 - Enabled +This register bit is connected to the output signal stby which can be used to control a +standby mode of a transceiver. +STBY cannot be set to 1 if TPE=1, TSONE=1 or TSALL=1. +If the host sets STBY to 0 then the host needs to wait for the time required by the +transceiver to start up before the host requests a new transmission. + 13 + 1 + read-write + + + TPE + Transmit Primary Enable +1 - Transmission enable for the message in the high-priority PTB +0 - No transmission for the PTB +If TPE is set, the message from the PTB will be transmitted at the next possible transmit +position. A started transmission from the STB will be completed before, but pending new +messages are delayed until the PTB message has been transmitted. +TPE stays set until the message has been transmitted successfully or it is aborted using +TPA. +The host controller can set TPE to 1 but can not reset it to 0. This would only be possible +using TPA and aborting the message. +The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and +LBME=0) or (TTEN=1 and TTTBM=1). + 12 + 1 + read-write + + + TPA + Transmit Primary Abort +1 – Aborts a transmission from PTB which has been requested by TPE=1 but not +started yet. (The data bytes of the message remains in the PTB.) +0 – no abort +The bit has to be set by the host controller and will be reset by CAN-CTRL. Setting TPA +automatically de-asserts TPE. +The host controller can set TPA to 1 but can not reset it to 0. +During the short time while the CAN-CTRL core resets the bit, it cannot be set by the +host. +The bit will be reset to the hardware reset value if RESET=1 or (TTEN=1 and TTTBM=1). +TPA should not be set simultaneously with TPE. + 11 + 1 + read-write + + + TSONE + Transmit Secondary ONE frame +1 – Transmission enable of one in the STB. In FIFO mode this is the oldest message +and in priority mode this is the one with the highest priority. +TSONE in priority mode is difficult to handle, because it is not always clear which +message will be transmitted if new messages are written to the STB meanwhile. +The controller starts the transmission as soon as the bus becomes vacant and +no request of the PTB (bit TPE) is pending. +0 – No transmission for the STB. +TSONE stays set until the message has been transmitted successfully or it is aborted +using TSA. +The host controller can set TSONE to 1 but can not reset it to 0. This would only be +possible using TSA and aborting the message. +The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and +LBME=0) or (TTEN=1 and TTTBM=1). + 10 + 1 + read-write + + + TSALL + Transmit Secondary ALL frames +1 – Transmission enable of all messages in the STB. +The controller starts the transmission as soon as the bus becomes vacant and +no request of the PTB (bit TPE) is pending. +0 – No transmission for the STB. +TSALL stays set until all messages have been transmitted successfully or they are aborted +using TSA. +The host controller can set TSALL to 1 but can not reset it to 0. This would only be +possible using TSA and aborting the messages. +The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and +LBME=0) or (TTEN=1 and TTTBM=1). +If during a transmission the STB is loaded with a new frame then the new frame will be +transmitted too. In other words: a transmission initiated by TSALL is finished when the +STB becomes empty. + 9 + 1 + read-write + + + TSA + Transmit Secondary Abort +1 – Aborts a transmission from STB which has been requested but not started yet. +For a TSONE transmission, only one frame is aborted while for a TSALL +Transmission, all frames are aborted. +One or all message slots will be released which updates TSSTAT. +All aborted messages are lost because they are not accessible any more. +If in priority mode a TSONE transmission is aborted, then it is not clear which +frame will be aborted if new frames are written to the STB meanwhile. +0 – no abort +The bit has to be set by the host controller and will be reset by CAN-CTRL. Setting TSA,automatically de-asserts TSONE or TSALL respectively. +The host controller can set TSA to 1 but can not reset it to 0. +The bit will be reset to the hardware reset value if RESET=1. +TSA should not be set simultaneously with TSONE or TSALL. + 8 + 1 + read-write + + + RESET + RESET request bit +1 - The host controller performs a local reset of CAN-CTRL. +0 - no local reset of CAN-CTRLThe some register (e.g for node configuration) can only be modified if RESET=1. +Bit RESET forces several components to a reset state. +RESET is automatically set if the node enters “bus off” state. +Note that a CAN node will participate in CAN communication after RESET is switched to 0after 11 CAN bit times. +This delay is required by the CAN standard (bus idle time).If RESET is set to 1 and immediately set to 0, then it takes some time until RESET can beread as 0 and becomes inactive. +The reason is clock domain crossing from host to CAN clockdomain. RESET is held active as long as needed depending on the relation between host andCAN clock. + 7 + 1 + read-write + + + LBME + Loop Back Mode, External +0 - Disabled +1 - EnabledLBME should not be enabled while a transmission is active + 6 + 1 + read-write + + + LBMI + Loop Back Mode, Internal +0 - Disabled1 - EnabledLBMI should not be enabled while a transmission is active. + 5 + 1 + read-write + + + TPSS + Transmission Primary Single Shot mode for PTB +0 - Disabled +1 - Enabled + 4 + 1 + read-write + + + TSSS + Transmission Secondary Single Shot mode for STB +0 - Disabled +1 - Enabled + 3 + 1 + read-write + + + RACTIVE + Reception ACTIVE (Receive Status bit) +1 - The controller is currently receiving a frame. +0 - No receive activity. + 2 + 1 + read-only + + + TACTIVE + Transmission ACTIVE (Transmit Status bit) +1 - The controller is currently transmitting a frame. +0 - No transmit activity. + 1 + 1 + read-only + + + BUSOFF + Bus Off (Bus Status bit) +1 - The controller status is “bus off”. +0 - The controller status is “bus on”. +Writing a 1 to BUSOFF will reset TECNT and RECNT. This should be done only for debugging. +See Chapter 3.9.10.6 for details. + 0 + 1 + read-write + + + + + RTIE + Receive and Transmit Interrupt Enable Register RTIE + 0xa4 + 8 + 0xFE + 0xFF + + + RIE + Receive Interrupt Enable +0 – Disabled, 1 – Enabled + 7 + 1 + read-write + + + ROIE + RB Overrun Interrupt Enable +0 – Disabled, 1 – Enabled + 6 + 1 + read-write + + + RFIE + RB Full Interrupt Enable +0 – Disabled, 1 – Enabled + 5 + 1 + read-write + + + RAFIE + RB Almost Full Interrupt Enable +0 – Disabled, 1 – Enabled + 4 + 1 + read-write + + + TPIE + Transmission Primary Interrupt Enable +0 – Disabled, 1 – Enabled + 3 + 1 + read-write + + + TSIE + Transmission Secondary Interrupt Enable +0 – Disabled, 1 – Enabled + 2 + 1 + read-write + + + EIE + Error Interrupt Enable +0 – Disabled, 1 – Enabled + 1 + 1 + read-write + + + TSFF + If TTEN=0 or TTTBM=0: Transmit Secondary buffer Full Flag +1 - The STB is filled with the maximal number of messages. +0 - The STB is not filled with the maximal number of messages. +If the STB is disabled using STB_DISABLE, then TSFF=0. +If TTEN=1 and TTTBM=1: Transmit buffer Slot Full Flag +1 - The buffer slot selected by TBPTR is filled. +0 - The buffer slot selected by TBPTR is empty. + 0 + 1 + read-only + + + + + RTIF + Receive and Transmit Interrupt Flag Register RTIF (0xa5) + 0xa5 + 8 + 0x00 + 0xFF + + + RIF + Receive Interrupt Flag +1 - Data or a remote frame has been received and is available in the receive buffer. +0 - No frame has been received. + 7 + 1 + write-only + + + ROIF + RB Overrun Interrupt Flag +1 - At least one received message has been overwritten in the RB. +0 - No RB overwritten. +In case of an overrun both ROIF and RFIF will be set. + 6 + 1 + write-only + + + RFIF + RB Full Interrupt Flag +1 - All RBs are full. If no RB will be released until the next valid message is received, +the oldest message will be lost. +0 - The RB FIFO is not full. + 5 + 1 + write-only + + + RAFIF + RB Almost Full Interrupt Flag +1 - number of filled RB slots >= AFWL_i +0 - number of filled RB slots < AFWL_i + 4 + 1 + write-only + + + TPIF + Transmission Primary Interrupt Flag +1 - The requested transmission of the PTB has been successfully completed. +0 - No transmission of the PTB has been completed. +In TTCAN mode, TPIF will never be set. Then only TSIF is valid. + 3 + 1 + write-only + + + TSIF + Transmission Secondary Interrupt Flag +1 - The requested transmission of the STB has been successfully completed. +0 - No transmission of the STB has been completed successfully. +In TTCAN mode TSIF will signal all successful transmissions, regardless of storage location of +the message. + 2 + 1 + write-only + + + EIF + Error Interrupt Flag +1 - The border of the error warning limit has been crossed in either direction, +or the BUSOFF bit has been changed in either direction. +0 - There has been no change. + 1 + 1 + write-only + + + AIF + Abort Interrupt Flag +1 - After setting TPA or TSA the appropriated message(s) have been aborted. +It is recommended to not set both TPA and TSA simultaneously because both +source AIF. +0 - No abort has been executed. +The AIF does not have an associated enable register. + 0 + 1 + write-only + + + + + ERRINT + ERRor INTerrupt Enable and Flag Register ERRINT + 0xa6 + 8 + 0x00 + 0xFF + + + EWARN + Error WARNing limit reached +1 - One of the error counters RECNT or TECNT is equal or bigger than EWL0 - The values in both counters are less than EWL. + 7 + 1 + read-only + + + EPASS + Error Passive mode active +0 - not active (node is error active) +1 - active (node is error passive) + 6 + 1 + read-only + + + EPIE + Error Passive Interrupt Enable + 5 + 1 + read-write + + + EPIF + Error Passive Interrupt Flag. EPIF will be activated if the error status changes from error +active to error passive or vice versa and if this interrupt is enabled. + 4 + 1 + write-only + + + ALIE + Arbitration Lost Interrupt Enable + 3 + 1 + read-write + + + ALIF + Arbitration Lost Interrupt Flag + 2 + 1 + write-only + + + BEIE + Bus Error Interrupt Enable + 1 + 1 + read-write + + + BEIF + Bus Error Interrupt Flag + 0 + 1 + write-only + + + + + LIMIT + Warning Limits Register LIMIT + 0xa7 + 8 + 0x1B + 0xFF + + + AFWL + receive buffer Almost Full Warning Limit +AFWL defines the internal warning limit AFWL_i with being the number of availableRB slots. +AFWL_i is compared to the number of filled RB slots and triggers RAFIF if equal. Thevalid range of . +AFWL = 0 is meaningless and automatically treated as 0x1. (Note that AFWL is meant in this rule and not AFWL_i.) +AFWL_i > nRB is meaningless and automatically treated as nRB. +AFWL_i = nRB is a valid value, but note that RFIF also exists. + 4 + 4 + read-write + + + EWL + Programmable Error Warning Limit = (EWL+1)*8. Possible Limit values: 8, 16, … 128. +The value of EWL controls EIF. + 0 + 4 + read-write + + + + + S_PRESC + Bit Timing Register(Slow Speed) + 0xa8 + 32 + 0x01020203 + 0xFF7F7FFF + + + S_PRESC + Prescaler (slow speed) +The prescaler divides the system clock to get the time quanta clock tq_clk.Valid range PRESC=[0x00, 0xff] results in divider values 1 to 256. + 24 + 8 + read-write + + + S_SJW + Synchronization Jump Width (slow speed) +The Synchronization Jump Width is the maximum time forshortening or lengthening the Bit Time for resynchronization, where TQ is a timequanta. + 16 + 7 + read-write + + + S_SEG_2 + Bit Timing Segment 2 (slow speed) +Time after the sample point. + 8 + 7 + read-write + + + S_SEG_1 + Bit Timing Segment 1 (slow speed) +The sample point will be set to after start of bit time. + 0 + 8 + read-write + + + + + F_PRESC + Bit Timing Register(Fast Speed) + 0xac + 32 + 0x01020203 + 0xFF0F0F0F + + + F_PRESC + Prescaler (fast speed) +The prescaler divides the system clock to get the time quanta clock tq_clk.Valid range PRESC=[0x00, 0xff] results in divider values 1 to 256. + 24 + 8 + read-write + + + F_SJW + Synchronization Jump Width (fast speed) +The Synchronization Jump Width is the maximum time forshortening or lengthening the Bit Time for resynchronization, where TQ is a timequanta. + 16 + 4 + read-write + + + F_SEG_2 + Bit Timing Segment 2 (fast speed) +Time after the sample point + 8 + 4 + read-write + + + F_SEG_1 + Bit Timing Segment 1 (fast speed) +The sample point will be set to after start of bit time. + 0 + 4 + read-write + + + + + EALCAP + Error and Arbitration Lost Capture Register EALCAP + 0xb0 + 8 + 0x00 + 0xFF + + + KOER + Kind Of ERror (Error code) +000 - no error +001 - BIT ERROR +010 - FORM ERROR +011 - STUFF ERROR +100 - ACKNOWLEDGEMENT ERROR +101 - CRC ERROR +110 - OTHER ERROR(dominant bits after own error flag, received active Error Flag too long,dominant bit during Passive-Error-Flag after ACK error) +111 - not used +KOER is updated with each new error. Therefore it stays untouched when frames aresuccessfully transmitted or received. + 5 + 3 + read-only + + + ALC + Arbitration Lost Capture (bit position in the frame where the arbitration has been lost) + 0 + 5 + read-only + + + + + TDC + Transmitter Delay Compensation Register TDC + 0xb1 + 8 + 0x00 + 0xFF + + + TDCEN + Transmitter Delay Compensation ENable +TDC will be activated during the data phase of a CAN FD frame if BRS is active if TDCEN=1. + 7 + 1 + read-write + + + SSPOFF + Secondary Sample Point OFFset +The transmitter delay plus SSPOFF defines the time of the secondary sample point for TDC. +SSPOFF is given as a number of TQ. + 0 + 7 + read-write + + + + + RECNT + Error Counter Registers RECNT + 0xb2 + 8 + 0x00 + 0xFF + + + RECNT + Receive Error CouNT (number of errors during reception) +RECNT is incremented and decremented as defined in the CAN specification. +RECNT does not overflow. +If TXB=1, then the error counters are frozen. + 0 + 8 + read-only + + + + + TECNT + Error Counter Registers TECNT + 0xb3 + 8 + 0x00 + 0xFF + + + TECNT + Transmit Error CouNT (number of errors during transmission) +TECNT is incremented and decremented as defined in the CAN specification. +In case of the “bus off state” TECNT may overflow. +If TXB=1, then the error counters are frozen. + 0 + 8 + read-only + + + + + ACFCTRL + Acceptance Filter Control Register ACFCTRL + 0xb4 + 8 + 0x00 + 0x2F + + + SELMASK + SELect acceptance MASK +0 - Registers ACF_x point to acceptance code +1 - Registers ACF_x point to acceptance mask. +ACFADR selects one specific acceptance filter. + 5 + 1 + read-write + + + ACFADR + acceptance filter address +ACFADR points to a specific acceptance filter. +The selected filter is accessible using theregisters ACF_x. +Bit SELMASK selects between acceptance code and mask for theselected acceptance filter. +A value of ACFADR>ACF_NUMBER-1 is meaningless and automatically treated as value ACF_NUMBER-1. +ACF_NUMBER = 16. + 0 + 4 + read-write + + + + + TIMECFG + CiA 603 Time-Stamping TIMECFG + 0xb5 + 8 + 0x00 + 0x03 + + + TIMEPOS + TIME-stamping POSition +0 – SOF1 – EOF (see Chapter 7)TIMEPOS can only be changed if TIMEEN=0, but it is possible to modify TIMPOS withthe same write access that sets TIMEEN=1. + 1 + 1 + read-write + + + TIMEEN + TIME-stamping ENable +0 – disabled +1 – enabled + 0 + 1 + read-write + + + + + ACF_EN + Acceptance Filter Enable ACF_EN + 0xb6 + 16 + 0x0000 + 0xFFFF + + + ACF_EN + Acceptance filter Enable +1 - acceptance filter enabled +0 - acceptance filter disable +Each acceptance filter (AMASK / ACODE) can be individually enabled or disabled. +Disabled filters reject a message. Only enabled filters can accept a message if the +appropriate AMASK / ACODE configuration matches. + 0 + 16 + read-write + + + + + ACF + Acceptance CODE ACODE or ACMASK + 0xb8 + 32 + 0x00000000 + 0x7FFFFFFF + + + AIDEE + Acceptance mask IDE bit check enable +1 - acceptance filter accepts either standard or extended as defined by AIDE +0 - acceptance filter accepts both standard or extended frames +Only filter 0 is affected by the power-on reset. All other filters stay uninitialized. + 30 + 1 + read-write + + + AIDE + Acceptance mask IDE bit value +If AIDEE=1 then: +1 - acceptance filter accepts only extended frames +0 - acceptance filter accepts only standard frames +Only filter 0 is affected by the power-on reset. All other filters stay uninitialized. + 29 + 1 + read-write + + + CODE_MASK + Acceptance CODE +1 - ACC bit value to compare with ID bit of the received message +0 - ACC bit value to compare with ID bit of the received message +ACODE_x(10:0) will be used for extended frames. +ACODE_x(28:0) will be used for extended frames. +Only filter 0 is affected by the power-on reset. +Acceptance MASK(if SELMASK ==1 ) +1 - acceptance check for these bits of receive identifier disabled +0 - acceptance check for these bits of receive identifier enable +AMASK_x(10:0) will be used for extended frames. +AMASK_x(28:0) will be used for extended frames. +Disabled bits result in accepting the message. Therefore the default configuration after +reset for filter 0 accepts all messages. +Only filter 0 is affected by the power-on reset. + 0 + 29 + read-write + + + + + VER + Version Information VER + 0xbc + 16 + 0x0000 + 0xFFFF + + + VERSION + Version of CAN-CTRL, given as decimal value. VER_1 holds the major version and +VER_0 the minor version.Example: version 5x16N00S00 is represented by VER_1=5 and VER_0=16 + 0 + 16 + read-write + + + + + TBSLOT + TTCAN: TB Slot Pointer TBSLOT + 0xbe + 8 + 0x00 + 0xFF + + + TBE + set TB slot to “Empty” +1 - slot selected by TBPTR shall be marked as “empty” +0 - no actionTBE is automatically reset to 0 as soon as the slot is marked as empty and TSFF=0. +If atransmission from this slot is active, then TBE stays set as long as either the transmission completes or after a transmission error or arbitration loss the + transmissionis not active any more. +If both TBF and TBE are set, then TBE wins + 7 + 1 + read-write + + + TBF + set TB slot to “Filled” +1 - slot selected by TBPTR shall be marked as “filled” +0 - no actionTBF is automatically reset to 0 as soon as the slot is marked as filled and TSFF=1. +If both TBF and TBE are set, then TBE wins. + 6 + 1 + read-write + + + TBPTR + Pointer to a TB message slot. +0x00 - Pointer to the PTB +others - Pointer to a slot in the STB +The message slot pointed to by TBPTR is readable / writable using the TBUF registers. +Write access is only possible if TSFF=0. +Setting TBF to 1 marks the selected slot asfilled and setting TBE to 1 marks the selected slot as empty. +TBSEL and TSNEXT are unused in TTCAN mode and have no meaning. +TBPTR can only point to buffer slots, that exist in the hardware. +Unusable bits ofTBPTR are fixed to 0. +TBPTR is limited to the PTB and 63 STB slots. + More slots cannot be used in TTCANmode.If TBPTR is too big and points to a slot that is not available, then TBF and TBE arereset automatically and no action takes place. + 0 + 6 + read-write + + + + + TTCFG + TTCAN: Time Trigger Configuration TTCFG + 0xbf + 8 + 0x00 + 0xFF + + + WTIE + Watch Trigger Interrupt Enable + 7 + 1 + read-write + + + WTIF + Watch Trigger Interrupt Flag +WTIF will be set if the cycle count reaches the limited defined by TT_WTRIG and WTIE is set. + 6 + 1 + read-write + + + TEIF + Trigger Error Interrupt Flag +The conditions when TEIF will be set, are defined in Chapter 6.4. There is no bit toenable or disable the handling of TEIF + 5 + 1 + read-write + + + TTIE + Time Trigger Interrupt Enable +If TTIE is set, then TTIF will be set if the cycle time is equal to the trigger timeTT_TRIG. + 4 + 1 + read-write + + + TTIF + Time Trigger Interrupt Flag +TTIF will be set if TTIE is set and the cycle time is equal to the trigger time TT_TRIG. +Writing a one to TTIF resets it. Writing a zero has no impact.TTIF will be set only once. +If TT_TRIG gets not updated, then TTIF will be not setagain in the next basic cycle. + 3 + 1 + read-write + + + T_PRESC + TTCAN Timer PRESCaler +00b - 1 +01b - 2 +10b - 4 +11b - 8 +The TTCAN time base is a CAN bittime defined by S_PRES, S_SEG_1 and S_SEG_2.With T_PRESC an additional prescaling factor of 1, 2, 4 or 8 is defined. +T_PRESC can only be modified if TTEN=0, but it is possible to modify T_PRESC and setTTEN simultaneously with one write access. + 1 + 2 + read-write + + + TTEN + Time Trigger Enable +1 - TTCAN enabled, timer is running0 - disabled + 0 + 1 + read-write + + + + + REF_MSG + TTCAN: Reference Message REF_MSG + 0xc0 + 32 + 0x00000000 + 0x9FFFFFFF + + + REF_IDE + REFerence message IDE bit. + 31 + 1 + read-write + + + REF_MSG + REFerence message IDentifier. +If REF_IDE is +1 - REF_ID(28:0) is valid (extended ID) +0 - REF_ID(10:0) is valid (standard ID) +REF_ID is used in TTCAN mode to detect a reference message. This holds for time +slaves (reception) as well as for the time master (transmission). If the reference +message is detected and there are no errors, then the Sync_Mark of this frame will +become the Ref_Mark. +REF_ID(2:0) is not tested and therefore the appropriate register bits are forced to 0. +These bits are used for up to 8 potential time masters. +CAN-CTRL recognizes the reference message only by ID. The payload is not tested. +Additional note: A time master will transmit a reference message in the same way as a +normal frame. REF_ID is intended for detection of a successful transmission of a +reference message. + 0 + 29 + read-write + + + + + TRIG_CFG + TTCAN: Trigger Configuration TRIG_CFG + 0xc4 + 16 + 0x0000 + 0xF73F + + + TEW + Transmit Enable Window +For a single shot transmit trigger there is a time of up to 16 ticks of the cycle time +where the frame is allowed to start. TWE+1 defines the number of ticks. +TEW=0 is a valid setting and shortens the transmit enable window to 1 tick + 12 + 4 + read-write + + + TTYPE + Trigger Type +000b - Immediate Trigger for immediate transmission +001b - Time Trigger for receive triggers +010b - Single Shot Transmit Trigger for exclusive time windows +011b - Transmit Start Trigger for merged arbitrating time windows +100b - Transmit Stop Trigger for merged arbitrating time windows +others - no action +The time of the trigger is defined by TT_TRIG. TTPTR selects the TB slot for the +transmit triggers. See Chapter 6.4 for more details. + 8 + 3 + read-write + + + TTPTR + Transmit Trigger TB slot Pointer +If TTPTR is too big and points to a slot that is not available, then TEIF is set and no +new trigger can be activated after a write access to TT_TRIG_1. +If TTPTR points to an empty slot, then TEIF will be set at the moment, when the +trigger time is reached. + 0 + 6 + read-write + + + + + TT_TRIG + TTCAN: Trigger Time TT_TRIG + 0xc6 + 16 + 0x0000 + 0xFFFF + + + TT_TRIG + Trigger Time +TT_TRIG(15:0) defines the cycle time for a trigger. +For a transmission trigger theearliest point of transmission of the SOF of the appropriate frame will be TT_TRIG+1. + 0 + 16 + read-write + + + + + TT_WTRIG + TTCAN: Watch Trigger Time TT_WTRIG + 0xc8 + 16 + 0x0000 + 0xFFFF + + + TT_WTRIG + Watch Trigger Time +TT_WTRIG(15:0) defines the cycle time for a watch trigger. The initial watch trigger isthe maximum cycle time 0xffff. + 0 + 16 + read-write + + + + + + + CAN1 + CAN1 + CAN + 0xf0084000 + + + CAN2 + CAN2 + CAN + 0xf0088000 + + + CAN3 + CAN3 + CAN + 0xf008c000 + + + WDG0 + WDG0 + WDOG + 0xf0090000 + + 0x10 + 0x10 + registers + + + + CTRL + Control Register + 0x10 + 32 + 0x00000000 + 0x000007FF + + + RSTTIME + The time interval of the reset stage: +0: Clock period x 2^7 +1: Clock period x 2^8 +2: Clock period x 2^9 +3: Clock period x 2^10 +4: Clock period x 2^11 +5: Clock period x 2^12 +6: Clock period x 2^13 +7: Clock period x 2^14 + 8 + 3 + read-write + + + INTTIME + The timer interval of the interrupt stage: +0: Clock period x 2^6 +1: Clock period x 2^8 +2: Clock period x 2^10 +3: Clock period x 2^11 +4: Clock period x 2^12 +5: Clock period x 2^13 +6: Clock period x 2^14 +7: Clock period x 2^15 +8: Clock period x 2^17 +9: Clock period x 2^19 +10: Clock period x 2^21 +11: Clock period x 2^23 +12: Clock period x 2^25 +13: Clock period x 2^27 +14: Clock period x 2^29 +15: Clock period x 2^31 + 4 + 4 + read-write + + + RSTEN + Enable or disable the watchdog reset +0: Disable +1: Enable + 3 + 1 + read-write + + + INTEN + Enable or disable the watchdog interrupt +0: Disable +1: Enable + 2 + 1 + read-write + + + CLKSEL + Clock source of timer: +0: EXTCLK +1: PCLK + 1 + 1 + read-write + + + EN + Enable or disable the watchdog timer +0: Disable +1: Enable + 0 + 1 + read-write + + + + + Restart + Restart Register + 0x14 + 32 + 0x00000000 + 0x0000FFFF + + + RESTART + Write the magic number +ATCWDT200_RESTART_NUM to restart the +watchdog timer. + 0 + 16 + write-only + + + + + WrEn + Write Protection Register + 0x18 + 32 + 0x00000000 + 0x0000FFFF + + + WEN + Write the magic code to disable the write +protection of the Control Register and the +Restart Register. + 0 + 16 + write-only + + + + + St + Status Register + 0x1c + 32 + 0x00000000 + 0x00000001 + + + INTEXPIRED + The status of the watchdog interrupt timer +0: timer is not expired yet +1: timer is expired + 0 + 1 + write-only + + + + + + + WDG1 + WDG1 + WDOG + 0xf0094000 + + + WDG2 + WDG2 + WDOG + 0xf0098000 + + + WDG3 + WDG3 + WDOG + 0xf009c000 + + + PWDG + PWDG + WDOG + 0xf40e8000 + + + MBX0A + MBX0A + MBX + 0xf00a0000 + + 0x0 + 0x24 + registers + + + + CR + Command Registers + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXRESET + Reset TX Fifo and word. + 31 + 1 + read-write + + + BARCTL + Bus Access Response Control, when bit 15:14= +00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. + 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. +10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. +11: reserved. + 14 + 2 + read-write + + + BEIE + Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. +1, enable the bus access error interrupt. +0, disable the bus access error interrupt. + 8 + 1 + read-write + + + TFMAIE + TX FIFO message available interrupt enable. +1, enable the TX FIFO massage available interrupt. +0, disable the TX FIFO message available interrupt. + 7 + 1 + read-write + + + TFMEIE + TX FIFO message empty interrupt enable. +1, enable the TX FIFO massage empty interrupt. +0, disable the TX FIFO message empty interrupt. + 6 + 1 + read-write + + + RFMAIE + RX FIFO message available interrupt enable. +1, enable the RX FIFO massage available interrupt. +0, disable the RX FIFO message available interrupt. + 5 + 1 + read-write + + + RFMFIE + RX fifo message full interrupt enable. +1, enable the RX fifo message full interrupt. +0, disable the RX fifo message full interrupt. + 4 + 1 + read-write + + + TWMEIE + TX word message empty interrupt enable. +1, enable the TX word massage empty interrupt. +0, disable the TX word message empty interrupt. + 1 + 1 + read-write + + + RWMVIE + RX word message valid interrupt enable. +1, enable the RX word massage valid interrupt. +0, disable the RX word message valid interrupt. + 0 + 1 + read-write + + + + + SR + Status Registers + 0x4 + 32 + 0x000000E2 + 0xFFFF3FFF + + + RFVC + RX FIFO valid message count + 20 + 4 + read-only + + + TFEC + TX FIFO empty message word count + 16 + 4 + read-only + + + ERRRE + bus Error for read when rx word message are still invalid, this bit is W1C bit. +1, read from word message when the word message are still invalid will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 13 + 1 + write-only + + + EWTRF + bus Error for write when tx word message are still valid, this bit is W1C bit. +1, write to word message when the word message are still valid will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 12 + 1 + write-only + + + ERRFE + bus Error for read when rx fifo empty, this bit is W1C bit. +1, read from a empty rx fifo will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 11 + 1 + write-only + + + EWTFF + bus Error for write when tx fifo full, this bit is W1C bit. +1, write to a fulled tx fifo will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 10 + 1 + write-only + + + EAIVA + bus Error for Accessing Invalid Address; this bit is W1C bit. +1, read and write to invalid address in the bus of this block, will set this bit. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 9 + 1 + write-only + + + EW2RO + bus Error for Write to Read Only address; this bit is W1C bit. +1, write to read only address happened in the bus of this block. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 8 + 1 + write-only + + + TFMA + TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. +1, TXFIFO message buffer has slot available +0, no slot available (fifo full) + 7 + 1 + read-write + + + TFME + TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. +1, no any message data in TXFIFO from other core. +0, there are some data in the 4x32 TX FIFO from other core yet. + 6 + 1 + read-write + + + RFMA + RX FIFO Message Available, available data in the 4x32 TX FIFO message buffer to the other core, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, no any data in the 4x32 TXFIFO message buffer. +0, there are some data in the the 4x32 TXFIFO message buffer already. + 5 + 1 + read-only + + + RFMF + RX FIFO Message Full, message from other core; will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, the other core had written 4x32 message in the RXFIFO. +0, no 4x32 RX FIFO message from other core yet. + 4 + 1 + read-only + + + TWME + TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, means this core had write word message to TXREG. +0, means no valid word message in the TXREG yet. + 1 + 1 + read-only + + + RWMV + RX word message valid, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, the other core had written word message in the RXREG. +0, no valid word message yet in the RXREG. + 0 + 1 + read-only + + + + + TXREG + Transmit word message to other core. + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXREG + Transmit word message to other core. + 0 + 32 + write-only + + + + + RXREG + Receive word message from other core. + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + RXREG + Receive word message from other core. + 0 + 32 + read-only + + + + + 1 + 0x4 + TXFIFO0 + TXWRD[%s] + no description available + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXFIFO + TXFIFO for sending message to other core, FIFO size, 4x32 +can write one of the word address to push data to the FIFO; +can also use 4x32 burst write from 0x010 to push 4 words to the FIFO. + 0 + 32 + write-only + + + + + 1 + 0x4 + RXFIFO0 + RXWRD[%s] + no description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXFIFO + RXFIFO for receiving message from other core, FIFO size, 4x32 +can read one of the word address to pop data to the FIFO; +can also use 4x32 burst read from 0x020 to read 4 words from the FIFO. + 0 + 32 + read-only + + + + + + + MBX0B + MBX0B + MBX + 0xf00a4000 + + + MBX1A + MBX1A + MBX + 0xf00a8000 + + + MBX1B + MBX1B + MBX + 0xf00ac000 + + + PTPC + PTPC + PTPC + 0xf00b0000 + + 0x0 + 0x3004 + registers + + + + 2 + 0x1000 + 0,1 + PTPC[%s] + no description available + 0x0 + + Ctrl0 + Control Register 0 + 0x0 + 32 + 0x00000000 + 0x000003FF + + + SUBSEC_DIGITAL_ROLLOVER + Format for ns counter rollover, +1-digital, overflow time 1000000000/0x3B9ACA00 +0-binary, overflow time 0x7FFFFFFF + 9 + 1 + read-write + + + CAPT_SNAP_KEEP + set will keep capture snap till software read capt_snapl. +If this bit is set, software should read capt_snaph first to avoid wrong result. +If this bit is cleared, capture result will be updated at each capture event + 8 + 1 + read-write + + + CAPT_SNAP_POS_EN + set will use posege of input capture signal to latch timestamp value + 7 + 1 + read-write + + + CAPT_SNAP_NEG_EN + No description available + 6 + 1 + read-write + + + COMP_EN + set to enable compare, will be cleared by HW when compare event triggered + 4 + 1 + read-write + + + UPDATE_TIMER + update timer with +/- ts_updt, pulse, clear after set + 3 + 1 + write-only + + + INIT_TIMER + initial timer with ts_updt, pulse, clear after set + 2 + 1 + write-only + + + FINE_COARSE_SEL + 0: coarse update, ns counter add ss_incr[7:0] each clk +1: fine update, ns counter add ss_incr[7:0] each time addend counter overflow + 1 + 1 + read-write + + + TIMER_ENABLE + No description available + 0 + 1 + read-write + + + + + ctrl1 + Control Register 1 + 0x4 + 32 + 0x00000000 + 0x000000FF + + + SS_INCR + constant value used to add ns counter; +such as for 50MHz timer clock, set it to 8'd20 + 0 + 8 + read-write + + + + + timeh + timestamp high + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMESTAMP_HIGH + No description available + 0 + 32 + read-only + + + + + timel + timestamp low + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMESTAMP_LOW + No description available + 0 + 32 + read-only + + + + + ts_updth + timestamp update high + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + SEC_UPDATE + together with ts_updtl, used to initial or update timestamp + 0 + 32 + read-write + + + + + ts_updtl + timestamp update low + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADD_SUB + 1 for sub; 0 for add, used only at update + 31 + 1 + read-write + + + NS_UPDATE + No description available + 0 + 31 + read-write + + + + + addend + No description available + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDEND + used in fine update mode only + 0 + 32 + read-write + + + + + tarh + No description available + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + TARGET_TIME_HIGH + used for generate compare signal if enabled + 0 + 32 + read-write + + + + + tarl + No description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + TARGET_TIME_LOW + No description available + 0 + 32 + read-write + + + + + pps_ctrl + No description available + 0x2c + 32 + 0x00000000 + 0x0000000F + + + PPS_CTRL + No description available + 0 + 4 + read-write + + + + + capt_snaph + No description available + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPT_SNAP_HIGH + take snapshot for input capture signal, at pos or neg or both; +the result can be kept or updated at each event according to cfg0.bit8 + 0 + 32 + read-only + + + + + capt_snapl + No description available + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPT_SNAP_LOW + No description available + 0 + 32 + read-write + + + + + + time_sel + No description available + 0x2000 + 32 + 0x00000000 + 0x0000000F + + + CAN3_TIME_SEL + No description available + 3 + 1 + read-write + + + CAN2_TIME_SEL + No description available + 2 + 1 + read-write + + + CAN1_TIME_SEL + No description available + 1 + 1 + read-write + + + CAN0_TIME_SEL + set to use ptpc1 for canx +clr to use ptpc0 for canx + 0 + 1 + read-write + + + + + int_sts + No description available + 0x2004 + 32 + 0x00000000 + 0x00070007 + + + COMP_INT_STS1 + No description available + 18 + 1 + write-only + + + CAPTURE_INT_STS1 + No description available + 17 + 1 + write-only + + + PPS_INT_STS1 + No description available + 16 + 1 + write-only + + + COMP_INT_STS0 + No description available + 2 + 1 + write-only + + + CAPTURE_INT_STS0 + No description available + 1 + 1 + write-only + + + PPS_INT_STS0 + No description available + 0 + 1 + write-only + + + + + int_en + No description available + 0x2008 + 32 + 0x00000000 + 0x00070007 + + + COMP_INT_STS1 + No description available + 18 + 1 + read-write + + + CAPTURE_INT_STS1 + No description available + 17 + 1 + read-write + + + PPS_INT_STS1 + No description available + 16 + 1 + read-write + + + COMP_INT_STS0 + No description available + 2 + 1 + read-write + + + CAPTURE_INT_STS0 + No description available + 1 + 1 + read-write + + + PPS_INT_STS0 + No description available + 0 + 1 + read-write + + + + + ptpc_can_ts_sel + No description available + 0x3000 + 32 + 0x00000000 + 0xFFFFFF00 + + + TSU_TBIN3_SEL + No description available + 26 + 6 + read-write + + + TSU_TBIN2_SEL + No description available + 20 + 6 + read-write + + + TSU_TBIN1_SEL + No description available + 14 + 6 + read-write + + + TSU_TBIN0_SEL + No description available + 8 + 6 + read-write + + + + + + + DMAMUX + DMAMUX + DMAMUX + 0xf00c0000 + + 0x0 + 0x40 + registers + + + + 16 + 0x4 + HDMA_MUX0,HDMA_MUX1,HDMA_MUX2,HDMA_MUX3,HDMA_MUX4,HDMA_MUX5,HDMA_MUX6,HDMA_MUX7,XDMA_MUX0,XDMA_MUX1,XDMA_MUX2,XDMA_MUX3,XDMA_MUX4,XDMA_MUX5,XDMA_MUX6,XDMA_MUX7 + MUXCFG[%s] + no description available + 0x0 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + + + HDMA + HDMA + DMA + 0xf00c4000 + + 0x10 + 0x130 + registers + + + + DMACfg + DMAC Configuration Register + 0x10 + 32 + 0x00000000 + 0xC3FFFFFF + + + CHAINXFR + Chain transfer +0x0: Chain transfer is not configured +0x1: Chain transfer is configured + 31 + 1 + read-only + + + REQSYNC + DMA request synchronization. The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. +0x0: Request synchronization is not configured +0x1: Request synchronization is configured + 30 + 1 + read-only + + + DATAWIDTH + AXI bus data width +0x0: 32 bits +0x1: 64 bits +0x2: 128 bits +0x3: 256 bits + 24 + 2 + read-only + + + ADDRWIDTH + AXI bus address width +0x18: 24 bits +0x19: 25 bits +... +0x40: 64 bits +Others: Invalid + 17 + 7 + read-only + + + CORENUM + DMA core number +0x0: 1 core +0x1: 2 cores + 16 + 1 + read-only + + + BUSNUM + AXI bus interface number +0x0: 1 AXI bus +0x1: 2 AXI busses + 15 + 1 + read-only + + + REQNUM + Request/acknowledge pair number +0x0: 0 pair +0x1: 1 pair +0x2: 2 pairs +... +0x10: 16 pairs + 10 + 5 + read-only + + + FIFODEPTH + FIFO depth +0x4: 4 entries +0x8: 8 entries +0x10: 16 entries +0x20: 32 entries +Others: Invalid + 4 + 6 + read-only + + + CHANNELNUM + Channel number +0x1: 1 channel +0x2: 2 channels +... +0x8: 8 channels +Others: Invalid + 0 + 4 + read-only + + + + + DMACtrl + DMAC Control Register + 0x20 + 32 + 0x00000000 + 0x00000001 + + + RESET + Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. +Note: The software reset may cause the in-completion of AXI transaction. + 0 + 1 + write-only + + + + + ChAbort + Channel Abort Register + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + CHABORT + Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) + 0 + 32 + write-only + + + + + IntStatus + Interrupt Status Register + 0x30 + 32 + 0x00000000 + 0x00FFFFFF + + + TC + The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. +0x0: Channel n has no terminal count status +0x1: Channel n has terminal count status + 16 + 8 + write-only + + + ABORT + The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. +0x0: Channel n has no abort status +0x1: Channel n has abort status + 8 + 8 + write-only + + + ERROR + The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: +- Bus error +- Unaligned address +- Unaligned transfer width +- Reserved configuration +0x0: Channel n has no error status +0x1: Channel n has error status + 0 + 8 + write-only + + + + + ChEN + Channel Enable Register + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + CHEN + Alias of the Enable field of all ChnCtrl registers + 0 + 32 + read-only + + + + + 8 + 0x20 + ch0,ch1,ch2,ch3,ch4,ch5,ch6,ch7 + CHCTRL[%s] + no description available + 0x40 + + Ctrl + Channel n Control Register + 0x0 + 32 + 0x00000000 + 0xEFFFFFFF + + + SRCBUSINFIDX + Bus interface index that source data is read from +0x0: Data is read from bus interface 0 +0x1: Data is read from bus interface + 31 + 1 + read-write + + + DSTBUSINFIDX + Bus interface index that destination data is written to +0x0: Data is written to bus interface 0 +0x1: Data is written to bus interface 1 + 30 + 1 + read-write + + + PRIORITY + Channel priority level +0x0: Lower priority +0x1: Higher priority + 29 + 1 + read-write + + + SRCBURSTSIZE + Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. +The burst transfer byte number is (SrcBurstSize * SrcWidth). +0x0: 1 transfer +0x1: 2 transfers +0x2: 4 transfers +0x3: 8 transfers +0x4: 16 transfers +0x5: 32 transfers +0x6: 64 transfers +0x7: 128 transfers +0x8: 256 transfers +0x9:512 transfers +0xa: 1024 transfers +0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 + 24 + 4 + read-write + + + SRCWIDTH + Source transfer width +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 + 21 + 3 + read-write + + + DSTWIDTH + Destination transfer width. +Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. +See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 + 18 + 3 + read-write + + + SRCMODE + Source DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 17 + 1 + read-write + + + DSTMODE + Destination DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 16 + 1 + read-write + + + SRCADDRCTRL + Source address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 14 + 2 + read-write + + + DSTADDRCTRL + Destination address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 12 + 2 + read-write + + + SRCREQSEL + Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + 8 + 4 + read-write + + + DSTREQSEL + Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + 4 + 4 + read-write + + + INTABTMASK + Channel abort interrupt mask +0x0: Allow the abort interrupt to be triggered +0x1: Disable the abort interrupt + 3 + 1 + read-write + + + INTERRMASK + Channel error interrupt mask +0x0: Allow the error interrupt to be triggered +0x1: Disable the error interrupt + 2 + 1 + read-write + + + INTTCMASK + Channel terminal count interrupt mask +0x0: Allow the terminal count interrupt to be triggered +0x1: Disable the terminal count interrupt + 1 + 1 + read-write + + + ENABLE + Channel enable bit +0x0: Disable +0x1: Enable + 0 + 1 + read-write + + + + + TranSize + Channel n Transfer Size Register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRANSIZE + Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. +If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + 0 + 32 + read-write + + + + + SrcAddr + Channel n Source Address Low Part Register + 0x8 + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRL + Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + 0 + 32 + read-write + + + + + SrcAddrH + Channel n Source Address High Part Register + 0xc + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRH + High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + DstAddr + Channel n Destination Address Low Part Register + 0x10 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRL + Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + 0 + 32 + read-write + + + + + DstAddrH + Channel n Destination Address High Part Register + 0x14 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRH + High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + LLPointer + Channel n Linked List Pointer Low Part Register + 0x18 + 32 + 0x00000000 + 0xFFFFFFF9 + + + LLPOINTERL + Low part of the pointer to the next descriptor. The pointer must be double word aligned. + 3 + 29 + read-write + + + LLDBUSINFIDX + Bus interface index that the next descriptor is read from +0x0: The next descriptor is read from bus interface 0 + 0 + 1 + read-write + + + + + LLPointerH + Channel n Linked List Pointer High Part Register + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + LLPOINTERH + High part of the pointer to the next descriptor. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + + + + XDMA + XDMA + DMA + 0xf3048000 + + + RNG + RNG + RNG + 0xf00c8000 + + 0x0 + 0x40 + registers + + + + CMD + Command Register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SFTRST + Soft Reset, Perform a software reset of the RNG This bit is self-clearing. +0 Do not perform a software reset. +1 Software reset + 6 + 1 + read-write + + + CLRERR + Clear the Error, clear the errors in the ESR register and the RNG interrupt. This bit is self-clearing. +0 Do not clear the errors and the interrupt. +1 Clear the errors and the interrupt. + 5 + 1 + read-write + + + CLRINT + Clear the Interrupt, clear the RNG interrupt if an error is not present. This bit is self-clearing. +0 Do not clear the interrupt. +1 Clear the interrupt + 4 + 1 + read-write + + + GENSD + Generate Seed, when both ST and GS triggered, ST first and GS next. + 1 + 1 + read-write + + + SLFCHK + Self Test, when both ST and GS triggered, ST first and GS next. + 0 + 1 + read-write + + + + + CTRL + Control Register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + MIRQERR + Mask Interrupt Request for Error + 6 + 1 + read-write + + + MIRQDN + Mask Interrupt Request for Done Event, asks the interrupts generated upon the completion of the seed and self-test modes. The status of these jobs can be viewed by: +• Reading the STA and viewing the seed done and the self-test done bits (STA[SDN, STDN]). +• Viewing the RNG_CMD for the generate-seed or the self-test bits (CMD[GS,ST]) being set, indicating that the operation is still taking place. + 5 + 1 + read-write + + + AUTRSD + Auto Reseed + 4 + 1 + read-write + + + FUFMOD + FIFO underflow response mode +00 Return all zeros and set the ESR[FUFE]. +01 Return all zeros and set the ESR[FUFE]. +10 Generate the bus transfer error +11 Generate the interrupt and return all zeros (overrides the CTRL[MASKERR]). + 0 + 2 + read-write + + + + + STA + Status Register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SCPF + Self Check Pass Fail + 21 + 3 + read-only + + + FUNCERR + Error was detected, check ESR register for details + 16 + 1 + read-only + + + FSIZE + Fifo Size, it is 5 in this design. + 12 + 4 + read-only + + + FRNNU + Fifo Level, Indicates the number of random words currently in the output FIFO + 8 + 4 + read-only + + + NSDDN + New seed done. + 6 + 1 + read-only + + + FSDDN + 1st Seed done +When "1", Indicates that the RNG generated the first seed. + 5 + 1 + read-only + + + SCDN + Self Check Done +Indicates whether Self Test is done or not. Can be cleared by the hardware reset or a new self test is +initiated by setting the CMD[ST]. +0 Self test not completed +1 Completed a self test since the last reset. + 4 + 1 + read-only + + + RSDREQ + Reseed needed +Indicates that the RNG needs to be reseeded. This is done by setting the CMD[GS], or +automatically if the CTRL[ARS] is set. + 3 + 1 + read-only + + + IDLE + Idle, the RNG is in the idle mode, and internal clocks are disabled, in this mode, access to the FIFO is allowed. Once the FIFO is empty, the RNGB fills the FIFO and then enters idle mode again. + 2 + 1 + read-only + + + BUSY + when 1, means the RNG engine is busy for seeding or random number generation, self test and so on. + 1 + 1 + read-only + + + + + ERR + Error Registers + 0xc + 32 + 0x00000000 + 0xFFFFFF3F + + + FUFE + FIFO access error(underflow) + 5 + 1 + read-only + + + SCKERR + Self-test error +Indicates that the RNG failed the most recent self test. This bit is sticky and can only be reset by a +hardware reset or by writing 1 to the CMD[CE] + 3 + 1 + read-only + + + + + FO2B + FIFO out to bus/cpu + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2B + SW read the FIFO output. + 0 + 32 + read-only + + + + + 8 + 0x4 + FO2S0,FO2S1,FO2S2,FO2S3,FO2S4,FO2S5,FO2S6,FO2S7 + R2SK[%s] + no description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2S0 + FIFO out to KMAN, will be SDP engine key. + 0 + 32 + read-only + + + + + + + KEYM + KEYM + KEYM + 0xf00cc000 + + 0x0 + 0x50 + registers + + + + 8 + 0x4 + SFK0,SFK1,SFK2,SFK3,SFK4,SFK5,SFK6,SFK7 + SOFTMKEY[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software symmetric key +key will be scambled to 4 variants for software to use, and replicable on same chip. +scramble keys are chip different, and not replicable on different chip +must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 + 0 + 32 + read-write + + + + + 8 + 0x4 + SPK0,SPK1,SPK2,SPK3,SPK4,SPK5,SPK6,SPK7 + SOFTPKEY[%s] + no description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software asymmetric key +key is derived from scrambles of fuse private key, software input key, SRK, and system security status. +This key os read once, sencondary read will read out 0 + 0 + 32 + read-write + + + + + SEC_KEY_CTL + secure key generation + 0x40 + 32 + 0x00000000 + 0x80011117 + + + LOCK_SEC_CTL + block secure state key setting being changed + 31 + 1 + read-write + + + SK_VAL + session key valid +0: session key is all 0's and not usable +1: session key is valid + 16 + 1 + read-only + + + SMK_SEL + software symmetric key selection +0: use origin value in software symmetric key +1: use scramble version of software symmetric key + 12 + 1 + read-write + + + ZMK_SEL + batt symmetric key selection +0: use scramble version of software symmetric key +1: use origin value in software symmetric key + 8 + 1 + read-write + + + FMK_SEL + fuse symmetric key selection +0: use scramble version of fuse symmetric key +1: use alnertave scramble of fuse symmetric key + 4 + 1 + read-write + + + KEY_SEL + secure symmtric key synthesize setting, key is a XOR of following +bit0: fuse mk, 0: not selected, 1:selected +bit1: zmk from batt, 0: not selected, 1:selected +bit2: software key 0: not selected, 1:selected + 0 + 3 + read-write + + + + + NSC_KEY_CTL + non-secure key generation + 0x44 + 32 + 0x00000000 + 0x80011117 + + + LOCK_NSC_CTL + block non-secure state key setting being changed + 31 + 1 + read-write + + + SK_VAL + session key valid +0: session key is all 0's and not usable +1: session key is valid + 16 + 1 + read-only + + + SMK_SEL + software symmetric key selection +0: use scramble version of software symmetric key +1: use origin value in software symmetric key + 12 + 1 + read-write + + + ZMK_SEL + batt symmetric key selection +0: use scramble version of software symmetric key +1: use origin value in software symmetric key + 8 + 1 + read-write + + + FMK_SEL + fuse symmetric key selection +0: use scramble version of fuse symmetric key +1: use origin value in fuse symmetric key + 4 + 1 + read-write + + + KEY_SEL + non-secure symmtric key synthesize setting, key is a XOR of following +bit0: fuse mk, 0: not selected, 1:selected +bit1: zmk from batt, 0: not selected, 1:selected +bit2: software key 0: not selected, 1:selected + 0 + 3 + read-write + + + + + RNG + Random number interface behavior + 0x48 + 32 + 0x00000000 + 0x00010001 + + + BLOCK_RNG_XOR + block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset +0: RNG_XOR can be changed by software +1: RNG_XOR ignore software change from software + 16 + 1 + read-write + + + RNG_XOR + control how SFK is accepted from random number generator +0: SFK value replaced by random number input +1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG + 0 + 1 + read-write + + + + + READ_CONTROL + key read out control + 0x4c + 32 + 0x00000000 + 0x00010001 + + + BLOCK_PK_READ + asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset +0: key can be read out +1: key cannot be read out + 16 + 1 + read-write + + + BLOCK_SMK_READ + symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset +0: key can be read out +1: key cannot be read out + 0 + 1 + read-write + + + + + + + I2S0 + I2S0 + I2S + 0xf0100000 + + 0x0 + 0x80 + registers + + + + CTRL + Control Register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SFTRST_RX + software reset the RX module if asserted to be 1'b1. Self-clear. + 18 + 1 + read-write + + + SFTRST_TX + software reset the TX module if asserted to be 1'b1. Self-clear. + 17 + 1 + read-write + + + SFTRST_CLKGEN + software reset the CLK GEN module if asserted to be 1'b1. Self-clear. + 16 + 1 + read-write + + + TXDNIE + TX buffer data needed interrupt enable +0: TXE interrupt masked +1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. + 15 + 1 + read-write + + + RXDAIE + RX buffer data available interrupt enable +0: RXNE interrupt masked +1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. + 14 + 1 + read-write + + + ERRIE + Error interrupt enable +This bit controls the generation of an interrupt when an error condition (UD, OV) occurs. +0: Error interrupt is masked +1: Error interrupt is enabled + 13 + 1 + read-write + + + TX_DMA_EN + Asserted to use DMA, else to use interrupt + 12 + 1 + read-write + + + RX_DMA_EN + Asserted to use DMA, else to use interrupt + 11 + 1 + read-write + + + TXFIFOCLR + Self-clear + 10 + 1 + read-write + + + RXFIFOCLR + Self-clear + 9 + 1 + read-write + + + TX_EN + enable for each TX data pad + 5 + 4 + read-write + + + RX_EN + enable for each RX data pad + 1 + 4 + read-write + + + I2S_EN + enable for the module + 0 + 1 + read-write + + + + + RFIFO_FILLINGS + Rx FIFO Filling Level + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RX3 + RX3 fifo fillings + 24 + 8 + read-only + + + RX2 + RX2 fifo fillings + 16 + 8 + read-only + + + RX1 + RX1 fifo fillings + 8 + 8 + read-only + + + RX0 + RX0 fifo fillings + 0 + 8 + read-only + + + + + TFIFO_FILLINGS + Tx FIFO Filling Level + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TX3 + TX3 fifo fillings + 24 + 8 + read-only + + + TX2 + TX2 fifo fillings + 16 + 8 + read-only + + + TX1 + TX1 fifo fillings + 8 + 8 + read-only + + + TX0 + TX0 fifo fillings + 0 + 8 + read-only + + + + + FIFO_THRESH + TX/RX FIFO Threshold setting. + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + TX + TX fifo threshold to trigger STA[tx_dn]. When tx fifo filling is smaller than or equal to the threshold, assert the tx_dn flag. + 8 + 8 + read-write + + + RX + RX fifo threshold to trigger STA[rx_da]. When rx fifo filling is greater than or equal to the threshold, assert the rx_da flag. + 0 + 8 + read-write + + + + + STA + Status Registers + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + TX_UD + Asserted when tx fifo is underflow. Should be ANDed with CTRL[tx_en] the for correct value. Write 1 to any of these 4 bits will clear the underflow error. + 13 + 4 + write-only + + + RX_OV + Asserted when rx fifo is overflow. Write 1 to any of these 4 bits will clear the overflow error. + 9 + 4 + write-only + + + TX_DN + Asserted when tx fifo data are needed. + 5 + 4 + read-only + + + RX_DA + Asserted when rx fifo data are available. + 1 + 4 + read-only + + + + + 4 + 0x4 + DATA0,DATA1,DATA2,DATA3 + RXD[%s] + no description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + D + No description available + 0 + 32 + read-only + + + + + 4 + 0x4 + DATA0,DATA1,DATA2,DATA3 + TXD[%s] + no description available + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + D + No description available + 0 + 32 + write-only + + + + + CFGR + Configruation Regsiters + 0x50 + 32 + 0x40000000 + 0xFFFFFFFF + + + BCLK_GATEOFF + Gate off the bclk. Asserted to gate-off the BCLK. + 30 + 1 + read-write + + + BCLK_DIV + Linear prescaler to generate BCLK from MCLK. +BCLK_DIV [8:0] = 0: BCLK=No CLK. +BCLK_DIV [8:0] = 1: BCLK=MCLK/1 +BCLK_DIV [8:0] = n: BCLK=MCLK/(n). +Note: These bits should be configured when the I2S is disabled. It is used only when the I2S is in master mode. + 21 + 9 + read-write + + + INV_BCLK_OUT + Invert the BCLK before sending it out to pad. Only valid in BCLK master mode + 20 + 1 + read-write + + + INV_BCLK_IN + Invert the BCLK pad input before using it internally. Only valid in BCLK slave mode + 19 + 1 + read-write + + + INV_FCLK_OUT + Invert the FCLK before sending it out to pad. Only valid in FCLK master mode + 18 + 1 + read-write + + + INV_FCLK_IN + Invert the FCLK pad input before using it internally. Only valid in FCLK slave mode + 17 + 1 + read-write + + + INV_MCLK_OUT + Invert the MCLK before sending it out to pad. Only valid in MCLK master mode + 16 + 1 + read-write + + + INV_MCLK_IN + Invert the MCLK pad input before using it internally. Only valid in MCLK slave mode + 15 + 1 + read-write + + + BCLK_SEL_OP + asserted to use external clk source + 14 + 1 + read-write + + + FCLK_SEL_OP + asserted to use external clk source + 13 + 1 + read-write + + + MCK_SEL_OP + asserted to use external clk source + 12 + 1 + read-write + + + FRAME_EDGE + The start edge of a frame +0: Falling edge indicates a new frame (Just like standard I2S Philips standard) +1: Rising edge indicates a new frame + 11 + 1 + read-write + + + CH_MAX + CH_MAX[4:0] s the number of channels supported in TDM mode. When not in TDM mode, it must be set as 2. +It must be an even number, so CH_MAX[0] is always 0. +5'h2: 2 channels +5'h4: 4 channels +... +5‘h10: 16 channels (max) + 6 + 5 + read-write + + + TDM_EN + TDM mode +0: not TDM mode +1: TDM mode + 5 + 1 + read-write + + + STD + I2S standard selection +00: I2S Philips standard. +01: MSB justified standard (left justified) +10: LSB justified standard (right justified) +11: PCM standard +Note: For correct operation, these bits should be configured when the I2S is disabled. + 3 + 2 + read-write + + + DATSIZ + Data length to be transferred +00: 16-bit data length +01: 24-bit data length +10: 32-bit data length +11: Not allowed +Note: For correct operation, these bits should be configured when the I2S is disabled. + 1 + 2 + read-write + + + CHSIZ + Channel length (number of bits per audio channel) +0: 16-bit wide +1: 32-bit wide +The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. +Note: For correct operation, this bit should be configured when the I2S is disabled. + 0 + 1 + read-write + + + + + MISC_CFGR + Misc configuration Registers + 0x58 + 32 + 0x00042000 + 0xFFFFEC01 + + + MCLK_GATEOFF + Gate off the mclk. This mclk is the output of a glitch prone mux, so every time to switch the mclk, the gate off clock should be asserted at first. After the clock is switched, de-assert this bit to ungate off the mclk. + 13 + 1 + read-write + + + MCLKOE + Master clock output to pad enable +0: Master clock output is disabled +1: Master clock output is enabled +Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. + 0 + 1 + read-write + + + + + 4 + 0x4 + DATA0,DATA1,DATA2,DATA3 + RXDSLOT[%s] + no description available + 0x60 + 32 + 0x0000FFFF + 0x0000FFFF + + + EN + No description available + 0 + 16 + read-write + + + + + 4 + 0x4 + DATA0,DATA1,DATA2,DATA3 + TXDSLOT[%s] + no description available + 0x70 + 32 + 0x0000FFFF + 0x0000FFFF + + + EN + No description available + 0 + 16 + read-write + + + + + + + I2S1 + I2S1 + I2S + 0xf0104000 + + + I2S2 + I2S2 + I2S + 0xf0108000 + + + I2S3 + I2S3 + I2S + 0xf010c000 + + + DAO + DAO + DAO + 0xf0110000 + + 0x0 + 0x1c + registers + + + + CTRL + Control Register + 0x0 + 32 + 0x00000000 + 0x000200FF + + + HPF_EN + Whether HPF is enabled. This HPF is used to filter out the DC part. + 17 + 1 + read-write + + + MONO + Asserted to let the left and right channel output the same value. + 7 + 1 + read-write + + + RIGHT_EN + Asserted to enable the right channel + 6 + 1 + read-write + + + LEFT_EN + Asserted to enable the left channel + 5 + 1 + read-write + + + REMAP + 1: Use remap pwm version. The remap version is a version that one pwm output is tied to zero when the input pcm signal is positive or negative +0: Don't use remap pwm version + 4 + 1 + read-write + + + INVERT + all the outputs are inverted before sending to pad + 3 + 1 + read-write + + + FALSE_LEVEL + the pad output in False run mode, or when the module is disabled +0: all low +1: all high +2: P-high, N-low +3. output is not enabled + 1 + 2 + read-write + + + FALSE_RUN + the module continues to consume data, but all the pads are constant, thus no audio out + 0 + 1 + read-write + + + + + CMD + Command Register + 0x8 + 32 + 0x00000000 + 0x00000003 + + + SFTRST + Self-clear + 1 + 1 + read-write + + + RUN + Enable this module to run. + 0 + 1 + read-write + + + + + RX_CFGR + Configuration Register + 0xc + 32 + 0x00000000 + 0x000007C0 + + + CH_MAX + CH_MAX[3:0] is the number if channels supported in TDM mode. When not in TDM mode, it must be set as 2. +It must be an even number, so CH_MAX[0] is always 0. +4'h2: 2 channels +4'h4: 4 channels +etc + 6 + 5 + read-write + + + + + RXSLT + RX Slot Control Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + EN + Slot enable for the channels. + 0 + 32 + read-write + + + + + HPF_MA + HPF A Coef Register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + COEF + Composite value of coef A of the Order-1 HPF + 0 + 32 + read-write + + + + + HPF_B + HPF B Coef Register + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + COEF + coef B of the Order-1 HPF + 0 + 32 + read-write + + + + + + + PDM + PDM + PDM + 0xf0114000 + + 0x0 + 0x34 + registers + + + + CTRL + Control Register + 0x0 + 32 + 0x00000000 + 0x809FF7FF + + + SFTRST + software reset the module. Self-clear. + 31 + 1 + read-write + + + SOF_FEDGE + asserted if the falling edge of the ref fclk from DAO is the start of a new frame. This is used to to align DAO feedback signal. + 23 + 1 + read-write + + + USE_COEF_RAM + Asserted to use Coef RAM instead of Coef ROM + 20 + 1 + read-write + + + FILT_CRX_ERR_IE + data accessed out of boundary error interruput enable. The error happens when the module cannot calculate the enough number of data in time. + 19 + 1 + read-write + + + OFIFO_OVFL_ERR_IE + output fifo overflow error interrupt enable + 18 + 1 + read-write + + + CIC_OVLD_ERR_IE + CIC overload error interrupt enable + 17 + 1 + read-write + + + CIC_SAT_ERR_IE + Error interrupt enable +This bit controls the generation of an interrupt when an error condition (CIC saturation) occurs. +0: Error interrupt is masked +1: Error interrupt is enabled + 16 + 1 + read-write + + + DEC_AFT_CIC + decimation rate after CIC. Now it is forced to be 3. + 12 + 4 + read-write + + + CAPT_DLY + Capture cycle delay>=0, should be less than PDM_CLK_HFDIV + 7 + 4 + read-write + + + PDM_CLK_HFDIV + The clock divider will work at least 4. +0: div-by-2, +1: div-by-4 +. . . +n: div-by-2*(n+1) + 3 + 4 + read-write + + + PDM_CLK_DIV_BYPASS + asserted to bypass the pdm clock divider + 2 + 1 + read-write + + + PDM_CLK_OE + pdm_clk_output_en + 1 + 1 + read-write + + + HPF_EN + pdm high pass filter enable. This order-1 HPF only applies to the PDM mic data. + 0 + 1 + read-write + + + + + CH_CTRL + Channel Control Register + 0x4 + 32 + 0x00000000 + 0x00FF03FF + + + CH_POL + Asserted to select PDM_CLK high level captured, otherwise to select PDM_CLK low level captured. + 16 + 8 + read-write + + + CH_EN + Asserted to enable the channel. +Ch8 & 9 are refs. +Ch0-7 are pdm mics. + 0 + 10 + read-write + + + + + ST + Status Register + 0x8 + 32 + 0x00000000 + 0x0000000F + + + FILT_CRX_ERR + data accessed out of boundary error + 3 + 1 + write-only + + + OFIFO_OVFL_ERR + output fifo overflow error. The reason may be sampling frequency mismatch, either fast or slow. + 2 + 1 + write-only + + + CIC_OVLD_ERR + CIC overload error. write 1 clear + 1 + 1 + write-only + + + CIC_SAT_ERR + CIC saturation. Write 1 clear + 0 + 1 + write-only + + + + + CH_CFG + Channel Configuration Register + 0xc + 32 + 0x00000000 + 0x000FFFFF + + + CH9_TYPE + No description available + 18 + 2 + read-write + + + CH8_TYPE + No description available + 16 + 2 + read-write + + + CH7_TYPE + No description available + 14 + 2 + read-write + + + CH6_TYPE + No description available + 12 + 2 + read-write + + + CH5_TYPE + No description available + 10 + 2 + read-write + + + CH4_TYPE + No description available + 8 + 2 + read-write + + + CH3_TYPE + No description available + 6 + 2 + read-write + + + CH2_TYPE + No description available + 4 + 2 + read-write + + + CH1_TYPE + No description available + 2 + 2 + read-write + + + CH0_TYPE + Type of Channel 0 +2'b00: dec-by-3 wiith filter type0 (CIC Compenstation+norm filter) +2'b01: dec-by-3 with filter type 1 (No CIC compenstation, only norm filter) + 0 + 2 + read-write + + + + + CIC_CFG + CIC configuration register + 0x10 + 32 + 0x00000000 + 0x0000FFFF + + + POST_SCALE + the shift value after CIC results. + 10 + 6 + read-write + + + SGD + Sigma_delta_order[1:0] +2'b00: 7 +2'b01: 6 +2'b10: 5 +Others: unused + 8 + 2 + read-write + + + CIC_DEC_RATIO + CIC decimation factor + 0 + 8 + read-write + + + + + CTRL_INBUF + In Buf Control Register + 0x14 + 32 + 0x00000000 + 0x3FFFFFFF + + + MAX_PTR + The buf size-1 for each channel + 22 + 8 + read-write + + + PITCH + The spacing between starting address of adjacent channels + 11 + 11 + read-write + + + START_ADDR + The starting address of channel 0 in filter data buffer + 0 + 11 + read-write + + + + + CTRL_FILT0 + Filter 0 Control Register + 0x18 + 32 + 0x00000000 + 0x0000FFFF + + + COEF_LEN_M0 + Coef length of filter type 2'b00 in coef memory + 8 + 8 + read-write + + + COEF_START_ADDR + Starting address of Coef of filter type 2'b00 in coef memory + 0 + 8 + read-write + + + + + CTRL_FILT1 + Filter 1 Control Register + 0x1c + 32 + 0x00000000 + 0x0000FFFF + + + COEF_LEN_M1 + Coef length of filter type 2'b01 in coef memory + 8 + 8 + read-write + + + COEF_START_ADDR + Starting address of Coef of filter type 2'b01 in coef memory + 0 + 8 + read-write + + + + + RUN + Run Register + 0x20 + 32 + 0x00000000 + 0x00000001 + + + PDM_EN + Asserted to enable the module + 0 + 1 + read-write + + + + + MEMAddr + Memory Access Address + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + 0--0x0FFFFFFF: COEF_RAM +0x10000000--0x1FFFFFFF: DATA_RAM + 0 + 32 + read-write + + + + + MEMData + Memory Access Data + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + The data write-to/read-from buffer + 0 + 32 + read-write + + + + + HPF_MA + HPF A Coef Register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + COEF + Composite value of coef A of the Order-1 HPF + 0 + 32 + read-write + + + + + HPF_B + HPF B Coef Register + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + COEF + coef B of the Order-1 HPF + 0 + 32 + read-write + + + + + + + PWM0 + PWM0 + PWM + 0xf0200000 + + 0x0 + 0x290 + registers + + + + unlk + Shadow registers unlock register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHUNLK + write 0xB0382607 to unlock the shadow registers of register offset from 0x04 to 0x78, +otherwise the shadow registers can not be written. + 0 + 32 + read-write + + + + + sta + Counter start register + UNION_STA + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + XSTA + pwm timer counter extended start point, should back to this value after reach xrld + 28 + 4 + read-write + + + STA + pwm timer counter start value + sta/rld will be loaded from shadow register to work register at main counter reload time, or software write unlk.shunlk + 4 + 24 + read-write + + + + + rld + Counter reload register + UNION_RLD + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + XRLD + timeout counter extended reload point, counter will reload to xsta after reach this point + 28 + 4 + read-write + + + RLD + pwm timer counter reload value + 4 + 24 + read-write + + + + + 24 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 + CMP[%s] + no description available + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, +and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + frcmd + Force output mode register + 0x78 + 32 + 0x00000000 + 0x0000FFFF + + + FRCMD + 2bit for each PWM output channel (0-7); +00: force output 0 +01: force output 1 +10: output highz +11: no force + 0 + 16 + read-write + + + + + shlk + Shadow registers lock register + 0x7c + 32 + 0x00000000 + 0x80000000 + + + SHLK + write 1 to lock all shawdow register, write access is not permitted + 31 + 1 + read-write + + + + + 24 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 + CHCFG[%s] + no description available + 0x80 + 32 + 0x00000000 + 0xFFFF0003 + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + + + gcr + Global control register + 0xf0 + 32 + 0x00000000 + 0xFDFFFFE7 + + + FAULTI3EN + 1- enable the internal fault input 3 + 31 + 1 + read-write + + + FAULTI2EN + 1- enable the internal fault input 2 + 30 + 1 + read-write + + + FAULTI1EN + 1- enable the internal fault input 1 + 29 + 1 + read-write + + + FAULTI0EN + 1- enable the internal fault input 0 + 28 + 1 + read-write + + + DEBUGFAULT + 1- enable debug mode output protection + 27 + 1 + read-write + + + FRCPOL + polarity of input pwm_force, +1- active low +0- active high + 26 + 1 + read-write + + + HWSHDWEDG + When hardware event is selected as shawdow register effective time and the select comparator is configured as input capture mode. +This bit assign its which edge is used as compare shadow register hardware load event. +1- Falling edge +0- Rising edge + 24 + 1 + read-write + + + CMPSHDWSEL + This bitfield select one of the comparators as hardware event time to load comparator shadow registers + 19 + 5 + read-write + + + FAULTRECEDG + When hardware load is selected as output fault recover trigger and the selected channel is capture mode. +This bit assign its effective edge of fault recover trigger. +1- Falling edge +0- Rising edge + 18 + 1 + read-write + + + FAULTRECHWSEL + Selec one of the 24 comparators as fault output recover trigger. + 13 + 5 + read-write + + + FAULTE1EN + 1- enable the external fault input 1 + 12 + 1 + read-write + + + FAULTE0EN + 1- enable the external fault input 0 + 11 + 1 + read-write + + + FAULTEXPOL + external fault polarity +1-active low +0-active high + 9 + 2 + read-write + + + RLDSYNCEN + 1- pwm timer counter reset to reload value (rld) by synci is enabled + 8 + 1 + read-write + + + CEN + 1- enable the pwm timer counter +0- stop the pwm timer counter + 7 + 1 + read-write + + + FAULTCLR + 1- Write 1 to clear the fault condition. The output will recover if FAULTRECTIME is set to 2b'11. +User should write 1 to this bit after the active FAULT signal de-assert and before it re-assert again. + 6 + 1 + read-write + + + XRLDSYNCEN + 1- pwm timer extended counter (xcnt) reset to extended reload value (xrld) by synci is enabled + 5 + 1 + read-write + + + FRCTIME + This bit field select the force effective time +00: force immediately +01: force at main counter reload time +10: force at FRCSYNCI +11: no force + 1 + 2 + write-only + + + SWFRC + 1- write 1 to enable software force, if the frcsrcsel is set to 0, force will take effect + 0 + 1 + read-write + + + + + shcr + Shadow register control register + 0xf4 + 32 + 0x00000000 + 0x00001FFF + + + FRCSHDWSEL + This bitfield select one of the comparators as hardware event time to load FRCMD shadow registers + 8 + 5 + read-write + + + CNTSHDWSEL + This bitfield select one of the comparators as hardware event time to load the counter related shadow registers (STA and RLD) + 3 + 5 + read-write + + + CNTSHDWUPT + This bitfield select when the counter related shadow registers (STA and RLD) will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 1 + 2 + read-write + + + SHLKEN + 1- enable shadow registers lock feature, +0- disable shadow registers lock, shlk bit will always be 0 + 0 + 1 + read-write + + + + + 24 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 + CAPPOS[%s] + no description available + 0x100 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + cnt + Counter + 0x170 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCNT + current extended counter value + 28 + 4 + read-only + + + CNT + current clock counter value + 4 + 24 + read-only + + + + + 24 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 + CAPNEG[%s] + no description available + 0x180 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + cntcopy + Counter copy + 0x1f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCNT + current extended counter value + 28 + 4 + read-only + + + CNT + current clock counter value + 4 + 24 + read-only + + + + + 8 + 0x4 + 0,1,2,3,4,5,6,7 + PWMCFG[%s] + no description available + 0x200 + 32 + 0x00000000 + 0x1FFFFFFF + + + OEN + PWM output enable +1- output is enabled +0- output is disabled + 28 + 1 + read-write + + + FRCSHDWUPT + This bitfield select when the FRCMD shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 26 + 2 + read-write + + + FAULTMODE + This bitfield defines the PWM output status when fault condition happen +00: force output 0 +01: force output 1 +1x: output highz + 24 + 2 + read-write + + + FAULTRECTIME + This bitfield select when to recover PWM output after fault condition removed. +00: immediately +01: after pwm timer counter reload time +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after software write faultclr bit in GCR register + 22 + 2 + read-write + + + FRCSRCSEL + Select sources for force output +0- force output is enabled when FRCI assert +1- force output is enabled by software write swfrc to 1 + 21 + 1 + read-write + + + PAIR + 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. +0- PWM output is in indepandent mode. + 20 + 1 + read-write + + + DEADAREA + This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. +Note: user should configure pair bit and this bitfield before PWM output is enabled. + 0 + 20 + read-write + + + + + sr + Status register + 0x220 + 32 + 0x00000000 + 0x0FFFFFFF + + + FAULTF + fault condition flag + 27 + 1 + write-only + + + XRLDF + extended reload flag, this flag set when xcnt count to xrld value or when SYNCI assert + 26 + 1 + write-only + + + HALFRLDF + half reload flag, this flag set when cnt count to rld/2 + 25 + 1 + write-only + + + RLDF + reload flag, this flag set when cnt count to rld value or when SYNCI assert + 24 + 1 + write-only + + + CMPFX + comparator output compare or input capture flag + 0 + 24 + write-only + + + + + irqen + Interrupt request enable register + 0x224 + 32 + 0x00000000 + 0x0FFFFFFF + + + FAULTIRQE + fault condition interrupt enable + 27 + 1 + read-write + + + XRLDIRQE + extended reload flag interrupt enable + 26 + 1 + read-write + + + HALFRLDIRQE + half reload flag interrupt enable + 25 + 1 + read-write + + + RLDIRQE + reload flag interrupt enable + 24 + 1 + read-write + + + CMPIRQEX + comparator output compare or input capture flag interrupt enable + 0 + 24 + read-write + + + + + dmaen + DMA request enable register + 0x22c + 32 + 0x00000000 + 0x0FFFFFFF + + + FAULTEN + fault condition DMA request enable + 27 + 1 + read-write + + + XRLDEN + extended reload flag DMA request enable + 26 + 1 + read-write + + + HALFRLDEN + half reload flag DMA request enable + 25 + 1 + read-write + + + RLDEN + reload flag DMA request enable + 24 + 1 + read-write + + + CMPENX + comparator output compare or input capture flag DMA request enable + 0 + 24 + read-write + + + + + 24 + 0x4 + cmpcfg0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 + CMPCFG[%s] + no description available + 0x230 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + + + + + PWM1 + PWM1 + PWM + 0xf0210000 + + + PWM2 + PWM2 + PWM + 0xf0220000 + + + PWM3 + PWM3 + PWM + 0xf0230000 + + + HALL0 + HALL0 + HALL + 0xf0204000 + + 0x0 + 0x88 + registers + + + + cr + Control Register + 0x0 + 32 + 0x00000000 + 0x8001083F + + + READ + 1- load ucnt, vcnt, wcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 + 31 + 1 + write-only + + + SNAPEN + 1- load ucnt, vcnt, wcnt and tmrcnt into their snap registers when snapi input assert + 11 + 1 + read-write + + + RSTCNT + set to reset all counter and related snapshots + 4 + 1 + read-write + + + + + phcfg + Phase configure register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DLYSEL + This bit select delay start time: +1- start counting delay after pre-trigger +0- start counting delay after u,v,w toggle + 31 + 1 + read-write + + + DLYCNT + delay clock cycles number + 0 + 24 + read-write + + + + + wdgcfg + Watchdog configure register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + WDGEN + 1- enable wdog counter + 31 + 1 + read-write + + + WDGTO + watch dog timeout value + 0 + 31 + read-write + + + + + uvwcfg + U,V,W configure register + 0xc + 32 + 0x00000000 + 0x07FFFFFF + + + PRECNT + the clock cycle number which the pre flag will set before the next uvw transition + 0 + 24 + read-write + + + + + trgoen + Trigger output enable register + 0x10 + 32 + 0x00000000 + 0xFFE00000 + + + WDGEN + 1- enable trigger output when wdg flag set + 31 + 1 + read-write + + + PHUPTEN + 1- enable trigger output when phupt flag set + 30 + 1 + read-write + + + PHPREEN + 1- enable trigger output when phpre flag set + 29 + 1 + read-write + + + PHDLYEN + 1- enable trigger output when phdly flag set + 28 + 1 + read-write + + + UFEN + 1- enable trigger output when u flag set + 23 + 1 + read-write + + + VFEN + 1- enable trigger output when v flag set + 22 + 1 + read-write + + + WFEN + 1- enable trigger output when w flag set + 21 + 1 + read-write + + + + + readen + Read event enable register + 0x14 + 32 + 0x00000000 + 0xFFE00000 + + + WDGEN + 1- load counters to their read registers when wdg flag set + 31 + 1 + read-write + + + PHUPTEN + 1- load counters to their read registers when phupt flag set + 30 + 1 + read-write + + + PHPREEN + 1- load counters to their read registers when phpre flag set + 29 + 1 + read-write + + + PHDLYEN + 1- load counters to their read registers when phdly flag set + 28 + 1 + read-write + + + UFEN + 1- load counters to their read registers when u flag set + 23 + 1 + read-write + + + VFEN + 1- load counters to their read registers when v flag set + 22 + 1 + read-write + + + WFEN + 1- load counters to their read registers when w flag set + 21 + 1 + read-write + + + + + dmaen + DMA enable register + 0x24 + 32 + 0x00000000 + 0xFFE00000 + + + WDGEN + 1- generate dma request when wdg flag set + 31 + 1 + read-write + + + PHUPTEN + 1- generate dma request when phupt flag set + 30 + 1 + read-write + + + PHPREEN + 1- generate dma request when phpre flag set + 29 + 1 + read-write + + + PHDLYEN + 1- generate dma request when phdly flag set + 28 + 1 + read-write + + + UFEN + 1- generate dma request when u flag set + 23 + 1 + read-write + + + VFEN + 1- generate dma request when v flag set + 22 + 1 + read-write + + + WFEN + 1- generate dma request when w flag set + 21 + 1 + read-write + + + + + sr + Status register + 0x28 + 32 + 0x00000000 + 0xFFE00000 + + + WDGF + watchdog count timeout flag + 31 + 1 + read-write + + + PHUPTF + phase update flag, will set when any of u, v, w signal toggle + 30 + 1 + read-write + + + PHPREF + phase update pre flag, will set PRECNT cycles before any of u, v, w signal toggle + 29 + 1 + read-write + + + PHDLYF + phase update delay flag, will set DLYCNT cycles after any of u, v, w signal toggle or after the phpre flag depands on DLYSEL setting + 28 + 1 + read-write + + + UF + u flag, will set when u signal toggle + 23 + 1 + read-write + + + VF + v flag, will set when v signal toggle + 22 + 1 + read-write + + + WF + w flag, will set when w signal toggle + 21 + 1 + read-write + + + + + irqen + Interrupt request enable register + 0x2c + 32 + 0x00000000 + 0xFFE00000 + + + WDGIE + 1- generate interrupt request when wdg flag set + 31 + 1 + read-write + + + PHUPTIE + 1- generate interrupt request when phupt flag set + 30 + 1 + read-write + + + PHPREIE + 1- generate interrupt request when phpre flag set + 29 + 1 + read-write + + + PHDLYIE + 1- generate interrupt request when phdly flag set + 28 + 1 + read-write + + + UFIE + 1- generate interrupt request when u flag set + 23 + 1 + read-write + + + VFIE + 1- generate interrupt request when v flag set + 22 + 1 + read-write + + + WFIE + 1- generate interrupt request when w flag set + 21 + 1 + read-write + + + + + 4 + 0x10 + current,read,snap0,snap1 + COUNT[%s] + no description available + 0x30 + + w + W counter + 0x0 + 32 + 0x00000000 + 0x0FFFFFFF + + + WCNT + wcnt counter + 0 + 28 + read-only + + + + + v + V counter + 0x4 + 32 + 0x00000000 + 0xCFFFFFFF + + + VCNT + vcnt counter + 0 + 28 + read-only + + + + + u + U counter + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 31 + 1 + read-only + + + USTAT + this bit indicate U state + 30 + 1 + read-only + + + VSTAT + this bit indicate V state + 29 + 1 + read-only + + + WSTAT + this bit indicate W state + 28 + 1 + read-only + + + UCNT + ucnt counter + 0 + 28 + read-only + + + + + tmr + Timer counter + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMER + 32 bit free run timer + 0 + 32 + read-only + + + + + + 3 + 0x8 + u,v,w + HIS[%s] + no description available + 0x70 + + his0 + history register 0 + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + UHIS0 + copy of ucnt when u signal transition from 0 to 1 + 0 + 32 + read-only + + + + + his1 + history register 1 + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + UHIS1 + copy of ucnt when u signal transition from 1 to 0 + 0 + 32 + read-only + + + + + + + + HALL1 + HALL1 + HALL + 0xf0214000 + + + HALL2 + HALL2 + HALL + 0xf0224000 + + + HALL3 + HALL3 + HALL + 0xf0234000 + + + QEI0 + QEI0 + QEI + 0xf0208000 + + 0x0 + 0x80 + registers + + + + cr + Control register + 0x0 + 32 + 0x00000000 + 0x80077F3F + + + READ + 1- load phcnt, zcnt, spdcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 + 31 + 1 + write-only + + + HRSTSPD + 1- reset spdcnt when H assert + 18 + 1 + read-write + + + HRSTPH + 1- reset phcnt when H assert + 17 + 1 + read-write + + + HRSTZ + 1- reset zcnt when H assert + 16 + 1 + read-write + + + PAUSESPD + 1- pause spdcnt when PAUSE assert + 14 + 1 + read-write + + + PAUSEPH + 1- pause phcnt when PAUSE assert + 13 + 1 + read-write + + + PAUSEZ + 1- pause zcnt when PAUSE assert + 12 + 1 + read-write + + + HRDIR1 + 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction) + 11 + 1 + read-write + + + HRDIR0 + 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction) + 10 + 1 + read-write + + + HFDIR1 + 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction) + 9 + 1 + read-write + + + HFDIR0 + 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction) + 8 + 1 + read-write + + + SNAPEN + 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert + 5 + 1 + read-write + + + RSTCNT + 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx + 4 + 1 + read-write + + + ENCTYP + 00-abz; 01-pd; 10-ud; 11-reserved + 0 + 2 + read-write + + + + + phcfg + Phase configure register + 0x4 + 32 + 0x00000000 + 0x007FFFFF + + + ZCNTCFG + 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 +0- zcnt will increment or decrement when Z input assert + 22 + 1 + read-write + + + PHCALIZ + 1- phcnt will set to phidx when Z input assert + 21 + 1 + read-write + + + PHMAX + maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax + 0 + 21 + read-write + + + + + wdgcfg + Watchdog configure register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + WDGEN + 1- enable wdog counter + 31 + 1 + read-write + + + WDGTO + watch dog timeout value + 0 + 31 + read-write + + + + + phidx + Phase index register + 0xc + 32 + 0x00000000 + 0x001FFFFF + + + PHIDX + phcnt reset value, phcnt will reset to phidx when phcaliz set to 1 + 0 + 21 + read-write + + + + + trgoen + Tigger output enable register + 0x10 + 32 + 0x00000000 + 0xF0000000 + + + WDGFEN + 1- enable trigger output when wdg flag set + 31 + 1 + read-write + + + HOMEFEN + 1- enable trigger output when homef flag set + 30 + 1 + read-write + + + POSCMPFEN + 1- enable trigger output when poscmpf flag set + 29 + 1 + read-write + + + ZPHFEN + 1- enable trigger output when zphf flag set + 28 + 1 + read-write + + + + + readen + Read event enable register + 0x14 + 32 + 0x00000000 + 0xF0000000 + + + WDGFEN + 1- load counters to their read registers when wdg flag set + 31 + 1 + read-write + + + HOMEFEN + 1- load counters to their read registers when homef flag set + 30 + 1 + read-write + + + POSCMPFEN + 1- load counters to their read registers when poscmpf flag set + 29 + 1 + read-write + + + ZPHFEN + 1- load counters to their read registers when zphf flag set + 28 + 1 + read-write + + + + + zcmp + Z comparator + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + ZCMP + zcnt postion compare value + 0 + 32 + read-write + + + + + phcmp + Phase comparator + 0x1c + 32 + 0x00000000 + 0xE01FFFFF + + + ZCMPDIS + 1- postion compare not include zcnt + 31 + 1 + read-write + + + DIRCMPDIS + 1- postion compare not include rotation direction + 30 + 1 + read-write + + + DIRCMP + 0- position compare need positive rotation +1- position compare need negative rotation + 29 + 1 + read-write + + + PHCMP + phcnt position compare value + 0 + 21 + read-write + + + + + spdcmp + Speed comparator + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + SPDCMP + spdcnt position compare value + 0 + 32 + read-write + + + + + dmaen + DMA request enable register + 0x24 + 32 + 0x00000000 + 0xF0000000 + + + WDGFEN + 1- generate dma request when wdg flag set + 31 + 1 + read-write + + + HOMEFEN + 1- generate dma request when homef flag set + 30 + 1 + read-write + + + POSCMPFEN + 1- generate dma request when poscmpf flag set + 29 + 1 + read-write + + + ZPHFEN + 1- generate dma request when zphf flag set + 28 + 1 + read-write + + + + + sr + Status register + 0x28 + 32 + 0x00000000 + 0xF0000000 + + + WDGF + watchdog flag + 31 + 1 + read-write + + + HOMEF + home flag + 30 + 1 + read-write + + + POSCMPF + postion compare match flag + 29 + 1 + read-write + + + ZPHF + z input flag + 28 + 1 + read-write + + + + + irqen + Interrupt request register + 0x2c + 32 + 0x00000000 + 0xF0000000 + + + WDGIE + 1- generate interrupt when wdg flag set + 31 + 1 + read-write + + + HOMEIE + 1- generate interrupt when homef flag set + 30 + 1 + read-write + + + POSCMPIE + 1- generate interrupt when poscmpf flag set + 29 + 1 + read-write + + + ZPHIE + 1- generate interrupt when zphf flag set + 28 + 1 + read-write + + + + + 4 + 0x10 + current,read,snap0,snap1 + COUNT[%s] + no description available + 0x30 + + z + Z counter + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + ZCNT + zcnt value + 0 + 32 + read-write + + + + + ph + Phase counter + 0x4 + 32 + 0x00000000 + 0x461FFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 30 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 26 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 25 + 1 + read-only + + + PHCNT + phcnt value + 0 + 21 + read-only + + + + + spd + Speed counter + 0x8 + 32 + 0x00000000 + 0xEFFFFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 31 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 30 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 29 + 1 + read-write + + + SPDCNT + spdcnt value + 0 + 28 + read-only + + + + + tmr + Timer counter + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + TMRCNT + 32 bit free run timer + 0 + 32 + read-only + + + + + + 4 + 0x4 + spdhis0,spdhis1,spdhis2,spdhis3 + SPDHIS[%s] + no description available + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + SPDHIS0 + copy of spdcnt, load from spdcnt after any transition from a = low, b = low + 0 + 32 + read-only + + + + + + + QEI1 + QEI1 + QEI + 0xf0218000 + + + QEI2 + QEI2 + QEI + 0xf0228000 + + + QEI3 + QEI3 + QEI + 0xf0238000 + + + TRGM0 + TRGM0 + TRGM + 0xf020c000 + + 0x0 + 0x404 + registers + + + + 20 + 0x4 + PWM_IN0,PWM_IN1,PWM_IN2,PWM_IN3,PWM_IN4,PWM_IN5,PWM_IN6,PWM_IN7,TRGM_IN0,TRGM_IN1,TRGM_IN2,TRGM_IN3,TRGM_IN4,TRGM_IN5,TRGM_IN6,TRGM_IN7,TRGM_IN8,TRGM_IN9,TRGM_IN10,TRGM_IN11 + FILTCFG[%s] + no description available + 0x0 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + 64 + 0x4 + TRGM_OUT0,TRGM_OUT1,TRGM_OUT2,TRGM_OUT3,TRGM_OUT4,TRGM_OUT5,TRGM_OUT6,TRGM_OUT7,TRGM_OUT8,TRGM_OUT9,TRGM_OUT10,TRGM_OUT11,TRGM_OUTX0,TRGM_OUTX1,PWM_SYNCI,PWM_FRCI,PWM_FRCSYNCI,PWM_SHRLDSYNCI,PWM_FAULTI0,PWM_FAULTI1,PWM_FAULTI2,PWM_FAULTI3,PWM_IN8,PWM_IN9,PWM_IN10,PWM_IN11,PWM_IN12,PWM_IN13,PWM_IN14,PWM_IN15,PWM_IN16,PWM_IN17,PWM_IN18,PWM_IN19,PWM_IN20,PWM_IN21,PWM_IN22,PWM_IN23,QEI_A,QEI_B,QEI_Z,QEI_H,QEI_PAUSE,QEI_SNAPI,HALL_U,HALL_V,HALL_W,HALL_SNAPI,ADC0_STRGI,ADC1_STRGI,ADC2_STRGI,ADC3_STRGI,ADCx_PTRGI0A,ADCx_PTRGI0B,ADCx_PTRGI0C,GPTMRa_SYNCI,GPTMRa_IN2,GPTMRa_IN3,GPTMRb_SYNCI,GPTMRb_IN2,GPTMRb_IN3,CMPx_WIN,CAN_PTPC0_CAP,CAN_PTPC1_CAP + TRGOCFG[%s] + no description available + 0x100 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + 4 + 0x4 + 0,1,2,3 + DMACFG[%s] + no description available + 0x200 + 32 + 0x00000000 + 0x0000001F + + + DMASRCSEL + This field selects one of the DMA requests as the DMA request output. + 0 + 5 + read-write + + + + + GCR + General Control Register + 0x400 + 32 + 0x00000000 + 0x00000FFF + + + TRGOPEN + The bitfield enable the TRGM outputs. + 0 + 12 + read-write + + + + + + + TRGM1 + TRGM1 + TRGM + 0xf021c000 + + + TRGM2 + TRGM2 + TRGM + 0xf022c000 + + + TRGM3 + TRGM3 + TRGM + 0xf023c000 + + + SYNT + SYNT + SYNT + 0xf0240000 + + 0x0 + 0x30 + registers + + + + gcr + Global control register + 0x0 + 32 + 0x00000000 + 0x00000003 + + + CRST + 1- Reset counter + 1 + 1 + read-write + + + CEN + 1- Enable counter + 0 + 1 + read-write + + + + + rld + Counter reload register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RLD + counter reload value + 0 + 32 + read-write + + + + + cnt + Counter + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + CNT + counter + 0 + 32 + read-only + + + + + 4 + 0x4 + 0,1,2,3 + CMP[%s] + no description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + comparator value, the output will assert when counter count to this value + 0 + 32 + read-write + + + + + + + LCDC + LCDC + LCDC + 0xf1000000 + + 0x0 + 0x404 + registers + + + + CTRL + Control Register + 0x0 + 32 + 0x00000000 + 0xFFF0001F + + + SW_RST + Software reset, high active. When write 1 ,all internal logical will be reset. +0b - No action +1b - All LCDC internal registers are forced into their reset state. Interface registers are not affected. + 31 + 1 + read-write + + + DISP_ON + Display panel On/Off mode. +0b - Display Off. +1b - Display On. +Display can be set off at any time, but it can only be set on after VS_BLANK status is asserted. +So a good procedure to stop and turn on the display is: +1) clr VS_BLANK status +2) assert software reset +3) de-assert software reset +4) set display off +5) check VS_BLANK status until it is asserted, +6)reset the module, change settings +7) set display on + 30 + 1 + read-write + + + LINE_PATTERN + LCDIF line output order. +000b - RGB. +001b - RBG. +010b - GBR. +011b - GRB. +100b - BRG. +101b - BGR. + 27 + 3 + read-write + + + DISP_MODE + LCDIF operating mode. +00b - Normal mode. Panel content controlled by layer configuration. +01b - Test Mode1.(BGND Color Display) +10b - Test Mode2.(Column Color Bar) +11b - Test Mode3.(Row Color Bar) + 25 + 2 + read-write + + + BGDCL4CLR + background color for clear mode when the alpha channel is 0 + 24 + 1 + read-write + + + ARQOS + ARQOS for bus fabric arbitration + 20 + 4 + read-write + + + INV_PXDATA + Indicates if value at the output (pixel data output) needs to be negated. +0b - Output is to remain same as the data inside memory +1b - Output to be negated from the data inside memory + 4 + 1 + read-write + + + INV_PXCLK + Polarity change of Pixel Clock. +0b - LCDC outputs data on the rising edge, and Display samples data on the falling edge +1b - LCDC outputs data on the falling edge, Display samples data on the rising edge + 3 + 1 + read-write + + + INV_HREF + Polarity of HREF +0b - HREF signal active HIGH, indicating active pixel data +1b - HREF signal active LOW + 2 + 1 + read-write + + + INV_VSYNC + Polarity of VSYNC +0b - VSYNC signal active HIGH +1b - VSYNC signal active LOW + 1 + 1 + read-write + + + INV_HSYNC + Polarity of HSYNC +0b - HSYNC signal active HIGH +1b - HSYNC signal active LOW + 0 + 1 + read-write + + + + + BGND_CL + Background Color Register + 0x4 + 32 + 0x00000000 + 0x00FFFFFF + + + R + Red component of the default color displayed in the sectors where no layer is active. + 16 + 8 + read-write + + + G + Green component of the default color displayed in the sectors where no layer is active. + 8 + 8 + read-write + + + B + Blue component of the default color displayed in the sectors where no layer is active. + 0 + 8 + read-write + + + + + DISP_WN_SIZE + Display Window Size Register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + Y + Sets the display size vertical resolution in pixels. + 16 + 12 + read-write + + + X + Sets the display size horizontal resolution in pixels. + 0 + 12 + read-write + + + + + HSYNC_PARA + HSYNC Config Register + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + FP + HSYNC front-porch pulse width (in pixel clock cycles). If zero, indicates no front-porch for HSYNC + 22 + 9 + read-write + + + BP + HSYNC back-porch pulse width (in pixel clock cycles). If zero, indicates no back-porch for HSYNC + 11 + 9 + read-write + + + PW + HSYNC active pulse width (in pixel clock cycles). Pulse width has a minimum value of 1. + 0 + 9 + read-write + + + + + VSYNC_PARA + VSYNC Config Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + FP + VSYNC front-porch pulse width (in horizontal line cycles). If zero, means no front-porch for VSYNC + 22 + 9 + read-write + + + BP + VSYNC back-porch pulse width (in horizontal line cycles). If zero, means no back-porch for VSYNC + 11 + 9 + read-write + + + PW + VSYNC active pulse width (in horizontal line cycles). Pulse width has a minimum value of 1. + 0 + 9 + read-write + + + + + DMA_ST + DMA Status Register + 0x14 + 32 + 0x00000000 + 0xFFFFFF00 + + + DMA_ERR + plane n axi error. W1C. + 24 + 8 + write-only + + + DMA1_DONE + Plane n frame 1 dma done. W1C. + 16 + 8 + write-only + + + DMA0_DONE + Plane n frame 0 dma done. W1C. + 8 + 8 + write-only + + + + + ST + Status Register + 0x18 + 32 + 0x00000000 + 0x0000000F + + + URGENT_UNDERRUN + Asserted when the output buffer urgent underrun condition encountered + 3 + 1 + write-only + + + VS_BLANK + Asserted when in vertical blanking period. At the start of VSYNC + 2 + 1 + write-only + + + UNDERRUN + Asserted when the output buffer underrun condition encountered + 1 + 1 + write-only + + + VSYNC + Asserted when in vertical blanking period. At the end of VSYNC + 0 + 1 + write-only + + + + + INT_EN + Interrupt Enable Register + 0x1c + 32 + 0x00000000 + 0xFFFFFF0F + + + DMA_ERR + Interrupt enable for DMA error + 24 + 8 + read-write + + + DMA_DONE + Interrupt enable for DMA done + 16 + 8 + read-write + + + URGENT_UNDERRUN + Asserted when the output buffer urgent underrun condition encountered + 3 + 1 + read-write + + + VS_BLANK + Interrupt enable for start of sof + 2 + 1 + read-write + + + UNDERRUN + Interrupt enable for underrun + 1 + 1 + read-write + + + VSYNC + Interrupt enable for end of sof + 0 + 1 + read-write + + + + + TXFIFO + TX FIFO Register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + THRSH + Threshold to start the lcd raster (0--0x7F) + 0 + 8 + read-write + + + + + 8 + 0x40 + 0,1,2,3,4,5,6,7 + LAYER[%s] + no description available + 0x200 + + LAYCTRL + Layer Control Register + 0x0 + 32 + 0x00000000 + 0x000FFFFD + + + PACK_DIR + The byte sequence of the 4 bytes in a 32-bit word. +1: {A0, A1, A2, A3} byte re-ordered. +0: {A3, A2, A1, A0} the normal case with no byte re-order + 19 + 1 + read-write + + + SHADOW_LOAD_EN + Shadow Load Enable +The SHADOW_LOAD_EN bit is written to 1 by software after all DMA control registers are written. If set to 1, shadowed control registers are updated to the active control registers on internal logical VSYNC of next frame. If set to 0, shadowed control registers are not loaded into the active control registers. The previous active control register settings will be used to process the next frame. Hardware will automatically clear this bit, when the shadow registers are loaded to the active control regsisters. + 16 + 1 + read-write + + + YUV_FORMAT + The YUV422 input format selection. +00b - The YVYU422 8bit sequence is U1,Y1,V1,Y2 +01b - The YVYU422 8bit sequence is V1,Y1,U1,Y2 +10b - The YVYU422 8bit sequence is Y1,U1,Y2,V1 +11b - The YVYU422 8bit sequence is Y1,V1,Y2,U1 +If not YUV422 mode, +FORMAT[0]: asserted to exchange sequence inside the bytes. Org [15:8]-->New[8:15], Org [7:0]-->New[0:7]. (First exchange) +FORMAT[1]: asserted to exchange the sequence of the odd and even 8 bits. Org Even [7:0]-->New[15:8], Org Odd [15:8]-->New[7:0]. (Second exchange) + 14 + 2 + read-write + + + PIXFORMAT + Layer encoding format (bit per pixel) +0000b - 1 bpp (pixel width must be multiples of 32), pixel sequence is from LSB to MSB in 32b word. +0001b - 2 bpp (pixel width must be multiples of 16), pixel sequence is from LSB to MSB in 32b word. +0010b - 4 bpp (pixel width must be multiples of 8), pixel sequence is from LSB to MSB in 32b word. +0011b - 8 bpp (pixel width must be multiples of 4), pixel sequence is from LSB to MSB in 32b word. +0100b - 16 bpp (RGB565), the low byte contains the full R component. +0111b - YCbCr422 (Only layer 0/1 can support this format), byte sequence determined by LAYCTRL[YUV_FORMAT] +1001b - 32 bpp (ARGB8888), byte sequence as B,G,R,A +1011b - Y8 (pixel width must be multiples of 4), byte sequence as Y1,Y2,Y3,Y4 + 10 + 4 + read-write + + + LOCALPHA_OP + The usage of the LOCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) +0: the LOCALPHA[7:0] is invalid, use the alpha value from the data stream +1: the LOCALPHA[7:0] is used to override the alpha value in the data stream (useful when the data stream has no alpha info) +2: the LOCALPHA[7:0] is used to scale the alpha value from the data stream +Others: Reserved + 8 + 2 + read-write + + + INALPHA_OP + The usage of the INALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) +0: the INALPHA[7:0] is invalid, use the alpha value from previous pipeline +1: the INALPHA[7:0] is used to override the alpha value from previous pipeline. (useful when the corresponding data stream has no alpha info) +2: the INALPHA[7:0] is used to scale the alpha value from previous pipeline +Others: Reserved + 6 + 2 + read-write + + + AB_MODE + Alpha Blending Mode +0: SKBlendMode_Clear; +1: SKBlendMode_Src ; +2: SKBlendMode_Dst +3: SKBlendMode_SrcOver +4: SKBlendMode_DstOver +5: SKBlendMode_SrcIn +6: SKBlendMode_DstIn +7: SKBlendMode_SrcOut +8: SKBlendMode_DstOut +9: SKBlendMode_SrcATop +10: SKBlendMode_DstATop +11: SKBlendMode_Xor +12: SKBlendMode_Plus (The conventional blending mode) +13: SKBlendMode_Modulate +14: SRC org +15: DST org +Others: Reserved. + 2 + 4 + read-write + + + EN + Asserted when the layer is enabled. If this layer is not enabled, it means a bypassing plane. + 0 + 1 + read-write + + + + + ALPHAS + Layer Alpha Register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCD + The system alpha value for the data stream of current layer stream (SRC) + 8 + 8 + read-write + + + IND + The system alpha value for the input stream from previous stage (DST) + 0 + 8 + read-write + + + + + LAYSIZE + Layer Size Register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + HEIGHT + Height of the layer in pixels + 16 + 12 + read-write + + + WIDTH + Width of the layer in pixels (Note: not actual width-1) +The layer width must be in multiples of the number of pixels that can be stored in 32 bits, and therefore differs depending on color encoding. For example, if 2 bits per pixel format is used, then the layer width must be configured in multiples of 16. + 0 + 12 + read-write + + + + + LAYPOS + Layer Position Register + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + Y + The vertical position of top row of the layer, where 0 is the top row of the panel, positive values are below the top row of the panel. + 16 + 16 + read-write + + + X + The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, positive values are to the right the left-hand column of the panel. + 0 + 16 + read-write + + + + + START0 + Layer Buffer Pointer Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR0 + Input buffer Start address 0 + 0 + 32 + read-write + + + + + LINECFG + Layer Bus Config Register + 0x18 + 32 + 0x00000000 + 0xE0FFFFFF + + + MPT_SIZE + Maximal Per Transfer Data Size: +0: 64 bytes +1: 128 bytes +2: 256 bytes +3: 512 bytes +4: 1024 bytes + 29 + 3 + read-write + + + MAX_OT + the number of outstanding axi read transactions. +If zero, it means max 8. + 21 + 3 + read-write + + + PITCH + Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundary. + 0 + 16 + read-write + + + + + BG_CL + Layer Background Color Register + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + ARGB + ARGB8888. It is only useful in the last active stage in the pipeline. + 0 + 32 + read-write + + + + + CSC_COEF0 + Layer Color Space Conversion Config Register 0 + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + YCBCR_MODE + This bit changes the behavior when performing U/V converting. +0b - Converting YUV to RGB data +1b - Converting YCbCr to RGB data + 31 + 1 + read-write + + + ENABLE + Enable the CSC unit in the LCDC plane data path. +0b - The CSC is bypassed and the input pixels are RGB data already +1b - The CSC is enabled and the pixels will be converted to RGB data +This bit will be shadowed. + 30 + 1 + read-write + + + C0 + Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) + 18 + 11 + read-write + + + UV_OFFSET + Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. +YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). + 9 + 9 + read-write + + + Y_OFFSET + Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is +typically -16 (0x1F0). + 0 + 9 + read-write + + + + + CSC_COEF1 + Layer Color Space Conversion Config Register 1 + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + C1 + Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). + 16 + 11 + read-write + + + C4 + Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). + 0 + 11 + read-write + + + + + CSC_COEF2 + Layer Color Space Conversion Config Register 2 + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + C2 + Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). + 16 + 11 + read-write + + + C3 + Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). + 0 + 11 + read-write + + + + + + CLUT_LOAD + Clut Load Control Register + 0x400 + 32 + 0x00000000 + 0x0000007F + + + SEL_NUM + Selected CLUT Number +The SEL_CLUT_NUM is used to select which plane's CLUT need to be updated. The hardware can only backup one CLUT setting and load, so the SEL_CLUT_NUM can't be changed when CLUT_LOAD[UPDATE_EN] is 1. +. 3'h0 - PLANE 0 +. 3'h1 - PLANE 1 +. ------ +. 3'h7 - PLANE 7 +CLUT 8 can be modified via APB even when display is on. +Currently CLUT for plane 0..7 cannot be modified via APB when display is on. Can only be updated via CLUT_LOAD[UPDATE_EN] bit. + 4 + 3 + read-write + + + UPDATE_EN + CLUT Update Enable +The bit is written to 1 when software want to update the Color Look Up Tables during display. +If set to 1, software update selected CLUT due to SEL_CLUT_NUM setting, the table will be copied from CLUT8 during vertical blanking period after SHADOW_LOAD_EN is set to 1. +If set to 0, software can update CLUT8 directly according to the CLUT memory map. +Hardware will automatically clear this bit when selected CLUT is updated according to SEL_CLUT_NUM. + 0 + 1 + read-write + + + + + + + CAM0 + CAM0 + CAM + 0xf1008000 + + 0x0 + 0x490 + registers + + + + CR1 + Control Register + 0x0 + 32 + 0x00000000 + 0xBF9AAFFF + + + COLOR_EXT + If asserted, will change the output color to ARGB8888 mode. Used by input color as RGB565, RGB888, YUV888, etc. +The byte sequence is B,G,R,A. Depends on correct CR2[ClrBitFormat] configuration. + 29 + 1 + read-write + + + INV_PIXCLK + invert pixclk pad input before it is used + 28 + 1 + read-write + + + INV_HSYNC + invert hsync pad input before it is used + 27 + 1 + read-write + + + INV_VSYNC + invert vsync pad input before it is used + 26 + 1 + read-write + + + SWAP16_EN + SWAP 16-Bit Enable. This bit enables the swapping of 16-bit data. Data is packed from 8-bit or 10-bit to 32-bit first (according to the setting of PACK_DIR) and then swapped as 16-bit words before being put into the RX FIFO. The action of the bit only affects the RX FIFO. +NOTE: Example of swapping enabled: +Data input to FIFO = 0x11223344 +Data in RX FIFO = 0x 33441122 +NOTE: Example of swapping disabled: +Data input to FIFO = 0x11223344 +Data in RX FIFO = 0x11223344 +0 Disable swapping +1 Enable swapping + 25 + 1 + read-write + + + PACK_DIR + Data Packing Direction. This bit Controls how 8-bit/10-bit image data is packed into 32-bit RX FIFO. +0 Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. +1 Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. + 24 + 1 + read-write + + + RESTART_BUSPTR + force to restart the bus pointer at the every end of the sof period, and at the same time, clr the fifo pointer + 23 + 1 + read-write + + + ASYNC_RXFIFO_CLR + ASynchronous Rx FIFO Clear. +When asserted, this bit clears RXFIFO immediately. +It will be auto-cleared. + 20 + 1 + read-write + + + SYNC_RXFIFO_CLR + Synchronous Rx FIFO Clear. +When asserted, this bit clears RXFIFO on every SOF. + 19 + 1 + read-write + + + SOF_INT_POL + SOF Interrupt Polarity. This bit controls the condition that generates an SOF interrupt. +0 SOF interrupt is generated on SOF falling edge +1 SOF interrupt is generated on SOF rising edge + 17 + 1 + read-write + + + INV_DATA + Invert Data Input. This bit enables or disables internal inverters on the data lines. +0 CAM_D data lines are directly applied to internal circuitry +1 CAM_D data lines are inverted before applied to internal circuitry + 15 + 1 + read-write + + + STORAGE_MODE + 00: Normal Mode (one plane mode) +01: Two Plane Mode (Y, UV plane) +10: Y-only Mode, byte sequence as Y0,Y1,Y2,Y3 +11: Binary Mode, bit sequence is from LSB to MSB when CR20[BIG_END]=0 + 10 + 2 + read-write + + + COLOR_FORMATS + input color formats: +0010b:24bit:RGB888 +0011b:24bit:RGB666 +0100b:16bit:RGB565 +0101b:16bit:RGB444 +0110b:16bit:RGB555 +0111b: 16bit: YCbCr422 (Y0 Cb Y1 Cr, each 8-bit) +YUV +YCrCb +Note: YUV420 is not supported. +1000b: 24bit: YUV444 + 3 + 4 + read-write + + + SENSOR_BIT_WIDTH + the bit width of the sensor +0: 8 bits +1: 10 bits +3:24bits +Others: Undefined + 0 + 3 + read-write + + + + + INT_EN + Interrupt Enable Register + 0x4 + 32 + 0x00000000 + 0xFFFFFF5F + + + ERR_CL_BWID_CFG_INT_EN + The unsupported color (color_formats[3:0]) and bitwidth (sensor_bit_width[2:0]) configuation interrupt enable + 13 + 1 + read-write + + + HIST_DONE_INT_EN + Enable hist done int + 12 + 1 + read-write + + + HRESP_ERR_EN + Hresponse Error Enable. This bit enables the hresponse error interrupt. +0 Disable hresponse error interrupt +1 Enable hresponse error interrupt + 11 + 1 + read-write + + + EOF_INT_EN + End-of-Frame Interrupt Enable. This bit enables and disables the EOF interrupt. +0 EOF interrupt is disabled. +1 EOF interrupt is generated when RX count value is reached. + 9 + 1 + read-write + + + RF_OR_INTEN + RxFIFO Overrun Interrupt Enable. This bit enables the RX FIFO overrun interrupt. +0 RxFIFO overrun interrupt is disabled +1 RxFIFO overrun interrupt is enabled + 6 + 1 + read-write + + + FB2_DMA_DONE_INTEN + Frame Buffer2 DMA Transfer Done Interrupt Enable. This bit enables the interrupt of Frame Buffer2 DMA +transfer done. +0 Frame Buffer2 DMA Transfer Done interrupt disable +1 Frame Buffer2 DMA Transfer Done interrupt enable + 3 + 1 + read-write + + + FB1_DMA_DONE_INTEN + Frame Buffer1 DMA Transfer Done Interrupt Enable. This bit enables the interrupt of Frame Buffer1 DMA +transfer done. +0 Frame Buffer1 DMA Transfer Done interrupt disable +1 Frame Buffer1 DMA Transfer Done interrupt enable + 2 + 1 + read-write + + + SOF_INT_EN + Start Of Frame (SOF) Interrupt Enable. This bit enables the SOF interrupt. +0 SOF interrupt disable +1 SOF interrupt enable + 0 + 1 + read-write + + + + + CR2 + Control 2 Register + 0x10 + 32 + 0x00000000 + 0xFFFF8FEF + + + FRMCNT_15_0 + Frame Counter. This is a 16-bit Frame Counter +(Wraps around automatically after reaching the maximum) + 16 + 16 + read-only + + + FRMCNT_RST + Frame Count Reset. Resets the Frame Counter. +0 Do not reset +1 Reset frame counter immediately + 15 + 1 + read-write + + + RXFF_LEVEL + RxFIFO Full Level. When the number of data in RxFIFO reaches this level, a RxFIFO full interrupt is generated, or an RXFIFO DMA request is sent. +000 4 Double words +001 8 Double words +010 16 Double words +011 24 Double words +100 32 Double words +101 48 Double words +110 64 Double words +111 96 Double words + 9 + 3 + read-write + + + DMA_REQ_EN_RFF + DMA Request Enable for RxFIFO. This bit enables the dma request from RxFIFO to the embedded DMA controller. +0 Disable the dma request +1 Enable the dma request. The UV Rx FIFO is only enabled to filling data in 2 plane mode. + 5 + 1 + read-write + + + CLRBITFORMAT + Input Byte & bit sequence same as OV5640, except for Raw mode. Used only for internal ARGB conversion. + 0 + 4 + read-write + + + + + STA + Status Register + 0x24 + 32 + 0x00000000 + 0xFFFFA7FC + + + ERR_CL_BWID_CFG + The unsupported color (color_formats[3:0]) and bitwidth (sensor_bit_width[2:0]) configuation found + 19 + 1 + write-only + + + HIST_DONE + hist cal done + 18 + 1 + write-only + + + RF_OR_INT + RxFIFO Overrun Interrupt Status. Indicates the overflow status of the RxFIFO register. (Cleared by writing +1) +0 RXFIFO has not overflowed. +1 RXFIFO has overflowed. + 13 + 1 + write-only + + + DMA_TSF_DONE_FB2 + DMA Transfer Done in Frame Buffer2. Indicates that the DMA transfer from RxFIFO to Frame Buffer2 is completed. It can trigger an interrupt if the corresponding enable bit is set in CAM_CR1. This bit can be cleared by by writing 1 or reflashing the RxFIFO dma controller in CAM_CR3. (Cleared by writing 1) +0 DMA transfer is not completed. +1 DMA transfer is completed. + 10 + 1 + write-only + + + DMA_TSF_DONE_FB1 + DMA Transfer Done in Frame Buffer1. Indicates that the DMA transfer from RxFIFO to Frame Buffer1 is completed. It can trigger an interrupt if the corresponding enable bit is set in CAM_CR1. This bit can be cleared by by writing 1 or reflashing the RxFIFO dma controller in CAM_CR3. (Cleared by writing 1) +0 DMA transfer is not completed. +1 DMA transfer is completed. + 9 + 1 + write-only + + + EOF_INT + End of Frame (EOF) Interrupt Status. Indicates when EOF is detected. (Cleared by writing 1) +0 EOF is not detected. +1 EOF is detected. + 7 + 1 + write-only + + + SOF_INT + Start of Frame Interrupt Status. Indicates when SOF is detected. (Cleared by writing 1) +0 SOF is not detected. +1 SOF is detected. + 6 + 1 + write-only + + + HRESP_ERR_INT + Hresponse Error Interrupt Status. Indicates that a hresponse error has been detected. (Cleared by writing +1) +0 No hresponse error. +1 Hresponse error is detected. + 2 + 1 + write-only + + + + + DMASA_FB1 + Pixel DMA Frame Buffer 1 Address + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + PTR + DMA Start Address in Frame Buffer1. Indicates the start address to write data. The embedded DMA controller will read data from RxFIFO and write it from this address through AHB bus. The address should be double words aligned. +In Two-Plane Mode, Y buffer1 + 2 + 30 + read-write + + + + + DMASA_FB2 + Pixel DMA Frame Buffer 2 Address + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + PTR + DMA Start Address in Frame Buffer2. Indicates the start address to write data. The embedded DMA controller will read data from RxFIFO and write it from this address through AHB bus. The address should be double words aligned. +In Two-Plane Mode, Y buffer2 + 2 + 30 + read-write + + + + + BUF_PARA + Buffer Parameters Register + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINEBSP_STRIDE + Line Blank Space Stride. Indicates the space between the end of line image storage and the start of a new line storage in the frame buffer. +The width of the line storage in frame buffer(in double words) minus the width of the image(in double words) is the stride. The stride should be double words aligned. The embedded DMA controller will skip the stride before starting to write the next row of the image. + 0 + 16 + read-write + + + + + IDEAL_WN_SIZE + Ideal Image Size Register + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + HEIGHT + Image Height. Indicates how many active pixels in a column of the image from the sensor. + 16 + 16 + read-write + + + WIDTH + Image Width. Indicates how many active pixels in a line of the image from the sensor. +The number of bytes to be transferred is re-calculated automatically in hardware based on cr1[color_ext] and cr1[store_mode]. Default value is 2*pixel number. +As the input data from the sensor is 8-bit/pixel format, the IMAGE_WIDTH should be a multiple of 8 pixels. + 0 + 16 + read-write + + + + + CR18 + Control CR18 Register + 0x4c + 32 + 0x00000000 + 0xFFFFE7BF + + + CAM_ENABLE + CAM global enable signal. Only when this bit is 1, CAM can start to receive the data and store to memory. + 31 + 1 + read-write + + + AWQOS + AWQOS for bus fabric arbitration + 7 + 4 + read-write + + + + + DMASA_UV1 + Pixel UV DMA Frame Buffer 1 Address + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + PTR + Two Plane UV Buffer Start Address 1 + 2 + 30 + read-write + + + + + DMASA_UV2 + Pixel UV DMA Frame Buffer 2 Address + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + PTR + Two Plane UV Buffer Start Address 2 + 2 + 30 + read-write + + + + + CR20 + Control CR20 Register + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + BINARY_EN + binary picture output enable + 31 + 1 + read-write + + + HISTOGRAM_EN + histogarm enable + 30 + 1 + read-write + + + BIG_END + Asserted when binary output is in big-endian type, which mean the right most data is at the LSBs. Take function only inside the 32-bit word. + 8 + 1 + read-write + + + THRESHOLD + Threshold to generate binary color. Bin 1 is output if the pixel is greater than the threshold. + 0 + 8 + read-write + + + + + CSC_COEF0 + Color Space Conversion Config Register 0 + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + YCBCR_MODE + This bit changes the behavior when performing U/V converting. +0b - Converting YUV to RGB data +1b - Converting YCbCr to RGB data + 31 + 1 + read-write + + + ENABLE + Enable the CSC unit +0b - The CSC is bypassed and the input pixels are RGB data already +1b - The CSC is enabled and the pixels will be converted to RGB data + 30 + 1 + read-write + + + C0 + Two's compliment Y multiplier coefficient. YUV=0x100 (1.000) YCbCr=0x12A (1.164) + 18 + 11 + read-write + + + UV_OFFSET + Two's compliment phase offset implicit for CbCr data. Generally used for YCbCr to RGB conversion. +YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). + 9 + 9 + read-write + + + Y_OFFSET + Two's compliment amplitude offset implicit in the Y data. For YUV, this is typically 0 and for YCbCr, this is +typically -16 (0x1F0). + 0 + 9 + read-write + + + + + CSC_COEF1 + Color Space Conversion Config Register 1 + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + C1 + Two's compliment Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596). + 16 + 11 + read-write + + + C4 + Two's compliment Blue U/Cb multiplier coefficient. YUV=0x208 (2.032) YCbCr=0x204 (2.017). + 0 + 11 + read-write + + + + + CSC_COEF2 + Color Space Conversion Config Register 2 + 0x78 + 32 + 0x00000000 + 0xFFFFFFFF + + + C2 + Two's compliment Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). + 16 + 11 + read-write + + + C3 + Two's compliment Green U/Cb multiplier coefficient. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). + 0 + 11 + read-write + + + + + CLRKEY_LOW + Low Color Key Register + 0x7c + 32 + 0x00000000 + 0xFFFFFFFF + + + LIMIT + Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. + 0 + 24 + read-write + + + + + CLRKEY_HIGH + High Color Key Register + 0x80 + 32 + 0x00000000 + 0xFFFFFFFF + + + LIMIT + Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. + 0 + 24 + read-write + + + + + 256 + 0x4 + DATA0,DATA1,DATA2,DATA3,DATA4,DATA5,DATA6,DATA7,DATA8,DATA9,DATA10,DATA11,DATA12,DATA13,DATA14,DATA15,DATA16,DATA17,DATA18,DATA19,DATA20,DATA21,DATA22,DATA23,DATA24,DATA25,DATA26,DATA27,DATA28,DATA29,DATA30,DATA31,DATA32,DATA33,DATA34,DATA35,DATA36,DATA37,DATA38,DATA39,DATA40,DATA41,DATA42,DATA43,DATA44,DATA45,DATA46,DATA47,DATA48,DATA49,DATA50,DATA51,DATA52,DATA53,DATA54,DATA55,DATA56,DATA57,DATA58,DATA59,DATA60,DATA61,DATA62,DATA63,DATA64,DATA65,DATA66,DATA67,DATA68,DATA69,DATA70,DATA71,DATA72,DATA73,DATA74,DATA75,DATA76,DATA77,DATA78,DATA79,DATA80,DATA81,DATA82,DATA83,DATA84,DATA85,DATA86,DATA87,DATA88,DATA89,DATA90,DATA91,DATA92,DATA93,DATA94,DATA95,DATA96,DATA97,DATA98,DATA99,DATA100,DATA101,DATA102,DATA103,DATA104,DATA105,DATA106,DATA107,DATA108,DATA109,DATA110,DATA111,DATA112,DATA113,DATA114,DATA115,DATA116,DATA117,DATA118,DATA119,DATA120,DATA121,DATA122,DATA123,DATA124,DATA125,DATA126,DATA127,DATA128,DATA129,DATA130,DATA131,DATA132,DATA133,DATA134,DATA135,DATA136,DATA137,DATA138,DATA139,DATA140,DATA141,DATA142,DATA143,DATA144,DATA145,DATA146,DATA147,DATA148,DATA149,DATA150,DATA151,DATA152,DATA153,DATA154,DATA155,DATA156,DATA157,DATA158,DATA159,DATA160,DATA161,DATA162,DATA163,DATA164,DATA165,DATA166,DATA167,DATA168,DATA169,DATA170,DATA171,DATA172,DATA173,DATA174,DATA175,DATA176,DATA177,DATA178,DATA179,DATA180,DATA181,DATA182,DATA183,DATA184,DATA185,DATA186,DATA187,DATA188,DATA189,DATA190,DATA191,DATA192,DATA193,DATA194,DATA195,DATA196,DATA197,DATA198,DATA199,DATA200,DATA201,DATA202,DATA203,DATA204,DATA205,DATA206,DATA207,DATA208,DATA209,DATA210,DATA211,DATA212,DATA213,DATA214,DATA215,DATA216,DATA217,DATA218,DATA219,DATA220,DATA221,DATA222,DATA223,DATA224,DATA225,DATA226,DATA227,DATA228,DATA229,DATA230,DATA231,DATA232,DATA233,DATA234,DATA235,DATA236,DATA237,DATA238,DATA239,DATA240,DATA241,DATA242,DATA243,DATA244,DATA245,DATA246,DATA247,DATA248,DATA249,DATA250,DATA251,DATA252,DATA253,DATA254,DATA255 + HISTOGRAM_FIFO[%s] + no description available + 0x90 + 32 + 0x00000000 + 0xFFFFFFFF + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + + + CAM1 + CAM1 + CAM + 0xf100c000 + + + PDMA + PDMA + PDMA + 0xf1010000 + + 0x0 + 0xc0 + registers + + + + CTRL + Control Register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + ARQOS + QoS for AXI read bus + 19 + 4 + read-write + + + AWQOS + QoS for AXI write bus + 15 + 4 + read-write + + + PACK_DIR + Decide the byte sequence of the 32-bit output word {A3, A2, A1, A0}. The bit sequence ina byte is not changed. +2'b00: no change {A3, A2, A1, A0} +2'b01: {A2, A3, A0, A1} +2'b10: {A1, A0, A3, A2} +2'b11: {A0, A1, A2, A3} + 13 + 2 + read-write + + + AXIERR_IRQ_EN + Enable interrupt of AXI bus error + 12 + 1 + read-write + + + PDMA_DONE_IRQ_EN + Enable interrupt of PDMA_DONE + 11 + 1 + read-write + + + CLKGATE + Assert this bit to gate off clock when the module is not working. If reset to zero, the internal clock is always on. + 9 + 1 + read-write + + + IRQ_EN + Enable normal interrupt + 6 + 1 + read-write + + + BS16 + Asserted when the Block Size is 16x16, else 8x8 + 5 + 1 + read-write + + + P1_EN + Plane 1 Enable + 4 + 1 + read-write + + + P0_EN + Plane 0 Enable + 3 + 1 + read-write + + + PDMA_SFTRST + Software Reset. +Write 1 to clear PDMA internal logic. +Write 0 to exit software reset mode. + 1 + 1 + read-write + + + PDMA_EN + 1b - Enabled + 0 + 1 + read-write + + + + + STAT + Status Register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + BLOCKY + Y block that is processing + 24 + 8 + read-only + + + BLOCKX + X block that is processing + 16 + 8 + read-only + + + PDMA_DONE + PDMA one image done + 9 + 1 + write-only + + + AXI_ERR_ID + AXI error ID + 5 + 4 + read-only + + + AXI_0_WRITE_ERR + AXI0 write err + 4 + 1 + write-only + + + AXI_1_READ_ERR + AXI1 read err + 3 + 1 + write-only + + + AXI_0_READ_ERR + AXI0 read err + 2 + 1 + write-only + + + IRQ + Asserted to indicate a IRQ event + 0 + 1 + read-only + + + + + OUT_CTRL + Out Layer Control Register + 0x8 + 32 + 0x00000000 + 0xFFFFFF3F + + + DSTALPHA + The destination (P1) system ALPHA value. + 24 + 8 + read-write + + + SRCALPHA + The source (P0) system ALPHA value. + 16 + 8 + read-write + + + DSTALPHA_OP + The usage of the DSTALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel embedded in the stream indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) +0: the DSTALPHA[7:0] is invalid, use the alpha value embedded in the stream +1: the DSTALPHA[7:0] is used to override the alpha value embedded in the stream. (useful when the corresponding data stream has no alpha info) +2: the DSTALPHA[7:0] is used to scale the alpha value embedded in the stream +Others: Reserved + 14 + 2 + read-write + + + SRCALPHA_OP + The usage of the SRCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel embedded in the stream indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) +0: the SRCALPHA[7:0] is invalid, use the alpha value embedded in the stream +1: the SRCALPHA[7:0] is used to override the alpha value embedded in the stream . (useful when the corresponding data stream has no alpha info) +2: the SRCALPHA[7:0] is used to scale the alpha value embedded in the stream +Others: Reserved + 12 + 2 + read-write + + + ABLEND_MODE + Alpha Blending Mode +0: SKBlendMode_Clear (If PS1_CTRL[BKGNDCL4CLR] is asserted, use PS1_BKGRND color to fill the range determined by PS1, else fill the range determined by PS1 with zero); +1: SKBlendMode_Src ; +2: SKBlendMode_Dst +3: SKBlendMode_SrcOver +4: SKBlendMode_DstOver +5: SKBlendMode_SrcIn +6: SKBlendMode_DstIn +7: SKBlendMode_SrcOut +8: SKBlendMode_DstOut +9: SKBlendMode_SrcATop +10: SKBlendMode_DstATop +11: SKBlendMode_Xor +12: SKBlendMode_Plus (The conventional belding mode) +13: SKBlendMode_Modulate +14: SRC org +15: DST org +Others: Reserved. + 8 + 4 + read-write + + + FORMAT + Output buffer format. +0x0 ARGB8888 - 32-bit pixles, byte sequence as B,G,R,A +0xE RGB565 - 16-bit pixels, byte sequence as B,R +0x12 UYVY1P422 - 16-bit pixels (1-plane , byte sequence as U0,Y0,V0,Y1) + 0 + 6 + read-write + + + + + OUT_BUF + Output buffer address + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + Current address pointer for the output frame buffer. The address can have any byte alignment. 64B alignment is recommended for optimal performance. + 0 + 32 + read-write + + + + + OUT_PITCH + Outlayer Pitch Register + 0x14 + 32 + 0x00000000 + 0x0000FFFF + + + BYTELEN + Indicates the number of bytes in memory between two vertically adjacent pixels. + 0 + 16 + read-write + + + + + OUT_LRC + Output Lower Right Corner Register + 0x18 + 32 + 0x00000000 + 0x3FFF3FFF + + + Y + This field indicates the lower right Y-coordinate (in pixels) of the output frame buffer. +The value is the height of the output image size. + 16 + 14 + read-write + + + X + This field indicates the lower right X-coordinate (in pixels) of the output frame buffer. +Should be the width of the output image size. + 0 + 14 + read-write + + + + + 2 + 0x8 + 0,1 + OUT_PS[%s] + no description available + 0x1c + + ULC + Layer Upper Left Corner Register + 0x0 + 32 + 0x00000000 + 0x3FFF3FFF + + + Y + This field indicates the upper left Y-coordinate (in pixels) of the processed surface in the output frame buffer. + 16 + 14 + read-write + + + X + This field indicates the upper left X-coordinate (in pixels) of the processed surface in the output frame buffer. + 0 + 14 + read-write + + + + + LRC + Layer Lower Right Corner Register + 0x4 + 32 + 0x00000000 + 0x3FFF3FFF + + + Y + This field indicates the lower right Y-coordinate (in pixels) of the processed surface in the output frame buffer. + 16 + 14 + read-write + + + X + This field indicates the lower right X-coordinate (in pixels) of the processed surface in the output frame buffer. + 0 + 14 + read-write + + + + + + 2 + 0x30 + 0,1 + PS[%s] + no description available + 0x30 + + CTRL + Layer Control Register + 0x0 + 32 + 0x00000000 + 0x001FFFFF + + + INB13_SWAP + Swap bit[31:24] and bit [15:8] before pack_dir operation. + 20 + 1 + read-write + + + PACK_DIR + Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence ina byte is not changed. +2'b00: no change {A3, A2, A1, A0} +2'b01: {A2, A3, A0, A1} +2'b10: {A1, A0, A3, A2} +2'b11: {A0, A1, A2, A3} + 18 + 2 + read-write + + + BKGCL4CLR + Enable to use background color for clear area + 17 + 1 + read-write + + + YCBCR_MODE + YCbCr mode or YUV mode + 16 + 1 + read-write + + + BYPASS + Asserted to bypass the CSC stage + 15 + 1 + read-write + + + VFLIP + Indicates that the input should be flipped vertically (effect applied before rotation). + 14 + 1 + read-write + + + HFLIP + Indicates that the input should be flipped horizontally (effect applied before rotation). + 13 + 1 + read-write + + + ROTATE + Indicates the clockwise rotation to be applied at the input buffer. The rotation effect is defined as occurring +after the FLIP_X and FLIP_Y permutation. +0x0 ROT_0 +0x1 ROT_90 +0x2 ROT_180 +0x3 ROT_270 + 11 + 2 + read-write + + + DECY + Verticle pre decimation filter control. +0x0 DISABLE - Disable pre-decimation filter. +0x1 DECY2 - Decimate PS by 2. +0x2 DECY4 - Decimate PS by 4. +0x3 DECY8 - Decimate PS by 8. + 9 + 2 + read-write + + + DECX + Horizontal pre decimation filter control. +0x0 DISABLE - Disable pre-decimation filter. +0x1 DECX2 - Decimate PS by 2. +0x2 DECX4 - Decimate PS by 4. +0x3 DECX8 - Decimate PS by 8. + 7 + 2 + read-write + + + HW_BYTE_SWAP + Swap bytes in half-words. For each 16 bit half-word, the two bytes will be swapped. + 6 + 1 + read-write + + + FORMAT + PS buffer format. To select between YUV and YCbCr formats, see bit 16 of this register. +0x0 ARGB888 - 32-bit pixels, byte sequence as B,G,R,A +0xE RGB565 - 16-bit pixels, byte sequence as B,R +0x13 YUYV1P422 - 16-bit pixels (1-plane byte sequence Y0,U0,Y1,V0 interleaved bytes) + 0 + 6 + read-write + + + + + BUF + Layer data buffer address + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + Address pointer for the PS RGB or Y (luma) input buffer. + 0 + 32 + read-write + + + + + PITCH + Layer data pitch register + 0x10 + 32 + 0x00000000 + 0x0000FFFF + + + BYTELEN + Indicates the number of bytes in memory between two vertically adjacent pixels. + 0 + 16 + read-write + + + + + BKGD + Layer background color register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + COLOR + Background color (in 32bpp format) for any pixels not within the scaled range of the picture, but within the buffer range specified by the PS ULC/LRC. The top 8-bit is the alpha channel. + 0 + 32 + read-write + + + + + SCALE + Layer scale register + 0x18 + 32 + 0x00000000 + 0x7FFF7FFF + + + Y + This is a two bit integer and 12 bit fractional representation (##.####_####_####) of the X scaling factor for the PS source buffer. The maximum value programmed should be 2 since scaling down by a factor greater than 2 is not supported with the bilinear filter. Decimation and the bilinear filter should be used together to achieve scaling by more than a factor of 2. + 16 + 15 + read-write + + + X + This is a two bit integer and 12 bit fractional representation (##.####_####_####) of the Y scaling factor for the PS source buffer. The maximum value programmed should be 2 since scaling down by a factor greater than 2 is not supported with the bilinear filter. Decimation and the bilinear filter should be used together to achieve scaling by more than a factor of 2. + 0 + 15 + read-write + + + + + OFFSET + Layer offset register + 0x1c + 32 + 0x00000000 + 0x0FFF0FFF + + + Y + This is a 12 bit fractional representation (0.####_####_####) of the Y scaling offset. This represents a fixed pixel offset which gets added to the scaled address to determine source data for the scaling engine. +It is applied after the decimation filter stage, and before the bilinear filter stage. + 16 + 12 + read-write + + + X + This is a 12 bit fractional representation (0.####_####_####) of the X scaling offset. This represents a fixed pixel offset which gets added to the scaled address to determine source data for the scaling engine. +It is applied after the decimation filter stage, and before the bilinear filter stage. + 0 + 12 + read-write + + + + + CLRKEY_LOW + Layer low color key register + 0x20 + 32 + 0x00000000 + 0x00FFFFFF + + + LIMIT + Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. + 0 + 24 + read-write + + + + + CLRKEY_HIGH + Layer high color key register + 0x24 + 32 + 0x00000000 + 0x00FFFFFF + + + LIMIT + High range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000 + 0 + 24 + read-write + + + + + ORG + Layer original size register + 0x28 + 32 + 0x00000000 + 0x3FFF3FFF + + + HIGHT + The number of vertical pixels of the original frame (not -1) + 16 + 14 + read-write + + + WIDTH + The number of horizontal pixels of the original frame (not -1) + 0 + 14 + read-write + + + + + + YUV2RGB_COEF0 + YUV2RGB coefficients register 0 + 0xa0 + 32 + 0x00000000 + 0x1FFFFFFF + + + C0 + Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) + 18 + 11 + read-write + + + UV_OFFSET + Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. +YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). + 9 + 9 + read-write + + + Y_OFFSET + Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is +typically -16 (0x1F0). + 0 + 9 + read-write + + + + + YUV2RGB_COEF1 + YUV2RGB coefficients register 1 + 0xa4 + 32 + 0x00000000 + 0x07FF07FF + + + C1 + Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). + 16 + 11 + read-write + + + C4 + Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). + 0 + 11 + read-write + + + + + YUV2RGB_COEF2 + YUV2RGB coefficients register 2 + 0xa8 + 32 + 0x00000000 + 0x07FF07FF + + + C2 + Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). + 16 + 11 + read-write + + + C3 + Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). + 0 + 11 + read-write + + + + + RGB2YUV_COEF0 + RGB2YUV coefficients register 0 + 0xac + 32 + 0x00000000 + 0xFFFFFFFF + + + YCBCR_MODE + Asserted to use YCrCb mode + 31 + 1 + read-write + + + ENABLE + Asserted to enable this RGB2YUV CSC stage + 30 + 1 + read-write + + + C0 + CSC parameters C0 + 18 + 11 + read-write + + + UV_OFFSET + CSC parameters UV_OFFSET + 9 + 9 + read-write + + + Y_OFFSET + CSC parameters Y_OFFSET + 0 + 9 + read-write + + + + + RGB2YUV_COEF1 + RGB2YUV coefficients register 1 + 0xb0 + 32 + 0x00000000 + 0x07FF07FF + + + C1 + CSC parameters C1 + 16 + 11 + read-write + + + C4 + CSC parameters C4 + 0 + 11 + read-write + + + + + RGB2YUV_COEF2 + RGB2YUV coefficients register 2 + 0xb4 + 32 + 0x00000000 + 0x07FF07FF + + + C2 + CSC parameters C2 + 16 + 11 + read-write + + + C3 + CSC parameters C3 + 0 + 11 + read-write + + + + + RGB2YUV_COEF3 + RGB2YUV coefficients register 3 + 0xb8 + 32 + 0x00000000 + 0x07FF07FF + + + C6 + CSC parameters C6 + 16 + 11 + read-write + + + C5 + CSC parameters C5 + 0 + 11 + read-write + + + + + RGB2YUV_COEF4 + RGB2YUV coefficients register 4 + 0xbc + 32 + 0x00000000 + 0x07FF07FF + + + C8 + CSC parameters C8 + 16 + 11 + read-write + + + C7 + CSC parameters C7 + 0 + 11 + read-write + + + + + + + JPEG + JPEG + JPEG + 0xf1014000 + + 0x0 + 0xa0 + registers + + + + InDMA_MISC + In DMA Misc Control Register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFC + + + ARQOS + QoS for AXI read channel + 19 + 4 + read-write + + + MAX_OT + max_ot when input are RGB pixels. +For 16 bits per pixel, it can be set as 4. +For 32 bits per pixel, it will be set as 2. + 15 + 4 + read-write + + + INB13_SWAP + Swap bit[31:24] and bit [15:8] before pack dir operation. Only work for pixel data. + 14 + 1 + read-write + + + PACK_DIR + Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence in a byte is not changed. Only work for pixel data. +2'b00: no change {A3, A2, A1, A0} +2'b01: {A2, A3, A0, A1} +2'b10: {A1, A0, A3, A2} +2'b11: {A0, A1, A2, A3} + 12 + 2 + read-write + + + INDMA_RENEW + Renew In DMA. Default is to continue the write address counter when a new DMA request comes. Asserted to reset the write address counter. + 11 + 1 + read-write + + + NXT_IRQ_EN + In DMA Next Interrupt Enable + 10 + 1 + read-write + + + IN_DMA_DONE_IRQ_EN + In DMA Done enable + 9 + 1 + read-write + + + AXI_ERR_IRQ_EN + In DMA axi bus error inetrrupt enable + 8 + 1 + read-write + + + IRQ_EN + interrupt enable for all interrupt sources of In DMA module + 7 + 1 + read-write + + + IN_DMA_ID + 0: Pixel (In) +1: ECS (In) +2: Qmem +3: HuffEnc +4: HuffMin +5: HuffBase +6: HuffSymb + 4 + 3 + read-write + + + IN_DMA_REQ + Asserted to request DMA. Automatically clear after DMA is done. + 3 + 1 + read-write + + + INDMA2D + Asserted if In_DMA_ID=Pixel. + 2 + 1 + read-write + + + + + InDMABase + In DMA Buf Address + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + Y plane (or Encoded Bit Plane) + 0 + 32 + read-write + + + + + InDMA_Ctrl0 + In DMA Buf Control 0 Register + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + TTLEN + Total length (Low 16 bits) in Bytes -1 for transfer when In_DMA_ID!=Pixel. + 16 + 16 + read-write + + + PITCH + Pitch between the starting point of Rows. Only active when In_DMA_ID=Pixel.. + 0 + 16 + read-write + + + + + InDMA_Ctrl1 + In DMA Buf Control 1 Register + 0x10 + 32 + 0x00000000 + 0x0000FFFF + + + ROWLEN + Total length (High 16 bits) in Bytes -1 for transfer. See reference in InDMA_Ctrl0[TTLEN] + 0 + 16 + read-write + + + + + INXT_CMD + In DMA Next Command Register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + The address pointing to the next command + 2 + 30 + read-write + + + OP_VALID + asserted if there is either a DATA DMA phase or NXTCMD phase. Automatically cleared. Will trigger the InDMA transfer if CFG[JPEG_EN] is 1. + 1 + 1 + read-write + + + EN + NXTCMD phase Enable Bit + 0 + 1 + read-write + + + + + OutDMA_MISC + Out DMA Misc Control Register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFC + + + AWQOS + No description available + 14 + 4 + read-write + + + PACK_DIR + Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence in a byte is not changed. All outdma data are impacted. +2'b00: no change {A3, A2, A1, A0} (This is used for ecs stream) +2'b01: {A2, A3, A0, A1} +2'b10: {A1, A0, A3, A2} +2'b11: {A0, A1, A2, A3} + 12 + 2 + read-write + + + EN_OUTCNT + Enable output counter (unit as bytes) + 11 + 1 + read-write + + + INI_OUTCNT + Asserted to ini output counter + 10 + 1 + read-write + + + ADD_ODMA_ENDINGS + Add 0xFFD9 to the ending of the odma stream when all original image pixels are processed by the encoder module. + 9 + 1 + read-write + + + NXT_IRQ_EN + Out DMA Next Interrupt Enable + 8 + 1 + read-write + + + OUT_DMA_DONE_IRQ_EN + Out DMA Done interrupt Enable + 7 + 1 + read-write + + + AXI_ERR_IRQ_EN + Out DMA axi bus error inetrrupt enable + 6 + 1 + read-write + + + IRQ_EN + interrupt enable for all interrupt sources of Out DMA module + 5 + 1 + read-write + + + OUT_DMA_ID + 0: Pixel (Out) +1: ECS (Out) + 4 + 1 + read-write + + + OUT_DMA_REQ + Asserted to enable Out DMA request + 3 + 1 + read-write + + + OUTDMA2D + Asserted if Out_DMA_ID==Pixel + 2 + 1 + read-write + + + + + OutDMABase + Out DMA Buf Address + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + Y plane (or Encoded Bit Plane) + 0 + 32 + read-write + + + + + OutDMA_Ctrl0 + Out DMA Buf Control 0 Register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + TTLEN + Total length (Low 16 bits) in Bytes -1 for transfer when Out_DMA_ID!=Pixel. If Out_DMA_ID=ECS, it can be any value greater than the length of the ECS, for example, the number of encoded bytes. + 16 + 16 + read-write + + + PITCH + Pitch between the starting point of Rows when Out_DMA_ID==Pixel + 0 + 16 + read-write + + + + + OutDMA_Ctrl1 + Out DMA Buf Control 1 Register + 0x30 + 32 + 0x00000000 + 0x0000FFFF + + + ROWLEN + Total length (High 16 bits) in Bytes -1 for transfer. See reference in OutDMA_Ctrl0[TTLEN] + 0 + 16 + read-write + + + + + ONXT_CMD + Out DMA Next Command Register + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + The address pointing to the next command + 2 + 30 + read-write + + + OP_VALID + asserted if there is either a DATA DMA phase or NXTCMD phase. Automatically cleared. Will trigger the OutDMA and NXTCMD phase transfer if CFG[JPEG_EN] is 1. + 1 + 1 + read-write + + + EN + NXTCMD phase Enable Bit + 0 + 1 + read-write + + + + + CFG + Configuration Register + 0x40 + 32 + 0x00000000 + 0xFFFFFFFF + + + JD_UVSWAP + Normally the default CbCr sequence is that Cb macro block coming before Cr macro blk. If Cr macro block is first, set this bit to 1'b1. This bit only impact the color space conversion from/to RGB. + 22 + 1 + read-write + + + CFG_IPATH_SEL + 2'b0:2-plane (Y- and UV- plane) or 1-plane (Y-only) as determined by the original data, byte sequence as Y0,Y1, or U,V +2'b01:ARGB8888, byte sequence as B,G,R,A +2'b10:RGB565, byte sequence as B,R +2'b11: YUV422H, byte sequence as Y0,U0,Y1,V0 + 20 + 2 + read-write + + + CODEC_OVER_IRQ_EN + The jpg endec process done interrupt enable + 19 + 1 + read-write + + + CODEC_RESTART_ERR_IRQ_EN + The jpg endec restart error interrupt enable + 18 + 1 + read-write + + + MEM_DEBUG_CLK_SEL + asserted to use APB clock, so that the memory contents could be read out through APB interface + 17 + 1 + read-write + + + CLKGATE + Assert this bit to gate off clock when the module is not working. If reset to zero, the internal clock is always on. + 9 + 1 + read-write + + + CFG_OPATH_SEL + 2'b0:2-plane (Y- and UV- plane) or 1-plane (Y-only) as determined by the original data, byte sequence as Y0,Y1, or U,V +2'b01:ARGB8888, byte sequence as B,G,R,A +2'b10:RGB565, byte sequence as R,B +2'b11: YUV422H1P, byte sequence as Y0,U0,Y1,V0 + 7 + 2 + read-write + + + JDATA_FORMAT + 3'b000: for 420, hy=2, vy=2, hc=1, vc=1 // 6 sub-blocks per MCU +3'b001: for 422h, hy=2, vy=1, hc=1, vc=1 // 4 sub-blocks per MCU +3'b010: for 422v, hy=1, vy=2, hc=1, vc=1 // 4 sub-blocks per MCU +3'b011: for 444, hy=1, vy=1, hc=1, vc=1 // 3 sub-blocks per MCU +3'b100: for 400, hy=2, vy=2, hc=0, vc=0 // 4 sub-blocks per MCU +Others: Undefined + 4 + 3 + read-write + + + JPEG_SFTRST + Software Reset + 3 + 1 + read-write + + + START + Asserted if to start a new encoder/decoder conversion. +It will at first stop the inner JPEG module, then reset it, and then re-run it. +It is a different mode from DMA phase mode. +It cannot be configured in the DMA chain descriptor. It should be configured by the core processor. +Auto clear. + 2 + 1 + read-write + + + MODE + 1: decoder, 0:encoder + 1 + 1 + read-write + + + JPEG_EN + 1b - Enabled + 0 + 1 + read-write + + + + + STAT + Status Register + 0x44 + 32 + 0x00000000 + 0xFFFFBFFE + + + BUSY + When 1 means that the module is busy doing conversion and data transfer. + 31 + 1 + read-only + + + AXI_ERR_ID + the axi err id + 10 + 4 + read-only + + + AXI_READ_ERR + in-dma axi bus error + 9 + 1 + read-only + + + AXI_WRITE_ERR + out-dma axi bus error + 8 + 1 + read-only + + + AXI_ERR + axi bus error + 7 + 1 + write-only + + + ONXT_IRQ + OutDMA next interrupt + 6 + 1 + write-only + + + INXT_IRQ + InDMA next interrupt + 5 + 1 + write-only + + + OUT_DMA_TRANSFER_DONE + OutDMA process done + 4 + 1 + write-only + + + IN_DMA_TRANSFER_DONE + InDMA process done + 3 + 1 + write-only + + + CODEC_OVER + Coding or decoding process is over. DMA is not included. +The module is completely not busy only when in_dma_transfer_done and out_dma_transfer_done, and codec_over are all asserted. + 2 + 1 + write-only + + + RESTART_MARKER_ERROR + codec restart marker error interrupt + 1 + 1 + write-only + + + + + Width + Image width register + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + IMG + Image Width (it is the max index of pixel counting from 0, assuming the top left pixel is indexed as [0,0]) + 0 + 16 + read-write + + + + + Height + Image height register + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + IMG + Image Height (it is the max index of pixel counting from 0, assuming the top left pixel is indexed as [0,0]) + 0 + 16 + read-write + + + + + BufAddr + Buf Access Addr + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + ADDR[31:28] denotes the buffer type: +0x2: Qmem +0x3: HuffEnc +0x4: HuffMin +0x5: HuffBase +0x6: HuffSymb +ADDR[27:0] is the address inside the buffer + 0 + 32 + read-write + + + + + BufData + Buf Access Data + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + The data write-to/read-from buffer. +The n-th address read will be actually the data written for n-1 th address, and the actual stored location is n-1 th address. + 0 + 32 + read-write + + + + + OutDMACnt + Out DMA Bytes Counter + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + The out DMA counter + 0 + 32 + read-only + + + + + CSC_COEF0 + YUV2RGB coefficients Register 0 + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + YCBCR_MODE + This bit changes the behavior when performing U/V converting. +0b - Converting YUV to RGB data +1b - Converting YCbCr to RGB data + 31 + 1 + read-write + + + ENABLE + Enable the CSC unit. +0b - The CSC is bypassed +1b - The CSC is enabled + 30 + 1 + read-write + + + C0 + Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) + 18 + 11 + read-write + + + UV_OFFSET + Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. +YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). + 9 + 9 + read-write + + + Y_OFFSET + Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is +typically -16 (0x1F0). + 0 + 9 + read-write + + + + + CSC_COEF1 + YUV2RGB coefficients Register 1 + 0x60 + 32 + 0x00000000 + 0xFFFFFFFF + + + C1 + Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). + 16 + 11 + read-write + + + C4 + Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). + 0 + 11 + read-write + + + + + CSC_COEF2 + YUV2RGB coefficients Register 2 + 0x64 + 32 + 0x00000000 + 0xFFFFFFFF + + + C2 + Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). + 16 + 11 + read-write + + + C3 + Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). + 0 + 11 + read-write + + + + + RGB2YUV_COEF0 + RGB2YUV coefficients Register 0 + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + YCBCR_MODE + Asserted to use YCrCb mode. Must be assigned as 1. + 31 + 1 + read-write + + + ENABLE + Asserted to enable this RGB2YCbCr CSC stage + 30 + 1 + read-write + + + C0 + CSC parameters C0 + 18 + 11 + read-write + + + UV_OFFSET + CSC parameters UV_OFFSET + 9 + 9 + read-write + + + Y_OFFSET + CSC parameters Y_OFFSET + 0 + 9 + read-write + + + + + RGB2YUV_COEF1 + RGB2YUV coefficients Register 1 + 0x6c + 32 + 0x00000000 + 0xFFFFFFFF + + + C1 + CSC parameters C1 + 16 + 11 + read-write + + + C4 + CSC parameters C4 + 0 + 11 + read-write + + + + + RGB2YUV_COEF2 + RGB2YUV coefficients Register 2 + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + C2 + CSC parameters C2 + 16 + 11 + read-write + + + C3 + CSC parameters C3 + 0 + 11 + read-write + + + + + RGB2YUV_COEF3 + RGB2YUV coefficients Register 3 + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + C6 + CSC parameters C6 + 16 + 11 + read-write + + + C5 + CSC parameters C5 + 0 + 11 + read-write + + + + + RGB2YUV_COEF4 + RGB2YUV coefficients Register 4 + 0x78 + 32 + 0x00000000 + 0xFFFFFFFF + + + C8 + CSC parameters C8 + 16 + 11 + read-write + + + C7 + CSC parameters C7 + 0 + 11 + read-write + + + + + ImgReg1 + Image Control Register 1 + 0x84 + 32 + 0x00000000 + 0xFFFFFFF7 + + + RE + Encoder Use only. +Asseted to enable the Restart Marker processing. A Restart Marker is inserted in the outputted ECS (Entropy Coded Segment) every NRST+1 MCUs + 2 + 1 + read-write + + + NCOL + Ncol is the number of color components in the image data to process minus 1. For example, for a grayscale image Ncol=0, for an RGB image, Ncol=2 + 0 + 2 + read-write + + + + + ImgReg2 + Image Control Register 2 + 0x88 + 32 + 0x00000000 + 0xFFFFFFFF + + + NMCU + Encoder Use only. +The number of NMCU to be generated in encoder mode + 0 + 26 + read-write + + + + + ImgReg3 + Image Control Register 3 + 0x8c + 32 + 0x00000000 + 0xFFFFFFFF + + + NRST + Encoder use only. +It is the number of MCUs between two Restart Markers (if enabled) minus 1. The content of this register is ignored if the Re bit inregister 1 is not set. + 0 + 16 + read-write + + + + + 4 + 0x4 + Reg40,Reg41,Reg42,Reg43 + IMGREG[%s] + no description available + 0x90 + 32 + 0x00000000 + 0xFFFFFFFF + + + NBLOCK + Encoder use only. +The number of data units (8x8 blocks of data) of the color componet contained in the MCU minus 1. + 4 + 4 + read-write + + + QT + Encoder use only. +The selection of the quantization table. + 2 + 2 + read-write + + + HA + Encoder use only. +The selection of the Huffman table for the encoding of the AC coefficients in the data units belonging to the color component. + 1 + 1 + read-write + + + HD + Encoder use only. +The selection of the Huffman table for the encoding of the DC coefficients in the data units belonging to the color component. + 0 + 1 + read-write + + + + + + + ENET0 + ENET0 + ENET + 0xf2000000 + + 0x0 + 0x1058 + registers + + + + MACCFG + MAC Configuration Register + 0x0 + 32 + 0x00000000 + 0x7FFFFFFF + + + SARC + Source Address Insertion or Replacement Control + This field controls the source address insertion or replacement for all transmitted frames. Bit 30 specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits [29:28]: +- 2'b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field generation. +- 2'b10: - If Bit 30 is set to 0, the MAC inserts the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, the MAC inserts the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. +- 2'b11: - If Bit 30 is set to 0, the MAC replaces the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, the MAC replaces the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. Note: - Changes to this field take effect only on the start of a frame. If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, that is, the current frame does not use the updated value. - These bits are reserved and RO when the Enable SA, VLAN, and CRC Insertion on TX feature is not selected during core configuration. + 28 + 3 + read-write + + + TWOKPE + IEEE 802.3as Support for 2K Packets + When set, the MAC considers all frames, with up to 2,000 bytes length, as normal packets. When Bit 20 (JE) is not set, the MAC considers all received frames of size more than 2K bytes as Giant frames. When this bit is reset and Bit 20 (JE) is not set, the MAC considers all received frames of size more than 1,518 bytes (1,522 bytes for tagged) as Giant frames. When Bit 20 is set, setting this bit has no effect on Giant Frame status. + 27 + 1 + read-write + + + SFTERR + SMII Force Transmit Error + When set, this bit indicates to the PHY to force a transmit error in the SMII frame being transmitted. This bit is reserved if the SMII PHY port is not selected during core configuration. + 26 + 1 + read-write + + + CST + CRC Stripping for Type Frames + When this bit is set, the last 4 bytes (FCS) of all frames of Ether type (Length/Type field greater than or equal to 1,536) are stripped and dropped before forwarding the frame to the application. This function is not valid when the IP Checksum Engine (Type 1) is enabled in the MAC receiver. This function is valid when Type 2 Checksum Offload Engine is enabled. + 25 + 1 + read-write + + + TC + Transmit Configuration in RGMII, SGMII, or SMII + When set, this bit enables the transmission of duplex mode, link speed, and link up or down information to the PHY in the RGMII, SMII, or SGMII port. When this bit is reset, no such information is driven to the PHY. This bit is reserved (and RO) if the RGMII, SMII, or SGMII PHY port is not selected during core configuration. + 24 + 1 + read-write + + + WD + Watchdog Disable + When this bit is set, the MAC disables the watchdog timer on the receiver. The MAC can receive frames of up to 16,383 bytes. + 23 + 1 + read-write + + + JD + Jabber Disable + When this bit is set, the MAC disables the jabber timer on the transmitter. The MAC can transfer frames of up to 16,383 bytes. When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission. + 22 + 1 + read-write + + + BE + Frame Burst Enable + When this bit is set, the MAC allows frame bursting during transmission in the GMII half-duplex mode. This bit is reserved (and RO) in the 10/100 Mbps only or full-duplex-only configurations. + 21 + 1 + read-write + + + JE + Jumbo Frame Enable + When this bit is set, the MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status. + 20 + 1 + read-write + + + IFG + Inter-Frame Gap + These bits control the minimum IFG between frames during transmission. +- 000: 96 bit times +- 001: 88 bit times +- 010: 80 bit times - ... +- 111: 40 bit times In the half-duplex mode, the minimum IFG can be configured only for 64 bit times (IFG = 100). Lower values are not considered. In the 1000-Mbps mode, the minimum IFG supported is 64 bit times (and above) in the GMAC-CORE configuration and 80 bit times (and above) in other configurations. When a JAM pattern is being transmitted because of backpressure activation, the MAC does not consider the minimum IFG. + 17 + 3 + read-write + + + DCRS + Disable Carrier Sense During Transmission + When set high, this bit makes the MAC transmitter ignore the (G)MII CRS signal during frame transmission in the half-duplex mode. This request results in no errors generated because of Loss of Carrier or No Carrier during such transmission. When this bit is low, the MAC transmitter generates such errors because of Carrier Sense and can even abort the transmissions. + 16 + 1 + read-write + + + PS + Port Select + This bit selects the Ethernet line speed. +- 0: For 1000 Mbps operations +- 1: For 10 or 100 Mbps operations In 10 or 100 Mbps operations, this bit, along with FES bit, selects the exact line speed. In the 10/100 Mbps-only (always 1) or 1000 Mbps-only (always 0) configurations, this bit is read-only with the appropriate value. In default 10/100/1000 Mbps configuration, this bit is R_W. The mac_portselect_o or mac_speed_o[1] signal reflects the value of this bit. + 15 + 1 + read-write + + + FES + Speed + This bit selects the speed in the MII, RMII, SMII, RGMII, SGMII, or RevMII interface: +- 0: 10 Mbps +- 1: 100 Mbps This bit is reserved (RO) by default and is enabled only when the parameter SPEED_SELECT = Enabled. This bit generates link speed encoding when Bit 24 (TC) is set in the RGMII, SMII, or SGMII mode. This bit is always enabled for RGMII, SGMII, SMII, or RevMII interface. In configurations with RGMII, SGMII, SMII, or RevMII interface, this bit is driven as an output signal (mac_speed_o[0]) to reflect the value of this bit in the mac_speed_o signal. In configurations with RMII, MII, or GMII interface, you can optionally drive this bit as an output signal (mac_speed_o[0]) to reflect its value in the mac_speed_o signal. + 14 + 1 + read-write + + + DO + Disable Receive Own + When this bit is set, the MAC disables the reception of frames when the phy_txen_o is asserted in the half-duplex mode. When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting. This bit is not applicable if the MAC is operating in the full-duplex mode. This bit is reserved (RO with default value) if the MAC is configured for the full-duplex-only operation. + 13 + 1 + read-write + + + LM + Loopback Mode + When this bit is set, the MAC operates in the loopback mode at GMII or MII. The (G)MII Receive clock input (clk_rx_i) is required for the loopback to work properly, because the Transmit clock is not looped-back internally. + 12 + 1 + read-write + + + DM + Duplex Mode + When this bit is set, the MAC operates in the full-duplex mode where it can transmit and receive simultaneously. + 11 + 1 + read-write + + + IPC + Checksum Offload +When this bit is set, the MAC calculates the 16-bit one’s complement of the one’s complement sum of all received Ethernet frame payloads. It also checks whether the IPv4 Header checksum (assumed to be bytes 25–26 or 29–30 (VLAN-tagged) of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word. The MAC also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the IPv4 header) and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected). When this bit is reset, this function is disabled. When Type 2 COE is selected, this bit, when set, enables the IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking. + 10 + 1 + read-write + + + DR + Disable Retry +When this bit is set, the MAC attempts only one transmission. When a collision occurs on the GMII or MII interface, the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset, the MAC attempts retries based on the settings of the BL field (Bits [6:5]). + 9 + 1 + read-write + + + LUD + Link Up or Down + This bit indicates whether the link is up or down during the transmission of configuration in the RGMII, SGMII, or SMII interface: +- 0: Link Down +- 1: Link Up + 8 + 1 + read-write + + + ACS + Automatic Pad or CRC Stripping + When this bit is set, the MAC strips the Pad or FCS field on the incoming frames only if the value of the length field is less than 1,536 bytes. All received frames with length field greater than or equal to 1,536 bytes are passed to the application without stripping the Pad or FCS field. When this bit is reset, the MAC passes all incoming frames, without modifying them, to the Host. + 7 + 1 + read-write + + + BL + Back-Off Limit + The Back-Off limit determines the random integer number (r) of slot time delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only in the half-duplex mode and is reserved (RO) in the full-duplex-only configuration. +- 00: k= min (n, 10) +- 01: k = min (n, 8) +- 10: k = min (n, 4) +- 11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0 ≤ r < 2k + 5 + 2 + read-write + + + DC + Deferral Check + When this bit is set, the deferral check function is enabled in the MAC. The MAC issues a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status, when the transmit state machine is deferred for more than 24,288 bit times in the 10 or 100 Mbps mode. If the MAC is configured for 1000 Mbps operation or if the Jumbo frame mode is enabled in the 10 or 100 Mbps mode, the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, but it is prevented because of an active carrier sense signal (CRS) on GMII or MII. The defer time is not cumulative. For example, if the transmitter defers for 10,000 bit times because the CRS signal is active and then the CRS signal becomes inactive, the transmitter transmits and collision happens. Because of collision, the transmitter needs to back off and then defer again after back off completion. In such a scenario, the deferral timer is reset to 0 and it is restarted. + 4 + 1 + read-write + + + TE + Transmitter Enable + When this bit is set, the transmit state machine of the MAC is enabled for transmission on the GMII or MII. When this bit is reset, the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and does not transmit any further frames. + 3 + 1 + read-write + + + RE + Receiver Enable + When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the GMII or MII. When this bit is reset, the MAC receive state machine is disabled after the completion of the reception of the current frame, and does not receive any further frames from the GMII or MII. + 2 + 1 + read-write + + + PRELEN + Preamble Length for Transmit frames + These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode. +- 2'b00: 7 bytes of preamble +- 2'b01: 5 bytes of preamble +- 2'b10: 3 bytes of preamble +- 2'b11: Reserved + 0 + 2 + read-write + + + + + MACFF + MAC Frame Filter + 0x4 + 32 + 0x00000000 + 0x803087FF + + + RA + Receive All + When this bit is set, the MAC Receiver module passes all received frames, irrespective of whether they pass the address filter or not, to the Application. The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, the Receiver module passes only those frames to the Application that pass the SA or DA address filter. + 31 + 1 + read-write + + + DNTU + Drop non-TCP/UDP over IP Frames + When set, this bit enables the MAC to drop the non-TCP or UDP over IP frames. The MAC forward only those frames that are processed by the Layer 4 filter. When reset, this bit enables the MAC to forward all non-TCP or UDP over IP frames. + 21 + 1 + read-write + + + IPFE + Layer 3 and Layer 4 Filter Enable + When set, this bit enables the MAC to drop frames that do not match the enabled Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for matching, this bit does not have any effect. When reset, the MAC forwards all frames irrespective of the match status of the Layer 3 and Layer 4 fields. + 20 + 1 + read-write + + + VTFE + VLAN Tag Filter Enable + When set, this bit enables the MAC to drop VLAN tagged frames that do not match the VLAN Tag comparison. When reset, the MAC forwards all frames irrespective of the match status of the VLAN Tag. + 15 + 1 + read-write + + + HPF + Hash or Perfect Filter + When this bit is set, it configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by the HMC or HUC bits. When this bit is low and the HUC or HMC bit is set, the frame is passed only if it matches the Hash filter. + 10 + 1 + read-write + + + SAF + Source Address Filter Enable + When this bit is set, the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison fails, the MAC drops the frame. When this bit is reset, the MAC forwards the received frame to the application with updated SAF bit of the Rx Status depending on the SA address comparison. + 9 + 1 + read-write + + + SAIF + SA Inverse Filtering +When this bit is set, the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter. When this bit is reset, frames whose SA does not match the SA registers are marked as failing the SA Address filter. + 8 + 1 + read-write + + + PCF + Pass Control Frames + These bits control the forwarding of all control frames (including unicast and multicast Pause frames). +- 00: MAC filters all control frames from reaching the application. +- 01: MAC forwards all control frames except Pause frames to application even if they fail the Address filter. +- 10: MAC forwards all control frames to application even if they fail the Address Filter. +- 11: MAC forwards control frames that pass the Address Filter. The following conditions should be true for the Pause frames processing: - Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register 6 (Flow Control Register) to 1. - Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register 6 (Flow Control Register) is set. - Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001. Note: This field should be set to 01 only when the Condition 1 is true, that is, the MAC is programmed to operate in the full-duplex mode and the RFE bit is enabled. Otherwise, the Pause frame filtering may be inconsistent. When Condition 1 is false, the Pause frames are considered as generic control frames. Therefore, to pass all control frames (including Pause frames) when the full-duplex mode and flow control is not enabled, you should set the PCF field to 10 or 11 (as required by the application). + 6 + 2 + read-write + + + DBF + Disable Broadcast Frames + When this bit is set, the AFM module blocks all incoming broadcast frames. In addition, it overrides all other filter settings. When this bit is reset, the AFM module passes all received broadcast frames. + 5 + 1 + read-write + + + PM + Pass All Multicast +When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. When reset, filtering of multicast frame depends on HMC bit. + 4 + 1 + read-write + + + DAIF + DA Inverse Filtering + When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. When reset, normal filtering of frames is performed. + 3 + 1 + read-write + + + HMC + Hash Multicast +When set, the MAC performs destination address filtering of received multicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers. + 2 + 1 + read-write + + + HUC + Hash Unicast + When set, the MAC performs destination address filtering of unicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers. + 1 + 1 + read-write + + + PR + Promiscuous Mode +When this bit is set, the Address Filter module passes all incoming frames irrespective of the destination or source address. The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR is set. + 0 + 1 + read-write + + + + + HASH_H + Hash Table High Register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + HTH + Hash Table High + This field contains the upper 32 bits of the Hash table. + 0 + 32 + read-write + + + + + HASH_L + Hash Table Low Register + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + HTL + Hash Table Low + This field contains the lower 32 bits of the Hash table. + 0 + 32 + read-write + + + + + GMII_ADDR + GMII Address Register + 0x10 + 32 + 0x00000000 + 0x0000FFFF + + + PA + Physical Layer Address + This field indicates which of the 32 possible PHY devices are being accessed. For RevMII, this field gives the PHY Address of the RevMII module. + 11 + 5 + read-write + + + GR + GMII Register + These bits select the desired GMII register in the selected PHY device. For RevMII, these bits select the desired CSR register in the RevMII Registers set. + 6 + 5 + read-write + + + CR + CSR Clock Range + The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design. The CSR clock corresponding to different GMAC configurations is given in Table 9-2 on page 564. The suggested range of CSR clock frequency applicable for each value (when Bit[5] = 0) ensures that the MDC clock is approximately between the frequency range 1.0 MHz–2.5 MHz. +- 0000: The CSR clock frequency is 60–100 MHz and the MDC clock frequency is CSR clock/42. +- 0001: The CSR clock frequency is 100–150 MHz and the MDC clock frequency is CSR clock/62. +- 0010: The CSR clock frequency is 20–35 MHz and the MDC clock frequency is CSR clock/16. +- 0011: The CSR clock frequency is 35–60 MHz and the MDC clock frequency is CSR clock/26. +- 0100: The CSR clock frequency is 150–250 MHz and the MDC clock frequency is CSR clock/102. +- 0101: The CSR clock frequency is 250–300 MHz and the MDC clock is CSR clock/124. +- 0110, 0111: Reserved When Bit 5 is set, you can achieve higher frequency of the MDC clock than the frequency limit of 2.5 MHz (specified in the IEEE Std 802.3) and program a clock divider of lower value. For example, when CSR clock is of 100 MHz frequency and you program these bits as 1010, then the resultant MDC clock is of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. Program the following values only if the interfacing chips support faster MDC clocks. +- 1000: CSR clock/4 +- 1001: CSR clock/6 +- 1010: CSR clock/8 +- 1011: CSR clock/10 +- 1100: CSR clock/12 +- 1101: CSR clock/14 +- 1110: CSR clock/16 +- 1111: CSR clock/18 These bits are not used for accessing RevMII. These bits are read-only if the RevMII interface is selected as single PHY interface. + 2 + 4 + read-write + + + GW + GMII Write + When set, this bit indicates to the PHY or RevMII that this is a Write operation using the GMII Data register. If this bit is not set, it indicates that this is a Read operation, that is, placing the data in the GMII Data register. + 1 + 1 + read-write + + + GB + GMII Busy + This bit should read logic 0 before writing to Register 4 and Register 5. During a PHY or RevMII register access, the software sets this bit to 1’b1 to indicate that a Read or Write access is in progress. Register 5 is invalid until this bit is cleared by the MAC. Therefore, Register 5 (GMII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. Similarly for a read operation, the contents of Register 5 are not valid until this bit is cleared. The subsequent read or write operation should happen only after the previous operation is complete. Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed, there is no change in the functionality of this bit even when the PHY is not present. + 0 + 1 + read-write + + + + + GMII_DATA + GMII Data Register + 0x14 + 32 + 0x00000000 + 0x0000FFFF + + + GD + GMII Data + This field contains the 16-bit data value read from the PHY or RevMII after a Management Read operation or the 16-bit data value to be written to the PHY or RevMII before a Management Write operation. + 0 + 16 + read-write + + + + + FLOWCTRL + Flow Control Register + 0x18 + 32 + 0x00000000 + 0xFFFF00BF + + + PT + Pause Time + This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the (G)MII clock domain, then consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain. + 16 + 16 + read-write + + + DZPQ + Disable Zero-Quanta Pause + When this bit is set, it disables the automatic generation of the Zero-Quanta Pause frames on the de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i/mti_flowctrl_i). When this bit is reset, normal operation with automatic Zero-Quanta Pause frame generation is enabled. + 7 + 1 + read-write + + + PLT + Pause Low Threshold + This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause frame. The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = 100H (256 slot-times), and PLT = 01, then a second Pause frame is automatically transmitted if the mti_flowctrl_i signal is asserted at 228 (256 – 28) slot times after the first Pause frame is transmitted. The following list provides the threshold values for different values: +- 00: The threshold is Pause time minus 4 slot times (PT – 4 slot times). +- 01: The threshold is Pause time minus 28 slot times (PT – 28 slot times). +- 10: The threshold is Pause time minus 144 slot times (PT – 144 slot times). +- 11: The threshold is Pause time minus 256 slot times (PT – 256 slot times). The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the GMII or MII interface. + 4 + 2 + read-write + + + UP + Unicast Pause Frame Detect A pause frame is processed when it has the unique multicast address specified in the IEEE Std 802.3. When this bit is set, the MAC can also detect Pause frames with unicast address of the station. This unicast address should be as specified in the MAC Address0 High Register and MAC Address0 Low Register. When this bit is reset, the MAC only detects Pause frames with unique multicast address. + 3 + 1 + read-write + + + RFE + Receive Flow Control Enable + When this bit is set, the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause) time. When this bit is reset, the decode function of the Pause frame is disabled. + 2 + 1 + read-write + + + TFE + Transmit Flow Control Enable +In the full-duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC does not transmit any Pause frames. In the half-duplex mode, when this bit is set, the MAC enables the backpressure operation. When this bit is reset, the backpressure feature is disabled. + 1 + 1 + read-write + + + FCB_BPA + Flow Control Busy or Backpressure Activate + This bit initiates a Pause frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set. In the full-duplex mode, this bit should be read as 1'b0 before writing to the Flow Control register. To initiate a Pause frame, the Application must set this bit to 1'b1. During a transfer of the Control Frame, this bit continues to be set to signify that a frame transmission is in progress. After the completion of Pause frame transmission, the MAC resets this bit to 1'b0. The Flow Control register should not be written to until this bit is cleared. In the half-duplex mode, when this bit is set (and TFE is set), then backpressure is asserted by the MAC. During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. This control register bit is logically ORed with the mti_flowctrl_i input signal for the backpressure function. When the MAC is configured for the full-duplex mode, the BPA is automatically disabled. + 0 + 1 + read-write + + + + + VLAN_TAG + VLAN Tag Register + 0x1c + 32 + 0x00000000 + 0x000FFFFF + + + VTHM + VLAN Tag Hash Table Match Enable + When set, the most significant four bits of the VLAN tag’s CRC are used to index the content of Register 354 (VLAN Hash Table Register). A value of 1 in the VLAN Hash Table register, corresponding to the index, indicates that the frame matched the VLAN hash table. When Bit 16 (ETV) is set, the CRC of the 12-bit VLAN Identifier (VID) is used for comparison whereas when ETV is reset, the CRC of the 16-bit VLAN tag is used for comparison. When reset, the VLAN Hash Match operation is not performed. + 19 + 1 + read-write + + + ESVL + Enable S-VLAN + When this bit is set, the MAC transmitter and receiver also consider the S-VLAN (Type = 0x88A8) frames as valid VLAN tagged frames. + 18 + 1 + read-write + + + VTIM + VLAN Tag Inverse Match Enable +When set, this bit enables the VLAN Tag inverse matching. The frames that do not have matching VLAN Tag are marked as matched. When reset, this bit enables the VLAN Tag perfect matching. The frames with matched VLAN Tag are marked as matched. + 17 + 1 + read-write + + + ETV + Enable 12-Bit VLAN Tag Comparison + When this bit is set, a 12-bit VLAN identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag. Bits [11:0] of VLAN tag are compared with the corresponding field in the received VLAN-tagged frame. Similarly, when enabled, only 12 bits of the VLAN tag in the received frame are used for hash-based VLAN filtering. When this bit is reset, all 16 bits of the 15th and 16th bytes of the received VLAN frame are used for comparison and VLAN hash filtering. + 16 + 1 + read-write + + + VL + VLAN Tag Identifier for Receive Frames + This field contains the 802.1Q VLAN tag to identify the VLAN frames and is compared to the 15th and 16th bytes of the frames being received for VLAN frames. The following list describes the bits of this field: - Bits [15:13]: User Priority - Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) - Bits[11:0]: VLAN tag’s VLAN Identifier (VID) field When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison. If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and 16th bytes for VLAN tag comparison, and declares all frames with a Type field value of 0x8100 or 0x88a8 as VLAN frames. + 0 + 16 + read-write + + + + + RWKFRMFILT + Remote Wake-Up Frame Filter Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + WKUPFRMFILT + This is the address through which the application writes or reads the remote wake-up frame filter registers (wkupfmfilter_reg). The wkupfmfilter_reg register is a pointer to eight wkupfmfilter_reg registers. The wkupfmfilter_reg register is loaded by sequentially loading the eight register values. Eight sequential writes to this address (0x0028) write all wkupfmfilter_reg registers. Similarly, eight sequential reads from this address (0x0028) read all wkupfmfilter_reg registers + 0 + 32 + read-write + + + + + PMT_CSR + PMT Control and Status Register + 0x2c + 32 + 0x00000000 + 0x9F000267 + + + RWKFILTRST + Remote Wake-Up Frame Filter Register Pointer Reset +When this bit is set, it resets the remote wake-up frame filter register pointer to 3’b000. It is automatically cleared after 1 clock cycle. + 31 + 1 + read-write + + + RWKPTR + Remote Wake-up FIFO Pointer +This field gives the current value (0 to 31) of the Remote Wake-up Frame filter register pointer. When the value of this pointer is equal to 7, 15, 23 or 31, the contents of the Remote Wake-up Frame Filter Register are transferred to the clk_rx_i domain when a write occurs to that register. The maximum value of the pointer is 7, 15, 23 and 31 respectively depending on the number of Remote Wakeup Filters selected during configuration. + 24 + 5 + read-write + + + GLBLUCAST + Global Unicast +When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a remote wake-up frame. + 9 + 1 + read-write + + + RWKPRCVD + Remote Wake-Up Frame Received +When set, this bit indicates the power management event is generated because of the reception of a remote wake-up frame. This bit is cleared by a Read into this register. + 6 + 1 + read-write + + + MGKPRCVD + Magic Packet Received +When set, this bit indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared by a Read into this register. + 5 + 1 + read-write + + + RWKPKTEN + Remote Wake-Up Frame Enable +When set, enables generation of a power management event because of remote wake-up frame reception. + 2 + 1 + read-write + + + MGKPKTEN + Magic Packet Enable +When set, enables generation of a power management event because of magic packet reception. + 1 + 1 + read-write + + + PWRDWN + Power Down +When set, the MAC receiver drops all received frames until it receives the expected magic packet or remote wake-up frame. This bit is then self-cleared and the power-down mode is disabled. The Software can also clear this bit before the expected magic packet or remote wake-up frame is received. The frames, received by the MAC after this bit is cleared, are forwarded to the application. This bit must only be set when the Magic Packet Enable, Global Unicast, or Remote Wake-Up Frame Enable bit is set high. Note: You can gate-off the CSR clock during the power-down mode. However, when the CSR clock is gated-off, you cannot perform any read or write operations on this register. Therefore, the Software cannot clear this bit. + 0 + 1 + read-write + + + + + LPI_CSR + LPI Control and Status Register + 0x30 + 32 + 0x00000000 + 0x000F030F + + + LPITXA + LPI TX Automate +This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the transmit side. This bit is not functional in the GMAC-CORE configuration in which the Tx clock gating is done during the LPI mode. If the LPITXA and LPIEN bits are set to 1, the MAC enters the LPI mode only after all outstanding frames (in the core) and pending frames (in the application interface) have been transmitted. The MAC comes out of the LPI mode when the application sends any frame for transmission or the application issues a TX FIFO Flush command. In addition, the MAC automatically clears the LPIEN bit when it exits the LPI state. If TX FIFO Flush is set in Bit 20 of Register 6 (Operation Mode Register), when the MAC is in the LPI mode, the MAC exits the LPI mode. When this bit is 0, the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode. + 19 + 1 + read-write + + + PLSEN + PHY Link Status Enable +This bit enables the link status received on the RGMII, SGMII, or SMII receive paths to be used for activating the LPI LS TIMER. When set, the MAC uses the link-status bits of Register 54 (SGMII/RGMII/SMII Control and Status Register) and Bit 17 (PLS) for the LPI LS Timer trigger. When cleared, the MAC ignores the link-status bits of Register 54 and takes only the PLS bit. This bit is RO and reserved if you have not selected the RGMII, SGMII, or SMII PHY interface. + 18 + 1 + read-write + + + PLS + PHY Link Status +This bit indicates the link status of the PHY. The MAC Transmitter asserts the LPI pattern only when the link status is up (okay) at least for the time indicated by the LPI LS TIMER. When set, the link is considered to be okay (up) and when reset, the link is considered to be down. + 17 + 1 + read-write + + + LPIEN + LPI Enable +When set, this bit instructs the MAC Transmitter to enter the LPI state. When reset, this bit instructs the MAC to exit the LPI state and resume normal transmission. This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission. + 16 + 1 + read-write + + + RLPIST + Receive LPI State +When set, this bit indicates that the MAC is receiving the LPI pattern on the GMII or MII interface. + 9 + 1 + read-write + + + TLPIST + Transmit LPI State +When set, this bit indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface. + 8 + 1 + read-write + + + RLPIEX + Receive LPI Exit +When set, this bit indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the normal reception. This bit is cleared by a read into this register. Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. + 3 + 1 + read-write + + + RLPIEN + Receive LPI Entry +When set, this bit indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register. Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. + 2 + 1 + read-write + + + TLPIEX + Transmit LPI Exit +When set, this bit indicates that the MAC transmitter has exited the LPI state after the user has cleared the LPIEN bit and the LPI TW Timer has expired. This bit is cleared by a read into this register. + 1 + 1 + read-write + + + TLPIEN + Transmit LPI Entry + When set, this bit indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register. + 0 + 1 + read-write + + + + + LPI_TCR + LPI Timers Control Register + 0x34 + 32 + 0x00000000 + 0x03FFFFFF + + + LST + LPI LS TIMER +This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count. The default value of the LPI LS Timer is 1000 (1 sec) as defined in the IEEE standard. + 16 + 10 + read-write + + + TWT + LPI TW TIMER +This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission. The TLPIEX status bit is set after the expiry of this timer. + 0 + 16 + read-write + + + + + INTR_STATUS + Interrupt Status Register + 0x38 + 32 + 0x00000000 + 0x00000EFF + + + GPIIS + GPI Interrupt Status +When the GPIO feature is enabled, this bit is set when any active event (LL or LH) occurs on the GPIS field (Bits [3:0]) of Register 56 (General Purpose IO Register) and the corresponding GPIE bit is enabled. This bit is cleared on reading lane 0 (GPIS) of Register 56 (General Purpose IO Register). When the GPIO feature is not enabled, this bit is reserved. + 11 + 1 + read-only + + + LPIIS + LPI Interrupt Status +When the Energy Efficient Ethernet feature is enabled, this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. This bit is cleared on reading Bit 0 of Register 12 (LPI Control and Status Register). In all other modes, this bit is reserved. + 10 + 1 + read-only + + + TSIS + Timestamp Interrupt Status +When the Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true: - The system time value equals or exceeds the value specified in the Target Time High and Low registers. - There is an overflow in the seconds register. - The Auxiliary snapshot trigger is asserted. This bit is cleared on reading Bit 0 of Register 458 (Timestamp Status Register). + 9 + 1 + read-only + + + MMCRXIPIS + MMC Receive Checksum Offload Interrupt Status +This bit is set high when an interrupt is generated in the MMC Receive Checksum Offload Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. + 7 + 1 + read-only + + + MMCTXIS + MMC Transmit Interrupt Status +This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. + 6 + 1 + read-only + + + MMCRXIS + MMC Receive Interrupt Status +This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. + 5 + 1 + read-only + + + MMCIS + MMC Interrupt Status +This bit is set high when any of the Bits [7:5] is set high and cleared only when all of these bits are low. + 4 + 1 + read-only + + + PMTIS + PMT Interrupt Status +This bit is set when a magic packet or remote wake-up frame is received in the power-down mode (see Bits 5 and 6 in the PMT Control and Status Register). This bit is cleared when both Bits[6:5] are cleared because of a read operation to the PMT Control and Status register. + 3 + 1 + read-only + + + PCSANCIS + PCS Auto-Negotiation Complete +This bit is set when the Auto-negotiation is completed in the TBI, RTBI, or SGMII PHY interface (Bit 5 in Register 49 (AN Status Register)). This bit is cleared when you perform a read operation to the AN Status register. + 2 + 1 + read-only + + + PCSLCHGIS + PCS Link Status Changed +This bit is set because of any change in Link Status in the TBI, RTBI, or SGMII PHY interface (Bit 2 in Register 49 (AN Status Register)). This bit is cleared when you perform a read operation on the AN Status register. + 1 + 1 + read-only + + + RGSMIIIS + RGMII or SMII Interrupt Status +This bit is set because of any change in value of the Link Status of RGMII or SMII interface (Bit 3 in Register 54 (SGMII/RGMII/SMII Control and Status Register)). This bit is cleared when you perform a read operation on the SGMII/RGMII/SMII Control and Status Register. + 0 + 1 + read-only + + + + + INTR_MASK + Interrupt Mask Register + 0x3c + 32 + 0x00000000 + 0x0000060F + + + LPIIM + LPI Interrupt Mask +When set, this bit disables the assertion of the interrupt signal because of the setting of the LPI Interrupt Status bit in Register 14 (Interrupt Status Register). + 10 + 1 + read-write + + + TSIM + Timestamp Interrupt Mask + When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Register 14 (Interrupt Status Register). + 9 + 1 + read-write + + + PMTIM + PMT Interrupt Mask + When set, this bit disables the assertion of the interrupt signal because of the setting of PMT Interrupt Status bit in Register 14 (Interrupt Status Register). + 3 + 1 + read-write + + + PCSANCIM + PCS AN Completion Interrupt Mask +When set, this bit disables the assertion of the interrupt signal because of the setting of PCS Auto-negotiation complete bit in Register 14 (Interrupt Status Register). + 2 + 1 + read-write + + + PCSLCHGIM + PCS Link Status Interrupt Mask +When set, this bit disables the assertion of the interrupt signal because of the setting of the PCS Link-status changed bit in Register 14 (Interrupt Status Register). + 1 + 1 + read-write + + + RGSMIIIM + RGMII or SMII Interrupt Mask +When set, this bit disables the assertion of the interrupt signal because of the setting of the RGMII or SMII Interrupt Status bit in Register 14 (Interrupt Status Register). + 0 + 1 + read-write + + + + + MAC_ADDR_0_HIGH + MAC Address 0 High Register + 0x40 + 32 + 0x00000000 + 0x8000FFFF + + + AE + Address Enable + This bit is RO. The bit value is fixed at 1. + 31 + 1 + read-only + + + ADDRHI + MAC Address0 [47:32] + This field contains the upper 16 bits (47:32) of the first 6-byte MAC address. The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. + 0 + 16 + read-write + + + + + MAC_ADDR_0_LOW + MAC Address 0 Low Register + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDRLO + MAC Address0 [31:0] + This field contains the lower 32 bits of the first 6-byte MAC address. This is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. + 0 + 32 + read-write + + + + + 4 + 0x8 + 1,2,3,4 + MAC_ADDR[%s] + no description available + 0x48 + + HIGH + MAC Address High Register + 0x0 + 32 + 0x00000000 + 0xFF00FFFF + + + AE + Address Enable +When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. + 31 + 1 + read-write + + + SA + Source Address +When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received frame. + 30 + 1 + read-write + + + MBC + Mask Byte Control +These bits are mask control bits for comparison of each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows: - Bit 29: Register 18[15:8] - Bit 28: Register 18[7:0] - Bit 27: Register 19[31:24] - ... - Bit 24: Register 19[7:0] You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. + 24 + 6 + read-write + + + ADDRHI + MAC Address1 [47:32] +This field contains the upper 16 bits (47:32) of the second 6-byte MAC address. + 0 + 16 + read-write + + + + + LOW + MAC Address Low Register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDRLO + MAC Address1 [31:0] +This field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process. + 0 + 32 + read-write + + + + + + XMII_CSR + SGMII/RGMII/SMII Control and Status Register + 0xd8 + 32 + 0x00000000 + 0x0000003F + + + FALSCARDET + False Carrier Detected + This bit indicates whether the SMII PHY detected false carrier (1'b1). This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. + 5 + 1 + read-write + + + JABTO + Jabber Timeout + This bit indicates whether there is jabber timeout error (1'b1) in the received frame. This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. + 4 + 1 + read-write + + + LNKSTS + Link Status + This bit indicates whether the link between the local PHY and the remote PHY is up or down. It gives the status of the link between the SGMII of MAC and the SGMII of the local PHY. The status bits are received from the local PHY during ANEG betweent he MAC and PHY on the SGMII link. + 3 + 1 + read-write + + + LNKSPEED + Link Speed + This bit indicates the current speed of the link: +- 00: 2.5 MHz +- 01: 25 MHz +- 10: 125 MHz Bit 2 is reserved when the MAC is configured for the SMII PHY interface. + 1 + 2 + read-write + + + LNKMOD + Link Mode + This bit indicates the current mode of operation of the link: +- 1’b0: Half-duplex mode +- 1’b1: Full-duplex mode + 0 + 1 + read-write + + + + + WDOG_WTO + Watchdog Timeout Register + 0xdc + 32 + 0x00000000 + 0x00013FFF + + + PWE + Programmable Watchdog Enable + When this bit is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, the WTO field (Bits[13:0]) is used as watchdog timeout for a received frame. When this bit is cleared, the watchdog timeout for a received frame is controlled by the setting of Bit 23 (WD) and Bit 20 (JE) in Register 0 (MAC Configuration Register). + 16 + 1 + read-write + + + WTO + Watchdog Timeout +When Bit 16 (PWE) is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, this field is used as watchdog timeout for a received frame. If the length of a received frame exceeds the value of this field, such frame is terminated and declared as an error frame. Note: When Bit 16 (PWE) is set, the value in this field should be more than 1,522 (0x05F2). Otherwise, the IEEE Std 802.3-specified valid tagged frames are declared as error frames and are dropped. + 0 + 14 + read-write + + + + + mmc_cntrl + MMC Control establishes the operating mode of MMC. + 0x100 + 32 + 0x00000000 + 0x0000013F + + + UCDBC + Update MMC Counters for Dropped Broadcast Frames +When set, the MAC updates all related MMC Counters for Broadcast frames that are dropped because of the setting of Bit 5 (DBF) of Register 1 (MAC Frame Filter). When reset, the MMC Counters are not updated for dropped Broadcast frames. + 8 + 1 + read-write + + + CNTPRSTLVL + Full-Half Preset +When this bit is low and Bit 4 is set, all MMC counters get preset to almost-half value. All octet counters get preset to 0x7FFF_F800 (half +- 2KBytes) and all frame-counters gets preset to 0x7FFF_FFF0 (half +- 16). When this bit is high and Bit 4 is set, all MMC counters get preset to almost-full value. All octet counters get preset to 0xFFFF_F800 (full +- 2KBytes) and all frame-counters gets preset to 0xFFFF_FFF0 (full +- 16). For 16-bit counters, the almost-half preset values are 0x7800 and 0x7FF0 for the respective octet and frame counters. Similarly, the almost-full preset values for the 16-bit counters are 0xF800 and 0xFFF0. + 5 + 1 + read-write + + + CNTPRST + Counters Preset +When this bit is set, all counters are initialized or preset to almost full or almost half according to Bit 5. This bit is cleared automatically after 1 clock cycle. This bit, along with Bit 5, is useful for debugging and testing the assertion of interrupts because of MMC counter becoming half-full or full. + 4 + 1 + read-write + + + CNTFREEZ + MMC Counter Freeze +When this bit is set, it freezes all MMC counters to their current value. Until this bit is reset to 0, no MMC counter is updated because of any transmitted or received frame. If any MMC counter is read with the Reset on Read bit set, then that counter is also cleared in this mode. + 3 + 1 + read-write + + + RSTONRD + Reset on Read +When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset). The counters are cleared when the least significant byte lane (Bits[7:0]) is read. + 2 + 1 + read-write + + + CNTSTOPRO + Counter Stop Rollover +When this bit is set, the counter does not roll over to zero after reaching the maximum value. + 1 + 1 + read-write + + + CNTRST + Counters Reset +When this bit is set, all counters are reset. This bit is cleared automatically after 1 clock cycle + 0 + 1 + read-write + + + + + mmc_intr_rx + MMC Receive Interrupt maintains the interrupt generated from all +of the receive statistic counters. + 0x104 + 32 + 0x00000000 + 0x03FFFFFF + + + RXCTRLFIS + MMC Receive Control Frame Counter Interrupt Status +This bit is set when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. + 25 + 1 + read-write + + + RXRCVERRFIS + MMC Receive Error Frame Counter Interrupt Status +This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value. + 24 + 1 + read-write + + + RXWDOGFIS + MMC Receive Watchdog Error Frame Counter Interrupt Status +This bit is set when the rxwatchdog error counter reaches half of the maximum value or the maximum value. + 23 + 1 + read-write + + + RXVLANGBFIS + MMC Receive VLAN Good Bad Frame Counter Interrupt Status +This bit is set when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. + 22 + 1 + read-write + + + RXFOVFIS + MMC Receive FIFO Overflow Frame Counter Interrupt Status +This bit is set when the rxfifooverflow counter reaches half of the maximum value or the maximum value. + 21 + 1 + read-write + + + RXPAUSFIS + MMC Receive Pause Frame Counter Interrupt Status +This bit is set when the rxpauseframes counter reaches half of the maximum value or the maximum value. + 20 + 1 + read-write + + + RXORANGEFIS + MMC Receive Out Of Range Error Frame Counter Interrupt Status. +This bit is set when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. + 19 + 1 + read-write + + + RXLENERFIS + MMC Receive Length Error Frame Counter Interrupt Status +This bit is set when the rxlengtherror counter reaches half of the maximum value or the maximum value. + 18 + 1 + read-write + + + RXUCGFIS + MMC Receive Unicast Good Frame Counter Interrupt Status +This bit is set when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. + 17 + 1 + read-write + + + RX1024TMAXOCTGBFIS + MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status. +This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. + 16 + 1 + read-write + + + RX512T1023OCTGBFIS + MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. + 15 + 1 + read-write + + + RX256T511OCTGBFIS + MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. + 14 + 1 + read-write + + + RX128T255OCTGBFIS + MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. + 13 + 1 + read-write + + + RX65T127OCTGBFIS + MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. + 12 + 1 + read-write + + + RX64OCTGBFIS + MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value. + 11 + 1 + read-write + + + RXOSIZEGFIS + MMC Receive Oversize Good Frame Counter Interrupt Status +This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value. + 10 + 1 + read-write + + + RXUSIZEGFIS + MMC Receive Undersize Good Frame Counter Interrupt Status +This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value. + 9 + 1 + read-write + + + RXJABERFIS + MMC Receive Jabber Error Frame Counter Interrupt Status +This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value. + 8 + 1 + read-write + + + RXRUNTFIS + MMC Receive Runt Frame Counter Interrupt Status +This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value. + 7 + 1 + read-write + + + RXALGNERFIS + MMC Receive Alignment Error Frame Counter Interrupt Status +This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value. + 6 + 1 + read-write + + + RXCRCERFIS + MMC Receive CRC Error Frame Counter Interrupt Status +This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value. + 5 + 1 + read-write + + + RXMCGFIS + MMC Receive Multicast Good Frame Counter Interrupt Status +This bit is set when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. + 4 + 1 + read-write + + + RXBCGFIS + MMC Receive Broadcast Good Frame Counter Interrupt Status +This bit is set when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. + 3 + 1 + read-write + + + RXGOCTIS + MMC Receive Good Octet Counter Interrupt Status +This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. + 2 + 1 + read-write + + + RXGBOCTIS + MMC Receive Good Bad Octet Counter Interrupt Status +This bit is set when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. + 1 + 1 + read-write + + + RXGBFRMIS + MMC Receive Good Bad Frame Counter Interrupt Status +This bit is set when the rxframecount_gb counter reaches half of the maximum value or the maximum value. + 0 + 1 + read-write + + + + + mmc_intr_tx + MMC Transmit Interrupt maintains the interrupt generated from all +of the transmit statistic counters + 0x108 + 32 + 0x00000000 + 0x03FFFFFF + + + TXOSIZEGFIS + MMC Transmit Oversize Good Frame Counter Interrupt Status +This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value. + 25 + 1 + read-write + + + TXVLANGFIS + MMC Transmit VLAN Good Frame Counter Interrupt Status +This bit is set when the txvlanframes_g counter reaches half of the maximum value or the maximum value. + 24 + 1 + read-write + + + TXPAUSFIS + MMC Transmit Pause Frame Counter Interrupt Status +This bit is set when the txpauseframeserror counter reaches half of the maximum value or the maximum value. + 23 + 1 + read-write + + + TXEXDEFFIS + MMC Transmit Excessive Deferral Frame Counter Interrupt Status +This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value. + 22 + 1 + read-write + + + TXGFRMIS + MMC Transmit Good Frame Counter Interrupt Status +This bit is set when the txframecount_g counter reaches half of the maximum value or the maximum value. + 21 + 1 + read-write + + + TXGOCTIS + MMC Transmit Good Octet Counter Interrupt Status +This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value. + 20 + 1 + read-write + + + TXCARERFIS + MMC Transmit Carrier Error Frame Counter Interrupt Status +This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value. + 19 + 1 + read-write + + + TXEXCOLFIS + MMC Transmit Excessive Collision Frame Counter Interrupt Status +This bit is set when the txexesscol counter reaches half of the maximum value or the maximum value. + 18 + 1 + read-write + + + TXLATCOLFIS + MMC Transmit Late Collision Frame Counter Interrupt Status +This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value. + 17 + 1 + read-write + + + TXDEFFIS + MMC Transmit Deferred Frame Counter Interrupt Status +This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value. + 16 + 1 + read-write + + + TXMCOLGFIS + MMC Transmit Multiple Collision Good Frame Counter Interrupt Status +This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value. + 15 + 1 + read-write + + + TXSCOLGFIS + MMC Transmit Single Collision Good Frame Counter Interrupt Status +This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value. + 14 + 1 + read-write + + + TXUFLOWERFIS + MMC Transmit Underflow Error Frame Counter Interrupt Status +This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value. + 13 + 1 + read-write + + + TXBCGBFIS + MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status +This bit is set when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. + 12 + 1 + read-write + + + TXMCGBFIS + MMC Transmit Multicast Good Bad Frame Counter Interrupt Status +The bit is set when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. + 11 + 1 + read-write + + + TXUCGBFIS + MMC Transmit Unicast Good Bad Frame Counter Interrupt Status +This bit is set when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. + 10 + 1 + read-write + + + TX1024TMAXOCTGBFIS + MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status +This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. + 9 + 1 + read-write + + + TX512T1023OCTGBFIS + MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. + 8 + 1 + read-write + + + TX256T511OCTGBFIS + MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. + 7 + 1 + read-write + + + TX128T255OCTGBFIS + MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. + 6 + 1 + read-write + + + TX65T127OCTGBFIS + MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the tx65to127octets_gb counter reaches half the maximum value, and also when it reaches the maximum value. + 5 + 1 + read-write + + + TX64OCTGBFIS + MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value. + 4 + 1 + read-write + + + TXMCGFIS + MMC Transmit Multicast Good Frame Counter Interrupt Status +This bit is set when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. + 3 + 1 + read-write + + + TXBCGFIS + MMC Transmit Broadcast Good Frame Counter Interrupt Status +This bit is set when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. + 2 + 1 + read-write + + + TXGBFRMIS + MMC Transmit Good Bad Frame Counter Interrupt Status +This bit is set when the txframecount_gb counter reaches half of the maximum value or the maximum value. + 1 + 1 + read-write + + + TXGBOCTIS + MMC Transmit Good Bad Octet Counter Interrupt Status +This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. + 0 + 1 + read-write + + + + + mmc_intr_mask_rx + MMC Receive Interrupt mask maintains the mask for the interrupt +generated from all of the receive statistic counters + 0x10c + 32 + 0x00000000 + 0x03FFFFFE + + + RXCTRLFIM + MMC Receive Control Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. + 25 + 1 + read-write + + + RXRCVERRFIM + MMC Receive Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value. + 24 + 1 + read-write + + + RXWDOGFIM + MMC Receive Watchdog Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value. + 23 + 1 + read-write + + + RXVLANGBFIM + MMC Receive VLAN Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. + 22 + 1 + read-write + + + RXFOVFIM + MMC Receive FIFO Overflow Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value. + 21 + 1 + read-write + + + RXPAUSFIM + MMC Receive Pause Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxpauseframes counter reaches half of the maximum value or the maximum value. + 20 + 1 + read-write + + + RXORANGEFIM + MMC Receive Out Of Range Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. + 19 + 1 + read-write + + + RXLENERFIM + MMC Receive Length Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value. + 18 + 1 + read-write + + + RXUCGFIM + MMC Receive Unicast Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. + 17 + 1 + read-write + + + RX1024TMAXOCTGBFIM + MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask. +Setting this bit masks the interrupt when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. + 16 + 1 + read-write + + + RX512T1023OCTGBFIM + MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. + 15 + 1 + read-write + + + RX256T511OCTGBFIM + MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. + 14 + 1 + read-write + + + RX128T255OCTGBFIM + MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. + 13 + 1 + read-write + + + RX65T127OCTGBFIM + MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. + 12 + 1 + read-write + + + RX64OCTGBFIM + MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value. + 11 + 1 + read-write + + + RXOSIZEGFIM + MMC Receive Oversize Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value. + 10 + 1 + read-write + + + RXUSIZEGFIM + MMC Receive Undersize Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value. + 9 + 1 + read-write + + + RXJABERFIM + MMC Receive Jabber Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value. + 8 + 1 + read-write + + + RXRUNTFIM + MMC Receive Runt Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value. + 7 + 1 + read-write + + + RXALGNERFIM + MMC Receive Alignment Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value. + 6 + 1 + read-write + + + RXCRCERFIM + MMC Receive CRC Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value. + 5 + 1 + read-write + + + RXMCGFIM + MMC Receive Multicast Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. + 4 + 1 + read-write + + + RXBCGFIM + MMC Receive Broadcast Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. + 3 + 1 + read-write + + + RXGOCTIM + MMC Receive Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. + 2 + 1 + read-write + + + RXGBOCTIM + MMC Receive Good Bad Octet Counter Interrupt Mask. +Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. + 1 + 1 + read-write + + + + + mmc_intr_mask_tx + MMC Transmit Interrupt Mask + 0x110 + 32 + 0x00000000 + 0x03FFFFFF + + + TXOSIZEGFIM + MMC Transmit Oversize Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value. + 25 + 1 + read-write + + + TXVLANGFIM + MMC Transmit VLAN Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txvlanframes_g counter reaches half of the maximum value or the maximum value. + 24 + 1 + read-write + + + TXPAUSFIM + MMC Transmit Pause Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txpauseframes counter reaches half of the maximum value or the maximum value. + 23 + 1 + read-write + + + TXEXDEFFIM + MMC Transmit Excessive Deferral Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value. + 22 + 1 + read-write + + + TXGFRMIM + MMC Transmit Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txframecount_g counter reaches half of the maximum value or the maximum value. + 21 + 1 + read-write + + + TXGOCTIM + MMC Transmit Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value. + 20 + 1 + read-write + + + TXCARERFIM + MMC Transmit Carrier Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value. + 19 + 1 + read-write + + + TXEXCOLFIM + MMC Transmit Excessive Collision Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value. + 18 + 1 + read-write + + + TXLATCOLFIM + MMC Transmit Late Collision Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value. + 17 + 1 + read-write + + + TXDEFFIM + MMC Transmit Deferred Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value. + 16 + 1 + read-write + + + TXMCOLGFIM + MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value. + 15 + 1 + read-write + + + TXSCOLGFIM + MMC Transmit Single Collision Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value. + 14 + 1 + read-write + + + TXUFLOWERFIM + MMC Transmit Underflow Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value. + 13 + 1 + read-write + + + TXBCGBFIM + MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. + 12 + 1 + read-write + + + TXMCGBFIM + MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. + 11 + 1 + read-write + + + TXUCGBFIM + MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. + 10 + 1 + read-write + + + TX1024TMAXOCTGBFIM + MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. + 9 + 1 + read-write + + + TX512T1023OCTGBFIM + MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. + 8 + 1 + read-write + + + TX256T511OCTGBFIM + MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. + 7 + 1 + read-write + + + TX128T255OCTGBFIM + MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. + 6 + 1 + read-write + + + TX65T127OCTGBFIM + MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value. + 5 + 1 + read-write + + + TX64OCTGBFIM + MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value. + 4 + 1 + read-write + + + TXMCGFIM + MMC Transmit Multicast Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. + 3 + 1 + read-write + + + TXBCGFIM + MMC Transmit Broadcast Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. + 2 + 1 + read-write + + + TXGBFRMIM + MMC Transmit Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txframecount_gb counter reaches half of the maximum value or the maximum value. + 1 + 1 + read-write + + + TXGBOCTIM + MMC Transmit Good Bad Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. + 0 + 1 + read-write + + + + + txoctetcount_gb + Number of bytes transmitted, exclusive of preamble and retried +bytes, in good and bad frames. + 0x114 + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes transmitted, exclusive of preamble and retried bytes, in good and bad frames. + 0 + 32 + read-write + + + + + txframecount_gb + Number of good and bad frames transmitted, exclusive of retried +frames. + 0x118 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted, exclusive of retried frames. + 0 + 32 + read-write + + + + + txbroadcastframes_g + Number of good broadcast frames transmitted + 0x11c + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good broadcast frames transmitted. + 0 + 32 + read-write + + + + + txmlticastframes_g + Number of good multicast frames transmitted + 0x120 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good multicast frames transmitted. + 0 + 32 + read-write + + + + + tx64octets_gb + Number of good and bad frames transmitted with length 64 bytes, +exclusive of preamble and retried frames. + 0x124 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted with length 64 bytes, exclusive of preamble and retried frames. + 0 + 32 + read-write + + + + + tx65to127octets_gb + Number of good and bad frames transmitted with length between +65 and 127 (inclusive) bytes, exclusive of preamble and retried +frames. + 0x128 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 32 + read-write + + + + + tx128to255octets_gb + Number of good and bad frames transmitted with length between +128 and 255 (inclusive) bytes, exclusive of preamble and retried +frames. + 0x12c + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted with length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 32 + read-write + + + + + tx256to511octets_gb + Number of good and bad frames transmitted with length between +256 and 511 (inclusive) bytes, exclusive of preamble and retried +frames. + 0x130 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted with length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 32 + read-write + + + + + tx512to1023octets_gb + Number of good and bad frames transmitted with length between +512 and 1,023 (inclusive) bytes, exclusive of preamble and retried +frames. + 0x134 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 32 + read-write + + + + + tx1024tomaxoctets_gb + Number of good and bad frames transmitted with length between +1,024 and maxsize (inclusive) bytes, exclusive of preamble and +retried frames. + 0x138 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 32 + read-write + + + + + rxframecount_gb + Number of good and bad frames received + 0x180 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames received. + 0 + 32 + read-write + + + + + mmc_ipc_intr_mask_rx + MMC IPC Receive Checksum Offload Interrupt Mask maintains +the mask for the interrupt generated from the receive IPC statistic +counters. + 0x200 + 32 + 0x00000000 + 0x3FFF3FFF + + + RXICMPEROIM + MMC Receive ICMP Error Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. + 29 + 1 + read-write + + + RXICMPGOIM + MMC Receive ICMP Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. + 28 + 1 + read-write + + + RXTCPEROIM + MMC Receive TCP Error Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. + 27 + 1 + read-write + + + RXTCPGOIM + MMC Receive TCP Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value. + 26 + 1 + read-write + + + RXUDPEROIM + MMC Receive UDP Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. + 25 + 1 + read-write + + + RXUDPGOIM + MMC Receive IPV6 No Payload Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. + 24 + 1 + read-write + + + RXIPV6NOPAYOIM + MMC Receive IPV6 Header Error Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. + 23 + 1 + read-write + + + RXIPV6HEROIM + MMC Receive IPV6 Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. + 22 + 1 + read-write + + + RXIPV6GOIM + MMC Receive IPV6 Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. + 21 + 1 + read-write + + + RXIPV4UDSBLOIM + MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. + 20 + 1 + read-write + + + RXIPV4FRAGOIM + MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. + 19 + 1 + read-write + + + RXIPV4NOPAYOIM + MMC Receive IPV4 No Payload Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. + 18 + 1 + read-write + + + RXIPV4HEROIM + MMC Receive IPV4 Header Error Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. + 17 + 1 + read-write + + + RXIPV4GOIM + MMC Receive IPV4 Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. + 16 + 1 + read-write + + + RXICMPERFIM + MMC Receive ICMP Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. + 13 + 1 + read-write + + + RXICMPGFIM + MMC Receive ICMP Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. + 12 + 1 + read-write + + + RXTCPERFIM + MMC Receive TCP Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. + 11 + 1 + read-write + + + RXTCPGFIM + MMC Receive TCP Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. + 10 + 1 + read-write + + + RXUDPERFIM + MMC Receive UDP Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. + 9 + 1 + read-write + + + RXUDPGFIM + MMC Receive UDP Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. + 8 + 1 + read-write + + + RXIPV6NOPAYFIM + MMC Receive IPV6 No Payload Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. + 7 + 1 + read-write + + + RXIPV6HERFIM + MMC Receive IPV6 Header Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. + 6 + 1 + read-write + + + RXIPV6GFIM + MMC Receive IPV6 Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. + 5 + 1 + read-write + + + RXIPV4UDSBLFIM + MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. + 4 + 1 + read-write + + + RXIPV4FRAGFIM + MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. + 3 + 1 + read-write + + + RXIPV4NOPAYFIM + MMC Receive IPV4 No Payload Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. + 2 + 1 + read-write + + + RXIPV4HERFIM + MMC Receive IPV4 Header Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. + 1 + 1 + read-write + + + RXIPV4GFIM + MMC Receive IPV4 Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. + 0 + 1 + read-write + + + + + mmc_ipc_intr_rx + MMC Receive Checksum Offload Interrupt maintains the interrupt +that the receive IPC statistic counters generate. See Table 4-25 +for further detail. + 0x208 + 32 + 0x00000000 + 0x3FFF3FFF + + + RXICMPEROIS + MMC Receive ICMP Error Octet Counter Interrupt Status +This bit is set when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. + 29 + 1 + read-write + + + RXICMPGOIS + MMC Receive ICMP Good Octet Counter Interrupt Status +This bit is set when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. + 28 + 1 + read-write + + + RXTCPEROIS + MMC Receive TCP Error Octet Counter Interrupt Status +This bit is set when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. + 27 + 1 + read-write + + + RXTCPGOIS + MMC Receive TCP Good Octet Counter Interrupt Status +This bit is set when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value + 26 + 1 + read-write + + + RXUDPEROIS + MMC Receive UDP Error Octet Counter Interrupt Status +This bit is set when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. + 25 + 1 + read-write + + + RXUDPGOIS + MMC Receive UDP Good Octet Counter Interrupt Status +This bit is set when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. + 24 + 1 + read-write + + + RXIPV6NOPAYOIS + MMC Receive IPV6 No Payload Octet Counter Interrupt Status +This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. + 23 + 1 + read-write + + + RXIPV6HEROIS + MMC Receive IPV6 Header Error Octet Counter Interrupt Status +This bit is set when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. + 22 + 1 + read-write + + + RXIPV6GOIS + MMC Receive IPV6 Good Octet Counter Interrupt Status +This bit is set when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. + 21 + 1 + read-write + + + RXIPV4UDSBLOIS + MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status +This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. + 20 + 1 + read-write + + + RXIPV4FRAGOIS + MMC Receive IPV4 Fragmented Octet Counter Interrupt Status +This bit is set when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. + 19 + 1 + read-write + + + RXIPV4NOPAYOIS + MMC Receive IPV4 No Payload Octet Counter Interrupt Status +This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. + 18 + 1 + read-write + + + RXIPV4HEROIS + MMC Receive IPV4 Header Error Octet Counter Interrupt Status +This bit is set when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. + 17 + 1 + read-write + + + RXIPV4GOIS + MMC Receive IPV4 Good Octet Counter Interrupt Status +This bit is set when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. + 16 + 1 + read-write + + + RXICMPERFIS + MMC Receive ICMP Error Frame Counter Interrupt Status +This bit is set when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. + 13 + 1 + read-write + + + RXICMPGFIS + MMC Receive ICMP Good Frame Counter Interrupt Status +This bit is set when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. + 12 + 1 + read-write + + + RXTCPERFIS + MMC Receive TCP Error Frame Counter Interrupt Status +This bit is set when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. + 11 + 1 + read-write + + + RXTCPGFIS + MMC Receive TCP Good Frame Counter Interrupt Status +This bit is set when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. + 10 + 1 + read-write + + + RXUDPERFIS + MMC Receive UDP Error Frame Counter Interrupt Status +This bit is set when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. + 9 + 1 + read-write + + + RXUDPGFIS + MMC Receive UDP Good Frame Counter Interrupt Status +This bit is set when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. + 8 + 1 + read-write + + + RXIPV6NOPAYFIS + MMC Receive IPV6 No Payload Frame Counter Interrupt Status +This bit is set when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. + 7 + 1 + read-write + + + RXIPV6HERFIS + MMC Receive IPV6 Header Error Frame Counter Interrupt Status +This bit is set when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. + 6 + 1 + read-write + + + RXIPV6GFIS + MMC Receive IPV6 Good Frame Counter Interrupt Status +This bit is set when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. + 5 + 1 + read-write + + + RXIPV4UDSBLFIS + MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status +This bit is set when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. + 4 + 1 + read-write + + + RXIPV4FRAGFIS + MMC Receive IPV4 Fragmented Frame Counter Interrupt Status +This bit is set when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. + 3 + 1 + read-write + + + RXIPV4NOPAYFIS + MMC Receive IPV4 No Payload Frame Counter Interrupt Status +This bit is set when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. + 2 + 1 + read-write + + + RXIPV4HERFIS + MMC Receive IPV4 Header Error Frame Counter Interrupt Status +This bit is set when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. + 1 + 1 + read-write + + + RXIPV4GFIS + MMC Receive IPV4 Good Frame Counter Interrupt Status +This bit is set when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. + 0 + 1 + read-write + + + + + rxipv4_gd_fms + Number of good IPv4 datagrams received with the TCP, UDP, or +ICMP payload + 0x210 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload + 0 + 32 + read-write + + + + + 1 + 0x20 + 0 + L3_L4_CFG[%s] + no description available + 0x400 + + L3_L4_CTRL + Layer 3 and Layer 4 Control Register + 0x0 + 32 + 0x00000000 + 0x003DFFFD + + + L4DPIM0 + Layer 4 Destination Port Inverse Match Enable + When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. + 21 + 1 + read-write + + + L4DPM0 + Layer 4 Destination Port Match Enable + When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching. + 20 + 1 + read-write + + + L4SPIM0 + Layer 4 Source Port Inverse Match Enable +When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. + 19 + 1 + read-write + + + L4SPM0 + Layer 4 Source Port Match Enable +When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. + 18 + 1 + read-write + + + L4PEN0 + Layer 4 Protocol Enable +When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. + 16 + 1 + read-write + + + L3HDBM0 + Layer 3 IP DA Higher Bits Match + IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - ... +- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - … +- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. + 11 + 5 + read-write + + + L3HSBM0 + Layer 3 IP SA Higher Bits Match + IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - ... +- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. + 6 + 5 + read-write + + + L3DAIM0 + Layer 3 IP DA Inverse Match Enable +When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. + 5 + 1 + read-write + + + L3DAM0 + Layer 3 IP DA Match Enable +When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. + 4 + 1 + read-write + + + L3SAIM0 + Layer 3 IP SA Inverse Match Enable +When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. + 3 + 1 + read-write + + + L3SAM0 + Layer 3 IP SA Match Enable +When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. + 2 + 1 + read-write + + + L3PEN0 + Layer 3 Protocol Enable + When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. + 0 + 1 + read-write + + + + + L4_Addr + Layer 4 Address Register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + L4DP0 + Layer 4 Destination Port Number Field +When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. + 16 + 16 + read-write + + + L4SP0 + Layer 4 Source Port Number Field + When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. + 0 + 16 + read-write + + + + + L3_Addr_0 + Layer 3 Address 0 Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A00 + Layer 3 Address 0 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Source Address field in the IPv4 frames. + 0 + 32 + read-write + + + + + L3_Addr_1 + Layer 3 Address 1 Register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A10 + Layer 3 Address 1 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. + 0 + 32 + read-write + + + + + L3_Addr_2 + Layer 3 Address 2 Register + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A20 + Layer 3 Address 2 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. + 0 + 32 + read-write + + + + + L3_Addr_3 + Layer 3 Address 3 Register + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A30 + Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. + 0 + 32 + read-write + + + + + + VLAN_TAG_INC_RPL + VLAN Tag Inclusion or Replacement Register + 0x584 + 32 + 0x00000000 + 0x000FFFFF + + + CSVL + C-VLAN or S-VLAN + When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted frames. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the transmitted frames. + 19 + 1 + read-write + + + VLP + VLAN Priority Control +When this bit is set, the control Bits [17:16] are used for VLAN deletion, insertion, or replacement. When this bit is reset, the mti_vlan_ctrl_i control input is used, and Bits [17:16] are ignored. + 18 + 1 + read-write + + + VLC + VLAN Tag Control in Transmit Frames +- 2’b00: No VLAN tag deletion, insertion, or replacement +- 2’b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted frames with VLAN tags. +- 2’b10: VLAN tag insertion The MAC inserts VLT in bytes 15 and 16 of the frame after inserting the Type value (0x8100/0x88a8) in bytes 13 and 14. This operation is performed on all transmitted frames, irrespective of whether they already have a VLAN tag. +- 2’b11: VLAN tag replacement The MAC replaces VLT in bytes 15 and 16 of all VLAN-type transmitted frames (Bytes 13 and 14 are 0x8100/0x88a8). Note: Changes to this field take effect only on the start of a frame. If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, that is, the current frame does not use the updated value. + 16 + 2 + read-write + + + VLT + VLAN Tag for Transmit Frames + This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. Bits[15:13] are the User Priority, Bit 12 is the CFI/DEI, and Bits[11:0] are the VLAN tag’s VID field. + 0 + 16 + read-write + + + + + VLAN_HASH + VLAN Hash Table Register + 0x588 + 32 + 0x00000000 + 0x0000FFFF + + + VLHT + VLAN Hash Table + This field contains the 16-bit VLAN Hash Table. + 0 + 16 + read-write + + + + + TS_CTRL + Timestamp Control Register + 0x700 + 32 + 0x00000000 + 0x1F07FF3F + + + ATSEN3 + Auxiliary Snapshot 3 Enable +This field controls capturing the Auxiliary Snapshot Trigger 3. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[3] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than four. + 28 + 1 + read-write + + + ATSEN2 + Auxiliary Snapshot 2 Enable +This field controls capturing the Auxiliary Snapshot Trigger 2. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[2] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than three. + 27 + 1 + read-write + + + ATSEN1 + Auxiliary Snapshot 1 Enable +This field controls capturing the Auxiliary Snapshot Trigger 1. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[1] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than two. + 26 + 1 + read-write + + + ATSEN0 + Auxiliary Snapshot 0 Enable +This field controls capturing the Auxiliary Snapshot Trigger 0. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled. When this bit is reset, the events on this input are ignored. + 25 + 1 + read-write + + + ATSFC + Auxiliary Snapshot FIFO Clear +When set, it resets the pointers of the Auxiliary Snapshot FIFO. This bit is cleared when the pointers are reset and the FIFO is empty. When this bit is high, auxiliary snapshots get stored in the FIFO. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration. + 24 + 1 + read-write + + + TSENMACADDR + Enable MAC address for PTP Frame Filtering +When set, the DA MAC address (that matches any MAC Address register) is used to filter the PTP frames when PTP is directly sent over Ethernet. + 18 + 1 + read-write + + + SNAPTYPSEL + Select PTP packets for Taking Snapshots + These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken. + 16 + 2 + read-write + + + TSMSTRENA + Enable Snapshot for Messages Relevant to Master +When set, the snapshot is taken only for the messages relevant to the master node. Otherwise, the snapshot is taken for the messages relevant to the slave node. + 15 + 1 + read-write + + + TSEVNTENA + Enable Timestamp Snapshot for Event Messages +When set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). When reset, the snapshot is taken for all messages except Announce, Management, and Signaling. + 14 + 1 + read-write + + + TSIPV4ENA + Enable Processing of PTP Frames Sent over IPv4-UDP + When set, the MAC receiver processes the PTP packets encapsulated in UDP over IPv4 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv4 packets. This bit is set by default. + 13 + 1 + read-write + + + TSIPV6ENA + Enable Processing of PTP Frames Sent over IPv6-UDP +When set, the MAC receiver processes PTP packets encapsulated in UDP over IPv6 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv6 packets. + 12 + 1 + read-write + + + TSIPENA + Enable Processing of PTP over Ethernet Frames +When set, the MAC receiver processes the PTP packets encapsulated directly in the Ethernet frames. When this bit is clear, the MAC ignores the PTP over Ethernet packets + 11 + 1 + read-write + + + TSVER2ENA + Enable PTP packet Processing for Version 2 Format +When set, the PTP packets are processed using the 1588 version 2 format. Otherwise, the PTP packets are processed using the version 1 format. + 10 + 1 + read-write + + + TSCTRLSSR + Timestamp Digital or Binary Rollover Control +When set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. When reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and the value of this bit. + 9 + 1 + read-write + + + TSENALL + Enable Timestamp for All Frames +When set, the timestamp snapshot is enabled for all frames received by the MAC. + 8 + 1 + read-write + + + TSADDREG + Addend Reg Update +When set, the content of the Timestamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. This register bit should be zero before setting it. + 5 + 1 + read-write + + + TSTRIG + Timestamp Interrupt Trigger Enable +When set, the timestamp interrupt is generated when the System Time becomes greater than the value written in the Target Time register. This bit is reset after the generation of the Timestamp Trigger Interrupt. + 4 + 1 + read-write + + + TSUPDT + Timestamp Update +When set, the system time is updated (added or subtracted) with the value specified in Register 452 (System Time – Seconds Update Register) and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. This bit is reset when the update is completed in hardware. The “Timestamp Higher Word” register (if enabled during core configuration) is not updated. + 3 + 1 + read-write + + + TSINIT + Timestamp Initialize +When set, the system time is initialized (overwritten) with the value specified in the Register 452 (System Time – Seconds Update Register) and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. This bit is reset when the initialization is complete. The “Timestamp Higher Word” register (if enabled during core configuration) can only be initialized. + 2 + 1 + read-write + + + TSCFUPDT + Timestamp Fine or Coarse Update +When set, this bit indicates that the system times update should be done using the fine update method. When reset, it indicates the system timestamp update should be done using the Coarse method. + 1 + 1 + read-write + + + TSENA + Timestamp Enable +When set, the timestamp is added for the transmit and receive frames. When disabled, timestamp is not added for the transmit and receive frames and the Timestamp Generator is also suspended. You need to initialize the Timestamp (system time) after enabling this mode. On the receive side, the MAC processes the 1588 frames only if this bit is set. + 0 + 1 + read-write + + + + + SUB_SEC_INCR + Sub-Second Increment Register + 0x704 + 32 + 0x00000000 + 0x000000FF + + + SSINC + Sub-second Increment Value +The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register. For example, when PTP clock is 50 MHz (period is 20 ns), you should program 20 (0x14) when the System Time- Nanoseconds register has an accuracy of 1 ns [Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register)]. When TSCTRLSSR is clear, the Nanoseconds register has a resolution of ~0.465ns. In this case, you should program a value of 43 (0x2B) that is derived by 20ns/0.465. + 0 + 8 + read-write + + + + + SYST_SEC + System Time - Seconds Register + 0x708 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSS + Timestamp Second + The value in this field indicates the current value in seconds of the System Time maintained by the MAC. + 0 + 32 + read-only + + + + + SYST_NSEC + System Time - Nanoseconds Register + 0x70c + 32 + 0x00000000 + 0x7FFFFFFF + + + TSSS + Timestamp Sub Seconds + The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the maximum value is 0x3B9A_C9FF, after which it rolls-over to zero. + 0 + 31 + read-only + + + + + SYST_SEC_UPD + System Time - Seconds Update Register + 0x710 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSS + Timestamp Second + The value in this field indicates the time in seconds to be initialized or added to the system time. + 0 + 32 + read-write + + + + + SYST_NSEC_UPD + System Time - Nanoseconds Update Register + 0x714 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDSUB + Add or Subtract Time + When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register. + 31 + 1 + read-write + + + TSSS + Timestamp Sub Seconds +The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF. + 0 + 31 + read-write + + + + + TS_ADDEND + Timestamp Addend Register + 0x718 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSAR + Timestamp Addend Register +This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization. + 0 + 32 + read-write + + + + + TGTTM_SEC + Target Time Seconds Register + 0x71c + 32 + 0x00000000 + 0xFFFFFFFF + + + TSTR + Target Time Seconds Register + This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [6:5] of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). + 0 + 32 + read-write + + + + + TGTTM_NSEC + Target Time Nanoseconds Register + 0x720 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRGTBUSY + Target Time Register Busy + The MAC sets this bit when the PPSCMD field (Bit [3:0]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD field to 010 or 011, instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. This bit is reserved when the Enable Flexible Pulse-Per-Second Output feature is not selected. + 31 + 1 + read-write + + + TTSLO + Target Timestamp Low Register +This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL0 field (Bits [6:5]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. + 0 + 31 + read-write + + + + + SYSTM_H_SEC + System Time - Higher Word Seconds Register + 0x724 + 32 + 0x00000000 + 0x0000FFFF + + + TSHWR + Timestamp Higher Word Register +This field contains the most significant 16-bits of the timestamp seconds value. This register is optional and can be selected using the Enable IEEE 1588 Higher Word Register option during core configuration. The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register. + 0 + 16 + read-write + + + + + TS_STATUS + Timestamp Status Register + 0x728 + 32 + 0x00000000 + 0x3F0F03FF + + + ATSNS + Number of Auxiliary Timestamp Snapshots +This field indicates the number of Snapshots available in the FIFO. A value equal to the selected depth of FIFO (4, 8, or 16) indicates that the Auxiliary Snapshot FIFO is full. These bits are cleared (to 00000) when the Auxiliary snapshot FIFO clear bit is set. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. + 25 + 5 + read-only + + + ATSSTM + Auxiliary Timestamp Snapshot Trigger Missed + This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set. This indicates that the latest snapshot is not stored in the FIFO. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. + 24 + 1 + read-only + + + ATSSTN + Auxiliary Timestamp Snapshot Trigger Identifier +These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. When more than one bit is set at the same time, it means that corresponding auxiliary triggers were sampled at the same clock. These bits are applicable only if the number of Auxiliary snapshots is more than one. One bit is assigned for each trigger as shown in the following list: - Bit 16: Auxiliary trigger 0 - Bit 17: Auxiliary trigger 1 - Bit 18: Auxiliary trigger 2 - Bit 19: Auxiliary trigger 3 The software can read this register to find the triggers that are set when the timestamp is taken. + 16 + 4 + read-only + + + TSTRGTERR3 + Timestamp Target Time Error +This bit is set when the target time, being programmed in Register 496 and Register 497, is already elapsed. This bit is cleared when read by the application. + 9 + 1 + read-only + + + TSTARGT3 + Timestamp Target Time Reached for Target Time PPS3 +When set, this bit indicates that the value of system time is greater than or equal to the value specified in Register 496 (PPS3 Target Time High Register) and Register 497 (PPS3 Target Time Low Register). + 8 + 1 + read-only + + + TSTRGTERR2 + No description available + 7 + 1 + read-only + + + TSTARGT2 + No description available + 6 + 1 + read-only + + + TSTRGTERR1 + No description available + 5 + 1 + read-only + + + TSTARGT1 + No description available + 4 + 1 + read-only + + + TSTRGTERR + No description available + 3 + 1 + read-only + + + AUXTSTRIG + No description available + 2 + 1 + read-only + + + TSTARGT + No description available + 1 + 1 + read-only + + + TSSOVF + No description available + 0 + 1 + read-only + + + + + PPS_CTRL + PPS Control Register + 0x72c + 32 + 0x00000000 + 0x6767777F + + + TRGTMODSEL3 + Target Time Register Mode for PPS3 Output +This field indicates the Target Time registers (register 496 and 497) mode for PPS3 output signal. This field is similar to the TRGTMODSEL0 field. + 29 + 2 + read-write + + + PPSCMD3 + Flexible PPS3 Output Control +This field controls the flexible PPS3 output (ptp_pps_o[3]) signal. This field is similar to PPSCMD0[2:0] in functionality. + 24 + 3 + read-write + + + TRGTMODSEL2 + Target Time Register Mode for PPS2 Output +This field indicates the Target Time registers (register 488 and 489) mode for PPS2 output signal. This field is similar to the TRGTMODSEL0 field. + 21 + 2 + read-write + + + PPSCMD2 + Flexible PPS2 Output Control +This field controls the flexible PPS2 output (ptp_pps_o[2]) signal. This field is similar to PPSCMD0[2:0] in functionality. + 16 + 3 + read-write + + + TRGTMODSEL1 + Target Time Register Mode for PPS1 Output +This field indicates the Target Time registers (register 480 and 481) mode for PPS1 output signal. This field is similar to the TRGTMODSEL0 field. + 13 + 2 + read-write + + + PPSEN1 + Flexible PPS1 Output Mode Enable +When set high, Bits[10:8] function as PPSCMD. + 12 + 1 + read-write + + + PPSCMD1 + Flexible PPS1 Output Control +This field controls the flexible PPS1 output (ptp_pps_o[1]) signal. This field is similar to PPSCMD0[2:0] in functionality. + 8 + 3 + read-write + + + TRGTMODSEL0 + Target Time Register Mode for PPS0 Output + This field indicates the Target Time registers (register 455 and 456) mode for PPS0 output signal: +- 00: Indicates that the Target Time registers are programmed only for generating the interrupt event. +- 01: Reserved +- 10: Indicates that the Target Time registers are programmed for generating the interrupt event and starting or stopping the generation of the PPS0 output signal. +- 11: Indicates that the Target Time registers are programmed only for starting or stopping the generation of the PPS0 output signal. No interrupt is asserted. + 5 + 2 + read-write + + + PPSEN0 + Flexible PPS Output Mode Enable +When set low, Bits [3:0] function as PPSCTRL (backward compatible). When set high, Bits[3:0] function as PPSCMD. + 4 + 1 + read-write + + + PPSCTRLCMD0 + PPSCTRL0: PPS0 Output Frequency Control +This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. The default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width clk_ptp_i) every second. For other values of PPSCTRL, the PPS output becomes a generated clock of following frequencies: +- 0001: The binary rollover is 2 Hz, and the digital rollover is 1 Hz. +- 0010: The binary rollover is 4 Hz, and the digital rollover is 2 Hz. +- 0011: The binary rollover is 8 Hz, and the digital rollover is 4 Hz. +- 0100: The binary rollover is 16 Hz, and the digital rollover is 8 Hz. - ... +- 1111: The binary rollover is 32.768 KHz, and the digital rollover is 16.384 KHz. Note: In the binary rollover mode, the PPS output (ptp_pps_o) has a duty cycle of 50 percent with these frequencies. In the digital rollover mode, the PPS output frequency is an average number. The actual clock is of different frequency that gets synchronized every second. For example: - When PPSCTRL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high period of 463 ms - When PPSCTRL = 0010, the PPS (2 Hz) is a sequence of: - One clock of 50 percent duty cycle and 537 ms period - Second clock of 463 ms period (268 ms low and 195 ms high) - When PPSCTRL = 0011, the PPS (4 Hz) is a sequence of: - Three clocks of 50 percent duty cycle and 268 ms period - Fourth clock of 195 ms period (134 ms low and 61 ms high) +PPSCMD0: Flexible PPS0 Output Control +0000: No Command +0001: START Single Pulse +This command generates single pulse rising at the start point defined in +Target Time Registers and of a duration defined +in the PPS0 Width Register. +0010: START Pulse Train +This command generates the train of pulses rising at the start point +defined in the Target Time Registers and of a duration defined in the +PPS0 Width Register and repeated at interval defined in the PPS +Interval Register. By default, the PPS pulse train is free-running unless +stopped by ‘STOP Pulse train at time’ or ‘STOP Pulse Train +immediately’ commands. +0011: Cancel START +This command cancels the START Single Pulse and START Pulse Train +commands if the system time has not crossed the programmed start +time. +0100: STOP Pulse train at time +This command stops the train of pulses initiated by the START Pulse +Train command (PPSCMD = 0010) after the time programmed in the +Target Time registers elapses. +0101: STOP Pulse Train immediately +This command immediately stops the train of pulses initiated by the +START Pulse Train command (PPSCMD = 0010). +0110: Cancel STOP Pulse train +This command cancels the STOP pulse train at time command if the +programmed stop time has not elapsed. The PPS pulse train becomes +free-running on the successful execution of this command. +0111-1111: Reserved +Note: These bits get cleared automatically + 0 + 4 + read-write + + + + + AUX_TS_NSEC + Auxiliary Timestamp - Nanoseconds Register + 0x730 + 32 + 0x00000000 + 0x7FFFFFFF + + + AUXTSLO + Contains the lower 31 bits (nano-seconds field) of the auxiliary timestamp. + 0 + 31 + read-only + + + + + AUX_TS_SEC + Auxiliary Timestamp - Seconds Register + 0x734 + 32 + 0x00000000 + 0xFFFFFFFF + + + AUXTSHI + Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. + 0 + 32 + read-only + + + + + PPS0_INTERVAL + PPS0 Interval Register + 0x760 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPSINT + PPS0 Output Signal Interval +These bits store the interval between the rising edges of PPS0 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS0 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. + 0 + 32 + read-write + + + + + PPS0_WIDTH + PPS0 Width Register + 0x764 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPSWIDTH + PPS0 Output Signal Width +These bits store the width between the rising edge and corresponding falling edge of the PPS0 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS0 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. + 0 + 32 + read-write + + + + + 3 + 0x20 + 1,2,3 + PPS[%s] + no description available + 0x780 + + TGTTM_SEC + PPS Target Time Seconds Register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSTRH1 + PPS1 Target Time Seconds Register +This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [14:13], TRGTMODSEL1, of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). + 0 + 32 + read-write + + + + + TGTTM_NSEC + PPS Target Time Nanoseconds Register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRGTBUSY1 + PPS1 Target Time Register Busy +The MAC sets this bit when the PPSCMD1 field (Bits [10:8]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. + 31 + 1 + read-write + + + TTSL1 + Target Time Low for PPS1 Register +This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL1 field (Bits [14:13]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. + 0 + 31 + read-write + + + + + INTERVAL + PPS Interval Register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPSINT + PPS1 Output Signal Interval +These bits store the interval between the rising edges of PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS1 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. + 0 + 32 + read-write + + + + + WIDTH + PPS Width Register + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + PPSWIDTH + PPS1 Output Signal Width +These bits store the width between the rising edge and corresponding falling edge of the PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS1 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. + 0 + 32 + read-write + + + + + + DMA_BUS_MODE + Bus Mode Register + 0x1000 + 32 + 0x00000000 + 0xBFFFFFFF + + + RIB + Rebuild INCRx Burst +When this bit is set high and the AHB master gets an EBT (Retry, Split, or Losing bus grant), the AHB master interface rebuilds the pending beats of any burst transfer initiated with INCRx. The AHB master interface rebuilds the beats with a combination of specified bursts with INCRx and SINGLE. By default, the AHB master interface rebuilds pending beats of an EBT with an unspecified (INCR) burst. + 31 + 1 + read-write + + + PRWG + Channel Priority +Weights This field sets the priority weights for Channel 0 during the round-robin arbitration between the DMA channels for the system bus. +- 00: The priority weight is 1. +- 01: The priority weight is 2. +- 10: The priority weight is 3. +- 11: The priority weight is 4. This field is present in all DWC_gmac configurations except GMAC-AXI when you select the AV feature. Otherwise, this field is reserved and read-only (RO). + 28 + 2 + read-write + + + TXPR + Transmit Priority +When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus. In the GMAC-AXI configuration, this bit is reserved and read-only (RO). + 27 + 1 + read-write + + + MB + Mixed Burst +When this bit is set high and the FB bit is low, the AHB master interface starts all bursts of length more than 16 with INCR (undefined burst), whereas it reverts to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less. + 26 + 1 + read-write + + + AAL + Address-Aligned Beats +When this bit is set high and the FB bit is equal to 1, the AHB or AXI interface generates all bursts aligned to the start address LS bits. If the FB bit is equal to 0, the first burst (accessing the start address of data buffer) is not aligned, but subsequent bursts are aligned to the address. + 25 + 1 + read-write + + + PBLX8 + PBLx8 Mode +When set high, this bit multiplies the programmed PBL value (Bits [22:17] and Bits[13:8]) eight times. Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. + 24 + 1 + read-write + + + USP + Use Separate PBL +When set high, this bit configures the Rx DMA to use the value configured in Bits [22:17] as PBL. The PBL value in Bits [13:8] is applicable only to the Tx DMA operations. When reset to low, the PBL value in Bits [13:8] is applicable for both DMA engines. + 23 + 1 + read-write + + + RPBL + Rx DMA PBL +This field indicates the maximum number of beats to be transferred in one Rx DMA transaction. This is the maximum value that is used in a single block Read or Write. The Rx DMA always attempts to burst as specified in the RPBL bit each time it starts a Burst transfer on the host bus. You can program RPBL with values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. This field is valid and applicable only when USP is set high. + 17 + 6 + read-write + + + FB + Fixed Burst + This bit controls whether the AHB or AXI master interface performs fixed burst transfers or not. When set, the AHB interface uses only SINGLE, INCR4, INCR8, or INCR16 during start of the normal burst transfers. When reset, the AHB or AXI interface uses SINGLE and INCR burst transfer operations. + 16 + 1 + read-write + + + PR + Priority Ratio + These bits control the priority ratio in the weighted round-robin arbitration between the Rx DMA and Tx DMA. These bits are valid only when Bit 1 (DA) is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 (TXPR) is reset or set. +- 00: The Priority Ratio is 1:1. +- 01: The Priority Ratio is 2:1. +- 10: The Priority Ratio is 3:1. +- 11: The Priority Ratio is 4:1. + 14 + 2 + read-write + + + PBL + Programmable Burst Length +These bits indicate the maximum number of beats to be transferred in one DMA transaction. This is the maximum value that is used in a single block Read or Write. The DMA always attempts to burst as specified in PBL each time it starts a Burst transfer on the host bus. PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. When USP is set high, this PBL value is applicable only for Tx DMA transactions. If the number of beats to be transferred is more than 32, then perform the following steps: 1. Set the PBLx8 mode. 2. Set the PBL. + 8 + 6 + read-write + + + ATDS + Alternate Descriptor Size +When set, the size of the alternate descriptor (described in “Alternate or Enhanced Descriptors” on page 545) increases to 32 bytes (8 DWORDS). This is required when the Advanced Timestamp feature or the IPC Full Checksum Offload Engine (Type 2) is enabled in the receiver. The enhanced descriptor is not required if the Advanced Timestamp and IPC Full Checksum Offload Engine (Type 2) features are not enabled. In such case, you can use the 16 bytes descriptor to save 4 bytes of memory. This bit is present only when you select the Alternate Descriptor feature and any one of the following features during core configuration: - Advanced Timestamp feature - IPC Full Checksum Offload Engine (Type 2) feature Otherwise, this bit is reserved and is read-only. When reset, the descriptor size reverts back to 4 DWORDs (16 bytes). + 7 + 1 + read-write + + + DSL + Descriptor Skip Length +This bit specifies the number of Word, Dword, or Lword (depending on the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors. The address skipping starts from the end of current descriptor to the start of next descriptor. When the DSL value is equal to zero, the descriptor table is taken as contiguous by the DMA in Ring mode. + 2 + 5 + read-write + + + DA + DMA Arbitration Scheme +This bit specifies the arbitration scheme between the transmit and receive paths of Channel 0. +- 0: Weighted round-robin with Rx:Tx or Tx:Rx The priority between the paths is according to the priority specified in Bits [15:14] (PR) and priority weights specified in Bit 27 (TXPR). +- 1: Fixed priority The transmit path has priority over receive path when Bit 27 (TXPR) is set. Otherwise, receive path has priority over the transmit path. + 1 + 1 + read-write + + + SWR + Software Reset + When this bit is set, the MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after the reset operation is complete in all of the DWC_gmac clock domains. Before reprogramming any register of the DWC_gmac, you should read a zero (0) value in this bit. Note: - The Software reset function is driven only by this bit. Bit 0 of Register 64 (Channel 1 Bus Mode Register) or Register 128 (Channel 2 Bus Mode Register) has no impact on the Software reset function. - The reset operation is completed only when all resets in all active clock domains are de-asserted. Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for the software reset completion. The time to complete the software reset operation depends on the frequency of the slowest active clock. + 0 + 1 + read-write + + + + + DMA_TX_POLL_DEMAND + Transmit Poll Demand Register + 0x1004 + 32 + 0x00000000 + 0xFFFFFFFF + + + TPD + Transmit Poll Demand +When these bits are written with any value, the DMA reads the current descriptor to which the Register 18 (Current Host Transmit Descriptor Register) is pointing. If that descriptor is not available (owned by the Host), the transmission returns to the Suspend state and Bit 2 (TU) of Register 5 (Status Register) is asserted. If the descriptor is available, the transmission resumes. + 0 + 32 + read-write + + + + + DMA_RX_POLL_DEMAND + Receive Poll Demand Register + 0x1008 + 32 + 0x00000000 + 0xFFFFFFFF + + + RPD + Receive Poll Demand +When these bits are written with any value, the DMA reads the current descriptor to which the Register 19 (Current Host Receive Descriptor Register) is pointing. If that descriptor is not available (owned by the Host), the reception returns to the Suspended state and Bit 7 (RU) of Register 5 (Status Register) is asserted. If the descriptor is available, the Rx DMA returns to the active state. + 0 + 32 + read-write + + + + + DMA_RX_DESC_LIST_ADDR + Receive Descriptor List Address Register + 0x100c + 32 + 0x00000000 + 0xFFFFFFFF + + + RDESLA + Start of Receive List +This field contains the base address of the first descriptor in the Receive Descriptor list. The LSB bits (1:0, 2:0, or 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). + 0 + 32 + read-write + + + + + DMA_TX_DESC_LIST_ADDR + Transmit Descriptor List Address Register + 0x1010 + 32 + 0x00000000 + 0xFFFFFFFF + + + TDESLA + Start of Transmit List +This field contains the base address of the first descriptor in the Transmit Descriptor list. The LSB bits (1:0, 2:0, 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and are internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). + 0 + 32 + read-write + + + + + DMA_STATUS + Status Register + 0x1014 + 32 + 0x00000000 + 0x7FFFE7FF + + + GLPII + GLPII: GMAC LPI Interrupt (for Channel 0) +This bit indicates an interrupt event in the LPI logic of the MAC. To reset this bit to 1'b0, the software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source. Note: GLPII status is given only in Channel 0 DMA register and is applicable only when the Energy Efficient Ethernet feature is enabled. Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. -or- GTMSI: GMAC TMS Interrupt (for Channel 1 and Channel 2) This bit indicates an interrupt event in the traffic manager and scheduler logic of DWC_gmac. To reset this bit, the software must read the corresponding registers (Channel Status Register) to get the exact cause of the interrupt and clear its source. Note: GTMSI status is given only in Channel 1 and Channel 2 DMA register when the AV feature is enabled and corresponding additional transmit channels are present. Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. + 30 + 1 + read-write + + + TTI + Timestamp Trigger Interrupt +This bit indicates an interrupt event in the Timestamp Generator block of the DWC_gmac. The software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source to reset this bit to 1'b0. When this bit is high, the interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high. This bit is applicable only when the IEEE 1588 Timestamp feature is enabled. Otherwise, this bit is reserved. + 29 + 1 + read-write + + + GPI + GMAC PMT Interrupt +This bit indicates an interrupt event in the PMT module of the DWC_gmac. The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1’b0. The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. This bit is applicable only when the Power Management feature is enabled. Otherwise, this bit is reserved. Note: The GPI and pmt_intr_o interrupts are generated in different clock domains. + 28 + 1 + read-write + + + GMI + GMAC MMC Interrupt + This bit reflects an interrupt event in the MMC module of the DWC_gmac. The software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear the source of interrupt to make this bit as 1’b0. The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. This bit is applicable only when the MAC Management Counters (MMC) are enabled. Otherwise, this bit is reserved. + 27 + 1 + read-write + + + GLI + GMAC Line Interface Interrupt +When set, this bit reflects any of the following interrupt events in the DWC_gmac interfaces (if present and enabled in your configuration): - PCS (TBI, RTBI, or SGMII): Link change or auto-negotiation complete event - SMII or RGMII: Link change event - General Purpose Input Status (GPIS): Any LL or LH event on the gpi_i input ports To identify the exact cause of the interrupt, the software must first read Bit 11 and Bits[2:0] of Register 14 (Interrupt Status Register) and then to clear the source of interrupt (which also clears the GLI interrupt), read any of the following corresponding registers: - PCS (TBI, RTBI, or SGMII): Register 49 (AN Status Register) - SMII or RGMII: Register 54 (SGMII/RGMII/SMII Control and Status Register) - General Purpose Input (GPI): Register 56 (General Purpose IO Register) The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. + 26 + 1 + read-write + + + EB + Error Bits +This field indicates the type of error that caused a Bus Error, for example, error response on the AHB or AXI interface. This field is valid only when Bit 13 (FBI) is set. This field does not generate an interrupt. +- 0 0 0: Error during Rx DMA Write Data Transfer +- 0 1 1: Error during Tx DMA Read Data Transfer +- 1 0 0: Error during Rx DMA Descriptor Write Access +- 1 0 1: Error during Tx DMA Descriptor Write Access +- 1 1 0: Error during Rx DMA Descriptor Read Access +- 1 1 1: Error during Tx DMA Descriptor Read Access Note: 001 and 010 are reserved. + 23 + 3 + read-write + + + TS + Transmit Process State +This field indicates the Transmit DMA FSM state. This field does not generate an interrupt. +- 3’b000: Stopped; Reset or Stop Transmit Command issued +- 3’b001: Running; Fetching Transmit Transfer Descriptor +- 3’b010: Running; Waiting for status +- 3’b011: Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO) +- 3’b100: TIME_STAMP write state +- 3’b101: Reserved for future use +- 3’b110: Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow +- 3’b111: Running; Closing Transmit Descriptor + 20 + 3 + read-write + + + RS + Receive Process State +This field indicates the Receive DMA FSM state. This field does not generate an interrupt. +- 3’b000: Stopped: Reset or Stop Receive Command issued +- 3’b001: Running: Fetching Receive Transfer Descriptor +- 3’b010: Reserved for future use +- 3’b011: Running: Waiting for receive packet +- 3’b100: Suspended: Receive Descriptor Unavailable +- 3’b101: Running: Closing Receive Descriptor +- 3’b110: TIME_STAMP write state +- 3’b111: Running: Transferring the receive packet data from receive buffer to host memory + 17 + 3 + read-write + + + NIS + Normal Interrupt Summary +Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register): - Register 5[0]: Transmit Interrupt - Register 5[2]: Transmit Buffer Unavailable - Register 5[6]: Receive Interrupt - Register 5[14]: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt enable is set in Register 7) affect the Normal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes NIS to be set, is cleared. + 16 + 1 + read-write + + + AIS + Abnormal Interrupt Summary +Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register): - Register 5[1]: Transmit Process Stopped - Register 5[3]: Transmit Jabber Timeout - Register 5[4]: Receive FIFO Overflow - Register 5[5]: Transmit Underflow - Register 5[7]: Receive Buffer Unavailable - Register 5[8]: Receive Process Stopped - Register 5[9]: Receive Watchdog Timeout - Register 5[10]: Early Transmit Interrupt - Register 5[13]: Fatal Bus Error Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes AIS to be set, is cleared. + 15 + 1 + read-write + + + ERI + Early Receive Interrupt +This bit indicates that the DMA filled the first data buffer of the packet. This bit is cleared when the software writes 1 to this bit or Bit 6 (RI) of this register is set (whichever occurs earlier). + 14 + 1 + read-write + + + FBI + Fatal Bus Error Interrupt +This bit indicates that a bus error occurred, as described in Bits [25:23]. When this bit is set, the corresponding DMA engine disables all of its bus accesses. + 13 + 1 + read-write + + + ETI + Early Transmit Interrupt +This bit indicates that the frame to be transmitted is fully transferred to the MTL Transmit FIFO. + 10 + 1 + read-write + + + RWT + Receive Watchdog Timeout +When set, this bit indicates that the Receive Watchdog Timer expired while receiving the current frame and the current frame is truncated after the watchdog timeout. + 9 + 1 + read-write + + + RPS + Receive Process Stopped +This bit is asserted when the Receive Process enters the Stopped state. + 8 + 1 + read-write + + + RU + Receive Buffer Unavailable +This bit indicates that the host owns the Next Descriptor in the Receive List and the DMA cannot acquire it. The Receive Process is suspended. To resume processing Receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, the Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor is owned by the DMA. + 7 + 1 + read-write + + + RI + Receive Interrupt +This bit indicates that the frame reception is complete. When reception is complete, the Bit 31 of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor, and the specific frame status information is updated in the descriptor. The reception remains in the Running state. + 6 + 1 + read-write + + + UNF + Transmit Underflow +This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set. + 5 + 1 + read-write + + + OVF + Receive Overflow +This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to the application, the overflow status is set in RDES0[11]. + 4 + 1 + read-write + + + TJT + Transmit Jabber Timeout +This bit indicates that the Transmit Jabber Timer expired, which happens when the frame size exceeds 2,048 (10,240 bytes when the Jumbo frame is enabled). When the Jabber Timeout occurs, the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert. + 3 + 1 + read-write + + + TU + Transmit Buffer Unavailable +This bit indicates that the host owns the Next Descriptor in the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing Transmit descriptors, the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command. + 2 + 1 + read-write + + + TPS + Transmit Process Stopped +This bit is set when the transmission is stopped. + 1 + 1 + read-write + + + TI + Transmit Interrupt +This bit indicates that the frame transmission is complete. When transmission is complete, Bit 31 (OWN) of TDES0 is reset, and the specific frame status information is updated in the descriptor. + 0 + 1 + read-write + + + + + DMA_OP_MODE + Operation Mode Register + 0x1018 + 32 + 0x00000000 + 0x13F1FFFE + + + DT + Disable Dropping of TCP/IP Checksum Error Frames +When this bit is set, the MAC does not drop the frames which only have errors detected by the Receive Checksum Offload engine. Such frames do not have any errors (including FCS error) in the Ethernet frame received by the MAC but have errors only in the encapsulated payload. When this bit is reset, all error frames are dropped if the FEF bit is reset. If the IPC Full Checksum Offload Engine (Type 2) is disabled, this bit is reserved (RO with value 1'b0). + 28 + 1 + read-write + + + RSF + Receive Store and Forward +When this bit is set, the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it, ignoring the RTC bits. When this bit is reset, the Rx FIFO operates in the cut-through mode, subject to the threshold specified by the RTC bits. + 25 + 1 + read-write + + + DFF + Disable Flushing of Received Frames +When this bit is set, the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers as it does normally when this bit is reset. (See “Receive Process Suspended” on page 83.) + 24 + 1 + read-write + + + RFA_2 + MSB of Threshold for Activating Flow Control +If the DWC_gmac is configured for an Rx FIFO size of 8 KB or more, this bit (when set) provides additional threshold levels for activating the flow control in both half-duplex and full-duplex modes. This bit (as Most Significant Bit), along with the RFA (Bits [10:9]), gives the following thresholds for activating flow control: +- 100: Full minus 5 KB, that is, FULL — 5 KB +- 101: Full minus 6 KB, that is, FULL — 6 KB +- 110: Full minus 7 KB, that is, FULL — 7 KB +- 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. + 23 + 1 + read-write + + + RFD_2 + MSB of Threshold for Deactivating Flow Control +If the DWC_gmac is configured for Rx FIFO size of 8 KB or more, this bit (when set) provides additional threshold levels for deactivating the flow control in both half-duplex and full-duplex modes. This bit (as Most Significant Bit) along with the RFD (Bits [12:11]) gives the following thresholds for deactivating flow control: +- 100: Full minus 5 KB, that is, FULL — 5 KB +- 101: Full minus 6 KB, that is, FULL — 6 KB +- 110: Full minus 7 KB, that is, FULL — 7 KB +- 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. + 22 + 1 + read-write + + + TSF + Transmit Store and Forward +When this bit is set, transmission starts when a full frame resides in the MTL Transmit FIFO. When this bit is set, the TTC values specified in Bits [16:14] are ignored. This bit should be changed only when the transmission is stopped. + 21 + 1 + read-write + + + FTF + Flush Transmit FIFO +When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flushed. This bit is cleared internally when the flushing operation is complete. The Operation Mode register should not be written to until this bit is cleared. The data which is already accepted by the MAC transmitter is not flushed. It is scheduled for transmission and results in underflow and runt frame transmission. + 20 + 1 + read-write + + + TTC + Transmit Threshold Control +These bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are also transmitted. These bits are used only when Bit 21 (TSF) is reset. +- 000: 64 +- 001: 128 +- 010: 192 +- 011: 256 +- 100: 40 +- 101: 32 +- 110: 24 +- 111: 16 + 14 + 3 + read-write + + + ST + Start or Stop Transmission Command +When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. Descriptor acquisition is attempted either from the current position in the list, which is the Transmit List Base Address set by Register 4 (Transmit Descriptor List Address Register), or from the position retained when transmission was stopped previously. If the DMA does not own the current descriptor, transmission enters the Suspended state and Bit 2 (Transmit Buffer Unavailable) of Register 5 (Status Register) is set. The Start Transmission command is effective only when transmission is stopped. If the command is issued before setting Register 4 (Transmit Descriptor List Address Register), then the DMA behavior is unpredictable. When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current frame. The Next Descriptor position in the Transmit List is saved, and it becomes the current position when transmission is restarted. To change the list address, you need to program Register 4 (Transmit Descriptor List Address Register) with a new value when this bit is reset. The new value is considered when this bit is set again. The stop transmission command is effective only when the transmission of the current frame is complete or the transmission is in the Suspended state. + 13 + 1 + read-write + + + RFD + Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (Fill-level of Rx FIFO) at which the flow control is de-asserted after activation. +- 00: Full minus 1 KB, that is, FULL — 1 KB +- 01: Full minus 2 KB, that is, FULL — 2 KB +- 10: Full minus 3 KB, that is, FULL — 3 KB +- 11: Full minus 4 KB, that is, FULL — 4 KB The de-assertion is effective only after flow control is asserted. If the Rx FIFO is 8 KB or more, an additional Bit (RFD_2) is used for more threshold levels as described in Bit 22. These bits are reserved and read-only when the Rx FIFO depth is less than 4 KB. + 11 + 2 + read-write + + + RFA + Threshold for Activating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (Fill level of Rx FIFO) at which the flow control is activated. +- 00: Full minus 1 KB, that is, FULL—1KB. +- 01: Full minus 2 KB, that is, FULL—2KB. +- 10: Full minus 3 KB, that is, FULL—3KB. +- 11: Full minus 4 KB, that is, FULL—4KB. These values are applicable only to Rx FIFOs of 4 KB or more and when Bit 8 (EFC) is set high. If the Rx FIFO is 8 KB or more, an additional Bit (RFA_2) is used for more threshold levels as described in Bit 23. These bits are reserved and read-only when the depth of Rx FIFO is less than 4 KB. Note: When FIFO size is exactly 4 KB, although the DWC_gmac allows you to program the value of these bits to 11, the software should not program these bits to 2'b11. The value 2'b11 means flow control on FIFO empty condition + 9 + 2 + read-write + + + EFC + Enable HW Flow Control +When this bit is set, the flow control signal operation based on the fill-level of Rx FIFO is enabled. When reset, the flow control operation is disabled. This bit is not used (reserved and always reset) when the Rx FIFO is less than 4 KB. + 8 + 1 + read-write + + + FEF + Forward Error Frames +When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or overflow). However, if the start byte (write) pointer of a frame is already transferred to the read controller side (in Threshold mode), then the frame is not dropped. In the GMAC-MTL configuration in which the Frame Length FIFO is also enabled during core configuration, the Rx FIFO drops the error frames if that frame's start byte is not transferred (output) on the ARI bus. When the FEF bit is set, all frames except runt error frames are forwarded to the DMA. If the Bit 25 (RSF) is set and the Rx FIFO overflows when a partial frame is written, then the frame is dropped irrespective of the FEF bit setting. However, if the Bit 25 (RSF) is reset and the Rx FIFO overflows when a partial frame is written, then a partial frame may be forwarded to the DMA. Note: When FEF bit is reset, the giant frames are dropped if the giant frame status is given in Rx Status (in Table 8-6 or Table 8-23) in the following configurations: - The IP checksum engine (Type 1) and full checksum offload engine (Type 2) are not selected. - The advanced timestamp feature is not selected but the extended status is selected. The extended status is available with the following features: - L3-L4 filter in GMAC-CORE or GMAC-MTL configurations - Full checksum offload engine (Type 2) with enhanced descriptor format in the GMAC-DMA, GMAC-AHB, or GMAC-AXI configurations. + 7 + 1 + read-write + + + FUF + Forward Undersized Good Frames +When set, the Rx FIFO forwards Undersized frames (that is, frames with no Error and length less than 64 bytes) including pad-bytes and CRC. When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a frame is already transferred because of the lower value of Receive Threshold, for example, RTC = 01. + 6 + 1 + read-write + + + DGF + Drop Giant Frames +When set, the MAC drops the received giant frames in the Rx FIFO, that is, frames that are larger than the computed giant frame limit. When reset, the MAC does not drop the giant frames in the Rx FIFO. Note: This bit is available in the following configurations in which the giant frame status is not provided in Rx status and giant frames are not dropped by default: - Configurations in which IP Checksum Offload (Type 1) is selected in Rx - Configurations in which the IPC Full Checksum Offload Engine (Type 2) is selected in Rx with normal descriptor format - Configurations in which the Advanced Timestamp feature is selected In all other configurations, this bit is not used (reserved and always reset). + 5 + 1 + read-write + + + RTC + Receive Threshold Control +These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. In addition, full frames with length less than the threshold are automatically transferred. The value of 11 is not applicable if the configured Receive FIFO size is 128 bytes. These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1. +- 00: 64 +- 01: 32 +- 10: 96 +- 11: 128 + 3 + 2 + read-write + + + OSF + Operate on Second Frame +When this bit is set, it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained. + 2 + 1 + read-write + + + SR + Start or Stop Receive +When this bit is set, the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames. The descriptor acquisition is attempted from the current position in the list, which is the address set by the Register 3 (Receive Descriptor List Address Register) or the position retained when the Receive process was previously stopped. If the DMA does not own the descriptor, reception is suspended and Bit 7 (Receive Buffer Unavailable) of Register 5 (Status Register) is set. The Start Receive command is effective only when the reception has stopped. If the command is issued before setting Register 3 (Receive Descriptor List Address Register), the DMA behavior is unpredictable. When this bit is cleared, the Rx DMA operation is stopped after the transfer of the current frame. The next descriptor position in the Receive list is saved and becomes the current position after the Receive process is restarted. The Stop Receive command is effective only when the Receive process is in either the Running (waiting for receive packet) or in the Suspended state. + 1 + 1 + read-write + + + + + DMA_INTR_EN + Interrupt Enable Register + 0x101c + 32 + 0x00000000 + 0x0001E7FF + + + NIE + Normal Interrupt Summary Enable +When this bit is set, normal interrupt summary is enabled. When this bit is reset, normal interrupt summary is disabled. This bit enables the following interrupts in Register 5 (Status Register): - Register 5[0]: Transmit Interrupt - Register 5[2]: Transmit Buffer Unavailable - Register 5[6]: Receive Interrupt - Register 5[14]: Early Receive Interrupt + 16 + 1 + read-write + + + AIE + Abnormal Interrupt Summary Enable +When this bit is set, abnormal interrupt summary is enabled. When this bit is reset, the abnormal interrupt summary is disabled. This bit enables the following interrupts in Register 5 (Status Register): - Register 5[1]: Transmit Process Stopped - Register 5[3]: Transmit Jabber Timeout - Register 5[4]: Receive Overflow - Register 5[5]: Transmit Underflow - Register 5[7]: Receive Buffer Unavailable - Register 5[8]: Receive Process Stopped - Register 5[9]: Receive Watchdog Timeout - Register 5[10]: Early Transmit Interrupt - Register 5[13]: Fatal Bus Error + 15 + 1 + read-write + + + ERE + Early Receive Interrupt Enable +When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Early Receive Interrupt is enabled. When this bit is reset, the Early Receive Interrupt is disabled. + 14 + 1 + read-write + + + FBE + Fatal Bus Error Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Fatal Bus Error Interrupt is enabled. When this bit is reset, the Fatal Bus Error Enable Interrupt is disabled. + 13 + 1 + read-write + + + ETE + Early Transmit Interrupt Enable +When this bit is set with an Abnormal Interrupt Summary Enable (Bit 15), the Early Transmit Interrupt is enabled. When this bit is reset, the Early Transmit Interrupt is disabled. + 10 + 1 + read-write + + + RWE + Receive Watchdog Timeout Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, the Receive Watchdog Timeout Interrupt is disabled. + 9 + 1 + read-write + + + RSE + Receive Stopped Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped Interrupt is disabled. + 8 + 1 + read-write + + + RUE + Receive Buffer Unavailable Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled. + 7 + 1 + read-write + + + RIE + Receive Interrupt Enable +When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Receive Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled. + 6 + 1 + read-write + + + UNE + Underflow Interrupt Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Underflow Interrupt is enabled. When this bit is reset, the Underflow Interrupt is disabled. + 5 + 1 + read-write + + + OVE + Overflow Interrupt Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Overflow Interrupt is enabled. When this bit is reset, the Overflow Interrupt is disabled. + 4 + 1 + read-write + + + TJE + Transmit Jabber Timeout Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, the Transmit Jabber Timeout Interrupt is disabled. + 3 + 1 + read-write + + + TUE + Transmit Buffer Unavailable Enable +When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled. + 2 + 1 + read-write + + + TSE + Transmit Stopped Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmission Stopped Interrupt is enabled. When this bit is reset, the Transmission Stopped Interrupt is disabled. + 1 + 1 + read-write + + + TIE + Transmit Interrupt Enable +When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Interrupt is enabled. When this bit is reset, the Transmit Interrupt is disabled. + 0 + 1 + read-write + + + + + DMA_MISS_OVF_CNT + Missed Frame And Buffer Overflow Counter Register + 0x1020 + 32 + 0x00000000 + 0x1FFFFFFF + + + ONFCNTOVF + Overflow Bit for FIFO Overflow Counter +This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows, that is, the Rx FIFO overflows with the overflow frame counter at maximum value. In such a scenario, the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened. + 28 + 1 + read-write + + + OVFFRMCNT + Overflow Frame Counter +This field indicates the number of frames missed by the application. This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read with mci_be_i[2] at 1’b1. + 17 + 11 + read-write + + + MISCNTOVF + Overflow Bit for Missed Frame Counter +This bit is set every time Missed Frame Counter (Bits[15:0]) overflows, that is, the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value. In such a scenario, the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened. + 16 + 1 + read-write + + + MISFRMCNT + Missed Frame Counter +This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with mci_be_i[0] at 1’b1. + 0 + 16 + read-write + + + + + DMA_RX_INTR_WDOG + Receive Interrupt Watchdog Timer Register + 0x1024 + 32 + 0x00000000 + 0x000000FF + + + RIWT + RI Watchdog Timer Count +This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer of a frame for which the RI status bit is not set because of the setting in the corresponding descriptor RDES1[31]. When the watchdog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame. + 0 + 8 + read-write + + + + + DMA_AXI_MODE + AXI Bus Mode Register + 0x1028 + 32 + 0x00000000 + 0xC0FF30FF + + + EN_LPI + Enable Low Power Interface (LPI) +When set to 1, this bit enables the LPI mode supported by the GMAC-AXI configuration and accepts the LPI request from the AXI System Clock controller. When set to 0, this bit disables the LPI mode and always denies the LPI request from the AXI System Clock controller. + 31 + 1 + read-write + + + LPI_XIT_FRM + Unlock on Magic Packet or Remote Wake-Up Frame +When set to 1, this bit enables the GMAC-AXI to come out of the LPI mode only when the magic packet or remote wake-up frame is received. When set to 0, this bit enables the GMAC-AXI to come out of LPI mode when any frame is received. + 30 + 1 + read-write + + + WR_OSR_LMT + AXI Maximum Write Outstanding Request Limit +This value limits the maximum outstanding request on the AXI write interface. Maximum outstanding requests = WR_OSR_LMT+1 Note: - Bit 22 is reserved if AXI_GM_MAX_WR_REQUESTS = 4. - Bit 23 bit is reserved if AXI_GM_MAX_WR_REQUESTS != 16. + 20 + 4 + read-write + + + RD_OSR_LMT + AXI Maximum Read Outstanding Request Limit +This value limits the maximum outstanding request on the AXI read interface. Maximum outstanding requests = RD_OSR_LMT+1 Note: - Bit 18 is reserved if AXI_GM_MAX_RD_REQUESTS = 4. - Bit 19 is reserved if AXI_GM_MAX_RD_REQUESTS != 16. + 16 + 4 + read-write + + + ONEKBBE + 1 KB Boundary Crossing Enable for the GMAC-AXI Master +When set, the GMAC-AXI master performs burst transfers that do not cross 1 KB boundary. When reset, the GMAC-AXI master performs burst transfers that do not cross 4 KB boundary. + 13 + 1 + read-write + + + AXI_AAL + Address-Aligned Beats +This bit is read-only bit and reflects the Bit 25 (AAL) of Register 0 (Bus Mode Register). When this bit is set to 1, the GMAC-AXI performs address-aligned burst transfers on both read and write channels. + 12 + 1 + read-write + + + BLEN256 + AXI Burst Length 256 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 256 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 256. Otherwise, this bit is reserved and is read-only (RO). + 7 + 1 + read-write + + + BLEN128 + AXI Burst Length 128 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 128 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 128 or more. Otherwise, this bit is reserved and is read-only (RO). + 6 + 1 + read-write + + + BLEN64 + AXI Burst Length 64 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 64 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 64 or more. Otherwise, this bit is reserved and is read-only (RO). + 5 + 1 + read-write + + + BLEN32 + AXI Burst Length 32 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 32 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 32 or more. Otherwise, this bit is reserved and is read-only (RO). + 4 + 1 + read-write + + + BLEN16 + AXI Burst Length 16 +When this bit is set to 1 or UNDEF is set to 1, the GMAC-AXI is allowed to select a burst length of 16 on the AXI master interface. + 3 + 1 + read-write + + + BLEN8 + AXI Burst Length 8 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 8 on the AXI master interface. Setting this bit has no effect when UNDEF is set to 1. + 2 + 1 + read-write + + + BLEN4 + AXI Burst Length 4 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 4 on the AXI master interface. Setting this bit has no effect when UNDEF is set to 1. + 1 + 1 + read-write + + + UNDEF + AXI Undefined Burst Length +This bit is read-only bit and indicates the complement (invert) value of Bit 16 (FB) in Register 0 (Bus Mode Register). - When this bit is set to 1, the GMAC-AXI is allowed to perform any burst length equal to or below the maximum allowed burst length programmed in Bits[7:3]. - When this bit is set to 0, the GMAC-AXI is allowed to perform only fixed burst lengths as indicated by BLEN256, BLEN128, BLEN64, BLEN32, BLEN16, BLEN8, or BLEN4, or a burst length of 1. If UNDEF is set and none of the BLEN bits is set, then GMAC-AXI is allowed to perform a burst length of 16. + 0 + 1 + read-write + + + + + DMA_BUS_STATUS + AHB or AXI Status Register + 0x102c + 32 + 0x00000000 + 0x00000003 + + + AXIRDSTS + AXI Master Read Channel Status +When high, it indicates that AXI master's read channel is active and transferring data. + 1 + 1 + read-write + + + AXWHSTS + AXI Master Write Channel or AHB Master Status +When high, it indicates that AXI master's write channel is active and transferring data in the GMAC-AXI configuration. In the GMAC-AHB configuration, it indicates that the AHB master interface FSMs are in the non-idle state. + 0 + 1 + read-write + + + + + DMA_CURR_HOST_TX_DESC + Current Host Transmit Descriptor Register + 0x1048 + 32 + 0x00000000 + 0xFFFFFFFF + + + CURTDESAPTR + Host Transmit Descriptor Address Pointer +Cleared on Reset. Pointer updated by the DMA during operation. + 0 + 32 + read-write + + + + + DMA_CURR_HOST_RX_DESC + Current Host Receive Descriptor Register + 0x104c + 32 + 0x00000000 + 0xFFFFFFFF + + + CURRDESAPTR + Host Receive Descriptor Address Pointer +Cleared on Reset. Pointer updated by the DMA during operation. + 0 + 32 + read-write + + + + + DMA_CURR_HOST_TX_BUF + Current Host Transmit Buffer Address Register + 0x1050 + 32 + 0x00000000 + 0xFFFFFFFF + + + CURTBUFAPTR + Host Transmit Buffer Address Pointer +Cleared on Reset. Pointer updated by the DMA during operation. + 0 + 32 + read-write + + + + + DMA_CURR_HOST_RX_BUF + Current Host Receive Buffer Address Register + 0x1054 + 32 + 0x00000000 + 0xFFFFFFFF + + + CURRBUFAPTR + Host Receive Buffer Address Pointer +Cleared on Reset. Pointer updated by the DMA during operation. + 0 + 32 + read-write + + + + + + + ENET1 + ENET1 + ENET + 0xf2004000 + + + NTMR0 + NTMR0 + TMR + 0xf2010000 + + 0x0 + 0x20c + registers + + + + 4 + 0x40 + ch0,ch1,ch2,ch3 + CHANNEL[%s] + no description available + 0x0 + + CR + Control Register + 0x0 + 32 + 0x00000000 + 0x80007FFF + + + CNTUPT + 1- update counter to new value as CNTUPTVAL +This bit will be auto cleared after 1 cycle + 31 + 1 + write-only + + + CNTRST + 1- reset counter + 14 + 1 + read-write + + + SYNCFLW + 1- enable this channel to reset counter to reload(RLD) together with its previous channel. +This bit is not valid for channel 0. + 13 + 1 + read-write + + + SYNCIFEN + 1- SYNCI is valid on its falling edge + 12 + 1 + read-write + + + SYNCIREN + 1- SYNCI is valid on its rising edge + 11 + 1 + read-write + + + CEN + 1- counter enable + 10 + 1 + read-write + + + CMPINIT + Output compare initial poliarity +1- The channel output initial level is high +0- The channel output initial level is low +User should set this bit before set CMPEN to 1. + 9 + 1 + read-write + + + CMPEN + 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. + 8 + 1 + read-write + + + DMASEL + select one of DMA request: +00- CMP0 flag +01- CMP1 flag +10- Input signal toggle captured +11- RLD flag, counter reload; + 6 + 2 + read-write + + + DMAEN + 1- enable dma + 5 + 1 + read-write + + + SWSYNCIEN + 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set + 4 + 1 + read-write + + + DBGPAUSE + 1- counter will pause if chip is in debug mode + 3 + 1 + read-write + + + CAPMODE + This bitfield define the input capture mode +100: width measure mode, timer will calculate the input signal period and duty cycle +011: capture at both rising edge and falling edge +010: capture at falling edge +001: capture at rising edge +000: No capture + 0 + 3 + read-write + + + + + 2 + 0x4 + CMP0,CMP1 + CMP[%s] + no description available + 0x4 + 32 + 0xFFFFFFF0 + 0xFFFFFFFF + + + CMP + compare value 0 + 0 + 32 + read-write + + + + + RLD + Reload register + 0xc + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + RLD + reload value + 0 + 32 + read-write + + + + + CNTUPTVAL + Counter update value register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTUPTVAL + counter will be set to this value when software write cntupt bit in CR + 0 + 32 + read-write + + + + + CAPPOS + Capture rising edge register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPOS + This register contains the counter value captured at input signal rising edge + 0 + 32 + read-only + + + + + CAPNEG + Capture falling edge register + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + This register contains the counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPPRD + PWM period measure register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPRD + This register contains the input signal period when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CAPDTY + PWM duty cycle measure register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + MEAS_HIGH + This register contains the input signal duty cycle when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CNT + Counter + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + 32 bit counter value + 0 + 32 + read-only + + + + + + SR + Status register + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH3CMP1F + channel 3 compare value 1 match flag + 15 + 1 + write-only + + + CH3CMP0F + channel 3 compare value 1 match flag + 14 + 1 + write-only + + + CH3CAPF + channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 13 + 1 + write-only + + + CH3RLDF + channel 3 counter reload flag + 12 + 1 + write-only + + + CH2CMP1F + channel 2 compare value 1 match flag + 11 + 1 + write-only + + + CH2CMP0F + channel 2 compare value 1 match flag + 10 + 1 + write-only + + + CH2CAPF + channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 9 + 1 + write-only + + + CH2RLDF + channel 2 counter reload flag + 8 + 1 + write-only + + + CH1CMP1F + channel 1 compare value 1 match flag + 7 + 1 + write-only + + + CH1CMP0F + channel 1 compare value 1 match flag + 6 + 1 + write-only + + + CH1CAPF + channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 5 + 1 + write-only + + + CH1RLDF + channel 1 counter reload flag + 4 + 1 + write-only + + + CH0CMP1F + channel 1 compare value 1 match flag + 3 + 1 + write-only + + + CH0CMP0F + channel 1 compare value 1 match flag + 2 + 1 + write-only + + + CH0CAPF + channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 1 + 1 + write-only + + + CH0RLDF + channel 1 counter reload flag + 0 + 1 + write-only + + + + + IRQEN + Interrupt request enable register + 0x204 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH3CMP1EN + 1- generate interrupt request when ch3cmp1f flag is set + 15 + 1 + read-write + + + CH3CMP0EN + 1- generate interrupt request when ch3cmp0f flag is set + 14 + 1 + read-write + + + CH3CAPEN + 1- generate interrupt request when ch3capf flag is set + 13 + 1 + read-write + + + CH3RLDEN + 1- generate interrupt request when ch3rldf flag is set + 12 + 1 + read-write + + + CH2CMP1EN + 1- generate interrupt request when ch2cmp1f flag is set + 11 + 1 + read-write + + + CH2CMP0EN + 1- generate interrupt request when ch2cmp0f flag is set + 10 + 1 + read-write + + + CH2CAPEN + 1- generate interrupt request when ch2capf flag is set + 9 + 1 + read-write + + + CH2RLDEN + 1- generate interrupt request when ch2rldf flag is set + 8 + 1 + read-write + + + CH1CMP1EN + 1- generate interrupt request when ch1cmp1f flag is set + 7 + 1 + read-write + + + CH1CMP0EN + 1- generate interrupt request when ch1cmp0f flag is set + 6 + 1 + read-write + + + CH1CAPEN + 1- generate interrupt request when ch1capf flag is set + 5 + 1 + read-write + + + CH1RLDEN + 1- generate interrupt request when ch1rldf flag is set + 4 + 1 + read-write + + + CH0CMP1EN + 1- generate interrupt request when ch0cmp1f flag is set + 3 + 1 + read-write + + + CH0CMP0EN + 1- generate interrupt request when ch0cmp0f flag is set + 2 + 1 + read-write + + + CH0CAPEN + 1- generate interrupt request when ch0capf flag is set + 1 + 1 + read-write + + + CH0RLDEN + 1- generate interrupt request when ch0rldf flag is set + 0 + 1 + read-write + + + + + GCR + Global control register + 0x208 + 32 + 0x00000000 + 0x0000000F + + + SWSYNCT + set this bitfield to trigger software counter sync event + 0 + 4 + read-write + + + + + + + NTMR1 + NTMR1 + TMR + 0xf2014000 + + + GPTMR0 + GPTMR0 + TMR + 0xf3000000 + + + GPTMR1 + GPTMR1 + TMR + 0xf3004000 + + + GPTMR2 + GPTMR2 + TMR + 0xf3008000 + + + GPTMR3 + GPTMR3 + TMR + 0xf300c000 + + + GPTMR4 + GPTMR4 + TMR + 0xf3010000 + + + GPTMR5 + GPTMR5 + TMR + 0xf3014000 + + + GPTMR6 + GPTMR6 + TMR + 0xf3018000 + + + GPTMR7 + GPTMR7 + TMR + 0xf301c000 + + + PTMR + PTMR + TMR + 0xf40e0000 + + + USB0 + USB0 + USB + 0xf2020000 + + 0x80 + 0x1a8 + registers + + + + GPTIMER0LD + General Purpose Timer #0 Load Register + 0x80 + 32 + 0x00000000 + 0x00FFFFFF + + + GPTLD + GPTLD +General Purpose Timer Load Value +These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. +This value represents the time in microseconds minus 1 for the timer duration. +Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. +NOTE: Max value is 0xFFFFFF or 16.777215 seconds. + 0 + 24 + read-write + + + + + GPTIMER0CTRL + General Purpose Timer #0 Controller Register + 0x84 + 32 + 0x00000000 + 0xC1FFFFFF + + + GPTRUN + GPTRUN +General Purpose Timer Run +GPTCNT bits are not effected when setting or clearing this bit. +0 - Stop counting +1 - Run + 31 + 1 + read-write + + + GPTRST + GPTRST +General Purpose Timer Reset +0 - No action +1 - Load counter value from GPTLD bits in n_GPTIMER0LD + 30 + 1 + write-only + + + GPTMODE + GPTMODE +General Purpose Timer Mode +In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is +reset by software; +In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the +counter value from GPTLD bits to start again. +0 - One Shot Mode +1 - Repeat Mode + 24 + 1 + read-write + + + GPTCNT + GPTCNT +General Purpose Timer Counter. +This field is the count value of the countdown timer. + 0 + 24 + read-only + + + + + GPTIMER1LD + General Purpose Timer #1 Load Register + 0x88 + 32 + 0x00000000 + 0x00FFFFFF + + + GPTLD + GPTLD +General Purpose Timer Load Value +These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. +This value represents the time in microseconds minus 1 for the timer duration. +Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. +NOTE: Max value is 0xFFFFFF or 16.777215 seconds. + 0 + 24 + read-write + + + + + GPTIMER1CTRL + General Purpose Timer #1 Controller Register + 0x8c + 32 + 0x00000000 + 0xC1FFFFFF + + + GPTRUN + GPTRUN +General Purpose Timer Run +GPTCNT bits are not effected when setting or clearing this bit. +0 - Stop counting +1 - Run + 31 + 1 + read-write + + + GPTRST + GPTRST +General Purpose Timer Reset +0 - No action +1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD + 30 + 1 + write-only + + + GPTMODE + GPTMODE +General Purpose Timer Mode +In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is +reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and +automatically reload the counter value from GPTLD bits to start again. +0 - One Shot Mode +1 - Repeat Mode + 24 + 1 + read-write + + + GPTCNT + GPTCNT +General Purpose Timer Counter. +This field is the count value of the countdown timer. + 0 + 24 + read-only + + + + + SBUSCFG + System Bus Config Register + 0x90 + 32 + 0x00000000 + 0x00000007 + + + AHBBRST + AHBBRST +AHB master interface Burst configuration +These bits control AHB master transfer type sequence (or priority). +NOTE: This register overrides n_BURSTSIZE register when its value is not zero. +000 - Incremental burst of unspecified length only +001 - INCR4 burst, then single transfer +010 - INCR8 burst, INCR4 burst, then single transfer +011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer +100 - Reserved, don't use +101 - INCR4 burst, then incremental burst of unspecified length +110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length +111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length + 0 + 3 + read-write + + + + + USBCMD + USB Command Register + 0x140 + 32 + 0x00080000 + 0x00FFEB7F + + + ITC + ITC +Interrupt Threshold Control -Read/Write. +The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. +ITC contains the maximum interrupt interval measured in micro-frames. Valid values are +shown below. +Value Maximum Interrupt Interval +00000000 - Immediate (no threshold) +00000001 - 1 micro-frame +00000010 - 2 micro-frames +00000100 - 4 micro-frames +00001000 - 8 micro-frames +00010000 - 16 micro-frames +00100000 - 32 micro-frames +01000000 - 64 micro-frames + 16 + 8 + read-write + + + FS_2 + FS_2 +Frame List Size - (Read/Write or Read Only). [host mode only] +This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. +This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. +NOTE: This field is made up from USBCMD bits 15, 3 and 2. +Value Meaning +0b000 - 1024 elements (4096 bytes) Default value +0b001 - 512 elements (2048 bytes) +0b010 - 256 elements (1024 bytes) +0b011 - 128 elements (512 bytes) +0b100 - 64 elements (256 bytes) +0b101 - 32 elements (128 bytes) +0b110 - 16 elements (64 bytes) +0b111 - 8 elements (32 bytes) + 15 + 1 + read-write + + + ATDTW + ATDTW +Add dTD TripWire - Read/Write. [device mode only] +This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's +linked list. This bit is set and cleared by software. +This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD +to a primed endpoint may go unrecognized. + 14 + 1 + read-write + + + SUTW + SUTW +Setup TripWire - Read/Write. [device mode only] +This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. +If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then +there is a hazard when new setup data arrives while the DCD is copying the setup data payload +from the QH for a previous setup packet. This bit is set and cleared by software. +This bit would also be cleared by hardware when a hazard detected. + 13 + 1 + read-write + + + ASPE + ASPE +Asynchronous Schedule Park Mode Enable - Read/Write. +If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. +Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. +When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. +NOTE: ASPE bit reset value: '0b' for OTG controller . + 11 + 1 + read-write + + + ASP + ASP +Asynchronous Schedule Park Mode Count - Read/Write. +If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. +It contains a count of the number of successive transactions the host controller is allowed to +execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. +Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. +This field is set to 3h in all controller core. + 8 + 2 + read-write + + + IAA + IAA +Interrupt on Async Advance Doorbell - Read/Write. +This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. +When the host controller has evicted all appropriate cached schedule states, +it sets the Interrupt on Async Advance status bit in the USBSTS register. +If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. +The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. +Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. +This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. + 6 + 1 + read-write + + + ASE + ASE +Asynchronous Schedule Enable - Read/Write. Default 0b. +This bit controls whether the host controller skips processing the Asynchronous Schedule. +Only the host controller uses this bit. +Values Meaning +0 - Do not process the Asynchronous Schedule. +1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. + 5 + 1 + read-write + + + PSE + PSE +Periodic Schedule Enable- Read/Write. Default 0b. +This bit controls whether the host controller skips processing the Periodic Schedule. +Only the host controller uses this bit. +Values Meaning +0 - Do not process the Periodic Schedule +1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. + 4 + 1 + read-write + + + FS_1 + FS_1 +See description at bit 15 + 2 + 2 + read-write + + + RST + RST +Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. +This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. +Host operation mode: +When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. +Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. +Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. +Attempting to reset an actively running host controller will result in undefined behavior. +Device operation mode: +When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. +Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. +In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. + 1 + 1 + read-write + + + RS + RS +Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. +Host operation mode: +When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. +When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. +The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. +Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). +Device operation mode: +Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. +This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. +Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. + 0 + 1 + read-write + + + + + USBSTS + USB Status Register + 0x144 + 32 + 0x00000000 + 0x030DF1FF + + + TI1 + TI1 +General Purpose Timer Interrupt 1(GPTINT1)--R/WC. +This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this +bit will clear it. + 25 + 1 + read-write + + + TI0 + TI0 +General Purpose Timer Interrupt 0(GPTINT0)--R/WC. +This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this +bit clears it. + 24 + 1 + read-write + + + UPI + USB Host Periodic Interrupt – RWC. Default = 0b. +This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction +where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. +This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. +A short packet is when the actual number of bytes received was less than expected. +This bit is not used by the device controller and will always be zero. + 19 + 1 + read-write + + + UAI + USB Host Asynchronous Interrupt – RWC. Default = 0b. +This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction +where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. +This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. +A short packet is when the actual number of bytes received was less than expected. +This bit is not used by the device controller and will always be zero + 18 + 1 + read-write + + + NAKI + NAKI +NAK Interrupt Bit--RO. +This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and +corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware +when all Enabled TX/RX Endpoint NAK bits are cleared. + 16 + 1 + read-only + + + AS + AS +Asynchronous Schedule Status - Read Only. +This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. +The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. +When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). +Only used in the host operation mode. + 15 + 1 + read-only + + + PS + PS +Periodic Schedule Status - Read Only. +This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. +The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. +When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). +Only used in the host operation mode. + 14 + 1 + read-only + + + RCL + RCL +Reclamation - Read Only. +This is a read-only status bit used to detect an empty asynchronous schedule. +Only used in the host operation mode. + 13 + 1 + read-only + + + HCH + HCH +HCHaIted - Read Only. +This bit is a zero whenever the Run/Stop bit is a one. + The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, + either by software or by the Controller hardware (for example, an internal error). +Only used in the host operation mode. +Default value is '0b' for OTG core . +This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE +register. +NOTE: HCH bit reset value: '0b' for OTG controller core . + 12 + 1 + read-only + + + SLI + SLI +DCSuspend - R/WC. +When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. +Only used in device operation mode. + 8 + 1 + read-write + + + SRI + SRI +SOF Received - R/WC. +When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. +When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. +Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. +Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. +In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. +Software writes a 1 to this bit to clear it. + 7 + 1 + read-write + + + URI + URI +USB Reset Received - R/WC. +When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. +Software can write a 1 to this bit to clear the USB Reset Received status bit. +Only used in device operation mode. + 6 + 1 + read-write + + + AAI + AAI +Interrupt on Async Advance - R/WC. +System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule +by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. +Only used in host operation mode. + 5 + 1 + read-write + + + SEI + System Error – RWC. Default = 0b. +In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. +In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) + 4 + 1 + read-write + + + FRI + FRI +Frame List Rollover - R/WC. +The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to +zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the +frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the +Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host +Controller sets this bit to a one every time FHINDEX [12] toggles. +Only used in host operation mode. + 3 + 1 + read-write + + + PCI + PCI +Port Change Detect - R/WC. +The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, +or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. +The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. +When the port controller exits the full or high-speed operation states due to Reset or Suspend events, +the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. + 2 + 1 + read-write + + + UEI + UEI +USB Error Interrupt (USBERRINT) - R/WC. +When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. +This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. + 1 + 1 + read-write + + + UI + UI +USB Interrupt (USBINT) - R/WC. +This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB +transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. +This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when +the actual number of bytes received was less than the expected number of bytes. + 0 + 1 + read-write + + + + + USBINTR + Interrupt Enable Register + 0x148 + 32 + 0x00000000 + 0x030D01FF + + + TIE1 + TIE1 +General Purpose Timer #1 Interrupt Enable +When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. + 25 + 1 + read-write + + + TIE0 + TIE0 +General Purpose Timer #0 Interrupt Enable +When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. + 24 + 1 + read-write + + + UPIE + UPIE +USB Host Periodic Interrupt Enable +When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an +interrupt at the next interrupt threshold. + 19 + 1 + read-write + + + UAIE + UAIE +USB Host Asynchronous Interrupt Enable +When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an +interrupt at the next interrupt threshold. + 18 + 1 + read-write + + + NAKE + NAKE +NAK Interrupt Enable +When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. + 16 + 1 + read-only + + + SLE + SLE +Sleep Interrupt Enable +When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. +Only used in device operation mode. + 8 + 1 + read-write + + + SRE + SRE +SOF Received Interrupt Enable +When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. + 7 + 1 + read-write + + + URE + URE +USB Reset Interrupt Enable +When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in device operation mode. + 6 + 1 + read-write + + + AAE + AAE +Async Advance Interrupt Enable +When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in host operation mode. + 5 + 1 + read-write + + + SEE + SEE +System Error Interrupt Enable +When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in host operation mode. + 4 + 1 + read-write + + + FRE + FRE +Frame List Rollover Interrupt Enable +When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in host operation mode. + 3 + 1 + read-write + + + PCE + PCE +Port Change Detect Interrupt Enable +When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. + 2 + 1 + read-write + + + UEE + UEE +USB Error Interrupt Enable +When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. + 1 + 1 + read-write + + + UE + UE +USB Interrupt Enable +When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. + 0 + 1 + read-write + + + + + FRINDEX + USB Frame Index Register + 0x14c + 32 + 0x00000000 + 0x00003FFF + + + FRINDEX + FRINDEX +Frame Index. +The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. +This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. +The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. +USBCMD [Frame List Size] Number Elements N +In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. +In either mode bits 2:0 indicate the current microframe. +The bit field values description below is represented as (Frame List Size) Number Elements N. +00000000000000 - (1024) 12 +00000000000001 - (512) 11 +00000000000010 - (256) 10 +00000000000011 - (128) 9 +00000000000100 - (64) 8 +00000000000101 - (32) 7 +00000000000110 - (16) 6 +00000000000111 - (8) 5 + 0 + 14 + read-write + + + + + DEVICEADDR + Device Address Register + UNION_154 + 0x154 + 32 + 0x00000000 + 0xFF000000 + + + USBADR + USBADR +Device Address. +These bits correspond to the USB device address + 25 + 7 + read-write + + + USBADRA + USBADRA +Device Address Advance. Default=0. +When this bit is '0', any writes to USBADR are instantaneous. + When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. +After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. +Hardware will automatically clear this bit on the following conditions: +1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). +2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). +3) Device Reset occurs (USBADR is reset to 0). +NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. +This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. +If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), +the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. + 24 + 1 + read-write + + + + + PERIODICLISTBASE + Frame List Base Address Register + UNION_154 + 0x154 + 32 + 0x00000000 + 0xFFFFF000 + + + BASEADR + BASEADR +Base Address (Low). +These bits correspond to memory address signals [31:12], respectively. +Only used by the host controller. + 12 + 20 + read-write + + + + + ASYNCLISTADDR + Next Asynch. Address Register + UNION_158 + 0x158 + 32 + 0x00000000 + 0xFFFFFFE0 + + + ASYBASE + ASYBASE +Link Pointer Low (LPL). +These bits correspond to memory address signals [31:5], respectively. This field may only reference a +Queue Head (QH). +Only used by the host controller. + 5 + 27 + read-write + + + + + ENDPTLISTADDR + Endpoint List Address Register + UNION_158 + 0x158 + 32 + 0x00000000 + 0xFFFFF800 + + + EPBASE + EPBASE +Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. +This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). + 11 + 21 + read-write + + + + + BURSTSIZE + Programmable Burst Size Register + 0x160 + 32 + 0x00000000 + 0x0000FFFF + + + TXPBURST + TXPBURST +Programmable TX Burst Size. +Default value is determined by TXBURST bits in n_HWTXBUF. +This register represents the maximum length of a the burst in 32-bit words while moving data from system +memory to the USB bus. + 8 + 8 + read-write + + + RXPBURST + RXPBURST +Programmable RX Burst Size. +Default value is determined by TXBURST bits in n_HWRXBUF. +This register represents the maximum length of a the burst in 32-bit words while moving data from the +USB bus to system memory. + 0 + 8 + read-write + + + + + TXFILLTUNING + TX FIFO Fill Tuning Register + 0x164 + 32 + 0x00000000 + 0x003F1F7F + + + TXFIFOTHRES + TXFIFOTHRES +FIFO Burst Threshold. (Read/Write) +This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. +The minimum value is 2 and this value should be a low as possible to maximize USB performance. +A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth +where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. +This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. + 16 + 6 + read-write + + + TXSCHHEALTH + TXSCHHEALTH +Scheduler Health Counter. (Read/Write To Clear) +Table continues on the next page +This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES +before running out of time to send the packet before the next Start-Of-Frame. +This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. +Writing to this register will clear the counter and this counter will max. at 31. + 8 + 5 + read-write + + + TXSCHOH + TXSCHOH +Scheduler Overhead. (Read/Write) [Default = 0] +This register adds an additional fixed offset to the schedule time estimator described above as Tff. +As an approximation, the value chosen for this register should limit the number of back-off events captured +in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. +Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. +The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. +The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. +Default value is '08h' for OTG controller core . + 0 + 7 + read-write + + + + + ENDPTNAK + Endpoint NAK Register + 0x178 + 32 + 0x00000000 + 0xFFFFFFFF + + + EPTN + EPTN +TX Endpoint NAK - R/WC. +Each TX endpoint has 1 bit in this field. The bit is set when the +device sends a NAK handshake on a received IN token for the corresponding endpoint. +Bit [N] - Endpoint #[N], N is 0-7 + 16 + 16 + read-write + + + EPRN + EPRN +RX Endpoint NAK - R/WC. +Each RX endpoint has 1 bit in this field. The bit is set when the +device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. +Bit [N] - Endpoint #[N], N is 0-7 + 0 + 16 + read-write + + + + + ENDPTNAKEN + Endpoint NAK Enable Register + 0x17c + 32 + 0x00000000 + 0xFFFFFFFF + + + EPTNE + EPTNE +TX Endpoint NAK Enable - R/W. +Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the +corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. +Bit [N] - Endpoint #[N], N is 0-7 + 16 + 16 + read-write + + + EPRNE + EPRNE +RX Endpoint NAK Enable - R/W. +Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the +corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. +Bit [N] - Endpoint #[N], N is 0-7 + 0 + 16 + read-write + + + + + PORTSC1 + Port Status & Control + 0x184 + 32 + 0x00000000 + 0x3DFF1FFF + + + STS + STS +Serial Transceiver Select +1 Serial Interface Engine is selected +0 Parallel Interface signals is selected +Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. +When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. + 29 + 1 + read-write + + + PTW + PTW +Parallel Transceiver Width +This bit has no effect if serial interface engine is used. +0 - Select the 8-bit UTMI interface [60MHz] +1 - Select the 16-bit UTMI interface [30MHz] + 28 + 1 + read-write + + + PSPD + PSPD +Port Speed - Read Only. +This register field indicates the speed at which the port is operating. +00 - Full Speed +01 - Low Speed +10 - High Speed +11 - Undefined + 26 + 2 + read-only + + + PFSC + PFSC +Port Force Full Speed Connect - Read/Write. Default = 0b. +When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp +sequence that allows the port to identify itself as High Speed. +0 - Normal operation +1 - Forced to full speed + 24 + 1 + read-write + + + PHCD + PHCD +PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. +When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY +clock. +NOTE: The PHY clock cannot be disabled if it is being used as the system clock. +In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD +Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend +will be cleared automatically when the host initials resume. Before forcing a resume from the device, the +device controller driver must clear this bit. +In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put +into suspend mode or when no downstream device is connected. Low power suspend is completely +under the control of software. +0 - Enable PHY clock +1 - Disable PHY clock + 23 + 1 + read-write + + + WKOC + WKOC +Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. +Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. +This field is zero if Port Power(PORTSC1) is zero. + 22 + 1 + read-write + + + WKDC + WKDC +Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables +the port to be sensitive to device disconnects as wake-up events. +This field is zero if Port Power(PORTSC1) is zero or in device mode. + 21 + 1 + read-write + + + WKCN + WKCN +Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. +Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. +This field is zero if Port Power(PORTSC1) is zero or in device mode. + 20 + 1 + read-write + + + PTC + PTC +Port Test Control - Read/Write. Default = 0000b. +Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. +The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. +Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. +Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. +NOTE: Low speed operations are not supported as a peripheral device. +Any other value than zero indicates that the port is operating in test mode. +Value Specific Test +0000 - TEST_MODE_DISABLE +0001 - J_STATE +0010 - K_STATE +0011 - SE0 (host) / NAK (device) +0100 - Packet +0101 - FORCE_ENABLE_HS +0110 - FORCE_ENABLE_FS +0111 - FORCE_ENABLE_LS +1000-1111 - Reserved + 16 + 4 + read-write + + + PP + PP +Port Power (PP)-Read/Write or Read Only. +The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: +PPC +PP Operation +0 +1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. +1 +1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). +When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. +When an over-current condition is detected on a powered port and PPC is a one, +the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). +This feature is implemented in all controller cores (PPC = 1). + 12 + 1 + read-write + + + LS + LS +Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal +lines. +In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because +the port controller state machine and the port routing manage the connection of LS and FS. +In device mode, the use of linestate by the device controller driver is not necessary. +The encoding of the bits are: +Bits [11:10] Meaning +00 - SE0 +01 - K-state +10 - J-state +11 - Undefined + 10 + 2 + read-only + + + HSP + HSP +High-Speed Port - Read Only. Default = 0b. +When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the +host/device connected to the port is not in a high-speed mode. +NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. + 9 + 1 + read-only + + + PR + PR +Port Reset - Read/Write or Read Only. Default = 0b. +In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. +When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. +This bit will automatically change to zero after the reset sequence is complete. +This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. +In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. + 8 + 1 + read-write + + + SUSP + SUSP +Suspend - Read/Write or Read Only. Default = 0b. +1=Port in suspend state. 0=Port not in suspend state. +In Host Mode: Read/Write. +Port Enabled Bit and Suspend bit of this register define the port states as follows: +Bits [Port Enabled, Suspend] Port State +0x Disable +10 Enable +11 Suspend +When in suspend state, downstream propagation of data is blocked on this port, except for port reset. +The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. +In the suspend state, the port is sensitive to resume detection. +Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. +The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. +If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: Read Only. +In device mode this bit is a read only status bit. + 7 + 1 + read-write + + + FPR + FPR +Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. +In Host Mode: +Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. +When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. +This bit will automatically change to zero after the resume sequence is complete. +This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. +Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. +The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. +Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. +This field is zero if Port Power(PORTSC1) is zero in host mode. +This bit is not-EHCI compatible. +In Device mode: +After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. +The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. +The bit will be cleared when the device returns to normal operation. + Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. + 6 + 1 + read-write + + + OCC + OCC +Over-current Change-R/WC. Default=0. +This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. + 5 + 1 + read-write + + + OCA + OCA +Over-current Active-Read Only. Default 0. +This bit will automatically transition from one to zero when the over current condition is removed. +0 - This port does not have an over-current condition. +1 - This port currently has an over-current condition + 4 + 1 + read-only + + + PEC + PEC +Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. +In Host Mode: +For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or +due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). +Software clears this by writing a one to it. +This field is zero if Port Power(PORTSC1) is zero. +In Device mode: +The device port is always enabled, so this bit is always '0b'. + 3 + 1 + read-write + + + PE + PE +Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. +In Host Mode: +Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. +Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. +Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. +When the port is disabled, (0b) downstream propagation of data is blocked except for reset. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: +The device port is always enabled, so this bit is always '1b'. + 2 + 1 + read-write + + + CSC + CSC +Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. +In Host Mode: +Indicates a change has occurred in the port's Current Connect Status. +The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. +For example, the insertion status changes twice before system software has cleared the changed condition, +hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: +This bit is undefined in device controller mode. + 1 + 1 + read-write + + + CCS + CCS +Current Connect Status-Read Only. +In Host Mode: +1=Device is present on port. 0=No device is present. Default = 0. +This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: +1=Attached. 0=Not Attached. Default=0. +A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. +A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. +It does not state the device being disconnected or Suspended. + 0 + 1 + read-write + + + + + OTGSC + On-The-Go Status & control Register + 0x1a4 + 32 + 0x00000000 + 0x07070723 + + + ASVIE + ASVIE +A Session Valid Interrupt Enable - Read/Write. + 26 + 1 + read-write + + + AVVIE + AVVIE +A VBus Valid Interrupt Enable - Read/Write. +Setting this bit enables the A VBus valid interrupt. + 25 + 1 + read-write + + + IDIE + IDIE +USB ID Interrupt Enable - Read/Write. +Setting this bit enables the USB ID interrupt. + 24 + 1 + read-write + + + ASVIS + ASVIS +A Session Valid Interrupt Status - Read/Write to Clear. +This bit is set when VBus has either risen above or fallen below the A session valid threshold. +Software must write a one to clear this bit. + 18 + 1 + read-write + + + AVVIS + AVVIS +A VBus Valid Interrupt Status - Read/Write to Clear. +This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. +Software must write a one to clear this bit. + 17 + 1 + read-write + + + IDIS + IDIS +USB ID Interrupt Status - Read/Write. +This bit is set when a change on the ID input has been detected. +Software must write a one to clear this bit. + 16 + 1 + read-write + + + ASV + ASV +A Session Valid - Read Only. +Indicates VBus is above the A session valid threshold. + 10 + 1 + read-only + + + AVV + AVV +A VBus Valid - Read Only. +Indicates VBus is above the A VBus valid threshold. + 9 + 1 + read-only + + + ID + ID +USB ID - Read Only. +0 = A device, 1 = B device + 8 + 1 + read-only + + + IDPU + IDPU +ID Pullup - Read/Write +This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input +will not be sampled. + 5 + 1 + read-write + + + VC + VC +VBUS Charge - Read/Write. +Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. + 1 + 1 + read-write + + + VD + VD +VBUS_Discharge - Read/Write. +Setting this bit causes VBus to discharge through a resistor. + 0 + 1 + read-write + + + + + USBMODE + USB Device Mode Register + 0x1a8 + 32 + 0x00000000 + 0x0000001F + + + SDIS + SDIS +Stream Disable Mode. (0 - Inactive [default]; 1 - Active) +Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. +This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. +Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. +Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems +where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. +NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for +the scheduler when using this feature. +NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. + 4 + 1 + read-write + + + SLOM + SLOM +Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . +0 - Setup Lockouts On (default); +1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. + 3 + 1 + read-write + + + ES + ES +Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the +host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected +by the value of this bit because they are based upon the 32-bit word. +Bit Meaning +0 - Little Endian [Default] +1 - Big Endian + 2 + 1 + read-write + + + CM + CM +Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only +implementations. For those designs that contain both host & device capability, the controller defaults to +an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ +device controllers, this register can only be written once after reset. If it is necessary to switch modes, +software must reset the controller by writing to the RESET bit in the USBCMD register before +reprogramming this register. +For OTG controller core, reset value is '00b'. +00 - Idle [Default for combination host/device] +01 - Reserved +10 - Device Controller [Default for device only controller] +11 - Host Controller [Default for host only controller] + 0 + 2 + read-write + + + + + ENDPTSETUPSTAT + Endpoint Setup Status Register + 0x1ac + 32 + 0x00000000 + 0x0000FFFF + + + ENDPTSETUPSTAT + ENDPTSETUPSTAT +Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. +Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. +The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. +This register is only used in device mode. + 0 + 16 + read-write + + + + + ENDPTPRIME + Endpoint Prime Register + 0x1b0 + 32 + 0x00000000 + 0xFFFFFFFF + + + PETB + PETB +Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a +buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. +Software should write a one to the corresponding bit when posting a new transfer descriptor to an +endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor +from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated +endpoint(s) is (are) successfully primed. +NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD +is retired, and the dQH is updated. +PETB[N] - Endpoint #N, N is in 0..7 + 16 + 16 + read-write + + + PERB + PERB +Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. +Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. +Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. +Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. +NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD +is retired, and the dQH is updated. +PERB[N] - Endpoint #N, N is in 0..7 + 0 + 16 + read-write + + + + + ENDPTFLUSH + Endpoint Flush Register + 0x1b4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FETB + FETB +Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. +If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. +Hardware clears this register after the endpoint flush operation is successful. +FETB[N] - Endpoint #N, N is in 0..7 + 16 + 16 + read-write + + + FERB + FERB +Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. + If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. +Hardware clears this register after the endpoint flush operation is successful. +FERB[N] - Endpoint #N, N is in 0..7 + 0 + 16 + read-write + + + + + ENDPTSTAT + Endpoint Status Register + 0x1b8 + 32 + 0x00000000 + 0xFFFFFFFF + + + ETBR + ETBR +Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. +This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. +There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. +This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. +Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. +NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. +ETBR[N] - Endpoint #N, N is in 0..7 + 16 + 16 + read-only + + + ERBR + ERBR +Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective +endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a +corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the +ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB +traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the +USB DMA system, or through the ENDPTFLUSH register. +NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations +when a dTD is retired, and the dQH is updated. +ERBR[N] - Endpoint #N, N is in 0..7 + 0 + 16 + read-only + + + + + ENDPTCOMPLETE + Endpoint Complete Register + 0x1bc + 32 + 0x00000000 + 0xFFFFFFFF + + + ETCE + ETCE +Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. +If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. +ETCE[N] - Endpoint #N, N is in 0..7 + 16 + 16 + read-write + + + ERCE + ERCE +Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred +and software should read the corresponding endpoint queue to determine the transfer status. If the +corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the +USBINT . Writing one clears the corresponding bit in this register. +ERCE[N] - Endpoint #N, N is in 0..7 + 0 + 16 + read-write + + + + + 8 + 0x4 + ENDPTCTRL0,ENDPTCTRL1,ENDPTCTRL2,ENDPTCTRL3,ENDPTCTRL4,ENDPTCTRL5,ENDPTCTRL6,ENDPTCTRL7 + ENDPTCTRL[%s] + no description available + 0x1c0 + 32 + 0x00000000 + 0x00CD00CD + + + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 + read-write + + + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 + 1 + write-only + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 + read-write + + + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured +as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 + 1 + read-write + + + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 + 1 + read-write + + + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 + 1 + write-only + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 + read-write + + + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 + 1 + read-write + + + + + OTG_CTRL0 + No description available + 0x200 + 32 + 0x00000000 + 0x020B3F90 + + + OTG_WKDPDMCHG_EN + No description available + 25 + 1 + read-write + + + AUTORESUME_EN + No description available + 19 + 1 + read-write + + + OTG_VBUS_WAKEUP_EN + No description available + 17 + 1 + read-write + + + OTG_ID_WAKEUP_EN + No description available + 16 + 1 + read-write + + + OTG_VBUS_SOURCE_SEL + No description available + 13 + 1 + read-write + + + OTG_UTMI_SUSPENDM_SW + default 0 for naneng usbphy + 12 + 1 + read-write + + + OTG_UTMI_RESET_SW + default 1 for naneng usbphy + 11 + 1 + read-write + + + OTG_WAKEUP_INT_ENABLE + No description available + 10 + 1 + read-write + + + OTG_POWER_MASK + No description available + 9 + 1 + read-write + + + OTG_OVER_CUR_POL + No description available + 8 + 1 + read-write + + + OTG_OVER_CUR_DIS + No description available + 7 + 1 + read-write + + + SER_MODE_SUSPEND_EN + for naneng usbphy, only switch to serial mode when suspend + 4 + 1 + read-write + + + + + PHY_CTRL0 + No description available + 0x210 + 32 + 0x00000000 + 0x02007007 + + + GPIO_ID_SEL_N + No description available + 25 + 1 + read-write + + + ID_DIG_OVERRIDE + No description available + 14 + 1 + read-write + + + SESS_VALID_OVERRIDE + No description available + 13 + 1 + read-write + + + VBUS_VALID_OVERRIDE + No description available + 12 + 1 + read-write + + + ID_DIG_OVERRIDE_EN + No description available + 2 + 1 + read-write + + + SESS_VALID_OVERRIDE_EN + No description available + 1 + 1 + read-write + + + VBUS_VALID_OVERRIDE_EN + No description available + 0 + 1 + read-write + + + + + PHY_CTRL1 + No description available + 0x214 + 32 + 0x00000000 + 0x00100002 + + + UTMI_CFG_RST_N + No description available + 20 + 1 + read-write + + + UTMI_OTG_SUSPENDM + OTG suspend, not utmi_suspendm + 1 + 1 + read-write + + + + + TOP_STATUS + No description available + 0x220 + 32 + 0x00000000 + 0x80000000 + + + WAKEUP_INT_STATUS + No description available + 31 + 1 + read-write + + + + + PHY_STATUS + No description available + 0x224 + 32 + 0x00000000 + 0x800000F5 + + + UTMI_CLK_VALID + No description available + 31 + 1 + read-write + + + LINE_STATE + No description available + 6 + 2 + read-write + + + HOST_DISCONNECT + No description available + 5 + 1 + read-write + + + ID_DIG + No description available + 4 + 1 + read-write + + + UTMI_SESS_VALID + No description available + 2 + 1 + read-write + + + VBUS_VALID + No description available + 0 + 1 + read-write + + + + + + + USB1 + USB1 + USB + 0xf2024000 + + + SDXC0 + SDXC0 + SDXC + 0xf2030000 + + 0x0 + 0x548 + registers + + + + SDMASA + No description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + BLOCKCNT_SDMASA + 32-bit Block Count (SDMA System Address) +- SDMA System Address (Host Version 4 Enable = 0): This register contains the system memory address for an SDMA transfer in the 32-bit addressing mode. +When the Host Controller stops an SDMA transfer, this register points to the system address of the next contiguous data position. +It can be accessed only if no transaction is executing. Reading this register during data transfers may +return an invalid value. +- 32-bit Block Count (Host Version 4 Enable = 1): From the Host Controller Version 4.10 specification, this register is redefined as 32-bit Block Count. +The Host Controller decrements the block count of this register for every block transfer and the data transfer stops when the count reaches zero. +This register must be accessed when no transaction is executing. Reading this register during data transfers may return invalid value. +Following are the values for BLOCKCNT_SDMASA: +- 0xFFFF_FFFF: 4G - 1 Block +- +- 0x0000_0002: 2 Blocks +- 0x0000_0001: 1 Block +- 0x0000_0000: Stop Count +Note: +- For Host Version 4 Enable = 0, the Host driver does not program the system address in this register while operating in ADMA mode. +The system address must be programmed in the ADMA System Address register. +- For Host Version 4 Enable = 0, the Host driver programs a non-zero 32-bit block count value in this register when Auto CMD23 is enabled for non-DMA and ADMA modes. +Auto CMD23 cannot be used with SDMA. +- This register must be programmed with a non-zero value for data transfer if the 32-bit Block count register is used instead of the 16-bit Block count register. + 0 + 32 + read-write + + + + + BLK_ATTR + No description available + 0x4 + 32 + 0x00020210 + 0xFFFF7FFF + + + BLOCK_CNT + 16-bit Block Count +- If the Host Version 4 Enable bit is set 0 or the 16-bit Block Count register is set to non-zero, the 16-bit Block Count register is selected. +- If the Host Version 4 Enable bit is set 1 and the 16-bit Block Count register is set to zero, the 32-bit Block Count register is selected. +Following are the values for BLOCK_CNT: +- 0x0: Stop Count +- 0x1: 1 Block +- 0x2: 2 Blocks +- . +- 0xFFFF: 65535 Blocks +Note: For Host Version 4 Enable = 0, this register must be set to 0000h before programming the 32-bit block count register when Auto CMD23 is enabled for non-DMA and ADMA modes. + 16 + 16 + read-write + + + SDMA_BUF_BDARY + SDMA Buffer Boundary +These bits specify the size of contiguous buffer in system memory. +The SDMA transfer waits at every boundary specified by these fields and the Host Controller generates the DMA interrupt to request the Host Driver to update the SDMA System Address register. +Values: +- 0x0 (BYTES_4K): 4K bytes SDMA Buffer Boundary +- 0x1 (BYTES_8K): 8K bytes SDMA Buffer Boundary +- 0x2 (BYTES_16K): 16K bytes SDMA Buffer Boundary +- 0x3 (BYTES_32K): 32K bytes SDMA Buffer Boundary +- 0x4 (BYTES_64K): 64K bytes SDMA Buffer Boundary +- 0x5 (BYTES_128K): 128K bytes SDMA Buffer Boundary +- 0x6 (BYTES_256K): 256K bytes SDMA Buffer Boundary +- 0x7 (BYTES_512K): 512K bytes SDMA Buffer Boundary + 12 + 3 + read-write + + + XFER_BLOCK_SIZE + Transfer Block Size +These bits specify the block size of data transfers. In case of memory, it is set to 512 bytes. It can be accessed only if no transaction is executing. +Read operations during transfers may return an invalid value, and write operations are ignored. Following are the values for XFER_BLOCK_SIZE: +- 0x1: 1 byte +- 0x2: 2 bytes +- 0x3: 3 bytes +- . +- 0x1FF: 511 byte +- 0x200: 512 byt es +- . +- 0x800: 2048 bytes +Note: This register must be programmed with a non-zero value for data transfer. + 0 + 12 + read-write + + + + + CMD_ARG + No description available + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + ARGUMNET + Command Argument +These bits specify the SD/eMMC command argument that is specified in bits 39-8 of the Command format. + 0 + 32 + read-write + + + + + CMD_XFER + No description available + 0xc + 32 + 0x00000000 + 0x3FFF01FF + + + CMD_INDEX + Command Index +These bits are set to the command number that is specified in bits 45-40 of the Command Format. + 24 + 6 + read-write + + + CMD_TYPE + Command Type +These bits indicate the command type. +Note: While issuing Abort CMD using CMD12/CMD52 or reset CMD using CMD0/CMD52, CMD_TYPE field shall be set to 0x3. +Values: +0x3 (ABORT_CMD): Abort +0x2 (RESUME_CMD): Resume +0x1 (SUSPEND_CMD): Suspend +0x0 (NORMAL_CMD): Normal + 22 + 2 + read-write + + + DATA_PRESENT_SEL + Data Present Select +This bit is set to 1 to indicate that data is present and that the data is transferred using the DAT line. This bit is set to 0 in the following instances: +Command using the CMD line +Command with no data transfer but using busy signal on the DAT[0] line +Resume Command +Values: +0x0 (NO_DATA): No Data Present +0x1 (DATA): Data Present + 21 + 1 + read-write + + + CMD_IDX_CHK_ENABLE + Command Index Check Enable +This bit enables the Host Controller to check the index field in the response to verify if it has the same value as the command index. +If the value is not the same, it is reported as a Command Index error. +Note: +Index Check enable must be set to 0 for the command with no response, R2 response, R3 response and R4 response. +For the tuning command, this bit must always be set to enable the index check. +Values: +0x0 (DISABLED): Disable +0x1 (ENABLED): Enable + 20 + 1 + read-write + + + CMD_CRC_CHK_ENABLE + Command CRC Check Enable +This bit enables the Host Controller to check the CRC field in the response. If an error is detected, it is reported as a Command CRC error. +Note: +CRC Check enable must be set to 0 for the command with no response, R3 response, and R4 response. +For the tuning command, this bit must always be set to 1 to enable the CRC check. +Values: +0x0 (DISABLED): Disable +0x1 (ENABLED): Enable + 19 + 1 + read-write + + + SUB_CMD_FLAG + Sub Command Flag +This bit distinguishes between a main command and a sub command. +Values: +0x0 (MAIN): Main Command +0x1 (SUB): Sub Command + 18 + 1 + read-write + + + RESP_TYPE_SELECT + Response Type Select +This bit indicates the type of response expected from the card. +Values: +0x0 (NO_RESP): No Response +0x1 (RESP_LEN_136): Response Length 136 +0x2 (RESP_LEN_48): Response Length 48 +0x3 (RESP_LEN_48B): Response Length 48; Check Busy after response + 16 + 2 + read-write + + + RESP_INT_DISABLE + Response Interrupt Disable +The Host Controller supports response check function to avoid overhead of response error check by the Host driver. +Response types of only R1 and R5 can be checked by the Controller. +If Host Driver checks the response error, set this bit to 0 and wait for Command Complete Interrupt and then check the response register. +If the Host Controller checks the response error, set this bit to 1 and set the Response Error Check Enable bit to 1. +The Command Complete Interrupt is disabled by this bit regardless of the Command Complete Signal Enable. +Note: During tuning (when the Execute Tuning bit in the Host Control2 register is set), the Command Complete Interrupt is not generated irrespective of the Response Interrupt Disable setting. +Values: +- 0x0 (ENABLED): Response Interrupt is enabled +- 0x1 (DISABLED): Response Interrupt is disabled + 8 + 1 + read-write + + + RESP_ERR_CHK_ENABLE + Response Error Check Enable +The Host Controller supports response check function to avoid overhead of response error check by Host driver. Response types of only R1 and R5 can be checked by the Controller. +If the Host Controller checks the response error, set this bit to 1 and set Response Interrupt Disable to 1. If an error is detected, the Response Error interrupt is generated in the Error Interrupt Status register. +Note: +- Response error check must not be enabled for any response type other than R1 and R5. +- Response check must not be enabled for the tuning command. +Values: +- 0x0 (DISABLED): Response Error Check is disabled +- 0x1 (ENABLED): Response Error Check is enabled + 7 + 1 + read-write + + + RESP_TYPE + Response Type R1/R5 +This bit selects either R1 or R5 as a response type when the Response Error Check is selected. +Error statuses checked in R1: +OUT_OF_RANGE +ADDRESS_ERROR +BLOCK_LEN_ERROR +WP_VIOLATION +CARD_IS_LOCKED +COM_CRC_ERROR +CARD_ECC_FAILED +CC_ERROR +ERROR +Response Flags checked in R5: +COM_CRC_ERROR +ERROR +FUNCTION_NUMBER +OUT_OF_RANGE +Values: +0x0 (RESP_R1): R1 (Memory) +0x1 (RESP_R5): R5 (SDIO) + 6 + 1 + read-write + + + MULTI_BLK_SEL + Multi/Single Block Select +This bit is set when issuing multiple-block transfer commands using the DAT line. If this bit is set to 0, it is not necessary to set the Block Count register. +Values: +0x0 (SINGLE): Single Block +0x1 (MULTI): Multiple Block + 5 + 1 + read-write + + + DATA_XFER_DIR + Data Transfer Direction Select +This bit defines the direction of DAT line data transfers. +This bit is set to 1 by the Host Driver to transfer data from the SD/eMMC card to the Host Controller and it is set to 0 for all other commands. +Values: +0x1 (READ): Read (Card to Host) +0x0 (WRITE): Write (Host to Card) + 4 + 1 + read-write + + + AUTO_CMD_ENABLE + Auto Command Enable +This field determines use of Auto Command functions. +Note: In SDIO, this field must be set as 00b (Auto Command Disabled). +Values: +0x0 (AUTO_CMD_DISABLED): Auto Command Disabled +0x1 (AUTO_CMD12_ENABLED): Auto CMD12 Enable +0x2 (AUTO_CMD23_ENABLED): Auto CMD23 Enable +0x3 (AUTO_CMD_AUTO_SEL): Auto CMD Auto Sel + 2 + 2 + read-write + + + BLOCK_COUNT_ENABLE + Block Count Enable +This bit is used to enable the Block Count register, which is relevant for multiple block transfers. +If this bit is set to 0, the Block Count register is disabled, which is useful in executing an infinite transfer. +The Host Driver must set this bit to 0 when ADMA is used. +Values: +0x1 (ENABLED): Enable +0x0 (DISABLED): Disable + 1 + 1 + read-write + + + DMA_ENABLE + DMA Enable +This bit enables the DMA functionality. If this bit is set to 1, a DMA operation begins when the Host Driver writes to the Command register. +You can select one of the DMA modes by using DMA Select in the Host Control 1 register. +Values: +0x1 (ENABLED): DMA Data transfer +0x0 (DISABLED): No data transfer or Non-DMA data transfer + 0 + 1 + read-write + + + + + 4 + 0x4 + RESP01,RESP23,RESP45,RESP67 + RESP[%s] + no description available + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESP01 + Command Response +These bits reflect 39-8 bits of SD/eMMC Response Field. +Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP[RESP67] register. + 0 + 32 + read-only + + + + + BUF_DATA + No description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + BUF_DATA + Buffer Data +These bits enable access to the Host Controller packet buffer. + 0 + 32 + read-write + + + + + PSTATE + No description available + 0x24 + 32 + 0x00000000 + 0x19FF0FFF + + + SUB_CMD_STAT + Sub Command Status +This bit is used to distinguish between a main command and a sub command status. +Values: +0x0 (FALSE): Main Command Status +0x1 (TRUE): Sub Command Status + 28 + 1 + read-only + + + CMD_ISSUE_ERR + Command Not Issued by Error +This bit is set if a command cannot be issued after setting the command register due to an error except the Auto CMD12 error. +Values: +0x0 (FALSE): No error for issuing a command +0x1 (TRUE): Command cannot be issued + 27 + 1 + read-only + + + CMD_LINE_LVL + Command-Line Signal Level +This bit is used to check the CMD line level to recover from errors and for debugging. These bits reflect the value of the sd_cmd_in signal. + 24 + 1 + read-only + + + DAT_3_0 + DAT[3:0] Line Signal Level +This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (lower nibble) signal. + 20 + 4 + read-only + + + WR_PROTECT_SW_LVL + Write Protect Switch Pin Level +This bit is supported only for memory and combo cards. This bit reflects the synchronized value of the card_write_prot signal. +Values: +0x0 (FALSE): Write protected +0x1 (TRUE): Write enabled + 19 + 1 + read-only + + + CARD_DETECT_PIN_LEVEL + Card Detect Pin Level +This bit reflects the inverse synchronized value of the card_detect_n signal. +Values: +0x0 (FALSE): No card present +0x1 (TRUE): Card Present + 18 + 1 + read-only + + + CARD_STABLE + Card Stable +This bit indicates the stability of the Card Detect Pin Level. A card is not detected if this bit is set to 1 and the value of the CARD_INSERTED bit is 0. +Values: +0x0 (FALSE): Reset or Debouncing +0x1 (TRUE): No Card or Inserted + 17 + 1 + read-only + + + CARD_INSERTED + Card Inserted +This bit indicates whether a card has been inserted. The Host Controller debounces this signal so that Host Driver need not wait for it to stabilize. +Values: +0x0 (FALSE): Reset, Debouncing, or No card +0x1 (TRUE): Card Inserted + 16 + 1 + read-only + + + BUF_RD_ENABLE + Buffer Read Enable +This bit is used for non-DMA transfers. This bit is set if valid data exists in the Host buffer. +Values: +0x0 (DISABLED): Read disable +0x1 (ENABLED): Read enable + 11 + 1 + read-only + + + BUF_WR_ENABLE + Buffer Write Enable +This bit is used for non-DMA transfers. This bit is set if space is available for writing data. +Values: +0x0 (DISABLED): Write disable +0x1 (ENABLED): Write enable + 10 + 1 + read-only + + + RD_XFER_ACTIVE + Read Transfer Active +This bit indicates whether a read transfer is active for SD/eMMC mode. +Values: +0x0 (INACTIVE): No valid data +0x1 (ACTIVE): Transferring data + 9 + 1 + read-only + + + WR_XFER_ACTIVE + Write Transfer Active +This status indicates whether a write transfer is active for SD/eMMC mode. +Values: +0x0 (INACTIVE): No valid data +0x1 (ACTIVE): Transferring data + 8 + 1 + read-only + + + DAT_7_4 + DAT[7:4] Line Signal Level +This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (upper nibble) signal. + 4 + 4 + read-only + + + RE_TUNE_REQ + Re-Tuning Request +SDXC does not generate retuning request. The software must maintain the Retuning timer. + 3 + 1 + read-only + + + DAT_LINE_ACTIVE + DAT Line Active ( +This bit indicates whether one of the DAT lines on the SD/eMMC bus is in use. +In the case of read transactions, this bit indicates whether a read transfer is executing on the SD/eMMC bus. +In the case of write transactions, this bit indicates whether a write transfer is executing on the SD/eMMC bus. +For a command with busy, this status indicates whether the command executing busy is executing on an SD or eMMC bus. +Values: +0x0 (INACTIVE): DAT Line Inactive +0x1 (ACTIVE): DAT Line Active + 2 + 1 + read-only + + + DAT_INHIBIT + Command Inhibit (DAT) +This bit is generated if either DAT line active or Read transfer active is set to 1. +If this bit is set to 0, it indicates that the Host Controller can issue subsequent SD/eMMC commands. +Values: +0x0 (READY): Can issue command which used DAT line +0x1 (NOT_READY): Cannot issue command which used DAT line + 1 + 1 + read-only + + + CMD_INHIBIT + Command Inhibit (CMD) +This bit indicates the following : +If this bit is set to 0, it indicates that the CMD line is not in use and the Host controller can issue an SD/eMMC command using the CMD line. +This bit is set when the command register is written. This bit is cleared when the command response is received. +This bit is not cleared by the response of auto CMD12/23 but cleared by the response of read/write command. +Values: +0x0 (READY): Host Controller is ready to issue a command +0x1 (NOT_READY): Host Controller is not ready to issue a command + 0 + 1 + read-only + + + + + PROT_CTRL + No description available + 0x28 + 32 + 0x00000000 + 0x070F0F3E + + + CARD_REMOVAL + Wakeup Event Enable on SD Card Removal +This bit enables wakeup event through Card Removal assertion in the Normal Interrupt Status register. +For the SDIO card, Wake Up Support (FN_WUS) in the Card Information Structure (CIS) register does not affect this bit. +Values: +0x0 (DISABLED): Disable +0x1 (ENABLED): Enable + 26 + 1 + read-write + + + CARD_INSERT + Wakeup Event Enable on SD Card Insertion +This bit enables wakeup event through Card Insertion assertion in the Normal Interrupt Status register. +FN_WUS (Wake Up Support) in CIS does not affect this bit. +Values: +0x0 (DISABLED): Disable +0x1 (ENABLED): Enable + 25 + 1 + read-write + + + CARD_INT + Wakeup Event Enable on Card Interrupt +This bit enables wakeup event through a Card Interrupt assertion in the Normal Interrupt Status register. +This bit can be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1. +Values: +0x0 (DISABLED): Disable +0x1 (ENABLED): Enable + 24 + 1 + read-write + + + INT_AT_BGAP + Interrupt At Block Gap +This bit is valid only in the 4-bit mode of an SDIO card and is used to select a sample point in the interrupt cycle. +Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. +Values: +0x0 (DISABLE): Disabled +0x1 (ENABLE): Enabled + 19 + 1 + read-write + + + RD_WAIT_CTRL + Read Wait Control +This bit is used to enable the read wait protocol to stop read data using DAT[2] line if the card supports read wait. +Otherwise, the Host Controller has to stop the card clock to hold the read data. In UHS-II mode, Read Wait is disabled. +Values: +0x0 (DISABLE): Disable Read Wait Control +0x1 (ENABLE): Enable Read Wait Control + 18 + 1 + read-write + + + CONTINUE_REQ + Continue Request +This bit is used to restart the transaction, which was stopped using the Stop At Block Gap Request. +The Host Controller automatically clears this bit when the transaction restarts. +If stop at block gap request is set to 1, any write to this bit is ignored. +Values: +0x0 (NO_AFFECT): No Affect +0x1 (RESTART): Restart + 17 + 1 + read-write + + + STOP_BG_REQ + Stop At Block Gap Request +This bit is used to stop executing read and write transactions at the next block gap for non-DMA, SDMA, and ADMA transfers. +Values: +0x0 (XFER): Transfer +0x1 (STOP): Stop + 16 + 1 + read-write + + + SD_BUS_VOL_VDD1 + SD Bus Voltage Select for VDD1/eMMC Bus Voltage Select for VDD +These bits enable the Host Driver to select the voltage level for an SD/eMMC card. +Before setting this register, the Host Driver checks the Voltage Support bits in the Capabilities register. +If an unsupported voltage is selected, the Host System does not supply the SD Bus voltage. +The value set in this field is available on the SDXC output signal (sd_vdd1_sel), which is used by the voltage switching circuitry. +SD Bus Voltage Select options: +0x7 : 3.3V(Typical) +0x6 : 3.0V(Typical) +0x5 : 1.8V(Typical) for Embedded +0x4 : 0x0 - Reserved +eMMC Bus Voltage Select options: +0x7 : 3.3V(Typical) +0x6 : 1.8V(Typical) +0x5 : 1.2V(Typical) +0x4 : 0x0 - Reserved +Values: +0x7 (V_3_3): 3.3V (Typ.) +0x6 (V_3_0): 3.0V (Typ.) +0x5 (V_1_8): 1.8V (Typ.) for Embedded +0x4 (RSVD4): Reserved +0x3 (RSVD3): Reserved +0x2 (RSVD2): Reserved +0x1 (RSVD1): Reserved +0x0 (RSVD0): Reserved + 9 + 3 + read-write + + + SD_BUS_PWR_VDD1 + SD Bus Power for VDD1 +This bit enables VDD1 power of the card. +This setting is available on the sd_vdd1_on output of SDXC so that it can be used to control the VDD1 power supply of the card. +Before setting this bit, the SD Host Driver sets the SD Bus Voltage Select bit. If the Host Controller detects a No Card state, this bit is cleared. +In SD mode, if this bit is cleared, the Host Controller stops the SD Clock by clearing the SD_CLK_EN bit in the SYS_CTRL register. +Values: +0x0 (OFF): Power off +0x1 (ON): Power on + 8 + 1 + read-write + + + EXT_DAT_XFER + Extended Data Transfer Width +This bit controls 8-bit bus width mode of embedded device. +Values: +0x1 (EIGHT_BIT): 8-bit Bus Width +0x0 (DEFAULT): Bus Width is selected by the Data Transfer Width + 5 + 1 + read-write + + + DMA_SEL + DMA Select +This field is used to select the DMA type. +When Host Version 4 Enable is 1 in Host Control 2 register: +0x0 : SDMA is selected +0x1 : Reserved +0x2 : ADMA2 is selected +0x3 : ADMA2 or ADMA3 is selected +When Host Version 4 Enable is 0 in Host Control 2 register: +0x0 : SDMA is selected +0x1 : Reserved +0x2 : 32-bit Address ADMA2 is selected +0x3 : 64-bit Address ADMA2 is selected +Values: +0x0 (SDMA): SDMA is selected +0x1 (RSVD_BIT): Reserved +0x2 (ADMA2): ADMA2 is selected +0x3 (ADMA2_3): ADMA2 or ADMA3 is selected + 3 + 2 + read-write + + + HIGH_SPEED_EN + High Speed Enable +this bit is used to determine the selection of preset value for High Speed mode. +Before setting this bit, the Host Driver checks the High Speed Support in the Capabilities register. +Note: SDXC always outputs the sd_cmd_out and sd_dat_out lines at the rising edge of cclk_tx clock irrespective of this bit. +Values: +0x1 (HIGH_SPEED): High Speed mode +0x0 (NORMAL_SPEED): Normal Speed mode + 2 + 1 + read-write + + + DAT_XFER_WIDTH + Data Transfer Width +For SD/eMMC mode,this bit selects the data transfer width of the Host Controller. +The Host Driver sets it to match the data width of the SD/eMMC card. In UHS-II mode, this bit is irrelevant. +Values: +0x1 (FOUR_BIT): 4-bit mode +0x0 (ONE_BIT): 1-bit mode + 1 + 1 + read-write + + + + + SYS_CTRL + No description available + 0x2c + 32 + 0x00000000 + 0x070FFFEF + + + SW_RST_DAT + Software Reset For DAT line +This bit is used in SD/eMMC mode and it resets only a part of the data circuit and the DMA circuit is also reset. +The following registers and bits are cleared by this bit: +Buffer Data Port register +-Buffer is cleared and initialized. +Present state register +-Buffer Read Enable +-Buffer Write Enable +-Read Transfer Active +-Write Transfer Active +-DAT Line Active +-Command Inhibit (DAT) +Block Gap Control register +-Continue Request +-Stop At Block Gap Request +Normal Interrupt status register +-Buffer Read Ready +-Buffer Write Ready +-DMA Interrupt +-Block Gap Event +-Transfer Complete +In UHS-II mode, this bit shall be set to 0 +Values: +0x0 (FALSE): Work +0x1 (TRUE): Reset + 26 + 1 + read-write + + + SW_RST_CMD + Software Reset For CMD line +This bit resets only a part of the command circuit to be able to issue a command. +It bit is also used to initialize a UHS-II command circuit. +This reset is effective only for a command issuing circuit (including response error statuses related to Command Inhibit (CMD) control) and does not affect the data transfer circuit. +Host Controller can continue data transfer even after this reset is executed while handling subcommand-response errors. +The following registers and bits are cleared by this bit: +Present State register : Command Inhibit (CMD) bit +Normal Interrupt Status register : Command Complete bit +Error Interrupt Status : Response error statuses related to Command Inhibit (CMD) bit +Values: +0x0 (FALSE): Work +0x1 (TRUE): Reset + 25 + 1 + read-write + + + SW_RST_ALL + Software Reset For All +This reset affects the entire Host Controller except for the card detection circuit. +During its initialization, the Host Driver sets this bit to 1 to reset the Host Controller. +All registers are reset except the capabilities register. +If this bit is set to 1, the Host Driver must issue reset command and reinitialize the card. +Values: +0x0 (FALSE): Work +0x1 (TRUE): Reset + 24 + 1 + read-write + + + TOUT_CNT + Data Timeout Counter Value. +This value determines the interval by which DAT line timeouts are detected. +The Timeout clock frequency is generated by dividing the base clock TMCLK value by this value. +When setting this register, prevent inadvertent timeout events by clearing the Data Timeout Error Status Enable (in the Error Interrupt Status Enable register). +The values for these bits are: +0xF : Reserved +0xE : TMCLK x 2^27 +......... +0x1 : TMCLK x 2^14 +0x0 : TMCLK x 2^13 +Note: During a boot operating in an eMMC mode, an application must configure the boot data timeout value (approximately 1 sec) in this bit. + 16 + 4 + read-write + + + FREQ_SEL + SDCLK/RCLK Frequency Select +These bits are used to select the frequency of the SDCLK signal. +These bits depend on setting of Preset Value Enable in the Host Control 2 register. +If Preset Value Enable = 0, these bits are set by the Host Driver. +If Preset Value Enable = 1, these bits are automatically set to a value specified in one of the Preset Value register. +The value is reflected on the lower 8-bit of the card_clk_freq_selsignal. +10-bit Divided Clock Mode: +0x3FF : 1/2046 Divided clock +.......... +N : 1/2N Divided Clock +.......... +0x002 : 1/4 Divided Clock +0x001 : 1/2 Divided Clock +0x000 : Base clock (10MHz - 255 MHz) +Programmable Clock Mode : Enables the Host System to select a fine grain SD clock frequency: +0x3FF : Base clock * M /1024 +.......... +N-1 : Base clock * M /N +.......... +0x002 : Base clock * M /3 +0x001 : Base clock * M /2 +0x000 : Base clock * M + 8 + 8 + read-write + + + UPPER_FREQ_SEL + These bits specify the upper 2 bits of 10-bit SDCLK/RCLK Frequency Select control. +The value is reflected on the upper 2 bits of the card_clk_freq_sel signal. + 6 + 2 + read-write + + + CLK_GEN_SELECT + Clock Generator Select +This bit is used to select the clock generator mode in SDCLK/RCLK Frequency Select. +If Preset Value Enable = 0, this bit is set by the Host Driver. +If Preset Value Enable = 1, this bit is automatically set to a value specified in one of the Preset Value registers. +The value is reflected on the card_clk_gen_sel signal. +Values: +0x0 (FALSE): Divided Clock Mode +0x1 (TRUE): Programmable Clock Mode + 5 + 1 + read-write + + + PLL_ENABLE + PLL Enable +This bit is used to activate the PLL (applicable when Host Version 4 Enable = 1). +When Host Version 4 Enable = 0, INTERNAL_CLK_EN bit may be used to activate PLL. The value is reflected on the card_clk_en signal. +Note: If this bit is not used to to active the PLL when Host Version 4 Enable = 1, it is recommended to set this bit to '1' . +Values: +0x0 (FALSE): PLL is in low power mode +0x1 (TRUE): PLL is enabled + 3 + 1 + read-write + + + SD_CLK_EN + SD/eMMC Clock Enable +This bit stops the SDCLK or RCLK when set to 0. +The SDCLK/RCLK Frequency Select bit can be changed when this bit is set to 0. +The value is reflected on the clk2card_on pin. +Values: +0x0 (FALSE): Disable providing SDCLK/RCLK +0x1 (TRUE): Enable providing SDCLK/RCLK + 2 + 1 + read-write + + + INTERNAL_CLK_STABLE + Internal Clock Stable +This bit enables the Host Driver to check the clock stability twice after the Internal Clock Enable bit is set and after the PLL Enable bit is set. +This bit reflects the synchronized value of the intclk_stable signal after the Internal Clock Enable bit is set to 1, +and also reflects the synchronized value of the card_clk_stable signal after the PLL Enable bit is set to 1. +Values: +0x0 (FALSE): Not Ready +0x1 (TRUE): Ready + 1 + 1 + read-write + + + INTERNAL_CLK_EN + Internal Clock Enable +This bit is set to 0 when the Host Driver is not using the Host Controller or the Host Controller awaits a wakeup interrupt. +The Host Controller must stop its internal clock to enter a very low power state. +However, registers can still be read and written to. The value is reflected on the intclk_en signal. +Note: If this bit is not used to control the internal clock (base clock and master clock), it is recommended to set this bit to '1' . +Values: +0x0 (FALSE): Stop +0x1 (TRUE): Oscillate + 0 + 1 + read-write + + + + + INT_STAT + No description available + 0x30 + 32 + 0x00000000 + 0x1FFFF1FF + + + BOOT_ACK_ERR + Boot Acknowledgment Error +This bit is set when there is a timeout for boot acknowledgement or when detecting boot ack status having a value other than 010. This is applicable only when boot acknowledgement is expected in eMMC mode. +In SD/UHS-II mode, this bit is irrelevant. + 28 + 1 + read-write + + + RESP_ERR + Response Error +Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. +If Response Error Check Enable is set to 1 in the Transfer Mode register, Host Controller Checks R1 or R5 response. If an error is detected in a response, this bit is set to 1.This is applicable in SD/eMMC mode. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 27 + 1 + read-write + + + TUNING_ERR + Tuning Error +This bit is set when an unrecoverable error is detected in a tuning circuit except during the tuning procedure +(occurrence of an error during tuning procedure is indicated by Sampling Clock Select in the Host Control 2 register). +By detecting Tuning Error, Host Driver needs to abort a command executing and perform tuning. +To reset tuning circuit, Sampling Clock Select is set to 0 before executing tuning procedure. +The Tuning Error is higher priority than the other error interrupts generated during data transfer. +By detecting Tuning Error, the Host Driver must discard data transferred by a current read/write command and retry data transfer after the Host Controller retrieved from the tuning circuit error. +This is applicable in SD/eMMC mode. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 26 + 1 + read-write + + + ADMA_ERR + ADMA Error +This bit is set when the Host Controller detects error during ADMA-based data transfer. The error could be due to following reasons: +Error response received from System bus (Master I/F) +ADMA3,ADMA2 Descriptors invalid +CQE Task or Transfer descriptors invalid +When the error occurs, the state of the ADMA is saved in the ADMA Error Status register. +In eMMC CQE mode: +The Host Controller generates this Interrupt when it detects an invalid descriptor data (Valid=0) at the ST_FDS state. +ADMA Error State in the ADMA Error Status indicates that an error has occurred in ST_FDS state. +The Host Driver may find that Valid bit is not set at the error descriptor. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 25 + 1 + read-write + + + AUTO_CMD_ERR + Auto CMD Error +This error status is used by Auto CMD12 and Auto CMD23 in SD/eMMC mode. +This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1. +D07 is effective in case of Auto CMD12. Auto CMD Error Status register is valid while this bit is set to 1 and may be cleared by clearing of this bit. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 24 + 1 + read-write + + + CUR_LMT_ERR + Current Limit Error +By setting the SD Bus Power bit in the Power Control register, the Host Controller is requested to supply power for the SD Bus. +If the Host Controller supports the Current Limit function, it can be protected from an illegal card by stopping power supply to the card in which case this bit indicates a failure status. +A reading of 1 for this bit means that the Host Controller is not supplying power to the SD card due to some failure. +A reading of 0 for this bit means that the Host Controller is supplying power and no error has occurred. +The Host Controller may require some sampling time to detect the current limit. +SDXC Host Controller does not support this function, this bit is always set to 0. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Power Fail + 23 + 1 + read-write + + + DATA_END_BIT_ERR + Data End Bit Error +This error occurs in SD/eMMC mode either when detecting 0 at the end bit position of read data that uses the DAT line or at the end bit position of the CRC status. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 22 + 1 + read-write + + + DATA_CRC_ERR + Data CRC Error +This error occurs in SD/eMMC mode when detecting CRC error when transferring read data which uses the DAT line, +when detecting the Write CRC status having a value of other than 010 or when write CRC status timeout. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 21 + 1 + read-write + + + DATA_TOUT_ERR + Data Timeout Error +This bit is set in SD/eMMC mode when detecting one of the following timeout conditions: +Busy timeout for R1b, R5b type +Busy timeout after Write CRC status +Write CRC Status timeout +Read Data timeout +Values: +0x0 (FALSE): No error +0x1 (TRUE): Time out + 20 + 1 + read-write + + + CMD_IDX_ERR + Command Index Error +This bit is set if a Command Index error occurs in the command respons in SD/eMMC mode. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 19 + 1 + read-write + + + CMD_END_BIT_ERR + Command End Bit Error +This bit is set when detecting that the end bit of a command response is 0 in SD/eMMC mode. +Values: +0x0 (FALSE): No error +0x1 (TRUE): End Bit error generated + 18 + 1 + read-write + + + CMD_CRC_ERR + Command CRC Error +Command CRC Error is generated in SD/eMMC mode for following two cases. +If a response is returned and the Command Timeout Error is set to 0 (indicating no timeout), this bit is set to 1 when detecting a CRC error in the command response. +The Host Controller detects a CMD line conflict by monitoring the CMD line when a command is issued. +If the Host Controller drives the CMD line to 1 level, +but detects 0 level on the CMD line at the next SD clock edge, then the Host Controller aborts the command (stop driving CMD line) and set this bit to 1. +The Command Timeout Error is also set to 1 to distinguish a CMD line conflict. +Values: +0x0 (FALSE): No error +0x1 (TRUE): CRC error generated + 17 + 1 + read-write + + + CMD_TOUT_ERR + Command Timeout Error +In SD/eMMC Mode,this bit is set only if no response is returned within 64 SD clock cycles from the end bit of the command. +If the Host Controller detects a CMD line conflict, along with Command CRC Error bit, this bit is set to 1, without waiting for 64 SD/eMMC card clock cycles. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Time out + 16 + 1 + read-write + + + ERR_INTERRUPT + Error Interrupt +If any of the bits in the Error Interrupt Status register are set, then this bit is set. +Values: +0x0 (FALSE): No Error +0x1 (TRUE): Error + 15 + 1 + read-only + + + CQE_EVENT + Command Queuing Event +This status is set if Command Queuing/Crypto related event has occurred in eMMC/SD mode. Read CQHCI's CQIS/CRNQIS register for more details. +Values: +0x0 (FALSE): No Event +0x1 (TRUE): Command Queuing Event is detected + 14 + 1 + read-write + + + FX_EVENT + FX Event +This status is set when R[14] of response register is set to 1 and Response Type R1/R5 is set to 0 in Transfer Mode register. This interrupt is used with response check function. +Values: +0x0 (FALSE): No Event +0x1 (TRUE): FX Event is detected + 13 + 1 + read-only + + + RE_TUNE_EVENT + Re-tuning Event +This bit is set if the Re-Tuning Request changes from 0 to 1. Re-Tuning request is not supported. + 12 + 1 + read-only + + + CARD_INTERRUPT + Card Interrupt +This bit reflects the synchronized value of: +DAT[1] Interrupt Input for SD Mode +DAT[2] Interrupt Input for UHS-II Mode +Values: +0x0 (FALSE): No Card Interrupt +0x1 (TRUE): Generate Card Interrupt + 8 + 1 + read-only + + + CARD_REMOVAL + Card Removal +This bit is set if the Card Inserted in the Present State register changes from 1 to 0. +Values: +0x0 (FALSE): Card state stable or Debouncing +0x1 (TRUE): Card Removed + 7 + 1 + read-write + + + CARD_INSERTION + Card Insertion +This bit is set if the Card Inserted in the Present State register changes from 0 to 1. +Values: +0x0 (FALSE): Card state stable or Debouncing +0x1 (TRUE): Card Inserted + 6 + 1 + read-write + + + BUF_RD_READY + Buffer Read Ready +This bit is set if the Buffer Read Enable changes from 0 to 1. +Values: +0x0 (FALSE): Not ready to read buffer +0x1 (TRUE): Ready to read buffer + 5 + 1 + read-write + + + BUF_WR_READY + Buffer Write Ready +This bit is set if the Buffer Write Enable changes from 0 to 1. +Values: +0x0 (FALSE): Not ready to write buffer +0x1 (TRUE): Ready to write buffer + 4 + 1 + read-write + + + DMA_INTERRUPT + DMA Interrupt +This bit is set if the Host Controller detects the SDMA Buffer Boundary during transfer. +In case of ADMA, by setting the Int field in the descriptor table, the Host controller generates this interrupt. +This interrupt is not generated after a Transfer Complete. +Values: +0x0 (FALSE): No DMA Interrupt +0x1 (TRUE): DMA Interrupt is generated + 3 + 1 + read-write + + + BGAP_EVENT + Block Gap Event +This bit is set when both read/write transaction is stopped at block gap due to a Stop at Block Gap Request. +Values: +0x0 (FALSE): No Block Gap Event +0x1 (TRUE): Transaction stopped at block gap + 2 + 1 + read-write + + + XFER_COMPLETE + Transfer Complete +This bit is set when a read/write transfer and a command with status busy is completed. +Values: +0x0 (FALSE): Not complete +0x1 (TRUE): Command execution is completed + 1 + 1 + read-write + + + CMD_COMPLETE + Command Complete +In an SD/eMMC Mode, this bit is set when the end bit of a response except for Auto CMD12 and Auto CMD23. +This interrupt is not generated when the Response Interrupt Disable in Transfer Mode Register is set to 1. +Values: +0x0 (FALSE): No command complete +0x1 (TRUE): Command Complete + 0 + 1 + read-write + + + + + INT_STAT_EN + No description available + 0x34 + 32 + 0x00000000 + 0x1FFF71FF + + + BOOT_ACK_ERR_STAT_EN + Boot Acknowledgment Error (eMMC Mode only) +Setting this bit to 1 enables setting of Boot Acknowledgment Error in Error Interrupt Status register (INT_STAT). +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 28 + 1 + read-write + + + RESP_ERR_STAT_EN + Response Error Status Enable (SD Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 27 + 1 + read-write + + + TUNING_ERR_STAT_EN + Tuning Error Status Enable (UHS-I Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 26 + 1 + read-write + + + ADMA_ERR_STAT_EN + ADMA Error Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 25 + 1 + read-write + + + AUTO_CMD_ERR_STAT_EN + Auto CMD Error Status Enable (SD/eMMC Mode only). +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 24 + 1 + read-write + + + CUR_LMT_ERR_STAT_EN + Current Limit Error Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 23 + 1 + read-write + + + DATA_END_BIT_ERR_STAT_EN + Data End Bit Error Status Enable (SD/eMMC Mode only). +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 22 + 1 + read-write + + + DATA_CRC_ERR_STAT_EN + Data CRC Error Status Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 21 + 1 + read-write + + + DATA_TOUT_ERR_STAT_EN + Data Timeout Error Status Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 20 + 1 + read-write + + + CMD_IDX_ERR_STAT_EN + Command Index Error Status Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 19 + 1 + read-write + + + CMD_END_BIT_ERR_STAT_EN + Command End Bit Error Status Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 18 + 1 + read-write + + + CMD_CRC_ERR_STAT_EN + Command CRC Error Status Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 17 + 1 + read-write + + + CMD_TOUT_ERR_STAT_EN + Command Timeout Error Status Enable (SD/eMMC Mode only). +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 16 + 1 + read-write + + + CQE_EVENT_STAT_EN + CQE Event Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 14 + 1 + read-write + + + FX_EVENT_STAT_EN + FX Event Status Enable +This bit is added from Version 4.10. +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 13 + 1 + read-write + + + RE_TUNE_EVENT_STAT_EN + Re-Tuning Event (UHS-I only) Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 12 + 1 + read-write + + + CARD_INTERRUPT_STAT_EN + Card Interrupt Status Enable +If this bit is set to 0, the Host Controller clears the interrupt request to the System. +The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. +The Host Driver may clear the Card Interrupt Status Enable before servicing the Card Interrupt and may set this bit again after all interrupt requests from the card are cleared to prevent inadvertent interrupts. +By setting this bit to 0, interrupt input must be masked by implementation so that the interrupt input is not affected by external signal in any state (for example, floating). +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 8 + 1 + read-write + + + CARD_REMOVAL_STAT_EN + Card Removal Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 7 + 1 + read-write + + + CARD_INSERTION_STAT_EN + Card Insertion Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 6 + 1 + read-write + + + BUF_RD_READY_STAT_EN + Buffer Read Ready Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 5 + 1 + read-write + + + BUF_WR_READY_STAT_EN + Buffer Write Ready Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 4 + 1 + read-write + + + DMA_INTERRUPT_STAT_EN + DMA Interrupt Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 3 + 1 + read-write + + + BGAP_EVENT_STAT_EN + Block Gap Event Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 2 + 1 + read-write + + + XFER_COMPLETE_STAT_EN + Transfer Complete Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 1 + 1 + read-write + + + CMD_COMPLETE_STAT_EN + Command Complete Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 0 + 1 + read-write + + + + + INT_SIGNAL_EN + No description available + 0x38 + 32 + 0x00000000 + 0x1FFF71FF + + + BOOT_ACK_ERR_SIGNAL_EN + Boot Acknowledgment Error (eMMC Mode only). +Setting this bit to 1 enables generating interrupt signal when Boot Acknowledgment Error in Error Interrupt Status register is set. +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 28 + 1 + read-write + + + RESP_ERR_SIGNAL_EN + Response Error Signal Enable (SD Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 27 + 1 + read-write + + + TUNING_ERR_SIGNAL_EN + Tuning Error Signal Enable (UHS-I Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 26 + 1 + read-write + + + ADMA_ERR_SIGNAL_EN + ADMA Error Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 25 + 1 + read-write + + + AUTO_CMD_ERR_SIGNAL_EN + Auto CMD Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 24 + 1 + read-write + + + CUR_LMT_ERR_SIGNAL_EN + Current Limit Error Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 23 + 1 + read-write + + + DATA_END_BIT_ERR_SIGNAL_EN + Data End Bit Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 22 + 1 + read-write + + + DATA_CRC_ERR_SIGNAL_EN + Data CRC Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 21 + 1 + read-write + + + DATA_TOUT_ERR_SIGNAL_EN + Data Timeout Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 20 + 1 + read-write + + + CMD_IDX_ERR_SIGNAL_EN + Command Index Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 19 + 1 + read-write + + + CMD_END_BIT_ERR_SIGNAL_EN + Command End Bit Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 18 + 1 + read-write + + + CMD_CRC_ERR_SIGNAL_EN + Command CRC Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 17 + 1 + read-write + + + CMD_TOUT_ERR_SIGNAL_EN + Command Timeout Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 16 + 1 + read-write + + + CQE_EVENT_SIGNAL_EN + Command Queuing Engine Event Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 14 + 1 + read-write + + + FX_EVENT_SIGNAL_EN + FX Event Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 13 + 1 + read-write + + + RE_TUNE_EVENT_SIGNAL_EN + Re-Tuning Event (UHS-I only) Signal Enable. +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 12 + 1 + read-write + + + CARD_INTERRUPT_SIGNAL_EN + Card Interrupt Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 8 + 1 + read-write + + + CARD_REMOVAL_SIGNAL_EN + Card Removal Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 7 + 1 + read-write + + + CARD_INSERTION_SIGNAL_EN + Card Insertion Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 6 + 1 + read-write + + + BUF_RD_READY_SIGNAL_EN + Buffer Read Ready Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 5 + 1 + read-write + + + BUF_WR_READY_SIGNAL_EN + Buffer Write Ready Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 4 + 1 + read-write + + + DMA_INTERRUPT_SIGNAL_EN + DMA Interrupt Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 3 + 1 + read-write + + + BGAP_EVENT_SIGNAL_EN + Block Gap Event Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 2 + 1 + read-write + + + XFER_COMPLETE_SIGNAL_EN + Transfer Complete Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 1 + 1 + read-write + + + CMD_COMPLETE_SIGNAL_EN + Command Complete Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 0 + 1 + read-write + + + + + AC_HOST_CTRL + No description available + 0x3c + 32 + 0x00000000 + 0xDCCF00BF + + + PRESET_VAL_ENABLE + Preset Value Enable +This bit enables automatic selection of SDCLK frequency and Driver strength Preset Value registers. +When Preset Value Enable is set, SDCLK frequency generation (Frequency Select and Clock Generator Select) and the driver strength selection are performed by the controller. +These values are selected from set of Preset Value registers based on selected speed mode. +Values: +0x0 (FALSE): SDCLK and Driver Strength are controlled by Host Driver +0x1 (TRUE): Automatic Selection by Preset Value are Enabled + 31 + 1 + read-write + + + ASYNC_INT_ENABLE + Asynchronous Interrupt Enable +This bit can be set if a card supports asynchronous interrupts and Asynchronous Interrupt Support is set to 1 in the Capabilities register. +Values: +0x0 (FALSE): Disabled +0x1 (TRUE): Enabled + 30 + 1 + read-write + + + HOST_VER4_ENABLE + Host Version 4 Enable +This bit selects either Version 3.00 compatible mode or Version 4 mode. +Functions of following fields are modified for Host Version 4 mode: +SDMA Address: SDMA uses ADMA System Address (05Fh-058h) instead of SDMA System Address register (003h-000h) +ADMA2/ADMA3 selection: ADMA3 is selected by DMA select in Host Control 1 register +64-bit ADMA Descriptor Size: 128-bit descriptor is used instead of 96-bit descriptor when 64-bit Addressing is set to 1 +Selection of 32-bit/64-bit System Addressing: Either 32-bit or 64-bit system addressing is selected by 64-bit Addressing bit in this register +32-bit Block Count: SDMA System Address register (003h-000h) is modified to 32-bit Block Count register +Note: It is recommended not to program ADMA3 Integrated Descriptor Address registers, +UHS-II registers and Command Queuing registers (if applicable) while operating in Host version less than 4 mode (Host Version 4 Enable = 0). +Values: +0x0 (FALSE): Version 3.00 compatible mode +0x1 (TRUE): Version 4 mode + 28 + 1 + read-write + + + CMD23_ENABLE + CMD23 Enable +If the card supports CMD23, this bit is set to 1. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3 data transfer. +Values: +0x0 (FALSE): Auto CMD23 is disabled +0x1 (TRUE): Auto CMD23 is enabled + 27 + 1 + read-write + + + ADMA2_LEN_MODE + ADMA2 Length Mode +This bit selects ADMA2 Length mode to be either 16-bit or 26-bit. +Values: +0x0 (FALSE): 16-bit Data Length Mode +0x1 (TRUE): 26-bit Data Length Mode + 26 + 1 + read-write + + + SAMPLE_CLK_SEL + Sampling Clock Select +This bit is used by the Host Controller to select the sampling clock in SD/eMMC mode to receive CMD and DAT. +This bit is set by the tuning procedure and is valid after the completion of tuning (when Execute Tuning is cleared). +Setting this bit to 1 means that tuning is completed successfully and setting this bit to 0 means that tuning has failed. +The value is reflected on the sample_cclk_sel pin. +Values: +0x0 (FALSE): Fixed clock is used to sample data +0x1 (TRUE): Tuned clock is used to sample data + 23 + 1 + read-write + + + EXEC_TUNING + Execute Tuning +This bit is set to 1 to start the tuning procedure in UHS-I/eMMC speed modes and this bit is automatically cleared when tuning procedure is completed. +Values: +0x0 (FALSE): Not Tuned or Tuning completed +0x1 (TRUE): Execute Tuning + 22 + 1 + read-write + + + SIGNALING_EN + 1.8V Signaling Enable +This bit controls voltage regulator for I/O cell in UHS-I/eMMC speed modes. +Setting this bit from 0 to 1 starts changing the signal voltage from 3.3V to 1.8V. +Host Controller clears this bit if switching to 1.8 signaling fails. The value is reflected on the uhs1_swvolt_en pin. +Note: This bit must be set for all UHS-I speed modes (SDR12/SDR25/SDR50/SDR104/DDR50). +Values: +0x0 (V_3_3): 3.3V Signalling +0x1 (V_1_8): 1.8V Signalling + 19 + 1 + read-write + + + UHS_MODE_SEL + UHS Mode/eMMC Speed Mode Select +These bits are used to select UHS mode in the SD mode of operation. In eMMC mode, these bits are used to select eMMC Speed mode. +UHS Mode (SD/UHS-II mode only): +0x0 (SDR12): SDR12/Legacy +0x1 (SDR25): SDR25/High Speed SDR +0x2 (SDR50): SDR50 +0x3 (SDR104): SDR104/HS200 +0x4 (DDR50): DDR50/High Speed DDR +0x5 (RSVD5): Reserved +0x6 (RSVD6): Reserved +0x7 (UHS2): UHS-II/HS400 +eMMC Speed Mode (eMMC mode only): +0x0: Legacy +0x1: High Speed SDR +0x2: Reserved +0x3: HS200 +0x4: High Speed DDR +0x5: Reserved +0x6: Reserved +0x7: HS400 + 16 + 3 + read-write + + + CMD_NOT_ISSUED_AUTO_CMD12 + Command Not Issued By Auto CMD12 Error +If this bit is set to 1, CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register. +This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. +Values: +0x1 (TRUE): Not Issued +0x0 (FALSE): No Error + 7 + 1 + read-only + + + AUTO_CMD_RESP_ERR + Auto CMD Response Error +This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or CMD13. +This status is ignored if any bit between D00 to D04 is set to 1. +Values: +0x1 (TRUE): Error +0x0 (FALSE): No Error + 5 + 1 + read-only + + + AUTO_CMD_IDX_ERR + Auto CMD Index Error +This bit is set if the command index error occurs in response to a command. +Values: +0x1 (TRUE): Error +0x0 (FALSE): No Error + 4 + 1 + read-only + + + AUTO_CMD_EBIT_ERR + Auto CMD End Bit Error +This bit is set when detecting that the end bit of command response is 0. +Values: +0x1 (TRUE): End Bit Error Generated +0x0 (FALSE): No Error + 3 + 1 + read-only + + + AUTO_CMD_CRC_ERR + Auto CMD CRC Error +This bit is set when detecting a CRC error in the command response. +Values: +0x1 (TRUE): CRC Error Generated +0x0 (FALSE): No Error + 2 + 1 + read-only + + + AUTO_CMD_TOUT_ERR + Auto CMD Timeout Error +This bit is set if no response is returned with 64 SDCLK cycles from the end bit of the command. +If this bit is set to 1, error status bits (D04-D01) are meaningless. +Values: +0x1 (TRUE): Time out +0x0 (FALSE): No Error + 1 + 1 + read-only + + + AUTO_CMD12_NOT_EXEC + Auto CMD12 Not Executed +If multiple memory block data transfer is not started due to a command error, this bit is not set because it is not necessary to issue an Auto CMD12. +Setting this bit to 1 means that the Host Controller cannot issue Auto CMD12 to stop multiple memory block data transfer, due to some error. + If this bit is set to 1, error status bits (D04-D01) is meaningless. +This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. +Values: +0x1 (TRUE): Not Executed +0x0 (FALSE): Executed + 0 + 1 + read-only + + + + + CAPABILITIES1 + No description available + 0x40 + 32 + 0x00000000 + 0xE7EFFFBF + + + SLOT_TYPE_R + Slot Type +These bits indicate usage of a slot by a specific Host System. +Values: +0x0 (REMOVABLE_SLOT): Removable Card Slot +0x1 (EMBEDDED_SLOT): Embedded Slot for one Device +0x2 (SHARED_SLOT): Shared Bus Slot (SD mode) +0x3 (UHS2_EMBEDDED_SLOT): UHS-II Multiple Embedded Devices + 30 + 2 + read-only + + + ASYNC_INT_SUPPORT + Asynchronous Interrupt Support (SD Mode only) +Values: +0x0 (FALSE): Asynchronous Interrupt Not Supported +0x1 (TRUE): Asynchronous Interrupt Supported + 29 + 1 + read-only + + + VOLT_18 + Voltage Support for 1.8V +Values: +0x0 (FALSE): 1.8V Not Supported +0x1 (TRUE): 1.8V Supported + 26 + 1 + read-only + + + VOLT_30 + Voltage Support for SD 3.0V or Embedded 1.2V +Values: +0x0 (FALSE): SD 3.0V or Embedded 1.2V Not Supported +0x1 (TRUE): SD 3.0V or Embedded Supported + 25 + 1 + read-only + + + VOLT_33 + Voltage Support for 3.3V +Values: +0x0 (FALSE): 3.3V Not Supported +0x1 (TRUE): 3.3V Supported + 24 + 1 + read-only + + + SUS_RES_SUPPORT + Suspense/Resume Support +This bit indicates whether the Host Controller supports Suspend/Resume functionality. +If this bit is 0, the Host Driver does not issue either Suspend or Resume commands because the Suspend and Resume mechanism is not supported. +Values: +0x0 (FALSE): Not Supported +0x1 (TRUE): Supported + 23 + 1 + read-only + + + SDMA_SUPPORT + SDMA Support +This bit indicates whether the Host Controller is capable of using SDMA to transfer data between the system memory and the Host Controller directly. +Values: +0x0 (FALSE): SDMA not Supported +0x1 (TRUE): SDMA Supported + 22 + 1 + read-only + + + HIGH_SPEED_SUPPORT + High Speed Support +This bit indicates whether the Host Controller and the Host System supports High Speed mode and they can supply the SD Clock frequency from 25 MHz to 50 MHz. +Values: +0x0 (FALSE): High Speed not Supported +0x1 (TRUE): High Speed Supported + 21 + 1 + read-only + + + ADMA2_SUPPORT + ADMA2 Support +This bit indicates whether the Host Controller is capable of using ADMA2. +Values: +0x0 (FALSE): ADMA2 not Supported +0x1 (TRUE): ADMA2 Supported + 19 + 1 + read-only + + + EMBEDDED_8_BIT + 8-bit Support for Embedded Device +This bit indicates whether the Host Controller is capable of using an 8-bit bus width mode. This bit is not effective when the Slot Type is set to 10b. +Values: +0x0 (FALSE): 8-bit Bus Width not Supported +0x1 (TRUE): 8-bit Bus Width Supported + 18 + 1 + read-only + + + MAX_BLK_LEN + Maximum Block Length +This bit indicates the maximum block size that the Host driver can read and write to the buffer in the Host Controller. +The buffer transfers this block size without wait cycles. The transfer block length is always 512 bytes for the SD Memory irrespective of this bit +Values: +0x0 (ZERO): 512 Byte +0x1 (ONE): 1024 Byte +0x2 (TWO): 2048 Byte +0x3 (THREE): Reserved + 16 + 2 + read-only + + + BASE_CLK_FREQ + Base Clock Frequency for SD clock +These bits indicate the base (maximum) clock frequency for the SD Clock. The definition of these bits depend on the Host Controller Version. +6-Bit Base Clock Frequency: This mode is supported by the Host Controller version 1.00 and 2.00. +The upper 2 bits are not effective and are always 0. The unit values are 1 MHz. The supported clock range is 10 MHz to 63 MHz. +-0x00 : Get information through another method +-0x01 : 1 MHz +-0x02 : 2 MHz +-............. +-0x3F : 63 MHz +-0x40-0xFF : Not Supported +8-Bit Base Clock Frequency: This mode is supported by the Host Controller version 3.00. The unit values are 1 MHz. The supported clock range is 10 MHz to 255 MHz. +-0x00 : Get information through another method +-0x01 : 1 MHz +-0x02 : 2 MHz +-............ +-0xFF : 255 MHz +If the frequency is 16.5 MHz, the larger value is set to 0001001b (17 MHz) because the Host Driver uses this value to calculate the clock divider value and it does not exceed the upper limit of the SD Clock frequency. +If these bits are all 0, the Host system has to get information using a different method. + 8 + 8 + read-only + + + TOUT_CLK_UNIT + Timeout Clock Unit +This bit shows the unit of base clock frequency used to detect Data TImeout Error. +Values: +0x0 (KHZ): KHz +0x1 (MHZ): MHz + 7 + 1 + read-only + + + TOUT_CLK_FREQ + Timeout Clock Frequency +This bit shows the base clock frequency used to detect Data Timeout Error. The Timeout Clock unit defines the unit of timeout clock frequency. It can be KHz or MHz. +0x00 : Get information through another method +0x01 : 1KHz / 1MHz +0x02 : 2KHz / 2MHz +0x03 : 3KHz / 3MHz + ........... +0x3F : 63KHz / 63MHz + 0 + 6 + read-only + + + + + CAPABILITIES2 + No description available + 0x44 + 32 + 0x00000000 + 0x18FFEF7F + + + VDD2_18V_SUPPORT + 1.8V VDD2 Support +This bit indicates support of VDD2 for the Host System. +0x0 (FALSE): 1.8V VDD2 is not Supported +0x1 (TRUE): 1.8V VDD2 is Supported + 28 + 1 + read-only + + + ADMA3_SUPPORT + ADMA3 Support +This bit indicates whether the Host Controller is capable of using ADMA3. +Values: +0x0 (FALSE): ADMA3 not Supported +0x1 (TRUE): ADMA3 Supported + 27 + 1 + read-only + + + CLK_MUL + Clock Multiplier +These bits indicate the clock multiplier of the programmable clock generator. Setting these bits to 0 means that the Host Controller does not support a programmable clock generator. +0x0: Clock Multiplier is not Supported +0x1: Clock Multiplier M = 2 +0x2: Clock Multiplier M = 3 + ......... +0xFF: Clock Multiplier M = 256 + 16 + 8 + read-only + + + RE_TUNING_MODES + Re-Tuning Modes (UHS-I only) +These bits select the re-tuning method and limit the maximum data length. +Values: +0x0 (MODE1): Timer +0x1 (MODE2): Timer and Re-Tuning Request (Not supported) +0x2 (MODE3): Auto Re-Tuning (for transfer) +0x3 (RSVD_MODE): Reserved + 14 + 2 + read-only + + + USE_TUNING_SDR50 + Use Tuning for SDR50 (UHS-I only) +Values: +0x0 (ZERO): SDR50 does not require tuning +0x1 (ONE): SDR50 requires tuning + 13 + 1 + read-only + + + RETUNE_CNT + Timer Count for Re-Tuning (UHS-I only) +0x0: Re-Tuning Timer disabled +0x1: 1 seconds +0x2: 2 seconds +0x3: 4 seconds + ........ +0xB: 1024 seconds +0xC: Reserved +0xD: Reserved +0xE: Reserved +0xF: Get information from other source + 8 + 4 + read-only + + + DRV_TYPED + Driver Type D Support (UHS-I only) +This bit indicates support of Driver Type D for 1.8 Signaling. +Values: +0x0 (FALSE): Driver Type D is not supported +0x1 (TRUE): Driver Type D is supported + 6 + 1 + read-only + + + DRV_TYPEC + Driver Type C Support (UHS-I only) +This bit indicates support of Driver Type C for 1.8 Signaling. +Values: +0x0 (FALSE): Driver Type C is not supported +0x1 (TRUE): Driver Type C is supported + 5 + 1 + read-only + + + DRV_TYPEA + Driver Type A Support (UHS-I only) +This bit indicates support of Driver Type A for 1.8 Signaling. +Values: +0x0 (FALSE): Driver Type A is not supported +0x1 (TRUE): Driver Type A is supported + 4 + 1 + read-only + + + UHS2_SUPPORT + UHS-II Support (UHS-II only) +This bit indicates whether Host Controller supports UHS-II. +Values: +0x0 (FALSE): UHS-II is not supported +0x1 (TRUE): UHS-II is supported + 3 + 1 + read-only + + + DDR50_SUPPORT + DDR50 Support (UHS-I only) +Values: +0x0 (FALSE): DDR50 is not supported +0x1 (TRUE): DDR50 is supported + 2 + 1 + read-only + + + SDR104_SUPPORT + SDR104 Support (UHS-I only) +This bit mentions that SDR104 requires tuning. +Values: +0x0 (FALSE): SDR104 is not supported +0x1 (TRUE): SDR104 is supported + 1 + 1 + read-only + + + SDR50_SUPPORT + SDR50 Support (UHS-I only) +This bit indicates that SDR50 is supported. The bit 13 (USE_TUNING_SDR50) indicates whether SDR50 requires tuning or not. +Values: +0x0 (FALSE): SDR50 is not supported +0x1 (TRUE): SDR50 is supported + 0 + 1 + read-only + + + + + CURR_CAPABILITIES1 + No description available + 0x48 + 32 + 0x00000000 + 0x00FFFFFF + + + MAX_CUR_18V + Maximum Current for 1.8V +This bit specifies the Maximum Current for 1.8V VDD1 power supply for the card. +0: Get information through another method +1: 4mA +2: 8mA +3: 13mA +....... +255: 1020mA + 16 + 8 + read-only + + + MAX_CUR_30V + Maximum Current for 3.0V +This bit specifies the Maximum Current for 3.0V VDD1 power supply for the card. +0: Get information through another method +1: 4mA +2: 8mA +3: 13mA +....... +255: 1020mA + 8 + 8 + read-only + + + MAX_CUR_33V + Maximum Current for 3.3V +This bit specifies the Maximum Current for 3.3V VDD1 power supply for the card. +0: Get information through another method +1: 4mA +2: 8mA +3: 13mA +....... +255: 1020mA + 0 + 8 + read-only + + + + + CURR_CAPABILITIES2 + No description available + 0x4c + 32 + 0x00000000 + 0x000000FF + + + MAX_CUR_VDD2_18V + Maximum Current for 1.8V VDD2 +This bit specifies the Maximum Current for 1.8V VDD2 power supply for the UHS-II card. +0: Get information through another method +1: 4mA +2: 8mA +3: 13mA +....... +255: 1020mA + 0 + 8 + read-only + + + + + FORCE_EVENT + No description available + 0x50 + 32 + 0x00000000 + 0x1FFF00BF + + + FORCE_BOOT_ACK_ERR + Force Event for Boot Ack error +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Boot ack Error Status is set + 28 + 1 + write-only + + + FORCE_RESP_ERR + Force Event for Response Error (SD Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Response Error Status is set + 27 + 1 + write-only + + + FORCE_TUNING_ERR + Force Event for Tuning Error (UHS-I Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Tuning Error Status is set + 26 + 1 + write-only + + + FORCE_ADMA_ERR + Force Event for ADMA Error +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): ADMA Error Status is set + 25 + 1 + write-only + + + FORCE_AUTO_CMD_ERR + Force Event for Auto CMD Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Auto CMD Error Status is set + 24 + 1 + write-only + + + FORCE_CUR_LMT_ERR + Force Event for Current Limit Error +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Current Limit Error Status is set + 23 + 1 + write-only + + + FORCE_DATA_END_BIT_ERR + Force Event for Data End Bit Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Data End Bit Error Status is set + 22 + 1 + write-only + + + FORCE_DATA_CRC_ERR + Force Event for Data CRC Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Data CRC Error Status is set + 21 + 1 + write-only + + + FORCE_DATA_TOUT_ERR + Force Event for Data Timeout Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Data Timeout Error Status is set + 20 + 1 + write-only + + + FORCE_CMD_IDX_ERR + Force Event for Command Index Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Command Index Error Status is set + 19 + 1 + write-only + + + FORCE_CMD_END_BIT_ERR + Force Event for Command End Bit Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Command End Bit Error Status is set + 18 + 1 + write-only + + + FORCE_CMD_CRC_ERR + Force Event for Command CRC Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Command CRC Error Status is set + 17 + 1 + write-only + + + FORCE_CMD_TOUT_ERR + Force Event for Command Timeout Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Command Timeout Error Status is set + 16 + 1 + write-only + + + FORCE_CMD_NOT_ISSUED_AUTO_CMD12 + Force Event for Command Not Issued By Auto CMD12 Error +Values: +0x1 (TRUE): Command Not Issued By Auto CMD12 Error Status is set +0x0 (FALSE): Not Affected + 7 + 1 + write-only + + + FORCE_AUTO_CMD_RESP_ERR + Force Event for Auto CMD Response Error +Values: +0x1 (TRUE): Auto CMD Response Error Status is set +0x0 (FALSE): Not Affected + 5 + 1 + write-only + + + FORCE_AUTO_CMD_IDX_ERR + Force Event for Auto CMD Index Error +Values: +0x1 (TRUE): Auto CMD Index Error Status is set +0x0 (FALSE): Not Affected + 4 + 1 + write-only + + + FORCE_AUTO_CMD_EBIT_ERR + Force Event for Auto CMD End Bit Error +Values: +0x1 (TRUE): Auto CMD End Bit Error Status is set +0x0 (FALSE): Not Affected + 3 + 1 + write-only + + + FORCE_AUTO_CMD_CRC_ERR + Force Event for Auto CMD CRC Error +Values: +0x1 (TRUE): Auto CMD CRC Error Status is set +0x0 (FALSE): Not Affected + 2 + 1 + write-only + + + FORCE_AUTO_CMD_TOUT_ERR + Force Event for Auto CMD Timeout Error +Values: +0x1 (TRUE): Auto CMD Timeout Error Status is set +0x0 (FALSE): Not Affected + 1 + 1 + write-only + + + FORCE_AUTO_CMD12_NOT_EXEC + Force Event for Auto CMD12 Not Executed +Values: +0x1 (TRUE): Auto CMD12 Not Executed Status is set +0x0 (FALSE): Not Affected + 0 + 1 + write-only + + + + + ADMA_ERR_STAT + No description available + 0x54 + 32 + 0x00000000 + 0x00000007 + + + ADMA_LEN_ERR + ADMA Length Mismatch Error States +This error occurs in the following instances: +While the Block Count Enable is being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length +When the total data length cannot be divided by the block length +Values: +0x0 (NO_ERR): No Error +0x1 (ERROR): Error + 2 + 1 + read-only + + + ADMA_ERR_STATES + ADMA Error States +These bits indicate the state of ADMA when an error occurs during ADMA data transfer. +Values: +0x0 (ST_STOP): Stop DMA - SYS_ADR register points to a location next to the error descriptor +0x1 (ST_FDS): Fetch Descriptor - SYS_ADR register points to the error descriptor +0x2 (UNUSED): Never set this state +0x3 (ST_TFR): Transfer Data - SYS_ADR register points to a location next to the error descriptor + 0 + 2 + read-only + + + + + ADMA_SYS_ADDR + No description available + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADMA_SA + ADMA System Address +These bits indicate the lower 32 bits of the ADMA system address. +SDMA: If Host Version 4 Enable is set to 1, this register stores the system address of the data location +ADMA2: This register stores the byte address of the executing command of the descriptor table +ADMA3: This register is set by ADMA3. ADMA2 increments the address of this register that points to the next line, every time a Descriptor line is fetched. + 0 + 32 + read-write + + + + + 9 + 0x2 + INIT,DS,HS,SDR12,SDR25,SDR50,SDR104,DDR50,rsv8,rsv9,UHS2 + PRESET[%s] + no description available + 0x60 + 16 + 0x0000 + 0x07FF + + + CLK_GEN_SEL_VAL + Clock Generator Select Value +This bit is effective when the Host Controller supports a programmable clock generator. +Values: +0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator +0x1 (PROG): Programmable Clock Generator + 10 + 1 + read-only + + + FREQ_SEL_VAL + SDCLK/RCLK Frequency Select Value +10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. + 0 + 10 + read-only + + + + + ADMA_ID_ADDR + No description available + 0x78 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADMA_ID_ADDR + ADMA Integrated Descriptor Address +These bits indicate the lower 32-bit of the ADMA Integrated Descriptor address. +The start address of Integrated Descriptor is set to these register bits. +The ADMA3 fetches one Descriptor Address and increments these bits to indicate the next Descriptor address. + 0 + 32 + read-write + + + + + P_EMBEDDED_CNTRL + No description available + 0xe6 + 16 + 0x0000 + 0x0FFF + + + REG_OFFSET_ADDR + Offset Address of Embedded Control register. + 0 + 12 + read-only + + + + + P_VENDOR_SPECIFIC_AREA + No description available + 0xe8 + 16 + 0x0000 + 0x0FFF + + + REG_OFFSET_ADDR + Base offset Address for Vendor-Specific registers. + 0 + 12 + read-only + + + + + P_VENDOR2_SPECIFIC_AREA + No description available + 0xea + 16 + 0x0000 + 0xFFFF + + + REG_OFFSET_ADDR + Base offset Address for Command Queuing registers. + 0 + 16 + read-only + + + + + SLOT_INTR_STATUS + No description available + 0xfc + 16 + 0x0000 + 0x00FF + + + INTR_SLOT + Interrupt signal for each Slot +These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot. +A maximum of 8 slots can be defined. If one interrupt signal is associated with multiple slots, the Host Driver can identify the interrupt that is generated by reading these bits. + By a power on reset or by setting Software Reset For All bit, the interrupt signals are de-asserted and this status reads 00h. +Bit 00: Slot 1 +Bit 01: Slot 2 +Bit 02: Slot 3 +.......... +.......... +Bit 07: Slot 8 +Note: MSHC Host Controller support single card slot. This register shall always return 0. + 0 + 8 + read-only + + + + + CQVER + No description available + 0x180 + 32 + 0x00000000 + 0x00000FFF + + + EMMC_VER_MAHOR + This bit indicates the eMMC major version (1st digit left of decimal point) in BCD format. + 8 + 4 + read-only + + + EMMC_VER_MINOR + This bit indicates the eMMC minor version (1st digit right of decimal point) in BCD format. + 4 + 4 + read-only + + + EMMC_VER_SUFFIX + This bit indicates the eMMC version suffix (2nd digit right of decimal point) in BCD format. + 0 + 4 + read-only + + + + + CQCAP + No description available + 0x184 + 32 + 0x00000000 + 0x1000F3FF + + + CRYPTO_SUPPORT + Crypto Support +This bit indicates whether the Host Controller supports cryptographic operations. +Values: +0x0 (FALSE): Crypto not Supported +0x1 (TRUE): Crypto Supported + 28 + 1 + read-only + + + ITCFMUL + Internal Timer Clock Frequency Multiplier (ITCFMUL) +This field indicates the frequency of the clock used for interrupt coalescing timer and for determining the SQS +polling period. See ITCFVAL definition for details. Values 0x5 to 0xF are reserved. +Values: +0x0 (CLK_1KHz): 1KHz clock +0x1 (CLK_10KHz): 10KHz clock +0x2 (CLK_100KHz): 100KHz clock +0x3 (CLK_1MHz): 1MHz clock +0x4 (CLK_10MHz): 10MHz clock + 12 + 4 + read-only + + + ITCFVAL + Internal Timer Clock Frequency Value (ITCFVAL) +This field scales the frequency of the timer clock provided by ITCFMUL. The Final clock frequency of actual timer clock is calculated as ITCFVAL* ITCFMUL. + 0 + 10 + read-only + + + + + CQCFG + No description available + 0x188 + 32 + 0x00000000 + 0x00001101 + + + DCMD_EN + This bit indicates to the hardware whether the Task +Descriptor in slot #31 of the TDL is a data transfer descriptor or a direct-command descriptor. CQE uses this bit when a task is issued in slot #31, to determine how to decode the Task Descriptor. +Values: +0x1 (SLOT31_DCMD_ENABLE): Task descriptor in slot #31 is a DCMD Task Descriptor +0x0 (SLOT31_DCMD_DISABLE): Task descriptor in slot #31 is a data Transfer Task Descriptor + 12 + 1 + read-write + + + TASK_DESC_SIZE + Bit Value Description +This bit indicates the size of task descriptor used in host memory. This bit can only be configured when Command Queuing Enable bit is 0 (command queuing is disabled). +Values: +0x1 (TASK_DESC_128b): Task descriptor size is 128 bits +0x0 (TASK_DESC_64b): Task descriptor size is 64 bit + 8 + 1 + read-write + + + CQ_EN + No description available + 0 + 1 + read-write + + + + + CQCTL + No description available + 0x18c + 32 + 0x00000000 + 0x00000101 + + + CLR_ALL_TASKS + Clear all tasks +This bit can only be written when the controller is halted. This bit does not clear tasks in the device. The software has to use the CMDQ_TASK_MGMT command to clear device's queue. +Values: +0x1 (CLEAR_ALL_TASKS): Clears all the tasks in the controller +0x0 (NO_EFFECT): Programming 0 has no effect + 8 + 1 + read-write + + + HALT + Halt request and resume +Values: +0x1 (HALT_CQE): Software writes 1 to this bit when it wants to acquire software control over the eMMC bus and to disable CQE from issuing command on the bus. +For example, issuing a Discard Task command (CMDQ_TASK_MGMT). +When the software writes 1, CQE completes the ongoing task (if any in progress). +After the task is completed and the CQE is in idle state, CQE does not issue new commands and indicates to the software by setting this bit to 1. +The software can poll on this bit until it is set to 1 and only then send commands on the eMMC bus. +0x0 (RESUME_CQE): Software writes 0 to this bit to exit from the halt state and resume CQE activity + 0 + 1 + read-write + + + + + CQIS + No description available + 0x190 + 32 + 0x00000000 + 0x0000000F + + + TCL + Task cleared interrupt +This status bit is asserted (if CQISE.TCL_STE=1) when a task clear operation is completed by CQE. +The completed task clear operation is either an individual task clear (by writing CQTCLR) or clearing of all tasks (by writing CQCTL). +A value of 1 clears this status bit. +Values: +0x1 (SET): TCL Interrupt is set +0x0 (NOTSET): TCL Interrupt is not set + 3 + 1 + read-write + + + RED + Response error detected interrupt +This status bit is asserted (if CQISE.RED_STE=1) when a response is received with an error bit set in the device status +field. Configure the CQRMEM register to identify device status bit fields that may trigger an interrupt and that are masked. +A value of 1 clears this status bit. +Values: +0x1 (SET): RED Interrupt is set +0x0 (NOTSET): RED Interrupt is not set + 2 + 1 + read-write + + + TCC + Task complete interrupt +This status bit is asserted (if CQISE.TCC_STE=1) when at least one of the following conditions are met: +A task is completed and the INT bit is set in its Task Descriptor +Interrupt caused by Interrupt Coalescing logic due to timeout +Interrupt Coalescing logic reached the configured threshold +A value of 1 clears this status bit + 1 + 1 + read-write + + + HAC + Halt complete interrupt +This status bit is asserted (only if CQISE.HAC_STE=1) when halt bit in the CQCTL register transitions from 0 to 1 indicating that the host controller has completed its current ongoing task and has entered halt state. +A value of 1 clears this status bit. +Values: +0x1 (SET): HAC Interrupt is set +0x0 (NOTSET): HAC Interrupt is not set + 0 + 1 + read-write + + + + + CQISE + No description available + 0x194 + 32 + 0x00000000 + 0x0000000F + + + TCL_STE + Task cleared interrupt status enable +Values: +0x1 (INT_STS_ENABLE): CQIS.TCL is set when its interrupt condition is active +0x0 (INT_STS_DISABLE): CQIS.TCL is disabled + 3 + 1 + read-write + + + RED_STE + Response error detected interrupt status enable +Values: +0x1 (INT_STS_ENABLE): CQIS.RED is set when its interrupt condition is active +0x0 (INT_STS_DISABLE): CQIS.RED is disabled + 2 + 1 + read-write + + + TCC_STE + Task complete interrupt status enable +Values: +0x1 (INT_STS_ENABLE): CQIS.TCC is set when its interrupt condition is active +0x0 (INT_STS_DISABLE): CQIS.TCC is disabled + 1 + 1 + read-write + + + HAC_STE + Halt complete interrupt status enable +Values: +0x1 (INT_STS_ENABLE): CQIS.HAC is set when its interrupt condition is active +0x0 (INT_STS_DISABLE): CQIS.HAC is disabled + 0 + 1 + read-write + + + + + CQISGE + No description available + 0x198 + 32 + 0x00000000 + 0x0000000F + + + TCL_SGE + Task cleared interrupt signal enable +Values: +0x1 (INT_SIG_ENABLE): CQIS.TCL interrupt signal generation is active +0x0 (INT_SIG_DISABLE): CQIS.TCL interrupt signal generation is disabled + 3 + 1 + read-write + + + RED_SGE + Response error detected interrupt signal enable +Values: +0x1 (INT_SIG_ENABLE): CQIS.RED interrupt signal generation is active +0x0 (INT_SIG_DISABLE): CQIS.RED interrupt signal generation is disabled + 2 + 1 + read-write + + + TCC_SGE + Task complete interrupt signal enable +Values: +0x1 (INT_SIG_ENABLE): CQIS.TCC interrupt signal generation is active +0x0 (INT_SIG_DISABLE): CQIS.TCC interrupt signal generation is disabled + 1 + 1 + read-write + + + HAC_SGE + Halt complete interrupt signal enable +Values: +0x1 (INT_SIG_ENABLE): CQIS.HAC interrupt signal generation is active +0x0 (INT_SIG_DISABLE): CQIS.HAC interrupt signal generation is disabled + 0 + 1 + read-write + + + + + CQIC + No description available + 0x19c + 32 + 0x00000000 + 0x80119FFF + + + INTC_EN + Interrupt Coalescing Enable Bit +Values: +0x1 (ENABLE_INT_COALESCING): Interrupt coalescing mechanism is active. Interrupts are counted and timed, and coalesced interrupts are generated +0x0 (DISABLE_INT_COALESCING): Interrupt coalescing mechanism is disabled (Default) + 31 + 1 + read-write + + + INTC_STAT + Interrupt Coalescing Status Bit +This bit indicates to the software whether any tasks (with INT=0) have completed and counted towards interrupt +coalescing (that is, this is set if and only if INTC counter > 0). +Values: +0x1 (INTC_ATLEAST1_COMP): At least one INT0 task completion has been counted (INTC counter > 0) +0x0 (INTC_NO_TASK_COMP): INT0 Task completions have not occurred since last counter reset (INTC counter == 0) + 20 + 1 + read-only + + + INTC_RST + Counter and Timer Reset +When host driver writes 1, the interrupt coalescing timer and counter are reset. +Values: +0x1 (ASSERT_INTC_RESET): Interrupt coalescing timer and counter are reset +0x0 (NO_EFFECT): No Effect + 16 + 1 + write-only + + + INTC_TH_WEN + Interrupt Coalescing Counter Threshold Write Enable +When software writes 1 to this bit, the value INTC_TH is updated with the contents written on the same cycle. +Values: +0x1 (WEN_SET): Sets INTC_TH_WEN +0x0 (WEN_CLR): Clears INTC_TH_WEN + 15 + 1 + write-only + + + INTC_TH + Interrupt Coalescing Counter Threshold filed +Software uses this field to configure the number of task completions (only tasks with INT=0 in the Task Descriptor), which are required in order to generate an interrupt. +Counter Operation: As data transfer tasks with INT=0 complete, they are counted by CQE. +The counter is reset by software during the interrupt service routine. +The counter stops counting when it reaches the value configured in INTC_TH, and generates interrupt. +0x0: Interrupt coalescing feature disabled +0x1: Interrupt coalescing interrupt generated after 1 task when INT=0 completes +0x2: Interrupt coalescing interrupt generated after 2 tasks when INT=0 completes +........ +0x1f: Interrupt coalescing interrupt generated after 31 tasks when INT=0 completes +To write to this field, the INTC_TH_WEN bit must be set during the same write operation. + 8 + 5 + write-only + + + TOUT_VAL_WEN + When software writes 1 to this bit, the value TOUT_VAL is updated with the contents written on the same cycle. +Values: +0x1 (WEN_SET): Sets TOUT_VAL_WEN +0x0 (WEN_CLR): clears TOUT_VAL_WEN + 7 + 1 + write-only + + + TOUT_VAL + Interrupt Coalescing Timeout Value +Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt. +Timer Operation: The timer is reset by software during the interrupt service routine. +It starts running when the first data transfer task with INT=0 is completed, after the timer was reset. +When the timer reaches the value configured in ICTOVAL field, it generates an interrupt and stops. +The timer's unit is equal to 1024 clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. +0x0: Timer is disabled. Timeout-based interrupt is not generated +0x1: Timeout on 01x1024 cycles of timer clock frequency +0x2: Timeout on 02x1024 cycles of timer clock frequency +........ +0x7f: Timeout on 127x1024 cycles of timer clock frequency +In order to write to this field, the TOUT_VAL_WEN bit must +be set at the same write operation. + 0 + 7 + read-write + + + + + CQTDLBA + No description available + 0x1a0 + 32 + 0x00000000 + 0xFFFFFFFF + + + TDLBA + This register stores the LSB bits (31:0) of the byte address of the head of the Task Descriptor List in system memory. +The size of the task descriptor list is 32 * (Task Descriptor size + Transfer Descriptor size) as configured by the host driver. +This address is set on 1 KB boundary. The lower 10 bits of this register are set to 0 by the software and are ignored by CQE + 0 + 32 + read-write + + + + + CQTDBR + No description available + 0x1a8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DBR + The software configures TDLBA and TDLBAU, and enable +CQE in CQCFG before using this register. +Writing 1 to bit n of this register triggers CQE to start processing the task encoded in slot n of the TDL. +Writing 0 by the software does not have any impact on the hardware, and does not change the value of the register bit. +CQE always processes tasks according to the order submitted to the list by CQTDBR write transactions. +CQE processes Data Transfer tasks by reading the Task Descriptor and sending QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) commands to +the device. CQE processes DCMD tasks (in slot #31, when enabled) by reading the Task Descriptor, and generating the command encoded by its index and argument. +The corresponding bit is cleared to 0 by CQE in one of the following events: +A task execution is completed (with success or error). +The task is cleared using CQTCLR register. +All tasks are cleared using CQCTL register. +CQE is disabled using CQCFG register. +Software may initiate multiple tasks at the same time (batch submission) by writing 1 to multiple bits of this register in the same transaction. +In the case of batch submission, CQE processes the tasks in order of the task index, starting with the lowest index. +If one or more tasks in the batch are marked with QBR, the ordering of execution is based on said processing order. + 0 + 32 + read-write + + + + + CQTCN + No description available + 0x1ac + 32 + 0x00000000 + 0xFFFFFFFF + + + TCN + Task Completion Notification +Each of the 32 bits are bit mapped to the 32 tasks. +Bit-N(1): Task-N has completed execution (with success or errors) +Bit-N(0): Task-N has not completed, could be pending or not submitted. +On task completion, software may read this register to know tasks that have completed. After reading this register, +software may clear the relevant bit fields by writing 1 to the corresponding bits. + 0 + 32 + read-write + + + + + CQDQS + No description available + 0x1b0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DQS + Device Queue Status +Each of the 32 bits are bit mapped to the 32 tasks. +Bit-N(1): Device has marked task N as ready for execution +Bit-N(0): Task-N is not ready for execution. This task could be pending in device or not submitted. +Host controller updates this register with response of the Device Queue Status command. + 0 + 32 + read-write + + + + + CQDPT + No description available + 0x1b4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DPT + Device-Pending Tasks +Each of the 32 bits are bit mapped to the 32 tasks. +Bit-N(1): Task-N has been successfully queued into the device and is awaiting execution +Bit-N(0): Task-N is not yet queued. +Bit n of this register is set if and only if QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) were sent for this specific task and if this task has not been executed. +The controller sets this bit after receiving a successful response for CMD45. CQE clears this bit after the task has completed execution. +Software reads this register in the task-discard procedure to determine if the task is queued in the device + 0 + 32 + read-write + + + + + CQTCLR + No description available + 0x1b8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TCLR + Writing 1 to bit n of this register orders CQE to clear a task that the software has previously issued. +This bit can only be written when CQE is in Halt state as indicated in CQCFG register Halt bit. +When software writes 1 to a bit in this register, CQE updates the value to 1, and starts clearing the data structures related to the task. +CQE clears the bit fields (sets a value of 0) in CQTCLR and in CQTDBR once the clear operation is complete. +Software must poll on the CQTCLR until it is leared to verify that a clear operation was done. + 0 + 32 + read-write + + + + + CQSSC1 + No description available + 0x1c0 + 32 + 0x00000000 + 0x000FFFFF + + + SQSCMD_BLK_CNT + This field indicates when SQS CMD is sent while data transfer is in progress. +A value of 'n' indicates that CQE sends status command on the CMD line, during the transfer of data block BLOCK_CNTn, on the data lines, where BLOCK_CNT is the number of blocks in the current transaction. +0x0: SEND_QUEUE_STATUS (CMD13) command is not sent during the transaction. Instead, it is sent only when the data lines are idle. +0x1: SEND_QUEUE_STATUS command is to be sent during the last block of the transaction. +0x2: SEND_QUEUE_STATUS command when last 2 blocks are pending. +0x3: SEND_QUEUE_STATUS command when last 3 blocks are pending. +........ +0xf: SEND_QUEUE_STATUS command when last 15 blocks are pending. +Should be programmed only when CQCFG.CQ_EN is 0 + 16 + 4 + read-write + + + SQSCMD_IDLE_TMR + This field configures the polling period to be used when using periodic SEND_QUEUE_STATUS (CMD13) polling. +Periodic polling is used when tasks are pending in the device, but no data transfer is in progress. +When a SEND_QUEUE_STATUS response indicates that no task is ready for execution, CQE counts the configured time until it issues the next SEND_QUEUE_STATUS. +Timer units are clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. +The minimum value is 0001h (1 clock period) and the maximum value is FFFFh (65535 clock periods). +For example, a CQCAP field value of 0 indicates a 19.2 MHz clock frequency (period = 52.08 ns). +If the setting in CQSSC1.CIT is 1000h, the calculated polling period is 4096*52.08 ns= 213.33 us. +Should be programmed only when CQCFG.CQ_EN is '0' + 0 + 16 + read-write + + + + + CQSSC2 + No description available + 0x1c4 + 32 + 0x00000000 + 0x0000FFFF + + + SQSCMD_RCA + This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_STATUS (CMD13) command argument. +CQE copies this field to bits 31:16 of the argument when transmitting SEND_ QUEUE_STATUS (CMD13) command. + 0 + 16 + read-write + + + + + CQCRDCT + No description available + 0x1c8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DCMD_RESP + This register contains the response of the command generated by the last direct command (DCMD) task that was sent. +Contents of this register are valid only after bit 31 of CQTDBR register is cleared by the controller. + 0 + 32 + read-only + + + + + CQRMEM + No description available + 0x1d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESP_ERR_MASK + The bits of this field are bit mapped to the device response. +This bit is used as an interrupt mask on the device status filed that is received in R1/R1b responses. +1: When a R1/R1b response is received, with a bit i in the device status set, a RED interrupt is generated. +0: When a R1/R1b response is received, bit i in the device status is ignored. +The reset value of this register is set to trigger an interrupt on all "Error" type bits in the device status. +Note: Responses to CMD13 (SQS) encode the QSR so that they are ignored by this logic. + 0 + 32 + read-write + + + + + CQTERRI + No description available + 0x1d4 + 32 + 0x00000000 + 0x1F3F9F3F + + + TRANS_ERR_TASKID + This field captures the ID of the task that was executed and whose data transfer has errors. + 24 + 5 + read-only + + + TRANS_ERR_CMD_INDX + This field captures the index of the command that was executed and whose data transfer has errors. + 16 + 6 + read-only + + + RESP_ERR_FIELDS_VALID + This bit is updated when an error is detected while a command transaction was in progress. +Values: +0x1 (SET): Response-related error is detected. Check contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX fields +0x0 (NOT_SET): Ignore contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX + 15 + 1 + read-only + + + RESP_ERR_TASKID + This field captures the ID of the task which was executed on the command line when the error occurred. + 8 + 5 + read-only + + + RESP_ERR_CMD_INDX + This field captures the index of the command that was executed on the command line when the error occurred + 0 + 6 + read-only + + + + + CQCRI + No description available + 0x1d8 + 32 + 0x00000000 + 0x0000003F + + + CMD_RESP_INDX + Last Command Response index +This field stores the index of the last received command response. Controller updates the value every time a command response is received + 0 + 6 + read-only + + + + + CQCRA + No description available + 0x1dc + 32 + 0x00000000 + 0xFFFFFFFF + + + CMD_RESP_ARG + Last Command Response argument +This field stores the argument of the last received command response. Controller updates the value every time a command response is received. + 0 + 32 + read-only + + + + + MSHC_VER_ID + No description available + 0x500 + 32 + 0x00000000 + 0xFFFFFFFF + + + VER_ID + No description available + 0 + 32 + read-only + + + + + MSHC_VER_TYPE + No description available + 0x504 + 32 + 0x00000000 + 0xFFFFFFFF + + + VER_TYPE + No description available + 0 + 32 + read-only + + + + + EMMC_BOOT_CTRL + No description available + 0x52c + 32 + 0x00000000 + 0xF181070F + + + BOOT_TOUT_CNT + Boot Ack Timeout Counter Value. +This value determines the interval by which boot ack timeout (50 ms) is detected when boot ack is expected during boot operation. +0xF : Reserved +0xE : TMCLK x 2^27 + ............ +0x1 : TMCLK x 2^14 +0x0 : TMCLK x 2^13 + 28 + 4 + read-write + + + BOOT_ACK_ENABLE + Boot Acknowledge Enable +When this bit set, SDXC checks for boot acknowledge start pattern of 0-1-0 during boot operation. This bit is applicable for both mandatory and alternate boot mode. +Values: +0x1 (TRUE): Boot Ack enable +0x0 (FALSE): Boot Ack disable + 24 + 1 + read-write + + + VALIDATE_BOOT + Validate Mandatory Boot Enable bit +This bit is used to validate the MAN_BOOT_EN bit. +Values: +0x1 (TRUE): Validate Mandatory boot enable bit +0x0 (FALSE): Ignore Mandatory boot Enable bit + 23 + 1 + write-only + + + MAN_BOOT_EN + Mandatory Boot Enable +This bit is used to initiate the mandatory boot operation. The application sets this bit along with VALIDATE_BOOT bit. +Writing 0 is ignored. The SDXC clears this bit after the boot transfer is completed or terminated. +Values: +0x1 (MAN_BOOT_EN): Mandatory boot enable +0x0 (MAN_BOOT_DIS): Mandatory boot disable + 16 + 1 + read-write + + + CQE_PREFETCH_DISABLE + Enable or Disable CQE's PREFETCH feature +This field allows Software to disable CQE's data prefetch feature when set to 1. +Values: +0x0 (PREFETCH_ENABLE): CQE can Prefetch data for sucessive WRITE transfers and pipeline sucessive READ transfers +0x1 (PREFETCH_DISABLE): Prefetch for WRITE and Pipeline for READ are disabled + 10 + 1 + read-write + + + CQE_ALGO_SEL + Scheduler algorithm selected for execution +This bit selects the Algorithm used for selecting one of the many ready tasks for execution. +Values: +0x0 (PRI_REORDER_PLUS_FCFS): Priority based reordering with FCFS to resolve equal priority tasks +0x1 (FCFS_ONLY): First come First serve, in the order of DBR rings + 9 + 1 + read-write + + + ENH_STROBE_ENABLE + Enhanced Strobe Enable +This bit instructs SDXC to sample the CMD line using data strobe for HS400 mode. +Values: +0x1 (ENH_STB_FOR_CMD): CMD line is sampled using data strobe for HS400 mode +0x0 (NO_STB_FOR_CMD): CMD line is sampled using cclk_rx for HS400 mode + 8 + 1 + read-write + + + EMMC_RST_N_OE + Output Enable control for EMMC Device Reset signal PAD +control. +This field drived sd_rst_n_oe output of SDXC +Values: +0x1 (ENABLE): sd_rst_n_oe is 1 +0x0 (DISABLE): sd_rst_n_oe is 0 + 3 + 1 + read-write + + + EMMC_RST_N + EMMC Device Reset signal control. +This register field controls the sd_rst_n output of SDXC +Values: +0x1 (RST_DEASSERT): Reset to eMMC device is deasserted +0x0 (RST_ASSERT): Reset to eMMC device asserted (active low) + 2 + 1 + read-write + + + DISABLE_DATA_CRC_CHK + Disable Data CRC Check +This bit controls masking of CRC16 error for Card Write in eMMC mode. +This is useful in bus testing (CMD19) for an eMMC device. In bus testing, an eMMC card does not send CRC status for a block, +which may generate CRC error. This CRC error can be masked using this bit during bus testing. +Values: +0x1 (DISABLE): DATA CRC check is disabled +0x0 (ENABLE): DATA CRC check is enabled + 1 + 1 + read-write + + + CARD_IS_EMMC + eMMC Card present +This bit indicates the type of card connected. An application program this bit based on the card connected to SDXC. +Values: +0x1 (EMMC_CARD): Card connected to SDXC is an eMMC card +0x0 (NON_EMMC_CARD): Card connected to SDXCis a non-eMMC card + 0 + 1 + read-write + + + + + AUTO_TUNING_CTRL + No description available + 0x540 + 32 + 0x00000000 + 0x7F1F0F1F + + + SWIN_TH_VAL + Sampling window threshold value setting +The maximum value that can be set here depends on the length of delayline used for tuning. A delayLine with 32 taps +can use values from 0x0 to 0x1F. +This field is valid only when SWIN_TH_EN is '1'. Should be programmed only when SAMPLE_CLK_SEL is '0' +0x0 : Threshold values is 0x1, windows of length 1 tap and above can be selected as sampling window. +0x1 : Threshold values is 0x2, windows of length 2 taps and above can be selected as sampling window. +0x2 : Threshold values is 0x1, windows of length 3 taps and above can be selected as sampling window. +........ +0x1F : Threshold values is 0x1, windows of length 32 taps and above can be selected as sampling window. + 24 + 7 + read-write + + + POST_CHANGE_DLY + Time taken for phase switching and stable clock output. +Specifies the maximum time (in terms of cclk cycles) that the delay line can take to switch its output phase after a change in tuning_cclk_sel or autotuning_cclk_sel. +Values: +0x0 (LATENCY_LT_1): Less than 1-cycle latency +0x1 (LATENCY_LT_2): Less than 2-cycle latency +0x2 (LATENCY_LT_3): Less than 3-cycle latency +0x3 (LATENCY_LT_4): Less than 4-cycle latency + 19 + 2 + read-write + + + PRE_CHANGE_DLY + Maximum Latency specification between cclk_tx and cclk_rx. +Values: +0x0 (LATENCY_LT_1): Less than 1-cycle latency +0x1 (LATENCY_LT_2): Less than 2-cycle latency +0x2 (LATENCY_LT_3): Less than 3-cycle latency +0x3 (LATENCY_LT_4): Less than 4-cycle latency + 17 + 2 + read-write + + + TUNE_CLK_STOP_EN + Clock stopping control for Tuning and auto-tuning circuit. +When enabled, clock gate control output of SDXC (clk2card_on) is pulled low before changing phase select codes on tuning_cclk_sel and autotuning_cclk_sel. +This effectively stops the Device/Card clock, cclk_rx and also drift_cclk_rx. Changing phase code when clocks are stopped ensures glitch free phase switching. + Set this bit to 0 if the PHY or delayline can guarantee glitch free switching. +Values: +0x1 (ENABLE_CLK_STOPPING): Clocks stopped during phase code change +0x0 (DISABLE_CLK_STOPPING): Clocks not stopped. PHY ensures glitch free phase switching + 16 + 1 + read-write + + + WIN_EDGE_SEL + This field sets the phase for Left and Right edges for drift monitoring. [Left edge offset + Right edge offset] must not be less than total taps of delayLine. +0x0: User selection disabled. Tuning calculated edges are used. +0x1: Right edge Phase is center + 2 stages, Left edge Phase is center - 2 stages. +0x2: Right edge Phase is center + 3 stages, Left edge Phase is center - 3 stagess +... +0xF: Right edge Phase is center + 16 stages, Left edge Phase is center - 16 stages. + 8 + 4 + read-write + + + SW_TUNE_EN + This fields enables software-managed tuning flow. +Values: +0x1 (SW_TUNING_ENABLE): Software-managed tuning enabled. AUTO_TUNING_STAT.CENTER_PH_CODE Field is now writable. +0x0 (SW_TUNING_DISABLE): Software-managed tuning disabled + 4 + 1 + read-write + + + RPT_TUNE_ERR + Framing errors are not generated when executing tuning. +This debug bit allows users to report these errors. +Values: +0x1 (DEBUG_ERRORS): Debug mode for reporting framing errors +0x0 (ERRORS_DISABLED): Default mode where as per SDXC no errors are reported. + 3 + 1 + read-write + + + SWIN_TH_EN + Sampling window Threshold enable +Selects the tuning mode +Field should be programmed only when SAMPLE_CLK_SEL is '0' +Values: +0x1 (THRESHOLD_MODE): Tuning engine selects the first complete sampling window that meets the threshold +set by SWIN_TH_VAL field +0x0 (LARGEST_WIN_MODE): Tuning engine sweeps all taps and settles at the largest window + 2 + 1 + read-write + + + CI_SEL + Selects the interval when the corrected center phase select code can be driven on tuning_cclk_sel output. +Values: +0x0 (WHEN_IN_BLK_GAP): Driven in block gap interval +0x1 (WHEN_IN_IDLE): Driven at the end of the transfer + 1 + 1 + read-write + + + AT_EN + Setting this bit enables Auto tuning engine. This bit is enabled by default when core is configured with mode3 retuning support. +Clear this bit to 0 when core is configured to have Mode3 re-tuning but SW wishes to disable mode3 retuning. +This field should be programmed only when SYS_CTRL.SD_CLK_EN is 0. +Values: +0x1 (AT_ENABLE): AutoTuning is enabled +0x0 (AT_DISABLE): AutoTuning is disabled + 0 + 1 + read-write + + + + + AUTO_TUNING_STAT + No description available + 0x544 + 32 + 0x00000000 + 0x00FFFFFF + + + L_EDGE_PH_CODE + Left Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Left edge of sampling window. + 16 + 8 + read-only + + + R_EDGE_PH_CODE + Right Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Right edge of sampling window. + 8 + 8 + read-only + + + CENTER_PH_CODE + Centered Phase code. Reading this field returns the current value on tuning_cclk_sel output. Setting AUTO_TUNING_CTRL.SW_TUNE_EN enables software to write to this field and its contents are reflected on tuning_cclk_sel + 0 + 8 + read-write + + + + + + + SDXC1 + SDXC1 + SDXC + 0xf2034000 + + + CONCTL + CONCTL + CONCTL + 0xf2040000 + + 0x0 + 0x18 + registers + + + + ctrl0 + No description available + 0x0 + 32 + 0x00000000 + 0xFF0FFFFF + + + ENET1_RXCLK_DLY_SEL + No description available + 15 + 5 + read-write + + + ENET1_TXCLK_DLY_SEL + No description available + 10 + 5 + read-write + + + ENET0_RXCLK_DLY_SEL + No description available + 5 + 5 + read-write + + + ENET0_TXCLK_DLY_SEL + No description available + 0 + 5 + read-write + + + + + ctrl2 + No description available + 0x8 + 32 + 0x00000000 + 0x2008F400 + + + ENET0_LPI_IRQ_EN + ENET0 LPI IRQ Enable + 29 + 1 + read-write + + + ENET0_REFCLK_OE + No description available + 19 + 1 + read-write + + + ENET0_PHY_INTF_SEL + 000:Reserved +001:RGMII +100:RMII +111:Reserved + 13 + 3 + read-write + + + ENET0_FLOWCTRL + No description available + 12 + 1 + read-write + + + ENET0_RMII_TXCLK_SEL + default to use internal clk. +set from pad， two option here: + internal 50MHz clock out to pad then in; + use external clock; + 10 + 1 + read-write + + + + + ctrl3 + No description available + 0xc + 32 + 0x00000000 + 0x2008F400 + + + ENET1_LPI_IRQ_EN + ENET1 LPI Interrupt Enable + 29 + 1 + read-write + + + ENET1_REFCLK_OE + No description available + 19 + 1 + read-write + + + ENET1_PHY_INTF_SEL + No description available + 13 + 3 + read-write + + + ENET1_FLOWCTRL + No description available + 12 + 1 + read-write + + + ENET1_RMII_TXCLK_SEL + No description available + 10 + 1 + read-write + + + + + ctrl4 + No description available + 0x10 + 32 + 0x00000000 + 0xDFFFF800 + + + SDXC0_SYS_IRQ_EN + system irq enable + 31 + 1 + read-write + + + SDXC0_WKP_IRQ_EN + wakeup irq enable + 30 + 1 + read-write + + + SDXC0_CARDCLK_INV_EN + card clock inverter enable + 28 + 1 + read-write + + + SDXC0_GPR_TUNING_CARD_CLK_SEL + for card clock DLL, default 0 + 23 + 5 + read-write + + + SDXC0_GPR_TUNING_STROBE_SEL + for strobe DLL, default 7taps(1ns) + 18 + 5 + read-write + + + SDXC0_GPR_STROBE_IN_ENABLE + enable strobe clock, maybe used when update strobe DLL + 17 + 1 + read-write + + + SDXC0_GPR_CCLK_RX_DLY_SW_SEL + No description available + 12 + 5 + read-write + + + SDXC0_GPR_CCLK_RX_DLY_SW_FORCE + force use sw DLL config + 11 + 1 + read-write + + + + + ctrl5 + No description available + 0x14 + 32 + 0x00000000 + 0xDFFFF800 + + + SDXC1_SYS_IRQ_EN + system irq enable + 31 + 1 + read-write + + + SDXC1_WKP_IRQ_EN + wakeup irq enable + 30 + 1 + read-write + + + SDXC1_CARDCLK_INV_EN + card clock inverter enable + 28 + 1 + read-write + + + SDXC1_GPR_TUNING_CARD_CLK_SEL + No description available + 23 + 5 + read-write + + + SDXC1_GPR_TUNING_STROBE_SEL + No description available + 18 + 5 + read-write + + + SDXC1_GPR_STROBE_IN_ENABLE + No description available + 17 + 1 + read-write + + + SDXC1_GPR_CCLK_RX_DLY_SW_SEL + No description available + 12 + 5 + read-write + + + SDXC1_GPR_CCLK_RX_DLY_SW_FORCE + No description available + 11 + 1 + read-write + + + + + + + I2C0 + I2C0 + I2C + 0xf3020000 + + 0x4 + 0x30 + registers + + + + Cfg + Configuration Register + 0x10 + 32 + 0x00000001 + 0xFFFFFFFF + + + FIFOSIZE + FIFO Size: +0: 2 bytes +1: 4 bytes +2: 8 bytes +3: 16 bytes + 0 + 2 + read-only + + + + + IntEn + Interrupt Enable Register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMPL + Set to enable the Completion Interrupt. +Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. +Slave: interrupts when a transaction addressing the controller is completed. + 9 + 1 + read-write + + + BYTERECV + Set to enable the Byte Receive Interrupt. +Interrupts when a byte of data is received +Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually. + 8 + 1 + read-write + + + BYTETRANS + Set to enable the Byte Transmit Interrupt. +Interrupts when a byte of data is transmitted. + 7 + 1 + read-write + + + START + Set to enable the START Condition Interrupt. +Interrupts when a START condition/repeated START condition is detected. + 6 + 1 + read-write + + + STOP + Set to enable the STOP Condition Interrupt +Interrupts when a STOP condition is detected. + 5 + 1 + read-write + + + ARBLOSE + Set to enable the Arbitration Lose Interrupt. +Master: interrupts when the controller loses the bus arbitration +Slave: not available in this mode. + 4 + 1 + read-write + + + ADDRHIT + Set to enable the Address Hit Interrupt. +Master: interrupts when the addressed slave returned an ACK. +Slave: interrupts when the controller is addressed. + 3 + 1 + read-write + + + FIFOHALF + Set to enable the FIFO Half Interrupt. +Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. +Transmitter: Interrupts when the FIFO is half-empty, i.e. there is <= 1/2 entries in the FIFO. +This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered. + 2 + 1 + read-write + + + FIFOFULL + Set to enable the FIFO Full Interrupt. +Interrupts when the FIFO is full. + 1 + 1 + read-write + + + FIFOEMPTY + Set to enabled the FIFO Empty Interrupt +Interrupts when the FIFO is empty. + 0 + 1 + read-write + + + + + Status + Status Register + 0x18 + 32 + 0x00000001 + 0xFFFFFFFF + + + LINESDA + Indicates the current status of the SDA line on the bus +1: high +0: low + 14 + 1 + read-only + + + LINESCL + Indicates the current status of the SCL line on the bus +1: high +0: low + 13 + 1 + read-only + + + GENCALL + Indicates that the address of the current transaction is a general call address: +1: General call +0: Not general call + 12 + 1 + read-only + + + BUSBUSY + Indicates that the bus is busy +The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus +1: Busy +0: Not busy + 11 + 1 + read-only + + + ACK + Indicates the type of the last received/transmitted acknowledgement bit: +1: ACK +0: NACK + 10 + 1 + read-only + + + CMPL + Transaction Completion +Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration +Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked. + 9 + 1 + write-only + + + BYTERECV + Indicates that a byte of data has been received. + 8 + 1 + write-only + + + BYTETRANS + Indicates that a byte of data has been transmitted. + 7 + 1 + write-only + + + START + Indicates that a START Condition or a repeated START condition has been transmitted/received. + 6 + 1 + write-only + + + STOP + Indicates that a STOP Condition has been transmitted/received. + 5 + 1 + write-only + + + ARBLOSE + Indicates that the controller has lost the bus arbitration. + 4 + 1 + write-only + + + ADDRHIT + Master: indicates that a slave has responded to the transaction. +Slave: indicates that a transaction is targeting the controller (including the General Call). + 3 + 1 + write-only + + + FIFOHALF + Transmitter: Indicates that the FIFO is half-empty. + 2 + 1 + read-only + + + FIFOFULL + Indicates that the FIFO is full. + 1 + 1 + read-only + + + FIFOEMPTY + Indicates that the FIFO is empty. + 0 + 1 + read-only + + + + + Addr + Address Register + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + The slave address. +For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid + 0 + 10 + read-write + + + + + Data + Data Register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + Write this register to put one byte of data to the FIFO. +Read this register to get one byte of data from the FIFO. + 0 + 8 + read-write + + + + + Ctrl + Control Register + 0x24 + 32 + 0x00001E00 + 0x000F9FFF + + + PHASE_START + Enable this bit to send a START condition at the beginning of transaction. +Master mode only. + 12 + 1 + read-write + + + PHASE_ADDR + Enable this bit to send the address after START condition. +Master mode only. + 11 + 1 + read-write + + + PHASE_DATA + Enable this bit to send the data after Address phase. +Master mode only. + 10 + 1 + read-write + + + PHASE_STOP + Enable this bit to send a STOP condition at the end of a transaction. +Master mode only. + 9 + 1 + read-write + + + DIR + Transaction direction +Master: Set this bit to determine the direction for the next transaction. +0: Transmitter +1: Receiver +Slave: The direction of the last received transaction. +0: Receiver +1: Transmitter + 8 + 1 + read-write + + + DATACNT + Data counts in bytes. +Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. +Slave: the meaning of DataCnt depends on the DMA mode: +If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. +If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. + 0 + 8 + read-write + + + + + Cmd + Command Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMD + Write this register with the following values to perform the corresponding actions: +0x0: no action +0x1: issue a data transaction (Master only) +0x2: respond with an ACK to the received byte +0x3: respond with a NACK to the received byte +0x4: clear the FIFO +0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) +When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. +Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled. + 0 + 3 + read-write + + + + + Setup + Setup Register + 0x2c + 32 + 0x05252100 + 0xFFFFFFFF + + + T_SUDAT + T_SUDAT defines the data setup time before releasing the SCL. +Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) +tpclk = PCLK period +TPM = The multiplier value in Timing Parameter Multiplier Register + 24 + 5 + read-write + + + T_SP + T_SP defines the pulse width of spikes that must be suppressed by the input filter. +Pulse width = T_SP * tpclk* (TPM+1) + 21 + 3 + read-write + + + T_HDDAT + T_HDDAT defines the data hold time after SCL goes LOW +Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) + 16 + 5 + read-write + + + T_SCLRADIO + The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. +SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) +1: ratio = 2 +0: ratio = 1 +This field is only valid when the controller is in the master mode. + 13 + 1 + read-write + + + T_SCLHI + The HIGH period of generated SCL clock is defined by T_SCLHi. +SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) +The T_SCLHi value must be greater than T_SP and T_HDDAT values. +This field is only valid when the controller is in the master mode. + 4 + 9 + read-write + + + DMAEN + Enable the direct memory access mode data transfer. +1: Enable +0: Disable + 3 + 1 + read-write + + + MASTER + Configure this device as a master or a slave. +1: Master mode +0: Slave mode + 2 + 1 + read-write + + + ADDRESSING + I2C addressing mode: +1: 10-bit addressing mode +0: 7-bit addressing mode + 1 + 1 + read-write + + + IICEN + Enable the I2C controller. +1: Enable +0: Disable + 0 + 1 + read-write + + + + + TPM + I2C Timing Paramater Multiplier + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + TPM + A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). + 0 + 5 + read-write + + + + + + + I2C1 + I2C1 + I2C + 0xf3024000 + + + I2C2 + I2C2 + I2C + 0xf3028000 + + + I2C3 + I2C3 + I2C + 0xf302c000 + + + SDP + SDP + SDP + 0xf304c000 + + 0x0 + 0x60 + registers + + + + SDPCR + SDP control register + 0x0 + 32 + 0x30000000 + 0xFFFE0001 + + + SFTRST + soft reset. +Write 1 then 0, to reset the SDP block. + 31 + 1 + read-write + + + CLKGAT + Clock Gate for the SDP main logic. +Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block. + 30 + 1 + read-write + + + CIPDIS + Cipher Disable, read the info, whether the CIPHER features is besing disable in this chip or not. +1, Cipher is disabled in this chip. +0, Cipher is enabled in this chip. + 29 + 1 + read-only + + + HASDIS + HASH Disable, read the info, whether the HASH features is besing disable in this chip or not. +1, HASH is disabled in this chip. +0, HASH is enabled in this chip. + 28 + 1 + read-only + + + CIPHEN + Cipher Enablement, controlled by SW. +1, Cipher is Enabled. +0, Cipher is Disabled. + 23 + 1 + read-write + + + HASHEN + HASH Enablement, controlled by SW. +1, HASH is Enabled. +0, HASH is Disabled. + 22 + 1 + read-write + + + MCPEN + Memory Copy Enablement, controlled by SW. +1, Memory copy is Enabled. +0, Memory copy is Disabled. + 21 + 1 + read-write + + + CONFEN + Constant Fill to memory, controlled by SW. +1, Constant fill is Enabled. +0, Constant fill is Disabled. + 20 + 1 + read-write + + + DCRPDI + Decryption Disable bit, Write to 1 to disable the decryption. + 19 + 1 + read-write + + + TSTPKT0IRQ + Test purpose for interrupt when Packet counter reachs "0", but CHAIN=1 in the current packet. + 17 + 1 + read-write + + + INTEN + Interrupt Enablement, controlled by SW. +1, SDP interrupt is enabled. +0, SDP interrupt is disabled. + 0 + 1 + read-write + + + + + MODCTRL + Mod control register. + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + AESALG + AES algorithem selection. +0x0 = AES 128; +0x1 = AES 256; +0x8 = SM4； +Others, reserved. + 28 + 4 + read-write + + + AESMOD + AES mode selection. +0x0 = ECB; +0x1 = CBC; +Others, reserved. + 24 + 4 + read-write + + + AESKS + AES Key Selection. +These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following: +0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key. +0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. +.... +0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key. +0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. +0x20: kman_sk0[127:0] from the key manager for AES128; AES256 will use kman_sk0[255:0] as AES key. +0x21: kman_sk0[255:128] from the key manager for AES128; not valid for AES256. +0x22: kman_sk1[127:0] from the key manager for AES128; AES256 will use kman_sk1[255:0] as AES key. +0x23: kman_sk1[255:128] from the key manager for AES128; not valid for AES256. +0x24: kman_sk2[127:0] from the key manager for AES128; AES256 will use kman_sk2[255:0] as AES key. +0x25: kman_sk2[255:128] from the key manager for AES128; not valid for AES256. +0x26: kman_sk3[127:0] from the key manager for AES128; AES256 will use kman_sk3[255:0] as AES key. +0x27: kman_sk3[255:128] from the key manager for AES128; not valid for AES256. +0x30: exip0_key[127:0] from OTP for AES128; AES256 will use exip0_key[255:0] as AES key. +0x31: exip0_key[255:128] from OTP for AES128; not valid for AES256. +0x32: exip1_key[127:0] from OTP for AES128; AES256 will use exip1_key[255:0] as AES key. +0x33: exip1_key[255:128] from OTP for AES128; not valid for AES256. +Other values, reserved. + 18 + 6 + read-write + + + AESDIR + AES direction +1x1, AES Decryption +1x0, AES Encryption. + 16 + 1 + read-write + + + HASALG + HASH Algorithem selection. +0x0 SHA1 — +0x1 CRC32 — +0x2 SHA256 — + 12 + 4 + read-write + + + CRCEN + CRC enable. +1x1, CRC is enabled. +1x0, CRC is disabled. + 11 + 1 + read-write + + + HASCHK + HASH Check Enable Bit. +1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers; +1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result. +For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words. + 10 + 1 + read-write + + + HASOUT + When hashing is enabled, this bit controls the input or output data of the AES engine is hashed. +0 INPUT HASH +1 OUTPUT HASH + 9 + 1 + read-write + + + DINSWP + Decide whether the SDP byteswaps the input data (big-endian data); +When all bits are set, the data is assumed to be in the big-endian format + 4 + 2 + read-write + + + DOUTSWP + Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format + 2 + 2 + read-write + + + KEYSWP + Decide whether the SDP byteswaps the Key (big-endian data). +When all bits are set, the data is assumed to be in the big-endian format + 0 + 2 + read-write + + + + + PKTCNT + packet counter registers. + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTVAL + This read-only field shows the current (instantaneous) value of the packet counter + 16 + 8 + read-only + + + CNTINCR + The value written to this field is added to the spacket count. + 0 + 8 + read-write + + + + + STA + Status Registers + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + TAG + packet tag. + 24 + 8 + read-only + + + IRQ + interrupt Request, requested when error happen, or when packet processing done, packet counter reach to zero. + 23 + 1 + write-only + + + CHN1PKT0 + the chain buffer "chain" bit is "1", while packet counter is "0", now, waiting for new buffer data. + 20 + 1 + write-only + + + AESBSY + AES Busy + 19 + 1 + read-only + + + HASBSY + Hashing Busy + 18 + 1 + read-only + + + PKTCNT0 + Packet Counter registers reachs to ZERO now. + 17 + 1 + write-only + + + PKTDON + Packet processing done, will trigger this itnerrrupt when the "PKTINT" bit set in the packet control word. + 16 + 1 + write-only + + + ERRSET + Working mode setup error. + 5 + 1 + write-only + + + ERRPKT + Packet head access error, or status update error. + 4 + 1 + write-only + + + ERRSRC + Source Buffer Access Error + 3 + 1 + write-only + + + ERRDST + Destination Buffer Error + 2 + 1 + write-only + + + ERRHAS + Hashing Check Error + 1 + 1 + write-only + + + ERRCHAIN + buffer chain error happen when packet's CHAIN bit=0, but the Packet counter is still not zero. + 0 + 1 + write-only + + + + + KEYADDR + Key Address + 0x10 + 32 + 0x00000040 + 0xFFFFFFFF + + + INDEX + To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. +Key index pointer. The valid indices are 0-[number_keys]. +In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses. + 16 + 8 + read-write + + + SUBWRD + Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field +increments; To write a key, the software must first write the desired key index/subword to this register. + 0 + 2 + read-write + + + + + KEYDAT + Key Data + 0x14 + 32 + 0x00000030 + 0xFFFFFFFF + + + KEYDAT + This register provides the write access to the key/key subword specified by the key index register. +Writing this location updates the selected subword for the key located at the index +specified by the key index register. The write also triggers the SUBWORD field of the +KEY register to increment to the next higher word in the key + 0 + 32 + read-write + + + + + 4 + 0x4 + CIPHIV0,CIPHIV1,CIPHIV2,CIPHIV3 + CIPHIV[%s] + no description available + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + CIPHIV + cipher initialization vector. + 0 + 32 + read-write + + + + + 8 + 0x4 + HASWRD0,HASWRD1,HASWRD2,HASWRD3,HASWRD4,HASWRD5,HASWRD6,HASWRD7 + HASWRD[%s] + no description available + 0x28 + 32 + 0x00000030 + 0xFFFFFFFF + + + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + 0 + 32 + read-write + + + + + CMDPTR + Command Pointer + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMDPTR + current command addresses the register points to the multiword +descriptor that is to be executed (or is currently being executed) + 0 + 32 + read-write + + + + + NPKTPTR + Next Packet Address Pointer + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + NPKTPTR + Next Packet Address Pointer + 0 + 32 + read-write + + + + + PKTCTL + Packet Control Registers + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTTAG + packet tag + 24 + 8 + read-write + + + CIPHIV + Load Initial Vector for the AES in this packet. + 6 + 1 + read-write + + + HASFNL + Hash Termination packet + 5 + 1 + read-write + + + HASINI + Hash Initialization packat + 4 + 1 + read-write + + + CHAIN + whether the next command pointer register must be loaded into the channel's current descriptor +pointer. + 3 + 1 + read-write + + + DCRSEMA + whether the channel's semaphore must be decremented at the end of the current operation. +When the semaphore reaches a value of zero, no more operations are issued from the channel. + 2 + 1 + read-write + + + PKTINT + Reflects whether the channel must issue an interrupt upon the completion of the packet + 1 + 1 + read-write + + + + + PKTSRC + Packet Memory Source Address + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTSRC + Packet Memory Source Address + 0 + 32 + read-write + + + + + PKTDST + Packet Memory Destination Address + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTDST + Packet Memory Destination Address + 0 + 32 + read-write + + + + + PKTBUF + Packet buffer size. + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTBUF + No description available + 0 + 32 + read-write + + + + + + + FEMC + FEMC + FEMC + 0xf3050000 + + 0x0 + 0x154 + registers + + + + CTRL + Control Register + 0x0 + 32 + 0x00000000 + 0x1FFF0007 + + + BTO + Bus timeout cycles +AXI Bus timeout cycle is as following (255*(2^BTO)): +00000b - 255*1 +00001-11110b - 255*2 - 255*2^30 +11111b - 255*2^31 + 24 + 5 + read-write + + + CTO + Command Execution timeout cycles +When Command Execution time exceed this timeout cycles, IPCMDERR or AXICMDERR interrupt is +generated. When CTO is set to zero, timeout cycle is 256*1024 cycle. otherwisee timeout cycle is +CTO*1024 cycle. + 16 + 8 + read-write + + + DQS + DQS (read strobe) mode +0b - Dummy read strobe loopbacked internally +1b - Dummy read strobe loopbacked from DQS pad + 2 + 1 + read-write + + + DIS + Module Disable +0b - Module enabled +1b - Module disabled + 1 + 1 + read-write + + + RST + Software Reset +Reset all internal logic in SEMC except configuration register + 0 + 1 + read-write + + + + + IOCTRL + IO Mux Control Register + 0x4 + 32 + 0x00000000 + 0x000000F0 + + + IO_CSX + IO_CSX output selection +0001b - SDRAM CS1 +0110b - SRAM CE# + 4 + 4 + read-write + + + + + BMW0 + Bus (AXI) Weight Control Register 0 + 0x8 + 32 + 0x00000000 + 0x00FFFFFF + + + RWS + Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is +same as current executing command with read/write operation switch. + 16 + 8 + read-write + + + SH + Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is +same as current executing command without read/write operation switch. + 8 + 8 + read-write + + + AGE + Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is +multiplied by WAGE to get weight score. + 4 + 4 + read-write + + + QOS + Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator +for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS +is multiplied by WQOS to get weight score. + 0 + 4 + read-write + + + + + BMW1 + Bus (AXI) Weight Control Register 1 + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + BR + Weight of Bank Rotation. This weight score is valid when queue command's bank is not same as current +executing command. + 24 + 8 + read-write + + + RWS + Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is +same as current executing command with read/write operation switch. + 16 + 8 + read-write + + + PH + Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is +same as current executing command without read/write operation switch. + 8 + 8 + read-write + + + AGE + Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is +multiplied by WAGE to get weight score. + 4 + 4 + read-write + + + QOS + Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator +for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS +is multiplied by WQOS to get weight score. + 0 + 4 + read-write + + + + + 3 + 0x4 + BASE0,BASE1,rsv2,rsv3,rsv4,rsv5,BASE6 + BR[%s] + no description available + 0x10 + 32 + 0x00000000 + 0xFFFFF03F + + + BASE + Base Address +This field determines high position 20 bits of SoC level Base Address. SoC level Base Address low +position 12 bits are all zero. + 12 + 20 + read-write + + + SIZE + Memory size +00000b - 4KB +00001b - 8KB +00010b - 16KB +00011b - 32KB +00100b - 64KB +00101b - 128KB +00110b - 256KB +00111b - 512KB +01000b - 1MB +01001b - 2MB +01010b - 4MB +01011b - 8MB +01100b - 16MB +01101b - 32MB +01110b - 64MB +01111b - 128MB +10000b - 256MB +10001b - 512MB +10010b - 1GB +10011b - 2GB +10100-11111b - 4GB + 1 + 5 + read-write + + + VLD + Valid + 0 + 1 + read-write + + + + + INTEN + Interrupt Enable Register + 0x38 + 32 + 0x00000000 + 0x0000000F + + + AXIBUSERR + AXI BUS error interrupt enable +0b - Interrupt is disabled +1b - Interrupt is enabled + 3 + 1 + read-write + + + AXICMDERR + AXI command error interrupt enable +0b - Interrupt is disabled +1b - Interrupt is enabled + 2 + 1 + read-write + + + IPCMDERR + IP command error interrupt enable +0b - Interrupt is disabled +1b - Interrupt is enabled + 1 + 1 + read-write + + + IPCMDDONE + IP command done interrupt enable +0b - Interrupt is disabled +1b - Interrupt is enabled + 0 + 1 + read-write + + + + + INTR + Interrupt Status Register + 0x3c + 32 + 0x00000000 + 0x0000000F + + + AXIBUSERR + AXI bus error interrupt +AXI Bus error interrupt is generated in following cases: +• AXI address is invalid +• AXI 8-bit or 16-bit WRAP write/read + 3 + 1 + write-only + + + AXICMDERR + AXI command error interrupt +AXI command error interrupt is generated when AXI command execution timeout. + 2 + 1 + write-only + + + IPCMDERR + IP command error done interrupt +IP command error interrupt is generated in following case: +• IP Command Address target invalid device space +• IP Command Code unsupported +• IP Command triggered when previous command + 1 + 1 + write-only + + + IPCMDDONE + IP command normal done interrupt + 0 + 1 + write-only + + + + + SDRCTRL0 + SDRAM Control Register 0 + 0x40 + 32 + 0x00000000 + 0x00004FFB + + + BANK2 + 2 Bank selection bit +0b - SDRAM device has 4 banks. +1b - SDRAM device has 2 banks. + 14 + 1 + read-write + + + CAS + CAS Latency +00b - 1 +01b - 1 +10b - 2 +11b - 3 + 10 + 2 + read-write + + + COL + Column address bit number +00b - 12 bit +01b - 11 bit +10b - 10 bit +11b - 9 bit + 8 + 2 + read-write + + + COL8 + Column 8 selection bit +0b - Column address bit number is decided by COL field. +1b - Column address bit number is 8. COL field is ignored. + 7 + 1 + read-write + + + BURSTLEN + Burst Length +000b - 1 +001b - 2 +010b - 4 +011b - 8 +100b - 8 +101b - 8 +110b - 8 +111b - 8 + 4 + 3 + read-write + + + HIGHBAND + high band select +0: use data[15:0] for 16bit SDRAM; +1: use data[31:16] for 16bit SDRAM; +only used when Port Size is 16bit(PORTSZ=01b) + 3 + 1 + read-write + + + PORTSZ + Port Size +00b - 8bit +01b - 16bit +10b - 32bit + 0 + 2 + read-write + + + + + SDRCTRL1 + SDRAM Control Register 1 + 0x44 + 32 + 0x00000000 + 0x00FFFFFF + + + ACT2PRE + ACT to Precharge minimum time +It is promised ACT2PRE+1 clock cycles delay between ACTIVE command to PRECHARGE/PRECHARGE_ALL command. + 20 + 4 + read-write + + + CKEOFF + CKE OFF minimum time +It is promised clock suspend last at leat CKEOFF+1 clock cycles. + 16 + 4 + read-write + + + WRC + Write recovery time +It is promised WRC+1 clock cycles delay between WRITE command to PRECHARGE/PRECHARGE_ALL command. This could help to meet tWR timing requirement by SDRAM device. + 13 + 3 + read-write + + + RFRC + Refresh recovery time +It is promised RFRC+1 clock cycles delay between REFRESH command to ACTIVE command. Thiscould help to meet tRFC timing requirement by SDRAM device. + 8 + 5 + read-write + + + ACT2RW + ACT to Read/Write wait time +It is promised ACT2RW+1 clock cycles delay between ACTIVE command to READ/WRITE command.This could help to meet tRCD timing requirement by SDRAM device. + 4 + 4 + read-write + + + PRE2ACT + PRECHARGE to ACT/Refresh wait time +It is promised PRE2ACT+1 clock cycles delay between PRECHARGE/PRECHARGE_ALL commandto ACTIVE/REFRESH command. This could help to meet tRP timing requirement by SDRAM device. + 0 + 4 + read-write + + + + + SDRCTRL2 + SDRAM Control Register 2 + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + ITO + SDRAM Idle timeout +It closes all opened pages if the SDRAM idle time lasts more than idle timeout period. SDRAM is +considered idle when there is no AXI Bus transfer and no SDRAM command pending. +00000000b - IDLE timeout period is 256*Prescale period. +00000001-11111111b - IDLE timeout period is ITO*Prescale period. + 24 + 8 + read-write + + + ACT2ACT + ACT to ACT wait time +It is promised ACT2ACT+1 clock cycles delay between ACTIVE command to ACTIVE command. This +could help to meet tRRD timing requirement by SDRAM device. + 16 + 8 + read-write + + + REF2REF + Refresh to Refresh wait time +It is promised REF2REF+1 clock cycles delay between REFRESH command to REFRESH command. +This could help to meet tRFC timing requirement by SDRAM device. + 8 + 8 + read-write + + + SRRC + Self Refresh Recovery time +It is promised SRRC+1 clock cycles delay between Self-REFRESH command to any command. + 0 + 8 + read-write + + + + + SDRCTRL3 + SDRAM Control Register 3 + 0x4c + 32 + 0x00000000 + 0xFFFFFF0F + + + UT + Refresh urgent threshold +Internal refresh request is generated on every Refresh period. Before internal request timer count up to +urgent request threshold, the refresh request is considered as normal refresh request. Normal refresh +request is handled in lower priority than any pending AXI command or IP command to SDRAM device. +When internal request timer count up to this urgent threshold, refresh request is considered as urgent +refresh request. Urgent refresh request is handled in higher priority than any pending AXI command or IP +command to SDRAM device. +NOTE: When urgent threshold is no less than refresh period, refresh request is always considered as +urgent refresh request. +Refresh urgent threshold is as follwoing: +00000000b - 256*Prescaler period +00000001-11111111b - UT*Prescaler period + 24 + 8 + read-write + + + RT + Refresh timer period +Refresh timer period is as following: +00000000b - 256*Prescaler period +00000001-11111111b - RT*Prescaler period + 16 + 8 + read-write + + + PRESCALE + Prescaler timer period +Prescaler timer period is as following: +00000000b - 256*16 clock cycles +00000001-11111111b - PRESCALE*16 clock cycles + 8 + 8 + read-write + + + REBL + Refresh burst length +It could send multiple Auto-Refresh command in one burst when REBL is set to non-zero. The +number of Auto-Refresh command cycle sent to all SDRAM device in one refresh period is as following. +000b - 1 +001b - 2 +010b - 3 +011b - 4 +100b - 5 +101b - 6 +110b - 7 +111b - 8 + 1 + 3 + read-write + + + REN + Refresh enable + 0 + 1 + read-write + + + + + SRCTRL0 + SRAM control register 0 + 0x70 + 32 + 0x00000000 + 0x00000F01 + + + ADVH + ADV hold state +0b - ADV is high during address hold state +1b - ADV is low during address hold state + 11 + 1 + read-write + + + ADVP + ADV polarity +0b - ADV is active low +1b - ADV is active high + 10 + 1 + read-write + + + ADM + address data mode +00b - address and data MUX mode +11b - address and data non-MUX mode + 8 + 2 + read-write + + + PORTSZ + port size +0b - 8bit +1b - 16bit + 0 + 1 + read-write + + + + + SRCTRL1 + SRAM control register 1 + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + OEH + OE high time, is OEH+1 clock cycles + 28 + 4 + read-write + + + OEL + OE low time, is OEL+1 clock cycles + 24 + 4 + read-write + + + WEH + WE high time, is WEH+1 clock cycles + 20 + 4 + read-write + + + WEL + WE low time, is WEL+1 clock cycles + 16 + 4 + read-write + + + AH + Address hold time, is AH+1 clock cycles + 12 + 4 + read-write + + + AS + Address setup time, is AS+1 clock cycles + 8 + 4 + read-write + + + CEH + Chip enable hold time, is CEH+1 clock cycles + 4 + 4 + read-write + + + CES + Chip enable setup time, is CES+1 clock cycles + 0 + 4 + read-write + + + + + SADDR + IP Command Control Register 0 + 0x90 + 32 + 0x00000000 + 0xFFFFFFFF + + + SA + Slave address + 0 + 32 + read-write + + + + + DATSZ + IP Command Control Register 1 + 0x94 + 32 + 0x00000000 + 0x00000007 + + + DATSZ + Data Size in Byte +When IP command is not a write/read operation, DATSZ field would be ignored. +000b - 4 +001b - 1 +010b - 2 +011b - 3 +100b - 4 +101b - 4 +110b - 4 +111b - 4 + 0 + 3 + read-write + + + + + BYTEMSK + IP Command Control Register 2 + 0x98 + 32 + 0x00000000 + 0x0000000F + + + BM3 + Byte Mask for Byte 3 (IPTXD bit 31:24) +0b - Byte Unmasked +1b - Byte Masked + 3 + 1 + read-write + + + BM2 + Byte Mask for Byte 2 (IPTXD bit 23:16) +0b - Byte Unmasked +1b - Byte Masked + 2 + 1 + read-write + + + BM1 + Byte Mask for Byte 1 (IPTXD bit 15:8) +0b - Byte Unmasked +1b - Byte Masked + 1 + 1 + read-write + + + BM0 + Byte Mask for Byte 0 (IPTXD bit 7:0) +0b - Byte Unmasked +1b - Byte Masked + 0 + 1 + read-write + + + + + IPCMD + IP Command Register + 0x9c + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + This field should be written with 0x5AA5 when trigging an IP command for all device types. The memory +device is selected by BRx settings and IPCR0 registers. + 16 + 16 + write-only + + + CMD + SDRAM Commands: +• 0x8: READ +• 0x9: WRITE +• 0xA: MODESET +• 0xB: ACTIVE +• 0xC: AUTO REFRESH +• 0xD: SELF REFRESH +• 0xE: PRECHARGE +• 0xF: PRECHARGE ALL +• Others: RSVD +NOTE: SELF REFRESH is sent to all SDRAM devices because they shared same CLK pin. + 0 + 16 + read-write + + + + + IPTX + TX DATA Register + 0xa0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DAT + Data + 0 + 32 + read-write + + + + + IPRX + RX DATA Register + 0xb0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DAT + Data + 0 + 32 + read-write + + + + + STAT0 + Status Register 0 + 0xc0 + 32 + 0x00000000 + 0x00000001 + + + IDLE + Indicating whether it is in IDLE state. +When IDLE=1, it is in IDLE state. There is no pending AXI command in internal queue and no +pending device access. + 0 + 1 + read-only + + + + + DLYCFG + Delay Line Config Register + 0x150 + 32 + 0x00000000 + 0x0000203F + + + OE + delay clock output enable, should be set after setting DLYEN and DLYSEL + 13 + 1 + read-write + + + DLYSEL + delay line select, 0 for 1 cell, 31 for all 32 cells + 1 + 5 + read-write + + + DLYEN + delay line enable + 0 + 1 + read-write + + + + + + + SYSCTL + SYSCTL + SYSCTL + 0xf4000000 + + 0x0 + 0x3000 + registers + + + + 195 + 0x4 + cpu0_core,cpu0_subsys,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,cpu1_core,cpx1_subsys,rsv10,rsv11,rsv12,rsv13,rsv14,rsv15,rsv16,rsv17,rsv18,rsv19,rsv20,pow_con,pow_vis,pow_cpu0,pow_cpu1,rst_soc,rst_con,rst_vis,rst_cpu0,rst_cpu1,rsv30,rsv31,clk_src_xtal,clk_src_pll0,clk_src_pll0clk0,clk_src_pll1,clk_src_pll1clk0,clk_src_pll1clk1,clk_src_pll2,clk_src_pll2clk0,clk_src_pll2clk1,clk_src_pll3,clk_src_pll3clk0,clk_src_pll4,clk_src_pll4clk0,rsv45,rsv46,rsv47,rsv48,rsv49,rsv50,rsv51,rsv52,rsv53,rsv54,rsv55,rsv56,rsv57,rsv58,rsv59,rsv60,rsv61,rsv62,rsv63,clk_top_cpu0,clk_top_mchtmr0,clk_top_cpu1,clk_top_mchtmr1,clk_top_axi,clk_top_conn,clk_top_vis,clk_top_ahb,clk_top_femc,clk_top_xpi0,clk_top_xpi1,clk_top_gptmr0,clk_top_gptmr1,clk_top_gptmr2,clk_top_gptmr3,clk_top_gptmr4,clk_top_gptmr5,clk_top_gptmr6,clk_top_gptmr7,clk_top_uart0,clk_top_uart1,clk_top_uart2,clk_top_uart3,clk_top_uart4,clk_top_uart5,clk_top_uart6,clk_top_uart7,clk_top_uart8,clk_top_uart9,clk_top_uart10,clk_top_uart11,clk_top_uart12,clk_top_uart13,clk_top_uart14,clk_top_uart15,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,clk_top_ptpc,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_aud0,clk_top_aud1,clk_top_aud2,clk_top_lcdc,clk_top_cam0,clk_top_cam1,clk_top_enet0,clk_top_enet1,clk_top_ptp0,clk_top_ptp1,clk_top_ref0,clk_top_ref1,clk_top_ntmr0,clk_top_ntmr1,clk_top_sdxc0,clk_top_sdxc1,rsv131,rsv132,rsv133,rsv134,rsv135,rsv136,rsv137,rsv138,rsv139,rsv140,rsv141,rsv142,rsv143,rsv144,rsv145,rsv146,rsv147,rsv148,rsv149,rsv150,rsv151,rsv152,rsv153,rsv154,rsv155,rsv156,rsv157,rsv158,rsv159,rsv160,rsv161,rsv162,rsv163,rsv164,rsv165,rsv166,rsv167,rsv168,rsv169,rsv170,rsv171,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,clk_top_adc0,clk_top_adc1,clk_top_adc2,clk_top_adc3,clk_top_i2s0,clk_top_i2s1,clk_top_i2s2,clk_top_i2s3,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,ahbapb_bus,axi_bus,conn_bus,vis_bus,femc,rom,lmm0,lmm1,mchtmr0,mchtmr1,axi_sram0,axi_sram1,xpi0,xpi1,sdp,rng,keym,hdma,xdma,gpio,mbx0,mbx1,wdg0,wdg1,wdg2,wdg3,gptmr0,gptmr1,gptmr2,gptmr3,gptmr4,gptmr5,gptmr6,gptmr7,uart0,uart1,uart2,uart3,uart4,uart5,uart6,uart7,uart8,uart9,uart10,uart11,uart12,uart13,uart14,uart15,i2c0,i2c1,i2c2,i2c3,spi0,spi1,spi2,spi3,can0,can1,can2,can3,ptpc,adc0,adc1,adc2,adc3,acmp,i2s0,i2s1,i2s2,i2s3,pdm,dao,synt,mot0,mot1,mot2,mot3,lcdc,cam0,cam1,jpeg,pdma,enet0,enet1,ntmr0,ntmr1,sdxc0,sdxc1,usb0,usb1,ref0,ref1 + RESOURCE[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + 3 + 0x10 + 0,1,2 + GROUP0[%s] + no description available + 0x800 + + VALUE + Goup setting + 0x0 + 32 + 0x00000023 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + SET + Goup setting + 0x4 + 32 + 0x00000023 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + CLEAR + Goup setting + 0x8 + 32 + 0x00000023 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + TOGGLE + Goup setting + 0xc + 32 + 0x00000023 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + + 3 + 0x10 + 0,1,2 + GROUP1[%s] + no description available + 0x840 + + VALUE + Goup setting + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + SET + Goup setting + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + CLEAR + Goup setting + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + TOGGLE + Goup setting + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + + 2 + 0x10 + cpu0,cpu1 + AFFILIATE[%s] + no description available + 0x900 + + VALUE + Affiliate of Group + 0x0 + 32 + 0x00000001 + 0x0000000F + + + LINK + Affiliate groups of cpu0 +bit0: cpu0 depends on logic node0 +bit1: cpu0 depends on logic node1 +bit2: cpu0 depends on logic node2 +bit3: cpu0 depends on logic node3 + 0 + 4 + read-write + + + + + SET + Affiliate of Group + 0x4 + 32 + 0x00000001 + 0x0000000F + + + LINK + Affiliate groups of cpu0 +bit0: cpu0 depends on logic node0 +bit1: cpu0 depends on logic node1 +bit2: cpu0 depends on logic node2 +bit3: cpu0 depends on logic node3 + 0 + 4 + read-write + + + + + CLEAR + Affiliate of Group + 0x8 + 32 + 0x00000001 + 0x0000000F + + + LINK + Affiliate groups of cpu0 +bit0: cpu0 depends on logic node0 +bit1: cpu0 depends on logic node1 +bit2: cpu0 depends on logic node2 +bit3: cpu0 depends on logic node3 + 0 + 4 + read-write + + + + + TOGGLE + Affiliate of Group + 0xc + 32 + 0x00000001 + 0x0000000F + + + LINK + Affiliate groups of cpu0 +bit0: cpu0 depends on logic node0 +bit1: cpu0 depends on logic node1 +bit2: cpu0 depends on logic node2 +bit3: cpu0 depends on logic node3 + 0 + 4 + read-write + + + + + + 2 + 0x10 + cpu0,cpu1 + RETENTION[%s] + no description available + 0x920 + + VALUE + Retention Control + 0x0 + 32 + 0x0000000F + 0x0003FFFF + + + LINK + retention setting while system sleep, each bit represents a resource +bit0: soc_pow +bit1: soc_rst +bit2: cpu0_pow +bit3: cpu0_rst +bit4: cpu1_pow +bit5: cpu1_rst +bit6: con_pow +bit7: con_rst +bit8: vis_pow +bit9: vis_rst +bit10: xtal +bit11: pll0 +bit12: pll1 +bit13: pll2 +bit14: pll3 +bit15: pll4 + 0 + 18 + read-write + + + + + SET + Retention Control + 0x4 + 32 + 0x0000000F + 0x0003FFFF + + + LINK + retention setting while system sleep + 0 + 18 + read-write + + + + + CLEAR + Retention Control + 0x8 + 32 + 0x0000000F + 0x0003FFFF + + + LINK + retention setting while system sleep + 0 + 18 + read-write + + + + + TOGGLE + Retention Control + 0xc + 32 + 0x0000000F + 0x0003FFFF + + + LINK + retention setting while system sleep + 0 + 18 + read-write + + + + + + 4 + 0x10 + cpu0,cpu1,con,vis + POWER[%s] + no description available + 0x1000 + + status + Power Setting + 0x0 + 32 + 0x80000000 + 0xC0001100 + + + FLAG + flag represents power cycle happened from last clear of this bit +0: power domain did not edurance power cycle since last clear of this bit +1: power domain enduranced power cycle since last clear of this bit + 31 + 1 + read-write + + + FLAG_WAKE + flag represents wakeup power cycle happened from last clear of this bit +0: power domain did not edurance wakeup power cycle since last clear of this bit +1: power domain enduranced wakeup power cycle since last clear of this bit + 30 + 1 + read-write + + + LF_DISABLE + low fanout power switch disable +0: low fanout power switches are turned on +1: low fanout power switches are truned off + 12 + 1 + read-only + + + LF_ACK + low fanout power switch feedback +0: low fanout power switches are turned on +1: low fanout power switches are truned off + 8 + 1 + read-only + + + + + lf_wait + Power Setting + 0x4 + 32 + 0x00000255 + 0x000FFFFF + + + WAIT + wait time for low fan out power switch turn on, default value is 255 +0: 0 clock cycle +1: 1 clock cycles +. . . +clock cycles count on 24MHz + 0 + 20 + read-write + + + + + off_wait + Power Setting + 0xc + 32 + 0x00000015 + 0x000FFFFF + + + WAIT + wait time for power switch turn off, default value is 15 +0: 0 clock cycle +1: 1 clock cycles +. . . +clock cycles count on 24MHz + 0 + 20 + read-write + + + + + + 5 + 0x10 + soc,con,vis,cpu0,cpu1 + RESET[%s] + no description available + 0x1400 + + control + Reset Setting + 0x0 + 32 + 0x80000000 + 0xC0000011 + + + FLAG + flag represents reset happened from last clear of this bit +0: domain did not edurance reset cycle since last clear of this bit +1: domain enduranced reset cycle since last clear of this bit + 31 + 1 + read-write + + + FLAG_WAKE + flag represents wakeup reset happened from last clear of this bit +0: domain did not edurance wakeup reset cycle since last clear of this bit +1: domain enduranced wakeup reset cycle since last clear of this bit + 30 + 1 + read-write + + + HOLD + perform reset and hold in reset, until ths bit cleared by software +0: reset is released for function +1: reset is assert and hold + 4 + 1 + read-write + + + RESET + perform reset and release imediately +0: reset is released +1 reset is asserted and will release automatically + 0 + 1 + read-write + + + + + config + Reset Setting + 0x4 + 32 + 0x00643203 + 0x00FFFFFF + + + PRE_WAIT + wait cycle numbers before assert reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 16 + 8 + read-write + + + RSTCLK_NUM + reset clock number(must be even number) +0: 0 cycle +1: 0 cycles +2: 2 cycles +3: 2 cycles +. . . +Note, clock cycle is base on 24M + 8 + 8 + read-write + + + POST_WAIT + time guard band for reset release +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 8 + read-write + + + + + counter + Reset Setting + 0xc + 32 + 0x00000000 + 0x000FFFFF + + + COUNTER + self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 20 + read-write + + + + + + 67 + 0x4 + clk_top_cpu0,clk_top_mchtmr0,clk_top_cpu1,clk_top_mchtmr,clk_top_axi,clk_top_conn,clk_top_vis,clk_top_ahb,clk_top_femc,clk_top_xpi0,clk_top_xpi1,clk_top_gptmr0,clk_top_gptmr1,clk_top_gptmr2,clk_top_gptmr3,clk_top_gptmr4,clk_top_gptmr5,clk_top_gptmr6,clk_top_gptmr7,clk_top_uart0,clk_top_uart1,clk_top_uart2,clk_top_uart3,clk_top_uart4,clk_top_uart5,clk_top_uart6,clk_top_uart7,clk_top_uart8,clk_top_uart9,clk_top_uart10,clk_top_uart11,clk_top_uart12,clk_top_uart13,clk_top_uart14,clk_top_uart15,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,clk_top_ptpc,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_aud0,clk_top_aud1,clk_top_aud2,clk_top_lcdc,clk_top_cam0,clk_top_cam1,clk_top_enet0,clk_top_enet1,clk_top_ptp0,clk_top_ptp1,clk_top_ref0,clk_top_ref1,clk_top_ntmr0,clk_top_ntmr1,clk_top_sdxc0,clk_top_sdxc1 + CLOCK[%s] + no description available + 0x1800 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + 4 + 0x4 + clk_top_adc0,clk_top_adc1,clk_top_adc2,clk_top_adc3 + ADCCLK[%s] + no description available + 0x1c00 + 32 + 0x00000000 + 0xC0000700 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0: ahb clock +1: adc clock 0 +2: adc clock 1 +3: adc clock 2 + 8 + 3 + read-write + + + + + 4 + 0x4 + clk_top_i2s0,clk_top_i2s1,clk_top_i2s2,clk_top_i2s3 + I2SCLK[%s] + no description available + 0x1c10 + 32 + 0x00000000 + 0xC0000700 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0: ahb clock +1: i2s clock 0 +2: i2s clock 1 +3: i2s clock 2 + 8 + 3 + read-write + + + + + global00 + Clock senario + 0x2000 + 32 + 0x00000000 + 0x0000000F + + + PRESET + global clock override request +bit0: override to preset0 +bit1: override to preset1 +bit2: override to preset2 +bit3: override to preset3 + 0 + 4 + read-write + + + + + 4 + 0x20 + slice0,slice1,slice2,slice3 + MONITOR[%s] + no description available + 0x2400 + + control + Clock measure and monitor control + 0x0 + 32 + 0x00000000 + 0x89FFD7FF + + + VALID + result is ready for read +0: not ready +1: result is ready + 31 + 1 + read-write + + + DIV_BUSY + divider is applying new setting + 27 + 1 + read-only + + + OUTEN + enable clock output + 24 + 1 + read-write + + + DIV + output divider + 16 + 8 + read-write + + + HIGH + clock frequency higher than upper limit + 15 + 1 + read-write + + + LOW + clock frequency lower than lower limit + 14 + 1 + read-write + + + START + start measurement + 12 + 1 + read-write + + + MODE + work mode, +0: register value will be compared to measurement +1: upper and lower value will be recordered in register + 10 + 1 + read-write + + + ACCURACY + measurement accuracy, +0: resolution is 1kHz +1: resolution is 1Hz + 9 + 1 + read-write + + + REFERENCE + reference clock selection, +0: 32k +1: 24M + 8 + 1 + read-write + + + SELECTION + clock measurement selection + 0 + 8 + read-write + + + + + current + Clock measure result + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + self updating measure result + 0 + 32 + read-only + + + + + low_limit + Clock lower limit + 0x8 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + FREQUENCY + lower frequency + 0 + 32 + read-write + + + + + high_limit + Clock upper limit + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + upper frequency + 0 + 32 + read-write + + + + + + 2 + 0x400 + cpu0,cpu1 + CPU[%s] + no description available + 0x2800 + + LP + No description available + 0x0 + 32 + 0x00001200 + 0xFF013703 + + + WAKE_CNT + CPU0 wake up counter, counter saturated at 255, write 0x00 to clear + 24 + 8 + read-write + + + HALT + halt request for CPU0, +0: CPU0 will start to execute after reset or receive wakeup request +1: CPU0 will not start after reset, or wakeup after WFI + 16 + 1 + read-write + + + WAKE + CPU0 is waking up +0: CPU0 wake up not asserted +1: CPU0 wake up asserted + 13 + 1 + read-only + + + EXEC + CPU0 is executing +0: CPU0 is not executing +1: CPU0 is executing + 12 + 1 + read-only + + + WAKE_FLAG + CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit +0: CPU0 wakeup not happened +1: CPU0 wakeup happened + 10 + 1 + read-write + + + SLEEP_FLAG + CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit +0: CPU0 sleep not happened +1: CPU0 sleep happened + 9 + 1 + read-write + + + RESET_FLAG + CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit +0: CPU0 sleep not happened +1: CPU0 sleep happened + 8 + 1 + read-write + + + MODE + Low power mode, system behavior after WFI +00: CPU clock stop after WFI +01: System enter low power mode after WFI +10: Keep running after WFI +11: reserved + 0 + 2 + read-write + + + + + LOCK + No description available + 0x4 + 32 + 0x00000002 + 0x0000FFFE + + + GPR + Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset + 2 + 14 + read-write + + + LOCK + Lock bit for CPU_LOCK + 1 + 1 + read-write + + + + + 14 + 0x4 + GPR0,GPR1,GPR2,GPR3,GPR4,GPR5,GPR6,GPR7,GPR8,GPR9,GPR10,GPR11,GPR12,GPR13 + GPR[%s] + no description available + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + 8 + 0x4 + STATUS0,STATUS1,STATUS2,STATUS3,STATUS4,STATUS5,STATUS6,STATUS7 + WAKEUP_STATUS[%s] + no description available + 0x40 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + 8 + 0x4 + ENABLE0,ENABLE1,ENABLE2,ENABLE3,ENABLE4,ENABLE5,ENABLE6,ENABLE7 + WAKEUP_ENABLE[%s] + no description available + 0x80 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + + + + IOC + IOC + IOC + 0xf4040000 + + 0x0 + 0xf60 + registers + + + + 492 + 0x8 + pa00,pa01,pa02,pa03,pa04,pa05,pa06,pa07,pa08,pa09,pa10,pa11,pa12,pa13,pa14,pa15,pa16,pa17,pa18,pa19,pa20,pa21,pa22,pa23,pa24,pa25,pa26,pa27,pa28,pa29,pa30,pa31,pb00,pb01,pb02,pb03,pb04,pb05,pb06,pb07,pb08,pb09,pb10,pb11,pb12,pb13,pb14,pb15,pb16,pb17,pb18,pb19,pb20,pb21,pb22,pb23,pb24,pb25,pb26,pb27,pb28,pb29,pb30,pb31,pc00,pc01,pc02,pc03,pc04,pc05,pc06,pc07,pc08,pc09,pc10,pc11,pc12,pc13,pc14,pc15,pc16,pc17,pc18,pc19,pc20,pc21,pc22,pc23,pc24,pc25,pc26,pc27,pc28,pc29,pc30,pc31,pd00,pd01,pd02,pd03,pd04,pd05,pd06,pd07,pd08,pd09,pd10,pd11,pd12,pd13,pd14,pd15,pd16,pd17,pd18,pd19,pd20,pd21,pd22,pd23,pd24,pd25,pd26,pd27,pd28,pd29,pd30,pd31,pe00,pe01,pe02,pe03,pe04,pe05,pe06,pe07,pe08,pe09,pe10,pe11,pe12,pe13,pe14,pe15,pe16,pe17,pe18,pe19,pe20,pe21,pe22,pe23,pe24,pe25,pe26,pe27,pe28,pe29,pe30,pe31,pf00,pf01,pf02,pf03,pf04,pf05,pf06,pf07,pf08,pf09,pf10,rsv171,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,rsv256,rsv257,rsv258,rsv259,rsv260,rsv261,rsv262,rsv263,rsv264,rsv265,rsv266,rsv267,rsv268,rsv269,rsv270,rsv271,rsv272,rsv273,rsv274,rsv275,rsv276,rsv277,rsv278,rsv279,rsv280,rsv281,rsv282,rsv283,rsv284,rsv285,rsv286,rsv287,rsv288,rsv289,rsv290,rsv291,rsv292,rsv293,rsv294,rsv295,rsv296,rsv297,rsv298,rsv299,rsv300,rsv301,rsv302,rsv303,rsv304,rsv305,rsv306,rsv307,rsv308,rsv309,rsv310,rsv311,rsv312,rsv313,rsv314,rsv315,rsv316,rsv317,rsv318,rsv319,rsv320,rsv321,rsv322,rsv323,rsv324,rsv325,rsv326,rsv327,rsv328,rsv329,rsv330,rsv331,rsv332,rsv333,rsv334,rsv335,rsv336,rsv337,rsv338,rsv339,rsv340,rsv341,rsv342,rsv343,rsv344,rsv345,rsv346,rsv347,rsv348,rsv349,rsv350,rsv351,rsv352,rsv353,rsv354,rsv355,rsv356,rsv357,rsv358,rsv359,rsv360,rsv361,rsv362,rsv363,rsv364,rsv365,rsv366,rsv367,rsv368,rsv369,rsv370,rsv371,rsv372,rsv373,rsv374,rsv375,rsv376,rsv377,rsv378,rsv379,rsv380,rsv381,rsv382,rsv383,rsv384,rsv385,rsv386,rsv387,rsv388,rsv389,rsv390,rsv391,rsv392,rsv393,rsv394,rsv395,rsv396,rsv397,rsv398,rsv399,rsv400,rsv401,rsv402,rsv403,rsv404,rsv405,rsv406,rsv407,rsv408,rsv409,rsv410,rsv411,rsv412,rsv413,rsv414,rsv415,px00,px01,px02,px03,px04,px05,px06,px07,px08,px09,px10,px11,rsv428,rsv429,rsv430,rsv431,rsv432,rsv433,rsv434,rsv435,rsv436,rsv437,rsv438,rsv439,rsv440,rsv441,rsv442,rsv443,rsv444,rsv445,rsv446,rsv447,py00,py01,py02,py03,py04,py05,py06,py07,py08,py09,py10,py11,rsv460,rsv461,rsv462,rsv463,rsv464,rsv465,rsv466,rsv467,rsv468,rsv469,rsv470,rsv471,rsv472,rsv473,rsv474,rsv475,rsv476,rsv477,rsv478,rsv479,pz00,pz01,pz02,pz03,pz04,pz05,pz06,pz07,pz08,pz09,pz10,pz11 + PAD[%s] + no description available + 0x0 + + FUNC_CTL + ALT SELECT + 0x0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_CTL + PAD SETTINGS + 0x4 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only available in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + + + + PIOC + PIOC + IOC + 0xf40d8000 + + + BIOC + BIOC + IOC + 0xf5010000 + + + OTPSHW + OTPSHW + OTP + 0xf4080000 + + 0x0 + 0xc08 + registers + + + + 128 + 0x4 + SHADOW000,SHADOW001,SHADOW002,SHADOW003,SHADOW004,SHADOW005,SHADOW006,SHADOW007,SHADOW008,SHADOW009,SHADOW010,SHADOW011,SHADOW012,SHADOW013,SHADOW014,SHADOW015,SHADOW016,SHADOW017,SHADOW018,SHADOW019,SHADOW020,SHADOW021,SHADOW022,SHADOW023,SHADOW024,SHADOW025,SHADOW026,SHADOW027,SHADOW028,SHADOW029,SHADOW030,SHADOW031,SHADOW032,SHADOW033,SHADOW034,SHADOW035,SHADOW036,SHADOW037,SHADOW038,SHADOW039,SHADOW040,SHADOW041,SHADOW042,SHADOW043,SHADOW044,SHADOW045,SHADOW046,SHADOW047,SHADOW048,SHADOW049,SHADOW050,SHADOW051,SHADOW052,SHADOW053,SHADOW054,SHADOW055,SHADOW056,SHADOW057,SHADOW058,SHADOW059,SHADOW060,SHADOW061,SHADOW062,SHADOW063,SHADOW064,SHADOW065,SHADOW066,SHADOW067,SHADOW068,SHADOW069,SHADOW070,SHADOW071,SHADOW072,SHADOW073,SHADOW074,SHADOW075,SHADOW076,SHADOW077,SHADOW078,SHADOW079,SHADOW080,SHADOW081,SHADOW082,SHADOW083,SHADOW084,SHADOW085,SHADOW086,SHADOW087,SHADOW088,SHADOW089,SHADOW090,SHADOW091,SHADOW092,SHADOW093,SHADOW094,SHADOW095,SHADOW096,SHADOW097,SHADOW098,SHADOW099,SHADOW100,SHADOW101,SHADOW102,SHADOW103,SHADOW104,SHADOW105,SHADOW106,SHADOW107,SHADOW108,SHADOW109,SHADOW110,SHADOW111,SHADOW112,SHADOW113,SHADOW114,SHADOW115,SHADOW116,SHADOW117,SHADOW118,SHADOW119,SHADOW120,SHADOW121,SHADOW122,SHADOW123,SHADOW124,SHADOW125,SHADOW126,SHADOW127 + SHADOW[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + 8 + 0x4 + LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 + SHADOW_LOCK[%s] + no description available + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + 128 + 0x4 + FUSE000,FUSE001,FUSE002,FUSE003,FUSE004,FUSE005,FUSE006,FUSE007,FUSE008,FUSE009,FUSE010,FUSE011,FUSE012,FUSE013,FUSE014,FUSE015,FUSE016,FUSE017,FUSE018,FUSE019,FUSE020,FUSE021,FUSE022,FUSE023,FUSE024,FUSE025,FUSE026,FUSE027,FUSE028,FUSE029,FUSE030,FUSE031,FUSE032,FUSE033,FUSE034,FUSE035,FUSE036,FUSE037,FUSE038,FUSE039,FUSE040,FUSE041,FUSE042,FUSE043,FUSE044,FUSE045,FUSE046,FUSE047,FUSE048,FUSE049,FUSE050,FUSE051,FUSE052,FUSE053,FUSE054,FUSE055,FUSE056,FUSE057,FUSE058,FUSE059,FUSE060,FUSE061,FUSE062,FUSE063,FUSE064,FUSE065,FUSE066,FUSE067,FUSE068,FUSE069,FUSE070,FUSE071,FUSE072,FUSE073,FUSE074,FUSE075,FUSE076,FUSE077,FUSE078,FUSE079,FUSE080,FUSE081,FUSE082,FUSE083,FUSE084,FUSE085,FUSE086,FUSE087,FUSE088,FUSE089,FUSE090,FUSE091,FUSE092,FUSE093,FUSE094,FUSE095,FUSE096,FUSE097,FUSE098,FUSE099,FUSE100,FUSE101,FUSE102,FUSE103,FUSE104,FUSE105,FUSE106,FUSE107,FUSE108,FUSE109,FUSE110,FUSE111,FUSE112,FUSE113,FUSE114,FUSE115,FUSE116,FUSE117,FUSE118,FUSE119,FUSE120,FUSE121,FUSE122,FUSE123,FUSE124,FUSE125,FUSE126,FUSE127 + FUSE[%s] + no description available + 0x400 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + 8 + 0x4 + LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 + FUSE_LOCK[%s] + no description available + 0x600 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + UNLOCK + UNLOCK + 0x800 + 32 + 0x00000000 + 0xFFFFFFFF + + + UNLOCK + unlock word for fuse array operation +write "OPEN" to unlock fuse array, write any other value will lock write to fuse. +Please make sure 24M crystal is running and 2.5V LDO working properly + 0 + 32 + read-write + + + + + DATA + DATA + 0x804 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + data register for non-blocking access +this register hold dat read from fuse array or data to by programmed to fuse array + 0 + 32 + read-write + + + + + ADDR + ADDR + 0x808 + 32 + 0x00000000 + 0x0000007F + + + ADDR + word address to be read or write + 0 + 7 + read-write + + + + + CMD + CMD + 0x80c + 32 + 0x00000000 + 0xFFFFFFFF + + + CMD + command to access fure array +"BLOW" will update fuse word at ADDR to value hold in DATA +"READ" will fetch fuse value in at ADDR to DATA register + 0 + 32 + read-write + + + + + LOAD_REQ + LOAD Request + 0xa00 + 32 + 0x00000007 + 0x0000000F + + + REQUEST + reload request for 4 regions +bit0: region0 +bit1: region1 +bit2: region2 +bit3: region3 + 0 + 4 + read-write + + + + + LOAD_COMP + LOAD complete + 0xa04 + 32 + 0x00000007 + 0x0000000F + + + COMPLETE + reload complete sign for 4 regions +bit0: region 0 +bit1: region1 +bit2: region2 +bit3: region3 + 0 + 4 + read-write + + + + + 4 + 0x4 + LOAD_REGION0,LOAD_REGION1,LOAD_REGION2,LOAD_REGION3 + REGION[%s] + no description available + 0xa20 + 32 + 0x00000800 + 0x00007F7F + + + STOP + stop address of load region, fuse word at end address will NOT be reloaded +region0: fixed at 8 +region1: fixed at 16 +region2: fixed at 0, +region3: usrer configurable + 8 + 7 + read-write + + + START + start address of load region, fuse word at start address will be reloaded +region0: fixed at 0 +region1: fixed at 8 +region2: fixed at 16, +region3: usrer configurable + 0 + 7 + read-write + + + + + INT_FLAG + interrupt flag + 0xc00 + 32 + 0x00000000 + 0x00000007 + + + WRITE + fuse write flag, write 1 to clear +0: fuse is not written or writing +1: value in DATA register is programmed into fuse + 2 + 1 + read-write + + + READ + fuse read flag, write 1 to clear +0: fuse is not read or reading +1: fuse value is put in DATA register + 1 + 1 + read-write + + + LOAD + fuse load flag, write 1 to clear +0: fuse is not loaded or loading +1: fuse loaded + 0 + 1 + read-write + + + + + INT_EN + interrupt enable + 0xc04 + 32 + 0x00000000 + 0x00000007 + + + WRITE + fuse write interrupt enable +0: fuse write interrupt is not enable +1: fuse write interrupt is enable + 2 + 1 + read-write + + + READ + fuse read interrupt enable +0: fuse read interrupt is not enable +1: fuse read interrupt is enable + 1 + 1 + read-write + + + LOAD + fuse load interrupt enable +0: fuse load interrupt is not enable +1: fuse load interrupt is enable + 0 + 1 + read-write + + + + + + + OTP + OTP + OTP + 0xf40c8000 + + + PPOR + PPOR + PPOR + 0xf40c0000 + + 0x0 + 0x20 + registers + + + + RESET_FLAG + flag indicate reset source + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FLAG + reset reason of last hard reset, write 1 to clear each bit +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + write-only + + + + + RESET_STATUS + reset source status + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + current status of reset sources +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + read-write + + + + + RESET_HOLD + reset hold attribute + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + read-write + + + + + RESET_ENABLE + reset source enable + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + enable of reset sources +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + read-write + + + + + RESET_HOT + reset type triggered by reset + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + TYPE + reset type of reset sources, 0 for cold/warm reset, all system control setting cleared including clock, ioc; 1 for hot reset, system control, ioc setting kept, peripheral setting cleared. +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + read-write + + + + + RESET_COLD + reset type attribute + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + FLAG + perform cold or warm reset of chip, 0 for warm reset, fuse value and debug connection preserved; 1 for cold reset, fuse value reloaded and debug connection corrupted. This bit is ignored when hot reset selected +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + read-write + + + + + SOFTWARE_RESET + Software reset counter + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset + 0 + 32 + read-write + + + + + + + PCFG + PCFG + PMU + 0xf40c4000 + + 0x0 + 0x70 + registers + + + + BANDGAP + BANGGAP control + 0x0 + 32 + 0x00101010 + 0x831F1F1F + + + VBG_TRIMMED + Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: bandgap is not trimmed +1: bandgap is trimmed + 31 + 1 + read-write + + + LOWPOWER_MODE + Banggap work in low power mode, banggap function limited +0: banggap works in normal mode +1: banggap works in low power mode + 25 + 1 + read-write + + + POWER_SAVE + Banggap work in power save mode, banggap function normally +0: banggap works in high performance mode +1: banggap works in power saving mode + 24 + 1 + read-write + + + VBG_1P0_TRIM + Banggap 1.0V output trim value + 16 + 5 + read-write + + + VBG_P65_TRIM + Banggap 1.0V output trim value + 8 + 5 + read-write + + + VBG_P50_TRIM + Banggap 1.0V output trim value + 0 + 5 + read-write + + + + + LDO1P1 + 1V LDO config + 0x4 + 32 + 0x0000044C + 0x00000FFF + + + VOLT + LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. +700: 700mV +720: 720mV +. . . +1320:1320mV + 0 + 12 + read-write + + + + + LDO2P5 + 2.5V LDO config + 0x8 + 32 + 0x000009C4 + 0x10010FFF + + + READY + Ready flag, will set 1ms after enabled or voltage change +0: LDO is not ready for use +1: LDO is ready + 28 + 1 + read-only + + + ENABLE + LDO enable +0: turn off LDO +1: turn on LDO + 16 + 1 + read-write + + + VOLT + LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. +2125: 2125mV +2150: 2150mV +. . . +2900:2900mV + 0 + 12 + read-write + + + + + DCDC_MODE + DCDC mode select + 0x10 + 32 + 0x00B010B0 + 0x10070FFF + + + READY + Ready flag +0: DCDC is applying new change +1: DCDC is ready + 28 + 1 + read-only + + + MODE + DCDC work mode +XX0: turn off +001: basic mode +011: generic mode +101: automatic mode +111: expert mode + 16 + 3 + read-write + + + VOLT + DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. +600: 600mV +625: 625mV +. . . +1375:1375mV + 0 + 12 + read-write + + + + + DCDC_LPMODE + DCDC low power mode + 0x14 + 32 + 0x00B010B0 + 0x00000FFF + + + STBY_VOLT + DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. +600: 600mV +625: 625mV +. . . +1375:1375mV + 0 + 12 + read-write + + + + + DCDC_PROT + DCDC protection + 0x18 + 32 + 0x00000000 + 0x11818191 + + + ILIMIT_LP + over current setting for low power mode +0:250mA +1:200mA + 28 + 1 + read-write + + + OVERLOAD_LP + over current in low power mode +0: current is below setting +1: overcurrent happened in low power mode + 24 + 1 + read-only + + + DISABLE_POWER_LOSS + disable power loss protection +0: power loss protection enabled, DCDC shuts down when power loss +1: power loss protection disabled, DCDC try working after power voltage drop + 23 + 1 + read-write + + + POWER_LOSS_FLAG + power loss +0: input power is good +1: input power is too low + 16 + 1 + read-only + + + DISABLE_OVERVOLTAGE + output over voltage protection +0: protection enabled, DCDC will shut down is output voltage is unexpected high +1: protection disabled, DCDC continue to adjust output voltage + 15 + 1 + read-write + + + OVERVOLT_FLAG + output over voltage flag +0: output is normal +1: output is unexpected high + 8 + 1 + read-only + + + DISABLE_SHORT + disable output short circuit protection +0: short circuits protection enabled, DCDC shut down if short circuit on output detected +1: short circuit protection disabled + 7 + 1 + read-write + + + SHORT_CURRENT + short circuit current setting +0: 2.0A, +1: 1.3A + 4 + 1 + read-write + + + SHORT_FLAG + short circuit flag +0: current is within limit +1: short circuits detected + 0 + 1 + read-only + + + + + DCDC_CURRENT + DCDC current estimation + 0x1c + 32 + 0x00000000 + 0x0000811F + + + ESTI_EN + enable current measure + 15 + 1 + read-write + + + VALID + Current level valid +0: data is invalid +1: data is valid + 8 + 1 + read-only + + + LEVEL + DCDC current level, current level is num * 50mA + 0 + 5 + read-only + + + + + DCDC_ADVMODE + DCDC advance setting + 0x20 + 32 + 0x00EF1C6E + 0x073F006F + + + EN_RCSCALE + Enable RC scale + 24 + 3 + read-write + + + DC_C + Loop C number + 20 + 2 + read-write + + + DC_R + Loop R number + 16 + 4 + read-write + + + EN_FF_DET + enable feed forward detect +0: feed forward detect is disabled +1: feed forward detect is enabled + 6 + 1 + read-write + + + EN_FF_LOOP + enable feed forward loop +0: feed forward loop is disabled +1: feed forward loop is enabled + 5 + 1 + read-write + + + EN_DCM_EXIT + avoid over voltage +0: stay in DCM mode when voltage excess +1: change to CCM mode when voltage excess + 3 + 1 + read-write + + + EN_SKIP + enable skip on narrow pulse +0: do not skip narrow pulse +1: skip narrow pulse + 2 + 1 + read-write + + + EN_IDLE + enable skip when voltage is higher than threshold +0: do not skip +1: skip if voltage is excess + 1 + 1 + read-write + + + EN_DCM + DCM mode +0: CCM mode +1: DCM mode + 0 + 1 + read-write + + + + + DCDC_ADVPARAM + DCDC advance parameter + 0x24 + 32 + 0x00EF1C6E + 0x00007F7F + + + MIN_DUT + minimum duty cycle + 8 + 7 + read-write + + + MAX_DUT + maximum duty cycle + 0 + 7 + read-write + + + + + DCDC_MISC + DCDC misc parameter + 0x28 + 32 + 0x00070100 + 0x13170317 + + + EN_HYST + hysteres enable + 28 + 1 + read-write + + + HYST_SIGN + hysteres sign + 25 + 1 + read-write + + + HYST_THRS + hysteres threshold + 24 + 1 + read-write + + + RC_SCALE + Loop RC scale threshold + 20 + 1 + read-write + + + DC_FF + Loop feed forward number + 16 + 3 + read-write + + + OL_THRE + overload for threshold for lod power mode + 8 + 2 + read-write + + + OL_HYST + current hysteres range +0: 12.5mV +1: 25mV + 4 + 1 + read-write + + + DELAY + enable delay +0: delay disabled, +1: delay enabled + 2 + 1 + read-write + + + CLK_SEL + clock selection +0: select DCDC internal oscillator +1: select RC24M oscillator + 1 + 1 + read-write + + + EN_STEP + enable stepping in voltage change +0: stepping disabled, +1: steping enabled + 0 + 1 + read-write + + + + + DCDC_DEBUG + DCDC Debug + 0x2c + 32 + 0x00005DBF + 0x000FFFFF + + + UPDATE_TIME + DCDC voltage change time in 24M clock cycles, default value is 1mS + 0 + 20 + read-write + + + + + DCDC_START_TIME + DCDC ramp time + 0x30 + 32 + 0x0001193F + 0x000FFFFF + + + START_TIME + Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS + 0 + 20 + read-write + + + + + DCDC_RESUME_TIME + DCDC resume time + 0x34 + 32 + 0x00008C9F + 0x000FFFFF + + + RESUME_TIME + Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS + 0 + 20 + read-write + + + + + POWER_TRAP + SOC power trap + 0x40 + 32 + 0x00000000 + 0x80010001 + + + TRIGGERED + Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. +0: low power trap is not triggered +1: low power trap triggered + 31 + 1 + read-write + + + RETENTION + DCDC enter standby mode, which will reduce voltage for memory content retention +0: Shutdown DCDC +1: reduce DCDC voltage + 16 + 1 + read-write + + + TRAP + Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered +0: trap not enabled, pmic side low power function disabled +1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. + 0 + 1 + read-write + + + + + WAKE_CAUSE + Wake up source + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAUSE + wake up cause, each bit represents one wake up source, write 1 to clear the register bit +0: wake up source is not active during last wakeup +1: wake up source is active furing last wakeup +bit 0: pmic_enable +bit 1: debug wakeup +bit 4: fuse interrupt +bit 7: UART interrupt +bit 8: TMR interrupt +bit 9: WDG interrupt +bit10: GPIO in PMIC interrupt +bit11: Security monitor interrupt +bit12: Security in PMIC event +bit16: Security violation in BATT +bit17: GPIO in BATT interrupt +bit18: BATT Button interrupt +bit19: RTC alarm interrupt + 0 + 32 + read-write + + + + + WAKE_MASK + Wake up mask + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + MASK + mask for wake up sources, each bit represents one wakeup source +0: allow source to wake up system +1: disallow source to wakeup system +bit 0: pmic_enable +bit 1: debug wakeup +bit 4: fuse interrupt +bit 7: UART interrupt +bit 8: TMR interrupt +bit 9: WDG interrupt +bit10: GPIO in PMIC interrupt +bit11: Security monitor interrupt +bit12: Security in PMIC event +bit16: Security violation in BATT +bit17: GPIO in BATT interrupt +bit18: BATT Button interrupt +bit19: RTC alarm interrupt + 0 + 32 + read-write + + + + + SCG_CTRL + Clock gate control in PMIC + 0x4c + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + SCG + control whether clock being gated during PMIC low power flow, 2 bits for each peripheral +00,01: reserved +10: clock is always off +11: clock is always on +bit0-1: fuse +bit2-3: sram +bit4-5: vad +bit6-7:gpio +bit8-9:ioc +bit10-11: timer +bit12-13:wdog +bit14-15:uart +bit16-17:debug + 0 + 32 + read-write + + + + + DEBUG_STOP + Debug stop config + 0x50 + 32 + 0x00000001 + 0x00000003 + + + CPU1 + Stop peripheral when CPU1 enter debug mode +0: peripheral keep running when CPU1 in debug mode +1: peripheral enter debug mode when CPU1 enter debug + 1 + 1 + read-write + + + CPU0 + Stop peripheral when CPU0 enter debug mode +0: peripheral keep running when CPU0 in debug mode +1: peripheral enter debug mode when CPU0 enter debug + 0 + 1 + read-write + + + + + RC24M + RC 24M config + 0x60 + 32 + 0x00000316 + 0x8000071F + + + RC_TRIMMED + RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: RC is not trimmed +1: RC is trimmed + 31 + 1 + read-write + + + TRIM_C + Coarse trim for RC24M, bigger value means faster + 8 + 3 + read-write + + + TRIM_F + Fine trim for RC24M, bigger value means faster + 0 + 5 + read-write + + + + + RC24M_TRACK + RC 24M track mode + 0x64 + 32 + 0x00000000 + 0x00010011 + + + SEL24M + Select track reference +0: select 32K as reference +1: select 24M XTAL as reference + 16 + 1 + read-write + + + RETURN + Retrun default value when XTAL loss +0: remain last tracking value +1: switch to default value + 4 + 1 + read-write + + + TRACK + track mode +0: RC24M free running +1: track RC24M to external XTAL + 0 + 1 + read-write + + + + + TRACK_TARGET + RC 24M track target + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRE_DIV + Divider for reference source + 16 + 16 + read-write + + + TARGET + Target frequency multiplier of divided source + 0 + 16 + read-write + + + + + STATUS + RC 24M track status + 0x6c + 32 + 0x00000000 + 0x0011871F + + + SEL32K + track is using XTAL32K +0: track is not using XTAL32K +1: track is using XTAL32K + 20 + 1 + read-only + + + SEL24M + track is using XTAL24M +0: track is not using XTAL24M +1: track is using XTAL24M + 16 + 1 + read-only + + + EN_TRIM + default value takes effect +0: default value is invalid +1: default value is valid + 15 + 1 + read-only + + + TRIM_C + default coarse trim value + 8 + 3 + read-only + + + TRIM_F + default fine trim value + 0 + 5 + read-only + + + + + + + PSEC + PSEC + PSEC + 0xf40cc000 + + 0x0 + 0x18 + registers + + + + SECURE_STATE + Secure state + 0x0 + 32 + 0x00000000 + 0x000300F0 + + + ALLOW_NSC + Non-secure state allow +0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter non-secure state + 17 + 1 + read-only + + + ALLOW_SEC + Secure state allow +0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter secure state + 16 + 1 + read-only + + + PMIC_FAIL + PMIC secure state one hot indicator +0: secure state is not in fail state +1: secure state is in fail state + 7 + 1 + read-write + + + PMIC_NSC + PMIC secure state one hot indicator +0: secure state is not in non-secure state +1: secure state is in non-secure state + 6 + 1 + read-write + + + PMIC_SEC + PMIC secure state one hot indicator +0: secure state is not in secure state +1: secure state is in secure state + 5 + 1 + read-write + + + PMIC_INS + PMIC secure state one hot indicator +0: secure state is not in inspect state +1: secure state is in inspect state + 4 + 1 + read-write + + + + + SECURE_STATE_CONFIG + secure state configuration + 0x4 + 32 + 0x00000000 + 0x00000009 + + + LOCK + Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset +0: not locked, register can be modified +1: register locked, write access to the register is ignored + 3 + 1 + read-write + + + ALLOW_RESTART + allow secure state restart from fail state +0: restart is not allowed, only hardware reset can recover secure state +1: software is allowed to switch to inspect state from fail state + 0 + 1 + read-write + + + + + VIOLATION_CONFIG + Security violation config + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 0 + 15 + read-write + + + + + ESCALATE_CONFIG + Escalate behavior on security event + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 0 + 15 + read-write + + + + + EVENT + Event and escalate status + 0x10 + 32 + 0x00000000 + 0xFFFF000C + + + EVENT + local event statue, each bit represents one security event + 16 + 16 + read-only + + + PMIC_ESC_NSC + PMIC is escalating non-secure event + 3 + 1 + read-only + + + PMIC_ESC_SEC + PMIC is escalting secure event + 2 + 1 + read-only + + + + + LIFECYCLE + Lifecycle + 0x14 + 32 + 0x00000000 + 0x000000FF + + + LIFECYCLE + lifecycle status, +bit7: lifecycle_debate, +bit6: lifecycle_scribe, +bit5: lifecycle_no_ret, +bit4: lifecycle_return, +bit3: lifecycle_secure, +bit2: lifecycle_nonsec, +bit1: lifecycle_create, +bit0: lifecycle_unknow + 0 + 8 + read-only + + + + + + + PMON + PMON + PMON + 0xf40d0000 + + 0x0 + 0x48 + registers + + + + 4 + 0x8 + glitch0,glitch1,clock0,clock1 + MONITOR[%s] + no description available + 0x0 + + CONTROL + Glitch and clock monitor control + 0x0 + 32 + 0x00000000 + 0x00000011 + + + ACTIVE + select glitch works in active mode or passve mode. +0: passive mode, depends on power glitch destroy DFF value +1: active mode, check glitch by DFF chain + 4 + 1 + read-write + + + ENABLE + enable glitch detector +0: detector disabled +1: detector enabled + 0 + 1 + read-write + + + + + STATUS + Glitch and clock monitor status + 0x4 + 32 + 0x00000000 + 0x00000001 + + + FLAG + flag for glitch detected, write 1 to clear this flag +0: glitch not detected +1: glitch detected + 0 + 1 + read-write + + + + + + IRQ_FLAG + No description available + 0x40 + 32 + 0x00000000 + 0x0000000F + + + FLAG + interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag +0: no monitor interrupt +1: monitor interrupt happened + 0 + 4 + read-write + + + + + IRQ_ENABLE + No description available + 0x44 + 32 + 0x00000000 + 0x0000000F + + + ENABLE + interrupt enable, each bit represents for one monitor +0: monitor interrupt disabled +1: monitor interrupt enabled + 0 + 4 + read-write + + + + + + + PGPR + PGPR + PGPR + 0xf40d4000 + + 0x0 + 0x40 + registers + + + + PMIC_GPR00 + Generic control + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR01 + Generic control + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR02 + Generic control + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR03 + Generic control + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR04 + Generic control + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR05 + Generic control + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR06 + Generic control + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR07 + Generic control + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR08 + Generic control + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR09 + Generic control + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR10 + Generic control + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR11 + Generic control + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR12 + Generic control + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR13 + Generic control + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR14 + Generic control + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR15 + Generic control + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + + + VAD + VAD + VAD + 0xf40ec000 + + 0x0 + 0xa4 + registers + + + + CTRL + Control Register + 0x0 + 32 + 0x00000000 + 0x0FF7FBFF + + + CAPT_DLY + Capture cycle delay>=0, should be less than PDM_CLK_HFDIV + 24 + 4 + read-write + + + PDM_CLK_HFDIV + The clock divider will work at least 4. +0: div-by-2, +1: div-by-4 +. . . +n: div-by-2*(n+1) + 20 + 4 + read-write + + + VAD_IE + VAD event interrupt enable + 18 + 1 + read-write + + + OFIFO_AV_IE + OFIFO data available interrupt enable + 17 + 1 + read-write + + + MEMBUF_EMPTY_IE + Buf empty interrupt enable + 16 + 1 + read-write + + + OFIFO_OVFL_ERR_IE + OFIFO overflow error interrupt enable + 15 + 1 + read-write + + + IIR_OVLD_ERR_IE + IIR overload error interrupt enable + 14 + 1 + read-write + + + IIR_OVFL_ERR_IE + IIR overflow error interrupt enable + 13 + 1 + read-write + + + CIC_OVLD_ERR_IE + CIC overload Interrupt Enable + 12 + 1 + read-write + + + CIC_SAT_ERR_IE + CIC saturation Interrupt Enable + 11 + 1 + read-write + + + MEMBUF_DISABLE + asserted to disable membuf + 9 + 1 + read-write + + + FIFO_THRSH + OFIFO threshold to generate ofifo_av (when fillings >= threshold) (fifo size: max 16 items, 16*32bits) + 5 + 4 + read-write + + + PDM_CLK_DIV_BYPASS + asserted to bypass the pdm clock divider + 4 + 1 + read-write + + + PDM_CLK_OE + pdm_clk_output_en + 3 + 1 + read-write + + + CH_POL + Asserted to select PDM_CLK high level captured, otherwise to select PDM_CLK low level captured. + 1 + 2 + read-write + + + CHNUM + the number of channels to be stored in buffer. Asserted to enable 2 channels. + 0 + 1 + read-write + + + + + FILTCTRL + Filter Control Register + 0x4 + 32 + 0x00000000 + 0x000007FF + + + DECRATIO + the decimation ratio of iir after CIC -1 +2: means dec-by-3 + 8 + 3 + read-write + + + IIR_SLOT_EN + IIR slot enable + 0 + 8 + read-write + + + + + DEC_CTRL0 + Decision Control Register 0 + 0x8 + 32 + 0x00000000 + 0xFFFF03FF + + + NOISE_TOL + the value of amplitude for noise determination when calculationg ZCR + 16 + 16 + read-write + + + BLK_CFG + asserted to have 3 sub-blocks, otherwise to have 2 sub-blocks + 9 + 1 + read-write + + + SUBBLK_LEN + length of sub-block + 0 + 9 + read-write + + + + + DEC_CTRL1 + Decision Control Register 1 + 0xc + 32 + 0x00000000 + 0x003FFFFF + + + ZCR_HIGH + ZCR high limit + 11 + 11 + read-write + + + ZCR_LOW + ZCR low limit + 0 + 11 + read-write + + + + + DEC_CTRL2 + Decision Control Register 2 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + AMP_HIGH + amplitude high limit + 16 + 16 + read-write + + + AMP_LOW + amplitude low limit + 0 + 16 + read-write + + + + + ST + Status + 0x18 + 32 + 0x00000000 + 0x000000FF + + + VAD + VAD event found + 7 + 1 + write-only + + + OFIFO_AV + OFIFO data available + 6 + 1 + read-only + + + MEMBUF_EMPTY + Buf empty + 5 + 1 + write-only + + + OFIFO_OVFL + OFIFO overflow + 4 + 1 + write-only + + + IIR_OVLD + IIR overloading + 3 + 1 + write-only + + + IIR_OVFL + IIR oberflow + 2 + 1 + write-only + + + CIC_OVLD_ERR + CIC overload + 1 + 1 + write-only + + + CIC_SAT_ERR + CIC saturation + 0 + 1 + write-only + + + + + OFIFO + Out FIFO + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + D + The PCM data. +When there is only one channel, the samples are from Ch0, and the 2 samples in the 32-bits are: bit [31:16]: the samples earlier in time ([T-1]). Bit [15:0]: the samples later in time ([T]). +When there is two channels, the samples in the 32-bits are: bit [31:16]: the samples belong to Ch 1 (when ch_pol[1:0]==2, the data is captured at the positive part of the pdm clk). bit [15:0]: the samples belong to Ch 0 (when ch_pol[1:0]==2, the data is captured at the negtive part of the pdm clk). + 0 + 32 + read-write + + + + + RUN + Run Command Register + 0x20 + 32 + 0x00000000 + 0x00000003 + + + SFTRST + software reset. Self-clear + 1 + 1 + read-write + + + VAD_EN + module enable + 0 + 1 + read-write + + + + + OFIFO_CTRL + Out FIFO Control Register + 0x24 + 32 + 0x00000000 + 0x00000001 + + + EN + Asserted to enable OFIFO + 0 + 1 + read-write + + + + + CIC_CFG + CIC Configuration Register + 0x28 + 32 + 0x00000000 + 0x0000FC00 + + + POST_SCALE + the shift value after CIC results. + 10 + 6 + read-write + + + + + 1 + 0x4 + STE_ACT + COEF[%s] + no description available + 0xa0 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + The current detected short time energy + 0 + 32 + read-only + + + + + + + PLLCTL + PLLCTL + PLLCTL + 0xf4100000 + + 0x0 + 0x300 + registers + + + + XTAL + Crystal control and status + 0x0 + 32 + 0x00000000 + 0x300FFFFF + + + RESPONSE + Crystal oscillator status +0: Oscillator is not stable +1: Oscillator is stable for use + 29 + 1 + read-only + + + ENABLE + Crystal oscillator enable status +0: Oscillator is off +1: Oscillator is on + 28 + 1 + read-only + + + RAMP_TIME + Rampup time of XTAL oscillator in cycles of IRC24M clock +0: 0 cycle +1: 1 cycle +2: 2 cycle +1048575: 1048575 cycles + 0 + 20 + read-write + + + + + 5 + 0x80 + pll0,pll1,pll2,pll3,pll4 + PLL[%s] + no description available + 0x80 + + CFG0 + PLLx config0 + 0x0 + 32 + 0x00140460 + 0xBF77FFE8 + + + SS_RSTPTR + reset pointer, for sscg, lock when lock_en[31]&~pll_ana_pd&~pll_lock_comb + 31 + 1 + read-write + + + REFDIV + refclk diverder, lock when lock_en[24]&~pll_ana_pd + 24 + 6 + read-write + + + POSTDIV1 + lock when lock_en[20]&~pll_ana_pd + 20 + 3 + read-write + + + SS_SPREAD + lock when lock_en[14]&~pll_ana_pd + 14 + 5 + read-write + + + SS_DIVVAL + sscg divval, lock when lock_en[8]&~pll_ana_pd + 8 + 6 + read-write + + + SS_DOWNSPREAD + Downspread control +1’b0 –> Center-Spread +1’b1 –> Downspread + 7 + 1 + read-write + + + SS_RESET + No description available + 6 + 1 + read-write + + + SS_DISABLE_SSCG + No description available + 5 + 1 + read-write + + + DSMPD + 1: int mode; 0: frac mode + 3 + 1 + read-write + + + + + CFG1 + PLLx config1 + 0x4 + 32 + 0x80000000 + 0x86008000 + + + PLLCTRL_HW_EN + 1: hardware controll PLL settings, software can update register, but result unknown; suggested only update fbdiv and frac value +0: full software control PLL settings + 31 + 1 + read-write + + + CLKEN_SW + the clock enable used to gate pll output, should be set after lock, and clear before power down pll. +pll_clock_enable = pllctrl_hw_en ? (pll_lock_comb & enable & pll_clk_enable_chg) : clken_sw; + 26 + 1 + read-write + + + PLLPD_SW + pll power down. +pll_ana_pd = pllctrl_hw_en ? (pll_pd_soc|pll_pd_chg) : pllpd_sw; +pll_pd_soc is just delay of soc enable, for soc to control pll on/off; +pll_pd_chg is used to power down pll when div_chg_mode is 1, if software update pll parameter(fbdiv or frac), pll_ctrl will power down pll, update parameter, then power up pll. response to soc will not de-asserted at this sequence + 25 + 1 + read-write + + + LOCK_CNT_CFG + used to wait lock if set larger than lock time; +default 1500 24M cycle if refdiv is 1, 4500 cycle if refdiv is 3 + 15 + 1 + read-write + + + + + CFG2 + PLLx config2 + 0x8 + 32 + 0x00000000 + 0x00000FFF + + + FBDIV_INT + fbdiv used in int mode + 0 + 12 + read-write + + + + + FREQ + PLLx frac mode frequency adjust + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + FRAC + PLL output frequency is : +Fout = Fref/refdiv*(fbdiv + frac/2^24)/postdiv1 +for default refdiv=1 and postdiv1=1, 24MHz refclk +Fout is 24*fbdiv in int mode +if frac is set to 0x800000, Fout is 24*(fbdiv+0.5) +Fout is 24*fbdiv in int mode +if frac is set to 0x200000, Fout is 24*(fbdiv+0.125) + 8 + 24 + read-write + + + FBDIV_FRAC + fbdiv used in frac mode + 0 + 8 + read-write + + + + + LOCK + PLLx lock control + 0x10 + 32 + 0x00000000 + 0x81104100 + + + LOCK_SS_RSTPTR + lock bit of field ss_rstptr +0: field is open foe software to change +1: field is locked, not changeable + 31 + 1 + read-write + + + LOCK_REFDIV + lock bit of field refdiv +0: field is open foe software to change +1: field is locked, not changeable + 24 + 1 + read-write + + + LOCK_POSTDIV1 + lock bit of field postdiv1 +0: field is open foe software to change +1: field is locked, not changeable + 20 + 1 + read-write + + + LOCK_SS_SPEAD + lock bit of field ss_spead +0: field is open foe software to change +1: field is locked, not changeable + 14 + 1 + read-write + + + LOCK_SS_DIVVAL + lock bit of field ss_divval +0: field is open foe software to change +1: field is locked, not changeable + 8 + 1 + read-write + + + + + STATUS + PLLx status + 0x20 + 32 + 0x00000000 + 0x08000007 + + + ENABLE + enable from SYSCTL block + 27 + 1 + read-only + + + RESPONSE + response to SYSCTL, PLL is power down when both enable and response are 0. + 2 + 1 + read-only + + + PLL_LOCK_COMB + No description available + 1 + 1 + read-only + + + PLL_LOCK_SYNC + No description available + 0 + 1 + read-only + + + + + DIV0 + PLLx divider0 control + 0x40 + 32 + 0x00000000 + 0xB00000FF + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Crystal oscillator status +0: Oscillator is not stable +1: Oscillator is stable for use + 29 + 1 + read-only + + + ENABLE + Crystal oscillator enable status +0: Oscillator is off +1: Oscillator is on + 28 + 1 + read-only + + + DIV + Divider +0: divide by 1 +1: divide by2 +. . . +255: divide by 256 + 0 + 8 + read-write + + + + + DIV1 + PLLx divider1 control + 0x44 + 32 + 0x00000000 + 0xB00000FF + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Crystal oscillator status +0: Oscillator is not stable +1: Oscillator is stable for use + 29 + 1 + read-only + + + ENABLE + Crystal oscillator enable status +0: Oscillator is off +1: Oscillator is on + 28 + 1 + read-only + + + DIV + Divider +0: divide by 1 +1: divide by2 +. . . +255: divide by 256 + 0 + 8 + read-write + + + + + + + + BPOR + BPOR + BPOR + 0xf5004000 + + 0x0 + 0x10 + registers + + + + POR_CAUSE + Power on cause + 0x0 + 32 + 0x00000000 + 0x0000001F + + + CAUSE + Power on cause, each bit represnts one cause, write 1 to clear each bit +bit0: wakeup button +bit1: security violation +bit2: RTC alarm 0 +bit3: RTC alarm 1 +bit4: GPIO + 0 + 5 + read-write + + + + + POR_SELECT + Power on select + 0x4 + 32 + 0x00000000 + 0x0000001F + + + SELECT + Power on cause select, each bit represnts one cause, value 1 enables corresponding cause +bit0: wakeup button +bit1: security violation +bit2: RTC alarm 0 +bit3: RTC alarm 1 +bit4: GPIO + 0 + 5 + read-write + + + + + POR_CONFIG + Power on reset config + 0x8 + 32 + 0x00000000 + 0x00000001 + + + RETENTION + retention battery domain setting +0: battery reset on reset pin reset happen +1: battery domain retention when reset pin reset happen + 0 + 1 + read-write + + + + + POR_CONTROL + Power down control + 0xc + 32 + 0x00000000 + 0x0000FFFF + + + COUNTER + Chip power down counter, counter decreasing if value is not 0, power down of chip happens on counter value is 1 + 0 + 16 + read-write + + + + + + + BCFG + BCFG + TRIM + 0xf5008000 + + 0x0 + 0x14 + registers + + + + VBG_CFG + Bandgap config + 0x0 + 32 + 0x00000000 + 0x831F1F1F + + + VBG_TRIMMED + Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: bandgap is not trimmed +1: bandgap is trimmed + 31 + 1 + read-write + + + LP_MODE + Bandgap works in low power mode +0: not in low power mode +1: bandgap work in low power mode + 25 + 1 + read-write + + + POWER_SAVE + Bandgap works in power save mode +0: not in power save mode +1: bandgap work in power save mode + 24 + 1 + read-write + + + VBG_1P0 + Bandgap 1.0V output trim + 16 + 5 + read-write + + + VBG_P65 + Bandgap 0.65V output trim + 8 + 5 + read-write + + + VBG_P50 + Bandgap 0.50V output trim + 0 + 5 + read-write + + + + + LDO_CFG + LDO config + 0x4 + 32 + 0x00010000 + 0x03370FFF + + + RES_TRIM + Resistor trim + 24 + 2 + read-write + + + CP_TRIM + Capacitor trim + 20 + 2 + read-write + + + EN_SL + enable selfload, this bit helps improve LDO performance when current less than 200nA +0: self load disabled +1: selfload enabled + 18 + 1 + read-write + + + DIS_PD + disable pull down resistor, enable pull down may lead to more power but better response +0: pulldown resistor enabled +1: pulldown resistor disabled + 17 + 1 + read-write + + + ENABLE + LDO enable +0: LDO is disabled +1: LDO is enabled + 16 + 1 + read-write + + + VOLT + LDO voltage setting in mV, valid range through 600mV to 1100mV, step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1100mV. +600: 600mV +620: 620mV +. . . +1100:1100mV + 0 + 12 + read-write + + + + + IRC32K_CFG + On-chip 32k oscillator config + 0x8 + 32 + 0x00000000 + 0x80C001FF + + + IRC_TRIMMED + IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: irc is not trimmed +1: irc is trimmed + 31 + 1 + read-write + + + CAPEX7_TRIM + IRC32K bit 7 + 23 + 1 + read-write + + + CAPEX6_TRIM + IRC32K bit 6 + 22 + 1 + read-write + + + CAP_TRIM + capacitor trim bits + 0 + 9 + read-write + + + + + XTAL32K_CFG + XTAL 32K config + 0xc + 32 + 0x00000000 + 0x00001313 + + + HYST_EN + crystal 32k hysteres enable + 12 + 1 + read-write + + + GMSEL + crystal 32k gm selection + 8 + 2 + read-write + + + CFG + crystal 32k config + 4 + 1 + read-write + + + AMP + crystal 32k amplifier + 0 + 2 + read-write + + + + + CLK_CFG + Clock config + 0x10 + 32 + 0x00000000 + 0x10010010 + + + XTAL_SEL + crystal selected + 28 + 1 + read-only + + + KEEP_IRC + force irc32k run + 16 + 1 + read-write + + + FORCE_XTAL + force switch to crystal + 4 + 1 + read-write + + + + + + + BUTN + BUTN + BUTN + 0xf500c000 + + 0x0 + 0xc + registers + + + + BTN_STATUS + Button status + 0x0 + 32 + 0x00000000 + 0x77770FFF + + + XWCLICK + wake button click status when power button held, write 1 to clear flag +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 28 + 3 + read-write + + + WCLICK + wake button click status, write 1 to clear flag +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 24 + 3 + read-write + + + XPCLICK + power button click status when wake button held, write 1 to clear flag +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 20 + 3 + read-write + + + PCLICK + power button click status, write 1 to clear flag +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 16 + 3 + read-write + + + DBTN + Dual button press status, write 1 to clear flag +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 8 + 4 + read-write + + + WBTN + Wake button press status, write 1 to clear flag +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 4 + 4 + read-write + + + PBTN + Power button press status, write 1 to clear flag +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 0 + 4 + read-write + + + + + BTN_IRQ_MASK + Button interrupt mask + 0x4 + 32 + 0x00000000 + 0x77770FFF + + + XWCLICK + wake button click status when power button held interrupt enable +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 28 + 3 + read-write + + + WCLICK + wake button click interrupt enable +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 24 + 3 + read-write + + + XPCLICK + power button click status when wake button held interrupt enable +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 20 + 3 + read-write + + + PCLICK + power button click interrupt enable +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 16 + 3 + read-write + + + DBTN + Dual button press interrupt enable +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 8 + 4 + read-write + + + WBTN + Wake button press interrupt enable +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 4 + 4 + read-write + + + PBTN + Power button press interrupt enable +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 0 + 4 + read-write + + + + + LED_INTENSE + Debounce setting + 0x8 + 32 + 0x00000000 + 0x000F000F + + + RLED + Rbutton brightness 0 + 16 + 4 + read-write + + + PLED + Pbutton brightness 0 + 0 + 4 + read-write + + + + + + + BGPR + BGPR + BGPR + 0xf5018000 + + 0x0 + 0x20 + registers + + + + 8 + 0x4 + 0,1,2,3,4,5,6,7 + GPR[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + Generic control + 0 + 32 + read-write + + + + + + + RTCSHW + RTCSHW + RTC + 0xf501c000 + + 0x0 + 0x28 + registers + + + + SECOND + Second counter + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SECOND + second counter + 0 + 32 + read-write + + + + + SUBSEC + Sub-second counter + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SUBSEC + sub second counter + 0 + 32 + read-only + + + + + SEC_SNAP + Second counter snap shot + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SEC_SNAP + second snap shot, write to take snap shot + 0 + 32 + read-write + + + + + SUB_SNAP + Sub-second counter snap shot + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + SUB_SNAP + sub second snap shot, write to take snap shot + 0 + 32 + read-write + + + + + ALARM0 + RTC alarm0 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + ALARM + Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC + 0 + 32 + read-write + + + + + ALARM0_INC + Alarm0 incremental + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + INCREASE + adder when ARLAM0 happen, helps to create periodical alarm + 0 + 32 + read-write + + + + + ALARM1 + RTC alarm1 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + ALARM + Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC + 0 + 32 + read-write + + + + + ALARM1_INC + Alarm1 incremental + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + INCREASE + adder when ARLAM0 happen, helps to create periodical alarm + 0 + 32 + read-write + + + + + ALARM_FLAG + RTC alarm flag + 0x20 + 32 + 0x00000000 + 0x00000003 + + + ALARM1 + alarm1 happen + 1 + 1 + read-write + + + ALARM0 + alarm0 happen + 0 + 1 + read-write + + + + + ALARM_EN + RTC alarm enable + 0x24 + 32 + 0x00000000 + 0x00000003 + + + ENABLE1 + alarm1 mask +0: alarm1 disabled +1: alarm1 enabled + 1 + 1 + read-write + + + ENABLE0 + alarm0 mask +0: alarm0 disabled +1: alarm0 enabled + 0 + 1 + read-write + + + + + + + RTC + RTC + RTC + 0xf5044000 + + + BSEC + BSEC + BSEC + 0xf5040000 + + 0x0 + 0x14 + registers + + + + SECURE_STATE + Secure state + 0x0 + 32 + 0x00000000 + 0x0003000F + + + ALLOW_NSC + Non-secure state allow +0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter non-secure state + 17 + 1 + read-only + + + ALLOW_SEC + Secure state allow +0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter secure state + 16 + 1 + read-only + + + BATT_FAIL + BATT secure state one hot indicator +0: secure state is not in fail state +1: secure state is in fail state + 3 + 1 + read-write + + + BATT_NSC + BATT secure state one hot indicator +0: secure state is not in non-secure state +1: secure state is in non-secure state + 2 + 1 + read-write + + + BATT_SEC + BATT secure state one hot indicator +0: secure state is not in secure state +1: secure state is in secure state + 1 + 1 + read-write + + + BATT_INS + BATT secure state one hot indicator +0: secure state is not in inspect state +1: secure state is in inspect state + 0 + 1 + read-write + + + + + SECURE_STATE_CONFIG + secure state configuration + 0x4 + 32 + 0x00000000 + 0x00000009 + + + LOCK + Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset +0: not locked, register can be modified +1: register locked, write access to the register is ignored + 3 + 1 + read-write + + + ALLOW_RESTART + allow secure state restart from fail state +0: restart is not allowed, only hardware reset can recover secure state +1: software is allowed to switch to inspect state from fail state + 0 + 1 + read-write + + + + + VIOLATION_CONFIG + Security violation config + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 0 + 15 + read-write + + + + + ESCALATE_CONFIG + Escalate behavior on security event + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 0 + 15 + read-write + + + + + EVENT + Event and escalate status + 0x10 + 32 + 0x00000000 + 0xFFFF0003 + + + EVENT + local event statue, each bit represents one security event + 16 + 16 + read-only + + + BATT_ESC_NSC + BATT is escalating non-secure event + 1 + 1 + read-only + + + BATT_ESC_SEC + BATT is escalting ssecure event + 0 + 1 + read-only + + + + + + + BKEY + BKEY + BKEY + 0xf5048000 + + 0x0 + 0x4c + registers + + + + 2 + 0x20 + 0,1 + KEY[%s] + no description available + 0x0 + + 8 + 0x4 + 0,1,2,3,4,5,6,7 + DATA[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + + 2 + 0x4 + KEY0,KEY1 + ECC[%s] + no description available + 0x40 + 32 + 0x00000000 + 0xC000FFFF + + + WLOCK + write lock to key0 +0: write enable +1: write ignored + 31 + 1 + read-write + + + RLOCK + read lock to key0 +0: key read enable +1: key always read as 0 + 30 + 1 + read-write + + + ECC + Parity check bits for key0 + 0 + 16 + read-write + + + + + SELECT + Key selection + 0x48 + 32 + 0x00000000 + 0x00000001 + + + SELECT + select key, key0 treated as secure key, in non-scure mode, only key1 can be selected +0: select key0 in secure mode, key1 in non-secure mode +1: select key1 in secure or nonsecure mode + 0 + 1 + read-write + + + + + + + BMON + BMON + BMON + 0xf504c000 + + 0x0 + 0x20 + registers + + + + 2 + 0x10 + glitch0,clock0 + MONITOR[%s] + no description available + 0x0 + + CONTROL + Glitch and clock monitor control + 0x0 + 32 + 0x00000000 + 0x00000011 + + + ACTIVE + select glitch works in active mode or passve mode. +0: passive mode, depends on power glitch destroy DFF value +1: active mode, check glitch by DFF chain + 4 + 1 + read-write + + + ENABLE + enable glitch detector +0: detector disabled +1: detector enabled + 0 + 1 + read-write + + + + + STATUS + Glitch and clock monitor status + 0x4 + 32 + 0x00000000 + 0x00000001 + + + FLAG + flag for glitch detected, write 1 to clear this flag +0: glitch not detected +1: glitch detected + 0 + 1 + read-write + + + + + + + + TAMP + TAMP + TAMP + 0xf5050000 + + 0x0 + 0x88 + registers + + + + 6 + 0x10 + tamp0,tamp1,tamp2,tamp3,tamp4,tamp5 + TAMP[%s] + no description available + 0x0 + + CONTROL + Tamper n control + 0x0 + 32 + 0x00000000 + 0x801F03F7 + + + LOCK + lock tamper setting +0: tamper setting can be changed +1: tamper setting will last to next battery domain power cycle + 31 + 1 + read-write + + + BYPASS + bypass tamper violation filter +0: filter applied +1: filter not used + 20 + 1 + read-write + + + FILTER + filter length +0: 1 cycle +1: 2 cycle +15: 65526 cycle + 16 + 4 + read-write + + + VALUE + pin value for passive tamper + 8 + 2 + read-write + + + SPEED + tamper speed selection, (2^SPEED) changes per second +0: 1 shift per second +1: 2 shifts per second +. . . +15: 32768 shifts per second + 4 + 4 + read-write + + + RECOVER + tamper will recover itself if tamper LFSR goes wrong +0: tamper will not recover +1: tamper will recover + 2 + 1 + read-write + + + ACTIVE + select active or passive tamper +0: passive tamper +1: active tamper + 1 + 1 + read-write + + + ENABLE + enable tamper +0: tamper disableed +1: tamper enabled + 0 + 1 + read-write + + + + + POLY + Tamper n Polynomial of LFSR + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + POLY + tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" + 0 + 32 + read-write + + + + + LFSR + Tamper n LFSR shift register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + LFSR + LFSR for active tamper, write only register, always read 0 + 0 + 32 + write-only + + + + + + TAMP_FLAG + Tamper flag + 0x80 + 32 + 0x00000000 + 0x00000FFF + + + FLAG + tamper flag, each bit represents one tamper pin, write 1 to clear the flag +Note, clear can only be cleared when tamper disappeared + 0 + 12 + read-write + + + + + IRQ_EN + Tamper interrupt enable + 0x84 + 32 + 0x00000000 + 0x80000FFF + + + LOCK + lock bit for IRQ enable +0: enable bits can be changed +1: enable bits hold until next battery domain power cycle + 31 + 1 + read-write + + + IRQ_EN + interrupt enable, each bit represents one tamper pin +0: interrupt disabled +1: interrupt enabled + 0 + 12 + read-write + + + + + + + MONO + MONO + MONO + 0xf5054000 + + 0x0 + 0x8 + registers + + + + MONOL + Low part of monotonic counter + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + low part of monotonica counter, write to this counter will cause counter increase by 1 + 0 + 32 + read-write + + + + + MONOH + High part of monotonic counter + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + EPOCH + Fuse value for high part of monotonica + 16 + 16 + read-write + + + COUNTER + high part of monotonica counter, write to this counter will cause counter increase by 1 if low part overflow + 0 + 16 + read-write + + + + + + + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_batt_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_batt_iomux.h index 1d3c6eb0c40..57e881864da 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_batt_iomux.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_batt_iomux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -9,73 +9,117 @@ #ifndef HPM_BATT_IOMUX_H #define HPM_BATT_IOMUX_H -/* IOC_PZ00_FUNC_CTL function mux definitions */ -#define IOC_PZ00_FUNC_CTL_BGPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ00_FUNC_CTL_PWR_ON IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ00_FUNC_CTL_TAMP_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ00_FUNC_CTL_SOC_PZ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PZ01_FUNC_CTL function mux definitions */ -#define IOC_PZ01_FUNC_CTL_BGPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ01_FUNC_CTL_RESETN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ01_FUNC_CTL_TAMP_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ01_FUNC_CTL_SOC_PZ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PZ02_FUNC_CTL function mux definitions */ -#define IOC_PZ02_FUNC_CTL_BGPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ02_FUNC_CTL_PBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ02_FUNC_CTL_TAMP_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ02_FUNC_CTL_SOC_PZ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PZ03_FUNC_CTL function mux definitions */ -#define IOC_PZ03_FUNC_CTL_BGPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ03_FUNC_CTL_WBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ03_FUNC_CTL_TAMP_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ03_FUNC_CTL_SOC_PZ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PZ04_FUNC_CTL function mux definitions */ -#define IOC_PZ04_FUNC_CTL_BGPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ04_FUNC_CTL_PLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ04_FUNC_CTL_TAMP_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ04_FUNC_CTL_SOC_PZ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PZ05_FUNC_CTL function mux definitions */ -#define IOC_PZ05_FUNC_CTL_BGPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ05_FUNC_CTL_WLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ05_FUNC_CTL_TAMP_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ05_FUNC_CTL_SOC_PZ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PZ06_FUNC_CTL function mux definitions */ -#define IOC_PZ06_FUNC_CTL_BGPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ06_FUNC_CTL_TAMP_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ06_FUNC_CTL_SOC_PZ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PZ07_FUNC_CTL function mux definitions */ -#define IOC_PZ07_FUNC_CTL_BGPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ07_FUNC_CTL_TAMP_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ07_FUNC_CTL_SOC_PZ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PZ08_FUNC_CTL function mux definitions */ -#define IOC_PZ08_FUNC_CTL_BGPIO_Z_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ08_FUNC_CTL_TAMP_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ08_FUNC_CTL_SOC_PZ_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PZ09_FUNC_CTL function mux definitions */ -#define IOC_PZ09_FUNC_CTL_BGPIO_Z_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ09_FUNC_CTL_TAMP_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ09_FUNC_CTL_SOC_PZ_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PZ10_FUNC_CTL function mux definitions */ -#define IOC_PZ10_FUNC_CTL_BGPIO_Z_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ10_FUNC_CTL_HIBERNATE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ10_FUNC_CTL_TAMP_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ10_FUNC_CTL_SOC_PZ_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PZ11_FUNC_CTL function mux definitions */ -#define IOC_PZ11_FUNC_CTL_BGPIO_Z_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ11_FUNC_CTL_STANDBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ11_FUNC_CTL_TAMP_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ11_FUNC_CTL_SOC_PZ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +/* BIOC_PZ00_FUNC_CTL function mux definitions */ +#define IOC_PZ00_FUNC_CTL_BGPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ00_FUNC_CTL_BGPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ00_FUNC_CTL_PWR_ON IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ00_FUNC_CTL_PWR_ON IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ00_FUNC_CTL_TAMP_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ00_FUNC_CTL_TAMP_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ00_FUNC_CTL_SOC_PZ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ00_FUNC_CTL_SOC_PZ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ01_FUNC_CTL function mux definitions */ +#define IOC_PZ01_FUNC_CTL_BGPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ01_FUNC_CTL_BGPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ01_FUNC_CTL_RESETN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ01_FUNC_CTL_RESETN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ01_FUNC_CTL_TAMP_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ01_FUNC_CTL_TAMP_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ01_FUNC_CTL_SOC_PZ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ01_FUNC_CTL_SOC_PZ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ02_FUNC_CTL function mux definitions */ +#define IOC_PZ02_FUNC_CTL_BGPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ02_FUNC_CTL_BGPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ02_FUNC_CTL_PBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ02_FUNC_CTL_PBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ02_FUNC_CTL_TAMP_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ02_FUNC_CTL_TAMP_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ02_FUNC_CTL_SOC_PZ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ02_FUNC_CTL_SOC_PZ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ03_FUNC_CTL function mux definitions */ +#define IOC_PZ03_FUNC_CTL_BGPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ03_FUNC_CTL_BGPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ03_FUNC_CTL_WBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ03_FUNC_CTL_WBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ03_FUNC_CTL_TAMP_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ03_FUNC_CTL_TAMP_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ03_FUNC_CTL_SOC_PZ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ03_FUNC_CTL_SOC_PZ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ04_FUNC_CTL function mux definitions */ +#define IOC_PZ04_FUNC_CTL_BGPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ04_FUNC_CTL_BGPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ04_FUNC_CTL_PLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ04_FUNC_CTL_PLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ04_FUNC_CTL_TAMP_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ04_FUNC_CTL_TAMP_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ04_FUNC_CTL_SOC_PZ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ04_FUNC_CTL_SOC_PZ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ05_FUNC_CTL function mux definitions */ +#define IOC_PZ05_FUNC_CTL_BGPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ05_FUNC_CTL_BGPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ05_FUNC_CTL_WLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ05_FUNC_CTL_WLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ05_FUNC_CTL_TAMP_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ05_FUNC_CTL_TAMP_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ05_FUNC_CTL_SOC_PZ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ05_FUNC_CTL_SOC_PZ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ06_FUNC_CTL function mux definitions */ +#define IOC_PZ06_FUNC_CTL_BGPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ06_FUNC_CTL_BGPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ06_FUNC_CTL_TAMP_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ06_FUNC_CTL_TAMP_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ06_FUNC_CTL_SOC_PZ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ06_FUNC_CTL_SOC_PZ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ07_FUNC_CTL function mux definitions */ +#define IOC_PZ07_FUNC_CTL_BGPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ07_FUNC_CTL_BGPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ07_FUNC_CTL_TAMP_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ07_FUNC_CTL_TAMP_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ07_FUNC_CTL_SOC_PZ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ07_FUNC_CTL_SOC_PZ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ08_FUNC_CTL function mux definitions */ +#define IOC_PZ08_FUNC_CTL_BGPIO_Z_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ08_FUNC_CTL_BGPIO_Z_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ08_FUNC_CTL_TAMP_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ08_FUNC_CTL_TAMP_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ08_FUNC_CTL_SOC_PZ_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ08_FUNC_CTL_SOC_PZ_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ09_FUNC_CTL function mux definitions */ +#define IOC_PZ09_FUNC_CTL_BGPIO_Z_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ09_FUNC_CTL_BGPIO_Z_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ09_FUNC_CTL_TAMP_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ09_FUNC_CTL_TAMP_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ09_FUNC_CTL_SOC_PZ_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ09_FUNC_CTL_SOC_PZ_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ10_FUNC_CTL function mux definitions */ +#define IOC_PZ10_FUNC_CTL_BGPIO_Z_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ10_FUNC_CTL_BGPIO_Z_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ10_FUNC_CTL_HIBERNATE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ10_FUNC_CTL_HIBERNATE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ10_FUNC_CTL_TAMP_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ10_FUNC_CTL_TAMP_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ10_FUNC_CTL_SOC_PZ_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ10_FUNC_CTL_SOC_PZ_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ11_FUNC_CTL function mux definitions */ +#define IOC_PZ11_FUNC_CTL_BGPIO_Z_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ11_FUNC_CTL_BGPIO_Z_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ11_FUNC_CTL_STANDBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ11_FUNC_CTL_STANDBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ11_FUNC_CTL_TAMP_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ11_FUNC_CTL_TAMP_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ11_FUNC_CTL_SOC_PZ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ11_FUNC_CTL_SOC_PZ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #endif /* HPM_BATT_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_bcfg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_bcfg_regs.h index 07e8001cd0b..30b36db600e 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_bcfg_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_bcfg_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_bgpr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_bgpr_regs.h index 46bb7beb07b..9d81aab19cf 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_bgpr_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_bgpr_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -10,106 +10,32 @@ #define HPM_BGPR_H typedef struct { - __RW uint32_t BATT_GPR0; /* 0x0: Generic control */ - __RW uint32_t BATT_GPR1; /* 0x4: Generic control */ - __RW uint32_t BATT_GPR2; /* 0x8: Generic control */ - __RW uint32_t BATT_GPR3; /* 0xC: Generic control */ - __RW uint32_t BATT_GPR4; /* 0x10: Generic control */ - __RW uint32_t BATT_GPR5; /* 0x14: Generic control */ - __RW uint32_t BATT_GPR6; /* 0x18: Generic control */ - __RW uint32_t BATT_GPR7; /* 0x1C: Generic control */ + __RW uint32_t GPR[8]; /* 0x0 - 0x1C: Generic control */ } BGPR_Type; -/* Bitfield definition for register: BATT_GPR0 */ +/* Bitfield definition for register array: GPR */ /* - * GPR (RW) + * DATA (RW) * * Generic control */ -#define BGPR_BATT_GPR0_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR0_GPR_SHIFT (0U) -#define BGPR_BATT_GPR0_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR0_GPR_SHIFT) & BGPR_BATT_GPR0_GPR_MASK) -#define BGPR_BATT_GPR0_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR0_GPR_MASK) >> BGPR_BATT_GPR0_GPR_SHIFT) +#define BGPR_GPR_DATA_MASK (0xFFFFFFFFUL) +#define BGPR_GPR_DATA_SHIFT (0U) +#define BGPR_GPR_DATA_SET(x) (((uint32_t)(x) << BGPR_GPR_DATA_SHIFT) & BGPR_GPR_DATA_MASK) +#define BGPR_GPR_DATA_GET(x) (((uint32_t)(x) & BGPR_GPR_DATA_MASK) >> BGPR_GPR_DATA_SHIFT) -/* Bitfield definition for register: BATT_GPR1 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR1_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR1_GPR_SHIFT (0U) -#define BGPR_BATT_GPR1_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR1_GPR_SHIFT) & BGPR_BATT_GPR1_GPR_MASK) -#define BGPR_BATT_GPR1_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR1_GPR_MASK) >> BGPR_BATT_GPR1_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR2 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR2_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR2_GPR_SHIFT (0U) -#define BGPR_BATT_GPR2_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR2_GPR_SHIFT) & BGPR_BATT_GPR2_GPR_MASK) -#define BGPR_BATT_GPR2_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR2_GPR_MASK) >> BGPR_BATT_GPR2_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR3 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR3_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR3_GPR_SHIFT (0U) -#define BGPR_BATT_GPR3_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR3_GPR_SHIFT) & BGPR_BATT_GPR3_GPR_MASK) -#define BGPR_BATT_GPR3_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR3_GPR_MASK) >> BGPR_BATT_GPR3_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR4 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR4_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR4_GPR_SHIFT (0U) -#define BGPR_BATT_GPR4_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR4_GPR_SHIFT) & BGPR_BATT_GPR4_GPR_MASK) -#define BGPR_BATT_GPR4_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR4_GPR_MASK) >> BGPR_BATT_GPR4_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR5 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR5_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR5_GPR_SHIFT (0U) -#define BGPR_BATT_GPR5_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR5_GPR_SHIFT) & BGPR_BATT_GPR5_GPR_MASK) -#define BGPR_BATT_GPR5_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR5_GPR_MASK) >> BGPR_BATT_GPR5_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR6 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR6_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR6_GPR_SHIFT (0U) -#define BGPR_BATT_GPR6_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR6_GPR_SHIFT) & BGPR_BATT_GPR6_GPR_MASK) -#define BGPR_BATT_GPR6_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR6_GPR_MASK) >> BGPR_BATT_GPR6_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR7 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR7_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR7_GPR_SHIFT (0U) -#define BGPR_BATT_GPR7_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR7_GPR_SHIFT) & BGPR_BATT_GPR7_GPR_MASK) -#define BGPR_BATT_GPR7_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR7_GPR_MASK) >> BGPR_BATT_GPR7_GPR_SHIFT) +/* GPR register group index macro definition */ +#define BGPR_GPR_0 (0UL) +#define BGPR_GPR_1 (1UL) +#define BGPR_GPR_2 (2UL) +#define BGPR_GPR_3 (3UL) +#define BGPR_GPR_4 (4UL) +#define BGPR_GPR_5 (5UL) +#define BGPR_GPR_6 (6UL) +#define BGPR_GPR_7 (7UL) #endif /* HPM_BGPR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_bpor_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_bpor_regs.h index 32147d05a2f..4f48a15578d 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_bpor_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_bpor_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.c index 9e897fef0e2..59a7a2706fc 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -58,6 +58,11 @@ static uint32_t get_frequency_for_i2s_or_adc(uint32_t clk_src_type, uint32_t ins */ static uint32_t get_frequency_for_wdg(uint32_t instance); +/** + * @brief Get Clock frequency for PWDG + */ +static uint32_t get_frequency_for_pwdg(void); + /** * @brief Turn on/off the IP clock */ @@ -106,6 +111,9 @@ uint32_t clock_get_frequency(clock_name_t clock_name) case CLK_SRC_GROUP_WDG: clk_freq = get_frequency_for_wdg(node_or_instance); break; + case CLK_SRC_GROUP_PWDG: + clk_freq = get_frequency_for_pwdg(); + break; case CLK_SRC_GROUP_PMIC: clk_freq = FREQ_PRESET1_OSC0_CLK0; break; @@ -219,7 +227,11 @@ static uint32_t get_frequency_for_i2s_or_adc(uint32_t clk_src_type, uint32_t ins } if (is_mux_valid) { - clk_freq = get_frequency_for_ip_in_common_group(node); + if (node == clock_node_ahb0) { + clk_freq = get_frequency_for_ip_in_common_group(clock_node_ahb0); + } else { + clk_freq = get_frequency_for_ip_in_common_group(node); + } } return clk_freq; } @@ -239,6 +251,18 @@ static uint32_t get_frequency_for_wdg(uint32_t instance) return freq_in_hz; } +static uint32_t get_frequency_for_pwdg(void) +{ + uint32_t freq_in_hz; + if (WDG_CTRL_CLKSEL_GET(HPM_PWDG->CTRL) == 0) { + freq_in_hz = FREQ_PRESET1_OSC0_CLK0; + } else { + freq_in_hz = FREQ_32KHz; + } + + return freq_in_hz; +} + clk_src_t clock_get_source(clock_name_t clock_name) { uint8_t clk_src_group = CLK_SRC_GROUP_INVALID; @@ -265,9 +289,13 @@ clk_src_t clock_get_source(clock_name_t clock_name) case CLK_SRC_GROUP_WDG: if (node_or_instance < WDG_INSTANCE_NUM) { clk_src_group = CLK_SRC_GROUP_WDG; - clk_src_index = (WDG_CTRL_CLKSEL_GET(s_wdgs[node_or_instance]->CTRL) == 0); + clk_src_index = WDG_CTRL_CLKSEL_GET(s_wdgs[node_or_instance]->CTRL); } break; + case CLK_SRC_GROUP_PWDG: + clk_src_group = CLK_SRC_GROUP_PWDG; + clk_src_index = WDG_CTRL_CLKSEL_GET(HPM_PWDG->CTRL); + break; case CLK_SRC_GROUP_PMIC: clk_src_group = CLK_SRC_GROUP_COMMON; clk_src_index = clock_source_osc0_clk0; @@ -314,6 +342,51 @@ clk_src_t clock_get_source(clock_name_t clock_name) return clk_src; } +uint32_t clock_get_divider(clock_name_t clock_name) +{ + uint32_t clk_divider = CLOCK_DIV_INVALID; + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + switch (clk_src_type) { + case CLK_SRC_GROUP_COMMON: + clk_divider = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[node_or_instance]); + break; + case CLK_SRC_GROUP_WDG: + if (node_or_instance < WDG_INSTANCE_NUM) { + clk_divider = 1UL; + } + break; + case CLK_SRC_GROUP_PWDG: + clk_divider = 1UL; + break; + case CLK_SRC_GROUP_PMIC: + clk_divider = 1UL; + break; + case CLK_SRC_GROUP_AHB: + clk_divider = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_ahb0]); + break; + case CLK_SRC_GROUP_AXI0: + clk_divider = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_axi0]); + break; + case CLK_SRC_GROUP_AXI1: + clk_divider = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_axi1]); + break; + case CLK_SRC_GROUP_AXI2: + clk_divider = SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_axi2]); + break; + case CLK_SRC_GROUP_CPU0: + clk_divider = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_cpu0]); + break; + case CLK_SRC_GROUP_CPU1: + clk_divider = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_cpu1]); + break; + default: + clk_divider = CLOCK_DIV_INVALID; + break; + } + return clk_divider; +} + hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src) { uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); @@ -323,7 +396,7 @@ hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src) return status_clk_invalid; } - if ((src <= clk_adc_src_ahb0) || (src >= clk_adc_src_ana2)) { + if ((src < clk_adc_src_ahb0) || (src > clk_adc_src_ana2)) { return status_clk_src_invalid; } @@ -369,21 +442,11 @@ hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint } break; case CLK_SRC_GROUP_ADC: - status = status_clk_operation_unsupported; - break; case CLK_SRC_GROUP_I2S: - status = status_clk_operation_unsupported; - break; case CLK_SRC_GROUP_WDG: - if (node_or_instance < WDG_INSTANCE_NUM) { - if (src == clk_wdg_src_ahb0) { - s_wdgs[node_or_instance]->CTRL &= ~WDG_CTRL_CLKSEL_MASK; - } else if (src == clk_wdg_src_osc32k) { - s_wdgs[node_or_instance]->CTRL |= WDG_CTRL_CLKSEL_MASK; - } else { - status = status_clk_src_invalid; - } - } + case CLK_SRC_GROUP_PWDG: + case CLK_SRC_GROUP_SRC: + status = status_clk_operation_unsupported; break; case CLK_SRC_GROUP_PMIC: status = status_clk_fixed; @@ -406,9 +469,6 @@ hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint case CLK_SRC_GROUP_CPU1: status = status_clk_shared_cpu1; break; - case CLK_SRC_GROUP_SRC: - status = status_clk_operation_unsupported; - break; default: status = status_clk_src_invalid; break; @@ -417,7 +477,7 @@ hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint return status; } -void switch_ip_clock(clock_name_t clock_name, bool on) +static void switch_ip_clock(clock_name_t clock_name, bool on) { uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); @@ -457,6 +517,13 @@ void clock_remove_from_group(clock_name_t clock_name, uint32_t group) } } +bool clock_check_in_group(clock_name_t clock_name, uint32_t group) +{ + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + return sysctl_check_group_resource_enable(HPM_SYSCTL, group, resource); +} + void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu) { if (cpu < 2U) { diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.h index 23a46a75c4c..13824aea228 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -18,6 +18,8 @@ * */ +#define CLOCK_DIV_INVALID (~0UL) + /** * @brief Error codes for clock driver */ @@ -51,6 +53,7 @@ enum { #define CLK_SRC_GROUP_CPU0 (9U) #define CLK_SRC_GROUP_CPU1 (10U) #define CLK_SRC_GROUP_SRC (11U) +#define CLK_SRC_GROUP_PWDG (12U) #define CLK_SRC_GROUP_INVALID (15U) #define MAKE_CLK_SRC(src_grp, index) (((uint8_t)(src_grp) << 4) | (index)) @@ -86,6 +89,9 @@ typedef enum _clock_sources { clk_wdg_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_WDG, 0), clk_wdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_WDG, 1), + clk_pwdg_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_PWDG, 0), + clk_pwdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_PWDG, 1), + clk_src_invalid = MAKE_CLK_SRC(CLK_SRC_GROUP_INVALID, 15), } clk_src_t; @@ -164,7 +170,7 @@ typedef enum _clock_name { clock_watchdog2 = MAKE_CLOCK_NAME(sysctl_resource_wdg2, CLK_SRC_GROUP_WDG, 2), clock_watchdog3 = MAKE_CLOCK_NAME(sysctl_resource_wdg3, CLK_SRC_GROUP_WDG, 3), clock_puart = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 0), - clock_pwdg = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 1), + clock_pwdg = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PWDG, 0), clock_eth0 = MAKE_CLOCK_NAME(sysctl_resource_eth0, CLK_SRC_GROUP_COMMON, clock_node_eth0), clock_eth1 = MAKE_CLOCK_NAME(sysctl_resource_eth1, CLK_SRC_GROUP_COMMON, clock_node_eth1), clock_ptp0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ptp0), @@ -189,8 +195,8 @@ typedef enum _clock_name { clock_mot2 = MAKE_CLOCK_NAME(sysctl_resource_mot2, CLK_SRC_GROUP_AHB, 8), clock_mot3 = MAKE_CLOCK_NAME(sysctl_resource_mot3, CLK_SRC_GROUP_AHB, 9), clock_acmp = MAKE_CLOCK_NAME(sysctl_resource_acmp, CLK_SRC_GROUP_AHB, 10), - clock_pdm = MAKE_CLOCK_NAME(sysctl_resource_i2spdm0, CLK_SRC_GROUP_AHB, 11), - clock_dao = MAKE_CLOCK_NAME(sysctl_resource_i2sdao, CLK_SRC_GROUP_AHB, 12), + clock_pdm = MAKE_CLOCK_NAME(sysctl_resource_i2spdm0, CLK_SRC_GROUP_I2S, 0), + clock_dao = MAKE_CLOCK_NAME(sysctl_resource_i2sdao, CLK_SRC_GROUP_I2S, 1), clock_msyn = MAKE_CLOCK_NAME(sysctl_resource_msyn, CLK_SRC_GROUP_AHB, 12), clock_lmm0 = MAKE_CLOCK_NAME(sysctl_resource_lmm0, CLK_SRC_GROUP_CPU0, 0), clock_lmm1 = MAKE_CLOCK_NAME(sysctl_resource_lmm1, CLK_SRC_GROUP_CPU1, 0), @@ -214,14 +220,14 @@ typedef enum _clock_name { clock_i2s3 = MAKE_CLOCK_NAME(sysctl_resource_i2s3, CLK_SRC_GROUP_I2S, 3), /* Clock sources */ - clk_osc0clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 0), - clk_pll0clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 1), - clk_pll1clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 2), - clk_pll1clk1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 3), - clk_pll2clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 4), - clk_pll2clk1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 5), - clk_pll3clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 6), - clk_pll4clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 7), + clk_osc0clk0 = MAKE_CLOCK_NAME(sysctl_resource_xtal, CLK_SRC_GROUP_SRC, 0), + clk_pll0clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll0, CLK_SRC_GROUP_SRC, 1), + clk_pll1clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll1, CLK_SRC_GROUP_SRC, 2), + clk_pll1clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll1, CLK_SRC_GROUP_SRC, 3), + clk_pll2clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll2, CLK_SRC_GROUP_SRC, 4), + clk_pll2clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll2, CLK_SRC_GROUP_SRC, 5), + clk_pll3clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll3, CLK_SRC_GROUP_SRC, 6), + clk_pll4clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll4, CLK_SRC_GROUP_SRC, 7), } clock_name_t; #ifdef __cplusplus @@ -229,126 +235,142 @@ extern "C" { #endif - /** - * @brief Get specified IP frequency - * @param[in] clock_name IP clock name - * - * @return IP clock frequency in Hz - */ - uint32_t clock_get_frequency(clock_name_t clock_name); - - /** - * @brief Get the IP clock source - * Note: This API return the direct clock source - * @return IP clock source - */ - clk_src_t clock_get_source(clock_name_t clock_name); - - /** - * @brief Set ADC clock source - * @param[in] clock_name ADC clock name - * @param[in] src ADC clock source - * - * @retval status_success Setting ADC clock source is successful - * @retval status_clk_invalid Invalid ADC clock - * @retval status_clk_src_invalid Invalid ADC clock source - */ - hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src); - - /** - * @brief Set I2S clock source - * @param[in] clock_name I2S clock name - * @param[in] src I2S clock source - * - * @retval status_success Setting I2S clock source is successful - * @retval status_clk_invalid Invalid I2S clock - * @retval status_clk_src_invalid Invalid I2S clock source - */ - hpm_stat_t clock_set_i2s_source(clock_name_t clock_name, clk_src_t src); - - /** - * @brief Set the IP clock source and divider - * @param[in] clock_name clock name - * @param[in] src clock source - * @param[in] div clock divider, valid range (1 - 256) - * - * @retval status_success Setting Clock source and divider is successful. - * @retval status_clk_set_by_other_api The clock should be set by other API - * @retval status_clk_src_invalid clock source is invalid. - * @retval status_clk_fixed clock source and divider is a fixed value - * @retval status_clk_shared_ahb Clock is shared with the AHB clock - * @retval status_clk_shared_axi0 Clock is shared with the AXI0 clock - * @retval status_clk_shared_axi1 CLock is shared with the AXI1 clock - * @retval status_clk_shared_axi2 Clock is shared with the AXI2 clock - * @retval status_clk_shared_cpu0 Clock is shared with the CPU0 clock - * @retval status_clk_shared_cpu1 Clock is shared with the CPU1 clock - */ - hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint32_t div); - - /** - * @brief Enable IP clock - * @param[in] clock_name IP clock name - */ - void clock_enable(clock_name_t clock_name); - - /** - * @brief Disable IP clock - * @param[in] clock_name IP clock name - */ - void clock_disable(clock_name_t clock_name); - - /** - * @brief Add IP to specified group - * @param[in] clock_name IP clock name - * @param[in] group resource group index, valid value: 0/1/2/3 - */ - void clock_add_to_group(clock_name_t clock_name, uint32_t group); - - /** - * @brief Remove IP from specified group - * @param[in] clock_name IP clock name - * @param[in] group resource group index, valid value: 0/1/2/3 - */ - void clock_remove_from_group(clock_name_t clock_name, uint32_t group); - - /** - * @brief Disconnect the clock group from specified CPU - * @param[in] group clock group index, value value is 0/1/2/3 - * @param[in] cpu CPU index, valid value is 0/1 - */ - void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu); - - /** - * @brief Disconnect the clock group from specified CPU - * @param[in] group clock group index, value value is 0/1/2/3 - * @param[in] cpu CPU index, valid value is 0/1 - */ - void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu); - - - /** - * @brief Delay specified microseconds - * - * @param [in] us expected delay interval in microseconds - */ - void clock_cpu_delay_us(uint32_t us); - - /** - * @brief Delay specified milliseconds - * - * @param [in] ms expected delay interval in milliseconds - */ - void clock_cpu_delay_ms(uint32_t ms); - - /** - * @brief Update the Core clock frequency - */ - void clock_update_core_clock(void); - - /** - * @brief HPM Core clock variable - */ - extern uint32_t hpm_core_clock; +/** + * @brief Get specified IP frequency + * @param[in] clock_name IP clock name + * + * @return IP clock frequency in Hz + */ +uint32_t clock_get_frequency(clock_name_t clock_name); + +/** + * @brief Get the IP clock source + * @param[in] clock_name IP clock name + * + * @return IP clock source + */ +clk_src_t clock_get_source(clock_name_t clock_name); + +/** + * @brief Get the IP clock divider + * Note:This API return the direct clock divider + * @param [in] clock_name clock name + * @return IP clock divider + */ +uint32_t clock_get_divider(clock_name_t clock_name); + +/** + * @brief Set ADC clock source + * @param[in] clock_name ADC clock name + * @param[in] src ADC clock source + * + * @retval status_success Setting ADC clock source is successful + * @retval status_clk_invalid Invalid ADC clock + * @retval status_clk_src_invalid Invalid ADC clock source + */ +hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src); + +/** + * @brief Set I2S clock source + * @param[in] clock_name I2S clock name + * @param[in] src I2S clock source + * + * @retval status_success Setting I2S clock source is successful + * @retval status_clk_invalid Invalid I2S clock + * @retval status_clk_src_invalid Invalid I2S clock source + */ +hpm_stat_t clock_set_i2s_source(clock_name_t clock_name, clk_src_t src); + +/** + * @brief Set the IP clock source and divider + * @param[in] clock_name clock name + * @param[in] src clock source + * @param[in] div clock divider, valid range (1 - 256) + * + * @retval status_success Setting Clock source and divider is successful. + * @retval status_clk_set_by_other_api The clock should be set by other API + * @retval status_clk_src_invalid clock source is invalid. + * @retval status_clk_fixed clock source and divider is a fixed value + * @retval status_clk_shared_ahb Clock is shared with the AHB clock + * @retval status_clk_shared_axi0 Clock is shared with the AXI0 clock + * @retval status_clk_shared_axi1 CLock is shared with the AXI1 clock + * @retval status_clk_shared_axi2 Clock is shared with the AXI2 clock + * @retval status_clk_shared_cpu0 Clock is shared with the CPU0 clock + * @retval status_clk_shared_cpu1 Clock is shared with the CPU1 clock + */ +hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint32_t div); + +/** + * @brief Enable IP clock + * @param[in] clock_name IP clock name + */ +void clock_enable(clock_name_t clock_name); + +/** + * @brief Disable IP clock + * @param[in] clock_name IP clock name + */ +void clock_disable(clock_name_t clock_name); + +/** + * @brief Add IP to specified group + * @param[in] clock_name IP clock name + * @param[in] group resource group index, valid value: 0/1/2/3 + */ +void clock_add_to_group(clock_name_t clock_name, uint32_t group); + +/** + * @brief Remove IP from specified group + * @param[in] clock_name IP clock name + * @param[in] group resource group index, valid value: 0/1/2/3 + */ +void clock_remove_from_group(clock_name_t clock_name, uint32_t group); + +/** + * @brief Check IP in specified group + * @param[in] clock_name IP clock name + * @param[in] group resource group index, valid value: 0/1/2/3 + * @return true if in group, false if not in group + */ +bool clock_check_in_group(clock_name_t clock_name, uint32_t group); + +/** + * @brief Disconnect the clock group from specified CPU + * @param[in] group clock group index, value value is 0/1/2/3 + * @param[in] cpu CPU index, valid value is 0/1 + */ +void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu); + +/** + * @brief Disconnect the clock group from specified CPU + * @param[in] group clock group index, value value is 0/1/2/3 + * @param[in] cpu CPU index, valid value is 0/1 + */ +void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu); + +/** + * @brief Delay specified microseconds + * + * @param [in] us expected delay interval in microseconds + */ +void clock_cpu_delay_us(uint32_t us); + +/** + * @brief Delay specified milliseconds + * + * @param [in] ms expected delay interval in milliseconds + */ +void clock_cpu_delay_ms(uint32_t ms); + +/** + * @brief Update the Core clock frequency + */ +void clock_update_core_clock(void); + +/** + * @brief HPM Core clock variable + */ +extern uint32_t hpm_core_clock; #ifdef __cplusplus } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_csr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_csr_regs.h index cc29018e112..5f43b12bd1a 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_csr_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_csr_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_dmamux_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_dmamux_regs.h index 640355344e8..e7f67339ea4 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_dmamux_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_dmamux_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_dmamux_src.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_dmamux_src.h index 6f36ba007c7..0dc437c7f7e 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_dmamux_src.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_dmamux_src.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_gpiom_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_gpiom_regs.h index 1ec106d8af4..d9924ef5f69 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_gpiom_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_gpiom_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_gpiom_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_gpiom_soc_drv.h index 2d44d44cbb3..79954c3d8fe 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_gpiom_soc_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_gpiom_soc_drv.h @@ -14,7 +14,7 @@ */ /* @brief gpiom control module */ -typedef enum hpm6700_gpiom_gpio { +typedef enum gpiom_gpio { gpiom_soc_gpio0 = 0, gpiom_soc_gpio1 = 1, gpiom_core0_fast = 2, diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_interrupt.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_interrupt.h index a4271a4d947..a776f7c2dfe 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_interrupt.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_interrupt.h @@ -7,8 +7,8 @@ #ifndef HPM_INTERRUPT_H #define HPM_INTERRUPT_H -#include "riscv/riscv_core.h" #include "hpm_common.h" +#include "hpm_csr_drv.h" #include "hpm_plic_drv.h" /** @@ -359,6 +359,59 @@ ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack */ #if __riscv_flen == 32 +#ifdef __ICCRISCV__ +#define SAVE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fswsp ft0, 20*4\n\ + c.fswsp ft1, 21*4 \n\ + c.fswsp ft2, 22*4 \n\ + c.fswsp ft3, 23*4 \n\ + c.fswsp ft4, 24*4 \n\ + c.fswsp ft5, 25*4 \n\ + c.fswsp ft6, 26*4 \n\ + c.fswsp ft7, 27*4 \n\ + c.fswsp fa0, 28*4 \n\ + c.fswsp fa1, 29*4 \n\ + c.fswsp fa2, 30*4 \n\ + c.fswsp fa3, 31*4 \n\ + c.fswsp fa4, 32*4 \n\ + c.fswsp fa5, 33*4 \n\ + c.fswsp fa6, 34*4 \n\ + c.fswsp fa7, 35*4 \n\ + c.fswsp ft8, 36*4 \n\ + c.fswsp ft9, 37*4 \n\ + c.fswsp ft10, 38*4 \n\ + c.fswsp ft11, 39*4 \n");\ +} + +/* + * Restore FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack + */ +#define RESTORE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.flwsp ft0, 20*4\n\ + c.flwsp ft1, 21*4 \n\ + c.flwsp ft2, 22*4 \n\ + c.flwsp ft3, 23*4 \n\ + c.flwsp ft4, 24*4 \n\ + c.flwsp ft5, 25*4 \n\ + c.flwsp ft6, 26*4 \n\ + c.flwsp ft7, 27*4 \n\ + c.flwsp fa0, 28*4 \n\ + c.flwsp fa1, 29*4 \n\ + c.flwsp fa2, 30*4 \n\ + c.flwsp fa3, 31*4 \n\ + c.flwsp fa4, 32*4 \n\ + c.flwsp fa5, 33*4 \n\ + c.flwsp fa6, 34*4 \n\ + c.flwsp fa7, 35*4 \n\ + c.flwsp ft8, 36*4 \n\ + c.flwsp ft9, 37*4 \n\ + c.flwsp ft10, 38*4 \n\ + c.flwsp ft11, 39*4 \n");\ +} +#else /* __ICCRISCV__ not defined */ #define SAVE_FPU_CONTEXT() { \ __asm volatile("\n\ c.fswsp ft0, 20*4(sp)\n\ @@ -410,7 +463,61 @@ ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) c.flwsp ft10, 38*4(sp) \n\ c.flwsp ft11, 39*4(sp) \n");\ } +#endif #else /*__riscv_flen == 64*/ +#ifdef __ICCRISCV__ +#define SAVE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fsdsp ft0, 20*4\n\ + c.fsdsp ft1, 22*4 \n\ + c.fsdsp ft2, 24*4 \n\ + c.fsdsp ft3, 26*4 \n\ + c.fsdsp ft4, 28*4 \n\ + c.fsdsp ft5, 30*4 \n\ + c.fsdsp ft6, 32*4 \n\ + c.fsdsp ft7, 34*4 \n\ + c.fsdsp fa0, 36*4 \n\ + c.fsdsp fa1, 38*4 \n\ + c.fsdsp fa2, 40*4 \n\ + c.fsdsp fa3, 42*4 \n\ + c.fsdsp fa4, 44*4 \n\ + c.fsdsp fa5, 46*4 \n\ + c.fsdsp fa6, 48*4 \n\ + c.fsdsp fa7, 50*4 \n\ + c.fsdsp ft8, 52*4 \n\ + c.fsdsp ft9, 54*4 \n\ + c.fsdsp ft10, 56*4 \n\ + c.fsdsp ft11, 58*4 \n");\ +} + +/* + * Restore FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack + */ +#define RESTORE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fldsp ft0, 20*4\n\ + c.fldsp ft1, 22*4 \n\ + c.fldsp ft2, 24*4 \n\ + c.fldsp ft3, 26*4 \n\ + c.fldsp ft4, 28*4 \n\ + c.fldsp ft5, 30*4 \n\ + c.fldsp ft6, 32*4 \n\ + c.fldsp ft7, 34*4 \n\ + c.fldsp fa0, 36*4 \n\ + c.fldsp fa1, 38*4 \n\ + c.fldsp fa2, 40*4 \n\ + c.fldsp fa3, 42*4 \n\ + c.fldsp fa4, 44*4 \n\ + c.fldsp fa5, 46*4 \n\ + c.fldsp fa6, 48*4 \n\ + c.fldsp fa7, 50*4 \n\ + c.fldsp ft8, 52*4 \n\ + c.fldsp ft9, 54*4 \n\ + c.fldsp ft10, 56*4 \n\ + c.fldsp ft11, 58*4 \n");\ +} +#else #define SAVE_FPU_CONTEXT() { \ __asm volatile("\n\ c.fsdsp ft0, 20*4(sp)\n\ @@ -463,11 +570,71 @@ ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) c.fldsp ft11, 58*4(sp) \n");\ } #endif +#endif #else #define SAVE_FPU_CONTEXT() #define RESTORE_FPU_CONTEXT() #endif +#ifdef __ICCRISCV__ +/** + * @brief Save the caller registers based on the RISC-V ABI specification + */ +#define SAVE_CALLER_CONTEXT() { \ + __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\ + __asm volatile("\n\ + c.swsp ra, 0*4 \n\ + c.swsp t0, 1*4 \n\ + c.swsp t1, 2*4 \n\ + c.swsp t2, 3*4 \n\ + c.swsp s0, 4*4 \n\ + c.swsp s1, 5*4 \n\ + c.swsp a0, 6*4 \n\ + c.swsp a1, 7*4 \n\ + c.swsp a2, 8*4 \n\ + c.swsp a3, 9*4 \n\ + c.swsp a4, 10*4 \n\ + c.swsp a5, 11*4 \n\ + c.swsp a6, 12*4 \n\ + c.swsp a7, 13*4 \n\ + c.swsp s2, 14*4 \n\ + c.swsp s3, 15*4 \n\ + c.swsp t3, 16*4 \n\ + c.swsp t4, 17*4 \n\ + c.swsp t5, 18*4 \n\ + c.swsp t6, 19*4"); \ + SAVE_FPU_CONTEXT(); \ +} + +/** + * @brief Restore the caller registers based on the RISC-V ABI specification + */ +#define RESTORE_CALLER_CONTEXT() { \ + __asm volatile("\n\ + c.lwsp ra, 0*4 \n\ + c.lwsp t0, 1*4 \n\ + c.lwsp t1, 2*4 \n\ + c.lwsp t2, 3*4 \n\ + c.lwsp s0, 4*4 \n\ + c.lwsp s1, 5*4 \n\ + c.lwsp a0, 6*4 \n\ + c.lwsp a1, 7*4 \n\ + c.lwsp a2, 8*4 \n\ + c.lwsp a3, 9*4 \n\ + c.lwsp a4, 10*4 \n\ + c.lwsp a5, 11*4 \n\ + c.lwsp a6, 12*4 \n\ + c.lwsp a7, 13*4 \n\ + c.lwsp s2, 14*4 \n\ + c.lwsp s3, 15*4 \n\ + c.lwsp t3, 16*4 \n\ + c.lwsp t4, 17*4 \n\ + c.lwsp t5, 18*4 \n\ + c.lwsp t6, 19*4 \n");\ + RESTORE_FPU_CONTEXT(); \ + __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\ +} +#else /** * @brief Save the caller registers based on the RISC-V ABI specification */ @@ -525,14 +692,15 @@ ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) RESTORE_FPU_CONTEXT(); \ __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\ } +#endif #ifdef __riscv_flen #define SAVE_FPU_STATE() { \ - __asm volatile("frsr s1\n"); \ + __asm volatile("frcsr s1\n"); \ } #define RESTORE_FPU_STATE() { \ - __asm volatile("fssr s1\n"); \ + __asm volatile("fscsr s1\n"); \ } #else #define SAVE_FPU_STATE() @@ -545,14 +713,14 @@ ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) * NOTE: DSP context registers are stored at word offset 41 in the stack */ #define SAVE_DSP_CONTEXT() { \ - __asm volatile("rdov s0\n"); \ + __asm volatile("csrrs s0, %0, x0\n" ::"i"(CSR_UCODE):); \ } /* * @brief Restore DSP context * @note DSP context registers are stored at word offset 41 in the stack */ #define RESTORE_DSP_CONTEXT() {\ - __asm volatile("csrw ucode, s0\n"); \ + __asm volatile("csrw %0, s0\n" ::"i"(CSR_UCODE):); \ } #else @@ -574,25 +742,17 @@ ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) csrr s3, mstatus \n");\ SAVE_FPU_STATE(); \ SAVE_DSP_CONTEXT(); \ - __asm volatile ("\n\ - c.li a5, 8\n\ - csrs mstatus, a5\n"); \ + __asm volatile("csrsi mstatus, 8"); \ } /* * @brief Complete IRQ Handling */ #define COMPLETE_IRQ_HANDLING_M(irq_num) { \ - __asm volatile("\n\ - lui a5, 0x1\n\ - addi a5, a5, -2048\n\ - csrc mie, a5\n"); \ - __asm volatile("\n\ - lui a4, 0xe4200\n");\ + __asm volatile("csrci mstatus, 8"); \ + __asm volatile("lui a4, 0xe4200"); \ __asm volatile("li a3, %0" : : "i" (irq_num) :); \ - __asm volatile("sw a3, 4(a4)\n\ - fence io, io\n"); \ - __asm volatile("csrs mie, a5"); \ + __asm volatile("sw a3, 4(a4)"); \ } /* @@ -611,7 +771,6 @@ ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) RESTORE_DSP_CONTEXT(); \ } - /* @brief Nested IRQ entry macro : Save CSRs and enable global irq. */ #define NESTED_IRQ_ENTER() \ SAVE_CSR(CSR_MEPC) \ @@ -629,18 +788,6 @@ ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) RESTORE_FCSR() \ RESTORE_UCODE() -/* - * @brief Nested IRQ exit macro : Restore CSRs - * @param[in] irq Target interrupt number - */ -#define NESTED_VPLIC_COMPLETE_INTERRUPT(irq) \ -do { \ - clear_csr(CSR_MIE, CSR_MIP_MEIP_MASK); \ - __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq); \ - __asm volatile("fence io, io"); \ - set_csr(CSR_MIE, CSR_MIP_MEIP_MASK); \ -} while (0) - #ifdef __cplusplus #define HPM_EXTERN_C extern "C" #else @@ -658,7 +805,7 @@ do { \ #define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ void isr(void) __attribute__((section(".isr_vector")));\ HPM_EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ -void ISR_NAME_M(irq_num)(void) \ +void ISR_NAME_M(irq_num)(void) \ { \ SAVE_CALLER_CONTEXT(); \ ENTER_NESTED_IRQ_HANDLING_M();\ @@ -667,6 +814,7 @@ void ISR_NAME_M(irq_num)(void) \ COMPLETE_IRQ_HANDLING_M(irq_num);\ EXIT_NESTED_IRQ_HANDLING_M();\ RESTORE_CALLER_CONTEXT();\ + __asm volatile("fence io, io");\ __asm volatile("mret\n");\ } #else diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ioc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ioc_regs.h index 91dbb44da0e..de42be177c4 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ioc_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ioc_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -84,7 +84,7 @@ typedef struct { /* * SMT (RW) * - * schmitt trigger enable, only avaiable in high-speed IO + * schmitt trigger enable, only available in high-speed IO * 0: disable * 1: enable */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_iomux.h index 6e13e8b131b..7f386ba80e1 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_iomux.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_iomux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_l1c_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_l1c_drv.h index e328193a072..1f1a21639a2 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_l1c_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_l1c_drv.h @@ -7,8 +7,8 @@ #ifndef _HPM_L1_CACHE_H #define _HPM_L1_CACHE_H -#include "riscv/riscv_core.h" #include "hpm_common.h" +#include "hpm_csr_drv.h" #include "hpm_soc.h" /** diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_otp_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_otp_drv.c index b9d9297b31f..f16c4c1b231 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_otp_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_otp_drv.c @@ -1,5 +1,5 @@ /* -* Copyright (c) 2021 HPMicro +* Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -8,12 +8,14 @@ #include "hpm_common.h" #include "hpm_soc.h" #include "hpm_otp_drv.h" +#include "hpm_clock_drv.h" /*********************************************************************************************************************** * Definitions **********************************************************************************************************************/ #define SHADOW_INDEX_IN_PMIC_OTP_END (15U) #define OTP_UNLOCK_MAGIC_NUM (0x4E45504FUL) /*!< ASCII: OPEN */ +#define OTP_LOCK_MAGIC_NUM (~OTP_UNLOCK_MAGIC_NUM) #define OTP_CMD_PROGRAM (0x574F4C42UL) /*!< ASCII: BLOW */ #define OTP_CMD_READ (0x44414552UL) /*!< ASCII: READ */ @@ -45,12 +47,7 @@ uint32_t otp_read_from_ip(uint32_t addr) { uint32_t ret_val = 0; if (addr < ARRAY_SIZE(HPM_OTP->SHADOW)) { - HPM_OTP->ADDR = addr; - HPM_OTP->INT_FLAG = OTP_INT_FLAG_READ_MASK; /* Write-1-Clear */ - HPM_OTP->CMD = OTP_CMD_READ; - while (!IS_HPM_BITMASK_SET(HPM_OTP->INT_FLAG, OTP_INT_FLAG_READ_MASK)) { - } - ret_val = HPM_OTP->DATA; + ret_val = HPM_OTP->FUSE[addr]; } return ret_val; } @@ -65,26 +62,13 @@ hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words /* Enable 2.5V LDO for FUSE programming */ uint32_t reg_val = (HPM_PCFG->LDO2P5 & ~PCFG_LDO2P5_VOLT_MASK) | PCFG_LDO2P5_ENABLE_MASK | PCFG_LDO2P5_VOLT_SET(2500); HPM_PCFG->LDO2P5 = reg_val; - /* TODO: delay 1ms, wait for design team's update to get a steady bit (bit28 in this reg) */ + clock_cpu_delay_ms(1); + HPM_OTP->UNLOCK = OTP_UNLOCK_MAGIC_NUM; for (uint32_t i = 0; i < num_of_words; i++) { - /* - HPM_OTP->UNLOCK = OTP_UNLOCK_MAGIC_NUM; HPM_OTP->FUSE[addr++] = *src++; - */ - HPM_OTP->UNLOCK = OTP_UNLOCK_MAGIC_NUM; - HPM_OTP->ADDR = addr; - HPM_OTP->DATA = *src; - HPM_OTP->INT_FLAG = OTP_INT_FLAG_WRITE_MASK; /* Write-1-Clear */ - HPM_OTP->CMD = OTP_CMD_PROGRAM; - - ++src; - ++addr; - while (!IS_HPM_BITMASK_SET(HPM_OTP->INT_FLAG, OTP_INT_FLAG_WRITE_MASK)) { - - } - } + HPM_OTP->UNLOCK = OTP_LOCK_MAGIC_NUM; /* Disable 2.5V LDO after FUSE programming for saving power */ HPM_PCFG->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; status = status_success; @@ -108,7 +92,6 @@ hpm_stat_t otp_reload(otp_region_t region) return status; } - hpm_stat_t otp_lock_otp(uint32_t addr, otp_lock_option_t lock_option) { hpm_stat_t status = status_invalid_argument; @@ -131,7 +114,6 @@ hpm_stat_t otp_lock_otp(uint32_t addr, otp_lock_option_t lock_option) return status; } - hpm_stat_t otp_lock_shadow(uint32_t addr, otp_lock_option_t lock_option) { hpm_stat_t status = status_invalid_argument; @@ -154,9 +136,6 @@ hpm_stat_t otp_lock_shadow(uint32_t addr, otp_lock_option_t lock_option) return status; } - - - hpm_stat_t otp_set_configurable_region(uint32_t start, uint32_t num_of_words) { hpm_stat_t status = status_invalid_argument; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_otp_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_otp_drv.h index 1b36b874503..fe647ac5e86 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_otp_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_otp_drv.h @@ -120,7 +120,7 @@ extern "C" { /** * @return Write data to OTP shadow register * @param [in] addr OTP word index - * @param [val] val Data to be written + * @param [in] val Data to be written * @return API execution status */ hpm_stat_t otp_write_shadow_register(uint32_t addr, uint32_t val); diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pcfg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pcfg_drv.h index e99e0837a59..72d7a5f5e84 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pcfg_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pcfg_drv.h @@ -153,26 +153,6 @@ static inline void pcfg_bandgap_reload_trim(PCFG_Type *ptr) ptr->BANDGAP &= ~PCFG_BANDGAP_VBG_TRIMMED_MASK; } -/** - * @brief turn off LDO 1V - * - * @param[in] ptr base address - */ -static inline void pcfg_ldo1p1_turn_off(PCFG_Type *ptr) -{ - ptr->LDO1P1 &= ~PCFG_LDO1P1_ENABLE_MASK; -} - -/** - * @brief turn of LDO 1V - * - * @param[in] ptr base address - */ -static inline void pcfg_ldo1p1_turn_on(PCFG_Type *ptr) -{ - ptr->LDO1P1 |= PCFG_LDO1P1_ENABLE_MASK; -} - /** * @brief turn off LDO2P5 * @@ -229,12 +209,12 @@ static inline void pcfg_dcdc_set_mode(PCFG_Type *ptr, uint8_t mode) * * @param[in] ptr base address * @param[in] limit current limit at low power mode - * @param[in] over_limit set to true means current is greater than limit + * @param[in] over_limit unused parameter, will be discarded */ static inline void pcfg_dcdc_set_lp_current_limit(PCFG_Type *ptr, pcfg_dcdc_lp_current_limit_t limit, bool over_limit) { - ptr->DCDC_PROT = (ptr->DCDC_PROT & ~(PCFG_DCDC_PROT_ILIMIT_LP_MASK | PCFG_DCDC_PROT_OVERLOAD_LP_MASK)) - | PCFG_DCDC_PROT_ILIMIT_LP_SET(limit) | PCFG_DCDC_PROT_OVERLOAD_LP_SET(over_limit); + (void) over_limit; + ptr->DCDC_PROT = (ptr->DCDC_PROT & ~PCFG_DCDC_PROT_ILIMIT_LP_MASK) | PCFG_DCDC_PROT_ILIMIT_LP_SET(limit); } /** @@ -580,6 +560,31 @@ static inline void pcfg_irc24m_reload_trim(PCFG_Type *ptr) ptr->RC24M &= ~PCFG_RC24M_RC_TRIMMED_MASK; } +/** + * @brief dcdc switch to dcm mode + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_switch_to_dcm_mode(PCFG_Type *ptr) +{ + const uint8_t pcfc_dcdc_min_duty_cycle[] = { + 0x6E, 0x6E, 0x70, 0x70, 0x70, 0x70, 0x72, 0x72, + 0x72, 0x72, 0x74, 0x74, 0x74, 0x74, 0x76, 0x76, + 0x76, 0x78, 0x78, 0x78, 0x78, 0x7A, 0x7A, 0x7A, + 0x7A, 0x7C, 0x7C, 0x7C, 0x7E, 0x7E, 0x7E, 0x7E + }; + uint16_t voltage; + + ptr->DCDC_MODE |= 0x77000u; + ptr->DCDC_ADVMODE = (ptr->DCDC_ADVMODE & ~0x73F0067u) | 0x4120067u; + ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_SHORT_CURRENT_MASK; + ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_SHORT_MASK; + ptr->DCDC_MISC = 0x100000u; + voltage = PCFG_DCDC_MODE_VOLT_GET(ptr->DCDC_MODE); + voltage = (voltage - 600) / 25; + ptr->DCDC_ADVPARAM = (ptr->DCDC_ADVPARAM & ~PCFG_DCDC_ADVPARAM_MIN_DUT_MASK) | PCFG_DCDC_ADVPARAM_MIN_DUT_SET(pcfc_dcdc_min_duty_cycle[voltage]); +} + /** * @brief config irc24m track * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pcfg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pcfg_regs.h index b05080feacc..cfc5f1eba37 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pcfg_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pcfg_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -106,18 +106,6 @@ typedef struct { #define PCFG_BANDGAP_VBG_P50_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_P50_TRIM_MASK) >> PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) /* Bitfield definition for register: LDO1P1 */ -/* - * ENABLE (RW) - * - * LDO enable - * 0: turn off LDO - * 1: turn on LDO - */ -#define PCFG_LDO1P1_ENABLE_MASK (0x10000UL) -#define PCFG_LDO1P1_ENABLE_SHIFT (16U) -#define PCFG_LDO1P1_ENABLE_SET(x) (((uint32_t)(x) << PCFG_LDO1P1_ENABLE_SHIFT) & PCFG_LDO1P1_ENABLE_MASK) -#define PCFG_LDO1P1_ENABLE_GET(x) (((uint32_t)(x) & PCFG_LDO1P1_ENABLE_MASK) >> PCFG_LDO1P1_ENABLE_SHIFT) - /* * VOLT (RW) * @@ -186,7 +174,7 @@ typedef struct { * MODE (RW) * * DCDC work mode - * XX0: trun off + * XX0: turn off * 001: basic mode * 011: generic mode * 101: automatic mode @@ -240,7 +228,7 @@ typedef struct { #define PCFG_DCDC_PROT_ILIMIT_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) >> PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) /* - * OVERLOAD_LP (RW) + * OVERLOAD_LP (RO) * * over current in low power mode * 0: current is below setting @@ -248,7 +236,6 @@ typedef struct { */ #define PCFG_DCDC_PROT_OVERLOAD_LP_MASK (0x1000000UL) #define PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT (24U) -#define PCFG_DCDC_PROT_OVERLOAD_LP_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT) & PCFG_DCDC_PROT_OVERLOAD_LP_MASK) #define PCFG_DCDC_PROT_OVERLOAD_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERLOAD_LP_MASK) >> PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT) /* @@ -277,7 +264,7 @@ typedef struct { /* * DISABLE_OVERVOLTAGE (RW) * - * ouput over voltage protection + * output over voltage protection * 0: protection enabled, DCDC will shut down is output voltage is unexpected high * 1: protection disabled, DCDC continue to adjust output voltage */ @@ -301,7 +288,7 @@ typedef struct { * DISABLE_SHORT (RW) * * disable output short circuit protection - * 0: short circuits protection enabled, DCDC shut down if short circuit on ouput detected + * 0: short circuits protection enabled, DCDC shut down if short circuit on output detected * 1: short circuit protection disabled */ #define PCFG_DCDC_PROT_DISABLE_SHORT_MASK (0x80U) @@ -418,18 +405,6 @@ typedef struct { #define PCFG_DCDC_ADVMODE_EN_FF_LOOP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) #define PCFG_DCDC_ADVMODE_EN_FF_LOOP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) >> PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) -/* - * EN_AUTOLP (RW) - * - * enable auto enter low power mode - * 0: do not enter low power mode - * 1: enter low power mode if current is detected low - */ -#define PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK (0x10U) -#define PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT (4U) -#define PCFG_DCDC_ADVMODE_EN_AUTOLP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT) & PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK) -#define PCFG_DCDC_ADVMODE_EN_AUTOLP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK) >> PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT) - /* * EN_DCM_EXIT (RW) * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pgpr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pgpr_regs.h index 0369149bdd6..acf20cfecd5 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pgpr_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pgpr_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pmic_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pmic_iomux.h index 7a8737a43af..2a8c98bd6ed 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pmic_iomux.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pmic_iomux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -9,77 +9,125 @@ #ifndef HPM_PMIC_IOMUX_H #define HPM_PMIC_IOMUX_H -/* IOC_PY00_FUNC_CTL function mux definitions */ -#define IOC_PY00_FUNC_CTL_PGPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY00_FUNC_CTL_JTAG_TDO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY00_FUNC_CTL_SOC_PY_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PY01_FUNC_CTL function mux definitions */ -#define IOC_PY01_FUNC_CTL_PGPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY01_FUNC_CTL_JTAG_TDI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY01_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY01_FUNC_CTL_SOC_PY_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PY02_FUNC_CTL function mux definitions */ -#define IOC_PY02_FUNC_CTL_PGPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY02_FUNC_CTL_JTAG_TCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY02_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY02_FUNC_CTL_SOC_PY_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PY03_FUNC_CTL function mux definitions */ -#define IOC_PY03_FUNC_CTL_PGPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY03_FUNC_CTL_JTAG_TMS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY03_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY03_FUNC_CTL_SOC_PY_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PY04_FUNC_CTL function mux definitions */ -#define IOC_PY04_FUNC_CTL_PGPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY04_FUNC_CTL_JTAG_TRST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY04_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY04_FUNC_CTL_SOC_PY_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PY05_FUNC_CTL function mux definitions */ -#define IOC_PY05_FUNC_CTL_PGPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY05_FUNC_CTL_PWDG_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY05_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY05_FUNC_CTL_SOC_PY_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PY06_FUNC_CTL function mux definitions */ -#define IOC_PY06_FUNC_CTL_PGPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY06_FUNC_CTL_PUART_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY06_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY06_FUNC_CTL_SOC_PY_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PY07_FUNC_CTL function mux definitions */ -#define IOC_PY07_FUNC_CTL_PGPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY07_FUNC_CTL_PUART_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY07_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY07_FUNC_CTL_SOC_PY_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PY08_FUNC_CTL function mux definitions */ -#define IOC_PY08_FUNC_CTL_PGPIO_Y_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY08_FUNC_CTL_PUART_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY08_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY08_FUNC_CTL_SOC_PY_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PY09_FUNC_CTL function mux definitions */ -#define IOC_PY09_FUNC_CTL_PGPIO_Y_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY09_FUNC_CTL_PUART_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY09_FUNC_CTL_PTMR_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY09_FUNC_CTL_SOC_PY_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PY10_FUNC_CTL function mux definitions */ -#define IOC_PY10_FUNC_CTL_PGPIO_Y_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY10_FUNC_CTL_VAD_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY10_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY10_FUNC_CTL_SOC_PY_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PY11_FUNC_CTL function mux definitions */ -#define IOC_PY11_FUNC_CTL_PGPIO_Y_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY11_FUNC_CTL_VAD_DAT IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY11_FUNC_CTL_PTMR_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY11_FUNC_CTL_SOC_PY_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +/* PIOC_PY00_FUNC_CTL function mux definitions */ +#define IOC_PY00_FUNC_CTL_PGPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY00_FUNC_CTL_PGPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY00_FUNC_CTL_JTAG_TDO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY00_FUNC_CTL_JTAG_TDO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY00_FUNC_CTL_SOC_PY_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY00_FUNC_CTL_SOC_PY_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY01_FUNC_CTL function mux definitions */ +#define IOC_PY01_FUNC_CTL_PGPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY01_FUNC_CTL_PGPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY01_FUNC_CTL_JTAG_TDI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY01_FUNC_CTL_JTAG_TDI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY01_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY01_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY01_FUNC_CTL_SOC_PY_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY01_FUNC_CTL_SOC_PY_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY02_FUNC_CTL function mux definitions */ +#define IOC_PY02_FUNC_CTL_PGPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY02_FUNC_CTL_PGPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY02_FUNC_CTL_JTAG_TCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY02_FUNC_CTL_JTAG_TCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY02_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY02_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY02_FUNC_CTL_SOC_PY_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY02_FUNC_CTL_SOC_PY_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY03_FUNC_CTL function mux definitions */ +#define IOC_PY03_FUNC_CTL_PGPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY03_FUNC_CTL_PGPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY03_FUNC_CTL_JTAG_TMS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY03_FUNC_CTL_JTAG_TMS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY03_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY03_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY03_FUNC_CTL_SOC_PY_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY03_FUNC_CTL_SOC_PY_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY04_FUNC_CTL function mux definitions */ +#define IOC_PY04_FUNC_CTL_PGPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY04_FUNC_CTL_PGPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY04_FUNC_CTL_JTAG_TRST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY04_FUNC_CTL_JTAG_TRST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY04_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY04_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY04_FUNC_CTL_SOC_PY_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY04_FUNC_CTL_SOC_PY_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY05_FUNC_CTL function mux definitions */ +#define IOC_PY05_FUNC_CTL_PGPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY05_FUNC_CTL_PGPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY05_FUNC_CTL_PWDG_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY05_FUNC_CTL_PWDG_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY05_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY05_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY05_FUNC_CTL_SOC_PY_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY05_FUNC_CTL_SOC_PY_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY06_FUNC_CTL function mux definitions */ +#define IOC_PY06_FUNC_CTL_PGPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY06_FUNC_CTL_PGPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY06_FUNC_CTL_PUART_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY06_FUNC_CTL_PUART_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY06_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY06_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY06_FUNC_CTL_SOC_PY_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY06_FUNC_CTL_SOC_PY_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY07_FUNC_CTL function mux definitions */ +#define IOC_PY07_FUNC_CTL_PGPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY07_FUNC_CTL_PGPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY07_FUNC_CTL_PUART_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY07_FUNC_CTL_PUART_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY07_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY07_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY07_FUNC_CTL_SOC_PY_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY07_FUNC_CTL_SOC_PY_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY08_FUNC_CTL function mux definitions */ +#define IOC_PY08_FUNC_CTL_PGPIO_Y_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY08_FUNC_CTL_PGPIO_Y_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY08_FUNC_CTL_PUART_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY08_FUNC_CTL_PUART_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY08_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY08_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY08_FUNC_CTL_SOC_PY_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY08_FUNC_CTL_SOC_PY_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY09_FUNC_CTL function mux definitions */ +#define IOC_PY09_FUNC_CTL_PGPIO_Y_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY09_FUNC_CTL_PGPIO_Y_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY09_FUNC_CTL_PUART_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY09_FUNC_CTL_PUART_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY09_FUNC_CTL_PTMR_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY09_FUNC_CTL_PTMR_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY09_FUNC_CTL_SOC_PY_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY09_FUNC_CTL_SOC_PY_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY10_FUNC_CTL function mux definitions */ +#define IOC_PY10_FUNC_CTL_PGPIO_Y_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY10_FUNC_CTL_PGPIO_Y_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY10_FUNC_CTL_VAD_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY10_FUNC_CTL_VAD_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY10_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY10_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY10_FUNC_CTL_SOC_PY_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY10_FUNC_CTL_SOC_PY_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY11_FUNC_CTL function mux definitions */ +#define IOC_PY11_FUNC_CTL_PGPIO_Y_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY11_FUNC_CTL_PGPIO_Y_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY11_FUNC_CTL_VAD_DAT IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY11_FUNC_CTL_VAD_DAT IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY11_FUNC_CTL_PTMR_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY11_FUNC_CTL_PTMR_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY11_FUNC_CTL_SOC_PY_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY11_FUNC_CTL_SOC_PY_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #endif /* HPM_PMIC_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ppor_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ppor_drv.h index b1eb6e6ac53..687508cc684 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ppor_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ppor_drv.h @@ -11,15 +11,7 @@ typedef enum { ppor_reset_brownout = 1 << 0, - ppor_reset_temperature = 1 << 1, - ppor_reset_pin = 1 << 2, ppor_reset_debug = 1 << 4, - ppor_reset_security_violation = 1 << 5, - ppor_reset_jtag = 1 << 6, - ppor_reset_cpu0_lockup = 1 << 8, - ppor_reset_cpu1_lockup = 1 << 9, - ppor_reset_cpu0_request = 1 << 10, - ppor_reset_cpu1_request = 1 << 11, ppor_reset_wdog0 = 1 << 16, ppor_reset_wdog1 = 1 << 17, ppor_reset_wdog2 = 1 << 18, @@ -92,7 +84,31 @@ static inline uint32_t ppor_reset_get_flags(PPOR_Type *ptr) */ static inline void ppor_reset_clear_flags(PPOR_Type *ptr, uint32_t mask) { - ptr->RESET_FLAG |= mask; + ptr->RESET_FLAG = mask; +} + +/* + * get reset hold + */ +static inline uint32_t ppor_reset_get_hold(PPOR_Type *ptr) +{ + return ptr->RESET_HOLD; +} + +/* + * set reset hold + */ +static inline void ppor_reset_set_hold_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_HOLD |= mask; +} + +/* + * clear reset hold + */ +static inline void ppor_reset_clear_hold_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_HOLD &= ~mask; } /* @@ -100,7 +116,7 @@ static inline void ppor_reset_clear_flags(PPOR_Type *ptr, uint32_t mask) */ static inline void ppor_reset_set_cold_reset_enable(PPOR_Type *ptr, uint32_t mask) { - ptr->RESET_COLD = mask; + ptr->RESET_COLD |= mask; } /* @@ -116,7 +132,7 @@ static inline void ppor_reset_clear_cold_reset_enable(PPOR_Type *ptr, uint32_t m */ static inline void ppor_reset_set_hot_reset_enable(PPOR_Type *ptr, uint32_t mask) { - ptr->RESET_HOT = mask; + ptr->RESET_HOT |= mask; } /* diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ppor_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ppor_regs.h index 21cb6fc2370..7ce378b07da 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ppor_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ppor_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_romapi.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_romapi.h index 0dab53b250c..5f226b0847e 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_romapi.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_romapi.h @@ -304,7 +304,7 @@ typedef struct { /**< Bootloader API table: copyright string address */ const char *copyright; /**< Bootloader API table: run_bootloader API */ - const hpm_stat_t (*run_bootloader)(void *arg); + hpm_stat_t (*run_bootloader)(void *arg); /**< Bootloader API table: otp driver interface address */ const otp_driver_interface_t *otp_driver_if; /**< Bootloader API table: xpi driver interface address */ @@ -685,7 +685,7 @@ static inline bool rom_xpi_nor_exip_region_config(XPI_Type *base, uint32_t index /** * @brief Disable EXiP Feature on specified EXiP Region - * @@param [in] base XPI base address + * @param [in] base XPI base address * @param [in] index EXiP Region index */ ATTR_RAMFUNC @@ -705,7 +705,7 @@ static inline void rom_xpi_nor_exip_region_disable(XPI_Type *base, uint32_t inde /** * @brief Enable global EXiP logic - * @@param [in] base XPI base address + * @param [in] base XPI base address */ ATTR_RAMFUNC static inline void rom_xpi_nor_exip_enable(XPI_Type *base) @@ -722,7 +722,7 @@ static inline void rom_xpi_nor_exip_enable(XPI_Type *base) /** * @brief Disable global EXiP logic - * @@param [in] base XPI base address + * @param [in] base XPI base address */ ATTR_RAMFUNC static inline void rom_xpi_nor_exip_disable(XPI_Type *base) @@ -993,6 +993,7 @@ static inline hpm_stat_t rom_sm4_crypt_ecb(sm4_context_t *ctx, uint32_t mode, ui * @param [in] ctx SM4 context * @param [in] mode SM4 operation: 1 - ENCRYPT, 0 - DECRYPT * @param [in] length Data length for SM4 encryption/decryption + * @param [in] iv The initial vector for SM4 CBC crypto operation * @param [in] input Input data * @param [out] output Output data * @return API execution status diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sdxc_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sdxc_soc_drv.h index 6fffe293095..23a42ab3bf5 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sdxc_soc_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sdxc_soc_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -53,14 +53,58 @@ static inline bool sdxc_is_inverse_clock_enabled(SDXC_Type *base) static inline void sdxc_select_cardclk_delay_source(SDXC_Type *base, bool delay_from_pad) { - + (void) base; + (void) delay_from_pad; } static inline void sdxc_set_cardclk_delay_chain(SDXC_Type *base, uint32_t delay_chain) { + (void) base; + volatile uint32_t *reg = (base == HPM_SDXC0) ? &HPM_CONCTL->CTRL4 : &HPM_CONCTL->CTRL5; + *reg = (*reg & ~CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_MASK) | + CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_SET(delay_chain); +} + +static inline void sdxc_set_data_strobe_delay(SDXC_Type *base, uint32_t num_delaycells) +{ + (void) base; + volatile uint32_t *reg = (base == HPM_SDXC0) ? &HPM_CONCTL->CTRL4 : &HPM_CONCTL->CTRL5; + *reg = (*reg & ~CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_MASK) | + CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_SET(num_delaycells); + *reg |= CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_MASK; +} + + +static inline uint32_t sdxc_get_default_strobe_delay(SDXC_Type *base) +{ + (void) base; + return 0; +} + +static inline void sdxc_set_rxclk_delay_chain(SDXC_Type *base, uint32_t num_delaycells) +{ + volatile uint32_t *reg = (base == HPM_SDXC0) ? &HPM_CONCTL->CTRL4 : &HPM_CONCTL->CTRL5; + *reg = (*reg & ~CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_MASK) | + CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_SET(num_delaycells); + + *reg |= CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_MASK; +} +static inline uint32_t sdxc_get_default_cardclk_delay_chain(SDXC_Type *base, uint32_t clock_freq) +{ + (void) base; + uint32_t num_delaycells = 1; + if (clock_freq <= 52000000) { + num_delaycells = 13; + } + return num_delaycells; } +static inline bool sdxc_is_ddr50_supported(SDXC_Type *base) +{ + (void) base; + return false; +} #if defined(__cplusplus) } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ses_reg.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ses_reg.xml index 8cb241610e2..c85f2eec268 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ses_reg.xml +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ses_reg.xml @@ -4856,6 +4856,111 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -4916,6 +5021,106 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -4976,6 +5181,106 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -5036,6 +5341,106 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -5346,8 +5751,8 @@ - - + + @@ -5357,8 +5762,8 @@ - - + + @@ -5368,8 +5773,8 @@ - - + + @@ -5379,8 +5784,8 @@ - - + + @@ -5390,8 +5795,8 @@ - - + + @@ -5401,8 +5806,8 @@ - - + + @@ -5412,8 +5817,8 @@ - - + + @@ -5423,8 +5828,8 @@ - - + + @@ -5434,8 +5839,8 @@ - - + + @@ -5445,8 +5850,8 @@ - - + + @@ -5456,8 +5861,8 @@ - - + + @@ -5467,8 +5872,8 @@ - - + + @@ -5478,8 +5883,8 @@ - - + + @@ -5489,8 +5894,8 @@ - - + + @@ -5500,8 +5905,8 @@ - - + + @@ -5511,8 +5916,8 @@ - - + + @@ -5522,8 +5927,8 @@ - - + + @@ -5533,8 +5938,8 @@ - - + + @@ -5544,8 +5949,8 @@ - - + + @@ -6010,8 +6415,8 @@ - - + + @@ -6021,8 +6426,8 @@ - - + + @@ -6032,8 +6437,8 @@ - - + + @@ -6043,8 +6448,8 @@ - - + + @@ -6054,8 +6459,8 @@ - - + + @@ -6065,8 +6470,8 @@ - - + + @@ -6076,8 +6481,8 @@ - - + + @@ -6087,8 +6492,8 @@ - - + + @@ -6098,8 +6503,8 @@ - - + + @@ -6109,8 +6514,8 @@ - - + + @@ -6120,8 +6525,8 @@ - - + + @@ -6131,8 +6536,8 @@ - - + + @@ -6142,8 +6547,8 @@ - - + + @@ -6153,8 +6558,8 @@ - - + + @@ -6164,8 +6569,8 @@ - - + + @@ -6175,8 +6580,8 @@ - - + + @@ -6186,8 +6591,8 @@ - - + + @@ -6197,8 +6602,8 @@ - - + + @@ -6208,8 +6613,8 @@ - - + + @@ -6674,8 +7079,8 @@ - - + + @@ -6685,8 +7090,8 @@ - - + + @@ -6696,8 +7101,8 @@ - - + + @@ -6707,8 +7112,8 @@ - - + + @@ -6718,8 +7123,8 @@ - - + + @@ -6729,8 +7134,8 @@ - - + + @@ -6740,8 +7145,8 @@ - - + + @@ -6751,8 +7156,8 @@ - - + + @@ -6762,8 +7167,8 @@ - - + + @@ -6773,8 +7178,8 @@ - - + + @@ -6784,8 +7189,8 @@ - - + + @@ -6795,8 +7200,8 @@ - - + + @@ -6806,8 +7211,8 @@ - - + + @@ -6817,8 +7222,8 @@ - - + + @@ -6828,8 +7233,8 @@ - - + + @@ -6839,8 +7244,8 @@ - - + + @@ -6850,8 +7255,8 @@ - - + + @@ -6861,8 +7266,8 @@ - - + + @@ -6872,8 +7277,8 @@ - - + + @@ -7216,9 +7621,6 @@ - - - @@ -7416,7 +7818,6 @@ - @@ -7431,7 +7832,7 @@ - + @@ -7445,7 +7846,7 @@ - + @@ -7692,7 +8093,6 @@ - @@ -7785,7 +8185,6 @@ - @@ -7878,7 +8277,6 @@ - @@ -7971,7 +8369,6 @@ - @@ -8064,7 +8461,6 @@ - @@ -8128,10 +8524,12 @@ + + + - @@ -8195,10 +8593,12 @@ + + + - @@ -8262,10 +8662,12 @@ + + + - @@ -8329,10 +8731,12 @@ + + + - @@ -8396,10 +8800,12 @@ + + + - @@ -8463,10 +8869,12 @@ + + + - @@ -8530,10 +8938,12 @@ + + + - @@ -8597,10 +9007,12 @@ + + + - @@ -8664,10 +9076,12 @@ + + + - @@ -8731,10 +9145,12 @@ + + + - @@ -8798,10 +9214,12 @@ + + + - @@ -8865,10 +9283,12 @@ + + + - @@ -8932,10 +9352,12 @@ + + + - @@ -8999,10 +9421,12 @@ + + + - @@ -9066,10 +9490,12 @@ + + + - @@ -9133,10 +9559,12 @@ + + + - @@ -9200,6 +9628,9 @@ + + + @@ -10335,20 +10766,16 @@ - - - - @@ -10361,7 +10788,6 @@ - @@ -10381,20 +10807,16 @@ - - - - @@ -10407,7 +10829,6 @@ - @@ -10427,20 +10848,16 @@ - - - - @@ -10453,7 +10870,6 @@ - @@ -10473,20 +10889,16 @@ - - - - @@ -10499,7 +10911,6 @@ - @@ -10522,7 +10933,6 @@ - @@ -10568,7 +10978,6 @@ - @@ -10631,6 +11040,12 @@ + + + + + + @@ -11394,48 +11809,33 @@ - - - - - - - - - - - - - - - @@ -11541,7 +11941,6 @@ - @@ -11569,17 +11968,14 @@ - - - @@ -11606,7 +12002,6 @@ - @@ -11626,10 +12021,7 @@ - - - @@ -11659,7 +12051,6 @@ - @@ -11687,17 +12078,14 @@ - - - @@ -11724,7 +12112,6 @@ - @@ -11744,10 +12131,7 @@ - - - @@ -11777,7 +12161,6 @@ - @@ -11805,17 +12188,14 @@ - - - @@ -11842,7 +12222,6 @@ - @@ -11862,10 +12241,7 @@ - - - @@ -11895,7 +12271,6 @@ - @@ -11923,17 +12298,14 @@ - - - @@ -11960,7 +12332,6 @@ - @@ -11980,10 +12351,7 @@ - - - @@ -12118,12 +12486,10 @@ - - @@ -12276,196 +12642,124 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -12569,7 +12863,6 @@ - @@ -12646,7 +12939,6 @@ - @@ -12745,145 +13037,121 @@ - - - - - - - - - - - - - - - - - - - - - - - - @@ -12893,12 +13161,10 @@ - - @@ -13051,196 +13317,124 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -13344,7 +13538,6 @@ - @@ -13421,7 +13614,6 @@ - @@ -13520,145 +13712,121 @@ - - - - - - - - - - - - - - - - - - - - - - - - @@ -13668,12 +13836,10 @@ - - @@ -13826,196 +13992,124 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -14119,7 +14213,6 @@ - @@ -14196,7 +14289,6 @@ - @@ -14295,145 +14387,121 @@ - - - - - - - - - - - - - - - - - - - - - - - - @@ -14443,12 +14511,10 @@ - - @@ -14601,196 +14667,124 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -14894,7 +14888,6 @@ - @@ -14971,7 +14964,6 @@ - @@ -15070,160 +15062,131 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -15231,7 +15194,6 @@ - @@ -15239,10 +15201,6 @@ - - - - @@ -15252,10 +15210,6 @@ - - - - @@ -15265,10 +15219,6 @@ - - - - @@ -15278,10 +15228,6 @@ - - - - @@ -15291,10 +15237,6 @@ - - - - @@ -15303,8 +15245,6 @@ - - @@ -15321,8 +15261,6 @@ - - @@ -15339,8 +15277,6 @@ - - @@ -15357,8 +15293,6 @@ - - @@ -15393,16 +15327,11 @@ - - - - - @@ -15410,7 +15339,6 @@ - @@ -15418,10 +15346,6 @@ - - - - @@ -15431,10 +15355,6 @@ - - - - @@ -15444,10 +15364,6 @@ - - - - @@ -15457,10 +15373,6 @@ - - - - @@ -15470,10 +15382,6 @@ - - - - @@ -15482,8 +15390,6 @@ - - @@ -15500,8 +15406,6 @@ - - @@ -15518,8 +15422,6 @@ - - @@ -15536,8 +15438,6 @@ - - @@ -15572,16 +15472,11 @@ - - - - - @@ -15589,7 +15484,6 @@ - @@ -15597,10 +15491,6 @@ - - - - @@ -15610,10 +15500,6 @@ - - - - @@ -15623,10 +15509,6 @@ - - - - @@ -15636,10 +15518,6 @@ - - - - @@ -15649,10 +15527,6 @@ - - - - @@ -15661,8 +15535,6 @@ - - @@ -15679,8 +15551,6 @@ - - @@ -15697,8 +15567,6 @@ - - @@ -15715,8 +15583,6 @@ - - @@ -15751,16 +15617,11 @@ - - - - - @@ -15768,7 +15629,6 @@ - @@ -15776,10 +15636,6 @@ - - - - @@ -15789,10 +15645,6 @@ - - - - @@ -15802,10 +15654,6 @@ - - - - @@ -15815,10 +15663,6 @@ - - - - @@ -15828,10 +15672,6 @@ - - - - @@ -15840,8 +15680,6 @@ - - @@ -15858,8 +15696,6 @@ - - @@ -15876,8 +15712,6 @@ - - @@ -15894,8 +15728,6 @@ - - @@ -15942,7 +15774,6 @@ - @@ -16099,7 +15930,6 @@ - @@ -16256,7 +16086,6 @@ - @@ -16413,7 +16242,6 @@ - @@ -18683,25 +18511,17 @@ - - - - - - - - @@ -18718,20 +18538,16 @@ - - - - @@ -18741,14 +18557,11 @@ - - - @@ -18761,7 +18574,6 @@ - @@ -18770,27 +18582,20 @@ - - - - - - - @@ -18800,14 +18605,11 @@ - - - @@ -18820,7 +18622,6 @@ - @@ -18829,27 +18630,20 @@ - - - - - - - @@ -18859,14 +18653,11 @@ - - - @@ -18879,7 +18670,6 @@ - @@ -18888,27 +18678,20 @@ - - - - - - - @@ -18918,14 +18701,11 @@ - - - @@ -18938,7 +18718,6 @@ - @@ -18947,27 +18726,20 @@ - - - - - - - @@ -18977,14 +18749,11 @@ - - - @@ -18997,7 +18766,6 @@ - @@ -19006,27 +18774,20 @@ - - - - - - - @@ -19036,14 +18797,11 @@ - - - @@ -19056,7 +18814,6 @@ - @@ -19065,27 +18822,20 @@ - - - - - - - @@ -19095,14 +18845,11 @@ - - - @@ -19115,7 +18862,6 @@ - @@ -19124,27 +18870,20 @@ - - - - - - - @@ -19154,14 +18893,11 @@ - - - @@ -19174,7 +18910,6 @@ - @@ -19183,32 +18918,25 @@ - - - - - - - @@ -19220,59 +18948,44 @@ - - - - - - - - - - - - - - - @@ -19281,1085 +18994,812 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -20371,59 +19811,44 @@ - - - - - - - - - - - - - - - @@ -20432,1117 +19857,840 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + @@ -21670,7 +20818,6 @@ - @@ -21694,7 +20841,6 @@ - @@ -21724,7 +20870,6 @@ - @@ -21754,14 +20899,11 @@ - - - @@ -21772,7 +20914,6 @@ - @@ -21785,11 +20926,9 @@ - - @@ -21804,91 +20943,70 @@ - - - - - - - - - - - - - - - - - - - - - @@ -22321,54 +21439,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -23067,54 +22137,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -23390,7 +22412,6 @@ - @@ -23433,7 +22454,6 @@ - @@ -23476,7 +22496,6 @@ - @@ -23519,7 +22538,6 @@ - @@ -23561,7 +22579,6 @@ - @@ -23580,7 +22597,6 @@ - @@ -23605,7 +22621,6 @@ - @@ -23648,7 +22663,6 @@ - @@ -23691,7 +22705,6 @@ - @@ -23734,7 +22747,6 @@ - @@ -23776,7 +22788,6 @@ - @@ -23795,7 +22806,6 @@ - @@ -23820,7 +22830,6 @@ - @@ -23863,7 +22872,6 @@ - @@ -23906,7 +22914,6 @@ - @@ -23949,7 +22956,6 @@ - @@ -23991,7 +22997,6 @@ - @@ -24010,7 +23015,6 @@ - @@ -24035,7 +23039,6 @@ - @@ -24078,7 +23081,6 @@ - @@ -24121,7 +23123,6 @@ - @@ -24164,7 +23165,6 @@ - @@ -24206,7 +23206,6 @@ - @@ -24225,7 +23224,6 @@ - @@ -24250,7 +23248,6 @@ - @@ -24293,7 +23290,6 @@ - @@ -24336,7 +23332,6 @@ - @@ -24379,7 +23374,6 @@ - @@ -24421,7 +23415,6 @@ - @@ -24440,7 +23433,6 @@ - @@ -24465,7 +23457,6 @@ - @@ -24508,7 +23499,6 @@ - @@ -24551,7 +23541,6 @@ - @@ -24594,7 +23583,6 @@ - @@ -24636,7 +23624,6 @@ - @@ -24655,7 +23642,6 @@ - @@ -24680,7 +23666,6 @@ - @@ -24723,7 +23708,6 @@ - @@ -24766,7 +23750,6 @@ - @@ -24809,7 +23792,6 @@ - @@ -24851,7 +23833,6 @@ - @@ -24870,7 +23851,6 @@ - @@ -24895,7 +23875,6 @@ - @@ -24938,7 +23917,6 @@ - @@ -24981,7 +23959,6 @@ - @@ -25024,7 +24001,6 @@ - @@ -25066,7 +24042,6 @@ - @@ -25085,7 +24060,6 @@ - @@ -25110,7 +24084,6 @@ - @@ -25153,7 +24126,6 @@ - @@ -25196,7 +24168,6 @@ - @@ -25239,7 +24210,6 @@ - @@ -25281,7 +24251,6 @@ - @@ -25300,7 +24269,6 @@ - @@ -25325,7 +24293,6 @@ - @@ -25368,7 +24335,6 @@ - @@ -25411,7 +24377,6 @@ - @@ -25454,7 +24419,6 @@ - @@ -25496,7 +24460,6 @@ - @@ -25515,7 +24478,6 @@ - @@ -25540,7 +24502,6 @@ - @@ -25583,7 +24544,6 @@ - @@ -25626,7 +24586,6 @@ - @@ -25669,7 +24628,6 @@ - @@ -25711,7 +24669,6 @@ - @@ -25730,7 +24687,6 @@ - @@ -25850,12 +24806,12 @@ - - + + - - + + @@ -25901,23 +24857,23 @@ - + - - + + - - + + - - + + - - + + @@ -26136,12 +25092,12 @@ - - + + - - + + @@ -26187,23 +25143,23 @@ - + - - + + - - + + - - + + - - + + @@ -26730,12 +25686,6 @@ - - - - - - @@ -27173,12 +26123,6 @@ - - - - - - @@ -27212,7 +26156,6 @@ - @@ -27255,11 +26198,9 @@ - - @@ -27272,7 +26213,6 @@ - @@ -27290,15 +26230,12 @@ - - - @@ -27307,15 +26244,12 @@ - - - @@ -27324,17 +26258,14 @@ - - - @@ -27347,7 +26278,6 @@ - @@ -27365,15 +26295,12 @@ - - - @@ -27382,15 +26309,12 @@ - - - @@ -27399,17 +26323,14 @@ - - - @@ -27422,7 +26343,6 @@ - @@ -27440,15 +26360,12 @@ - - - @@ -27457,15 +26374,12 @@ - - - @@ -27474,17 +26388,14 @@ - - - @@ -27497,7 +26408,6 @@ - @@ -27515,15 +26425,12 @@ - - - @@ -27532,15 +26439,12 @@ - - - @@ -27549,7 +26453,6 @@ - @@ -27559,13 +26462,11 @@ - - @@ -27573,36 +26474,27 @@ - - - - - - - - - @@ -27611,9 +26503,7 @@ - - @@ -27663,14 +26553,12 @@ - - @@ -39602,7 +38490,6 @@ - @@ -39640,7 +38527,6 @@ - @@ -40220,29 +39106,29 @@ - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + @@ -40537,4 +39423,4 @@ - \ No newline at end of file + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ses_riscv_cpu_regs.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ses_riscv_cpu_regs.xml index de6e896482d..9e30fbc73a7 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ses_riscv_cpu_regs.xml +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ses_riscv_cpu_regs.xml @@ -767,4 +767,4 @@ - \ No newline at end of file + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_soc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_soc.h index 7c5e148244d..3f1b0a44686 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_soc.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_soc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -11,133 +11,133 @@ /* List of external IRQs */ -#define IRQn_GPIO0_A 1 /* GPIO0_A IRQ */ -#define IRQn_GPIO0_B 2 /* GPIO0_B IRQ */ -#define IRQn_GPIO0_C 3 /* GPIO0_C IRQ */ -#define IRQn_GPIO0_D 4 /* GPIO0_D IRQ */ -#define IRQn_GPIO0_E 5 /* GPIO0_E IRQ */ -#define IRQn_GPIO0_F 6 /* GPIO0_F IRQ */ -#define IRQn_GPIO0_X 7 /* GPIO0_X IRQ */ -#define IRQn_GPIO0_Y 8 /* GPIO0_Y IRQ */ -#define IRQn_GPIO0_Z 9 /* GPIO0_Z IRQ */ -#define IRQn_GPIO1_A 10 /* GPIO1_A IRQ */ -#define IRQn_GPIO1_B 11 /* GPIO1_B IRQ */ -#define IRQn_GPIO1_C 12 /* GPIO1_C IRQ */ -#define IRQn_GPIO1_D 13 /* GPIO1_D IRQ */ -#define IRQn_GPIO1_E 14 /* GPIO1_E IRQ */ -#define IRQn_GPIO1_F 15 /* GPIO1_F IRQ */ -#define IRQn_GPIO1_X 16 /* GPIO1_X IRQ */ -#define IRQn_GPIO1_Y 17 /* GPIO1_Y IRQ */ -#define IRQn_GPIO1_Z 18 /* GPIO1_Z IRQ */ -#define IRQn_ADC0 19 /* ADC0 IRQ */ -#define IRQn_ADC1 20 /* ADC1 IRQ */ -#define IRQn_ADC2 21 /* ADC2 IRQ */ -#define IRQn_ADC3 22 /* ADC3 IRQ */ -#define IRQn_ACMP_0 23 /* ACMP[0] IRQ */ -#define IRQn_ACMP_1 24 /* ACMP[1] IRQ */ -#define IRQn_ACMP_2 25 /* ACMP[2] IRQ */ -#define IRQn_ACMP_3 26 /* ACMP[3] IRQ */ -#define IRQn_SPI0 27 /* SPI0 IRQ */ -#define IRQn_SPI1 28 /* SPI1 IRQ */ -#define IRQn_SPI2 29 /* SPI2 IRQ */ -#define IRQn_SPI3 30 /* SPI3 IRQ */ -#define IRQn_UART0 31 /* UART0 IRQ */ -#define IRQn_UART1 32 /* UART1 IRQ */ -#define IRQn_UART2 33 /* UART2 IRQ */ -#define IRQn_UART3 34 /* UART3 IRQ */ -#define IRQn_UART4 35 /* UART4 IRQ */ -#define IRQn_UART5 36 /* UART5 IRQ */ -#define IRQn_UART6 37 /* UART6 IRQ */ -#define IRQn_UART7 38 /* UART7 IRQ */ -#define IRQn_UART8 39 /* UART8 IRQ */ -#define IRQn_UART9 40 /* UART9 IRQ */ -#define IRQn_UART10 41 /* UART10 IRQ */ -#define IRQn_UART11 42 /* UART11 IRQ */ -#define IRQn_UART12 43 /* UART12 IRQ */ -#define IRQn_UART13 44 /* UART13 IRQ */ -#define IRQn_UART14 45 /* UART14 IRQ */ -#define IRQn_UART15 46 /* UART15 IRQ */ -#define IRQn_CAN0 47 /* CAN0 IRQ */ -#define IRQn_CAN1 48 /* CAN1 IRQ */ -#define IRQn_CAN2 49 /* CAN2 IRQ */ -#define IRQn_CAN3 50 /* CAN3 IRQ */ -#define IRQn_PTPC 51 /* PTPC IRQ */ -#define IRQn_WDG0 52 /* WDG0 IRQ */ -#define IRQn_WDG1 53 /* WDG1 IRQ */ -#define IRQn_WDG2 54 /* WDG2 IRQ */ -#define IRQn_WDG3 55 /* WDG3 IRQ */ -#define IRQn_MBX0A 56 /* MBX0A IRQ */ -#define IRQn_MBX0B 57 /* MBX0B IRQ */ -#define IRQn_MBX1A 58 /* MBX1A IRQ */ -#define IRQn_MBX1B 59 /* MBX1B IRQ */ -#define IRQn_GPTMR0 60 /* GPTMR0 IRQ */ -#define IRQn_GPTMR1 61 /* GPTMR1 IRQ */ -#define IRQn_GPTMR2 62 /* GPTMR2 IRQ */ -#define IRQn_GPTMR3 63 /* GPTMR3 IRQ */ -#define IRQn_GPTMR4 64 /* GPTMR4 IRQ */ -#define IRQn_GPTMR5 65 /* GPTMR5 IRQ */ -#define IRQn_GPTMR6 66 /* GPTMR6 IRQ */ -#define IRQn_GPTMR7 67 /* GPTMR7 IRQ */ -#define IRQn_I2C0 68 /* I2C0 IRQ */ -#define IRQn_I2C1 69 /* I2C1 IRQ */ -#define IRQn_I2C2 70 /* I2C2 IRQ */ -#define IRQn_I2C3 71 /* I2C3 IRQ */ -#define IRQn_PWM0 72 /* PWM0 IRQ */ -#define IRQn_HALL0 73 /* HALL0 IRQ */ -#define IRQn_QEI0 74 /* QEI0 IRQ */ -#define IRQn_PWM1 75 /* PWM1 IRQ */ -#define IRQn_HALL1 76 /* HALL1 IRQ */ -#define IRQn_QEI1 77 /* QEI1 IRQ */ -#define IRQn_PWM2 78 /* PWM2 IRQ */ -#define IRQn_HALL2 79 /* HALL2 IRQ */ -#define IRQn_QEI2 80 /* QEI2 IRQ */ -#define IRQn_PWM3 81 /* PWM3 IRQ */ -#define IRQn_HALL3 82 /* HALL3 IRQ */ -#define IRQn_QEI3 83 /* QEI3 IRQ */ -#define IRQn_SDP 84 /* SDP IRQ */ -#define IRQn_XPI0 85 /* XPI0 IRQ */ -#define IRQn_XPI1 86 /* XPI1 IRQ */ -#define IRQn_XDMA 87 /* XDMA IRQ */ -#define IRQn_HDMA 88 /* HDMA IRQ */ -#define IRQn_FEMC 89 /* FEMC IRQ */ -#define IRQn_RNG 90 /* RNG IRQ */ -#define IRQn_I2S0 91 /* I2S0 IRQ */ -#define IRQn_I2S1 92 /* I2S1 IRQ */ -#define IRQn_I2S2 93 /* I2S2 IRQ */ -#define IRQn_I2S3 94 /* I2S3 IRQ */ -#define IRQn_DAO 95 /* DAO IRQ */ -#define IRQn_PDM 96 /* PDM IRQ */ -#define IRQn_CAM0 97 /* CAM0 IRQ */ -#define IRQn_CAM1 98 /* CAM1 IRQ */ -#define IRQn_LCDC_D0 99 /* LCDC_D0 IRQ */ -#define IRQn_LCDC_D1 100 /* LCDC_D1 IRQ */ -#define IRQn_PDMA_D0 101 /* PDMA_D0 IRQ */ -#define IRQn_PDMA_D1 102 /* PDMA_D1 IRQ */ -#define IRQn_JPEG 103 /* JPEG IRQ */ -#define IRQn_NTMR0 104 /* NTMR0 IRQ */ -#define IRQn_NTMR1 105 /* NTMR1 IRQ */ -#define IRQn_USB0 106 /* USB0 IRQ */ -#define IRQn_USB1 107 /* USB1 IRQ */ -#define IRQn_ENET0 108 /* ENET0 IRQ */ -#define IRQn_ENET1 109 /* ENET1 IRQ */ -#define IRQn_SDXC0 110 /* SDXC0 IRQ */ -#define IRQn_SDXC1 111 /* SDXC1 IRQ */ -#define IRQn_PSEC 112 /* PSEC IRQ */ -#define IRQn_PGPIO 113 /* PGPIO IRQ */ -#define IRQn_PWDG 114 /* PWDG IRQ */ -#define IRQn_PTMR 115 /* PTMR IRQ */ -#define IRQn_PUART 116 /* PUART IRQ */ -#define IRQn_VAD 117 /* VAD IRQ */ -#define IRQn_FUSE 118 /* FUSE IRQ */ -#define IRQn_SECMON 119 /* SECMON IRQ */ -#define IRQn_RTC 120 /* RTC IRQ */ -#define IRQn_BUTN 121 /* BUTN IRQ */ -#define IRQn_BGPIO 122 /* BGPIO IRQ */ -#define IRQn_BVIO 123 /* BVIO IRQ */ -#define IRQn_BROWNOUT 124 /* BROWNOUT IRQ */ -#define IRQn_SYSCTL 125 /* SYSCTL IRQ */ -#define IRQn_DEBUG_0 126 /* DEBUG[0] IRQ */ -#define IRQn_DEBUG_1 127 /* DEBUG[1] IRQ */ +#define IRQn_GPIO0_A 1 /* GPIO0_A IRQ */ +#define IRQn_GPIO0_B 2 /* GPIO0_B IRQ */ +#define IRQn_GPIO0_C 3 /* GPIO0_C IRQ */ +#define IRQn_GPIO0_D 4 /* GPIO0_D IRQ */ +#define IRQn_GPIO0_E 5 /* GPIO0_E IRQ */ +#define IRQn_GPIO0_F 6 /* GPIO0_F IRQ */ +#define IRQn_GPIO0_X 7 /* GPIO0_X IRQ */ +#define IRQn_GPIO0_Y 8 /* GPIO0_Y IRQ */ +#define IRQn_GPIO0_Z 9 /* GPIO0_Z IRQ */ +#define IRQn_GPIO1_A 10 /* GPIO1_A IRQ */ +#define IRQn_GPIO1_B 11 /* GPIO1_B IRQ */ +#define IRQn_GPIO1_C 12 /* GPIO1_C IRQ */ +#define IRQn_GPIO1_D 13 /* GPIO1_D IRQ */ +#define IRQn_GPIO1_E 14 /* GPIO1_E IRQ */ +#define IRQn_GPIO1_F 15 /* GPIO1_F IRQ */ +#define IRQn_GPIO1_X 16 /* GPIO1_X IRQ */ +#define IRQn_GPIO1_Y 17 /* GPIO1_Y IRQ */ +#define IRQn_GPIO1_Z 18 /* GPIO1_Z IRQ */ +#define IRQn_ADC0 19 /* ADC0 IRQ */ +#define IRQn_ADC1 20 /* ADC1 IRQ */ +#define IRQn_ADC2 21 /* ADC2 IRQ */ +#define IRQn_ADC3 22 /* ADC3 IRQ */ +#define IRQn_ACMP_0 23 /* ACMP[0] IRQ */ +#define IRQn_ACMP_1 24 /* ACMP[1] IRQ */ +#define IRQn_ACMP_2 25 /* ACMP[2] IRQ */ +#define IRQn_ACMP_3 26 /* ACMP[3] IRQ */ +#define IRQn_SPI0 27 /* SPI0 IRQ */ +#define IRQn_SPI1 28 /* SPI1 IRQ */ +#define IRQn_SPI2 29 /* SPI2 IRQ */ +#define IRQn_SPI3 30 /* SPI3 IRQ */ +#define IRQn_UART0 31 /* UART0 IRQ */ +#define IRQn_UART1 32 /* UART1 IRQ */ +#define IRQn_UART2 33 /* UART2 IRQ */ +#define IRQn_UART3 34 /* UART3 IRQ */ +#define IRQn_UART4 35 /* UART4 IRQ */ +#define IRQn_UART5 36 /* UART5 IRQ */ +#define IRQn_UART6 37 /* UART6 IRQ */ +#define IRQn_UART7 38 /* UART7 IRQ */ +#define IRQn_UART8 39 /* UART8 IRQ */ +#define IRQn_UART9 40 /* UART9 IRQ */ +#define IRQn_UART10 41 /* UART10 IRQ */ +#define IRQn_UART11 42 /* UART11 IRQ */ +#define IRQn_UART12 43 /* UART12 IRQ */ +#define IRQn_UART13 44 /* UART13 IRQ */ +#define IRQn_UART14 45 /* UART14 IRQ */ +#define IRQn_UART15 46 /* UART15 IRQ */ +#define IRQn_CAN0 47 /* CAN0 IRQ */ +#define IRQn_CAN1 48 /* CAN1 IRQ */ +#define IRQn_CAN2 49 /* CAN2 IRQ */ +#define IRQn_CAN3 50 /* CAN3 IRQ */ +#define IRQn_PTPC 51 /* PTPC IRQ */ +#define IRQn_WDG0 52 /* WDG0 IRQ */ +#define IRQn_WDG1 53 /* WDG1 IRQ */ +#define IRQn_WDG2 54 /* WDG2 IRQ */ +#define IRQn_WDG3 55 /* WDG3 IRQ */ +#define IRQn_MBX0A 56 /* MBX0A IRQ */ +#define IRQn_MBX0B 57 /* MBX0B IRQ */ +#define IRQn_MBX1A 58 /* MBX1A IRQ */ +#define IRQn_MBX1B 59 /* MBX1B IRQ */ +#define IRQn_GPTMR0 60 /* GPTMR0 IRQ */ +#define IRQn_GPTMR1 61 /* GPTMR1 IRQ */ +#define IRQn_GPTMR2 62 /* GPTMR2 IRQ */ +#define IRQn_GPTMR3 63 /* GPTMR3 IRQ */ +#define IRQn_GPTMR4 64 /* GPTMR4 IRQ */ +#define IRQn_GPTMR5 65 /* GPTMR5 IRQ */ +#define IRQn_GPTMR6 66 /* GPTMR6 IRQ */ +#define IRQn_GPTMR7 67 /* GPTMR7 IRQ */ +#define IRQn_I2C0 68 /* I2C0 IRQ */ +#define IRQn_I2C1 69 /* I2C1 IRQ */ +#define IRQn_I2C2 70 /* I2C2 IRQ */ +#define IRQn_I2C3 71 /* I2C3 IRQ */ +#define IRQn_PWM0 72 /* PWM0 IRQ */ +#define IRQn_HALL0 73 /* HALL0 IRQ */ +#define IRQn_QEI0 74 /* QEI0 IRQ */ +#define IRQn_PWM1 75 /* PWM1 IRQ */ +#define IRQn_HALL1 76 /* HALL1 IRQ */ +#define IRQn_QEI1 77 /* QEI1 IRQ */ +#define IRQn_PWM2 78 /* PWM2 IRQ */ +#define IRQn_HALL2 79 /* HALL2 IRQ */ +#define IRQn_QEI2 80 /* QEI2 IRQ */ +#define IRQn_PWM3 81 /* PWM3 IRQ */ +#define IRQn_HALL3 82 /* HALL3 IRQ */ +#define IRQn_QEI3 83 /* QEI3 IRQ */ +#define IRQn_SDP 84 /* SDP IRQ */ +#define IRQn_XPI0 85 /* XPI0 IRQ */ +#define IRQn_XPI1 86 /* XPI1 IRQ */ +#define IRQn_XDMA 87 /* XDMA IRQ */ +#define IRQn_HDMA 88 /* HDMA IRQ */ +#define IRQn_FEMC 89 /* FEMC IRQ */ +#define IRQn_RNG 90 /* RNG IRQ */ +#define IRQn_I2S0 91 /* I2S0 IRQ */ +#define IRQn_I2S1 92 /* I2S1 IRQ */ +#define IRQn_I2S2 93 /* I2S2 IRQ */ +#define IRQn_I2S3 94 /* I2S3 IRQ */ +#define IRQn_DAO 95 /* DAO IRQ */ +#define IRQn_PDM 96 /* PDM IRQ */ +#define IRQn_CAM0 97 /* CAM0 IRQ */ +#define IRQn_CAM1 98 /* CAM1 IRQ */ +#define IRQn_LCDC_D0 99 /* LCDC_D0 IRQ */ +#define IRQn_LCDC_D1 100 /* LCDC_D1 IRQ */ +#define IRQn_PDMA_D0 101 /* PDMA_D0 IRQ */ +#define IRQn_PDMA_D1 102 /* PDMA_D1 IRQ */ +#define IRQn_JPEG 103 /* JPEG IRQ */ +#define IRQn_NTMR0 104 /* NTMR0 IRQ */ +#define IRQn_NTMR1 105 /* NTMR1 IRQ */ +#define IRQn_USB0 106 /* USB0 IRQ */ +#define IRQn_USB1 107 /* USB1 IRQ */ +#define IRQn_ENET0 108 /* ENET0 IRQ */ +#define IRQn_ENET1 109 /* ENET1 IRQ */ +#define IRQn_SDXC0 110 /* SDXC0 IRQ */ +#define IRQn_SDXC1 111 /* SDXC1 IRQ */ +#define IRQn_PSEC 112 /* PSEC IRQ */ +#define IRQn_PGPIO 113 /* PGPIO IRQ */ +#define IRQn_PWDG 114 /* PWDG IRQ */ +#define IRQn_PTMR 115 /* PTMR IRQ */ +#define IRQn_PUART 116 /* PUART IRQ */ +#define IRQn_VAD 117 /* VAD IRQ */ +#define IRQn_FUSE 118 /* FUSE IRQ */ +#define IRQn_SECMON 119 /* SECMON IRQ */ +#define IRQn_RTC 120 /* RTC IRQ */ +#define IRQn_BUTN 121 /* BUTN IRQ */ +#define IRQn_BGPIO 122 /* BGPIO IRQ */ +#define IRQn_BVIO 123 /* BVIO IRQ */ +#define IRQn_BROWNOUT 124 /* BROWNOUT IRQ */ +#define IRQn_SYSCTL 125 /* SYSCTL IRQ */ +#define IRQn_DEBUG_0 126 /* DEBUG[0] IRQ */ +#define IRQn_DEBUG_1 127 /* DEBUG[1] IRQ */ #include "hpm_common.h" @@ -849,4 +849,4 @@ #include "hpm_iomux.h" #include "hpm_pmic_iomux.h" #include "hpm_batt_iomux.h" -#endif /* HPM_SOC_H */ \ No newline at end of file +#endif /* HPM_SOC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_soc_feature.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_soc_feature.h index f554062f28d..2f27b1d1dd9 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_soc_feature.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_soc_feature.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -63,7 +63,6 @@ */ #define DMA_SOC_TRANSFER_WIDTH_MAX(x) (((x) == HPM_XDMA) ? DMA_TRANSFER_WIDTH_DOUBLE_WORD : DMA_TRANSFER_WIDTH_WORD) #define DMA_SOC_TRANSFER_PER_BURST_MAX(x) (((x) == HPM_XDMA) ? DMA_NUM_TRANSFER_PER_BURST_1024T : DMA_NUM_TRANSFER_PER_BURST_128T) -#define DMA_SOC_BUS_NUM (1U) #define DMA_SOC_CHANNEL_NUM (8U) #define DMA_SOC_MAX_COUNT (2U) #define DMA_SOC_CHN_TO_DMAMUX_CHN(x, n) (((x) == HPM_XDMA) ? (DMAMUX_MUXCFG_XDMA_MUX0 + n) : (DMAMUX_MUXCFG_HDMA_MUX0 + n)) @@ -72,7 +71,7 @@ * PDMA Section */ #define PDMA_SOC_PS_MAX_COUNT (2U) - +#define PDMA_SOC_SUPPORT_BS16 (1U) /* * LCDC Section */ @@ -88,18 +87,15 @@ #define USB_SOC_DCD_QTD_NEXT_INVALID (1U) #define USB_SOC_DCD_QHD_BUFFER_COUNT (5U) -#define USB_SOC_DCD_QTD_ALIGNMENT (32U) -#define USB_SOC_DCD_QHD_ALIGNMENT (64U) #define USB_SOC_DCD_MAX_ENDPOINT_COUNT (8U) -#define USB_SOC_DCD_MAX_QTD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U) +#ifndef USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT +#define USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT (8U) +#endif +#define USB_SOC_DCD_MAX_QTD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U * USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT) #define USB_SOS_DCD_MAX_QHD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U) #define USB_SOC_DCD_DATA_RAM_ADDRESS_ALIGNMENT (2048U) -#define USB_SOC_HCD_QTD_BUFFER_COUNT (5U) -#define USB_SOC_HCD_QTD_ALIGNMENT (32U) -#define USB_SOC_HCD_QHD_ALIGNMENT (32U) #define USB_SOC_HCD_FRAMELIST_MAX_ELEMENTS (1024U) -#define USB_SOC_HCD_DATA_RAM_ADDRESS_ALIGNMENT (4096U) /* * ENET Section @@ -122,6 +118,7 @@ /* * ADC Section */ +#define ADC_SOC_IP_VERSION (0U) #define ADC_SOC_SEQ_MAX_LEN (16U) #define ADC_SOC_MAX_TRIG_CH_LEN (4U) #define ADC_SOC_MAX_TRIG_CH_NUM (11U) @@ -192,6 +189,9 @@ /* * OTP Section */ +#define OTP_SOC_MAC0_IDX (65U) +#define OTP_SOC_MAC0_LEN (6U) /* in bytes */ + #define OTP_SOC_UUID_IDX (88U) #define OTP_SOC_UUID_LEN (16U) /* in bytes */ @@ -203,12 +203,4 @@ #define PWM_SOC_SHADOW_TRIG_SUPPORT (0U) #define PWM_SOC_TIMER_RESET_SUPPORT (0U) - -/** - * IOC Section - * - */ -#define IOC_SOC_PAD_MAX (491) - - #endif /* HPM_SOC_FEATURE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_soc_ip_feature.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_soc_ip_feature.h new file mode 100644 index 00000000000..d21c1e5be3e --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_soc_ip_feature.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_SOC_IP_FEATURE_H +#define HPM_SOC_IP_FEATURE_H + +/* ADC16 related feature */ +#define HPM_IP_FEATURE_ADC16_HAS_TEMPSNS 1 + +#endif /* HPM_SOC_IP_FEATURE_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.c index 203258cd10e..9e23887d5de 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.c @@ -129,6 +129,7 @@ hpm_stat_t sysctl_cpu1_set_gpr(SYSCTL_Type *ptr, void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config) { + (void) ptr; config->mode = monitor_work_mode_record; config->accuracy = monitor_accuracy_1khz; config->reference = monitor_reference_24mhz; @@ -202,32 +203,83 @@ hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry) hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, uint8_t group, - sysctl_resource_t linkable_resource, + sysctl_resource_t resource, bool enable) { uint32_t index, offset; - if (linkable_resource < sysctl_resource_linkable_start) { + if (resource < sysctl_resource_linkable_start) { return status_invalid_argument; } - index = (linkable_resource - sysctl_resource_linkable_start) / 32; - offset = (linkable_resource - sysctl_resource_linkable_start) % 32; + index = (resource - sysctl_resource_linkable_start) / 32; + offset = (resource - sysctl_resource_linkable_start) % 32; switch (group) { - case SYSCTL_RESOURCE_GROUP0: - ptr->GROUP0[index].VALUE = (ptr->GROUP0[index].VALUE & ~(1UL << offset)) - | (enable ? (1UL << offset) : 0); - break; - case SYSCTL_RESOURCE_GROUP1: - ptr->GROUP1[index].VALUE = (ptr->GROUP1[index].VALUE & ~(1UL << offset)) - | (enable ? (1UL << offset) : 0); - break; - default: - return status_invalid_argument; + case SYSCTL_RESOURCE_GROUP0: + ptr->GROUP0[index].VALUE = (ptr->GROUP0[index].VALUE & ~(1UL << offset)) + | (enable ? (1UL << offset) : 0); + if (enable) { + while (sysctl_resource_target_is_busy(ptr, resource)) { + ; + } + } + break; + case SYSCTL_RESOURCE_GROUP1: + ptr->GROUP1[index].VALUE = (ptr->GROUP1[index].VALUE & ~(1UL << offset)) + | (enable ? (1UL << offset) : 0); + if (enable) { + while (sysctl_resource_target_is_busy(ptr, resource)) { + ; + } + } + break; + default: + return status_invalid_argument; } return status_success; } +bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, + uint8_t group, + sysctl_resource_t resource) +{ + uint32_t index, offset; + bool enable; + + index = (resource - sysctl_resource_linkable_start) / 32; + offset = (resource - sysctl_resource_linkable_start) % 32; + switch (group) { + case SYSCTL_RESOURCE_GROUP0: + enable = ((ptr->GROUP0[index].VALUE & (1UL << offset)) != 0) ? true : false; + break; + case SYSCTL_RESOURCE_GROUP1: + enable = ((ptr->GROUP1[index].VALUE & (1UL << offset)) != 0) ? true : false; + break; + default: + enable = false; + break; + } + + return enable; +} + +uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index) +{ + uint32_t value; + switch (group) { + case SYSCTL_RESOURCE_GROUP0: + value = ptr->GROUP0[index].VALUE; + break; + case SYSCTL_RESOURCE_GROUP1: + value = ptr->GROUP1[index].VALUE; + break; + default: + value = 0; + break; + } + return value; +} + hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) { return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, true); @@ -284,9 +336,8 @@ hpm_stat_t sysctl_set_adc_i2s_clock_mux(SYSCTL_Type *ptr, return status_success; } -hpm_stat_t sysctl_update_divider(SYSCTL_Type *ptr, clock_node_t node_index, uint32_t divide_by) +hpm_stat_t sysctl_update_divider(SYSCTL_Type *ptr, clock_node_t node, uint32_t divide_by) { - uint32_t node = (uint32_t) node_index; if (node >= clock_node_adc_i2s_start) { return status_invalid_argument; } @@ -297,11 +348,9 @@ hpm_stat_t sysctl_update_divider(SYSCTL_Type *ptr, clock_node_t node_index, uint return status_success; } - -hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node_index, +hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node, clock_source_t source, uint32_t divide_by) { - uint32_t node = (uint32_t) node_index; if (node >= clock_node_adc_i2s_start) { return status_invalid_argument; } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.h index 042227459b3..a0fef2167af 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.h @@ -748,6 +748,19 @@ static inline void sysctl_resource_target_set_mode(SYSCTL_Type *ptr, SYSCTL_RESOURCE_MODE_SET(mode); } +/** + * @brief Get target mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource target resource index + * @return target resource mode + */ +static inline uint8_t sysctl_resource_target_get_mode(SYSCTL_Type *ptr, + sysctl_resource_t resource) +{ + return SYSCTL_RESOURCE_MODE_GET(ptr->RESOURCE[resource]); +} + /** * @brief Disable resource retention when specific CPU enters stop mode * @@ -927,7 +940,7 @@ static inline bool sysctl_clock_any_is_busy(SYSCTL_Type *ptr) * @return true if target clock is busy */ static inline bool sysctl_clock_target_is_busy(SYSCTL_Type *ptr, - uint32_t clock) + clock_node_t clock) { return ptr->CLOCK[clock] & SYSCTL_CLOCK_LOC_BUSY_MASK; } @@ -1523,6 +1536,27 @@ hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t resource, bool enable); + +/** + * @brief Check group resource enable status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] group target group to be checked + * @param[in] resource target resource to be checked from group + * @return enable true if resource enable, false if resource disable + */ +bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t resource); + +/** + * @brief Get group resource value + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] group target group to be getted + * @param[in] index target group index + * @return group index value + */ +uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index); + /** * @brief Add resource to CPU0 * @@ -1579,7 +1613,7 @@ void sysctl_monitor_init(SYSCTL_Type *ptr, monitor_config_t *config); /** - * @brief Save data to GPU0 GPR starting from given index + * @brief Save data to CPU0 GPR starting from given index * * @param[in] ptr SYSCTL_Type base address * @param[in] start Starting GPR index @@ -1595,7 +1629,7 @@ hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, bool lock); /** - * @brief Get data saved from GPU0 GPR starting from given index + * @brief Get data saved from CPU0 GPR starting from given index * * @param[in] ptr SYSCTL_Type base address * @param[in] start Starting GPR index diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_regs.h index 20847100f42..3f8e145154b 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -33,10 +33,10 @@ typedef struct { __RW uint32_t TOGGLE; /* 0x90C: Affiliate of Group */ } AFFILIATE[2]; struct { - __RW uint32_t VALUE; /* 0x920: Retention Contol */ - __RW uint32_t SET; /* 0x924: Retention Contol */ - __RW uint32_t CLEAR; /* 0x928: Retention Contol */ - __RW uint32_t TOGGLE; /* 0x92C: Retention Contol */ + __RW uint32_t VALUE; /* 0x920: Retention Control */ + __RW uint32_t SET; /* 0x924: Retention Control */ + __RW uint32_t CLEAR; /* 0x928: Retention Control */ + __RW uint32_t TOGGLE; /* 0x92C: Retention Control */ } RETENTION[2]; __R uint8_t RESERVED3[1728]; /* 0x940 - 0xFFF: Reserved */ struct { @@ -460,7 +460,7 @@ typedef struct { * * perform reset and release imediately * 0: reset is released - * 1 reset is asserted and will release automaticly + * 1 reset is asserted and will release automatically */ #define SYSCTL_RESET_CONTROL_RESET_MASK (0x1U) #define SYSCTL_RESET_CONTROL_RESET_SHIFT (0U) @@ -771,7 +771,7 @@ typedef struct { /* * REFERENCE (RW) * - * refrence clock selection, + * reference clock selection, * 0: 32k * 1: 24M */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_trgm_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_trgm_regs.h index e737a08c7b4..6f996212bb6 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_trgm_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_trgm_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_trgmmux_src.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_trgmmux_src.h index 6b10ecd5139..a1e7d691c3a 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_trgmmux_src.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_trgmmux_src.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/soc_modules.list b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/soc_modules.list index 01bdca78b73..a5255e66227 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/soc_modules.list +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/soc_modules.list @@ -1,38 +1,67 @@ -# Copyright (c) 2022 HPMicro +# +# Copyright (c) 2024 HPMicro +# # SPDX-License-Identifier: BSD-3-Clause # -# In this file, all modules available on this part are listed -CONFIG_HAS_HPMSDK_UART=y -CONFIG_HAS_HPMSDK_FEMC=y -CONFIG_HAS_HPMSDK_SDP=y -CONFIG_HAS_HPMSDK_LCDC=y -CONFIG_HAS_HPMSDK_I2C=y -CONFIG_HAS_HPMSDK_PMP=y -CONFIG_HAS_HPMSDK_RNG=y -CONFIG_HAS_HPMSDK_GPIO=y -CONFIG_HAS_HPMSDK_SPI=y -CONFIG_HAS_HPMSDK_PDMA=y -CONFIG_HAS_HPMSDK_WDG=y -CONFIG_HAS_HPMSDK_DMA=y -CONFIG_HAS_HPMSDK_GPTMR=y -CONFIG_HAS_HPMSDK_PWM=y -CONFIG_HAS_HPMSDK_PLLCTL=y -CONFIG_HAS_HPMSDK_USB=y -CONFIG_HAS_HPMSDK_RTC=y -CONFIG_HAS_HPMSDK_ACMP=y -CONFIG_HAS_HPMSDK_I2S=y -CONFIG_HAS_HPMSDK_DAO=y -CONFIG_HAS_HPMSDK_PDM=y -CONFIG_HAS_HPMSDK_VAD=y -CONFIG_HAS_HPMSDK_CAM=y -CONFIG_HAS_HPMSDK_CAN=y -CONFIG_HAS_HPMSDK_JPEG=y -CONFIG_HAS_HPMSDK_ENET=y -CONFIG_HAS_HPMSDK_SDXC=y -CONFIG_HAS_HPMSDK_ADC12=y -CONFIG_HAS_HPMSDK_ADC16=y -CONFIG_HAS_HPMSDK_PCFG=y -CONFIG_HAS_HPMSDK_PTPC=y -CONFIG_HAS_HPMSDK_MCHTMR=y +HPMSOC_HAS_HPMSDK_MULTICORE=y +HPMSOC_HAS_HPMSDK_GPIO=y +HPMSOC_HAS_HPMSDK_PLIC=y +HPMSOC_HAS_HPMSDK_MCHTMR=y +HPMSOC_HAS_HPMSDK_PLICSW=y +HPMSOC_HAS_HPMSDK_GPIOM=y +HPMSOC_HAS_HPMSDK_ADC12=y +HPMSOC_HAS_HPMSDK_ADC16=y +HPMSOC_HAS_HPMSDK_ACMP=y +HPMSOC_HAS_HPMSDK_SPI=y +HPMSOC_HAS_HPMSDK_UART=y +HPMSOC_HAS_HPMSDK_CAN=y +HPMSOC_HAS_HPMSDK_WDG=y +HPMSOC_HAS_HPMSDK_MBX=y +HPMSOC_HAS_HPMSDK_PTPC=y +HPMSOC_HAS_HPMSDK_DMAMUX=y +HPMSOC_HAS_HPMSDK_DMA=y +HPMSOC_HAS_HPMSDK_RNG=y +HPMSOC_HAS_HPMSDK_KEYM=y +HPMSOC_HAS_HPMSDK_I2S=y +HPMSOC_HAS_HPMSDK_DAO=y +HPMSOC_HAS_HPMSDK_PDM=y +HPMSOC_HAS_HPMSDK_PWM=y +HPMSOC_HAS_HPMSDK_HALL=y +HPMSOC_HAS_HPMSDK_QEI=y +HPMSOC_HAS_HPMSDK_TRGM=y +HPMSOC_HAS_HPMSDK_SYNT=y +HPMSOC_HAS_HPMSDK_LCDC=y +HPMSOC_HAS_HPMSDK_CAM=y +HPMSOC_HAS_HPMSDK_PDMA=y +HPMSOC_HAS_HPMSDK_JPEG=y +HPMSOC_HAS_HPMSDK_ENET=y +HPMSOC_HAS_HPMSDK_GPTMR=y +HPMSOC_HAS_HPMSDK_USB=y +HPMSOC_HAS_HPMSDK_SDXC=y +HPMSOC_HAS_HPMSDK_CONCTL=y +HPMSOC_HAS_HPMSDK_I2C=y +HPMSOC_HAS_HPMSDK_SDP=y +HPMSOC_HAS_HPMSDK_FEMC=y +HPMSOC_HAS_HPMSDK_SYSCTL=y +HPMSOC_HAS_HPMSDK_IOC=y +HPMSOC_HAS_HPMSDK_OTP=y +HPMSOC_HAS_HPMSDK_PPOR=y +HPMSOC_HAS_HPMSDK_PCFG=y +HPMSOC_HAS_HPMSDK_PSEC=y +HPMSOC_HAS_HPMSDK_PMON=y +HPMSOC_HAS_HPMSDK_PGPR=y +HPMSOC_HAS_HPMSDK_VAD=y +HPMSOC_HAS_HPMSDK_PLLCTL=y +HPMSOC_HAS_HPMSDK_BPOR=y +HPMSOC_HAS_HPMSDK_BCFG=y +HPMSOC_HAS_HPMSDK_BUTN=y +HPMSOC_HAS_HPMSDK_BGPR=y +HPMSOC_HAS_HPMSDK_RTC=y +HPMSOC_HAS_HPMSDK_BSEC=y +HPMSOC_HAS_HPMSDK_BKEY=y +HPMSOC_HAS_HPMSDK_BMON=y +HPMSOC_HAS_HPMSDK_TAMP=y +HPMSOC_HAS_HPMSDK_MONO=y +HPMSOC_HAS_HPMSDK_PMP=y diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/system.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/system.c index 2c0c81f64f2..4e1fc21b466 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/system.c +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/system.c @@ -42,11 +42,4 @@ __attribute__((weak)) void system_init(void) uint32_t mcounteren = read_csr(CSR_MCOUNTEREN); write_csr(CSR_MCOUNTEREN, mcounteren | 1); /* Enable MCYCLE */ #endif -#ifndef CONFIG_NOT_ENABLE_ICACHE - l1c_ic_enable(); -#endif -#ifndef CONFIG_NOT_ENABLE_DCACHE - l1c_dc_enable(); - l1c_dc_invalidate_all(); -#endif } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash.ld index e169e802e70..ebdf6f9aba7 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash.ld +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash.ld @@ -5,8 +5,8 @@ ENTRY(_start) -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; +STACK_SIZE = _stack_size; +HEAP_SIZE = _heap_size; MEMORY { @@ -14,7 +14,7 @@ MEMORY ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 512K /* AXI SRAM0 */ - NONCACHEABLE_RAM (w) : ORIGIN = 0x01100000, LENGTH = 256K /* AXI SRAM1 */ + NONCACHEABLE_RAM (wx) : ORIGIN = 0x01100000, LENGTH = 256K /* AXI SRAM1 */ SHARE_RAM (w) : ORIGIN = 0x0117C000, LENGTH = 16K AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k @@ -27,7 +27,17 @@ SECTIONS KEEP(*(.start)) } > XPI0 - .text : { + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { . = ALIGN(8); *(.text) *(.text*) @@ -46,36 +56,51 @@ SECTIONS KEEP (*(.init)) KEEP (*(.fini)) - . = ALIGN(8); - } > XPI0 - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - /* section information for usbh class */ - .usbh_class_info : { - . = ALIGN(4); + /* section information for usbh class */ + . = ALIGN(8); __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; + + /* RT-Thread related sections - Start */ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ . = ALIGN(8); } > XPI0 + .rel : { + KEEP(*(.rel*)) + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - .vectors ORIGIN(ILM) : AT(etext) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .data : AT(etext + __vector_ram_end__ - __vector_ram_start__) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -83,8 +108,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -128,10 +151,12 @@ SECTIONS PROVIDE (edata = .); } > AXI_SRAM - .fast : AT(etext + __vector_ram_end__ - __vector_ram_start__ + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) + *(.fast.*) . = ALIGN(8); PROVIDE(__ramfunc_end__ = .); } > ILM @@ -141,11 +166,9 @@ SECTIONS __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -153,13 +176,37 @@ SECTIONS __bss_end__ = .; } > AXI_SRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > AXI_SRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > AXI_SRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > AXI_SRAM - .noncacheable.init : AT(etext + __vector_ram_end__ - __vector_ram_start__ + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -213,5 +260,6 @@ SECTIONS __share_mem_start__ = ORIGIN(SHARE_RAM); __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - ASSERT((STACK_SIZE + HEAP_SIZE) <= 256K, "stack and heap total size larger than 256k") + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_uf2.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_uf2.ld index 4753a5ee883..e4fa23b2cf1 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_uf2.ld +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_uf2.ld @@ -5,8 +5,8 @@ ENTRY(_start) -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; +STACK_SIZE = _stack_size; +HEAP_SIZE = _heap_size; UF2_BOOTLOADER_RESERVED_LENGTH = DEFINED(_uf2_bl_length) ? _uf2_bl_length : 0x20000; MEMORY @@ -29,7 +29,17 @@ SECTIONS KEEP(*(.start)) } > XPI0 - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__): { + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)): { . = ALIGN(8); *(.text) *(.text*) @@ -48,37 +58,51 @@ SECTIONS KEEP (*(.init)) KEEP (*(.fini)) - . = ALIGN(8); - } > XPI0 - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - /* section information for usbh class */ - .usbh_class_info : { - . = ALIGN(4); + /* section information for usbh class */ + . = ALIGN(8); __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; + + /* RT-Thread related sections - Start */ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ . = ALIGN(8); } > XPI0 + .rel : { + KEEP(*(.rel*)) + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .data : AT(etext) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -86,8 +110,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -131,10 +153,12 @@ SECTIONS PROVIDE (edata = .); } > SDRAM - .fast : AT(etext + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) + *(.fast.*) . = ALIGN(8); PROVIDE(__ramfunc_end__ = .); } > ILM @@ -144,11 +168,9 @@ SECTIONS __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -156,13 +178,37 @@ SECTIONS __bss_end__ = .; } > SDRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > SDRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > SDRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > SDRAM - .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -215,4 +261,7 @@ SECTIONS __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); __share_mem_start__ = ORIGIN(SHARE_RAM); __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_xip.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_xip.ld index 96e99bf4447..7550b8f6e20 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_xip.ld +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_xip.ld @@ -5,8 +5,8 @@ ENTRY(_start) -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; +STACK_SIZE = _stack_size; +HEAP_SIZE = _heap_size; MEMORY { @@ -46,7 +46,17 @@ SECTIONS KEEP(*(.start)) } > XPI0 - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { . = ALIGN(8); *(EXCLUDE_FILE (nx*.o*) .text) *(EXCLUDE_FILE (nx*.o*) .text*) @@ -65,37 +75,51 @@ SECTIONS KEEP (*(.init)) KEEP (*(.fini)) - . = ALIGN(8); - } > XPI0 - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - /* section information for usbh class */ - .usbh_class_info : { - . = ALIGN(4); + /* section information for usbh class */ + . = ALIGN(8); __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; + + /* RT-Thread related sections - Start */ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ . = ALIGN(8); } > XPI0 + .rel : { + KEEP(*(.rel*)) + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .data : AT(etext) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -103,8 +127,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -142,16 +164,19 @@ SECTIONS KEEP(*(SORT(.dtors.*))) KEEP(*(.dtors)) . = ALIGN(8); + __data_end__ = .; PROVIDE (__edata = .); PROVIDE (_edata = .); PROVIDE (edata = .); } > SDRAM - .fast : AT(etext + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) + *(.fast.*) nx*.o*(.text) nx*.o*(.text*) nx*.o*(.rodata) @@ -162,17 +187,14 @@ SECTIONS PROVIDE(__ramfunc_end__ = .); } > ILM - __fw_size__ = __ramfunc_end__ - __ramfunc_start__ + __data_end__ - __data_start__ + etext - __app_load_addr__; .bss (NOLOAD) : { . = ALIGN(8); __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -180,13 +202,37 @@ SECTIONS __bss_end__ = .; } > SDRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > SDRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > SDRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > SDRAM - .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -239,4 +285,7 @@ SECTIONS __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); __share_mem_start__ = ORIGIN(SHARE_RAM); __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_uf2.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_uf2.ld index 6a87b2842ba..ce10de7b61b 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_uf2.ld +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_uf2.ld @@ -5,8 +5,8 @@ ENTRY(_start) -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; +STACK_SIZE = _stack_size; +HEAP_SIZE = _heap_size; UF2_BOOTLOADER_RESERVED_LENGTH = DEFINED(_uf2_bl_length) ? _uf2_bl_length : 0x20000; MEMORY @@ -15,7 +15,7 @@ MEMORY ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 512K /* AXI SRAM0 */ - NONCACHEABLE_RAM (w) : ORIGIN = 0x01100000, LENGTH = 256K /* AXI SRAM1 */ + NONCACHEABLE_RAM (wx) : ORIGIN = 0x01100000, LENGTH = 256K /* AXI SRAM1 */ SHARE_RAM (w) : ORIGIN = 0x0117C000, LENGTH = 16K AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k @@ -28,7 +28,17 @@ SECTIONS KEEP(*(.start)) } > XPI0 - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__): { + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)): { . = ALIGN(8); *(.text) *(.text*) @@ -47,37 +57,51 @@ SECTIONS KEEP (*(.init)) KEEP (*(.fini)) - . = ALIGN(8); - } > XPI0 - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - /* section information for usbh class */ - .usbh_class_info : { - . = ALIGN(4); + /* section information for usbh class */ + . = ALIGN(8); __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; + + /* RT-Thread related sections - Start */ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ . = ALIGN(8); } > XPI0 + .rel : { + KEEP(*(.rel*)) + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .data : AT(etext) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -85,8 +109,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -130,10 +152,12 @@ SECTIONS PROVIDE (edata = .); } > AXI_SRAM - .fast : AT(etext + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) + *(.fast.*) . = ALIGN(8); PROVIDE(__ramfunc_end__ = .); } > ILM @@ -143,11 +167,9 @@ SECTIONS __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -155,13 +177,37 @@ SECTIONS __bss_end__ = .; } > AXI_SRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > AXI_SRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > AXI_SRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -215,5 +261,6 @@ SECTIONS __share_mem_start__ = ORIGIN(SHARE_RAM); __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - ASSERT((STACK_SIZE + HEAP_SIZE) <= 256K, "stack and heap total size larger than 256k") + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_xip.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_xip.ld index 7bff4c76bdc..77467ca1c90 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_xip.ld +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_xip.ld @@ -5,8 +5,8 @@ ENTRY(_start) -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; +STACK_SIZE = _stack_size; +HEAP_SIZE = _heap_size; MEMORY { @@ -14,7 +14,7 @@ MEMORY ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 512K /* AXI SRAM0 */ - NONCACHEABLE_RAM (w) : ORIGIN = 0x01100000, LENGTH = 256K /* AXI SRAM1 */ + NONCACHEABLE_RAM (wx) : ORIGIN = 0x01100000, LENGTH = 256K /* AXI SRAM1 */ SHARE_RAM (w) : ORIGIN = 0x0117C000, LENGTH = 16K AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k @@ -46,7 +46,17 @@ SECTIONS KEEP(*(.start)) } > XPI0 - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { . = ALIGN(8); *(EXCLUDE_FILE (nx*.o*) .text) *(EXCLUDE_FILE (nx*.o*) .text*) @@ -65,37 +75,51 @@ SECTIONS KEEP (*(.init)) KEEP (*(.fini)) - . = ALIGN(8); - } > XPI0 - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - /* section information for usbh class */ - .usbh_class_info : { - . = ALIGN(4); + /* section information for usbh class */ + . = ALIGN(8); __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; + + /* RT-Thread related sections - Start */ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ . = ALIGN(8); } > XPI0 + .rel : { + KEEP(*(.rel*)) + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .data : AT(etext) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -103,8 +127,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -148,10 +170,12 @@ SECTIONS PROVIDE (edata = .); } > AXI_SRAM - .fast : AT(etext + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) + *(.fast.*) nx*.o*(.text) nx*.o*(.text*) nx*.o*(.rodata) @@ -162,17 +186,14 @@ SECTIONS PROVIDE(__ramfunc_end__ = .); } > ILM - __fw_size__ = __ramfunc_end__ - __ramfunc_start__ + __data_end__ - __data_start__ + etext - __app_load_addr__; .bss (NOLOAD) : { . = ALIGN(8); __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -180,13 +201,37 @@ SECTIONS __bss_end__ = .; } > AXI_SRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > AXI_SRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > AXI_SRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -240,5 +285,6 @@ SECTIONS __share_mem_start__ = ORIGIN(SHARE_RAM); __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - ASSERT((STACK_SIZE + HEAP_SIZE) <= 256K, "stack and heap total size larger than 256k") + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram.ld index 261dde48ad2..b17052247d8 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram.ld +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram.ld @@ -5,15 +5,15 @@ ENTRY(_start) -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; +STACK_SIZE = _stack_size; +HEAP_SIZE = _heap_size; MEMORY { ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 512K /* AXI SRAM0 */ - NONCACHEABLE_RAM (w) : ORIGIN = 0x01100000, LENGTH = 256K /* AXI SRAM1 */ + NONCACHEABLE_RAM (wx) : ORIGIN = 0x01100000, LENGTH = 256K /* AXI SRAM1 */ SHARE_RAM (w) : ORIGIN = 0x0117C000, LENGTH = 16K AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k @@ -63,13 +63,40 @@ SECTIONS KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; + /* RT-Thread related sections - Start */ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + . = ALIGN(8); PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); } > ILM - .data : AT(etext) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -77,8 +104,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -123,10 +148,12 @@ SECTIONS PROVIDE (edata = .); } > AXI_SRAM - .fast : AT(etext + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) + *(.fast.*) . = ALIGN(8); PROVIDE(__ramfunc_end__ = .); } > ILM @@ -136,11 +163,9 @@ SECTIONS __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -148,13 +173,37 @@ SECTIONS __bss_end__ = .; } > AXI_SRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > AXI_SRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > AXI_SRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -208,5 +257,7 @@ SECTIONS __share_mem_start__ = ORIGIN(SHARE_RAM); __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - ASSERT((STACK_SIZE + HEAP_SIZE) <= 256K, "stack and heap total size larger than 256k") + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + __last_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); + ASSERT(((__fw_size__ <= LENGTH(ILM)) && (__last_addr__ <= (ORIGIN(ILM) + LENGTH(ILM)))), "****** FAILED! ILM has not enough space! ******") } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram_core1.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram_core1.ld index d7bba310a05..18042acfe55 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram_core1.ld +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram_core1.ld @@ -5,14 +5,14 @@ ENTRY(_start) -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; +STACK_SIZE = _stack_size; +HEAP_SIZE = _heap_size; MEMORY { ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K - NONCACHEABLE_RAM (w) : ORIGIN = 0x01140000, LENGTH = 64K /* AXI SRAM1 */ + NONCACHEABLE_RAM (wx) : ORIGIN = 0x01140000, LENGTH = 64K /* AXI SRAM1 */ AXI_SRAM (wx) : ORIGIN = 0x01150000, LENGTH = 176K SHARE_RAM (w) : ORIGIN = 0x0117C000, LENGTH = 16K } @@ -61,13 +61,46 @@ SECTIONS KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + /* RT-Thread related sections - Start */ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + . = ALIGN(8); PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); } > ILM - .data : AT(etext) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -75,8 +108,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -121,10 +152,12 @@ SECTIONS PROVIDE (edata = .); } > AXI_SRAM - .fast : AT(etext + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) + *(.fast.*) . = ALIGN(8); PROVIDE(__ramfunc_end__ = .); } > ILM @@ -134,11 +167,9 @@ SECTIONS __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -146,13 +177,37 @@ SECTIONS __bss_end__ = .; } > AXI_SRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > AXI_SRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > AXI_SRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -198,5 +253,7 @@ SECTIONS __share_mem_start__ = ORIGIN(SHARE_RAM); __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - ASSERT((STACK_SIZE + HEAP_SIZE) <= 256K, "stack and heap total size larger than 256k") + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + __last_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); + ASSERT(((__fw_size__ <= LENGTH(ILM)) && (__last_addr__ <= (ORIGIN(ILM) + LENGTH(ILM)))), "****** FAILED! ILM has not enough space! ******") } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/start.S b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/start.S index f5e1b28a4f9..8eb6bedbab5 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/start.S +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/start.S @@ -16,6 +16,7 @@ _start: .option push .option norelax la gp, __global_pointer$ + la tp, __thread_pointer$ .option pop /* reset mstatus to 0*/ @@ -30,6 +31,12 @@ _start: fscsr zero #endif + /* Enable LMM1 clock */ + la t0, 0xF4000800 + lw t1, 0(t0) + ori t1, t1, 0x80 + sw t1, 0(t0) + #ifdef INIT_EXT_RAM_FOR_DATA la t0, _stack_safe mv sp, t0 @@ -40,6 +47,19 @@ _start: la t0, _stack mv sp, t0 +#ifdef CONFIG_NOT_ENABLE_ICACHE + call l1c_ic_disable +#else + call l1c_ic_enable +#endif +#ifdef CONFIG_NOT_ENABLE_DCACHE + call l1c_dc_invalidate_all + call l1c_dc_disable +#else + call l1c_dc_enable + call l1c_dc_invalidate_all +#endif + /* * Initialize LMA/VMA sections. * Relocation for any sections that need to be copied from LMA to VMA. @@ -85,6 +105,14 @@ _start: /* Use mscratch to store isr level */ csrw mscratch, 0 + +#elif defined(CONFIG_RTTHREAD) && CONFIG_RTTHREAD + #define HANDLER_TRAP rtt_risc_v_trap_handler + #define HANDLER_S_TRAP rtt_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 + #else #define HANDLER_TRAP irq_handler_trap #endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/reset.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/reset.c index ed38e338a7b..9fb2135db6a 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/reset.c +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/reset.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,6 +12,10 @@ extern void system_init(void); +#ifndef MAIN_ENTRY +#define MAIN_ENTRY main +#endif +extern int MAIN_ENTRY(void); __attribute__((weak)) void _clean_up(void) { @@ -30,6 +34,15 @@ __attribute__((weak)) void _clean_up(void) __attribute__((weak)) void c_startup(void) { uint32_t i, size; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __tdata_start__[], __tdata_end__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + extern uint8_t __data_load_addr__[], __tdata_load_addr__[]; + extern uint8_t __fast_load_addr__[], __noncacheable_init_load_addr__[]; + #if defined(FLASH_XIP) || defined(FLASH_UF2) extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; size = __vector_ram_end__ - __vector_ram_start__; @@ -38,13 +51,6 @@ __attribute__((weak)) void c_startup(void) } #endif - extern uint8_t __etext[]; - extern uint8_t __bss_start__[], __bss_end__[]; - extern uint8_t __data_start__[], __data_end__[]; - extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; - extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; - extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; - /* bss section */ size = __bss_end__ - __bss_start__; for (i = 0; i < size; i++) { @@ -60,19 +66,25 @@ __attribute__((weak)) void c_startup(void) /* data section LMA: etext */ size = __data_end__ - __data_start__; for (i = 0; i < size; i++) { - *(__data_start__ + i) = *(__etext + i); + *(__data_start__ + i) = *(__data_load_addr__ + i); } /* ramfunc section LMA: etext + data length */ size = __ramfunc_end__ - __ramfunc_start__; for (i = 0; i < size; i++) { - *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __data_start__) + i); + *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i); } - /* noncacheable init section LMA: etext + data length + ramfunc legnth */ + /* tdata section LMA: etext + data length + ramfunc length */ + size = __tdata_end__ - __tdata_start__; + for (i = 0; i < size; i++) { + *(__tdata_start__ + i) = *(__tdata_load_addr__ + i); + } + + /* noncacheable init section LMA: etext + data length + ramfunc legnth + tdata length*/ size = __noncacheable_init_end__ - __noncacheable_init_start__; for (i = 0; i < size; i++) { - *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __data_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); + *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); } } @@ -85,14 +97,13 @@ __attribute__((weak)) int main(void) __attribute__((weak)) void reset_handler(void) { - l1c_dc_disable(); - l1c_dc_invalidate_all(); + fencei(); /* Call platform specific hardware initialization */ system_init(); /* Entry function */ - main(); + MAIN_ENTRY(); } /* @@ -102,12 +113,46 @@ __attribute__((weak)) void reset_handler(void) */ __attribute__((weak)) void __cxa_atexit(void (*arg1)(void *), void *arg2, void *arg3) { + (void) arg1; + (void) arg2; + (void) arg3; } -#if !defined(__SEGGER_RTL_VERSION) || defined(__riscv_xandes) +#if (!defined(__SEGGER_RTL_VERSION) || defined(__riscv_xandes)) && !defined(__ICCRISCV__) void *__dso_handle = (void *) &__dso_handle; #endif __attribute__((weak)) void _init(void) { } + + +#ifdef __ICCRISCV__ +int __low_level_init(void) +{ +#ifdef IAR_MANUAL_COPY /* Enable this code snippet if the .isr_vector and .vector_table need to be copied to RAM manually */ +#pragma section = ".isr_vector" +#pragma section = ".isr_vector_init" +#pragma section = ".vector_table" +#pragma section = ".vector_table_init" + /* Initialize section .isr_vector, section .vector_table */ + uint8_t *__isr_vector_ram_start = __section_begin(".isr_vector"); + uint32_t __isr_vector_ram_size = __section_size(".isr_vector"); + uint8_t *__isr_vector_rom_start = __section_begin(".isr_vector_init"); + + for (uint32_t i = 0; i < __isr_vector_ram_size; i++) { + __isr_vector_ram_start[i] = __isr_vector_rom_start[i]; + } + + uint8_t *__vector_table_ram_start = __section_begin(".vector_table"); + uint32_t __vector_table_ram_size = __section_size(".vector_table"); + uint8_t *__vector_rom_start = __section_begin(".vector_table_init"); + + for (uint32_t i = 0; i < __vector_table_ram_size; i++) { + __vector_table_ram_start[i] = __vector_rom_start[i]; + } +#endif + + return 1; +} +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash.icf deleted file mode 100644 index 934bafc3051..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash.icf +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region XPI0 = [from 0x80000000 + 0x3000, size _flash_size - 0x3000]; /* XPI0 */ -define region ILM = [from 0x00000000 size 256k]; /* ILM */ -define region DLM = [from 0x00080000 size 256k]; /* DLM */ -define region AXI_SRAM = [from 0x01080000 size 512k]; /* AXI SRAM0 */ -define region NONCACHEABLE_RAM = [from 0x01100000 size 256k]; /* AXI SRAM1 */ -define region SHARE_RAM = [from 0x0117C000 size 16k]; -define region AHB_SRAM = [from 0xF0300000 size 32k]; -define region APB_SRAM = [from 0xF40F0000 size 8k]; - -assert (__STACKSIZE__ + __HEAPSIZE__) <= 256k with error "stack and heap total size larger than 256k"; - -/* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; - - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; - -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; - -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -/* Initialization */ -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place at start of XPI0 with fixed order { symbol _start}; - -place at start of ILM with fixed order { block vectors }; - -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { - section .fast, section .fast.*, // "ramfunc" section - }; - -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; - -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - - -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in APB_SRAM { section .backup_sram}; // Backup SRAM memory -place in DLM { section .fast_ram}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_uf2.icf deleted file mode 100644 index c8a224459db..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_uf2.icf +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -/* Regions */ -define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */ -define region ILM = [from 0x00000000 size 256k]; /* ILM */ -define region DLM = [from 0x00080000 size 256k]; /* DLM */ -define region AXI_SRAM = [from 0x01080000 size 768k]; /* AXI SRAM */ -define region SHARE_RAM = [from 0x0117C000 size 16k]; -define region AHB_SRAM = [from 0xF0300000 size 32k]; -define region APB_SRAM = [from 0xF40F0000 size 8k]; -define region SDRAM = [from 0x40000000 size _extram_size - 4M]; -define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M]; - -/* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; - - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; - -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; - -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -/* Initialization */ -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place at start of XPI0 with fixed order { section .uf2_signature }; -place in XPI0 with fixed order { symbol _start }; - - -place at start of ILM with fixed order { block vectors }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { - section .fast, section .fast.*, // "ramfunc" section - }; - -place in SDRAM { block cherryusb_usbh_class_info }; -place in SDRAM { block framebuffer }; - -place in AXI_SRAM then SDRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - - -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in APB_SRAM { section .backup_sram}; // Backup SRAM memory -place in DLM { section .fast_ram}; // Fast access memory -place in SDRAM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .uf2_signature }; -keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_xip.icf deleted file mode 100644 index 13fc9264f4b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_xip.icf +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region NOR_CFG_OPTION = [ from 0x80000400 size 0x0C00 ]; -define region BOOT_HEADER = [ from 0x80001000 size 0x2000 ]; -define region XPI0 = [from 0x80003000 size (_flash_size - 0x3000) ]; /* XPI0 */ -define region ILM = [from 0x00000000 size 256k]; /* ILM */ -define region DLM = [from 0x00080000 size 256k]; /* DLM */ -define region AXI_SRAM = [from 0x01080000 size 768k]; /* AXI SRAM */ -define region SHARE_RAM = [from 0x0117C000 size 16k]; -define region AHB_SRAM = [from 0xF0300000 size 32k]; -define region APB_SRAM = [from 0xF40F0000 size 8k]; -define region SDRAM = [from 0x40000000 size _extram_size - 4M]; -define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M]; - -/* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; -define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; -define exported symbol __app_load_addr__ = start of region XPI0; -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size of block boot_header; -define exported symbol __fw_size__ = 0x1000; - -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; - -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; - -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -/* Initialization */ -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.*, section .text.*nx* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER with fixed order { block boot_header }; -place at start of XPI0 with fixed order { symbol _start}; -place at start of ILM with fixed order { block vectors }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { - section .fast, section .fast.*, section .text.*nx*, // "ramfunc" section - }; - -place in SDRAM { block cherryusb_usbh_class_info }; -place in SDRAM { block framebuffer }; - -place in AXI_SRAM then SDRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - - -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in APB_SRAM { section .backup_sram}; // Backup SRAM memory -place in DLM { section .fast_ram}; // Fast access memory -place in SDRAM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; -keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_uf2.icf deleted file mode 100644 index 258d55b101c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_uf2.icf +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -/* Regions */ -define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */ -define region ILM = [from 0x00000000 size 256k]; /* ILM */ -define region DLM = [from 0x00080000 size 256k]; /* DLM */ -define region AXI_SRAM = [from 0x01080000 size 512k]; /* AXI SRAM0 */ -define region NONCACHEABLE_RAM = [from 0x01100000 size 256k]; /* AXI SRAM1 */ -define region SHARE_RAM = [from 0x0117C000 size 16k]; -define region AHB_SRAM = [from 0xF0300000 size 32k]; -define region APB_SRAM = [from 0xF40F0000 size 8k]; - -assert (__STACKSIZE__ + __HEAPSIZE__) <= 256k with error "stack and heap total size larger than 256k"; - -/* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; - -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; - -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -/* Initialization */ -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -initialize by copy { block vectors }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place at start of XPI0 with fixed order { section .uf2_signature }; -place in XPI0 with fixed order { symbol _start }; - -place at start of ILM with fixed order { block vectors }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { - section .fast, section .fast.*, // "ramfunc" section - }; - -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; - -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - - -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in APB_SRAM { section .backup_sram}; // Backup SRAM memory -place in DLM { section .fast_ram}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .uf2_signature }; -keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_xip.icf deleted file mode 100644 index 48c4804fef8..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_xip.icf +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region NOR_CFG_OPTION = [ from 0x80000400 size 0x0C00 ]; -define region BOOT_HEADER = [ from 0x80001000 size 0x2000 ]; -define region XPI0 = [from 0x80003000 size (_flash_size - 0x3000) ]; /* XPI0 */ -define region ILM = [from 0x00000000 size 256k]; /* ILM */ -define region DLM = [from 0x00080000 size 256k]; /* DLM */ -define region AXI_SRAM = [from 0x01080000 size 512k]; /* AXI SRAM0 */ -define region NONCACHEABLE_RAM = [from 0x01100000 size 256k]; /* AXI SRAM1 */ -define region SHARE_RAM = [from 0x0117C000 size 16k]; -define region AHB_SRAM = [from 0xF0300000 size 32k]; -define region APB_SRAM = [from 0xF40F0000 size 8k]; - -assert (__STACKSIZE__ + __HEAPSIZE__) <= 256k with error "stack and heap total size larger than 256k"; - -/* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; -define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; -define exported symbol __app_load_addr__ = start of region XPI0; -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size of block boot_header; -define exported symbol __fw_size__ = 0x1000; - -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; - -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; - -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -/* Initialization */ -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.*, section .text.*nx* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER with fixed order { block boot_header }; -place at start of XPI0 with fixed order { symbol _start}; -place at start of ILM with fixed order { block vectors }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { - section .fast, section .fast.*, section .text.*nx*, // "ramfunc" section - }; - -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; - -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - - -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in APB_SRAM { section .backup_sram}; // Backup SRAM memory -place in DLM { section .fast_ram}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; -keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram.icf deleted file mode 100644 index 4476af4ceb8..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram.icf +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define memory with size = 4G; - -/* Regions */ -define region ILM = [from 0x00000000 size 256k]; /* ILM */ -define region DLM = [from 0x00080000 size 256k]; /* DLM */ -define region AXI_SRAM = [from 0x01080000 size 512k]; /* AXI SRAM0 */ -define region NONCACHEABLE_RAM = [from 0x01100000 size 256k]; /* AXI SRAM1 */ -define region SHARE_RAM = [from 0x0117C000 size 16k]; -define region AHB_SRAM = [from 0xF0300000 size 32k]; -define region APB_SRAM = [from 0xF40F0000 size 8k]; - -assert (__STACKSIZE__ + __HEAPSIZE__) <= 256k with error "stack and heap total size larger than 256k"; - -/* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block cherryusb_usbh_class_info { section .usbh_class_info }; -define block framebuffer { section .framebuffer }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; - -define exported symbol _stack = end of block stack + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -/* Initialization */ -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -/* Placement */ -place at start of ILM { symbol _start }; -place in ILM { block vectors }; // Vector table section -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in ILM with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in APB_SRAM { section .backup_sram}; // Backup SRAM memory -place in DLM { section .fast_ram}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram_core1.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram_core1.icf deleted file mode 100644 index 1c778b03896..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram_core1.icf +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region ILM = [from 0x00000000 size 256k]; /* ILM */ -define region DLM = [from 0x00080000 size 256k]; /* DLM */ -define region NONCACHEABLE_RAM = [from 0x01140000 size 64k]; /* AXI SRAM1 */ -define region AXI_SRAM = [from 0x01150000 size 176k]; -define region SHARE_RAM = [from 0x0117C000 size 16k]; - -assert (__STACKSIZE__ + __HEAPSIZE__) <= 256k with error "stack and heap total size larger than 256k"; - -/* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block cherryusb_usbh_class_info { section .usbh_class_info }; -define block framebuffer { section .framebuffer }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; - -define exported symbol _stack = end of block stack + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -/* Initialization */ -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -/* Placement */ -place at start of ILM { symbol _start }; -place in ILM { block vectors }; // Vector table section -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in ILM with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in DLM { section .fast_ram}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/startup.s b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/startup.s deleted file mode 100644 index 3b6c089188c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/startup.s +++ /dev/null @@ -1,390 +0,0 @@ -/********************************************************************* -* SEGGER Microcontroller GmbH * -* The Embedded Experts * -********************************************************************** -* * -* (c) 2014 - 2021 SEGGER Microcontroller GmbH * -* * -* www.segger.com Support: support@segger.com * -* * -********************************************************************** -* * -* All rights reserved. * -* * -* Redistribution and use in source and binary forms, with or * -* without modification, are permitted provided that the following * -* condition is met: * -* * -* - Redistributions of source code must retain the above copyright * -* notice, this condition and the following disclaimer. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * -* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * -* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * -* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * -* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * -* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * -* DAMAGE. * -* * -********************************************************************** - --------------------------- END-OF-HEADER ----------------------------- - -File : SEGGER_RISCV_crt0.s -Purpose : Generic runtime init startup code for RISC-V CPUs. - Designed to work with the SEGGER linker to produce - smallest possible executables. - - This file does not normally require any customization. - -Additional information: - Preprocessor Definitions - FULL_LIBRARY - If defined then - - argc, argv are set up by calling SEGGER_SEMIHOST_GetArgs(). - - the exit symbol is defined and executes on return from main. - - the exit symbol calls destructors, atexit functions and then - calls SEGGER_SEMIHOST_Exit(). - - If not defined then - - argc and argv are not valid (main is assumed to not take parameters) - - the exit symbol is defined, executes on return from main and - halts in a loop. -*/ - -#include "hpm_csr_regs.h" - -/********************************************************************* -* -* Defines, configurable -* -********************************************************************** -*/ -#ifndef APP_ENTRY_POINT - #define APP_ENTRY_POINT reset_handler -#endif - -#ifndef ARGSSPACE - #define ARGSSPACE 128 -#endif - -/********************************************************************* -* -* Macros -* -********************************************************************** -*/ -// -// Declare a label as function symbol (without switching sections) -// -.macro MARK_FUNC Name - .global \Name - .type \Name, function -\Name: -.endm - -// -// Declare a regular function. -// Functions from the startup are placed in the init section. -// -.macro START_FUNC Name - .section .init.\Name, "ax" - .global \Name -#if __riscv_compressed - .balign 2 -#else - .balign 4 -#endif - .type \Name, function -\Name: -.endm - -// -// Declare a weak function -// -.macro WEAK_FUNC Name - .section .init.\Name, "ax", %progbits - .global \Name - .weak \Name -#if __riscv_compressed - .balign 2 -#else - .balign 4 -#endif - .type \Name, function -\Name: -.endm - -// -// Mark the end of a function and calculate its size -// -.macro END_FUNC name - .size \name,.-\name -.endm - -/********************************************************************* -* -* Externals -* -********************************************************************** -*/ - .extern APP_ENTRY_POINT // typically main - -/********************************************************************* -* -* Global functions -* -********************************************************************** -*/ -/********************************************************************* -* -* _start -* -* Function description -* Entry point for the startup code. -* Usually called by the reset handler. -* Performs all initialisation, based on the entries in the -* linker-generated init table, then calls main(). -* It is device independent, so there should not be any need for an -* end-user to modify it. -* -* Additional information -* At this point, the stack pointer should already have been -* initialized -* - by hardware (such as on Cortex-M), -* - by the device-specific reset handler, -* - or by the debugger (such as for RAM Code). -*/ -#undef L -#define L(label) .L_start_##label - -START_FUNC _start - .option push - .option norelax - lui gp, %hi(__global_pointer$) - addi gp, gp, %lo(__global_pointer$) - lui tp, %hi(__thread_pointer$) - addi tp, tp, %lo(__thread_pointer$) - .option pop - - csrw mstatus, zero - csrw mcause, zero - -#ifdef __riscv_flen - /* Enable FPU */ - li t0, CSR_MSTATUS_FS_MASK - csrrs t0, mstatus, t0 - - /* Initialize FCSR */ - fscsr zero -#endif - -#ifdef INIT_EXT_RAM_FOR_DATA - la t0, _stack_safe - mv sp, t0 - call _init_ext_ram -#endif - - lui t0, %hi(__stack_end__) - addi sp, t0, %lo(__stack_end__) - -#ifndef __NO_SYSTEM_INIT - // - // Call _init - // - call _init -#endif - // - // Call linker init functions which in turn performs the following: - // * Perform segment init - // * Perform heap init (if used) - // * Call constructors of global Objects (if any exist) - // - la s0, __SEGGER_init_table__ // Set table pointer to start of initialization table -L(RunInit): - lw a0, (s0) // Get next initialization function from table - add s0, s0, 4 // Increment table pointer to point to function arguments - jalr a0 // Call initialization function - j L(RunInit) - // -MARK_FUNC __SEGGER_init_done - // - // Time to call main(), the application entry point. - // - -#ifndef NO_CLEANUP_AT_START - /* clean up */ - call _clean_up -#endif - -#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS - #define HANDLER_TRAP freertos_risc_v_trap_handler - #define HANDLER_S_TRAP freertos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III - #define HANDLER_TRAP ucos_risc_v_trap_handler - #define HANDLER_S_TRAP ucos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_THREADX) && CONFIG_THREADX - #define HANDLER_TRAP tx_risc_v_trap_handler - #define HANDLER_S_TRAP tx_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#else - #define HANDLER_TRAP irq_handler_trap - #define HANDLER_S_TRAP irq_handler_s_trap -#endif - -#ifndef USE_NONVECTOR_MODE - /* Initial machine trap-vector Base */ - la t0, __vector_table - csrw mtvec, t0 - - /* Enable vectored external PLIC interrupt */ - csrsi CSR_MMISC_CTL, 2 -#else - /* Initial machine trap-vector Base */ - la t0, HANDLER_TRAP - csrw mtvec, t0 - - /* Disable vectored external PLIC interrupt */ - csrci CSR_MMISC_CTL, 2 -#endif - -MARK_FUNC start -#ifndef FULL_LIBRARY - // - // In a real embedded application ("Free-standing environment"), - // main() does not get any arguments, - // which means it is not necessary to init a0 and a1. - // - call APP_ENTRY_POINT - tail exit - -END_FUNC _start - // - // end of _start - // Fall-through to exit if main ever returns. - // -MARK_FUNC exit - // - // In a free-standing environment, if returned from application: - // Loop forever. - // - j . - .size exit,.-exit -#else - // - // In a hosted environment, - // we need to load a0 and a1 with argc and argv, in order to handle - // the command line arguments. - // This is required for some programs running under control of a - // debugger, such as automated tests. - // - li a0, ARGSSPACE - la a1, args - call debug_getargs - li a0, ARGSSPACE - la a1, args - - call APP_ENTRY_POINT // Call to application entry point (usually main()) - call exit // Call exit function - j . // If we unexpectedly return from exit, hang. -END_FUNC _start -#endif - -#ifdef FULL_LIBRARY - li a0, ARGSSPACE - la a1, args - call debug_getargs - li a0, ARGSSPACE - la a1, args -#else - li a0, 0 - li a1, 0 -#endif - - call APP_ENTRY_POINT - tail exit - -END_FUNC _start - - // -#ifdef FULL_LIBRARY -/********************************************************************* -* -* exit -* -* Function description -* Exit of the system. -* Called on return from application entry point or explicit call -* to exit. -* -* Additional information -* In a hosted environment exit gracefully, by -* saving the return value, -* calling destructurs of global objects, -* calling registered atexit functions, -* and notifying the host/debugger. -*/ -#undef L -#define L(label) .L_exit_##label - -WEAK_FUNC exit - mv s1, a0 // Save the exit parameter/return result - // - // Call destructors - // - la s0, __dtors_start__ -L(Loop): - la t0, __dtors_end__ - beq s0, t0, L(End) - lw t1, 0(s0) - addi s0, s0, 4 - jalr t1 - j L(Loop) -L(End): - // - // Call atexit functions - // - call _execute_at_exit_fns - // - // Call debug_exit with return result/exit parameter - // - mv a0, s1 - call debug_exit - // - // If execution is not terminated, loop forever - // -L(ExitLoop): - j L(ExitLoop) // Loop forever. -END_FUNC exit -#endif - -#ifdef FULL_LIBRARY - .bss -args: - .space ARGSSPACE - .size args, .-args - .type args, %object -#endif - - .section .isr_vector, "ax" - .weak nmi_handler -nmi_handler: -1: j 1b - -#include "../vectors.h" - -/*************************** End of file ****************************/ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/trap.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/trap.c index ae000f40050..f812f2c2730 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/trap.c +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -8,6 +8,10 @@ #include "hpm_common.h" #include "hpm_soc.h" +#ifdef __ICCRISCV__ +#pragma language = extended +#endif + /********************** MCAUSE exception types **************************************/ #define MCAUSE_INSTR_ADDR_MISALIGNED (0U) //!< Instruction Address misaligned #define MCAUSE_INSTR_ACCESS_FAULT (1U) //!< Instruction access fault @@ -48,6 +52,11 @@ __attribute__((weak)) void swi_isr(void) __attribute__((weak)) void syscall_handler(long n, long a0, long a1, long a2, long a3) { + (void) n; + (void) a0; + (void) a1; + (void) a2; + (void) a3; } __attribute__((weak)) long exception_handler(long cause, long epc) @@ -88,11 +97,17 @@ __attribute__((weak)) long exception_handler(long cause, long epc) return epc; } -#if !defined(CONFIG_FREERTOS) && !defined(CONFIG_UCOS_III) && !defined(CONFIG_THREADX) -void irq_handler_trap(void) __attribute__ ((section(".isr_vector"), interrupt("machine"), aligned(4))); +#if !defined(CONFIG_FREERTOS) && !defined(CONFIG_UCOS_III) && !defined(CONFIG_THREADX) && !defined(CONFIG_RTTHREAD) +HPM_ATTR_MACHINE_INTERRUPT void irq_handler_trap(void); +#define IRQ_HANDLER_TRAP_AS_ISR 1 #else void irq_handler_trap(void) __attribute__ ((section(".isr_vector"))); #endif + +#if defined(__ICCRISCV__) && (IRQ_HANDLER_TRAP_AS_ISR == 1) +extern int __vector_table[]; +HPM_ATTR_MACHINE_INTERRUPT +#endif void irq_handler_trap(void) { long mcause = read_csr(CSR_MCAUSE); diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/vectors.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/vectors.h index c1ab56467bb..6eb11a1eadd 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/vectors.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/vectors.h @@ -1,9 +1,290 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ +#ifdef __IAR_SYSTEMS_ASM__ + +IRQ_HANDLER macro + dc32 default_isr_\1 + endm + +IRQ_DEFAULT_HANDLER macro + PUBWEAK default_isr_\1 +default_isr_\1 + j default_irq_handler + endm + + SECTION `.isr_vector`:CODE:ROOT(9) + PUBWEAK default_irq_handler +default_irq_handler + j default_irq_handler + IRQ_DEFAULT_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_DEFAULT_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_DEFAULT_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_DEFAULT_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_DEFAULT_HANDLER 5 /* GPIO0_E IRQ handler */ + IRQ_DEFAULT_HANDLER 6 /* GPIO0_F IRQ handler */ + IRQ_DEFAULT_HANDLER 7 /* GPIO0_X IRQ handler */ + IRQ_DEFAULT_HANDLER 8 /* GPIO0_Y IRQ handler */ + IRQ_DEFAULT_HANDLER 9 /* GPIO0_Z IRQ handler */ + IRQ_DEFAULT_HANDLER 10 /* GPIO1_A IRQ handler */ + IRQ_DEFAULT_HANDLER 11 /* GPIO1_B IRQ handler */ + IRQ_DEFAULT_HANDLER 12 /* GPIO1_C IRQ handler */ + IRQ_DEFAULT_HANDLER 13 /* GPIO1_D IRQ handler */ + IRQ_DEFAULT_HANDLER 14 /* GPIO1_E IRQ handler */ + IRQ_DEFAULT_HANDLER 15 /* GPIO1_F IRQ handler */ + IRQ_DEFAULT_HANDLER 16 /* GPIO1_X IRQ handler */ + IRQ_DEFAULT_HANDLER 17 /* GPIO1_Y IRQ handler */ + IRQ_DEFAULT_HANDLER 18 /* GPIO1_Z IRQ handler */ + IRQ_DEFAULT_HANDLER 19 /* ADC0 IRQ handler */ + IRQ_DEFAULT_HANDLER 20 /* ADC1 IRQ handler */ + IRQ_DEFAULT_HANDLER 21 /* ADC2 IRQ handler */ + IRQ_DEFAULT_HANDLER 22 /* ADC3 IRQ handler */ + IRQ_DEFAULT_HANDLER 23 /* ACMP[0] IRQ handler */ + IRQ_DEFAULT_HANDLER 24 /* ACMP[1] IRQ handler */ + IRQ_DEFAULT_HANDLER 25 /* ACMP[2] IRQ handler */ + IRQ_DEFAULT_HANDLER 26 /* ACMP[3] IRQ handler */ + IRQ_DEFAULT_HANDLER 27 /* SPI0 IRQ handler */ + IRQ_DEFAULT_HANDLER 28 /* SPI1 IRQ handler */ + IRQ_DEFAULT_HANDLER 29 /* SPI2 IRQ handler */ + IRQ_DEFAULT_HANDLER 30 /* SPI3 IRQ handler */ + IRQ_DEFAULT_HANDLER 31 /* UART0 IRQ handler */ + IRQ_DEFAULT_HANDLER 32 /* UART1 IRQ handler */ + IRQ_DEFAULT_HANDLER 33 /* UART2 IRQ handler */ + IRQ_DEFAULT_HANDLER 34 /* UART3 IRQ handler */ + IRQ_DEFAULT_HANDLER 35 /* UART4 IRQ handler */ + IRQ_DEFAULT_HANDLER 36 /* UART5 IRQ handler */ + IRQ_DEFAULT_HANDLER 37 /* UART6 IRQ handler */ + IRQ_DEFAULT_HANDLER 38 /* UART7 IRQ handler */ + IRQ_DEFAULT_HANDLER 39 /* UART8 IRQ handler */ + IRQ_DEFAULT_HANDLER 40 /* UART9 IRQ handler */ + IRQ_DEFAULT_HANDLER 41 /* UART10 IRQ handler */ + IRQ_DEFAULT_HANDLER 42 /* UART11 IRQ handler */ + IRQ_DEFAULT_HANDLER 43 /* UART12 IRQ handler */ + IRQ_DEFAULT_HANDLER 44 /* UART13 IRQ handler */ + IRQ_DEFAULT_HANDLER 45 /* UART14 IRQ handler */ + IRQ_DEFAULT_HANDLER 46 /* UART15 IRQ handler */ + IRQ_DEFAULT_HANDLER 47 /* CAN0 IRQ handler */ + IRQ_DEFAULT_HANDLER 48 /* CAN1 IRQ handler */ + IRQ_DEFAULT_HANDLER 49 /* CAN2 IRQ handler */ + IRQ_DEFAULT_HANDLER 50 /* CAN3 IRQ handler */ + IRQ_DEFAULT_HANDLER 51 /* PTPC IRQ handler */ + IRQ_DEFAULT_HANDLER 52 /* WDG0 IRQ handler */ + IRQ_DEFAULT_HANDLER 53 /* WDG1 IRQ handler */ + IRQ_DEFAULT_HANDLER 54 /* WDG2 IRQ handler */ + IRQ_DEFAULT_HANDLER 55 /* WDG3 IRQ handler */ + IRQ_DEFAULT_HANDLER 56 /* MBX0A IRQ handler */ + IRQ_DEFAULT_HANDLER 57 /* MBX0B IRQ handler */ + IRQ_DEFAULT_HANDLER 58 /* MBX1A IRQ handler */ + IRQ_DEFAULT_HANDLER 59 /* MBX1B IRQ handler */ + IRQ_DEFAULT_HANDLER 60 /* GPTMR0 IRQ handler */ + IRQ_DEFAULT_HANDLER 61 /* GPTMR1 IRQ handler */ + IRQ_DEFAULT_HANDLER 62 /* GPTMR2 IRQ handler */ + IRQ_DEFAULT_HANDLER 63 /* GPTMR3 IRQ handler */ + IRQ_DEFAULT_HANDLER 64 /* GPTMR4 IRQ handler */ + IRQ_DEFAULT_HANDLER 65 /* GPTMR5 IRQ handler */ + IRQ_DEFAULT_HANDLER 66 /* GPTMR6 IRQ handler */ + IRQ_DEFAULT_HANDLER 67 /* GPTMR7 IRQ handler */ + IRQ_DEFAULT_HANDLER 68 /* I2C0 IRQ handler */ + IRQ_DEFAULT_HANDLER 69 /* I2C1 IRQ handler */ + IRQ_DEFAULT_HANDLER 70 /* I2C2 IRQ handler */ + IRQ_DEFAULT_HANDLER 71 /* I2C3 IRQ handler */ + IRQ_DEFAULT_HANDLER 72 /* PWM0 IRQ handler */ + IRQ_DEFAULT_HANDLER 73 /* HALL0 IRQ handler */ + IRQ_DEFAULT_HANDLER 74 /* QEI0 IRQ handler */ + IRQ_DEFAULT_HANDLER 75 /* PWM1 IRQ handler */ + IRQ_DEFAULT_HANDLER 76 /* HALL1 IRQ handler */ + IRQ_DEFAULT_HANDLER 77 /* QEI1 IRQ handler */ + IRQ_DEFAULT_HANDLER 78 /* PWM2 IRQ handler */ + IRQ_DEFAULT_HANDLER 79 /* HALL2 IRQ handler */ + IRQ_DEFAULT_HANDLER 80 /* QEI2 IRQ handler */ + IRQ_DEFAULT_HANDLER 81 /* PWM3 IRQ handler */ + IRQ_DEFAULT_HANDLER 82 /* HALL3 IRQ handler */ + IRQ_DEFAULT_HANDLER 83 /* QEI3 IRQ handler */ + IRQ_DEFAULT_HANDLER 84 /* SDP IRQ handler */ + IRQ_DEFAULT_HANDLER 85 /* XPI0 IRQ handler */ + IRQ_DEFAULT_HANDLER 86 /* XPI1 IRQ handler */ + IRQ_DEFAULT_HANDLER 87 /* XDMA IRQ handler */ + IRQ_DEFAULT_HANDLER 88 /* HDMA IRQ handler */ + IRQ_DEFAULT_HANDLER 89 /* FEMC IRQ handler */ + IRQ_DEFAULT_HANDLER 90 /* RNG IRQ handler */ + IRQ_DEFAULT_HANDLER 91 /* I2S0 IRQ handler */ + IRQ_DEFAULT_HANDLER 92 /* I2S1 IRQ handler */ + IRQ_DEFAULT_HANDLER 93 /* I2S2 IRQ handler */ + IRQ_DEFAULT_HANDLER 94 /* I2S3 IRQ handler */ + IRQ_DEFAULT_HANDLER 95 /* DAO IRQ handler */ + IRQ_DEFAULT_HANDLER 96 /* PDM IRQ handler */ + IRQ_DEFAULT_HANDLER 97 /* CAM0 IRQ handler */ + IRQ_DEFAULT_HANDLER 98 /* CAM1 IRQ handler */ + IRQ_DEFAULT_HANDLER 99 /* LCDC_D0 IRQ handler */ + IRQ_DEFAULT_HANDLER 100 /* LCDC_D1 IRQ handler */ + IRQ_DEFAULT_HANDLER 101 /* PDMA_D0 IRQ handler */ + IRQ_DEFAULT_HANDLER 102 /* PDMA_D1 IRQ handler */ + IRQ_DEFAULT_HANDLER 103 /* JPEG IRQ handler */ + IRQ_DEFAULT_HANDLER 104 /* NTMR0 IRQ handler */ + IRQ_DEFAULT_HANDLER 105 /* NTMR1 IRQ handler */ + IRQ_DEFAULT_HANDLER 106 /* USB0 IRQ handler */ + IRQ_DEFAULT_HANDLER 107 /* USB1 IRQ handler */ + IRQ_DEFAULT_HANDLER 108 /* ENET0 IRQ handler */ + IRQ_DEFAULT_HANDLER 109 /* ENET1 IRQ handler */ + IRQ_DEFAULT_HANDLER 110 /* SDXC0 IRQ handler */ + IRQ_DEFAULT_HANDLER 111 /* SDXC1 IRQ handler */ + IRQ_DEFAULT_HANDLER 112 /* PSEC IRQ handler */ + IRQ_DEFAULT_HANDLER 113 /* PGPIO IRQ handler */ + IRQ_DEFAULT_HANDLER 114 /* PWDG IRQ handler */ + IRQ_DEFAULT_HANDLER 115 /* PTMR IRQ handler */ + IRQ_DEFAULT_HANDLER 116 /* PUART IRQ handler */ + IRQ_DEFAULT_HANDLER 117 /* VAD IRQ handler */ + IRQ_DEFAULT_HANDLER 118 /* FUSE IRQ handler */ + IRQ_DEFAULT_HANDLER 119 /* SECMON IRQ handler */ + IRQ_DEFAULT_HANDLER 120 /* RTC IRQ handler */ + IRQ_DEFAULT_HANDLER 121 /* BUTN IRQ handler */ + IRQ_DEFAULT_HANDLER 122 /* BGPIO IRQ handler */ + IRQ_DEFAULT_HANDLER 123 /* BVIO IRQ handler */ + IRQ_DEFAULT_HANDLER 124 /* BROWNOUT IRQ handler */ + IRQ_DEFAULT_HANDLER 125 /* SYSCTL IRQ handler */ + IRQ_DEFAULT_HANDLER 126 /* DEBUG[0] IRQ handler */ + IRQ_DEFAULT_HANDLER 127 /* DEBUG[1] IRQ handler */ + + EXTERN irq_handler_trap + SECTION `.vector_table`:CODE:ROOT(9) + PUBLIC __vector_table + DATA + +__vector_table + dc32 irq_handler_trap + IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_HANDLER 5 /* GPIO0_E IRQ handler */ + IRQ_HANDLER 6 /* GPIO0_F IRQ handler */ + IRQ_HANDLER 7 /* GPIO0_X IRQ handler */ + IRQ_HANDLER 8 /* GPIO0_Y IRQ handler */ + IRQ_HANDLER 9 /* GPIO0_Z IRQ handler */ + IRQ_HANDLER 10 /* GPIO1_A IRQ handler */ + IRQ_HANDLER 11 /* GPIO1_B IRQ handler */ + IRQ_HANDLER 12 /* GPIO1_C IRQ handler */ + IRQ_HANDLER 13 /* GPIO1_D IRQ handler */ + IRQ_HANDLER 14 /* GPIO1_E IRQ handler */ + IRQ_HANDLER 15 /* GPIO1_F IRQ handler */ + IRQ_HANDLER 16 /* GPIO1_X IRQ handler */ + IRQ_HANDLER 17 /* GPIO1_Y IRQ handler */ + IRQ_HANDLER 18 /* GPIO1_Z IRQ handler */ + IRQ_HANDLER 19 /* ADC0 IRQ handler */ + IRQ_HANDLER 20 /* ADC1 IRQ handler */ + IRQ_HANDLER 21 /* ADC2 IRQ handler */ + IRQ_HANDLER 22 /* ADC3 IRQ handler */ + IRQ_HANDLER 23 /* ACMP[0] IRQ handler */ + IRQ_HANDLER 24 /* ACMP[1] IRQ handler */ + IRQ_HANDLER 25 /* ACMP[2] IRQ handler */ + IRQ_HANDLER 26 /* ACMP[3] IRQ handler */ + IRQ_HANDLER 27 /* SPI0 IRQ handler */ + IRQ_HANDLER 28 /* SPI1 IRQ handler */ + IRQ_HANDLER 29 /* SPI2 IRQ handler */ + IRQ_HANDLER 30 /* SPI3 IRQ handler */ + IRQ_HANDLER 31 /* UART0 IRQ handler */ + IRQ_HANDLER 32 /* UART1 IRQ handler */ + IRQ_HANDLER 33 /* UART2 IRQ handler */ + IRQ_HANDLER 34 /* UART3 IRQ handler */ + IRQ_HANDLER 35 /* UART4 IRQ handler */ + IRQ_HANDLER 36 /* UART5 IRQ handler */ + IRQ_HANDLER 37 /* UART6 IRQ handler */ + IRQ_HANDLER 38 /* UART7 IRQ handler */ + IRQ_HANDLER 39 /* UART8 IRQ handler */ + IRQ_HANDLER 40 /* UART9 IRQ handler */ + IRQ_HANDLER 41 /* UART10 IRQ handler */ + IRQ_HANDLER 42 /* UART11 IRQ handler */ + IRQ_HANDLER 43 /* UART12 IRQ handler */ + IRQ_HANDLER 44 /* UART13 IRQ handler */ + IRQ_HANDLER 45 /* UART14 IRQ handler */ + IRQ_HANDLER 46 /* UART15 IRQ handler */ + IRQ_HANDLER 47 /* CAN0 IRQ handler */ + IRQ_HANDLER 48 /* CAN1 IRQ handler */ + IRQ_HANDLER 49 /* CAN2 IRQ handler */ + IRQ_HANDLER 50 /* CAN3 IRQ handler */ + IRQ_HANDLER 51 /* PTPC IRQ handler */ + IRQ_HANDLER 52 /* WDG0 IRQ handler */ + IRQ_HANDLER 53 /* WDG1 IRQ handler */ + IRQ_HANDLER 54 /* WDG2 IRQ handler */ + IRQ_HANDLER 55 /* WDG3 IRQ handler */ + IRQ_HANDLER 56 /* MBX0A IRQ handler */ + IRQ_HANDLER 57 /* MBX0B IRQ handler */ + IRQ_HANDLER 58 /* MBX1A IRQ handler */ + IRQ_HANDLER 59 /* MBX1B IRQ handler */ + IRQ_HANDLER 60 /* GPTMR0 IRQ handler */ + IRQ_HANDLER 61 /* GPTMR1 IRQ handler */ + IRQ_HANDLER 62 /* GPTMR2 IRQ handler */ + IRQ_HANDLER 63 /* GPTMR3 IRQ handler */ + IRQ_HANDLER 64 /* GPTMR4 IRQ handler */ + IRQ_HANDLER 65 /* GPTMR5 IRQ handler */ + IRQ_HANDLER 66 /* GPTMR6 IRQ handler */ + IRQ_HANDLER 67 /* GPTMR7 IRQ handler */ + IRQ_HANDLER 68 /* I2C0 IRQ handler */ + IRQ_HANDLER 69 /* I2C1 IRQ handler */ + IRQ_HANDLER 70 /* I2C2 IRQ handler */ + IRQ_HANDLER 71 /* I2C3 IRQ handler */ + IRQ_HANDLER 72 /* PWM0 IRQ handler */ + IRQ_HANDLER 73 /* HALL0 IRQ handler */ + IRQ_HANDLER 74 /* QEI0 IRQ handler */ + IRQ_HANDLER 75 /* PWM1 IRQ handler */ + IRQ_HANDLER 76 /* HALL1 IRQ handler */ + IRQ_HANDLER 77 /* QEI1 IRQ handler */ + IRQ_HANDLER 78 /* PWM2 IRQ handler */ + IRQ_HANDLER 79 /* HALL2 IRQ handler */ + IRQ_HANDLER 80 /* QEI2 IRQ handler */ + IRQ_HANDLER 81 /* PWM3 IRQ handler */ + IRQ_HANDLER 82 /* HALL3 IRQ handler */ + IRQ_HANDLER 83 /* QEI3 IRQ handler */ + IRQ_HANDLER 84 /* SDP IRQ handler */ + IRQ_HANDLER 85 /* XPI0 IRQ handler */ + IRQ_HANDLER 86 /* XPI1 IRQ handler */ + IRQ_HANDLER 87 /* XDMA IRQ handler */ + IRQ_HANDLER 88 /* HDMA IRQ handler */ + IRQ_HANDLER 89 /* FEMC IRQ handler */ + IRQ_HANDLER 90 /* RNG IRQ handler */ + IRQ_HANDLER 91 /* I2S0 IRQ handler */ + IRQ_HANDLER 92 /* I2S1 IRQ handler */ + IRQ_HANDLER 93 /* I2S2 IRQ handler */ + IRQ_HANDLER 94 /* I2S3 IRQ handler */ + IRQ_HANDLER 95 /* DAO IRQ handler */ + IRQ_HANDLER 96 /* PDM IRQ handler */ + IRQ_HANDLER 97 /* CAM0 IRQ handler */ + IRQ_HANDLER 98 /* CAM1 IRQ handler */ + IRQ_HANDLER 99 /* LCDC_D0 IRQ handler */ + IRQ_HANDLER 100 /* LCDC_D1 IRQ handler */ + IRQ_HANDLER 101 /* PDMA_D0 IRQ handler */ + IRQ_HANDLER 102 /* PDMA_D1 IRQ handler */ + IRQ_HANDLER 103 /* JPEG IRQ handler */ + IRQ_HANDLER 104 /* NTMR0 IRQ handler */ + IRQ_HANDLER 105 /* NTMR1 IRQ handler */ + IRQ_HANDLER 106 /* USB0 IRQ handler */ + IRQ_HANDLER 107 /* USB1 IRQ handler */ + IRQ_HANDLER 108 /* ENET0 IRQ handler */ + IRQ_HANDLER 109 /* ENET1 IRQ handler */ + IRQ_HANDLER 110 /* SDXC0 IRQ handler */ + IRQ_HANDLER 111 /* SDXC1 IRQ handler */ + IRQ_HANDLER 112 /* PSEC IRQ handler */ + IRQ_HANDLER 113 /* PGPIO IRQ handler */ + IRQ_HANDLER 114 /* PWDG IRQ handler */ + IRQ_HANDLER 115 /* PTMR IRQ handler */ + IRQ_HANDLER 116 /* PUART IRQ handler */ + IRQ_HANDLER 117 /* VAD IRQ handler */ + IRQ_HANDLER 118 /* FUSE IRQ handler */ + IRQ_HANDLER 119 /* SECMON IRQ handler */ + IRQ_HANDLER 120 /* RTC IRQ handler */ + IRQ_HANDLER 121 /* BUTN IRQ handler */ + IRQ_HANDLER 122 /* BGPIO IRQ handler */ + IRQ_HANDLER 123 /* BVIO IRQ handler */ + IRQ_HANDLER 124 /* BROWNOUT IRQ handler */ + IRQ_HANDLER 125 /* SYSCTL IRQ handler */ + IRQ_HANDLER 126 /* DEBUG[0] IRQ handler */ + IRQ_HANDLER 127 /* DEBUG[1] IRQ handler */ + +#else + .global default_irq_handler .weak default_irq_handler .align 2 @@ -151,3 +432,5 @@ IRQ_HANDLER 125 /* SYSCTL IRQ handler */ IRQ_HANDLER 126 /* DEBUG[0] IRQ handler */ IRQ_HANDLER 127 /* DEBUG[1] IRQ handler */ + +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/HPM6880_svd.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/HPM6880_svd.xml new file mode 100644 index 00000000000..282d01d1206 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/HPM6880_svd.xml @@ -0,0 +1,54354 @@ + + + HPMICRO + HPM6880 + HPM6800 + 1.0 + HPM6800 device + + /* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + + + other + r0p0 + little + false + true + true + 7 + false + + + + 8 + 32 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + + + FGPIO + FGPIO + GPIO + 0xc0000 + + 0x0 + 0x824 + registers + + + + 16 + 0x10 + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + DI[%s] + no description available + 0x0 + + VALUE + GPIO input value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-only + + + + + + 16 + 0x10 + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + DO[%s] + no description available + 0x100 + + VALUE + GPIO output value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + SET + GPIO output set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + CLEAR + GPIO output clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + TOGGLE + GPIO output toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + + 16 + 0x10 + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + OE[%s] + no description available + 0x200 + + VALUE + GPIO direction value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + SET + GPIO direction set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + CLEAR + GPIO direction clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + TOGGLE + GPIO direction toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + + 16 + 0x10 + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + IF[%s] + no description available + 0x300 + + VALUE + GPIO interrupt flag value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + write-only + + + + + + 16 + 0x10 + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + IE[%s] + no description available + 0x400 + + VALUE + GPIO interrupt enable value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + SET + GPIO interrupt enable set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + CLEAR + GPIO interrupt enable clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + TOGGLE + GPIO interrupt enable toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + + 16 + 0x10 + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + PL[%s] + no description available + 0x500 + + VALUE + GPIO interrupt polarity value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + SET + GPIO interrupt polarity set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + CLEAR + GPIO interrupt polarity clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + TOGGLE + GPIO interrupt polarity toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + + 16 + 0x10 + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + TP[%s] + no description available + 0x600 + + VALUE + GPIO interrupt type value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + SET + GPIO interrupt type set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + CLEAR + GPIO interrupt type clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TOGGLE + GPIO interrupt type toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + + 16 + 0x10 + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + AS[%s] + no description available + 0x700 + + VALUE + GPIO interrupt asynchronous value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + SET + GPIO interrupt asynchronous set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + CLEAR + GPIO interrupt asynchronous clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + TOGGLE + GPIO interrupt asynchronous toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + + + + GPIO0 + GPIO0 + GPIO + 0xf00d0000 + + + PGPIO + PGPIO + GPIO + 0xf411c000 + + + BGPIO + BGPIO + GPIO + 0xf4214000 + + + PLIC + PLIC + PLIC + 0xe4000000 + + 0x0 + 0x202000 + registers + + + + feature + Feature enable register + 0x0 + 32 + 0x00000000 + 0x00000003 + + + VECTORED + Vector mode enable +0: Disabled +1: Enabled + 1 + 1 + read-write + + + PREEMPT + Preemptive priority interrupt enable +0: Disabled +1: Enabled + 0 + 1 + read-write + + + + + 127 + 0x4 + PRIORITY1,PRIORITY2,PRIORITY3,PRIORITY4,PRIORITY5,PRIORITY6,PRIORITY7,PRIORITY8,PRIORITY9,PRIORITY10,PRIORITY11,PRIORITY12,PRIORITY13,PRIORITY14,PRIORITY15,PRIORITY16,PRIORITY17,PRIORITY18,PRIORITY19,PRIORITY20,PRIORITY21,PRIORITY22,PRIORITY23,PRIORITY24,PRIORITY25,PRIORITY26,PRIORITY27,PRIORITY28,PRIORITY29,PRIORITY30,PRIORITY31,PRIORITY32,PRIORITY33,PRIORITY34,PRIORITY35,PRIORITY36,PRIORITY37,PRIORITY38,PRIORITY39,PRIORITY40,PRIORITY41,PRIORITY42,PRIORITY43,PRIORITY44,PRIORITY45,PRIORITY46,PRIORITY47,PRIORITY48,PRIORITY49,PRIORITY50,PRIORITY51,PRIORITY52,PRIORITY53,PRIORITY54,PRIORITY55,PRIORITY56,PRIORITY57,PRIORITY58,PRIORITY59,PRIORITY60,PRIORITY61,PRIORITY62,PRIORITY63,PRIORITY64,PRIORITY65,PRIORITY66,PRIORITY67,PRIORITY68,PRIORITY69,PRIORITY70,PRIORITY71,PRIORITY72,PRIORITY73,PRIORITY74,PRIORITY75,PRIORITY76,PRIORITY77,PRIORITY78,PRIORITY79,PRIORITY80,PRIORITY81,PRIORITY82,PRIORITY83,PRIORITY84,PRIORITY85,PRIORITY86,PRIORITY87,PRIORITY88,PRIORITY89,PRIORITY90,PRIORITY91,PRIORITY92,PRIORITY93,PRIORITY94,PRIORITY95,PRIORITY96,PRIORITY97,PRIORITY98,PRIORITY99,PRIORITY100,PRIORITY101,PRIORITY102,PRIORITY103,PRIORITY104,PRIORITY105,PRIORITY106,PRIORITY107,PRIORITY108,PRIORITY109,PRIORITY110,PRIORITY111,PRIORITY112,PRIORITY113,PRIORITY114,PRIORITY115,PRIORITY116,PRIORITY117,PRIORITY118,PRIORITY119,PRIORITY120,PRIORITY121,PRIORITY122,PRIORITY123,PRIORITY124,PRIORITY125,PRIORITY126,PRIORITY127 + PRIORITY[%s] + no description available + 0x4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + 4 + 0x4 + PENDING0,PENDING1,PENDING2,PENDING3 + PENDING[%s] + no description available + 0x1000 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + 4 + 0x4 + TRIGGER0,TRIGGER1,TRIGGER2,TRIGGER3 + TRIGGER[%s] + no description available + 0x1080 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. +0: Level-triggered interrupt +1: Edge-triggered interrupt + 0 + 32 + read-only + + + + + NUMBER + Number of supported interrupt sources and targets + 0x1100 + 32 + 0xFFFFFFFF + + + NUM_TARGET + The number of supported targets + 16 + 16 + read-only + + + NUM_INTERRUPT + The number of supported interrupt sources + 0 + 16 + read-only + + + + + INFO + Version and the maximum priority + 0x1104 + 32 + 0xFFFFFFFF + + + MAX_PRIORITY + The maximum priority supported + 16 + 16 + read-only + + + VERSION + The version of the PLIC design + 0 + 16 + read-only + + + + + 2 + 0x80 + target0,target1 + TARGETINT[%s] + no description available + 0x2000 + + 4 + 0x4 + INTEN0,INTEN1,INTEN2,INTEN3 + INTEN[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + + 2 + 0x1000 + target0,target1 + TARGETCONFIG[%s] + no description available + 0x200000 + + THRESHOLD + Target0 priority threshold + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + THRESHOLD + Interrupt priority threshold. + 0 + 32 + read-write + + + + + CLAIM + Target claim and complete + 0x4 + 32 + 0x00000000 + 0x000003FF + + + INTERRUPT_ID + On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). + 0 + 10 + read-write + + + + + PPS + Preempted priority stack + 0x400 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY_PREEMPTED + Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. + 0 + 32 + read-write + + + + + + + + MCHTMR + MCHTMR + MCHTMR + 0xe6000000 + + 0x0 + 0x10 + registers + + + + MTIME + Machine Time + 0x0 + 64 + 0x0000000000020210 + 0xFFFFFFFFFFFFFFFF + + + MTIME + Machine time + 0 + 64 + read-write + + + + + MTIMECMP + Machine Time Compare + 0x8 + 64 + 0x0000000000020210 + 0xFFFFFFFFFFFFFFFF + + + MTIMECMP + Machine time compare + 0 + 64 + read-write + + + + + + + PLICSW + PLICSW + PLIC_SW + 0xe6400000 + + 0x1000 + 0x1ff008 + registers + + + + PENDING + Pending status + 0x1000 + 32 + 0x00000000 + 0x00000002 + + + INTERRUPT + writing 1 to trigger software interrupt + 1 + 1 + read-write + + + + + INTEN + Interrupt enable + 0x2000 + 32 + 0x00000000 + 0x00000001 + + + INTERRUPT + enable software interrupt + 0 + 1 + read-write + + + + + CLAIM + Claim and complete. + 0x200004 + 32 + 0x00000000 + 0x00000001 + + + INTERRUPT_ID + On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). + 0 + 1 + read-write + + + + + + + CRC + CRC + CRC + 0xf000c000 + + 0x0 + 0x200 + registers + + + + 8 + 0x40 + 0,1,2,3,4,5,6,7 + CHN[%s] + no description available + 0x0 + + pre_set + &index0 pre set for crc setting + 0x0 + 32 + 0x00000000 + 0x000000FF + + + PRE_SET + 0: no pre set +1: CRC32 +2: CRC32-AUTOSAR +3: CRC16-CCITT +4: CRC16-XMODEM +5: CRC16-MODBUS +1: CRC32 +2: CRC32-autosar +3: CRC16-ccitt +4: CRC16-xmodem +5: CRC16-modbus +6: crc16_dnp +7: crc16_x25 +8: crc16_usb +9: crc16_maxim +10: crc16_ibm +11: crc8_maxim +12: crc8_rohc +13: crc8_itu +14: crc8 +15: crc5_usb + 0 + 8 + read-write + + + + + clr + chn&index0 clear crc result and setting + 0x4 + 32 + 0x00000000 + 0x00000001 + + + CLR + write 1 to clr crc setting and result for its channel. +always read 0. + 0 + 1 + read-write + + + + + poly + chn&index0 poly + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + POLY + poly setting + 0 + 32 + read-write + + + + + init_data + chn&index0 init_data + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + INIT_DATA + initial data of CRC + 0 + 32 + read-write + + + + + xorout + chn&index0 xorout + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + XOROUT + XOR for CRC result + 0 + 32 + read-write + + + + + misc_setting + chn&index0 misc_setting + 0x14 + 32 + 0x00000000 + 0x0101013F + + + BYTE_REV + 0: no wrap input byte order +1: wrap input byte order + 24 + 1 + read-write + + + REV_OUT + 0: no wrap output bit order +1: wrap output bit order + 16 + 1 + read-write + + + REV_IN + 0: no wrap input bit order +1: wrap input bit order + 8 + 1 + read-write + + + POLY_WIDTH + crc data length + 0 + 6 + read-write + + + + + data + chn&index0 data + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + data for crc + 0 + 32 + read-write + + + + + result + chn&index0 result + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + RESULT + crc result + 0 + 32 + read-write + + + + + + + + UART0 + UART0 + UART + 0xf0040000 + + 0x4 + 0x3c + registers + + + + IDLE_CFG + Idle Configuration Register + 0x4 + 32 + 0x00000000 + 0x00000BFF + + + RXEN + UART receive enable. +0 - hold RX input to high, avoide wrong data input when config pinmux +1 - bypass RX input from PIN +software should set it after config pinmux + 11 + 1 + read-write + + + RX_IDLE_COND + IDLE Detection Condition +0 - Treat as idle if RX pin is logic one +1 - Treat as idle if UART state machine state is idle + 9 + 1 + read-write + + + RX_IDLE_EN + UART Idle Detect Enable +0 - Disable +1 - Enable +it should be enabled if enable address match feature + 8 + 1 + read-write + + + RX_IDLE_THR + Threshold for UART Receive Idle detection (in terms of bits) + 0 + 8 + read-write + + + + + Cfg + Configuration Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + FIFOSIZE + The depth of RXFIFO and TXFIFO +0: 16-byte FIFO +1: 32-byte FIFO +2: 64-byte FIFO +3: 128-byte FIFO + 0 + 2 + read-only + + + + + OSCR + Over Sample Control Register + 0x14 + 32 + 0x00000010 + 0x0000001F + + + OSC + Over-sample control +The value must be an even number; any odd value +writes to this field will be converted to an even value. +OSC=0: reserved +OSC<=8: The over-sample ratio is 8 +8 < OSC< 32: The over sample ratio is OSC + 0 + 5 + read-write + + + + + FCRR + FIFO Control Register config + 0x18 + 32 + 0x00000000 + 0x000000FF + + + RFIFOT + Receiver FIFO trigger level + 6 + 2 + read-write + + + TFIFOT + Transmitter FIFO trigger level + 4 + 2 + read-write + + + DMAE + DMA enable +0: Disable +1: Enable + 3 + 1 + read-write + + + TFIFORST + Transmitter FIFO reset +Write 1 to clear all bytes in the TXFIFO and resets its +counter. The Transmitter Shift Register is not cleared. +This bit will automatically be cleared. + 2 + 1 + write-only + + + RFIFORST + Receiver FIFO reset +Write 1 to clear all bytes in the RXFIFO and resets its +counter. The Receiver Shift Register is not cleared. +This bit will automatically be cleared. + 1 + 1 + write-only + + + FIFOE + FIFO enable +Write 1 to enable both the transmitter and receiver +FIFOs. +The FIFOs are reset when the value of this bit toggles. + 0 + 1 + read-write + + + + + RBR + Receiver Buffer Register (when DLAB = 0) + UNION_20 + 0x20 + 32 + 0x00000000 + 0x000000FF + + + RBR + Receive data read port + 0 + 8 + read-only + + + + + THR + Transmitter Holding Register (when DLAB = 0) + UNION_20 + 0x20 + 32 + 0x00000000 + 0x000000FF + + + THR + Transmit data write port + 0 + 8 + write-only + + + + + DLL + Divisor Latch LSB (when DLAB = 1) + UNION_20 + 0x20 + 32 + 0x00000001 + 0x000000FF + + + DLL + Least significant byte of the Divisor Latch + 0 + 8 + read-write + + + + + IER + Interrupt Enable Register (when DLAB = 0) + UNION_24 + 0x24 + 32 + 0x00000000 + 0x8000000F + + + ERXIDLE + Enable Receive Idle interrupt +0 - Disable Idle interrupt +1 - Enable Idle interrupt + 31 + 1 + read-write + + + EMSI + Enable modem status interrupt +The interrupt asserts when the status of one of the +following occurs: +The status of modem_rin, modem_dcdn, +modem_dsrn or modem_ctsn (If the auto-cts mode is +disabled) has been changed. +If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), +modem_ctsn would be used to control the transmitter. + 3 + 1 + read-write + + + ELSI + Enable receiver line status interrupt + 2 + 1 + read-write + + + ETHEI + Enable transmitter holding register interrupt + 1 + 1 + read-write + + + ERBI + Enable received data available interrupt and the +character timeout interrupt +0: Disable +1: Enable + 0 + 1 + read-write + + + + + DLM + Divisor Latch MSB (when DLAB = 1) + UNION_24 + 0x24 + 32 + 0x00000000 + 0x000000FF + + + DLM + Most significant byte of the Divisor Latch + 0 + 8 + read-write + + + + + IIR + Interrupt Identification Register + UNION_28 + 0x28 + 32 + 0x00000001 + 0x800000CF + + + RXIDLE_FLAG + UART IDLE Flag +0 - UART is busy +1 - UART is idle +NOTE: when write one to clear this bit, avoid changging FCR register since it's same address as IIR + 31 + 1 + write-only + + + FIFOED + FIFOs enabled +These two bits are 1 when bit 0 of the FIFO Control +Register (FIFOE) is set to 1. + 6 + 2 + read-only + + + INTRID + Interrupt ID, see IIR2 for detail decoding + 0 + 4 + read-only + + + + + FCR + FIFO Control Register + UNION_28 + 0x28 + 32 + 0x00000000 + 0x000000FF + + + RFIFOT + Receiver FIFO trigger level + 6 + 2 + write-only + + + TFIFOT + Transmitter FIFO trigger level + 4 + 2 + write-only + + + DMAE + DMA enable +0: Disable +1: Enable + 3 + 1 + write-only + + + TFIFORST + Transmitter FIFO reset +Write 1 to clear all bytes in the TXFIFO and resets its +counter. The Transmitter Shift Register is not cleared. +This bit will automatically be cleared. + 2 + 1 + write-only + + + RFIFORST + Receiver FIFO reset +Write 1 to clear all bytes in the RXFIFO and resets its +counter. The Receiver Shift Register is not cleared. +This bit will automatically be cleared. + 1 + 1 + write-only + + + FIFOE + FIFO enable +Write 1 to enable both the transmitter and receiver +FIFOs. +The FIFOs are reset when the value of this bit toggles. + 0 + 1 + write-only + + + + + LCR + Line Control Register + 0x2c + 32 + 0x00000000 + 0x000000FF + + + DLAB + Divisor latch access bit + 7 + 1 + read-write + + + BC + Break control + 6 + 1 + read-write + + + SPS + Stick parity +1: Parity bit is constant 0 or 1, depending on bit4 (EPS). +0: Disable the sticky bit parity. + 5 + 1 + read-write + + + EPS + Even parity select +1: Even parity (an even number of logic-1 is in the data +and parity bits) +0: Old parity. + 4 + 1 + read-write + + + PEN + Parity enable +When this bit is set, a parity bit is generated in +transmitted data before the first STOP bit and the parity +bit would be checked for the received data. + 3 + 1 + read-write + + + STB + Number of STOP bits +0: 1 bits +1: The number of STOP bit is based on the WLS setting +When WLS = 0, STOP bit is 1.5 bits +When WLS = 1, 2, 3, STOP bit is 2 bits + 2 + 1 + read-write + + + WLS + Word length setting +0: 5 bits +1: 6 bits +2: 7 bits +3: 8 bits + 0 + 2 + read-write + + + + + MCR + Modem Control Register ( + 0x30 + 32 + 0x00000000 + 0x00000032 + + + AFE + Auto flow control enable +0: Disable +1: The auto-CTS and auto-RTS setting is based on the +RTS bit setting: +When RTS = 0, auto-CTS only +When RTS = 1, auto-CTS and auto-RTS + 5 + 1 + read-write + + + LOOP + Enable loopback mode +0: Disable +1: Enable + 4 + 1 + read-write + + + RTS + Request to send +This bit controls the modem_rtsn output. +0: The modem_rtsn output signal will be driven HIGH +1: The modem_rtsn output signal will be driven LOW + 1 + 1 + read-write + + + + + LSR + Line Status Register + 0x34 + 32 + 0x00000000 + 0x000000FF + + + ERRF + Error in RXFIFO +In the FIFO mode, this bit is set when there is at least +one parity error, framing error, or line break +associated with data in the RXFIFO. It is cleared when +this register is read and there is no more error for the +rest of data in the RXFIFO. + 7 + 1 + read-only + + + TEMT + Transmitter empty +This bit is 1 when the THR (TXFIFO in the FIFO +mode) and the Transmitter Shift Register (TSR) are +both empty. Otherwise, it is zero. + 6 + 1 + read-only + + + THRE + Transmitter Holding Register empty +This bit is 1 when the THR (TXFIFO in the FIFO +mode) is empty. Otherwise, it is zero. +If the THRE interrupt is enabled, an interrupt is +triggered when THRE becomes 1. + 5 + 1 + read-only + + + LBREAK + Line break +This bit is set when the uart_sin input signal was held +LOWfor longer than the time for a full-word +transmission. A full-word transmission is the +transmission of the START, data, parity, and STOP +bits. It is cleared when this register is read. +In the FIFO mode, this bit indicates the line break for +the received data at the top of the RXFIFO. + 4 + 1 + read-only + + + FE + Framing error +This bit is set when the received STOP bit is not +HIGH. It is cleared when this register is read. +In the FIFO mode, this bit indicates the framing error +for the received data at the top of the RXFIFO. + 3 + 1 + read-only + + + PE + Parity error +This bit is set when the received parity does not match +with the parity selected in the LCR[5:4]. It is cleared +when this register is read. +In the FIFO mode, this bit indicates the parity error +for the received data at the top of the RXFIFO. + 2 + 1 + read-only + + + OE + Overrun error +This bit indicates that data in the Receiver Buffer +Register (RBR) is overrun. + 1 + 1 + read-only + + + DR + Data ready. +This bit is set when there are incoming received data +in the Receiver Buffer Register (RBR). It is cleared +when all of the received data are read. + 0 + 1 + read-only + + + + + MSR + Modem Status Register + 0x38 + 32 + 0x00000000 + 0x00000011 + + + CTS + Clear to send +0: The modem_ctsn input signal is HIGH. +1: The modem_ctsn input signal is LOW. + 4 + 1 + read-only + + + DCTS + Delta clear to send +This bit is set when the state of the modem_ctsn input +signal has been changed since the last time this +register is read. + 0 + 1 + read-only + + + + + GPR + GPR Register + 0x3c + 32 + 0x00000000 + 0x000000FF + + + DATA + A one-byte storage register + 0 + 8 + read-write + + + + + + + UART1 + UART1 + UART + 0xf0044000 + + + UART2 + UART2 + UART + 0xf0048000 + + + UART3 + UART3 + UART + 0xf004c000 + + + UART4 + UART4 + UART + 0xf0050000 + + + UART5 + UART5 + UART + 0xf0054000 + + + UART6 + UART6 + UART + 0xf0058000 + + + UART7 + UART7 + UART + 0xf005c000 + + + PUART + PUART + UART + 0xf4124000 + + + I2C0 + I2C0 + I2C + 0xf0060000 + + 0x4 + 0x30 + registers + + + + Cfg + Configuration Register + 0x10 + 32 + 0x00000001 + 0xFFFFFFFF + + + FIFOSIZE + FIFO Size: +0: 2 bytes +1: 4 bytes +2: 8 bytes +3: 16 bytes + 0 + 2 + read-only + + + + + IntEn + Interrupt Enable Register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMPL + Set to enable the Completion Interrupt. +Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. +Slave: interrupts when a transaction addressing the controller is completed. + 9 + 1 + read-write + + + BYTERECV + Set to enable the Byte Receive Interrupt. +Interrupts when a byte of data is received +Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually. + 8 + 1 + read-write + + + BYTETRANS + Set to enable the Byte Transmit Interrupt. +Interrupts when a byte of data is transmitted. + 7 + 1 + read-write + + + START + Set to enable the START Condition Interrupt. +Interrupts when a START condition/repeated START condition is detected. + 6 + 1 + read-write + + + STOP + Set to enable the STOP Condition Interrupt +Interrupts when a STOP condition is detected. + 5 + 1 + read-write + + + ARBLOSE + Set to enable the Arbitration Lose Interrupt. +Master: interrupts when the controller loses the bus arbitration +Slave: not available in this mode. + 4 + 1 + read-write + + + ADDRHIT + Set to enable the Address Hit Interrupt. +Master: interrupts when the addressed slave returned an ACK. +Slave: interrupts when the controller is addressed. + 3 + 1 + read-write + + + FIFOHALF + Set to enable the FIFO Half Interrupt. +Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. +Transmitter: Interrupts when the FIFO is half-empty, i.e. there is <= 1/2 entries in the FIFO. +This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered. + 2 + 1 + read-write + + + FIFOFULL + Set to enable the FIFO Full Interrupt. +Interrupts when the FIFO is full. + 1 + 1 + read-write + + + FIFOEMPTY + Set to enabled the FIFO Empty Interrupt +Interrupts when the FIFO is empty. + 0 + 1 + read-write + + + + + Status + Status Register + 0x18 + 32 + 0x00000001 + 0xFFFFFFFF + + + LINESDA + Indicates the current status of the SDA line on the bus +1: high +0: low + 14 + 1 + read-only + + + LINESCL + Indicates the current status of the SCL line on the bus +1: high +0: low + 13 + 1 + read-only + + + GENCALL + Indicates that the address of the current transaction is a general call address: +1: General call +0: Not general call + 12 + 1 + read-only + + + BUSBUSY + Indicates that the bus is busy +The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus +1: Busy +0: Not busy + 11 + 1 + read-only + + + ACK + Indicates the type of the last received/transmitted acknowledgement bit: +1: ACK +0: NACK + 10 + 1 + read-only + + + CMPL + Transaction Completion +Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration +Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked. + 9 + 1 + write-only + + + BYTERECV + Indicates that a byte of data has been received. + 8 + 1 + write-only + + + BYTETRANS + Indicates that a byte of data has been transmitted. + 7 + 1 + write-only + + + START + Indicates that a START Condition or a repeated START condition has been transmitted/received. + 6 + 1 + write-only + + + STOP + Indicates that a STOP Condition has been transmitted/received. + 5 + 1 + write-only + + + ARBLOSE + Indicates that the controller has lost the bus arbitration. + 4 + 1 + write-only + + + ADDRHIT + Master: indicates that a slave has responded to the transaction. +Slave: indicates that a transaction is targeting the controller (including the General Call). + 3 + 1 + write-only + + + FIFOHALF + Transmitter: Indicates that the FIFO is half-empty. + 2 + 1 + read-only + + + FIFOFULL + Indicates that the FIFO is full. + 1 + 1 + read-only + + + FIFOEMPTY + Indicates that the FIFO is empty. + 0 + 1 + read-only + + + + + Addr + Address Register + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + The slave address. +For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid + 0 + 10 + read-write + + + + + Data + Data Register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + Write this register to put one byte of data to the FIFO. +Read this register to get one byte of data from the FIFO. + 0 + 8 + read-write + + + + + Ctrl + Control Register + 0x24 + 32 + 0x00905E00 + 0xFFFFFFFF + + + DATACNT_HIGH + Data counts in bytes. +Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. +Slave: the meaning of DataCnt depends on the DMA mode: +If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. +If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. + 24 + 8 + read-write + + + RESET_LEN + reset clock cycles. the clock high/low time is defined by Setup.T_SCLHi, 50% duty cycle. + 20 + 4 + read-write + + + RESET_HOLD_SCKIN + set to hold input clock to high when reset is active + 14 + 1 + read-write + + + RESET_ON + set to send reset signals(just toggle clock bus defined by reset_len). +this register is clered when reset is end, can't be cleared by software + 13 + 1 + read-write + + + PHASE_START + Enable this bit to send a START condition at the beginning of transaction. +Master mode only. + 12 + 1 + read-write + + + PHASE_ADDR + Enable this bit to send the address after START condition. +Master mode only. + 11 + 1 + read-write + + + PHASE_DATA + Enable this bit to send the data after Address phase. +Master mode only. + 10 + 1 + read-write + + + PHASE_STOP + Enable this bit to send a STOP condition at the end of a transaction. +Master mode only. + 9 + 1 + read-write + + + DIR + Transaction direction +Master: Set this bit to determine the direction for the next transaction. +0: Transmitter +1: Receiver +Slave: The direction of the last received transaction. +0: Receiver +1: Transmitter + 8 + 1 + read-write + + + DATACNT + Data counts in bytes. +Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. +Slave: the meaning of DataCnt depends on the DMA mode: +If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. +If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. + 0 + 8 + read-write + + + + + Cmd + Command Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMD + Write this register with the following values to perform the corresponding actions: +0x0: no action +0x1: issue a data transaction (Master only) +0x2: respond with an ACK to the received byte +0x3: respond with a NACK to the received byte +0x4: clear the FIFO +0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) +When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. +Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled. + 0 + 3 + read-write + + + + + Setup + Setup Register + 0x2c + 32 + 0x05252100 + 0xFFFFFFFF + + + T_SUDAT + T_SUDAT defines the data setup time before releasing the SCL. +Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) +tpclk = PCLK period +TPM = The multiplier value in Timing Parameter Multiplier Register + 24 + 5 + read-write + + + T_SP + T_SP defines the pulse width of spikes that must be suppressed by the input filter. +Pulse width = T_SP * tpclk* (TPM+1) + 21 + 3 + read-write + + + T_HDDAT + T_HDDAT defines the data hold time after SCL goes LOW +Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) + 16 + 5 + read-write + + + T_SCLRADIO + The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. +SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) +1: ratio = 2 +0: ratio = 1 +This field is only valid when the controller is in the master mode. + 13 + 1 + read-write + + + T_SCLHI + The HIGH period of generated SCL clock is defined by T_SCLHi. +SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) +The T_SCLHi value must be greater than T_SP and T_HDDAT values. +This field is only valid when the controller is in the master mode. + 4 + 9 + read-write + + + DMAEN + Enable the direct memory access mode data transfer. +1: Enable +0: Disable + 3 + 1 + read-write + + + MASTER + Configure this device as a master or a slave. +1: Master mode +0: Slave mode + 2 + 1 + read-write + + + ADDRESSING + I2C addressing mode: +1: 10-bit addressing mode +0: 7-bit addressing mode + 1 + 1 + read-write + + + IICEN + Enable the I2C controller. +1: Enable +0: Disable + 0 + 1 + read-write + + + + + TPM + I2C Timing Paramater Multiplier + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + TPM + A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). + 0 + 5 + read-write + + + + + + + I2C1 + I2C1 + I2C + 0xf0064000 + + + I2C2 + I2C2 + I2C + 0xf0068000 + + + I2C3 + I2C3 + I2C + 0xf006c000 + + + SPI0 + SPI0 + SPI + 0xf0070000 + + 0x4 + 0x7c + registers + + + + wr_trans_cnt + Transfer count for write data + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + WRTRANCNT + Transfer count for write data +WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). +WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. +The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. +For TransMode 0, WrTranCnt must be equal to RdTranCnt. + 0 + 32 + read-write + + + + + rd_trans_cnt + Transfer count for read data + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RDTRANCNT + Transfer count for read data +RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). +RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. +The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. +For TransMode 0, WrTranCnt must equal RdTranCnt. + 0 + 32 + read-write + + + + + TransFmt + Transfer Format Register + 0x10 + 32 + 0x00020780 + 0xFFFF1F9F + + + ADDRLEN + Address length in bytes +0x0: 1 byte +0x1: 2 bytes +0x2: 3 bytes +0x3: 4 bytes + 16 + 2 + read-write + + + DATALEN + The length of each data unit in bits +The actual bit number of a data unit is (DataLen + 1) + 8 + 5 + read-write + + + DATAMERGE + Enable Data Merge mode, which does automatic data split on write and data coalescing on read. +This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. +When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed. + 7 + 1 + read-write + + + MOSIBIDIR + Bi-directional MOSI in regular (single) mode +0x0: MOSI is uni-directional signal in regular mode. +0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two + 4 + 1 + read-write + + + LSB + Transfer data with the least significant bit first +0x0: Most significant bit first +0x1: Least significant bit first + 3 + 1 + read-write + + + SLVMODE + SPI Master/Slave mode selection +0x0: Master mode +0x1: Slave mode + 2 + 1 + read-write + + + CPOL + SPI Clock Polarity +0x0: SCLK is LOW in the idle states +0x1: SCLK is HIGH in the idle states + 1 + 1 + read-write + + + CPHA + SPI Clock Phase +0x0: Sampling data at odd SCLK edges +0x1: Sampling data at even SCLK edges + 0 + 1 + read-write + + + + + DirectIO + Direct IO Control Register + 0x14 + 32 + 0x00003100 + 0x013F3F3F + + + DIRECTIOEN + Enable Direct IO +0x0: Disable +0x1: Enable + 24 + 1 + read-write + + + HOLD_OE + Output enable for the SPI Flash hold signal + 21 + 1 + read-write + + + WP_OE + Output enable for the SPI Flash write protect signal + 20 + 1 + read-write + + + MISO_OE + Output enable fo the SPI MISO signal + 19 + 1 + read-write + + + MOSI_OE + Output enable for the SPI MOSI signal + 18 + 1 + read-write + + + SCLK_OE + Output enable for the SPI SCLK signal + 17 + 1 + read-write + + + CS_OE + Output enable for SPI CS (chip select) signal + 16 + 1 + read-write + + + HOLD_O + Output value for the SPI Flash hold signal + 13 + 1 + read-write + + + WP_O + Output value for the SPI Flash write protect signal + 12 + 1 + read-write + + + MISO_O + Output value for the SPI MISO signal + 11 + 1 + read-write + + + MOSI_O + Output value for the SPI MOSI signal + 10 + 1 + read-write + + + SCLK_O + Output value for the SPI SCLK signal + 9 + 1 + read-write + + + CS_O + Output value for the SPI CS (chip select) signal + 8 + 1 + read-write + + + HOLD_I + Status of the SPI Flash hold signal + 5 + 1 + read-only + + + WP_I + Status of the SPI Flash write protect signal + 4 + 1 + read-only + + + MISO_I + Status of the SPI MISO signal + 3 + 1 + read-only + + + MOSI_I + Status of the SPI MOSI signal + 2 + 1 + read-only + + + SCLK_I + Status of the SPI SCLK signal + 1 + 1 + read-only + + + CS_I + Status of the SPI CS (chip select) signal + 0 + 1 + read-only + + + + + TransCtrl + Transfer Control Register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + SLVDATAONLY + Data-only mode (slave mode only) +0x0: Disable the data-only mode +0x1: Enable the data-only mode +Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0. + 31 + 1 + read-write + + + CMDEN + SPI command phase enable (Master mode only) +0x0: Disable the command phase +0x1: Enable the command phase + 30 + 1 + read-write + + + ADDREN + SPI address phase enable (Master mode only) +0x0: Disable the address phase +0x1: Enable the address phase + 29 + 1 + read-write + + + ADDRFMT + SPI address phase format (Master mode only) +0x0: Address phase is the regular (single) mode +0x1: The format of the address phase is the same as the data phase (DualQuad). + 28 + 1 + read-write + + + TRANSMODE + Transfer mode +The transfer sequence could be +0x0: Write and read at the same time +0x1: Write only +0x2: Read only +0x3: Write, Read +0x4: Read, Write +0x5: Write, Dummy, Read +0x6: Read, Dummy, Write +0x7: None Data (must enable CmdEn or AddrEn in master mode) +0x8: Dummy, Write +0x9: Dummy, Read +0xa~0xf: Reserved + 24 + 4 + read-write + + + DUALQUAD + SPI data phase format +0x0: Regular (Single) mode +0x1: Dual I/O mode +0x2: Quad I/O mode +0x3: Reserved + 22 + 2 + read-write + + + TOKENEN + Token transfer enable (Master mode only) +Append a one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. +0x0: Disable the one-byte special token +0x1: Enable the one-byte special token + 21 + 1 + read-write + + + WRTRANCNT + Transfer count for write data +WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). +WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. +The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. +For TransMode 0, WrTranCnt must be equal to RdTranCnt. + 12 + 9 + read-write + + + TOKENVALUE + Token value (Master mode only) +The value of the one-byte special token following the address phase for SPI read transfers. +0x0: token value = 0x00 +0x1: token value = 0x69 + 11 + 1 + read-write + + + DUMMYCNT + Dummy data count. The actual dummy count is (DummyCnt +1). +The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) +The Data pins are put into the high impedance during the dummy data phase. +DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases. + 9 + 2 + read-write + + + RDTRANCNT + Transfer count for read data +RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). +RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. +The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. +For TransMode 0, WrTranCnt must equal RdTranCnt. + 0 + 9 + read-write + + + + + Cmd + Command Register + 0x24 + 32 + 0x00000000 + 0x000000FF + + + CMD + SPI Command + 0 + 8 + read-write + + + + + Addr + Address Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + SPI Address +(Master mode only) + 0 + 32 + read-write + + + + + Data + Data Register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + Data to transmit or the received data +For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. +For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. +The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. +If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset. + 0 + 32 + read-write + + + + + Ctrl + Control Register + 0x30 + 32 + 0x00000000 + 0x0FFFFF1F + + + CS_EN + No description available + 24 + 4 + read-write + + + TXTHRES + Transmit (TX) FIFO Threshold +The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold. + 16 + 8 + read-write + + + RXTHRES + Receive (RX) FIFO Threshold +The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold. + 8 + 8 + read-write + + + TXDMAEN + TX DMA enable + 4 + 1 + read-write + + + RXDMAEN + RX DMA enable + 3 + 1 + read-write + + + TXFIFORST + Transmit FIFO reset +Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. + 2 + 1 + read-write + + + RXFIFORST + Receive FIFO reset +Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. + 1 + 1 + read-write + + + SPIRST + SPI reset +Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. + 0 + 1 + read-write + + + + + Status + Status Register + 0x34 + 32 + 0x00000000 + 0x33FFFF01 + + + TXNUM_7_6 + Number of valid entries in the Transmit FIFO + 28 + 2 + read-only + + + RXNUM_7_6 + Number of valid entries in the Receive FIFO + 24 + 2 + read-only + + + TXFULL + Transmit FIFO Full flag + 23 + 1 + read-only + + + TXEMPTY + Transmit FIFO Empty flag + 22 + 1 + read-only + + + TXNUM_5_0 + Number of valid entries in the Transmit FIFO + 16 + 6 + read-only + + + RXFULL + Receive FIFO Full flag + 15 + 1 + read-only + + + RXEMPTY + Receive FIFO Empty flag + 14 + 1 + read-only + + + RXNUM_5_0 + Number of valid entries in the Receive FIFO + 8 + 6 + read-only + + + SPIACTIVE + SPI register programming is in progress. +In master mode, SPIActive becomes 1 after the SPI command register is written and becomes 0 after the transfer is finished. +In slave mode, SPIActive becomes 1 after the SPI CS signal is asserted and becomes 0 after the SPI CS signal is deasserted. +Note that due to clock synchronization, it may take at most two spi_clock cycles for SPIActive to change when the corresponding condition happens. +Note this bit stays 0 when Direct IO Control or the memory-mapped interface is used. + 0 + 1 + read-only + + + + + IntrEn + Interrupt Enable Register + 0x38 + 32 + 0x00000000 + 0x0000003F + + + SLVCMDEN + Enable the Slave Command Interrupt. +Control whether interrupts are triggered whenever slave commands are received. +(Slave mode only) + 5 + 1 + read-write + + + ENDINTEN + Enable the End of SPI Transfer interrupt. +Control whether interrupts are triggered when SPI transfers end. +(In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.) + 4 + 1 + read-write + + + TXFIFOINTEN + Enable the SPI Transmit FIFO Threshold interrupt. +Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold. + 3 + 1 + read-write + + + RXFIFOINTEN + Enable the SPI Receive FIFO Threshold interrupt. +Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold. + 2 + 1 + read-write + + + TXFIFOURINTEN + Enable the SPI Transmit FIFO Underrun interrupt. +Control whether interrupts are triggered when the Transmit FIFO run out of data. +(Slave mode only) + 1 + 1 + read-write + + + RXFIFOORINTEN + Enable the SPI Receive FIFO Overrun interrupt. +Control whether interrupts are triggered when the Receive FIFO overflows. +(Slave mode only) + 0 + 1 + read-write + + + + + IntrSt + Interrupt Status Register + 0x3c + 32 + 0x00000000 + 0x0000003F + + + SLVCMDINT + Slave Command Interrupt. +This bit is set when Slave Command interrupts occur. +(Slave mode only) + 5 + 1 + write-only + + + ENDINT + End of SPI Transfer interrupt. +This bit is set when End of SPI Transfer interrupts occur. + 4 + 1 + write-only + + + TXFIFOINT + TX FIFO Threshold interrupt. +This bit is set when TX FIFO Threshold interrupts occur. + 3 + 1 + write-only + + + RXFIFOINT + RX FIFO Threshold interrupt. +This bit is set when RX FIFO Threshold interrupts occur. + 2 + 1 + write-only + + + TXFIFOURINT + TX FIFO Underrun interrupt. +This bit is set when TX FIFO Underrun interrupts occur. +(Slave mode only) + 1 + 1 + write-only + + + RXFIFOORINT + RX FIFO Overrun interrupt. +This bit is set when RX FIFO Overrun interrupts occur. +(Slave mode only) + 0 + 1 + write-only + + + + + Timing + Interface Timing Register + 0x40 + 32 + 0x00000000 + 0x00003FFF + + + CS2SCLK + The minimum time between the edges of SPI CS and the edges of SCLK. +SCLK_period * (CS2SCLK + 1) / 2 + 12 + 2 + read-write + + + CSHT + The minimum time that SPI CS should stay HIGH. +SCLK_period * (CSHT + 1) / 2 + 8 + 4 + read-write + + + SCLK_DIV + The clock frequency ratio between the clock source and SPI interface SCLK. +SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) +The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency. + 0 + 8 + read-write + + + + + SlvSt + Slave Status Register + 0x60 + 32 + 0x00000000 + 0x0007FFFF + + + UNDERRUN + Data underrun occurs in the last transaction + 18 + 1 + write-only + + + OVERRUN + Data overrun occurs in the last transaction + 17 + 1 + read-write + + + READY + Set this bit to indicate that the ATCSPI200 is ready for data transaction. +When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0. + 16 + 1 + read-write + + + USR_STATUS + User defined status flags + 0 + 16 + read-write + + + + + SlvDataCnt + Slave Data Count Register + 0x64 + 32 + 0x00000000 + 0x03FF03FF + + + WCNT + Slave transmitted data count + 16 + 10 + read-only + + + RCNT + Slave received data count + 0 + 10 + read-only + + + + + SlvDataWCnt + WCnt + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + No description available + 0 + 32 + read-only + + + + + SlvDataRCnt + RCnt + 0x6c + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + No description available + 0 + 32 + read-only + + + + + Config + Configuration Register + 0x7c + 32 + 0x00004311 + 0x000043FF + + + SLAVE + Support for SPI Slave mode + 14 + 1 + read-only + + + QUADSPI + Support for Quad I/O SPI + 9 + 1 + read-only + + + DUALSPI + Support for Dual I/O SPI + 8 + 1 + read-only + + + TXFIFOSIZE + Depth of TX FIFO +0x0: 2 words +0x1: 4 words +0x2: 8 words +0x3: 16 words +0x4: 32 words +0x5: 64 words +0x6: 128 words + 4 + 4 + read-only + + + RXFIFOSIZE + Depth of RX FIFO +0x0: 2 words +0x1: 4 words +0x2: 8 words +0x3: 16 words +0x4: 32 words +0x5: 64 words +0x6: 128 words + 0 + 4 + read-only + + + + + + + SPI1 + SPI1 + SPI + 0xf0074000 + + + SPI2 + SPI2 + SPI + 0xf0078000 + + + SPI3 + SPI3 + SPI + 0xf007c000 + + + GPTMR0 + GPTMR0 + TMR + 0xf0080000 + + 0x0 + 0x20c + registers + + + + 4 + 0x40 + ch0,ch1,ch2,ch3 + CHANNEL[%s] + no description available + 0x0 + + CR + Control Register + 0x0 + 32 + 0x00000000 + 0x8003FFFF + + + CNTUPT + 1- update counter to new value as CNTUPTVAL +This bit will be auto cleared after 1 cycle + 31 + 1 + write-only + + + OPMODE + 0: round mode +1: one-shot mode, timer will stopped at reload point. +NOTE: reload irq will be always set at one-shot mode at end + 17 + 1 + read-write + + + MONITOR_SEL + set to monitor input signal high level time(chan_meas_high) +clr to monitor input signal period(chan_meas_prd) + 16 + 1 + read-write + + + MONITOR_EN + set to monitor input signal period or high level time. +When this bit is set, if detected period less than val_0 or more than val_1, will set related irq_sts +* only can be used when trig_mode is selected as measure mode(100) +* the time may not correct after reload, so monitor is disabled after reload point, and enabled again after two continul posedge. +if no posedge after reload for more than val_1, will also assert irq_capt + 15 + 1 + read-write + + + CNTRST + 1- reset counter + 14 + 1 + read-write + + + SYNCFLW + 1- enable this channel to reset counter to reload(RLD) together with its previous channel. +This bit is not valid for channel 0. + 13 + 1 + read-write + + + SYNCIFEN + 1- SYNCI is valid on its falling edge + 12 + 1 + read-write + + + SYNCIREN + 1- SYNCI is valid on its rising edge + 11 + 1 + read-write + + + CEN + 1- counter enable + 10 + 1 + read-write + + + CMPINIT + Output compare initial poliarity +1- The channel output initial level is high +0- The channel output initial level is low +User should set this bit before set CMPEN to 1. + 9 + 1 + read-write + + + CMPEN + 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. + 8 + 1 + read-write + + + DMASEL + select one of DMA request: +00- CMP0 flag +01- CMP1 flag +10- Input signal toggle captured +11- RLD flag, counter reload; + 6 + 2 + read-write + + + DMAEN + 1- enable dma + 5 + 1 + read-write + + + SWSYNCIEN + 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set + 4 + 1 + read-write + + + DBGPAUSE + 1- counter will pause if chip is in debug mode + 3 + 1 + read-write + + + CAPMODE + This bitfield define the input capture mode +100: width measure mode, timer will calculate the input signal period and duty cycle +011: capture at both rising edge and falling edge +010: capture at falling edge +001: capture at rising edge +000: No capture + 0 + 3 + read-write + + + + + 2 + 0x4 + CMP0,CMP1 + CMP[%s] + no description available + 0x4 + 32 + 0xFFFFFFF0 + 0xFFFFFFFF + + + CMP + compare value 0 + 0 + 32 + read-write + + + + + RLD + Reload register + 0xc + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + RLD + reload value + 0 + 32 + read-write + + + + + CNTUPTVAL + Counter update value register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTUPTVAL + counter will be set to this value when software write cntupt bit in CR + 0 + 32 + read-write + + + + + CAPPOS + Capture rising edge register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPOS + This register contains the counter value captured at input signal rising edge + 0 + 32 + read-only + + + + + CAPNEG + Capture falling edge register + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + This register contains the counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPPRD + PWM period measure register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPRD + This register contains the input signal period when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CAPDTY + PWM duty cycle measure register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + MEAS_HIGH + This register contains the input signal duty cycle when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CNT + Counter + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + 32 bit counter value + 0 + 32 + read-only + + + + + + SR + Status register + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH3CMP1F + channel 3 compare value 1 match flag + 15 + 1 + write-only + + + CH3CMP0F + channel 3 compare value 1 match flag + 14 + 1 + write-only + + + CH3CAPF + channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 13 + 1 + write-only + + + CH3RLDF + channel 3 counter reload flag + 12 + 1 + write-only + + + CH2CMP1F + channel 2 compare value 1 match flag + 11 + 1 + write-only + + + CH2CMP0F + channel 2 compare value 1 match flag + 10 + 1 + write-only + + + CH2CAPF + channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 9 + 1 + write-only + + + CH2RLDF + channel 2 counter reload flag + 8 + 1 + write-only + + + CH1CMP1F + channel 1 compare value 1 match flag + 7 + 1 + write-only + + + CH1CMP0F + channel 1 compare value 1 match flag + 6 + 1 + write-only + + + CH1CAPF + channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 5 + 1 + write-only + + + CH1RLDF + channel 1 counter reload flag + 4 + 1 + write-only + + + CH0CMP1F + channel 1 compare value 1 match flag + 3 + 1 + write-only + + + CH0CMP0F + channel 1 compare value 1 match flag + 2 + 1 + write-only + + + CH0CAPF + channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 1 + 1 + write-only + + + CH0RLDF + channel 1 counter reload flag + 0 + 1 + write-only + + + + + IRQEN + Interrupt request enable register + 0x204 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH3CMP1EN + 1- generate interrupt request when ch3cmp1f flag is set + 15 + 1 + read-write + + + CH3CMP0EN + 1- generate interrupt request when ch3cmp0f flag is set + 14 + 1 + read-write + + + CH3CAPEN + 1- generate interrupt request when ch3capf flag is set + 13 + 1 + read-write + + + CH3RLDEN + 1- generate interrupt request when ch3rldf flag is set + 12 + 1 + read-write + + + CH2CMP1EN + 1- generate interrupt request when ch2cmp1f flag is set + 11 + 1 + read-write + + + CH2CMP0EN + 1- generate interrupt request when ch2cmp0f flag is set + 10 + 1 + read-write + + + CH2CAPEN + 1- generate interrupt request when ch2capf flag is set + 9 + 1 + read-write + + + CH2RLDEN + 1- generate interrupt request when ch2rldf flag is set + 8 + 1 + read-write + + + CH1CMP1EN + 1- generate interrupt request when ch1cmp1f flag is set + 7 + 1 + read-write + + + CH1CMP0EN + 1- generate interrupt request when ch1cmp0f flag is set + 6 + 1 + read-write + + + CH1CAPEN + 1- generate interrupt request when ch1capf flag is set + 5 + 1 + read-write + + + CH1RLDEN + 1- generate interrupt request when ch1rldf flag is set + 4 + 1 + read-write + + + CH0CMP1EN + 1- generate interrupt request when ch0cmp1f flag is set + 3 + 1 + read-write + + + CH0CMP0EN + 1- generate interrupt request when ch0cmp0f flag is set + 2 + 1 + read-write + + + CH0CAPEN + 1- generate interrupt request when ch0capf flag is set + 1 + 1 + read-write + + + CH0RLDEN + 1- generate interrupt request when ch0rldf flag is set + 0 + 1 + read-write + + + + + GCR + Global control register + 0x208 + 32 + 0x00000000 + 0x0000000F + + + SWSYNCT + set this bitfield to trigger software counter sync event + 0 + 4 + read-write + + + + + + + GPTMR1 + GPTMR1 + TMR + 0xf0084000 + + + GPTMR2 + GPTMR2 + TMR + 0xf0088000 + + + GPTMR3 + GPTMR3 + TMR + 0xf008c000 + + + GPTMR4 + GPTMR4 + TMR + 0xf0090000 + + + GPTMR5 + GPTMR5 + TMR + 0xf0094000 + + + GPTMR6 + GPTMR6 + TMR + 0xf0098000 + + + GPTMR7 + GPTMR7 + TMR + 0xf009c000 + + + NTMR0 + NTMR0 + TMR + 0xf1110000 + + + PTMR + PTMR + TMR + 0xf4120000 + + + MBX0A + MBX0A + MBX + 0xf00a0000 + + 0x0 + 0x24 + registers + + + + CR + Command Registers + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXRESET + Reset TX Fifo and word. + 31 + 1 + read-write + + + BARCTL + Bus Access Response Control, when bit 15:14= +00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. + 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. +10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. +11: reserved. + 14 + 2 + read-write + + + BEIE + Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. +1, enable the bus access error interrupt. +0, disable the bus access error interrupt. + 8 + 1 + read-write + + + TFMAIE + TX FIFO message available interrupt enable. +1, enable the TX FIFO massage available interrupt. +0, disable the TX FIFO message available interrupt. + 7 + 1 + read-write + + + TFMEIE + TX FIFO message empty interrupt enable. +1, enable the TX FIFO massage empty interrupt. +0, disable the TX FIFO message empty interrupt. + 6 + 1 + read-write + + + RFMAIE + RX FIFO message available interrupt enable. +1, enable the RX FIFO massage available interrupt. +0, disable the RX FIFO message available interrupt. + 5 + 1 + read-write + + + RFMFIE + RX fifo message full interrupt enable. +1, enable the RX fifo message full interrupt. +0, disable the RX fifo message full interrupt. + 4 + 1 + read-write + + + TWMEIE + TX word message empty interrupt enable. +1, enable the TX word massage empty interrupt. +0, disable the TX word message empty interrupt. + 1 + 1 + read-write + + + RWMVIE + RX word message valid interrupt enable. +1, enable the RX word massage valid interrupt. +0, disable the RX word message valid interrupt. + 0 + 1 + read-write + + + + + SR + Status Registers + 0x4 + 32 + 0x000000E2 + 0xFFFF3FFF + + + RFVC + RX FIFO valid message count + 20 + 4 + read-only + + + TFEC + TX FIFO empty message word count + 16 + 4 + read-only + + + ERRRE + bus Error for read when rx word message are still invalid, this bit is W1C bit. +1, read from word message when the word message are still invalid will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 13 + 1 + write-only + + + EWTRF + bus Error for write when tx word message are still valid, this bit is W1C bit. +1, write to word message when the word message are still valid will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 12 + 1 + write-only + + + ERRFE + bus Error for read when rx fifo empty, this bit is W1C bit. +1, read from a empty rx fifo will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 11 + 1 + write-only + + + EWTFF + bus Error for write when tx fifo full, this bit is W1C bit. +1, write to a fulled tx fifo will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 10 + 1 + write-only + + + EAIVA + bus Error for Accessing Invalid Address; this bit is W1C bit. +1, read and write to invalid address in the bus of this block, will set this bit. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 9 + 1 + write-only + + + EW2RO + bus Error for Write to Read Only address; this bit is W1C bit. +1, write to read only address happened in the bus of this block. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 8 + 1 + write-only + + + TFMA + TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. +1, TXFIFO message buffer has slot available +0, no slot available (fifo full) + 7 + 1 + read-write + + + TFME + TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. +1, no any message data in TXFIFO from other core. +0, there are some data in the 4x32 TX FIFO from other core yet. + 6 + 1 + read-write + + + RFMA + RX FIFO Message Available, available data in the 4x32 TX FIFO message buffer to the other core, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, no any data in the 4x32 TXFIFO message buffer. +0, there are some data in the the 4x32 TXFIFO message buffer already. + 5 + 1 + read-only + + + RFMF + RX FIFO Message Full, message from other core; will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, the other core had written 4x32 message in the RXFIFO. +0, no 4x32 RX FIFO message from other core yet. + 4 + 1 + read-only + + + TWME + TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, means this core had write word message to TXREG. +0, means no valid word message in the TXREG yet. + 1 + 1 + read-only + + + RWMV + RX word message valid, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, the other core had written word message in the RXREG. +0, no valid word message yet in the RXREG. + 0 + 1 + read-only + + + + + TXREG + Transmit word message to other core. + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXREG + Transmit word message to other core. + 0 + 32 + write-only + + + + + RXREG + Receive word message from other core. + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + RXREG + Receive word message from other core. + 0 + 32 + read-only + + + + + 1 + 0x4 + TXFIFO0 + TXWRD[%s] + no description available + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXFIFO + TXFIFO for sending message to other core, FIFO size, 4x32 +can write one of the word address to push data to the FIFO; +can also use 4x32 burst write from 0x010 to push 4 words to the FIFO. + 0 + 32 + write-only + + + + + 1 + 0x4 + RXFIFO0 + RXWRD[%s] + no description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXFIFO + RXFIFO for receiving message from other core, FIFO size, 4x32 +can read one of the word address to pop data to the FIFO; +can also use 4x32 burst read from 0x020 to read 4 words from the FIFO. + 0 + 32 + read-only + + + + + + + MBX0B + MBX0B + MBX + 0xf00a4000 + + + MBX1A + MBX1A + MBX + 0xf00a8000 + + + MBX1B + MBX1B + MBX + 0xf00ac000 + + + EWDG0 + EWDG0 + EWDG + 0xf00b0000 + + 0x0 + 0x28 + registers + + + + CTRL0 + wdog ctrl register 0 +Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits + 0x0 + 32 + 0x00000000 + 0x2FE2F03F + + + CLK_SEL + clock select +0：bus clock +1：ext clock + 29 + 1 + read-write + + + DIV_VALUE + clock divider, the clock divider works as 2 ^ div_value for wdt counter + 25 + 3 + read-write + + + WIN_EN + window mode enable + 24 + 1 + read-write + + + WIN_LOWER + Once window mode is opened, the lower counter value to refresh wdt +00: 4/8 overtime value +01: 5/8 of overtime value +10: 6/8 of overtime value +11: 7/8 of overtime value + 22 + 2 + read-write + + + CFG_LOCK + The register is locked and unlock is needed before re-config registers +Once the lock mechanism takes effect, the CTRL0, CTRL1, timeout int register, timeout rst register, needs unlock before re-config them. +The register update needs to be finished in the required period defined by UPD_OT_TIME register + 21 + 1 + read-write + + + OT_SELF_CLEAR + overtime reset can be self released after 32 function cycles + 17 + 1 + read-write + + + REF_OT_REQ + If refresh event has to be limited into a period after refresh unlocked. +Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter + 15 + 1 + read-write + + + WIN_UPPER + The upper threshold of window value +The window period upper limit is: lower_limit + (overtime_rst_value / 16) * upper_reg_value +If this register value is zero, then no upper level limitation + 12 + 3 + read-write + + + REF_LOCK + WDT refresh has to be unlocked firstly once refresh lock is enable. + 5 + 1 + read-write + + + REF_UNLOCK_MEC + Unlock refresh mechanism +00: the required unlock password is the same with refresh_psd_register +01: the required unlock password is a ring shift left value of refresh_psd_register +10: the required unlock password is always 16'h55AA, no matter what refresh_psd_register is +11: the required unlock password is a LSFR result of refresh_psd_register, the characteristic polynomial is X^15 + 1 + 3 + 2 + read-write + + + EN_DBG + WTD enable or not in debug mode + 2 + 1 + read-write + + + EN_LP + WDT enable or not in low power mode +2'b00: wdt is halted once in low power mode +2'b01: wdt will work with 1/4 normal clock freq in low power mode +2'b10: wdt will work with 1/2 normal clock freq in low power mode +2'b11: wdt will work with normal clock freq in low power mode + 0 + 2 + read-write + + + + + CTRL1 + wdog ctrl register 1 +Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits + 0x4 + 32 + 0x00000000 + 0x00F200FC + + + REF_FAIL_RST_EN + Refresh violation will trigger an reset. +These event will be taken as a refresh violation: +1) Not refresh in the window once window mode is enabled +2) Not unlock refresh firstly if unlock is required +3) Not refresh in the required time after unlock, once refresh unlock overtime is enabled. +4) Not write the required word to refresh wdt. + 23 + 1 + read-write + + + REF_FAIL_INT_EN + Refresh violation will trigger an interrupt + 22 + 1 + read-write + + + UNL_REF_FAIL_RST_EN + Refresh unlock fail will trigger a reset + 21 + 1 + read-write + + + UNL_REF_FAIL_INT_EN + Refresh unlock fail will trigger a interrupt + 20 + 1 + read-write + + + OT_RST_EN + WDT overtime will generate a reset + 17 + 1 + read-write + + + CTL_VIO_RST_EN + Ctrl update violation will trigger a reset +The violation event is to try updating the locked register before unlock them + 7 + 1 + read-write + + + CTL_VIO_INT_EN + Ctrl update violation will trigger a interrupt + 6 + 1 + read-write + + + UNL_CTL_FAIL_RST_EN + Unlock register update failure will trigger a reset + 5 + 1 + read-write + + + UNL_CTL_FAIL_INT_EN + Unlock register update failure will trigger a interrupt + 4 + 1 + read-write + + + PARITY_FAIL_RST_EN + Parity error will trigger a reset +A parity check is required once writing to ctrl0 and ctrl1 register. The result should be zero by modular two addition of all bits + 3 + 1 + read-write + + + PARITY_FAIL_INT_EN + Parity error will trigger a interrupt + 2 + 1 + read-write + + + + + OT_RST_VAL + wdog timeout reset counter value + 0xc + 32 + 0x00000000 + 0x0000FFFF + + + OT_RST_VAL + WDT timeout reset value + 0 + 16 + read-write + + + + + WDT_REFRESH_REG + wdog refresh register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + WDT_REFRESH_REG + Write this register by 32'h5A45_524F to refresh wdog +Note: Reading this register can read back wdt real time counter value, while it is only used by debug purpose + 0 + 32 + write-only + + + + + WDT_STATUS + wdog status register + 0x14 + 32 + 0x00000000 + 0x0000006F + + + PARITY_ERROR + parity error +Write one to clear the bit + 6 + 1 + read-write + + + OT_RST + Timeout happens, a reset will happen once enable bit set +This bit can be cleared only by refreshing wdt or reset + 5 + 1 + read-only + + + CTL_UNL_FAIL + Unlock ctrl reg update protection fail +Write one to clear the bit + 3 + 1 + read-write + + + CTL_VIO + Violate register update protection mechanism +Write one to clear the bit + 2 + 1 + read-write + + + REF_UNL_FAIL + Refresh unlock fail +Write one to clear the bit + 1 + 1 + read-write + + + REF_VIO + Refresh fail +Write one to clear the bit + 0 + 1 + read-write + + + + + CFG_PROT + ctrl register protection register + 0x18 + 32 + 0x00000000 + 0x000FFFFF + + + UPD_OT_TIME + The period in which register update has to be in after unlock +The required period is less than： 128 * 2 ^ UPD_OT_TIME * bus_clock_cycle + 16 + 4 + read-write + + + UPD_PSD + The password of unlocking register update + 0 + 16 + read-write + + + + + REF_PROT + refresh protection register + 0x1c + 32 + 0x00000000 + 0x0000FFFF + + + REF_UNL_PSD + The password to unlock refreshing + 0 + 16 + read-write + + + + + WDT_EN + Wdog enable + 0x20 + 32 + 0x00000000 + 0x00000001 + + + WDOG_EN + Wdog is enabled, the re-written of this register is impacted by enable lock function + 0 + 1 + read-write + + + + + REF_TIME + Refresh period value + 0x24 + 32 + 0x00000000 + 0x0000FFFF + + + REFRESH_PERIOD + The refresh period after refresh unlocked +Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter + 0 + 16 + read-write + + + + + + + EWDG1 + EWDG1 + EWDG + 0xf00b4000 + + + PEWDG + PEWDG + EWDG + 0xf4128000 + + + DMAMUX + DMAMUX + DMAMUX + 0xf00c4000 + + 0x0 + 0x100 + registers + + + + 64 + 0x4 + HDMA_MUX0,HDMA_MUX1,HDMA_MUX2,HDMA_MUX3,HDMA_MUX4,HDMA_MUX5,HDMA_MUX6,HDMA_MUX7,HDMA_MUX8,HDMA_MUX9,HDMA_MUX10,HDMA_MUX11,HDMA_MUX12,HDMA_MUX13,HDMA_MUX14,HDMA_MUX15,HDMA_MUX16,HDMA_MUX17,HDMA_MUX18,HDMA_MUX19,HDMA_MUX20,HDMA_MUX21,HDMA_MUX22,HDMA_MUX23,HDMA_MUX24,HDMA_MUX25,HDMA_MUX26,HDMA_MUX27,HDMA_MUX28,HDMA_MUX29,HDMA_MUX30,HDMA_MUX31,XDMA_MUX0,XDMA_MUX1,XDMA_MUX2,XDMA_MUX3,XDMA_MUX4,XDMA_MUX5,XDMA_MUX6,XDMA_MUX7,XDMA_MUX8,XDMA_MUX9,XDMA_MUX10,XDMA_MUX11,XDMA_MUX12,XDMA_MUX13,XDMA_MUX14,XDMA_MUX15,XDMA_MUX16,XDMA_MUX17,XDMA_MUX18,XDMA_MUX19,XDMA_MUX20,XDMA_MUX21,XDMA_MUX22,XDMA_MUX23,XDMA_MUX24,XDMA_MUX25,XDMA_MUX26,XDMA_MUX27,XDMA_MUX28,XDMA_MUX29,XDMA_MUX30,XDMA_MUX31 + MUXCFG[%s] + no description available + 0x0 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + + + HDMA + HDMA + DMAV2 + 0xf00c8000 + + 0x4 + 0x43c + registers + + + + IDMisc + ID Misc + 0x4 + 32 + 0x00000000 + 0x0000FF00 + + + DMASTATE + DMA state machine +localparam ST_IDLE = 3'b000; +localparam ST_READ = 3'b001; +localparam ST_READ_ACK = 3'b010; +localparam ST_WRITE = 3'b011; +localparam ST_WRITE_ACK = 3'b100; +localparam ST_LL = 3'b101; +localparam ST_END = 3'b110; +localparam ST_END_WAIT = 3'b111; + 13 + 3 + read-only + + + CURCHAN + current channel in used + 8 + 5 + read-only + + + + + DMACfg + DMAC Configuration Register + 0x10 + 32 + 0x00000000 + 0xC3FFFFFF + + + CHAINXFR + Chain transfer +0x0: Chain transfer is not configured +0x1: Chain transfer is configured + 31 + 1 + read-only + + + REQSYNC + DMA request synchronization. +The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, +which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. +0x0: Request synchronization is not configured +0x1: Request synchronization is configured + 30 + 1 + read-only + + + DATAWIDTH + AXI bus data width +0x0: 32 bits +0x1: 64 bits +0x2: 128 bits +0x3: 256 bits + 24 + 2 + read-only + + + ADDRWIDTH + AXI bus address width +0x18: 24 bits +0x19: 25 bits +... +0x40: 64 bits +Others: Invalid + 17 + 7 + read-only + + + CORENUM + DMA core number +0x0: 1 core +0x1: 2 cores + 16 + 1 + read-only + + + BUSNUM + AXI bus interface number +0x0: 1 AXI bus +0x1: 2 AXI busses + 15 + 1 + read-only + + + REQNUM + Request/acknowledge pair number +0x0: 0 pair +0x1: 1 pair +0x2: 2 pairs +... +0x10: 16 pairs + 10 + 5 + read-only + + + FIFODEPTH + FIFO depth +0x4: 4 entries +0x8: 8 entries +0x10: 16 entries +0x20: 32 entries +Others: Invalid + 4 + 6 + read-only + + + CHANNELNUM + Channel number +0x1: 1 channel +0x2: 2 channels +... +0x8: 8 channels +Others: Invalid + 0 + 4 + read-only + + + + + DMACtrl + DMAC Control Register + 0x14 + 32 + 0x00000000 + 0x00000001 + + + RESET + Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. +Note: The software reset may cause the in-completion of AXI transaction. + 0 + 1 + write-only + + + + + ChAbort + Channel Abort Register + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + CHABORT + Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. +Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) + 0 + 32 + write-only + + + + + INTHALFSTS + Harlf Complete Interrupt Status + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + STS + half transfer done irq status + 0 + 32 + read-write + + + + + INTTCSTS + Trans Complete Interrupt Status Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + STS + The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. +0x0: Channel n has no terminal count status +0x1: Channel n has terminal count status + 0 + 32 + write-only + + + + + INTABORTSTS + Abort Interrupt Status Register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + STS + The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. +0x0: Channel n has no abort status +0x1: Channel n has abort status + 0 + 32 + write-only + + + + + INTERRSTS + Error Interrupt Status Register + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + STS + The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: +- Bus error +- Unaligned address +- Unaligned transfer width +- Reserved configuration +0x0: Channel n has no error status +0x1: Channel n has error status + 0 + 32 + write-only + + + + + ChEN + Channel Enable Register + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + CHEN + Alias of the Enable field of all ChnCtrl registers + 0 + 32 + read-only + + + + + 32 + 0x20 + ch0,ch1,ch2,ch3,ch4,ch5,ch6,ch7,ch8,ch9,ch10,ch11,ch12,ch13,ch14,ch15,ch16,ch17,ch18,ch19,ch20,ch21,ch22,ch23,ch24,ch25,ch26,ch27,ch28,ch29,ch30,ch31 + CHCTRL[%s] + no description available + 0x40 + + Ctrl + Channel &index0 Control Register + 0x0 + 32 + 0x00000000 + 0xFFFFF01F + + + INFINITELOOP + set to loop current config infinitely + 31 + 1 + read-write + + + HANDSHAKEOPT + 0: one request to transfer one burst +1: one request to transfer all the data defined in ch_tts + 30 + 1 + read-write + + + PRIORITY + Channel priority level +0x0: Lower priority +0x1: Higher priority + 29 + 1 + read-write + + + BURSTOPT + set to change burst_size definition + 28 + 1 + read-write + + + SRCBURSTSIZE + Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. +The burst transfer byte number is (SrcBurstSize * SrcWidth). +0x0: 1 transfer +0x1: 2 transfers +0x2: 4 transfers +0x3: 8 transfers +0x4: 16 transfers +0x5: 32 transfers +0x6: 64 transfers +0x7: 128 transfers +0x8: 256 transfers +0x9:512 transfers +0xa: 1024 transfers +0xb - 0xf: Reserved, setting this field with a reserved value triggers the error exception + 24 + 4 + read-write + + + SRCWIDTH + Source transfer width +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception + 21 + 3 + read-write + + + DSTWIDTH + Destination transfer width. +Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; +otherwise the error event will be triggered. +For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. +See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception + 18 + 3 + read-write + + + SRCMODE + Source DMA handshake mode +0x0: Normal mode +0x1: Handshake mode +Normal mode is enabled and started by software set Enable bit; +Handshake mode is enabled by software set Enable bit, started by hardware dma request from DMAMUX block + 17 + 1 + read-write + + + DSTMODE + Destination DMA handshake mode +0x0: Normal mode +0x1: Handshake mode +the difference bewteen Source/Destination handshake mode is: +the dma block will response hardware request after read in Source handshake mode; +the dma block will response hardware request after write in Destination handshake mode; +NOTE: can't set SrcMode and DstMode at same time, otherwise result unknown. + 16 + 1 + read-write + + + SRCADDRCTRL + Source address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 14 + 2 + read-write + + + DSTADDRCTRL + Destination address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 12 + 2 + read-write + + + INTHALFCNTMASK + Channel half interrupt mask +0x0: Allow the half interrupt to be triggered +0x1: Disable the half interrupt + 4 + 1 + read-write + + + INTABTMASK + Channel abort interrupt mask +0x0: Allow the abort interrupt to be triggered +0x1: Disable the abort interrupt + 3 + 1 + read-write + + + INTERRMASK + Channel error interrupt mask +0x0: Allow the error interrupt to be triggered +0x1: Disable the error interrupt + 2 + 1 + read-write + + + INTTCMASK + Channel terminal count interrupt mask +0x0: Allow the terminal count interrupt to be triggered +0x1: Disable the terminal count interrupt + 1 + 1 + read-write + + + ENABLE + Channel enable bit +0x0: Disable +0x1: Enable + 0 + 1 + read-write + + + + + TranSize + Channel &index0Transfer Size Register + 0x4 + 32 + 0x00000000 + 0x0FFFFFFF + + + TRANSIZE + Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. +If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + 0 + 28 + read-write + + + + + SrcAddr + Channel &index0 Source Address Low Part Register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SRCADDRL + Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + 0 + 32 + read-write + + + + + ChanReqCtrl + Channel &index0 DMA Request Control Register + 0xc + 32 + 0x00000000 + 0x1F1F0000 + + + SRCREQSEL + Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + 24 + 5 + read-write + + + DSTREQSEL + Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + 16 + 5 + read-write + + + + + DstAddr + Channel &index0 Destination Address Low Part Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + DSTADDRL + Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + 0 + 32 + read-write + + + + + LLPointer + Channel &index0 Linked List Pointer Low Part Register + 0x18 + 32 + 0x00000000 + 0xFFFFFFF8 + + + LLPOINTERL + Low part of the pointer to the next descriptor. The pointer must be double word aligned. + 3 + 29 + read-write + + + + + + + + XDMA + XDMA + DMAV2 + 0xf3008000 + + + GPIOM + GPIOM + GPIOM + 0xf00d8000 + + 0x0 + 0x800 + registers + + + + 16 + 0x80 + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz + ASSIGN[%s] + no description available + 0x0 + + 32 + 0x4 + PIN00,PIN01,PIN02,PIN03,PIN04,PIN05,PIN06,PIN07,PIN08,PIN09,PIN10,PIN11,PIN12,PIN13,PIN14,PIN15,PIN16,PIN17,PIN18,PIN19,PIN20,PIN21,PIN22,PIN23,PIN24,PIN25,PIN26,PIN27,PIN28,PIN29,PIN30,PIN31 + PIN[%s] + no description available + 0x0 + 32 + 0x00000000 + 0x80000303 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +2: cpu0 fastgpio + 0 + 2 + read-write + + + + + + + + ADC0 + ADC0 + ADC16 + 0xf00e0000 + + 0x0 + 0x1464 + registers + + + + 12 + 0x4 + trg0a,trg0b,trg0c,trg1a,trg1b,trg1c,trg2a,trg2b,trg2c,trg3a,trg3b,trg3c + CONFIG[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFF3F3F7F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interrupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interrupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interrupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + QUEUE_EN + preemption queue enable control + 6 + 1 + read-write + + + INTEN0 + interrupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + trg_dma_addr + No description available + 0x30 + 32 + 0x00000000 + 0xFFFFFFFC + + + TRG_DMA_ADDR + buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) + 2 + 30 + read-write + + + + + trg_sw_sta + No description available + 0x34 + 32 + 0x00000000 + 0x0000001F + + + TRG_SW_STA + SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it. + 4 + 1 + read-write + + + TRIG_SW_INDEX + which trigger for the SW trigger +0 for trig0a, 1 for trig0b… +3 for trig1a, …11 for trig3c + 0 + 4 + read-write + + + + + 16 + 0x4 + chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 + BUS_RESULT[%s] + no description available + 0x400 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + buf_cfg0 + No description available + 0x500 + 32 + 0x00000000 + 0x00000001 + + + WAIT_DIS + set to disable read waiting, get result immediately but maybe not current conversion result. + 0 + 1 + read-write + + + + + seq_cfg0 + No description available + 0x800 + 32 + 0x00000000 + 0x80000F1F + + + CYCLE + current dma write cycle bit + 31 + 1 + read-only + + + SEQ_LEN + sequence queue length, 0 for one, 0xF for 16 + 8 + 4 + read-write + + + RESTART_EN + if set together with cont_en, HW will continue process the whole queue after trigger once. +If cont_en is 0, this bit is not used + 4 + 1 + read-write + + + CONT_EN + if set, HW will continue process the queue till end(seq_len) after trigger once + 3 + 1 + read-write + + + SW_TRIG + SW trigger, pulse signal, cleared by HW one cycle later + 2 + 1 + write-only + + + SW_TRIG_EN + set to enable SW trigger + 1 + 1 + read-write + + + HW_TRIG_EN + set to enable external HW trigger, only trigger on posedge + 0 + 1 + read-write + + + + + seq_dma_addr + No description available + 0x804 + 32 + 0x00000000 + 0xFFFFFFFC + + + TAR_ADDR + dma target address, should be 4-byte aligned + 2 + 30 + read-write + + + + + seq_wr_addr + No description available + 0x808 + 32 + 0x00000000 + 0x00FFFFFF + + + SEQ_WR_POINTER + HW update this field after each dma write, it indicate the next dma write pointer. +dma write address is (tar_addr+seq_wr_pointer)*4 + 0 + 24 + read-only + + + + + seq_dma_cfg + No description available + 0x80c + 32 + 0x00000000 + 0x0FFF3FFF + + + STOP_POS + if stop_en is set, SW is responsible to update this field to the next read point, HW should not write data to this point since it's not read out by SW yet + 16 + 12 + read-write + + + DMA_RST + set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. +SW should clear all cycle bit in buffer to 0 before clear dma_rst + 13 + 1 + read-write + + + STOP_EN + set to stop dma if reach the stop_pos + 12 + 1 + read-write + + + BUF_LEN + dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 +0 for 4byte; +0xFFF for 16kbyte. + 0 + 12 + read-write + + + + + 16 + 0x4 + cfg0,cfg1,cfg2,cfg3,cfg4,cfg5,cfg6,cfg7,cfg8,cfg9,cfg10,cfg11,cfg12,cfg13,cfg14,cfg15 + SEQ_QUE[%s] + no description available + 0x810 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + seq_high_cfg + No description available + 0x850 + 32 + 0x00000000 + 0x00FFFFFF + + + STOP_POS_HIGH + No description available + 12 + 12 + read-write + + + BUF_LEN_HIGH + No description available + 0 + 12 + read-write + + + + + 16 + 0x10 + chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 + PRD_CFG[%s] + no description available + 0xc00 + + prd_cfg + No description available + 0x0 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + prd_thshd_cfg + No description available + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + prd_result + No description available + 0x8 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + + 16 + 0x4 + chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 + SAMPLE_CFG[%s] + no description available + 0x1000 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + conv_cfg1 + No description available + 0x1104 + 32 + 0x00000000 + 0x000001FF + + + CONVERT_CLOCK_NUMBER + convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider); +user can use small value to get faster conversion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. +Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC conversion(plus sample) need 25 cycles(50MHz). + 4 + 5 + read-write + + + CLOCK_DIVIDER + clock_period, N half clock cycle per half adc cycle +0 for same adc_clk and bus_clk, +1 for 1:2, +2 for 1:3, +... +15 for 1:16 +Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk + 0 + 4 + read-write + + + + + adc_cfg0 + No description available + 0x1108 + 32 + 0x00000000 + 0xA0000001 + + + SEL_SYNC_AHB + set to 1 will enable sync AHB bus, to get better bus performance. +Adc_clk must to be set to same as bus clock at this mode + 31 + 1 + read-write + + + ADC_AHB_EN + set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; + 29 + 1 + read-write + + + PORT3_REALTIME + set to enable trg queue stop other queues + 0 + 1 + read-write + + + + + int_sts + No description available + 0x1110 + 32 + 0x00000000 + 0xFFE0FFFF + + + TRIG_CMPT + interrupt for one trigger conversion complete if enabled + 31 + 1 + read-write + + + TRIG_SW_CFLCT + No description available + 30 + 1 + read-write + + + TRIG_HW_CFLCT + No description available + 29 + 1 + read-write + + + READ_CFLCT + read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel + 28 + 1 + read-write + + + SEQ_SW_CFLCT + sequence queue conflict interrupt, set if HW or SW trigger received during conversion + 27 + 1 + read-write + + + SEQ_HW_CFLCT + No description available + 26 + 1 + read-write + + + SEQ_DMAABT + dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set + 25 + 1 + read-write + + + SEQ_CMPT + the whole sequence complete interrupt + 24 + 1 + read-write + + + SEQ_CVC + one conversion complete in seq_queue if related seq_int_en is set + 23 + 1 + read-write + + + DMA_FIFO_FULL + DMA fifo full interrupt, user need to check clock frequency if it's set. + 22 + 1 + read-write + + + AHB_ERR + set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr + 21 + 1 + read-write + + + WDOG + set if one chanel watch dog event triggered + 0 + 16 + read-write + + + + + int_en + No description available + 0x1114 + 32 + 0x00000000 + 0xFFE0FFFF + + + TRIG_CMPT + interrupt for one trigger conversion complete if enabled + 31 + 1 + read-write + + + TRIG_SW_CFLCT + No description available + 30 + 1 + read-write + + + TRIG_HW_CFLCT + No description available + 29 + 1 + read-write + + + READ_CFLCT + read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel + 28 + 1 + read-write + + + SEQ_SW_CFLCT + sequence queue conflict interrupt, set if HW or SW trigger received during conversion + 27 + 1 + read-write + + + SEQ_HW_CFLCT + No description available + 26 + 1 + read-write + + + SEQ_DMAABT + dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set + 25 + 1 + read-write + + + SEQ_CMPT + the whole sequence complete interrupt + 24 + 1 + read-write + + + SEQ_CVC + one conversion complete in seq_queue if related seq_int_en is set + 23 + 1 + read-write + + + DMA_FIFO_FULL + DMA fifo full interrupt, user need to check clock frequency if it's set. + 22 + 1 + read-write + + + AHB_ERR + set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr + 21 + 1 + read-write + + + WDOG + set if one chanel watch dog event triggered + 0 + 16 + read-write + + + + + ana_ctrl0 + No description available + 0x1200 + 32 + 0x00000000 + 0x00001004 + + + ADC_CLK_ON + set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. +MUST set clock_period to 0 or 1 for adc16 reg access + 12 + 1 + read-write + + + STARTCAL + set to start the offset calibration cycle (Active H). user need to clear it after setting it. + 2 + 1 + read-write + + + + + ana_status + No description available + 0x1210 + 32 + 0x00000000 + 0x00000080 + + + CALON + Indicates if the ADC is in calibration mode (Active H). + 7 + 1 + read-write + + + + + 34 + 0x2 + adc16_para00,adc16_para01,adc16_para02,adc16_para03,adc16_para04,adc16_para05,adc16_para06,adc16_para07,adc16_para08,adc16_para09,adc16_para10,adc16_para11,adc16_para12,adc16_para13,adc16_para14,adc16_para15,adc16_para16,adc16_para17,adc16_para18,adc16_para19,adc16_para20,adc16_para21,adc16_para22,adc16_para23,adc16_para24,adc16_para25,adc16_para26,adc16_para27,adc16_para28,adc16_para29,adc16_para30,adc16_para31,adc16_para32,adc16_para33 + ADC16_PARAMS[%s] + no description available + 0x1400 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description available + 0 + 16 + read-write + + + + + adc16_config0 + No description available + 0x1444 + 32 + 0x00000000 + 0x01F07FFF + + + REG_EN + set to enable regulator + 24 + 1 + read-write + + + BANDGAP_EN + set to enable bandgap. user should set reg_en and bandgap_en before use adc16. + 23 + 1 + read-write + + + CAL_AVG_CFG + for average the calibration result. +0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; +4- 16 loops; 5-32 loops; others reserved + 20 + 3 + read-write + + + PREEMPT_EN + set to enable preemption feature + 14 + 1 + read-write + + + CONV_PARAM + conversion parameter + 0 + 14 + read-write + + + + + adc16_config1 + No description available + 0x1460 + 32 + 0x00000000 + 0x00001F00 + + + COV_END_CNT + used for faster conversion, user can change it to get higher convert speed(but less accuracy). +should set to (21-convert_clock_number+1). + 8 + 5 + read-write + + + + + + + I2S0 + I2S0 + I2S + 0xf0200000 + + 0x0 + 0x80 + registers + + + + CTRL + Control Register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SFTRST_RX + software reset the RX module if asserted to be 1'b1. Self-clear. + 18 + 1 + read-write + + + SFTRST_TX + software reset the TX module if asserted to be 1'b1. Self-clear. + 17 + 1 + read-write + + + SFTRST_CLKGEN + software reset the CLK GEN module if asserted to be 1'b1. Self-clear. + 16 + 1 + read-write + + + TXDNIE + TX buffer data needed interrupt enable +0: TXE interrupt masked +1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. + 15 + 1 + read-write + + + RXDAIE + RX buffer data available interrupt enable +0: RXNE interrupt masked +1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. + 14 + 1 + read-write + + + ERRIE + Error interrupt enable +This bit controls the generation of an interrupt when an error condition (UD, OV) occurs. +0: Error interrupt is masked +1: Error interrupt is enabled + 13 + 1 + read-write + + + TX_DMA_EN + Asserted to use DMA, else to use interrupt + 12 + 1 + read-write + + + RX_DMA_EN + Asserted to use DMA, else to use interrupt + 11 + 1 + read-write + + + TXFIFOCLR + Self-clear + 10 + 1 + read-write + + + RXFIFOCLR + Self-clear + 9 + 1 + read-write + + + TX_EN + enable for each TX data pad + 5 + 4 + read-write + + + RX_EN + enable for each RX data pad + 1 + 4 + read-write + + + I2S_EN + enable for the module + 0 + 1 + read-write + + + + + RFIFO_FILLINGS + Rx FIFO Filling Level + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RX3 + RX3 fifo fillings + 24 + 8 + read-only + + + RX2 + RX2 fifo fillings + 16 + 8 + read-only + + + RX1 + RX1 fifo fillings + 8 + 8 + read-only + + + RX0 + RX0 fifo fillings + 0 + 8 + read-only + + + + + TFIFO_FILLINGS + Tx FIFO Filling Level + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TX3 + TX3 fifo fillings + 24 + 8 + read-only + + + TX2 + TX2 fifo fillings + 16 + 8 + read-only + + + TX1 + TX1 fifo fillings + 8 + 8 + read-only + + + TX0 + TX0 fifo fillings + 0 + 8 + read-only + + + + + FIFO_THRESH + TX/RX FIFO Threshold setting. + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + TX + TX fifo threshold to trigger STA[tx_dn]. When tx fifo filling is smaller than or equal to the threshold, assert the tx_dn flag. + 8 + 8 + read-write + + + RX + RX fifo threshold to trigger STA[rx_da]. When rx fifo filling is greater than or equal to the threshold, assert the rx_da flag. + 0 + 8 + read-write + + + + + STA + Status Registers + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + TX_UD + Asserted when tx fifo is underflow. Should be ANDed with CTRL[tx_en] the for correct value. Write 1 to any of these 4 bits will clear the underflow error. + 13 + 4 + write-only + + + RX_OV + Asserted when rx fifo is overflow. Write 1 to any of these 4 bits will clear the overflow error. + 9 + 4 + write-only + + + TX_DN + Asserted when tx fifo data are needed. + 5 + 4 + read-only + + + RX_DA + Asserted when rx fifo data are available. + 1 + 4 + read-only + + + + + 4 + 0x4 + DATA0,DATA1,DATA2,DATA3 + RXD[%s] + no description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + D + No description available + 0 + 32 + read-only + + + + + 4 + 0x4 + DATA0,DATA1,DATA2,DATA3 + TXD[%s] + no description available + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + D + No description available + 0 + 32 + write-only + + + + + CFGR + Configruation Regsiters + 0x50 + 32 + 0x40000000 + 0xFFFFFFFF + + + BCLK_GATEOFF + Gate off the bclk. Asserted to gate-off the BCLK. + 30 + 1 + read-write + + + BCLK_DIV + Linear prescaler to generate BCLK from MCLK. +BCLK_DIV [8:0] = 0: BCLK=No CLK. +BCLK_DIV [8:0] = 1: BCLK=MCLK/1 +BCLK_DIV [8:0] = n: BCLK=MCLK/(n). +Note: These bits should be configured when the I2S is disabled. It is used only when the I2S is in master mode. + 21 + 9 + read-write + + + INV_BCLK_OUT + Invert the BCLK before sending it out to pad. Only valid in BCLK master mode + 20 + 1 + read-write + + + INV_BCLK_IN + Invert the BCLK pad input before using it internally. Only valid in BCLK slave mode + 19 + 1 + read-write + + + INV_FCLK_OUT + Invert the FCLK before sending it out to pad. Only valid in FCLK master mode + 18 + 1 + read-write + + + INV_FCLK_IN + Invert the FCLK pad input before using it internally. Only valid in FCLK slave mode + 17 + 1 + read-write + + + INV_MCLK_OUT + Invert the MCLK before sending it out to pad. Only valid in MCLK master mode + 16 + 1 + read-write + + + INV_MCLK_IN + Invert the MCLK pad input before using it internally. Only valid in MCLK slave mode + 15 + 1 + read-write + + + BCLK_SEL_OP + asserted to use external clk source + 14 + 1 + read-write + + + FCLK_SEL_OP + asserted to use external clk source + 13 + 1 + read-write + + + MCK_SEL_OP + asserted to use external clk source + 12 + 1 + read-write + + + FRAME_EDGE + The start edge of a frame +0: Falling edge indicates a new frame (Just like standard I2S Philips standard) +1: Rising edge indicates a new frame + 11 + 1 + read-write + + + CH_MAX + CH_MAX[4:0] s the number of channels supported in TDM mode. When not in TDM mode, it must be set as 2. +It must be an even number, so CH_MAX[0] is always 0. +5'h2: 2 channels +5'h4: 4 channels +... +5‘h10: 16 channels (max) + 6 + 5 + read-write + + + TDM_EN + TDM mode +0: not TDM mode +1: TDM mode + 5 + 1 + read-write + + + STD + I2S standard selection +00: I2S Philips standard. +01: MSB justified standard (left justified) +10: LSB justified standard (right justified) +11: PCM standard +Note: For correct operation, these bits should be configured when the I2S is disabled. + 3 + 2 + read-write + + + DATSIZ + Data length to be transferred +00: 16-bit data length +01: 24-bit data length +10: 32-bit data length +11: Not allowed +Note: For correct operation, these bits should be configured when the I2S is disabled. + 1 + 2 + read-write + + + CHSIZ + Channel length (number of bits per audio channel) +0: 16-bit wide +1: 32-bit wide +The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. +Note: For correct operation, this bit should be configured when the I2S is disabled. + 0 + 1 + read-write + + + + + MISC_CFGR + Misc configuration Registers + 0x58 + 32 + 0x00042000 + 0xFFFFEC01 + + + MCLK_GATEOFF + Gate off the mclk. This mclk is the output of a glitch prone mux, so every time to switch the mclk, the gate off clock should be asserted at first. After the clock is switched, de-assert this bit to ungate off the mclk. + 13 + 1 + read-write + + + MCLKOE + Master clock output to pad enable +0: Master clock output is disabled +1: Master clock output is enabled +Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. + 0 + 1 + read-write + + + + + 4 + 0x4 + DATA0,DATA1,DATA2,DATA3 + RXDSLOT[%s] + no description available + 0x60 + 32 + 0x0000FFFF + 0x0000FFFF + + + EN + No description available + 0 + 16 + read-write + + + + + 4 + 0x4 + DATA0,DATA1,DATA2,DATA3 + TXDSLOT[%s] + no description available + 0x70 + 32 + 0x0000FFFF + 0x0000FFFF + + + EN + No description available + 0 + 16 + read-write + + + + + + + I2S1 + I2S1 + I2S + 0xf0204000 + + + I2S2 + I2S2 + I2S + 0xf0208000 + + + I2S3 + I2S3 + I2S + 0xf020c000 + + + DAO + DAO + DAO + 0xf0210000 + + 0x0 + 0x1c + registers + + + + CTRL + Control Register + 0x0 + 32 + 0x00000000 + 0x000200FF + + + HPF_EN + Whether HPF is enabled. This HPF is used to filter out the DC part. + 17 + 1 + read-write + + + MONO + Asserted to let the left and right channel output the same value. + 7 + 1 + read-write + + + RIGHT_EN + Asserted to enable the right channel + 6 + 1 + read-write + + + LEFT_EN + Asserted to enable the left channel + 5 + 1 + read-write + + + REMAP + 1: Use remap pwm version. The remap version is a version that one pwm output is tied to zero when the input pcm signal is positive or negative +0: Don't use remap pwm version + 4 + 1 + read-write + + + INVERT + all the outputs are inverted before sending to pad + 3 + 1 + read-write + + + FALSE_LEVEL + the pad output in False run mode, or when the module is disabled +0: all low +1: all high +2: P-high, N-low +3. output is not enabled + 1 + 2 + read-write + + + FALSE_RUN + the module continues to consume data, but all the pads are constant, thus no audio out + 0 + 1 + read-write + + + + + CMD + Command Register + 0x8 + 32 + 0x00000000 + 0x00000003 + + + SFTRST + Self-clear + 1 + 1 + read-write + + + RUN + Enable this module to run. + 0 + 1 + read-write + + + + + RX_CFGR + Configuration Register + 0xc + 32 + 0x00000000 + 0x00000FFF + + + FRAME_EDGE + The start edge of a frame +0: Falling edge indicates a new frame (Just like standard I2S Philips standard) +1: Rising edge indicates a new frame + 11 + 1 + read-write + + + CH_MAX + CH_MAX[3:0] is the number if channels supported in TDM mode. When not in TDM mode, it must be set as 2. +It must be an even number, so CH_MAX[0] is always 0. +4'h2: 2 channels +4'h4: 4 channels +etc + 6 + 5 + read-write + + + TDM_EN + TDM mode +0: not TDM mode +1: TDM mode + 5 + 1 + read-write + + + STD + I2S standard selection +00: I2S Philips standard. +01: MSB justified standard (left justified) +10: LSB justified standard (right justified) +11: PCM standard +For more details on I2S standards. +Note: For correct operation, these bits should be configured when the I2S is disabled. + 3 + 2 + read-write + + + DATSIZ + Data length to be transferred +00: 16-bit data length +01: 24-bit data length +10: 32-bit data length +11: Not allowed +Note: For correct operation, these bits should be configured when the I2S is disabled. + 1 + 2 + read-write + + + CHSIZ + Channel length (number of bits per audio channel) +0: 16-bit wide +1: 32-bit wide +The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. +Note: For correct operation, this bit should be configured when the I2S is disabled. + 0 + 1 + read-write + + + + + RXSLT + RX Slot Control Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + EN + Slot enable for the channels. + 0 + 32 + read-write + + + + + HPF_MA + HPF A Coef Register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + COEF + Composite value of coef A of the Order-1 HPF + 0 + 32 + read-write + + + + + HPF_B + HPF B Coef Register + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + COEF + coef B of the Order-1 HPF + 0 + 32 + read-write + + + + + + + PDM + PDM + PDM + 0xf0214000 + + 0x0 + 0x34 + registers + + + + CTRL + Control Register + 0x0 + 32 + 0x00000000 + 0x809FF7FF + + + SFTRST + software reset the module. Self-clear. + 31 + 1 + read-write + + + SOF_FEDGE + asserted if the falling edge of the ref fclk from DAO is the start of a new frame. This is used to to align DAO feedback signal. + 23 + 1 + read-write + + + USE_COEF_RAM + Asserted to use Coef RAM instead of Coef ROM + 20 + 1 + read-write + + + FILT_CRX_ERR_IE + data accessed out of boundary error interruput enable. The error happens when the module cannot calculate the enough number of data in time. + 19 + 1 + read-write + + + OFIFO_OVFL_ERR_IE + output fifo overflow error interrupt enable + 18 + 1 + read-write + + + CIC_OVLD_ERR_IE + CIC overload error interrupt enable + 17 + 1 + read-write + + + CIC_SAT_ERR_IE + Error interrupt enable +This bit controls the generation of an interrupt when an error condition (CIC saturation) occurs. +0: Error interrupt is masked +1: Error interrupt is enabled + 16 + 1 + read-write + + + DEC_AFT_CIC + decimation rate after CIC. Now it is forced to be 3. + 12 + 4 + read-write + + + CAPT_DLY + Capture cycle delay>=0, should be less than PDM_CLK_HFDIV + 7 + 4 + read-write + + + PDM_CLK_HFDIV + The clock divider will work at least 4. +0: div-by-2, +1: div-by-4 +. . . +n: div-by-2*(n+1) + 3 + 4 + read-write + + + PDM_CLK_DIV_BYPASS + asserted to bypass the pdm clock divider + 2 + 1 + read-write + + + PDM_CLK_OE + pdm_clk_output_en + 1 + 1 + read-write + + + HPF_EN + pdm high pass filter enable. This order-1 HPF only applies to the PDM mic data. + 0 + 1 + read-write + + + + + CH_CTRL + Channel Control Register + 0x4 + 32 + 0x00000000 + 0x00FF03FF + + + CH_POL + Asserted to select PDM_CLK high level captured, otherwise to select PDM_CLK low level captured. + 16 + 8 + read-write + + + CH_EN + Asserted to enable the channel. +Ch8 & 9 are refs. +Ch0-7 are pdm mics. + 0 + 10 + read-write + + + + + ST + Status Register + 0x8 + 32 + 0x00000000 + 0x0000000F + + + FILT_CRX_ERR + data accessed out of boundary error + 3 + 1 + write-only + + + OFIFO_OVFL_ERR + output fifo overflow error. The reason may be sampling frequency mismatch, either fast or slow. + 2 + 1 + write-only + + + CIC_OVLD_ERR + CIC overload error. write 1 clear + 1 + 1 + write-only + + + CIC_SAT_ERR + CIC saturation. Write 1 clear + 0 + 1 + write-only + + + + + CH_CFG + Channel Configuration Register + 0xc + 32 + 0x00000000 + 0x000FFFFF + + + CH9_TYPE + No description available + 18 + 2 + read-write + + + CH8_TYPE + No description available + 16 + 2 + read-write + + + CH7_TYPE + No description available + 14 + 2 + read-write + + + CH6_TYPE + No description available + 12 + 2 + read-write + + + CH5_TYPE + No description available + 10 + 2 + read-write + + + CH4_TYPE + No description available + 8 + 2 + read-write + + + CH3_TYPE + No description available + 6 + 2 + read-write + + + CH2_TYPE + No description available + 4 + 2 + read-write + + + CH1_TYPE + No description available + 2 + 2 + read-write + + + CH0_TYPE + Type of Channel 0 +2'b00: dec-by-3 wiith filter type0 (CIC Compenstation+norm filter) +2'b01: dec-by-3 with filter type 1 (No CIC compenstation, only norm filter) + 0 + 2 + read-write + + + + + CIC_CFG + CIC configuration register + 0x10 + 32 + 0x00000000 + 0x0000FFFF + + + POST_SCALE + the shift value after CIC results. + 10 + 6 + read-write + + + SGD + Sigma_delta_order[1:0] +2'b00: 7 +2'b01: 6 +2'b10: 5 +Others: unused + 8 + 2 + read-write + + + CIC_DEC_RATIO + CIC decimation factor + 0 + 8 + read-write + + + + + CTRL_INBUF + In Buf Control Register + 0x14 + 32 + 0x00000000 + 0x3FFFFFFF + + + MAX_PTR + The buf size-1 for each channel + 22 + 8 + read-write + + + PITCH + The spacing between starting address of adjacent channels + 11 + 11 + read-write + + + START_ADDR + The starting address of channel 0 in filter data buffer + 0 + 11 + read-write + + + + + CTRL_FILT0 + Filter 0 Control Register + 0x18 + 32 + 0x00000000 + 0x0000FFFF + + + COEF_LEN_M0 + Coef length of filter type 2'b00 in coef memory + 8 + 8 + read-write + + + COEF_START_ADDR + Starting address of Coef of filter type 2'b00 in coef memory + 0 + 8 + read-write + + + + + CTRL_FILT1 + Filter 1 Control Register + 0x1c + 32 + 0x00000000 + 0x0000FFFF + + + COEF_LEN_M1 + Coef length of filter type 2'b01 in coef memory + 8 + 8 + read-write + + + COEF_START_ADDR + Starting address of Coef of filter type 2'b01 in coef memory + 0 + 8 + read-write + + + + + RUN + Run Register + 0x20 + 32 + 0x00000000 + 0x00000001 + + + PDM_EN + Asserted to enable the module + 0 + 1 + read-write + + + + + MEMAddr + Memory Access Address + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + 0--0x0FFFFFFF: COEF_RAM +0x10000000--0x1FFFFFFF: DATA_RAM + 0 + 32 + read-write + + + + + MEMData + Memory Access Data + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + The data write-to/read-from buffer + 0 + 32 + read-write + + + + + HPF_MA + HPF A Coef Register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + COEF + Composite value of coef A of the Order-1 HPF + 0 + 32 + read-write + + + + + HPF_B + HPF B Coef Register + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + COEF + coef B of the Order-1 HPF + 0 + 32 + read-write + + + + + + + SMIX + SMIX + SMIX + 0xf0218000 + + 0x0 + 0xac0 + registers + + + + DMAC_ID + DMAC_ID Register + 0x0 + 32 + 0x00000001 + 0x0007FFFF + + + REV + Revision + 0 + 19 + read-only + + + + + DMAC_TC_ST + Transfer Complete Status + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH + The terminal count status is set when a channel transfer finishes without abort or error events + 0 + 26 + write-only + + + + + DMAC_ABRT_ST + Transfer Abort Status + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH + The abort status is set when a channel transfer is aborted + 0 + 26 + write-only + + + + + DMAC_ERR_ST + Transfer Error Status + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + CH + The error status is set when a channel transfer encounters the following error events: +. Bus error +. Unaligned address +. Unaligned transfer width +. Reserved configuration + 0 + 26 + write-only + + + + + DMAC_CTRL + Control Register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + SRST + Software Reset + 0 + 1 + read-write + + + + + DMAC_ABRT_CMD + Abort Command Register + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH + Write 1 to force the corresponding channel into abort status + 0 + 26 + write-only + + + + + DMAC_CHEN + Channel Enable Register + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH + Write 1 to enable the corresponding channel + 0 + 26 + read-only + + + + + 26 + 0x20 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25 + DMA_CH[%s] + no description available + 0x40 + + CTL + Channel N Control Register + 0x0 + 32 + 0x00000000 + 0xFFEFFFEF + + + SRCREQSEL + Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + 26 + 5 + read-write + + + DSTREQSEL + Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + 21 + 5 + read-write + + + PRIORITY + 0x0: Lower priority +0x1: Higher priority + 19 + 1 + read-write + + + SRCBURSTSIZE + 0x0: 1 beat per transfer +0x1: 2 beats per transfer +0x2: 4 beats per transfer +0x3: 8 beats per transfer +0x4: 16 beats per transfer +0x5: 32 beats per transfer +0x6: 64 beats per transfer +0x7: 128 beats per transfer + 15 + 4 + read-write + + + SRCWIDTH + Source Transfer Beat Size: +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer + 13 + 2 + read-write + + + DSTWIDTH + Destination Transfer Beat Size: +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer + 11 + 2 + read-write + + + SRCMODE + DMA Source handshake mode +0x0: Normal mode +0x1: Handshake mode + 10 + 1 + read-write + + + DSTMODE + DMA Destination handshake mode +0x0: Normal mode +0x1: Handshake mode + 9 + 1 + read-write + + + SRCADDRCTRL + 0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers an error exception + 7 + 2 + read-write + + + DSTADDRCTRL + 0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers an error exception + 5 + 2 + read-write + + + ABRT_INT_EN + Abort interrupt enable + 3 + 1 + read-write + + + ERR_INT_EN + Err interrupt enable + 2 + 1 + read-write + + + TC_INT_EN + TC interrupt enable + 1 + 1 + read-write + + + EN + channel enable bit + 0 + 1 + read-write + + + + + BURST_COUNT + Channel N Source Total Beats Register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + NUM + the total number of source beats + 0 + 32 + read-write + + + + + SrcAddr + Channel N Source Register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + PTR + source address + 0 + 32 + read-write + + + + + DstAddr + Channel N Destination Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + PTR + destination address + 0 + 32 + read-write + + + + + LLP + Channel N Linked List Pointer Register + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + PTR + the address pointer for the linked list descriptor + 0 + 32 + read-write + + + + + + CALSAT_ST + SMIX Cal Saturation Status Register + 0x800 + 32 + 0x00000000 + 0xFFFFFFFF + + + DST + DST CAL_SAT_ERR. W1C + 30 + 2 + write-only + + + SRC + SRC CAL_SAT_ERR. W1C + 0 + 14 + write-only + + + + + FDOT_DONE_ST + SMIX Fade-Out Done Status Register + 0x804 + 32 + 0x00000000 + 0xFFFFFFFF + + + DST + DST fadeout done. W1C + 30 + 2 + write-only + + + SRC + SRC fadeout done. W1C + 0 + 14 + write-only + + + + + DATA_ST + SMIX Data Status Register + 0x808 + 32 + 0x00000000 + 0xFFFFFFFF + + + DST_DA + DST data available + 30 + 2 + read-only + + + DST_UNDL + DST data underflow + 28 + 2 + read-only + + + SRC_DN + SRC data needed + 0 + 14 + read-only + + + + + 2 + 0x40 + 0,1 + DST_CH[%s] + no description available + 0x840 + + CTRL + SMIX Dstination N Control Register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA_UNFL_IE + Data Underflow Error IntEn + 20 + 1 + read-write + + + THRSH + FIFO threshold for DMA or Int. >= will generate req. Must be greater or equal than 8. The read burst of DMA should make the fillings in the buffer be greater than 4. + 12 + 8 + read-write + + + CALSAT_INT_EN + Cal Saturation IntEn + 11 + 1 + read-write + + + DA_INT_EN + Data Available IntEn + 10 + 1 + read-write + + + ADEACTFADEOUT_EN + AutoDeactAfterFadeOut_En: +Asserted to enter de-activated mode after fade-out done + 9 + 1 + read-write + + + FADEOUT_DONE_IE + Fade-Out interrupt enable + 8 + 1 + read-write + + + DST_DEACT + de-activate the destination channel + 7 + 1 + read-write + + + DST_ACT + activate the destination channel + 6 + 1 + read-write + + + DSTFADOUT_MEN + Manual FadeOut_Ctrl for destionation. Auto clear. + 5 + 1 + read-write + + + DSTFADOUT_AEN + Automatically FadeOut_Ctrl for destionation. Only effective after DST_AFADEOUT is assigned a non-zero value + 4 + 1 + read-write + + + DSTFADIN_EN + FadeIn_Ctrl for destionation. Auto clear. + 3 + 1 + read-write + + + DST_EN + Dst enabled. When disabled, clear the FIFO pointers. + 2 + 1 + read-write + + + SOFTRST + Soft reset + 1 + 1 + read-write + + + MIXER_EN + mixer function enable. + 0 + 1 + read-write + + + + + GAIN + SMIX Dstination N Gain Register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + Unsigned Int, with 12 fractional bits. . The top 3 bits are for shift. Same as SHFT_CTR[2:0] + 0 + 15 + read-write + + + + + BUFSIZE + SMIX Dstination N Max Index Register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + MAX_IDX + The total length of the dst stream -1. If zero, means there is no end of the stream. + 0 + 32 + read-write + + + + + FADEIN + SMIX Dstination N Fade-In Configuration Register + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + DELTA + Fade-in delta for linear fading in from 0 to 1 (about at most 20s for 48kHz sampled sound) +(Using only top 14 bits for mul) + 0 + 20 + read-write + + + + + FADEOUT + SMIX Dstination N Fade-Out Configuration Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + DELTA + Fade out in 2^DELTA samples. Now DELTA can be at most 14。 + 0 + 20 + read-write + + + + + ST + SMIX Dstination N Status Register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + FIFO_FILLINGS + destination channel output FIFO fillings + 6 + 9 + read-only + + + FDOUT_DONE + Fade-Out Done. W1C + 5 + 1 + read-only + + + CALSAT + Saturate Error Found. W1C + 4 + 1 + read-only + + + DA + Data Available + 3 + 1 + read-only + + + MODE + The modes are: +Mode 0: Disabled: after reset. Program the registers, and DSTn_CTRL [DST_EN] to enter Mode 1. +Mode 1: Enabled and not-activated. wait for DSTn_CTRL [DSTFADIN_EN] or DSTn_CTRL [DST_ACT], jump to Mode 3 or Mode 4 based on whether Fade-in enabled. +Mode 3: Enabled and activated and fade-in in progress: Can not be fade out. Will send data to DMA. Jump to Mode 4 after fadin op done. +Mode 4: Enabled and activated and done fade-in, no fade-out yet: Can be fade out. Will send data to DMA. +Mode 5: Enabled and activated and fade-out in progress: After faded out OP. Will send data to DMA. Will transfer to mode 6 or mode 7 depending on the DSTn_CTRL [ADeactFadeOut_En] cfg +Mode 6: Enabled and activated and faded-out: faded out is done. Will send data to DMA. Will transfer to mode 7 if manual deactivated. +Mode 7: Enabled and De-activated: If configured to enter this mode, after auto or manuallly fade-out, or after manual de-activated. Won't send data to DMA. Won't gen data avail signals. Intf register can be programmed. Will change to Mode 3 or Mode 4 after manual ACT or Fade-in CMD. Will transfer to Mode 0 if DSTn_CTRL [DST_EN] is assigned 0. To support a new stream or, to continue the old stream after a pause. + 0 + 3 + read-only + + + + + Data + SMIX Dstination N Data Out Register + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + Output data buffer + 0 + 32 + read-only + + + + + SOURCE_EN + SMIX Dstination N Source Enable Register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + After enabled, Data needed req will be asserted. DMA can feed in data. The channel will join in the sum operation of mixer operation. + 0 + 8 + read-write + + + + + SOURCE_ACT + SMIX Dstination N Source Activation Register + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + Manually Activate the channel + 0 + 8 + write-only + + + + + SOURCE_DEACT + SMIX Dstination N Source De-Activation Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + Manually DeActivate the channel + 0 + 8 + write-only + + + + + SOURCE_FADEIN_CTRL + SMIX Dstination N Source Fade-in Control Register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + AOP + Asserted to start fade-in operation. When the amplification factors are stable, auto clear. + 0 + 8 + read-write + + + + + DEACT_ST + SMIX Dstination N Source Deactivation Status Register + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + DST_DEACT + Asserted when in de-active mode + 31 + 1 + read-only + + + SRC_DEACT_ST + Asserted when in de-active mode + 0 + 8 + read-only + + + + + SOURCE_MFADEOUT_CTRL + SMIX Dstination N Source Manual Fade-out Control Register + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + OP + Asserted to start fade-out operation. When the amplification factors are stable, auto clear. + 0 + 8 + read-write + + + + + + 14 + 0x20 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13 + SOURCE_CH[%s] + no description available + 0x900 + + CTRL + SMIX Source N Control Register + 0x0 + 32 + 0x00000000 + 0xFFFFFFC7 + + + FIFO_RESET + Asserted to reset FIFO pointer. Cleared to exit reset state. + 21 + 1 + read-write + + + THRSH + FIFO threshold for DMA or Int. <= will generate req. Must be greater or equal than 8. This threshold is also used to trgger the internal FIR operation. To avoid the reading and writing to the same address in the memory block, the threshold should greater than 4. + 13 + 8 + read-write + + + CALSAT_INT_EN + Cal Saturation IntEn + 12 + 1 + read-write + + + DN_INT_EN + Data Needed IntEn + 11 + 1 + read-write + + + SHFT_CTRL + Shift operation after FIR +0: no shift (when no upsampling or up-sampling-by-2 or up-sampling-by-3) +1: left-shift-by-1 (when up-sampling-by-4 or up-sampling-by-6) +2: left-shift-by-1 (when up-sampling-by-8 or up-sampling-by-12) +7: /2 (when rate /2) +Other n: shift-left-by-n, but not suggested to be used. + 8 + 3 + read-write + + + AUTODEACTAFTERFADEOUT_EN + Asserted to enter de-activated mode after fade-out done + 7 + 1 + read-write + + + FADEOUT_DONE_IE + Fade-Out interrupt enable + 6 + 1 + read-write + + + RATECONV + 0: no rate conversion +1: up-conversion x2 +2: up-conversion x3 +3: up-conversion x4 +4: up-conversion x6 +5: up-conversion x8 +6: up-conversion x12 +7: down-conversion /2 + 0 + 3 + read-write + + + + + GAIN + SMIX Source N Gain Register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + Unsigned Int, with 12 fractional bits. The top 3 bits are for shift. Same as SHFT_CTR[2:0]. + 0 + 15 + read-write + + + + + FADEIN + SMIX Source N Fade-in Control Register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DELTA + Fade -in confg. + 0 + 20 + read-write + + + + + FADEOUT + SMIX Source N Fade-out Control Register + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + DELTA + Fade out in 2^DELTA samples. Now DELTA can be at most 14。 + 0 + 20 + read-write + + + + + BufSize + SMIX Source N Buffer Size Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + MAXIDX + unit as 16-bits per sample. Zero means no length limit. = Act Len-1. +The actual length is the up_rate*(input_data_length-4). +If the filter processing is down-sampling, the value of up_rate above is 1. +If the filter processing is up-sampling, the value of up_rate above is the up-sampling rate. + 0 + 32 + read-write + + + + + ST + SMIX Source N Status Register + 0x14 + 32 + 0x00000000 + 0x0007FFFF + + + FIFO_FILLINGS + The fillings of input FIFO. + 10 + 9 + read-only + + + FDOUT_DONE + Fade-Out Done. W1C + 9 + 1 + write-only + + + CALSAT + Calculation saturation status. W1C + 8 + 1 + write-only + + + DN + Data needed flag + 7 + 1 + read-only + + + FIRPHASE + the poly phase counter + 3 + 4 + read-only + + + MODE + The modes are: +Mode 0: Disabled: after reset. Program the registers, and DSTx_SRC_EN[n] to enter Mode 1. +Mode 1: Enabled but not activated: After Enabled. Data needed signal can send out, can receive DMA data. Will enter Mode 2 after manual ACT or Fade-in CMD +Mode 2: Enabled and activated and buffer feed-in in progress: Can not be fade out. Will consume data from DMA. If not enter due to Fade-in CMD, will enter Mode 4, else enter Mode 3. This mode is used to make the channel in MIX only after initial data are ready, thus will not stall mix operation due to the lackness of data of this channel omly. +Mode 3: Enabled and activated and fade-in in progress: Can not be fade out. Will consume data from DMA. +Mode 4: Enabled and activated and done fade-in, no fade-out yet: Can be fade out. Will consume data from DMA. +Mode 5: Enabled and activated and fade-out in progress: After faded out done. Will consume data from DMA. Will transfer to mode 6 or mode 7 depending on the SRCn_CTRL[AutoDeactAfterFadeOut_En] cfg +Mode 6: Enabled and activated and faded-out: faded out is done. Will consume data from DMA. Will transfer to mode 7 if manual deactivated. +Mode 7: Enabled and De-activated: If configured to enter this mode, after auto or manuallly fade-out, or after manual de-activated. Won't consume data from DMA. Won't gen data needed signals. Intf register can be programmed. Will change to Mode 2 after manual ACT or Fade-in CMD. Will transfer to Mode 0 if DSTx_SRC_EN[n] is assigned 0. To support a new stream or, to continue the old stream after a pause. + 0 + 3 + read-only + + + + + Data + SMIX Source N Data Input Register + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + Data input register + 0 + 32 + write-only + + + + + + + + MCAN0 + MCAN0 + MCAN + 0xf0280000 + + 0x4 + 0x29fc + registers + + + + ENDN + endian register + 0x4 + 32 + 0x87654321 + 0xFFFFFFFF + + + EVT + Endianness Test Value +The endianness test value is 0x87654321. + 0 + 32 + read-only + + + + + DBTP + data bit timing and prescaler, writeable when CCCR.CCE and CCCR.INT are set + 0xc + 32 + 0x00000A33 + 0x009F1FFF + + + TDC + transmitter delay compensation enable +0= Transmitter Delay Compensation disabled +1= Transmitter Delay Compensation enabled + 23 + 1 + read-write + + + DBRP + Data Bit Rate Prescaler +The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. +When TDC = ‘1’, the range is limited to 0,1. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + 16 + 5 + read-write + + + DTSEG1 + Data time segment before sample point +Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. + 8 + 5 + read-write + + + DTSEG2 + Data time segment after sample point +Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. + 4 + 4 + read-write + + + DSJW + Data (Re)Synchronization Jump Width +Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + 0 + 4 + read-write + + + + + TEST + test register + 0x10 + 32 + 0x00000000 + 0x003F3FF0 + + + SVAL + Started Valid +0= Value of TXBNS not valid +1= Value of TXBNS valid + 21 + 1 + read-only + + + TXBNS + Tx Buffer Number Started +Tx Buffer number of message whose transmission was started last. Valid when SVAL is set. Valid values are 0 to 31. + 16 + 5 + read-only + + + PVAL + Prepared Valid +0= Value of TXBNP not valid +1= Value of TXBNP valid + 13 + 1 + read-only + + + TXBNP + Tx Buffer Number Prepared +Tx Buffer number of message that is ready for transmission. Valid when PVAL is set.Valid values are 0 to 31. + 8 + 5 + read-only + + + RX + Receive Pin +Monitors the actual value of pin m_can_rx +0= The CAN bus is dominant (m_can_rx = ‘0’) +1= The CAN bus is recessive (m_can_rx = ‘1’) + 7 + 1 + read-only + + + TX + Control of Transmit Pin +00 Reset value, m_can_tx controlled by the CAN Core, updated at the end of the CAN bit time +01 Sample Point can be monitored at pin m_can_tx +10 Dominant (‘0’) level at pin m_can_tx +11 Recessive (‘1’) at pin m_can_tx + 5 + 2 + read-write + + + LBCK + Loop Back Mode +0= Reset value, Loop Back Mode is disabled +1= Loop Back Mode is enabled + 4 + 1 + read-write + + + + + RWD + ram watchdog + 0x14 + 32 + 0x00000000 + 0x0000FFFF + + + WDV + Watchdog Value +Actual Message RAM Watchdog Counter Value. + 8 + 8 + read-only + + + WDC + Watchdog Configuration +Start value of the Message RAM Watchdog Counter. With the reset value of “00” the counter is disabled. + 0 + 8 + read-write + + + + + CCCR + CC control register + 0x18 + 32 + 0x00000001 + 0x0000FFFF + + + NISO + Non ISO Operation +If this bit is set, the M_CAN uses the CAN FD frame format as specified by the Bosch CAN FD +Specification V1.0. +0= CAN FD frame format according to ISO 11898-1:2015 +1= CAN FD frame format according to Bosch CAN FD Specification V1.0 +Note: When the generic parameter iso_only_g is set to ‘1’ in hardware synthesis, this bit becomes reserved and is read as ‘0’. The M_CAN always operates with the CAN FD frame format according to ISO 11898-1:2015. + 15 + 1 + read-write + + + TXP + Transmit Pause +If this bit is set, the M_CAN pauses for two CAN bit times before starting the next transmission after +itself has successfully transmitted a frame (see Section 3.5). +0= Transmit pause disabled +1= Transmit pause enabled + 14 + 1 + read-write + + + EFBI + Edge Filtering during Bus Integration +0= Edge filtering disabled +1= Two consecutive dominant tq required to detect an edge for hard synchronization + 13 + 1 + read-write + + + PXHD + Protocol Exception Handling Disable +0= Protocol exception handling enabled +1= Protocol exception handling disabled +Note: When protocol exception handling is disabled, the M_CAN will transmit an error frame when it detects a protocol exception condition. + 12 + 1 + read-write + + + WMM + Wide Message Marker +Enables the use of 16-bit Wide Message Markers. When 16-bit Wide Message Markers are used (WMM = ‘1’), 16-bit internal timestamping is disabled for the Tx Event FIFO. +0= 8-bit Message Marker used +1= 16-bit Message Marker used, replacing 16-bit timestamps in Tx Event FIFO + 11 + 1 + read-write + + + UTSU + Use Timestamping Unit +When UTSU is set, 16-bit Wide Message Markers are also enabled regardless of the value of WMM. +0= Internal time stamping +1= External time stamping by TSU +Note: When generic parameter connected_tsu_g = ‘0’, there is no TSU connected to the M_CAN. +In this case bit UTSU is fixed to zero by synthesis. + 10 + 1 + read-write + + + BRSE + Bit Rate Switch Enable +0= Bit rate switching for transmissions disabled +1= Bit rate switching for transmissions enabled +Note: When CAN FD operation is disabled FDOE = ‘0’, BRSE is not evaluated. + 9 + 1 + read-write + + + FDOE + FD Operation Enable +0= FD operation disabled +1= FD operation enabled + 8 + 1 + read-write + + + TEST + Test Mode Enable +0= Normal operation, register TEST holds reset values +1= Test Mode, write access to register TEST enabled + 7 + 1 + read-write + + + DAR + Disable Automatic Retransmission +0= Automatic retransmission of messages not transmitted successfully enabled +1= Automatic retransmission disabled + 6 + 1 + read-write + + + MON + Bus Monitoring Mode +Bit MON can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. +0= Bus Monitoring Mode is disabled +1= Bus Monitoring Mode is enabled + 5 + 1 + read-write + + + CSR + Clock Stop Request +0= No clock stop is requested +1= Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle. + 4 + 1 + read-write + + + CSA + Clock Stop Acknowledge +0= No clock stop acknowledged +1= M_CAN may be set in power down by stopping m_can_hclk and m_can_cclk + 3 + 1 + read-only + + + ASM + Restricted Operation Mode +Bit ASM can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. For a description of the Restricted Operation Mode see Section 3.1.5. +0= Normal CAN operation +1= Restricted Operation Mode active + 2 + 1 + read-write + + + CCE + Configuration Change Enable +0= The CPU has no write access to the protected configuration registers +1= The CPU has write access to the protected configuration registers (while CCCR.INIT = ‘1’) + 1 + 1 + read-write + + + INIT + Initialization +0= Normal Operation +1= Initialization is started + 0 + 1 + read-write + + + + + NBTP + nominal bit timing and prescaler register + 0x1c + 32 + 0x06000A03 + 0xFFFFFF7F + + + NSJW + Nominal (Re)Synchronization Jump Width +Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + 25 + 7 + read-write + + + NBRP + Nominal Bit Rate Prescaler +The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is +such that one more than the value programmed here is used. + 16 + 9 + read-write + + + NTSEG1 + Nominal Time segment before sample point +Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. + 8 + 8 + read-write + + + NTSEG2 + Nominal Time segment after sample point +Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. + 0 + 7 + read-write + + + + + TSCC + timestamp counter configuration + 0x20 + 32 + 0x00000000 + 0x000F0003 + + + TCP + Timestamp Counter Prescaler +Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1…16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + 16 + 4 + read-write + + + TSS + timestamp Select +00= Timestamp counter value always 0x0000 +01= Timestamp counter value incremented according to TCP +10= External timestamp counter value used +11= Same as “00” + 0 + 2 + read-write + + + + + TSCV + timestamp counter value + 0x24 + 32 + 0x00000000 + 0x0000FFFF + + + TSC + Timestamp Counter +The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx).When TSCC.TSS = “01”, the Timestamp Counter is incremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. +A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = “10”, TSC reflects the external Timestamp Counter value. A write access has no impact. + 0 + 16 + read-only + + + + + TOCC + timeout counter configuration + 0x28 + 32 + 0xFFFF0000 + 0xFFFF0007 + + + TOP + Timeout Period +Start value of the Timeout Counter (down-counter). Configures the Timeout Period. + 16 + 16 + read-write + + + TOS + Timeout Select +When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. +When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. +00= Continuous operation +01= Timeout controlled by Tx Event FIFO +10= Timeout controlled by Rx FIFO 0 +11= Timeout controlled by Rx FIFO 1 + 1 + 2 + read-write + + + RP + Enable Timeout Counter +0= Timeout Counter disabled +1= Timeout Counter enabled + 0 + 1 + read-write + + + + + TOCV + timeout counter value + 0x2c + 32 + 0x0000FFFF + 0x0000FFFF + + + TOC + Timeout Counter +The Timeout Counter is decremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. +When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. +Note: Byte access: when TOCC.TOS = “00，writing one of the register bytes 3/2/1/0 will preset the Timeout Counter. + 0 + 16 + read-only + + + + + ECR + error counter register + 0x40 + 32 + 0x00000000 + 0x00FFFFFF + + + CEL + CAN Error Logging +The counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. +The counter is also incremented when the Bus_Off limit is reached. It is not incremented when only RP is set without changing REC. The increment of CEL follows after the increment of REC or TEC. +The counter is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. +Note: Byte access: Reading byte 2 will reset CEL to zero, reading bytes 3/1/0 has no impact. + 16 + 8 + read-only + + + RP + Receive Error Passive +0= The Receive Error Counter is below the error passive level of 128 +1= The Receive Error Counter has reached the error passive level of 128 + 15 + 1 + read-only + + + REC + Receive Error Counter +Actual state of the Receive Error Counter, values between 0 and 127 + 8 + 7 + read-only + + + TEC + Transmit Error Counter +Actual state of the Transmit Error Counter, values between 0 and 255 +Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented. + 0 + 8 + read-only + + + + + PSR + protocol status register + 0x44 + 32 + 0x00000707 + 0x007F7FFF + + + TDCV + Transmitter Delay Compensation Value +Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. +The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. + 16 + 7 + read-only + + + PXE + Protocol Exception Event +0= No protocol exception event occurred since last read access +1= Protocol exception event occurred +Note: Byte access: Reading byte 0 will reset PXE, reading bytes 3/2/1 has no impact. + 14 + 1 + read-only + + + RFDF + Received a CAN FD Message +This bit is set independent of acceptance filtering. +0= Since this bit was reset by the CPU, no CAN FD message has been received +1= Message in CAN FD format with FDF flag set has been received +Note: Byte access: Reading byte 0 will reset RFDF, reading bytes 3/2/1 has no impact. + 13 + 1 + read-only + + + RBRS + BRS flag of last received CAN FD Message +This bit is set together with RFDF, independent of acceptance filtering. +0= Last received CAN FD message did not have its BRS flag set +1= Last received CAN FD message had its BRS flag set +Note: Byte access: Reading byte 0 will reset RBRS, reading bytes 3/2/1 has no impact. + 12 + 1 + read-only + + + RESI + ESI flag of last received CAN FD Message +This bit is set together with RFDF, independent of acceptance filtering. +0= Last received CAN FD message did not have its ESI flag set +1= Last received CAN FD message had its ESI flag set +Note: Byte access: Reading byte 0 will reset RESI, reading bytes 3/2/1 has no impact. + 11 + 1 + read-only + + + DLEC + Data Phase Last Error Code +Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set.Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with +its BRS flag set has been transferred (reception or transmission) without error. +Note: Byte access: Reading byte 0 will set DLEC to “111”, reading bytes 3/2/1 has no impact. + 8 + 3 + read-only + + + BO + Bus_Off Status +0= The M_CAN is not Bus_Off +1= The M_CAN is in Bus_Off state + 7 + 1 + read-only + + + EW + Warning Status +0= Both error counters are below the Error_Warning limit of 96 +1= At least one of error counter has reached the Error_Warning limit of 96 + 6 + 1 + read-only + + + EP + Error Passive +0= The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected +1= The M_CAN is in the Error_Passive state + 5 + 1 + read-only + + + ACT + Activity +Monitors the module’s CAN communication state. +00= Synchronizing - node is synchronizing on CAN communication +01= Idle - node is neither receiver nor transmitter +10= Receiver - node is operating as receiver +11= Transmitter - node is operating as transmitter +Note: ACT is set to “00” by a Protocol Exception Event. + 3 + 2 + read-only + + + LEC + Last Error Code +The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to ‘0’when a message has been transferred (reception or transmission) without error. +0= No Error: No error occurred since LEC has been reset by successful reception or transmission. +1= Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. +2= Form Error: A fixed format part of a received frame has the wrong format. +3= AckError: The message transmitted by the M_CAN was not acknowledged by another node. +4= Bit1Error: During the transmission of a message (with the exception of the arbitration field), +the device wanted to send a recessive level (bit of logical value ‘1’), but the monitored bus +value was dominant. +5= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value‘0’), but the monitored bus value was recessive. + During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at +dominant or continuously disturbed). +6= CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. +7= NoChange: Any read access to the Protocol Status Register re-initializes the LEC to ‘7’. When the LEC shows the value ‘7’, no CAN bus event was detected since the last CPU read access to the Protocol Status Register. +Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error. +Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord,stopping all bus activities. + Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. +At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, +enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences. +Note: Byte access: Reading byte 0 will set LEC to “111”, reading bytes 3/2/1 has no impact. + 0 + 3 + read-only + + + + + TDCR + transmitter delay compensation + 0x48 + 32 + 0x00000000 + 0x00007F7F + + + TDCO + Transmitter Delay Compensation SSP Offset +Offset value defining the distance between the measured delay from m_can_tx to m_can_rx and the secondary sample point. Valid values are 0 to 127 mtq. + 8 + 7 + read-write + + + TDCF + Transmitter Delay Compensation Filter Window Length +Defines the minimum value for the SSP position, dominant edges on m_can_rx that would result in an earlier SSP position are ignored for transmitter delay measurement. +The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq. + 0 + 7 + read-write + + + + + IR + interrupt register + 0x50 + 32 + 0x00000000 + 0x3FFFFFFF + + + ARA + Access to Reserved Address +0= No access to reserved address occurred +1= Access to reserved address occurred + 29 + 1 + read-write + + + PED + Protocol Error in Data Phase (Data Bit Time is used) +0= No protocol error in data phase +1= Protocol error in data phase detected (PSR.DLEC ≠ 0,7) + 28 + 1 + read-write + + + PEA + Protocol Error in Arbitration Phase (Nominal Bit Time is used) +0= No protocol error in arbitration phase +1= Protocol error in arbitration phase detected (PSR.LEC ≠ 0,7) + 27 + 1 + read-write + + + WDI + Watchdog Interrupt +0= No Message RAM Watchdog event occurred +1= Message RAM Watchdog event due to missing READY + 26 + 1 + read-write + + + BO + Bus_Off Status +0= Bus_Off status unchanged +1= Bus_Off status changed + 25 + 1 + read-write + + + EW + Warning Status +0= Error_Warning status unchanged +1= Error_Warning status changed + 24 + 1 + read-write + + + EP + Error Passive +0= Error_Passive status unchanged +1= Error_Passive status changed + 23 + 1 + read-write + + + ELO + Error Logging Overflow +0= CAN Error Logging Counter did not overflow +1= Overflow of CAN Error Logging Counter occurred + 22 + 1 + read-write + + + BEU + Bit Error Uncorrected +Message RAM bit error detected, uncorrected. Controlled by input signal m_can_aeim_berr[1] generated by an optional external parity / ECC logic attached to the Message RAM. +An uncorrected Message RAM bit error sets CCCR.INIT to ‘1’. This is done to avoid transmission of corrupted data. +0= No bit error detected when reading from Message RAM +1= Bit error detected, uncorrected (e.g. parity logic) + 21 + 1 + read-write + + + BEC + Bit Error Corrected +Message RAM bit error detected and corrected. Controlled by input signal m_can_aeim_berr[0] generated by an optional external parity / ECC logic attached to the Message RAM. +0= No bit error detected when reading from Message RAM +1= Bit error detected and corrected (e.g. ECC) + 20 + 1 + read-write + + + DRX + Message stored to Dedicated Rx Buffer +The flag is set whenever a received message has been stored into a dedicated Rx Buffer. +0= No Rx Buffer updated +1= At least one received message stored into an Rx Buffer + 19 + 1 + read-write + + + TOO + Timeout Occurred +0= No timeout +1= Timeout reached + 18 + 1 + read-write + + + MRAF + Message RAM Access Failure +The flag is set, when the Rx Handler +.has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message +storage is aborted and the Rx Handler starts processing of the following message. +.was not able to write a message to the Message RAM. In this case message storage is aborted. +In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. +The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the +M_CAN is switched into Restricted Operation Mode (see Section 3.1.5). To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM. +0= No Message RAM access failure occurred +1= Message RAM access failure occurred + 17 + 1 + read-write + + + TSW + Timestamp Wraparound +0= No timestamp counter wrap-around +1= Timestamp counter wrapped around + 16 + 1 + read-write + + + TEFL + Tx Event FIFO Element Lost +0= No Tx Event FIFO element lost +1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero + 15 + 1 + read-write + + + TEFF + Tx Event FIFO Full +0= Tx Event FIFO not full +1= Tx Event FIFO full + 14 + 1 + read-write + + + TEFW + Tx Event FIFO Watermark Reached +0= Tx Event FIFO fill level below watermark +1= Tx Event FIFO fill level reached watermark + 13 + 1 + read-write + + + TEFN + Tx Event FIFO New Entry +0= Tx Event FIFO unchanged +1= Tx Handler wrote Tx Event FIFO element + 12 + 1 + read-write + + + TFE + Tx FIFO Empty +0= Tx FIFO non-empty +1= Tx FIFO empty + 11 + 1 + read-write + + + TCF + Transmission Cancellation Finished +0= No transmission cancellation finished +1= Transmission cancellation finished + 10 + 1 + read-write + + + TC + Transmission Completed +0= No transmission completed +1= Transmission completed + 9 + 1 + read-write + + + HPM + High Priority Message +0= No high priority message received +1= High priority message received + 8 + 1 + read-write + + + RF1L + Rx FIFO 1 Message Lost +0= No Rx FIFO 1 message lost +1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero + 7 + 1 + read-write + + + RF1F + Rx FIFO 1 Full +0= Rx FIFO 1 not full +1= Rx FIFO 1 full + 6 + 1 + read-write + + + RF1W + Rx FIFO 1 Watermark Reached +0= Rx FIFO 1 fill level below watermark +1= Rx FIFO 1 fill level reached watermark + 5 + 1 + read-write + + + RF1N + Rx FIFO 1 New Message +0= No new message written to Rx FIFO 1 +1= New message written to Rx FIFO 1 + 4 + 1 + read-write + + + RF0L + Rx FIFO 0 Message Lost +0= No Rx FIFO 0 message lost +1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero + 3 + 1 + read-write + + + RF0F + Rx FIFO 0 Full +0= Rx FIFO 0 not full +1= Rx FIFO 0 full + 2 + 1 + read-write + + + RF0W + Rx FIFO 0 Watermark Reached +0= Rx FIFO 0 fill level below watermark +1= Rx FIFO 0 fill level reached watermark + 1 + 1 + read-write + + + RF0N + Rx FIFO 0 New Message +0= No new message written to Rx FIFO 0 +1= New message written to Rx FIFO 0 + 0 + 1 + read-write + + + + + IE + interrupt enable + 0x54 + 32 + 0x00000000 + 0x3FFFFFFF + + + ARAE + Access to Reserved Address Enable + 29 + 1 + read-write + + + PEDE + Protocol Error in Data Phase Enable + 28 + 1 + read-write + + + PEAE + Protocol Error in Arbitration Phase Enable + 27 + 1 + read-write + + + WDIE + Watchdog Interrupt Enable + 26 + 1 + read-write + + + BOE + Bus_Off Status Interrupt Enable + 25 + 1 + read-write + + + EWE + Warning Status Interrupt Enable + 24 + 1 + read-write + + + EPE + Error Passive Interrupt Enable + 23 + 1 + read-write + + + ELOE + Error Logging Overflow Interrupt Enable + 22 + 1 + read-write + + + BEUE + Bit Error Uncorrected Interrupt Enable + 21 + 1 + read-write + + + BECE + Bit Error Corrected Interrupt Enable + 20 + 1 + read-write + + + DRXE + Message stored to Dedicated Rx Buffer Interrupt Enable + 19 + 1 + read-write + + + TOOE + Timeout Occurred Interrupt Enable + 18 + 1 + read-write + + + MRAFE + Message RAM Access Failure Interrupt Enable + 17 + 1 + read-write + + + TSWE + Timestamp Wraparound Interrupt Enable + 16 + 1 + read-write + + + TEFLE + Tx Event FIFO Event Lost Interrupt Enable + 15 + 1 + read-write + + + TEFFE + Tx Event FIFO Full Interrupt Enable + 14 + 1 + read-write + + + TEFWE + Tx Event FIFO Watermark Reached Interrupt Enable + 13 + 1 + read-write + + + TEFNE + Tx Event FIFO New Entry Interrupt Enable + 12 + 1 + read-write + + + TFEE + Tx FIFO Empty Interrupt Enable + 11 + 1 + read-write + + + TCFE + Transmission Cancellation Finished Interrupt Enable + 10 + 1 + read-write + + + TCE + Transmission Completed Interrupt Enable + 9 + 1 + read-write + + + HPME + High Priority Message Interrupt Enable + 8 + 1 + read-write + + + RF1LE + Rx FIFO 1 Message Lost Interrupt Enable + 7 + 1 + read-write + + + RF1FE + Rx FIFO 1 Full Interrupt Enable + 6 + 1 + read-write + + + RF1WE + Rx FIFO 1 Watermark Reached Interrupt Enable + 5 + 1 + read-write + + + RF1NE + Rx FIFO 1 New Message Interrupt Enable + 4 + 1 + read-write + + + RF0LE + Rx FIFO 0 Message Lost Interrupt Enable + 3 + 1 + read-write + + + RF0FE + Rx FIFO 0 Full Interrupt Enable + 2 + 1 + read-write + + + RF0WE + Rx FIFO 0 Watermark Reached Interrupt Enable + 1 + 1 + read-write + + + RF0NE + Rx FIFO 0 New Message Interrupt Enable + 0 + 1 + read-write + + + + + ILS + interrupt line select + 0x58 + 32 + 0x00000000 + 0x3FFFFFFF + + + ARAL + Access to Reserved Address Line + 29 + 1 + read-write + + + PEDL + Protocol Error in Data Phase Line + 28 + 1 + read-write + + + PEAL + Protocol Error in Arbitration Phase Line + 27 + 1 + read-write + + + WDIL + Watchdog Interrupt Line + 26 + 1 + read-write + + + BOL + Bus_Off Status Interrupt Line + 25 + 1 + read-write + + + EWL + Warning Status Interrupt Line + 24 + 1 + read-write + + + EPL + Error Passive Interrupt Line + 23 + 1 + read-write + + + ELOL + Error Logging Overflow Interrupt Line + 22 + 1 + read-write + + + BEUL + Bit Error Uncorrected Interrupt Line + 21 + 1 + read-write + + + BECL + Bit Error Corrected Interrupt Line + 20 + 1 + read-write + + + DRXL + Message stored to Dedicated Rx Buffer Interrupt Line + 19 + 1 + read-write + + + TOOL + Timeout Occurred Interrupt Line + 18 + 1 + read-write + + + MRAFL + Message RAM Access Failure Interrupt Line + 17 + 1 + read-write + + + TSWL + Timestamp Wraparound Interrupt Line + 16 + 1 + read-write + + + TEFLL + Tx Event FIFO Event Lost Interrupt Line + 15 + 1 + read-write + + + TEFFL + Tx Event FIFO Full Interrupt Line + 14 + 1 + read-write + + + TEFWL + Tx Event FIFO Watermark Reached Interrupt Line + 13 + 1 + read-write + + + TEFNL + Tx Event FIFO New Entry Interrupt Line + 12 + 1 + read-write + + + TFEL + Tx FIFO Empty Interrupt Line + 11 + 1 + read-write + + + TCFL + Transmission Cancellation Finished Interrupt Line + 10 + 1 + read-write + + + TCL + Transmission Completed Interrupt Line + 9 + 1 + read-write + + + HPML + High Priority Message Interrupt Line + 8 + 1 + read-write + + + RF1LL + Rx FIFO 1 Message Lost Interrupt Line + 7 + 1 + read-write + + + RF1FL + Rx FIFO 1 Full Interrupt Line + 6 + 1 + read-write + + + RF1WL + Rx FIFO 1 Watermark Reached Interrupt Line + 5 + 1 + read-write + + + RF1NL + Rx FIFO 1 New Message Interrupt Line + 4 + 1 + read-write + + + RF0LL + Rx FIFO 0 Message Lost Interrupt Line + 3 + 1 + read-write + + + RF0FL + Rx FIFO 0 Full Interrupt Line + 2 + 1 + read-write + + + RF0WL + Rx FIFO 0 Watermark Reached Interrupt Line + 1 + 1 + read-write + + + RF0NL + Rx FIFO 0 New Message Interrupt Line + 0 + 1 + read-write + + + + + ILE + interrupt line enable + 0x5c + 32 + 0x00000000 + 0x00000003 + + + EINT1 + Enable Interrupt Line 1 +0= Interrupt line m_can_int1 disabled +1= Interrupt line m_can_int1 enabled + 1 + 1 + read-write + + + EINT0 + Enable Interrupt Line 0 +0= Interrupt line m_can_int0 disabled +1= Interrupt line m_can_int0 enabled + 0 + 1 + read-write + + + + + GFC + global filter configuration + 0x80 + 32 + 0x00000000 + 0x0000003F + + + ANFS + Accept Non-matching Frames Standard +Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. +00= Accept in Rx FIFO 0 +01= Accept in Rx FIFO 1 +10= Reject +11= Reject + 4 + 2 + read-write + + + ANFE + Accept Non-matching Frames Extended +Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. +00= Accept in Rx FIFO 0 +01= Accept in Rx FIFO 1 +10= Reject +11= Reject + 2 + 2 + read-write + + + RRFS + Reject Remote Frames Standard +0= Filter remote frames with 11-bit standard IDs +1= Reject all remote frames with 11-bit standard IDs + 1 + 1 + read-write + + + RRFE + Reject Remote Frames Extended +0= Filter remote frames with 29-bit extended IDs +1= Reject all remote frames with 29-bit extended IDs + 0 + 1 + read-write + + + + + SIDFC + standard ID filter configuration + 0x84 + 32 + 0x00000000 + 0x00FFFFFC + + + LSS + List Size Standard +0= No standard Message ID filter +1-128= Number of standard Message ID filter elements +>128= Values greater than 128 are interpreted as 128 + 16 + 8 + read-write + + + FLSSA + Filter List Standard Start Address +Start address of standard Message ID filter list (32-bit word address) + 2 + 14 + read-write + + + + + XIDFC + extended ID filter configuration + 0x88 + 32 + 0x00000000 + 0x007FFFFC + + + LSE + List Size Extended +0= No extended Message ID filter +1-64= Number of extended Message ID filter elements +>64= Values greater than 64 are interpreted as 64 + 16 + 7 + read-write + + + FLESA + Filter List Extended Start Address +Start address of extended Message ID filter list (32-bit word address). + 2 + 14 + read-write + + + + + XIDAM + extended id and mask + 0x90 + 32 + 0x1FFFFFFF + 0x1FFFFFFF + + + EIDM + Extended ID Mask +For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. + Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active. + 0 + 29 + read-write + + + + + HPMS + high priority message status + 0x94 + 32 + 0x00000000 + 0x0000FFFF + + + FLST + Filter List +Indicates the filter list of the matching filter element. +0= Standard Filter List +1= Extended Filter List + 15 + 1 + read-only + + + FIDX + Filter Index +Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1. + 8 + 7 + read-only + + + MSI + Message Storage Indicator +00= No FIFO selected +01= FIFO message lost +10= Message stored in FIFO 0 +11= Message stored in FIFO 1 + 6 + 2 + read-only + + + BIDX + Buffer Index +Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = ‘1’. + 0 + 6 + read-only + + + + + NDAT1 + new data1 + 0x98 + 32 + 0x00000000 + 0xFFFFFFFF + + + ND1 + New Data[31:0] +The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. +The flags remain set until the Host clears them.A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. +0= Rx Buffer not updated +1= Rx Buffer updated from new message + 0 + 32 + read-write + + + + + NDAT2 + new data2 + 0x9c + 32 + 0x00000000 + 0xFFFFFFFF + + + ND2 + New Data[63:32] +The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. +The flags remain set until the Host clears them. A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. +0= Rx Buffer not updated +1= Rx Buffer updated from new message + 0 + 32 + read-write + + + + + RXF0C + rx fifo 0 configuration + 0xa0 + 32 + 0x00000000 + 0xFF7FFFFC + + + F0OM + FIFO 0 Operation Mode +FIFO 0 can be operated in blocking or in overwrite mode (see Section 3.4.2). +0= FIFO 0 blocking mode +1= FIFO 0 overwrite mode + 31 + 1 + read-write + + + F0WM + Rx FIFO 0 Watermark +0= Watermark interrupt disabled +1-64= Level for Rx FIFO 0 watermark interrupt (IR.RF0W) +>64= Watermark interrupt disabled + 24 + 7 + read-write + + + F0S + Rx FIFO 0 Size +0= No Rx FIFO 0 +1-64= Number of Rx FIFO 0 elements +>64= Values greater than 64 are interpreted as 64 +The Rx FIFO 0 elements are indexed from 0 to F0S-1 + 16 + 7 + read-write + + + F0SA + Rx FIFO 0 Start Address +Start address of Rx FIFO 0 in Message RAM (32-bit word address) + 2 + 14 + read-write + + + + + RXF0S + rx fifo 0 status + 0xa4 + 32 + 0x00000000 + 0x033F3F7F + + + RF0L + Rx FIFO 0 Message Lost +This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset. +0= No Rx FIFO 0 message lost +1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero +Note: Overwriting the oldest message when RXF0C.F0OM = ‘1’ will not set this flag. + 25 + 1 + read-only + + + F0F + Rx FIFO 0 Full +0= Rx FIFO 0 not full +1= Rx FIFO 0 full + 24 + 1 + read-only + + + F0PI + Rx FIFO 0 Put Index +Rx FIFO 0 write index pointer, range 0 to 63. + 16 + 6 + read-only + + + F0GI + Rx FIFO 0 Get Index +Rx FIFO 0 read index pointer, range 0 to 63. + 8 + 6 + read-only + + + F0FL + Rx FIFO 0 Fill Level +Number of elements stored in Rx FIFO 0, range 0 to 64. + 0 + 7 + read-only + + + + + RXF0A + rx fifo0 acknowledge + 0xa8 + 32 + 0x00000000 + 0x0000003F + + + F0AI + Rx FIFO 0 Acknowledge Index +After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. +This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. + 0 + 6 + read-write + + + + + RXBC + rx buffer configuration + 0xac + 32 + 0x00000000 + 0x0000FFFC + + + RBSA + Rx Buffer Start Address +Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address).Also used to reference debug messages A,B,C. + 2 + 14 + read-write + + + + + RXF1C + rx fifo1 configuration + 0xb0 + 32 + 0x00000000 + 0xFF7FFFFC + + + F1OM + FIFO 1 Operation Mode +FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2). +0= FIFO 1 blocking mode +1= FIFO 1 overwrite mode + 31 + 1 + read-write + + + F1WM + Rx FIFO 1 Watermark +0= Watermark interrupt disabled +1-64= Level for Rx FIFO 1 watermark interrupt (IR.RF1W) +>64= Watermark interrupt disabled + 24 + 7 + read-write + + + F1S + Rx FIFO 1 Size +0= No Rx FIFO 1 +1-64= Number of Rx FIFO 1 elements +>64= Values greater than 64 are interpreted as 64 +The Rx FIFO 1 elements are indexed from 0 to F1S - 1 + 16 + 7 + read-write + + + F1SA + Rx FIFO 1 Start Address +Start address of Rx FIFO 1 in Message RAM (32-bit word address) + 2 + 14 + read-write + + + + + RXF1S + rx fifo1 status + 0xb4 + 32 + 0x00000000 + 0xC33F3F7F + + + DMS + Debug Message Status +00= Idle state, wait for reception of debug messages, DMA request is cleared +01= Debug message A received +10= Debug messages A, B received +11= Debug messages A, B, C received, DMA request is set + 30 + 2 + read-only + + + RF1L + Rx FIFO 1 Message Lost +This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset. +0= No Rx FIFO 1 message lost +1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero +Note: Overwriting the oldest message when RXF1C.F1OM = ‘1’ will not set this flag. + 25 + 1 + read-only + + + F1F + Rx FIFO 1 Full +0= Rx FIFO 1 not full +1= Rx FIFO 1 full + 24 + 1 + read-only + + + F1PI + Rx FIFO 1 Put Index +Rx FIFO 1 write index pointer, range 0 to 63. + 16 + 6 + read-only + + + F1GI + Rx FIFO 1 Get Index +Rx FIFO 1 read index pointer, range 0 to 63. + 8 + 6 + read-only + + + F1FL + Rx FIFO 1 Fill Level +Number of elements stored in Rx FIFO 1, range 0 to 64. + 0 + 7 + read-only + + + + + RXF1A + rx fifo 1 acknowledge + 0xb8 + 32 + 0x00000000 + 0x0000003F + + + F1AI + Rx FIFO 1 Acknowledge Index +After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. +This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. + 0 + 6 + read-write + + + + + RXESC + rx buffer/fifo element size configuration + 0xbc + 32 + 0x00000000 + 0x00000777 + + + RBDS + Rx Buffer Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field + 8 + 3 + read-write + + + F1DS + Rx FIFO 1 Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field + 4 + 3 + read-write + + + F0DS + Rx FIFO 0 Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field +Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, +only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame’s data field is ignored. + 0 + 3 + read-write + + + + + TXBC + tx buffer configuration + 0xc0 + 32 + 0x00000000 + 0x7F3FFFFC + + + TFQM + Tx FIFO/Queue Mode +0= Tx FIFO operation +1= Tx Queue operation + 30 + 1 + read-write + + + TFQS + Transmit FIFO/Queue Size +0= No Tx FIFO/Queue +1-32= Number of Tx Buffers used for Tx FIFO/Queue +>32= Values greater than 32 are interpreted as 32 + 24 + 6 + read-write + + + NDTB + Number of Dedicated Transmit Buffers +0= No Dedicated Tx Buffers +1-32= Number of Dedicated Tx Buffers +>32= Values greater than 32 are interpreted as 32 + 16 + 6 + read-write + + + TBSA + Tx Buffers Start Address +Start address of Tx Buffers section in Message RAM (32-bit word address, see Figure 2). +Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers. + 2 + 14 + read-write + + + + + TXFQS + tx fifo/queue status + 0xc4 + 32 + 0x00000000 + 0x003F1F3F + + + TFQF + Tx FIFO/Queue Full +0= Tx FIFO/Queue not full +1= Tx FIFO/Queue full + 21 + 1 + read-only + + + TFQPI + Tx FIFO/Queue Put Index +Tx FIFO/Queue write index pointer, range 0 to 31. + 16 + 5 + read-only + + + TFGI + Tx FIFO Get Index +Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured +(TXBC.TFQM = ‘1’). + 8 + 5 + read-only + + + TFFL + Tx FIFO Free Level +Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = ‘1’) +Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with +the first dedicated Tx Buffers. +Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO. + 0 + 6 + read-only + + + + + TXESC + tx buffer element size configuration + 0xc8 + 32 + 0x00000000 + 0x00000007 + + + TBDS + Tx Buffer Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field +Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TXESC.TBDS, the bytes not defined by the Tx Buffer are transmitted as “0xCC” (padding bytes). + 0 + 3 + read-write + + + + + TXBRP + tx buffer request pending + 0xcc + 32 + 0x00000000 + 0xFFFFFFFF + + + TRP + Transmission Request Pending +Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR.The bits are reset after a requested transmission has completed or has been cancelled via register +TXBCR. +TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan (see Section 3.5, Tx Handling) is started to check for the pending Tx request with the +highest priority (Tx Buffer with lowest Message ID). +A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, +this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. +After a cancellation has been requested, a finished cancellation is signalled via TXBCF +? after successful transmission together with the corresponding TXBTO bit +? when the transmission has not yet been started at the point of cancellation +? when the transmission has been aborted due to lost arbitration +? when an error occurred during frame transmission +In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. +0= No transmission request pending +1= Transmission request pending +Note: TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding TXBRP bit is reset. + 0 + 32 + read-only + + + + + TXBAR + tx buffer add request + 0xd0 + 32 + 0x00000000 + 0xFFFFFFFF + + + AR + Add Request +Each Tx Buffer has its own Add Request bit. Writing a ‘1’ will set the corresponding Add Request bit; writing a ‘0’ has no impact. This enables the Host to set transmission requests for multiple Tx +Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. +When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. +0= No transmission request added +1= Transmission requested added +Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding TXBRP bit already set), this add request is ignored. + 0 + 32 + read-write + + + + + TXBCR + tx buffer cancellation request + 0xd4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CR + Cancellation Request +Each Tx Buffer has its own Cancellation Request bit. Writing a ‘1’ will set the corresponding Cancellation Request bit; writing a ‘0’ has no impact. +This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. +0= No cancellation pending +1= Cancellation pending + 0 + 32 + read-write + + + + + TXBTO + tx buffer transmission occurred + 0xd8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TO + Transmission Occurred +Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. +0= No transmission occurred +1= Transmission occurred + 0 + 32 + read-only + + + + + TXBCF + tx buffer cancellation finished + 0xdc + 32 + 0x00000000 + 0xFFFFFFFF + + + CF + Cancellation Finished +Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. +In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. +0= No transmit buffer cancellation +1= Transmit buffer cancellation finished + 0 + 32 + read-only + + + + + TXBTIE + tx buffer transmission interrupt enable + 0xe0 + 32 + 0x00000000 + 0xFFFFFFFF + + + TIE + Transmission Interrupt Enable +Each Tx Buffer has its own Transmission Interrupt Enable bit. +0= Transmission interrupt disabled +1= Transmission interrupt enable + 0 + 32 + read-write + + + + + TXBCIE + tx buffer cancellation finished interrupt enable + 0xe4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CFIE + Cancellation Finished Interrupt Enable +Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. +0= Cancellation finished interrupt disabled +1= Cancellation finished interrupt enabled + 0 + 32 + read-write + + + + + TXEFC + tx event fifo configuration + 0xf0 + 32 + 0x00000000 + 0x3F3FFFFC + + + EFWM + Event FIFO Watermark +0= Watermark interrupt disabled +1-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW) +>32= Watermark interrupt disabled + 24 + 6 + read-write + + + EFS + Event FIFO Size +0= Tx Event FIFO disabled +1-32= Number of Tx Event FIFO elements +>32= Values greater than 32 are interpreted as 32 +The Tx Event FIFO elements are indexed from 0 to EFS - 1 + 16 + 6 + read-write + + + EFSA + Event FIFO Start Address +Start address of Tx Event FIFO in Message RAM (32-bit word address) + 2 + 14 + read-write + + + + + TXEFS + tx event fifo status + 0xf4 + 32 + 0x00000000 + 0x031F1F3F + + + TEFL + Tx Event FIFO Element Lost +This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset. +0= No Tx Event FIFO element lost +1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. + 25 + 1 + read-only + + + EFF + Event FIFO Full +0= Tx Event FIFO not full +1= Tx Event FIFO full + 24 + 1 + read-only + + + EFPI + Event FIFO Put Index +Tx Event FIFO write index pointer, range 0 to 31. + 16 + 5 + read-only + + + EFGI + Event FIFO Get Index +Tx Event FIFO read index pointer, range 0 to 31. + 8 + 5 + read-only + + + EFFL + Event FIFO Fill Level +Number of elements stored in Tx Event FIFO, range 0 to 32. + 0 + 6 + read-only + + + + + TXEFA + tx event fifo acknowledge + 0xf8 + 32 + 0x00000000 + 0x0000001F + + + EFAI + Event FIFO Acknowledge Index +After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get +Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL. + 0 + 5 + read-write + + + + + 16 + 0x4 + TS_SEL0,TS_SEL1,TS_SEL2,TS_SEL3,TS_SEL4,TS_SEL5,TS_SEL6,TS_SEL7,TS_SEL8,TS_SEL9,TS_SEL10,TS_SEL11,TS_SEL12,TS_SEL13,TS_SEL14,TS_SEL15 + TS_SEL[%s] + no description available + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + TS + Timestamp Word TS +default can save 16 timestamps with 32bit; +if ts64_en is set, then work at 64bit mode, can save 8 timestamps with 01/23/45…. + 0 + 32 + read-only + + + + + CREL + core release register + 0x240 + 32 + 0x00000000 + 0xFFFFFFFF + + + REL + Core Release +One digit, BCD-coded + 28 + 4 + read-only + + + STEP + Step of Core Release +One digit, BCD-coded. + 24 + 4 + read-only + + + SUBSTEP + Sub-step of Core Release +One digit, BCD-coded + 20 + 4 + read-only + + + YEAR + Timestamp Year +One digit, BCD-coded. This field is set by generic parameter on +synthesis. + 16 + 4 + read-only + + + MON + Timestamp Month +Two digits, BCD-coded. This field is set by generic parameter +on synthesis. + 8 + 8 + read-only + + + DAY + Timestamp Day +Two digits, BCD-coded. This field is set by generic parameter +on synthesis. + 0 + 8 + read-only + + + + + TSCFG + timestamp configuration + 0x244 + 32 + 0x00000000 + 0x0000FF0F + + + TBPRE + Timebase Prescaler +0x00 to 0xFF +The value by which the oscillator frequency is divided for +generating the timebase counter clock. Valid values for the +Timebase Prescaler are 0 to 255. The actual interpretation by +the hardware of this value is such that one more than the value +programmed here is used. Affects only the TSU internal +timebase. When the internal timebase is excluded by synthesis, +TBPRE[7:0] is fixed to 0x00, the Timestamp Prescaler is not +used. + 8 + 8 + read-write + + + EN64 + set to use 64bit timestamp. +when enabled, tsu can save up to 8 different timestamps, TS(k) and TS(k+1) are used for one 64bit timestamp, k is 0~7. +TSP can be used to select different one + 3 + 1 + read-write + + + SCP + Select Capturing Position +0: Capture Timestamp at EOF +1: Capture Timestamp at SOF + 2 + 1 + read-write + + + TBCS + Timebase Counter Select +When the internal timebase is excluded by synthesis, TBCS is +fixed to ‘1’. +0: Timestamp value captured from internal timebase counter, + ATB.TB[31:0] is the internal timbase counter +1: Timestamp value captured from input tsu_tbin[31:0],ATB.TB[31:0] is tsu_tbin[31:0] + 1 + 1 + read-write + + + TSUE + Timestamp Unit Enable +0: TSU disabled +1: TSU enabled + 0 + 1 + read-write + + + + + TSS1 + timestamp status1 + 0x248 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSL + Timestamp Lost +Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when the timestamp stored in the related Timestamp register was overwritten before it was read. +Reading a Timestamp register resets the related bit. + 16 + 16 + read-only + + + TSN + Timestamp New +Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when a timestamp was stored in the related +Timestamp register. Reading a Timestamp register resets the related bit. + 0 + 16 + read-only + + + + + TSS2 + timestamp status2 + 0x24c + 32 + 0x00000000 + 0x0000000F + + + TSP + Timestamp Pointer +The Timestamp Pointer is incremented by one each time a timestamp is captured. From its maximum value (3, 7, or 15 +depending on number_ts_g), it is incremented to 0. +Value also signalled on output m_can_tsp[3:0]. + 0 + 4 + read-only + + + + + ATB + actual timebase + 0x250 + 32 + 0x00000000 + 0xFFFFFFFF + + + TB + timebase for timestamp generation 31-0 + 0 + 32 + read-only + + + + + ATBH + actual timebase high + 0x254 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBH + timebase for timestamp generation 63-32 + 0 + 32 + read-only + + + + + GLB_CTL + global control + 0x400 + 32 + 0x00000000 + 0xE0000003 + + + M_CAN_STBY + m_can standby control + 31 + 1 + read-write + + + STBY_CLR_EN + m_can standby clear control +0:controlled by software by standby bit[bit31] +1:auto clear standby by hardware when rx data is 0 + 30 + 1 + read-write + + + STBY_POL + standby polarity selection + 29 + 1 + read-write + + + TSU_TBIN_SEL + external timestamp select. each CAN block has 4 timestamp input, this register is used to select one of them as timestame if TSCFG.TBCS is set to 1 + 0 + 2 + read-write + + + + + GLB_STATUS + global status + 0x404 + 32 + 0x00000000 + 0x0000000C + + + M_CAN_INT1 + m_can interrupt status1 + 3 + 1 + read-only + + + M_CAN_INT0 + m_can interrupt status0 + 2 + 1 + read-only + + + + + 640 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255,256,257,258,259,260,261,262,263,264,265,266,267,268,269,270,271,272,273,274,275,276,277,278,279,280,281,282,283,284,285,286,287,288,289,290,291,292,293,294,295,296,297,298,299,300,301,302,303,304,305,306,307,308,309,310,311,312,313,314,315,316,317,318,319,320,321,322,323,324,325,326,327,328,329,330,331,332,333,334,335,336,337,338,339,340,341,342,343,344,345,346,347,348,349,350,351,352,353,354,355,356,357,358,359,360,361,362,363,364,365,366,367,368,369,370,371,372,373,374,375,376,377,378,379,380,381,382,383,384,385,386,387,388,389,390,391,392,393,394,395,396,397,398,399,400,401,402,403,404,405,406,407,408,409,410,411,412,413,414,415,416,417,418,419,420,421,422,423,424,425,426,427,428,429,430,431,432,433,434,435,436,437,438,439,440,441,442,443,444,445,446,447,448,449,450,451,452,453,454,455,456,457,458,459,460,461,462,463,464,465,466,467,468,469,470,471,472,473,474,475,476,477,478,479,480,481,482,483,484,485,486,487,488,489,490,491,492,493,494,495,496,497,498,499,500,501,502,503,504,505,506,507,508,509,510,511,512,513,514,515,516,517,518,519,520,521,522,523,524,525,526,527,528,529,530,531,532,533,534,535,536,537,538,539,540,541,542,543,544,545,546,547,548,549,550,551,552,553,554,555,556,557,558,559,560,561,562,563,564,565,566,567,568,569,570,571,572,573,574,575,576,577,578,579,580,581,582,583,584,585,586,587,588,589,590,591,592,593,594,595,596,597,598,599,600,601,602,603,604,605,606,607,608,609,610,611,612,613,614,615,616,617,618,619,620,621,622,623,624,625,626,627,628,629,630,631,632,633,634,635,636,637,638,639 + MESSAGE_BUFF[%s] + no description available + 0x2000 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + + + MCAN1 + MCAN1 + MCAN + 0xf0284000 + + + MCAN2 + MCAN2 + MCAN + 0xf0288000 + + + MCAN3 + MCAN3 + MCAN + 0xf028c000 + + + MCAN4 + MCAN4 + MCAN + 0xf0290000 + + + MCAN5 + MCAN5 + MCAN + 0xf0294000 + + + MCAN6 + MCAN6 + MCAN + 0xf0298000 + + + MCAN7 + MCAN7 + MCAN + 0xf029c000 + + + PTPC + PTPC + PTPC + 0xf02fc000 + + 0x0 + 0x3004 + registers + + + + 2 + 0x1000 + 0,1 + PTPC[%s] + no description available + 0x0 + + Ctrl0 + Control Register 0 + 0x0 + 32 + 0x00000000 + 0x000003FF + + + SUBSEC_DIGITAL_ROLLOVER + Format for ns counter rollover, +1-digital, overflow time 1000000000/0x3B9ACA00 +0-binary, overflow time 0x7FFFFFFF + 9 + 1 + read-write + + + CAPT_SNAP_KEEP + set will keep capture snap till software read capt_snapl. +If this bit is set, software should read capt_snaph first to avoid wrong result. +If this bit is cleared, capture result will be updated at each capture event + 8 + 1 + read-write + + + CAPT_SNAP_POS_EN + set will use posege of input capture signal to latch timestamp value + 7 + 1 + read-write + + + CAPT_SNAP_NEG_EN + No description available + 6 + 1 + read-write + + + COMP_EN + set to enable compare, will be cleared by HW when compare event triggered + 4 + 1 + read-write + + + UPDATE_TIMER + update timer with +/- ts_updt, pulse, clear after set + 3 + 1 + write-only + + + INIT_TIMER + initial timer with ts_updt, pulse, clear after set + 2 + 1 + write-only + + + FINE_COARSE_SEL + 0: coarse update, ns counter add ss_incr[7:0] each clk +1: fine update, ns counter add ss_incr[7:0] each time addend counter overflow + 1 + 1 + read-write + + + TIMER_ENABLE + No description available + 0 + 1 + read-write + + + + + ctrl1 + Control Register 1 + 0x4 + 32 + 0x00000000 + 0x000000FF + + + SS_INCR + constant value used to add ns counter; +such as for 50MHz timer clock, set it to 8'd20 + 0 + 8 + read-write + + + + + timeh + timestamp high + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMESTAMP_HIGH + No description available + 0 + 32 + read-only + + + + + timel + timestamp low + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMESTAMP_LOW + No description available + 0 + 32 + read-only + + + + + ts_updth + timestamp update high + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + SEC_UPDATE + together with ts_updtl, used to initial or update timestamp + 0 + 32 + read-write + + + + + ts_updtl + timestamp update low + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADD_SUB + 1 for sub; 0 for add, used only at update + 31 + 1 + read-write + + + NS_UPDATE + No description available + 0 + 31 + read-write + + + + + addend + No description available + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDEND + used in fine update mode only + 0 + 32 + read-write + + + + + tarh + No description available + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + TARGET_TIME_HIGH + used for generate compare signal if enabled + 0 + 32 + read-write + + + + + tarl + No description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + TARGET_TIME_LOW + No description available + 0 + 32 + read-write + + + + + pps_ctrl + No description available + 0x2c + 32 + 0x00000000 + 0x0000000F + + + PPS_CTRL + No description available + 0 + 4 + read-write + + + + + capt_snaph + No description available + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPT_SNAP_HIGH + take snapshot for input capture signal, at pos or neg or both; +the result can be kept or updated at each event according to cfg0.bit8 + 0 + 32 + read-only + + + + + capt_snapl + No description available + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPT_SNAP_LOW + No description available + 0 + 32 + read-write + + + + + + time_sel + No description available + 0x2000 + 32 + 0x00000000 + 0x0000000F + + + CAN3_TIME_SEL + No description available + 3 + 1 + read-write + + + CAN2_TIME_SEL + No description available + 2 + 1 + read-write + + + CAN1_TIME_SEL + No description available + 1 + 1 + read-write + + + CAN0_TIME_SEL + set to use ptpc1 for canx +clr to use ptpc0 for canx + 0 + 1 + read-write + + + + + int_sts + No description available + 0x2004 + 32 + 0x00000000 + 0x00070007 + + + COMP_INT_STS1 + No description available + 18 + 1 + write-only + + + CAPTURE_INT_STS1 + No description available + 17 + 1 + write-only + + + PPS_INT_STS1 + No description available + 16 + 1 + write-only + + + COMP_INT_STS0 + No description available + 2 + 1 + write-only + + + CAPTURE_INT_STS0 + No description available + 1 + 1 + write-only + + + PPS_INT_STS0 + No description available + 0 + 1 + write-only + + + + + int_en + No description available + 0x2008 + 32 + 0x00000000 + 0x00070007 + + + COMP_INT_STS1 + No description available + 18 + 1 + read-write + + + CAPTURE_INT_STS1 + No description available + 17 + 1 + read-write + + + PPS_INT_STS1 + No description available + 16 + 1 + read-write + + + COMP_INT_STS0 + No description available + 2 + 1 + read-write + + + CAPTURE_INT_STS0 + No description available + 1 + 1 + read-write + + + PPS_INT_STS0 + No description available + 0 + 1 + read-write + + + + + ptpc_can_ts_sel + No description available + 0x3000 + 32 + 0x00000000 + 0xFFFFFF00 + + + TSU_TBIN3_SEL + No description available + 26 + 6 + read-write + + + TSU_TBIN2_SEL + No description available + 20 + 6 + read-write + + + TSU_TBIN1_SEL + No description available + 14 + 6 + read-write + + + TSU_TBIN0_SEL + No description available + 8 + 6 + read-write + + + + + + + LCDC + LCDC + LCDC + 0xf1000000 + + 0x0 + 0x404 + registers + + + + CTRL + Control Register + 0x0 + 32 + 0x00000000 + 0xFFF3E01F + + + SW_RST + Software reset, high active. When write 1 ,all internal logical will be reset. +0b - No action +1b - All LCDC internal registers are forced into their reset state. Interface registers are not affected. + 31 + 1 + read-write + + + DISP_ON + Display panel On/Off mode. +0b - Display Off. +1b - Display On. +Display can be set off at any time, but it can only be set on after VS_BLANK status is asserted. +So a good procedure to stop and turn on the display is: +1) clr VS_BLANK status +2) assert software reset +3) de-assert software reset +4) set display off +5) check VS_BLANK status until it is asserted, +6)reset the module, change settings +7) set display on + 30 + 1 + read-write + + + LINE_PATTERN + LCDIF line output order. +000b - RGB. +001b - RBG. +010b - GBR. +011b - GRB. +100b - BRG. +101b - BGR. + 27 + 3 + read-write + + + DISP_MODE + LCDIF operating mode. +00b - Normal mode. Panel content controlled by layer configuration. +01b - Test Mode1.(BGND Color Display) +10b - Test Mode2.(Column Color Bar) +11b - Test Mode3.(Row Color Bar) + 25 + 2 + read-write + + + BGDCL4CLR + background color for clear mode when the alpha channel is 0 + 24 + 1 + read-write + + + ARQOS + ARQOS for bus fabric arbitration + 20 + 4 + read-write + + + SHADOW_OP + Shadow Option +1: Use physical VSYNC (ST[VS_BLANK]) as shadow time. +0: Use layer internal logic VSYNC as shadow time. In general, this type of shadow control will have longer memory read time, so less underflow risk. + 17 + 1 + read-write + + + B_LE_MODE + Endianness mode for Blue Color Pads +1: Little endian. Pad 0 --> Color LSB 0 +0: Big Endian. Pad 0--> Color MSB 7 + 16 + 1 + read-write + + + G_LE_MODE + Endianness mode for Green Color Pads +1: Little endian. Pad 0 --> Color LSB 0 +0: Big Endian. Pad 0--> Color MSB 7 + 15 + 1 + read-write + + + R_LE_MODE + Endianness mode for Red Color Pads +1: Little endian. Pad 0 --> Color LSB 0 +0: Big Endian. Pad 0--> Color MSB 7 + 14 + 1 + read-write + + + CAM_SYNC_EN + Enable the VSYNC synchronization of CAM and LCDC + 13 + 1 + read-write + + + INV_PXDATA + Indicates if value at the output (pixel data output) needs to be negated. +0b - Output is to remain same as the data inside memory +1b - Output to be negated from the data inside memory + 4 + 1 + read-write + + + INV_PXCLK + Polarity change of Pixel Clock. +0b - LCDC outputs data on the rising edge, and Display samples data on the falling edge +1b - LCDC outputs data on the falling edge, Display samples data on the rising edge + 3 + 1 + read-write + + + INV_HREF + Polarity of HREF +0b - HREF signal active HIGH, indicating active pixel data +1b - HREF signal active LOW + 2 + 1 + read-write + + + INV_VSYNC + Polarity of VSYNC +0b - VSYNC signal active HIGH +1b - VSYNC signal active LOW + 1 + 1 + read-write + + + INV_HSYNC + Polarity of HSYNC +0b - HSYNC signal active HIGH +1b - HSYNC signal active LOW + 0 + 1 + read-write + + + + + BGND_CL + Background Color Register + 0x4 + 32 + 0x00000000 + 0x00FFFFFF + + + R + Red component of the default color displayed in the sectors where no layer is active. + 16 + 8 + read-write + + + G + Green component of the default color displayed in the sectors where no layer is active. + 8 + 8 + read-write + + + B + Blue component of the default color displayed in the sectors where no layer is active. + 0 + 8 + read-write + + + + + DISP_WN_SIZE + Display Window Size Register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + Y + Sets the display size vertical resolution in pixels. + 16 + 12 + read-write + + + X + Sets the display size horizontal resolution in pixels. + 0 + 12 + read-write + + + + + HSYNC_PARA + HSYNC Config Register + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + FP + HSYNC front-porch pulse width (in pixel clock cycles). If zero, indicates no front-porch for HSYNC + 22 + 9 + read-write + + + BP + HSYNC back-porch pulse width (in pixel clock cycles). If zero, indicates no back-porch for HSYNC + 11 + 9 + read-write + + + PW + HSYNC active pulse width (in pixel clock cycles). Pulse width has a minimum value of 1. + 0 + 9 + read-write + + + + + VSYNC_PARA + VSYNC Config Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + FP + VSYNC front-porch pulse width (in horizontal line cycles). If zero, means no front-porch for VSYNC + 22 + 9 + read-write + + + BP + VSYNC back-porch pulse width (in horizontal line cycles). If zero, means no back-porch for VSYNC + 11 + 9 + read-write + + + PW + VSYNC active pulse width (in horizontal line cycles). Pulse width has a minimum value of 1. + 0 + 9 + read-write + + + + + DMA_ST + DMA Status Register + 0x14 + 32 + 0x00000000 + 0xFFFFFF00 + + + DMA_ERR + plane n axi error. W1C. + 24 + 8 + write-only + + + DMA1_DONE + Plane n frame 1 dma done. W1C. + 16 + 8 + write-only + + + DMA0_DONE + Plane n frame 0 dma done. W1C. + 8 + 8 + write-only + + + + + ST + Status Register + 0x18 + 32 + 0x00000000 + 0x000001FF + + + P1_HANDSHAKE_ABORT + Plane 1 handshake abort error. W1C + 8 + 1 + write-only + + + P0_HANDSHAKE_ABORT + Plane 0 handshake abort error. W1C + 7 + 1 + write-only + + + CAM_HCNT_FAIL + During cam_vsync mode, sync fail due to hcnt out of acceptable ranges. W1C + 6 + 1 + write-only + + + CAM_VSYNC_FAIL + During cam_vsync mode, sync fail due to out of vsync parameters. W1C + 5 + 1 + write-only + + + SHADOW_DONE + Shadow done status. This is an OR-ed signals of all shadow_done signals of all planes, and it can only be cleared by writing 1 for all asserted bits in SHADOW_DONE_ST register. + 4 + 1 + read-only + + + URGENT_UNDERRUN + Asserted when the output buffer urgent underrun condition encountered + 3 + 1 + write-only + + + VS_BLANK + Asserted when in vertical blanking period. At the start of VSYNC + 2 + 1 + write-only + + + UNDERRUN + Asserted when the output buffer underrun condition encountered + 1 + 1 + write-only + + + VSYNC + Asserted when in vertical blanking period. At the end of VSYNC + 0 + 1 + write-only + + + + + INT_EN + Interrupt Enable Register + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + DMA_ERR + Interrupt enable for DMA error + 24 + 8 + read-write + + + DMA_DONE + Interrupt enable for DMA done + 16 + 8 + read-write + + + HANDSHAKE_ABORT + Handshake abort error int enable + 7 + 1 + read-write + + + CAM_HCNT_FAIL + hcnt out of acceptable ranges interrupt enable + 6 + 1 + read-write + + + CAM_VSYNC_FAIL + cam_vsync fail interrupt enable + 5 + 1 + read-write + + + SHADOW_DONE + Shadow done interrupt enable + 4 + 1 + read-write + + + URGENT_UNDERRUN + Asserted when the output buffer urgent underrun condition encountered + 3 + 1 + read-write + + + VS_BLANK + Interrupt enable for start of sof + 2 + 1 + read-write + + + UNDERRUN + Interrupt enable for underrun + 1 + 1 + read-write + + + VSYNC + Interrupt enable for end of sof + 0 + 1 + read-write + + + + + TXFIFO + TX FIFO Register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + THRSH + Threshold to start the lcd raster (0--0x7F) + 0 + 8 + read-write + + + + + CTRL_BP_V_RANGE + BP_V range for CAMSYNC mode + 0x24 + 32 + 0x00000000 + 0x07FFFFFF + + + MAX + Maximal BP_V values + 18 + 9 + read-write + + + BEST + Best BP_V values + 9 + 9 + read-write + + + MIN + Minimal BP_V values + 0 + 9 + read-write + + + + + CTRL_PW_V_RANGE + PW_V range for CAMSYNC mode + 0x28 + 32 + 0x00000000 + 0x07FFFFFF + + + MAX + Maximal PW_V values + 18 + 9 + read-write + + + BEST + Best PW_V values + 9 + 9 + read-write + + + MIN + Minimal PW_V values + 0 + 9 + read-write + + + + + CTRL_FP_V_RANGE + FP_V range for CAMSYNC mode + 0x2c + 32 + 0x00000000 + 0x07FFFFFF + + + MAX + Maximal FP_V values + 18 + 9 + read-write + + + BEST + Best FP_V values + 9 + 9 + read-write + + + MIN + Minimal FP_V values + 0 + 9 + read-write + + + + + CAM_SYNC_HCNT_MIN + min HCNT value for CAMSYNC mode + 0x30 + 32 + 0x00000000 + 0x0000FFFF + + + VAL + minimal acceptable HCNT Value + 0 + 16 + read-write + + + + + CAM_SYNC_HCNT_BEST + best HCNT value for CAMSYNC mode + 0x34 + 32 + 0x00000000 + 0x00FFFFFF + + + HYST + hysteresys of acceptable HCNT Value + 16 + 8 + read-write + + + VAL + best acceptable HCNT Value + 0 + 16 + read-write + + + + + CAM_SYNC_HCNT_MAX + max HCNT value for CAMSYNC mode + 0x38 + 32 + 0x00000000 + 0x0000FFFF + + + VAL + maximal acceptable HCNT Value + 0 + 16 + read-write + + + + + CAM_SYNC_HCNT_ST + current HCNT value for CAMSYNC mode + 0x3c + 32 + 0x00000000 + 0x0000FFFF + + + VAL + current HCNT value + 0 + 16 + read-only + + + + + SHADOW_DONE_ST + Shadow done status + 0x40 + 32 + 0x00000000 + 0x000000FF + + + VAL + current shadow_done value for plane 7,...,0 respectively + 0 + 8 + write-only + + + + + SHADOW_DONE_INT_EN + Shadow done interrupt enable + 0x44 + 32 + 0x00000000 + 0x000000FF + + + VAL + shadow_done interrupt enable for plane 7,...,0 respectively + 0 + 8 + read-write + + + + + 8 + 0x40 + 0,1,2,3,4,5,6,7 + LAYER[%s] + no description available + 0x200 + + LAYCTRL + Layer Control Register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFD + + + RESAMPLE_VRATIO + Resample the input data stream in the verticle direction +0: don't resample +positive n: upsample-by-n+1 (2 to 8) +negtive n: downsample-by-n+1 (2 to 8) + 28 + 4 + read-write + + + RESAMPLE_HRATIO + Resample the input data stream in the horizontal direction +0: don't resample +positive n: upsample-by-n+1 (2 to 8) +negtive n: downsample-by-n+1 (2 to 8) + 24 + 4 + read-write + + + NORMLZ_OUT + Normalize the pixel out for the not-overlapped pixels + 23 + 1 + read-write + + + HANDSHAKE_ABORT_INT_EN + 1: Enable the handshake abort error interrupt. +0: don't Enable the handshake abort error interrupt. +Abort is generated when the LCDC is going to switch bank to a new bank, and the new bank data is not ready yet. +Abort is only useful when communicating with the offline calculator (such as PDMA as the active pixel generator mode). +PDMA as the active generator mode, means it is the first pixel generator with data sources from offline memory, and not from on-the-fly streaming data (such as camera captured data). +While with on-the-fly streaming data, error condition is indicated by display buffer underflow. + 22 + 1 + read-write + + + HANDSHAKE_BUFSIZE + 1: handshake buffer is 16 rows hight per ping or pang buf. +0: handshake buffer is 8 rows hight per ping or pang buf. + 21 + 1 + read-write + + + ENABLE_HANDSHAKE + Enable handshake with input pixel controller. When this is set, the LCDC will not process an entire framebuffer, +but will instead process rows of NxN blocks in a double-buffer handshake with the input pixel controlller. This enables +the use of the onboard SRAM for a partial frame buffer. Only valid for Plane 0 & 1. +1: handshake enabled +0: handshake disabled + 20 + 1 + read-write + + + PACK_DIR + The byte sequence of the 4 bytes in a 32-bit word. +1: {A0, A1, A2, A3} byte re-ordered. +0: {A3, A2, A1, A0} the normal case with no byte re-order + 19 + 1 + read-write + + + SHADOW_LOAD_EN + Shadow Load Enable +The SHADOW_LOAD_EN bit is written to 1 by software after all DMA control registers are written. If set to 1, shadowed control registers are updated to the active control registers on internal logical VSYNC of next frame. If set to 0, shadowed control registers are not loaded into the active control registers. The previous active control register settings will be used to process the next frame. Hardware will automatically clear this bit, when the shadow registers are loaded to the active control regsisters. + 16 + 1 + read-write + + + YUV_FORMAT + The YUV422 input format selection. +00b - The YVYU422 8bit sequence is U1,Y1,V1,Y2 +01b - The YVYU422 8bit sequence is V1,Y1,U1,Y2 +10b - The YVYU422 8bit sequence is Y1,U1,Y2,V1 +11b - The YVYU422 8bit sequence is Y1,V1,Y2,U1 +If not YUV422 mode, +FORMAT[0]: asserted to exchange sequence inside the bytes. Org [15:8]-->New[8:15], Org [7:0]-->New[0:7]. (First exchange) +FORMAT[1]: asserted to exchange the sequence of the odd and even 8 bits. Org Even [7:0]-->New[15:8], Org Odd [15:8]-->New[7:0]. (Second exchange) + 14 + 2 + read-write + + + PIXFORMAT + Layer encoding format (bit per pixel) +0000b - 1 bpp (pixel width must be multiples of 32), pixel sequence is from LSB to MSB in 32b word. +0001b - 2 bpp (pixel width must be multiples of 16), pixel sequence is from LSB to MSB in 32b word. +0010b - 4 bpp (pixel width must be multiples of 8), pixel sequence is from LSB to MSB in 32b word. +0011b - 8 bpp (pixel width must be multiples of 4), pixel sequence is from LSB to MSB in 32b word. +0100b - 16 bpp (RGB565), the low byte contains the full R component. +0111b - YCbCr422 (Only layer 0/1 can support this format), byte sequence determined by LAYCTRL[YUV_FORMAT] +1001b - 32 bpp (ARGB8888), byte sequence as B,G,R,A +1011b - Y8 (pixel width must be multiples of 4), byte sequence as Y1,Y2,Y3,Y4 + 10 + 4 + read-write + + + LOCALPHA_OP + The usage of the LOCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) +0: the LOCALPHA[7:0] is invalid, use the alpha value from the data stream +1: the LOCALPHA[7:0] is used to override the alpha value in the data stream (useful when the data stream has no alpha info) +2: the LOCALPHA[7:0] is used to scale the alpha value from the data stream +Others: Reserved + 8 + 2 + read-write + + + INALPHA_OP + The usage of the INALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) +0: the INALPHA[7:0] is invalid, use the alpha value from previous pipeline +1: the INALPHA[7:0] is used to override the alpha value from previous pipeline. (useful when the corresponding data stream has no alpha info) +2: the INALPHA[7:0] is used to scale the alpha value from previous pipeline +Others: Reserved + 6 + 2 + read-write + + + AB_MODE + Alpha Blending Mode +0: SKBlendMode_Clear; +3: SKBlendMode_SrcOver +14: SRC org +15: DST org +Others: Reserved. + 2 + 4 + read-write + + + EN + Asserted when the layer is enabled. If this layer is not enabled, it means a bypassing plane. + 0 + 1 + read-write + + + + + ALPHAS + Layer Alpha Register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCD + The system alpha value for the data stream of current layer stream (SRC) + 8 + 8 + read-write + + + IND + The system alpha value for the input stream from previous stage (DST) + 0 + 8 + read-write + + + + + LAYSIZE + Layer Size Register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + HEIGHT + Height of the layer in pixels + 16 + 12 + read-write + + + WIDTH + Width of the layer in pixels (Note: not actual width-1) +The layer width must be in multiples of the number of pixels that can be stored in 32 bits, and therefore differs depending on color encoding. For example, if 2 bits per pixel format is used, then the layer width must be configured in multiples of 16. + 0 + 12 + read-write + + + + + LAYPOS + Layer Position Register + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + Y + The vertical position of top row of the layer, where 0 is the top row of the panel, positive values are below the top row of the panel. + 16 + 16 + read-write + + + X + The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, positive values are to the right the left-hand column of the panel. + 0 + 16 + read-write + + + + + START0 + Layer Buffer Pointer Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR0 + Input buffer Start address 0 + 0 + 32 + read-write + + + + + LINECFG + Layer Bus Config Register + 0x18 + 32 + 0x00000000 + 0xE0FFFFFF + + + MPT_SIZE + Maximal Per Transfer Data Size: +0: 64 bytes +1: 128 bytes +2: 256 bytes +3: 512 bytes +4: 1024 bytes + 29 + 3 + read-write + + + MAX_OT + the number of outstanding axi read transactions. +If zero, it means max 8. + 21 + 3 + read-write + + + PITCH + Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundary. + 0 + 16 + read-write + + + + + BG_CL + Layer Background Color Register + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + ARGB + ARGB8888. It is only useful in the last active stage in the pipeline. + 0 + 32 + read-write + + + + + CSC_COEF0 + Layer Color Space Conversion Config Register 0 + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + YCBCR_MODE + This bit changes the behavior when performing U/V converting. +0b - Converting YUV to RGB data +1b - Converting YCbCr to RGB data + 31 + 1 + read-write + + + ENABLE + Enable the CSC unit in the LCDC plane data path. +0b - The CSC is bypassed and the input pixels are RGB data already +1b - The CSC is enabled and the pixels will be converted to RGB data +This bit will be shadowed. + 30 + 1 + read-write + + + C0 + Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) + 18 + 11 + read-write + + + UV_OFFSET + Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. +YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). + 9 + 9 + read-write + + + Y_OFFSET + Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is +typically -16 (0x1F0). + 0 + 9 + read-write + + + + + CSC_COEF1 + Layer Color Space Conversion Config Register 1 + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + C1 + Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). + 16 + 11 + read-write + + + C4 + Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). + 0 + 11 + read-write + + + + + CSC_COEF2 + Layer Color Space Conversion Config Register 2 + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + C2 + Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). + 16 + 11 + read-write + + + C3 + Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). + 0 + 11 + read-write + + + + + + CLUT_LOAD + Clut Load Control Register + 0x400 + 32 + 0x00000000 + 0x8000007F + + + STR_HIGH + 1'b1: Store 8+ CLUT tables through APB +1'b0: Store 0-7 CLUT tables through APB + 31 + 1 + read-write + + + SEL_NUM + Selected CLUT Number +The SEL_CLUT_NUM is used to select which plane's CLUT need to be updated. The hardware can only backup one CLUT setting and load, so the SEL_CLUT_NUM can't be changed when CLUT_LOAD[UPDATE_EN] is 1. +. 3'h0 - PLANE 0 +. 3'h1 - PLANE 1 +. ------ +. 3'h7 - PLANE 7 +CLUT 8 can be modified via APB even when display is on. +Currently CLUT for plane 0..7 cannot be modified via APB when display is on. Can only be updated via CLUT_LOAD[UPDATE_EN] bit. + 4 + 3 + read-write + + + UPDATE_EN + CLUT Update Enable +The bit is written to 1 when software want to update the Color Look Up Tables during display. +If set to 1, software update selected CLUT due to SEL_CLUT_NUM setting, the table will be copied from CLUT8 during vertical blanking period after SHADOW_LOAD_EN is set to 1. +If set to 0, software can update CLUT8 directly according to the CLUT memory map. +Hardware will automatically clear this bit when selected CLUT is updated according to SEL_CLUT_NUM. + 0 + 1 + read-write + + + + + + + LCDC1 + LCDC1 + LCDC + 0xf1004000 + + + CAM0 + CAM0 + CAM + 0xf1008000 + + 0x0 + 0x4b0 + registers + + + + CR1 + Control Register + 0x0 + 32 + 0x00000000 + 0xFF9AAFFF + + + INV_DEN + invert den pad input before it is used + 30 + 1 + read-write + + + COLOR_EXT + If asserted, will change the output color to ARGB8888 mode. Used by input color as RGB565, RGB888, YUV888, etc. +The byte sequence is B,G,R,A. Depends on correct CR2[ClrBitFormat] configuration. + 29 + 1 + read-write + + + INV_PIXCLK + invert pixclk pad input before it is used + 28 + 1 + read-write + + + INV_HSYNC + invert hsync pad input before it is used + 27 + 1 + read-write + + + INV_VSYNC + invert vsync pad input before it is used + 26 + 1 + read-write + + + SWAP16_EN + SWAP 16-Bit Enable. This bit enables the swapping of 16-bit data. Data is packed from 8-bit or 10-bit to 32-bit first (according to the setting of PACK_DIR) and then swapped as 16-bit words before being put into the RX FIFO. The action of the bit only affects the RX FIFO. +NOTE: Example of swapping enabled: +Data input to FIFO = 0x11223344 +Data in RX FIFO = 0x 33441122 +NOTE: Example of swapping disabled: +Data input to FIFO = 0x11223344 +Data in RX FIFO = 0x11223344 +0 Disable swapping +1 Enable swapping + 25 + 1 + read-write + + + PACK_DIR + Data Packing Direction. This bit Controls how 8-bit/10-bit image data is packed into 32-bit RX FIFO. +0 Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. +1 Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. + 24 + 1 + read-write + + + RESTART_BUSPTR + force to restart the bus pointer at the every end of the sof period, and at the same time, clr the fifo pointer + 23 + 1 + read-write + + + ASYNC_RXFIFO_CLR + ASynchronous Rx FIFO Clear. +When asserted, this bit clears RXFIFO immediately. +It will be auto-cleared. + 20 + 1 + read-write + + + SYNC_RXFIFO_CLR + Synchronous Rx FIFO Clear. +When asserted, this bit clears RXFIFO on every SOF. + 19 + 1 + read-write + + + SOF_INT_POL + SOF Interrupt Polarity. This bit controls the condition that generates an SOF interrupt. +0 SOF interrupt is generated on SOF falling edge +1 SOF interrupt is generated on SOF rising edge + 17 + 1 + read-write + + + INV_DATA + Invert Data Input. This bit enables or disables internal inverters on the data lines. +0 CAM_D data lines are directly applied to internal circuitry +1 CAM_D data lines are inverted before applied to internal circuitry + 15 + 1 + read-write + + + STORAGE_MODE + 00: Normal Mode (one plane mode) +01: Two Plane Mode (Y, UV plane) +10: Y-only Mode, byte sequence as Y0,Y1,Y2,Y3 +11: Binary Mode, bit sequence is from LSB to MSB when CR20[BIG_END]=0 + 10 + 2 + read-write + + + COLOR_FORMATS + input color formats: +0010b:24bit:RGB888 +0011b:24bit:RGB666 +0100b:16bit:RGB565 +0101b:16bit:RGB444 +0110b:16bit:RGB555 +0111b: 16bit: YCbCr422 (Y0 Cb Y1 Cr, each 8-bit) +YUV +YCrCb +Note: YUV420 is not supported. +1000b: 24bit: YUV444 + 3 + 4 + read-write + + + SENSOR_BIT_WIDTH + the bit width of the sensor +0: 8 bits +1: 10 bits +3:24bits +Others: Undefined + 0 + 3 + read-write + + + + + INT_EN + Interrupt Enable Register + 0x4 + 32 + 0x00000000 + 0xFFFFFF5F + + + ERR_CL_BWID_CFG_INT_EN + The unsupported color (color_formats[3:0]) and bitwidth (sensor_bit_width[2:0]) configuation interrupt enable + 13 + 1 + read-write + + + HIST_DONE_INT_EN + Enable hist done int + 12 + 1 + read-write + + + HRESP_ERR_EN + Hresponse Error Enable. This bit enables the hresponse error interrupt. +0 Disable hresponse error interrupt +1 Enable hresponse error interrupt + 11 + 1 + read-write + + + EOF_INT_EN + End-of-Frame Interrupt Enable. This bit enables and disables the EOF interrupt. +0 EOF interrupt is disabled. +1 EOF interrupt is generated when RX count value is reached. + 9 + 1 + read-write + + + RF_OR_INTEN + RxFIFO Overrun Interrupt Enable. This bit enables the RX FIFO overrun interrupt. +0 RxFIFO overrun interrupt is disabled +1 RxFIFO overrun interrupt is enabled + 6 + 1 + read-write + + + FB2_DMA_DONE_INTEN + Frame Buffer2 DMA Transfer Done Interrupt Enable. This bit enables the interrupt of Frame Buffer2 DMA +transfer done. +0 Frame Buffer2 DMA Transfer Done interrupt disable +1 Frame Buffer2 DMA Transfer Done interrupt enable + 3 + 1 + read-write + + + FB1_DMA_DONE_INTEN + Frame Buffer1 DMA Transfer Done Interrupt Enable. This bit enables the interrupt of Frame Buffer1 DMA +transfer done. +0 Frame Buffer1 DMA Transfer Done interrupt disable +1 Frame Buffer1 DMA Transfer Done interrupt enable + 2 + 1 + read-write + + + SOF_INT_EN + Start Of Frame (SOF) Interrupt Enable. This bit enables the SOF interrupt. +0 SOF interrupt disable +1 SOF interrupt enable + 0 + 1 + read-write + + + + + CR2 + Control 2 Register + 0x10 + 32 + 0x00000000 + 0xFFFF8FEF + + + FRMCNT_15_0 + Frame Counter. This is a 16-bit Frame Counter +(Wraps around automatically after reaching the maximum) + 16 + 16 + read-only + + + FRMCNT_RST + Frame Count Reset. Resets the Frame Counter. +0 Do not reset +1 Reset frame counter immediately + 15 + 1 + read-write + + + RXFF_LEVEL + RxFIFO Full Level. When the number of data in RxFIFO reaches this level, a RxFIFO full interrupt is generated, or an RXFIFO DMA request is sent. +000 4 Double words +001 8 Double words +010 16 Double words +011 24 Double words +100 32 Double words +101 48 Double words +110 64 Double words +111 96 Double words + 9 + 3 + read-write + + + DMA_REQ_EN_RFF + DMA Request Enable for RxFIFO. This bit enables the dma request from RxFIFO to the embedded DMA controller. +0 Disable the dma request +1 Enable the dma request. The UV Rx FIFO is only enabled to filling data in 2 plane mode. + 5 + 1 + read-write + + + CLRBITFORMAT + Input Byte & bit sequence same as OV5640, except for Raw mode. Used only for internal ARGB conversion. + 0 + 4 + read-write + + + + + STA + Status Register + 0x24 + 32 + 0x00000000 + 0xFFFFA7FC + + + ERR_CL_BWID_CFG + The unsupported color (color_formats[3:0]) and bitwidth (sensor_bit_width[2:0]) configuation found + 19 + 1 + write-only + + + HIST_DONE + hist cal done + 18 + 1 + write-only + + + RF_OR_INT + RxFIFO Overrun Interrupt Status. Indicates the overflow status of the RxFIFO register. (Cleared by writing +1) +0 RXFIFO has not overflowed. +1 RXFIFO has overflowed. + 13 + 1 + write-only + + + DMA_TSF_DONE_FB2 + DMA Transfer Done in Frame Buffer2. Indicates that the DMA transfer from RxFIFO to Frame Buffer2 is completed. It can trigger an interrupt if the corresponding enable bit is set in CAM_CR1. This bit can be cleared by by writing 1 or reflashing the RxFIFO dma controller in CAM_CR3. (Cleared by writing 1) +0 DMA transfer is not completed. +1 DMA transfer is completed. + 10 + 1 + write-only + + + DMA_TSF_DONE_FB1 + DMA Transfer Done in Frame Buffer1. Indicates that the DMA transfer from RxFIFO to Frame Buffer1 is completed. It can trigger an interrupt if the corresponding enable bit is set in CAM_CR1. This bit can be cleared by by writing 1 or reflashing the RxFIFO dma controller in CAM_CR3. (Cleared by writing 1) +0 DMA transfer is not completed. +1 DMA transfer is completed. + 9 + 1 + write-only + + + EOF_INT + End of Frame (EOF) Interrupt Status. Indicates when EOF is detected. (Cleared by writing 1) +0 EOF is not detected. +1 EOF is detected. + 7 + 1 + write-only + + + SOF_INT + Start of Frame Interrupt Status. Indicates when SOF is detected. (Cleared by writing 1) +0 SOF is not detected. +1 SOF is detected. + 6 + 1 + write-only + + + HRESP_ERR_INT + Hresponse Error Interrupt Status. Indicates that a hresponse error has been detected. (Cleared by writing +1) +0 No hresponse error. +1 Hresponse error is detected. + 2 + 1 + write-only + + + + + DMASA_FB1 + Pixel DMA Frame Buffer 1 Address + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + PTR + DMA Start Address in Frame Buffer1. Indicates the start address to write data. The embedded DMA controller will read data from RxFIFO and write it from this address through AHB bus. The address should be double words aligned. +In Two-Plane Mode, Y buffer1 + 2 + 30 + read-write + + + + + DMASA_FB2 + Pixel DMA Frame Buffer 2 Address + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + PTR + DMA Start Address in Frame Buffer2. Indicates the start address to write data. The embedded DMA controller will read data from RxFIFO and write it from this address through AHB bus. The address should be double words aligned. +In Two-Plane Mode, Y buffer2 + 2 + 30 + read-write + + + + + BUF_PARA + Buffer Parameters Register + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINEBSP_STRIDE + Line Blank Space Stride. Indicates the space between the end of line image storage and the start of a new line storage in the frame buffer. +The width of the line storage in frame buffer(in double words) minus the width of the image(in double words) is the stride. The stride should be double words aligned. The embedded DMA controller will skip the stride before starting to write the next row of the image. + 0 + 16 + read-write + + + + + IDEAL_WN_SIZE + Ideal Image Size Register + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + HEIGHT + Image Height. Indicates how many active pixels in a column of the image from the sensor. + 16 + 16 + read-write + + + WIDTH + Image Width. Indicates how many active pixels in a line of the image from the sensor. +The number of bytes to be transferred is re-calculated automatically in hardware based on cr1[color_ext] and cr1[store_mode]. Default value is 2*pixel number. +As the input data from the sensor is 8-bit/pixel format, the IMAGE_WIDTH should be a multiple of 8 pixels. + 0 + 16 + read-write + + + + + CR18 + Control CR18 Register + 0x4c + 32 + 0x00000000 + 0x7FFFE7BF + + + AWQOS + AWQOS for bus fabric arbitration + 7 + 4 + read-write + + + + + DMASA_UV1 + Pixel UV DMA Frame Buffer 1 Address + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + PTR + Two Plane UV Buffer Start Address 1 + 2 + 30 + read-write + + + + + DMASA_UV2 + Pixel UV DMA Frame Buffer 2 Address + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + PTR + Two Plane UV Buffer Start Address 2 + 2 + 30 + read-write + + + + + CR20 + Control CR20 Register + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + BINARY_EN + binary picture output enable + 31 + 1 + read-write + + + HISTOGRAM_EN + histogarm enable + 30 + 1 + read-write + + + BIG_END + Asserted when binary output is in big-endian type, which mean the right most data is at the LSBs. Take function only inside the 32-bit word. + 8 + 1 + read-write + + + THRESHOLD + Threshold to generate binary color. Bin 1 is output if the pixel is greater than the threshold. + 0 + 8 + read-write + + + + + CSC_COEF0 + Color Space Conversion Config Register 0 + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + YCBCR_MODE + This bit changes the behavior when performing U/V converting. +0b - Converting YUV to RGB data +1b - Converting YCbCr to RGB data + 31 + 1 + read-write + + + ENABLE + Enable the CSC unit +0b - The CSC is bypassed and the input pixels are RGB data already +1b - The CSC is enabled and the pixels will be converted to RGB data + 30 + 1 + read-write + + + C0 + Two's compliment Y multiplier coefficient. YUV=0x100 (1.000) YCbCr=0x12A (1.164) + 18 + 11 + read-write + + + UV_OFFSET + Two's compliment phase offset implicit for CbCr data. Generally used for YCbCr to RGB conversion. +YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). + 9 + 9 + read-write + + + Y_OFFSET + Two's compliment amplitude offset implicit in the Y data. For YUV, this is typically 0 and for YCbCr, this is +typically -16 (0x1F0). + 0 + 9 + read-write + + + + + CSC_COEF1 + Color Space Conversion Config Register 1 + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + C1 + Two's compliment Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596). + 16 + 11 + read-write + + + C4 + Two's compliment Blue U/Cb multiplier coefficient. YUV=0x208 (2.032) YCbCr=0x204 (2.017). + 0 + 11 + read-write + + + + + CSC_COEF2 + Color Space Conversion Config Register 2 + 0x78 + 32 + 0x00000000 + 0xFFFFFFFF + + + C2 + Two's compliment Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). + 16 + 11 + read-write + + + C3 + Two's compliment Green U/Cb multiplier coefficient. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). + 0 + 11 + read-write + + + + + CLRKEY_LOW + Low Color Key Register + 0x7c + 32 + 0x00000000 + 0xFFFFFFFF + + + LIMIT + Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. + 0 + 24 + read-write + + + + + CLRKEY_HIGH + High Color Key Register + 0x80 + 32 + 0x00000000 + 0xFFFFFFFF + + + LIMIT + Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. + 0 + 24 + read-write + + + + + 256 + 0x4 + DATA0,DATA1,DATA2,DATA3,DATA4,DATA5,DATA6,DATA7,DATA8,DATA9,DATA10,DATA11,DATA12,DATA13,DATA14,DATA15,DATA16,DATA17,DATA18,DATA19,DATA20,DATA21,DATA22,DATA23,DATA24,DATA25,DATA26,DATA27,DATA28,DATA29,DATA30,DATA31,DATA32,DATA33,DATA34,DATA35,DATA36,DATA37,DATA38,DATA39,DATA40,DATA41,DATA42,DATA43,DATA44,DATA45,DATA46,DATA47,DATA48,DATA49,DATA50,DATA51,DATA52,DATA53,DATA54,DATA55,DATA56,DATA57,DATA58,DATA59,DATA60,DATA61,DATA62,DATA63,DATA64,DATA65,DATA66,DATA67,DATA68,DATA69,DATA70,DATA71,DATA72,DATA73,DATA74,DATA75,DATA76,DATA77,DATA78,DATA79,DATA80,DATA81,DATA82,DATA83,DATA84,DATA85,DATA86,DATA87,DATA88,DATA89,DATA90,DATA91,DATA92,DATA93,DATA94,DATA95,DATA96,DATA97,DATA98,DATA99,DATA100,DATA101,DATA102,DATA103,DATA104,DATA105,DATA106,DATA107,DATA108,DATA109,DATA110,DATA111,DATA112,DATA113,DATA114,DATA115,DATA116,DATA117,DATA118,DATA119,DATA120,DATA121,DATA122,DATA123,DATA124,DATA125,DATA126,DATA127,DATA128,DATA129,DATA130,DATA131,DATA132,DATA133,DATA134,DATA135,DATA136,DATA137,DATA138,DATA139,DATA140,DATA141,DATA142,DATA143,DATA144,DATA145,DATA146,DATA147,DATA148,DATA149,DATA150,DATA151,DATA152,DATA153,DATA154,DATA155,DATA156,DATA157,DATA158,DATA159,DATA160,DATA161,DATA162,DATA163,DATA164,DATA165,DATA166,DATA167,DATA168,DATA169,DATA170,DATA171,DATA172,DATA173,DATA174,DATA175,DATA176,DATA177,DATA178,DATA179,DATA180,DATA181,DATA182,DATA183,DATA184,DATA185,DATA186,DATA187,DATA188,DATA189,DATA190,DATA191,DATA192,DATA193,DATA194,DATA195,DATA196,DATA197,DATA198,DATA199,DATA200,DATA201,DATA202,DATA203,DATA204,DATA205,DATA206,DATA207,DATA208,DATA209,DATA210,DATA211,DATA212,DATA213,DATA214,DATA215,DATA216,DATA217,DATA218,DATA219,DATA220,DATA221,DATA222,DATA223,DATA224,DATA225,DATA226,DATA227,DATA228,DATA229,DATA230,DATA231,DATA232,DATA233,DATA234,DATA235,DATA236,DATA237,DATA238,DATA239,DATA240,DATA241,DATA242,DATA243,DATA244,DATA245,DATA246,DATA247,DATA248,DATA249,DATA250,DATA251,DATA252,DATA253,DATA254,DATA255 + HISTOGRAM_FIFO[%s] + no description available + 0x90 + 32 + 0x00000000 + 0xFFFFFFFF + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + ROI_WIDTH + Roi Width Config Register + 0x490 + 32 + 0x00000000 + 0xFFFFFFFF + + + ROI_WIDTH_END + end address of width for roi + 16 + 16 + read-write + + + ROI_WIDTH_START + start address of width for roi + 0 + 16 + read-write + + + + + ROI_HEIGHT + Roi Width Config Register + 0x494 + 32 + 0x00000000 + 0xFFFFFFFF + + + ROI_HEIGHT_END + end address of height for roi + 16 + 16 + read-write + + + ROI_HEIGHT_START + start address of height for roi + 0 + 16 + read-write + + + + + PRO_CTRL + Pro Config Register + 0x498 + 32 + 0x00000000 + 0xFFFF40FF + + + ERR_INJECT + 0 generate alarm in normal mode +1 force to generate fatal alarm + 14 + 1 + read-write + + + ROI_UPDATE + roi configration update + 7 + 1 + read-write + + + SCALE_UPDATE + scale configration update + 6 + 1 + read-write + + + SCALE_HEIGHT_SELECT + 000 keep all pixel for height +001 keep 1 for every 2 pixel for height +010 keep 1 for every 3 pixel for height +011 keep 1 for every 4 pixel for height +100 keep 1 for every 5 pixel for height +101 keep 1 for every 6 pixel for height +110 keep 1 for every 7 pixel for height +111 keep 1 for every 8 pixel for height + 3 + 3 + read-write + + + SCALE_WIDTH_SELECT + 000 keep all pixel for width +001 keep 1 for every 2 pixel for width +010 keep 1 for every 3 pixel for width +011 keep 1 for every 4 pixel for width +100 keep 1 for every 5 pixel for width +101 keep 1 for every 6 pixel for width +110 keep 1 for every 7 pixel for width +111 keep 1 for every 8 pixel for width + 0 + 3 + read-write + + + + + ACT_SIZE + actual size + 0x49c + 32 + 0x00000000 + 0xFFFFFFFF + + + ACT_HEIGHT + actual height after scale and/or roi + 16 + 16 + read-write + + + ACT_WIDTH + actual width after scale and/or roi + 0 + 16 + read-write + + + + + VSYNC_VALID_CNT + vsync valid counter + 0x4a0 + 32 + 0x00000000 + 0xFFFFFFFF + + + VSYNC_VALID_CNT + vsync valid counter + 0 + 32 + read-write + + + + + HSYNC_VALID_CNT + hsync valid counter + 0x4a4 + 32 + 0x00000000 + 0xFFFFFFFF + + + HSYNC_VALID_CNT + hsync valid counter + 0 + 32 + read-write + + + + + VALID_MARGIN + valid margin + 0x4a8 + 32 + 0x00000000 + 0xFFFFFFFF + + + HSYNC_VALID_MARGIN + hsync valid margin + 16 + 16 + read-write + + + VSYNC_VALID_MARGIN + vsync valid margin + 0 + 16 + read-write + + + + + ALARM_SET + alarm set + 0x4ac + 32 + 0x00000000 + 0xFFFFFFFF + + + SIG_NORMAL + define signal duty cycles(base clock) +0x0: disable signal +0x1: high 1, low 15 +0x2: high 2, low 14 +…... +0xF: high 15, low 1 + 20 + 4 + read-write + + + FATAL_NORMAL + define signal duty cycles(base clock) +0x0: disable signal +0x1: high 1, low 15 +0x2: high 2, low 14 +…... +0xF: high 15, low 1 + 16 + 4 + read-write + + + PRE_DIV + frequency division + 0 + 16 + read-write + + + + + + + CAM1 + CAM1 + CAM + 0xf100c000 + + + PDMA + PDMA + PDMA + 0xf1010000 + + 0x0 + 0xc0 + registers + + + + CTRL + Control Register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + ARQOS + QoS for AXI read bus + 19 + 4 + read-write + + + AWQOS + QoS for AXI write bus + 15 + 4 + read-write + + + PACK_DIR + Decide the byte sequence of the 32-bit output word {A3, A2, A1, A0}. The bit sequence ina byte is not changed. +2'b00: no change {A3, A2, A1, A0} +2'b01: {A2, A3, A0, A1} +2'b10: {A1, A0, A3, A2} +2'b11: {A0, A1, A2, A3} + 13 + 2 + read-write + + + AXIERR_IRQ_EN + Enable interrupt of AXI bus error + 12 + 1 + read-write + + + PDMA_DONE_IRQ_EN + Enable interrupt of PDMA_DONE + 11 + 1 + read-write + + + CLKGATE + Assert this bit to gate off clock when the module is not working. If reset to zero, the internal clock is always on. + 9 + 1 + read-write + + + IRQ_EN + Enable normal interrupt + 6 + 1 + read-write + + + BS16 + Asserted when the Block Size is 16x16, else 8x8 + 5 + 1 + read-write + + + P1_EN + Plane 1 Enable + 4 + 1 + read-write + + + P0_EN + Plane 0 Enable + 3 + 1 + read-write + + + PDMA_SFTRST + Software Reset. +Write 1 to clear PDMA internal logic. +Write 0 to exit software reset mode. + 1 + 1 + read-write + + + PDMA_EN + 1b - Enabled + 0 + 1 + read-write + + + + + STAT + Status Register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + BLOCKY + Y block that is processing + 24 + 8 + read-only + + + BLOCKX + X block that is processing + 16 + 8 + read-only + + + PDMA_DONE + PDMA one image done + 9 + 1 + write-only + + + AXI_ERR_ID + AXI error ID + 5 + 4 + read-only + + + AXI_0_WRITE_ERR + AXI0 write err + 4 + 1 + write-only + + + AXI_1_READ_ERR + AXI1 read err + 3 + 1 + write-only + + + AXI_0_READ_ERR + AXI0 read err + 2 + 1 + write-only + + + IRQ + Asserted to indicate a IRQ event + 0 + 1 + read-only + + + + + OUT_CTRL + Out Layer Control Register + 0x8 + 32 + 0x00000000 + 0xFFFFFFBF + + + DSTALPHA + The destination (P1) system ALPHA value. + 24 + 8 + read-write + + + SRCALPHA + The source (P0) system ALPHA value. + 16 + 8 + read-write + + + DSTALPHA_OP + The usage of the DSTALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel embedded in the stream indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) +0: the DSTALPHA[7:0] is invalid, use the alpha value embedded in the stream +1: the DSTALPHA[7:0] is used to override the alpha value embedded in the stream. (useful when the corresponding data stream has no alpha info) +2: the DSTALPHA[7:0] is used to scale the alpha value embedded in the stream +3: don't multiply the color data with any alpha values for blender inputs. + 14 + 2 + read-write + + + SRCALPHA_OP + The usage of the SRCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel embedded in the stream indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) +0: the SRCALPHA[7:0] is invalid, use the alpha value embedded in the stream +1: the SRCALPHA[7:0] is used to override the alpha value embedded in the stream . (useful when the corresponding data stream has no alpha info) +2: the SRCALPHA[7:0] is used to scale the alpha value embedded in the stream +3: don't multiply the color data with any alpha values for blender inputs. + 12 + 2 + read-write + + + ABLEND_MODE + Alpha Blending Mode +0: SKBlendMode_Clear (If PS1_CTRL[BKGNDCL4CLR] is asserted, use PS1_BKGRND color to fill the range determined by PS1, else fill the range determined by PS1 with zero); +1: SKBlendMode_Src ; +2: SKBlendMode_Dst +3: SKBlendMode_SrcOver +4: SKBlendMode_DstOver +5: SKBlendMode_SrcIn +6: SKBlendMode_DstIn +7: SKBlendMode_SrcOut +8: SKBlendMode_DstOut +9: SKBlendMode_SrcATop +10: SKBlendMode_DstATop +11: SKBlendMode_Xor +12: SKBlendMode_Plus (The conventional belding mode) +13: SKBlendMode_Modulate +14: SRC org +15: DST org +Others: Reserved. + 8 + 4 + read-write + + + NORM_OUT + Asserted to normalize the output color channels with alpha channels + 7 + 1 + read-write + + + FORMAT + Output buffer format. +0x0 ARGB8888 - 32-bit pixles, byte sequence as B,G,R,A +0xE RGB565 - 16-bit pixels, byte sequence as B,R +0x12 UYVY1P422 - 16-bit pixels (1-plane , byte sequence as U0,Y0,V0,Y1) + 0 + 6 + read-write + + + + + OUT_BUF + Output buffer address + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + Current address pointer for the output frame buffer. The address can have any byte alignment. 64B alignment is recommended for optimal performance. + 0 + 32 + read-write + + + + + OUT_PITCH + Outlayer Pitch Register + 0x14 + 32 + 0x00000000 + 0x0000FFFF + + + BYTELEN + Indicates the number of bytes in memory between two vertically adjacent pixels. + 0 + 16 + read-write + + + + + OUT_LRC + Output Lower Right Corner Register + 0x18 + 32 + 0x00000000 + 0x3FFF3FFF + + + Y + This field indicates the lower right Y-coordinate (in pixels) of the output frame buffer. +The value is the height of the output image size. + 16 + 14 + read-write + + + X + This field indicates the lower right X-coordinate (in pixels) of the output frame buffer. +Should be the width of the output image size. + 0 + 14 + read-write + + + + + 2 + 0x8 + 0,1 + OUT_PS[%s] + no description available + 0x1c + + ULC + Layer Upper Left Corner Register + 0x0 + 32 + 0x00000000 + 0x3FFF3FFF + + + Y + This field indicates the upper left Y-coordinate (in pixels) of the processed surface in the output frame buffer. + 16 + 14 + read-write + + + X + This field indicates the upper left X-coordinate (in pixels) of the processed surface in the output frame buffer. + 0 + 14 + read-write + + + + + LRC + Layer Lower Right Corner Register + 0x4 + 32 + 0x00000000 + 0x3FFF3FFF + + + Y + This field indicates the lower right Y-coordinate (in pixels) of the processed surface in the output frame buffer. + 16 + 14 + read-write + + + X + This field indicates the lower right X-coordinate (in pixels) of the processed surface in the output frame buffer. + 0 + 14 + read-write + + + + + + 2 + 0x30 + 0,1 + PS[%s] + no description available + 0x30 + + CTRL + Layer Control Register + 0x0 + 32 + 0x00000000 + 0x011FFFFF + + + PL_ONLY_BLENDOP + 1: For those pixels that are this plane-only, use the colcor values and alpha values directly as blender output for un-normalized outputs configurations. +0: For those pixels that are this plane-only, the operations are determined by other operation configurations. + 24 + 1 + read-write + + + INB13_SWAP + Swap bit[31:24] and bit [15:8] before pack_dir operation. + 20 + 1 + read-write + + + PACK_DIR + Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence ina byte is not changed. +2'b00: no change {A3, A2, A1, A0} +2'b01: {A2, A3, A0, A1} +2'b10: {A1, A0, A3, A2} +2'b11: {A0, A1, A2, A3} + 18 + 2 + read-write + + + BKGCL4CLR + Enable to use background color for clear area + 17 + 1 + read-write + + + YCBCR_MODE + YCbCr mode or YUV mode + 16 + 1 + read-write + + + BYPASS + Asserted to bypass the CSC stage + 15 + 1 + read-write + + + VFLIP + Indicates that the input should be flipped vertically (effect applied before rotation). + 14 + 1 + read-write + + + HFLIP + Indicates that the input should be flipped horizontally (effect applied before rotation). + 13 + 1 + read-write + + + ROTATE + Indicates the clockwise rotation to be applied at the input buffer. The rotation effect is defined as occurring +after the FLIP_X and FLIP_Y permutation. +0x0 ROT_0 +0x1 ROT_90 +0x2 ROT_180 +0x3 ROT_270 + 11 + 2 + read-write + + + DECY + Verticle pre decimation filter control. +0x0 DISABLE - Disable pre-decimation filter. +0x1 DECY2 - Decimate PS by 2. +0x2 DECY4 - Decimate PS by 4. +0x3 DECY8 - Decimate PS by 8. + 9 + 2 + read-write + + + DECX + Horizontal pre decimation filter control. +0x0 DISABLE - Disable pre-decimation filter. +0x1 DECX2 - Decimate PS by 2. +0x2 DECX4 - Decimate PS by 4. +0x3 DECX8 - Decimate PS by 8. + 7 + 2 + read-write + + + HW_BYTE_SWAP + Swap bytes in half-words. For each 16 bit half-word, the two bytes will be swapped. + 6 + 1 + read-write + + + FORMAT + PS buffer format. To select between YUV and YCbCr formats, see bit 16 of this register. +0x0 ARGB888 - 32-bit pixels, byte sequence as B,G,R,A +0xE RGB565 - 16-bit pixels, byte sequence as B,R +0x13 YUYV1P422 - 16-bit pixels (1-plane byte sequence Y0,U0,Y1,V0 interleaved bytes) + 0 + 6 + read-write + + + + + BUF + Layer data buffer address + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + Address pointer for the PS RGB or Y (luma) input buffer. + 0 + 32 + read-write + + + + + PITCH + Layer data pitch register + 0x10 + 32 + 0x00000000 + 0x0000FFFF + + + BYTELEN + Indicates the number of bytes in memory between two vertically adjacent pixels. + 0 + 16 + read-write + + + + + BKGD + Layer background color register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + COLOR + Background color (in 32bpp format) for any pixels not within the scaled range of the picture, but within the buffer range specified by the PS ULC/LRC. The top 8-bit is the alpha channel. + 0 + 32 + read-write + + + + + SCALE + Layer scale register + 0x18 + 32 + 0x00000000 + 0x7FFF7FFF + + + Y + This is a two bit integer and 12 bit fractional representation (##.####_####_####) of the X scaling factor for the PS source buffer. The maximum value programmed should be 2 since scaling down by a factor greater than 2 is not supported with the bilinear filter. Decimation and the bilinear filter should be used together to achieve scaling by more than a factor of 2. + 16 + 15 + read-write + + + X + This is a two bit integer and 12 bit fractional representation (##.####_####_####) of the Y scaling factor for the PS source buffer. The maximum value programmed should be 2 since scaling down by a factor greater than 2 is not supported with the bilinear filter. Decimation and the bilinear filter should be used together to achieve scaling by more than a factor of 2. + 0 + 15 + read-write + + + + + OFFSET + Layer offset register + 0x1c + 32 + 0x00000000 + 0x0FFF0FFF + + + Y + This is a 12 bit fractional representation (0.####_####_####) of the Y scaling offset. This represents a fixed pixel offset which gets added to the scaled address to determine source data for the scaling engine. +It is applied after the decimation filter stage, and before the bilinear filter stage. + 16 + 12 + read-write + + + X + This is a 12 bit fractional representation (0.####_####_####) of the X scaling offset. This represents a fixed pixel offset which gets added to the scaled address to determine source data for the scaling engine. +It is applied after the decimation filter stage, and before the bilinear filter stage. + 0 + 12 + read-write + + + + + CLRKEY_LOW + Layer low color key register + 0x20 + 32 + 0x00000000 + 0x00FFFFFF + + + LIMIT + Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. + 0 + 24 + read-write + + + + + CLRKEY_HIGH + Layer high color key register + 0x24 + 32 + 0x00000000 + 0x00FFFFFF + + + LIMIT + High range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000 + 0 + 24 + read-write + + + + + ORG + Layer original size register + 0x28 + 32 + 0x00000000 + 0x3FFF3FFF + + + HIGHT + The number of vertical pixels of the original frame (not -1) + 16 + 14 + read-write + + + WIDTH + The number of horizontal pixels of the original frame (not -1) + 0 + 14 + read-write + + + + + + YUV2RGB_COEF0 + YUV2RGB coefficients register 0 + 0xa0 + 32 + 0x00000000 + 0x1FFFFFFF + + + C0 + Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) + 18 + 11 + read-write + + + UV_OFFSET + Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. +YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). + 9 + 9 + read-write + + + Y_OFFSET + Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is +typically -16 (0x1F0). + 0 + 9 + read-write + + + + + YUV2RGB_COEF1 + YUV2RGB coefficients register 1 + 0xa4 + 32 + 0x00000000 + 0x07FF07FF + + + C1 + Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). + 16 + 11 + read-write + + + C4 + Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). + 0 + 11 + read-write + + + + + YUV2RGB_COEF2 + YUV2RGB coefficients register 2 + 0xa8 + 32 + 0x00000000 + 0x07FF07FF + + + C2 + Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). + 16 + 11 + read-write + + + C3 + Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). + 0 + 11 + read-write + + + + + RGB2YUV_COEF0 + RGB2YUV coefficients register 0 + 0xac + 32 + 0x00000000 + 0xFFFFFFFF + + + YCBCR_MODE + Asserted to use YCrCb mode + 31 + 1 + read-write + + + ENABLE + Asserted to enable this RGB2YUV CSC stage + 30 + 1 + read-write + + + C0 + CSC parameters C0 + 18 + 11 + read-write + + + UV_OFFSET + CSC parameters UV_OFFSET + 9 + 9 + read-write + + + Y_OFFSET + CSC parameters Y_OFFSET + 0 + 9 + read-write + + + + + RGB2YUV_COEF1 + RGB2YUV coefficients register 1 + 0xb0 + 32 + 0x00000000 + 0x07FF07FF + + + C1 + CSC parameters C1 + 16 + 11 + read-write + + + C4 + CSC parameters C4 + 0 + 11 + read-write + + + + + RGB2YUV_COEF2 + RGB2YUV coefficients register 2 + 0xb4 + 32 + 0x00000000 + 0x07FF07FF + + + C2 + CSC parameters C2 + 16 + 11 + read-write + + + C3 + CSC parameters C3 + 0 + 11 + read-write + + + + + RGB2YUV_COEF3 + RGB2YUV coefficients register 3 + 0xb8 + 32 + 0x00000000 + 0x07FF07FF + + + C6 + CSC parameters C6 + 16 + 11 + read-write + + + C5 + CSC parameters C5 + 0 + 11 + read-write + + + + + RGB2YUV_COEF4 + RGB2YUV coefficients register 4 + 0xbc + 32 + 0x00000000 + 0x07FF07FF + + + C8 + CSC parameters C8 + 16 + 11 + read-write + + + C7 + CSC parameters C7 + 0 + 11 + read-write + + + + + + + JPEG + JPEG + JPEG + 0xf1014000 + + 0x0 + 0xa0 + registers + + + + InDMA_MISC + In DMA Misc Control Register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFC + + + ARQOS + QoS for AXI read channel + 19 + 4 + read-write + + + MAX_OT + max_ot when input are RGB pixels. +For 16 bits per pixel, it can be set as 4. +For 32 bits per pixel, it will be set as 2. + 15 + 4 + read-write + + + INB13_SWAP + Swap bit[31:24] and bit [15:8] before pack dir operation. Only work for pixel data. + 14 + 1 + read-write + + + PACK_DIR + Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence in a byte is not changed. Only work for pixel data. +2'b00: no change {A3, A2, A1, A0} +2'b01: {A2, A3, A0, A1} +2'b10: {A1, A0, A3, A2} +2'b11: {A0, A1, A2, A3} + 12 + 2 + read-write + + + INDMA_RENEW + Renew In DMA. Default is to continue the write address counter when a new DMA request comes. Asserted to reset the write address counter. + 11 + 1 + read-write + + + NXT_IRQ_EN + In DMA Next Interrupt Enable + 10 + 1 + read-write + + + IN_DMA_DONE_IRQ_EN + In DMA Done enable + 9 + 1 + read-write + + + AXI_ERR_IRQ_EN + In DMA axi bus error inetrrupt enable + 8 + 1 + read-write + + + IRQ_EN + interrupt enable for all interrupt sources of In DMA module + 7 + 1 + read-write + + + IN_DMA_ID + 0: Pixel (In) +1: ECS (In) +2: Qmem +3: HuffEnc +4: HuffMin +5: HuffBase +6: HuffSymb + 4 + 3 + read-write + + + IN_DMA_REQ + Asserted to request DMA. Automatically clear after DMA is done. + 3 + 1 + read-write + + + INDMA2D + Asserted if In_DMA_ID=Pixel. + 2 + 1 + read-write + + + + + InDMABase + In DMA Buf Address + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + Y plane (or Encoded Bit Plane) + 0 + 32 + read-write + + + + + InDMA_Ctrl0 + In DMA Buf Control 0 Register + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + TTLEN + Total length (Low 16 bits) in Bytes -1 for transfer when In_DMA_ID!=Pixel. + 16 + 16 + read-write + + + PITCH + Pitch between the starting point of Rows. Only active when In_DMA_ID=Pixel.. + 0 + 16 + read-write + + + + + InDMA_Ctrl1 + In DMA Buf Control 1 Register + 0x10 + 32 + 0x00000000 + 0x0000FFFF + + + ROWLEN + Total length (High 16 bits) in Bytes -1 for transfer. See reference in InDMA_Ctrl0[TTLEN] + 0 + 16 + read-write + + + + + INXT_CMD + In DMA Next Command Register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + The address pointing to the next command + 2 + 30 + read-write + + + OP_VALID + asserted if there is either a DATA DMA phase or NXTCMD phase. Automatically cleared. Will trigger the InDMA transfer if CFG[JPEG_EN] is 1. + 1 + 1 + read-write + + + EN + NXTCMD phase Enable Bit + 0 + 1 + read-write + + + + + OutDMA_MISC + Out DMA Misc Control Register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFC + + + AWQOS + No description available + 14 + 4 + read-write + + + PACK_DIR + Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence in a byte is not changed. All outdma data are impacted. +2'b00: no change {A3, A2, A1, A0} (This is used for ecs stream) +2'b01: {A2, A3, A0, A1} +2'b10: {A1, A0, A3, A2} +2'b11: {A0, A1, A2, A3} + 12 + 2 + read-write + + + EN_OUTCNT + Enable output counter (unit as bytes) + 11 + 1 + read-write + + + INI_OUTCNT + Asserted to ini output counter + 10 + 1 + read-write + + + ADD_ODMA_ENDINGS + Add 0xFFD9 to the ending of the odma stream when all original image pixels are processed by the encoder module. + 9 + 1 + read-write + + + NXT_IRQ_EN + Out DMA Next Interrupt Enable + 8 + 1 + read-write + + + OUT_DMA_DONE_IRQ_EN + Out DMA Done interrupt Enable + 7 + 1 + read-write + + + AXI_ERR_IRQ_EN + Out DMA axi bus error inetrrupt enable + 6 + 1 + read-write + + + IRQ_EN + interrupt enable for all interrupt sources of Out DMA module + 5 + 1 + read-write + + + OUT_DMA_ID + 0: Pixel (Out) +1: ECS (Out) + 4 + 1 + read-write + + + OUT_DMA_REQ + Asserted to enable Out DMA request + 3 + 1 + read-write + + + OUTDMA2D + Asserted if Out_DMA_ID==Pixel + 2 + 1 + read-write + + + + + OutDMABase + Out DMA Buf Address + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + Y plane (or Encoded Bit Plane) + 0 + 32 + read-write + + + + + OutDMA_Ctrl0 + Out DMA Buf Control 0 Register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + TTLEN + Total length (Low 16 bits) in Bytes -1 for transfer when Out_DMA_ID!=Pixel. If Out_DMA_ID=ECS, it can be any value greater than the length of the ECS, for example, the number of encoded bytes. + 16 + 16 + read-write + + + PITCH + Pitch between the starting point of Rows when Out_DMA_ID==Pixel + 0 + 16 + read-write + + + + + OutDMA_Ctrl1 + Out DMA Buf Control 1 Register + 0x30 + 32 + 0x00000000 + 0x0000FFFF + + + ROWLEN + Total length (High 16 bits) in Bytes -1 for transfer. See reference in OutDMA_Ctrl0[TTLEN] + 0 + 16 + read-write + + + + + ONXT_CMD + Out DMA Next Command Register + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + The address pointing to the next command + 2 + 30 + read-write + + + OP_VALID + asserted if there is either a DATA DMA phase or NXTCMD phase. Automatically cleared. Will trigger the OutDMA and NXTCMD phase transfer if CFG[JPEG_EN] is 1. + 1 + 1 + read-write + + + EN + NXTCMD phase Enable Bit + 0 + 1 + read-write + + + + + CFG + Configuration Register + 0x40 + 32 + 0x00000000 + 0xFFFFFFFF + + + JD_UVSWAP + Normally the default CbCr sequence is that Cb macro block coming before Cr macro blk. If Cr macro block is first, set this bit to 1'b1. This bit only impact the color space conversion from/to RGB. + 22 + 1 + read-write + + + CFG_IPATH_SEL + 2'b0:2-plane (Y- and UV- plane) or 1-plane (Y-only) as determined by the original data, byte sequence as Y0,Y1, or U,V +2'b01:ARGB8888, byte sequence as B,G,R,A +2'b10:RGB565, byte sequence as B,R +2'b11: YUV422H, byte sequence as Y0,U0,Y1,V0 + 20 + 2 + read-write + + + CODEC_OVER_IRQ_EN + The jpg endec process done interrupt enable + 19 + 1 + read-write + + + CODEC_RESTART_ERR_IRQ_EN + The jpg endec restart error interrupt enable + 18 + 1 + read-write + + + MEM_DEBUG_CLK_SEL + asserted to use APB clock, so that the memory contents could be read out through APB interface + 17 + 1 + read-write + + + CLKGATE + Assert this bit to gate off clock when the module is not working. If reset to zero, the internal clock is always on. + 9 + 1 + read-write + + + CFG_OPATH_SEL + 2'b0:2-plane (Y- and UV- plane) or 1-plane (Y-only) as determined by the original data, byte sequence as Y0,Y1, or U,V +2'b01:ARGB8888, byte sequence as B,G,R,A +2'b10:RGB565, byte sequence as R,B +2'b11: YUV422H1P, byte sequence as Y0,U0,Y1,V0 + 7 + 2 + read-write + + + JDATA_FORMAT + 3'b000: for 420, hy=2, vy=2, hc=1, vc=1 // 6 sub-blocks per MCU +3'b001: for 422h, hy=2, vy=1, hc=1, vc=1 // 4 sub-blocks per MCU +3'b010: for 422v, hy=1, vy=2, hc=1, vc=1 // 4 sub-blocks per MCU +3'b011: for 444, hy=1, vy=1, hc=1, vc=1 // 3 sub-blocks per MCU +3'b100: for 400, hy=2, vy=2, hc=0, vc=0 // 4 sub-blocks per MCU +Others: Undefined + 4 + 3 + read-write + + + JPEG_SFTRST + Software Reset + 3 + 1 + read-write + + + START + Asserted if to start a new encoder/decoder conversion. +It will at first stop the inner JPEG module, then reset it, and then re-run it. +It is a different mode from DMA phase mode. +It cannot be configured in the DMA chain descriptor. It should be configured by the core processor. +Auto clear. + 2 + 1 + read-write + + + MODE + 1: decoder, 0:encoder + 1 + 1 + read-write + + + JPEG_EN + 1b - Enabled + 0 + 1 + read-write + + + + + STAT + Status Register + 0x44 + 32 + 0x00000000 + 0xFFFFBFFE + + + BUSY + When 1 means that the module is busy doing conversion and data transfer. + 31 + 1 + read-only + + + AXI_ERR_ID + the axi err id + 10 + 4 + read-only + + + AXI_READ_ERR + in-dma axi bus error + 9 + 1 + read-only + + + AXI_WRITE_ERR + out-dma axi bus error + 8 + 1 + read-only + + + AXI_ERR + axi bus error + 7 + 1 + write-only + + + ONXT_IRQ + OutDMA next interrupt + 6 + 1 + write-only + + + INXT_IRQ + InDMA next interrupt + 5 + 1 + write-only + + + OUT_DMA_TRANSFER_DONE + OutDMA process done + 4 + 1 + write-only + + + IN_DMA_TRANSFER_DONE + InDMA process done + 3 + 1 + write-only + + + CODEC_OVER + Coding or decoding process is over. DMA is not included. +The module is completely not busy only when in_dma_transfer_done and out_dma_transfer_done, and codec_over are all asserted. + 2 + 1 + write-only + + + RESTART_MARKER_ERROR + codec restart marker error interrupt + 1 + 1 + write-only + + + + + Width + Image width register + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + IMG + Image Width (it is the max index of pixel counting from 0, assuming the top left pixel is indexed as [0,0]) + 0 + 16 + read-write + + + + + Height + Image height register + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + IMG + Image Height (it is the max index of pixel counting from 0, assuming the top left pixel is indexed as [0,0]) + 0 + 16 + read-write + + + + + BufAddr + Buf Access Addr + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + ADDR[31:28] denotes the buffer type: +0x2: Qmem +0x3: HuffEnc +0x4: HuffMin +0x5: HuffBase +0x6: HuffSymb +ADDR[27:0] is the address inside the buffer + 0 + 32 + read-write + + + + + BufData + Buf Access Data + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + The data write-to/read-from buffer. +The n-th address read will be actually the data written for n-1 th address, and the actual stored location is n-1 th address. + 0 + 32 + read-write + + + + + OutDMACnt + Out DMA Bytes Counter + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + The out DMA counter + 0 + 32 + read-only + + + + + CSC_COEF0 + YUV2RGB coefficients Register 0 + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + YCBCR_MODE + This bit changes the behavior when performing U/V converting. +0b - Converting YUV to RGB data +1b - Converting YCbCr to RGB data + 31 + 1 + read-write + + + ENABLE + Enable the CSC unit. +0b - The CSC is bypassed +1b - The CSC is enabled + 30 + 1 + read-write + + + C0 + Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) + 18 + 11 + read-write + + + UV_OFFSET + Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. +YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). + 9 + 9 + read-write + + + Y_OFFSET + Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is +typically -16 (0x1F0). + 0 + 9 + read-write + + + + + CSC_COEF1 + YUV2RGB coefficients Register 1 + 0x60 + 32 + 0x00000000 + 0xFFFFFFFF + + + C1 + Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). + 16 + 11 + read-write + + + C4 + Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). + 0 + 11 + read-write + + + + + CSC_COEF2 + YUV2RGB coefficients Register 2 + 0x64 + 32 + 0x00000000 + 0xFFFFFFFF + + + C2 + Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). + 16 + 11 + read-write + + + C3 + Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). + 0 + 11 + read-write + + + + + RGB2YUV_COEF0 + RGB2YUV coefficients Register 0 + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + YCBCR_MODE + Asserted to use YCrCb mode. Must be assigned as 1. + 31 + 1 + read-write + + + ENABLE + Asserted to enable this RGB2YCbCr CSC stage + 30 + 1 + read-write + + + C0 + CSC parameters C0 + 18 + 11 + read-write + + + UV_OFFSET + CSC parameters UV_OFFSET + 9 + 9 + read-write + + + Y_OFFSET + CSC parameters Y_OFFSET + 0 + 9 + read-write + + + + + RGB2YUV_COEF1 + RGB2YUV coefficients Register 1 + 0x6c + 32 + 0x00000000 + 0xFFFFFFFF + + + C1 + CSC parameters C1 + 16 + 11 + read-write + + + C4 + CSC parameters C4 + 0 + 11 + read-write + + + + + RGB2YUV_COEF2 + RGB2YUV coefficients Register 2 + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + C2 + CSC parameters C2 + 16 + 11 + read-write + + + C3 + CSC parameters C3 + 0 + 11 + read-write + + + + + RGB2YUV_COEF3 + RGB2YUV coefficients Register 3 + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + C6 + CSC parameters C6 + 16 + 11 + read-write + + + C5 + CSC parameters C5 + 0 + 11 + read-write + + + + + RGB2YUV_COEF4 + RGB2YUV coefficients Register 4 + 0x78 + 32 + 0x00000000 + 0xFFFFFFFF + + + C8 + CSC parameters C8 + 16 + 11 + read-write + + + C7 + CSC parameters C7 + 0 + 11 + read-write + + + + + ImgReg1 + Image Control Register 1 + 0x84 + 32 + 0x00000000 + 0xFFFFFFF7 + + + RE + Encoder Use only. +Asseted to enable the Restart Marker processing. A Restart Marker is inserted in the outputted ECS (Entropy Coded Segment) every NRST+1 MCUs + 2 + 1 + read-write + + + NCOL + Ncol is the number of color components in the image data to process minus 1. For example, for a grayscale image Ncol=0, for an RGB image, Ncol=2 + 0 + 2 + read-write + + + + + ImgReg2 + Image Control Register 2 + 0x88 + 32 + 0x00000000 + 0xFFFFFFFF + + + NMCU + Encoder Use only. +The number of NMCU to be generated in encoder mode + 0 + 26 + read-write + + + + + ImgReg3 + Image Control Register 3 + 0x8c + 32 + 0x00000000 + 0xFFFFFFFF + + + NRST + Encoder use only. +It is the number of MCUs between two Restart Markers (if enabled) minus 1. The content of this register is ignored if the Re bit inregister 1 is not set. + 0 + 16 + read-write + + + + + 4 + 0x4 + Reg40,Reg41,Reg42,Reg43 + IMGREG[%s] + no description available + 0x90 + 32 + 0x00000000 + 0xFFFFFFFF + + + NBLOCK + Encoder use only. +The number of data units (8x8 blocks of data) of the color componet contained in the MCU minus 1. + 4 + 4 + read-write + + + QT + Encoder use only. +The selection of the quantization table. + 2 + 2 + read-write + + + HA + Encoder use only. +The selection of the Huffman table for the encoding of the AC coefficients in the data units belonging to the color component. + 1 + 1 + read-write + + + HD + Encoder use only. +The selection of the Huffman table for the encoding of the DC coefficients in the data units belonging to the color component. + 0 + 1 + read-write + + + + + + + GWC0 + GWC0 + GWC + 0xf1018000 + + 0x0 + 0x1f0 + registers + + + + glb_ctrl + control reg + 0x0 + 32 + 0x00000000 + 0x00000081 + + + CLK_POL + graphic clock polarity. +set to invert input graphic clock + 7 + 1 + read-write + + + GWC_EN + graphic window check enable. +set to enable the whole block + 0 + 1 + read-write + + + + + irq_mask + interrupt enable + 0x4 + 32 + 0x00000000 + 0x0000000B + + + MASK_RREEZ + freeze mask, set to disable changing ERR_MASK and FUNC_MASK. +can only be cleared by system reset + 3 + 1 + read-write + + + FUNC_MASK + function interrupt mask + 1 + 1 + read-write + + + ERR_MASK + error interrupt mask + 0 + 1 + read-write + + + + + irq_sts + interrupt status + 0x8 + 32 + 0x00000000 + 0x0003FFFF + + + FUNC_STS + function interrupt status. +it's set when detect two VSYNC signals after the block is enabled(GWC_EN is set) +software write 1 to clear. + 17 + 1 + write-only + + + ERR_STS + error status, it's OR of GWC_FAIL_STS[15:0] + 16 + 1 + read-only + + + GWC_FAIL_STS + graphic window check fail interrupt status. +will be set if the calculated CRC not equal reference CRC. +one bit for each channel. +software write 1 to clear. + 0 + 16 + write-only + + + + + 2 + 0xf0 + ch0,ch15 + CHANNEL[%s] + no description available + 0x10 + + cfg0 + config reg 0 + 0x0 + 32 + 0x00000000 + 0xCFFF1FFF + + + ENABLE + channel enable + 31 + 1 + read-write + + + FREEZE + freeze config. set to freeze all other config registers for current channel. +can only be cleared by system reset + 30 + 1 + read-write + + + START_ROW + define the window start row number + 16 + 12 + read-write + + + START_COL + define the window start column number + 0 + 13 + read-write + + + + + cfg1 + config reg 1 + 0x4 + 32 + 0x00000000 + 0x0FFF1FFF + + + END_ROW + define the window end row number + 16 + 12 + read-write + + + END_COL + define the window end column number + 0 + 13 + read-write + + + + + refcrc + reference CRC + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + REF_CRC + reference CRC +polynomial function: 0x104C11DB7 + 0 + 32 + read-write + + + + + calcrc + calculated CRC + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + CAL_CRC + calculated CRC for last frame + 0 + 32 + read-write + + + + + + + + GWC1 + GWC1 + GWC + 0xf101c000 + + + MIPI_DSI0 + MIPI_DSI0 + MIPI_DSI + 0xf1020000 + + 0x0 + 0x194 + registers + + + + version + version + 0x0 + 32 + 0x3134302A + 0xFFFFFFFF + + + VERSION + version of DSI + 0 + 32 + read-only + + + + + pwr_up + power up + 0x4 + 32 + 0x00000000 + 0x00000001 + + + SHUTDOWNZ + 0x0: reset the core +0x1: power up the core + 0 + 1 + read-write + + + + + clkmgr_cfg + divide lanebyteclk for timeout + 0x8 + 32 + 0x00000000 + 0x0000FFFF + + + TO_CLK_DIVISION + the timeout clock division factor for HS to LP and LP to HS transition error + 8 + 8 + read-write + + + TX_ESC_CLK_DIVISION + the division factor for the TX Escape clock source lanebyteclk + 0 + 8 + read-write + + + + + dpi_vcid + virtual channel ID for DPI traffic + 0xc + 32 + 0x00000000 + 0x00000003 + + + DPI_VCID + the DPI virtual channel id to the video mode packets + 0 + 2 + read-write + + + + + dpi_color_coding + dpi color coding + 0x10 + 32 + 0x00000000 + 0x0000010F + + + LOOSELY18_EN + when set to 1, this bit activates loosely packed variant to 18-bit configurations + 8 + 1 + read-write + + + DPI_COLOR_CODING + configures the DPI color for video mode + 0 + 4 + read-write + + + + + dpi_cfg_pol + the polarity of DPI signals + 0x14 + 32 + 0x00000000 + 0x0000001F + + + COLORM_ACTIVE_LOW + configures the color mode pin as active low + 4 + 1 + read-write + + + SHUTD_ACTIVE_LOW + configures the shutdown pin as active low + 3 + 1 + read-write + + + HSYNC_ACTIVE_LOW + configures the horizontal synchronism pin as active low + 2 + 1 + read-write + + + VSYNC_ACTIVE_LOW + configures the vertical synchronism pin as active low + 1 + 1 + read-write + + + DATAEN_ACTIVE_LOW + configures the data enable pin active low + 0 + 1 + read-write + + + + + dpi_lp_cmd_tim + the timing for low-power commands sent while in video mode + 0x18 + 32 + 0x00000000 + 0x00FF00FF + + + OUTVACT_LPCMD_TIME + transmission of commands in low-power mode, defines the size in bytes of the largest pachet that can fit in a line during the VSA VBP and VFP; + 16 + 8 + read-write + + + INVACT_LPCMD_TIME + transmission of commands in low-power mode, defines the size in bytes of the largest packet that can fit in a line during the VACT region. + 0 + 8 + read-write + + + + + pckhdl_cfg + configures how EoTp, BTA, CRC and ECC to be used + 0x2c + 32 + 0x00000000 + 0x0000003F + + + EOTP_TX_LP_EN + enable the EoTp transmission in low-power + 5 + 1 + read-write + + + CRC_RX_EN + enable the crc reception and error reporting + 4 + 1 + read-write + + + ECC_RX_EN + enable the ecc reception error correction and reporting + 3 + 1 + read-write + + + BTA_EN + enable the bus turn-around request + 2 + 1 + read-write + + + EOTP_RX_EN + enable the EoTp reception + 1 + 1 + read-write + + + EOTP_TX_EN + enable the EoTp transmission in high-speed + 0 + 1 + read-write + + + + + gen_vcid + configures the virtual channel ID of read response to store and return to generic interface + 0x30 + 32 + 0x00000000 + 0x00030303 + + + GEN_VCID_TX_AUTO + indicates the generic interface virtual channel identification where generic packet is automatically generated and transmitted + 16 + 2 + read-write + + + GEN_VCID_TEAR_AUTO + indicates the virtual channel identification for tear effect by hardware + 8 + 2 + read-write + + + GEN_VCID_RX + indicates the generic interface read-back virtual channel identication + 0 + 2 + read-write + + + + + mode_cfg + configures the mode of operation between video or command mode + 0x34 + 32 + 0x00000001 + 0x00000001 + + + CMD_VIDEO_MODE + 0x0: video mode +0x1: command mode + 0 + 1 + read-write + + + + + vid_mode_cfg + several aspect of video mode operation + 0x38 + 32 + 0x00000000 + 0x0111FF03 + + + VPG_ORIENTATION + indicates the color bar orientation : +0x0: vertical mode +0x1: horizontal mode + 24 + 1 + read-write + + + VPG_MODE + 0x0: colorbar +0x1: berpattern, vertical only + 20 + 1 + read-write + + + VPG_EN + enable video mode pattern generator + 16 + 1 + read-write + + + LP_CMD_EN + enable command transmission only in low-power mode + 15 + 1 + read-write + + + FRAME_BTA_ACK_EN + enable the request for an acknowledge response at the end of a frame + 14 + 1 + read-write + + + LP_HFP_EN + enable the return to low-power inside the HFP period when timing allows + 13 + 1 + read-write + + + LP_HBP_EN + enable the return to low-power inside the HBP period when timing allows + 12 + 1 + read-write + + + LP_VACT_EN + enable the return to low-power inside the VACT period when timing allows + 11 + 1 + read-write + + + LP_VFP_EN + enable the return to low-power inside the VFP period when timing allows + 10 + 1 + read-write + + + LP_VBP_EN + enable the return to low-power inside the VBP period when timing allows + 9 + 1 + read-write + + + LP_VSA_EN + enable the return to low-power inside the VSA period when timing allows + 8 + 1 + read-write + + + VID_MODE_TYPE + indicates the video mode transmission type + 0 + 2 + read-write + + + + + vid_pkt_size + configures the video packet size + 0x3c + 32 + 0x00000000 + 0x00003FFF + + + VID_PKT_SIZE + configures the number of pixels in a single video packet + 0 + 14 + read-write + + + + + vid_num_chunks + configures the number of chunks to use + 0x40 + 32 + 0x00000000 + 0x00001FFF + + + VID_NUM_CHUNKS + configures the number of chunks to be transmitted a line period + 0 + 13 + read-write + + + + + vid_null_size + configures the size of null packets + 0x44 + 32 + 0x00000000 + 0x00001FFF + + + VID_NULL_SIZE + configures the number of bytes inside a null packet + 0 + 13 + read-write + + + + + vid_hsa_time + configures the video HAS time + 0x48 + 32 + 0x00000000 + 0x00000FFF + + + VID_HSA_TIME + configure the Horizontal synchronism active period in lane byte clock cycles + 0 + 12 + read-write + + + + + vid_hbp_time + configure the video HBP time + 0x4c + 32 + 0x00000000 + 0x00000FFF + + + VID_HPB_TIME + configures the Horizontal back porch period in lane byte clock cycles + 0 + 12 + read-write + + + + + vid_hline_time + configures the overall time for each video line + 0x50 + 32 + 0x00000000 + 0x00007FFF + + + VID_HLINE_TIME + configures the size of the total line time in lane byte clock cycles + 0 + 15 + read-write + + + + + vid_vsa_lines + configures the vsa period + 0x54 + 32 + 0x00000000 + 0x000003FF + + + VSA_LINES + configures the verical synchronism active period measured in number of horizontal lines + 0 + 10 + read-write + + + + + vid_vbp_lines + configures the vbp period + 0x58 + 32 + 0x00000000 + 0x000003FF + + + VBP_LINES + configures the vertical back porch period measured in number of horizontal lines + 0 + 10 + read-write + + + + + vid_vfp_lines + configures the vfp period + 0x5c + 32 + 0x00000000 + 0x000003FF + + + VFP_LINIES + configures the vertical front porch period measured in number of horizontal lines + 0 + 10 + read-write + + + + + vid_vactive_lines + configures the vertical resolution of video + 0x60 + 32 + 0x00000000 + 0x00003FFF + + + V_ACTIVE_LINES + configures the vertical active period measured in number of horizontal lines + 0 + 14 + read-write + + + + + CMD_MODE_CFG + This register configures several aspect of command mode operation, tearing effect, acknowledge for each packet and the speed mode to transmit each Data Type related to commands. + 0x68 + 32 + 0x00000000 + 0x010F7F03 + + + MAX_RD_PKT_SIZE + This bit configures the maximum read packet size command transmission type: +0x0 (HIGHSPEED): Transition type is High Speed +0x1 (LOWPOWER): Transition type is Low Power + 24 + 1 + read-write + + + DCS_LW_TX + This bit configures the DCS long write packet command transmission type: +0x0 (HIGHSPEED): Transition type is High Speed +0x1 (LOWPOWER): Transition type is Low Power + 19 + 1 + read-write + + + DCS_SR_0P_TX + This bit configures the DCS short read packet with zero parameter command transmission type: +0x0 (HIGHSPEED): Transition type is High Speed +0x1 (LOWPOWER): Transition type is Low Power + 18 + 1 + read-write + + + DCS_SW_1P_TX + This bit configures the DCS short write packet with one parameter command transmission type: +0x0 (HIGHSPEED): Transition type is High Speed +0x1 (LOWPOWER): Transition type is Low Power + 17 + 1 + read-write + + + DCS_SW_0P_TX + This bit configures the DCS short write packet with zero parameter command transmission type: +0x0 (HIGHSPEED): Transition type is High Speed +0x1 (LOWPOWER): Transition type is Low Power + 16 + 1 + read-write + + + GEN_LW_TX + This bit configures the Generic long write packet command transmission type: +0x0 (HIGHSPEED): Transition type is High Speed +0x1 (LOWPOWER): Transition type is Low Power + 14 + 1 + read-write + + + GEN_SR_2P_TX + This bit configures the Generic short read packet with two parameters command transmission type: +0x0 (HIGHSPEED): Transition type is High Speed +0x1 (LOWPOWER): Transition type is Low Power + 13 + 1 + read-write + + + GEN_SR_1P_TX + This bit configures the Generic short read packet with two parameters command transmission type: +0x0 (HIGHSPEED): Transition type is High Speed +0x1 (LOWPOWER): Transition type is Low Power + 12 + 1 + read-write + + + GEN_SR_0P_TX + This bit configures the Generic short read packet with two parameters command transmission type: +0x0 (HIGHSPEED): Transition type is High Speed +0x1 (LOWPOWER): Transition type is Low Power + 11 + 1 + read-write + + + GEN_SW_2P_TX + This bit configures the Generic short read packet with two parameters command transmission type: +0x0 (HIGHSPEED): Transition type is High Speed +0x1 (LOWPOWER): Transition type is Low Power + 10 + 1 + read-write + + + GEN_SW_1P_TX + This bit configures the Generic short read packet with two parameters command transmission type: +0x0 (HIGHSPEED): Transition type is High Speed +0x1 (LOWPOWER): Transition type is Low Power + 9 + 1 + read-write + + + GEN_SW_0P_TX + This bit configures the Generic short read packet with two parameters command transmission type: +0x0 (HIGHSPEED): Transition type is High Speed +0x1 (LOWPOWER): Transition type is Low Power + 8 + 1 + read-write + + + ACK_RQST_EN + When set to 1, this bit enables the acknowledge request after each packet transmission. + 1 + 1 + read-write + + + TEAR_FX_EN + When set to 1, this bit enables the tearing effect acknowledge request. + 0 + 1 + read-write + + + + + gen_hdr + sets the header for new packets sent using the generic interface + 0x6c + 32 + 0x00000000 + 0x00FFFFFF + + + GEN_WC_MSBYTE + configures the most significant byte of the header packet's word count for long packets or data 1 for shout packets + 16 + 8 + read-write + + + GEN_WC_LSBYTE + configures the least significant byte of the header packet's word count for long packets or data0 for short packets + 8 + 8 + read-write + + + GEN_VC + configures the virtual channel ID of the header packet + 6 + 2 + read-write + + + GEN_DT + configures the packet data type of the header packet + 0 + 6 + read-write + + + + + gen_pld_data + sets the payload for packets sent using the generic interface + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + GEN_PLD_B4 + indicates byte4 of the packet payload + 24 + 8 + read-write + + + GEN_PLD_B3 + indicates byte3 of the packet payload + 16 + 8 + read-write + + + GEN_PLD_B2 + indicates byte2 of the packet payload + 8 + 8 + read-write + + + GEN_PLD_B1 + indicates byte1 of the packet payload + 0 + 8 + read-write + + + + + cmd_pkt_status + information about the status of FIFOs related to DBI and Generic interface + 0x74 + 32 + 0x00000000 + 0x000F007F + + + GEN_BUFF_PLD_FULL + the full status of the generic payload internal buffer + 19 + 1 + read-only + + + GEN_BUFF_PLD_EMPTY + the empty status of the generic payload internal buffer + 18 + 1 + read-only + + + GEN_BUFF_CMD_FULL + the full status of the generic command internal buffer + 17 + 1 + read-only + + + GEN_BUFF_CMD_EMPTY + the empty status of the generic command internal buffer + 16 + 1 + read-only + + + GEN_RD_CMD_BUSY + indicates a read command is issued and the entire response is not sotred in the FIFO + 6 + 1 + read-only + + + GEN_PLD_R_FULL + indicates the full status of the generic read payoad FIFO + 5 + 1 + read-only + + + GEN_PLD_R_EMPTY + indicates the empty status of the generic read payload FIFO + 4 + 1 + read-only + + + GEN_PLD_W_FULL + indicates the full status of the generic write payload FIFO + 3 + 1 + read-only + + + GEN_PLD_W_EMPTY + indicates the empty status of the generic write payload FIFO + 2 + 1 + read-only + + + GEN_CMD_FULL + indicates the full status of the generic command FIFO + 1 + 1 + read-only + + + GEN_CMD_EMPTY + indicates the empty status of the generic command FIFO + 0 + 1 + read-only + + + + + to_cnt_cfg + configures the trigger timeout errors + 0x78 + 32 + 0x00000000 + 0xFFFFFFFF + + + HSTX_TO_CNT + configures the timeout counter that triggers a high speed transmission timeout contention detection + 16 + 16 + read-write + + + LPRX_TO_CNT + configures the timeout counter that triggers a low power reception timeout contention detection + 0 + 16 + read-write + + + + + hs_rd_to_cnt + configures the peripheral response timeout after high speed read operations + 0x7c + 32 + 0x00000000 + 0x0000FFFF + + + HS_RD_TO_CNT + sets a period for which DWC_mipi_dsi_host keeps the link still after sending a high speed read operation; + 0 + 16 + read-write + + + + + lp_rd_to_cnt + configures the peripheral response timeout after low-power read operation + 0x80 + 32 + 0x00000000 + 0x0000FFFF + + + LP_RD_TO_CNT + sets a period for which dwc_mipi_dsi_host keeps the link still after sending a low power read operation + 0 + 16 + read-write + + + + + hs_wr_to_cnt + configures the peripheral response timeout after high speed write operations + 0x84 + 32 + 0x00000000 + 0x0000FFFF + + + HS_WR_TO_CNT + sets the period for which dwc_mipi_dsi_host keeps the link still after sending a high speed write operation + 0 + 16 + read-write + + + + + lp_wr_to_cnt + configures the peripheral response timeout after low power write operations + 0x88 + 32 + 0x00000000 + 0x0000FFFF + + + LP_WR_TO_CNT + sets the period for which dsi host keeps the link still after sending a low power write operation + 0 + 16 + read-write + + + + + bta_to_cnt + configures the periphera response timeout after bus turnaround + 0x8c + 32 + 0x00000000 + 0x0000FFFF + + + BTA_TO_CNT + sets the period for which dsi host keeps the link still after completing a bus turnaround. + 0 + 16 + read-write + + + + + sdf_3d + sotres 3d control information for vss packets in video mode + 0x90 + 32 + 0x00000000 + 0x0001003F + + + SEND_3D_CFG + set the next vss packet to include 3d control payload in every vss packet + 16 + 1 + read-write + + + RIGHT_FIRST + 0x0: left eye is sent first +0x1:right eye is sent first + 5 + 1 + read-write + + + SECOND_VSYNC + defines whether there is a second VSYNC pulse + 4 + 1 + read-write + + + FORMAT_3D + defines 3D image format + 2 + 2 + read-write + + + MODE_3D + defines 3D mode on/off + 0 + 2 + read-write + + + + + lpclk_ctrl + configures the possibility for using non continuous clock in the clock lane + 0x94 + 32 + 0x00000000 + 0x00000003 + + + AUTO_CLKLANE_CTRL + enables the automatic mechanism to stop providing clock in the clock lane + 1 + 1 + read-write + + + PHY_TXREQUESTCLKHS + controls the D-PHY PPI txrequestclkhs signal + 0 + 1 + read-write + + + + + phy_tmr_lpclk_cfg + sets the time that dsi host assumes in calculations for the clock lane to switch between high-speed and low-power + 0x98 + 32 + 0x00000000 + 0x03FF03FF + + + PHY_CLKHS2LP_TIME + configures the maximum time that the d-phy clock lane takes to go from high-speed to low-power transmission + 16 + 10 + read-write + + + PHY_CLKLP2HS_TIME + configures the maximum time that the d-phy clock lane takes to go from low-power to high-speed transmission + 0 + 10 + read-write + + + + + phy_tmr_cfg + sets the time that dsi host assumes in calculations for data lanes to switch between hs to lp + 0x9c + 32 + 0x00000000 + 0x03FF03FF + + + PHY_HS2LP_TIME + This field configures the maximum time that the D-PHY data +lanes take to go from high-speed to low-power transmission +measured in lane byte clock cycles + 16 + 10 + read-write + + + PHY_LP2HS_TIME + This field configures the maximum time that the D-PHY data +lanes take to go from low-power to high-speed transmission +measured in lane byte clock cycles. + 0 + 10 + read-write + + + + + phy_rstz + controls resets and the pll of d-phy + 0xa0 + 32 + 0x00000000 + 0x0000000F + + + PHY_FORCEPLL + when the d-phy is in ulps, enable the d-phy pll + 3 + 1 + read-write + + + PHY_ENABLECLK + enable dphy clock lane + 2 + 1 + read-write + + + PHY_RSTZ + make the dphy in reset state when set to 0 + 1 + 1 + read-write + + + PHY_SHUTDOWNZ + places the dphy macro in power down mode when set to 0 + 0 + 1 + read-write + + + + + phy_if_cfg + configures the number of active lanes + 0xa4 + 32 + 0x00000000 + 0x0000FF03 + + + PHY_STOP_WAIT_TIME + configures the minimum time phy needs to stay in stopstate before requesting an highspeed transmission + 8 + 8 + read-write + + + N_LANES + configures the number of active data lanes + 0 + 2 + read-write + + + + + phy_ulps_ctrl + configures entering and leaving ulps + 0xa8 + 32 + 0x00000000 + 0x0000000F + + + PHY_TXEXITULPSLAN + ulps mode exit on all active data lanes + 3 + 1 + read-write + + + PHY_TXREQULPSLAN + ulps mode request on all active data lanes + 2 + 1 + read-write + + + PHY_TXEXITULPSCLK + ulps mode exit on clock lane + 1 + 1 + read-write + + + PHY_TXREQULPSCLK + ulps mode request on clock lane + 0 + 1 + read-write + + + + + phy_tx_triggers + configures the pins that activate triggers in the d-phy + 0xac + 32 + 0x00000000 + 0x0000000F + + + PHY_TX_TRIGGERS + controls the trigger transmissions + 0 + 4 + read-write + + + + + phy_status + contains information about the status of the d-phy + 0xb0 + 32 + 0x00000000 + 0x00001FFF + + + PHY_ULPSACTIVENOT3LANE + indicates the status of ulpsactivenot3lane d-phy signal + 12 + 1 + read-only + + + PHY_STOPSTATE3LANE + This bit indicates the status of phystopstate3lane D-PHY +signal. + 11 + 1 + read-only + + + PHY_ULPSACTIVENOT2LANE + This bit indicates the status of ulpsactivenot2lane D-PHY +signa + 10 + 1 + read-only + + + PHY_STOPSTATE2LANE + This bit indicates the status of phystopstate2lane D-PHY +signal + 9 + 1 + read-only + + + PHY_ULPSACTIVENOT1LANE + This bit indicates the status of ulpsactivenot1lane D-PHY +signal + 8 + 1 + read-only + + + PHY_STOPSTATE1LANE + This bit indicates the status of phystopstate1lane D-PHY +signal + 7 + 1 + read-only + + + PHY_RXULPSESC0LANE + This bit indicates the status of rxulpsesc0lane D-PHY signa + 6 + 1 + read-only + + + PHY_ULPSACTIVENOT0LANE + This bit indicates the status of ulpsactivenot0lane D-PHY +signal + 5 + 1 + read-only + + + PHY_STOPSTATE0LANE + This bit indicates the status of phystopstate0lane D-PHY +signal + 4 + 1 + read-only + + + PHY_ULPSACTIVENOTCLK + This bit indicates the status of phyulpsactivenotclk D-PHY +signal + 3 + 1 + read-only + + + PHY_STOPSTATECLKLANE + This bit indicates the status of phystopstateclklane D-PHY +signal + 2 + 1 + read-only + + + PHY_DIRECTION + This bit indicates the status of phydirection D-PHY signal + 1 + 1 + read-only + + + PHY_LOCK + This bit indicates the status of phylock D-PHY signal + 0 + 1 + read-only + + + + + phy_tst_ctrl0 + controls clock and clear pins of the d-phy vendor specific interface + 0xb4 + 32 + 0x00000000 + 0x00000003 + + + PHY_TESTCLK + reserve + 1 + 1 + read-write + + + PHY_TESTCLR + reserve + 0 + 1 + read-write + + + + + phy_tst_ctrl1 + controls data and enable pins of the d-phy + 0xb8 + 32 + 0x00000000 + 0x0001FFFF + + + PHY_TESTEN + reserve + 16 + 1 + read-write + + + PHY_TESTDOUT + reserve + 8 + 8 + read-only + + + PHY_TESTDIN + reserve + 0 + 8 + read-write + + + + + int_st0 + controls the status of interrupt + 0xbc + 32 + 0x00000000 + 0x001FFFFF + + + DPHY_ERRORS_4 + indicates LP1 contention error ErrContentionLP1 from lane0 + 20 + 1 + read-only + + + DPHY_ERRORS_3 + indicates LP0 contention error ErrContentionLP0 from lane0 + 19 + 1 + read-only + + + DPHY_ERRORS_2 + indicates control error ErrControl from lane0 + 18 + 1 + read-only + + + DPHY_ERRORS_1 + indicates ErrSyncEsc low-power data transmission synchronization error from lane 0 + 17 + 1 + read-only + + + DPHY_ERRORS_0 + indicates ErrEsc escape entry error from lane0 + 16 + 1 + read-only + + + ACK_WITH_ERR_15 + retrives the DSI protocal violation from the acknowledge error report + 15 + 1 + read-only + + + ACK_WITH_ERR_14 + retrives the reserved from the acknowledge error report + 14 + 1 + read-only + + + ACK_WITH_ERR_13 + retrives the invalid transmission length from the acknowledge error report + 13 + 1 + read-only + + + ACK_WITH_ERR_12 + retrieves the dsi vc id invalid from the acknowledge error report + 12 + 1 + read-only + + + ACK_WITH_ERR_11 + retrives the not recongnized dsi data type from the acknowledge error report + 11 + 1 + read-only + + + ACK_WITH_ERR_10 + retrives the checksum error from the acknowledge error report + 10 + 1 + read-only + + + ACK_WITH_ERR_9 + retrives the ECC error multi-bit from the acknowledge error report + 9 + 1 + read-only + + + ACK_WITH_ERR8 + retrives the ecc error sigle-bit from the acknowledge error report + 8 + 1 + read-only + + + ACK_WITH_ERR7 + retrieves the reserved from the acknowledge error report + 7 + 1 + read-only + + + ACK_WITH_ERR6 + retrieves the false control error fro the acknowledge error report + 6 + 1 + read-only + + + ACK_WITH_ERR5 + retrives the peripheral timeout error from the acknowledge error report + 5 + 1 + read-only + + + ACK_WITH_ERR4 + retrives the LP transmit sync error from the acknowledge error report + 4 + 1 + read-only + + + ACK_WITH_ERR3 + retrives the Escap mode entry command error from the acknowledge error report + 3 + 1 + read-only + + + ACK_WITH_ERR2 + retrives the EoT sync error from the acknowledge error report + 2 + 1 + read-only + + + ACK_WITH_ERR1 + retrives the SoT sync error from the acknowledge error report + 1 + 1 + read-only + + + ACK_WITH_ERR0 + retrives the SoT serror from the acknowledge error report + 0 + 1 + read-only + + + + + int_st1 + the interrupt source related to timeout etc + 0xc0 + 32 + 0x00000000 + 0x00181FFF + + + TEAR_REQUEST_ERR + indicates tear_request has occurred but tear effect is not active in dsi host and device + 20 + 1 + read-only + + + DPI_BUFF_PLD_UNDER + indicates an underflow when reading payload to build dsi packet for video mode + 19 + 1 + read-only + + + GEN_PLD_RECEV_ERR + indicates that during a generic interface packet read back, the payload FIFO full + 12 + 1 + read-only + + + GEN_PLD_RD_ERR + indicates that during a DCS read data, the payload FIFO becomes empty + 11 + 1 + read-only + + + GEN_PLD_SEND_ERR + indicates the payload FIFO become empty when packet build + 10 + 1 + read-only + + + GEN_PLD_WR_ERR + indicates the system tried to write a payload and FIFO is full + 9 + 1 + read-only + + + GEN_CMD_WR_ERR + indicates the system tried to write a command and FIFO is full + 8 + 1 + read-only + + + DPI_BPLD_WR_ERR + indicates the payload FIFO is full during a DPI pixel line storage + 7 + 1 + read-only + + + EOPT_ERR + indicates that the EoTp packet has not been received at the end of the incoming peripheral transmission + 6 + 1 + read-only + + + PKT_SIZE_ERR + indicates that the packet size error has been detected during the packet reception + 5 + 1 + read-only + + + CRC_ERR + indicates that the CRC error has been detected in the reveived packet payload + 4 + 1 + read-only + + + ECC_MULTI_ERR + indicates that the ECC multiple error has been detected in a revieved packet + 3 + 1 + read-only + + + ECC_SIGLE_ERR + indicates that the ECC single error has been detected and corrected in a reveived packet + 2 + 1 + read-only + + + TO_LP_TX + indicates that the low-power reception timeout counter reached the end and contention has been detected + 1 + 1 + read-only + + + TO_HS_TX + indicates that the high-speed transmission timeout counter reached the end and contention has been detected + 0 + 1 + read-only + + + + + int_msk0 + configures masks for the sources of interrupt that affec int_st0 + 0xc4 + 32 + 0x00000000 + 0x001FFFFF + + + MASK_DPHY_ERRORS_4 + disable LP1 contention error ErrContentionLP1 from lane0 + 20 + 1 + read-write + + + MASK_DPHY_ERRORS_3 + disable LP0 contention error ErrContentionLP0 from lane0 + 19 + 1 + read-write + + + MASK_DPHY_ERRORS_2 + disable control error ErrControl from lane0 + 18 + 1 + read-write + + + MASK_DPHY_ERRORS_1 + disable ErrSyncEsc low-power data transmission synchronization error from lane 0 + 17 + 1 + read-write + + + MASK_DPHY_ERRORS_0 + disable ErrEsc escape entry error from lane0 + 16 + 1 + read-write + + + MASK_ACK_WITH_ERR_15 + disable the DSI protocal violation from the acknowledge error report + 15 + 1 + read-write + + + MASK_ACK_WITH_ERR_14 + disable the reserved from the acknowledge error report + 14 + 1 + read-write + + + MASK_ACK_WITH_ERR_13 + disable the invalid transmission length from the acknowledge error report + 13 + 1 + read-write + + + MASK_ACK_WITH_ERR_12 + disable the dsi vc id invalid from the acknowledge error report + 12 + 1 + read-write + + + MASK_ACK_WITH_ERR_11 + disable the not recongnized dsi data type from the acknowledge error report + 11 + 1 + read-write + + + MASK_ACK_WITH_ERR_10 + disable the checksum error from the acknowledge error report + 10 + 1 + read-write + + + MASK_ACK_WITH_ERR_9 + disable the ECC error multi-bit from the acknowledge error report + 9 + 1 + read-write + + + MASK_ACK_WITH_ERR8 + disable the ecc error sigle-bit from the acknowledge error report + 8 + 1 + read-write + + + MASK_ACK_WITH_ERR7 + disable the reserved from the acknowledge error report + 7 + 1 + read-write + + + MASK_ACK_WITH_ERR6 + disable the false control error fro the acknowledge error report + 6 + 1 + read-write + + + MASK_ACK_WITH_ERR5 + disable the peripheral timeout error from the acknowledge error report + 5 + 1 + read-write + + + MASK_ACK_WITH_ERR4 + disable the LP transmit sync error from the acknowledge error report + 4 + 1 + read-write + + + MASK_ACK_WITH_ERR3 + disable the Escap mode entry command error from the acknowledge error report + 3 + 1 + read-write + + + MASK_ACK_WITH_ERR2 + disable the EoT sync error from the acknowledge error report + 2 + 1 + read-write + + + MASK_ACK_WITH_ERR1 + disable the SoT sync error from the acknowledge error report + 1 + 1 + read-write + + + MASK_ACK_WITH_ERR0 + disable the SoT serror from the acknowledge error report + 0 + 1 + read-write + + + + + int_msk1 + configures masks for int_st1 + 0xc8 + 32 + 0x00000000 + 0x00181FFF + + + MASK_TEAR_REQUEST_ERR + disable tear_request has occurred but tear effect is not active in dsi host and device + 20 + 1 + read-write + + + MASK_DPI_BUFF_PLD_UNDER + disable an underflow when reading payload to build dsi packet for video mode + 19 + 1 + read-write + + + MASK_GEN_PLD_RECEV_ERR + disable that during a generic interface packet read back, the payload FIFO full + 12 + 1 + read-write + + + MASK_GEN_PLD_RD_ERR + disable that during a DCS read data, the payload FIFO becomes empty + 11 + 1 + read-write + + + MASK_GEN_PLD_SEND_ERR + disable the payload FIFO become empty when packet build + 10 + 1 + read-write + + + MASK_GEN_PLD_WR_ERR + disable the system tried to write a payload and FIFO is full + 9 + 1 + read-write + + + MASK_GEN_CMD_WR_ERR + disable the system tried to write a command and FIFO is full + 8 + 1 + read-write + + + MASK_DPI_BPLD_WR_ERR + disable the payload FIFO is full during a DPI pixel line storage + 7 + 1 + read-write + + + MASK_EOPT_ERR + disable that the EoTp packet has not been received at the end of the incoming peripheral transmission + 6 + 1 + read-write + + + MASK_PKT_SIZE_ERR + disable that the packet size error has been detected during the packet reception + 5 + 1 + read-write + + + MASK_CRC_ERR + disable that the CRC error has been detected in the reveived packet payload + 4 + 1 + read-write + + + MASK_ECC_MULTI_ERR + disable that the ECC multiple error has been detected in a revieved packet + 3 + 1 + read-write + + + MASK_ECC_SIGLE_ERR + disable that the ECC single error has been detected and corrected in a reveived packet + 2 + 1 + read-write + + + MASK_TO_LP_TX + disable that the low-power reception timeout counter reached the end and contention has been detected + 1 + 1 + read-write + + + MASK_TO_HS_TX + disable that the high-speed transmission timeout counter reached the end and contention has been detected + 0 + 1 + read-write + + + + + phy_cal + controls the skew calibration of D-phy + 0xcc + 32 + 0x00000000 + 0x00000001 + + + TXSKEWCALHS + High-speed skew calibration is started when txskewcalhs is +set high (assuming that PHY is in Stop state) + 0 + 1 + read-write + + + + + int_force0 + forces that affect the int_st0 register + 0xd8 + 32 + 0x00000000 + 0x001FFFFF + + + FORCE_DPHY_ERRORS_4 + force LP1 contention error ErrContentionLP1 from lane0 + 20 + 1 + read-write + + + FORCE_DPHY_ERRORS_3 + force LP0 contention error ErrContentionLP0 from lane0 + 19 + 1 + read-write + + + FORCE_DPHY_ERRORS_2 + force control error ErrControl from lane0 + 18 + 1 + read-write + + + FORCE_DPHY_ERRORS_1 + force ErrSyncEsc low-power data transmission synchronization error from lane 0 + 17 + 1 + read-write + + + FORCE_DPHY_ERRORS_0 + force ErrEsc escape entry error from lane0 + 16 + 1 + read-write + + + FORCE_ACK_WITH_ERR_15 + force the DSI protocal violation from the acknowledge error report + 15 + 1 + read-write + + + FORCE_ACK_WITH_ERR_14 + force the reserved from the acknowledge error report + 14 + 1 + read-write + + + FORCE_ACK_WITH_ERR_13 + force the invalid transmission length from the acknowledge error report + 13 + 1 + read-write + + + FORCE_ACK_WITH_ERR_12 + force the dsi vc id invalid from the acknowledge error report + 12 + 1 + read-write + + + FORCE_ACK_WITH_ERR_11 + force the not recongnized dsi data type from the acknowledge error report + 11 + 1 + read-write + + + FORCE_ACK_WITH_ERR_10 + force the checksum error from the acknowledge error report + 10 + 1 + read-write + + + FORCE_ACK_WITH_ERR_9 + force the ECC error multi-bit from the acknowledge error report + 9 + 1 + read-write + + + FORCE_ACK_WITH_ERR8 + force the ecc error sigle-bit from the acknowledge error report + 8 + 1 + read-write + + + FORCE_ACK_WITH_ERR7 + force the reserved from the acknowledge error report + 7 + 1 + read-write + + + FORCE_ACK_WITH_ERR6 + force the false control error fro the acknowledge error report + 6 + 1 + read-write + + + FORCE_ACK_WITH_ERR5 + force the peripheral timeout error from the acknowledge error report + 5 + 1 + read-write + + + FORCE_ACK_WITH_ERR4 + force the LP transmit sync error from the acknowledge error report + 4 + 1 + read-write + + + FORCE_ACK_WITH_ERR3 + force the Escap mode entry command error from the acknowledge error report + 3 + 1 + read-write + + + FORCE_ACK_WITH_ERR2 + force the EoT sync error from the acknowledge error report + 2 + 1 + read-write + + + FORCE_ACK_WITH_ERR1 + force the SoT sync error from the acknowledge error report + 1 + 1 + read-write + + + FORCE_ACK_WITH_ERR0 + force the SoT serror from the acknowledge error report + 0 + 1 + read-write + + + + + int_force1 + forces interrupts that affect the int_st1 register + 0xdc + 32 + 0x00000000 + 0x00181FFF + + + FORCE_TEAR_REQUEST_ERR + force tear_request has occurred but tear effect is not active in dsi host and device + 20 + 1 + read-write + + + FORCE_DPI_BUFF_PLD_UNDER + force an underflow when reading payload to build dsi packet for video mode + 19 + 1 + read-write + + + FORCE_GEN_PLD_RECEV_ERR + force that during a generic interface packet read back, the payload FIFO full + 12 + 1 + read-write + + + FORCE_GEN_PLD_RD_ERR + force that during a DCS read data, the payload FIFO becomes empty + 11 + 1 + read-write + + + FORCE_GEN_PLD_SEND_ERR + force the payload FIFO become empty when packet build + 10 + 1 + read-write + + + FORCE_GEN_PLD_WR_ERR + force the system tried to write a payload and FIFO is full + 9 + 1 + read-write + + + FORCE_GEN_CMD_WR_ERR + force the system tried to write a command and FIFO is full + 8 + 1 + read-write + + + FORCE_DPI_BPLD_WR_ERR + force the payload FIFO is full during a DPI pixel line storage + 7 + 1 + read-write + + + FORCE_EOPT_ERR + force that the EoTp packet has not been received at the end of the incoming peripheral transmission + 6 + 1 + read-write + + + FORCE_PKT_SIZE_ERR + force that the packet size error has been detected during the packet reception + 5 + 1 + read-write + + + FORCE_CRC_ERR + force that the CRC error has been detected in the reveived packet payload + 4 + 1 + read-write + + + FORCE_ECC_MULTI_ERR + force that the ECC multiple error has been detected in a revieved packet + 3 + 1 + read-write + + + FORCE_ECC_SIGLE_ERR + force that the ECC single error has been detected and corrected in a reveived packet + 2 + 1 + read-write + + + FORCE_TO_LP_TX + force that the low-power reception timeout counter reached the end and contention has been detected + 1 + 1 + read-write + + + FORCE_TO_HS_TX + force that the high-speed transmission timeout counter reached the end and contention has been detected + 0 + 1 + read-write + + + + + phy_tmr_rd + configures times related to PHY to perform some operations in lane byte clock cycle + 0xf4 + 32 + 0x00000000 + 0x00007FFF + + + MAX_RD_TIME + the maximum time required to perform a read command in lane byte clock cycles. + 0 + 15 + read-write + + + + + auto_ulps_min_time + configures the minimum time required by phy between ulpsactivenot and ulpsexitreq for clock and data lane + 0xf8 + 32 + 0x00000000 + 0x00000FFF + + + ULPS_MIN_TIME + configures the minimum time required by phy between ulpsactivenot and ulpsexitreq for clock and data lane + 0 + 12 + read-write + + + + + phy_mode + select phy mode + 0xfc + 32 + 0x00000000 + 0x00000001 + + + PHY_MODE + sel DPHY or CPHY + 0 + 1 + read-write + + + + + vid_shadow_ctrl + controls dpi shadow feature + 0x100 + 32 + 0x00000000 + 0x00010101 + + + VID_SHADOW_PIN_REQ + when set to 1, the video request is done by external pin + 16 + 1 + read-write + + + VID_SHADOW_REQ + when set to 1, request that the dpi register from regbank are copied to the auxiliary registers + 8 + 1 + read-write + + + VID_SHADOW_EN + when set to 1, DPI receives the active configuration from the auxiliary register + 0 + 1 + read-write + + + + + dpi_vcid_act + holds the value that controller is using for DPI_VCID + 0x10c + 32 + 0x00000000 + 0x00000003 + + + DPI_VCID + specifies the DPI virtual channel id that is indexed to the video mode packets + 0 + 2 + read-only + + + + + dpi_color_coding_act + holds the value that controller is using for DPI_COLOR_CODING + 0x110 + 32 + 0x00000000 + 0x0000010F + + + LOOSELY18_EN + avtivates loosely packed variant to 18-bit configuration + 8 + 1 + read-only + + + DIP_COLOR_CODING + configures the DPI color for video mode + 0 + 4 + read-only + + + + + dpi_lp_cmd_tim_act + holds value that controller is using for dpi_lp_cmd_time + 0x118 + 32 + 0x00000000 + 0x00FF00FF + + + OUTVACT_LPCMD_TIME + transmission of commands in low-power mode, it specifies the size in bytes of the lagest packet that can fit in a line during the VSA VBP and VFP regions. + 16 + 8 + read-only + + + INVACT_LPCMD_TIME + transmission of commands in low-power mode, it specifies the size in bytes of the lagest packet that can fit in a line during the vact regions. + 0 + 8 + read-only + + + + + vid_mode_cfg_act + holds value that controller is using for vid_mode_cfg + 0x138 + 32 + 0x00000000 + 0x000003FF + + + LP_CMD_EN + enable the command transmission only in low-power mode + 9 + 1 + read-only + + + FRAME_BTA_ACK_EN + enable the request for an acknowledge response at the end of a frame + 8 + 1 + read-only + + + LP_HFP_EN + enable the returne to low-power inside the HFP period when timing allows + 7 + 1 + read-only + + + LP_HBP_EN + enable the returne to low-power inside the HBP period when timing allows + 6 + 1 + read-only + + + LP_VACT_EN + enable the returne to low-power inside the VACT period when timing allows + 5 + 1 + read-only + + + LP_VFP_EN + enable the returne to low-power inside the VFP period when timing allows + 4 + 1 + read-only + + + LP_VBP_EN + enable the returne to low-power inside the VBP period when timing allows + 3 + 1 + read-only + + + LP_VSA_EN + enable the returne to low-power inside the VSA period when timing allows + 2 + 1 + read-only + + + VID_MODE_TYPE + specifies the video mode transmission type + 0 + 2 + read-only + + + + + vid_pkt_size_act + holds value that controller is using for vid_pkt_size + 0x13c + 32 + 0x00000000 + 0x00003FFF + + + VID_PKT_SIZE + the number of pixels in a single video packet + 0 + 14 + read-only + + + + + vid_num_chunks_act + holds value that controller is using for vid_num_chunks + 0x140 + 32 + 0x00000000 + 0x00001FFF + + + VID_NUM_CHUNKS + the number of chunks to be transmitted during a line period + 0 + 13 + read-only + + + + + vid_null_size_act + holds the value that controller is using for vid_null_size + 0x144 + 32 + 0x00000000 + 0x00001FFF + + + VID_NULL_SIZE + the number of bytes in side a null packet + 0 + 13 + read-only + + + + + vid_hsa_time_act + the value of vid_hsa_time + 0x148 + 32 + 0x00000000 + 0x00000FFF + + + VID_HSA_TIME + the horizontal synchronism active period in lane byte clock cycles + 0 + 12 + read-only + + + + + vid_hbp_time_act + the value that controller is using for vid_hbp_time + 0x14c + 32 + 0x00000000 + 0x00000FFF + + + VID_HBP_TIME + the horizontal back porch period in lane byte clock cycles + 0 + 12 + read-only + + + + + vid_hline_time_act + the value for vid_hline_time + 0x150 + 32 + 0x00000000 + 0x00007FFF + + + VID_HLINE_TIME + the size of total line: hsa+hbp+hact+hfp + 0 + 15 + read-only + + + + + vid_vsa_lines_act + value for vid_vsa_lines + 0x154 + 32 + 0x00000000 + 0x000003FF + + + VSA_LINES + vertical synchronism active period + 0 + 10 + read-only + + + + + vid_vbp_lines_act + value for vid_vbp_lines + 0x158 + 32 + 0x00000000 + 0x000003FF + + + VBP_LINES + vertical back porch period + 0 + 10 + read-only + + + + + vid_vfp_lines_act + value for vid_vfp_lines + 0x15c + 32 + 0x00000000 + 0x000003FF + + + VFP_LINES + vertical porch period + 0 + 10 + read-only + + + + + vid_vactive_lines_act + value for vid_vactive_lines + 0x160 + 32 + 0x00000000 + 0x00003FFF + + + V_ACTIVE_LINES + vertical active period + 0 + 14 + read-only + + + + + vid_pkt_status + status of fifo related to dpi + 0x168 + 32 + 0x00000000 + 0x0003000F + + + DPI_BUFF_PLD_FULL + This bit indicates the full status of the payload internal buffer +for video Mode. This bit is set to 0 for command Mode + 17 + 1 + read-only + + + DPI_BUFF_PLD_EMPTY + This bit indicates the empty status of the payload internal +buffer for video Mode. This bit is set to 0 for command Mod + 16 + 1 + read-only + + + DPI_PLD_W_FULL + This bit indicates the full status of write payload FIFO for +video Mode. This bit is set to 0 for command Mode + 3 + 1 + read-only + + + DPI_PLD_W_EMPTY + This bit indicates the empty status of write payload FIFO for +video Mode. This bit is set to 0 for command Mode + 2 + 1 + read-only + + + DPI_CMD_W_FULL + This bit indicates the full status of write command FIFO for +video Mode. This bit is set to 0 for command Mode + 1 + 1 + read-only + + + DPI_CMD_W_EMPTY + This bit indicates the empty status of write command FIFO +for video Mode. This bit is set to 0 for command Mode + 0 + 1 + read-only + + + + + sdf_3d_act + value for sdf_3d + 0x190 + 32 + 0x00000000 + 0x0001003F + + + SEND_3D_CFG + When set, causes the next VSS packet to include 3D control +payload in every VSS packet. + 16 + 1 + read-only + + + RIGHT_FIRST + This bit specifies the left/right order + 5 + 1 + read-only + + + SECOND_VSYNC + This field specifies whether there is a second VSYNC pulse +between Left and Right Images, when 3D Image Format is +Frame-based + 4 + 1 + read-only + + + FORMAT_3D + This field specifies 3D Image Format + 2 + 2 + read-only + + + MODE_3D + This field specifies 3D Mode On/Off and Display Orientation + 0 + 2 + read-only + + + + + + + MIPI_DSI1 + MIPI_DSI1 + MIPI_DSI + 0xf1024000 + + + MIPI_CSI0 + MIPI_CSI0 + MIPI_CSI + 0xf1028000 + + 0x0 + 0x2bc + registers + + + + version + version code + 0x0 + 32 + 0x3134302A + 0xFFFFFFFF + + + VERSION + version code + 0 + 32 + read-only + + + + + n_lanes + the number of active lanes + 0x4 + 32 + 0x00000001 + 0x00000007 + + + N_LANES + number of active data lanes + 0 + 3 + read-write + + + + + csi2_resetn + the internal logic of the controller goes into the reset state when active + 0x8 + 32 + 0x00000000 + 0x00000001 + + + CSI2_RESETN + DWC_mipi_csi2_host reset output, active low + 0 + 1 + read-write + + + + + int_st_main + contains the stateus of individual interrupt sources + 0xc + 32 + 0x00000000 + 0x000700FF + + + STATUS_INT_IPI4_FATAL + status of int_st_ipi_fatal + 18 + 1 + read-only + + + STATUS_INT_LINE + status of int_st_line + 17 + 1 + read-only + + + STATUS_INT_PHY + status of int_st_phy + 16 + 1 + read-only + + + STATUS_INT_ECC_CORRECTED + status of status_int_ecc_corrected + 7 + 1 + read-only + + + STATUS_INT_DATA_ID + status of status_int_data_id + 6 + 1 + read-only + + + STATUS_INT_PLD_CRC_FATAL + status of status_int_pld_crc_fatal + 5 + 1 + read-only + + + STATUS_INT_CRC_FRAME_FATAL + status of status_int_crc_frame_fatal + 4 + 1 + read-only + + + STATUS_INT_SEQ_FRAME_FATAL + status of status_int_seq_frame_fatal + 3 + 1 + read-only + + + STATUS_INT_BNDRY_FRAME_FATAL + status of int_st_bndry_frame_fatal + 2 + 1 + read-only + + + STATUS_INT_PKT_FATAL + status of int_st_pkt_fatal + 1 + 1 + read-only + + + STATUS_INT_PHY_FATAL + status of int_st_phy_fatal + 0 + 1 + read-only + + + + + data_ids_1 + programs data type fields for data ID monitors + 0x10 + 32 + 0x00000000 + 0x3F3F3F3F + + + DI3_DT + data type for programmed data ID 3 + 24 + 6 + read-write + + + DI2_DT + data type for programmed data ID 2 + 16 + 6 + read-write + + + DI1_DT + data type for programmed data ID 1 + 8 + 6 + read-write + + + DI0_DT + data type for programmed data ID 0 + 0 + 6 + read-write + + + + + data_ids_2 + programs data type fields for data ID monitors + 0x14 + 32 + 0x00000000 + 0x3F3F3F3F + + + DI7_DT + data type for programmed data ID 7 + 24 + 6 + read-write + + + DI6_DT + data type for programmed data ID 6 + 16 + 6 + read-write + + + DI5_DT + data type for programmed data ID 5 + 8 + 6 + read-write + + + DI4_DT + data type for programmed data ID 4 + 0 + 6 + read-write + + + + + int_st_ap_main + contains the status of individual interrupt sources + 0x2c + 32 + 0x00000000 + 0x00001FFF + + + STATUS_INT_IPI_FATAL + status of int_st_ipi_fatal + 12 + 1 + read-only + + + STATUS_INT_ST_AP_IPI_FATAL + status of int_st_ap_ipi_fatal + 11 + 1 + read-only + + + STATUS_INT_LINE + status of int_st_line + 10 + 1 + read-only + + + STATUS_INT_ECC_CORRECTED + status of status_int_ecc_corrected + 9 + 1 + read-only + + + STATUS_INT_DATA_ID + status of status_int_data_id + 8 + 1 + read-only + + + STATUS_INT_PLD_CRC_FATAL + status of status_int_pld_crc_fatal + 7 + 1 + read-only + + + STATUS_INT_PHY + status of int_st_phy + 6 + 1 + read-only + + + STATUS_INT_CRC_FRAME_FATAL + status of status_int_crc_frame_fatal + 5 + 1 + read-only + + + STATUS_INT_SEQ_FRAME_FATAL + status of status_int_seq_frame_fatal + 4 + 1 + read-only + + + STATUS_INT_BNDRY_FRAME_FATAL + status of int_st_bndry_frame_fatal + 3 + 1 + read-only + + + STATUS_INT_PKT_FATAL + status of int_st_pkt_fatal + 2 + 1 + read-only + + + STATUS_INT_PHY_FATAL + status of int_st_phy_fatal + 1 + 1 + read-only + + + STATUS_INT_ST_AP_GENERIC + status of int_st_ap_generic + 0 + 1 + read-only + + + + + phy_shutdownz + controls the phy shutdown mode + 0x40 + 32 + 0x00000000 + 0x00000001 + + + PHY_SHUTDOWNZ + shutdown input,active low + 0 + 1 + read-write + + + + + dphy_rstz + controls the phy reset mode + 0x44 + 32 + 0x00000000 + 0x00000001 + + + DPHY_RSTZ + phy reset output, active low + 0 + 1 + read-write + + + + + phy_rx + contains the status of rx-related signals from phy + 0x48 + 32 + 0x00010000 + 0x00030003 + + + PHY_RXCLKACTIVEHS + indicates the d-phy clock lane is actively receiving a ddr clock + 17 + 1 + read-only + + + PHY_RXULPSCLKNOT + active low. Indicates the d-phy clock lane module has entered the Ultra low power state + 16 + 1 + read-only + + + PHY_RXULLPSESC_1 + lane module 1 has entered the ultra low power mode + 1 + 1 + read-only + + + PHY_RXULPSESC_0 + lane module 0 has entered the ultra low power mode + 0 + 1 + read-only + + + + + phy_stopstate + contains the stopstate signal status from phy + 0x4c + 32 + 0x00000000 + 0x00010003 + + + PHY_STOPSTATECLK + d-phy clock lane in stop state + 16 + 1 + read-only + + + PHY_STOPSTATEDATA_1 + data lane 1 in stop state + 1 + 1 + read-only + + + PHY_STOPSTATEDATA_0 + data lane 0 in stop state + 0 + 1 + read-only + + + + + ipi_mode + selects how the ipi interface generates the video frame + 0x80 + 32 + 0x00000000 + 0x01010101 + + + IPI_ENABLE + enables the interface + 24 + 1 + read-write + + + IPI_CUT_THROUGH + cut-through mode state active when high + 16 + 1 + read-write + + + IPI_COLOR_COM + if color mode components are deliverd as follows: 0x0 48bit intercase 0x1: 16bit interface + 8 + 1 + read-write + + + IPI_MODE + indicates the video mode transmission type 0x0: camera timing 0x1:controller timing + 0 + 1 + read-write + + + + + ipi_vcid + selects the vritual channel processed by ipi + 0x84 + 32 + 0x00000000 + 0x0000000F + + + IPI_VCX_0_1 + virtual channel extension of data to be processed by pixel interface + 2 + 2 + read-write + + + IP_VCID + virtual channel of data to be processed by pixel interface + 0 + 2 + read-write + + + + + ipi_data_type + selects the data type processed by ipi + 0x88 + 32 + 0x00000000 + 0x0000013F + + + EMBENDED_DATA + enable embedded data processing on ipi interface + 8 + 1 + read-write + + + IPI_DATA_TYPE + data type of data to be processed by pixel interface + 0 + 6 + read-write + + + + + ipi_mem_flash + control the flush of ipi memory + 0x8c + 32 + 0x00000000 + 0x00000101 + + + IPI_AUTO_FLUSH + memory is automatically flashed at each vsync + 8 + 1 + read-write + + + IPI_FLUSH + flush ipi memory, this bit is auto clear + 0 + 1 + read-write + + + + + ipi_hsa_time + configures the video horizontal synchronism active time + 0x90 + 32 + 0x00000000 + 0x00000FFF + + + IPI_HSA_TIME + configures the Horizontal Synchronism Active period in pixclk cycles + 0 + 12 + read-write + + + + + ipi_hbp_time + configures the video horizontal synchronism back porch time + 0x94 + 32 + 0x00000000 + 0x00000FFF + + + IPI_HBP_TIME + configures the Horizontal Synchronism back porch period in pixclk cycles + 0 + 12 + read-write + + + + + ipi_hsd_time + configures the vedeo Horizontal Sync Delay time + 0x98 + 32 + 0x00000000 + 0x00000FFF + + + IPI_HSD_TIME + configures the Horizontal Sync Porch delay period in pixclk cycles + 0 + 12 + read-write + + + + + ipi_hline_time + configures the overall tiem for each video line + 0x9c + 32 + 0x00000000 + 0x00007FFF + + + IPI_HLIN_TIME + configures the size of the line time counted in pixclk cycles + 0 + 15 + read-write + + + + + ipi_softrstn + congtrols the ipi logic reset state + 0xa0 + 32 + 0x00000001 + 0x00000001 + + + IPI_SOFTRSTN + resets ipi one, active low + 0 + 1 + read-write + + + + + ipi_adv_features + configures advanced features for ipi mode + 0xac + 32 + 0x00000000 + 0x013F3F01 + + + IPI_SYNC_EVENT_MODE + for camera mode: 0x0- frame start do not trigger any sync event + 24 + 1 + read-write + + + EN_EMBEDDED + allows the use of embendded packets for ipi synchronization events + 21 + 1 + read-write + + + EN_BLANKING + allows the use of blankong packets for IPI synchronization events + 20 + 1 + read-write + + + EN_NULL + allows the use of null packets for IPI synchronization events + 19 + 1 + read-write + + + EN_LINE_START + allows the use of line start packets for ipi synchronization events + 18 + 1 + read-write + + + EN_VIDEO + allows the use of video packets for ipi synchronization events + 17 + 1 + read-write + + + LINE_EVENT_SELECTION + for camero mode, allows manual selection of the packet fo line delimiter as follows: 0x0-controller seletc it automaticlly 0x1-select packets from list programmed in 17:21 + 16 + 1 + read-write + + + IPI_DT + datatype to overwrite + 8 + 6 + read-write + + + IPI_DT_OVERWRITE + ignore datatype of the header using the programmed datatype for decoding + 0 + 1 + read-write + + + + + ipi_vsa_lines + configures the vertical synchronism active period + 0xb0 + 32 + 0x00000000 + 0x000003FF + + + IPI_VSA_LINES + configures the vertical synchronism active period measured in number of horizontal lines + 0 + 10 + read-write + + + + + ipi_vbp_lines + configures the verticall back porch period + 0xb4 + 32 + 0x00000000 + 0x000003FF + + + IPI_VBP_LINES + configuress the vertical back porch period measured in number of horizontal lines + 0 + 10 + read-write + + + + + ipi_vfp_lines + configures the vertical front porch period + 0xb8 + 32 + 0x00000000 + 0x000003FF + + + IPI_VFP_LINES + configures the vertical front porch period measured in number of horizontall lines + 0 + 10 + read-write + + + + + ipi_vactive_lines + configures the vertical resolution of video + 0xbc + 32 + 0x00000000 + 0x00003FFF + + + IPI_VACTIVE_LINES + configures the vertical active period measured in bumber of horizontal lines + 0 + 14 + read-write + + + + + vc_extension + active extra bits for virtual channel + 0xc8 + 32 + 0x00000000 + 0x00000001 + + + VCX + indicates status of virtual channel extension: 0-virtual channel extension is enable 1-legacy mode + 0 + 1 + read-write + + + + + phy_cal + contains the calibration signal status from synopsys d-phy + 0xcc + 32 + 0x00000000 + 0x00000001 + + + RXSKEWCALHS + a low-to-high transition on rxskewcalhs signal means the the phy has initiated the de-skew calibration + 0 + 1 + read-only + + + + + int_st_phy_fatal + groups the phy interruptions caused by phy packets discarded + 0xe0 + 32 + 0x00000000 + 0x00000103 + + + ERR_DESKEW + reports whenever data is lost due to an existent skew between lanes greater than 2 rxwordclkhs + 8 + 1 + read-only + + + PHY_ERRSOTSYNCHS_1 + start of transmission error on data lane1 + 1 + 1 + read-only + + + PHY_ERRSOTSYNCHS_0 + start of transmission error on data lane0 + 0 + 1 + read-only + + + + + int_msk_phy_fatal + interrupt mask for int_st_phy_fatal + 0xe4 + 32 + 0x00000000 + 0x00000103 + + + ERR_DESKEW + mask for err_deskew + 8 + 1 + read-write + + + MASK_PHY_ERRSOTSYNCHS_1 + mask for phy_errsotsynchs_1 + 1 + 1 + read-write + + + MASK_PHY_ERRSOTSYNCHS_0 + mask for phy_errsotsynchs_0 + 0 + 1 + read-write + + + + + int_force_phy_fatal + interrupt force register for test purposes + 0xe8 + 32 + 0x00000000 + 0x00000103 + + + ERR_DESKEW + force err_deskew + 8 + 1 + read-write + + + FORCE_PHY_ERRSOTSYNCHS_1 + force phy_errsotsynchs_1 + 1 + 1 + read-write + + + FORCE_PHY_ERRSOTSYNCHS_0 + force phy_errsotsynchs_0 + 0 + 1 + read-write + + + + + int_st_pkt_fatal + groups the fatal interruption related with packet construction + 0xf0 + 32 + 0x00000000 + 0x00000001 + + + ERR_ECC_DOUBLE + header ecc contains at least 2 errors + 0 + 1 + read-only + + + + + int_msk_pkt_fatal + interrupt mask for int_st_pkt_fatal + 0xf4 + 32 + 0x00000000 + 0x00000001 + + + MASK_ERR_ECC_DOUBLE + mask for err_ecc_double + 0 + 1 + read-write + + + + + int_force_pkt_fatal + interrupt force register is used for test purpos + 0xf8 + 32 + 0x00000000 + 0x00000001 + + + FORCE_ERR_ECC_DOUBLE + force err_ecc_double + 0 + 1 + read-write + + + + + int_st_phy + interruption caused by phy + 0x110 + 32 + 0x00000000 + 0x00030003 + + + PHY_ERRESC_1 + start of transmission error on data lane 1 + 17 + 1 + read-only + + + PHY_ERRESC_0 + start of transmission error on data lane 0 + 16 + 1 + read-only + + + PHY_ERRSOTHS_1 + start of transmission error on data lane 1 + 1 + 1 + read-only + + + PHY_ERRSOTHS_0 + start of transmission error on data lane 0 + 0 + 1 + read-only + + + + + int_msk_phy + interrupt mask for int_st_phy + 0x114 + 32 + 0x00000000 + 0x00030003 + + + MASK_PHY_ERRESC_1 + mask for phy_erresc_1 + 17 + 1 + read-write + + + MASK_PHY_ERRESC_0 + mask for phy_erresc_0 + 16 + 1 + read-write + + + MASK_PHY_ERRSOTHS_1 + mask for phy_errsoths_1 + 1 + 1 + read-write + + + MASK_PHY_ERRSOTHS_0 + mask for phy_errsoths_0 + 0 + 1 + read-write + + + + + int_force_phy + interrupt force register + 0x118 + 32 + 0x00000000 + 0x00030003 + + + FORCE_PHY_ERRESC_1 + force phy_erresc_1 + 17 + 1 + read-write + + + FORCE_PHY_ERRESC_0 + force phy_erresc_0 + 16 + 1 + read-write + + + FORCE_PHY_ERRSOTHS_1 + force phy_errsoths_1 + 1 + 1 + read-write + + + FORCE_PHY_ERRSOTHS_0 + force phy_errsoths_0 + 0 + 1 + read-write + + + + + int_st_ipi_fatal + fatal interruption caused by ipi interface + 0x140 + 32 + 0x00000000 + 0x0000003F + + + INT_EVENT_FIFO_OVERFLOW + reporting internal fifo overflow + 5 + 1 + read-only + + + PIXEL_IF_HLINE_ERR + horizontal line time error + 4 + 1 + read-only + + + PIXEL_IF_FIFO_NEMPTY_FS + the fifo of pixel interface is not empty at the starat of a new frame + 3 + 1 + read-only + + + PIXEL_IF_FRAME_SYNC_ERR + whenever in controller mode, notifies if a new frame is received but previous has not been completed + 2 + 1 + read-only + + + PIXEL_IF_FIFO_OVERFLOW + the fifo of pixel interface has lost information because some data arrived and fifo is already full + 1 + 1 + read-only + + + PIXEL_IF_FIFO_UNDERFLOW + the fifo has become empty before the expected bumber of pixels could be extracted to the pixel intefcese + 0 + 1 + read-only + + + + + int_msk_ipi_fatal + interrupt mask for int_st_ipi_fatal + 0x144 + 32 + 0x00000000 + 0x0000003F + + + MSK_INT_EVENT_FIFO_OVERFLOW + mask int_event_fifo_overflow + 5 + 1 + read-write + + + MSK_PIXEL_IF_HLINE_ERR + mask pixel_if_hline_err + 4 + 1 + read-write + + + MSK_PIXEL_IF_FIFO_NEMPTY_FS + mask pixel_if_fifo_nempty_fs + 3 + 1 + read-write + + + MSK_FRAME_SYNC_ERR + mask for pixel_if_frame_sync_err + 2 + 1 + read-write + + + MSK_PIXEL_IF_FIFO_OVERFLOW + mask for pixel_if_fifo_overflow + 1 + 1 + read-write + + + MSK_PIXEL_IF_FIFO_UNDERFLOW + mask for pixel_if_fifo_unterflow + 0 + 1 + read-write + + + + + int_force_ipi_fatal + interrupt force register + 0x148 + 32 + 0x00000000 + 0x0000003F + + + FORCE_INT_EVENT_FIFO_OVERFLOW + force int_event_fifo_overflow + 5 + 1 + read-write + + + FORCE_PIXEL_IF_HLINE_ERR + force pixel_if_hline_err + 4 + 1 + read-write + + + FORCE_PIXEL_IF_FIFO_NEMPTY_FS + force pixel_if_fifo_nempty_fs + 3 + 1 + read-write + + + FORCE_FRAME_SYNC_ERR + force for frame_sync_err + 2 + 1 + read-write + + + FORCE_PIXEL_IF_FIFO_OVERFLOW + force for pixel_if_fifo_overflow + 1 + 1 + read-write + + + FORCE_PIXEL_IF_FIFO_UNDERFLOW + force for pixel_if_fifo_underflow + 0 + 1 + read-write + + + + + int_st_ap_generic + groups and notifies which interruption bits caused the interruption + 0x180 + 32 + 0x00000000 + 0x0001FFFF + + + SYNCHRONIZER_PIXCLK_AP_ERR + ap error in synchronizer block for pixclk domain + 16 + 1 + read-only + + + SYNCHRONIZER_RXBYTECLKHS_AP_ERR + ap error in synchronizer block for rxbyteclkhs domain + 15 + 1 + read-only + + + SYNCHRONIZER_FPCLK_AP_ERR + ap error in synchronizer block for fpclk domain + 14 + 1 + read-only + + + ERR_HANDLE_AP_ERR + ap error in error handler block + 13 + 1 + read-only + + + ERR_MSGR_AP_ERR + ap error in err msgr block + 12 + 1 + read-only + + + PREP_OUTS_AP_ERR + ap error in prepare outs block + 10 + 2 + read-only + + + PACKET_ANALYZER_AP_ERR + ap error in packet analyzer block + 8 + 2 + read-only + + + PHY_ADAPTER_AP_ERR + ap error in phy adapter block + 7 + 1 + read-only + + + DESCRAMBLER_AP_ERR + ap error in descrambler block + 6 + 1 + read-only + + + PIPELINE_DELAY_AP_ERR + ap error in pipeline delay block + 5 + 1 + read-only + + + DE_SKEW_AP_ERR + ap error in de-skew block + 4 + 1 + read-only + + + REG_BANK_AP_ERR + ap error in register bank block + 2 + 2 + read-only + + + APB_AP_ERR + ap error in apb block + 0 + 2 + read-only + + + + + int_msk_ap_generic + interrupt mask for int_st_ap_generic + 0x184 + 32 + 0x00000000 + 0x0001FFFF + + + MSK_SYNCHRONIZER_PIXCLK_AP_ERR + No description available + 16 + 1 + read-write + + + MSK_SYNCHRONIZER_RXBYTECLKHS_AP_ERR + No description available + 15 + 1 + read-write + + + MSK_SYNCHRONIZER_FPCLK_AP_ERR + No description available + 14 + 1 + read-write + + + MSK_ERR_HANDLE_AP_ERR + No description available + 13 + 1 + read-write + + + MSK_ERR_MSGR_AP_ERR + No description available + 12 + 1 + read-write + + + MSK_PREP_OUTS_AP_ERR + No description available + 10 + 2 + read-write + + + MSK_PACKET_ANALYZER_AP_ERR + No description available + 8 + 2 + read-write + + + MSK_PHY_ADAPTER_AP_ERR + No description available + 7 + 1 + read-write + + + MSK_DESCRAMBLER_AP_ERR + No description available + 6 + 1 + read-write + + + MSK_PIPELINE_DELAY_AP_ERR + No description available + 5 + 1 + read-write + + + MSK_DE_SKEW_AP_ERR + No description available + 4 + 1 + read-write + + + MSK_REG_BANK_AP_ERR + No description available + 2 + 2 + read-write + + + MSK_APB_AP_ERR + No description available + 0 + 2 + read-write + + + + + int_force_ap_generic + interrupt force register used for test purposes + 0x188 + 32 + 0x00000000 + 0x0001FFFF + + + FORCE_SYNCHRONIZER_PIXCLK_AP_ERR + No description available + 16 + 1 + read-write + + + FORCE_SYNCHRONIZER_RXBYTECLKHS_AP_ERR + No description available + 15 + 1 + read-write + + + FORCE_SYNCHRONIZER_FPCLK_AP_ERR + No description available + 14 + 1 + read-write + + + FORCE_ERR_HANDLE_AP_ERR + No description available + 13 + 1 + read-write + + + FORCE_ERR_MSGR_AP_ERR + No description available + 12 + 1 + read-write + + + FORCE_PREP_OUTS_AP_ERR + No description available + 10 + 2 + read-write + + + FORCE_PACKET_ANALYZER_AP_ERR + No description available + 8 + 2 + read-write + + + FORCE_PHY_ADAPTER_AP_ERR + No description available + 7 + 1 + read-write + + + FORCE_DESCRAMBLER_AP_ERR + No description available + 6 + 1 + read-write + + + FORCE_PIPELINE_DELAY_AP_ERR + No description available + 5 + 1 + read-write + + + FORCE_DE_SKEW_AP_ERR + No description available + 4 + 1 + read-write + + + FORCE_REG_BANK_AP_ERR + No description available + 2 + 2 + read-write + + + FORCE_APB_AP_ERR + No description available + 0 + 2 + read-write + + + + + int_st_ap_ipi_fatal + groups and notifies which interruption bits + 0x190 + 32 + 0x00000000 + 0x0000003F + + + REDUNDANCY_ERR + ap redundancy error in ipi1 + 5 + 1 + read-only + + + CRC_ERR + ap crc error in ipi1 + 4 + 1 + read-only + + + ECC_MULTIPLE_ERR + ap ecc multiple error in ipi1 + 3 + 1 + read-only + + + ECC_SINGLE_ERR + ap ecc sigle error in ipi1 + 2 + 1 + read-only + + + PARITY_RX_ERR + ap parity rx error in ipi1 + 1 + 1 + read-only + + + PARITY_TX_ERR + ap parity tx error in ipi1 + 0 + 1 + read-only + + + + + int_msk_ap_ipi_fatal + interrupt mask for int_st_ap_ipi_fatal controls + 0x194 + 32 + 0x00000000 + 0x0000003F + + + MASK_REDUNDANCY_ERR + No description available + 5 + 1 + read-only + + + MASK_CRC_ERR + No description available + 4 + 1 + read-only + + + MASK_ECC_MULTIPLE_ERR + No description available + 3 + 1 + read-only + + + MASK_ECC_SINGLE_ERR + No description available + 2 + 1 + read-only + + + MASK_PARITY_RX_ERR + No description available + 1 + 1 + read-only + + + MASK_PARITY_TX_ERR + No description available + 0 + 1 + read-only + + + + + int_force_ap_ipi_fatal + interrupt force register + 0x198 + 32 + 0x00000000 + 0x0000003F + + + FORCE_REDUNDANCY_ERR + No description available + 5 + 1 + read-only + + + FORCE_CRC_ERR + No description available + 4 + 1 + read-only + + + FORCE_ECC_MULTIPLE_ERR + No description available + 3 + 1 + read-only + + + FORCE_ECC_SINGLE_ERR + No description available + 2 + 1 + read-only + + + FORCE_PARITY_RX_ERR + No description available + 1 + 1 + read-only + + + FORCE_PARITY_TX_ERR + No description available + 0 + 1 + read-only + + + + + int_st_bndry_frame_fatal + fatal interruption related with matching frame start with frame end for a specific virtual channel + 0x280 + 32 + 0x00000000 + 0x0000FFFF + + + ERR_F_BNDRY_MATCH_VC15 + error matching frame start with frame end for virtual channel 15 + 15 + 1 + read-only + + + ERR_F_BNDRY_MATCH_VC14 + error matching frame start with frame end for virtual channel 14 + 14 + 1 + read-only + + + ERR_F_BNDRY_MATCH_VC13 + error matching frame start with frame end for virtual channel 13 + 13 + 1 + read-only + + + ERR_F_BNDRY_MATCH_VC12 + error matching frame start with frame end for virtual channel 12 + 12 + 1 + read-only + + + ERR_F_BNDRY_MATCH_VC11 + error matching frame start with frame end for virtual channel 11 + 11 + 1 + read-only + + + ERR_F_BNDRY_MATCH_VC10 + error matching frame start with frame end for virtual channel 10 + 10 + 1 + read-only + + + ERR_F_BNDRY_MATCH_VC9 + error matching frame start with frame end for virtual channel 9 + 9 + 1 + read-only + + + ERR_F_BNDRY_MATCH_VC8 + error matching frame start with frame end for virtual channel 8 + 8 + 1 + read-only + + + ERR_F_BNDRY_MATCH_VC7 + error matching frame start with frame end for virtual channel 7 + 7 + 1 + read-only + + + ERR_F_BNDRY_MATCH_VC6 + error matching frame start with frame end for virtual channel 6 + 6 + 1 + read-only + + + ERR_F_BNDRY_MATCH_VC5 + error matching frame start with frame end for virtual channel 5 + 5 + 1 + read-only + + + ERR_F_BNDRY_MATCH_VC4 + error matching frame start with frame end for virtual channel 4 + 4 + 1 + read-only + + + ERR_F_BNDRY_MATCH_VC3 + error matching frame start with frame end for virtual channel 3 + 3 + 1 + read-only + + + ERR_F_BNDRY_MATCH_VC2 + error matching frame start with frame end for virtual channel 2 + 2 + 1 + read-only + + + ERR_F_BNDRY_MATCH_VC1 + error matching frame start with frame end for virtual channel 1 + 1 + 1 + read-only + + + ERR_F_BNDRY_MATCH_VC0 + error matching frame start with frame end for virtual channel 0 + 0 + 1 + read-only + + + + + int_msk_bndry_frame_fatal + interrupt mask for int_st_bndry_frame_fatal + 0x284 + 32 + 0x00000000 + 0x0000FFFF + + + MSK_ERR_F_BNDRY_MATCH_VC15 + error matching frame start with frame end for virtual channel 15 + 15 + 1 + read-write + + + MSK_ERR_F_BNDRY_MATCH_VC14 + error matching frame start with frame end for virtual channel 14 + 14 + 1 + read-write + + + MSK_ERR_F_BNDRY_MATCH_VC13 + error matching frame start with frame end for virtual channel 13 + 13 + 1 + read-write + + + MSK_ERR_F_BNDRY_MATCH_VC12 + error matching frame start with frame end for virtual channel 12 + 12 + 1 + read-write + + + MSK_ERR_F_BNDRY_MATCH_VC11 + error matching frame start with frame end for virtual channel 11 + 11 + 1 + read-write + + + MSK_ERR_F_BNDRY_MATCH_VC10 + error matching frame start with frame end for virtual channel 10 + 10 + 1 + read-write + + + MSK_ERR_F_BNDRY_MATCH_VC9 + error matching frame start with frame end for virtual channel 9 + 9 + 1 + read-write + + + MSK_ERR_F_BNDRY_MATCH_VC8 + error matching frame start with frame end for virtual channel 8 + 8 + 1 + read-write + + + MSK_ERR_F_BNDRY_MATCH_VC7 + error matching frame start with frame end for virtual channel 7 + 7 + 1 + read-write + + + MSK_ERR_F_BNDRY_MATCH_VC6 + error matching frame start with frame end for virtual channel 6 + 6 + 1 + read-write + + + MSK_ERR_F_BNDRY_MATCH_VC5 + error matching frame start with frame end for virtual channel 5 + 5 + 1 + read-write + + + MSK_ERR_F_BNDRY_MATCH_VC4 + error matching frame start with frame end for virtual channel 4 + 4 + 1 + read-write + + + MSK_ERR_F_BNDRY_MATCH_VC3 + error matching frame start with frame end for virtual channel 3 + 3 + 1 + read-write + + + MSK_ERR_F_BNDRY_MATCH_VC2 + error matching frame start with frame end for virtual channel 2 + 2 + 1 + read-write + + + MSK_ERR_F_BNDRY_MATCH_VC1 + error matching frame start with frame end for virtual channel 1 + 1 + 1 + read-write + + + MSK_ERR_F_BNDRY_MATCH_VC0 + error matching frame start with frame end for virtual channel 0 + 0 + 1 + read-write + + + + + int_force_bndry_frame_fatal + interrupt force register is used for test purposes + 0x288 + 32 + 0x00000000 + 0x0000FFFF + + + FORCE_ERR_F_BNDRY_MATCH_VC15 + error matching frame start with frame end for virtual channel 15 + 15 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC14 + error matching frame start with frame end for virtual channel 14 + 14 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC13 + error matching frame start with frame end for virtual channel 13 + 13 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC12 + error matching frame start with frame end for virtual channel 12 + 12 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC11 + error matching frame start with frame end for virtual channel 11 + 11 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC10 + error matching frame start with frame end for virtual channel 10 + 10 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC9 + error matching frame start with frame end for virtual channel 9 + 9 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC8 + error matching frame start with frame end for virtual channel 8 + 8 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC7 + error matching frame start with frame end for virtual channel 7 + 7 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC6 + error matching frame start with frame end for virtual channel 6 + 6 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC5 + error matching frame start with frame end for virtual channel 5 + 5 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC4 + error matching frame start with frame end for virtual channel 4 + 4 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC3 + error matching frame start with frame end for virtual channel 3 + 3 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC2 + error matching frame start with frame end for virtual channel 2 + 2 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC1 + error matching frame start with frame end for virtual channel 1 + 1 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC0 + error matching frame start with frame end for virtual channel 0 + 0 + 1 + read-write + + + + + int_st_seq_frame_fatal + fatal interruption related with matching frame start with frame end for a specific virtual channel + 0x290 + 32 + 0x00000000 + 0x0000FFFF + + + ERR_F_SEQ_MATCH_VC15 + error matching frame start with frame end for virtual channel 15 + 15 + 1 + read-only + + + ERR_F_SEQ_MATCH_VC14 + error matching frame start with frame end for virtual channel 14 + 14 + 1 + read-only + + + ERR_F_SEQ_MATCH_VC13 + error matching frame start with frame end for virtual channel 13 + 13 + 1 + read-only + + + ERR_F_SEQ_MATCH_VC12 + error matching frame start with frame end for virtual channel 12 + 12 + 1 + read-only + + + ERR_F_SEQ_MATCH_VC11 + error matching frame start with frame end for virtual channel 11 + 11 + 1 + read-only + + + ERR_F_SEQ_MATCH_VC10 + error matching frame start with frame end for virtual channel 10 + 10 + 1 + read-only + + + ERR_F_SEQ_MATCH_VC9 + error matching frame start with frame end for virtual channel 9 + 9 + 1 + read-only + + + ERR_F_SEQ_MATCH_VC8 + error matching frame start with frame end for virtual channel 8 + 8 + 1 + read-only + + + ERR_F_SEQ_MATCH_VC7 + error matching frame start with frame end for virtual channel 7 + 7 + 1 + read-only + + + ERR_F_SEQ_MATCH_VC6 + error matching frame start with frame end for virtual channel 6 + 6 + 1 + read-only + + + ERR_F_SEQ_MATCH_VC5 + error matching frame start with frame end for virtual channel 5 + 5 + 1 + read-only + + + ERR_F_SEQ_MATCH_VC4 + error matching frame start with frame end for virtual channel 4 + 4 + 1 + read-only + + + ERR_F_SEQ_MATCH_VC3 + error matching frame start with frame end for virtual channel 3 + 3 + 1 + read-only + + + ERR_F_SEQ_MATCH_VC2 + error matching frame start with frame end for virtual channel 2 + 2 + 1 + read-only + + + ERR_F_SEQ_MATCH_VC1 + error matching frame start with frame end for virtual channel 1 + 1 + 1 + read-only + + + ERR_F_SEQ_MATCH_VC0 + error matching frame start with frame end for virtual channel 0 + 0 + 1 + read-only + + + + + int_msk_seq_frame_fatal + interrupt mask for int_st_seq_frame_fatal + 0x294 + 32 + 0x00000000 + 0x0000FFFF + + + MSK_ERR_F_SEQ_MATCH_VC15 + error matching frame start with frame end for virtual channel 15 + 15 + 1 + read-write + + + MSK_ERR_F_SEQ_MATCH_VC14 + error matching frame start with frame end for virtual channel 14 + 14 + 1 + read-write + + + MSK_ERR_F_SEQ_MATCH_VC13 + error matching frame start with frame end for virtual channel 13 + 13 + 1 + read-write + + + MSK_ERR_F_SEQ_MATCH_VC12 + error matching frame start with frame end for virtual channel 12 + 12 + 1 + read-write + + + MSK_ERR_F_SEQ_MATCH_VC11 + error matching frame start with frame end for virtual channel 11 + 11 + 1 + read-write + + + MSK_ERR_F_SEQ_MATCH_VC10 + error matching frame start with frame end for virtual channel 10 + 10 + 1 + read-write + + + MSK_ERR_F_SEQ_MATCH_VC9 + error matching frame start with frame end for virtual channel 9 + 9 + 1 + read-write + + + MSK_ERR_F_SEQ_MATCH_VC8 + error matching frame start with frame end for virtual channel 8 + 8 + 1 + read-write + + + MSK_ERR_F_SEQ_MATCH_VC7 + error matching frame start with frame end for virtual channel 7 + 7 + 1 + read-write + + + MSK_ERR_F_SEQ_MATCH_VC6 + error matching frame start with frame end for virtual channel 6 + 6 + 1 + read-write + + + MSK_ERR_F_SEQ_MATCH_VC5 + error matching frame start with frame end for virtual channel 5 + 5 + 1 + read-write + + + MSK_ERR_F_SEQ_MATCH_VC4 + error matching frame start with frame end for virtual channel 4 + 4 + 1 + read-write + + + MSK_ERR_F_SEQ_MATCH_VC3 + error matching frame start with frame end for virtual channel 3 + 3 + 1 + read-write + + + MSK_ERR_F_SEQ_MATCH_VC2 + error matching frame start with frame end for virtual channel 2 + 2 + 1 + read-write + + + MSK_ERR_F_SEQ_MATCH_VC1 + error matching frame start with frame end for virtual channel 1 + 1 + 1 + read-write + + + MSK_ERR_F_SEQ_MATCH_VC0 + error matching frame start with frame end for virtual channel 0 + 0 + 1 + read-write + + + + + int_force_seq_frame_fatal + interrupt force register is used for test purposes + 0x298 + 32 + 0x00000000 + 0x0000FFFF + + + FORCE_ERR_F_SEQ_MATCH_VC15 + error matching frame start with frame end for virtual channel 15 + 15 + 1 + read-write + + + FORCE_ERR_F_SEQ_MATCH_VC14 + error matching frame start with frame end for virtual channel 14 + 14 + 1 + read-write + + + FORCE_ERR_F_SEQ_MATCH_VC13 + error matching frame start with frame end for virtual channel 13 + 13 + 1 + read-write + + + FORCE_ERR_F_SEQ_MATCH_VC12 + error matching frame start with frame end for virtual channel 12 + 12 + 1 + read-write + + + FORCE_ERR_F_SEQ_MATCH_VC11 + error matching frame start with frame end for virtual channel 11 + 11 + 1 + read-write + + + FORCE_ERR_F_SEQ_MATCH_VC10 + error matching frame start with frame end for virtual channel 10 + 10 + 1 + read-write + + + FORCE_ERR_F_SEQ_MATCH_VC9 + error matching frame start with frame end for virtual channel 9 + 9 + 1 + read-write + + + FORCE_ERR_F_SEQ_MATCH_VC8 + error matching frame start with frame end for virtual channel 8 + 8 + 1 + read-write + + + FORCE_ERR_F_SEQ_MATCH_VC7 + error matching frame start with frame end for virtual channel 7 + 7 + 1 + read-write + + + FORCE_ERR_F_SEQ_MATCH_VC6 + error matching frame start with frame end for virtual channel 6 + 6 + 1 + read-write + + + FORCE_ERR_F_SEQ_MATCH_VC5 + error matching frame start with frame end for virtual channel 5 + 5 + 1 + read-write + + + FORCE_ERR_F_SEQ_MATCH_VC4 + error matching frame start with frame end for virtual channel 4 + 4 + 1 + read-write + + + FORCE_ERR_F_SEQ_MATCH_VC3 + error matching frame start with frame end for virtual channel 3 + 3 + 1 + read-write + + + FORCE_ERR_F_SEQ_MATCH_VC2 + error matching frame start with frame end for virtual channel 2 + 2 + 1 + read-write + + + FORCE_ERR_F_SEQ_MATCH_VC1 + error matching frame start with frame end for virtual channel 1 + 1 + 1 + read-write + + + FORCE_ERR_F_SEQ_MATCH_VC0 + error matching frame start with frame end for virtual channel 0 + 0 + 1 + read-write + + + + + int_st_crc_frame_fatal + fatal interruption related with matching frame start with frame end for a specific virtual channel + 0x2a0 + 32 + 0x00000000 + 0x0000FFFF + + + ERR_F_CRC_MATCH_VC15 + error matching frame start with frame end for virtual channel 15 + 15 + 1 + read-only + + + ERR_F_CRC_MATCH_VC14 + error matching frame start with frame end for virtual channel 14 + 14 + 1 + read-only + + + ERR_F_CRC_MATCH_VC13 + error matching frame start with frame end for virtual channel 13 + 13 + 1 + read-only + + + ERR_F_CRC_MATCH_VC12 + error matching frame start with frame end for virtual channel 12 + 12 + 1 + read-only + + + ERR_F_CRC_MATCH_VC11 + error matching frame start with frame end for virtual channel 11 + 11 + 1 + read-only + + + ERR_F_CRC_MATCH_VC10 + error matching frame start with frame end for virtual channel 10 + 10 + 1 + read-only + + + ERR_F_CRC_MATCH_VC9 + error matching frame start with frame end for virtual channel 9 + 9 + 1 + read-only + + + ERR_F_CRC_MATCH_VC8 + error matching frame start with frame end for virtual channel 8 + 8 + 1 + read-only + + + ERR_F_CRC_MATCH_VC7 + error matching frame start with frame end for virtual channel 7 + 7 + 1 + read-only + + + ERR_F_CRC_MATCH_VC6 + error matching frame start with frame end for virtual channel 6 + 6 + 1 + read-only + + + ERR_F_CRC_MATCH_VC5 + error matching frame start with frame end for virtual channel 5 + 5 + 1 + read-only + + + ERR_F_CRC_MATCH_VC4 + error matching frame start with frame end for virtual channel 4 + 4 + 1 + read-only + + + ERR_F_CRC_MATCH_VC3 + error matching frame start with frame end for virtual channel 3 + 3 + 1 + read-only + + + ERR_F_CRC_MATCH_VC2 + error matching frame start with frame end for virtual channel 2 + 2 + 1 + read-only + + + ERR_F_CRC_MATCH_VC1 + error matching frame start with frame end for virtual channel 1 + 1 + 1 + read-only + + + ERR_F_CRC_MATCH_VC0 + error matching frame start with frame end for virtual channel 0 + 0 + 1 + read-only + + + + + int_msk_crc_frame_fatal + interrupt mask for int_st_crc_frame_fatal + 0x2a4 + 32 + 0x00000000 + 0x0000FFFF + + + MSK_ERR_F_CRC_MATCH_VC15 + error matching frame start with frame end for virtual channel 15 + 15 + 1 + read-write + + + MSK_ERR_F_CRC_MATCH_VC14 + error matching frame start with frame end for virtual channel 14 + 14 + 1 + read-write + + + MSK_ERR_F_CRC_MATCH_VC13 + error matching frame start with frame end for virtual channel 13 + 13 + 1 + read-write + + + MSK_ERR_F_CRC_MATCH_VC12 + error matching frame start with frame end for virtual channel 12 + 12 + 1 + read-write + + + MSK_ERR_F_CRC_MATCH_VC11 + error matching frame start with frame end for virtual channel 11 + 11 + 1 + read-write + + + MSK_ERR_F_CRC_MATCH_VC10 + error matching frame start with frame end for virtual channel 10 + 10 + 1 + read-write + + + MSK_ERR_F_CRC_MATCH_VC9 + error matching frame start with frame end for virtual channel 9 + 9 + 1 + read-write + + + MSK_ERR_F_CRC_MATCH_VC8 + error matching frame start with frame end for virtual channel 8 + 8 + 1 + read-write + + + MSK_ERR_F_CRC_MATCH_VC7 + error matching frame start with frame end for virtual channel 7 + 7 + 1 + read-write + + + MSK_ERR_F_CRC_MATCH_VC6 + error matching frame start with frame end for virtual channel 6 + 6 + 1 + read-write + + + MSK_ERR_F_CRC_MATCH_VC5 + error matching frame start with frame end for virtual channel 5 + 5 + 1 + read-write + + + MSK_ERR_F_CRC_MATCH_VC4 + error matching frame start with frame end for virtual channel 4 + 4 + 1 + read-write + + + MSK_ERR_F_CRC_MATCH_VC3 + error matching frame start with frame end for virtual channel 3 + 3 + 1 + read-write + + + MSK_ERR_F_CRC_MATCH_VC2 + error matching frame start with frame end for virtual channel 2 + 2 + 1 + read-write + + + MSK_ERR_F_CRC_MATCH_VC1 + error matching frame start with frame end for virtual channel 1 + 1 + 1 + read-write + + + MSK_ERR_F_CRC_MATCH_VC0 + error matching frame start with frame end for virtual channel 0 + 0 + 1 + read-write + + + + + int_force_crc_frame_fatal + interrupt force register is used for test purposes + 0x2a8 + 32 + 0x00000000 + 0x0000FFFF + + + FORCE_ERR_F_CRC_MATCH_VC15 + error matching frame start with frame end for virtual channel 15 + 15 + 1 + read-write + + + FORCE_ERR_F_CRC_MATCH_VC14 + error matching frame start with frame end for virtual channel 14 + 14 + 1 + read-write + + + FORCE_ERR_F_CRC_MATCH_VC13 + error matching frame start with frame end for virtual channel 13 + 13 + 1 + read-write + + + FORCE_ERR_F_CRC_MATCH_VC12 + error matching frame start with frame end for virtual channel 12 + 12 + 1 + read-write + + + FORCE_ERR_F_CRC_MATCH_VC11 + error matching frame start with frame end for virtual channel 11 + 11 + 1 + read-write + + + FORCE_ERR_F_CRC_MATCH_VC10 + error matching frame start with frame end for virtual channel 10 + 10 + 1 + read-write + + + FORCE_ERR_F_CRC_MATCH_VC9 + error matching frame start with frame end for virtual channel 9 + 9 + 1 + read-write + + + FORCE_ERR_F_CRC_MATCH_VC8 + error matching frame start with frame end for virtual channel 8 + 8 + 1 + read-write + + + FORCE_ERR_F_CRC_MATCH_VC7 + error matching frame start with frame end for virtual channel 7 + 7 + 1 + read-write + + + FORCE_ERR_F_CRC_MATCH_VC6 + error matching frame start with frame end for virtual channel 6 + 6 + 1 + read-write + + + FORCE_ERR_F_CRC_MATCH_VC5 + error matching frame start with frame end for virtual channel 5 + 5 + 1 + read-write + + + FORCE_ERR_F_CRC_MATCH_VC4 + error matching frame start with frame end for virtual channel 4 + 4 + 1 + read-write + + + FORCE_ERR_F_CRC_MATCH_VC3 + error matching frame start with frame end for virtual channel 3 + 3 + 1 + read-write + + + FORCE_ERR_F_CRC_MATCH_VC2 + error matching frame start with frame end for virtual channel 2 + 2 + 1 + read-write + + + FORCE_ERR_F_CRC_MATCH_VC1 + error matching frame start with frame end for virtual channel 1 + 1 + 1 + read-write + + + FORCE_ERR_F_CRC_MATCH_VC0 + error matching frame start with frame end for virtual channel 0 + 0 + 1 + read-write + + + + + int_st_pld_crc_frame_fatal + fatal interruption related with matching frame start with frame end for a specific virtual channel + 0x2b0 + 32 + 0x00000000 + 0x0000FFFF + + + ERR_CRC_MATCH_VC15 + error matching frame start with frame end for virtual channel 15 + 15 + 1 + read-only + + + ERR_CRC_MATCH_VC14 + error matching frame start with frame end for virtual channel 14 + 14 + 1 + read-only + + + ERR_CRC_MATCH_VC13 + error matching frame start with frame end for virtual channel 13 + 13 + 1 + read-only + + + ERR_CRC_MATCH_VC12 + error matching frame start with frame end for virtual channel 12 + 12 + 1 + read-only + + + ERR_CRC_MATCH_VC11 + error matching frame start with frame end for virtual channel 11 + 11 + 1 + read-only + + + ERR_CRC_MATCH_VC10 + error matching frame start with frame end for virtual channel 10 + 10 + 1 + read-only + + + ERR_CRC_MATCH_VC9 + error matching frame start with frame end for virtual channel 9 + 9 + 1 + read-only + + + ERR_CRC_MATCH_VC8 + error matching frame start with frame end for virtual channel 8 + 8 + 1 + read-only + + + ERR_CRC_MATCH_VC7 + error matching frame start with frame end for virtual channel 7 + 7 + 1 + read-only + + + ERR_CRC_MATCH_VC6 + error matching frame start with frame end for virtual channel 6 + 6 + 1 + read-only + + + ERR_CRC_MATCH_VC5 + error matching frame start with frame end for virtual channel 5 + 5 + 1 + read-only + + + ERR_CRC_MATCH_VC4 + error matching frame start with frame end for virtual channel 4 + 4 + 1 + read-only + + + ERR_CRC_MATCH_VC3 + error matching frame start with frame end for virtual channel 3 + 3 + 1 + read-only + + + ERR_CRC_MATCH_VC2 + error matching frame start with frame end for virtual channel 2 + 2 + 1 + read-only + + + ERR_CRC_MATCH_VC1 + error matching frame start with frame end for virtual channel 1 + 1 + 1 + read-only + + + ERR_CRC_MATCH_VC0 + error matching frame start with frame end for virtual channel 0 + 0 + 1 + read-only + + + + + int_msk_pld_crc_frame_fatal + interrupt mask for int_st_crc_frame_fatal + 0x2b4 + 32 + 0x00000000 + 0x0000FFFF + + + MSK_ERR_CRC_MATCH_VC15 + error matching frame start with frame end for virtual channel 15 + 15 + 1 + read-write + + + MSK_ERR_CRC_MATCH_VC14 + error matching frame start with frame end for virtual channel 14 + 14 + 1 + read-write + + + MSK_ERR_CRC_MATCH_VC13 + error matching frame start with frame end for virtual channel 13 + 13 + 1 + read-write + + + MSK_ERR_CRC_MATCH_VC12 + error matching frame start with frame end for virtual channel 12 + 12 + 1 + read-write + + + MSK_ERR_CRC_MATCH_VC11 + error matching frame start with frame end for virtual channel 11 + 11 + 1 + read-write + + + MSK_ERR_CRC_MATCH_VC10 + error matching frame start with frame end for virtual channel 10 + 10 + 1 + read-write + + + MSK_ERR_CRC_MATCH_VC9 + error matching frame start with frame end for virtual channel 9 + 9 + 1 + read-write + + + MSK_ERR_CRC_MATCH_VC8 + error matching frame start with frame end for virtual channel 8 + 8 + 1 + read-write + + + MSK_ERR_CRC_MATCH_VC7 + error matching frame start with frame end for virtual channel 7 + 7 + 1 + read-write + + + MSK_ERR_CRC_MATCH_VC6 + error matching frame start with frame end for virtual channel 6 + 6 + 1 + read-write + + + MSK_ERR_CRC_MATCH_VC5 + error matching frame start with frame end for virtual channel 5 + 5 + 1 + read-write + + + MSK_ERR_CRC_MATCH_VC4 + error matching frame start with frame end for virtual channel 4 + 4 + 1 + read-write + + + MSK_ERR_CRC_MATCH_VC3 + error matching frame start with frame end for virtual channel 3 + 3 + 1 + read-write + + + MSK_ERR_CRC_MATCH_VC2 + error matching frame start with frame end for virtual channel 2 + 2 + 1 + read-write + + + MSK_ERR_CRC_MATCH_VC1 + error matching frame start with frame end for virtual channel 1 + 1 + 1 + read-write + + + MSK_ERR_CRC_MATCH_VC0 + error matching frame start with frame end for virtual channel 0 + 0 + 1 + read-write + + + + + int_force_pld_crc_frame_fatal + interrupt force register is used for test purposes + 0x2b8 + 32 + 0x00000000 + 0x0000FFFF + + + FORCE_ERR_CRC_MATCH_VC15 + error matching frame start with frame end for virtual channel 15 + 15 + 1 + read-write + + + FORCE_ERR_CRC_MATCH_VC14 + error matching frame start with frame end for virtual channel 14 + 14 + 1 + read-write + + + FORCE_ERR_CRC_MATCH_VC13 + error matching frame start with frame end for virtual channel 13 + 13 + 1 + read-write + + + FORCE_ERR_CRC_MATCH_VC12 + error matching frame start with frame end for virtual channel 12 + 12 + 1 + read-write + + + FORCE_ERR_CRC_MATCH_VC11 + error matching frame start with frame end for virtual channel 11 + 11 + 1 + read-write + + + FORCE_ERR_CRC_MATCH_VC10 + error matching frame start with frame end for virtual channel 10 + 10 + 1 + read-write + + + FORCE_ERR_CRC_MATCH_VC9 + error matching frame start with frame end for virtual channel 9 + 9 + 1 + read-write + + + FORCE_ERR_CRC_MATCH_VC8 + error matching frame start with frame end for virtual channel 8 + 8 + 1 + read-write + + + FORCE_ERR_CRC_MATCH_VC7 + error matching frame start with frame end for virtual channel 7 + 7 + 1 + read-write + + + FORCE_ERR_CRC_MATCH_VC6 + error matching frame start with frame end for virtual channel 6 + 6 + 1 + read-write + + + FORCE_ERR_CRC_MATCH_VC5 + error matching frame start with frame end for virtual channel 5 + 5 + 1 + read-write + + + FORCE_ERR_CRC_MATCH_VC4 + error matching frame start with frame end for virtual channel 4 + 4 + 1 + read-write + + + FORCE_ERR_CRC_MATCH_VC3 + error matching frame start with frame end for virtual channel 3 + 3 + 1 + read-write + + + FORCE_ERR_CRC_MATCH_VC2 + error matching frame start with frame end for virtual channel 2 + 2 + 1 + read-write + + + FORCE_ERR_CRC_MATCH_VC1 + error matching frame start with frame end for virtual channel 1 + 1 + 1 + read-write + + + FORCE_ERR_CRC_MATCH_VC0 + error matching frame start with frame end for virtual channel 0 + 0 + 1 + read-write + + + + + + + MIPI_CSI1 + MIPI_CSI1 + MIPI_CSI + 0xf102c000 + + + LVB + LVB + LVB + 0xf1030000 + + 0x0 + 0x6c + registers + + + + CTRL + control register + 0x0 + 32 + 0x00000000 + 0x0F0307AF + + + SPLIT_CH_REVERSE + Just for split mode, reverse two channel data + 27 + 1 + read-write + + + SPLIT_CH_MODE + Just for split mode +1: two channel pixel data are not aligned +0: two channel pixel data are aligned + 26 + 1 + read-write + + + SPLIT_HSWHBP_WIDTH + Just for split mode, the sum of HSW and HBP width is even +1: yes +0: no + 25 + 1 + read-write + + + SPLIT_MODE_EN + Split mode enable: +1: enable +0: disable +Note: when using split mode, ch0/1 should be enabled, and should select same DI + 24 + 1 + read-write + + + DI1_VSYNC_POLARITY + DI 1 vsync polarity: +1: active low +0: active high + 17 + 1 + read-write + + + DI0_VSYNC_POLARITY + DI 0 vsync polarity: +1: active low +0: active high + 16 + 1 + read-write + + + LVDS_TXCLK_SHIFT + Shift the LVDS TX PHY clock in relation to the data. +000: txck is 7'b1100011 +001: txck is 7‘b1110001 +010: txck is 7‘b1111000 +011: txck is 7‘b1000111 +100: txck is 7‘b0001111 +101: txck is 7‘b0011110 +110: txck is 7‘b0111100 +111: txck is 7‘b1100011 + 8 + 3 + read-write + + + CH1_BIT_MAPPING + Channel 1 data protocol: +1: JEIDA standard +0: SPWG standard + 7 + 1 + read-write + + + CH0_BIT_MAPPING + Channel 0 data protocol: +1: JEIDA standard +0: SPWG standard + 5 + 1 + read-write + + + CH1_SEL + Channel 1 select: +1: select DI 1 +0: select DI 0 + 3 + 1 + read-write + + + CH1_EN + Channel 1 enable: +1: enable +0: disable + 2 + 1 + read-write + + + CH0_SEL + Channel 0 select: +1: select DI 1 +0: select DI 0 + 1 + 1 + read-write + + + CH0_EN + Channel 0 enable: +1: enable +0: disable + 0 + 1 + read-write + + + + + PHY_STAT + LVDS TX PHY Status register + 0x10 + 32 + 0x00000000 + 0x00000003 + + + LVDS1_TX_PHY_PLL_LOCK + LVDS1 TX PHY PLL Lock indication Signal, 1 means pll already locked + 1 + 1 + read-only + + + LVDS0_TX_PHY_PLL_LOCK + LVDS0 TX PHY PLL Lock indication Signal, 1 means pll already locked + 0 + 1 + read-only + + + + + 2 + 0x4 + lvds0,lvds1 + PHY_POW_CTRL[%s] + no description available + 0x14 + 32 + 0x0000001F + 0x0000003F + + + PWON_PLL + pll power on + 5 + 1 + read-write + + + TXCK_PD + Power down control signal of channel txck +0: Normal operation +1: Power down channel + 4 + 1 + read-write + + + TX3_PD + Power down control signal of channel tx3 +0: Normal operation +1: Power down channel + 3 + 1 + read-write + + + TX2_PD + Power down control signal of channel tx2 +0: Normal operation +1: Power down channel + 2 + 1 + read-write + + + TX1_PD + Power down control signal of channel tx1 +0: Normal operation +1: Power down channel + 1 + 1 + read-write + + + TX0_PD + Power down control signal of channel tx0 +0: Normal operation +1: Power down channel + 0 + 1 + read-write + + + + + 10 + 0x8 + lvds0_tx0,lvds0_tx1,lvds0_tx2,lvds0_tx3,lvds0_txck,lvds1_tx0,lvds1_tx1,lvds1_tx2,lvds1_tx3,lvds1_txck + TX_PHY[%s] + no description available + 0x1c + + CTL0 + TX PHY Setting + 0x0 + 32 + 0x000A0358 + 0x001FFFFF + + + TX_IDLE + Force the high-speed differential signal to common mode. +This signal can be set during IP power up stage to prevent unexpected leakage current in TXP/TXN +0: Normal operation +1: Force TXPN /TXMN to common mode + 20 + 1 + read-write + + + TX_RTERM_EN + Inner Terminal Resistance enable +0: Disable rterm 2000ohm +1: Enable rterm 100ohm + 19 + 1 + read-write + + + TX_BUS_WIDTH + Parallel data bus width select： +000: 4-bit mode, txN_data[3:0] are valid, txN_data[11:4] can be arbitrary state. +001: 6-bit mode, txN_data[5:0] are valid, txN_data[11:6] can be arbitrary state. +010: 7-bit mode. txN_data[6:0] are valid, txN_data[11:7] can be arbitrary state. +011: 8-bit mode. txN_data[7:0] are valid, txN_data[11:8] can be arbitrary state. +100: 9-bit mode. txN_data[8:0] are valid, txN_data[11:9] can be arbitrary state. +101: 10-bit mode. txN_data[9:0] are valid, txN_data[11:10] can be arbitrary state. +110: 11-bit mode. txN_data[10:0] are valid, txN_data[11] can be arbitrary state. +111: 12-bit mode. txN_data[11:0] are valid + 16 + 3 + read-write + + + TX_PHASE_SEL + data/clock lane output phase adjustment: +0000: 0 +0001: data lane is 1/32, clock lane is 1/16 +0010: data lane is 2/32, clock lane is 2/16 +0011: data lane is 3/32, clock lane is 3/16 +0100: data lane is 4/32, clock lane is 4/16 +0101: data lane is 5/32, clock lane is 5/16 +0110: data lane is 6/32, clock lane is 6/16 +0111: data lane is 7/32, clock lane is 7/16 +1000: data lane is 8/32, clock lane is 8/16 +1001: data lane is 9/32, clock lane is 9/16 +1010: data lane is 10/32, clock lane is 10/16 +1011: data lane is 11/32, clock lane is 11/16 +1100: data lane is 12/32, clock lane is 12/16 +1101: data lane is 13/32, clock lane is 13/16 +1110: data lane is 14/32, clock lane is 14/16 +1111: data lane is 15/32, clock lane is 15/16 + 12 + 4 + read-write + + + TX_VCOM + output Common Mode Voltage adjustment(Unit: V). +0000: 0.7 +0001: 0.8 +0010: 0.9 +0011: 1.0 +0100: 1.1 +0101: 1.2 +0110: 1.3 +0111: 1.4 +1000~1111: 1.5 + 8 + 4 + read-write + + + TX_AMP + Output voltage Adjustment(Unit: mV). +0000 : 50 +0001: 100 +0010: 150 +0011: 200 +0100: 250 +0101: 300 +0110: 350 +0111: 400 +1000: 450 +1001: 500 +1010: 550 +1011~1111: 600 + 4 + 4 + read-write + + + TX_SR + output slew-rate trimming +00: slowest slew-rate; +11: fastest slew-rate + 2 + 2 + read-write + + + TX_DEEMP + output de-emphasis level trimming(Unit: dB) +00: 0 +01: 2.5 +10: 6.0 +11: 6.0 + 0 + 2 + read-write + + + + + CTL1 + TX_PHY Setting + 0x4 + 32 + 0x00000080 + 0x000FFFFF + + + TX_CTL + No description available + 0 + 20 + read-write + + + + + + + + PIXEL_MUX + PIXEL_MUX + PIXELMUX + 0xf1034000 + + 0x0 + 0x64 + registers + + + + PIXMUX + pixel path mux register + 0x0 + 32 + 0x00000000 + 0x3FFF00FF + + + RGB_EN + RGB pixel bus enable + 29 + 1 + read-write + + + RGB_SEL + RGB pixel bus selection +1: LCDC1 +0: LCDC0 + 28 + 1 + read-write + + + GWC1_EN + GWC1 pixel bus enable + 27 + 1 + read-write + + + GWC1_SEL + GWC1 pixel bus selection +1: LCDC1 +0: LCDC0 + 26 + 1 + read-write + + + GWC0_EN + GWC0 pixel bus enable + 25 + 1 + read-write + + + GWC0_SEL + GWC0 pixel bus selection +1: LCDC1 +0: LCDC0 + 24 + 1 + read-write + + + LVB_DI1_EN + LVB DI1 pixel bus enable + 23 + 1 + read-write + + + LVB_DI1_SEL + LVB DI1 pixel bus selection +1: LCDC1 +0: LCDC0 + 22 + 1 + read-write + + + LVB_DI0_EN + LVB DI0 pixel bus enable + 21 + 1 + read-write + + + LVB_DI0_SEL + LVB DI0 pixel bus selection +1: LCDC1 +0: LCDC0 + 20 + 1 + read-write + + + DSI1_EN + DSI0 pixel bus enable + 19 + 1 + read-write + + + DSI1_SEL + DSI0 pixel bus selection +1: LCDC1 +0: LCDC0 + 18 + 1 + read-write + + + DSI0_EN + DSI1 pixel bus enable + 17 + 1 + read-write + + + DSI0_SEL + DSI1 pixel bus selection +1: LCDC1 +0: LCDC0 + 16 + 1 + read-write + + + CAM1_EN + CAM1 pixel bus enable + 7 + 1 + read-write + + + CAM1_SEL + CAM1 pixel bus selection +111: Reserved +110: LCB1 +101: LCB0 +100: LCDC1 +011: LCDC0 +010: CSI1 +001: CSI0 +000: DVP + 4 + 3 + read-write + + + CAM0_EN + CAM0 pixel bus enable + 3 + 1 + read-write + + + CAM0_SEL + CAM0 pixel bus selection +111: Reserved +110: LCB1 +101: LCB0 +100: LCDC1 +011: LCDC0 +010: CSI1 +001: CSI0 +000: DVP + 0 + 3 + read-write + + + + + 2 + 0x4 + DSI0_CFG,DSI1_CFG + DSI_SETTING[%s] + no description available + 0x4 + 32 + 0x00200005 + 0xFFFF000F + + + DSI_DATA_ENABLE + DSI pixel data type enable: +Bit0: RGB565_CFG1 +Bit1: RGB565_CFG2 +Bit2: RGB565_CFG3 +Bit3: RGB666_CFG1 +Bit4: RGB666_CFG2 +Bit5: RGB888 +Bit6: RGB_10BIT +Bit7: RGB_12BIT, no support +Bit8: YUV422_12BIT, no support +Bit9: YUV422_10BIT, no support +Bit10: YUV422_8BIT, no support +Bit11:YUV420_8BIT,no support +others: Reserved + 16 + 16 + read-write + + + DSI_DATA_TYPE + DSI input pixel data type: +‘h0: RGB565_CFG1 +‘h1: RGB565_CFG2 +‘h2: RGB565_CFG3 +‘h3: RGB666_CFG1 +‘h4: RGB666_CFG2 +‘h5: RGB888 +‘h6: RGB_10BIT +‘h7: RGB_12BIT, no support +‘h8:YUV422_12BIT,no support +‘h9: YUV422_10BIT, no support +‘ha: YUV422_8BIT, no support +‘hb: YUV420_8BIT,no support +‘hc~’hf: Reserved + 0 + 4 + read-write + + + + + MISC + common register + 0xc + 32 + 0x00000000 + 0x00000003 + + + LVB_DI1_CTL + LVB DI1 optional general purpose control which is usually unused by display + 1 + 1 + read-write + + + LVB_DI0_CTL + LVB DI0 optional general purpose control which is usually unused by display + 0 + 1 + read-write + + + + + GPR_WR_D0 + gpr write-read register 0 + 0x10 + 32 + 0x0000000F + 0x07F7F3FF + + + CSI1_CFG_AP_IF_CHECK_EN + csi1 apb interface parity check enable + 22 + 5 + read-write + + + CSI1_CFG_AP_IF_INT_EN + csi1 apb interface error interrupt enable + 21 + 1 + read-write + + + CSI1_CFG_APB_SLVERROR_EN + csi1 apb interface error check enable + 20 + 1 + read-write + + + CSI0_CFG_AP_IF_CHECK_EN + csi0 apb interface parity check enable + 14 + 5 + read-write + + + CSI0_CFG_AP_IF_INT_EN + csi0 apb interface error interrupt enable + 13 + 1 + read-write + + + CSI0_CFG_APB_SLVERROR_EN + csi0 apb interface error check enable + 12 + 1 + read-write + + + DSI1_DPIUPDATECFG + dsi1 dpi update configure + 9 + 1 + read-write + + + DSI1_DPICOLORM + dsi1 dpi cholor mode control + 8 + 1 + read-write + + + DSI1_DPISHUTDN + dsi1 dpi shuntdown control + 7 + 1 + read-write + + + DSI0_DPIUPDATECFG + dsi0 dpi update configure + 6 + 1 + read-write + + + DSI0_DPICOLORM + dsi0 dpi cholor mode control + 5 + 1 + read-write + + + DSI0_DPISHUTDN + dsi0 dpi shuntdown control + 4 + 1 + read-write + + + CSI1_SOFT_RESET_N + csi controller 1 reset, active low + 3 + 1 + read-write + + + CSI0_SOFT_RESET_N + csi controller 0 reset, active low + 2 + 1 + read-write + + + DSI1_SOFT_RESET_N + dsi controller 1 reset, active low + 1 + 1 + read-write + + + DSI0_SOFT_RESET_N + dsi controller 0 reset, active low + 0 + 1 + read-write + + + + + GPR_WR_D1 + gpr write-read register 1 + 0x14 + 32 + 0x00000000 + 0x0FFFFFFF + + + JPEG_CTRL + bit0: select cam0; +bit1: select cam1; +bit2: select jpeg; +bit3: select pdma + 24 + 4 + read-write + + + PDMA_P1_CTRL + bit0: select cam0; +bit1: select cam1; +bit2: select jpeg; +bit3: select pdma + 20 + 4 + read-write + + + PDMA_P0_CTRL + bit0: select cam0; +bit1: select cam1; +bit2: select jpeg; +bit3: select pdma + 16 + 4 + read-write + + + LCDC1_P1_CTRL + bit0: select cam0; +bit1: select cam1; +bit2: select jpeg; +bit3: select pdma + 12 + 4 + read-write + + + LCDC1_P0_CTRL + bit0: select cam0; +bit1: select cam1; +bit2: select jpeg; +bit3: select pdma + 8 + 4 + read-write + + + LCDC0_P1_CTRL + bit0: select cam0; +bit1: select cam1; +bit2: select jpeg; +bit3: select pdma + 4 + 4 + read-write + + + LCDC0_P0_CTRL + bit0: select cam0; +bit1: select cam1; +bit2: select jpeg; +bit3: select pdma + 0 + 4 + read-write + + + + + GPR_WR_D2 + gpr write-read register 2 + 0x18 + 32 + 0x20003800 + 0x3EFF7FFF + + + TX_PHY0_PORT_PLL_RDY_SEL + tx phy0 port_pll_rdy_sel + 29 + 1 + read-write + + + TX_PHY0_RATE_LVDS + tx phy0 rate_lvds + 27 + 2 + read-write + + + TX_PHY0_PHY_MODE + tx phy0 phy_mode + 25 + 2 + read-write + + + TX_PHY0_REFCLK_DIV + tx phy0 refclk_div + 20 + 4 + read-write + + + TX_PHY0_IDDQ_EN + tx phy0 iddq_en + 19 + 1 + read-write + + + TX_PHY0_RESET_N + tx phy0 reset, active low + 18 + 1 + read-write + + + TX_PHY0_SHUTDOWNZ + tx phy0 shutdownz, active low + 17 + 1 + read-write + + + TX_PHY0_BYPS_CKDET + tx phy0 byps_ckdet + 16 + 1 + read-write + + + TX_PHY0_PLL_DIV + tx phy0 pll_div + 0 + 15 + read-write + + + + + GPR_WR_D3 + gpr write-read register 3 + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + TX_PHY0_PLL_CTRL + tx phy0 pll_ctrl + 0 + 32 + read-write + + + + + GPR_WR_D4 + gpr write-read register 4 + 0x20 + 32 + 0x00000900 + 0xFFFFFDFF + + + TX_PHY0_TXCK_BIST_EN + tx phy0 txck_bist_en + 31 + 1 + read-write + + + TX_PHY0_TX3_BIST_EN + tx phy0 tx3_bist_en + 30 + 1 + read-write + + + TX_PHY0_TX2_BIST_EN + tx phy0 tx2_bist_en + 29 + 1 + read-write + + + TX_PHY0_TX1_BIST_EN + tx phy0 tx1_bist_en + 28 + 1 + read-write + + + TX_PHY0_TX0_BIST_EN + tx phy0 tx0_bist_en + 27 + 1 + read-write + + + TX_PHY0_TXCK_LPBK_EN + tx_phy0 txck_lpbk_en + 26 + 1 + read-write + + + TX_PHY0_TX3_LPBK_EN + tx_phy0 tx3_lpbk_en + 25 + 1 + read-write + + + TX_PHY0_TX2_LPBK_EN + tx_phy0 tx2_lpbk_en + 24 + 1 + read-write + + + TX_PHY0_TX1_LPBK_EN + tx_phy0 tx1_lpbk_en + 23 + 1 + read-write + + + TX_PHY0_TX0_LPBK_EN + tx_phy0 tx0_lpbk_en + 22 + 1 + read-write + + + TX_PHY0_TXCK_PAT_SEL + tx phy0 txck_pat_sel + 20 + 2 + read-write + + + TX_PHY0_TX3_PAT_SEL + tx phy0 tx3_pat_sel + 18 + 2 + read-write + + + TX_PHY0_TX2_PAT_SEL + tx phy0 tx2_pat_sel + 16 + 2 + read-write + + + TX_PHY0_TX1_PAT_SEL + tx phy0 tx1_pat_sel + 14 + 2 + read-write + + + TX_PHY0_TX0_PAT_SEL + tx phy0 tx0_pat_sel + 12 + 2 + read-write + + + TX_PHY0_DSI0_PRBS_DISABLE + tx phy0 dsi0_prbs_disable + 11 + 1 + read-write + + + TX_PHY0_DSI0_PRBS_START + tx phy0 dsi0_prbs_start + 10 + 1 + read-write + + + TX_PHY0_CKPHY_CTL + tx phy0 ckphy_ctl + 0 + 9 + read-write + + + + + GPR_WR_D5 + gpr write-read register 5 + 0x24 + 32 + 0x20003800 + 0x3EFF7FFF + + + TX_PHY1_PORT_PLL_RDY_SEL + tx phy1 port_pll_rdy_sel + 29 + 1 + read-write + + + TX_PHY1_RATE_LVDS + tx phy1 rate_lvds + 27 + 2 + read-write + + + TX_PHY1_PHY_MODE + tx phy1 phy_mode + 25 + 2 + read-write + + + TX_PHY1_REFCLK_DIV + tx phy1 refclk_div + 20 + 4 + read-write + + + TX_PHY1_IDDQ_EN + tx phy1 iddq_en + 19 + 1 + read-write + + + TX_PHY1_RESET_N + tx phy1 reset, active low + 18 + 1 + read-write + + + TX_PHY1_SHUTDOWNZ + tx phy1 shutdownz, active low + 17 + 1 + read-write + + + TX_PHY1_BYPS_CKDET + tx phy1 byps_ckdet + 16 + 1 + read-write + + + TX_PHY1_PLL_DIV + tx phy1 pll_div + 0 + 15 + read-write + + + + + GPR_WR_D6 + gpr write-read register 6 + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + TX_PHY1_PLL_CTRL + tx phy1 pll_ctrl + 0 + 32 + read-write + + + + + GPR_WR_D7 + gpr write-read register 7 + 0x2c + 32 + 0x00000900 + 0xFFFFFDFF + + + TX_PHY1_TXCK_BIST_EN + tx phy1 txck_bist_en + 31 + 1 + read-write + + + TX_PHY1_TX3_BIST_EN + tx phy1 tx3_bist_en + 30 + 1 + read-write + + + TX_PHY1_TX2_BIST_EN + tx phy1 tx2_bist_en + 29 + 1 + read-write + + + TX_PHY1_TX1_BIST_EN + tx phy1 tx1_bist_en + 28 + 1 + read-write + + + TX_PHY1_TX0_BIST_EN + tx phy1 tx0_bist_en + 27 + 1 + read-write + + + TX_PHY1_TXCK_LPBK_EN + tx_phy1 txck_lpbk_en + 26 + 1 + read-write + + + TX_PHY1_TX3_LPBK_EN + tx_phy1 tx3_lpbk_en + 25 + 1 + read-write + + + TX_PHY1_TX2_LPBK_EN + tx_phy1 tx2_lpbk_en + 24 + 1 + read-write + + + TX_PHY1_TX1_LPBK_EN + tx_phy1 tx1_lpbk_en + 23 + 1 + read-write + + + TX_PHY1_TX0_LPBK_EN + tx_phy1 tx0_lpbk_en + 22 + 1 + read-write + + + TX_PHY1_TXCK_PAT_SEL + tx phy1 txck_pat_sel + 20 + 2 + read-write + + + TX_PHY1_TX3_PAT_SEL + tx phy1 tx3_pat_sel + 18 + 2 + read-write + + + TX_PHY1_TX2_PAT_SEL + tx phy1 tx2_pat_sel + 16 + 2 + read-write + + + TX_PHY1_TX1_PAT_SEL + tx phy1 tx1_pat_sel + 14 + 2 + read-write + + + TX_PHY1_TX0_PAT_SEL + tx phy1 tx0_pat_sel + 12 + 2 + read-write + + + TX_PHY1_DSI0_PRBS_DISABLE + tx phy1 dsi0_prbs_disable + 11 + 1 + read-write + + + TX_PHY1_DSI0_PRBS_START + tx phy1 dsi0_prbs_start + 10 + 1 + read-write + + + TX_PHY1_CKPHY_CTL + tx phy1 ckphy_ctl + 0 + 9 + read-write + + + + + GPR_WR_D8 + gpr write-read register 8 + 0x30 + 32 + 0x00000000 + 0xFF7C0003 + + + RX_PHY0_BRUN_IN_MODE + rx phy0 burn_in_mode + 31 + 1 + read-write + + + RX_PHY0_BURN_IN_EN_PAD + rx phy0 burn_in_en_pad + 30 + 1 + read-write + + + RX_PHY0_LPBK_MODE + rx phy0 lpbk_mode + 28 + 2 + read-write + + + RX_PHY0_BIST_FREQ_TRIM + rx phy0 bist_freq_trim + 24 + 4 + read-write + + + RX_PHY0_RX0_BIST_EN + rx phy0 rx0_bist_en rx1_bist_en + 22 + 1 + read-write + + + RX_PHY0_BIST_MODE + rx phy0 bist_mode + 21 + 1 + read-write + + + RX_PHY0_BIST_EN_PAD + rx phy0 bist_en_pad + 20 + 1 + read-write + + + RX_PHY0_BIST_EN + rx phy0 bist_en + 19 + 1 + read-write + + + RX_PHY0_BIST_CKIN_SEL + rx phy0 bist_ckin_sel + 18 + 1 + read-write + + + RX_PHY0_PHY_MODE + rx phy0 phy_mode + 0 + 2 + read-write + + + + + GPR_WR_D9 + gpr write-read register 9 + 0x34 + 32 + 0x00000000 + 0xFF7C0003 + + + RX_PHY1_BRUN_IN_MODE + rx phy1 burn_in_mode + 31 + 1 + read-write + + + RX_PHY1_BURN_IN_EN_PAD + rx phy1 burn_in_en_pad + 30 + 1 + read-write + + + RX_PHY1_LPBK_MODE + rx phy1 lpbk_mode + 28 + 2 + read-write + + + RX_PHY1_BIST_FREQ_TRIM + rx phy1 bist_freq_trim + 24 + 4 + read-write + + + RX_PHY1_RX0_BIST_EN + rx phy1 rx0_bist_en rx1_bist_en + 22 + 1 + read-write + + + RX_PHY1_BIST_MODE + rx phy1 bist_mode + 21 + 1 + read-write + + + RX_PHY1_BIST_EN_PAD + rx phy1 bist_en_pad + 20 + 1 + read-write + + + RX_PHY1_BIST_EN + rx phy1 bist_en + 19 + 1 + read-write + + + RX_PHY1_BIST_CKIN_SEL + rx phy1 bist_ckin_sel + 18 + 1 + read-write + + + RX_PHY1_PHY_MODE + rx phy1 phy_mode + 0 + 2 + read-write + + + + + GPR_RO_D0 + gpr read-only register 0 + 0x38 + 32 + 0x00000000 + 0x0000FFFF + + + TX_PHY1_CTL_O + {2'b0, +tx_phy1_tx3_ctl_o,tx_phy1_tx2_ctl_o, +tx_phy1_tx1_ctl_o,tx_phy1_tx0_ctl_o, +tx_phy1_txck_ctl_o,tx_phy1_pll_dtest_o} + 8 + 8 + read-only + + + TX_PHY0_CTL_O + {2'b0, +tx_phy0_tx3_ctl_o,tx_phy0_tx2_ctl_o, +tx_phy0_tx1_ctl_o,tx_phy0_tx0_ctl_o, +tx_phy0_txck_ctl_o,tx_phy0_pll_dtest_o} + 0 + 8 + read-only + + + + + GPR_RO_D1 + gpr read-only register 1 + 0x3c + 32 + 0x00000000 + 0x0003FFFF + + + IRQ_CSI0_AP + interrupt of csi0 ap + 17 + 1 + read-only + + + CSI0_CFG_CSI_AP_DIAG_FAULTS + csi0 ap diag faults + 5 + 12 + read-only + + + CSI0_STA_AP_IF_INT_STA + csi0 apb parity check interrupt satus + 0 + 5 + read-only + + + + + GPR_RO_D2 + gpr read-only register 2 + 0x40 + 32 + 0x00000000 + 0x0003FFFF + + + IRQ_CSI1_AP + interrupt of csi1 ap + 17 + 1 + read-only + + + CSI1_CFG_CSI_AP_DIAG_FAULTS + csi1 ap diag faults + 5 + 12 + read-only + + + CSI1_STA_AP_IF_INT_STA + csi1 apb parity check interrupt satus + 0 + 5 + read-only + + + + + GPR_RO_D3 + gpr read-only register 3 + 0x44 + 32 + 0x00000000 + 0x0000FFFF + + + RX_PHY0_RXCK_CTLO + rx phy0 rxck_ctlo + 8 + 8 + read-only + + + RX_PHY0_RX1_CTLO + rx phy0 rx1_ctlo + 4 + 4 + read-only + + + RX_PHY0_RX0_CTLO + rx phy0 rx0_ctlo + 0 + 4 + read-only + + + + + GPR_RO_D4 + gpr read-only register 4 + 0x48 + 32 + 0x00000000 + 0x0000FFFF + + + RX_PHY1_RXCK_CTLO + rx phy1 rxck_ctlo + 8 + 8 + read-only + + + RX_PHY1_RX1_CTLO + rx phy1 rx1_ctlo + 4 + 4 + read-only + + + RX_PHY1_RX0_CTLO + rx phy1 rx0_ctlo + 0 + 4 + read-only + + + + + GPR_RO_D5 + gpr read-only register 5 + 0x4c + 32 + 0x00000000 + 0x0000FFFF + + + DSI0_PRBS_STATE + dsi0_prbs_state for debug only + 12 + 4 + read-only + + + TX_PHY0_TXCK_BIST_DONE_PAD + tx phy0 txck_done_pad + 11 + 1 + read-only + + + TX_PHY0_TXCK_BIST_OK_PAD + tx phy0 txck_ok_pad + 10 + 1 + read-only + + + TX_PHY0_TXCK_BIST_DONE + tx phy0 txck_bist_done + 9 + 1 + read-only + + + TX_PHY0_TX3_BIST_DONE + tx phy0 tx3_bist_done + 8 + 1 + read-only + + + TX_PHY0_TX2_BIST_DONE + tx phy0 tx2_bist_done + 7 + 1 + read-only + + + TX_PHY0_TX1_BIST_DONE + tx phy0 tx1_bist_done + 6 + 1 + read-only + + + TX_PHY0_TX0_BIST_DONE + tx phy0 tx0_bist_done + 5 + 1 + read-only + + + TX_PHY0_TXCK_BIST_OUT + tx phy0 txck_bist_out + 4 + 1 + read-only + + + TX_PHY0_TX3_BIST_OUT + tx phy0 tx3_bist_out + 3 + 1 + read-only + + + TX_PHY0_TX2_BIST_OUT + tx phy0 tx2_bist_out + 2 + 1 + read-only + + + TX_PHY0_TX1_BIST_OUT + tx phy0 tx1_bist_out + 1 + 1 + read-only + + + TX_PHY0_TX0_BIST_OUT + tx phy0 tx0_bist_out + 0 + 1 + read-only + + + + + GPR_RO_D6 + gpr read-only register 6 + 0x50 + 32 + 0x00000000 + 0x0000FFFF + + + DSI1_PRBS_STATE + dsi1_prbs_state for debug only + 12 + 4 + read-only + + + TX_PHY1_TXCK_BIST_DONE_PAD + tx phy1 txck_done_pad + 11 + 1 + read-only + + + TX_PHY1_TXCK_BIST_OK_PAD + tx phy1 txck_ok_pad + 10 + 1 + read-only + + + TX_PHY1_TXCK_BIST_DONE + tx phy1 txck_bist_done + 9 + 1 + read-only + + + TX_PHY1_TX3_BIST_DONE + tx phy1 tx3_bist_done + 8 + 1 + read-only + + + TX_PHY1_TX2_BIST_DONE + tx phy1 tx2_bist_done + 7 + 1 + read-only + + + TX_PHY1_TX1_BIST_DONE + tx phy1 tx1_bist_done + 6 + 1 + read-only + + + TX_PHY1_TX0_BIST_DONE + tx phy1 tx0_bist_done + 5 + 1 + read-only + + + TX_PHY1_TXCK_BIST_OUT + tx phy1 txck_bist_out + 4 + 1 + read-only + + + TX_PHY1_TX3_BIST_OUT + tx phy1 tx3_bist_out + 3 + 1 + read-only + + + TX_PHY1_TX2_BIST_OUT + tx phy1 tx2_bist_out + 2 + 1 + read-only + + + TX_PHY1_TX1_BIST_OUT + tx phy1 tx1_bist_out + 1 + 1 + read-only + + + TX_PHY1_TX0_BIST_OUT + tx phy1 tx0_bist_out + 0 + 1 + read-only + + + + + GPR_RO_D7 + gpr read-only register 7 + 0x54 + 32 + 0x00000000 + 0x0000007F + + + RX_PHY0_BURN_IN_OK_PAD + rx_phy0_burn_in_ok_pad + 6 + 1 + read-only + + + RX_PHY0_RX1_BIST_DONE + rx phy0 rx1_bist_done + 5 + 1 + read-only + + + RX_PHY0_RX0_BIST_DONE + rx phy0 rx0_bist_done + 4 + 1 + read-only + + + RX_PHY0_RX1_BIST_OUT + rx phy0 rx1_bist_out + 3 + 1 + read-only + + + RX_PHY0_RX0_BIST_OUT + rx phy0 rx0_bist_out + 2 + 1 + read-only + + + RX_PHY0_BIST_OK_PAD + rx phy0 bist_ok_pad + 1 + 1 + read-only + + + RX_PHY0_BIST_DONE_PAD + rx phy0 bist_done_pad + 0 + 1 + read-only + + + + + GPR_RO_D8 + gpr read-only register 8 + 0x58 + 32 + 0x00000000 + 0x0000007F + + + RX_PHY1_BURN_IN_OK_PAD + rx_phy1_burn_in_ok_pad + 6 + 1 + read-only + + + RX_PHY1_RX1_BIST_DONE + rx phy1 rx1_bist_done + 5 + 1 + read-only + + + RX_PHY1_RX0_BIST_DONE + rx phy1 rx0_bist_done + 4 + 1 + read-only + + + RX_PHY1_RX1_BIST_OUT + rx phy1 rx1_bist_out + 3 + 1 + read-only + + + RX_PHY1_RX0_BIST_OUT + rx phy1 rx0_bist_out + 2 + 1 + read-only + + + RX_PHY1_BIST_OK_PAD + rx phy1 bist_ok_pad + 1 + 1 + read-only + + + RX_PHY1_BIST_DONE_PAD + rx phy1 bist_done_pad + 0 + 1 + read-only + + + + + GPR_RO_D9 + gpr read-only register 9 + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + + + GPR_WR1_CLR_D0 + gpr write1 set/no-write clr register + 0x60 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR_WR1_CLR_DATA + gpr register, write 1 /no-write set/clr matching bit + 0 + 32 + read-write + + + + + + + LCB + LCB + LCB + 0xf1038000 + + 0x0 + 0x98 + registers + + + + CTRL + control register + 0x0 + 32 + 0x00000010 + 0x000001F3 + + + LVDS_RXCK_SEL + just for LVDS Display mode and CAM LINK mode, clock selection: +1: LVDS1 RXCK +0: LVDS0 RXCK + 8 + 1 + read-write + + + CAM_LINK_WIDTH + just for CAM LINK mode, data width: +00: 24bit +01: 30bit +10: 36bit +11: reserved + 6 + 2 + read-write + + + BIT_MAPPING + just for LVDS Display mode, data protocol: +1: JEIDA standard +0: SPWG standard + 5 + 1 + read-write + + + DATA_WIDTH + just for LVDS Display mode, data width: +1: 24bit +0: 18bit(3line) + 4 + 1 + read-write + + + MODE + mode selection： +00: lvds display(4 line), two LVDS RX PHY must be LVDS display mode +01: cam link(4 line), two LVDS RX PHY must be LVDS display mode +10: sync code(2 line), LVDS RX PHY must be LVDS cameral mode +11: sync code(1line), LVDS RX PHY must be LVDS cameral mode + 0 + 2 + read-write + + + + + PHY_STAT + LVDS RX PHY Status register + 0x64 + 32 + 0x00000000 + 0x00000003 + + + LVDS1_RX_PHY_DLL_LOCK + LVDS1 RX PHY DLL Lock indication Signal, 1 means dll already locked + 1 + 1 + read-only + + + LVDS0_RX_PHY_DLL_LOCK + LVDS0 RX PHY DLL Lock indication Signal, 1 means dll already locked + 0 + 1 + read-only + + + + + 2 + 0x4 + lvds0,lvds1 + PHY_POW_CTRL[%s] + no description available + 0x68 + 32 + 0x0000000F + 0x0000000F + + + IDDQ_EN + Power down control signal of channel rxck/rx1/rx0 +0: Normal operation +1: Power down channel + 3 + 1 + read-write + + + RXCK_PD + Power down control signal of channel rxck +0: Normal operation +1: Power down channel + 2 + 1 + read-write + + + RX1_PD + Power down control signal of channel rx1 +0: Normal operation +1: Power down channel + 1 + 1 + read-write + + + RX0_PD + Power down control signal of channel rx0 +0: Normal operation +1: Power down channel + 0 + 1 + read-write + + + + + 4 + 0x4 + lvds0_rx0,lvds0_rx1,lvds1_rx0,lvds1_rx1 + PHY_D_CTRL[%s] + no description available + 0x70 + 32 + 0x00080E29 + 0x003FFFFF + + + RX_VCOM + bit 1: Receiver hysteresis enable signal. 0: enable; 1: disable +bit 0: Terminal impedance common mode selection control signal. 0: floating; 1: Ground + 20 + 2 + read-write + + + RX_RTERM + Terminal impedance regulation control signal +0000: hi-z; +0001: 150ohm; +1000:100ohm; +1111:75ohm + 16 + 4 + read-write + + + RX_CTL + bit 0 : Lane N Data MSB first enable signal. 0: LSB ; 1: MSB +bit 1 : Lane N Data Polarity signal. 0: Not inverting; 1: Inverting +bit [4:2] : Phase difference between the output first bit data (rxN[6:0]) and the input clock (RCKP/N) in LVDS Display Mode. +bit 5 : Reserved +bit 6 : Output data sampling clock control signal +0: Sampling using the rising edge of the clock pck. +1: Sampling using the falling edge of the clock pck. +bit 7 : Reserved +bit 8 : Data Lane N Skew adjust enable in LVDS Camera Mode. +bit [12:9] : Data Lane N Skew adjust; 0000: min; 0111: default; 1111: max. +bit [15:13] : Reserved + 0 + 16 + read-write + + + + + 2 + 0x4 + lvds0_rxck,lvds1_rxck + PHY_CK_CTRL[%s] + no description available + 0x80 + 32 + 0x00080435 + 0x003FFFFF + + + RX_VCOM + bit 1: Receiver hysteresis enable signal. 0: enable; 1: disable +bit 0: Terminal impedance common mode selection control signal. 0: floating; 1: Ground + 20 + 2 + read-write + + + RX_RTERM + Terminal impedance regulation control signal +0000: hi-z; +0001: 150ohm; +1000:100ohm; +1111:75ohm + 16 + 4 + read-write + + + RX_CTL + bit 0 : DLL loop delay adjustment minimum control signal +0: used for RCKP/RCKN’s frequency is 40Mhz~70Mhz +1:used for RCKP/RCKN’s frequency is 70Mhz~110Mhz +bit [2:1] : DLL loop delay adjustment current regulation control signal. 00: min; 11: max +bit 3 : Reserved +bit 4 : Clock Lane Skew adjust enable in LVDS Camera Mode. +bit [7:5] : Bus width selection in LVDS Camera Mode +000: 4bit; 001:6bit; 010:7bit; 011:8bit; 100:9bit; 101:10bit; 110:11bit; 111:12bit. +bit [10:8] : DDR Clock duty cycle adjust in LVDS Camera Mode. +bit [15:11] : Reserved + 0 + 16 + read-write + + + + + 2 + 0x4 + lvds0,lvds1 + PHY_ADJ_CTRL[%s] + no description available + 0x88 + 32 + 0x414101FF + 0xFFFF01FF + + + LVDS_RX0_DLINE_ADJ + LVDS RX PHY RX0 line: +bit [7:0] : Lane N skew adjustment control signal between data and clock +0000000: max; 1111111: min +bit 8 : Reserved + 24 + 8 + read-write + + + LVDS_RX1_DLINE_ADJ + LVDS RX PHY RX1 line: +bit [7:0] : Lane N skew adjustment control signal between data and clock +0000000: max; 1111111: min +bit 8 : Reserved + 16 + 8 + read-write + + + LVDS_DLL_TUNING_INT + LVDS RX PHY RXCK line: +DLL loop delay coarse adjustment initial signal +00000000: min ; 11111111: max + 0 + 9 + read-write + + + + + 2 + 0x4 + lvds0,lvds1 + PHY_SU_CTRL[%s] + no description available + 0x90 + 32 + 0x00000001 + 0x000000FF + + + SU_CTRL + bit [2:0] : Reference voltage/current adjustment control signal. 000: min; 111: max +bit [3] : Internal bias circuit selection signal. 0: from Bandgap Mode; 1: from self-bias mode +bit [7:4] : Reserved + 0 + 8 + read-write + + + + + + + GPU + GPU + GPU + 0xf1080000 + + 0x0 + 0x50c + registers + + + + AQHiClockControl + clock control register + 0x0 + 32 + 0x00070100 + 0x000F3FFE + + + ISOLATE_GPU + isolate GPU bit, used for power on/off + 19 + 1 + read-write + + + IDLE_VG + vg pipe is idle + 18 + 1 + read-only + + + IDLE2_D + 2D pipe is idle or not present + 17 + 1 + read-only + + + IDLE3_D + 3D pipe is idle or not present + 16 + 1 + read-only + + + DISABLE_RAM_POWER_OPTIMIZATION + disables ram power optimization + 13 + 1 + read-write + + + SOFT_RESET + soft reset the IP + 12 + 1 + read-write + + + DISABLE_DEBUG_REGISTERS + disable debug registers + 11 + 1 + read-write + + + DISABLE_RAM_CLOCK_GATING + disables clock gating for rams + 10 + 1 + read-write + + + FSCALE_CMD_LOAD + core clock frequency scale value enable + 9 + 1 + read-write + + + FSCALE_VAL + core clock frequency scale value + 2 + 7 + read-write + + + CLK2D_DIS + disable 2D/VG clock + 1 + 1 + read-write + + + + + AQHildle + idle status register + 0x4 + 32 + 0x80001FFF + 0x80001FFF + + + AXI_LP + axi is in low power mode + 31 + 1 + read-only + + + IDLE_BLT + BLT is idle or not present + 12 + 1 + read-only + + + IDLE_TS + Tessellation Engine is idle + 11 + 1 + read-only + + + IDLE_FP + FP is idle or not present + 10 + 1 + read-only + + + IDLE_IM + Image Engine is idle + 9 + 1 + read-only + + + IDLE_VG + Vector Graphics Engine is idle + 8 + 1 + read-only + + + IDLE_TX + TX is idle or not present + 7 + 1 + read-only + + + IDLE_RA + RA is idle or not present + 6 + 1 + read-only + + + IDLE_SE + SE is idle or not present + 5 + 1 + read-only + + + IDLE_PA + PA is idle or not present + 4 + 1 + read-only + + + IDLE_SH + SH is idle or not present + 3 + 1 + read-only + + + IDLE_PE + Pixel engine is idle + 2 + 1 + read-only + + + IDLE_DE + DE is dile or not present + 1 + 1 + read-only + + + IDLE_FE + 0: fetch engine is busy 1:fetch engine is idle + 0 + 1 + read-only + + + + + AQIntrAcknowledge + interrupt acknoledge register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTR_VEC + for each interrupt event, 0=clear,1=interrupt active + 0 + 32 + read-only + + + + + AQIntrEnbl + interrupt enable register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTR_ENBL_VEC + 0=disable interrupt; 1=enable interrupt + 0 + 32 + read-write + + + + + GCChipRev + chip revison register + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + REV + revision + 0 + 32 + read-only + + + + + GCChipDate + chip date register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATE + date + 0 + 32 + read-only + + + + + gcregHIChipPatchRev + chip patch revision register + 0x98 + 32 + 0x00000000 + 0x000000FF + + + PATCH_REV + patch revision + 0 + 8 + read-only + + + + + gcProductID + product identification register + 0xa8 + 32 + 0x03002655 + 0x0FFFFFFF + + + TYPE + product type is 3:VG + 24 + 4 + read-only + + + NUM + product number is 265 + 4 + 20 + read-only + + + GRADE_LEVEL + 0:None_no extra letter on the product name for this core 1:nano 5:nano ultra + 0 + 4 + read-only + + + + + gcModulePowerControls + module power control register + 0x100 + 32 + 0x00000020 + 0xFFFF00F7 + + + TURN_OFF_COUNTER + counter value for clock gating the module if the module is idle for this amout of clock cycles + 16 + 16 + read-write + + + TURN_ON_COUNTER + number of clock cycle gating the module if the modules is idle for this amout of clockk cycles + 4 + 4 + read-write + + + DISABLE_STARVE_MODULE_CLOCK_GATING + disable module level clock gating for starve/idle condition + 2 + 1 + read-write + + + DISABLE_STALL_MODULE_CLOCK_GATING + disable module level clock gating for stall condition + 1 + 1 + read-write + + + ENABLE_MODULE_CLOCK_GATING + enable module level clock gating + 0 + 1 + read-write + + + + + gcModulePowerModuleControl + module power module control register + 0x104 + 32 + 0x00000000 + 0x00001B05 + + + DISABLE_MODULE_CLOCKGATING_FLEXA + disables module level clock gating for flexa, not supported for all variants + 12 + 1 + read-write + + + DISABLE_MODULE_CLOCK_GATING_TS + disables module level clock gating for TS + 11 + 1 + read-write + + + DISABLE_MODULE_CLOCK_GATING_IM + disables module level clock gating for IM + 9 + 1 + read-write + + + DISABLE_MODULE_CLOCK_GATING_VG + disables module lelvel clock gating for VG + 8 + 1 + read-write + + + DISABLE_MODULE_CLOCK_GATING_PE + disables module level clock gating for PE + 2 + 1 + read-write + + + DISABLE_MODULE_CLOCK_GATING_FE + disables module level clock gating for FE + 0 + 1 + read-write + + + + + gcModulePowerModuleStatus + module power module status register + 0x108 + 32 + 0x00000000 + 0x00001B05 + + + MODULE_CLOCK_GATED_FLEXA + module level ckock gating is on for flexa + 12 + 1 + read-only + + + MODULE_CLOCK_GATED_TS + module level ckock gating is on for ts + 11 + 1 + read-only + + + MODULE_CLOCK_GATED_IM + module level clock gating is on for IM + 9 + 1 + read-only + + + MODULE_CLOCK_GATED_VG + module level clock gating is on for VG + 8 + 1 + read-only + + + MODULE_CLOCK_GATED_PE + module level clock gating is on for PE + 2 + 1 + read-only + + + MODULE_CLOCK_GATED_FE + module level clock gating is on for FE + 0 + 1 + read-only + + + + + AQMemoryFePageTable + fetch engine page table base address register + 0x400 + 32 + 0x00000000 + 0xFFFFF000 + + + BASE_ADDRESS + base address for the FE virtual address lookup table + 12 + 20 + read-write + + + + + AQMemoryDebug + memory debug register + 0x414 + 32 + 0x3C000000 + 0x3F0000FF + + + ZCOMP_LIMIT + not relevant for vector graphics IP + 24 + 6 + read-write + + + MAX_OUTSTANDING_READS + limits the total number of outstanding read requests + 0 + 8 + read-write + + + + + AQRegisterTimingControl + timing control register + 0x42c + 32 + 0x00030000 + 0x001FFFFF + + + POWER_DOWN + powerdown memory + 20 + 1 + read-write + + + FAST_WTC + WTC for fast rams + 18 + 2 + read-write + + + FAST_RTC + RTC for fast rams + 16 + 2 + read-write + + + FOR_RF2P + for 2 port ram + 8 + 8 + read-write + + + FOR_RF1P + for 1 port ram + 0 + 8 + read-write + + + + + gcregFetchAddress + fetch command buffer base address register + 0x500 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDRESS + address of command buffer + 2 + 30 + read-write + + + TYPE + 0=system 2=vritual 1=local + 0 + 2 + read-write + + + + + gcregFetchControl + fetch control register + 0x504 + 32 + 0x00000000 + 0x001FFFFF + + + COUNT + number of 64bit words to fetch + 0 + 21 + read-write + + + + + gcregCurrentFetchAddress + current fetch command address register + 0x508 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDRESS + address + 0 + 32 + read-only + + + + + + + ENET0 + ENET0 + ENET + 0xf1100000 + + 0x0 + 0x3028 + registers + + + + MACCFG + MAC Configuration Register + 0x0 + 32 + 0x00000000 + 0x7FFFFFFF + + + SARC + Source Address Insertion or Replacement Control + This field controls the source address insertion or replacement for all transmitted frames. Bit 30 specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits [29:28]: +- 2'b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field generation. +- 2'b10: - If Bit 30 is set to 0, the MAC inserts the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, the MAC inserts the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. +- 2'b11: - If Bit 30 is set to 0, the MAC replaces the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, the MAC replaces the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. Note: - Changes to this field take effect only on the start of a frame. If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, that is, the current frame does not use the updated value. - These bits are reserved and RO when the Enable SA, VLAN, and CRC Insertion on TX feature is not selected during core configuration. + 28 + 3 + read-write + + + TWOKPE + IEEE 802.3as Support for 2K Packets + When set, the MAC considers all frames, with up to 2,000 bytes length, as normal packets. When Bit 20 (JE) is not set, the MAC considers all received frames of size more than 2K bytes as Giant frames. When this bit is reset and Bit 20 (JE) is not set, the MAC considers all received frames of size more than 1,518 bytes (1,522 bytes for tagged) as Giant frames. When Bit 20 is set, setting this bit has no effect on Giant Frame status. + 27 + 1 + read-write + + + SFTERR + SMII Force Transmit Error + When set, this bit indicates to the PHY to force a transmit error in the SMII frame being transmitted. This bit is reserved if the SMII PHY port is not selected during core configuration. + 26 + 1 + read-write + + + CST + CRC Stripping for Type Frames + When this bit is set, the last 4 bytes (FCS) of all frames of Ether type (Length/Type field greater than or equal to 1,536) are stripped and dropped before forwarding the frame to the application. This function is not valid when the IP Checksum Engine (Type 1) is enabled in the MAC receiver. This function is valid when Type 2 Checksum Offload Engine is enabled. + 25 + 1 + read-write + + + TC + Transmit Configuration in RGMII, SGMII, or SMII + When set, this bit enables the transmission of duplex mode, link speed, and link up or down information to the PHY in the RGMII, SMII, or SGMII port. When this bit is reset, no such information is driven to the PHY. This bit is reserved (and RO) if the RGMII, SMII, or SGMII PHY port is not selected during core configuration. + 24 + 1 + read-write + + + WD + Watchdog Disable + When this bit is set, the MAC disables the watchdog timer on the receiver. The MAC can receive frames of up to 16,383 bytes. + 23 + 1 + read-write + + + JD + Jabber Disable + When this bit is set, the MAC disables the jabber timer on the transmitter. The MAC can transfer frames of up to 16,383 bytes. When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission. + 22 + 1 + read-write + + + BE + Frame Burst Enable + When this bit is set, the MAC allows frame bursting during transmission in the GMII half-duplex mode. This bit is reserved (and RO) in the 10/100 Mbps only or full-duplex-only configurations. + 21 + 1 + read-write + + + JE + Jumbo Frame Enable + When this bit is set, the MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status. + 20 + 1 + read-write + + + IFG + Inter-Frame Gap + These bits control the minimum IFG between frames during transmission. +- 000: 96 bit times +- 001: 88 bit times +- 010: 80 bit times - ... +- 111: 40 bit times In the half-duplex mode, the minimum IFG can be configured only for 64 bit times (IFG = 100). Lower values are not considered. In the 1000-Mbps mode, the minimum IFG supported is 64 bit times (and above) in the GMAC-CORE configuration and 80 bit times (and above) in other configurations. When a JAM pattern is being transmitted because of backpressure activation, the MAC does not consider the minimum IFG. + 17 + 3 + read-write + + + DCRS + Disable Carrier Sense During Transmission + When set high, this bit makes the MAC transmitter ignore the (G)MII CRS signal during frame transmission in the half-duplex mode. This request results in no errors generated because of Loss of Carrier or No Carrier during such transmission. When this bit is low, the MAC transmitter generates such errors because of Carrier Sense and can even abort the transmissions. + 16 + 1 + read-write + + + PS + Port Select + This bit selects the Ethernet line speed. +- 0: For 1000 Mbps operations +- 1: For 10 or 100 Mbps operations In 10 or 100 Mbps operations, this bit, along with FES bit, selects the exact line speed. In the 10/100 Mbps-only (always 1) or 1000 Mbps-only (always 0) configurations, this bit is read-only with the appropriate value. In default 10/100/1000 Mbps configuration, this bit is R_W. The mac_portselect_o or mac_speed_o[1] signal reflects the value of this bit. + 15 + 1 + read-write + + + FES + Speed + This bit selects the speed in the MII, RMII, SMII, RGMII, SGMII, or RevMII interface: +- 0: 10 Mbps +- 1: 100 Mbps This bit is reserved (RO) by default and is enabled only when the parameter SPEED_SELECT = Enabled. This bit generates link speed encoding when Bit 24 (TC) is set in the RGMII, SMII, or SGMII mode. This bit is always enabled for RGMII, SGMII, SMII, or RevMII interface. In configurations with RGMII, SGMII, SMII, or RevMII interface, this bit is driven as an output signal (mac_speed_o[0]) to reflect the value of this bit in the mac_speed_o signal. In configurations with RMII, MII, or GMII interface, you can optionally drive this bit as an output signal (mac_speed_o[0]) to reflect its value in the mac_speed_o signal. + 14 + 1 + read-write + + + DO + Disable Receive Own + When this bit is set, the MAC disables the reception of frames when the phy_txen_o is asserted in the half-duplex mode. When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting. This bit is not applicable if the MAC is operating in the full-duplex mode. This bit is reserved (RO with default value) if the MAC is configured for the full-duplex-only operation. + 13 + 1 + read-write + + + LM + Loopback Mode + When this bit is set, the MAC operates in the loopback mode at GMII or MII. The (G)MII Receive clock input (clk_rx_i) is required for the loopback to work properly, because the Transmit clock is not looped-back internally. + 12 + 1 + read-write + + + DM + Duplex Mode + When this bit is set, the MAC operates in the full-duplex mode where it can transmit and receive simultaneously. + 11 + 1 + read-write + + + IPC + Checksum Offload +When this bit is set, the MAC calculates the 16-bit one’s complement of the one’s complement sum of all received Ethernet frame payloads. It also checks whether the IPv4 Header checksum (assumed to be bytes 25–26 or 29–30 (VLAN-tagged) of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word. The MAC also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the IPv4 header) and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected). When this bit is reset, this function is disabled. When Type 2 COE is selected, this bit, when set, enables the IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking. + 10 + 1 + read-write + + + DR + Disable Retry +When this bit is set, the MAC attempts only one transmission. When a collision occurs on the GMII or MII interface, the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset, the MAC attempts retries based on the settings of the BL field (Bits [6:5]). + 9 + 1 + read-write + + + LUD + Link Up or Down + This bit indicates whether the link is up or down during the transmission of configuration in the RGMII, SGMII, or SMII interface: +- 0: Link Down +- 1: Link Up + 8 + 1 + read-write + + + ACS + Automatic Pad or CRC Stripping + When this bit is set, the MAC strips the Pad or FCS field on the incoming frames only if the value of the length field is less than 1,536 bytes. All received frames with length field greater than or equal to 1,536 bytes are passed to the application without stripping the Pad or FCS field. When this bit is reset, the MAC passes all incoming frames, without modifying them, to the Host. + 7 + 1 + read-write + + + BL + Back-Off Limit + The Back-Off limit determines the random integer number (r) of slot time delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only in the half-duplex mode and is reserved (RO) in the full-duplex-only configuration. +- 00: k= min (n, 10) +- 01: k = min (n, 8) +- 10: k = min (n, 4) +- 11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0 ≤ r < 2k + 5 + 2 + read-write + + + DC + Deferral Check + When this bit is set, the deferral check function is enabled in the MAC. The MAC issues a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status, when the transmit state machine is deferred for more than 24,288 bit times in the 10 or 100 Mbps mode. If the MAC is configured for 1000 Mbps operation or if the Jumbo frame mode is enabled in the 10 or 100 Mbps mode, the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, but it is prevented because of an active carrier sense signal (CRS) on GMII or MII. The defer time is not cumulative. For example, if the transmitter defers for 10,000 bit times because the CRS signal is active and then the CRS signal becomes inactive, the transmitter transmits and collision happens. Because of collision, the transmitter needs to back off and then defer again after back off completion. In such a scenario, the deferral timer is reset to 0 and it is restarted. + 4 + 1 + read-write + + + TE + Transmitter Enable + When this bit is set, the transmit state machine of the MAC is enabled for transmission on the GMII or MII. When this bit is reset, the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and does not transmit any further frames. + 3 + 1 + read-write + + + RE + Receiver Enable + When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the GMII or MII. When this bit is reset, the MAC receive state machine is disabled after the completion of the reception of the current frame, and does not receive any further frames from the GMII or MII. + 2 + 1 + read-write + + + PRELEN + Preamble Length for Transmit frames + These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode. +- 2'b00: 7 bytes of preamble +- 2'b01: 5 bytes of preamble +- 2'b10: 3 bytes of preamble +- 2'b11: Reserved + 0 + 2 + read-write + + + + + MACFF + MAC Frame Filter + 0x4 + 32 + 0x00000000 + 0x803087FF + + + RA + Receive All + When this bit is set, the MAC Receiver module passes all received frames, irrespective of whether they pass the address filter or not, to the Application. The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, the Receiver module passes only those frames to the Application that pass the SA or DA address filter. + 31 + 1 + read-write + + + DNTU + Drop non-TCP/UDP over IP Frames + When set, this bit enables the MAC to drop the non-TCP or UDP over IP frames. The MAC forward only those frames that are processed by the Layer 4 filter. When reset, this bit enables the MAC to forward all non-TCP or UDP over IP frames. + 21 + 1 + read-write + + + IPFE + Layer 3 and Layer 4 Filter Enable + When set, this bit enables the MAC to drop frames that do not match the enabled Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for matching, this bit does not have any effect. When reset, the MAC forwards all frames irrespective of the match status of the Layer 3 and Layer 4 fields. + 20 + 1 + read-write + + + VTFE + VLAN Tag Filter Enable + When set, this bit enables the MAC to drop VLAN tagged frames that do not match the VLAN Tag comparison. When reset, the MAC forwards all frames irrespective of the match status of the VLAN Tag. + 15 + 1 + read-write + + + HPF + Hash or Perfect Filter + When this bit is set, it configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by the HMC or HUC bits. When this bit is low and the HUC or HMC bit is set, the frame is passed only if it matches the Hash filter. + 10 + 1 + read-write + + + SAF + Source Address Filter Enable + When this bit is set, the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison fails, the MAC drops the frame. When this bit is reset, the MAC forwards the received frame to the application with updated SAF bit of the Rx Status depending on the SA address comparison. + 9 + 1 + read-write + + + SAIF + SA Inverse Filtering +When this bit is set, the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter. When this bit is reset, frames whose SA does not match the SA registers are marked as failing the SA Address filter. + 8 + 1 + read-write + + + PCF + Pass Control Frames + These bits control the forwarding of all control frames (including unicast and multicast Pause frames). +- 00: MAC filters all control frames from reaching the application. +- 01: MAC forwards all control frames except Pause frames to application even if they fail the Address filter. +- 10: MAC forwards all control frames to application even if they fail the Address Filter. +- 11: MAC forwards control frames that pass the Address Filter. The following conditions should be true for the Pause frames processing: - Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register 6 (Flow Control Register) to 1. - Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register 6 (Flow Control Register) is set. - Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001. Note: This field should be set to 01 only when the Condition 1 is true, that is, the MAC is programmed to operate in the full-duplex mode and the RFE bit is enabled. Otherwise, the Pause frame filtering may be inconsistent. When Condition 1 is false, the Pause frames are considered as generic control frames. Therefore, to pass all control frames (including Pause frames) when the full-duplex mode and flow control is not enabled, you should set the PCF field to 10 or 11 (as required by the application). + 6 + 2 + read-write + + + DBF + Disable Broadcast Frames + When this bit is set, the AFM module blocks all incoming broadcast frames. In addition, it overrides all other filter settings. When this bit is reset, the AFM module passes all received broadcast frames. + 5 + 1 + read-write + + + PM + Pass All Multicast +When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. When reset, filtering of multicast frame depends on HMC bit. + 4 + 1 + read-write + + + DAIF + DA Inverse Filtering + When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. When reset, normal filtering of frames is performed. + 3 + 1 + read-write + + + HMC + Hash Multicast +When set, the MAC performs destination address filtering of received multicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers. + 2 + 1 + read-write + + + HUC + Hash Unicast + When set, the MAC performs destination address filtering of unicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers. + 1 + 1 + read-write + + + PR + Promiscuous Mode +When this bit is set, the Address Filter module passes all incoming frames irrespective of the destination or source address. The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR is set. + 0 + 1 + read-write + + + + + HASH_H + Hash Table High Register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + HTH + Hash Table High + This field contains the upper 32 bits of the Hash table. + 0 + 32 + read-write + + + + + HASH_L + Hash Table Low Register + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + HTL + Hash Table Low + This field contains the lower 32 bits of the Hash table. + 0 + 32 + read-write + + + + + GMII_ADDR + GMII Address Register + 0x10 + 32 + 0x00000000 + 0x0000FFFF + + + PA + Physical Layer Address + This field indicates which of the 32 possible PHY devices are being accessed. For RevMII, this field gives the PHY Address of the RevMII module. + 11 + 5 + read-write + + + GR + GMII Register + These bits select the desired GMII register in the selected PHY device. For RevMII, these bits select the desired CSR register in the RevMII Registers set. + 6 + 5 + read-write + + + CR + CSR Clock Range + The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design. The CSR clock corresponding to different GMAC configurations is given in Table 9-2 on page 564. The suggested range of CSR clock frequency applicable for each value (when Bit[5] = 0) ensures that the MDC clock is approximately between the frequency range 1.0 MHz–2.5 MHz. +- 0000: The CSR clock frequency is 60–100 MHz and the MDC clock frequency is CSR clock/42. +- 0001: The CSR clock frequency is 100–150 MHz and the MDC clock frequency is CSR clock/62. +- 0010: The CSR clock frequency is 20–35 MHz and the MDC clock frequency is CSR clock/16. +- 0011: The CSR clock frequency is 35–60 MHz and the MDC clock frequency is CSR clock/26. +- 0100: The CSR clock frequency is 150–250 MHz and the MDC clock frequency is CSR clock/102. +- 0101: The CSR clock frequency is 250–300 MHz and the MDC clock is CSR clock/124. +- 0110, 0111: Reserved When Bit 5 is set, you can achieve higher frequency of the MDC clock than the frequency limit of 2.5 MHz (specified in the IEEE Std 802.3) and program a clock divider of lower value. For example, when CSR clock is of 100 MHz frequency and you program these bits as 1010, then the resultant MDC clock is of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. Program the following values only if the interfacing chips support faster MDC clocks. +- 1000: CSR clock/4 +- 1001: CSR clock/6 +- 1010: CSR clock/8 +- 1011: CSR clock/10 +- 1100: CSR clock/12 +- 1101: CSR clock/14 +- 1110: CSR clock/16 +- 1111: CSR clock/18 These bits are not used for accessing RevMII. These bits are read-only if the RevMII interface is selected as single PHY interface. + 2 + 4 + read-write + + + GW + GMII Write + When set, this bit indicates to the PHY or RevMII that this is a Write operation using the GMII Data register. If this bit is not set, it indicates that this is a Read operation, that is, placing the data in the GMII Data register. + 1 + 1 + read-write + + + GB + GMII Busy + This bit should read logic 0 before writing to Register 4 and Register 5. During a PHY or RevMII register access, the software sets this bit to 1’b1 to indicate that a Read or Write access is in progress. Register 5 is invalid until this bit is cleared by the MAC. Therefore, Register 5 (GMII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. Similarly for a read operation, the contents of Register 5 are not valid until this bit is cleared. The subsequent read or write operation should happen only after the previous operation is complete. Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed, there is no change in the functionality of this bit even when the PHY is not present. + 0 + 1 + read-write + + + + + GMII_DATA + GMII Data Register + 0x14 + 32 + 0x00000000 + 0x0000FFFF + + + GD + GMII Data + This field contains the 16-bit data value read from the PHY or RevMII after a Management Read operation or the 16-bit data value to be written to the PHY or RevMII before a Management Write operation. + 0 + 16 + read-write + + + + + FLOWCTRL + Flow Control Register + 0x18 + 32 + 0x00000000 + 0xFFFF00BF + + + PT + Pause Time + This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the (G)MII clock domain, then consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain. + 16 + 16 + read-write + + + DZPQ + Disable Zero-Quanta Pause + When this bit is set, it disables the automatic generation of the Zero-Quanta Pause frames on the de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i/mti_flowctrl_i). When this bit is reset, normal operation with automatic Zero-Quanta Pause frame generation is enabled. + 7 + 1 + read-write + + + PLT + Pause Low Threshold + This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause frame. The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = 100H (256 slot-times), and PLT = 01, then a second Pause frame is automatically transmitted if the mti_flowctrl_i signal is asserted at 228 (256 – 28) slot times after the first Pause frame is transmitted. The following list provides the threshold values for different values: +- 00: The threshold is Pause time minus 4 slot times (PT – 4 slot times). +- 01: The threshold is Pause time minus 28 slot times (PT – 28 slot times). +- 10: The threshold is Pause time minus 144 slot times (PT – 144 slot times). +- 11: The threshold is Pause time minus 256 slot times (PT – 256 slot times). The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the GMII or MII interface. + 4 + 2 + read-write + + + UP + Unicast Pause Frame Detect A pause frame is processed when it has the unique multicast address specified in the IEEE Std 802.3. When this bit is set, the MAC can also detect Pause frames with unicast address of the station. This unicast address should be as specified in the MAC Address0 High Register and MAC Address0 Low Register. When this bit is reset, the MAC only detects Pause frames with unique multicast address. + 3 + 1 + read-write + + + RFE + Receive Flow Control Enable + When this bit is set, the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause) time. When this bit is reset, the decode function of the Pause frame is disabled. + 2 + 1 + read-write + + + TFE + Transmit Flow Control Enable +In the full-duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC does not transmit any Pause frames. In the half-duplex mode, when this bit is set, the MAC enables the backpressure operation. When this bit is reset, the backpressure feature is disabled. + 1 + 1 + read-write + + + FCB_BPA + Flow Control Busy or Backpressure Activate + This bit initiates a Pause frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set. In the full-duplex mode, this bit should be read as 1'b0 before writing to the Flow Control register. To initiate a Pause frame, the Application must set this bit to 1'b1. During a transfer of the Control Frame, this bit continues to be set to signify that a frame transmission is in progress. After the completion of Pause frame transmission, the MAC resets this bit to 1'b0. The Flow Control register should not be written to until this bit is cleared. In the half-duplex mode, when this bit is set (and TFE is set), then backpressure is asserted by the MAC. During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. This control register bit is logically ORed with the mti_flowctrl_i input signal for the backpressure function. When the MAC is configured for the full-duplex mode, the BPA is automatically disabled. + 0 + 1 + read-write + + + + + VLAN_TAG + VLAN Tag Register + 0x1c + 32 + 0x00000000 + 0x000FFFFF + + + VTHM + VLAN Tag Hash Table Match Enable + When set, the most significant four bits of the VLAN tag’s CRC are used to index the content of Register 354 (VLAN Hash Table Register). A value of 1 in the VLAN Hash Table register, corresponding to the index, indicates that the frame matched the VLAN hash table. When Bit 16 (ETV) is set, the CRC of the 12-bit VLAN Identifier (VID) is used for comparison whereas when ETV is reset, the CRC of the 16-bit VLAN tag is used for comparison. When reset, the VLAN Hash Match operation is not performed. + 19 + 1 + read-write + + + ESVL + Enable S-VLAN + When this bit is set, the MAC transmitter and receiver also consider the S-VLAN (Type = 0x88A8) frames as valid VLAN tagged frames. + 18 + 1 + read-write + + + VTIM + VLAN Tag Inverse Match Enable +When set, this bit enables the VLAN Tag inverse matching. The frames that do not have matching VLAN Tag are marked as matched. When reset, this bit enables the VLAN Tag perfect matching. The frames with matched VLAN Tag are marked as matched. + 17 + 1 + read-write + + + ETV + Enable 12-Bit VLAN Tag Comparison + When this bit is set, a 12-bit VLAN identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag. Bits [11:0] of VLAN tag are compared with the corresponding field in the received VLAN-tagged frame. Similarly, when enabled, only 12 bits of the VLAN tag in the received frame are used for hash-based VLAN filtering. When this bit is reset, all 16 bits of the 15th and 16th bytes of the received VLAN frame are used for comparison and VLAN hash filtering. + 16 + 1 + read-write + + + VL + VLAN Tag Identifier for Receive Frames + This field contains the 802.1Q VLAN tag to identify the VLAN frames and is compared to the 15th and 16th bytes of the frames being received for VLAN frames. The following list describes the bits of this field: - Bits [15:13]: User Priority - Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) - Bits[11:0]: VLAN tag’s VLAN Identifier (VID) field When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison. If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and 16th bytes for VLAN tag comparison, and declares all frames with a Type field value of 0x8100 or 0x88a8 as VLAN frames. + 0 + 16 + read-write + + + + + RWKFRMFILT + Remote Wake-Up Frame Filter Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + WKUPFRMFILT + This is the address through which the application writes or reads the remote wake-up frame filter registers (wkupfmfilter_reg). The wkupfmfilter_reg register is a pointer to eight wkupfmfilter_reg registers. The wkupfmfilter_reg register is loaded by sequentially loading the eight register values. Eight sequential writes to this address (0x0028) write all wkupfmfilter_reg registers. Similarly, eight sequential reads from this address (0x0028) read all wkupfmfilter_reg registers + 0 + 32 + read-write + + + + + PMT_CSR + PMT Control and Status Register + 0x2c + 32 + 0x00000000 + 0x9F000267 + + + RWKFILTRST + Remote Wake-Up Frame Filter Register Pointer Reset +When this bit is set, it resets the remote wake-up frame filter register pointer to 3’b000. It is automatically cleared after 1 clock cycle. + 31 + 1 + read-write + + + RWKPTR + Remote Wake-up FIFO Pointer +This field gives the current value (0 to 31) of the Remote Wake-up Frame filter register pointer. When the value of this pointer is equal to 7, 15, 23 or 31, the contents of the Remote Wake-up Frame Filter Register are transferred to the clk_rx_i domain when a write occurs to that register. The maximum value of the pointer is 7, 15, 23 and 31 respectively depending on the number of Remote Wakeup Filters selected during configuration. + 24 + 5 + read-write + + + GLBLUCAST + Global Unicast +When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a remote wake-up frame. + 9 + 1 + read-write + + + RWKPRCVD + Remote Wake-Up Frame Received +When set, this bit indicates the power management event is generated because of the reception of a remote wake-up frame. This bit is cleared by a Read into this register. + 6 + 1 + read-write + + + MGKPRCVD + Magic Packet Received +When set, this bit indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared by a Read into this register. + 5 + 1 + read-write + + + RWKPKTEN + Remote Wake-Up Frame Enable +When set, enables generation of a power management event because of remote wake-up frame reception. + 2 + 1 + read-write + + + MGKPKTEN + Magic Packet Enable +When set, enables generation of a power management event because of magic packet reception. + 1 + 1 + read-write + + + PWRDWN + Power Down +When set, the MAC receiver drops all received frames until it receives the expected magic packet or remote wake-up frame. This bit is then self-cleared and the power-down mode is disabled. The Software can also clear this bit before the expected magic packet or remote wake-up frame is received. The frames, received by the MAC after this bit is cleared, are forwarded to the application. This bit must only be set when the Magic Packet Enable, Global Unicast, or Remote Wake-Up Frame Enable bit is set high. Note: You can gate-off the CSR clock during the power-down mode. However, when the CSR clock is gated-off, you cannot perform any read or write operations on this register. Therefore, the Software cannot clear this bit. + 0 + 1 + read-write + + + + + LPI_CSR + LPI Control and Status Register + 0x30 + 32 + 0x00000000 + 0x000F030F + + + LPITXA + LPI TX Automate +This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the transmit side. This bit is not functional in the GMAC-CORE configuration in which the Tx clock gating is done during the LPI mode. If the LPITXA and LPIEN bits are set to 1, the MAC enters the LPI mode only after all outstanding frames (in the core) and pending frames (in the application interface) have been transmitted. The MAC comes out of the LPI mode when the application sends any frame for transmission or the application issues a TX FIFO Flush command. In addition, the MAC automatically clears the LPIEN bit when it exits the LPI state. If TX FIFO Flush is set in Bit 20 of Register 6 (Operation Mode Register), when the MAC is in the LPI mode, the MAC exits the LPI mode. When this bit is 0, the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode. + 19 + 1 + read-write + + + PLSEN + PHY Link Status Enable +This bit enables the link status received on the RGMII, SGMII, or SMII receive paths to be used for activating the LPI LS TIMER. When set, the MAC uses the link-status bits of Register 54 (SGMII/RGMII/SMII Control and Status Register) and Bit 17 (PLS) for the LPI LS Timer trigger. When cleared, the MAC ignores the link-status bits of Register 54 and takes only the PLS bit. This bit is RO and reserved if you have not selected the RGMII, SGMII, or SMII PHY interface. + 18 + 1 + read-write + + + PLS + PHY Link Status +This bit indicates the link status of the PHY. The MAC Transmitter asserts the LPI pattern only when the link status is up (okay) at least for the time indicated by the LPI LS TIMER. When set, the link is considered to be okay (up) and when reset, the link is considered to be down. + 17 + 1 + read-write + + + LPIEN + LPI Enable +When set, this bit instructs the MAC Transmitter to enter the LPI state. When reset, this bit instructs the MAC to exit the LPI state and resume normal transmission. This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission. + 16 + 1 + read-write + + + RLPIST + Receive LPI State +When set, this bit indicates that the MAC is receiving the LPI pattern on the GMII or MII interface. + 9 + 1 + read-write + + + TLPIST + Transmit LPI State +When set, this bit indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface. + 8 + 1 + read-write + + + RLPIEX + Receive LPI Exit +When set, this bit indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the normal reception. This bit is cleared by a read into this register. Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. + 3 + 1 + read-write + + + RLPIEN + Receive LPI Entry +When set, this bit indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register. Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. + 2 + 1 + read-write + + + TLPIEX + Transmit LPI Exit +When set, this bit indicates that the MAC transmitter has exited the LPI state after the user has cleared the LPIEN bit and the LPI TW Timer has expired. This bit is cleared by a read into this register. + 1 + 1 + read-write + + + TLPIEN + Transmit LPI Entry + When set, this bit indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register. + 0 + 1 + read-write + + + + + LPI_TCR + LPI Timers Control Register + 0x34 + 32 + 0x00000000 + 0x03FFFFFF + + + LST + LPI LS TIMER +This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count. The default value of the LPI LS Timer is 1000 (1 sec) as defined in the IEEE standard. + 16 + 10 + read-write + + + TWT + LPI TW TIMER +This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission. The TLPIEX status bit is set after the expiry of this timer. + 0 + 16 + read-write + + + + + INTR_STATUS + Interrupt Status Register + 0x38 + 32 + 0x00000000 + 0x00000EFF + + + GPIIS + GPI Interrupt Status +When the GPIO feature is enabled, this bit is set when any active event (LL or LH) occurs on the GPIS field (Bits [3:0]) of Register 56 (General Purpose IO Register) and the corresponding GPIE bit is enabled. This bit is cleared on reading lane 0 (GPIS) of Register 56 (General Purpose IO Register). When the GPIO feature is not enabled, this bit is reserved. + 11 + 1 + read-only + + + LPIIS + LPI Interrupt Status +When the Energy Efficient Ethernet feature is enabled, this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. This bit is cleared on reading Bit 0 of Register 12 (LPI Control and Status Register). In all other modes, this bit is reserved. + 10 + 1 + read-only + + + TSIS + Timestamp Interrupt Status +When the Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true: - The system time value equals or exceeds the value specified in the Target Time High and Low registers. - There is an overflow in the seconds register. - The Auxiliary snapshot trigger is asserted. This bit is cleared on reading Bit 0 of Register 458 (Timestamp Status Register). + 9 + 1 + read-only + + + MMCRXIPIS + MMC Receive Checksum Offload Interrupt Status +This bit is set high when an interrupt is generated in the MMC Receive Checksum Offload Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. + 7 + 1 + read-only + + + MMCTXIS + MMC Transmit Interrupt Status +This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. + 6 + 1 + read-only + + + MMCRXIS + MMC Receive Interrupt Status +This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. + 5 + 1 + read-only + + + MMCIS + MMC Interrupt Status +This bit is set high when any of the Bits [7:5] is set high and cleared only when all of these bits are low. + 4 + 1 + read-only + + + PMTIS + PMT Interrupt Status +This bit is set when a magic packet or remote wake-up frame is received in the power-down mode (see Bits 5 and 6 in the PMT Control and Status Register). This bit is cleared when both Bits[6:5] are cleared because of a read operation to the PMT Control and Status register. + 3 + 1 + read-only + + + PCSANCIS + PCS Auto-Negotiation Complete +This bit is set when the Auto-negotiation is completed in the TBI, RTBI, or SGMII PHY interface (Bit 5 in Register 49 (AN Status Register)). This bit is cleared when you perform a read operation to the AN Status register. + 2 + 1 + read-only + + + PCSLCHGIS + PCS Link Status Changed +This bit is set because of any change in Link Status in the TBI, RTBI, or SGMII PHY interface (Bit 2 in Register 49 (AN Status Register)). This bit is cleared when you perform a read operation on the AN Status register. + 1 + 1 + read-only + + + RGSMIIIS + RGMII or SMII Interrupt Status +This bit is set because of any change in value of the Link Status of RGMII or SMII interface (Bit 3 in Register 54 (SGMII/RGMII/SMII Control and Status Register)). This bit is cleared when you perform a read operation on the SGMII/RGMII/SMII Control and Status Register. + 0 + 1 + read-only + + + + + INTR_MASK + Interrupt Mask Register + 0x3c + 32 + 0x00000000 + 0x0000060F + + + LPIIM + LPI Interrupt Mask +When set, this bit disables the assertion of the interrupt signal because of the setting of the LPI Interrupt Status bit in Register 14 (Interrupt Status Register). + 10 + 1 + read-write + + + TSIM + Timestamp Interrupt Mask + When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Register 14 (Interrupt Status Register). + 9 + 1 + read-write + + + PMTIM + PMT Interrupt Mask + When set, this bit disables the assertion of the interrupt signal because of the setting of PMT Interrupt Status bit in Register 14 (Interrupt Status Register). + 3 + 1 + read-write + + + PCSANCIM + PCS AN Completion Interrupt Mask +When set, this bit disables the assertion of the interrupt signal because of the setting of PCS Auto-negotiation complete bit in Register 14 (Interrupt Status Register). + 2 + 1 + read-write + + + PCSLCHGIM + PCS Link Status Interrupt Mask +When set, this bit disables the assertion of the interrupt signal because of the setting of the PCS Link-status changed bit in Register 14 (Interrupt Status Register). + 1 + 1 + read-write + + + RGSMIIIM + RGMII or SMII Interrupt Mask +When set, this bit disables the assertion of the interrupt signal because of the setting of the RGMII or SMII Interrupt Status bit in Register 14 (Interrupt Status Register). + 0 + 1 + read-write + + + + + MAC_ADDR_0_HIGH + MAC Address 0 High Register + 0x40 + 32 + 0x00000000 + 0x8000FFFF + + + AE + Address Enable + This bit is RO. The bit value is fixed at 1. + 31 + 1 + read-only + + + ADDRHI + MAC Address0 [47:32] + This field contains the upper 16 bits (47:32) of the first 6-byte MAC address. The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. + 0 + 16 + read-write + + + + + MAC_ADDR_0_LOW + MAC Address 0 Low Register + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDRLO + MAC Address0 [31:0] + This field contains the lower 32 bits of the first 6-byte MAC address. This is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. + 0 + 32 + read-write + + + + + 4 + 0x8 + 1,2,3,4 + MAC_ADDR[%s] + no description available + 0x48 + + HIGH + MAC Address High Register + 0x0 + 32 + 0x00000000 + 0xFF00FFFF + + + AE + Address Enable +When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. + 31 + 1 + read-write + + + SA + Source Address +When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received frame. + 30 + 1 + read-write + + + MBC + Mask Byte Control +These bits are mask control bits for comparison of each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows: - Bit 29: Register 18[15:8] - Bit 28: Register 18[7:0] - Bit 27: Register 19[31:24] - ... - Bit 24: Register 19[7:0] You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. + 24 + 6 + read-write + + + ADDRHI + MAC Address1 [47:32] +This field contains the upper 16 bits (47:32) of the second 6-byte MAC address. + 0 + 16 + read-write + + + + + LOW + MAC Address Low Register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDRLO + MAC Address1 [31:0] +This field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process. + 0 + 32 + read-write + + + + + + XMII_CSR + SGMII/RGMII/SMII Control and Status Register + 0xd8 + 32 + 0x00000000 + 0x0000003F + + + FALSCARDET + False Carrier Detected + This bit indicates whether the SMII PHY detected false carrier (1'b1). This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. + 5 + 1 + read-write + + + JABTO + Jabber Timeout + This bit indicates whether there is jabber timeout error (1'b1) in the received frame. This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. + 4 + 1 + read-write + + + LNKSTS + Link Status + This bit indicates whether the link between the local PHY and the remote PHY is up or down. It gives the status of the link between the SGMII of MAC and the SGMII of the local PHY. The status bits are received from the local PHY during ANEG betweent he MAC and PHY on the SGMII link. + 3 + 1 + read-write + + + LNKSPEED + Link Speed + This bit indicates the current speed of the link: +- 00: 2.5 MHz +- 01: 25 MHz +- 10: 125 MHz Bit 2 is reserved when the MAC is configured for the SMII PHY interface. + 1 + 2 + read-write + + + LNKMOD + Link Mode + This bit indicates the current mode of operation of the link: +- 1’b0: Half-duplex mode +- 1’b1: Full-duplex mode + 0 + 1 + read-write + + + + + WDOG_WTO + Watchdog Timeout Register + 0xdc + 32 + 0x00000000 + 0x00013FFF + + + PWE + Programmable Watchdog Enable + When this bit is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, the WTO field (Bits[13:0]) is used as watchdog timeout for a received frame. When this bit is cleared, the watchdog timeout for a received frame is controlled by the setting of Bit 23 (WD) and Bit 20 (JE) in Register 0 (MAC Configuration Register). + 16 + 1 + read-write + + + WTO + Watchdog Timeout +When Bit 16 (PWE) is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, this field is used as watchdog timeout for a received frame. If the length of a received frame exceeds the value of this field, such frame is terminated and declared as an error frame. Note: When Bit 16 (PWE) is set, the value in this field should be more than 1,522 (0x05F2). Otherwise, the IEEE Std 802.3-specified valid tagged frames are declared as error frames and are dropped. + 0 + 14 + read-write + + + + + mmc_cntrl + MMC Control establishes the operating mode of MMC. + 0x100 + 32 + 0x00000000 + 0x0000013F + + + UCDBC + Update MMC Counters for Dropped Broadcast Frames +When set, the MAC updates all related MMC Counters for Broadcast frames that are dropped because of the setting of Bit 5 (DBF) of Register 1 (MAC Frame Filter). When reset, the MMC Counters are not updated for dropped Broadcast frames. + 8 + 1 + read-write + + + CNTPRSTLVL + Full-Half Preset +When this bit is low and Bit 4 is set, all MMC counters get preset to almost-half value. All octet counters get preset to 0x7FFF_F800 (half +- 2KBytes) and all frame-counters gets preset to 0x7FFF_FFF0 (half +- 16). When this bit is high and Bit 4 is set, all MMC counters get preset to almost-full value. All octet counters get preset to 0xFFFF_F800 (full +- 2KBytes) and all frame-counters gets preset to 0xFFFF_FFF0 (full +- 16). For 16-bit counters, the almost-half preset values are 0x7800 and 0x7FF0 for the respective octet and frame counters. Similarly, the almost-full preset values for the 16-bit counters are 0xF800 and 0xFFF0. + 5 + 1 + read-write + + + CNTPRST + Counters Preset +When this bit is set, all counters are initialized or preset to almost full or almost half according to Bit 5. This bit is cleared automatically after 1 clock cycle. This bit, along with Bit 5, is useful for debugging and testing the assertion of interrupts because of MMC counter becoming half-full or full. + 4 + 1 + read-write + + + CNTFREEZ + MMC Counter Freeze +When this bit is set, it freezes all MMC counters to their current value. Until this bit is reset to 0, no MMC counter is updated because of any transmitted or received frame. If any MMC counter is read with the Reset on Read bit set, then that counter is also cleared in this mode. + 3 + 1 + read-write + + + RSTONRD + Reset on Read +When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset). The counters are cleared when the least significant byte lane (Bits[7:0]) is read. + 2 + 1 + read-write + + + CNTSTOPRO + Counter Stop Rollover +When this bit is set, the counter does not roll over to zero after reaching the maximum value. + 1 + 1 + read-write + + + CNTRST + Counters Reset +When this bit is set, all counters are reset. This bit is cleared automatically after 1 clock cycle + 0 + 1 + read-write + + + + + mmc_intr_rx + MMC Receive Interrupt maintains the interrupt generated from all +of the receive statistic counters. + 0x104 + 32 + 0x00000000 + 0x03FFFFFF + + + RXCTRLFIS + MMC Receive Control Frame Counter Interrupt Status +This bit is set when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. + 25 + 1 + read-write + + + RXRCVERRFIS + MMC Receive Error Frame Counter Interrupt Status +This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value. + 24 + 1 + read-write + + + RXWDOGFIS + MMC Receive Watchdog Error Frame Counter Interrupt Status +This bit is set when the rxwatchdog error counter reaches half of the maximum value or the maximum value. + 23 + 1 + read-write + + + RXVLANGBFIS + MMC Receive VLAN Good Bad Frame Counter Interrupt Status +This bit is set when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. + 22 + 1 + read-write + + + RXFOVFIS + MMC Receive FIFO Overflow Frame Counter Interrupt Status +This bit is set when the rxfifooverflow counter reaches half of the maximum value or the maximum value. + 21 + 1 + read-write + + + RXPAUSFIS + MMC Receive Pause Frame Counter Interrupt Status +This bit is set when the rxpauseframes counter reaches half of the maximum value or the maximum value. + 20 + 1 + read-write + + + RXORANGEFIS + MMC Receive Out Of Range Error Frame Counter Interrupt Status. +This bit is set when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. + 19 + 1 + read-write + + + RXLENERFIS + MMC Receive Length Error Frame Counter Interrupt Status +This bit is set when the rxlengtherror counter reaches half of the maximum value or the maximum value. + 18 + 1 + read-write + + + RXUCGFIS + MMC Receive Unicast Good Frame Counter Interrupt Status +This bit is set when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. + 17 + 1 + read-write + + + RX1024TMAXOCTGBFIS + MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status. +This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. + 16 + 1 + read-write + + + RX512T1023OCTGBFIS + MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. + 15 + 1 + read-write + + + RX256T511OCTGBFIS + MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. + 14 + 1 + read-write + + + RX128T255OCTGBFIS + MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. + 13 + 1 + read-write + + + RX65T127OCTGBFIS + MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. + 12 + 1 + read-write + + + RX64OCTGBFIS + MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value. + 11 + 1 + read-write + + + RXOSIZEGFIS + MMC Receive Oversize Good Frame Counter Interrupt Status +This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value. + 10 + 1 + read-write + + + RXUSIZEGFIS + MMC Receive Undersize Good Frame Counter Interrupt Status +This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value. + 9 + 1 + read-write + + + RXJABERFIS + MMC Receive Jabber Error Frame Counter Interrupt Status +This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value. + 8 + 1 + read-write + + + RXRUNTFIS + MMC Receive Runt Frame Counter Interrupt Status +This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value. + 7 + 1 + read-write + + + RXALGNERFIS + MMC Receive Alignment Error Frame Counter Interrupt Status +This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value. + 6 + 1 + read-write + + + RXCRCERFIS + MMC Receive CRC Error Frame Counter Interrupt Status +This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value. + 5 + 1 + read-write + + + RXMCGFIS + MMC Receive Multicast Good Frame Counter Interrupt Status +This bit is set when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. + 4 + 1 + read-write + + + RXBCGFIS + MMC Receive Broadcast Good Frame Counter Interrupt Status +This bit is set when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. + 3 + 1 + read-write + + + RXGOCTIS + MMC Receive Good Octet Counter Interrupt Status +This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. + 2 + 1 + read-write + + + RXGBOCTIS + MMC Receive Good Bad Octet Counter Interrupt Status +This bit is set when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. + 1 + 1 + read-write + + + RXGBFRMIS + MMC Receive Good Bad Frame Counter Interrupt Status +This bit is set when the rxframecount_gb counter reaches half of the maximum value or the maximum value. + 0 + 1 + read-write + + + + + mmc_intr_tx + MMC Transmit Interrupt maintains the interrupt generated from all +of the transmit statistic counters + 0x108 + 32 + 0x00000000 + 0x03FFFFFF + + + TXOSIZEGFIS + MMC Transmit Oversize Good Frame Counter Interrupt Status +This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value. + 25 + 1 + read-write + + + TXVLANGFIS + MMC Transmit VLAN Good Frame Counter Interrupt Status +This bit is set when the txvlanframes_g counter reaches half of the maximum value or the maximum value. + 24 + 1 + read-write + + + TXPAUSFIS + MMC Transmit Pause Frame Counter Interrupt Status +This bit is set when the txpauseframeserror counter reaches half of the maximum value or the maximum value. + 23 + 1 + read-write + + + TXEXDEFFIS + MMC Transmit Excessive Deferral Frame Counter Interrupt Status +This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value. + 22 + 1 + read-write + + + TXGFRMIS + MMC Transmit Good Frame Counter Interrupt Status +This bit is set when the txframecount_g counter reaches half of the maximum value or the maximum value. + 21 + 1 + read-write + + + TXGOCTIS + MMC Transmit Good Octet Counter Interrupt Status +This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value. + 20 + 1 + read-write + + + TXCARERFIS + MMC Transmit Carrier Error Frame Counter Interrupt Status +This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value. + 19 + 1 + read-write + + + TXEXCOLFIS + MMC Transmit Excessive Collision Frame Counter Interrupt Status +This bit is set when the txexesscol counter reaches half of the maximum value or the maximum value. + 18 + 1 + read-write + + + TXLATCOLFIS + MMC Transmit Late Collision Frame Counter Interrupt Status +This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value. + 17 + 1 + read-write + + + TXDEFFIS + MMC Transmit Deferred Frame Counter Interrupt Status +This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value. + 16 + 1 + read-write + + + TXMCOLGFIS + MMC Transmit Multiple Collision Good Frame Counter Interrupt Status +This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value. + 15 + 1 + read-write + + + TXSCOLGFIS + MMC Transmit Single Collision Good Frame Counter Interrupt Status +This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value. + 14 + 1 + read-write + + + TXUFLOWERFIS + MMC Transmit Underflow Error Frame Counter Interrupt Status +This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value. + 13 + 1 + read-write + + + TXBCGBFIS + MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status +This bit is set when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. + 12 + 1 + read-write + + + TXMCGBFIS + MMC Transmit Multicast Good Bad Frame Counter Interrupt Status +The bit is set when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. + 11 + 1 + read-write + + + TXUCGBFIS + MMC Transmit Unicast Good Bad Frame Counter Interrupt Status +This bit is set when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. + 10 + 1 + read-write + + + TX1024TMAXOCTGBFIS + MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status +This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. + 9 + 1 + read-write + + + TX512T1023OCTGBFIS + MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. + 8 + 1 + read-write + + + TX256T511OCTGBFIS + MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. + 7 + 1 + read-write + + + TX128T255OCTGBFIS + MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. + 6 + 1 + read-write + + + TX65T127OCTGBFIS + MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the tx65to127octets_gb counter reaches half the maximum value, and also when it reaches the maximum value. + 5 + 1 + read-write + + + TX64OCTGBFIS + MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value. + 4 + 1 + read-write + + + TXMCGFIS + MMC Transmit Multicast Good Frame Counter Interrupt Status +This bit is set when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. + 3 + 1 + read-write + + + TXBCGFIS + MMC Transmit Broadcast Good Frame Counter Interrupt Status +This bit is set when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. + 2 + 1 + read-write + + + TXGBFRMIS + MMC Transmit Good Bad Frame Counter Interrupt Status +This bit is set when the txframecount_gb counter reaches half of the maximum value or the maximum value. + 1 + 1 + read-write + + + TXGBOCTIS + MMC Transmit Good Bad Octet Counter Interrupt Status +This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. + 0 + 1 + read-write + + + + + mmc_intr_mask_rx + MMC Receive Interrupt mask maintains the mask for the interrupt +generated from all of the receive statistic counters + 0x10c + 32 + 0x00000000 + 0x03FFFFFE + + + RXCTRLFIM + MMC Receive Control Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. + 25 + 1 + read-write + + + RXRCVERRFIM + MMC Receive Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value. + 24 + 1 + read-write + + + RXWDOGFIM + MMC Receive Watchdog Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value. + 23 + 1 + read-write + + + RXVLANGBFIM + MMC Receive VLAN Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. + 22 + 1 + read-write + + + RXFOVFIM + MMC Receive FIFO Overflow Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value. + 21 + 1 + read-write + + + RXPAUSFIM + MMC Receive Pause Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxpauseframes counter reaches half of the maximum value or the maximum value. + 20 + 1 + read-write + + + RXORANGEFIM + MMC Receive Out Of Range Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. + 19 + 1 + read-write + + + RXLENERFIM + MMC Receive Length Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value. + 18 + 1 + read-write + + + RXUCGFIM + MMC Receive Unicast Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. + 17 + 1 + read-write + + + RX1024TMAXOCTGBFIM + MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask. +Setting this bit masks the interrupt when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. + 16 + 1 + read-write + + + RX512T1023OCTGBFIM + MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. + 15 + 1 + read-write + + + RX256T511OCTGBFIM + MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. + 14 + 1 + read-write + + + RX128T255OCTGBFIM + MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. + 13 + 1 + read-write + + + RX65T127OCTGBFIM + MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. + 12 + 1 + read-write + + + RX64OCTGBFIM + MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value. + 11 + 1 + read-write + + + RXOSIZEGFIM + MMC Receive Oversize Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value. + 10 + 1 + read-write + + + RXUSIZEGFIM + MMC Receive Undersize Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value. + 9 + 1 + read-write + + + RXJABERFIM + MMC Receive Jabber Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value. + 8 + 1 + read-write + + + RXRUNTFIM + MMC Receive Runt Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value. + 7 + 1 + read-write + + + RXALGNERFIM + MMC Receive Alignment Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value. + 6 + 1 + read-write + + + RXCRCERFIM + MMC Receive CRC Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value. + 5 + 1 + read-write + + + RXMCGFIM + MMC Receive Multicast Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. + 4 + 1 + read-write + + + RXBCGFIM + MMC Receive Broadcast Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. + 3 + 1 + read-write + + + RXGOCTIM + MMC Receive Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. + 2 + 1 + read-write + + + RXGBOCTIM + MMC Receive Good Bad Octet Counter Interrupt Mask. +Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. + 1 + 1 + read-write + + + + + mmc_intr_mask_tx + MMC Transmit Interrupt Mask + 0x110 + 32 + 0x00000000 + 0x03FFFFFF + + + TXOSIZEGFIM + MMC Transmit Oversize Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value. + 25 + 1 + read-write + + + TXVLANGFIM + MMC Transmit VLAN Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txvlanframes_g counter reaches half of the maximum value or the maximum value. + 24 + 1 + read-write + + + TXPAUSFIM + MMC Transmit Pause Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txpauseframes counter reaches half of the maximum value or the maximum value. + 23 + 1 + read-write + + + TXEXDEFFIM + MMC Transmit Excessive Deferral Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value. + 22 + 1 + read-write + + + TXGFRMIM + MMC Transmit Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txframecount_g counter reaches half of the maximum value or the maximum value. + 21 + 1 + read-write + + + TXGOCTIM + MMC Transmit Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value. + 20 + 1 + read-write + + + TXCARERFIM + MMC Transmit Carrier Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value. + 19 + 1 + read-write + + + TXEXCOLFIM + MMC Transmit Excessive Collision Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value. + 18 + 1 + read-write + + + TXLATCOLFIM + MMC Transmit Late Collision Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value. + 17 + 1 + read-write + + + TXDEFFIM + MMC Transmit Deferred Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value. + 16 + 1 + read-write + + + TXMCOLGFIM + MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value. + 15 + 1 + read-write + + + TXSCOLGFIM + MMC Transmit Single Collision Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value. + 14 + 1 + read-write + + + TXUFLOWERFIM + MMC Transmit Underflow Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value. + 13 + 1 + read-write + + + TXBCGBFIM + MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. + 12 + 1 + read-write + + + TXMCGBFIM + MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. + 11 + 1 + read-write + + + TXUCGBFIM + MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. + 10 + 1 + read-write + + + TX1024TMAXOCTGBFIM + MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. + 9 + 1 + read-write + + + TX512T1023OCTGBFIM + MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. + 8 + 1 + read-write + + + TX256T511OCTGBFIM + MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. + 7 + 1 + read-write + + + TX128T255OCTGBFIM + MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. + 6 + 1 + read-write + + + TX65T127OCTGBFIM + MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value. + 5 + 1 + read-write + + + TX64OCTGBFIM + MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value. + 4 + 1 + read-write + + + TXMCGFIM + MMC Transmit Multicast Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. + 3 + 1 + read-write + + + TXBCGFIM + MMC Transmit Broadcast Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. + 2 + 1 + read-write + + + TXGBFRMIM + MMC Transmit Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txframecount_gb counter reaches half of the maximum value or the maximum value. + 1 + 1 + read-write + + + TXGBOCTIM + MMC Transmit Good Bad Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. + 0 + 1 + read-write + + + + + txoctetcount_gb + Number of bytes transmitted, exclusive of preamble and retried +bytes, in good and bad frames. + 0x114 + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes transmitted, exclusive of preamble and retried bytes, in good and bad frames. + 0 + 32 + read-write + + + + + txframecount_gb + Number of good and bad frames transmitted, exclusive of retried +frames. + 0x118 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted, exclusive of retried frames. + 0 + 32 + read-write + + + + + txbroadcastframes_g + Number of good broadcast frames transmitted + 0x11c + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good broadcast frames transmitted. + 0 + 32 + read-write + + + + + txmlticastframes_g + Number of good multicast frames transmitted + 0x120 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good multicast frames transmitted. + 0 + 32 + read-write + + + + + tx64octets_gb + Number of good and bad frames transmitted with length 64 bytes, +exclusive of preamble and retried frames. + 0x124 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted with length 64 bytes, exclusive of preamble and retried frames. + 0 + 32 + read-write + + + + + tx65to127octets_gb + Number of good and bad frames transmitted with length between +65 and 127 (inclusive) bytes, exclusive of preamble and retried +frames. + 0x128 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 32 + read-write + + + + + tx128to255octets_gb + Number of good and bad frames transmitted with length between +128 and 255 (inclusive) bytes, exclusive of preamble and retried +frames. + 0x12c + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted with length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 32 + read-write + + + + + tx256to511octets_gb + Number of good and bad frames transmitted with length between +256 and 511 (inclusive) bytes, exclusive of preamble and retried +frames. + 0x130 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted with length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 32 + read-write + + + + + tx512to1023octets_gb + Number of good and bad frames transmitted with length between +512 and 1,023 (inclusive) bytes, exclusive of preamble and retried +frames. + 0x134 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 32 + read-write + + + + + tx1024tomaxoctets_gb + Number of good and bad frames transmitted with length between +1,024 and maxsize (inclusive) bytes, exclusive of preamble and +retried frames. + 0x138 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 32 + read-write + + + + + rxframecount_gb + Number of good and bad frames received + 0x180 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames received. + 0 + 32 + read-write + + + + + mmc_ipc_intr_mask_rx + MMC IPC Receive Checksum Offload Interrupt Mask maintains +the mask for the interrupt generated from the receive IPC statistic +counters. + 0x200 + 32 + 0x00000000 + 0x3FFF3FFF + + + RXICMPEROIM + MMC Receive ICMP Error Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. + 29 + 1 + read-write + + + RXICMPGOIM + MMC Receive ICMP Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. + 28 + 1 + read-write + + + RXTCPEROIM + MMC Receive TCP Error Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. + 27 + 1 + read-write + + + RXTCPGOIM + MMC Receive TCP Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value. + 26 + 1 + read-write + + + RXUDPEROIM + MMC Receive UDP Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. + 25 + 1 + read-write + + + RXUDPGOIM + MMC Receive IPV6 No Payload Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. + 24 + 1 + read-write + + + RXIPV6NOPAYOIM + MMC Receive IPV6 Header Error Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. + 23 + 1 + read-write + + + RXIPV6HEROIM + MMC Receive IPV6 Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. + 22 + 1 + read-write + + + RXIPV6GOIM + MMC Receive IPV6 Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. + 21 + 1 + read-write + + + RXIPV4UDSBLOIM + MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. + 20 + 1 + read-write + + + RXIPV4FRAGOIM + MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. + 19 + 1 + read-write + + + RXIPV4NOPAYOIM + MMC Receive IPV4 No Payload Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. + 18 + 1 + read-write + + + RXIPV4HEROIM + MMC Receive IPV4 Header Error Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. + 17 + 1 + read-write + + + RXIPV4GOIM + MMC Receive IPV4 Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. + 16 + 1 + read-write + + + RXICMPERFIM + MMC Receive ICMP Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. + 13 + 1 + read-write + + + RXICMPGFIM + MMC Receive ICMP Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. + 12 + 1 + read-write + + + RXTCPERFIM + MMC Receive TCP Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. + 11 + 1 + read-write + + + RXTCPGFIM + MMC Receive TCP Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. + 10 + 1 + read-write + + + RXUDPERFIM + MMC Receive UDP Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. + 9 + 1 + read-write + + + RXUDPGFIM + MMC Receive UDP Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. + 8 + 1 + read-write + + + RXIPV6NOPAYFIM + MMC Receive IPV6 No Payload Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. + 7 + 1 + read-write + + + RXIPV6HERFIM + MMC Receive IPV6 Header Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. + 6 + 1 + read-write + + + RXIPV6GFIM + MMC Receive IPV6 Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. + 5 + 1 + read-write + + + RXIPV4UDSBLFIM + MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. + 4 + 1 + read-write + + + RXIPV4FRAGFIM + MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. + 3 + 1 + read-write + + + RXIPV4NOPAYFIM + MMC Receive IPV4 No Payload Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. + 2 + 1 + read-write + + + RXIPV4HERFIM + MMC Receive IPV4 Header Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. + 1 + 1 + read-write + + + RXIPV4GFIM + MMC Receive IPV4 Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. + 0 + 1 + read-write + + + + + mmc_ipc_intr_rx + MMC Receive Checksum Offload Interrupt maintains the interrupt +that the receive IPC statistic counters generate. See Table 4-25 +for further detail. + 0x208 + 32 + 0x00000000 + 0x3FFF3FFF + + + RXICMPEROIS + MMC Receive ICMP Error Octet Counter Interrupt Status +This bit is set when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. + 29 + 1 + read-write + + + RXICMPGOIS + MMC Receive ICMP Good Octet Counter Interrupt Status +This bit is set when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. + 28 + 1 + read-write + + + RXTCPEROIS + MMC Receive TCP Error Octet Counter Interrupt Status +This bit is set when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. + 27 + 1 + read-write + + + RXTCPGOIS + MMC Receive TCP Good Octet Counter Interrupt Status +This bit is set when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value + 26 + 1 + read-write + + + RXUDPEROIS + MMC Receive UDP Error Octet Counter Interrupt Status +This bit is set when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. + 25 + 1 + read-write + + + RXUDPGOIS + MMC Receive UDP Good Octet Counter Interrupt Status +This bit is set when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. + 24 + 1 + read-write + + + RXIPV6NOPAYOIS + MMC Receive IPV6 No Payload Octet Counter Interrupt Status +This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. + 23 + 1 + read-write + + + RXIPV6HEROIS + MMC Receive IPV6 Header Error Octet Counter Interrupt Status +This bit is set when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. + 22 + 1 + read-write + + + RXIPV6GOIS + MMC Receive IPV6 Good Octet Counter Interrupt Status +This bit is set when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. + 21 + 1 + read-write + + + RXIPV4UDSBLOIS + MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status +This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. + 20 + 1 + read-write + + + RXIPV4FRAGOIS + MMC Receive IPV4 Fragmented Octet Counter Interrupt Status +This bit is set when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. + 19 + 1 + read-write + + + RXIPV4NOPAYOIS + MMC Receive IPV4 No Payload Octet Counter Interrupt Status +This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. + 18 + 1 + read-write + + + RXIPV4HEROIS + MMC Receive IPV4 Header Error Octet Counter Interrupt Status +This bit is set when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. + 17 + 1 + read-write + + + RXIPV4GOIS + MMC Receive IPV4 Good Octet Counter Interrupt Status +This bit is set when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. + 16 + 1 + read-write + + + RXICMPERFIS + MMC Receive ICMP Error Frame Counter Interrupt Status +This bit is set when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. + 13 + 1 + read-write + + + RXICMPGFIS + MMC Receive ICMP Good Frame Counter Interrupt Status +This bit is set when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. + 12 + 1 + read-write + + + RXTCPERFIS + MMC Receive TCP Error Frame Counter Interrupt Status +This bit is set when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. + 11 + 1 + read-write + + + RXTCPGFIS + MMC Receive TCP Good Frame Counter Interrupt Status +This bit is set when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. + 10 + 1 + read-write + + + RXUDPERFIS + MMC Receive UDP Error Frame Counter Interrupt Status +This bit is set when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. + 9 + 1 + read-write + + + RXUDPGFIS + MMC Receive UDP Good Frame Counter Interrupt Status +This bit is set when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. + 8 + 1 + read-write + + + RXIPV6NOPAYFIS + MMC Receive IPV6 No Payload Frame Counter Interrupt Status +This bit is set when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. + 7 + 1 + read-write + + + RXIPV6HERFIS + MMC Receive IPV6 Header Error Frame Counter Interrupt Status +This bit is set when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. + 6 + 1 + read-write + + + RXIPV6GFIS + MMC Receive IPV6 Good Frame Counter Interrupt Status +This bit is set when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. + 5 + 1 + read-write + + + RXIPV4UDSBLFIS + MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status +This bit is set when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. + 4 + 1 + read-write + + + RXIPV4FRAGFIS + MMC Receive IPV4 Fragmented Frame Counter Interrupt Status +This bit is set when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. + 3 + 1 + read-write + + + RXIPV4NOPAYFIS + MMC Receive IPV4 No Payload Frame Counter Interrupt Status +This bit is set when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. + 2 + 1 + read-write + + + RXIPV4HERFIS + MMC Receive IPV4 Header Error Frame Counter Interrupt Status +This bit is set when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. + 1 + 1 + read-write + + + RXIPV4GFIS + MMC Receive IPV4 Good Frame Counter Interrupt Status +This bit is set when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. + 0 + 1 + read-write + + + + + rxipv4_gd_fms + Number of good IPv4 datagrams received with the TCP, UDP, or +ICMP payload + 0x210 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload + 0 + 32 + read-write + + + + + 1 + 0x20 + 0 + L3_L4_CFG[%s] + no description available + 0x400 + + L3_L4_CTRL + Layer 3 and Layer 4 Control Register + 0x0 + 32 + 0x00000000 + 0x003DFFFD + + + L4DPIM0 + Layer 4 Destination Port Inverse Match Enable + When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. + 21 + 1 + read-write + + + L4DPM0 + Layer 4 Destination Port Match Enable + When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching. + 20 + 1 + read-write + + + L4SPIM0 + Layer 4 Source Port Inverse Match Enable +When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. + 19 + 1 + read-write + + + L4SPM0 + Layer 4 Source Port Match Enable +When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. + 18 + 1 + read-write + + + L4PEN0 + Layer 4 Protocol Enable +When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. + 16 + 1 + read-write + + + L3HDBM0 + Layer 3 IP DA Higher Bits Match + IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - ... +- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - … +- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. + 11 + 5 + read-write + + + L3HSBM0 + Layer 3 IP SA Higher Bits Match + IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - ... +- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. + 6 + 5 + read-write + + + L3DAIM0 + Layer 3 IP DA Inverse Match Enable +When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. + 5 + 1 + read-write + + + L3DAM0 + Layer 3 IP DA Match Enable +When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. + 4 + 1 + read-write + + + L3SAIM0 + Layer 3 IP SA Inverse Match Enable +When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. + 3 + 1 + read-write + + + L3SAM0 + Layer 3 IP SA Match Enable +When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. + 2 + 1 + read-write + + + L3PEN0 + Layer 3 Protocol Enable + When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. + 0 + 1 + read-write + + + + + L4_Addr + Layer 4 Address Register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + L4DP0 + Layer 4 Destination Port Number Field +When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. + 16 + 16 + read-write + + + L4SP0 + Layer 4 Source Port Number Field + When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. + 0 + 16 + read-write + + + + + L3_Addr_0 + Layer 3 Address 0 Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A00 + Layer 3 Address 0 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Source Address field in the IPv4 frames. + 0 + 32 + read-write + + + + + L3_Addr_1 + Layer 3 Address 1 Register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A10 + Layer 3 Address 1 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. + 0 + 32 + read-write + + + + + L3_Addr_2 + Layer 3 Address 2 Register + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A20 + Layer 3 Address 2 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. + 0 + 32 + read-write + + + + + L3_Addr_3 + Layer 3 Address 3 Register + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A30 + Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. + 0 + 32 + read-write + + + + + + VLAN_TAG_INC_RPL + VLAN Tag Inclusion or Replacement Register + 0x584 + 32 + 0x00000000 + 0x000FFFFF + + + CSVL + C-VLAN or S-VLAN + When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted frames. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the transmitted frames. + 19 + 1 + read-write + + + VLP + VLAN Priority Control +When this bit is set, the control Bits [17:16] are used for VLAN deletion, insertion, or replacement. When this bit is reset, the mti_vlan_ctrl_i control input is used, and Bits [17:16] are ignored. + 18 + 1 + read-write + + + VLC + VLAN Tag Control in Transmit Frames +- 2’b00: No VLAN tag deletion, insertion, or replacement +- 2’b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted frames with VLAN tags. +- 2’b10: VLAN tag insertion The MAC inserts VLT in bytes 15 and 16 of the frame after inserting the Type value (0x8100/0x88a8) in bytes 13 and 14. This operation is performed on all transmitted frames, irrespective of whether they already have a VLAN tag. +- 2’b11: VLAN tag replacement The MAC replaces VLT in bytes 15 and 16 of all VLAN-type transmitted frames (Bytes 13 and 14 are 0x8100/0x88a8). Note: Changes to this field take effect only on the start of a frame. If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, that is, the current frame does not use the updated value. + 16 + 2 + read-write + + + VLT + VLAN Tag for Transmit Frames + This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. Bits[15:13] are the User Priority, Bit 12 is the CFI/DEI, and Bits[11:0] are the VLAN tag’s VID field. + 0 + 16 + read-write + + + + + VLAN_HASH + VLAN Hash Table Register + 0x588 + 32 + 0x00000000 + 0x0000FFFF + + + VLHT + VLAN Hash Table + This field contains the 16-bit VLAN Hash Table. + 0 + 16 + read-write + + + + + TS_CTRL + Timestamp Control Register + 0x700 + 32 + 0x00000000 + 0x1F07FF3F + + + ATSEN3 + Auxiliary Snapshot 3 Enable +This field controls capturing the Auxiliary Snapshot Trigger 3. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[3] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than four. + 28 + 1 + read-write + + + ATSEN2 + Auxiliary Snapshot 2 Enable +This field controls capturing the Auxiliary Snapshot Trigger 2. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[2] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than three. + 27 + 1 + read-write + + + ATSEN1 + Auxiliary Snapshot 1 Enable +This field controls capturing the Auxiliary Snapshot Trigger 1. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[1] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than two. + 26 + 1 + read-write + + + ATSEN0 + Auxiliary Snapshot 0 Enable +This field controls capturing the Auxiliary Snapshot Trigger 0. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled. When this bit is reset, the events on this input are ignored. + 25 + 1 + read-write + + + ATSFC + Auxiliary Snapshot FIFO Clear +When set, it resets the pointers of the Auxiliary Snapshot FIFO. This bit is cleared when the pointers are reset and the FIFO is empty. When this bit is high, auxiliary snapshots get stored in the FIFO. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration. + 24 + 1 + read-write + + + TSENMACADDR + Enable MAC address for PTP Frame Filtering +When set, the DA MAC address (that matches any MAC Address register) is used to filter the PTP frames when PTP is directly sent over Ethernet. + 18 + 1 + read-write + + + SNAPTYPSEL + Select PTP packets for Taking Snapshots + These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken. + 16 + 2 + read-write + + + TSMSTRENA + Enable Snapshot for Messages Relevant to Master +When set, the snapshot is taken only for the messages relevant to the master node. Otherwise, the snapshot is taken for the messages relevant to the slave node. + 15 + 1 + read-write + + + TSEVNTENA + Enable Timestamp Snapshot for Event Messages +When set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). When reset, the snapshot is taken for all messages except Announce, Management, and Signaling. + 14 + 1 + read-write + + + TSIPV4ENA + Enable Processing of PTP Frames Sent over IPv4-UDP + When set, the MAC receiver processes the PTP packets encapsulated in UDP over IPv4 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv4 packets. This bit is set by default. + 13 + 1 + read-write + + + TSIPV6ENA + Enable Processing of PTP Frames Sent over IPv6-UDP +When set, the MAC receiver processes PTP packets encapsulated in UDP over IPv6 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv6 packets. + 12 + 1 + read-write + + + TSIPENA + Enable Processing of PTP over Ethernet Frames +When set, the MAC receiver processes the PTP packets encapsulated directly in the Ethernet frames. When this bit is clear, the MAC ignores the PTP over Ethernet packets + 11 + 1 + read-write + + + TSVER2ENA + Enable PTP packet Processing for Version 2 Format +When set, the PTP packets are processed using the 1588 version 2 format. Otherwise, the PTP packets are processed using the version 1 format. + 10 + 1 + read-write + + + TSCTRLSSR + Timestamp Digital or Binary Rollover Control +When set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. When reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and the value of this bit. + 9 + 1 + read-write + + + TSENALL + Enable Timestamp for All Frames +When set, the timestamp snapshot is enabled for all frames received by the MAC. + 8 + 1 + read-write + + + TSADDREG + Addend Reg Update +When set, the content of the Timestamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. This register bit should be zero before setting it. + 5 + 1 + read-write + + + TSTRIG + Timestamp Interrupt Trigger Enable +When set, the timestamp interrupt is generated when the System Time becomes greater than the value written in the Target Time register. This bit is reset after the generation of the Timestamp Trigger Interrupt. + 4 + 1 + read-write + + + TSUPDT + Timestamp Update +When set, the system time is updated (added or subtracted) with the value specified in Register 452 (System Time – Seconds Update Register) and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. This bit is reset when the update is completed in hardware. The “Timestamp Higher Word” register (if enabled during core configuration) is not updated. + 3 + 1 + read-write + + + TSINIT + Timestamp Initialize +When set, the system time is initialized (overwritten) with the value specified in the Register 452 (System Time – Seconds Update Register) and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. This bit is reset when the initialization is complete. The “Timestamp Higher Word” register (if enabled during core configuration) can only be initialized. + 2 + 1 + read-write + + + TSCFUPDT + Timestamp Fine or Coarse Update +When set, this bit indicates that the system times update should be done using the fine update method. When reset, it indicates the system timestamp update should be done using the Coarse method. + 1 + 1 + read-write + + + TSENA + Timestamp Enable +When set, the timestamp is added for the transmit and receive frames. When disabled, timestamp is not added for the transmit and receive frames and the Timestamp Generator is also suspended. You need to initialize the Timestamp (system time) after enabling this mode. On the receive side, the MAC processes the 1588 frames only if this bit is set. + 0 + 1 + read-write + + + + + SUB_SEC_INCR + Sub-Second Increment Register + 0x704 + 32 + 0x00000000 + 0x000000FF + + + SSINC + Sub-second Increment Value +The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register. For example, when PTP clock is 50 MHz (period is 20 ns), you should program 20 (0x14) when the System Time- Nanoseconds register has an accuracy of 1 ns [Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register)]. When TSCTRLSSR is clear, the Nanoseconds register has a resolution of ~0.465ns. In this case, you should program a value of 43 (0x2B) that is derived by 20ns/0.465. + 0 + 8 + read-write + + + + + SYST_SEC + System Time - Seconds Register + 0x708 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSS + Timestamp Second + The value in this field indicates the current value in seconds of the System Time maintained by the MAC. + 0 + 32 + read-only + + + + + SYST_NSEC + System Time - Nanoseconds Register + 0x70c + 32 + 0x00000000 + 0x7FFFFFFF + + + TSSS + Timestamp Sub Seconds + The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the maximum value is 0x3B9A_C9FF, after which it rolls-over to zero. + 0 + 31 + read-only + + + + + SYST_SEC_UPD + System Time - Seconds Update Register + 0x710 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSS + Timestamp Second + The value in this field indicates the time in seconds to be initialized or added to the system time. + 0 + 32 + read-write + + + + + SYST_NSEC_UPD + System Time - Nanoseconds Update Register + 0x714 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDSUB + Add or Subtract Time + When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register. + 31 + 1 + read-write + + + TSSS + Timestamp Sub Seconds +The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF. + 0 + 31 + read-write + + + + + TS_ADDEND + Timestamp Addend Register + 0x718 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSAR + Timestamp Addend Register +This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization. + 0 + 32 + read-write + + + + + TGTTM_SEC + Target Time Seconds Register + 0x71c + 32 + 0x00000000 + 0xFFFFFFFF + + + TSTR + Target Time Seconds Register + This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [6:5] of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). + 0 + 32 + read-write + + + + + TGTTM_NSEC + Target Time Nanoseconds Register + 0x720 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRGTBUSY + Target Time Register Busy + The MAC sets this bit when the PPSCMD field (Bit [3:0]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD field to 010 or 011, instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. This bit is reserved when the Enable Flexible Pulse-Per-Second Output feature is not selected. + 31 + 1 + read-write + + + TTSLO + Target Timestamp Low Register +This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL0 field (Bits [6:5]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. + 0 + 31 + read-write + + + + + SYSTM_H_SEC + System Time - Higher Word Seconds Register + 0x724 + 32 + 0x00000000 + 0x0000FFFF + + + TSHWR + Timestamp Higher Word Register +This field contains the most significant 16-bits of the timestamp seconds value. This register is optional and can be selected using the Enable IEEE 1588 Higher Word Register option during core configuration. The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register. + 0 + 16 + read-write + + + + + TS_STATUS + Timestamp Status Register + 0x728 + 32 + 0x00000000 + 0x3F0F03FF + + + ATSNS + Number of Auxiliary Timestamp Snapshots +This field indicates the number of Snapshots available in the FIFO. A value equal to the selected depth of FIFO (4, 8, or 16) indicates that the Auxiliary Snapshot FIFO is full. These bits are cleared (to 00000) when the Auxiliary snapshot FIFO clear bit is set. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. + 25 + 5 + read-only + + + ATSSTM + Auxiliary Timestamp Snapshot Trigger Missed + This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set. This indicates that the latest snapshot is not stored in the FIFO. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. + 24 + 1 + read-only + + + ATSSTN + Auxiliary Timestamp Snapshot Trigger Identifier +These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. When more than one bit is set at the same time, it means that corresponding auxiliary triggers were sampled at the same clock. These bits are applicable only if the number of Auxiliary snapshots is more than one. One bit is assigned for each trigger as shown in the following list: - Bit 16: Auxiliary trigger 0 - Bit 17: Auxiliary trigger 1 - Bit 18: Auxiliary trigger 2 - Bit 19: Auxiliary trigger 3 The software can read this register to find the triggers that are set when the timestamp is taken. + 16 + 4 + read-only + + + TSTRGTERR3 + Timestamp Target Time Error +This bit is set when the target time, being programmed in Register 496 and Register 497, is already elapsed. This bit is cleared when read by the application. + 9 + 1 + read-only + + + TSTARGT3 + Timestamp Target Time Reached for Target Time PPS3 +When set, this bit indicates that the value of system time is greater than or equal to the value specified in Register 496 (PPS3 Target Time High Register) and Register 497 (PPS3 Target Time Low Register). + 8 + 1 + read-only + + + TSTRGTERR2 + No description available + 7 + 1 + read-only + + + TSTARGT2 + No description available + 6 + 1 + read-only + + + TSTRGTERR1 + No description available + 5 + 1 + read-only + + + TSTARGT1 + No description available + 4 + 1 + read-only + + + TSTRGTERR + No description available + 3 + 1 + read-only + + + AUXTSTRIG + No description available + 2 + 1 + read-only + + + TSTARGT + No description available + 1 + 1 + read-only + + + TSSOVF + No description available + 0 + 1 + read-only + + + + + PPS_CTRL + PPS Control Register + 0x72c + 32 + 0x00000000 + 0x6767777F + + + TRGTMODSEL3 + Target Time Register Mode for PPS3 Output +This field indicates the Target Time registers (register 496 and 497) mode for PPS3 output signal. This field is similar to the TRGTMODSEL0 field. + 29 + 2 + read-write + + + PPSCMD3 + Flexible PPS3 Output Control +This field controls the flexible PPS3 output (ptp_pps_o[3]) signal. This field is similar to PPSCMD0[2:0] in functionality. + 24 + 3 + read-write + + + TRGTMODSEL2 + Target Time Register Mode for PPS2 Output +This field indicates the Target Time registers (register 488 and 489) mode for PPS2 output signal. This field is similar to the TRGTMODSEL0 field. + 21 + 2 + read-write + + + PPSCMD2 + Flexible PPS2 Output Control +This field controls the flexible PPS2 output (ptp_pps_o[2]) signal. This field is similar to PPSCMD0[2:0] in functionality. + 16 + 3 + read-write + + + TRGTMODSEL1 + Target Time Register Mode for PPS1 Output +This field indicates the Target Time registers (register 480 and 481) mode for PPS1 output signal. This field is similar to the TRGTMODSEL0 field. + 13 + 2 + read-write + + + PPSEN1 + Flexible PPS1 Output Mode Enable +When set high, Bits[10:8] function as PPSCMD. + 12 + 1 + read-write + + + PPSCMD1 + Flexible PPS1 Output Control +This field controls the flexible PPS1 output (ptp_pps_o[1]) signal. This field is similar to PPSCMD0[2:0] in functionality. + 8 + 3 + read-write + + + TRGTMODSEL0 + Target Time Register Mode for PPS0 Output + This field indicates the Target Time registers (register 455 and 456) mode for PPS0 output signal: +- 00: Indicates that the Target Time registers are programmed only for generating the interrupt event. +- 01: Reserved +- 10: Indicates that the Target Time registers are programmed for generating the interrupt event and starting or stopping the generation of the PPS0 output signal. +- 11: Indicates that the Target Time registers are programmed only for starting or stopping the generation of the PPS0 output signal. No interrupt is asserted. + 5 + 2 + read-write + + + PPSEN0 + Flexible PPS Output Mode Enable +When set low, Bits [3:0] function as PPSCTRL (backward compatible). When set high, Bits[3:0] function as PPSCMD. + 4 + 1 + read-write + + + PPSCTRLCMD0 + PPSCTRL0: PPS0 Output Frequency Control +This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. The default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width clk_ptp_i) every second. For other values of PPSCTRL, the PPS output becomes a generated clock of following frequencies: +- 0001: The binary rollover is 2 Hz, and the digital rollover is 1 Hz. +- 0010: The binary rollover is 4 Hz, and the digital rollover is 2 Hz. +- 0011: The binary rollover is 8 Hz, and the digital rollover is 4 Hz. +- 0100: The binary rollover is 16 Hz, and the digital rollover is 8 Hz. - ... +- 1111: The binary rollover is 32.768 KHz, and the digital rollover is 16.384 KHz. Note: In the binary rollover mode, the PPS output (ptp_pps_o) has a duty cycle of 50 percent with these frequencies. In the digital rollover mode, the PPS output frequency is an average number. The actual clock is of different frequency that gets synchronized every second. For example: - When PPSCTRL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high period of 463 ms - When PPSCTRL = 0010, the PPS (2 Hz) is a sequence of: - One clock of 50 percent duty cycle and 537 ms period - Second clock of 463 ms period (268 ms low and 195 ms high) - When PPSCTRL = 0011, the PPS (4 Hz) is a sequence of: - Three clocks of 50 percent duty cycle and 268 ms period - Fourth clock of 195 ms period (134 ms low and 61 ms high) +PPSCMD0: Flexible PPS0 Output Control +0000: No Command +0001: START Single Pulse +This command generates single pulse rising at the start point defined in +Target Time Registers and of a duration defined +in the PPS0 Width Register. +0010: START Pulse Train +This command generates the train of pulses rising at the start point +defined in the Target Time Registers and of a duration defined in the +PPS0 Width Register and repeated at interval defined in the PPS +Interval Register. By default, the PPS pulse train is free-running unless +stopped by ‘STOP Pulse train at time’ or ‘STOP Pulse Train +immediately’ commands. +0011: Cancel START +This command cancels the START Single Pulse and START Pulse Train +commands if the system time has not crossed the programmed start +time. +0100: STOP Pulse train at time +This command stops the train of pulses initiated by the START Pulse +Train command (PPSCMD = 0010) after the time programmed in the +Target Time registers elapses. +0101: STOP Pulse Train immediately +This command immediately stops the train of pulses initiated by the +START Pulse Train command (PPSCMD = 0010). +0110: Cancel STOP Pulse train +This command cancels the STOP pulse train at time command if the +programmed stop time has not elapsed. The PPS pulse train becomes +free-running on the successful execution of this command. +0111-1111: Reserved +Note: These bits get cleared automatically + 0 + 4 + read-write + + + + + AUX_TS_NSEC + Auxiliary Timestamp - Nanoseconds Register + 0x730 + 32 + 0x00000000 + 0x7FFFFFFF + + + AUXTSLO + Contains the lower 31 bits (nano-seconds field) of the auxiliary timestamp. + 0 + 31 + read-only + + + + + AUX_TS_SEC + Auxiliary Timestamp - Seconds Register + 0x734 + 32 + 0x00000000 + 0xFFFFFFFF + + + AUXTSHI + Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. + 0 + 32 + read-only + + + + + PPS0_INTERVAL + PPS0 Interval Register + 0x760 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPSINT + PPS0 Output Signal Interval +These bits store the interval between the rising edges of PPS0 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS0 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. + 0 + 32 + read-write + + + + + PPS0_WIDTH + PPS0 Width Register + 0x764 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPSWIDTH + PPS0 Output Signal Width +These bits store the width between the rising edge and corresponding falling edge of the PPS0 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS0 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. + 0 + 32 + read-write + + + + + 3 + 0x20 + 1,2,3 + PPS[%s] + no description available + 0x780 + + TGTTM_SEC + PPS Target Time Seconds Register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSTRH1 + PPS1 Target Time Seconds Register +This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [14:13], TRGTMODSEL1, of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). + 0 + 32 + read-write + + + + + TGTTM_NSEC + PPS Target Time Nanoseconds Register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRGTBUSY1 + PPS1 Target Time Register Busy +The MAC sets this bit when the PPSCMD1 field (Bits [10:8]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. + 31 + 1 + read-write + + + TTSL1 + Target Time Low for PPS1 Register +This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL1 field (Bits [14:13]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. + 0 + 31 + read-write + + + + + INTERVAL + PPS Interval Register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPSINT + PPS1 Output Signal Interval +These bits store the interval between the rising edges of PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS1 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. + 0 + 32 + read-write + + + + + WIDTH + PPS Width Register + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + PPSWIDTH + PPS1 Output Signal Width +These bits store the width between the rising edge and corresponding falling edge of the PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS1 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. + 0 + 32 + read-write + + + + + + DMA_BUS_MODE + Bus Mode Register + 0x1000 + 32 + 0x00000000 + 0xBFFFFFFF + + + RIB + Rebuild INCRx Burst +When this bit is set high and the AHB master gets an EBT (Retry, Split, or Losing bus grant), the AHB master interface rebuilds the pending beats of any burst transfer initiated with INCRx. The AHB master interface rebuilds the beats with a combination of specified bursts with INCRx and SINGLE. By default, the AHB master interface rebuilds pending beats of an EBT with an unspecified (INCR) burst. + 31 + 1 + read-write + + + PRWG + Channel Priority +Weights This field sets the priority weights for Channel 0 during the round-robin arbitration between the DMA channels for the system bus. +- 00: The priority weight is 1. +- 01: The priority weight is 2. +- 10: The priority weight is 3. +- 11: The priority weight is 4. This field is present in all DWC_gmac configurations except GMAC-AXI when you select the AV feature. Otherwise, this field is reserved and read-only (RO). + 28 + 2 + read-write + + + TXPR + Transmit Priority +When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus. In the GMAC-AXI configuration, this bit is reserved and read-only (RO). + 27 + 1 + read-write + + + MB + Mixed Burst +When this bit is set high and the FB bit is low, the AHB master interface starts all bursts of length more than 16 with INCR (undefined burst), whereas it reverts to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less. + 26 + 1 + read-write + + + AAL + Address-Aligned Beats +When this bit is set high and the FB bit is equal to 1, the AHB or AXI interface generates all bursts aligned to the start address LS bits. If the FB bit is equal to 0, the first burst (accessing the start address of data buffer) is not aligned, but subsequent bursts are aligned to the address. + 25 + 1 + read-write + + + PBLX8 + PBLx8 Mode +When set high, this bit multiplies the programmed PBL value (Bits [22:17] and Bits[13:8]) eight times. Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. + 24 + 1 + read-write + + + USP + Use Separate PBL +When set high, this bit configures the Rx DMA to use the value configured in Bits [22:17] as PBL. The PBL value in Bits [13:8] is applicable only to the Tx DMA operations. When reset to low, the PBL value in Bits [13:8] is applicable for both DMA engines. + 23 + 1 + read-write + + + RPBL + Rx DMA PBL +This field indicates the maximum number of beats to be transferred in one Rx DMA transaction. This is the maximum value that is used in a single block Read or Write. The Rx DMA always attempts to burst as specified in the RPBL bit each time it starts a Burst transfer on the host bus. You can program RPBL with values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. This field is valid and applicable only when USP is set high. + 17 + 6 + read-write + + + FB + Fixed Burst + This bit controls whether the AHB or AXI master interface performs fixed burst transfers or not. When set, the AHB interface uses only SINGLE, INCR4, INCR8, or INCR16 during start of the normal burst transfers. When reset, the AHB or AXI interface uses SINGLE and INCR burst transfer operations. + 16 + 1 + read-write + + + PR + Priority Ratio + These bits control the priority ratio in the weighted round-robin arbitration between the Rx DMA and Tx DMA. These bits are valid only when Bit 1 (DA) is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 (TXPR) is reset or set. +- 00: The Priority Ratio is 1:1. +- 01: The Priority Ratio is 2:1. +- 10: The Priority Ratio is 3:1. +- 11: The Priority Ratio is 4:1. + 14 + 2 + read-write + + + PBL + Programmable Burst Length +These bits indicate the maximum number of beats to be transferred in one DMA transaction. This is the maximum value that is used in a single block Read or Write. The DMA always attempts to burst as specified in PBL each time it starts a Burst transfer on the host bus. PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. When USP is set high, this PBL value is applicable only for Tx DMA transactions. If the number of beats to be transferred is more than 32, then perform the following steps: 1. Set the PBLx8 mode. 2. Set the PBL. + 8 + 6 + read-write + + + ATDS + Alternate Descriptor Size +When set, the size of the alternate descriptor (described in “Alternate or Enhanced Descriptors” on page 545) increases to 32 bytes (8 DWORDS). This is required when the Advanced Timestamp feature or the IPC Full Checksum Offload Engine (Type 2) is enabled in the receiver. The enhanced descriptor is not required if the Advanced Timestamp and IPC Full Checksum Offload Engine (Type 2) features are not enabled. In such case, you can use the 16 bytes descriptor to save 4 bytes of memory. This bit is present only when you select the Alternate Descriptor feature and any one of the following features during core configuration: - Advanced Timestamp feature - IPC Full Checksum Offload Engine (Type 2) feature Otherwise, this bit is reserved and is read-only. When reset, the descriptor size reverts back to 4 DWORDs (16 bytes). + 7 + 1 + read-write + + + DSL + Descriptor Skip Length +This bit specifies the number of Word, Dword, or Lword (depending on the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors. The address skipping starts from the end of current descriptor to the start of next descriptor. When the DSL value is equal to zero, the descriptor table is taken as contiguous by the DMA in Ring mode. + 2 + 5 + read-write + + + DA + DMA Arbitration Scheme +This bit specifies the arbitration scheme between the transmit and receive paths of Channel 0. +- 0: Weighted round-robin with Rx:Tx or Tx:Rx The priority between the paths is according to the priority specified in Bits [15:14] (PR) and priority weights specified in Bit 27 (TXPR). +- 1: Fixed priority The transmit path has priority over receive path when Bit 27 (TXPR) is set. Otherwise, receive path has priority over the transmit path. + 1 + 1 + read-write + + + SWR + Software Reset + When this bit is set, the MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after the reset operation is complete in all of the DWC_gmac clock domains. Before reprogramming any register of the DWC_gmac, you should read a zero (0) value in this bit. Note: - The Software reset function is driven only by this bit. Bit 0 of Register 64 (Channel 1 Bus Mode Register) or Register 128 (Channel 2 Bus Mode Register) has no impact on the Software reset function. - The reset operation is completed only when all resets in all active clock domains are de-asserted. Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for the software reset completion. The time to complete the software reset operation depends on the frequency of the slowest active clock. + 0 + 1 + read-write + + + + + DMA_TX_POLL_DEMAND + Transmit Poll Demand Register + 0x1004 + 32 + 0x00000000 + 0xFFFFFFFF + + + TPD + Transmit Poll Demand +When these bits are written with any value, the DMA reads the current descriptor to which the Register 18 (Current Host Transmit Descriptor Register) is pointing. If that descriptor is not available (owned by the Host), the transmission returns to the Suspend state and Bit 2 (TU) of Register 5 (Status Register) is asserted. If the descriptor is available, the transmission resumes. + 0 + 32 + read-write + + + + + DMA_RX_POLL_DEMAND + Receive Poll Demand Register + 0x1008 + 32 + 0x00000000 + 0xFFFFFFFF + + + RPD + Receive Poll Demand +When these bits are written with any value, the DMA reads the current descriptor to which the Register 19 (Current Host Receive Descriptor Register) is pointing. If that descriptor is not available (owned by the Host), the reception returns to the Suspended state and Bit 7 (RU) of Register 5 (Status Register) is asserted. If the descriptor is available, the Rx DMA returns to the active state. + 0 + 32 + read-write + + + + + DMA_RX_DESC_LIST_ADDR + Receive Descriptor List Address Register + 0x100c + 32 + 0x00000000 + 0xFFFFFFFF + + + RDESLA + Start of Receive List +This field contains the base address of the first descriptor in the Receive Descriptor list. The LSB bits (1:0, 2:0, or 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). + 0 + 32 + read-write + + + + + DMA_TX_DESC_LIST_ADDR + Transmit Descriptor List Address Register + 0x1010 + 32 + 0x00000000 + 0xFFFFFFFF + + + TDESLA + Start of Transmit List +This field contains the base address of the first descriptor in the Transmit Descriptor list. The LSB bits (1:0, 2:0, 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and are internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). + 0 + 32 + read-write + + + + + DMA_STATUS + Status Register + 0x1014 + 32 + 0x00000000 + 0x7FFFE7FF + + + GLPII + GLPII: GMAC LPI Interrupt (for Channel 0) +This bit indicates an interrupt event in the LPI logic of the MAC. To reset this bit to 1'b0, the software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source. Note: GLPII status is given only in Channel 0 DMA register and is applicable only when the Energy Efficient Ethernet feature is enabled. Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. -or- GTMSI: GMAC TMS Interrupt (for Channel 1 and Channel 2) This bit indicates an interrupt event in the traffic manager and scheduler logic of DWC_gmac. To reset this bit, the software must read the corresponding registers (Channel Status Register) to get the exact cause of the interrupt and clear its source. Note: GTMSI status is given only in Channel 1 and Channel 2 DMA register when the AV feature is enabled and corresponding additional transmit channels are present. Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. + 30 + 1 + read-write + + + TTI + Timestamp Trigger Interrupt +This bit indicates an interrupt event in the Timestamp Generator block of the DWC_gmac. The software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source to reset this bit to 1'b0. When this bit is high, the interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high. This bit is applicable only when the IEEE 1588 Timestamp feature is enabled. Otherwise, this bit is reserved. + 29 + 1 + read-write + + + GPI + GMAC PMT Interrupt +This bit indicates an interrupt event in the PMT module of the DWC_gmac. The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1’b0. The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. This bit is applicable only when the Power Management feature is enabled. Otherwise, this bit is reserved. Note: The GPI and pmt_intr_o interrupts are generated in different clock domains. + 28 + 1 + read-write + + + GMI + GMAC MMC Interrupt + This bit reflects an interrupt event in the MMC module of the DWC_gmac. The software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear the source of interrupt to make this bit as 1’b0. The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. This bit is applicable only when the MAC Management Counters (MMC) are enabled. Otherwise, this bit is reserved. + 27 + 1 + read-write + + + GLI + GMAC Line Interface Interrupt +When set, this bit reflects any of the following interrupt events in the DWC_gmac interfaces (if present and enabled in your configuration): - PCS (TBI, RTBI, or SGMII): Link change or auto-negotiation complete event - SMII or RGMII: Link change event - General Purpose Input Status (GPIS): Any LL or LH event on the gpi_i input ports To identify the exact cause of the interrupt, the software must first read Bit 11 and Bits[2:0] of Register 14 (Interrupt Status Register) and then to clear the source of interrupt (which also clears the GLI interrupt), read any of the following corresponding registers: - PCS (TBI, RTBI, or SGMII): Register 49 (AN Status Register) - SMII or RGMII: Register 54 (SGMII/RGMII/SMII Control and Status Register) - General Purpose Input (GPI): Register 56 (General Purpose IO Register) The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. + 26 + 1 + read-write + + + EB + Error Bits +This field indicates the type of error that caused a Bus Error, for example, error response on the AHB or AXI interface. This field is valid only when Bit 13 (FBI) is set. This field does not generate an interrupt. +- 0 0 0: Error during Rx DMA Write Data Transfer +- 0 1 1: Error during Tx DMA Read Data Transfer +- 1 0 0: Error during Rx DMA Descriptor Write Access +- 1 0 1: Error during Tx DMA Descriptor Write Access +- 1 1 0: Error during Rx DMA Descriptor Read Access +- 1 1 1: Error during Tx DMA Descriptor Read Access Note: 001 and 010 are reserved. + 23 + 3 + read-write + + + TS + Transmit Process State +This field indicates the Transmit DMA FSM state. This field does not generate an interrupt. +- 3’b000: Stopped; Reset or Stop Transmit Command issued +- 3’b001: Running; Fetching Transmit Transfer Descriptor +- 3’b010: Running; Waiting for status +- 3’b011: Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO) +- 3’b100: TIME_STAMP write state +- 3’b101: Reserved for future use +- 3’b110: Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow +- 3’b111: Running; Closing Transmit Descriptor + 20 + 3 + read-write + + + RS + Receive Process State +This field indicates the Receive DMA FSM state. This field does not generate an interrupt. +- 3’b000: Stopped: Reset or Stop Receive Command issued +- 3’b001: Running: Fetching Receive Transfer Descriptor +- 3’b010: Reserved for future use +- 3’b011: Running: Waiting for receive packet +- 3’b100: Suspended: Receive Descriptor Unavailable +- 3’b101: Running: Closing Receive Descriptor +- 3’b110: TIME_STAMP write state +- 3’b111: Running: Transferring the receive packet data from receive buffer to host memory + 17 + 3 + read-write + + + NIS + Normal Interrupt Summary +Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register): - Register 5[0]: Transmit Interrupt - Register 5[2]: Transmit Buffer Unavailable - Register 5[6]: Receive Interrupt - Register 5[14]: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt enable is set in Register 7) affect the Normal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes NIS to be set, is cleared. + 16 + 1 + read-write + + + AIS + Abnormal Interrupt Summary +Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register): - Register 5[1]: Transmit Process Stopped - Register 5[3]: Transmit Jabber Timeout - Register 5[4]: Receive FIFO Overflow - Register 5[5]: Transmit Underflow - Register 5[7]: Receive Buffer Unavailable - Register 5[8]: Receive Process Stopped - Register 5[9]: Receive Watchdog Timeout - Register 5[10]: Early Transmit Interrupt - Register 5[13]: Fatal Bus Error Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes AIS to be set, is cleared. + 15 + 1 + read-write + + + ERI + Early Receive Interrupt +This bit indicates that the DMA filled the first data buffer of the packet. This bit is cleared when the software writes 1 to this bit or Bit 6 (RI) of this register is set (whichever occurs earlier). + 14 + 1 + read-write + + + FBI + Fatal Bus Error Interrupt +This bit indicates that a bus error occurred, as described in Bits [25:23]. When this bit is set, the corresponding DMA engine disables all of its bus accesses. + 13 + 1 + read-write + + + ETI + Early Transmit Interrupt +This bit indicates that the frame to be transmitted is fully transferred to the MTL Transmit FIFO. + 10 + 1 + read-write + + + RWT + Receive Watchdog Timeout +When set, this bit indicates that the Receive Watchdog Timer expired while receiving the current frame and the current frame is truncated after the watchdog timeout. + 9 + 1 + read-write + + + RPS + Receive Process Stopped +This bit is asserted when the Receive Process enters the Stopped state. + 8 + 1 + read-write + + + RU + Receive Buffer Unavailable +This bit indicates that the host owns the Next Descriptor in the Receive List and the DMA cannot acquire it. The Receive Process is suspended. To resume processing Receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, the Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor is owned by the DMA. + 7 + 1 + read-write + + + RI + Receive Interrupt +This bit indicates that the frame reception is complete. When reception is complete, the Bit 31 of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor, and the specific frame status information is updated in the descriptor. The reception remains in the Running state. + 6 + 1 + read-write + + + UNF + Transmit Underflow +This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set. + 5 + 1 + read-write + + + OVF + Receive Overflow +This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to the application, the overflow status is set in RDES0[11]. + 4 + 1 + read-write + + + TJT + Transmit Jabber Timeout +This bit indicates that the Transmit Jabber Timer expired, which happens when the frame size exceeds 2,048 (10,240 bytes when the Jumbo frame is enabled). When the Jabber Timeout occurs, the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert. + 3 + 1 + read-write + + + TU + Transmit Buffer Unavailable +This bit indicates that the host owns the Next Descriptor in the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing Transmit descriptors, the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command. + 2 + 1 + read-write + + + TPS + Transmit Process Stopped +This bit is set when the transmission is stopped. + 1 + 1 + read-write + + + TI + Transmit Interrupt +This bit indicates that the frame transmission is complete. When transmission is complete, Bit 31 (OWN) of TDES0 is reset, and the specific frame status information is updated in the descriptor. + 0 + 1 + read-write + + + + + DMA_OP_MODE + Operation Mode Register + 0x1018 + 32 + 0x00000000 + 0x13F1FFFE + + + DT + Disable Dropping of TCP/IP Checksum Error Frames +When this bit is set, the MAC does not drop the frames which only have errors detected by the Receive Checksum Offload engine. Such frames do not have any errors (including FCS error) in the Ethernet frame received by the MAC but have errors only in the encapsulated payload. When this bit is reset, all error frames are dropped if the FEF bit is reset. If the IPC Full Checksum Offload Engine (Type 2) is disabled, this bit is reserved (RO with value 1'b0). + 28 + 1 + read-write + + + RSF + Receive Store and Forward +When this bit is set, the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it, ignoring the RTC bits. When this bit is reset, the Rx FIFO operates in the cut-through mode, subject to the threshold specified by the RTC bits. + 25 + 1 + read-write + + + DFF + Disable Flushing of Received Frames +When this bit is set, the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers as it does normally when this bit is reset. (See “Receive Process Suspended” on page 83.) + 24 + 1 + read-write + + + RFA_2 + MSB of Threshold for Activating Flow Control +If the DWC_gmac is configured for an Rx FIFO size of 8 KB or more, this bit (when set) provides additional threshold levels for activating the flow control in both half-duplex and full-duplex modes. This bit (as Most Significant Bit), along with the RFA (Bits [10:9]), gives the following thresholds for activating flow control: +- 100: Full minus 5 KB, that is, FULL — 5 KB +- 101: Full minus 6 KB, that is, FULL — 6 KB +- 110: Full minus 7 KB, that is, FULL — 7 KB +- 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. + 23 + 1 + read-write + + + RFD_2 + MSB of Threshold for Deactivating Flow Control +If the DWC_gmac is configured for Rx FIFO size of 8 KB or more, this bit (when set) provides additional threshold levels for deactivating the flow control in both half-duplex and full-duplex modes. This bit (as Most Significant Bit) along with the RFD (Bits [12:11]) gives the following thresholds for deactivating flow control: +- 100: Full minus 5 KB, that is, FULL — 5 KB +- 101: Full minus 6 KB, that is, FULL — 6 KB +- 110: Full minus 7 KB, that is, FULL — 7 KB +- 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. + 22 + 1 + read-write + + + TSF + Transmit Store and Forward +When this bit is set, transmission starts when a full frame resides in the MTL Transmit FIFO. When this bit is set, the TTC values specified in Bits [16:14] are ignored. This bit should be changed only when the transmission is stopped. + 21 + 1 + read-write + + + FTF + Flush Transmit FIFO +When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flushed. This bit is cleared internally when the flushing operation is complete. The Operation Mode register should not be written to until this bit is cleared. The data which is already accepted by the MAC transmitter is not flushed. It is scheduled for transmission and results in underflow and runt frame transmission. + 20 + 1 + read-write + + + TTC + Transmit Threshold Control +These bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are also transmitted. These bits are used only when Bit 21 (TSF) is reset. +- 000: 64 +- 001: 128 +- 010: 192 +- 011: 256 +- 100: 40 +- 101: 32 +- 110: 24 +- 111: 16 + 14 + 3 + read-write + + + ST + Start or Stop Transmission Command +When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. Descriptor acquisition is attempted either from the current position in the list, which is the Transmit List Base Address set by Register 4 (Transmit Descriptor List Address Register), or from the position retained when transmission was stopped previously. If the DMA does not own the current descriptor, transmission enters the Suspended state and Bit 2 (Transmit Buffer Unavailable) of Register 5 (Status Register) is set. The Start Transmission command is effective only when transmission is stopped. If the command is issued before setting Register 4 (Transmit Descriptor List Address Register), then the DMA behavior is unpredictable. When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current frame. The Next Descriptor position in the Transmit List is saved, and it becomes the current position when transmission is restarted. To change the list address, you need to program Register 4 (Transmit Descriptor List Address Register) with a new value when this bit is reset. The new value is considered when this bit is set again. The stop transmission command is effective only when the transmission of the current frame is complete or the transmission is in the Suspended state. + 13 + 1 + read-write + + + RFD + Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (Fill-level of Rx FIFO) at which the flow control is de-asserted after activation. +- 00: Full minus 1 KB, that is, FULL — 1 KB +- 01: Full minus 2 KB, that is, FULL — 2 KB +- 10: Full minus 3 KB, that is, FULL — 3 KB +- 11: Full minus 4 KB, that is, FULL — 4 KB The de-assertion is effective only after flow control is asserted. If the Rx FIFO is 8 KB or more, an additional Bit (RFD_2) is used for more threshold levels as described in Bit 22. These bits are reserved and read-only when the Rx FIFO depth is less than 4 KB. + 11 + 2 + read-write + + + RFA + Threshold for Activating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (Fill level of Rx FIFO) at which the flow control is activated. +- 00: Full minus 1 KB, that is, FULL—1KB. +- 01: Full minus 2 KB, that is, FULL—2KB. +- 10: Full minus 3 KB, that is, FULL—3KB. +- 11: Full minus 4 KB, that is, FULL—4KB. These values are applicable only to Rx FIFOs of 4 KB or more and when Bit 8 (EFC) is set high. If the Rx FIFO is 8 KB or more, an additional Bit (RFA_2) is used for more threshold levels as described in Bit 23. These bits are reserved and read-only when the depth of Rx FIFO is less than 4 KB. Note: When FIFO size is exactly 4 KB, although the DWC_gmac allows you to program the value of these bits to 11, the software should not program these bits to 2'b11. The value 2'b11 means flow control on FIFO empty condition + 9 + 2 + read-write + + + EFC + Enable HW Flow Control +When this bit is set, the flow control signal operation based on the fill-level of Rx FIFO is enabled. When reset, the flow control operation is disabled. This bit is not used (reserved and always reset) when the Rx FIFO is less than 4 KB. + 8 + 1 + read-write + + + FEF + Forward Error Frames +When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or overflow). However, if the start byte (write) pointer of a frame is already transferred to the read controller side (in Threshold mode), then the frame is not dropped. In the GMAC-MTL configuration in which the Frame Length FIFO is also enabled during core configuration, the Rx FIFO drops the error frames if that frame's start byte is not transferred (output) on the ARI bus. When the FEF bit is set, all frames except runt error frames are forwarded to the DMA. If the Bit 25 (RSF) is set and the Rx FIFO overflows when a partial frame is written, then the frame is dropped irrespective of the FEF bit setting. However, if the Bit 25 (RSF) is reset and the Rx FIFO overflows when a partial frame is written, then a partial frame may be forwarded to the DMA. Note: When FEF bit is reset, the giant frames are dropped if the giant frame status is given in Rx Status (in Table 8-6 or Table 8-23) in the following configurations: - The IP checksum engine (Type 1) and full checksum offload engine (Type 2) are not selected. - The advanced timestamp feature is not selected but the extended status is selected. The extended status is available with the following features: - L3-L4 filter in GMAC-CORE or GMAC-MTL configurations - Full checksum offload engine (Type 2) with enhanced descriptor format in the GMAC-DMA, GMAC-AHB, or GMAC-AXI configurations. + 7 + 1 + read-write + + + FUF + Forward Undersized Good Frames +When set, the Rx FIFO forwards Undersized frames (that is, frames with no Error and length less than 64 bytes) including pad-bytes and CRC. When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a frame is already transferred because of the lower value of Receive Threshold, for example, RTC = 01. + 6 + 1 + read-write + + + DGF + Drop Giant Frames +When set, the MAC drops the received giant frames in the Rx FIFO, that is, frames that are larger than the computed giant frame limit. When reset, the MAC does not drop the giant frames in the Rx FIFO. Note: This bit is available in the following configurations in which the giant frame status is not provided in Rx status and giant frames are not dropped by default: - Configurations in which IP Checksum Offload (Type 1) is selected in Rx - Configurations in which the IPC Full Checksum Offload Engine (Type 2) is selected in Rx with normal descriptor format - Configurations in which the Advanced Timestamp feature is selected In all other configurations, this bit is not used (reserved and always reset). + 5 + 1 + read-write + + + RTC + Receive Threshold Control +These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. In addition, full frames with length less than the threshold are automatically transferred. The value of 11 is not applicable if the configured Receive FIFO size is 128 bytes. These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1. +- 00: 64 +- 01: 32 +- 10: 96 +- 11: 128 + 3 + 2 + read-write + + + OSF + Operate on Second Frame +When this bit is set, it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained. + 2 + 1 + read-write + + + SR + Start or Stop Receive +When this bit is set, the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames. The descriptor acquisition is attempted from the current position in the list, which is the address set by the Register 3 (Receive Descriptor List Address Register) or the position retained when the Receive process was previously stopped. If the DMA does not own the descriptor, reception is suspended and Bit 7 (Receive Buffer Unavailable) of Register 5 (Status Register) is set. The Start Receive command is effective only when the reception has stopped. If the command is issued before setting Register 3 (Receive Descriptor List Address Register), the DMA behavior is unpredictable. When this bit is cleared, the Rx DMA operation is stopped after the transfer of the current frame. The next descriptor position in the Receive list is saved and becomes the current position after the Receive process is restarted. The Stop Receive command is effective only when the Receive process is in either the Running (waiting for receive packet) or in the Suspended state. + 1 + 1 + read-write + + + + + DMA_INTR_EN + Interrupt Enable Register + 0x101c + 32 + 0x00000000 + 0x0001E7FF + + + NIE + Normal Interrupt Summary Enable +When this bit is set, normal interrupt summary is enabled. When this bit is reset, normal interrupt summary is disabled. This bit enables the following interrupts in Register 5 (Status Register): - Register 5[0]: Transmit Interrupt - Register 5[2]: Transmit Buffer Unavailable - Register 5[6]: Receive Interrupt - Register 5[14]: Early Receive Interrupt + 16 + 1 + read-write + + + AIE + Abnormal Interrupt Summary Enable +When this bit is set, abnormal interrupt summary is enabled. When this bit is reset, the abnormal interrupt summary is disabled. This bit enables the following interrupts in Register 5 (Status Register): - Register 5[1]: Transmit Process Stopped - Register 5[3]: Transmit Jabber Timeout - Register 5[4]: Receive Overflow - Register 5[5]: Transmit Underflow - Register 5[7]: Receive Buffer Unavailable - Register 5[8]: Receive Process Stopped - Register 5[9]: Receive Watchdog Timeout - Register 5[10]: Early Transmit Interrupt - Register 5[13]: Fatal Bus Error + 15 + 1 + read-write + + + ERE + Early Receive Interrupt Enable +When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Early Receive Interrupt is enabled. When this bit is reset, the Early Receive Interrupt is disabled. + 14 + 1 + read-write + + + FBE + Fatal Bus Error Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Fatal Bus Error Interrupt is enabled. When this bit is reset, the Fatal Bus Error Enable Interrupt is disabled. + 13 + 1 + read-write + + + ETE + Early Transmit Interrupt Enable +When this bit is set with an Abnormal Interrupt Summary Enable (Bit 15), the Early Transmit Interrupt is enabled. When this bit is reset, the Early Transmit Interrupt is disabled. + 10 + 1 + read-write + + + RWE + Receive Watchdog Timeout Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, the Receive Watchdog Timeout Interrupt is disabled. + 9 + 1 + read-write + + + RSE + Receive Stopped Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped Interrupt is disabled. + 8 + 1 + read-write + + + RUE + Receive Buffer Unavailable Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled. + 7 + 1 + read-write + + + RIE + Receive Interrupt Enable +When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Receive Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled. + 6 + 1 + read-write + + + UNE + Underflow Interrupt Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Underflow Interrupt is enabled. When this bit is reset, the Underflow Interrupt is disabled. + 5 + 1 + read-write + + + OVE + Overflow Interrupt Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Overflow Interrupt is enabled. When this bit is reset, the Overflow Interrupt is disabled. + 4 + 1 + read-write + + + TJE + Transmit Jabber Timeout Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, the Transmit Jabber Timeout Interrupt is disabled. + 3 + 1 + read-write + + + TUE + Transmit Buffer Unavailable Enable +When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled. + 2 + 1 + read-write + + + TSE + Transmit Stopped Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmission Stopped Interrupt is enabled. When this bit is reset, the Transmission Stopped Interrupt is disabled. + 1 + 1 + read-write + + + TIE + Transmit Interrupt Enable +When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Interrupt is enabled. When this bit is reset, the Transmit Interrupt is disabled. + 0 + 1 + read-write + + + + + DMA_MISS_OVF_CNT + Missed Frame And Buffer Overflow Counter Register + 0x1020 + 32 + 0x00000000 + 0x1FFFFFFF + + + ONFCNTOVF + Overflow Bit for FIFO Overflow Counter +This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows, that is, the Rx FIFO overflows with the overflow frame counter at maximum value. In such a scenario, the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened. + 28 + 1 + read-write + + + OVFFRMCNT + Overflow Frame Counter +This field indicates the number of frames missed by the application. This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read with mci_be_i[2] at 1’b1. + 17 + 11 + read-write + + + MISCNTOVF + Overflow Bit for Missed Frame Counter +This bit is set every time Missed Frame Counter (Bits[15:0]) overflows, that is, the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value. In such a scenario, the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened. + 16 + 1 + read-write + + + MISFRMCNT + Missed Frame Counter +This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with mci_be_i[0] at 1’b1. + 0 + 16 + read-write + + + + + DMA_RX_INTR_WDOG + Receive Interrupt Watchdog Timer Register + 0x1024 + 32 + 0x00000000 + 0x000000FF + + + RIWT + RI Watchdog Timer Count +This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer of a frame for which the RI status bit is not set because of the setting in the corresponding descriptor RDES1[31]. When the watchdog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame. + 0 + 8 + read-write + + + + + DMA_AXI_MODE + AXI Bus Mode Register + 0x1028 + 32 + 0x00000000 + 0xC0FF30FF + + + EN_LPI + Enable Low Power Interface (LPI) +When set to 1, this bit enables the LPI mode supported by the GMAC-AXI configuration and accepts the LPI request from the AXI System Clock controller. When set to 0, this bit disables the LPI mode and always denies the LPI request from the AXI System Clock controller. + 31 + 1 + read-write + + + LPI_XIT_FRM + Unlock on Magic Packet or Remote Wake-Up Frame +When set to 1, this bit enables the GMAC-AXI to come out of the LPI mode only when the magic packet or remote wake-up frame is received. When set to 0, this bit enables the GMAC-AXI to come out of LPI mode when any frame is received. + 30 + 1 + read-write + + + WR_OSR_LMT + AXI Maximum Write Outstanding Request Limit +This value limits the maximum outstanding request on the AXI write interface. Maximum outstanding requests = WR_OSR_LMT+1 Note: - Bit 22 is reserved if AXI_GM_MAX_WR_REQUESTS = 4. - Bit 23 bit is reserved if AXI_GM_MAX_WR_REQUESTS != 16. + 20 + 4 + read-write + + + RD_OSR_LMT + AXI Maximum Read Outstanding Request Limit +This value limits the maximum outstanding request on the AXI read interface. Maximum outstanding requests = RD_OSR_LMT+1 Note: - Bit 18 is reserved if AXI_GM_MAX_RD_REQUESTS = 4. - Bit 19 is reserved if AXI_GM_MAX_RD_REQUESTS != 16. + 16 + 4 + read-write + + + ONEKBBE + 1 KB Boundary Crossing Enable for the GMAC-AXI Master +When set, the GMAC-AXI master performs burst transfers that do not cross 1 KB boundary. When reset, the GMAC-AXI master performs burst transfers that do not cross 4 KB boundary. + 13 + 1 + read-write + + + AXI_AAL + Address-Aligned Beats +This bit is read-only bit and reflects the Bit 25 (AAL) of Register 0 (Bus Mode Register). When this bit is set to 1, the GMAC-AXI performs address-aligned burst transfers on both read and write channels. + 12 + 1 + read-write + + + BLEN256 + AXI Burst Length 256 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 256 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 256. Otherwise, this bit is reserved and is read-only (RO). + 7 + 1 + read-write + + + BLEN128 + AXI Burst Length 128 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 128 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 128 or more. Otherwise, this bit is reserved and is read-only (RO). + 6 + 1 + read-write + + + BLEN64 + AXI Burst Length 64 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 64 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 64 or more. Otherwise, this bit is reserved and is read-only (RO). + 5 + 1 + read-write + + + BLEN32 + AXI Burst Length 32 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 32 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 32 or more. Otherwise, this bit is reserved and is read-only (RO). + 4 + 1 + read-write + + + BLEN16 + AXI Burst Length 16 +When this bit is set to 1 or UNDEF is set to 1, the GMAC-AXI is allowed to select a burst length of 16 on the AXI master interface. + 3 + 1 + read-write + + + BLEN8 + AXI Burst Length 8 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 8 on the AXI master interface. Setting this bit has no effect when UNDEF is set to 1. + 2 + 1 + read-write + + + BLEN4 + AXI Burst Length 4 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 4 on the AXI master interface. Setting this bit has no effect when UNDEF is set to 1. + 1 + 1 + read-write + + + UNDEF + AXI Undefined Burst Length +This bit is read-only bit and indicates the complement (invert) value of Bit 16 (FB) in Register 0 (Bus Mode Register). - When this bit is set to 1, the GMAC-AXI is allowed to perform any burst length equal to or below the maximum allowed burst length programmed in Bits[7:3]. - When this bit is set to 0, the GMAC-AXI is allowed to perform only fixed burst lengths as indicated by BLEN256, BLEN128, BLEN64, BLEN32, BLEN16, BLEN8, or BLEN4, or a burst length of 1. If UNDEF is set and none of the BLEN bits is set, then GMAC-AXI is allowed to perform a burst length of 16. + 0 + 1 + read-write + + + + + DMA_BUS_STATUS + AHB or AXI Status Register + 0x102c + 32 + 0x00000000 + 0x00000003 + + + AXIRDSTS + AXI Master Read Channel Status +When high, it indicates that AXI master's read channel is active and transferring data. + 1 + 1 + read-write + + + AXWHSTS + AXI Master Write Channel or AHB Master Status +When high, it indicates that AXI master's write channel is active and transferring data in the GMAC-AXI configuration. In the GMAC-AHB configuration, it indicates that the AHB master interface FSMs are in the non-idle state. + 0 + 1 + read-write + + + + + DMA_CURR_HOST_TX_DESC + Current Host Transmit Descriptor Register + 0x1048 + 32 + 0x00000000 + 0xFFFFFFFF + + + CURTDESAPTR + Host Transmit Descriptor Address Pointer +Cleared on Reset. Pointer updated by the DMA during operation. + 0 + 32 + read-write + + + + + DMA_CURR_HOST_RX_DESC + Current Host Receive Descriptor Register + 0x104c + 32 + 0x00000000 + 0xFFFFFFFF + + + CURRDESAPTR + Host Receive Descriptor Address Pointer +Cleared on Reset. Pointer updated by the DMA during operation. + 0 + 32 + read-write + + + + + DMA_CURR_HOST_TX_BUF + Current Host Transmit Buffer Address Register + 0x1050 + 32 + 0x00000000 + 0xFFFFFFFF + + + CURTBUFAPTR + Host Transmit Buffer Address Pointer +Cleared on Reset. Pointer updated by the DMA during operation. + 0 + 32 + read-write + + + + + DMA_CURR_HOST_RX_BUF + Current Host Receive Buffer Address Register + 0x1054 + 32 + 0x00000000 + 0xFFFFFFFF + + + CURRBUFAPTR + Host Receive Buffer Address Pointer +Cleared on Reset. Pointer updated by the DMA during operation. + 0 + 32 + read-write + + + + + CTRL0 + Control Register 0 + 0x3000 + 32 + 0x00000000 + 0x00003F3F + + + ENET0_RXCLK_DLY_SEL + No description available + 8 + 6 + read-write + + + ENET0_TXCLK_DLY_SEL + No description available + 0 + 6 + read-write + + + + + CTRL2 + Control Register 1 + 0x3008 + 32 + 0x00000000 + 0x2008F400 + + + ENET0_LPI_IRQ_EN + lowpower interrupt enable, for internal use only, user should use core registers for enable/disable interrupt + 29 + 1 + read-write + + + ENET0_REFCLK_OE + set to enable output 50MHz clock to rmii phy. +User should set it if use soc internal clock as refclk + 19 + 1 + read-write + + + ENET0_PHY_INF_SEL + PHY mode select +000MII; 001RGMII; 100RMII; +should be set before config IOMUX, otherwise may cause glitch for RGMII + 13 + 3 + read-write + + + ENET0_FLOWCTRL + flow control request + 12 + 1 + read-write + + + ENET0_RMII_TXCLK_SEL + RMII mode output clock pad select +set to use txck as RMII refclk; +clr to use rxck as RMII refclk; default 0(rxck) +refclk is always from pad, can use external clock from pad, or use internal clock output to pad then loopback. + 10 + 1 + read-write + + + + + + + USB0 + USB0 + USB + 0xf1120000 + + 0x80 + 0x1a8 + registers + + + + GPTIMER0LD + General Purpose Timer #0 Load Register + 0x80 + 32 + 0x00000000 + 0x00FFFFFF + + + GPTLD + GPTLD +General Purpose Timer Load Value +These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. +This value represents the time in microseconds minus 1 for the timer duration. +Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. +NOTE: Max value is 0xFFFFFF or 16.777215 seconds. + 0 + 24 + read-write + + + + + GPTIMER0CTRL + General Purpose Timer #0 Controller Register + 0x84 + 32 + 0x00000000 + 0xC1FFFFFF + + + GPTRUN + GPTRUN +General Purpose Timer Run +GPTCNT bits are not effected when setting or clearing this bit. +0 - Stop counting +1 - Run + 31 + 1 + read-write + + + GPTRST + GPTRST +General Purpose Timer Reset +0 - No action +1 - Load counter value from GPTLD bits in n_GPTIMER0LD + 30 + 1 + write-only + + + GPTMODE + GPTMODE +General Purpose Timer Mode +In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is +reset by software; +In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the +counter value from GPTLD bits to start again. +0 - One Shot Mode +1 - Repeat Mode + 24 + 1 + read-write + + + GPTCNT + GPTCNT +General Purpose Timer Counter. +This field is the count value of the countdown timer. + 0 + 24 + read-only + + + + + GPTIMER1LD + General Purpose Timer #1 Load Register + 0x88 + 32 + 0x00000000 + 0x00FFFFFF + + + GPTLD + GPTLD +General Purpose Timer Load Value +These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. +This value represents the time in microseconds minus 1 for the timer duration. +Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. +NOTE: Max value is 0xFFFFFF or 16.777215 seconds. + 0 + 24 + read-write + + + + + GPTIMER1CTRL + General Purpose Timer #1 Controller Register + 0x8c + 32 + 0x00000000 + 0xC1FFFFFF + + + GPTRUN + GPTRUN +General Purpose Timer Run +GPTCNT bits are not effected when setting or clearing this bit. +0 - Stop counting +1 - Run + 31 + 1 + read-write + + + GPTRST + GPTRST +General Purpose Timer Reset +0 - No action +1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD + 30 + 1 + write-only + + + GPTMODE + GPTMODE +General Purpose Timer Mode +In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is +reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and +automatically reload the counter value from GPTLD bits to start again. +0 - One Shot Mode +1 - Repeat Mode + 24 + 1 + read-write + + + GPTCNT + GPTCNT +General Purpose Timer Counter. +This field is the count value of the countdown timer. + 0 + 24 + read-only + + + + + SBUSCFG + System Bus Config Register + 0x90 + 32 + 0x00000000 + 0x00000007 + + + AHBBRST + AHBBRST +AHB master interface Burst configuration +These bits control AHB master transfer type sequence (or priority). +NOTE: This register overrides n_BURSTSIZE register when its value is not zero. +000 - Incremental burst of unspecified length only +001 - INCR4 burst, then single transfer +010 - INCR8 burst, INCR4 burst, then single transfer +011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer +100 - Reserved, don't use +101 - INCR4 burst, then incremental burst of unspecified length +110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length +111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length + 0 + 3 + read-write + + + + + USBCMD + USB Command Register + 0x140 + 32 + 0x00080000 + 0x00FFFB7F + + + ITC + ITC +Interrupt Threshold Control -Read/Write. +The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. +ITC contains the maximum interrupt interval measured in micro-frames. Valid values are +shown below. +Value Maximum Interrupt Interval +00000000 - Immediate (no threshold) +00000001 - 1 micro-frame +00000010 - 2 micro-frames +00000100 - 4 micro-frames +00001000 - 8 micro-frames +00010000 - 16 micro-frames +00100000 - 32 micro-frames +01000000 - 64 micro-frames + 16 + 8 + read-write + + + FS_2 + FS_2 +Frame List Size - (Read/Write or Read Only). [host mode only] +This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. +This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. +NOTE: This field is made up from USBCMD bits 15, 3 and 2. +Value Meaning +0b000 - 1024 elements (4096 bytes) Default value +0b001 - 512 elements (2048 bytes) +0b010 - 256 elements (1024 bytes) +0b011 - 128 elements (512 bytes) +0b100 - 64 elements (256 bytes) +0b101 - 32 elements (128 bytes) +0b110 - 16 elements (64 bytes) +0b111 - 8 elements (32 bytes) + 15 + 1 + read-write + + + ATDTW + ATDTW +Add dTD TripWire - Read/Write. [device mode only] +This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's +linked list. This bit is set and cleared by software. +This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD +to a primed endpoint may go unrecognized. + 14 + 1 + read-write + + + SUTW + SUTW +Setup TripWire - Read/Write. [device mode only] +This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. +If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then +there is a hazard when new setup data arrives while the DCD is copying the setup data payload +from the QH for a previous setup packet. This bit is set and cleared by software. +This bit would also be cleared by hardware when a hazard detected. + 13 + 1 + read-write + + + PRM + Asynchronous Schedule start- Write only， host mode only。 +this bit is used to notify hostcontroller to start async schedule immediately. + 12 + 1 + write-only + + + ASPE + ASPE +Asynchronous Schedule Park Mode Enable - Read/Write. +If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. +Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. +When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. +NOTE: ASPE bit reset value: '0b' for OTG controller . + 11 + 1 + read-write + + + ASP + ASP +Asynchronous Schedule Park Mode Count - Read/Write. +If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. +It contains a count of the number of successive transactions the host controller is allowed to +execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. +Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. +This field is set to 3h in all controller core. + 8 + 2 + read-write + + + IAA + IAA +Interrupt on Async Advance Doorbell - Read/Write. +This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. +When the host controller has evicted all appropriate cached schedule states, +it sets the Interrupt on Async Advance status bit in the USBSTS register. +If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. +The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. +Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. +This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. + 6 + 1 + read-write + + + ASE + ASE +Asynchronous Schedule Enable - Read/Write. Default 0b. +This bit controls whether the host controller skips processing the Asynchronous Schedule. +Only the host controller uses this bit. +Values Meaning +0 - Do not process the Asynchronous Schedule. +1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. + 5 + 1 + read-write + + + PSE + PSE +Periodic Schedule Enable- Read/Write. Default 0b. +This bit controls whether the host controller skips processing the Periodic Schedule. +Only the host controller uses this bit. +Values Meaning +0 - Do not process the Periodic Schedule +1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. + 4 + 1 + read-write + + + FS_1 + FS_1 +See description at bit 15 + 2 + 2 + read-write + + + RST + RST +Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. +This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. +Host operation mode: +When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. +Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. +Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. +Attempting to reset an actively running host controller will result in undefined behavior. +Device operation mode: +When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. +Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. +In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. + 1 + 1 + read-write + + + RS + RS +Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. +Host operation mode: +When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. +When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. +The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. +Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). +Device operation mode: +Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. +This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. +Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. + 0 + 1 + read-write + + + + + USBSTS + USB Status Register + 0x144 + 32 + 0x00000000 + 0x030DF1FF + + + TI1 + TI1 +General Purpose Timer Interrupt 1(GPTINT1)--R/WC. +This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this +bit will clear it. + 25 + 1 + read-write + + + TI0 + TI0 +General Purpose Timer Interrupt 0(GPTINT0)--R/WC. +This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this +bit clears it. + 24 + 1 + read-write + + + UPI + USB Host Periodic Interrupt – RWC. Default = 0b. +This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction +where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. +This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. +A short packet is when the actual number of bytes received was less than expected. +This bit is not used by the device controller and will always be zero. + 19 + 1 + read-write + + + UAI + USB Host Asynchronous Interrupt – RWC. Default = 0b. +This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction +where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. +This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. +A short packet is when the actual number of bytes received was less than expected. +This bit is not used by the device controller and will always be zero + 18 + 1 + read-write + + + NAKI + NAKI +NAK Interrupt Bit--RO. +This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and +corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware +when all Enabled TX/RX Endpoint NAK bits are cleared. + 16 + 1 + read-only + + + AS + AS +Asynchronous Schedule Status - Read Only. +This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. +The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. +When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). +Only used in the host operation mode. + 15 + 1 + read-only + + + PS + PS +Periodic Schedule Status - Read Only. +This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. +The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. +When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). +Only used in the host operation mode. + 14 + 1 + read-only + + + RCL + RCL +Reclamation - Read Only. +This is a read-only status bit used to detect an empty asynchronous schedule. +Only used in the host operation mode. + 13 + 1 + read-only + + + HCH + HCH +HCHaIted - Read Only. +This bit is a zero whenever the Run/Stop bit is a one. + The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, + either by software or by the Controller hardware (for example, an internal error). +Only used in the host operation mode. +Default value is '0b' for OTG core . +This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE +register. +NOTE: HCH bit reset value: '0b' for OTG controller core . + 12 + 1 + read-only + + + SLI + SLI +DCSuspend - R/WC. +When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. +Only used in device operation mode. + 8 + 1 + read-write + + + SRI + SRI +SOF Received - R/WC. +When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. +When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. +Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. +Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. +In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. +Software writes a 1 to this bit to clear it. + 7 + 1 + read-write + + + URI + URI +USB Reset Received - R/WC. +When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. +Software can write a 1 to this bit to clear the USB Reset Received status bit. +Only used in device operation mode. + 6 + 1 + read-write + + + AAI + AAI +Interrupt on Async Advance - R/WC. +System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule +by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. +Only used in host operation mode. + 5 + 1 + read-write + + + SEI + System Error – RWC. Default = 0b. +In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. +In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) + 4 + 1 + read-write + + + FRI + FRI +Frame List Rollover - R/WC. +The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to +zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the +frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the +Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host +Controller sets this bit to a one every time FHINDEX [12] toggles. +Only used in host operation mode. + 3 + 1 + read-write + + + PCI + PCI +Port Change Detect - R/WC. +The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, +or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. +The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. +When the port controller exits the full or high-speed operation states due to Reset or Suspend events, +the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. + 2 + 1 + read-write + + + UEI + UEI +USB Error Interrupt (USBERRINT) - R/WC. +When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. +This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. + 1 + 1 + read-write + + + UI + UI +USB Interrupt (USBINT) - R/WC. +This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB +transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. +This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when +the actual number of bytes received was less than the expected number of bytes. + 0 + 1 + read-write + + + + + USBINTR + Interrupt Enable Register + 0x148 + 32 + 0x00000000 + 0x030D01FF + + + TIE1 + TIE1 +General Purpose Timer #1 Interrupt Enable +When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. + 25 + 1 + read-write + + + TIE0 + TIE0 +General Purpose Timer #0 Interrupt Enable +When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. + 24 + 1 + read-write + + + UPIE + UPIE +USB Host Periodic Interrupt Enable +When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an +interrupt at the next interrupt threshold. + 19 + 1 + read-write + + + UAIE + UAIE +USB Host Asynchronous Interrupt Enable +When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an +interrupt at the next interrupt threshold. + 18 + 1 + read-write + + + NAKE + NAKE +NAK Interrupt Enable +When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. + 16 + 1 + read-only + + + SLE + SLE +Sleep Interrupt Enable +When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. +Only used in device operation mode. + 8 + 1 + read-write + + + SRE + SRE +SOF Received Interrupt Enable +When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. + 7 + 1 + read-write + + + URE + URE +USB Reset Interrupt Enable +When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in device operation mode. + 6 + 1 + read-write + + + AAE + AAE +Async Advance Interrupt Enable +When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in host operation mode. + 5 + 1 + read-write + + + SEE + SEE +System Error Interrupt Enable +When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in host operation mode. + 4 + 1 + read-write + + + FRE + FRE +Frame List Rollover Interrupt Enable +When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in host operation mode. + 3 + 1 + read-write + + + PCE + PCE +Port Change Detect Interrupt Enable +When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. + 2 + 1 + read-write + + + UEE + UEE +USB Error Interrupt Enable +When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. + 1 + 1 + read-write + + + UE + UE +USB Interrupt Enable +When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. + 0 + 1 + read-write + + + + + FRINDEX + USB Frame Index Register + 0x14c + 32 + 0x00000000 + 0x00003FFF + + + FRINDEX + FRINDEX +Frame Index. +The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. +This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. +The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. +USBCMD [Frame List Size] Number Elements N +In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. +In either mode bits 2:0 indicate the current microframe. +The bit field values description below is represented as (Frame List Size) Number Elements N. +00000000000000 - (1024) 12 +00000000000001 - (512) 11 +00000000000010 - (256) 10 +00000000000011 - (128) 9 +00000000000100 - (64) 8 +00000000000101 - (32) 7 +00000000000110 - (16) 6 +00000000000111 - (8) 5 + 0 + 14 + read-write + + + + + DEVICEADDR + Device Address Register + UNION_154 + 0x154 + 32 + 0x00000000 + 0xFF000000 + + + USBADR + USBADR +Device Address. +These bits correspond to the USB device address + 25 + 7 + read-write + + + USBADRA + USBADRA +Device Address Advance. Default=0. +When this bit is '0', any writes to USBADR are instantaneous. + When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. +After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. +Hardware will automatically clear this bit on the following conditions: +1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). +2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). +3) Device Reset occurs (USBADR is reset to 0). +NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. +This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. +If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), +the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. + 24 + 1 + read-write + + + + + PERIODICLISTBASE + Frame List Base Address Register + UNION_154 + 0x154 + 32 + 0x00000000 + 0xFFFFF000 + + + BASEADR + BASEADR +Base Address (Low). +These bits correspond to memory address signals [31:12], respectively. +Only used by the host controller. + 12 + 20 + read-write + + + + + ASYNCLISTADDR + Next Asynch. Address Register + UNION_158 + 0x158 + 32 + 0x00000000 + 0xFFFFFFE0 + + + ASYBASE + ASYBASE +Link Pointer Low (LPL). +These bits correspond to memory address signals [31:5], respectively. This field may only reference a +Queue Head (QH). +Only used by the host controller. + 5 + 27 + read-write + + + + + ENDPTLISTADDR + Endpoint List Address Register + UNION_158 + 0x158 + 32 + 0x00000000 + 0xFFFFF800 + + + EPBASE + EPBASE +Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. +This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). + 11 + 21 + read-write + + + + + BURSTSIZE + Programmable Burst Size Register + 0x160 + 32 + 0x00000000 + 0x0000FFFF + + + TXPBURST + TXPBURST +Programmable TX Burst Size. +Default value is determined by TXBURST bits in n_HWTXBUF. +This register represents the maximum length of a the burst in 32-bit words while moving data from system +memory to the USB bus. + 8 + 8 + read-write + + + RXPBURST + RXPBURST +Programmable RX Burst Size. +Default value is determined by TXBURST bits in n_HWRXBUF. +This register represents the maximum length of a the burst in 32-bit words while moving data from the +USB bus to system memory. + 0 + 8 + read-write + + + + + TXFILLTUNING + TX FIFO Fill Tuning Register + 0x164 + 32 + 0x00000000 + 0x003F1F7F + + + TXFIFOTHRES + TXFIFOTHRES +FIFO Burst Threshold. (Read/Write) +This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. +The minimum value is 2 and this value should be a low as possible to maximize USB performance. +A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth +where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. +This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. + 16 + 6 + read-write + + + TXSCHHEALTH + TXSCHHEALTH +Scheduler Health Counter. (Read/Write To Clear) +Table continues on the next page +This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES +before running out of time to send the packet before the next Start-Of-Frame. +This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. +Writing to this register will clear the counter and this counter will max. at 31. + 8 + 5 + read-write + + + TXSCHOH + TXSCHOH +Scheduler Overhead. (Read/Write) [Default = 0] +This register adds an additional fixed offset to the schedule time estimator described above as Tff. +As an approximation, the value chosen for this register should limit the number of back-off events captured +in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. +Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. +The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. +The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. +Default value is '08h' for OTG controller core . + 0 + 7 + read-write + + + + + ENDPTNAK + Endpoint NAK Register + 0x178 + 32 + 0x00000000 + 0xFFFFFFFF + + + EPTN + EPTN +TX Endpoint NAK - R/WC. +Each TX endpoint has 1 bit in this field. The bit is set when the +device sends a NAK handshake on a received IN token for the corresponding endpoint. +Bit [N] - Endpoint #[N], N is 0-7 + 16 + 16 + read-write + + + EPRN + EPRN +RX Endpoint NAK - R/WC. +Each RX endpoint has 1 bit in this field. The bit is set when the +device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. +Bit [N] - Endpoint #[N], N is 0-7 + 0 + 16 + read-write + + + + + ENDPTNAKEN + Endpoint NAK Enable Register + 0x17c + 32 + 0x00000000 + 0xFFFFFFFF + + + EPTNE + EPTNE +TX Endpoint NAK Enable - R/W. +Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the +corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. +Bit [N] - Endpoint #[N], N is 0-7 + 16 + 16 + read-write + + + EPRNE + EPRNE +RX Endpoint NAK Enable - R/W. +Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the +corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. +Bit [N] - Endpoint #[N], N is 0-7 + 0 + 16 + read-write + + + + + PORTSC1 + Port Status & Control + 0x184 + 32 + 0x00000000 + 0x3DFF1FFF + + + STS + STS +Serial Transceiver Select +1 Serial Interface Engine is selected +0 Parallel Interface signals is selected +Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. +When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. + 29 + 1 + read-write + + + PTW + PTW +Parallel Transceiver Width +This bit has no effect if serial interface engine is used. +0 - Select the 8-bit UTMI interface [60MHz] +1 - Select the 16-bit UTMI interface [30MHz] + 28 + 1 + read-write + + + PSPD + PSPD +Port Speed - Read Only. +This register field indicates the speed at which the port is operating. +00 - Full Speed +01 - Low Speed +10 - High Speed +11 - Undefined + 26 + 2 + read-only + + + PFSC + PFSC +Port Force Full Speed Connect - Read/Write. Default = 0b. +When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp +sequence that allows the port to identify itself as High Speed. +0 - Normal operation +1 - Forced to full speed + 24 + 1 + read-write + + + PHCD + PHCD +PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. +When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY +clock. +NOTE: The PHY clock cannot be disabled if it is being used as the system clock. +In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD +Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend +will be cleared automatically when the host initials resume. Before forcing a resume from the device, the +device controller driver must clear this bit. +In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put +into suspend mode or when no downstream device is connected. Low power suspend is completely +under the control of software. +0 - Enable PHY clock +1 - Disable PHY clock + 23 + 1 + read-write + + + WKOC + WKOC +Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. +Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. +This field is zero if Port Power(PORTSC1) is zero. + 22 + 1 + read-write + + + WKDC + WKDC +Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables +the port to be sensitive to device disconnects as wake-up events. +This field is zero if Port Power(PORTSC1) is zero or in device mode. + 21 + 1 + read-write + + + WKCN + WKCN +Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. +Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. +This field is zero if Port Power(PORTSC1) is zero or in device mode. + 20 + 1 + read-write + + + PTC + PTC +Port Test Control - Read/Write. Default = 0000b. +Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. +The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. +Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. +Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. +NOTE: Low speed operations are not supported as a peripheral device. +Any other value than zero indicates that the port is operating in test mode. +Value Specific Test +0000 - TEST_MODE_DISABLE +0001 - J_STATE +0010 - K_STATE +0011 - SE0 (host) / NAK (device) +0100 - Packet +0101 - FORCE_ENABLE_HS +0110 - FORCE_ENABLE_FS +0111 - FORCE_ENABLE_LS +1000-1111 - Reserved + 16 + 4 + read-write + + + PP + PP +Port Power (PP)-Read/Write or Read Only. +The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: +PPC +PP Operation +0 +1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. +1 +1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). +When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. +When an over-current condition is detected on a powered port and PPC is a one, +the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). +This feature is implemented in all controller cores (PPC = 1). + 12 + 1 + read-write + + + LS + LS +Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal +lines. +In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because +the port controller state machine and the port routing manage the connection of LS and FS. +In device mode, the use of linestate by the device controller driver is not necessary. +The encoding of the bits are: +Bits [11:10] Meaning +00 - SE0 +01 - K-state +10 - J-state +11 - Undefined + 10 + 2 + read-only + + + HSP + HSP +High-Speed Port - Read Only. Default = 0b. +When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the +host/device connected to the port is not in a high-speed mode. +NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. + 9 + 1 + read-only + + + PR + PR +Port Reset - Read/Write or Read Only. Default = 0b. +In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. +When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. +This bit will automatically change to zero after the reset sequence is complete. +This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. +In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. + 8 + 1 + read-write + + + SUSP + SUSP +Suspend - Read/Write or Read Only. Default = 0b. +1=Port in suspend state. 0=Port not in suspend state. +In Host Mode: Read/Write. +Port Enabled Bit and Suspend bit of this register define the port states as follows: +Bits [Port Enabled, Suspend] Port State +0x Disable +10 Enable +11 Suspend +When in suspend state, downstream propagation of data is blocked on this port, except for port reset. +The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. +In the suspend state, the port is sensitive to resume detection. +Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. +The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. +If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: Read Only. +In device mode this bit is a read only status bit. + 7 + 1 + read-write + + + FPR + FPR +Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. +In Host Mode: +Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. +When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. +This bit will automatically change to zero after the resume sequence is complete. +This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. +Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. +The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. +Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. +This field is zero if Port Power(PORTSC1) is zero in host mode. +This bit is not-EHCI compatible. +In Device mode: +After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. +The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. +The bit will be cleared when the device returns to normal operation. + Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. + 6 + 1 + read-write + + + OCC + OCC +Over-current Change-R/WC. Default=0. +This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. + 5 + 1 + read-write + + + OCA + OCA +Over-current Active-Read Only. Default 0. +This bit will automatically transition from one to zero when the over current condition is removed. +0 - This port does not have an over-current condition. +1 - This port currently has an over-current condition + 4 + 1 + read-only + + + PEC + PEC +Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. +In Host Mode: +For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or +due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). +Software clears this by writing a one to it. +This field is zero if Port Power(PORTSC1) is zero. +In Device mode: +The device port is always enabled, so this bit is always '0b'. + 3 + 1 + read-write + + + PE + PE +Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. +In Host Mode: +Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. +Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. +Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. +When the port is disabled, (0b) downstream propagation of data is blocked except for reset. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: +The device port is always enabled, so this bit is always '1b'. + 2 + 1 + read-write + + + CSC + CSC +Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. +In Host Mode: +Indicates a change has occurred in the port's Current Connect Status. +The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. +For example, the insertion status changes twice before system software has cleared the changed condition, +hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: +This bit is undefined in device controller mode. + 1 + 1 + read-write + + + CCS + CCS +Current Connect Status-Read Only. +In Host Mode: +1=Device is present on port. 0=No device is present. Default = 0. +This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: +1=Attached. 0=Not Attached. Default=0. +A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. +A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. +It does not state the device being disconnected or Suspended. + 0 + 1 + read-write + + + + + OTGSC + On-The-Go Status & control Register + 0x1a4 + 32 + 0x00000000 + 0x07070723 + + + ASVIE + ASVIE +A Session Valid Interrupt Enable - Read/Write. + 26 + 1 + read-write + + + AVVIE + AVVIE +A VBus Valid Interrupt Enable - Read/Write. +Setting this bit enables the A VBus valid interrupt. + 25 + 1 + read-write + + + IDIE + IDIE +USB ID Interrupt Enable - Read/Write. +Setting this bit enables the USB ID interrupt. + 24 + 1 + read-write + + + ASVIS + ASVIS +A Session Valid Interrupt Status - Read/Write to Clear. +This bit is set when VBus has either risen above or fallen below the A session valid threshold. +Software must write a one to clear this bit. + 18 + 1 + read-write + + + AVVIS + AVVIS +A VBus Valid Interrupt Status - Read/Write to Clear. +This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. +Software must write a one to clear this bit. + 17 + 1 + read-write + + + IDIS + IDIS +USB ID Interrupt Status - Read/Write. +This bit is set when a change on the ID input has been detected. +Software must write a one to clear this bit. + 16 + 1 + read-write + + + ASV + ASV +A Session Valid - Read Only. +Indicates VBus is above the A session valid threshold. + 10 + 1 + read-only + + + AVV + AVV +A VBus Valid - Read Only. +Indicates VBus is above the A VBus valid threshold. + 9 + 1 + read-only + + + ID + ID +USB ID - Read Only. +0 = A device, 1 = B device + 8 + 1 + read-only + + + IDPU + IDPU +ID Pullup - Read/Write +This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input +will not be sampled. + 5 + 1 + read-write + + + VC + VC +VBUS Charge - Read/Write. +Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. + 1 + 1 + read-write + + + VD + VD +VBUS_Discharge - Read/Write. +Setting this bit causes VBus to discharge through a resistor. + 0 + 1 + read-write + + + + + USBMODE + USB Device Mode Register + 0x1a8 + 32 + 0x00000000 + 0x0000001F + + + SDIS + SDIS +Stream Disable Mode. (0 - Inactive [default]; 1 - Active) +Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. +This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. +Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. +Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems +where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. +NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for +the scheduler when using this feature. +NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. + 4 + 1 + read-write + + + SLOM + SLOM +Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . +0 - Setup Lockouts On (default); +1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. + 3 + 1 + read-write + + + ES + ES +Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the +host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected +by the value of this bit because they are based upon the 32-bit word. +Bit Meaning +0 - Little Endian [Default] +1 - Big Endian + 2 + 1 + read-write + + + CM + CM +Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only +implementations. For those designs that contain both host & device capability, the controller defaults to +an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ +device controllers, this register can only be written once after reset. If it is necessary to switch modes, +software must reset the controller by writing to the RESET bit in the USBCMD register before +reprogramming this register. +For OTG controller core, reset value is '00b'. +00 - Idle [Default for combination host/device] +01 - Reserved +10 - Device Controller [Default for device only controller] +11 - Host Controller [Default for host only controller] + 0 + 2 + read-write + + + + + ENDPTSETUPSTAT + Endpoint Setup Status Register + 0x1ac + 32 + 0x00000000 + 0x0000FFFF + + + ENDPTSETUPSTAT + ENDPTSETUPSTAT +Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. +Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. +The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. +This register is only used in device mode. + 0 + 16 + read-write + + + + + ENDPTPRIME + Endpoint Prime Register + 0x1b0 + 32 + 0x00000000 + 0xFFFFFFFF + + + PETB + PETB +Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a +buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. +Software should write a one to the corresponding bit when posting a new transfer descriptor to an +endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor +from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated +endpoint(s) is (are) successfully primed. +NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD +is retired, and the dQH is updated. +PETB[N] - Endpoint #N, N is in 0..7 + 16 + 16 + read-write + + + PERB + PERB +Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. +Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. +Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. +Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. +NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD +is retired, and the dQH is updated. +PERB[N] - Endpoint #N, N is in 0..7 + 0 + 16 + read-write + + + + + ENDPTFLUSH + Endpoint Flush Register + 0x1b4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FETB + FETB +Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. +If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. +Hardware clears this register after the endpoint flush operation is successful. +FETB[N] - Endpoint #N, N is in 0..7 + 16 + 16 + read-write + + + FERB + FERB +Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. + If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. +Hardware clears this register after the endpoint flush operation is successful. +FERB[N] - Endpoint #N, N is in 0..7 + 0 + 16 + read-write + + + + + ENDPTSTAT + Endpoint Status Register + 0x1b8 + 32 + 0x00000000 + 0xFFFFFFFF + + + ETBR + ETBR +Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. +This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. +There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. +This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. +Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. +NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. +ETBR[N] - Endpoint #N, N is in 0..7 + 16 + 16 + read-only + + + ERBR + ERBR +Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective +endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a +corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the +ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB +traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the +USB DMA system, or through the ENDPTFLUSH register. +NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations +when a dTD is retired, and the dQH is updated. +ERBR[N] - Endpoint #N, N is in 0..7 + 0 + 16 + read-only + + + + + ENDPTCOMPLETE + Endpoint Complete Register + 0x1bc + 32 + 0x00000000 + 0xFFFFFFFF + + + ETCE + ETCE +Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. +If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. +ETCE[N] - Endpoint #N, N is in 0..7 + 16 + 16 + read-write + + + ERCE + ERCE +Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred +and software should read the corresponding endpoint queue to determine the transfer status. If the +corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the +USBINT . Writing one clears the corresponding bit in this register. +ERCE[N] - Endpoint #N, N is in 0..7 + 0 + 16 + read-write + + + + + 16 + 0x4 + ENDPTCTRL0,ENDPTCTRL1,ENDPTCTRL2,ENDPTCTRL3,ENDPTCTRL4,ENDPTCTRL5,ENDPTCTRL6,ENDPTCTRL7,ENDPTCTRL8,ENDPTCTRL9,ENDPTCTRL10,ENDPTCTRL11,ENDPTCTRL12,ENDPTCTRL13,ENDPTCTRL14,ENDPTCTRL15 + ENDPTCTRL[%s] + no description available + 0x1c0 + 32 + 0x00000000 + 0x00CD00CD + + + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 + read-write + + + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 + 1 + write-only + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 + read-write + + + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured +as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 + 1 + read-write + + + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 + 1 + read-write + + + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 + 1 + write-only + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 + read-write + + + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 + 1 + read-write + + + + + OTG_CTRL0 + No description available + 0x200 + 32 + 0x00000000 + 0x020B3F90 + + + OTG_WKDPDMCHG_EN + No description available + 25 + 1 + read-write + + + AUTORESUME_EN + No description available + 19 + 1 + read-write + + + OTG_VBUS_WAKEUP_EN + No description available + 17 + 1 + read-write + + + OTG_ID_WAKEUP_EN + No description available + 16 + 1 + read-write + + + OTG_VBUS_SOURCE_SEL + No description available + 13 + 1 + read-write + + + OTG_UTMI_SUSPENDM_SW + default 0 for naneng usbphy + 12 + 1 + read-write + + + OTG_UTMI_RESET_SW + default 1 for naneng usbphy + 11 + 1 + read-write + + + OTG_WAKEUP_INT_ENABLE + No description available + 10 + 1 + read-write + + + OTG_POWER_MASK + No description available + 9 + 1 + read-write + + + OTG_OVER_CUR_POL + No description available + 8 + 1 + read-write + + + OTG_OVER_CUR_DIS + No description available + 7 + 1 + read-write + + + SER_MODE_SUSPEND_EN + for naneng usbphy, only switch to serial mode when suspend + 4 + 1 + read-write + + + + + PHY_CTRL0 + No description available + 0x210 + 32 + 0x00000000 + 0x02007007 + + + GPIO_ID_SEL_N + No description available + 25 + 1 + read-write + + + ID_DIG_OVERRIDE + No description available + 14 + 1 + read-write + + + SESS_VALID_OVERRIDE + No description available + 13 + 1 + read-write + + + VBUS_VALID_OVERRIDE + No description available + 12 + 1 + read-write + + + ID_DIG_OVERRIDE_EN + No description available + 2 + 1 + read-write + + + SESS_VALID_OVERRIDE_EN + No description available + 1 + 1 + read-write + + + VBUS_VALID_OVERRIDE_EN + No description available + 0 + 1 + read-write + + + + + PHY_CTRL1 + No description available + 0x214 + 32 + 0x00000000 + 0x00100002 + + + UTMI_CFG_RST_N + No description available + 20 + 1 + read-write + + + UTMI_OTG_SUSPENDM + OTG suspend, not utmi_suspendm + 1 + 1 + read-write + + + + + TOP_STATUS + No description available + 0x220 + 32 + 0x00000000 + 0x80000000 + + + WAKEUP_INT_STATUS + No description available + 31 + 1 + read-write + + + + + PHY_STATUS + No description available + 0x224 + 32 + 0x00000000 + 0x800000F5 + + + UTMI_CLK_VALID + No description available + 31 + 1 + read-write + + + LINE_STATE + No description available + 6 + 2 + read-write + + + HOST_DISCONNECT + No description available + 5 + 1 + read-write + + + ID_DIG + No description available + 4 + 1 + read-write + + + UTMI_SESS_VALID + No description available + 2 + 1 + read-write + + + VBUS_VALID + No description available + 0 + 1 + read-write + + + + + + + SDXC0 + SDXC0 + SDXC + 0xf1130000 + + 0x0 + 0x3008 + registers + + + + SDMASA + No description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + BLOCKCNT_SDMASA + 32-bit Block Count (SDMA System Address) +- SDMA System Address (Host Version 4 Enable = 0): This register contains the system memory address for an SDMA transfer in the 32-bit addressing mode. +When the Host Controller stops an SDMA transfer, this register points to the system address of the next contiguous data position. +It can be accessed only if no transaction is executing. Reading this register during data transfers may +return an invalid value. +- 32-bit Block Count (Host Version 4 Enable = 1): From the Host Controller Version 4.10 specification, this register is redefined as 32-bit Block Count. +The Host Controller decrements the block count of this register for every block transfer and the data transfer stops when the count reaches zero. +This register must be accessed when no transaction is executing. Reading this register during data transfers may return invalid value. +Following are the values for BLOCKCNT_SDMASA: +- 0xFFFF_FFFF: 4G - 1 Block +- +- 0x0000_0002: 2 Blocks +- 0x0000_0001: 1 Block +- 0x0000_0000: Stop Count +Note: +- For Host Version 4 Enable = 0, the Host driver does not program the system address in this register while operating in ADMA mode. +The system address must be programmed in the ADMA System Address register. +- For Host Version 4 Enable = 0, the Host driver programs a non-zero 32-bit block count value in this register when Auto CMD23 is enabled for non-DMA and ADMA modes. +Auto CMD23 cannot be used with SDMA. +- This register must be programmed with a non-zero value for data transfer if the 32-bit Block count register is used instead of the 16-bit Block count register. + 0 + 32 + read-write + + + + + BLK_ATTR + No description available + 0x4 + 32 + 0x00020210 + 0xFFFF7FFF + + + BLOCK_CNT + 16-bit Block Count +- If the Host Version 4 Enable bit is set 0 or the 16-bit Block Count register is set to non-zero, the 16-bit Block Count register is selected. +- If the Host Version 4 Enable bit is set 1 and the 16-bit Block Count register is set to zero, the 32-bit Block Count register is selected. +Following are the values for BLOCK_CNT: +- 0x0: Stop Count +- 0x1: 1 Block +- 0x2: 2 Blocks +- . +- 0xFFFF: 65535 Blocks +Note: For Host Version 4 Enable = 0, this register must be set to 0000h before programming the 32-bit block count register when Auto CMD23 is enabled for non-DMA and ADMA modes. + 16 + 16 + read-write + + + SDMA_BUF_BDARY + SDMA Buffer Boundary +These bits specify the size of contiguous buffer in system memory. +The SDMA transfer waits at every boundary specified by these fields and the Host Controller generates the DMA interrupt to request the Host Driver to update the SDMA System Address register. +Values: +- 0x0 (BYTES_4K): 4K bytes SDMA Buffer Boundary +- 0x1 (BYTES_8K): 8K bytes SDMA Buffer Boundary +- 0x2 (BYTES_16K): 16K bytes SDMA Buffer Boundary +- 0x3 (BYTES_32K): 32K bytes SDMA Buffer Boundary +- 0x4 (BYTES_64K): 64K bytes SDMA Buffer Boundary +- 0x5 (BYTES_128K): 128K bytes SDMA Buffer Boundary +- 0x6 (BYTES_256K): 256K bytes SDMA Buffer Boundary +- 0x7 (BYTES_512K): 512K bytes SDMA Buffer Boundary + 12 + 3 + read-write + + + XFER_BLOCK_SIZE + Transfer Block Size +These bits specify the block size of data transfers. In case of memory, it is set to 512 bytes. It can be accessed only if no transaction is executing. +Read operations during transfers may return an invalid value, and write operations are ignored. Following are the values for XFER_BLOCK_SIZE: +- 0x1: 1 byte +- 0x2: 2 bytes +- 0x3: 3 bytes +- . +- 0x1FF: 511 byte +- 0x200: 512 byt es +- . +- 0x800: 2048 bytes +Note: This register must be programmed with a non-zero value for data transfer. + 0 + 12 + read-write + + + + + CMD_ARG + No description available + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + ARGUMNET + Command Argument +These bits specify the SD/eMMC command argument that is specified in bits 39-8 of the Command format. + 0 + 32 + read-write + + + + + CMD_XFER + No description available + 0xc + 32 + 0x00000000 + 0x3FFF01FF + + + CMD_INDEX + Command Index +These bits are set to the command number that is specified in bits 45-40 of the Command Format. + 24 + 6 + read-write + + + CMD_TYPE + Command Type +These bits indicate the command type. +Note: While issuing Abort CMD using CMD12/CMD52 or reset CMD using CMD0/CMD52, CMD_TYPE field shall be set to 0x3. +Values: +0x3 (ABORT_CMD): Abort +0x2 (RESUME_CMD): Resume +0x1 (SUSPEND_CMD): Suspend +0x0 (NORMAL_CMD): Normal + 22 + 2 + read-write + + + DATA_PRESENT_SEL + Data Present Select +This bit is set to 1 to indicate that data is present and that the data is transferred using the DAT line. This bit is set to 0 in the following instances: +Command using the CMD line +Command with no data transfer but using busy signal on the DAT[0] line +Resume Command +Values: +0x0 (NO_DATA): No Data Present +0x1 (DATA): Data Present + 21 + 1 + read-write + + + CMD_IDX_CHK_ENABLE + Command Index Check Enable +This bit enables the Host Controller to check the index field in the response to verify if it has the same value as the command index. +If the value is not the same, it is reported as a Command Index error. +Note: +Index Check enable must be set to 0 for the command with no response, R2 response, R3 response and R4 response. +For the tuning command, this bit must always be set to enable the index check. +Values: +0x0 (DISABLED): Disable +0x1 (ENABLED): Enable + 20 + 1 + read-write + + + CMD_CRC_CHK_ENABLE + Command CRC Check Enable +This bit enables the Host Controller to check the CRC field in the response. If an error is detected, it is reported as a Command CRC error. +Note: +CRC Check enable must be set to 0 for the command with no response, R3 response, and R4 response. +For the tuning command, this bit must always be set to 1 to enable the CRC check. +Values: +0x0 (DISABLED): Disable +0x1 (ENABLED): Enable + 19 + 1 + read-write + + + SUB_CMD_FLAG + Sub Command Flag +This bit distinguishes between a main command and a sub command. +Values: +0x0 (MAIN): Main Command +0x1 (SUB): Sub Command + 18 + 1 + read-write + + + RESP_TYPE_SELECT + Response Type Select +This bit indicates the type of response expected from the card. +Values: +0x0 (NO_RESP): No Response +0x1 (RESP_LEN_136): Response Length 136 +0x2 (RESP_LEN_48): Response Length 48 +0x3 (RESP_LEN_48B): Response Length 48; Check Busy after response + 16 + 2 + read-write + + + RESP_INT_DISABLE + Response Interrupt Disable +The Host Controller supports response check function to avoid overhead of response error check by the Host driver. +Response types of only R1 and R5 can be checked by the Controller. +If Host Driver checks the response error, set this bit to 0 and wait for Command Complete Interrupt and then check the response register. +If the Host Controller checks the response error, set this bit to 1 and set the Response Error Check Enable bit to 1. +The Command Complete Interrupt is disabled by this bit regardless of the Command Complete Signal Enable. +Note: During tuning (when the Execute Tuning bit in the Host Control2 register is set), the Command Complete Interrupt is not generated irrespective of the Response Interrupt Disable setting. +Values: +- 0x0 (ENABLED): Response Interrupt is enabled +- 0x1 (DISABLED): Response Interrupt is disabled + 8 + 1 + read-write + + + RESP_ERR_CHK_ENABLE + Response Error Check Enable +The Host Controller supports response check function to avoid overhead of response error check by Host driver. Response types of only R1 and R5 can be checked by the Controller. +If the Host Controller checks the response error, set this bit to 1 and set Response Interrupt Disable to 1. If an error is detected, the Response Error interrupt is generated in the Error Interrupt Status register. +Note: +- Response error check must not be enabled for any response type other than R1 and R5. +- Response check must not be enabled for the tuning command. +Values: +- 0x0 (DISABLED): Response Error Check is disabled +- 0x1 (ENABLED): Response Error Check is enabled + 7 + 1 + read-write + + + RESP_TYPE + Response Type R1/R5 +This bit selects either R1 or R5 as a response type when the Response Error Check is selected. +Error statuses checked in R1: +OUT_OF_RANGE +ADDRESS_ERROR +BLOCK_LEN_ERROR +WP_VIOLATION +CARD_IS_LOCKED +COM_CRC_ERROR +CARD_ECC_FAILED +CC_ERROR +ERROR +Response Flags checked in R5: +COM_CRC_ERROR +ERROR +FUNCTION_NUMBER +OUT_OF_RANGE +Values: +0x0 (RESP_R1): R1 (Memory) +0x1 (RESP_R5): R5 (SDIO) + 6 + 1 + read-write + + + MULTI_BLK_SEL + Multi/Single Block Select +This bit is set when issuing multiple-block transfer commands using the DAT line. If this bit is set to 0, it is not necessary to set the Block Count register. +Values: +0x0 (SINGLE): Single Block +0x1 (MULTI): Multiple Block + 5 + 1 + read-write + + + DATA_XFER_DIR + Data Transfer Direction Select +This bit defines the direction of DAT line data transfers. +This bit is set to 1 by the Host Driver to transfer data from the SD/eMMC card to the Host Controller and it is set to 0 for all other commands. +Values: +0x1 (READ): Read (Card to Host) +0x0 (WRITE): Write (Host to Card) + 4 + 1 + read-write + + + AUTO_CMD_ENABLE + Auto Command Enable +This field determines use of Auto Command functions. +Note: In SDIO, this field must be set as 00b (Auto Command Disabled). +Values: +0x0 (AUTO_CMD_DISABLED): Auto Command Disabled +0x1 (AUTO_CMD12_ENABLED): Auto CMD12 Enable +0x2 (AUTO_CMD23_ENABLED): Auto CMD23 Enable +0x3 (AUTO_CMD_AUTO_SEL): Auto CMD Auto Sel + 2 + 2 + read-write + + + BLOCK_COUNT_ENABLE + Block Count Enable +This bit is used to enable the Block Count register, which is relevant for multiple block transfers. +If this bit is set to 0, the Block Count register is disabled, which is useful in executing an infinite transfer. +The Host Driver must set this bit to 0 when ADMA is used. +Values: +0x1 (ENABLED): Enable +0x0 (DISABLED): Disable + 1 + 1 + read-write + + + DMA_ENABLE + DMA Enable +This bit enables the DMA functionality. If this bit is set to 1, a DMA operation begins when the Host Driver writes to the Command register. +You can select one of the DMA modes by using DMA Select in the Host Control 1 register. +Values: +0x1 (ENABLED): DMA Data transfer +0x0 (DISABLED): No data transfer or Non-DMA data transfer + 0 + 1 + read-write + + + + + 4 + 0x4 + RESP01,RESP23,RESP45,RESP67 + RESP[%s] + no description available + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESP01 + Command Response +These bits reflect 39-8 bits of SD/eMMC Response Field. +Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP[RESP67] register. + 0 + 32 + read-only + + + + + BUF_DATA + No description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + BUF_DATA + Buffer Data +These bits enable access to the Host Controller packet buffer. + 0 + 32 + read-write + + + + + PSTATE + No description available + 0x24 + 32 + 0x00000000 + 0x19FF0FFF + + + SUB_CMD_STAT + Sub Command Status +This bit is used to distinguish between a main command and a sub command status. +Values: +0x0 (FALSE): Main Command Status +0x1 (TRUE): Sub Command Status + 28 + 1 + read-only + + + CMD_ISSUE_ERR + Command Not Issued by Error +This bit is set if a command cannot be issued after setting the command register due to an error except the Auto CMD12 error. +Values: +0x0 (FALSE): No error for issuing a command +0x1 (TRUE): Command cannot be issued + 27 + 1 + read-only + + + CMD_LINE_LVL + Command-Line Signal Level +This bit is used to check the CMD line level to recover from errors and for debugging. These bits reflect the value of the sd_cmd_in signal. + 24 + 1 + read-only + + + DAT_3_0 + DAT[3:0] Line Signal Level +This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (lower nibble) signal. + 20 + 4 + read-only + + + WR_PROTECT_SW_LVL + Write Protect Switch Pin Level +This bit is supported only for memory and combo cards. This bit reflects the synchronized value of the card_write_prot signal. +Values: +0x0 (FALSE): Write protected +0x1 (TRUE): Write enabled + 19 + 1 + read-only + + + CARD_DETECT_PIN_LEVEL + Card Detect Pin Level +This bit reflects the inverse synchronized value of the card_detect_n signal. +Values: +0x0 (FALSE): No card present +0x1 (TRUE): Card Present + 18 + 1 + read-only + + + CARD_STABLE + Card Stable +This bit indicates the stability of the Card Detect Pin Level. A card is not detected if this bit is set to 1 and the value of the CARD_INSERTED bit is 0. +Values: +0x0 (FALSE): Reset or Debouncing +0x1 (TRUE): No Card or Inserted + 17 + 1 + read-only + + + CARD_INSERTED + Card Inserted +This bit indicates whether a card has been inserted. The Host Controller debounces this signal so that Host Driver need not wait for it to stabilize. +Values: +0x0 (FALSE): Reset, Debouncing, or No card +0x1 (TRUE): Card Inserted + 16 + 1 + read-only + + + BUF_RD_ENABLE + Buffer Read Enable +This bit is used for non-DMA transfers. This bit is set if valid data exists in the Host buffer. +Values: +0x0 (DISABLED): Read disable +0x1 (ENABLED): Read enable + 11 + 1 + read-only + + + BUF_WR_ENABLE + Buffer Write Enable +This bit is used for non-DMA transfers. This bit is set if space is available for writing data. +Values: +0x0 (DISABLED): Write disable +0x1 (ENABLED): Write enable + 10 + 1 + read-only + + + RD_XFER_ACTIVE + Read Transfer Active +This bit indicates whether a read transfer is active for SD/eMMC mode. +Values: +0x0 (INACTIVE): No valid data +0x1 (ACTIVE): Transferring data + 9 + 1 + read-only + + + WR_XFER_ACTIVE + Write Transfer Active +This status indicates whether a write transfer is active for SD/eMMC mode. +Values: +0x0 (INACTIVE): No valid data +0x1 (ACTIVE): Transferring data + 8 + 1 + read-only + + + DAT_7_4 + DAT[7:4] Line Signal Level +This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (upper nibble) signal. + 4 + 4 + read-only + + + RE_TUNE_REQ + Re-Tuning Request +SDXC does not generate retuning request. The software must maintain the Retuning timer. + 3 + 1 + read-only + + + DAT_LINE_ACTIVE + DAT Line Active ( +This bit indicates whether one of the DAT lines on the SD/eMMC bus is in use. +In the case of read transactions, this bit indicates whether a read transfer is executing on the SD/eMMC bus. +In the case of write transactions, this bit indicates whether a write transfer is executing on the SD/eMMC bus. +For a command with busy, this status indicates whether the command executing busy is executing on an SD or eMMC bus. +Values: +0x0 (INACTIVE): DAT Line Inactive +0x1 (ACTIVE): DAT Line Active + 2 + 1 + read-only + + + DAT_INHIBIT + Command Inhibit (DAT) +This bit is generated if either DAT line active or Read transfer active is set to 1. +If this bit is set to 0, it indicates that the Host Controller can issue subsequent SD/eMMC commands. +Values: +0x0 (READY): Can issue command which used DAT line +0x1 (NOT_READY): Cannot issue command which used DAT line + 1 + 1 + read-only + + + CMD_INHIBIT + Command Inhibit (CMD) +This bit indicates the following : +If this bit is set to 0, it indicates that the CMD line is not in use and the Host controller can issue an SD/eMMC command using the CMD line. +This bit is set when the command register is written. This bit is cleared when the command response is received. +This bit is not cleared by the response of auto CMD12/23 but cleared by the response of read/write command. +Values: +0x0 (READY): Host Controller is ready to issue a command +0x1 (NOT_READY): Host Controller is not ready to issue a command + 0 + 1 + read-only + + + + + PROT_CTRL + No description available + 0x28 + 32 + 0x00000000 + 0x070F0F3E + + + CARD_REMOVAL + Wakeup Event Enable on SD Card Removal +This bit enables wakeup event through Card Removal assertion in the Normal Interrupt Status register. +For the SDIO card, Wake Up Support (FN_WUS) in the Card Information Structure (CIS) register does not affect this bit. +Values: +0x0 (DISABLED): Disable +0x1 (ENABLED): Enable + 26 + 1 + read-write + + + CARD_INSERT + Wakeup Event Enable on SD Card Insertion +This bit enables wakeup event through Card Insertion assertion in the Normal Interrupt Status register. +FN_WUS (Wake Up Support) in CIS does not affect this bit. +Values: +0x0 (DISABLED): Disable +0x1 (ENABLED): Enable + 25 + 1 + read-write + + + CARD_INT + Wakeup Event Enable on Card Interrupt +This bit enables wakeup event through a Card Interrupt assertion in the Normal Interrupt Status register. +This bit can be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1. +Values: +0x0 (DISABLED): Disable +0x1 (ENABLED): Enable + 24 + 1 + read-write + + + INT_AT_BGAP + Interrupt At Block Gap +This bit is valid only in the 4-bit mode of an SDIO card and is used to select a sample point in the interrupt cycle. +Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. +Values: +0x0 (DISABLE): Disabled +0x1 (ENABLE): Enabled + 19 + 1 + read-write + + + RD_WAIT_CTRL + Read Wait Control +This bit is used to enable the read wait protocol to stop read data using DAT[2] line if the card supports read wait. +Otherwise, the Host Controller has to stop the card clock to hold the read data. In UHS-II mode, Read Wait is disabled. +Values: +0x0 (DISABLE): Disable Read Wait Control +0x1 (ENABLE): Enable Read Wait Control + 18 + 1 + read-write + + + CONTINUE_REQ + Continue Request +This bit is used to restart the transaction, which was stopped using the Stop At Block Gap Request. +The Host Controller automatically clears this bit when the transaction restarts. +If stop at block gap request is set to 1, any write to this bit is ignored. +Values: +0x0 (NO_AFFECT): No Affect +0x1 (RESTART): Restart + 17 + 1 + read-write + + + STOP_BG_REQ + Stop At Block Gap Request +This bit is used to stop executing read and write transactions at the next block gap for non-DMA, SDMA, and ADMA transfers. +Values: +0x0 (XFER): Transfer +0x1 (STOP): Stop + 16 + 1 + read-write + + + SD_BUS_VOL_VDD1 + SD Bus Voltage Select for VDD1/eMMC Bus Voltage Select for VDD +These bits enable the Host Driver to select the voltage level for an SD/eMMC card. +Before setting this register, the Host Driver checks the Voltage Support bits in the Capabilities register. +If an unsupported voltage is selected, the Host System does not supply the SD Bus voltage. +The value set in this field is available on the SDXC output signal (sd_vdd1_sel), which is used by the voltage switching circuitry. +SD Bus Voltage Select options: +0x7 : 3.3V(Typical) +0x6 : 3.0V(Typical) +0x5 : 1.8V(Typical) for Embedded +0x4 : 0x0 - Reserved +eMMC Bus Voltage Select options: +0x7 : 3.3V(Typical) +0x6 : 1.8V(Typical) +0x5 : 1.2V(Typical) +0x4 : 0x0 - Reserved +Values: +0x7 (V_3_3): 3.3V (Typ.) +0x6 (V_3_0): 3.0V (Typ.) +0x5 (V_1_8): 1.8V (Typ.) for Embedded +0x4 (RSVD4): Reserved +0x3 (RSVD3): Reserved +0x2 (RSVD2): Reserved +0x1 (RSVD1): Reserved +0x0 (RSVD0): Reserved + 9 + 3 + read-write + + + SD_BUS_PWR_VDD1 + SD Bus Power for VDD1 +This bit enables VDD1 power of the card. +This setting is available on the sd_vdd1_on output of SDXC so that it can be used to control the VDD1 power supply of the card. +Before setting this bit, the SD Host Driver sets the SD Bus Voltage Select bit. If the Host Controller detects a No Card state, this bit is cleared. +In SD mode, if this bit is cleared, the Host Controller stops the SD Clock by clearing the SD_CLK_EN bit in the SYS_CTRL register. +Values: +0x0 (OFF): Power off +0x1 (ON): Power on + 8 + 1 + read-write + + + EXT_DAT_XFER + Extended Data Transfer Width +This bit controls 8-bit bus width mode of embedded device. +Values: +0x1 (EIGHT_BIT): 8-bit Bus Width +0x0 (DEFAULT): Bus Width is selected by the Data Transfer Width + 5 + 1 + read-write + + + DMA_SEL + DMA Select +This field is used to select the DMA type. +When Host Version 4 Enable is 1 in Host Control 2 register: +0x0 : SDMA is selected +0x1 : Reserved +0x2 : ADMA2 is selected +0x3 : ADMA2 or ADMA3 is selected +When Host Version 4 Enable is 0 in Host Control 2 register: +0x0 : SDMA is selected +0x1 : Reserved +0x2 : 32-bit Address ADMA2 is selected +0x3 : 64-bit Address ADMA2 is selected +Values: +0x0 (SDMA): SDMA is selected +0x1 (RSVD_BIT): Reserved +0x2 (ADMA2): ADMA2 is selected +0x3 (ADMA2_3): ADMA2 or ADMA3 is selected + 3 + 2 + read-write + + + HIGH_SPEED_EN + High Speed Enable +this bit is used to determine the selection of preset value for High Speed mode. +Before setting this bit, the Host Driver checks the High Speed Support in the Capabilities register. +Note: SDXC always outputs the sd_cmd_out and sd_dat_out lines at the rising edge of cclk_tx clock irrespective of this bit. +Values: +0x1 (HIGH_SPEED): High Speed mode +0x0 (NORMAL_SPEED): Normal Speed mode + 2 + 1 + read-write + + + DAT_XFER_WIDTH + Data Transfer Width +For SD/eMMC mode,this bit selects the data transfer width of the Host Controller. +The Host Driver sets it to match the data width of the SD/eMMC card. In UHS-II mode, this bit is irrelevant. +Values: +0x1 (FOUR_BIT): 4-bit mode +0x0 (ONE_BIT): 1-bit mode + 1 + 1 + read-write + + + + + SYS_CTRL + No description available + 0x2c + 32 + 0x00000000 + 0x070FFFEF + + + SW_RST_DAT + Software Reset For DAT line +This bit is used in SD/eMMC mode and it resets only a part of the data circuit and the DMA circuit is also reset. +The following registers and bits are cleared by this bit: +Buffer Data Port register +-Buffer is cleared and initialized. +Present state register +-Buffer Read Enable +-Buffer Write Enable +-Read Transfer Active +-Write Transfer Active +-DAT Line Active +-Command Inhibit (DAT) +Block Gap Control register +-Continue Request +-Stop At Block Gap Request +Normal Interrupt status register +-Buffer Read Ready +-Buffer Write Ready +-DMA Interrupt +-Block Gap Event +-Transfer Complete +In UHS-II mode, this bit shall be set to 0 +Values: +0x0 (FALSE): Work +0x1 (TRUE): Reset + 26 + 1 + read-write + + + SW_RST_CMD + Software Reset For CMD line +This bit resets only a part of the command circuit to be able to issue a command. +It bit is also used to initialize a UHS-II command circuit. +This reset is effective only for a command issuing circuit (including response error statuses related to Command Inhibit (CMD) control) and does not affect the data transfer circuit. +Host Controller can continue data transfer even after this reset is executed while handling subcommand-response errors. +The following registers and bits are cleared by this bit: +Present State register : Command Inhibit (CMD) bit +Normal Interrupt Status register : Command Complete bit +Error Interrupt Status : Response error statuses related to Command Inhibit (CMD) bit +Values: +0x0 (FALSE): Work +0x1 (TRUE): Reset + 25 + 1 + read-write + + + SW_RST_ALL + Software Reset For All +This reset affects the entire Host Controller except for the card detection circuit. +During its initialization, the Host Driver sets this bit to 1 to reset the Host Controller. +All registers are reset except the capabilities register. +If this bit is set to 1, the Host Driver must issue reset command and reinitialize the card. +Values: +0x0 (FALSE): Work +0x1 (TRUE): Reset + 24 + 1 + read-write + + + TOUT_CNT + Data Timeout Counter Value. +This value determines the interval by which DAT line timeouts are detected. +The Timeout clock frequency is generated by dividing the base clock TMCLK value by this value. +When setting this register, prevent inadvertent timeout events by clearing the Data Timeout Error Status Enable (in the Error Interrupt Status Enable register). +The values for these bits are: +0xF : Reserved +0xE : TMCLK x 2^27 +......... +0x1 : TMCLK x 2^14 +0x0 : TMCLK x 2^13 +Note: During a boot operating in an eMMC mode, an application must configure the boot data timeout value (approximately 1 sec) in this bit. + 16 + 4 + read-write + + + FREQ_SEL + SDCLK/RCLK Frequency Select +These bits are used to select the frequency of the SDCLK signal. +These bits depend on setting of Preset Value Enable in the Host Control 2 register. +If Preset Value Enable = 0, these bits are set by the Host Driver. +If Preset Value Enable = 1, these bits are automatically set to a value specified in one of the Preset Value register. +The value is reflected on the lower 8-bit of the card_clk_freq_selsignal. +10-bit Divided Clock Mode: +0x3FF : 1/2046 Divided clock +.......... +N : 1/2N Divided Clock +.......... +0x002 : 1/4 Divided Clock +0x001 : 1/2 Divided Clock +0x000 : Base clock (10MHz - 255 MHz) +Programmable Clock Mode : Enables the Host System to select a fine grain SD clock frequency: +0x3FF : Base clock * M /1024 +.......... +N-1 : Base clock * M /N +.......... +0x002 : Base clock * M /3 +0x001 : Base clock * M /2 +0x000 : Base clock * M + 8 + 8 + read-write + + + UPPER_FREQ_SEL + These bits specify the upper 2 bits of 10-bit SDCLK/RCLK Frequency Select control. +The value is reflected on the upper 2 bits of the card_clk_freq_sel signal. + 6 + 2 + read-write + + + CLK_GEN_SELECT + Clock Generator Select +This bit is used to select the clock generator mode in SDCLK/RCLK Frequency Select. +If Preset Value Enable = 0, this bit is set by the Host Driver. +If Preset Value Enable = 1, this bit is automatically set to a value specified in one of the Preset Value registers. +The value is reflected on the card_clk_gen_sel signal. +Values: +0x0 (FALSE): Divided Clock Mode +0x1 (TRUE): Programmable Clock Mode + 5 + 1 + read-write + + + PLL_ENABLE + PLL Enable +This bit is used to activate the PLL (applicable when Host Version 4 Enable = 1). +When Host Version 4 Enable = 0, INTERNAL_CLK_EN bit may be used to activate PLL. The value is reflected on the card_clk_en signal. +Note: If this bit is not used to to active the PLL when Host Version 4 Enable = 1, it is recommended to set this bit to '1' . +Values: +0x0 (FALSE): PLL is in low power mode +0x1 (TRUE): PLL is enabled + 3 + 1 + read-write + + + SD_CLK_EN + SD/eMMC Clock Enable +This bit stops the SDCLK or RCLK when set to 0. +The SDCLK/RCLK Frequency Select bit can be changed when this bit is set to 0. +The value is reflected on the clk2card_on pin. +Values: +0x0 (FALSE): Disable providing SDCLK/RCLK +0x1 (TRUE): Enable providing SDCLK/RCLK + 2 + 1 + read-write + + + INTERNAL_CLK_STABLE + Internal Clock Stable +This bit enables the Host Driver to check the clock stability twice after the Internal Clock Enable bit is set and after the PLL Enable bit is set. +This bit reflects the synchronized value of the intclk_stable signal after the Internal Clock Enable bit is set to 1, +and also reflects the synchronized value of the card_clk_stable signal after the PLL Enable bit is set to 1. +Values: +0x0 (FALSE): Not Ready +0x1 (TRUE): Ready + 1 + 1 + read-write + + + INTERNAL_CLK_EN + Internal Clock Enable +This bit is set to 0 when the Host Driver is not using the Host Controller or the Host Controller awaits a wakeup interrupt. +The Host Controller must stop its internal clock to enter a very low power state. +However, registers can still be read and written to. The value is reflected on the intclk_en signal. +Note: If this bit is not used to control the internal clock (base clock and master clock), it is recommended to set this bit to '1' . +Values: +0x0 (FALSE): Stop +0x1 (TRUE): Oscillate + 0 + 1 + read-write + + + + + INT_STAT + No description available + 0x30 + 32 + 0x00000000 + 0x1FFFF1FF + + + BOOT_ACK_ERR + Boot Acknowledgment Error +This bit is set when there is a timeout for boot acknowledgement or when detecting boot ack status having a value other than 010. This is applicable only when boot acknowledgement is expected in eMMC mode. +In SD/UHS-II mode, this bit is irrelevant. + 28 + 1 + read-write + + + RESP_ERR + Response Error +Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. +If Response Error Check Enable is set to 1 in the Transfer Mode register, Host Controller Checks R1 or R5 response. If an error is detected in a response, this bit is set to 1.This is applicable in SD/eMMC mode. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 27 + 1 + read-write + + + TUNING_ERR + Tuning Error +This bit is set when an unrecoverable error is detected in a tuning circuit except during the tuning procedure +(occurrence of an error during tuning procedure is indicated by Sampling Clock Select in the Host Control 2 register). +By detecting Tuning Error, Host Driver needs to abort a command executing and perform tuning. +To reset tuning circuit, Sampling Clock Select is set to 0 before executing tuning procedure. +The Tuning Error is higher priority than the other error interrupts generated during data transfer. +By detecting Tuning Error, the Host Driver must discard data transferred by a current read/write command and retry data transfer after the Host Controller retrieved from the tuning circuit error. +This is applicable in SD/eMMC mode. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 26 + 1 + read-write + + + ADMA_ERR + ADMA Error +This bit is set when the Host Controller detects error during ADMA-based data transfer. The error could be due to following reasons: +Error response received from System bus (Master I/F) +ADMA3,ADMA2 Descriptors invalid +CQE Task or Transfer descriptors invalid +When the error occurs, the state of the ADMA is saved in the ADMA Error Status register. +In eMMC CQE mode: +The Host Controller generates this Interrupt when it detects an invalid descriptor data (Valid=0) at the ST_FDS state. +ADMA Error State in the ADMA Error Status indicates that an error has occurred in ST_FDS state. +The Host Driver may find that Valid bit is not set at the error descriptor. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 25 + 1 + read-write + + + AUTO_CMD_ERR + Auto CMD Error +This error status is used by Auto CMD12 and Auto CMD23 in SD/eMMC mode. +This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1. +D07 is effective in case of Auto CMD12. Auto CMD Error Status register is valid while this bit is set to 1 and may be cleared by clearing of this bit. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 24 + 1 + read-write + + + CUR_LMT_ERR + Current Limit Error +By setting the SD Bus Power bit in the Power Control register, the Host Controller is requested to supply power for the SD Bus. +If the Host Controller supports the Current Limit function, it can be protected from an illegal card by stopping power supply to the card in which case this bit indicates a failure status. +A reading of 1 for this bit means that the Host Controller is not supplying power to the SD card due to some failure. +A reading of 0 for this bit means that the Host Controller is supplying power and no error has occurred. +The Host Controller may require some sampling time to detect the current limit. +SDXC Host Controller does not support this function, this bit is always set to 0. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Power Fail + 23 + 1 + read-write + + + DATA_END_BIT_ERR + Data End Bit Error +This error occurs in SD/eMMC mode either when detecting 0 at the end bit position of read data that uses the DAT line or at the end bit position of the CRC status. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 22 + 1 + read-write + + + DATA_CRC_ERR + Data CRC Error +This error occurs in SD/eMMC mode when detecting CRC error when transferring read data which uses the DAT line, +when detecting the Write CRC status having a value of other than 010 or when write CRC status timeout. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 21 + 1 + read-write + + + DATA_TOUT_ERR + Data Timeout Error +This bit is set in SD/eMMC mode when detecting one of the following timeout conditions: +Busy timeout for R1b, R5b type +Busy timeout after Write CRC status +Write CRC Status timeout +Read Data timeout +Values: +0x0 (FALSE): No error +0x1 (TRUE): Time out + 20 + 1 + read-write + + + CMD_IDX_ERR + Command Index Error +This bit is set if a Command Index error occurs in the command respons in SD/eMMC mode. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 19 + 1 + read-write + + + CMD_END_BIT_ERR + Command End Bit Error +This bit is set when detecting that the end bit of a command response is 0 in SD/eMMC mode. +Values: +0x0 (FALSE): No error +0x1 (TRUE): End Bit error generated + 18 + 1 + read-write + + + CMD_CRC_ERR + Command CRC Error +Command CRC Error is generated in SD/eMMC mode for following two cases. +If a response is returned and the Command Timeout Error is set to 0 (indicating no timeout), this bit is set to 1 when detecting a CRC error in the command response. +The Host Controller detects a CMD line conflict by monitoring the CMD line when a command is issued. +If the Host Controller drives the CMD line to 1 level, +but detects 0 level on the CMD line at the next SD clock edge, then the Host Controller aborts the command (stop driving CMD line) and set this bit to 1. +The Command Timeout Error is also set to 1 to distinguish a CMD line conflict. +Values: +0x0 (FALSE): No error +0x1 (TRUE): CRC error generated + 17 + 1 + read-write + + + CMD_TOUT_ERR + Command Timeout Error +In SD/eMMC Mode,this bit is set only if no response is returned within 64 SD clock cycles from the end bit of the command. +If the Host Controller detects a CMD line conflict, along with Command CRC Error bit, this bit is set to 1, without waiting for 64 SD/eMMC card clock cycles. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Time out + 16 + 1 + read-write + + + ERR_INTERRUPT + Error Interrupt +If any of the bits in the Error Interrupt Status register are set, then this bit is set. +Values: +0x0 (FALSE): No Error +0x1 (TRUE): Error + 15 + 1 + read-only + + + CQE_EVENT + Command Queuing Event +This status is set if Command Queuing/Crypto related event has occurred in eMMC/SD mode. Read CQHCI's CQIS/CRNQIS register for more details. +Values: +0x0 (FALSE): No Event +0x1 (TRUE): Command Queuing Event is detected + 14 + 1 + read-write + + + FX_EVENT + FX Event +This status is set when R[14] of response register is set to 1 and Response Type R1/R5 is set to 0 in Transfer Mode register. This interrupt is used with response check function. +Values: +0x0 (FALSE): No Event +0x1 (TRUE): FX Event is detected + 13 + 1 + read-only + + + RE_TUNE_EVENT + Re-tuning Event +This bit is set if the Re-Tuning Request changes from 0 to 1. Re-Tuning request is not supported. + 12 + 1 + read-only + + + CARD_INTERRUPT + Card Interrupt +This bit reflects the synchronized value of: +DAT[1] Interrupt Input for SD Mode +DAT[2] Interrupt Input for UHS-II Mode +Values: +0x0 (FALSE): No Card Interrupt +0x1 (TRUE): Generate Card Interrupt + 8 + 1 + read-only + + + CARD_REMOVAL + Card Removal +This bit is set if the Card Inserted in the Present State register changes from 1 to 0. +Values: +0x0 (FALSE): Card state stable or Debouncing +0x1 (TRUE): Card Removed + 7 + 1 + read-write + + + CARD_INSERTION + Card Insertion +This bit is set if the Card Inserted in the Present State register changes from 0 to 1. +Values: +0x0 (FALSE): Card state stable or Debouncing +0x1 (TRUE): Card Inserted + 6 + 1 + read-write + + + BUF_RD_READY + Buffer Read Ready +This bit is set if the Buffer Read Enable changes from 0 to 1. +Values: +0x0 (FALSE): Not ready to read buffer +0x1 (TRUE): Ready to read buffer + 5 + 1 + read-write + + + BUF_WR_READY + Buffer Write Ready +This bit is set if the Buffer Write Enable changes from 0 to 1. +Values: +0x0 (FALSE): Not ready to write buffer +0x1 (TRUE): Ready to write buffer + 4 + 1 + read-write + + + DMA_INTERRUPT + DMA Interrupt +This bit is set if the Host Controller detects the SDMA Buffer Boundary during transfer. +In case of ADMA, by setting the Int field in the descriptor table, the Host controller generates this interrupt. +This interrupt is not generated after a Transfer Complete. +Values: +0x0 (FALSE): No DMA Interrupt +0x1 (TRUE): DMA Interrupt is generated + 3 + 1 + read-write + + + BGAP_EVENT + Block Gap Event +This bit is set when both read/write transaction is stopped at block gap due to a Stop at Block Gap Request. +Values: +0x0 (FALSE): No Block Gap Event +0x1 (TRUE): Transaction stopped at block gap + 2 + 1 + read-write + + + XFER_COMPLETE + Transfer Complete +This bit is set when a read/write transfer and a command with status busy is completed. +Values: +0x0 (FALSE): Not complete +0x1 (TRUE): Command execution is completed + 1 + 1 + read-write + + + CMD_COMPLETE + Command Complete +In an SD/eMMC Mode, this bit is set when the end bit of a response except for Auto CMD12 and Auto CMD23. +This interrupt is not generated when the Response Interrupt Disable in Transfer Mode Register is set to 1. +Values: +0x0 (FALSE): No command complete +0x1 (TRUE): Command Complete + 0 + 1 + read-write + + + + + INT_STAT_EN + No description available + 0x34 + 32 + 0x00000000 + 0x1FFF71FF + + + BOOT_ACK_ERR_STAT_EN + Boot Acknowledgment Error (eMMC Mode only) +Setting this bit to 1 enables setting of Boot Acknowledgment Error in Error Interrupt Status register (INT_STAT). +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 28 + 1 + read-write + + + RESP_ERR_STAT_EN + Response Error Status Enable (SD Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 27 + 1 + read-write + + + TUNING_ERR_STAT_EN + Tuning Error Status Enable (UHS-I Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 26 + 1 + read-write + + + ADMA_ERR_STAT_EN + ADMA Error Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 25 + 1 + read-write + + + AUTO_CMD_ERR_STAT_EN + Auto CMD Error Status Enable (SD/eMMC Mode only). +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 24 + 1 + read-write + + + CUR_LMT_ERR_STAT_EN + Current Limit Error Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 23 + 1 + read-write + + + DATA_END_BIT_ERR_STAT_EN + Data End Bit Error Status Enable (SD/eMMC Mode only). +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 22 + 1 + read-write + + + DATA_CRC_ERR_STAT_EN + Data CRC Error Status Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 21 + 1 + read-write + + + DATA_TOUT_ERR_STAT_EN + Data Timeout Error Status Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 20 + 1 + read-write + + + CMD_IDX_ERR_STAT_EN + Command Index Error Status Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 19 + 1 + read-write + + + CMD_END_BIT_ERR_STAT_EN + Command End Bit Error Status Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 18 + 1 + read-write + + + CMD_CRC_ERR_STAT_EN + Command CRC Error Status Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 17 + 1 + read-write + + + CMD_TOUT_ERR_STAT_EN + Command Timeout Error Status Enable (SD/eMMC Mode only). +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 16 + 1 + read-write + + + CQE_EVENT_STAT_EN + CQE Event Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 14 + 1 + read-write + + + FX_EVENT_STAT_EN + FX Event Status Enable +This bit is added from Version 4.10. +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 13 + 1 + read-write + + + RE_TUNE_EVENT_STAT_EN + Re-Tuning Event (UHS-I only) Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 12 + 1 + read-write + + + CARD_INTERRUPT_STAT_EN + Card Interrupt Status Enable +If this bit is set to 0, the Host Controller clears the interrupt request to the System. +The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. +The Host Driver may clear the Card Interrupt Status Enable before servicing the Card Interrupt and may set this bit again after all interrupt requests from the card are cleared to prevent inadvertent interrupts. +By setting this bit to 0, interrupt input must be masked by implementation so that the interrupt input is not affected by external signal in any state (for example, floating). +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 8 + 1 + read-write + + + CARD_REMOVAL_STAT_EN + Card Removal Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 7 + 1 + read-write + + + CARD_INSERTION_STAT_EN + Card Insertion Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 6 + 1 + read-write + + + BUF_RD_READY_STAT_EN + Buffer Read Ready Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 5 + 1 + read-write + + + BUF_WR_READY_STAT_EN + Buffer Write Ready Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 4 + 1 + read-write + + + DMA_INTERRUPT_STAT_EN + DMA Interrupt Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 3 + 1 + read-write + + + BGAP_EVENT_STAT_EN + Block Gap Event Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 2 + 1 + read-write + + + XFER_COMPLETE_STAT_EN + Transfer Complete Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 1 + 1 + read-write + + + CMD_COMPLETE_STAT_EN + Command Complete Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 0 + 1 + read-write + + + + + INT_SIGNAL_EN + No description available + 0x38 + 32 + 0x00000000 + 0x1FFF71FF + + + BOOT_ACK_ERR_SIGNAL_EN + Boot Acknowledgment Error (eMMC Mode only). +Setting this bit to 1 enables generating interrupt signal when Boot Acknowledgment Error in Error Interrupt Status register is set. +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 28 + 1 + read-write + + + RESP_ERR_SIGNAL_EN + Response Error Signal Enable (SD Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 27 + 1 + read-write + + + TUNING_ERR_SIGNAL_EN + Tuning Error Signal Enable (UHS-I Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 26 + 1 + read-write + + + ADMA_ERR_SIGNAL_EN + ADMA Error Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 25 + 1 + read-write + + + AUTO_CMD_ERR_SIGNAL_EN + Auto CMD Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 24 + 1 + read-write + + + CUR_LMT_ERR_SIGNAL_EN + Current Limit Error Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 23 + 1 + read-write + + + DATA_END_BIT_ERR_SIGNAL_EN + Data End Bit Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 22 + 1 + read-write + + + DATA_CRC_ERR_SIGNAL_EN + Data CRC Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 21 + 1 + read-write + + + DATA_TOUT_ERR_SIGNAL_EN + Data Timeout Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 20 + 1 + read-write + + + CMD_IDX_ERR_SIGNAL_EN + Command Index Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 19 + 1 + read-write + + + CMD_END_BIT_ERR_SIGNAL_EN + Command End Bit Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 18 + 1 + read-write + + + CMD_CRC_ERR_SIGNAL_EN + Command CRC Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 17 + 1 + read-write + + + CMD_TOUT_ERR_SIGNAL_EN + Command Timeout Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 16 + 1 + read-write + + + CQE_EVENT_SIGNAL_EN + Command Queuing Engine Event Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 14 + 1 + read-write + + + FX_EVENT_SIGNAL_EN + FX Event Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 13 + 1 + read-write + + + RE_TUNE_EVENT_SIGNAL_EN + Re-Tuning Event (UHS-I only) Signal Enable. +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 12 + 1 + read-write + + + CARD_INTERRUPT_SIGNAL_EN + Card Interrupt Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 8 + 1 + read-write + + + CARD_REMOVAL_SIGNAL_EN + Card Removal Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 7 + 1 + read-write + + + CARD_INSERTION_SIGNAL_EN + Card Insertion Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 6 + 1 + read-write + + + BUF_RD_READY_SIGNAL_EN + Buffer Read Ready Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 5 + 1 + read-write + + + BUF_WR_READY_SIGNAL_EN + Buffer Write Ready Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 4 + 1 + read-write + + + DMA_INTERRUPT_SIGNAL_EN + DMA Interrupt Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 3 + 1 + read-write + + + BGAP_EVENT_SIGNAL_EN + Block Gap Event Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 2 + 1 + read-write + + + XFER_COMPLETE_SIGNAL_EN + Transfer Complete Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 1 + 1 + read-write + + + CMD_COMPLETE_SIGNAL_EN + Command Complete Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 0 + 1 + read-write + + + + + AC_HOST_CTRL + No description available + 0x3c + 32 + 0x00000000 + 0xDCCF00BF + + + PRESET_VAL_ENABLE + Preset Value Enable +This bit enables automatic selection of SDCLK frequency and Driver strength Preset Value registers. +When Preset Value Enable is set, SDCLK frequency generation (Frequency Select and Clock Generator Select) and the driver strength selection are performed by the controller. +These values are selected from set of Preset Value registers based on selected speed mode. +Values: +0x0 (FALSE): SDCLK and Driver Strength are controlled by Host Driver +0x1 (TRUE): Automatic Selection by Preset Value are Enabled + 31 + 1 + read-write + + + ASYNC_INT_ENABLE + Asynchronous Interrupt Enable +This bit can be set if a card supports asynchronous interrupts and Asynchronous Interrupt Support is set to 1 in the Capabilities register. +Values: +0x0 (FALSE): Disabled +0x1 (TRUE): Enabled + 30 + 1 + read-write + + + HOST_VER4_ENABLE + Host Version 4 Enable +This bit selects either Version 3.00 compatible mode or Version 4 mode. +Functions of following fields are modified for Host Version 4 mode: +SDMA Address: SDMA uses ADMA System Address (05Fh-058h) instead of SDMA System Address register (003h-000h) +ADMA2/ADMA3 selection: ADMA3 is selected by DMA select in Host Control 1 register +64-bit ADMA Descriptor Size: 128-bit descriptor is used instead of 96-bit descriptor when 64-bit Addressing is set to 1 +Selection of 32-bit/64-bit System Addressing: Either 32-bit or 64-bit system addressing is selected by 64-bit Addressing bit in this register +32-bit Block Count: SDMA System Address register (003h-000h) is modified to 32-bit Block Count register +Note: It is recommended not to program ADMA3 Integrated Descriptor Address registers, +UHS-II registers and Command Queuing registers (if applicable) while operating in Host version less than 4 mode (Host Version 4 Enable = 0). +Values: +0x0 (FALSE): Version 3.00 compatible mode +0x1 (TRUE): Version 4 mode + 28 + 1 + read-write + + + CMD23_ENABLE + CMD23 Enable +If the card supports CMD23, this bit is set to 1. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3 data transfer. +Values: +0x0 (FALSE): Auto CMD23 is disabled +0x1 (TRUE): Auto CMD23 is enabled + 27 + 1 + read-write + + + ADMA2_LEN_MODE + ADMA2 Length Mode +This bit selects ADMA2 Length mode to be either 16-bit or 26-bit. +Values: +0x0 (FALSE): 16-bit Data Length Mode +0x1 (TRUE): 26-bit Data Length Mode + 26 + 1 + read-write + + + SAMPLE_CLK_SEL + Sampling Clock Select +This bit is used by the Host Controller to select the sampling clock in SD/eMMC mode to receive CMD and DAT. +This bit is set by the tuning procedure and is valid after the completion of tuning (when Execute Tuning is cleared). +Setting this bit to 1 means that tuning is completed successfully and setting this bit to 0 means that tuning has failed. +The value is reflected on the sample_cclk_sel pin. +Values: +0x0 (FALSE): Fixed clock is used to sample data +0x1 (TRUE): Tuned clock is used to sample data + 23 + 1 + read-write + + + EXEC_TUNING + Execute Tuning +This bit is set to 1 to start the tuning procedure in UHS-I/eMMC speed modes and this bit is automatically cleared when tuning procedure is completed. +Values: +0x0 (FALSE): Not Tuned or Tuning completed +0x1 (TRUE): Execute Tuning + 22 + 1 + read-write + + + SIGNALING_EN + 1.8V Signaling Enable +This bit controls voltage regulator for I/O cell in UHS-I/eMMC speed modes. +Setting this bit from 0 to 1 starts changing the signal voltage from 3.3V to 1.8V. +Host Controller clears this bit if switching to 1.8 signaling fails. The value is reflected on the uhs1_swvolt_en pin. +Note: This bit must be set for all UHS-I speed modes (SDR12/SDR25/SDR50/SDR104/DDR50). +Values: +0x0 (V_3_3): 3.3V Signalling +0x1 (V_1_8): 1.8V Signalling + 19 + 1 + read-write + + + UHS_MODE_SEL + UHS Mode/eMMC Speed Mode Select +These bits are used to select UHS mode in the SD mode of operation. In eMMC mode, these bits are used to select eMMC Speed mode. +UHS Mode (SD/UHS-II mode only): +0x0 (SDR12): SDR12/Legacy +0x1 (SDR25): SDR25/High Speed SDR +0x2 (SDR50): SDR50 +0x3 (SDR104): SDR104/HS200 +0x4 (DDR50): DDR50/High Speed DDR +0x5 (RSVD5): Reserved +0x6 (RSVD6): Reserved +0x7 (UHS2): UHS-II/HS400 +eMMC Speed Mode (eMMC mode only): +0x0: Legacy +0x1: High Speed SDR +0x2: Reserved +0x3: HS200 +0x4: High Speed DDR +0x5: Reserved +0x6: Reserved +0x7: HS400 + 16 + 3 + read-write + + + CMD_NOT_ISSUED_AUTO_CMD12 + Command Not Issued By Auto CMD12 Error +If this bit is set to 1, CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register. +This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. +Values: +0x1 (TRUE): Not Issued +0x0 (FALSE): No Error + 7 + 1 + read-only + + + AUTO_CMD_RESP_ERR + Auto CMD Response Error +This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or CMD13. +This status is ignored if any bit between D00 to D04 is set to 1. +Values: +0x1 (TRUE): Error +0x0 (FALSE): No Error + 5 + 1 + read-only + + + AUTO_CMD_IDX_ERR + Auto CMD Index Error +This bit is set if the command index error occurs in response to a command. +Values: +0x1 (TRUE): Error +0x0 (FALSE): No Error + 4 + 1 + read-only + + + AUTO_CMD_EBIT_ERR + Auto CMD End Bit Error +This bit is set when detecting that the end bit of command response is 0. +Values: +0x1 (TRUE): End Bit Error Generated +0x0 (FALSE): No Error + 3 + 1 + read-only + + + AUTO_CMD_CRC_ERR + Auto CMD CRC Error +This bit is set when detecting a CRC error in the command response. +Values: +0x1 (TRUE): CRC Error Generated +0x0 (FALSE): No Error + 2 + 1 + read-only + + + AUTO_CMD_TOUT_ERR + Auto CMD Timeout Error +This bit is set if no response is returned with 64 SDCLK cycles from the end bit of the command. +If this bit is set to 1, error status bits (D04-D01) are meaningless. +Values: +0x1 (TRUE): Time out +0x0 (FALSE): No Error + 1 + 1 + read-only + + + AUTO_CMD12_NOT_EXEC + Auto CMD12 Not Executed +If multiple memory block data transfer is not started due to a command error, this bit is not set because it is not necessary to issue an Auto CMD12. +Setting this bit to 1 means that the Host Controller cannot issue Auto CMD12 to stop multiple memory block data transfer, due to some error. + If this bit is set to 1, error status bits (D04-D01) is meaningless. +This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. +Values: +0x1 (TRUE): Not Executed +0x0 (FALSE): Executed + 0 + 1 + read-only + + + + + CAPABILITIES1 + No description available + 0x40 + 32 + 0x00000000 + 0xE7EFFFBF + + + SLOT_TYPE_R + Slot Type +These bits indicate usage of a slot by a specific Host System. +Values: +0x0 (REMOVABLE_SLOT): Removable Card Slot +0x1 (EMBEDDED_SLOT): Embedded Slot for one Device +0x2 (SHARED_SLOT): Shared Bus Slot (SD mode) +0x3 (UHS2_EMBEDDED_SLOT): UHS-II Multiple Embedded Devices + 30 + 2 + read-only + + + ASYNC_INT_SUPPORT + Asynchronous Interrupt Support (SD Mode only) +Values: +0x0 (FALSE): Asynchronous Interrupt Not Supported +0x1 (TRUE): Asynchronous Interrupt Supported + 29 + 1 + read-only + + + VOLT_18 + Voltage Support for 1.8V +Values: +0x0 (FALSE): 1.8V Not Supported +0x1 (TRUE): 1.8V Supported + 26 + 1 + read-only + + + VOLT_30 + Voltage Support for SD 3.0V or Embedded 1.2V +Values: +0x0 (FALSE): SD 3.0V or Embedded 1.2V Not Supported +0x1 (TRUE): SD 3.0V or Embedded Supported + 25 + 1 + read-only + + + VOLT_33 + Voltage Support for 3.3V +Values: +0x0 (FALSE): 3.3V Not Supported +0x1 (TRUE): 3.3V Supported + 24 + 1 + read-only + + + SUS_RES_SUPPORT + Suspense/Resume Support +This bit indicates whether the Host Controller supports Suspend/Resume functionality. +If this bit is 0, the Host Driver does not issue either Suspend or Resume commands because the Suspend and Resume mechanism is not supported. +Values: +0x0 (FALSE): Not Supported +0x1 (TRUE): Supported + 23 + 1 + read-only + + + SDMA_SUPPORT + SDMA Support +This bit indicates whether the Host Controller is capable of using SDMA to transfer data between the system memory and the Host Controller directly. +Values: +0x0 (FALSE): SDMA not Supported +0x1 (TRUE): SDMA Supported + 22 + 1 + read-only + + + HIGH_SPEED_SUPPORT + High Speed Support +This bit indicates whether the Host Controller and the Host System supports High Speed mode and they can supply the SD Clock frequency from 25 MHz to 50 MHz. +Values: +0x0 (FALSE): High Speed not Supported +0x1 (TRUE): High Speed Supported + 21 + 1 + read-only + + + ADMA2_SUPPORT + ADMA2 Support +This bit indicates whether the Host Controller is capable of using ADMA2. +Values: +0x0 (FALSE): ADMA2 not Supported +0x1 (TRUE): ADMA2 Supported + 19 + 1 + read-only + + + EMBEDDED_8_BIT + 8-bit Support for Embedded Device +This bit indicates whether the Host Controller is capable of using an 8-bit bus width mode. This bit is not effective when the Slot Type is set to 10b. +Values: +0x0 (FALSE): 8-bit Bus Width not Supported +0x1 (TRUE): 8-bit Bus Width Supported + 18 + 1 + read-only + + + MAX_BLK_LEN + Maximum Block Length +This bit indicates the maximum block size that the Host driver can read and write to the buffer in the Host Controller. +The buffer transfers this block size without wait cycles. The transfer block length is always 512 bytes for the SD Memory irrespective of this bit +Values: +0x0 (ZERO): 512 Byte +0x1 (ONE): 1024 Byte +0x2 (TWO): 2048 Byte +0x3 (THREE): Reserved + 16 + 2 + read-only + + + BASE_CLK_FREQ + Base Clock Frequency for SD clock +These bits indicate the base (maximum) clock frequency for the SD Clock. The definition of these bits depend on the Host Controller Version. +6-Bit Base Clock Frequency: This mode is supported by the Host Controller version 1.00 and 2.00. +The upper 2 bits are not effective and are always 0. The unit values are 1 MHz. The supported clock range is 10 MHz to 63 MHz. +-0x00 : Get information through another method +-0x01 : 1 MHz +-0x02 : 2 MHz +-............. +-0x3F : 63 MHz +-0x40-0xFF : Not Supported +8-Bit Base Clock Frequency: This mode is supported by the Host Controller version 3.00. The unit values are 1 MHz. The supported clock range is 10 MHz to 255 MHz. +-0x00 : Get information through another method +-0x01 : 1 MHz +-0x02 : 2 MHz +-............ +-0xFF : 255 MHz +If the frequency is 16.5 MHz, the larger value is set to 0001001b (17 MHz) because the Host Driver uses this value to calculate the clock divider value and it does not exceed the upper limit of the SD Clock frequency. +If these bits are all 0, the Host system has to get information using a different method. + 8 + 8 + read-only + + + TOUT_CLK_UNIT + Timeout Clock Unit +This bit shows the unit of base clock frequency used to detect Data TImeout Error. +Values: +0x0 (KHZ): KHz +0x1 (MHZ): MHz + 7 + 1 + read-only + + + TOUT_CLK_FREQ + Timeout Clock Frequency +This bit shows the base clock frequency used to detect Data Timeout Error. The Timeout Clock unit defines the unit of timeout clock frequency. It can be KHz or MHz. +0x00 : Get information through another method +0x01 : 1KHz / 1MHz +0x02 : 2KHz / 2MHz +0x03 : 3KHz / 3MHz + ........... +0x3F : 63KHz / 63MHz + 0 + 6 + read-only + + + + + CAPABILITIES2 + No description available + 0x44 + 32 + 0x00000000 + 0x18FFEF7F + + + VDD2_18V_SUPPORT + 1.8V VDD2 Support +This bit indicates support of VDD2 for the Host System. +0x0 (FALSE): 1.8V VDD2 is not Supported +0x1 (TRUE): 1.8V VDD2 is Supported + 28 + 1 + read-only + + + ADMA3_SUPPORT + ADMA3 Support +This bit indicates whether the Host Controller is capable of using ADMA3. +Values: +0x0 (FALSE): ADMA3 not Supported +0x1 (TRUE): ADMA3 Supported + 27 + 1 + read-only + + + CLK_MUL + Clock Multiplier +These bits indicate the clock multiplier of the programmable clock generator. Setting these bits to 0 means that the Host Controller does not support a programmable clock generator. +0x0: Clock Multiplier is not Supported +0x1: Clock Multiplier M = 2 +0x2: Clock Multiplier M = 3 + ......... +0xFF: Clock Multiplier M = 256 + 16 + 8 + read-only + + + RE_TUNING_MODES + Re-Tuning Modes (UHS-I only) +These bits select the re-tuning method and limit the maximum data length. +Values: +0x0 (MODE1): Timer +0x1 (MODE2): Timer and Re-Tuning Request (Not supported) +0x2 (MODE3): Auto Re-Tuning (for transfer) +0x3 (RSVD_MODE): Reserved + 14 + 2 + read-only + + + USE_TUNING_SDR50 + Use Tuning for SDR50 (UHS-I only) +Values: +0x0 (ZERO): SDR50 does not require tuning +0x1 (ONE): SDR50 requires tuning + 13 + 1 + read-only + + + RETUNE_CNT + Timer Count for Re-Tuning (UHS-I only) +0x0: Re-Tuning Timer disabled +0x1: 1 seconds +0x2: 2 seconds +0x3: 4 seconds + ........ +0xB: 1024 seconds +0xC: Reserved +0xD: Reserved +0xE: Reserved +0xF: Get information from other source + 8 + 4 + read-only + + + DRV_TYPED + Driver Type D Support (UHS-I only) +This bit indicates support of Driver Type D for 1.8 Signaling. +Values: +0x0 (FALSE): Driver Type D is not supported +0x1 (TRUE): Driver Type D is supported + 6 + 1 + read-only + + + DRV_TYPEC + Driver Type C Support (UHS-I only) +This bit indicates support of Driver Type C for 1.8 Signaling. +Values: +0x0 (FALSE): Driver Type C is not supported +0x1 (TRUE): Driver Type C is supported + 5 + 1 + read-only + + + DRV_TYPEA + Driver Type A Support (UHS-I only) +This bit indicates support of Driver Type A for 1.8 Signaling. +Values: +0x0 (FALSE): Driver Type A is not supported +0x1 (TRUE): Driver Type A is supported + 4 + 1 + read-only + + + UHS2_SUPPORT + UHS-II Support (UHS-II only) +This bit indicates whether Host Controller supports UHS-II. +Values: +0x0 (FALSE): UHS-II is not supported +0x1 (TRUE): UHS-II is supported + 3 + 1 + read-only + + + DDR50_SUPPORT + DDR50 Support (UHS-I only) +Values: +0x0 (FALSE): DDR50 is not supported +0x1 (TRUE): DDR50 is supported + 2 + 1 + read-only + + + SDR104_SUPPORT + SDR104 Support (UHS-I only) +This bit mentions that SDR104 requires tuning. +Values: +0x0 (FALSE): SDR104 is not supported +0x1 (TRUE): SDR104 is supported + 1 + 1 + read-only + + + SDR50_SUPPORT + SDR50 Support (UHS-I only) +This bit indicates that SDR50 is supported. The bit 13 (USE_TUNING_SDR50) indicates whether SDR50 requires tuning or not. +Values: +0x0 (FALSE): SDR50 is not supported +0x1 (TRUE): SDR50 is supported + 0 + 1 + read-only + + + + + CURR_CAPABILITIES1 + No description available + 0x48 + 32 + 0x00000000 + 0x00FFFFFF + + + MAX_CUR_18V + Maximum Current for 1.8V +This bit specifies the Maximum Current for 1.8V VDD1 power supply for the card. +0: Get information through another method +1: 4mA +2: 8mA +3: 13mA +....... +255: 1020mA + 16 + 8 + read-only + + + MAX_CUR_30V + Maximum Current for 3.0V +This bit specifies the Maximum Current for 3.0V VDD1 power supply for the card. +0: Get information through another method +1: 4mA +2: 8mA +3: 13mA +....... +255: 1020mA + 8 + 8 + read-only + + + MAX_CUR_33V + Maximum Current for 3.3V +This bit specifies the Maximum Current for 3.3V VDD1 power supply for the card. +0: Get information through another method +1: 4mA +2: 8mA +3: 13mA +....... +255: 1020mA + 0 + 8 + read-only + + + + + CURR_CAPABILITIES2 + No description available + 0x4c + 32 + 0x00000000 + 0x000000FF + + + MAX_CUR_VDD2_18V + Maximum Current for 1.8V VDD2 +This bit specifies the Maximum Current for 1.8V VDD2 power supply for the UHS-II card. +0: Get information through another method +1: 4mA +2: 8mA +3: 13mA +....... +255: 1020mA + 0 + 8 + read-only + + + + + FORCE_EVENT + No description available + 0x50 + 32 + 0x00000000 + 0x1FFF00BF + + + FORCE_BOOT_ACK_ERR + Force Event for Boot Ack error +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Boot ack Error Status is set + 28 + 1 + write-only + + + FORCE_RESP_ERR + Force Event for Response Error (SD Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Response Error Status is set + 27 + 1 + write-only + + + FORCE_TUNING_ERR + Force Event for Tuning Error (UHS-I Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Tuning Error Status is set + 26 + 1 + write-only + + + FORCE_ADMA_ERR + Force Event for ADMA Error +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): ADMA Error Status is set + 25 + 1 + write-only + + + FORCE_AUTO_CMD_ERR + Force Event for Auto CMD Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Auto CMD Error Status is set + 24 + 1 + write-only + + + FORCE_CUR_LMT_ERR + Force Event for Current Limit Error +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Current Limit Error Status is set + 23 + 1 + write-only + + + FORCE_DATA_END_BIT_ERR + Force Event for Data End Bit Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Data End Bit Error Status is set + 22 + 1 + write-only + + + FORCE_DATA_CRC_ERR + Force Event for Data CRC Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Data CRC Error Status is set + 21 + 1 + write-only + + + FORCE_DATA_TOUT_ERR + Force Event for Data Timeout Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Data Timeout Error Status is set + 20 + 1 + write-only + + + FORCE_CMD_IDX_ERR + Force Event for Command Index Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Command Index Error Status is set + 19 + 1 + write-only + + + FORCE_CMD_END_BIT_ERR + Force Event for Command End Bit Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Command End Bit Error Status is set + 18 + 1 + write-only + + + FORCE_CMD_CRC_ERR + Force Event for Command CRC Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Command CRC Error Status is set + 17 + 1 + write-only + + + FORCE_CMD_TOUT_ERR + Force Event for Command Timeout Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Command Timeout Error Status is set + 16 + 1 + write-only + + + FORCE_CMD_NOT_ISSUED_AUTO_CMD12 + Force Event for Command Not Issued By Auto CMD12 Error +Values: +0x1 (TRUE): Command Not Issued By Auto CMD12 Error Status is set +0x0 (FALSE): Not Affected + 7 + 1 + write-only + + + FORCE_AUTO_CMD_RESP_ERR + Force Event for Auto CMD Response Error +Values: +0x1 (TRUE): Auto CMD Response Error Status is set +0x0 (FALSE): Not Affected + 5 + 1 + write-only + + + FORCE_AUTO_CMD_IDX_ERR + Force Event for Auto CMD Index Error +Values: +0x1 (TRUE): Auto CMD Index Error Status is set +0x0 (FALSE): Not Affected + 4 + 1 + write-only + + + FORCE_AUTO_CMD_EBIT_ERR + Force Event for Auto CMD End Bit Error +Values: +0x1 (TRUE): Auto CMD End Bit Error Status is set +0x0 (FALSE): Not Affected + 3 + 1 + write-only + + + FORCE_AUTO_CMD_CRC_ERR + Force Event for Auto CMD CRC Error +Values: +0x1 (TRUE): Auto CMD CRC Error Status is set +0x0 (FALSE): Not Affected + 2 + 1 + write-only + + + FORCE_AUTO_CMD_TOUT_ERR + Force Event for Auto CMD Timeout Error +Values: +0x1 (TRUE): Auto CMD Timeout Error Status is set +0x0 (FALSE): Not Affected + 1 + 1 + write-only + + + FORCE_AUTO_CMD12_NOT_EXEC + Force Event for Auto CMD12 Not Executed +Values: +0x1 (TRUE): Auto CMD12 Not Executed Status is set +0x0 (FALSE): Not Affected + 0 + 1 + write-only + + + + + ADMA_ERR_STAT + No description available + 0x54 + 32 + 0x00000000 + 0x00000007 + + + ADMA_LEN_ERR + ADMA Length Mismatch Error States +This error occurs in the following instances: +While the Block Count Enable is being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length +When the total data length cannot be divided by the block length +Values: +0x0 (NO_ERR): No Error +0x1 (ERROR): Error + 2 + 1 + read-only + + + ADMA_ERR_STATES + ADMA Error States +These bits indicate the state of ADMA when an error occurs during ADMA data transfer. +Values: +0x0 (ST_STOP): Stop DMA - SYS_ADR register points to a location next to the error descriptor +0x1 (ST_FDS): Fetch Descriptor - SYS_ADR register points to the error descriptor +0x2 (UNUSED): Never set this state +0x3 (ST_TFR): Transfer Data - SYS_ADR register points to a location next to the error descriptor + 0 + 2 + read-only + + + + + ADMA_SYS_ADDR + No description available + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADMA_SA + ADMA System Address +These bits indicate the lower 32 bits of the ADMA system address. +SDMA: If Host Version 4 Enable is set to 1, this register stores the system address of the data location +ADMA2: This register stores the byte address of the executing command of the descriptor table +ADMA3: This register is set by ADMA3. ADMA2 increments the address of this register that points to the next line, every time a Descriptor line is fetched. + 0 + 32 + read-write + + + + + 9 + 0x2 + INIT,DS,HS,SDR12,SDR25,SDR50,SDR104,DDR50,rsv8,rsv9,UHS2 + PRESET[%s] + no description available + 0x60 + 16 + 0x0000 + 0x07FF + + + CLK_GEN_SEL_VAL + Clock Generator Select Value +This bit is effective when the Host Controller supports a programmable clock generator. +Values: +0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator +0x1 (PROG): Programmable Clock Generator + 10 + 1 + read-only + + + FREQ_SEL_VAL + SDCLK/RCLK Frequency Select Value +10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. + 0 + 10 + read-only + + + + + ADMA_ID_ADDR + No description available + 0x78 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADMA_ID_ADDR + ADMA Integrated Descriptor Address +These bits indicate the lower 32-bit of the ADMA Integrated Descriptor address. +The start address of Integrated Descriptor is set to these register bits. +The ADMA3 fetches one Descriptor Address and increments these bits to indicate the next Descriptor address. + 0 + 32 + read-write + + + + + P_EMBEDDED_CNTRL + No description available + 0xe6 + 16 + 0x0000 + 0x0FFF + + + REG_OFFSET_ADDR + Offset Address of Embedded Control register. + 0 + 12 + read-only + + + + + P_VENDOR_SPECIFIC_AREA + No description available + 0xe8 + 16 + 0x0000 + 0x0FFF + + + REG_OFFSET_ADDR + Base offset Address for Vendor-Specific registers. + 0 + 12 + read-only + + + + + P_VENDOR2_SPECIFIC_AREA + No description available + 0xea + 16 + 0x0000 + 0xFFFF + + + REG_OFFSET_ADDR + Base offset Address for Command Queuing registers. + 0 + 16 + read-only + + + + + SLOT_INTR_STATUS + No description available + 0xfc + 16 + 0x0000 + 0x00FF + + + INTR_SLOT + Interrupt signal for each Slot +These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot. +A maximum of 8 slots can be defined. If one interrupt signal is associated with multiple slots, the Host Driver can identify the interrupt that is generated by reading these bits. + By a power on reset or by setting Software Reset For All bit, the interrupt signals are de-asserted and this status reads 00h. +Bit 00: Slot 1 +Bit 01: Slot 2 +Bit 02: Slot 3 +.......... +.......... +Bit 07: Slot 8 +Note: MSHC Host Controller support single card slot. This register shall always return 0. + 0 + 8 + read-only + + + + + CQVER + No description available + 0x180 + 32 + 0x00000000 + 0x00000FFF + + + EMMC_VER_MAHOR + This bit indicates the eMMC major version (1st digit left of decimal point) in BCD format. + 8 + 4 + read-only + + + EMMC_VER_MINOR + This bit indicates the eMMC minor version (1st digit right of decimal point) in BCD format. + 4 + 4 + read-only + + + EMMC_VER_SUFFIX + This bit indicates the eMMC version suffix (2nd digit right of decimal point) in BCD format. + 0 + 4 + read-only + + + + + CQCAP + No description available + 0x184 + 32 + 0x00000000 + 0x1000F3FF + + + CRYPTO_SUPPORT + Crypto Support +This bit indicates whether the Host Controller supports cryptographic operations. +Values: +0x0 (FALSE): Crypto not Supported +0x1 (TRUE): Crypto Supported + 28 + 1 + read-only + + + ITCFMUL + Internal Timer Clock Frequency Multiplier (ITCFMUL) +This field indicates the frequency of the clock used for interrupt coalescing timer and for determining the SQS +polling period. See ITCFVAL definition for details. Values 0x5 to 0xF are reserved. +Values: +0x0 (CLK_1KHz): 1KHz clock +0x1 (CLK_10KHz): 10KHz clock +0x2 (CLK_100KHz): 100KHz clock +0x3 (CLK_1MHz): 1MHz clock +0x4 (CLK_10MHz): 10MHz clock + 12 + 4 + read-only + + + ITCFVAL + Internal Timer Clock Frequency Value (ITCFVAL) +This field scales the frequency of the timer clock provided by ITCFMUL. The Final clock frequency of actual timer clock is calculated as ITCFVAL* ITCFMUL. + 0 + 10 + read-only + + + + + CQCFG + No description available + 0x188 + 32 + 0x00000000 + 0x00001101 + + + DCMD_EN + This bit indicates to the hardware whether the Task +Descriptor in slot #31 of the TDL is a data transfer descriptor or a direct-command descriptor. CQE uses this bit when a task is issued in slot #31, to determine how to decode the Task Descriptor. +Values: +0x1 (SLOT31_DCMD_ENABLE): Task descriptor in slot #31 is a DCMD Task Descriptor +0x0 (SLOT31_DCMD_DISABLE): Task descriptor in slot #31 is a data Transfer Task Descriptor + 12 + 1 + read-write + + + TASK_DESC_SIZE + Bit Value Description +This bit indicates the size of task descriptor used in host memory. This bit can only be configured when Command Queuing Enable bit is 0 (command queuing is disabled). +Values: +0x1 (TASK_DESC_128b): Task descriptor size is 128 bits +0x0 (TASK_DESC_64b): Task descriptor size is 64 bit + 8 + 1 + read-write + + + CQ_EN + No description available + 0 + 1 + read-write + + + + + CQCTL + No description available + 0x18c + 32 + 0x00000000 + 0x00000101 + + + CLR_ALL_TASKS + Clear all tasks +This bit can only be written when the controller is halted. This bit does not clear tasks in the device. The software has to use the CMDQ_TASK_MGMT command to clear device's queue. +Values: +0x1 (CLEAR_ALL_TASKS): Clears all the tasks in the controller +0x0 (NO_EFFECT): Programming 0 has no effect + 8 + 1 + read-write + + + HALT + Halt request and resume +Values: +0x1 (HALT_CQE): Software writes 1 to this bit when it wants to acquire software control over the eMMC bus and to disable CQE from issuing command on the bus. +For example, issuing a Discard Task command (CMDQ_TASK_MGMT). +When the software writes 1, CQE completes the ongoing task (if any in progress). +After the task is completed and the CQE is in idle state, CQE does not issue new commands and indicates to the software by setting this bit to 1. +The software can poll on this bit until it is set to 1 and only then send commands on the eMMC bus. +0x0 (RESUME_CQE): Software writes 0 to this bit to exit from the halt state and resume CQE activity + 0 + 1 + read-write + + + + + CQIS + No description available + 0x190 + 32 + 0x00000000 + 0x0000000F + + + TCL + Task cleared interrupt +This status bit is asserted (if CQISE.TCL_STE=1) when a task clear operation is completed by CQE. +The completed task clear operation is either an individual task clear (by writing CQTCLR) or clearing of all tasks (by writing CQCTL). +A value of 1 clears this status bit. +Values: +0x1 (SET): TCL Interrupt is set +0x0 (NOTSET): TCL Interrupt is not set + 3 + 1 + read-write + + + RED + Response error detected interrupt +This status bit is asserted (if CQISE.RED_STE=1) when a response is received with an error bit set in the device status +field. Configure the CQRMEM register to identify device status bit fields that may trigger an interrupt and that are masked. +A value of 1 clears this status bit. +Values: +0x1 (SET): RED Interrupt is set +0x0 (NOTSET): RED Interrupt is not set + 2 + 1 + read-write + + + TCC + Task complete interrupt +This status bit is asserted (if CQISE.TCC_STE=1) when at least one of the following conditions are met: +A task is completed and the INT bit is set in its Task Descriptor +Interrupt caused by Interrupt Coalescing logic due to timeout +Interrupt Coalescing logic reached the configured threshold +A value of 1 clears this status bit + 1 + 1 + read-write + + + HAC + Halt complete interrupt +This status bit is asserted (only if CQISE.HAC_STE=1) when halt bit in the CQCTL register transitions from 0 to 1 indicating that the host controller has completed its current ongoing task and has entered halt state. +A value of 1 clears this status bit. +Values: +0x1 (SET): HAC Interrupt is set +0x0 (NOTSET): HAC Interrupt is not set + 0 + 1 + read-write + + + + + CQISE + No description available + 0x194 + 32 + 0x00000000 + 0x0000000F + + + TCL_STE + Task cleared interrupt status enable +Values: +0x1 (INT_STS_ENABLE): CQIS.TCL is set when its interrupt condition is active +0x0 (INT_STS_DISABLE): CQIS.TCL is disabled + 3 + 1 + read-write + + + RED_STE + Response error detected interrupt status enable +Values: +0x1 (INT_STS_ENABLE): CQIS.RED is set when its interrupt condition is active +0x0 (INT_STS_DISABLE): CQIS.RED is disabled + 2 + 1 + read-write + + + TCC_STE + Task complete interrupt status enable +Values: +0x1 (INT_STS_ENABLE): CQIS.TCC is set when its interrupt condition is active +0x0 (INT_STS_DISABLE): CQIS.TCC is disabled + 1 + 1 + read-write + + + HAC_STE + Halt complete interrupt status enable +Values: +0x1 (INT_STS_ENABLE): CQIS.HAC is set when its interrupt condition is active +0x0 (INT_STS_DISABLE): CQIS.HAC is disabled + 0 + 1 + read-write + + + + + CQISGE + No description available + 0x198 + 32 + 0x00000000 + 0x0000000F + + + TCL_SGE + Task cleared interrupt signal enable +Values: +0x1 (INT_SIG_ENABLE): CQIS.TCL interrupt signal generation is active +0x0 (INT_SIG_DISABLE): CQIS.TCL interrupt signal generation is disabled + 3 + 1 + read-write + + + RED_SGE + Response error detected interrupt signal enable +Values: +0x1 (INT_SIG_ENABLE): CQIS.RED interrupt signal generation is active +0x0 (INT_SIG_DISABLE): CQIS.RED interrupt signal generation is disabled + 2 + 1 + read-write + + + TCC_SGE + Task complete interrupt signal enable +Values: +0x1 (INT_SIG_ENABLE): CQIS.TCC interrupt signal generation is active +0x0 (INT_SIG_DISABLE): CQIS.TCC interrupt signal generation is disabled + 1 + 1 + read-write + + + HAC_SGE + Halt complete interrupt signal enable +Values: +0x1 (INT_SIG_ENABLE): CQIS.HAC interrupt signal generation is active +0x0 (INT_SIG_DISABLE): CQIS.HAC interrupt signal generation is disabled + 0 + 1 + read-write + + + + + CQIC + No description available + 0x19c + 32 + 0x00000000 + 0x80119FFF + + + INTC_EN + Interrupt Coalescing Enable Bit +Values: +0x1 (ENABLE_INT_COALESCING): Interrupt coalescing mechanism is active. Interrupts are counted and timed, and coalesced interrupts are generated +0x0 (DISABLE_INT_COALESCING): Interrupt coalescing mechanism is disabled (Default) + 31 + 1 + read-write + + + INTC_STAT + Interrupt Coalescing Status Bit +This bit indicates to the software whether any tasks (with INT=0) have completed and counted towards interrupt +coalescing (that is, this is set if and only if INTC counter > 0). +Values: +0x1 (INTC_ATLEAST1_COMP): At least one INT0 task completion has been counted (INTC counter > 0) +0x0 (INTC_NO_TASK_COMP): INT0 Task completions have not occurred since last counter reset (INTC counter == 0) + 20 + 1 + read-only + + + INTC_RST + Counter and Timer Reset +When host driver writes 1, the interrupt coalescing timer and counter are reset. +Values: +0x1 (ASSERT_INTC_RESET): Interrupt coalescing timer and counter are reset +0x0 (NO_EFFECT): No Effect + 16 + 1 + write-only + + + INTC_TH_WEN + Interrupt Coalescing Counter Threshold Write Enable +When software writes 1 to this bit, the value INTC_TH is updated with the contents written on the same cycle. +Values: +0x1 (WEN_SET): Sets INTC_TH_WEN +0x0 (WEN_CLR): Clears INTC_TH_WEN + 15 + 1 + write-only + + + INTC_TH + Interrupt Coalescing Counter Threshold filed +Software uses this field to configure the number of task completions (only tasks with INT=0 in the Task Descriptor), which are required in order to generate an interrupt. +Counter Operation: As data transfer tasks with INT=0 complete, they are counted by CQE. +The counter is reset by software during the interrupt service routine. +The counter stops counting when it reaches the value configured in INTC_TH, and generates interrupt. +0x0: Interrupt coalescing feature disabled +0x1: Interrupt coalescing interrupt generated after 1 task when INT=0 completes +0x2: Interrupt coalescing interrupt generated after 2 tasks when INT=0 completes +........ +0x1f: Interrupt coalescing interrupt generated after 31 tasks when INT=0 completes +To write to this field, the INTC_TH_WEN bit must be set during the same write operation. + 8 + 5 + write-only + + + TOUT_VAL_WEN + When software writes 1 to this bit, the value TOUT_VAL is updated with the contents written on the same cycle. +Values: +0x1 (WEN_SET): Sets TOUT_VAL_WEN +0x0 (WEN_CLR): clears TOUT_VAL_WEN + 7 + 1 + write-only + + + TOUT_VAL + Interrupt Coalescing Timeout Value +Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt. +Timer Operation: The timer is reset by software during the interrupt service routine. +It starts running when the first data transfer task with INT=0 is completed, after the timer was reset. +When the timer reaches the value configured in ICTOVAL field, it generates an interrupt and stops. +The timer's unit is equal to 1024 clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. +0x0: Timer is disabled. Timeout-based interrupt is not generated +0x1: Timeout on 01x1024 cycles of timer clock frequency +0x2: Timeout on 02x1024 cycles of timer clock frequency +........ +0x7f: Timeout on 127x1024 cycles of timer clock frequency +In order to write to this field, the TOUT_VAL_WEN bit must +be set at the same write operation. + 0 + 7 + read-write + + + + + CQTDLBA + No description available + 0x1a0 + 32 + 0x00000000 + 0xFFFFFFFF + + + TDLBA + This register stores the LSB bits (31:0) of the byte address of the head of the Task Descriptor List in system memory. +The size of the task descriptor list is 32 * (Task Descriptor size + Transfer Descriptor size) as configured by the host driver. +This address is set on 1 KB boundary. The lower 10 bits of this register are set to 0 by the software and are ignored by CQE + 0 + 32 + read-write + + + + + CQTDBR + No description available + 0x1a8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DBR + The software configures TDLBA and TDLBAU, and enable +CQE in CQCFG before using this register. +Writing 1 to bit n of this register triggers CQE to start processing the task encoded in slot n of the TDL. +Writing 0 by the software does not have any impact on the hardware, and does not change the value of the register bit. +CQE always processes tasks according to the order submitted to the list by CQTDBR write transactions. +CQE processes Data Transfer tasks by reading the Task Descriptor and sending QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) commands to +the device. CQE processes DCMD tasks (in slot #31, when enabled) by reading the Task Descriptor, and generating the command encoded by its index and argument. +The corresponding bit is cleared to 0 by CQE in one of the following events: +A task execution is completed (with success or error). +The task is cleared using CQTCLR register. +All tasks are cleared using CQCTL register. +CQE is disabled using CQCFG register. +Software may initiate multiple tasks at the same time (batch submission) by writing 1 to multiple bits of this register in the same transaction. +In the case of batch submission, CQE processes the tasks in order of the task index, starting with the lowest index. +If one or more tasks in the batch are marked with QBR, the ordering of execution is based on said processing order. + 0 + 32 + read-write + + + + + CQTCN + No description available + 0x1ac + 32 + 0x00000000 + 0xFFFFFFFF + + + TCN + Task Completion Notification +Each of the 32 bits are bit mapped to the 32 tasks. +Bit-N(1): Task-N has completed execution (with success or errors) +Bit-N(0): Task-N has not completed, could be pending or not submitted. +On task completion, software may read this register to know tasks that have completed. After reading this register, +software may clear the relevant bit fields by writing 1 to the corresponding bits. + 0 + 32 + read-write + + + + + CQDQS + No description available + 0x1b0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DQS + Device Queue Status +Each of the 32 bits are bit mapped to the 32 tasks. +Bit-N(1): Device has marked task N as ready for execution +Bit-N(0): Task-N is not ready for execution. This task could be pending in device or not submitted. +Host controller updates this register with response of the Device Queue Status command. + 0 + 32 + read-write + + + + + CQDPT + No description available + 0x1b4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DPT + Device-Pending Tasks +Each of the 32 bits are bit mapped to the 32 tasks. +Bit-N(1): Task-N has been successfully queued into the device and is awaiting execution +Bit-N(0): Task-N is not yet queued. +Bit n of this register is set if and only if QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) were sent for this specific task and if this task has not been executed. +The controller sets this bit after receiving a successful response for CMD45. CQE clears this bit after the task has completed execution. +Software reads this register in the task-discard procedure to determine if the task is queued in the device + 0 + 32 + read-write + + + + + CQTCLR + No description available + 0x1b8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TCLR + Writing 1 to bit n of this register orders CQE to clear a task that the software has previously issued. +This bit can only be written when CQE is in Halt state as indicated in CQCFG register Halt bit. +When software writes 1 to a bit in this register, CQE updates the value to 1, and starts clearing the data structures related to the task. +CQE clears the bit fields (sets a value of 0) in CQTCLR and in CQTDBR once the clear operation is complete. +Software must poll on the CQTCLR until it is leared to verify that a clear operation was done. + 0 + 32 + read-write + + + + + CQSSC1 + No description available + 0x1c0 + 32 + 0x00000000 + 0x000FFFFF + + + SQSCMD_BLK_CNT + This field indicates when SQS CMD is sent while data transfer is in progress. +A value of 'n' indicates that CQE sends status command on the CMD line, during the transfer of data block BLOCK_CNTn, on the data lines, where BLOCK_CNT is the number of blocks in the current transaction. +0x0: SEND_QUEUE_STATUS (CMD13) command is not sent during the transaction. Instead, it is sent only when the data lines are idle. +0x1: SEND_QUEUE_STATUS command is to be sent during the last block of the transaction. +0x2: SEND_QUEUE_STATUS command when last 2 blocks are pending. +0x3: SEND_QUEUE_STATUS command when last 3 blocks are pending. +........ +0xf: SEND_QUEUE_STATUS command when last 15 blocks are pending. +Should be programmed only when CQCFG.CQ_EN is 0 + 16 + 4 + read-write + + + SQSCMD_IDLE_TMR + This field configures the polling period to be used when using periodic SEND_QUEUE_STATUS (CMD13) polling. +Periodic polling is used when tasks are pending in the device, but no data transfer is in progress. +When a SEND_QUEUE_STATUS response indicates that no task is ready for execution, CQE counts the configured time until it issues the next SEND_QUEUE_STATUS. +Timer units are clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. +The minimum value is 0001h (1 clock period) and the maximum value is FFFFh (65535 clock periods). +For example, a CQCAP field value of 0 indicates a 19.2 MHz clock frequency (period = 52.08 ns). +If the setting in CQSSC1.CIT is 1000h, the calculated polling period is 4096*52.08 ns= 213.33 us. +Should be programmed only when CQCFG.CQ_EN is '0' + 0 + 16 + read-write + + + + + CQSSC2 + No description available + 0x1c4 + 32 + 0x00000000 + 0x0000FFFF + + + SQSCMD_RCA + This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_STATUS (CMD13) command argument. +CQE copies this field to bits 31:16 of the argument when transmitting SEND_ QUEUE_STATUS (CMD13) command. + 0 + 16 + read-write + + + + + CQCRDCT + No description available + 0x1c8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DCMD_RESP + This register contains the response of the command generated by the last direct command (DCMD) task that was sent. +Contents of this register are valid only after bit 31 of CQTDBR register is cleared by the controller. + 0 + 32 + read-only + + + + + CQRMEM + No description available + 0x1d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESP_ERR_MASK + The bits of this field are bit mapped to the device response. +This bit is used as an interrupt mask on the device status filed that is received in R1/R1b responses. +1: When a R1/R1b response is received, with a bit i in the device status set, a RED interrupt is generated. +0: When a R1/R1b response is received, bit i in the device status is ignored. +The reset value of this register is set to trigger an interrupt on all "Error" type bits in the device status. +Note: Responses to CMD13 (SQS) encode the QSR so that they are ignored by this logic. + 0 + 32 + read-write + + + + + CQTERRI + No description available + 0x1d4 + 32 + 0x00000000 + 0x1F3F9F3F + + + TRANS_ERR_TASKID + This field captures the ID of the task that was executed and whose data transfer has errors. + 24 + 5 + read-only + + + TRANS_ERR_CMD_INDX + This field captures the index of the command that was executed and whose data transfer has errors. + 16 + 6 + read-only + + + RESP_ERR_FIELDS_VALID + This bit is updated when an error is detected while a command transaction was in progress. +Values: +0x1 (SET): Response-related error is detected. Check contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX fields +0x0 (NOT_SET): Ignore contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX + 15 + 1 + read-only + + + RESP_ERR_TASKID + This field captures the ID of the task which was executed on the command line when the error occurred. + 8 + 5 + read-only + + + RESP_ERR_CMD_INDX + This field captures the index of the command that was executed on the command line when the error occurred + 0 + 6 + read-only + + + + + CQCRI + No description available + 0x1d8 + 32 + 0x00000000 + 0x0000003F + + + CMD_RESP_INDX + Last Command Response index +This field stores the index of the last received command response. Controller updates the value every time a command response is received + 0 + 6 + read-only + + + + + CQCRA + No description available + 0x1dc + 32 + 0x00000000 + 0xFFFFFFFF + + + CMD_RESP_ARG + Last Command Response argument +This field stores the argument of the last received command response. Controller updates the value every time a command response is received. + 0 + 32 + read-only + + + + + MSHC_VER_ID + No description available + 0x500 + 32 + 0x00000000 + 0xFFFFFFFF + + + VER_ID + No description available + 0 + 32 + read-only + + + + + MSHC_VER_TYPE + No description available + 0x504 + 32 + 0x00000000 + 0xFFFFFFFF + + + VER_TYPE + No description available + 0 + 32 + read-only + + + + + EMMC_BOOT_CTRL + No description available + 0x52c + 32 + 0x00000000 + 0xF181070F + + + BOOT_TOUT_CNT + Boot Ack Timeout Counter Value. +This value determines the interval by which boot ack timeout (50 ms) is detected when boot ack is expected during boot operation. +0xF : Reserved +0xE : TMCLK x 2^27 + ............ +0x1 : TMCLK x 2^14 +0x0 : TMCLK x 2^13 + 28 + 4 + read-write + + + BOOT_ACK_ENABLE + Boot Acknowledge Enable +When this bit set, SDXC checks for boot acknowledge start pattern of 0-1-0 during boot operation. This bit is applicable for both mandatory and alternate boot mode. +Values: +0x1 (TRUE): Boot Ack enable +0x0 (FALSE): Boot Ack disable + 24 + 1 + read-write + + + VALIDATE_BOOT + Validate Mandatory Boot Enable bit +This bit is used to validate the MAN_BOOT_EN bit. +Values: +0x1 (TRUE): Validate Mandatory boot enable bit +0x0 (FALSE): Ignore Mandatory boot Enable bit + 23 + 1 + write-only + + + MAN_BOOT_EN + Mandatory Boot Enable +This bit is used to initiate the mandatory boot operation. The application sets this bit along with VALIDATE_BOOT bit. +Writing 0 is ignored. The SDXC clears this bit after the boot transfer is completed or terminated. +Values: +0x1 (MAN_BOOT_EN): Mandatory boot enable +0x0 (MAN_BOOT_DIS): Mandatory boot disable + 16 + 1 + read-write + + + CQE_PREFETCH_DISABLE + Enable or Disable CQE's PREFETCH feature +This field allows Software to disable CQE's data prefetch feature when set to 1. +Values: +0x0 (PREFETCH_ENABLE): CQE can Prefetch data for sucessive WRITE transfers and pipeline sucessive READ transfers +0x1 (PREFETCH_DISABLE): Prefetch for WRITE and Pipeline for READ are disabled + 10 + 1 + read-write + + + CQE_ALGO_SEL + Scheduler algorithm selected for execution +This bit selects the Algorithm used for selecting one of the many ready tasks for execution. +Values: +0x0 (PRI_REORDER_PLUS_FCFS): Priority based reordering with FCFS to resolve equal priority tasks +0x1 (FCFS_ONLY): First come First serve, in the order of DBR rings + 9 + 1 + read-write + + + ENH_STROBE_ENABLE + Enhanced Strobe Enable +This bit instructs SDXC to sample the CMD line using data strobe for HS400 mode. +Values: +0x1 (ENH_STB_FOR_CMD): CMD line is sampled using data strobe for HS400 mode +0x0 (NO_STB_FOR_CMD): CMD line is sampled using cclk_rx for HS400 mode + 8 + 1 + read-write + + + EMMC_RST_N_OE + Output Enable control for EMMC Device Reset signal PAD +control. +This field drived sd_rst_n_oe output of SDXC +Values: +0x1 (ENABLE): sd_rst_n_oe is 1 +0x0 (DISABLE): sd_rst_n_oe is 0 + 3 + 1 + read-write + + + EMMC_RST_N + EMMC Device Reset signal control. +This register field controls the sd_rst_n output of SDXC +Values: +0x1 (RST_DEASSERT): Reset to eMMC device is deasserted +0x0 (RST_ASSERT): Reset to eMMC device asserted (active low) + 2 + 1 + read-write + + + DISABLE_DATA_CRC_CHK + Disable Data CRC Check +This bit controls masking of CRC16 error for Card Write in eMMC mode. +This is useful in bus testing (CMD19) for an eMMC device. In bus testing, an eMMC card does not send CRC status for a block, +which may generate CRC error. This CRC error can be masked using this bit during bus testing. +Values: +0x1 (DISABLE): DATA CRC check is disabled +0x0 (ENABLE): DATA CRC check is enabled + 1 + 1 + read-write + + + CARD_IS_EMMC + eMMC Card present +This bit indicates the type of card connected. An application program this bit based on the card connected to SDXC. +Values: +0x1 (EMMC_CARD): Card connected to SDXC is an eMMC card +0x0 (NON_EMMC_CARD): Card connected to SDXCis a non-eMMC card + 0 + 1 + read-write + + + + + AUTO_TUNING_CTRL + No description available + 0x540 + 32 + 0x00000000 + 0x7F1F0F1F + + + SWIN_TH_VAL + Sampling window threshold value setting +The maximum value that can be set here depends on the length of delayline used for tuning. A delayLine with 32 taps +can use values from 0x0 to 0x1F. +This field is valid only when SWIN_TH_EN is '1'. Should be programmed only when SAMPLE_CLK_SEL is '0' +0x0 : Threshold values is 0x1, windows of length 1 tap and above can be selected as sampling window. +0x1 : Threshold values is 0x2, windows of length 2 taps and above can be selected as sampling window. +0x2 : Threshold values is 0x1, windows of length 3 taps and above can be selected as sampling window. +........ +0x1F : Threshold values is 0x1, windows of length 32 taps and above can be selected as sampling window. + 24 + 7 + read-write + + + POST_CHANGE_DLY + Time taken for phase switching and stable clock output. +Specifies the maximum time (in terms of cclk cycles) that the delay line can take to switch its output phase after a change in tuning_cclk_sel or autotuning_cclk_sel. +Values: +0x0 (LATENCY_LT_1): Less than 1-cycle latency +0x1 (LATENCY_LT_2): Less than 2-cycle latency +0x2 (LATENCY_LT_3): Less than 3-cycle latency +0x3 (LATENCY_LT_4): Less than 4-cycle latency + 19 + 2 + read-write + + + PRE_CHANGE_DLY + Maximum Latency specification between cclk_tx and cclk_rx. +Values: +0x0 (LATENCY_LT_1): Less than 1-cycle latency +0x1 (LATENCY_LT_2): Less than 2-cycle latency +0x2 (LATENCY_LT_3): Less than 3-cycle latency +0x3 (LATENCY_LT_4): Less than 4-cycle latency + 17 + 2 + read-write + + + TUNE_CLK_STOP_EN + Clock stopping control for Tuning and auto-tuning circuit. +When enabled, clock gate control output of SDXC (clk2card_on) is pulled low before changing phase select codes on tuning_cclk_sel and autotuning_cclk_sel. +This effectively stops the Device/Card clock, cclk_rx and also drift_cclk_rx. Changing phase code when clocks are stopped ensures glitch free phase switching. + Set this bit to 0 if the PHY or delayline can guarantee glitch free switching. +Values: +0x1 (ENABLE_CLK_STOPPING): Clocks stopped during phase code change +0x0 (DISABLE_CLK_STOPPING): Clocks not stopped. PHY ensures glitch free phase switching + 16 + 1 + read-write + + + WIN_EDGE_SEL + This field sets the phase for Left and Right edges for drift monitoring. [Left edge offset + Right edge offset] must not be less than total taps of delayLine. +0x0: User selection disabled. Tuning calculated edges are used. +0x1: Right edge Phase is center + 2 stages, Left edge Phase is center - 2 stages. +0x2: Right edge Phase is center + 3 stages, Left edge Phase is center - 3 stagess +... +0xF: Right edge Phase is center + 16 stages, Left edge Phase is center - 16 stages. + 8 + 4 + read-write + + + SW_TUNE_EN + This fields enables software-managed tuning flow. +Values: +0x1 (SW_TUNING_ENABLE): Software-managed tuning enabled. AUTO_TUNING_STAT.CENTER_PH_CODE Field is now writable. +0x0 (SW_TUNING_DISABLE): Software-managed tuning disabled + 4 + 1 + read-write + + + RPT_TUNE_ERR + Framing errors are not generated when executing tuning. +This debug bit allows users to report these errors. +Values: +0x1 (DEBUG_ERRORS): Debug mode for reporting framing errors +0x0 (ERRORS_DISABLED): Default mode where as per SDXC no errors are reported. + 3 + 1 + read-write + + + SWIN_TH_EN + Sampling window Threshold enable +Selects the tuning mode +Field should be programmed only when SAMPLE_CLK_SEL is '0' +Values: +0x1 (THRESHOLD_MODE): Tuning engine selects the first complete sampling window that meets the threshold +set by SWIN_TH_VAL field +0x0 (LARGEST_WIN_MODE): Tuning engine sweeps all taps and settles at the largest window + 2 + 1 + read-write + + + CI_SEL + Selects the interval when the corrected center phase select code can be driven on tuning_cclk_sel output. +Values: +0x0 (WHEN_IN_BLK_GAP): Driven in block gap interval +0x1 (WHEN_IN_IDLE): Driven at the end of the transfer + 1 + 1 + read-write + + + AT_EN + Setting this bit enables Auto tuning engine. This bit is enabled by default when core is configured with mode3 retuning support. +Clear this bit to 0 when core is configured to have Mode3 re-tuning but SW wishes to disable mode3 retuning. +This field should be programmed only when SYS_CTRL.SD_CLK_EN is 0. +Values: +0x1 (AT_ENABLE): AutoTuning is enabled +0x0 (AT_DISABLE): AutoTuning is disabled + 0 + 1 + read-write + + + + + AUTO_TUNING_STAT + No description available + 0x544 + 32 + 0x00000000 + 0x00FFFFFF + + + L_EDGE_PH_CODE + Left Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Left edge of sampling window. + 16 + 8 + read-only + + + R_EDGE_PH_CODE + Right Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Right edge of sampling window. + 8 + 8 + read-only + + + CENTER_PH_CODE + Centered Phase code. Reading this field returns the current value on tuning_cclk_sel output. Setting AUTO_TUNING_CTRL.SW_TUNE_EN enables software to write to this field and its contents are reflected on tuning_cclk_sel + 0 + 8 + read-write + + + + + MISC_CTRL0 + No description available + 0x3000 + 32 + 0x00000000 + 0x10020FFF + + + CARDCLK_INV_EN + set to invert card_clk, for slow speed card to meet 5ns setup timing. +May cause glitch on clock, should be set before enable clk(in core cfg) + 28 + 1 + read-write + + + PAD_CLK_SEL_B + set to use internal clock directly, may have timing issue; +clr to use clock loopback from pad. + 17 + 1 + read-write + + + FREQ_SEL_SW_EN + set to use FREQ_SEL_SW as card clock divider; +clear to use core logic as clock divider. + 11 + 1 + read-write + + + TMCLK_EN + set to force enable tmclk; +clear to use core signal intclk_en to control it + 10 + 1 + read-write + + + FREQ_SEL_SW + software card clock divider, it will be used only when FREQ_SEL_SW_EN is set + 0 + 10 + read-write + + + + + MISC_CTRL1 + No description available + 0x3004 + 32 + 0x00000000 + 0xB3F3F000 + + + CARD_ACTIVE + SW write 1 to start card clock delay counter(delay time is configed by CARD_ACTIVE_PERIOD_SEL). +When counter finished, this bit will be cleared by hardware. +Write 1 when this bit is 1 will cause unknown result(actually no use except write at exact finish time) + 31 + 1 + read-write + + + CARD_ACTIVE_PERIOD_SEL + card clock delay config. +00 for 100 cycle; 01 for 74 cycle; 10 for 128 cycle; 11 for 256 cycle + 28 + 2 + read-write + + + CARDCLK_DLYSEL + for card clock DLL, default 0 + 20 + 6 + read-write + + + STROBE_DLYSEL + for strobe DLL, default 7taps(1ns) + 12 + 6 + read-write + + + + + + + SDXC1 + SDXC1 + SDXC + 0xf1134000 + + + DDRCTL + DDRCTL + DDRCTL + 0xf3010000 + + 0x0 + 0xf34 + registers + + + + MSTR + Description: Master Register + 0x0 + 32 + 0x03040001 + 0x0F0FB601 + + + ACTIVE_RANKS + Description: Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations, only bits[25:24] are present. +1 - populated +0 - unpopulated +LSB is the lowest rank number. +For 2 ranks following combinations are legal: +01 - One rank +11 - Two ranks +Others - Reserved. +For 4 ranks following combinations are legal: +0001 - One rank +0011 - Two ranks +1111 - Four ranks +Value After Reset: "(MEMC_NUM_RANKS==4) ? 0xF +:((MEMC_NUM_RANKS==2) ? 0x3 : 0x1)" +Exists: MEMC_NUM_RANKS>1 + 24 + 4 + read-write + + + BURST_RDWR + Description: SDRAM burst length used: +0001 - Burst length of 2 (only supported for mDDR) +0010 - Burst length of 4 +0100 - Burst length of 8 +1000 - Burst length of 16 (only supported for mDDR and LPDDR2) +All other values are reserved. +This controls the burst size used to access the SDRAM. This must match the burst length mode register setting in the SDRAM. Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGTH is 8. +Value After Reset: 0x4 +Exists: Always + 16 + 4 + read-write + + + DLL_OFF_MODE + Description: Set to 1 when uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation. +Set to 0 to put uMCTL2 and DRAM in DLL-on mode for normal frequency operation. +Value After Reset: 0x0 +Exists: MEMC_DDR3_OR_4==1 + 15 + 1 + read-write + + + DATA_BUS_WIDTH + Description: Selects proportion of DQ bus width that is used by the SDRAM +00 - Full DQ bus width to SDRAM +01 - Half DQ bus width to SDRAM +10 - Quarter DQ bus width to SDRAM +11 - Reserved. +Note that half bus width mode is only supported when the SDRAM bus width is a multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus width (excluding any ECC width). +Value After Reset: 0x0 +Exists: Always + 12 + 2 + read-write + + + EN_2T_TIMING_MODE + Description: If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command +Note: 2T timing is not supported in LPDDR2/LPDDR3 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set +Note: 2T timing is not supported in DDR4 geardown mode. +Value After Reset: 0x0 +Exists: MEMC_CMD_RTN2IDLE==0 + 10 + 1 + read-write + + + BURSTCHOP + Description: When set, enable burst-chop in DDR3/DDR4. This is only supported in full bus width mode (MSTR.data_bus_width = 00). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), burst chop is not supported, and this bit must be set to '0' +Value After Reset: 0x0 +Exists: MEMC_DDR3==1 || MEMC_DDR4==1 + 9 + 1 + read-write + + + DDR3 + Description: Select DDR3 SDRAM +1 - DDR3 SDRAM device in use +0 - non-DDR3 SDRAM device in use Only present in designs that support DDR3. +Value After Reset: "(MEMC_DDR3_EN==1) ? 0x1 : 0x0" +Exists: MEMC_DDR3==1 + 0 + 1 + read-write + + + + + STAT + Description: Operating Mode Status Register + 0x4 + 32 + 0x00000000 + 0x00000037 + + + SELFREF_TYPE + Description: Flags if Self Refresh is entered and if it was under Automatic Self Refresh control only or not. +00 - SDRAM is not in Self Refresh +11 - SDRAM is in Self Refresh and Self Refresh was caused by Automatic Self Refresh only +10 - SDRAM is in Self Refresh and Self Refresh was not caused solely under Automatic Self Refresh control. It could have been caused by Hardware Low Power Interface and/or Software (reg_ddrc_selfref_sw). +Value After Reset: 0x0 +Exists: Always + 4 + 2 + read-only + + + OPERATING_MODE + Description: Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/DDR4 support and 2-bits in all other configurations. +non-mDDR/LPDDR2/LPDDR3 and non-DDR4 designs: +00 - Init +01 - Normal +10 - Power-down +11 - Self refresh +mDDR/LPDDR2/LPDDR3 or DDR4 designs: +000 - Init +001 - Normal +010 - Power-down +011 - Self refresh +1XX - Deep power-down / Maximum Power Saving Mode +Value After Reset: 0x0 +Exists: Always + 0 + 3 + read-only + + + + + MRCTRL0 + Description: Mode Register Read/Write Control Register 0 + 0x10 + 32 + 0x00000030 + 0x8000F0F0 + + + MR_WR + Description: Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the uMCTL2 automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power- down or MPSM operating modes. +Value After Reset: 0x0 +Exists: Always + 31 + 1 + read-write + + + MR_ADDR + Description: Address of the mode register that is to be written to. +0000 - MR0 +0001 - MR1 +0010 - MR2 +0011 - MR3 +0100 - MR4 +0101 - MR5 +0110 - MR6 +0111 - MR7 +Don't Care for LPDDR2/LPDDR3 (see MRCTRL1.mr_data for mode register addressing in LPDDR2/LPDDR3) +This signal is also used for writing to control words of RDIMMs. In that case, it corresponds to the bank address bits sent to the RDIMM +In case of DDR4, the bit[3:2] corresponds to the bank group bits. Therefore, the bit[3] as well as the bit[2:0] must be set to an appropriate value which is considered both the Address Mirroring of UDIMMs/RDIMMs and the Output Inversion of RDIMMs. +Value After Reset: 0x0 +Exists: Always + 12 + 4 + read-write + + + MR_RANK + Description: Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs which implement address mirroring, it may be necessary to access ranks individually. +Examples (assume uMCTL2 is configured for 4 ranks): +0x1 - select rank 0 only +0x2 - select rank 1 only +0x5 - select ranks 0 and 2 +0xA - select ranks 1 and 3 +0xF - select ranks 0, 1, 2 and 3 +Value After Reset: "(MEMC_NUM_RANKS==4) ? 0xF +:((MEMC_NUM_RANKS==2) ? 0x3 : 0x1)" +Exists: Always + 4 + 4 + read-write + + + + + MRCTRL1 + Description: Mode Register Read/Write Control Register 1 + 0x14 + 32 + 0x00000000 + 0x0003FFFF + + + MR_DATA + Description: Mode register write data for all non- LPDDR2/non-LPDDR3 modes. +For LPDDR2/LPDDR3, MRCTRL1[15:0] are interpreted as [15:8] MR Address and [7:0] MR data for writes, don't care for reads. This is 18-bits wide in configurations with DDR4 support and 16-bits in all other configurations. +Value After Reset: 0x0 +Exists: Always + 0 + 18 + read-write + + + + + MRSTAT + Description: Mode Register Read/Write Status Register + 0x18 + 32 + 0x00000000 + 0x00000001 + + + MR_WR_BUSY + Description: The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when 'MRSTAT.mr_wr_busy' is high. +0 - Indicates that the SoC core can initiate a mode register write operation +1 - Indicates that mode register write operation is in progress +Value After Reset: 0x0 +Exists: Always + 0 + 1 + read-only + + + + + PWRCTL + Description: Low Power Control Register + 0x30 + 32 + 0x00000000 + 0x0000002B + + + SELFREF_SW + Description: A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. +1 - Software Entry to Self Refresh +0 - Software Exit from Self Refresh +Value After Reset: 0x0 +Exists: Always + 5 + 1 + read-write + + + EN_DFI_DRAM_CLK_DISABLE + Description: Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. +If set to 0, dfi_dram_clk_disable is never asserted. Assertion of dfi_dram_clk_disable is as follows: +In DDR2/DDR3, can only be asserted in Self Refresh. In DDR4, can be asserted in following: +in Self Refresh. +in Maximum Power Saving Mode +In mDDR/LPDDR2/LPDDR3, can be asserted in following: +in Self Refresh +in Power Down +in Deep Power Down +during Normal operation (Clock Stop) +Value After Reset: 0x0 +Exists: Always + 3 + 1 + read-write + + + POWERDOWN_EN + Description: If true then the uMCTL2 goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). +This register bit may be re-programmed during the course of normal operation. +Value After Reset: 0x0 +Exists: Always + 1 + 1 + read-write + + + SELFREF_EN + Description: If true then the uMCTL2 puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re- programmed during the course of normal operation. +Value After Reset: 0x0 +Exists: Always + 0 + 1 + read-write + + + + + PWRTMG + Description: Low Power Timing Register + 0x34 + 32 + 0x00400010 + 0x00FF001F + + + SELFREF_TO_X32 + Description: After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into Self Refresh. This must be enabled in the PWRCTL.selfref_en. +Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. +Value After Reset: 0x40 +Exists: Always + 16 + 8 + read-write + + + POWERDOWN_TO_X32 + Description: After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into power-down. This must be enabled in the PWRCTL.powerdown_en. +Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY. +Value After Reset: 0x10 +Exists: Always + 0 + 5 + read-write + + + + + HWLPCTL + Description: Hardware Low Power Control Register + 0x38 + 32 + 0x00000003 + 0x0FFF0003 + + + HW_LP_IDLE_X32 + Description: Hardware idle period. The cactive_ddrc output is driven low if the system is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The hardware idle function is disabled when hw_lp_idle_x32=0. +Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. +Value After Reset: 0x0 +Exists: Always + 16 + 12 + read-write + + + HW_LP_EXIT_IDLE_EN + Description: When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it will not cause exit of Self-Refresh that was caused by Hardware Low Power Interface and/or Software (PWRCTL.selfref_sw). +Value After Reset: 0x1 +Exists: Always + 1 + 1 + read-write + + + HW_LP_EN + Description: Enable for Hardware Low Power Interface. +Value After Reset: 0x1 +Exists: Always + 0 + 1 + read-write + + + + + RFSHCTL0 + Description: Refresh Control Register 0 + 0x50 + 32 + 0x00210000 + 0x00F1F1F0 + + + REFRESH_MARGIN + Description: Threshold value in number of clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3, internally used t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_nom_x32 will be equal to RFSHTMG.t_rfc_nom_x32. +Unit: Multiples of 32 clocks. Value After Reset: 0x2 Exists: Always + 20 + 4 + read-write + + + REFRESH_TO_X32 + Description: If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the uMCTL2. +FOR PERFORMANCE ONLY. +Value After Reset: 0x10 +Exists: Always + 12 + 5 + read-write + + + REFRESH_BURST + Description: The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. +0 - single refresh +1 - burst-of-2 refresh +7 - burst-of-8 refresh +For information on burst refresh feature refer to section 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. +For DDR2/3, the refresh is always per-rank and not per- bank. The rank refresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granuarity feature, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated updates, care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiated update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY- initiated update is complete. +Value After Reset: 0x0 +Exists: Always + 4 + 5 + read-write + + + + + RFSHCTL1 + Description: Refresh Control Register 1 + 0x54 + 32 + 0x00000000 + 0x0FFF0FFF + + + REFRESH_TIMER1_START_VALUE_X32 + Description: Refresh timer start for rank 1 (only present in multi-rank configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to proceed. This is explained in Refresh Controls section of architecture chapter. +Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. +Value After Reset: 0x0 +Exists: MEMC_NUM_RANKS>1 + 16 + 12 + read-write + + + REFRESH_TIMER0_START_VALUE_X32 + Description: Refresh timer start for rank 0 (only present in multi-rank configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to proceed. This is explained in Refresh Controls section of architecture chapter. +Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. +Value After Reset: 0x0 +Exists: MEMC_NUM_RANKS>1 + 0 + 12 + read-write + + + + + RFSHCTL3 + Description: Refresh Control Register 0 + 0x60 + 32 + 0x00000000 + 0x00000003 + + + REFRESH_UPDATE_LEVEL + Description: Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. +The value is automatically updated when exiting soft reset, so it does not need to be toggled initially. +Value After Reset: 0x0 +Exists: Always + 1 + 1 + read-write + + + DIS_AUTO_REFRESH + Description: When '1', disable auto-refresh generated by the uMCTL2. When auto-refresh is disabled, the SoC core must generate refreshes using the registers reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. +When dis_auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the uMCTL2. +If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto- refresh is not supported, and this bit must be set to '0'. +This register field is changeable on the fly. +Value After Reset: 0x0 +Exists: Always + 0 + 1 + read-write + + + + + RFSHTMG + Description: Refresh Timing Register + 0x64 + 32 + 0x0062008C + 0x0FFF01FF + + + T_RFC_NOM_X32 + Description: tREFI: Average time interval between refreshes per rank (specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2 and LPDDR3). +For LPDDR2/LPDDR3: +if using all-bank refreshes (RFSHCTL0.per_bank_refresh += 0), this register should be set to tREFIab +if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should be set to tREFIpb +For configurations with MEMC_FREQ_RATIO=2, program this to (tREFI/2), no rounding up. +In DDR4 mode, tREFI value is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value programmed in the refresh mode register. +Note that RFSHTMG.t_rfc_nom_x32 * 32 must be greater than RFSHTMG.t_rfc_min. Unit: Multiples of 32 clocks. +Value After Reset: 0x62 +Exists: Always + 16 + 12 + read-write + + + T_RFC_MIN + Description: tRFC (min): Minimum time from refresh to refresh or activate. +For LPDDR2/LPDDR3: +if using all-bank refreshes (RFSHCTL0.per_bank_refresh += 0), this register should be set to tRFCab +if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should be set to tRFCpb +For configurations with MEMC_FREQ_RATIO=2, program this to tRFC(min)/2 and round up to next integer value. +In DDR4 mode, tRFC(min) value is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the appropriate value from the spec based on the 'refresh_mode' and the device density that is used. +Unit: Clocks. +Value After Reset: 0x8c +Exists: Always + 0 + 9 + read-write + + + + + ECCUADDR0 + Description: ECC Uncorrected Error Address Register 0 + 0xa4 + 32 + 0x00000000 + 0x0303FFFF + + + ECC_UNCORR_RANK + Description: Rank number of a read resulting in an uncorrected ECC error +Value After Reset: 0x0 +Exists: MEMC_NUM_RANKS>1 + 24 + 2 + read-only + + + ECC_UNCORR_ROW + Description: Page/row number of a read resulting in an uncorrected ECC error. This is 18-bits wide in configurations with DDR4 support and 16-bits in all other configurations. +Value After Reset: 0x0 +Exists: Always + 0 + 18 + read-only + + + + + CRCPARCTL0 + Description: CRC Parity Control Register0 + 0xc0 + 32 + 0x00000000 + 0x00000007 + + + DFI_ALERT_ERR_CNT_CLR + Description: DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit will clear the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the uMCTL2 automatically clears this bit. +Value After Reset: 0x0 +Exists: Always + 2 + 1 + read-write + + + DFI_ALERT_ERR_INT_CLR + Description: Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int will be cleared. When the clear operation is complete, the uMCTL2 automatically clears this bit. +Value After Reset: 0x0 +Exists: Always + 1 + 1 + read-write + + + DFI_ALERT_ERR_INT_EN + Description: Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input will result in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. +Value After Reset: 0x0 +Exists: Always + 0 + 1 + read-write + + + + + CRCPARSTAT + Description: CRC Parity Status Register + 0xcc + 32 + 0x00000000 + 0x0001FFFF + + + DFI_ALERT_ERR_INT + Description: DFI alert error interrupt. +If a parity/CRC error is detected on dfi_alert_n, and the interrupt is enabled by CRCPARCTL0.dfi_alert_err_int_en, this interrupt bit will be set. It will remain set until cleared by CRCPARCTL0.dfi_alert_err_int_clr +Value After Reset: 0x0 +Exists: Always + 16 + 1 + read-only + + + DFI_ALERT_ERR_CNT + Description: DFI alert error count. +If a parity/CRC error is detected on dfi_alert_n, this counter be incremented. This is independent of the setting of CRCPARCTL0.dfi_alert_err_int_en. It will saturate at 0xFFFF, and can be cleared by asserting CRCPARCTL0.dfi_alert_err_cnt_clr. +Value After Reset: 0x0 +Exists: Always + 0 + 16 + read-only + + + + + INIT0 + Description: SDRAM Initialization Register 0 + 0xd0 + 32 + 0x0002004E + 0xC3FF03FF + + + SKIP_DRAM_INIT + Description: If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed +00 - SDRAM Initialization routine is run after power-up +01 - SDRAM Initialization routine is skipped after power- up. Controller starts up in Normal Mode +11 - SDRAM Initialization routine is skipped after power- up. Controller starts up in Self-refresh Mode +10 - SDRAM Initialization routine is run after power-up. +Value After Reset: 0x0 +Exists: Always + 30 + 2 + read-write + + + POST_CKE_X1024 + Description: Cycles to wait after driving CKE high to start the SDRAM initialization sequence. +Unit: 1024 clocks. +DDR2 typically requires a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. +LPDDR2/LPDDR3 typically requires this to be programmed for a delay of 200 us. +For configurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it up to next integer value. +Value After Reset: 0x2 +Exists: Always + 16 + 10 + read-write + + + PRE_CKE_X1024 + Description: Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. +Unit: 1024 clock cycles. +DDR2 specifications typically require this to be programmed for a delay of >= 200 us. +LPDDR2/LPDDR3: tINIT1 of 100 ns (min) +For configurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it up to next integer value. +Value After Reset: 0x4e +Exists: Always + 0 + 10 + read-write + + + + + INIT1 + Description: SDRAM Initialization Register 1 + 0xd4 + 32 + 0x00000000 + 0x00FF7F0F + + + DRAM_RSTN_X1024 + Description: Number of cycles to assert SDRAM reset signal during init sequence. +This is only present for designs supporting DDR3/DDR4 devices. For use with a Synopsys DDR PHY, this should be set to a minimum of 1 +Value After Reset: 0x0 +Exists: MEMC_DDR3==1 || MEMC_DDR4==1 + 16 + 8 + read-write + + + FINAL_WAIT_X32 + Description: Cycles to wait after completing the SDRAM initialization sequence before starting the dynamic scheduler. +Unit: Counts of a global timer that pulses every 32 clock cycles. +There is no known specific requirement for this; it may be set to zero. +Value After Reset: 0x0 +Exists: Always + 8 + 7 + read-write + + + PRE_OCD_X32 + Description: Wait period before driving the OCD complete command to SDRAM. +Unit: Counts of a global timer that pulses every 32 clock cycles. +There is no known specific requirement for this; it may be set to zero. +Value After Reset: 0x0 +Exists: Always + 0 + 4 + read-write + + + + + INIT3 + Description: SDRAM Initialization Register 3 + 0xdc + 32 + 0x00000510 + 0xFFFFFFFF + + + MR + Description: DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately. +DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. +LPDDR2/LPDDR3 - Value to write to MR1 register +Value After Reset: 0x0 +Exists: Always + 16 + 16 + read-write + + + EMR + Description: DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those bits appropriately. +DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, this bit is set appropriately by the uMCTL2 during write leveling. +mDDR: Value to write to EMR register. LPDDR2/LPDDR3 - Value to write to MR2 register Value After Reset: 0x510 +Exists: Always + 0 + 16 + read-write + + + + + INIT4 + Description: SDRAM Initialization Register 4 + 0xe0 + 32 + 0x00000000 + 0xFFFFFFFF + + + EMR2 + Description: DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3: Value to write to MR3 register mDDR: Unused +Value After Reset: 0x0 +Exists: Always + 16 + 16 + read-write + + + EMR3 + Description: DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused +Value After Reset: 0x0 +Exists: Always + 0 + 16 + read-write + + + + + INIT5 + Description: SDRAM Initialization Register 5 + 0xe4 + 32 + 0x00100000 + 0x00FF0000 + + + DEV_ZQINIT_X32 + Description: ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. +Unit: 32 clock cycles. +DDR3 typically requires 512 clocks. DDR4 requires 1024 clocks. +LPDDR2/LPDDR3 requires 1 us. +Value After Reset: 0x10 +Exists: MEMC_DDR3==1 || MEMC_DDR4 == 1 || MEMC_LPDDR2==1 + 16 + 8 + read-write + + + + + DIMMCTL + Description: DIMM Control Register + 0xf0 + 32 + 0x00000000 + 0x00000003 + + + DIMM_ADDR_MIRR_EN + Description: Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM implementations). +Some UDIMMs and DDR4 RDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), +(BG0, BG1) for the DDR4. Setting this bit ensures that, for mode register accesses during the automatic initialization routine, these bits are swapped within the uMCTL2 to compensate for this UDIMM/RDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM, they are swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. +Note: This has no effect on the address of any other memory accesses, or of software-driven mode register accesses. +This is not supported for mDDR, LPDDR2 or LPDDR3 SDRAMs. +Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid, hence dimm_dis_bg_mirroring register must be set to 1. +1 - For odd ranks, implement address mirroring for MRS commands to during initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM implements address mirroring) +0 - Do not implement address mirroring +Value After Reset: 0x0 +Exists: Always + 1 + 1 + read-write + + + DIMM_STAGGER_CS_EN + Description: Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIMM implementations only). This is not supported for DDR4, mDDR, LPDDR2 or LPDDR3 SDRAMs. +1 - Stagger accesses to even and odd ranks +0 - Do not stagger accesses +Value After Reset: 0x0 +Exists: Always + 0 + 1 + read-write + + + + + RANKCTL + Description: Rank Control Register + 0xf4 + 32 + 0x0000066F + 0x00000FFF + + + DIFF_RANK_WR_GAP + Description: Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive writes to different ranks. +This is used to switch the delays in the PHY to match the rank requirements. +The value programmed in this register takes care of the ODT switch off timing requirement when switching ranks during writes. +For configurations with MEMC_FREQ_RATIO=2, program this to (N/2) and round it up to the next integer value. N is value required by PHY, in terms of PHY clocks. +Value After Reset: 0x6 +Exists: MEMC_NUM_RANKS>1 + 8 + 4 + read-write + + + DIFF_RANK_RD_GAP + Description: Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive reads to different ranks. +This is used to switch the delays in the PHY to match the rank requirements. +The value programmed in this register takes care of the ODT switch off timing requirement when switching ranks during reads. +For configurations with MEMC_FREQ_RATIO=2, program this to (N/2) and round it up to the next integer value. N is value required by PHY, in terms of PHY clocks. +Value After Reset: 0x6 +Exists: MEMC_NUM_RANKS>1 + 4 + 4 + read-write + + + MAX_RANK_RD + Description: Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to different ranks require additional gap +dictated by the register RANKCTL.diff_rank_rd_gap. This is +to avoid possible data bus contention as well as to give PHY enough time to switch the delay when changing ranks. The uMCTL2 arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there are few clock cycles (determined by the value on diff_rank_rd_gap register) in which only reads from the same rank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. +This parameter represents the maximum number of reads that can be scheduled consecutively to the same rank. After this number is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness. +This feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on the same rank as long as commands are available for it. +Minimum programmable value is 0 (feature disabled) and maximum programmable value is 0xF. +Feature limitation: max_rank_rd feature works as described only in the mode in which one command at the DDRC input results in one DFI command at the output. An example of this mode is: BL8 hardware configuration (MEMC_BURST_LENGTH=8) and Full bus width mode (MSTR.data_bus_width=2'b00) and BL8 mode of operation (MSTR.burst_rdwr=4'b0100). In modes where single HIF command results in multiple DFI commands (eg: Half Bus Width, BL4 etc.), the same rank commands would be serviced for as long as they are available, which is equivalent to this feature being disabled. +FOR PERFORMANCE ONLY. +Value After Reset: 0xf +Exists: MEMC_NUM_RANKS>1 + 0 + 4 + read-write + + + + + DRAMTMG0 + Description: SDRAM Timing Register 0 + 0x100 + 32 + 0x0F101B0F + 0x7F3F7F3F + + + WR2PRE + Description: Minimum time between write and precharge to same bank. +Unit: Clocks +Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower frequencies where: +WL = write latency +BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. +tWR = Write recovery time. This comes directly from the SDRAM specification. +Add one extra cycle for LPDDR2/LPDDR3 for this parameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. +For configurations with MEMC_FREQ_RATIO=2, 2T mode, divide the above value by 2 and add 1. No rounding up. +Value After Reset: 0xf +Exists: Always + 24 + 7 + read-write + + + T_FAW + Description: tFAW Valid only when 8 or more banks(or banks x bank groups) are present. +In 8-bank design, at most 4 banks must be activated in a rolling window of tFAW cycles. +For configurations with MEMC_FREQ_RATIO=2, program this to (tFAW/2) and round up to next integer value. +In a 4-bank design, set this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. +Unit: Clocks +Value After Reset: 0x10 +Exists: Always + 16 + 6 + read-write + + + T_RAS_MAX + Description: tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open +Minimum value of this register is 1. Zero is invalid. +For configurations with MEMC_FREQ_RATIO=2, program this to (tRAS(max)-1)/2. No rounding up. +Unit: Multiples of 1024 clocks. Value After Reset: 0x1b Exists: Always + 8 + 7 + read-write + + + T_RAS_MIN + Description: tRAS(min): Minimum time between activate and precharge to the same bank. +For configurations with MEMC_FREQ_RATIO=2, 1T mode, program this to tRAS(min)/2. No rounding up. +For configurations with MEMC_FREQ_RATIO=2, 2T mode, program this to (tRAS(min)/2 + 1). No rounding up of the division operation. +Unit: Clocks +Value After Reset: 0xf +Exists: Always + 0 + 6 + read-write + + + + + DRAMTMG1 + Description: SDRAM Timing Register 1 + 0x104 + 32 + 0x00080414 + 0x001F1F7F + + + T_XP + Description: tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. +If C/A parity for DDR4 is used, set to (tXP+PL) instead. For configurations with MEMC_FREQ_RATIO=2, program this to (tXP/2) and round it up to the next integer value. +Units: Clocks +Value After Reset: 0x8 +Exists: Always + 16 + 5 + read-write + + + RD2PRE + Description: tRTP: Minimum time from read to precharge of same bank. +DDR2: tAL + BL/2 + max(tRTP, 2) - 2 +DDR3: tAL + max (tRTP, 4) +DDR4: Max of following two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. +mDDR: BL/2 +LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. +LPDDR3: BL/2 + max(tRTP,4) - 4 +For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. +For configurations with MEMC_FREQ_RATIO=2, 2T mode, divide the above value by 2 and add 1. No rounding up of division operation. +Unit: Clocks. +Value After Reset: 0x4 +Exists: Always + 8 + 5 + read-write + + + T_RC + Description: tRC: Minimum time between activates to same bank. +For configurations with MEMC_FREQ_RATIO=2, program this to (tRC/2) and round up to next integer value. +Unit: Clocks. +Value After Reset: 0x14 +Exists: Always + 0 + 7 + read-write + + + + + DRAMTMG2 + Description: SDRAM Timing Register 2 + 0x108 + 32 + 0x0000060D + 0x00001F3F + + + RD2WR + Description: DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL +LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL. +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. +Unit: Clocks. Where: +WL = write latency +BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM +RL = read latency = CAS latency +WR_PREAMBLE = write preamble. This is unique to DDR4. +For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer. +Value After Reset: 0x6 +Exists: Always + 8 + 5 + read-write + + + WR2RD + Description: DDR4: WL + BL/2 + tWTR_L Others: WL + BL/2 + tWTR +In DDR4, minimum time from write command to read command for same bank group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and global constraints. +Unit: Clocks. Where: +WL = write latency +BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM +tWTR_L = internal write to read command delay for same bank group. This comes directly from the SDRAM specification. +tWTR = internal write to read command delay. This comes directly from the SDRAM specification. +Add one extra cycle for LPDDR2/LPDDR3 operation. +For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer. +Value After Reset: 0xd +Exists: Always + 0 + 6 + read-write + + + + + DRAMTMG3 + Description: SDRAM Timing Register 3 + 0x10c + 32 + 0x0000400C + 0x0003F3FF + + + T_MRD + Description: tMRD: Cycles between load mode commands. If MEMC_DDR3_OR_4 = 0, this parameter is also used to define the cycles between load mode command and following non-load mode command. +For configurations with MEMC_FREQ_RATIO=2, program this to (tMRD/2) and round it up to the next integer value. +If C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead +Value After Reset: 0x4 +Exists: Always + 12 + 6 + read-write + + + T_MOD + Description: tMOD: Present if MEMC_DDR3_OR_4 = 1. Cycles between load mode command and following non-load mode command. This is required to be programmed even when a design that supports DDR3/4 is running in DDR2 mode. +If C/A parity for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead +Set to tMOD if MEMC_FREQ_RATIO=1, or tMOD/2 (rounded up to next integer) if MEMC_FREQ_RATIO=2. Note that if using RDIMM, depending on the PHY, it may be necessary to use a value of tMOD + 1 or (tMOD + 1)/2 to compensate for the extra cycle of latency applied to mode register writes by the RDIMM chip +Value After Reset: "(MEMC_DDR3_EN==1 || MEMC_DDR4_EN==1 ) ? 0xc : 0x0" +Exists: MEMC_DDR3==1 || MEMC_DDR4==1 + 0 + 10 + read-write + + + + + DRAMTMG4 + Description: SDRAM Timing Register 4 + 0x110 + 32 + 0x05040405 + 0x1F070F1F + + + T_RCD + Description: tRCD - tAL: Minimum time from activate to read or write command to same bank. +For configurations with MEMC_FREQ_RATIO=2, program this to ((tRCD - tAL)/2) and round it up to the next integer value. +Minimum value allowed for this register is 1, which implies minimum (tRCD - tAL) value to be 2 in configurations with MEMC_FREQ_RATIO=2. +Unit: Clocks. +Value After Reset: 0x5 +Exists: Always + 24 + 5 + read-write + + + T_CCD + Description: DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum time between two reads +or two writes. +For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. +Unit: clocks. +Value After Reset: 0x4 +Exists: Always + 16 + 3 + read-write + + + T_RRD + Description: DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. Others: tRRD: Minimum time between activates from bank +"a" to bank "b" +For configurations with MEMC_FREQ_RATIO=2, program this to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. +Unit: Clocks. +Value After Reset: 0x4 +Exists: Always + 8 + 4 + read-write + + + T_RP + Description: tRP: Minimum time from precharge to activate of same bank. +For configurations with MEMC_FREQ_RATIO=2, program this to (tRP/2 + 1). No round up of the fraction. +Unit: Clocks. +Value After Reset: 0x5 +Exists: Always + 0 + 5 + read-write + + + + + DRAMTMG5 + Description: SDRAM Timing Register 5 + 0x114 + 32 + 0x05050403 + 0x0F0F3F1F + + + T_CKSRX + Description: This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. +Recommended settings: +mDDR: 1 +LPDDR2: 2 +LPDDR3: 2 +DDR2: 1 +DDR3: tCKSRX +DDR4: tCKSRX +For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next integer. +Value After Reset: 0x5 +Exists: Always + 24 + 4 + read-write + + + T_CKSRE + Description: This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. +Recommended settings: +mDDR: 0 +LPDDR2: 2 +LPDDR3: 2 +DDR2: 1 +DDR3: max (10 ns, 5 tCK) +DDR4: max (10 ns, 5 tCK) +For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next integer. +Value After Reset: 0x5 +Exists: Always + 16 + 4 + read-write + + + T_CKESR + Description: Minimum CKE low width for Self refresh entry to exit timing im memory clock cycles. +Recommended settings: +mDDR: tRFC +LPDDR2: tCKESR +LPDDR3: tCKESR +DDR2: tCKE +DDR3: tCKE + 1 +DDR4: tCKE + 1 +For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next integer. +Value After Reset: 0x4 +Exists: Always + 8 + 6 + read-write + + + T_CKE + Description: Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. +LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR +Non-LPDDR2/non-LPDDR3 designs: Set this to tCKE value. +For configurations with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and round it up to the next integer value. +Unit: Clocks. +Value After Reset: 0x3 +Exists: Always + 0 + 5 + read-write + + + + + DRAMTMG8 + Description: SDRAM Timing Register 8 + 0x120 + 32 + 0x00004405 + 0x00007F7F + + + T_XS_DLL_X32 + Description: tXSDLL: Exit Self Refresh to commands requiring a locked DLL. +For configurations with MEMC_FREQ_RATIO=2, program this to the above value divided by 2 and round up to next integer value. +Unit: Multiples of 32 clocks. +Note: In LPDDR2/LPDDR3/Mobile DDR mode, t_xs_x32 and t_xs_dll_x32 must be set the same values derived from tXSR. +Value After Reset: 0x44 +Exists: Always + 8 + 7 + read-write + + + T_XS_X32 + Description: tXS: Exit Self Refresh to commands not requiring a locked DLL. +For configurations with MEMC_FREQ_RATIO=2, program this to the above value divided by 2 and round up to next integer value. +Unit: Multiples of 32 clocks. +Note: In LPDDR2/LPDDR3/Mobile DDR mode, t_xs_x32 and t_xs_dll_x32 must be set the same values derived from tXSR. +Value After Reset: 0x5 +Exists: Always + 0 + 7 + read-write + + + + + ZQCTL0 + Description: ZQ Control Register 0 + 0x180 + 32 + 0x02000040 + 0xE3FF03FF + + + DIS_AUTO_ZQ + Description: +1 - Disable uMCTL2 generation of ZQCS command. Register reg_ddrc_zq_calib_short can be used instead to control ZQ calibration commands. +0 - Internally generate ZQCS commands based on ZQCTL1.t_zq_short_interval_x1024. +This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 devices. +Value After Reset: 0x0 +Exists: MEMC_DDR3==1 || MEMC_DDR4==1 || MEMC_LPDDR2==1 + 31 + 1 + read-write + + + DIS_SRX_ZQCL + Description: +1 - Disable issuing of ZQCL command at Self-Refresh exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 mode. +0 - Enable issuing of ZQCL command at Self-Refresh exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 mode. +This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 devices. +Value After Reset: 0x0 +Exists: MEMC_DDR3==1 || MEMC_DDR4==1 || MEMC_LPDDR2==1 + 30 + 1 + read-write + + + ZQ_RESISTOR_SHARED + Description: +1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS timing met between commands so that commands to different ranks do not overlap. +0 - ZQ resistor is not shared. +This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 devices. +Value After Reset: 0x0 +Exists: MEMC_DDR3==1 || MEMC_DDR4==1 || MEMC_LPDDR2==1 + 29 + 1 + read-write + + + T_ZQ_LONG_NOP + Description: tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to SDRAM. +For configurations with MEMC_FREQ_RATIO=2: DDR3/DDR4: program this to tZQoper/2 and round it up to the next integer value. +LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer value. +Unit: Clock cycles. +This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 devices. +Value After Reset: 0x200 +Exists: MEMC_DDR3==1 || MEMC_DDR4==1 || MEMC_LPDDR2==1 + 16 + 10 + read-write + + + T_ZQ_SHORT_NOP + Description: tZQCS: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to SDRAM. +For configurations with MEMC_FREQ_RATIO=2, program this to tZQCS/2 and round it up to the next integer value. Unit: Clock cycles. +This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 devices. +Value After Reset: 0x40 +Exists: MEMC_DDR3==1 || MEMC_DDR4==1 || MEMC_LPDDR2==1 + 0 + 10 + read-write + + + + + ZQCTL1 + Description: ZQ Control Register 1 + 0x184 + 32 + 0x00000100 + 0x000FFFFF + + + T_ZQ_SHORT_INTERVAL_X1024 + Description: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3/DDR4/LPDDR2/LPDDR3 devices. +Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles. +This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 devices. +Value After Reset: 0x100 +Exists: MEMC_DDR3==1 || MEMC_DDR4==1 || MEMC_LPDDR2==1 + 0 + 20 + read-write + + + + + ZQSTAT + Description: ZQ Status Register + 0x18c + 32 + 0x00000000 + 0x00000001 + + + ZQ_RESET_BUSY + Description: SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. +0 - Indicates that the SoC core can initiate a ZQ Reset operation +1 - Indicates that ZQ Reset operation is in progress +Value After Reset: 0x0 +Exists: Always + 0 + 1 + read-only + + + + + DFITMG0 + Description: DFI Timing Register 0 + 0x190 + 32 + 0x07020002 + 0x1FBFBF3F + + + DFI_T_CTRL_DELAY + Description: Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, depending on the PHY, it may be necessary to increment this parameter by 1. This is to compensate for the extra cycle of latency through the RDIMM +Value After Reset: 0x7 +Exists: Always + 24 + 5 + read-write + + + DFI_RDDATA_USE_SDR + Description: Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: +0 in terms of HDR clock cycles +1 in terms of SDR clock cycles +Refer to PHY specification for correct value. +Value After Reset: 0x0 +Exists: MEMC_FREQ_RATIO==2 + 23 + 1 + read-write + + + DFI_T_RDDATA_EN + Description: Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. +This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle of latency through the RDIMM. +Unit: Clocks +Value After Reset: 0x2 +Exists: Always + 16 + 6 + read-write + + + DFI_WRDATA_USE_SDR + Description: Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or HDR clock cycles +0 in terms of HDR clock cycles +1 in terms of SDR clock cycles +Refer to PHY specification for correct value. +Value After Reset: 0x0 +Exists: MEMC_FREQ_RATIO==2 + 15 + 1 + read-write + + + DFI_TPHY_WRDATA + Description: Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. +Unit: Clocks +Value After Reset: 0x0 +Exists: Always + 8 + 6 + read-write + + + DFI_TPHY_WRLAT + Description: Write latency +Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. The minimum supported value is as follows: +0 for configurations with MEMC_WL0 = 1 +1 for configurations with MEMC_WL0 = 0 +Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency through the RDIMM. +Value After Reset: 0x2 +Exists: Always + 0 + 6 + read-write + + + + + DFITMG1 + Description: DFI Timing Register 1 + 0x194 + 32 + 0x00000404 + 0x001F0F0F + + + DFI_T_WRDATA_DELAY + Description: Specifies the number of DFI clocks between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification for correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Value to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ_RATIO=2, divide PHY's value by 2 and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. +Unit: Clocks +Value After Reset: 0x0 +Exists: Always + 16 + 5 + read-write + + + DFI_T_DRAM_CLK_DISABLE + Description: Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY- DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +Value After Reset: 0x4 +Exists: Always + 8 + 4 + read-write + + + DFI_T_DRAM_CLK_ENABLE + Description: Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +Value After Reset: 0x4 +Exists: Always + 0 + 4 + read-write + + + + + DFILPCFG0 + Description: DFI Low Power Configuration Register 0 + 0x198 + 32 + 0x07000000 + 0x0F00F1F1 + + + DFI_TLP_RESP + Description: Setting for DFI's tlp_resp time. +Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1 specification onwards, recommends using a fixed +value of 7 always. +Value After Reset: 0x7 +Exists: Always + 24 + 4 + read-write + + + DFI_LP_WAKEUP_SR + Description: Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. +Determines the DFI's tlp_wakeup time: +0x0 - 16 cycles +0x1 - 32 cycles +0x2 - 64 cycles +0x3 - 128 cycles +0x4 - 256 cycles +0x5 - 512 cycles +0x6 - 1024 cycles +0x7 - 2048 cycles +0x8 - 4096 cycles +0x9 - 8192 cycles +0xA - 16384 cycles +0xB - 32768 cycles +0xC - 65536 cycles +0xD - 131072 cycles +0xE - 262144 cycles +0xF - Unlimited Value After Reset: 0x0 Exists: Always + 12 + 4 + read-write + + + DFI_LP_EN_SR + Description: Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. +0 - Disabled +1 - Enabled +Value After Reset: 0x0 +Exists: Always + 8 + 1 + read-write + + + DFI_LP_WAKEUP_PD + Description: Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. +Determines the DFI's tlp_wakeup time: +0x0 - 16 cycles +0x1 - 32 cycles +0x2 - 64 cycles +0x3 - 128 cycles +0x4 - 256 cycles +0x5 - 512 cycles +0x6 - 1024 cycles +0x7 - 2048 cycles +0x8 - 4096 cycles +0x9 - 8192 cycles +0xA - 16384 cycles +0xB - 32768 cycles +0xC - 65536 cycles +0xD - 131072 cycles +0xE - 262144 cycles +0xF - Unlimited Value After Reset: 0x0 Exists: Always + 4 + 4 + read-write + + + DFI_LP_EN_PD + Description: Enables DFI Low Power interface handshaking during Power Down Entry/Exit. +0 - Disabled +1 - Enabled +Value After Reset: 0x0 +Exists: Always + 0 + 1 + read-write + + + + + DFIUPD0 + Description: DFI Update Register 0 + 0x1a0 + 32 + 0x00400003 + 0x83FF03FF + + + DIS_AUTO_CTRLUPD + Description: When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2. The core must issue the dfi_ctrlupd_req signal using register reg_ddrc_ctrlupd. This register field is changeable on the fly. +When '0', uMCTL2 issues dfi_ctrlupd_req periodically. +Value After Reset: 0x0 +Exists: Always + 31 + 1 + read-write + + + DFI_T_CTRLUP_MAX + Description: Specifies the maximum number of clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. +Unit: Clocks +Value After Reset: 0x40 +Exists: Always + 16 + 10 + read-write + + + DFI_T_CTRLUP_MIN + Description: Specifies the minimum number of clock cycles that the dfi_ctrlupd_req signal must be asserted. The uMCTL2 expects the PHY to respond within this time. If the PHY does not respond, the uMCTL2 will de-assert dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. +Unit: Clocks +Value After Reset: 0x3 +Exists: Always + 0 + 10 + read-write + + + + + DFIUPD1 + Description: DFI Update Register 1 + 0x1a4 + 32 + 0x00000000 + 0x00FF00FF + + + DFI_T_CTRLUPD_INTERVAL_MIN_X1024 + Description: This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the uMCTL2 is idle. +Unit: 1024 clocks Value After Reset: 0x0 + Exists: Always + 16 + 8 + read-write + + + DFI_T_CTRLUPD_INTERVAL_MAX_X1024 + Description: This is the maximum amount of time between uMCTL2 initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. +Updates are required to maintain calibration over PVT, but frequent updates may impact performance. +Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. +Unit: 1024 clocks Value After Reset: 0x0 +Exists: Always + 0 + 8 + read-write + + + + + DFIUPD2 + Description: DFI Update Register 2 + 0x1a8 + 32 + 0x80100010 + 0x8FFF0FFF + + + DFI_PHYUPD_EN + Description: Enables the support for acknowledging PHY- initiated updates: +0 - Disabled +1 - Enabled +Value After Reset: 0x1 +Exists: Always + 31 + 1 + read-write + + + DFI_PHYUPD_TYPE1 + Description: Specifies the maximum number of DFI clock cycles that the dfi_phyupd_req signal may remain asserted after the assertion of the dfi_phyupd_ack signal for dfi_phyupd_type = 2'b01. The dfi_phyupd_req signal may de-assert at any cycle after the assertion of the dfi_phyupd_ack signal. +Value After Reset: 0x10 +Exists: Always + 16 + 12 + read-write + + + DFI_PHYUPD_TYPE0 + Description: Specifies the maximum number of DFI clock cycles that the dfi_phyupd_req signal may remain asserted after the assertion of the dfi_phyupd_ack signal for dfi_phyupd_type = 2'b00. The dfi_phyupd_req signal may de-assert at any cycle after the assertion of the dfi_phyupd_ack signal. +Value After Reset: 0x10 +Exists: Always + 0 + 12 + read-write + + + + + DFIUPD3 + Description: DFI Update Register 3 + 0x1ac + 32 + 0x00100010 + 0x0FFF0FFF + + + DFI_PHYUPD_TYPE3 + Description: Specifies the maximum number of DFI clock cycles that the dfi_phyupd_req signal may remain asserted after the assertion of the dfi_phyupd_ack signal for dfi_phyupd_type = 2'b11. The dfi_phyupd_req signal may de-assert at any cycle after the assertion of the dfi_phyupd_ack signal. +Value After Reset: 0x10 +Exists: Always + 16 + 12 + read-write + + + DFI_PHYUPD_TYPE2 + Description: Specifies the maximum number of DFI clock cycles that the dfi_phyupd_req signal may remain asserted after the assertion of the dfi_phyupd_ack signal for dfi_phyupd_type = 2'b10. The dfi_phyupd_req signal may de-assert at any cycle after the assertion of the dfi_phyupd_ack signal. +Value After Reset: 0x10 +Exists: Always + 0 + 12 + read-write + + + + + DFIMISC + Description: DFI Miscellaneous Control Register + 0x1b0 + 32 + 0x00000001 + 0x00000001 + + + DFI_INIT_COMPLETE_EN + Description: PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisation +Value After Reset: 0x1 +Exists: Always + 0 + 1 + read-write + + + + + DFITMG2 + Description: DFI Timing Register 2 + 0x1b4 + 32 + 0x00000202 + 0x00003F3F + + + DFI_TPHY_RDCSLAT + Description: Number of clocks between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs_n signal is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value. +Value After Reset: 0x2 +Exists: Always + 8 + 6 + read-write + + + DFI_TPHY_WRCSLAT + Description: Number of clocks between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs_n signal is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. The minimum supported value is as follows: +0 for configurations with MEMC_WL0 = 1 +1 for configurations with MEMC_WL0 = 0 Refer to PHY specification for correct value. Value After Reset: 0x2 +Exists: Always + 0 + 6 + read-write + + + + + ADDRMAP0 + Description: Address Map Register 0 + 0x200 + 32 + 0x00000000 + 0x0000001F + + + ADDRMAP_CS_BIT0 + Description: Selects the HIF address bit used as rank address bit 0. +Valid Range: 0 to 27, and 31 +Internal Base: 6 +The selected HIF address bit is determined by adding the internal base to the value of this field. +If set to 31, rank address bit 0 is set to 0. +Value After Reset: 0x0 +Exists: MEMC_NUM_RANKS>1 + 0 + 5 + read-write + + + + + ADDRMAP1 + Description: Address Map Register 1 + 0x204 + 32 + 0x00000000 + 0x001F1F1F + + + ADDRMAP_BANK_B2 + Description: Selects the HIF address bit used as bank address bit 2. +Valid Range: 0 to 29 and 31 +Internal Base: 4 +The selected HIF address bit is determined by adding the internal base to the value of this field. +If set to 31, bank address bit 2 is set to 0. +Value After Reset: 0x0 +Exists: Always + 16 + 5 + read-write + + + ADDRMAP_BANK_B1 + Description: Selects the HIF address bits used as bank address bit 1. +Valid Range: 0 to 30 +Internal Base: 3 +The selected HIF address bit for each of the bank address bits is determined by adding the internal base to the value of this field. +Value After Reset: 0x0 +Exists: Always + 8 + 5 + read-write + + + ADDRMAP_BANK_B0 + Description: Selects the HIF address bits used as bank address bit 0. +Valid Range: 0 to 30 +Internal Base: 2 +The selected HIF address bit for each of the bank address bits is determined by adding the internal base to the value of this field. +Value After Reset: 0x0 +Exists: Always + 0 + 5 + read-write + + + + + ADDRMAP2 + Description: Address Map Register 2 + 0x208 + 32 + 0x00000000 + 0x0F0F0F0F + + + ADDRMAP_COL_B5 + Description: Full bus width mode: Selects the HIF address bit used as column address bit 5 (if MEMC_BURST_LENGTH = 4) or 6 (if +MEMC_BURST_LENGTH = 8). +Half bus width mode: Selects the HIF address bit used as column address bit 6 (if MEMC_BURST_LENGTH = 4) or 7 (if MEMC_BURST_LENGTH = 8). +Quarter bus width mode: Selects the HIF address bit used as column address bit 7 (if MEMC_BURST_LENGTH = 4) or 8 (if MEMC_BURST_LENGTH = 8). +Valid Range: 0 to 7, and 15 +Internal Base: 5 +The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. +Value After Reset: 0x0 +Exists: Always + 24 + 4 + read-write + + + ADDRMAP_COL_B4 + Description: Full bus width mode: Selects the HIF address bit used as column address bit 4 (if MEMC_BURST_LENGTH = 4) or 5 (if +MEMC_BURST_LENGTH = 8). +Half bus width mode: Selects the HIF address bit used as column address bit 5 (if MEMC_BURST_LENGTH = 4) or 6 (if MEMC_BURST_LENGTH = 8). +Quarter bus width mode: Selects the HIF address bit used as column address bit 6 (if MEMC_BURST_LENGTH = 4) or 7 (if MEMC_BURST_LENGTH = 8). +Valid Range: 0 to 7, and 15 +Internal Base: 4 +The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. +Value After Reset: 0x0 +Exists: Always + 16 + 4 + read-write + + + ADDRMAP_COL_B3 + Description: Full bus width mode: Selects the HIF address bit used as column address bit 3 (if MEMC_BURST_LENGTH = 4) or 4 (if +MEMC_BURST_LENGTH = 8). +Half bus width mode: Selects the HIF address bit used as column address bit 4 (if MEMC_BURST_LENGTH = 4) or 5 (if MEMC_BURST_LENGTH = 8). +Quarter bus width mode: Selects the HIF address bit used as column address bit 5 (if MEMC_BURST_LENGTH = 4) or 6 (if MEMC_BURST_LENGTH = 8). +Valid Range: 0 to 7 +Internal Base: 3 +The selected HIF address bit is determined by adding the internal base to the value of this field. +Value After Reset: 0x0 +Exists: Always + 8 + 4 + read-write + + + ADDRMAP_COL_B2 + Description: Full bus width mode: Selects the HIF address bit used as column address bit 2 (if MEMC_BURST_LENGTH = 4) or 3 (if +MEMC_BURST_LENGTH = 8). +Half bus width mode: Selects the HIF address bit used as column address bit 3 (if MEMC_BURST_LENGTH = 4) or 4 (if MEMC_BURST_LENGTH = 8). +Quarter bus width mode: Selects the HIF address bit used as column address bit 4 (if MEMC_BURST_LENGTH = 4) or 5 (if MEMC_BURST_LENGTH = 8). +Valid Range: 0 to 7 +Internal Base: 2 +The selected HIF address bit is determined by adding the internal base to the value of this field. +Value After Reset: 0x0 +Exists: Always + 0 + 4 + read-write + + + + + ADDRMAP3 + Description: Address Map Register 3 + 0x20c + 32 + 0x00000000 + 0x0F0F0F0F + + + ADDRMAP_COL_B9 + Description: Full bus width mode: Selects the HIF address bit used as column address bit 9 (if MEMC_BURST_LENGTH = 4) or 11 (10 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 8) +Half bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 4) or 13 (11 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 8). +(Column address bit 11 in LPDDR2/LPDDR3 mode) Quarter bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) (if +MEMC_BURST_LENGTH = 4) or UNUSED (if +MEMC_BURST_LENGTH = 8). +Valid Range: 0 to 7, and 15 +Internal Base: 9 +The selected HIF address bit is determined by adding the internal base to the value of this field. +If set to 15, this column address bit is set to 0. +Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. +In LPDDR2/LPDDR3, there is a dedicated bit for auto- precharge in the CA bus and hence column bit 10 is used. Value After Reset: 0x0 +Exists: Always + 24 + 4 + read-write + + + ADDRMAP_COL_B8 + Description: Full bus width mode: Selects the HIF address bit used as column address bit 8 (if MEMC_BURST_LENGTH = 4) or 9 (if +MEMC_BURST_LENGTH = 8). +Half bus width mode: Selects the HIF address bit used as column address bit 9 (if MEMC_BURST_LENGTH = 4) or 11 (10 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 8). +Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 4) or 13 (11 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 8). +Valid Range: 0 to 7, and 15 +Internal Base: 8 +The selected HIF address bit is determined by adding the internal base to the value of this field. +If set to 15, this column address bit is set to 0. +Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. +In LPDDR2/LPDDR3, there is a dedicated bit for auto- precharge in the CA bus and hence column bit 10 is used. Value After Reset: 0x0 +Exists: Always + 16 + 4 + read-write + + + ADDRMAP_COL_B7 + Description: Full bus width mode: Selects the HIF address bit used as column address bit 7 (if MEMC_BURST_LENGTH = 4) or 8 (if +MEMC_BURST_LENGTH = 8). +Half bus width mode: Selects the HIF address bit used as column address bit 8 (if MEMC_BURST_LENGTH = 4) or 9 (if MEMC_BURST_LENGTH = 8). +Quarter bus width mode: Selects the HIF address bit used as column address bit 9 (if MEMC_BURST_LENGTH = 4) or 11 (10 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 8). +Valid Range: 0 to 7, and 15 +Internal Base: 7 +The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. +Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge and hence no source address bit can be mapped to column address bit 10. +In LPDDR2/LPDDR3, there is a dedicated bit for auto- precharge in the CA bus and hence column bit 10 is used. Value After Reset: 0x0 +Exists: Always + 8 + 4 + read-write + + + ADDRMAP_COL_B6 + Description: Full bus width mode: Selects the HIF address bit used as column address bit 6 (if MEMC_BURST_LENGTH = 4) or 7 (if +MEMC_BURST_LENGTH = 8). +Half bus width mode: Selects the HIF address bit used as column address bit 7 (if MEMC_BURST_LENGTH = 4) or 8 (if MEMC_BURST_LENGTH = 8). +Quarter bus width mode: Selects the HIF address bit used as column address bit 8 (if MEMC_BURST_LENGTH = 4) or 9 (if MEMC_BURST_LENGTH = 8). +Valid Range: 0 to 7, and 15 +Internal Base: 6 +The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. +Value After Reset: 0x0 +Exists: Always + 0 + 4 + read-write + + + + + ADDRMAP4 + Description: Address Map Register 4 + 0x210 + 32 + 0x00000000 + 0x00000F0F + + + ADDRMAP_COL_B11 + Description: Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 4) or UNUSED (if MEMC_BURST_LENGTH = 8). +Half bus width mode: Unused. To make it unused, this should be tied to 4'hF. +Quarter bus width mode: Unused. To make it unused, this must be tied to 4'hF. +Valid Range: 0 to 7, and 15 +Internal Base: 11 +The selected HIF address bit is determined by adding the internal base to the value of this field. +If set to 15, this column address bit is set to 0. +Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. +In LPDDR2/LPDDR3, there is a dedicated bit for auto- precharge in the CA bus and hence column bit 10 is used. Value After Reset: 0x0 +Exists: Always + 8 + 4 + read-write + + + ADDRMAP_COL_B10 + Description: Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 4) or 13 (11 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 8). +Half bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 4) or UNUSED (if MEMC_BURST_LENGTH = 8) +Quarter bus width mode: UNUSED. To make it unused, this must be tied to 4'hF. +Valid Range: 0 to 7, and 15 +Internal Base: 10 +The selected HIF address bit is determined by adding the internal base to the value of this field. +If set to 15, this column address bit is set to 0. +Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. +In LPDDR2/LPDDR3, there is a dedicated bit for auto- precharge in the CA bus and hence column bit 10 is used. Value After Reset: 0x0 +Exists: Always + 0 + 4 + read-write + + + + + ADDRMAP5 + Description: Address Map Register 5 + 0x214 + 32 + 0x00000000 + 0x0F0F0F0F + + + ADDRMAP_ROW_B11 + Description: Selects the HIF address bit used as row address bit 11. +Valid Range: 0 to 11, and 15 +Internal Base: 17 +The selected HIF address bit is determined by adding the internal base to the value of this field. +If set to 15, row address bit 11 is set to 0. +Value After Reset: 0x0 +Exists: Always + 24 + 4 + read-write + + + ADDRMAP_ROW_B2_10 + Description: Selects the HIF address bits used as row address bits 2 to 10. +Valid Range: 0 to 11 +Internal Base: 8 (for row address bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc increasing to 16 (for row +address bit 10) +The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. +Value After Reset: 0x0 +Exists: Always + 16 + 4 + read-write + + + ADDRMAP_ROW_B1 + Description: Selects the HIF address bits used as row address bit 1. +Valid Range: 0 to 11 +Internal Base: 7 +The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. +Value After Reset: 0x0 +Exists: Always + 8 + 4 + read-write + + + ADDRMAP_ROW_B0 + Description: Selects the HIF address bits used as row address bit 0. +Valid Range: 0 to 11 +Internal Base: 6 +The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. +Value After Reset: 0x0 +Exists: Always + 0 + 4 + read-write + + + + + ADDRMAP6 + Description: Address Map Register 6 + 0x218 + 32 + 0x00000000 + 0x0F0F0F0F + + + ADDRMAP_ROW_B15 + Description: Selects the HIF address bit used as row address bit 15. +Valid Range: 0 to 11, and 15 +Internal Base: 21 +The selected HIF address bit is determined by adding the internal base to the value of this field. +If set to 15, row address bit 15 is set to 0. +Value After Reset: 0x0 +Exists: Always + 24 + 4 + read-write + + + ADDRMAP_ROW_B14 + Description: Selects the HIF address bit used as row address bit 14. +Valid Range: 0 to 11, and 15 +Internal Base: 20 +The selected HIF address bit is determined by adding the internal base to the value of this field. +If set to 15, row address bit 14 is set to 0. +Value After Reset: 0x0 +Exists: Always + 16 + 4 + read-write + + + ADDRMAP_ROW_B13 + Description: Selects the HIF address bit used as row address bit 13. +Valid Range: 0 to 11, and 15 +Internal Base: 19 +The selected HIF address bit is determined by adding the internal base to the value of this field. +If set to 15, row address bit 13 is set to 0. +Value After Reset: 0x0 +Exists: Always + 8 + 4 + read-write + + + ADDRMAP_ROW_B12 + Description: Selects the HIF address bit used as row address bit 12. +Valid Range: 0 to 11, and 15 +Internal Base: 18 +The selected HIF address bit is determined by adding the internal base to the value of this field. +If set to 15, row address bit 12 is set to 0. +Value After Reset: 0x0 +Exists: Always + 0 + 4 + read-write + + + + + ODTCFG + Description: ODT Configuration Register + 0x240 + 32 + 0x04000400 + 0x0F1F0F7C + + + WR_ODT_HOLD + Description: Cycles to hold ODT for a write command. The minimum supported value is 2. DDR2/DDR3/DDR4 +BL8 - 0x6 +BL4 - 0x4 +LPDDR3 - RU(tDQSSmax/tCK) + 4 +Value After Reset: 0x4 +Exists: Always + 24 + 4 + read-write + + + WR_ODT_DELAY + Description: The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. ODT is used only in DDR2, DDR3, DDR4 and LPDDR3 designs. +Recommended values: +DDR2 +If (CWL + AL < 3), then 0. +If (CWL + AL >= 3), then (CWL + AL - 3) DDR3 - 0 +DDR4 - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) +LPDDR3 - (CWL - RU(tODToffmax/tCK)) +Value After Reset: 0x0 +Exists: Always + 16 + 5 + read-write + + + RD_ODT_HOLD + Description: Cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2/DDR3 +BL8 - 0x6 +BL4 - 0x4 +DDR4 - 0x6, but needs to be reduced to 0x5 in CAL mode to avoid overlap of read and write ODT LPDDR3 - RU(tDQSCKmax/tCK) + 4 + 1 +Value After Reset: 0x4 +Exists: Always + 8 + 4 + read-write + + + RD_ODT_DELAY + Description: The delay, in clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. ODT is used only in DDR2, DDR3, DDR4 and LPDDR3 designs. +Recommended values: +DDR2 +If (CL + AL < 4), then 0. +If (CL + AL >= 4), then (CL + AL - 4) DDR3 +(CL - CWL) DDR4 +If CAL mode is enabled, CL - CWL + DFITMG1.dfi_t_cmd_lat +If CAL mode is not enabled, CL - CWL -1, or 0 if CL - CWL < 1 +LPDDR3, MEMC_FREQ_RATIO=2 +CL - RU(tODToffmax/tCK)) Value After Reset: 0x0 Exists: Always + 2 + 5 + read-write + + + + + ODTMAP + Description: ODT/Rank Map Register + 0x244 + 32 + 0x00002211 + 0x0000FFFF + + + RANK1_RD_ODT + Description: Indicates which remote ODTs must be turned on during a read from rank 1. +Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. +Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. +For each rank, set its bit to 1 to enable its ODT. +Present only in configurations that have 2 or more ranks Value After Reset: "(MEMC_NUM_RANKS>1) ? 0x2 : 0x0" Exists: MEMC_NUM_RANKS>1 + 12 + 4 + read-write + + + RANK1_WR_ODT + Description: Indicates which remote ODTs must be turned on during a write to rank 1. +Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. +Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. +For each rank, set its bit to 1 to enable its ODT. +Present only in configurations that have 2 or more ranks Value After Reset: "(MEMC_NUM_RANKS>1) ? 0x2 : 0x0" Exists: MEMC_NUM_RANKS>1 + 8 + 4 + read-write + + + RANK0_RD_ODT + Description: Indicates which remote ODTs must be turned on during a read from rank 0. +Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. +Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. +For each rank, set its bit to 1 to enable its ODT. +Value After Reset: 0x1 +Exists: Always + 4 + 4 + read-write + + + RANK0_WR_ODT + Description: Indicates which remote ODTs must be turned on during a write to rank 0. +Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. +Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. +For each rank, set its bit to 1 to enable its ODT. +Value After Reset: 0x1 +Exists: Always + 0 + 4 + read-write + + + + + SCHED + Description: Scheduler Control Register + 0x250 + 32 + 0x00000805 + 0x7FFF3F07 + + + RDWR_IDLE_GAP + Description: When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. +The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternative store. +When prefer write over read is set this is reversed. +0x0 is a legal value for this register. When set to 0x0, the transaction store switching will happen immediately when the switching conditions become true. +FOR PERFORMANCE ONLY +Value After Reset: 0x0 +Exists: Always + 24 + 7 + read-write + + + GO2CRITICAL_HYSTERESIS + Description: UNUSED Value After Reset: 0x0 Exists: Always + 16 + 8 + read-write + + + LPR_NUM_ENTRIES + Description: Number of entries in the low priority transaction store is this value + 1. +(MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of entries available for the high priority transaction store. +Setting this to maximum value allocates all entries to low priority transaction store. +Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high priority transaction store. +Note: In ECC configurations, the numbers of write and low priority read credits issued is one less than in the non-ECC case. One entry each is reserved in the write and low- priority read CAMs for storing the RMW requests arising out of single bit error correction RMW operation. +Value After Reset: "MEMC_NO_OF_ENTRY/2" +Exists: Always + 8 + 6 + read-write + + + PAGECLOSE + Description: If true, bank is kept open only until there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit will be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between Write and Read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. If false, the bank remains open until there is a need to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy. The open page policy can be overridden by setting the per-command-autopre bit on the HIF interface (co_ih_rxcmd_autopre). +The pageclose feature provids a midway between Open and Close page policies. +FOR PERFORMANCE ONLY. +Value After Reset: 0x1 +Exists: Always + 2 + 1 + read-write + + + PREFER_WRITE + Description: If set then the bank selector prefers writes over reads. +FOR DEBUG ONLY. +Value After Reset: 0x0 +Exists: Always + 1 + 1 + read-write + + + FORCE_LOW_PRI_N + Description: Active low signal. When asserted ('0'), all incoming transactions are forced to low priority. This implies that all High Priority Read (HPR) and Variable Priority Read commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write side, all Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off Bypass path for read commands. +FOR PERFORMANCE ONLY. +Value After Reset: 0x1 +Exists: Always + 0 + 1 + read-write + + + + + SCHED1 + Description: Scheduler Control Register 1 + 0x254 + 32 + 0x00000000 + 0x000000FF + + + PAGECLOSE_TIMER + Description: This field works in conjunction with SCHED.pageclose. It only has meaning if SCHED.pageclose==1. +If SCHED.pageclose==1 and pageclose_timer==0, then an auto-precharge may be scheduled for last read or write command in the CAM with a bank and page hit. Note, sometimes an explicit precharge is scheduled instead of the auto-precharge. See SCHED.pageclose for details of when this may happen. +If SCHED.pageclose==1 and pageclose_timer>0, then an auto-precharge is not scheduled for last read or write command in the CAM with a bank and page hit. Instead, a timer is started, with pageclose_timer as the initial value. There is a timer on a per bank basis. The timer decrements unless the next read or write in the CAM to a bank is a page hit. It gets reset to pageclose_timer value if the next read or write in the CAM to a bank is a page hit. Once the timer has reached zero, an explcit precharge will be attempted to be scheduled. +Value After Reset: 0x0 +Exists: Always + 0 + 8 + read-write + + + + + PERFHPR1 + Description: High Priority Read CAM Register 1 + 0x25c + 32 + 0x0F000001 + 0xFF00FFFF + + + HPR_XACT_RUN_LENGTH + Description: Number of transactions that are serviced once the HPR queue goes critical is the smaller of: +This number +Number of transactions available Unit: Transaction. +FOR PERFORMANCE ONLY. +Value After Reset: 0xf +Exists: Always + 24 + 8 + read-write + + + HPR_MAX_STARVE + Description: Number of clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not be disabled as it will cause excessive latencies. +Unit: Clock cycles. +FOR PERFORMANCE ONLY. +Value After Reset: 0x1 +Exists: Always + 0 + 16 + read-write + + + + + PERFLPR1 + Description: Low Priority Read CAM Register 1 + 0x264 + 32 + 0x0F00007F + 0xFF00FFFF + + + LPR_XACT_RUN_LENGTH + Description: Number of transactions that are serviced once the LPR queue goes critical is the smaller of: +This number +Number of transactions available. Unit: Transaction. +FOR PERFORMANCE ONLY. +Value After Reset: 0xf +Exists: Always + 24 + 8 + read-write + + + LPR_MAX_STARVE + Description: Number of clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not be disabled as it will cause excessive latencies. +Unit: Clock cycles. +FOR PERFORMANCE ONLY. +Value After Reset: 0x7f +Exists: Always + 0 + 16 + read-write + + + + + PERFWR1 + Description: Write CAM Register 1 + 0x26c + 32 + 0x0F00007F + 0xFF00FFFF + + + W_XACT_RUN_LENGTH + Description: Number of transactions that are serviced once the WR queue goes critical is the smaller of: +This number +Number of transactions available. Unit: Transaction. +FOR PERFORMANCE ONLY. +Value After Reset: 0xf +Exists: Always + 24 + 8 + read-write + + + W_MAX_STARVE + Description: Number of clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not be disabled as it will cause excessive latencies. +Unit: Clock cycles. +FOR PERFORMANCE ONLY. +Value After Reset: 0x7f +Exists: Always + 0 + 16 + read-write + + + + + PERFVPR1 + Description: Variable Priority Read CAM Register 1 + 0x274 + 32 + 0x00000000 + 0x000007FF + + + VPR_TIMEOUT_RANGE + Description: Indicates the range of the timeout value that is used for grouping the expired VPR commands in the CAM in DDRC. For example, if the register value is set to 0xF, then the priorities of all the VPR commands whose timeout counters are 15 or below will be considered as expired-VPR commands when the timeout value of any of the VPR commands reach 0. The expired-VPR commands, when present, are given higher priority than HPR commands. The VPR commands are expected to consist of largely page hit traffic and by grouping them together the bus utilization is expected to increase. This register applies to transactions inside the DDRC only. +The Max value for this register is 0x7FF and the Min value is 0x0. +When programmed to the Max value of 0x7FF, all the VPR commands that come in to DDRC will time-out right-away and will be considered as expired-VPR. +When programmed to the Min value of 0x0, the timer of each command would have to reach a value of 0 before it will be considered as expired-VPR. +Unit: Clock cycles. +FOR PERFORMANCE ONLY. +Value After Reset: 0x0 +Exists: UMCTL2_VPR_EN==1 + 0 + 11 + read-write + + + + + PERFVPW1 + Description: Variable Priority Write CAM Register 1 + 0x278 + 32 + 0x00000000 + 0x000007FF + + + VPW_TIMEOUT_RANGE + Description: Indicates the range of the timeout value that is used for grouping the expired VPW commands in the CAM in DDRC. For example, if the register value is set to 0xF, then the priorities of all the VPW commands whose timeout counters are 15 or below will be considered as expired-VPW commands when the timeout value of any of the VPW commands reach 0. The expired-VPW commands, when present, are given higher priority than normal Write commands. The VPW commands are expected to consist of largely page hit traffic and by grouping them together the bus utilization is expected to increase. This register applies to transactions inside the DDRC only. +The Max value for this register is 0x7FF and the Min value is 0x0. +When programmed to the Max value of 0x7FF, all the VPW commands that come in to DDRC will time-out right-away and will be considered as expired-VPW. +When programmed to the Min value of 0x0, the timer of each command would have to reach a value of 0 before it will be considered as expired-VPW. +Unit: Clock cycles. +FOR PERFORMANCE ONLY. +Value After Reset: 0x0 +Exists: UMCTL2_VPW_EN==1 + 0 + 11 + read-write + + + + + DBG0 + Description: Debug Register 0 + 0x300 + 32 + 0x00000000 + 0x00000017 + + + DIS_COLLISION_PAGE_OPT + Description: When this is set to '0', auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). +FOR DEBUG ONLY. +Value After Reset: 0x0 +Exists: Always + 4 + 1 + read-write + + + DIS_ACT_BYPASS + Description: Only present in designs supporting activate bypass. +When 1, disable bypass path for high priority read activates FOR DEBUG ONLY. +Value After Reset: 0x0 +Exists: MEMC_BYPASS==1 + 2 + 1 + read-write + + + DIS_RD_BYPASS + Description: Only present in designs supporting read bypass. +When 1, disable bypass path for high priority read page hits FOR DEBUG ONLY. +Value After Reset: 0x0 +Exists: MEMC_BYPASS==1 + 1 + 1 + read-write + + + DIS_WC + Description: When 1, disable write combine. FOR DEBUG ONLY +Value After Reset: 0x0 +Exists: Always + 0 + 1 + read-write + + + + + DBG1 + Description: Debug Register 1 + 0x304 + 32 + 0x00000000 + 0x00000003 + + + DIS_HIF + Description: When 1, uMCTL2 asserts the HIF command ih_co_stall. uMCTL2 will ignore the co_ih_rxcmd_valid and all other associated request signals. +This bit is intended to be switched on-the-fly. +Value After Reset: 0x0 +Exists: Always + 1 + 1 + read-write + + + DIS_DQ + Description: When 1, uMCTL2 will not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. +This bit may be used to prevent reads or writes being issued by the uMCTL2, which makes it safe to modify certain register fields associated with reads and writes (see User Guide for details). After setting this bit, it is strongly recommended to poll DBGCAM.wr_data_pipeline_empty and DBGCAM.rd_data_pipeline_empty, before making changes to any registers which affect reads and writes. This will ensure that the relevant logic in the DDRC is idle. +This bit is intended to be switched on-the-fly. +Value After Reset: 0x0 +Exists: Always + 0 + 1 + read-write + + + + + DBGCAM + Description: CAM Debug Register + 0x308 + 32 + 0x00000000 + 0x377F7F7F + + + WR_DATA_PIPELINE_EMPTY + Description: This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. +Value After Reset: 0x0 +Exists: Always + 29 + 1 + read-only + + + RD_DATA_PIPELINE_EMPTY + Description: This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. +Value After Reset: 0x0 +Exists: Always + 28 + 1 + read-only + + + DBG_WR_Q_EMPTY + Description: When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. +An example use-case scenario: When Controller enters Self- Refresh using the Low-Power entry sequence, Controller is expected to have executed all the commands in its queues and the write and read data drained. Hence this register should be 1 at that time. +FOR DEBUG ONLY +Value After Reset: 0x0 +Exists: Always + 26 + 1 + read-only + + + DBG_RD_Q_EMPTY + Description: When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. +An example use-case scenario: When Controller enters Self- Refresh using the Low-Power entry sequence, Controller is expected to have executed all the commands in its queues and the write and read data drained. Hence this register should be 1 at that time. +FOR DEBUG ONLY +Value After Reset: 0x0 +Exists: Always + 25 + 1 + read-only + + + DBG_STALL + Description: Stall FOR DEBUG ONLY +Value After Reset: 0x0 +Exists: Always + 24 + 1 + read-only + + + DBG_W_Q_DEPTH + Description: Write queue depth +Note: The width of this field is dependent on log(MEMC_NO_OF_ENTRY+1). For example, if CAM depth += 32, then register width is 6 bits and bit 22 is reserved. FOR DEBUG ONLY +Value After Reset: 0x0 +Exists: Always + 16 + 7 + read-only + + + DBG_LPR_Q_DEPTH + Description: Low priority read queue depth Note: The width of this field is dependent on +log(MEMC_NO_OF_ENTRY+1). For example, if CAM depth += 32, then register width is 6 bits and bit 14 is reserved FOR DEBUG ONLY +Value After Reset: 0x0 +Exists: Always + 8 + 7 + read-only + + + DBG_HPR_Q_DEPTH + Description: High priority read queue depth Note: The width of this field is dependent on +log(MEMC_NO_OF_ENTRY+1). For example, if CAM depth += 32, then register width is 6 bits and bit 6 is reserved FOR DEBUG ONLY +Value After Reset: 0x0 +Exists: Always + 0 + 7 + read-only + + + + + DBGCMD + Description: Command Debug Register + 0x30c + 32 + 0x00000000 + 0x00000033 + + + CTRLUPD + Description: Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in uMCTL2, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. +Value After Reset: 0x0 +Exists: Always + 5 + 1 + read-write + + + ZQ_CALIB_SHORT + Description: Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short) command to the SDRAM. When this request is stored in uMCTL2, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register bit is ignored when in Self-Refresh and Deep power-down operating modes. +Value After Reset: 0x0 +Exists: MEMC_DDR3_OR_4_OR_LPDDR2==1 + 4 + 1 + read-write + + + RANK1_REFRESH + Description: Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. When this request is stored in uMCTL2, the bit is automatically cleared. This operation can be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-down operating modes or Maximum Power Saving Mode. +Value After Reset: 0x0 +Exists: MEMC_NUM_RANKS>1 + 1 + 1 + read-write + + + RANK0_REFRESH + Description: Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. When this request is stored in uMCTL2, the bit is automatically cleared. This operation can be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-down operating modes or Maximum Power Saving Mode. +Value After Reset: 0x0 +Exists: Always + 0 + 1 + read-write + + + + + DBGSTAT + Description: Status Debug Register + 0x310 + 32 + 0x00000000 + 0x00000033 + + + CTRLUPD_BUSY + Description: SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in uMCTL2. It is recommended not to perform ctrlupd operations when this signal is high. +0 - Indicates that the SoC core can initiate a ctrlupd operation +1 - Indicates that ctrlupd operation has not been initiated yet in uMCTL2 +Value After Reset: 0x0 +Exists: Always + 5 + 1 + read-only + + + ZQ_CALIB_SHORT_BUSY + Description: SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ZQCS request. It goes low when the ZQCS operation is initiated in uMCTL2. It is recommended not to perform ZQCS operations when this signal is high. +0 - Indicates that the SoC core can initiate a ZQCS operation +1 - Indicates that ZQCS operation has not been initiated yet in uMCTL2 +Value After Reset: 0x0 +Exists: MEMC_DDR3_OR_4_OR_LPDDR2==1 + 4 + 1 + read-only + + + RANK1_REFRESH_BUSY + Description: SoC core may initiate a rank1_refresh operation (refresh operation to rank 1) only if this signal is low. This signal goes high in the clock after DBGCMD.rank1_refresh is set to one. It goes low when the rank1_refresh operation is stored in uMCTL2. It is recommended not to perform rank1_refresh operations when this signal is high. +0 - Indicates that the SoC core can initiate a rank1_refresh operation +1 - Indicates that rank1_refresh operation has not been stored yet in uMCTL2 +Value After Reset: 0x0 +Exists: MEMC_NUM_RANKS>1 + 1 + 1 + read-only + + + RANK0_REFRESH_BUSY + Description: SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in uMCTL2. It is recommended not to perform rank0_refresh operations when this signal is high. +0 - Indicates that the SoC core can initiate a rank0_refresh operation +1 - Indicates that rank0_refresh operation has not been stored yet in uMCTL2 +Value After Reset: 0x0 +Exists: Always + 0 + 1 + read-only + + + + + PSTAT + Description: Port Status Register + 0x3fc + 32 + 0x00000000 + 0xFFFFFFFF + + + WR_PORT_BUSY_15 + Description: Indicates if there are outstanding writes for port 15. +Value After Reset: 0x0 +Exists: UMCTL2_PORT_15==1 + 31 + 1 + read-only + + + WR_PORT_BUSY_14 + Description: Indicates if there are outstanding writes for port 14. +Value After Reset: 0x0 +Exists: UMCTL2_PORT_14==1 + 30 + 1 + read-only + + + WR_PORT_BUSY_13 + Description: Indicates if there are outstanding writes for port 13. +Value After Reset: 0x0 +Exists: UMCTL2_PORT_13==1 + 29 + 1 + read-only + + + WR_PORT_BUSY_12 + Description: Indicates if there are outstanding writes for port 12. +Value After Reset: 0x0 +Exists: UMCTL2_PORT_12==1 + 28 + 1 + read-only + + + WR_PORT_BUSY_11 + Description: Indicates if there are outstanding writes for port 11. +Value After Reset: 0x0 +Exists: UMCTL2_PORT_11==1 + 27 + 1 + read-only + + + WR_PORT_BUSY_10 + Description: Indicates if there are outstanding writes for port 10. +Value After Reset: 0x0 +Exists: UMCTL2_PORT_10==1 + 26 + 1 + read-only + + + WR_PORT_BUSY_9 + Description: Indicates if there are outstanding writes for port 9. +Value After Reset: 0x0 +Exists: UMCTL2_PORT_9==1 + 25 + 1 + read-only + + + WR_PORT_BUSY_8 + Description: Indicates if there are outstanding writes for port 8. +Value After Reset: 0x0 +Exists: UMCTL2_PORT_8==1 + 24 + 1 + read-only + + + WR_PORT_BUSY_7 + Description: Indicates if there are outstanding writes for port 7. +Value After Reset: 0x0 +Exists: UMCTL2_PORT_7==1 + 23 + 1 + read-only + + + WR_PORT_BUSY_6 + Description: Indicates if there are outstanding writes for port 6. +Value After Reset: 0x0 +Exists: UMCTL2_PORT_6==1 + 22 + 1 + read-only + + + WR_PORT_BUSY_5 + Description: Indicates if there are outstanding writes for port 5. +Value After Reset: 0x0 +Exists: UMCTL2_PORT_5==1 + 21 + 1 + read-only + + + WR_PORT_BUSY_4 + Description: Indicates if there are outstanding writes for port 4. +Value After Reset: 0x0 +Exists: UMCTL2_PORT_4==1 + 20 + 1 + read-only + + + WR_PORT_BUSY_3 + Description: Indicates if there are outstanding writes for port 3. +Value After Reset: 0x0 +Exists: UMCTL2_PORT_3==1 + 19 + 1 + read-only + + + WR_PORT_BUSY_2 + Description: Indicates if there are outstanding writes for port 2. +Value After Reset: 0x0 +Exists: UMCTL2_PORT_2==1 + 18 + 1 + read-only + + + WR_PORT_BUSY_1 + Description: Indicates if there are outstanding writes for port 1. +Value After Reset: 0x0 +Exists: UMCTL2_PORT_1==1 + 17 + 1 + read-only + + + WR_PORT_BUSY_0 + Description: Indicates if there are outstanding writes for port 0. +Value After Reset: 0x0 +Exists: UMCTL2_PORT_0==1 + 16 + 1 + read-only + + + RD_PORT_BUSY_15 + Description: Indicates if there are outstanding reads for port 15. +Value After Reset: 0x0 +Exists: UMCTL2_PORT_15==1 + 15 + 1 + read-only + + + RD_PORT_BUSY_14 + Description: Indicates if there are outstanding reads for port 14. +Value After Reset: 0x0 +Exists: UMCTL2_PORT_14==1 + 14 + 1 + read-only + + + RD_PORT_BUSY_13 + Description: Indicates if there are outstanding reads for port 13. +Value After Reset: 0x0 +Exists: UMCTL2_PORT_13==1 + 13 + 1 + read-only + + + RD_PORT_BUSY_12 + Description: Indicates if there are outstanding reads for port 12. +Value After Reset: 0x0 +Exists: UMCTL2_PORT_12==1 + 12 + 1 + read-only + + + RD_PORT_BUSY_11 + Description: Indicates if there are outstanding reads for port 11. +Value After Reset: 0x0 +Exists: UMCTL2_PORT_11==1 + 11 + 1 + read-only + + + RD_PORT_BUSY_10 + Description: Indicates if there are outstanding reads for port 10. +Value After Reset: 0x0 +Exists: UMCTL2_PORT_10==1 + 10 + 1 + read-only + + + RD_PORT_BUSY_9 + Description: Indicates if there are outstanding reads for port 9. +Value After Reset: 0x0 +Exists: UMCTL2_PORT_9==1 + 9 + 1 + read-only + + + RD_PORT_BUSY_8 + Description: Indicates if there are outstanding reads for port 8. +Value After Reset: 0x0 +Exists: UMCTL2_PORT_8==1 + 8 + 1 + read-only + + + RD_PORT_BUSY_7 + Description: Indicates if there are outstanding reads for port 7. +Value After Reset: 0x0 +Exists: UMCTL2_PORT_7==1 + 7 + 1 + read-only + + + RD_PORT_BUSY_6 + Description: Indicates if there are outstanding reads for port 6. +Value After Reset: 0x0 +Exists: UMCTL2_PORT_6==1 + 6 + 1 + read-only + + + RD_PORT_BUSY_5 + Description: Indicates if there are outstanding reads for port 5. +Value After Reset: 0x0 +Exists: UMCTL2_PORT_5==1 + 5 + 1 + read-only + + + RD_PORT_BUSY_4 + Description: Indicates if there are outstanding reads for port 4. +Value After Reset: 0x0 +Exists: UMCTL2_PORT_4==1 + 4 + 1 + read-only + + + RD_PORT_BUSY_3 + Description: Indicates if there are outstanding reads for port 3. +Value After Reset: 0x0 +Exists: UMCTL2_PORT_3==1 + 3 + 1 + read-only + + + RD_PORT_BUSY_2 + Description: Indicates if there are outstanding reads for port 2. +Value After Reset: 0x0 +Exists: UMCTL2_PORT_2==1 + 2 + 1 + read-only + + + RD_PORT_BUSY_1 + Description: Indicates if there are outstanding reads for port 1. +Value After Reset: 0x0 +Exists: UMCTL2_PORT_1==1 + 1 + 1 + read-only + + + RD_PORT_BUSY_0 + Description: Indicates if there are outstanding reads for port 0. +Value After Reset: 0x0 +Exists: UMCTL2_PORT_0==1 + 0 + 1 + read-only + + + + + PCCFG + Description: Port Common Configuration Register + 0x400 + 32 + 0x00000000 + 0x00000011 + + + PAGEMATCH_LIMIT + Description: Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. +Value After Reset: 0x0 +Exists: Always + 4 + 1 + read-write + + + GO2CRITICAL_EN + Description: If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_rd signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_rd signals at DDRC are driven to 1b'0. +Value After Reset: 0x0 +Exists: Always + 0 + 1 + read-write + + + + + 16 + 0xb0 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + PCFG[%s] + no description available + 0x404 + + R + Description: Port n Configuration Read Register + 0x0 + 32 + 0x00004000 + 0x000073FF + + + RD_PORT_PAGEMATCH_EN + Description: If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (i.e. same bank and same row). See also related PCCFG.pagematch_limit register. +Value After Reset: "(MEMC_DDR4_EN==1) ? 0x0 : 0x1" +Exists: Always + 14 + 1 + read-write + + + RD_PORT_URGENT_EN + Description: If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_rd signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). +Value After Reset: 0x0 +Exists: Always + 13 + 1 + read-write + + + RD_PORT_AGING_EN + Description: If set to 1, enables aging function for the read channel of the port. +Value After Reset: 0x0 +Exists: Always + 12 + 1 + read-write + + + RD_PORT_PRIORITY + Description: Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority will increase as the higher significant 5-bits of the counter starts to decrease. +When the aging counter becomes 0, the corresponding port channel will have the highest priority level (timeout condition +- Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: The two LSBs of this register field are tied internally to 2'b00. +Value After Reset: 0x0 +Exists: Always + 0 + 10 + read-write + + + + + W + Description: Port n Configuration Write Register + 0x4 + 32 + 0x00004000 + 0x000073FF + + + WR_PORT_PAGEMATCH_EN + Description: If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (i.e. same bank and same row). See also related PCCFG.pagematch_limit register. +Value After Reset: 0x1 +Exists: Always + 14 + 1 + read-write + + + WR_PORT_URGENT_EN + Description: If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). +Value After Reset: 0x0 +Exists: Always + 13 + 1 + read-write + + + WR_PORT_AGING_EN + Description: If set to 1, enables aging function for the write channel of the port. +Value After Reset: 0x0 +Exists: Always + 12 + 1 + read-write + + + WR_PORT_PRIORITY + Description: Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the +write channel of a given port. Port's priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. Note: The two LSBs of this register field are tied internally to 2'b00. +Value After Reset: 0x0 +Exists: Always + 0 + 10 + read-write + + + + + C + Description: Port n Common Configuration Register + 0x8 + 32 + 0x00000000 + 0x00000003 + + + AHB_ENDIANNESS + Description: If set to 0, enables support for little endian on the AHB port. If set to 1, enables support for big endian (BE- 32) on the AHB port. If set to 2, enables support for big endian (BE-A) on the AHB port. +Value After Reset: 0x0 +Exists: UMCTL2_A_AHB_n==1 + 0 + 2 + read-write + + + + + 16 + 0x8 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + ID[%s] + no description available + 0xc + + MASKCH + Description: Port n Channel m Configuration ID Mask Register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + ID_MASK + Description: Determines the mask used in the ID mapping function for virtual channel m. +Value After Reset: 0x0 +Exists: Always + 0 + 32 + read-write + + + + + VALUECH + Description: Port n Channel m Configuration ID Value Register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + ID_VALUE + Description: Determines the value used in the ID mapping function for virtual channel m. +Value After Reset: 0x0 +Exists: Always + 0 + 32 + read-write + + + + + + CTRL + Description: Port n Control Register + 0x8c + 32 + 0x00000000 + 0x00000001 + + + PORT_EN + Description: Enables port n. +Value After Reset: "UMCTL2_PORT_EN_RESET_VALUE" +Exists: Always + 0 + 1 + read-write + + + + + QOS0 + Description: Port n Read QoS Configuration Register 0 + 0x90 + 32 + 0x00000000 + 0x0033000F + + + RQOS_MAP_REGION1 + Description: This bitfield indicates the traffic class of region +1. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR) then VPR traffic is aliased to LPR traffic. +Value After Reset: 0x0 +Exists: Always + 20 + 2 + read-write + + + RQOS_MAP_REGION0 + Description: This bitfield indicates the traffic class of region +0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR) then VPR traffic is aliased to LPR traffic. +Value After Reset: 0x0 +Exists: Always + 16 + 2 + read-write + + + RQOS_MAP_LEVEL1 + Description: Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13(for dual RAQ) or 0 to 14(for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinct values. +Value After Reset: 0x0 +Exists: Always + 0 + 4 + read-write + + + + + QOS1 + Description: Port n Read QoS Configuration Register 1 + 0x94 + 32 + 0x00000000 + 0x07FF07FF + + + RQOS_MAP_TIMEOUTR + Description: Specifies the timeout value for transactions mapped to the red address queue. +Value After Reset: 0x0 +Exists: Always + 16 + 11 + read-write + + + RQOS_MAP_TIMEOUTB + Description: Specifies the timeout value for transactions mapped to the blue address queue. +Value After Reset: 0x0 +Exists: Always + 0 + 11 + read-write + + + + + WQOS0 + Description: Port n Write QoS Configuration Register 0 + 0x98 + 32 + 0x00000000 + 0x0033000F + + + WQOS_MAP_REGION1 + Description: This bitfield indicates the traffic class of region +1. Valid values are: +0: NPW +1: VPW +When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW) then VPW traffic is aliased to NPW traffic. +Value After Reset: 0x0 +Exists: Always + 20 + 2 + read-write + + + WQOS_MAP_REGION0 + Description: This bitfield indicates the traffic class of region +0. Valid values are: +0: NPW +1: VPW +When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region0 is set to 1 (VPW) then VPW traffic is aliased to NPW traffic. +Value After Reset: 0x0 +Exists: Always + 16 + 2 + read-write + + + WQOS_MAP_LEVEL + Description: Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which corresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value corresponds to higher port priority. +Value After Reset: 0x0 +Exists: Always + 0 + 4 + read-write + + + + + WQOS1 + Description: Port n Write QoS Configuration Register 1 + 0x9c + 32 + 0x00000000 + 0x000007FF + + + WQOS_MAP_TIMEOUT + Description: Specifies the timeout value for write transactions. +Value After Reset: 0x0 +Exists: Always + 0 + 11 + read-write + + + + + + 4 + 0x8 + 0,1,2,3 + SAR[%s] + no description available + 0xf04 + + BASE + Description: SAR Base Address Register n + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + BASE_ADDR + Description: Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). +Value After Reset: 0x0 +Exists: Always + 0 + 32 + read-write + + + + + SIZE + Description: SAR Size Register n + 0x4 + 32 + 0x00000000 + 0x000000FF + + + NBLOCKS + Description: Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block size as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. +Value After Reset: 0x0 +Exists: Always + 0 + 8 + read-write + + + + + + SBRCTL + Description: Scrubber Control Register + 0xf24 + 32 + 0x0000FF10 + 0x001FFF77 + + + SCRUB_INTERVAL + Description: Scrub interval. (512 x scrub_interval) number of clock cycles between two scrub read commands. If set to 0, scrub commands are issued back-to-back. This mode of operation (scrub_interval=0) can typically be used for scrubbing the full range of memory at once before or after SW controlled low power operations. After completing the full range of scrub while scrub_interval=0, scrub_done register is set and sbr_done_intr interrupt signal is asserted. +Value After Reset: 0xff +Exists: UMCTL2_SBR_EN_1==1 + 8 + 13 + read-write + + + SCRUB_BURST + Description: Scrub burst count. Determines the number of back-to-back scrub read commands that can be issued together when the controller is in one of the HW controlled low power modes. During low power, the period of the scrub burst becomes \"scrub_burst*scrub_interval\" cycles. +During normal operation mode of the controller (ie. not in power-down or self refresh), scrub_burst is ignored and only one scrub command is generated. Valid values are: 1: 1 read, 2: 4 reads, 3: 16 reads, 4: 64 reads, 5: 256 reads, +6: 1024 reads. +Value After Reset: 0x1 +Exists: UMCTL2_SBR_EN_1==1 + 4 + 3 + read-write + + + SCRUB_MODE + Description: scrub_mode:0 ECC scrubber will perform reads scrub_mode:1 ECC scrubber will perform writes Value After Reset: 0x0 +Exists: UMCTL2_SBR_EN_1==1 + 2 + 1 + read-write + + + SCRUB_DURING_LOWPOWER + Description: Continue scrubbing during low power. If set to 1, burst of scrubs will be issued in HW controlled low power modes. There are two such modes: automatically initiated by idleness or initiated by HW low-power (LP) interface. If set to 0, the scrubber will not attempt to send commands while the DDRC is in HW controlled low power modes. In this case, the scrubber will remember the last address issued and will automatically continue from there when the DDRC exits the LP mode. +Value After Reset: 0x0 +Exists: UMCTL2_SBR_EN_1==1 + 1 + 1 + read-write + + + SCRUB_EN + Description: Enable ECC scrubber. If set to 1, enables the scrubber to generate background read commands after the memories are initialized. If set to 0, disables the scrubber, resets the address generator to 0 and clears the scrubber status. This bitfield must be accessed separately from the other bitfields in this register. +Value After Reset: 0x0 +Exists: UMCTL2_SBR_EN_1==1 + 0 + 1 + read-write + + + + + SBRSTAT + Description: Scrubber Status Register + 0xf28 + 32 + 0x00000000 + 0x00000003 + + + SCRUB_DONE + Description: Scrubber done. Controller sets this bit to 1, after full range of addresses are scrubbed once while scrub_interval is set to 0. Cleared if scrub_en is set to 0 (scrubber disabled) or scrub_interval is set to a non-zero value for normal scrub operation. The interrupt signal, sbr_done_intr, is equivalent to this status bitfield. +Value After Reset: 0x0 +Exists: UMCTL2_SBR_EN_1==1 + 1 + 1 + read-only + + + SCRUB_BUSY + Description: Scrubber busy. Controller sets this bit to 1 when the scrubber logic has outstanding read commands being executed. Cleared when there are no active outstanding scrub reads in the system. +Value After Reset: 0x0 +Exists: UMCTL2_SBR_EN_1==1 + 0 + 1 + read-only + + + + + SBRWDATA0 + Description: Scrubber Write Data Pattern0 + 0xf2c + 32 + 0x00000000 + 0xFFFFFFFF + + + SCRUB_PATTERN0 + Description: ECC Scrubber write data pattern for data bus[31:0] +Value After Reset: 0x0 +Exists: UMCTL2_SBR_EN_1==1 + 0 + 32 + read-write + + + + + + + FFA + FFA + FFA + 0xf3018000 + + 0x0 + 0x48 + registers + + + + CTRL + No description available + 0x0 + 32 + 0x00000000 + 0x80000001 + + + SFTRST + software reset the module if asserted to be 1. +EN is only active after this bit is zero. + 31 + 1 + read-write + + + EN + Asserted to enable the module + 0 + 1 + read-write + + + + + STATUS + No description available + 0x4 + 32 + 0x00000000 + 0x000000FF + + + FIR_OV + FIR Overflow err + 7 + 1 + write-only + + + FFT_OV + FFT Overflow Err + 6 + 1 + write-only + + + WR_ERR + AXI Data Write Error + 5 + 1 + write-only + + + RD_NXT_ERR + AXI Read Bus Error for NXT DATA + 4 + 1 + write-only + + + RD_ERR + AXI Data Read Error + 3 + 1 + write-only + + + NXT_CMD_RD_DONE + Indicate that next command sequence is already read into the module. + 1 + 1 + write-only + + + OP_CMD_DONE + Indicate that operation cmd is done, and data are available in system memory. + 0 + 1 + write-only + + + + + INT_EN + No description available + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + WRSV1 + Reserved + 8 + 24 + read-write + + + FIR_OV + FIR Overflow err + 7 + 1 + read-write + + + FFT_OV + FFT Overflow Err + 6 + 1 + read-write + + + WR_ERR + Enable Data Write Error interrupt + 5 + 1 + read-write + + + RD_NXT_ERR + Enable Read Bus Error for NXT DATA interrupt + 4 + 1 + read-write + + + RD_ERR + Enable Data Read Error interrupt + 3 + 1 + read-write + + + NXT_CMD_RD_DONE + Indicate that next command sequence is already read into the module. + 1 + 1 + read-write + + + OP_CMD_DONE + Indicate that operation cmd is done, and data are available in system memory. + 0 + 1 + read-write + + + + + OP_CTRL + No description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + NXT_ADDR + The address for the next command. +It will be processed after CUR_CMD is executed and done.. + 2 + 30 + read-write + + + NXT_EN + Whether NXT_CMD is enabled. +Asserted to enable the NXT_CMD when CUR_CMD is done, or CUR_CMD is not enabled.. + 1 + 1 + read-write + + + EN + Whether CUR_CMD is enabled. +Asserted to enable the CUR_CMD + 0 + 1 + read-write + + + + + OP_CMD + No description available + 0x24 + 32 + 0x00000000 + 0x01FFFEFF + + + CONJ_C + asserted to have conjuate value for coefs in computation + 24 + 1 + read-write + + + CMD + The Command Used: +0: FIR +2: FFT +Others: Reserved + 18 + 6 + read-write + + + OUTD_TYPE + Output data type: +0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 +4:complex sp float 5: real sp float + 15 + 3 + read-write + + + COEF_TYPE + Coef data type (used for FIR): +0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 +4:complex sp float 5: real sp float + 12 + 3 + read-write + + + IND_TYPE + Input data type: +0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 +4:complex sp float 5: real sp float + 9 + 3 + read-write + + + NXT_CMD_LEN + The length of nxt commands in 32-bit words + 0 + 8 + read-write + + + + + OP_REG0 + No description available + UNION_28 + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + CT + Contents + 0 + 32 + read-write + + + + + OP_FIR_MISC + No description available + UNION_28 + 0x28 + 32 + 0x00000000 + 0x00003FFF + + + FIR_COEF_TAPS + Length of FIR coefs （max 256） + 0 + 14 + read-write + + + + + OP_FFT_MISC + No description available + UNION_28 + 0x28 + 32 + 0x00000000 + 0x000007FF + + + FFT_LEN + FFT length +0:8, +..., +n:2^(3+n) + 7 + 4 + read-write + + + IFFT + Asserted to indicate IFFT + 6 + 1 + read-write + + + TMP_BLK + Memory block for indata. Should be assigned as 1 + 2 + 2 + read-write + + + IND_BLK + Memory block for indata. Should be assigned as 0 + 0 + 2 + read-write + + + + + OP_REG1 + No description available + UNION_2C + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + CT + Contents + 0 + 32 + read-write + + + + + OP_FIR_MISC1 + No description available + UNION_2C + 0x2c + 32 + 0x00000000 + 0x003FFFFF + + + OUTD_MEM_BLK + Should be assigned as 0 + 20 + 2 + read-write + + + COEF_MEM_BLK + Should be assigned as 1 + 18 + 2 + read-write + + + IND_MEM_BLK + Should be assigned as 2 + 16 + 2 + read-write + + + FIR_DATA_TAPS + The input data data length + 0 + 16 + read-write + + + + + OP_REG2 + No description available + UNION_30 + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + CT + Contents + 0 + 32 + read-write + + + + + OP_FFT_INRBUF + No description available + UNION_30 + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOC + The input (real) data buffer pointer + 0 + 32 + read-write + + + + + OP_REG3 + No description available + UNION_34 + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + CT + Contents + 0 + 32 + read-write + + + + + OP_FIR_INBUF + No description available + UNION_34 + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOC + The input data buffer pointer + 0 + 32 + read-write + + + + + OP_REG4 + No description available + UNION_38 + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + CT + Contents + 0 + 32 + read-write + + + + + OP_FIR_COEFBUF + No description available + UNION_38 + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOC + The coef buf pointer + 0 + 32 + read-write + + + + + OP_FFT_OUTRBUF + No description available + UNION_38 + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOC + The output (real) data buffer pointer + 0 + 32 + read-write + + + + + OP_REG5 + No description available + UNION_3C + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + CT + Contents + 0 + 32 + read-write + + + + + OP_FIR_OUTBUF + No description available + UNION_3C + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + LOC + The output data buffer pointer. The length of the output buffer should be （FIR_DATA_TAPS - FIR_COEF_TAPS + 1） + 0 + 32 + read-write + + + + + OP_REG6 + No description available + 0x40 + 32 + 0x00000000 + 0xFFFFFFFF + + + CT + Contents + 0 + 32 + read-write + + + + + OP_REG7 + No description available + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + CT + Contents + 0 + 32 + read-write + + + + + + + SDP + SDP + SDP + 0xf3040000 + + 0x0 + 0x60 + registers + + + + SDPCR + SDP control register + 0x0 + 32 + 0x30000000 + 0xFFFE0101 + + + SFTRST + soft reset. +Write 1 then 0, to reset the SDP block. + 31 + 1 + read-write + + + CLKGAT + Clock Gate for the SDP main logic. +Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block. + 30 + 1 + read-write + + + CIPDIS + Cipher Disable, read the info, whether the CIPHER features is besing disable in this chip or not. +1, Cipher is disabled in this chip. +0, Cipher is enabled in this chip. + 29 + 1 + read-only + + + HASDIS + HASH Disable, read the info, whether the HASH features is besing disable in this chip or not. +1, HASH is disabled in this chip. +0, HASH is enabled in this chip. + 28 + 1 + read-only + + + CIPHEN + Cipher Enablement, controlled by SW. +1, Cipher is Enabled. +0, Cipher is Disabled. + 23 + 1 + read-write + + + HASHEN + HASH Enablement, controlled by SW. +1, HASH is Enabled. +0, HASH is Disabled. + 22 + 1 + read-write + + + MCPEN + Memory Copy Enablement, controlled by SW. +1, Memory copy is Enabled. +0, Memory copy is Disabled. + 21 + 1 + read-write + + + CONFEN + Constant Fill to memory, controlled by SW. +1, Constant fill is Enabled. +0, Constant fill is Disabled. + 20 + 1 + read-write + + + DCRPDI + Decryption Disable bit, Write to 1 to disable the decryption. + 19 + 1 + read-write + + + TSTPKT0IRQ + Test purpose for interrupt when Packet counter reachs "0", but CHAIN=1 in the current packet. + 17 + 1 + read-write + + + RDSCEN + when set to "1", the 1st data packet descriptor loacted in the register(CMDPTR, NPKTPTR, ...) +when set to "0", the 1st data packet descriptor loacted in the memeory(pointed by CMDPTR) + 8 + 1 + read-write + + + INTEN + Interrupt Enablement, controlled by SW. +1, SDP interrupt is enabled. +0, SDP interrupt is disabled. + 0 + 1 + read-write + + + + + MODCTRL + Mod control register. + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + AESALG + AES algorithem selection. +0x0 = AES 128; +0x1 = AES 256; +0x8 = SM4； +Others, reserved. + 28 + 4 + read-write + + + AESMOD + AES mode selection. +0x0 = ECB; +0x1 = CBC; +Others, reserved. + 24 + 4 + read-write + + + AESKS + AES Key Selection. +These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following: +0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key. +0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. +.... +0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key. +0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. +0x20: kman_sk0[127:0] from the key manager for AES128; AES256 will use kman_sk0[255:0] as AES key. +0x21: kman_sk0[255:128] from the key manager for AES128; not valid for AES256. +0x22: kman_sk1[127:0] from the key manager for AES128; AES256 will use kman_sk1[255:0] as AES key. +0x23: kman_sk1[255:128] from the key manager for AES128; not valid for AES256. +0x24: kman_sk2[127:0] from the key manager for AES128; AES256 will use kman_sk2[255:0] as AES key. +0x25: kman_sk2[255:128] from the key manager for AES128; not valid for AES256. +0x26: kman_sk3[127:0] from the key manager for AES128; AES256 will use kman_sk3[255:0] as AES key. +0x27: kman_sk3[255:128] from the key manager for AES128; not valid for AES256. +0x30: exip0_key[127:0] from OTP for AES128; AES256 will use exip0_key[255:0] as AES key. +0x31: exip0_key[255:128] from OTP for AES128; not valid for AES256. +0x32: exip1_key[127:0] from OTP for AES128; AES256 will use exip1_key[255:0] as AES key. +0x33: exip1_key[255:128] from OTP for AES128; not valid for AES256. +Other values, reserved. + 18 + 6 + read-write + + + AESDIR + AES direction +1x1, AES Decryption +1x0, AES Encryption. + 16 + 1 + read-write + + + HASALG + HASH Algorithem selection. +0x0 SHA1 — +0x1 CRC32 — +0x2 SHA256 — + 12 + 4 + read-write + + + CRCEN + CRC enable. +1x1, CRC is enabled. +1x0, CRC is disabled. + 11 + 1 + read-write + + + HASCHK + HASH Check Enable Bit. +1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers; +1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result. +For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words. + 10 + 1 + read-write + + + HASOUT + When hashing is enabled, this bit controls the input or output data of the AES engine is hashed. +0 INPUT HASH +1 OUTPUT HASH + 9 + 1 + read-write + + + DINSWP + Decide whether the SDP byteswaps the input data (big-endian data); +When all bits are set, the data is assumed to be in the big-endian format + 4 + 2 + read-write + + + DOUTSWP + Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format + 2 + 2 + read-write + + + KEYSWP + Decide whether the SDP byteswaps the Key (big-endian data). +When all bits are set, the data is assumed to be in the big-endian format + 0 + 2 + read-write + + + + + PKTCNT + packet counter registers. + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTVAL + This read-only field shows the current (instantaneous) value of the packet counter + 16 + 8 + read-only + + + CNTINCR + The value written to this field is added to the spacket count. + 0 + 8 + read-write + + + + + STA + Status Registers + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + TAG + packet tag. + 24 + 8 + read-only + + + IRQ + interrupt Request, requested when error happen, or when packet processing done, packet counter reach to zero. + 23 + 1 + write-only + + + CHN1PKT0 + the chain buffer "chain" bit is "1", while packet counter is "0", now, waiting for new buffer data. + 20 + 1 + write-only + + + AESBSY + AES Busy + 19 + 1 + read-only + + + HASBSY + Hashing Busy + 18 + 1 + read-only + + + PKTCNT0 + Packet Counter registers reachs to ZERO now. + 17 + 1 + write-only + + + PKTDON + Packet processing done, will trigger this itnerrrupt when the "PKTINT" bit set in the packet control word. + 16 + 1 + write-only + + + ERRSET + Working mode setup error. + 5 + 1 + write-only + + + ERRPKT + Packet head access error, or status update error. + 4 + 1 + write-only + + + ERRSRC + Source Buffer Access Error + 3 + 1 + write-only + + + ERRDST + Destination Buffer Error + 2 + 1 + write-only + + + ERRHAS + Hashing Check Error + 1 + 1 + write-only + + + ERRCHAIN + buffer chain error happen when packet's CHAIN bit=0, but the Packet counter is still not zero. + 0 + 1 + write-only + + + + + KEYADDR + Key Address + 0x10 + 32 + 0x00000040 + 0xFFFFFFFF + + + INDEX + To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. +Key index pointer. The valid indices are 0-[number_keys]. +In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses. + 16 + 8 + read-write + + + SUBWRD + Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field +increments; To write a key, the software must first write the desired key index/subword to this register. + 0 + 2 + read-write + + + + + KEYDAT + Key Data + 0x14 + 32 + 0x00000030 + 0xFFFFFFFF + + + KEYDAT + This register provides the write access to the key/key subword specified by the key index register. +Writing this location updates the selected subword for the key located at the index +specified by the key index register. The write also triggers the SUBWORD field of the +KEY register to increment to the next higher word in the key + 0 + 32 + read-write + + + + + 4 + 0x4 + CIPHIV0,CIPHIV1,CIPHIV2,CIPHIV3 + CIPHIV[%s] + no description available + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + CIPHIV + cipher initialization vector. + 0 + 32 + read-write + + + + + 8 + 0x4 + HASWRD0,HASWRD1,HASWRD2,HASWRD3,HASWRD4,HASWRD5,HASWRD6,HASWRD7 + HASWRD[%s] + no description available + 0x28 + 32 + 0x00000030 + 0xFFFFFFFF + + + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + 0 + 32 + read-write + + + + + CMDPTR + Command Pointer + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMDPTR + current command addresses the register points to the multiword +descriptor that is to be executed (or is currently being executed) + 0 + 32 + read-write + + + + + NPKTPTR + Next Packet Address Pointer + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + NPKTPTR + Next Packet Address Pointer + 0 + 32 + read-write + + + + + PKTCTL + Packet Control Registers + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTTAG + packet tag + 24 + 8 + read-write + + + CIPHIV + Load Initial Vector for the AES in this packet. + 6 + 1 + read-write + + + HASFNL + Hash Termination packet + 5 + 1 + read-write + + + HASINI + Hash Initialization packat + 4 + 1 + read-write + + + CHAIN + whether the next command pointer register must be loaded into the channel's current descriptor +pointer. + 3 + 1 + read-write + + + DCRSEMA + whether the channel's semaphore must be decremented at the end of the current operation. +When the semaphore reaches a value of zero, no more operations are issued from the channel. + 2 + 1 + read-write + + + PKTINT + Reflects whether the channel must issue an interrupt upon the completion of the packet + 1 + 1 + read-write + + + + + PKTSRC + Packet Memory Source Address + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTSRC + Packet Memory Source Address + 0 + 32 + read-write + + + + + PKTDST + Packet Memory Destination Address + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTDST + Packet Memory Destination Address + 0 + 32 + read-write + + + + + PKTBUF + Packet buffer size. + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTBUF + No description available + 0 + 32 + read-write + + + + + + + SEC + SEC + SEC + 0xf3044000 + + 0x0 + 0x18 + registers + + + + SECURE_STATE + Secure state + 0x0 + 32 + 0x00000000 + 0x000300F0 + + + ALLOW_NSC + Non-secure state allow +0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter non-secure state + 17 + 1 + read-only + + + ALLOW_SEC + Secure state allow +0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter secure state + 16 + 1 + read-only + + + PMIC_FAIL + PMIC secure state one hot indicator +0: secure state is not in fail state +1: secure state is in fail state + 7 + 1 + read-write + + + PMIC_NSC + PMIC secure state one hot indicator +0: secure state is not in non-secure state +1: secure state is in non-secure state + 6 + 1 + read-write + + + PMIC_SEC + PMIC secure state one hot indicator +0: secure state is not in secure state +1: secure state is in secure state + 5 + 1 + read-write + + + PMIC_INS + PMIC secure state one hot indicator +0: secure state is not in inspect state +1: secure state is in inspect state + 4 + 1 + read-write + + + + + SECURE_STATE_CONFIG + secure state configuration + 0x4 + 32 + 0x00000000 + 0x00000009 + + + LOCK + Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset +0: not locked, register can be modified +1: register locked, write access to the register is ignored + 3 + 1 + read-write + + + ALLOW_RESTART + allow secure state restart from fail state +0: restart is not allowed, only hardware reset can recover secure state +1: software is allowed to switch to inspect state from fail state + 0 + 1 + read-write + + + + + VIOLATION_CONFIG + Security violation config + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 0 + 15 + read-write + + + + + ESCALATE_CONFIG + Escalate behavior on security event + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 0 + 15 + read-write + + + + + EVENT + Event and escalate status + 0x10 + 32 + 0x00000000 + 0xFFFF000C + + + EVENT + local event statue, each bit represents one security event + 16 + 16 + read-only + + + PMIC_ESC_NSC + PMIC is escalating non-secure event + 3 + 1 + read-only + + + PMIC_ESC_SEC + PMIC is escalting secure event + 2 + 1 + read-only + + + + + LIFECYCLE + Lifecycle + 0x14 + 32 + 0x00000000 + 0x000000FF + + + LIFECYCLE + lifecycle status, +bit7: lifecycle_debate, +bit6: lifecycle_scribe, +bit5: lifecycle_no_ret, +bit4: lifecycle_return, +bit3: lifecycle_secure, +bit2: lifecycle_nonsec, +bit1: lifecycle_create, +bit0: lifecycle_unknow + 0 + 8 + read-only + + + + + + + MON + MON + MON + 0xf3048000 + + 0x0 + 0x48 + registers + + + + 4 + 0x8 + glitch0,glitch1,clock0,clock1 + MONITOR[%s] + no description available + 0x0 + + CONTROL + Glitch and clock monitor control + 0x0 + 32 + 0x00000000 + 0x00000011 + + + ACTIVE + select glitch works in active mode or passve mode. +0: passive mode, depends on power glitch destroy DFF value +1: active mode, check glitch by DFF chain + 4 + 1 + read-write + + + ENABLE + enable glitch detector +0: detector disabled +1: detector enabled + 0 + 1 + read-write + + + + + STATUS + Glitch and clock monitor status + 0x4 + 32 + 0x00000000 + 0x00000001 + + + FLAG + flag for glitch detected, write 1 to clear this flag +0: glitch not detected +1: glitch detected + 0 + 1 + read-write + + + + + + IRQ_FLAG + No description available + 0x40 + 32 + 0x00000000 + 0x0000000F + + + FLAG + interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag +0: no monitor interrupt +1: monitor interrupt happened + 0 + 4 + read-write + + + + + IRQ_ENABLE + No description available + 0x44 + 32 + 0x00000000 + 0x0000000F + + + ENABLE + interrupt enable, each bit represents for one monitor +0: monitor interrupt disabled +1: monitor interrupt enabled + 0 + 4 + read-write + + + + + + + RNG + RNG + RNG + 0xf304c000 + + 0x0 + 0x40 + registers + + + + CMD + Command Register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SFTRST + Soft Reset, Perform a software reset of the RNG This bit is self-clearing. +0 Do not perform a software reset. +1 Software reset + 6 + 1 + read-write + + + CLRERR + Clear the Error, clear the errors in the ESR register and the RNG interrupt. This bit is self-clearing. +0 Do not clear the errors and the interrupt. +1 Clear the errors and the interrupt. + 5 + 1 + read-write + + + CLRINT + Clear the Interrupt, clear the RNG interrupt if an error is not present. This bit is self-clearing. +0 Do not clear the interrupt. +1 Clear the interrupt + 4 + 1 + read-write + + + GENSD + Generate Seed, when both ST and GS triggered, ST first and GS next. + 1 + 1 + read-write + + + SLFCHK + Self Test, when both ST and GS triggered, ST first and GS next. + 0 + 1 + read-write + + + + + CTRL + Control Register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + MIRQERR + Mask Interrupt Request for Error + 6 + 1 + read-write + + + MIRQDN + Mask Interrupt Request for Done Event, asks the interrupts generated upon the completion of the seed and self-test modes. The status of these jobs can be viewed by: +• Reading the STA and viewing the seed done and the self-test done bits (STA[SDN, STDN]). +• Viewing the RNG_CMD for the generate-seed or the self-test bits (CMD[GS,ST]) being set, indicating that the operation is still taking place. + 5 + 1 + read-write + + + AUTRSD + Auto Reseed + 4 + 1 + read-write + + + FUFMOD + FIFO underflow response mode +00 Return all zeros and set the ESR[FUFE]. +01 Return all zeros and set the ESR[FUFE]. +10 Generate the bus transfer error +11 Generate the interrupt and return all zeros (overrides the CTRL[MASKERR]). + 0 + 2 + read-write + + + + + STA + Status Register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SCPF + Self Check Pass Fail + 21 + 3 + read-only + + + FUNCERR + Error was detected, check ESR register for details + 16 + 1 + read-only + + + FSIZE + Fifo Size, it is 5 in this design. + 12 + 4 + read-only + + + FRNNU + Fifo Level, Indicates the number of random words currently in the output FIFO + 8 + 4 + read-only + + + NSDDN + New seed done. + 6 + 1 + read-only + + + FSDDN + 1st Seed done +When "1", Indicates that the RNG generated the first seed. + 5 + 1 + read-only + + + SCDN + Self Check Done +Indicates whether Self Test is done or not. Can be cleared by the hardware reset or a new self test is +initiated by setting the CMD[ST]. +0 Self test not completed +1 Completed a self test since the last reset. + 4 + 1 + read-only + + + RSDREQ + Reseed needed +Indicates that the RNG needs to be reseeded. This is done by setting the CMD[GS], or +automatically if the CTRL[ARS] is set. + 3 + 1 + read-only + + + IDLE + Idle, the RNG is in the idle mode, and internal clocks are disabled, in this mode, access to the FIFO is allowed. Once the FIFO is empty, the RNGB fills the FIFO and then enters idle mode again. + 2 + 1 + read-only + + + BUSY + when 1, means the RNG engine is busy for seeding or random number generation, self test and so on. + 1 + 1 + read-only + + + + + ERR + Error Registers + 0xc + 32 + 0x00000000 + 0xFFFFFF3F + + + FUFE + FIFO access error(underflow) + 5 + 1 + read-only + + + SCKERR + Self-test error +Indicates that the RNG failed the most recent self test. This bit is sticky and can only be reset by a +hardware reset or by writing 1 to the CMD[CE] + 3 + 1 + read-only + + + + + FO2B + FIFO out to bus/cpu + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2B + SW read the FIFO output. + 0 + 32 + read-only + + + + + 8 + 0x4 + FO2S0,FO2S1,FO2S2,FO2S3,FO2S4,FO2S5,FO2S6,FO2S7 + R2SK[%s] + no description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2S0 + FIFO out to KMAN, will be SDP engine key. + 0 + 32 + read-only + + + + + + + OTP + OTP + OTP + 0xf3050000 + + 0x0 + 0xc08 + registers + + + + 128 + 0x4 + SHADOW000,SHADOW001,SHADOW002,SHADOW003,SHADOW004,SHADOW005,SHADOW006,SHADOW007,SHADOW008,SHADOW009,SHADOW010,SHADOW011,SHADOW012,SHADOW013,SHADOW014,SHADOW015,SHADOW016,SHADOW017,SHADOW018,SHADOW019,SHADOW020,SHADOW021,SHADOW022,SHADOW023,SHADOW024,SHADOW025,SHADOW026,SHADOW027,SHADOW028,SHADOW029,SHADOW030,SHADOW031,SHADOW032,SHADOW033,SHADOW034,SHADOW035,SHADOW036,SHADOW037,SHADOW038,SHADOW039,SHADOW040,SHADOW041,SHADOW042,SHADOW043,SHADOW044,SHADOW045,SHADOW046,SHADOW047,SHADOW048,SHADOW049,SHADOW050,SHADOW051,SHADOW052,SHADOW053,SHADOW054,SHADOW055,SHADOW056,SHADOW057,SHADOW058,SHADOW059,SHADOW060,SHADOW061,SHADOW062,SHADOW063,SHADOW064,SHADOW065,SHADOW066,SHADOW067,SHADOW068,SHADOW069,SHADOW070,SHADOW071,SHADOW072,SHADOW073,SHADOW074,SHADOW075,SHADOW076,SHADOW077,SHADOW078,SHADOW079,SHADOW080,SHADOW081,SHADOW082,SHADOW083,SHADOW084,SHADOW085,SHADOW086,SHADOW087,SHADOW088,SHADOW089,SHADOW090,SHADOW091,SHADOW092,SHADOW093,SHADOW094,SHADOW095,SHADOW096,SHADOW097,SHADOW098,SHADOW099,SHADOW100,SHADOW101,SHADOW102,SHADOW103,SHADOW104,SHADOW105,SHADOW106,SHADOW107,SHADOW108,SHADOW109,SHADOW110,SHADOW111,SHADOW112,SHADOW113,SHADOW114,SHADOW115,SHADOW116,SHADOW117,SHADOW118,SHADOW119,SHADOW120,SHADOW121,SHADOW122,SHADOW123,SHADOW124,SHADOW125,SHADOW126,SHADOW127 + SHADOW[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + 8 + 0x4 + LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 + SHADOW_LOCK[%s] + no description available + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + 128 + 0x4 + FUSE000,FUSE001,FUSE002,FUSE003,FUSE004,FUSE005,FUSE006,FUSE007,FUSE008,FUSE009,FUSE010,FUSE011,FUSE012,FUSE013,FUSE014,FUSE015,FUSE016,FUSE017,FUSE018,FUSE019,FUSE020,FUSE021,FUSE022,FUSE023,FUSE024,FUSE025,FUSE026,FUSE027,FUSE028,FUSE029,FUSE030,FUSE031,FUSE032,FUSE033,FUSE034,FUSE035,FUSE036,FUSE037,FUSE038,FUSE039,FUSE040,FUSE041,FUSE042,FUSE043,FUSE044,FUSE045,FUSE046,FUSE047,FUSE048,FUSE049,FUSE050,FUSE051,FUSE052,FUSE053,FUSE054,FUSE055,FUSE056,FUSE057,FUSE058,FUSE059,FUSE060,FUSE061,FUSE062,FUSE063,FUSE064,FUSE065,FUSE066,FUSE067,FUSE068,FUSE069,FUSE070,FUSE071,FUSE072,FUSE073,FUSE074,FUSE075,FUSE076,FUSE077,FUSE078,FUSE079,FUSE080,FUSE081,FUSE082,FUSE083,FUSE084,FUSE085,FUSE086,FUSE087,FUSE088,FUSE089,FUSE090,FUSE091,FUSE092,FUSE093,FUSE094,FUSE095,FUSE096,FUSE097,FUSE098,FUSE099,FUSE100,FUSE101,FUSE102,FUSE103,FUSE104,FUSE105,FUSE106,FUSE107,FUSE108,FUSE109,FUSE110,FUSE111,FUSE112,FUSE113,FUSE114,FUSE115,FUSE116,FUSE117,FUSE118,FUSE119,FUSE120,FUSE121,FUSE122,FUSE123,FUSE124,FUSE125,FUSE126,FUSE127 + FUSE[%s] + no description available + 0x400 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + 8 + 0x4 + LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 + FUSE_LOCK[%s] + no description available + 0x600 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + UNLOCK + UNLOCK + 0x800 + 32 + 0x00000000 + 0xFFFFFFFF + + + UNLOCK + unlock word for fuse array operation +write "OPEN" to unlock fuse array, write any other value will lock write to fuse. +Please make sure 24M crystal is running and 2.5V LDO working properly + 0 + 32 + read-write + + + + + DATA + DATA + 0x804 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + data register for non-blocking access +this register hold dat read from fuse array or data to by programmed to fuse array + 0 + 32 + read-write + + + + + ADDR + ADDR + 0x808 + 32 + 0x00000000 + 0x0000007F + + + ADDR + word address to be read or write + 0 + 7 + read-write + + + + + CMD + CMD + 0x80c + 32 + 0x00000000 + 0xFFFFFFFF + + + CMD + command to access fure array +"BLOW" will update fuse word at ADDR to value hold in DATA +"READ" will fetch fuse value in at ADDR to DATA register + 0 + 32 + read-write + + + + + LOAD_REQ + LOAD Request + 0xa00 + 32 + 0x00000007 + 0x0000000F + + + REQUEST + reload request for 4 regions +bit0: region0 +bit1: region1 +bit2: region2 +bit3: region3 + 0 + 4 + read-write + + + + + LOAD_COMP + LOAD complete + 0xa04 + 32 + 0x00000007 + 0x0000000F + + + COMPLETE + reload complete sign for 4 regions +bit0: region 0 +bit1: region1 +bit2: region2 +bit3: region3 + 0 + 4 + read-write + + + + + 4 + 0x4 + LOAD_REGION0,LOAD_REGION1,LOAD_REGION2,LOAD_REGION3 + REGION[%s] + no description available + 0xa20 + 32 + 0x00000800 + 0x00007F7F + + + STOP + stop address of load region, fuse word at end address will NOT be reloaded +region0: fixed at 8 +region1: fixed at 16 +region2: fixed at 0, +region3: usrer configurable + 8 + 7 + read-write + + + START + start address of load region, fuse word at start address will be reloaded +region0: fixed at 0 +region1: fixed at 8 +region2: fixed at 16, +region3: usrer configurable + 0 + 7 + read-write + + + + + INT_FLAG + interrupt flag + 0xc00 + 32 + 0x00000000 + 0x00000007 + + + WRITE + fuse write flag, write 1 to clear +0: fuse is not written or writing +1: value in DATA register is programmed into fuse + 2 + 1 + read-write + + + READ + fuse read flag, write 1 to clear +0: fuse is not read or reading +1: fuse value is put in DATA register + 1 + 1 + read-write + + + LOAD + fuse load flag, write 1 to clear +0: fuse is not loaded or loading +1: fuse loaded + 0 + 1 + read-write + + + + + INT_EN + interrupt enable + 0xc04 + 32 + 0x00000000 + 0x00000007 + + + WRITE + fuse write interrupt enable +0: fuse write interrupt is not enable +1: fuse write interrupt is enable + 2 + 1 + read-write + + + READ + fuse read interrupt enable +0: fuse read interrupt is not enable +1: fuse read interrupt is enable + 1 + 1 + read-write + + + LOAD + fuse load interrupt enable +0: fuse load interrupt is not enable +1: fuse load interrupt is enable + 0 + 1 + read-write + + + + + + + KEYM + KEYM + KEYM + 0xf3054000 + + 0x0 + 0x50 + registers + + + + 8 + 0x4 + SFK0,SFK1,SFK2,SFK3,SFK4,SFK5,SFK6,SFK7 + SOFTMKEY[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software symmetric key +key will be scambled to 4 variants for software to use, and replicable on same chip. +scramble keys are chip different, and not replicable on different chip +must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 + 0 + 32 + read-write + + + + + 8 + 0x4 + SPK0,SPK1,SPK2,SPK3,SPK4,SPK5,SPK6,SPK7 + SOFTPKEY[%s] + no description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software asymmetric key +key is derived from scrambles of fuse private key, software input key, SRK, and system security status. +This key os read once, sencondary read will read out 0 + 0 + 32 + read-write + + + + + SEC_KEY_CTL + secure key generation + 0x40 + 32 + 0x00000000 + 0x80011117 + + + LOCK_SEC_CTL + block secure state key setting being changed + 31 + 1 + read-write + + + SK_VAL + session key valid +0: session key is all 0's and not usable +1: session key is valid + 16 + 1 + read-only + + + SMK_SEL + software symmetric key selection +0: use origin value in software symmetric key +1: use scramble version of software symmetric key + 12 + 1 + read-write + + + ZMK_SEL + batt symmetric key selection +0: use scramble version of software symmetric key +1: use origin value in software symmetric key + 8 + 1 + read-write + + + FMK_SEL + fuse symmetric key selection +0: use scramble version of fuse symmetric key +1: use alnertave scramble of fuse symmetric key + 4 + 1 + read-write + + + KEY_SEL + secure symmtric key synthesize setting, key is a XOR of following +bit0: fuse mk, 0: not selected, 1:selected +bit1: zmk from batt, 0: not selected, 1:selected +bit2: software key 0: not selected, 1:selected + 0 + 3 + read-write + + + + + NSC_KEY_CTL + non-secure key generation + 0x44 + 32 + 0x00000000 + 0x80011117 + + + LOCK_NSC_CTL + block non-secure state key setting being changed + 31 + 1 + read-write + + + SK_VAL + session key valid +0: session key is all 0's and not usable +1: session key is valid + 16 + 1 + read-only + + + SMK_SEL + software symmetric key selection +0: use scramble version of software symmetric key +1: use origin value in software symmetric key + 12 + 1 + read-write + + + ZMK_SEL + batt symmetric key selection +0: use scramble version of software symmetric key +1: use origin value in software symmetric key + 8 + 1 + read-write + + + FMK_SEL + fuse symmetric key selection +0: use scramble version of fuse symmetric key +1: use origin value in fuse symmetric key + 4 + 1 + read-write + + + KEY_SEL + non-secure symmtric key synthesize setting, key is a XOR of following +bit0: fuse mk, 0: not selected, 1:selected +bit1: zmk from batt, 0: not selected, 1:selected +bit2: software key 0: not selected, 1:selected + 0 + 3 + read-write + + + + + RNG + Random number interface behavior + 0x48 + 32 + 0x00000000 + 0x00010001 + + + BLOCK_RNG_XOR + block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset +0: RNG_XOR can be changed by software +1: RNG_XOR ignore software change from software + 16 + 1 + read-write + + + RNG_XOR + control how SFK is accepted from random number generator +0: SFK value replaced by random number input +1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG + 0 + 1 + read-write + + + + + READ_CONTROL + key read out control + 0x4c + 32 + 0x00000000 + 0x00010001 + + + BLOCK_PK_READ + asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset +0: key can be read out +1: key cannot be read out + 16 + 1 + read-write + + + BLOCK_SMK_READ + symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset +0: key can be read out +1: key cannot be read out + 0 + 1 + read-write + + + + + + + SYSCTL + SYSCTL + SYSCTL + 0xf4000000 + + 0x0 + 0x2c00 + registers + + + + 200 + 0x4 + cpu0,cpx0,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,rsv14,rsv15,rsv16,rsv17,rsv18,rsv19,rsv20,pow_vis,pow_cpu0,pow_gpu,rsv24,rst_soc,rst_con,rst_vis,rst_cpu0,rst_gpu,rsv30,rsv31,clk_src_xtal,clk_src_pll0,clk_src_clk0_pll0,clk_src_pll1,clk_src_clk0_pll1,clk_src_clk1_pll1,clk_src_pll2,clk_src_clk0_pll2,clk_src_clk1_pll2,clk_src_pll3,clk_src_clk0_pll3,clk_src_pll4,clk_src_clk0_pll4,clk_src_pll0_ref,clk_src_pll1_ref,clk_src_pll2_ref,clk_src_pll3_ref,clk_src_pll4_ref,rsv50,rsv51,rsv52,rsv53,rsv54,rsv55,rsv56,rsv57,rsv58,rsv59,rsv60,rsv61,rsv62,rsv63,clk_top_cpu0,clk_top_mct0,clk_top_gpu0,clk_top_axif,clk_top_axis,clk_top_axic,clk_top_axiv,clk_top_axid,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,clk_top_can4,clk_top_can5,clk_top_can6,clk_top_can7,clk_top_lin0,clk_top_lin1,clk_top_lin2,clk_top_lin3,clk_top_lin4,clk_top_lin5,clk_top_lin6,clk_top_lin7,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_urt0,clk_top_urt1,clk_top_urt2,clk_top_urt3,clk_top_urt4,clk_top_urt5,clk_top_urt6,clk_top_urt7,clk_top_tmr0,clk_top_tmr1,clk_top_tmr2,clk_top_tmr3,clk_top_tmr4,clk_top_tmr5,clk_top_tmr6,clk_top_tmr7,clk_top_xpi0,clk_top_xram,clk_top_ana0,clk_top_ana1,clk_top_aud0,clk_top_aud1,clk_top_aud2,clk_top_aud3,clk_top_eth0,clk_top_ptp0,clk_top_sdc0,clk_top_sdc1,clk_top_ntm0,clk_top_ref0,clk_top_ref1,clk_top_cam0,clk_top_cam1,clk_top_lcd0,clk_top_lcd1,clk_top_csi0,clk_top_csi1,clk_top_adc0,clk_top_adc1,clk_top_i2s0,clk_top_i2s1,clk_top_i2s2,clk_top_i2s3,rsv139,rsv140,rsv141,rsv142,rsv143,rsv144,rsv145,rsv146,rsv147,rsv148,rsv149,rsv150,rsv151,rsv152,rsv153,rsv154,rsv155,rsv156,rsv157,rsv158,rsv159,rsv160,rsv161,rsv162,rsv163,rsv164,rsv165,rsv166,rsv167,rsv168,rsv169,rsv170,rsv171,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,axis,axic,axiv,axig,lmm0,mct0,rom0,ddr0,xram,can0,can1,can2,can3,can4,can5,can6,can7,ptpc,crc0,oamp,lin0,lin1,lin2,lin3,lin4,lin5,lin6,lin7,i2c0,i2c1,i2c2,i2c3,spi0,spi1,spi2,spi3,urt0,urt1,urt2,urt3,urt4,urt5,urt6,urt7,wdg0,wdg1,mbx0,mbx1,tmr0,tmr1,tmr2,tmr3,tmr4,tmr5,tmr6,tmr7,i2s0,i2s1,i2s2,i2s3,pdm0,dao0,smix,rng0,sdp0,kman,gpio,adc0,adc1,sdm0,hdma,xdma,xpi0,ffa0,tsns,eth0,usb0,sdc0,sdc1,ntm0,ref0,ref1,cam0,cam1,pdma,jpeg,lcd0,lcd1,gwc0,gwc1,csi0,csi1,dsi0,dsi1,lvb0,lcb0,gpu0 + RESOURCE[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + 4 + 0x10 + link0,link1,link2,link3 + GROUP0[%s] + no description available + 0x800 + + VALUE + Group setting + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + SET + Group setting + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: add periphera into this group，periphera is needed + 0 + 32 + read-write + + + + + CLEAR + Group setting + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: delete periphera in this group，periphera is not needed + 0 + 32 + read-write + + + + + TOGGLE + Group setting + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: toggle the result that whether periphera is needed before + 0 + 32 + read-write + + + + + + 1 + 0x10 + cpu0 + AFFILIATE[%s] + no description available + 0x900 + + VALUE + Affiliate of Group + 0x0 + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0, each bit represents a group +bit0: cpu0 depends on group0 +bit1: cpu0 depends on group1 +bit2: cpu0 depends on group2 +bit3: cpu0 depends on group3 + 0 + 4 + read-write + + + + + SET + Affiliate of Group + 0x4 + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0，each bit represents a group +0: no effect +1: the group is assigned to CPU0 + 0 + 4 + read-write + + + + + CLEAR + Affiliate of Group + 0x8 + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0, each bit represents a group +0: no effect +1: the group is not assigned to CPU0 + 0 + 4 + read-write + + + + + TOGGLE + Affiliate of Group + 0xc + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0, each bit represents a group +0: no effect +1: toggle the result that whether the group is assigned to CPU0 before + 0 + 4 + read-write + + + + + + 1 + 0x10 + cpu0 + RETENTION[%s] + no description available + 0x920 + + VALUE + Retention Control + 0x0 + 32 + 0x00000000 + 0x00007FFF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +bit00: soc_mem is kept on while cpu0 stop +bit01: soc_ctx is kept on while cpu0 stop +bit02: cpu0_mem is kept on while cpu0 stop +bit03: cpu0_ctx is kept on while cpu0 stop +bit04: con_ctx is kept on while cpu0 stop +bit05: vis_mem is kept on while cpu0 stop +bit06: vis_ctx is kept on while cpu0 stop +bit07: gpu_mem is kept on while cpu0 stop +bit08: gpu_ctx is kept on while cpu0 stop +bit09: xtal_hold is kept on while cpu0 stop +bit10: pll0_hold is kept on while cpu0 stop +bit11: pll1_hold is kept on while cpu0 stop +bit12: pll2_hold is kept on while cpu0 stop +bit13: pll3 is kept on while cpu0 stop +bit14: pll4 is kept on while cpu0 stop + 0 + 15 + read-write + + + + + SET + Retention Control + 0x4 + 32 + 0x00000000 + 0x00007FFF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +0: no effect +1: keep + 0 + 15 + read-write + + + + + CLEAR + Retention Control + 0x8 + 32 + 0x00000000 + 0x00007FFF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +0: no effect +1: no keep + 0 + 15 + read-write + + + + + TOGGLE + Retention Control + 0xc + 32 + 0x00000000 + 0x00007FFF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +0: no effect +1: toggle the result that whether the resource is kept on while CPU0 stop before + 0 + 15 + read-write + + + + + + 3 + 0x10 + vis,cpu0,gpu + POWER[%s] + no description available + 0x1000 + + status + Power Setting + 0x0 + 32 + 0x80000000 + 0xC0001100 + + + FLAG + flag represents power cycle happened from last clear of this bit +0: power domain did not edurance power cycle since last clear of this bit +1: power domain enduranced power cycle since last clear of this bit + 31 + 1 + read-write + + + FLAG_WAKE + flag represents wakeup power cycle happened from last clear of this bit +0: power domain did not edurance wakeup power cycle since last clear of this bit +1: power domain enduranced wakeup power cycle since last clear of this bit + 30 + 1 + read-write + + + LF_DISABLE + low fanout power switch disable +0: low fanout power switches are turned on +1: low fanout power switches are truned off + 12 + 1 + read-only + + + LF_ACK + low fanout power switch feedback +0: low fanout power switches are turned on +1: low fanout power switches are truned off + 8 + 1 + read-only + + + + + lf_wait + Power Setting + 0x4 + 32 + 0x000000FF + 0x000FFFFF + + + WAIT + wait time for low fan out power switch turn on, default value is 255 +0: 0 clock cycle +1: 1 clock cycles +. . . +clock cycles count on 24MHz + 0 + 20 + read-write + + + + + off_wait + Power Setting + 0xc + 32 + 0x0000000F + 0x000FFFFF + + + WAIT + wait time for power switch turn off, default value is 15 +0: 0 clock cycle +1: 1 clock cycles +. . . +clock cycles count on 24MHz + 0 + 20 + read-write + + + + + + 5 + 0x10 + soc,con,vis,cpu0,gpu + RESET[%s] + no description available + 0x1400 + + control + Reset Setting + 0x0 + 32 + 0x80000000 + 0xC0000011 + + + FLAG + flag represents reset happened from last clear of this bit +0: domain did not edurance reset cycle since last clear of this bit +1: domain enduranced reset cycle since last clear of this bit + 31 + 1 + read-write + + + FLAG_WAKE + flag represents wakeup reset happened from last clear of this bit +0: domain did not edurance wakeup reset cycle since last clear of this bit +1: domain enduranced wakeup reset cycle since last clear of this bit + 30 + 1 + read-write + + + HOLD + perform reset and hold in reset, until ths bit cleared by software +0: reset is released for function +1: reset is assert and hold + 4 + 1 + read-write + + + RESET + perform reset and release imediately +0: reset is released +1 reset is asserted and will release automatically + 0 + 1 + read-write + + + + + config + Reset Setting + 0x4 + 32 + 0x00402003 + 0x00FFFFFF + + + PRE_WAIT + wait cycle numbers before assert reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 16 + 8 + read-write + + + RSTCLK_NUM + reset clock number(must be even number) +0: 0 cycle +1: 0 cycles +2: 2 cycles +3: 2 cycles +. . . +Note, clock cycle is base on 24M + 8 + 8 + read-write + + + POST_WAIT + time guard band for reset release +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 8 + read-write + + + + + counter + Reset Setting + 0xc + 32 + 0x00000000 + 0x000FFFFF + + + COUNTER + self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 20 + read-write + + + + + + 69 + 0x4 + clk_top_cpu0,clk_top_mct0,clk_top_gpu0,clk_top_axif,clk_top_axis,clk_top_axic,clk_top_axiv,clk_top_axid,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,clk_top_can4,clk_top_can5,clk_top_can6,clk_top_can7,clk_top_lin0,clk_top_lin1,clk_top_lin2,clk_top_lin3,clk_top_lin4,clk_top_lin5,clk_top_lin6,clk_top_lin7,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_urt0,clk_top_urt1,clk_top_urt2,clk_top_urt3,clk_top_urt4,clk_top_urt5,clk_top_urt6,clk_top_urt7,clk_top_tmr0,clk_top_tmr1,clk_top_tmr2,clk_top_tmr3,clk_top_tmr4,clk_top_tmr5,clk_top_tmr6,clk_top_tmr7,clk_top_xpi0,clk_top_xram,clk_top_ana0,clk_top_ana1,clk_top_aud0,clk_top_aud1,clk_top_aud2,clk_top_aud3,clk_top_eth0,clk_top_ptp0,clk_top_sdc0,clk_top_sdc1,clk_top_ntm0,clk_top_ref0,clk_top_ref1,clk_top_cam0,clk_top_cam1,clk_top_lcd0,clk_top_lcd1,clk_top_csi0,clk_top_csi1 + CLOCK[%s] + no description available + 0x1800 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + 2 + 0x4 + clk_top_adc0,clk_top_adc1 + ADCCLK[%s] + no description available + 0x1c00 + 32 + 0x00000000 + 0xD0000100 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux +0: ana clock N +1: axi clock + 8 + 1 + read-write + + + + + 4 + 0x4 + clk_top_i2s0,clk_top_i2s1,clk_top_i2s2,clk_top_i2s3 + I2SCLK[%s] + no description available + 0x1c08 + 32 + 0x00000000 + 0xD0000100 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux +0: aud clock N +1: aud clock 0 + 8 + 1 + read-write + + + + + global00 + Clock senario + 0x2000 + 32 + 0x00000000 + 0x000000FF + + + MUX + global clock override request +bit0: override to preset0 +bit1: override to preset1 +bit2: override to preset2 +bit3: override to preset3 +bit4: override to preset4 +bit5: override to preset5 +bit6: override to preset6 +bit7: override to preset7 + 0 + 8 + read-write + + + + + 4 + 0x20 + slice0,slice1,slice2,slice3 + MONITOR[%s] + no description available + 0x2400 + + control + Clock measure and monitor control + 0x0 + 32 + 0x00000000 + 0x89FFD7FF + + + VALID + result is ready for read +0: not ready +1: result is ready + 31 + 1 + read-write + + + DIV_BUSY + divider is applying new setting + 27 + 1 + read-only + + + OUTEN + enable clock output + 24 + 1 + read-write + + + DIV + output divider + 16 + 8 + read-write + + + HIGH + clock frequency higher than upper limit + 15 + 1 + read-write + + + LOW + clock frequency lower than lower limit + 14 + 1 + read-write + + + START + start measurement + 12 + 1 + read-write + + + MODE + work mode, +0: register value will be compared to measurement +1: upper and lower value will be recordered in register + 10 + 1 + read-write + + + ACCURACY + measurement accuracy, +0: resolution is 1kHz +1: resolution is 1Hz + 9 + 1 + read-write + + + REFERENCE + reference clock selection, +0: 32k +1: 24M + 8 + 1 + read-write + + + SELECTION + clock measurement selection + 0 + 8 + read-write + + + + + current + Clock measure result + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + self updating measure result + 0 + 32 + read-only + + + + + low_limit + Clock lower limit + 0x8 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + FREQUENCY + lower frequency + 0 + 32 + read-write + + + + + high_limit + Clock upper limit + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + upper frequency + 0 + 32 + read-write + + + + + + 1 + 0x400 + cpu0 + CPU[%s] + no description available + 0x2800 + + LP + CPU0 LP control + 0x0 + 32 + 0x00001000 + 0xFF013703 + + + WAKE_CNT + CPU0 wake up counter, counter satuated at 255, write 0x00 to clear + 24 + 8 + read-write + + + HALT + halt request for CPU0, +0: CPU0 will start to execute after reset or receive wakeup request +1: CPU0 will not start after reset, or wakeup after WFI + 16 + 1 + read-write + + + WAKE + CPU0 is waking up +0: CPU0 wake up not asserted +1: CPU0 wake up asserted + 13 + 1 + read-only + + + EXEC + CPU0 is executing +0: CPU0 is not executing +1: CPU0 is executing + 12 + 1 + read-only + + + WAKE_FLAG + CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit +0: CPU0 wakeup not happened +1: CPU0 wake up happened + 10 + 1 + read-write + + + SLEEP_FLAG + CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit +0: CPU0 sleep not happened +1: CPU0 sleep happened + 9 + 1 + read-write + + + RESET_FLAG + CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit +0: CPU0 reset not happened +1: CPU0 reset happened + 8 + 1 + read-write + + + MODE + Low power mode, system behavior after WFI +00: CPU clock stop after WFI +01: System enter low power mode after WFI +10: Keep running after WFI +11: reserved + 0 + 2 + read-write + + + + + LOCK + CPU0 Lock GPR + 0x4 + 32 + 0x00000000 + 0x0000FFFE + + + GPR + Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset + 2 + 14 + read-write + + + LOCK + Lock bit for CPU_LOCK + 1 + 1 + read-write + + + + + 14 + 0x4 + GPR0,GPR1,GPR2,GPR3,GPR4,GPR5,GPR6,GPR7,GPR8,GPR9,GPR10,GPR11,GPR12,GPR13 + GPR[%s] + no description available + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + 4 + 0x4 + STATUS0,STATUS1,STATUS2,STATUS3 + WAKEUP_STATUS[%s] + no description available + 0x40 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + 4 + 0x4 + ENABLE0,ENABLE1,ENABLE2,ENABLE3 + WAKEUP_ENABLE[%s] + no description available + 0x80 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + + + + IOC + IOC + IOC + 0xf4040000 + + 0x0 + 0xf80 + registers + + + + 496 + 0x8 + pa00,pa01,pa02,pa03,pa04,pa05,pa06,pa07,pa08,pa09,pa10,pa11,pa12,pa13,pa14,pa15,pa16,pa17,pa18,pa19,pa20,pa21,pa22,pa23,pa24,pa25,pa26,pa27,pa28,pa29,pa30,pa31,pb00,pb01,pb02,pb03,pb04,pb05,pb06,pb07,pb08,pb09,pb10,pb11,pb12,pb13,pb14,pb15,pb16,pb17,pb18,pb19,pb20,pb21,pb22,pb23,pb24,pb25,pb26,pb27,pb28,pb29,pb30,pb31,pc00,pc01,pc02,pc03,pc04,pc05,pc06,pc07,pc08,pc09,pc10,pc11,pc12,pc13,pc14,pc15,pc16,pc17,pc18,pc19,pc20,pc21,pc22,pc23,pc24,pc25,pc26,pc27,pc28,pc29,pc30,pc31,pd00,pd01,pd02,pd03,pd04,pd05,pd06,pd07,pd08,pd09,pd10,pd11,pd12,pd13,pd14,pd15,pd16,pd17,pd18,pd19,pd20,pd21,pd22,pd23,pd24,pd25,pd26,pd27,pd28,pd29,pd30,pd31,pe00,pe01,pe02,pe03,pe04,pe05,pe06,pe07,pe08,pe09,pe10,pe11,pe12,pe13,pe14,pe15,pe16,pe17,pe18,pe19,pe20,pe21,pe22,pe23,pe24,pe25,pe26,pe27,pe28,pe29,pe30,pe31,pf00,pf01,pf02,pf03,pf04,pf05,pf06,pf07,pf08,pf09,pf10,pf11,pf12,pf13,pf14,pf15,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,rsv256,rsv257,rsv258,rsv259,rsv260,rsv261,rsv262,rsv263,rsv264,rsv265,rsv266,rsv267,rsv268,rsv269,rsv270,rsv271,rsv272,rsv273,rsv274,rsv275,rsv276,rsv277,rsv278,rsv279,rsv280,rsv281,rsv282,rsv283,rsv284,rsv285,rsv286,rsv287,rsv288,rsv289,rsv290,rsv291,rsv292,rsv293,rsv294,rsv295,rsv296,rsv297,rsv298,rsv299,rsv300,rsv301,rsv302,rsv303,rsv304,rsv305,rsv306,rsv307,rsv308,rsv309,rsv310,rsv311,rsv312,rsv313,rsv314,rsv315,rsv316,rsv317,rsv318,rsv319,rsv320,rsv321,rsv322,rsv323,rsv324,rsv325,rsv326,rsv327,rsv328,rsv329,rsv330,rsv331,rsv332,rsv333,rsv334,rsv335,rsv336,rsv337,rsv338,rsv339,rsv340,rsv341,rsv342,rsv343,rsv344,rsv345,rsv346,rsv347,rsv348,rsv349,rsv350,rsv351,rsv352,rsv353,rsv354,rsv355,rsv356,rsv357,rsv358,rsv359,rsv360,rsv361,rsv362,rsv363,rsv364,rsv365,rsv366,rsv367,rsv368,rsv369,rsv370,rsv371,rsv372,rsv373,rsv374,rsv375,rsv376,rsv377,rsv378,rsv379,rsv380,rsv381,rsv382,rsv383,rsv384,rsv385,rsv386,rsv387,rsv388,rsv389,rsv390,rsv391,rsv392,rsv393,rsv394,rsv395,rsv396,rsv397,rsv398,rsv399,rsv400,rsv401,rsv402,rsv403,rsv404,rsv405,rsv406,rsv407,rsv408,rsv409,rsv410,rsv411,rsv412,rsv413,rsv414,rsv415,px00,px01,px02,px03,px04,px05,px06,px07,px08,px09,px10,px11,px12,px13,px14,px15,rsv432,rsv433,rsv434,rsv435,rsv436,rsv437,rsv438,rsv439,rsv440,rsv441,rsv442,rsv443,rsv444,rsv445,rsv446,rsv447,py00,py01,py02,py03,py04,py05,py06,py07,py08,py09,py10,py11,py12,py13,py14,py15,rsv464,rsv465,rsv466,rsv467,rsv468,rsv469,rsv470,rsv471,rsv472,rsv473,rsv474,rsv475,rsv476,rsv477,rsv478,rsv479,pz00,pz01,pz02,pz03,pz04,pz05,pz06,pz07,pz08,pz09,pz10,pz11,pz12,pz13,pz14,pz15 + PAD[%s] + no description available + 0x0 + + FUNC_CTL + ALT SELECT + 0x0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +... +31:ALT31 + 0 + 5 + read-write + + + + + PAD_CTL + PAD SETTINGS + 0x4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + + + + PIOC + PIOC + IOC + 0xf4118000 + + + BIOC + BIOC + IOC + 0xf4210000 + + + PLLCTLV2 + PLLCTLV2 + PLLCTLV2 + 0xf40c0000 + + 0x0 + 0x300 + registers + + + + XTAL + OSC configuration + 0x0 + 32 + 0x0001FFFF + 0xB00FFFFF + + + BUSY + Busy flag +0: Oscillator is working or shutdown +1: Oscillator is changing status + 31 + 1 + read-only + + + RESPONSE + Crystal oscillator status +0: Oscillator is not stable +1: Oscillator is stable for use + 29 + 1 + read-only + + + ENABLE + Crystal oscillator enable status +0: Oscillator is off +1: Oscillator is on + 28 + 1 + read-only + + + RAMP_TIME + Rampup time of XTAL oscillator in cycles of RC24M clock +0: 0 cycle +1: 1 cycle +2: 2 cycle +1048575: 1048575 cycles + 0 + 20 + read-write + + + + + 5 + 0x80 + pll0,pll1,pll2,pll3,pll4 + PLL[%s] + no description available + 0x80 + + MFI + PLL0 multiple register + 0x0 + 32 + 0x00000010 + 0xB000007F + + + BUSY + Busy flag +0: PLL is stable or shutdown +1: PLL is changing status + 31 + 1 + read-only + + + RESPONSE + PLL status +0: PLL is not stable +1: PLL is stable for use + 29 + 1 + read-only + + + ENABLE + PLL enable status +0: PLL is off +1: PLL is on + 28 + 1 + read-only + + + MFI + loop back divider of PLL, support from 13 to 42, f=fref*(mfi + mfn/mfd) +0-15: invalid +16: divide by 16 +17: divide by17 +. . . +42: divide by 42 +43~:invalid + 0 + 7 + read-write + + + + + MFN + PLL0 fraction numerator register + 0x4 + 32 + 0x09896800 + 0x3FFFFFFF + + + MFN + Numeratorof fractional part,f=fref*(mfi + mfn/mfd). This field supports changing while running. + 0 + 30 + read-write + + + + + MFD + PLL0 fraction demoninator register + 0x8 + 32 + 0x0E4E1C00 + 0x3FFFFFFF + + + MFD + Demoninator of fraction part,f=fref*(mfi + mfn/mfd). This field should not be changed during PLL enabled. If changed, change will take efftect when PLL re-enabled. + 0 + 30 + read-write + + + + + SS_STEP + PLL0 spread spectrum step register + 0xc + 32 + 0x00000000 + 0x3FFFFFFF + + + STEP + Step of spread spectrum modulator. +This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. + 0 + 30 + read-write + + + + + SS_STOP + PLL0 spread spectrum stop register + 0x10 + 32 + 0x00000000 + 0x3FFFFFFF + + + STOP + Stop point of spread spectrum modulator +This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. + 0 + 30 + read-write + + + + + CONFIG + PLL0 confguration register + 0x14 + 32 + 0x00000000 + 0x00000101 + + + SPREAD + Enable spread spectrum function. This field supports changing during PLL running. + 8 + 1 + read-write + + + REFSEL + Select reference clock, This filed support changing while running, but application must take frequency error and jitter into consideration. And if MFN changed before reference switch, application need make sure time is enough for MFN updating. +0: XTAL24M +1: IRC24M + 0 + 1 + read-write + + + + + LOCKTIME + PLL0 lock time register + 0x18 + 32 + 0x000009C4 + 0x0000FFFF + + + LOCKTIME + Lock time of PLL in 24M clock cycles, typical value is 2500. If MFI changed during PLL startup, PLL lock time may be longer than this setting. + 0 + 16 + read-write + + + + + STEPTIME + PLL0 step time register + 0x1c + 32 + 0x000009C4 + 0x0000FFFF + + + STEPTIME + Step time for MFI on-the-fly change in 24M clock cycles, typical value is 2500. + 0 + 16 + read-write + + + + + ADVANCED + PLL0 advance configuration register + 0x20 + 32 + 0x00000000 + 0x11000000 + + + SLOW + Use slow lock flow, PLL lock expendite is disabled. This mode might be stabler. And software need config LOCKTIME field accordingly. +0: fast lock enabled, lock time is 100us +1: fast lock disabled, lock time is 400us + 28 + 1 + read-write + + + DITHER + Enable dither function + 24 + 1 + read-write + + + + + 3 + 0x4 + DIV0,DIV1,DIV2 + DIV[%s] + no description available + 0x40 + 32 + 0x00000000 + 0xB000003F + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Divider response status +0: Divider is not stable +1: Divider is stable for use + 29 + 1 + read-only + + + ENABLE + Divider enable status +0: Divider is off +1: Divider is on + 28 + 1 + read-only + + + DIV + Divider factor, divider factor is DIV/5 + 1 +0: divide by 1 +1: divide by 1.2 +2: divide by 1.4 +. . . +63: divide by 13.6 + 0 + 6 + read-write + + + + + + + + PPOR + PPOR + PPOR + 0xf4100000 + + 0x0 + 0x20 + registers + + + + RESET_FLAG + flag indicate reset source + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FLAG + reset reason of last hard reset, write 1 to clear each bit +0: brownout +1: temperature(not available) +4: debug reset +5: jtag soft reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2(not available) +19: watch dog 3(not available) +24: pmic watch dog +30: jtag ieee reset +31: software + 0 + 32 + write-only + + + + + RESET_STATUS + reset source status + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + current status of reset sources +0: brownout +1: temperature(not available) +4: debug reset +5: jtag soft reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2(not available) +19: watch dog 3(not available) +24: pmic watch dog +30: jtag ieee reset +31: software + 0 + 32 + read-only + + + + + RESET_HOLD + reset hold attribute + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + HOLD + hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status +0: brownout +1: temperature(not available) +4: debug reset +5: jtag soft reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2(not available) +19: watch dog 3(not available) +24: pmic watch dog +30: jtag ieee reset +31: software + 0 + 32 + read-write + + + + + RESET_ENABLE + reset source enable + 0xc + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + ENABLE + enable of reset sources +0: brownout +1: temperature(not available) +4: debug reset +5: jtag soft reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2(not available) +19: watch dog 3(not available) +24: pmic watch dog +30: jtag ieee reset +31: software + 0 + 32 + read-write + + + + + SOFTWARE_RESET + Software reset counter + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset + 0 + 32 + read-write + + + + + + + PCFG + PCFG + PMU + 0xf4104000 + + 0x0 + 0xac + registers + + + + BANDGAP + BANGGAP control + 0x0 + 32 + 0x00101010 + 0x831F1F1F + + + VBG_TRIMMED + Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: bandgap is not trimmed +1: bandgap is trimmed + 31 + 1 + read-write + + + LOWPOWER_MODE + Banggap work in low power mode, banggap function limited +0: banggap works in normal mode +1: banggap works in low power mode + 25 + 1 + read-write + + + POWER_SAVE + Banggap work in power save mode, banggap function normally +0: banggap works in high performance mode +1: banggap works in power saving mode + 24 + 1 + read-write + + + VBG_1P0_TRIM + Banggap 1.0V output trim value + 16 + 5 + read-write + + + VBG_P65_TRIM + Banggap 1.0V output trim value + 8 + 5 + read-write + + + VBG_P50_TRIM + Banggap 1.0V output trim value + 0 + 5 + read-write + + + + + LDO1P1 + 1V LDO config + 0x4 + 32 + 0x0000044C + 0x00000FFF + + + VOLT + LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. +700: 700mV +720: 720mV +. . . +1320:1320mV + 0 + 12 + read-write + + + + + LDO2P5 + 2.5V LDO config + 0x8 + 32 + 0x000009C4 + 0x10010FFF + + + READY + Ready flag, will set 1ms after enabled or voltage change +0: LDO is not ready for use +1: LDO is ready + 28 + 1 + read-only + + + ENABLE + LDO enable +0: turn off LDO +1: turn on LDO + 16 + 1 + read-write + + + VOLT + LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. +2125: 2125mV +2150: 2150mV +. . . +2900:2900mV + 0 + 12 + read-write + + + + + DCDC_MODE + DCDC mode select + 0x10 + 32 + 0x0003047E + 0x10070FFF + + + READY + Ready flag +0: DCDC is applying new change +1: DCDC is ready + 28 + 1 + read-only + + + MODE + DCDC work mode +XX0: turn off +001: basic mode +011: generic mode +101: automatic mode +111: expert mode + 16 + 3 + read-write + + + VOLT + DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. +600: 600mV +625: 625mV +. . . +1375:1375mV + 0 + 12 + read-write + + + + + DCDC_LPMODE + DCDC low power mode + 0x14 + 32 + 0x00000384 + 0x00000FFF + + + STBY_VOLT + DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. +600: 600mV +625: 625mV +. . . +1375:1375mV + 0 + 12 + read-write + + + + + DCDC_PROT + DCDC protection + 0x18 + 32 + 0x00000000 + 0x11818191 + + + ILIMIT_LP + over current setting for low power mode +0:250mA +1:200mA + 28 + 1 + read-write + + + OVERLOAD_LP + over current in low power mode +0: current is below setting +1: overcurrent happened in low power mode + 24 + 1 + read-only + + + DISABLE_POWER_LOSS + disable power loss protection +0: power loss protection enabled, DCDC shuts down when power loss +1: power loss protection disabled, DCDC try working after power voltage drop + 23 + 1 + read-write + + + POWER_LOSS_FLAG + power loss +0: input power is good +1: input power is too low + 16 + 1 + read-only + + + DISABLE_OVERVOLTAGE + output over voltage protection +0: protection enabled, DCDC will shut down is output voltage is unexpected high +1: protection disabled, DCDC continue to adjust output voltage + 15 + 1 + read-write + + + OVERVOLT_FLAG + output over voltage flag +0: output is normal +1: output is unexpected high + 8 + 1 + read-only + + + DISABLE_SHORT + disable output short circuit protection +0: short circuits protection enabled, DCDC shut down if short circuit on output detected +1: short circuit protection disabled + 7 + 1 + read-write + + + SHORT_CURRENT + short circuit current setting +0: 2.0A, +1: 1.3A + 4 + 1 + read-write + + + SHORT_FLAG + short circuit flag +0: current is within limit +1: short circuits detected + 0 + 1 + read-only + + + + + DCDC_CURRENT + DCDC current estimation + 0x1c + 32 + 0x00000000 + 0x0000811F + + + ESTI_EN + enable current measure + 15 + 1 + read-write + + + VALID + Current level valid +0: data is invalid +1: data is valid + 8 + 1 + read-only + + + LEVEL + DCDC current level, current level is num * 50mA + 0 + 5 + read-only + + + + + DCDC_ADVMODE + DCDC advance setting + 0x20 + 32 + 0x05120067 + 0x073F006F + + + EN_RCSCALE + Enable RC scale + 24 + 3 + read-write + + + DC_C + Loop C number + 20 + 2 + read-write + + + DC_R + Loop R number + 16 + 4 + read-write + + + EN_FF_DET + enable feed forward detect +0: feed forward detect is disabled +1: feed forward detect is enabled + 6 + 1 + read-write + + + EN_FF_LOOP + enable feed forward loop +0: feed forward loop is disabled +1: feed forward loop is enabled + 5 + 1 + read-write + + + EN_DCM_EXIT + avoid over voltage +0: stay in DCM mode when voltage excess +1: change to CCM mode when voltage excess + 3 + 1 + read-write + + + EN_SKIP + enable skip on narrow pulse +0: do not skip narrow pulse +1: skip narrow pulse + 2 + 1 + read-write + + + EN_IDLE + enable skip when voltage is higher than threshold +0: do not skip +1: skip if voltage is excess + 1 + 1 + read-write + + + EN_DCM + DCM mode +0: CCM mode +1: DCM mode + 0 + 1 + read-write + + + + + DCDC_ADVPARAM + DCDC advance parameter + 0x24 + 32 + 0x00006E1C + 0x00007F7F + + + MIN_DUT + minimum duty cycle + 8 + 7 + read-write + + + MAX_DUT + maximum duty cycle + 0 + 7 + read-write + + + + + DCDC_MISC + DCDC misc parameter + 0x28 + 32 + 0x00070100 + 0x13170317 + + + EN_HYST + hysteres enable + 28 + 1 + read-write + + + HYST_SIGN + hysteres sign + 25 + 1 + read-write + + + HYST_THRS + hysteres threshold + 24 + 1 + read-write + + + RC_SCALE + Loop RC scale threshold + 20 + 1 + read-write + + + DC_FF + Loop feed forward number + 16 + 3 + read-write + + + OL_THRE + overload for threshold for lod power mode + 8 + 2 + read-write + + + OL_HYST + current hysteres range +0: 12.5mV +1: 25mV + 4 + 1 + read-write + + + DELAY + enable delay +0: delay disabled, +1: delay enabled + 2 + 1 + read-write + + + CLK_SEL + clock selection +0: select DCDC internal oscillator +1: select RC24M oscillator + 1 + 1 + read-write + + + EN_STEP + enable stepping in voltage change +0: stepping disabled, +1: steping enabled + 0 + 1 + read-write + + + + + DCDC_DEBUG + DCDC Debug + 0x2c + 32 + 0x00005DBF + 0x000FFFFF + + + UPDATE_TIME + DCDC voltage change time in 24M clock cycles, default value is 1mS + 0 + 20 + read-write + + + + + DCDC_START_TIME + DCDC ramp time + 0x30 + 32 + 0x0001193F + 0x000FFFFF + + + START_TIME + Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS + 0 + 20 + read-write + + + + + DCDC_RESUME_TIME + DCDC resume time + 0x34 + 32 + 0x00008C9F + 0x000FFFFF + + + RESUME_TIME + Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS + 0 + 20 + read-write + + + + + POWER_TRAP + power trap + 0x40 + 32 + 0x00000000 + 0x80010001 + + + TRIGGERED + Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. +0: low power trap is not triggered +1: low power trap triggered + 31 + 1 + read-write + + + RETENTION + DCDC enter standby mode, which will reduce voltage for memory content retention +0: Shutdown DCDC +1: reduce DCDC voltage + 16 + 1 + read-write + + + TRAP + Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered +0: trap not enabled, pmic side low power function disabled +1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. + 0 + 1 + read-write + + + + + WAKE_CAUSE + Wake up source + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAUSE + wake up cause, each bit represents one wake up source, write 1 to clear the register bit +0: wake up source is not active during last wakeup +1: wake up source is active furing last wakeup +bit 0: pmic_enable +bit 5: VAD interrupt +bit 6: VAD wake interrupt +bit 7: UART interrupt +bit 8: TMR interrupt +bit 9: WDG interrupt +bit10: GPIO in PMIC interrupt +bit16: Security violation in BATT +bit17: GPIO in BATT interrupt +bit19: RTC alarm interrupt + 0 + 32 + read-write + + + + + WAKE_MASK + Wake up mask + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + MASK + mask for wake up sources, each bit represents one wakeup source +0: allow source to wake up system +1: disallow source to wakeup system +bit 0: pmic_enable +bit 5: VAD interrupt +bit 6: VAD wake interrupt +bit 7: UART interrupt +bit 8: TMR interrupt +bit 9: WDG interrupt +bit10: GPIO in PMIC interrupt +bit16: Security violation in BATT +bit17: GPIO in BATT interrupt +bit19: RTC alarm interrupt + 0 + 32 + read-write + + + + + SCG_CTRL + Clock gate control in PMIC + 0x4c + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + SCG + control whether clock being gated during PMIC low power flow, 2 bits for each peripheral +00,01: reserved +10: clock is always off +11: clock is always on +bit6-7:gpio +bit8-9:ioc +bit10-11: timer +bit12-13:wdog +bit14-15:uart +bit16-17:VAD +bit18-19:SRAM + 0 + 32 + read-write + + + + + RC24M + RC 24M config + 0x60 + 32 + 0x00000310 + 0x8000071F + + + RC_TRIMMED + RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: RC is not trimmed +1: RC is trimmed + 31 + 1 + read-write + + + TRIM_C + Coarse trim for RC24M, bigger value means faster + 8 + 3 + read-write + + + TRIM_F + Fine trim for RC24M, bigger value means faster + 0 + 5 + read-write + + + + + RC24M_TRACK + RC 24M track mode + 0x64 + 32 + 0x00000000 + 0x00010011 + + + SEL24M + Select track reference +0: select 32K as reference +1: select 24M XTAL as reference + 16 + 1 + read-write + + + RETURN + Retrun default value when XTAL loss +0: remain last tracking value +1: switch to default value + 4 + 1 + read-write + + + TRACK + track mode +0: RC24M free running +1: track RC24M to external XTAL + 0 + 1 + read-write + + + + + TRACK_TARGET + RC 24M track target + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRE_DIV + Divider for reference source + 16 + 16 + read-write + + + TARGET + Target frequency multiplier of divided source + 0 + 16 + read-write + + + + + STATUS + RC 24M track status + 0x6c + 32 + 0x00000000 + 0x0011871F + + + SEL32K + track is using XTAL32K +0: track is not using XTAL32K +1: track is using XTAL32K + 20 + 1 + read-only + + + SEL24M + track is using XTAL24M +0: track is not using XTAL24M +1: track is using XTAL24M + 16 + 1 + read-only + + + EN_TRIM + default value takes effect +0: default value is invalid +1: default value is valid + 15 + 1 + read-only + + + TRIM_C + default coarse trim value + 8 + 3 + read-only + + + TRIM_F + default fine trim value + 0 + 5 + read-only + + + + + DCDCM_MODE + DCDCM mode select + 0x80 + 32 + 0x00030546 + 0x10070FFF + + + READY + Ready flag +0: DCDCM is applying new change +1: DCDCM is ready + 28 + 1 + read-only + + + MODE + DCDCM work mode +XX0: turn off +001: basic mode +011: generic mode +101: automatic mode +111: expert mode + 16 + 3 + read-write + + + VOLT + DCDCM voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. +600: 600mV +625: 625mV +. . . +1375:1375mV + 0 + 12 + read-write + + + + + DCDCM_LPMODE + DCDCM low power mode + 0x84 + 32 + 0x00000546 + 0x00000FFF + + + STBY_VOLT + DCDCM voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. +600: 600mV +625: 625mV +. . . +1375:1375mV + 0 + 12 + read-write + + + + + DCDCM_PROT + DCDCM protection + 0x88 + 32 + 0x00000010 + 0x11818191 + + + ILIMIT_LP + over current setting for low power mode +0:250mA +1:200mA + 28 + 1 + read-write + + + OVERLOAD_LP + over current in low power mode +0: current is below setting +1: overcurrent happened in low power mode + 24 + 1 + read-only + + + DISABLE_POWER_LOSS + disable power loss protection +0: power loss protection enabled, DCDCM shuts down when power loss +1: power loss protection disabled, DCDCM try working after power voltage drop + 23 + 1 + read-write + + + POWER_LOSS_FLAG + power loss +0: input power is good +1: input power is too low + 16 + 1 + read-only + + + DISABLE_OVERVOLTAGE + output over voltage protection +0: protection enabled, DCDCM will shut down is output voltage is unexpected high +1: protection disabled, DCDCM continue to adjust output voltage + 15 + 1 + read-write + + + OVERVOLT_FLAG + output over voltage flag +0: output is normal +1: output is unexpected high + 8 + 1 + read-only + + + DISABLE_SHORT + disable output short circuit protection +0: short circuits protection enabled, DCDCM shut down if short circuit on output detected +1: short circuit protection disabled + 7 + 1 + read-write + + + SHORT_CURRENT + short circuit current setting +0: 2.0A +1: 1.3A + 4 + 1 + read-write + + + SHORT_FLAG + short circuit flag +0: current is within limit +1: short circuits detected + 0 + 1 + read-only + + + + + DCDCM_CURRENT + DCDCM current estimation + 0x8c + 32 + 0x00000000 + 0x0000811F + + + ESTI_EN + enable current measure + 15 + 1 + read-write + + + VALID + Current level valid +0: data is invalid +1: data is valid + 8 + 1 + read-only + + + LEVEL + DCDCM current level, current level is num * 50mA + 0 + 5 + read-only + + + + + DCDCM_ADVMODE + DCDCM advance setting + 0x90 + 32 + 0x05120067 + 0x073F007F + + + EN_RCSCALE + Enable RC scale + 24 + 3 + read-write + + + DC_C + Loop C number + 20 + 2 + read-write + + + DC_R + Loop R number + 16 + 4 + read-write + + + EN_FF_DET + enable feed forward detect +0: feed forward detect is disabled +1: feed forward detect is enabled + 6 + 1 + read-write + + + EN_FF_LOOP + enable feed forward loop +0: feed forward loop is disabled +1: feed forward loop is enabled + 5 + 1 + read-write + + + EN_AUTOLP + enable auto enter low power mode +0: do not enter low power mode +1: enter low power mode if current is detected low + 4 + 1 + read-write + + + EN_DCM_EXIT + avoid over voltage +0: stay in DCM mode when voltage excess +1: change to CCM mode when voltage excess + 3 + 1 + read-write + + + EN_SKIP + enable skip on narrow pulse +0: do not skip narrow pulse +1: skip narrow pulse + 2 + 1 + read-write + + + EN_IDLE + enable skip when voltage is higher than threshold +0: do not skip +1: skip if voltage is excess + 1 + 1 + read-write + + + EN_DCM + DCM mode +0: CCM mode +1: DCM mode + 0 + 1 + read-write + + + + + DCDCM_ADVPARAM + DCDCM advance parameter + 0x94 + 32 + 0x0000701C + 0x00007F7F + + + MIN_DUT + minimum duty cycle + 8 + 7 + read-write + + + MAX_DUT + maximum duty cycle + 0 + 7 + read-write + + + + + DCDCM_MISC + DCDCM misc parameter + 0x98 + 32 + 0x00070100 + 0x13170317 + + + EN_HYST + hysteres enable + 28 + 1 + read-write + + + HYST_SIGN + hysteres sign + 25 + 1 + read-write + + + HYST_THRS + hysteres threshold + 24 + 1 + read-write + + + RC_SCALE + Loop RC scale threshold + 20 + 1 + read-write + + + DC_FF + Loop feed forward number + 16 + 3 + read-write + + + OL_THRE + overload for threshold for lod power mode + 8 + 2 + read-write + + + OL_HYST + current hysteres range +0: 12.5mV +1: 25mV + 4 + 1 + read-write + + + DELAY + enable delay +0: delay disabled, +1: delay enabled + 2 + 1 + read-write + + + CLK_SEL + clock selection +0: select DCDCM internal oscillator +1: select RC24M oscillator + 1 + 1 + read-write + + + EN_STEP + enable stepping in voltage change +0: stepping disabled, +1: steping enabled + 0 + 1 + read-write + + + + + DCDCM_DEBUG + DCDCM Debug + 0x9c + 32 + 0x00005DBF + 0x000FFFFF + + + UPDATE_TIME + DCDCM voltage change time in 24M clock cycles, default value is 1mS + 0 + 20 + read-write + + + + + DCDCM_START_TIME + DCDCM ramp time + 0xa0 + 32 + 0x0001193F + 0x000FFFFF + + + START_TIME + Start delay for DCDCM to turn on, in 24M clock cycles, default value is 3mS + 0 + 20 + read-write + + + + + DCDCM_RESUME_TIME + DCDCM resume time + 0xa4 + 32 + 0x000000F0 + 0x000FFFFF + + + RESUME_TIME + Resume delay for DCDCM to recover from low power mode, in 24M clock cycles, default value is 10uS + 0 + 20 + read-write + + + + + DCDCM_POWER_CONFIG + DCDCM power config + 0xa8 + 32 + 0x00000000 + 0x00010000 + + + RETENTION + DCDCM enter standby mode, which will reduce voltage for memory content retention +0: Shutdown DCDCM +1: reduce DCDC voltage + 16 + 1 + read-write + + + + + + + PGPR0 + PGPR0 + PGPR + 0xf4110000 + + 0x0 + 0x40 + registers + + + + PMIC_GPR00 + Generic control + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR01 + Generic control + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR02 + Generic control + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR03 + Generic control + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR04 + Generic control + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR05 + Generic control + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR06 + Generic control + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR07 + Generic control + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR08 + Generic control + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR09 + Generic control + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR10 + Generic control + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR11 + Generic control + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR12 + Generic control + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR13 + Generic control + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR14 + Generic control + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR15 + Generic control + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + + + PGPR1 + PGPR1 + PGPR + 0xf4114000 + + + VAD + VAD + VAD + 0xf412c000 + + 0x0 + 0xa4 + registers + + + + CTRL + Control Register + 0x0 + 32 + 0x00000000 + 0x0FF7FBFF + + + CAPT_DLY + Capture cycle delay>=0, should be less than PDM_CLK_HFDIV + 24 + 4 + read-write + + + PDM_CLK_HFDIV + The clock divider will work at least 4. +0: div-by-2, +1: div-by-4 +. . . +n: div-by-2*(n+1) + 20 + 4 + read-write + + + VAD_IE + VAD event interrupt enable + 18 + 1 + read-write + + + OFIFO_AV_IE + OFIFO data available interrupt enable + 17 + 1 + read-write + + + MEMBUF_EMPTY_IE + Buf empty interrupt enable + 16 + 1 + read-write + + + OFIFO_OVFL_ERR_IE + OFIFO overflow error interrupt enable + 15 + 1 + read-write + + + IIR_OVLD_ERR_IE + IIR overload error interrupt enable + 14 + 1 + read-write + + + IIR_OVFL_ERR_IE + IIR overflow error interrupt enable + 13 + 1 + read-write + + + CIC_OVLD_ERR_IE + CIC overload Interrupt Enable + 12 + 1 + read-write + + + CIC_SAT_ERR_IE + CIC saturation Interrupt Enable + 11 + 1 + read-write + + + MEMBUF_DISABLE + asserted to disable membuf + 9 + 1 + read-write + + + FIFO_THRSH + OFIFO threshold to generate ofifo_av (when fillings >= threshold) (fifo size: max 16 items, 16*32bits) + 5 + 4 + read-write + + + PDM_CLK_DIV_BYPASS + asserted to bypass the pdm clock divider + 4 + 1 + read-write + + + PDM_CLK_OE + pdm_clk_output_en + 3 + 1 + read-write + + + CH_POL + Asserted to select PDM_CLK high level captured, otherwise to select PDM_CLK low level captured. + 1 + 2 + read-write + + + CHNUM + the number of channels to be stored in buffer. Asserted to enable 2 channels. + 0 + 1 + read-write + + + + + FILTCTRL + Filter Control Register + 0x4 + 32 + 0x00000000 + 0x000007FF + + + DECRATIO + the decimation ratio of iir after CIC -1 +2: means dec-by-3 + 8 + 3 + read-write + + + IIR_SLOT_EN + IIR slot enable + 0 + 8 + read-write + + + + + DEC_CTRL0 + Decision Control Register 0 + 0x8 + 32 + 0x00000000 + 0xFFFF03FF + + + NOISE_TOL + the value of amplitude for noise determination when calculationg ZCR + 16 + 16 + read-write + + + BLK_CFG + asserted to have 3 sub-blocks, otherwise to have 2 sub-blocks + 9 + 1 + read-write + + + SUBBLK_LEN + length of sub-block + 0 + 9 + read-write + + + + + DEC_CTRL1 + Decision Control Register 1 + 0xc + 32 + 0x00000000 + 0x003FFFFF + + + ZCR_HIGH + ZCR high limit + 11 + 11 + read-write + + + ZCR_LOW + ZCR low limit + 0 + 11 + read-write + + + + + DEC_CTRL2 + Decision Control Register 2 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + AMP_HIGH + amplitude high limit + 16 + 16 + read-write + + + AMP_LOW + amplitude low limit + 0 + 16 + read-write + + + + + ST + Status + 0x18 + 32 + 0x00000000 + 0x000000FF + + + VAD + VAD event found + 7 + 1 + write-only + + + OFIFO_AV + OFIFO data available + 6 + 1 + read-only + + + MEMBUF_EMPTY + Buf empty + 5 + 1 + write-only + + + OFIFO_OVFL + OFIFO overflow + 4 + 1 + write-only + + + IIR_OVLD + IIR overloading + 3 + 1 + write-only + + + IIR_OVFL + IIR oberflow + 2 + 1 + write-only + + + CIC_OVLD_ERR + CIC overload + 1 + 1 + write-only + + + CIC_SAT_ERR + CIC saturation + 0 + 1 + write-only + + + + + OFIFO + Out FIFO + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + D + The PCM data. +When there is only one channel, the samples are from Ch0, and the 2 samples in the 32-bits are: bit [31:16]: the samples earlier in time ([T-1]). Bit [15:0]: the samples later in time ([T]). +When there is two channels, the samples in the 32-bits are: bit [31:16]: the samples belong to Ch 1 (when ch_pol[1:0]==2, the data is captured at the positive part of the pdm clk). bit [15:0]: the samples belong to Ch 0 (when ch_pol[1:0]==2, the data is captured at the negtive part of the pdm clk). + 0 + 32 + read-write + + + + + RUN + Run Command Register + 0x20 + 32 + 0x00000000 + 0x00000003 + + + SFTRST + software reset. Self-clear + 1 + 1 + read-write + + + VAD_EN + module enable + 0 + 1 + read-write + + + + + OFIFO_CTRL + Out FIFO Control Register + 0x24 + 32 + 0x00000000 + 0x00000001 + + + EN + Asserted to enable OFIFO + 0 + 1 + read-write + + + + + CIC_CFG + CIC Configuration Register + 0x28 + 32 + 0x00000000 + 0x0000FC00 + + + POST_SCALE + the shift value after CIC results. + 10 + 6 + read-write + + + + + 1 + 0x4 + STE_ACT + COEF[%s] + no description available + 0xa0 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + The current detected short time energy + 0 + 32 + read-only + + + + + + + MIPI_DSI_PHY0 + MIPI_DSI_PHY0 + MIPI_DSI_PHY + 0xf4140000 + + 0x0 + 0x94 + registers + + + + clane_para0 + timer counter about clock lane parameter + 0x0 + 32 + 0x00000050 + 0x0000FFFF + + + T_RST2ENLPTX_C + the soft reset of clk_cfg domain + 0 + 16 + read-write + + + + + clane_para1 + timer counter about clock lane parameter + 0x4 + 32 + 0x00000100 + 0xFFFFFFFF + + + T_INITTIME_C + the number of byteclk cycles that clklane drive LP-11 during initialization period + 0 + 32 + read-write + + + + + clane_para2 + timer counter about clock lane parameter + 0x8 + 32 + 0x00808080 + 0x00FFFFFF + + + T_CLKPREPARE_C + the number of byteclk cycles that clock lane clkp/n lines are at the hs prepare state lp-00 during a hs clock transmission + 16 + 8 + read-write + + + T_CLKZERO_C + the number of byteclk cycles that clock lane clkp/n lines are at the hs-zero state hs-0 during a hs clock transmission + 8 + 8 + read-write + + + T_CLKPRE_C + the number of byteclk cycles that hs clock shall be driven prior to data lane beginning the transition from lp to hs mode + 0 + 8 + read-write + + + + + clane_para3 + timer counter about clock lane parameter + 0xc + 32 + 0x00808080 + 0x00FFFFFF + + + T_CLKPOST_C + the number of byteclk cycles that the clock lane should keep sending the hs-clock after the last associated data lane has transitioned to LP mode. + 16 + 8 + read-write + + + T_CLKTRIAL_C + the number of byteclk cycles that the clock lane clkp/n lines are at state hs-tail sate hs-0 during a hs clock transmission + 8 + 8 + read-write + + + T_HSEXIT_C + the number of byteclk cycles that the clock lane clkp/n lines are at hs-exit state after a hs clock transmission + 0 + 8 + read-write + + + + + dlane0_para0 + timer counter about datalane0 parameter + 0x10 + 32 + 0x00000050 + 0x0000FFFF + + + T_RST2ENLPTX_D0 + the number of byteclk cycles that datalane0 wait to enable lptx_en after reset release + 0 + 16 + read-write + + + + + dlane0_para1 + timer counter about datalane0 parameter + 0x14 + 32 + 0x00000014 + 0xFFFFFFFF + + + T_INITTIME_D0 + the number of byteclk cycles that datalane0 drive lp-11 during initiaalization period + 0 + 32 + read-write + + + + + dlane0_para2 + timer counter about datalane0 parameter + 0x18 + 32 + 0x80808080 + 0xFFFFFFFF + + + T_HSPREPARE_D0 + the number of byteclk cycles that the datalane0 stay at hs prepare state lp-00 during a hs transmission + 24 + 8 + read-write + + + T_HSZERO_D0 + the number of byteclk cycles that the datalane0 stay at hs-zero sate during a hs transmission + 16 + 8 + read-write + + + T_HSTRAIL_D0 + the number of byteclk cycles that the datalane0 stay at hs-trail state during a hs clock transmission + 8 + 8 + read-write + + + T_HSEXIT_D0 + the number of byteclk cycles that the datalane0 stay at state hs-exit sate after a hs clock transmission + 0 + 8 + read-write + + + + + dlane0_para3 + timer counter about datalane0 parameter + 0x1c + 32 + 0x00000100 + 0xFFFFFFFF + + + T_WAKEUP_D0 + the number of byteclk cycles from exiting ultra low power sate to enabling the low-power driver + 0 + 32 + read-write + + + + + dlane0_para4 + timer counter about datalane0 parameter + 0x20 + 32 + 0x00808080 + 0x00FFFFFF + + + T_TAGO_D0 + the number of byteclk cycles that the tx drives the bridge state during a turnaroud procedure + 16 + 8 + read-write + + + T_TASURE_D0 + the number of byteclk cycles that the rx waits after a bridge state has been detected during a turnaround procedure + 8 + 8 + read-write + + + T_TAGET_D0 + the number of byteclk cycles that the new transmitter drivers the bridge state after accepting control during bta + 0 + 8 + read-write + + + + + dlane1_para0 + timer counter about datalane1 parameter + 0x24 + 32 + 0x00000050 + 0x0000FFFF + + + T_RST2ENLPTX_D1 + the number of byteclk cycles that datalane1 wait to enable lptx_en after reset release + 0 + 16 + read-write + + + + + dlane1_para1 + timer counter about datalane1 parameter + 0x28 + 32 + 0x00000014 + 0xFFFFFFFF + + + T_INITTIME_D1 + the number of byteclk cycles that datalane1 drive lp-11 during initiaalization period + 0 + 32 + read-write + + + + + dlane1_para2 + timer counter about datalane1 parameter + 0x2c + 32 + 0x80808080 + 0xFFFFFFFF + + + T_HSPREPARE_D1 + the number of byteclk cycles that the datalane1 stay at hs prepare state lp-00 during a hs transmission + 24 + 8 + read-write + + + T_HSZERO_D1 + the number of byteclk cycles that the datalane1 stay at hs-zero sate during a hs transmission + 16 + 8 + read-write + + + T_HSTRAIL_D1 + the number of byteclk cycles that the datalane1 stay at hs-trail state during a hs clock transmission + 8 + 8 + read-write + + + T_HSEXIT_D1 + the number of byteclk cycles that the datalane1 stay at state hs-exit sate after a hs clock transmission + 0 + 8 + read-write + + + + + dlane1_para3 + timer counter about datalane1 parameter + 0x30 + 32 + 0x00000100 + 0xFFFFFFFF + + + T_WAKEUP_D1 + the number of byteclk cycles from exiting ultra low power sate to enabling the low-power driver + 0 + 32 + read-write + + + + + dlane2_para0 + timer counter about datalane2 parameter + 0x34 + 32 + 0x00000050 + 0x0000FFFF + + + T_RST2ENLPTX_D2 + the number of byteclk cycles that datalane2 wait to enable lptx_en after reset release + 0 + 16 + read-write + + + + + dlane2_para1 + timer counter about datalane2 parameter + 0x38 + 32 + 0x00000014 + 0xFFFFFFFF + + + T_INITTIME_D2 + the number of byteclk cycles that datalane2 drive lp-11 during initiaalization period + 0 + 32 + read-write + + + + + dlane2_para2 + timer counter about datalane2 parameter + 0x3c + 32 + 0x80808080 + 0xFFFFFFFF + + + T_HSPREPARE_D2 + the number of byteclk cycles that the datalane2 stay at hs prepare state lp-00 during a hs transmission + 24 + 8 + read-write + + + T_HSZERO_D2 + the number of byteclk cycles that the datalane2 stay at hs-zero sate during a hs transmission + 16 + 8 + read-write + + + T_HSTRAIL_D2 + the number of byteclk cycles that the datalane2 stay at hs-trail state during a hs clock transmission + 8 + 8 + read-write + + + T_HSEXIT_D2 + the number of byteclk cycles that the datalane2 stay at state hs-exit sate after a hs clock transmission + 0 + 8 + read-write + + + + + dlane2_para3 + timer counter about datalane2 parameter + 0x40 + 32 + 0x00000100 + 0xFFFFFFFF + + + T_WAKEUP_D2 + the number of byteclk cycles from exiting ultra low power sate to enabling the low-power driver + 0 + 32 + read-write + + + + + dlane3_para0 + timer counter about datalane3 parameter + 0x44 + 32 + 0x00000050 + 0x0000FFFF + + + T_RST2ENLPTX_D3 + the number of byteclk cycles that datalane3 wait to enable lptx_en after reset release + 0 + 16 + read-write + + + + + dlane3_para1 + timer counter about datalane3 parameter + 0x48 + 32 + 0x00000014 + 0xFFFFFFFF + + + T_INITTIME_D3 + the number of byteclk cycles that datalane3 drive lp-11 during initiaalization period + 0 + 32 + read-write + + + + + dlane3_para2 + timer counter about datalane3 parameter + 0x4c + 32 + 0x80808080 + 0xFFFFFFFF + + + T_HSPREPARE_D3 + the number of byteclk cycles that the datalane3 stay at hs prepare state lp-00 during a hs transmission + 24 + 8 + read-write + + + T_HSZERO_D3 + the number of byteclk cycles that the datalane3 stay at hs-zero sate during a hs transmission + 16 + 8 + read-write + + + T_HSTRAIL_D3 + the number of byteclk cycles that the datalane3 stay at hs-trail state during a hs clock transmission + 8 + 8 + read-write + + + T_HSEXIT_D3 + the number of byteclk cycles that the datalane3 stay at state hs-exit sate after a hs clock transmission + 0 + 8 + read-write + + + + + dlane3_para3 + timer counter about datalane3 parameter + 0x50 + 32 + 0x00000100 + 0xFFFFFFFF + + + T_WAKEUP_D3 + the number of byteclk cycles from exiting ultra low power sate to enabling the low-power driver + 0 + 32 + read-write + + + + + common_para0 + timing parameter for all lanes + 0x54 + 32 + 0x00000014 + 0x000000FF + + + T_LPX + the number of byteclk cycles of transmitted length of any low-power state period + 0 + 8 + read-write + + + + + ctrl_para0 + dphy control parameter + 0x58 + 32 + 0x000000E0 + 0x000000FF + + + VBG_RDY + the indicator signal of reference generator is ready + 7 + 1 + read-only + + + EN_ULPRX_D0 + ulp-rx enable for lane0 + 6 + 1 + read-write + + + EN_LPRX_D0 + lp-rx enable for lane0 + 5 + 1 + read-write + + + EN_LPCD_D0 + lp-cd enable for lane0 + 4 + 1 + read-write + + + PWON_SEL + select the cource of PMA power on control signals + 3 + 1 + read-write + + + PWON_PLL + power on pll high active + 2 + 1 + read-write + + + PWON_DSI + power on all dsi lane + 1 + 1 + read-write + + + SU_IDDQ_EN + power down all modules inside su includes ivref, r-calibration and pll, high effective + 0 + 1 + read-write + + + + + pll_ctrl_para0 + dphy pll control parameter + 0x5c + 32 + 0x01029AB6 + 0x0FFFFFFF + + + PLL_LOCK + pll lock indication + 27 + 1 + read-only + + + RATE + data reate control signal + 24 + 3 + read-write + + + REFCLK_DIV + input reference clock divider ratio control + 19 + 5 + read-write + + + PLL_DIV + pll loop divider ratio control + 4 + 15 + read-write + + + DSI_PIXELCLK_DIV + pixell clock divided from pll output + 0 + 4 + read-write + + + + + rcal_ctrl + dphy calibration control parameter + 0x64 + 32 + 0x00002E00 + 0x00003FFF + + + RCAL_EN + enable hs-tx output impedance trimming + 13 + 1 + read-write + + + RCAL_TRIM + default value of hs-tx output resistance configure + 9 + 4 + read-write + + + RCAL_CTRL + resistor calibration control, reserved for test + 1 + 8 + read-write + + + RCAL_DONE + hs-tx output impedance trimming done indicator signal + 0 + 1 + read-only + + + + + trim_para + dphy trimming parameter + 0x68 + 32 + 0x00003322 + 0x00003FFF + + + HSTX_AMP_TRIM + hs-tx output vod trimming for lane-0~4 + 11 + 3 + read-write + + + LPTX_SR_TRIM + lp-tx output slew-rate trimming for lane0~4 + 8 + 3 + read-write + + + LPRX_VREF_TRIM + lp-rx input threshold voltage trimming for lane0 + 4 + 4 + read-write + + + LPCD_VREF_TRIM + lp-cd input threshold voltage trimming for lane0 + 0 + 4 + read-write + + + + + test_para0 + dphy test control parameter + 0x6c + 32 + 0x00000000 + 0x007FFFFF + + + ERROR_NUM + the byte num of mismatch data of lane in bist mode + 17 + 6 + read-only + + + BIST_N_DONE + indicate prbs7 bist test is done + 12 + 5 + read-only + + + BIST_N_OK + indicate prbs7 bist test is ok + 7 + 5 + read-only + + + ATEST_EN + analog test signal enable + 6 + 1 + read-write + + + ATEST_SEL + analog test signal select + 4 + 2 + read-write + + + FSET_EN + enable fast transmission between lp-tx and hs-tx + 3 + 1 + read-write + + + FT_SEL + pt/ft test mode select + 0 + 3 + read-write + + + + + test_para1 + dphy bist test control parameter + 0x70 + 32 + 0x009C40C0 + 0xFFFFFFFF + + + CHECK_NUM + the byte num of prbs bist check num + 10 + 22 + read-write + + + ERR_THRESHOLD + the threshold of prbs bit error + 6 + 4 + read-write + + + BIST_BIT_ERROR + enable insert error in bist test pattern + 5 + 1 + read-write + + + BIST_EN + bist enable + 3 + 2 + read-write + + + BIST_SEL + bist mode select + 2 + 1 + read-write + + + PRBS_SEL + prbs generator and checker pattern select signal + 0 + 2 + read-write + + + + + misc_para + dphy control parameter + 0x74 + 32 + 0x0000007F + 0x000007FF + + + DLL_SEL + the phase select of clk_rxesc + 7 + 4 + read-write + + + LANE_NUM + the number of active data lanes + 5 + 2 + read-write + + + PHYERR_MASK + mask the phy error + 0 + 5 + read-write + + + + + clane_para4 + dphy clock lane control parameter + 0x78 + 32 + 0x00000100 + 0xFFFFFFFF + + + T_WAKEUP_C + the number of byteclk cycles from exiting ultra low power state to enabling the low-power driver + 0 + 32 + read-write + + + + + interface_para + dphy clock lane control parameter + 0x7c + 32 + 0x00000301 + 0x0000FFFF + + + TXREADYESC_EXTEND_VLD + the extend length of txreadyesc + 8 + 8 + read-write + + + RXVALIDESC_EXTEND_VLD + the extend length of rxvalidesc + 0 + 8 + read-write + + + + + pcs_reserved_pin_para + reserved the pins for pcs + 0x80 + 32 + 0x00000000 + 0x0000001F + + + CLK_TXHS_SEL_INNER + select the clock source of clk_txhs in pcs + 4 + 1 + read-write + + + INV_CLK_TXHS + clk_txhs inverter signal + 3 + 1 + read-write + + + INV_CLK_TXESC + clk_txesc inverter signal + 2 + 1 + read-write + + + INV_PCLK + pclk inverter signal + 1 + 1 + read-write + + + INV_DSI_RCLK + pma clock dsi_rclk_i inverter signal + 0 + 1 + read-write + + + + + clane_data_para + parallel data about clock lane parameter + 0x8c + 32 + 0x000000AA + 0x000001FF + + + CLANE_DATA_SEL + select the data about clock lane + 8 + 1 + read-write + + + CLANE_DATA + the parallel data about clock lane + 0 + 8 + read-write + + + + + pma_lane_sel_para + pma about clock lane select parameter + 0x90 + 32 + 0x0000000D + 0x0000000F + + + PMA_DLANE4_SEL + select the channel 4 as the data lane + 3 + 1 + read-write + + + PMA_DLANE3_SEL + select the channel 3 as the data lane + 2 + 1 + read-write + + + PMA_DLANE2_SEL + select the channel 2 as the data lane + 1 + 1 + read-write + + + PMA_DLANE1_SEL + select the channel 1 as the data lane + 0 + 1 + read-write + + + + + + + MIPI_DSI_PHY1 + MIPI_DSI_PHY1 + MIPI_DSI_PHY + 0xf4144000 + + + MIPI_CSI_PHY0 + MIPI_CSI_PHY0 + MIPI_CSI_PHY + 0xf4148000 + + 0x0 + 0xd28 + registers + + + + soft_rst + soft reset control + 0x0 + 32 + 0x00000000 + 0x00000003 + + + HS_CLK_SOFT_RST + the soft reset of clk_hs domain + 1 + 1 + read-write + + + CFG_CLK_SOFT_RST + the soft reset of clk_cfg domain + 0 + 1 + read-write + + + + + phy_rcal + dphy resistor calibration + 0x4 + 32 + 0x0000E00F + 0x0003FFFF + + + RCAL_DONE + hs-rx terminal trimming done indicator signal + 17 + 1 + read-only + + + RCAL_OUT + hs-rx terminal trimming results + 13 + 4 + read-only + + + RCAL_CTL + rcal function control + 5 + 8 + read-write + + + RCAL_TRIM + default value of HS-RX terminal configure + 1 + 4 + read-write + + + RCAL_EN + enable hs-rx terminal trimming + 0 + 1 + read-write + + + + + ulp_rx_en + enable lprx and ulprx + 0x8 + 32 + 0x000000E3 + 0x000000E3 + + + CSI_1_ULPRX_EN + data lane1 ulp-rx receiver enable control + 7 + 1 + read-write + + + CSI_0_ULPRX_EN + data lane0 ulp-rx receiver enable control + 6 + 1 + read-write + + + CSI_CLK_ULPRX_EN + clock lane ulp-rx receiver enable control + 5 + 1 + read-write + + + CSI_1_LPRX_EN + data lane1 lp-rx receiver enable control + 1 + 1 + read-write + + + CSI_CLK_LPRX_EN + clock lane lp=rx receiver enable control + 0 + 1 + read-write + + + + + voffcal_out + hs-rx dc-offset auto-calibration results + 0xc + 32 + 0x00000000 + 0x3FFFF000 + + + CSI_CLK_VOFFCAL_DONE + clock lane hs-rx dc-offset auto-calibration done + 29 + 1 + read-only + + + CSI_CLK_VOFFCAL_OUT + clock lane hs-rx dc-offset auto-calibration results + 24 + 5 + read-only + + + CSI_0_VOFFCAL_DONE + data lane0 hs-rx dc-offset auto-calibration done + 23 + 1 + read-only + + + CSI_O_VOFFCAL_OUT + data lane0 hs-rx dc-offset auto-calibration result + 18 + 5 + read-only + + + CSI_1_VOFFCAL_DONE + data lane1 hs-rx dc-offset auto-calibration done + 17 + 1 + read-only + + + CSI_1_VOFFCAL_OUT + data lane1 hs-rx dc-offset auto-calibration result + 12 + 5 + read-only + + + + + csi_ctl01 + dphy hardcore control + 0x10 + 32 + 0x00000000 + 0x3F7F3F7F + + + CSI_CTL1_7 + clock lane hs-rx dc-offset auto-calibration enable + 29 + 1 + read-write + + + CSI_CTL1_6 + clock lane hs-rx dc-offset trimming control + 24 + 5 + read-write + + + CSI_CTL1_5 + ulprx_vref_trim + 21 + 2 + read-write + + + CSI_CTL1_4 + bypass hs_rx_voffcal_en + 20 + 1 + read-write + + + CSI_CTL1_3 + hs_rx_voffcal_trim_polar + 19 + 1 + read-write + + + CSI_CTL1_2 + ulprx_lpen + 18 + 1 + read-write + + + CSI_CTL1_1 + force data lane-n and clock lane lp/ulprx to be normal operation + 17 + 1 + read-write + + + CSI_CTL1_0 + force data lane-n and clock lane hs-rx to be normal operation + 16 + 1 + read-write + + + CSI_CTL0_7 + clock lane hs-rx dc-offset auto-calibration enable + 13 + 1 + read-write + + + CSI_CTL0_6 + clock lane hs-rx dc-offset trimming control + 8 + 5 + read-write + + + CSI_CTL0_5 + ulprx_vref_trim + 5 + 2 + read-write + + + CSI_CTL0_4 + bypass hs_rx_voffcal_en + 4 + 1 + read-write + + + CSI_CTL0_3 + hs_rx_voffcal_trim_polar + 3 + 1 + read-write + + + CSI_CTL0_2 + ulprx_lpen + 2 + 1 + read-write + + + CSI_CTL0_1 + force data lane-n and clock lane lp/ulprx to be normal operation + 1 + 1 + read-write + + + CSI_CTL0_0 + force data lane-n and clock lane hs-rx to be normal operation + 0 + 1 + read-write + + + + + csi_ctl23 + dphy hardcore control + 0x14 + 32 + 0x00000000 + 0x1F1F0000 + + + CSI_CTL3_3 + data lane-1 skew trimming enable + 28 + 1 + read-write + + + CSI_CTL3_2 + data lane-1 hs-rx skew adjust with binary code + 24 + 4 + read-write + + + CSI_CTL3_1 + data lane-0 skew trimming enable + 20 + 1 + read-write + + + CSI_CTL3_0 + data lane-0 hs-rx skew adjust with binary code + 16 + 4 + read-write + + + + + csi_vinit + ulp lp-rx input threshold voltage trimming for data lane + 0x1c + 32 + 0x00200000 + 0x00FF00FF + + + CSI_LPRX_VREF_TRIM + pt ft indicator in csi clk data lane + 20 + 4 + read-write + + + CSI_CLK_LPRX_VINT + pt ft indicator in csi clk lane + 16 + 4 + read-only + + + CSI_1_LPRX_VINIT + pt ft indicator in csi lane-1 + 4 + 4 + read-only + + + CSI_0_LPRX_VINIT + pt ft indicator in csi lane-0 + 0 + 4 + read-only + + + + + clane_para + clock lane parameter + 0x20 + 32 + 0x00000314 + 0x0000FFFF + + + T_CLK_TERMEN + time for the clock lane receiver to enable the HS line termination + 8 + 8 + read-write + + + T_CLK_SETTLE + the value of tclk-settle of clklane + 0 + 8 + read-write + + + + + t_hs_termen + t-termen of all datalane + 0x24 + 32 + 0x00000303 + 0x0000FFFF + + + T_D1_TERMEN + the value of ths-termen of datalane1 + 8 + 8 + read-write + + + T_D0_TERMEN + the value of ths-termen of datalane0 + 0 + 8 + read-write + + + + + t_hs_settle + t-settle of all data lanes + 0x28 + 32 + 0x00000A0A + 0x0000FFFF + + + T_D1_SETTLE + the value of ths-settle of data lane1 + 8 + 8 + read-write + + + T_D0_SETTLE + the value of ths-settle of data lane0 + 0 + 8 + read-write + + + + + t_clane_init + t-init of clock lane + 0x30 + 32 + 0x00007530 + 0x00FFFFFF + + + T_CLK_INIT + initialization time of lock lane + 0 + 24 + read-write + + + + + t_lane_init0 + t-init of data lane0 + 0x34 + 32 + 0x00007530 + 0x00FFFFFF + + + T_D0_INIT + initialization time of data lane + 0 + 24 + read-write + + + + + t_lane_init1 + t-init of data lane1 + 0x38 + 32 + 0x00007530 + 0x00FFFFFF + + + T_D1_INIT + initialization time of data lane + 0 + 24 + read-write + + + + + tlpx_ctrl + the time of tlpx_ctrl of all lane + 0x44 + 32 + 0x00000002 + 0x000001FF + + + EN_TLPX_CHECK + enable the tlpx width check + 8 + 1 + read-write + + + TLPX + the width of tlpx + 0 + 8 + read-write + + + + + ne_swap + lane swap and dp/dn swap select + 0x48 + 32 + 0x00000004 + 0x0000030F + + + DPDN_SWAP_LANE1 + datalane1 dpdn swap + 9 + 1 + read-write + + + DPDN_SWAP_LAN0 + datalane0 dpdn swap + 8 + 1 + read-write + + + LANE_SWAP_LAN1 + data lane1 swap + 2 + 2 + read-write + + + LANE_SWAP_LANE0 + data lane0 swap + 0 + 2 + read-write + + + + + misc_info + misc info of dphyrx_pcs control + 0x4c + 32 + 0x00000000 + 0x00000003 + + + ULPS_LP10_SEL + the lp10 select signal in ulps_exit state + 1 + 1 + read-write + + + LONG_SOTSYNC_EN + at least six zero is checked before sot swquence "00011101" + 0 + 1 + read-write + + + + + bist_test0 + bist test control + 0x70 + 32 + 0x00000000 + 0x000000CF + + + BIST_DONE_LAN1 + bist_done of lane1 + 7 + 1 + read-only + + + BIST_DONE_LAN0 + bist_done of lane0 + 6 + 1 + read-only + + + BIST_OK_LANE1 + bist_ok of lane1 + 3 + 1 + read-only + + + BIST_OK_LANE0 + bist_ok of lane0 + 2 + 1 + read-only + + + BIST_EN_SEL + the source of bist_en sel + 1 + 1 + read-write + + + BIST_EN_SOFT + enable prbs bist test + 0 + 1 + read-write + + + + + bist_test1 + bist test control + 0x74 + 32 + 0x00000100 + 0xFFFFFFFF + + + PRBS_CHECK_NUM + the byte num of prbs bist check num + 0 + 32 + read-write + + + + + bist_test2 + bist test control + 0x78 + 32 + 0x007F0005 + 0x00FFFFFF + + + PRBS_SEED + the seed of prbs7 + 16 + 8 + read-write + + + PRBS_ERR_THRESHOLD + the threshold of prbs bist error + 0 + 16 + read-write + + + + + bist_test3 + bist test control + 0x7c + 32 + 0x00000000 + 0xFFFFFFFF + + + PRBS_ERR_NUM_LAN1 + the byte num of mismatch data of data lane1 in bist mode + 16 + 16 + read-only + + + PRBS_ERR_NUM_LAN0 + the byte num of mismatch data of data lane0 in bist mode + 0 + 16 + read-only + + + + + burn_in_test0 + burn-in test control + 0xa0 + 32 + 0x00000000 + 0x0000004F + + + BURN_IN_OK_CLAN + burn_in_ok of clock lane + 6 + 1 + read-only + + + BURN_IN_OK_LAN1 + burn_in_ok of lane1 + 3 + 1 + read-only + + + BURN_IN_OK_LAN0 + burn_in_ok of lane0 + 2 + 1 + read-only + + + BURN_IN_EN_SEL + the source of prbs burn_in_en sel + 1 + 1 + read-write + + + BURN_IN_EN_SOFT + enable prbs burn_in test + 0 + 1 + read-write + + + + + burn_in_test1 + burn-in test control + 0xa4 + 32 + 0x00000000 + 0x000000FF + + + BURN_IN_SEED + the seed of prbs7 for brun-in test + 0 + 8 + read-write + + + + + burn_in_test2 + bist test control + 0xa8 + 32 + 0x00000000 + 0xFFFFFFFF + + + BURN_IN_ERR_NUM_LAN1 + the bit num of mismatch data on data lan1 in burn-in mode + 16 + 16 + read-only + + + BURN_IN_ERR_NUM_LAN0 + the bit num of mismatch data on data lan0 in burn-in mode + 0 + 16 + read-only + + + + + burn_in_test4 + bist test control + 0xb0 + 32 + 0x00000000 + 0x0000FFFF + + + BURN_IN_ERR_NUM_CLAN + the bit num of mismatch data on clock lane in burn-in mode + 0 + 16 + read-only + + + + + burn_in_test5 + burn-in test control + 0xb4 + 32 + 0x00000000 + 0xFFFFFFFF + + + BURN_IN_CHECK_NUM_LAN0 + the checked bit num of lane0 + 0 + 32 + read-only + + + + + burn_in_test6 + burn-in test control + 0xb8 + 32 + 0x00000000 + 0xFFFFFFFF + + + BURN_IN_CHECKED_NUM_LAN1 + the checked bit num of lane1 + 0 + 32 + read-only + + + + + burn_in_test9 + burn-in test control + 0xc4 + 32 + 0x00000000 + 0xFFFFFFFF + + + BURN_IN_CHECK_NUM_CLAN + the checked bit num of clock lane + 0 + 32 + read-only + + + + + debug_info + debug data control + 0xd0 + 32 + 0x00000000 + 0x003F0000 + + + DEBUG_MODE_SEL + the debug bus sel + 16 + 6 + read-write + + + + + debug_cfg_reg0 + the hardcore interface control in debug mode + 0xd4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DEBUG_CFG_REG0 + debug config register0 + 0 + 32 + read-write + + + + + debug_cfg_reg1 + the hardcore interface control in debug mode + 0xd8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DEBUG_CFG_REG1 + debug config register1 + 0 + 32 + read-write + + + + + debug_cfg_reg2 + the hardcore interface control in debug mode + 0xd12 + 32 + 0x00000000 + 0xFFFFFFFF + + + DEBUG_CFG_REG2 + debug config register2 + 0 + 32 + read-write + + + + + debug_cfg_reg3 + the hardcore interface control in debug mode + 0xd16 + 32 + 0x00000000 + 0xFFFFFFFF + + + DEBUG_CFG_REG3 + debug config register3 + 0 + 32 + read-write + + + + + debug_cfg_reg4 + the hardcore interface control in debug mode + 0xd20 + 32 + 0x00000000 + 0xFFFFFFFF + + + DEBUG_CFG_REG4 + debug config register4 + 0 + 32 + read-write + + + + + debug_cfg_reg5 + the hardcore interface control in debug mode + 0xd24 + 32 + 0x00000000 + 0xFFFFFFFF + + + DEBUG_CFG_REG5 + debug config register5 + 0 + 32 + read-write + + + + + + + MIPI_CSI_PHY1 + MIPI_CSI_PHY1 + MIPI_CSI_PHY + 0xf414c000 + + + DDRPHY + DDRPHY + DDRPHY + 0xf4150000 + + 0x0 + 0x400 + registers + + + + RIDR + Revision Identification Register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + UDRID + User-Defined Revision ID: General purpose revision identification set by the user. + 24 + 8 + read-only + + + PHYMJR + PHY Major Revision: Indicates major revision of the PHY such addition of the features that make the new version not compatible with previous versions. + 20 + 4 + read-only + + + PHYMDR + PHY Moderate Revision: Indicates moderate revision of the PHY such as addition of new features. Normally the new version is still compatible with previous versions. + 16 + 4 + read-only + + + PHYMNR + PHY Minor Revision: Indicates minor update of the PHY such as bug fixes. Normally no new features are included. + 12 + 4 + read-only + + + PUBMJR + PUB Major Revision: Indicates major revision of the PUB such addition of the features that make the new version not compatible with previous versions. + 8 + 4 + read-only + + + PUBMDR + PUB Moderate Revision: Indicates moderate revision of the PUB such as addition of new features. Normally the new version is still compatible with previous versions. + 4 + 4 + read-only + + + PUBMNR + PUB Minor Revision: Indicates minor update of the PUB such as bug fixes. Normally no new features are included. + 0 + 4 + read-only + + + + + PIR + PHY Initialization Register (PIR) + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + INITBYP + Initialization Bypass: Bypasses or stops, if set, all initialization routines currently running, including PHY initialization, DRAM initialization, and PHY training. +Initialization may be triggered manually using INIT and the other relevant bits of the PIR register. This bit is self-clearing. + 31 + 1 + read-write + + + ZCALBYP + Impedance Calibration Bypass: Bypasses or stops, if set, impedance calibration of all ZQ control blocks that automatically triggers after reset. Impedance calibration may be triggered manually using INIT and ZCAL bits of the PIR register. This bit is self-clearing. + 30 + 1 + read-write + + + DCALBYP + Digital Delay Line (DDL) Calibration Bypass: Bypasses or stops, if set, DDL calibration that automatically triggers after reset. DDL calibration may be triggered manually using INIT and DCAL bits of the PIR register. This bit is self- clearing. + 29 + 1 + read-write + + + LOCKBYP + PLL Lock Bypass: Bypasses or stops, if set, the waiting of PLLs to lock. PLL lock wait is automatically triggered after reset. PLL lock wait may be triggered manually using INIT and PLLINIT bits of the PIR register. This bit is self-clearing. + 28 + 1 + read-write + + + CLRSR + Clear Status Registers: Writing 1 to this bit clears (reset to 0) select status bits in register PGSR0. +This bit is primarily for debug purposes and is typically not needed during normal functional operation. It can be used when PGSR.IDONE=1, to manually clear a selection of the PGSR status bits, although starting a new initialization process (PIR[0].INIT = 1’b1) automatically clears the PGSR status bits associated with the initialization steps enabled. +The following list describes which bits within the PGSR0 register are cleared when CLRSR is set to 1’b1 and which bits are not cleared: +The following bits are not cleared by PIR[27] (CLRSR): +PGSR0[31] (APLOCK) +PGSR0[29:28] (PLDONE_CHN) +PGSR0[23] (WLAERR) +PGSR0[21] (WLERR) +PGSR0[4] (DIDONE) +PGSR0[2] (DCDONE) +PGSR0[1] (PLDONE) +PGSR0[0] (IDONE) +The following bits are always zero: +PGSR0[30] (reserved) +PGSR0[19:12] (reserved) +The following bits are cleared unconditionally by PIR[27] (CLRSR): +PGSR0[27] (WEERR) +PGSR0[26] (REERR) +PGSR0[25] (WDERR) +PGSR0[24] (RDERR) +- PGSR0[22] (QSGERR) +- PGSR0[20] (ZCERR) +- PGSR0[11] (WEDONE) +- PGSR0[10] (REDONE) +- PGSR0[9] (WDDONE) +- PGSR0[8] (RDDONE) +- PGSR0[7] (WLADONE) +- PGSR0[6] (QSGDONE) +- PGSR0[5] (WLDONE) +- PGSR0[3] (ZCDONE) + 27 + 1 + read-write + + + RDIMMINIT + RDIMM Initialization: Executes the RDIMM buffer chip initialization before executing DRAM initialization. The RDIMM buffer chip initialization is run after the DRAM is reset and CKE have been driven high by the DRAM initialization sequence. + 19 + 1 + read-write + + + CTLDINIT + Controller DRAM Initialization: Indicates, if set, that DRAM initialization will be performed by the controller. Otherwise if not set it indicates that DRAM initialization will be performed using the built-in initialization sequence or using software through the configuration port. + 18 + 1 + read-write + + + PLLBYP + PLL Bypass: A setting of 1 on this bit will put all PHY PLLs in bypass mode. + 17 + 1 + read-write + + + ICPC + Initialization Complete Pin Configuration: Specifies how the DFI initialization complete output pin (dfi_init_complete) should be used to indicate the status of initialization. Valid value are: +0 = Asserted after PHY initialization (DLL locking and impedance calibration) is complete. +1 = Asserted after PHY initialization is complete and the triggered the PUB initialization (DRAM initialization, data training, or initialization trigger with no selected initialization) is complete. + 16 + 1 + read-write + + + WREYE + Write Data Eye Training: Executes a PUB training routine to maximize the write data eye. + 15 + 1 + read-write + + + RDEYE + Read Data Eye Training: Executes a PUB training routine to maximize the read data eye. + 14 + 1 + read-write + + + WRDSKW + Write Data Bit Deskew: Executes a PUB training routine to deskew the DQ bits during write. + 13 + 1 + read-write + + + RDDSKW + Read Data Bit Deskew: Executes a PUB training routine to deskew the DQ bits during read. + 12 + 1 + read-write + + + WLADJ + Write Leveling Adjust (DDR3 Only): Executes a PUB training routine that re- adjusts the write latency used during write in case the write leveling routine changed the expected latency. +Note: Ensure that the DCU command cache is cleared prior to running WLADJ. + 11 + 1 + read-write + + + QSGATE + Read DQS Gate Training: Executes a PUB training routine to determine the optimum position of the read data DQS strobe for maximum system timing margins. + 10 + 1 + read-write + + + WL + Write Leveling (DDR3 Only): Executes a PUB write leveling routine. + 9 + 1 + read-write + + + DRAMINIT + DRAM Initialization: Executes the DRAM initialization sequence. + 8 + 1 + read-write + + + DRAMRST + DRAM Reset (DDR3 Only): Issues a reset to the DRAM (by driving the DRAM reset pin low) and wait 200us. This can be triggered in isolation or with the full DRAM initialization (DRAMINIT). For the later case, the reset is issued and 200us is waited before starting the full initialization sequence. + 7 + 1 + read-write + + + PHYRST + PHY Reset: Resets the AC and DATX8 modules by asserting the AC/DATX8 reset pin. + 6 + 1 + read-write + + + DCAL + Digital Delay Line (DDL) Calibration: Performs PHY delay line calibration. + 5 + 1 + read-write + + + PLLINIT + PLL Initialization: Executes the PLL initialization sequence which includes correct driving of PLL power-down, reset and gear shift pins, and then waiting for the PHY PLLs to lock. + 4 + 1 + read-write + + + ZCAL + Impedance Calibration: Performs PHY impedance calibration. When set the impedance calibration will be performed in parallel with PHY initialization (PLL initialization + DDL calibration + PHY reset). + 1 + 1 + read-write + + + INIT + Initialization Trigger: A write of '1' to this bit triggers the DDR system initialization, including PHY initialization, DRAM initialization, and PHY training. The exact initialization steps to be executed are specified in bits 1 to 15 of this register. A bit setting of 1 means the step will be executed as part of the initialization sequence, while a setting of ‘0’ means the step will be bypassed. The initialization trigger bit is self-clearing. + 0 + 1 + read-write + + + + + PGCR0 + PHY General Configuration Registers 0-1 (PGCR0- 1) + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CKEN + CK Enable: Controls whether the CK going to the SDRAM is enabled (toggling) or disabled (static value) and whether the CK is inverted. Two bits for each of the up to three CK pairs. Valid values for the two bits are: +00 = CK disabled (Driven to constant 0) 01 = CK toggling with inverted polarity +10 = CK toggling with normal polarity (This should be the default setting) 11 = CK disabled (Driven to constant 1) + 26 + 6 + read-write + + + PUBMODE + Enables, if set, the PUB to control the interface to the PHY and SDRAM. In this mode the DFI commands from the controller are ignored. The bit must be set to 0 after the system determines it is convenient to pass control of the DFI bus to the controller. When set to 0 the DFI interface has control of the PHY and SDRAM interface except when triggering pub operations such as BIST, DCU or data training. + 25 + 1 + read-write + + + DTOSEL + Digital Test Output Select: Selects the PHY digital test output that is driven onto PHY digital test output (phy_dto) pin: Valid values are: +00000 = DATX8 0 PLL digital test output 00001 = DATX8 1 PLL digital test output 00010 = DATX8 2 PLL digital test output 00011 = DATX8 3 PLL digital test output 00100 = DATX8 4 PLL digital test output 00101 = DATX8 5 PLL digital test output 00110 = DATX8 6 PLL digital test output 00111 = DATX8 7 PLL digital test output 01000 = DATX8 8 PLL digital test output 01001 = AC PLL digital test output 01010 – 01111 = Reserved +10000 = DATX8 0 delay line digital test output 10001 = DATX8 1 delay line digital test output 10010 = DATX8 2 delay line digital test output 10011 = DATX8 3 delay line digital test output 10100 = DATX8 4 delay line digital test output 10101 = DATX8 5 delay line digital test output 10110 = DATX8 6 delay line digital test output 10111 = DATX8 7 delay line digital test output 11000 = DATX8 8 delay line digital test output 11001 = AC delay line digital test output 11010 – 11111 = Reserved + 14 + 5 + read-write + + + OSCWDL + Oscillator Mode Write-Leveling Delay Line Select: Selects which of the two write leveling LCDLs is active. The delay select value of the inactive LCDL is set to zero while the delay select value of the active LCDL can be varied by the input write leveling delay select pin. Valid values are: +00 = No WL LCDL is active 01 = DDR WL LCDL is active 10 = SDR WL LCDL is active 11 = Both LCDLs are active + 12 + 2 + read-write + + + OSCDIV + Oscillator Mode Division: Specifies the factor by which the delay line oscillator mode output is divided down before it is output on the delay line digital test output pin dl_dto. Valid values are: +000 = Divide by 1 +001 = Divide by 256 +010 = Divide by 512 +011 = Divide by 1024 +100 = Divide by 2048 +101 = Divide by 4096 +110 = Divide by 8192 +111 = Divide by 65536 + 9 + 3 + read-write + + + OSCEN + Oscillator Enable: Enables, if set, the delay line oscillation. + 8 + 1 + read-write + + + DLTST + Delay Line Test Start: A write of '1' to this bit will trigger delay line oscillator mode period measurement. This bit is not self clearing and needs to be reset to '0' before the measurement can be re-triggered. + 7 + 1 + read-write + + + DLTMODE + Delay Line Test Mode: Selects, if set, the delay line oscillator test mode. Setting this bit also clears all delay line register values. For DL oscillator testing, first set this bit, then apply desired non-zero LCDL and BDL register programmings. + 6 + 1 + read-write + + + RDBVT + Read Data BDL VT Compensation: Enables, if set, the VT drift compensation of the read data bit delay lines. + 5 + 1 + read-write + + + WDBVT + Write Data BDL VT Compensation: Enables, if set, the VT drift compensation of the write data bit delay lines. + 4 + 1 + read-write + + + RGLVT + Read DQS Gating LCDL Delay VT Compensation: Enables, if set, the VT drift compensation of the read DQS gating LCDL. + 3 + 1 + read-write + + + RDLVT + Read DQS LCDL Delay VT Compensation: Enables, if set, the VT drift compensation of the read DQS LCDL. + 2 + 1 + read-write + + + WDLVT + Write DQ LCDL Delay VT Compensation: Enables, if set, the VT drift compensation of the write DQ LCDL. + 1 + 1 + read-write + + + WLLVT + Write Leveling LCDL Delay VT Compensation: Enables, if set, the VT drift compensation of the write leveling LCDL. + 0 + 1 + read-write + + + + + PGCR1 + PHY General Configuration Registers 0-1 (PGCR0- 1) + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + LBMODE + Loopback Mode: Indicates, if set, that the PHY/PUB is in loopback mode. + 31 + 1 + read-write + + + LBGDQS + Loopback DQS Gating: Selects the DQS gating mode that should be used when the PHY is in loopback mode, including BIST loopback mode. Valid values are: +00 = DQS gate is always on +01 = DQS gate training will be triggered on the PUB 10 = DQS gate is set manually using software +11 = Reserved + 29 + 2 + read-write + + + LBDQSS + Loopback DQS Shift: Selects how the read DQS is shifted during loopback to ensure that the read DQS is centered into the read data eye. Valid values are: +1b0 = PUB sets the read DQS LCDL to 0 (internally). DQS is already shifted 90 degrees by write path +1b1 = The read DQS shift is set manually through software + 28 + 1 + read-write + + + IOLB + I/O Loop-Back Select: Selects where inside the I/O the loop-back of signals happens. Valid values are: +0 = Loopback is after output buffer; output enable must be asserted 1 = Loopback is before output buffer; output enable is don’t care + 27 + 1 + read-write + + + INHVT + VT Calculation Inhibit: Inhibits calculation of the next VT compensated delay line values. A value of 1 will inhibit the VT calculation. This bit should be set to 1 during writes to the delay line registers. + 26 + 1 + read-write + + + DXHRST + DX PHY High-Speed Reset: a Write of '0' to this bit resets the DX macro without resetting the PUB RTL logic. This bit is not self-clearing and a '1' must be written to de-assert the reset. + 25 + 1 + read-write + + + ZCKSEL + Impedance Clock Divider Select: Selects the divide ratio for the clock used by the impedance control logic relative to the clock used by the memory controller and SDRAM. +Valid values are: +00 = Divide by 2 +01 = Divide by 8 +10 = Divide by 32 +11 = Divide by 64 +For more information, refer to “Impedance Calibration” on page 174. + 23 + 2 + read-write + + + DLDLMT + Delay Line VT Drift Limit: Specifies the minimum change in the delay line VT drift in one direction which should result in the assertion of the delay line VT drift status signal (vt_drift). The limit is specified in terms of delay select values. A value of 0 disables the assertion of delay line VT drift status signal. + 15 + 8 + read-write + + + FDEPTH + Filter Depth: Specifies the number of measurements over which all AC and DATX8 initial period measurements, that happen after reset or when calibration is manually triggered, are averaged. Valid values are: +00 = 2 +01 = 4 +10 = 8 +11 = 16 + 13 + 2 + read-write + + + LPFDEPTH + Low-Pass Filter Depth: Specifies the number of measurements over which MDL period measurements are filtered. This determines the time constant of the low pass filter. Valid values are: +00 = 2 +01 = 4 +10 = 8 +11 = 16 + 11 + 2 + read-write + + + LPFEN + Low-Pass Filter Enable: Enables, if set, the low pass filtering of MDL period measurements. + 10 + 1 + read-write + + + MDLEN + Master Delay Line Enable: Enables, if set, the AC master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or on when calibration is manually triggered. These additional measurements are accumulated and filtered as long as this bit remains high. + 9 + 1 + read-write + + + IODDRM + I/O DDR Mode (D3F I/O Only): Selects the DDR mode for the I/Os. These bits connect to bits [2:1] of the IOM pin of the SSTL I/O. For more information, refer to the SSTL I/O chapter in the DWC DDR PHY Databook. + 7 + 2 + read-write + + + WLSELT + Write Leveling Select Type: Selects the encoding type for the write leveling select signal depending on the desired setup/hold margins for the internal pipelines. Refer to the DDR PHY Databook for details of how the select type is used. Valid values are: +0 = Type 1: Setup margin of 90 degrees and hold margin of 90 degrees 1 = Type 2: Setup margin of 135 degrees and hold margin of 45 degrees + 6 + 1 + read-write + + + ACHRST + AC PHY High-Speed Reset: a Write of '0' to this bit resets the AC macro without resetting the PUB RTL logic. This bit is not self-clearing and a '1' must be written to de-assert the reset. + 5 + 1 + read-write + + + WSLOPT + Write System Latency Optimization: controls the insertion of a pipeline stage on the AC signals from the DFI interface to the PHY to cater for a negative write system latency (WSL) value (only -1 possible). +0x0 = A pipeline stage is inserted only if WL2 training results in a WSL of -1 for any rank +0x1 = Inserts a pipeline stage + 4 + 1 + read-write + + + WLSTEP + Write Leveling Step: Specifies the number of delay step-size increments during each step of write leveling. Valid values are: +0 = computed to be 1/2 of the associated lane's DXnGSR0.WLPRD value 1 = 1 step size + 2 + 1 + read-write + + + WLMODE + Write Leveling (Software) Mode: Indicates, if set, that the PUB is in software write leveling mode in which software executes single steps of DQS pulsing by writing '1' to PIR.WL. The write leveling DQ status from the DRAM is captured in DXnGSR0.WLDQ. + 1 + 1 + read-write + + + PDDISDX + Power Down Disabled Byte: Indicates, if set, that the PLL and I/Os of a disabled byte should be powered down. + 0 + 1 + read-write + + + + + PGSR0 + “PHY General Status Registers 0-1 (PGSR0-1)” on page 89 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + APLOCK + AC PLL Lock: Indicates, if set, that AC PLL has locked. This is a direct status of the AC PLL lock pin. + 31 + 1 + read-only + + + PLDONE_CHN + PLL Lock Done per Channel: Indicates PLL locking has completed for each underlying channel. Bit 28 represents channel 0 while bit 29 represents channel 1. + 28 + 2 + read-only + + + WEERR + Write Eye Training Error: Indicates, if set, that there is an error in write eye training. + 27 + 1 + read-only + + + REERR + Read Data Eye Training Error: Indicates, if set, that there is an error in read eye training. + 26 + 1 + read-only + + + WDERR + Write Data Bit Deskew Error: Indicates, if set, that there is an error in write bit deskew. + 25 + 1 + read-only + + + RDERR + Read Data Bit Deskew Error: Indicates, if set, that there is an error in read bit deskew. + 24 + 1 + read-only + + + WLAERR + Write Data Leveling Adjustment Error: Indicates, if set, that there is an error in write leveling adjustment. + 23 + 1 + read-only + + + QSGERR + Read DQS Gate Training Error: Indicates, if set, that there is an error in DQS gate training. + 22 + 1 + read-only + + + WLERR + Write Leveling Error: Indicates, if set, that there is an error in write leveling. + 21 + 1 + read-only + + + ZCERR + Impedance Calibration Error: Indicates, if set, that there is an error in impedance calibration. + 20 + 1 + read-only + + + WEDONE + Write Data Eye Training Done: Indicates, if set, that write eye training has completed. + 11 + 1 + read-only + + + REDONE + Read Data Eye Training Done: Indicates, if set, that read eye training has completed. + 10 + 1 + read-only + + + WDDONE + Write Data Bit Deskew Done: Indicates, if set, that write bit deskew has completed. + 9 + 1 + read-only + + + RDDONE + Read Data Bit Deskew Done: Indicates, if set, that read bit deskew has completed. + 8 + 1 + read-only + + + WLADONE + Write Leveling Adjustment Done: Indicates, if set, that write leveling adjustment has completed. + 7 + 1 + read-only + + + QSGDONE + Read DQS Gate Training Done: Indicates, if set, that DQS gate training has completed. + 6 + 1 + read-only + + + WLDONE + Write Leveling Done: Indicates, if set, that write leveling has completed. + 5 + 1 + read-only + + + DIDONE + DRAM Initialization Done: Indicates, if set, that DRAM initialization has completed. + 4 + 1 + read-only + + + ZCDONE + Impedance Calibration Done: Indicates, if set, that impedance calibration has completed. + 3 + 1 + read-only + + + DCDONE + Digital Delay Line (DDL) Calibration Done: Indicates, if set, that DDL calibration has completed. + 2 + 1 + read-only + + + PLDONE + PLL Lock Done: Indicates, if set, that PLL locking has completed. + 1 + 1 + read-only + + + IDONE + Initialization Done: Indicates, if set, that the DDR system initialization has completed. This bit is set after all the selected initialization routines in PIR register have completed. + 0 + 1 + read-only + + + + + PGSR1 + “PHY General Status Registers 0-1 (PGSR0-1)” on page 89 + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + PARERR + RDIMM Parity Error: Indicates, if set, that there was a parity error (i.e. err_out_n was sampled low) during one of the transactions to the RDIMM buffer chip. This bit remains asserted until cleared by the PIR.CLRSR. + 31 + 1 + read-only + + + VTSTOP + VT Stop: Indicates, if set, that the VT calculation logic has stopped computing the next values for the VT compensated delay line values. After assertion of the PGCR.INHVT, the VTSTOP bit should be read to ensure all VT compensation logic has stopped computations before writing to the delay line registers. + 30 + 1 + read-only + + + DLTCODE + Delay Line Test Code: Returns the code measured by the PHY control block that corresponds to the period of the AC delay line digital test output. + 1 + 24 + read-only + + + DLTDONE + Delay Line Test Done: Indicates, if set, that the PHY control block has finished doing period measurement of the AC delay line digital test output. + 0 + 1 + read-only + + + + + PLLCR + “PLL Control Register (PLLCR)” on page 91 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + BYP + PLL Bypass: Bypasses the PLL, if set, to 1. + 31 + 1 + read-write + + + PLLRST + PLL Rest: Resets the PLLs by driving the PLL reset pin. This bit is not self-clearing and a ‘0’ must be written to de-assert the reset. + 30 + 1 + read-write + + + PLLPD + PLL Power Down: Puts the PLLs in power down mode by driving the PLL power down pin. This bit is not self-clearing and a ‘0’ must be written to de-assert the power-down. + 29 + 1 + read-write + + + FRQSEL + PLL Frequency Select: Selects the operating range of the PLL. Valid values for PHYs that go up to 2133 Mbps are: +00 = PLL reference clock (ctl_clk/REF_CLK) ranges from 335MHz to 533MHz 01 = PLL reference clock (ctl_clk/REF_CLK) ranges from 225MHz to 385MHz 10 = Reserved +11 = PLL reference clock (ctl_clk/REF_CLK) ranges from 166MHz to 275MHz +Valid values for PHYs that don’t go up to 2133 Mbps are: +00 = PLL reference clock (ctl_clk/REF_CLK) ranges from 250MHz to 400MHz 01 = PLL reference clock (ctl_clk/REF_CLK) ranges from 166MHz to 300MHz 10 = Reserved +11 = Reserved + 18 + 2 + read-write + + + QPMODE + PLL Quadrature Phase Mode: Enables, if set, the quadrature phase clock outputs. This mode is not used in this version of the PHY. + 17 + 1 + read-write + + + CPPC + Charge Pump Proportional Current Control + 13 + 4 + read-write + + + CPIC + Charge Pump Integrating Current Control + 11 + 2 + read-write + + + GSHIFT + Gear Shift: Enables, if set, rapid locking mode. + 10 + 1 + read-write + + + ATOEN + Analog Test Enable (ATOEN): Selects the analog test signal that is driven on the analog test output pin. Otherwise the analog test output is tri-stated. This allows analog test output pins from multiple PLLs to be connected together. Valid values are: +0000 = All PLL analog test signals are tri-stated 0001 = AC PLL analog test signal is driven out +0010 = DATX8 0 PLL analog test signal is driven out 0011 = DATX8 1 PLL analog test signal is driven out 0100 = DATX8 2 PLL analog test signal is driven out 0101 = DATX8 3 PLL analog test signal is driven out 0110 = DATX8 4 PLL analog test signal is driven out 0111 = DATX8 5 PLL analog test signal is driven out 1000 = DATX8 6 PLL analog test signal is driven out 1001 = DATX8 7 PLL analog test signal is driven out 1010 = DATX8 8 PLL analog test signal is driven out 1011 – 1111 = Reserved + 6 + 4 + read-write + + + ATC + Analog Test Control: Selects various PLL analog test signals to be brought out via PLL analog test output pin (pll_ato). Valid values are: +0000 = Reserved +0001 = vdd_ckin +0010 = vrfbf +0011 = vdd_cko +0100 = vp_cp +0101 = vpfil(vp) +0110 = Reserved +0111 = gd +1000 = vcntrl_atb +1001 = vref_atb +1010 = vpsf_atb +1011 – 1111 = Reserved + 2 + 4 + read-write + + + DTC + Digital Test Control: Selects various PLL digital test signals and other test mode signals to be brought out via bit [1] of the PLL digital test output (pll_dto[1]). Valid values are: +00 = ‘0’ (Test output is disabled) 01 = PLL x1 clock (X1) +10 = PLL reference (input) clock (REF_CLK) 11 = PLL feedback clock (FB_X1) + 0 + 2 + read-write + + + + + PTR0 + PHY Timing Registers 0-4 (PTR0-4) + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + TPLLPD + PLL Power-Down Time: Number of configuration or APB clock cycles that the PLL must remain in power-down mode, i.e. number of clock cycles from when PLL power-down pin is asserted to when PLL power-down pin is de-asserted. This must correspond to a value that is equal to or more than 1us. Default value corresponds to 1us. + 21 + 11 + read-write + + + TPLLGS + PLL Gear Shift Time: Number of configuration or APB clock cycles from when the PLL reset pin is de-asserted to when the PLL gear shift pin is de-asserted. This must correspond to a value that is equal to or more than 4us. Default value corresponds to 4us. + 6 + 15 + read-write + + + TPHYRST + PHY Reset Time: Number of configuration or APB clock cycles that the PHY reset must remain asserted after PHY calibration is done before the reset to the PHY is de-asserted. This is used to extend the reset to the PHY so that the reset is asserted for some clock cycles after the clocks are stable. Valid values are from 1 to 63 (the value must be non-zero). + 0 + 6 + read-write + + + + + PTR1 + PHY Timing Registers 0-4 (PTR0-4) + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + TPLLLOCK + PLL Lock Time: Number of configuration or APB clock cycles for the PLL to stabilize and lock, i.e. number of clock cycles from when the PLL reset pin is de-asserted to when the PLL has lock and is ready for use. This must correspond to a value that is equal to or more than 100us. Default value corresponds to 100us. + 16 + 16 + read-write + + + TPLLRST + PLL Reset Time: Number of configuration or APB clock cycles that the PLL must remain in reset mode, i.e. number of clock cycles from when PLL power-down pin is de-asserted and PLL reset pin is asserted to when PLL reset pin is de-asserted. +The setting must correspond to a value that is equal to, or greater than, 3us. + 0 + 13 + read-write + + + + + PTR2 + PHY Timing Registers 0-4 (PTR0-4) + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + TWLDLYS + Write Leveling Delay Settling Time: Number of controller clock cycles from when a new value of the write leveling delay is applies to the LCDL to when to DQS high is driven high. This allows the delay to settle. + 15 + 5 + read-write + + + TCALH + Calibration Hold Time: Number of controller clock cycles from when the clock was disabled (cal_clk_en deasserted) to when calibration is enable (cal_en asserted). + 10 + 5 + read-write + + + TCALS + Calibration Setup Time: Number of controller clock cycles from when calibration is enabled (cal_en asserted) to when the calibration clock is asserted again (cal_clk_en asserted). + 5 + 5 + read-write + + + TCALON + Calibration On Time: Number of clock cycles that the calibration clock is enabled (cal_clk_en asserted). + 0 + 5 + read-write + + + + + PTR3 + PHY Timing Registers 0-4 (PTR0-4) + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + TDINIT1 + DRAM Initialization Time 1: DRAM initialization time in DRAM clock cycles corresponding to the following: +DDR3 = CKE high time to first command (tRFC + 10 ns or 5 tCK, whichever is bigger) DDR2 = CKE high time to first command (400 ns) +Default value corresponds to DDR3 tRFC of 360ns at 1066 MHz. + 20 + 9 + read-write + + + TDINIT0 + DRAM Initialization Time 0: DRAM initialization time in DRAM clock cycles corresponding to the following: +DDR3 = CKE low time with power and clock stable (500 us) DDR2 = CKE low time with power and clock stable (200 us) Default value corresponds to DDR3 500 us at 1066 MHz. +During Verilog simulations, it is recommended that this value is changed to a much smaller value in order to avoid long simulation times. However, this may cause a memory model error, due to a violation of the CKE setup sequence. This violation is expected if this value is not programmed to the required SDRAM CKE low time, but memory models should be able to tolerate this violation without malfunction of the model. + 0 + 20 + read-write + + + + + PTR4 + PHY Timing Registers 0-4 (PTR0-4) + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + TDINIT3 + DRAM Initialization Time 3: DRAM initialization time in DRAM clock cycles corresponding to the following: +DDR3 = Time from ZQ initialization command to first command (1 us) Default value corresponds to the DDR3 640ns at 1066 MHz. + 18 + 10 + read-write + + + TDINIT2 + DRAM Initialization Time 2: DRAM initialization time in DRAM clock cycles corresponding to the following: +DDR3 = Reset low time (200 us on power-up or 100 ns after power-up) Default value corresponds to DDR3 200 us at 1066 MHz. + 0 + 18 + read-write + + + + + ACMDLR + “AC Master Delay Line Register (ACMDLR)” on page 96 + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + MDLD + MDL Delay: Delay select for the LCDL for the Master Delay Line. + 16 + 8 + read-write + + + TPRD + Target Period: Target period measured by the master delay line calibration for VT drift compensation. This is the current measured value of the period and is continuously updated if the MDL is enabled to do so. + 8 + 8 + read-write + + + IPRD + Initial Period: Initial period measured by the master delay line calibration for VT drift compensation. This value is used as the denominator when calculating the ratios of updates during VT compensation. + 0 + 8 + read-write + + + + + ACBDLR + “AC Bit Delay Line Register (ACBDLR)” on page 96 + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + ACBD + Address/Command Bit Delay: Delay select for the BDLs on address and command signals. + 18 + 6 + read-write + + + CK2BD + CK2 Bit Delay: Delay select for the BDL on CK2. + 12 + 6 + read-write + + + CK1BD + CK1 Bit Delay: Delay select for the BDL on CK1. + 6 + 6 + read-write + + + CK0BD + CK0 Bit Delay: Delay select for the BDL on CK0. + 0 + 6 + read-write + + + + + ACIOCR + “AC I/O Configuration Register (ACIOCR)” on page 97 + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + ACSR + Address/Command Slew Rate (D3F I/O Only): Selects slew rate of the I/O for all address and command pins. + 30 + 2 + read-write + + + RSTIOM + SDRAM Reset I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for SDRAM Reset. + 29 + 1 + read-write + + + RSTPDR + SDRAM Reset Power Down Receiver: Powers down, when set, the input receiver on the I/O for SDRAM RST# pin. + 28 + 1 + read-write + + + RSTPDD1 + SDRAM Reset Power Down Driver: Powers down, when set, the output driver on the I/O for SDRAM RST# pin. + 27 + 1 + read-write + + + RSTODT + SDRAM Reset On-Die Termination: Enables, when set, the on-die termination on the I/O for SDRAM RST# pin. + 26 + 1 + read-write + + + RANKPDR + Rank Power Down Receiver: Powers down, when set, the input receiver on the I/O CKE[3:0], ODT[3:0], and CS#[3:0] pins. RANKPDR[0] controls the power down for CKE[0], ODT[0], and CS#[0], RANKPDR[1] controls the power down for CKE[1], ODT[1], and CS#[1], and so on. + 22 + 4 + read-write + + + CSPDD1 + CS# Power Down Driver: Powers down, when set, the output driver on the I/O for CS#[3:0] pins. CSPDD[0] controls the power down for CS#[0], CSPDD[1] controls the power down for CS#[1], and so on. CKE and ODT driver power down is controlled by DSGCR register. + 18 + 4 + read-write + + + RANKODT + Rank On-Die Termination: Enables, when set, the on-die termination on the I/O for CKE[3:0], ODT[3:0], and CS#[3:0] pins. RANKODT[0] controls the on-die termination for CKE[0], ODT[0], and CS#[0], RANKODT[1] controls the on-die termination for CKE[1], ODT[1], and CS#[1], and so on. + 14 + 4 + read-write + + + CKPDR + CK Power Down Receiver: Powers down, when set, the input receiver on the I/O for CK[0], CK[1], and CK[2] pins, respectively. + 11 + 3 + read-write + + + CKPDD1 + CK Power Down Driver: Powers down, when set, the output driver on the I/O for CK[0], CK[1], and CK[2] pins, respectively. + 8 + 3 + read-write + + + CKODT + CK On-Die Termination: Enables, when set, the on-die termination on the I/O for CK[0], CK[1], and CK[2] pins, respectively. + 5 + 3 + read-write + + + ACPDR + AC Power Down Receiver: Powers down, when set, the input receiver on the I/O for RAS#, CAS#, WE#, BA[2:0], and A[15:0] pins. + 4 + 1 + read-write + + + ACPDD1 + AC Power Down Driver: Powers down, when set, the output driver on the I/O for RAS#, CAS#, WE#, BA[2:0], and A[15:0] pins. + 3 + 1 + read-write + + + ACODT + Address/Command On-Die Termination: Enables, when set, the on-die termination on the I/O for RAS#, CAS#, WE#, BA[2:0], and A[15:0] pins. + 2 + 1 + read-write + + + ACOE + Address/Command Output Enable: Enables, when set, the output driver on the I/O for all address and command pins. + 1 + 1 + read-write + + + ACIOM + Address/Command I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for all address and command pins. This bit connects to bit +[0] of the IOM pin on the D3F I/Os, and for other I/O libraries, it connects to the IOM pin of the I/O. + 0 + 1 + read-write + + + + + DXCCR + “DATX8 Common Configuration Register (DXCCR)” on page 99 + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + DDPDRCDO + Dynamic Data Power Down Receiver Count Down Offset: Offset applied in calculating window of time where receiver is powered up + 28 + 4 + read-write + + + DDPDDCDO + Dynamic Data Power Down Driver Count Down Offset: Offset applied in calculating window of time where driver is powered up + 24 + 4 + read-write + + + DYNDXPDR + Data Power Down Receiver: Dynamically powers down, when set, the input receiver on I/O for the DQ pins of the active DATX8 macros. Applies only when DXPDR and DXnGCR.DXPDR are not set to 1. Receiver is powered-up on a DFI READ command and powered-down (trddata_en + fixed_read_latency + n) HDR cycles after the last DFI READ command. Note that n is defined by the register bit field DXCCR[31:28] (DDPDRCDO). + 23 + 1 + read-write + + + DYNDXPDD1 + Dynamic Data Power Down Driver: Dynamically powers down, when set, the output driver on I/O for the DQ pins of the active DATX8 macros. Applies only when DXPDD and DXnGCR.DXPDD are not set to 1. Driver is powered-up on a DFI WRITE command and powered-down (twrlat + WL/2 + n) HDR cycles after the last DFI WRITE command. Note that n is defined by the register bit field DXCCR[27:24] (DDPDDCDO). + 22 + 1 + read-write + + + UDQIOM + Unused DQ I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for unused DQ pins. + 21 + 1 + read-write + + + UDQPDR + Unused DQ Power Down Receiver: Powers down, when set, the input receiver on the I/O for unused DQ pins. + 20 + 1 + read-write + + + UDQPDD1 + Unused DQ Power Down Driver: Powers down, when set, the output driver on the I/O for unused DQ pins. + 19 + 1 + read-write + + + UDQODT + Unused DQ On-Die Termination: Enables, when set, the on-die termination on the I/O for unused DQ pins. + 18 + 1 + read-write + + + MSBUDQ + Most Significant Byte Unused DQs: Specifies the number of DQ bits that are not used in the most significant byte. The used (valid) bits for this byte are [8-MSBDQ- 1:0]. To disable the whole byte, use the DXnGCR.DXEN register. + 15 + 3 + read-write + + + DXSR + Data Slew Rate (D3F I/O Only): Selects slew rate of the I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. + 13 + 2 + read-write + + + DQSNRES + DQS# Resistor: Selects the on-die pull-up/pull-down resistor for DQS# pins. Same encoding as DQSRES. +Refer PHY databook for pull-down/pull-up resistor values (RA_SEL/RB_SEL) for DQS/DQS_b. + 9 + 4 + read-write + + + DQSRES + DQS Resistor: Selects the on-die pull-down/pull-up resistor for DQS pins. DQSRES[3] selects pull-down (when set to 0) or pull-up (when set to 1). DQSRES[2:0] selects the resistor value. +Refer PHY databook for pull-down/pull-up resistor values (RA_SEL/RB_SEL) for DQS/DQS_b. + 5 + 4 + read-write + + + DXPDR + Data Power Down Receiver: Powers down, when set, the input receiver on I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. This bit is ORed with the PDR configuration bit of the individual DATX8. + 4 + 1 + read-write + + + DXPDD1 + Data Power Down Driver: Powers down, when set, the output driver on I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. This bit is ORed with the PDD configuration bit of the individual DATX8. + 3 + 1 + read-write + + + MDLEN + Master Delay Line Enable: Enables, if set, all DATX8 master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or on when calibration is manually triggered. These additional measurements are accumulated and filtered as long as this bit remains high. This bit is ANDed with the MDLEN bit in the individual DATX8. + 2 + 1 + read-write + + + DXIOM + Data I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. This bit is ORed with the IOM configuration bit of the individual DATX8. + 1 + 1 + read-write + + + DXODT + Data On-Die Termination: Enables, when set, the on-die termination on the I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. This bit is ORed with the ODT configuration bit of the individual DATX8 (“DATX8 General Configuration Register (DXnGCR)” on page 148) + 0 + 1 + read-write + + + + + DSGCR + “DDR System General Configuration Register (DSGCR)” on page 101 + 0x40 + 32 + 0x00000000 + 0xFFFFFFFF + + + CKEOE + SDRAM CKE Output Enable: Enables, when set, the output driver on the I/O for SDRAM CKE pins. + 31 + 1 + read-write + + + RSTOE + SDRAM Reset Output Enable: Enables, when set, the output driver on the I/O for SDRAM RST# pin. + 30 + 1 + read-write + + + ODTOE + SDRAM ODT Output Enable: Enables, when set, the output driver on the I/O for SDRAM ODT pins. + 29 + 1 + read-write + + + CKOE + SDRAM CK Output Enable: Enables, when set, the output driver on the I/O for SDRAM CK/CK# pins. + 28 + 1 + read-write + + + ODTPDD1 + ODT Power Down Driver: Powers down, when set, the output driver on the I/O for ODT[3:0] pins. ODTPDD[0] controls the power down for ODT[0], ODTPDD[1] controls the power down for ODT[1], and so on. + 24 + 4 + read-write + + + CKEPDD1 + CKE Power Down Driver: Powers down, when set, the output driver on the I/O for CKE[3:0] pins. CKEPDD[0] controls the power down for CKE[0], CKEPDD[1] controls the power down for CKE[1], and so on. + 20 + 4 + read-write + + + SDRMODE + Single Data Rate Mode: Indicates, if set, that the external controller is configured to run in single data rate (SDR) mode. Otherwise if not set the controller is running in half data rate (HDR) mode. This bit not supported in the current version of the PUB. + 19 + 1 + read-write + + + RRMODE + Rise-to-Rise Mode: Indicates, if set, that the PHY mission mode is configured to run in rise-to-rise mode. Otherwise if not set the PHY mission mode is running in rise-to- fall mode. + 18 + 1 + read-write + + + ATOAE + ATO Analog Test Enable: Enables, if set, the analog test output (ATO) I/O. + 17 + 1 + read-write + + + DTOOE + DTO Output Enable: Enables, when set, the output driver on the I/O for DTO pins. + 16 + 1 + read-write + + + DTOIOM + DTO I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DTO pins. + 15 + 1 + read-write + + + DTOPDR + DTO Power Down Receiver: Powers down, when set, the input receiver on the I/O for DTO pins. + 14 + 1 + read-write + + + DTOPDD1 + DTO Power Down Driver: Powers down, when set, the output driver on the I/O for DTO pins. + 13 + 1 + read-write + + + DTOODT + DTO On-Die Termination: Enables, when set, the on-die termination on the I/O for DTO pins. + 12 + 1 + read-write + + + PUAD + PHY Update Acknowledge Delay: Specifies the number of clock cycles that the indication for the completion of PHY update from the PHY to the controller should be delayed. This essentially delays, by this many clock cycles, the de-assertion of dfi_ctrlup_ack and dfi_phyupd_req signals relative to the time when the delay lines or I/Os are updated. + 8 + 4 + read-write + + + BRRMODE + Bypass Rise-to-Rise Mode: Indicates, if set, that the PHY bypass mode is configured to run in rise-to-rise mode. Otherwise if not set the PHY bypass mode is running in rise-to-fall mode. + 7 + 1 + read-write + + + DQSGX + DQS Gate Extension: Specifies, if set, that the DQS gating must be extended by two DRAM clock cycles and then re-centered, i.e. one clock cycle extension on either side. + 6 + 1 + read-write + + + CUAEN + Controller Update Acknowledge Enable: Specifies, if set, that the PHY should issue controller update acknowledge when the DFI controller update request is asserted. By default the PHY does not acknowledge controller initiated update requests but simply does an update whenever there is a controller update request. This speeds up the update. + 5 + 1 + read-write + + + LPPLLPD + Low Power PLL Power Down: Specifies, if set, that the PHY should respond to the DFI low power opportunity request and power down the PLL of the byte if the wakeup time request satisfies the PLL lock time. + 4 + 1 + read-write + + + LPIOPD + Low Power I/O Power Down: Specifies, if set, that the PHY should respond to the DFI low power opportunity request and power down the I/Os of the byte. + 3 + 1 + read-write + + + ZUEN + Impedance Update Enable: Specifies, if set, that in addition to DDL VT update, the PHY could also perform impedance calibration (update). +Refer to the “Impedance Control Register 0-1 (ZQnCR0-1)” on page 145 bit fields DFICU0, DFICU1 and DFICCU bits to control if an impedance calibration is performed (update) with a DFI controller update request. +Refer to the “Impedance Control Register 0-1 (ZQnCR0-1)” on page 145 bit fields DFIPU0 and DFIPU1 bits to control if an impedance calibration is performed (update) with a DFI PHY update request. + 2 + 1 + read-write + + + BDISEN + Byte Disable Enable: Specifies, if set, that the PHY should respond to DFI byte disable request. Otherwise the byte disable from the DFI is ignored in which case bytes can only be disabled using the DXnGCR register. + 1 + 1 + read-write + + + PUREN + PHY Update Request Enable: Specifies if set, that the PHY should issue PHY- initiated update request when there is DDL VT drift. + 0 + 1 + read-write + + + + + DCR + “DRAM Configuration Register (DCR)” on page 103 + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + UDIMM + Un-buffered DIMM Address Mirroring: Indicates, if set, that there is address mirroring on the second rank of an un-buffered DIMM (the rank connected to CS#[1]). In this case, the PUB re-scrambles the bank and address when sending mode register commands to the second rank. This only applies to PUB internal SDRAM transactions. Transactions generated by the controller must make its own adjustments when using an un-buffered DIMM. DCR[NOSRA] must be set if address mirroring is enabled. + 29 + 1 + read-write + + + DDR2T + DDR 2T Timing: Indicates, if set, that 2T timing should be used by PUB internally generated SDRAM transactions. + 28 + 1 + read-write + + + NOSRA + No Simultaneous Rank Access: Specifies, if set, that simultaneous rank access on the same clock cycle is not allowed. This means that multiple chip select signals should not be asserted at the same time. This may be required on some DIMM systems. + 27 + 1 + read-write + + + BYTEMASK + Byte Mask: Mask applied to all beats of read data on all bytes lanes during read DQS gate training. This allows training to be conducted based on selected bit(s) from the byte lanes. +Valid values for each bit are: +0 = Disable compare for that bit 1 = Enable compare for that bit +Note that this mask applies in DDR3 MPR operation mode as well and must be in keeping with the PDQ field setting. + 10 + 8 + read-write + + + MPRDQ + Multi-Purpose Register (MPR) DQ (DDR3 Only): Specifies the value that is driven on non-primary DQ pins during MPR reads. Valid values are: +0 = Primary DQ drives out the data from MPR (0-1-0-1); non-primary DQs drive ‘0’ 1 = Primary DQ and non-primary DQs all drive the same data from MPR (0-1-0-1) + 7 + 1 + read-write + + + PDQ + Primary DQ (DDR3 Only): Specifies the DQ pin in a byte that is designated as a primary pin for Multi-Purpose Register (MPR) reads. Valid values are 0 to 7 for DQ[0] to DQ[7], respectively. + 4 + 3 + read-write + + + DDR8BNK + DDR 8-Bank: Indicates, if set, that the SDRAM used has 8 banks. tRPA = tRP+1 and tFAW are used for 8-bank DRAMs, otherwise tRPA = tRP and no tFAW is used. +Note that a setting of 1 for DRAMs that have fewer than 8 banks results in correct functionality, but less tight DRAM command spacing for the parameters. + 3 + 1 + read-write + + + DDRMD + DDR Mode: SDRAM DDR mode. Valid values are: 000 = Reserved +001 = Reserved +010 = DDR2 +011 = DDR3 +100 – 111 = Reserved + 0 + 3 + read-write + + + + + DTPR0 + DRAM Timing Parameters Register 0-2 (DTPR0-2) + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRC + Activate to activate command delay (same bank). Valid values are 2 to 63. + 26 + 6 + read-write + + + TRRD + Activate to activate command delay (different banks). Valid values are 1 to 15. + 22 + 4 + read-write + + + TRAS + Activate to precharge command delay. Valid values are 2 to 63. + 16 + 6 + read-write + + + TRCD + Activate to read or write delay. Minimum time from when an activate command is issued to when a read or write to the activated row can be issued. Valid values are 2 to 15. + 12 + 4 + read-write + + + TRP + Precharge command period: The minimum time between a precharge command and any other command. Note that the Controller automatically derives tRPA for 8- bank DDR2 devices by adding 1 to tRP. Valid values are 2 to 15. + 8 + 4 + read-write + + + TWTR + Internal write to read command delay. Valid values are 1 to 15. + 4 + 4 + read-write + + + TRTP + Internal read to precharge command delay. Valid values are 2 to 15. + 0 + 4 + read-write + + + + + DTPR1 + DRAM Timing Parameters Register 0-2 (DTPR0-2) + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + TAOND_TAOFD + ODT turn-on/turn-off delays (DDR2 only). Valid values are: 00 = 2/2.5 +01 = 3/3.5 +10 = 4/4.5 +11 = 5/5.5 +Most DDR2 devices utilize a fixed value of 2/2.5. For non-standard SDRAMs, the user must ensure that the operational Write Latency is always greater than or equal to the ODT turn-on delay. For example, a DDR2 SDRAM with CAS latency set to 3 and CAS additive latency set to 0 has a Write Latency of 2. Thus 2/2.5 can be used, but not 3/3.5 or higher. + 30 + 2 + read-write + + + TWLO + Write leveling output delay: Number of clock cycles from when write leveling DQS is driven high by the control block to when the results from the SDRAM on DQ is sampled by the control block. This must include the SDRAM tWLO timing parameter plus the round trip delay from control block to SDRAM back to control block. + 26 + 4 + read-write + + + TWLMRD + Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge. + 20 + 6 + read-write + + + TRFC + Refresh-to-Refresh: Indicates the minimum time between two refresh commands or between a refresh and an active command. This is derived from the minimum refresh interval from the datasheet, tRFC(min), divided by the clock cycle time. The default number of clock cycles is for the largest JEDEC tRFC(min parameter value supported. + 11 + 9 + read-write + + + TFAW + 4-bank activate period. No more than 4-bank activate commands may be issued in a given tFAW period. Only applies to 8-bank devices. Valid values are 2 to 63. + 5 + 6 + read-write + + + TMOD + Load mode update delay (DDR3 only). The minimum time between a load mode register command and a non-load mode register command. Valid values are: 000 = 12 +001 = 13 +010 = 14 +011 = 15 +100 = 16 +101 = 17 +110 – 111 = Reserved + 2 + 3 + read-write + + + TMRD + Load mode cycle time: The minimum time between a load mode register command and any other command. For DDR3 this is the minimum time between two load mode register commands. Valid values for DDR2 are 2 to 3. For DDR3, the value used for tMRD is 4 plus the value programmed in these bits, i.e. tMRD value for DDR3 ranges from 4 to 7. + 0 + 2 + read-write + + + + + DTPR2 + DRAM Timing Parameters Register 0-2 (DTPR0-2) + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + TCCD + Read to read and write to write command delay. Valid values are: 0 = BL/2 for DDR2 and 4 for DDR3 +1 = BL/2 + 1 for DDR2 and 5 for DDR3 + 31 + 1 + read-write + + + TRTW + Read to Write command delay. Valid values are: +0 = standard bus turn around delay +1 = add 1 clock to standard bus turn around delay +This parameter allows the user to increase the delay between issuing Write commands to the SDRAM when preceded by Read commands. This provides an option to increase bus turn-around margin for high frequency systems. + 30 + 1 + read-write + + + TRTODT + Read to ODT delay (DDR3 only). Specifies whether ODT can be enabled immediately after the read post-amble or one clock delay has to be added. Valid values are: +0 = ODT may be turned on immediately after read post-amble +1 = ODT may not be turned on until one clock after the read post-amble +If tRTODT is set to 1, then the read-to-write latency is increased by 1 if ODT is enabled. + 29 + 1 + read-write + + + TDLLK + DLL locking time. Valid values are 2 to 1023. + 19 + 10 + read-write + + + TCKE + CKE minimum pulse width. Also specifies the minimum time that the SDRAM must remain in power down or self refresh mode. For DDR3 this parameter must be set to the value of tCKESR which is usually bigger than the value of tCKE. Valid values are 2 to 15. + 15 + 4 + read-write + + + TXP + Power down exit delay. The minimum time between a power down exit command and any other command. This parameter must be set to the maximum of the various minimum power down exit delay parameters specified in the SDRAM datasheet, i.e. max(tXP, tXARD, tXARDS) for DDR2 and max(tXP, tXPDLL) for DDR3. Valid values are 2 to 31. + 10 + 5 + read-write + + + TXS + Self refresh exit delay. The minimum time between a self refresh exit command and any other command. This parameter must be set to the maximum of the various minimum self refresh exit delay parameters specified in the SDRAM datasheet, i.e. max(tXSNR, tXSRD) for DDR2 and max(tXS, tXSDLL) for DDR3. Valid values are 2 to 1023. + 0 + 10 + read-write + + + + + MR0 + “Mode Register 0 (MR0)” on page 108 + UNION_MR0 + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + PD + Power-Down Control: Controls the exit time for power-down modes. Refer to the SDRAM datasheet for details on power-down modes. Valid values are: +0 = Slow exit (DLL off) 1 = Fast exit (DLL on) + 12 + 1 + read-write + + + WR + Write Recovery: This is the value of the write recovery. It is calculated by dividing the datasheet write recovery time, tWR (ns) by the datasheet clock cycle time, tCK (ns) and rounding up a non-integer value to the next integer. Valid values are: +000 = 16 +001 = 5 +010 = 6 +011 = 7 +100 = 8 +101 = 10 +110 = 12 +111 = 14 +All other settings are reserved and should not be used. +NOTE: tWR (ns) is the time from the first SDRAM positive clock edge after the last data-in pair of a write command, to when a precharge of the same bank can be issued. + 9 + 3 + read-write + + + DR + DLL Reset: Writing a ‘1’ to this bit will reset the SDRAM DLL. This bit is self- clearing, i.e. it returns back to ‘0’ after the DLL reset has been issued. + 8 + 1 + read-write + + + TM + Operating Mode: Selects either normal operating mode (0) or test mode (1). Test mode is reserved for the manufacturer and should not be used. + 7 + 1 + read-write + + + CLH + CAS Latency: The delay between when the SDRAM registers a read command to when data is available. Valid values are: +0010 = 5 +0100 = 6 +0110 = 7 +1000 = 8 +1010 = 9 +1100 = 10 +1110 = 11 +0001 = 12 +0011 = 13 +0101 = 14 +All other settings are reserved and should not be used. + 4 + 3 + read-write + + + BT + Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). + 3 + 1 + read-write + + + CLL + CAS Latency low bit + 2 + 1 + read-write + + + BL + Burst Length: Determines the maximum number of column locations that can be accessed during a given read or write command. Valid values are: +Valid values for DDR3 are: 00 = 8 (Fixed) +01 = 4 or 8 (On the fly) +10 = 4 (Fixed) +11 = Reserved + 0 + 2 + read-write + + + + + MR + No description available + UNION_MR0 + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + PD + Power-Down Control: Controls the exit time for power-down modes. Refer to the SDRAM datasheet for details on power-down modes. Valid values are: +0 = Fast exit 1 = Slow exit + 12 + 1 + read-write + + + WR + Write Recovery: This is the value of the write recovery. It is calculated by dividing the datasheet write recovery time, tWR (ns) by the datasheet clock cycle time, tCK (ns) and rounding up a non-integer value to the next integer. Valid values are: +001 = 2 +010 = 3 +011 = 4 +100 = 5 +101 = 6 +All other settings are reserved and should not be used. +NOTE: tWR (ns) is the time from the first SDRAM positive clock edge after the last data-in pair of a write command, to when a precharge of the same bank can be issued. + 9 + 3 + read-write + + + DR + DLL Reset: Writing a ‘1’ to this bit will reset the SDRAM DLL. This bit is self- clearing, i.e. it returns back to ‘0’ after the DLL reset has been issued. + 8 + 1 + read-write + + + TM + Operating Mode: Selects either normal operating mode (0) or test mode (1). Test mode is reserved for the manufacturer and should not be used. + 7 + 1 + read-write + + + CL + CAS Latency: The delay between when the SDRAM registers a read command to when data is available. Valid values are: +010 = 2 +011 = 3 +100 = 4 +101 = 5 +110 = 6 +111 = 7 +All other settings are reserved and should not be used. + 4 + 3 + read-write + + + BT + Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). + 3 + 1 + read-write + + + BL + Burst Length: Determines the maximum number of column locations that can be accessed during a given read or write command. Valid values are: +010 = 4 +011 = 8 +All other settings are reserved and should not be used. + 0 + 3 + read-write + + + + + MR1 + “Mode Register 1 (MR1)” on page 111 + UNION_MR1 + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + QOFF + Output Enable/Disable: When ‘0’, all outputs function normal; when ‘1’ all SDRAM outputs are disabled removing output buffer current. This feature is intended to be used for IDD characterization of read current and should not be used in normal operation. + 12 + 1 + read-write + + + TDQS + Termination Data Strobe: When enabled (‘1’) TDQS provides additional termination resistance outputs that may be useful in some system configurations. Refer to the SDRAM datasheet for details. + 11 + 1 + read-write + + + RTTH + On Die Termination high bit + 9 + 1 + read-write + + + LEVEL + Write Leveling Enable: Enables write-leveling when set. + 7 + 1 + read-write + + + RTTM + On Die Termination mid bit: +Selects the effective resistance for SDRAM on die termination. Valid values are: +000 = ODT disabled 001 = RZQ/4 +010 = RZQ/2 +011 = RZQ/6 +100 = RZQ/12 +101 = RZQ/8 +All other settings are reserved and should not be used. +Bit on [9, 6,2] + 6 + 1 + read-write + + + DICH + Output Driver Impedance Control high bit: +Controls the output drive strength. Valid values are: +00 = RZQ/6 +01 = RZQ7 +10 = Reserved +11 = Reserved + 5 + 1 + read-write + + + AL + Posted CAS Additive Latency: Setting additive latency that allows read and write commands to be issued to the SDRAM earlier than normal (refer to the SDRAM datasheet for details). Valid values are: +00 = 0 (AL disabled) +01 = CL - 1 +10 = CL - 2 +11 = Reserved + 3 + 2 + read-write + + + RTTL + On Die Termination low bit + 2 + 1 + read-write + + + DICL + Output Driver Impedance Control low bit + 1 + 1 + read-write + + + DE + DLL Enable/Disable: Enable (0) or disable (1) the DLL. DLL must be enabled for normal operation. +Note: SDRAM DLL off mode is not supported + 0 + 1 + read-write + + + + + EMR + No description available + UNION_MR1 + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + QOFF + Output Enable/Disable: When ‘0’, all outputs function normal; when ‘1’ all SDRAM outputs are disabled removing output buffer current. This feature is intended to be +used for IDD characterization of read current and should not be used in normal operation. + 12 + 1 + read-write + + + RDQS + RDQS Enable/Disable: When enabled (‘1’), RDQS is identical in function and timing to data strobe DQS during a read, and ignored during a write. A ‘0’ disables the SDRAM from driving RDQS. The Controller does not allow the user to change this bit. + 11 + 1 + read-write + + + DQS + DQS_b Enable/Disable: When ‘0’, DQS_b is the complement of the differential data strobe pair DQS/DQS_b. When ‘1’, DQS is used in a single-ended mode and the DQS_b pin is disabled. Also used to similarly enable/disable RDQS_b if RDQS is enabled. The Controller does not allow the user to change this bit. + 10 + 1 + read-write + + + OCD + Off-Chip Driver (OCD) Impedance Calibration: Used to calibrate and match pull-up to pull- down impedance to 18  nominal (refer to the SDRAM datasheet for details). Valid values are: +000 = OCD calibration mode exit 001 = Drive (1) pull-up +010 = Drive (0) pull-down +100 = OCD enter adjust mode 111 = OCD calibration default +All other settings are reserved and should not be used. Note that OCD is not supported by all vendors. Refer to the SDRAM datasheet for details on the recommended OCD settings. + 7 + 3 + read-write + + + RTTH + On Die Termination high bit: +Selects the effective resistance for SDRAM on die termination. Valid values are: +00 = ODT disabled 01 = 75 +10 = 150 +11 = 50 (some vendors) + 6 + 1 + read-write + + + AL + Posted CAS Additive Latency: Setting additive latency that allows read and write commands to be issued to the SDRAM earlier than normal (refer to the SDRAM datasheet for details). Valid values are: +000 = 0 +001 = 1 +010 = 2 +011 = 3 +100 = 4 +101 = 5 +All other settings are reserved and should not be used. The maximum allowed value of AL is tRCD-1. + 3 + 3 + read-write + + + RTTL + On Die Termination low bit: + 2 + 1 + read-write + + + DIC + Output Driver Impedance Control: Controls the output drive strength. Valid values are: +0 = Full strength +1 = Reduced strength + 1 + 1 + read-write + + + DE + DLL Enable/Disable: Enable (0) or disable (1) the DLL. DLL must be enabled for normal operation. + 0 + 1 + read-write + + + + + MR2 + “Mode Register 2/Extended Mode Register 2 (MR2/EMR2)” on page 114 + UNION_MR2 + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + RTTWR + Dynamic ODT: Selects RTT for dynamic ODT. Valid values are: 00 = Dynamic ODT off +01 = RZQ/4 +10 = RZQ/2 +11 = Reserved + 9 + 2 + read-write + + + SRT + Self-Refresh Temperature Range: Selects either normal (‘0’) or extended (‘1’) operating temperature range during self-refresh. + 7 + 1 + read-write + + + ASR + Auto Self-Refresh: When enabled (‘1’), SDRAM automatically provides self-refresh power management functions for all supported operating temperature values. +Otherwise the SRT bit must be programmed to indicate the temperature range. + 6 + 1 + read-write + + + CWL + CAS Write Latency: The delay between when the SDRAM registers a write command to when write data is available. Valid values are: +000 = 5 (tCK > 2.5ns) +001 = 6 (2.5ns > tCK > 1.875ns) +010 = 7 (1.875ns > tCK> 1.5ns) +011 = 8 (1.5ns > tCK > 1.25ns) +100 = 9 (1.25ns > tCK > 1.07ns) +101 = 10 (1.07ns > tCK > 0.935ns) +110 = 11 (0.935ns > tCK > 0.833ns) +111 = 12 (0.833ns > tCK > 0.75ns) +All other settings are reserved and should not be used. + 3 + 3 + read-write + + + PASR + Partial Array Self Refresh: Specifies that data located in areas of the array beyond the specified location will be lost if self refresh is entered. +Valid settings for 4 banks are: +000 = Full Array +001 = Half Array (BA[1:0] = 00 & 01) +010 = Quarter Array (BA[1:0] = 00) 011 = Not defined +100 = 3/4 Array (BA[1:0] = 01, 10, & 11) +101 = Half Array (BA[1:0] = 10 & 11) +110 = Quarter Array (BA[1:0] = 11) 111 = Not defined +Valid settings for 8 banks are: +000 = Full Array +001 = Half Array (BA[2:0] = 000, 001, 010 & 011) +010 = Quarter Array (BA[2:0] = 000, 001) 011 = 1/8 Array (BA[2:0] = 000) +100 = 3/4 Array (BA[2:0] = 010, 011, 100, 101, 110 & 111) +101 = Half Array (BA[2:0] = 100, 101, 110 & 111) +110 = Quarter Array (BA[2:0] = 110 & 111) +111 = 1/8 Array (BA[2:0] 111) + 0 + 3 + read-write + + + + + EMR2 + No description available + UNION_MR2 + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + SRF + Self Refresh Rate: Enables, if set, high temperature self refresh rate. + 7 + 1 + read-write + + + DCC + Duty Cycle Corrector: Enables, if set, duty cycle correction within SDRAM. + 3 + 1 + read-write + + + PASR + Partial Array Self Refresh: Specifies that data located in areas of the array beyond the specified location will be lost if self refresh is entered. +Valid settings for 4 banks are: +000 = Full Array +001 = Half Array (BA[1:0] = 00 & 01) +010 = Quarter Array (BA[1:0] = 00) 011 = Not defined +100 = 3/4 Array (BA[1:0] = 01, 10, & 11) +101 = Half Array (BA[1:0] = 10 & 11) +110 = Quarter Array (BA[1:0] = 11) 111 = Not defined +Valid settings for 8 banks are: +000 = Full Array +001 = Half Array (BA[2:0] = 000, 001, 010 & 011) +010 = Quarter Array (BA[2:0] = 000, 001) 011 = 1/8 Array (BA[2:0] = 000) +100 = 3/4 Array (BA[2:0] = 010, 011, 100, 101, 110 & 111) +101 = Half Array (BA[2:0] = 100, 101, 110 & 111) +110 = Quarter Array (BA[2:0] = 110 & 111) +111 = 1/8 Array (BA[2:0] 111) + 0 + 3 + read-write + + + + + MR3 + “Mode Register 3 (MR3)” on page 116 + UNION_MR3 + 0x60 + 32 + 0x00000000 + 0xFFFFFFFF + + + MPR + Multi-Purpose Register Enable: Enables, if set, that read data should come from the Multi-Purpose Register. Otherwise read data come from the DRAM array. + 2 + 1 + read-write + + + MPRLOC + Multi-Purpose Register (MPR) Location: Selects MPR data location: Valid value are: 00 = Predefined pattern for system calibration +All other settings are reserved and should not be used. + 0 + 2 + read-write + + + + + EMR3 + No description available + UNION_MR3 + 0x60 + 32 + 0x00000000 + 0xFFFFFFFF + + + + + ODTCR + “ODT Configuration Register (ODTCR)” on page 117 + 0x64 + 32 + 0x00000000 + 0xFFFFFFFF + + + WRODT3 + No description available + 28 + 4 + read-write + + + WRODT2 + No description available + 24 + 4 + read-write + + + WRODT1 + No description available + 20 + 4 + read-write + + + WRODT0 + Write ODT: Specifies whether ODT should be enabled (‘1’) or disabled (‘0’) on each of the up to four ranks when a write command is sent to rank n. WRODT0, WRODT1, WRODT2, and WRODT3 specify ODT settings when a write is to rank 0, rank 1, rank 2, and rank 3, respectively. The four bits of each field each represent a rank, the LSB being rank 0 and the MSB being rank 3. Default is to enable ODT only on rank being written to. + 16 + 4 + read-write + + + RDODT3 + No description available + 12 + 4 + read-write + + + RDODT2 + No description available + 8 + 4 + read-write + + + RDODT1 + No description available + 4 + 4 + read-write + + + RDODT0 + Read ODT: Specifies whether ODT should be enabled (‘1’) or disabled (‘0’) on each of the up to four ranks when a read command is sent to rank n. RDODT0, RDODT1, RDODT2, and RDODT3 specify ODT settings when a read is to rank 0, rank 1, rank 2, and rank 3, respectively. The four bits of each field each represent a rank, the LSB being rank 0 and the MSB being rank 3. Default is to disable ODT during reads. + 0 + 4 + read-write + + + + + DTCR + “Data Training Configuration Register (DTCR)” on page 118 + 0x68 + 32 + 0x00000000 + 0xFF7FFFFF + + + RFSHDT + Refresh During Training: A non-zero value specifies that a burst of refreshes equal to the number specified in this field should be sent to the SDRAM after training each rank except the last rank. + 28 + 4 + read-write + + + RANKEN + Rank Enable: Specifies the ranks that are enabled for data-training. Bit 0 controls rank 0, bit 1 controls rank 1, bit 2 controls rank 2, and bit 3 controls rank 3. Setting the bit to ‘1’ enables the rank, and setting it to ‘0’ disables the rank. + 24 + 4 + read-write + + + DTEXD + Data Training Extended Write DQS: Enables, if set, an extended write DQS whereby two additional pulses of DQS are added as post-amble to a burst of writes. +Generally this should only be enabled when running read bit deskew with the intention of performing read eye deskew prior to running write leveling adjustment. + 22 + 1 + read-write + + + DTDSTP + Data Training Debug Step: A write of 1 to this bit steps the data training algorithm through a single step. This bit is used to initiate one step of the data training algorithm in question. +This bit is self-clearing. To trigger the next step, this bit must be written to again. Note: The training steps must be repeated in order to get new data in the “Data Training Eye Data Register 0-1 (DTEDR0-1)” on page 122. For example, to see the +training results for a different lane, select that lane and repeat the training steps to +populate DTEDR0 and DTEDR1 with the correct data. + 21 + 1 + read-write + + + DTDEN + Data Training Debug Enable: Enables, if set, the data training single step debug mode. + 20 + 1 + read-write + + + DTDBS + Data Training Debug Byte Select: Selects the byte during data training single step debug mode. +Note: DTDEN is not used to enable this feature. + 16 + 4 + read-write + + + DTWDQMO + Data Training WDQ Margin Override: If set, the Training WDQ Margin value specified in DTCR[11:8] (DTWDQM) is used during data training. Otherwise the value is computed as ¼ of the ddr_clk period measurement found during calibration of the WDQ LCDL. + 14 + 1 + read-write + + + DTBDC + Data Training Bit Deskew Centering: Enables, if set, eye centering capability during write and read bit deskew training. + 13 + 1 + read-write + + + DTWBDDM + Data Training Write Bit Deskew Data Mask, if set, it enables write bit deskew of the data mask + 12 + 1 + read-write + + + DTWDQM + Training WDQ Margin: Defines how close to 0 or how close to 2*(wdq calibration_value) the WDQ LCDL can be moved during training. Basically defines how much timing margin. + 8 + 4 + read-write + + + DTCMPD + Read Data Training Compare Data: Specifies, if set, that DQS gate training should also check if the returning read data is correct. Otherwise data-training only checks if the correct number of DQS edges were returned. + 7 + 1 + read-write + + + DTMPR + Read Data Training Using MPR (DDR3 Only): Specifies, if set, that DQS gate training should use the SDRAM Multi-Purpose Register (MPR) register. Otherwise data-training is performed by first writing to some locations in the SDRAM and then reading them back. + 6 + 1 + read-write + + + DTRANK + Data Training Rank: Select the SDRAM rank to be used during Read DQS gate training, Read/Write Data Bit Deskew, Read/Write Eye Training. + 4 + 2 + read-write + + + DTRPTN + Data Training Repeat Number: Repeat number used to confirm stability of DDR write or read. +Note: The minimum value should be 0x4 and the maximum value should be 0x14. + 0 + 4 + read-write + + + + + DTAR0 + Data Training Address Register 0-3 (DTAR0-3) + 0x6c + 32 + 0x00000000 + 0xFFFFFFFF + + + DTBANK + Data Training Bank Address: Selects the SDRAM bank address to be used during data training. + 28 + 3 + read-write + + + DTROW + Data Training Row Address: Selects the SDRAM row address to be used during data training. + 12 + 16 + read-write + + + DTCOL + Data Training Column Address: Selects the SDRAM column address to be used during data training. The lower four bits of this address must always be “000”. + 0 + 12 + read-write + + + + + DTAR1 + Data Training Address Register 0-3 (DTAR0-3) + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + DTBANK + Data Training Bank Address: Selects the SDRAM bank address to be used during data training. + 28 + 3 + read-write + + + DTROW + Data Training Row Address: Selects the SDRAM row address to be used during data training. + 12 + 16 + read-write + + + DTCOL + Data Training Column Address: Selects the SDRAM column address to be used during data training. The lower four bits of this address must always be “000”. + 0 + 12 + read-write + + + + + DTAR2 + Data Training Address Register 0-3 (DTAR0-3) + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + DTBANK + Data Training Bank Address: Selects the SDRAM bank address to be used during data training. + 28 + 3 + read-write + + + DTROW + Data Training Row Address: Selects the SDRAM row address to be used during data training. + 12 + 16 + read-write + + + DTCOL + Data Training Column Address: Selects the SDRAM column address to be used during data training. The lower four bits of this address must always be “000”. + 0 + 12 + read-write + + + + + DTAR3 + Data Training Address Register 0-3 (DTAR0-3) + 0x78 + 32 + 0x00000000 + 0xFFFFFFFF + + + DTBANK + Data Training Bank Address: Selects the SDRAM bank address to be used during data training. + 28 + 3 + read-write + + + DTROW + Data Training Row Address: Selects the SDRAM row address to be used during data training. + 12 + 16 + read-write + + + DTCOL + Data Training Column Address: Selects the SDRAM column address to be used during data training. The lower four bits of this address must always be “000”. + 0 + 12 + read-write + + + + + DTDR0 + Data Training Eye Data Register 0-1 (DTEDR0-1) + 0x7c + 32 + 0x00000000 + 0xFFFFFFFF + + + DTBYTE3 + No description available + 24 + 8 + read-write + + + DTBYTE2 + No description available + 16 + 8 + read-write + + + DTBYTE1 + No description available + 8 + 8 + read-write + + + DTBYTE0 + Data Training Data: The first 4 bytes of data used during data training. This same data byte is used for each Byte Lane. Default sequence is a walking 1 while toggling data every data cycle. + 0 + 8 + read-write + + + + + DTDR1 + Data Training Eye Data Register 0-1 (DTEDR0-1) + 0x80 + 32 + 0x00000000 + 0xFFFFFFFF + + + DTBYTE7 + No description available + 24 + 8 + read-write + + + DTBYTE6 + No description available + 16 + 8 + read-write + + + DTBYTE5 + No description available + 8 + 8 + read-write + + + DTBYTE4 + Data Training Data: The second 4 bytes of data used during data training. This same data byte is used for each Byte Lane. Default sequence is a walking 1 while toggling data every data cycle. + 0 + 8 + read-write + + + + + DTEDR0 + Data Training Eye Data Register 0-1 (DTEDR0-1) + 0x84 + 32 + 0x00000000 + 0xFFFFFFFF + + + DTWBMX + Data Training Write BDL Shift Maximum. + 24 + 8 + read-only + + + DTWBMN + Data Training Write BDL Shift Minimum. + 16 + 8 + read-only + + + DTWLMX + Data Training WDQ LCDL Maximum. + 8 + 8 + read-only + + + DTWLMN + Data Training WDQ LCDL Minimum. + 0 + 8 + read-only + + + + + DTEDR1 + Data Training Eye Data Register 0-1 (DTEDR0-1) + 0x88 + 32 + 0x00000000 + 0xFFFFFFFF + + + DTRBMX + Data Training Read BDL Shift Maximum. + 24 + 8 + read-only + + + DTRBMN + Data Training Read BDL Shift Minimum. + 16 + 8 + read-only + + + DTRLMX + Data Training RDQS LCDL Maximum. + 8 + 8 + read-only + + + DTRLMN + Data Training RDQS LCDL Minimum. + 0 + 8 + read-only + + + + + PGCR2 + “PHY General Configuration Register 2 (PGCR2)” on page 87 + 0x8c + 32 + 0x00000000 + 0xFFFFFFFF + + + DYNACPDD1 + Dynamic AC Power Down Driver: Powers down, when set, the output driver on I/O for ADDR and BA. This bit is ORed with bit ACIOCR[3] (ACPDD). + 31 + 1 + read-write + + + LPMSTRC0 + Low-Power Master Channel 0: set to 1 to have channel 0 act as master to drive channel 1 low-power functions simultaneously. Only valid in shared-AC mode. + 30 + 1 + read-write + + + ACPDDC + AC Power-Down with Dual Channels: Set to 1 to power-down address/command lane when both data channels are powered-down. Only valid in shared-AC mode. + 29 + 1 + read-write + + + SHRAC + Shared-AC mode: set to 1 to enable shared address/command mode with two independent data channels – available only if shared address/command mode support is compiled in. + 28 + 1 + read-write + + + DTPMXTMR + Data Training PUB Mode Timer Exit: Specifies the number of controller clocks to wait when entering and exiting pub mode data training. The default value ensures controller refreshes do not cause memory model errors when entering and exiting data training. The value should be increased if controller initiated SDRAM ZQ short or long operation may occur just before or just after the execution of data training. + 20 + 8 + read-write + + + FXDLAT + Fixed Latency: Specified whether all reads should be returned to the controller with a fixed read latency. Enabling fixed read latency increases the read latency. Valid values are: +0 = Disable fixed read latency 1 = Enable fixed read latency +Fixed read latency is calculated as (12 + (maximum DXnGTR.RxDGSL)/2) HDR clock cycles + 19 + 1 + read-write + + + NOBUB + No Bubbles: Specified whether reads should be returned to the controller with no bubbles. Enabling no-bubble reads increases the read latency. Valid values are: 0 = Bubbles are allowed during reads +1 = Bubbles are not allowed during reads + 18 + 1 + read-write + + + TREFPRD + Refresh Period: Indicates the period, after which the PUB has to issue a refresh command to the SDRAM. This is derived from the maximum refresh interval from the datasheet, tRFC(max) or REFI, divided by the clock cycle time. A further 400 clocks must be subtracted from the derived number to account for command flow and missed slots of refreshes in the internal PUB blocks. The default corresponds to DDR3 9*7.8us at 1066MHz when a burst of 9 refreshes are issued at every refresh interval. + 0 + 18 + read-write + + + + + RDIMMGCR0 + RDIMM General Configuration Register 0-1 (RDIMMGCR0-1) + 0xb0 + 32 + 0x00000000 + 0xFFFFFFFF + + + MIRROR + RDIMM Mirror: Selects between two different ballouts of the RDIMM buffer chip for front or back operation. This register bit controls the buffer chip MIRROR signal. + 31 + 1 + read-only + + + QCSEN + RDMIMM Quad CS Enable: Enables, if set, the Quad CS mode for the RDIMM registering buffer chip. This register bit controls the buffer chip QCSEN# signal. + 30 + 1 + read-only + + + MIRROROE + MIRROR Output Enable: Enables, when set, the output driver on the I/O for MIRROR pin. + 29 + 1 + read-only + + + QCSENOE + QCSEN# Output Enable: Enables, when set, the output driver on the I/O for QCSEN# pin. + 28 + 1 + read-only + + + RDIMMIOM + RDIMM Outputs I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for QCSEN# and MIRROR pins. + 27 + 1 + read-only + + + RDIMMPDR + RDIMM Outputs Power Down Receiver: Powers down, when set, the input receiver on the I/O for QCSEN# and MIRROR pins. + 26 + 1 + read-only + + + RDIMMPDD + RDIMM Outputs Power Down Driver: Powers down, when set, the output driver on the I/O for QCSEN# and MIRROR pins. + 25 + 1 + read-only + + + RDIMMODT + RDIMM Outputs On-Die Termination: Enables, when set, the on-die termination on the I/O for QCSEN# and MIRROR pins. + 24 + 1 + read-only + + + ERROUTOE + ERROUT# Output Enable: Enables, when set, the output driver on the I/O for ERROUT# pin. + 23 + 1 + read-only + + + ERROUTIOM + ERROUT# I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for ERROUT# pin. + 22 + 1 + read-only + + + ERROUTPDR + ERROUT# Power Down Receiver: Powers down, when set, the input receiver on the I/O for ERROUT# pin. + 21 + 1 + read-only + + + ERROUTPDD + ERROUT# Power Down Driver: Powers down, when set, the output driver on the I/O for ERROUT# pin. + 20 + 1 + read-only + + + ERROUTODT + ERROUT# On-Die Termination: Enables, when set, the on-die termination on the I/O for ERROUT# pin. + 19 + 1 + read-only + + + PARINOE + PAR_IN Output Enable: Enables, when set, the output driver on the I/O for PAR_IN pin. + 18 + 1 + read-only + + + PARINIOM + PAR_IN I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for PAR_IN pin. + 17 + 1 + read-only + + + PARINPDR + PAR_IN Power Down Receiver: Powers down, when set, the input receiver on the I/O for PAR_IN pin. + 16 + 1 + read-only + + + PARINPDD + PAR_IN Power Down Driver: Powers down, when set, the output driver on the I/O for PAR_IN pin. + 15 + 1 + read-only + + + PARINODT + PAR_IN On-Die Termination: Enables, when set, the on-die termination on the I/O for PAR_IN pin. + 14 + 1 + read-only + + + SOPERR + Stop On Parity Error: Indicates, if set, that the PUB is to stop driving commands to the DRAM upon encountering a parity error. Transactions can resume only after status is cleared via PIR.CLRSR. + 2 + 1 + read-only + + + ERRNOREG + Parity Error No Registering: Indicates, if set, that parity error signal from the RDIMM should be passed to the DFI controller without any synchronization or registering. Otherwise, the error signal is synchronized as shown in Figure 4-30 on page 262. + 1 + 1 + read-only + + + RDIMM + Registered DIMM: Indicates, if set, that a registered DIMM is used. In this case, the PUB increases the SDRAM write and read latencies (WL/RL) by 1 and also enforces that accesses adhere to RDIMM buffer chip. This only applies to PUB internal SDRAM transactions. Transactions generated by the controller must make its own adjustments to WL/RL when using a registered DIMM. The DCR.NOSRA register bit must be set to ‘1’ if using the standard RDIMM buffer chip so that normal DRAM accesses do not assert multiple chip select bits at the same time. + 0 + 1 + read-only + + + + + RDIMMGCR1 + RDIMM General Configuration Register 0-1 (RDIMMGCR0-1) + 0xb4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CRINIT + Control Registers Initialization Enable: Indicates which RDIMM buffer chip control registers (RC0 to RC15) should be initialized (written) when the PUB is triggered to initialize the buffer chip. A setting of ‘1’ on CRINIT[n] bit means that CRn should be written during initialization. + 16 + 16 + read-only + + + TBCMRD + Command word to command word programming delay: Number of DRAM clock cycles between two RDIMM buffer chip command programming accesses. The value used for tBCMRD is 8 plus the value programmed in these bits, i.e. tBCMRD value ranges from 8 to 15. This parameter corresponds to the buffer chip tMRD parameter. + 12 + 3 + read-only + + + TBCSTAB + Stabilization time: Number of DRAM clock cycles for the RDIMM buffer chip to stabilize. This parameter corresponds to the buffer chip tSTAB parameter. Default value is in decimal format and corresponds to 6us at 533MHz. + 0 + 12 + read-only + + + + + RDIMMCR0 + RDIMM Control Register 0-1 (RDIMMCR0-1) + 0xb8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RC7 + Control Word 7: Reserved, free to use by vendor. + 28 + 4 + read-only + + + RC6 + Control Word 6: Reserved, free to use by vendor. + 24 + 4 + read-only + + + RC5 + Control Word 5 (CK Driver Characteristics Control Word): RC5[1:0] is driver settings for clock Y1, Y1#, Y3, and Y3# outputs, and RC5[3:2] is driver settings for clock Y0, Y0#, Y2, and Y2# outputs. Bit definitions are: +00 = Light drive (4 or 5 DRAM loads) +01 = Moderate drive (8 or 10 DRAM loads) +10 = Strong drive (16 or 20 DRAM loads) +11 = Reserved + 20 + 4 + read-only + + + RC4 + Control Word 4 (Control Signals Driver Characteristics Control Word): RC4[1:0] is driver settings for control A outputs, and RC4[3:2] is driver settings for control B outputs. Bit definitions are: +00 = Light drive (4 or 5 DRAM loads) +01 = Moderate drive (8 or 10 DRAM loads) +10 = Reserved +11 = Reserved + 16 + 4 + read-only + + + RC3 + Control Word 3 (Command/Address Signals Driver Characteristics Control Word): RC3[1:0] is driver settings for command/address A outputs, and RC3[3:2] is driver settings for command/address B outputs. Bit definitions are: +00 = Light drive (4 or 5 DRAM loads) +01 = Moderate drive (8 or 10 DRAM loads) +10 = Strong drive (16 or 20 DRAM loads) +11 = Reserved + 12 + 4 + read-only + + + RC2 + Control Word 2 (Timing Control Word): Bit definitions are: +RC2[0]: 0 = Standard (1/2 clock) pre-launch, 1 = Prelaunch controlled by RC12. RC2[1]: 0 = Reserved. +RC2[2]: 0 = 100 Ohm input bus termination, 1 = 150 Ohm input bus termination. RC2[3]: 0 = Operation frequency band 1, 1 = Test mode frequency band 2. + 8 + 4 + read-only + + + RC1 + Control Word 1 (Clock Driver Enable Control Word): Bit definitions are: RC1[0]: 0 = Y0/Y0# clock enabled, 1 = Y0/Y0# clock disabled. +RC1[1]: 0 = Y1/Y1# clock enabled, 1 = Y1/Y1# clock disabled. RC1[2]: 0 = Y2/Y2# clock enabled, 1 = Y2/Y2# clock disabled. RC1[3]: 0 = Y3/Y3# clock enabled, 1 = Y3/Y3# clock disabled. + 4 + 4 + read-only + + + RC0 + Control Word 0 (Global Features Control Word): Bit definitions are: RC0[0]: 0 = Output inversion enabled, 1 = Output inversion disabled. RC0[1]: 0 = Floating outputs disabled, 1 = Floating outputs enabled. RC0[2]: 0 = A outputs enabled, 1 = A outputs disabled. +RC0[3]: 0 = B outputs enabled, 1 = B outputs disabled. + 0 + 4 + read-only + + + + + RDIMMCR1 + RDIMM Control Register 0-1 (RDIMMCR0-1) + 0xbc + 32 + 0x00000000 + 0xFFFFFFFF + + + RC15 + Control Word 15: Reserved for future use. + 28 + 4 + read-only + + + RC14 + Control Word 14: Reserved for future use. + 24 + 4 + read-only + + + RC13 + Control Word 13: Reserved for future use. + 20 + 4 + read-only + + + RC12 + Control Word 12: Reserved for future use. + 16 + 4 + read-only + + + RC11 + Control Word 11 (Operating Voltage VDD Control Word): RC10[1:0] is VDD operating voltage setting as follows: 00 = DDR3 1.5V mode +01 = DDR3L 1.35V mode +10 = Reserved +11 = Reserved RC10[3:2]: Reserved. + 12 + 4 + read-only + + + RC10 + Control Word 10 (RDIMM Operating Speed Control Word): RC10[2:0] is RDIMM operating speed setting as follows: 000 = DDR3/DDR3L-800 +001 = DDR3/DDR3L-1066 +010 = DDR3/DDR3L-1333 +011 = DDR3/DDR3L-1600 +100 = Reserved +101 = Reserved +110 = Reserved +111 = Reserved RC10[3]: Don’t care. + 8 + 4 + read-only + + + RC9 + Control Word 9 (Power Saving Settings Control Word): Bit definitions are: RC9[0]: 0 = Floating outputs as defined in RC0, 1 = Weak drive enabled. RC9[1]: 0 = Reserved. +RC9[2]: 0 = CKE power down with IBT ON, QxODT is a function of DxODT, 1 = CKE power down with IBT off, QxODT held LOW. RC9[2] is valid only when RC9[3] is 1. +RC9[3]: 0 = CKE power down mode disabled, 1 = CKE power down mode enabled. + 4 + 4 + read-only + + + RC8 + Control Word 8 (Additional Input Bus Termination Setting Control Word): RC8[2:0] is Input Bus Termination (IBT) setting as follows: +000 = IBT as defined in RC2. 001 = Reserved +010 = 200 Ohm +011 = Reserved +100 = 300 Ohm +101 = Reserved +110 = Reserved +111 = Off +RC8[3]: 0 = IBT off when MIRROR is HIGH, 1 = IBT on when MIRROR is high + 0 + 4 + read-only + + + + + DCUAR + “DCU Address Register (DCUAR)” on page 129 + 0xc0 + 32 + 0x00000000 + 0xFFFFFFFF + + + ATYPE + Access Type: Specifies the type of access to be performed using this address. Valid values are: +0 = Write access 1 = Read access + 11 + 1 + read-write + + + INCA + Increment Address: Specifies, if set, that the cache address specified in WADDR and SADDR should be automatically incremented after each access of the cache. The increment happens in such a way that all the slices of a selected word are first accessed before going to the next word. + 10 + 1 + read-write + + + CSEL + Cache Select: Selects the cache to be accessed. Valid values are: 00 = Command cache +01 = Expected data cache 10 = Read data cache +11 = Reserved + 8 + 2 + read-write + + + CSADDR + Cache Slice Address: Address of the cache slice to be accessed. + 4 + 4 + read-write + + + CWADDR + Cache Word Address: Address of the cache word to be accessed. + 0 + 4 + read-write + + + + + DCUDR + “DCU Data Register (DCUDR)” on page 130 + 0xc4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CDATA + Cache Data: Data to be written to or read from a cache. This data corresponds to the cache word slice specified by the DCU Address Register. + 0 + 32 + read-write + + + + + DCURR + “DCU Run Register (DCURR)” on page 130 + 0xc8 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCEN + Expected Compare Enable: Indicates, if set, that read data coming back from the SDRAM should be should be compared with the expected data. + 23 + 1 + read-write + + + RCEN + Read Capture Enable: Indicates, if set, that read data coming back from the SDRAM should be captured into the read data cache. + 22 + 1 + read-write + + + SCOF + Stop Capture On Full: Specifies, if set, that the capture of read data should stop when the capture cache is full. + 21 + 1 + read-write + + + SONF + Stop On Nth Fail: Specifies, if set, that the execution of commands and the capture of read data should stop when there are N read data failures. The number of failures is specified by NFAIL. Otherwise commands execute until the end of the program or until manually stopped using a STOP command. + 20 + 1 + read-write + + + NFAIL + Number of Failures: Specifies the number of failures after which the execution of commands and the capture of read data should stop if SONF bit of this register is set. Execution of commands and the capture of read data will stop after (NFAIL+1) failures if SONF is set. +Valid values are from 0 to 254. + 12 + 8 + read-write + + + EADDR + End Address: Cache word address where the execution of command should end. + 8 + 4 + read-write + + + SADDR + Start Address: Cache word address where the execution of commands should begin. + 4 + 4 + read-write + + + DINST + DCU Instruction: Selects the DCU command to be executed: Valid values are: 0000 = NOP: No operation +0001 = Run: Triggers the execution of commands in the command cache. 0010 = Stop: Stops the execution of commands in the command cache. +0011 = Stop Loop: Stops the execution of an infinite loop in the command cache. 0100 = Reset: Resets all DCU run time registers. See “DCU Status” on page 255 for details. +0101 – 1111 Reserved + 0 + 4 + read-write + + + + + DCULR + “DCU Loop Register (DCULR)” on page 131 + 0xcc + 32 + 0x00000000 + 0xFFFFFFFF + + + XLEADDR + Expected Data Loop End Address: The last expected data cache word address that contains valid expected data. Expected data should looped between 0 and this address. +XLEADDR field uses only the following bits based on the cache depth: +DCU expected data cache = 4, XLEADDR[1:0] +DCU expected data cache = 8, XLEADDR[2:0] +DCU expected data cache = 16, XLEADDR[3:0] + 28 + 4 + read-write + + + IDA + Increment DRAM Address: Indicates, if set, that DRAM addresses should be incremented every time a DRAM read/write command inside the loop is executed. + 17 + 1 + read-write + + + LINF + Loop Infinite: Indicates, if set, that the loop should be executed indefinitely until stopped by the STOP command. Otherwise the loop is execute LCNT times. + 16 + 1 + read-write + + + LCNT + Loop Count: The number of times that the loop should be executed if LINF is not set. + 8 + 8 + read-write + + + LEADDR + Loop End Address: Command cache word address where the loop should end. + 4 + 4 + read-write + + + LSADDR + Loop Start Address: Command cache word address where the loop should start. + 0 + 4 + read-write + + + + + DCUGCR + “DCU General Configuration Register (DCUGCR)” on page 132 + 0xd0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RCSW + Read Capture Start Word: The capture and compare of read data should start after Nth word. For example setting this value to 12 will skip the first 12 read data. + 0 + 16 + read-write + + + + + DCUTPR + “DCU Timing Parameter Register (DCUTPR)” on page 132 + 0xd4 + 32 + 0x00000000 + 0xFFFFFFFF + + + TDCUT3 + DCU Generic Timing Parameter 3 + 24 + 8 + read-write + + + TDCUT2 + DCU Generic Timing Parameter 2 + 16 + 8 + read-write + + + TDCUT1 + DCU Generic Timing Parameter 1 + 8 + 8 + read-write + + + TDCUT0 + DCU Generic Timing Parameter 0 + 0 + 8 + read-write + + + + + DCUSR0 + DCU Status Register 0-1 (DCUSR0-1) + 0xd8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CFULL + Capture Full: Indicates, if set, that the capture cache is full. + 2 + 1 + read-only + + + CFAIL + Capture Fail: Indicates, if set, that at least one read data word has failed. + 1 + 1 + read-only + + + RDONE + Run Done: Indicates, if set, that the DCU has finished executing the commands in the command cache. This bit is also set to indicate that a STOP command has successfully been executed and command execution has stopped. + 0 + 1 + read-only + + + + + DCUSR1 + DCU Status Register 0-1 (DCUSR0-1) + 0xdc + 32 + 0x00000000 + 0xFFFFFFFF + + + LPCNT + Loop Count: Indicates the value of the loop count. This is useful when the program has stopped because of failures to assess how many reads were executed before first fail. + 24 + 8 + read-only + + + FLCNT + Fail Count: Number of read words that have failed. + 16 + 8 + read-only + + + RDCNT + Read Count: Number of read words returned from the SDRAM. + 0 + 16 + read-only + + + + + BISTRR + “BIST Run Register (BISTRR)” on page 133 + 0x100 + 32 + 0x00000000 + 0xFFFFFFFF + + + BCCSEL + BIST Clock Cycle Select: Selects the clock numbers on which the AC loopback data is written into the FIFO. Data is written into the loopback FIFO once every four clock cycles. Valid values are: +00 = Clock cycle 0, 4, 8, 12, etc. +01 = Clock cycle 1, 5, 9, 13, etc. +10 = Clock cycle 2, 6, 10, 14, etc. +11 = Clock cycle 3, 7, 11, 15, etc. + 25 + 2 + read-write + + + BCKSEL + BIST CK Select: Selects the CK that should be used to register the AC loopback signals from the I/Os. Valid values are: +00 = CK[0] +01 = CK[1] +10 = CK[2] +11 = Reserved + 23 + 2 + read-write + + + BDXSEL + BIST DATX8 Select: Select the byte lane for comparison of loopback/read data. Valid values are 0 to 8. + 19 + 4 + read-write + + + BDPAT + BIST Data Pattern: Selects the data pattern used during BIST. Valid values are: 00 = Walking 0 +01 = Walking 1 +10 = LFSR-based pseudo-random +11 = User programmable (Not valid for AC loopback). + 17 + 2 + read-write + + + BDMEN + BIST Data Mask Enable: Enables, if set, that the data mask BIST should be included in the BIST run, i.e. data pattern generated and loopback data compared. This is valid only for loopback mode. + 16 + 1 + read-write + + + BACEN + BIST AC Enable: Enables the running of BIST on the address/command lane PHY. This bit is exclusive with BDXEN, i.e. both cannot be set to ‘1’ at the same time. + 15 + 1 + read-write + + + BDXEN + BIST DATX8 Enable: Enables the running of BIST on the data byte lane PHYs. This bit is exclusive with BACEN, i.e. both cannot be set to ‘1’ at the same time. + 14 + 1 + read-write + + + BSONF + BIST Stop On Nth Fail: Specifies, if set, that the BIST should stop when an nth data word or address/command comparison error has been encountered. + 13 + 1 + read-write + + + NFAIL + Number of Failures: Specifies the number of failures after which the execution of commands and the capture of read data should stop if BSONF bit of this register is set. Execution of commands and the capture of read data will stop after (NFAIL+1) failures if BSONF is set. + 5 + 8 + read-write + + + BINF + BIST Infinite Run: Specifies, if set, that the BIST should be run indefinitely until when it is either stopped or a failure has been encountered. Otherwise BIST is run until number of BIST words specified in the BISTWCR register has been generated. + 4 + 1 + read-write + + + BMODE + BIST Mode: Selects the mode in which BIST is run. Valid values are: +0 = Loopback mode: Address, commands and data loop back at the PHY I/Os. +1 = DRAM mode: Address, commands and data go to DRAM for normal memory accesses. + 3 + 1 + read-write + + + BINST + BIST Instruction: Selects the BIST instruction to be executed: Valid values are: 000 = NOP: No operation +001 = Run: Triggers the running of the BIST. 010 = Stop: Stops the running of the BIST. +011 = Reset: Resets all BIST run-time registers, such as error counters. 100 – 111 Reserved + 0 + 3 + read-write + + + + + BISTWCR + “BIST Word Count Register (BISTWCR)” on page 136 + 0x104 + 32 + 0x00000000 + 0xFFFFFFFF + + + BWCNT + BIST Word Count: Indicates the number of words to generate during BIST. This must be a multiple of DRAM burst length (BL) divided by 2, e.g. for BL=8, valid values are 4, 8, 12, 16, and so on. + 0 + 16 + read-write + + + + + BISTMSKR0 + BIST Mask Register 0-2 (BISTMSKR0-2) + 0x108 + 32 + 0x00000000 + 0xFFFFFFFF + + + ODTMSK + Mask bit for each of the up to 4 ODT bits. + 28 + 4 + read-write + + + CSMSK + Mask bit for each of the up to 4 CS# bits. + 24 + 4 + read-write + + + CKEMSK + Mask bit for each of the up to 4 CKE bits. + 20 + 4 + read-write + + + WEMSK + Mask bit for the WE#. + 19 + 1 + read-write + + + BAMSK + Mask bit for each of the up to 3 bank address bits. + 16 + 3 + read-write + + + AMSK + Mask bit for each of the up to 16 address bits. + 0 + 16 + read-write + + + + + BISTMSKR1 + BIST Mask Register 0-2 (BISTMSKR0-2) + 0x10c + 32 + 0x00000000 + 0xFFFFFFFF + + + DMMSK + Mask bit for the data mask (DM) bit. + 28 + 4 + read-write + + + PARMSK + Mask bit for the PAR_IN. Only for DIMM parity support and only if the design is compiled for less than 3 ranks. + 27 + 1 + read-write + + + CASMSK + Mask bit for the CAS. + 1 + 1 + read-write + + + RASMSK + Mask bit for the RAS. + 0 + 1 + read-write + + + + + BISTMSKR2 + BIST Mask Register 0-2 (BISTMSKR0-2) + 0x110 + 32 + 0x00000000 + 0xFFFFFFFF + + + DQMSK + Mask bit for each of the 8 data (DQ) bits. + 0 + 32 + read-write + + + + + BISTLSR + “BIST LFSR Seed Register (BISTLSR)” on page 137 + 0x114 + 32 + 0x00000000 + 0xFFFFFFFF + + + SEED + LFSR seed for pseudo-random BIST patterns. + 0 + 32 + read-write + + + + + BISTAR0 + BIST Address Register 0-2 (BISTAR0-2) + 0x118 + 32 + 0x00000000 + 0xFFFFFFFF + + + BBANK + BIST Bank Address: Selects the SDRAM bank address to be used during BIST. + 28 + 3 + read-write + + + BROW + BIST Row Address: Selects the SDRAM row address to be used during BIST. + 12 + 16 + read-write + + + BCOL + BIST Column Address: Selects the SDRAM column address to be used during BIST. The lower bits of this address must be “0000” for BL16, “000” for BL8, “00” for BL4 and “0” for BL2. + 0 + 12 + read-write + + + + + BISTAR1 + BIST Address Register 0-2 (BISTAR0-2) + 0x11c + 32 + 0x00000000 + 0xFFFFFFFF + + + BAINC + BIST Address Increment: Selects the value by which the SDRAM address is incremented for each write/read access. This value must be at the beginning of a burst boundary, i.e. the lower bits must be “0000” for BL16, “000” for BL8, “00” for BL4 and “0” for BL2. + 4 + 12 + read-write + + + BMRANK + BIST Maximum Rank: Specifies the maximum SDRAM rank to be used during BIST. The default value is set to maximum ranks minus 1. Example default shown here is for a 4-rank system + 2 + 2 + read-write + + + BRANK + BIST Rank: Selects the SDRAM rank to be used during BIST. Valid values range from 0 to maximum ranks minus 1. + 0 + 2 + read-write + + + + + BISTAR2 + BIST Address Register 0-2 (BISTAR0-2) + 0x120 + 32 + 0x00000000 + 0xFFFFFFFF + + + BMBANK + BIST Maximum Bank Address: Specifies the maximum SDRAM bank address to be used during BIST before the address increments to the next rank. + 28 + 3 + read-write + + + BMROW + BIST Maximum Row Address: Specifies the maximum SDRAM row address to be used during BIST before the address increments to the next bank. + 12 + 16 + read-write + + + BMCOL + BIST Maximum Column Address: Specifies the maximum SDRAM column address to be used during BIST before the address increments to the next row. + 0 + 12 + read-write + + + + + BISTUDPR + “BIST User Data Pattern Register (BISTUDPR)” on page 138 + 0x124 + 32 + 0x00000000 + 0xFFFFFFFF + + + BUDP1 + BIST User Data Pattern 1: Data to be applied on odd DQ pins during BIST. + 16 + 16 + read-write + + + BUDP0 + BIST User Data Pattern 0: Data to be applied on even DQ pins during BIST. + 0 + 16 + read-write + + + + + BISTGSR + “BIST General Status Register (BISTGSR)” on page 139 + 0x128 + 32 + 0x00000000 + 0xFFFFFFFF + + + CASBER + CAS Bit Error: Indicates the number of bit errors on CAS. + 30 + 2 + read-only + + + RASBER + RAS Bit Error: Indicates the number of bit errors on RAS. + 28 + 2 + read-only + + + DMBER + DM Bit Error: Indicates the number of bit errors on data mask (DM) bit. DMBER[1:0] are for even DQS cycles first DM beat, and DMBER[3:2] are for even DQS cycles second DM beat. Similarly, DMBER[5:4] are for odd DQS cycles first DM beat, and DMBER[7:6] are for odd DQS cycles second DM beat. + 20 + 8 + read-only + + + PARBER + PAR_IN Bit Error (DIMM Only): Indicates the number of bit errors on PAR_IN + 16 + 2 + read-only + + + BDXERR + BIST Data Error: indicates, if set, that there is a data comparison error in the byte lane. + 2 + 1 + read-only + + + BACERR + BIST Address/Command Error: indicates, if set, that there is a data comparison error in the address/command lane. + 1 + 1 + read-only + + + BDONE + BIST Done: Indicates, if set, that the BIST has finished executing. This bit is reset to zero when BIST is triggered. + 0 + 1 + read-only + + + + + BISTWER + “BIST Word Error Register (BISTWER)” on page 139 + 0x12c + 32 + 0x00000000 + 0xFFFFFFFF + + + DXWER + Byte Word Error: Indicates the number of word errors on the byte lane. An error on any bit of the data bus including the data mask bit increments the error count. + 16 + 16 + read-only + + + ACWER + Address/Command Word Error: Indicates the number of word errors on the address/command lane. An error on any bit of the address/command bus increments the error count. + 0 + 16 + read-only + + + + + BISTBER0 + BIST Bit Error Register 0-3 (BISTBER0-3) + 0x130 + 32 + 0x00000000 + 0xFFFFFFFF + + + ABER + Address Bit Error: Each group of two bits indicate the bit error count on each of the + 0 + 32 + read-only + + + + + BISTBER1 + BIST Bit Error Register 0-3 (BISTBER0-3) + 0x134 + 32 + 0x00000000 + 0xFFFFFFFF + + + ODTBER + ODT Bit Error: Each group of two bits indicates the bit error count on each of the up to 4 ODT bits. [1:0] is the error count for ODT[0], [3:2] for ODT[1], and so on. + 24 + 8 + read-only + + + CSBER + CS# Bit Error: Each group of two bits indicate the bit error count on each of the up to 4 CS# bits. [1:0] is the error count for CS#[0], [3:2] for CS#[1], and so on. + 16 + 8 + read-only + + + CKEBER + CKE Bit Error: Each group of two bits indicate the bit error count on each of the up to 4 CKE bits. [1:0] is the error count for CKE[0], [3:2] for CKE[1], and so on. + 8 + 8 + read-only + + + WEBER + WE# Bit Error: Indicates the number of bit errors on WE#. + 6 + 2 + read-only + + + BABER + Bank Address Bit Error: Each group of two bits indicate the bit error count on each of the up to 3 bank address bits. [1:0] is the error count for BA[0], [3:2] for BA[1], and so on. + 0 + 6 + read-only + + + + + BISTBER2 + BIST Bit Error Register 0-3 (BISTBER0-3) + 0x138 + 32 + 0x00000000 + 0xFFFFFFFF + + + DQBER0 + Data Bit Error: The error count for even DQS cycles. The first 16 bits indicate the error count for the first data beat (i.e. the data driven out on DQ[7:0] on the rising edge of DQS). The second 16 bits indicate the error on the second data beat (i.e. the error count of the data driven out on DQ[7:0] on the falling edge of DQS). For each of the 16-bit group, the first 2 bits are for DQ[0], the second for DQ[1], and so on. + 0 + 32 + read-only + + + + + BISTBER3 + BIST Bit Error Register 0-3 (BISTBER0-3) + 0x13c + 32 + 0x00000000 + 0xFFFFFFFF + + + DQBER1 + Data Bit Error: The error count for odd DQS cycles. The first 16 bits indicate the error count for the first data beat (i.e. the data driven out on DQ[7:0] on the rising edge of DQS). The second 16 bits indicate the error on the second data beat (i.e. the error count of the data driven out on DQ[7:0] on the falling edge of DQS). For each of the 16-bit group, the first 2 bits are for DQ[0], the second for DQ[1], and so on. + 0 + 32 + read-only + + + + + BISTWCSR + “BIST Word Count Status Register (BISTWCSR)” on page 141 + 0x140 + 32 + 0x00000000 + 0xFFFFFFFF + + + DXWCNT + Byte Word Count: Indicates the number of words received from the byte lane. + 16 + 16 + read-only + + + ACWCNT + Address/Command Word Count: Indicates the number of words received from the address/command lane. + 0 + 16 + read-only + + + + + BISTFWR0 + BIST Fail Word Register 0-2 (BISTFWR0-2) + 0x144 + 32 + 0x00000000 + 0xFFFFFFFF + + + ODTWEBS + Bit status during a word error for each of the up to 4 ODT bits. + 28 + 4 + read-only + + + CSWEBS + Bit status during a word error for each of the up to 4 CS# bits. + 24 + 4 + read-only + + + CKEWEBS + Bit status during a word error for each of the up to 4 CKE bits. + 20 + 4 + read-only + + + WEWEBS + Bit status during a word error for the WE#. + 19 + 1 + read-only + + + BAWEBS + Bit status during a word error for each of the up to 3 bank address bits. + 16 + 3 + read-only + + + AWEBS + Bit status during a word error for each of the up to 16 address bits. + 0 + 16 + read-only + + + + + BISTFWR1 + BIST Fail Word Register 0-2 (BISTFWR0-2) + 0x148 + 32 + 0x00000000 + 0xFFFFFFFF + + + DMWEBS + Bit status during a word error for the data mask (DM) bit. DMWEBS [0] is for the first DM beat, DMWEBS [1] is for the second DM beat, and so on. + 28 + 4 + read-only + + + PARWEBS + Bit status during a word error for the PAR_IN. Only for DIMM parity support + 26 + 1 + read-only + + + CASWEBS + Bit status during a word error for the CAS. + 1 + 1 + read-only + + + RASWEBS + Bit status during a word error for the RAS. + 0 + 1 + read-only + + + + + BISTFWR2 + BIST Fail Word Register 0-2 (BISTFWR0-2) + 0x14c + 32 + 0x00000000 + 0xFFFFFFFF + + + DQWEBS + Bit status during a word error for each of the 8 data (DQ) bits. The first 8 bits indicate the status of the first data beat (i.e. the status of the data driven out on DQ[7:0] on the rising edge of DQS). The second 8 bits indicate the status of the second data beat (i.e. the status of the data driven out on DQ[7:0] on the falling edge of DQS), and so on. For each of the 8-bit group, the first bit is for DQ[0], the second bit is for DQ[1], and so on. + 0 + 32 + read-only + + + + + AACR + “Anti-Aging Control Register (AACR)” on page 143 + 0x174 + 32 + 0x00000000 + 0xFFFFFFFF + + + AAOENC + Anti-Aging PAD Output Enable Control: Enables, if set, anti-aging toggling on the pad output enable signal “ctl_oe_n” going into the DATX8s. This will increase power consumption for the anti-aging feature. + 31 + 1 + read-write + + + AAENC + Anti-Aging Enable Control: Enables, if set, the automatic toggling of the data going to the DATX8 when the data channel from the controller/PUB to DATX8 is idle for programmable number of clock cycles. + 30 + 1 + read-write + + + AATR + Anti-Aging Toggle Rate: Defines the number of controller clock (ctl_clk) cycles after which the PUB will toggle the data going to DATX8 if the data channel between the controller/PUB and DATX8 has been idle for this long. +The default value correspond to a toggling count of 4096 ctl_clk cycles. For a ctl_clk running at 533MHz the toggle rate will be approximately 7.68us. +The default value may also be overridden by the macro DWC_AACR_AATR_DFLT. + 0 + 30 + read-write + + + + + GPR0 + General Purpose Register 0-1 (GPR0-1) + 0x178 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR0 + General Purpose Register 0: General purpose register bits. + 0 + 32 + read-write + + + + + GPR1 + General Purpose Register 0-1 (GPR0-1) + 0x17c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR1 + General Purpose Register 1: General purpose register bits. + 0 + 32 + read-write + + + + + 4 + 0x10 + 0,1,2,3 + ZQ[%s] + no description available + 0x180 + + CR0 + Impedance Control Register 0-1 (ZQnCR0-1) + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + ZQPD + ZQ Power Down: Powers down, if set, the PZQ cell. + 31 + 1 + read-write + + + ZCALEN + Impedance Calibration Enable: Enables, if set, the impedance calibration of this ZQ control block when impedance calibration is triggered using either the ZCAL bit of PIR register or the DFI update interface. + 30 + 1 + read-write + + + ZCALBYP + Impedance Calibration Bypass: Bypasses, if set, impedance calibration of this ZQ control block when impedance calibration is already in progress. Impedance calibration can be disabled prior to trigger by using the ZCALEN bit. + 29 + 1 + read-write + + + ZDEN + Impedance Over-ride Enable: When this bit is set, it allows users to directly drive the impedance control using the data programmed in the ZDATA field. Otherwise, the control is generated automatically by the impedance control logic. + 28 + 1 + read-write + + + ZDATA + Impedance Over-Ride Data: Data used to directly drive the impedance control. +ZDATA field mapping for D3F I/Os is as follows: +ZDATA[27:21] is used to select the pull-up on-die termination impedance ZDATA[20:14] is used to select the pull-down on-die termination impedance ZDATA[13:7] is used to select the pull-up output impedance +ZDATA[6:0] is used to select the pull-down output impedance +ZDATA field mapping for D3A/B/R I/Os is as follows: ZDATA[27:20] is reserved and returns zeros on reads +ZDATA[19:15] is used to select the pull-up on-die termination impedance ZDATA[14:10] is used to select the pull-down on-die termination impedance ZDATA[9:5] is used to select the pull-up output impedance +ZDATA[4:0] is used to select the pull-down output impedance +The default value is 0x000014A for I/O type D3C/R and 0x0001830 for I/O type D3F. + 0 + 28 + read-write + + + + + CR1 + Impedance Control Register 0-1 (ZQnCR0-1) + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DFIPU1 + DFI Update Interface 1: Sets this impedance controller to be enabled for calibration when the DFI PHY update interface 1 (channel 1) requests an update. Only valid in shared-AC mode. + 17 + 1 + read-write + + + DFIPU0 + DFI Update Interface 0: Sets this impedance controller to be enabled for calibration when the DFI PHY update interface 0 (channel 0) requests an update. + 16 + 1 + read-write + + + DFICCU + DFI Concurrent Controller Update Interface: Sets this impedance controller to be enabled for calibration when both of the DFI controller update interfaces request an update on the same clock. This provides the ability to enable impedance calibration updates for the Address/Command lane. Only valid in shared-AC mode. + 14 + 1 + read-write + + + DFICU1 + DFI Controller Update Interface 1: Sets this impedance controller to be enabled for calibration when the DFI controller update interface 1 (channel 1) requests an update. Only valid in shared-AC mode. + 13 + 1 + read-write + + + DFICU0 + DFI Controller Update Interface 0: Sets this impedance controller to be enabled for calibration when the DFI controller update interface 0 (channel 0) requests an update. + 12 + 1 + read-write + + + ZPROG + Impedance Divide Ratio: Selects the external resistor divide ratio to be used to set the output impedance and the on-die termination as follows: +ZPROG[7:4] = On-die termination divide select ZPROG[3:0] = Output impedance divide select + 0 + 8 + read-write + + + + + SR0 + Impedance Status Register 0-1 (ZQnSR0-1) + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + ZDONE + Impedance Calibration Done: Indicates that impedance calibration has completed. + 31 + 1 + read-only + + + ZERR + Impedance Calibration Error: If set, indicates that there was an error during impedance calibration. + 30 + 1 + read-only + + + ZCTRL + Impedance Control: Current value of impedance control. ZCTRL field mapping for D3F I/Os is as follows: +ZCTRL[27:21] is used to select the pull-up on-die termination impedance ZCTRL[20:14] is used to select the pull-down on-die termination impedance ZCTRL[13:7] is used to select the pull-up output impedance +ZCTRL[6:0] is used to select the pull-down output impedance +ZCTRL field mapping for D3A/B/R I/Os is as follows: ZCTRL[27:20] is reserved and returns zeros on reads +ZCTRL[19:15] is used to select the pull-up on-die termination impedance ZCTRL[14:10] is used to select the pull-down on-die termination impedance ZCTRL[9:5] is used to select the pull-up output impedance +ZCTRL[4:0] is used to select the pull-down output impedance +Note: The default value is 0x000014A for I/O type D3C/D3R and 0x0001839 for I/O type D3F. + 0 + 28 + read-only + + + + + SR1 + Impedance Status Register 0-1 (ZQnSR0-1) + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + OPU + On-die termination (ODT) pull-up calibration status. Similar status encodings as ZPD. + 6 + 2 + read-only + + + OPD + On-die termination (ODT) pull-down calibration status. Similar status encodings as ZPD. + 4 + 2 + read-only + + + ZPU + Output impedance pull-up calibration status. Similar status encodings as ZPD. + 2 + 2 + read-only + + + ZPD + Output impedance pull-down calibration status. Valid status encodings are: 00 = Completed with no errors +01 = Overflow error 10 = Underflow error +11 = Calibration in progress + 0 + 2 + read-only + + + + + + 9 + 0x40 + 0,1,2,3,4,5,6,7,8 + DX[%s] + no description available + 0x1c0 + + GCR + “DATX8 General Configuration Register (DXnGCR)” on page 148 + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CALBYP + Calibration Bypass: Prevents, if set, period measurement calibration from automatically triggering after PHY initialization. + 31 + 1 + read-write + + + MDLEN + Master Delay Line Enable: Enables, if set, the DATX8 master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or when calibration is manually triggered. These additional measurements are accumulated and filtered as long as this bit remains high. This bit is ANDed with the common DATX8 MDL enable bit. + 30 + 1 + read-write + + + WLRKEN + Write Level Rank Enable: Specifies the ranks that should be write leveled for this byte. Write leveling responses from ranks that are not enabled for write leveling for a particular byte are ignored and write leveling is flagged as done for these ranks. +WLRKEN[0] enables rank 0, [1] enables rank 1, [2] enables rank 2, and [3] enables +rank 3. + 26 + 4 + read-write + + + PLLBYP + PLL Bypass: Puts the byte PLL in bypass mode by driving the PLL bypass pin. This bit is not self-clearing and a '0' must be written to de-assert the bypass. This bit is ORed with the global BYP configuration bit (see Table 3-10 on page 91). + 19 + 1 + read-write + + + GSHIFT + Gear Shift: Enables, if set, rapid locking mode on the byte PLL. This bit is ORed with the global GSHIFT configuration bit (see Table 3-10 on page 91). + 18 + 1 + read-write + + + PLLPD + PLL Power Down: Puts the byte PLL in power down mode by driving the PLL power down pin. This bit is not self-clearing and a '0' must be written to de-assert the power-down. This bit is ORed with the global PLLPD configuration bit (see +Table 3-10 on page 91). + 17 + 1 + read-write + + + PLLRST + PLL Rest: Resets the byte PLL by driving the PLL reset pin. This bit is not self- clearing and a '0' must be written to de-assert the reset. This bit is ORed with the global PLLRST configuration bit (see Table 3-10 on page 91). + 16 + 1 + read-write + + + DXOEO + Data Byte Output Enable Override: Specifies whether the output I/O output enable for the byte lane should be set to a fixed value. Valid values are: +00 = No override. Output enable is controlled by DFI transactions 01 = output enable is asserted (I/O is forced to output mode). +10 = Output enable is de-asserted (I/O is forced to input mode) 11 = Reserved + 14 + 2 + read-write + + + RTTOAL + RTT On Additive Latency: Indicates when the ODT control of DQ/DQS SSTL I/Os is set to the value in DQODT/DQSODT during read cycles. Valid values are: +0 = ODT control is set to DQSODT/DQODT almost two cycles before read data preamble +1 = ODT control is set to DQSODT/DQODT almost one cycle before read data preamble + 13 + 1 + read-write + + + RTTOH + RTT Output Hold: Indicates the number of clock cycles (from 0 to 3) after the read data postamble for which ODT control should remain set to DQSODT for DQS or DQODT for DQ/DM before disabling it (setting it to ‘0’) when using dynamic ODT control. ODT is disabled almost RTTOH clock cycles after the read postamble. + 11 + 2 + read-write + + + DQRTT + DQ Dynamic RTT Control: If set, the on die termination (ODT) control of the DQ/DM SSTL I/O is dynamically generated to enable the ODT during read operation and disabled otherwise. By setting this bit to '0' the dynamic ODT feature is disabled. To control ODT statically this bit must be set to '0' and DXnGCR0[2] (DQODT) is used to enable ODT (when set to '1') or disable ODT(when set to '0'). + 10 + 1 + read-write + + + DQSRTT + DQS Dynamic RTT Control: If set, the on die termination (ODT) control of the DQS/DQS# SSTL I/O is dynamically generated to enable the ODT during read operation and disabled otherwise. By setting this bit to '0' the dynamic ODT feature is disabled. To control ODT statically this bit must be set to '0' and DXnGCR0[1] (DQSODT) is used to enable ODT (when set to '1') or disable ODT(when set to '0'). + 9 + 1 + read-write + + + DSEN + Write DQS Enable: Controls whether the write DQS going to the SDRAM is enabled (toggling) or disabled (static value) and whether the DQS is inverted. DQS# is always the inversion of DQS. These values are valid only when DQS/DQS# output enable is on, otherwise the DQS/DQS# is tristated. Valid settings are: +00 = Reserved +01 = DQS toggling with normal polarity (This should be the default setting) 10 = Reserved +11 = Reserved + 7 + 2 + read-write + + + DQSRPD + DQSR Power Down: Powers down, if set, the PDQSR cell. This bit is ORed with the common PDR configuration bit (see “DATX8 Common Configuration Register (DXCCR)” on page 99) + 6 + 1 + read-write + + + DXPDR + Data Power Down Receiver: Powers down, when set, the input receiver on I/O for DQ, DM, and DQS/DQS# pins of the byte. This bit is ORed with the common PDR configuration bit (see “DATX8 Common Configuration Register (DXCCR)” on page 99). + 5 + 1 + read-write + + + DXPDD1 + Data Power Down Driver: Powers down, when set, the output driver on I/O for DQ, DM, and DQS/DQS# pins of the byte. This bit is ORed with the common PDD configuration bit (see “DATX8 Common Configuration Register (DXCCR)” on page 99). + 4 + 1 + read-write + + + DXIOM + Data I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DQ, DM, and DQS/DQS# pins of the byte. This bit is ORed with the IOM configuration bit of the individual DATX8(see “DATX8 Common Configuration Register (DXCCR)” on page 99). + 3 + 1 + read-write + + + DQODT + Data On-Die Termination: Enables, when set, the on-die termination on the I/O for DQ and DM pins of the byte. This bit is ORed with the common DATX8 ODT configuration bit (see “DATX8 Common Configuration Register (DXCCR)” on page 99). +Note: This bit is only valid when DXnGCR0[10] is '0'. + 2 + 1 + read-write + + + DQSODT + DQS On-Die Termination: Enables, when set, the on-die termination on the I/O for DQS/DQS# pin of the byte. This bit is ORed with the common DATX8 ODT configuration bit (see “DATX8 Common Configuration Register (DXCCR)” on page 99). +Note: This bit is only valid when DXnGCR0[9] is '0'. + 1 + 1 + read-write + + + DXEN + Data Byte Enable: Enables, if set, the data byte. Setting this bit to '0' disables the byte, i.e. the byte is not used in PHY initialization or training and is ignored during SDRAM read/write operations. + 0 + 1 + read-write + + + + + GSR0 + DATX8 General Status Registers 0-2 (DXnGSR0-2) + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + WLDQ + Write Leveling DQ Status: Captures the write leveling DQ status from the DRAM during software write leveling. + 28 + 1 + read-only + + + QSGERR + DQS Gate Training Error: Indicates, if set, that there is an error in DQS gate training. One bit for each of the up to 4 ranks. + 24 + 4 + read-only + + + GDQSPRD + Read DQS gating Period: Returns the DDR clock period measured by the read DQS gating LCDL during calibration. This value is PVT compensated. + 16 + 8 + read-only + + + DPLOCK + DATX8 PLL Lock: Indicates, if set, that the DATX8 PLL has locked. This is a direct status of the DATX8 PLL lock pin. + 15 + 1 + read-only + + + WLPRD + Write Leveling Period: Returns the DDR clock period measured by the write leveling LCDL during calibration. The measured period is used to generate the control of the write leveling pipeline which is a function of the write-leveling delay and the clock period. This value is PVT compensated. + 7 + 8 + read-only + + + WLERR + Write Leveling Error: Indicates, if set, that there is a write leveling error in the DATX8. + 6 + 1 + read-only + + + WLDONE + Write Leveling Done: Indicates, if set, that the DATX8 has completed write leveling. + 5 + 1 + read-only + + + WLCAL + Write Leveling Calibration: Indicates, if set, that the DATX8 has finished doing period measurement calibration for the write leveling slave delay line. + 4 + 1 + read-only + + + GDQSCAL + Read DQS gating Calibration: Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS gating LCDL. + 3 + 1 + read-only + + + RDQSNCAL + Read DQS# Calibration (Type B/B1 PHY Only): Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS# LCDL. + 2 + 1 + read-only + + + RDQSCAL + Read DQS Calibration: Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS LCDL. + 1 + 1 + read-only + + + WDQCAL + Write DQ Calibration: Indicates, if set, that the DATX8 has finished doing period measurement calibration for the write DQ LCDL. + 0 + 1 + read-only + + + + + GSR1 + DATX8 General Status Registers 0-2 (DXnGSR0-2) + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DLTCODE + Delay Line Test Code: Returns the code measured by the PHY control block that corresponds to the period of the DATX8 delay line digital test output. + 1 + 24 + read-only + + + DLTDONE + Delay Line Test Done: Indicates, if set, that the PHY control block has finished doing period measurement of the DATX8 delay line digital test output. + 0 + 1 + read-only + + + + + BDLR0 + DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + DQ4WBD + DQ4 Write Bit Delay: Delay select for the BDL on DQ4 write path. + 24 + 6 + read-write + + + DQ3WBD + DQ3 Write Bit Delay: Delay select for the BDL on DQ3 write path + 18 + 6 + read-write + + + DQ2WBD + DQ2 Write Bit Delay: Delay select for the BDL on DQ2 write path. + 12 + 6 + read-write + + + DQ1WBD + DQ1 Write Bit Delay: Delay select for the BDL on DQ1 write path. + 6 + 6 + read-write + + + DQ0WBD + DQ0 Write Bit Delay: Delay select for the BDL on DQ0 write path. + 0 + 6 + read-write + + + + + BDLR1 + DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + DSWBD + DQS Write Bit Delay: Delay select for the BDL on DQS write path + 24 + 6 + read-write + + + DMWBD + DM Write Bit Delay: Delay select for the BDL on DM write path. + 18 + 6 + read-write + + + DQ7WBD + DQ7 Write Bit Delay: Delay select for the BDL on DQ7 write path. + 12 + 6 + read-write + + + DQ6WBD + DQ6 Write Bit Delay: Delay select for the BDL on DQ6 write path. + 6 + 6 + read-write + + + DQ5WBD + DQ5 Write Bit Delay: Delay select for the BDL on DQ5 write path. + 0 + 6 + read-write + + + + + BDLR2 + DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + DSNRBD + DQSN Read Bit Delay (Type B/B1 PHY Only): Delay select for the BDL on DQSN read path + 18 + 6 + read-write + + + DSRBD + DQS Read Bit Delay: Delay select for the BDL on DQS read path + 12 + 6 + read-write + + + DQOEBD + DQ Output Enable Bit Delay: Delay select for the BDL on DQ/DM output enable path. + 6 + 6 + read-write + + + DSOEBD + DQS Output Enable Bit Delay: Delay select for the BDL on DQS output enable path + 0 + 6 + read-write + + + + + BDLR3 + DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + DQ4RBD + DQ4 Read Bit Delay: Delay select for the BDL on DQ4 read path. + 24 + 6 + read-write + + + DQ3RBD + DQ3 Read Bit Delay: Delay select for the BDL on DQ3 read path + 18 + 6 + read-write + + + DQ2RBD + DQ2 Read Bit Delay: Delay select for the BDL on DQ2 read path. + 12 + 6 + read-write + + + DQ1RBD + DQ1 Read Bit Delay: Delay select for the BDL on DQ1 read path. + 6 + 6 + read-write + + + DQ0RBD + DQ0 Read Bit Delay: Delay select for the BDL on DQ0 read path. + 0 + 6 + read-write + + + + + BDLR4 + DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + DMRBD + DM Read Bit Delay: Delay select for the BDL on DM read path. + 18 + 6 + read-write + + + DQ7RBD + DQ7 Read Bit Delay: Delay select for the BDL on DQ7 read path. + 12 + 6 + read-write + + + DQ6RBD + DQ6 Read Bit Delay: Delay select for the BDL on DQ6 read path. + 6 + 6 + read-write + + + DQ5RBD + DQ5 Read Bit Delay: Delay select for the BDL on DQ5 read path. + 0 + 6 + read-write + + + + + LCDLR0 + DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + R3WLD + Rank 3 Write Leveling Delay: Rank 3 delay select for the write leveling (WL) LCDL + 24 + 8 + read-write + + + R2WLD + Rank 2 Write Leveling Delay: Rank 2 delay select for the write leveling (WL) LCDL + 16 + 8 + read-write + + + R1WLD + Rank 1 Write Leveling Delay: Rank 1 delay select for the write leveling (WL) LCDL + 8 + 8 + read-write + + + R0WLD + Rank 0 Write Leveling Delay: Rank 0 delay select for the write leveling (WL) LCDL + 0 + 8 + read-write + + + + + LCDLR1 + DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + RDQSND + Read DQSN Delay (Type B/B1 PHY Only): Delay select for the read DQSN (RDQS) LCDL + 16 + 8 + read-write + + + RDQSD + Read DQS Delay: Delay select for the read DQS (RDQS) LCDL + 8 + 8 + read-write + + + WDQD + Write Data Delay: Delay select for the write data (WDQ) LCDL + 0 + 8 + read-write + + + + + LCDLR2 + DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + R3DQSGD + Rank 3 Read DQS Gating Delay: Rank 3 delay select for the read DQS gating (DQSG) LCDL + 24 + 8 + read-write + + + R2DQSGD + Rank 2 Read DQS Gating Delay: Rank 2 delay select for the read DQS gating (DQSG) LCDL + 16 + 8 + read-write + + + R1DQSGD + Rank 1 Read DQS Gating Delay: Rank 1 delay select for the read DQS gating (DQSG) LCDL + 8 + 8 + read-write + + + R0DQSGD + Rank 0 Read DQS Gating Delay: Rank 0 delay select for the read DQS gating (DQSG) LCDL + 0 + 8 + read-write + + + + + MDLR + “DATX8 Master Delay Line Register (DXnMDLR)” on page 157 + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + MDLD + MDL Delay: Delay select for the LCDL for the Master Delay Line. + 16 + 8 + read-write + + + TPRD + Target Period: Target period measured by the master delay line calibration for VT drift compensation. This is the current measured value of the period and is continuously updated if the MDL is enabled to do so. + 8 + 8 + read-write + + + IPRD + Initial Period: Initial period measured by the master delay line calibration for VT drift compensation. This value is used as the denominator when calculating the ratios of updates during VT compensation. + 0 + 8 + read-write + + + + + GTR + “DATX8 General Timing Register (DXnGTR)” on page 159 + 0x30 + 32 + 0x00000000 + 0x000FFFFF + + + R3WLSL + No description available + 18 + 2 + read-write + + + R2WLSL + No description available + 16 + 2 + read-write + + + R1WLSL + No description available + 14 + 2 + read-write + + + R0WLSL + Rank n Write Leveling System Latency: This is used to adjust the write latency after write leveling. Power-up default is 01 (i.e. no extra clock cycles required). The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register. Every two bits of this register control the latency of each of the (up to) four ranks. R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on. Valid values: +00 = Write latency = WL - 1 01 = Write latency = WL +10 = Write latency = WL + 1 11 = Reserved + 12 + 2 + read-write + + + R3DGSL + No description available + 9 + 3 + read-write + + + R2DGSL + No description available + 6 + 3 + read-write + + + R1DGSL + No description available + 3 + 3 + read-write + + + R0DGSL + Rank n DQS Gating System Latency: This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles. +This is used to compensate for board delays and other system delays. Power-up default is 000 (i.e. no extra clock cycles required). The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register. Every three bits of this register control the latency of each of the (up to) four ranks. R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on. Valid values are 0 to 7: + 0 + 3 + read-write + + + + + GSR2 + “DATX8 General Status Register 2 (DXnGSR2)” on page 152 + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + ESTAT + Error Status: If an error occurred for this lane as indicated by RDERR, WDERR, REERR or WEERR the error status code can provide additional information regard when the error occurred during the algorithm execution. + 8 + 4 + read-write + + + WEWN + Write Data Eye Training Warning: Indicates, if set, that the DATX8 has encountered a warning during execution of the write data eye training. + 7 + 1 + read-write + + + WEERR + Write Data Eye Training Error: Indicates, if set, that the DATX8 has encountered an error during execution of the write data eye training. + 6 + 1 + read-write + + + REWN + Read Data Eye Training Warning: Indicates, if set, that the DATX8 has encountered a warning during execution of the read data eye training. + 5 + 1 + read-write + + + REERR + Read Data Eye Training Error: Indicates, if set, that the DATX8 has encountered an error during execution of the read data eye training. + 4 + 1 + read-write + + + WDWN + Write Bit Deskew Warning: Indicates, if set, that the DATX8 has encountered a warning during execution of the write bit deskew training. + 3 + 1 + read-write + + + WDERR + Write Bit Deskew Error: Indicates, if set, that the DATX8 has encountered an error during execution of the write bit deskew training. + 2 + 1 + read-write + + + RDWN + Read Bit Deskew Warning: Indicates, if set, that the DATX8 has encountered a warning during execution of the read bit deskew training. + 1 + 1 + read-write + + + RDERR + Read Bit Deskew Error: Indicates, if set, that the DATX8 has encountered an error during execution of the read bit deskew training. + 0 + 1 + read-write + + + + + + + + TSNS + TSNS + TSNS + 0xf4154000 + + 0x0 + 0x3c + registers + + + + T + Temperature + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Signed number of temperature in 256 x celsius degree + 0 + 32 + read-only + + + + + TMAX + Maximum Temperature + 0x4 + 32 + 0xFF800000 + 0xFFFFFFFF + + + T + maximum temperature ever found + 0 + 32 + read-only + + + + + TMIN + Minimum Temperature + 0x8 + 32 + 0x007FFFFF + 0xFFFFFFFF + + + T + minimum temperature ever found + 0 + 32 + read-only + + + + + AGE + Sample age + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + AGE + age of T register in 24MHz clock cycles + 0 + 32 + read-only + + + + + STATUS + Status + 0x10 + 32 + 0x00000000 + 0x80000001 + + + VALID + indicate value in T is valid or not +0: not valid +1:valid + 31 + 1 + read-only + + + TRIGGER + Software trigger for sensing in trigger mode, trigger will be ignored if in sensing or other mode + 0 + 1 + write-only + + + + + CONFIG + Configuration + 0x14 + 32 + 0x00600300 + 0xC3FF0713 + + + IRQ_EN + Enable interrupt + 31 + 1 + read-write + + + RST_EN + Enable reset + 30 + 1 + read-write + + + COMPARE_MIN_EN + Enable compare for minimum temperature + 25 + 1 + read-write + + + COMPARE_MAX_EN + Enable compare for maximum temperature + 24 + 1 + read-write + + + SPEED + cycles of a progressive step in 24M clock, valid from 24-255, default 96 +24: 24 cycle for a step +25: 25 cycle for a step +26: 26 cycle for a step +... +255: 255 cycle for a step + 16 + 8 + read-write + + + AVERAGE + Average time, default in 3 +0: measure and return +1: twice and average +2: 4 times and average +. . . +7: 128 times and average + 8 + 3 + read-write + + + CONTINUOUS + continuous mode that keep sampling temperature peridically +0: trigger mode +1: continuous mode + 4 + 1 + read-write + + + ASYNC + Acynchronous mode, this mode can work without clock, only available function ios compare to certain ADC value +0: active mode +1: Async mode + 1 + 1 + read-write + + + ENABLE + Enable temperature +0: disable, temperature sensor is shut down +1: enable. Temperature sensor enabled + 0 + 1 + read-write + + + + + VALIDITY + Sample validity + 0x18 + 32 + 0x016E3600 + 0xFFFFFFFF + + + VALIDITY + time for temperature values to expire in 24M clock cycles + 0 + 32 + read-write + + + + + FLAG + Temperature flag + 0x1c + 32 + 0x00000000 + 0x00330001 + + + RECORD_MIN_CLR + Clear minimum recorder of temerature, write 1 to clear + 21 + 1 + read-write + + + RECORD_MAX_CLR + Clear maximum recorder of temerature, write 1 to clear + 20 + 1 + read-write + + + UNDER_TEMP + Clear under temperature status, write 1 to clear + 17 + 1 + read-write + + + OVER_TEMP + Clear over temperature status, write 1 to clear + 16 + 1 + read-write + + + IRQ + IRQ flag, write 1 to clear + 0 + 1 + read-write + + + + + UPPER_LIM_IRQ + Maximum temperature to interrupt + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Maximum temperature for compare + 0 + 32 + read-write + + + + + LOWER_LIM_IRQ + Minimum temperature to interrupt + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Minimum temperature for compare + 0 + 32 + read-write + + + + + UPPER_LIM_RST + Maximum temperature to reset + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Maximum temperature for compare + 0 + 32 + read-write + + + + + LOWER_LIM_RST + Minimum temperature to reset + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Minimum temperature for compare + 0 + 32 + read-write + + + + + ASYNC + Configuration in asynchronous mode + 0x30 + 32 + 0x00000000 + 0x010107FF + + + ASYNC_TYPE + Compare hotter than or colder than in asynchoronous mode +0: hotter than +1: colder than + 24 + 1 + read-write + + + POLARITY + Polarity of internal comparator + 16 + 1 + read-write + + + VALUE + Value of async mode to compare + 0 + 11 + read-write + + + + + ADVAN + Advance configuration + 0x38 + 32 + 0x00000000 + 0x03010003 + + + ASYNC_IRQ + interrupt status of asynchronous mode + 25 + 1 + read-only + + + ACTIVE_IRQ + interrupt status of active mode + 24 + 1 + read-only + + + SAMPLING + temperature sampling is working + 16 + 1 + read-only + + + NEG_ONLY + use negative compare polarity only + 1 + 1 + read-write + + + POS_ONLY + use positive compare polarity only + 0 + 1 + read-write + + + + + + + BACC + BACC + BACC + 0xf4200000 + + 0x0 + 0x10 + registers + + + + CONFIG + Access timing for access + 0x0 + 32 + 0x00000000 + 0x3000FFFF + + + FAST_WRITE + Use fast write +0: Write normally +1: boost write + 29 + 1 + read-write + + + FAST_READ + Use fast read +0: Read normally +1: boost read + 28 + 1 + read-write + + + TIMING + Time in APB clock cycles, for battery timing penerate + 0 + 16 + read-write + + + + + PRE_TIME + Timing gap before rising edge + 0x8 + 32 + 0x00000000 + 0x000FFFFF + + + PRE_RATIO + Ratio of guard band before rising edge +0: 0 +1: 1/32768 of low level width +2: 1/16384 of low level width +14: 1/4 of low level width +15: 1/2 of low level width + 16 + 4 + read-write + + + PRE_OFFSET + guard band before rising edge +this value will be added to ratio number + 0 + 16 + read-write + + + + + POST_TIME + Timing gap after rising edge + 0xc + 32 + 0x00000000 + 0x000FFFFF + + + POST_RATIO + Ratio of guard band after rising edge +0: 0 +1: 1/32768 of high level width +2: 1/16384 of high level width +14: 1/4 of high level width +15: 1/2 of high level width + 16 + 4 + read-write + + + POST_OFFSET + guard band after rising edge +this value will be added to ratio number + 0 + 16 + read-write + + + + + + + BPOR + BPOR + BPOR + 0xf4204000 + + 0x0 + 0x4 + registers + + + + POR_CONFIG + Power on reset config + 0x0 + 32 + 0x00000000 + 0x00000001 + + + RETENTION + retention battery domain setting +0: battery reset on reset pin reset happen +1: battery domain retention when reset pin reset happen + 0 + 1 + read-write + + + + + + + BCFG + BCFG + TRIM + 0xf4208000 + + 0x0 + 0x14 + registers + + + + VBG_CFG + Bandgap config + 0x0 + 32 + 0x00000000 + 0x811F1F1F + + + VBG_TRIMMED + Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: bandgap is not trimmed +1: bandgap is trimmed + 31 + 1 + read-write + + + POWER_SAVE + Bandgap works in power save mode +0: not in power save mode +1: bandgap work in power save mode + 24 + 1 + read-write + + + VBG_1P0 + Bandgap 1.0V output trim + 16 + 5 + read-write + + + VBG_P65 + Bandgap 0.65V output trim + 8 + 5 + read-write + + + VBG_P50 + Bandgap 0.50V output trim + 0 + 5 + read-write + + + + + IRC32K_CFG + On-chip 32k oscillator config + 0x8 + 32 + 0x00000000 + 0x80C001FF + + + IRC_TRIMMED + IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: irc is not trimmed +1: irc is trimmed + 31 + 1 + read-write + + + CAPEX7_TRIM + IRC32K bit 7 + 23 + 1 + read-write + + + CAPEX6_TRIM + IRC32K bit 6 + 22 + 1 + read-write + + + CAP_TRIM + capacitor trim bits + 0 + 9 + read-write + + + + + XTAL32K_CFG + XTAL 32K config + 0xc + 32 + 0x00000000 + 0x00001313 + + + HYST_EN + crystal 32k hysteres enable + 12 + 1 + read-write + + + GMSEL + crystal 32k gm selection + 8 + 2 + read-write + + + CFG + crystal 32k config + 4 + 1 + read-write + + + AMP + crystal 32k amplifier + 0 + 2 + read-write + + + + + CLK_CFG + Clock config + 0x10 + 32 + 0x00000000 + 0x10010010 + + + XTAL_SEL + crystal selected + 28 + 1 + read-only + + + KEEP_IRC + force irc32k run + 16 + 1 + read-write + + + FORCE_XTAL + force switch to crystal + 4 + 1 + read-write + + + + + + + BUTN + BUTN + BUTN + 0xf420c000 + + 0x0 + 0xc + registers + + + + BTN_STATUS + Button status + 0x0 + 32 + 0x00000000 + 0x77770FFF + + + XWCLICK + wake button click status when power button held, write 1 to clear flag +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 28 + 3 + read-write + + + WCLICK + wake button click status, write 1 to clear flag +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 24 + 3 + read-write + + + XPCLICK + power button click status when wake button held, write 1 to clear flag +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 20 + 3 + read-write + + + PCLICK + power button click status, write 1 to clear flag +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 16 + 3 + read-write + + + DBTN + Dual button press status, write 1 to clear flag +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 8 + 4 + read-write + + + WBTN + Wake button press status, write 1 to clear flag +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 4 + 4 + read-write + + + PBTN + Power button press status, write 1 to clear flag +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 0 + 4 + read-write + + + + + BTN_IRQ_MASK + Button interrupt mask + 0x4 + 32 + 0x00000000 + 0x77770FFF + + + XWCLICK + wake button click status when power button held interrupt enable +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 28 + 3 + read-write + + + WCLICK + wake button click interrupt enable +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 24 + 3 + read-write + + + XPCLICK + power button click status when wake button held interrupt enable +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 20 + 3 + read-write + + + PCLICK + power button click interrupt enable +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 16 + 3 + read-write + + + DBTN + Dual button press interrupt enable +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 8 + 4 + read-write + + + WBTN + Wake button press interrupt enable +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 4 + 4 + read-write + + + PBTN + Power button press interrupt enable +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 0 + 4 + read-write + + + + + LED_INTENSE + Debounce setting + 0x8 + 32 + 0x00000000 + 0x000F000F + + + RLED + Rbutton brightness 0 + 16 + 4 + read-write + + + PLED + Pbutton brightness 0 + 0 + 4 + read-write + + + + + + + BGPR + BGPR + BGPR + 0xf4218000 + + 0x0 + 0x20 + registers + + + + 8 + 0x4 + 0,1,2,3,4,5,6,7 + GPR[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + Generic control + 0 + 32 + read-write + + + + + + + RTCSHW + RTCSHW + RTC + 0xf421c000 + + 0x0 + 0x28 + registers + + + + SECOND + Second counter + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SECOND + second counter + 0 + 32 + read-write + + + + + SUBSEC + Sub-second counter + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SUBSEC + sub second counter + 0 + 32 + read-only + + + + + SEC_SNAP + Second counter snap shot + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SEC_SNAP + second snap shot, write to take snap shot + 0 + 32 + read-write + + + + + SUB_SNAP + Sub-second counter snap shot + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + SUB_SNAP + sub second snap shot, write to take snap shot + 0 + 32 + read-write + + + + + ALARM0 + RTC alarm0 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + ALARM + Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC + 0 + 32 + read-write + + + + + ALARM0_INC + Alarm0 incremental + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + INCREASE + adder when ARLAM0 happen, helps to create periodical alarm + 0 + 32 + read-write + + + + + ALARM1 + RTC alarm1 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + ALARM + Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC + 0 + 32 + read-write + + + + + ALARM1_INC + Alarm1 incremental + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + INCREASE + adder when ARLAM0 happen, helps to create periodical alarm + 0 + 32 + read-write + + + + + ALARM_FLAG + RTC alarm flag + 0x20 + 32 + 0x00000000 + 0x00000003 + + + ALARM1 + alarm1 happen + 1 + 1 + read-write + + + ALARM0 + alarm0 happen + 0 + 1 + read-write + + + + + ALARM_EN + RTC alarm enable + 0x24 + 32 + 0x00000000 + 0x00000003 + + + ENABLE1 + alarm1 mask +0: alarm1 disabled +1: alarm1 enabled + 1 + 1 + read-write + + + ENABLE0 + alarm0 mask +0: alarm0 disabled +1: alarm0 enabled + 0 + 1 + read-write + + + + + + + RTC + RTC + RTC + 0xf4244000 + + + BSEC + BSEC + BSEC + 0xf4240000 + + 0x0 + 0x14 + registers + + + + SECURE_STATE + Secure state + 0x0 + 32 + 0x00000000 + 0x0003000F + + + ALLOW_NSC + Non-secure state allow +0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter non-secure state + 17 + 1 + read-only + + + ALLOW_SEC + Secure state allow +0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter secure state + 16 + 1 + read-only + + + BATT_FAIL + BATT secure state one hot indicator +0: secure state is not in fail state +1: secure state is in fail state + 3 + 1 + read-write + + + BATT_NSC + BATT secure state one hot indicator +0: secure state is not in non-secure state +1: secure state is in non-secure state + 2 + 1 + read-write + + + BATT_SEC + BATT secure state one hot indicator +0: secure state is not in secure state +1: secure state is in secure state + 1 + 1 + read-write + + + BATT_INS + BATT secure state one hot indicator +0: secure state is not in inspect state +1: secure state is in inspect state + 0 + 1 + read-write + + + + + SECURE_STATE_CONFIG + secure state configuration + 0x4 + 32 + 0x00000000 + 0x00000009 + + + LOCK + Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset +0: not locked, register can be modified +1: register locked, write access to the register is ignored + 3 + 1 + read-write + + + ALLOW_RESTART + allow secure state restart from fail state +0: restart is not allowed, only hardware reset can recover secure state +1: software is allowed to switch to inspect state from fail state + 0 + 1 + read-write + + + + + VIOLATION_CONFIG + Security violation config + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 0 + 15 + read-write + + + + + ESCALATE_CONFIG + Escalate behavior on security event + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 0 + 15 + read-write + + + + + EVENT + Event and escalate status + 0x10 + 32 + 0x00000000 + 0xFFFF0003 + + + EVENT + local event statue, each bit represents one security event + 16 + 16 + read-only + + + BATT_ESC_NSC + BATT is escalating non-secure event + 1 + 1 + read-only + + + BATT_ESC_SEC + BATT is escalting ssecure event + 0 + 1 + read-only + + + + + + + BKEY + BKEY + BKEY + 0xf4248000 + + 0x0 + 0x4c + registers + + + + 2 + 0x20 + 0,1 + KEY[%s] + no description available + 0x0 + + 8 + 0x4 + 0,1,2,3,4,5,6,7 + DATA[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + + 2 + 0x4 + KEY0,KEY1 + ECC[%s] + no description available + 0x40 + 32 + 0x00000000 + 0xC000FFFF + + + WLOCK + write lock to key0 +0: write enable +1: write ignored + 31 + 1 + read-write + + + RLOCK + read lock to key0 +0: key read enable +1: key always read as 0 + 30 + 1 + read-write + + + ECC + Parity check bits for key0 + 0 + 16 + read-write + + + + + SELECT + Key selection + 0x48 + 32 + 0x00000000 + 0x00000001 + + + SELECT + select key, key0 treated as secure key, in non-scure mode, only key1 can be selected +0: select key0 in secure mode, key1 in non-secure mode +1: select key1 in secure or nonsecure mode + 0 + 1 + read-write + + + + + + + BMON + BMON + BMON + 0xf424c000 + + 0x0 + 0x20 + registers + + + + 2 + 0x10 + glitch0,clock0 + MONITOR[%s] + no description available + 0x0 + + CONTROL + Glitch and clock monitor control + 0x0 + 32 + 0x00000000 + 0x00000011 + + + ACTIVE + select glitch works in active mode or passve mode. +0: passive mode, depends on power glitch destroy DFF value +1: active mode, check glitch by DFF chain + 4 + 1 + read-write + + + ENABLE + enable glitch detector +0: detector disabled +1: detector enabled + 0 + 1 + read-write + + + + + STATUS + Glitch and clock monitor status + 0x4 + 32 + 0x00000000 + 0x00000001 + + + FLAG + flag for glitch detected, write 1 to clear this flag +0: glitch not detected +1: glitch detected + 0 + 1 + read-write + + + + + + + + TAMP + TAMP + TAMP + 0xf4250000 + + 0x0 + 0x88 + registers + + + + 4 + 0x10 + tamp0,tamp1,tamp2,tamp3 + TAMP[%s] + no description available + 0x0 + + CONTROL + Tamper n control + 0x0 + 32 + 0x00000000 + 0x801F03F7 + + + LOCK + lock tamper setting +0: tamper setting can be changed +1: tamper setting will last to next battery domain power cycle + 31 + 1 + read-write + + + BYPASS + bypass tamper violation filter +0: filter applied +1: filter not used + 20 + 1 + read-write + + + FILTER + filter length +0: 1 cycle +1: 2 cycle +15: 65526 cycle + 16 + 4 + read-write + + + VALUE + pin value for passive tamper + 8 + 2 + read-write + + + SPEED + tamper speed selection, (2^SPEED) changes per second +0: 1 shift per second +1: 2 shifts per second +. . . +15: 32768 shifts per second + 4 + 4 + read-write + + + RECOVER + tamper will recover itself if tamper LFSR goes wrong +0: tamper will not recover +1: tamper will recover + 2 + 1 + read-write + + + ACTIVE + select active or passive tamper +0: passive tamper +1: active tamper + 1 + 1 + read-write + + + ENABLE + enable tamper +0: tamper disableed +1: tamper enabled + 0 + 1 + read-write + + + + + POLY + Tamper n Polynomial of LFSR + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + POLY + tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" + 0 + 32 + read-write + + + + + LFSR + Tamper n LFSR shift register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + LFSR + LFSR for active tamper, write only register, always read 0 + 0 + 32 + write-only + + + + + + TAMP_FLAG + Tamper flag + 0x80 + 32 + 0x00000000 + 0x00000FFF + + + FLAG + tamper flag, each bit represents one tamper pin, write 1 to clear the flag +Note, clear can only be cleared when tamper disappeared + 0 + 12 + read-write + + + + + IRQ_EN + Tamper interrupt enable + 0x84 + 32 + 0x00000000 + 0x80000FFF + + + LOCK + lock bit for IRQ enable +0: enable bits can be changed +1: enable bits hold until next battery domain power cycle + 31 + 1 + read-write + + + IRQ_EN + interrupt enable, each bit represents one tamper pin +0: interrupt disabled +1: interrupt enabled + 0 + 12 + read-write + + + + + + + MONO + MONO + MONO + 0xf4254000 + + 0x0 + 0x8 + registers + + + + MONOL + Low part of monotonic counter + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + low part of monotonica counter, write to this counter will cause counter increase by 1 + 0 + 32 + read-write + + + + + MONOH + High part of monotonic counter + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + EPOCH + Fuse value for high part of monotonica + 16 + 16 + read-write + + + COUNTER + high part of monotonica counter, write to this counter will cause counter increase by 1 if low part overflow + 0 + 16 + read-write + + + + + + + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/SConscript b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/SConscript new file mode 100644 index 00000000000..5717c3e6317 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/SConscript @@ -0,0 +1,25 @@ +import os +import sys +Import('rtconfig') +from building import * + +#get current directory +cwd = GetCurrentDir() + +# Update include path +path = [ cwd, cwd + '/boot' ] + +# The set of source files associated with this SConscript file. +src = Split(''' + system.c + hpm_l1c_drv.c + hpm_sysctl_drv.c + hpm_clock_drv.c + hpm_otp_drv.c + boot/hpm_bootheader.c +''') + + +group = DefineGroup('SoC', src, depend = [''], CPPPATH = path) + +Return ('group') diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/boot/hpm_bootheader.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/boot/hpm_bootheader.c new file mode 100644 index 00000000000..57cdf5aa2e6 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/boot/hpm_bootheader.c @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_bootheader.h" + +/* symbol exported from startup.S */ +extern uint32_t _start[]; + +/* following symbols exported from linker script */ +extern uint32_t __app_load_addr__[]; +extern uint32_t __app_offset__[]; +extern uint32_t __fw_size__[]; + +#define FW_SIZE (32768) +__attribute__ ((section(".fw_info_table"))) const fw_info_table_t fw_info = { + (uint32_t)__app_offset__, /* offset */ + (uint32_t)__fw_size__, /* size */ + 0, /* flags */ + 0, /* reserved0 */ + (uint32_t) &__app_load_addr__, /* load_addr */ + 0, /* reserved1 */ + (uint32_t) _start, /* entry_point */ + 0, /* reserved2 */ + {0}, /* hash */ + {0}, /* iv */ +}; + +__attribute__ ((section(".boot_header"))) const boot_header_t header = { + HPM_BOOTHEADER_TAG, /* tag */ + 0x10, /* version*/ + sizeof(header) + sizeof(fw_info), + 0, /* flags */ + 0, /* sw_version */ + 0, /* fuse_version */ + 1, /* fw_count */ + 0, + 0, /* sig_block_offset */ +}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/boot/hpm_bootheader.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/boot/hpm_bootheader.h new file mode 100644 index 00000000000..d7f22fd8240 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/boot/hpm_bootheader.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_BOOT_HEADER_H +#define HPM_BOOT_HEADER_H + +#include "hpm_common.h" + +#define HPM_BOOTHEADER_TAG (0xBFU) +#define HPM_BOOTHEADER_MAX_FW_COUNT (2U) + +#ifndef HPM_BOOT_FW_COUNT +#define HPM_BOOT_FW_COUNT 1 +#endif + +#if HPM_BOOT_FW_COUNT < 1 +#error "HPM_BOOT_FW_COUNT can't be less than 1" +#endif + +typedef struct { + uint32_t offset; /* 0x0: offset to boot_header start */ + uint32_t size; /* 0x4: size in bytes */ + uint32_t flags; /* 0x8: [3:0] fw type: */ + /* 0 - executable */ + /* 1 - cmd container */ + /* [11:8] - hash type */ + /* 0 - none */ + /* 1 - sha256 */ + /* 2 - sm3 */ + uint32_t reserved0; /* 0xC */ + uint32_t load_addr; /* 0x10: load address */ + uint32_t reserved1; /* 0x14 */ + uint32_t entry_point; /* 0x18: application entry */ + uint32_t reserved2; /* 0x1C */ + uint8_t hash[64]; /* 0x20: hash value */ + uint8_t iv[32]; /* 0x60: initial vector */ +} fw_info_table_t; + +typedef struct { + uint8_t tag; /* 0x0: must be '0xbf' */ + uint8_t version; /* 0x1: header version */ + uint16_t length; /* 0x2: header length, max 8KB */ + uint32_t flags; /* 0x4: [3:0] SRK set */ + /* [7:4] SRK index */ + /* [15:8] SRK_REVOKE_MASK */ + /* [19:16] Signature Type */ + /* 1: ECDSA */ + /* 2: SM2 */ + uint16_t sw_version; /* 0x8: software version */ + uint8_t fuse_version; /* 0xA: fuse version */ + uint8_t fw_count; /* 0xB: number of fw */ + uint16_t dc_block_offset; /* 0xC: device config block offset*/ + uint16_t sig_block_offset; /* 0xE: signature block offset */ + /* + * fw_info_table_t fw_info[HPM_BOOT_FW_COUNT]; [> 0x10: fw table <] + * uint32_t dc_info[]; [> <] + */ +} boot_header_t; + +#endif /* HPM_BOOT_HEADER_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_batt_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_batt_iomux.h new file mode 100644 index 00000000000..aac63f47982 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_batt_iomux.h @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_BATT_IOMUX_H +#define HPM_BATT_IOMUX_H + +/* BIOC_PZ00_FUNC_CTL function mux definitions */ +#define IOC_PZ00_FUNC_CTL_GPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ00_FUNC_CTL_GPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ00_FUNC_CTL_TAMP_PZ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ00_FUNC_CTL_TAMP_PZ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ00_FUNC_CTL_SOC_PZ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ00_FUNC_CTL_SOC_PZ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ01_FUNC_CTL function mux definitions */ +#define IOC_PZ01_FUNC_CTL_GPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ01_FUNC_CTL_GPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ01_FUNC_CTL_TAMP_PZ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ01_FUNC_CTL_TAMP_PZ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ01_FUNC_CTL_SOC_PZ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ01_FUNC_CTL_SOC_PZ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ02_FUNC_CTL function mux definitions */ +#define IOC_PZ02_FUNC_CTL_GPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ02_FUNC_CTL_GPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ02_FUNC_CTL_TAMP_PZ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ02_FUNC_CTL_TAMP_PZ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ02_FUNC_CTL_SOC_PZ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ02_FUNC_CTL_SOC_PZ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ03_FUNC_CTL function mux definitions */ +#define IOC_PZ03_FUNC_CTL_GPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ03_FUNC_CTL_GPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ03_FUNC_CTL_TAMP_PZ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ03_FUNC_CTL_TAMP_PZ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ03_FUNC_CTL_SOC_PZ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ03_FUNC_CTL_SOC_PZ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ04_FUNC_CTL function mux definitions */ +#define IOC_PZ04_FUNC_CTL_GPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ04_FUNC_CTL_GPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ04_FUNC_CTL_TAMP_PZ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ04_FUNC_CTL_TAMP_PZ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ04_FUNC_CTL_SOC_PZ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ04_FUNC_CTL_SOC_PZ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ05_FUNC_CTL function mux definitions */ +#define IOC_PZ05_FUNC_CTL_GPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ05_FUNC_CTL_GPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ05_FUNC_CTL_TAMP_PZ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ05_FUNC_CTL_TAMP_PZ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ05_FUNC_CTL_SOC_PZ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ05_FUNC_CTL_SOC_PZ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ06_FUNC_CTL function mux definitions */ +#define IOC_PZ06_FUNC_CTL_GPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ06_FUNC_CTL_GPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ06_FUNC_CTL_TAMP_PZ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ06_FUNC_CTL_TAMP_PZ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ06_FUNC_CTL_SOC_PZ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ06_FUNC_CTL_SOC_PZ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ07_FUNC_CTL function mux definitions */ +#define IOC_PZ07_FUNC_CTL_GPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ07_FUNC_CTL_GPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ07_FUNC_CTL_TAMP_PZ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ07_FUNC_CTL_TAMP_PZ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ07_FUNC_CTL_SOC_PZ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ07_FUNC_CTL_SOC_PZ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ08_FUNC_CTL function mux definitions */ +#define IOC_PZ08_FUNC_CTL_GPIO_Z_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ08_FUNC_CTL_GPIO_Z_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ08_FUNC_CTL_TAMP_PZ_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ08_FUNC_CTL_TAMP_PZ_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ08_FUNC_CTL_SOC_PZ_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ08_FUNC_CTL_SOC_PZ_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ09_FUNC_CTL function mux definitions */ +#define IOC_PZ09_FUNC_CTL_GPIO_Z_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ09_FUNC_CTL_GPIO_Z_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ09_FUNC_CTL_TAMP_PZ_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ09_FUNC_CTL_TAMP_PZ_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ09_FUNC_CTL_SOC_PZ_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ09_FUNC_CTL_SOC_PZ_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ10_FUNC_CTL function mux definitions */ +#define IOC_PZ10_FUNC_CTL_GPIO_Z_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ10_FUNC_CTL_GPIO_Z_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ10_FUNC_CTL_TAMP_PZ_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ10_FUNC_CTL_TAMP_PZ_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ10_FUNC_CTL_SOC_PZ_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ10_FUNC_CTL_SOC_PZ_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ11_FUNC_CTL function mux definitions */ +#define IOC_PZ11_FUNC_CTL_GPIO_Z_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ11_FUNC_CTL_GPIO_Z_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ11_FUNC_CTL_TAMP_PZ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ11_FUNC_CTL_TAMP_PZ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ11_FUNC_CTL_SOC_PZ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ11_FUNC_CTL_SOC_PZ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ12_FUNC_CTL function mux definitions */ +#define IOC_PZ12_FUNC_CTL_GPIO_Z_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ12_FUNC_CTL_GPIO_Z_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ12_FUNC_CTL_TAMP_PZ_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ12_FUNC_CTL_TAMP_PZ_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ12_FUNC_CTL_SOC_PZ_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ12_FUNC_CTL_SOC_PZ_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ13_FUNC_CTL function mux definitions */ +#define IOC_PZ13_FUNC_CTL_GPIO_Z_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ13_FUNC_CTL_GPIO_Z_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ13_FUNC_CTL_TAMP_PZ_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ13_FUNC_CTL_TAMP_PZ_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ13_FUNC_CTL_SOC_PZ_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ13_FUNC_CTL_SOC_PZ_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ14_FUNC_CTL function mux definitions */ +#define IOC_PZ14_FUNC_CTL_GPIO_Z_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ14_FUNC_CTL_GPIO_Z_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ14_FUNC_CTL_TAMP_PZ_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ14_FUNC_CTL_TAMP_PZ_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ14_FUNC_CTL_SOC_PZ_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ14_FUNC_CTL_SOC_PZ_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* BIOC_PZ15_FUNC_CTL function mux definitions */ +#define IOC_PZ15_FUNC_CTL_GPIO_Z_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ15_FUNC_CTL_GPIO_Z_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ15_FUNC_CTL_TAMP_PZ_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ15_FUNC_CTL_TAMP_PZ_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ15_FUNC_CTL_SOC_PZ_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ +#define BIOC_PZ15_FUNC_CTL_SOC_PZ_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + + +#endif /* HPM_BATT_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_bcfg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_bcfg_drv.h new file mode 100644 index 00000000000..e477b5b543c --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_bcfg_drv.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_BCFG_DRV_H +#define HPM_BCFG_DRV_H + +#include "hpm_common.h" +#include "hpm_bcfg_regs.h" + +/** + * + * @brief BCFG driver APIs + * @defgroup bcfg_interface BCFG driver APIs + * @ingroup io_interfaces + * @{ + */ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief enable power save mode + * + * @param[in] ptr base address + */ +static inline void bcfg_vbg_enable_power_save_mode(BCFG_Type *ptr) +{ + ptr->VBG_CFG |= BCFG_VBG_CFG_POWER_SAVE_MASK; +} + +/** + * @brief disable power save mode + * + * @param[in] ptr base address + */ +static inline void bcfg_vbg_disable_power_save_mode(BCFG_Type *ptr) +{ + ptr->VBG_CFG &= ~BCFG_VBG_CFG_POWER_SAVE_MASK; +} + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_BCFG_DRV_H */ + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_bcfg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_bcfg_regs.h new file mode 100644 index 00000000000..059283c4cee --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_bcfg_regs.h @@ -0,0 +1,193 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_BCFG_H +#define HPM_BCFG_H + +typedef struct { + __RW uint32_t VBG_CFG; /* 0x0: Bandgap config */ + __R uint8_t RESERVED0[4]; /* 0x4 - 0x7: Reserved */ + __RW uint32_t IRC32K_CFG; /* 0x8: On-chip 32k oscillator config */ + __RW uint32_t XTAL32K_CFG; /* 0xC: XTAL 32K config */ + __RW uint32_t CLK_CFG; /* 0x10: Clock config */ +} BCFG_Type; + + +/* Bitfield definition for register: VBG_CFG */ +/* + * VBG_TRIMMED (RW) + * + * Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value + * 0: bandgap is not trimmed + * 1: bandgap is trimmed + */ +#define BCFG_VBG_CFG_VBG_TRIMMED_MASK (0x80000000UL) +#define BCFG_VBG_CFG_VBG_TRIMMED_SHIFT (31U) +#define BCFG_VBG_CFG_VBG_TRIMMED_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_TRIMMED_SHIFT) & BCFG_VBG_CFG_VBG_TRIMMED_MASK) +#define BCFG_VBG_CFG_VBG_TRIMMED_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_TRIMMED_MASK) >> BCFG_VBG_CFG_VBG_TRIMMED_SHIFT) + +/* + * POWER_SAVE (RW) + * + * Bandgap works in power save mode + * 0: not in power save mode + * 1: bandgap work in power save mode + */ +#define BCFG_VBG_CFG_POWER_SAVE_MASK (0x1000000UL) +#define BCFG_VBG_CFG_POWER_SAVE_SHIFT (24U) +#define BCFG_VBG_CFG_POWER_SAVE_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_POWER_SAVE_SHIFT) & BCFG_VBG_CFG_POWER_SAVE_MASK) +#define BCFG_VBG_CFG_POWER_SAVE_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_POWER_SAVE_MASK) >> BCFG_VBG_CFG_POWER_SAVE_SHIFT) + +/* + * VBG_1P0 (RW) + * + * Bandgap 1.0V output trim + */ +#define BCFG_VBG_CFG_VBG_1P0_MASK (0x1F0000UL) +#define BCFG_VBG_CFG_VBG_1P0_SHIFT (16U) +#define BCFG_VBG_CFG_VBG_1P0_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_1P0_SHIFT) & BCFG_VBG_CFG_VBG_1P0_MASK) +#define BCFG_VBG_CFG_VBG_1P0_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_1P0_MASK) >> BCFG_VBG_CFG_VBG_1P0_SHIFT) + +/* + * VBG_P65 (RW) + * + * Bandgap 0.65V output trim + */ +#define BCFG_VBG_CFG_VBG_P65_MASK (0x1F00U) +#define BCFG_VBG_CFG_VBG_P65_SHIFT (8U) +#define BCFG_VBG_CFG_VBG_P65_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_P65_SHIFT) & BCFG_VBG_CFG_VBG_P65_MASK) +#define BCFG_VBG_CFG_VBG_P65_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_P65_MASK) >> BCFG_VBG_CFG_VBG_P65_SHIFT) + +/* + * VBG_P50 (RW) + * + * Bandgap 0.50V output trim + */ +#define BCFG_VBG_CFG_VBG_P50_MASK (0x1FU) +#define BCFG_VBG_CFG_VBG_P50_SHIFT (0U) +#define BCFG_VBG_CFG_VBG_P50_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_P50_SHIFT) & BCFG_VBG_CFG_VBG_P50_MASK) +#define BCFG_VBG_CFG_VBG_P50_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_P50_MASK) >> BCFG_VBG_CFG_VBG_P50_SHIFT) + +/* Bitfield definition for register: IRC32K_CFG */ +/* + * IRC_TRIMMED (RW) + * + * IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value + * 0: irc is not trimmed + * 1: irc is trimmed + */ +#define BCFG_IRC32K_CFG_IRC_TRIMMED_MASK (0x80000000UL) +#define BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT (31U) +#define BCFG_IRC32K_CFG_IRC_TRIMMED_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT) & BCFG_IRC32K_CFG_IRC_TRIMMED_MASK) +#define BCFG_IRC32K_CFG_IRC_TRIMMED_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_IRC_TRIMMED_MASK) >> BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT) + +/* + * CAPEX7_TRIM (RW) + * + * IRC32K bit 7 + */ +#define BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK (0x800000UL) +#define BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT (23U) +#define BCFG_IRC32K_CFG_CAPEX7_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK) +#define BCFG_IRC32K_CFG_CAPEX7_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK) >> BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT) + +/* + * CAPEX6_TRIM (RW) + * + * IRC32K bit 6 + */ +#define BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK (0x400000UL) +#define BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT (22U) +#define BCFG_IRC32K_CFG_CAPEX6_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK) +#define BCFG_IRC32K_CFG_CAPEX6_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK) >> BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT) + +/* + * CAP_TRIM (RW) + * + * capacitor trim bits + */ +#define BCFG_IRC32K_CFG_CAP_TRIM_MASK (0x1FFU) +#define BCFG_IRC32K_CFG_CAP_TRIM_SHIFT (0U) +#define BCFG_IRC32K_CFG_CAP_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAP_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAP_TRIM_MASK) +#define BCFG_IRC32K_CFG_CAP_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAP_TRIM_MASK) >> BCFG_IRC32K_CFG_CAP_TRIM_SHIFT) + +/* Bitfield definition for register: XTAL32K_CFG */ +/* + * HYST_EN (RW) + * + * crystal 32k hysteres enable + */ +#define BCFG_XTAL32K_CFG_HYST_EN_MASK (0x1000U) +#define BCFG_XTAL32K_CFG_HYST_EN_SHIFT (12U) +#define BCFG_XTAL32K_CFG_HYST_EN_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_HYST_EN_SHIFT) & BCFG_XTAL32K_CFG_HYST_EN_MASK) +#define BCFG_XTAL32K_CFG_HYST_EN_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_HYST_EN_MASK) >> BCFG_XTAL32K_CFG_HYST_EN_SHIFT) + +/* + * GMSEL (RW) + * + * crystal 32k gm selection + */ +#define BCFG_XTAL32K_CFG_GMSEL_MASK (0x300U) +#define BCFG_XTAL32K_CFG_GMSEL_SHIFT (8U) +#define BCFG_XTAL32K_CFG_GMSEL_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_GMSEL_SHIFT) & BCFG_XTAL32K_CFG_GMSEL_MASK) +#define BCFG_XTAL32K_CFG_GMSEL_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_GMSEL_MASK) >> BCFG_XTAL32K_CFG_GMSEL_SHIFT) + +/* + * CFG (RW) + * + * crystal 32k config + */ +#define BCFG_XTAL32K_CFG_CFG_MASK (0x10U) +#define BCFG_XTAL32K_CFG_CFG_SHIFT (4U) +#define BCFG_XTAL32K_CFG_CFG_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_CFG_SHIFT) & BCFG_XTAL32K_CFG_CFG_MASK) +#define BCFG_XTAL32K_CFG_CFG_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_CFG_MASK) >> BCFG_XTAL32K_CFG_CFG_SHIFT) + +/* + * AMP (RW) + * + * crystal 32k amplifier + */ +#define BCFG_XTAL32K_CFG_AMP_MASK (0x3U) +#define BCFG_XTAL32K_CFG_AMP_SHIFT (0U) +#define BCFG_XTAL32K_CFG_AMP_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_AMP_SHIFT) & BCFG_XTAL32K_CFG_AMP_MASK) +#define BCFG_XTAL32K_CFG_AMP_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_AMP_MASK) >> BCFG_XTAL32K_CFG_AMP_SHIFT) + +/* Bitfield definition for register: CLK_CFG */ +/* + * XTAL_SEL (RO) + * + * crystal selected + */ +#define BCFG_CLK_CFG_XTAL_SEL_MASK (0x10000000UL) +#define BCFG_CLK_CFG_XTAL_SEL_SHIFT (28U) +#define BCFG_CLK_CFG_XTAL_SEL_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_XTAL_SEL_MASK) >> BCFG_CLK_CFG_XTAL_SEL_SHIFT) + +/* + * KEEP_IRC (RW) + * + * force irc32k run + */ +#define BCFG_CLK_CFG_KEEP_IRC_MASK (0x10000UL) +#define BCFG_CLK_CFG_KEEP_IRC_SHIFT (16U) +#define BCFG_CLK_CFG_KEEP_IRC_SET(x) (((uint32_t)(x) << BCFG_CLK_CFG_KEEP_IRC_SHIFT) & BCFG_CLK_CFG_KEEP_IRC_MASK) +#define BCFG_CLK_CFG_KEEP_IRC_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_KEEP_IRC_MASK) >> BCFG_CLK_CFG_KEEP_IRC_SHIFT) + +/* + * FORCE_XTAL (RW) + * + * force switch to crystal + */ +#define BCFG_CLK_CFG_FORCE_XTAL_MASK (0x10U) +#define BCFG_CLK_CFG_FORCE_XTAL_SHIFT (4U) +#define BCFG_CLK_CFG_FORCE_XTAL_SET(x) (((uint32_t)(x) << BCFG_CLK_CFG_FORCE_XTAL_SHIFT) & BCFG_CLK_CFG_FORCE_XTAL_MASK) +#define BCFG_CLK_CFG_FORCE_XTAL_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_FORCE_XTAL_MASK) >> BCFG_CLK_CFG_FORCE_XTAL_SHIFT) + + + + +#endif /* HPM_BCFG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_bgpr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_bgpr_regs.h new file mode 100644 index 00000000000..9d81aab19cf --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_bgpr_regs.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_BGPR_H +#define HPM_BGPR_H + +typedef struct { + __RW uint32_t GPR[8]; /* 0x0 - 0x1C: Generic control */ +} BGPR_Type; + + +/* Bitfield definition for register array: GPR */ +/* + * DATA (RW) + * + * Generic control + */ +#define BGPR_GPR_DATA_MASK (0xFFFFFFFFUL) +#define BGPR_GPR_DATA_SHIFT (0U) +#define BGPR_GPR_DATA_SET(x) (((uint32_t)(x) << BGPR_GPR_DATA_SHIFT) & BGPR_GPR_DATA_MASK) +#define BGPR_GPR_DATA_GET(x) (((uint32_t)(x) & BGPR_GPR_DATA_MASK) >> BGPR_GPR_DATA_SHIFT) + + + +/* GPR register group index macro definition */ +#define BGPR_GPR_0 (0UL) +#define BGPR_GPR_1 (1UL) +#define BGPR_GPR_2 (2UL) +#define BGPR_GPR_3 (3UL) +#define BGPR_GPR_4 (4UL) +#define BGPR_GPR_5 (5UL) +#define BGPR_GPR_6 (6UL) +#define BGPR_GPR_7 (7UL) + + +#endif /* HPM_BGPR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_bpor_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_bpor_drv.h new file mode 100644 index 00000000000..b20cd5c3687 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_bpor_drv.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_BPOR_DRV_H +#define HPM_BPOR_DRV_H + +#include "hpm_common.h" +#include "hpm_bpor_regs.h" + +/** + * + * @brief BPOR driver APIs + * @defgroup bpor_interface BPOR driver APIs + * @ingroup io_interfaces + * @{ + * + */ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable register value retention when power down occurs + * + * @param[in] ptr BPOR base address + */ +static inline void bpor_enable_reg_value_retention(BPOR_Type *ptr) +{ + ptr->POR_CONFIG |= BPOR_POR_CONFIG_RETENTION_MASK; +} + +/** + * @brief Disable register value retention when power down occurs + * + * @param[in] ptr BPOR base address + */ +static inline void bpor_disable_reg_value_retention(BPOR_Type *ptr) +{ + ptr->POR_CONFIG &= ~BPOR_POR_CONFIG_RETENTION_MASK; +} + + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_BPOR_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_bpor_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_bpor_regs.h new file mode 100644 index 00000000000..8d0c023fdb9 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_bpor_regs.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_BPOR_H +#define HPM_BPOR_H + +typedef struct { + __RW uint32_t POR_CONFIG; /* 0x0: Power on reset config */ +} BPOR_Type; + + +/* Bitfield definition for register: POR_CONFIG */ +/* + * RETENTION (RW) + * + * retention battery domain setting + * 0: battery reset on reset pin reset happen + * 1: battery domain retention when reset pin reset happen + */ +#define BPOR_POR_CONFIG_RETENTION_MASK (0x1U) +#define BPOR_POR_CONFIG_RETENTION_SHIFT (0U) +#define BPOR_POR_CONFIG_RETENTION_SET(x) (((uint32_t)(x) << BPOR_POR_CONFIG_RETENTION_SHIFT) & BPOR_POR_CONFIG_RETENTION_MASK) +#define BPOR_POR_CONFIG_RETENTION_GET(x) (((uint32_t)(x) & BPOR_POR_CONFIG_RETENTION_MASK) >> BPOR_POR_CONFIG_RETENTION_SHIFT) + + + + +#endif /* HPM_BPOR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_clock_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_clock_drv.c new file mode 100644 index 00000000000..9fa5ebc8473 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_clock_drv.c @@ -0,0 +1,545 @@ +/* + * Copyright (c) 2023-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_clock_drv.h" +#include "hpm_sysctl_drv.h" +#include "hpm_soc.h" +#include "hpm_common.h" +#include "hpm_pllctlv2_drv.h" +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/* Clock preset values */ +#define FREQ_PRESET1_OSC0_CLK0 (24000000UL) +#define FREQ_PRESET1_PLL0_CLK0 (500000000UL) +#define FREQ_PRESET1_PLL1_CLK0 (800000000UL) +#define FREQ_PRESET1_PLL1_CLK1 (666666666UL) +#define FREQ_PRESET1_PLL2_CLK0 (600000000UL) +#define FREQ_PRESET1_PLL2_CLK1 (500000000UL) +#define FREQ_PRESET1_PLL3_CLK0 (516096000UL) +#define FREQ_PRESET1_PLL4_CLK0 (594000000UL) +#define FREQ_32KHz (32768UL) +#define ADC_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->ADCCLK) +#define I2S_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->I2SCLK) +#define WDG_INSTANCE_NUM (2U) +#define BUS_FREQ_MAX (200000000UL) +#define FREQ_1MHz (1000000UL) + +/* Clock On/Off definitions */ +#define CLOCK_ON (true) +#define CLOCK_OFF (false) + + +/*********************************************************************************************************************** + * Prototypes + **********************************************************************************************************************/ +/** + * @brief Get Clock frequency for IP in common group + */ +static uint32_t get_frequency_for_ip_in_common_group(clock_node_t node); + +/** + * @brief Get Clock frequency for ADC + */ +static uint32_t get_frequency_for_adc(uint32_t instance); + +/** + * @brief Get Clock frequency for I2S + */ +static uint32_t get_frequency_for_i2s(uint32_t instance); + +/** + * @brief Get Clock frequency for EWDG + */ +static uint32_t get_frequency_for_ewdg(uint32_t instance); + +/** + * @brief Get Clock frequency for PEWDG + */ +static uint32_t get_frequency_for_pewdg(void); + +/** + * @brief Turn on/off the IP clock + */ +static void switch_ip_clock(clock_name_t clock_name, bool on); + + +/*********************************************************************************************************************** + * Variables + **********************************************************************************************************************/ +static const clock_node_t s_adc_clk_mux_node[] = { + clock_node_ana0, + clock_node_axis, +}; + +static EWDG_Type *const s_wdgs[] = { HPM_EWDG0, HPM_EWDG1}; + +uint32_t hpm_core_clock; + +/*********************************************************************************************************************** + * Codes + **********************************************************************************************************************/ +uint32_t clock_get_frequency(clock_name_t clock_name) +{ + uint32_t clk_freq = 0UL; + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + switch (clk_src_type) { + case CLK_SRC_GROUP_COMMON: + clk_freq = get_frequency_for_ip_in_common_group((clock_node_t) node_or_instance); + break; + case CLK_SRC_GROUP_ADC: + clk_freq = get_frequency_for_adc(node_or_instance); + break; + case CLK_SRC_GROUP_I2S: + clk_freq = get_frequency_for_i2s(node_or_instance); + break; + case CLK_SRC_GROUP_EWDG: + clk_freq = get_frequency_for_ewdg(node_or_instance); + break; + case CLK_SRC_GROUP_PEWDG: + clk_freq = get_frequency_for_pewdg(); + break; + case CLK_SRC_GROUP_PMIC: + clk_freq = FREQ_PRESET1_OSC0_CLK0; + break; + case CLK_SRC_GROUP_AXI_SOC: + clk_freq = get_frequency_for_ip_in_common_group(clock_node_axis); + break; + case CLK_SRC_GROUP_AXI_FAST: + clk_freq = get_frequency_for_ip_in_common_group(clock_node_axif); + break; + case CLK_SRC_GROUP_AXI_VIDEO: + clk_freq = get_frequency_for_ip_in_common_group(clock_node_axiv); + break; + case CLK_SRC_GROUP_SRC: + clk_freq = get_frequency_for_source((clock_source_t) node_or_instance); + break; + default: + clk_freq = 0UL; + break; + } + return clk_freq; +} + +uint32_t get_frequency_for_source(clock_source_t source) +{ + uint32_t clk_freq = 0UL; + switch (source) { + case clock_source_osc0_clk0: + clk_freq = FREQ_PRESET1_OSC0_CLK0; + break; + case clock_source_pll0_clk0: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 0U); + break; + case clock_source_pll1_clk0: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 0U); + break; + case clock_source_pll1_clk1: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 1U); + break; + case clock_source_pll2_clk0: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 2U, 0U); + break; + case clock_source_pll2_clk1: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 2U, 1U); + break; + case clock_source_pll3_clk0: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 3U, 0U); + break; + case clock_source_pll4_clk0: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 4U, 0U); + break; + default: + clk_freq = 0UL; + break; + } + + return clk_freq; +} + +static uint32_t get_frequency_for_ip_in_common_group(clock_node_t node) +{ + uint32_t clk_freq = 0UL; + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(node); + + if (node_or_instance < clock_node_end) { + uint32_t clk_node = (uint32_t) node_or_instance; + + uint32_t clk_div = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[clk_node]); + clock_source_t clk_mux = (clock_source_t) SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[clk_node]); + clk_freq = get_frequency_for_source(clk_mux) / clk_div; + } + return clk_freq; +} + +static uint32_t get_frequency_for_ahb(void) +{ + return get_frequency_for_ip_in_common_group(clock_node_axis); +} + +static uint32_t get_frequency_for_adc(uint32_t instance) +{ + uint32_t clk_freq = 0UL; + bool is_mux_valid = false; + clock_node_t node = clock_node_end; + if (instance < ADC_INSTANCE_NUM) { + uint32_t mux_in_reg = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[instance]); + if (mux_in_reg < ARRAY_SIZE(s_adc_clk_mux_node)) { + node = s_adc_clk_mux_node[mux_in_reg]; + is_mux_valid = true; + } + } + + if (is_mux_valid) { + if (node == clock_node_axis) { + clk_freq = get_frequency_for_ahb(); + } else { + node += instance; + clk_freq = get_frequency_for_ip_in_common_group(node); + } + } + return clk_freq; +} + +static uint32_t get_frequency_for_i2s(uint32_t instance) +{ + uint32_t clk_freq = 0UL; + clock_node_t node; + uint32_t mux_in_reg; + + if (instance < I2S_INSTANCE_NUM) { + mux_in_reg = SYSCTL_I2SCLK_MUX_GET(HPM_SYSCTL->I2SCLK[instance]); + if (mux_in_reg == 0) { + node = clock_node_aud0 + instance; + } else if (instance == 0) { + node = clock_node_aud1; + } else { + node = clock_node_aud0; + } + clk_freq = get_frequency_for_ip_in_common_group(node); + } + + return clk_freq; +} + +static uint32_t get_frequency_for_ewdg(uint32_t instance) +{ + uint32_t freq_in_hz; + if (EWDG_CTRL0_CLK_SEL_GET(s_wdgs[instance]->CTRL0) == 0) { + freq_in_hz = get_frequency_for_ahb(); + } else { + freq_in_hz = FREQ_32KHz; + } + + return freq_in_hz; +} + +static uint32_t get_frequency_for_pewdg(void) +{ + uint32_t freq_in_hz; + if (EWDG_CTRL0_CLK_SEL_GET(HPM_PEWDG->CTRL0) == 0) { + freq_in_hz = FREQ_PRESET1_OSC0_CLK0; + } else { + freq_in_hz = FREQ_32KHz; + } + + return freq_in_hz; +} + +clk_src_t clock_get_source(clock_name_t clock_name) +{ + uint8_t clk_src_group = CLK_SRC_GROUP_INVALID; + uint8_t clk_src_index = 0xFU; + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + switch (clk_src_type) { + case CLK_SRC_GROUP_COMMON: + clk_src_group = CLK_SRC_GROUP_COMMON; + clk_src_index = SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[node_or_instance]); + break; + case CLK_SRC_GROUP_ADC: + if (node_or_instance < ADC_INSTANCE_NUM) { + clk_src_group = CLK_SRC_GROUP_ADC; + clk_src_index = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[node_or_instance]); + } + break; + case CLK_SRC_GROUP_I2S: + if (node_or_instance < I2S_INSTANCE_NUM) { + clk_src_group = CLK_SRC_GROUP_I2S; + clk_src_index = SYSCTL_I2SCLK_MUX_GET(HPM_SYSCTL->I2SCLK[node_or_instance]); + } + break; + case CLK_SRC_GROUP_EWDG: + if (node_or_instance < WDG_INSTANCE_NUM) { + clk_src_group = CLK_SRC_GROUP_EWDG; + clk_src_index = EWDG_CTRL0_CLK_SEL_GET(s_wdgs[node_or_instance]->CTRL0); + } + break; + case CLK_SRC_GROUP_PEWDG: + clk_src_group = CLK_SRC_GROUP_PEWDG; + clk_src_index = EWDG_CTRL0_CLK_SEL_GET(HPM_PEWDG->CTRL0); + break; + case CLK_SRC_GROUP_PMIC: + clk_src_group = CLK_SRC_GROUP_COMMON; + clk_src_index = clock_source_osc0_clk0; + break; + case CLK_SRC_GROUP_AXI_SOC: + clk_src_group = CLK_SRC_GROUP_COMMON; + clk_src_index = SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_axis]); + break; + case CLK_SRC_GROUP_AXI_VIDEO: + clk_src_group = CLK_SRC_GROUP_COMMON; + clk_src_index = SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_axiv]); + break; + case CLK_SRC_GROUP_AXI_FAST: + clk_src_group = CLK_SRC_GROUP_COMMON; + clk_src_index = SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_axif]); + break; + case CLK_SRC_GROUP_SRC: + clk_src_index = (clk_src_t) node_or_instance; + break; + + default: + clk_src_group = CLK_SRC_GROUP_INVALID; + break; + } + + clk_src_t clk_src; + if (clk_src_group != CLK_SRC_GROUP_INVALID) { + clk_src = MAKE_CLK_SRC(clk_src_group, clk_src_index); + } else { + clk_src = clk_src_invalid; + } + + return clk_src; +} + +uint32_t clock_get_divider(clock_name_t clock_name) +{ + uint32_t clk_divider = CLOCK_DIV_INVALID; + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + switch (clk_src_type) { + case CLK_SRC_GROUP_COMMON: + clk_divider = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[node_or_instance]); + break; + case CLK_SRC_GROUP_EWDG: + if (node_or_instance < WDG_INSTANCE_NUM) { + clk_divider = 1UL; + } + break; + case CLK_SRC_GROUP_PEWDG: + clk_divider = 1UL; + break; + case CLK_SRC_GROUP_PMIC: + clk_divider = 1UL; + break; + case CLK_SRC_GROUP_AXI_SOC: + clk_divider = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_axis]); + break; + case CLK_SRC_GROUP_AXI_VIDEO: + clk_divider = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_axiv]); + break; + case CLK_SRC_GROUP_AXI_FAST: + clk_divider = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_axif]); + break; + default: + clk_divider = CLOCK_DIV_INVALID; + break; + } + return clk_divider; +} + +hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src) +{ + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + + if ((clk_src_type != CLK_SRC_GROUP_ADC) || (node_or_instance >= ADC_INSTANCE_NUM)) { + return status_clk_invalid; + } + + if ((src < clk_adc_src_ana0) || (src > clk_adc_src_ahb0)) { + return status_clk_src_invalid; + } + + uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); + HPM_SYSCTL->ADCCLK[node_or_instance] = + (HPM_SYSCTL->ADCCLK[node_or_instance] & ~SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(clk_src_index); + + return status_success; +} + +hpm_stat_t clock_set_i2s_source(clock_name_t clock_name, clk_src_t src) +{ + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + + if ((clk_src_type != CLK_SRC_GROUP_I2S) || (node_or_instance >= I2S_INSTANCE_NUM)) { + return status_clk_invalid; + } + + if ((src < clk_i2s_src_aud0) || (src > clk_i2s_src_audx)) { + return status_clk_src_invalid; + } + + uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); + HPM_SYSCTL->I2SCLK[node_or_instance] = + (HPM_SYSCTL->I2SCLK[node_or_instance] & ~SYSCTL_I2SCLK_MUX_MASK) | SYSCTL_I2SCLK_MUX_SET(clk_src_index); + + return status_success; +} + +hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint32_t div) +{ + hpm_stat_t status = status_success; + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + switch (clk_src_type) { + case CLK_SRC_GROUP_COMMON: + if ((div < 1U) || (div > 256U)) { + status = status_clk_div_invalid; + } else { + clock_source_t clk_src = GET_CLOCK_SOURCE_FROM_CLK_SRC(src); + sysctl_config_clock(HPM_SYSCTL, (clock_node_t) node_or_instance, clk_src, div); + } + break; + case CLK_SRC_GROUP_ADC: + case CLK_SRC_GROUP_I2S: + case CLK_SRC_GROUP_EWDG: + case CLK_SRC_GROUP_PEWDG: + case CLK_SRC_GROUP_SRC: + status = status_clk_operation_unsupported; + break; + case CLK_SRC_GROUP_PMIC: + status = status_clk_fixed; + break; + case CLK_SRC_GROUP_AXI_FAST: + status = status_clk_shared_axif; + break; + case CLK_SRC_GROUP_AXI_VIDEO: + status = status_clk_shared_axiv; + break; + case CLK_SRC_GROUP_AXI_SOC: + status = status_clk_shared_axis; + break; + default: + status = status_clk_src_invalid; + break; + } + + return status; +} + +static void switch_ip_clock(clock_name_t clock_name, bool on) +{ + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + if (resource < sysctl_resource_end) { + uint32_t mode = on ? 1UL : 2UL; + HPM_SYSCTL->RESOURCE[resource] = + (HPM_SYSCTL->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | SYSCTL_RESOURCE_MODE_SET(mode); + } +} + +void clock_enable(clock_name_t clock_name) +{ + switch_ip_clock(clock_name, CLOCK_ON); +} + +void clock_disable(clock_name_t clock_name) +{ + switch_ip_clock(clock_name, CLOCK_OFF); +} + +void clock_add_to_group(clock_name_t clock_name, uint32_t group) +{ + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + if (resource < sysctl_resource_end) { + sysctl_enable_group_resource(HPM_SYSCTL, group, resource, true); + } +} + +void clock_remove_from_group(clock_name_t clock_name, uint32_t group) +{ + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + if (resource < sysctl_resource_end) { + sysctl_enable_group_resource(HPM_SYSCTL, group, resource, false); + } +} + +bool clock_check_in_group(clock_name_t clock_name, uint32_t group) +{ + bool added = false; + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + if (resource < sysctl_resource_end) { + added = sysctl_check_group_resource_enable(HPM_SYSCTL, group, resource); + } + + return added; +} + +void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu) +{ + if (cpu < 1U) { + HPM_SYSCTL->AFFILIATE[cpu].SET = (1UL << group); + } +} + +void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu) +{ + if (cpu < 1U) { + HPM_SYSCTL->AFFILIATE[cpu].CLEAR = (1UL << group); + } +} + +static uint64_t get_core_mcycle(void) +{ + uint64_t result; + uint32_t resultl_first = read_csr(CSR_MCYCLE); + uint32_t resulth = read_csr(CSR_MCYCLEH); + uint32_t resultl_second = read_csr(CSR_MCYCLE); + if (resultl_first < resultl_second) { + result = ((uint64_t)resulth << 32) | resultl_first; /* if MCYCLE didn't roll over, return the value directly */ + } else { + resulth = read_csr(CSR_MCYCLEH); + result = ((uint64_t)resulth << 32) | resultl_second; /* if MCYCLE rolled over, need to get the MCYCLEH again */ + } + return result; + } + +void clock_cpu_delay_us(uint32_t us) +{ + uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; + uint32_t mcounteren = read_csr(CSR_MCOUNTEREN); + write_csr(CSR_MCOUNTEREN, mcounteren | 1); /* Enable MCYCLE */ + uint64_t expected_ticks = get_core_mcycle() + ticks_per_us * us; + while (get_core_mcycle() < expected_ticks) { + } + write_csr(CSR_MCOUNTEREN, mcounteren); /* Restore MCOUNTEREN */ +} + +void clock_cpu_delay_ms(uint32_t ms) +{ + uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; + uint32_t mcounteren = read_csr(CSR_MCOUNTEREN); + write_csr(CSR_MCOUNTEREN, mcounteren | 1); /* Enable MCYCLE */ + uint64_t expected_ticks = get_core_mcycle() + (uint64_t)ticks_per_us * 1000UL * ms; + while (get_core_mcycle() < expected_ticks) { + } + write_csr(CSR_MCOUNTEREN, mcounteren); /* Restore MCOUNTEREN */ +} + +void clock_update_core_clock(void) +{ + clock_name_t cpu_clk_name = clock_cpu0; + hpm_core_clock = clock_get_frequency(cpu_clk_name); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_clock_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_clock_drv.h new file mode 100644 index 00000000000..7a23fff4bab --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_clock_drv.h @@ -0,0 +1,400 @@ +/* + * Copyright (c) 2022-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_CLOCK_DRV_H +#define HPM_CLOCK_DRV_H + +#include "hpm_common.h" +#include "hpm_sysctl_drv.h" +#include "hpm_csr_drv.h" + +#define CLOCK_DIV_INVALID (~0UL) + +/** + * @brief Error codes for clock driver + */ +enum { + status_clk_div_invalid = MAKE_STATUS(status_group_clk, 0), + status_clk_src_invalid = MAKE_STATUS(status_group_clk, 1), + status_clk_invalid = MAKE_STATUS(status_group_clk, 2), + status_clk_operation_unsupported = MAKE_STATUS(status_group_clk, 3), + status_clk_shared_ahb = MAKE_STATUS(status_group_clk, 4), + status_clk_shared_axis = MAKE_STATUS(status_group_clk, 5), + status_clk_shared_axic = MAKE_STATUS(status_group_clk, 6), + status_clk_shared_axiv = MAKE_STATUS(status_group_clk, 7), + status_clk_shared_axif = MAKE_STATUS(status_group_clk, 8), + status_clk_shared_axid = MAKE_STATUS(status_group_clk, 9), + status_clk_fixed = MAKE_STATUS(status_group_clk, 10), + +}; + + +/** + * @brief Clock source group definitions + */ +#define CLK_SRC_GROUP_COMMON (0U) +#define CLK_SRC_GROUP_ADC (1U) +#define CLK_SRC_GROUP_I2S (2U) +#define CLK_SRC_GROUP_EWDG (3U) +#define CLK_SRC_GROUP_PEWDG (4U) +#define CLK_SRC_GROUP_PMIC (5U) +#define CLK_SRC_GROUP_AXI_SOC (6U) +#define CLK_SRC_GROUP_AXI_FAST (7U) +#define CLK_SRC_GROUP_AXI_VIDEO (8U) +#define CLK_SRC_GROUP_SRC (9U) +#define CLK_SRC_GROUP_INVALID (15U) + +#define MAKE_CLK_SRC(src_grp, index) (((uint8_t)(src_grp)<<4) | (index)) +#define GET_CLK_SRC_GROUP(src) (((uint8_t)(src) >> 4) & 0x0FU) +#define GET_CLK_SRC_INDEX(src) ((uint8_t)(src) & 0x0FU) + +#define GET_CLOCK_SOURCE_FROM_CLK_SRC(clk_src) (clock_source_t)((uint32_t)(clk_src) & 0xFU) + +/** + * @brief Clock source definitions + */ +typedef enum _clock_sources { + clk_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 0), + clk_src_pll0_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 1), + clk_src_pll1_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 2), + clk_src_pll1_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 3), + clk_src_pll2_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 4), + clk_src_pll2_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 5), + clk_src_pll3_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 6), + clk_src_pll4_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 7), + clk_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 8), + + clk_adc_src_ana0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), + clk_adc_src_ana1 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), + clk_adc_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 1), + + clk_i2s_src_aud0 = MAKE_CLK_SRC(CLK_SRC_GROUP_I2S, 0), + clk_i2s_src_aud1 = MAKE_CLK_SRC(CLK_SRC_GROUP_I2S, 0), + clk_i2s_src_aud2 = MAKE_CLK_SRC(CLK_SRC_GROUP_I2S, 0), + clk_i2s_src_aud3 = MAKE_CLK_SRC(CLK_SRC_GROUP_I2S, 0), + clk_i2s_src_audx = MAKE_CLK_SRC(CLK_SRC_GROUP_I2S, 1), + + clk_wdg_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_EWDG, 0), + clk_wdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_EWDG, 1), + + clk_pwdg_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_PEWDG, 0), + clk_pwdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_PEWDG, 1), + + clk_src_invalid = MAKE_CLK_SRC(CLK_SRC_GROUP_INVALID, 15), +} clk_src_t; + + +#define RESOURCE_INVALID (0xFFFFU) +#define RESOURCE_SHARED_AXI_SOC (0xFFFEU) + +/* Clock NAME related Macros */ +#define MAKE_CLOCK_NAME(resource, src_type, node) (((uint32_t)(resource) << 16) | ((uint32_t)(src_type) << 8) | ((uint32_t)node)) +#define GET_CLK_SRC_GROUP_FROM_NAME(name) (((uint32_t)(name) >> 8) & 0xFFUL) +#define GET_CLK_NODE_FROM_NAME(name) ((uint32_t)(name) & 0xFFUL) +#define GET_CLK_RESOURCE_FROM_NAME(name) ((uint32_t)(name) >> 16) + +/** + * @brief Peripheral Clock Type Description + */ +typedef enum _clock_name { + clock_axif = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_axif), + clock_axis = MAKE_CLOCK_NAME(sysctl_resource_axis, CLK_SRC_GROUP_COMMON, clock_node_axis), + clock_axic = MAKE_CLOCK_NAME(sysctl_resource_axic, CLK_SRC_GROUP_COMMON, clock_node_axic), + clock_axiv = MAKE_CLOCK_NAME(sysctl_resource_axiv, CLK_SRC_GROUP_COMMON, clock_node_axiv), + clock_axig = MAKE_CLOCK_NAME(sysctl_resource_axig, CLK_SRC_GROUP_COMMON, clock_node_gpu0), + clock_axid = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_axid), + + /* Software definition for compatibility */ + clock_ahb = MAKE_CLOCK_NAME(RESOURCE_SHARED_AXI_SOC, CLK_SRC_GROUP_AXI_SOC, clock_node_axis), + + clock_cpu0 = MAKE_CLOCK_NAME(sysctl_resource_cpu0, CLK_SRC_GROUP_COMMON, clock_node_cpu0), + clock_mchtmr0 = MAKE_CLOCK_NAME(sysctl_resource_mchtmr0, CLK_SRC_GROUP_COMMON, clock_node_mchtmr0), + clock_gpu0 = MAKE_CLOCK_NAME(sysctl_resource_gpu0, CLK_SRC_GROUP_COMMON, clock_node_gpu0), + + clock_can0 = MAKE_CLOCK_NAME(sysctl_resource_can0, CLK_SRC_GROUP_COMMON, clock_node_can0), + clock_can1 = MAKE_CLOCK_NAME(sysctl_resource_can1, CLK_SRC_GROUP_COMMON, clock_node_can1), + clock_can2 = MAKE_CLOCK_NAME(sysctl_resource_can2, CLK_SRC_GROUP_COMMON, clock_node_can2), + clock_can3 = MAKE_CLOCK_NAME(sysctl_resource_can3, CLK_SRC_GROUP_COMMON, clock_node_can3), + clock_can4 = MAKE_CLOCK_NAME(sysctl_resource_can4, CLK_SRC_GROUP_COMMON, clock_node_can4), + clock_can5 = MAKE_CLOCK_NAME(sysctl_resource_can5, CLK_SRC_GROUP_COMMON, clock_node_can5), + clock_can6 = MAKE_CLOCK_NAME(sysctl_resource_can6, CLK_SRC_GROUP_COMMON, clock_node_can6), + clock_can7 = MAKE_CLOCK_NAME(sysctl_resource_can7, CLK_SRC_GROUP_COMMON, clock_node_can7), + + clock_lin0 = MAKE_CLOCK_NAME(sysctl_resource_lin0, CLK_SRC_GROUP_COMMON, clock_node_lin0), + clock_lin1 = MAKE_CLOCK_NAME(sysctl_resource_lin1, CLK_SRC_GROUP_COMMON, clock_node_lin1), + clock_lin2 = MAKE_CLOCK_NAME(sysctl_resource_lin2, CLK_SRC_GROUP_COMMON, clock_node_lin2), + clock_lin3 = MAKE_CLOCK_NAME(sysctl_resource_lin3, CLK_SRC_GROUP_COMMON, clock_node_lin3), + clock_lin4 = MAKE_CLOCK_NAME(sysctl_resource_lin4, CLK_SRC_GROUP_COMMON, clock_node_lin4), + clock_lin5 = MAKE_CLOCK_NAME(sysctl_resource_lin5, CLK_SRC_GROUP_COMMON, clock_node_lin5), + clock_lin6 = MAKE_CLOCK_NAME(sysctl_resource_lin6, CLK_SRC_GROUP_COMMON, clock_node_lin6), + clock_lin7 = MAKE_CLOCK_NAME(sysctl_resource_lin7, CLK_SRC_GROUP_COMMON, clock_node_lin7), + + clock_i2c0 = MAKE_CLOCK_NAME(sysctl_resource_i2c0, CLK_SRC_GROUP_COMMON, clock_node_i2c0), + clock_i2c1 = MAKE_CLOCK_NAME(sysctl_resource_i2c1, CLK_SRC_GROUP_COMMON, clock_node_i2c1), + clock_i2c2 = MAKE_CLOCK_NAME(sysctl_resource_i2c2, CLK_SRC_GROUP_COMMON, clock_node_i2c2), + clock_i2c3 = MAKE_CLOCK_NAME(sysctl_resource_i2c3, CLK_SRC_GROUP_COMMON, clock_node_i2c3), + + clock_spi0 = MAKE_CLOCK_NAME(sysctl_resource_spi0, CLK_SRC_GROUP_COMMON, clock_node_spi0), + clock_spi1 = MAKE_CLOCK_NAME(sysctl_resource_spi1, CLK_SRC_GROUP_COMMON, clock_node_spi1), + clock_spi2 = MAKE_CLOCK_NAME(sysctl_resource_spi2, CLK_SRC_GROUP_COMMON, clock_node_spi2), + clock_spi3 = MAKE_CLOCK_NAME(sysctl_resource_spi3, CLK_SRC_GROUP_COMMON, clock_node_spi3), + + clock_uart0 = MAKE_CLOCK_NAME(sysctl_resource_uart0, CLK_SRC_GROUP_COMMON, clock_node_uart0), + clock_uart1 = MAKE_CLOCK_NAME(sysctl_resource_uart1, CLK_SRC_GROUP_COMMON, clock_node_uart1), + clock_uart2 = MAKE_CLOCK_NAME(sysctl_resource_uart2, CLK_SRC_GROUP_COMMON, clock_node_uart2), + clock_uart3 = MAKE_CLOCK_NAME(sysctl_resource_uart3, CLK_SRC_GROUP_COMMON, clock_node_uart3), + clock_uart4 = MAKE_CLOCK_NAME(sysctl_resource_uart4, CLK_SRC_GROUP_COMMON, clock_node_uart4), + clock_uart5 = MAKE_CLOCK_NAME(sysctl_resource_uart5, CLK_SRC_GROUP_COMMON, clock_node_uart5), + clock_uart6 = MAKE_CLOCK_NAME(sysctl_resource_uart6, CLK_SRC_GROUP_COMMON, clock_node_uart6), + clock_uart7 = MAKE_CLOCK_NAME(sysctl_resource_uart7, CLK_SRC_GROUP_COMMON, clock_node_uart7), + + clock_gptmr0 = MAKE_CLOCK_NAME(sysctl_resource_gptmr0, CLK_SRC_GROUP_COMMON, clock_node_gptmr0), + clock_gptmr1 = MAKE_CLOCK_NAME(sysctl_resource_gptmr1, CLK_SRC_GROUP_COMMON, clock_node_gptmr1), + clock_gptmr2 = MAKE_CLOCK_NAME(sysctl_resource_gptmr2, CLK_SRC_GROUP_COMMON, clock_node_gptmr2), + clock_gptmr3 = MAKE_CLOCK_NAME(sysctl_resource_gptmr3, CLK_SRC_GROUP_COMMON, clock_node_gptmr3), + clock_gptmr4 = MAKE_CLOCK_NAME(sysctl_resource_gptmr4, CLK_SRC_GROUP_COMMON, clock_node_gptmr4), + clock_gptmr5 = MAKE_CLOCK_NAME(sysctl_resource_gptmr5, CLK_SRC_GROUP_COMMON, clock_node_gptmr5), + clock_gptmr6 = MAKE_CLOCK_NAME(sysctl_resource_gptmr6, CLK_SRC_GROUP_COMMON, clock_node_gptmr6), + clock_gptmr7 = MAKE_CLOCK_NAME(sysctl_resource_gptmr7, CLK_SRC_GROUP_COMMON, clock_node_gptmr7), + + clock_xpi0 = MAKE_CLOCK_NAME(sysctl_resource_xpi0, CLK_SRC_GROUP_COMMON, clock_node_xpi0), + + clock_xram = MAKE_CLOCK_NAME(sysctl_resource_xram, CLK_SRC_GROUP_COMMON, clock_node_xram), + clock_ddr0 = MAKE_CLOCK_NAME(sysctl_resource_ddr0, CLK_SRC_GROUP_AXI_FAST, clock_node_axif), + + clock_eth0 = MAKE_CLOCK_NAME(sysctl_resource_eth0, CLK_SRC_GROUP_COMMON, clock_node_eth0), + + clock_ptp0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ptp0), + + clock_sdxc0 = MAKE_CLOCK_NAME(sysctl_resource_sdc0, CLK_SRC_GROUP_COMMON, clock_node_sdc0), + clock_sdxc1 = MAKE_CLOCK_NAME(sysctl_resource_sdc1, CLK_SRC_GROUP_COMMON, clock_node_sdc1), + + clock_ntm0 = MAKE_CLOCK_NAME(sysctl_resource_ntm0, CLK_SRC_GROUP_COMMON, clock_node_ntm0), + + clock_ref0 = MAKE_CLOCK_NAME(sysctl_resource_ref0, CLK_SRC_GROUP_COMMON, clock_node_ref0), + clock_ref1 = MAKE_CLOCK_NAME(sysctl_resource_ref1, CLK_SRC_GROUP_COMMON, clock_node_ref1), + + clock_cam0 = MAKE_CLOCK_NAME(sysctl_resource_cam0, CLK_SRC_GROUP_COMMON, clock_node_cam0), + clock_cam1 = MAKE_CLOCK_NAME(sysctl_resource_cam1, CLK_SRC_GROUP_COMMON, clock_node_cam1), + + clock_lcd0 = MAKE_CLOCK_NAME(sysctl_resource_lcd0, CLK_SRC_GROUP_COMMON, clock_node_lcd0), + clock_lcd1 = MAKE_CLOCK_NAME(sysctl_resource_lcd1, CLK_SRC_GROUP_COMMON, clock_node_lcd1), + + clock_csi0 = MAKE_CLOCK_NAME(sysctl_resource_csi0, CLK_SRC_GROUP_COMMON, clock_node_csi0), + clock_csi1 = MAKE_CLOCK_NAME(sysctl_resource_csi1, CLK_SRC_GROUP_COMMON, clock_node_csi1), + clock_dsi0 = MAKE_CLOCK_NAME(sysctl_resource_dsi0, CLK_SRC_GROUP_AXI_VIDEO, clock_node_invalid), + clock_dsi1 = MAKE_CLOCK_NAME(sysctl_resource_dsi1, CLK_SRC_GROUP_AXI_VIDEO, clock_node_invalid), + + clock_gwc0 = MAKE_CLOCK_NAME(sysctl_resource_gwc0, CLK_SRC_GROUP_AXI_VIDEO, clock_node_invalid), + clock_gwc1 = MAKE_CLOCK_NAME(sysctl_resource_gwc1, CLK_SRC_GROUP_AXI_VIDEO, clock_node_invalid), + + clock_lvb = MAKE_CLOCK_NAME(sysctl_resource_lvb0, CLK_SRC_GROUP_AXI_VIDEO, clock_node_invalid), + clock_lcb = MAKE_CLOCK_NAME(sysctl_resource_lcb0, CLK_SRC_GROUP_AXI_VIDEO, clock_node_invalid), + + clock_ffa = MAKE_CLOCK_NAME(sysctl_resource_ffa0, CLK_SRC_GROUP_AXI_SOC, clock_node_invalid), + clock_tsns = MAKE_CLOCK_NAME(sysctl_resource_tsns, CLK_SRC_GROUP_PMIC, clock_node_invalid), + + clock_ptpc = MAKE_CLOCK_NAME(sysctl_resource_ptpc, CLK_SRC_GROUP_AXI_SOC, clock_node_invalid), + clock_watchdog0 = MAKE_CLOCK_NAME(sysctl_resource_wdg0, CLK_SRC_GROUP_EWDG, 0), /* 0 - instance */ + clock_watchdog1 = MAKE_CLOCK_NAME(sysctl_resource_wdg1, CLK_SRC_GROUP_EWDG, 1), /* 1 - instance */ + clock_puart = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, clock_node_invalid), + clock_pwdg = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, clock_node_invalid), + clock_sdp = MAKE_CLOCK_NAME(sysctl_resource_sdp0, CLK_SRC_GROUP_AXI_SOC, clock_node_invalid), + clock_xdma = MAKE_CLOCK_NAME(sysctl_resource_dma1, CLK_SRC_GROUP_AXI_SOC, clock_node_invalid), + clock_rom = MAKE_CLOCK_NAME(sysctl_resource_rom0, CLK_SRC_GROUP_AXI_SOC, clock_node_invalid), + clock_usb0 = MAKE_CLOCK_NAME(sysctl_resource_usb0, CLK_SRC_GROUP_AXI_SOC, clock_node_invalid), + clock_jpeg = MAKE_CLOCK_NAME(sysctl_resource_jpeg, CLK_SRC_GROUP_AXI_VIDEO, clock_node_invalid), + clock_pdma = MAKE_CLOCK_NAME(sysctl_resource_pdma, CLK_SRC_GROUP_AXI_VIDEO, clock_node_invalid), + clock_kman = MAKE_CLOCK_NAME(sysctl_resource_kman, CLK_SRC_GROUP_AXI_SOC, clock_node_invalid), + clock_gpio = MAKE_CLOCK_NAME(sysctl_resource_gpio, CLK_SRC_GROUP_AXI_SOC, clock_node_invalid), + clock_mbx0 = MAKE_CLOCK_NAME(sysctl_resource_mbx0, CLK_SRC_GROUP_AXI_SOC, clock_node_invalid), + clock_mbx1 = MAKE_CLOCK_NAME(sysctl_resource_mbx1, CLK_SRC_GROUP_AXI_SOC, clock_node_invalid), + clock_hdma = MAKE_CLOCK_NAME(sysctl_resource_dma0, CLK_SRC_GROUP_AXI_SOC, clock_node_invalid), + clock_rng = MAKE_CLOCK_NAME(sysctl_resource_rng0, CLK_SRC_GROUP_AXI_SOC, clock_node_invalid), + clock_pdm = MAKE_CLOCK_NAME(sysctl_resource_pdm0, CLK_SRC_GROUP_I2S, clock_node_invalid), + clock_dao = MAKE_CLOCK_NAME(sysctl_resource_dao0, CLK_SRC_GROUP_I2S, clock_node_invalid), + clock_smix = MAKE_CLOCK_NAME(sysctl_resource_smix, CLK_SRC_GROUP_I2S, clock_node_invalid), + + /* For ADC, there are 2-stage clock source and divider configuration */ + clock_ana0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana0), + clock_ana1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana1), + clock_adc0 = MAKE_CLOCK_NAME(sysctl_resource_adc0, CLK_SRC_GROUP_ADC, 0), /* 0 - instance */ + clock_adc1 = MAKE_CLOCK_NAME(sysctl_resource_adc1, CLK_SRC_GROUP_ADC, 1), /* 1 - instance */ + + clock_crc0 = MAKE_CLOCK_NAME(sysctl_resource_crc0, CLK_SRC_GROUP_AXI_SOC, clock_node_invalid), + + /* For I2S, there are 2-stage clock source and divider configuration */ + clock_aud0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_aud0), + clock_aud1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_aud1), + clock_aud2 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_aud2), + clock_aud3 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_aud3), + clock_i2s0 = MAKE_CLOCK_NAME(sysctl_resource_i2s0, CLK_SRC_GROUP_I2S, 0), /* 0 - instance */ + clock_i2s1 = MAKE_CLOCK_NAME(sysctl_resource_i2s1, CLK_SRC_GROUP_I2S, 1), /* 1 - instance */ + clock_i2s2 = MAKE_CLOCK_NAME(sysctl_resource_i2s2, CLK_SRC_GROUP_I2S, 2), /* 2 - instance */ + clock_i2s3 = MAKE_CLOCK_NAME(sysctl_resource_i2s3, CLK_SRC_GROUP_I2S, 3), /* 3 - instance */ + + /* Clock sources */ + clk_osc0clk0 = MAKE_CLOCK_NAME(sysctl_resource_xtal, CLK_SRC_GROUP_SRC, 0), + clk_pll0clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll0, CLK_SRC_GROUP_SRC, 1), + clk_pll1clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll1, CLK_SRC_GROUP_SRC, 2), + clk_pll1clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll1, CLK_SRC_GROUP_SRC, 3), + clk_pll2clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll2, CLK_SRC_GROUP_SRC, 4), + clk_pll2clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll2, CLK_SRC_GROUP_SRC, 5), + clk_pll3clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll3, CLK_SRC_GROUP_SRC, 6), + clk_pll4clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll4, CLK_SRC_GROUP_SRC, 7), + +} clock_name_t; + +extern uint32_t hpm_core_clock; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Get specified IP frequency + * @param[in] clock_name IP clock name + * + * @return IP clock frequency in Hz + */ +uint32_t clock_get_frequency(clock_name_t clock_name); + + +/** + * @brief Get Clock frequency for selected clock source + * @param [in] source clock source + * @return clock frequency for selected clock source + */ +uint32_t get_frequency_for_source(clock_source_t source); + +/** + * @brief Get the IP clock source + * Note: This API return the direct clock source + * @param [in] clock_name clock name + * @return IP clock source + */ +clk_src_t clock_get_source(clock_name_t clock_name); + +/** + * @brief Get the IP clock divider + * Note:This API return the direct clock divider + * @param [in] clock_name clock name + * @return IP clock divider + */ +uint32_t clock_get_divider(clock_name_t clock_name); + +/** + * @brief Set ADC clock source + * @param[in] clock_name ADC clock name + * @param[in] src ADC clock source + * + * @return #status_success Setting ADC clock source is successful + * #status_clk_invalid Invalid ADC clock + * #status_clk_src_invalid Invalid ADC clock source + */ +hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src); + +/** + * @brief Set I2S clock source + * @param[in] clock_name I2S clock name + * @param[in] src I2S clock source + * + * @return #status_success Setting DAC clock source is successful + * #status_clk_invalid Invalid DAC clock + * #status_clk_src_invalid Invalid DAC clock source + */ +hpm_stat_t clock_set_i2s_source(clock_name_t clock_name, clk_src_t src); + +/** + * @brief Set the IP clock source and divider + * @param[in] clock_name clock name + * @param[in] src clock source + * @param[in] div clock divider, valid range (1 - 256) + * + * @return #status_success Setting Clock source and divider is successful. + * #status_clk_src_invalid clock source is invalid. + * #status_clk_fixed clock source and divider is a fixed value + * #status_clk_shared_ahb Clock is shared with the AHB clock + * #status_clk_shared_axis Clock is shared with the AXI_SOC clock + * #status_clk_shared_axic CLock is shared with the AXI_CONNECTIVITY clock + * #status_clk_shared_axiv Clock is shared with the AXI_VIDEO clock + * #status_clk_shared_axif Clock is shared with the AXI_FAST clock + * #status_clk_shared_axid Clock is shared with the AXI_DISPLAY clock + */ +hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint32_t div); + +/** + * @brief Enable IP clock + * @param[in] clock_name IP clock name + */ +void clock_enable(clock_name_t clock_name); + +/** + * @brief Disable IP clock + * @param[in] clock_name IP clock name + */ +void clock_disable(clock_name_t clock_name); + +/** + * @brief Add IP to specified group + * @param[in] clock_name IP clock name + * @param[in] group resource group index, valid value: 0/1/2/3 + */ +void clock_add_to_group(clock_name_t clock_name, uint32_t group); + +/** + * @brief Remove IP from specified group + * @param[in] clock_name IP clock name + * @param[in] group resource group index, valid value: 0/1/2/3 + */ +void clock_remove_from_group(clock_name_t clock_name, uint32_t group); + +/** + * @brief Check IP in specified group + * @param[in] clock_name IP clock name + * @return true if in group, false if not in group + */ +bool clock_check_in_group(clock_name_t clock_name, uint32_t group); + +/** + * @brief Disconnect the clock group from specified CPU + * @param[in] group clock group index, value value is 0/1/2/3 + * @param[in] cpu CPU index, valid value is 0/1 + */ +void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu); + +/** + * @brief Disconnect the clock group from specified CPU + * @param[in] group clock group index, value value is 0/1/2/3 + * @param[in] cpu CPU index, valid value is 0/1 + */ +void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu); + +/** + * @brief Delay specified microseconds + * + * @param [in] us expected delay interval in microseconds + */ +void clock_cpu_delay_us(uint32_t us); + +/** + * @brief Delay specified milliseconds + * + * @param [in] ms expected delay interval in milliseconds + */ +void clock_cpu_delay_ms(uint32_t ms); + +/** + * @brief Update the Core clock frequency + */ +void clock_update_core_clock(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_CLOCK_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_csr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_csr_regs.h new file mode 100644 index 00000000000..5f43b12bd1a --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_csr_regs.h @@ -0,0 +1,6512 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_CSR_H +#define HPM_CSR_H + +/* STANDARD CRS address definition */ +#define CSR_USTATUS (0x0) +#define CSR_UIE (0x4) +#define CSR_UTVEC (0x5) +#define CSR_USCRATCH (0x40) +#define CSR_UEPC (0x41) +#define CSR_UCAUSE (0x42) +#define CSR_UTVAL (0x43) +#define CSR_UIP (0x44) +#define CSR_SSTATUS (0x100) +#define CSR_SEDELEG (0x102) +#define CSR_SIDELEG (0x103) +#define CSR_SIE (0x104) +#define CSR_STVEC (0x105) +#define CSR_SSCRATCH (0x140) +#define CSR_SEPC (0x141) +#define CSR_SCAUSE (0x142) +#define CSR_STVAL (0x143) +#define CSR_SIP (0x144) +#define CSR_SATP (0x180) +#define CSR_MSTATUS (0x300) +#define CSR_MISA (0x301) +#define CSR_MEDELEG (0x302) +#define CSR_MIDELEG (0x303) +#define CSR_MIE (0x304) +#define CSR_MTVEC (0x305) +#define CSR_MCOUNTEREN (0x306) +#define CSR_MHPMEVENT3 (0x323) +#define CSR_MHPMEVENT4 (0x324) +#define CSR_MHPMEVENT5 (0x325) +#define CSR_MHPMEVENT6 (0x326) +#define CSR_MSCRATCH (0x340) +#define CSR_MEPC (0x341) +#define CSR_MCAUSE (0x342) +#define CSR_MTVAL (0x343) +#define CSR_MIP (0x344) +#define CSR_PMPCFG0 (0x3A0) +#define CSR_PMPCFG1 (0x3A1) +#define CSR_PMPCFG2 (0x3A2) +#define CSR_PMPCFG3 (0x3A3) +#define CSR_PMPADDR0 (0x3B0) +#define CSR_PMPADDR1 (0x3B1) +#define CSR_PMPADDR2 (0x3B2) +#define CSR_PMPADDR3 (0x3B3) +#define CSR_PMPADDR4 (0x3B4) +#define CSR_PMPADDR5 (0x3B5) +#define CSR_PMPADDR6 (0x3B6) +#define CSR_PMPADDR7 (0x3B7) +#define CSR_PMPADDR8 (0x3B8) +#define CSR_PMPADDR9 (0x3B9) +#define CSR_PMPADDR10 (0x3BA) +#define CSR_PMPADDR11 (0x3BB) +#define CSR_PMPADDR12 (0x3BC) +#define CSR_PMPADDR13 (0x3BD) +#define CSR_PMPADDR14 (0x3BE) +#define CSR_PMPADDR15 (0x3BF) +#define CSR_TSELECT (0x7A0) +#define CSR_TDATA1 (0x7A1) +#define CSR_MCONTROL (0x7A1) +#define CSR_ICOUNT (0x7A1) +#define CSR_ITRIGGER (0x7A1) +#define CSR_ETRIGGER (0x7A1) +#define CSR_TDATA2 (0x7A2) +#define CSR_TDATA3 (0x7A3) +#define CSR_TEXTRA (0x7A3) +#define CSR_TINFO (0x7A4) +#define CSR_TCONTROL (0x7A5) +#define CSR_MCONTEXT (0x7A8) +#define CSR_SCONTEXT (0x7AA) +#define CSR_DCSR (0x7B0) +#define CSR_DPC (0x7B1) +#define CSR_DSCRATCH0 (0x7B2) +#define CSR_DSCRATCH1 (0x7B3) +#define CSR_MCYCLE (0xB00) +#define CSR_MINSTRET (0xB02) +#define CSR_MHPMCOUNTER3 (0xB03) +#define CSR_MHPMCOUNTER4 (0xB04) +#define CSR_MHPMCOUNTER5 (0xB05) +#define CSR_MHPMCOUNTER6 (0xB06) +#define CSR_MCYCLEH (0xB80) +#define CSR_MINSTRETH (0xB82) +#define CSR_MHPMCOUNTER3H (0xB83) +#define CSR_MHPMCOUNTER4H (0xB84) +#define CSR_MHPMCOUNTER5H (0xB85) +#define CSR_MHPMCOUNTER6H (0xB86) +#define CSR_PMACFG0 (0xBC0) +#define CSR_PMACFG1 (0xBC1) +#define CSR_PMACFG2 (0xBC2) +#define CSR_PMACFG3 (0xBC3) +#define CSR_PMAADDR0 (0xBD0) +#define CSR_PMAADDR1 (0xBD1) +#define CSR_PMAADDR2 (0xBD2) +#define CSR_PMAADDR3 (0xBD3) +#define CSR_PMAADDR4 (0xBD4) +#define CSR_PMAADDR5 (0xBD5) +#define CSR_PMAADDR6 (0xBD6) +#define CSR_PMAADDR7 (0xBD7) +#define CSR_PMAADDR8 (0xBD8) +#define CSR_PMAADDR9 (0xBD9) +#define CSR_PMAADDR10 (0xBDA) +#define CSR_PMAADDR11 (0xBDB) +#define CSR_PMAADDR12 (0xBDC) +#define CSR_PMAADDR13 (0xBDD) +#define CSR_PMAADDR14 (0xBDE) +#define CSR_PMAADDR15 (0xBDF) +#define CSR_CYCLE (0xC00) +#define CSR_CYCLEH (0xC80) +#define CSR_MVENDORID (0xF11) +#define CSR_MARCHID (0xF12) +#define CSR_MIMPID (0xF13) +#define CSR_MHARTID (0xF14) + +/* NON-STANDARD CRS address definition */ +#define CSR_SCOUNTEREN (0x106) +#define CSR_MCOUNTINHIBIT (0x320) +#define CSR_MILMB (0x7C0) +#define CSR_MDLMB (0x7C1) +#define CSR_MECC_CODE (0x7C2) +#define CSR_MNVEC (0x7C3) +#define CSR_MXSTATUS (0x7C4) +#define CSR_MPFT_CTL (0x7C5) +#define CSR_MHSP_CTL (0x7C6) +#define CSR_MSP_BOUND (0x7C7) +#define CSR_MSP_BASE (0x7C8) +#define CSR_MDCAUSE (0x7C9) +#define CSR_MCACHE_CTL (0x7CA) +#define CSR_MCCTLBEGINADDR (0x7CB) +#define CSR_MCCTLCOMMAND (0x7CC) +#define CSR_MCCTLDATA (0x7CD) +#define CSR_MCOUNTERWEN (0x7CE) +#define CSR_MCOUNTERINTEN (0x7CF) +#define CSR_MMISC_CTL (0x7D0) +#define CSR_MCOUNTERMASK_M (0x7D1) +#define CSR_MCOUNTERMASK_S (0x7D2) +#define CSR_MCOUNTERMASK_U (0x7D3) +#define CSR_MCOUNTEROVF (0x7D4) +#define CSR_MSLIDELEG (0x7D5) +#define CSR_MCLK_CTL (0x7DF) +#define CSR_DEXC2DBG (0x7E0) +#define CSR_DDCAUSE (0x7E1) +#define CSR_UITB (0x800) +#define CSR_UCODE (0x801) +#define CSR_UDCAUSE (0x809) +#define CSR_UCCTLBEGINADDR (0x80B) +#define CSR_UCCTLCOMMAND (0x80C) +#define CSR_SLIE (0x9C4) +#define CSR_SLIP (0x9C5) +#define CSR_SDCAUSE (0x9C9) +#define CSR_SCCTLDATA (0x9CD) +#define CSR_SCOUNTERINTEN (0x9CF) +#define CSR_SCOUNTERMASK_M (0x9D1) +#define CSR_SCOUNTERMASK_S (0x9D2) +#define CSR_SCOUNTERMASK_U (0x9D3) +#define CSR_SCOUNTEROVF (0x9D4) +#define CSR_SCOUNTINHIBIT (0x9E0) +#define CSR_SHPMEVENT3 (0x9E3) +#define CSR_SHPMEVENT4 (0x9E4) +#define CSR_SHPMEVENT5 (0x9E5) +#define CSR_SHPMEVENT6 (0x9E6) +#define CSR_MICM_CFG (0xFC0) +#define CSR_MDCM_CFG (0xFC1) +#define CSR_MMSC_CFG (0xFC2) +#define CSR_MMSC_CFG2 (0xFC3) + +/* STANDARD CRS register bitfiled definitions */ + +/* Bitfield definition for register: USTATUS */ +/* + * UPIE (RW) + * + * UPIE holds the value of the UIE bit prior to a trap. + */ +#define CSR_USTATUS_UPIE_MASK (0x10U) +#define CSR_USTATUS_UPIE_SHIFT (4U) +#define CSR_USTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_USTATUS_UPIE_SHIFT) & CSR_USTATUS_UPIE_MASK) +#define CSR_USTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_USTATUS_UPIE_MASK) >> CSR_USTATUS_UPIE_SHIFT) + +/* + * UIE (RW) + * + * U mode interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_USTATUS_UIE_MASK (0x1U) +#define CSR_USTATUS_UIE_SHIFT (0U) +#define CSR_USTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_USTATUS_UIE_SHIFT) & CSR_USTATUS_UIE_MASK) +#define CSR_USTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_USTATUS_UIE_MASK) >> CSR_USTATUS_UIE_SHIFT) + +/* Bitfield definition for register: UIE */ +/* + * UEIE (RW) + * + * U mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_UIE_UEIE_MASK (0x100U) +#define CSR_UIE_UEIE_SHIFT (8U) +#define CSR_UIE_UEIE_SET(x) (((uint32_t)(x) << CSR_UIE_UEIE_SHIFT) & CSR_UIE_UEIE_MASK) +#define CSR_UIE_UEIE_GET(x) (((uint32_t)(x) & CSR_UIE_UEIE_MASK) >> CSR_UIE_UEIE_SHIFT) + +/* + * UTIE (RW) + * + * U mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_UIE_UTIE_MASK (0x10U) +#define CSR_UIE_UTIE_SHIFT (4U) +#define CSR_UIE_UTIE_SET(x) (((uint32_t)(x) << CSR_UIE_UTIE_SHIFT) & CSR_UIE_UTIE_MASK) +#define CSR_UIE_UTIE_GET(x) (((uint32_t)(x) & CSR_UIE_UTIE_MASK) >> CSR_UIE_UTIE_SHIFT) + +/* + * USIE (RW) + * + * U mode software interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_UIE_USIE_MASK (0x1U) +#define CSR_UIE_USIE_SHIFT (0U) +#define CSR_UIE_USIE_SET(x) (((uint32_t)(x) << CSR_UIE_USIE_SHIFT) & CSR_UIE_USIE_MASK) +#define CSR_UIE_USIE_GET(x) (((uint32_t)(x) & CSR_UIE_USIE_MASK) >> CSR_UIE_USIE_SHIFT) + +/* Bitfield definition for register: UTVEC */ +/* + * BASE_31_2 (RW) + * + * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode. + */ +#define CSR_UTVEC_BASE_31_2_MASK (0xFFFFFFFCUL) +#define CSR_UTVEC_BASE_31_2_SHIFT (2U) +#define CSR_UTVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_UTVEC_BASE_31_2_SHIFT) & CSR_UTVEC_BASE_31_2_MASK) +#define CSR_UTVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_UTVEC_BASE_31_2_MASK) >> CSR_UTVEC_BASE_31_2_SHIFT) + +/* Bitfield definition for register: USCRATCH */ +/* + * USCRATCH (RW) + * + * Scratch register storage. + */ +#define CSR_USCRATCH_USCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_USCRATCH_USCRATCH_SHIFT (0U) +#define CSR_USCRATCH_USCRATCH_SET(x) (((uint32_t)(x) << CSR_USCRATCH_USCRATCH_SHIFT) & CSR_USCRATCH_USCRATCH_MASK) +#define CSR_USCRATCH_USCRATCH_GET(x) (((uint32_t)(x) & CSR_USCRATCH_USCRATCH_MASK) >> CSR_USCRATCH_USCRATCH_SHIFT) + +/* Bitfield definition for register: UEPC */ +/* + * EPC (RW) + * + * Exception program counter. + */ +#define CSR_UEPC_EPC_MASK (0xFFFFFFFEUL) +#define CSR_UEPC_EPC_SHIFT (1U) +#define CSR_UEPC_EPC_SET(x) (((uint32_t)(x) << CSR_UEPC_EPC_SHIFT) & CSR_UEPC_EPC_MASK) +#define CSR_UEPC_EPC_GET(x) (((uint32_t)(x) & CSR_UEPC_EPC_MASK) >> CSR_UEPC_EPC_SHIFT) + +/* Bitfield definition for register: UCAUSE */ +/* + * INTERRUPT (RW) + * + * Interrupt. + */ +#define CSR_UCAUSE_INTERRUPT_MASK (0x80000000UL) +#define CSR_UCAUSE_INTERRUPT_SHIFT (31U) +#define CSR_UCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_UCAUSE_INTERRUPT_SHIFT) & CSR_UCAUSE_INTERRUPT_MASK) +#define CSR_UCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_UCAUSE_INTERRUPT_MASK) >> CSR_UCAUSE_INTERRUPT_SHIFT) + +/* + * EXCEPTION_CODE (RW) + * + * Exception Code. + * When interrupt is 1: + * 0:User software interrupt + * 4:User timer interrupt + * 8:User external interrupt + * When interrupt is 0: + * 0:Instruction address misaligned + * 1:Instruction access fault + * 2:Illegal instruction + * 3:Breakpoint + * 4:Load address misaligned + * 5:Load access fault + * 6:Store/AMO address misaligned + * 7:Store/AMO access fault + * 8:Environment call from U-mode + * 9-11:Reserved + * 12:Instruction page fault + * 13:Load page fault + * 14:Reserved + * 15:Store/AMO page fault + * 32：Stack overflow exception + * 33:Stack underflow exception + * 40-47:Reserved + */ +#define CSR_UCAUSE_EXCEPTION_CODE_MASK (0x3FFU) +#define CSR_UCAUSE_EXCEPTION_CODE_SHIFT (0U) +#define CSR_UCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_UCAUSE_EXCEPTION_CODE_SHIFT) & CSR_UCAUSE_EXCEPTION_CODE_MASK) +#define CSR_UCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_UCAUSE_EXCEPTION_CODE_MASK) >> CSR_UCAUSE_EXCEPTION_CODE_SHIFT) + +/* Bitfield definition for register: UTVAL */ +/* + * UTVAL (RW) + * + * Exception-specific information for software trap handling. + */ +#define CSR_UTVAL_UTVAL_MASK (0xFFFFFFFFUL) +#define CSR_UTVAL_UTVAL_SHIFT (0U) +#define CSR_UTVAL_UTVAL_SET(x) (((uint32_t)(x) << CSR_UTVAL_UTVAL_SHIFT) & CSR_UTVAL_UTVAL_MASK) +#define CSR_UTVAL_UTVAL_GET(x) (((uint32_t)(x) & CSR_UTVAL_UTVAL_MASK) >> CSR_UTVAL_UTVAL_SHIFT) + +/* Bitfield definition for register: UIP */ +/* + * UEIP (RW) + * + * U mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_UIP_UEIP_MASK (0x100U) +#define CSR_UIP_UEIP_SHIFT (8U) +#define CSR_UIP_UEIP_SET(x) (((uint32_t)(x) << CSR_UIP_UEIP_SHIFT) & CSR_UIP_UEIP_MASK) +#define CSR_UIP_UEIP_GET(x) (((uint32_t)(x) & CSR_UIP_UEIP_MASK) >> CSR_UIP_UEIP_SHIFT) + +/* + * UTIP (RW) + * + * U mode timer interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_UIP_UTIP_MASK (0x10U) +#define CSR_UIP_UTIP_SHIFT (4U) +#define CSR_UIP_UTIP_SET(x) (((uint32_t)(x) << CSR_UIP_UTIP_SHIFT) & CSR_UIP_UTIP_MASK) +#define CSR_UIP_UTIP_GET(x) (((uint32_t)(x) & CSR_UIP_UTIP_MASK) >> CSR_UIP_UTIP_SHIFT) + +/* + * USIP (RW) + * + * U mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_UIP_USIP_MASK (0x1U) +#define CSR_UIP_USIP_SHIFT (0U) +#define CSR_UIP_USIP_SET(x) (((uint32_t)(x) << CSR_UIP_USIP_SHIFT) & CSR_UIP_USIP_MASK) +#define CSR_UIP_USIP_GET(x) (((uint32_t)(x) & CSR_UIP_USIP_MASK) >> CSR_UIP_USIP_SHIFT) + +/* Bitfield definition for register: SSTATUS */ +/* + * SD (RO) + * + * SD summarizes whether either the FS field or XS field is dirty. + */ +#define CSR_SSTATUS_SD_MASK (0x80000000UL) +#define CSR_SSTATUS_SD_SHIFT (31U) +#define CSR_SSTATUS_SD_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SD_MASK) >> CSR_SSTATUS_SD_SHIFT) + +/* + * MXR (RW) + * + * MXR controls whether execute-only pages are readable. It has no effect when page-based virtual memory is not in effect. + * 0:Execute-only pages are not readable + * 1:Execute-only pages are readable + */ +#define CSR_SSTATUS_MXR_MASK (0x80000UL) +#define CSR_SSTATUS_MXR_SHIFT (19U) +#define CSR_SSTATUS_MXR_SET(x) (((uint32_t)(x) << CSR_SSTATUS_MXR_SHIFT) & CSR_SSTATUS_MXR_MASK) +#define CSR_SSTATUS_MXR_GET(x) (((uint32_t)(x) & CSR_SSTATUS_MXR_MASK) >> CSR_SSTATUS_MXR_SHIFT) + +/* + * SUM (RW) + * + * SUM controls whether a S-mode load/store instruction to a user accessible page is allowed or not when page translation is enabled. It is in effect in two scenarios: (a) M-mode with MPRV=1 and MPP=S, and (b) in S-mode. It has no effect when page-based virtual memory is not in effect. A page is user accessible when the U bit of the corresponding PTE entry is 1. + * 0:Not Allowed + * 1:Allowed + */ +#define CSR_SSTATUS_SUM_MASK (0x40000UL) +#define CSR_SSTATUS_SUM_SHIFT (18U) +#define CSR_SSTATUS_SUM_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SUM_SHIFT) & CSR_SSTATUS_SUM_MASK) +#define CSR_SSTATUS_SUM_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SUM_MASK) >> CSR_SSTATUS_SUM_SHIFT) + +/* + * XS (RO) + * + * XS holds the status of the architectural states (ACE registers) of ACE instructions. The value of this field is zero if ACE extension is not configured. + * This field is primarily managed by software. The processor hardware assists the state managements in two regards: + * Illegal instruction exceptions are triggeredwhen XS is Off. + * XS is updated to the Dirty state with the execution of ACE instructions when XS is not Off. + * Changing the setting of this field has no effect on the contents of ACE states. In particular, setting XS to Off does not destroy the states, nor does setting XS to Initial clear the contents. + * The same copy of XS bits are shared by both mstatus and sstatus. Normally the supervisor mode privileged software would use the XS bits to manage deferred context switches of ACE states. Machine mode software should be more conservative in managing context switches using XS bits + * 0:Off + * 1:Initial + * 2:Clean + * 3:Dirty + */ +#define CSR_SSTATUS_XS_MASK (0x18000UL) +#define CSR_SSTATUS_XS_SHIFT (15U) +#define CSR_SSTATUS_XS_GET(x) (((uint32_t)(x) & CSR_SSTATUS_XS_MASK) >> CSR_SSTATUS_XS_SHIFT) + +/* + * FS (RW) + * + * FS holds the status of the architectural states of the floating-point unit, including the fcsr CSR and f0 – f31 floating-point data registers. The value of this field is zero and read-only if the processor does not have FPU. + * This field is primarily managed by software. The processor hardware assists the state managements in two regards: + * Attempts to access fcsr or any f register raise an illegal-instruction exception when FS is Off. + * Otherwise, FS is updated to the Dirty state by any instruction that updates fcsr or any f register. + * Changing the setting of this field has no effect on the contents of the floating-point register states. In particular, setting FS to Off does not destroy the states, nor does setting FS to Initial clear the contents. + * The same copy of FS bits are shared by both mstatus and sstatus. Normally the supervisor mode privileged software would use the FS bits to manage deferred context switches of FPU states. Machine mode software should be more conservative in managing context switches using FS bits. + * 0:Off + * 1:Initial + * 2:Clean + * 3:Dirty + */ +#define CSR_SSTATUS_FS_MASK (0x6000U) +#define CSR_SSTATUS_FS_SHIFT (13U) +#define CSR_SSTATUS_FS_SET(x) (((uint32_t)(x) << CSR_SSTATUS_FS_SHIFT) & CSR_SSTATUS_FS_MASK) +#define CSR_SSTATUS_FS_GET(x) (((uint32_t)(x) & CSR_SSTATUS_FS_MASK) >> CSR_SSTATUS_FS_SHIFT) + +/* + * SPP (RW) + * + * SPP holds the privilege mode prior to a trap. Encoding is 1 for S-mode and 0 for U-mode. + */ +#define CSR_SSTATUS_SPP_MASK (0x100U) +#define CSR_SSTATUS_SPP_SHIFT (8U) +#define CSR_SSTATUS_SPP_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SPP_SHIFT) & CSR_SSTATUS_SPP_MASK) +#define CSR_SSTATUS_SPP_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SPP_MASK) >> CSR_SSTATUS_SPP_SHIFT) + +/* + * SPIE (RW) + * + * SPIE holds the value of the SIE bit prior to a trap. + */ +#define CSR_SSTATUS_SPIE_MASK (0x20U) +#define CSR_SSTATUS_SPIE_SHIFT (5U) +#define CSR_SSTATUS_SPIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SPIE_SHIFT) & CSR_SSTATUS_SPIE_MASK) +#define CSR_SSTATUS_SPIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SPIE_MASK) >> CSR_SSTATUS_SPIE_SHIFT) + +/* + * UPIE (RW) + * + * UPIE holds the value of the UIE bit prior to a trap. + */ +#define CSR_SSTATUS_UPIE_MASK (0x10U) +#define CSR_SSTATUS_UPIE_SHIFT (4U) +#define CSR_SSTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_UPIE_SHIFT) & CSR_SSTATUS_UPIE_MASK) +#define CSR_SSTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_UPIE_MASK) >> CSR_SSTATUS_UPIE_SHIFT) + +/* + * SIE (RW) + * + * S mode interrupt enable bit + * 0 Disabled + * 1 Enabled + */ +#define CSR_SSTATUS_SIE_MASK (0x2U) +#define CSR_SSTATUS_SIE_SHIFT (1U) +#define CSR_SSTATUS_SIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SIE_SHIFT) & CSR_SSTATUS_SIE_MASK) +#define CSR_SSTATUS_SIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SIE_MASK) >> CSR_SSTATUS_SIE_SHIFT) + +/* + * UIE (RW) + * + * U mode interrupt enable bit. + * 0 Disabled + * 1 Enabled + */ +#define CSR_SSTATUS_UIE_MASK (0x1U) +#define CSR_SSTATUS_UIE_SHIFT (0U) +#define CSR_SSTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_UIE_SHIFT) & CSR_SSTATUS_UIE_MASK) +#define CSR_SSTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_UIE_MASK) >> CSR_SSTATUS_UIE_SHIFT) + +/* Bitfield definition for register: SEDELEG */ +/* + * SPF (RW) + * + * SPF indicates whether a Store/AMO Page Fault exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_SPF_MASK (0x8000U) +#define CSR_SEDELEG_SPF_SHIFT (15U) +#define CSR_SEDELEG_SPF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_SPF_SHIFT) & CSR_SEDELEG_SPF_MASK) +#define CSR_SEDELEG_SPF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_SPF_MASK) >> CSR_SEDELEG_SPF_SHIFT) + +/* + * LPF (RW) + * + * LPF indicates whether a Load Page Fault exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_LPF_MASK (0x2000U) +#define CSR_SEDELEG_LPF_SHIFT (13U) +#define CSR_SEDELEG_LPF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_LPF_SHIFT) & CSR_SEDELEG_LPF_MASK) +#define CSR_SEDELEG_LPF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_LPF_MASK) >> CSR_SEDELEG_LPF_SHIFT) + +/* + * IPF (RW) + * + * IPF indicates whether an Instruction Page Fault exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_IPF_MASK (0x1000U) +#define CSR_SEDELEG_IPF_SHIFT (12U) +#define CSR_SEDELEG_IPF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_IPF_SHIFT) & CSR_SEDELEG_IPF_MASK) +#define CSR_SEDELEG_IPF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_IPF_MASK) >> CSR_SEDELEG_IPF_SHIFT) + +/* + * UEC (RW) + * + * UEC indicates whether an exception triggered by environment call from U-mode will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_UEC_MASK (0x100U) +#define CSR_SEDELEG_UEC_SHIFT (8U) +#define CSR_SEDELEG_UEC_SET(x) (((uint32_t)(x) << CSR_SEDELEG_UEC_SHIFT) & CSR_SEDELEG_UEC_MASK) +#define CSR_SEDELEG_UEC_GET(x) (((uint32_t)(x) & CSR_SEDELEG_UEC_MASK) >> CSR_SEDELEG_UEC_SHIFT) + +/* + * SAF (RW) + * + * SAF indicates whether a Store/AMO Access Fault exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_SAF_MASK (0x80U) +#define CSR_SEDELEG_SAF_SHIFT (7U) +#define CSR_SEDELEG_SAF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_SAF_SHIFT) & CSR_SEDELEG_SAF_MASK) +#define CSR_SEDELEG_SAF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_SAF_MASK) >> CSR_SEDELEG_SAF_SHIFT) + +/* + * SAM (RW) + * + * SAM indicates whether a Store/AMO Address Misaligned exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_SAM_MASK (0x40U) +#define CSR_SEDELEG_SAM_SHIFT (6U) +#define CSR_SEDELEG_SAM_SET(x) (((uint32_t)(x) << CSR_SEDELEG_SAM_SHIFT) & CSR_SEDELEG_SAM_MASK) +#define CSR_SEDELEG_SAM_GET(x) (((uint32_t)(x) & CSR_SEDELEG_SAM_MASK) >> CSR_SEDELEG_SAM_SHIFT) + +/* + * LAF (RW) + * + * LAF indicates whether a Load Access Fault exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_LAF_MASK (0x20U) +#define CSR_SEDELEG_LAF_SHIFT (5U) +#define CSR_SEDELEG_LAF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_LAF_SHIFT) & CSR_SEDELEG_LAF_MASK) +#define CSR_SEDELEG_LAF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_LAF_MASK) >> CSR_SEDELEG_LAF_SHIFT) + +/* + * LAM (RW) + * + * LAM indicates whether a Load Address Misaligned exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_LAM_MASK (0x10U) +#define CSR_SEDELEG_LAM_SHIFT (4U) +#define CSR_SEDELEG_LAM_SET(x) (((uint32_t)(x) << CSR_SEDELEG_LAM_SHIFT) & CSR_SEDELEG_LAM_MASK) +#define CSR_SEDELEG_LAM_GET(x) (((uint32_t)(x) & CSR_SEDELEG_LAM_MASK) >> CSR_SEDELEG_LAM_SHIFT) + +/* + * B (RW) + * + * B indicates whether an exception triggered by breakpoint will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_B_MASK (0x8U) +#define CSR_SEDELEG_B_SHIFT (3U) +#define CSR_SEDELEG_B_SET(x) (((uint32_t)(x) << CSR_SEDELEG_B_SHIFT) & CSR_SEDELEG_B_MASK) +#define CSR_SEDELEG_B_GET(x) (((uint32_t)(x) & CSR_SEDELEG_B_MASK) >> CSR_SEDELEG_B_SHIFT) + +/* + * II (RW) + * + * II indicates whether an Illegal Instruction exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_II_MASK (0x4U) +#define CSR_SEDELEG_II_SHIFT (2U) +#define CSR_SEDELEG_II_SET(x) (((uint32_t)(x) << CSR_SEDELEG_II_SHIFT) & CSR_SEDELEG_II_MASK) +#define CSR_SEDELEG_II_GET(x) (((uint32_t)(x) & CSR_SEDELEG_II_MASK) >> CSR_SEDELEG_II_SHIFT) + +/* + * IAF (RW) + * + * IAF indicates whether an Instruction Access Fault exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_IAF_MASK (0x2U) +#define CSR_SEDELEG_IAF_SHIFT (1U) +#define CSR_SEDELEG_IAF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_IAF_SHIFT) & CSR_SEDELEG_IAF_MASK) +#define CSR_SEDELEG_IAF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_IAF_MASK) >> CSR_SEDELEG_IAF_SHIFT) + +/* + * IAM (RW) + * + * IAM indicates whether an Instruction Address Misaligned exception will be delegated to U-mode.. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_IAM_MASK (0x1U) +#define CSR_SEDELEG_IAM_SHIFT (0U) +#define CSR_SEDELEG_IAM_SET(x) (((uint32_t)(x) << CSR_SEDELEG_IAM_SHIFT) & CSR_SEDELEG_IAM_MASK) +#define CSR_SEDELEG_IAM_GET(x) (((uint32_t)(x) & CSR_SEDELEG_IAM_MASK) >> CSR_SEDELEG_IAM_SHIFT) + +/* Bitfield definition for register: SIDELEG */ +/* + * UEI (RW) + * + * UEI indicates whether an U-mode external interrupt will be delegated to S-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SIDELEG_UEI_MASK (0x100U) +#define CSR_SIDELEG_UEI_SHIFT (8U) +#define CSR_SIDELEG_UEI_SET(x) (((uint32_t)(x) << CSR_SIDELEG_UEI_SHIFT) & CSR_SIDELEG_UEI_MASK) +#define CSR_SIDELEG_UEI_GET(x) (((uint32_t)(x) & CSR_SIDELEG_UEI_MASK) >> CSR_SIDELEG_UEI_SHIFT) + +/* + * UTI (RW) + * + * UTI indicates whether an U-mode timer interrupt will be delegated to S-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SIDELEG_UTI_MASK (0x10U) +#define CSR_SIDELEG_UTI_SHIFT (4U) +#define CSR_SIDELEG_UTI_SET(x) (((uint32_t)(x) << CSR_SIDELEG_UTI_SHIFT) & CSR_SIDELEG_UTI_MASK) +#define CSR_SIDELEG_UTI_GET(x) (((uint32_t)(x) & CSR_SIDELEG_UTI_MASK) >> CSR_SIDELEG_UTI_SHIFT) + +/* + * USI (RW) + * + * USI indicates whether an U-mode software interrupt will be delegated to S-mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SIDELEG_USI_MASK (0x1U) +#define CSR_SIDELEG_USI_SHIFT (0U) +#define CSR_SIDELEG_USI_SET(x) (((uint32_t)(x) << CSR_SIDELEG_USI_SHIFT) & CSR_SIDELEG_USI_MASK) +#define CSR_SIDELEG_USI_GET(x) (((uint32_t)(x) & CSR_SIDELEG_USI_MASK) >> CSR_SIDELEG_USI_SHIFT) + +/* Bitfield definition for register: SIE */ +/* + * SEIE (RW) + * + * S mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_SIE_SEIE_MASK (0x200U) +#define CSR_SIE_SEIE_SHIFT (9U) +#define CSR_SIE_SEIE_SET(x) (((uint32_t)(x) << CSR_SIE_SEIE_SHIFT) & CSR_SIE_SEIE_MASK) +#define CSR_SIE_SEIE_GET(x) (((uint32_t)(x) & CSR_SIE_SEIE_MASK) >> CSR_SIE_SEIE_SHIFT) + +/* + * UEIE (RW) + * + * U mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_SIE_UEIE_MASK (0x100U) +#define CSR_SIE_UEIE_SHIFT (8U) +#define CSR_SIE_UEIE_SET(x) (((uint32_t)(x) << CSR_SIE_UEIE_SHIFT) & CSR_SIE_UEIE_MASK) +#define CSR_SIE_UEIE_GET(x) (((uint32_t)(x) & CSR_SIE_UEIE_MASK) >> CSR_SIE_UEIE_SHIFT) + +/* + * STIE (RW) + * + * S mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_SIE_STIE_MASK (0x20U) +#define CSR_SIE_STIE_SHIFT (5U) +#define CSR_SIE_STIE_SET(x) (((uint32_t)(x) << CSR_SIE_STIE_SHIFT) & CSR_SIE_STIE_MASK) +#define CSR_SIE_STIE_GET(x) (((uint32_t)(x) & CSR_SIE_STIE_MASK) >> CSR_SIE_STIE_SHIFT) + +/* + * UTIE (RW) + * + * U mode timer interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_SIE_UTIE_MASK (0x10U) +#define CSR_SIE_UTIE_SHIFT (4U) +#define CSR_SIE_UTIE_SET(x) (((uint32_t)(x) << CSR_SIE_UTIE_SHIFT) & CSR_SIE_UTIE_MASK) +#define CSR_SIE_UTIE_GET(x) (((uint32_t)(x) & CSR_SIE_UTIE_MASK) >> CSR_SIE_UTIE_SHIFT) + +/* + * SSIE (RW) + * + * S mode software interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_SIE_SSIE_MASK (0x2U) +#define CSR_SIE_SSIE_SHIFT (1U) +#define CSR_SIE_SSIE_SET(x) (((uint32_t)(x) << CSR_SIE_SSIE_SHIFT) & CSR_SIE_SSIE_MASK) +#define CSR_SIE_SSIE_GET(x) (((uint32_t)(x) & CSR_SIE_SSIE_MASK) >> CSR_SIE_SSIE_SHIFT) + +/* + * USIE (RW) + * + * U mode software interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_SIE_USIE_MASK (0x1U) +#define CSR_SIE_USIE_SHIFT (0U) +#define CSR_SIE_USIE_SET(x) (((uint32_t)(x) << CSR_SIE_USIE_SHIFT) & CSR_SIE_USIE_MASK) +#define CSR_SIE_USIE_GET(x) (((uint32_t)(x) & CSR_SIE_USIE_MASK) >> CSR_SIE_USIE_SHIFT) + +/* Bitfield definition for register: STVEC */ +/* + * BASE_31_2 (RW) + * + * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode. + */ +#define CSR_STVEC_BASE_31_2_MASK (0xFFFFFFFCUL) +#define CSR_STVEC_BASE_31_2_SHIFT (2U) +#define CSR_STVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_STVEC_BASE_31_2_SHIFT) & CSR_STVEC_BASE_31_2_MASK) +#define CSR_STVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_STVEC_BASE_31_2_MASK) >> CSR_STVEC_BASE_31_2_SHIFT) + +/* Bitfield definition for register: SSCRATCH */ +/* + * SSCRATCH (RW) + * + * Scratch register storage. + */ +#define CSR_SSCRATCH_SSCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_SSCRATCH_SSCRATCH_SHIFT (0U) +#define CSR_SSCRATCH_SSCRATCH_SET(x) (((uint32_t)(x) << CSR_SSCRATCH_SSCRATCH_SHIFT) & CSR_SSCRATCH_SSCRATCH_MASK) +#define CSR_SSCRATCH_SSCRATCH_GET(x) (((uint32_t)(x) & CSR_SSCRATCH_SSCRATCH_MASK) >> CSR_SSCRATCH_SSCRATCH_SHIFT) + +/* Bitfield definition for register: SEPC */ +/* + * EPC (RW) + * + * Exception program counter. + */ +#define CSR_SEPC_EPC_MASK (0xFFFFFFFEUL) +#define CSR_SEPC_EPC_SHIFT (1U) +#define CSR_SEPC_EPC_SET(x) (((uint32_t)(x) << CSR_SEPC_EPC_SHIFT) & CSR_SEPC_EPC_MASK) +#define CSR_SEPC_EPC_GET(x) (((uint32_t)(x) & CSR_SEPC_EPC_MASK) >> CSR_SEPC_EPC_SHIFT) + +/* Bitfield definition for register: SCAUSE */ +/* + * INTERRUPT (RW) + * + * Interrupt. + */ +#define CSR_SCAUSE_INTERRUPT_MASK (0x80000000UL) +#define CSR_SCAUSE_INTERRUPT_SHIFT (31U) +#define CSR_SCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_SCAUSE_INTERRUPT_SHIFT) & CSR_SCAUSE_INTERRUPT_MASK) +#define CSR_SCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_SCAUSE_INTERRUPT_MASK) >> CSR_SCAUSE_INTERRUPT_SHIFT) + +/* + * EXCEPTION_CODE (RW) + * + * Exception Code. + * When interrupt is 1: + * 0:User software interrupt + * 1:Supervisor software interrupt + * 4:User timer interrupt + * 5:Supervisor timer interrupt + * 8:User external interrupt + * 9:Supervisor external interrupt + * 256+16:Slave port ECC error interrupt (S-mode) + * 256+17:Bus write transaction error interrupt (S-mode) + * 256+18:Performance monitor overflow interrupt(S-mode) + * When interrupt is 0: + * 0:Instruction address misaligned + * 1:Instruction access fault + * 2:Illegal instruction + * 3:Breakpoint + * 4:Load address misaligned + * 5:Load access fault + * 6:Store/AMO address misaligned + * 7:Store/AMO access fault + * 8:Environment call from U-mode + * 9:Environment call from S-mode + * 11:10:Reserved + * 12:Instruction page fault + * 13:Load page fault + * 14:Reserved + * 15:Store/AMO page fault + * 32:Stack overflow exception + * 33:Stack underflow exception + * 40-47:Reserved + */ +#define CSR_SCAUSE_EXCEPTION_CODE_MASK (0x3FFU) +#define CSR_SCAUSE_EXCEPTION_CODE_SHIFT (0U) +#define CSR_SCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_SCAUSE_EXCEPTION_CODE_SHIFT) & CSR_SCAUSE_EXCEPTION_CODE_MASK) +#define CSR_SCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_SCAUSE_EXCEPTION_CODE_MASK) >> CSR_SCAUSE_EXCEPTION_CODE_SHIFT) + +/* Bitfield definition for register: STVAL */ +/* + * STVAL (RW) + * + * Exception-specific information for software trap handling. + */ +#define CSR_STVAL_STVAL_MASK (0xFFFFFFFFUL) +#define CSR_STVAL_STVAL_SHIFT (0U) +#define CSR_STVAL_STVAL_SET(x) (((uint32_t)(x) << CSR_STVAL_STVAL_SHIFT) & CSR_STVAL_STVAL_MASK) +#define CSR_STVAL_STVAL_GET(x) (((uint32_t)(x) & CSR_STVAL_STVAL_MASK) >> CSR_STVAL_STVAL_SHIFT) + +/* Bitfield definition for register: SIP */ +/* + * SEIP (RO) + * + * S mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_SIP_SEIP_MASK (0x200U) +#define CSR_SIP_SEIP_SHIFT (9U) +#define CSR_SIP_SEIP_GET(x) (((uint32_t)(x) & CSR_SIP_SEIP_MASK) >> CSR_SIP_SEIP_SHIFT) + +/* + * UEIP (RW) + * + * U mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_SIP_UEIP_MASK (0x100U) +#define CSR_SIP_UEIP_SHIFT (8U) +#define CSR_SIP_UEIP_SET(x) (((uint32_t)(x) << CSR_SIP_UEIP_SHIFT) & CSR_SIP_UEIP_MASK) +#define CSR_SIP_UEIP_GET(x) (((uint32_t)(x) & CSR_SIP_UEIP_MASK) >> CSR_SIP_UEIP_SHIFT) + +/* + * STIP (RO) + * + * S mode timer interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_SIP_STIP_MASK (0x20U) +#define CSR_SIP_STIP_SHIFT (5U) +#define CSR_SIP_STIP_GET(x) (((uint32_t)(x) & CSR_SIP_STIP_MASK) >> CSR_SIP_STIP_SHIFT) + +/* + * UTIP (RO) + * + * U mode timer interrupt pending bit + * 0:Not pending + * 1:Pending + */ +#define CSR_SIP_UTIP_MASK (0x10U) +#define CSR_SIP_UTIP_SHIFT (4U) +#define CSR_SIP_UTIP_GET(x) (((uint32_t)(x) & CSR_SIP_UTIP_MASK) >> CSR_SIP_UTIP_SHIFT) + +/* + * SSIP (RW) + * + * S mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_SIP_SSIP_MASK (0x2U) +#define CSR_SIP_SSIP_SHIFT (1U) +#define CSR_SIP_SSIP_SET(x) (((uint32_t)(x) << CSR_SIP_SSIP_SHIFT) & CSR_SIP_SSIP_MASK) +#define CSR_SIP_SSIP_GET(x) (((uint32_t)(x) & CSR_SIP_SSIP_MASK) >> CSR_SIP_SSIP_SHIFT) + +/* + * USIP (RW) + * + * U mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_SIP_USIP_MASK (0x1U) +#define CSR_SIP_USIP_SHIFT (0U) +#define CSR_SIP_USIP_SET(x) (((uint32_t)(x) << CSR_SIP_USIP_SHIFT) & CSR_SIP_USIP_MASK) +#define CSR_SIP_USIP_GET(x) (((uint32_t)(x) & CSR_SIP_USIP_MASK) >> CSR_SIP_USIP_SHIFT) + +/* Bitfield definition for register: SATP */ +/* + * MODE (RW) + * + * MODE holds the page translation mode. When MODE is Bare, virtual addresses are equal to physical addresses in S-mode. When MMU is + * not supported in the product, this CSR will be + * hardwired to 0. + * 0:No page translation + * 1:Page-based 32-bit virtual addressing + */ +#define CSR_SATP_MODE_MASK (0x80000000UL) +#define CSR_SATP_MODE_SHIFT (31U) +#define CSR_SATP_MODE_SET(x) (((uint32_t)(x) << CSR_SATP_MODE_SHIFT) & CSR_SATP_MODE_MASK) +#define CSR_SATP_MODE_GET(x) (((uint32_t)(x) & CSR_SATP_MODE_MASK) >> CSR_SATP_MODE_SHIFT) + +/* + * ASID (RW) + * + * ASID holds the address space identifier. + */ +#define CSR_SATP_ASID_MASK (0x7FC00000UL) +#define CSR_SATP_ASID_SHIFT (22U) +#define CSR_SATP_ASID_SET(x) (((uint32_t)(x) << CSR_SATP_ASID_SHIFT) & CSR_SATP_ASID_MASK) +#define CSR_SATP_ASID_GET(x) (((uint32_t)(x) & CSR_SATP_ASID_MASK) >> CSR_SATP_ASID_SHIFT) + +/* + * PPN (RW) + * + * PPN holds the physical page number of the root page table. + */ +#define CSR_SATP_PPN_MASK (0x3FFFFFUL) +#define CSR_SATP_PPN_SHIFT (0U) +#define CSR_SATP_PPN_SET(x) (((uint32_t)(x) << CSR_SATP_PPN_SHIFT) & CSR_SATP_PPN_MASK) +#define CSR_SATP_PPN_GET(x) (((uint32_t)(x) & CSR_SATP_PPN_MASK) >> CSR_SATP_PPN_SHIFT) + +/* Bitfield definition for register: MSTATUS */ +/* + * SD (RO) + * + * SD summarizes whether either the FS field or XS field is dirty. + */ +#define CSR_MSTATUS_SD_MASK (0x80000000UL) +#define CSR_MSTATUS_SD_SHIFT (31U) +#define CSR_MSTATUS_SD_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SD_MASK) >> CSR_MSTATUS_SD_SHIFT) + +/* + * TSR (RW) + * + * TSR controls whether executing SRET instructions in S-mode will raise illegal instruction exceptions. It is hardwired to 0 when S-mode is not supported. + * 0: Normal execution + * 1: Raising exceptions + */ +#define CSR_MSTATUS_TSR_MASK (0x400000UL) +#define CSR_MSTATUS_TSR_SHIFT (22U) +#define CSR_MSTATUS_TSR_SET(x) (((uint32_t)(x) << CSR_MSTATUS_TSR_SHIFT) & CSR_MSTATUS_TSR_MASK) +#define CSR_MSTATUS_TSR_GET(x) (((uint32_t)(x) & CSR_MSTATUS_TSR_MASK) >> CSR_MSTATUS_TSR_SHIFT) + +/* + * TW (RW) + * + * TW controls whether executing WFI instructions in S-mode will raise illegal instruction exceptions. It is hardwired to 0 when S-mode is not supported. + * 0: Normal execution + * 1: Raising exceptions + */ +#define CSR_MSTATUS_TW_MASK (0x200000UL) +#define CSR_MSTATUS_TW_SHIFT (21U) +#define CSR_MSTATUS_TW_SET(x) (((uint32_t)(x) << CSR_MSTATUS_TW_SHIFT) & CSR_MSTATUS_TW_MASK) +#define CSR_MSTATUS_TW_GET(x) (((uint32_t)(x) & CSR_MSTATUS_TW_MASK) >> CSR_MSTATUS_TW_SHIFT) + +/* + * TVM (RW) + * + * TVM controls whether performing certain virtual memory operations in S-mode will raise illegal instruction exceptions. The operations include accessing the satp register and executing the SFENCE.VMA instruction. It is hardwired to 0 when S-mode is not supported. + * 0:Normal execution + * 1:Raising exceptions + */ +#define CSR_MSTATUS_TVM_MASK (0x100000UL) +#define CSR_MSTATUS_TVM_SHIFT (20U) +#define CSR_MSTATUS_TVM_SET(x) (((uint32_t)(x) << CSR_MSTATUS_TVM_SHIFT) & CSR_MSTATUS_TVM_MASK) +#define CSR_MSTATUS_TVM_GET(x) (((uint32_t)(x) & CSR_MSTATUS_TVM_MASK) >> CSR_MSTATUS_TVM_SHIFT) + +/* + * MXR (RW) + * + * MXR controls whether execute-only pages are readable. It has no effect when page-based virtual memory is not in effect + * 0:Execute-only pages are not readable + * 1:Execute-only pages are readable + */ +#define CSR_MSTATUS_MXR_MASK (0x80000UL) +#define CSR_MSTATUS_MXR_SHIFT (19U) +#define CSR_MSTATUS_MXR_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MXR_SHIFT) & CSR_MSTATUS_MXR_MASK) +#define CSR_MSTATUS_MXR_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MXR_MASK) >> CSR_MSTATUS_MXR_SHIFT) + +/* + * SUM (RW) + * + * SUM controls whether a S-mode load/store instruction to a user accessible page is allowed or not when page translation is enabled. It is in effect in two scenarios: (a) M-mode with MPRV=1 and MPP=S, and (b) in S-mode. It has no effect when page-based virtual memory is not in effect. A page is user accessible when the U bit of the corresponding PTE entry is 1. It is hardwired to 0 when S-mode is not supported. + * 0:Not Allowed + * 1:Allowed + */ +#define CSR_MSTATUS_SUM_MASK (0x40000UL) +#define CSR_MSTATUS_SUM_SHIFT (18U) +#define CSR_MSTATUS_SUM_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SUM_SHIFT) & CSR_MSTATUS_SUM_MASK) +#define CSR_MSTATUS_SUM_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SUM_MASK) >> CSR_MSTATUS_SUM_SHIFT) + +/* + * MPRV (RW) + * + * When the MPRV bit is set, the memory access privilege for load and store are specified by the MPP field. When U-mode is not available, this field is hardwired to 0. + */ +#define CSR_MSTATUS_MPRV_MASK (0x20000UL) +#define CSR_MSTATUS_MPRV_SHIFT (17U) +#define CSR_MSTATUS_MPRV_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPRV_SHIFT) & CSR_MSTATUS_MPRV_MASK) +#define CSR_MSTATUS_MPRV_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPRV_MASK) >> CSR_MSTATUS_MPRV_SHIFT) + +/* + * XS (RO) + * + * XS holds the status of the architectural states (ACE registers) of ACE instructions. The value of this field is zero if ACE extension is not configured. This field is primarily managed by software. The processor hardware assists the state managements in two regards: + * Illegal instruction exceptions are triggered when XS is Off. + * XS is updated to the Dirty state with the execution of ACE instructions when XS is not Off. Changing the setting of this field has no effect on the contents of ACE states. In particular, setting XS to Off does not destroy the states, nor does setting XS to Initial clear the contents. + * 0:Off + * 1:Initial + * 2:Clean + * 3:Dirty + */ +#define CSR_MSTATUS_XS_MASK (0x18000UL) +#define CSR_MSTATUS_XS_SHIFT (15U) +#define CSR_MSTATUS_XS_GET(x) (((uint32_t)(x) & CSR_MSTATUS_XS_MASK) >> CSR_MSTATUS_XS_SHIFT) + +/* + * FS (RW) + * + * FS holds the status of the architectural states of the floating-point unit, including the fcsr CSR and f0 – f31 floating-point data registers. The value of this field is zero and read-only if the processor does not have FPU. This field is primarily managed by software. The processor hardware assists the state + * managements in two regards: + * Attempts to access fcsr or any f register raise an illegal-instruction exception when FS is Off. + * FS is updated to the Dirty state with the execution of any instruction that updates fcsr or any f register when FS is Initial or Clean. Changing the setting of this field has no effect on the contents of the floating-point register states. In particular, setting FS to Off does not destroy the states, nor does setting FS to Initial clear the contents. + * 0:Off + * 1:Initial + * 2:Clean + * 3:Dirty + */ +#define CSR_MSTATUS_FS_MASK (0x6000U) +#define CSR_MSTATUS_FS_SHIFT (13U) +#define CSR_MSTATUS_FS_SET(x) (((uint32_t)(x) << CSR_MSTATUS_FS_SHIFT) & CSR_MSTATUS_FS_MASK) +#define CSR_MSTATUS_FS_GET(x) (((uint32_t)(x) & CSR_MSTATUS_FS_MASK) >> CSR_MSTATUS_FS_SHIFT) + +/* + * MPP (RW) + * + * MPP holds the privilege mode prior to a trap. Encoding for privilege mode is described in Table5. When U-mode is not available, this field is hardwired to 3. + */ +#define CSR_MSTATUS_MPP_MASK (0x1800U) +#define CSR_MSTATUS_MPP_SHIFT (11U) +#define CSR_MSTATUS_MPP_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPP_SHIFT) & CSR_MSTATUS_MPP_MASK) +#define CSR_MSTATUS_MPP_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPP_MASK) >> CSR_MSTATUS_MPP_SHIFT) + +/* + * SPP (RW) + * + * SPP holds the privilege mode prior to a trap. Encoding is 1 for S-mode and 0 for U-mode. + */ +#define CSR_MSTATUS_SPP_MASK (0x100U) +#define CSR_MSTATUS_SPP_SHIFT (8U) +#define CSR_MSTATUS_SPP_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SPP_SHIFT) & CSR_MSTATUS_SPP_MASK) +#define CSR_MSTATUS_SPP_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SPP_MASK) >> CSR_MSTATUS_SPP_SHIFT) + +/* + * MPIE (RW) + * + * MPIE holds the value of the MIE bit prior to a trap. + */ +#define CSR_MSTATUS_MPIE_MASK (0x80U) +#define CSR_MSTATUS_MPIE_SHIFT (7U) +#define CSR_MSTATUS_MPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPIE_SHIFT) & CSR_MSTATUS_MPIE_MASK) +#define CSR_MSTATUS_MPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPIE_MASK) >> CSR_MSTATUS_MPIE_SHIFT) + +/* + * SPIE (RW) + * + * SPIE holds the value of the SIE bit prior to a trap. + */ +#define CSR_MSTATUS_SPIE_MASK (0x20U) +#define CSR_MSTATUS_SPIE_SHIFT (5U) +#define CSR_MSTATUS_SPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SPIE_SHIFT) & CSR_MSTATUS_SPIE_MASK) +#define CSR_MSTATUS_SPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SPIE_MASK) >> CSR_MSTATUS_SPIE_SHIFT) + +/* + * UPIE (RW) + * + * UPIE holds the value of the UIE bit prior to a trap. + */ +#define CSR_MSTATUS_UPIE_MASK (0x10U) +#define CSR_MSTATUS_UPIE_SHIFT (4U) +#define CSR_MSTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_UPIE_SHIFT) & CSR_MSTATUS_UPIE_MASK) +#define CSR_MSTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_UPIE_MASK) >> CSR_MSTATUS_UPIE_SHIFT) + +/* + * MIE (RW) + * + * M mode interrupt enable bit. + * 0: Disabled + * 1: Enabled + */ +#define CSR_MSTATUS_MIE_MASK (0x8U) +#define CSR_MSTATUS_MIE_SHIFT (3U) +#define CSR_MSTATUS_MIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MIE_SHIFT) & CSR_MSTATUS_MIE_MASK) +#define CSR_MSTATUS_MIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MIE_MASK) >> CSR_MSTATUS_MIE_SHIFT) + +/* + * SIE (RW) + * + * S mode interrupt enable bit. + * 0: Disabled + * 1: Enabled + */ +#define CSR_MSTATUS_SIE_MASK (0x2U) +#define CSR_MSTATUS_SIE_SHIFT (1U) +#define CSR_MSTATUS_SIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SIE_SHIFT) & CSR_MSTATUS_SIE_MASK) +#define CSR_MSTATUS_SIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SIE_MASK) >> CSR_MSTATUS_SIE_SHIFT) + +/* + * UIE (RW) + * + * U mode interrupt enable bit. + * 0: Disabled + * 1: Enabled + */ +#define CSR_MSTATUS_UIE_MASK (0x1U) +#define CSR_MSTATUS_UIE_SHIFT (0U) +#define CSR_MSTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_UIE_SHIFT) & CSR_MSTATUS_UIE_MASK) +#define CSR_MSTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_UIE_MASK) >> CSR_MSTATUS_UIE_SHIFT) + +/* Bitfield definition for register: MISA */ +/* + * BASE (RO) + * + * The general-purpose register width of the native base integer ISA. + * 0:Reserved + * 1:32 + * 2:64 + * 3:128 + */ +#define CSR_MISA_BASE_MASK (0xC0000000UL) +#define CSR_MISA_BASE_SHIFT (30U) +#define CSR_MISA_BASE_GET(x) (((uint32_t)(x) & CSR_MISA_BASE_MASK) >> CSR_MISA_BASE_SHIFT) + +/* + * Z (RO) + * + * Reserved + */ +#define CSR_MISA_Z_MASK (0x2000000UL) +#define CSR_MISA_Z_SHIFT (25U) +#define CSR_MISA_Z_GET(x) (((uint32_t)(x) & CSR_MISA_Z_MASK) >> CSR_MISA_Z_SHIFT) + +/* + * Y (RO) + * + * Reserved + */ +#define CSR_MISA_Y_MASK (0x1000000UL) +#define CSR_MISA_Y_SHIFT (24U) +#define CSR_MISA_Y_GET(x) (((uint32_t)(x) & CSR_MISA_Y_MASK) >> CSR_MISA_Y_SHIFT) + +/* + * X (RO) + * + * Non-standard extensions present + */ +#define CSR_MISA_X_MASK (0x800000UL) +#define CSR_MISA_X_SHIFT (23U) +#define CSR_MISA_X_GET(x) (((uint32_t)(x) & CSR_MISA_X_MASK) >> CSR_MISA_X_SHIFT) + +/* + * W (RO) + * + * Reserved + */ +#define CSR_MISA_W_MASK (0x400000UL) +#define CSR_MISA_W_SHIFT (22U) +#define CSR_MISA_W_GET(x) (((uint32_t)(x) & CSR_MISA_W_MASK) >> CSR_MISA_W_SHIFT) + +/* + * V (RO) + * + * Tentatively reserved for Vector extension + */ +#define CSR_MISA_V_MASK (0x200000UL) +#define CSR_MISA_V_SHIFT (21U) +#define CSR_MISA_V_GET(x) (((uint32_t)(x) & CSR_MISA_V_MASK) >> CSR_MISA_V_SHIFT) + +/* + * U (RO) + * + * User mode implemented + * 0:Machine + * 1:Machine + User / Machine + Supervisor + User + */ +#define CSR_MISA_U_MASK (0x100000UL) +#define CSR_MISA_U_SHIFT (20U) +#define CSR_MISA_U_GET(x) (((uint32_t)(x) & CSR_MISA_U_MASK) >> CSR_MISA_U_SHIFT) + +/* + * T (RO) + * + * Tentatively reserved for Transactional Memory extension + */ +#define CSR_MISA_T_MASK (0x80000UL) +#define CSR_MISA_T_SHIFT (19U) +#define CSR_MISA_T_GET(x) (((uint32_t)(x) & CSR_MISA_T_MASK) >> CSR_MISA_T_SHIFT) + +/* + * S (RO) + * + * Supervisor mode implemented + * 0:Machine / Machine + User + * 1:Machine + Supervisor + User + */ +#define CSR_MISA_S_MASK (0x40000UL) +#define CSR_MISA_S_SHIFT (18U) +#define CSR_MISA_S_GET(x) (((uint32_t)(x) & CSR_MISA_S_MASK) >> CSR_MISA_S_SHIFT) + +/* + * R (RO) + * + * Reserved + */ +#define CSR_MISA_R_MASK (0x20000UL) +#define CSR_MISA_R_SHIFT (17U) +#define CSR_MISA_R_GET(x) (((uint32_t)(x) & CSR_MISA_R_MASK) >> CSR_MISA_R_SHIFT) + +/* + * Q (RO) + * + * Quad-precision floating-point extension + */ +#define CSR_MISA_Q_MASK (0x10000UL) +#define CSR_MISA_Q_SHIFT (16U) +#define CSR_MISA_Q_GET(x) (((uint32_t)(x) & CSR_MISA_Q_MASK) >> CSR_MISA_Q_SHIFT) + +/* + * P (RO) + * + * Tentatively reserved for Packed-SIMD extension + */ +#define CSR_MISA_P_MASK (0x8000U) +#define CSR_MISA_P_SHIFT (15U) +#define CSR_MISA_P_GET(x) (((uint32_t)(x) & CSR_MISA_P_MASK) >> CSR_MISA_P_SHIFT) + +/* + * O (RO) + * + * Reserved + */ +#define CSR_MISA_O_MASK (0x4000U) +#define CSR_MISA_O_SHIFT (14U) +#define CSR_MISA_O_GET(x) (((uint32_t)(x) & CSR_MISA_O_MASK) >> CSR_MISA_O_SHIFT) + +/* + * N (RO) + * + * User-level interrupts supported + * 0:no + * 1:yes + */ +#define CSR_MISA_N_MASK (0x2000U) +#define CSR_MISA_N_SHIFT (13U) +#define CSR_MISA_N_GET(x) (((uint32_t)(x) & CSR_MISA_N_MASK) >> CSR_MISA_N_SHIFT) + +/* + * M (RO) + * + * Integer Multiply/Divide extension + */ +#define CSR_MISA_M_MASK (0x1000U) +#define CSR_MISA_M_SHIFT (12U) +#define CSR_MISA_M_GET(x) (((uint32_t)(x) & CSR_MISA_M_MASK) >> CSR_MISA_M_SHIFT) + +/* + * L (RO) + * + * Tentatively reserved for Decimal Floating-Point extension + */ +#define CSR_MISA_L_MASK (0x800U) +#define CSR_MISA_L_SHIFT (11U) +#define CSR_MISA_L_GET(x) (((uint32_t)(x) & CSR_MISA_L_MASK) >> CSR_MISA_L_SHIFT) + +/* + * K (RO) + * + * Reserved + */ +#define CSR_MISA_K_MASK (0x400U) +#define CSR_MISA_K_SHIFT (10U) +#define CSR_MISA_K_GET(x) (((uint32_t)(x) & CSR_MISA_K_MASK) >> CSR_MISA_K_SHIFT) + +/* + * J (RO) + * + * Tentatively reserved for Dynamically Translated Languages extension + */ +#define CSR_MISA_J_MASK (0x200U) +#define CSR_MISA_J_SHIFT (9U) +#define CSR_MISA_J_GET(x) (((uint32_t)(x) & CSR_MISA_J_MASK) >> CSR_MISA_J_SHIFT) + +/* + * I (RO) + * + * RV32I/64I/128I base ISA + */ +#define CSR_MISA_I_MASK (0x100U) +#define CSR_MISA_I_SHIFT (8U) +#define CSR_MISA_I_GET(x) (((uint32_t)(x) & CSR_MISA_I_MASK) >> CSR_MISA_I_SHIFT) + +/* + * H (RO) + * + * Reserved + */ +#define CSR_MISA_H_MASK (0x80U) +#define CSR_MISA_H_SHIFT (7U) +#define CSR_MISA_H_GET(x) (((uint32_t)(x) & CSR_MISA_H_MASK) >> CSR_MISA_H_SHIFT) + +/* + * G (RO) + * + * Additional standard extensions present + */ +#define CSR_MISA_G_MASK (0x40U) +#define CSR_MISA_G_SHIFT (6U) +#define CSR_MISA_G_GET(x) (((uint32_t)(x) & CSR_MISA_G_MASK) >> CSR_MISA_G_SHIFT) + +/* + * F (RO) + * + * Single-precision floating-point extension + * 0:none + * 1:double+single precision / single precision + */ +#define CSR_MISA_F_MASK (0x20U) +#define CSR_MISA_F_SHIFT (5U) +#define CSR_MISA_F_GET(x) (((uint32_t)(x) & CSR_MISA_F_MASK) >> CSR_MISA_F_SHIFT) + +/* + * E (RO) + * + * RV32E base ISA + */ +#define CSR_MISA_E_MASK (0x10U) +#define CSR_MISA_E_SHIFT (4U) +#define CSR_MISA_E_GET(x) (((uint32_t)(x) & CSR_MISA_E_MASK) >> CSR_MISA_E_SHIFT) + +/* + * D (RO) + * + * Double-precision floating-point extension + * 0:single precision / none + * 1:double+single precision + */ +#define CSR_MISA_D_MASK (0x8U) +#define CSR_MISA_D_SHIFT (3U) +#define CSR_MISA_D_GET(x) (((uint32_t)(x) & CSR_MISA_D_MASK) >> CSR_MISA_D_SHIFT) + +/* + * C (RO) + * + * Compressed extension + */ +#define CSR_MISA_C_MASK (0x4U) +#define CSR_MISA_C_SHIFT (2U) +#define CSR_MISA_C_GET(x) (((uint32_t)(x) & CSR_MISA_C_MASK) >> CSR_MISA_C_SHIFT) + +/* + * B (RO) + * + * Tentatively reserved for Bit operations extension + */ +#define CSR_MISA_B_MASK (0x2U) +#define CSR_MISA_B_SHIFT (1U) +#define CSR_MISA_B_GET(x) (((uint32_t)(x) & CSR_MISA_B_MASK) >> CSR_MISA_B_SHIFT) + +/* + * A (RO) + * + * Atomic extension + * 0:no + * 1:yes + */ +#define CSR_MISA_A_MASK (0x1U) +#define CSR_MISA_A_SHIFT (0U) +#define CSR_MISA_A_GET(x) (((uint32_t)(x) & CSR_MISA_A_MASK) >> CSR_MISA_A_SHIFT) + +/* Bitfield definition for register: MEDELEG */ +/* + * SPF (RW) + * + * SPF indicates whether a Store/AMO Page Fault exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_SPF_MASK (0x8000U) +#define CSR_MEDELEG_SPF_SHIFT (15U) +#define CSR_MEDELEG_SPF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SPF_SHIFT) & CSR_MEDELEG_SPF_MASK) +#define CSR_MEDELEG_SPF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SPF_MASK) >> CSR_MEDELEG_SPF_SHIFT) + +/* + * LPF (RW) + * + * LPF indicates whether a Load Page Fault exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_LPF_MASK (0x2000U) +#define CSR_MEDELEG_LPF_SHIFT (13U) +#define CSR_MEDELEG_LPF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_LPF_SHIFT) & CSR_MEDELEG_LPF_MASK) +#define CSR_MEDELEG_LPF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_LPF_MASK) >> CSR_MEDELEG_LPF_SHIFT) + +/* + * IPF (RW) + * + * IPF indicates whether an Instruction Page Fault exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_IPF_MASK (0x1000U) +#define CSR_MEDELEG_IPF_SHIFT (12U) +#define CSR_MEDELEG_IPF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_IPF_SHIFT) & CSR_MEDELEG_IPF_MASK) +#define CSR_MEDELEG_IPF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_IPF_MASK) >> CSR_MEDELEG_IPF_SHIFT) + +/* + * SEC (RW) + * + * SEC indicates whether an exception triggered by environment call from S-mode will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_SEC_MASK (0x200U) +#define CSR_MEDELEG_SEC_SHIFT (9U) +#define CSR_MEDELEG_SEC_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SEC_SHIFT) & CSR_MEDELEG_SEC_MASK) +#define CSR_MEDELEG_SEC_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SEC_MASK) >> CSR_MEDELEG_SEC_SHIFT) + +/* + * UEC (RW) + * + * UEC indicates whether an exception triggered by environment call from U-mode will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_UEC_MASK (0x100U) +#define CSR_MEDELEG_UEC_SHIFT (8U) +#define CSR_MEDELEG_UEC_SET(x) (((uint32_t)(x) << CSR_MEDELEG_UEC_SHIFT) & CSR_MEDELEG_UEC_MASK) +#define CSR_MEDELEG_UEC_GET(x) (((uint32_t)(x) & CSR_MEDELEG_UEC_MASK) >> CSR_MEDELEG_UEC_SHIFT) + +/* + * SAF (RW) + * + * SAF indicates whether a Store/AMO Access Fault exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_SAF_MASK (0x80U) +#define CSR_MEDELEG_SAF_SHIFT (7U) +#define CSR_MEDELEG_SAF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SAF_SHIFT) & CSR_MEDELEG_SAF_MASK) +#define CSR_MEDELEG_SAF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SAF_MASK) >> CSR_MEDELEG_SAF_SHIFT) + +/* + * SAM (RW) + * + * SAM indicates whether a Store/AMO Address Misaligned exception will be delegated to S-mode + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_SAM_MASK (0x40U) +#define CSR_MEDELEG_SAM_SHIFT (6U) +#define CSR_MEDELEG_SAM_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SAM_SHIFT) & CSR_MEDELEG_SAM_MASK) +#define CSR_MEDELEG_SAM_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SAM_MASK) >> CSR_MEDELEG_SAM_SHIFT) + +/* + * LAF (RW) + * + * LAF indicates whether a Load Access Fault exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_LAF_MASK (0x20U) +#define CSR_MEDELEG_LAF_SHIFT (5U) +#define CSR_MEDELEG_LAF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_LAF_SHIFT) & CSR_MEDELEG_LAF_MASK) +#define CSR_MEDELEG_LAF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_LAF_MASK) >> CSR_MEDELEG_LAF_SHIFT) + +/* + * LAM (RW) + * + * LAM indicates whether a Load Address Misaligned exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_LAM_MASK (0x10U) +#define CSR_MEDELEG_LAM_SHIFT (4U) +#define CSR_MEDELEG_LAM_SET(x) (((uint32_t)(x) << CSR_MEDELEG_LAM_SHIFT) & CSR_MEDELEG_LAM_MASK) +#define CSR_MEDELEG_LAM_GET(x) (((uint32_t)(x) & CSR_MEDELEG_LAM_MASK) >> CSR_MEDELEG_LAM_SHIFT) + +/* + * II (RW) + * + * II indicates whether an Illegal Instruction exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_II_MASK (0x4U) +#define CSR_MEDELEG_II_SHIFT (2U) +#define CSR_MEDELEG_II_SET(x) (((uint32_t)(x) << CSR_MEDELEG_II_SHIFT) & CSR_MEDELEG_II_MASK) +#define CSR_MEDELEG_II_GET(x) (((uint32_t)(x) & CSR_MEDELEG_II_MASK) >> CSR_MEDELEG_II_SHIFT) + +/* + * IAF (RW) + * + * IAF indicates whether an Instruction Access Fault exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_IAF_MASK (0x2U) +#define CSR_MEDELEG_IAF_SHIFT (1U) +#define CSR_MEDELEG_IAF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_IAF_SHIFT) & CSR_MEDELEG_IAF_MASK) +#define CSR_MEDELEG_IAF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_IAF_MASK) >> CSR_MEDELEG_IAF_SHIFT) + +/* + * IAM (RW) + * + * IAM indicates whether an Instruction Address Misaligned exception will be delegated to S-Mode + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_IAM_MASK (0x1U) +#define CSR_MEDELEG_IAM_SHIFT (0U) +#define CSR_MEDELEG_IAM_SET(x) (((uint32_t)(x) << CSR_MEDELEG_IAM_SHIFT) & CSR_MEDELEG_IAM_MASK) +#define CSR_MEDELEG_IAM_GET(x) (((uint32_t)(x) & CSR_MEDELEG_IAM_MASK) >> CSR_MEDELEG_IAM_SHIFT) + +/* Bitfield definition for register: MIDELEG */ +/* + * SEI (RW) + * + * SEI indicates whether an S-mode external interrupt will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MIDELEG_SEI_MASK (0x200U) +#define CSR_MIDELEG_SEI_SHIFT (9U) +#define CSR_MIDELEG_SEI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_SEI_SHIFT) & CSR_MIDELEG_SEI_MASK) +#define CSR_MIDELEG_SEI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_SEI_MASK) >> CSR_MIDELEG_SEI_SHIFT) + +/* + * UEI (RW) + * + * UEI indicates whether an U-mode external interrupt will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MIDELEG_UEI_MASK (0x100U) +#define CSR_MIDELEG_UEI_SHIFT (8U) +#define CSR_MIDELEG_UEI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_UEI_SHIFT) & CSR_MIDELEG_UEI_MASK) +#define CSR_MIDELEG_UEI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_UEI_MASK) >> CSR_MIDELEG_UEI_SHIFT) + +/* + * STI (RW) + * + * STI indicates whether an S-mode timer interrupt will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MIDELEG_STI_MASK (0x20U) +#define CSR_MIDELEG_STI_SHIFT (5U) +#define CSR_MIDELEG_STI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_STI_SHIFT) & CSR_MIDELEG_STI_MASK) +#define CSR_MIDELEG_STI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_STI_MASK) >> CSR_MIDELEG_STI_SHIFT) + +/* + * UTI (RW) + * + * UTI indicates whether an U-mode timer interrupt will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MIDELEG_UTI_MASK (0x10U) +#define CSR_MIDELEG_UTI_SHIFT (4U) +#define CSR_MIDELEG_UTI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_UTI_SHIFT) & CSR_MIDELEG_UTI_MASK) +#define CSR_MIDELEG_UTI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_UTI_MASK) >> CSR_MIDELEG_UTI_SHIFT) + +/* + * SSI (RW) + * + * SSI indicates whether an S-mode software interrupt will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MIDELEG_SSI_MASK (0x2U) +#define CSR_MIDELEG_SSI_SHIFT (1U) +#define CSR_MIDELEG_SSI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_SSI_SHIFT) & CSR_MIDELEG_SSI_MASK) +#define CSR_MIDELEG_SSI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_SSI_MASK) >> CSR_MIDELEG_SSI_SHIFT) + +/* + * USI (RW) + * + * USI indicates whether an U-mode software interrupt will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MIDELEG_USI_MASK (0x1U) +#define CSR_MIDELEG_USI_SHIFT (0U) +#define CSR_MIDELEG_USI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_USI_SHIFT) & CSR_MIDELEG_USI_MASK) +#define CSR_MIDELEG_USI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_USI_MASK) >> CSR_MIDELEG_USI_SHIFT) + +/* Bitfield definition for register: MIE */ +/* + * PMOVI (RW) + * + * Performance monitor overflow local interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_PMOVI_MASK (0x40000UL) +#define CSR_MIE_PMOVI_SHIFT (18U) +#define CSR_MIE_PMOVI_SET(x) (((uint32_t)(x) << CSR_MIE_PMOVI_SHIFT) & CSR_MIE_PMOVI_MASK) +#define CSR_MIE_PMOVI_GET(x) (((uint32_t)(x) & CSR_MIE_PMOVI_MASK) >> CSR_MIE_PMOVI_SHIFT) + +/* + * BWEI (RW) + * + * Bus read/write transaction error local interrupt enable bit. The processor may receive bus errors on load/store instructions or cache writebacks. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_BWEI_MASK (0x20000UL) +#define CSR_MIE_BWEI_SHIFT (17U) +#define CSR_MIE_BWEI_SET(x) (((uint32_t)(x) << CSR_MIE_BWEI_SHIFT) & CSR_MIE_BWEI_MASK) +#define CSR_MIE_BWEI_GET(x) (((uint32_t)(x) & CSR_MIE_BWEI_MASK) >> CSR_MIE_BWEI_SHIFT) + +/* + * IMECCI (RW) + * + * Imprecise ECC error local interrupt enable bit. The processor may receive imprecise ECC errors on slave port accesses or cache writebacks. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_IMECCI_MASK (0x10000UL) +#define CSR_MIE_IMECCI_SHIFT (16U) +#define CSR_MIE_IMECCI_SET(x) (((uint32_t)(x) << CSR_MIE_IMECCI_SHIFT) & CSR_MIE_IMECCI_MASK) +#define CSR_MIE_IMECCI_GET(x) (((uint32_t)(x) & CSR_MIE_IMECCI_MASK) >> CSR_MIE_IMECCI_SHIFT) + +/* + * MEIE (RW) + * + * M mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_MEIE_MASK (0x800U) +#define CSR_MIE_MEIE_SHIFT (11U) +#define CSR_MIE_MEIE_SET(x) (((uint32_t)(x) << CSR_MIE_MEIE_SHIFT) & CSR_MIE_MEIE_MASK) +#define CSR_MIE_MEIE_GET(x) (((uint32_t)(x) & CSR_MIE_MEIE_MASK) >> CSR_MIE_MEIE_SHIFT) + +/* + * SEIE (RW) + * + * S mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_SEIE_MASK (0x200U) +#define CSR_MIE_SEIE_SHIFT (9U) +#define CSR_MIE_SEIE_SET(x) (((uint32_t)(x) << CSR_MIE_SEIE_SHIFT) & CSR_MIE_SEIE_MASK) +#define CSR_MIE_SEIE_GET(x) (((uint32_t)(x) & CSR_MIE_SEIE_MASK) >> CSR_MIE_SEIE_SHIFT) + +/* + * UEIE (RW) + * + * U mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_UEIE_MASK (0x100U) +#define CSR_MIE_UEIE_SHIFT (8U) +#define CSR_MIE_UEIE_SET(x) (((uint32_t)(x) << CSR_MIE_UEIE_SHIFT) & CSR_MIE_UEIE_MASK) +#define CSR_MIE_UEIE_GET(x) (((uint32_t)(x) & CSR_MIE_UEIE_MASK) >> CSR_MIE_UEIE_SHIFT) + +/* + * MTIE (RW) + * + * M mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_MTIE_MASK (0x80U) +#define CSR_MIE_MTIE_SHIFT (7U) +#define CSR_MIE_MTIE_SET(x) (((uint32_t)(x) << CSR_MIE_MTIE_SHIFT) & CSR_MIE_MTIE_MASK) +#define CSR_MIE_MTIE_GET(x) (((uint32_t)(x) & CSR_MIE_MTIE_MASK) >> CSR_MIE_MTIE_SHIFT) + +/* + * STIE (RW) + * + * S mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_STIE_MASK (0x20U) +#define CSR_MIE_STIE_SHIFT (5U) +#define CSR_MIE_STIE_SET(x) (((uint32_t)(x) << CSR_MIE_STIE_SHIFT) & CSR_MIE_STIE_MASK) +#define CSR_MIE_STIE_GET(x) (((uint32_t)(x) & CSR_MIE_STIE_MASK) >> CSR_MIE_STIE_SHIFT) + +/* + * UTIE (RW) + * + * U mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_UTIE_MASK (0x10U) +#define CSR_MIE_UTIE_SHIFT (4U) +#define CSR_MIE_UTIE_SET(x) (((uint32_t)(x) << CSR_MIE_UTIE_SHIFT) & CSR_MIE_UTIE_MASK) +#define CSR_MIE_UTIE_GET(x) (((uint32_t)(x) & CSR_MIE_UTIE_MASK) >> CSR_MIE_UTIE_SHIFT) + +/* + * MSIE (RW) + * + * M mode software interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_MSIE_MASK (0x8U) +#define CSR_MIE_MSIE_SHIFT (3U) +#define CSR_MIE_MSIE_SET(x) (((uint32_t)(x) << CSR_MIE_MSIE_SHIFT) & CSR_MIE_MSIE_MASK) +#define CSR_MIE_MSIE_GET(x) (((uint32_t)(x) & CSR_MIE_MSIE_MASK) >> CSR_MIE_MSIE_SHIFT) + +/* + * SSIE (RW) + * + * S mode software interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_SSIE_MASK (0x2U) +#define CSR_MIE_SSIE_SHIFT (1U) +#define CSR_MIE_SSIE_SET(x) (((uint32_t)(x) << CSR_MIE_SSIE_SHIFT) & CSR_MIE_SSIE_MASK) +#define CSR_MIE_SSIE_GET(x) (((uint32_t)(x) & CSR_MIE_SSIE_MASK) >> CSR_MIE_SSIE_SHIFT) + +/* + * USIE (RW) + * + * U mode software interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_USIE_MASK (0x1U) +#define CSR_MIE_USIE_SHIFT (0U) +#define CSR_MIE_USIE_SET(x) (((uint32_t)(x) << CSR_MIE_USIE_SHIFT) & CSR_MIE_USIE_MASK) +#define CSR_MIE_USIE_GET(x) (((uint32_t)(x) & CSR_MIE_USIE_MASK) >> CSR_MIE_USIE_SHIFT) + +/* Bitfield definition for register: MTVEC */ +/* + * BASE_31_2 (RW) + * + * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode + */ +#define CSR_MTVEC_BASE_31_2_MASK (0xFFFFFFFCUL) +#define CSR_MTVEC_BASE_31_2_SHIFT (2U) +#define CSR_MTVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_MTVEC_BASE_31_2_SHIFT) & CSR_MTVEC_BASE_31_2_MASK) +#define CSR_MTVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_MTVEC_BASE_31_2_MASK) >> CSR_MTVEC_BASE_31_2_SHIFT) + +/* Bitfield definition for register: MCOUNTEREN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_HPM6_MASK (0x40U) +#define CSR_MCOUNTEREN_HPM6_SHIFT (6U) +#define CSR_MCOUNTEREN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM6_SHIFT) & CSR_MCOUNTEREN_HPM6_MASK) +#define CSR_MCOUNTEREN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM6_MASK) >> CSR_MCOUNTEREN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_HPM5_MASK (0x20U) +#define CSR_MCOUNTEREN_HPM5_SHIFT (5U) +#define CSR_MCOUNTEREN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM5_SHIFT) & CSR_MCOUNTEREN_HPM5_MASK) +#define CSR_MCOUNTEREN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM5_MASK) >> CSR_MCOUNTEREN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_HPM4_MASK (0x10U) +#define CSR_MCOUNTEREN_HPM4_SHIFT (4U) +#define CSR_MCOUNTEREN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM4_SHIFT) & CSR_MCOUNTEREN_HPM4_MASK) +#define CSR_MCOUNTEREN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM4_MASK) >> CSR_MCOUNTEREN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_HPM3_MASK (0x8U) +#define CSR_MCOUNTEREN_HPM3_SHIFT (3U) +#define CSR_MCOUNTEREN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM3_SHIFT) & CSR_MCOUNTEREN_HPM3_MASK) +#define CSR_MCOUNTEREN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM3_MASK) >> CSR_MCOUNTEREN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_IR_MASK (0x4U) +#define CSR_MCOUNTEREN_IR_SHIFT (2U) +#define CSR_MCOUNTEREN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_IR_SHIFT) & CSR_MCOUNTEREN_IR_MASK) +#define CSR_MCOUNTEREN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_IR_MASK) >> CSR_MCOUNTEREN_IR_SHIFT) + +/* + * TM (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_TM_MASK (0x2U) +#define CSR_MCOUNTEREN_TM_SHIFT (1U) +#define CSR_MCOUNTEREN_TM_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_TM_SHIFT) & CSR_MCOUNTEREN_TM_MASK) +#define CSR_MCOUNTEREN_TM_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_TM_MASK) >> CSR_MCOUNTEREN_TM_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_CY_MASK (0x1U) +#define CSR_MCOUNTEREN_CY_SHIFT (0U) +#define CSR_MCOUNTEREN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_CY_SHIFT) & CSR_MCOUNTEREN_CY_MASK) +#define CSR_MCOUNTEREN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_CY_MASK) >> CSR_MCOUNTEREN_CY_SHIFT) + +/* Bitfield definition for register: MHPMEVENT3 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT3_SEL_MASK (0x1F0U) +#define CSR_MHPMEVENT3_SEL_SHIFT (4U) +#define CSR_MHPMEVENT3_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT3_SEL_SHIFT) & CSR_MHPMEVENT3_SEL_MASK) +#define CSR_MHPMEVENT3_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT3_SEL_MASK) >> CSR_MHPMEVENT3_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT3_TYPE_MASK (0xFU) +#define CSR_MHPMEVENT3_TYPE_SHIFT (0U) +#define CSR_MHPMEVENT3_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT3_TYPE_SHIFT) & CSR_MHPMEVENT3_TYPE_MASK) +#define CSR_MHPMEVENT3_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT3_TYPE_MASK) >> CSR_MHPMEVENT3_TYPE_SHIFT) + +/* Bitfield definition for register: MHPMEVENT4 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT4_SEL_MASK (0x1F0U) +#define CSR_MHPMEVENT4_SEL_SHIFT (4U) +#define CSR_MHPMEVENT4_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT4_SEL_SHIFT) & CSR_MHPMEVENT4_SEL_MASK) +#define CSR_MHPMEVENT4_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT4_SEL_MASK) >> CSR_MHPMEVENT4_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT4_TYPE_MASK (0xFU) +#define CSR_MHPMEVENT4_TYPE_SHIFT (0U) +#define CSR_MHPMEVENT4_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT4_TYPE_SHIFT) & CSR_MHPMEVENT4_TYPE_MASK) +#define CSR_MHPMEVENT4_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT4_TYPE_MASK) >> CSR_MHPMEVENT4_TYPE_SHIFT) + +/* Bitfield definition for register: MHPMEVENT5 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT5_SEL_MASK (0x1F0U) +#define CSR_MHPMEVENT5_SEL_SHIFT (4U) +#define CSR_MHPMEVENT5_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT5_SEL_SHIFT) & CSR_MHPMEVENT5_SEL_MASK) +#define CSR_MHPMEVENT5_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT5_SEL_MASK) >> CSR_MHPMEVENT5_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT5_TYPE_MASK (0xFU) +#define CSR_MHPMEVENT5_TYPE_SHIFT (0U) +#define CSR_MHPMEVENT5_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT5_TYPE_SHIFT) & CSR_MHPMEVENT5_TYPE_MASK) +#define CSR_MHPMEVENT5_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT5_TYPE_MASK) >> CSR_MHPMEVENT5_TYPE_SHIFT) + +/* Bitfield definition for register: MHPMEVENT6 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT6_SEL_MASK (0x1F0U) +#define CSR_MHPMEVENT6_SEL_SHIFT (4U) +#define CSR_MHPMEVENT6_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT6_SEL_SHIFT) & CSR_MHPMEVENT6_SEL_MASK) +#define CSR_MHPMEVENT6_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT6_SEL_MASK) >> CSR_MHPMEVENT6_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT6_TYPE_MASK (0xFU) +#define CSR_MHPMEVENT6_TYPE_SHIFT (0U) +#define CSR_MHPMEVENT6_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT6_TYPE_SHIFT) & CSR_MHPMEVENT6_TYPE_MASK) +#define CSR_MHPMEVENT6_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT6_TYPE_MASK) >> CSR_MHPMEVENT6_TYPE_SHIFT) + +/* Bitfield definition for register: MSCRATCH */ +/* + * MSCRATCH (RW) + * + * Scratch register storage. + */ +#define CSR_MSCRATCH_MSCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_MSCRATCH_MSCRATCH_SHIFT (0U) +#define CSR_MSCRATCH_MSCRATCH_SET(x) (((uint32_t)(x) << CSR_MSCRATCH_MSCRATCH_SHIFT) & CSR_MSCRATCH_MSCRATCH_MASK) +#define CSR_MSCRATCH_MSCRATCH_GET(x) (((uint32_t)(x) & CSR_MSCRATCH_MSCRATCH_MASK) >> CSR_MSCRATCH_MSCRATCH_SHIFT) + +/* Bitfield definition for register: MEPC */ +/* + * EPC (RW) + * + * Exception program counter. + */ +#define CSR_MEPC_EPC_MASK (0xFFFFFFFEUL) +#define CSR_MEPC_EPC_SHIFT (1U) +#define CSR_MEPC_EPC_SET(x) (((uint32_t)(x) << CSR_MEPC_EPC_SHIFT) & CSR_MEPC_EPC_MASK) +#define CSR_MEPC_EPC_GET(x) (((uint32_t)(x) & CSR_MEPC_EPC_MASK) >> CSR_MEPC_EPC_SHIFT) + +/* Bitfield definition for register: MCAUSE */ +/* + * INTERRUPT (RW) + * + * Interrupt + */ +#define CSR_MCAUSE_INTERRUPT_MASK (0x80000000UL) +#define CSR_MCAUSE_INTERRUPT_SHIFT (31U) +#define CSR_MCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_MCAUSE_INTERRUPT_SHIFT) & CSR_MCAUSE_INTERRUPT_MASK) +#define CSR_MCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_MCAUSE_INTERRUPT_MASK) >> CSR_MCAUSE_INTERRUPT_SHIFT) + +/* + * EXCEPTION_CODE (RW) + * + * Exception code + * When interrupt is 1, the value means: + * 0:User software interrupt + * 1:Supervisor software interrupt + * 3:Machine software interrupt + * 4:User timer interrupt + * 5:Supervisor timer interrupt + * 7:Machine timer interrupt + * 8:User external interrupt + * 9:Supervisor external interrupt + * 11:Machine external interrupt + * 16:Imprecise ECC error interrupt (slave port accesses, D-Cache evictions, and nonblocking load/stores) (M-mode) + * 17:Bus read/write transaction error interrupt (M-mode) + * 18:Performance monitor overflow interrupt (M-mode) + * 256+16:Imprecise ECC error interrupt (slave port accesses, D-Cache evictions, and nonblocking load/stores) (S-mode) + * 256+17:Bus write transaction error interrupt (S-mode) + * 256+18:Performance monitor overflow interrupt (S-mode) + * When interrupt bit is 0, the value means: + * 0:Instruction address misaligned + * 1:Instruction access fault + * 2:Illegal instruction + * 3:Breakpoint + * 4:Load address misaligned + * 5:Load access fault + * 6:Store/AMO address misaligned + * 7:Store/AMO access fault + * 8:Environment call from U-mode + * 9:Environment call from S-mode + * 11:Environment call from M-mode + * 32:Stack overflow exception + * 33:Stack underflow exception + * 40-47:Reserved + */ +#define CSR_MCAUSE_EXCEPTION_CODE_MASK (0xFFFU) +#define CSR_MCAUSE_EXCEPTION_CODE_SHIFT (0U) +#define CSR_MCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_MCAUSE_EXCEPTION_CODE_SHIFT) & CSR_MCAUSE_EXCEPTION_CODE_MASK) +#define CSR_MCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_MCAUSE_EXCEPTION_CODE_MASK) >> CSR_MCAUSE_EXCEPTION_CODE_SHIFT) + +/* Bitfield definition for register: MTVAL */ +/* + * MTVAL (RW) + * + * Exception-specific information for software trap handling. + */ +#define CSR_MTVAL_MTVAL_MASK (0xFFFFFFFFUL) +#define CSR_MTVAL_MTVAL_SHIFT (0U) +#define CSR_MTVAL_MTVAL_SET(x) (((uint32_t)(x) << CSR_MTVAL_MTVAL_SHIFT) & CSR_MTVAL_MTVAL_MASK) +#define CSR_MTVAL_MTVAL_GET(x) (((uint32_t)(x) & CSR_MTVAL_MTVAL_MASK) >> CSR_MTVAL_MTVAL_SHIFT) + +/* Bitfield definition for register: MIP */ +/* + * PMOVI (RW) + * + * Performance monitor overflow local interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_PMOVI_MASK (0x40000UL) +#define CSR_MIP_PMOVI_SHIFT (18U) +#define CSR_MIP_PMOVI_SET(x) (((uint32_t)(x) << CSR_MIP_PMOVI_SHIFT) & CSR_MIP_PMOVI_MASK) +#define CSR_MIP_PMOVI_GET(x) (((uint32_t)(x) & CSR_MIP_PMOVI_MASK) >> CSR_MIP_PMOVI_SHIFT) + +/* + * BWEI (RW) + * + * Bus read/write transaction error local interrupt pending bit. The processor may receive bus errors on load/store instructions or cache writebacks. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_BWEI_MASK (0x20000UL) +#define CSR_MIP_BWEI_SHIFT (17U) +#define CSR_MIP_BWEI_SET(x) (((uint32_t)(x) << CSR_MIP_BWEI_SHIFT) & CSR_MIP_BWEI_MASK) +#define CSR_MIP_BWEI_GET(x) (((uint32_t)(x) & CSR_MIP_BWEI_MASK) >> CSR_MIP_BWEI_SHIFT) + +/* + * IMECCI (RW) + * + * Imprecise ECC error local interrupt enable bit. The processor may receive imprecise ECC errors on slave port accesses or cache writebacks. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_IMECCI_MASK (0x10000UL) +#define CSR_MIP_IMECCI_SHIFT (16U) +#define CSR_MIP_IMECCI_SET(x) (((uint32_t)(x) << CSR_MIP_IMECCI_SHIFT) & CSR_MIP_IMECCI_MASK) +#define CSR_MIP_IMECCI_GET(x) (((uint32_t)(x) & CSR_MIP_IMECCI_MASK) >> CSR_MIP_IMECCI_SHIFT) + +/* + * MEIP (RW) + * + * M mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_MEIP_MASK (0x800U) +#define CSR_MIP_MEIP_SHIFT (11U) +#define CSR_MIP_MEIP_SET(x) (((uint32_t)(x) << CSR_MIP_MEIP_SHIFT) & CSR_MIP_MEIP_MASK) +#define CSR_MIP_MEIP_GET(x) (((uint32_t)(x) & CSR_MIP_MEIP_MASK) >> CSR_MIP_MEIP_SHIFT) + +/* + * SEIP (RW) + * + * S mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_SEIP_MASK (0x200U) +#define CSR_MIP_SEIP_SHIFT (9U) +#define CSR_MIP_SEIP_SET(x) (((uint32_t)(x) << CSR_MIP_SEIP_SHIFT) & CSR_MIP_SEIP_MASK) +#define CSR_MIP_SEIP_GET(x) (((uint32_t)(x) & CSR_MIP_SEIP_MASK) >> CSR_MIP_SEIP_SHIFT) + +/* + * UEIP (RW) + * + * U mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_UEIP_MASK (0x100U) +#define CSR_MIP_UEIP_SHIFT (8U) +#define CSR_MIP_UEIP_SET(x) (((uint32_t)(x) << CSR_MIP_UEIP_SHIFT) & CSR_MIP_UEIP_MASK) +#define CSR_MIP_UEIP_GET(x) (((uint32_t)(x) & CSR_MIP_UEIP_MASK) >> CSR_MIP_UEIP_SHIFT) + +/* + * MTIP (RW) + * + * M mode timer interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_MTIP_MASK (0x80U) +#define CSR_MIP_MTIP_SHIFT (7U) +#define CSR_MIP_MTIP_SET(x) (((uint32_t)(x) << CSR_MIP_MTIP_SHIFT) & CSR_MIP_MTIP_MASK) +#define CSR_MIP_MTIP_GET(x) (((uint32_t)(x) & CSR_MIP_MTIP_MASK) >> CSR_MIP_MTIP_SHIFT) + +/* + * STIP (RW) + * + * S mode timer interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_STIP_MASK (0x20U) +#define CSR_MIP_STIP_SHIFT (5U) +#define CSR_MIP_STIP_SET(x) (((uint32_t)(x) << CSR_MIP_STIP_SHIFT) & CSR_MIP_STIP_MASK) +#define CSR_MIP_STIP_GET(x) (((uint32_t)(x) & CSR_MIP_STIP_MASK) >> CSR_MIP_STIP_SHIFT) + +/* + * UTIP (RW) + * + * U mode timer interrupt pending bit + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_UTIP_MASK (0x10U) +#define CSR_MIP_UTIP_SHIFT (4U) +#define CSR_MIP_UTIP_SET(x) (((uint32_t)(x) << CSR_MIP_UTIP_SHIFT) & CSR_MIP_UTIP_MASK) +#define CSR_MIP_UTIP_GET(x) (((uint32_t)(x) & CSR_MIP_UTIP_MASK) >> CSR_MIP_UTIP_SHIFT) + +/* + * MSIP (RW) + * + * M mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_MSIP_MASK (0x8U) +#define CSR_MIP_MSIP_SHIFT (3U) +#define CSR_MIP_MSIP_SET(x) (((uint32_t)(x) << CSR_MIP_MSIP_SHIFT) & CSR_MIP_MSIP_MASK) +#define CSR_MIP_MSIP_GET(x) (((uint32_t)(x) & CSR_MIP_MSIP_MASK) >> CSR_MIP_MSIP_SHIFT) + +/* + * SSIP (RW) + * + * S mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_SSIP_MASK (0x2U) +#define CSR_MIP_SSIP_SHIFT (1U) +#define CSR_MIP_SSIP_SET(x) (((uint32_t)(x) << CSR_MIP_SSIP_SHIFT) & CSR_MIP_SSIP_MASK) +#define CSR_MIP_SSIP_GET(x) (((uint32_t)(x) & CSR_MIP_SSIP_MASK) >> CSR_MIP_SSIP_SHIFT) + +/* + * USIP (RW) + * + * U mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_USIP_MASK (0x1U) +#define CSR_MIP_USIP_SHIFT (0U) +#define CSR_MIP_USIP_SET(x) (((uint32_t)(x) << CSR_MIP_USIP_SHIFT) & CSR_MIP_USIP_MASK) +#define CSR_MIP_USIP_GET(x) (((uint32_t)(x) & CSR_MIP_USIP_MASK) >> CSR_MIP_USIP_SHIFT) + +/* Bitfield definition for register: PMPCFG0 */ +/* + * PMP3CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG0_PMP3CFG_MASK (0xFF000000UL) +#define CSR_PMPCFG0_PMP3CFG_SHIFT (24U) +#define CSR_PMPCFG0_PMP3CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP3CFG_SHIFT) & CSR_PMPCFG0_PMP3CFG_MASK) +#define CSR_PMPCFG0_PMP3CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP3CFG_MASK) >> CSR_PMPCFG0_PMP3CFG_SHIFT) + +/* + * PMP2CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG0_PMP2CFG_MASK (0xFF0000UL) +#define CSR_PMPCFG0_PMP2CFG_SHIFT (16U) +#define CSR_PMPCFG0_PMP2CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP2CFG_SHIFT) & CSR_PMPCFG0_PMP2CFG_MASK) +#define CSR_PMPCFG0_PMP2CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP2CFG_MASK) >> CSR_PMPCFG0_PMP2CFG_SHIFT) + +/* + * PMP1CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG0_PMP1CFG_MASK (0xFF00U) +#define CSR_PMPCFG0_PMP1CFG_SHIFT (8U) +#define CSR_PMPCFG0_PMP1CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP1CFG_SHIFT) & CSR_PMPCFG0_PMP1CFG_MASK) +#define CSR_PMPCFG0_PMP1CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP1CFG_MASK) >> CSR_PMPCFG0_PMP1CFG_SHIFT) + +/* + * PMP0CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG0_PMP0CFG_MASK (0xFFU) +#define CSR_PMPCFG0_PMP0CFG_SHIFT (0U) +#define CSR_PMPCFG0_PMP0CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP0CFG_SHIFT) & CSR_PMPCFG0_PMP0CFG_MASK) +#define CSR_PMPCFG0_PMP0CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP0CFG_MASK) >> CSR_PMPCFG0_PMP0CFG_SHIFT) + +/* Bitfield definition for register: PMPCFG1 */ +/* + * PMP7CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG1_PMP7CFG_MASK (0xFF000000UL) +#define CSR_PMPCFG1_PMP7CFG_SHIFT (24U) +#define CSR_PMPCFG1_PMP7CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP7CFG_SHIFT) & CSR_PMPCFG1_PMP7CFG_MASK) +#define CSR_PMPCFG1_PMP7CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP7CFG_MASK) >> CSR_PMPCFG1_PMP7CFG_SHIFT) + +/* + * PMP6CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG1_PMP6CFG_MASK (0xFF0000UL) +#define CSR_PMPCFG1_PMP6CFG_SHIFT (16U) +#define CSR_PMPCFG1_PMP6CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP6CFG_SHIFT) & CSR_PMPCFG1_PMP6CFG_MASK) +#define CSR_PMPCFG1_PMP6CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP6CFG_MASK) >> CSR_PMPCFG1_PMP6CFG_SHIFT) + +/* + * PMP5CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG1_PMP5CFG_MASK (0xFF00U) +#define CSR_PMPCFG1_PMP5CFG_SHIFT (8U) +#define CSR_PMPCFG1_PMP5CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP5CFG_SHIFT) & CSR_PMPCFG1_PMP5CFG_MASK) +#define CSR_PMPCFG1_PMP5CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP5CFG_MASK) >> CSR_PMPCFG1_PMP5CFG_SHIFT) + +/* + * PMP4CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG1_PMP4CFG_MASK (0xFFU) +#define CSR_PMPCFG1_PMP4CFG_SHIFT (0U) +#define CSR_PMPCFG1_PMP4CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP4CFG_SHIFT) & CSR_PMPCFG1_PMP4CFG_MASK) +#define CSR_PMPCFG1_PMP4CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP4CFG_MASK) >> CSR_PMPCFG1_PMP4CFG_SHIFT) + +/* Bitfield definition for register: PMPCFG2 */ +/* + * PMP11CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG2_PMP11CFG_MASK (0xFF000000UL) +#define CSR_PMPCFG2_PMP11CFG_SHIFT (24U) +#define CSR_PMPCFG2_PMP11CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP11CFG_SHIFT) & CSR_PMPCFG2_PMP11CFG_MASK) +#define CSR_PMPCFG2_PMP11CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP11CFG_MASK) >> CSR_PMPCFG2_PMP11CFG_SHIFT) + +/* + * PMP10CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG2_PMP10CFG_MASK (0xFF0000UL) +#define CSR_PMPCFG2_PMP10CFG_SHIFT (16U) +#define CSR_PMPCFG2_PMP10CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP10CFG_SHIFT) & CSR_PMPCFG2_PMP10CFG_MASK) +#define CSR_PMPCFG2_PMP10CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP10CFG_MASK) >> CSR_PMPCFG2_PMP10CFG_SHIFT) + +/* + * PMP9CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG2_PMP9CFG_MASK (0xFF00U) +#define CSR_PMPCFG2_PMP9CFG_SHIFT (8U) +#define CSR_PMPCFG2_PMP9CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP9CFG_SHIFT) & CSR_PMPCFG2_PMP9CFG_MASK) +#define CSR_PMPCFG2_PMP9CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP9CFG_MASK) >> CSR_PMPCFG2_PMP9CFG_SHIFT) + +/* + * PMP8CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG2_PMP8CFG_MASK (0xFFU) +#define CSR_PMPCFG2_PMP8CFG_SHIFT (0U) +#define CSR_PMPCFG2_PMP8CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP8CFG_SHIFT) & CSR_PMPCFG2_PMP8CFG_MASK) +#define CSR_PMPCFG2_PMP8CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP8CFG_MASK) >> CSR_PMPCFG2_PMP8CFG_SHIFT) + +/* Bitfield definition for register: PMPCFG3 */ +/* + * PMP15CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG3_PMP15CFG_MASK (0xFF000000UL) +#define CSR_PMPCFG3_PMP15CFG_SHIFT (24U) +#define CSR_PMPCFG3_PMP15CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP15CFG_SHIFT) & CSR_PMPCFG3_PMP15CFG_MASK) +#define CSR_PMPCFG3_PMP15CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP15CFG_MASK) >> CSR_PMPCFG3_PMP15CFG_SHIFT) + +/* + * PMP14CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG3_PMP14CFG_MASK (0xFF0000UL) +#define CSR_PMPCFG3_PMP14CFG_SHIFT (16U) +#define CSR_PMPCFG3_PMP14CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP14CFG_SHIFT) & CSR_PMPCFG3_PMP14CFG_MASK) +#define CSR_PMPCFG3_PMP14CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP14CFG_MASK) >> CSR_PMPCFG3_PMP14CFG_SHIFT) + +/* + * PMP13CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG3_PMP13CFG_MASK (0xFF00U) +#define CSR_PMPCFG3_PMP13CFG_SHIFT (8U) +#define CSR_PMPCFG3_PMP13CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP13CFG_SHIFT) & CSR_PMPCFG3_PMP13CFG_MASK) +#define CSR_PMPCFG3_PMP13CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP13CFG_MASK) >> CSR_PMPCFG3_PMP13CFG_SHIFT) + +/* + * PMP12CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG3_PMP12CFG_MASK (0xFFU) +#define CSR_PMPCFG3_PMP12CFG_SHIFT (0U) +#define CSR_PMPCFG3_PMP12CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP12CFG_SHIFT) & CSR_PMPCFG3_PMP12CFG_MASK) +#define CSR_PMPCFG3_PMP12CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP12CFG_MASK) >> CSR_PMPCFG3_PMP12CFG_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * Register Content : Match Size(Byte) + * aaaa. . . aaa0 8 + * aaaa. . . aa01 16 + * aaaa. . . a011 32 + * . . . . . . + * aa01. . . 1111 2^{XLEN} + * a011. . . 1111 2^{XLEN+1} + * 0111. . . 1111 2^{XLEN+2} + * 1111. . . 1111 2^{XLEN+3*1} + */ +#define CSR_PMPADDR0_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR0_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR0_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR0_PMPADDR_31_2_SHIFT) & CSR_PMPADDR0_PMPADDR_31_2_MASK) +#define CSR_PMPADDR0_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR0_PMPADDR_31_2_MASK) >> CSR_PMPADDR0_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR1_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR1_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR1_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR1_PMPADDR_31_2_SHIFT) & CSR_PMPADDR1_PMPADDR_31_2_MASK) +#define CSR_PMPADDR1_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR1_PMPADDR_31_2_MASK) >> CSR_PMPADDR1_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR2_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR2_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR2_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR2_PMPADDR_31_2_SHIFT) & CSR_PMPADDR2_PMPADDR_31_2_MASK) +#define CSR_PMPADDR2_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR2_PMPADDR_31_2_MASK) >> CSR_PMPADDR2_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR3_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR3_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR3_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR3_PMPADDR_31_2_SHIFT) & CSR_PMPADDR3_PMPADDR_31_2_MASK) +#define CSR_PMPADDR3_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR3_PMPADDR_31_2_MASK) >> CSR_PMPADDR3_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR4_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR4_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR4_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR4_PMPADDR_31_2_SHIFT) & CSR_PMPADDR4_PMPADDR_31_2_MASK) +#define CSR_PMPADDR4_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR4_PMPADDR_31_2_MASK) >> CSR_PMPADDR4_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR5_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR5_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR5_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR5_PMPADDR_31_2_SHIFT) & CSR_PMPADDR5_PMPADDR_31_2_MASK) +#define CSR_PMPADDR5_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR5_PMPADDR_31_2_MASK) >> CSR_PMPADDR5_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR6_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR6_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR6_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR6_PMPADDR_31_2_SHIFT) & CSR_PMPADDR6_PMPADDR_31_2_MASK) +#define CSR_PMPADDR6_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR6_PMPADDR_31_2_MASK) >> CSR_PMPADDR6_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR7_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR7_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR7_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR7_PMPADDR_31_2_SHIFT) & CSR_PMPADDR7_PMPADDR_31_2_MASK) +#define CSR_PMPADDR7_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR7_PMPADDR_31_2_MASK) >> CSR_PMPADDR7_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR8_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR8_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR8_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR8_PMPADDR_31_2_SHIFT) & CSR_PMPADDR8_PMPADDR_31_2_MASK) +#define CSR_PMPADDR8_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR8_PMPADDR_31_2_MASK) >> CSR_PMPADDR8_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR9_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR9_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR9_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR9_PMPADDR_31_2_SHIFT) & CSR_PMPADDR9_PMPADDR_31_2_MASK) +#define CSR_PMPADDR9_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR9_PMPADDR_31_2_MASK) >> CSR_PMPADDR9_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR10_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR10_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR10_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR10_PMPADDR_31_2_SHIFT) & CSR_PMPADDR10_PMPADDR_31_2_MASK) +#define CSR_PMPADDR10_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR10_PMPADDR_31_2_MASK) >> CSR_PMPADDR10_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR11_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR11_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR11_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR11_PMPADDR_31_2_SHIFT) & CSR_PMPADDR11_PMPADDR_31_2_MASK) +#define CSR_PMPADDR11_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR11_PMPADDR_31_2_MASK) >> CSR_PMPADDR11_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR12_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR12_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR12_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR12_PMPADDR_31_2_SHIFT) & CSR_PMPADDR12_PMPADDR_31_2_MASK) +#define CSR_PMPADDR12_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR12_PMPADDR_31_2_MASK) >> CSR_PMPADDR12_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR13_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR13_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR13_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR13_PMPADDR_31_2_SHIFT) & CSR_PMPADDR13_PMPADDR_31_2_MASK) +#define CSR_PMPADDR13_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR13_PMPADDR_31_2_MASK) >> CSR_PMPADDR13_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR14_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR14_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR14_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR14_PMPADDR_31_2_SHIFT) & CSR_PMPADDR14_PMPADDR_31_2_MASK) +#define CSR_PMPADDR14_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR14_PMPADDR_31_2_MASK) >> CSR_PMPADDR14_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR15_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR15_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR15_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR15_PMPADDR_31_2_SHIFT) & CSR_PMPADDR15_PMPADDR_31_2_MASK) +#define CSR_PMPADDR15_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR15_PMPADDR_31_2_MASK) >> CSR_PMPADDR15_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register: TSELECT */ +/* + * TRIGGER_INDEX (RW) + * + * This register determines which trigger is accessible through other trigger registers. + */ +#define CSR_TSELECT_TRIGGER_INDEX_MASK (0xFFFFFFFFUL) +#define CSR_TSELECT_TRIGGER_INDEX_SHIFT (0U) +#define CSR_TSELECT_TRIGGER_INDEX_SET(x) (((uint32_t)(x) << CSR_TSELECT_TRIGGER_INDEX_SHIFT) & CSR_TSELECT_TRIGGER_INDEX_MASK) +#define CSR_TSELECT_TRIGGER_INDEX_GET(x) (((uint32_t)(x) & CSR_TSELECT_TRIGGER_INDEX_MASK) >> CSR_TSELECT_TRIGGER_INDEX_SHIFT) + +/* Bitfield definition for register: TDATA1 */ +/* + * TYPE (RW) + * + * Indicates the trigger type. + * 0:The selected trigger is invalid. + * 2:The selected trigger is an address/data match trigger. + * 3:The selected trigger is an instruction count trigger + * 4:The selected trigger is an interrupt trigger. + * 5:The selected trigger is an exception trigger. + */ +#define CSR_TDATA1_TYPE_MASK (0xF0000000UL) +#define CSR_TDATA1_TYPE_SHIFT (28U) +#define CSR_TDATA1_TYPE_SET(x) (((uint32_t)(x) << CSR_TDATA1_TYPE_SHIFT) & CSR_TDATA1_TYPE_MASK) +#define CSR_TDATA1_TYPE_GET(x) (((uint32_t)(x) & CSR_TDATA1_TYPE_MASK) >> CSR_TDATA1_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_TDATA1_DMODE_MASK (0x8000000UL) +#define CSR_TDATA1_DMODE_SHIFT (27U) +#define CSR_TDATA1_DMODE_SET(x) (((uint32_t)(x) << CSR_TDATA1_DMODE_SHIFT) & CSR_TDATA1_DMODE_MASK) +#define CSR_TDATA1_DMODE_GET(x) (((uint32_t)(x) & CSR_TDATA1_DMODE_MASK) >> CSR_TDATA1_DMODE_SHIFT) + +/* + * DATA (RW) + * + * Trigger-specific data + */ +#define CSR_TDATA1_DATA_MASK (0x7FFFFFFUL) +#define CSR_TDATA1_DATA_SHIFT (0U) +#define CSR_TDATA1_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA1_DATA_SHIFT) & CSR_TDATA1_DATA_MASK) +#define CSR_TDATA1_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA1_DATA_MASK) >> CSR_TDATA1_DATA_SHIFT) + +/* Bitfield definition for register: MCONTROL */ +/* + * TYPE (RW) + * + * Indicates the trigger type. + * 0:The selected trigger is invalid. + * 2:The selected trigger is an address/data match trigger. + */ +#define CSR_MCONTROL_TYPE_MASK (0xF0000000UL) +#define CSR_MCONTROL_TYPE_SHIFT (28U) +#define CSR_MCONTROL_TYPE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_TYPE_SHIFT) & CSR_MCONTROL_TYPE_MASK) +#define CSR_MCONTROL_TYPE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_TYPE_MASK) >> CSR_MCONTROL_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_MCONTROL_DMODE_MASK (0x8000000UL) +#define CSR_MCONTROL_DMODE_SHIFT (27U) +#define CSR_MCONTROL_DMODE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_DMODE_SHIFT) & CSR_MCONTROL_DMODE_MASK) +#define CSR_MCONTROL_DMODE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_DMODE_MASK) >> CSR_MCONTROL_DMODE_SHIFT) + +/* + * MASKMAX (RO) + * + * Indicates the largest naturally aligned range supported by the hardware is 2ˆ12 bytes. + */ +#define CSR_MCONTROL_MASKMAX_MASK (0x7E00000UL) +#define CSR_MCONTROL_MASKMAX_SHIFT (21U) +#define CSR_MCONTROL_MASKMAX_GET(x) (((uint32_t)(x) & CSR_MCONTROL_MASKMAX_MASK) >> CSR_MCONTROL_MASKMAX_SHIFT) + +/* + * ACTION (RW) + * + * Setting this field to select what happens when this trigger matches. + * 0:Raise a breakpoint exception + * 1:Enter Debug Mode. (Only supported when DMODE is 1.) + */ +#define CSR_MCONTROL_ACTION_MASK (0xF000U) +#define CSR_MCONTROL_ACTION_SHIFT (12U) +#define CSR_MCONTROL_ACTION_SET(x) (((uint32_t)(x) << CSR_MCONTROL_ACTION_SHIFT) & CSR_MCONTROL_ACTION_MASK) +#define CSR_MCONTROL_ACTION_GET(x) (((uint32_t)(x) & CSR_MCONTROL_ACTION_MASK) >> CSR_MCONTROL_ACTION_SHIFT) + +/* + * CHAIN (RW) + * + * Setting this field to enable trigger chain. + * 0:When this trigger matches, the configured action is taken. + * 1:While this trigger does not match, it prevents the trigger with the next index from matching. + * If Number of Triggers is 2, this field is hardwired to 0 on trigger 1 (tselect = 1). + * If Number of Triggers is 4, this field is hardwired + * to 0 on trigger 3 (tselect = 3). + * If Number of Triggers is 8, this field is hardwired to 0 on trigger 3 and trigger 7 (tselect = 3 or 7). + */ +#define CSR_MCONTROL_CHAIN_MASK (0x800U) +#define CSR_MCONTROL_CHAIN_SHIFT (11U) +#define CSR_MCONTROL_CHAIN_SET(x) (((uint32_t)(x) << CSR_MCONTROL_CHAIN_SHIFT) & CSR_MCONTROL_CHAIN_MASK) +#define CSR_MCONTROL_CHAIN_GET(x) (((uint32_t)(x) & CSR_MCONTROL_CHAIN_MASK) >> CSR_MCONTROL_CHAIN_SHIFT) + +/* + * MATCH (RW) + * + * Setting this field to select the matching scheme. 0:Matches when the value equals tdata2. 1:Matches when the top M bits of the value match the top M bits of tdata2. M is 31 minus the index of the least-significant bit containing 0 in tdata2. + * 2:Matches when the value is greater than (unsigned) or equal to tdata2. + * 3:Matches when the value is less than (unsigned) tdata2 + */ +#define CSR_MCONTROL_MATCH_MASK (0x780U) +#define CSR_MCONTROL_MATCH_SHIFT (7U) +#define CSR_MCONTROL_MATCH_SET(x) (((uint32_t)(x) << CSR_MCONTROL_MATCH_SHIFT) & CSR_MCONTROL_MATCH_MASK) +#define CSR_MCONTROL_MATCH_GET(x) (((uint32_t)(x) & CSR_MCONTROL_MATCH_MASK) >> CSR_MCONTROL_MATCH_SHIFT) + +/* + * M (RW) + * + * Setting this field to enable this trigger in M-mode. + */ +#define CSR_MCONTROL_M_MASK (0x40U) +#define CSR_MCONTROL_M_SHIFT (6U) +#define CSR_MCONTROL_M_SET(x) (((uint32_t)(x) << CSR_MCONTROL_M_SHIFT) & CSR_MCONTROL_M_MASK) +#define CSR_MCONTROL_M_GET(x) (((uint32_t)(x) & CSR_MCONTROL_M_MASK) >> CSR_MCONTROL_M_SHIFT) + +/* + * S (RW) + * + * Setting this field to enable this trigger in S-mode. + */ +#define CSR_MCONTROL_S_MASK (0x10U) +#define CSR_MCONTROL_S_SHIFT (4U) +#define CSR_MCONTROL_S_SET(x) (((uint32_t)(x) << CSR_MCONTROL_S_SHIFT) & CSR_MCONTROL_S_MASK) +#define CSR_MCONTROL_S_GET(x) (((uint32_t)(x) & CSR_MCONTROL_S_MASK) >> CSR_MCONTROL_S_SHIFT) + +/* + * U (RW) + * + * Setting this field to enable this trigger in U-mode. + */ +#define CSR_MCONTROL_U_MASK (0x8U) +#define CSR_MCONTROL_U_SHIFT (3U) +#define CSR_MCONTROL_U_SET(x) (((uint32_t)(x) << CSR_MCONTROL_U_SHIFT) & CSR_MCONTROL_U_MASK) +#define CSR_MCONTROL_U_GET(x) (((uint32_t)(x) & CSR_MCONTROL_U_MASK) >> CSR_MCONTROL_U_SHIFT) + +/* + * EXECUTE (RW) + * + * Setting this field to enable this trigger to compare virtual address of an instruction. + */ +#define CSR_MCONTROL_EXECUTE_MASK (0x4U) +#define CSR_MCONTROL_EXECUTE_SHIFT (2U) +#define CSR_MCONTROL_EXECUTE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_EXECUTE_SHIFT) & CSR_MCONTROL_EXECUTE_MASK) +#define CSR_MCONTROL_EXECUTE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_EXECUTE_MASK) >> CSR_MCONTROL_EXECUTE_SHIFT) + +/* + * STORE (RW) + * + * Setting this field to enable this trigger to compare virtual address of a store. + */ +#define CSR_MCONTROL_STORE_MASK (0x2U) +#define CSR_MCONTROL_STORE_SHIFT (1U) +#define CSR_MCONTROL_STORE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_STORE_SHIFT) & CSR_MCONTROL_STORE_MASK) +#define CSR_MCONTROL_STORE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_STORE_MASK) >> CSR_MCONTROL_STORE_SHIFT) + +/* + * LOAD (RW) + * + * Setting this field to enable this trigger to compare virtual address of a load. + */ +#define CSR_MCONTROL_LOAD_MASK (0x1U) +#define CSR_MCONTROL_LOAD_SHIFT (0U) +#define CSR_MCONTROL_LOAD_SET(x) (((uint32_t)(x) << CSR_MCONTROL_LOAD_SHIFT) & CSR_MCONTROL_LOAD_MASK) +#define CSR_MCONTROL_LOAD_GET(x) (((uint32_t)(x) & CSR_MCONTROL_LOAD_MASK) >> CSR_MCONTROL_LOAD_SHIFT) + +/* Bitfield definition for register: ICOUNT */ +/* + * TYPE (RW) + * + * The selected trigger is an instruction count trigger. + */ +#define CSR_ICOUNT_TYPE_MASK (0xF0000000UL) +#define CSR_ICOUNT_TYPE_SHIFT (28U) +#define CSR_ICOUNT_TYPE_SET(x) (((uint32_t)(x) << CSR_ICOUNT_TYPE_SHIFT) & CSR_ICOUNT_TYPE_MASK) +#define CSR_ICOUNT_TYPE_GET(x) (((uint32_t)(x) & CSR_ICOUNT_TYPE_MASK) >> CSR_ICOUNT_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_ICOUNT_DMODE_MASK (0x8000000UL) +#define CSR_ICOUNT_DMODE_SHIFT (27U) +#define CSR_ICOUNT_DMODE_SET(x) (((uint32_t)(x) << CSR_ICOUNT_DMODE_SHIFT) & CSR_ICOUNT_DMODE_MASK) +#define CSR_ICOUNT_DMODE_GET(x) (((uint32_t)(x) & CSR_ICOUNT_DMODE_MASK) >> CSR_ICOUNT_DMODE_SHIFT) + +/* + * COUNT (RO) + * + * This field is hardwired to 1 for single-stepping support + */ +#define CSR_ICOUNT_COUNT_MASK (0x400U) +#define CSR_ICOUNT_COUNT_SHIFT (10U) +#define CSR_ICOUNT_COUNT_GET(x) (((uint32_t)(x) & CSR_ICOUNT_COUNT_MASK) >> CSR_ICOUNT_COUNT_SHIFT) + +/* + * M (RW) + * + * Setting this field to enable this trigger in M-mode. + */ +#define CSR_ICOUNT_M_MASK (0x200U) +#define CSR_ICOUNT_M_SHIFT (9U) +#define CSR_ICOUNT_M_SET(x) (((uint32_t)(x) << CSR_ICOUNT_M_SHIFT) & CSR_ICOUNT_M_MASK) +#define CSR_ICOUNT_M_GET(x) (((uint32_t)(x) & CSR_ICOUNT_M_MASK) >> CSR_ICOUNT_M_SHIFT) + +/* + * S (RW) + * + * Setting this field to enable this trigger in S-mode. + */ +#define CSR_ICOUNT_S_MASK (0x80U) +#define CSR_ICOUNT_S_SHIFT (7U) +#define CSR_ICOUNT_S_SET(x) (((uint32_t)(x) << CSR_ICOUNT_S_SHIFT) & CSR_ICOUNT_S_MASK) +#define CSR_ICOUNT_S_GET(x) (((uint32_t)(x) & CSR_ICOUNT_S_MASK) >> CSR_ICOUNT_S_SHIFT) + +/* + * U (RW) + * + * Setting this field to enable this trigger in U-mode. + */ +#define CSR_ICOUNT_U_MASK (0x40U) +#define CSR_ICOUNT_U_SHIFT (6U) +#define CSR_ICOUNT_U_SET(x) (((uint32_t)(x) << CSR_ICOUNT_U_SHIFT) & CSR_ICOUNT_U_MASK) +#define CSR_ICOUNT_U_GET(x) (((uint32_t)(x) & CSR_ICOUNT_U_MASK) >> CSR_ICOUNT_U_SHIFT) + +/* + * ACTION (RW) + * + * Setting this field to select what happens when this trigger matches. + * 0:Raise a breakpoint exception + * 1:Enter Debug Mode. (Only supported when DMODE is 1.) + */ +#define CSR_ICOUNT_ACTION_MASK (0x3FU) +#define CSR_ICOUNT_ACTION_SHIFT (0U) +#define CSR_ICOUNT_ACTION_SET(x) (((uint32_t)(x) << CSR_ICOUNT_ACTION_SHIFT) & CSR_ICOUNT_ACTION_MASK) +#define CSR_ICOUNT_ACTION_GET(x) (((uint32_t)(x) & CSR_ICOUNT_ACTION_MASK) >> CSR_ICOUNT_ACTION_SHIFT) + +/* Bitfield definition for register: ITRIGGER */ +/* + * TYPE (RW) + * + * The selected trigger is an interrupt trigger. + */ +#define CSR_ITRIGGER_TYPE_MASK (0xF0000000UL) +#define CSR_ITRIGGER_TYPE_SHIFT (28U) +#define CSR_ITRIGGER_TYPE_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_TYPE_SHIFT) & CSR_ITRIGGER_TYPE_MASK) +#define CSR_ITRIGGER_TYPE_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_TYPE_MASK) >> CSR_ITRIGGER_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_ITRIGGER_DMODE_MASK (0x8000000UL) +#define CSR_ITRIGGER_DMODE_SHIFT (27U) +#define CSR_ITRIGGER_DMODE_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_DMODE_SHIFT) & CSR_ITRIGGER_DMODE_MASK) +#define CSR_ITRIGGER_DMODE_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_DMODE_MASK) >> CSR_ITRIGGER_DMODE_SHIFT) + +/* + * M (RW) + * + * Setting this field to enable this trigger in M-mode. + */ +#define CSR_ITRIGGER_M_MASK (0x200U) +#define CSR_ITRIGGER_M_SHIFT (9U) +#define CSR_ITRIGGER_M_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_M_SHIFT) & CSR_ITRIGGER_M_MASK) +#define CSR_ITRIGGER_M_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_M_MASK) >> CSR_ITRIGGER_M_SHIFT) + +/* + * S (RW) + * + * Setting this field to enable this trigger in S-mode. + */ +#define CSR_ITRIGGER_S_MASK (0x80U) +#define CSR_ITRIGGER_S_SHIFT (7U) +#define CSR_ITRIGGER_S_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_S_SHIFT) & CSR_ITRIGGER_S_MASK) +#define CSR_ITRIGGER_S_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_S_MASK) >> CSR_ITRIGGER_S_SHIFT) + +/* + * U (RW) + * + * Setting this field to enable this trigger in U-mode. + */ +#define CSR_ITRIGGER_U_MASK (0x40U) +#define CSR_ITRIGGER_U_SHIFT (6U) +#define CSR_ITRIGGER_U_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_U_SHIFT) & CSR_ITRIGGER_U_MASK) +#define CSR_ITRIGGER_U_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_U_MASK) >> CSR_ITRIGGER_U_SHIFT) + +/* + * ACTION (RW) + * + * Setting this field to select what happens when this trigger matches. + * 0:Raise a breakpoint exception. + * 1:Enter Debug Mode. (Only supported when DMODE is 1.) + */ +#define CSR_ITRIGGER_ACTION_MASK (0x3FU) +#define CSR_ITRIGGER_ACTION_SHIFT (0U) +#define CSR_ITRIGGER_ACTION_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_ACTION_SHIFT) & CSR_ITRIGGER_ACTION_MASK) +#define CSR_ITRIGGER_ACTION_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_ACTION_MASK) >> CSR_ITRIGGER_ACTION_SHIFT) + +/* Bitfield definition for register: ETRIGGER */ +/* + * TYPE (RW) + * + * The selected trigger is an exception trigger. + */ +#define CSR_ETRIGGER_TYPE_MASK (0xF0000000UL) +#define CSR_ETRIGGER_TYPE_SHIFT (28U) +#define CSR_ETRIGGER_TYPE_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_TYPE_SHIFT) & CSR_ETRIGGER_TYPE_MASK) +#define CSR_ETRIGGER_TYPE_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_TYPE_MASK) >> CSR_ETRIGGER_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_ETRIGGER_DMODE_MASK (0x8000000UL) +#define CSR_ETRIGGER_DMODE_SHIFT (27U) +#define CSR_ETRIGGER_DMODE_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_DMODE_SHIFT) & CSR_ETRIGGER_DMODE_MASK) +#define CSR_ETRIGGER_DMODE_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_DMODE_MASK) >> CSR_ETRIGGER_DMODE_SHIFT) + +/* + * NMI (RW) + * + * Setting this field to enable this trigger in non-maskable interrupts, regardless of the values of s, u, and m. + */ +#define CSR_ETRIGGER_NMI_MASK (0x400U) +#define CSR_ETRIGGER_NMI_SHIFT (10U) +#define CSR_ETRIGGER_NMI_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_NMI_SHIFT) & CSR_ETRIGGER_NMI_MASK) +#define CSR_ETRIGGER_NMI_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_NMI_MASK) >> CSR_ETRIGGER_NMI_SHIFT) + +/* + * M (RW) + * + * Setting this field to enable this trigger in M-mode. + */ +#define CSR_ETRIGGER_M_MASK (0x200U) +#define CSR_ETRIGGER_M_SHIFT (9U) +#define CSR_ETRIGGER_M_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_M_SHIFT) & CSR_ETRIGGER_M_MASK) +#define CSR_ETRIGGER_M_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_M_MASK) >> CSR_ETRIGGER_M_SHIFT) + +/* + * S (RW) + * + * Setting this field to enable this trigger in S-mode. + */ +#define CSR_ETRIGGER_S_MASK (0x80U) +#define CSR_ETRIGGER_S_SHIFT (7U) +#define CSR_ETRIGGER_S_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_S_SHIFT) & CSR_ETRIGGER_S_MASK) +#define CSR_ETRIGGER_S_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_S_MASK) >> CSR_ETRIGGER_S_SHIFT) + +/* + * U (RW) + * + * Setting this field to enable this trigger in U-mode. + */ +#define CSR_ETRIGGER_U_MASK (0x40U) +#define CSR_ETRIGGER_U_SHIFT (6U) +#define CSR_ETRIGGER_U_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_U_SHIFT) & CSR_ETRIGGER_U_MASK) +#define CSR_ETRIGGER_U_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_U_MASK) >> CSR_ETRIGGER_U_SHIFT) + +/* + * ACTION (RW) + * + * Setting this field to select what happens when this trigger matches. + * 0:Raise a breakpoint exception + * 1:Enter Debug Mode. (Only supported when DMODE is 1.) + */ +#define CSR_ETRIGGER_ACTION_MASK (0x3FU) +#define CSR_ETRIGGER_ACTION_SHIFT (0U) +#define CSR_ETRIGGER_ACTION_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_ACTION_SHIFT) & CSR_ETRIGGER_ACTION_MASK) +#define CSR_ETRIGGER_ACTION_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_ACTION_MASK) >> CSR_ETRIGGER_ACTION_SHIFT) + +/* Bitfield definition for register: TDATA2 */ +/* + * DATA (RW) + * + * This register provides accesses to the tdata2 register of the currently selected trigger registers selected by the tselect register, and it holds trigger-specific data.. + */ +#define CSR_TDATA2_DATA_MASK (0xFFFFFFFFUL) +#define CSR_TDATA2_DATA_SHIFT (0U) +#define CSR_TDATA2_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA2_DATA_SHIFT) & CSR_TDATA2_DATA_MASK) +#define CSR_TDATA2_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA2_DATA_MASK) >> CSR_TDATA2_DATA_SHIFT) + +/* Bitfield definition for register: TDATA3 */ +/* + * DATA (RW) + * + * This register provides accesses to the tdata3 register of the currently selected trigger registers selected by the tselect register, and it holds trigger-specific data.. + */ +#define CSR_TDATA3_DATA_MASK (0xFFFFFFFFUL) +#define CSR_TDATA3_DATA_SHIFT (0U) +#define CSR_TDATA3_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA3_DATA_SHIFT) & CSR_TDATA3_DATA_MASK) +#define CSR_TDATA3_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA3_DATA_MASK) >> CSR_TDATA3_DATA_SHIFT) + +/* Bitfield definition for register: TEXTRA */ +/* + * MVALUE (RW) + * + * Data used together with MSELECT. + */ +#define CSR_TEXTRA_MVALUE_MASK (0xFC000000UL) +#define CSR_TEXTRA_MVALUE_SHIFT (26U) +#define CSR_TEXTRA_MVALUE_SET(x) (((uint32_t)(x) << CSR_TEXTRA_MVALUE_SHIFT) & CSR_TEXTRA_MVALUE_MASK) +#define CSR_TEXTRA_MVALUE_GET(x) (((uint32_t)(x) & CSR_TEXTRA_MVALUE_MASK) >> CSR_TEXTRA_MVALUE_SHIFT) + +/* + * MSELECT (RW) + * + * 0:Ignore MVALUE. + * 1:This trigger will only match if the lower bits of mcontext equal MVALUE. + */ +#define CSR_TEXTRA_MSELECT_MASK (0x2000000UL) +#define CSR_TEXTRA_MSELECT_SHIFT (25U) +#define CSR_TEXTRA_MSELECT_SET(x) (((uint32_t)(x) << CSR_TEXTRA_MSELECT_SHIFT) & CSR_TEXTRA_MSELECT_MASK) +#define CSR_TEXTRA_MSELECT_GET(x) (((uint32_t)(x) & CSR_TEXTRA_MSELECT_MASK) >> CSR_TEXTRA_MSELECT_SHIFT) + +/* + * SVALUE (RW) + * + * Data used together with SSELECT. + */ +#define CSR_TEXTRA_SVALUE_MASK (0x7FCU) +#define CSR_TEXTRA_SVALUE_SHIFT (2U) +#define CSR_TEXTRA_SVALUE_SET(x) (((uint32_t)(x) << CSR_TEXTRA_SVALUE_SHIFT) & CSR_TEXTRA_SVALUE_MASK) +#define CSR_TEXTRA_SVALUE_GET(x) (((uint32_t)(x) & CSR_TEXTRA_SVALUE_MASK) >> CSR_TEXTRA_SVALUE_SHIFT) + +/* + * SSELECT (RW) + * + * 0:Ignore MVALUE + * 1:This trigger will only match if the lower bits of scontext equal SVALUE + * 2This trigger will only match if satp.ASID equals SVALUE. + */ +#define CSR_TEXTRA_SSELECT_MASK (0x3U) +#define CSR_TEXTRA_SSELECT_SHIFT (0U) +#define CSR_TEXTRA_SSELECT_SET(x) (((uint32_t)(x) << CSR_TEXTRA_SSELECT_SHIFT) & CSR_TEXTRA_SSELECT_MASK) +#define CSR_TEXTRA_SSELECT_GET(x) (((uint32_t)(x) & CSR_TEXTRA_SSELECT_MASK) >> CSR_TEXTRA_SSELECT_SHIFT) + +/* Bitfield definition for register: TINFO */ +/* + * INFO (RO) + * + * One bit for each possible type in tdata1. Bit N corresponds to type N. If the bit is set, then that + * type is supported by the currently selected trigger. If the currently selected trigger does not exist, this field contains 1. + * 0:When this bit is set, there is no trigger at this tselect + * 1:Reserved and hardwired to 0. + * 2：When this bit is set, the selected trigger supports type of address/data match trigger + * 3:When this bit is set, the selected trigger supports type of instruction count trigger. + * 4:When this bit is set, the selected trigger supports type of interrupt trigger + * 5:When this bit is set, the selected trigger supports type of exception trigger + * 15:When this bit is set, the selected trigger exists (so enumeration shouldn’t terminate), but is not currently available. + * Others:Reserved for future use. + */ +#define CSR_TINFO_INFO_MASK (0xFFFFU) +#define CSR_TINFO_INFO_SHIFT (0U) +#define CSR_TINFO_INFO_GET(x) (((uint32_t)(x) & CSR_TINFO_INFO_MASK) >> CSR_TINFO_INFO_SHIFT) + +/* Bitfield definition for register: TCONTROL */ +/* + * MPTE (RW) + * + * M-mode previous trigger enable field. When a trap into M-mode is taken, MPTE is set to the value of MTE. + */ +#define CSR_TCONTROL_MPTE_MASK (0x80U) +#define CSR_TCONTROL_MPTE_SHIFT (7U) +#define CSR_TCONTROL_MPTE_SET(x) (((uint32_t)(x) << CSR_TCONTROL_MPTE_SHIFT) & CSR_TCONTROL_MPTE_MASK) +#define CSR_TCONTROL_MPTE_GET(x) (((uint32_t)(x) & CSR_TCONTROL_MPTE_MASK) >> CSR_TCONTROL_MPTE_SHIFT) + +/* + * MTE (RW) + * + * M-mode trigger enable field. When a trap into M-mode is taken, MTE is set to 0. When the MRET instruction is executed, MTE is set to the value of MPTE. + * 0:Triggers do not match/fire while the hart is in M-mode. + * 1:Triggers do match/fire while the hart is in M-mode. + */ +#define CSR_TCONTROL_MTE_MASK (0x8U) +#define CSR_TCONTROL_MTE_SHIFT (3U) +#define CSR_TCONTROL_MTE_SET(x) (((uint32_t)(x) << CSR_TCONTROL_MTE_SHIFT) & CSR_TCONTROL_MTE_MASK) +#define CSR_TCONTROL_MTE_GET(x) (((uint32_t)(x) & CSR_TCONTROL_MTE_MASK) >> CSR_TCONTROL_MTE_SHIFT) + +/* Bitfield definition for register: MCONTEXT */ +/* + * MCONTEXT (RW) + * + * Machine mode software can write a context number to this register, which can be used to set triggers that only fire in that specific context. + */ +#define CSR_MCONTEXT_MCONTEXT_MASK (0x3FU) +#define CSR_MCONTEXT_MCONTEXT_SHIFT (0U) +#define CSR_MCONTEXT_MCONTEXT_SET(x) (((uint32_t)(x) << CSR_MCONTEXT_MCONTEXT_SHIFT) & CSR_MCONTEXT_MCONTEXT_MASK) +#define CSR_MCONTEXT_MCONTEXT_GET(x) (((uint32_t)(x) & CSR_MCONTEXT_MCONTEXT_MASK) >> CSR_MCONTEXT_MCONTEXT_SHIFT) + +/* Bitfield definition for register: SCONTEXT */ +/* + * SCONTEXT (RW) + * + * Machine mode software can write a context number to this register, which can be used to set triggers that only fire in that specific context. + */ +#define CSR_SCONTEXT_SCONTEXT_MASK (0x1FFU) +#define CSR_SCONTEXT_SCONTEXT_SHIFT (0U) +#define CSR_SCONTEXT_SCONTEXT_SET(x) (((uint32_t)(x) << CSR_SCONTEXT_SCONTEXT_SHIFT) & CSR_SCONTEXT_SCONTEXT_MASK) +#define CSR_SCONTEXT_SCONTEXT_GET(x) (((uint32_t)(x) & CSR_SCONTEXT_SCONTEXT_MASK) >> CSR_SCONTEXT_SCONTEXT_SHIFT) + +/* Bitfield definition for register: DCSR */ +/* + * XDEBUGVER (RO) + * + * Version of the external debugger. 0 indicates that no external debugger exists and 4 indicates that the external debugger conforms to the RISC-V External Debug Support (TD003) V0.13 + */ +#define CSR_DCSR_XDEBUGVER_MASK (0xF0000000UL) +#define CSR_DCSR_XDEBUGVER_SHIFT (28U) +#define CSR_DCSR_XDEBUGVER_GET(x) (((uint32_t)(x) & CSR_DCSR_XDEBUGVER_MASK) >> CSR_DCSR_XDEBUGVER_SHIFT) + +/* + * EBREAKM (RW) + * + * This bit controls the behavior of EBREAK instructions in Machine Mode + * 0:Generate a regular breakpoint exception + * 1:Enter Debug Mode + */ +#define CSR_DCSR_EBREAKM_MASK (0x8000U) +#define CSR_DCSR_EBREAKM_SHIFT (15U) +#define CSR_DCSR_EBREAKM_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKM_SHIFT) & CSR_DCSR_EBREAKM_MASK) +#define CSR_DCSR_EBREAKM_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKM_MASK) >> CSR_DCSR_EBREAKM_SHIFT) + +/* + * EBREAKS (RW) + * + * This bit controls the behavior of EBREAK instructions in Supervisor Mode. + * 0:Generate a regular breakpoint exception + * 1:Enter Debug Mode + */ +#define CSR_DCSR_EBREAKS_MASK (0x2000U) +#define CSR_DCSR_EBREAKS_SHIFT (13U) +#define CSR_DCSR_EBREAKS_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKS_SHIFT) & CSR_DCSR_EBREAKS_MASK) +#define CSR_DCSR_EBREAKS_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKS_MASK) >> CSR_DCSR_EBREAKS_SHIFT) + +/* + * EBREAKU (RW) + * + * This bit controls the behavior of EBREAK instructions in User/Application Mode + * 0:Generate a regular breakpoint exception + * 1:Enter Debug Mode + */ +#define CSR_DCSR_EBREAKU_MASK (0x1000U) +#define CSR_DCSR_EBREAKU_SHIFT (12U) +#define CSR_DCSR_EBREAKU_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKU_SHIFT) & CSR_DCSR_EBREAKU_MASK) +#define CSR_DCSR_EBREAKU_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKU_MASK) >> CSR_DCSR_EBREAKU_SHIFT) + +/* + * STEPIE (RW) + * + * This bit controls whether interrupts are enabled during single stepping + * 0:Disable interrupts during single stepping + * 1:Allow interrupts in single stepping + */ +#define CSR_DCSR_STEPIE_MASK (0x800U) +#define CSR_DCSR_STEPIE_SHIFT (11U) +#define CSR_DCSR_STEPIE_SET(x) (((uint32_t)(x) << CSR_DCSR_STEPIE_SHIFT) & CSR_DCSR_STEPIE_MASK) +#define CSR_DCSR_STEPIE_GET(x) (((uint32_t)(x) & CSR_DCSR_STEPIE_MASK) >> CSR_DCSR_STEPIE_SHIFT) + +/* + * STOPCOUNT (RW) + * + * This bit controls whether performance counters are stopped in Debug Mode. + * 0:Do not stop counters in Debug Mode + * 1:Stop counters in Debug Mode + */ +#define CSR_DCSR_STOPCOUNT_MASK (0x400U) +#define CSR_DCSR_STOPCOUNT_SHIFT (10U) +#define CSR_DCSR_STOPCOUNT_SET(x) (((uint32_t)(x) << CSR_DCSR_STOPCOUNT_SHIFT) & CSR_DCSR_STOPCOUNT_MASK) +#define CSR_DCSR_STOPCOUNT_GET(x) (((uint32_t)(x) & CSR_DCSR_STOPCOUNT_MASK) >> CSR_DCSR_STOPCOUNT_SHIFT) + +/* + * STOPTIME (RW) + * + * This bit controls whether timers are stopped in Debug Mode. The processor only drives its stoptime output pin to 1 if it is in Debug Mode and this bit is set. Integration effort is required to make timers in the platform observe this pin to really stop them. + * 0:Do not stop timers in Debug Mode + * 1:Stop timers in Debug Mode + */ +#define CSR_DCSR_STOPTIME_MASK (0x200U) +#define CSR_DCSR_STOPTIME_SHIFT (9U) +#define CSR_DCSR_STOPTIME_SET(x) (((uint32_t)(x) << CSR_DCSR_STOPTIME_SHIFT) & CSR_DCSR_STOPTIME_MASK) +#define CSR_DCSR_STOPTIME_GET(x) (((uint32_t)(x) & CSR_DCSR_STOPTIME_MASK) >> CSR_DCSR_STOPTIME_SHIFT) + +/* + * CAUSE (RO) + * + * Reason why Debug Mode was entered. When there are multiple reasons to enter Debug Mode, the priority to determine the CAUSE value will be: trigger module > EBREAK > halt-on-reset > halt request > single step. Halt requests are requests issued by the external debugger + * 0:Reserved + * 1:EBREAK + * 2:Trigger module + * 3:Halt request + * 4:Single step + * 5:Halt-on-reset + * 6-7:Reserved + */ +#define CSR_DCSR_CAUSE_MASK (0x1C0U) +#define CSR_DCSR_CAUSE_SHIFT (6U) +#define CSR_DCSR_CAUSE_GET(x) (((uint32_t)(x) & CSR_DCSR_CAUSE_MASK) >> CSR_DCSR_CAUSE_SHIFT) + +/* + * MPRVEN (RW) + * + * This bit controls whether mstatus.MPRV takes effect in Debug Mode. + * 0:MPRV in mstatus is ignored in Debug Mode. + * 1:MPRV in mstatus takes effect in Debug Mode. + */ +#define CSR_DCSR_MPRVEN_MASK (0x10U) +#define CSR_DCSR_MPRVEN_SHIFT (4U) +#define CSR_DCSR_MPRVEN_SET(x) (((uint32_t)(x) << CSR_DCSR_MPRVEN_SHIFT) & CSR_DCSR_MPRVEN_MASK) +#define CSR_DCSR_MPRVEN_GET(x) (((uint32_t)(x) & CSR_DCSR_MPRVEN_MASK) >> CSR_DCSR_MPRVEN_SHIFT) + +/* + * NMIP (RO) + * + * When this bit is set, there is a Non-Maskable-Interrupt (NMI) pending for the hart. Since an NMI can indicate a hardware error condition, reliable debugging may no longer be possible once this bit becomes set. + */ +#define CSR_DCSR_NMIP_MASK (0x8U) +#define CSR_DCSR_NMIP_SHIFT (3U) +#define CSR_DCSR_NMIP_GET(x) (((uint32_t)(x) & CSR_DCSR_NMIP_MASK) >> CSR_DCSR_NMIP_SHIFT) + +/* + * STEP (RW) + * + * This bit controls whether non-Debug Mode instruction execution is in the single step mode. When set, the hart returns to Debug Mode after a single instruction execution. If the instruction does not complete due to an exception, the hart will immediately enter Debug Mode before executing the trap handler, with appropriate exception registers set. + * 0:Single Step Mode is off + * 1:Single Step Mode is on + */ +#define CSR_DCSR_STEP_MASK (0x4U) +#define CSR_DCSR_STEP_SHIFT (2U) +#define CSR_DCSR_STEP_SET(x) (((uint32_t)(x) << CSR_DCSR_STEP_SHIFT) & CSR_DCSR_STEP_MASK) +#define CSR_DCSR_STEP_GET(x) (((uint32_t)(x) & CSR_DCSR_STEP_MASK) >> CSR_DCSR_STEP_SHIFT) + +/* + * PRV (RW) + * + * The privilege level that the hart was operating in when Debug Mode was entered. The external debugger can modify this value to change the hart’s privilege level when exiting Debug Mode. + * 0:User/Application + * 1:Supervisor + * 2:Reserved + * 3:Machine + */ +#define CSR_DCSR_PRV_MASK (0x3U) +#define CSR_DCSR_PRV_SHIFT (0U) +#define CSR_DCSR_PRV_SET(x) (((uint32_t)(x) << CSR_DCSR_PRV_SHIFT) & CSR_DCSR_PRV_MASK) +#define CSR_DCSR_PRV_GET(x) (((uint32_t)(x) & CSR_DCSR_PRV_MASK) >> CSR_DCSR_PRV_SHIFT) + +/* Bitfield definition for register: DPC */ +/* + * DPC (RW) + * + * Debug Program Counter. Bit 0 is hardwired to 0. + */ +#define CSR_DPC_DPC_MASK (0xFFFFFFFFUL) +#define CSR_DPC_DPC_SHIFT (0U) +#define CSR_DPC_DPC_SET(x) (((uint32_t)(x) << CSR_DPC_DPC_SHIFT) & CSR_DPC_DPC_MASK) +#define CSR_DPC_DPC_GET(x) (((uint32_t)(x) & CSR_DPC_DPC_MASK) >> CSR_DPC_DPC_SHIFT) + +/* Bitfield definition for register: DSCRATCH0 */ +/* + * DSCRATCH (RO) + * + * A scratch register that is reserved for use by Debug Module. + */ +#define CSR_DSCRATCH0_DSCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_DSCRATCH0_DSCRATCH_SHIFT (0U) +#define CSR_DSCRATCH0_DSCRATCH_GET(x) (((uint32_t)(x) & CSR_DSCRATCH0_DSCRATCH_MASK) >> CSR_DSCRATCH0_DSCRATCH_SHIFT) + +/* Bitfield definition for register: DSCRATCH1 */ +/* + * DSCRATCH (RO) + * + * A scratch register that is reserved for use by Debug Module. + */ +#define CSR_DSCRATCH1_DSCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_DSCRATCH1_DSCRATCH_SHIFT (0U) +#define CSR_DSCRATCH1_DSCRATCH_GET(x) (((uint32_t)(x) & CSR_DSCRATCH1_DSCRATCH_MASK) >> CSR_DSCRATCH1_DSCRATCH_SHIFT) + +/* Bitfield definition for register: MCYCLE */ +/* + * COUNTER (RW) + * + * the lower 32 bits of Machine Cycle Counter + */ +#define CSR_MCYCLE_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MCYCLE_COUNTER_SHIFT (0U) +#define CSR_MCYCLE_COUNTER_SET(x) (((uint32_t)(x) << CSR_MCYCLE_COUNTER_SHIFT) & CSR_MCYCLE_COUNTER_MASK) +#define CSR_MCYCLE_COUNTER_GET(x) (((uint32_t)(x) & CSR_MCYCLE_COUNTER_MASK) >> CSR_MCYCLE_COUNTER_SHIFT) + +/* Bitfield definition for register: MINSTRET */ +/* + * COUNTER (RW) + * + * the lower 32 bits of Machine Instruction-Retired Counter + */ +#define CSR_MINSTRET_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MINSTRET_COUNTER_SHIFT (0U) +#define CSR_MINSTRET_COUNTER_SET(x) (((uint32_t)(x) << CSR_MINSTRET_COUNTER_SHIFT) & CSR_MINSTRET_COUNTER_MASK) +#define CSR_MINSTRET_COUNTER_GET(x) (((uint32_t)(x) & CSR_MINSTRET_COUNTER_MASK) >> CSR_MINSTRET_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER3 */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent3 + */ +#define CSR_MHPMCOUNTER3_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER3_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER3_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER3_COUNTER_SHIFT) & CSR_MHPMCOUNTER3_COUNTER_MASK) +#define CSR_MHPMCOUNTER3_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER3_COUNTER_MASK) >> CSR_MHPMCOUNTER3_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER4 */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent4 + */ +#define CSR_MHPMCOUNTER4_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER4_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER4_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER4_COUNTER_SHIFT) & CSR_MHPMCOUNTER4_COUNTER_MASK) +#define CSR_MHPMCOUNTER4_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER4_COUNTER_MASK) >> CSR_MHPMCOUNTER4_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER5 */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent5 + */ +#define CSR_MHPMCOUNTER5_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER5_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER5_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER5_COUNTER_SHIFT) & CSR_MHPMCOUNTER5_COUNTER_MASK) +#define CSR_MHPMCOUNTER5_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER5_COUNTER_MASK) >> CSR_MHPMCOUNTER5_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER6 */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent6 + */ +#define CSR_MHPMCOUNTER6_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER6_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER6_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER6_COUNTER_SHIFT) & CSR_MHPMCOUNTER6_COUNTER_MASK) +#define CSR_MHPMCOUNTER6_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER6_COUNTER_MASK) >> CSR_MHPMCOUNTER6_COUNTER_SHIFT) + +/* Bitfield definition for register: MCYCLEH */ +/* + * COUNTER (RW) + * + * the higher 32 bits of Machine Cycle Counter + */ +#define CSR_MCYCLEH_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MCYCLEH_COUNTER_SHIFT (0U) +#define CSR_MCYCLEH_COUNTER_SET(x) (((uint32_t)(x) << CSR_MCYCLEH_COUNTER_SHIFT) & CSR_MCYCLEH_COUNTER_MASK) +#define CSR_MCYCLEH_COUNTER_GET(x) (((uint32_t)(x) & CSR_MCYCLEH_COUNTER_MASK) >> CSR_MCYCLEH_COUNTER_SHIFT) + +/* Bitfield definition for register: MINSTRETH */ +/* + * COUNTER (RW) + * + * the higher 32 bits of Machine Instruction-Retired Counter + */ +#define CSR_MINSTRETH_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MINSTRETH_COUNTER_SHIFT (0U) +#define CSR_MINSTRETH_COUNTER_SET(x) (((uint32_t)(x) << CSR_MINSTRETH_COUNTER_SHIFT) & CSR_MINSTRETH_COUNTER_MASK) +#define CSR_MINSTRETH_COUNTER_GET(x) (((uint32_t)(x) & CSR_MINSTRETH_COUNTER_MASK) >> CSR_MINSTRETH_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER3H */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent3 + */ +#define CSR_MHPMCOUNTER3H_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER3H_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER3H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER3H_COUNTER_SHIFT) & CSR_MHPMCOUNTER3H_COUNTER_MASK) +#define CSR_MHPMCOUNTER3H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER3H_COUNTER_MASK) >> CSR_MHPMCOUNTER3H_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER4H */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent4 + */ +#define CSR_MHPMCOUNTER4H_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER4H_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER4H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER4H_COUNTER_SHIFT) & CSR_MHPMCOUNTER4H_COUNTER_MASK) +#define CSR_MHPMCOUNTER4H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER4H_COUNTER_MASK) >> CSR_MHPMCOUNTER4H_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER5H */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent5 + */ +#define CSR_MHPMCOUNTER5H_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER5H_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER5H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER5H_COUNTER_SHIFT) & CSR_MHPMCOUNTER5H_COUNTER_MASK) +#define CSR_MHPMCOUNTER5H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER5H_COUNTER_MASK) >> CSR_MHPMCOUNTER5H_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER6H */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent6 + */ +#define CSR_MHPMCOUNTER6H_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER6H_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER6H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER6H_COUNTER_SHIFT) & CSR_MHPMCOUNTER6H_COUNTER_MASK) +#define CSR_MHPMCOUNTER6H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER6H_COUNTER_MASK) >> CSR_MHPMCOUNTER6H_COUNTER_SHIFT) + +/* Bitfield definition for register: PMACFG0 */ +/* + * PMA3CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG0_PMA3CFG_MASK (0xFF000000UL) +#define CSR_PMACFG0_PMA3CFG_SHIFT (24U) +#define CSR_PMACFG0_PMA3CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA3CFG_SHIFT) & CSR_PMACFG0_PMA3CFG_MASK) +#define CSR_PMACFG0_PMA3CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA3CFG_MASK) >> CSR_PMACFG0_PMA3CFG_SHIFT) + +/* + * PMA2CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG0_PMA2CFG_MASK (0xFF0000UL) +#define CSR_PMACFG0_PMA2CFG_SHIFT (16U) +#define CSR_PMACFG0_PMA2CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA2CFG_SHIFT) & CSR_PMACFG0_PMA2CFG_MASK) +#define CSR_PMACFG0_PMA2CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA2CFG_MASK) >> CSR_PMACFG0_PMA2CFG_SHIFT) + +/* + * PMA1CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG0_PMA1CFG_MASK (0xFF00U) +#define CSR_PMACFG0_PMA1CFG_SHIFT (8U) +#define CSR_PMACFG0_PMA1CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA1CFG_SHIFT) & CSR_PMACFG0_PMA1CFG_MASK) +#define CSR_PMACFG0_PMA1CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA1CFG_MASK) >> CSR_PMACFG0_PMA1CFG_SHIFT) + +/* + * PMA0CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG0_PMA0CFG_MASK (0xFFU) +#define CSR_PMACFG0_PMA0CFG_SHIFT (0U) +#define CSR_PMACFG0_PMA0CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA0CFG_SHIFT) & CSR_PMACFG0_PMA0CFG_MASK) +#define CSR_PMACFG0_PMA0CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA0CFG_MASK) >> CSR_PMACFG0_PMA0CFG_SHIFT) + +/* Bitfield definition for register: PMACFG1 */ +/* + * PMA7CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG1_PMA7CFG_MASK (0xFF000000UL) +#define CSR_PMACFG1_PMA7CFG_SHIFT (24U) +#define CSR_PMACFG1_PMA7CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA7CFG_SHIFT) & CSR_PMACFG1_PMA7CFG_MASK) +#define CSR_PMACFG1_PMA7CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA7CFG_MASK) >> CSR_PMACFG1_PMA7CFG_SHIFT) + +/* + * PMA6CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG1_PMA6CFG_MASK (0xFF0000UL) +#define CSR_PMACFG1_PMA6CFG_SHIFT (16U) +#define CSR_PMACFG1_PMA6CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA6CFG_SHIFT) & CSR_PMACFG1_PMA6CFG_MASK) +#define CSR_PMACFG1_PMA6CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA6CFG_MASK) >> CSR_PMACFG1_PMA6CFG_SHIFT) + +/* + * PMA5CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG1_PMA5CFG_MASK (0xFF00U) +#define CSR_PMACFG1_PMA5CFG_SHIFT (8U) +#define CSR_PMACFG1_PMA5CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA5CFG_SHIFT) & CSR_PMACFG1_PMA5CFG_MASK) +#define CSR_PMACFG1_PMA5CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA5CFG_MASK) >> CSR_PMACFG1_PMA5CFG_SHIFT) + +/* + * PMA4CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG1_PMA4CFG_MASK (0xFFU) +#define CSR_PMACFG1_PMA4CFG_SHIFT (0U) +#define CSR_PMACFG1_PMA4CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA4CFG_SHIFT) & CSR_PMACFG1_PMA4CFG_MASK) +#define CSR_PMACFG1_PMA4CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA4CFG_MASK) >> CSR_PMACFG1_PMA4CFG_SHIFT) + +/* Bitfield definition for register: PMACFG2 */ +/* + * PMA11CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG2_PMA11CFG_MASK (0xFF000000UL) +#define CSR_PMACFG2_PMA11CFG_SHIFT (24U) +#define CSR_PMACFG2_PMA11CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA11CFG_SHIFT) & CSR_PMACFG2_PMA11CFG_MASK) +#define CSR_PMACFG2_PMA11CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA11CFG_MASK) >> CSR_PMACFG2_PMA11CFG_SHIFT) + +/* + * PMA10CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG2_PMA10CFG_MASK (0xFF0000UL) +#define CSR_PMACFG2_PMA10CFG_SHIFT (16U) +#define CSR_PMACFG2_PMA10CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA10CFG_SHIFT) & CSR_PMACFG2_PMA10CFG_MASK) +#define CSR_PMACFG2_PMA10CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA10CFG_MASK) >> CSR_PMACFG2_PMA10CFG_SHIFT) + +/* + * PMA9CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG2_PMA9CFG_MASK (0xFF00U) +#define CSR_PMACFG2_PMA9CFG_SHIFT (8U) +#define CSR_PMACFG2_PMA9CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA9CFG_SHIFT) & CSR_PMACFG2_PMA9CFG_MASK) +#define CSR_PMACFG2_PMA9CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA9CFG_MASK) >> CSR_PMACFG2_PMA9CFG_SHIFT) + +/* + * PMA8CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG2_PMA8CFG_MASK (0xFFU) +#define CSR_PMACFG2_PMA8CFG_SHIFT (0U) +#define CSR_PMACFG2_PMA8CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA8CFG_SHIFT) & CSR_PMACFG2_PMA8CFG_MASK) +#define CSR_PMACFG2_PMA8CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA8CFG_MASK) >> CSR_PMACFG2_PMA8CFG_SHIFT) + +/* Bitfield definition for register: PMACFG3 */ +/* + * PMA15CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG3_PMA15CFG_MASK (0xFF000000UL) +#define CSR_PMACFG3_PMA15CFG_SHIFT (24U) +#define CSR_PMACFG3_PMA15CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA15CFG_SHIFT) & CSR_PMACFG3_PMA15CFG_MASK) +#define CSR_PMACFG3_PMA15CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA15CFG_MASK) >> CSR_PMACFG3_PMA15CFG_SHIFT) + +/* + * PMA14CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG3_PMA14CFG_MASK (0xFF0000UL) +#define CSR_PMACFG3_PMA14CFG_SHIFT (16U) +#define CSR_PMACFG3_PMA14CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA14CFG_SHIFT) & CSR_PMACFG3_PMA14CFG_MASK) +#define CSR_PMACFG3_PMA14CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA14CFG_MASK) >> CSR_PMACFG3_PMA14CFG_SHIFT) + +/* + * PMA13CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG3_PMA13CFG_MASK (0xFF00U) +#define CSR_PMACFG3_PMA13CFG_SHIFT (8U) +#define CSR_PMACFG3_PMA13CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA13CFG_SHIFT) & CSR_PMACFG3_PMA13CFG_MASK) +#define CSR_PMACFG3_PMA13CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA13CFG_MASK) >> CSR_PMACFG3_PMA13CFG_SHIFT) + +/* + * PMA12CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG3_PMA12CFG_MASK (0xFFU) +#define CSR_PMACFG3_PMA12CFG_SHIFT (0U) +#define CSR_PMACFG3_PMA12CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA12CFG_SHIFT) & CSR_PMACFG3_PMA12CFG_MASK) +#define CSR_PMACFG3_PMA12CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA12CFG_MASK) >> CSR_PMACFG3_PMA12CFG_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * Register Content : Match Size(Byte) + * aaaa. . . aaaaaaaaaaa Reserved + * . . . . . . + * aaaa. . . aa011111111 Reserved + * aaaa. . . a0111111111 2^{12} + * aaaa. . . 01111111111 2^{13} + * . . . . . . + * aa01. . . 11111111111 2^{XLEN} + * a011. . . 11111111111 2^{XLEN+1} + * 0111. . . 11111111111 2^{XLEN+2} + * 1111. . . 11111111111 Reserved + */ +#define CSR_PMAADDR0_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR0_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR0_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR0_PMAADDR_31_2_SHIFT) & CSR_PMAADDR0_PMAADDR_31_2_MASK) +#define CSR_PMAADDR0_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR0_PMAADDR_31_2_MASK) >> CSR_PMAADDR0_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR1_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR1_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR1_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR1_PMAADDR_31_2_SHIFT) & CSR_PMAADDR1_PMAADDR_31_2_MASK) +#define CSR_PMAADDR1_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR1_PMAADDR_31_2_MASK) >> CSR_PMAADDR1_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR2_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR2_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR2_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR2_PMAADDR_31_2_SHIFT) & CSR_PMAADDR2_PMAADDR_31_2_MASK) +#define CSR_PMAADDR2_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR2_PMAADDR_31_2_MASK) >> CSR_PMAADDR2_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR3_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR3_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR3_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR3_PMAADDR_31_2_SHIFT) & CSR_PMAADDR3_PMAADDR_31_2_MASK) +#define CSR_PMAADDR3_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR3_PMAADDR_31_2_MASK) >> CSR_PMAADDR3_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR4_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR4_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR4_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR4_PMAADDR_31_2_SHIFT) & CSR_PMAADDR4_PMAADDR_31_2_MASK) +#define CSR_PMAADDR4_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR4_PMAADDR_31_2_MASK) >> CSR_PMAADDR4_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR5_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR5_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR5_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR5_PMAADDR_31_2_SHIFT) & CSR_PMAADDR5_PMAADDR_31_2_MASK) +#define CSR_PMAADDR5_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR5_PMAADDR_31_2_MASK) >> CSR_PMAADDR5_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR6_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR6_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR6_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR6_PMAADDR_31_2_SHIFT) & CSR_PMAADDR6_PMAADDR_31_2_MASK) +#define CSR_PMAADDR6_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR6_PMAADDR_31_2_MASK) >> CSR_PMAADDR6_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR7_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR7_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR7_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR7_PMAADDR_31_2_SHIFT) & CSR_PMAADDR7_PMAADDR_31_2_MASK) +#define CSR_PMAADDR7_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR7_PMAADDR_31_2_MASK) >> CSR_PMAADDR7_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR8_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR8_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR8_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR8_PMAADDR_31_2_SHIFT) & CSR_PMAADDR8_PMAADDR_31_2_MASK) +#define CSR_PMAADDR8_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR8_PMAADDR_31_2_MASK) >> CSR_PMAADDR8_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR9_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR9_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR9_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR9_PMAADDR_31_2_SHIFT) & CSR_PMAADDR9_PMAADDR_31_2_MASK) +#define CSR_PMAADDR9_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR9_PMAADDR_31_2_MASK) >> CSR_PMAADDR9_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR10_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR10_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR10_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR10_PMAADDR_31_2_SHIFT) & CSR_PMAADDR10_PMAADDR_31_2_MASK) +#define CSR_PMAADDR10_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR10_PMAADDR_31_2_MASK) >> CSR_PMAADDR10_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR11_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR11_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR11_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR11_PMAADDR_31_2_SHIFT) & CSR_PMAADDR11_PMAADDR_31_2_MASK) +#define CSR_PMAADDR11_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR11_PMAADDR_31_2_MASK) >> CSR_PMAADDR11_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR12_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR12_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR12_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR12_PMAADDR_31_2_SHIFT) & CSR_PMAADDR12_PMAADDR_31_2_MASK) +#define CSR_PMAADDR12_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR12_PMAADDR_31_2_MASK) >> CSR_PMAADDR12_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR13_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR13_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR13_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR13_PMAADDR_31_2_SHIFT) & CSR_PMAADDR13_PMAADDR_31_2_MASK) +#define CSR_PMAADDR13_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR13_PMAADDR_31_2_MASK) >> CSR_PMAADDR13_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR14_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR14_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR14_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR14_PMAADDR_31_2_SHIFT) & CSR_PMAADDR14_PMAADDR_31_2_MASK) +#define CSR_PMAADDR14_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR14_PMAADDR_31_2_MASK) >> CSR_PMAADDR14_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR15_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR15_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR15_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR15_PMAADDR_31_2_SHIFT) & CSR_PMAADDR15_PMAADDR_31_2_MASK) +#define CSR_PMAADDR15_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR15_PMAADDR_31_2_MASK) >> CSR_PMAADDR15_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register: CYCLE */ +/* + * CYCLE (RW) + * + * Cycle Counter + */ +#define CSR_CYCLE_CYCLE_MASK (0xFFFFFFFFUL) +#define CSR_CYCLE_CYCLE_SHIFT (0U) +#define CSR_CYCLE_CYCLE_SET(x) (((uint32_t)(x) << CSR_CYCLE_CYCLE_SHIFT) & CSR_CYCLE_CYCLE_MASK) +#define CSR_CYCLE_CYCLE_GET(x) (((uint32_t)(x) & CSR_CYCLE_CYCLE_MASK) >> CSR_CYCLE_CYCLE_SHIFT) + +/* Bitfield definition for register: CYCLEH */ +/* + * CYCLEH (RW) + * + * Cycle Counter Higher 32-bit + */ +#define CSR_CYCLEH_CYCLEH_MASK (0xFFFFFFFFUL) +#define CSR_CYCLEH_CYCLEH_SHIFT (0U) +#define CSR_CYCLEH_CYCLEH_SET(x) (((uint32_t)(x) << CSR_CYCLEH_CYCLEH_SHIFT) & CSR_CYCLEH_CYCLEH_MASK) +#define CSR_CYCLEH_CYCLEH_GET(x) (((uint32_t)(x) & CSR_CYCLEH_CYCLEH_MASK) >> CSR_CYCLEH_CYCLEH_SHIFT) + +/* Bitfield definition for register: MVENDORID */ +/* + * MVENDORID (RO) + * + * The manufacturer ID + */ +#define CSR_MVENDORID_MVENDORID_MASK (0xFFFFFFFFUL) +#define CSR_MVENDORID_MVENDORID_SHIFT (0U) +#define CSR_MVENDORID_MVENDORID_GET(x) (((uint32_t)(x) & CSR_MVENDORID_MVENDORID_MASK) >> CSR_MVENDORID_MVENDORID_SHIFT) + +/* Bitfield definition for register: MARCHID */ +/* + * CPU_ID (RO) + * + * CPU ID + */ +#define CSR_MARCHID_CPU_ID_MASK (0x7FFFFFFFUL) +#define CSR_MARCHID_CPU_ID_SHIFT (0U) +#define CSR_MARCHID_CPU_ID_GET(x) (((uint32_t)(x) & CSR_MARCHID_CPU_ID_MASK) >> CSR_MARCHID_CPU_ID_SHIFT) + +/* Bitfield definition for register: MIMPID */ +/* + * MAJOR (RO) + * + * Revision major + */ +#define CSR_MIMPID_MAJOR_MASK (0xFFFFFF00UL) +#define CSR_MIMPID_MAJOR_SHIFT (8U) +#define CSR_MIMPID_MAJOR_GET(x) (((uint32_t)(x) & CSR_MIMPID_MAJOR_MASK) >> CSR_MIMPID_MAJOR_SHIFT) + +/* + * MINOR (RO) + * + * Revision minor + */ +#define CSR_MIMPID_MINOR_MASK (0xF0U) +#define CSR_MIMPID_MINOR_SHIFT (4U) +#define CSR_MIMPID_MINOR_GET(x) (((uint32_t)(x) & CSR_MIMPID_MINOR_MASK) >> CSR_MIMPID_MINOR_SHIFT) + +/* + * EXTENSION (RO) + * + * Revision extension + */ +#define CSR_MIMPID_EXTENSION_MASK (0xFU) +#define CSR_MIMPID_EXTENSION_SHIFT (0U) +#define CSR_MIMPID_EXTENSION_GET(x) (((uint32_t)(x) & CSR_MIMPID_EXTENSION_MASK) >> CSR_MIMPID_EXTENSION_SHIFT) + +/* Bitfield definition for register: MHARTID */ +/* + * MHARTID (RO) + * + * Hart ID + */ +#define CSR_MHARTID_MHARTID_MASK (0xFFFFFFFFUL) +#define CSR_MHARTID_MHARTID_SHIFT (0U) +#define CSR_MHARTID_MHARTID_GET(x) (((uint32_t)(x) & CSR_MHARTID_MHARTID_MASK) >> CSR_MHARTID_MHARTID_SHIFT) + +/* NON-STANDARD CRS register bitfiled definitions */ + +/* Bitfield definition for register: SCOUNTEREN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTEREN_HPM6_MASK (0x40U) +#define CSR_SCOUNTEREN_HPM6_SHIFT (6U) +#define CSR_SCOUNTEREN_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM6_SHIFT) & CSR_SCOUNTEREN_HPM6_MASK) +#define CSR_SCOUNTEREN_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM6_MASK) >> CSR_SCOUNTEREN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTEREN_HPM5_MASK (0x20U) +#define CSR_SCOUNTEREN_HPM5_SHIFT (5U) +#define CSR_SCOUNTEREN_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM5_SHIFT) & CSR_SCOUNTEREN_HPM5_MASK) +#define CSR_SCOUNTEREN_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM5_MASK) >> CSR_SCOUNTEREN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTEREN_HPM4_MASK (0x10U) +#define CSR_SCOUNTEREN_HPM4_SHIFT (4U) +#define CSR_SCOUNTEREN_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM4_SHIFT) & CSR_SCOUNTEREN_HPM4_MASK) +#define CSR_SCOUNTEREN_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM4_MASK) >> CSR_SCOUNTEREN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTEREN_HPM3_MASK (0x8U) +#define CSR_SCOUNTEREN_HPM3_SHIFT (3U) +#define CSR_SCOUNTEREN_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM3_SHIFT) & CSR_SCOUNTEREN_HPM3_MASK) +#define CSR_SCOUNTEREN_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM3_MASK) >> CSR_SCOUNTEREN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTEREN_IR_MASK (0x4U) +#define CSR_SCOUNTEREN_IR_SHIFT (2U) +#define CSR_SCOUNTEREN_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_IR_SHIFT) & CSR_SCOUNTEREN_IR_MASK) +#define CSR_SCOUNTEREN_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_IR_MASK) >> CSR_SCOUNTEREN_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTEREN_CY_MASK (0x1U) +#define CSR_SCOUNTEREN_CY_SHIFT (0U) +#define CSR_SCOUNTEREN_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_CY_SHIFT) & CSR_SCOUNTEREN_CY_MASK) +#define CSR_SCOUNTEREN_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_CY_MASK) >> CSR_SCOUNTEREN_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTINHIBIT */ +/* + * HPM6 (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_HPM6_MASK (0x40U) +#define CSR_MCOUNTINHIBIT_HPM6_SHIFT (6U) +#define CSR_MCOUNTINHIBIT_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM6_SHIFT) & CSR_MCOUNTINHIBIT_HPM6_MASK) +#define CSR_MCOUNTINHIBIT_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM6_MASK) >> CSR_MCOUNTINHIBIT_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_HPM5_MASK (0x20U) +#define CSR_MCOUNTINHIBIT_HPM5_SHIFT (5U) +#define CSR_MCOUNTINHIBIT_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM5_SHIFT) & CSR_MCOUNTINHIBIT_HPM5_MASK) +#define CSR_MCOUNTINHIBIT_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM5_MASK) >> CSR_MCOUNTINHIBIT_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_HPM4_MASK (0x10U) +#define CSR_MCOUNTINHIBIT_HPM4_SHIFT (4U) +#define CSR_MCOUNTINHIBIT_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM4_SHIFT) & CSR_MCOUNTINHIBIT_HPM4_MASK) +#define CSR_MCOUNTINHIBIT_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM4_MASK) >> CSR_MCOUNTINHIBIT_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_HPM3_MASK (0x8U) +#define CSR_MCOUNTINHIBIT_HPM3_SHIFT (3U) +#define CSR_MCOUNTINHIBIT_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM3_SHIFT) & CSR_MCOUNTINHIBIT_HPM3_MASK) +#define CSR_MCOUNTINHIBIT_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM3_MASK) >> CSR_MCOUNTINHIBIT_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_IR_MASK (0x4U) +#define CSR_MCOUNTINHIBIT_IR_SHIFT (2U) +#define CSR_MCOUNTINHIBIT_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_IR_SHIFT) & CSR_MCOUNTINHIBIT_IR_MASK) +#define CSR_MCOUNTINHIBIT_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_IR_MASK) >> CSR_MCOUNTINHIBIT_IR_SHIFT) + +/* + * TM (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_TM_MASK (0x2U) +#define CSR_MCOUNTINHIBIT_TM_SHIFT (1U) +#define CSR_MCOUNTINHIBIT_TM_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_TM_SHIFT) & CSR_MCOUNTINHIBIT_TM_MASK) +#define CSR_MCOUNTINHIBIT_TM_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_TM_MASK) >> CSR_MCOUNTINHIBIT_TM_SHIFT) + +/* + * CY (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_CY_MASK (0x1U) +#define CSR_MCOUNTINHIBIT_CY_SHIFT (0U) +#define CSR_MCOUNTINHIBIT_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_CY_SHIFT) & CSR_MCOUNTINHIBIT_CY_MASK) +#define CSR_MCOUNTINHIBIT_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_CY_MASK) >> CSR_MCOUNTINHIBIT_CY_SHIFT) + +/* Bitfield definition for register: MILMB */ +/* + * IBPA (RO) + * + * The base physical address of ILM. It has to be an integer multiple of the ILM size + */ +#define CSR_MILMB_IBPA_MASK (0xFFFFFC00UL) +#define CSR_MILMB_IBPA_SHIFT (10U) +#define CSR_MILMB_IBPA_GET(x) (((uint32_t)(x) & CSR_MILMB_IBPA_MASK) >> CSR_MILMB_IBPA_SHIFT) + +/* + * RWECC (RW) + * + * Controls diagnostic accesses of ECC codes of the ILM RAMs. When set, load/store to ILM reads/writes ECC codes to the mecc_code register. This bit can be set for injecting ECC errors to test the ECC handler. + * 0:Disable diagnostic accesses of ECC codes + * 1:Enable diagnostic accesses of ECC codes + */ +#define CSR_MILMB_RWECC_MASK (0x8U) +#define CSR_MILMB_RWECC_SHIFT (3U) +#define CSR_MILMB_RWECC_SET(x) (((uint32_t)(x) << CSR_MILMB_RWECC_SHIFT) & CSR_MILMB_RWECC_MASK) +#define CSR_MILMB_RWECC_GET(x) (((uint32_t)(x) & CSR_MILMB_RWECC_MASK) >> CSR_MILMB_RWECC_SHIFT) + +/* + * ECCEN (RW) + * + * Parity/ECC enable control: + * 0:Disable parity/ECC + * 1:Reserved + * 2:Generate exceptions only on uncorrectable parity/ECC errors + * 3:Generate exceptions on any type of parity/ECC errors + */ +#define CSR_MILMB_ECCEN_MASK (0x6U) +#define CSR_MILMB_ECCEN_SHIFT (1U) +#define CSR_MILMB_ECCEN_SET(x) (((uint32_t)(x) << CSR_MILMB_ECCEN_SHIFT) & CSR_MILMB_ECCEN_MASK) +#define CSR_MILMB_ECCEN_GET(x) (((uint32_t)(x) & CSR_MILMB_ECCEN_MASK) >> CSR_MILMB_ECCEN_SHIFT) + +/* + * IEN (RO) + * + * ILM enable control: + * 0:ILM is disabled + * 1:ILM is enabled + */ +#define CSR_MILMB_IEN_MASK (0x1U) +#define CSR_MILMB_IEN_SHIFT (0U) +#define CSR_MILMB_IEN_GET(x) (((uint32_t)(x) & CSR_MILMB_IEN_MASK) >> CSR_MILMB_IEN_SHIFT) + +/* Bitfield definition for register: MDLMB */ +/* + * DBPA (RO) + * + * The base physical address of DLM. It has to be an integer multiple of the DLM size + */ +#define CSR_MDLMB_DBPA_MASK (0xFFFFFC00UL) +#define CSR_MDLMB_DBPA_SHIFT (10U) +#define CSR_MDLMB_DBPA_GET(x) (((uint32_t)(x) & CSR_MDLMB_DBPA_MASK) >> CSR_MDLMB_DBPA_SHIFT) + +/* + * RWECC (RW) + * + * Controls diagnostic accesses of ECC codes of the DLM RAMs. When set, load/store to DLM reads/writes ECC codes to the mecc_code register. This bit can be set for injecting ECC errors to test the ECC handler. + * 0:Disable diagnostic accesses of ECC codes + * 1:Enable diagnostic accesses of ECC codes + */ +#define CSR_MDLMB_RWECC_MASK (0x8U) +#define CSR_MDLMB_RWECC_SHIFT (3U) +#define CSR_MDLMB_RWECC_SET(x) (((uint32_t)(x) << CSR_MDLMB_RWECC_SHIFT) & CSR_MDLMB_RWECC_MASK) +#define CSR_MDLMB_RWECC_GET(x) (((uint32_t)(x) & CSR_MDLMB_RWECC_MASK) >> CSR_MDLMB_RWECC_SHIFT) + +/* + * ECCEN (RW) + * + * Parity/ECC enable control: + * 0:Disable parity/ECC + * 1:Reserved + * 2:Generate exceptions only on uncorrectable parity/ECC errors + * 3:Generate exceptions on any type of parity/ECC errors + */ +#define CSR_MDLMB_ECCEN_MASK (0x6U) +#define CSR_MDLMB_ECCEN_SHIFT (1U) +#define CSR_MDLMB_ECCEN_SET(x) (((uint32_t)(x) << CSR_MDLMB_ECCEN_SHIFT) & CSR_MDLMB_ECCEN_MASK) +#define CSR_MDLMB_ECCEN_GET(x) (((uint32_t)(x) & CSR_MDLMB_ECCEN_MASK) >> CSR_MDLMB_ECCEN_SHIFT) + +/* + * DEN (RO) + * + * DLM enable control: + * 0:DLM is disabled + * 1:DLM is enabled + */ +#define CSR_MDLMB_DEN_MASK (0x1U) +#define CSR_MDLMB_DEN_SHIFT (0U) +#define CSR_MDLMB_DEN_GET(x) (((uint32_t)(x) & CSR_MDLMB_DEN_MASK) >> CSR_MDLMB_DEN_SHIFT) + +/* Bitfield definition for register: MECC_CODE */ +/* + * INSN (RO) + * + * Indicates if the parity/ECC error is caused by instruction fetch or data access. + * 0:Data access + * 1:Instruction fetch + */ +#define CSR_MECC_CODE_INSN_MASK (0x400000UL) +#define CSR_MECC_CODE_INSN_SHIFT (22U) +#define CSR_MECC_CODE_INSN_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_INSN_MASK) >> CSR_MECC_CODE_INSN_SHIFT) + +/* + * RAMID (RO) + * + * The ID of RAM that caused parity/ECC errors. + * This bit is updated on parity/ECC error exceptions. + * 0–1:Reserved + * 2:Tag RAM of I-Cache + * 3:Data RAM of I-Cache + * 4:Tag RAM of D-Cache + * 5:Data RAM of D-Cache + * 6:Tag RAM of TLB + * 7:Data RAM of TLB + * 8:ILM + * 9:DLM + * 10–15:Reserved + */ +#define CSR_MECC_CODE_RAMID_MASK (0x3C0000UL) +#define CSR_MECC_CODE_RAMID_SHIFT (18U) +#define CSR_MECC_CODE_RAMID_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_RAMID_MASK) >> CSR_MECC_CODE_RAMID_SHIFT) + +/* + * P (RO) + * + * Precise error. This bit is updated on parity/ECC error exceptions. + * 0:Imprecise error + * 1:Precise error + */ +#define CSR_MECC_CODE_P_MASK (0x20000UL) +#define CSR_MECC_CODE_P_SHIFT (17U) +#define CSR_MECC_CODE_P_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_P_MASK) >> CSR_MECC_CODE_P_SHIFT) + +/* + * C (RO) + * + * Correctable error. This bit is updated on parity/ECC error exceptions. + * 0:Uncorrectable error + * 1:Correctable error + */ +#define CSR_MECC_CODE_C_MASK (0x10000UL) +#define CSR_MECC_CODE_C_SHIFT (16U) +#define CSR_MECC_CODE_C_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_C_MASK) >> CSR_MECC_CODE_C_SHIFT) + +/* + * CODE (RW) + * + * This field records the ECC value on ECC error exceptions. This field is also used to read/write the ECC codes when diagnostic access of ECC codes are enabled (milmb.RWECC or mdlmb.RWECC is 1). + */ +#define CSR_MECC_CODE_CODE_MASK (0x7FU) +#define CSR_MECC_CODE_CODE_SHIFT (0U) +#define CSR_MECC_CODE_CODE_SET(x) (((uint32_t)(x) << CSR_MECC_CODE_CODE_SHIFT) & CSR_MECC_CODE_CODE_MASK) +#define CSR_MECC_CODE_CODE_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_CODE_MASK) >> CSR_MECC_CODE_CODE_SHIFT) + +/* Bitfield definition for register: MNVEC */ +/* + * MNVEC (RO) + * + * Base address of the NMI handler. Its value is the zero-extended value of the reset_vector. + */ +#define CSR_MNVEC_MNVEC_MASK (0xFFFFFFFFUL) +#define CSR_MNVEC_MNVEC_SHIFT (0U) +#define CSR_MNVEC_MNVEC_GET(x) (((uint32_t)(x) & CSR_MNVEC_MNVEC_MASK) >> CSR_MNVEC_MNVEC_SHIFT) + +/* Bitfield definition for register: MXSTATUS */ +/* + * PDME (RW) + * + * For saving previous DME state on entering a trap. This field is hardwired to 0 if data cache and data local memory are not supported. + */ +#define CSR_MXSTATUS_PDME_MASK (0x20U) +#define CSR_MXSTATUS_PDME_SHIFT (5U) +#define CSR_MXSTATUS_PDME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PDME_SHIFT) & CSR_MXSTATUS_PDME_MASK) +#define CSR_MXSTATUS_PDME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PDME_MASK) >> CSR_MXSTATUS_PDME_SHIFT) + +/* + * DME (RW) + * + * Data Machine Error flag. It indicates an exception occurred at the data cache or data local memory (DLM). Load/store accesses will bypass D-Cache when this bit is set. The exception handler should clear this bit after the machine error has been dealt with. + */ +#define CSR_MXSTATUS_DME_MASK (0x10U) +#define CSR_MXSTATUS_DME_SHIFT (4U) +#define CSR_MXSTATUS_DME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_DME_SHIFT) & CSR_MXSTATUS_DME_MASK) +#define CSR_MXSTATUS_DME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_DME_MASK) >> CSR_MXSTATUS_DME_SHIFT) + +/* + * PPFT_EN (RW) + * + * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding + * is defined as follows: + * 0: User mode + * 1: Supervisor mode + * 2: Reserved + * 3: Machine mode + */ +#define CSR_MXSTATUS_PPFT_EN_MASK (0x2U) +#define CSR_MXSTATUS_PPFT_EN_SHIFT (1U) +#define CSR_MXSTATUS_PPFT_EN_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PPFT_EN_SHIFT) & CSR_MXSTATUS_PPFT_EN_MASK) +#define CSR_MXSTATUS_PPFT_EN_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PPFT_EN_MASK) >> CSR_MXSTATUS_PPFT_EN_SHIFT) + +/* + * PFT_EN (RW) + * + * Enable performance throttling. When throttling is enabled, the processor executes instructions at the performance level specified in mpft_ctl.T_LEVEL. On entering a trap: + * PPFT_EN <= PFT_EN; + * PFT_EN <= mpft_ctl.FAST_INT ? 0 :PFT_EN; + * On executing an MRET instruction: + * PFT_EN <= PPFT_EN; + * This field is hardwired to 0 if the PowerBrake feature is not supported. + */ +#define CSR_MXSTATUS_PFT_EN_MASK (0x1U) +#define CSR_MXSTATUS_PFT_EN_SHIFT (0U) +#define CSR_MXSTATUS_PFT_EN_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PFT_EN_SHIFT) & CSR_MXSTATUS_PFT_EN_MASK) +#define CSR_MXSTATUS_PFT_EN_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PFT_EN_MASK) >> CSR_MXSTATUS_PFT_EN_SHIFT) + +/* Bitfield definition for register: MPFT_CTL */ +/* + * FAST_INT (RW) + * + * Fast interrupt response. If this field is set, mxstatus.PFT_EN will be automatically cleared when the processor enters an interrupt handler. + */ +#define CSR_MPFT_CTL_FAST_INT_MASK (0x100U) +#define CSR_MPFT_CTL_FAST_INT_SHIFT (8U) +#define CSR_MPFT_CTL_FAST_INT_SET(x) (((uint32_t)(x) << CSR_MPFT_CTL_FAST_INT_SHIFT) & CSR_MPFT_CTL_FAST_INT_MASK) +#define CSR_MPFT_CTL_FAST_INT_GET(x) (((uint32_t)(x) & CSR_MPFT_CTL_FAST_INT_MASK) >> CSR_MPFT_CTL_FAST_INT_SHIFT) + +/* + * T_LEVEL (RW) + * + * Throttling Level. The processor has the highest performance at throttling level 0 and the lowest + * performance at throttling level 15. + * 0:Level 0 (the highest performance) + * 1-14:Level 1-14 + * 15:Level 15 (the lowest performance) + */ +#define CSR_MPFT_CTL_T_LEVEL_MASK (0xF0U) +#define CSR_MPFT_CTL_T_LEVEL_SHIFT (4U) +#define CSR_MPFT_CTL_T_LEVEL_SET(x) (((uint32_t)(x) << CSR_MPFT_CTL_T_LEVEL_SHIFT) & CSR_MPFT_CTL_T_LEVEL_MASK) +#define CSR_MPFT_CTL_T_LEVEL_GET(x) (((uint32_t)(x) & CSR_MPFT_CTL_T_LEVEL_MASK) >> CSR_MPFT_CTL_T_LEVEL_SHIFT) + +/* Bitfield definition for register: MHSP_CTL */ +/* + * M (RW) + * + * Enables the SP protection and recording mechanism in Machine mode + * 0:The mechanism is disabled in Machine mode. + * 1: The mechanism is enabled in Machine mode. + */ +#define CSR_MHSP_CTL_M_MASK (0x20U) +#define CSR_MHSP_CTL_M_SHIFT (5U) +#define CSR_MHSP_CTL_M_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_M_SHIFT) & CSR_MHSP_CTL_M_MASK) +#define CSR_MHSP_CTL_M_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_M_MASK) >> CSR_MHSP_CTL_M_SHIFT) + +/* + * S (RW) + * + * Enables the SP protection and recording mechanism in Supervisor mode + * 0:The mechanism is disabled in Supervisor mode + * 1:The mechanism is enabled in Supervisor mode + */ +#define CSR_MHSP_CTL_S_MASK (0x10U) +#define CSR_MHSP_CTL_S_SHIFT (4U) +#define CSR_MHSP_CTL_S_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_S_SHIFT) & CSR_MHSP_CTL_S_MASK) +#define CSR_MHSP_CTL_S_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_S_MASK) >> CSR_MHSP_CTL_S_SHIFT) + +/* + * U (RW) + * + * Enables the SP protection and recording mechanism in User mode + * 0:The mechanism is disabled in User mode + * 1:The mechanism is enabled in User mode. + */ +#define CSR_MHSP_CTL_U_MASK (0x8U) +#define CSR_MHSP_CTL_U_SHIFT (3U) +#define CSR_MHSP_CTL_U_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_U_SHIFT) & CSR_MHSP_CTL_U_MASK) +#define CSR_MHSP_CTL_U_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_U_MASK) >> CSR_MHSP_CTL_U_SHIFT) + +/* + * SCHM (RW) + * + * Selects the operating scheme of the stack protection and recording mechanism + * 0:Stack overflow/underflow detection + * 1:Top-of-stack recording + */ +#define CSR_MHSP_CTL_SCHM_MASK (0x4U) +#define CSR_MHSP_CTL_SCHM_SHIFT (2U) +#define CSR_MHSP_CTL_SCHM_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_SCHM_SHIFT) & CSR_MHSP_CTL_SCHM_MASK) +#define CSR_MHSP_CTL_SCHM_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_SCHM_MASK) >> CSR_MHSP_CTL_SCHM_SHIFT) + +/* + * UDF_EN (RW) + * + * Enable bit for the stack underflow protection mechanism. This bit will be cleared to 0 automatically by hardware when a stack protection (overflow or underflow) exception is taken. + * 0:The stack underflow protection is disabled + * 1:The stack underflow protection is enabled. + */ +#define CSR_MHSP_CTL_UDF_EN_MASK (0x2U) +#define CSR_MHSP_CTL_UDF_EN_SHIFT (1U) +#define CSR_MHSP_CTL_UDF_EN_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_UDF_EN_SHIFT) & CSR_MHSP_CTL_UDF_EN_MASK) +#define CSR_MHSP_CTL_UDF_EN_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_UDF_EN_MASK) >> CSR_MHSP_CTL_UDF_EN_SHIFT) + +/* + * OVF_EN (RW) + * + * Enable bit for the stack overflow protection and recording mechanism. This bit will be cleared to 0 automatically by hardware when a stack protection (overflow or underflow) exception is taken. + * 0:The stack overflow protection and recording mechanism are disabled. + * 1:The stack overflow protection and recording mechanism are enabled. + */ +#define CSR_MHSP_CTL_OVF_EN_MASK (0x1U) +#define CSR_MHSP_CTL_OVF_EN_SHIFT (0U) +#define CSR_MHSP_CTL_OVF_EN_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_OVF_EN_SHIFT) & CSR_MHSP_CTL_OVF_EN_MASK) +#define CSR_MHSP_CTL_OVF_EN_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_OVF_EN_MASK) >> CSR_MHSP_CTL_OVF_EN_SHIFT) + +/* Bitfield definition for register: MSP_BOUND */ +/* + * MSP_BOUND (RW) + * + * Machine SP Bound + */ +#define CSR_MSP_BOUND_MSP_BOUND_MASK (0xFFFFFFFFUL) +#define CSR_MSP_BOUND_MSP_BOUND_SHIFT (0U) +#define CSR_MSP_BOUND_MSP_BOUND_SET(x) (((uint32_t)(x) << CSR_MSP_BOUND_MSP_BOUND_SHIFT) & CSR_MSP_BOUND_MSP_BOUND_MASK) +#define CSR_MSP_BOUND_MSP_BOUND_GET(x) (((uint32_t)(x) & CSR_MSP_BOUND_MSP_BOUND_MASK) >> CSR_MSP_BOUND_MSP_BOUND_SHIFT) + +/* Bitfield definition for register: MSP_BASE */ +/* + * SP_BASE (RW) + * + * Machine SP base + */ +#define CSR_MSP_BASE_SP_BASE_MASK (0xFFFFFFFFUL) +#define CSR_MSP_BASE_SP_BASE_SHIFT (0U) +#define CSR_MSP_BASE_SP_BASE_SET(x) (((uint32_t)(x) << CSR_MSP_BASE_SP_BASE_SHIFT) & CSR_MSP_BASE_SP_BASE_MASK) +#define CSR_MSP_BASE_SP_BASE_GET(x) (((uint32_t)(x) & CSR_MSP_BASE_SP_BASE_MASK) >> CSR_MSP_BASE_SP_BASE_SHIFT) + +/* Bitfield definition for register: MDCAUSE */ +/* + * PM (RW) + * + * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding is defined as follows: + * 0: User mode + * 1: Supervisor mode + * 2: Reserved + * 3: Machine mode + */ +#define CSR_MDCAUSE_PM_MASK (0x60U) +#define CSR_MDCAUSE_PM_SHIFT (5U) +#define CSR_MDCAUSE_PM_SET(x) (((uint32_t)(x) << CSR_MDCAUSE_PM_SHIFT) & CSR_MDCAUSE_PM_MASK) +#define CSR_MDCAUSE_PM_GET(x) (((uint32_t)(x) & CSR_MDCAUSE_PM_MASK) >> CSR_MDCAUSE_PM_SHIFT) + +/* + * MDCAUSE (RW) + * + * This register further disambiguates causes of traps recorded in the mcause register. + * The value of MDCAUSE for precise exception: + * When mcause == 1 (Instruction access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP instruction access violation; 3:Bus error; 4:PMA empty hole access + * When mcause == 2 (Illegal instruction): + * 0:Please parse the mtval CSR; 1:FP disabled exception; 2:ACE disabled exception + * When mcause == 5 (Load access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception + * When mcause == 7 (Store access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception + * The value of MDCAUSE for imprecise exception: + * When mcause == Local Interrupt 16 or Local Interrupt 272 (16 + 256) (ECC error local interrupt) + * 0:Reserved; 1:LM slave port ECC/Parity error; 2:Imprecise store ECC/Parity error; 3:Imprecise load ECC/Parity error + * When mcause == Local Interrupt 17 or Local Interrupt 273 (17 + 256) (Bus read/write transaction error local interrupt) + * 0:Reserved; 1:Bus read error; 2:Bus write error; 3:PMP error caused by load instructions; 4:PMP error caused by store instructions; 5:PMA error caused by load instructions; 6:PMA error caused by store instructions + */ +#define CSR_MDCAUSE_MDCAUSE_MASK (0x7U) +#define CSR_MDCAUSE_MDCAUSE_SHIFT (0U) +#define CSR_MDCAUSE_MDCAUSE_SET(x) (((uint32_t)(x) << CSR_MDCAUSE_MDCAUSE_SHIFT) & CSR_MDCAUSE_MDCAUSE_MASK) +#define CSR_MDCAUSE_MDCAUSE_GET(x) (((uint32_t)(x) & CSR_MDCAUSE_MDCAUSE_MASK) >> CSR_MDCAUSE_MDCAUSE_SHIFT) + +/* Bitfield definition for register: MCACHE_CTL */ +/* + * DC_WAROUND (RW) + * + * Cache Write-Around threshold + * 0:Disables streaming. All cacheable write misses allocate a cache line according to PMA settings. + * 1:Stop allocating D-Cache entries regardless of PMA settings after consecutive stores to 4 cache lines. + * 2:Stop allocating D-Cache entries regardless of PMA settings after consecutive stores to 64 cache lines. + * 3:Stop allocating D-Cache entries regardless of PMA settings after consecutive stores to 128 cache lines. + */ +#define CSR_MCACHE_CTL_DC_WAROUND_MASK (0x6000U) +#define CSR_MCACHE_CTL_DC_WAROUND_SHIFT (13U) +#define CSR_MCACHE_CTL_DC_WAROUND_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_WAROUND_SHIFT) & CSR_MCACHE_CTL_DC_WAROUND_MASK) +#define CSR_MCACHE_CTL_DC_WAROUND_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_WAROUND_MASK) >> CSR_MCACHE_CTL_DC_WAROUND_SHIFT) + +/* + * DC_FIRST_WORD (RO) + * + * Cache miss allocation filling policy + * 0:Cache line data is returned critical (double) word first + * 1:Cache line data is returned the lowest address (double) word first + */ +#define CSR_MCACHE_CTL_DC_FIRST_WORD_MASK (0x1000U) +#define CSR_MCACHE_CTL_DC_FIRST_WORD_SHIFT (12U) +#define CSR_MCACHE_CTL_DC_FIRST_WORD_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_FIRST_WORD_MASK) >> CSR_MCACHE_CTL_DC_FIRST_WORD_SHIFT) + +/* + * IC_FIRST_WORD (RO) + * + * Cache miss allocation filling policy + * 0:Cache line data is returned critical (double) word first + * 1:Cache line data is returned the lowest address (double) word first + */ +#define CSR_MCACHE_CTL_IC_FIRST_WORD_MASK (0x800U) +#define CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT (11U) +#define CSR_MCACHE_CTL_IC_FIRST_WORD_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_FIRST_WORD_MASK) >> CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT) + +/* + * DPREF_EN (RW) + * + * This bit controls hardware prefetch for load/store accesses to cacheable memory regions when D-Cache size is not 0 + * 0:Disable hardware prefetch on load/store memory accesses + * 1:Enable hardware prefetch on load/store memory accesses + */ +#define CSR_MCACHE_CTL_DPREF_EN_MASK (0x400U) +#define CSR_MCACHE_CTL_DPREF_EN_SHIFT (10U) +#define CSR_MCACHE_CTL_DPREF_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DPREF_EN_SHIFT) & CSR_MCACHE_CTL_DPREF_EN_MASK) +#define CSR_MCACHE_CTL_DPREF_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DPREF_EN_MASK) >> CSR_MCACHE_CTL_DPREF_EN_SHIFT) + +/* + * IPREF_EN (RW) + * + * This bit controls hardware prefetch for instruction fetches to cacheable memory regions when Cache size is not 0 + * 0:Disable hardware prefetch on instruction fetches + * 1:Enable hardware prefetch on instruction fetches + */ +#define CSR_MCACHE_CTL_IPREF_EN_MASK (0x200U) +#define CSR_MCACHE_CTL_IPREF_EN_SHIFT (9U) +#define CSR_MCACHE_CTL_IPREF_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IPREF_EN_SHIFT) & CSR_MCACHE_CTL_IPREF_EN_MASK) +#define CSR_MCACHE_CTL_IPREF_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IPREF_EN_MASK) >> CSR_MCACHE_CTL_IPREF_EN_SHIFT) + +/* + * CCTL_SUEN (RW) + * + * Enable bit for Superuser-mode and User-mode software to access ucctlbeginaddr and ucctlcommand CSRs + * 0:Disable ucctlbeginaddr and ucctlcommand accesses in S/U mode + * 1:Enable ucctlbeginaddr and ucctlcommand accesses in S/U mode + */ +#define CSR_MCACHE_CTL_CCTL_SUEN_MASK (0x100U) +#define CSR_MCACHE_CTL_CCTL_SUEN_SHIFT (8U) +#define CSR_MCACHE_CTL_CCTL_SUEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_CCTL_SUEN_SHIFT) & CSR_MCACHE_CTL_CCTL_SUEN_MASK) +#define CSR_MCACHE_CTL_CCTL_SUEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_CCTL_SUEN_MASK) >> CSR_MCACHE_CTL_CCTL_SUEN_SHIFT) + +/* + * DC_RWECC (RW) + * + * Controls diagnostic accesses of ECC codes of the data cache RAMs. It is set to enable CCTL operations to access the ECC codes. This bit can be set for injecting ECC errors to test the ECC handler + * 0:Disable diagnostic accesses of ECC codes + * 1:Enable diagnostic accesses of ECC codes + */ +#define CSR_MCACHE_CTL_DC_RWECC_MASK (0x80U) +#define CSR_MCACHE_CTL_DC_RWECC_SHIFT (7U) +#define CSR_MCACHE_CTL_DC_RWECC_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_RWECC_SHIFT) & CSR_MCACHE_CTL_DC_RWECC_MASK) +#define CSR_MCACHE_CTL_DC_RWECC_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_RWECC_MASK) >> CSR_MCACHE_CTL_DC_RWECC_SHIFT) + +/* + * IC_RWECC (RW) + * + * Controls diagnostic accesses of ECC codes of the instruction cache RAMs. It is set to enable CCTL operations to access the ECC codes . This bit can be set for injecting ECC errors to test the ECC handler. + * 0:Disable diagnostic accesses of ECC codes + * 1:Enable diagnostic accesses of ECC codes + */ +#define CSR_MCACHE_CTL_IC_RWECC_MASK (0x40U) +#define CSR_MCACHE_CTL_IC_RWECC_SHIFT (6U) +#define CSR_MCACHE_CTL_IC_RWECC_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_RWECC_SHIFT) & CSR_MCACHE_CTL_IC_RWECC_MASK) +#define CSR_MCACHE_CTL_IC_RWECC_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_RWECC_MASK) >> CSR_MCACHE_CTL_IC_RWECC_SHIFT) + +/* + * DC_ECCEN (RW) + * + * Parity/ECC error checking enable control for the + * data cache. + * 0:Disable parity/ECC + * 1:Reserved + * 2:Generate exceptions only on uncorrectable parity/ECC errors + * 3:Generate exceptions on any type of parity/ECC errors + */ +#define CSR_MCACHE_CTL_DC_ECCEN_MASK (0x30U) +#define CSR_MCACHE_CTL_DC_ECCEN_SHIFT (4U) +#define CSR_MCACHE_CTL_DC_ECCEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_ECCEN_SHIFT) & CSR_MCACHE_CTL_DC_ECCEN_MASK) +#define CSR_MCACHE_CTL_DC_ECCEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_ECCEN_MASK) >> CSR_MCACHE_CTL_DC_ECCEN_SHIFT) + +/* + * IC_ECCEN (RW) + * + * Parity/ECC error checking enable control for the + * instruction cache + * 0:Disable parity/ECC + * 1:Reserved + * 2:Generate exceptions only on uncorrectable parity/ECC errors + * 3:Generate exceptions on any type of parity/ECC errors + */ +#define CSR_MCACHE_CTL_IC_ECCEN_MASK (0xCU) +#define CSR_MCACHE_CTL_IC_ECCEN_SHIFT (2U) +#define CSR_MCACHE_CTL_IC_ECCEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_ECCEN_SHIFT) & CSR_MCACHE_CTL_IC_ECCEN_MASK) +#define CSR_MCACHE_CTL_IC_ECCEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_ECCEN_MASK) >> CSR_MCACHE_CTL_IC_ECCEN_SHIFT) + +/* + * DC_EN (RW) + * + * Controls if the data cache is enabled or not. + * 0:D-Cache is disabled + * 1:D-Cache is enabled + */ +#define CSR_MCACHE_CTL_DC_EN_MASK (0x2U) +#define CSR_MCACHE_CTL_DC_EN_SHIFT (1U) +#define CSR_MCACHE_CTL_DC_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_EN_SHIFT) & CSR_MCACHE_CTL_DC_EN_MASK) +#define CSR_MCACHE_CTL_DC_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_EN_MASK) >> CSR_MCACHE_CTL_DC_EN_SHIFT) + +/* + * IC_EN (RW) + * + * Controls if the instruction cache is enabled or not. + * 0:I-Cache is disabled + * 1:I-Cache is enabled + */ +#define CSR_MCACHE_CTL_IC_EN_MASK (0x1U) +#define CSR_MCACHE_CTL_IC_EN_SHIFT (0U) +#define CSR_MCACHE_CTL_IC_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_EN_SHIFT) & CSR_MCACHE_CTL_IC_EN_MASK) +#define CSR_MCACHE_CTL_IC_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_EN_MASK) >> CSR_MCACHE_CTL_IC_EN_SHIFT) + +/* Bitfield definition for register: MCCTLBEGINADDR */ +/* + * VA (RW) + * + * This register holds the address information required by CCTL operations + */ +#define CSR_MCCTLBEGINADDR_VA_MASK (0xFFFFFFFFUL) +#define CSR_MCCTLBEGINADDR_VA_SHIFT (0U) +#define CSR_MCCTLBEGINADDR_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLBEGINADDR_VA_SHIFT) & CSR_MCCTLBEGINADDR_VA_MASK) +#define CSR_MCCTLBEGINADDR_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLBEGINADDR_VA_MASK) >> CSR_MCCTLBEGINADDR_VA_SHIFT) + +/* Bitfield definition for register: MCCTLCOMMAND */ +/* + * VA (RW) + * + * See CCTL Command Definition Table + */ +#define CSR_MCCTLCOMMAND_VA_MASK (0x1FU) +#define CSR_MCCTLCOMMAND_VA_SHIFT (0U) +#define CSR_MCCTLCOMMAND_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLCOMMAND_VA_SHIFT) & CSR_MCCTLCOMMAND_VA_MASK) +#define CSR_MCCTLCOMMAND_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLCOMMAND_VA_MASK) >> CSR_MCCTLCOMMAND_VA_SHIFT) + +/* Bitfield definition for register: MCCTLDATA */ +/* + * VA (RW) + * + * See CCTL Commands Which Access mcctldata Table + */ +#define CSR_MCCTLDATA_VA_MASK (0x1FU) +#define CSR_MCCTLDATA_VA_SHIFT (0U) +#define CSR_MCCTLDATA_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLDATA_VA_SHIFT) & CSR_MCCTLDATA_VA_MASK) +#define CSR_MCCTLDATA_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLDATA_VA_MASK) >> CSR_MCCTLDATA_VA_SHIFT) + +/* Bitfield definition for register: MCOUNTERWEN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_HPM6_MASK (0x40U) +#define CSR_MCOUNTERWEN_HPM6_SHIFT (6U) +#define CSR_MCOUNTERWEN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM6_SHIFT) & CSR_MCOUNTERWEN_HPM6_MASK) +#define CSR_MCOUNTERWEN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM6_MASK) >> CSR_MCOUNTERWEN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_HPM5_MASK (0x20U) +#define CSR_MCOUNTERWEN_HPM5_SHIFT (5U) +#define CSR_MCOUNTERWEN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM5_SHIFT) & CSR_MCOUNTERWEN_HPM5_MASK) +#define CSR_MCOUNTERWEN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM5_MASK) >> CSR_MCOUNTERWEN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_HPM4_MASK (0x10U) +#define CSR_MCOUNTERWEN_HPM4_SHIFT (4U) +#define CSR_MCOUNTERWEN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM4_SHIFT) & CSR_MCOUNTERWEN_HPM4_MASK) +#define CSR_MCOUNTERWEN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM4_MASK) >> CSR_MCOUNTERWEN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_HPM3_MASK (0x8U) +#define CSR_MCOUNTERWEN_HPM3_SHIFT (3U) +#define CSR_MCOUNTERWEN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM3_SHIFT) & CSR_MCOUNTERWEN_HPM3_MASK) +#define CSR_MCOUNTERWEN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM3_MASK) >> CSR_MCOUNTERWEN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_IR_MASK (0x4U) +#define CSR_MCOUNTERWEN_IR_SHIFT (2U) +#define CSR_MCOUNTERWEN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_IR_SHIFT) & CSR_MCOUNTERWEN_IR_MASK) +#define CSR_MCOUNTERWEN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_IR_MASK) >> CSR_MCOUNTERWEN_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_CY_MASK (0x1U) +#define CSR_MCOUNTERWEN_CY_SHIFT (0U) +#define CSR_MCOUNTERWEN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_CY_SHIFT) & CSR_MCOUNTERWEN_CY_MASK) +#define CSR_MCOUNTERWEN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_CY_MASK) >> CSR_MCOUNTERWEN_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTERINTEN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_HPM6_MASK (0x40U) +#define CSR_MCOUNTERINTEN_HPM6_SHIFT (6U) +#define CSR_MCOUNTERINTEN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM6_SHIFT) & CSR_MCOUNTERINTEN_HPM6_MASK) +#define CSR_MCOUNTERINTEN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM6_MASK) >> CSR_MCOUNTERINTEN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_HPM5_MASK (0x20U) +#define CSR_MCOUNTERINTEN_HPM5_SHIFT (5U) +#define CSR_MCOUNTERINTEN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM5_SHIFT) & CSR_MCOUNTERINTEN_HPM5_MASK) +#define CSR_MCOUNTERINTEN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM5_MASK) >> CSR_MCOUNTERINTEN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_HPM4_MASK (0x10U) +#define CSR_MCOUNTERINTEN_HPM4_SHIFT (4U) +#define CSR_MCOUNTERINTEN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM4_SHIFT) & CSR_MCOUNTERINTEN_HPM4_MASK) +#define CSR_MCOUNTERINTEN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM4_MASK) >> CSR_MCOUNTERINTEN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_HPM3_MASK (0x8U) +#define CSR_MCOUNTERINTEN_HPM3_SHIFT (3U) +#define CSR_MCOUNTERINTEN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM3_SHIFT) & CSR_MCOUNTERINTEN_HPM3_MASK) +#define CSR_MCOUNTERINTEN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM3_MASK) >> CSR_MCOUNTERINTEN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_IR_MASK (0x4U) +#define CSR_MCOUNTERINTEN_IR_SHIFT (2U) +#define CSR_MCOUNTERINTEN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_IR_SHIFT) & CSR_MCOUNTERINTEN_IR_MASK) +#define CSR_MCOUNTERINTEN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_IR_MASK) >> CSR_MCOUNTERINTEN_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_CY_MASK (0x1U) +#define CSR_MCOUNTERINTEN_CY_SHIFT (0U) +#define CSR_MCOUNTERINTEN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_CY_SHIFT) & CSR_MCOUNTERINTEN_CY_MASK) +#define CSR_MCOUNTERINTEN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_CY_MASK) >> CSR_MCOUNTERINTEN_CY_SHIFT) + +/* Bitfield definition for register: MMISC_CTL */ +/* + * NBLD_EN (RW) + * + * This field controls the blocking behavior of load instructions. When this bit is clear, load instructions accessing non-device regions are blocking. When this bit is set, load instructions will not be blocking on such occasions and bus errors will no longer be reported synchronously. + * 0:Load to memory regions are blocking. + * 1:Load to memory regions are non-blocking. + */ +#define CSR_MMISC_CTL_NBLD_EN_MASK (0x100U) +#define CSR_MMISC_CTL_NBLD_EN_SHIFT (8U) +#define CSR_MMISC_CTL_NBLD_EN_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_NBLD_EN_SHIFT) & CSR_MMISC_CTL_NBLD_EN_MASK) +#define CSR_MMISC_CTL_NBLD_EN_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_NBLD_EN_MASK) >> CSR_MMISC_CTL_NBLD_EN_SHIFT) + +/* + * MSA_UNA (RW) + * + * This field controls whether the load/store instructions can access misaligned memory locations without generating Address Misaligned exceptions. + * Supported instructions: LW/LH/LHU/SW/SH + * 0:Misaligned accesses generate Address Misaligned exceptions. + * 1:Misaligned accesses generate Address Misaligned exceptions. + */ +#define CSR_MMISC_CTL_MSA_UNA_MASK (0x40U) +#define CSR_MMISC_CTL_MSA_UNA_SHIFT (6U) +#define CSR_MMISC_CTL_MSA_UNA_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_MSA_UNA_SHIFT) & CSR_MMISC_CTL_MSA_UNA_MASK) +#define CSR_MMISC_CTL_MSA_UNA_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_MSA_UNA_MASK) >> CSR_MMISC_CTL_MSA_UNA_SHIFT) + +/* + * BRPE (RW) + * + * Branch prediction enable bit. This bit controls all branch prediction structures. + * 0:Disabled + * 1:Enabled + * This bit is hardwired to 0 if branch prediction structure is not supported. + */ +#define CSR_MMISC_CTL_BRPE_MASK (0x8U) +#define CSR_MMISC_CTL_BRPE_SHIFT (3U) +#define CSR_MMISC_CTL_BRPE_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_BRPE_SHIFT) & CSR_MMISC_CTL_BRPE_MASK) +#define CSR_MMISC_CTL_BRPE_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_BRPE_MASK) >> CSR_MMISC_CTL_BRPE_SHIFT) + +/* + * RVCOMPM (RW) + * + * RISC-V compatibility mode enable bit. If the compatibility mode is turned on, all specific instructions become reserved instructions + * 0:Disabled + * 1:Enabled + */ +#define CSR_MMISC_CTL_RVCOMPM_MASK (0x4U) +#define CSR_MMISC_CTL_RVCOMPM_SHIFT (2U) +#define CSR_MMISC_CTL_RVCOMPM_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_RVCOMPM_SHIFT) & CSR_MMISC_CTL_RVCOMPM_MASK) +#define CSR_MMISC_CTL_RVCOMPM_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_RVCOMPM_MASK) >> CSR_MMISC_CTL_RVCOMPM_SHIFT) + +/* + * VEC_PLIC (RW) + * + * Selects the operation mode of PLIC: + * 0:Regular mode + * 1:Vector mode + * Please note that both this bit and the vector mode enable bit (VECTORED) of the Feature Enable Register in NCEPLIC100 should be turned on for the vectored interrupt support to work correctly. This bit is hardwired to 0 if the vectored PLIC feature is not supported. + */ +#define CSR_MMISC_CTL_VEC_PLIC_MASK (0x2U) +#define CSR_MMISC_CTL_VEC_PLIC_SHIFT (1U) +#define CSR_MMISC_CTL_VEC_PLIC_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_VEC_PLIC_SHIFT) & CSR_MMISC_CTL_VEC_PLIC_MASK) +#define CSR_MMISC_CTL_VEC_PLIC_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_VEC_PLIC_MASK) >> CSR_MMISC_CTL_VEC_PLIC_SHIFT) + +/* Bitfield definition for register: MCOUNTERMASK_M */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_HPM6_MASK (0x40U) +#define CSR_MCOUNTERMASK_M_HPM6_SHIFT (6U) +#define CSR_MCOUNTERMASK_M_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM6_SHIFT) & CSR_MCOUNTERMASK_M_HPM6_MASK) +#define CSR_MCOUNTERMASK_M_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM6_MASK) >> CSR_MCOUNTERMASK_M_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_HPM5_MASK (0x20U) +#define CSR_MCOUNTERMASK_M_HPM5_SHIFT (5U) +#define CSR_MCOUNTERMASK_M_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM5_SHIFT) & CSR_MCOUNTERMASK_M_HPM5_MASK) +#define CSR_MCOUNTERMASK_M_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM5_MASK) >> CSR_MCOUNTERMASK_M_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_HPM4_MASK (0x10U) +#define CSR_MCOUNTERMASK_M_HPM4_SHIFT (4U) +#define CSR_MCOUNTERMASK_M_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM4_SHIFT) & CSR_MCOUNTERMASK_M_HPM4_MASK) +#define CSR_MCOUNTERMASK_M_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM4_MASK) >> CSR_MCOUNTERMASK_M_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_HPM3_MASK (0x8U) +#define CSR_MCOUNTERMASK_M_HPM3_SHIFT (3U) +#define CSR_MCOUNTERMASK_M_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM3_SHIFT) & CSR_MCOUNTERMASK_M_HPM3_MASK) +#define CSR_MCOUNTERMASK_M_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM3_MASK) >> CSR_MCOUNTERMASK_M_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_IR_MASK (0x4U) +#define CSR_MCOUNTERMASK_M_IR_SHIFT (2U) +#define CSR_MCOUNTERMASK_M_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_IR_SHIFT) & CSR_MCOUNTERMASK_M_IR_MASK) +#define CSR_MCOUNTERMASK_M_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_IR_MASK) >> CSR_MCOUNTERMASK_M_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_CY_MASK (0x1U) +#define CSR_MCOUNTERMASK_M_CY_SHIFT (0U) +#define CSR_MCOUNTERMASK_M_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_CY_SHIFT) & CSR_MCOUNTERMASK_M_CY_MASK) +#define CSR_MCOUNTERMASK_M_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_CY_MASK) >> CSR_MCOUNTERMASK_M_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTERMASK_S */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_HPM6_MASK (0x40U) +#define CSR_MCOUNTERMASK_S_HPM6_SHIFT (6U) +#define CSR_MCOUNTERMASK_S_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM6_SHIFT) & CSR_MCOUNTERMASK_S_HPM6_MASK) +#define CSR_MCOUNTERMASK_S_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM6_MASK) >> CSR_MCOUNTERMASK_S_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_HPM5_MASK (0x20U) +#define CSR_MCOUNTERMASK_S_HPM5_SHIFT (5U) +#define CSR_MCOUNTERMASK_S_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM5_SHIFT) & CSR_MCOUNTERMASK_S_HPM5_MASK) +#define CSR_MCOUNTERMASK_S_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM5_MASK) >> CSR_MCOUNTERMASK_S_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_HPM4_MASK (0x10U) +#define CSR_MCOUNTERMASK_S_HPM4_SHIFT (4U) +#define CSR_MCOUNTERMASK_S_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM4_SHIFT) & CSR_MCOUNTERMASK_S_HPM4_MASK) +#define CSR_MCOUNTERMASK_S_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM4_MASK) >> CSR_MCOUNTERMASK_S_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_HPM3_MASK (0x8U) +#define CSR_MCOUNTERMASK_S_HPM3_SHIFT (3U) +#define CSR_MCOUNTERMASK_S_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM3_SHIFT) & CSR_MCOUNTERMASK_S_HPM3_MASK) +#define CSR_MCOUNTERMASK_S_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM3_MASK) >> CSR_MCOUNTERMASK_S_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_IR_MASK (0x4U) +#define CSR_MCOUNTERMASK_S_IR_SHIFT (2U) +#define CSR_MCOUNTERMASK_S_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_IR_SHIFT) & CSR_MCOUNTERMASK_S_IR_MASK) +#define CSR_MCOUNTERMASK_S_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_IR_MASK) >> CSR_MCOUNTERMASK_S_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_CY_MASK (0x1U) +#define CSR_MCOUNTERMASK_S_CY_SHIFT (0U) +#define CSR_MCOUNTERMASK_S_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_CY_SHIFT) & CSR_MCOUNTERMASK_S_CY_MASK) +#define CSR_MCOUNTERMASK_S_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_CY_MASK) >> CSR_MCOUNTERMASK_S_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTERMASK_U */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_HPM6_MASK (0x40U) +#define CSR_MCOUNTERMASK_U_HPM6_SHIFT (6U) +#define CSR_MCOUNTERMASK_U_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM6_SHIFT) & CSR_MCOUNTERMASK_U_HPM6_MASK) +#define CSR_MCOUNTERMASK_U_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM6_MASK) >> CSR_MCOUNTERMASK_U_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_HPM5_MASK (0x20U) +#define CSR_MCOUNTERMASK_U_HPM5_SHIFT (5U) +#define CSR_MCOUNTERMASK_U_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM5_SHIFT) & CSR_MCOUNTERMASK_U_HPM5_MASK) +#define CSR_MCOUNTERMASK_U_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM5_MASK) >> CSR_MCOUNTERMASK_U_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_HPM4_MASK (0x10U) +#define CSR_MCOUNTERMASK_U_HPM4_SHIFT (4U) +#define CSR_MCOUNTERMASK_U_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM4_SHIFT) & CSR_MCOUNTERMASK_U_HPM4_MASK) +#define CSR_MCOUNTERMASK_U_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM4_MASK) >> CSR_MCOUNTERMASK_U_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_HPM3_MASK (0x8U) +#define CSR_MCOUNTERMASK_U_HPM3_SHIFT (3U) +#define CSR_MCOUNTERMASK_U_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM3_SHIFT) & CSR_MCOUNTERMASK_U_HPM3_MASK) +#define CSR_MCOUNTERMASK_U_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM3_MASK) >> CSR_MCOUNTERMASK_U_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_IR_MASK (0x4U) +#define CSR_MCOUNTERMASK_U_IR_SHIFT (2U) +#define CSR_MCOUNTERMASK_U_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_IR_SHIFT) & CSR_MCOUNTERMASK_U_IR_MASK) +#define CSR_MCOUNTERMASK_U_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_IR_MASK) >> CSR_MCOUNTERMASK_U_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_CY_MASK (0x1U) +#define CSR_MCOUNTERMASK_U_CY_SHIFT (0U) +#define CSR_MCOUNTERMASK_U_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_CY_SHIFT) & CSR_MCOUNTERMASK_U_CY_MASK) +#define CSR_MCOUNTERMASK_U_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_CY_MASK) >> CSR_MCOUNTERMASK_U_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTEROVF */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_HPM6_MASK (0x40U) +#define CSR_MCOUNTEROVF_HPM6_SHIFT (6U) +#define CSR_MCOUNTEROVF_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM6_SHIFT) & CSR_MCOUNTEROVF_HPM6_MASK) +#define CSR_MCOUNTEROVF_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM6_MASK) >> CSR_MCOUNTEROVF_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_HPM5_MASK (0x20U) +#define CSR_MCOUNTEROVF_HPM5_SHIFT (5U) +#define CSR_MCOUNTEROVF_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM5_SHIFT) & CSR_MCOUNTEROVF_HPM5_MASK) +#define CSR_MCOUNTEROVF_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM5_MASK) >> CSR_MCOUNTEROVF_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_HPM4_MASK (0x10U) +#define CSR_MCOUNTEROVF_HPM4_SHIFT (4U) +#define CSR_MCOUNTEROVF_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM4_SHIFT) & CSR_MCOUNTEROVF_HPM4_MASK) +#define CSR_MCOUNTEROVF_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM4_MASK) >> CSR_MCOUNTEROVF_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_HPM3_MASK (0x8U) +#define CSR_MCOUNTEROVF_HPM3_SHIFT (3U) +#define CSR_MCOUNTEROVF_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM3_SHIFT) & CSR_MCOUNTEROVF_HPM3_MASK) +#define CSR_MCOUNTEROVF_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM3_MASK) >> CSR_MCOUNTEROVF_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_IR_MASK (0x4U) +#define CSR_MCOUNTEROVF_IR_SHIFT (2U) +#define CSR_MCOUNTEROVF_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_IR_SHIFT) & CSR_MCOUNTEROVF_IR_MASK) +#define CSR_MCOUNTEROVF_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_IR_MASK) >> CSR_MCOUNTEROVF_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_CY_MASK (0x1U) +#define CSR_MCOUNTEROVF_CY_SHIFT (0U) +#define CSR_MCOUNTEROVF_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_CY_SHIFT) & CSR_MCOUNTEROVF_CY_MASK) +#define CSR_MCOUNTEROVF_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_CY_MASK) >> CSR_MCOUNTEROVF_CY_SHIFT) + +/* Bitfield definition for register: MSLIDELEG */ +/* + * PMOVI (RW) + * + * Delegate S-mode performance monitor overflow local interrupt to S-mode. + * 0:Do not delegate to S-mode. + * 1:Delegate to S-mode. + */ +#define CSR_MSLIDELEG_PMOVI_MASK (0x40000UL) +#define CSR_MSLIDELEG_PMOVI_SHIFT (18U) +#define CSR_MSLIDELEG_PMOVI_SET(x) (((uint32_t)(x) << CSR_MSLIDELEG_PMOVI_SHIFT) & CSR_MSLIDELEG_PMOVI_MASK) +#define CSR_MSLIDELEG_PMOVI_GET(x) (((uint32_t)(x) & CSR_MSLIDELEG_PMOVI_MASK) >> CSR_MSLIDELEG_PMOVI_SHIFT) + +/* + * BWEI (RW) + * + * Delegate S-mode bus read/write transaction error local interrupt to S-mode + * 0:Do not delegate to S-mode. + * 1:Delegate to S-mode. + */ +#define CSR_MSLIDELEG_BWEI_MASK (0x20000UL) +#define CSR_MSLIDELEG_BWEI_SHIFT (17U) +#define CSR_MSLIDELEG_BWEI_SET(x) (((uint32_t)(x) << CSR_MSLIDELEG_BWEI_SHIFT) & CSR_MSLIDELEG_BWEI_MASK) +#define CSR_MSLIDELEG_BWEI_GET(x) (((uint32_t)(x) & CSR_MSLIDELEG_BWEI_MASK) >> CSR_MSLIDELEG_BWEI_SHIFT) + +/* + * IMECCI (RW) + * + * Delegate S-mode slave-port ECC error local interrupt to S-mode + * 0:Do not delegate to S-mode. + * 1:Delegate to S-mode. + */ +#define CSR_MSLIDELEG_IMECCI_MASK (0x10000UL) +#define CSR_MSLIDELEG_IMECCI_SHIFT (16U) +#define CSR_MSLIDELEG_IMECCI_SET(x) (((uint32_t)(x) << CSR_MSLIDELEG_IMECCI_SHIFT) & CSR_MSLIDELEG_IMECCI_MASK) +#define CSR_MSLIDELEG_IMECCI_GET(x) (((uint32_t)(x) & CSR_MSLIDELEG_IMECCI_MASK) >> CSR_MSLIDELEG_IMECCI_SHIFT) + +/* Bitfield definition for register: MCLK_CTL */ +/* + * FUNIT (RW) + * + * Level 2 clock gating enable for function units listed in the following table. + * 16:integer arithmetic unit + * 17:integer permutation unit + * 18:integer mask unit + * 19:integer division unit + * 20:integer multiply and add unit + * 21:floating-point multiply and add + * unit + * 22:floating-point miscellaneous unit + * 23:floating-point division unit + * 24:load/store unit + * 31:25:Reserved + */ +#define CSR_MCLK_CTL_FUNIT_MASK (0xFFFF0000UL) +#define CSR_MCLK_CTL_FUNIT_SHIFT (16U) +#define CSR_MCLK_CTL_FUNIT_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_FUNIT_SHIFT) & CSR_MCLK_CTL_FUNIT_MASK) +#define CSR_MCLK_CTL_FUNIT_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_FUNIT_MASK) >> CSR_MCLK_CTL_FUNIT_SHIFT) + +/* + * VI (RW) + * + * Level 1 clock gating enable for the vector/floating-point issue queues. + */ +#define CSR_MCLK_CTL_VI_MASK (0x8000U) +#define CSR_MCLK_CTL_VI_SHIFT (15U) +#define CSR_MCLK_CTL_VI_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_VI_SHIFT) & CSR_MCLK_CTL_VI_MASK) +#define CSR_MCLK_CTL_VI_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_VI_MASK) >> CSR_MCLK_CTL_VI_SHIFT) + +/* + * VR (RW) + * + * Level 1 clock gating enable for the vector/floating-point register file. + */ +#define CSR_MCLK_CTL_VR_MASK (0x4000U) +#define CSR_MCLK_CTL_VR_SHIFT (14U) +#define CSR_MCLK_CTL_VR_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_VR_SHIFT) & CSR_MCLK_CTL_VR_MASK) +#define CSR_MCLK_CTL_VR_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_VR_MASK) >> CSR_MCLK_CTL_VR_SHIFT) + +/* + * AQ (RW) + * + * Level 1 clock gating enable for ACE load/store queues. + */ +#define CSR_MCLK_CTL_AQ_MASK (0x2000U) +#define CSR_MCLK_CTL_AQ_SHIFT (13U) +#define CSR_MCLK_CTL_AQ_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_AQ_SHIFT) & CSR_MCLK_CTL_AQ_MASK) +#define CSR_MCLK_CTL_AQ_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_AQ_MASK) >> CSR_MCLK_CTL_AQ_SHIFT) + +/* + * DQ (RW) + * + * Level 1 clock gating enable for data cache load/store queues. + */ +#define CSR_MCLK_CTL_DQ_MASK (0x1000U) +#define CSR_MCLK_CTL_DQ_SHIFT (12U) +#define CSR_MCLK_CTL_DQ_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_DQ_SHIFT) & CSR_MCLK_CTL_DQ_MASK) +#define CSR_MCLK_CTL_DQ_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_DQ_MASK) >> CSR_MCLK_CTL_DQ_SHIFT) + +/* + * UQ (RW) + * + * Level 1 clock gating enable for uncached queues + */ +#define CSR_MCLK_CTL_UQ_MASK (0x800U) +#define CSR_MCLK_CTL_UQ_SHIFT (11U) +#define CSR_MCLK_CTL_UQ_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_UQ_SHIFT) & CSR_MCLK_CTL_UQ_MASK) +#define CSR_MCLK_CTL_UQ_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_UQ_MASK) >> CSR_MCLK_CTL_UQ_SHIFT) + +/* + * FP (RW) + * + * Level 1 clock gating enable for scalar floating point issue unit and queues. + */ +#define CSR_MCLK_CTL_FP_MASK (0x400U) +#define CSR_MCLK_CTL_FP_SHIFT (10U) +#define CSR_MCLK_CTL_FP_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_FP_SHIFT) & CSR_MCLK_CTL_FP_MASK) +#define CSR_MCLK_CTL_FP_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_FP_MASK) >> CSR_MCLK_CTL_FP_SHIFT) + +/* + * CLKGATE (RW) + * + * One-hot clock gating levels. + * 0:Level 1 clock gating in module level + * 1:Level 2 clock gating in unit level + * 2:Level 3 clock gating in VPU level + * 7:3:Reserved + */ +#define CSR_MCLK_CTL_CLKGATE_MASK (0xFFU) +#define CSR_MCLK_CTL_CLKGATE_SHIFT (0U) +#define CSR_MCLK_CTL_CLKGATE_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_CLKGATE_SHIFT) & CSR_MCLK_CTL_CLKGATE_MASK) +#define CSR_MCLK_CTL_CLKGATE_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_CLKGATE_MASK) >> CSR_MCLK_CTL_CLKGATE_SHIFT) + +/* Bitfield definition for register: DEXC2DBG */ +/* + * PMOV (RW) + * + * Indicates whether performance counter overflow interrupts are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_PMOV_MASK (0x80000UL) +#define CSR_DEXC2DBG_PMOV_SHIFT (19U) +#define CSR_DEXC2DBG_PMOV_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_PMOV_SHIFT) & CSR_DEXC2DBG_PMOV_MASK) +#define CSR_DEXC2DBG_PMOV_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_PMOV_MASK) >> CSR_DEXC2DBG_PMOV_SHIFT) + +/* + * SPF (RW) + * + * Indicates whether store page fault exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SPF_MASK (0x40000UL) +#define CSR_DEXC2DBG_SPF_SHIFT (18U) +#define CSR_DEXC2DBG_SPF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SPF_SHIFT) & CSR_DEXC2DBG_SPF_MASK) +#define CSR_DEXC2DBG_SPF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SPF_MASK) >> CSR_DEXC2DBG_SPF_SHIFT) + +/* + * LPF (RW) + * + * Indicates whether load fault exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_LPF_MASK (0x20000UL) +#define CSR_DEXC2DBG_LPF_SHIFT (17U) +#define CSR_DEXC2DBG_LPF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LPF_SHIFT) & CSR_DEXC2DBG_LPF_MASK) +#define CSR_DEXC2DBG_LPF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LPF_MASK) >> CSR_DEXC2DBG_LPF_SHIFT) + +/* + * IPF (RW) + * + * Indicates whether instruction page fault exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_IPF_MASK (0x10000UL) +#define CSR_DEXC2DBG_IPF_SHIFT (16U) +#define CSR_DEXC2DBG_IPF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IPF_SHIFT) & CSR_DEXC2DBG_IPF_MASK) +#define CSR_DEXC2DBG_IPF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IPF_MASK) >> CSR_DEXC2DBG_IPF_SHIFT) + +/* + * BWE (RW) + * + * Indicates whether Bus-write Transaction Error local interrupts are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_BWE_MASK (0x8000U) +#define CSR_DEXC2DBG_BWE_SHIFT (15U) +#define CSR_DEXC2DBG_BWE_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_BWE_SHIFT) & CSR_DEXC2DBG_BWE_MASK) +#define CSR_DEXC2DBG_BWE_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_BWE_MASK) >> CSR_DEXC2DBG_BWE_SHIFT) + +/* + * SLPECC (RW) + * + * Indicates whether local memory slave port ECC Error local interrupts are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SLPECC_MASK (0x4000U) +#define CSR_DEXC2DBG_SLPECC_SHIFT (14U) +#define CSR_DEXC2DBG_SLPECC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SLPECC_SHIFT) & CSR_DEXC2DBG_SLPECC_MASK) +#define CSR_DEXC2DBG_SLPECC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SLPECC_MASK) >> CSR_DEXC2DBG_SLPECC_SHIFT) + +/* + * ACE (RW) + * + * Indicates whether ACE-related exceptions are redirected to enter Debug Mode. This bit is present only when mmsc_cfg.ACE is set + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_ACE_MASK (0x2000U) +#define CSR_DEXC2DBG_ACE_SHIFT (13U) +#define CSR_DEXC2DBG_ACE_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_ACE_SHIFT) & CSR_DEXC2DBG_ACE_MASK) +#define CSR_DEXC2DBG_ACE_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_ACE_MASK) >> CSR_DEXC2DBG_ACE_SHIFT) + +/* + * HSP (RW) + * + * Indicates whether Stack Protection exceptions are redirected to enter Debug Mode. This bit is present only when mmsc_cfg.HSP is set. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_HSP_MASK (0x1000U) +#define CSR_DEXC2DBG_HSP_SHIFT (12U) +#define CSR_DEXC2DBG_HSP_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_HSP_SHIFT) & CSR_DEXC2DBG_HSP_MASK) +#define CSR_DEXC2DBG_HSP_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_HSP_MASK) >> CSR_DEXC2DBG_HSP_SHIFT) + +/* + * MEC (RW) + * + * Indicates whether M-mode Environment Call exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_MEC_MASK (0x800U) +#define CSR_DEXC2DBG_MEC_SHIFT (11U) +#define CSR_DEXC2DBG_MEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_MEC_SHIFT) & CSR_DEXC2DBG_MEC_MASK) +#define CSR_DEXC2DBG_MEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_MEC_MASK) >> CSR_DEXC2DBG_MEC_SHIFT) + +/* + * SEC (RW) + * + * Indicates whether S-mode Environment Call exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SEC_MASK (0x200U) +#define CSR_DEXC2DBG_SEC_SHIFT (9U) +#define CSR_DEXC2DBG_SEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SEC_SHIFT) & CSR_DEXC2DBG_SEC_MASK) +#define CSR_DEXC2DBG_SEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SEC_MASK) >> CSR_DEXC2DBG_SEC_SHIFT) + +/* + * UEC (RW) + * + * Indicates whether U-mode Environment Call exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_UEC_MASK (0x100U) +#define CSR_DEXC2DBG_UEC_SHIFT (8U) +#define CSR_DEXC2DBG_UEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_UEC_SHIFT) & CSR_DEXC2DBG_UEC_MASK) +#define CSR_DEXC2DBG_UEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_UEC_MASK) >> CSR_DEXC2DBG_UEC_SHIFT) + +/* + * SAF (RW) + * + * Indicates whether Store Access Fault exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SAF_MASK (0x80U) +#define CSR_DEXC2DBG_SAF_SHIFT (7U) +#define CSR_DEXC2DBG_SAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SAF_SHIFT) & CSR_DEXC2DBG_SAF_MASK) +#define CSR_DEXC2DBG_SAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SAF_MASK) >> CSR_DEXC2DBG_SAF_SHIFT) + +/* + * SAM (RW) + * + * Indicates whether Store Access Misaligned exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SAM_MASK (0x40U) +#define CSR_DEXC2DBG_SAM_SHIFT (6U) +#define CSR_DEXC2DBG_SAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SAM_SHIFT) & CSR_DEXC2DBG_SAM_MASK) +#define CSR_DEXC2DBG_SAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SAM_MASK) >> CSR_DEXC2DBG_SAM_SHIFT) + +/* + * LAF (RW) + * + * Indicates whether Load Access Fault exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_LAF_MASK (0x20U) +#define CSR_DEXC2DBG_LAF_SHIFT (5U) +#define CSR_DEXC2DBG_LAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LAF_SHIFT) & CSR_DEXC2DBG_LAF_MASK) +#define CSR_DEXC2DBG_LAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LAF_MASK) >> CSR_DEXC2DBG_LAF_SHIFT) + +/* + * LAM (RW) + * + * Indicates whether Load Access Misaligned exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_LAM_MASK (0x10U) +#define CSR_DEXC2DBG_LAM_SHIFT (4U) +#define CSR_DEXC2DBG_LAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LAM_SHIFT) & CSR_DEXC2DBG_LAM_MASK) +#define CSR_DEXC2DBG_LAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LAM_MASK) >> CSR_DEXC2DBG_LAM_SHIFT) + +/* + * NMI (RW) + * + * Indicates whether Non-Maskable Interrupt + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_NMI_MASK (0x8U) +#define CSR_DEXC2DBG_NMI_SHIFT (3U) +#define CSR_DEXC2DBG_NMI_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_NMI_SHIFT) & CSR_DEXC2DBG_NMI_MASK) +#define CSR_DEXC2DBG_NMI_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_NMI_MASK) >> CSR_DEXC2DBG_NMI_SHIFT) + +/* + * II (RW) + * + * Indicates whether Illegal Instruction exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_II_MASK (0x4U) +#define CSR_DEXC2DBG_II_SHIFT (2U) +#define CSR_DEXC2DBG_II_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_II_SHIFT) & CSR_DEXC2DBG_II_MASK) +#define CSR_DEXC2DBG_II_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_II_MASK) >> CSR_DEXC2DBG_II_SHIFT) + +/* + * IAF (RW) + * + * Indicates whether Instruction Access Fault exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_IAF_MASK (0x2U) +#define CSR_DEXC2DBG_IAF_SHIFT (1U) +#define CSR_DEXC2DBG_IAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IAF_SHIFT) & CSR_DEXC2DBG_IAF_MASK) +#define CSR_DEXC2DBG_IAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IAF_MASK) >> CSR_DEXC2DBG_IAF_SHIFT) + +/* + * IAM (RW) + * + * Indicates whether Instruction Access Misaligned exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_IAM_MASK (0x1U) +#define CSR_DEXC2DBG_IAM_SHIFT (0U) +#define CSR_DEXC2DBG_IAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IAM_SHIFT) & CSR_DEXC2DBG_IAM_MASK) +#define CSR_DEXC2DBG_IAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IAM_MASK) >> CSR_DEXC2DBG_IAM_SHIFT) + +/* Bitfield definition for register: DDCAUSE */ +/* + * SUBTYPE (RO) + * + * Subtypes for main type. + * The table below lists the subtypes for DCSR.CAUSE==1 and DDCAUSE.MAINTYPE==3. + * 0:Illegal instruction + * 1:Privileged instruction + * 2:Non-existent CSR + * 3:Privilege CSR access + * 4:Read-only CSR update + */ +#define CSR_DDCAUSE_SUBTYPE_MASK (0xFF00U) +#define CSR_DDCAUSE_SUBTYPE_SHIFT (8U) +#define CSR_DDCAUSE_SUBTYPE_GET(x) (((uint32_t)(x) & CSR_DDCAUSE_SUBTYPE_MASK) >> CSR_DDCAUSE_SUBTYPE_SHIFT) + +/* + * MAINTYPE (RO) + * + * Cause for redirection to Debug Mode. + * 0:Software Breakpoint (EBREAK) + * 1:Instruction Access Misaligned (IAM) + * 2:Instruction Access Fault (IAF) + * 3:Illegal Instruction (II) + * 4:Non-Maskable Interrupt (NMI) + * 5:Load Access Misaligned (LAM) + * 6:Load Access Fault (LAF) + * 7:Store Access Misaligned (SAM) + * 8:Store Access Fault (SAF) + * 9:U-mode Environment Call (UEC) + * 10:S-mode Environment Call (SEC) + * 11:Instruction page fault + * 12:M-mode Environment Call (MEC) + * 13:Load page fault + * 14:Reserved + * 15:Store/AMO page fault + * 16:Imprecise ECC error + * 17;Bus write transaction error + * 18:Performance Counter overflow + * 19–31:Reserved + * 32:Stack overflow exception + * 33:Stack underflow exception + * 34:ACE disabled exception + * 35–39:Reserved + * 40–47:ACE exception + * ≥48:Reserved + */ +#define CSR_DDCAUSE_MAINTYPE_MASK (0xFFU) +#define CSR_DDCAUSE_MAINTYPE_SHIFT (0U) +#define CSR_DDCAUSE_MAINTYPE_GET(x) (((uint32_t)(x) & CSR_DDCAUSE_MAINTYPE_MASK) >> CSR_DDCAUSE_MAINTYPE_SHIFT) + +/* Bitfield definition for register: UITB */ +/* + * ADDR (RW) + * + * The base address of the CoDense instruction table. This field is reserved if uitb.HW == 1. + */ +#define CSR_UITB_ADDR_MASK (0xFFFFFFFCUL) +#define CSR_UITB_ADDR_SHIFT (2U) +#define CSR_UITB_ADDR_SET(x) (((uint32_t)(x) << CSR_UITB_ADDR_SHIFT) & CSR_UITB_ADDR_MASK) +#define CSR_UITB_ADDR_GET(x) (((uint32_t)(x) & CSR_UITB_ADDR_MASK) >> CSR_UITB_ADDR_SHIFT) + +/* + * HW (RO) + * + * This bit specifies if the CoDense instruction table is hardwired. + * 0:The instruction table is located in memory. uitb.ADDR should be initialized to point to the table before using the CoDense instructions. + * 1:The instruction table is hardwired. Initialization of uitb.ADDR is not needed before using the CoDense instructions. + */ +#define CSR_UITB_HW_MASK (0x1U) +#define CSR_UITB_HW_SHIFT (0U) +#define CSR_UITB_HW_GET(x) (((uint32_t)(x) & CSR_UITB_HW_MASK) >> CSR_UITB_HW_SHIFT) + +/* Bitfield definition for register: UCODE */ +/* + * OV (RW) + * + * Overflow flag. It will be set by DSP instructions with a saturated result. + * 0:A saturated result is not generated + * 1:A saturated result is generated + */ +#define CSR_UCODE_OV_MASK (0x1U) +#define CSR_UCODE_OV_SHIFT (0U) +#define CSR_UCODE_OV_SET(x) (((uint32_t)(x) << CSR_UCODE_OV_SHIFT) & CSR_UCODE_OV_MASK) +#define CSR_UCODE_OV_GET(x) (((uint32_t)(x) & CSR_UCODE_OV_MASK) >> CSR_UCODE_OV_SHIFT) + +/* Bitfield definition for register: UDCAUSE */ +/* + * UDCAUSE (RW) + * + * This register further disambiguates causes of traps recorded in the ucause register. See the list below for details. + * The value of UDCAUSE for precise exception: + * When ucause == 1 (Instruction access fault) + * 0:Reserved + * 1:ECC/Parity error + * 2:PMP instruction access violation + * 3:Bus error + * 4:PMA empty hole access + * When ucause == 2 (Illegal instruction) + * 0:Please parse the utval CSR + * 1:FP disabled exception + * 2:ACE disabled exception + * When ucause == 5 (Load access fault) + * 0:Reserved + * 1:ECC/Parity error + * 2:PMP load access violation + * 3:Bus error + * 4:Misaligned address + * 5:PMA empty hole access + * 6:PMA attribute inconsistency + * 7:PMA NAMO exception + * When ucause == 7 (Store access fault) + * 0:Reserved + * 1:ECC/Parity error + * 2:PMP store access violation + * 3:Bus error + * 4:Misaligned address + * 5:PMA empty hole access + * 6:PMA attribute inconsistency + * 7:PMA NAMO exception + */ +#define CSR_UDCAUSE_UDCAUSE_MASK (0x7U) +#define CSR_UDCAUSE_UDCAUSE_SHIFT (0U) +#define CSR_UDCAUSE_UDCAUSE_SET(x) (((uint32_t)(x) << CSR_UDCAUSE_UDCAUSE_SHIFT) & CSR_UDCAUSE_UDCAUSE_MASK) +#define CSR_UDCAUSE_UDCAUSE_GET(x) (((uint32_t)(x) & CSR_UDCAUSE_UDCAUSE_MASK) >> CSR_UDCAUSE_UDCAUSE_SHIFT) + +/* Bitfield definition for register: UCCTLBEGINADDR */ +/* + * VA (RW) + * + * It is an alias to the mcctlbeginaddr register and it is only accessible to Supervisor-mode and User-mode software when mcache_ctl.CCTL_SUEN is 1. Otherwise illegal instruction exceptions will be triggered. + */ +#define CSR_UCCTLBEGINADDR_VA_MASK (0xFFFFFFFFUL) +#define CSR_UCCTLBEGINADDR_VA_SHIFT (0U) +#define CSR_UCCTLBEGINADDR_VA_SET(x) (((uint32_t)(x) << CSR_UCCTLBEGINADDR_VA_SHIFT) & CSR_UCCTLBEGINADDR_VA_MASK) +#define CSR_UCCTLBEGINADDR_VA_GET(x) (((uint32_t)(x) & CSR_UCCTLBEGINADDR_VA_MASK) >> CSR_UCCTLBEGINADDR_VA_SHIFT) + +/* Bitfield definition for register: UCCTLCOMMAND */ +/* + * VA (RW) + * + * See User CCTL Command Definition Table + */ +#define CSR_UCCTLCOMMAND_VA_MASK (0x1FU) +#define CSR_UCCTLCOMMAND_VA_SHIFT (0U) +#define CSR_UCCTLCOMMAND_VA_SET(x) (((uint32_t)(x) << CSR_UCCTLCOMMAND_VA_SHIFT) & CSR_UCCTLCOMMAND_VA_MASK) +#define CSR_UCCTLCOMMAND_VA_GET(x) (((uint32_t)(x) & CSR_UCCTLCOMMAND_VA_MASK) >> CSR_UCCTLCOMMAND_VA_SHIFT) + +/* Bitfield definition for register: SLIE */ +/* + * PMOVI (RW) + * + * Enable S-mode performance monitor overflow local interrupt. + * 0:Local interrupt is not enabled. + * 1:Local interrupt is enabled + */ +#define CSR_SLIE_PMOVI_MASK (0x40000UL) +#define CSR_SLIE_PMOVI_SHIFT (18U) +#define CSR_SLIE_PMOVI_SET(x) (((uint32_t)(x) << CSR_SLIE_PMOVI_SHIFT) & CSR_SLIE_PMOVI_MASK) +#define CSR_SLIE_PMOVI_GET(x) (((uint32_t)(x) & CSR_SLIE_PMOVI_MASK) >> CSR_SLIE_PMOVI_SHIFT) + +/* + * BWEI (RW) + * + * Enable S-mode bus read/write transaction error local interrupt. The processor may receive bus errors on load/store instructions or cache writebacks. + * 0:Local interrupt is not enabled. + * 1:Local interrupt is enabled + */ +#define CSR_SLIE_BWEI_MASK (0x20000UL) +#define CSR_SLIE_BWEI_SHIFT (17U) +#define CSR_SLIE_BWEI_SET(x) (((uint32_t)(x) << CSR_SLIE_BWEI_SHIFT) & CSR_SLIE_BWEI_MASK) +#define CSR_SLIE_BWEI_GET(x) (((uint32_t)(x) & CSR_SLIE_BWEI_MASK) >> CSR_SLIE_BWEI_SHIFT) + +/* + * IMECCI (RW) + * + * Enable S-mode slave-port ECC error local interrupt. + * 0:Local interrupt is not enabled. + * 1:Local interrupt is enabled + */ +#define CSR_SLIE_IMECCI_MASK (0x10000UL) +#define CSR_SLIE_IMECCI_SHIFT (16U) +#define CSR_SLIE_IMECCI_SET(x) (((uint32_t)(x) << CSR_SLIE_IMECCI_SHIFT) & CSR_SLIE_IMECCI_MASK) +#define CSR_SLIE_IMECCI_GET(x) (((uint32_t)(x) & CSR_SLIE_IMECCI_MASK) >> CSR_SLIE_IMECCI_SHIFT) + +/* Bitfield definition for register: SLIP */ +/* + * PMOVI (RW) + * + * Pending control and status of S-mode performance monitor overflow local interrupt. + * 0:Local interrupt is not enabled. + * 1:Local interrupt is enabled + */ +#define CSR_SLIP_PMOVI_MASK (0x40000UL) +#define CSR_SLIP_PMOVI_SHIFT (18U) +#define CSR_SLIP_PMOVI_SET(x) (((uint32_t)(x) << CSR_SLIP_PMOVI_SHIFT) & CSR_SLIP_PMOVI_MASK) +#define CSR_SLIP_PMOVI_GET(x) (((uint32_t)(x) & CSR_SLIP_PMOVI_MASK) >> CSR_SLIP_PMOVI_SHIFT) + +/* + * BWEI (RW) + * + * Pending control and status of S-mode bus read/write transaction error local interrupt. The processor may receive bus errors on load/store instructions or cache writebacks. + * 0:Local interrupt is not enabled. + * 1:Local interrupt is enabled + */ +#define CSR_SLIP_BWEI_MASK (0x20000UL) +#define CSR_SLIP_BWEI_SHIFT (17U) +#define CSR_SLIP_BWEI_SET(x) (((uint32_t)(x) << CSR_SLIP_BWEI_SHIFT) & CSR_SLIP_BWEI_MASK) +#define CSR_SLIP_BWEI_GET(x) (((uint32_t)(x) & CSR_SLIP_BWEI_MASK) >> CSR_SLIP_BWEI_SHIFT) + +/* + * IMECCI (RW) + * + * Pending control and status of S-mode slave-port ECC error local interrupt.. + * 0:Local interrupt is not enabled. + * 1:Local interrupt is enabled + */ +#define CSR_SLIP_IMECCI_MASK (0x10000UL) +#define CSR_SLIP_IMECCI_SHIFT (16U) +#define CSR_SLIP_IMECCI_SET(x) (((uint32_t)(x) << CSR_SLIP_IMECCI_SHIFT) & CSR_SLIP_IMECCI_MASK) +#define CSR_SLIP_IMECCI_GET(x) (((uint32_t)(x) & CSR_SLIP_IMECCI_MASK) >> CSR_SLIP_IMECCI_SHIFT) + +/* Bitfield definition for register: SDCAUSE */ +/* + * PM (RW) + * + * When scause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding is defined as follows: + * 0:User mode + * 1:Supervisor mode + * 2:Reserved + * 3:Machine mode + */ +#define CSR_SDCAUSE_PM_MASK (0x60U) +#define CSR_SDCAUSE_PM_SHIFT (5U) +#define CSR_SDCAUSE_PM_SET(x) (((uint32_t)(x) << CSR_SDCAUSE_PM_SHIFT) & CSR_SDCAUSE_PM_MASK) +#define CSR_SDCAUSE_PM_GET(x) (((uint32_t)(x) & CSR_SDCAUSE_PM_MASK) >> CSR_SDCAUSE_PM_SHIFT) + +/* + * SDCAUSE (RW) + * + * This register further disambiguates causes of traps recorded in the scause register. See the list below for details. + * The value of SDCAUSE for precise exception: + * When scause == 1 (Instruction access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP instruction access violation; 3:Bus error; 4:PMA empty hole access + * When scause == 2 (Illegal instruction): + * 0:Please parse the stval CSR; 1:FP disabled exception; 2:ACE disabled exception + * When scause == 5 (Load access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception + * When scause == 7 (Store access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception + * The value of SDCAUSE for imprecise exception: + * When scause == Local Interrupt 16 or Local Interrupt 272 (16 + 256) (ECC error local interrupt) + * 0:Reserved; 1:LM slave port ECC/Parity error; 2:Imprecise store ECC/Parity error; 3:Imprecise load ECC/Parity error + * When scause == Local Interrupt 17 or Local Interrupt 273 (17 + 256) (Bus read/write transaction error local interrupt) + * 0:Reserved; 1:Bus read error; 2:Bus write error; 3:PMP error caused by load instructions; 4:PMP error caused by store instructions; 5:PMA error caused by load instructions; 6:PMA error caused by store instructions + */ +#define CSR_SDCAUSE_SDCAUSE_MASK (0x7U) +#define CSR_SDCAUSE_SDCAUSE_SHIFT (0U) +#define CSR_SDCAUSE_SDCAUSE_SET(x) (((uint32_t)(x) << CSR_SDCAUSE_SDCAUSE_SHIFT) & CSR_SDCAUSE_SDCAUSE_MASK) +#define CSR_SDCAUSE_SDCAUSE_GET(x) (((uint32_t)(x) & CSR_SDCAUSE_SDCAUSE_MASK) >> CSR_SDCAUSE_SDCAUSE_SHIFT) + +/* Bitfield definition for register: SCCTLDATA */ +/* + * VA (RW) + * + * See CCTL Commands Which Access mcctldata Table + */ +#define CSR_SCCTLDATA_VA_MASK (0x1FU) +#define CSR_SCCTLDATA_VA_SHIFT (0U) +#define CSR_SCCTLDATA_VA_SET(x) (((uint32_t)(x) << CSR_SCCTLDATA_VA_SHIFT) & CSR_SCCTLDATA_VA_MASK) +#define CSR_SCCTLDATA_VA_GET(x) (((uint32_t)(x) & CSR_SCCTLDATA_VA_MASK) >> CSR_SCCTLDATA_VA_SHIFT) + +/* Bitfield definition for register: SCOUNTERINTEN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTERINTEN_HPM6_MASK (0x40U) +#define CSR_SCOUNTERINTEN_HPM6_SHIFT (6U) +#define CSR_SCOUNTERINTEN_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM6_SHIFT) & CSR_SCOUNTERINTEN_HPM6_MASK) +#define CSR_SCOUNTERINTEN_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM6_MASK) >> CSR_SCOUNTERINTEN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTERINTEN_HPM5_MASK (0x20U) +#define CSR_SCOUNTERINTEN_HPM5_SHIFT (5U) +#define CSR_SCOUNTERINTEN_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM5_SHIFT) & CSR_SCOUNTERINTEN_HPM5_MASK) +#define CSR_SCOUNTERINTEN_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM5_MASK) >> CSR_SCOUNTERINTEN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTERINTEN_HPM4_MASK (0x10U) +#define CSR_SCOUNTERINTEN_HPM4_SHIFT (4U) +#define CSR_SCOUNTERINTEN_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM4_SHIFT) & CSR_SCOUNTERINTEN_HPM4_MASK) +#define CSR_SCOUNTERINTEN_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM4_MASK) >> CSR_SCOUNTERINTEN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTERINTEN_HPM3_MASK (0x8U) +#define CSR_SCOUNTERINTEN_HPM3_SHIFT (3U) +#define CSR_SCOUNTERINTEN_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM3_SHIFT) & CSR_SCOUNTERINTEN_HPM3_MASK) +#define CSR_SCOUNTERINTEN_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM3_MASK) >> CSR_SCOUNTERINTEN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTERINTEN_IR_MASK (0x4U) +#define CSR_SCOUNTERINTEN_IR_SHIFT (2U) +#define CSR_SCOUNTERINTEN_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_IR_SHIFT) & CSR_SCOUNTERINTEN_IR_MASK) +#define CSR_SCOUNTERINTEN_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_IR_MASK) >> CSR_SCOUNTERINTEN_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTERINTEN_CY_MASK (0x1U) +#define CSR_SCOUNTERINTEN_CY_SHIFT (0U) +#define CSR_SCOUNTERINTEN_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_CY_SHIFT) & CSR_SCOUNTERINTEN_CY_MASK) +#define CSR_SCOUNTERINTEN_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_CY_MASK) >> CSR_SCOUNTERINTEN_CY_SHIFT) + +/* Bitfield definition for register: SCOUNTERMASK_M */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_M_HPM6_MASK (0x40U) +#define CSR_SCOUNTERMASK_M_HPM6_SHIFT (6U) +#define CSR_SCOUNTERMASK_M_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM6_SHIFT) & CSR_SCOUNTERMASK_M_HPM6_MASK) +#define CSR_SCOUNTERMASK_M_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM6_MASK) >> CSR_SCOUNTERMASK_M_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_M_HPM5_MASK (0x20U) +#define CSR_SCOUNTERMASK_M_HPM5_SHIFT (5U) +#define CSR_SCOUNTERMASK_M_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM5_SHIFT) & CSR_SCOUNTERMASK_M_HPM5_MASK) +#define CSR_SCOUNTERMASK_M_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM5_MASK) >> CSR_SCOUNTERMASK_M_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_M_HPM4_MASK (0x10U) +#define CSR_SCOUNTERMASK_M_HPM4_SHIFT (4U) +#define CSR_SCOUNTERMASK_M_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM4_SHIFT) & CSR_SCOUNTERMASK_M_HPM4_MASK) +#define CSR_SCOUNTERMASK_M_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM4_MASK) >> CSR_SCOUNTERMASK_M_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_M_HPM3_MASK (0x8U) +#define CSR_SCOUNTERMASK_M_HPM3_SHIFT (3U) +#define CSR_SCOUNTERMASK_M_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM3_SHIFT) & CSR_SCOUNTERMASK_M_HPM3_MASK) +#define CSR_SCOUNTERMASK_M_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM3_MASK) >> CSR_SCOUNTERMASK_M_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_M_IR_MASK (0x4U) +#define CSR_SCOUNTERMASK_M_IR_SHIFT (2U) +#define CSR_SCOUNTERMASK_M_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_IR_SHIFT) & CSR_SCOUNTERMASK_M_IR_MASK) +#define CSR_SCOUNTERMASK_M_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_IR_MASK) >> CSR_SCOUNTERMASK_M_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_M_CY_MASK (0x1U) +#define CSR_SCOUNTERMASK_M_CY_SHIFT (0U) +#define CSR_SCOUNTERMASK_M_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_CY_SHIFT) & CSR_SCOUNTERMASK_M_CY_MASK) +#define CSR_SCOUNTERMASK_M_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_CY_MASK) >> CSR_SCOUNTERMASK_M_CY_SHIFT) + +/* Bitfield definition for register: SCOUNTERMASK_S */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_S_HPM6_MASK (0x40U) +#define CSR_SCOUNTERMASK_S_HPM6_SHIFT (6U) +#define CSR_SCOUNTERMASK_S_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM6_SHIFT) & CSR_SCOUNTERMASK_S_HPM6_MASK) +#define CSR_SCOUNTERMASK_S_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM6_MASK) >> CSR_SCOUNTERMASK_S_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_S_HPM5_MASK (0x20U) +#define CSR_SCOUNTERMASK_S_HPM5_SHIFT (5U) +#define CSR_SCOUNTERMASK_S_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM5_SHIFT) & CSR_SCOUNTERMASK_S_HPM5_MASK) +#define CSR_SCOUNTERMASK_S_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM5_MASK) >> CSR_SCOUNTERMASK_S_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_S_HPM4_MASK (0x10U) +#define CSR_SCOUNTERMASK_S_HPM4_SHIFT (4U) +#define CSR_SCOUNTERMASK_S_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM4_SHIFT) & CSR_SCOUNTERMASK_S_HPM4_MASK) +#define CSR_SCOUNTERMASK_S_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM4_MASK) >> CSR_SCOUNTERMASK_S_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_S_HPM3_MASK (0x8U) +#define CSR_SCOUNTERMASK_S_HPM3_SHIFT (3U) +#define CSR_SCOUNTERMASK_S_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM3_SHIFT) & CSR_SCOUNTERMASK_S_HPM3_MASK) +#define CSR_SCOUNTERMASK_S_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM3_MASK) >> CSR_SCOUNTERMASK_S_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_S_IR_MASK (0x4U) +#define CSR_SCOUNTERMASK_S_IR_SHIFT (2U) +#define CSR_SCOUNTERMASK_S_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_IR_SHIFT) & CSR_SCOUNTERMASK_S_IR_MASK) +#define CSR_SCOUNTERMASK_S_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_IR_MASK) >> CSR_SCOUNTERMASK_S_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_S_CY_MASK (0x1U) +#define CSR_SCOUNTERMASK_S_CY_SHIFT (0U) +#define CSR_SCOUNTERMASK_S_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_CY_SHIFT) & CSR_SCOUNTERMASK_S_CY_MASK) +#define CSR_SCOUNTERMASK_S_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_CY_MASK) >> CSR_SCOUNTERMASK_S_CY_SHIFT) + +/* Bitfield definition for register: SCOUNTERMASK_U */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_U_HPM6_MASK (0x40U) +#define CSR_SCOUNTERMASK_U_HPM6_SHIFT (6U) +#define CSR_SCOUNTERMASK_U_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM6_SHIFT) & CSR_SCOUNTERMASK_U_HPM6_MASK) +#define CSR_SCOUNTERMASK_U_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM6_MASK) >> CSR_SCOUNTERMASK_U_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_U_HPM5_MASK (0x20U) +#define CSR_SCOUNTERMASK_U_HPM5_SHIFT (5U) +#define CSR_SCOUNTERMASK_U_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM5_SHIFT) & CSR_SCOUNTERMASK_U_HPM5_MASK) +#define CSR_SCOUNTERMASK_U_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM5_MASK) >> CSR_SCOUNTERMASK_U_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_U_HPM4_MASK (0x10U) +#define CSR_SCOUNTERMASK_U_HPM4_SHIFT (4U) +#define CSR_SCOUNTERMASK_U_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM4_SHIFT) & CSR_SCOUNTERMASK_U_HPM4_MASK) +#define CSR_SCOUNTERMASK_U_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM4_MASK) >> CSR_SCOUNTERMASK_U_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_U_HPM3_MASK (0x8U) +#define CSR_SCOUNTERMASK_U_HPM3_SHIFT (3U) +#define CSR_SCOUNTERMASK_U_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM3_SHIFT) & CSR_SCOUNTERMASK_U_HPM3_MASK) +#define CSR_SCOUNTERMASK_U_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM3_MASK) >> CSR_SCOUNTERMASK_U_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_U_IR_MASK (0x4U) +#define CSR_SCOUNTERMASK_U_IR_SHIFT (2U) +#define CSR_SCOUNTERMASK_U_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_IR_SHIFT) & CSR_SCOUNTERMASK_U_IR_MASK) +#define CSR_SCOUNTERMASK_U_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_IR_MASK) >> CSR_SCOUNTERMASK_U_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_U_CY_MASK (0x1U) +#define CSR_SCOUNTERMASK_U_CY_SHIFT (0U) +#define CSR_SCOUNTERMASK_U_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_CY_SHIFT) & CSR_SCOUNTERMASK_U_CY_MASK) +#define CSR_SCOUNTERMASK_U_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_CY_MASK) >> CSR_SCOUNTERMASK_U_CY_SHIFT) + +/* Bitfield definition for register: SCOUNTEROVF */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTEROVF_HPM6_MASK (0x40U) +#define CSR_SCOUNTEROVF_HPM6_SHIFT (6U) +#define CSR_SCOUNTEROVF_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM6_SHIFT) & CSR_SCOUNTEROVF_HPM6_MASK) +#define CSR_SCOUNTEROVF_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM6_MASK) >> CSR_SCOUNTEROVF_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTEROVF_HPM5_MASK (0x20U) +#define CSR_SCOUNTEROVF_HPM5_SHIFT (5U) +#define CSR_SCOUNTEROVF_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM5_SHIFT) & CSR_SCOUNTEROVF_HPM5_MASK) +#define CSR_SCOUNTEROVF_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM5_MASK) >> CSR_SCOUNTEROVF_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTEROVF_HPM4_MASK (0x10U) +#define CSR_SCOUNTEROVF_HPM4_SHIFT (4U) +#define CSR_SCOUNTEROVF_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM4_SHIFT) & CSR_SCOUNTEROVF_HPM4_MASK) +#define CSR_SCOUNTEROVF_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM4_MASK) >> CSR_SCOUNTEROVF_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTEROVF_HPM3_MASK (0x8U) +#define CSR_SCOUNTEROVF_HPM3_SHIFT (3U) +#define CSR_SCOUNTEROVF_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM3_SHIFT) & CSR_SCOUNTEROVF_HPM3_MASK) +#define CSR_SCOUNTEROVF_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM3_MASK) >> CSR_SCOUNTEROVF_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTEROVF_IR_MASK (0x4U) +#define CSR_SCOUNTEROVF_IR_SHIFT (2U) +#define CSR_SCOUNTEROVF_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_IR_SHIFT) & CSR_SCOUNTEROVF_IR_MASK) +#define CSR_SCOUNTEROVF_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_IR_MASK) >> CSR_SCOUNTEROVF_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTEROVF_CY_MASK (0x1U) +#define CSR_SCOUNTEROVF_CY_SHIFT (0U) +#define CSR_SCOUNTEROVF_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_CY_SHIFT) & CSR_SCOUNTEROVF_CY_MASK) +#define CSR_SCOUNTEROVF_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_CY_MASK) >> CSR_SCOUNTEROVF_CY_SHIFT) + +/* Bitfield definition for register: SCOUNTINHIBIT */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_HPM6_MASK (0x40U) +#define CSR_SCOUNTINHIBIT_HPM6_SHIFT (6U) +#define CSR_SCOUNTINHIBIT_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM6_SHIFT) & CSR_SCOUNTINHIBIT_HPM6_MASK) +#define CSR_SCOUNTINHIBIT_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM6_MASK) >> CSR_SCOUNTINHIBIT_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_HPM5_MASK (0x20U) +#define CSR_SCOUNTINHIBIT_HPM5_SHIFT (5U) +#define CSR_SCOUNTINHIBIT_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM5_SHIFT) & CSR_SCOUNTINHIBIT_HPM5_MASK) +#define CSR_SCOUNTINHIBIT_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM5_MASK) >> CSR_SCOUNTINHIBIT_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_HPM4_MASK (0x10U) +#define CSR_SCOUNTINHIBIT_HPM4_SHIFT (4U) +#define CSR_SCOUNTINHIBIT_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM4_SHIFT) & CSR_SCOUNTINHIBIT_HPM4_MASK) +#define CSR_SCOUNTINHIBIT_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM4_MASK) >> CSR_SCOUNTINHIBIT_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_HPM3_MASK (0x8U) +#define CSR_SCOUNTINHIBIT_HPM3_SHIFT (3U) +#define CSR_SCOUNTINHIBIT_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM3_SHIFT) & CSR_SCOUNTINHIBIT_HPM3_MASK) +#define CSR_SCOUNTINHIBIT_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM3_MASK) >> CSR_SCOUNTINHIBIT_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_IR_MASK (0x4U) +#define CSR_SCOUNTINHIBIT_IR_SHIFT (2U) +#define CSR_SCOUNTINHIBIT_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_IR_SHIFT) & CSR_SCOUNTINHIBIT_IR_MASK) +#define CSR_SCOUNTINHIBIT_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_IR_MASK) >> CSR_SCOUNTINHIBIT_IR_SHIFT) + +/* + * TM (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_TM_MASK (0x2U) +#define CSR_SCOUNTINHIBIT_TM_SHIFT (1U) +#define CSR_SCOUNTINHIBIT_TM_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_TM_SHIFT) & CSR_SCOUNTINHIBIT_TM_MASK) +#define CSR_SCOUNTINHIBIT_TM_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_TM_MASK) >> CSR_SCOUNTINHIBIT_TM_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_CY_MASK (0x1U) +#define CSR_SCOUNTINHIBIT_CY_SHIFT (0U) +#define CSR_SCOUNTINHIBIT_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_CY_SHIFT) & CSR_SCOUNTINHIBIT_CY_MASK) +#define CSR_SCOUNTINHIBIT_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_CY_MASK) >> CSR_SCOUNTINHIBIT_CY_SHIFT) + +/* Bitfield definition for register: SHPMEVENT3 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT3_SEL_MASK (0x1F0U) +#define CSR_SHPMEVENT3_SEL_SHIFT (4U) +#define CSR_SHPMEVENT3_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT3_SEL_SHIFT) & CSR_SHPMEVENT3_SEL_MASK) +#define CSR_SHPMEVENT3_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT3_SEL_MASK) >> CSR_SHPMEVENT3_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT3_TYPE_MASK (0xFU) +#define CSR_SHPMEVENT3_TYPE_SHIFT (0U) +#define CSR_SHPMEVENT3_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT3_TYPE_SHIFT) & CSR_SHPMEVENT3_TYPE_MASK) +#define CSR_SHPMEVENT3_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT3_TYPE_MASK) >> CSR_SHPMEVENT3_TYPE_SHIFT) + +/* Bitfield definition for register: SHPMEVENT4 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT4_SEL_MASK (0x1F0U) +#define CSR_SHPMEVENT4_SEL_SHIFT (4U) +#define CSR_SHPMEVENT4_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT4_SEL_SHIFT) & CSR_SHPMEVENT4_SEL_MASK) +#define CSR_SHPMEVENT4_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT4_SEL_MASK) >> CSR_SHPMEVENT4_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT4_TYPE_MASK (0xFU) +#define CSR_SHPMEVENT4_TYPE_SHIFT (0U) +#define CSR_SHPMEVENT4_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT4_TYPE_SHIFT) & CSR_SHPMEVENT4_TYPE_MASK) +#define CSR_SHPMEVENT4_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT4_TYPE_MASK) >> CSR_SHPMEVENT4_TYPE_SHIFT) + +/* Bitfield definition for register: SHPMEVENT5 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT5_SEL_MASK (0x1F0U) +#define CSR_SHPMEVENT5_SEL_SHIFT (4U) +#define CSR_SHPMEVENT5_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT5_SEL_SHIFT) & CSR_SHPMEVENT5_SEL_MASK) +#define CSR_SHPMEVENT5_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT5_SEL_MASK) >> CSR_SHPMEVENT5_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT5_TYPE_MASK (0xFU) +#define CSR_SHPMEVENT5_TYPE_SHIFT (0U) +#define CSR_SHPMEVENT5_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT5_TYPE_SHIFT) & CSR_SHPMEVENT5_TYPE_MASK) +#define CSR_SHPMEVENT5_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT5_TYPE_MASK) >> CSR_SHPMEVENT5_TYPE_SHIFT) + +/* Bitfield definition for register: SHPMEVENT6 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT6_SEL_MASK (0x1F0U) +#define CSR_SHPMEVENT6_SEL_SHIFT (4U) +#define CSR_SHPMEVENT6_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT6_SEL_SHIFT) & CSR_SHPMEVENT6_SEL_MASK) +#define CSR_SHPMEVENT6_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT6_SEL_MASK) >> CSR_SHPMEVENT6_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT6_TYPE_MASK (0xFU) +#define CSR_SHPMEVENT6_TYPE_SHIFT (0U) +#define CSR_SHPMEVENT6_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT6_TYPE_SHIFT) & CSR_SHPMEVENT6_TYPE_MASK) +#define CSR_SHPMEVENT6_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT6_TYPE_MASK) >> CSR_SHPMEVENT6_TYPE_SHIFT) + +/* Bitfield definition for register: MICM_CFG */ +/* + * SETH (RO) + * + * This bit extends the ISET field. + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_SETH_MASK (0x1000000UL) +#define CSR_MICM_CFG_SETH_SHIFT (24U) +#define CSR_MICM_CFG_SETH_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_SETH_MASK) >> CSR_MICM_CFG_SETH_SHIFT) + +/* + * ILM_ECC (RO) + * + * ILM soft-error protection scheme + * 0:No parity/ECC + * 1:Parity + * 2:ECC + * 3:Reserved + * ILM is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ILM_ECC_MASK (0x600000UL) +#define CSR_MICM_CFG_ILM_ECC_SHIFT (21U) +#define CSR_MICM_CFG_ILM_ECC_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILM_ECC_MASK) >> CSR_MICM_CFG_ILM_ECC_SHIFT) + +/* + * ILMSZ (RO) + * + * ILM Size + * 0:0 Byte + * 1:1 KiB + * 2:2 KiB + * 3:4 KiB + * 4:8 KiB + * 5:16 KiB + * 6:32 KiB + * 7:64 KiB + * 8:128 KiB + * 9:256 KiB + * 10:512 KiB + * 11:1 MiB + * 12:2 MiB + * 13:4 MiB + * 14:8 MiB + * 15:16 MiB + * 16-31:Reserved + * When ILM is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ILMSZ_MASK (0xF8000UL) +#define CSR_MICM_CFG_ILMSZ_SHIFT (15U) +#define CSR_MICM_CFG_ILMSZ_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILMSZ_MASK) >> CSR_MICM_CFG_ILMSZ_SHIFT) + +/* + * ILMB (RW) + * + * Number of ILM base registers present + * 0:No ILM base register present + * 1:One ILM base register present + * 2-7:Reserved + * When ILM is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ILMB_MASK (0x7000U) +#define CSR_MICM_CFG_ILMB_SHIFT (12U) +#define CSR_MICM_CFG_ILMB_SET(x) (((uint32_t)(x) << CSR_MICM_CFG_ILMB_SHIFT) & CSR_MICM_CFG_ILMB_MASK) +#define CSR_MICM_CFG_ILMB_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILMB_MASK) >> CSR_MICM_CFG_ILMB_SHIFT) + +/* + * IC_ECC (RO) + * + * Cache soft-error protection scheme + * 0:No parity/ECC + * 1:Parity + * 2:ECC + * 3:Reserved + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_IC_ECC_MASK (0xC00U) +#define CSR_MICM_CFG_IC_ECC_SHIFT (10U) +#define CSR_MICM_CFG_IC_ECC_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_IC_ECC_MASK) >> CSR_MICM_CFG_IC_ECC_SHIFT) + +/* + * ILCK (RO) + * + * I-Cache locking support + * 0:No locking support + * 1:With locking support + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ILCK_MASK (0x200U) +#define CSR_MICM_CFG_ILCK_SHIFT (9U) +#define CSR_MICM_CFG_ILCK_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILCK_MASK) >> CSR_MICM_CFG_ILCK_SHIFT) + +/* + * ISZ (RO) + * + * Cache block (line) size + * 0:No I-Cache + * 1:8 bytes + * 2:16 bytes + * 3:32 bytes + * 4:64 bytes + * 5:128 bytes + * 6-7:Reserved + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ISZ_MASK (0x1C0U) +#define CSR_MICM_CFG_ISZ_SHIFT (6U) +#define CSR_MICM_CFG_ISZ_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ISZ_MASK) >> CSR_MICM_CFG_ISZ_SHIFT) + +/* + * IWAY (RO) + * + * Associativity of I-Cache + * 0:Direct-mapped + * 1:2-way + * 2:3-way + * 3:4-way + * 4:5-way + * 5:6-way + * 6:7-way + * 7:8-way + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_IWAY_MASK (0x38U) +#define CSR_MICM_CFG_IWAY_SHIFT (3U) +#define CSR_MICM_CFG_IWAY_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_IWAY_MASK) >> CSR_MICM_CFG_IWAY_SHIFT) + +/* + * ISET (RO) + * + * I-Cache sets (# of cache lines per way): + * When micm_cfg.SETH==0: + * 0:64 + * 1:128 + * 2:256 + * 3:512 + * 4:1024 + * 5:2048 + * 6:4096 + * 7:Reserved + * When micm_cfg.SETH==1: + * 0:32 + * 1:16 + * 2:8 + * 3-7:Reserved + */ +#define CSR_MICM_CFG_ISET_MASK (0x7U) +#define CSR_MICM_CFG_ISET_SHIFT (0U) +#define CSR_MICM_CFG_ISET_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ISET_MASK) >> CSR_MICM_CFG_ISET_SHIFT) + +/* Bitfield definition for register: MDCM_CFG */ +/* + * SETH (RO) + * + * This bit extends the DSET field. + * When data cache is not configured, this field should be ignored + */ +#define CSR_MDCM_CFG_SETH_MASK (0x1000000UL) +#define CSR_MDCM_CFG_SETH_SHIFT (24U) +#define CSR_MDCM_CFG_SETH_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_SETH_MASK) >> CSR_MDCM_CFG_SETH_SHIFT) + +/* + * DLM_ECC (RO) + * + * DLM soft-error protection scheme + * 0:No parity/ECC + * 1:Parity + * 2:ECC + * 3:Reserved + * When DLM is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DLM_ECC_MASK (0x600000UL) +#define CSR_MDCM_CFG_DLM_ECC_SHIFT (21U) +#define CSR_MDCM_CFG_DLM_ECC_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLM_ECC_MASK) >> CSR_MDCM_CFG_DLM_ECC_SHIFT) + +/* + * DLMSZ (RO) + * + * DLM Size + * 0:0 Byte + * 1:1 KiB + * 2:2 KiB + * 3:4 KiB + * 4:8 KiB + * 5:16 KiB + * 6:32 KiB + * 7:64 KiB + * 8:128 KiB + * 9:256 KiB + * 10:512 KiB + * 11:1 MiB + * 12:2 MiB + * 13:4 MiB + * 14:8 MiB + * 15:16 MiB + * 16-31:Reserved + * When ILM is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DLMSZ_MASK (0xF8000UL) +#define CSR_MDCM_CFG_DLMSZ_SHIFT (15U) +#define CSR_MDCM_CFG_DLMSZ_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLMSZ_MASK) >> CSR_MDCM_CFG_DLMSZ_SHIFT) + +/* + * DLMB (RO) + * + * Number of DLM base registers present + * 0:No DLM base register present + * 1:One DLM base register present + * 2-7:Reserved + * When DLM is not configured, this field should be ignored + */ +#define CSR_MDCM_CFG_DLMB_MASK (0x7000U) +#define CSR_MDCM_CFG_DLMB_SHIFT (12U) +#define CSR_MDCM_CFG_DLMB_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLMB_MASK) >> CSR_MDCM_CFG_DLMB_SHIFT) + +/* + * DC_ECC (RO) + * + * Cache soft-error protection scheme + * 0:No parity/ECC support + * 1:Has parity support + * 2:Has ECC support + * 3:Reserved + * When data cache is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DC_ECC_MASK (0xC00U) +#define CSR_MDCM_CFG_DC_ECC_SHIFT (10U) +#define CSR_MDCM_CFG_DC_ECC_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DC_ECC_MASK) >> CSR_MDCM_CFG_DC_ECC_SHIFT) + +/* + * DLCK (RO) + * + * D-Cache locking support + * 0:No locking support + * 1:With locking support + * When data cache is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DLCK_MASK (0x200U) +#define CSR_MDCM_CFG_DLCK_SHIFT (9U) +#define CSR_MDCM_CFG_DLCK_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLCK_MASK) >> CSR_MDCM_CFG_DLCK_SHIFT) + +/* + * DSZ (RO) + * + * Cache block (line) size + * 0:No I-Cache + * 1:8 bytes + * 2:16 bytes + * 3:32 bytes + * 4:64 bytes + * 5:128 bytes + * 6-7:Reserved + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DSZ_MASK (0x1C0U) +#define CSR_MDCM_CFG_DSZ_SHIFT (6U) +#define CSR_MDCM_CFG_DSZ_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DSZ_MASK) >> CSR_MDCM_CFG_DSZ_SHIFT) + +/* + * DWAY (RO) + * + * Associativity of D-Cache + * 0:Direct-mapped + * 1:2-way + * 2:3-way + * 3:4-way + * 4:5-way + * 5:6-way + * 6:7-way + * 7:8-way + * When data cache is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DWAY_MASK (0x38U) +#define CSR_MDCM_CFG_DWAY_SHIFT (3U) +#define CSR_MDCM_CFG_DWAY_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DWAY_MASK) >> CSR_MDCM_CFG_DWAY_SHIFT) + +/* + * DSET (RO) + * + * D-Cache sets (# of cache lines per way): + * When mdcm_cfg.SETH==0: + * 0:64 + * 1:128 + * 2:256 + * 3:512 + * 4:1024 + * 5:2048 + * 6:4096 + * 7:Reserved + * When mdcm_cfg.SETH==1: + * 0:32 + * 1:16 + * 2:8 + * 3-7:Reserved + * When data cache is not configured, this field should be ignored + */ +#define CSR_MDCM_CFG_DSET_MASK (0x7U) +#define CSR_MDCM_CFG_DSET_SHIFT (0U) +#define CSR_MDCM_CFG_DSET_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DSET_MASK) >> CSR_MDCM_CFG_DSET_SHIFT) + +/* Bitfield definition for register: MMSC_CFG */ +/* + * MSC_EXT (RO) + * + * Indicates if the mmsc_cfg2 CSR is present or not. + * 0:The mmsc_cfg2 CSR is not present. + * 1:The mmsc_cfg2 CSR is present + */ +#define CSR_MMSC_CFG_MSC_EXT_MASK (0x80000000UL) +#define CSR_MMSC_CFG_MSC_EXT_SHIFT (31U) +#define CSR_MMSC_CFG_MSC_EXT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_MSC_EXT_MASK) >> CSR_MMSC_CFG_MSC_EXT_SHIFT) + +/* + * PPMA (RO) + * + * Indicates if programmable PMA setup with PMA region CSRs is supported or not + * 0:Programmable PMA setup is not supported. + * 1:Programmable PMA setup is supported. + */ +#define CSR_MMSC_CFG_PPMA_MASK (0x40000000UL) +#define CSR_MMSC_CFG_PPMA_SHIFT (30U) +#define CSR_MMSC_CFG_PPMA_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PPMA_MASK) >> CSR_MMSC_CFG_PPMA_SHIFT) + +/* + * EDSP (RO) + * + * Indicates if the DSP extension is supported or not + * 0:The DSP extension is not supported. + * 1:The DSP extension is supported. + */ +#define CSR_MMSC_CFG_EDSP_MASK (0x20000000UL) +#define CSR_MMSC_CFG_EDSP_SHIFT (29U) +#define CSR_MMSC_CFG_EDSP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EDSP_MASK) >> CSR_MMSC_CFG_EDSP_SHIFT) + +/* + * VCCTL (RO) + * + * Indicates the version number of CCTL command operation scheme supported by an implementation + * 0:instruction cache and data cache are not configured. + * 1:instruction cache or data cache is configured. + */ +#define CSR_MMSC_CFG_VCCTL_MASK (0xC0000UL) +#define CSR_MMSC_CFG_VCCTL_SHIFT (18U) +#define CSR_MMSC_CFG_VCCTL_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_VCCTL_MASK) >> CSR_MMSC_CFG_VCCTL_SHIFT) + +/* + * EFHW (RO) + * + * Indicates the support of FLHW and FSHW instructions + * 0:FLHW and FSHW instructions are not supported + * 1:FLHW and FSHW instructions are supported. + */ +#define CSR_MMSC_CFG_EFHW_MASK (0x20000UL) +#define CSR_MMSC_CFG_EFHW_SHIFT (17U) +#define CSR_MMSC_CFG_EFHW_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EFHW_MASK) >> CSR_MMSC_CFG_EFHW_SHIFT) + +/* + * CCTLCSR (RO) + * + * Indicates the presence of CSRs for CCTL operations. + * 0:Feature of CSRs for CCTL operations is not supported. + * 1:Feature of CSRs for CCTL operations is supported. + */ +#define CSR_MMSC_CFG_CCTLCSR_MASK (0x10000UL) +#define CSR_MMSC_CFG_CCTLCSR_SHIFT (16U) +#define CSR_MMSC_CFG_CCTLCSR_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_CCTLCSR_MASK) >> CSR_MMSC_CFG_CCTLCSR_SHIFT) + +/* + * PMNDS (RO) + * + * Indicates if Andes-enhanced performance monitoring feature is present or no. + * 0:Andes-enhanced performance monitoring feature is not supported. + * 1:Andes-enhanced performance monitoring feature is supported. + */ +#define CSR_MMSC_CFG_PMNDS_MASK (0x8000U) +#define CSR_MMSC_CFG_PMNDS_SHIFT (15U) +#define CSR_MMSC_CFG_PMNDS_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PMNDS_MASK) >> CSR_MMSC_CFG_PMNDS_SHIFT) + +/* + * LMSLVP (RO) + * + * Indicates if local memory slave port is present or not. + * 0:Local memory slave port is not present. + * 1:Local memory slave port is implemented. + */ +#define CSR_MMSC_CFG_LMSLVP_MASK (0x4000U) +#define CSR_MMSC_CFG_LMSLVP_SHIFT (14U) +#define CSR_MMSC_CFG_LMSLVP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_LMSLVP_MASK) >> CSR_MMSC_CFG_LMSLVP_SHIFT) + +/* + * EV5PE (RO) + * + * Indicates whether AndeStar V5 Performance Extension is implemented or not. D45 always implements AndeStar V5 Performance Extension. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_EV5PE_MASK (0x2000U) +#define CSR_MMSC_CFG_EV5PE_SHIFT (13U) +#define CSR_MMSC_CFG_EV5PE_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EV5PE_MASK) >> CSR_MMSC_CFG_EV5PE_SHIFT) + +/* + * VPLIC (RO) + * + * Indicates whether the Andes Vectored PLIC Extension is implemented or not. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_VPLIC_MASK (0x1000U) +#define CSR_MMSC_CFG_VPLIC_SHIFT (12U) +#define CSR_MMSC_CFG_VPLIC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_VPLIC_MASK) >> CSR_MMSC_CFG_VPLIC_SHIFT) + +/* + * ACE (RO) + * + * Indicates whether the Andes StackSafe hardware stack protection extension is implemented or not. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_ACE_MASK (0x40U) +#define CSR_MMSC_CFG_ACE_SHIFT (6U) +#define CSR_MMSC_CFG_ACE_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ACE_MASK) >> CSR_MMSC_CFG_ACE_SHIFT) + +/* + * HSP (RO) + * + * Indicates whether the Andes PowerBrake (Performance Throttling) power/performance scaling extension is implemented or not. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_HSP_MASK (0x20U) +#define CSR_MMSC_CFG_HSP_SHIFT (5U) +#define CSR_MMSC_CFG_HSP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_HSP_MASK) >> CSR_MMSC_CFG_HSP_SHIFT) + +/* + * PFT (RO) + * + * Indicates whether the Andes PowerBrake (Performance Throttling) power/performance scaling extension is implemented or not + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_PFT_MASK (0x10U) +#define CSR_MMSC_CFG_PFT_SHIFT (4U) +#define CSR_MMSC_CFG_PFT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PFT_MASK) >> CSR_MMSC_CFG_PFT_SHIFT) + +/* + * ECD (RO) + * + * Indicates whether the Andes CoDense Extension is implemented or not. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_ECD_MASK (0x8U) +#define CSR_MMSC_CFG_ECD_SHIFT (3U) +#define CSR_MMSC_CFG_ECD_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ECD_MASK) >> CSR_MMSC_CFG_ECD_SHIFT) + +/* + * TLB_ECC (RO) + * + * TLB parity/ECC support configuration. + * 0:No parity/ECC + * 1:Parity + * 2:ECC + * 3:Reserved + */ +#define CSR_MMSC_CFG_TLB_ECC_MASK (0x6U) +#define CSR_MMSC_CFG_TLB_ECC_SHIFT (1U) +#define CSR_MMSC_CFG_TLB_ECC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_TLB_ECC_MASK) >> CSR_MMSC_CFG_TLB_ECC_SHIFT) + +/* + * ECC (RO) + * + * Indicates whether the parity/ECC soft-error protection is implemented or not. + * 0:Not implemented. + * 1:Implemented. + * The specific parity/ECC scheme used for each protected RAM is specified by the control bits in the following list. + * micm_cfg.IC_ECC + * micm_cfg.ILM_ECC + * mdcm_cfg.DC_ECC + * mdcm_cfg.DLM_ECC + * mmsc_cfg.TLB_ECC + */ +#define CSR_MMSC_CFG_ECC_MASK (0x1U) +#define CSR_MMSC_CFG_ECC_SHIFT (0U) +#define CSR_MMSC_CFG_ECC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ECC_MASK) >> CSR_MMSC_CFG_ECC_SHIFT) + +/* Bitfield definition for register: MMSC_CFG2 */ +/* + * FINV (RO) + * + * Indicates if scalar FPU is implemented in VPU + * 0:Scalar FPU is not implemented in VPU + * 1:Scalar FPU is implemented in VPU + */ +#define CSR_MMSC_CFG2_FINV_MASK (0x20U) +#define CSR_MMSC_CFG2_FINV_SHIFT (5U) +#define CSR_MMSC_CFG2_FINV_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_FINV_MASK) >> CSR_MMSC_CFG2_FINV_SHIFT) + +/* + * ZFH (RO) + * + * Indicates if the FP16 half-precision floating-point extension (Zfh) is supported or not. + * 0:The FP16 extension is not supported. + * 1:The FP16 extension is supported + */ +#define CSR_MMSC_CFG2_ZFH_MASK (0x2U) +#define CSR_MMSC_CFG2_ZFH_SHIFT (1U) +#define CSR_MMSC_CFG2_ZFH_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_ZFH_MASK) >> CSR_MMSC_CFG2_ZFH_SHIFT) + +/* + * BF16CVT (RO) + * + * Indicates if the BFLOAT16 conversion extension + * is supported or not. + * 0:The BFLOAT16 conversion extension is not supported + * 1:The BFLOAT16 conversion extension is supported + */ +#define CSR_MMSC_CFG2_BF16CVT_MASK (0x1U) +#define CSR_MMSC_CFG2_BF16CVT_SHIFT (0U) +#define CSR_MMSC_CFG2_BF16CVT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_BF16CVT_MASK) >> CSR_MMSC_CFG2_BF16CVT_SHIFT) + + +#endif /* HPM_CSR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_dmamux_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_dmamux_regs.h new file mode 100644 index 00000000000..781a9b7a4f8 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_dmamux_regs.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_DMAMUX_H +#define HPM_DMAMUX_H + +typedef struct { + __RW uint32_t MUXCFG[64]; /* 0x0 - 0xFC: HDMA MUX0 Configuration */ +} DMAMUX_Type; + + +/* Bitfield definition for register array: MUXCFG */ +/* + * ENABLE (RW) + * + * DMA Mux Channel Enable + * Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be + * used to disable or reconfigure a DMA channel. + * 0b - DMA Mux channel is disabled + * 1b - DMA Mux channel is enabled + */ +#define DMAMUX_MUXCFG_ENABLE_MASK (0x80000000UL) +#define DMAMUX_MUXCFG_ENABLE_SHIFT (31U) +#define DMAMUX_MUXCFG_ENABLE_SET(x) (((uint32_t)(x) << DMAMUX_MUXCFG_ENABLE_SHIFT) & DMAMUX_MUXCFG_ENABLE_MASK) +#define DMAMUX_MUXCFG_ENABLE_GET(x) (((uint32_t)(x) & DMAMUX_MUXCFG_ENABLE_MASK) >> DMAMUX_MUXCFG_ENABLE_SHIFT) + +/* + * SOURCE (RW) + * + * DMA Channel Source + * Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + */ +#define DMAMUX_MUXCFG_SOURCE_MASK (0x7FU) +#define DMAMUX_MUXCFG_SOURCE_SHIFT (0U) +#define DMAMUX_MUXCFG_SOURCE_SET(x) (((uint32_t)(x) << DMAMUX_MUXCFG_SOURCE_SHIFT) & DMAMUX_MUXCFG_SOURCE_MASK) +#define DMAMUX_MUXCFG_SOURCE_GET(x) (((uint32_t)(x) & DMAMUX_MUXCFG_SOURCE_MASK) >> DMAMUX_MUXCFG_SOURCE_SHIFT) + + + +/* MUXCFG register group index macro definition */ +#define DMAMUX_MUXCFG_HDMA_MUX0 (0UL) +#define DMAMUX_MUXCFG_HDMA_MUX1 (1UL) +#define DMAMUX_MUXCFG_HDMA_MUX2 (2UL) +#define DMAMUX_MUXCFG_HDMA_MUX3 (3UL) +#define DMAMUX_MUXCFG_HDMA_MUX4 (4UL) +#define DMAMUX_MUXCFG_HDMA_MUX5 (5UL) +#define DMAMUX_MUXCFG_HDMA_MUX6 (6UL) +#define DMAMUX_MUXCFG_HDMA_MUX7 (7UL) +#define DMAMUX_MUXCFG_HDMA_MUX8 (8UL) +#define DMAMUX_MUXCFG_HDMA_MUX9 (9UL) +#define DMAMUX_MUXCFG_HDMA_MUX10 (10UL) +#define DMAMUX_MUXCFG_HDMA_MUX11 (11UL) +#define DMAMUX_MUXCFG_HDMA_MUX12 (12UL) +#define DMAMUX_MUXCFG_HDMA_MUX13 (13UL) +#define DMAMUX_MUXCFG_HDMA_MUX14 (14UL) +#define DMAMUX_MUXCFG_HDMA_MUX15 (15UL) +#define DMAMUX_MUXCFG_HDMA_MUX16 (16UL) +#define DMAMUX_MUXCFG_HDMA_MUX17 (17UL) +#define DMAMUX_MUXCFG_HDMA_MUX18 (18UL) +#define DMAMUX_MUXCFG_HDMA_MUX19 (19UL) +#define DMAMUX_MUXCFG_HDMA_MUX20 (20UL) +#define DMAMUX_MUXCFG_HDMA_MUX21 (21UL) +#define DMAMUX_MUXCFG_HDMA_MUX22 (22UL) +#define DMAMUX_MUXCFG_HDMA_MUX23 (23UL) +#define DMAMUX_MUXCFG_HDMA_MUX24 (24UL) +#define DMAMUX_MUXCFG_HDMA_MUX25 (25UL) +#define DMAMUX_MUXCFG_HDMA_MUX26 (26UL) +#define DMAMUX_MUXCFG_HDMA_MUX27 (27UL) +#define DMAMUX_MUXCFG_HDMA_MUX28 (28UL) +#define DMAMUX_MUXCFG_HDMA_MUX29 (29UL) +#define DMAMUX_MUXCFG_HDMA_MUX30 (30UL) +#define DMAMUX_MUXCFG_HDMA_MUX31 (31UL) +#define DMAMUX_MUXCFG_XDMA_MUX0 (32UL) +#define DMAMUX_MUXCFG_XDMA_MUX1 (33UL) +#define DMAMUX_MUXCFG_XDMA_MUX2 (34UL) +#define DMAMUX_MUXCFG_XDMA_MUX3 (35UL) +#define DMAMUX_MUXCFG_XDMA_MUX4 (36UL) +#define DMAMUX_MUXCFG_XDMA_MUX5 (37UL) +#define DMAMUX_MUXCFG_XDMA_MUX6 (38UL) +#define DMAMUX_MUXCFG_XDMA_MUX7 (39UL) +#define DMAMUX_MUXCFG_XDMA_MUX8 (40UL) +#define DMAMUX_MUXCFG_XDMA_MUX9 (41UL) +#define DMAMUX_MUXCFG_XDMA_MUX10 (42UL) +#define DMAMUX_MUXCFG_XDMA_MUX11 (43UL) +#define DMAMUX_MUXCFG_XDMA_MUX12 (44UL) +#define DMAMUX_MUXCFG_XDMA_MUX13 (45UL) +#define DMAMUX_MUXCFG_XDMA_MUX14 (46UL) +#define DMAMUX_MUXCFG_XDMA_MUX15 (47UL) +#define DMAMUX_MUXCFG_XDMA_MUX16 (48UL) +#define DMAMUX_MUXCFG_XDMA_MUX17 (49UL) +#define DMAMUX_MUXCFG_XDMA_MUX18 (50UL) +#define DMAMUX_MUXCFG_XDMA_MUX19 (51UL) +#define DMAMUX_MUXCFG_XDMA_MUX20 (52UL) +#define DMAMUX_MUXCFG_XDMA_MUX21 (53UL) +#define DMAMUX_MUXCFG_XDMA_MUX22 (54UL) +#define DMAMUX_MUXCFG_XDMA_MUX23 (55UL) +#define DMAMUX_MUXCFG_XDMA_MUX24 (56UL) +#define DMAMUX_MUXCFG_XDMA_MUX25 (57UL) +#define DMAMUX_MUXCFG_XDMA_MUX26 (58UL) +#define DMAMUX_MUXCFG_XDMA_MUX27 (59UL) +#define DMAMUX_MUXCFG_XDMA_MUX28 (60UL) +#define DMAMUX_MUXCFG_XDMA_MUX29 (61UL) +#define DMAMUX_MUXCFG_XDMA_MUX30 (62UL) +#define DMAMUX_MUXCFG_XDMA_MUX31 (63UL) + + +#endif /* HPM_DMAMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_dmamux_src.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_dmamux_src.h new file mode 100644 index 00000000000..c6128331b47 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_dmamux_src.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_DMAMUX_SRC_H +#define HPM_DMAMUX_SRC_H + +/* dma mux definitions */ +#define HPM_DMA_SRC_SPI0_RX (0x0UL) +#define HPM_DMA_SRC_SPI0_TX (0x1UL) +#define HPM_DMA_SRC_SPI1_RX (0x2UL) +#define HPM_DMA_SRC_SPI1_TX (0x3UL) +#define HPM_DMA_SRC_SPI2_RX (0x4UL) +#define HPM_DMA_SRC_SPI2_TX (0x5UL) +#define HPM_DMA_SRC_SPI3_RX (0x6UL) +#define HPM_DMA_SRC_SPI3_TX (0x7UL) +#define HPM_DMA_SRC_UART0_RX (0x8UL) +#define HPM_DMA_SRC_UART0_TX (0x9UL) +#define HPM_DMA_SRC_UART1_RX (0xAUL) +#define HPM_DMA_SRC_UART1_TX (0xBUL) +#define HPM_DMA_SRC_UART2_RX (0xCUL) +#define HPM_DMA_SRC_UART2_TX (0xDUL) +#define HPM_DMA_SRC_UART3_RX (0xEUL) +#define HPM_DMA_SRC_UART3_TX (0xFUL) +#define HPM_DMA_SRC_UART4_RX (0x10UL) +#define HPM_DMA_SRC_UART4_TX (0x11UL) +#define HPM_DMA_SRC_UART5_RX (0x12UL) +#define HPM_DMA_SRC_UART5_TX (0x13UL) +#define HPM_DMA_SRC_UART6_RX (0x14UL) +#define HPM_DMA_SRC_UART6_TX (0x15UL) +#define HPM_DMA_SRC_UART7_RX (0x16UL) +#define HPM_DMA_SRC_UART7_TX (0x17UL) +#define HPM_DMA_SRC_MCAN0 (0x18UL) +#define HPM_DMA_SRC_MCAN1 (0x19UL) +#define HPM_DMA_SRC_MCAN2 (0x1AUL) +#define HPM_DMA_SRC_MCAN3 (0x1BUL) +#define HPM_DMA_SRC_MCAN4 (0x1CUL) +#define HPM_DMA_SRC_MCAN5 (0x1DUL) +#define HPM_DMA_SRC_MCAN6 (0x1EUL) +#define HPM_DMA_SRC_MCAN7 (0x1FUL) +#define HPM_DMA_SRC_I2S0_RX (0x20UL) +#define HPM_DMA_SRC_I2S0_TX (0x21UL) +#define HPM_DMA_SRC_I2S1_RX (0x22UL) +#define HPM_DMA_SRC_I2S1_TX (0x23UL) +#define HPM_DMA_SRC_I2S2_RX (0x24UL) +#define HPM_DMA_SRC_I2S2_TX (0x25UL) +#define HPM_DMA_SRC_I2S3_RX (0x26UL) +#define HPM_DMA_SRC_I2S3_TX (0x27UL) +#define HPM_DMA_SRC_GPTMR0_0 (0x28UL) +#define HPM_DMA_SRC_GPTMR0_1 (0x29UL) +#define HPM_DMA_SRC_GPTMR0_2 (0x2AUL) +#define HPM_DMA_SRC_GPTMR0_3 (0x2BUL) +#define HPM_DMA_SRC_GPTMR1_0 (0x2CUL) +#define HPM_DMA_SRC_GPTMR1_1 (0x2DUL) +#define HPM_DMA_SRC_GPTMR1_2 (0x2EUL) +#define HPM_DMA_SRC_GPTMR1_3 (0x2FUL) +#define HPM_DMA_SRC_GPTMR2_0 (0x30UL) +#define HPM_DMA_SRC_GPTMR2_1 (0x31UL) +#define HPM_DMA_SRC_GPTMR2_2 (0x32UL) +#define HPM_DMA_SRC_GPTMR2_3 (0x33UL) +#define HPM_DMA_SRC_GPTMR3_0 (0x34UL) +#define HPM_DMA_SRC_GPTMR3_1 (0x35UL) +#define HPM_DMA_SRC_GPTMR3_2 (0x36UL) +#define HPM_DMA_SRC_GPTMR3_3 (0x37UL) +#define HPM_DMA_SRC_GPTMR4_0 (0x38UL) +#define HPM_DMA_SRC_GPTMR4_1 (0x39UL) +#define HPM_DMA_SRC_GPTMR4_2 (0x3AUL) +#define HPM_DMA_SRC_GPTMR4_3 (0x3BUL) +#define HPM_DMA_SRC_GPTMR5_0 (0x3CUL) +#define HPM_DMA_SRC_GPTMR5_1 (0x3DUL) +#define HPM_DMA_SRC_GPTMR5_2 (0x3EUL) +#define HPM_DMA_SRC_GPTMR5_3 (0x3FUL) +#define HPM_DMA_SRC_GPTMR6_0 (0x40UL) +#define HPM_DMA_SRC_GPTMR6_1 (0x41UL) +#define HPM_DMA_SRC_GPTMR6_2 (0x42UL) +#define HPM_DMA_SRC_GPTMR6_3 (0x43UL) +#define HPM_DMA_SRC_GPTMR7_0 (0x44UL) +#define HPM_DMA_SRC_GPTMR7_1 (0x45UL) +#define HPM_DMA_SRC_GPTMR7_2 (0x46UL) +#define HPM_DMA_SRC_GPTMR7_3 (0x47UL) +#define HPM_DMA_SRC_I2C0 (0x48UL) +#define HPM_DMA_SRC_I2C1 (0x49UL) +#define HPM_DMA_SRC_I2C2 (0x4AUL) +#define HPM_DMA_SRC_I2C3 (0x4BUL) +#define HPM_DMA_SRC_XPI0_RX (0x4CUL) +#define HPM_DMA_SRC_XPI0_TX (0x4DUL) + + + +#endif /* HPM_DMAMUX_SRC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_enet_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_enet_soc_drv.h new file mode 100644 index 00000000000..fadee53a327 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_enet_soc_drv.h @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_ENET_SOC_DRV_H +#define HPM_ENET_SOC_DRV_H + +#include "hpm_soc.h" + +#if defined __cplusplus +extern "C" { +#endif + +static inline hpm_stat_t enet_intf_selection(ENET_Type *ptr, uint8_t inf_type) +{ + hpm_stat_t stat = status_success; + + if (ptr == HPM_ENET0) { + ptr->CTRL2 &= ~ENET_CTRL2_ENET0_PHY_INF_SEL_MASK; + ptr->CTRL2 |= ENET_CTRL2_ENET0_PHY_INF_SEL_SET(inf_type); + } else { + return status_invalid_argument; + } + + return stat; +} + +static inline hpm_stat_t enet_enable_lpi_interrupt(ENET_Type *ptr) +{ + hpm_stat_t stat = status_success; + + if (ptr == HPM_ENET0) { + ptr->CTRL2 |= ENET_CTRL2_ENET0_LPI_IRQ_EN_MASK; + } else { + return status_invalid_argument; + } + + return stat; +} + +static inline hpm_stat_t enet_disable_lpi_interrupt(ENET_Type *ptr) +{ + hpm_stat_t stat = status_success; + + if (ptr == HPM_ENET0) { + ptr->CTRL2 &= ~ENET_CTRL2_ENET0_LPI_IRQ_EN_MASK; + } else { + return status_invalid_argument; + } + + return stat; +} + +static inline hpm_stat_t enet_rgmii_set_clock_delay(ENET_Type *ptr, uint8_t tx_delay, uint8_t rx_delay) +{ + hpm_stat_t stat = status_success; + + if (ptr == HPM_ENET0) { + ptr->CTRL0 &= ~(ENET_CTRL0_ENET0_TXCLK_DLY_SEL_MASK | ENET_CTRL0_ENET0_RXCLK_DLY_SEL_MASK); + ptr->CTRL0 |= ENET_CTRL0_ENET0_TXCLK_DLY_SEL_SET(tx_delay) | ENET_CTRL0_ENET0_RXCLK_DLY_SEL_SET(rx_delay); + } else { + return status_invalid_argument; + } + + return stat; +} + +static inline hpm_stat_t enet_rmii_enable_clock(ENET_Type *ptr, bool internal) +{ + hpm_stat_t stat = status_success; + + /* use an internal PLL clock as reference clock for rmii mode */ + if (ptr == HPM_ENET0) { + if (internal == true) { + /* use a pll clock */ + ptr->CTRL2 |= ENET_CTRL2_ENET0_REFCLK_OE_MASK | ENET_CTRL2_ENET0_RMII_TXCLK_SEL_MASK; + } else { + /* use an external clock as reference clock for rmii mode */ + ptr->CTRL2 |= ENET_CTRL2_ENET0_RMII_TXCLK_SEL_MASK; /* use an external clock */ + } + } else { + return status_invalid_argument; + } + + return stat; +} + +static inline hpm_stat_t enet_rgmii_enable_clock(ENET_Type *ptr) +{ + hpm_stat_t stat = status_success; + + if (ptr == HPM_ENET0) { + /* use an internal PLL clock for rgmii mode */ + ptr->CTRL2 &= ~ENET_CTRL2_ENET0_RMII_TXCLK_SEL_MASK; + } else { + return status_invalid_argument; + } + + return stat; +} + +#if defined __cplusplus +} /* __cplusplus */ +#endif + +#endif /* HPM_ENET_SOC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_gpiom_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_gpiom_regs.h new file mode 100644 index 00000000000..c138b4451f8 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_gpiom_regs.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_GPIOM_H +#define HPM_GPIOM_H + +typedef struct { + struct { + __RW uint32_t PIN[32]; /* 0x0 - 0x7C: GPIO mananger */ + } ASSIGN[16]; +} GPIOM_Type; + + +/* Bitfield definition for register of struct array ASSIGN: PIN00 */ +/* + * LOCK (RW) + * + * lock fields in this register, lock can only be cleared by soc reset + * 0: fields can be changed + * 1: fields locked to current value, not changeable + */ +#define GPIOM_ASSIGN_PIN_LOCK_MASK (0x80000000UL) +#define GPIOM_ASSIGN_PIN_LOCK_SHIFT (31U) +#define GPIOM_ASSIGN_PIN_LOCK_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_LOCK_SHIFT) & GPIOM_ASSIGN_PIN_LOCK_MASK) +#define GPIOM_ASSIGN_PIN_LOCK_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_LOCK_MASK) >> GPIOM_ASSIGN_PIN_LOCK_SHIFT) + +/* + * HIDE (RW) + * + * pin value visibility to gpios, + * bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 + * bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + */ +#define GPIOM_ASSIGN_PIN_HIDE_MASK (0x300U) +#define GPIOM_ASSIGN_PIN_HIDE_SHIFT (8U) +#define GPIOM_ASSIGN_PIN_HIDE_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_HIDE_SHIFT) & GPIOM_ASSIGN_PIN_HIDE_MASK) +#define GPIOM_ASSIGN_PIN_HIDE_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_HIDE_MASK) >> GPIOM_ASSIGN_PIN_HIDE_SHIFT) + +/* + * SELECT (RW) + * + * select which gpio controls chip pin, + * 0: soc gpio0; + * 2: cpu0 fastgpio + */ +#define GPIOM_ASSIGN_PIN_SELECT_MASK (0x3U) +#define GPIOM_ASSIGN_PIN_SELECT_SHIFT (0U) +#define GPIOM_ASSIGN_PIN_SELECT_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_SELECT_SHIFT) & GPIOM_ASSIGN_PIN_SELECT_MASK) +#define GPIOM_ASSIGN_PIN_SELECT_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_SELECT_MASK) >> GPIOM_ASSIGN_PIN_SELECT_SHIFT) + + + +/* PIN register group index macro definition */ +#define GPIOM_ASSIGN_PIN_PIN00 (0UL) +#define GPIOM_ASSIGN_PIN_PIN01 (1UL) +#define GPIOM_ASSIGN_PIN_PIN02 (2UL) +#define GPIOM_ASSIGN_PIN_PIN03 (3UL) +#define GPIOM_ASSIGN_PIN_PIN04 (4UL) +#define GPIOM_ASSIGN_PIN_PIN05 (5UL) +#define GPIOM_ASSIGN_PIN_PIN06 (6UL) +#define GPIOM_ASSIGN_PIN_PIN07 (7UL) +#define GPIOM_ASSIGN_PIN_PIN08 (8UL) +#define GPIOM_ASSIGN_PIN_PIN09 (9UL) +#define GPIOM_ASSIGN_PIN_PIN10 (10UL) +#define GPIOM_ASSIGN_PIN_PIN11 (11UL) +#define GPIOM_ASSIGN_PIN_PIN12 (12UL) +#define GPIOM_ASSIGN_PIN_PIN13 (13UL) +#define GPIOM_ASSIGN_PIN_PIN14 (14UL) +#define GPIOM_ASSIGN_PIN_PIN15 (15UL) +#define GPIOM_ASSIGN_PIN_PIN16 (16UL) +#define GPIOM_ASSIGN_PIN_PIN17 (17UL) +#define GPIOM_ASSIGN_PIN_PIN18 (18UL) +#define GPIOM_ASSIGN_PIN_PIN19 (19UL) +#define GPIOM_ASSIGN_PIN_PIN20 (20UL) +#define GPIOM_ASSIGN_PIN_PIN21 (21UL) +#define GPIOM_ASSIGN_PIN_PIN22 (22UL) +#define GPIOM_ASSIGN_PIN_PIN23 (23UL) +#define GPIOM_ASSIGN_PIN_PIN24 (24UL) +#define GPIOM_ASSIGN_PIN_PIN25 (25UL) +#define GPIOM_ASSIGN_PIN_PIN26 (26UL) +#define GPIOM_ASSIGN_PIN_PIN27 (27UL) +#define GPIOM_ASSIGN_PIN_PIN28 (28UL) +#define GPIOM_ASSIGN_PIN_PIN29 (29UL) +#define GPIOM_ASSIGN_PIN_PIN30 (30UL) +#define GPIOM_ASSIGN_PIN_PIN31 (31UL) + +/* ASSIGN register group index macro definition */ +#define GPIOM_ASSIGN_GPIOA (0UL) +#define GPIOM_ASSIGN_GPIOB (1UL) +#define GPIOM_ASSIGN_GPIOC (2UL) +#define GPIOM_ASSIGN_GPIOD (3UL) +#define GPIOM_ASSIGN_GPIOE (4UL) +#define GPIOM_ASSIGN_GPIOF (5UL) +#define GPIOM_ASSIGN_GPIOX (13UL) +#define GPIOM_ASSIGN_GPIOY (14UL) +#define GPIOM_ASSIGN_GPIOZ (15UL) + + +#endif /* HPM_GPIOM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_gpiom_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_gpiom_soc_drv.h new file mode 100644 index 00000000000..fcfcfce2aa4 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_gpiom_soc_drv.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_GPIOM_SOC_DRV_H +#define HPM_GPIOM_SOC_DRV_H + +/** + * @addtogroup gpiom_interface GPIOM driver APIs + * @{ + */ + +/* @brief gpiom control module */ +typedef enum gpiom_gpio { + gpiom_soc_gpio0 = 0, + gpiom_core0_fast = 2, +} gpiom_gpio_t; + +/** + * @} + */ + +#endif /* HPM_GPIOM_SOC_DRV_H */ + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_interrupt.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_interrupt.h new file mode 100644 index 00000000000..810971e255f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_interrupt.h @@ -0,0 +1,1181 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_INTERRUPT_H +#define HPM_INTERRUPT_H +#include "hpm_common.h" +#include "hpm_csr_drv.h" +#include "hpm_plic_drv.h" + +/** + * @brief INTERRUPT driver APIs + * @defgroup irq_interface INTERRUPT driver APIs + * @{ + */ + +#define M_MODE 0 /*!< Machine mode */ +#define S_MODE 1 /*!< Supervisor mode */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Machine mode API: these APIs are supposed to be called at machine mode */ + +/** + * @brief Enable global IRQ with mask + * + * @param[in] mask interrupt mask to be enabaled + */ +ATTR_ALWAYS_INLINE static inline void enable_global_irq(uint32_t mask) +{ + set_csr(CSR_MSTATUS, mask); +} + +/** + * @brief Disable global IRQ with mask and return mstatus + * + * @param[in] mask interrupt mask to be disabled + * @retval current mstatus value before irq mask is disabled + */ +ATTR_ALWAYS_INLINE static inline uint32_t disable_global_irq(uint32_t mask) +{ + return read_clear_csr(CSR_MSTATUS, mask); +} + +/** + * @brief Restore global IRQ with mask + * + * @param[in] mask interrupt mask to be restored + */ +ATTR_ALWAYS_INLINE static inline void restore_global_irq(uint32_t mask) +{ + set_csr(CSR_MSTATUS, mask); +} + +/** + * @brief Enable IRQ from interrupt controller + * + */ +ATTR_ALWAYS_INLINE static inline void enable_irq_from_intc(void) +{ + set_csr(CSR_MIE, CSR_MIE_MEIE_MASK); +} + +/** + * @brief Disable IRQ from interrupt controller + * + */ +ATTR_ALWAYS_INLINE static inline void disable_irq_from_intc(void) +{ + clear_csr(CSR_MIE, CSR_MIE_MEIE_MASK); +} + +/** + * @brief Enable machine timer IRQ + */ +ATTR_ALWAYS_INLINE static inline void enable_mchtmr_irq(void) +{ + set_csr(CSR_MIE, CSR_MIE_MTIE_MASK); +} + +/** + * @brief Disable machine timer IRQ + * + */ +ATTR_ALWAYS_INLINE static inline void disable_mchtmr_irq(void) +{ + clear_csr(CSR_MIE, CSR_MIE_MTIE_MASK); +} + +/** + * @brief Delegate IRQ handling + * + * @param[in] mask interrupt mask to be delegated + */ +ATTR_ALWAYS_INLINE static inline void delegate_irq(uint32_t mask) +{ + set_csr(CSR_MIDELEG, mask); +} + +/** + * @brief Undelegate IRQ handling + * + * @param[in] mask interrupt mask to be undelegated + */ +ATTR_ALWAYS_INLINE static inline void undelegate_irq(uint32_t mask) +{ + clear_csr(CSR_MIDELEG, mask); +} + + +/* Supervisor mode API: these APIs are supposed to be called at supervisor mode */ + +/** + * @brief Enable global IRQ with mask for supervisor mode + * + * @param[in] mask interrupt mask to be enabaled + */ +ATTR_ALWAYS_INLINE static inline void enable_s_global_irq(uint32_t mask) +{ + set_csr(CSR_SSTATUS, mask); +} + +/** + * @brief Disable global IRQ with mask and return sstatus for supervisor mode + * + * @param[in] mask interrupt mask to be disabled + * @retval current sstatus value before irq mask is disabled + */ +ATTR_ALWAYS_INLINE static inline uint32_t disable_s_global_irq(uint32_t mask) +{ + return read_clear_csr(CSR_SSTATUS, mask); +} + +/** + * @brief Restore global IRQ with mask for supervisor mode + * + * @param[in] mask interrupt mask to be restored + */ +ATTR_ALWAYS_INLINE static inline void restore_s_global_irq(uint32_t mask) +{ + set_csr(CSR_SSTATUS, mask); +} + +/** + * @brief Disable IRQ from interrupt controller for supervisor mode + * + */ +ATTR_ALWAYS_INLINE static inline void disable_s_irq_from_intc(void) +{ + clear_csr(CSR_SIE, CSR_SIE_SEIE_MASK); +} + +/** + * @brief Enable IRQ from interrupt controller for supervisor mode + * + */ +ATTR_ALWAYS_INLINE static inline void enable_s_irq_from_intc(void) +{ + set_csr(CSR_SIE, CSR_SIE_SEIE_MASK); +} + +/** + * @brief Enable machine timer IRQ for supervisor mode + */ +ATTR_ALWAYS_INLINE static inline void enable_s_mchtmr_irq(void) +{ + set_csr(CSR_SIE, CSR_SIE_STIE_MASK); +} + +/** + * @brief Disable machine timer IRQ + * + */ +ATTR_ALWAYS_INLINE static inline void disable_s_mchtmr_irq(void) +{ + clear_csr(CSR_SIE, CSR_SIE_STIE_MASK); +} + + +/* + * CPU Machine SWI control + * + * Machine SWI (MSIP) is connected to PLICSW irq 1. + */ +#define PLICSWI 1 + +/** + * @brief Initialize software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_init_swi(void) +{ + __plic_enable_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI); +} + + +/** + * @brief Enable software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_enable_swi(void) +{ + set_csr(CSR_MIE, CSR_MIE_MSIE_MASK); +} + + +/** + * @brief Disable software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_disable_swi(void) +{ + clear_csr(CSR_MIE, CSR_MIE_MSIE_MASK); +} + + +/** + * @brief Trigger software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_trigger_swi(void) +{ + __plic_set_irq_pending(HPM_PLICSW_BASE, PLICSWI); +} + +/** + * @brief Claim software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_claim_swi(void) +{ + __plic_claim_irq(HPM_PLICSW_BASE, 0); +} + +/** + * @brief Complete software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_complete_swi(void) +{ + __plic_complete_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI); +} + +/* + * @brief Enable IRQ for machine mode + * + * @param[in] irq Interrupt number + */ +#define intc_m_enable_irq(irq) \ + intc_enable_irq(HPM_PLIC_TARGET_M_MODE, irq) + +/* + * @brief Disable IRQ for machine mode + * + * @param[in] irq Interrupt number + */ +#define intc_m_disable_irq(irq) \ + intc_disable_irq(HPM_PLIC_TARGET_M_MODE, irq) + +#define intc_m_set_threshold(threshold) \ + intc_set_threshold(HPM_PLIC_TARGET_M_MODE, threshold) + +/* + * @brief Complete IRQ for machine mode + * + * @param[in] irq Interrupt number + */ +#define intc_m_complete_irq(irq) \ + intc_complete_irq(HPM_PLIC_TARGET_M_MODE, irq) + +/* + * @brief Claim IRQ for machine mode + * + */ +#define intc_m_claim_irq() intc_claim_irq(HPM_PLIC_TARGET_M_MODE) + +/* + * @brief Enable IRQ for machine mode with priority + * + * @param[in] irq Interrupt number + * @param[in] priority Priority of interrupt + */ +#define intc_m_enable_irq_with_priority(irq, priority) \ + do { \ + intc_set_irq_priority(irq, priority); \ + intc_m_enable_irq(irq); \ + } while (0) + + + +/* Supervisor mode */ + +/** + * @brief Enable software interrupt for supervisor mode + * + */ +ATTR_ALWAYS_INLINE static inline void intc_s_enable_swi(void) +{ + set_csr(CSR_SIE, CSR_SIE_SSIE_MASK); +} + + +/** + * @brief Disable software interrupt for supervisor mode + * + */ +ATTR_ALWAYS_INLINE static inline void intc_s_disable_swi(void) +{ + clear_csr(CSR_SIE, CSR_SIE_SSIE_MASK); +} + + +/** + * @brief Trigger software interrupt for supervisor mode + * + */ +ATTR_ALWAYS_INLINE static inline void intc_s_trigger_swi(void) +{ + set_csr(CSR_SIP, CSR_SIP_SSIP_MASK); +} + + +/** + * @brief Complete software interrupt for supervisor mode + * + */ +ATTR_ALWAYS_INLINE static inline void intc_s_complete_swi(void) +{ + clear_csr(CSR_SIP, CSR_SIP_SSIP_MASK); +} + +/* + * @brief Enable IRQ for supervisor mode + * + * @param[in] irq Interrupt number + */ +#define intc_s_enable_irq(irq) \ + intc_enable_irq(HPM_PLIC_TARGET_S_MODE, irq) + +/* + * @brief Disable IRQ for supervisor mode + * + * @param[in] irq Interrupt number + */ +#define intc_s_disable_irq(irq) \ + intc_disable_irq(HPM_PLIC_TARGET_S_MODE, irq) + +#define intc_set_s_threshold(threshold) \ + intc_set_threshold(HPM_PLIC_TARGET_S_MODE, threshold) + +/* + * @brief Complete IRQ for supervisor mode + * + * @param[in] irq Interrupt number + */ +#define intc_s_complete_irq(irq) \ + intc_complete_irq(HPM_PLIC_TARGET_S_MODE, irq) + +/* + * @brief Claim IRQ for supervisor mode + * + */ +#define intc_s_claim_irq() intc_claim_irq(HPM_PLIC_TARGET_S_MODE) + +/* + * @brief Enable IRQ for supervisor mode with priority + * + * @param[in] irq Interrupt number + * @param[in] priority Priority of interrupt + */ +#define intc_s_enable_irq_with_priority(irq, priority) \ + do { \ + intc_set_irq_priority(irq, priority); \ + intc_s_enable_irq(irq); \ + } while (0) + + +/* + * @brief Enable specific interrupt + * + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number + */ +ATTR_ALWAYS_INLINE static inline void intc_enable_irq(uint32_t target, uint32_t irq) +{ + __plic_enable_irq(HPM_PLIC_BASE, target, irq); +} + +/** + * @brief Set interrupt priority + * + * @param[in] irq Interrupt number + * @param[in] priority Priority of interrupt + */ +ATTR_ALWAYS_INLINE static inline void intc_set_irq_priority(uint32_t irq, uint32_t priority) +{ + __plic_set_irq_priority(HPM_PLIC_BASE, irq, priority); +} + +/** + * @brief Disable specific interrupt + * + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number + */ +ATTR_ALWAYS_INLINE static inline void intc_disable_irq(uint32_t target, uint32_t irq) +{ + __plic_disable_irq(HPM_PLIC_BASE, target, irq); +} + +/** + * @brief Set interrupt threshold + * + * @param[in] target Target to handle specific interrupt + * @param[in] threshold Threshold of IRQ can be serviced + */ +ATTR_ALWAYS_INLINE static inline void intc_set_threshold(uint32_t target, uint32_t threshold) +{ + __plic_set_threshold(HPM_PLIC_BASE, target, threshold); +} + +/** + * @brief Claim IRQ + * + * @param[in] target Target to handle specific interrupt + * + */ +ATTR_ALWAYS_INLINE static inline uint32_t intc_claim_irq(uint32_t target) +{ + return __plic_claim_irq(HPM_PLIC_BASE, target); +} + +/** + * @brief Complete IRQ + * + * @param[in] target Target to handle specific interrupt + * @param[in] irq Specific IRQ to be completed + * + */ +ATTR_ALWAYS_INLINE static inline void intc_complete_irq(uint32_t target, uint32_t irq) +{ + __plic_complete_irq(HPM_PLIC_BASE, target, irq); +} + +/* + * Vectored based irq install and uninstall + */ +/* Machine mode */ +extern int __vector_table[]; +extern void default_irq_entry(void); + +/** + * @brief Install ISR for certain IRQ for ram based vector table + * + * @param[in] irq Target interrupt number + * @param[in] isr Interrupt service routine + * + */ +ATTR_ALWAYS_INLINE static inline void install_isr(uint32_t irq, uint32_t isr) +{ + __vector_table[irq] = isr; +} + +/** + * @brief Uninstall ISR for certain IRQ for ram based vector table + * + * @param[in] irq Target interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) +{ + __vector_table[irq] = (int) default_irq_entry; +} + +/* Supervisor mode */ +extern int __vector_s_table[]; +extern void default_s_irq_entry(void); +/** + * @brief Install ISR for certain IRQ for ram based vector table for supervisor mode + * + * @param[in] irq Target interrupt number + * @param[in] isr Interrupt service routine + * + */ +ATTR_ALWAYS_INLINE static inline void install_s_isr(uint32_t irq, uint32_t isr) +{ + __vector_s_table[irq] = isr; +} + +/** + * @brief Uninstall ISR for certain IRQ for ram based vector table for supervisor mode + * + * @param[in] irq Target interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) +{ + __vector_s_table[irq] = (int) default_s_irq_entry; +} + + +/* + * Inline nested irq entry/exit macros + */ +/* + * @brief Save CSR + * @param[in] r Target CSR to be saved + */ +#define SAVE_CSR(r) register long __##r = read_csr(r); + +/* + * @brief Restore macro + * + * @param[in] r Target CSR to be restored + */ +#define RESTORE_CSR(r) write_csr(r, __##r); + +#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH +#define SAVE_MXSTATUS() SAVE_CSR(CSR_MXSTATUS) +#define RESTORE_MXSTATUS() RESTORE_CSR(CSR_MXSTATUS) +#else +#define SAVE_MXSTATUS() +#define RESTORE_MXSTATUS() +#endif + +#ifdef __riscv_flen +#define SAVE_FCSR() register int __fcsr = read_fcsr(); +#define RESTORE_FCSR() write_fcsr(__fcsr); +#else +#define SAVE_FCSR() +#define RESTORE_FCSR() +#endif + +#ifdef __riscv_dsp +#define SAVE_UCODE() SAVE_CSR(CSR_UCODE) +#define RESTORE_UCODE() RESTORE_CSR(CSR_UCODE) +#else +#define SAVE_UCODE() +#define RESTORE_UCODE() +#endif + +#ifdef __riscv_flen +#if __riscv_flen == 32 +/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + 20 FPU caller registers +FCSR + UCODE (DSP) */ +#define CONTEXT_REG_NUM (4 * (16 + 4 + 20)) +#else /* __riscv_flen = 64 */ +/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + 20 DFPU caller + FCSR registers + UCODE (DSP) */ +#define CONTEXT_REG_NUM (4 * (16 + 4 + 20 * 2)) +#endif + +#else +/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + UCODE (DSP)*/ +#define CONTEXT_REG_NUM (4 * (16 + 4)) +#endif + +#ifdef __riscv_flen +/* + * Save FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack + */ +#if __riscv_flen == 32 +#ifdef __ICCRISCV__ +#define SAVE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fswsp ft0, 20*4\n\ + c.fswsp ft1, 21*4 \n\ + c.fswsp ft2, 22*4 \n\ + c.fswsp ft3, 23*4 \n\ + c.fswsp ft4, 24*4 \n\ + c.fswsp ft5, 25*4 \n\ + c.fswsp ft6, 26*4 \n\ + c.fswsp ft7, 27*4 \n\ + c.fswsp fa0, 28*4 \n\ + c.fswsp fa1, 29*4 \n\ + c.fswsp fa2, 30*4 \n\ + c.fswsp fa3, 31*4 \n\ + c.fswsp fa4, 32*4 \n\ + c.fswsp fa5, 33*4 \n\ + c.fswsp fa6, 34*4 \n\ + c.fswsp fa7, 35*4 \n\ + c.fswsp ft8, 36*4 \n\ + c.fswsp ft9, 37*4 \n\ + c.fswsp ft10, 38*4 \n\ + c.fswsp ft11, 39*4 \n");\ +} + +/* + * Restore FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack + */ +#define RESTORE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.flwsp ft0, 20*4\n\ + c.flwsp ft1, 21*4 \n\ + c.flwsp ft2, 22*4 \n\ + c.flwsp ft3, 23*4 \n\ + c.flwsp ft4, 24*4 \n\ + c.flwsp ft5, 25*4 \n\ + c.flwsp ft6, 26*4 \n\ + c.flwsp ft7, 27*4 \n\ + c.flwsp fa0, 28*4 \n\ + c.flwsp fa1, 29*4 \n\ + c.flwsp fa2, 30*4 \n\ + c.flwsp fa3, 31*4 \n\ + c.flwsp fa4, 32*4 \n\ + c.flwsp fa5, 33*4 \n\ + c.flwsp fa6, 34*4 \n\ + c.flwsp fa7, 35*4 \n\ + c.flwsp ft8, 36*4 \n\ + c.flwsp ft9, 37*4 \n\ + c.flwsp ft10, 38*4 \n\ + c.flwsp ft11, 39*4 \n");\ +} +#else /* __ICCRISCV__ not defined */ +#define SAVE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fswsp ft0, 20*4(sp)\n\ + c.fswsp ft1, 21*4(sp) \n\ + c.fswsp ft2, 22*4(sp) \n\ + c.fswsp ft3, 23*4(sp) \n\ + c.fswsp ft4, 24*4(sp) \n\ + c.fswsp ft5, 25*4(sp) \n\ + c.fswsp ft6, 26*4(sp) \n\ + c.fswsp ft7, 27*4(sp) \n\ + c.fswsp fa0, 28*4(sp) \n\ + c.fswsp fa1, 29*4(sp) \n\ + c.fswsp fa2, 30*4(sp) \n\ + c.fswsp fa3, 31*4(sp) \n\ + c.fswsp fa4, 32*4(sp) \n\ + c.fswsp fa5, 33*4(sp) \n\ + c.fswsp fa6, 34*4(sp) \n\ + c.fswsp fa7, 35*4(sp) \n\ + c.fswsp ft8, 36*4(sp) \n\ + c.fswsp ft9, 37*4(sp) \n\ + c.fswsp ft10, 38*4(sp) \n\ + c.fswsp ft11, 39*4(sp) \n");\ +} + +/* + * Restore FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack + */ +#define RESTORE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.flwsp ft0, 20*4(sp)\n\ + c.flwsp ft1, 21*4(sp) \n\ + c.flwsp ft2, 22*4(sp) \n\ + c.flwsp ft3, 23*4(sp) \n\ + c.flwsp ft4, 24*4(sp) \n\ + c.flwsp ft5, 25*4(sp) \n\ + c.flwsp ft6, 26*4(sp) \n\ + c.flwsp ft7, 27*4(sp) \n\ + c.flwsp fa0, 28*4(sp) \n\ + c.flwsp fa1, 29*4(sp) \n\ + c.flwsp fa2, 30*4(sp) \n\ + c.flwsp fa3, 31*4(sp) \n\ + c.flwsp fa4, 32*4(sp) \n\ + c.flwsp fa5, 33*4(sp) \n\ + c.flwsp fa6, 34*4(sp) \n\ + c.flwsp fa7, 35*4(sp) \n\ + c.flwsp ft8, 36*4(sp) \n\ + c.flwsp ft9, 37*4(sp) \n\ + c.flwsp ft10, 38*4(sp) \n\ + c.flwsp ft11, 39*4(sp) \n");\ +} +#endif +#else /*__riscv_flen == 64*/ +#ifdef __ICCRISCV__ +#define SAVE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fsdsp ft0, 20*4\n\ + c.fsdsp ft1, 22*4 \n\ + c.fsdsp ft2, 24*4 \n\ + c.fsdsp ft3, 26*4 \n\ + c.fsdsp ft4, 28*4 \n\ + c.fsdsp ft5, 30*4 \n\ + c.fsdsp ft6, 32*4 \n\ + c.fsdsp ft7, 34*4 \n\ + c.fsdsp fa0, 36*4 \n\ + c.fsdsp fa1, 38*4 \n\ + c.fsdsp fa2, 40*4 \n\ + c.fsdsp fa3, 42*4 \n\ + c.fsdsp fa4, 44*4 \n\ + c.fsdsp fa5, 46*4 \n\ + c.fsdsp fa6, 48*4 \n\ + c.fsdsp fa7, 50*4 \n\ + c.fsdsp ft8, 52*4 \n\ + c.fsdsp ft9, 54*4 \n\ + c.fsdsp ft10, 56*4 \n\ + c.fsdsp ft11, 58*4 \n");\ +} + +/* + * Restore FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack + */ +#define RESTORE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fldsp ft0, 20*4\n\ + c.fldsp ft1, 22*4 \n\ + c.fldsp ft2, 24*4 \n\ + c.fldsp ft3, 26*4 \n\ + c.fldsp ft4, 28*4 \n\ + c.fldsp ft5, 30*4 \n\ + c.fldsp ft6, 32*4 \n\ + c.fldsp ft7, 34*4 \n\ + c.fldsp fa0, 36*4 \n\ + c.fldsp fa1, 38*4 \n\ + c.fldsp fa2, 40*4 \n\ + c.fldsp fa3, 42*4 \n\ + c.fldsp fa4, 44*4 \n\ + c.fldsp fa5, 46*4 \n\ + c.fldsp fa6, 48*4 \n\ + c.fldsp fa7, 50*4 \n\ + c.fldsp ft8, 52*4 \n\ + c.fldsp ft9, 54*4 \n\ + c.fldsp ft10, 56*4 \n\ + c.fldsp ft11, 58*4 \n");\ +} +#else /*__riscv_flen == 64*/ +#define SAVE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fsdsp ft0, 20*4(sp)\n\ + c.fsdsp ft1, 22*4(sp) \n\ + c.fsdsp ft2, 24*4(sp) \n\ + c.fsdsp ft3, 26*4(sp) \n\ + c.fsdsp ft4, 28*4(sp) \n\ + c.fsdsp ft5, 30*4(sp) \n\ + c.fsdsp ft6, 32*4(sp) \n\ + c.fsdsp ft7, 34*4(sp) \n\ + c.fsdsp fa0, 36*4(sp) \n\ + c.fsdsp fa1, 38*4(sp) \n\ + c.fsdsp fa2, 40*4(sp) \n\ + c.fsdsp fa3, 42*4(sp) \n\ + c.fsdsp fa4, 44*4(sp) \n\ + c.fsdsp fa5, 46*4(sp) \n\ + c.fsdsp fa6, 48*4(sp) \n\ + c.fsdsp fa7, 50*4(sp) \n\ + c.fsdsp ft8, 52*4(sp) \n\ + c.fsdsp ft9, 54*4(sp) \n\ + c.fsdsp ft10, 56*4(sp) \n\ + c.fsdsp ft11, 58*4(sp) \n");\ +} + +/* + * Restore FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack + */ +#define RESTORE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fldsp ft0, 20*4(sp)\n\ + c.fldsp ft1, 22*4(sp) \n\ + c.fldsp ft2, 24*4(sp) \n\ + c.fldsp ft3, 26*4(sp) \n\ + c.fldsp ft4, 28*4(sp) \n\ + c.fldsp ft5, 30*4(sp) \n\ + c.fldsp ft6, 32*4(sp) \n\ + c.fldsp ft7, 34*4(sp) \n\ + c.fldsp fa0, 36*4(sp) \n\ + c.fldsp fa1, 38*4(sp) \n\ + c.fldsp fa2, 40*4(sp) \n\ + c.fldsp fa3, 42*4(sp) \n\ + c.fldsp fa4, 44*4(sp) \n\ + c.fldsp fa5, 46*4(sp) \n\ + c.fldsp fa6, 48*4(sp) \n\ + c.fldsp fa7, 50*4(sp) \n\ + c.fldsp ft8, 52*4(sp) \n\ + c.fldsp ft9, 54*4(sp) \n\ + c.fldsp ft10, 56*4(sp) \n\ + c.fldsp ft11, 58*4(sp) \n");\ +} +#endif +#endif +#else +#define SAVE_FPU_CONTEXT() +#define RESTORE_FPU_CONTEXT() +#endif + +#ifdef __ICCRISCV__ +/** + * @brief Save the caller registers based on the RISC-V ABI specification + */ +#define SAVE_CALLER_CONTEXT() { \ + __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\ + __asm volatile("\n\ + c.swsp ra, 0*4 \n\ + c.swsp t0, 1*4 \n\ + c.swsp t1, 2*4 \n\ + c.swsp t2, 3*4 \n\ + c.swsp s0, 4*4 \n\ + c.swsp s1, 5*4 \n\ + c.swsp a0, 6*4 \n\ + c.swsp a1, 7*4 \n\ + c.swsp a2, 8*4 \n\ + c.swsp a3, 9*4 \n\ + c.swsp a4, 10*4 \n\ + c.swsp a5, 11*4 \n\ + c.swsp a6, 12*4 \n\ + c.swsp a7, 13*4 \n\ + c.swsp s2, 14*4 \n\ + c.swsp s3, 15*4 \n\ + c.swsp t3, 16*4 \n\ + c.swsp t4, 17*4 \n\ + c.swsp t5, 18*4 \n\ + c.swsp t6, 19*4"); \ + SAVE_FPU_CONTEXT(); \ +} + +/** + * @brief Restore the caller registers based on the RISC-V ABI specification + */ +#define RESTORE_CALLER_CONTEXT() { \ + __asm volatile("\n\ + c.lwsp ra, 0*4 \n\ + c.lwsp t0, 1*4 \n\ + c.lwsp t1, 2*4 \n\ + c.lwsp t2, 3*4 \n\ + c.lwsp s0, 4*4 \n\ + c.lwsp s1, 5*4 \n\ + c.lwsp a0, 6*4 \n\ + c.lwsp a1, 7*4 \n\ + c.lwsp a2, 8*4 \n\ + c.lwsp a3, 9*4 \n\ + c.lwsp a4, 10*4 \n\ + c.lwsp a5, 11*4 \n\ + c.lwsp a6, 12*4 \n\ + c.lwsp a7, 13*4 \n\ + c.lwsp s2, 14*4 \n\ + c.lwsp s3, 15*4 \n\ + c.lwsp t3, 16*4 \n\ + c.lwsp t4, 17*4 \n\ + c.lwsp t5, 18*4 \n\ + c.lwsp t6, 19*4 \n");\ + RESTORE_FPU_CONTEXT(); \ + __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\ +} +#else +/** + * @brief Save the caller registers based on the RISC-V ABI specification + */ +#define SAVE_CALLER_CONTEXT() { \ + __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\ + __asm volatile("\n\ + c.swsp ra, 0*4(sp) \n\ + c.swsp t0, 1*4(sp) \n\ + c.swsp t1, 2*4(sp) \n\ + c.swsp t2, 3*4(sp) \n\ + c.swsp s0, 4*4(sp) \n\ + c.swsp s1, 5*4(sp) \n\ + c.swsp a0, 6*4(sp) \n\ + c.swsp a1, 7*4(sp) \n\ + c.swsp a2, 8*4(sp) \n\ + c.swsp a3, 9*4(sp) \n\ + c.swsp a4, 10*4(sp) \n\ + c.swsp a5, 11*4(sp) \n\ + c.swsp a6, 12*4(sp) \n\ + c.swsp a7, 13*4(sp) \n\ + c.swsp s2, 14*4(sp) \n\ + c.swsp s3, 15*4(sp) \n\ + c.swsp t3, 16*4(sp) \n\ + c.swsp t4, 17*4(sp) \n\ + c.swsp t5, 18*4(sp) \n\ + c.swsp t6, 19*4(sp)"); \ + SAVE_FPU_CONTEXT(); \ +} + +/** + * @brief Restore the caller registers based on the RISC-V ABI specification + */ +#define RESTORE_CALLER_CONTEXT() { \ + __asm volatile("\n\ + c.lwsp ra, 0*4(sp) \n\ + c.lwsp t0, 1*4(sp) \n\ + c.lwsp t1, 2*4(sp) \n\ + c.lwsp t2, 3*4(sp) \n\ + c.lwsp s0, 4*4(sp) \n\ + c.lwsp s1, 5*4(sp) \n\ + c.lwsp a0, 6*4(sp) \n\ + c.lwsp a1, 7*4(sp) \n\ + c.lwsp a2, 8*4(sp) \n\ + c.lwsp a3, 9*4(sp) \n\ + c.lwsp a4, 10*4(sp) \n\ + c.lwsp a5, 11*4(sp) \n\ + c.lwsp a6, 12*4(sp) \n\ + c.lwsp a7, 13*4(sp) \n\ + c.lwsp s2, 14*4(sp) \n\ + c.lwsp s3, 15*4(sp) \n\ + c.lwsp t3, 16*4(sp) \n\ + c.lwsp t4, 17*4(sp) \n\ + c.lwsp t5, 18*4(sp) \n\ + c.lwsp t6, 19*4(sp) \n");\ + RESTORE_FPU_CONTEXT(); \ + __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\ +} +#endif + +#ifdef __riscv_flen +#define SAVE_FPU_STATE() { \ + __asm volatile("frcsr s1\n"); \ +} + +#define RESTORE_FPU_STATE() { \ + __asm volatile("fscsr s1\n"); \ +} +#else +#define SAVE_FPU_STATE() +#define RESTORE_FPU_STATE() +#endif + +#ifdef __riscv_dsp +/* + * Save DSP context + * NOTE: DSP context registers are stored at word offset 41 in the stack + */ +#define SAVE_DSP_CONTEXT() { \ + __asm volatile("csrrs s0, %0, x0\n" ::"i"(CSR_UCODE):); \ +} +/* + * @brief Restore DSP context + * @note DSP context registers are stored at word offset 41 in the stack + */ +#define RESTORE_DSP_CONTEXT() {\ + __asm volatile("csrw %0, s0\n" ::"i"(CSR_UCODE):); \ +} + +#else +#define SAVE_DSP_CONTEXT() +#define RESTORE_DSP_CONTEXT() +#endif + +/* + * @brief Enter Nested IRQ Handling + * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: + * MCAUSE - word offset 16 (not used in the vectored mode) + * EPC - word offset 17 + * MSTATUS = word offset 18 + * MXSTATUS = word offset 19 + */ +#define ENTER_NESTED_IRQ_HANDLING_M() { \ + __asm volatile("\n\ + csrr s2, mepc \n\ + csrr s3, mstatus \n");\ + SAVE_FPU_STATE(); \ + SAVE_DSP_CONTEXT(); \ + __asm volatile("csrsi mstatus, 8"); \ +} + +/* + * @brief Complete IRQ Handling + */ +#define COMPLETE_IRQ_HANDLING_M(irq_num) { \ + __asm volatile("csrci mstatus, 8"); \ + __asm volatile("lui a4, 0xe4200"); \ + __asm volatile("li a3, %0" : : "i" (irq_num) :); \ + __asm volatile("sw a3, 4(a4)"); \ +} + +/* + * @brief Exit Nested IRQ Handling + * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: + * MCAUSE - word offset 16 (not used in the vectored mode) + * EPC - word offset 17 + * MSTATUS = word offset 18 + * MXSTATUS = word offset 19 + */ +#define EXIT_NESTED_IRQ_HANDLING_M() { \ + __asm volatile("\n\ + csrw mstatus, s3 \n\ + csrw mepc, s2 \n");\ + RESTORE_FPU_STATE(); \ + RESTORE_DSP_CONTEXT(); \ +} + + +#define ENTER_NESTED_IRQ_HANDLING_S() {\ + __asm volatile("\n\ + csrr s2, sepc \n\ + csrr s3, sstatus \n");\ + SAVE_FPU_STATE(); \ + SAVE_DSP_CONTEXT(); \ + __asm volatile("csrsi sstatus, 2"); \ +} +#define COMPLETE_IRQ_HANDLING_S(irq_num) {\ + __asm volatile("csrci sstatus, 2"); \ + __asm volatile("lui a4, 0xe4201"); \ + __asm volatile("li a3, %0" : : "i" (irq_num) :); \ + __asm volatile("sw a3, 4(a4)"); \ +} + +/* + * @brief Exit Nested IRQ Handling at supervisor mode + * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: + * SCAUSE - word offset 16 (not used in the vectored mode) + * EPC - word offset 17 + * SSTATUS = word offset 18 + */ +#define EXIT_NESTED_IRQ_HANDLING_S() { \ + __asm volatile("\n\ + csrw sstatus, s3 \n\ + csrw sepc, s2 \n");\ + RESTORE_FPU_STATE(); \ + RESTORE_DSP_CONTEXT(); \ +} + +/* @brief Nested IRQ entry macro : Save CSRs and enable global irq. */ +#define NESTED_IRQ_ENTER() \ + SAVE_CSR(CSR_MEPC) \ + SAVE_CSR(CSR_MSTATUS) \ + SAVE_MXSTATUS() \ + SAVE_FCSR() \ + SAVE_UCODE() \ + set_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); + +/* @brief Nested IRQ exit macro : Restore CSRs */ +#define NESTED_IRQ_EXIT() \ + RESTORE_CSR(CSR_MSTATUS) \ + RESTORE_CSR(CSR_MEPC) \ + RESTORE_MXSTATUS() \ + RESTORE_FCSR() \ + RESTORE_UCODE() + +#ifdef __cplusplus +#define EXTERN_C extern "C" +#else +#define EXTERN_C +#endif + +#define ISR_NAME_M(irq_num) default_isr_##irq_num +#define ISR_NAME_S(irq_num) default_isr_s_##irq_num +/** + * @brief Declare an external interrupt handler for machine mode + * + * @param[in] irq_num - IRQ number index + * @param[in] isr - Application IRQ handler function pointer + */ +#ifndef USE_NONVECTOR_MODE + +#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ +void isr(void) __attribute__((section(".isr_vector")));\ +EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ +void ISR_NAME_M(irq_num)(void) \ +{ \ + SAVE_CALLER_CONTEXT(); \ + ENTER_NESTED_IRQ_HANDLING_M();\ + __asm volatile("la t1, %0\n\t" : : "i" (isr) : );\ + __asm volatile("jalr t1\n");\ + COMPLETE_IRQ_HANDLING_M(irq_num);\ + EXIT_NESTED_IRQ_HANDLING_M();\ + RESTORE_CALLER_CONTEXT();\ + __asm volatile("fence io, io");\ + __asm volatile("mret\n");\ +} + +/** + * @brief Declare an external interrupt handler for supervisor mode + * + * @param[in] irq_num - IRQ number index + * @param[in] isr - Application IRQ handler function pointer + */ +#define SDK_DECLARE_EXT_ISR_S(irq_num, isr) \ +void isr(void) __attribute__((section(".isr_s_vector")));\ +EXTERN_C void ISR_NAME_S(irq_num)(void) __attribute__((section(".isr_s_vector")));\ +void ISR_NAME_S(irq_num)(void) {\ + SAVE_CALLER_CONTEXT(); \ + ENTER_NESTED_IRQ_HANDLING_S();\ + __asm volatile("la t1, %0\n\t" : : "i" (isr) : );\ + __asm volatile("jalr t1\n");\ + COMPLETE_IRQ_HANDLING_S(irq_num);\ + EXIT_NESTED_IRQ_HANDLING_S();\ + RESTORE_CALLER_CONTEXT();\ + __asm volatile("fence io, io");\ + __asm volatile("sret\n");\ +} + +#else + +#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ +void isr(void) __attribute__((section(".isr_vector")));\ +EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ +void ISR_NAME_M(irq_num)(void) { \ + isr(); \ +} + +#define SDK_DECLARE_EXT_ISR_S(irq_num, isr) \ +void isr(void) __attribute__((section(".isr_vector")));\ +EXTERN_C void ISR_NAME_S(irq_num)(void) __attribute__((section(".isr_vector")));\ +void ISR_NAME_S(irq_num)(void) { \ + isr(); \ +} + +#endif + + +/** + * @brief Declare machine timer interrupt handler + * + * @param[in] isr - MCHTMR IRQ handler function pointer + */ +#define SDK_DECLARE_MCHTMR_ISR(isr) \ +void isr(void) __attribute__((section(".isr_vector")));\ +EXTERN_C void mchtmr_isr(void) __attribute__((section(".isr_vector"))); \ +void mchtmr_isr(void) {\ + isr();\ +} + +/** + * @brief Declare machine software interrupt handler + * + * @param[in] isr - SWI IRQ handler function pointer + */ +#define SDK_DECLARE_SWI_ISR(isr)\ +void isr(void) __attribute__((section(".isr_vector")));\ +EXTERN_C void swi_isr(void) __attribute__((section(".isr_vector"))); \ +void swi_isr(void) {\ + isr();\ +} + +/* Supervisor mode */ + +/** + * @brief Declare machine timer interrupt handler + * + * @param[in] isr - MCHTMR IRQ handler function pointer + */ +#define SDK_DECLARE_MCHTMR_ISR_S(isr) \ +void isr(void) __attribute__((section(".isr_vector")));\ +EXTERN_C void mchtmr_s_isr(void) __attribute__((section(".isr_vector"))); \ +void mchtmr_s_isr(void) {\ + isr();\ +} + +/** + * @brief Declare machine software interrupt handler + * + * @param[in] isr - SWI IRQ handler function pointer + */ +#define SDK_DECLARE_SWI_ISR_S(isr)\ +void isr(void) __attribute__((section(".isr_vector")));\ +EXTERN_C void swi_s_isr(void) __attribute__((section(".isr_vector"))); \ +void swi_s_isr(void) {\ + isr();\ +} + +#define CSR_MSTATUS_MPP_S_MODE (0x1) +#define MODE_SWITCH_FROM_M(mstatus, mepc, label, mode) \ +do { \ + if (label) { \ + write_csr(mepc, label); \ + } \ + clear_csr(mstatus, CSR_MSTATUS_MPP_MASK); \ + set_csr(mstatus, CSR_MSTATUS_MPP_SET(mode)); \ +} while(0) + +typedef void (*s_mode_entry)(void); + +/** + * @brief Switch mode to supervisor from machine + * + * @param[in] entry - entry point after mode is switched + */ +static inline void switch_to_s_mode(s_mode_entry entry) +{ + write_csr(CSR_SEPC, entry); + MODE_SWITCH_FROM_M(CSR_MSTATUS, CSR_MEPC, entry, CSR_MSTATUS_MPP_S_MODE); + if (entry) { + __asm("mret"); + } +} +#ifdef __cplusplus +} +#endif + +/** + * @} + */ +#endif /* HPM_INTERRUPT_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_ioc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_ioc_regs.h new file mode 100644 index 00000000000..26042597d8c --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_ioc_regs.h @@ -0,0 +1,419 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_IOC_H +#define HPM_IOC_H + +typedef struct { + struct { + __RW uint32_t FUNC_CTL; /* 0x0: ALT SELECT */ + __RW uint32_t PAD_CTL; /* 0x4: PAD SETTINGS */ + } PAD[496]; +} IOC_Type; + + +/* Bitfield definition for register of struct array PAD: FUNC_CTL */ +/* + * LOOP_BACK (RW) + * + * force input on + * 0: disable + * 1: enable + */ +#define IOC_PAD_FUNC_CTL_LOOP_BACK_MASK (0x10000UL) +#define IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT (16U) +#define IOC_PAD_FUNC_CTL_LOOP_BACK_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT) & IOC_PAD_FUNC_CTL_LOOP_BACK_MASK) +#define IOC_PAD_FUNC_CTL_LOOP_BACK_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_LOOP_BACK_MASK) >> IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT) + +/* + * ANALOG (RW) + * + * select analog pin in pad + * 0: disable + * 1: enable + */ +#define IOC_PAD_FUNC_CTL_ANALOG_MASK (0x100U) +#define IOC_PAD_FUNC_CTL_ANALOG_SHIFT (8U) +#define IOC_PAD_FUNC_CTL_ANALOG_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_ANALOG_SHIFT) & IOC_PAD_FUNC_CTL_ANALOG_MASK) +#define IOC_PAD_FUNC_CTL_ANALOG_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_ANALOG_MASK) >> IOC_PAD_FUNC_CTL_ANALOG_SHIFT) + +/* + * ALT_SELECT (RW) + * + * alt select + * 0: ALT0 + * 1: ALT1 + * ... + * 31:ALT31 + */ +#define IOC_PAD_FUNC_CTL_ALT_SELECT_MASK (0x1FU) +#define IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT (0U) +#define IOC_PAD_FUNC_CTL_ALT_SELECT_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT) & IOC_PAD_FUNC_CTL_ALT_SELECT_MASK) +#define IOC_PAD_FUNC_CTL_ALT_SELECT_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_ALT_SELECT_MASK) >> IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT) + +/* Bitfield definition for register of struct array PAD: PAD_CTL */ +/* + * HYS (RW) + * + * schmitt trigger enable + * 0: disable + * 1: enable + */ +#define IOC_PAD_PAD_CTL_HYS_MASK (0x1000000UL) +#define IOC_PAD_PAD_CTL_HYS_SHIFT (24U) +#define IOC_PAD_PAD_CTL_HYS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_HYS_SHIFT) & IOC_PAD_PAD_CTL_HYS_MASK) +#define IOC_PAD_PAD_CTL_HYS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_HYS_MASK) >> IOC_PAD_PAD_CTL_HYS_SHIFT) + +/* + * PRS (RW) + * + * select pull up/down internal resistance strength: + * For pull down, only have 100 Kohm resistance + * For pull up: + * 00: 100 KOhm + * 01: 47 KOhm + * 10: 22 KOhm + * 11: 22 KOhm + */ +#define IOC_PAD_PAD_CTL_PRS_MASK (0x300000UL) +#define IOC_PAD_PAD_CTL_PRS_SHIFT (20U) +#define IOC_PAD_PAD_CTL_PRS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PRS_SHIFT) & IOC_PAD_PAD_CTL_PRS_MASK) +#define IOC_PAD_PAD_CTL_PRS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PRS_MASK) >> IOC_PAD_PAD_CTL_PRS_SHIFT) + +/* + * PS (RW) + * + * pull select + * 0: pull down + * 1: pull up + */ +#define IOC_PAD_PAD_CTL_PS_MASK (0x40000UL) +#define IOC_PAD_PAD_CTL_PS_SHIFT (18U) +#define IOC_PAD_PAD_CTL_PS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PS_SHIFT) & IOC_PAD_PAD_CTL_PS_MASK) +#define IOC_PAD_PAD_CTL_PS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PS_MASK) >> IOC_PAD_PAD_CTL_PS_SHIFT) + +/* + * PE (RW) + * + * pull enable + * 0: pull disable + * 1: pull enable + */ +#define IOC_PAD_PAD_CTL_PE_MASK (0x20000UL) +#define IOC_PAD_PAD_CTL_PE_SHIFT (17U) +#define IOC_PAD_PAD_CTL_PE_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PE_SHIFT) & IOC_PAD_PAD_CTL_PE_MASK) +#define IOC_PAD_PAD_CTL_PE_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PE_MASK) >> IOC_PAD_PAD_CTL_PE_SHIFT) + +/* + * KE (RW) + * + * keeper capability enable + * 0: keeper disable + * 1: keeper enable + */ +#define IOC_PAD_PAD_CTL_KE_MASK (0x10000UL) +#define IOC_PAD_PAD_CTL_KE_SHIFT (16U) +#define IOC_PAD_PAD_CTL_KE_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_KE_SHIFT) & IOC_PAD_PAD_CTL_KE_MASK) +#define IOC_PAD_PAD_CTL_KE_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_KE_MASK) >> IOC_PAD_PAD_CTL_KE_SHIFT) + +/* + * OD (RW) + * + * open drain + * 0: open drain disable + * 1: open drain enable + */ +#define IOC_PAD_PAD_CTL_OD_MASK (0x100U) +#define IOC_PAD_PAD_CTL_OD_SHIFT (8U) +#define IOC_PAD_PAD_CTL_OD_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_OD_SHIFT) & IOC_PAD_PAD_CTL_OD_MASK) +#define IOC_PAD_PAD_CTL_OD_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_OD_MASK) >> IOC_PAD_PAD_CTL_OD_SHIFT) + +/* + * SR (RW) + * + * slew rate + * 0: Slow slew rate + * 1: Fast slew rate + */ +#define IOC_PAD_PAD_CTL_SR_MASK (0x40U) +#define IOC_PAD_PAD_CTL_SR_SHIFT (6U) +#define IOC_PAD_PAD_CTL_SR_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_SR_SHIFT) & IOC_PAD_PAD_CTL_SR_MASK) +#define IOC_PAD_PAD_CTL_SR_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_SR_MASK) >> IOC_PAD_PAD_CTL_SR_SHIFT) + +/* + * SPD (RW) + * + * additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise + * 00: Slow frequency slew rate(50Mhz) + * 01: Medium frequency slew rate(100 Mhz) + * 10: Fast frequency slew rate(150 Mhz) + * 11: Max frequency slew rate(200Mhz) + */ +#define IOC_PAD_PAD_CTL_SPD_MASK (0x30U) +#define IOC_PAD_PAD_CTL_SPD_SHIFT (4U) +#define IOC_PAD_PAD_CTL_SPD_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_SPD_SHIFT) & IOC_PAD_PAD_CTL_SPD_MASK) +#define IOC_PAD_PAD_CTL_SPD_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_SPD_MASK) >> IOC_PAD_PAD_CTL_SPD_SHIFT) + +/* + * DS (RW) + * + * drive strength + * 1.8V Mode: + * 000: 260 Ohm + * 001: 260 Ohm + * 010: 130 Ohm + * 011: 88 Ohm + * 100: 65 Ohm + * 101: 52 Ohm + * 110: 43 Ohm + * 111: 37 Ohm + * 3.3V Mode: + * 000: 157 Ohm + * 001: 157 Ohm + * 010: 78 Ohm + * 011: 53 Ohm + * 100: 39 Ohm + * 101: 32 Ohm + * 110: 26 Ohm + * 111: 23 Ohm + */ +#define IOC_PAD_PAD_CTL_DS_MASK (0x7U) +#define IOC_PAD_PAD_CTL_DS_SHIFT (0U) +#define IOC_PAD_PAD_CTL_DS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_DS_SHIFT) & IOC_PAD_PAD_CTL_DS_MASK) +#define IOC_PAD_PAD_CTL_DS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_DS_MASK) >> IOC_PAD_PAD_CTL_DS_SHIFT) + + + +/* PAD register group index macro definition */ +#define IOC_PAD_PA00 (0UL) +#define IOC_PAD_PA01 (1UL) +#define IOC_PAD_PA02 (2UL) +#define IOC_PAD_PA03 (3UL) +#define IOC_PAD_PA04 (4UL) +#define IOC_PAD_PA05 (5UL) +#define IOC_PAD_PA06 (6UL) +#define IOC_PAD_PA07 (7UL) +#define IOC_PAD_PA08 (8UL) +#define IOC_PAD_PA09 (9UL) +#define IOC_PAD_PA10 (10UL) +#define IOC_PAD_PA11 (11UL) +#define IOC_PAD_PA12 (12UL) +#define IOC_PAD_PA13 (13UL) +#define IOC_PAD_PA14 (14UL) +#define IOC_PAD_PA15 (15UL) +#define IOC_PAD_PA16 (16UL) +#define IOC_PAD_PA17 (17UL) +#define IOC_PAD_PA18 (18UL) +#define IOC_PAD_PA19 (19UL) +#define IOC_PAD_PA20 (20UL) +#define IOC_PAD_PA21 (21UL) +#define IOC_PAD_PA22 (22UL) +#define IOC_PAD_PA23 (23UL) +#define IOC_PAD_PA24 (24UL) +#define IOC_PAD_PA25 (25UL) +#define IOC_PAD_PA26 (26UL) +#define IOC_PAD_PA27 (27UL) +#define IOC_PAD_PA28 (28UL) +#define IOC_PAD_PA29 (29UL) +#define IOC_PAD_PA30 (30UL) +#define IOC_PAD_PA31 (31UL) +#define IOC_PAD_PB00 (32UL) +#define IOC_PAD_PB01 (33UL) +#define IOC_PAD_PB02 (34UL) +#define IOC_PAD_PB03 (35UL) +#define IOC_PAD_PB04 (36UL) +#define IOC_PAD_PB05 (37UL) +#define IOC_PAD_PB06 (38UL) +#define IOC_PAD_PB07 (39UL) +#define IOC_PAD_PB08 (40UL) +#define IOC_PAD_PB09 (41UL) +#define IOC_PAD_PB10 (42UL) +#define IOC_PAD_PB11 (43UL) +#define IOC_PAD_PB12 (44UL) +#define IOC_PAD_PB13 (45UL) +#define IOC_PAD_PB14 (46UL) +#define IOC_PAD_PB15 (47UL) +#define IOC_PAD_PB16 (48UL) +#define IOC_PAD_PB17 (49UL) +#define IOC_PAD_PB18 (50UL) +#define IOC_PAD_PB19 (51UL) +#define IOC_PAD_PB20 (52UL) +#define IOC_PAD_PB21 (53UL) +#define IOC_PAD_PB22 (54UL) +#define IOC_PAD_PB23 (55UL) +#define IOC_PAD_PB24 (56UL) +#define IOC_PAD_PB25 (57UL) +#define IOC_PAD_PB26 (58UL) +#define IOC_PAD_PB27 (59UL) +#define IOC_PAD_PB28 (60UL) +#define IOC_PAD_PB29 (61UL) +#define IOC_PAD_PB30 (62UL) +#define IOC_PAD_PB31 (63UL) +#define IOC_PAD_PC00 (64UL) +#define IOC_PAD_PC01 (65UL) +#define IOC_PAD_PC02 (66UL) +#define IOC_PAD_PC03 (67UL) +#define IOC_PAD_PC04 (68UL) +#define IOC_PAD_PC05 (69UL) +#define IOC_PAD_PC06 (70UL) +#define IOC_PAD_PC07 (71UL) +#define IOC_PAD_PC08 (72UL) +#define IOC_PAD_PC09 (73UL) +#define IOC_PAD_PC10 (74UL) +#define IOC_PAD_PC11 (75UL) +#define IOC_PAD_PC12 (76UL) +#define IOC_PAD_PC13 (77UL) +#define IOC_PAD_PC14 (78UL) +#define IOC_PAD_PC15 (79UL) +#define IOC_PAD_PC16 (80UL) +#define IOC_PAD_PC17 (81UL) +#define IOC_PAD_PC18 (82UL) +#define IOC_PAD_PC19 (83UL) +#define IOC_PAD_PC20 (84UL) +#define IOC_PAD_PC21 (85UL) +#define IOC_PAD_PC22 (86UL) +#define IOC_PAD_PC23 (87UL) +#define IOC_PAD_PC24 (88UL) +#define IOC_PAD_PC25 (89UL) +#define IOC_PAD_PC26 (90UL) +#define IOC_PAD_PC27 (91UL) +#define IOC_PAD_PC28 (92UL) +#define IOC_PAD_PC29 (93UL) +#define IOC_PAD_PC30 (94UL) +#define IOC_PAD_PC31 (95UL) +#define IOC_PAD_PD00 (96UL) +#define IOC_PAD_PD01 (97UL) +#define IOC_PAD_PD02 (98UL) +#define IOC_PAD_PD03 (99UL) +#define IOC_PAD_PD04 (100UL) +#define IOC_PAD_PD05 (101UL) +#define IOC_PAD_PD06 (102UL) +#define IOC_PAD_PD07 (103UL) +#define IOC_PAD_PD08 (104UL) +#define IOC_PAD_PD09 (105UL) +#define IOC_PAD_PD10 (106UL) +#define IOC_PAD_PD11 (107UL) +#define IOC_PAD_PD12 (108UL) +#define IOC_PAD_PD13 (109UL) +#define IOC_PAD_PD14 (110UL) +#define IOC_PAD_PD15 (111UL) +#define IOC_PAD_PD16 (112UL) +#define IOC_PAD_PD17 (113UL) +#define IOC_PAD_PD18 (114UL) +#define IOC_PAD_PD19 (115UL) +#define IOC_PAD_PD20 (116UL) +#define IOC_PAD_PD21 (117UL) +#define IOC_PAD_PD22 (118UL) +#define IOC_PAD_PD23 (119UL) +#define IOC_PAD_PD24 (120UL) +#define IOC_PAD_PD25 (121UL) +#define IOC_PAD_PD26 (122UL) +#define IOC_PAD_PD27 (123UL) +#define IOC_PAD_PD28 (124UL) +#define IOC_PAD_PD29 (125UL) +#define IOC_PAD_PD30 (126UL) +#define IOC_PAD_PD31 (127UL) +#define IOC_PAD_PE00 (128UL) +#define IOC_PAD_PE01 (129UL) +#define IOC_PAD_PE02 (130UL) +#define IOC_PAD_PE03 (131UL) +#define IOC_PAD_PE04 (132UL) +#define IOC_PAD_PE05 (133UL) +#define IOC_PAD_PE06 (134UL) +#define IOC_PAD_PE07 (135UL) +#define IOC_PAD_PE08 (136UL) +#define IOC_PAD_PE09 (137UL) +#define IOC_PAD_PE10 (138UL) +#define IOC_PAD_PE11 (139UL) +#define IOC_PAD_PE12 (140UL) +#define IOC_PAD_PE13 (141UL) +#define IOC_PAD_PE14 (142UL) +#define IOC_PAD_PE15 (143UL) +#define IOC_PAD_PE16 (144UL) +#define IOC_PAD_PE17 (145UL) +#define IOC_PAD_PE18 (146UL) +#define IOC_PAD_PE19 (147UL) +#define IOC_PAD_PE20 (148UL) +#define IOC_PAD_PE21 (149UL) +#define IOC_PAD_PE22 (150UL) +#define IOC_PAD_PE23 (151UL) +#define IOC_PAD_PE24 (152UL) +#define IOC_PAD_PE25 (153UL) +#define IOC_PAD_PE26 (154UL) +#define IOC_PAD_PE27 (155UL) +#define IOC_PAD_PE28 (156UL) +#define IOC_PAD_PE29 (157UL) +#define IOC_PAD_PE30 (158UL) +#define IOC_PAD_PE31 (159UL) +#define IOC_PAD_PF00 (160UL) +#define IOC_PAD_PF01 (161UL) +#define IOC_PAD_PF02 (162UL) +#define IOC_PAD_PF03 (163UL) +#define IOC_PAD_PF04 (164UL) +#define IOC_PAD_PF05 (165UL) +#define IOC_PAD_PF06 (166UL) +#define IOC_PAD_PF07 (167UL) +#define IOC_PAD_PF08 (168UL) +#define IOC_PAD_PF09 (169UL) +#define IOC_PAD_PF10 (170UL) +#define IOC_PAD_PF11 (171UL) +#define IOC_PAD_PF12 (172UL) +#define IOC_PAD_PF13 (173UL) +#define IOC_PAD_PF14 (174UL) +#define IOC_PAD_PF15 (175UL) +#define IOC_PAD_PX00 (416UL) +#define IOC_PAD_PX01 (417UL) +#define IOC_PAD_PX02 (418UL) +#define IOC_PAD_PX03 (419UL) +#define IOC_PAD_PX04 (420UL) +#define IOC_PAD_PX05 (421UL) +#define IOC_PAD_PX06 (422UL) +#define IOC_PAD_PX07 (423UL) +#define IOC_PAD_PX08 (424UL) +#define IOC_PAD_PX09 (425UL) +#define IOC_PAD_PX10 (426UL) +#define IOC_PAD_PX11 (427UL) +#define IOC_PAD_PX12 (428UL) +#define IOC_PAD_PX13 (429UL) +#define IOC_PAD_PX14 (430UL) +#define IOC_PAD_PX15 (431UL) +#define IOC_PAD_PY00 (448UL) +#define IOC_PAD_PY01 (449UL) +#define IOC_PAD_PY02 (450UL) +#define IOC_PAD_PY03 (451UL) +#define IOC_PAD_PY04 (452UL) +#define IOC_PAD_PY05 (453UL) +#define IOC_PAD_PY06 (454UL) +#define IOC_PAD_PY07 (455UL) +#define IOC_PAD_PY08 (456UL) +#define IOC_PAD_PY09 (457UL) +#define IOC_PAD_PY10 (458UL) +#define IOC_PAD_PY11 (459UL) +#define IOC_PAD_PY12 (460UL) +#define IOC_PAD_PY13 (461UL) +#define IOC_PAD_PY14 (462UL) +#define IOC_PAD_PY15 (463UL) +#define IOC_PAD_PZ00 (480UL) +#define IOC_PAD_PZ01 (481UL) +#define IOC_PAD_PZ02 (482UL) +#define IOC_PAD_PZ03 (483UL) +#define IOC_PAD_PZ04 (484UL) +#define IOC_PAD_PZ05 (485UL) +#define IOC_PAD_PZ06 (486UL) +#define IOC_PAD_PZ07 (487UL) +#define IOC_PAD_PZ08 (488UL) +#define IOC_PAD_PZ09 (489UL) +#define IOC_PAD_PZ10 (490UL) +#define IOC_PAD_PZ11 (491UL) +#define IOC_PAD_PZ12 (492UL) +#define IOC_PAD_PZ13 (493UL) +#define IOC_PAD_PZ14 (494UL) +#define IOC_PAD_PZ15 (495UL) + + +#endif /* HPM_IOC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_iomux.h new file mode 100644 index 00000000000..2677132d897 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_iomux.h @@ -0,0 +1,1965 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_IOMUX_H +#define HPM_IOMUX_H + +/* IOC_PA00_FUNC_CTL function mux definitions */ +#define IOC_PA00_FUNC_CTL_GPIO_A_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA00_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA00_FUNC_CTL_DAO_RN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PA01_FUNC_CTL function mux definitions */ +#define IOC_PA01_FUNC_CTL_GPIO_A_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA01_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA01_FUNC_CTL_DAO_RP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PA02_FUNC_CTL function mux definitions */ +#define IOC_PA02_FUNC_CTL_GPIO_A_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA02_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA02_FUNC_CTL_DAO_LN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PA03_FUNC_CTL function mux definitions */ +#define IOC_PA03_FUNC_CTL_GPIO_A_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA03_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA03_FUNC_CTL_DAO_LP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PA04_FUNC_CTL function mux definitions */ +#define IOC_PA04_FUNC_CTL_GPIO_A_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA04_FUNC_CTL_GPTMR1_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA04_FUNC_CTL_JTAG_TDO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA05_FUNC_CTL function mux definitions */ +#define IOC_PA05_FUNC_CTL_GPIO_A_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA05_FUNC_CTL_GPTMR1_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA05_FUNC_CTL_JTAG_TDI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA06_FUNC_CTL function mux definitions */ +#define IOC_PA06_FUNC_CTL_GPIO_A_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA06_FUNC_CTL_JTAG_TCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA07_FUNC_CTL function mux definitions */ +#define IOC_PA07_FUNC_CTL_GPIO_A_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA07_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA07_FUNC_CTL_JTAG_TMS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA08_FUNC_CTL function mux definitions */ +#define IOC_PA08_FUNC_CTL_GPIO_A_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA08_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA08_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA08_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PA08_FUNC_CTL_JTAG_TRST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA09_FUNC_CTL function mux definitions */ +#define IOC_PA09_FUNC_CTL_GPIO_A_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA09_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA09_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA09_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PA10_FUNC_CTL function mux definitions */ +#define IOC_PA10_FUNC_CTL_GPIO_A_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA10_FUNC_CTL_GPTMR0_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA10_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA10_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA10_FUNC_CTL_SPI0_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA10_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PA10_FUNC_CTL_DIS0_G_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA10_FUNC_CTL_CAM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA11_FUNC_CTL function mux definitions */ +#define IOC_PA11_FUNC_CTL_GPIO_A_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA11_FUNC_CTL_GPTMR0_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA11_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA11_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA11_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PA11_FUNC_CTL_DIS0_G_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA11_FUNC_CTL_CAM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA12_FUNC_CTL function mux definitions */ +#define IOC_PA12_FUNC_CTL_GPIO_A_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA12_FUNC_CTL_GPTMR1_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA12_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA12_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA12_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA12_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PA12_FUNC_CTL_DIS0_G_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA12_FUNC_CTL_CAM0_D_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA13_FUNC_CTL function mux definitions */ +#define IOC_PA13_FUNC_CTL_GPIO_A_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA13_FUNC_CTL_GPTMR1_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA13_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA13_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA13_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA13_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA13_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PA13_FUNC_CTL_DIS0_G_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA13_FUNC_CTL_CAM0_D_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA14_FUNC_CTL function mux definitions */ +#define IOC_PA14_FUNC_CTL_GPIO_A_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA14_FUNC_CTL_GPTMR0_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA14_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA14_FUNC_CTL_I2S0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PA14_FUNC_CTL_DIS0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA14_FUNC_CTL_CAM0_VSYNC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA15_FUNC_CTL function mux definitions */ +#define IOC_PA15_FUNC_CTL_GPIO_A_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA15_FUNC_CTL_GPTMR0_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA15_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA15_FUNC_CTL_I2S0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PA15_FUNC_CTL_DIS0_R_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA15_FUNC_CTL_CAM0_HSYNC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA16_FUNC_CTL function mux definitions */ +#define IOC_PA16_FUNC_CTL_GPIO_A_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA16_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA16_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA16_FUNC_CTL_MCAN4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA16_FUNC_CTL_I2S0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PA16_FUNC_CTL_DIS0_R_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA16_FUNC_CTL_CAM0_D_9 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA17_FUNC_CTL function mux definitions */ +#define IOC_PA17_FUNC_CTL_GPIO_A_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA17_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA17_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA17_FUNC_CTL_MCAN4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA17_FUNC_CTL_I2S0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PA17_FUNC_CTL_DIS0_R_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA17_FUNC_CTL_CAM0_D_8 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA18_FUNC_CTL function mux definitions */ +#define IOC_PA18_FUNC_CTL_GPIO_A_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA18_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA18_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA18_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA18_FUNC_CTL_MCAN4_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA18_FUNC_CTL_I2S0_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PA18_FUNC_CTL_DIS0_R_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA18_FUNC_CTL_CAM0_D_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) +#define IOC_PA18_FUNC_CTL_CPU0_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA19_FUNC_CTL function mux definitions */ +#define IOC_PA19_FUNC_CTL_GPIO_A_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA19_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA19_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA19_FUNC_CTL_MCAN5_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA19_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PA19_FUNC_CTL_DIS0_R_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA19_FUNC_CTL_CAM0_D_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA20_FUNC_CTL function mux definitions */ +#define IOC_PA20_FUNC_CTL_GPIO_A_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA20_FUNC_CTL_GPTMR3_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA20_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA20_FUNC_CTL_MCAN5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA20_FUNC_CTL_I2S0_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PA20_FUNC_CTL_DIS0_G_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA20_FUNC_CTL_CAM0_PIXCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA21_FUNC_CTL function mux definitions */ +#define IOC_PA21_FUNC_CTL_GPIO_A_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA21_FUNC_CTL_GPTMR3_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA21_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA21_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA21_FUNC_CTL_MCAN5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA21_FUNC_CTL_I2S0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PA21_FUNC_CTL_CAM0_XCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA22_FUNC_CTL function mux definitions */ +#define IOC_PA22_FUNC_CTL_GPIO_A_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA22_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA22_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA22_FUNC_CTL_I2S0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) + +/* IOC_PA23_FUNC_CTL function mux definitions */ +#define IOC_PA23_FUNC_CTL_GPIO_A_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA23_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA23_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA23_FUNC_CTL_I2S0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PA23_FUNC_CTL_SDC0_RSTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA23_FUNC_CTL_CAM0_D_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA24_FUNC_CTL function mux definitions */ +#define IOC_PA24_FUNC_CTL_GPIO_A_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA24_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA24_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA24_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA24_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA24_FUNC_CTL_MCAN6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA24_FUNC_CTL_I2S0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PA24_FUNC_CTL_SDC1_VON IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA24_FUNC_CTL_CAM0_D_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA25_FUNC_CTL function mux definitions */ +#define IOC_PA25_FUNC_CTL_GPIO_A_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA25_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA25_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA25_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA25_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA25_FUNC_CTL_MCAN6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA25_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PA25_FUNC_CTL_SDC1_VSEL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA25_FUNC_CTL_CAM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA26_FUNC_CTL function mux definitions */ +#define IOC_PA26_FUNC_CTL_GPIO_A_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA26_FUNC_CTL_GPTMR2_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA26_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA26_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA26_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA26_FUNC_CTL_MCAN6_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA26_FUNC_CTL_SDC1_CDN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA26_FUNC_CTL_CAM0_PIXCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA27_FUNC_CTL function mux definitions */ +#define IOC_PA27_FUNC_CTL_GPIO_A_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA27_FUNC_CTL_GPTMR2_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA27_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA27_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA27_FUNC_CTL_SDC1_WP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA27_FUNC_CTL_CAM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA28_FUNC_CTL function mux definitions */ +#define IOC_PA28_FUNC_CTL_GPIO_A_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA28_FUNC_CTL_GPTMR3_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA28_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA28_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA28_FUNC_CTL_DIS0_R_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PA29_FUNC_CTL function mux definitions */ +#define IOC_PA29_FUNC_CTL_GPIO_A_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA29_FUNC_CTL_GPTMR3_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA29_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA29_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA29_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA29_FUNC_CTL_MCAN7_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA29_FUNC_CTL_CAM0_XCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA30_FUNC_CTL function mux definitions */ +#define IOC_PA30_FUNC_CTL_GPIO_A_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA30_FUNC_CTL_GPTMR2_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA30_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA30_FUNC_CTL_MCAN7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA30_FUNC_CTL_DIS0_R_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PA31_FUNC_CTL function mux definitions */ +#define IOC_PA31_FUNC_CTL_GPIO_A_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA31_FUNC_CTL_GPTMR2_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA31_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA31_FUNC_CTL_MCAN7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA31_FUNC_CTL_DIS0_R_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PB00_FUNC_CTL function mux definitions */ +#define IOC_PB00_FUNC_CTL_GPIO_B_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB00_FUNC_CTL_GPTMR5_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB00_FUNC_CTL_DIS0_G_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PB01_FUNC_CTL function mux definitions */ +#define IOC_PB01_FUNC_CTL_GPIO_B_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB01_FUNC_CTL_GPTMR5_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB01_FUNC_CTL_DIS0_G_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PB02_FUNC_CTL function mux definitions */ +#define IOC_PB02_FUNC_CTL_GPIO_B_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB02_FUNC_CTL_GPTMR5_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB02_FUNC_CTL_DIS0_B_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PB03_FUNC_CTL function mux definitions */ +#define IOC_PB03_FUNC_CTL_GPIO_B_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB03_FUNC_CTL_GPTMR5_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB03_FUNC_CTL_SPI3_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB03_FUNC_CTL_DIS0_B_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PB04_FUNC_CTL function mux definitions */ +#define IOC_PB04_FUNC_CTL_GPIO_B_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB04_FUNC_CTL_GPTMR5_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB04_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB04_FUNC_CTL_DIS0_B_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PB05_FUNC_CTL function mux definitions */ +#define IOC_PB05_FUNC_CTL_GPIO_B_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB05_FUNC_CTL_GPTMR5_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB05_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB05_FUNC_CTL_DIS0_G_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PB06_FUNC_CTL function mux definitions */ +#define IOC_PB06_FUNC_CTL_GPIO_B_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB06_FUNC_CTL_GPTMR4_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB06_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB06_FUNC_CTL_DIS0_B_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PB07_FUNC_CTL function mux definitions */ +#define IOC_PB07_FUNC_CTL_GPIO_B_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB07_FUNC_CTL_GPTMR4_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB07_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB07_FUNC_CTL_DIS0_B_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PB08_FUNC_CTL function mux definitions */ +#define IOC_PB08_FUNC_CTL_GPIO_B_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB08_FUNC_CTL_GPTMR4_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB08_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB08_FUNC_CTL_SPI3_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB08_FUNC_CTL_DIS0_B_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PB09_FUNC_CTL function mux definitions */ +#define IOC_PB09_FUNC_CTL_GPIO_B_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB09_FUNC_CTL_GPTMR4_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB09_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB09_FUNC_CTL_SPI3_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB09_FUNC_CTL_DIS0_B_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PB10_FUNC_CTL function mux definitions */ +#define IOC_PB10_FUNC_CTL_GPIO_B_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB10_FUNC_CTL_GPTMR4_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB10_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB10_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB10_FUNC_CTL_SPI3_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB10_FUNC_CTL_DIS0_EN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PB11_FUNC_CTL function mux definitions */ +#define IOC_PB11_FUNC_CTL_GPIO_B_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB11_FUNC_CTL_GPTMR4_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB11_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB11_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB11_FUNC_CTL_DIS0_B_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PB12_FUNC_CTL function mux definitions */ +#define IOC_PB12_FUNC_CTL_GPIO_B_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB12_FUNC_CTL_GPTMR5_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB12_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB12_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB12_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB12_FUNC_CTL_DIS0_HSYNC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PB13_FUNC_CTL function mux definitions */ +#define IOC_PB13_FUNC_CTL_GPIO_B_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB13_FUNC_CTL_GPTMR5_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB13_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB13_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB13_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB13_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB13_FUNC_CTL_DIS0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PB14_FUNC_CTL function mux definitions */ +#define IOC_PB14_FUNC_CTL_GPIO_B_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB14_FUNC_CTL_GPTMR4_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB14_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB14_FUNC_CTL_SPI3_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB14_FUNC_CTL_DIS0_VSYNC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB14_FUNC_CTL_SYSCTL_CLK_OBS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PB15_FUNC_CTL function mux definitions */ +#define IOC_PB15_FUNC_CTL_GPIO_B_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB15_FUNC_CTL_GPTMR4_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB15_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB15_FUNC_CTL_SPI3_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB15_FUNC_CTL_SDC0_DS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB15_FUNC_CTL_SYSCTL_CLK_OBS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PB16_FUNC_CTL function mux definitions */ +#define IOC_PB16_FUNC_CTL_GPIO_B_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB16_FUNC_CTL_GPTMR7_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB16_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB16_FUNC_CTL_MCAN4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB16_FUNC_CTL_CAM0_D_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PB17_FUNC_CTL function mux definitions */ +#define IOC_PB17_FUNC_CTL_GPIO_B_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB17_FUNC_CTL_GPTMR7_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB17_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB17_FUNC_CTL_MCAN4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB17_FUNC_CTL_CAM0_D_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PB18_FUNC_CTL function mux definitions */ +#define IOC_PB18_FUNC_CTL_GPIO_B_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB18_FUNC_CTL_GPTMR7_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB18_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB18_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB18_FUNC_CTL_MCAN4_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB18_FUNC_CTL_I2S1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB18_FUNC_CTL_CAM0_D_9 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PB19_FUNC_CTL function mux definitions */ +#define IOC_PB19_FUNC_CTL_GPIO_B_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB19_FUNC_CTL_GPTMR7_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB19_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB19_FUNC_CTL_SPI0_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB19_FUNC_CTL_MCAN5_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB19_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB19_FUNC_CTL_CAM0_D_8 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PB20_FUNC_CTL function mux definitions */ +#define IOC_PB20_FUNC_CTL_GPIO_B_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB20_FUNC_CTL_GPTMR7_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB20_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB20_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB20_FUNC_CTL_MCAN5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB20_FUNC_CTL_I2S1_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB20_FUNC_CTL_CAM0_HSYNC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PB21_FUNC_CTL function mux definitions */ +#define IOC_PB21_FUNC_CTL_GPIO_B_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB21_FUNC_CTL_GPTMR7_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB21_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB21_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB21_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB21_FUNC_CTL_MCAN5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB21_FUNC_CTL_I2S1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB21_FUNC_CTL_CAM0_VSYNC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PB22_FUNC_CTL function mux definitions */ +#define IOC_PB22_FUNC_CTL_GPIO_B_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB22_FUNC_CTL_GPTMR6_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB22_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB22_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB22_FUNC_CTL_I2S1_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB22_FUNC_CTL_SDC0_DATA_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB23_FUNC_CTL function mux definitions */ +#define IOC_PB23_FUNC_CTL_GPIO_B_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB23_FUNC_CTL_GPTMR6_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB23_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB23_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB23_FUNC_CTL_I2S1_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB23_FUNC_CTL_SDC0_DATA_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB24_FUNC_CTL function mux definitions */ +#define IOC_PB24_FUNC_CTL_GPIO_B_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB24_FUNC_CTL_GPTMR6_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB24_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB24_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB24_FUNC_CTL_SPI0_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB24_FUNC_CTL_MCAN6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB24_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB24_FUNC_CTL_SDC0_DATA_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB25_FUNC_CTL function mux definitions */ +#define IOC_PB25_FUNC_CTL_GPIO_B_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB25_FUNC_CTL_GPTMR6_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB25_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB25_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB25_FUNC_CTL_SPI0_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB25_FUNC_CTL_MCAN6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB25_FUNC_CTL_I2S1_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB25_FUNC_CTL_SDC0_DATA_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB26_FUNC_CTL function mux definitions */ +#define IOC_PB26_FUNC_CTL_GPIO_B_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB26_FUNC_CTL_GPTMR6_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB26_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB26_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB26_FUNC_CTL_SPI0_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB26_FUNC_CTL_MCAN6_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB26_FUNC_CTL_I2S1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB26_FUNC_CTL_SDC0_DATA_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB27_FUNC_CTL function mux definitions */ +#define IOC_PB27_FUNC_CTL_GPIO_B_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB27_FUNC_CTL_GPTMR6_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB27_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB27_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB27_FUNC_CTL_I2S1_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB27_FUNC_CTL_SDC0_DATA_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB28_FUNC_CTL function mux definitions */ +#define IOC_PB28_FUNC_CTL_GPIO_B_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB28_FUNC_CTL_GPTMR7_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB28_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB28_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB28_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB28_FUNC_CTL_I2S1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB28_FUNC_CTL_SDC0_DATA_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB28_FUNC_CTL_CPU0_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PB29_FUNC_CTL function mux definitions */ +#define IOC_PB29_FUNC_CTL_GPIO_B_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB29_FUNC_CTL_GPTMR7_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB29_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB29_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB29_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB29_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB29_FUNC_CTL_MCAN7_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB29_FUNC_CTL_I2S1_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB29_FUNC_CTL_SDC0_DATA_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB30_FUNC_CTL function mux definitions */ +#define IOC_PB30_FUNC_CTL_GPIO_B_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB30_FUNC_CTL_GPTMR6_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB30_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB30_FUNC_CTL_SPI0_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB30_FUNC_CTL_MCAN7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB30_FUNC_CTL_SDC0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB31_FUNC_CTL function mux definitions */ +#define IOC_PB31_FUNC_CTL_GPIO_B_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB31_FUNC_CTL_GPTMR6_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB31_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB31_FUNC_CTL_SPI0_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB31_FUNC_CTL_MCAN7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB31_FUNC_CTL_SDC0_CMD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PC00_FUNC_CTL function mux definitions */ +#define IOC_PC00_FUNC_CTL_GPIO_C_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC00_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC00_FUNC_CTL_I2S2_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PC00_FUNC_CTL_SDC0_DS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC00_FUNC_CTL_XPI_SLV_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PC01_FUNC_CTL function mux definitions */ +#define IOC_PC01_FUNC_CTL_GPIO_C_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC01_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC01_FUNC_CTL_I2S2_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PC01_FUNC_CTL_SDC0_CMD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC01_FUNC_CTL_CPU0_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) +#define IOC_PC01_FUNC_CTL_XPI_SLV_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PC02_FUNC_CTL function mux definitions */ +#define IOC_PC02_FUNC_CTL_GPIO_C_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC02_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC02_FUNC_CTL_I2S2_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PC02_FUNC_CTL_SDC0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC02_FUNC_CTL_XPI_SLV_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PC03_FUNC_CTL function mux definitions */ +#define IOC_PC03_FUNC_CTL_GPIO_C_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC03_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC03_FUNC_CTL_I2S2_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PC03_FUNC_CTL_SDC0_DATA_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC03_FUNC_CTL_XPI_SLV_ADQ_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PC04_FUNC_CTL function mux definitions */ +#define IOC_PC04_FUNC_CTL_GPIO_C_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC04_FUNC_CTL_GPTMR1_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC04_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC04_FUNC_CTL_I2S2_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PC04_FUNC_CTL_SDC0_DATA_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC04_FUNC_CTL_XPI_SLV_ADQ_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PC05_FUNC_CTL function mux definitions */ +#define IOC_PC05_FUNC_CTL_GPIO_C_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC05_FUNC_CTL_GPTMR1_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC05_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC05_FUNC_CTL_I2S2_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PC05_FUNC_CTL_SDC0_DATA_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC05_FUNC_CTL_XPI_SLV_ADQ_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PC06_FUNC_CTL function mux definitions */ +#define IOC_PC06_FUNC_CTL_GPIO_C_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC06_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC06_FUNC_CTL_I2S2_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PC06_FUNC_CTL_SDC0_DATA_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC06_FUNC_CTL_XPI_SLV_ADQ_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PC07_FUNC_CTL function mux definitions */ +#define IOC_PC07_FUNC_CTL_GPIO_C_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC07_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC07_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC07_FUNC_CTL_I2S2_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PC07_FUNC_CTL_SDC0_RSTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PC08_FUNC_CTL function mux definitions */ +#define IOC_PC08_FUNC_CTL_GPIO_C_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC08_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC08_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC08_FUNC_CTL_I2S2_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PC08_FUNC_CTL_DAO_LN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PC08_FUNC_CTL_SDC0_DATA_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC08_FUNC_CTL_XPI_SLV_ERR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PC09_FUNC_CTL function mux definitions */ +#define IOC_PC09_FUNC_CTL_GPIO_C_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC09_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC09_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC09_FUNC_CTL_I2S2_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PC09_FUNC_CTL_DAO_LP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PC09_FUNC_CTL_SDC0_DATA_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC09_FUNC_CTL_XPI_SLV_RDY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PC10_FUNC_CTL function mux definitions */ +#define IOC_PC10_FUNC_CTL_GPIO_C_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC10_FUNC_CTL_GPTMR0_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC10_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC10_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC10_FUNC_CTL_I2S2_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PC10_FUNC_CTL_DAO_RN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PC10_FUNC_CTL_SDC0_DATA_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PC11_FUNC_CTL function mux definitions */ +#define IOC_PC11_FUNC_CTL_GPIO_C_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC11_FUNC_CTL_GPTMR0_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC11_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC11_FUNC_CTL_I2S2_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PC11_FUNC_CTL_DAO_RP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PC11_FUNC_CTL_SDC0_DATA_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PC12_FUNC_CTL function mux definitions */ +#define IOC_PC12_FUNC_CTL_GPIO_C_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC12_FUNC_CTL_GPTMR1_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC12_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC12_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC12_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC12_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PC12_FUNC_CTL_SDC1_DATA_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PC13_FUNC_CTL function mux definitions */ +#define IOC_PC13_FUNC_CTL_GPIO_C_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC13_FUNC_CTL_GPTMR1_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC13_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC13_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC13_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC13_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC13_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PC13_FUNC_CTL_SDC1_CMD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PC14_FUNC_CTL function mux definitions */ +#define IOC_PC14_FUNC_CTL_GPIO_C_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC14_FUNC_CTL_GPTMR0_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC14_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC14_FUNC_CTL_SPI3_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC14_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PC14_FUNC_CTL_SDC1_DATA_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PC15_FUNC_CTL function mux definitions */ +#define IOC_PC15_FUNC_CTL_GPIO_C_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC15_FUNC_CTL_GPTMR0_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC15_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC15_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC15_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PC15_FUNC_CTL_SDC1_DATA_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PC16_FUNC_CTL function mux definitions */ +#define IOC_PC16_FUNC_CTL_GPIO_C_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC16_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC16_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC16_FUNC_CTL_MCAN4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC16_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PC16_FUNC_CTL_SDC1_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PC17_FUNC_CTL function mux definitions */ +#define IOC_PC17_FUNC_CTL_GPIO_C_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC17_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC17_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC17_FUNC_CTL_MCAN4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC17_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PC17_FUNC_CTL_SDC1_DATA_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PC18_FUNC_CTL function mux definitions */ +#define IOC_PC18_FUNC_CTL_GPIO_C_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC18_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC18_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC18_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC18_FUNC_CTL_MCAN4_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC18_FUNC_CTL_I2S1_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PC18_FUNC_CTL_SDC1_DATA_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC18_FUNC_CTL_ETH0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PC19_FUNC_CTL function mux definitions */ +#define IOC_PC19_FUNC_CTL_GPIO_C_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC19_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC19_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC19_FUNC_CTL_SPI1_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC19_FUNC_CTL_MCAN5_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC19_FUNC_CTL_I2S1_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PC19_FUNC_CTL_SDC1_DATA_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC19_FUNC_CTL_ETH0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PC19_FUNC_CTL_ADC0_DBG IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PC20_FUNC_CTL function mux definitions */ +#define IOC_PC20_FUNC_CTL_GPIO_C_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC20_FUNC_CTL_GPTMR3_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC20_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC20_FUNC_CTL_SPI0_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC20_FUNC_CTL_MCAN5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC20_FUNC_CTL_I2S1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PC20_FUNC_CTL_SDC1_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC20_FUNC_CTL_ETH0_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PC21_FUNC_CTL function mux definitions */ +#define IOC_PC21_FUNC_CTL_GPIO_C_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC21_FUNC_CTL_GPTMR3_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC21_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC21_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC21_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC21_FUNC_CTL_MCAN5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC21_FUNC_CTL_I2S1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PC21_FUNC_CTL_SDC1_CMD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC21_FUNC_CTL_ETH0_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PC22_FUNC_CTL function mux definitions */ +#define IOC_PC22_FUNC_CTL_GPIO_C_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC22_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC22_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC22_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC22_FUNC_CTL_I2S1_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PC22_FUNC_CTL_SDC1_DATA_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC22_FUNC_CTL_ETH0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PC23_FUNC_CTL function mux definitions */ +#define IOC_PC23_FUNC_CTL_GPIO_C_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC23_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC23_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC23_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC23_FUNC_CTL_I2S1_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PC23_FUNC_CTL_SDC1_DATA_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC23_FUNC_CTL_ETH0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PC23_FUNC_CTL_SYSCTL_CLK_OBS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PC24_FUNC_CTL function mux definitions */ +#define IOC_PC24_FUNC_CTL_GPIO_C_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC24_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC24_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC24_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC24_FUNC_CTL_SPI1_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC24_FUNC_CTL_MCAN6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC24_FUNC_CTL_I2S1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PC24_FUNC_CTL_SDC1_CDN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC24_FUNC_CTL_ETH0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PC25_FUNC_CTL function mux definitions */ +#define IOC_PC25_FUNC_CTL_GPIO_C_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC25_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC25_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC25_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC25_FUNC_CTL_SPI1_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC25_FUNC_CTL_MCAN6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC25_FUNC_CTL_I2S1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PC25_FUNC_CTL_SDC1_VSEL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC25_FUNC_CTL_ETH0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PC26_FUNC_CTL function mux definitions */ +#define IOC_PC26_FUNC_CTL_GPIO_C_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC26_FUNC_CTL_GPTMR2_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC26_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC26_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC26_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC26_FUNC_CTL_MCAN6_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC26_FUNC_CTL_I2S1_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PC26_FUNC_CTL_SDC1_WP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC26_FUNC_CTL_ETH0_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PC27_FUNC_CTL function mux definitions */ +#define IOC_PC27_FUNC_CTL_GPIO_C_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC27_FUNC_CTL_GPTMR2_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC27_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC27_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC27_FUNC_CTL_I2S1_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PC27_FUNC_CTL_SDC1_VON IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC27_FUNC_CTL_ETH0_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PC27_FUNC_CTL_SYSCTL_CLK_OBS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PC28_FUNC_CTL function mux definitions */ +#define IOC_PC28_FUNC_CTL_GPIO_C_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC28_FUNC_CTL_GPTMR3_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC28_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC28_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC28_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC28_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PC28_FUNC_CTL_ETH0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PC29_FUNC_CTL function mux definitions */ +#define IOC_PC29_FUNC_CTL_GPIO_C_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC29_FUNC_CTL_GPTMR3_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC29_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC29_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC29_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC29_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC29_FUNC_CTL_MCAN7_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC29_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PC29_FUNC_CTL_ETH0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PC30_FUNC_CTL function mux definitions */ +#define IOC_PC30_FUNC_CTL_GPIO_C_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC30_FUNC_CTL_GPTMR2_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC30_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC30_FUNC_CTL_MCAN7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC30_FUNC_CTL_DAO_LN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PC30_FUNC_CTL_SDC1_CDN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PC31_FUNC_CTL function mux definitions */ +#define IOC_PC31_FUNC_CTL_GPIO_C_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC31_FUNC_CTL_GPTMR2_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC31_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC31_FUNC_CTL_MCAN7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC31_FUNC_CTL_DAO_LP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PC31_FUNC_CTL_SDC1_VSEL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PD00_FUNC_CTL function mux definitions */ +#define IOC_PD00_FUNC_CTL_GPIO_D_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD00_FUNC_CTL_GPTMR5_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD00_FUNC_CTL_DAO_RN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PD00_FUNC_CTL_SDC1_VON IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PD01_FUNC_CTL function mux definitions */ +#define IOC_PD01_FUNC_CTL_GPIO_D_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD01_FUNC_CTL_GPTMR5_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD01_FUNC_CTL_DAO_RP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PD01_FUNC_CTL_SDC1_WP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PD02_FUNC_CTL function mux definitions */ +#define IOC_PD02_FUNC_CTL_GPIO_D_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD02_FUNC_CTL_GPTMR5_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD02_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PD03_FUNC_CTL function mux definitions */ +#define IOC_PD03_FUNC_CTL_GPIO_D_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD03_FUNC_CTL_GPTMR5_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD03_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PD04_FUNC_CTL function mux definitions */ +#define IOC_PD04_FUNC_CTL_GPIO_D_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD04_FUNC_CTL_GPTMR5_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD04_FUNC_CTL_SPI3_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD04_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PD04_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PD05_FUNC_CTL function mux definitions */ +#define IOC_PD05_FUNC_CTL_GPIO_D_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD05_FUNC_CTL_GPTMR5_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD05_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD05_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PD05_FUNC_CTL_XPI0_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PD06_FUNC_CTL function mux definitions */ +#define IOC_PD06_FUNC_CTL_GPIO_D_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD06_FUNC_CTL_GPTMR4_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD06_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD06_FUNC_CTL_I2S2_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD06_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PD06_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD06_FUNC_CTL_ETH0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PD07_FUNC_CTL function mux definitions */ +#define IOC_PD07_FUNC_CTL_GPIO_D_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD07_FUNC_CTL_GPTMR4_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD07_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD07_FUNC_CTL_I2S2_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD07_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PD07_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD07_FUNC_CTL_ETH0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PD08_FUNC_CTL function mux definitions */ +#define IOC_PD08_FUNC_CTL_GPIO_D_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD08_FUNC_CTL_GPTMR4_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD08_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PD08_FUNC_CTL_SPI2_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD08_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PD08_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD08_FUNC_CTL_ETH0_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PD09_FUNC_CTL function mux definitions */ +#define IOC_PD09_FUNC_CTL_GPIO_D_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD09_FUNC_CTL_GPTMR4_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD09_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PD09_FUNC_CTL_SPI2_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD09_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PD09_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD09_FUNC_CTL_ETH0_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PD10_FUNC_CTL function mux definitions */ +#define IOC_PD10_FUNC_CTL_GPIO_D_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD10_FUNC_CTL_GPTMR4_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD10_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD10_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD10_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD10_FUNC_CTL_I2S2_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD10_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD10_FUNC_CTL_ETH0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PD11_FUNC_CTL function mux definitions */ +#define IOC_PD11_FUNC_CTL_GPIO_D_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD11_FUNC_CTL_GPTMR4_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD11_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD11_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD11_FUNC_CTL_I2S2_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD11_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD11_FUNC_CTL_ETH0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PD12_FUNC_CTL function mux definitions */ +#define IOC_PD12_FUNC_CTL_GPIO_D_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD12_FUNC_CTL_GPTMR5_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD12_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD12_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PD12_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD12_FUNC_CTL_I2S2_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD12_FUNC_CTL_XPI0_CB_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD12_FUNC_CTL_ETH0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PD13_FUNC_CTL function mux definitions */ +#define IOC_PD13_FUNC_CTL_GPIO_D_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD13_FUNC_CTL_GPTMR5_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD13_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD13_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD13_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PD13_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD13_FUNC_CTL_I2S2_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD13_FUNC_CTL_XPI0_CB_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD13_FUNC_CTL_ETH0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PD14_FUNC_CTL function mux definitions */ +#define IOC_PD14_FUNC_CTL_GPIO_D_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD14_FUNC_CTL_GPTMR4_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD14_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD14_FUNC_CTL_SPI2_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD14_FUNC_CTL_I2S2_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD14_FUNC_CTL_XPI0_CB_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD14_FUNC_CTL_ETH0_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PD15_FUNC_CTL function mux definitions */ +#define IOC_PD15_FUNC_CTL_GPIO_D_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD15_FUNC_CTL_GPTMR4_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD15_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD15_FUNC_CTL_SPI2_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD15_FUNC_CTL_I2S2_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD15_FUNC_CTL_XPI0_CB_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD15_FUNC_CTL_ETH0_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PD16_FUNC_CTL function mux definitions */ +#define IOC_PD16_FUNC_CTL_GPIO_D_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD16_FUNC_CTL_GPTMR7_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD16_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD16_FUNC_CTL_MCAN4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD16_FUNC_CTL_I2S2_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD16_FUNC_CTL_XPI0_CB_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD16_FUNC_CTL_ETH0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PD17_FUNC_CTL function mux definitions */ +#define IOC_PD17_FUNC_CTL_GPIO_D_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD17_FUNC_CTL_GPTMR7_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD17_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD17_FUNC_CTL_MCAN4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD17_FUNC_CTL_I2S2_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD17_FUNC_CTL_XPI0_CB_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD17_FUNC_CTL_ETH0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PD18_FUNC_CTL function mux definitions */ +#define IOC_PD18_FUNC_CTL_GPIO_D_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD18_FUNC_CTL_GPTMR7_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD18_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD18_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD18_FUNC_CTL_MCAN4_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD18_FUNC_CTL_I2S2_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD18_FUNC_CTL_XPI0_CB_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PD19_FUNC_CTL function mux definitions */ +#define IOC_PD19_FUNC_CTL_GPIO_D_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD19_FUNC_CTL_GPTMR7_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD19_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD19_FUNC_CTL_SPI1_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD19_FUNC_CTL_MCAN5_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD19_FUNC_CTL_I2S2_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD19_FUNC_CTL_XPI0_CB_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PD20_FUNC_CTL function mux definitions */ +#define IOC_PD20_FUNC_CTL_GPIO_D_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD20_FUNC_CTL_GPTMR7_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD20_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD20_FUNC_CTL_SPI0_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD20_FUNC_CTL_MCAN5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD20_FUNC_CTL_I2S3_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD20_FUNC_CTL_ETH0_EVTI_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PD21_FUNC_CTL function mux definitions */ +#define IOC_PD21_FUNC_CTL_GPIO_D_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD21_FUNC_CTL_GPTMR7_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD21_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD21_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD21_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD21_FUNC_CTL_MCAN5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD21_FUNC_CTL_I2S3_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD21_FUNC_CTL_ETH0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PD22_FUNC_CTL function mux definitions */ +#define IOC_PD22_FUNC_CTL_GPIO_D_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD22_FUNC_CTL_GPTMR6_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD22_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD22_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD22_FUNC_CTL_I2S3_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD22_FUNC_CTL_ETH0_EVTI_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PD23_FUNC_CTL function mux definitions */ +#define IOC_PD23_FUNC_CTL_GPIO_D_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD23_FUNC_CTL_GPTMR6_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD23_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD23_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD23_FUNC_CTL_I2S3_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD23_FUNC_CTL_ETH0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PD24_FUNC_CTL function mux definitions */ +#define IOC_PD24_FUNC_CTL_GPIO_D_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD24_FUNC_CTL_GPTMR6_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD24_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD24_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PD24_FUNC_CTL_SPI1_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD24_FUNC_CTL_MCAN6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD24_FUNC_CTL_I2S3_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD24_FUNC_CTL_ETH0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PD25_FUNC_CTL function mux definitions */ +#define IOC_PD25_FUNC_CTL_GPIO_D_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD25_FUNC_CTL_GPTMR6_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD25_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD25_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PD25_FUNC_CTL_SPI1_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD25_FUNC_CTL_MCAN6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD25_FUNC_CTL_I2S3_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD25_FUNC_CTL_ETH0_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PD26_FUNC_CTL function mux definitions */ +#define IOC_PD26_FUNC_CTL_GPIO_D_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD26_FUNC_CTL_GPTMR6_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD26_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD26_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD26_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD26_FUNC_CTL_MCAN6_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD26_FUNC_CTL_I2S3_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD26_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PD27_FUNC_CTL function mux definitions */ +#define IOC_PD27_FUNC_CTL_GPIO_D_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD27_FUNC_CTL_GPTMR6_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD27_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD27_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD27_FUNC_CTL_I2S3_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD27_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PD28_FUNC_CTL function mux definitions */ +#define IOC_PD28_FUNC_CTL_GPIO_D_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD28_FUNC_CTL_GPTMR7_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD28_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD28_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PD28_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD28_FUNC_CTL_I2S3_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) + +/* IOC_PD29_FUNC_CTL function mux definitions */ +#define IOC_PD29_FUNC_CTL_GPIO_D_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD29_FUNC_CTL_GPTMR7_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD29_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD29_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD29_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PD29_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD29_FUNC_CTL_MCAN7_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD29_FUNC_CTL_I2S3_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD29_FUNC_CTL_CPU0_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PD30_FUNC_CTL function mux definitions */ +#define IOC_PD30_FUNC_CTL_GPIO_D_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD30_FUNC_CTL_GPTMR6_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD30_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD30_FUNC_CTL_SPI1_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD30_FUNC_CTL_MCAN7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD30_FUNC_CTL_I2S3_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD30_FUNC_CTL_ETH0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PD30_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PD31_FUNC_CTL function mux definitions */ +#define IOC_PD31_FUNC_CTL_GPIO_D_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD31_FUNC_CTL_GPTMR6_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD31_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD31_FUNC_CTL_SPI1_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD31_FUNC_CTL_MCAN7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD31_FUNC_CTL_I2S3_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD31_FUNC_CTL_ETH0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PD31_FUNC_CTL_SOC_REF1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PE00_FUNC_CTL function mux definitions */ +#define IOC_PE00_FUNC_CTL_GPIO_E_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE00_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE00_FUNC_CTL_I2S3_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE00_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PE00_FUNC_CTL_SYSCTL_CLK_OBS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PE01_FUNC_CTL function mux definitions */ +#define IOC_PE01_FUNC_CTL_GPIO_E_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE01_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE01_FUNC_CTL_I2S3_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE01_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PE02_FUNC_CTL function mux definitions */ +#define IOC_PE02_FUNC_CTL_GPIO_E_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE02_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PE02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE02_FUNC_CTL_I2S3_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE02_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PE02_FUNC_CTL_SYSCTL_CLK_OBS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PE03_FUNC_CTL function mux definitions */ +#define IOC_PE03_FUNC_CTL_GPIO_E_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE03_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PE03_FUNC_CTL_SPI2_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE03_FUNC_CTL_I2S3_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE03_FUNC_CTL_SYSCTL_CLK_OBS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PE04_FUNC_CTL function mux definitions */ +#define IOC_PE04_FUNC_CTL_GPIO_E_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE04_FUNC_CTL_GPTMR1_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PE04_FUNC_CTL_SPI3_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE04_FUNC_CTL_I2S3_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE04_FUNC_CTL_SYSCTL_CLK_OBS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PE05_FUNC_CTL function mux definitions */ +#define IOC_PE05_FUNC_CTL_GPIO_E_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE05_FUNC_CTL_GPTMR1_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PE05_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE05_FUNC_CTL_DAO_RP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PE06_FUNC_CTL function mux definitions */ +#define IOC_PE06_FUNC_CTL_GPIO_E_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE06_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE06_FUNC_CTL_DAO_LN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PE07_FUNC_CTL function mux definitions */ +#define IOC_PE07_FUNC_CTL_GPIO_E_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE07_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE07_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE07_FUNC_CTL_DAO_LP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PE08_FUNC_CTL function mux definitions */ +#define IOC_PE08_FUNC_CTL_GPIO_E_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE08_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE08_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PE08_FUNC_CTL_SPI2_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE08_FUNC_CTL_I2S3_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE08_FUNC_CTL_ETH0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PE09_FUNC_CTL function mux definitions */ +#define IOC_PE09_FUNC_CTL_GPIO_E_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE09_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE09_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PE09_FUNC_CTL_SPI2_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE09_FUNC_CTL_I2S3_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE09_FUNC_CTL_ETH0_EVTI_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PE10_FUNC_CTL function mux definitions */ +#define IOC_PE10_FUNC_CTL_GPIO_E_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE10_FUNC_CTL_GPTMR0_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE10_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE10_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PE10_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE10_FUNC_CTL_I2S3_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE10_FUNC_CTL_ETH0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PE11_FUNC_CTL function mux definitions */ +#define IOC_PE11_FUNC_CTL_GPIO_E_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE11_FUNC_CTL_GPTMR0_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE11_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PE11_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE11_FUNC_CTL_DAO_RN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PE11_FUNC_CTL_ETH0_EVTI_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PE12_FUNC_CTL function mux definitions */ +#define IOC_PE12_FUNC_CTL_GPIO_E_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE12_FUNC_CTL_GPTMR1_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE12_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PE12_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PE12_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE12_FUNC_CTL_I2S3_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE12_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PE12_FUNC_CTL_ETH0_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PE13_FUNC_CTL function mux definitions */ +#define IOC_PE13_FUNC_CTL_GPIO_E_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE13_FUNC_CTL_GPTMR1_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE13_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE13_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PE13_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PE13_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE13_FUNC_CTL_I2S3_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE13_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PE13_FUNC_CTL_ETH0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PE14_FUNC_CTL function mux definitions */ +#define IOC_PE14_FUNC_CTL_GPIO_E_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE14_FUNC_CTL_GPTMR0_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE14_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE14_FUNC_CTL_SPI2_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE14_FUNC_CTL_I2S3_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE14_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PE14_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PE14_FUNC_CTL_ETH0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PE15_FUNC_CTL function mux definitions */ +#define IOC_PE15_FUNC_CTL_GPIO_E_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE15_FUNC_CTL_GPTMR0_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE15_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE15_FUNC_CTL_SPI2_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE15_FUNC_CTL_I2S3_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE15_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PE15_FUNC_CTL_ETH0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PE16_FUNC_CTL function mux definitions */ +#define IOC_PE16_FUNC_CTL_GPIO_E_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE16_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE16_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE16_FUNC_CTL_MCAN4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE16_FUNC_CTL_I2S0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE16_FUNC_CTL_ETH0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PE17_FUNC_CTL function mux definitions */ +#define IOC_PE17_FUNC_CTL_GPIO_E_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE17_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE17_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE17_FUNC_CTL_MCAN4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE17_FUNC_CTL_I2S0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE17_FUNC_CTL_ETH0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PE18_FUNC_CTL function mux definitions */ +#define IOC_PE18_FUNC_CTL_GPIO_E_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE18_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE18_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE18_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PE18_FUNC_CTL_MCAN4_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE18_FUNC_CTL_I2S0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE18_FUNC_CTL_ETH0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PE18_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PE19_FUNC_CTL function mux definitions */ +#define IOC_PE19_FUNC_CTL_GPIO_E_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE19_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE19_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PE19_FUNC_CTL_SPI1_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE19_FUNC_CTL_MCAN5_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE19_FUNC_CTL_I2S0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE19_FUNC_CTL_ETH0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PE20_FUNC_CTL function mux definitions */ +#define IOC_PE20_FUNC_CTL_GPIO_E_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE20_FUNC_CTL_GPTMR3_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE20_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PE20_FUNC_CTL_SPI0_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE20_FUNC_CTL_MCAN5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE20_FUNC_CTL_I2S0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE20_FUNC_CTL_ETH0_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PE20_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PE21_FUNC_CTL function mux definitions */ +#define IOC_PE21_FUNC_CTL_GPIO_E_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE21_FUNC_CTL_GPTMR3_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE21_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE21_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PE21_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE21_FUNC_CTL_MCAN5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE21_FUNC_CTL_I2S0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE21_FUNC_CTL_ETH0_EVTI_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PE22_FUNC_CTL function mux definitions */ +#define IOC_PE22_FUNC_CTL_GPIO_E_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE22_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE22_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE22_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE22_FUNC_CTL_I2S0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE22_FUNC_CTL_ETH0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PE23_FUNC_CTL function mux definitions */ +#define IOC_PE23_FUNC_CTL_GPIO_E_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE23_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE23_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE23_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE23_FUNC_CTL_I2S0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE23_FUNC_CTL_ETH0_EVTI_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PE23_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PE24_FUNC_CTL function mux definitions */ +#define IOC_PE24_FUNC_CTL_GPIO_E_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE24_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE24_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE24_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PE24_FUNC_CTL_SPI1_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE24_FUNC_CTL_MCAN6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE24_FUNC_CTL_I2S0_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE24_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PE25_FUNC_CTL function mux definitions */ +#define IOC_PE25_FUNC_CTL_GPIO_E_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE25_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE25_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE25_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PE25_FUNC_CTL_SPI1_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE25_FUNC_CTL_MCAN6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE25_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE25_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PE26_FUNC_CTL function mux definitions */ +#define IOC_PE26_FUNC_CTL_GPIO_E_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE26_FUNC_CTL_GPTMR2_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE26_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE26_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PE26_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE26_FUNC_CTL_MCAN6_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE26_FUNC_CTL_I2S0_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) + +/* IOC_PE27_FUNC_CTL function mux definitions */ +#define IOC_PE27_FUNC_CTL_GPIO_E_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE27_FUNC_CTL_GPTMR2_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE27_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PE27_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE27_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE27_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PE28_FUNC_CTL function mux definitions */ +#define IOC_PE28_FUNC_CTL_GPIO_E_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE28_FUNC_CTL_GPTMR3_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE28_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PE28_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PE28_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE28_FUNC_CTL_DAO_RP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PE28_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PE29_FUNC_CTL function mux definitions */ +#define IOC_PE29_FUNC_CTL_GPIO_E_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE29_FUNC_CTL_GPTMR3_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE29_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE29_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PE29_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PE29_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE29_FUNC_CTL_MCAN7_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE29_FUNC_CTL_DAO_LN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PE30_FUNC_CTL function mux definitions */ +#define IOC_PE30_FUNC_CTL_GPIO_E_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE30_FUNC_CTL_GPTMR2_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE30_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE30_FUNC_CTL_SPI1_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE30_FUNC_CTL_MCAN7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE30_FUNC_CTL_DAO_RN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PE30_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PE31_FUNC_CTL function mux definitions */ +#define IOC_PE31_FUNC_CTL_GPIO_E_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE31_FUNC_CTL_GPTMR2_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE31_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE31_FUNC_CTL_SPI1_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE31_FUNC_CTL_MCAN7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE31_FUNC_CTL_DAO_LP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PF00_FUNC_CTL function mux definitions */ +#define IOC_PF00_FUNC_CTL_GPIO_F_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PF00_FUNC_CTL_GPTMR5_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PF00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PF00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PF00_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PF00_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PF01_FUNC_CTL function mux definitions */ +#define IOC_PF01_FUNC_CTL_GPIO_F_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PF01_FUNC_CTL_GPTMR5_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PF01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PF01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PF01_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PF01_FUNC_CTL_CPU0_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PF02_FUNC_CTL function mux definitions */ +#define IOC_PF02_FUNC_CTL_GPIO_F_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PF02_FUNC_CTL_GPTMR5_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PF02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PF02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PF02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PF02_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PF02_FUNC_CTL_ETH0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PF03_FUNC_CTL function mux definitions */ +#define IOC_PF03_FUNC_CTL_GPIO_F_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PF03_FUNC_CTL_GPTMR5_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PF03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PF03_FUNC_CTL_SPI3_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PF03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PF03_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PF03_FUNC_CTL_ETH0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PF03_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PF04_FUNC_CTL function mux definitions */ +#define IOC_PF04_FUNC_CTL_GPIO_F_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PF04_FUNC_CTL_GPTMR5_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PF04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PF04_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PF04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PF04_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PF04_FUNC_CTL_ETH0_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PF04_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PF05_FUNC_CTL function mux definitions */ +#define IOC_PF05_FUNC_CTL_GPIO_F_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PF05_FUNC_CTL_GPTMR5_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PF05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PF05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PF05_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PF05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PF05_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PF05_FUNC_CTL_ETH0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PF06_FUNC_CTL function mux definitions */ +#define IOC_PF06_FUNC_CTL_GPIO_F_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PF06_FUNC_CTL_GPTMR4_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PF06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PF06_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PF06_FUNC_CTL_ETH0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PF07_FUNC_CTL function mux definitions */ +#define IOC_PF07_FUNC_CTL_GPIO_F_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PF07_FUNC_CTL_GPTMR4_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PF07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PF07_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PF07_FUNC_CTL_ETH0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PF08_FUNC_CTL function mux definitions */ +#define IOC_PF08_FUNC_CTL_GPIO_F_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PF08_FUNC_CTL_GPTMR4_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PF08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PF08_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PF08_FUNC_CTL_SPI3_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PF08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PF08_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PF08_FUNC_CTL_ETH0_EVTI_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PF09_FUNC_CTL function mux definitions */ +#define IOC_PF09_FUNC_CTL_GPIO_F_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PF09_FUNC_CTL_GPTMR4_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PF09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PF09_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PF09_FUNC_CTL_SPI3_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PF09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PF09_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PF09_FUNC_CTL_ETH0_EVTI_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PF10_FUNC_CTL function mux definitions */ +#define IOC_PF10_FUNC_CTL_GPIO_F_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PF10_FUNC_CTL_GPTMR4_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PF10_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PF10_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PF10_FUNC_CTL_SPI3_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PF10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PF11_FUNC_CTL function mux definitions */ +#define IOC_PF11_FUNC_CTL_GPIO_F_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PF11_FUNC_CTL_GPTMR4_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PF11_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PF11_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) + +/* IOC_PF12_FUNC_CTL function mux definitions */ +#define IOC_PF12_FUNC_CTL_GPIO_F_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PF12_FUNC_CTL_GPTMR5_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PF12_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PF12_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PF12_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) + +/* IOC_PF13_FUNC_CTL function mux definitions */ +#define IOC_PF13_FUNC_CTL_GPIO_F_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PF13_FUNC_CTL_GPTMR5_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PF13_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PF13_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PF13_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PF13_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PF13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PF14_FUNC_CTL function mux definitions */ +#define IOC_PF14_FUNC_CTL_GPIO_F_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PF14_FUNC_CTL_GPTMR4_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PF14_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PF14_FUNC_CTL_SPI3_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PF14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PF15_FUNC_CTL function mux definitions */ +#define IOC_PF15_FUNC_CTL_GPIO_F_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PF15_FUNC_CTL_GPTMR4_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PF15_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PF15_FUNC_CTL_SPI3_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PF15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PX00_FUNC_CTL function mux definitions */ +#define IOC_PX00_FUNC_CTL_GPIO_X_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX00_FUNC_CTL_GPTMR7_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PX00_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PX00_FUNC_CTL_MCAN4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PX00_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX01_FUNC_CTL function mux definitions */ +#define IOC_PX01_FUNC_CTL_GPIO_X_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX01_FUNC_CTL_GPTMR7_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PX01_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PX01_FUNC_CTL_MCAN4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PX01_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX02_FUNC_CTL function mux definitions */ +#define IOC_PX02_FUNC_CTL_GPIO_X_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX02_FUNC_CTL_GPTMR7_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PX02_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PX02_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PX02_FUNC_CTL_MCAN4_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PX02_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PX02_FUNC_CTL_SDC1_DATA_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PX03_FUNC_CTL function mux definitions */ +#define IOC_PX03_FUNC_CTL_GPIO_X_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX03_FUNC_CTL_GPTMR7_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PX03_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PX03_FUNC_CTL_SPI0_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PX03_FUNC_CTL_MCAN5_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PX03_FUNC_CTL_XPI0_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PX03_FUNC_CTL_SDC1_DATA_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PX04_FUNC_CTL function mux definitions */ +#define IOC_PX04_FUNC_CTL_GPIO_X_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX04_FUNC_CTL_GPTMR7_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PX04_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PX04_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PX04_FUNC_CTL_MCAN5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PX04_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PX04_FUNC_CTL_SDC1_DATA_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PX05_FUNC_CTL function mux definitions */ +#define IOC_PX05_FUNC_CTL_GPIO_X_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX05_FUNC_CTL_GPTMR7_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PX05_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PX05_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PX05_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PX05_FUNC_CTL_MCAN5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PX05_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PX05_FUNC_CTL_SDC1_DATA_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PX06_FUNC_CTL function mux definitions */ +#define IOC_PX06_FUNC_CTL_GPIO_X_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX06_FUNC_CTL_GPTMR6_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PX06_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PX06_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PX06_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX07_FUNC_CTL function mux definitions */ +#define IOC_PX07_FUNC_CTL_GPIO_X_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX07_FUNC_CTL_GPTMR6_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PX07_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PX07_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PX07_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX08_FUNC_CTL function mux definitions */ +#define IOC_PX08_FUNC_CTL_GPIO_X_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX08_FUNC_CTL_GPTMR6_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PX08_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PX08_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PX08_FUNC_CTL_SPI0_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PX08_FUNC_CTL_MCAN6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PX08_FUNC_CTL_XPI0_CB_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PX08_FUNC_CTL_SDC1_DATA_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PX09_FUNC_CTL function mux definitions */ +#define IOC_PX09_FUNC_CTL_GPIO_X_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX09_FUNC_CTL_GPTMR6_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PX09_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PX09_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PX09_FUNC_CTL_SPI0_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PX09_FUNC_CTL_MCAN6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PX09_FUNC_CTL_XPI0_CB_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PX09_FUNC_CTL_SDC1_DATA_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PX10_FUNC_CTL function mux definitions */ +#define IOC_PX10_FUNC_CTL_GPIO_X_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX10_FUNC_CTL_GPTMR6_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PX10_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PX10_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PX10_FUNC_CTL_SPI0_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PX10_FUNC_CTL_MCAN6_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PX10_FUNC_CTL_XPI0_CB_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PX10_FUNC_CTL_SDC1_CMD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PX11_FUNC_CTL function mux definitions */ +#define IOC_PX11_FUNC_CTL_GPIO_X_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX11_FUNC_CTL_GPTMR6_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PX11_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PX11_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PX11_FUNC_CTL_XPI0_CB_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PX11_FUNC_CTL_SDC1_DS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PX12_FUNC_CTL function mux definitions */ +#define IOC_PX12_FUNC_CTL_GPIO_X_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX12_FUNC_CTL_GPTMR7_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PX12_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PX12_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PX12_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PX12_FUNC_CTL_XPI0_CB_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PX12_FUNC_CTL_SDC1_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PX13_FUNC_CTL function mux definitions */ +#define IOC_PX13_FUNC_CTL_GPIO_X_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX13_FUNC_CTL_GPTMR7_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PX13_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PX13_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PX13_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PX13_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PX13_FUNC_CTL_MCAN7_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PX13_FUNC_CTL_XPI0_CB_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PX13_FUNC_CTL_SDC1_DATA_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PX14_FUNC_CTL function mux definitions */ +#define IOC_PX14_FUNC_CTL_GPIO_X_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX14_FUNC_CTL_GPTMR6_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PX14_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PX14_FUNC_CTL_SPI0_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PX14_FUNC_CTL_MCAN7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PX14_FUNC_CTL_XPI0_CB_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PX14_FUNC_CTL_SDC1_DATA_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PX15_FUNC_CTL function mux definitions */ +#define IOC_PX15_FUNC_CTL_GPIO_X_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX15_FUNC_CTL_GPTMR6_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PX15_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PX15_FUNC_CTL_SPI0_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PX15_FUNC_CTL_MCAN7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PX15_FUNC_CTL_XPI0_CB_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PX15_FUNC_CTL_SDC1_RSTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PY00_FUNC_CTL function mux definitions */ +#define IOC_PY00_FUNC_CTL_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY00_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PY01_FUNC_CTL function mux definitions */ +#define IOC_PY01_FUNC_CTL_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY01_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PY02_FUNC_CTL function mux definitions */ +#define IOC_PY02_FUNC_CTL_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY02_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY02_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PY03_FUNC_CTL function mux definitions */ +#define IOC_PY03_FUNC_CTL_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY03_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY03_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PY04_FUNC_CTL function mux definitions */ +#define IOC_PY04_FUNC_CTL_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY04_FUNC_CTL_GPTMR1_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY04_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY04_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PY05_FUNC_CTL function mux definitions */ +#define IOC_PY05_FUNC_CTL_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY05_FUNC_CTL_GPTMR1_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY05_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY05_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PY06_FUNC_CTL function mux definitions */ +#define IOC_PY06_FUNC_CTL_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY06_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY06_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PY07_FUNC_CTL function mux definitions */ +#define IOC_PY07_FUNC_CTL_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY07_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY07_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY07_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PY08_FUNC_CTL function mux definitions */ +#define IOC_PY08_FUNC_CTL_GPIO_Y_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY08_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY08_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PY08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PY09_FUNC_CTL function mux definitions */ +#define IOC_PY09_FUNC_CTL_GPIO_Y_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY09_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY09_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PY09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PY10_FUNC_CTL function mux definitions */ +#define IOC_PY10_FUNC_CTL_GPIO_Y_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY10_FUNC_CTL_GPTMR0_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY10_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY10_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY10_FUNC_CTL_SPI3_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PY11_FUNC_CTL function mux definitions */ +#define IOC_PY11_FUNC_CTL_GPIO_Y_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY11_FUNC_CTL_GPTMR0_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY11_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY11_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) + +/* IOC_PY12_FUNC_CTL function mux definitions */ +#define IOC_PY12_FUNC_CTL_GPIO_Y_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY12_FUNC_CTL_GPTMR1_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY12_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY12_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PY12_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) + +/* IOC_PY13_FUNC_CTL function mux definitions */ +#define IOC_PY13_FUNC_CTL_GPIO_Y_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY13_FUNC_CTL_GPTMR1_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY13_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY13_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY13_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PY13_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PY14_FUNC_CTL function mux definitions */ +#define IOC_PY14_FUNC_CTL_GPIO_Y_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY14_FUNC_CTL_GPTMR0_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY14_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PY15_FUNC_CTL function mux definitions */ +#define IOC_PY15_FUNC_CTL_GPIO_Y_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY15_FUNC_CTL_GPTMR0_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY15_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PZ00_FUNC_CTL function mux definitions */ +#define IOC_PZ00_FUNC_CTL_GPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ00_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ00_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ00_FUNC_CTL_MCAN4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PZ01_FUNC_CTL function mux definitions */ +#define IOC_PZ01_FUNC_CTL_GPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ01_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ01_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ01_FUNC_CTL_MCAN4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PZ02_FUNC_CTL function mux definitions */ +#define IOC_PZ02_FUNC_CTL_GPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ02_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ02_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ02_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PZ02_FUNC_CTL_MCAN4_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PZ02_FUNC_CTL_DAO_RP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PZ03_FUNC_CTL function mux definitions */ +#define IOC_PZ03_FUNC_CTL_GPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ03_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ03_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PZ03_FUNC_CTL_MCAN5_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PZ03_FUNC_CTL_DAO_RN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PZ04_FUNC_CTL function mux definitions */ +#define IOC_PZ04_FUNC_CTL_GPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ04_FUNC_CTL_GPTMR3_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ04_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PZ04_FUNC_CTL_SPI0_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PZ04_FUNC_CTL_MCAN5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PZ04_FUNC_CTL_DAO_LP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PZ05_FUNC_CTL function mux definitions */ +#define IOC_PZ05_FUNC_CTL_GPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ05_FUNC_CTL_GPTMR3_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ05_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ05_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PZ05_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PZ05_FUNC_CTL_MCAN5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PZ05_FUNC_CTL_DAO_LN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PZ06_FUNC_CTL function mux definitions */ +#define IOC_PZ06_FUNC_CTL_GPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ06_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ06_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ06_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) + +/* IOC_PZ07_FUNC_CTL function mux definitions */ +#define IOC_PZ07_FUNC_CTL_GPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ07_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ07_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ07_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) + +/* IOC_PZ08_FUNC_CTL function mux definitions */ +#define IOC_PZ08_FUNC_CTL_GPIO_Z_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ08_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ08_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ08_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PZ08_FUNC_CTL_MCAN6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PZ09_FUNC_CTL function mux definitions */ +#define IOC_PZ09_FUNC_CTL_GPIO_Z_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ09_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ09_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ09_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PZ09_FUNC_CTL_MCAN6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PZ10_FUNC_CTL function mux definitions */ +#define IOC_PZ10_FUNC_CTL_GPIO_Z_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ10_FUNC_CTL_GPTMR2_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ10_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ10_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PZ10_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PZ10_FUNC_CTL_MCAN6_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PZ11_FUNC_CTL function mux definitions */ +#define IOC_PZ11_FUNC_CTL_GPIO_Z_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ11_FUNC_CTL_GPTMR2_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ11_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PZ11_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) + +/* IOC_PZ12_FUNC_CTL function mux definitions */ +#define IOC_PZ12_FUNC_CTL_GPIO_Z_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ12_FUNC_CTL_GPTMR3_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ12_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PZ12_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PZ12_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) + +/* IOC_PZ13_FUNC_CTL function mux definitions */ +#define IOC_PZ13_FUNC_CTL_GPIO_Z_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ13_FUNC_CTL_GPTMR3_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ13_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ13_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PZ13_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PZ13_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PZ13_FUNC_CTL_MCAN7_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PZ14_FUNC_CTL function mux definitions */ +#define IOC_PZ14_FUNC_CTL_GPIO_Z_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ14_FUNC_CTL_GPTMR2_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ14_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ14_FUNC_CTL_MCAN7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PZ15_FUNC_CTL function mux definitions */ +#define IOC_PZ15_FUNC_CTL_GPIO_Z_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ15_FUNC_CTL_GPTMR2_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ15_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ15_FUNC_CTL_MCAN7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + + +#endif /* HPM_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_l1c_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_l1c_drv.c new file mode 100644 index 00000000000..c55600dcdcc --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_l1c_drv.c @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2021-2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_l1c_drv.h" +#include + + +#define ASSERT_ADDR_SIZE(addr, size) do { \ + assert(address % HPM_L1C_CACHELINE_SIZE == 0); \ + assert(size % HPM_L1C_CACHELINE_SIZE == 0); \ + } while (0) + +static void l1c_op(uint8_t opcode, uint32_t address, uint32_t size) +{ + register uint32_t i; + register uint32_t next_address; + register uint32_t tmp; + register uint32_t csr; + + csr = read_clear_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); + +#define CCTL_VERSION (3U << 18) + + if ((read_csr(CSR_MMSC_CFG) & CCTL_VERSION)) { + l1c_cctl_address(address); + next_address = address; + while ((next_address < (address + size)) && (next_address >= address)) { + l1c_cctl_cmd(opcode); + next_address = l1c_cctl_get_address(); + } + } else { + for (i = 0, tmp = 0; tmp < size; i++) { + l1c_cctl_address_cmd(opcode, address + i * HPM_L1C_CACHELINE_SIZE); + tmp += HPM_L1C_CACHELINE_SIZE; + } + } + + write_csr(CSR_MSTATUS, csr); +} + +void l1c_dc_enable(void) +{ + if (!l1c_dc_is_enabled()) { + clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_DC_WAROUND_MASK); + set_csr(CSR_MCACHE_CTL, +#ifdef L1C_DC_WAROUND_VALUE + HPM_MCACHE_CTL_DC_WAROUND(L1C_DC_WAROUND_VALUE) | +#endif + HPM_MCACHE_CTL_DPREF_EN_MASK + | HPM_MCACHE_CTL_DC_EN_MASK); + } +} + +void l1c_dc_disable(void) +{ + if (l1c_dc_is_enabled()) { + clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_DC_EN_MASK); + } +} + +void l1c_ic_enable(void) +{ + if (!l1c_ic_is_enabled()) { + set_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_IPREF_EN_MASK + | HPM_MCACHE_CTL_CCTL_SUEN_MASK + | HPM_MCACHE_CTL_IC_EN_MASK); + } +} + +void l1c_ic_disable(void) +{ + if (l1c_ic_is_enabled()) { + clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_IC_EN_MASK); + } +} + +void l1c_fence_i(void) +{ + __asm("fence.i"); +} + +void l1c_dc_invalidate_all(void) +{ + l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_INVAL_ALL); +} + +void l1c_dc_writeback_all(void) +{ + l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_WB_ALL); +} + +void l1c_dc_flush_all(void) +{ + l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_WBINVAL_ALL); +} + +void l1c_dc_fill_lock(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_LOCK, address, size); +} + +void l1c_dc_invalidate(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_INVAL, address, size); +} + +void l1c_dc_writeback(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_WB, address, size); +} + +void l1c_dc_flush(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_WBINVAL, address, size); +} + +void l1c_ic_invalidate(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1I_VA_INVAL, address, size); +} + +void l1c_ic_fill_lock(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1I_VA_LOCK, address, size); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_l1c_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_l1c_drv.h new file mode 100644 index 00000000000..1f1a21639a2 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_l1c_drv.h @@ -0,0 +1,485 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_L1_CACHE_H +#define _HPM_L1_CACHE_H +#include "hpm_common.h" +#include "hpm_csr_drv.h" +#include "hpm_soc.h" + +/** + * + * @brief L1CACHE driver APIs + * @defgroup l1cache_interface L1CACHE driver APIs + * @{ + */ + +/* cache size is 32KB */ +#define HPM_L1C_CACHE_SIZE (uint32_t)(32 * SIZE_1KB) +#define HPM_L1C_ICACHE_SIZE (HPM_L1C_CACHE_SIZE) +#define HPM_L1C_DCACHE_SIZE (HPM_L1C_CACHE_SIZE) +/* cache line size is 64B */ +#define HPM_L1C_CACHELINE_SIZE (64) +/* cache way is 128 */ +#define HPM_L1C_CACHELINES_PER_WAY (128) + +/* mcache_ctl register */ +/* + * Controls if the instruction cache is enabled or not. + * + * 0 I-Cache is disabled + * 1 I-Cache is enabled + */ +#define HPM_MCACHE_CTL_IC_EN_SHIFT (0UL) +#define HPM_MCACHE_CTL_IC_EN_MASK (1UL << HPM_MCACHE_CTL_IC_EN_SHIFT) +#define HPM_MCACHE_CTL_IC_EN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IC_EN_SHIFT) & HPM_MCACHE_CTL_IC_EN_MASK) + +/* + * Controls if the data cache is enabled or not. + * + * 0 D-Cache is disabled + * 1 D-Cache is enabled + */ +#define HPM_MCACHE_CTL_DC_EN_SHIFT (1UL) +#define HPM_MCACHE_CTL_DC_EN_MASK (1UL << HPM_MCACHE_CTL_DC_EN_SHIFT) +#define HPM_MCACHE_CTL_DC_EN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_EN_SHIFT) & HPM_MCACHE_CTL_DC_EN_MASK) + +/* + * Parity/ECC error checking enable control for the instruction cache. + * + * 0 Disable parity/ECC + * 1 Reserved + * 2 Generate exceptions only on uncorrectable parity/ECC errors + * 3 Generate exceptions on any type of parity/ECC errors + */ +#define HPM_MCACHE_CTL_IC_ECCEN_SHIFT (0x2UL) +#define HPM_MCACHE_CTL_IC_ECCEN_MASK (0x3UL << HPM_MCACHE_CTL_IC_ECCEN_SHIFT) +#define HPM_MCACHE_CTL_IC_ECCEN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IC_ECCEN_SHIFT) & HPM_MCACHE_CTL_IC_ECCEN_MASK) + +/* + * + * Parity/ECC error checking enable control for the data cache. + * + * 0 Disable parity/ECC + * 1 Reserved + * 2 Generate exceptions only on uncorrectable parity/ECC errors + * 3 Generate exceptions on any type of parity/ECC errors + */ +#define HPM_MCACHE_CTL_DC_ECCEN_SHIFT (0x4UL) +#define HPM_MCACHE_CTL_DC_ECCEN_MASK (0x3UL << HPM_MCACHE_CTL_DC_ECCEN_SHIFT) +#define HPM_MCACHE_CTL_DC_ECCEN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_ECCEN_SHIFT) & HPM_MCACHE_CTL_DC_ECCEN_MASK) + +/* + * + * Controls diagnostic accesses of ECC codes of the instruction cache RAMs. + * It is set to enable CCTL operations to access the ECC codes. This bit + * can be set for injecting ECC errors to test the ECC handler. + * + * 0 Disable diagnostic accesses of ECC codes + * 1 Enable diagnostic accesses of ECC codes + */ +#define HPM_MCACHE_CTL_IC_RWECC_SHIFT (0x6UL) +#define HPM_MCACHE_CTL_IC_RWECC_MASK (0x1UL << HPM_MCACHE_CTL_IC_RWECC_SHIFT) +#define HPM_MCACHE_CTL_IC_RWECC(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IC_RWECC_SHIFT) & HPM_MCACHE_CTL_IC_RWECC_MASK) + +/* + * + * Controls diagnostic accesses of ECC codes of the data cache RAMs. It is + * set to enable CCTL operations to access the ECC codes. This bit can be + * set for injecting + * + * ECC errors to test the ECC handler. + * 0 Disable diagnostic accesses of ECC codes + * 1 Enable diagnostic accesses of ECC codes + */ +#define HPM_MCACHE_CTL_DC_RWECC_SHIFT (0x7UL) +#define HPM_MCACHE_CTL_DC_RWECC_MASK (0x1UL << HPM_MCACHE_CTL_DC_RWECC_SHIFT) +#define HPM_MCACHE_CTL_DC_RWECC(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_RWECC_SHIFT) & HPM_MCACHE_CTL_DC_RWECC_MASK) + +/* + * Enable bit for Superuser-mode and User-mode software to access + * ucctlbeginaddr and ucctlcommand CSRs. + * + * 0 Disable ucctlbeginaddr and ucctlcommand accesses in S/U mode + * 1 Enable ucctlbeginaddr and ucctlcommand accesses in S/U mode + */ +#define HPM_MCACHE_CTL_CCTL_SUEN_SHIFT (0x8UL) +#define HPM_MCACHE_CTL_CCTL_SUEN_MASK (0x1UL << HPM_MCACHE_CTL_CCTL_SUEN_SHIFT) +#define HPM_MCACHE_CTL_CCTL_SUEN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_CCTL_SUEN_SHIFT) & HPM_MCACHE_CTL_CCTL_SUEN_MASK) + +/* + * This bit controls hardware prefetch for instruction fetches to cacheable + * memory regions when I-Cache size is not 0. + * + * 0 Disable hardware prefetch on instruction fetches + * 1 Enable hardware prefetch on instruction fetches + */ +#define HPM_MCACHE_CTL_IPREF_EN_SHIFT (0x9UL) +#define HPM_MCACHE_CTL_IPREF_EN_MASK (0x1UL << HPM_MCACHE_CTL_IPREF_EN_SHIFT) +#define HPM_MCACHE_CTL_IPREF_EN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IPREF_EN_SHIFT) & HPM_MCACHE_CTL_IPREF_EN_MASK) + +/* + * This bit controls hardware prefetch for load/store accesses to cacheable + * memory regions when D-Cache size is not 0. + * + * 0 Disable hardware prefetch on load/store memory accesses. + * 1 Enable hardware prefetch on load/store memory accesses. + */ +#define HPM_MCACHE_CTL_DPREF_EN_SHIFT (0x10UL) +#define HPM_MCACHE_CTL_DPREF_EN_MASK (0x1UL << HPM_MCACHE_CTL_DPREF_EN_SHIFT) +#define HPM_MCACHE_CTL_DPREF_EN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DPREF_EN_SHIFT) & HPM_MCACHE_CTL_DPREF_EN_MASK) + +/* + * I-Cache miss allocation filling policy Value Meaning + * + * 0 Cache line data is returned critical (double) word first + * 1 Cache line data is returned the lowest address (double) word first + */ +#define HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT (0x11UL) +#define HPM_MCACHE_CTL_IC_FIRST_WORD_MASK (0x1UL << HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT) +#define HPM_MCACHE_CTL_IC_FIRST_WORD(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT) & HPM_MCACHE_CTL_IC_FIRST_WORD_MASK) + +/* + * D-Cache miss allocation filling policy + * + * 0 Cache line data is returned critical (double) word first + * 1 Cache line data is returned the lowest address (double) word first + */ +#define HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT (0x12UL) +#define HPM_MCACHE_CTL_DC_FIRST_WORD_MASK (0x1UL << HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT) +#define HPM_MCACHE_CTL_DC_FIRST_WORD(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT) & HPM_MCACHE_CTL_DC_FIRST_WORD_MASK) + +/* + * D-Cache Write-Around threshold + * + * 0 Disables streaming. All cacheable write misses allocate a cache line + * according to PMA settings. + * 1 Override PMA setting and do not allocate D-Cache entries after + * consecutive stores to 4 cache lines. + * 2 Override PMA setting and do not allocate D-Cache entries after + * consecutive stores to 64 cache lines. + * 3 Override PMA setting and do not allocate D-Cache entries after + * consecutive stores to 128 cache lines. + */ +#define HPM_MCACHE_CTL_DC_WAROUND_SHIFT (0x13UL) +#define HPM_MCACHE_CTL_DC_WAROUND_MASK (0x3UL << HPM_MCACHE_CTL_DC_WAROUND_SHIFT) +#define HPM_MCACHE_CTL_DC_WAROUND(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_WAROUND_SHIFT) & HPM_MCACHE_CTL_DC_WAROUND_MASK) + +/* CCTL command list */ +#define HPM_L1C_CCTL_CMD_L1D_VA_INVAL (0UL) +#define HPM_L1C_CCTL_CMD_L1D_VA_WB (1UL) +#define HPM_L1C_CCTL_CMD_L1D_VA_WBINVAL (2UL) +#define HPM_L1C_CCTL_CMD_L1D_VA_LOCK (3UL) +#define HPM_L1C_CCTL_CMD_L1D_VA_UNLOCK (4UL) +#define HPM_L1C_CCTL_CMD_L1D_WBINVAL_ALL (6UL) +#define HPM_L1C_CCTL_CMD_L1D_WB_ALL (7UL) + +#define HPM_L1C_CCTL_CMD_L1I_VA_INVAL (8UL) +#define HPM_L1C_CCTL_CMD_L1I_VA_LOCK (11UL) +#define HPM_L1C_CCTL_CMD_L1I_VA_UNLOCK (12UL) + +#define HPM_L1C_CCTL_CMD_L1D_IX_INVAL (16UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_WB (17UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_WBINVAL (18UL) + +#define HPM_L1C_CCTL_CMD_L1D_IX_RTAG (19UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_RDATA (20UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_WTAG (21UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_WDATA (22UL) + +#define HPM_L1C_CCTL_CMD_L1D_INVAL_ALL (23UL) + +#define HPM_L1C_CCTL_CMD_L1I_IX_INVAL (24UL) +#define HPM_L1C_CCTL_CMD_L1I_IX_RTAG (27UL) +#define HPM_L1C_CCTL_CMD_L1I_IX_RDATA (28UL) +#define HPM_L1C_CCTL_CMD_L1I_IX_WTAG (29UL) +#define HPM_L1C_CCTL_CMD_L1I_IX_WDATA (30UL) + +#define HPM_L1C_CCTL_CMD_SUCCESS (1UL) +#define HPM_L1C_CCTL_CMD_FAIL (0UL) + +#ifdef __cplusplus +extern "C" { +#endif +/* get cache control register value */ +__attribute__((always_inline)) static inline uint32_t l1c_get_control(void) +{ + return read_csr(CSR_MCACHE_CTL); +} + +__attribute__((always_inline)) static inline bool l1c_dc_is_enabled(void) +{ + return l1c_get_control() & HPM_MCACHE_CTL_DC_EN_MASK; +} + +__attribute__((always_inline)) static inline bool l1c_ic_is_enabled(void) +{ + return l1c_get_control() & HPM_MCACHE_CTL_IC_EN_MASK; +} + +/* mcctlbeginaddress register bitfield layout for CCTL IX type command */ +#define HPM_MCCTLBEGINADDR_OFFSET_SHIFT (2UL) +#define HPM_MCCTLBEGINADDR_OFFSET_MASK ((uint32_t) 0xF << HPM_MCCTLBEGINADDR_OFFSET_SHIFT) +#define HPM_MCCTLBEGINADDR_OFFSET(x) \ + (uint32_t)(((x) << HPM_MCCTLBEGINADDR_OFFSET_SHIFT) & HPM_MCCTLBEGINADDR_OFFSET_MASK) +#define HPM_MCCTLBEGINADDR_INDEX_SHIFT (6UL) +#define HPM_MCCTLBEGINADDR_INDEX_MASK ((uint32_t) 0x3F << HPM_MCCTLBEGINADDR_INDEX_SHIFT) +#define HPM_MCCTLBEGINADDR_INDEX(x) \ + (uint32_t)(((x) << HPM_MCCTLBEGINADDR_INDEX_SHIFT) & HPM_MCCTLBEGINADDR_INDEX_MASK) +#define HPM_MCCTLBEGINADDR_WAY_SHIFT (13UL) +#define HPM_MCCTLBEGINADDR_WAY_MASK ((uint32_t) 0x3 << HPM_MCCTLBEGINADDR_WAY_SHIFT) +#define HPM_MCCTLBEGINADDR_WAY(x) \ + (uint32_t)(((x) << HPM_MCCTLBEGINADDR_WAY_SHIFT) & HPM_MCCTLBEGINADDR_WAY_MASK) + +/* send IX command */ +__attribute__((always_inline)) static inline void l1c_cctl_address(uint32_t address) +{ + write_csr(CSR_MCCTLBEGINADDR, address); +} + +/* send command */ +__attribute__((always_inline)) static inline void l1c_cctl_cmd(uint8_t cmd) +{ + write_csr(CSR_MCCTLCOMMAND, cmd); +} + +__attribute__((always_inline)) static inline uint32_t l1c_cctl_get_address(void) +{ + return read_csr(CSR_MCCTLBEGINADDR); +} + +/* send IX command */ +__attribute__((always_inline)) static inline + void l1c_cctl_address_cmd(uint8_t cmd, uint32_t address) +{ + write_csr(CSR_MCCTLBEGINADDR, address); + write_csr(CSR_MCCTLCOMMAND, cmd); +} + +#define HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT (2UL) +#define HPM_MCCTLDATA_I_TAG_ADDRESS_MASK (uint32_t)(0XFFFFF << HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT) +#define HPM_MCCTLDATA_I_TAG_ADDRESS(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT) & HPM_MCCTLDATA_I_TAG_ADDRESS_MASK) + +#define HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT (29UL) +#define HPM_MCCTLDATA_I_TAG_LOCK_DUP_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT) +#define HPM_MCCTLDATA_I_TAG_LOCK_DUP(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT) & HPM_MCCTLDATA_I_TAG_LOCK_DUP_MASK) + +#define HPM_MCCTLDATA_I_TAG_LOCK_SHIFT (30UL) +#define HPM_MCCTLDATA_I_TAG_LOCK_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_LOCK_SHIFT) +#define HPM_MCCTLDATA_I_TAG_LOCK(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_LOCK_SHIFT) & HPM_MCCTLDATA_I_TAG_LOCK_MASK) + +#define HPM_MCCTLDATA_I_TAG_VALID_SHIFT (31UL) +#define HPM_MCCTLDATA_I_TAG_VALID_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_VALID_SHIFT) +#define HPM_MCCTLDATA_I_TAG_VALID(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_VALID_SHIFT) & HPM_MCCTLDATA_I_TAG_VALID_MASK) + +#define HPM_MCCTLDATA_D_TAG_MESI_SHIFT (0UL) +#define HPM_MCCTLDATA_D_TAG_MESI_MASK (uint32_t)(0x3 << HPM_MCCTLDATA_D_TAG_MESI_SHIFT) +#define HPM_MCCTLDATA_D_TAG_MESI(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_MESI_SHIFT) & HPM_MCCTLDATA_D_TAG_MESI_MASK) + +#define HPM_MCCTLDATA_D_TAG_LOCK_SHIFT (3UL) +#define HPM_MCCTLDATA_D_TAG_LOCK_MASK (uint32_t)(0x1 << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) +#define HPM_MCCTLDATA_D_TAG_LOCK(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) & HPM_MCCTLDATA_D_TAG_LOCK_MASK) + +#define HPM_MCCTLDATA_D_TAG_TAG_SHIFT (4UL) +#define HPM_MCCTLDATA_D_TAG_TAG_MASK (uint32_t)(0xFFFF << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) +#define HPM_MCCTLDATA_D_TAG_TAG(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_TAG_SHIFT) & HPM_MCCTLDATA_D_TAG_TAG_MASK) + +/* + * @brief Cache control command read address + * + * Send IX read tag/data cmd + * @param[in] cmd Command code + * @param[in] address Target address + * @param[in] ecc_data ECC value + * @return data read + */ +ATTR_ALWAYS_INLINE static inline + uint32_t l1c_cctl_address_cmd_read(uint8_t cmd, uint32_t address, uint32_t *ecc_data) +{ + write_csr(CSR_MCCTLBEGINADDR, address); + write_csr(CSR_MCCTLCOMMAND, cmd); + *ecc_data = read_csr(CSR_MECC_CODE); + return read_csr(CSR_MCCTLDATA); +} + +/* + * @brief Cache control command write address + * + * Send IX write tag/data cmd + * @param[in] cmd Command code + * @param[in] address Target address + * @param[in] data Data to be written + * @param[in] ecc_data ECC of data + */ +ATTR_ALWAYS_INLINE static inline + void l1c_cctl_address_cmd_write(uint8_t cmd, uint32_t address, uint32_t data, uint32_t ecc_data) +{ + write_csr(CSR_MCCTLBEGINADDR, address); + write_csr(CSR_MCCTLCOMMAND, cmd); + write_csr(CSR_MCCTLDATA, data); + write_csr(CSR_MECC_CODE, ecc_data); +} + +#define HPM_L1C_CFG_SET_SHIFT (0UL) +#define HPM_L1C_CFG_SET_MASK (uint32_t)(0x7 << HPM_L1C_CFG_SET_SHIFT) +#define HPM_L1C_CFG_WAY_SHIFT (3UL) +#define HPM_L1C_CFG_WAY_MASK (uint32_t)(0x7 << HPM_L1C_CFG_WAY_SHIFT) +#define HPM_L1C_CFG_SIZE_SHIFT (6UL) +#define HPM_L1C_CFG_SIZE_MASK (uint32_t)(0x7 << HPM_L1C_CFG_SIZE_SHIFT) +#define HPM_L1C_CFG_LOCK_SHIFT (9UL) +#define HPM_L1C_CFG_LOCK_MASK (uint32_t)(0x1 << HPM_L1C_CFG_LOCK_SHIFT) +#define HPM_L1C_CFG_ECC_SHIFT (10UL) +#define HPM_L1C_CFG_ECC_MASK (uint32_t)(0x3 << HPM_L1C_CFG_ECC_SHIFT) +#define HPM_L1C_CFG_LMB_SHIFT (12UL) +#define HPM_L1C_CFG_LMB_MASK (uint32_t)(0x7 << HPM_L1C_CFG_LMB_SHIFT) +#define HPM_L1C_CFG_LM_SIZE_SHIFT (15UL) +#define HPM_L1C_CFG_LM_SIZE_MASK (uint32_t)(0x1F << HPM_L1C_CFG_LM_SIZE_SHIFT) +#define HPM_L1C_CFG_LM_ECC_SHIFT (21UL) +#define HPM_L1C_CFG_LM_ECC_MASK (uint32_t)(0x3 << HPM_L1C_CFG_LM_ECC_SHIFT) +#define HPM_L1C_CFG_SETH_SHIFT (24UL) +#define HPM_L1C_CFG_SETH_MASK (uint32_t)(0x1 << HPM_L1C_CFG_SETH_SHIFT) + +/** + * @brief Align down based on cache line size + */ +#define HPM_L1C_CACHELINE_ALIGN_DOWN(n) ((uint32_t)(n) & ~(HPM_L1C_CACHELINE_SIZE - 1U)) + +/** + * @brief Align up based on cache line size + */ +#define HPM_L1C_CACHELINE_ALIGN_UP(n) HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)(n) + HPM_L1C_CACHELINE_SIZE - 1U) + +/** + * @brief Get I-cache configuration + * + * @return I-cache config register + */ +ATTR_ALWAYS_INLINE static inline uint32_t l1c_ic_get_config(void) +{ + return read_csr(CSR_MICM_CFG); +} + +/** + * @brief Get D-cache configuration + * + * @return D-cache config register + */ +ATTR_ALWAYS_INLINE static inline uint32_t l1c_dc_get_config(void) +{ + return read_csr(CSR_MDCM_CFG); +} + +/* + * @brief D-cache disable + */ +void l1c_dc_disable(void); + +/* + * @brief D-cache enable + */ +void l1c_dc_enable(void); + +/* + * @brief D-cache invalidate by address + * @param[in] address Start address to be invalidated + * @param[in] size Size of memory to be invalidated + */ +void l1c_dc_invalidate(uint32_t address, uint32_t size); + +/* + * @brief D-cache writeback by address + * @param[in] address Start address to be writtenback + * @param[in] size Size of memory to be writtenback + */ +void l1c_dc_writeback(uint32_t address, uint32_t size); + +/* + * @brief D-cache invalidate and writeback by address + * @param[in] address Start address to be invalidated and writtenback + * @param[in] size Size of memory to be invalidted and writtenback + */ +void l1c_dc_flush(uint32_t address, uint32_t size); + +/* + * @brief D-cache fill and lock by address + * @param[in] address Start address to be filled and locked + * @param[in] size Size of memory to be filled and locked + */ +void l1c_dc_fill_lock(uint32_t address, uint32_t size); + +/* + * @brief I-cache disable + */ +void l1c_ic_disable(void); + +/* + * @brief I-cache enable + */ +void l1c_ic_enable(void); + +/* + * @brief I-cache invalidate by address + * @param[in] address Start address to be invalidated + * @param[in] size Size of memory to be invalidated + */ +void l1c_ic_invalidate(uint32_t address, uint32_t size); + +/* + * @brief I-cache fill and lock by address + * @param[in] address Start address to be locked + * @param[in] size Size of memory to be locked + */ +void l1c_ic_fill_lock(uint32_t address, uint32_t size); + +/* + * @brief Invalidate all icache and writeback all dcache + */ +void l1c_fence_i(void); + +/* + * @brief Invalidate all d-cache + */ +void l1c_dc_invalidate_all(void); + +/* + * @brief Writeback all d-cache + */ +void l1c_dc_writeback_all(void); + +/* + * @brief Flush all d-cache + */ +void l1c_dc_flush_all(void); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* _HPM_L1_CACHE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_mcan_soc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_mcan_soc.h new file mode 100644 index 00000000000..d52c180db8f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_mcan_soc.h @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_MCAN_SOC_H +#define HPM_MCAN_SOC_H + +#include +#include "hpm_mcan_regs.h" +#include "hpm_soc.h" + +#define MCAN_SOC_TSU_SRC_TWO_STAGES (1U) + +#define HPM_MCAN_EXT_TBSEL_NUM (4U) +#define HPM_MCAN_TBSEL_BASE (0xF02FF000UL) +#define HPM_MCAN_TBSEL (*(volatile uint32_t *)HPM_MCAN_TBSEL_BASE) +#define HPM_MCAN_TBSEL_BITWDITH (6U) +#define HPM_MCAN_TBSEL_MASK ((1UL << HPM_MCAN_TBSEL_BITWDITH) - 1UL) +#define HPM_MCAN_TBSEL0_SHIFT (8U) + +/** + * @brief MCAN MSG BUF base address (AHB_RAM) + */ +#define MCAN_MSG_BUF_BASE (0xF0400000UL) +#define MCAN_MSG_BUF_SIZE_IN_WORDS (640U) +#define MCAN_IP_SLOT_SIZE (0x4000U) + +/** + * @brief TSU External Timebase Sources + */ +#define MCAN_TSU_EXT_TIMEBASE_SRC_MIN (0U) +#define MCAN_TSU_EXT_TIMEBASE_SRC_TBSEL_0 (MCAN_TSU_EXT_TIMEBASE_SRC_MIN) +#define MCAN_TSU_EXT_TIMEBASE_SRC_TBSEL_1 (1U) +#define MCAN_TSU_EXT_TIMEBASE_SRC_TBSEL_2 (2U) +#define MCAN_TSU_EXT_TIMEBASE_SRC_TBSEL_3 (3U) +#define MCAN_TSU_EXT_TIMEBASE_SRC_MAX (MCAN_TSU_EXT_TIMEBASE_SRC_TBSEL_3) + +/** + * @brief MCAN TSU timebase option for each External Timebase + */ +#define MCAN_TSU_TBSEL_PTPC0 (0x20) +#define MCAN_TSU_TBSEL_MCAN0 (0x00) +#define MCAN_TSU_TBSEL_MCAN1 (0x01) +#define MCAN_TSU_TBSEL_MCAN2 (0x02) +#define MCAN_TSU_TBSEL_MCAN3 (0x03) +#define MCAN_TSU_TBSEL_MCAN4 (0x04) +#define MCAN_TSU_TBSEL_MCAN5 (0x05) +#define MCAN_TSU_TBSEL_MCAN6 (0x06) +#define MCAN_TSU_TBSEL_MCAN7 (0x07) + + +#ifdef __cpluspus +extern "C" { +#endif + +/** + * @brief Set External Timebase Source for MCAN TSU + * @param [in] ptr MCAN base + * @param [in] src External Timebase source + */ +static inline void mcan_set_tsu_ext_timebase_src(MCAN_Type *ptr, uint8_t src) +{ + if (src < HPM_MCAN_EXT_TBSEL_NUM) { + ptr->GLB_CTL = (ptr->GLB_CTL & ~MCAN_GLB_CTL_TSU_TBIN_SEL_MASK) | MCAN_GLB_CTL_TSU_TBIN_SEL_SET(src); + } +} + +/** + * @brief Set the Source for specified external timebase + * + * @param [in] ptr MCAN base + * @param [in] ext_tbsel External TBSEL index + * @param [in] tbsel_option Timebase source selection + */ +static inline void mcan_set_tsu_tbsel_option(MCAN_Type *ptr, uint8_t ext_tbsel, uint8_t tbsel_option) +{ + (void) ptr; + if (ext_tbsel < HPM_MCAN_EXT_TBSEL_NUM) { + uint32_t tbsel_shift = (ext_tbsel * HPM_MCAN_TBSEL_BITWDITH) + HPM_MCAN_TBSEL0_SHIFT; + uint32_t tbsel_mask = HPM_MCAN_TBSEL_MASK << tbsel_shift; + HPM_MCAN_TBSEL = (HPM_MCAN_TBSEL & ~tbsel_mask) | (((uint32_t)tbsel_option << tbsel_shift) & tbsel_mask); + } +} + +/** + * @brief Enable Standby Pin for MCAN + * @param [in] ptr MCAN base + */ +static inline void mcan_enable_standby_pin(MCAN_Type *ptr) +{ + ptr->GLB_CTL |= MCAN_GLB_CTL_M_CAN_STBY_MASK; +} + +/** + * @brief Disable Standby pin for MCAN + * @param [in] ptr MCAN base + */ +static inline void mcan_disable_standby_pin(MCAN_Type *ptr) +{ + ptr->GLB_CTL &= ~MCAN_GLB_CTL_M_CAN_STBY_MASK; +} + +/** + * @brief Get RAM base for MCAN + * @param [in] ptr MCAN base + * @return RAM base for MCAN + */ +static inline uint32_t mcan_get_ram_base(MCAN_Type *ptr) +{ + (void) ptr; + return MCAN_MSG_BUF_BASE; +} + +/** + * @brief Get the MCAN RAM offset in the dedicated/shared RAM for + * @param [in] ptr MCAN base + * @return RAM offset for MCAN + */ +static inline uint32_t mcan_get_ram_offset(MCAN_Type *ptr) +{ + uint32_t index = ((uint32_t) ptr - HPM_MCAN0_BASE) / MCAN_IP_SLOT_SIZE; + + return (index * MCAN_MSG_BUF_SIZE_IN_WORDS * sizeof(uint32_t)); +} + +/** + * @brief Get MCAN RAM size + * @param [in] ptr MCAN base + * @return RAM size in bytes + */ +static inline uint32_t mcan_get_ram_size(MCAN_Type *ptr) +{ + (void) ptr; + return (MCAN_MSG_BUF_SIZE_IN_WORDS * sizeof(uint32_t)); +} + +#ifdef __cpluspus +} +#endif + +#endif /* HPM_MCAN_SOC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_misc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_misc.h new file mode 100644 index 00000000000..e81a74fa29f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_misc.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_MISC_H +#define HPM_MISC_H + +#define ILM_LOCAL_BASE (0x0U) +#define ILM_SIZE_IN_BYTE (0x40000U) +#define DLM_LOCAL_BASE (0x80000U) +#define DLM_SIZE_IN_BYTE (0x40000U) +#define CORE0_ILM_SYSTEM_BASE (0x1040000U) +#define CORE0_DLM_SYSTEM_BASE (0x1060000U) +#define CORE1_ILM_SYSTEM_BASE (0x1180000U) +#define CORE1_DLM_SYSTEM_BASE (0x11C0000U) + +#define ADDRESS_IN_ILM(address) \ + ((ILM_LOCAL_BASE) <= (address)) && \ + ((ILM_LOCAL_BASE + ILM_SIZE_IN_BYTE) > (address)) +#define ADDRESS_IN_DLM(address) \ + ((DLM_LOCAL_BASE) <= (address)) && \ + ((DLM_LOCAL_BASE + DLM_SIZE_IN_BYTE) > (address)) +#define ADDRESS_IN_CORE0_DLM_SYSTEM(address) \ + ((CORE0_DLM_SYSTEM_BASE) <= (address)) && \ + ((CORE0_DLM_SYSTEM_BASE + DLM_SIZE_IN_BYTE) > (address)) + +#define DLM_TO_SYSTEM(address) \ + (CORE0_DLM_SYSTEM_BASE + (address) - (DLM_LOCAL_BASE)) +#define ILM_TO_SYSTEM(address) \ + (CORE0_ILM_SYSTEM_BASE + (address) - (ILM_LOCAL_BASE)) +#define SYSTEM_TO_DLM(address) \ + ((address) - CORE0_DLM_SYSTEM_BASE + (DLM_LOCAL_BASE)) + +#define HPM_CORE0 (0U) +#define HPM_CORE1 (1U) + +/* map core local memory(DLM/ILM) to system address */ +static inline uint32_t core_local_mem_to_sys_address(uint8_t core_id, uint32_t addr) +{ + (void) core_id; + return addr; +} + +/* map system address to core local memory(DLM/ILM) */ +static inline uint32_t sys_address_to_core_local_mem(uint8_t core_id, uint32_t addr) +{ + (void) core_id; + return addr; +} +#endif /* HPM_MISC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_otp_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_otp_drv.c new file mode 100644 index 00000000000..36c05c561f4 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_otp_drv.c @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2021-2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_otp_drv.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +#define SHADOW_INDEX_IN_PMIC_OTP_END (15U) +#define OTP_UNLOCK_MAGIC_NUM (0x4E45504FUL) /*!< ASCII: OPEN */ +#define OTP_LOCK_MAGIC_NUM (~OTP_UNLOCK_MAGIC_NUM) +#define OTP_CMD_PROGRAM (0x574F4C42UL) /*!< ASCII: BLOW */ +#define OTP_CMD_READ (0x44414552UL) /*!< ASCII: READ */ + + +/*********************************************************************************************************************** + * Codes + **********************************************************************************************************************/ +void otp_init(void) +{ + +} + +void otp_deinit(void) +{ + +} + +uint32_t otp_read_from_shadow(uint32_t addr) +{ + uint32_t ret_val = 0; + if (addr < ARRAY_SIZE(HPM_OTP->SHADOW)) { + ret_val = HPM_OTP->SHADOW[addr]; + } + + return ret_val; +} + +uint32_t otp_read_from_ip(uint32_t addr) +{ + uint32_t ret_val = 0; + if (addr < ARRAY_SIZE(HPM_OTP->SHADOW)) { + ret_val = HPM_OTP->FUSE[addr]; + } + return ret_val; +} + +hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words) +{ + hpm_stat_t status = status_invalid_argument; + do { + uint32_t fuse_idx_max = ARRAY_SIZE(HPM_OTP->SHADOW); + HPM_BREAK_IF((addr >= fuse_idx_max) || (num_of_words > fuse_idx_max) || (addr + num_of_words > fuse_idx_max)); + + /* Enable 2.5V LDO for FUSE programming */ + uint32_t reg_val = (HPM_PCFG->LDO2P5 & ~PCFG_LDO2P5_VOLT_MASK) | PCFG_LDO2P5_ENABLE_MASK | PCFG_LDO2P5_VOLT_SET(2500); + HPM_PCFG->LDO2P5 = reg_val; + /* Wait until LDO is ready */ + while (!IS_HPM_BITMASK_SET(HPM_PCFG->LDO2P5, PCFG_DCDC_MODE_READY_MASK)) { + } + HPM_OTP->UNLOCK = OTP_UNLOCK_MAGIC_NUM; + for (uint32_t i = 0; i < num_of_words; i++) { + HPM_OTP->FUSE[addr++] = *src++; + } + HPM_OTP->UNLOCK = OTP_LOCK_MAGIC_NUM; + /* Disable 2.5V LDO after FUSE programming for saving power */ + HPM_PCFG->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; + status = status_success; + } while (false); + + return status; +} + +hpm_stat_t otp_reload(otp_region_t region) +{ + hpm_stat_t status = status_invalid_argument; + if ((uint32_t)region < 0x10 && (region >= otp_region0_mask)) { + HPM_OTP->LOAD_REQ = (uint32_t)region; + HPM_OTP->LOAD_COMP = (uint32_t)region; + while (!IS_HPM_BITMASK_SET(HPM_OTP->LOAD_COMP, region)) { + + } + status = status_success; + } + + return status; +} + +hpm_stat_t otp_lock_otp(uint32_t addr, otp_lock_option_t lock_option) +{ + hpm_stat_t status = status_invalid_argument; + + do { + HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW) || (lock_option > otp_lock_option_max)); + + OTP_Type *otp_base = HPM_OTP; + + uint32_t lock_reg_idx = (addr << 1) / 32; + uint32_t lock_reg_offset = (addr << 1) % 32; + + uint32_t lock_mask = ((uint32_t)lock_option) << lock_reg_offset; + + otp_base->FUSE_LOCK[lock_reg_idx] = lock_mask; + + status = status_success; + } while (false); + + return status; +} + +hpm_stat_t otp_lock_shadow(uint32_t addr, otp_lock_option_t lock_option) +{ + hpm_stat_t status = status_invalid_argument; + + do { + HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW) || (lock_option > otp_lock_option_max)); + + OTP_Type *otp_base = HPM_OTP; + + uint32_t lock_reg_idx = (addr << 1) / 32; + uint32_t lock_reg_offset = (addr << 1) % 32; + + uint32_t lock_mask = ((uint32_t)lock_option) << lock_reg_offset; + + otp_base->SHADOW_LOCK[lock_reg_idx] = lock_mask; + + status = status_success; + } while (false); + + return status; +} + +hpm_stat_t otp_set_configurable_region(uint32_t start, uint32_t num_of_words) +{ + hpm_stat_t status = status_invalid_argument; + + do { + uint32_t max_fuse_idx = ARRAY_SIZE(HPM_OTP->SHADOW); + HPM_BREAK_IF((start >= max_fuse_idx) || (num_of_words > max_fuse_idx) || ((start + num_of_words) > max_fuse_idx)); + + HPM_OTP->REGION[3] = OTP_REGION_START_SET(start) + | OTP_REGION_STOP_SET(start + num_of_words); + + status = status_success; + } while (false); + + return status; +} + +hpm_stat_t otp_write_shadow_register(uint32_t addr, uint32_t val) +{ + hpm_stat_t status = status_invalid_argument; + do { + HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW)); + + uint32_t lock_reg_idx = (addr << 1) / 32; + uint32_t lock_reg_offset = (addr << 1) % 32; + uint32_t lock_mask = 3U << lock_reg_offset; + + OTP_Type *otp_base = HPM_OTP; + otp_lock_option_t lock_opt = (otp_lock_option_t) ((otp_base->SHADOW_LOCK[lock_reg_idx] & lock_mask) + >> lock_reg_offset); + + if (lock_opt != otp_no_lock) { + status = otp_write_disallowed; + break; + } + + otp_base->SHADOW[addr] = val; + + status = status_success; + } while (false); + + return status; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_otp_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_otp_drv.h new file mode 100644 index 00000000000..afb2f22de54 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_otp_drv.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2022-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_OTP_DRV_H +#define HPM_OTP_DRV_H + +/** + * @brief OTP APIs + * @defgroup otp_interface OTP driver APIs + * @{ + */ + +#include "hpm_common.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +/** + * @brief OTP region definitions + */ +typedef enum { + otp_region0_mask = 1U, /*!< Address range: [0, 7] */ + otp_region1_mask = 2U, /*!< Address range: [8, 15] */ + otp_region2_mask = 4U, /*!< Address range: [16, 127] */ + otp_region3_mask = 8U, /*!< Address range: user defined */ +} otp_region_t; + +/** + * @brief OTP lock options + */ +typedef enum { + otp_no_lock = 0, + otp_read_only = 1, + otp_permanent_no_lock = 2, + otp_disable_access = 3, + otp_lock_option_max = otp_disable_access, +} otp_lock_option_t; + +enum { + otp_write_disallowed = MAKE_STATUS(status_group_otp, 0), +}; + +/*********************************************************************************************************************** + * Prototypes + **********************************************************************************************************************/ +#ifdef __cpluscplus +extern "C" { +#endif + +/** + * @brief Initialize OTP controller + */ +void otp_init(void); + +/** + * @brief De-initialize OTP controller + */ +void otp_deinit(void); + +/** + * @brief Read the OTP word from shadow register + * @param [in] addr OTP word index + * @retval OTP word value + */ +uint32_t otp_read_from_shadow(uint32_t addr); + +/** + * @brief Read the specified OTP word from OTP IP bus + * @param [in] addr OTP word index + * @retval OTP word value + */ +uint32_t otp_read_from_ip(uint32_t addr); + +/** + * @brief Program a word to specified OTP field + * @param [in] addr OTP word index + * @param [in] src Pointer to the data to be programmed + * @param [in] num_of_words Number of words to be programmed, only 1 is allowed + * @return API execution status + */ +hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words); + +/** + * @brief Reload a OTP region + * @param [in] region OTP region option + * @return API execution status + */ +hpm_stat_t otp_reload(otp_region_t region); + +/** + * @brief Change the Software lock permission + * @param [in] addr OTP word index + * @param [in] lock_option OTP lcok option + * @return API execution status + */ +hpm_stat_t otp_lock_otp(uint32_t addr, otp_lock_option_t lock_option); + +/** + * @brief OTP lock shadow + * @param [in] addr OTP word index + * @param [in] lock_option OTP lock option + * @return API execution status + */ +hpm_stat_t otp_lock_shadow(uint32_t addr, otp_lock_option_t lock_option); + +/** + * @brief Set the configurable region range + * @param [in] start OTP word start index + * @param [in] num_of_words Number of words in configuration region + * @retval status_out_of_range Invalid range + * @retval status_success Operation is successful + */ +hpm_stat_t otp_set_configurable_region(uint32_t start, uint32_t num_of_words); + +/** + * @return Write data to OTP shadow register + * @param [in] addr OTP word index + * @param [in] val Data to be written + * @return API execution status + */ +hpm_stat_t otp_write_shadow_register(uint32_t addr, uint32_t val); + + +#ifdef __cpluscplus +} +#endif +/** + * @} + */ + + + + +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_pcfg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_pcfg_drv.h new file mode 100644 index 00000000000..b4d5a6068ed --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_pcfg_drv.h @@ -0,0 +1,888 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PCFG_DRV_H +#define HPM_PCFG_DRV_H + +#include "hpm_common.h" +#include "hpm_pcfg_regs.h" + +/** + * + * @brief PCFG driver APIs + * @defgroup pcfg_interface PCFG driver APIs + * @ingroup io_interfaces + * @{ + */ +#define PCFG_CLOCK_GATE_MODE_ALWAYS_ON (0x3UL) +#define PCFG_CLOCK_GATE_MODE_ALWAYS_OFF (0x2UL) + +#define PCFG_PERIPH_KEEP_CLOCK_ON(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_ON << (p)) +#define PCFG_PERIPH_KEEP_CLOCK_OFF(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_OFF << (p)) + +/* @brief PCFG irc24m reference */ +typedef enum { + pcfg_irc24m_reference_32k = 0, + pcfg_irc24m_reference_24m_xtal = 1 +} pcfg_irc24m_reference_t; + +/* @brief PCFG dcdc current limit */ +typedef enum { + pcfg_dcdc_lp_current_limit_250ma = 0, + pcfg_dcdc_lp_current_limit_200ma = 1, +} pcfg_dcdc_lp_current_limit_t; + +typedef enum { + pcfg_dcdc_oc_limit_2000ma = 0, + pcfg_dcdc_oc_limit_1300ma = 1, +} pcfg_dcdc_oc_limit_t; + +/* @brief PCFG dcdc current hys */ +typedef enum { + pcfg_dcdc_current_hys_12_5mv = 0, + pcfg_dcdc_current_hys_25mv = 1, +} pcfg_dcdc_current_hys_t; + +/* @brief PCFG dcdc mode */ +typedef enum { + pcfg_dcdc_mode_off = 0, + pcfg_dcdc_mode_basic = 1, + pcfg_dcdc_mode_general = 3, + pcfg_dcdc_mode_expert = 7, +} pcfg_dcdc_mode_t; + +/* @brief PCFG pmc domain peripherals */ +typedef enum { + pcfg_pmc_periph_gpio = 6, + pcfg_pmc_periph_ioc = 8, + pcfg_pmc_periph_timer = 10, + pcfg_pmc_periph_wdog = 12, + pcfg_pmc_periph_uart = 14, + pcfg_pmc_periph_vad = 16, + pcfg_pmc_periph_pmic_mem = 18, +} pcfg_pmc_periph_t; + +/* @brief PCFG status */ +enum { + status_pcfg_ldo_out_of_range = MAKE_STATUS(status_group_pcfg, 1), +}; + +/* @brief PCFG irc24m config */ +typedef struct { + uint32_t freq_in_hz; + pcfg_irc24m_reference_t reference; + bool return_to_default_on_xtal_loss; + bool free_run; +} pcfg_irc24m_config_t; + + +#define PCFG_CLOCK_GATE_CONTROL_MASK(module, mode) \ + ((uint32_t) (mode) << ((module) << 1)) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief bandgap disable power save mode + * + * @param[in] ptr base address + */ +static inline void pcfg_bandgap_disable_power_save_mode(PCFG_Type *ptr) +{ + ptr->BANDGAP &= ~PCFG_BANDGAP_POWER_SAVE_MASK; +} + +/** + * @brief bandgap enable power save mode + * + * @param[in] ptr base address + */ +static inline void pcfg_bandgap_enable_power_save_mode(PCFG_Type *ptr) +{ + ptr->BANDGAP |= PCFG_BANDGAP_POWER_SAVE_MASK; +} + +/** + * @brief bandgap disable power save mode + * + * @param[in] ptr base address + */ +static inline void pcfg_bandgap_disable_lowpower_mode(PCFG_Type *ptr) +{ + ptr->BANDGAP &= ~PCFG_BANDGAP_LOWPOWER_MODE_MASK; +} + +/** + * @brief bandgap enable low power mode + * + * @param[in] ptr base address + */ +static inline void pcfg_bandgap_enable_lowpower_mode(PCFG_Type *ptr) +{ + ptr->BANDGAP |= PCFG_BANDGAP_LOWPOWER_MODE_MASK; +} + +/** + * @brief check if bandgap is trimmed or not + * + * @param[in] ptr base address + * + * @retval true if bandgap is trimmed + */ +static inline bool pcfg_bandgap_is_trimmed(PCFG_Type *ptr) +{ + return ptr->BANDGAP & PCFG_BANDGAP_VBG_TRIMMED_MASK; +} + +/** + * @brief bandgap reload trim value + * + * @param[in] ptr base address + */ +static inline void pcfg_bandgap_reload_trim(PCFG_Type *ptr) +{ + ptr->BANDGAP &= ~PCFG_BANDGAP_VBG_TRIMMED_MASK; +} + +/** + * @brief turn off LDO2P5 + * + * @param[in] ptr base address + */ +static inline void pcfg_ldo2p5_turn_off(PCFG_Type *ptr) +{ + ptr->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; +} + +/** + * @brief turn on LDO 2.5V + * + * @param[in] ptr base address + */ +static inline void pcfg_ldo2p5_turn_on(PCFG_Type *ptr) +{ + ptr->LDO2P5 |= PCFG_LDO2P5_ENABLE_MASK; +} + +/** + * @brief check if LDO 2.5V is stable + * + * @param[in] ptr base address + * + * @retval true if LDO2P5 is stable + */ +static inline bool pcfg_ldo2p5_is_stable(PCFG_Type *ptr) +{ + return PCFG_LDO2P5_READY_GET(ptr->LDO2P5); +} + +/* + * @brief check if DCDC is stable or not + * @param[in] ptr base address + * @retval true if DCDC is stable + */ +static inline bool pcfg_dcdc_is_stable(PCFG_Type *ptr) +{ + return PCFG_DCDC_MODE_READY_GET(ptr->DCDC_MODE); +} + +/* + * @brief set DCDC work mode + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_set_mode(PCFG_Type *ptr, uint8_t mode) +{ + ptr->DCDC_MODE = (ptr->DCDC_MODE & ~PCFG_DCDC_MODE_MODE_MASK) | PCFG_DCDC_MODE_MODE_SET(mode); +} + +/** + * @brief set low power current limit + * + * @param[in] ptr base address + * @param[in] limit current limit at low power mode + * @param[in] over_limit unused + */ +static inline void pcfg_dcdc_set_lp_current_limit(PCFG_Type *ptr, pcfg_dcdc_lp_current_limit_t limit, bool over_limit) +{ + (void) over_limit; + ptr->DCDC_PROT = (ptr->DCDC_PROT & ~(PCFG_DCDC_PROT_ILIMIT_LP_MASK)) + | PCFG_DCDC_PROT_ILIMIT_LP_SET(limit); +} + +/** + * @brief disable power loss protection + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_disable_power_loss_prot(PCFG_Type *ptr) +{ + ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK; +} + +/** + * @brief enable power loss protection + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_enable_power_loss_prot(PCFG_Type *ptr) +{ + ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK; +} + +/** + * @brief check if power loss flag is set + * + * @param[in] ptr base address + * + * @retval true if power loss is set + */ +static inline bool pcfg_dcdc_is_power_loss(PCFG_Type *ptr) +{ + return PCFG_DCDC_PROT_POWER_LOSS_FLAG_GET(ptr->DCDC_PROT); +} + +/** + * @brief disable over voltage protection + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_disable_over_voltage_prot(PCFG_Type *ptr) +{ + ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK; +} + +/** + * @brief enable over voltage protection + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_enable_over_voltage_prot(PCFG_Type *ptr) +{ + ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK; +} + +/** + * @brief checkover over voltage flag + * + * @param[in] ptr base address + * @retval true if flag is set + */ +static inline bool pcfg_dcdc_is_over_voltage(PCFG_Type *ptr) +{ + return PCFG_DCDC_PROT_OVERVOLT_FLAG_GET(ptr->DCDC_PROT); +} + +/** + * @brief disable over current protection + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_disable_over_current_prot(PCFG_Type *ptr) +{ + ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_SHORT_MASK; +} + +/** + * @brief enable over current protection + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_enable_over_current_prot(PCFG_Type *ptr) +{ + ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_DISABLE_SHORT_MASK; +} + +/** + * @brief set over current limit + * + * @param[in] ptr base address + * @param[in] limit reference pcfg_dcdc_oc_limit_t + */ +static inline void pcfg_dcdc_set_over_current_limit(PCFG_Type *ptr, pcfg_dcdc_oc_limit_t limit) +{ + ptr->DCDC_PROT = (ptr->DCDC_PROT & ~PCFG_DCDC_PROT_SHORT_CURRENT_MASK) | PCFG_DCDC_PROT_SHORT_CURRENT_SET(limit); +} + +/** + * @brief checkover over current flag + * + * @param[in] ptr base address + * @retval true if flag is set + */ +static inline bool pcfg_dcdc_is_over_current(PCFG_Type *ptr) +{ + return PCFG_DCDC_PROT_SHORT_FLAG_GET(ptr->DCDC_PROT); +} + +/** + * @brief disable current measurement + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_disable_measure_current(PCFG_Type *ptr) +{ + ptr->DCDC_CURRENT &= ~PCFG_DCDC_CURRENT_ESTI_EN_MASK; +} + +/** + * @brief enable current measurement + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_enable_measure_current(PCFG_Type *ptr) +{ + ptr->DCDC_CURRENT |= PCFG_DCDC_CURRENT_ESTI_EN_MASK; +} + +/** + * @brief check if measured current is valid + * + * @param[in] ptr base address + * + * @retval true if measured current is valid + */ +static inline bool pcfg_dcdc_is_measure_current_valid(PCFG_Type *ptr) +{ + return ptr->DCDC_CURRENT & PCFG_DCDC_CURRENT_VALID_MASK; +} + +/** + * @brief get measured current level + * + * @param[in] ptr base address + * + * @retval measured current, unit 50mA + */ +static inline bool pcfg_dcdc_get_measured_current_level(PCFG_Type *ptr) +{ + return PCFG_DCDC_CURRENT_LEVEL_GET(ptr->DCDC_CURRENT); +} + +/** + * @brief get DCDC start time in number of 24MHz clock cycles + * + * @param[in] ptr base address + * + * @retval dcdc start time in cycles + */ +static inline uint32_t pcfg_dcdc_get_start_time_in_cycle(PCFG_Type *ptr) +{ + return PCFG_DCDC_START_TIME_START_TIME_GET(ptr->DCDC_START_TIME); +} + +/** + * @brief get DCDC resume time in number of 24MHz clock cycles + * + * @param[in] ptr base address + * + * @retval dcdc resuem time in cycles + */ +static inline uint32_t pcfg_dcdc_get_resume_time_in_cycle(PCFG_Type *ptr) +{ + return PCFG_DCDC_RESUME_TIME_RESUME_TIME_GET(ptr->DCDC_RESUME_TIME); +} + +/** + * @brief set DCDC start time in 24MHz clock cycles + * + * @param[in] ptr base address + * @param[in] cycles start time in cycles + */ +static inline void pcfg_dcdc_set_start_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) +{ + ptr->DCDC_START_TIME = PCFG_DCDC_START_TIME_START_TIME_SET(cycles); +} + +/** + * @brief set DCDC resuem time in 24MHz clock cycles + * + * @param[in] ptr base address + * @param[in] cycles resume time in cycles + */ +static inline void pcfg_dcdc_set_resume_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) +{ + ptr->DCDC_RESUME_TIME = PCFG_DCDC_RESUME_TIME_RESUME_TIME_SET(cycles); +} + +/** + * @brief set dcdc current hysteres range + * + * @param[in] ptr base address + * @param[in] range current hysteres range + */ +static inline void pcfg_dcdc_set_current_hys_range(PCFG_Type *ptr, pcfg_dcdc_current_hys_t range) +{ + ptr->DCDC_MISC = (ptr->DCDC_MISC & (~PCFG_DCDC_MISC_OL_HYST_MASK)) | PCFG_DCDC_MISC_OL_HYST_SET(range); +} + +/** + * @brief disable power trap + * + * @param[in] ptr base address + */ +static inline void pcfg_disable_power_trap(PCFG_Type *ptr) +{ + ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_TRAP_MASK; +} + +/** + * @brief enable power trap + * + * @param[in] ptr base address + */ +static inline void pcfg_enable_power_trap(PCFG_Type *ptr) +{ + ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRAP_MASK; +} + +/** + * @brief check if power trap is triggered + * + * @param[in] ptr base address + * + * @retval true if power trap is triggered + */ +static inline bool pcfg_is_power_trap_triggered(PCFG_Type *ptr) +{ + return ptr->POWER_TRAP & PCFG_POWER_TRAP_TRIGGERED_MASK; +} + +/** + * @brief clear power trap trigger flag + * + * @param[in] ptr base address + */ +static inline void pcfg_clear_power_trap_trigger_flag(PCFG_Type *ptr) +{ + ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRIGGERED_MASK; +} + +/** + * @brief disable dcdc retention + * + * @param[in] ptr base address + */ +static inline void pcfg_disable_dcdc_retention(PCFG_Type *ptr) +{ + ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_RETENTION_MASK; +} + +/** + * @brief enable dcdc retention to retain soc sram data + * + * @param[in] ptr base address + */ +static inline void pcfg_enable_dcdc_retention(PCFG_Type *ptr) +{ + ptr->POWER_TRAP |= PCFG_POWER_TRAP_RETENTION_MASK; +} + +/** + * @brief clear wakeup cause flag + * + * @param[in] ptr base address + * @param[in] mask mask of flags to be cleared + */ +static inline void pcfg_clear_wakeup_cause(PCFG_Type *ptr, uint32_t mask) +{ + ptr->WAKE_CAUSE |= mask; +} + +/** + * @brief get wakeup cause + * + * @param[in] ptr base address + * + * @retval mask of wake cause + */ +static inline uint32_t pcfg_get_wakeup_cause(PCFG_Type *ptr) +{ + return ptr->WAKE_CAUSE; +} + +/** + * @brief enable wakeup source + * + * @param[in] ptr base address + * @param[in] mask wakeup source mask + */ +static inline void pcfg_enable_wakeup_source(PCFG_Type *ptr, uint32_t mask) +{ + ptr->WAKE_MASK &= ~mask; +} + +/** + * @brief disable wakeup source + * + * @param[in] ptr base address + * @param[in] mask source to be disabled as wakeup source + */ +static inline void pcfg_disable_wakeup_source(PCFG_Type *ptr, uint32_t mask) +{ + ptr->WAKE_MASK |= mask; +} + +/** + * @brief set clock gate mode in vpmc domain + * + * @param[in] ptr base address + * @param[in] mode clock gate mode mask + */ +static inline void pcfg_set_periph_clock_mode(PCFG_Type *ptr, uint32_t mode) +{ + ptr->SCG_CTRL = mode; +} + +/* + * @brief check if DDR DCDC is stable or not + * @param[in] ptr base address + * @retval true if DDR DCDC is stable + */ +static inline bool pcfg_ddr_dcdc_is_stable(PCFG_Type *ptr) +{ + return PCFG_DCDCM_MODE_READY_GET(ptr->DCDCM_MODE); +} + +/* + * @brief set DDR DCDC work mode + * @param[in] ptr base address + */ +static inline void pcfg_ddr_dcdc_set_mode(PCFG_Type *ptr, uint8_t mode) +{ + ptr->DCDCM_MODE = (ptr->DCDCM_MODE & ~PCFG_DCDCM_MODE_MODE_MASK) | PCFG_DCDCM_MODE_MODE_SET(mode); +} + + +/* + * @brief set on-chip DDR DCDC enable and voltage + * @param[in] ptr base address + * @param[in] voltage unit mv + */ +static inline void pcfg_ddr_dcdc_set_voltage_output(PCFG_Type *ptr, uint8_t voltage) +{ + ptr->DCDCM_MODE = (ptr->DCDCM_MODE & ~(PCFG_DCDCM_MODE_VOLT_MASK | PCFG_DCDCM_MODE_MODE_MASK)) + | PCFG_DCDCM_MODE_VOLT_SET(voltage) | PCFG_DCDCM_MODE_MODE_SET(pcfg_dcdc_mode_basic); +} + +/** + * @brief set ddr low power current limit + * + * @param[in] ptr base address + * @param[in] limit current limit at low power mode + */ +static inline void pcfg_ddr_dcdc_set_lp_current_limit(PCFG_Type *ptr, pcfg_dcdc_lp_current_limit_t limit) +{ + ptr->DCDCM_PROT = (ptr->DCDCM_PROT & ~(PCFG_DCDCM_PROT_ILIMIT_LP_MASK)) + | PCFG_DCDCM_PROT_ILIMIT_LP_SET(limit); +} + +/** + * @brief disable ddr power loss protection + * + * @param[in] ptr base address + */ +static inline void pcfg_ddr_dcdc_disable_power_loss_prot(PCFG_Type *ptr) +{ + ptr->DCDCM_PROT |= PCFG_DCDCM_PROT_DISABLE_POWER_LOSS_MASK; +} + +/** + * @brief enable ddr power loss protection + * + * @param[in] ptr base address + */ +static inline void pcfg_ddr_dcdc_enable_power_loss_prot(PCFG_Type *ptr) +{ + ptr->DCDCM_PROT &= ~PCFG_DCDCM_PROT_DISABLE_POWER_LOSS_MASK; +} + +/** + * @brief check if ddr power loss flag is set + * + * @param[in] ptr base address + * + * @retval true if power loss is set + */ +static inline bool pcfg_ddr_dcdc_is_power_loss(PCFG_Type *ptr) +{ + return PCFG_DCDCM_PROT_POWER_LOSS_FLAG_GET(ptr->DCDCM_PROT); +} + +/** + * @brief disable ddr over voltage protection + * + * @param[in] ptr base address + */ +static inline void pcfg_ddr_dcdc_disable_over_voltage_prot(PCFG_Type *ptr) +{ + ptr->DCDCM_PROT |= PCFG_DCDCM_PROT_DISABLE_OVERVOLTAGE_MASK; +} + +/** + * @brief enable ddr over voltage protection + * + * @param[in] ptr base address + */ +static inline void pcfg_ddr_dcdc_enable_over_voltage_prot(PCFG_Type *ptr) +{ + ptr->DCDCM_PROT &= ~PCFG_DCDCM_PROT_DISABLE_OVERVOLTAGE_MASK; +} + +/** + * @brief checkover ddr over voltage flag + * + * @param[in] ptr base address + * @retval true if flag is set + */ +static inline bool pcfg_ddr_dcdc_is_over_voltage(PCFG_Type *ptr) +{ + return PCFG_DCDCM_PROT_OVERVOLT_FLAG_GET(ptr->DCDCM_PROT); +} + +/** + * @brief disable ddr over current protection + * + * @param[in] ptr base address + */ +static inline void pcfg_ddr_dcdc_disable_over_current_prot(PCFG_Type *ptr) +{ + ptr->DCDCM_PROT |= PCFG_DCDCM_PROT_DISABLE_SHORT_MASK; +} + +/** + * @brief enable ddr over current protection + * + * @param[in] ptr base address + */ +static inline void pcfg_ddr_dcdc_enable_over_current_prot(PCFG_Type *ptr) +{ + ptr->DCDCM_PROT &= ~PCFG_DCDCM_PROT_DISABLE_SHORT_MASK; +} + +/** + * @brief set ddr over current limit + * + * @param[in] ptr base address + * @param[in] limit reference pcfg_dcdc_oc_limit_t + */ +static inline void pcfg_ddr_dcdc_set_over_current_limit(PCFG_Type *ptr, pcfg_dcdc_oc_limit_t limit) +{ + ptr->DCDCM_PROT = (ptr->DCDCM_PROT & ~PCFG_DCDCM_PROT_SHORT_CURRENT_MASK) | PCFG_DCDCM_PROT_SHORT_CURRENT_SET(limit); +} + +/** + * @brief checkover ddr over current flag + * + * @param[in] ptr base address + * @retval true if flag is set + */ +static inline bool pcfg_ddr_dcdc_is_over_current(PCFG_Type *ptr) +{ + return PCFG_DCDCM_PROT_SHORT_FLAG_GET(ptr->DCDCM_PROT); +} + +/** + * @brief disable ddr current measurement + * + * @param[in] ptr base address + */ +static inline void pcfg_ddr_dcdc_disable_measure_current(PCFG_Type *ptr) +{ + ptr->DCDCM_CURRENT &= ~PCFG_DCDCM_CURRENT_ESTI_EN_MASK; +} + +/** + * @brief enable ddr current measurement + * + * @param[in] ptr base address + */ +static inline void pcfg_ddr_dcdc_enable_measure_current(PCFG_Type *ptr) +{ + ptr->DCDCM_CURRENT |= PCFG_DCDCM_CURRENT_ESTI_EN_MASK; +} + +/** + * @brief check if measured ddr current is valid + * + * @param[in] ptr base address + * + * @retval true if measured ddr current is valid + */ +static inline bool pcfg_ddr_dcdc_is_measure_current_valid(PCFG_Type *ptr) +{ + return ptr->DCDCM_CURRENT & PCFG_DCDCM_CURRENT_VALID_MASK; +} + +/** + * @brief get measured ddr current level + * + * @param[in] ptr base address + * + * @retval measured ddr current, unit 50mA + */ +static inline bool pcfg_ddr_dcdc_get_measured_current_level(PCFG_Type *ptr) +{ + return PCFG_DCDCM_CURRENT_LEVEL_GET(ptr->DCDCM_CURRENT); +} + +/** + * @brief get ddr dcdc start time in number of 24MHz clock cycles + * + * @param[in] ptr base address + * + * @retval ddr dcdc start time in cycles + */ +static inline uint32_t pcfg_ddr_dcdc_get_start_time_in_cycle(PCFG_Type *ptr) +{ + return PCFG_DCDCM_START_TIME_START_TIME_GET(ptr->DCDCM_START_TIME); +} + +/** + * @brief get ddr dcdc resume time in number of 24MHz clock cycles + * + * @param[in] ptr base address + * + * @retval ddr dcdc resuem time in cycles + */ +static inline uint32_t pcfg_ddr_dcdc_get_resume_time_in_cycle(PCFG_Type *ptr) +{ + return PCFG_DCDCM_RESUME_TIME_RESUME_TIME_GET(ptr->DCDCM_RESUME_TIME); +} + +/** + * @brief set ddr dcdc start time in 24MHz clock cycles + * + * @param[in] ptr base address + * @param[in] cycles start time in cycles + */ +static inline void pcfg_ddr_dcdc_set_start_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) +{ + ptr->DCDCM_START_TIME = PCFG_DCDCM_START_TIME_START_TIME_SET(cycles); +} + +/** + * @brief set ddr dcdc resuem time in 24MHz clock cycles + * + * @param[in] ptr base address + * @param[in] cycles resume time in cycles + */ +static inline void pcfg_ddr_dcdc_set_resume_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) +{ + ptr->DCDCM_RESUME_TIME = PCFG_DCDCM_RESUME_TIME_RESUME_TIME_SET(cycles); +} + +/** + * @brief set ddr dcdc current hysteres range + * + * @param[in] ptr base address + * @param[in] range current hysteres range + */ +static inline void pcfg_ddr_dcdc_set_current_hys_range(PCFG_Type *ptr, pcfg_dcdc_current_hys_t range) +{ + ptr->DCDCM_MISC = (ptr->DCDCM_MISC & (~PCFG_DCDCM_MISC_OL_HYST_MASK)) | PCFG_DCDCM_MISC_OL_HYST_SET(range); +} + +/** + * @brief disable ddr dcdc retention + * + * @param[in] ptr base address + */ +static inline void pcfg_ddr_dcdc_disable_retention(PCFG_Type *ptr) +{ + ptr->DCDCM_POWER_CONFIG &= ~PCFG_DCDCM_POWER_CONFIG_RETENTION_MASK; +} + +/** + * @brief enable ddr dcdc retention to retain soc sram data + * + * @param[in] ptr base address + */ +static inline void pcfg_ddr_dcdc_enable_retention(PCFG_Type *ptr) +{ + ptr->DCDCM_POWER_CONFIG |= PCFG_DCDCM_POWER_CONFIG_RETENTION_MASK; +} + +/** + * @brief check if irc24m is trimmed + * + * @param[in] ptr base address + * + * @retval true if it is trimmed + */ +static inline bool pcfg_irc24m_is_trimmed(PCFG_Type *ptr) +{ + return ptr->RC24M & PCFG_RC24M_RC_TRIMMED_MASK; +} + +/** + * @brief reload irc24m trim value + * + * @param[in] ptr base address + */ +static inline void pcfg_irc24m_reload_trim(PCFG_Type *ptr) +{ + ptr->RC24M &= ~PCFG_RC24M_RC_TRIMMED_MASK; +} + +/** + * @brief config irc24m track + * + * @param[in] ptr base address + * @param[in] config config data + */ +void pcfg_irc24m_config_track(PCFG_Type *ptr, pcfg_irc24m_config_t *config); + +/* + * @brief set DCDC voltage at standby mode + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_dcdc_set_lpmode_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief set output voltage of LDO 2.5V in mV + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_ldo2p5_set_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief set DCDC voltage + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_dcdc_set_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief set output voltage of LDO 1V in mV + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_ldo1p1_set_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief get current DCDC current level in mA + * + * @param[in] ptr base address + * @retval Current level at mA + */ +uint16_t pcfg_dcdc_get_current_level(PCFG_Type *ptr); + + +#ifdef __cplusplus +} +#endif +/** + * @} + */ + +#endif /* HPM_PCFG_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_pcfg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_pcfg_regs.h new file mode 100644 index 00000000000..6ba4922766e --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_pcfg_regs.h @@ -0,0 +1,1363 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PCFG_H +#define HPM_PCFG_H + +typedef struct { + __RW uint32_t BANDGAP; /* 0x0: BANGGAP control */ + __RW uint32_t LDO1P1; /* 0x4: 1V LDO config */ + __RW uint32_t LDO2P5; /* 0x8: 2.5V LDO config */ + __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ + __RW uint32_t DCDC_MODE; /* 0x10: DCDC mode select */ + __RW uint32_t DCDC_LPMODE; /* 0x14: DCDC low power mode */ + __RW uint32_t DCDC_PROT; /* 0x18: DCDC protection */ + __RW uint32_t DCDC_CURRENT; /* 0x1C: DCDC current estimation */ + __RW uint32_t DCDC_ADVMODE; /* 0x20: DCDC advance setting */ + __RW uint32_t DCDC_ADVPARAM; /* 0x24: DCDC advance parameter */ + __RW uint32_t DCDC_MISC; /* 0x28: DCDC misc parameter */ + __RW uint32_t DCDC_DEBUG; /* 0x2C: DCDC Debug */ + __RW uint32_t DCDC_START_TIME; /* 0x30: DCDC ramp time */ + __RW uint32_t DCDC_RESUME_TIME; /* 0x34: DCDC resume time */ + __R uint8_t RESERVED1[8]; /* 0x38 - 0x3F: Reserved */ + __RW uint32_t POWER_TRAP; /* 0x40: power trap */ + __RW uint32_t WAKE_CAUSE; /* 0x44: Wake up source */ + __RW uint32_t WAKE_MASK; /* 0x48: Wake up mask */ + __RW uint32_t SCG_CTRL; /* 0x4C: Clock gate control in PMIC */ + __R uint8_t RESERVED2[16]; /* 0x50 - 0x5F: Reserved */ + __RW uint32_t RC24M; /* 0x60: RC 24M config */ + __RW uint32_t RC24M_TRACK; /* 0x64: RC 24M track mode */ + __RW uint32_t TRACK_TARGET; /* 0x68: RC 24M track target */ + __R uint32_t STATUS; /* 0x6C: RC 24M track status */ + __R uint8_t RESERVED3[16]; /* 0x70 - 0x7F: Reserved */ + __RW uint32_t DCDCM_MODE; /* 0x80: DCDCM mode select */ + __RW uint32_t DCDCM_LPMODE; /* 0x84: DCDCM low power mode */ + __RW uint32_t DCDCM_PROT; /* 0x88: DCDCM protection */ + __RW uint32_t DCDCM_CURRENT; /* 0x8C: DCDCM current estimation */ + __RW uint32_t DCDCM_ADVMODE; /* 0x90: DCDCM advance setting */ + __RW uint32_t DCDCM_ADVPARAM; /* 0x94: DCDCM advance parameter */ + __RW uint32_t DCDCM_MISC; /* 0x98: DCDCM misc parameter */ + __RW uint32_t DCDCM_DEBUG; /* 0x9C: DCDCM Debug */ + __RW uint32_t DCDCM_START_TIME; /* 0xA0: DCDCM ramp time */ + __RW uint32_t DCDCM_RESUME_TIME; /* 0xA4: DCDCM resume time */ + __RW uint32_t DCDCM_POWER_CONFIG; /* 0xA8: DCDCM power config */ +} PCFG_Type; + + +/* Bitfield definition for register: BANDGAP */ +/* + * VBG_TRIMMED (RW) + * + * Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value + * 0: bandgap is not trimmed + * 1: bandgap is trimmed + */ +#define PCFG_BANDGAP_VBG_TRIMMED_MASK (0x80000000UL) +#define PCFG_BANDGAP_VBG_TRIMMED_SHIFT (31U) +#define PCFG_BANDGAP_VBG_TRIMMED_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_TRIMMED_SHIFT) & PCFG_BANDGAP_VBG_TRIMMED_MASK) +#define PCFG_BANDGAP_VBG_TRIMMED_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_TRIMMED_MASK) >> PCFG_BANDGAP_VBG_TRIMMED_SHIFT) + +/* + * LOWPOWER_MODE (RW) + * + * Banggap work in low power mode, banggap function limited + * 0: banggap works in normal mode + * 1: banggap works in low power mode + */ +#define PCFG_BANDGAP_LOWPOWER_MODE_MASK (0x2000000UL) +#define PCFG_BANDGAP_LOWPOWER_MODE_SHIFT (25U) +#define PCFG_BANDGAP_LOWPOWER_MODE_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_LOWPOWER_MODE_SHIFT) & PCFG_BANDGAP_LOWPOWER_MODE_MASK) +#define PCFG_BANDGAP_LOWPOWER_MODE_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_LOWPOWER_MODE_MASK) >> PCFG_BANDGAP_LOWPOWER_MODE_SHIFT) + +/* + * POWER_SAVE (RW) + * + * Banggap work in power save mode, banggap function normally + * 0: banggap works in high performance mode + * 1: banggap works in power saving mode + */ +#define PCFG_BANDGAP_POWER_SAVE_MASK (0x1000000UL) +#define PCFG_BANDGAP_POWER_SAVE_SHIFT (24U) +#define PCFG_BANDGAP_POWER_SAVE_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_POWER_SAVE_SHIFT) & PCFG_BANDGAP_POWER_SAVE_MASK) +#define PCFG_BANDGAP_POWER_SAVE_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_POWER_SAVE_MASK) >> PCFG_BANDGAP_POWER_SAVE_SHIFT) + +/* + * VBG_1P0_TRIM (RW) + * + * Banggap 1.0V output trim value + */ +#define PCFG_BANDGAP_VBG_1P0_TRIM_MASK (0x1F0000UL) +#define PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT (16U) +#define PCFG_BANDGAP_VBG_1P0_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT) & PCFG_BANDGAP_VBG_1P0_TRIM_MASK) +#define PCFG_BANDGAP_VBG_1P0_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_1P0_TRIM_MASK) >> PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT) + +/* + * VBG_P65_TRIM (RW) + * + * Banggap 1.0V output trim value + */ +#define PCFG_BANDGAP_VBG_P65_TRIM_MASK (0x1F00U) +#define PCFG_BANDGAP_VBG_P65_TRIM_SHIFT (8U) +#define PCFG_BANDGAP_VBG_P65_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_P65_TRIM_SHIFT) & PCFG_BANDGAP_VBG_P65_TRIM_MASK) +#define PCFG_BANDGAP_VBG_P65_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_P65_TRIM_MASK) >> PCFG_BANDGAP_VBG_P65_TRIM_SHIFT) + +/* + * VBG_P50_TRIM (RW) + * + * Banggap 1.0V output trim value + */ +#define PCFG_BANDGAP_VBG_P50_TRIM_MASK (0x1FU) +#define PCFG_BANDGAP_VBG_P50_TRIM_SHIFT (0U) +#define PCFG_BANDGAP_VBG_P50_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) & PCFG_BANDGAP_VBG_P50_TRIM_MASK) +#define PCFG_BANDGAP_VBG_P50_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_P50_TRIM_MASK) >> PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) + +/* Bitfield definition for register: LDO1P1 */ +/* + * VOLT (RW) + * + * LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. + * 700: 700mV + * 720: 720mV + * . . . + * 1320:1320mV + */ +#define PCFG_LDO1P1_VOLT_MASK (0xFFFU) +#define PCFG_LDO1P1_VOLT_SHIFT (0U) +#define PCFG_LDO1P1_VOLT_SET(x) (((uint32_t)(x) << PCFG_LDO1P1_VOLT_SHIFT) & PCFG_LDO1P1_VOLT_MASK) +#define PCFG_LDO1P1_VOLT_GET(x) (((uint32_t)(x) & PCFG_LDO1P1_VOLT_MASK) >> PCFG_LDO1P1_VOLT_SHIFT) + +/* Bitfield definition for register: LDO2P5 */ +/* + * READY (RO) + * + * Ready flag, will set 1ms after enabled or voltage change + * 0: LDO is not ready for use + * 1: LDO is ready + */ +#define PCFG_LDO2P5_READY_MASK (0x10000000UL) +#define PCFG_LDO2P5_READY_SHIFT (28U) +#define PCFG_LDO2P5_READY_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_READY_MASK) >> PCFG_LDO2P5_READY_SHIFT) + +/* + * ENABLE (RW) + * + * LDO enable + * 0: turn off LDO + * 1: turn on LDO + */ +#define PCFG_LDO2P5_ENABLE_MASK (0x10000UL) +#define PCFG_LDO2P5_ENABLE_SHIFT (16U) +#define PCFG_LDO2P5_ENABLE_SET(x) (((uint32_t)(x) << PCFG_LDO2P5_ENABLE_SHIFT) & PCFG_LDO2P5_ENABLE_MASK) +#define PCFG_LDO2P5_ENABLE_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_ENABLE_MASK) >> PCFG_LDO2P5_ENABLE_SHIFT) + +/* + * VOLT (RW) + * + * LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. + * 2125: 2125mV + * 2150: 2150mV + * . . . + * 2900:2900mV + */ +#define PCFG_LDO2P5_VOLT_MASK (0xFFFU) +#define PCFG_LDO2P5_VOLT_SHIFT (0U) +#define PCFG_LDO2P5_VOLT_SET(x) (((uint32_t)(x) << PCFG_LDO2P5_VOLT_SHIFT) & PCFG_LDO2P5_VOLT_MASK) +#define PCFG_LDO2P5_VOLT_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_VOLT_MASK) >> PCFG_LDO2P5_VOLT_SHIFT) + +/* Bitfield definition for register: DCDC_MODE */ +/* + * READY (RO) + * + * Ready flag + * 0: DCDC is applying new change + * 1: DCDC is ready + */ +#define PCFG_DCDC_MODE_READY_MASK (0x10000000UL) +#define PCFG_DCDC_MODE_READY_SHIFT (28U) +#define PCFG_DCDC_MODE_READY_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_READY_MASK) >> PCFG_DCDC_MODE_READY_SHIFT) + +/* + * MODE (RW) + * + * DCDC work mode + * XX0: turn off + * 001: basic mode + * 011: generic mode + * 101: automatic mode + * 111: expert mode + */ +#define PCFG_DCDC_MODE_MODE_MASK (0x70000UL) +#define PCFG_DCDC_MODE_MODE_SHIFT (16U) +#define PCFG_DCDC_MODE_MODE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MODE_MODE_SHIFT) & PCFG_DCDC_MODE_MODE_MASK) +#define PCFG_DCDC_MODE_MODE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_MODE_MASK) >> PCFG_DCDC_MODE_MODE_SHIFT) + +/* + * VOLT (RW) + * + * DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. + * 600: 600mV + * 625: 625mV + * . . . + * 1375:1375mV + */ +#define PCFG_DCDC_MODE_VOLT_MASK (0xFFFU) +#define PCFG_DCDC_MODE_VOLT_SHIFT (0U) +#define PCFG_DCDC_MODE_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDC_MODE_VOLT_SHIFT) & PCFG_DCDC_MODE_VOLT_MASK) +#define PCFG_DCDC_MODE_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_VOLT_MASK) >> PCFG_DCDC_MODE_VOLT_SHIFT) + +/* Bitfield definition for register: DCDC_LPMODE */ +/* + * STBY_VOLT (RW) + * + * DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. + * 600: 600mV + * 625: 625mV + * . . . + * 1375:1375mV + */ +#define PCFG_DCDC_LPMODE_STBY_VOLT_MASK (0xFFFU) +#define PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT (0U) +#define PCFG_DCDC_LPMODE_STBY_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT) & PCFG_DCDC_LPMODE_STBY_VOLT_MASK) +#define PCFG_DCDC_LPMODE_STBY_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDC_LPMODE_STBY_VOLT_MASK) >> PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT) + +/* Bitfield definition for register: DCDC_PROT */ +/* + * ILIMIT_LP (RW) + * + * over current setting for low power mode + * 0:250mA + * 1:200mA + */ +#define PCFG_DCDC_PROT_ILIMIT_LP_MASK (0x10000000UL) +#define PCFG_DCDC_PROT_ILIMIT_LP_SHIFT (28U) +#define PCFG_DCDC_PROT_ILIMIT_LP_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) +#define PCFG_DCDC_PROT_ILIMIT_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) >> PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) + +/* + * OVERLOAD_LP (RO) + * + * over current in low power mode + * 0: current is below setting + * 1: overcurrent happened in low power mode + */ +#define PCFG_DCDC_PROT_OVERLOAD_LP_MASK (0x1000000UL) +#define PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT (24U) +#define PCFG_DCDC_PROT_OVERLOAD_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERLOAD_LP_MASK) >> PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT) + +/* + * DISABLE_POWER_LOSS (RW) + * + * disable power loss protection + * 0: power loss protection enabled, DCDC shuts down when power loss + * 1: power loss protection disabled, DCDC try working after power voltage drop + */ +#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK (0x800000UL) +#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SHIFT (23U) +#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SHIFT) & PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK) +#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK) >> PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SHIFT) + +/* + * POWER_LOSS_FLAG (RO) + * + * power loss + * 0: input power is good + * 1: input power is too low + */ +#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_MASK (0x10000UL) +#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_SHIFT (16U) +#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_POWER_LOSS_FLAG_MASK) >> PCFG_DCDC_PROT_POWER_LOSS_FLAG_SHIFT) + +/* + * DISABLE_OVERVOLTAGE (RW) + * + * output over voltage protection + * 0: protection enabled, DCDC will shut down is output voltage is unexpected high + * 1: protection disabled, DCDC continue to adjust output voltage + */ +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK (0x8000U) +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT (15U) +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT) & PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK) +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK) >> PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT) + +/* + * OVERVOLT_FLAG (RO) + * + * output over voltage flag + * 0: output is normal + * 1: output is unexpected high + */ +#define PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK (0x100U) +#define PCFG_DCDC_PROT_OVERVOLT_FLAG_SHIFT (8U) +#define PCFG_DCDC_PROT_OVERVOLT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK) >> PCFG_DCDC_PROT_OVERVOLT_FLAG_SHIFT) + +/* + * DISABLE_SHORT (RW) + * + * disable output short circuit protection + * 0: short circuits protection enabled, DCDC shut down if short circuit on output detected + * 1: short circuit protection disabled + */ +#define PCFG_DCDC_PROT_DISABLE_SHORT_MASK (0x80U) +#define PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT (7U) +#define PCFG_DCDC_PROT_DISABLE_SHORT_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT) & PCFG_DCDC_PROT_DISABLE_SHORT_MASK) +#define PCFG_DCDC_PROT_DISABLE_SHORT_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_SHORT_MASK) >> PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT) + +/* + * SHORT_CURRENT (RW) + * + * short circuit current setting + * 0: 2.0A, + * 1: 1.3A + */ +#define PCFG_DCDC_PROT_SHORT_CURRENT_MASK (0x10U) +#define PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT (4U) +#define PCFG_DCDC_PROT_SHORT_CURRENT_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT) & PCFG_DCDC_PROT_SHORT_CURRENT_MASK) +#define PCFG_DCDC_PROT_SHORT_CURRENT_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_SHORT_CURRENT_MASK) >> PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT) + +/* + * SHORT_FLAG (RO) + * + * short circuit flag + * 0: current is within limit + * 1: short circuits detected + */ +#define PCFG_DCDC_PROT_SHORT_FLAG_MASK (0x1U) +#define PCFG_DCDC_PROT_SHORT_FLAG_SHIFT (0U) +#define PCFG_DCDC_PROT_SHORT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_SHORT_FLAG_MASK) >> PCFG_DCDC_PROT_SHORT_FLAG_SHIFT) + +/* Bitfield definition for register: DCDC_CURRENT */ +/* + * ESTI_EN (RW) + * + * enable current measure + */ +#define PCFG_DCDC_CURRENT_ESTI_EN_MASK (0x8000U) +#define PCFG_DCDC_CURRENT_ESTI_EN_SHIFT (15U) +#define PCFG_DCDC_CURRENT_ESTI_EN_SET(x) (((uint32_t)(x) << PCFG_DCDC_CURRENT_ESTI_EN_SHIFT) & PCFG_DCDC_CURRENT_ESTI_EN_MASK) +#define PCFG_DCDC_CURRENT_ESTI_EN_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_ESTI_EN_MASK) >> PCFG_DCDC_CURRENT_ESTI_EN_SHIFT) + +/* + * VALID (RO) + * + * Current level valid + * 0: data is invalid + * 1: data is valid + */ +#define PCFG_DCDC_CURRENT_VALID_MASK (0x100U) +#define PCFG_DCDC_CURRENT_VALID_SHIFT (8U) +#define PCFG_DCDC_CURRENT_VALID_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_VALID_MASK) >> PCFG_DCDC_CURRENT_VALID_SHIFT) + +/* + * LEVEL (RO) + * + * DCDC current level, current level is num * 50mA + */ +#define PCFG_DCDC_CURRENT_LEVEL_MASK (0x1FU) +#define PCFG_DCDC_CURRENT_LEVEL_SHIFT (0U) +#define PCFG_DCDC_CURRENT_LEVEL_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_LEVEL_MASK) >> PCFG_DCDC_CURRENT_LEVEL_SHIFT) + +/* Bitfield definition for register: DCDC_ADVMODE */ +/* + * EN_RCSCALE (RW) + * + * Enable RC scale + */ +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK (0x7000000UL) +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT (24U) +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT) & PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK) +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK) >> PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT) + +/* + * DC_C (RW) + * + * Loop C number + */ +#define PCFG_DCDC_ADVMODE_DC_C_MASK (0x300000UL) +#define PCFG_DCDC_ADVMODE_DC_C_SHIFT (20U) +#define PCFG_DCDC_ADVMODE_DC_C_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_DC_C_SHIFT) & PCFG_DCDC_ADVMODE_DC_C_MASK) +#define PCFG_DCDC_ADVMODE_DC_C_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_DC_C_MASK) >> PCFG_DCDC_ADVMODE_DC_C_SHIFT) + +/* + * DC_R (RW) + * + * Loop R number + */ +#define PCFG_DCDC_ADVMODE_DC_R_MASK (0xF0000UL) +#define PCFG_DCDC_ADVMODE_DC_R_SHIFT (16U) +#define PCFG_DCDC_ADVMODE_DC_R_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_DC_R_SHIFT) & PCFG_DCDC_ADVMODE_DC_R_MASK) +#define PCFG_DCDC_ADVMODE_DC_R_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_DC_R_MASK) >> PCFG_DCDC_ADVMODE_DC_R_SHIFT) + +/* + * EN_FF_DET (RW) + * + * enable feed forward detect + * 0: feed forward detect is disabled + * 1: feed forward detect is enabled + */ +#define PCFG_DCDC_ADVMODE_EN_FF_DET_MASK (0x40U) +#define PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT (6U) +#define PCFG_DCDC_ADVMODE_EN_FF_DET_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT) & PCFG_DCDC_ADVMODE_EN_FF_DET_MASK) +#define PCFG_DCDC_ADVMODE_EN_FF_DET_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_FF_DET_MASK) >> PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT) + +/* + * EN_FF_LOOP (RW) + * + * enable feed forward loop + * 0: feed forward loop is disabled + * 1: feed forward loop is enabled + */ +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK (0x20U) +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT (5U) +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) >> PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) + +/* + * EN_DCM_EXIT (RW) + * + * avoid over voltage + * 0: stay in DCM mode when voltage excess + * 1: change to CCM mode when voltage excess + */ +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK (0x8U) +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT (3U) +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT) & PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK) +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK) >> PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT) + +/* + * EN_SKIP (RW) + * + * enable skip on narrow pulse + * 0: do not skip narrow pulse + * 1: skip narrow pulse + */ +#define PCFG_DCDC_ADVMODE_EN_SKIP_MASK (0x4U) +#define PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT (2U) +#define PCFG_DCDC_ADVMODE_EN_SKIP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT) & PCFG_DCDC_ADVMODE_EN_SKIP_MASK) +#define PCFG_DCDC_ADVMODE_EN_SKIP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_SKIP_MASK) >> PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT) + +/* + * EN_IDLE (RW) + * + * enable skip when voltage is higher than threshold + * 0: do not skip + * 1: skip if voltage is excess + */ +#define PCFG_DCDC_ADVMODE_EN_IDLE_MASK (0x2U) +#define PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT (1U) +#define PCFG_DCDC_ADVMODE_EN_IDLE_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT) & PCFG_DCDC_ADVMODE_EN_IDLE_MASK) +#define PCFG_DCDC_ADVMODE_EN_IDLE_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_IDLE_MASK) >> PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT) + +/* + * EN_DCM (RW) + * + * DCM mode + * 0: CCM mode + * 1: DCM mode + */ +#define PCFG_DCDC_ADVMODE_EN_DCM_MASK (0x1U) +#define PCFG_DCDC_ADVMODE_EN_DCM_SHIFT (0U) +#define PCFG_DCDC_ADVMODE_EN_DCM_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_DCM_SHIFT) & PCFG_DCDC_ADVMODE_EN_DCM_MASK) +#define PCFG_DCDC_ADVMODE_EN_DCM_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_DCM_MASK) >> PCFG_DCDC_ADVMODE_EN_DCM_SHIFT) + +/* Bitfield definition for register: DCDC_ADVPARAM */ +/* + * MIN_DUT (RW) + * + * minimum duty cycle + */ +#define PCFG_DCDC_ADVPARAM_MIN_DUT_MASK (0x7F00U) +#define PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT (8U) +#define PCFG_DCDC_ADVPARAM_MIN_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT) & PCFG_DCDC_ADVPARAM_MIN_DUT_MASK) +#define PCFG_DCDC_ADVPARAM_MIN_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVPARAM_MIN_DUT_MASK) >> PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT) + +/* + * MAX_DUT (RW) + * + * maximum duty cycle + */ +#define PCFG_DCDC_ADVPARAM_MAX_DUT_MASK (0x7FU) +#define PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT (0U) +#define PCFG_DCDC_ADVPARAM_MAX_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT) & PCFG_DCDC_ADVPARAM_MAX_DUT_MASK) +#define PCFG_DCDC_ADVPARAM_MAX_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVPARAM_MAX_DUT_MASK) >> PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT) + +/* Bitfield definition for register: DCDC_MISC */ +/* + * EN_HYST (RW) + * + * hysteres enable + */ +#define PCFG_DCDC_MISC_EN_HYST_MASK (0x10000000UL) +#define PCFG_DCDC_MISC_EN_HYST_SHIFT (28U) +#define PCFG_DCDC_MISC_EN_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_EN_HYST_SHIFT) & PCFG_DCDC_MISC_EN_HYST_MASK) +#define PCFG_DCDC_MISC_EN_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_EN_HYST_MASK) >> PCFG_DCDC_MISC_EN_HYST_SHIFT) + +/* + * HYST_SIGN (RW) + * + * hysteres sign + */ +#define PCFG_DCDC_MISC_HYST_SIGN_MASK (0x2000000UL) +#define PCFG_DCDC_MISC_HYST_SIGN_SHIFT (25U) +#define PCFG_DCDC_MISC_HYST_SIGN_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_HYST_SIGN_SHIFT) & PCFG_DCDC_MISC_HYST_SIGN_MASK) +#define PCFG_DCDC_MISC_HYST_SIGN_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_HYST_SIGN_MASK) >> PCFG_DCDC_MISC_HYST_SIGN_SHIFT) + +/* + * HYST_THRS (RW) + * + * hysteres threshold + */ +#define PCFG_DCDC_MISC_HYST_THRS_MASK (0x1000000UL) +#define PCFG_DCDC_MISC_HYST_THRS_SHIFT (24U) +#define PCFG_DCDC_MISC_HYST_THRS_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_HYST_THRS_SHIFT) & PCFG_DCDC_MISC_HYST_THRS_MASK) +#define PCFG_DCDC_MISC_HYST_THRS_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_HYST_THRS_MASK) >> PCFG_DCDC_MISC_HYST_THRS_SHIFT) + +/* + * RC_SCALE (RW) + * + * Loop RC scale threshold + */ +#define PCFG_DCDC_MISC_RC_SCALE_MASK (0x100000UL) +#define PCFG_DCDC_MISC_RC_SCALE_SHIFT (20U) +#define PCFG_DCDC_MISC_RC_SCALE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_RC_SCALE_SHIFT) & PCFG_DCDC_MISC_RC_SCALE_MASK) +#define PCFG_DCDC_MISC_RC_SCALE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_RC_SCALE_MASK) >> PCFG_DCDC_MISC_RC_SCALE_SHIFT) + +/* + * DC_FF (RW) + * + * Loop feed forward number + */ +#define PCFG_DCDC_MISC_DC_FF_MASK (0x70000UL) +#define PCFG_DCDC_MISC_DC_FF_SHIFT (16U) +#define PCFG_DCDC_MISC_DC_FF_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_DC_FF_SHIFT) & PCFG_DCDC_MISC_DC_FF_MASK) +#define PCFG_DCDC_MISC_DC_FF_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_DC_FF_MASK) >> PCFG_DCDC_MISC_DC_FF_SHIFT) + +/* + * OL_THRE (RW) + * + * overload for threshold for lod power mode + */ +#define PCFG_DCDC_MISC_OL_THRE_MASK (0x300U) +#define PCFG_DCDC_MISC_OL_THRE_SHIFT (8U) +#define PCFG_DCDC_MISC_OL_THRE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_OL_THRE_SHIFT) & PCFG_DCDC_MISC_OL_THRE_MASK) +#define PCFG_DCDC_MISC_OL_THRE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_OL_THRE_MASK) >> PCFG_DCDC_MISC_OL_THRE_SHIFT) + +/* + * OL_HYST (RW) + * + * current hysteres range + * 0: 12.5mV + * 1: 25mV + */ +#define PCFG_DCDC_MISC_OL_HYST_MASK (0x10U) +#define PCFG_DCDC_MISC_OL_HYST_SHIFT (4U) +#define PCFG_DCDC_MISC_OL_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_OL_HYST_SHIFT) & PCFG_DCDC_MISC_OL_HYST_MASK) +#define PCFG_DCDC_MISC_OL_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_OL_HYST_MASK) >> PCFG_DCDC_MISC_OL_HYST_SHIFT) + +/* + * DELAY (RW) + * + * enable delay + * 0: delay disabled, + * 1: delay enabled + */ +#define PCFG_DCDC_MISC_DELAY_MASK (0x4U) +#define PCFG_DCDC_MISC_DELAY_SHIFT (2U) +#define PCFG_DCDC_MISC_DELAY_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_DELAY_SHIFT) & PCFG_DCDC_MISC_DELAY_MASK) +#define PCFG_DCDC_MISC_DELAY_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_DELAY_MASK) >> PCFG_DCDC_MISC_DELAY_SHIFT) + +/* + * CLK_SEL (RW) + * + * clock selection + * 0: select DCDC internal oscillator + * 1: select RC24M oscillator + */ +#define PCFG_DCDC_MISC_CLK_SEL_MASK (0x2U) +#define PCFG_DCDC_MISC_CLK_SEL_SHIFT (1U) +#define PCFG_DCDC_MISC_CLK_SEL_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_CLK_SEL_SHIFT) & PCFG_DCDC_MISC_CLK_SEL_MASK) +#define PCFG_DCDC_MISC_CLK_SEL_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_CLK_SEL_MASK) >> PCFG_DCDC_MISC_CLK_SEL_SHIFT) + +/* + * EN_STEP (RW) + * + * enable stepping in voltage change + * 0: stepping disabled, + * 1: steping enabled + */ +#define PCFG_DCDC_MISC_EN_STEP_MASK (0x1U) +#define PCFG_DCDC_MISC_EN_STEP_SHIFT (0U) +#define PCFG_DCDC_MISC_EN_STEP_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_EN_STEP_SHIFT) & PCFG_DCDC_MISC_EN_STEP_MASK) +#define PCFG_DCDC_MISC_EN_STEP_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_EN_STEP_MASK) >> PCFG_DCDC_MISC_EN_STEP_SHIFT) + +/* Bitfield definition for register: DCDC_DEBUG */ +/* + * UPDATE_TIME (RW) + * + * DCDC voltage change time in 24M clock cycles, default value is 1mS + */ +#define PCFG_DCDC_DEBUG_UPDATE_TIME_MASK (0xFFFFFUL) +#define PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT (0U) +#define PCFG_DCDC_DEBUG_UPDATE_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT) & PCFG_DCDC_DEBUG_UPDATE_TIME_MASK) +#define PCFG_DCDC_DEBUG_UPDATE_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_DEBUG_UPDATE_TIME_MASK) >> PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT) + +/* Bitfield definition for register: DCDC_START_TIME */ +/* + * START_TIME (RW) + * + * Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS + */ +#define PCFG_DCDC_START_TIME_START_TIME_MASK (0xFFFFFUL) +#define PCFG_DCDC_START_TIME_START_TIME_SHIFT (0U) +#define PCFG_DCDC_START_TIME_START_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_START_TIME_START_TIME_SHIFT) & PCFG_DCDC_START_TIME_START_TIME_MASK) +#define PCFG_DCDC_START_TIME_START_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_START_TIME_START_TIME_MASK) >> PCFG_DCDC_START_TIME_START_TIME_SHIFT) + +/* Bitfield definition for register: DCDC_RESUME_TIME */ +/* + * RESUME_TIME (RW) + * + * Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS + */ +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK (0xFFFFFUL) +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT (0U) +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT) & PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK) +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK) >> PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT) + +/* Bitfield definition for register: POWER_TRAP */ +/* + * TRIGGERED (RW) + * + * Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. + * 0: low power trap is not triggered + * 1: low power trap triggered + */ +#define PCFG_POWER_TRAP_TRIGGERED_MASK (0x80000000UL) +#define PCFG_POWER_TRAP_TRIGGERED_SHIFT (31U) +#define PCFG_POWER_TRAP_TRIGGERED_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_TRIGGERED_SHIFT) & PCFG_POWER_TRAP_TRIGGERED_MASK) +#define PCFG_POWER_TRAP_TRIGGERED_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_TRIGGERED_MASK) >> PCFG_POWER_TRAP_TRIGGERED_SHIFT) + +/* + * RETENTION (RW) + * + * DCDC enter standby mode, which will reduce voltage for memory content retention + * 0: Shutdown DCDC + * 1: reduce DCDC voltage + */ +#define PCFG_POWER_TRAP_RETENTION_MASK (0x10000UL) +#define PCFG_POWER_TRAP_RETENTION_SHIFT (16U) +#define PCFG_POWER_TRAP_RETENTION_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_RETENTION_SHIFT) & PCFG_POWER_TRAP_RETENTION_MASK) +#define PCFG_POWER_TRAP_RETENTION_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_RETENTION_MASK) >> PCFG_POWER_TRAP_RETENTION_SHIFT) + +/* + * TRAP (RW) + * + * Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered + * 0: trap not enabled, pmic side low power function disabled + * 1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. + */ +#define PCFG_POWER_TRAP_TRAP_MASK (0x1U) +#define PCFG_POWER_TRAP_TRAP_SHIFT (0U) +#define PCFG_POWER_TRAP_TRAP_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_TRAP_SHIFT) & PCFG_POWER_TRAP_TRAP_MASK) +#define PCFG_POWER_TRAP_TRAP_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_TRAP_MASK) >> PCFG_POWER_TRAP_TRAP_SHIFT) + +/* Bitfield definition for register: WAKE_CAUSE */ +/* + * CAUSE (RW) + * + * wake up cause, each bit represents one wake up source, write 1 to clear the register bit + * 0: wake up source is not active during last wakeup + * 1: wake up source is active furing last wakeup + * bit 0: pmic_enable + * bit 5: VAD interrupt + * bit 6: VAD wake interrupt + * bit 7: UART interrupt + * bit 8: TMR interrupt + * bit 9: WDG interrupt + * bit10: GPIO in PMIC interrupt + * bit16: Security violation in BATT + * bit17: GPIO in BATT interrupt + * bit19: RTC alarm interrupt + */ +#define PCFG_WAKE_CAUSE_CAUSE_MASK (0xFFFFFFFFUL) +#define PCFG_WAKE_CAUSE_CAUSE_SHIFT (0U) +#define PCFG_WAKE_CAUSE_CAUSE_SET(x) (((uint32_t)(x) << PCFG_WAKE_CAUSE_CAUSE_SHIFT) & PCFG_WAKE_CAUSE_CAUSE_MASK) +#define PCFG_WAKE_CAUSE_CAUSE_GET(x) (((uint32_t)(x) & PCFG_WAKE_CAUSE_CAUSE_MASK) >> PCFG_WAKE_CAUSE_CAUSE_SHIFT) + +/* Bitfield definition for register: WAKE_MASK */ +/* + * MASK (RW) + * + * mask for wake up sources, each bit represents one wakeup source + * 0: allow source to wake up system + * 1: disallow source to wakeup system + * bit 0: pmic_enable + * bit 5: VAD interrupt + * bit 6: VAD wake interrupt + * bit 7: UART interrupt + * bit 8: TMR interrupt + * bit 9: WDG interrupt + * bit10: GPIO in PMIC interrupt + * bit16: Security violation in BATT + * bit17: GPIO in BATT interrupt + * bit19: RTC alarm interrupt + */ +#define PCFG_WAKE_MASK_MASK_MASK (0xFFFFFFFFUL) +#define PCFG_WAKE_MASK_MASK_SHIFT (0U) +#define PCFG_WAKE_MASK_MASK_SET(x) (((uint32_t)(x) << PCFG_WAKE_MASK_MASK_SHIFT) & PCFG_WAKE_MASK_MASK_MASK) +#define PCFG_WAKE_MASK_MASK_GET(x) (((uint32_t)(x) & PCFG_WAKE_MASK_MASK_MASK) >> PCFG_WAKE_MASK_MASK_SHIFT) + +/* Bitfield definition for register: SCG_CTRL */ +/* + * SCG (RW) + * + * control whether clock being gated during PMIC low power flow, 2 bits for each peripheral + * 00,01: reserved + * 10: clock is always off + * 11: clock is always on + * bit6-7:gpio + * bit8-9:ioc + * bit10-11: timer + * bit12-13:wdog + * bit14-15:uart + * bit16-17:VAD + * bit18-19:SRAM + */ +#define PCFG_SCG_CTRL_SCG_MASK (0xFFFFFFFFUL) +#define PCFG_SCG_CTRL_SCG_SHIFT (0U) +#define PCFG_SCG_CTRL_SCG_SET(x) (((uint32_t)(x) << PCFG_SCG_CTRL_SCG_SHIFT) & PCFG_SCG_CTRL_SCG_MASK) +#define PCFG_SCG_CTRL_SCG_GET(x) (((uint32_t)(x) & PCFG_SCG_CTRL_SCG_MASK) >> PCFG_SCG_CTRL_SCG_SHIFT) + +/* Bitfield definition for register: RC24M */ +/* + * RC_TRIMMED (RW) + * + * RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value + * 0: RC is not trimmed + * 1: RC is trimmed + */ +#define PCFG_RC24M_RC_TRIMMED_MASK (0x80000000UL) +#define PCFG_RC24M_RC_TRIMMED_SHIFT (31U) +#define PCFG_RC24M_RC_TRIMMED_SET(x) (((uint32_t)(x) << PCFG_RC24M_RC_TRIMMED_SHIFT) & PCFG_RC24M_RC_TRIMMED_MASK) +#define PCFG_RC24M_RC_TRIMMED_GET(x) (((uint32_t)(x) & PCFG_RC24M_RC_TRIMMED_MASK) >> PCFG_RC24M_RC_TRIMMED_SHIFT) + +/* + * TRIM_C (RW) + * + * Coarse trim for RC24M, bigger value means faster + */ +#define PCFG_RC24M_TRIM_C_MASK (0x700U) +#define PCFG_RC24M_TRIM_C_SHIFT (8U) +#define PCFG_RC24M_TRIM_C_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRIM_C_SHIFT) & PCFG_RC24M_TRIM_C_MASK) +#define PCFG_RC24M_TRIM_C_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRIM_C_MASK) >> PCFG_RC24M_TRIM_C_SHIFT) + +/* + * TRIM_F (RW) + * + * Fine trim for RC24M, bigger value means faster + */ +#define PCFG_RC24M_TRIM_F_MASK (0x1FU) +#define PCFG_RC24M_TRIM_F_SHIFT (0U) +#define PCFG_RC24M_TRIM_F_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRIM_F_SHIFT) & PCFG_RC24M_TRIM_F_MASK) +#define PCFG_RC24M_TRIM_F_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRIM_F_MASK) >> PCFG_RC24M_TRIM_F_SHIFT) + +/* Bitfield definition for register: RC24M_TRACK */ +/* + * SEL24M (RW) + * + * Select track reference + * 0: select 32K as reference + * 1: select 24M XTAL as reference + */ +#define PCFG_RC24M_TRACK_SEL24M_MASK (0x10000UL) +#define PCFG_RC24M_TRACK_SEL24M_SHIFT (16U) +#define PCFG_RC24M_TRACK_SEL24M_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_SEL24M_SHIFT) & PCFG_RC24M_TRACK_SEL24M_MASK) +#define PCFG_RC24M_TRACK_SEL24M_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_SEL24M_MASK) >> PCFG_RC24M_TRACK_SEL24M_SHIFT) + +/* + * RETURN (RW) + * + * Retrun default value when XTAL loss + * 0: remain last tracking value + * 1: switch to default value + */ +#define PCFG_RC24M_TRACK_RETURN_MASK (0x10U) +#define PCFG_RC24M_TRACK_RETURN_SHIFT (4U) +#define PCFG_RC24M_TRACK_RETURN_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_RETURN_SHIFT) & PCFG_RC24M_TRACK_RETURN_MASK) +#define PCFG_RC24M_TRACK_RETURN_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_RETURN_MASK) >> PCFG_RC24M_TRACK_RETURN_SHIFT) + +/* + * TRACK (RW) + * + * track mode + * 0: RC24M free running + * 1: track RC24M to external XTAL + */ +#define PCFG_RC24M_TRACK_TRACK_MASK (0x1U) +#define PCFG_RC24M_TRACK_TRACK_SHIFT (0U) +#define PCFG_RC24M_TRACK_TRACK_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_TRACK_SHIFT) & PCFG_RC24M_TRACK_TRACK_MASK) +#define PCFG_RC24M_TRACK_TRACK_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_TRACK_MASK) >> PCFG_RC24M_TRACK_TRACK_SHIFT) + +/* Bitfield definition for register: TRACK_TARGET */ +/* + * PRE_DIV (RW) + * + * Divider for reference source + */ +#define PCFG_TRACK_TARGET_PRE_DIV_MASK (0xFFFF0000UL) +#define PCFG_TRACK_TARGET_PRE_DIV_SHIFT (16U) +#define PCFG_TRACK_TARGET_PRE_DIV_SET(x) (((uint32_t)(x) << PCFG_TRACK_TARGET_PRE_DIV_SHIFT) & PCFG_TRACK_TARGET_PRE_DIV_MASK) +#define PCFG_TRACK_TARGET_PRE_DIV_GET(x) (((uint32_t)(x) & PCFG_TRACK_TARGET_PRE_DIV_MASK) >> PCFG_TRACK_TARGET_PRE_DIV_SHIFT) + +/* + * TARGET (RW) + * + * Target frequency multiplier of divided source + */ +#define PCFG_TRACK_TARGET_TARGET_MASK (0xFFFFU) +#define PCFG_TRACK_TARGET_TARGET_SHIFT (0U) +#define PCFG_TRACK_TARGET_TARGET_SET(x) (((uint32_t)(x) << PCFG_TRACK_TARGET_TARGET_SHIFT) & PCFG_TRACK_TARGET_TARGET_MASK) +#define PCFG_TRACK_TARGET_TARGET_GET(x) (((uint32_t)(x) & PCFG_TRACK_TARGET_TARGET_MASK) >> PCFG_TRACK_TARGET_TARGET_SHIFT) + +/* Bitfield definition for register: STATUS */ +/* + * SEL32K (RO) + * + * track is using XTAL32K + * 0: track is not using XTAL32K + * 1: track is using XTAL32K + */ +#define PCFG_STATUS_SEL32K_MASK (0x100000UL) +#define PCFG_STATUS_SEL32K_SHIFT (20U) +#define PCFG_STATUS_SEL32K_GET(x) (((uint32_t)(x) & PCFG_STATUS_SEL32K_MASK) >> PCFG_STATUS_SEL32K_SHIFT) + +/* + * SEL24M (RO) + * + * track is using XTAL24M + * 0: track is not using XTAL24M + * 1: track is using XTAL24M + */ +#define PCFG_STATUS_SEL24M_MASK (0x10000UL) +#define PCFG_STATUS_SEL24M_SHIFT (16U) +#define PCFG_STATUS_SEL24M_GET(x) (((uint32_t)(x) & PCFG_STATUS_SEL24M_MASK) >> PCFG_STATUS_SEL24M_SHIFT) + +/* + * EN_TRIM (RO) + * + * default value takes effect + * 0: default value is invalid + * 1: default value is valid + */ +#define PCFG_STATUS_EN_TRIM_MASK (0x8000U) +#define PCFG_STATUS_EN_TRIM_SHIFT (15U) +#define PCFG_STATUS_EN_TRIM_GET(x) (((uint32_t)(x) & PCFG_STATUS_EN_TRIM_MASK) >> PCFG_STATUS_EN_TRIM_SHIFT) + +/* + * TRIM_C (RO) + * + * default coarse trim value + */ +#define PCFG_STATUS_TRIM_C_MASK (0x700U) +#define PCFG_STATUS_TRIM_C_SHIFT (8U) +#define PCFG_STATUS_TRIM_C_GET(x) (((uint32_t)(x) & PCFG_STATUS_TRIM_C_MASK) >> PCFG_STATUS_TRIM_C_SHIFT) + +/* + * TRIM_F (RO) + * + * default fine trim value + */ +#define PCFG_STATUS_TRIM_F_MASK (0x1FU) +#define PCFG_STATUS_TRIM_F_SHIFT (0U) +#define PCFG_STATUS_TRIM_F_GET(x) (((uint32_t)(x) & PCFG_STATUS_TRIM_F_MASK) >> PCFG_STATUS_TRIM_F_SHIFT) + +/* Bitfield definition for register: DCDCM_MODE */ +/* + * READY (RO) + * + * Ready flag + * 0: DCDCM is applying new change + * 1: DCDCM is ready + */ +#define PCFG_DCDCM_MODE_READY_MASK (0x10000000UL) +#define PCFG_DCDCM_MODE_READY_SHIFT (28U) +#define PCFG_DCDCM_MODE_READY_GET(x) (((uint32_t)(x) & PCFG_DCDCM_MODE_READY_MASK) >> PCFG_DCDCM_MODE_READY_SHIFT) + +/* + * MODE (RW) + * + * DCDCM work mode + * XX0: turn off + * 001: basic mode + * 011: generic mode + * 101: automatic mode + * 111: expert mode + */ +#define PCFG_DCDCM_MODE_MODE_MASK (0x70000UL) +#define PCFG_DCDCM_MODE_MODE_SHIFT (16U) +#define PCFG_DCDCM_MODE_MODE_SET(x) (((uint32_t)(x) << PCFG_DCDCM_MODE_MODE_SHIFT) & PCFG_DCDCM_MODE_MODE_MASK) +#define PCFG_DCDCM_MODE_MODE_GET(x) (((uint32_t)(x) & PCFG_DCDCM_MODE_MODE_MASK) >> PCFG_DCDCM_MODE_MODE_SHIFT) + +/* + * VOLT (RW) + * + * DCDCM voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. + * 600: 600mV + * 625: 625mV + * . . . + * 1375:1375mV + */ +#define PCFG_DCDCM_MODE_VOLT_MASK (0xFFFU) +#define PCFG_DCDCM_MODE_VOLT_SHIFT (0U) +#define PCFG_DCDCM_MODE_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDCM_MODE_VOLT_SHIFT) & PCFG_DCDCM_MODE_VOLT_MASK) +#define PCFG_DCDCM_MODE_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDCM_MODE_VOLT_MASK) >> PCFG_DCDCM_MODE_VOLT_SHIFT) + +/* Bitfield definition for register: DCDCM_LPMODE */ +/* + * STBY_VOLT (RW) + * + * DCDCM voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. + * 600: 600mV + * 625: 625mV + * . . . + * 1375:1375mV + */ +#define PCFG_DCDCM_LPMODE_STBY_VOLT_MASK (0xFFFU) +#define PCFG_DCDCM_LPMODE_STBY_VOLT_SHIFT (0U) +#define PCFG_DCDCM_LPMODE_STBY_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDCM_LPMODE_STBY_VOLT_SHIFT) & PCFG_DCDCM_LPMODE_STBY_VOLT_MASK) +#define PCFG_DCDCM_LPMODE_STBY_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDCM_LPMODE_STBY_VOLT_MASK) >> PCFG_DCDCM_LPMODE_STBY_VOLT_SHIFT) + +/* Bitfield definition for register: DCDCM_PROT */ +/* + * ILIMIT_LP (RW) + * + * over current setting for low power mode + * 0:250mA + * 1:200mA + */ +#define PCFG_DCDCM_PROT_ILIMIT_LP_MASK (0x10000000UL) +#define PCFG_DCDCM_PROT_ILIMIT_LP_SHIFT (28U) +#define PCFG_DCDCM_PROT_ILIMIT_LP_SET(x) (((uint32_t)(x) << PCFG_DCDCM_PROT_ILIMIT_LP_SHIFT) & PCFG_DCDCM_PROT_ILIMIT_LP_MASK) +#define PCFG_DCDCM_PROT_ILIMIT_LP_GET(x) (((uint32_t)(x) & PCFG_DCDCM_PROT_ILIMIT_LP_MASK) >> PCFG_DCDCM_PROT_ILIMIT_LP_SHIFT) + +/* + * OVERLOAD_LP (RO) + * + * over current in low power mode + * 0: current is below setting + * 1: overcurrent happened in low power mode + */ +#define PCFG_DCDCM_PROT_OVERLOAD_LP_MASK (0x1000000UL) +#define PCFG_DCDCM_PROT_OVERLOAD_LP_SHIFT (24U) +#define PCFG_DCDCM_PROT_OVERLOAD_LP_GET(x) (((uint32_t)(x) & PCFG_DCDCM_PROT_OVERLOAD_LP_MASK) >> PCFG_DCDCM_PROT_OVERLOAD_LP_SHIFT) + +/* + * DISABLE_POWER_LOSS (RW) + * + * disable power loss protection + * 0: power loss protection enabled, DCDCM shuts down when power loss + * 1: power loss protection disabled, DCDCM try working after power voltage drop + */ +#define PCFG_DCDCM_PROT_DISABLE_POWER_LOSS_MASK (0x800000UL) +#define PCFG_DCDCM_PROT_DISABLE_POWER_LOSS_SHIFT (23U) +#define PCFG_DCDCM_PROT_DISABLE_POWER_LOSS_SET(x) (((uint32_t)(x) << PCFG_DCDCM_PROT_DISABLE_POWER_LOSS_SHIFT) & PCFG_DCDCM_PROT_DISABLE_POWER_LOSS_MASK) +#define PCFG_DCDCM_PROT_DISABLE_POWER_LOSS_GET(x) (((uint32_t)(x) & PCFG_DCDCM_PROT_DISABLE_POWER_LOSS_MASK) >> PCFG_DCDCM_PROT_DISABLE_POWER_LOSS_SHIFT) + +/* + * POWER_LOSS_FLAG (RO) + * + * power loss + * 0: input power is good + * 1: input power is too low + */ +#define PCFG_DCDCM_PROT_POWER_LOSS_FLAG_MASK (0x10000UL) +#define PCFG_DCDCM_PROT_POWER_LOSS_FLAG_SHIFT (16U) +#define PCFG_DCDCM_PROT_POWER_LOSS_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDCM_PROT_POWER_LOSS_FLAG_MASK) >> PCFG_DCDCM_PROT_POWER_LOSS_FLAG_SHIFT) + +/* + * DISABLE_OVERVOLTAGE (RW) + * + * output over voltage protection + * 0: protection enabled, DCDCM will shut down is output voltage is unexpected high + * 1: protection disabled, DCDCM continue to adjust output voltage + */ +#define PCFG_DCDCM_PROT_DISABLE_OVERVOLTAGE_MASK (0x8000U) +#define PCFG_DCDCM_PROT_DISABLE_OVERVOLTAGE_SHIFT (15U) +#define PCFG_DCDCM_PROT_DISABLE_OVERVOLTAGE_SET(x) (((uint32_t)(x) << PCFG_DCDCM_PROT_DISABLE_OVERVOLTAGE_SHIFT) & PCFG_DCDCM_PROT_DISABLE_OVERVOLTAGE_MASK) +#define PCFG_DCDCM_PROT_DISABLE_OVERVOLTAGE_GET(x) (((uint32_t)(x) & PCFG_DCDCM_PROT_DISABLE_OVERVOLTAGE_MASK) >> PCFG_DCDCM_PROT_DISABLE_OVERVOLTAGE_SHIFT) + +/* + * OVERVOLT_FLAG (RO) + * + * output over voltage flag + * 0: output is normal + * 1: output is unexpected high + */ +#define PCFG_DCDCM_PROT_OVERVOLT_FLAG_MASK (0x100U) +#define PCFG_DCDCM_PROT_OVERVOLT_FLAG_SHIFT (8U) +#define PCFG_DCDCM_PROT_OVERVOLT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDCM_PROT_OVERVOLT_FLAG_MASK) >> PCFG_DCDCM_PROT_OVERVOLT_FLAG_SHIFT) + +/* + * DISABLE_SHORT (RW) + * + * disable output short circuit protection + * 0: short circuits protection enabled, DCDCM shut down if short circuit on output detected + * 1: short circuit protection disabled + */ +#define PCFG_DCDCM_PROT_DISABLE_SHORT_MASK (0x80U) +#define PCFG_DCDCM_PROT_DISABLE_SHORT_SHIFT (7U) +#define PCFG_DCDCM_PROT_DISABLE_SHORT_SET(x) (((uint32_t)(x) << PCFG_DCDCM_PROT_DISABLE_SHORT_SHIFT) & PCFG_DCDCM_PROT_DISABLE_SHORT_MASK) +#define PCFG_DCDCM_PROT_DISABLE_SHORT_GET(x) (((uint32_t)(x) & PCFG_DCDCM_PROT_DISABLE_SHORT_MASK) >> PCFG_DCDCM_PROT_DISABLE_SHORT_SHIFT) + +/* + * SHORT_CURRENT (RW) + * + * short circuit current setting + * 0: 2.0A + * 1: 1.3A + */ +#define PCFG_DCDCM_PROT_SHORT_CURRENT_MASK (0x10U) +#define PCFG_DCDCM_PROT_SHORT_CURRENT_SHIFT (4U) +#define PCFG_DCDCM_PROT_SHORT_CURRENT_SET(x) (((uint32_t)(x) << PCFG_DCDCM_PROT_SHORT_CURRENT_SHIFT) & PCFG_DCDCM_PROT_SHORT_CURRENT_MASK) +#define PCFG_DCDCM_PROT_SHORT_CURRENT_GET(x) (((uint32_t)(x) & PCFG_DCDCM_PROT_SHORT_CURRENT_MASK) >> PCFG_DCDCM_PROT_SHORT_CURRENT_SHIFT) + +/* + * SHORT_FLAG (RO) + * + * short circuit flag + * 0: current is within limit + * 1: short circuits detected + */ +#define PCFG_DCDCM_PROT_SHORT_FLAG_MASK (0x1U) +#define PCFG_DCDCM_PROT_SHORT_FLAG_SHIFT (0U) +#define PCFG_DCDCM_PROT_SHORT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDCM_PROT_SHORT_FLAG_MASK) >> PCFG_DCDCM_PROT_SHORT_FLAG_SHIFT) + +/* Bitfield definition for register: DCDCM_CURRENT */ +/* + * ESTI_EN (RW) + * + * enable current measure + */ +#define PCFG_DCDCM_CURRENT_ESTI_EN_MASK (0x8000U) +#define PCFG_DCDCM_CURRENT_ESTI_EN_SHIFT (15U) +#define PCFG_DCDCM_CURRENT_ESTI_EN_SET(x) (((uint32_t)(x) << PCFG_DCDCM_CURRENT_ESTI_EN_SHIFT) & PCFG_DCDCM_CURRENT_ESTI_EN_MASK) +#define PCFG_DCDCM_CURRENT_ESTI_EN_GET(x) (((uint32_t)(x) & PCFG_DCDCM_CURRENT_ESTI_EN_MASK) >> PCFG_DCDCM_CURRENT_ESTI_EN_SHIFT) + +/* + * VALID (RO) + * + * Current level valid + * 0: data is invalid + * 1: data is valid + */ +#define PCFG_DCDCM_CURRENT_VALID_MASK (0x100U) +#define PCFG_DCDCM_CURRENT_VALID_SHIFT (8U) +#define PCFG_DCDCM_CURRENT_VALID_GET(x) (((uint32_t)(x) & PCFG_DCDCM_CURRENT_VALID_MASK) >> PCFG_DCDCM_CURRENT_VALID_SHIFT) + +/* + * LEVEL (RO) + * + * DCDCM current level, current level is num * 50mA + */ +#define PCFG_DCDCM_CURRENT_LEVEL_MASK (0x1FU) +#define PCFG_DCDCM_CURRENT_LEVEL_SHIFT (0U) +#define PCFG_DCDCM_CURRENT_LEVEL_GET(x) (((uint32_t)(x) & PCFG_DCDCM_CURRENT_LEVEL_MASK) >> PCFG_DCDCM_CURRENT_LEVEL_SHIFT) + +/* Bitfield definition for register: DCDCM_ADVMODE */ +/* + * EN_RCSCALE (RW) + * + * Enable RC scale + */ +#define PCFG_DCDCM_ADVMODE_EN_RCSCALE_MASK (0x7000000UL) +#define PCFG_DCDCM_ADVMODE_EN_RCSCALE_SHIFT (24U) +#define PCFG_DCDCM_ADVMODE_EN_RCSCALE_SET(x) (((uint32_t)(x) << PCFG_DCDCM_ADVMODE_EN_RCSCALE_SHIFT) & PCFG_DCDCM_ADVMODE_EN_RCSCALE_MASK) +#define PCFG_DCDCM_ADVMODE_EN_RCSCALE_GET(x) (((uint32_t)(x) & PCFG_DCDCM_ADVMODE_EN_RCSCALE_MASK) >> PCFG_DCDCM_ADVMODE_EN_RCSCALE_SHIFT) + +/* + * DC_C (RW) + * + * Loop C number + */ +#define PCFG_DCDCM_ADVMODE_DC_C_MASK (0x300000UL) +#define PCFG_DCDCM_ADVMODE_DC_C_SHIFT (20U) +#define PCFG_DCDCM_ADVMODE_DC_C_SET(x) (((uint32_t)(x) << PCFG_DCDCM_ADVMODE_DC_C_SHIFT) & PCFG_DCDCM_ADVMODE_DC_C_MASK) +#define PCFG_DCDCM_ADVMODE_DC_C_GET(x) (((uint32_t)(x) & PCFG_DCDCM_ADVMODE_DC_C_MASK) >> PCFG_DCDCM_ADVMODE_DC_C_SHIFT) + +/* + * DC_R (RW) + * + * Loop R number + */ +#define PCFG_DCDCM_ADVMODE_DC_R_MASK (0xF0000UL) +#define PCFG_DCDCM_ADVMODE_DC_R_SHIFT (16U) +#define PCFG_DCDCM_ADVMODE_DC_R_SET(x) (((uint32_t)(x) << PCFG_DCDCM_ADVMODE_DC_R_SHIFT) & PCFG_DCDCM_ADVMODE_DC_R_MASK) +#define PCFG_DCDCM_ADVMODE_DC_R_GET(x) (((uint32_t)(x) & PCFG_DCDCM_ADVMODE_DC_R_MASK) >> PCFG_DCDCM_ADVMODE_DC_R_SHIFT) + +/* + * EN_FF_DET (RW) + * + * enable feed forward detect + * 0: feed forward detect is disabled + * 1: feed forward detect is enabled + */ +#define PCFG_DCDCM_ADVMODE_EN_FF_DET_MASK (0x40U) +#define PCFG_DCDCM_ADVMODE_EN_FF_DET_SHIFT (6U) +#define PCFG_DCDCM_ADVMODE_EN_FF_DET_SET(x) (((uint32_t)(x) << PCFG_DCDCM_ADVMODE_EN_FF_DET_SHIFT) & PCFG_DCDCM_ADVMODE_EN_FF_DET_MASK) +#define PCFG_DCDCM_ADVMODE_EN_FF_DET_GET(x) (((uint32_t)(x) & PCFG_DCDCM_ADVMODE_EN_FF_DET_MASK) >> PCFG_DCDCM_ADVMODE_EN_FF_DET_SHIFT) + +/* + * EN_FF_LOOP (RW) + * + * enable feed forward loop + * 0: feed forward loop is disabled + * 1: feed forward loop is enabled + */ +#define PCFG_DCDCM_ADVMODE_EN_FF_LOOP_MASK (0x20U) +#define PCFG_DCDCM_ADVMODE_EN_FF_LOOP_SHIFT (5U) +#define PCFG_DCDCM_ADVMODE_EN_FF_LOOP_SET(x) (((uint32_t)(x) << PCFG_DCDCM_ADVMODE_EN_FF_LOOP_SHIFT) & PCFG_DCDCM_ADVMODE_EN_FF_LOOP_MASK) +#define PCFG_DCDCM_ADVMODE_EN_FF_LOOP_GET(x) (((uint32_t)(x) & PCFG_DCDCM_ADVMODE_EN_FF_LOOP_MASK) >> PCFG_DCDCM_ADVMODE_EN_FF_LOOP_SHIFT) + +/* + * EN_AUTOLP (RW) + * + * enable auto enter low power mode + * 0: do not enter low power mode + * 1: enter low power mode if current is detected low + */ +#define PCFG_DCDCM_ADVMODE_EN_AUTOLP_MASK (0x10U) +#define PCFG_DCDCM_ADVMODE_EN_AUTOLP_SHIFT (4U) +#define PCFG_DCDCM_ADVMODE_EN_AUTOLP_SET(x) (((uint32_t)(x) << PCFG_DCDCM_ADVMODE_EN_AUTOLP_SHIFT) & PCFG_DCDCM_ADVMODE_EN_AUTOLP_MASK) +#define PCFG_DCDCM_ADVMODE_EN_AUTOLP_GET(x) (((uint32_t)(x) & PCFG_DCDCM_ADVMODE_EN_AUTOLP_MASK) >> PCFG_DCDCM_ADVMODE_EN_AUTOLP_SHIFT) + +/* + * EN_DCM_EXIT (RW) + * + * avoid over voltage + * 0: stay in DCM mode when voltage excess + * 1: change to CCM mode when voltage excess + */ +#define PCFG_DCDCM_ADVMODE_EN_DCM_EXIT_MASK (0x8U) +#define PCFG_DCDCM_ADVMODE_EN_DCM_EXIT_SHIFT (3U) +#define PCFG_DCDCM_ADVMODE_EN_DCM_EXIT_SET(x) (((uint32_t)(x) << PCFG_DCDCM_ADVMODE_EN_DCM_EXIT_SHIFT) & PCFG_DCDCM_ADVMODE_EN_DCM_EXIT_MASK) +#define PCFG_DCDCM_ADVMODE_EN_DCM_EXIT_GET(x) (((uint32_t)(x) & PCFG_DCDCM_ADVMODE_EN_DCM_EXIT_MASK) >> PCFG_DCDCM_ADVMODE_EN_DCM_EXIT_SHIFT) + +/* + * EN_SKIP (RW) + * + * enable skip on narrow pulse + * 0: do not skip narrow pulse + * 1: skip narrow pulse + */ +#define PCFG_DCDCM_ADVMODE_EN_SKIP_MASK (0x4U) +#define PCFG_DCDCM_ADVMODE_EN_SKIP_SHIFT (2U) +#define PCFG_DCDCM_ADVMODE_EN_SKIP_SET(x) (((uint32_t)(x) << PCFG_DCDCM_ADVMODE_EN_SKIP_SHIFT) & PCFG_DCDCM_ADVMODE_EN_SKIP_MASK) +#define PCFG_DCDCM_ADVMODE_EN_SKIP_GET(x) (((uint32_t)(x) & PCFG_DCDCM_ADVMODE_EN_SKIP_MASK) >> PCFG_DCDCM_ADVMODE_EN_SKIP_SHIFT) + +/* + * EN_IDLE (RW) + * + * enable skip when voltage is higher than threshold + * 0: do not skip + * 1: skip if voltage is excess + */ +#define PCFG_DCDCM_ADVMODE_EN_IDLE_MASK (0x2U) +#define PCFG_DCDCM_ADVMODE_EN_IDLE_SHIFT (1U) +#define PCFG_DCDCM_ADVMODE_EN_IDLE_SET(x) (((uint32_t)(x) << PCFG_DCDCM_ADVMODE_EN_IDLE_SHIFT) & PCFG_DCDCM_ADVMODE_EN_IDLE_MASK) +#define PCFG_DCDCM_ADVMODE_EN_IDLE_GET(x) (((uint32_t)(x) & PCFG_DCDCM_ADVMODE_EN_IDLE_MASK) >> PCFG_DCDCM_ADVMODE_EN_IDLE_SHIFT) + +/* + * EN_DCM (RW) + * + * DCM mode + * 0: CCM mode + * 1: DCM mode + */ +#define PCFG_DCDCM_ADVMODE_EN_DCM_MASK (0x1U) +#define PCFG_DCDCM_ADVMODE_EN_DCM_SHIFT (0U) +#define PCFG_DCDCM_ADVMODE_EN_DCM_SET(x) (((uint32_t)(x) << PCFG_DCDCM_ADVMODE_EN_DCM_SHIFT) & PCFG_DCDCM_ADVMODE_EN_DCM_MASK) +#define PCFG_DCDCM_ADVMODE_EN_DCM_GET(x) (((uint32_t)(x) & PCFG_DCDCM_ADVMODE_EN_DCM_MASK) >> PCFG_DCDCM_ADVMODE_EN_DCM_SHIFT) + +/* Bitfield definition for register: DCDCM_ADVPARAM */ +/* + * MIN_DUT (RW) + * + * minimum duty cycle + */ +#define PCFG_DCDCM_ADVPARAM_MIN_DUT_MASK (0x7F00U) +#define PCFG_DCDCM_ADVPARAM_MIN_DUT_SHIFT (8U) +#define PCFG_DCDCM_ADVPARAM_MIN_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDCM_ADVPARAM_MIN_DUT_SHIFT) & PCFG_DCDCM_ADVPARAM_MIN_DUT_MASK) +#define PCFG_DCDCM_ADVPARAM_MIN_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDCM_ADVPARAM_MIN_DUT_MASK) >> PCFG_DCDCM_ADVPARAM_MIN_DUT_SHIFT) + +/* + * MAX_DUT (RW) + * + * maximum duty cycle + */ +#define PCFG_DCDCM_ADVPARAM_MAX_DUT_MASK (0x7FU) +#define PCFG_DCDCM_ADVPARAM_MAX_DUT_SHIFT (0U) +#define PCFG_DCDCM_ADVPARAM_MAX_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDCM_ADVPARAM_MAX_DUT_SHIFT) & PCFG_DCDCM_ADVPARAM_MAX_DUT_MASK) +#define PCFG_DCDCM_ADVPARAM_MAX_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDCM_ADVPARAM_MAX_DUT_MASK) >> PCFG_DCDCM_ADVPARAM_MAX_DUT_SHIFT) + +/* Bitfield definition for register: DCDCM_MISC */ +/* + * EN_HYST (RW) + * + * hysteres enable + */ +#define PCFG_DCDCM_MISC_EN_HYST_MASK (0x10000000UL) +#define PCFG_DCDCM_MISC_EN_HYST_SHIFT (28U) +#define PCFG_DCDCM_MISC_EN_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDCM_MISC_EN_HYST_SHIFT) & PCFG_DCDCM_MISC_EN_HYST_MASK) +#define PCFG_DCDCM_MISC_EN_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDCM_MISC_EN_HYST_MASK) >> PCFG_DCDCM_MISC_EN_HYST_SHIFT) + +/* + * HYST_SIGN (RW) + * + * hysteres sign + */ +#define PCFG_DCDCM_MISC_HYST_SIGN_MASK (0x2000000UL) +#define PCFG_DCDCM_MISC_HYST_SIGN_SHIFT (25U) +#define PCFG_DCDCM_MISC_HYST_SIGN_SET(x) (((uint32_t)(x) << PCFG_DCDCM_MISC_HYST_SIGN_SHIFT) & PCFG_DCDCM_MISC_HYST_SIGN_MASK) +#define PCFG_DCDCM_MISC_HYST_SIGN_GET(x) (((uint32_t)(x) & PCFG_DCDCM_MISC_HYST_SIGN_MASK) >> PCFG_DCDCM_MISC_HYST_SIGN_SHIFT) + +/* + * HYST_THRS (RW) + * + * hysteres threshold + */ +#define PCFG_DCDCM_MISC_HYST_THRS_MASK (0x1000000UL) +#define PCFG_DCDCM_MISC_HYST_THRS_SHIFT (24U) +#define PCFG_DCDCM_MISC_HYST_THRS_SET(x) (((uint32_t)(x) << PCFG_DCDCM_MISC_HYST_THRS_SHIFT) & PCFG_DCDCM_MISC_HYST_THRS_MASK) +#define PCFG_DCDCM_MISC_HYST_THRS_GET(x) (((uint32_t)(x) & PCFG_DCDCM_MISC_HYST_THRS_MASK) >> PCFG_DCDCM_MISC_HYST_THRS_SHIFT) + +/* + * RC_SCALE (RW) + * + * Loop RC scale threshold + */ +#define PCFG_DCDCM_MISC_RC_SCALE_MASK (0x100000UL) +#define PCFG_DCDCM_MISC_RC_SCALE_SHIFT (20U) +#define PCFG_DCDCM_MISC_RC_SCALE_SET(x) (((uint32_t)(x) << PCFG_DCDCM_MISC_RC_SCALE_SHIFT) & PCFG_DCDCM_MISC_RC_SCALE_MASK) +#define PCFG_DCDCM_MISC_RC_SCALE_GET(x) (((uint32_t)(x) & PCFG_DCDCM_MISC_RC_SCALE_MASK) >> PCFG_DCDCM_MISC_RC_SCALE_SHIFT) + +/* + * DC_FF (RW) + * + * Loop feed forward number + */ +#define PCFG_DCDCM_MISC_DC_FF_MASK (0x70000UL) +#define PCFG_DCDCM_MISC_DC_FF_SHIFT (16U) +#define PCFG_DCDCM_MISC_DC_FF_SET(x) (((uint32_t)(x) << PCFG_DCDCM_MISC_DC_FF_SHIFT) & PCFG_DCDCM_MISC_DC_FF_MASK) +#define PCFG_DCDCM_MISC_DC_FF_GET(x) (((uint32_t)(x) & PCFG_DCDCM_MISC_DC_FF_MASK) >> PCFG_DCDCM_MISC_DC_FF_SHIFT) + +/* + * OL_THRE (RW) + * + * overload for threshold for lod power mode + */ +#define PCFG_DCDCM_MISC_OL_THRE_MASK (0x300U) +#define PCFG_DCDCM_MISC_OL_THRE_SHIFT (8U) +#define PCFG_DCDCM_MISC_OL_THRE_SET(x) (((uint32_t)(x) << PCFG_DCDCM_MISC_OL_THRE_SHIFT) & PCFG_DCDCM_MISC_OL_THRE_MASK) +#define PCFG_DCDCM_MISC_OL_THRE_GET(x) (((uint32_t)(x) & PCFG_DCDCM_MISC_OL_THRE_MASK) >> PCFG_DCDCM_MISC_OL_THRE_SHIFT) + +/* + * OL_HYST (RW) + * + * current hysteres range + * 0: 12.5mV + * 1: 25mV + */ +#define PCFG_DCDCM_MISC_OL_HYST_MASK (0x10U) +#define PCFG_DCDCM_MISC_OL_HYST_SHIFT (4U) +#define PCFG_DCDCM_MISC_OL_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDCM_MISC_OL_HYST_SHIFT) & PCFG_DCDCM_MISC_OL_HYST_MASK) +#define PCFG_DCDCM_MISC_OL_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDCM_MISC_OL_HYST_MASK) >> PCFG_DCDCM_MISC_OL_HYST_SHIFT) + +/* + * DELAY (RW) + * + * enable delay + * 0: delay disabled, + * 1: delay enabled + */ +#define PCFG_DCDCM_MISC_DELAY_MASK (0x4U) +#define PCFG_DCDCM_MISC_DELAY_SHIFT (2U) +#define PCFG_DCDCM_MISC_DELAY_SET(x) (((uint32_t)(x) << PCFG_DCDCM_MISC_DELAY_SHIFT) & PCFG_DCDCM_MISC_DELAY_MASK) +#define PCFG_DCDCM_MISC_DELAY_GET(x) (((uint32_t)(x) & PCFG_DCDCM_MISC_DELAY_MASK) >> PCFG_DCDCM_MISC_DELAY_SHIFT) + +/* + * CLK_SEL (RW) + * + * clock selection + * 0: select DCDCM internal oscillator + * 1: select RC24M oscillator + */ +#define PCFG_DCDCM_MISC_CLK_SEL_MASK (0x2U) +#define PCFG_DCDCM_MISC_CLK_SEL_SHIFT (1U) +#define PCFG_DCDCM_MISC_CLK_SEL_SET(x) (((uint32_t)(x) << PCFG_DCDCM_MISC_CLK_SEL_SHIFT) & PCFG_DCDCM_MISC_CLK_SEL_MASK) +#define PCFG_DCDCM_MISC_CLK_SEL_GET(x) (((uint32_t)(x) & PCFG_DCDCM_MISC_CLK_SEL_MASK) >> PCFG_DCDCM_MISC_CLK_SEL_SHIFT) + +/* + * EN_STEP (RW) + * + * enable stepping in voltage change + * 0: stepping disabled, + * 1: steping enabled + */ +#define PCFG_DCDCM_MISC_EN_STEP_MASK (0x1U) +#define PCFG_DCDCM_MISC_EN_STEP_SHIFT (0U) +#define PCFG_DCDCM_MISC_EN_STEP_SET(x) (((uint32_t)(x) << PCFG_DCDCM_MISC_EN_STEP_SHIFT) & PCFG_DCDCM_MISC_EN_STEP_MASK) +#define PCFG_DCDCM_MISC_EN_STEP_GET(x) (((uint32_t)(x) & PCFG_DCDCM_MISC_EN_STEP_MASK) >> PCFG_DCDCM_MISC_EN_STEP_SHIFT) + +/* Bitfield definition for register: DCDCM_DEBUG */ +/* + * UPDATE_TIME (RW) + * + * DCDCM voltage change time in 24M clock cycles, default value is 1mS + */ +#define PCFG_DCDCM_DEBUG_UPDATE_TIME_MASK (0xFFFFFUL) +#define PCFG_DCDCM_DEBUG_UPDATE_TIME_SHIFT (0U) +#define PCFG_DCDCM_DEBUG_UPDATE_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDCM_DEBUG_UPDATE_TIME_SHIFT) & PCFG_DCDCM_DEBUG_UPDATE_TIME_MASK) +#define PCFG_DCDCM_DEBUG_UPDATE_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDCM_DEBUG_UPDATE_TIME_MASK) >> PCFG_DCDCM_DEBUG_UPDATE_TIME_SHIFT) + +/* Bitfield definition for register: DCDCM_START_TIME */ +/* + * START_TIME (RW) + * + * Start delay for DCDCM to turn on, in 24M clock cycles, default value is 3mS + */ +#define PCFG_DCDCM_START_TIME_START_TIME_MASK (0xFFFFFUL) +#define PCFG_DCDCM_START_TIME_START_TIME_SHIFT (0U) +#define PCFG_DCDCM_START_TIME_START_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDCM_START_TIME_START_TIME_SHIFT) & PCFG_DCDCM_START_TIME_START_TIME_MASK) +#define PCFG_DCDCM_START_TIME_START_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDCM_START_TIME_START_TIME_MASK) >> PCFG_DCDCM_START_TIME_START_TIME_SHIFT) + +/* Bitfield definition for register: DCDCM_RESUME_TIME */ +/* + * RESUME_TIME (RW) + * + * Resume delay for DCDCM to recover from low power mode, in 24M clock cycles, default value is 10uS + */ +#define PCFG_DCDCM_RESUME_TIME_RESUME_TIME_MASK (0xFFFFFUL) +#define PCFG_DCDCM_RESUME_TIME_RESUME_TIME_SHIFT (0U) +#define PCFG_DCDCM_RESUME_TIME_RESUME_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDCM_RESUME_TIME_RESUME_TIME_SHIFT) & PCFG_DCDCM_RESUME_TIME_RESUME_TIME_MASK) +#define PCFG_DCDCM_RESUME_TIME_RESUME_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDCM_RESUME_TIME_RESUME_TIME_MASK) >> PCFG_DCDCM_RESUME_TIME_RESUME_TIME_SHIFT) + +/* Bitfield definition for register: DCDCM_POWER_CONFIG */ +/* + * RETENTION (RW) + * + * DCDCM enter standby mode, which will reduce voltage for memory content retention + * 0: Shutdown DCDCM + * 1: reduce DCDC voltage + */ +#define PCFG_DCDCM_POWER_CONFIG_RETENTION_MASK (0x10000UL) +#define PCFG_DCDCM_POWER_CONFIG_RETENTION_SHIFT (16U) +#define PCFG_DCDCM_POWER_CONFIG_RETENTION_SET(x) (((uint32_t)(x) << PCFG_DCDCM_POWER_CONFIG_RETENTION_SHIFT) & PCFG_DCDCM_POWER_CONFIG_RETENTION_MASK) +#define PCFG_DCDCM_POWER_CONFIG_RETENTION_GET(x) (((uint32_t)(x) & PCFG_DCDCM_POWER_CONFIG_RETENTION_MASK) >> PCFG_DCDCM_POWER_CONFIG_RETENTION_SHIFT) + + + + +#endif /* HPM_PCFG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_pgpr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_pgpr_regs.h new file mode 100644 index 00000000000..acf20cfecd5 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_pgpr_regs.h @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PGPR_H +#define HPM_PGPR_H + +typedef struct { + __RW uint32_t PMIC_GPR00; /* 0x0: Generic control */ + __RW uint32_t PMIC_GPR01; /* 0x4: Generic control */ + __RW uint32_t PMIC_GPR02; /* 0x8: Generic control */ + __RW uint32_t PMIC_GPR03; /* 0xC: Generic control */ + __RW uint32_t PMIC_GPR04; /* 0x10: Generic control */ + __RW uint32_t PMIC_GPR05; /* 0x14: Generic control */ + __RW uint32_t PMIC_GPR06; /* 0x18: Generic control */ + __RW uint32_t PMIC_GPR07; /* 0x1C: Generic control */ + __RW uint32_t PMIC_GPR08; /* 0x20: Generic control */ + __RW uint32_t PMIC_GPR09; /* 0x24: Generic control */ + __RW uint32_t PMIC_GPR10; /* 0x28: Generic control */ + __RW uint32_t PMIC_GPR11; /* 0x2C: Generic control */ + __RW uint32_t PMIC_GPR12; /* 0x30: Generic control */ + __RW uint32_t PMIC_GPR13; /* 0x34: Generic control */ + __RW uint32_t PMIC_GPR14; /* 0x38: Generic control */ + __RW uint32_t PMIC_GPR15; /* 0x3C: Generic control */ +} PGPR_Type; + + +/* Bitfield definition for register: PMIC_GPR00 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR00_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR00_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR00_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR00_GPR_SHIFT) & PGPR_PMIC_GPR00_GPR_MASK) +#define PGPR_PMIC_GPR00_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR00_GPR_MASK) >> PGPR_PMIC_GPR00_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR01 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR01_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR01_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR01_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR01_GPR_SHIFT) & PGPR_PMIC_GPR01_GPR_MASK) +#define PGPR_PMIC_GPR01_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR01_GPR_MASK) >> PGPR_PMIC_GPR01_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR02 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR02_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR02_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR02_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR02_GPR_SHIFT) & PGPR_PMIC_GPR02_GPR_MASK) +#define PGPR_PMIC_GPR02_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR02_GPR_MASK) >> PGPR_PMIC_GPR02_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR03 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR03_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR03_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR03_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR03_GPR_SHIFT) & PGPR_PMIC_GPR03_GPR_MASK) +#define PGPR_PMIC_GPR03_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR03_GPR_MASK) >> PGPR_PMIC_GPR03_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR04 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR04_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR04_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR04_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR04_GPR_SHIFT) & PGPR_PMIC_GPR04_GPR_MASK) +#define PGPR_PMIC_GPR04_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR04_GPR_MASK) >> PGPR_PMIC_GPR04_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR05 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR05_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR05_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR05_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR05_GPR_SHIFT) & PGPR_PMIC_GPR05_GPR_MASK) +#define PGPR_PMIC_GPR05_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR05_GPR_MASK) >> PGPR_PMIC_GPR05_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR06 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR06_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR06_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR06_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR06_GPR_SHIFT) & PGPR_PMIC_GPR06_GPR_MASK) +#define PGPR_PMIC_GPR06_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR06_GPR_MASK) >> PGPR_PMIC_GPR06_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR07 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR07_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR07_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR07_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR07_GPR_SHIFT) & PGPR_PMIC_GPR07_GPR_MASK) +#define PGPR_PMIC_GPR07_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR07_GPR_MASK) >> PGPR_PMIC_GPR07_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR08 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR08_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR08_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR08_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR08_GPR_SHIFT) & PGPR_PMIC_GPR08_GPR_MASK) +#define PGPR_PMIC_GPR08_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR08_GPR_MASK) >> PGPR_PMIC_GPR08_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR09 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR09_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR09_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR09_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR09_GPR_SHIFT) & PGPR_PMIC_GPR09_GPR_MASK) +#define PGPR_PMIC_GPR09_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR09_GPR_MASK) >> PGPR_PMIC_GPR09_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR10 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR10_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR10_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR10_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR10_GPR_SHIFT) & PGPR_PMIC_GPR10_GPR_MASK) +#define PGPR_PMIC_GPR10_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR10_GPR_MASK) >> PGPR_PMIC_GPR10_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR11 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR11_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR11_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR11_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR11_GPR_SHIFT) & PGPR_PMIC_GPR11_GPR_MASK) +#define PGPR_PMIC_GPR11_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR11_GPR_MASK) >> PGPR_PMIC_GPR11_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR12 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR12_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR12_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR12_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR12_GPR_SHIFT) & PGPR_PMIC_GPR12_GPR_MASK) +#define PGPR_PMIC_GPR12_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR12_GPR_MASK) >> PGPR_PMIC_GPR12_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR13 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR13_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR13_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR13_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR13_GPR_SHIFT) & PGPR_PMIC_GPR13_GPR_MASK) +#define PGPR_PMIC_GPR13_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR13_GPR_MASK) >> PGPR_PMIC_GPR13_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR14 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR14_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR14_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR14_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR14_GPR_SHIFT) & PGPR_PMIC_GPR14_GPR_MASK) +#define PGPR_PMIC_GPR14_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR14_GPR_MASK) >> PGPR_PMIC_GPR14_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR15 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR15_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR15_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR15_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR15_GPR_SHIFT) & PGPR_PMIC_GPR15_GPR_MASK) +#define PGPR_PMIC_GPR15_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR15_GPR_MASK) >> PGPR_PMIC_GPR15_GPR_SHIFT) + + + + +#endif /* HPM_PGPR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_plic_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_plic_drv.h new file mode 100644 index 00000000000..9595051f906 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_plic_drv.h @@ -0,0 +1,186 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PLIC_DRV_H +#define HPM_PLIC_DRV_H + +/** + * @brief PLIC driver APIs + * @defgroup plic_interface PLIC driver APIs + * @{ + */ + +#define HPM_PLIC_TARGET_M_MODE 0 +#define HPM_PLIC_TARGET_S_MODE 1 + +/* Feature Register */ +#define HPM_PLIC_FEATURE_OFFSET (0x00000000UL) +#define HPM_PLIC_FEATURE_VECTORED_MODE (0x2UL) +#define HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ (0x1UL) + +/* Priority Register - 32 bits per irq */ +#define HPM_PLIC_PRIORITY_OFFSET (0x00000004UL) +#define HPM_PLIC_PRIORITY_SHIFT_PER_SOURCE 2 + +/* Pending Register - 1 bit per source */ +#define HPM_PLIC_PENDING_OFFSET (0x00001000UL) +#define HPM_PLIC_PENDING_SHIFT_PER_SOURCE 0 + +/* Enable Register - 0x80 per target */ +#define HPM_PLIC_ENABLE_OFFSET (0x00002000UL) +#define HPM_PLIC_ENABLE_SHIFT_PER_TARGET 7 + +/* Priority Threshold Register - 0x1000 per target */ +#define HPM_PLIC_THRESHOLD_OFFSET (0x00200000UL) +#define HPM_PLIC_THRESHOLD_SHIFT_PER_TARGET 12 + +/* Claim Register - 0x1000 per target */ +#define HPM_PLIC_CLAIM_OFFSET (0x00200004UL) +#define HPM_PLIC_CLAIM_SHIFT_PER_TARGET 12 + +#if !defined(__ASSEMBLER__) + +/** + * @brief Set plic feature + * + * @param[in] base PLIC base address + * @param[in] feature Specific feature to be set + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_set_feature(uint32_t base, uint32_t feature) +{ + *(volatile uint32_t *)(base + HPM_PLIC_FEATURE_OFFSET) = feature; +} + +/** + * @brief Set plic threshold + * + * @param[in] base PLIC base address + * @param[in] target Target to handle specific interrupt + * @param[in] threshold Threshold of IRQ can be serviced + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_set_threshold(uint32_t base, + uint32_t target, + uint32_t threshold) +{ + volatile uint32_t *threshold_ptr = (volatile uint32_t *)(base + + HPM_PLIC_THRESHOLD_OFFSET + + (target << HPM_PLIC_THRESHOLD_SHIFT_PER_TARGET)); + *threshold_ptr = threshold; +} + +/** + * @brief Set interrupt priority + * + * @param[in] base PLIC base address + * @param[in] irq Target interrupt number + * @param[in] priority Priority to be assigned + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_set_irq_priority(uint32_t base, + uint32_t irq, + uint32_t priority) +{ + volatile uint32_t *priority_ptr = (volatile uint32_t *)(base + + HPM_PLIC_PRIORITY_OFFSET + ((irq-1) << HPM_PLIC_PRIORITY_SHIFT_PER_SOURCE)); + *priority_ptr = priority; +} + +/** + * @brief Set interrupt pending bit + * + * @param[in] base PLIC base address + * @param[in] irq Target interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_set_irq_pending(uint32_t base, uint32_t irq) +{ + volatile uint32_t *current_ptr = (volatile uint32_t *)(base + + HPM_PLIC_PENDING_OFFSET + ((irq >> 5) << 2)); + *current_ptr = (1 << (irq & 0x1F)); +} + +/** + * @brief Enable interrupt + * + * @param[in] base PLIC base address + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number to be enabled + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_enable_irq(uint32_t base, + uint32_t target, + uint32_t irq) +{ + volatile uint32_t *current_ptr = (volatile uint32_t *)(base + + HPM_PLIC_ENABLE_OFFSET + + (target << HPM_PLIC_ENABLE_SHIFT_PER_TARGET) + + ((irq >> 5) << 2)); + uint32_t current = *current_ptr; + current = current | (1 << (irq & 0x1F)); + *current_ptr = current; +} + +/** + * @brief Disable interrupt + * + * @param[in] base PLIC base address + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number to be disabled + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_disable_irq(uint32_t base, + uint32_t target, + uint32_t irq) +{ + volatile uint32_t *current_ptr = (volatile uint32_t *)(base + + HPM_PLIC_ENABLE_OFFSET + + (target << HPM_PLIC_ENABLE_SHIFT_PER_TARGET) + + ((irq >> 5) << 2)); + uint32_t current = *current_ptr; + current = current & ~((1 << (irq & 0x1F))); + *current_ptr = current; +} + +/** + * @brief Claim interrupt + * + * @param[in] base PLIC base address + * @param[in] target Target to claim interrupt + * + */ +ATTR_ALWAYS_INLINE static inline uint32_t __plic_claim_irq(uint32_t base, uint32_t target) +{ + volatile uint32_t *claim_addr = (volatile uint32_t *)(base + + HPM_PLIC_CLAIM_OFFSET + + (target << HPM_PLIC_CLAIM_SHIFT_PER_TARGET)); + return *claim_addr; +} + +/** + * @brief Complete interrupt + * + * @param[in] base PLIC base address + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_complete_irq(uint32_t base, + uint32_t target, + uint32_t irq) +{ + volatile uint32_t *claim_addr = (volatile uint32_t *)(base + + HPM_PLIC_CLAIM_OFFSET + + (target << HPM_PLIC_CLAIM_SHIFT_PER_TARGET)); + *claim_addr = irq; +} +#endif /* __ASSEMBLER__ */ +/** + * @} + */ +#endif /* HPM_PLIC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_pmic_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_pmic_iomux.h new file mode 100644 index 00000000000..de65786285c --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_pmic_iomux.h @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PMIC_IOMUX_H +#define HPM_PMIC_IOMUX_H + +/* PIOC_PY00_FUNC_CTL function mux definitions */ +#define IOC_PY00_FUNC_CTL_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY00_FUNC_CTL_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY00_FUNC_CTL_PURT_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY00_FUNC_CTL_PURT_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY00_FUNC_CTL_SOC_PY_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY00_FUNC_CTL_SOC_PY_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY01_FUNC_CTL function mux definitions */ +#define IOC_PY01_FUNC_CTL_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY01_FUNC_CTL_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY01_FUNC_CTL_PURT_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY01_FUNC_CTL_PURT_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY01_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY01_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY01_FUNC_CTL_SOC_PY_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY01_FUNC_CTL_SOC_PY_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY02_FUNC_CTL function mux definitions */ +#define IOC_PY02_FUNC_CTL_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY02_FUNC_CTL_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY02_FUNC_CTL_PURT_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY02_FUNC_CTL_PURT_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY02_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY02_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY02_FUNC_CTL_SOC_PY_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY02_FUNC_CTL_SOC_PY_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY03_FUNC_CTL function mux definitions */ +#define IOC_PY03_FUNC_CTL_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY03_FUNC_CTL_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY03_FUNC_CTL_PURT_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY03_FUNC_CTL_PURT_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY03_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY03_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY03_FUNC_CTL_SOC_PY_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY03_FUNC_CTL_SOC_PY_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY04_FUNC_CTL function mux definitions */ +#define IOC_PY04_FUNC_CTL_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY04_FUNC_CTL_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY04_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY04_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY04_FUNC_CTL_SOC_PY_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY04_FUNC_CTL_SOC_PY_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY05_FUNC_CTL function mux definitions */ +#define IOC_PY05_FUNC_CTL_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY05_FUNC_CTL_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY05_FUNC_CTL_PWDG_RSTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY05_FUNC_CTL_PWDG_RSTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY05_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY05_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY05_FUNC_CTL_SOC_PY_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY05_FUNC_CTL_SOC_PY_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY06_FUNC_CTL function mux definitions */ +#define IOC_PY06_FUNC_CTL_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY06_FUNC_CTL_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY06_FUNC_CTL_VAD_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY06_FUNC_CTL_VAD_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY06_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY06_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY06_FUNC_CTL_SOC_PY_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY06_FUNC_CTL_SOC_PY_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY07_FUNC_CTL function mux definitions */ +#define IOC_PY07_FUNC_CTL_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY07_FUNC_CTL_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY07_FUNC_CTL_VAD_DAT IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY07_FUNC_CTL_VAD_DAT IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY07_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY07_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY07_FUNC_CTL_SOC_PY_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY07_FUNC_CTL_SOC_PY_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY08_FUNC_CTL function mux definitions */ +#define IOC_PY08_FUNC_CTL_GPIO_Y_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY08_FUNC_CTL_GPIO_Y_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY08_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY08_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY08_FUNC_CTL_SOC_PY_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY08_FUNC_CTL_SOC_PY_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY09_FUNC_CTL function mux definitions */ +#define IOC_PY09_FUNC_CTL_GPIO_Y_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY09_FUNC_CTL_GPIO_Y_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY09_FUNC_CTL_PTMR_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY09_FUNC_CTL_PTMR_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY09_FUNC_CTL_SOC_PY_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY09_FUNC_CTL_SOC_PY_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY10_FUNC_CTL function mux definitions */ +#define IOC_PY10_FUNC_CTL_GPIO_Y_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY10_FUNC_CTL_GPIO_Y_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY10_FUNC_CTL_PTMR_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY10_FUNC_CTL_PTMR_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY10_FUNC_CTL_SOC_PY_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY10_FUNC_CTL_SOC_PY_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY11_FUNC_CTL function mux definitions */ +#define IOC_PY11_FUNC_CTL_GPIO_Y_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY11_FUNC_CTL_GPIO_Y_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY11_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY11_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY11_FUNC_CTL_SOC_PY_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY11_FUNC_CTL_SOC_PY_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY12_FUNC_CTL function mux definitions */ +#define IOC_PY12_FUNC_CTL_GPIO_Y_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY12_FUNC_CTL_GPIO_Y_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY12_FUNC_CTL_SOC_PY_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY12_FUNC_CTL_SOC_PY_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY13_FUNC_CTL function mux definitions */ +#define IOC_PY13_FUNC_CTL_GPIO_Y_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY13_FUNC_CTL_GPIO_Y_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY13_FUNC_CTL_SOC_PY_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY13_FUNC_CTL_SOC_PY_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY14_FUNC_CTL function mux definitions */ +#define IOC_PY14_FUNC_CTL_GPIO_Y_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY14_FUNC_CTL_GPIO_Y_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY14_FUNC_CTL_SOC_PY_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY14_FUNC_CTL_SOC_PY_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* PIOC_PY15_FUNC_CTL function mux definitions */ +#define IOC_PY15_FUNC_CTL_GPIO_Y_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY15_FUNC_CTL_GPIO_Y_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY15_FUNC_CTL_SOC_PY_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ +#define PIOC_PY15_FUNC_CTL_SOC_PY_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + + +#endif /* HPM_PMIC_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_ppor_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_ppor_drv.h new file mode 100644 index 00000000000..1913a26aa1a --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_ppor_drv.h @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PPOR_DRV_H +#define HPM_PPOR_DRV_H +#include "hpm_common.h" +#include "hpm_ppor_regs.h" + +typedef enum { + ppor_reset_brownout = 1 << 0, + ppor_reset_debug = 1 << 4, + ppor_reset_wdog0 = 1 << 16, + ppor_reset_wdog1 = 1 << 17, + ppor_reset_wdog2 = 1 << 18, + ppor_reset_wdog3 = 1 << 19, + ppor_reset_pmic_wdog = 1 << 20, + ppor_reset_software = 1 << 31, +} ppor_reset_source_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * perform software reset in counter * (1/24Mhz) seconds + */ +static inline void ppor_sw_reset(PPOR_Type *ptr, uint32_t counter) +{ + ptr->SOFTWARE_RESET = counter; +} + +/* + * clear enable reset source according to the given mask + */ +static inline void ppor_reset_mask_clear_source_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_ENABLE &= ~mask; +} + +/* + * set enable reset source according to the given mask + */ +static inline void ppor_reset_mask_set_source_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_ENABLE |= mask; +} + +/* + * set enable reset source + */ +static inline void ppor_reset_set_source_enable(PPOR_Type *ptr, uint32_t reset_sources) +{ + ptr->RESET_ENABLE = reset_sources; +} + +/* + * get enabled reset source + */ +static inline uint32_t ppor_reset_get_enabled_source(PPOR_Type *ptr) +{ + return ptr->RESET_ENABLE; +} + +/* + * get reset status + */ +static inline uint32_t ppor_reset_get_status(PPOR_Type *ptr) +{ + return ptr->RESET_STATUS; +} + +/* + * get reset flags + */ +static inline uint32_t ppor_reset_get_flags(PPOR_Type *ptr) +{ + return ptr->RESET_FLAG; +} + +/* + * clear reset flags + */ +static inline void ppor_reset_clear_flags(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_FLAG = mask; +} + +/* + * get reset hold + */ +static inline uint32_t ppor_reset_get_hold(PPOR_Type *ptr) +{ + return ptr->RESET_HOLD; +} + +/* + * set reset hold + */ +static inline void ppor_reset_set_hold_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_HOLD |= mask; +} + +/* + * clear reset hold + */ +static inline void ppor_reset_clear_hold_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_HOLD &= ~mask; +} + +/* + * set cold reset + */ +static inline void ppor_reset_set_cold_reset_enable(PPOR_Type *ptr, uint32_t mask) +{ + (void) ptr; + (void) mask; +} + +/* + * clear cold reset + */ +static inline void ppor_reset_clear_cold_reset_enable(PPOR_Type *ptr, uint32_t mask) +{ + (void) ptr; + (void) mask; +} + +/* + * set hot reset + */ +static inline void ppor_reset_set_hot_reset_enable(PPOR_Type *ptr, uint32_t mask) +{ + (void) ptr; + (void) mask; +} + +/* + * clear hot reset + */ +static inline void ppor_reset_clear_hot_reset_enable(PPOR_Type *ptr, uint32_t mask) +{ + (void) ptr; + (void) mask; +} + +#ifdef __cplusplus +} +#endif +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_ppor_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_ppor_regs.h new file mode 100644 index 00000000000..11181004dbd --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_ppor_regs.h @@ -0,0 +1,139 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PPOR_H +#define HPM_PPOR_H + +typedef struct { + __W uint32_t RESET_FLAG; /* 0x0: flag indicate reset source */ + __R uint32_t RESET_STATUS; /* 0x4: reset source status */ + __RW uint32_t RESET_HOLD; /* 0x8: reset hold attribute */ + __RW uint32_t RESET_ENABLE; /* 0xC: reset source enable */ + __R uint8_t RESERVED0[12]; /* 0x10 - 0x1B: Reserved */ + __RW uint32_t SOFTWARE_RESET; /* 0x1C: Software reset counter */ +} PPOR_Type; + + +/* Bitfield definition for register: RESET_FLAG */ +/* + * FLAG (W1C) + * + * reset reason of last hard reset, write 1 to clear each bit + * 0: brownout + * 1: temperature(not available) + * 4: debug reset + * 5: jtag soft reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2(not available) + * 19: watch dog 3(not available) + * 24: pmic watch dog + * 30: jtag ieee reset + * 31: software + */ +#define PPOR_RESET_FLAG_FLAG_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_FLAG_FLAG_SHIFT (0U) +#define PPOR_RESET_FLAG_FLAG_SET(x) (((uint32_t)(x) << PPOR_RESET_FLAG_FLAG_SHIFT) & PPOR_RESET_FLAG_FLAG_MASK) +#define PPOR_RESET_FLAG_FLAG_GET(x) (((uint32_t)(x) & PPOR_RESET_FLAG_FLAG_MASK) >> PPOR_RESET_FLAG_FLAG_SHIFT) + +/* Bitfield definition for register: RESET_STATUS */ +/* + * STATUS (RO) + * + * current status of reset sources + * 0: brownout + * 1: temperature(not available) + * 4: debug reset + * 5: jtag soft reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2(not available) + * 19: watch dog 3(not available) + * 24: pmic watch dog + * 30: jtag ieee reset + * 31: software + */ +#define PPOR_RESET_STATUS_STATUS_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_STATUS_STATUS_SHIFT (0U) +#define PPOR_RESET_STATUS_STATUS_GET(x) (((uint32_t)(x) & PPOR_RESET_STATUS_STATUS_MASK) >> PPOR_RESET_STATUS_STATUS_SHIFT) + +/* Bitfield definition for register: RESET_HOLD */ +/* + * HOLD (RW) + * + * hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status + * 0: brownout + * 1: temperature(not available) + * 4: debug reset + * 5: jtag soft reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2(not available) + * 19: watch dog 3(not available) + * 24: pmic watch dog + * 30: jtag ieee reset + * 31: software + */ +#define PPOR_RESET_HOLD_HOLD_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_HOLD_HOLD_SHIFT (0U) +#define PPOR_RESET_HOLD_HOLD_SET(x) (((uint32_t)(x) << PPOR_RESET_HOLD_HOLD_SHIFT) & PPOR_RESET_HOLD_HOLD_MASK) +#define PPOR_RESET_HOLD_HOLD_GET(x) (((uint32_t)(x) & PPOR_RESET_HOLD_HOLD_MASK) >> PPOR_RESET_HOLD_HOLD_SHIFT) + +/* Bitfield definition for register: RESET_ENABLE */ +/* + * ENABLE (RW) + * + * enable of reset sources + * 0: brownout + * 1: temperature(not available) + * 4: debug reset + * 5: jtag soft reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2(not available) + * 19: watch dog 3(not available) + * 24: pmic watch dog + * 30: jtag ieee reset + * 31: software + */ +#define PPOR_RESET_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_ENABLE_ENABLE_SHIFT (0U) +#define PPOR_RESET_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << PPOR_RESET_ENABLE_ENABLE_SHIFT) & PPOR_RESET_ENABLE_ENABLE_MASK) +#define PPOR_RESET_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & PPOR_RESET_ENABLE_ENABLE_MASK) >> PPOR_RESET_ENABLE_ENABLE_SHIFT) + +/* Bitfield definition for register: SOFTWARE_RESET */ +/* + * COUNTER (RW) + * + * counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset + */ +#define PPOR_SOFTWARE_RESET_COUNTER_MASK (0xFFFFFFFFUL) +#define PPOR_SOFTWARE_RESET_COUNTER_SHIFT (0U) +#define PPOR_SOFTWARE_RESET_COUNTER_SET(x) (((uint32_t)(x) << PPOR_SOFTWARE_RESET_COUNTER_SHIFT) & PPOR_SOFTWARE_RESET_COUNTER_MASK) +#define PPOR_SOFTWARE_RESET_COUNTER_GET(x) (((uint32_t)(x) & PPOR_SOFTWARE_RESET_COUNTER_MASK) >> PPOR_SOFTWARE_RESET_COUNTER_SHIFT) + + + + +#endif /* HPM_PPOR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_romapi.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_romapi.h new file mode 100644 index 00000000000..308a5d1f7df --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_romapi.h @@ -0,0 +1,1016 @@ +/* + * Copyright (c) 2022-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_ROMAPI_H +#define HPM_ROMAPI_H + +/** + * @brief ROM APIs + * @defgroup romapi_interface ROM APIs + * @{ + */ + +#include "hpm_common.h" +#include "hpm_otp_drv.h" +#include "hpm_romapi_xpi_def.h" +#include "hpm_romapi_xpi_soc_def.h" +#include "hpm_romapi_xpi_nor_def.h" +#include "hpm_romapi_xpi_ram_def.h" +#include "hpm_sdp_drv.h" + +/* XPI0 base address */ +#define HPM_XPI0_BASE (0xF3000000UL) /**< XPI0 Base address */ +/* XPI0 base pointer */ +#define HPM_XPI0 ((XPI_Type *) HPM_XPI0_BASE) /**< XPI0 Base pointer */ + + +/*********************************************************************************************************************** + * + * + * Definitions + * + * + **********************************************************************************************************************/ +/** + * @brief Enter Bootloader API argument + */ +typedef union { + uint32_t U; + struct { + uint32_t index: 8; /**< Image index */ + uint32_t peripheral: 8; /**< Boot peripheral */ + uint32_t src: 8; /**< Boot source */ + uint32_t tag: 8; /**< ROM API parameter tag, must be 0xEB */ + }; +} api_boot_arg_t; + +/*EXiP Region Parameter */ +typedef struct { + uint32_t start; /**< Start address, must be 4KB aligned */ + uint32_t len; /**< Must be 4KB aligned */ + uint8_t key[16]; /**< AES Key */ + uint8_t ctr[8]; /**< Initial Vector/Counter */ +} exip_region_param_t; + +#define API_BOOT_TAG (0xEBU) /**< ROM API parameter tag */ +#define API_BOOT_SRC_OTP (0U) /**< Boot source: OTP */ +#define API_BOOT_SRC_PRIMARY (1U) /**< Boot source: Primary */ +#define API_BOOT_SRC_SERIAL_BOOT (2U) /**< Boot source: Serial Boot */ +#define API_BOOT_SRC_ISP (3U) /**< Boot source: ISP */ +#define API_BOOT_PERIPH_AUTO (0U) /**< Boot peripheral: Auto detected */ +#define API_BOOT_PERIPH_UART (1U) /**< Boot peripheral: UART */ +#define API_BOOT_PERIPH_USBHID (2U) /**< Boot Peripheral: USB-HID */ + +/** + * @brief OTP driver interface + */ +typedef struct { + /**< OTP driver interface version */ + uint32_t version; + /**< OTP driver interface: init */ + void (*init)(void); + /**< OTP driver interface: deinit */ + void (*deinit)(void); + /**< OTP driver interface: read from shadow */ + uint32_t (*read_from_shadow)(uint32_t addr); + /**< OTP driver interface: read from ip */ + uint32_t (*read_from_ip)(uint32_t addr); + /**< OTP driver interface: program */ + hpm_stat_t (*program)(uint32_t addr, const uint32_t *src, uint32_t num_of_words); + /**< OTP driver interface: reload */ + hpm_stat_t (*reload)(otp_region_t region); + /**< OTP driver interface: lock */ + hpm_stat_t (*lock)(uint32_t addr, otp_lock_option_t lock_option); + /**< OTP driver interface: lock_shadow */ + hpm_stat_t (*lock_shadow)(uint32_t addr, otp_lock_option_t lock_option); + /**< OTP driver interface: set_configurable_region */ + hpm_stat_t (*set_configurable_region)(uint32_t start, uint32_t num_of_words); + /**< OTP driver interface: write_shadow_register */ + hpm_stat_t (*write_shadow_register)(uint32_t addr, uint32_t data); +} otp_driver_interface_t; + +/** + * @brief XPI driver interface + */ +typedef struct { + /**< XPI driver interface: version */ + uint32_t version; + /**< XPI driver interface: get default configuration */ + hpm_stat_t (*get_default_config)(xpi_config_t *xpi_config); + /**< XPI driver interface: get default device configuration */ + hpm_stat_t (*get_default_device_config)(xpi_device_config_t *dev_config); + /**< XPI driver interface: initialize the XPI using xpi_config */ + hpm_stat_t (*init)(XPI_Type *base, xpi_config_t *xpi_config); + /**< XPI driver interface: configure the AHB buffer */ + hpm_stat_t (*config_ahb_buffer)(XPI_Type *base, xpi_ahb_buffer_cfg_t *ahb_buf_cfg); + /**< XPI driver interface: configure the device */ + hpm_stat_t (*config_device)(XPI_Type *base, xpi_device_config_t *dev_cfg, xpi_channel_t channel); + /**< XPI driver interface: update instruction talbe */ + hpm_stat_t (*update_instr_table)(XPI_Type *base, const uint32_t *inst_base, uint32_t seq_idx, uint32_t num); + /**< XPI driver interface: transfer command/data using block interface */ + hpm_stat_t (*transfer_blocking)(XPI_Type *base, xpi_xfer_ctx_t *xfer); + /**< Software reset the XPI controller */ + void (*software_reset)(XPI_Type *base); + /**< XPI driver interface: Check whether IP is idle */ + bool (*is_idle)(XPI_Type *base); + /**< XPI driver interface: update delay line setting */ + void (*update_dllcr)(XPI_Type *base, + uint32_t serial_root_clk_freq, + uint32_t data_valid_time, + xpi_channel_t channel, + uint32_t dly_target); + /**< XPI driver interface: Get absolute address for APB transfer */ + hpm_stat_t + (*get_abs_apb_xfer_addr)(XPI_Type *base, xpi_xfer_channel_t channel, uint32_t in_addr, uint32_t *out_addr); +} xpi_driver_interface_t; + +/** + * @brief XPI NOR driver interface + */ +typedef struct { + /**< XPI NOR driver interface: API version */ + uint32_t version; + /**< XPI NOR driver interface: Get FLASH configuration */ + hpm_stat_t (*get_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option); + /**< XPI NOR driver interface: initialize FLASH */ + hpm_stat_t (*init)(XPI_Type *base, xpi_nor_config_t *nor_config); + /**< XPI NOR driver interface: Enable write access to FLASH */ + hpm_stat_t + (*enable_write)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + /**< XPI NOR driver interface: Get FLASH status register */ + hpm_stat_t (*get_status)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t addr, + uint16_t *out_status); + /**< XPI NOR driver interface: Wait when FLASH is still busy */ + hpm_stat_t + (*wait_busy)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + /**< XPI NOR driver interface: erase a specified FLASH region */ + hpm_stat_t (*erase)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start, + uint32_t length); + /**< XPI NOR driver interface: Erase the whole FLASH */ + hpm_stat_t (*erase_chip)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config); + /**< XPI NOR driver interface: Erase specified FLASH sector */ + hpm_stat_t + (*erase_sector)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + /**< XPI NOR driver interface: Erase specified FLASH block */ + hpm_stat_t + (*erase_block)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + /**< XPI NOR driver interface: Program data to specified FLASH address */ + hpm_stat_t (*program)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + const uint32_t *src, + uint32_t dst_addr, + uint32_t length); + /**< XPI NOR driver interface: read data from specified FLASH address */ + hpm_stat_t (*read)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t *dst, + uint32_t start, + uint32_t length); + /**< XPI NOR driver interface: program FLASH page using nonblocking interface */ + hpm_stat_t (*page_program_nonblocking)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + const uint32_t *src, + uint32_t dst_addr, + uint32_t length); + /**< XPI NOR driver interface: erase FLASH sector using nonblocking interface */ + hpm_stat_t (*erase_sector_nonblocking)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t addr); + /**< XPI NOR driver interface: erase FLASH block using nonblocking interface */ + hpm_stat_t (*erase_block_nonblocking)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t addr); + /**< XPI NOR driver interface: erase the whole FLASh using nonblocking interface */ + hpm_stat_t + (*erase_chip_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config); + + uint32_t reserved0[3]; + + /**< XPI NOR driver interface: automatically configuration flash based on the cfg_option setting */ + hpm_stat_t (*auto_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option); + + /**< XPI NOR driver interface: Get FLASH properties */ + hpm_stat_t (*get_property)(XPI_Type *base, xpi_nor_config_t *nor_cfg, uint32_t property_id, uint32_t *value); + +} xpi_nor_driver_interface_t; + +/** + * @brief XPI RAM driver interface + */ +typedef struct { + /**< XPI RAM driver interface: API version */ + uint32_t version; + + /**< Get XPI RAM configuration based on cfg_option */ + hpm_stat_t (*get_config)(XPI_Type *base, xpi_ram_config_t *ram_cfg, xpi_ram_config_option_t *cfg_option); + + /**< XPI RAM driver interface: Initialize XPI RAM */ + hpm_stat_t (*init)(XPI_Type *base, xpi_ram_config_t *ram_cfg); +} xpi_ram_driver_interface_t; + +/** + * @brief SDP API interface + */ +typedef struct { + /**< SDP API interface: API version */ + uint32_t version; + /**< SDP API interface: Initialize IP */ + hpm_stat_t (*sdp_ip_init)(void); + /**< SDP API interface: Deinitialize IP */ + hpm_stat_t (*sdp_ip_deinit)(void); + /**< SDP API interface: Set AES key */ + hpm_stat_t (*aes_set_key)(sdp_aes_ctx_t *aes_ctx, const uint8_t *key, sdp_aes_key_bits_t keybits, uint32_t key_idx); + /**< SDP API interface: AES ECB crypto operation */ + hpm_stat_t (*aes_crypt_ecb)(sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t len, const uint8_t *in, uint8_t *out); + /**< SDP API interface: AES CBC crypto operation */ + hpm_stat_t (*aes_crypt_cbc)(sdp_aes_ctx_t *aes_ctx, + sdp_aes_op_t op, + uint32_t length, + uint8_t iv[16], + const uint8_t *input, + uint8_t *output); + /**< SDP API interface: AES CTR crypto operation */ + hpm_stat_t + (*aes_crypt_ctr)(sdp_aes_ctx_t *aes_ctx, uint8_t *nonce_ctr, uint8_t *input, uint8_t *output, uint32_t length); + /**< SDP API interface: AES CCM encryption */ + hpm_stat_t (*aes_ccm_gen_enc)(sdp_aes_ctx_t *aes_ctx, + uint32_t input_len, + const uint8_t *nonce, + uint32_t nonce_len, + const uint8_t *aad, + uint32_t aad_len, + const uint8_t *input, + uint8_t *output, + uint8_t *tag, + uint32_t tag_len); + /**< SDP API interface: AES CCM Decrypt and verify */ + hpm_stat_t (*aes_ccm_dec_verify)(sdp_aes_ctx_t *aes_ctx, + uint32_t input_len, + const uint8_t *nonce, + uint32_t nonce_len, + const uint8_t *aad, + uint32_t aad_len, + const uint8_t *input, + uint8_t *output, + const uint8_t *tag, + uint32_t tag_len); + /**< SDP API interface: memcpy */ + hpm_stat_t (*memcpy)(sdp_dma_ctx_t *dma_ctx, void *dst, const void *src, uint32_t length); + /**< SDP API interface: memset */ + hpm_stat_t (*memset)(sdp_dma_ctx_t *dma_ctx, void *dst, uint8_t pattern, uint32_t length); + /**< SDP API interface: HASH initialization */ + hpm_stat_t (*hash_init)(sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg); + /**< SDP API interface: HASH update */ + hpm_stat_t (*hash_update)(sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length); + /**< SDP API interface: HASH finish */ + hpm_stat_t (*hash_finish)(sdp_hash_ctx_t *hash_ctx, uint8_t *digest); + /**< SDP API interface: Set SM4 Key */ + hpm_stat_t (*sm4_set_key)(sdp_sm4_ctx_t *sm4_ctx, const uint8_t *key, sdp_sm4_key_bits_t keybits, uint32_t key_idx); + /**< SDP API interface: SM4 Crypto ECB mode */ + hpm_stat_t (*sm4_crypt_ecb)(sdp_sm4_ctx_t *sm4_ctx, sdp_sm4_op_t op, uint32_t len, const uint8_t *in, uint8_t *out); + /**< SDP API Interface: SM4 Crypto CBC mode*/ + hpm_stat_t (*sm4_crypt_cbc)(sdp_sm4_ctx_t *sm4_ctx, + sdp_sm4_op_t op, + uint32_t length, + uint8_t iv[16], + const uint8_t *input, + uint8_t *output); + /**< SDP API Interface: SM4 CTR mode */ + hpm_stat_t + (*sm4_crypt_ctr)(sdp_sm4_ctx_t *sm4_ctx, uint8_t *nonce_ctr, uint8_t *input, uint8_t *output, uint32_t length); + /**< SDP API Interface: SM4 CCM Encryption */ + hpm_stat_t (*sm4_ccm_gen_enc)(sdp_sm4_ctx_t *sm4_ctx, + uint32_t input_len, + const uint8_t *nonce, + uint32_t nonce_len, + const uint8_t *aad, + uint32_t aad_len, + const uint8_t *input, + uint8_t *output, + uint8_t *tag, + uint32_t tag_len); + /**< SDP API Interface: SM4 CCM Decrypt and Verify */ + hpm_stat_t (*sm4_ccm_dec_verify)(sdp_sm4_ctx_t *sm4_ctx, + uint32_t input_len, + const uint8_t *nonce, + uint32_t nonce_len, + const uint8_t *aad, + uint32_t aad_len, + const uint8_t *input, + uint8_t *output, + const uint8_t *tag, + uint32_t tag_len); +} sdp_driver_interface_t; + +/** + * @brief Bootloader API table + */ +typedef struct { + /**< Bootloader API table: version */ + const uint32_t version; + /**< Bootloader API table: copyright string address */ + const char *copyright; + /**< Bootloader API table: run_bootloader API */ + hpm_stat_t (*run_bootloader)(void *arg); + /**< Bootloader API table: otp driver interface address */ + const otp_driver_interface_t *otp_driver_if; + /**< Bootloader API table: xpi driver interface address */ + const xpi_driver_interface_t *xpi_driver_if; + /**< Bootloader API table: xpi nor driver interface address */ + const xpi_nor_driver_interface_t *xpi_nor_driver_if; + /**< Bootloader API table: xpi ram driver interface address */ + const xpi_ram_driver_interface_t *xpi_ram_driver_if; + /**< Bootloader API table: sdp driver interface address */ + const sdp_driver_interface_t *sdp_driver_if; +} bootloader_api_table_t; + +/**< Bootloader API table Root */ +#define ROM_API_TABLE_ROOT ((const bootloader_api_table_t *)0x2001FF00U) + + +#ifdef __cplusplus +extern "C" { +#endif + +/*********************************************************************************************************************** + * + * + * Enter bootloader Wrapper + * + * + **********************************************************************************************************************/ + +/** + * @brief Eneter specified Boot mode + * @param [in] ctx Enter bootloader context + * @retval status_invalid Invalid parameters were deteced + */ +static inline hpm_stat_t rom_enter_bootloader(void *ctx) +{ + return ROM_API_TABLE_ROOT->run_bootloader(ctx); +} + +/*********************************************************************************************************************** + * + * + * XPI NOR Driver Wrapper + * + * + **********************************************************************************************************************/ + +/** + * @brief Get XPI NOR configuration via cfg_option + * @param [in] base XPI base address + * @param [out] nor_cfg XPI NOR configuration structure + * @param [in] cfg_option XPI NOR configuration option + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_get_config(XPI_Type *base, + xpi_nor_config_t *nor_cfg, + xpi_nor_config_option_t *cfg_option) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_config(base, nor_cfg, cfg_option); +} + +/** + * @brief Initialize XPI NOR based on nor_config + * @param [in] base XPI base address + * @param[in] nor_config XPI NOR configuration + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_init(XPI_Type *base, xpi_nor_config_t *nor_config) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->init(base, nor_config); +} + +/** + * @brief Erase specified FLASH region + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI nOR configuration + * @param[in] start Erase address start address + * @param[in] length Region size to be erased + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start, + uint32_t length) +{ + hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase(base, channel, nor_config, start, length); + fencei(); + return status; +} + +/** + * @brief Erase specified FLASH sector in blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] start Sector address + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_sector(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start) +{ + hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector(base, channel, nor_config, start); + fencei(); + return status; +} + +/** + * @brief Erase specified FLASH sector in non-blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] start Sector address + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_sector_nonblocking(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector_nonblocking(base, channel, nor_config, start); +} + +/** + * @brief Erase specified FLASH blcok in blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] start Block address + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_block(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start) +{ + hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block(base, channel, nor_config, start); + fencei(); + return status; +} + +/** + * @brief Erase specified FLASH blcok in non-blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] start Block address + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_block_nonblocking(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block_nonblocking(base, channel, nor_config, start); +} + +/** + * @brief Erase the whole FLASH in blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_chip(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip(base, channel, nor_config); +} + +/** + * @brief Erase the whole FLASH in non-blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_chip_nonblocking(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config) +{ + hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip_nonblocking(base, channel, nor_config); + fencei(); + return status; +} + +/** + * @brief Program data to specified FLASH address in blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] src data source address + * @param[in] dst_addr Destination FLASH address + * @param[in] length length of data to be programmed + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_program(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + const uint32_t *src, + uint32_t dst_addr, + uint32_t length) +{ + hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->program(base, channel, nor_config, src, dst_addr, length); + fencei(); + return status; +} + +/** + * @brief Page-Program data to specified FLASH address in non-blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] src data source address + * @param[in] dst_addr Destination FLASH address + * @param[in] length length of data to be programmed + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_page_program_nonblocking(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + const uint32_t *src, + uint32_t dst_addr, + uint32_t length) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if + ->page_program_nonblocking(base, channel, nor_config, src, dst_addr, length); +} + +/** + * @brief Read data from specified FLASH address + * @param [in] base XPI base address + * @param [in] channel XPI transfer channel + * @param [in] nor_config XPI NOR configuration + * @param [in] dst Memory start address to store the data read out from FLASH + * @param [in] start FLASH address for data read + * @param [in] length length of data to be read out + * @return API execution address + */ +static inline hpm_stat_t rom_xpi_nor_read(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t *dst, + uint32_t start, + uint32_t length) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->read(base, channel, nor_config, dst, start, length); +} + +/** + * @brief Automatically configure XPI NOR based on cfg_option + * @param [in] base XPI base address + * @param [out] config XPI NOR configuration structure + * @param [in] cfg_option XPI NOR configuration option + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_auto_config(XPI_Type *base, + xpi_nor_config_t *config, + xpi_nor_config_option_t *cfg_option) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->auto_config(base, config, cfg_option); +} + +/** + * @brief Get XPI NOR properties + * @param [in] base XPI base address + * @param [in] nor_cfg XPI NOR configuration structure + * @param [in] property_id + * @param [out] value property value retrieved by this API + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_get_property(XPI_Type *base, + xpi_nor_config_t *nor_cfg, + uint32_t property_id, + uint32_t *value) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_property(base, nor_cfg, property_id, value); +} + +/** + * @brief Return the status register value on XPI NOR FLASH + * + * @param [in] base XPI base address + * @param [in] channel XPI transfer channel + * @param [in] nor_config XPI NOR configuration + * @param [in] addr FLASH address offset + * @param [out] out_status FLASH status register value + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_get_status(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t addr, + uint16_t *out_status) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_status(base, channel, nor_config, addr, out_status); +} + +/** + * @brief Configure the XPI Address Remapping Logic + * @param [in] base XPI base address + * @param [in] start Start Address (memory mapped address) + * @param [in] len Size for the remapping region + * @param [in] offset Relative address based on parameter "start" + * @retval true is all parameters are valid + * @retval false if any parameter is invalid + */ +ATTR_RAMFUNC +static inline bool rom_xpi_nor_remap_config(XPI_Type *base, uint32_t start, uint32_t len, uint32_t offset) +{ + if ((base != HPM_XPI0) || ((start & 0xFFF) != 0) || ((len & 0xFFF) != 0) + || ((offset & 0xFFF) != 0)) { + return false; + } + static const uint8_t k_mc_xpi_remap_config[] = { + 0x2e, 0x96, 0x23, 0x22, 0xc5, 0x42, 0x23, 0x24, + 0xd5, 0x42, 0x93, 0xe5, 0x15, 0x00, 0x23, 0x20, + 0xb5, 0x42, 0x05, 0x45, 0x82, 0x80, + }; + typedef bool (*remap_config_cb_t)(XPI_Type *, uint32_t, uint32_t, uint32_t); + remap_config_cb_t cb = (remap_config_cb_t) &k_mc_xpi_remap_config; + bool result = cb(base, start, len, offset); + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); + fencei(); + return result; +} + +/** + * @brief Disable XPI Remapping logic + * @param [in] base XPI base address + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_remap_disable(XPI_Type *base) +{ + static const uint8_t k_mc_xpi_remap_disable[] = { + 0x83, 0x27, 0x05, 0x42, 0xf9, 0x9b, 0x23, 0x20, + 0xf5, 0x42, 0x82, 0x80, + }; + typedef void (*remap_disable_cb_t)(XPI_Type *); + remap_disable_cb_t cb = (remap_disable_cb_t) &k_mc_xpi_remap_disable; + cb(base); + fencei(); +} + +/** + * @brief Check whether XPI Remapping is enabled + * @param [in] base XPI base address + * + * @retval true Remapping logic is enabled + * @retval false Remapping logic is disabled + */ +ATTR_RAMFUNC +static inline bool rom_xpi_nor_is_remap_enabled(XPI_Type *base) +{ + static const uint8_t k_mc_xpi_remap_enabled[] = { + 0x03, 0x25, 0x05, 0x42, 0x05, 0x89, 0x82, 0x80, + }; + typedef bool (*remap_chk_cb_t)(XPI_Type *); + remap_chk_cb_t chk_cb = (remap_chk_cb_t) &k_mc_xpi_remap_enabled; + return chk_cb(base); +} + +/** + * @brief Configure Specified EXiP Region + * @param [in] base XPI base address + * @param [in] index EXiP Region index + * @param [in] param ExiP Region Parameter + * @retval true All parameters are valid + * @retval false Any parameter is invalid + */ +ATTR_RAMFUNC +static inline bool rom_xpi_nor_exip_region_config(XPI_Type *base, uint32_t index, exip_region_param_t *param) +{ + if (base != HPM_XPI0) { + return false; + } + static const uint8_t k_mc_exip_region_config[] = { + 0x18, 0x4a, 0x9a, 0x05, 0x2e, 0x95, 0x85, 0x67, + 0xaa, 0x97, 0x23, 0xa4, 0xe7, 0xd0, 0x4c, 0x4a, + 0x14, 0x42, 0x58, 0x42, 0x23, 0xa6, 0xb7, 0xd0, + 0x4c, 0x46, 0x36, 0x97, 0x13, 0x77, 0x07, 0xc0, + 0x23, 0xa2, 0xb7, 0xd0, 0x0c, 0x46, 0x13, 0x67, + 0x37, 0x00, 0x05, 0x45, 0x23, 0xa0, 0xb7, 0xd0, + 0x0c, 0x4e, 0x23, 0xaa, 0xb7, 0xd0, 0x50, 0x4e, + 0x23, 0xa8, 0xc7, 0xd0, 0x23, 0xac, 0xd7, 0xd0, + 0x23, 0xae, 0xe7, 0xd0, 0x82, 0x80, + }; + typedef void (*exip_region_config_cb_t)(XPI_Type *, uint32_t, exip_region_param_t *); + exip_region_config_cb_t cb = (exip_region_config_cb_t) &k_mc_exip_region_config; + cb(base, index, param); + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); + fencei(); + return true; +} + +/** + * @brief Disable EXiP Feature on specified EXiP Region + * @param [in] base XPI base address + * @param [in] index EXiP Region index + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_exip_region_disable(XPI_Type *base, uint32_t index) +{ + static const uint8_t k_mc_exip_region_disable[] = { + 0x9a, 0x05, 0x2e, 0x95, 0x85, 0x67, 0xaa, 0x97, + 0x03, 0xa7, 0xc7, 0xd1, 0x75, 0x9b, 0x23, 0xae, + 0xe7, 0xd0, 0x82, 0x80 + }; + typedef void (*exip_region_disable_cb_t)(XPI_Type *, uint32_t); + exip_region_disable_cb_t cb = (exip_region_disable_cb_t) &k_mc_exip_region_disable; + cb(base, index); + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); + fencei(); +} + +/** + * @brief Enable global EXiP logic + * @param [in] base XPI base address + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_exip_enable(XPI_Type *base) +{ + static const uint8_t k_mc_exip_enable[] = { + 0x85, 0x67, 0x3e, 0x95, 0x83, 0x27, 0x05, 0xc0, + 0x37, 0x07, 0x00, 0x80, 0xd9, 0x8f, 0x23, 0x20, + 0xf5, 0xc0, 0x82, 0x80 + }; + typedef void (*exip_enable_cb_t)(XPI_Type *); + exip_enable_cb_t cb = (exip_enable_cb_t) &k_mc_exip_enable; + cb(base); +} + +/** + * @brief Disable global EXiP logic + * @param [in] base XPI base address + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_exip_disable(XPI_Type *base) +{ + static const uint8_t k_mc_exip_disable[] = { + 0x85, 0x67, 0x3e, 0x95, 0x83, 0x27, 0x05, 0xc0, + 0x86, 0x07, 0x85, 0x83, 0x23, 0x20, 0xf5, 0xc0, + 0x82, 0x80 + }; + typedef void (*exip_disable_cb_t)(XPI_Type *); + exip_disable_cb_t cb = (exip_disable_cb_t) &k_mc_exip_disable; + cb(base); + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); + fencei(); +} + +/*********************************************************************************************************************** + * + * + * XPI RAM Driver Wrapper + * + * + **********************************************************************************************************************/ +/** + * @brief Get XPI RAM configuration based on cfg_option + * @param [in] base XPI base address + * @param [out] ram_cfg XPI RAM configuration structure + * @param [in] cfg_option XPI RAM configuration option + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_ram_get_config(XPI_Type *base, + xpi_ram_config_t *ram_cfg, + xpi_ram_config_option_t *cfg_option) +{ + return ROM_API_TABLE_ROOT->xpi_ram_driver_if->get_config(base, ram_cfg, cfg_option); +} + +/** + * @brief Initialize XPI RAM + * @param [in] base XPI base address + * @param [in] ram_cfg XPI ram configuration + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_ram_init(XPI_Type *base, xpi_ram_config_t *ram_cfg) +{ + return ROM_API_TABLE_ROOT->xpi_ram_driver_if->init(base, ram_cfg); +} + +/*********************************************************************************************************************** + * + * + * SDP Driver Wrapper + * + * + **********************************************************************************************************************/ +/** + * @brief Initialize SDP IP + */ +static inline void rom_sdp_init(void) +{ + ROM_API_TABLE_ROOT->sdp_driver_if->sdp_ip_init(); +} + +/** + * @brief De-initialize SDP IP + */ +static inline void rom_sdp_deinit(void) +{ + ROM_API_TABLE_ROOT->sdp_driver_if->sdp_ip_deinit(); +} + +/** + * @brief Set AES key to SDP + * @param [in] aes_ctx AES context + * @param [in] key AES key buffer + * @param [in] key_bits AES key-bit option + * @param[in] key_idx AES key index + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_aes_set_key(sdp_aes_ctx_t *aes_ctx, + const uint8_t *key, + sdp_aes_key_bits_t key_bits, + uint32_t key_idx) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->aes_set_key(aes_ctx, key, key_bits, key_idx); +} + +/** + * @brief SDP AES ECB crypto operation(Encrypt or Decrypt) + * @param [in] aes_ctx AES context + * @param [in] op AES operation: encrypt or decrypt + * @param [in] len Data length for AES encryption/decryption + * @param [in] in Input data + * @param [out] out Output data + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_aes_crypt_ecb(sdp_aes_ctx_t *aes_ctx, + sdp_aes_op_t op, + uint32_t len, + const uint8_t *in, + uint8_t *out) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->aes_crypt_ecb(aes_ctx, op, len, in, out); +} + +/** + * @brief SDP AES CBC crypto operation(Encrypt or Decrypt) + * @param [in] aes_ctx AES context + * @param [in] op AES operation: encrypt or decrypt + * @param [in] length Data length for AES encryption/decryption + * @param [in] iv Initial vector/nonce + * @param [in] in Input data + * @param [out] out Output data + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_aes_crypt_cbc(sdp_aes_ctx_t *aes_ctx, + sdp_aes_op_t op, + uint32_t length, + uint8_t iv[16], + const uint8_t *in, + uint8_t *out) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->aes_crypt_cbc(aes_ctx, op, length, iv, in, out); +} + +/** + * @brief Set SM4 key to SDP + * @param [in] sm4_ctx SM4 context + * @param [in] key SM4 key buffer + * @param [in] key_bits SM4 key-bit option + * @param[in] key_idx SM4 key index + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_sm4_set_key(sdp_sm4_ctx_t *sm4_ctx, + const uint8_t *key, + sdp_sm4_key_bits_t key_bits, + uint32_t key_idx) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->sm4_set_key(sm4_ctx, key, key_bits, key_idx); +} + +/** + * @brief SDP SM4 ECB crypto operation(Encrypt or Decrypt) + * @param [in] sm4_ctx SM4 context + * @param [in] op SM4 operation: encrypt or decrypt + * @param [in] len Data length for SM4 encryption/decryption + * @param [in] in Input data + * @param [out] out Output data + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_sm4_crypt_ecb(sdp_sm4_ctx_t *sm4_ctx, + sdp_sm4_op_t op, + uint32_t len, + const uint8_t *in, + uint8_t *out) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->sm4_crypt_ecb(sm4_ctx, op, len, in, out); +} + +/** + * @brief SDP SM4 CBC crypto operation(Encrypt or Decrypt) + * @param [in] sm4_ctx SM4 context + * @param [in] op SM4 operation: encrypt or decrypt + * @param [in] length Data length for SM4 encryption/decryption + * @param [in] iv Initial vector/nonce + * @param [in] in Input data + * @param [out] out Output data + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_sm4_crypt_cbc(sdp_sm4_ctx_t *sm4_ctx, + sdp_sm4_op_t op, + uint32_t length, + uint8_t iv[16], + const uint8_t *in, + uint8_t *out) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->sm4_crypt_cbc(sm4_ctx, op, length, iv, in, out); +} + +/** + * @brief HASH initialization + * @param [in] hash_ctx HASH context + * @param [in] alg HASH algorithm + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_hash_init(sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->hash_init(hash_ctx, alg); +} + +/** + * @brief HASH Update + * @param [in] hash_ctx HASH context + * @param [in] data Data for HASH operation + * @param [in] length of the data for HASH operation + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_hash_update(sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->hash_update(hash_ctx, data, length); +} + +/** + * @brief HASH finialize + * @param [in] hash_ctx HASH context + * @param [out] digest the output digest + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_hash_finish(sdp_hash_ctx_t *hash_ctx, uint8_t *digest) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->hash_finish(hash_ctx, digest); +} + +/** + * @brief SDP memcpy operation + * @param [in] dma_ctx DMA context + * @param [out] dst Destination address for memcpy + * @param [in] src Source address for memcpy + * @param [in] length Size of data for memcpy operation + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_memcpy(sdp_dma_ctx_t *dma_ctx, void *dst, const void *src, uint32_t length) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->memcpy(dma_ctx, dst, src, length); +} + +/** + * @brief SDP memset operation + * @param [in] dma_ctx DMA context + * @param [out] dst Destination address for memset + * @param [in] pattern pattern for memset + * @param [in] length Size of data for memset operation + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_memset(sdp_dma_ctx_t *dma_ctx, void *dst, uint8_t pattern, uint32_t length) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->memset(dma_ctx, dst, pattern, length); +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + + +#endif /* HPM_ROMAPI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_romapi_xpi_soc_def.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_romapi_xpi_soc_def.h new file mode 100644 index 00000000000..ea3ba9e8f9b --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_romapi_xpi_soc_def.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_ROMAPI_XPI_SOC_DEF_H +#define HPM_ROMAPI_XPI_SOC_DEF_H + +#include "hpm_common.h" +#include "hpm_romapi_xpi_def.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +#define XPI_CLK_OUT_FREQ_OPTION_30MHz (1U) +#define XPI_CLK_OUT_FREQ_OPTION_50MHz (2U) +#define XPI_CLK_OUT_FREQ_OPTION_66MHz (3U) +#define XPI_CLK_OUT_FREQ_OPTION_80MHz (4U) +#define XPI_CLK_OUT_FREQ_OPTION_104MHz (5U) +#define XPI_CLK_OUT_FREQ_OPTION_120MHz (6U) +#define XPI_CLK_OUT_FREQ_OPTION_133MHz (7U) +#define XPI_CLK_OUT_FREQ_OPTION_166MHz (8U) +#define XPI_CLK_OUT_FREQ_OPTION_200MHz (9U) + +typedef struct { + struct { + uint8_t priority; /* Offset: 0x00 */ + uint8_t master_idx; /* Offset: 0x01 */ + uint8_t buf_size_in_dword; /* Offset: 0x02 */ + bool enable_prefetch; /* Offset: 0x03 */ + } entry[8]; +} xpi_ahb_buffer_cfg_t; + +typedef struct { + uint8_t data_pads; + xpi_channel_t channel; + xpi_io_group_t io_group; + uint8_t drive_strength; + bool enable_dqs; + bool enable_diff_clk; +} xpi_io_config_t; + +typedef enum { + xpi_freq_type_typical, + xpi_freq_type_mhz, +} clk_freq_type_t; + +typedef enum { + xpi_clk_src_auto, + xpi_clk_src_osc, + xpi_clk_src_pll0clk0, + xpi_clk_src_pll1clk0, + xpi_clk_src_pll1clk1, + xpi_clk_src_pll2clk0, + xpi_clk_src_pll2clk1, + xpi_clk_src_pll3clk0, + xpi_clk_src_pll4clk0, +} xpi_clk_src_t; + + +typedef union { + struct { + uint8_t freq; + bool enable_ddr; + xpi_clk_src_t clk_src; + clk_freq_type_t freq_type; + }; + uint32_t freq_opt; +} xpi_clk_config_t; + +typedef enum { + xpi_clock_bus, + xpi_clock_serial_root, + xpi_clock_serial, +} xpi_clock_t; + +#endif /* HPM_ROMAPI_XPI_SOC_DEF_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_sdxc_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_sdxc_soc_drv.h new file mode 100644 index 00000000000..26782aa2e3f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_sdxc_soc_drv.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2022-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_SDXC_SOC_DRV_H +#define HPM_SDXC_SOC_DRV_H + +#include "hpm_soc.h" +#include "hpm_sdxc_regs.h" + +#if defined(__cplusplus) +extern "C" { +#endif + + +static inline void sdxc_enable_tm_clock(SDXC_Type *base) +{ + base->MISC_CTRL0 |= SDXC_MISC_CTRL0_TMCLK_EN_MASK; +} + +static inline void sdxc_enable_freq_selection(SDXC_Type *base) +{ + base->MISC_CTRL0 |= SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK; +} + +static inline void sdxc_disable_freq_selection(SDXC_Type *base) +{ + base->MISC_CTRL0 &= ~SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK; +} + +/** + * @brief Set SDXC clock divider + * @param [in] base SDXC base + * @param [in] div SDXC divider + */ +static inline void sdxc_set_clock_divider(SDXC_Type *base, uint32_t div) +{ + base->MISC_CTRL0 = + (base->MISC_CTRL0 & ~SDXC_MISC_CTRL0_FREQ_SEL_SW_MASK) | SDXC_MISC_CTRL0_FREQ_SEL_SW_SET(div - 1U) | + SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK; +} + +/** + * @brief Get SDXC divider + * @param [in] base SDXC base + * @return SDXC divider value + */ +static inline uint32_t sdxc_get_clock_divider(SDXC_Type *base) +{ + return (1U + SDXC_MISC_CTRL0_FREQ_SEL_SW_GET(base->MISC_CTRL0)); +} + +/** + * @brief Wait at least 74 clocks until card is ready to receive the first command + */ +static inline void sdxc_wait_card_active(SDXC_Type *base) +{ + base->SYS_CTRL |= SDXC_SYS_CTRL_SD_CLK_EN_MASK; + + base->MISC_CTRL1 |= SDXC_MISC_CTRL1_CARD_ACTIVE_MASK; + + while (!IS_HPM_BITMASK_SET(base->MISC_CTRL1, SDXC_MISC_CTRL1_CARD_ACTIVE_MASK)) { + } +} + +/** + * @brief Inverse SDXC clock + * @param [in] base SDXC base + * @param [in] enable Enable/disable SDXC inverse clock + */ +static inline void sdxc_enable_inverse_clock(SDXC_Type *base, bool enable) +{ + if (enable) { + base->MISC_CTRL0 |= SDXC_MISC_CTRL0_CARDCLK_INV_EN_MASK; + } else { + base->MISC_CTRL0 &= ~SDXC_MISC_CTRL0_CARDCLK_INV_EN_MASK; + } +} + +/** + * @brief Check whether SDXC inverse clock is enabled or not + * @param [in] base SDXC base + * + * @retval true if inverse clock is enabled + */ +static inline bool sdxc_is_inverse_clock_enabled(SDXC_Type *base) +{ + return ((base->MISC_CTRL0 & SDXC_MISC_CTRL0_CARDCLK_INV_EN_MASK) != 0U); +} + +/** + * @brief Select the Card Clock Delay source + * @param [in] base SDXC base + * @param [in] loopback_from_pad true if the delay source is loopback from pad + */ +static inline void sdxc_select_cardclk_delay_source(SDXC_Type *base, bool loopback_from_pad) +{ + if (loopback_from_pad) { + base->MISC_CTRL0 &= ~SDXC_MISC_CTRL0_PAD_CLK_SEL_B_MASK; + } else { + base->MISC_CTRL0 |= SDXC_MISC_CTRL0_PAD_CLK_SEL_B_MASK; + } +} + +/** + * @brief Set Card Clock delay chain + * @param [in] base SDXC base + * @param [in] num_delaycells Number of delay cells + */ +static inline void sdxc_set_cardclk_delay_chain(SDXC_Type *base, uint32_t num_delaycells) +{ + base->MISC_CTRL1 = (base->MISC_CTRL1 & ~SDXC_MISC_CTRL1_CARDCLK_DLYSEL_MASK) | + SDXC_MISC_CTRL1_CARDCLK_DLYSEL_SET(num_delaycells); +} + +/** + * @brief Set SDXC data strobe delay chain + * @param [in] base SDXC base + * @param [in] num_of_delaycells Number of delay cells for Data strobe + */ +static inline void sdxc_set_data_strobe_delay(SDXC_Type *base, uint8_t num_of_delaycells) +{ + base->MISC_CTRL1 = (base->MISC_CTRL1 & ~SDXC_MISC_CTRL1_STROBE_DLYSEL_MASK) | + SDXC_MISC_CTRL1_STROBE_DLYSEL_SET(num_of_delaycells); +} + +static inline uint32_t sdxc_get_default_strobe_delay(SDXC_Type *base) +{ + (void) base; + uint32_t num_delaycells = 0; + if (IOC_PAD_FUNC_CTL_ALT_SELECT_GET(HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL) == IOC_PC00_FUNC_CTL_SDC0_DS) { + num_delaycells = 2; + } + return num_delaycells; +} + +static inline uint32_t sdxc_get_default_cardclk_delay_chain(SDXC_Type *base, uint32_t clock_freq) +{ + (void) base; + uint32_t num_delaycells = 3; + if (clock_freq <= 52000000) { + num_delaycells = 26; + } + return num_delaycells; +} + +static inline bool sdxc_is_ddr50_supported(SDXC_Type *base) +{ + (void) base; + return true; +} + + +#if defined(__cplusplus) +} +#endif + + +#endif /* HPM_SDXC_SOC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_ses_reg.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_ses_reg.xml new file mode 100644 index 00000000000..7f6a02b9a5b --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_ses_reg.xml @@ -0,0 +1,60238 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_ses_riscv_cpu_regs.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_ses_riscv_cpu_regs.xml new file mode 100644 index 00000000000..9e30fbc73a7 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_ses_riscv_cpu_regs.xml @@ -0,0 +1,770 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_soc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_soc.h new file mode 100644 index 00000000000..849447a61de --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_soc.h @@ -0,0 +1,814 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_SOC_H +#define HPM_SOC_H + + +/* List of external IRQs */ +#define IRQn_GPIO0_A 1 /* GPIO0_A IRQ */ +#define IRQn_GPIO0_B 2 /* GPIO0_B IRQ */ +#define IRQn_GPIO0_C 3 /* GPIO0_C IRQ */ +#define IRQn_GPIO0_D 4 /* GPIO0_D IRQ */ +#define IRQn_GPIO0_E 5 /* GPIO0_E IRQ */ +#define IRQn_GPIO0_F 6 /* GPIO0_F IRQ */ +#define IRQn_GPIO0_X 7 /* GPIO0_X IRQ */ +#define IRQn_GPIO0_Y 8 /* GPIO0_Y IRQ */ +#define IRQn_GPIO0_Z 9 /* GPIO0_Z IRQ */ +#define IRQn_MCAN0 10 /* MCAN0 IRQ */ +#define IRQn_MCAN1 11 /* MCAN1 IRQ */ +#define IRQn_MCAN2 12 /* MCAN2 IRQ */ +#define IRQn_MCAN3 13 /* MCAN3 IRQ */ +#define IRQn_MCAN4 14 /* MCAN4 IRQ */ +#define IRQn_MCAN5 15 /* MCAN5 IRQ */ +#define IRQn_MCAN6 16 /* MCAN6 IRQ */ +#define IRQn_MCAN7 17 /* MCAN7 IRQ */ +#define IRQn_PTPC 18 /* PTPC IRQ */ +#define IRQn_UART0 27 /* UART0 IRQ */ +#define IRQn_UART1 28 /* UART1 IRQ */ +#define IRQn_UART2 29 /* UART2 IRQ */ +#define IRQn_UART3 30 /* UART3 IRQ */ +#define IRQn_UART4 31 /* UART4 IRQ */ +#define IRQn_UART5 32 /* UART5 IRQ */ +#define IRQn_UART6 33 /* UART6 IRQ */ +#define IRQn_UART7 34 /* UART7 IRQ */ +#define IRQn_I2C0 35 /* I2C0 IRQ */ +#define IRQn_I2C1 36 /* I2C1 IRQ */ +#define IRQn_I2C2 37 /* I2C2 IRQ */ +#define IRQn_I2C3 38 /* I2C3 IRQ */ +#define IRQn_SPI0 39 /* SPI0 IRQ */ +#define IRQn_SPI1 40 /* SPI1 IRQ */ +#define IRQn_SPI2 41 /* SPI2 IRQ */ +#define IRQn_SPI3 42 /* SPI3 IRQ */ +#define IRQn_GPTMR0 43 /* GPTMR0 IRQ */ +#define IRQn_GPTMR1 44 /* GPTMR1 IRQ */ +#define IRQn_GPTMR2 45 /* GPTMR2 IRQ */ +#define IRQn_GPTMR3 46 /* GPTMR3 IRQ */ +#define IRQn_GPTMR4 47 /* GPTMR4 IRQ */ +#define IRQn_GPTMR5 48 /* GPTMR5 IRQ */ +#define IRQn_GPTMR6 49 /* GPTMR6 IRQ */ +#define IRQn_GPTMR7 50 /* GPTMR7 IRQ */ +#define IRQn_EWDG0 51 /* EWDG0 IRQ */ +#define IRQn_EWDG1 52 /* EWDG1 IRQ */ +#define IRQn_MBX0A 53 /* MBX0A IRQ */ +#define IRQn_MBX0B 54 /* MBX0B IRQ */ +#define IRQn_MBX1A 55 /* MBX1A IRQ */ +#define IRQn_MBX1B 56 /* MBX1B IRQ */ +#define IRQn_RNG 57 /* RNG IRQ */ +#define IRQn_HDMA 58 /* HDMA IRQ */ +#define IRQn_ADC0 59 /* ADC0 IRQ */ +#define IRQn_ADC1 60 /* ADC1 IRQ */ +#define IRQn_SDM 61 /* SDM IRQ */ +#define IRQn_OPAMP 62 /* OPAMP IRQ */ +#define IRQn_I2S0 63 /* I2S0 IRQ */ +#define IRQn_I2S1 64 /* I2S1 IRQ */ +#define IRQn_I2S2 65 /* I2S2 IRQ */ +#define IRQn_I2S3 66 /* I2S3 IRQ */ +#define IRQn_DAO 67 /* DAO IRQ */ +#define IRQn_PDM 68 /* PDM IRQ */ +#define IRQn_SMIX_DMA 69 /* SMIX_DMA IRQ */ +#define IRQn_SMIX_ASRC 70 /* SMIX_ASRC IRQ */ +#define IRQn_CAM0 71 /* CAM0 IRQ */ +#define IRQn_CAM1 72 /* CAM1 IRQ */ +#define IRQn_LCDC 73 /* LCDC IRQ */ +#define IRQn_LCDC1 74 /* LCDC1 IRQ */ +#define IRQn_PDMA 75 /* PDMA IRQ */ +#define IRQn_JPEG 76 /* JPEG IRQ */ +#define IRQn_GWCK0_FUNC 77 /* GWCK0_FUNC IRQ */ +#define IRQn_GWCK0_ERR 78 /* GWCK0_ERR IRQ */ +#define IRQn_GWCK1_FUNC 79 /* GWCK1_FUNC IRQ */ +#define IRQn_GWCK1_ERR 80 /* GWCK1_ERR IRQ */ +#define IRQn_MIPI_DSI0 81 /* MIPI_DSI0 IRQ */ +#define IRQn_MIPI_DSI1 82 /* MIPI_DSI1 IRQ */ +#define IRQn_MIPI_CSI0 83 /* MIPI_CSI0 IRQ */ +#define IRQn_MIPI_CSI0_AP 84 /* MIPI_CSI0_AP IRQ */ +#define IRQn_MIPI_CSI0_DIAG 85 /* MIPI_CSI0_DIAG IRQ */ +#define IRQn_MIPI_CSI1_AP 86 /* MIPI_CSI1_AP IRQ */ +#define IRQn_MIPI_CSI1_DIAG 87 /* MIPI_CSI1_DIAG IRQ */ +#define IRQn_MIPI_CSI1 88 /* MIPI_CSI1 IRQ */ +#define IRQn_LCB0 89 /* LCB0 IRQ */ +#define IRQn_LCB1 90 /* LCB1 IRQ */ +#define IRQn_GPU 91 /* GPU IRQ */ +#define IRQn_ENET0 92 /* ENET0 IRQ */ +#define IRQn_NTMR0 93 /* NTMR0 IRQ */ +#define IRQn_USB0 94 /* USB0 IRQ */ +#define IRQn_SDXC0 95 /* SDXC0 IRQ */ +#define IRQn_SDXC1 96 /* SDXC1 IRQ */ +#define IRQn_SDP 97 /* SDP IRQ */ +#define IRQn_XPI0 98 /* XPI0 IRQ */ +#define IRQn_XDMA 99 /* XDMA IRQ */ +#define IRQn_DDR 100 /* DDR IRQ */ +#define IRQn_FFA 101 /* FFA IRQ */ +#define IRQn_PSEC 102 /* PSEC IRQ */ +#define IRQn_TSNS 103 /* TSNS IRQ */ +#define IRQn_VAD 104 /* VAD IRQ */ +#define IRQn_PGPIO 105 /* PGPIO IRQ */ +#define IRQn_PWDG 106 /* PWDG IRQ */ +#define IRQn_PTMR 107 /* PTMR IRQ */ +#define IRQn_PUART 108 /* PUART IRQ */ +#define IRQn_FUSE 109 /* FUSE IRQ */ +#define IRQn_SECMON 110 /* SECMON IRQ */ +#define IRQn_RTC 111 /* RTC IRQ */ +#define IRQn_BGPIO 112 /* BGPIO IRQ */ +#define IRQn_BVIO 113 /* BVIO IRQ */ +#define IRQn_BROWNOUT 114 /* BROWNOUT IRQ */ +#define IRQn_SYSCTL 115 /* SYSCTL IRQ */ +#define IRQn_DEBUG0 116 /* DEBUG0 IRQ */ +#define IRQn_DEBUG1 117 /* DEBUG1 IRQ */ + +#include "hpm_common.h" + +#include "hpm_gpio_regs.h" +/* Address of GPIO instances */ +/* FGPIO base address */ +#define HPM_FGPIO_BASE (0xC0000UL) +/* FGPIO base pointer */ +#define HPM_FGPIO ((GPIO_Type *) HPM_FGPIO_BASE) +/* GPIO0 base address */ +#define HPM_GPIO0_BASE (0xF00D0000UL) +/* GPIO0 base pointer */ +#define HPM_GPIO0 ((GPIO_Type *) HPM_GPIO0_BASE) +/* PGPIO base address */ +#define HPM_PGPIO_BASE (0xF411C000UL) +/* PGPIO base pointer */ +#define HPM_PGPIO ((GPIO_Type *) HPM_PGPIO_BASE) +/* BGPIO base address */ +#define HPM_BGPIO_BASE (0xF4214000UL) +/* BGPIO base pointer */ +#define HPM_BGPIO ((GPIO_Type *) HPM_BGPIO_BASE) + +/* Address of DM instances */ +/* DM base address */ +#define HPM_DM_BASE (0x30000000UL) + +#include "hpm_plic_regs.h" +/* Address of PLIC instances */ +/* PLIC base address */ +#define HPM_PLIC_BASE (0xE4000000UL) +/* PLIC base pointer */ +#define HPM_PLIC ((PLIC_Type *) HPM_PLIC_BASE) + +#include "hpm_mchtmr_regs.h" +/* Address of MCHTMR instances */ +/* MCHTMR base address */ +#define HPM_MCHTMR_BASE (0xE6000000UL) +/* MCHTMR base pointer */ +#define HPM_MCHTMR ((MCHTMR_Type *) HPM_MCHTMR_BASE) + +#include "hpm_plic_sw_regs.h" +/* Address of PLICSW instances */ +/* PLICSW base address */ +#define HPM_PLICSW_BASE (0xE6400000UL) +/* PLICSW base pointer */ +#define HPM_PLICSW ((PLIC_SW_Type *) HPM_PLICSW_BASE) + +#include "hpm_crc_regs.h" +/* Address of CRC instances */ +/* CRC base address */ +#define HPM_CRC_BASE (0xF000C000UL) +/* CRC base pointer */ +#define HPM_CRC ((CRC_Type *) HPM_CRC_BASE) + +#include "hpm_uart_regs.h" +/* Address of UART instances */ +/* UART0 base address */ +#define HPM_UART0_BASE (0xF0040000UL) +/* UART0 base pointer */ +#define HPM_UART0 ((UART_Type *) HPM_UART0_BASE) +/* UART1 base address */ +#define HPM_UART1_BASE (0xF0044000UL) +/* UART1 base pointer */ +#define HPM_UART1 ((UART_Type *) HPM_UART1_BASE) +/* UART2 base address */ +#define HPM_UART2_BASE (0xF0048000UL) +/* UART2 base pointer */ +#define HPM_UART2 ((UART_Type *) HPM_UART2_BASE) +/* UART3 base address */ +#define HPM_UART3_BASE (0xF004C000UL) +/* UART3 base pointer */ +#define HPM_UART3 ((UART_Type *) HPM_UART3_BASE) +/* UART4 base address */ +#define HPM_UART4_BASE (0xF0050000UL) +/* UART4 base pointer */ +#define HPM_UART4 ((UART_Type *) HPM_UART4_BASE) +/* UART5 base address */ +#define HPM_UART5_BASE (0xF0054000UL) +/* UART5 base pointer */ +#define HPM_UART5 ((UART_Type *) HPM_UART5_BASE) +/* UART6 base address */ +#define HPM_UART6_BASE (0xF0058000UL) +/* UART6 base pointer */ +#define HPM_UART6 ((UART_Type *) HPM_UART6_BASE) +/* UART7 base address */ +#define HPM_UART7_BASE (0xF005C000UL) +/* UART7 base pointer */ +#define HPM_UART7 ((UART_Type *) HPM_UART7_BASE) +/* PUART base address */ +#define HPM_PUART_BASE (0xF4124000UL) +/* PUART base pointer */ +#define HPM_PUART ((UART_Type *) HPM_PUART_BASE) + +#include "hpm_i2c_regs.h" +/* Address of I2C instances */ +/* I2C0 base address */ +#define HPM_I2C0_BASE (0xF0060000UL) +/* I2C0 base pointer */ +#define HPM_I2C0 ((I2C_Type *) HPM_I2C0_BASE) +/* I2C1 base address */ +#define HPM_I2C1_BASE (0xF0064000UL) +/* I2C1 base pointer */ +#define HPM_I2C1 ((I2C_Type *) HPM_I2C1_BASE) +/* I2C2 base address */ +#define HPM_I2C2_BASE (0xF0068000UL) +/* I2C2 base pointer */ +#define HPM_I2C2 ((I2C_Type *) HPM_I2C2_BASE) +/* I2C3 base address */ +#define HPM_I2C3_BASE (0xF006C000UL) +/* I2C3 base pointer */ +#define HPM_I2C3 ((I2C_Type *) HPM_I2C3_BASE) + +#include "hpm_spi_regs.h" +/* Address of SPI instances */ +/* SPI0 base address */ +#define HPM_SPI0_BASE (0xF0070000UL) +/* SPI0 base pointer */ +#define HPM_SPI0 ((SPI_Type *) HPM_SPI0_BASE) +/* SPI1 base address */ +#define HPM_SPI1_BASE (0xF0074000UL) +/* SPI1 base pointer */ +#define HPM_SPI1 ((SPI_Type *) HPM_SPI1_BASE) +/* SPI2 base address */ +#define HPM_SPI2_BASE (0xF0078000UL) +/* SPI2 base pointer */ +#define HPM_SPI2 ((SPI_Type *) HPM_SPI2_BASE) +/* SPI3 base address */ +#define HPM_SPI3_BASE (0xF007C000UL) +/* SPI3 base pointer */ +#define HPM_SPI3 ((SPI_Type *) HPM_SPI3_BASE) + +#include "hpm_gptmr_regs.h" +/* Address of TMR instances */ +/* GPTMR0 base address */ +#define HPM_GPTMR0_BASE (0xF0080000UL) +/* GPTMR0 base pointer */ +#define HPM_GPTMR0 ((GPTMR_Type *) HPM_GPTMR0_BASE) +/* GPTMR1 base address */ +#define HPM_GPTMR1_BASE (0xF0084000UL) +/* GPTMR1 base pointer */ +#define HPM_GPTMR1 ((GPTMR_Type *) HPM_GPTMR1_BASE) +/* GPTMR2 base address */ +#define HPM_GPTMR2_BASE (0xF0088000UL) +/* GPTMR2 base pointer */ +#define HPM_GPTMR2 ((GPTMR_Type *) HPM_GPTMR2_BASE) +/* GPTMR3 base address */ +#define HPM_GPTMR3_BASE (0xF008C000UL) +/* GPTMR3 base pointer */ +#define HPM_GPTMR3 ((GPTMR_Type *) HPM_GPTMR3_BASE) +/* GPTMR4 base address */ +#define HPM_GPTMR4_BASE (0xF0090000UL) +/* GPTMR4 base pointer */ +#define HPM_GPTMR4 ((GPTMR_Type *) HPM_GPTMR4_BASE) +/* GPTMR5 base address */ +#define HPM_GPTMR5_BASE (0xF0094000UL) +/* GPTMR5 base pointer */ +#define HPM_GPTMR5 ((GPTMR_Type *) HPM_GPTMR5_BASE) +/* GPTMR6 base address */ +#define HPM_GPTMR6_BASE (0xF0098000UL) +/* GPTMR6 base pointer */ +#define HPM_GPTMR6 ((GPTMR_Type *) HPM_GPTMR6_BASE) +/* GPTMR7 base address */ +#define HPM_GPTMR7_BASE (0xF009C000UL) +/* GPTMR7 base pointer */ +#define HPM_GPTMR7 ((GPTMR_Type *) HPM_GPTMR7_BASE) +/* NTMR0 base address */ +#define HPM_NTMR0_BASE (0xF1110000UL) +/* NTMR0 base pointer */ +#define HPM_NTMR0 ((GPTMR_Type *) HPM_NTMR0_BASE) +/* PTMR base address */ +#define HPM_PTMR_BASE (0xF4120000UL) +/* PTMR base pointer */ +#define HPM_PTMR ((GPTMR_Type *) HPM_PTMR_BASE) + +#include "hpm_mbx_regs.h" +/* Address of MBX instances */ +/* MBX0A base address */ +#define HPM_MBX0A_BASE (0xF00A0000UL) +/* MBX0A base pointer */ +#define HPM_MBX0A ((MBX_Type *) HPM_MBX0A_BASE) +/* MBX0B base address */ +#define HPM_MBX0B_BASE (0xF00A4000UL) +/* MBX0B base pointer */ +#define HPM_MBX0B ((MBX_Type *) HPM_MBX0B_BASE) +/* MBX1A base address */ +#define HPM_MBX1A_BASE (0xF00A8000UL) +/* MBX1A base pointer */ +#define HPM_MBX1A ((MBX_Type *) HPM_MBX1A_BASE) +/* MBX1B base address */ +#define HPM_MBX1B_BASE (0xF00AC000UL) +/* MBX1B base pointer */ +#define HPM_MBX1B ((MBX_Type *) HPM_MBX1B_BASE) + +#include "hpm_ewdg_regs.h" +/* Address of EWDG instances */ +/* EWDG0 base address */ +#define HPM_EWDG0_BASE (0xF00B0000UL) +/* EWDG0 base pointer */ +#define HPM_EWDG0 ((EWDG_Type *) HPM_EWDG0_BASE) +/* EWDG1 base address */ +#define HPM_EWDG1_BASE (0xF00B4000UL) +/* EWDG1 base pointer */ +#define HPM_EWDG1 ((EWDG_Type *) HPM_EWDG1_BASE) +/* PEWDG base address */ +#define HPM_PEWDG_BASE (0xF4128000UL) +/* PEWDG base pointer */ +#define HPM_PEWDG ((EWDG_Type *) HPM_PEWDG_BASE) + +#include "hpm_dmamux_regs.h" +/* Address of DMAMUX instances */ +/* DMAMUX base address */ +#define HPM_DMAMUX_BASE (0xF00C4000UL) +/* DMAMUX base pointer */ +#define HPM_DMAMUX ((DMAMUX_Type *) HPM_DMAMUX_BASE) + +#include "hpm_dmav2_regs.h" +/* Address of DMAV2 instances */ +/* HDMA base address */ +#define HPM_HDMA_BASE (0xF00C8000UL) +/* HDMA base pointer */ +#define HPM_HDMA ((DMAV2_Type *) HPM_HDMA_BASE) +/* XDMA base address */ +#define HPM_XDMA_BASE (0xF3008000UL) +/* XDMA base pointer */ +#define HPM_XDMA ((DMAV2_Type *) HPM_XDMA_BASE) + +#include "hpm_gpiom_regs.h" +/* Address of GPIOM instances */ +/* GPIOM base address */ +#define HPM_GPIOM_BASE (0xF00D8000UL) +/* GPIOM base pointer */ +#define HPM_GPIOM ((GPIOM_Type *) HPM_GPIOM_BASE) + +#include "hpm_adc16_regs.h" +/* Address of ADC16 instances */ +/* ADC0 base address */ +#define HPM_ADC0_BASE (0xF00E0000UL) +/* ADC0 base pointer */ +#define HPM_ADC0 ((ADC16_Type *) HPM_ADC0_BASE) + +#include "hpm_i2s_regs.h" +/* Address of I2S instances */ +/* I2S0 base address */ +#define HPM_I2S0_BASE (0xF0200000UL) +/* I2S0 base pointer */ +#define HPM_I2S0 ((I2S_Type *) HPM_I2S0_BASE) +/* I2S1 base address */ +#define HPM_I2S1_BASE (0xF0204000UL) +/* I2S1 base pointer */ +#define HPM_I2S1 ((I2S_Type *) HPM_I2S1_BASE) +/* I2S2 base address */ +#define HPM_I2S2_BASE (0xF0208000UL) +/* I2S2 base pointer */ +#define HPM_I2S2 ((I2S_Type *) HPM_I2S2_BASE) +/* I2S3 base address */ +#define HPM_I2S3_BASE (0xF020C000UL) +/* I2S3 base pointer */ +#define HPM_I2S3 ((I2S_Type *) HPM_I2S3_BASE) + +#include "hpm_dao_regs.h" +/* Address of DAO instances */ +/* DAO base address */ +#define HPM_DAO_BASE (0xF0210000UL) +/* DAO base pointer */ +#define HPM_DAO ((DAO_Type *) HPM_DAO_BASE) + +#include "hpm_pdm_regs.h" +/* Address of PDM instances */ +/* PDM base address */ +#define HPM_PDM_BASE (0xF0214000UL) +/* PDM base pointer */ +#define HPM_PDM ((PDM_Type *) HPM_PDM_BASE) + +#include "hpm_smix_regs.h" +/* Address of SMIX instances */ +/* SMIX base address */ +#define HPM_SMIX_BASE (0xF0218000UL) +/* SMIX base pointer */ +#define HPM_SMIX ((SMIX_Type *) HPM_SMIX_BASE) + +#include "hpm_mcan_regs.h" +/* Address of MCAN instances */ +/* MCAN0 base address */ +#define HPM_MCAN0_BASE (0xF0280000UL) +/* MCAN0 base pointer */ +#define HPM_MCAN0 ((MCAN_Type *) HPM_MCAN0_BASE) +/* MCAN1 base address */ +#define HPM_MCAN1_BASE (0xF0284000UL) +/* MCAN1 base pointer */ +#define HPM_MCAN1 ((MCAN_Type *) HPM_MCAN1_BASE) +/* MCAN2 base address */ +#define HPM_MCAN2_BASE (0xF0288000UL) +/* MCAN2 base pointer */ +#define HPM_MCAN2 ((MCAN_Type *) HPM_MCAN2_BASE) +/* MCAN3 base address */ +#define HPM_MCAN3_BASE (0xF028C000UL) +/* MCAN3 base pointer */ +#define HPM_MCAN3 ((MCAN_Type *) HPM_MCAN3_BASE) +/* MCAN4 base address */ +#define HPM_MCAN4_BASE (0xF0290000UL) +/* MCAN4 base pointer */ +#define HPM_MCAN4 ((MCAN_Type *) HPM_MCAN4_BASE) +/* MCAN5 base address */ +#define HPM_MCAN5_BASE (0xF0294000UL) +/* MCAN5 base pointer */ +#define HPM_MCAN5 ((MCAN_Type *) HPM_MCAN5_BASE) +/* MCAN6 base address */ +#define HPM_MCAN6_BASE (0xF0298000UL) +/* MCAN6 base pointer */ +#define HPM_MCAN6 ((MCAN_Type *) HPM_MCAN6_BASE) +/* MCAN7 base address */ +#define HPM_MCAN7_BASE (0xF029C000UL) +/* MCAN7 base pointer */ +#define HPM_MCAN7 ((MCAN_Type *) HPM_MCAN7_BASE) + +#include "hpm_ptpc_regs.h" +/* Address of PTPC instances */ +/* PTPC base address */ +#define HPM_PTPC_BASE (0xF02FC000UL) +/* PTPC base pointer */ +#define HPM_PTPC ((PTPC_Type *) HPM_PTPC_BASE) + +#include "hpm_lcdc_regs.h" +/* Address of LCDC instances */ +/* LCDC base address */ +#define HPM_LCDC_BASE (0xF1000000UL) +/* LCDC base pointer */ +#define HPM_LCDC ((LCDC_Type *) HPM_LCDC_BASE) +/* LCDC1 base address */ +#define HPM_LCDC1_BASE (0xF1004000UL) +/* LCDC1 base pointer */ +#define HPM_LCDC1 ((LCDC_Type *) HPM_LCDC1_BASE) + +#include "hpm_cam_regs.h" +/* Address of CAM instances */ +/* CAM0 base address */ +#define HPM_CAM0_BASE (0xF1008000UL) +/* CAM0 base pointer */ +#define HPM_CAM0 ((CAM_Type *) HPM_CAM0_BASE) +/* CAM1 base address */ +#define HPM_CAM1_BASE (0xF100C000UL) +/* CAM1 base pointer */ +#define HPM_CAM1 ((CAM_Type *) HPM_CAM1_BASE) + +#include "hpm_pdma_regs.h" +/* Address of PDMA instances */ +/* PDMA base address */ +#define HPM_PDMA_BASE (0xF1010000UL) +/* PDMA base pointer */ +#define HPM_PDMA ((PDMA_Type *) HPM_PDMA_BASE) + +#include "hpm_jpeg_regs.h" +/* Address of JPEG instances */ +/* JPEG base address */ +#define HPM_JPEG_BASE (0xF1014000UL) +/* JPEG base pointer */ +#define HPM_JPEG ((JPEG_Type *) HPM_JPEG_BASE) + +#include "hpm_gwc_regs.h" +/* Address of GWC instances */ +/* GWC0 base address */ +#define HPM_GWC0_BASE (0xF1018000UL) +/* GWC0 base pointer */ +#define HPM_GWC0 ((GWC_Type *) HPM_GWC0_BASE) +/* GWC1 base address */ +#define HPM_GWC1_BASE (0xF101C000UL) +/* GWC1 base pointer */ +#define HPM_GWC1 ((GWC_Type *) HPM_GWC1_BASE) + +#include "hpm_mipi_dsi_regs.h" +/* Address of MIPI_DSI instances */ +/* MIPI_DSI0 base address */ +#define HPM_MIPI_DSI0_BASE (0xF1020000UL) +/* MIPI_DSI0 base pointer */ +#define HPM_MIPI_DSI0 ((MIPI_DSI_Type *) HPM_MIPI_DSI0_BASE) +/* MIPI_DSI1 base address */ +#define HPM_MIPI_DSI1_BASE (0xF1024000UL) +/* MIPI_DSI1 base pointer */ +#define HPM_MIPI_DSI1 ((MIPI_DSI_Type *) HPM_MIPI_DSI1_BASE) + +#include "hpm_mipi_csi_regs.h" +/* Address of MIPI_CSI instances */ +/* MIPI_CSI0 base address */ +#define HPM_MIPI_CSI0_BASE (0xF1028000UL) +/* MIPI_CSI0 base pointer */ +#define HPM_MIPI_CSI0 ((MIPI_CSI_Type *) HPM_MIPI_CSI0_BASE) +/* MIPI_CSI1 base address */ +#define HPM_MIPI_CSI1_BASE (0xF102C000UL) +/* MIPI_CSI1 base pointer */ +#define HPM_MIPI_CSI1 ((MIPI_CSI_Type *) HPM_MIPI_CSI1_BASE) + +#include "hpm_lvb_regs.h" +/* Address of LVB instances */ +/* LVB base address */ +#define HPM_LVB_BASE (0xF1030000UL) +/* LVB base pointer */ +#define HPM_LVB ((LVB_Type *) HPM_LVB_BASE) + +#include "hpm_pixelmux_regs.h" +/* Address of PIXELMUX instances */ +/* PIXEL_MUX base address */ +#define HPM_PIXEL_MUX_BASE (0xF1034000UL) +/* PIXEL_MUX base pointer */ +#define HPM_PIXEL_MUX ((PIXELMUX_Type *) HPM_PIXEL_MUX_BASE) + +#include "hpm_lcb_regs.h" +/* Address of LCB instances */ +/* LCB base address */ +#define HPM_LCB_BASE (0xF1038000UL) +/* LCB base pointer */ +#define HPM_LCB ((LCB_Type *) HPM_LCB_BASE) + +#include "hpm_gpu_regs.h" +/* Address of GPU instances */ +/* GPU base address */ +#define HPM_GPU_BASE (0xF1080000UL) +/* GPU base pointer */ +#define HPM_GPU ((GPU_Type *) HPM_GPU_BASE) + +#include "hpm_enet_regs.h" +/* Address of ENET instances */ +/* ENET0 base address */ +#define HPM_ENET0_BASE (0xF1100000UL) +/* ENET0 base pointer */ +#define HPM_ENET0 ((ENET_Type *) HPM_ENET0_BASE) + +#include "hpm_usb_regs.h" +/* Address of USB instances */ +/* USB0 base address */ +#define HPM_USB0_BASE (0xF1120000UL) +/* USB0 base pointer */ +#define HPM_USB0 ((USB_Type *) HPM_USB0_BASE) + +#include "hpm_sdxc_regs.h" +/* Address of SDXC instances */ +/* SDXC0 base address */ +#define HPM_SDXC0_BASE (0xF1130000UL) +/* SDXC0 base pointer */ +#define HPM_SDXC0 ((SDXC_Type *) HPM_SDXC0_BASE) +/* SDXC1 base address */ +#define HPM_SDXC1_BASE (0xF1134000UL) +/* SDXC1 base pointer */ +#define HPM_SDXC1 ((SDXC_Type *) HPM_SDXC1_BASE) + +#include "hpm_ddrctl_regs.h" +/* Address of DDRCTL instances */ +/* DDRCTL base address */ +#define HPM_DDRCTL_BASE (0xF3010000UL) +/* DDRCTL base pointer */ +#define HPM_DDRCTL ((DDRCTL_Type *) HPM_DDRCTL_BASE) + +/* Address of ROMC instances */ +/* ROMC base address */ +#define HPM_ROMC_BASE (0xF3014000UL) + +#include "hpm_ffa_regs.h" +/* Address of FFA instances */ +/* FFA base address */ +#define HPM_FFA_BASE (0xF3018000UL) +/* FFA base pointer */ +#define HPM_FFA ((FFA_Type *) HPM_FFA_BASE) + +#include "hpm_sdp_regs.h" +/* Address of SDP instances */ +/* SDP base address */ +#define HPM_SDP_BASE (0xF3040000UL) +/* SDP base pointer */ +#define HPM_SDP ((SDP_Type *) HPM_SDP_BASE) + +#include "hpm_sec_regs.h" +/* Address of SEC instances */ +/* SEC base address */ +#define HPM_SEC_BASE (0xF3044000UL) +/* SEC base pointer */ +#define HPM_SEC ((SEC_Type *) HPM_SEC_BASE) + +#include "hpm_mon_regs.h" +/* Address of MON instances */ +/* MON base address */ +#define HPM_MON_BASE (0xF3048000UL) +/* MON base pointer */ +#define HPM_MON ((MON_Type *) HPM_MON_BASE) + +#include "hpm_rng_regs.h" +/* Address of RNG instances */ +/* RNG base address */ +#define HPM_RNG_BASE (0xF304C000UL) +/* RNG base pointer */ +#define HPM_RNG ((RNG_Type *) HPM_RNG_BASE) + +#include "hpm_otp_regs.h" +/* Address of OTP instances */ +/* OTP base address */ +#define HPM_OTP_BASE (0xF3050000UL) +/* OTP base pointer */ +#define HPM_OTP ((OTP_Type *) HPM_OTP_BASE) + +#include "hpm_keym_regs.h" +/* Address of KEYM instances */ +/* KEYM base address */ +#define HPM_KEYM_BASE (0xF3054000UL) +/* KEYM base pointer */ +#define HPM_KEYM ((KEYM_Type *) HPM_KEYM_BASE) + +#include "hpm_sysctl_regs.h" +/* Address of SYSCTL instances */ +/* SYSCTL base address */ +#define HPM_SYSCTL_BASE (0xF4000000UL) +/* SYSCTL base pointer */ +#define HPM_SYSCTL ((SYSCTL_Type *) HPM_SYSCTL_BASE) + +#include "hpm_ioc_regs.h" +/* Address of IOC instances */ +/* IOC base address */ +#define HPM_IOC_BASE (0xF4040000UL) +/* IOC base pointer */ +#define HPM_IOC ((IOC_Type *) HPM_IOC_BASE) +/* PIOC base address */ +#define HPM_PIOC_BASE (0xF4118000UL) +/* PIOC base pointer */ +#define HPM_PIOC ((IOC_Type *) HPM_PIOC_BASE) +/* BIOC base address */ +#define HPM_BIOC_BASE (0xF4210000UL) +/* BIOC base pointer */ +#define HPM_BIOC ((IOC_Type *) HPM_BIOC_BASE) + +#include "hpm_pllctlv2_regs.h" +/* Address of PLLCTLV2 instances */ +/* PLLCTLV2 base address */ +#define HPM_PLLCTLV2_BASE (0xF40C0000UL) +/* PLLCTLV2 base pointer */ +#define HPM_PLLCTLV2 ((PLLCTLV2_Type *) HPM_PLLCTLV2_BASE) + +#include "hpm_ppor_regs.h" +/* Address of PPOR instances */ +/* PPOR base address */ +#define HPM_PPOR_BASE (0xF4100000UL) +/* PPOR base pointer */ +#define HPM_PPOR ((PPOR_Type *) HPM_PPOR_BASE) + +#include "hpm_pcfg_regs.h" +/* Address of PCFG instances */ +/* PCFG base address */ +#define HPM_PCFG_BASE (0xF4104000UL) +/* PCFG base pointer */ +#define HPM_PCFG ((PCFG_Type *) HPM_PCFG_BASE) + +#include "hpm_pgpr_regs.h" +/* Address of PGPR instances */ +/* PGPR0 base address */ +#define HPM_PGPR0_BASE (0xF4110000UL) +/* PGPR0 base pointer */ +#define HPM_PGPR0 ((PGPR_Type *) HPM_PGPR0_BASE) +/* PGPR1 base address */ +#define HPM_PGPR1_BASE (0xF4114000UL) +/* PGPR1 base pointer */ +#define HPM_PGPR1 ((PGPR_Type *) HPM_PGPR1_BASE) + +#include "hpm_vad_regs.h" +/* Address of VAD instances */ +/* VAD base address */ +#define HPM_VAD_BASE (0xF412C000UL) +/* VAD base pointer */ +#define HPM_VAD ((VAD_Type *) HPM_VAD_BASE) + +#include "hpm_mipi_dsi_phy_regs.h" +/* Address of MIPI_DSI_PHY instances */ +/* MIPI_DSI_PHY0 base address */ +#define HPM_MIPI_DSI_PHY0_BASE (0xF4140000UL) +/* MIPI_DSI_PHY0 base pointer */ +#define HPM_MIPI_DSI_PHY0 ((MIPI_DSI_PHY_Type *) HPM_MIPI_DSI_PHY0_BASE) +/* MIPI_DSI_PHY1 base address */ +#define HPM_MIPI_DSI_PHY1_BASE (0xF4144000UL) +/* MIPI_DSI_PHY1 base pointer */ +#define HPM_MIPI_DSI_PHY1 ((MIPI_DSI_PHY_Type *) HPM_MIPI_DSI_PHY1_BASE) + +#include "hpm_mipi_csi_phy_regs.h" +/* Address of MIPI_CSI_PHY instances */ +/* MIPI_CSI_PHY0 base address */ +#define HPM_MIPI_CSI_PHY0_BASE (0xF4148000UL) +/* MIPI_CSI_PHY0 base pointer */ +#define HPM_MIPI_CSI_PHY0 ((MIPI_CSI_PHY_Type *) HPM_MIPI_CSI_PHY0_BASE) +/* MIPI_CSI_PHY1 base address */ +#define HPM_MIPI_CSI_PHY1_BASE (0xF414C000UL) +/* MIPI_CSI_PHY1 base pointer */ +#define HPM_MIPI_CSI_PHY1 ((MIPI_CSI_PHY_Type *) HPM_MIPI_CSI_PHY1_BASE) + +#include "hpm_ddrphy_regs.h" +/* Address of DDRPHY instances */ +/* DDRPHY base address */ +#define HPM_DDRPHY_BASE (0xF4150000UL) +/* DDRPHY base pointer */ +#define HPM_DDRPHY ((DDRPHY_Type *) HPM_DDRPHY_BASE) + +#include "hpm_tsns_regs.h" +/* Address of TSNS instances */ +/* TSNS base address */ +#define HPM_TSNS_BASE (0xF4154000UL) +/* TSNS base pointer */ +#define HPM_TSNS ((TSNS_Type *) HPM_TSNS_BASE) + +#include "hpm_bacc_regs.h" +/* Address of BACC instances */ +/* BACC base address */ +#define HPM_BACC_BASE (0xF4200000UL) +/* BACC base pointer */ +#define HPM_BACC ((BACC_Type *) HPM_BACC_BASE) + +#include "hpm_bpor_regs.h" +/* Address of BPOR instances */ +/* BPOR base address */ +#define HPM_BPOR_BASE (0xF4204000UL) +/* BPOR base pointer */ +#define HPM_BPOR ((BPOR_Type *) HPM_BPOR_BASE) + +#include "hpm_bcfg_regs.h" +/* Address of BCFG instances */ +/* BCFG base address */ +#define HPM_BCFG_BASE (0xF4208000UL) +/* BCFG base pointer */ +#define HPM_BCFG ((BCFG_Type *) HPM_BCFG_BASE) + +#include "hpm_butn_regs.h" +/* Address of BUTN instances */ +/* BUTN base address */ +#define HPM_BUTN_BASE (0xF420C000UL) +/* BUTN base pointer */ +#define HPM_BUTN ((BUTN_Type *) HPM_BUTN_BASE) + +#include "hpm_bgpr_regs.h" +/* Address of BGPR instances */ +/* BGPR base address */ +#define HPM_BGPR_BASE (0xF4218000UL) +/* BGPR base pointer */ +#define HPM_BGPR ((BGPR_Type *) HPM_BGPR_BASE) + +#include "hpm_rtc_regs.h" +/* Address of RTC instances */ +/* RTCSHW base address */ +#define HPM_RTCSHW_BASE (0xF421C000UL) +/* RTCSHW base pointer */ +#define HPM_RTCSHW ((RTC_Type *) HPM_RTCSHW_BASE) +/* RTC base address */ +#define HPM_RTC_BASE (0xF4244000UL) +/* RTC base pointer */ +#define HPM_RTC ((RTC_Type *) HPM_RTC_BASE) + +#include "hpm_bsec_regs.h" +/* Address of BSEC instances */ +/* BSEC base address */ +#define HPM_BSEC_BASE (0xF4240000UL) +/* BSEC base pointer */ +#define HPM_BSEC ((BSEC_Type *) HPM_BSEC_BASE) + +#include "hpm_bkey_regs.h" +/* Address of BKEY instances */ +/* BKEY base address */ +#define HPM_BKEY_BASE (0xF4248000UL) +/* BKEY base pointer */ +#define HPM_BKEY ((BKEY_Type *) HPM_BKEY_BASE) + +#include "hpm_bmon_regs.h" +/* Address of BMON instances */ +/* BMON base address */ +#define HPM_BMON_BASE (0xF424C000UL) +/* BMON base pointer */ +#define HPM_BMON ((BMON_Type *) HPM_BMON_BASE) + +#include "hpm_tamp_regs.h" +/* Address of TAMP instances */ +/* TAMP base address */ +#define HPM_TAMP_BASE (0xF4250000UL) +/* TAMP base pointer */ +#define HPM_TAMP ((TAMP_Type *) HPM_TAMP_BASE) + +#include "hpm_mono_regs.h" +/* Address of MONO instances */ +/* MONO base address */ +#define HPM_MONO_BASE (0xF4254000UL) +/* MONO base pointer */ +#define HPM_MONO ((MONO_Type *) HPM_MONO_BASE) + + +#include "riscv/riscv_core.h" +#include "hpm_csr_regs.h" +#include "hpm_interrupt.h" +#include "hpm_misc.h" +#include "hpm_dmamux_src.h" +#include "hpm_iomux.h" +#include "hpm_pmic_iomux.h" +#include "hpm_batt_iomux.h" +#endif /* HPM_SOC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_soc_feature.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_soc_feature.h new file mode 100644 index 00000000000..b5d1d0c81e0 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_soc_feature.h @@ -0,0 +1,221 @@ +/* + * Copyright (c) 2023-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_SOC_FEATURE_H +#define HPM_SOC_FEATURE_H + +#include "hpm_soc.h" +#include "hpm_soc_ip_feature.h" + +/* + * I2C Section + */ +#define I2C_SOC_FIFO_SIZE (4U) +#define I2C_SOC_TRANSFER_COUNT_MAX (4096U) + +/* + * PMIC Section + */ +#define PCFG_SOC_LDO1P1_MIN_VOLTAGE_IN_MV (700U) +#define PCFG_SOC_LDO1P1_MAX_VOLTAGE_IN_MV (1320U) +#define PCFG_SOC_LDO2P5_MIN_VOLTAGE_IN_MV (2125) +#define PCFG_SOC_LDO2P5_MAX_VOLTAGE_IN_MV (2900U) +#define PCFG_SOC_DCDC_MIN_VOLTAGE_IN_MV (600U) +#define PCFG_SOC_DCDC_MAX_VOLTAGE_IN_MV (1375U) + +/* + * I2S Section + */ +#define I2S_SOC_MAX_CHANNEL_NUM (16U) +#define I2S_SOC_MAX_TX_CHANNEL_NUM (8U) +#define I2S_SOC_MAX_TX_FIFO_DEPTH (8U) +#define PDM_I2S HPM_I2S0 +#define DAO_I2S HPM_I2S1 +#define PDM_SOC_SAMPLE_RATE_IN_HZ (16000U) +#define VAD_SOC_SAMPLE_RATE_IN_HZ (16000U) +#define DAO_SOC_SAMPLE_RATE_IN_HZ (48000U) +#define DAO_SOC_PDM_SAMPLE_RATE_RATIO (3U) +#define DAO_SOC_VAD_SAMPLE_RATE_RATIO (3U) +#define DAO_SOC_SUPPORT_DATA_FORMAT_CONFIG (1U) + +/* + * PLLCTL Section + */ +#define PLLCTL_SOC_PLL_MAX_COUNT (5U) +/* PLL reference clock in hz */ +#define PLLCTL_SOC_PLL_REFCLK_FREQ (24U * 1000000UL) +/* only PLL1 and PLL2 have DIV0, DIV1 */ +#define PLLCTL_SOC_PLL_HAS_DIV0(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0) +#define PLLCTL_SOC_PLL_HAS_DIV1(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0) + + +/* + * PWM Section + */ +#define PWM_SOC_PWM_MAX_COUNT (8U) +#define PWM_SOC_CMP_MAX_COUNT (24U) +#define PWM_SOC_OUTPUT_TO_PWM_MAX_COUNT (8U) +#define PWM_SOC_OUTPUT_MAX_COUNT (24U) + +/* + * DMA Section + */ +#define DMA_SOC_TRANSFER_WIDTH_MAX(x) (((x) == HPM_XDMA) ? DMA_TRANSFER_WIDTH_DOUBLE_WORD : DMA_TRANSFER_WIDTH_WORD) +#define DMA_SOC_TRANSFER_PER_BURST_MAX(x) (((x) == HPM_XDMA) ? DMA_NUM_TRANSFER_PER_BURST_1024T : DMA_NUM_TRANSFER_PER_BURST_128T) +#define DMA_SOC_CHANNEL_NUM (32U) +#define DMA_SOC_MAX_COUNT (2U) +#define DMA_SOC_CHN_TO_DMAMUX_CHN(x, n) (((x) == HPM_XDMA) ? (DMAMUX_MUXCFG_XDMA_MUX0 + n) : (DMAMUX_MUXCFG_HDMA_MUX0 + n)) +#define DMA_SOC_HAS_IDLE_FLAG (1U) + +/* + * PDMA Section + */ +#define PDMA_SOC_PS_MAX_COUNT (2U) +#define PDMA_SOC_SUPPORT_BS16 (0U) + +/* + * LCDC Section + */ +#define LCDC_SOC_MAX_LAYER_COUNT (8U) +#define LCDC_SOC_MAX_CSC_LAYER_COUNT (2U) +#define LCDC_SOC_LAYER_SUPPORTS_CSC(x) ((x) < 2) +#define LCDC_SOC_LAYER_SUPPORTS_YUV(x) ((x) < 2) + +/* + * USB Section + */ +#define USB_SOC_MAX_COUNT (1U) + +#define USB_SOC_DCD_QTD_NEXT_INVALID (1U) +#define USB_SOC_DCD_QHD_BUFFER_COUNT (5U) +#define USB_SOC_DCD_MAX_ENDPOINT_COUNT (16U) +#ifndef USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT +#define USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT (8U) +#endif +#define USB_SOC_DCD_MAX_QTD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U * USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT) +#define USB_SOS_DCD_MAX_QHD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U) +#define USB_SOC_DCD_DATA_RAM_ADDRESS_ALIGNMENT (2048U) + +#define USB_SOC_HCD_FRAMELIST_MAX_ELEMENTS (1024U) + +/* + * ENET Section + */ +#define ENET_SOC_RGMII_EN (1U) +#define ENET_SOC_DESC_ADDR_ALIGNMENT (32U) +#define ENET_SOC_BUFF_ADDR_ALIGNMENT (4U) +#define ENET_SOC_ADDR_MAX_COUNT (5U) +#define ENET_SOC_ALT_EHD_DES_MIN_LEN (4U) +#define ENET_SOC_ALT_EHD_DES_MAX_LEN (8U) +#define ENET_SOC_ALT_EHD_DES_LEN (8U) +#define ENET_SOC_PPS_MAX_COUNT (4L) +#define ENET_SOC_PPS1_EN (0U) + +/* + * ADC Section + */ +#define ADC_SOC_SEQ_MAX_LEN (16U) +#define ADC_SOC_SEQ_HCFG_EN (1U) +#define ADC_SOC_MAX_TRIG_CH_LEN (4U) +#define ADC_SOC_MAX_TRIG_CH_NUM (11U) +#define ADC_SOC_DMA_ADDR_ALIGNMENT (4U) +#define ADC_SOC_CONFIG_INTEN_CHAN_BIT_SIZE (8U) +#define ADC_SOC_PREEMPT_ENABLE_CTRL_SUPPORT (1U) +#define ADC_SOC_SEQ_MAX_DMA_BUFF_LEN_IN_4BYTES (16777216U) +#define ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES (48U) +#define ADC_SOC_NO_HW_TRIG_SRC (1U) + +#define ADC16_SOC_PARAMS_LEN (34U) +#define ADC16_SOC_MAX_CH_NUM (15U) +#define ADC16_SOC_TEMP_CH_EN (0U) +#define ADC16_SOC_MAX_SAMPLE_VALUE (65535U) +#define ADC16_SOC_MAX_CONV_CLK_NUM (21U) + +/* + * SYSCTL Section + */ +#define SYSCTL_SOC_CPU_GPR_COUNT (14U) +#define SYSCTL_SOC_MONITOR_SLICE_COUNT (4U) + +/* + * PTPC Section + */ +#define PTPC_SOC_TIMER_MAX_COUNT (2U) + +/* + * SDP Section + */ +#define SDP_REGISTER_DESCRIPTOR_COUNT (1U) +#define SDP_HAS_SM3_SUPPORT (1U) +#define SDP_HAS_SM4_SUPPORT (1U) + +/* + * SOC Privilege mdoe + */ +#define SOC_HAS_S_MODE (1U) + +/* + * DAC Section + */ +#define DAC_SOC_BUFF_ALIGNED_SIZE (32U) +#define DAC_SOC_MAX_DATA (4095U) +#define DAC_SOC_MAX_BUFF_COUNT (65536U) +#define DAC_SOC_MAX_OUTPUT_FREQ (1000000UL) + + +/* + * SDXC Section + */ +#define SDXC_SOC_HAS_MISC_CTRL0 (1) +#define SDXC_SOC_HAS_MISC_CTRL1 (1) +#define SDXC_SOC_MAX_COUNT (2) + +/* + * UART Section + */ +#define UART_SOC_FIFO_SIZE (16U) + +/* + * SPI Section + */ +#define SPI_SOC_TRANSFER_COUNT_MAX (0xFFFFFFFFU) +#define SPI_SOC_FIFO_DEPTH (4U) + +/* + * EWDG Section + */ +#define EWDG_SOC_CLK_DIV_VAL_MAX (5U) +#define EWDG_SOC_OVERTIME_REG_WIDTH (16U) +#define EWDG_SOC_SUPPORT_TIMEOUT_INTERRUPT (0U) + + +/* + * MCAN Section + */ +#define MCAN_SOC_MSG_BUF_IN_IP (0U) +#define MCAN_SOC_MSG_BUF_IN_AHB_RAM (1U) +#define MCAN_SOC_MAX_COUNT (8U) +#define CAN_SOC_MAX_COUNT MCAN_SOC_MAX_COUNT + +/* + * OTP Section + */ +#define OTP_SOC_MAC0_IDX (65U) +#define OTP_SOC_MAC0_LEN (6U) /* in bytes */ + +#define OTP_SOC_UUID_IDX (88U) +#define OTP_SOC_UUID_LEN (16U) /* in bytes */ + +/** + * PWM Section + * + */ +#define PWM_SOC_HRPWM_SUPPORT (0U) +#define PWM_SOC_SHADOW_TRIG_SUPPORT (0U) +#define PWM_SOC_TIMER_RESET_SUPPORT (0U) + +#endif /* HPM_SOC_FEATURE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_soc_ip_feature.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_soc_ip_feature.h new file mode 100644 index 00000000000..8b860720e22 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_soc_ip_feature.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_SOC_IP_FEATURE_H +#define HPM_SOC_IP_FEATURE_H + +/* UART related feature */ +#define HPM_IP_FEATURE_UART_RX_IDLE_DETECT 1 +#define HPM_IP_FEATURE_UART_FCRR 1 +#define HPM_IP_FEATURE_UART_RX_EN 1 + +/* I2C related feature */ +#define HPM_IP_FEATURE_I2C_SUPPORT_RESET 1 + +/* SPI related feature */ +#define HPM_IP_FEATURE_SPI_NEW_TRANS_COUNT 1 +#define HPM_IP_FEATURE_SPI_CS_SELECT 1 +#define HPM_IP_FEATURE_SPI_SUPPORT_DIRECTIO 1 + +/* DAO related feature */ +#define HPM_IP_FEATURE_DAO_DATA_FORMAT_CONFIG 1 + +#endif /* HPM_SOC_IP_FEATURE_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_sysctl_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_sysctl_drv.c new file mode 100644 index 00000000000..fed8e823434 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_sysctl_drv.c @@ -0,0 +1,244 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_sysctl_drv.h" +#include "hpm_soc_feature.h" + +#define SYSCTL_RESOURCE_GROUP0 0 + +#define SYSCTL_CPU_RELEASE_KEY(cpu) (0xC0BEF1A9UL | ((cpu & 1) << 24)) + +hpm_stat_t sysctl_get_cpu0_gpr(SYSCTL_Type *ptr, uint32_t *data, uint32_t size) +{ + uint32_t i; + for (i = 0; i < size; i++) { + *(data + i) = ptr->CPU[0].GPR[i]; + } + return status_success; +} + +hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data) +{ + uint8_t i, size = ARRAY_SIZE(ptr->CPU[0].GPR); + if ((data == NULL) || !count || start > size || count > size || + (start + count) > size) { + return status_invalid_argument; + } + for (i = 0; i < count; i++) { + *(data + i) = ptr->CPU[0].GPR[start + i]; + } + return status_success; +} + +hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock) +{ + uint8_t i, size = ARRAY_SIZE(ptr->CPU[0].GPR); + uint32_t gpr_mask; + if ((data == NULL) || !count || start > size || count > size || + (start + count) > size) { + return status_invalid_argument; + } + for (i = 0; i < count; i++) { + ptr->CPU[0].GPR[start + i] = *(data + i); + } + if (lock) { + gpr_mask = ((1 << count) - 1) << start; + sysctl_cpu0_lock_gpr_with_mask(ptr, gpr_mask); + } + return status_success; +} + +void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config) +{ + (void) ptr; + config->mode = monitor_work_mode_record; + config->accuracy = monitor_accuracy_1khz; + config->reference = monitor_reference_24mhz; + config->divide_by = 1; + config->high_limit = 0; + config->low_limit = 0; + config->start_measure = true; + config->enable_output = false; + config->target = monitor_target_clk_top_cpu0; +} + +void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config_t *config) +{ + ptr->MONITOR[monitor_index].CONTROL &= ~(SYSCTL_MONITOR_CONTROL_START_MASK | SYSCTL_MONITOR_CONTROL_OUTEN_MASK); + + if (config->mode == monitor_work_mode_compare) { + ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(config->high_limit); + ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(config->low_limit); + } + + ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL & + ~(SYSCTL_MONITOR_CONTROL_DIV_MASK | SYSCTL_MONITOR_CONTROL_MODE_MASK | SYSCTL_MONITOR_CONTROL_ACCURACY_MASK | + SYSCTL_MONITOR_CONTROL_REFERENCE_MASK | SYSCTL_MONITOR_CONTROL_SELECTION_MASK)) | + (SYSCTL_MONITOR_CONTROL_DIV_SET(config->divide_by - 1) | SYSCTL_MONITOR_CONTROL_MODE_SET(config->mode) | + SYSCTL_MONITOR_CONTROL_ACCURACY_SET(config->accuracy) | + SYSCTL_MONITOR_CONTROL_REFERENCE_SET(config->reference) | + SYSCTL_MONITOR_CONTROL_START_SET(config->start_measure) | + SYSCTL_MONITOR_CONTROL_OUTEN_SET(config->enable_output) | + SYSCTL_MONITOR_CONTROL_SELECTION_SET(config->target)); +} + +uint32_t +sysctl_monitor_measure_frequency(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_target_t target, bool enable_output) +{ + uint32_t frequency = 0; + monitor_config_t monitor = { 0 }; + sysctl_monitor_get_default_config(ptr, &monitor); + monitor.target = target; + monitor.enable_output = enable_output; + sysctl_monitor_init(ptr, monitor_index, &monitor); + if (monitor_index < SYSCTL_SOC_MONITOR_SLICE_COUNT) { + frequency = sysctl_monitor_get_current_result(ptr, monitor_index); + } + return frequency; +} + +hpm_stat_t sysctl_set_cpu0_entry(SYSCTL_Type *ptr, uint32_t entry) +{ + ptr->CPU[0].GPR[0] = entry; + ptr->CPU[0].GPR[1] = SYSCTL_CPU_RELEASE_KEY(0); + return status_success; +} + +hpm_stat_t sysctl_set_cpu0_lp_mode(SYSCTL_Type *ptr, cpu_lp_mode_t mode) +{ + ptr->CPU[0].LP = (ptr->CPU[0].LP & ~(SYSCTL_CPU_LP_MODE_MASK)) | (mode); + return status_success; +} + +hpm_stat_t +sysctl_enable_group_resource(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t resource, bool enable) +{ + uint32_t index, offset; + if (resource < sysctl_resource_linkable_start) { + return status_invalid_argument; + } + + index = (resource - sysctl_resource_linkable_start) / 32; + offset = (resource - sysctl_resource_linkable_start) % 32; + switch (group) { + case SYSCTL_RESOURCE_GROUP0: + ptr->GROUP0[index].VALUE = (ptr->GROUP0[index].VALUE & ~(1UL << offset)) | (enable ? (1UL << offset) : 0); + if (enable) { + while (sysctl_resource_target_is_busy(ptr, resource)) { + ; + } + } + break; + default: + return status_invalid_argument; + } + + return status_success; +} + +bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, + uint8_t group, + sysctl_resource_t resource) +{ + uint32_t index, offset; + bool enable; + + index = (resource - sysctl_resource_linkable_start) / 32; + offset = (resource - sysctl_resource_linkable_start) % 32; + switch (group) { + case SYSCTL_RESOURCE_GROUP0: + enable = ((ptr->GROUP0[index].VALUE & (1UL << offset)) != 0) ? true : false; + break; + default: + enable = false; + break; + } + + return enable; +} + +uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index) +{ + uint32_t value; + switch (group) { + case SYSCTL_RESOURCE_GROUP0: + value = ptr->GROUP0[index].VALUE; + break; + default: + value = 0; + break; + } + return value; +} + +hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) +{ + return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, true); +} + +hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) +{ + return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, false); +} + +hpm_stat_t sysctl_update_divider(SYSCTL_Type *ptr, clock_node_t node, uint32_t divide_by) +{ + if (node >= clock_node_adc_start) { + return status_invalid_argument; + } + + ptr->CLOCK[node] = (ptr->CLOCK[node] & ~(SYSCTL_CLOCK_DIV_MASK)) | SYSCTL_CLOCK_DIV_SET(divide_by - 1); + while (sysctl_clock_target_is_busy(ptr, node)) { + } + return status_success; +} + +hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node, clock_source_t source, uint32_t divide_by) +{ + if (node >= clock_node_adc_start) { + return status_invalid_argument; + } + + if (source >= clock_source_general_source_end) { + return status_invalid_argument; + } + ptr->CLOCK[node] = (ptr->CLOCK[node] & ~(SYSCTL_CLOCK_MUX_MASK | SYSCTL_CLOCK_DIV_MASK)) | + (SYSCTL_CLOCK_MUX_SET(source) | SYSCTL_CLOCK_DIV_SET(divide_by - 1)); + while (sysctl_clock_target_is_busy(ptr, node)) { + } + return status_success; +} + +hpm_stat_t sysctl_set_adc_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_adc_t source) +{ + if (source >= clock_source_adc_clk_end) { + return status_invalid_argument; + } + uint32_t adc_index = (uint32_t)(node - clock_node_adc_start); + if (adc_index >= ARRAY_SIZE(ptr->ADCCLK)) { + return status_invalid_argument; + } + + ptr->ADCCLK[adc_index] = (ptr->ADCCLK[adc_index] & ~SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(source); + + return status_success; +} + +hpm_stat_t sysctl_set_i2s_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_i2s_t source) +{ + if (source >= clock_source_i2s_clk_end) { + return status_invalid_argument; + } + uint32_t i2s_index = (uint32_t)(node - clock_node_i2s_start); + if (i2s_index >= ARRAY_SIZE(ptr->I2SCLK)) { + return status_invalid_argument; + } + + ptr->I2SCLK[i2s_index] = (ptr->I2SCLK[i2s_index] & ~SYSCTL_I2SCLK_MUX_MASK) | SYSCTL_I2SCLK_MUX_SET(source); + + return status_success; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_sysctl_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_sysctl_drv.h new file mode 100644 index 00000000000..1aff71cb26b --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_sysctl_drv.h @@ -0,0 +1,1220 @@ +/** + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_SYSCTL_DRV_H +#define HPM_SYSCTL_DRV_H + +#include "hpm_common.h" +#include "hpm_sysctl_regs.h" + +/** + * + * @brief SYSCTL driver APIs + * @defgroup sysctl_interface SYSCTL driver APIs + * @ingroup io_interfaces + * @{ + */ + +/** + * @brief Retention domains + */ +typedef enum { + sysctl_retention_domain_sys = 0, + sysctl_retention_domain_cpu0 = 2, + sysctl_retention_domain_con = 4, + sysctl_retention_domain_vis = 5, + sysctl_retention_domain_gpu = 7, + sysctl_retention_domain_xtal24m = 9, + sysctl_retention_domain_pll0 = 10, + sysctl_retention_domain_pll1 = 11, + sysctl_retention_domain_pll2 = 12, + sysctl_retention_domain_pll3 = 13, + sysctl_retention_domain_pll4 = 14, +} sysctl_retention_domain_t; + +/** + * @brief Clock presets + */ +typedef enum { + sysctl_preset_0 = 1 << 0, + sysctl_preset_1 = 1 << 1, + sysctl_preset_2 = 1 << 2, + sysctl_preset_3 = 1 << 3, +} sysctl_preset_t; + +/** + * @brief Reset domains + */ +typedef enum { + sysctl_reset_domain_soc = 0, + sysctl_reset_domain_con, + sysctl_reset_domain_vis, + sysctl_reset_domain_cpu0, + sysctl_reset_domain_gpu +} sysctl_reset_domain_t; + +/** + * @brief Resource + */ +typedef enum { + sysctl_resource_cpu0 = SYSCTL_RESOURCE_CPU0, + sysctl_resource_cpx0 = SYSCTL_RESOURCE_CPX0, + sysctl_resource_pow_cpu0 = SYSCTL_RESOURCE_POW_CPU0, + sysctl_resource_rst_soc = SYSCTL_RESOURCE_RST_SOC, + sysctl_resource_rst_cpu0 = SYSCTL_RESOURCE_RST_CPU0, + sysctl_resource_xtal = SYSCTL_RESOURCE_CLK_SRC_XTAL, + sysctl_resource_pll0 = SYSCTL_RESOURCE_CLK_SRC_PLL0, + sysctl_resource_clk0_pll0 = SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL0, + sysctl_resource_pll1 = SYSCTL_RESOURCE_CLK_SRC_PLL1, + sysctl_resource_clk0_pll1 = SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL1, + sysctl_resource_clk1_pll1 = SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL1, + sysctl_resource_pll2 = SYSCTL_RESOURCE_CLK_SRC_PLL2, + sysctl_resource_clk0_pll2 = SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL2, + sysctl_resource_clk1_pll2 = SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL2, + sysctl_resource_pll3 = SYSCTL_RESOURCE_CLK_SRC_PLL3, + sysctl_resource_clk0_pll3 = SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL3, + sysctl_resource_pll4 = SYSCTL_RESOURCE_CLK_SRC_PLL4, + sysctl_resource_clk0_pll4 = SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL4, + sysctl_resource_pll0_ref = SYSCTL_RESOURCE_CLK_SRC_PLL0_REF, + sysctl_resource_pll1_ref = SYSCTL_RESOURCE_CLK_SRC_PLL1_REF, + sysctl_resource_pll2_ref = SYSCTL_RESOURCE_CLK_SRC_PLL2_REF, + sysctl_resource_pll3_ref = SYSCTL_RESOURCE_CLK_SRC_PLL3_REF, + sysctl_resource_pll4_ref = SYSCTL_RESOURCE_CLK_SRC_PLL4_REF, + + sysctl_resource_clk_top_cpu0 = SYSCTL_RESOURCE_CLK_TOP_CPU0, + sysctl_resource_clk_top_mchtmr0 = SYSCTL_RESOURCE_CLK_TOP_MCT0, + sysctl_resource_clk_top_gpu0 = SYSCTL_RESOURCE_CLK_TOP_GPU0, + sysctl_resource_clk_top_axif = SYSCTL_RESOURCE_CLK_TOP_AXIF, + sysctl_resource_clk_top_axis = SYSCTL_RESOURCE_CLK_TOP_AXIS, + sysctl_resource_clk_top_axic = SYSCTL_RESOURCE_CLK_TOP_AXIC, + sysctl_resource_clk_top_axiv = SYSCTL_RESOURCE_CLK_TOP_AXIV, + sysctl_resource_clk_top_axid = SYSCTL_RESOURCE_CLK_TOP_AXID, + sysctl_resource_clk_top_can0 = SYSCTL_RESOURCE_CLK_TOP_CAN0, + sysctl_resource_clk_top_can1 = SYSCTL_RESOURCE_CLK_TOP_CAN1, + sysctl_resource_clk_top_can2 = SYSCTL_RESOURCE_CLK_TOP_CAN2, + sysctl_resource_clk_top_can3 = SYSCTL_RESOURCE_CLK_TOP_CAN3, + sysctl_resource_clk_top_can4 = SYSCTL_RESOURCE_CLK_TOP_CAN4, + sysctl_resource_clk_top_can5 = SYSCTL_RESOURCE_CLK_TOP_CAN5, + sysctl_resource_clk_top_can6 = SYSCTL_RESOURCE_CLK_TOP_CAN6, + sysctl_resource_clk_top_can7 = SYSCTL_RESOURCE_CLK_TOP_CAN7, + sysctl_resource_clk_top_lin0 = SYSCTL_RESOURCE_CLK_TOP_LIN0, + sysctl_resource_clk_top_lin1 = SYSCTL_RESOURCE_CLK_TOP_LIN1, + sysctl_resource_clk_top_lin2 = SYSCTL_RESOURCE_CLK_TOP_LIN2, + sysctl_resource_clk_top_lin3 = SYSCTL_RESOURCE_CLK_TOP_LIN3, + sysctl_resource_clk_top_lin4 = SYSCTL_RESOURCE_CLK_TOP_LIN4, + sysctl_resource_clk_top_lin5 = SYSCTL_RESOURCE_CLK_TOP_LIN5, + sysctl_resource_clk_top_lin6 = SYSCTL_RESOURCE_CLK_TOP_LIN6, + sysctl_resource_clk_top_lin7 = SYSCTL_RESOURCE_CLK_TOP_LIN7, + sysctl_resource_clk_top_i2c0 = SYSCTL_RESOURCE_CLK_TOP_I2C0, + sysctl_resource_clk_top_i2c1 = SYSCTL_RESOURCE_CLK_TOP_I2C1, + sysctl_resource_clk_top_i2c2 = SYSCTL_RESOURCE_CLK_TOP_I2C2, + sysctl_resource_clk_top_i2c3 = SYSCTL_RESOURCE_CLK_TOP_I2C3, + sysctl_resource_clk_top_spi0 = SYSCTL_RESOURCE_CLK_TOP_SPI0, + sysctl_resource_clk_top_spi1 = SYSCTL_RESOURCE_CLK_TOP_SPI1, + sysctl_resource_clk_top_spi2 = SYSCTL_RESOURCE_CLK_TOP_SPI2, + sysctl_resource_clk_top_spi3 = SYSCTL_RESOURCE_CLK_TOP_SPI3, + sysctl_resource_clk_top_uart0 = SYSCTL_RESOURCE_CLK_TOP_URT0, + sysctl_resource_clk_top_uart1 = SYSCTL_RESOURCE_CLK_TOP_URT1, + sysctl_resource_clk_top_uart2 = SYSCTL_RESOURCE_CLK_TOP_URT2, + sysctl_resource_clk_top_uart3 = SYSCTL_RESOURCE_CLK_TOP_URT3, + sysctl_resource_clk_top_uart4 = SYSCTL_RESOURCE_CLK_TOP_URT4, + sysctl_resource_clk_top_uart5 = SYSCTL_RESOURCE_CLK_TOP_URT5, + sysctl_resource_clk_top_uart6 = SYSCTL_RESOURCE_CLK_TOP_URT6, + sysctl_resource_clk_top_uart7 = SYSCTL_RESOURCE_CLK_TOP_URT7, + sysctl_resource_clk_top_gptmr0 = SYSCTL_RESOURCE_CLK_TOP_TMR0, + sysctl_resource_clk_top_gptmr1 = SYSCTL_RESOURCE_CLK_TOP_TMR1, + sysctl_resource_clk_top_gptmr2 = SYSCTL_RESOURCE_CLK_TOP_TMR2, + sysctl_resource_clk_top_gptmr3 = SYSCTL_RESOURCE_CLK_TOP_TMR3, + sysctl_resource_clk_top_gptmr4 = SYSCTL_RESOURCE_CLK_TOP_TMR4, + sysctl_resource_clk_top_gptmr5 = SYSCTL_RESOURCE_CLK_TOP_TMR5, + sysctl_resource_clk_top_gptmr6 = SYSCTL_RESOURCE_CLK_TOP_TMR6, + sysctl_resource_clk_top_gptmr7 = SYSCTL_RESOURCE_CLK_TOP_TMR7, + sysctl_resource_clk_top_xpi0 = SYSCTL_RESOURCE_CLK_TOP_XPI0, + sysctl_resource_clk_top_xram = SYSCTL_RESOURCE_CLK_TOP_XRAM, + sysctl_resource_clk_top_ana0 = SYSCTL_RESOURCE_CLK_TOP_ANA0, + sysctl_resource_clk_top_ana1 = SYSCTL_RESOURCE_CLK_TOP_ANA1, + sysctl_resource_clk_top_aud0 = SYSCTL_RESOURCE_CLK_TOP_AUD0, + sysctl_resource_clk_top_aud1 = SYSCTL_RESOURCE_CLK_TOP_AUD1, + sysctl_resource_clk_top_aud2 = SYSCTL_RESOURCE_CLK_TOP_AUD2, + sysctl_resource_clk_top_aud3 = SYSCTL_RESOURCE_CLK_TOP_AUD3, + sysctl_resource_clk_top_eth0 = SYSCTL_RESOURCE_CLK_TOP_ETH0, + sysctl_resource_clk_top_ptp0 = SYSCTL_RESOURCE_CLK_TOP_PTP0, + sysctl_resource_clk_top_sdc0 = SYSCTL_RESOURCE_CLK_TOP_SDC0, + sysctl_resource_clk_top_sdc1 = SYSCTL_RESOURCE_CLK_TOP_SDC1, + sysctl_resource_clk_top_ntm0 = SYSCTL_RESOURCE_CLK_TOP_NTM0, + sysctl_resource_clk_top_ref0 = SYSCTL_RESOURCE_CLK_TOP_REF0, + sysctl_resource_clk_top_ref1 = SYSCTL_RESOURCE_CLK_TOP_REF1, + sysctl_resource_clk_top_cam0 = SYSCTL_RESOURCE_CLK_TOP_CAM0, + sysctl_resource_clk_top_cam1 = SYSCTL_RESOURCE_CLK_TOP_CAM1, + sysctl_resource_clk_top_lcd0 = SYSCTL_RESOURCE_CLK_TOP_LCD0, + sysctl_resource_clk_top_lcd1 = SYSCTL_RESOURCE_CLK_TOP_LCD1, + sysctl_resource_clk_top_csi0 = SYSCTL_RESOURCE_CLK_TOP_CSI0, + sysctl_resource_clk_top_csi1 = SYSCTL_RESOURCE_CLK_TOP_CSI1, + sysctl_resource_clk_top_adc0 = SYSCTL_RESOURCE_CLK_TOP_ADC0, + sysctl_resource_clk_top_adc1 = SYSCTL_RESOURCE_CLK_TOP_ADC1, + sysctl_resource_clk_top_i2s0 = SYSCTL_RESOURCE_CLK_TOP_I2S0, + sysctl_resource_clk_top_i2s1 = SYSCTL_RESOURCE_CLK_TOP_I2S1, + sysctl_resource_clk_top_i2s2 = SYSCTL_RESOURCE_CLK_TOP_I2S2, + sysctl_resource_clk_top_i2s3 = SYSCTL_RESOURCE_CLK_TOP_I2S3, + + + sysctl_resource_linkable_start = 256, + sysctl_resource_axis = SYSCTL_RESOURCE_AXIS, + sysctl_resource_axic = SYSCTL_RESOURCE_AXIC, + sysctl_resource_axiv = SYSCTL_RESOURCE_AXIV, + sysctl_resource_axig = SYSCTL_RESOURCE_AXIG, + sysctl_resource_lmm0 = SYSCTL_RESOURCE_LMM0, + sysctl_resource_mchtmr0 = SYSCTL_RESOURCE_MCT0, + sysctl_resource_rom0 = SYSCTL_RESOURCE_ROM0, + sysctl_resource_ddr0 = SYSCTL_RESOURCE_DDR0, + sysctl_resource_xram = SYSCTL_RESOURCE_XRAM, + sysctl_resource_can0 = SYSCTL_RESOURCE_CAN0, + sysctl_resource_can1 = SYSCTL_RESOURCE_CAN1, + sysctl_resource_can2 = SYSCTL_RESOURCE_CAN2, + sysctl_resource_can3 = SYSCTL_RESOURCE_CAN3, + sysctl_resource_can4 = SYSCTL_RESOURCE_CAN4, + sysctl_resource_can5 = SYSCTL_RESOURCE_CAN5, + sysctl_resource_can6 = SYSCTL_RESOURCE_CAN6, + sysctl_resource_can7 = SYSCTL_RESOURCE_CAN7, + sysctl_resource_ptpc = SYSCTL_RESOURCE_PTPC, + sysctl_resource_crc0 = SYSCTL_RESOURCE_CRC0, + sysctl_resource_oamp = SYSCTL_RESOURCE_OAMP, + sysctl_resource_lin0 = SYSCTL_RESOURCE_LIN0, + sysctl_resource_lin1 = SYSCTL_RESOURCE_LIN1, + sysctl_resource_lin2 = SYSCTL_RESOURCE_LIN2, + sysctl_resource_lin3 = SYSCTL_RESOURCE_LIN3, + sysctl_resource_lin4 = SYSCTL_RESOURCE_LIN4, + sysctl_resource_lin5 = SYSCTL_RESOURCE_LIN5, + sysctl_resource_lin6 = SYSCTL_RESOURCE_LIN6, + sysctl_resource_lin7 = SYSCTL_RESOURCE_LIN7, + sysctl_resource_i2c0 = SYSCTL_RESOURCE_I2C0, + sysctl_resource_i2c1 = SYSCTL_RESOURCE_I2C1, + sysctl_resource_i2c2 = SYSCTL_RESOURCE_I2C2, + sysctl_resource_i2c3 = SYSCTL_RESOURCE_I2C3, + sysctl_resource_spi0 = SYSCTL_RESOURCE_SPI0, + sysctl_resource_spi1 = SYSCTL_RESOURCE_SPI1, + sysctl_resource_spi2 = SYSCTL_RESOURCE_SPI2, + sysctl_resource_spi3 = SYSCTL_RESOURCE_SPI3, + sysctl_resource_uart0 = SYSCTL_RESOURCE_URT0, + sysctl_resource_uart1 = SYSCTL_RESOURCE_URT1, + sysctl_resource_uart2 = SYSCTL_RESOURCE_URT2, + sysctl_resource_uart3 = SYSCTL_RESOURCE_URT3, + sysctl_resource_uart4 = SYSCTL_RESOURCE_URT4, + sysctl_resource_uart5 = SYSCTL_RESOURCE_URT5, + sysctl_resource_uart6 = SYSCTL_RESOURCE_URT6, + sysctl_resource_uart7 = SYSCTL_RESOURCE_URT7, + sysctl_resource_wdg0 = SYSCTL_RESOURCE_WDG0, + sysctl_resource_wdg1 = SYSCTL_RESOURCE_WDG1, + sysctl_resource_mbx0 = SYSCTL_RESOURCE_MBX0, + sysctl_resource_mbx1 = SYSCTL_RESOURCE_MBX1, + sysctl_resource_gptmr0 = SYSCTL_RESOURCE_TMR0, + sysctl_resource_gptmr1 = SYSCTL_RESOURCE_TMR1, + sysctl_resource_gptmr2 = SYSCTL_RESOURCE_TMR2, + sysctl_resource_gptmr3 = SYSCTL_RESOURCE_TMR3, + sysctl_resource_gptmr4 = SYSCTL_RESOURCE_TMR4, + sysctl_resource_gptmr5 = SYSCTL_RESOURCE_TMR5, + sysctl_resource_gptmr6 = SYSCTL_RESOURCE_TMR6, + sysctl_resource_gptmr7 = SYSCTL_RESOURCE_TMR7, + sysctl_resource_i2s0 = SYSCTL_RESOURCE_I2S0, + sysctl_resource_i2s1 = SYSCTL_RESOURCE_I2S1, + sysctl_resource_i2s2 = SYSCTL_RESOURCE_I2S2, + sysctl_resource_i2s3 = SYSCTL_RESOURCE_I2S3, + sysctl_resource_pdm0 = SYSCTL_RESOURCE_PDM0, + sysctl_resource_dao0 = SYSCTL_RESOURCE_DAO0, + sysctl_resource_smix = SYSCTL_RESOURCE_SMIX, + sysctl_resource_rng0 = SYSCTL_RESOURCE_RNG0, + sysctl_resource_sdp0 = SYSCTL_RESOURCE_SDP0, + sysctl_resource_kman = SYSCTL_RESOURCE_KMAN, + sysctl_resource_gpio = SYSCTL_RESOURCE_GPIO, + sysctl_resource_adc0 = SYSCTL_RESOURCE_ADC0, + sysctl_resource_adc1 = SYSCTL_RESOURCE_ADC1, + sysctl_resource_sdm0 = SYSCTL_RESOURCE_SDM0, + sysctl_resource_dma0 = SYSCTL_RESOURCE_HDMA, + sysctl_resource_dma1 = SYSCTL_RESOURCE_XDMA, + sysctl_resource_xpi0 = SYSCTL_RESOURCE_XPI0, + sysctl_resource_ffa0 = SYSCTL_RESOURCE_FFA0, + sysctl_resource_tsns = SYSCTL_RESOURCE_TSNS, + sysctl_resource_eth0 = SYSCTL_RESOURCE_ETH0, + sysctl_resource_usb0 = SYSCTL_RESOURCE_USB0, + sysctl_resource_sdc0 = SYSCTL_RESOURCE_SDC0, + sysctl_resource_sdc1 = SYSCTL_RESOURCE_SDC1, + sysctl_resource_ntm0 = SYSCTL_RESOURCE_NTM0, + sysctl_resource_ref0 = SYSCTL_RESOURCE_REF0, + sysctl_resource_ref1 = SYSCTL_RESOURCE_REF1, + sysctl_resource_cam0 = SYSCTL_RESOURCE_CAM0, + sysctl_resource_cam1 = SYSCTL_RESOURCE_CAM1, + sysctl_resource_pdma = SYSCTL_RESOURCE_PDMA, + sysctl_resource_jpeg = SYSCTL_RESOURCE_JPEG, + sysctl_resource_lcd0 = SYSCTL_RESOURCE_LCD0, + sysctl_resource_lcd1 = SYSCTL_RESOURCE_LCD1, + sysctl_resource_gwc0 = SYSCTL_RESOURCE_GWC0, + sysctl_resource_gwc1 = SYSCTL_RESOURCE_GWC1, + sysctl_resource_csi0 = SYSCTL_RESOURCE_CSI0, + sysctl_resource_csi1 = SYSCTL_RESOURCE_CSI1, + sysctl_resource_dsi0 = SYSCTL_RESOURCE_DSI0, + sysctl_resource_dsi1 = SYSCTL_RESOURCE_DSI1, + sysctl_resource_lvb0 = SYSCTL_RESOURCE_LVB0, + sysctl_resource_lcb0 = SYSCTL_RESOURCE_LCB0, + sysctl_resource_gpu0 = SYSCTL_RESOURCE_GPU0, + sysctl_resource_linkable_end, + sysctl_resource_end = sysctl_resource_linkable_end, +} sysctl_resource_t; + +/** + * @brief Resource modes + */ +typedef enum { + sysctl_resource_mode_auto = 0, + sysctl_resource_mode_force_on, + sysctl_resource_mode_force_off, +} sysctl_resource_mode_t; + +/** + * @brief Clock nodes + */ +typedef enum { + clock_node_cpu0 = SYSCTL_CLOCK_CLK_TOP_CPU0, + clock_node_mchtmr0 = SYSCTL_CLOCK_CLK_TOP_MCT0, + clock_node_gpu0 = SYSCTL_CLOCK_CLK_TOP_GPU0, + clock_node_axif, + clock_node_axis, + clock_node_axic, + clock_node_axiv, + clock_node_axid, + clock_node_can0 = SYSCTL_CLOCK_CLK_TOP_CAN0, + clock_node_can1 = SYSCTL_CLOCK_CLK_TOP_CAN1, + clock_node_can2 = SYSCTL_CLOCK_CLK_TOP_CAN2, + clock_node_can3 = SYSCTL_CLOCK_CLK_TOP_CAN3, + clock_node_can4, + clock_node_can5, + clock_node_can6, + clock_node_can7, + clock_node_lin0 = SYSCTL_CLOCK_CLK_TOP_LIN0, + clock_node_lin1 = SYSCTL_CLOCK_CLK_TOP_LIN1, + clock_node_lin2 = SYSCTL_CLOCK_CLK_TOP_LIN2, + clock_node_lin3 = SYSCTL_CLOCK_CLK_TOP_LIN3, + clock_node_lin4, + clock_node_lin5, + clock_node_lin6, + clock_node_lin7, + clock_node_i2c0 = SYSCTL_CLOCK_CLK_TOP_I2C0, + clock_node_i2c1 = SYSCTL_CLOCK_CLK_TOP_I2C1, + clock_node_i2c2 = SYSCTL_CLOCK_CLK_TOP_I2C2, + clock_node_i2c3 = SYSCTL_CLOCK_CLK_TOP_I2C3, + clock_node_spi0 = SYSCTL_CLOCK_CLK_TOP_SPI0, + clock_node_spi1 = SYSCTL_CLOCK_CLK_TOP_SPI1, + clock_node_spi2 = SYSCTL_CLOCK_CLK_TOP_SPI2, + clock_node_spi3 = SYSCTL_CLOCK_CLK_TOP_SPI3, + clock_node_uart0 = SYSCTL_CLOCK_CLK_TOP_URT0, + clock_node_uart1 = SYSCTL_CLOCK_CLK_TOP_URT1, + clock_node_uart2 = SYSCTL_CLOCK_CLK_TOP_URT2, + clock_node_uart3 = SYSCTL_CLOCK_CLK_TOP_URT3, + clock_node_uart4 = SYSCTL_CLOCK_CLK_TOP_URT4, + clock_node_uart5 = SYSCTL_CLOCK_CLK_TOP_URT5, + clock_node_uart6 = SYSCTL_CLOCK_CLK_TOP_URT6, + clock_node_uart7 = SYSCTL_CLOCK_CLK_TOP_URT7, + + clock_node_gptmr0 = SYSCTL_CLOCK_CLK_TOP_TMR0, + clock_node_gptmr1 = SYSCTL_CLOCK_CLK_TOP_TMR1, + clock_node_gptmr2 = SYSCTL_CLOCK_CLK_TOP_TMR2, + clock_node_gptmr3 = SYSCTL_CLOCK_CLK_TOP_TMR3, + clock_node_gptmr4 = SYSCTL_CLOCK_CLK_TOP_TMR4, + clock_node_gptmr5 = SYSCTL_CLOCK_CLK_TOP_TMR5, + clock_node_gptmr6 = SYSCTL_CLOCK_CLK_TOP_TMR6, + clock_node_gptmr7 = SYSCTL_CLOCK_CLK_TOP_TMR7, + clock_node_xpi0 = SYSCTL_CLOCK_CLK_TOP_XPI0, + clock_node_xram, + clock_node_ana0 = SYSCTL_CLOCK_CLK_TOP_ANA0, + clock_node_ana1 = SYSCTL_CLOCK_CLK_TOP_ANA1, + clock_node_aud0, + clock_node_aud1, + clock_node_aud2, + clock_node_aud3, + clock_node_eth0, + clock_node_ptp0, + clock_node_sdc0, + clock_node_sdc1, + clock_node_ntm0, + clock_node_ref0 = SYSCTL_CLOCK_CLK_TOP_REF0, + clock_node_ref1 = SYSCTL_CLOCK_CLK_TOP_REF1, + clock_node_cam0, + clock_node_cam1, + clock_node_lcd0, + clock_node_lcd1, + clock_node_csi0, + clock_node_csi1, + + clock_node_adc_start, + clock_node_adc0 = clock_node_adc_start, + clock_node_adc1, + + clock_node_i2s_start, + clock_node_i2s0 = clock_node_i2s_start, + clock_node_i2s1, + clock_node_i2s2, + clock_node_i2s3, + + clock_node_end, + clock_node_invalid = 0xff, +} clock_node_t; + +/** + * @brief General clock sources + */ +typedef enum { + clock_source_osc0_clk0 = 0, + clock_source_pll0_clk0 = 1, + clock_source_pll1_clk0 = 2, + clock_source_pll1_clk1 = 3, + clock_source_pll2_clk0 = 4, + clock_source_pll2_clk1 = 5, + clock_source_pll3_clk0 = 6, + clock_source_pll4_clk0 = 7, + clock_source_general_source_end, +} clock_source_t; + +/** + * @brief ADC clock sources + */ +typedef enum { + clock_source_adc_ana_clock = 0, + clock_source_adc_ahb_clock = 1, + clock_source_adc_clk_end, +} clock_source_adc_t; + +/** + * @brief I2S clock sources + */ +typedef enum { + clock_source_i2s_audn_clock = 0, + clock_source_i2s_audx_clock = 1, + clock_source_i2s_clk_end, +} clock_source_i2s_t; + +/** + * @brief CPU low power mode + */ +typedef enum { + cpu_lp_mode_gate_cpu_clock = 0, + cpu_lp_mode_trigger_system_lp = 0x1, + cpu_lp_mode_ungate_cpu_clock = 0x2, +} cpu_lp_mode_t; + +/** + * @brief Monitor targets + */ +/* FIXME */ +typedef enum { + monitor_target_clk_32k = 0, + monitor_target_clk_irc24m = 1, + monitor_target_clk_xtal_24m = 2, + monitor_target_clk_usb0_phy = 3, + monitor_target_clk_usb1_phy = 4, + monitor_target_clk0_osc0 = 8, + monitor_target_clk0_pll0 = 9, + monitor_target_clk0_pll1 = 10, + monitor_target_clk1_pll1 = 11, + monitor_target_clk0_pll2 = 12, + monitor_target_clk1_pll2 = 13, + monitor_target_clk0_pll3 = 14, + monitor_target_clk0_pll4 = 15, + monitor_target_clk_top_cpu0 = 128, + monitor_target_clk_top_mchtmr0 = 129, + monitor_target_clk_top_cpu1 = 130, + monitor_target_clk_top_mchtmr1 = 131, + monitor_target_clk_top_axi0 = 132, + monitor_target_clk_top_axi1 = 133, + monitor_target_clk_top_axi2 = 134, + monitor_target_clk_top_ahb0 = 135, + monitor_target_clk_top_dram = 136, + monitor_target_clk_top_xpi0 = 137, + monitor_target_clk_top_xpi1 = 138, + monitor_target_clk_top_gptmr0 = 139, + monitor_target_clk_top_gptmr1 = 140, + monitor_target_clk_top_gptmr2 = 141, + monitor_target_clk_top_gptmr3 = 142, + monitor_target_clk_top_gptmr4 = 143, + monitor_target_clk_top_gptmr5 = 144, + monitor_target_clk_top_gptmr6 = 145, + monitor_target_clk_top_gptmr7 = 146, + monitor_target_clk_top_uart0 = 147, + monitor_target_clk_top_uart1 = 148, + monitor_target_clk_top_uart2 = 149, + monitor_target_clk_top_uart3 = 150, + monitor_target_clk_top_uart4 = 151, + monitor_target_clk_top_uart5 = 152, + monitor_target_clk_top_uart6 = 153, + monitor_target_clk_top_uart7 = 154, + monitor_target_clk_top_uart8 = 155, + monitor_target_clk_top_uart9 = 156, + monitor_target_clk_top_uarta = 157, + monitor_target_clk_top_uartb = 158, + monitor_target_clk_top_uartc = 159, + monitor_target_clk_top_uartd = 160, + monitor_target_clk_top_uarte = 161, + monitor_target_clk_top_uartf = 162, + monitor_target_clk_top_i2c0 = 163, + monitor_target_clk_top_i2c1 = 164, + monitor_target_clk_top_i2c2 = 165, + monitor_target_clk_top_i2c3 = 166, + monitor_target_clk_top_spi0 = 167, + monitor_target_clk_top_spi1 = 168, + monitor_target_clk_top_spi2 = 169, + monitor_target_clk_top_spi3 = 170, + monitor_target_clk_top_can0 = 171, + monitor_target_clk_top_can1 = 172, + monitor_target_clk_top_can2 = 173, + monitor_target_clk_top_can3 = 174, + monitor_target_clk_top_ptpc = 175, + monitor_target_clk_top_ana0 = 176, + monitor_target_clk_top_ana1 = 177, + monitor_target_clk_top_ana2 = 178, + monitor_target_clk_top_aud0 = 179, + monitor_target_clk_top_aud1 = 180, + monitor_target_clk_top_aud2 = 181, + monitor_target_clk_top_dis0 = 182, + monitor_target_clk_top_cam0 = 183, + monitor_target_clk_top_cam1 = 184, + monitor_target_clk_top_eth0 = 185, + monitor_target_clk_top_eth1 = 186, + monitor_target_clk_top_ptp0 = 187, + monitor_target_clk_top_ptp1 = 188, + monitor_target_clk_top_ref0 = 189, + monitor_target_clk_top_ref1 = 190, + monitor_target_clk_top_ntmr0 = 191, + monitor_target_clk_top_ntmr1 = 192, + monitor_target_clk_top_sdxc0 = 193, + monitor_target_clk_top_sdxc1 = 194, +} monitor_target_t; + +/** + * @brief Monitor work mode + */ +typedef enum { + monitor_work_mode_compare = 0, + monitor_work_mode_record = 1, +} monitor_work_mode_t; + +/** + * @brief Monitor accuracy + */ +typedef enum { + monitor_accuracy_1khz = 0, + monitor_accuracy_1hz = 1, +} monitor_accuracy_t; + +/** + * @brief Monitor reference clock source + */ +typedef enum { + monitor_reference_32khz = 0, + monitor_reference_24mhz = 1, +} monitor_reference_t; + +/** + * @brief Monitor config + */ +typedef struct monitor_config { + uint8_t divide_by; /**< Divider to be used for OBS output to pads */ + monitor_work_mode_t mode; /**< Monitor work mode */ + monitor_accuracy_t accuracy; /**< Monitor reference accuracy */ + monitor_reference_t reference; /**< Monitor reference clock source */ + monitor_target_t target; /**< Monitor target */ + bool start_measure; /**< Start flag */ + bool enable_output; /**< Enable output to pads if true */ + uint32_t high_limit; /**< Maximum frequency at compare mode */ + uint32_t low_limit; /**< Minimum frequency at compare mode */ +} monitor_config_t; + +typedef enum { + cpu_event_flag_mask_reset = SYSCTL_CPU_LP_RESET_FLAG_MASK, + cpu_event_flag_mask_sleep = SYSCTL_CPU_LP_SLEEP_FLAG_MASK, + cpu_event_flag_mask_wake = SYSCTL_CPU_LP_WAKE_FLAG_MASK, + cpu_event_flag_mask_all = SYSCTL_CPU_LP_RESET_FLAG_MASK | SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK, +} cpu_event_flag_mask_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Check if monitor result is valid + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * + * @return true if it is valid + */ +static inline bool sysctl_monitor_result_is_valid(SYSCTL_Type *ptr, uint8_t monitor_index) +{ + return SYSCTL_MONITOR_CONTROL_VALID_GET(ptr->MONITOR[monitor_index].CONTROL); +} + +/** + * @brief Get target monitor instance result + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @return value of monitor result measured + */ +static inline uint32_t sysctl_monitor_get_current_result(SYSCTL_Type *ptr, uint8_t monitor_index) +{ + while (!sysctl_monitor_result_is_valid(ptr, monitor_index)) { + } + return ptr->MONITOR[monitor_index].CURRENT; +} + +/** + * @brief Set work mode for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] mode monitor_work_mode_compare, monitor_work_mode_record + */ +static inline void sysctl_monitor_set_work_mode(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_work_mode_t mode) +{ + ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL & ~SYSCTL_MONITOR_CONTROL_MODE_MASK) | + (SYSCTL_MONITOR_CONTROL_MODE_SET(mode)); +} + +/** + * @brief Set minimum frequency for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] limit measurement low limit + */ +static inline hpm_stat_t sysctl_monitor_set_limit_low(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit) +{ + if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { + return status_invalid_argument; + } + ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit); + return status_success; +} + +/** + * @brief Set maximum frequency for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] limit measurement high limit + */ +static inline hpm_stat_t sysctl_monitor_set_limit_high(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit) +{ + if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { + return status_invalid_argument; + } + ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit); + return status_success; +} + +/** + * @brief Set frequency limit for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] limit_high measurement high limit + * @param[in] limit_low measurement low limit + */ +static inline hpm_stat_t sysctl_monitor_set_limit(SYSCTL_Type *ptr, + uint8_t monitor_index, + uint32_t limit_high, + uint32_t limit_low) +{ + if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { + return status_invalid_argument; + } + ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit_high); + ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit_low); + return status_success; +} + +/** + * @brief Get maximum frequency for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @return current high limit value + */ +static inline uint32_t sysctl_monitor_get_limit_high(SYSCTL_Type *ptr, uint32_t monitor_index) +{ + return SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(ptr->MONITOR[monitor_index].HIGH_LIMIT); +} + +/** + * @brief Get minimum frequency for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @return current low limit value + */ +static inline uint32_t sysctl_monitor_get_limit_low(SYSCTL_Type *ptr, uint32_t monitor_index) +{ + return SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(ptr->MONITOR[monitor_index].LOW_LIMIT); +} + +/** + * @brief Measure specific target frequency + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] target monitor target to be measured + * @param[in] enable_output enable clock obs output + * @return frequency of monitor target measured + */ +uint32_t sysctl_monitor_measure_frequency(SYSCTL_Type *ptr, + uint8_t monitor_index, + monitor_target_t target, + bool enable_output); + +/** + * @brief Link current CPU core its own group + * + * Once it is linked, peripherals state in that group will keep on as long as this core is not in low power mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index to enable its own affiliated group + */ +static inline void sysctl_set_enable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + ptr->AFFILIATE[cpu_index].SET = 1 << cpu_index; +} + +/** + * @brief Unlink current CPU core with its own group + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index to enable its own affiliated group + */ +static inline void sysctl_set_disable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + ptr->AFFILIATE[cpu_index].CLEAR = 1 << cpu_index; +} + +/** + * @brief Check if any resource is busy + * + * @param[in] ptr SYSCTL_Type base address + * @return true if any resource is busy + */ +static inline bool sysctl_resource_any_is_busy(SYSCTL_Type *ptr) +{ + return ptr->RESOURCE[0] & SYSCTL_RESOURCE_GLB_BUSY_MASK; +} + +/** + * @brief Check if specific target is busy + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource target resource index + * @return true if target resource is busy + */ +static inline bool sysctl_resource_target_is_busy(SYSCTL_Type *ptr, sysctl_resource_t resource) +{ + return ptr->RESOURCE[resource] & SYSCTL_RESOURCE_LOC_BUSY_MASK; +} + +/** + * @brief Set target mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource target resource index + * @param[in] mode target resource mode + */ +static inline void sysctl_resource_target_set_mode(SYSCTL_Type *ptr, + sysctl_resource_t resource, + sysctl_resource_mode_t mode) +{ + ptr->RESOURCE[resource] = (ptr->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | SYSCTL_RESOURCE_MODE_SET(mode); +} + +/** + * @brief Get target mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource target resource index + * @return target resource mode + */ +static inline uint8_t sysctl_resource_target_get_mode(SYSCTL_Type *ptr, + sysctl_resource_t resource) +{ + return SYSCTL_RESOURCE_MODE_GET(ptr->RESOURCE[resource]); +} + +/** + * @brief Disable resource retention when specific CPU enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index + * @param[in] mask bit mask to clear + */ +static inline void sysctl_cpu_lp_clear_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask) +{ + ptr->RETENTION[cpu_index].CLEAR = mask; +} + +/** + * @brief Enable resource retention when specific CPU enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index + * @param[in] mask bit mask to set + */ +static inline void sysctl_cpu_lp_set_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask) +{ + ptr->RETENTION[cpu_index].SET = mask; +} + +/** + * @brief Retain target domain for specific CPU + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] domain target domain power to be retained + * @param[in] retain_mem set true to retain memory/register of target domain + */ +static inline void sysctl_cpu_lp_retain_domain(SYSCTL_Type *ptr, + uint8_t cpu_index, + sysctl_retention_domain_t domain, + bool retain_mem) +{ + uint8_t set_mask = 0x1; + if ((domain < sysctl_retention_domain_xtal24m) && (domain != sysctl_retention_domain_con)) { + set_mask = retain_mem ? 0x3 : 0x1; + } + ptr->RETENTION[cpu_index].SET = (set_mask << domain); +} + +/** + * @brief Enable resource retention when specific CPU enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index + * @param[in] value value to be set + */ +static inline void sysctl_set_cpu_lp_retention(SYSCTL_Type *ptr, + uint8_t cpu_index, + uint32_t value) +{ + ptr->RETENTION[cpu_index].VALUE = value; +} + +/** + * @brief Enable resource retention when CPU0 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] value value to be set + */ +static inline void sysctl_set_cpu0_lp_retention(SYSCTL_Type *ptr, uint32_t value) +{ + sysctl_set_cpu_lp_retention(ptr, 0, value); +} + + +/** + * @brief Check if any clock is busy + * + * @param[in] ptr SYSCTL_Type base address + * @return true if any clock is busy + */ +static inline bool sysctl_clock_any_is_busy(SYSCTL_Type *ptr) +{ + return ptr->CLOCK[0] & SYSCTL_CLOCK_GLB_BUSY_MASK; +} + +/** + * @brief Clear CPU event flags + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] flags flag mask to be cleared + */ +static inline void sysctl_clear_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_event_flag_mask_t flags) +{ + ptr->CPU[cpu_index].LP |= ((SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK) & flags); +} + +/** + * @brief Clear CPU0 event flags + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] flags flag mask to be cleared + */ +static inline void sysctl_clear_cpu0_flags(SYSCTL_Type *ptr, cpu_event_flag_mask_t flags) +{ + sysctl_clear_cpu_flags(ptr, 0, flags); +} + +/** + * @brief Check if target clock is busy + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] clock target clock + * @return true if target clock is busy + */ +static inline bool sysctl_clock_target_is_busy(SYSCTL_Type *ptr, clock_node_t clock) +{ + return ptr->CLOCK[clock] & SYSCTL_CLOCK_LOC_BUSY_MASK; +} + +/** + * @brief Preserve clock setting for certain node + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] clock target clock + */ +static inline void sysctl_clock_preserve_settings(SYSCTL_Type *ptr, clock_node_t clock) +{ + ptr->CLOCK[clock] |= SYSCTL_CLOCK_PRESERVE_MASK; +} + +/** + * @brief Unpreserve clock setting for certain node + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] clock target clock + */ +static inline void sysctl_clock_unpreserve_settings(SYSCTL_Type *ptr, clock_node_t clock) +{ + ptr->CLOCK[clock] &= ~SYSCTL_CLOCK_PRESERVE_MASK; +} + +/** + * @brief Set clock preset + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] preset preset + */ +static inline void sysctl_clock_set_preset(SYSCTL_Type *ptr, sysctl_preset_t preset) +{ + ptr->GLOBAL00 = (ptr->GLOBAL00 & ~SYSCTL_GLOBAL00_MUX_MASK) | SYSCTL_GLOBAL00_MUX_SET(preset); +} + +/** + * @brief Check if target reset domain wakeup status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + * @return true if target domain was taken wakeup reset + */ +static inline bool sysctl_reset_check_target_domain_wakeup_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; +} + +/** + * @brief Clear target reset domain wakeup status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + */ +static inline void sysctl_reset_clear_target_domain_wakeup_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; +} + +/** + * @brief Clear target reset domain reset status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + * @return true if target domain was taken reset + */ +static inline bool sysctl_reset_check_target_domain_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_MASK; +} + +/** + * @brief Clear target reset domain reset status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + */ +static inline void sysctl_reset_clear_target_domain_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK; +} + +/** + * @brief Clear target reset domain for all reset status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + */ +static inline void sysctl_reset_clear_target_domain_all_flags(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK | SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; +} + +/** + * @brief Get target CPU wakeup source status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] status_index wakeup status index 0 - 7 + * @return wakeup source status mask + */ +static inline uint32_t sysctl_get_wakeup_source_status(SYSCTL_Type *ptr, uint8_t cpu_index, uint8_t status_index) +{ + return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index]; +} + +/** + * @brief Check wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] status_index wakeup status index 0 - 7 + * @param[in] mask expected status mask + * @return wakeup status according to given bit mask + */ +static inline uint32_t sysctl_check_wakeup_source_status_with_mask(SYSCTL_Type *ptr, + uint8_t cpu_index, + uint8_t status_index, + uint32_t mask) +{ + return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index] & mask; +} + +/** + * @brief Enable wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void sysctl_enable_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t cpu_index, + uint8_t enable_index, + uint32_t mask) +{ + ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] |= mask; +} + +/** + * @brief Disable wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void sysctl_disable_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t cpu_index, + uint8_t enable_index, + uint32_t mask) +{ + ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] &= ~mask; +} + +/** + * @brief Disable wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] irq_num irq number to be set as wakeup source + */ +static inline void sysctl_disable_wakeup_source_with_irq(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t irq_num) +{ + ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num >> 2] &= ~(1UL << (irq_num % 32)); +} + +/** + * @brief Enable wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] irq_num irq number to be set as wakeup source + */ +static inline void sysctl_enable_wakeup_source_with_irq(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t irq_num) +{ + ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num / 32] |= 1UL << (irq_num % 32); +} + +/** + * @brief Enable CPU0 wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] irq_num irq number to be set as wakeup source + */ +static inline void sysctl_enable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr, + uint16_t irq_num) +{ + sysctl_enable_wakeup_source_with_irq(ptr, 0, irq_num); +} + +/** + * @brief Lock CPU0 gpr with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] gpr_mask bit mask of gpr registers to be locked + */ +static inline void sysctl_cpu0_lock_gpr_with_mask(SYSCTL_Type *ptr, uint16_t gpr_mask) +{ + ptr->CPU[0].LOCK |= SYSCTL_CPU_LOCK_GPR_SET(gpr_mask); +} + +/** + * @brief Lock CPU0 lock + * + * @param[in] ptr SYSCTL_Type base address + */ +static inline void sysctl_cpu0_lock(SYSCTL_Type *ptr) +{ + ptr->CPU[0].LOCK |= SYSCTL_CPU_LOCK_LOCK_MASK; +} + +/** + * @brief Config lock + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] node clock node to be configured + * @param[in] source clock source to be used + * @param[in] divide_by clock frequency divider + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node, clock_source_t source, uint32_t divide_by); + +/** + * @brief Set ADC clock mux + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] node clock node to be configured + * @param[in] source clock source to be used + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_set_adc_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_adc_t source); + + +/** + * @brief Set I2S clock mux + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] node clock node to be configured + * @param[in] source clock source to be used + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_set_i2s_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_i2s_t source); + +/** + * @brief Set CPU0 low power mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mode target mode to set + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_set_cpu0_lp_mode(SYSCTL_Type *ptr, cpu_lp_mode_t mode); + +/** + * @brief Enable group resource + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] group target group to be modified + * @param[in] resource target resource to be added/removed from group + * @param[in] enable set true to add resource, remove otherwise + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t resource, bool enable); + +/** + * @brief Check group resource enable status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] group target group to be checked + * @param[in] resource target resource to be checked from group + * @return enable true if resource enable, false if resource disable + */ +bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t resource); + +/** + * @brief Get group resource value + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] group target group to be getted + * @param[in] index target group index + * @return group index value + */ +uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index); + +/** + * @brief Add resource to CPU0 + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource resource to be added to CPU0 + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource); + +/** + * @brief Remove resource from CPU0 + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource Resource to be removed to CPU0 + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource); + +/** + * @brief Get default monitor config + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] config Monitor config structure pointer + */ +void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config); + +/** + * @brief Initialize Monitor + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index Monitor instance to be initialized + * @param[in] config Monitor config structure pointer + */ +void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config_t *config); + +/** + * @brief Save data to CPU0 GPR starting from given index + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] start Starting GPR index + * @param[in] count Number of GPR registers to set + * @param[in] data Pointer to data buffer + * @param[in] lock Set true to lock written GPR registers after setting + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock); + +/** + * @brief Get data saved from CPU0 GPR starting from given index + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] start Starting GPR index + * @param[in] count Number of GPR registers to set + * @param[out] data Pointer of buffer to save data + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data); + +/** + * @brief Set entry point on CPU0 wakeup + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] entry Entry address for CPU0 on its wakeup + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry); + + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_SYSCTL_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_sysctl_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_sysctl_regs.h new file mode 100644 index 00000000000..d523199888b --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_sysctl_regs.h @@ -0,0 +1,1297 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_SYSCTL_H +#define HPM_SYSCTL_H + +typedef struct { + __RW uint32_t RESOURCE[353]; /* 0x0 - 0x580: Resource control register for cpu0_core */ + __R uint8_t RESERVED0[636]; /* 0x584 - 0x7FF: Reserved */ + struct { + __RW uint32_t VALUE; /* 0x800: Group setting */ + __RW uint32_t SET; /* 0x804: Group setting */ + __RW uint32_t CLEAR; /* 0x808: Group setting */ + __RW uint32_t TOGGLE; /* 0x80C: Group setting */ + } GROUP0[4]; + __R uint8_t RESERVED1[192]; /* 0x840 - 0x8FF: Reserved */ + struct { + __RW uint32_t VALUE; /* 0x900: Affiliate of Group */ + __RW uint32_t SET; /* 0x904: Affiliate of Group */ + __RW uint32_t CLEAR; /* 0x908: Affiliate of Group */ + __RW uint32_t TOGGLE; /* 0x90C: Affiliate of Group */ + } AFFILIATE[1]; + __R uint8_t RESERVED2[16]; /* 0x910 - 0x91F: Reserved */ + struct { + __RW uint32_t VALUE; /* 0x920: Retention Control */ + __RW uint32_t SET; /* 0x924: Retention Control */ + __RW uint32_t CLEAR; /* 0x928: Retention Control */ + __RW uint32_t TOGGLE; /* 0x92C: Retention Control */ + } RETENTION[1]; + __R uint8_t RESERVED3[1744]; /* 0x930 - 0xFFF: Reserved */ + struct { + __RW uint32_t STATUS; /* 0x1000: Power Setting */ + __RW uint32_t LF_WAIT; /* 0x1004: Power Setting */ + __R uint8_t RESERVED0[4]; /* 0x1008 - 0x100B: Reserved */ + __RW uint32_t OFF_WAIT; /* 0x100C: Power Setting */ + } POWER[3]; + __R uint8_t RESERVED4[976]; /* 0x1030 - 0x13FF: Reserved */ + struct { + __RW uint32_t CONTROL; /* 0x1400: Reset Setting */ + __RW uint32_t CONFIG; /* 0x1404: Reset Setting */ + __R uint8_t RESERVED0[4]; /* 0x1408 - 0x140B: Reserved */ + __RW uint32_t COUNTER; /* 0x140C: Reset Setting */ + } RESET[5]; + __R uint8_t RESERVED5[944]; /* 0x1450 - 0x17FF: Reserved */ + __RW uint32_t CLOCK[69]; /* 0x1800 - 0x1910: Clock setting */ + __R uint8_t RESERVED6[748]; /* 0x1914 - 0x1BFF: Reserved */ + __RW uint32_t ADCCLK[2]; /* 0x1C00 - 0x1C04: Clock setting */ + __RW uint32_t I2SCLK[4]; /* 0x1C08 - 0x1C14: Clock setting */ + __R uint8_t RESERVED7[1000]; /* 0x1C18 - 0x1FFF: Reserved */ + __RW uint32_t GLOBAL00; /* 0x2000: Clock senario */ + __R uint8_t RESERVED8[1020]; /* 0x2004 - 0x23FF: Reserved */ + struct { + __RW uint32_t CONTROL; /* 0x2400: Clock measure and monitor control */ + __R uint32_t CURRENT; /* 0x2404: Clock measure result */ + __RW uint32_t LOW_LIMIT; /* 0x2408: Clock lower limit */ + __RW uint32_t HIGH_LIMIT; /* 0x240C: Clock upper limit */ + __R uint8_t RESERVED0[16]; /* 0x2410 - 0x241F: Reserved */ + } MONITOR[4]; + __R uint8_t RESERVED9[896]; /* 0x2480 - 0x27FF: Reserved */ + struct { + __RW uint32_t LP; /* 0x2800: CPU0 LP control */ + __RW uint32_t LOCK; /* 0x2804: CPU0 Lock GPR */ + __RW uint32_t GPR[14]; /* 0x2808 - 0x283C: CPU0 GPR0 */ + __R uint32_t WAKEUP_STATUS[4]; /* 0x2840 - 0x284C: CPU0 wakeup IRQ status */ + __R uint8_t RESERVED0[48]; /* 0x2850 - 0x287F: Reserved */ + __RW uint32_t WAKEUP_ENABLE[4]; /* 0x2880 - 0x288C: CPU0 wakeup IRQ enable */ + __R uint8_t RESERVED1[880]; /* 0x2890 - 0x2BFF: Reserved */ + } CPU[1]; +} SYSCTL_Type; + + +/* Bitfield definition for register array: RESOURCE */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any nodes + * 1: any of nodes is changing status + */ +#define SYSCTL_RESOURCE_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_RESOURCE_GLB_BUSY_SHIFT (31U) +#define SYSCTL_RESOURCE_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_GLB_BUSY_MASK) >> SYSCTL_RESOURCE_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: no change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_RESOURCE_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_RESOURCE_LOC_BUSY_SHIFT (30U) +#define SYSCTL_RESOURCE_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_LOC_BUSY_MASK) >> SYSCTL_RESOURCE_LOC_BUSY_SHIFT) + +/* + * MODE (RW) + * + * resource work mode + * 0:auto turn on and off as system required(recommended) + * 1:always on + * 2:always off + * 3:reserved + */ +#define SYSCTL_RESOURCE_MODE_MASK (0x3U) +#define SYSCTL_RESOURCE_MODE_SHIFT (0U) +#define SYSCTL_RESOURCE_MODE_SET(x) (((uint32_t)(x) << SYSCTL_RESOURCE_MODE_SHIFT) & SYSCTL_RESOURCE_MODE_MASK) +#define SYSCTL_RESOURCE_MODE_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_MODE_MASK) >> SYSCTL_RESOURCE_MODE_SHIFT) + +/* Bitfield definition for register of struct array GROUP0: VALUE */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: peripheral is not needed + * 1: periphera is needed + */ +#define SYSCTL_GROUP0_VALUE_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP0_VALUE_LINK_SHIFT (0U) +#define SYSCTL_GROUP0_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_VALUE_LINK_SHIFT) & SYSCTL_GROUP0_VALUE_LINK_MASK) +#define SYSCTL_GROUP0_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_VALUE_LINK_MASK) >> SYSCTL_GROUP0_VALUE_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP0: SET */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: no effect + * 1: add periphera into this group，periphera is needed + */ +#define SYSCTL_GROUP0_SET_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP0_SET_LINK_SHIFT (0U) +#define SYSCTL_GROUP0_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_SET_LINK_SHIFT) & SYSCTL_GROUP0_SET_LINK_MASK) +#define SYSCTL_GROUP0_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_SET_LINK_MASK) >> SYSCTL_GROUP0_SET_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP0: CLEAR */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: no effect + * 1: delete periphera in this group，periphera is not needed + */ +#define SYSCTL_GROUP0_CLEAR_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP0_CLEAR_LINK_SHIFT (0U) +#define SYSCTL_GROUP0_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_CLEAR_LINK_SHIFT) & SYSCTL_GROUP0_CLEAR_LINK_MASK) +#define SYSCTL_GROUP0_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_CLEAR_LINK_MASK) >> SYSCTL_GROUP0_CLEAR_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP0: TOGGLE */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: no effect + * 1: toggle the result that whether periphera is needed before + */ +#define SYSCTL_GROUP0_TOGGLE_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP0_TOGGLE_LINK_SHIFT (0U) +#define SYSCTL_GROUP0_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) +#define SYSCTL_GROUP0_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) >> SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) + +/* Bitfield definition for register of struct array AFFILIATE: VALUE */ +/* + * LINK (RW) + * + * Affiliate groups of cpu0, each bit represents a group + * bit0: cpu0 depends on group0 + * bit1: cpu0 depends on group1 + * bit2: cpu0 depends on group2 + * bit3: cpu0 depends on group3 + */ +#define SYSCTL_AFFILIATE_VALUE_LINK_MASK (0xFU) +#define SYSCTL_AFFILIATE_VALUE_LINK_SHIFT (0U) +#define SYSCTL_AFFILIATE_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) +#define SYSCTL_AFFILIATE_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) >> SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) + +/* Bitfield definition for register of struct array AFFILIATE: SET */ +/* + * LINK (RW) + * + * Affiliate groups of cpu0，each bit represents a group + * 0: no effect + * 1: the group is assigned to CPU0 + */ +#define SYSCTL_AFFILIATE_SET_LINK_MASK (0xFU) +#define SYSCTL_AFFILIATE_SET_LINK_SHIFT (0U) +#define SYSCTL_AFFILIATE_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_SET_LINK_SHIFT) & SYSCTL_AFFILIATE_SET_LINK_MASK) +#define SYSCTL_AFFILIATE_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_SET_LINK_MASK) >> SYSCTL_AFFILIATE_SET_LINK_SHIFT) + +/* Bitfield definition for register of struct array AFFILIATE: CLEAR */ +/* + * LINK (RW) + * + * Affiliate groups of cpu0, each bit represents a group + * 0: no effect + * 1: the group is not assigned to CPU0 + */ +#define SYSCTL_AFFILIATE_CLEAR_LINK_MASK (0xFU) +#define SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT (0U) +#define SYSCTL_AFFILIATE_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) +#define SYSCTL_AFFILIATE_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) >> SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) + +/* Bitfield definition for register of struct array AFFILIATE: TOGGLE */ +/* + * LINK (RW) + * + * Affiliate groups of cpu0, each bit represents a group + * 0: no effect + * 1: toggle the result that whether the group is assigned to CPU0 before + */ +#define SYSCTL_AFFILIATE_TOGGLE_LINK_MASK (0xFU) +#define SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT (0U) +#define SYSCTL_AFFILIATE_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) +#define SYSCTL_AFFILIATE_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) >> SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) + +/* Bitfield definition for register of struct array RETENTION: VALUE */ +/* + * LINK (RW) + * + * retention setting while CPU0 enter stop mode, each bit represents a resource + * bit00: soc_mem is kept on while cpu0 stop + * bit01: soc_ctx is kept on while cpu0 stop + * bit02: cpu0_mem is kept on while cpu0 stop + * bit03: cpu0_ctx is kept on while cpu0 stop + * bit04: con_ctx is kept on while cpu0 stop + * bit05: vis_mem is kept on while cpu0 stop + * bit06: vis_ctx is kept on while cpu0 stop + * bit07: gpu_mem is kept on while cpu0 stop + * bit08: gpu_ctx is kept on while cpu0 stop + * bit09: xtal_hold is kept on while cpu0 stop + * bit10: pll0_hold is kept on while cpu0 stop + * bit11: pll1_hold is kept on while cpu0 stop + * bit12: pll2_hold is kept on while cpu0 stop + * bit13: pll3 is kept on while cpu0 stop + * bit14: pll4 is kept on while cpu0 stop + */ +#define SYSCTL_RETENTION_VALUE_LINK_MASK (0x7FFFU) +#define SYSCTL_RETENTION_VALUE_LINK_SHIFT (0U) +#define SYSCTL_RETENTION_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_VALUE_LINK_SHIFT) & SYSCTL_RETENTION_VALUE_LINK_MASK) +#define SYSCTL_RETENTION_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_VALUE_LINK_MASK) >> SYSCTL_RETENTION_VALUE_LINK_SHIFT) + +/* Bitfield definition for register of struct array RETENTION: SET */ +/* + * LINK (RW) + * + * retention setting while CPU0 enter stop mode, each bit represents a resource + * 0: no effect + * 1: keep + */ +#define SYSCTL_RETENTION_SET_LINK_MASK (0x7FFFU) +#define SYSCTL_RETENTION_SET_LINK_SHIFT (0U) +#define SYSCTL_RETENTION_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_SET_LINK_SHIFT) & SYSCTL_RETENTION_SET_LINK_MASK) +#define SYSCTL_RETENTION_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_SET_LINK_MASK) >> SYSCTL_RETENTION_SET_LINK_SHIFT) + +/* Bitfield definition for register of struct array RETENTION: CLEAR */ +/* + * LINK (RW) + * + * retention setting while CPU0 enter stop mode, each bit represents a resource + * 0: no effect + * 1: no keep + */ +#define SYSCTL_RETENTION_CLEAR_LINK_MASK (0x7FFFU) +#define SYSCTL_RETENTION_CLEAR_LINK_SHIFT (0U) +#define SYSCTL_RETENTION_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_CLEAR_LINK_SHIFT) & SYSCTL_RETENTION_CLEAR_LINK_MASK) +#define SYSCTL_RETENTION_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_CLEAR_LINK_MASK) >> SYSCTL_RETENTION_CLEAR_LINK_SHIFT) + +/* Bitfield definition for register of struct array RETENTION: TOGGLE */ +/* + * LINK (RW) + * + * retention setting while CPU0 enter stop mode, each bit represents a resource + * 0: no effect + * 1: toggle the result that whether the resource is kept on while CPU0 stop before + */ +#define SYSCTL_RETENTION_TOGGLE_LINK_MASK (0x7FFFU) +#define SYSCTL_RETENTION_TOGGLE_LINK_SHIFT (0U) +#define SYSCTL_RETENTION_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) +#define SYSCTL_RETENTION_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) >> SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) + +/* Bitfield definition for register of struct array POWER: STATUS */ +/* + * FLAG (RW) + * + * flag represents power cycle happened from last clear of this bit + * 0: power domain did not edurance power cycle since last clear of this bit + * 1: power domain enduranced power cycle since last clear of this bit + */ +#define SYSCTL_POWER_STATUS_FLAG_MASK (0x80000000UL) +#define SYSCTL_POWER_STATUS_FLAG_SHIFT (31U) +#define SYSCTL_POWER_STATUS_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_SHIFT) & SYSCTL_POWER_STATUS_FLAG_MASK) +#define SYSCTL_POWER_STATUS_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_MASK) >> SYSCTL_POWER_STATUS_FLAG_SHIFT) + +/* + * FLAG_WAKE (RW) + * + * flag represents wakeup power cycle happened from last clear of this bit + * 0: power domain did not edurance wakeup power cycle since last clear of this bit + * 1: power domain enduranced wakeup power cycle since last clear of this bit + */ +#define SYSCTL_POWER_STATUS_FLAG_WAKE_MASK (0x40000000UL) +#define SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT (30U) +#define SYSCTL_POWER_STATUS_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) +#define SYSCTL_POWER_STATUS_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) >> SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) + +/* + * LF_DISABLE (RO) + * + * low fanout power switch disable + * 0: low fanout power switches are turned on + * 1: low fanout power switches are truned off + */ +#define SYSCTL_POWER_STATUS_LF_DISABLE_MASK (0x1000U) +#define SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT (12U) +#define SYSCTL_POWER_STATUS_LF_DISABLE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_DISABLE_MASK) >> SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT) + +/* + * LF_ACK (RO) + * + * low fanout power switch feedback + * 0: low fanout power switches are turned on + * 1: low fanout power switches are truned off + */ +#define SYSCTL_POWER_STATUS_LF_ACK_MASK (0x100U) +#define SYSCTL_POWER_STATUS_LF_ACK_SHIFT (8U) +#define SYSCTL_POWER_STATUS_LF_ACK_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_ACK_MASK) >> SYSCTL_POWER_STATUS_LF_ACK_SHIFT) + +/* Bitfield definition for register of struct array POWER: LF_WAIT */ +/* + * WAIT (RW) + * + * wait time for low fan out power switch turn on, default value is 255 + * 0: 0 clock cycle + * 1: 1 clock cycles + * . . . + * clock cycles count on 24MHz + */ +#define SYSCTL_POWER_LF_WAIT_WAIT_MASK (0xFFFFFUL) +#define SYSCTL_POWER_LF_WAIT_WAIT_SHIFT (0U) +#define SYSCTL_POWER_LF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) +#define SYSCTL_POWER_LF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) >> SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) + +/* Bitfield definition for register of struct array POWER: OFF_WAIT */ +/* + * WAIT (RW) + * + * wait time for power switch turn off, default value is 15 + * 0: 0 clock cycle + * 1: 1 clock cycles + * . . . + * clock cycles count on 24MHz + */ +#define SYSCTL_POWER_OFF_WAIT_WAIT_MASK (0xFFFFFUL) +#define SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT (0U) +#define SYSCTL_POWER_OFF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) +#define SYSCTL_POWER_OFF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) >> SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) + +/* Bitfield definition for register of struct array RESET: CONTROL */ +/* + * FLAG (RW) + * + * flag represents reset happened from last clear of this bit + * 0: domain did not edurance reset cycle since last clear of this bit + * 1: domain enduranced reset cycle since last clear of this bit + */ +#define SYSCTL_RESET_CONTROL_FLAG_MASK (0x80000000UL) +#define SYSCTL_RESET_CONTROL_FLAG_SHIFT (31U) +#define SYSCTL_RESET_CONTROL_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_MASK) +#define SYSCTL_RESET_CONTROL_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_MASK) >> SYSCTL_RESET_CONTROL_FLAG_SHIFT) + +/* + * FLAG_WAKE (RW) + * + * flag represents wakeup reset happened from last clear of this bit + * 0: domain did not edurance wakeup reset cycle since last clear of this bit + * 1: domain enduranced wakeup reset cycle since last clear of this bit + */ +#define SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK (0x40000000UL) +#define SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT (30U) +#define SYSCTL_RESET_CONTROL_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) +#define SYSCTL_RESET_CONTROL_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) >> SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) + +/* + * HOLD (RW) + * + * perform reset and hold in reset, until ths bit cleared by software + * 0: reset is released for function + * 1: reset is assert and hold + */ +#define SYSCTL_RESET_CONTROL_HOLD_MASK (0x10U) +#define SYSCTL_RESET_CONTROL_HOLD_SHIFT (4U) +#define SYSCTL_RESET_CONTROL_HOLD_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_HOLD_SHIFT) & SYSCTL_RESET_CONTROL_HOLD_MASK) +#define SYSCTL_RESET_CONTROL_HOLD_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_HOLD_MASK) >> SYSCTL_RESET_CONTROL_HOLD_SHIFT) + +/* + * RESET (RW) + * + * perform reset and release imediately + * 0: reset is released + * 1 reset is asserted and will release automatically + */ +#define SYSCTL_RESET_CONTROL_RESET_MASK (0x1U) +#define SYSCTL_RESET_CONTROL_RESET_SHIFT (0U) +#define SYSCTL_RESET_CONTROL_RESET_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_RESET_SHIFT) & SYSCTL_RESET_CONTROL_RESET_MASK) +#define SYSCTL_RESET_CONTROL_RESET_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_RESET_MASK) >> SYSCTL_RESET_CONTROL_RESET_SHIFT) + +/* Bitfield definition for register of struct array RESET: CONFIG */ +/* + * PRE_WAIT (RW) + * + * wait cycle numbers before assert reset + * 0: wait 0 cycle + * 1: wait 1 cycles + * . . . + * Note, clock cycle is base on 24M + */ +#define SYSCTL_RESET_CONFIG_PRE_WAIT_MASK (0xFF0000UL) +#define SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT (16U) +#define SYSCTL_RESET_CONFIG_PRE_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) +#define SYSCTL_RESET_CONFIG_PRE_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) >> SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) + +/* + * RSTCLK_NUM (RW) + * + * reset clock number(must be even number) + * 0: 0 cycle + * 1: 0 cycles + * 2: 2 cycles + * 3: 2 cycles + * . . . + * Note, clock cycle is base on 24M + */ +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK (0xFF00U) +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT (8U) +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) >> SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) + +/* + * POST_WAIT (RW) + * + * time guard band for reset release + * 0: wait 0 cycle + * 1: wait 1 cycles + * . . . + * Note, clock cycle is base on 24M + */ +#define SYSCTL_RESET_CONFIG_POST_WAIT_MASK (0xFFU) +#define SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT (0U) +#define SYSCTL_RESET_CONFIG_POST_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) +#define SYSCTL_RESET_CONFIG_POST_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) >> SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) + +/* Bitfield definition for register of struct array RESET: COUNTER */ +/* + * COUNTER (RW) + * + * self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset + * 0: wait 0 cycle + * 1: wait 1 cycles + * . . . + * Note, clock cycle is base on 24M + */ +#define SYSCTL_RESET_COUNTER_COUNTER_MASK (0xFFFFFUL) +#define SYSCTL_RESET_COUNTER_COUNTER_SHIFT (0U) +#define SYSCTL_RESET_COUNTER_COUNTER_SET(x) (((uint32_t)(x) << SYSCTL_RESET_COUNTER_COUNTER_SHIFT) & SYSCTL_RESET_COUNTER_COUNTER_MASK) +#define SYSCTL_RESET_COUNTER_COUNTER_GET(x) (((uint32_t)(x) & SYSCTL_RESET_COUNTER_COUNTER_MASK) >> SYSCTL_RESET_COUNTER_COUNTER_SHIFT) + +/* Bitfield definition for register array: CLOCK */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any clock + * 1: any of nodes is changing status + */ +#define SYSCTL_CLOCK_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_CLOCK_GLB_BUSY_SHIFT (31U) +#define SYSCTL_CLOCK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_GLB_BUSY_MASK) >> SYSCTL_CLOCK_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: a change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_CLOCK_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_CLOCK_LOC_BUSY_SHIFT (30U) +#define SYSCTL_CLOCK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_LOC_BUSY_MASK) >> SYSCTL_CLOCK_LOC_BUSY_SHIFT) + +/* + * PRESERVE (RW) + * + * preserve function against global select + * 0: select global clock setting + * 1: not select global clock setting + */ +#define SYSCTL_CLOCK_PRESERVE_MASK (0x10000000UL) +#define SYSCTL_CLOCK_PRESERVE_SHIFT (28U) +#define SYSCTL_CLOCK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_PRESERVE_SHIFT) & SYSCTL_CLOCK_PRESERVE_MASK) +#define SYSCTL_CLOCK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_PRESERVE_MASK) >> SYSCTL_CLOCK_PRESERVE_SHIFT) + +/* + * MUX (RW) + * + * current mux in clock component + * 0:osc0_clk0 + * 1:pll0_clk0 + * 2:pll1_clk0 + * 3:pll1_clk1 + * 4:pll2_clk0 + * 5:pll2_clk1 + * 6:pll3_clk0 + * 7:pll4_clk0 + */ +#define SYSCTL_CLOCK_MUX_MASK (0x700U) +#define SYSCTL_CLOCK_MUX_SHIFT (8U) +#define SYSCTL_CLOCK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_MUX_SHIFT) & SYSCTL_CLOCK_MUX_MASK) +#define SYSCTL_CLOCK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_MUX_MASK) >> SYSCTL_CLOCK_MUX_SHIFT) + +/* + * DIV (RW) + * + * clock divider + * 0: divider by 1 + * 1: divider by 2 + * 2: divider by 3 + * . . . + * 255: divider by 256 + */ +#define SYSCTL_CLOCK_DIV_MASK (0xFFU) +#define SYSCTL_CLOCK_DIV_SHIFT (0U) +#define SYSCTL_CLOCK_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_DIV_SHIFT) & SYSCTL_CLOCK_DIV_MASK) +#define SYSCTL_CLOCK_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_DIV_MASK) >> SYSCTL_CLOCK_DIV_SHIFT) + +/* Bitfield definition for register array: ADCCLK */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any clock + * 1: any of nodes is changing status + */ +#define SYSCTL_ADCCLK_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_ADCCLK_GLB_BUSY_SHIFT (31U) +#define SYSCTL_ADCCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_GLB_BUSY_MASK) >> SYSCTL_ADCCLK_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: a change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_ADCCLK_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_ADCCLK_LOC_BUSY_SHIFT (30U) +#define SYSCTL_ADCCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_LOC_BUSY_MASK) >> SYSCTL_ADCCLK_LOC_BUSY_SHIFT) + +/* + * PRESERVE (RW) + * + * preserve function against global select + * 0: select global clock setting + * 1: not select global clock setting + */ +#define SYSCTL_ADCCLK_PRESERVE_MASK (0x10000000UL) +#define SYSCTL_ADCCLK_PRESERVE_SHIFT (28U) +#define SYSCTL_ADCCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_PRESERVE_SHIFT) & SYSCTL_ADCCLK_PRESERVE_MASK) +#define SYSCTL_ADCCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_PRESERVE_MASK) >> SYSCTL_ADCCLK_PRESERVE_SHIFT) + +/* + * MUX (RW) + * + * current mux + * 0: ana clock N + * 1: axi clock + */ +#define SYSCTL_ADCCLK_MUX_MASK (0x100U) +#define SYSCTL_ADCCLK_MUX_SHIFT (8U) +#define SYSCTL_ADCCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_MUX_SHIFT) & SYSCTL_ADCCLK_MUX_MASK) +#define SYSCTL_ADCCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_MUX_MASK) >> SYSCTL_ADCCLK_MUX_SHIFT) + +/* Bitfield definition for register array: I2SCLK */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any clock + * 1: any of nodes is changing status + */ +#define SYSCTL_I2SCLK_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_I2SCLK_GLB_BUSY_SHIFT (31U) +#define SYSCTL_I2SCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_GLB_BUSY_MASK) >> SYSCTL_I2SCLK_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: a change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_I2SCLK_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_I2SCLK_LOC_BUSY_SHIFT (30U) +#define SYSCTL_I2SCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_LOC_BUSY_MASK) >> SYSCTL_I2SCLK_LOC_BUSY_SHIFT) + +/* + * PRESERVE (RW) + * + * preserve function against global select + * 0: select global clock setting + * 1: not select global clock setting + */ +#define SYSCTL_I2SCLK_PRESERVE_MASK (0x10000000UL) +#define SYSCTL_I2SCLK_PRESERVE_SHIFT (28U) +#define SYSCTL_I2SCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_I2SCLK_PRESERVE_SHIFT) & SYSCTL_I2SCLK_PRESERVE_MASK) +#define SYSCTL_I2SCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_PRESERVE_MASK) >> SYSCTL_I2SCLK_PRESERVE_SHIFT) + +/* + * MUX (RW) + * + * current mux + * 0: aud clock N + * 1: aud clock 0 + */ +#define SYSCTL_I2SCLK_MUX_MASK (0x100U) +#define SYSCTL_I2SCLK_MUX_SHIFT (8U) +#define SYSCTL_I2SCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_I2SCLK_MUX_SHIFT) & SYSCTL_I2SCLK_MUX_MASK) +#define SYSCTL_I2SCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_MUX_MASK) >> SYSCTL_I2SCLK_MUX_SHIFT) + +/* Bitfield definition for register: GLOBAL00 */ +/* + * MUX (RW) + * + * global clock override request + * bit0: override to preset0 + * bit1: override to preset1 + * bit2: override to preset2 + * bit3: override to preset3 + * bit4: override to preset4 + * bit5: override to preset5 + * bit6: override to preset6 + * bit7: override to preset7 + */ +#define SYSCTL_GLOBAL00_MUX_MASK (0xFFU) +#define SYSCTL_GLOBAL00_MUX_SHIFT (0U) +#define SYSCTL_GLOBAL00_MUX_SET(x) (((uint32_t)(x) << SYSCTL_GLOBAL00_MUX_SHIFT) & SYSCTL_GLOBAL00_MUX_MASK) +#define SYSCTL_GLOBAL00_MUX_GET(x) (((uint32_t)(x) & SYSCTL_GLOBAL00_MUX_MASK) >> SYSCTL_GLOBAL00_MUX_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: CONTROL */ +/* + * VALID (RW) + * + * result is ready for read + * 0: not ready + * 1: result is ready + */ +#define SYSCTL_MONITOR_CONTROL_VALID_MASK (0x80000000UL) +#define SYSCTL_MONITOR_CONTROL_VALID_SHIFT (31U) +#define SYSCTL_MONITOR_CONTROL_VALID_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_VALID_SHIFT) & SYSCTL_MONITOR_CONTROL_VALID_MASK) +#define SYSCTL_MONITOR_CONTROL_VALID_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_VALID_MASK) >> SYSCTL_MONITOR_CONTROL_VALID_SHIFT) + +/* + * DIV_BUSY (RO) + * + * divider is applying new setting + */ +#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK (0x8000000UL) +#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT (27U) +#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT) + +/* + * OUTEN (RW) + * + * enable clock output + */ +#define SYSCTL_MONITOR_CONTROL_OUTEN_MASK (0x1000000UL) +#define SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT (24U) +#define SYSCTL_MONITOR_CONTROL_OUTEN_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) +#define SYSCTL_MONITOR_CONTROL_OUTEN_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) >> SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) + +/* + * DIV (RW) + * + * output divider + */ +#define SYSCTL_MONITOR_CONTROL_DIV_MASK (0xFF0000UL) +#define SYSCTL_MONITOR_CONTROL_DIV_SHIFT (16U) +#define SYSCTL_MONITOR_CONTROL_DIV_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_DIV_SHIFT) & SYSCTL_MONITOR_CONTROL_DIV_MASK) +#define SYSCTL_MONITOR_CONTROL_DIV_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_SHIFT) + +/* + * HIGH (RW) + * + * clock frequency higher than upper limit + */ +#define SYSCTL_MONITOR_CONTROL_HIGH_MASK (0x8000U) +#define SYSCTL_MONITOR_CONTROL_HIGH_SHIFT (15U) +#define SYSCTL_MONITOR_CONTROL_HIGH_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) +#define SYSCTL_MONITOR_CONTROL_HIGH_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) >> SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) + +/* + * LOW (RW) + * + * clock frequency lower than lower limit + */ +#define SYSCTL_MONITOR_CONTROL_LOW_MASK (0x4000U) +#define SYSCTL_MONITOR_CONTROL_LOW_SHIFT (14U) +#define SYSCTL_MONITOR_CONTROL_LOW_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_LOW_SHIFT) & SYSCTL_MONITOR_CONTROL_LOW_MASK) +#define SYSCTL_MONITOR_CONTROL_LOW_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_LOW_MASK) >> SYSCTL_MONITOR_CONTROL_LOW_SHIFT) + +/* + * START (RW) + * + * start measurement + */ +#define SYSCTL_MONITOR_CONTROL_START_MASK (0x1000U) +#define SYSCTL_MONITOR_CONTROL_START_SHIFT (12U) +#define SYSCTL_MONITOR_CONTROL_START_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_START_SHIFT) & SYSCTL_MONITOR_CONTROL_START_MASK) +#define SYSCTL_MONITOR_CONTROL_START_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_START_MASK) >> SYSCTL_MONITOR_CONTROL_START_SHIFT) + +/* + * MODE (RW) + * + * work mode, + * 0: register value will be compared to measurement + * 1: upper and lower value will be recordered in register + */ +#define SYSCTL_MONITOR_CONTROL_MODE_MASK (0x400U) +#define SYSCTL_MONITOR_CONTROL_MODE_SHIFT (10U) +#define SYSCTL_MONITOR_CONTROL_MODE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_MODE_SHIFT) & SYSCTL_MONITOR_CONTROL_MODE_MASK) +#define SYSCTL_MONITOR_CONTROL_MODE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_MODE_MASK) >> SYSCTL_MONITOR_CONTROL_MODE_SHIFT) + +/* + * ACCURACY (RW) + * + * measurement accuracy, + * 0: resolution is 1kHz + * 1: resolution is 1Hz + */ +#define SYSCTL_MONITOR_CONTROL_ACCURACY_MASK (0x200U) +#define SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT (9U) +#define SYSCTL_MONITOR_CONTROL_ACCURACY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) +#define SYSCTL_MONITOR_CONTROL_ACCURACY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) >> SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) + +/* + * REFERENCE (RW) + * + * reference clock selection, + * 0: 32k + * 1: 24M + */ +#define SYSCTL_MONITOR_CONTROL_REFERENCE_MASK (0x100U) +#define SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT (8U) +#define SYSCTL_MONITOR_CONTROL_REFERENCE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) +#define SYSCTL_MONITOR_CONTROL_REFERENCE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) >> SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) + +/* + * SELECTION (RW) + * + * clock measurement selection + */ +#define SYSCTL_MONITOR_CONTROL_SELECTION_MASK (0xFFU) +#define SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT (0U) +#define SYSCTL_MONITOR_CONTROL_SELECTION_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) +#define SYSCTL_MONITOR_CONTROL_SELECTION_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) >> SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: CURRENT */ +/* + * FREQUENCY (RO) + * + * self updating measure result + */ +#define SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK (0xFFFFFFFFUL) +#define SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT (0U) +#define SYSCTL_MONITOR_CURRENT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK) >> SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: LOW_LIMIT */ +/* + * FREQUENCY (RW) + * + * lower frequency + */ +#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL) +#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT (0U) +#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) +#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: HIGH_LIMIT */ +/* + * FREQUENCY (RW) + * + * upper frequency + */ +#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL) +#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT (0U) +#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) +#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) + +/* Bitfield definition for register of struct array CPU: LP */ +/* + * WAKE_CNT (RW) + * + * CPU0 wake up counter, counter satuated at 255, write 0x00 to clear + */ +#define SYSCTL_CPU_LP_WAKE_CNT_MASK (0xFF000000UL) +#define SYSCTL_CPU_LP_WAKE_CNT_SHIFT (24U) +#define SYSCTL_CPU_LP_WAKE_CNT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_CNT_SHIFT) & SYSCTL_CPU_LP_WAKE_CNT_MASK) +#define SYSCTL_CPU_LP_WAKE_CNT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_CNT_MASK) >> SYSCTL_CPU_LP_WAKE_CNT_SHIFT) + +/* + * HALT (RW) + * + * halt request for CPU0, + * 0: CPU0 will start to execute after reset or receive wakeup request + * 1: CPU0 will not start after reset, or wakeup after WFI + */ +#define SYSCTL_CPU_LP_HALT_MASK (0x10000UL) +#define SYSCTL_CPU_LP_HALT_SHIFT (16U) +#define SYSCTL_CPU_LP_HALT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_HALT_SHIFT) & SYSCTL_CPU_LP_HALT_MASK) +#define SYSCTL_CPU_LP_HALT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_HALT_MASK) >> SYSCTL_CPU_LP_HALT_SHIFT) + +/* + * WAKE (RO) + * + * CPU0 is waking up + * 0: CPU0 wake up not asserted + * 1: CPU0 wake up asserted + */ +#define SYSCTL_CPU_LP_WAKE_MASK (0x2000U) +#define SYSCTL_CPU_LP_WAKE_SHIFT (13U) +#define SYSCTL_CPU_LP_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_MASK) >> SYSCTL_CPU_LP_WAKE_SHIFT) + +/* + * EXEC (RO) + * + * CPU0 is executing + * 0: CPU0 is not executing + * 1: CPU0 is executing + */ +#define SYSCTL_CPU_LP_EXEC_MASK (0x1000U) +#define SYSCTL_CPU_LP_EXEC_SHIFT (12U) +#define SYSCTL_CPU_LP_EXEC_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_EXEC_MASK) >> SYSCTL_CPU_LP_EXEC_SHIFT) + +/* + * WAKE_FLAG (RW) + * + * CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit + * 0: CPU0 wakeup not happened + * 1: CPU0 wake up happened + */ +#define SYSCTL_CPU_LP_WAKE_FLAG_MASK (0x400U) +#define SYSCTL_CPU_LP_WAKE_FLAG_SHIFT (10U) +#define SYSCTL_CPU_LP_WAKE_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) +#define SYSCTL_CPU_LP_WAKE_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) >> SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) + +/* + * SLEEP_FLAG (RW) + * + * CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit + * 0: CPU0 sleep not happened + * 1: CPU0 sleep happened + */ +#define SYSCTL_CPU_LP_SLEEP_FLAG_MASK (0x200U) +#define SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT (9U) +#define SYSCTL_CPU_LP_SLEEP_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) +#define SYSCTL_CPU_LP_SLEEP_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) >> SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) + +/* + * RESET_FLAG (RW) + * + * CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit + * 0: CPU0 reset not happened + * 1: CPU0 reset happened + */ +#define SYSCTL_CPU_LP_RESET_FLAG_MASK (0x100U) +#define SYSCTL_CPU_LP_RESET_FLAG_SHIFT (8U) +#define SYSCTL_CPU_LP_RESET_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_RESET_FLAG_SHIFT) & SYSCTL_CPU_LP_RESET_FLAG_MASK) +#define SYSCTL_CPU_LP_RESET_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_RESET_FLAG_MASK) >> SYSCTL_CPU_LP_RESET_FLAG_SHIFT) + +/* + * MODE (RW) + * + * Low power mode, system behavior after WFI + * 00: CPU clock stop after WFI + * 01: System enter low power mode after WFI + * 10: Keep running after WFI + * 11: reserved + */ +#define SYSCTL_CPU_LP_MODE_MASK (0x3U) +#define SYSCTL_CPU_LP_MODE_SHIFT (0U) +#define SYSCTL_CPU_LP_MODE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_MODE_SHIFT) & SYSCTL_CPU_LP_MODE_MASK) +#define SYSCTL_CPU_LP_MODE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_MODE_MASK) >> SYSCTL_CPU_LP_MODE_SHIFT) + +/* Bitfield definition for register of struct array CPU: LOCK */ +/* + * GPR (RW) + * + * Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset + */ +#define SYSCTL_CPU_LOCK_GPR_MASK (0xFFFCU) +#define SYSCTL_CPU_LOCK_GPR_SHIFT (2U) +#define SYSCTL_CPU_LOCK_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_GPR_SHIFT) & SYSCTL_CPU_LOCK_GPR_MASK) +#define SYSCTL_CPU_LOCK_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_GPR_MASK) >> SYSCTL_CPU_LOCK_GPR_SHIFT) + +/* + * LOCK (RW) + * + * Lock bit for CPU_LOCK + */ +#define SYSCTL_CPU_LOCK_LOCK_MASK (0x2U) +#define SYSCTL_CPU_LOCK_LOCK_SHIFT (1U) +#define SYSCTL_CPU_LOCK_LOCK_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_LOCK_SHIFT) & SYSCTL_CPU_LOCK_LOCK_MASK) +#define SYSCTL_CPU_LOCK_LOCK_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_LOCK_MASK) >> SYSCTL_CPU_LOCK_LOCK_SHIFT) + +/* Bitfield definition for register of struct array CPU: GPR0 */ +/* + * GPR (RW) + * + * register for software to handle resume, can save resume address or status + */ +#define SYSCTL_CPU_GPR_GPR_MASK (0xFFFFFFFFUL) +#define SYSCTL_CPU_GPR_GPR_SHIFT (0U) +#define SYSCTL_CPU_GPR_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_GPR_GPR_SHIFT) & SYSCTL_CPU_GPR_GPR_MASK) +#define SYSCTL_CPU_GPR_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_GPR_GPR_MASK) >> SYSCTL_CPU_GPR_GPR_SHIFT) + +/* Bitfield definition for register of struct array CPU: STATUS0 */ +/* + * STATUS (RO) + * + * IRQ values + */ +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK (0xFFFFFFFFUL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT (0U) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK) >> SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT) + +/* Bitfield definition for register of struct array CPU: ENABLE0 */ +/* + * ENABLE (RW) + * + * IRQ wakeup enable + */ +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT (0U) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) >> SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) + + + +/* RESOURCE register group index macro definition */ +#define SYSCTL_RESOURCE_CPU0 (0UL) +#define SYSCTL_RESOURCE_CPX0 (1UL) +#define SYSCTL_RESOURCE_POW_VIS (21UL) +#define SYSCTL_RESOURCE_POW_CPU0 (22UL) +#define SYSCTL_RESOURCE_POW_GPU (23UL) +#define SYSCTL_RESOURCE_RST_SOC (25UL) +#define SYSCTL_RESOURCE_RST_CON (26UL) +#define SYSCTL_RESOURCE_RST_VIS (27UL) +#define SYSCTL_RESOURCE_RST_CPU0 (28UL) +#define SYSCTL_RESOURCE_RST_GPU (29UL) +#define SYSCTL_RESOURCE_CLK_SRC_XTAL (32UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL0 (33UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL0 (34UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL1 (35UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL1 (36UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL1 (37UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL2 (38UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL2 (39UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL2 (40UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL3 (41UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL3 (42UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL4 (43UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL4 (44UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL0_REF (45UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL1_REF (46UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL2_REF (47UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL3_REF (48UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL4_REF (49UL) +#define SYSCTL_RESOURCE_CLK_TOP_CPU0 (64UL) +#define SYSCTL_RESOURCE_CLK_TOP_MCT0 (65UL) +#define SYSCTL_RESOURCE_CLK_TOP_GPU0 (66UL) +#define SYSCTL_RESOURCE_CLK_TOP_AXIF (67UL) +#define SYSCTL_RESOURCE_CLK_TOP_AXIS (68UL) +#define SYSCTL_RESOURCE_CLK_TOP_AXIC (69UL) +#define SYSCTL_RESOURCE_CLK_TOP_AXIV (70UL) +#define SYSCTL_RESOURCE_CLK_TOP_AXID (71UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN0 (72UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN1 (73UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN2 (74UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN3 (75UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN4 (76UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN5 (77UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN6 (78UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN7 (79UL) +#define SYSCTL_RESOURCE_CLK_TOP_LIN0 (80UL) +#define SYSCTL_RESOURCE_CLK_TOP_LIN1 (81UL) +#define SYSCTL_RESOURCE_CLK_TOP_LIN2 (82UL) +#define SYSCTL_RESOURCE_CLK_TOP_LIN3 (83UL) +#define SYSCTL_RESOURCE_CLK_TOP_LIN4 (84UL) +#define SYSCTL_RESOURCE_CLK_TOP_LIN5 (85UL) +#define SYSCTL_RESOURCE_CLK_TOP_LIN6 (86UL) +#define SYSCTL_RESOURCE_CLK_TOP_LIN7 (87UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2C0 (88UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2C1 (89UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2C2 (90UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2C3 (91UL) +#define SYSCTL_RESOURCE_CLK_TOP_SPI0 (92UL) +#define SYSCTL_RESOURCE_CLK_TOP_SPI1 (93UL) +#define SYSCTL_RESOURCE_CLK_TOP_SPI2 (94UL) +#define SYSCTL_RESOURCE_CLK_TOP_SPI3 (95UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT0 (96UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT1 (97UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT2 (98UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT3 (99UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT4 (100UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT5 (101UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT6 (102UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT7 (103UL) +#define SYSCTL_RESOURCE_CLK_TOP_TMR0 (104UL) +#define SYSCTL_RESOURCE_CLK_TOP_TMR1 (105UL) +#define SYSCTL_RESOURCE_CLK_TOP_TMR2 (106UL) +#define SYSCTL_RESOURCE_CLK_TOP_TMR3 (107UL) +#define SYSCTL_RESOURCE_CLK_TOP_TMR4 (108UL) +#define SYSCTL_RESOURCE_CLK_TOP_TMR5 (109UL) +#define SYSCTL_RESOURCE_CLK_TOP_TMR6 (110UL) +#define SYSCTL_RESOURCE_CLK_TOP_TMR7 (111UL) +#define SYSCTL_RESOURCE_CLK_TOP_XPI0 (112UL) +#define SYSCTL_RESOURCE_CLK_TOP_XRAM (113UL) +#define SYSCTL_RESOURCE_CLK_TOP_ANA0 (114UL) +#define SYSCTL_RESOURCE_CLK_TOP_ANA1 (115UL) +#define SYSCTL_RESOURCE_CLK_TOP_AUD0 (116UL) +#define SYSCTL_RESOURCE_CLK_TOP_AUD1 (117UL) +#define SYSCTL_RESOURCE_CLK_TOP_AUD2 (118UL) +#define SYSCTL_RESOURCE_CLK_TOP_AUD3 (119UL) +#define SYSCTL_RESOURCE_CLK_TOP_ETH0 (120UL) +#define SYSCTL_RESOURCE_CLK_TOP_PTP0 (121UL) +#define SYSCTL_RESOURCE_CLK_TOP_SDC0 (122UL) +#define SYSCTL_RESOURCE_CLK_TOP_SDC1 (123UL) +#define SYSCTL_RESOURCE_CLK_TOP_NTM0 (124UL) +#define SYSCTL_RESOURCE_CLK_TOP_REF0 (125UL) +#define SYSCTL_RESOURCE_CLK_TOP_REF1 (126UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAM0 (127UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAM1 (128UL) +#define SYSCTL_RESOURCE_CLK_TOP_LCD0 (129UL) +#define SYSCTL_RESOURCE_CLK_TOP_LCD1 (130UL) +#define SYSCTL_RESOURCE_CLK_TOP_CSI0 (131UL) +#define SYSCTL_RESOURCE_CLK_TOP_CSI1 (132UL) +#define SYSCTL_RESOURCE_CLK_TOP_ADC0 (133UL) +#define SYSCTL_RESOURCE_CLK_TOP_ADC1 (134UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2S0 (135UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2S1 (136UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2S2 (137UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2S3 (138UL) +#define SYSCTL_RESOURCE_AXIS (256UL) +#define SYSCTL_RESOURCE_AXIC (257UL) +#define SYSCTL_RESOURCE_AXIV (258UL) +#define SYSCTL_RESOURCE_AXIG (259UL) +#define SYSCTL_RESOURCE_LMM0 (260UL) +#define SYSCTL_RESOURCE_MCT0 (261UL) +#define SYSCTL_RESOURCE_ROM0 (262UL) +#define SYSCTL_RESOURCE_DDR0 (263UL) +#define SYSCTL_RESOURCE_XRAM (264UL) +#define SYSCTL_RESOURCE_CAN0 (265UL) +#define SYSCTL_RESOURCE_CAN1 (266UL) +#define SYSCTL_RESOURCE_CAN2 (267UL) +#define SYSCTL_RESOURCE_CAN3 (268UL) +#define SYSCTL_RESOURCE_CAN4 (269UL) +#define SYSCTL_RESOURCE_CAN5 (270UL) +#define SYSCTL_RESOURCE_CAN6 (271UL) +#define SYSCTL_RESOURCE_CAN7 (272UL) +#define SYSCTL_RESOURCE_PTPC (273UL) +#define SYSCTL_RESOURCE_CRC0 (274UL) +#define SYSCTL_RESOURCE_OAMP (275UL) +#define SYSCTL_RESOURCE_LIN0 (276UL) +#define SYSCTL_RESOURCE_LIN1 (277UL) +#define SYSCTL_RESOURCE_LIN2 (278UL) +#define SYSCTL_RESOURCE_LIN3 (279UL) +#define SYSCTL_RESOURCE_LIN4 (280UL) +#define SYSCTL_RESOURCE_LIN5 (281UL) +#define SYSCTL_RESOURCE_LIN6 (282UL) +#define SYSCTL_RESOURCE_LIN7 (283UL) +#define SYSCTL_RESOURCE_I2C0 (284UL) +#define SYSCTL_RESOURCE_I2C1 (285UL) +#define SYSCTL_RESOURCE_I2C2 (286UL) +#define SYSCTL_RESOURCE_I2C3 (287UL) +#define SYSCTL_RESOURCE_SPI0 (288UL) +#define SYSCTL_RESOURCE_SPI1 (289UL) +#define SYSCTL_RESOURCE_SPI2 (290UL) +#define SYSCTL_RESOURCE_SPI3 (291UL) +#define SYSCTL_RESOURCE_URT0 (292UL) +#define SYSCTL_RESOURCE_URT1 (293UL) +#define SYSCTL_RESOURCE_URT2 (294UL) +#define SYSCTL_RESOURCE_URT3 (295UL) +#define SYSCTL_RESOURCE_URT4 (296UL) +#define SYSCTL_RESOURCE_URT5 (297UL) +#define SYSCTL_RESOURCE_URT6 (298UL) +#define SYSCTL_RESOURCE_URT7 (299UL) +#define SYSCTL_RESOURCE_WDG0 (300UL) +#define SYSCTL_RESOURCE_WDG1 (301UL) +#define SYSCTL_RESOURCE_MBX0 (302UL) +#define SYSCTL_RESOURCE_MBX1 (303UL) +#define SYSCTL_RESOURCE_TMR0 (304UL) +#define SYSCTL_RESOURCE_TMR1 (305UL) +#define SYSCTL_RESOURCE_TMR2 (306UL) +#define SYSCTL_RESOURCE_TMR3 (307UL) +#define SYSCTL_RESOURCE_TMR4 (308UL) +#define SYSCTL_RESOURCE_TMR5 (309UL) +#define SYSCTL_RESOURCE_TMR6 (310UL) +#define SYSCTL_RESOURCE_TMR7 (311UL) +#define SYSCTL_RESOURCE_I2S0 (312UL) +#define SYSCTL_RESOURCE_I2S1 (313UL) +#define SYSCTL_RESOURCE_I2S2 (314UL) +#define SYSCTL_RESOURCE_I2S3 (315UL) +#define SYSCTL_RESOURCE_PDM0 (316UL) +#define SYSCTL_RESOURCE_DAO0 (317UL) +#define SYSCTL_RESOURCE_SMIX (318UL) +#define SYSCTL_RESOURCE_RNG0 (319UL) +#define SYSCTL_RESOURCE_SDP0 (320UL) +#define SYSCTL_RESOURCE_KMAN (321UL) +#define SYSCTL_RESOURCE_GPIO (322UL) +#define SYSCTL_RESOURCE_ADC0 (323UL) +#define SYSCTL_RESOURCE_ADC1 (324UL) +#define SYSCTL_RESOURCE_SDM0 (325UL) +#define SYSCTL_RESOURCE_HDMA (326UL) +#define SYSCTL_RESOURCE_XDMA (327UL) +#define SYSCTL_RESOURCE_XPI0 (328UL) +#define SYSCTL_RESOURCE_FFA0 (329UL) +#define SYSCTL_RESOURCE_TSNS (330UL) +#define SYSCTL_RESOURCE_ETH0 (331UL) +#define SYSCTL_RESOURCE_USB0 (332UL) +#define SYSCTL_RESOURCE_SDC0 (333UL) +#define SYSCTL_RESOURCE_SDC1 (334UL) +#define SYSCTL_RESOURCE_NTM0 (335UL) +#define SYSCTL_RESOURCE_REF0 (336UL) +#define SYSCTL_RESOURCE_REF1 (337UL) +#define SYSCTL_RESOURCE_CAM0 (338UL) +#define SYSCTL_RESOURCE_CAM1 (339UL) +#define SYSCTL_RESOURCE_PDMA (340UL) +#define SYSCTL_RESOURCE_JPEG (341UL) +#define SYSCTL_RESOURCE_LCD0 (342UL) +#define SYSCTL_RESOURCE_LCD1 (343UL) +#define SYSCTL_RESOURCE_GWC0 (344UL) +#define SYSCTL_RESOURCE_GWC1 (345UL) +#define SYSCTL_RESOURCE_CSI0 (346UL) +#define SYSCTL_RESOURCE_CSI1 (347UL) +#define SYSCTL_RESOURCE_DSI0 (348UL) +#define SYSCTL_RESOURCE_DSI1 (349UL) +#define SYSCTL_RESOURCE_LVB0 (350UL) +#define SYSCTL_RESOURCE_LCB0 (351UL) +#define SYSCTL_RESOURCE_GPU0 (352UL) + +/* GROUP0 register group index macro definition */ +#define SYSCTL_GROUP0_LINK0 (0UL) +#define SYSCTL_GROUP0_LINK1 (1UL) +#define SYSCTL_GROUP0_LINK2 (2UL) +#define SYSCTL_GROUP0_LINK3 (3UL) + +/* AFFILIATE register group index macro definition */ +#define SYSCTL_AFFILIATE_CPU0 (0UL) + +/* RETENTION register group index macro definition */ +#define SYSCTL_RETENTION_CPU0 (0UL) + +/* POWER register group index macro definition */ +#define SYSCTL_POWER_VIS (0UL) +#define SYSCTL_POWER_CPU0 (1UL) +#define SYSCTL_POWER_GPU (2UL) + +/* RESET register group index macro definition */ +#define SYSCTL_RESET_SOC (0UL) +#define SYSCTL_RESET_CON (1UL) +#define SYSCTL_RESET_VIS (2UL) +#define SYSCTL_RESET_CPU0 (3UL) +#define SYSCTL_RESET_GPU (4UL) + +/* CLOCK register group index macro definition */ +#define SYSCTL_CLOCK_CLK_TOP_CPU0 (0UL) +#define SYSCTL_CLOCK_CLK_TOP_MCT0 (1UL) +#define SYSCTL_CLOCK_CLK_TOP_GPU0 (2UL) +#define SYSCTL_CLOCK_CLK_TOP_AXIF (3UL) +#define SYSCTL_CLOCK_CLK_TOP_AXIS (4UL) +#define SYSCTL_CLOCK_CLK_TOP_AXIC (5UL) +#define SYSCTL_CLOCK_CLK_TOP_AXIV (6UL) +#define SYSCTL_CLOCK_CLK_TOP_AXID (7UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN0 (8UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN1 (9UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN2 (10UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN3 (11UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN4 (12UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN5 (13UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN6 (14UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN7 (15UL) +#define SYSCTL_CLOCK_CLK_TOP_LIN0 (16UL) +#define SYSCTL_CLOCK_CLK_TOP_LIN1 (17UL) +#define SYSCTL_CLOCK_CLK_TOP_LIN2 (18UL) +#define SYSCTL_CLOCK_CLK_TOP_LIN3 (19UL) +#define SYSCTL_CLOCK_CLK_TOP_LIN4 (20UL) +#define SYSCTL_CLOCK_CLK_TOP_LIN5 (21UL) +#define SYSCTL_CLOCK_CLK_TOP_LIN6 (22UL) +#define SYSCTL_CLOCK_CLK_TOP_LIN7 (23UL) +#define SYSCTL_CLOCK_CLK_TOP_I2C0 (24UL) +#define SYSCTL_CLOCK_CLK_TOP_I2C1 (25UL) +#define SYSCTL_CLOCK_CLK_TOP_I2C2 (26UL) +#define SYSCTL_CLOCK_CLK_TOP_I2C3 (27UL) +#define SYSCTL_CLOCK_CLK_TOP_SPI0 (28UL) +#define SYSCTL_CLOCK_CLK_TOP_SPI1 (29UL) +#define SYSCTL_CLOCK_CLK_TOP_SPI2 (30UL) +#define SYSCTL_CLOCK_CLK_TOP_SPI3 (31UL) +#define SYSCTL_CLOCK_CLK_TOP_URT0 (32UL) +#define SYSCTL_CLOCK_CLK_TOP_URT1 (33UL) +#define SYSCTL_CLOCK_CLK_TOP_URT2 (34UL) +#define SYSCTL_CLOCK_CLK_TOP_URT3 (35UL) +#define SYSCTL_CLOCK_CLK_TOP_URT4 (36UL) +#define SYSCTL_CLOCK_CLK_TOP_URT5 (37UL) +#define SYSCTL_CLOCK_CLK_TOP_URT6 (38UL) +#define SYSCTL_CLOCK_CLK_TOP_URT7 (39UL) +#define SYSCTL_CLOCK_CLK_TOP_TMR0 (40UL) +#define SYSCTL_CLOCK_CLK_TOP_TMR1 (41UL) +#define SYSCTL_CLOCK_CLK_TOP_TMR2 (42UL) +#define SYSCTL_CLOCK_CLK_TOP_TMR3 (43UL) +#define SYSCTL_CLOCK_CLK_TOP_TMR4 (44UL) +#define SYSCTL_CLOCK_CLK_TOP_TMR5 (45UL) +#define SYSCTL_CLOCK_CLK_TOP_TMR6 (46UL) +#define SYSCTL_CLOCK_CLK_TOP_TMR7 (47UL) +#define SYSCTL_CLOCK_CLK_TOP_XPI0 (48UL) +#define SYSCTL_CLOCK_CLK_TOP_XRAM (49UL) +#define SYSCTL_CLOCK_CLK_TOP_ANA0 (50UL) +#define SYSCTL_CLOCK_CLK_TOP_ANA1 (51UL) +#define SYSCTL_CLOCK_CLK_TOP_AUD0 (52UL) +#define SYSCTL_CLOCK_CLK_TOP_AUD1 (53UL) +#define SYSCTL_CLOCK_CLK_TOP_AUD2 (54UL) +#define SYSCTL_CLOCK_CLK_TOP_AUD3 (55UL) +#define SYSCTL_CLOCK_CLK_TOP_ETH0 (56UL) +#define SYSCTL_CLOCK_CLK_TOP_PTP0 (57UL) +#define SYSCTL_CLOCK_CLK_TOP_SDC0 (58UL) +#define SYSCTL_CLOCK_CLK_TOP_SDC1 (59UL) +#define SYSCTL_CLOCK_CLK_TOP_NTM0 (60UL) +#define SYSCTL_CLOCK_CLK_TOP_REF0 (61UL) +#define SYSCTL_CLOCK_CLK_TOP_REF1 (62UL) +#define SYSCTL_CLOCK_CLK_TOP_CAM0 (63UL) +#define SYSCTL_CLOCK_CLK_TOP_CAM1 (64UL) +#define SYSCTL_CLOCK_CLK_TOP_LCD0 (65UL) +#define SYSCTL_CLOCK_CLK_TOP_LCD1 (66UL) +#define SYSCTL_CLOCK_CLK_TOP_CSI0 (67UL) +#define SYSCTL_CLOCK_CLK_TOP_CSI1 (68UL) + +/* ADCCLK register group index macro definition */ +#define SYSCTL_ADCCLK_CLK_TOP_ADC0 (0UL) +#define SYSCTL_ADCCLK_CLK_TOP_ADC1 (1UL) + +/* I2SCLK register group index macro definition */ +#define SYSCTL_I2SCLK_CLK_TOP_I2S0 (0UL) +#define SYSCTL_I2SCLK_CLK_TOP_I2S1 (1UL) +#define SYSCTL_I2SCLK_CLK_TOP_I2S2 (2UL) +#define SYSCTL_I2SCLK_CLK_TOP_I2S3 (3UL) + +/* MONITOR register group index macro definition */ +#define SYSCTL_MONITOR_SLICE0 (0UL) +#define SYSCTL_MONITOR_SLICE1 (1UL) +#define SYSCTL_MONITOR_SLICE2 (2UL) +#define SYSCTL_MONITOR_SLICE3 (3UL) + +/* GPR register group index macro definition */ +#define SYSCTL_CPU_GPR_GPR0 (0UL) +#define SYSCTL_CPU_GPR_GPR1 (1UL) +#define SYSCTL_CPU_GPR_GPR2 (2UL) +#define SYSCTL_CPU_GPR_GPR3 (3UL) +#define SYSCTL_CPU_GPR_GPR4 (4UL) +#define SYSCTL_CPU_GPR_GPR5 (5UL) +#define SYSCTL_CPU_GPR_GPR6 (6UL) +#define SYSCTL_CPU_GPR_GPR7 (7UL) +#define SYSCTL_CPU_GPR_GPR8 (8UL) +#define SYSCTL_CPU_GPR_GPR9 (9UL) +#define SYSCTL_CPU_GPR_GPR10 (10UL) +#define SYSCTL_CPU_GPR_GPR11 (11UL) +#define SYSCTL_CPU_GPR_GPR12 (12UL) +#define SYSCTL_CPU_GPR_GPR13 (13UL) + +/* WAKEUP_STATUS register group index macro definition */ +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS0 (0UL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS1 (1UL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS2 (2UL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS3 (3UL) + +/* WAKEUP_ENABLE register group index macro definition */ +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE0 (0UL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE1 (1UL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE2 (2UL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE3 (3UL) + +/* CPU register group index macro definition */ +#define SYSCTL_CPU_CPU0 (0UL) + + +#endif /* HPM_SYSCTL_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/soc_modules.list b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/soc_modules.list new file mode 100644 index 00000000000..3ca99879b6d --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/soc_modules.list @@ -0,0 +1,73 @@ +# +# Copyright (c) 2024 HPMicro +# +# SPDX-License-Identifier: BSD-3-Clause +# + +HPMSOC_HAS_HPMSDK_GPIO=y +HPMSOC_HAS_HPMSDK_PLIC=y +HPMSOC_HAS_HPMSDK_MCHTMR=y +HPMSOC_HAS_HPMSDK_PLICSW=y +HPMSOC_HAS_HPMSDK_CRC=y +HPMSOC_HAS_HPMSDK_UART=y +HPMSOC_HAS_HPMSDK_I2C=y +HPMSOC_HAS_HPMSDK_SPI=y +HPMSOC_HAS_HPMSDK_GPTMR=y +HPMSOC_HAS_HPMSDK_MBX=y +HPMSOC_HAS_HPMSDK_EWDG=y +HPMSOC_HAS_HPMSDK_DMAMUX=y +HPMSOC_HAS_HPMSDK_DMAV2=y +HPMSOC_HAS_HPMSDK_GPIOM=y +HPMSOC_HAS_HPMSDK_ADC16=y +HPMSOC_HAS_HPMSDK_I2S=y +HPMSOC_HAS_HPMSDK_DAO=y +HPMSOC_HAS_HPMSDK_PDM=y +HPMSOC_HAS_HPMSDK_SMIX=y +HPMSOC_HAS_HPMSDK_MCAN=y +HPMSOC_HAS_HPMSDK_PTPC=y +HPMSOC_HAS_HPMSDK_LCDC=y +HPMSOC_HAS_HPMSDK_CAM=y +HPMSOC_HAS_HPMSDK_PDMA=y +HPMSOC_HAS_HPMSDK_JPEG=y +HPMSOC_HAS_HPMSDK_GWC=y +HPMSOC_HAS_HPMSDK_MIPI_DSI=y +HPMSOC_HAS_HPMSDK_MIPI_CSI=y +HPMSOC_HAS_HPMSDK_LVB=y +HPMSOC_HAS_HPMSDK_PIXELMUX=y +HPMSOC_HAS_HPMSDK_LCB=y +HPMSOC_HAS_HPMSDK_GPU=y +HPMSOC_HAS_HPMSDK_ENET=y +HPMSOC_HAS_HPMSDK_USB=y +HPMSOC_HAS_HPMSDK_SDXC=y +HPMSOC_HAS_HPMSDK_DDRCTL=y +HPMSOC_HAS_HPMSDK_FFA=y +HPMSOC_HAS_HPMSDK_SDP=y +HPMSOC_HAS_HPMSDK_SEC=y +HPMSOC_HAS_HPMSDK_MON=y +HPMSOC_HAS_HPMSDK_RNG=y +HPMSOC_HAS_HPMSDK_OTP=y +HPMSOC_HAS_HPMSDK_KEYM=y +HPMSOC_HAS_HPMSDK_SYSCTL=y +HPMSOC_HAS_HPMSDK_IOC=y +HPMSOC_HAS_HPMSDK_PLLCTLV2=y +HPMSOC_HAS_HPMSDK_PPOR=y +HPMSOC_HAS_HPMSDK_PCFG=y +HPMSOC_HAS_HPMSDK_PGPR=y +HPMSOC_HAS_HPMSDK_VAD=y +HPMSOC_HAS_HPMSDK_MIPI_DSI_PHY=y +HPMSOC_HAS_HPMSDK_MIPI_CSI_PHY=y +HPMSOC_HAS_HPMSDK_DDRPHY=y +HPMSOC_HAS_HPMSDK_TSNS=y +HPMSOC_HAS_HPMSDK_BACC=y +HPMSOC_HAS_HPMSDK_BPOR=y +HPMSOC_HAS_HPMSDK_BCFG=y +HPMSOC_HAS_HPMSDK_BUTN=y +HPMSOC_HAS_HPMSDK_BGPR=y +HPMSOC_HAS_HPMSDK_RTC=y +HPMSOC_HAS_HPMSDK_BSEC=y +HPMSOC_HAS_HPMSDK_BKEY=y +HPMSOC_HAS_HPMSDK_BMON=y +HPMSOC_HAS_HPMSDK_TAMP=y +HPMSOC_HAS_HPMSDK_MONO=y +HPMSOC_HAS_HPMSDK_PMP=y + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/system.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/system.c new file mode 100644 index 00000000000..b0bf37a5b30 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/system.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" + +#ifndef CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP +#define CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP 0 +#endif + +void enable_plic_feature(void) +{ + uint32_t plic_feature = 0; +#ifndef USE_NONVECTOR_MODE + /* enabled vector mode and preemptive priority interrupt */ + plic_feature |= HPM_PLIC_FEATURE_VECTORED_MODE; +#endif +#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) + /* enabled preemptive priority interrupt */ + plic_feature |= HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ; +#endif + __plic_set_feature(HPM_PLIC_BASE, plic_feature); +} + +__attribute__((weak)) void system_init(void) +{ +#ifndef CONFIG_NOT_ENALBE_ACCESS_TO_CYCLE_CSR + uint32_t mcounteren = read_csr(CSR_MCOUNTEREN); + write_csr(CSR_MCOUNTEREN, mcounteren | 1); /* Enable MCYCLE */ +#endif + +#ifdef USE_S_MODE_IRQ + disable_global_irq(CSR_MSTATUS_MIE_MASK | CSR_MSTATUS_SIE_MASK); +#else + disable_global_irq(CSR_MSTATUS_MIE_MASK); +#endif + + disable_irq_from_intc(); +#ifdef USE_S_MODE_IRQ + disable_s_irq_from_intc(); +#endif + + enable_plic_feature(); + enable_irq_from_intc(); + +#ifdef USE_S_MODE_IRQ + delegate_irq(CSR_MIDELEG_SEI_MASK | CSR_MIDELEG_SSI_MASK | CSR_MIDELEG_STI_MASK); + enable_s_irq_from_intc(); +#if !CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP + enable_global_irq(CSR_MSTATUS_MIE_MASK | CSR_MSTATUS_SIE_MASK); +#endif +#else +#if !CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP + enable_global_irq(CSR_MSTATUS_MIE_MASK); +#endif +#endif +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/gcc/flash.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/gcc/flash.ld new file mode 100644 index 00000000000..9a4aad13dec --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/gcc/flash.ld @@ -0,0 +1,258 @@ +/* + * Copyright (c) 2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = _stack_size; +HEAP_SIZE = _heap_size; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80003000, LENGTH = _flash_size - 0x3000 + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x0120000, LENGTH = 256K + AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01240000, LENGTH = 256K + AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF4130000, LENGTH = 16k +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + /* RT-Thread related sections - Start */ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + . = ALIGN(8); + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + *(.fast.*) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > ILM + + .bss (NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > AXI_SRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); + __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/gcc/flash_sdram_uf2.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/gcc/flash_sdram_uf2.ld new file mode 100644 index 00000000000..cbf8efe63c6 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/gcc/flash_sdram_uf2.ld @@ -0,0 +1,266 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = _stack_size; +HEAP_SIZE = _heap_size; +UF2_BOOTLOADER_RESERVED_LENGTH = DEFINED(_uf2_bl_length) ? _uf2_bl_length : 0x20000; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH, LENGTH = _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x1200000, LENGTH = 512K + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = (_extram_size - 32M) + SDRAM_NONCACHEABLE (wx) : ORIGIN = 0x40000000 + (_extram_size - 32M), LENGTH = 32M + AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF4130000, LENGTH = 16k +} + +SECTIONS +{ + .start : { + KEEP(*(.uf2_signature)) + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)): { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + /* RT-Thread related sections - Start */ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + . = ALIGN(8); + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > SDRAM + + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + *(.fast.*) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > ILM + + .bss (NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > SDRAM + + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > SDRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > SDRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > SDRAM + + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > SDRAM_NONCACHEABLE + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > SDRAM_NONCACHEABLE + + .sh_mem (NOLOAD) : { + KEEP(*(.sh_mem)) + } > SHARE_RAM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > SDRAM + + .stack (NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __noncacheable_start__ = ORIGIN(SDRAM_NONCACHEABLE); + __noncacheable_end__ = ORIGIN(SDRAM_NONCACHEABLE) + LENGTH(SDRAM_NONCACHEABLE); + __share_mem_start__ = ORIGIN(SHARE_RAM); + __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/gcc/flash_sdram_xip.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/gcc/flash_sdram_xip.ld new file mode 100644 index 00000000000..1808e01de1a --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/gcc/flash_sdram_xip.ld @@ -0,0 +1,278 @@ +/* + * Copyright (c) 2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = _stack_size; +HEAP_SIZE = _heap_size; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = _flash_size + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x1200000, LENGTH = 512K + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = (_extram_size - 32M) + SDRAM_NONCACHEABLE (wx) : ORIGIN = 0x40000000 + (_extram_size - 32M), LENGTH = 32M + AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF4130000, LENGTH = 16k +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + /* RT-Thread related sections - Start */ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + . = ALIGN(8); + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > SDRAM + + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + *(.fast.*) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > ILM + + .bss (NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > SDRAM + + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > SDRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > SDRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > SDRAM + + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > SDRAM_NONCACHEABLE + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > SDRAM_NONCACHEABLE + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > SDRAM + + .stack (NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __noncacheable_start__ = ORIGIN(SDRAM_NONCACHEABLE); + __noncacheable_end__ = ORIGIN(SDRAM_NONCACHEABLE) + LENGTH(SDRAM_NONCACHEABLE); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/gcc/flash_uf2.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/gcc/flash_uf2.ld new file mode 100644 index 00000000000..9d5c4449540 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/gcc/flash_uf2.ld @@ -0,0 +1,259 @@ +/* + * Copyright (c) 2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = _stack_size; +HEAP_SIZE = _heap_size; +UF2_BOOTLOADER_RESERVED_LENGTH = DEFINED(_uf2_bl_length) ? _uf2_bl_length : 0x20000; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH, LENGTH = _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x01200000, LENGTH = 256K + AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01240000, LENGTH = 256K + AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF4130000, LENGTH = 16k +} + +SECTIONS +{ + .start : { + KEEP(*(.uf2_signature)) + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)): { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + /* RT-Thread related sections - Start */ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + . = ALIGN(8); + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + *(.fast.*) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > ILM + + .bss (NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > AXI_SRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); + __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/gcc/flash_xip.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/gcc/flash_xip.ld new file mode 100644 index 00000000000..1f8a077bda8 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/gcc/flash_xip.ld @@ -0,0 +1,277 @@ +/* + * Copyright (c) 2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = _stack_size; +HEAP_SIZE = _heap_size; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = _flash_size - 0x3000 + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x01200000, LENGTH = 256K + AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01240000, LENGTH = 256K + AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF4130000, LENGTH = 16k +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + /* RT-Thread related sections - Start */ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + . = ALIGN(8); + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + *(.fast.*) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > ILM + + .bss (NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > AXI_SRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); + __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/gcc/initfini.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/gcc/initfini.c new file mode 100644 index 00000000000..7d2b85799c8 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/gcc/initfini.c @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2021-2022 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#ifndef USE_LIBC_INITFINI +#define USE_LIBC_INITFINI 0 +#endif + +#if USE_LIBC_INITFINI + +/* + * The _init() and _fini() will be called respectively when use __libc_init_array() + * and __libc_fnit_array() in libc.a to perform constructor and destructor handling. + * The dummy versions of these functions should be provided. + */ +void _init(void) +{ +} + +void _fini(void) +{ +} + +#else + +/* These magic symbols are provided by the linker. */ +extern void (*__preinit_array_start[])(void) __attribute__((weak)); +extern void (*__preinit_array_end[])(void) __attribute__((weak)); +extern void (*__init_array_start[])(void) __attribute__((weak)); +extern void (*__init_array_end[])(void) __attribute__((weak)); + +/* + * The __libc_init_array()/__libc_fnit_array() function is used to do global + * constructor/destructor and can NOT be compilied to generate the code coverage + * data. We have the function attribute to be 'no_profile_instrument_function' + * to prevent been instrumented for coverage analysis when GCOV=1 is applied. + */ +/* Iterate over all the init routines. */ +void __libc_init_array(void) __attribute__((no_profile_instrument_function)); +void __libc_init_array(void) +{ + uint32_t count; + uint32_t i; + + count = __preinit_array_end - __preinit_array_start; + for (i = 0; i < count; i++) { + __preinit_array_start[i](); + } + + count = __init_array_end - __init_array_start; + for (i = 0; i < count; i++) { + __init_array_start[i](); + } +} + +extern void (*__fini_array_start[])(void) __attribute__((weak)); +extern void (*__fini_array_end[])(void) __attribute__((weak)); + +/* Run all the cleanup routines. */ +void __libc_fini_array(void) __attribute__((no_profile_instrument_function)); +void __libc_fini_array(void) +{ + uint32_t count; + uint32_t i; + + count = __fini_array_end - __fini_array_start; + for (i = count; i > 0; i--) { + __fini_array_start[i - 1](); + } +} + +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/gcc/ram.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/gcc/ram.ld new file mode 100644 index 00000000000..60638420f3f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/gcc/ram.ld @@ -0,0 +1,258 @@ +/* + * Copyright (c) 2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = _stack_size; +HEAP_SIZE = _heap_size; + +MEMORY +{ + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x01200000, LENGTH = 256K + AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01240000, LENGTH = 256K + AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF4130000, LENGTH = 16k +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > ILM + + .vectors : { + . = ALIGN(8); + KEEP(*(.isr_vector)) + KEEP(*(.vector_table)) + KEEP(*(.isr_s_vector)) + KEEP(*(.vector_s_table)) + . = ALIGN(8); + } > ILM + + .rel : { + KEEP(*(.rel*)) + } > ILM + + .text : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + /* RT-Thread related sections - Start */ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + . = ALIGN(8); + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + } > ILM + + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + *(.fast.*) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > ILM + + .bss (NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > AXI_SRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); + __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + __last_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); + ASSERT(((__fw_size__ <= LENGTH(ILM)) && (__last_addr__ <= (ORIGIN(ILM) + LENGTH(ILM)))), "****** FAILED! ILM has not enough space! ******") +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/gcc/start.S b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/gcc/start.S new file mode 100644 index 00000000000..2282fcf4928 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/gcc/start.S @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_csr_regs.h" + + .section .start, "ax" + + .global _start + .type _start,@function + +_start: + /* Initialize global pointer */ + .option push + .option norelax + la gp, __global_pointer$ + .option pop + + /* reset mstatus to 0*/ + csrrw x0, mstatus, x0 + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + +#ifdef INIT_EXT_RAM_FOR_DATA + la t0, _stack_safe + mv sp, t0 + call _init_ext_ram +#endif + + /* Initialize stack pointer */ + la t0, _stack + mv sp, t0 + +#ifdef CONFIG_NOT_ENABLE_ICACHE + call l1c_ic_disable +#else + call l1c_ic_enable +#endif +#ifdef CONFIG_NOT_ENABLE_DCACHE + call l1c_dc_invalidate_all + call l1c_dc_disable +#else + call l1c_dc_enable + call l1c_dc_invalidate_all +#endif + + /* + * Initialize LMA/VMA sections. + * Relocation for any sections that need to be copied from LMA to VMA. + */ + call c_startup + +#if defined(__SES_RISCV) + /* Initialize the heap */ + la a0, __heap_start__ + la a1, __heap_end__ + sub a1, a1, a0 + la t1, __SEGGER_RTL_init_heap + jalr t1 +#endif + + /* Do global constructors */ + call __libc_init_array + +#ifndef NO_CLEANUP_AT_START + /* clean up */ + call _clean_up +#endif + +#ifdef __nds_execit + /* Initialize EXEC.IT table */ + la t0, _ITB_BASE_ + csrw uitb, t0 +#endif + +#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS + #define HANDLER_TRAP freertos_risc_v_trap_handler + #define HANDLER_S_TRAP freertos_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 +#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III + #define HANDLER_TRAP ucos_risc_v_trap_handler + #define HANDLER_S_TRAP ucos_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 +#elif defined(CONFIG_THREADX) && CONFIG_THREADX + #define HANDLER_TRAP tx_risc_v_trap_handler + #define HANDLER_S_TRAP tx_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 + +#elif defined(CONFIG_RTTHREAD) && CONFIG_RTTHREAD + #define HANDLER_TRAP rtt_risc_v_trap_handler + #define HANDLER_S_TRAP rtt_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 + +#else + #define HANDLER_TRAP irq_handler_trap + #define HANDLER_S_TRAP irq_handler_s_trap +#endif + +#ifndef USE_NONVECTOR_MODE + /* Initial machine trap-vector Base */ + la t0, __vector_table + csrw mtvec, t0 + +#if defined (USE_S_MODE_IRQ) + la t0, __vector_s_table + csrw stvec, t0 +#endif + /* Enable vectored external PLIC interrupt */ + csrsi CSR_MMISC_CTL, 2 +#else + /* Initial machine trap-vector Base */ + la t0, HANDLER_TRAP + csrw mtvec, t0 +#if defined (USE_S_MODE_IRQ) + la t0, HANDLER_S_TRAP + csrw stvec, t0 +#endif + + /* Disable vectored external PLIC interrupt */ + csrci CSR_MMISC_CTL, 2 +#endif + + /* System reset handler */ + call reset_handler + + /* Infinite loop, if returned accidentally */ +1: j 1b + + .weak exit +exit: +1: j 1b + + .section .isr_vector, "ax" + .weak nmi_handler +nmi_handler: +1: j 1b + +#include "../vectors.h" diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/reset.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/reset.c new file mode 100644 index 00000000000..499110d52d8 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/reset.c @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2023-2024 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" +#include "hpm_interrupt.h" + + +extern void system_init(void); + +#ifndef MAIN_ENTRY +#define MAIN_ENTRY main +#endif +extern int MAIN_ENTRY(void); + +__attribute__((weak)) void _clean_up(void) +{ + /* clean up plic, it will help while debugging */ + disable_irq_from_intc(); + intc_m_set_threshold(0); + for (uint32_t irq = 0; irq < 128; irq++) { + intc_m_complete_irq(irq); + } + /* clear any bits left in plic enable register */ + for (uint32_t i = 0; i < 4; i++) { + *(volatile uint32_t *)(HPM_PLIC_BASE + HPM_PLIC_ENABLE_OFFSET + (i << 2)) = 0; + } +} + +__attribute__((weak)) void c_startup(void) +{ + uint32_t i, size; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __tdata_start__[], __tdata_end__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + extern uint8_t __data_load_addr__[], __tdata_load_addr__[]; + extern uint8_t __fast_load_addr__[], __noncacheable_init_load_addr__[]; + +#if defined(FLASH_XIP) || defined(FLASH_UF2) + extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; + size = __vector_ram_end__ - __vector_ram_start__; + for (i = 0; i < size; i++) { + *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); + } +#endif + + /* bss section */ + size = __bss_end__ - __bss_start__; + for (i = 0; i < size; i++) { + *(__bss_start__ + i) = 0; + } + + /* noncacheable bss section */ + size = __noncacheable_bss_end__ - __noncacheable_bss_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_bss_start__ + i) = 0; + } + + /* data section LMA: etext */ + size = __data_end__ - __data_start__; + for (i = 0; i < size; i++) { + *(__data_start__ + i) = *(__data_load_addr__ + i); + } + + /* ramfunc section LMA: etext + data length */ + size = __ramfunc_end__ - __ramfunc_start__; + for (i = 0; i < size; i++) { + *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i); + } + + /* tdata section LMA: etext + data length + ramfunc length */ + size = __tdata_end__ - __tdata_start__; + for (i = 0; i < size; i++) { + *(__tdata_start__ + i) = *(__tdata_load_addr__ + i); + } + + /* noncacheable init section LMA: etext + data length + ramfunc legnth + tdata length*/ + size = __noncacheable_init_end__ - __noncacheable_init_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); + } +} + +__attribute__((weak)) int main(void) +{ + while (1) { + ; + } +} + +__attribute__((weak)) void reset_handler(void) +{ + fencei(); + + /* Call platform specific hardware initialization */ + system_init(); + + /* Entry function */ + MAIN_ENTRY(); +} + +/* + * When compiling C++ code with static objects, the compiler inserts + * a call to __cxa_atexit() with __dso_handle as one of the arguments. + * The dummy versions of these symbols should be provided. + */ +__attribute__((weak)) void __cxa_atexit(void (*arg1)(void *), void *arg2, void *arg3) +{ + (void) arg1; + (void) arg2; + (void) arg3; +} + +#if (!defined(__SEGGER_RTL_VERSION) || defined(__riscv_xandes)) && !defined(__ICCRISCV__) +void *__dso_handle = (void *) &__dso_handle; +#endif + +__attribute__((weak)) void _init(void) +{ +} + + +#ifdef __ICCRISCV__ +int __low_level_init(void) +{ +#ifdef IAR_MANUAL_COPY /* Enable this code snippet if the .isr_vector and .vector_table need to be copied to RAM manually */ +#pragma section = ".isr_vector" +#pragma section = ".isr_vector_init" +#pragma section = ".vector_table" +#pragma section = ".vector_table_init" + /* Initialize section .isr_vector, section .vector_table */ + uint8_t *__isr_vector_ram_start = __section_begin(".isr_vector"); + uint32_t __isr_vector_ram_size = __section_size(".isr_vector"); + uint8_t *__isr_vector_rom_start = __section_begin(".isr_vector_init"); + + for (uint32_t i = 0; i < __isr_vector_ram_size; i++) { + __isr_vector_ram_start[i] = __isr_vector_rom_start[i]; + } + + uint8_t *__vector_table_ram_start = __section_begin(".vector_table"); + uint32_t __vector_table_ram_size = __section_size(".vector_table"); + uint8_t *__vector_rom_start = __section_begin(".vector_table_init"); + + for (uint32_t i = 0; i < __vector_table_ram_size; i++) { + __vector_table_ram_start[i] = __vector_rom_start[i]; + } +#endif + + return 1; +} +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/trap.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/trap.c new file mode 100644 index 00000000000..539c77c4804 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/trap.c @@ -0,0 +1,282 @@ +/* + * Copyright (c) 2023-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_soc.h" + +#ifdef __ICCRISCV__ +#pragma language = extended +#endif + +/********************** MCAUSE exception types **************************************/ +#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) /* !< Instruction Address misaligned */ +#define MCAUSE_INSTR_ACCESS_FAULT (1U) /* !< Instruction access fault */ +#define MCAUSE_ILLEGAL_INSTR (2U) /* !< Illegal instruction */ +#define MCAUSE_BREAKPOINT (3U) /* !< Breakpoint */ +#define MCAUSE_LOAD_ADDR_MISALIGNED (4U) /* !< Load address misaligned */ +#define MCAUSE_LOAD_ACCESS_FAULT (5U) /* !< Load access fault */ +#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U) /* !< Store/AMO address misaligned */ +#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U) /* !< Store/AMO access fault */ +#define MCAUSE_ECALL_FROM_USER_MODE (8U) /* !< Environment call from User mode */ +#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U) /* !< Environment call from Supervisor mode */ +#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U) /* !< Environment call from machine mode */ +#define MCAUSE_INSTR_PAGE_FAULT (12U) /* !< Instruction page fault */ +#define MCAUSE_LOAD_PAGE_FAULT (13) /* !< Load page fault */ +#define MCAUSE_STORE_AMO_PAGE_FAULT (15U) /* !< Store/AMO page fault */ + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +__attribute__((weak)) void mchtmr_isr(void) +{ +} + +__attribute__((weak)) void swi_isr(void) +{ +} + +__attribute__((weak)) void syscall_handler(long n, long a0, long a1, long a2, long a3) +{ + (void) n; + (void) a0; + (void) a1; + (void) a2; + (void) a3; +} + +__attribute__((weak)) long exception_handler(long cause, long epc) +{ + switch (cause) { + case MCAUSE_INSTR_ADDR_MISALIGNED: + break; + case MCAUSE_INSTR_ACCESS_FAULT: + break; + case MCAUSE_ILLEGAL_INSTR: + break; + case MCAUSE_BREAKPOINT: + break; + case MCAUSE_LOAD_ADDR_MISALIGNED: + break; + case MCAUSE_LOAD_ACCESS_FAULT: + break; + case MCAUSE_STORE_AMO_ADDR_MISALIGNED: + break; + case MCAUSE_STORE_AMO_ACCESS_FAULT: + break; + case MCAUSE_ECALL_FROM_USER_MODE: + break; + case MCAUSE_ECALL_FROM_SUPERVISOR_MODE: + break; + case MCAUSE_ECALL_FROM_MACHINE_MODE: + break; + case MCAUSE_INSTR_PAGE_FAULT: + break; + case MCAUSE_LOAD_PAGE_FAULT: + break; + case MCAUSE_STORE_AMO_PAGE_FAULT: + break; + default: + break; + } + /* Unhandled Trap */ + return epc; +} + +__attribute__((weak)) long exception_s_handler(long cause, long epc) +{ + (void) cause; + return epc; +} + +__attribute__((weak)) void swi_s_isr(void) +{ +} + +__attribute__((weak)) void mchtmr_s_isr(void) +{ +} + +#if !defined(CONFIG_FREERTOS) && !defined(CONFIG_UCOS_III) && !defined(CONFIG_THREADX) && !defined(CONFIG_RTTHREAD) +HPM_ATTR_MACHINE_INTERRUPT void irq_handler_trap(void); +#define IRQ_HANDLER_TRAP_AS_ISR 1 +#else +void irq_handler_trap(void) __attribute__ ((section(".isr_vector"))); +#endif + +#if defined(__ICCRISCV__) && (IRQ_HANDLER_TRAP_AS_ISR == 1) +extern int __vector_table[]; +HPM_ATTR_MACHINE_INTERRUPT +#endif +void irq_handler_trap(void) +{ + long mcause = read_csr(CSR_MCAUSE); + long mepc = read_csr(CSR_MEPC); + long mstatus = read_csr(CSR_MSTATUS); +#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH + long mxstatus = read_csr(CSR_MXSTATUS); +#endif +#ifdef __riscv_dsp + int ucode = read_csr(CSR_UCODE); +#endif +#ifdef __riscv_flen + int fcsr = read_fcsr(); +#endif + + /* clobbers list for ecall */ +#ifdef __riscv_32e + __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3"); +#else + __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3"); +#endif + + /* Do your trap handling */ + if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_TIMER)) { + /* Machine timer interrupt */ + mchtmr_isr(); + } +#ifdef USE_NONVECTOR_MODE + else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_EXT)) { + + typedef void(*isr_func_t)(void); + + /* Machine-level interrupt from PLIC */ + uint32_t irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); + if (irq_index) { + /* Workaround: irq number returned by __plic_claim_irq might be 0, which is caused by plic. So skip invalid irq_index as a workaround */ +#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) + enable_global_irq(CSR_MSTATUS_MIE_MASK); +#endif + ((isr_func_t)__vector_table[irq_index])(); + __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index); + } + + } +#endif + + else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_SOFT)) { + /* Machine SWI interrupt */ + intc_m_claim_swi(); + swi_isr(); + intc_m_complete_swi(); + } else if (!(mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == MCAUSE_ECALL_FROM_MACHINE_MODE)) { + /* Machine Syscal call */ + __asm volatile( + "mv a4, a3\n" + "mv a3, a2\n" + "mv a2, a1\n" + "mv a1, a0\n" + #ifdef __riscv_32e + "mv a0, t0\n" + #else + "mv a0, a7\n" + #endif + "jalr %0\n" + : :"r"(syscall_handler) : "a4" + ); + mepc += 4; + } else { + mepc = exception_handler(mcause, mepc); + } + + /* Restore CSR */ + write_csr(CSR_MSTATUS, mstatus); + write_csr(CSR_MEPC, mepc); +#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH + write_csr(CSR_MXSTATUS, mxstatus); +#endif +#ifdef __riscv_dsp + write_csr(CSR_UCODE, ucode); +#endif +#ifdef __riscv_flen + write_fcsr(fcsr); +#endif +} + + +#if !defined(CONFIG_FREERTOS) && !defined(CONFIG_UCOS_III) && !defined(CONFIG_THREADX) +HPM_ATTR_SUPERVISOR_INTERRUPT void irq_handler_s_trap(void); +#define IRQ_HANDLER_TRAP_AS_ISR 1 +#else +void irq_handler_s_trap(void) __attribute__ ((section(".isr_s_vector"))); +#endif + +#if defined(__ICCRISCV__) && (IRQ_HANDLER_TRAP_AS_ISR == 1) +extern int __vector_s_table[]; +HPM_ATTR_SUPERVISOR_INTERRUPT +#endif +void irq_handler_s_trap(void) +{ + long scause = read_csr(CSR_SCAUSE); + long sepc = read_csr(CSR_SEPC); + long sstatus = read_csr(CSR_SSTATUS); + + /* clobbers list for ecall */ +#ifdef __riscv_32e + __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3"); +#else + __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3"); +#endif + + /* Do your trap handling */ + if ((scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == IRQ_S_TIMER)) { + /* Machine timer interrupt */ + mchtmr_s_isr(); + } +#ifdef USE_NONVECTOR_MODE + else if ((scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == IRQ_S_EXT)) { + + typedef void(*isr_func_t)(void); + + /* Machine-level interrupt from PLIC */ + uint32_t irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_S_MODE); +#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) + enable_s_global_irq(CSR_SSTATUS_SIE_MASK); +#endif + ((isr_func_t)__vector_s_table[irq_index])(); + __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_S_MODE, irq_index); + + } +#endif + + else if ((scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == IRQ_S_SOFT)) { + /* Machine SWI interrupt */ + intc_m_claim_swi(); + swi_s_isr(); + intc_s_complete_swi(); + } else if (!(scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == MCAUSE_ECALL_FROM_SUPERVISOR_MODE)) { + /* Machine Syscal call */ + __asm volatile( + "mv a4, a3\n" + "mv a3, a2\n" + "mv a2, a1\n" + "mv a1, a0\n" + #ifdef __riscv_32e + "mv a0, t0\n" + #else + "mv a0, a7\n" + #endif + "jalr %0\n" + : :"r"(syscall_handler) : "a4" + ); + sepc += 4; + } else { + sepc = exception_s_handler(scause, sepc); + } + + /* Restore CSR */ + write_csr(CSR_SSTATUS, sstatus); + write_csr(CSR_SEPC, sepc); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/vectors.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/vectors.h new file mode 100644 index 00000000000..4df47e4fae0 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/vectors.h @@ -0,0 +1,807 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifdef __IAR_SYSTEMS_ASM__ + +IRQ_HANDLER macro + dc32 default_isr_\1 + endm + +IRQ_DEFAULT_HANDLER macro + PUBWEAK default_isr_\1 +default_isr_\1 + j default_irq_handler + endm + + SECTION `.isr_vector`:CODE:ROOT(9) + PUBWEAK default_irq_handler +default_irq_handler + j default_irq_handler + IRQ_DEFAULT_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_DEFAULT_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_DEFAULT_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_DEFAULT_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_DEFAULT_HANDLER 5 /* GPIO0_E IRQ handler */ + IRQ_DEFAULT_HANDLER 6 /* GPIO0_F IRQ handler */ + IRQ_DEFAULT_HANDLER 7 /* GPIO0_X IRQ handler */ + IRQ_DEFAULT_HANDLER 8 /* GPIO0_Y IRQ handler */ + IRQ_DEFAULT_HANDLER 9 /* GPIO0_Z IRQ handler */ + IRQ_DEFAULT_HANDLER 10 /* MCAN0 IRQ handler */ + IRQ_DEFAULT_HANDLER 11 /* MCAN1 IRQ handler */ + IRQ_DEFAULT_HANDLER 12 /* MCAN2 IRQ handler */ + IRQ_DEFAULT_HANDLER 13 /* MCAN3 IRQ handler */ + IRQ_DEFAULT_HANDLER 14 /* MCAN4 IRQ handler */ + IRQ_DEFAULT_HANDLER 15 /* MCAN5 IRQ handler */ + IRQ_DEFAULT_HANDLER 16 /* MCAN6 IRQ handler */ + IRQ_DEFAULT_HANDLER 17 /* MCAN7 IRQ handler */ + IRQ_DEFAULT_HANDLER 18 /* PTPC IRQ handler */ + IRQ_DEFAULT_HANDLER 19 /* Reserved */ + IRQ_DEFAULT_HANDLER 20 /* Reserved */ + IRQ_DEFAULT_HANDLER 21 /* Reserved */ + IRQ_DEFAULT_HANDLER 22 /* Reserved */ + IRQ_DEFAULT_HANDLER 23 /* Reserved */ + IRQ_DEFAULT_HANDLER 24 /* Reserved */ + IRQ_DEFAULT_HANDLER 25 /* Reserved */ + IRQ_DEFAULT_HANDLER 26 /* Reserved */ + IRQ_DEFAULT_HANDLER 27 /* UART0 IRQ handler */ + IRQ_DEFAULT_HANDLER 28 /* UART1 IRQ handler */ + IRQ_DEFAULT_HANDLER 29 /* UART2 IRQ handler */ + IRQ_DEFAULT_HANDLER 30 /* UART3 IRQ handler */ + IRQ_DEFAULT_HANDLER 31 /* UART4 IRQ handler */ + IRQ_DEFAULT_HANDLER 32 /* UART5 IRQ handler */ + IRQ_DEFAULT_HANDLER 33 /* UART6 IRQ handler */ + IRQ_DEFAULT_HANDLER 34 /* UART7 IRQ handler */ + IRQ_DEFAULT_HANDLER 35 /* I2C0 IRQ handler */ + IRQ_DEFAULT_HANDLER 36 /* I2C1 IRQ handler */ + IRQ_DEFAULT_HANDLER 37 /* I2C2 IRQ handler */ + IRQ_DEFAULT_HANDLER 38 /* I2C3 IRQ handler */ + IRQ_DEFAULT_HANDLER 39 /* SPI0 IRQ handler */ + IRQ_DEFAULT_HANDLER 40 /* SPI1 IRQ handler */ + IRQ_DEFAULT_HANDLER 41 /* SPI2 IRQ handler */ + IRQ_DEFAULT_HANDLER 42 /* SPI3 IRQ handler */ + IRQ_DEFAULT_HANDLER 43 /* GPTMR0 IRQ handler */ + IRQ_DEFAULT_HANDLER 44 /* GPTMR1 IRQ handler */ + IRQ_DEFAULT_HANDLER 45 /* GPTMR2 IRQ handler */ + IRQ_DEFAULT_HANDLER 46 /* GPTMR3 IRQ handler */ + IRQ_DEFAULT_HANDLER 47 /* GPTMR4 IRQ handler */ + IRQ_DEFAULT_HANDLER 48 /* GPTMR5 IRQ handler */ + IRQ_DEFAULT_HANDLER 49 /* GPTMR6 IRQ handler */ + IRQ_DEFAULT_HANDLER 50 /* GPTMR7 IRQ handler */ + IRQ_DEFAULT_HANDLER 51 /* EWDG0 IRQ handler */ + IRQ_DEFAULT_HANDLER 52 /* EWDG1 IRQ handler */ + IRQ_DEFAULT_HANDLER 53 /* MBX0A IRQ handler */ + IRQ_DEFAULT_HANDLER 54 /* MBX0B IRQ handler */ + IRQ_DEFAULT_HANDLER 55 /* MBX1A IRQ handler */ + IRQ_DEFAULT_HANDLER 56 /* MBX1B IRQ handler */ + IRQ_DEFAULT_HANDLER 57 /* RNG IRQ handler */ + IRQ_DEFAULT_HANDLER 58 /* HDMA IRQ handler */ + IRQ_DEFAULT_HANDLER 59 /* ADC0 IRQ handler */ + IRQ_DEFAULT_HANDLER 60 /* ADC1 IRQ handler */ + IRQ_DEFAULT_HANDLER 61 /* SDM IRQ handler */ + IRQ_DEFAULT_HANDLER 62 /* OPAMP IRQ handler */ + IRQ_DEFAULT_HANDLER 63 /* I2S0 IRQ handler */ + IRQ_DEFAULT_HANDLER 64 /* I2S1 IRQ handler */ + IRQ_DEFAULT_HANDLER 65 /* I2S2 IRQ handler */ + IRQ_DEFAULT_HANDLER 66 /* I2S3 IRQ handler */ + IRQ_DEFAULT_HANDLER 67 /* DAO IRQ handler */ + IRQ_DEFAULT_HANDLER 68 /* PDM IRQ handler */ + IRQ_DEFAULT_HANDLER 69 /* SMIX_DMA IRQ handler */ + IRQ_DEFAULT_HANDLER 70 /* SMIX_ASRC IRQ handler */ + IRQ_DEFAULT_HANDLER 71 /* CAM0 IRQ handler */ + IRQ_DEFAULT_HANDLER 72 /* CAM1 IRQ handler */ + IRQ_DEFAULT_HANDLER 73 /* LCDC IRQ handler */ + IRQ_DEFAULT_HANDLER 74 /* LCDC1 IRQ handler */ + IRQ_DEFAULT_HANDLER 75 /* PDMA IRQ handler */ + IRQ_DEFAULT_HANDLER 76 /* JPEG IRQ handler */ + IRQ_DEFAULT_HANDLER 77 /* GWCK0_FUNC IRQ handler */ + IRQ_DEFAULT_HANDLER 78 /* GWCK0_ERR IRQ handler */ + IRQ_DEFAULT_HANDLER 79 /* GWCK1_FUNC IRQ handler */ + IRQ_DEFAULT_HANDLER 80 /* GWCK1_ERR IRQ handler */ + IRQ_DEFAULT_HANDLER 81 /* MIPI_DSI0 IRQ handler */ + IRQ_DEFAULT_HANDLER 82 /* MIPI_DSI1 IRQ handler */ + IRQ_DEFAULT_HANDLER 83 /* MIPI_CSI0 IRQ handler */ + IRQ_DEFAULT_HANDLER 84 /* MIPI_CSI0_AP IRQ handler */ + IRQ_DEFAULT_HANDLER 85 /* MIPI_CSI0_DIAG IRQ handler */ + IRQ_DEFAULT_HANDLER 86 /* MIPI_CSI1_AP IRQ handler */ + IRQ_DEFAULT_HANDLER 87 /* MIPI_CSI1_DIAG IRQ handler */ + IRQ_DEFAULT_HANDLER 88 /* MIPI_CSI1 IRQ handler */ + IRQ_DEFAULT_HANDLER 89 /* LCB0 IRQ handler */ + IRQ_DEFAULT_HANDLER 90 /* LCB1 IRQ handler */ + IRQ_DEFAULT_HANDLER 91 /* GPU IRQ handler */ + IRQ_DEFAULT_HANDLER 92 /* ENET0 IRQ handler */ + IRQ_DEFAULT_HANDLER 93 /* NTMR0 IRQ handler */ + IRQ_DEFAULT_HANDLER 94 /* USB0 IRQ handler */ + IRQ_DEFAULT_HANDLER 95 /* SDXC0 IRQ handler */ + IRQ_DEFAULT_HANDLER 96 /* SDXC1 IRQ handler */ + IRQ_DEFAULT_HANDLER 97 /* SDP IRQ handler */ + IRQ_DEFAULT_HANDLER 98 /* XPI0 IRQ handler */ + IRQ_DEFAULT_HANDLER 99 /* XDMA IRQ handler */ + IRQ_DEFAULT_HANDLER 100 /* DDR IRQ handler */ + IRQ_DEFAULT_HANDLER 101 /* FFA IRQ handler */ + IRQ_DEFAULT_HANDLER 102 /* PSEC IRQ handler */ + IRQ_DEFAULT_HANDLER 103 /* TSNS IRQ handler */ + IRQ_DEFAULT_HANDLER 104 /* VAD IRQ handler */ + IRQ_DEFAULT_HANDLER 105 /* PGPIO IRQ handler */ + IRQ_DEFAULT_HANDLER 106 /* PWDG IRQ handler */ + IRQ_DEFAULT_HANDLER 107 /* PTMR IRQ handler */ + IRQ_DEFAULT_HANDLER 108 /* PUART IRQ handler */ + IRQ_DEFAULT_HANDLER 109 /* FUSE IRQ handler */ + IRQ_DEFAULT_HANDLER 110 /* SECMON IRQ handler */ + IRQ_DEFAULT_HANDLER 111 /* RTC IRQ handler */ + IRQ_DEFAULT_HANDLER 112 /* BGPIO IRQ handler */ + IRQ_DEFAULT_HANDLER 113 /* BVIO IRQ handler */ + IRQ_DEFAULT_HANDLER 114 /* BROWNOUT IRQ handler */ + IRQ_DEFAULT_HANDLER 115 /* SYSCTL IRQ handler */ + IRQ_DEFAULT_HANDLER 116 /* DEBUG0 IRQ handler */ + IRQ_DEFAULT_HANDLER 117 /* DEBUG1 IRQ handler */ + + EXTERN irq_handler_trap + SECTION `.vector_table`:CODE:ROOT(9) + PUBLIC __vector_table + DATA + +__vector_table + dc32 irq_handler_trap + IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_HANDLER 5 /* GPIO0_E IRQ handler */ + IRQ_HANDLER 6 /* GPIO0_F IRQ handler */ + IRQ_HANDLER 7 /* GPIO0_X IRQ handler */ + IRQ_HANDLER 8 /* GPIO0_Y IRQ handler */ + IRQ_HANDLER 9 /* GPIO0_Z IRQ handler */ + IRQ_HANDLER 10 /* MCAN0 IRQ handler */ + IRQ_HANDLER 11 /* MCAN1 IRQ handler */ + IRQ_HANDLER 12 /* MCAN2 IRQ handler */ + IRQ_HANDLER 13 /* MCAN3 IRQ handler */ + IRQ_HANDLER 14 /* MCAN4 IRQ handler */ + IRQ_HANDLER 15 /* MCAN5 IRQ handler */ + IRQ_HANDLER 16 /* MCAN6 IRQ handler */ + IRQ_HANDLER 17 /* MCAN7 IRQ handler */ + IRQ_HANDLER 18 /* PTPC IRQ handler */ + IRQ_HANDLER 19 /* Reserved */ + IRQ_HANDLER 20 /* Reserved */ + IRQ_HANDLER 21 /* Reserved */ + IRQ_HANDLER 22 /* Reserved */ + IRQ_HANDLER 23 /* Reserved */ + IRQ_HANDLER 24 /* Reserved */ + IRQ_HANDLER 25 /* Reserved */ + IRQ_HANDLER 26 /* Reserved */ + IRQ_HANDLER 27 /* UART0 IRQ handler */ + IRQ_HANDLER 28 /* UART1 IRQ handler */ + IRQ_HANDLER 29 /* UART2 IRQ handler */ + IRQ_HANDLER 30 /* UART3 IRQ handler */ + IRQ_HANDLER 31 /* UART4 IRQ handler */ + IRQ_HANDLER 32 /* UART5 IRQ handler */ + IRQ_HANDLER 33 /* UART6 IRQ handler */ + IRQ_HANDLER 34 /* UART7 IRQ handler */ + IRQ_HANDLER 35 /* I2C0 IRQ handler */ + IRQ_HANDLER 36 /* I2C1 IRQ handler */ + IRQ_HANDLER 37 /* I2C2 IRQ handler */ + IRQ_HANDLER 38 /* I2C3 IRQ handler */ + IRQ_HANDLER 39 /* SPI0 IRQ handler */ + IRQ_HANDLER 40 /* SPI1 IRQ handler */ + IRQ_HANDLER 41 /* SPI2 IRQ handler */ + IRQ_HANDLER 42 /* SPI3 IRQ handler */ + IRQ_HANDLER 43 /* GPTMR0 IRQ handler */ + IRQ_HANDLER 44 /* GPTMR1 IRQ handler */ + IRQ_HANDLER 45 /* GPTMR2 IRQ handler */ + IRQ_HANDLER 46 /* GPTMR3 IRQ handler */ + IRQ_HANDLER 47 /* GPTMR4 IRQ handler */ + IRQ_HANDLER 48 /* GPTMR5 IRQ handler */ + IRQ_HANDLER 49 /* GPTMR6 IRQ handler */ + IRQ_HANDLER 50 /* GPTMR7 IRQ handler */ + IRQ_HANDLER 51 /* EWDG0 IRQ handler */ + IRQ_HANDLER 52 /* EWDG1 IRQ handler */ + IRQ_HANDLER 53 /* MBX0A IRQ handler */ + IRQ_HANDLER 54 /* MBX0B IRQ handler */ + IRQ_HANDLER 55 /* MBX1A IRQ handler */ + IRQ_HANDLER 56 /* MBX1B IRQ handler */ + IRQ_HANDLER 57 /* RNG IRQ handler */ + IRQ_HANDLER 58 /* HDMA IRQ handler */ + IRQ_HANDLER 59 /* ADC0 IRQ handler */ + IRQ_HANDLER 60 /* ADC1 IRQ handler */ + IRQ_HANDLER 61 /* SDM IRQ handler */ + IRQ_HANDLER 62 /* OPAMP IRQ handler */ + IRQ_HANDLER 63 /* I2S0 IRQ handler */ + IRQ_HANDLER 64 /* I2S1 IRQ handler */ + IRQ_HANDLER 65 /* I2S2 IRQ handler */ + IRQ_HANDLER 66 /* I2S3 IRQ handler */ + IRQ_HANDLER 67 /* DAO IRQ handler */ + IRQ_HANDLER 68 /* PDM IRQ handler */ + IRQ_HANDLER 69 /* SMIX_DMA IRQ handler */ + IRQ_HANDLER 70 /* SMIX_ASRC IRQ handler */ + IRQ_HANDLER 71 /* CAM0 IRQ handler */ + IRQ_HANDLER 72 /* CAM1 IRQ handler */ + IRQ_HANDLER 73 /* LCDC IRQ handler */ + IRQ_HANDLER 74 /* LCDC1 IRQ handler */ + IRQ_HANDLER 75 /* PDMA IRQ handler */ + IRQ_HANDLER 76 /* JPEG IRQ handler */ + IRQ_HANDLER 77 /* GWCK0_FUNC IRQ handler */ + IRQ_HANDLER 78 /* GWCK0_ERR IRQ handler */ + IRQ_HANDLER 79 /* GWCK1_FUNC IRQ handler */ + IRQ_HANDLER 80 /* GWCK1_ERR IRQ handler */ + IRQ_HANDLER 81 /* MIPI_DSI0 IRQ handler */ + IRQ_HANDLER 82 /* MIPI_DSI1 IRQ handler */ + IRQ_HANDLER 83 /* MIPI_CSI0 IRQ handler */ + IRQ_HANDLER 84 /* MIPI_CSI0_AP IRQ handler */ + IRQ_HANDLER 85 /* MIPI_CSI0_DIAG IRQ handler */ + IRQ_HANDLER 86 /* MIPI_CSI1_AP IRQ handler */ + IRQ_HANDLER 87 /* MIPI_CSI1_DIAG IRQ handler */ + IRQ_HANDLER 88 /* MIPI_CSI1 IRQ handler */ + IRQ_HANDLER 89 /* LCB0 IRQ handler */ + IRQ_HANDLER 90 /* LCB1 IRQ handler */ + IRQ_HANDLER 91 /* GPU IRQ handler */ + IRQ_HANDLER 92 /* ENET0 IRQ handler */ + IRQ_HANDLER 93 /* NTMR0 IRQ handler */ + IRQ_HANDLER 94 /* USB0 IRQ handler */ + IRQ_HANDLER 95 /* SDXC0 IRQ handler */ + IRQ_HANDLER 96 /* SDXC1 IRQ handler */ + IRQ_HANDLER 97 /* SDP IRQ handler */ + IRQ_HANDLER 98 /* XPI0 IRQ handler */ + IRQ_HANDLER 99 /* XDMA IRQ handler */ + IRQ_HANDLER 100 /* DDR IRQ handler */ + IRQ_HANDLER 101 /* FFA IRQ handler */ + IRQ_HANDLER 102 /* PSEC IRQ handler */ + IRQ_HANDLER 103 /* TSNS IRQ handler */ + IRQ_HANDLER 104 /* VAD IRQ handler */ + IRQ_HANDLER 105 /* PGPIO IRQ handler */ + IRQ_HANDLER 106 /* PWDG IRQ handler */ + IRQ_HANDLER 107 /* PTMR IRQ handler */ + IRQ_HANDLER 108 /* PUART IRQ handler */ + IRQ_HANDLER 109 /* FUSE IRQ handler */ + IRQ_HANDLER 110 /* SECMON IRQ handler */ + IRQ_HANDLER 111 /* RTC IRQ handler */ + IRQ_HANDLER 112 /* BGPIO IRQ handler */ + IRQ_HANDLER 113 /* BVIO IRQ handler */ + IRQ_HANDLER 114 /* BROWNOUT IRQ handler */ + IRQ_HANDLER 115 /* SYSCTL IRQ handler */ + IRQ_HANDLER 116 /* DEBUG0 IRQ handler */ + IRQ_HANDLER 117 /* DEBUG1 IRQ handler */ + +#else + +.global default_irq_handler +.weak default_irq_handler +.align 2 +default_irq_handler: +1: j 1b + +.macro IRQ_HANDLER irq + .weak default_isr_\irq + .set default_isr_\irq, default_irq_handler + .long default_isr_\irq +.endm + +.section .vector_table, "a" +.global __vector_table +.align 9 + +__vector_table: + .weak default_isr_trap + .set default_isr_trap, irq_handler_trap + .long default_isr_trap + IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_HANDLER 5 /* GPIO0_E IRQ handler */ + IRQ_HANDLER 6 /* GPIO0_F IRQ handler */ + IRQ_HANDLER 7 /* GPIO0_X IRQ handler */ + IRQ_HANDLER 8 /* GPIO0_Y IRQ handler */ + IRQ_HANDLER 9 /* GPIO0_Z IRQ handler */ + IRQ_HANDLER 10 /* MCAN0 IRQ handler */ + IRQ_HANDLER 11 /* MCAN1 IRQ handler */ + IRQ_HANDLER 12 /* MCAN2 IRQ handler */ + IRQ_HANDLER 13 /* MCAN3 IRQ handler */ + IRQ_HANDLER 14 /* MCAN4 IRQ handler */ + IRQ_HANDLER 15 /* MCAN5 IRQ handler */ + IRQ_HANDLER 16 /* MCAN6 IRQ handler */ + IRQ_HANDLER 17 /* MCAN7 IRQ handler */ + IRQ_HANDLER 18 /* PTPC IRQ handler */ + IRQ_HANDLER 19 /* Reserved */ + IRQ_HANDLER 20 /* Reserved */ + IRQ_HANDLER 21 /* Reserved */ + IRQ_HANDLER 22 /* Reserved */ + IRQ_HANDLER 23 /* Reserved */ + IRQ_HANDLER 24 /* Reserved */ + IRQ_HANDLER 25 /* Reserved */ + IRQ_HANDLER 26 /* Reserved */ + IRQ_HANDLER 27 /* UART0 IRQ handler */ + IRQ_HANDLER 28 /* UART1 IRQ handler */ + IRQ_HANDLER 29 /* UART2 IRQ handler */ + IRQ_HANDLER 30 /* UART3 IRQ handler */ + IRQ_HANDLER 31 /* UART4 IRQ handler */ + IRQ_HANDLER 32 /* UART5 IRQ handler */ + IRQ_HANDLER 33 /* UART6 IRQ handler */ + IRQ_HANDLER 34 /* UART7 IRQ handler */ + IRQ_HANDLER 35 /* I2C0 IRQ handler */ + IRQ_HANDLER 36 /* I2C1 IRQ handler */ + IRQ_HANDLER 37 /* I2C2 IRQ handler */ + IRQ_HANDLER 38 /* I2C3 IRQ handler */ + IRQ_HANDLER 39 /* SPI0 IRQ handler */ + IRQ_HANDLER 40 /* SPI1 IRQ handler */ + IRQ_HANDLER 41 /* SPI2 IRQ handler */ + IRQ_HANDLER 42 /* SPI3 IRQ handler */ + IRQ_HANDLER 43 /* GPTMR0 IRQ handler */ + IRQ_HANDLER 44 /* GPTMR1 IRQ handler */ + IRQ_HANDLER 45 /* GPTMR2 IRQ handler */ + IRQ_HANDLER 46 /* GPTMR3 IRQ handler */ + IRQ_HANDLER 47 /* GPTMR4 IRQ handler */ + IRQ_HANDLER 48 /* GPTMR5 IRQ handler */ + IRQ_HANDLER 49 /* GPTMR6 IRQ handler */ + IRQ_HANDLER 50 /* GPTMR7 IRQ handler */ + IRQ_HANDLER 51 /* EWDG0 IRQ handler */ + IRQ_HANDLER 52 /* EWDG1 IRQ handler */ + IRQ_HANDLER 53 /* MBX0A IRQ handler */ + IRQ_HANDLER 54 /* MBX0B IRQ handler */ + IRQ_HANDLER 55 /* MBX1A IRQ handler */ + IRQ_HANDLER 56 /* MBX1B IRQ handler */ + IRQ_HANDLER 57 /* RNG IRQ handler */ + IRQ_HANDLER 58 /* HDMA IRQ handler */ + IRQ_HANDLER 59 /* ADC0 IRQ handler */ + IRQ_HANDLER 60 /* ADC1 IRQ handler */ + IRQ_HANDLER 61 /* SDM IRQ handler */ + IRQ_HANDLER 62 /* OPAMP IRQ handler */ + IRQ_HANDLER 63 /* I2S0 IRQ handler */ + IRQ_HANDLER 64 /* I2S1 IRQ handler */ + IRQ_HANDLER 65 /* I2S2 IRQ handler */ + IRQ_HANDLER 66 /* I2S3 IRQ handler */ + IRQ_HANDLER 67 /* DAO IRQ handler */ + IRQ_HANDLER 68 /* PDM IRQ handler */ + IRQ_HANDLER 69 /* SMIX_DMA IRQ handler */ + IRQ_HANDLER 70 /* SMIX_ASRC IRQ handler */ + IRQ_HANDLER 71 /* CAM0 IRQ handler */ + IRQ_HANDLER 72 /* CAM1 IRQ handler */ + IRQ_HANDLER 73 /* LCDC IRQ handler */ + IRQ_HANDLER 74 /* LCDC1 IRQ handler */ + IRQ_HANDLER 75 /* PDMA IRQ handler */ + IRQ_HANDLER 76 /* JPEG IRQ handler */ + IRQ_HANDLER 77 /* GWCK0_FUNC IRQ handler */ + IRQ_HANDLER 78 /* GWCK0_ERR IRQ handler */ + IRQ_HANDLER 79 /* GWCK1_FUNC IRQ handler */ + IRQ_HANDLER 80 /* GWCK1_ERR IRQ handler */ + IRQ_HANDLER 81 /* MIPI_DSI0 IRQ handler */ + IRQ_HANDLER 82 /* MIPI_DSI1 IRQ handler */ + IRQ_HANDLER 83 /* MIPI_CSI0 IRQ handler */ + IRQ_HANDLER 84 /* MIPI_CSI0_AP IRQ handler */ + IRQ_HANDLER 85 /* MIPI_CSI0_DIAG IRQ handler */ + IRQ_HANDLER 86 /* MIPI_CSI1_AP IRQ handler */ + IRQ_HANDLER 87 /* MIPI_CSI1_DIAG IRQ handler */ + IRQ_HANDLER 88 /* MIPI_CSI1 IRQ handler */ + IRQ_HANDLER 89 /* LCB0 IRQ handler */ + IRQ_HANDLER 90 /* LCB1 IRQ handler */ + IRQ_HANDLER 91 /* GPU IRQ handler */ + IRQ_HANDLER 92 /* ENET0 IRQ handler */ + IRQ_HANDLER 93 /* NTMR0 IRQ handler */ + IRQ_HANDLER 94 /* USB0 IRQ handler */ + IRQ_HANDLER 95 /* SDXC0 IRQ handler */ + IRQ_HANDLER 96 /* SDXC1 IRQ handler */ + IRQ_HANDLER 97 /* SDP IRQ handler */ + IRQ_HANDLER 98 /* XPI0 IRQ handler */ + IRQ_HANDLER 99 /* XDMA IRQ handler */ + IRQ_HANDLER 100 /* DDR IRQ handler */ + IRQ_HANDLER 101 /* FFA IRQ handler */ + IRQ_HANDLER 102 /* PSEC IRQ handler */ + IRQ_HANDLER 103 /* TSNS IRQ handler */ + IRQ_HANDLER 104 /* VAD IRQ handler */ + IRQ_HANDLER 105 /* PGPIO IRQ handler */ + IRQ_HANDLER 106 /* PWDG IRQ handler */ + IRQ_HANDLER 107 /* PTMR IRQ handler */ + IRQ_HANDLER 108 /* PUART IRQ handler */ + IRQ_HANDLER 109 /* FUSE IRQ handler */ + IRQ_HANDLER 110 /* SECMON IRQ handler */ + IRQ_HANDLER 111 /* RTC IRQ handler */ + IRQ_HANDLER 112 /* BGPIO IRQ handler */ + IRQ_HANDLER 113 /* BVIO IRQ handler */ + IRQ_HANDLER 114 /* BROWNOUT IRQ handler */ + IRQ_HANDLER 115 /* SYSCTL IRQ handler */ + IRQ_HANDLER 116 /* DEBUG0 IRQ handler */ + IRQ_HANDLER 117 /* DEBUG1 IRQ handler */ + +#endif + +#ifdef __IAR_SYSTEMS_ASM__ + +IRQ_S_HANDLER macro + dc32 default_isr_s_\1 + endm + +IRQ_DEFAULT_S_HANDLER macro + PUBWEAK default_isr_s_\1 +default_isr_s_\1 + j default_irq_s_handler + endm + + SECTION `.isr_s_vector`:CODE:ROOT(9) + PUBWEAK default_irq_s_handler +default_irq_s_handler + j default_irq_s_handler + IRQ_DEFAULT_S_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_DEFAULT_S_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_DEFAULT_S_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_DEFAULT_S_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_DEFAULT_S_HANDLER 5 /* GPIO0_E IRQ handler */ + IRQ_DEFAULT_S_HANDLER 6 /* GPIO0_F IRQ handler */ + IRQ_DEFAULT_S_HANDLER 7 /* GPIO0_X IRQ handler */ + IRQ_DEFAULT_S_HANDLER 8 /* GPIO0_Y IRQ handler */ + IRQ_DEFAULT_S_HANDLER 9 /* GPIO0_Z IRQ handler */ + IRQ_DEFAULT_S_HANDLER 10 /* MCAN0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 11 /* MCAN1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 12 /* MCAN2 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 13 /* MCAN3 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 14 /* MCAN4 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 15 /* MCAN5 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 16 /* MCAN6 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 17 /* MCAN7 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 18 /* PTPC IRQ handler */ + IRQ_DEFAULT_S_HANDLER 19 /* Reserved */ + IRQ_DEFAULT_S_HANDLER 20 /* Reserved */ + IRQ_DEFAULT_S_HANDLER 21 /* Reserved */ + IRQ_DEFAULT_S_HANDLER 22 /* Reserved */ + IRQ_DEFAULT_S_HANDLER 23 /* Reserved */ + IRQ_DEFAULT_S_HANDLER 24 /* Reserved */ + IRQ_DEFAULT_S_HANDLER 25 /* Reserved */ + IRQ_DEFAULT_S_HANDLER 26 /* Reserved */ + IRQ_DEFAULT_S_HANDLER 27 /* UART0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 28 /* UART1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 29 /* UART2 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 30 /* UART3 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 31 /* UART4 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 32 /* UART5 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 33 /* UART6 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 34 /* UART7 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 35 /* I2C0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 36 /* I2C1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 37 /* I2C2 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 38 /* I2C3 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 39 /* SPI0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 40 /* SPI1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 41 /* SPI2 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 42 /* SPI3 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 43 /* GPTMR0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 44 /* GPTMR1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 45 /* GPTMR2 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 46 /* GPTMR3 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 47 /* GPTMR4 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 48 /* GPTMR5 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 49 /* GPTMR6 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 50 /* GPTMR7 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 51 /* EWDG0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 52 /* EWDG1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 53 /* MBX0A IRQ handler */ + IRQ_DEFAULT_S_HANDLER 54 /* MBX0B IRQ handler */ + IRQ_DEFAULT_S_HANDLER 55 /* MBX1A IRQ handler */ + IRQ_DEFAULT_S_HANDLER 56 /* MBX1B IRQ handler */ + IRQ_DEFAULT_S_HANDLER 57 /* RNG IRQ handler */ + IRQ_DEFAULT_S_HANDLER 58 /* HDMA IRQ handler */ + IRQ_DEFAULT_S_HANDLER 59 /* ADC0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 60 /* ADC1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 61 /* SDM IRQ handler */ + IRQ_DEFAULT_S_HANDLER 62 /* OPAMP IRQ handler */ + IRQ_DEFAULT_S_HANDLER 63 /* I2S0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 64 /* I2S1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 65 /* I2S2 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 66 /* I2S3 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 67 /* DAO IRQ handler */ + IRQ_DEFAULT_S_HANDLER 68 /* PDM IRQ handler */ + IRQ_DEFAULT_S_HANDLER 69 /* SMIX_DMA IRQ handler */ + IRQ_DEFAULT_S_HANDLER 70 /* SMIX_ASRC IRQ handler */ + IRQ_DEFAULT_S_HANDLER 71 /* CAM0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 72 /* CAM1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 73 /* LCDC IRQ handler */ + IRQ_DEFAULT_S_HANDLER 74 /* LCDC1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 75 /* PDMA IRQ handler */ + IRQ_DEFAULT_S_HANDLER 76 /* JPEG IRQ handler */ + IRQ_DEFAULT_S_HANDLER 77 /* GWCK0_FUNC IRQ handler */ + IRQ_DEFAULT_S_HANDLER 78 /* GWCK0_ERR IRQ handler */ + IRQ_DEFAULT_S_HANDLER 79 /* GWCK1_FUNC IRQ handler */ + IRQ_DEFAULT_S_HANDLER 80 /* GWCK1_ERR IRQ handler */ + IRQ_DEFAULT_S_HANDLER 81 /* MIPI_DSI0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 82 /* MIPI_DSI1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 83 /* MIPI_CSI0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 84 /* MIPI_CSI0_AP IRQ handler */ + IRQ_DEFAULT_S_HANDLER 85 /* MIPI_CSI0_DIAG IRQ handler */ + IRQ_DEFAULT_S_HANDLER 86 /* MIPI_CSI1_AP IRQ handler */ + IRQ_DEFAULT_S_HANDLER 87 /* MIPI_CSI1_DIAG IRQ handler */ + IRQ_DEFAULT_S_HANDLER 88 /* MIPI_CSI1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 89 /* LCB0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 90 /* LCB1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 91 /* GPU IRQ handler */ + IRQ_DEFAULT_S_HANDLER 92 /* ENET0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 93 /* NTMR0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 94 /* USB0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 95 /* SDXC0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 96 /* SDXC1 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 97 /* SDP IRQ handler */ + IRQ_DEFAULT_S_HANDLER 98 /* XPI0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 99 /* XDMA IRQ handler */ + IRQ_DEFAULT_S_HANDLER 100 /* DDR IRQ handler */ + IRQ_DEFAULT_S_HANDLER 101 /* FFA IRQ handler */ + IRQ_DEFAULT_S_HANDLER 102 /* PSEC IRQ handler */ + IRQ_DEFAULT_S_HANDLER 103 /* TSNS IRQ handler */ + IRQ_DEFAULT_S_HANDLER 104 /* VAD IRQ handler */ + IRQ_DEFAULT_S_HANDLER 105 /* PGPIO IRQ handler */ + IRQ_DEFAULT_S_HANDLER 106 /* PWDG IRQ handler */ + IRQ_DEFAULT_S_HANDLER 107 /* PTMR IRQ handler */ + IRQ_DEFAULT_S_HANDLER 108 /* PUART IRQ handler */ + IRQ_DEFAULT_S_HANDLER 109 /* FUSE IRQ handler */ + IRQ_DEFAULT_S_HANDLER 110 /* SECMON IRQ handler */ + IRQ_DEFAULT_S_HANDLER 111 /* RTC IRQ handler */ + IRQ_DEFAULT_S_HANDLER 112 /* BGPIO IRQ handler */ + IRQ_DEFAULT_S_HANDLER 113 /* BVIO IRQ handler */ + IRQ_DEFAULT_S_HANDLER 114 /* BROWNOUT IRQ handler */ + IRQ_DEFAULT_S_HANDLER 115 /* SYSCTL IRQ handler */ + IRQ_DEFAULT_S_HANDLER 116 /* DEBUG0 IRQ handler */ + IRQ_DEFAULT_S_HANDLER 117 /* DEBUG1 IRQ handler */ + + EXTERN irq_handler_s_trap + SECTION `.vector_s_table`:CODE:ROOT(9) + PUBLIC __vector_s_table + DATA + +__vector_s_table + dc32 irq_handler_s_trap + IRQ_S_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_S_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_S_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_S_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_S_HANDLER 5 /* GPIO0_E IRQ handler */ + IRQ_S_HANDLER 6 /* GPIO0_F IRQ handler */ + IRQ_S_HANDLER 7 /* GPIO0_X IRQ handler */ + IRQ_S_HANDLER 8 /* GPIO0_Y IRQ handler */ + IRQ_S_HANDLER 9 /* GPIO0_Z IRQ handler */ + IRQ_S_HANDLER 10 /* MCAN0 IRQ handler */ + IRQ_S_HANDLER 11 /* MCAN1 IRQ handler */ + IRQ_S_HANDLER 12 /* MCAN2 IRQ handler */ + IRQ_S_HANDLER 13 /* MCAN3 IRQ handler */ + IRQ_S_HANDLER 14 /* MCAN4 IRQ handler */ + IRQ_S_HANDLER 15 /* MCAN5 IRQ handler */ + IRQ_S_HANDLER 16 /* MCAN6 IRQ handler */ + IRQ_S_HANDLER 17 /* MCAN7 IRQ handler */ + IRQ_S_HANDLER 18 /* PTPC IRQ handler */ + IRQ_S_HANDLER 19 /* Reserved */ + IRQ_S_HANDLER 20 /* Reserved */ + IRQ_S_HANDLER 21 /* Reserved */ + IRQ_S_HANDLER 22 /* Reserved */ + IRQ_S_HANDLER 23 /* Reserved */ + IRQ_S_HANDLER 24 /* Reserved */ + IRQ_S_HANDLER 25 /* Reserved */ + IRQ_S_HANDLER 26 /* Reserved */ + IRQ_S_HANDLER 27 /* UART0 IRQ handler */ + IRQ_S_HANDLER 28 /* UART1 IRQ handler */ + IRQ_S_HANDLER 29 /* UART2 IRQ handler */ + IRQ_S_HANDLER 30 /* UART3 IRQ handler */ + IRQ_S_HANDLER 31 /* UART4 IRQ handler */ + IRQ_S_HANDLER 32 /* UART5 IRQ handler */ + IRQ_S_HANDLER 33 /* UART6 IRQ handler */ + IRQ_S_HANDLER 34 /* UART7 IRQ handler */ + IRQ_S_HANDLER 35 /* I2C0 IRQ handler */ + IRQ_S_HANDLER 36 /* I2C1 IRQ handler */ + IRQ_S_HANDLER 37 /* I2C2 IRQ handler */ + IRQ_S_HANDLER 38 /* I2C3 IRQ handler */ + IRQ_S_HANDLER 39 /* SPI0 IRQ handler */ + IRQ_S_HANDLER 40 /* SPI1 IRQ handler */ + IRQ_S_HANDLER 41 /* SPI2 IRQ handler */ + IRQ_S_HANDLER 42 /* SPI3 IRQ handler */ + IRQ_S_HANDLER 43 /* GPTMR0 IRQ handler */ + IRQ_S_HANDLER 44 /* GPTMR1 IRQ handler */ + IRQ_S_HANDLER 45 /* GPTMR2 IRQ handler */ + IRQ_S_HANDLER 46 /* GPTMR3 IRQ handler */ + IRQ_S_HANDLER 47 /* GPTMR4 IRQ handler */ + IRQ_S_HANDLER 48 /* GPTMR5 IRQ handler */ + IRQ_S_HANDLER 49 /* GPTMR6 IRQ handler */ + IRQ_S_HANDLER 50 /* GPTMR7 IRQ handler */ + IRQ_S_HANDLER 51 /* EWDG0 IRQ handler */ + IRQ_S_HANDLER 52 /* EWDG1 IRQ handler */ + IRQ_S_HANDLER 53 /* MBX0A IRQ handler */ + IRQ_S_HANDLER 54 /* MBX0B IRQ handler */ + IRQ_S_HANDLER 55 /* MBX1A IRQ handler */ + IRQ_S_HANDLER 56 /* MBX1B IRQ handler */ + IRQ_S_HANDLER 57 /* RNG IRQ handler */ + IRQ_S_HANDLER 58 /* HDMA IRQ handler */ + IRQ_S_HANDLER 59 /* ADC0 IRQ handler */ + IRQ_S_HANDLER 60 /* ADC1 IRQ handler */ + IRQ_S_HANDLER 61 /* SDM IRQ handler */ + IRQ_S_HANDLER 62 /* OPAMP IRQ handler */ + IRQ_S_HANDLER 63 /* I2S0 IRQ handler */ + IRQ_S_HANDLER 64 /* I2S1 IRQ handler */ + IRQ_S_HANDLER 65 /* I2S2 IRQ handler */ + IRQ_S_HANDLER 66 /* I2S3 IRQ handler */ + IRQ_S_HANDLER 67 /* DAO IRQ handler */ + IRQ_S_HANDLER 68 /* PDM IRQ handler */ + IRQ_S_HANDLER 69 /* SMIX_DMA IRQ handler */ + IRQ_S_HANDLER 70 /* SMIX_ASRC IRQ handler */ + IRQ_S_HANDLER 71 /* CAM0 IRQ handler */ + IRQ_S_HANDLER 72 /* CAM1 IRQ handler */ + IRQ_S_HANDLER 73 /* LCDC IRQ handler */ + IRQ_S_HANDLER 74 /* LCDC1 IRQ handler */ + IRQ_S_HANDLER 75 /* PDMA IRQ handler */ + IRQ_S_HANDLER 76 /* JPEG IRQ handler */ + IRQ_S_HANDLER 77 /* GWCK0_FUNC IRQ handler */ + IRQ_S_HANDLER 78 /* GWCK0_ERR IRQ handler */ + IRQ_S_HANDLER 79 /* GWCK1_FUNC IRQ handler */ + IRQ_S_HANDLER 80 /* GWCK1_ERR IRQ handler */ + IRQ_S_HANDLER 81 /* MIPI_DSI0 IRQ handler */ + IRQ_S_HANDLER 82 /* MIPI_DSI1 IRQ handler */ + IRQ_S_HANDLER 83 /* MIPI_CSI0 IRQ handler */ + IRQ_S_HANDLER 84 /* MIPI_CSI0_AP IRQ handler */ + IRQ_S_HANDLER 85 /* MIPI_CSI0_DIAG IRQ handler */ + IRQ_S_HANDLER 86 /* MIPI_CSI1_AP IRQ handler */ + IRQ_S_HANDLER 87 /* MIPI_CSI1_DIAG IRQ handler */ + IRQ_S_HANDLER 88 /* MIPI_CSI1 IRQ handler */ + IRQ_S_HANDLER 89 /* LCB0 IRQ handler */ + IRQ_S_HANDLER 90 /* LCB1 IRQ handler */ + IRQ_S_HANDLER 91 /* GPU IRQ handler */ + IRQ_S_HANDLER 92 /* ENET0 IRQ handler */ + IRQ_S_HANDLER 93 /* NTMR0 IRQ handler */ + IRQ_S_HANDLER 94 /* USB0 IRQ handler */ + IRQ_S_HANDLER 95 /* SDXC0 IRQ handler */ + IRQ_S_HANDLER 96 /* SDXC1 IRQ handler */ + IRQ_S_HANDLER 97 /* SDP IRQ handler */ + IRQ_S_HANDLER 98 /* XPI0 IRQ handler */ + IRQ_S_HANDLER 99 /* XDMA IRQ handler */ + IRQ_S_HANDLER 100 /* DDR IRQ handler */ + IRQ_S_HANDLER 101 /* FFA IRQ handler */ + IRQ_S_HANDLER 102 /* PSEC IRQ handler */ + IRQ_S_HANDLER 103 /* TSNS IRQ handler */ + IRQ_S_HANDLER 104 /* VAD IRQ handler */ + IRQ_S_HANDLER 105 /* PGPIO IRQ handler */ + IRQ_S_HANDLER 106 /* PWDG IRQ handler */ + IRQ_S_HANDLER 107 /* PTMR IRQ handler */ + IRQ_S_HANDLER 108 /* PUART IRQ handler */ + IRQ_S_HANDLER 109 /* FUSE IRQ handler */ + IRQ_S_HANDLER 110 /* SECMON IRQ handler */ + IRQ_S_HANDLER 111 /* RTC IRQ handler */ + IRQ_S_HANDLER 112 /* BGPIO IRQ handler */ + IRQ_S_HANDLER 113 /* BVIO IRQ handler */ + IRQ_S_HANDLER 114 /* BROWNOUT IRQ handler */ + IRQ_S_HANDLER 115 /* SYSCTL IRQ handler */ + IRQ_S_HANDLER 116 /* DEBUG0 IRQ handler */ + IRQ_S_HANDLER 117 /* DEBUG1 IRQ handler */ + +#else + +.global default_irq_s_handler +.weak default_irq_s_handler +.align 2 +default_irq_s_handler: +1: j 1b + +.macro IRQ_S_HANDLER irq + .weak default_isr_s_\irq + .set default_isr_s_\irq, default_irq_s_handler + .long default_isr_s_\irq +.endm + +.section .vector_s_table, "a" +.global __vector_s_table +.align 9 + +__vector_s_table: + .weak default_isr_s_trap + .set default_isr_s_trap, irq_handler_s_trap + .long default_isr_s_trap + IRQ_S_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_S_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_S_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_S_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_S_HANDLER 5 /* GPIO0_E IRQ handler */ + IRQ_S_HANDLER 6 /* GPIO0_F IRQ handler */ + IRQ_S_HANDLER 7 /* GPIO0_X IRQ handler */ + IRQ_S_HANDLER 8 /* GPIO0_Y IRQ handler */ + IRQ_S_HANDLER 9 /* GPIO0_Z IRQ handler */ + IRQ_S_HANDLER 10 /* MCAN0 IRQ handler */ + IRQ_S_HANDLER 11 /* MCAN1 IRQ handler */ + IRQ_S_HANDLER 12 /* MCAN2 IRQ handler */ + IRQ_S_HANDLER 13 /* MCAN3 IRQ handler */ + IRQ_S_HANDLER 14 /* MCAN4 IRQ handler */ + IRQ_S_HANDLER 15 /* MCAN5 IRQ handler */ + IRQ_S_HANDLER 16 /* MCAN6 IRQ handler */ + IRQ_S_HANDLER 17 /* MCAN7 IRQ handler */ + IRQ_S_HANDLER 18 /* PTPC IRQ handler */ + IRQ_S_HANDLER 19 /* Reserved */ + IRQ_S_HANDLER 20 /* Reserved */ + IRQ_S_HANDLER 21 /* Reserved */ + IRQ_S_HANDLER 22 /* Reserved */ + IRQ_S_HANDLER 23 /* Reserved */ + IRQ_S_HANDLER 24 /* Reserved */ + IRQ_S_HANDLER 25 /* Reserved */ + IRQ_S_HANDLER 26 /* Reserved */ + IRQ_S_HANDLER 27 /* UART0 IRQ handler */ + IRQ_S_HANDLER 28 /* UART1 IRQ handler */ + IRQ_S_HANDLER 29 /* UART2 IRQ handler */ + IRQ_S_HANDLER 30 /* UART3 IRQ handler */ + IRQ_S_HANDLER 31 /* UART4 IRQ handler */ + IRQ_S_HANDLER 32 /* UART5 IRQ handler */ + IRQ_S_HANDLER 33 /* UART6 IRQ handler */ + IRQ_S_HANDLER 34 /* UART7 IRQ handler */ + IRQ_S_HANDLER 35 /* I2C0 IRQ handler */ + IRQ_S_HANDLER 36 /* I2C1 IRQ handler */ + IRQ_S_HANDLER 37 /* I2C2 IRQ handler */ + IRQ_S_HANDLER 38 /* I2C3 IRQ handler */ + IRQ_S_HANDLER 39 /* SPI0 IRQ handler */ + IRQ_S_HANDLER 40 /* SPI1 IRQ handler */ + IRQ_S_HANDLER 41 /* SPI2 IRQ handler */ + IRQ_S_HANDLER 42 /* SPI3 IRQ handler */ + IRQ_S_HANDLER 43 /* GPTMR0 IRQ handler */ + IRQ_S_HANDLER 44 /* GPTMR1 IRQ handler */ + IRQ_S_HANDLER 45 /* GPTMR2 IRQ handler */ + IRQ_S_HANDLER 46 /* GPTMR3 IRQ handler */ + IRQ_S_HANDLER 47 /* GPTMR4 IRQ handler */ + IRQ_S_HANDLER 48 /* GPTMR5 IRQ handler */ + IRQ_S_HANDLER 49 /* GPTMR6 IRQ handler */ + IRQ_S_HANDLER 50 /* GPTMR7 IRQ handler */ + IRQ_S_HANDLER 51 /* EWDG0 IRQ handler */ + IRQ_S_HANDLER 52 /* EWDG1 IRQ handler */ + IRQ_S_HANDLER 53 /* MBX0A IRQ handler */ + IRQ_S_HANDLER 54 /* MBX0B IRQ handler */ + IRQ_S_HANDLER 55 /* MBX1A IRQ handler */ + IRQ_S_HANDLER 56 /* MBX1B IRQ handler */ + IRQ_S_HANDLER 57 /* RNG IRQ handler */ + IRQ_S_HANDLER 58 /* HDMA IRQ handler */ + IRQ_S_HANDLER 59 /* ADC0 IRQ handler */ + IRQ_S_HANDLER 60 /* ADC1 IRQ handler */ + IRQ_S_HANDLER 61 /* SDM IRQ handler */ + IRQ_S_HANDLER 62 /* OPAMP IRQ handler */ + IRQ_S_HANDLER 63 /* I2S0 IRQ handler */ + IRQ_S_HANDLER 64 /* I2S1 IRQ handler */ + IRQ_S_HANDLER 65 /* I2S2 IRQ handler */ + IRQ_S_HANDLER 66 /* I2S3 IRQ handler */ + IRQ_S_HANDLER 67 /* DAO IRQ handler */ + IRQ_S_HANDLER 68 /* PDM IRQ handler */ + IRQ_S_HANDLER 69 /* SMIX_DMA IRQ handler */ + IRQ_S_HANDLER 70 /* SMIX_ASRC IRQ handler */ + IRQ_S_HANDLER 71 /* CAM0 IRQ handler */ + IRQ_S_HANDLER 72 /* CAM1 IRQ handler */ + IRQ_S_HANDLER 73 /* LCDC IRQ handler */ + IRQ_S_HANDLER 74 /* LCDC1 IRQ handler */ + IRQ_S_HANDLER 75 /* PDMA IRQ handler */ + IRQ_S_HANDLER 76 /* JPEG IRQ handler */ + IRQ_S_HANDLER 77 /* GWCK0_FUNC IRQ handler */ + IRQ_S_HANDLER 78 /* GWCK0_ERR IRQ handler */ + IRQ_S_HANDLER 79 /* GWCK1_FUNC IRQ handler */ + IRQ_S_HANDLER 80 /* GWCK1_ERR IRQ handler */ + IRQ_S_HANDLER 81 /* MIPI_DSI0 IRQ handler */ + IRQ_S_HANDLER 82 /* MIPI_DSI1 IRQ handler */ + IRQ_S_HANDLER 83 /* MIPI_CSI0 IRQ handler */ + IRQ_S_HANDLER 84 /* MIPI_CSI0_AP IRQ handler */ + IRQ_S_HANDLER 85 /* MIPI_CSI0_DIAG IRQ handler */ + IRQ_S_HANDLER 86 /* MIPI_CSI1_AP IRQ handler */ + IRQ_S_HANDLER 87 /* MIPI_CSI1_DIAG IRQ handler */ + IRQ_S_HANDLER 88 /* MIPI_CSI1 IRQ handler */ + IRQ_S_HANDLER 89 /* LCB0 IRQ handler */ + IRQ_S_HANDLER 90 /* LCB1 IRQ handler */ + IRQ_S_HANDLER 91 /* GPU IRQ handler */ + IRQ_S_HANDLER 92 /* ENET0 IRQ handler */ + IRQ_S_HANDLER 93 /* NTMR0 IRQ handler */ + IRQ_S_HANDLER 94 /* USB0 IRQ handler */ + IRQ_S_HANDLER 95 /* SDXC0 IRQ handler */ + IRQ_S_HANDLER 96 /* SDXC1 IRQ handler */ + IRQ_S_HANDLER 97 /* SDP IRQ handler */ + IRQ_S_HANDLER 98 /* XPI0 IRQ handler */ + IRQ_S_HANDLER 99 /* XDMA IRQ handler */ + IRQ_S_HANDLER 100 /* DDR IRQ handler */ + IRQ_S_HANDLER 101 /* FFA IRQ handler */ + IRQ_S_HANDLER 102 /* PSEC IRQ handler */ + IRQ_S_HANDLER 103 /* TSNS IRQ handler */ + IRQ_S_HANDLER 104 /* VAD IRQ handler */ + IRQ_S_HANDLER 105 /* PGPIO IRQ handler */ + IRQ_S_HANDLER 106 /* PWDG IRQ handler */ + IRQ_S_HANDLER 107 /* PTMR IRQ handler */ + IRQ_S_HANDLER 108 /* PUART IRQ handler */ + IRQ_S_HANDLER 109 /* FUSE IRQ handler */ + IRQ_S_HANDLER 110 /* SECMON IRQ handler */ + IRQ_S_HANDLER 111 /* RTC IRQ handler */ + IRQ_S_HANDLER 112 /* BGPIO IRQ handler */ + IRQ_S_HANDLER 113 /* BVIO IRQ handler */ + IRQ_S_HANDLER 114 /* BROWNOUT IRQ handler */ + IRQ_S_HANDLER 115 /* SYSCTL IRQ handler */ + IRQ_S_HANDLER 116 /* DEBUG0 IRQ handler */ + IRQ_S_HANDLER 117 /* DEBUG1 IRQ handler */ + +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_adc12_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_adc12_regs.h index 0e319e5b75d..95d38eca593 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_adc12_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_adc12_regs.h @@ -392,8 +392,8 @@ typedef struct { * * threshold high, assert interrupt(if enabled) if result exceed high or low. */ -#define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK (0xFFFF0000UL) -#define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT (16U) +#define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK (0xFFF00000UL) +#define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT (20U) #define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_SET(x) (((uint32_t)(x) << ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT) & ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK) #define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_GET(x) (((uint32_t)(x) & ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK) >> ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT) @@ -402,8 +402,8 @@ typedef struct { * * threshold low */ -#define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK (0xFFFFU) -#define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT (0U) +#define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK (0xFFF0U) +#define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT (4U) #define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_SET(x) (((uint32_t)(x) << ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT) & ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK) #define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_GET(x) (((uint32_t)(x) & ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK) >> ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT) @@ -502,7 +502,7 @@ typedef struct { /* Bitfield definition for register: INT_STS */ /* - * TRIG_CMPT (W1C) + * TRIG_CMPT (RW1C) * * interrupt for one trigger conversion complete if enabled */ @@ -512,7 +512,7 @@ typedef struct { #define ADC12_INT_STS_TRIG_CMPT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_TRIG_CMPT_MASK) >> ADC12_INT_STS_TRIG_CMPT_SHIFT) /* - * TRIG_SW_CFLCT (W1C) + * TRIG_SW_CFLCT (RW1C) * */ #define ADC12_INT_STS_TRIG_SW_CFLCT_MASK (0x40000000UL) @@ -521,7 +521,7 @@ typedef struct { #define ADC12_INT_STS_TRIG_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_TRIG_SW_CFLCT_MASK) >> ADC12_INT_STS_TRIG_SW_CFLCT_SHIFT) /* - * TRIG_HW_CFLCT (RW) + * TRIG_HW_CFLCT (RW1C) * */ #define ADC12_INT_STS_TRIG_HW_CFLCT_MASK (0x20000000UL) @@ -530,7 +530,7 @@ typedef struct { #define ADC12_INT_STS_TRIG_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_TRIG_HW_CFLCT_MASK) >> ADC12_INT_STS_TRIG_HW_CFLCT_SHIFT) /* - * READ_CFLCT (W1C) + * READ_CFLCT (RW1C) * * read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel */ @@ -540,7 +540,7 @@ typedef struct { #define ADC12_INT_STS_READ_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_READ_CFLCT_MASK) >> ADC12_INT_STS_READ_CFLCT_SHIFT) /* - * SEQ_SW_CFLCT (W1C) + * SEQ_SW_CFLCT (RW1C) * * sequence queue conflict interrup, set if HW or SW trigger received during conversion */ @@ -550,7 +550,7 @@ typedef struct { #define ADC12_INT_STS_SEQ_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_SEQ_SW_CFLCT_MASK) >> ADC12_INT_STS_SEQ_SW_CFLCT_SHIFT) /* - * SEQ_HW_CFLCT (RW) + * SEQ_HW_CFLCT (RW1C) * */ #define ADC12_INT_STS_SEQ_HW_CFLCT_MASK (0x4000000UL) @@ -559,7 +559,7 @@ typedef struct { #define ADC12_INT_STS_SEQ_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_SEQ_HW_CFLCT_MASK) >> ADC12_INT_STS_SEQ_HW_CFLCT_SHIFT) /* - * SEQ_DMAABT (W1C) + * SEQ_DMAABT (RW1C) * * dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set */ @@ -569,7 +569,7 @@ typedef struct { #define ADC12_INT_STS_SEQ_DMAABT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_SEQ_DMAABT_MASK) >> ADC12_INT_STS_SEQ_DMAABT_SHIFT) /* - * SEQ_CMPT (W1C) + * SEQ_CMPT (RW1C) * * the whole sequence complete interrupt */ @@ -579,7 +579,7 @@ typedef struct { #define ADC12_INT_STS_SEQ_CMPT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_SEQ_CMPT_MASK) >> ADC12_INT_STS_SEQ_CMPT_SHIFT) /* - * SEQ_CVC (W1C) + * SEQ_CVC (RW1C) * * one conversion complete in seq_queue if related seq_int_en is set */ @@ -589,7 +589,7 @@ typedef struct { #define ADC12_INT_STS_SEQ_CVC_GET(x) (((uint32_t)(x) & ADC12_INT_STS_SEQ_CVC_MASK) >> ADC12_INT_STS_SEQ_CVC_SHIFT) /* - * DMA_FIFO_FULL (RW) + * DMA_FIFO_FULL (RW1C) * */ #define ADC12_INT_STS_DMA_FIFO_FULL_MASK (0x400000UL) @@ -598,7 +598,7 @@ typedef struct { #define ADC12_INT_STS_DMA_FIFO_FULL_GET(x) (((uint32_t)(x) & ADC12_INT_STS_DMA_FIFO_FULL_MASK) >> ADC12_INT_STS_DMA_FIFO_FULL_SHIFT) /* - * AHB_ERR (RW) + * AHB_ERR (RW1C) * * set if got hresp=1 */ @@ -608,7 +608,7 @@ typedef struct { #define ADC12_INT_STS_AHB_ERR_GET(x) (((uint32_t)(x) & ADC12_INT_STS_AHB_ERR_MASK) >> ADC12_INT_STS_AHB_ERR_SHIFT) /* - * WDOG (W1C) + * WDOG (RW1C) * * set if one chanel watch dog event triggered */ @@ -619,7 +619,7 @@ typedef struct { /* Bitfield definition for register: INT_EN */ /* - * TRIG_CMPT (W1C) + * TRIG_CMPT (RW) * * interrupt for one trigger conversion complete if enabled */ @@ -629,7 +629,7 @@ typedef struct { #define ADC12_INT_EN_TRIG_CMPT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_TRIG_CMPT_MASK) >> ADC12_INT_EN_TRIG_CMPT_SHIFT) /* - * TRIG_SW_CFLCT (W1C) + * TRIG_SW_CFLCT (RW) * */ #define ADC12_INT_EN_TRIG_SW_CFLCT_MASK (0x40000000UL) @@ -647,7 +647,7 @@ typedef struct { #define ADC12_INT_EN_TRIG_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_TRIG_HW_CFLCT_MASK) >> ADC12_INT_EN_TRIG_HW_CFLCT_SHIFT) /* - * READ_CFLCT (W1C) + * READ_CFLCT (RW) * * read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel */ @@ -657,7 +657,7 @@ typedef struct { #define ADC12_INT_EN_READ_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_READ_CFLCT_MASK) >> ADC12_INT_EN_READ_CFLCT_SHIFT) /* - * SEQ_SW_CFLCT (W1C) + * SEQ_SW_CFLCT (RW) * * sequence queue conflict interrup, set if HW or SW trigger received during conversion */ @@ -676,7 +676,7 @@ typedef struct { #define ADC12_INT_EN_SEQ_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_SEQ_HW_CFLCT_MASK) >> ADC12_INT_EN_SEQ_HW_CFLCT_SHIFT) /* - * SEQ_DMAABT (W1C) + * SEQ_DMAABT (RW) * * dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set */ @@ -686,7 +686,7 @@ typedef struct { #define ADC12_INT_EN_SEQ_DMAABT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_SEQ_DMAABT_MASK) >> ADC12_INT_EN_SEQ_DMAABT_SHIFT) /* - * SEQ_CMPT (W1C) + * SEQ_CMPT (RW) * * the whole sequence complete interrupt */ @@ -696,7 +696,7 @@ typedef struct { #define ADC12_INT_EN_SEQ_CMPT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_SEQ_CMPT_MASK) >> ADC12_INT_EN_SEQ_CMPT_SHIFT) /* - * SEQ_CVC (W1C) + * SEQ_CVC (RW) * * one conversion complete in seq_queue if related seq_int_en is set */ @@ -706,7 +706,7 @@ typedef struct { #define ADC12_INT_EN_SEQ_CVC_GET(x) (((uint32_t)(x) & ADC12_INT_EN_SEQ_CVC_MASK) >> ADC12_INT_EN_SEQ_CVC_SHIFT) /* - * DMA_FIFO_FULL (W1C) + * DMA_FIFO_FULL (RW) * * DMA fifo full interrupt, user need to check clock frequency if it's set. */ @@ -716,7 +716,7 @@ typedef struct { #define ADC12_INT_EN_DMA_FIFO_FULL_GET(x) (((uint32_t)(x) & ADC12_INT_EN_DMA_FIFO_FULL_MASK) >> ADC12_INT_EN_DMA_FIFO_FULL_SHIFT) /* - * AHB_ERR (W1C) + * AHB_ERR (RW) * * set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr */ @@ -726,7 +726,7 @@ typedef struct { #define ADC12_INT_EN_AHB_ERR_GET(x) (((uint32_t)(x) & ADC12_INT_EN_AHB_ERR_MASK) >> ADC12_INT_EN_AHB_ERR_SHIFT) /* - * WDOG (W1C) + * WDOG (RW) * * set if one chanel watch dog event triggered */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_adc16_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_adc16_regs.h index 865d0d475c2..a2c5711f23f 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_adc16_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_adc16_regs.h @@ -23,7 +23,8 @@ typedef struct { __R uint32_t SEQ_WR_ADDR; /* 0x808: */ __RW uint32_t SEQ_DMA_CFG; /* 0x80C: */ __RW uint32_t SEQ_QUE[16]; /* 0x810 - 0x84C: */ - __R uint8_t RESERVED3[944]; /* 0x850 - 0xBFF: Reserved */ + __RW uint32_t SEQ_HIGH_CFG; /* 0x850: */ + __R uint8_t RESERVED3[940]; /* 0x854 - 0xBFF: Reserved */ struct { __RW uint32_t PRD_CFG; /* 0xC00: */ __RW uint32_t PRD_THSHD_CFG; /* 0xC04: */ @@ -388,6 +389,25 @@ typedef struct { #define ADC16_SEQ_QUE_CHAN_NUM_4_0_SET(x) (((uint32_t)(x) << ADC16_SEQ_QUE_CHAN_NUM_4_0_SHIFT) & ADC16_SEQ_QUE_CHAN_NUM_4_0_MASK) #define ADC16_SEQ_QUE_CHAN_NUM_4_0_GET(x) (((uint32_t)(x) & ADC16_SEQ_QUE_CHAN_NUM_4_0_MASK) >> ADC16_SEQ_QUE_CHAN_NUM_4_0_SHIFT) +/* Bitfield definition for register: SEQ_HIGH_CFG */ +/* + * STOP_POS_HIGH (RW) + * + */ +#define ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_MASK (0xFFF000UL) +#define ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_SHIFT (12U) +#define ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_SET(x) (((uint32_t)(x) << ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_SHIFT) & ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_MASK) +#define ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_GET(x) (((uint32_t)(x) & ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_MASK) >> ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_SHIFT) + +/* + * BUF_LEN_HIGH (RW) + * + */ +#define ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_MASK (0xFFFU) +#define ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_SHIFT (0U) +#define ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_SET(x) (((uint32_t)(x) << ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_SHIFT) & ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_MASK) +#define ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_GET(x) (((uint32_t)(x) & ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_MASK) >> ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_SHIFT) + /* Bitfield definition for register of struct array PRD_CFG: PRD_CFG */ /* * PRESCALE (RW) @@ -467,7 +487,7 @@ typedef struct { /* * CONVERT_CLOCK_NUMBER (RW) * - * convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 22 adc clock cycles(based on clock after divider); + * convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider); * user can use small value to get faster convertion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. * Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC convertion(plus sample) need 25 cycles(50MHz). */ @@ -536,7 +556,7 @@ typedef struct { /* Bitfield definition for register: INT_STS */ /* - * TRIG_CMPT (W1C) + * TRIG_CMPT (RW1C) * * interrupt for one trigger conversion complete if enabled */ @@ -546,7 +566,7 @@ typedef struct { #define ADC16_INT_STS_TRIG_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_TRIG_CMPT_MASK) >> ADC16_INT_STS_TRIG_CMPT_SHIFT) /* - * TRIG_SW_CFLCT (W1C) + * TRIG_SW_CFLCT (RW1C) * */ #define ADC16_INT_STS_TRIG_SW_CFLCT_MASK (0x40000000UL) @@ -555,7 +575,7 @@ typedef struct { #define ADC16_INT_STS_TRIG_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_TRIG_SW_CFLCT_MASK) >> ADC16_INT_STS_TRIG_SW_CFLCT_SHIFT) /* - * TRIG_HW_CFLCT (RW) + * TRIG_HW_CFLCT (RW1C) * */ #define ADC16_INT_STS_TRIG_HW_CFLCT_MASK (0x20000000UL) @@ -564,7 +584,7 @@ typedef struct { #define ADC16_INT_STS_TRIG_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_TRIG_HW_CFLCT_MASK) >> ADC16_INT_STS_TRIG_HW_CFLCT_SHIFT) /* - * READ_CFLCT (W1C) + * READ_CFLCT (RW1C) * * read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel */ @@ -574,7 +594,7 @@ typedef struct { #define ADC16_INT_STS_READ_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_READ_CFLCT_MASK) >> ADC16_INT_STS_READ_CFLCT_SHIFT) /* - * SEQ_SW_CFLCT (W1C) + * SEQ_SW_CFLCT (RW1C) * * sequence queue conflict interrup, set if HW or SW trigger received during conversion */ @@ -584,7 +604,7 @@ typedef struct { #define ADC16_INT_STS_SEQ_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_SW_CFLCT_MASK) >> ADC16_INT_STS_SEQ_SW_CFLCT_SHIFT) /* - * SEQ_HW_CFLCT (RW) + * SEQ_HW_CFLCT (RW1C) * */ #define ADC16_INT_STS_SEQ_HW_CFLCT_MASK (0x4000000UL) @@ -593,7 +613,7 @@ typedef struct { #define ADC16_INT_STS_SEQ_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_HW_CFLCT_MASK) >> ADC16_INT_STS_SEQ_HW_CFLCT_SHIFT) /* - * SEQ_DMAABT (W1C) + * SEQ_DMAABT (RW1C) * * dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set */ @@ -603,7 +623,7 @@ typedef struct { #define ADC16_INT_STS_SEQ_DMAABT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_DMAABT_MASK) >> ADC16_INT_STS_SEQ_DMAABT_SHIFT) /* - * SEQ_CMPT (W1C) + * SEQ_CMPT (RW1C) * * the whole sequence complete interrupt */ @@ -613,7 +633,7 @@ typedef struct { #define ADC16_INT_STS_SEQ_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_CMPT_MASK) >> ADC16_INT_STS_SEQ_CMPT_SHIFT) /* - * SEQ_CVC (W1C) + * SEQ_CVC (RW1C) * * one conversion complete in seq_queue if related seq_int_en is set */ @@ -623,7 +643,7 @@ typedef struct { #define ADC16_INT_STS_SEQ_CVC_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_CVC_MASK) >> ADC16_INT_STS_SEQ_CVC_SHIFT) /* - * DMA_FIFO_FULL (RW) + * DMA_FIFO_FULL (RW1C) * * DMA fifo full interrupt, user need to check clock frequency if it's set. */ @@ -633,7 +653,7 @@ typedef struct { #define ADC16_INT_STS_DMA_FIFO_FULL_GET(x) (((uint32_t)(x) & ADC16_INT_STS_DMA_FIFO_FULL_MASK) >> ADC16_INT_STS_DMA_FIFO_FULL_SHIFT) /* - * AHB_ERR (RW) + * AHB_ERR (RW1C) * * set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr */ @@ -643,7 +663,7 @@ typedef struct { #define ADC16_INT_STS_AHB_ERR_GET(x) (((uint32_t)(x) & ADC16_INT_STS_AHB_ERR_MASK) >> ADC16_INT_STS_AHB_ERR_SHIFT) /* - * WDOG (W1C) + * WDOG (RW1C) * * set if one chanel watch dog event triggered */ @@ -654,7 +674,7 @@ typedef struct { /* Bitfield definition for register: INT_EN */ /* - * TRIG_CMPT (W1C) + * TRIG_CMPT (RW) * * interrupt for one trigger conversion complete if enabled */ @@ -664,7 +684,7 @@ typedef struct { #define ADC16_INT_EN_TRIG_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_TRIG_CMPT_MASK) >> ADC16_INT_EN_TRIG_CMPT_SHIFT) /* - * TRIG_SW_CFLCT (W1C) + * TRIG_SW_CFLCT (RW) * */ #define ADC16_INT_EN_TRIG_SW_CFLCT_MASK (0x40000000UL) @@ -682,7 +702,7 @@ typedef struct { #define ADC16_INT_EN_TRIG_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_TRIG_HW_CFLCT_MASK) >> ADC16_INT_EN_TRIG_HW_CFLCT_SHIFT) /* - * READ_CFLCT (W1C) + * READ_CFLCT (RW) * * read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel */ @@ -692,7 +712,7 @@ typedef struct { #define ADC16_INT_EN_READ_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_READ_CFLCT_MASK) >> ADC16_INT_EN_READ_CFLCT_SHIFT) /* - * SEQ_SW_CFLCT (W1C) + * SEQ_SW_CFLCT (RW) * * sequence queue conflict interrup, set if HW or SW trigger received during conversion */ @@ -711,7 +731,7 @@ typedef struct { #define ADC16_INT_EN_SEQ_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_HW_CFLCT_MASK) >> ADC16_INT_EN_SEQ_HW_CFLCT_SHIFT) /* - * SEQ_DMAABT (W1C) + * SEQ_DMAABT (RW) * * dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set */ @@ -721,7 +741,7 @@ typedef struct { #define ADC16_INT_EN_SEQ_DMAABT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_DMAABT_MASK) >> ADC16_INT_EN_SEQ_DMAABT_SHIFT) /* - * SEQ_CMPT (W1C) + * SEQ_CMPT (RW) * * the whole sequence complete interrupt */ @@ -731,7 +751,7 @@ typedef struct { #define ADC16_INT_EN_SEQ_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_CMPT_MASK) >> ADC16_INT_EN_SEQ_CMPT_SHIFT) /* - * SEQ_CVC (W1C) + * SEQ_CVC (RW) * * one conversion complete in seq_queue if related seq_int_en is set */ @@ -761,7 +781,7 @@ typedef struct { #define ADC16_INT_EN_AHB_ERR_GET(x) (((uint32_t)(x) & ADC16_INT_EN_AHB_ERR_MASK) >> ADC16_INT_EN_AHB_ERR_SHIFT) /* - * WDOG (W1C) + * WDOG (RW) * * set if one chanel watch dog event triggered */ @@ -771,6 +791,17 @@ typedef struct { #define ADC16_INT_EN_WDOG_GET(x) (((uint32_t)(x) & ADC16_INT_EN_WDOG_MASK) >> ADC16_INT_EN_WDOG_SHIFT) /* Bitfield definition for register: ANA_CTRL0 */ +/* + * MOTO_EN (RW) + * + * "set to enable moto_soc and moto_valid. + * Should use AHB clock for adc, this bit can be used avoid async output" + */ +#define ADC16_ANA_CTRL0_MOTO_EN_MASK (0x80000000UL) +#define ADC16_ANA_CTRL0_MOTO_EN_SHIFT (31U) +#define ADC16_ANA_CTRL0_MOTO_EN_SET(x) (((uint32_t)(x) << ADC16_ANA_CTRL0_MOTO_EN_SHIFT) & ADC16_ANA_CTRL0_MOTO_EN_MASK) +#define ADC16_ANA_CTRL0_MOTO_EN_GET(x) (((uint32_t)(x) & ADC16_ANA_CTRL0_MOTO_EN_MASK) >> ADC16_ANA_CTRL0_MOTO_EN_SHIFT) + /* * ADC_CLK_ON (RW) * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_cam_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_cam_regs.h index b0db9cc101f..d2cc2c2df37 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_cam_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_cam_regs.h @@ -26,8 +26,7 @@ typedef struct { __RW uint32_t DMASA_UV1; /* 0x50: Pixel UV DMA Frame Buffer 1 Address */ __RW uint32_t DMASA_UV2; /* 0x54: Pixel UV DMA Frame Buffer 2 Address */ __RW uint32_t CR20; /* 0x58: Control CR20 Register */ - __RW uint32_t MAX_WN_CYCLE; /* 0x5C: Max Window Size Register */ - __R uint8_t RESERVED4[16]; /* 0x60 - 0x6F: Reserved */ + __R uint8_t RESERVED4[20]; /* 0x5C - 0x6F: Reserved */ __RW uint32_t CSC_COEF0; /* 0x70: Color Space Conversion Config Register 0 */ __RW uint32_t CSC_COEF1; /* 0x74: Color Space Conversion Config Register 1 */ __RW uint32_t CSC_COEF2; /* 0x78: Color Space Conversion Config Register 2 */ @@ -628,27 +627,6 @@ typedef struct { #define CAM_CR20_THRESHOLD_SET(x) (((uint32_t)(x) << CAM_CR20_THRESHOLD_SHIFT) & CAM_CR20_THRESHOLD_MASK) #define CAM_CR20_THRESHOLD_GET(x) (((uint32_t)(x) & CAM_CR20_THRESHOLD_MASK) >> CAM_CR20_THRESHOLD_SHIFT) -/* Bitfield definition for register: MAX_WN_CYCLE */ -/* - * ROW (RW) - * - * Max Width-1 - */ -#define CAM_MAX_WN_CYCLE_ROW_MASK (0xFFFF0000UL) -#define CAM_MAX_WN_CYCLE_ROW_SHIFT (16U) -#define CAM_MAX_WN_CYCLE_ROW_SET(x) (((uint32_t)(x) << CAM_MAX_WN_CYCLE_ROW_SHIFT) & CAM_MAX_WN_CYCLE_ROW_MASK) -#define CAM_MAX_WN_CYCLE_ROW_GET(x) (((uint32_t)(x) & CAM_MAX_WN_CYCLE_ROW_MASK) >> CAM_MAX_WN_CYCLE_ROW_SHIFT) - -/* - * COL (RW) - * - * Max Height-1 - */ -#define CAM_MAX_WN_CYCLE_COL_MASK (0xFFFFU) -#define CAM_MAX_WN_CYCLE_COL_SHIFT (0U) -#define CAM_MAX_WN_CYCLE_COL_SET(x) (((uint32_t)(x) << CAM_MAX_WN_CYCLE_COL_SHIFT) & CAM_MAX_WN_CYCLE_COL_MASK) -#define CAM_MAX_WN_CYCLE_COL_GET(x) (((uint32_t)(x) & CAM_MAX_WN_CYCLE_COL_MASK) >> CAM_MAX_WN_CYCLE_COL_SHIFT) - /* Bitfield definition for register: CSC_COEF0 */ /* * YCBCR_MODE (RW) @@ -823,17 +801,6 @@ typedef struct { #define CAM_ROI_HEIGHT_ROI_HEIGHT_START_GET(x) (((uint32_t)(x) & CAM_ROI_HEIGHT_ROI_HEIGHT_START_MASK) >> CAM_ROI_HEIGHT_ROI_HEIGHT_START_SHIFT) /* Bitfield definition for register: PRO_CTRL */ -/* - * ASYNC_FIFO_SEL (RW) - * - * 0 use fifo for sync - * 1 use flipflop for sync - */ -#define CAM_PRO_CTRL_ASYNC_FIFO_SEL_MASK (0x8000U) -#define CAM_PRO_CTRL_ASYNC_FIFO_SEL_SHIFT (15U) -#define CAM_PRO_CTRL_ASYNC_FIFO_SEL_SET(x) (((uint32_t)(x) << CAM_PRO_CTRL_ASYNC_FIFO_SEL_SHIFT) & CAM_PRO_CTRL_ASYNC_FIFO_SEL_MASK) -#define CAM_PRO_CTRL_ASYNC_FIFO_SEL_GET(x) (((uint32_t)(x) & CAM_PRO_CTRL_ASYNC_FIFO_SEL_MASK) >> CAM_PRO_CTRL_ASYNC_FIFO_SEL_SHIFT) - /* * ERR_INJECT (RW) * @@ -845,59 +812,6 @@ typedef struct { #define CAM_PRO_CTRL_ERR_INJECT_SET(x) (((uint32_t)(x) << CAM_PRO_CTRL_ERR_INJECT_SHIFT) & CAM_PRO_CTRL_ERR_INJECT_MASK) #define CAM_PRO_CTRL_ERR_INJECT_GET(x) (((uint32_t)(x) & CAM_PRO_CTRL_ERR_INJECT_MASK) >> CAM_PRO_CTRL_ERR_INJECT_SHIFT) -/* - * BAYER_BIG_ENDIAN (RW) - * - * 0 bayer data is little-endian - * 1 bayer data is big-endian - */ -#define CAM_PRO_CTRL_BAYER_BIG_ENDIAN_MASK (0x2000U) -#define CAM_PRO_CTRL_BAYER_BIG_ENDIAN_SHIFT (13U) -#define CAM_PRO_CTRL_BAYER_BIG_ENDIAN_SET(x) (((uint32_t)(x) << CAM_PRO_CTRL_BAYER_BIG_ENDIAN_SHIFT) & CAM_PRO_CTRL_BAYER_BIG_ENDIAN_MASK) -#define CAM_PRO_CTRL_BAYER_BIG_ENDIAN_GET(x) (((uint32_t)(x) & CAM_PRO_CTRL_BAYER_BIG_ENDIAN_MASK) >> CAM_PRO_CTRL_BAYER_BIG_ENDIAN_SHIFT) - -/* - * READY_ERROR (W1C) - * - * indicate cam_te_b0_ready and cam_te_b1_ready assert at the same time - * clear by writing 1 - */ -#define CAM_PRO_CTRL_READY_ERROR_MASK (0x1000U) -#define CAM_PRO_CTRL_READY_ERROR_SHIFT (12U) -#define CAM_PRO_CTRL_READY_ERROR_SET(x) (((uint32_t)(x) << CAM_PRO_CTRL_READY_ERROR_SHIFT) & CAM_PRO_CTRL_READY_ERROR_MASK) -#define CAM_PRO_CTRL_READY_ERROR_GET(x) (((uint32_t)(x) & CAM_PRO_CTRL_READY_ERROR_MASK) >> CAM_PRO_CTRL_READY_ERROR_SHIFT) - -/* - * READY_ENABLE (RO) - * - * indicate cam_in_init assert - */ -#define CAM_PRO_CTRL_READY_ENABLE_MASK (0x800U) -#define CAM_PRO_CTRL_READY_ENABLE_SHIFT (11U) -#define CAM_PRO_CTRL_READY_ENABLE_GET(x) (((uint32_t)(x) & CAM_PRO_CTRL_READY_ENABLE_MASK) >> CAM_PRO_CTRL_READY_ENABLE_SHIFT) - -/* - * READY_DISABLE (RW) - * - * indicate cam_out_init de-assert - */ -#define CAM_PRO_CTRL_READY_DISABLE_MASK (0x400U) -#define CAM_PRO_CTRL_READY_DISABLE_SHIFT (10U) -#define CAM_PRO_CTRL_READY_DISABLE_SET(x) (((uint32_t)(x) << CAM_PRO_CTRL_READY_DISABLE_SHIFT) & CAM_PRO_CTRL_READY_DISABLE_MASK) -#define CAM_PRO_CTRL_READY_DISABLE_GET(x) (((uint32_t)(x) & CAM_PRO_CTRL_READY_DISABLE_MASK) >> CAM_PRO_CTRL_READY_DISABLE_SHIFT) - -/* - * BUFFER_SWITCH (RW) - * - * 00 switch buffer every frame - * 01 switch buffer every 8 lines - * 10 switch buffer every 16 lines - */ -#define CAM_PRO_CTRL_BUFFER_SWITCH_MASK (0x300U) -#define CAM_PRO_CTRL_BUFFER_SWITCH_SHIFT (8U) -#define CAM_PRO_CTRL_BUFFER_SWITCH_SET(x) (((uint32_t)(x) << CAM_PRO_CTRL_BUFFER_SWITCH_SHIFT) & CAM_PRO_CTRL_BUFFER_SWITCH_MASK) -#define CAM_PRO_CTRL_BUFFER_SWITCH_GET(x) (((uint32_t)(x) & CAM_PRO_CTRL_BUFFER_SWITCH_MASK) >> CAM_PRO_CTRL_BUFFER_SWITCH_SHIFT) - /* * ROI_UPDATE (RW) * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dac_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dac_regs.h index 70c2d441443..101e4c0d7e8 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dac_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dac_regs.h @@ -90,6 +90,9 @@ typedef struct { * 00: direct mode, DAC output the fixed configured data(from sw_dac_data) * 01: step mode, DAC output from start_point to end point, with configured step, can step up or step down * 10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; + * 11: trigger mode, DAC output from external trigger signals + * Note: + * Trigger mode is not supported in hpm63xx and hpm62xx families. */ #define DAC_CFG0_DAC_MODE_MASK (0x30U) #define DAC_CFG0_DAC_MODE_SHIFT (4U) @@ -125,6 +128,7 @@ typedef struct { * ANA_CLK_EN (RW) * * set to enable analog clock(divided by ana_div_cfg) + * need to be set in direct mode and trigger mode */ #define DAC_CFG1_ANA_CLK_EN_MASK (0x40000UL) #define DAC_CFG1_ANA_CLK_EN_SHIFT (18U) @@ -148,8 +152,12 @@ typedef struct { /* * DIV_CFG (RW) * - * how many clk_dac cycles to change data to analog, should configured to less than 1MHz data rate. - * Used for step mode and buffer mode, if set to continual trigger mode + * step mode and buffer mode: + * defines how many clk_dac cycles to change data to analog, should configured to less than 1MHz data rate. + * Direct mode and trigger mode: + * defines how many clk_dac cycles to accpet the input data, dac will not accept new written data or trigger data before the clock cycles passed. should configured to less than 1MHz. + * Note: + * For direct mode and trigger mode, this config is not supported in hpm63xx and hpm62xx families. */ #define DAC_CFG1_DIV_CFG_MASK (0xFFFFU) #define DAC_CFG1_DIV_CFG_SHIFT (0U) diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dao_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dao_regs.h index 1162cb3a59f..acc1172c260 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dao_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dao_regs.h @@ -128,6 +128,18 @@ typedef struct { #define DAO_CMD_RUN_GET(x) (((uint32_t)(x) & DAO_CMD_RUN_MASK) >> DAO_CMD_RUN_SHIFT) /* Bitfield definition for register: RX_CFGR */ +/* + * FRAME_EDGE (RW) + * + * The start edge of a frame + * 0: Falling edge indicates a new frame (Just like standard I2S Philips standard) + * 1: Rising edge indicates a new frame + */ +#define DAO_RX_CFGR_FRAME_EDGE_MASK (0x800U) +#define DAO_RX_CFGR_FRAME_EDGE_SHIFT (11U) +#define DAO_RX_CFGR_FRAME_EDGE_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_FRAME_EDGE_SHIFT) & DAO_RX_CFGR_FRAME_EDGE_MASK) +#define DAO_RX_CFGR_FRAME_EDGE_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_FRAME_EDGE_MASK) >> DAO_RX_CFGR_FRAME_EDGE_SHIFT) + /* * CH_MAX (RW) * @@ -142,6 +154,63 @@ typedef struct { #define DAO_RX_CFGR_CH_MAX_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_CH_MAX_SHIFT) & DAO_RX_CFGR_CH_MAX_MASK) #define DAO_RX_CFGR_CH_MAX_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_CH_MAX_MASK) >> DAO_RX_CFGR_CH_MAX_SHIFT) +/* + * TDM_EN (RW) + * + * TDM mode + * 0: not TDM mode + * 1: TDM mode + */ +#define DAO_RX_CFGR_TDM_EN_MASK (0x20U) +#define DAO_RX_CFGR_TDM_EN_SHIFT (5U) +#define DAO_RX_CFGR_TDM_EN_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_TDM_EN_SHIFT) & DAO_RX_CFGR_TDM_EN_MASK) +#define DAO_RX_CFGR_TDM_EN_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_TDM_EN_MASK) >> DAO_RX_CFGR_TDM_EN_SHIFT) + +/* + * STD (RW) + * + * I2S standard selection + * 00: I2S Philips standard. + * 01: MSB justified standard (left justified) + * 10: LSB justified standard (right justified) + * 11: PCM standard + * For more details on I2S standards. + * Note: For correct operation, these bits should be configured when the I2S is disabled. + */ +#define DAO_RX_CFGR_STD_MASK (0x18U) +#define DAO_RX_CFGR_STD_SHIFT (3U) +#define DAO_RX_CFGR_STD_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_STD_SHIFT) & DAO_RX_CFGR_STD_MASK) +#define DAO_RX_CFGR_STD_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_STD_MASK) >> DAO_RX_CFGR_STD_SHIFT) + +/* + * DATSIZ (RW) + * + * Data length to be transferred + * 00: 16-bit data length + * 01: 24-bit data length + * 10: 32-bit data length + * 11: Not allowed + * Note: For correct operation, these bits should be configured when the I2S is disabled. + */ +#define DAO_RX_CFGR_DATSIZ_MASK (0x6U) +#define DAO_RX_CFGR_DATSIZ_SHIFT (1U) +#define DAO_RX_CFGR_DATSIZ_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_DATSIZ_SHIFT) & DAO_RX_CFGR_DATSIZ_MASK) +#define DAO_RX_CFGR_DATSIZ_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_DATSIZ_MASK) >> DAO_RX_CFGR_DATSIZ_SHIFT) + +/* + * CHSIZ (RW) + * + * Channel length (number of bits per audio channel) + * 0: 16-bit wide + * 1: 32-bit wide + * The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. + * Note: For correct operation, this bit should be configured when the I2S is disabled. + */ +#define DAO_RX_CFGR_CHSIZ_MASK (0x1U) +#define DAO_RX_CFGR_CHSIZ_SHIFT (0U) +#define DAO_RX_CFGR_CHSIZ_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_CHSIZ_SHIFT) & DAO_RX_CFGR_CHSIZ_MASK) +#define DAO_RX_CFGR_CHSIZ_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_CHSIZ_MASK) >> DAO_RX_CFGR_CHSIZ_SHIFT) + /* Bitfield definition for register: RXSLT */ /* * EN (RW) @@ -178,4 +247,4 @@ typedef struct { -#endif /* HPM_DAO_H */ \ No newline at end of file +#endif /* HPM_DAO_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ddrctl_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ddrctl_regs.h new file mode 100644 index 00000000000..337c1109852 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ddrctl_regs.h @@ -0,0 +1,3636 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_DDRCTL_H +#define HPM_DDRCTL_H + +typedef struct { + __RW uint32_t MSTR; /* 0x0: Description: Master Register */ + __R uint32_t STAT; /* 0x4: Description: Operating Mode Status Register */ + __R uint8_t RESERVED0[8]; /* 0x8 - 0xF: Reserved */ + __RW uint32_t MRCTRL0; /* 0x10: Description: Mode Register Read/Write Control Register 0 */ + __RW uint32_t MRCTRL1; /* 0x14: Description: Mode Register Read/Write Control Register 1 */ + __R uint32_t MRSTAT; /* 0x18: Description: Mode Register Read/Write Status Register */ + __R uint8_t RESERVED1[20]; /* 0x1C - 0x2F: Reserved */ + __RW uint32_t PWRCTL; /* 0x30: Description: Low Power Control Register */ + __RW uint32_t PWRTMG; /* 0x34: Description: Low Power Timing Register */ + __RW uint32_t HWLPCTL; /* 0x38: Description: Hardware Low Power Control Register */ + __R uint8_t RESERVED2[20]; /* 0x3C - 0x4F: Reserved */ + __RW uint32_t RFSHCTL0; /* 0x50: Description: Refresh Control Register 0 */ + __RW uint32_t RFSHCTL1; /* 0x54: Description: Refresh Control Register 1 */ + __R uint8_t RESERVED3[8]; /* 0x58 - 0x5F: Reserved */ + __RW uint32_t RFSHCTL3; /* 0x60: Description: Refresh Control Register 0 */ + __RW uint32_t RFSHTMG; /* 0x64: Description: Refresh Timing Register */ + __R uint8_t RESERVED4[60]; /* 0x68 - 0xA3: Reserved */ + __R uint32_t ECCUADDR0; /* 0xA4: Description: ECC Uncorrected Error Address Register 0 */ + __R uint8_t RESERVED5[24]; /* 0xA8 - 0xBF: Reserved */ + __RW uint32_t CRCPARCTL0; /* 0xC0: Description: CRC Parity Control Register0 */ + __R uint8_t RESERVED6[8]; /* 0xC4 - 0xCB: Reserved */ + __R uint32_t CRCPARSTAT; /* 0xCC: Description: CRC Parity Status Register */ + __RW uint32_t INIT0; /* 0xD0: Description: SDRAM Initialization Register 0 */ + __RW uint32_t INIT1; /* 0xD4: Description: SDRAM Initialization Register 1 */ + __R uint8_t RESERVED7[4]; /* 0xD8 - 0xDB: Reserved */ + __RW uint32_t INIT3; /* 0xDC: Description: SDRAM Initialization Register 3 */ + __RW uint32_t INIT4; /* 0xE0: Description: SDRAM Initialization Register 4 */ + __RW uint32_t INIT5; /* 0xE4: Description: SDRAM Initialization Register 5 */ + __R uint8_t RESERVED8[8]; /* 0xE8 - 0xEF: Reserved */ + __RW uint32_t DIMMCTL; /* 0xF0: Description: DIMM Control Register */ + __RW uint32_t RANKCTL; /* 0xF4: Description: Rank Control Register */ + __R uint8_t RESERVED9[8]; /* 0xF8 - 0xFF: Reserved */ + __RW uint32_t DRAMTMG0; /* 0x100: Description: SDRAM Timing Register 0 */ + __RW uint32_t DRAMTMG1; /* 0x104: Description: SDRAM Timing Register 1 */ + __RW uint32_t DRAMTMG2; /* 0x108: Description: SDRAM Timing Register 2 */ + __RW uint32_t DRAMTMG3; /* 0x10C: Description: SDRAM Timing Register 3 */ + __RW uint32_t DRAMTMG4; /* 0x110: Description: SDRAM Timing Register 4 */ + __RW uint32_t DRAMTMG5; /* 0x114: Description: SDRAM Timing Register 5 */ + __R uint8_t RESERVED10[8]; /* 0x118 - 0x11F: Reserved */ + __RW uint32_t DRAMTMG8; /* 0x120: Description: SDRAM Timing Register 8 */ + __R uint8_t RESERVED11[92]; /* 0x124 - 0x17F: Reserved */ + __RW uint32_t ZQCTL0; /* 0x180: Description: ZQ Control Register 0 */ + __RW uint32_t ZQCTL1; /* 0x184: Description: ZQ Control Register 1 */ + __R uint8_t RESERVED12[4]; /* 0x188 - 0x18B: Reserved */ + __R uint32_t ZQSTAT; /* 0x18C: Description: ZQ Status Register */ + __RW uint32_t DFITMG0; /* 0x190: Description: DFI Timing Register 0 */ + __RW uint32_t DFITMG1; /* 0x194: Description: DFI Timing Register 1 */ + __RW uint32_t DFILPCFG0; /* 0x198: Description: DFI Low Power Configuration Register 0 */ + __R uint8_t RESERVED13[4]; /* 0x19C - 0x19F: Reserved */ + __RW uint32_t DFIUPD0; /* 0x1A0: Description: DFI Update Register 0 */ + __RW uint32_t DFIUPD1; /* 0x1A4: Description: DFI Update Register 1 */ + __RW uint32_t DFIUPD2; /* 0x1A8: Description: DFI Update Register 2 */ + __RW uint32_t DFIUPD3; /* 0x1AC: Description: DFI Update Register 3 */ + __RW uint32_t DFIMISC; /* 0x1B0: Description: DFI Miscellaneous Control Register */ + __RW uint32_t DFITMG2; /* 0x1B4: Description: DFI Timing Register 2 */ + __R uint8_t RESERVED14[72]; /* 0x1B8 - 0x1FF: Reserved */ + __RW uint32_t ADDRMAP0; /* 0x200: Description: Address Map Register 0 */ + __RW uint32_t ADDRMAP1; /* 0x204: Description: Address Map Register 1 */ + __RW uint32_t ADDRMAP2; /* 0x208: Description: Address Map Register 2 */ + __RW uint32_t ADDRMAP3; /* 0x20C: Description: Address Map Register 3 */ + __RW uint32_t ADDRMAP4; /* 0x210: Description: Address Map Register 4 */ + __RW uint32_t ADDRMAP5; /* 0x214: Description: Address Map Register 5 */ + __RW uint32_t ADDRMAP6; /* 0x218: Description: Address Map Register 6 */ + __R uint8_t RESERVED15[36]; /* 0x21C - 0x23F: Reserved */ + __RW uint32_t ODTCFG; /* 0x240: Description: ODT Configuration Register */ + __RW uint32_t ODTMAP; /* 0x244: Description: ODT/Rank Map Register */ + __R uint8_t RESERVED16[8]; /* 0x248 - 0x24F: Reserved */ + __RW uint32_t SCHED; /* 0x250: Description: Scheduler Control Register */ + __RW uint32_t SCHED1; /* 0x254: Description: Scheduler Control Register 1 */ + __R uint8_t RESERVED17[4]; /* 0x258 - 0x25B: Reserved */ + __RW uint32_t PERFHPR1; /* 0x25C: Description: High Priority Read CAM Register 1 */ + __R uint8_t RESERVED18[4]; /* 0x260 - 0x263: Reserved */ + __RW uint32_t PERFLPR1; /* 0x264: Description: Low Priority Read CAM Register 1 */ + __R uint8_t RESERVED19[4]; /* 0x268 - 0x26B: Reserved */ + __RW uint32_t PERFWR1; /* 0x26C: Description: Write CAM Register 1 */ + __R uint8_t RESERVED20[4]; /* 0x270 - 0x273: Reserved */ + __RW uint32_t PERFVPR1; /* 0x274: Description: Variable Priority Read CAM Register 1 */ + __RW uint32_t PERFVPW1; /* 0x278: Description: Variable Priority Write CAM Register 1 */ + __R uint8_t RESERVED21[132]; /* 0x27C - 0x2FF: Reserved */ + __RW uint32_t DBG0; /* 0x300: Description: Debug Register 0 */ + __RW uint32_t DBG1; /* 0x304: Description: Debug Register 1 */ + __R uint32_t DBGCAM; /* 0x308: Description: CAM Debug Register */ + __RW uint32_t DBGCMD; /* 0x30C: Description: Command Debug Register */ + __R uint32_t DBGSTAT; /* 0x310: Description: Status Debug Register */ + __R uint8_t RESERVED22[232]; /* 0x314 - 0x3FB: Reserved */ + __R uint32_t PSTAT; /* 0x3FC: Description: Port Status Register */ + __RW uint32_t PCCFG; /* 0x400: Description: Port Common Configuration Register */ + struct { + __RW uint32_t R; /* 0x404: Description: Port n Configuration Read Register */ + __RW uint32_t W; /* 0x408: Description: Port n Configuration Write Register */ + __RW uint32_t C; /* 0x40C: Description: Port n Common Configuration Register */ + struct { + __RW uint32_t MASKCH; /* 0x410: Description: Port n Channel m Configuration ID Mask Register */ + __RW uint32_t VALUECH; /* 0x414: Description: Port n Channel m Configuration ID Value Register */ + } ID[16]; + __RW uint32_t CTRL; /* 0x490: Description: Port n Control Register */ + __RW uint32_t QOS0; /* 0x494: Description: Port n Read QoS Configuration Register 0 */ + __RW uint32_t QOS1; /* 0x498: Description: Port n Read QoS Configuration Register 1 */ + __RW uint32_t WQOS0; /* 0x49C: Description: Port n Write QoS Configuration Register 0 */ + __RW uint32_t WQOS1; /* 0x4A0: Description: Port n Write QoS Configuration Register 1 */ + __R uint8_t RESERVED0[16]; /* 0x4A4 - 0x4B3: Reserved */ + } PCFG[16]; + struct { + __RW uint32_t BASE; /* 0xF04: Description: SAR Base Address Register n */ + __RW uint32_t SIZE; /* 0xF08: Description: SAR Size Register n */ + } SAR[4]; + __RW uint32_t SBRCTL; /* 0xF24: Description: Scrubber Control Register */ + __R uint32_t SBRSTAT; /* 0xF28: Description: Scrubber Status Register */ + __RW uint32_t SBRWDATA0; /* 0xF2C: Description: Scrubber Write Data Pattern0 */ + __R uint8_t RESERVED23[4]; /* 0xF30 - 0xF33: Reserved */ +} DDRCTL_Type; + + +/* Bitfield definition for register: MSTR */ +/* + * ACTIVE_RANKS (R/W) + * + * Description: Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations, only bits[25:24] are present. + * 1 - populated + * 0 - unpopulated + * LSB is the lowest rank number. + * For 2 ranks following combinations are legal: + * 01 - One rank + * 11 - Two ranks + * Others - Reserved. + * For 4 ranks following combinations are legal: + * 0001 - One rank + * 0011 - Two ranks + * 1111 - Four ranks + * Value After Reset: "(MEMC_NUM_RANKS==4) ? 0xF + * :((MEMC_NUM_RANKS==2) ? 0x3 : 0x1)" + * Exists: MEMC_NUM_RANKS>1 + */ +#define DDRCTL_MSTR_ACTIVE_RANKS_MASK (0xF000000UL) +#define DDRCTL_MSTR_ACTIVE_RANKS_SHIFT (24U) +#define DDRCTL_MSTR_ACTIVE_RANKS_SET(x) (((uint32_t)(x) << DDRCTL_MSTR_ACTIVE_RANKS_SHIFT) & DDRCTL_MSTR_ACTIVE_RANKS_MASK) +#define DDRCTL_MSTR_ACTIVE_RANKS_GET(x) (((uint32_t)(x) & DDRCTL_MSTR_ACTIVE_RANKS_MASK) >> DDRCTL_MSTR_ACTIVE_RANKS_SHIFT) + +/* + * BURST_RDWR (R/W) + * + * Description: SDRAM burst length used: + * 0001 - Burst length of 2 (only supported for mDDR) + * 0010 - Burst length of 4 + * 0100 - Burst length of 8 + * 1000 - Burst length of 16 (only supported for mDDR and LPDDR2) + * All other values are reserved. + * This controls the burst size used to access the SDRAM. This must match the burst length mode register setting in the SDRAM. Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGTH is 8. + * Value After Reset: 0x4 + * Exists: Always + */ +#define DDRCTL_MSTR_BURST_RDWR_MASK (0xF0000UL) +#define DDRCTL_MSTR_BURST_RDWR_SHIFT (16U) +#define DDRCTL_MSTR_BURST_RDWR_SET(x) (((uint32_t)(x) << DDRCTL_MSTR_BURST_RDWR_SHIFT) & DDRCTL_MSTR_BURST_RDWR_MASK) +#define DDRCTL_MSTR_BURST_RDWR_GET(x) (((uint32_t)(x) & DDRCTL_MSTR_BURST_RDWR_MASK) >> DDRCTL_MSTR_BURST_RDWR_SHIFT) + +/* + * DLL_OFF_MODE (R/W) + * + * Description: Set to 1 when uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation. + * Set to 0 to put uMCTL2 and DRAM in DLL-on mode for normal frequency operation. + * Value After Reset: 0x0 + * Exists: MEMC_DDR3_OR_4==1 + */ +#define DDRCTL_MSTR_DLL_OFF_MODE_MASK (0x8000U) +#define DDRCTL_MSTR_DLL_OFF_MODE_SHIFT (15U) +#define DDRCTL_MSTR_DLL_OFF_MODE_SET(x) (((uint32_t)(x) << DDRCTL_MSTR_DLL_OFF_MODE_SHIFT) & DDRCTL_MSTR_DLL_OFF_MODE_MASK) +#define DDRCTL_MSTR_DLL_OFF_MODE_GET(x) (((uint32_t)(x) & DDRCTL_MSTR_DLL_OFF_MODE_MASK) >> DDRCTL_MSTR_DLL_OFF_MODE_SHIFT) + +/* + * DATA_BUS_WIDTH (R/W) + * + * Description: Selects proportion of DQ bus width that is used by the SDRAM + * 00 - Full DQ bus width to SDRAM + * 01 - Half DQ bus width to SDRAM + * 10 - Quarter DQ bus width to SDRAM + * 11 - Reserved. + * Note that half bus width mode is only supported when the SDRAM bus width is a multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus width (excluding any ECC width). + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_MSTR_DATA_BUS_WIDTH_MASK (0x3000U) +#define DDRCTL_MSTR_DATA_BUS_WIDTH_SHIFT (12U) +#define DDRCTL_MSTR_DATA_BUS_WIDTH_SET(x) (((uint32_t)(x) << DDRCTL_MSTR_DATA_BUS_WIDTH_SHIFT) & DDRCTL_MSTR_DATA_BUS_WIDTH_MASK) +#define DDRCTL_MSTR_DATA_BUS_WIDTH_GET(x) (((uint32_t)(x) & DDRCTL_MSTR_DATA_BUS_WIDTH_MASK) >> DDRCTL_MSTR_DATA_BUS_WIDTH_SHIFT) + +/* + * EN_2T_TIMING_MODE (R/W) + * + * Description: If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command + * Note: 2T timing is not supported in LPDDR2/LPDDR3 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set + * Note: 2T timing is not supported in DDR4 geardown mode. + * Value After Reset: 0x0 + * Exists: MEMC_CMD_RTN2IDLE==0 + */ +#define DDRCTL_MSTR_EN_2T_TIMING_MODE_MASK (0x400U) +#define DDRCTL_MSTR_EN_2T_TIMING_MODE_SHIFT (10U) +#define DDRCTL_MSTR_EN_2T_TIMING_MODE_SET(x) (((uint32_t)(x) << DDRCTL_MSTR_EN_2T_TIMING_MODE_SHIFT) & DDRCTL_MSTR_EN_2T_TIMING_MODE_MASK) +#define DDRCTL_MSTR_EN_2T_TIMING_MODE_GET(x) (((uint32_t)(x) & DDRCTL_MSTR_EN_2T_TIMING_MODE_MASK) >> DDRCTL_MSTR_EN_2T_TIMING_MODE_SHIFT) + +/* + * BURSTCHOP (R/W) + * + * Description: When set, enable burst-chop in DDR3/DDR4. This is only supported in full bus width mode (MSTR.data_bus_width = 00). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), burst chop is not supported, and this bit must be set to '0' + * Value After Reset: 0x0 + * Exists: MEMC_DDR3==1 || MEMC_DDR4==1 + */ +#define DDRCTL_MSTR_BURSTCHOP_MASK (0x200U) +#define DDRCTL_MSTR_BURSTCHOP_SHIFT (9U) +#define DDRCTL_MSTR_BURSTCHOP_SET(x) (((uint32_t)(x) << DDRCTL_MSTR_BURSTCHOP_SHIFT) & DDRCTL_MSTR_BURSTCHOP_MASK) +#define DDRCTL_MSTR_BURSTCHOP_GET(x) (((uint32_t)(x) & DDRCTL_MSTR_BURSTCHOP_MASK) >> DDRCTL_MSTR_BURSTCHOP_SHIFT) + +/* + * DDR3 (R/W) + * + * Description: Select DDR3 SDRAM + * 1 - DDR3 SDRAM device in use + * 0 - non-DDR3 SDRAM device in use Only present in designs that support DDR3. + * Value After Reset: "(MEMC_DDR3_EN==1) ? 0x1 : 0x0" + * Exists: MEMC_DDR3==1 + */ +#define DDRCTL_MSTR_DDR3_MASK (0x1U) +#define DDRCTL_MSTR_DDR3_SHIFT (0U) +#define DDRCTL_MSTR_DDR3_SET(x) (((uint32_t)(x) << DDRCTL_MSTR_DDR3_SHIFT) & DDRCTL_MSTR_DDR3_MASK) +#define DDRCTL_MSTR_DDR3_GET(x) (((uint32_t)(x) & DDRCTL_MSTR_DDR3_MASK) >> DDRCTL_MSTR_DDR3_SHIFT) + +/* Bitfield definition for register: STAT */ +/* + * SELFREF_TYPE (R) + * + * Description: Flags if Self Refresh is entered and if it was under Automatic Self Refresh control only or not. + * 00 - SDRAM is not in Self Refresh + * 11 - SDRAM is in Self Refresh and Self Refresh was caused by Automatic Self Refresh only + * 10 - SDRAM is in Self Refresh and Self Refresh was not caused solely under Automatic Self Refresh control. It could have been caused by Hardware Low Power Interface and/or Software (reg_ddrc_selfref_sw). + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_STAT_SELFREF_TYPE_MASK (0x30U) +#define DDRCTL_STAT_SELFREF_TYPE_SHIFT (4U) +#define DDRCTL_STAT_SELFREF_TYPE_GET(x) (((uint32_t)(x) & DDRCTL_STAT_SELFREF_TYPE_MASK) >> DDRCTL_STAT_SELFREF_TYPE_SHIFT) + +/* + * OPERATING_MODE (R) + * + * Description: Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/DDR4 support and 2-bits in all other configurations. + * non-mDDR/LPDDR2/LPDDR3 and non-DDR4 designs: + * 00 - Init + * 01 - Normal + * 10 - Power-down + * 11 - Self refresh + * mDDR/LPDDR2/LPDDR3 or DDR4 designs: + * 000 - Init + * 001 - Normal + * 010 - Power-down + * 011 - Self refresh + * 1XX - Deep power-down / Maximum Power Saving Mode + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_STAT_OPERATING_MODE_MASK (0x7U) +#define DDRCTL_STAT_OPERATING_MODE_SHIFT (0U) +#define DDRCTL_STAT_OPERATING_MODE_GET(x) (((uint32_t)(x) & DDRCTL_STAT_OPERATING_MODE_MASK) >> DDRCTL_STAT_OPERATING_MODE_SHIFT) + +/* Bitfield definition for register: MRCTRL0 */ +/* + * MR_WR (R/W) + * + * Description: Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the uMCTL2 automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power- down or MPSM operating modes. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_MRCTRL0_MR_WR_MASK (0x80000000UL) +#define DDRCTL_MRCTRL0_MR_WR_SHIFT (31U) +#define DDRCTL_MRCTRL0_MR_WR_SET(x) (((uint32_t)(x) << DDRCTL_MRCTRL0_MR_WR_SHIFT) & DDRCTL_MRCTRL0_MR_WR_MASK) +#define DDRCTL_MRCTRL0_MR_WR_GET(x) (((uint32_t)(x) & DDRCTL_MRCTRL0_MR_WR_MASK) >> DDRCTL_MRCTRL0_MR_WR_SHIFT) + +/* + * MR_ADDR (R/W) + * + * Description: Address of the mode register that is to be written to. + * 0000 - MR0 + * 0001 - MR1 + * 0010 - MR2 + * 0011 - MR3 + * 0100 - MR4 + * 0101 - MR5 + * 0110 - MR6 + * 0111 - MR7 + * Don't Care for LPDDR2/LPDDR3 (see MRCTRL1.mr_data for mode register addressing in LPDDR2/LPDDR3) + * This signal is also used for writing to control words of RDIMMs. In that case, it corresponds to the bank address bits sent to the RDIMM + * In case of DDR4, the bit[3:2] corresponds to the bank group bits. Therefore, the bit[3] as well as the bit[2:0] must be set to an appropriate value which is considered both the Address Mirroring of UDIMMs/RDIMMs and the Output Inversion of RDIMMs. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_MRCTRL0_MR_ADDR_MASK (0xF000U) +#define DDRCTL_MRCTRL0_MR_ADDR_SHIFT (12U) +#define DDRCTL_MRCTRL0_MR_ADDR_SET(x) (((uint32_t)(x) << DDRCTL_MRCTRL0_MR_ADDR_SHIFT) & DDRCTL_MRCTRL0_MR_ADDR_MASK) +#define DDRCTL_MRCTRL0_MR_ADDR_GET(x) (((uint32_t)(x) & DDRCTL_MRCTRL0_MR_ADDR_MASK) >> DDRCTL_MRCTRL0_MR_ADDR_SHIFT) + +/* + * MR_RANK (R/W) + * + * Description: Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs which implement address mirroring, it may be necessary to access ranks individually. + * Examples (assume uMCTL2 is configured for 4 ranks): + * 0x1 - select rank 0 only + * 0x2 - select rank 1 only + * 0x5 - select ranks 0 and 2 + * 0xA - select ranks 1 and 3 + * 0xF - select ranks 0, 1, 2 and 3 + * Value After Reset: "(MEMC_NUM_RANKS==4) ? 0xF + * :((MEMC_NUM_RANKS==2) ? 0x3 : 0x1)" + * Exists: Always + */ +#define DDRCTL_MRCTRL0_MR_RANK_MASK (0xF0U) +#define DDRCTL_MRCTRL0_MR_RANK_SHIFT (4U) +#define DDRCTL_MRCTRL0_MR_RANK_SET(x) (((uint32_t)(x) << DDRCTL_MRCTRL0_MR_RANK_SHIFT) & DDRCTL_MRCTRL0_MR_RANK_MASK) +#define DDRCTL_MRCTRL0_MR_RANK_GET(x) (((uint32_t)(x) & DDRCTL_MRCTRL0_MR_RANK_MASK) >> DDRCTL_MRCTRL0_MR_RANK_SHIFT) + +/* Bitfield definition for register: MRCTRL1 */ +/* + * MR_DATA (R/W) + * + * Description: Mode register write data for all non- LPDDR2/non-LPDDR3 modes. + * For LPDDR2/LPDDR3, MRCTRL1[15:0] are interpreted as [15:8] MR Address and [7:0] MR data for writes, don't care for reads. This is 18-bits wide in configurations with DDR4 support and 16-bits in all other configurations. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_MRCTRL1_MR_DATA_MASK (0x3FFFFUL) +#define DDRCTL_MRCTRL1_MR_DATA_SHIFT (0U) +#define DDRCTL_MRCTRL1_MR_DATA_SET(x) (((uint32_t)(x) << DDRCTL_MRCTRL1_MR_DATA_SHIFT) & DDRCTL_MRCTRL1_MR_DATA_MASK) +#define DDRCTL_MRCTRL1_MR_DATA_GET(x) (((uint32_t)(x) & DDRCTL_MRCTRL1_MR_DATA_MASK) >> DDRCTL_MRCTRL1_MR_DATA_SHIFT) + +/* Bitfield definition for register: MRSTAT */ +/* + * MR_WR_BUSY (R) + * + * Description: The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when 'MRSTAT.mr_wr_busy' is high. + * 0 - Indicates that the SoC core can initiate a mode register write operation + * 1 - Indicates that mode register write operation is in progress + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_MRSTAT_MR_WR_BUSY_MASK (0x1U) +#define DDRCTL_MRSTAT_MR_WR_BUSY_SHIFT (0U) +#define DDRCTL_MRSTAT_MR_WR_BUSY_GET(x) (((uint32_t)(x) & DDRCTL_MRSTAT_MR_WR_BUSY_MASK) >> DDRCTL_MRSTAT_MR_WR_BUSY_SHIFT) + +/* Bitfield definition for register: PWRCTL */ +/* + * SELFREF_SW (R/W) + * + * Description: A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. + * 1 - Software Entry to Self Refresh + * 0 - Software Exit from Self Refresh + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_PWRCTL_SELFREF_SW_MASK (0x20U) +#define DDRCTL_PWRCTL_SELFREF_SW_SHIFT (5U) +#define DDRCTL_PWRCTL_SELFREF_SW_SET(x) (((uint32_t)(x) << DDRCTL_PWRCTL_SELFREF_SW_SHIFT) & DDRCTL_PWRCTL_SELFREF_SW_MASK) +#define DDRCTL_PWRCTL_SELFREF_SW_GET(x) (((uint32_t)(x) & DDRCTL_PWRCTL_SELFREF_SW_MASK) >> DDRCTL_PWRCTL_SELFREF_SW_SHIFT) + +/* + * EN_DFI_DRAM_CLK_DISABLE (R/W) + * + * Description: Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. + * If set to 0, dfi_dram_clk_disable is never asserted. Assertion of dfi_dram_clk_disable is as follows: + * In DDR2/DDR3, can only be asserted in Self Refresh. In DDR4, can be asserted in following: + * in Self Refresh. + * in Maximum Power Saving Mode + * In mDDR/LPDDR2/LPDDR3, can be asserted in following: + * in Self Refresh + * in Power Down + * in Deep Power Down + * during Normal operation (Clock Stop) + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK (0x8U) +#define DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT (3U) +#define DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SET(x) (((uint32_t)(x) << DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT) & DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK) +#define DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_GET(x) (((uint32_t)(x) & DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK) >> DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT) + +/* + * POWERDOWN_EN (R/W) + * + * Description: If true then the uMCTL2 goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). + * This register bit may be re-programmed during the course of normal operation. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_PWRCTL_POWERDOWN_EN_MASK (0x2U) +#define DDRCTL_PWRCTL_POWERDOWN_EN_SHIFT (1U) +#define DDRCTL_PWRCTL_POWERDOWN_EN_SET(x) (((uint32_t)(x) << DDRCTL_PWRCTL_POWERDOWN_EN_SHIFT) & DDRCTL_PWRCTL_POWERDOWN_EN_MASK) +#define DDRCTL_PWRCTL_POWERDOWN_EN_GET(x) (((uint32_t)(x) & DDRCTL_PWRCTL_POWERDOWN_EN_MASK) >> DDRCTL_PWRCTL_POWERDOWN_EN_SHIFT) + +/* + * SELFREF_EN (R/W) + * + * Description: If true then the uMCTL2 puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re- programmed during the course of normal operation. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_PWRCTL_SELFREF_EN_MASK (0x1U) +#define DDRCTL_PWRCTL_SELFREF_EN_SHIFT (0U) +#define DDRCTL_PWRCTL_SELFREF_EN_SET(x) (((uint32_t)(x) << DDRCTL_PWRCTL_SELFREF_EN_SHIFT) & DDRCTL_PWRCTL_SELFREF_EN_MASK) +#define DDRCTL_PWRCTL_SELFREF_EN_GET(x) (((uint32_t)(x) & DDRCTL_PWRCTL_SELFREF_EN_MASK) >> DDRCTL_PWRCTL_SELFREF_EN_SHIFT) + +/* Bitfield definition for register: PWRTMG */ +/* + * SELFREF_TO_X32 (R/W) + * + * Description: After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into Self Refresh. This must be enabled in the PWRCTL.selfref_en. + * Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. + * Value After Reset: 0x40 + * Exists: Always + */ +#define DDRCTL_PWRTMG_SELFREF_TO_X32_MASK (0xFF0000UL) +#define DDRCTL_PWRTMG_SELFREF_TO_X32_SHIFT (16U) +#define DDRCTL_PWRTMG_SELFREF_TO_X32_SET(x) (((uint32_t)(x) << DDRCTL_PWRTMG_SELFREF_TO_X32_SHIFT) & DDRCTL_PWRTMG_SELFREF_TO_X32_MASK) +#define DDRCTL_PWRTMG_SELFREF_TO_X32_GET(x) (((uint32_t)(x) & DDRCTL_PWRTMG_SELFREF_TO_X32_MASK) >> DDRCTL_PWRTMG_SELFREF_TO_X32_SHIFT) + +/* + * POWERDOWN_TO_X32 (R/W) + * + * Description: After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into power-down. This must be enabled in the PWRCTL.powerdown_en. + * Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY. + * Value After Reset: 0x10 + * Exists: Always + */ +#define DDRCTL_PWRTMG_POWERDOWN_TO_X32_MASK (0x1FU) +#define DDRCTL_PWRTMG_POWERDOWN_TO_X32_SHIFT (0U) +#define DDRCTL_PWRTMG_POWERDOWN_TO_X32_SET(x) (((uint32_t)(x) << DDRCTL_PWRTMG_POWERDOWN_TO_X32_SHIFT) & DDRCTL_PWRTMG_POWERDOWN_TO_X32_MASK) +#define DDRCTL_PWRTMG_POWERDOWN_TO_X32_GET(x) (((uint32_t)(x) & DDRCTL_PWRTMG_POWERDOWN_TO_X32_MASK) >> DDRCTL_PWRTMG_POWERDOWN_TO_X32_SHIFT) + +/* Bitfield definition for register: HWLPCTL */ +/* + * HW_LP_IDLE_X32 (R/W) + * + * Description: Hardware idle period. The cactive_ddrc output is driven low if the system is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The hardware idle function is disabled when hw_lp_idle_x32=0. + * Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_HWLPCTL_HW_LP_IDLE_X32_MASK (0xFFF0000UL) +#define DDRCTL_HWLPCTL_HW_LP_IDLE_X32_SHIFT (16U) +#define DDRCTL_HWLPCTL_HW_LP_IDLE_X32_SET(x) (((uint32_t)(x) << DDRCTL_HWLPCTL_HW_LP_IDLE_X32_SHIFT) & DDRCTL_HWLPCTL_HW_LP_IDLE_X32_MASK) +#define DDRCTL_HWLPCTL_HW_LP_IDLE_X32_GET(x) (((uint32_t)(x) & DDRCTL_HWLPCTL_HW_LP_IDLE_X32_MASK) >> DDRCTL_HWLPCTL_HW_LP_IDLE_X32_SHIFT) + +/* + * HW_LP_EXIT_IDLE_EN (R/W) + * + * Description: When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it will not cause exit of Self-Refresh that was caused by Hardware Low Power Interface and/or Software (PWRCTL.selfref_sw). + * Value After Reset: 0x1 + * Exists: Always + */ +#define DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_MASK (0x2U) +#define DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_SHIFT (1U) +#define DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_SET(x) (((uint32_t)(x) << DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_SHIFT) & DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_MASK) +#define DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_GET(x) (((uint32_t)(x) & DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_MASK) >> DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_SHIFT) + +/* + * HW_LP_EN (R/W) + * + * Description: Enable for Hardware Low Power Interface. + * Value After Reset: 0x1 + * Exists: Always + */ +#define DDRCTL_HWLPCTL_HW_LP_EN_MASK (0x1U) +#define DDRCTL_HWLPCTL_HW_LP_EN_SHIFT (0U) +#define DDRCTL_HWLPCTL_HW_LP_EN_SET(x) (((uint32_t)(x) << DDRCTL_HWLPCTL_HW_LP_EN_SHIFT) & DDRCTL_HWLPCTL_HW_LP_EN_MASK) +#define DDRCTL_HWLPCTL_HW_LP_EN_GET(x) (((uint32_t)(x) & DDRCTL_HWLPCTL_HW_LP_EN_MASK) >> DDRCTL_HWLPCTL_HW_LP_EN_SHIFT) + +/* Bitfield definition for register: RFSHCTL0 */ +/* + * REFRESH_MARGIN (R/W) + * + * Description: Threshold value in number of clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3, internally used t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_nom_x32 will be equal to RFSHTMG.t_rfc_nom_x32. + * Unit: Multiples of 32 clocks. Value After Reset: 0x2 Exists: Always + */ +#define DDRCTL_RFSHCTL0_REFRESH_MARGIN_MASK (0xF00000UL) +#define DDRCTL_RFSHCTL0_REFRESH_MARGIN_SHIFT (20U) +#define DDRCTL_RFSHCTL0_REFRESH_MARGIN_SET(x) (((uint32_t)(x) << DDRCTL_RFSHCTL0_REFRESH_MARGIN_SHIFT) & DDRCTL_RFSHCTL0_REFRESH_MARGIN_MASK) +#define DDRCTL_RFSHCTL0_REFRESH_MARGIN_GET(x) (((uint32_t)(x) & DDRCTL_RFSHCTL0_REFRESH_MARGIN_MASK) >> DDRCTL_RFSHCTL0_REFRESH_MARGIN_SHIFT) + +/* + * REFRESH_TO_X32 (R/W) + * + * Description: If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the uMCTL2. + * FOR PERFORMANCE ONLY. + * Value After Reset: 0x10 + * Exists: Always + */ +#define DDRCTL_RFSHCTL0_REFRESH_TO_X32_MASK (0x1F000UL) +#define DDRCTL_RFSHCTL0_REFRESH_TO_X32_SHIFT (12U) +#define DDRCTL_RFSHCTL0_REFRESH_TO_X32_SET(x) (((uint32_t)(x) << DDRCTL_RFSHCTL0_REFRESH_TO_X32_SHIFT) & DDRCTL_RFSHCTL0_REFRESH_TO_X32_MASK) +#define DDRCTL_RFSHCTL0_REFRESH_TO_X32_GET(x) (((uint32_t)(x) & DDRCTL_RFSHCTL0_REFRESH_TO_X32_MASK) >> DDRCTL_RFSHCTL0_REFRESH_TO_X32_SHIFT) + +/* + * REFRESH_BURST (R/W) + * + * Description: The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. + * 0 - single refresh + * 1 - burst-of-2 refresh + * 7 - burst-of-8 refresh + * For information on burst refresh feature refer to section 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. + * For DDR2/3, the refresh is always per-rank and not per- bank. The rank refresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granuarity feature, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated updates, care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiated update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY- initiated update is complete. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_RFSHCTL0_REFRESH_BURST_MASK (0x1F0U) +#define DDRCTL_RFSHCTL0_REFRESH_BURST_SHIFT (4U) +#define DDRCTL_RFSHCTL0_REFRESH_BURST_SET(x) (((uint32_t)(x) << DDRCTL_RFSHCTL0_REFRESH_BURST_SHIFT) & DDRCTL_RFSHCTL0_REFRESH_BURST_MASK) +#define DDRCTL_RFSHCTL0_REFRESH_BURST_GET(x) (((uint32_t)(x) & DDRCTL_RFSHCTL0_REFRESH_BURST_MASK) >> DDRCTL_RFSHCTL0_REFRESH_BURST_SHIFT) + +/* Bitfield definition for register: RFSHCTL1 */ +/* + * REFRESH_TIMER1_START_VALUE_X32 (R/W) + * + * Description: Refresh timer start for rank 1 (only present in multi-rank configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to proceed. This is explained in Refresh Controls section of architecture chapter. + * Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. + * Value After Reset: 0x0 + * Exists: MEMC_NUM_RANKS>1 + */ +#define DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK (0xFFF0000UL) +#define DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT (16U) +#define DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SET(x) (((uint32_t)(x) << DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT) & DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK) +#define DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_GET(x) (((uint32_t)(x) & DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK) >> DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT) + +/* + * REFRESH_TIMER0_START_VALUE_X32 (R/W) + * + * Description: Refresh timer start for rank 0 (only present in multi-rank configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to proceed. This is explained in Refresh Controls section of architecture chapter. + * Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. + * Value After Reset: 0x0 + * Exists: MEMC_NUM_RANKS>1 + */ +#define DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK (0xFFFU) +#define DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT (0U) +#define DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SET(x) (((uint32_t)(x) << DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT) & DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK) +#define DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_GET(x) (((uint32_t)(x) & DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK) >> DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT) + +/* Bitfield definition for register: RFSHCTL3 */ +/* + * REFRESH_UPDATE_LEVEL (R/W) + * + * Description: Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. + * The value is automatically updated when exiting soft reset, so it does not need to be toggled initially. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK (0x2U) +#define DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT (1U) +#define DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_SET(x) (((uint32_t)(x) << DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT) & DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK) +#define DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_GET(x) (((uint32_t)(x) & DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK) >> DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT) + +/* + * DIS_AUTO_REFRESH (R/W) + * + * Description: When '1', disable auto-refresh generated by the uMCTL2. When auto-refresh is disabled, the SoC core must generate refreshes using the registers reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. + * When dis_auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the uMCTL2. + * If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto- refresh is not supported, and this bit must be set to '0'. + * This register field is changeable on the fly. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_MASK (0x1U) +#define DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT (0U) +#define DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_SET(x) (((uint32_t)(x) << DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT) & DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_MASK) +#define DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_GET(x) (((uint32_t)(x) & DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_MASK) >> DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT) + +/* Bitfield definition for register: RFSHTMG */ +/* + * T_RFC_NOM_X32 (R/W) + * + * Description: tREFI: Average time interval between refreshes per rank (specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2 and LPDDR3). + * For LPDDR2/LPDDR3: + * if using all-bank refreshes (RFSHCTL0.per_bank_refresh + * = 0), this register should be set to tREFIab + * if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should be set to tREFIpb + * For configurations with MEMC_FREQ_RATIO=2, program this to (tREFI/2), no rounding up. + * In DDR4 mode, tREFI value is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value programmed in the refresh mode register. + * Note that RFSHTMG.t_rfc_nom_x32 * 32 must be greater than RFSHTMG.t_rfc_min. Unit: Multiples of 32 clocks. + * Value After Reset: 0x62 + * Exists: Always + */ +#define DDRCTL_RFSHTMG_T_RFC_NOM_X32_MASK (0xFFF0000UL) +#define DDRCTL_RFSHTMG_T_RFC_NOM_X32_SHIFT (16U) +#define DDRCTL_RFSHTMG_T_RFC_NOM_X32_SET(x) (((uint32_t)(x) << DDRCTL_RFSHTMG_T_RFC_NOM_X32_SHIFT) & DDRCTL_RFSHTMG_T_RFC_NOM_X32_MASK) +#define DDRCTL_RFSHTMG_T_RFC_NOM_X32_GET(x) (((uint32_t)(x) & DDRCTL_RFSHTMG_T_RFC_NOM_X32_MASK) >> DDRCTL_RFSHTMG_T_RFC_NOM_X32_SHIFT) + +/* + * T_RFC_MIN (R/W) + * + * Description: tRFC (min): Minimum time from refresh to refresh or activate. + * For LPDDR2/LPDDR3: + * if using all-bank refreshes (RFSHCTL0.per_bank_refresh + * = 0), this register should be set to tRFCab + * if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should be set to tRFCpb + * For configurations with MEMC_FREQ_RATIO=2, program this to tRFC(min)/2 and round up to next integer value. + * In DDR4 mode, tRFC(min) value is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the appropriate value from the spec based on the 'refresh_mode' and the device density that is used. + * Unit: Clocks. + * Value After Reset: 0x8c + * Exists: Always + */ +#define DDRCTL_RFSHTMG_T_RFC_MIN_MASK (0x1FFU) +#define DDRCTL_RFSHTMG_T_RFC_MIN_SHIFT (0U) +#define DDRCTL_RFSHTMG_T_RFC_MIN_SET(x) (((uint32_t)(x) << DDRCTL_RFSHTMG_T_RFC_MIN_SHIFT) & DDRCTL_RFSHTMG_T_RFC_MIN_MASK) +#define DDRCTL_RFSHTMG_T_RFC_MIN_GET(x) (((uint32_t)(x) & DDRCTL_RFSHTMG_T_RFC_MIN_MASK) >> DDRCTL_RFSHTMG_T_RFC_MIN_SHIFT) + +/* Bitfield definition for register: ECCUADDR0 */ +/* + * ECC_UNCORR_RANK (R) + * + * Description: Rank number of a read resulting in an uncorrected ECC error + * Value After Reset: 0x0 + * Exists: MEMC_NUM_RANKS>1 + */ +#define DDRCTL_ECCUADDR0_ECC_UNCORR_RANK_MASK (0x3000000UL) +#define DDRCTL_ECCUADDR0_ECC_UNCORR_RANK_SHIFT (24U) +#define DDRCTL_ECCUADDR0_ECC_UNCORR_RANK_GET(x) (((uint32_t)(x) & DDRCTL_ECCUADDR0_ECC_UNCORR_RANK_MASK) >> DDRCTL_ECCUADDR0_ECC_UNCORR_RANK_SHIFT) + +/* + * ECC_UNCORR_ROW (R) + * + * Description: Page/row number of a read resulting in an uncorrected ECC error. This is 18-bits wide in configurations with DDR4 support and 16-bits in all other configurations. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_ECCUADDR0_ECC_UNCORR_ROW_MASK (0x3FFFFUL) +#define DDRCTL_ECCUADDR0_ECC_UNCORR_ROW_SHIFT (0U) +#define DDRCTL_ECCUADDR0_ECC_UNCORR_ROW_GET(x) (((uint32_t)(x) & DDRCTL_ECCUADDR0_ECC_UNCORR_ROW_MASK) >> DDRCTL_ECCUADDR0_ECC_UNCORR_ROW_SHIFT) + +/* Bitfield definition for register: CRCPARCTL0 */ +/* + * DFI_ALERT_ERR_CNT_CLR (R/W1C) + * + * Description: DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit will clear the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the uMCTL2 automatically clears this bit. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_MASK (0x4U) +#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_SHIFT (2U) +#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_SET(x) (((uint32_t)(x) << DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_SHIFT) & DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_MASK) +#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_GET(x) (((uint32_t)(x) & DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_MASK) >> DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_SHIFT) + +/* + * DFI_ALERT_ERR_INT_CLR (R/W1C) + * + * Description: Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int will be cleared. When the clear operation is complete, the uMCTL2 automatically clears this bit. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_MASK (0x2U) +#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_SHIFT (1U) +#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_SET(x) (((uint32_t)(x) << DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_SHIFT) & DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_MASK) +#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_GET(x) (((uint32_t)(x) & DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_MASK) >> DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_SHIFT) + +/* + * DFI_ALERT_ERR_INT_EN (R/W) + * + * Description: Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input will result in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_MASK (0x1U) +#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_SHIFT (0U) +#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_SET(x) (((uint32_t)(x) << DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_SHIFT) & DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_MASK) +#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_GET(x) (((uint32_t)(x) & DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_MASK) >> DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_SHIFT) + +/* Bitfield definition for register: CRCPARSTAT */ +/* + * DFI_ALERT_ERR_INT (R) + * + * Description: DFI alert error interrupt. + * If a parity/CRC error is detected on dfi_alert_n, and the interrupt is enabled by CRCPARCTL0.dfi_alert_err_int_en, this interrupt bit will be set. It will remain set until cleared by CRCPARCTL0.dfi_alert_err_int_clr + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_INT_MASK (0x10000UL) +#define DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_INT_SHIFT (16U) +#define DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_INT_GET(x) (((uint32_t)(x) & DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_INT_MASK) >> DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_INT_SHIFT) + +/* + * DFI_ALERT_ERR_CNT (R) + * + * Description: DFI alert error count. + * If a parity/CRC error is detected on dfi_alert_n, this counter be incremented. This is independent of the setting of CRCPARCTL0.dfi_alert_err_int_en. It will saturate at 0xFFFF, and can be cleared by asserting CRCPARCTL0.dfi_alert_err_cnt_clr. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_CNT_MASK (0xFFFFU) +#define DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_CNT_SHIFT (0U) +#define DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_CNT_GET(x) (((uint32_t)(x) & DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_CNT_MASK) >> DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_CNT_SHIFT) + +/* Bitfield definition for register: INIT0 */ +/* + * SKIP_DRAM_INIT (R/W) + * + * Description: If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed + * 00 - SDRAM Intialization routine is run after power-up + * 01 - SDRAM Intialization routine is skipped after power- up. Controller starts up in Normal Mode + * 11 - SDRAM Intialization routine is skipped after power- up. Controller starts up in Self-refresh Mode + * 10 - SDRAM Intialization routine is run after power-up. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_INIT0_SKIP_DRAM_INIT_MASK (0xC0000000UL) +#define DDRCTL_INIT0_SKIP_DRAM_INIT_SHIFT (30U) +#define DDRCTL_INIT0_SKIP_DRAM_INIT_SET(x) (((uint32_t)(x) << DDRCTL_INIT0_SKIP_DRAM_INIT_SHIFT) & DDRCTL_INIT0_SKIP_DRAM_INIT_MASK) +#define DDRCTL_INIT0_SKIP_DRAM_INIT_GET(x) (((uint32_t)(x) & DDRCTL_INIT0_SKIP_DRAM_INIT_MASK) >> DDRCTL_INIT0_SKIP_DRAM_INIT_SHIFT) + +/* + * POST_CKE_X1024 (R/W) + * + * Description: Cycles to wait after driving CKE high to start the SDRAM initialization sequence. + * Unit: 1024 clocks. + * DDR2 typically requires a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. + * LPDDR2/LPDDR3 typically requires this to be programmed for a delay of 200 us. + * For configurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it up to next integer value. + * Value After Reset: 0x2 + * Exists: Always + */ +#define DDRCTL_INIT0_POST_CKE_X1024_MASK (0x3FF0000UL) +#define DDRCTL_INIT0_POST_CKE_X1024_SHIFT (16U) +#define DDRCTL_INIT0_POST_CKE_X1024_SET(x) (((uint32_t)(x) << DDRCTL_INIT0_POST_CKE_X1024_SHIFT) & DDRCTL_INIT0_POST_CKE_X1024_MASK) +#define DDRCTL_INIT0_POST_CKE_X1024_GET(x) (((uint32_t)(x) & DDRCTL_INIT0_POST_CKE_X1024_MASK) >> DDRCTL_INIT0_POST_CKE_X1024_SHIFT) + +/* + * PRE_CKE_X1024 (R/W) + * + * Description: Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. + * Unit: 1024 clock cycles. + * DDR2 specifications typically require this to be programmed for a delay of >= 200 us. + * LPDDR2/LPDDR3: tINIT1 of 100 ns (min) + * For configurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it up to next integer value. + * Value After Reset: 0x4e + * Exists: Always + */ +#define DDRCTL_INIT0_PRE_CKE_X1024_MASK (0x3FFU) +#define DDRCTL_INIT0_PRE_CKE_X1024_SHIFT (0U) +#define DDRCTL_INIT0_PRE_CKE_X1024_SET(x) (((uint32_t)(x) << DDRCTL_INIT0_PRE_CKE_X1024_SHIFT) & DDRCTL_INIT0_PRE_CKE_X1024_MASK) +#define DDRCTL_INIT0_PRE_CKE_X1024_GET(x) (((uint32_t)(x) & DDRCTL_INIT0_PRE_CKE_X1024_MASK) >> DDRCTL_INIT0_PRE_CKE_X1024_SHIFT) + +/* Bitfield definition for register: INIT1 */ +/* + * DRAM_RSTN_X1024 (R/W) + * + * Description: Number of cycles to assert SDRAM reset signal during init sequence. + * This is only present for designs supporting DDR3/DDR4 devices. For use with a Synopsys DDR PHY, this should be set to a minimum of 1 + * Value After Reset: 0x0 + * Exists: MEMC_DDR3==1 || MEMC_DDR4==1 + */ +#define DDRCTL_INIT1_DRAM_RSTN_X1024_MASK (0xFF0000UL) +#define DDRCTL_INIT1_DRAM_RSTN_X1024_SHIFT (16U) +#define DDRCTL_INIT1_DRAM_RSTN_X1024_SET(x) (((uint32_t)(x) << DDRCTL_INIT1_DRAM_RSTN_X1024_SHIFT) & DDRCTL_INIT1_DRAM_RSTN_X1024_MASK) +#define DDRCTL_INIT1_DRAM_RSTN_X1024_GET(x) (((uint32_t)(x) & DDRCTL_INIT1_DRAM_RSTN_X1024_MASK) >> DDRCTL_INIT1_DRAM_RSTN_X1024_SHIFT) + +/* + * FINAL_WAIT_X32 (R/W) + * + * Description: Cycles to wait after completing the SDRAM initialization sequence before starting the dynamic scheduler. + * Unit: Counts of a global timer that pulses every 32 clock cycles. + * There is no known specific requirement for this; it may be set to zero. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_INIT1_FINAL_WAIT_X32_MASK (0x7F00U) +#define DDRCTL_INIT1_FINAL_WAIT_X32_SHIFT (8U) +#define DDRCTL_INIT1_FINAL_WAIT_X32_SET(x) (((uint32_t)(x) << DDRCTL_INIT1_FINAL_WAIT_X32_SHIFT) & DDRCTL_INIT1_FINAL_WAIT_X32_MASK) +#define DDRCTL_INIT1_FINAL_WAIT_X32_GET(x) (((uint32_t)(x) & DDRCTL_INIT1_FINAL_WAIT_X32_MASK) >> DDRCTL_INIT1_FINAL_WAIT_X32_SHIFT) + +/* + * PRE_OCD_X32 (R/W) + * + * Description: Wait period before driving the OCD complete command to SDRAM. + * Unit: Counts of a global timer that pulses every 32 clock cycles. + * There is no known specific requirement for this; it may be set to zero. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_INIT1_PRE_OCD_X32_MASK (0xFU) +#define DDRCTL_INIT1_PRE_OCD_X32_SHIFT (0U) +#define DDRCTL_INIT1_PRE_OCD_X32_SET(x) (((uint32_t)(x) << DDRCTL_INIT1_PRE_OCD_X32_SHIFT) & DDRCTL_INIT1_PRE_OCD_X32_MASK) +#define DDRCTL_INIT1_PRE_OCD_X32_GET(x) (((uint32_t)(x) & DDRCTL_INIT1_PRE_OCD_X32_MASK) >> DDRCTL_INIT1_PRE_OCD_X32_SHIFT) + +/* Bitfield definition for register: INIT3 */ +/* + * MR (R/W) + * + * Description: DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately. + * DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. + * LPDDR2/LPDDR3 - Value to write to MR1 register + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_INIT3_MR_MASK (0xFFFF0000UL) +#define DDRCTL_INIT3_MR_SHIFT (16U) +#define DDRCTL_INIT3_MR_SET(x) (((uint32_t)(x) << DDRCTL_INIT3_MR_SHIFT) & DDRCTL_INIT3_MR_MASK) +#define DDRCTL_INIT3_MR_GET(x) (((uint32_t)(x) & DDRCTL_INIT3_MR_MASK) >> DDRCTL_INIT3_MR_SHIFT) + +/* + * EMR (R/W) + * + * Description: DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those bits appropriately. + * DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, this bit is set appropriately by the uMCTL2 during write leveling. + * mDDR: Value to write to EMR register. LPDDR2/LPDDR3 - Value to write to MR2 register Value After Reset: 0x510 + * Exists: Always + */ +#define DDRCTL_INIT3_EMR_MASK (0xFFFFU) +#define DDRCTL_INIT3_EMR_SHIFT (0U) +#define DDRCTL_INIT3_EMR_SET(x) (((uint32_t)(x) << DDRCTL_INIT3_EMR_SHIFT) & DDRCTL_INIT3_EMR_MASK) +#define DDRCTL_INIT3_EMR_GET(x) (((uint32_t)(x) & DDRCTL_INIT3_EMR_MASK) >> DDRCTL_INIT3_EMR_SHIFT) + +/* Bitfield definition for register: INIT4 */ +/* + * EMR2 (R/W) + * + * Description: DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3: Value to write to MR3 register mDDR: Unused + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_INIT4_EMR2_MASK (0xFFFF0000UL) +#define DDRCTL_INIT4_EMR2_SHIFT (16U) +#define DDRCTL_INIT4_EMR2_SET(x) (((uint32_t)(x) << DDRCTL_INIT4_EMR2_SHIFT) & DDRCTL_INIT4_EMR2_MASK) +#define DDRCTL_INIT4_EMR2_GET(x) (((uint32_t)(x) & DDRCTL_INIT4_EMR2_MASK) >> DDRCTL_INIT4_EMR2_SHIFT) + +/* + * EMR3 (R/W) + * + * Description: DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_INIT4_EMR3_MASK (0xFFFFU) +#define DDRCTL_INIT4_EMR3_SHIFT (0U) +#define DDRCTL_INIT4_EMR3_SET(x) (((uint32_t)(x) << DDRCTL_INIT4_EMR3_SHIFT) & DDRCTL_INIT4_EMR3_MASK) +#define DDRCTL_INIT4_EMR3_GET(x) (((uint32_t)(x) & DDRCTL_INIT4_EMR3_MASK) >> DDRCTL_INIT4_EMR3_SHIFT) + +/* Bitfield definition for register: INIT5 */ +/* + * DEV_ZQINIT_X32 (R/W) + * + * Description: ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. + * Unit: 32 clock cycles. + * DDR3 typically requires 512 clocks. DDR4 requires 1024 clocks. + * LPDDR2/LPDDR3 requires 1 us. + * Value After Reset: 0x10 + * Exists: MEMC_DDR3==1 || MEMC_DDR4 == 1 || MEMC_LPDDR2==1 + */ +#define DDRCTL_INIT5_DEV_ZQINIT_X32_MASK (0xFF0000UL) +#define DDRCTL_INIT5_DEV_ZQINIT_X32_SHIFT (16U) +#define DDRCTL_INIT5_DEV_ZQINIT_X32_SET(x) (((uint32_t)(x) << DDRCTL_INIT5_DEV_ZQINIT_X32_SHIFT) & DDRCTL_INIT5_DEV_ZQINIT_X32_MASK) +#define DDRCTL_INIT5_DEV_ZQINIT_X32_GET(x) (((uint32_t)(x) & DDRCTL_INIT5_DEV_ZQINIT_X32_MASK) >> DDRCTL_INIT5_DEV_ZQINIT_X32_SHIFT) + +/* Bitfield definition for register: DIMMCTL */ +/* + * DIMM_ADDR_MIRR_EN (R/W) + * + * Description: Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM implementations). + * Some UDIMMs and DDR4 RDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), + * (BG0, BG1) for the DDR4. Setting this bit ensures that, for mode register accesses during the automatic initialization routine, these bits are swapped within the uMCTL2 to compensate for this UDIMM/RDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM, they are swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. + * Note: This has no effect on the address of any other memory accesses, or of software-driven mode register accesses. + * This is not supported for mDDR, LPDDR2 or LPDDR3 SDRAMs. + * Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid, hence dimm_dis_bg_mirroring register must be set to 1. + * 1 - For odd ranks, implement address mirroring for MRS commands to during initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM implements address mirroring) + * 0 - Do not implement address mirroring + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK (0x2U) +#define DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT (1U) +#define DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_SET(x) (((uint32_t)(x) << DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT) & DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK) +#define DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_GET(x) (((uint32_t)(x) & DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK) >> DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT) + +/* + * DIMM_STAGGER_CS_EN (R/W) + * + * Description: Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIMM implementations only). This is not supported for DDR4, mDDR, LPDDR2 or LPDDR3 SDRAMs. + * 1 - Stagger accesses to even and odd ranks + * 0 - Do not stagger accesses + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_MASK (0x1U) +#define DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT (0U) +#define DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_SET(x) (((uint32_t)(x) << DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT) & DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_MASK) +#define DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_GET(x) (((uint32_t)(x) & DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_MASK) >> DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT) + +/* Bitfield definition for register: RANKCTL */ +/* + * DIFF_RANK_WR_GAP (R/W) + * + * Description: Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive writes to different ranks. + * This is used to switch the delays in the PHY to match the rank requirements. + * The value programmed in this register takes care of the ODT switch off timing requirement when switching ranks during writes. + * For configurations with MEMC_FREQ_RATIO=2, program this to (N/2) and round it up to the next integer value. N is value required by PHY, in terms of PHY clocks. + * Value After Reset: 0x6 + * Exists: MEMC_NUM_RANKS>1 + */ +#define DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_MASK (0xF00U) +#define DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_SHIFT (8U) +#define DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_SET(x) (((uint32_t)(x) << DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_SHIFT) & DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_MASK) +#define DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_GET(x) (((uint32_t)(x) & DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_MASK) >> DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_SHIFT) + +/* + * DIFF_RANK_RD_GAP (R/W) + * + * Description: Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive reads to different ranks. + * This is used to switch the delays in the PHY to match the rank requirements. + * The value programmed in this register takes care of the ODT switch off timing requirement when switching ranks during reads. + * For configurations with MEMC_FREQ_RATIO=2, program this to (N/2) and round it up to the next integer value. N is value required by PHY, in terms of PHY clocks. + * Value After Reset: 0x6 + * Exists: MEMC_NUM_RANKS>1 + */ +#define DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_MASK (0xF0U) +#define DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_SHIFT (4U) +#define DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_SET(x) (((uint32_t)(x) << DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_SHIFT) & DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_MASK) +#define DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_GET(x) (((uint32_t)(x) & DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_MASK) >> DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_SHIFT) + +/* + * MAX_RANK_RD (R/W) + * + * Description: Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to different ranks require additional gap + * dictated by the register RANKCTL.diff_rank_rd_gap. This is + * to avoid possible data bus contention as well as to give PHY enough time to switch the delay when changing ranks. The uMCTL2 arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there are few clock cycles (determined by the value on diff_rank_rd_gap register) in which only reads from the same rank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. + * This parameter represents the maximum number of reads that can be scheduled consecutively to the same rank. After this number is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness. + * This feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on the same rank as long as commands are available for it. + * Minimum programmable value is 0 (feature disabled) and maximum programmable value is 0xF. + * Feature limitation: max_rank_rd feature works as described only in the mode in which one command at the DDRC input results in one DFI command at the output. An example of this mode is: BL8 hardware configuration (MEMC_BURST_LENGTH=8) and Full bus width mode (MSTR.data_bus_width=2'b00) and BL8 mode of operation (MSTR.burst_rdwr=4'b0100). In modes where single HIF command results in multiple DFI commands (eg: Half Bus Width, BL4 etc.), the same rank commands would be serviced for as long as they are available, which is equivalent to this feature being disabled. + * FOR PERFORMANCE ONLY. + * Value After Reset: 0xf + * Exists: MEMC_NUM_RANKS>1 + */ +#define DDRCTL_RANKCTL_MAX_RANK_RD_MASK (0xFU) +#define DDRCTL_RANKCTL_MAX_RANK_RD_SHIFT (0U) +#define DDRCTL_RANKCTL_MAX_RANK_RD_SET(x) (((uint32_t)(x) << DDRCTL_RANKCTL_MAX_RANK_RD_SHIFT) & DDRCTL_RANKCTL_MAX_RANK_RD_MASK) +#define DDRCTL_RANKCTL_MAX_RANK_RD_GET(x) (((uint32_t)(x) & DDRCTL_RANKCTL_MAX_RANK_RD_MASK) >> DDRCTL_RANKCTL_MAX_RANK_RD_SHIFT) + +/* Bitfield definition for register: DRAMTMG0 */ +/* + * WR2PRE (R/W) + * + * Description: Minimum time between write and precharge to same bank. + * Unit: Clocks + * Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower frequencies where: + * WL = write latency + * BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. + * tWR = Write recovery time. This comes directly from the SDRAM specification. + * Add one extra cycle for LPDDR2/LPDDR3 for this parameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. + * For configurations with MEMC_FREQ_RATIO=2, 2T mode, divide the above value by 2 and add 1. No rounding up. + * Value After Reset: 0xf + * Exists: Always + */ +#define DDRCTL_DRAMTMG0_WR2PRE_MASK (0x7F000000UL) +#define DDRCTL_DRAMTMG0_WR2PRE_SHIFT (24U) +#define DDRCTL_DRAMTMG0_WR2PRE_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG0_WR2PRE_SHIFT) & DDRCTL_DRAMTMG0_WR2PRE_MASK) +#define DDRCTL_DRAMTMG0_WR2PRE_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG0_WR2PRE_MASK) >> DDRCTL_DRAMTMG0_WR2PRE_SHIFT) + +/* + * T_FAW (R/W) + * + * Description: tFAW Valid only when 8 or more banks(or banks x bank groups) are present. + * In 8-bank design, at most 4 banks must be activated in a rolling window of tFAW cycles. + * For configurations with MEMC_FREQ_RATIO=2, program this to (tFAW/2) and round up to next integer value. + * In a 4-bank design, set this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. + * Unit: Clocks + * Value After Reset: 0x10 + * Exists: Always + */ +#define DDRCTL_DRAMTMG0_T_FAW_MASK (0x3F0000UL) +#define DDRCTL_DRAMTMG0_T_FAW_SHIFT (16U) +#define DDRCTL_DRAMTMG0_T_FAW_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG0_T_FAW_SHIFT) & DDRCTL_DRAMTMG0_T_FAW_MASK) +#define DDRCTL_DRAMTMG0_T_FAW_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG0_T_FAW_MASK) >> DDRCTL_DRAMTMG0_T_FAW_SHIFT) + +/* + * T_RAS_MAX (R/W) + * + * Description: tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open + * Minimum value of this register is 1. Zero is invalid. + * For configurations with MEMC_FREQ_RATIO=2, program this to (tRAS(max)-1)/2. No rounding up. + * Unit: Multiples of 1024 clocks. Value After Reset: 0x1b Exists: Always + */ +#define DDRCTL_DRAMTMG0_T_RAS_MAX_MASK (0x7F00U) +#define DDRCTL_DRAMTMG0_T_RAS_MAX_SHIFT (8U) +#define DDRCTL_DRAMTMG0_T_RAS_MAX_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG0_T_RAS_MAX_SHIFT) & DDRCTL_DRAMTMG0_T_RAS_MAX_MASK) +#define DDRCTL_DRAMTMG0_T_RAS_MAX_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG0_T_RAS_MAX_MASK) >> DDRCTL_DRAMTMG0_T_RAS_MAX_SHIFT) + +/* + * T_RAS_MIN (R/W) + * + * Description: tRAS(min): Minimum time between activate and precharge to the same bank. + * For configurations with MEMC_FREQ_RATIO=2, 1T mode, program this to tRAS(min)/2. No rounding up. + * For configurations with MEMC_FREQ_RATIO=2, 2T mode, program this to (tRAS(min)/2 + 1). No rounding up of the division operation. + * Unit: Clocks + * Value After Reset: 0xf + * Exists: Always + */ +#define DDRCTL_DRAMTMG0_T_RAS_MIN_MASK (0x3FU) +#define DDRCTL_DRAMTMG0_T_RAS_MIN_SHIFT (0U) +#define DDRCTL_DRAMTMG0_T_RAS_MIN_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG0_T_RAS_MIN_SHIFT) & DDRCTL_DRAMTMG0_T_RAS_MIN_MASK) +#define DDRCTL_DRAMTMG0_T_RAS_MIN_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG0_T_RAS_MIN_MASK) >> DDRCTL_DRAMTMG0_T_RAS_MIN_SHIFT) + +/* Bitfield definition for register: DRAMTMG1 */ +/* + * T_XP (R/W) + * + * Description: tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. + * If C/A parity for DDR4 is used, set to (tXP+PL) instead. For configurations with MEMC_FREQ_RATIO=2, program this to (tXP/2) and round it up to the next integer value. + * Units: Clocks + * Value After Reset: 0x8 + * Exists: Always + */ +#define DDRCTL_DRAMTMG1_T_XP_MASK (0x1F0000UL) +#define DDRCTL_DRAMTMG1_T_XP_SHIFT (16U) +#define DDRCTL_DRAMTMG1_T_XP_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG1_T_XP_SHIFT) & DDRCTL_DRAMTMG1_T_XP_MASK) +#define DDRCTL_DRAMTMG1_T_XP_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG1_T_XP_MASK) >> DDRCTL_DRAMTMG1_T_XP_SHIFT) + +/* + * RD2PRE (R/W) + * + * Description: tRTP: Minimum time from read to precharge of same bank. + * DDR2: tAL + BL/2 + max(tRTP, 2) - 2 + * DDR3: tAL + max (tRTP, 4) + * DDR4: Max of following two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. + * mDDR: BL/2 + * LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. + * LPDDR3: BL/2 + max(tRTP,4) - 4 + * For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. + * For configurations with MEMC_FREQ_RATIO=2, 2T mode, divide the above value by 2 and add 1. No rounding up of division operation. + * Unit: Clocks. + * Value After Reset: 0x4 + * Exists: Always + */ +#define DDRCTL_DRAMTMG1_RD2PRE_MASK (0x1F00U) +#define DDRCTL_DRAMTMG1_RD2PRE_SHIFT (8U) +#define DDRCTL_DRAMTMG1_RD2PRE_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG1_RD2PRE_SHIFT) & DDRCTL_DRAMTMG1_RD2PRE_MASK) +#define DDRCTL_DRAMTMG1_RD2PRE_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG1_RD2PRE_MASK) >> DDRCTL_DRAMTMG1_RD2PRE_SHIFT) + +/* + * T_RC (R/W) + * + * Description: tRC: Minimum time between activates to same bank. + * For configurations with MEMC_FREQ_RATIO=2, program this to (tRC/2) and round up to next integer value. + * Unit: Clocks. + * Value After Reset: 0x14 + * Exists: Always + */ +#define DDRCTL_DRAMTMG1_T_RC_MASK (0x7FU) +#define DDRCTL_DRAMTMG1_T_RC_SHIFT (0U) +#define DDRCTL_DRAMTMG1_T_RC_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG1_T_RC_SHIFT) & DDRCTL_DRAMTMG1_T_RC_MASK) +#define DDRCTL_DRAMTMG1_T_RC_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG1_T_RC_MASK) >> DDRCTL_DRAMTMG1_T_RC_SHIFT) + +/* Bitfield definition for register: DRAMTMG2 */ +/* + * RD2WR (R/W) + * + * Description: DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL + * LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL. + * Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. + * Unit: Clocks. Where: + * WL = write latency + * BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM + * RL = read latency = CAS latency + * WR_PREAMBLE = write preamble. This is unique to DDR4. + * For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer. + * Value After Reset: 0x6 + * Exists: Always + */ +#define DDRCTL_DRAMTMG2_RD2WR_MASK (0x1F00U) +#define DDRCTL_DRAMTMG2_RD2WR_SHIFT (8U) +#define DDRCTL_DRAMTMG2_RD2WR_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG2_RD2WR_SHIFT) & DDRCTL_DRAMTMG2_RD2WR_MASK) +#define DDRCTL_DRAMTMG2_RD2WR_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG2_RD2WR_MASK) >> DDRCTL_DRAMTMG2_RD2WR_SHIFT) + +/* + * WR2RD (R/W) + * + * Description: DDR4: WL + BL/2 + tWTR_L Others: WL + BL/2 + tWTR + * In DDR4, minimum time from write command to read command for same bank group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and global constraints. + * Unit: Clocks. Where: + * WL = write latency + * BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM + * tWTR_L = internal write to read command delay for same bank group. This comes directly from the SDRAM specification. + * tWTR = internal write to read command delay. This comes directly from the SDRAM specification. + * Add one extra cycle for LPDDR2/LPDDR3 operation. + * For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer. + * Value After Reset: 0xd + * Exists: Always + */ +#define DDRCTL_DRAMTMG2_WR2RD_MASK (0x3FU) +#define DDRCTL_DRAMTMG2_WR2RD_SHIFT (0U) +#define DDRCTL_DRAMTMG2_WR2RD_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG2_WR2RD_SHIFT) & DDRCTL_DRAMTMG2_WR2RD_MASK) +#define DDRCTL_DRAMTMG2_WR2RD_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG2_WR2RD_MASK) >> DDRCTL_DRAMTMG2_WR2RD_SHIFT) + +/* Bitfield definition for register: DRAMTMG3 */ +/* + * T_MRD (R/W) + * + * Description: tMRD: Cycles between load mode commands. If MEMC_DDR3_OR_4 = 0, this parameter is also used to define the cycles between load mode command and following non-load mode command. + * For configurations with MEMC_FREQ_RATIO=2, program this to (tMRD/2) and round it up to the next integer value. + * If C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead + * Value After Reset: 0x4 + * Exists: Always + */ +#define DDRCTL_DRAMTMG3_T_MRD_MASK (0x3F000UL) +#define DDRCTL_DRAMTMG3_T_MRD_SHIFT (12U) +#define DDRCTL_DRAMTMG3_T_MRD_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG3_T_MRD_SHIFT) & DDRCTL_DRAMTMG3_T_MRD_MASK) +#define DDRCTL_DRAMTMG3_T_MRD_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG3_T_MRD_MASK) >> DDRCTL_DRAMTMG3_T_MRD_SHIFT) + +/* + * T_MOD (R/W) + * + * Description: tMOD: Present if MEMC_DDR3_OR_4 = 1. Cycles between load mode command and following non-load mode command. This is required to be programmed even when a design that supports DDR3/4 is running in DDR2 mode. + * If C/A parity for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead + * Set to tMOD if MEMC_FREQ_RATIO=1, or tMOD/2 (rounded up to next integer) if MEMC_FREQ_RATIO=2. Note that if using RDIMM, depending on the PHY, it may be necessary to use a value of tMOD + 1 or (tMOD + 1)/2 to compensate for the extra cycle of latency applied to mode register writes by the RDIMM chip + * Value After Reset: "(MEMC_DDR3_EN==1 || MEMC_DDR4_EN==1 ) ? 0xc : 0x0" + * Exists: MEMC_DDR3==1 || MEMC_DDR4==1 + */ +#define DDRCTL_DRAMTMG3_T_MOD_MASK (0x3FFU) +#define DDRCTL_DRAMTMG3_T_MOD_SHIFT (0U) +#define DDRCTL_DRAMTMG3_T_MOD_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG3_T_MOD_SHIFT) & DDRCTL_DRAMTMG3_T_MOD_MASK) +#define DDRCTL_DRAMTMG3_T_MOD_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG3_T_MOD_MASK) >> DDRCTL_DRAMTMG3_T_MOD_SHIFT) + +/* Bitfield definition for register: DRAMTMG4 */ +/* + * T_RCD (R/W) + * + * Description: tRCD - tAL: Minimum time from activate to read or write command to same bank. + * For configurations with MEMC_FREQ_RATIO=2, program this to ((tRCD - tAL)/2) and round it up to the next integer value. + * Minimum value allowed for this register is 1, which implies minimum (tRCD - tAL) value to be 2 in configurations with MEMC_FREQ_RATIO=2. + * Unit: Clocks. + * Value After Reset: 0x5 + * Exists: Always + */ +#define DDRCTL_DRAMTMG4_T_RCD_MASK (0x1F000000UL) +#define DDRCTL_DRAMTMG4_T_RCD_SHIFT (24U) +#define DDRCTL_DRAMTMG4_T_RCD_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG4_T_RCD_SHIFT) & DDRCTL_DRAMTMG4_T_RCD_MASK) +#define DDRCTL_DRAMTMG4_T_RCD_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG4_T_RCD_MASK) >> DDRCTL_DRAMTMG4_T_RCD_SHIFT) + +/* + * T_CCD (R/W) + * + * Description: DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum time between two reads + * or two writes. + * For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. + * Unit: clocks. + * Value After Reset: 0x4 + * Exists: Always + */ +#define DDRCTL_DRAMTMG4_T_CCD_MASK (0x70000UL) +#define DDRCTL_DRAMTMG4_T_CCD_SHIFT (16U) +#define DDRCTL_DRAMTMG4_T_CCD_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG4_T_CCD_SHIFT) & DDRCTL_DRAMTMG4_T_CCD_MASK) +#define DDRCTL_DRAMTMG4_T_CCD_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG4_T_CCD_MASK) >> DDRCTL_DRAMTMG4_T_CCD_SHIFT) + +/* + * T_RRD (R/W) + * + * Description: DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. Others: tRRD: Minimum time between activates from bank + * "a" to bank "b" + * For configurations with MEMC_FREQ_RATIO=2, program this to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. + * Unit: Clocks. + * Value After Reset: 0x4 + * Exists: Always + */ +#define DDRCTL_DRAMTMG4_T_RRD_MASK (0xF00U) +#define DDRCTL_DRAMTMG4_T_RRD_SHIFT (8U) +#define DDRCTL_DRAMTMG4_T_RRD_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG4_T_RRD_SHIFT) & DDRCTL_DRAMTMG4_T_RRD_MASK) +#define DDRCTL_DRAMTMG4_T_RRD_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG4_T_RRD_MASK) >> DDRCTL_DRAMTMG4_T_RRD_SHIFT) + +/* + * T_RP (R/W) + * + * Description: tRP: Minimum time from precharge to activate of same bank. + * For configurations with MEMC_FREQ_RATIO=2, program this to (tRP/2 + 1). No round up of the fraction. + * Unit: Clocks. + * Value After Reset: 0x5 + * Exists: Always + */ +#define DDRCTL_DRAMTMG4_T_RP_MASK (0x1FU) +#define DDRCTL_DRAMTMG4_T_RP_SHIFT (0U) +#define DDRCTL_DRAMTMG4_T_RP_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG4_T_RP_SHIFT) & DDRCTL_DRAMTMG4_T_RP_MASK) +#define DDRCTL_DRAMTMG4_T_RP_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG4_T_RP_MASK) >> DDRCTL_DRAMTMG4_T_RP_SHIFT) + +/* Bitfield definition for register: DRAMTMG5 */ +/* + * T_CKSRX (R/W) + * + * Description: This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. + * Recommended settings: + * mDDR: 1 + * LPDDR2: 2 + * LPDDR3: 2 + * DDR2: 1 + * DDR3: tCKSRX + * DDR4: tCKSRX + * For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next integer. + * Value After Reset: 0x5 + * Exists: Always + */ +#define DDRCTL_DRAMTMG5_T_CKSRX_MASK (0xF000000UL) +#define DDRCTL_DRAMTMG5_T_CKSRX_SHIFT (24U) +#define DDRCTL_DRAMTMG5_T_CKSRX_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG5_T_CKSRX_SHIFT) & DDRCTL_DRAMTMG5_T_CKSRX_MASK) +#define DDRCTL_DRAMTMG5_T_CKSRX_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG5_T_CKSRX_MASK) >> DDRCTL_DRAMTMG5_T_CKSRX_SHIFT) + +/* + * T_CKSRE (R/W) + * + * Description: This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. + * Recommended settings: + * mDDR: 0 + * LPDDR2: 2 + * LPDDR3: 2 + * DDR2: 1 + * DDR3: max (10 ns, 5 tCK) + * DDR4: max (10 ns, 5 tCK) + * For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next integer. + * Value After Reset: 0x5 + * Exists: Always + */ +#define DDRCTL_DRAMTMG5_T_CKSRE_MASK (0xF0000UL) +#define DDRCTL_DRAMTMG5_T_CKSRE_SHIFT (16U) +#define DDRCTL_DRAMTMG5_T_CKSRE_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG5_T_CKSRE_SHIFT) & DDRCTL_DRAMTMG5_T_CKSRE_MASK) +#define DDRCTL_DRAMTMG5_T_CKSRE_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG5_T_CKSRE_MASK) >> DDRCTL_DRAMTMG5_T_CKSRE_SHIFT) + +/* + * T_CKESR (R/W) + * + * Description: Minimum CKE low width for Self refresh entry to exit timing im memory clock cycles. + * Recommended settings: + * mDDR: tRFC + * LPDDR2: tCKESR + * LPDDR3: tCKESR + * DDR2: tCKE + * DDR3: tCKE + 1 + * DDR4: tCKE + 1 + * For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next integer. + * Value After Reset: 0x4 + * Exists: Always + */ +#define DDRCTL_DRAMTMG5_T_CKESR_MASK (0x3F00U) +#define DDRCTL_DRAMTMG5_T_CKESR_SHIFT (8U) +#define DDRCTL_DRAMTMG5_T_CKESR_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG5_T_CKESR_SHIFT) & DDRCTL_DRAMTMG5_T_CKESR_MASK) +#define DDRCTL_DRAMTMG5_T_CKESR_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG5_T_CKESR_MASK) >> DDRCTL_DRAMTMG5_T_CKESR_SHIFT) + +/* + * T_CKE (R/W) + * + * Description: Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. + * LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR + * Non-LPDDR2/non-LPDDR3 designs: Set this to tCKE value. + * For configurations with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and round it up to the next integer value. + * Unit: Clocks. + * Value After Reset: 0x3 + * Exists: Always + */ +#define DDRCTL_DRAMTMG5_T_CKE_MASK (0x1FU) +#define DDRCTL_DRAMTMG5_T_CKE_SHIFT (0U) +#define DDRCTL_DRAMTMG5_T_CKE_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG5_T_CKE_SHIFT) & DDRCTL_DRAMTMG5_T_CKE_MASK) +#define DDRCTL_DRAMTMG5_T_CKE_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG5_T_CKE_MASK) >> DDRCTL_DRAMTMG5_T_CKE_SHIFT) + +/* Bitfield definition for register: DRAMTMG8 */ +/* + * T_XS_DLL_X32 (R/W) + * + * Description: tXSDLL: Exit Self Refresh to commands requiring a locked DLL. + * For configurations with MEMC_FREQ_RATIO=2, program this to the above value divided by 2 and round up to next integer value. + * Unit: Multiples of 32 clocks. + * Note: In LPDDR2/LPDDR3/Mobile DDR mode, t_xs_x32 and t_xs_dll_x32 must be set the same values derived from tXSR. + * Value After Reset: 0x44 + * Exists: Always + */ +#define DDRCTL_DRAMTMG8_T_XS_DLL_X32_MASK (0x7F00U) +#define DDRCTL_DRAMTMG8_T_XS_DLL_X32_SHIFT (8U) +#define DDRCTL_DRAMTMG8_T_XS_DLL_X32_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG8_T_XS_DLL_X32_SHIFT) & DDRCTL_DRAMTMG8_T_XS_DLL_X32_MASK) +#define DDRCTL_DRAMTMG8_T_XS_DLL_X32_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG8_T_XS_DLL_X32_MASK) >> DDRCTL_DRAMTMG8_T_XS_DLL_X32_SHIFT) + +/* + * T_XS_X32 (R/W) + * + * Description: tXS: Exit Self Refresh to commands not requiring a locked DLL. + * For configurations with MEMC_FREQ_RATIO=2, program this to the above value divided by 2 and round up to next integer value. + * Unit: Multiples of 32 clocks. + * Note: In LPDDR2/LPDDR3/Mobile DDR mode, t_xs_x32 and t_xs_dll_x32 must be set the same values derived from tXSR. + * Value After Reset: 0x5 + * Exists: Always + */ +#define DDRCTL_DRAMTMG8_T_XS_X32_MASK (0x7FU) +#define DDRCTL_DRAMTMG8_T_XS_X32_SHIFT (0U) +#define DDRCTL_DRAMTMG8_T_XS_X32_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG8_T_XS_X32_SHIFT) & DDRCTL_DRAMTMG8_T_XS_X32_MASK) +#define DDRCTL_DRAMTMG8_T_XS_X32_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG8_T_XS_X32_MASK) >> DDRCTL_DRAMTMG8_T_XS_X32_SHIFT) + +/* Bitfield definition for register: ZQCTL0 */ +/* + * DIS_AUTO_ZQ (R/W) + * + * Description: + * 1 - Disable uMCTL2 generation of ZQCS command. Register reg_ddrc_zq_calib_short can be used instead to control ZQ calibration commands. + * 0 - Internally generate ZQCS commands based on ZQCTL1.t_zq_short_interval_x1024. + * This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 devices. + * Value After Reset: 0x0 + * Exists: MEMC_DDR3==1 || MEMC_DDR4==1 || MEMC_LPDDR2==1 + */ +#define DDRCTL_ZQCTL0_DIS_AUTO_ZQ_MASK (0x80000000UL) +#define DDRCTL_ZQCTL0_DIS_AUTO_ZQ_SHIFT (31U) +#define DDRCTL_ZQCTL0_DIS_AUTO_ZQ_SET(x) (((uint32_t)(x) << DDRCTL_ZQCTL0_DIS_AUTO_ZQ_SHIFT) & DDRCTL_ZQCTL0_DIS_AUTO_ZQ_MASK) +#define DDRCTL_ZQCTL0_DIS_AUTO_ZQ_GET(x) (((uint32_t)(x) & DDRCTL_ZQCTL0_DIS_AUTO_ZQ_MASK) >> DDRCTL_ZQCTL0_DIS_AUTO_ZQ_SHIFT) + +/* + * DIS_SRX_ZQCL (R/W) + * + * Description: + * 1 - Disable issuing of ZQCL command at Self-Refresh exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 mode. + * 0 - Enable issuing of ZQCL command at Self-Refresh exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 mode. + * This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 devices. + * Value After Reset: 0x0 + * Exists: MEMC_DDR3==1 || MEMC_DDR4==1 || MEMC_LPDDR2==1 + */ +#define DDRCTL_ZQCTL0_DIS_SRX_ZQCL_MASK (0x40000000UL) +#define DDRCTL_ZQCTL0_DIS_SRX_ZQCL_SHIFT (30U) +#define DDRCTL_ZQCTL0_DIS_SRX_ZQCL_SET(x) (((uint32_t)(x) << DDRCTL_ZQCTL0_DIS_SRX_ZQCL_SHIFT) & DDRCTL_ZQCTL0_DIS_SRX_ZQCL_MASK) +#define DDRCTL_ZQCTL0_DIS_SRX_ZQCL_GET(x) (((uint32_t)(x) & DDRCTL_ZQCTL0_DIS_SRX_ZQCL_MASK) >> DDRCTL_ZQCTL0_DIS_SRX_ZQCL_SHIFT) + +/* + * ZQ_RESISTOR_SHARED (R/W) + * + * Description: + * 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS timing met between commands so that commands to different ranks do not overlap. + * 0 - ZQ resistor is not shared. + * This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 devices. + * Value After Reset: 0x0 + * Exists: MEMC_DDR3==1 || MEMC_DDR4==1 || MEMC_LPDDR2==1 + */ +#define DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_MASK (0x20000000UL) +#define DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT (29U) +#define DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_SET(x) (((uint32_t)(x) << DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT) & DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_MASK) +#define DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_GET(x) (((uint32_t)(x) & DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_MASK) >> DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT) + +/* + * T_ZQ_LONG_NOP (R/W) + * + * Description: tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to SDRAM. + * For configurations with MEMC_FREQ_RATIO=2: DDR3/DDR4: program this to tZQoper/2 and round it up to the next integer value. + * LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer value. + * Unit: Clock cycles. + * This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 devices. + * Value After Reset: 0x200 + * Exists: MEMC_DDR3==1 || MEMC_DDR4==1 || MEMC_LPDDR2==1 + */ +#define DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_MASK (0x3FF0000UL) +#define DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_SHIFT (16U) +#define DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_SET(x) (((uint32_t)(x) << DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_SHIFT) & DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_MASK) +#define DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_GET(x) (((uint32_t)(x) & DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_MASK) >> DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_SHIFT) + +/* + * T_ZQ_SHORT_NOP (R/W) + * + * Description: tZQCS: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to SDRAM. + * For configurations with MEMC_FREQ_RATIO=2, program this to tZQCS/2 and round it up to the next integer value. Unit: Clock cycles. + * This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 devices. + * Value After Reset: 0x40 + * Exists: MEMC_DDR3==1 || MEMC_DDR4==1 || MEMC_LPDDR2==1 + */ +#define DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_MASK (0x3FFU) +#define DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT (0U) +#define DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_SET(x) (((uint32_t)(x) << DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT) & DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_MASK) +#define DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_GET(x) (((uint32_t)(x) & DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_MASK) >> DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT) + +/* Bitfield definition for register: ZQCTL1 */ +/* + * T_ZQ_SHORT_INTERVAL_X1024 (R/W) + * + * Description: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3/DDR4/LPDDR2/LPDDR3 devices. + * Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles. + * This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 devices. + * Value After Reset: 0x100 + * Exists: MEMC_DDR3==1 || MEMC_DDR4==1 || MEMC_LPDDR2==1 + */ +#define DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK (0xFFFFFUL) +#define DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT (0U) +#define DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SET(x) (((uint32_t)(x) << DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT) & DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK) +#define DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_GET(x) (((uint32_t)(x) & DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK) >> DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT) + +/* Bitfield definition for register: ZQSTAT */ +/* + * ZQ_RESET_BUSY (R) + * + * Description: SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. + * 0 - Indicates that the SoC core can initiate a ZQ Reset operation + * 1 - Indicates that ZQ Reset operation is in progress + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_ZQSTAT_ZQ_RESET_BUSY_MASK (0x1U) +#define DDRCTL_ZQSTAT_ZQ_RESET_BUSY_SHIFT (0U) +#define DDRCTL_ZQSTAT_ZQ_RESET_BUSY_GET(x) (((uint32_t)(x) & DDRCTL_ZQSTAT_ZQ_RESET_BUSY_MASK) >> DDRCTL_ZQSTAT_ZQ_RESET_BUSY_SHIFT) + +/* Bitfield definition for register: DFITMG0 */ +/* + * DFI_T_CTRL_DELAY (R/W) + * + * Description: Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, depending on the PHY, it may be necessary to increment this parameter by 1. This is to compensate for the extra cycle of latency through the RDIMM + * Value After Reset: 0x7 + * Exists: Always + */ +#define DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_MASK (0x1F000000UL) +#define DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_SHIFT (24U) +#define DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_SET(x) (((uint32_t)(x) << DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_SHIFT) & DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_MASK) +#define DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_GET(x) (((uint32_t)(x) & DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_MASK) >> DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_SHIFT) + +/* + * DFI_RDDATA_USE_SDR (R/W) + * + * Description: Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: + * 0 in terms of HDR clock cycles + * 1 in terms of SDR clock cycles + * Refer to PHY specification for correct value. + * Value After Reset: 0x0 + * Exists: MEMC_FREQ_RATIO==2 + */ +#define DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_MASK (0x800000UL) +#define DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT (23U) +#define DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_SET(x) (((uint32_t)(x) << DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT) & DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_MASK) +#define DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_GET(x) (((uint32_t)(x) & DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_MASK) >> DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT) + +/* + * DFI_T_RDDATA_EN (R/W) + * + * Description: Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. + * This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle of latency through the RDIMM. + * Unit: Clocks + * Value After Reset: 0x2 + * Exists: Always + */ +#define DDRCTL_DFITMG0_DFI_T_RDDATA_EN_MASK (0x3F0000UL) +#define DDRCTL_DFITMG0_DFI_T_RDDATA_EN_SHIFT (16U) +#define DDRCTL_DFITMG0_DFI_T_RDDATA_EN_SET(x) (((uint32_t)(x) << DDRCTL_DFITMG0_DFI_T_RDDATA_EN_SHIFT) & DDRCTL_DFITMG0_DFI_T_RDDATA_EN_MASK) +#define DDRCTL_DFITMG0_DFI_T_RDDATA_EN_GET(x) (((uint32_t)(x) & DDRCTL_DFITMG0_DFI_T_RDDATA_EN_MASK) >> DDRCTL_DFITMG0_DFI_T_RDDATA_EN_SHIFT) + +/* + * DFI_WRDATA_USE_SDR (R/W) + * + * Description: Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or HDR clock cycles + * 0 in terms of HDR clock cycles + * 1 in terms of SDR clock cycles + * Refer to PHY specification for correct value. + * Value After Reset: 0x0 + * Exists: MEMC_FREQ_RATIO==2 + */ +#define DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_MASK (0x8000U) +#define DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT (15U) +#define DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_SET(x) (((uint32_t)(x) << DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT) & DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_MASK) +#define DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_GET(x) (((uint32_t)(x) & DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_MASK) >> DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT) + +/* + * DFI_TPHY_WRDATA (R/W) + * + * Description: Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. + * Unit: Clocks + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_DFITMG0_DFI_TPHY_WRDATA_MASK (0x3F00U) +#define DDRCTL_DFITMG0_DFI_TPHY_WRDATA_SHIFT (8U) +#define DDRCTL_DFITMG0_DFI_TPHY_WRDATA_SET(x) (((uint32_t)(x) << DDRCTL_DFITMG0_DFI_TPHY_WRDATA_SHIFT) & DDRCTL_DFITMG0_DFI_TPHY_WRDATA_MASK) +#define DDRCTL_DFITMG0_DFI_TPHY_WRDATA_GET(x) (((uint32_t)(x) & DDRCTL_DFITMG0_DFI_TPHY_WRDATA_MASK) >> DDRCTL_DFITMG0_DFI_TPHY_WRDATA_SHIFT) + +/* + * DFI_TPHY_WRLAT (R/W) + * + * Description: Write latency + * Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. The minimum supported value is as follows: + * 0 for configurations with MEMC_WL0 = 1 + * 1 for configurations with MEMC_WL0 = 0 + * Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency through the RDIMM. + * Value After Reset: 0x2 + * Exists: Always + */ +#define DDRCTL_DFITMG0_DFI_TPHY_WRLAT_MASK (0x3FU) +#define DDRCTL_DFITMG0_DFI_TPHY_WRLAT_SHIFT (0U) +#define DDRCTL_DFITMG0_DFI_TPHY_WRLAT_SET(x) (((uint32_t)(x) << DDRCTL_DFITMG0_DFI_TPHY_WRLAT_SHIFT) & DDRCTL_DFITMG0_DFI_TPHY_WRLAT_MASK) +#define DDRCTL_DFITMG0_DFI_TPHY_WRLAT_GET(x) (((uint32_t)(x) & DDRCTL_DFITMG0_DFI_TPHY_WRLAT_MASK) >> DDRCTL_DFITMG0_DFI_TPHY_WRLAT_SHIFT) + +/* Bitfield definition for register: DFITMG1 */ +/* + * DFI_T_WRDATA_DELAY (R/W) + * + * Description: Specifies the number of DFI clocks between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification for correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Value to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ_RATIO=2, divide PHY's value by 2 and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. + * Unit: Clocks + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_MASK (0x1F0000UL) +#define DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT (16U) +#define DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_SET(x) (((uint32_t)(x) << DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT) & DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_MASK) +#define DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_GET(x) (((uint32_t)(x) & DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_MASK) >> DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT) + +/* + * DFI_T_DRAM_CLK_DISABLE (R/W) + * + * Description: Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY- DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. + * Value After Reset: 0x4 + * Exists: Always + */ +#define DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK (0xF00U) +#define DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT (8U) +#define DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SET(x) (((uint32_t)(x) << DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT) & DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK) +#define DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_GET(x) (((uint32_t)(x) & DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK) >> DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT) + +/* + * DFI_T_DRAM_CLK_ENABLE (R/W) + * + * Description: Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. + * Value After Reset: 0x4 + * Exists: Always + */ +#define DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK (0xFU) +#define DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT (0U) +#define DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SET(x) (((uint32_t)(x) << DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT) & DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK) +#define DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_GET(x) (((uint32_t)(x) & DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK) >> DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT) + +/* Bitfield definition for register: DFILPCFG0 */ +/* + * DFI_TLP_RESP (R/W) + * + * Description: Setting for DFI's tlp_resp time. + * Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1 specification onwards, recommends using a fixed + * value of 7 always. + * Value After Reset: 0x7 + * Exists: Always + */ +#define DDRCTL_DFILPCFG0_DFI_TLP_RESP_MASK (0xF000000UL) +#define DDRCTL_DFILPCFG0_DFI_TLP_RESP_SHIFT (24U) +#define DDRCTL_DFILPCFG0_DFI_TLP_RESP_SET(x) (((uint32_t)(x) << DDRCTL_DFILPCFG0_DFI_TLP_RESP_SHIFT) & DDRCTL_DFILPCFG0_DFI_TLP_RESP_MASK) +#define DDRCTL_DFILPCFG0_DFI_TLP_RESP_GET(x) (((uint32_t)(x) & DDRCTL_DFILPCFG0_DFI_TLP_RESP_MASK) >> DDRCTL_DFILPCFG0_DFI_TLP_RESP_SHIFT) + +/* + * DFI_LP_WAKEUP_SR (R/W) + * + * Description: Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. + * Determines the DFI's tlp_wakeup time: + * 0x0 - 16 cycles + * 0x1 - 32 cycles + * 0x2 - 64 cycles + * 0x3 - 128 cycles + * 0x4 - 256 cycles + * 0x5 - 512 cycles + * 0x6 - 1024 cycles + * 0x7 - 2048 cycles + * 0x8 - 4096 cycles + * 0x9 - 8192 cycles + * 0xA - 16384 cycles + * 0xB - 32768 cycles + * 0xC - 65536 cycles + * 0xD - 131072 cycles + * 0xE - 262144 cycles + * 0xF - Unlimited Value After Reset: 0x0 Exists: Always + */ +#define DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK (0xF000U) +#define DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT (12U) +#define DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_SET(x) (((uint32_t)(x) << DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT) & DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK) +#define DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_GET(x) (((uint32_t)(x) & DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK) >> DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT) + +/* + * DFI_LP_EN_SR (R/W) + * + * Description: Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. + * 0 - Disabled + * 1 - Enabled + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_DFILPCFG0_DFI_LP_EN_SR_MASK (0x100U) +#define DDRCTL_DFILPCFG0_DFI_LP_EN_SR_SHIFT (8U) +#define DDRCTL_DFILPCFG0_DFI_LP_EN_SR_SET(x) (((uint32_t)(x) << DDRCTL_DFILPCFG0_DFI_LP_EN_SR_SHIFT) & DDRCTL_DFILPCFG0_DFI_LP_EN_SR_MASK) +#define DDRCTL_DFILPCFG0_DFI_LP_EN_SR_GET(x) (((uint32_t)(x) & DDRCTL_DFILPCFG0_DFI_LP_EN_SR_MASK) >> DDRCTL_DFILPCFG0_DFI_LP_EN_SR_SHIFT) + +/* + * DFI_LP_WAKEUP_PD (R/W) + * + * Description: Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. + * Determines the DFI's tlp_wakeup time: + * 0x0 - 16 cycles + * 0x1 - 32 cycles + * 0x2 - 64 cycles + * 0x3 - 128 cycles + * 0x4 - 256 cycles + * 0x5 - 512 cycles + * 0x6 - 1024 cycles + * 0x7 - 2048 cycles + * 0x8 - 4096 cycles + * 0x9 - 8192 cycles + * 0xA - 16384 cycles + * 0xB - 32768 cycles + * 0xC - 65536 cycles + * 0xD - 131072 cycles + * 0xE - 262144 cycles + * 0xF - Unlimited Value After Reset: 0x0 Exists: Always + */ +#define DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK (0xF0U) +#define DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT (4U) +#define DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_SET(x) (((uint32_t)(x) << DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT) & DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK) +#define DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_GET(x) (((uint32_t)(x) & DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK) >> DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT) + +/* + * DFI_LP_EN_PD (R/W) + * + * Description: Enables DFI Low Power interface handshaking during Power Down Entry/Exit. + * 0 - Disabled + * 1 - Enabled + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_DFILPCFG0_DFI_LP_EN_PD_MASK (0x1U) +#define DDRCTL_DFILPCFG0_DFI_LP_EN_PD_SHIFT (0U) +#define DDRCTL_DFILPCFG0_DFI_LP_EN_PD_SET(x) (((uint32_t)(x) << DDRCTL_DFILPCFG0_DFI_LP_EN_PD_SHIFT) & DDRCTL_DFILPCFG0_DFI_LP_EN_PD_MASK) +#define DDRCTL_DFILPCFG0_DFI_LP_EN_PD_GET(x) (((uint32_t)(x) & DDRCTL_DFILPCFG0_DFI_LP_EN_PD_MASK) >> DDRCTL_DFILPCFG0_DFI_LP_EN_PD_SHIFT) + +/* Bitfield definition for register: DFIUPD0 */ +/* + * DIS_AUTO_CTRLUPD (R/W) + * + * Description: When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2. The core must issue the dfi_ctrlupd_req signal using register reg_ddrc_ctrlupd. This register field is changeable on the fly. + * When '0', uMCTL2 issues dfi_ctrlupd_req periodically. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_MASK (0x80000000UL) +#define DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT (31U) +#define DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_SET(x) (((uint32_t)(x) << DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT) & DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_MASK) +#define DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_GET(x) (((uint32_t)(x) & DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_MASK) >> DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT) + +/* + * DFI_T_CTRLUP_MAX (R/W) + * + * Description: Specifies the maximum number of clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. + * Unit: Clocks + * Value After Reset: 0x40 + * Exists: Always + */ +#define DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_MASK (0x3FF0000UL) +#define DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT (16U) +#define DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_SET(x) (((uint32_t)(x) << DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT) & DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_MASK) +#define DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_GET(x) (((uint32_t)(x) & DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_MASK) >> DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT) + +/* + * DFI_T_CTRLUP_MIN (R/W) + * + * Description: Specifies the minimum number of clock cycles that the dfi_ctrlupd_req signal must be asserted. The uMCTL2 expects the PHY to respond within this time. If the PHY does not respond, the uMCTL2 will de-assert dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. + * Unit: Clocks + * Value After Reset: 0x3 + * Exists: Always + */ +#define DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_MASK (0x3FFU) +#define DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT (0U) +#define DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_SET(x) (((uint32_t)(x) << DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT) & DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_MASK) +#define DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_GET(x) (((uint32_t)(x) & DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_MASK) >> DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT) + +/* Bitfield definition for register: DFIUPD1 */ +/* + * DFI_T_CTRLUPD_INTERVAL_MIN_X1024 (R/W) + * + * Description: This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the uMCTL2 is idle. + * Unit: 1024 clocks Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK (0xFF0000UL) +#define DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT (16U) +#define DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SET(x) (((uint32_t)(x) << DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT) & DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK) +#define DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_GET(x) (((uint32_t)(x) & DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK) >> DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT) + +/* + * DFI_T_CTRLUPD_INTERVAL_MAX_X1024 (R/W) + * + * Description: This is the maximum amount of time between uMCTL2 initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. + * Updates are required to maintain calibration over PVT, but frequent updates may impact performance. + * Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. + * Unit: 1024 clocks Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK (0xFFU) +#define DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT (0U) +#define DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SET(x) (((uint32_t)(x) << DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT) & DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK) +#define DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_GET(x) (((uint32_t)(x) & DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK) >> DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT) + +/* Bitfield definition for register: DFIUPD2 */ +/* + * DFI_PHYUPD_EN (R/W) + * + * Description: Enables the support for acknowledging PHY- initiated updates: + * 0 - Disabled + * 1 - Enabled + * Value After Reset: 0x1 + * Exists: Always + */ +#define DDRCTL_DFIUPD2_DFI_PHYUPD_EN_MASK (0x80000000UL) +#define DDRCTL_DFIUPD2_DFI_PHYUPD_EN_SHIFT (31U) +#define DDRCTL_DFIUPD2_DFI_PHYUPD_EN_SET(x) (((uint32_t)(x) << DDRCTL_DFIUPD2_DFI_PHYUPD_EN_SHIFT) & DDRCTL_DFIUPD2_DFI_PHYUPD_EN_MASK) +#define DDRCTL_DFIUPD2_DFI_PHYUPD_EN_GET(x) (((uint32_t)(x) & DDRCTL_DFIUPD2_DFI_PHYUPD_EN_MASK) >> DDRCTL_DFIUPD2_DFI_PHYUPD_EN_SHIFT) + +/* + * DFI_PHYUPD_TYPE1 (R/W) + * + * Description: Specifies the maximum number of DFI clock cycles that the dfi_phyupd_req signal may remain asserted after the assertion of the dfi_phyupd_ack signal for dfi_phyupd_type = 2'b01. The dfi_phyupd_req signal may de-assert at any cycle after the assertion of the dfi_phyupd_ack signal. + * Value After Reset: 0x10 + * Exists: Always + */ +#define DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_MASK (0xFFF0000UL) +#define DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_SHIFT (16U) +#define DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_SET(x) (((uint32_t)(x) << DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_SHIFT) & DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_MASK) +#define DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_GET(x) (((uint32_t)(x) & DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_MASK) >> DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_SHIFT) + +/* + * DFI_PHYUPD_TYPE0 (R/W) + * + * Description: Specifies the maximum number of DFI clock cycles that the dfi_phyupd_req signal may remain asserted after the assertion of the dfi_phyupd_ack signal for dfi_phyupd_type = 2'b00. The dfi_phyupd_req signal may de-assert at any cycle after the assertion of the dfi_phyupd_ack signal. + * Value After Reset: 0x10 + * Exists: Always + */ +#define DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_MASK (0xFFFU) +#define DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_SHIFT (0U) +#define DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_SET(x) (((uint32_t)(x) << DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_SHIFT) & DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_MASK) +#define DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_GET(x) (((uint32_t)(x) & DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_MASK) >> DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_SHIFT) + +/* Bitfield definition for register: DFIUPD3 */ +/* + * DFI_PHYUPD_TYPE3 (R/W) + * + * Description: Specifies the maximum number of DFI clock cycles that the dfi_phyupd_req signal may remain asserted after the assertion of the dfi_phyupd_ack signal for dfi_phyupd_type = 2'b11. The dfi_phyupd_req signal may de-assert at any cycle after the assertion of the dfi_phyupd_ack signal. + * Value After Reset: 0x10 + * Exists: Always + */ +#define DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_MASK (0xFFF0000UL) +#define DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_SHIFT (16U) +#define DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_SET(x) (((uint32_t)(x) << DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_SHIFT) & DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_MASK) +#define DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_GET(x) (((uint32_t)(x) & DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_MASK) >> DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_SHIFT) + +/* + * DFI_PHYUPD_TYPE2 (R/W) + * + * Description: Specifies the maximum number of DFI clock cycles that the dfi_phyupd_req signal may remain asserted after the assertion of the dfi_phyupd_ack signal for dfi_phyupd_type = 2'b10. The dfi_phyupd_req signal may de-assert at any cycle after the assertion of the dfi_phyupd_ack signal. + * Value After Reset: 0x10 + * Exists: Always + */ +#define DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_MASK (0xFFFU) +#define DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_SHIFT (0U) +#define DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_SET(x) (((uint32_t)(x) << DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_SHIFT) & DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_MASK) +#define DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_GET(x) (((uint32_t)(x) & DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_MASK) >> DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_SHIFT) + +/* Bitfield definition for register: DFIMISC */ +/* + * DFI_INIT_COMPLETE_EN (R/W) + * + * Description: PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisation + * Value After Reset: 0x1 + * Exists: Always + */ +#define DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_MASK (0x1U) +#define DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT (0U) +#define DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_SET(x) (((uint32_t)(x) << DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT) & DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_MASK) +#define DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_GET(x) (((uint32_t)(x) & DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_MASK) >> DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT) + +/* Bitfield definition for register: DFITMG2 */ +/* + * DFI_TPHY_RDCSLAT (R/W) + * + * Description: Number of clocks between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs_n signal is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value. + * Value After Reset: 0x2 + * Exists: Always + */ +#define DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_MASK (0x3F00U) +#define DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT (8U) +#define DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_SET(x) (((uint32_t)(x) << DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT) & DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_MASK) +#define DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_GET(x) (((uint32_t)(x) & DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_MASK) >> DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT) + +/* + * DFI_TPHY_WRCSLAT (R/W) + * + * Description: Number of clocks between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs_n signal is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. The minimum supported value is as follows: + * 0 for configurations with MEMC_WL0 = 1 + * 1 for configurations with MEMC_WL0 = 0 Refer to PHY specification for correct value. Value After Reset: 0x2 + * Exists: Always + */ +#define DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_MASK (0x3FU) +#define DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT (0U) +#define DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_SET(x) (((uint32_t)(x) << DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT) & DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_MASK) +#define DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_GET(x) (((uint32_t)(x) & DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_MASK) >> DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT) + +/* Bitfield definition for register: ADDRMAP0 */ +/* + * ADDRMAP_CS_BIT0 (R/W) + * + * Description: Selects the HIF address bit used as rank address bit 0. + * Valid Range: 0 to 27, and 31 + * Internal Base: 6 + * The selected HIF address bit is determined by adding the internal base to the value of this field. + * If set to 31, rank address bit 0 is set to 0. + * Value After Reset: 0x0 + * Exists: MEMC_NUM_RANKS>1 + */ +#define DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_MASK (0x1FU) +#define DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT (0U) +#define DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT) & DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_MASK) +#define DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_MASK) >> DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT) + +/* Bitfield definition for register: ADDRMAP1 */ +/* + * ADDRMAP_BANK_B2 (R/W) + * + * Description: Selects the HIF address bit used as bank address bit 2. + * Valid Range: 0 to 29 and 31 + * Internal Base: 4 + * The selected HIF address bit is determined by adding the internal base to the value of this field. + * If set to 31, bank address bit 2 is set to 0. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_MASK (0x1F0000UL) +#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT (16U) +#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT) & DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_MASK) +#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_MASK) >> DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT) + +/* + * ADDRMAP_BANK_B1 (R/W) + * + * Description: Selects the HIF address bits used as bank address bit 1. + * Valid Range: 0 to 30 + * Internal Base: 3 + * The selected HIF address bit for each of the bank address bits is determined by adding the internal base to the value of this field. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_MASK (0x1F00U) +#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT (8U) +#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT) & DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_MASK) +#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_MASK) >> DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT) + +/* + * ADDRMAP_BANK_B0 (R/W) + * + * Description: Selects the HIF address bits used as bank address bit 0. + * Valid Range: 0 to 30 + * Internal Base: 2 + * The selected HIF address bit for each of the bank address bits is determined by adding the internal base to the value of this field. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_MASK (0x1FU) +#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT (0U) +#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT) & DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_MASK) +#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_MASK) >> DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT) + +/* Bitfield definition for register: ADDRMAP2 */ +/* + * ADDRMAP_COL_B5 (R/W) + * + * Description: Full bus width mode: Selects the HIF address bit used as column address bit 5 (if MEMC_BURST_LENGTH = 4) or 6 (if + * MEMC_BURST_LENGTH = 8). + * Half bus width mode: Selects the HIF address bit used as column address bit 6 (if MEMC_BURST_LENGTH = 4) or 7 (if MEMC_BURST_LENGTH = 8). + * Quarter bus width mode: Selects the HIF address bit used as column address bit 7 (if MEMC_BURST_LENGTH = 4) or 8 (if MEMC_BURST_LENGTH = 8). + * Valid Range: 0 to 7, and 15 + * Internal Base: 5 + * The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_MASK (0xF000000UL) +#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_SHIFT (24U) +#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_SHIFT) & DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_MASK) +#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_MASK) >> DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_SHIFT) + +/* + * ADDRMAP_COL_B4 (R/W) + * + * Description: Full bus width mode: Selects the HIF address bit used as column address bit 4 (if MEMC_BURST_LENGTH = 4) or 5 (if + * MEMC_BURST_LENGTH = 8). + * Half bus width mode: Selects the HIF address bit used as column address bit 5 (if MEMC_BURST_LENGTH = 4) or 6 (if MEMC_BURST_LENGTH = 8). + * Quarter bus width mode: Selects the HIF address bit used as column address bit 6 (if MEMC_BURST_LENGTH = 4) or 7 (if MEMC_BURST_LENGTH = 8). + * Valid Range: 0 to 7, and 15 + * Internal Base: 4 + * The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_MASK (0xF0000UL) +#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_SHIFT (16U) +#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_SHIFT) & DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_MASK) +#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_MASK) >> DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_SHIFT) + +/* + * ADDRMAP_COL_B3 (R/W) + * + * Description: Full bus width mode: Selects the HIF address bit used as column address bit 3 (if MEMC_BURST_LENGTH = 4) or 4 (if + * MEMC_BURST_LENGTH = 8). + * Half bus width mode: Selects the HIF address bit used as column address bit 4 (if MEMC_BURST_LENGTH = 4) or 5 (if MEMC_BURST_LENGTH = 8). + * Quarter bus width mode: Selects the HIF address bit used as column address bit 5 (if MEMC_BURST_LENGTH = 4) or 6 (if MEMC_BURST_LENGTH = 8). + * Valid Range: 0 to 7 + * Internal Base: 3 + * The selected HIF address bit is determined by adding the internal base to the value of this field. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_MASK (0xF00U) +#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_SHIFT (8U) +#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_SHIFT) & DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_MASK) +#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_MASK) >> DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_SHIFT) + +/* + * ADDRMAP_COL_B2 (R/W) + * + * Description: Full bus width mode: Selects the HIF address bit used as column address bit 2 (if MEMC_BURST_LENGTH = 4) or 3 (if + * MEMC_BURST_LENGTH = 8). + * Half bus width mode: Selects the HIF address bit used as column address bit 3 (if MEMC_BURST_LENGTH = 4) or 4 (if MEMC_BURST_LENGTH = 8). + * Quarter bus width mode: Selects the HIF address bit used as column address bit 4 (if MEMC_BURST_LENGTH = 4) or 5 (if MEMC_BURST_LENGTH = 8). + * Valid Range: 0 to 7 + * Internal Base: 2 + * The selected HIF address bit is determined by adding the internal base to the value of this field. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_MASK (0xFU) +#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_SHIFT (0U) +#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_SHIFT) & DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_MASK) +#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_MASK) >> DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_SHIFT) + +/* Bitfield definition for register: ADDRMAP3 */ +/* + * ADDRMAP_COL_B9 (R/W) + * + * Description: Full bus width mode: Selects the HIF address bit used as column address bit 9 (if MEMC_BURST_LENGTH = 4) or 11 (10 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 8) + * Half bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 4) or 13 (11 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 8). + * (Column address bit 11 in LPDDR2/LPDDR3 mode) Quarter bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) (if + * MEMC_BURST_LENGTH = 4) or UNUSED (if + * MEMC_BURST_LENGTH = 8). + * Valid Range: 0 to 7, and 15 + * Internal Base: 9 + * The selected HIF address bit is determined by adding the internal base to the value of this field. + * If set to 15, this column address bit is set to 0. + * Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. + * In LPDDR2/LPDDR3, there is a dedicated bit for auto- precharge in the CA bus and hence column bit 10 is used. Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_MASK (0xF000000UL) +#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_SHIFT (24U) +#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_SHIFT) & DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_MASK) +#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_MASK) >> DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_SHIFT) + +/* + * ADDRMAP_COL_B8 (R/W) + * + * Description: Full bus width mode: Selects the HIF address bit used as column address bit 8 (if MEMC_BURST_LENGTH = 4) or 9 (if + * MEMC_BURST_LENGTH = 8). + * Half bus width mode: Selects the HIF address bit used as column address bit 9 (if MEMC_BURST_LENGTH = 4) or 11 (10 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 8). + * Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 4) or 13 (11 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 8). + * Valid Range: 0 to 7, and 15 + * Internal Base: 8 + * The selected HIF address bit is determined by adding the internal base to the value of this field. + * If set to 15, this column address bit is set to 0. + * Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. + * In LPDDR2/LPDDR3, there is a dedicated bit for auto- precharge in the CA bus and hence column bit 10 is used. Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_MASK (0xF0000UL) +#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_SHIFT (16U) +#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_SHIFT) & DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_MASK) +#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_MASK) >> DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_SHIFT) + +/* + * ADDRMAP_COL_B7 (R/W) + * + * Description: Full bus width mode: Selects the HIF address bit used as column address bit 7 (if MEMC_BURST_LENGTH = 4) or 8 (if + * MEMC_BURST_LENGTH = 8). + * Half bus width mode: Selects the HIF address bit used as column address bit 8 (if MEMC_BURST_LENGTH = 4) or 9 (if MEMC_BURST_LENGTH = 8). + * Quarter bus width mode: Selects the HIF address bit used as column address bit 9 (if MEMC_BURST_LENGTH = 4) or 11 (10 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 8). + * Valid Range: 0 to 7, and 15 + * Internal Base: 7 + * The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. + * Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge and hence no source address bit can be mapped to column address bit 10. + * In LPDDR2/LPDDR3, there is a dedicated bit for auto- precharge in the CA bus and hence column bit 10 is used. Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_MASK (0xF00U) +#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_SHIFT (8U) +#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_SHIFT) & DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_MASK) +#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_MASK) >> DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_SHIFT) + +/* + * ADDRMAP_COL_B6 (R/W) + * + * Description: Full bus width mode: Selects the HIF address bit used as column address bit 6 (if MEMC_BURST_LENGTH = 4) or 7 (if + * MEMC_BURST_LENGTH = 8). + * Half bus width mode: Selects the HIF address bit used as column address bit 7 (if MEMC_BURST_LENGTH = 4) or 8 (if MEMC_BURST_LENGTH = 8). + * Quarter bus width mode: Selects the HIF address bit used as column address bit 8 (if MEMC_BURST_LENGTH = 4) or 9 (if MEMC_BURST_LENGTH = 8). + * Valid Range: 0 to 7, and 15 + * Internal Base: 6 + * The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_MASK (0xFU) +#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_SHIFT (0U) +#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_SHIFT) & DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_MASK) +#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_MASK) >> DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_SHIFT) + +/* Bitfield definition for register: ADDRMAP4 */ +/* + * ADDRMAP_COL_B11 (R/W) + * + * Description: Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 4) or UNUSED (if MEMC_BURST_LENGTH = 8). + * Half bus width mode: Unused. To make it unused, this should be tied to 4'hF. + * Quarter bus width mode: Unused. To make it unused, this must be tied to 4'hF. + * Valid Range: 0 to 7, and 15 + * Internal Base: 11 + * The selected HIF address bit is determined by adding the internal base to the value of this field. + * If set to 15, this column address bit is set to 0. + * Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. + * In LPDDR2/LPDDR3, there is a dedicated bit for auto- precharge in the CA bus and hence column bit 10 is used. Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_MASK (0xF00U) +#define DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_SHIFT (8U) +#define DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_SHIFT) & DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_MASK) +#define DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_MASK) >> DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_SHIFT) + +/* + * ADDRMAP_COL_B10 (R/W) + * + * Description: Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 4) or 13 (11 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 8). + * Half bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 4) or UNUSED (if MEMC_BURST_LENGTH = 8) + * Quarter bus width mode: UNUSED. To make it unused, this must be tied to 4'hF. + * Valid Range: 0 to 7, and 15 + * Internal Base: 10 + * The selected HIF address bit is determined by adding the internal base to the value of this field. + * If set to 15, this column address bit is set to 0. + * Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. + * In LPDDR2/LPDDR3, there is a dedicated bit for auto- precharge in the CA bus and hence column bit 10 is used. Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_MASK (0xFU) +#define DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_SHIFT (0U) +#define DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_SHIFT) & DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_MASK) +#define DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_MASK) >> DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_SHIFT) + +/* Bitfield definition for register: ADDRMAP5 */ +/* + * ADDRMAP_ROW_B11 (R/W) + * + * Description: Selects the HIF address bit used as row address bit 11. + * Valid Range: 0 to 11, and 15 + * Internal Base: 17 + * The selected HIF address bit is determined by adding the internal base to the value of this field. + * If set to 15, row address bit 11 is set to 0. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_MASK (0xF000000UL) +#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT (24U) +#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT) & DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_MASK) +#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_MASK) >> DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT) + +/* + * ADDRMAP_ROW_B2_10 (R/W) + * + * Description: Selects the HIF address bits used as row address bits 2 to 10. + * Valid Range: 0 to 11 + * Internal Base: 8 (for row address bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc increasing to 16 (for row + * address bit 10) + * The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK (0xF0000UL) +#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT (16U) +#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT) & DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK) +#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK) >> DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT) + +/* + * ADDRMAP_ROW_B1 (R/W) + * + * Description: Selects the HIF address bits used as row address bit 1. + * Valid Range: 0 to 11 + * Internal Base: 7 + * The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_MASK (0xF00U) +#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT (8U) +#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT) & DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_MASK) +#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_MASK) >> DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT) + +/* + * ADDRMAP_ROW_B0 (R/W) + * + * Description: Selects the HIF address bits used as row address bit 0. + * Valid Range: 0 to 11 + * Internal Base: 6 + * The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_MASK (0xFU) +#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT (0U) +#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT) & DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_MASK) +#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_MASK) >> DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT) + +/* Bitfield definition for register: ADDRMAP6 */ +/* + * ADDRMAP_ROW_B15 (R/W) + * + * Description: Selects the HIF address bit used as row address bit 15. + * Valid Range: 0 to 11, and 15 + * Internal Base: 21 + * The selected HIF address bit is determined by adding the internal base to the value of this field. + * If set to 15, row address bit 15 is set to 0. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_MASK (0xF000000UL) +#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT (24U) +#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT) & DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_MASK) +#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_MASK) >> DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT) + +/* + * ADDRMAP_ROW_B14 (R/W) + * + * Description: Selects the HIF address bit used as row address bit 14. + * Valid Range: 0 to 11, and 15 + * Internal Base: 20 + * The selected HIF address bit is determined by adding the internal base to the value of this field. + * If set to 15, row address bit 14 is set to 0. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_MASK (0xF0000UL) +#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT (16U) +#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT) & DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_MASK) +#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_MASK) >> DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT) + +/* + * ADDRMAP_ROW_B13 (R/W) + * + * Description: Selects the HIF address bit used as row address bit 13. + * Valid Range: 0 to 11, and 15 + * Internal Base: 19 + * The selected HIF address bit is determined by adding the internal base to the value of this field. + * If set to 15, row address bit 13 is set to 0. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_MASK (0xF00U) +#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT (8U) +#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT) & DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_MASK) +#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_MASK) >> DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT) + +/* + * ADDRMAP_ROW_B12 (R/W) + * + * Description: Selects the HIF address bit used as row address bit 12. + * Valid Range: 0 to 11, and 15 + * Internal Base: 18 + * The selected HIF address bit is determined by adding the internal base to the value of this field. + * If set to 15, row address bit 12 is set to 0. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_MASK (0xFU) +#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT (0U) +#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT) & DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_MASK) +#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_MASK) >> DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT) + +/* Bitfield definition for register: ODTCFG */ +/* + * WR_ODT_HOLD (R/W) + * + * Description: Cycles to hold ODT for a write command. The minimum supported value is 2. DDR2/DDR3/DDR4 + * BL8 - 0x6 + * BL4 - 0x4 + * LPDDR3 - RU(tDQSSmax/tCK) + 4 + * Value After Reset: 0x4 + * Exists: Always + */ +#define DDRCTL_ODTCFG_WR_ODT_HOLD_MASK (0xF000000UL) +#define DDRCTL_ODTCFG_WR_ODT_HOLD_SHIFT (24U) +#define DDRCTL_ODTCFG_WR_ODT_HOLD_SET(x) (((uint32_t)(x) << DDRCTL_ODTCFG_WR_ODT_HOLD_SHIFT) & DDRCTL_ODTCFG_WR_ODT_HOLD_MASK) +#define DDRCTL_ODTCFG_WR_ODT_HOLD_GET(x) (((uint32_t)(x) & DDRCTL_ODTCFG_WR_ODT_HOLD_MASK) >> DDRCTL_ODTCFG_WR_ODT_HOLD_SHIFT) + +/* + * WR_ODT_DELAY (R/W) + * + * Description: The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. ODT is used only in DDR2, DDR3, DDR4 and LPDDR3 designs. + * Recommended values: + * DDR2 + * If (CWL + AL < 3), then 0. + * If (CWL + AL >= 3), then (CWL + AL - 3) DDR3 - 0 + * DDR4 - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) + * LPDDR3 - (CWL - RU(tODToffmax/tCK)) + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_ODTCFG_WR_ODT_DELAY_MASK (0x1F0000UL) +#define DDRCTL_ODTCFG_WR_ODT_DELAY_SHIFT (16U) +#define DDRCTL_ODTCFG_WR_ODT_DELAY_SET(x) (((uint32_t)(x) << DDRCTL_ODTCFG_WR_ODT_DELAY_SHIFT) & DDRCTL_ODTCFG_WR_ODT_DELAY_MASK) +#define DDRCTL_ODTCFG_WR_ODT_DELAY_GET(x) (((uint32_t)(x) & DDRCTL_ODTCFG_WR_ODT_DELAY_MASK) >> DDRCTL_ODTCFG_WR_ODT_DELAY_SHIFT) + +/* + * RD_ODT_HOLD (R/W) + * + * Description: Cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2/DDR3 + * BL8 - 0x6 + * BL4 - 0x4 + * DDR4 - 0x6, but needs to be reduced to 0x5 in CAL mode to avoid overlap of read and write ODT LPDDR3 - RU(tDQSCKmax/tCK) + 4 + 1 + * Value After Reset: 0x4 + * Exists: Always + */ +#define DDRCTL_ODTCFG_RD_ODT_HOLD_MASK (0xF00U) +#define DDRCTL_ODTCFG_RD_ODT_HOLD_SHIFT (8U) +#define DDRCTL_ODTCFG_RD_ODT_HOLD_SET(x) (((uint32_t)(x) << DDRCTL_ODTCFG_RD_ODT_HOLD_SHIFT) & DDRCTL_ODTCFG_RD_ODT_HOLD_MASK) +#define DDRCTL_ODTCFG_RD_ODT_HOLD_GET(x) (((uint32_t)(x) & DDRCTL_ODTCFG_RD_ODT_HOLD_MASK) >> DDRCTL_ODTCFG_RD_ODT_HOLD_SHIFT) + +/* + * RD_ODT_DELAY (R/W) + * + * Description: The delay, in clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. ODT is used only in DDR2, DDR3, DDR4 and LPDDR3 designs. + * Recommended values: + * DDR2 + * If (CL + AL < 4), then 0. + * If (CL + AL >= 4), then (CL + AL - 4) DDR3 + * (CL - CWL) DDR4 + * If CAL mode is enabled, CL - CWL + DFITMG1.dfi_t_cmd_lat + * If CAL mode is not enabled, CL - CWL -1, or 0 if CL - CWL < 1 + * LPDDR3, MEMC_FREQ_RATIO=2 + * CL - RU(tODToffmax/tCK)) Value After Reset: 0x0 Exists: Always + */ +#define DDRCTL_ODTCFG_RD_ODT_DELAY_MASK (0x7CU) +#define DDRCTL_ODTCFG_RD_ODT_DELAY_SHIFT (2U) +#define DDRCTL_ODTCFG_RD_ODT_DELAY_SET(x) (((uint32_t)(x) << DDRCTL_ODTCFG_RD_ODT_DELAY_SHIFT) & DDRCTL_ODTCFG_RD_ODT_DELAY_MASK) +#define DDRCTL_ODTCFG_RD_ODT_DELAY_GET(x) (((uint32_t)(x) & DDRCTL_ODTCFG_RD_ODT_DELAY_MASK) >> DDRCTL_ODTCFG_RD_ODT_DELAY_SHIFT) + +/* Bitfield definition for register: ODTMAP */ +/* + * RANK1_RD_ODT (R/W) + * + * Description: Indicates which remote ODTs must be turned on during a read from rank 1. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. + * Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. + * For each rank, set its bit to 1 to enable its ODT. + * Present only in configurations that have 2 or more ranks Value After Reset: "(MEMC_NUM_RANKS>1) ? 0x2 : 0x0" Exists: MEMC_NUM_RANKS>1 + */ +#define DDRCTL_ODTMAP_RANK1_RD_ODT_MASK (0xF000U) +#define DDRCTL_ODTMAP_RANK1_RD_ODT_SHIFT (12U) +#define DDRCTL_ODTMAP_RANK1_RD_ODT_SET(x) (((uint32_t)(x) << DDRCTL_ODTMAP_RANK1_RD_ODT_SHIFT) & DDRCTL_ODTMAP_RANK1_RD_ODT_MASK) +#define DDRCTL_ODTMAP_RANK1_RD_ODT_GET(x) (((uint32_t)(x) & DDRCTL_ODTMAP_RANK1_RD_ODT_MASK) >> DDRCTL_ODTMAP_RANK1_RD_ODT_SHIFT) + +/* + * RANK1_WR_ODT (R/W) + * + * Description: Indicates which remote ODTs must be turned on during a write to rank 1. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. + * Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. + * For each rank, set its bit to 1 to enable its ODT. + * Present only in configurations that have 2 or more ranks Value After Reset: "(MEMC_NUM_RANKS>1) ? 0x2 : 0x0" Exists: MEMC_NUM_RANKS>1 + */ +#define DDRCTL_ODTMAP_RANK1_WR_ODT_MASK (0xF00U) +#define DDRCTL_ODTMAP_RANK1_WR_ODT_SHIFT (8U) +#define DDRCTL_ODTMAP_RANK1_WR_ODT_SET(x) (((uint32_t)(x) << DDRCTL_ODTMAP_RANK1_WR_ODT_SHIFT) & DDRCTL_ODTMAP_RANK1_WR_ODT_MASK) +#define DDRCTL_ODTMAP_RANK1_WR_ODT_GET(x) (((uint32_t)(x) & DDRCTL_ODTMAP_RANK1_WR_ODT_MASK) >> DDRCTL_ODTMAP_RANK1_WR_ODT_SHIFT) + +/* + * RANK0_RD_ODT (R/W) + * + * Description: Indicates which remote ODTs must be turned on during a read from rank 0. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. + * Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. + * For each rank, set its bit to 1 to enable its ODT. + * Value After Reset: 0x1 + * Exists: Always + */ +#define DDRCTL_ODTMAP_RANK0_RD_ODT_MASK (0xF0U) +#define DDRCTL_ODTMAP_RANK0_RD_ODT_SHIFT (4U) +#define DDRCTL_ODTMAP_RANK0_RD_ODT_SET(x) (((uint32_t)(x) << DDRCTL_ODTMAP_RANK0_RD_ODT_SHIFT) & DDRCTL_ODTMAP_RANK0_RD_ODT_MASK) +#define DDRCTL_ODTMAP_RANK0_RD_ODT_GET(x) (((uint32_t)(x) & DDRCTL_ODTMAP_RANK0_RD_ODT_MASK) >> DDRCTL_ODTMAP_RANK0_RD_ODT_SHIFT) + +/* + * RANK0_WR_ODT (R/W) + * + * Description: Indicates which remote ODTs must be turned on during a write to rank 0. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. + * Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. + * For each rank, set its bit to 1 to enable its ODT. + * Value After Reset: 0x1 + * Exists: Always + */ +#define DDRCTL_ODTMAP_RANK0_WR_ODT_MASK (0xFU) +#define DDRCTL_ODTMAP_RANK0_WR_ODT_SHIFT (0U) +#define DDRCTL_ODTMAP_RANK0_WR_ODT_SET(x) (((uint32_t)(x) << DDRCTL_ODTMAP_RANK0_WR_ODT_SHIFT) & DDRCTL_ODTMAP_RANK0_WR_ODT_MASK) +#define DDRCTL_ODTMAP_RANK0_WR_ODT_GET(x) (((uint32_t)(x) & DDRCTL_ODTMAP_RANK0_WR_ODT_MASK) >> DDRCTL_ODTMAP_RANK0_WR_ODT_SHIFT) + +/* Bitfield definition for register: SCHED */ +/* + * RDWR_IDLE_GAP (R/W) + * + * Description: When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. + * The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternative store. + * When prefer write over read is set this is reversed. + * 0x0 is a legal value for this register. When set to 0x0, the transaction store switching will happen immediately when the switching conditions become true. + * FOR PERFORMANCE ONLY + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_SCHED_RDWR_IDLE_GAP_MASK (0x7F000000UL) +#define DDRCTL_SCHED_RDWR_IDLE_GAP_SHIFT (24U) +#define DDRCTL_SCHED_RDWR_IDLE_GAP_SET(x) (((uint32_t)(x) << DDRCTL_SCHED_RDWR_IDLE_GAP_SHIFT) & DDRCTL_SCHED_RDWR_IDLE_GAP_MASK) +#define DDRCTL_SCHED_RDWR_IDLE_GAP_GET(x) (((uint32_t)(x) & DDRCTL_SCHED_RDWR_IDLE_GAP_MASK) >> DDRCTL_SCHED_RDWR_IDLE_GAP_SHIFT) + +/* + * GO2CRITICAL_HYSTERESIS (R/W) + * + * Description: UNUSED Value After Reset: 0x0 Exists: Always + */ +#define DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_MASK (0xFF0000UL) +#define DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT (16U) +#define DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_SET(x) (((uint32_t)(x) << DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT) & DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_MASK) +#define DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_GET(x) (((uint32_t)(x) & DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_MASK) >> DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT) + +/* + * LPR_NUM_ENTRIES (R/W) + * + * Description: Number of entries in the low priority transaction store is this value + 1. + * (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of entries available for the high priority transaction store. + * Setting this to maximum value allocates all entries to low priority transaction store. + * Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high priority transaction store. + * Note: In ECC configurations, the numbers of write and low priority read credits issued is one less than in the non-ECC case. One entry each is reserved in the write and low- priority read CAMs for storing the RMW requests arising out of single bit error correction RMW operation. + * Value After Reset: "MEMC_NO_OF_ENTRY/2" + * Exists: Always + */ +#define DDRCTL_SCHED_LPR_NUM_ENTRIES_MASK (0x3F00U) +#define DDRCTL_SCHED_LPR_NUM_ENTRIES_SHIFT (8U) +#define DDRCTL_SCHED_LPR_NUM_ENTRIES_SET(x) (((uint32_t)(x) << DDRCTL_SCHED_LPR_NUM_ENTRIES_SHIFT) & DDRCTL_SCHED_LPR_NUM_ENTRIES_MASK) +#define DDRCTL_SCHED_LPR_NUM_ENTRIES_GET(x) (((uint32_t)(x) & DDRCTL_SCHED_LPR_NUM_ENTRIES_MASK) >> DDRCTL_SCHED_LPR_NUM_ENTRIES_SHIFT) + +/* + * PAGECLOSE (R/W) + * + * Description: If true, bank is kept open only until there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit will be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between Write and Read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. If false, the bank remains open until there is a need to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy. The open page policy can be overridden by setting the per-command-autopre bit on the HIF interface (co_ih_rxcmd_autopre). + * The pageclose feature provids a midway between Open and Close page policies. + * FOR PERFORMANCE ONLY. + * Value After Reset: 0x1 + * Exists: Always + */ +#define DDRCTL_SCHED_PAGECLOSE_MASK (0x4U) +#define DDRCTL_SCHED_PAGECLOSE_SHIFT (2U) +#define DDRCTL_SCHED_PAGECLOSE_SET(x) (((uint32_t)(x) << DDRCTL_SCHED_PAGECLOSE_SHIFT) & DDRCTL_SCHED_PAGECLOSE_MASK) +#define DDRCTL_SCHED_PAGECLOSE_GET(x) (((uint32_t)(x) & DDRCTL_SCHED_PAGECLOSE_MASK) >> DDRCTL_SCHED_PAGECLOSE_SHIFT) + +/* + * PREFER_WRITE (R/W) + * + * Description: If set then the bank selector prefers writes over reads. + * FOR DEBUG ONLY. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_SCHED_PREFER_WRITE_MASK (0x2U) +#define DDRCTL_SCHED_PREFER_WRITE_SHIFT (1U) +#define DDRCTL_SCHED_PREFER_WRITE_SET(x) (((uint32_t)(x) << DDRCTL_SCHED_PREFER_WRITE_SHIFT) & DDRCTL_SCHED_PREFER_WRITE_MASK) +#define DDRCTL_SCHED_PREFER_WRITE_GET(x) (((uint32_t)(x) & DDRCTL_SCHED_PREFER_WRITE_MASK) >> DDRCTL_SCHED_PREFER_WRITE_SHIFT) + +/* + * FORCE_LOW_PRI_N (R/W) + * + * Description: Active low signal. When asserted ('0'), all incoming transactions are forced to low priority. This implies that all High Priority Read (HPR) and Variable Priority Read commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write side, all Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off Bypass path for read commands. + * FOR PERFORMANCE ONLY. + * Value After Reset: 0x1 + * Exists: Always + */ +#define DDRCTL_SCHED_FORCE_LOW_PRI_N_MASK (0x1U) +#define DDRCTL_SCHED_FORCE_LOW_PRI_N_SHIFT (0U) +#define DDRCTL_SCHED_FORCE_LOW_PRI_N_SET(x) (((uint32_t)(x) << DDRCTL_SCHED_FORCE_LOW_PRI_N_SHIFT) & DDRCTL_SCHED_FORCE_LOW_PRI_N_MASK) +#define DDRCTL_SCHED_FORCE_LOW_PRI_N_GET(x) (((uint32_t)(x) & DDRCTL_SCHED_FORCE_LOW_PRI_N_MASK) >> DDRCTL_SCHED_FORCE_LOW_PRI_N_SHIFT) + +/* Bitfield definition for register: SCHED1 */ +/* + * PAGECLOSE_TIMER (R/W) + * + * Description: This field works in conjunction with SCHED.pageclose. It only has meaning if SCHED.pageclose==1. + * If SCHED.pageclose==1 and pageclose_timer==0, then an auto-precharge may be scheduled for last read or write command in the CAM with a bank and page hit. Note, sometimes an explicit precharge is scheduled instead of the auto-precharge. See SCHED.pageclose for details of when this may happen. + * If SCHED.pageclose==1 and pageclose_timer>0, then an auto-precharge is not scheduled for last read or write command in the CAM with a bank and page hit. Instead, a timer is started, with pageclose_timer as the initial value. There is a timer on a per bank basis. The timer decrements unless the next read or write in the CAM to a bank is a page hit. It gets reset to pageclose_timer value if the next read or write in the CAM to a bank is a page hit. Once the timer has reached zero, an explcit precharge will be attempted to be scheduled. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_SCHED1_PAGECLOSE_TIMER_MASK (0xFFU) +#define DDRCTL_SCHED1_PAGECLOSE_TIMER_SHIFT (0U) +#define DDRCTL_SCHED1_PAGECLOSE_TIMER_SET(x) (((uint32_t)(x) << DDRCTL_SCHED1_PAGECLOSE_TIMER_SHIFT) & DDRCTL_SCHED1_PAGECLOSE_TIMER_MASK) +#define DDRCTL_SCHED1_PAGECLOSE_TIMER_GET(x) (((uint32_t)(x) & DDRCTL_SCHED1_PAGECLOSE_TIMER_MASK) >> DDRCTL_SCHED1_PAGECLOSE_TIMER_SHIFT) + +/* Bitfield definition for register: PERFHPR1 */ +/* + * HPR_XACT_RUN_LENGTH (R/W) + * + * Description: Number of transactions that are serviced once the HPR queue goes critical is the smaller of: + * This number + * Number of transactions available Unit: Transaction. + * FOR PERFORMANCE ONLY. + * Value After Reset: 0xf + * Exists: Always + */ +#define DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_MASK (0xFF000000UL) +#define DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_SHIFT (24U) +#define DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_SET(x) (((uint32_t)(x) << DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_SHIFT) & DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_MASK) +#define DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_GET(x) (((uint32_t)(x) & DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_MASK) >> DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_SHIFT) + +/* + * HPR_MAX_STARVE (R/W) + * + * Description: Number of clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not be disabled as it will cause excessive latencies. + * Unit: Clock cycles. + * FOR PERFORMANCE ONLY. + * Value After Reset: 0x1 + * Exists: Always + */ +#define DDRCTL_PERFHPR1_HPR_MAX_STARVE_MASK (0xFFFFU) +#define DDRCTL_PERFHPR1_HPR_MAX_STARVE_SHIFT (0U) +#define DDRCTL_PERFHPR1_HPR_MAX_STARVE_SET(x) (((uint32_t)(x) << DDRCTL_PERFHPR1_HPR_MAX_STARVE_SHIFT) & DDRCTL_PERFHPR1_HPR_MAX_STARVE_MASK) +#define DDRCTL_PERFHPR1_HPR_MAX_STARVE_GET(x) (((uint32_t)(x) & DDRCTL_PERFHPR1_HPR_MAX_STARVE_MASK) >> DDRCTL_PERFHPR1_HPR_MAX_STARVE_SHIFT) + +/* Bitfield definition for register: PERFLPR1 */ +/* + * LPR_XACT_RUN_LENGTH (R/W) + * + * Description: Number of transactions that are serviced once the LPR queue goes critical is the smaller of: + * This number + * Number of transactions available. Unit: Transaction. + * FOR PERFORMANCE ONLY. + * Value After Reset: 0xf + * Exists: Always + */ +#define DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK (0xFF000000UL) +#define DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT (24U) +#define DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_SET(x) (((uint32_t)(x) << DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT) & DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK) +#define DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_GET(x) (((uint32_t)(x) & DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK) >> DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT) + +/* + * LPR_MAX_STARVE (R/W) + * + * Description: Number of clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not be disabled as it will cause excessive latencies. + * Unit: Clock cycles. + * FOR PERFORMANCE ONLY. + * Value After Reset: 0x7f + * Exists: Always + */ +#define DDRCTL_PERFLPR1_LPR_MAX_STARVE_MASK (0xFFFFU) +#define DDRCTL_PERFLPR1_LPR_MAX_STARVE_SHIFT (0U) +#define DDRCTL_PERFLPR1_LPR_MAX_STARVE_SET(x) (((uint32_t)(x) << DDRCTL_PERFLPR1_LPR_MAX_STARVE_SHIFT) & DDRCTL_PERFLPR1_LPR_MAX_STARVE_MASK) +#define DDRCTL_PERFLPR1_LPR_MAX_STARVE_GET(x) (((uint32_t)(x) & DDRCTL_PERFLPR1_LPR_MAX_STARVE_MASK) >> DDRCTL_PERFLPR1_LPR_MAX_STARVE_SHIFT) + +/* Bitfield definition for register: PERFWR1 */ +/* + * W_XACT_RUN_LENGTH (R/W) + * + * Description: Number of transactions that are serviced once the WR queue goes critical is the smaller of: + * This number + * Number of transactions available. Unit: Transaction. + * FOR PERFORMANCE ONLY. + * Value After Reset: 0xf + * Exists: Always + */ +#define DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_MASK (0xFF000000UL) +#define DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_SHIFT (24U) +#define DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_SET(x) (((uint32_t)(x) << DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_SHIFT) & DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_MASK) +#define DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_GET(x) (((uint32_t)(x) & DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_MASK) >> DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_SHIFT) + +/* + * W_MAX_STARVE (R/W) + * + * Description: Number of clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not be disabled as it will cause excessive latencies. + * Unit: Clock cycles. + * FOR PERFORMANCE ONLY. + * Value After Reset: 0x7f + * Exists: Always + */ +#define DDRCTL_PERFWR1_W_MAX_STARVE_MASK (0xFFFFU) +#define DDRCTL_PERFWR1_W_MAX_STARVE_SHIFT (0U) +#define DDRCTL_PERFWR1_W_MAX_STARVE_SET(x) (((uint32_t)(x) << DDRCTL_PERFWR1_W_MAX_STARVE_SHIFT) & DDRCTL_PERFWR1_W_MAX_STARVE_MASK) +#define DDRCTL_PERFWR1_W_MAX_STARVE_GET(x) (((uint32_t)(x) & DDRCTL_PERFWR1_W_MAX_STARVE_MASK) >> DDRCTL_PERFWR1_W_MAX_STARVE_SHIFT) + +/* Bitfield definition for register: PERFVPR1 */ +/* + * VPR_TIMEOUT_RANGE (R/W) + * + * Description: Indicates the range of the timeout value that is used for grouping the expired VPR commands in the CAM in DDRC. For example, if the register value is set to 0xF, then the priorities of all the VPR commands whose timeout counters are 15 or below will be considered as expired-VPR commands when the timeout value of any of the VPR commands reach 0. The expired-VPR commands, when present, are given higher priority than HPR commands. The VPR commands are expected to consist of largely page hit traffic and by grouping them together the bus utilization is expected to increase. This register applies to transactions inside the DDRC only. + * The Max value for this register is 0x7FF and the Min value is 0x0. + * When programmed to the Max value of 0x7FF, all the VPR commands that come in to DDRC will time-out right-away and will be considered as expired-VPR. + * When programmed to the Min value of 0x0, the timer of each command would have to reach a value of 0 before it will be considered as expired-VPR. + * Unit: Clock cycles. + * FOR PERFORMANCE ONLY. + * Value After Reset: 0x0 + * Exists: UMCTL2_VPR_EN==1 + */ +#define DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_MASK (0x7FFU) +#define DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_SHIFT (0U) +#define DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_SET(x) (((uint32_t)(x) << DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_SHIFT) & DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_MASK) +#define DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_GET(x) (((uint32_t)(x) & DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_MASK) >> DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_SHIFT) + +/* Bitfield definition for register: PERFVPW1 */ +/* + * VPW_TIMEOUT_RANGE (R/W) + * + * Description: Indicates the range of the timeout value that is used for grouping the expired VPW commands in the CAM in DDRC. For example, if the register value is set to 0xF, then the priorities of all the VPW commands whose timeout counters are 15 or below will be considered as expired-VPW commands when the timeout value of any of the VPW commands reach 0. The expired-VPW commands, when present, are given higher priority than normal Write commands. The VPW commands are expected to consist of largely page hit traffic and by grouping them together the bus utilization is expected to increase. This register applies to transactions inside the DDRC only. + * The Max value for this register is 0x7FF and the Min value is 0x0. + * When programmed to the Max value of 0x7FF, all the VPW commands that come in to DDRC will time-out right-away and will be considered as expired-VPW. + * When programmed to the Min value of 0x0, the timer of each command would have to reach a value of 0 before it will be considered as expired-VPW. + * Unit: Clock cycles. + * FOR PERFORMANCE ONLY. + * Value After Reset: 0x0 + * Exists: UMCTL2_VPW_EN==1 + */ +#define DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_MASK (0x7FFU) +#define DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_SHIFT (0U) +#define DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_SET(x) (((uint32_t)(x) << DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_SHIFT) & DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_MASK) +#define DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_GET(x) (((uint32_t)(x) & DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_MASK) >> DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_SHIFT) + +/* Bitfield definition for register: DBG0 */ +/* + * DIS_COLLISION_PAGE_OPT (R/W) + * + * Description: When this is set to '0', auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). + * FOR DEBUG ONLY. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_MASK (0x10U) +#define DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT (4U) +#define DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_SET(x) (((uint32_t)(x) << DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT) & DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_MASK) +#define DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_GET(x) (((uint32_t)(x) & DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_MASK) >> DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT) + +/* + * DIS_ACT_BYPASS (R/W) + * + * Description: Only present in designs supporting activate bypass. + * When 1, disable bypass path for high priority read activates FOR DEBUG ONLY. + * Value After Reset: 0x0 + * Exists: MEMC_BYPASS==1 + */ +#define DDRCTL_DBG0_DIS_ACT_BYPASS_MASK (0x4U) +#define DDRCTL_DBG0_DIS_ACT_BYPASS_SHIFT (2U) +#define DDRCTL_DBG0_DIS_ACT_BYPASS_SET(x) (((uint32_t)(x) << DDRCTL_DBG0_DIS_ACT_BYPASS_SHIFT) & DDRCTL_DBG0_DIS_ACT_BYPASS_MASK) +#define DDRCTL_DBG0_DIS_ACT_BYPASS_GET(x) (((uint32_t)(x) & DDRCTL_DBG0_DIS_ACT_BYPASS_MASK) >> DDRCTL_DBG0_DIS_ACT_BYPASS_SHIFT) + +/* + * DIS_RD_BYPASS (R/W) + * + * Description: Only present in designs supporting read bypass. + * When 1, disable bypass path for high priority read page hits FOR DEBUG ONLY. + * Value After Reset: 0x0 + * Exists: MEMC_BYPASS==1 + */ +#define DDRCTL_DBG0_DIS_RD_BYPASS_MASK (0x2U) +#define DDRCTL_DBG0_DIS_RD_BYPASS_SHIFT (1U) +#define DDRCTL_DBG0_DIS_RD_BYPASS_SET(x) (((uint32_t)(x) << DDRCTL_DBG0_DIS_RD_BYPASS_SHIFT) & DDRCTL_DBG0_DIS_RD_BYPASS_MASK) +#define DDRCTL_DBG0_DIS_RD_BYPASS_GET(x) (((uint32_t)(x) & DDRCTL_DBG0_DIS_RD_BYPASS_MASK) >> DDRCTL_DBG0_DIS_RD_BYPASS_SHIFT) + +/* + * DIS_WC (R/W) + * + * Description: When 1, disable write combine. FOR DEBUG ONLY + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_DBG0_DIS_WC_MASK (0x1U) +#define DDRCTL_DBG0_DIS_WC_SHIFT (0U) +#define DDRCTL_DBG0_DIS_WC_SET(x) (((uint32_t)(x) << DDRCTL_DBG0_DIS_WC_SHIFT) & DDRCTL_DBG0_DIS_WC_MASK) +#define DDRCTL_DBG0_DIS_WC_GET(x) (((uint32_t)(x) & DDRCTL_DBG0_DIS_WC_MASK) >> DDRCTL_DBG0_DIS_WC_SHIFT) + +/* Bitfield definition for register: DBG1 */ +/* + * DIS_HIF (R/W) + * + * Description: When 1, uMCTL2 asserts the HIF command ih_co_stall. uMCTL2 will ignore the co_ih_rxcmd_valid and all other associated request signals. + * This bit is intended to be switched on-the-fly. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_DBG1_DIS_HIF_MASK (0x2U) +#define DDRCTL_DBG1_DIS_HIF_SHIFT (1U) +#define DDRCTL_DBG1_DIS_HIF_SET(x) (((uint32_t)(x) << DDRCTL_DBG1_DIS_HIF_SHIFT) & DDRCTL_DBG1_DIS_HIF_MASK) +#define DDRCTL_DBG1_DIS_HIF_GET(x) (((uint32_t)(x) & DDRCTL_DBG1_DIS_HIF_MASK) >> DDRCTL_DBG1_DIS_HIF_SHIFT) + +/* + * DIS_DQ (R/W) + * + * Description: When 1, uMCTL2 will not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. + * This bit may be used to prevent reads or writes being issued by the uMCTL2, which makes it safe to modify certain register fields associated with reads and writes (see User Guide for details). After setting this bit, it is strongly recommended to poll DBGCAM.wr_data_pipeline_empty and DBGCAM.rd_data_pipeline_empty, before making changes to any registers which affect reads and writes. This will ensure that the relevant logic in the DDRC is idle. + * This bit is intended to be switched on-the-fly. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_DBG1_DIS_DQ_MASK (0x1U) +#define DDRCTL_DBG1_DIS_DQ_SHIFT (0U) +#define DDRCTL_DBG1_DIS_DQ_SET(x) (((uint32_t)(x) << DDRCTL_DBG1_DIS_DQ_SHIFT) & DDRCTL_DBG1_DIS_DQ_MASK) +#define DDRCTL_DBG1_DIS_DQ_GET(x) (((uint32_t)(x) & DDRCTL_DBG1_DIS_DQ_MASK) >> DDRCTL_DBG1_DIS_DQ_SHIFT) + +/* Bitfield definition for register: DBGCAM */ +/* + * WR_DATA_PIPELINE_EMPTY (R) + * + * Description: This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_DBGCAM_WR_DATA_PIPELINE_EMPTY_MASK (0x20000000UL) +#define DDRCTL_DBGCAM_WR_DATA_PIPELINE_EMPTY_SHIFT (29U) +#define DDRCTL_DBGCAM_WR_DATA_PIPELINE_EMPTY_GET(x) (((uint32_t)(x) & DDRCTL_DBGCAM_WR_DATA_PIPELINE_EMPTY_MASK) >> DDRCTL_DBGCAM_WR_DATA_PIPELINE_EMPTY_SHIFT) + +/* + * RD_DATA_PIPELINE_EMPTY (R) + * + * Description: This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_DBGCAM_RD_DATA_PIPELINE_EMPTY_MASK (0x10000000UL) +#define DDRCTL_DBGCAM_RD_DATA_PIPELINE_EMPTY_SHIFT (28U) +#define DDRCTL_DBGCAM_RD_DATA_PIPELINE_EMPTY_GET(x) (((uint32_t)(x) & DDRCTL_DBGCAM_RD_DATA_PIPELINE_EMPTY_MASK) >> DDRCTL_DBGCAM_RD_DATA_PIPELINE_EMPTY_SHIFT) + +/* + * DBG_WR_Q_EMPTY (R) + * + * Description: When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. + * An example use-case scenario: When Controller enters Self- Refresh using the Low-Power entry sequence, Controller is expected to have executed all the commands in its queues and the write and read data drained. Hence this register should be 1 at that time. + * FOR DEBUG ONLY + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_DBGCAM_DBG_WR_Q_EMPTY_MASK (0x4000000UL) +#define DDRCTL_DBGCAM_DBG_WR_Q_EMPTY_SHIFT (26U) +#define DDRCTL_DBGCAM_DBG_WR_Q_EMPTY_GET(x) (((uint32_t)(x) & DDRCTL_DBGCAM_DBG_WR_Q_EMPTY_MASK) >> DDRCTL_DBGCAM_DBG_WR_Q_EMPTY_SHIFT) + +/* + * DBG_RD_Q_EMPTY (R) + * + * Description: When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. + * An example use-case scenario: When Controller enters Self- Refresh using the Low-Power entry sequence, Controller is expected to have executed all the commands in its queues and the write and read data drained. Hence this register should be 1 at that time. + * FOR DEBUG ONLY + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_DBGCAM_DBG_RD_Q_EMPTY_MASK (0x2000000UL) +#define DDRCTL_DBGCAM_DBG_RD_Q_EMPTY_SHIFT (25U) +#define DDRCTL_DBGCAM_DBG_RD_Q_EMPTY_GET(x) (((uint32_t)(x) & DDRCTL_DBGCAM_DBG_RD_Q_EMPTY_MASK) >> DDRCTL_DBGCAM_DBG_RD_Q_EMPTY_SHIFT) + +/* + * DBG_STALL (R) + * + * Description: Stall FOR DEBUG ONLY + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_DBGCAM_DBG_STALL_MASK (0x1000000UL) +#define DDRCTL_DBGCAM_DBG_STALL_SHIFT (24U) +#define DDRCTL_DBGCAM_DBG_STALL_GET(x) (((uint32_t)(x) & DDRCTL_DBGCAM_DBG_STALL_MASK) >> DDRCTL_DBGCAM_DBG_STALL_SHIFT) + +/* + * DBG_W_Q_DEPTH (R) + * + * Description: Write queue depth + * Note: The width of this field is dependent on log(MEMC_NO_OF_ENTRY+1). For example, if CAM depth + * = 32, then register width is 6 bits and bit 22 is reserved. FOR DEBUG ONLY + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_DBGCAM_DBG_W_Q_DEPTH_MASK (0x7F0000UL) +#define DDRCTL_DBGCAM_DBG_W_Q_DEPTH_SHIFT (16U) +#define DDRCTL_DBGCAM_DBG_W_Q_DEPTH_GET(x) (((uint32_t)(x) & DDRCTL_DBGCAM_DBG_W_Q_DEPTH_MASK) >> DDRCTL_DBGCAM_DBG_W_Q_DEPTH_SHIFT) + +/* + * DBG_LPR_Q_DEPTH (R) + * + * Description: Low priority read queue depth Note: The width of this field is dependent on + * log(MEMC_NO_OF_ENTRY+1). For example, if CAM depth + * = 32, then register width is 6 bits and bit 14 is reserved FOR DEBUG ONLY + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_DBGCAM_DBG_LPR_Q_DEPTH_MASK (0x7F00U) +#define DDRCTL_DBGCAM_DBG_LPR_Q_DEPTH_SHIFT (8U) +#define DDRCTL_DBGCAM_DBG_LPR_Q_DEPTH_GET(x) (((uint32_t)(x) & DDRCTL_DBGCAM_DBG_LPR_Q_DEPTH_MASK) >> DDRCTL_DBGCAM_DBG_LPR_Q_DEPTH_SHIFT) + +/* + * DBG_HPR_Q_DEPTH (R) + * + * Description: High priority read queue depth Note: The width of this field is dependent on + * log(MEMC_NO_OF_ENTRY+1). For example, if CAM depth + * = 32, then register width is 6 bits and bit 6 is reserved FOR DEBUG ONLY + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_DBGCAM_DBG_HPR_Q_DEPTH_MASK (0x7FU) +#define DDRCTL_DBGCAM_DBG_HPR_Q_DEPTH_SHIFT (0U) +#define DDRCTL_DBGCAM_DBG_HPR_Q_DEPTH_GET(x) (((uint32_t)(x) & DDRCTL_DBGCAM_DBG_HPR_Q_DEPTH_MASK) >> DDRCTL_DBGCAM_DBG_HPR_Q_DEPTH_SHIFT) + +/* Bitfield definition for register: DBGCMD */ +/* + * CTRLUPD (R/WSC) + * + * Description: Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in uMCTL2, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_DBGCMD_CTRLUPD_MASK (0x20U) +#define DDRCTL_DBGCMD_CTRLUPD_SHIFT (5U) +#define DDRCTL_DBGCMD_CTRLUPD_SET(x) (((uint32_t)(x) << DDRCTL_DBGCMD_CTRLUPD_SHIFT) & DDRCTL_DBGCMD_CTRLUPD_MASK) +#define DDRCTL_DBGCMD_CTRLUPD_GET(x) (((uint32_t)(x) & DDRCTL_DBGCMD_CTRLUPD_MASK) >> DDRCTL_DBGCMD_CTRLUPD_SHIFT) + +/* + * ZQ_CALIB_SHORT (R/WSC) + * + * Description: Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short) command to the SDRAM. When this request is stored in uMCTL2, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register bit is ignored when in Self-Refresh and Deep power-down operating modes. + * Value After Reset: 0x0 + * Exists: MEMC_DDR3_OR_4_OR_LPDDR2==1 + */ +#define DDRCTL_DBGCMD_ZQ_CALIB_SHORT_MASK (0x10U) +#define DDRCTL_DBGCMD_ZQ_CALIB_SHORT_SHIFT (4U) +#define DDRCTL_DBGCMD_ZQ_CALIB_SHORT_SET(x) (((uint32_t)(x) << DDRCTL_DBGCMD_ZQ_CALIB_SHORT_SHIFT) & DDRCTL_DBGCMD_ZQ_CALIB_SHORT_MASK) +#define DDRCTL_DBGCMD_ZQ_CALIB_SHORT_GET(x) (((uint32_t)(x) & DDRCTL_DBGCMD_ZQ_CALIB_SHORT_MASK) >> DDRCTL_DBGCMD_ZQ_CALIB_SHORT_SHIFT) + +/* + * RANK1_REFRESH (R/WSC) + * + * Description: Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. When this request is stored in uMCTL2, the bit is automatically cleared. This operation can be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-down operating modes or Maximum Power Saving Mode. + * Value After Reset: 0x0 + * Exists: MEMC_NUM_RANKS>1 + */ +#define DDRCTL_DBGCMD_RANK1_REFRESH_MASK (0x2U) +#define DDRCTL_DBGCMD_RANK1_REFRESH_SHIFT (1U) +#define DDRCTL_DBGCMD_RANK1_REFRESH_SET(x) (((uint32_t)(x) << DDRCTL_DBGCMD_RANK1_REFRESH_SHIFT) & DDRCTL_DBGCMD_RANK1_REFRESH_MASK) +#define DDRCTL_DBGCMD_RANK1_REFRESH_GET(x) (((uint32_t)(x) & DDRCTL_DBGCMD_RANK1_REFRESH_MASK) >> DDRCTL_DBGCMD_RANK1_REFRESH_SHIFT) + +/* + * RANK0_REFRESH (R/WSC) + * + * Description: Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. When this request is stored in uMCTL2, the bit is automatically cleared. This operation can be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-down operating modes or Maximum Power Saving Mode. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_DBGCMD_RANK0_REFRESH_MASK (0x1U) +#define DDRCTL_DBGCMD_RANK0_REFRESH_SHIFT (0U) +#define DDRCTL_DBGCMD_RANK0_REFRESH_SET(x) (((uint32_t)(x) << DDRCTL_DBGCMD_RANK0_REFRESH_SHIFT) & DDRCTL_DBGCMD_RANK0_REFRESH_MASK) +#define DDRCTL_DBGCMD_RANK0_REFRESH_GET(x) (((uint32_t)(x) & DDRCTL_DBGCMD_RANK0_REFRESH_MASK) >> DDRCTL_DBGCMD_RANK0_REFRESH_SHIFT) + +/* Bitfield definition for register: DBGSTAT */ +/* + * CTRLUPD_BUSY (R) + * + * Description: SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in uMCTL2. It is recommended not to perform ctrlupd operations when this signal is high. + * 0 - Indicates that the SoC core can initiate a ctrlupd operation + * 1 - Indicates that ctrlupd operation has not been initiated yet in uMCTL2 + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_DBGSTAT_CTRLUPD_BUSY_MASK (0x20U) +#define DDRCTL_DBGSTAT_CTRLUPD_BUSY_SHIFT (5U) +#define DDRCTL_DBGSTAT_CTRLUPD_BUSY_GET(x) (((uint32_t)(x) & DDRCTL_DBGSTAT_CTRLUPD_BUSY_MASK) >> DDRCTL_DBGSTAT_CTRLUPD_BUSY_SHIFT) + +/* + * ZQ_CALIB_SHORT_BUSY (R) + * + * Description: SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ZQCS request. It goes low when the ZQCS operation is initiated in uMCTL2. It is recommended not to perform ZQCS operations when this signal is high. + * 0 - Indicates that the SoC core can initiate a ZQCS operation + * 1 - Indicates that ZQCS operation has not been initiated yet in uMCTL2 + * Value After Reset: 0x0 + * Exists: MEMC_DDR3_OR_4_OR_LPDDR2==1 + */ +#define DDRCTL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_MASK (0x10U) +#define DDRCTL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_SHIFT (4U) +#define DDRCTL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_GET(x) (((uint32_t)(x) & DDRCTL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_MASK) >> DDRCTL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_SHIFT) + +/* + * RANK1_REFRESH_BUSY (R) + * + * Description: SoC core may initiate a rank1_refresh operation (refresh operation to rank 1) only if this signal is low. This signal goes high in the clock after DBGCMD.rank1_refresh is set to one. It goes low when the rank1_refresh operation is stored in uMCTL2. It is recommended not to perform rank1_refresh operations when this signal is high. + * 0 - Indicates that the SoC core can initiate a rank1_refresh operation + * 1 - Indicates that rank1_refresh operation has not been stored yet in uMCTL2 + * Value After Reset: 0x0 + * Exists: MEMC_NUM_RANKS>1 + */ +#define DDRCTL_DBGSTAT_RANK1_REFRESH_BUSY_MASK (0x2U) +#define DDRCTL_DBGSTAT_RANK1_REFRESH_BUSY_SHIFT (1U) +#define DDRCTL_DBGSTAT_RANK1_REFRESH_BUSY_GET(x) (((uint32_t)(x) & DDRCTL_DBGSTAT_RANK1_REFRESH_BUSY_MASK) >> DDRCTL_DBGSTAT_RANK1_REFRESH_BUSY_SHIFT) + +/* + * RANK0_REFRESH_BUSY (R) + * + * Description: SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in uMCTL2. It is recommended not to perform rank0_refresh operations when this signal is high. + * 0 - Indicates that the SoC core can initiate a rank0_refresh operation + * 1 - Indicates that rank0_refresh operation has not been stored yet in uMCTL2 + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_DBGSTAT_RANK0_REFRESH_BUSY_MASK (0x1U) +#define DDRCTL_DBGSTAT_RANK0_REFRESH_BUSY_SHIFT (0U) +#define DDRCTL_DBGSTAT_RANK0_REFRESH_BUSY_GET(x) (((uint32_t)(x) & DDRCTL_DBGSTAT_RANK0_REFRESH_BUSY_MASK) >> DDRCTL_DBGSTAT_RANK0_REFRESH_BUSY_SHIFT) + +/* Bitfield definition for register: PSTAT */ +/* + * WR_PORT_BUSY_15 (R) + * + * Description: Indicates if there are outstanding writes for port 15. + * Value After Reset: 0x0 + * Exists: UMCTL2_PORT_15==1 + */ +#define DDRCTL_PSTAT_WR_PORT_BUSY_15_MASK (0x80000000UL) +#define DDRCTL_PSTAT_WR_PORT_BUSY_15_SHIFT (31U) +#define DDRCTL_PSTAT_WR_PORT_BUSY_15_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_15_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_15_SHIFT) + +/* + * WR_PORT_BUSY_14 (R) + * + * Description: Indicates if there are outstanding writes for port 14. + * Value After Reset: 0x0 + * Exists: UMCTL2_PORT_14==1 + */ +#define DDRCTL_PSTAT_WR_PORT_BUSY_14_MASK (0x40000000UL) +#define DDRCTL_PSTAT_WR_PORT_BUSY_14_SHIFT (30U) +#define DDRCTL_PSTAT_WR_PORT_BUSY_14_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_14_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_14_SHIFT) + +/* + * WR_PORT_BUSY_13 (R) + * + * Description: Indicates if there are outstanding writes for port 13. + * Value After Reset: 0x0 + * Exists: UMCTL2_PORT_13==1 + */ +#define DDRCTL_PSTAT_WR_PORT_BUSY_13_MASK (0x20000000UL) +#define DDRCTL_PSTAT_WR_PORT_BUSY_13_SHIFT (29U) +#define DDRCTL_PSTAT_WR_PORT_BUSY_13_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_13_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_13_SHIFT) + +/* + * WR_PORT_BUSY_12 (R) + * + * Description: Indicates if there are outstanding writes for port 12. + * Value After Reset: 0x0 + * Exists: UMCTL2_PORT_12==1 + */ +#define DDRCTL_PSTAT_WR_PORT_BUSY_12_MASK (0x10000000UL) +#define DDRCTL_PSTAT_WR_PORT_BUSY_12_SHIFT (28U) +#define DDRCTL_PSTAT_WR_PORT_BUSY_12_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_12_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_12_SHIFT) + +/* + * WR_PORT_BUSY_11 (R) + * + * Description: Indicates if there are outstanding writes for port 11. + * Value After Reset: 0x0 + * Exists: UMCTL2_PORT_11==1 + */ +#define DDRCTL_PSTAT_WR_PORT_BUSY_11_MASK (0x8000000UL) +#define DDRCTL_PSTAT_WR_PORT_BUSY_11_SHIFT (27U) +#define DDRCTL_PSTAT_WR_PORT_BUSY_11_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_11_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_11_SHIFT) + +/* + * WR_PORT_BUSY_10 (R) + * + * Description: Indicates if there are outstanding writes for port 10. + * Value After Reset: 0x0 + * Exists: UMCTL2_PORT_10==1 + */ +#define DDRCTL_PSTAT_WR_PORT_BUSY_10_MASK (0x4000000UL) +#define DDRCTL_PSTAT_WR_PORT_BUSY_10_SHIFT (26U) +#define DDRCTL_PSTAT_WR_PORT_BUSY_10_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_10_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_10_SHIFT) + +/* + * WR_PORT_BUSY_9 (R) + * + * Description: Indicates if there are outstanding writes for port 9. + * Value After Reset: 0x0 + * Exists: UMCTL2_PORT_9==1 + */ +#define DDRCTL_PSTAT_WR_PORT_BUSY_9_MASK (0x2000000UL) +#define DDRCTL_PSTAT_WR_PORT_BUSY_9_SHIFT (25U) +#define DDRCTL_PSTAT_WR_PORT_BUSY_9_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_9_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_9_SHIFT) + +/* + * WR_PORT_BUSY_8 (R) + * + * Description: Indicates if there are outstanding writes for port 8. + * Value After Reset: 0x0 + * Exists: UMCTL2_PORT_8==1 + */ +#define DDRCTL_PSTAT_WR_PORT_BUSY_8_MASK (0x1000000UL) +#define DDRCTL_PSTAT_WR_PORT_BUSY_8_SHIFT (24U) +#define DDRCTL_PSTAT_WR_PORT_BUSY_8_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_8_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_8_SHIFT) + +/* + * WR_PORT_BUSY_7 (R) + * + * Description: Indicates if there are outstanding writes for port 7. + * Value After Reset: 0x0 + * Exists: UMCTL2_PORT_7==1 + */ +#define DDRCTL_PSTAT_WR_PORT_BUSY_7_MASK (0x800000UL) +#define DDRCTL_PSTAT_WR_PORT_BUSY_7_SHIFT (23U) +#define DDRCTL_PSTAT_WR_PORT_BUSY_7_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_7_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_7_SHIFT) + +/* + * WR_PORT_BUSY_6 (R) + * + * Description: Indicates if there are outstanding writes for port 6. + * Value After Reset: 0x0 + * Exists: UMCTL2_PORT_6==1 + */ +#define DDRCTL_PSTAT_WR_PORT_BUSY_6_MASK (0x400000UL) +#define DDRCTL_PSTAT_WR_PORT_BUSY_6_SHIFT (22U) +#define DDRCTL_PSTAT_WR_PORT_BUSY_6_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_6_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_6_SHIFT) + +/* + * WR_PORT_BUSY_5 (R) + * + * Description: Indicates if there are outstanding writes for port 5. + * Value After Reset: 0x0 + * Exists: UMCTL2_PORT_5==1 + */ +#define DDRCTL_PSTAT_WR_PORT_BUSY_5_MASK (0x200000UL) +#define DDRCTL_PSTAT_WR_PORT_BUSY_5_SHIFT (21U) +#define DDRCTL_PSTAT_WR_PORT_BUSY_5_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_5_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_5_SHIFT) + +/* + * WR_PORT_BUSY_4 (R) + * + * Description: Indicates if there are outstanding writes for port 4. + * Value After Reset: 0x0 + * Exists: UMCTL2_PORT_4==1 + */ +#define DDRCTL_PSTAT_WR_PORT_BUSY_4_MASK (0x100000UL) +#define DDRCTL_PSTAT_WR_PORT_BUSY_4_SHIFT (20U) +#define DDRCTL_PSTAT_WR_PORT_BUSY_4_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_4_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_4_SHIFT) + +/* + * WR_PORT_BUSY_3 (R) + * + * Description: Indicates if there are outstanding writes for port 3. + * Value After Reset: 0x0 + * Exists: UMCTL2_PORT_3==1 + */ +#define DDRCTL_PSTAT_WR_PORT_BUSY_3_MASK (0x80000UL) +#define DDRCTL_PSTAT_WR_PORT_BUSY_3_SHIFT (19U) +#define DDRCTL_PSTAT_WR_PORT_BUSY_3_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_3_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_3_SHIFT) + +/* + * WR_PORT_BUSY_2 (R) + * + * Description: Indicates if there are outstanding writes for port 2. + * Value After Reset: 0x0 + * Exists: UMCTL2_PORT_2==1 + */ +#define DDRCTL_PSTAT_WR_PORT_BUSY_2_MASK (0x40000UL) +#define DDRCTL_PSTAT_WR_PORT_BUSY_2_SHIFT (18U) +#define DDRCTL_PSTAT_WR_PORT_BUSY_2_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_2_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_2_SHIFT) + +/* + * WR_PORT_BUSY_1 (R) + * + * Description: Indicates if there are outstanding writes for port 1. + * Value After Reset: 0x0 + * Exists: UMCTL2_PORT_1==1 + */ +#define DDRCTL_PSTAT_WR_PORT_BUSY_1_MASK (0x20000UL) +#define DDRCTL_PSTAT_WR_PORT_BUSY_1_SHIFT (17U) +#define DDRCTL_PSTAT_WR_PORT_BUSY_1_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_1_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_1_SHIFT) + +/* + * WR_PORT_BUSY_0 (R) + * + * Description: Indicates if there are outstanding writes for port 0. + * Value After Reset: 0x0 + * Exists: UMCTL2_PORT_0==1 + */ +#define DDRCTL_PSTAT_WR_PORT_BUSY_0_MASK (0x10000UL) +#define DDRCTL_PSTAT_WR_PORT_BUSY_0_SHIFT (16U) +#define DDRCTL_PSTAT_WR_PORT_BUSY_0_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_0_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_0_SHIFT) + +/* + * RD_PORT_BUSY_15 (R) + * + * Description: Indicates if there are outstanding reads for port 15. + * Value After Reset: 0x0 + * Exists: UMCTL2_PORT_15==1 + */ +#define DDRCTL_PSTAT_RD_PORT_BUSY_15_MASK (0x8000U) +#define DDRCTL_PSTAT_RD_PORT_BUSY_15_SHIFT (15U) +#define DDRCTL_PSTAT_RD_PORT_BUSY_15_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_15_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_15_SHIFT) + +/* + * RD_PORT_BUSY_14 (R) + * + * Description: Indicates if there are outstanding reads for port 14. + * Value After Reset: 0x0 + * Exists: UMCTL2_PORT_14==1 + */ +#define DDRCTL_PSTAT_RD_PORT_BUSY_14_MASK (0x4000U) +#define DDRCTL_PSTAT_RD_PORT_BUSY_14_SHIFT (14U) +#define DDRCTL_PSTAT_RD_PORT_BUSY_14_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_14_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_14_SHIFT) + +/* + * RD_PORT_BUSY_13 (R) + * + * Description: Indicates if there are outstanding reads for port 13. + * Value After Reset: 0x0 + * Exists: UMCTL2_PORT_13==1 + */ +#define DDRCTL_PSTAT_RD_PORT_BUSY_13_MASK (0x2000U) +#define DDRCTL_PSTAT_RD_PORT_BUSY_13_SHIFT (13U) +#define DDRCTL_PSTAT_RD_PORT_BUSY_13_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_13_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_13_SHIFT) + +/* + * RD_PORT_BUSY_12 (R) + * + * Description: Indicates if there are outstanding reads for port 12. + * Value After Reset: 0x0 + * Exists: UMCTL2_PORT_12==1 + */ +#define DDRCTL_PSTAT_RD_PORT_BUSY_12_MASK (0x1000U) +#define DDRCTL_PSTAT_RD_PORT_BUSY_12_SHIFT (12U) +#define DDRCTL_PSTAT_RD_PORT_BUSY_12_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_12_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_12_SHIFT) + +/* + * RD_PORT_BUSY_11 (R) + * + * Description: Indicates if there are outstanding reads for port 11. + * Value After Reset: 0x0 + * Exists: UMCTL2_PORT_11==1 + */ +#define DDRCTL_PSTAT_RD_PORT_BUSY_11_MASK (0x800U) +#define DDRCTL_PSTAT_RD_PORT_BUSY_11_SHIFT (11U) +#define DDRCTL_PSTAT_RD_PORT_BUSY_11_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_11_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_11_SHIFT) + +/* + * RD_PORT_BUSY_10 (R) + * + * Description: Indicates if there are outstanding reads for port 10. + * Value After Reset: 0x0 + * Exists: UMCTL2_PORT_10==1 + */ +#define DDRCTL_PSTAT_RD_PORT_BUSY_10_MASK (0x400U) +#define DDRCTL_PSTAT_RD_PORT_BUSY_10_SHIFT (10U) +#define DDRCTL_PSTAT_RD_PORT_BUSY_10_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_10_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_10_SHIFT) + +/* + * RD_PORT_BUSY_9 (R) + * + * Description: Indicates if there are outstanding reads for port 9. + * Value After Reset: 0x0 + * Exists: UMCTL2_PORT_9==1 + */ +#define DDRCTL_PSTAT_RD_PORT_BUSY_9_MASK (0x200U) +#define DDRCTL_PSTAT_RD_PORT_BUSY_9_SHIFT (9U) +#define DDRCTL_PSTAT_RD_PORT_BUSY_9_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_9_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_9_SHIFT) + +/* + * RD_PORT_BUSY_8 (R) + * + * Description: Indicates if there are outstanding reads for port 8. + * Value After Reset: 0x0 + * Exists: UMCTL2_PORT_8==1 + */ +#define DDRCTL_PSTAT_RD_PORT_BUSY_8_MASK (0x100U) +#define DDRCTL_PSTAT_RD_PORT_BUSY_8_SHIFT (8U) +#define DDRCTL_PSTAT_RD_PORT_BUSY_8_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_8_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_8_SHIFT) + +/* + * RD_PORT_BUSY_7 (R) + * + * Description: Indicates if there are outstanding reads for port 7. + * Value After Reset: 0x0 + * Exists: UMCTL2_PORT_7==1 + */ +#define DDRCTL_PSTAT_RD_PORT_BUSY_7_MASK (0x80U) +#define DDRCTL_PSTAT_RD_PORT_BUSY_7_SHIFT (7U) +#define DDRCTL_PSTAT_RD_PORT_BUSY_7_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_7_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_7_SHIFT) + +/* + * RD_PORT_BUSY_6 (R) + * + * Description: Indicates if there are outstanding reads for port 6. + * Value After Reset: 0x0 + * Exists: UMCTL2_PORT_6==1 + */ +#define DDRCTL_PSTAT_RD_PORT_BUSY_6_MASK (0x40U) +#define DDRCTL_PSTAT_RD_PORT_BUSY_6_SHIFT (6U) +#define DDRCTL_PSTAT_RD_PORT_BUSY_6_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_6_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_6_SHIFT) + +/* + * RD_PORT_BUSY_5 (R) + * + * Description: Indicates if there are outstanding reads for port 5. + * Value After Reset: 0x0 + * Exists: UMCTL2_PORT_5==1 + */ +#define DDRCTL_PSTAT_RD_PORT_BUSY_5_MASK (0x20U) +#define DDRCTL_PSTAT_RD_PORT_BUSY_5_SHIFT (5U) +#define DDRCTL_PSTAT_RD_PORT_BUSY_5_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_5_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_5_SHIFT) + +/* + * RD_PORT_BUSY_4 (R) + * + * Description: Indicates if there are outstanding reads for port 4. + * Value After Reset: 0x0 + * Exists: UMCTL2_PORT_4==1 + */ +#define DDRCTL_PSTAT_RD_PORT_BUSY_4_MASK (0x10U) +#define DDRCTL_PSTAT_RD_PORT_BUSY_4_SHIFT (4U) +#define DDRCTL_PSTAT_RD_PORT_BUSY_4_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_4_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_4_SHIFT) + +/* + * RD_PORT_BUSY_3 (R) + * + * Description: Indicates if there are outstanding reads for port 3. + * Value After Reset: 0x0 + * Exists: UMCTL2_PORT_3==1 + */ +#define DDRCTL_PSTAT_RD_PORT_BUSY_3_MASK (0x8U) +#define DDRCTL_PSTAT_RD_PORT_BUSY_3_SHIFT (3U) +#define DDRCTL_PSTAT_RD_PORT_BUSY_3_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_3_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_3_SHIFT) + +/* + * RD_PORT_BUSY_2 (R) + * + * Description: Indicates if there are outstanding reads for port 2. + * Value After Reset: 0x0 + * Exists: UMCTL2_PORT_2==1 + */ +#define DDRCTL_PSTAT_RD_PORT_BUSY_2_MASK (0x4U) +#define DDRCTL_PSTAT_RD_PORT_BUSY_2_SHIFT (2U) +#define DDRCTL_PSTAT_RD_PORT_BUSY_2_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_2_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_2_SHIFT) + +/* + * RD_PORT_BUSY_1 (R) + * + * Description: Indicates if there are outstanding reads for port 1. + * Value After Reset: 0x0 + * Exists: UMCTL2_PORT_1==1 + */ +#define DDRCTL_PSTAT_RD_PORT_BUSY_1_MASK (0x2U) +#define DDRCTL_PSTAT_RD_PORT_BUSY_1_SHIFT (1U) +#define DDRCTL_PSTAT_RD_PORT_BUSY_1_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_1_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_1_SHIFT) + +/* + * RD_PORT_BUSY_0 (R) + * + * Description: Indicates if there are outstanding reads for port 0. + * Value After Reset: 0x0 + * Exists: UMCTL2_PORT_0==1 + */ +#define DDRCTL_PSTAT_RD_PORT_BUSY_0_MASK (0x1U) +#define DDRCTL_PSTAT_RD_PORT_BUSY_0_SHIFT (0U) +#define DDRCTL_PSTAT_RD_PORT_BUSY_0_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_0_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_0_SHIFT) + +/* Bitfield definition for register: PCCFG */ +/* + * PAGEMATCH_LIMIT (R/W) + * + * Description: Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_PCCFG_PAGEMATCH_LIMIT_MASK (0x10U) +#define DDRCTL_PCCFG_PAGEMATCH_LIMIT_SHIFT (4U) +#define DDRCTL_PCCFG_PAGEMATCH_LIMIT_SET(x) (((uint32_t)(x) << DDRCTL_PCCFG_PAGEMATCH_LIMIT_SHIFT) & DDRCTL_PCCFG_PAGEMATCH_LIMIT_MASK) +#define DDRCTL_PCCFG_PAGEMATCH_LIMIT_GET(x) (((uint32_t)(x) & DDRCTL_PCCFG_PAGEMATCH_LIMIT_MASK) >> DDRCTL_PCCFG_PAGEMATCH_LIMIT_SHIFT) + +/* + * GO2CRITICAL_EN (R/W) + * + * Description: If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_rd signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_rd signals at DDRC are driven to 1b'0. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_PCCFG_GO2CRITICAL_EN_MASK (0x1U) +#define DDRCTL_PCCFG_GO2CRITICAL_EN_SHIFT (0U) +#define DDRCTL_PCCFG_GO2CRITICAL_EN_SET(x) (((uint32_t)(x) << DDRCTL_PCCFG_GO2CRITICAL_EN_SHIFT) & DDRCTL_PCCFG_GO2CRITICAL_EN_MASK) +#define DDRCTL_PCCFG_GO2CRITICAL_EN_GET(x) (((uint32_t)(x) & DDRCTL_PCCFG_GO2CRITICAL_EN_MASK) >> DDRCTL_PCCFG_GO2CRITICAL_EN_SHIFT) + +/* Bitfield definition for register of struct array PCFG: R */ +/* + * RD_PORT_PAGEMATCH_EN (R/W) + * + * Description: If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (i.e. same bank and same row). See also related PCCFG.pagematch_limit register. + * Value After Reset: "(MEMC_DDR4_EN==1) ? 0x0 : 0x1" + * Exists: Always + */ +#define DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_MASK (0x4000U) +#define DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_SHIFT (14U) +#define DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_SHIFT) & DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_MASK) +#define DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_MASK) >> DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_SHIFT) + +/* + * RD_PORT_URGENT_EN (R/W) + * + * Description: If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_rd signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_PCFG_R_RD_PORT_URGENT_EN_MASK (0x2000U) +#define DDRCTL_PCFG_R_RD_PORT_URGENT_EN_SHIFT (13U) +#define DDRCTL_PCFG_R_RD_PORT_URGENT_EN_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_R_RD_PORT_URGENT_EN_SHIFT) & DDRCTL_PCFG_R_RD_PORT_URGENT_EN_MASK) +#define DDRCTL_PCFG_R_RD_PORT_URGENT_EN_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_R_RD_PORT_URGENT_EN_MASK) >> DDRCTL_PCFG_R_RD_PORT_URGENT_EN_SHIFT) + +/* + * RD_PORT_AGING_EN (R/W) + * + * Description: If set to 1, enables aging function for the read channel of the port. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_PCFG_R_RD_PORT_AGING_EN_MASK (0x1000U) +#define DDRCTL_PCFG_R_RD_PORT_AGING_EN_SHIFT (12U) +#define DDRCTL_PCFG_R_RD_PORT_AGING_EN_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_R_RD_PORT_AGING_EN_SHIFT) & DDRCTL_PCFG_R_RD_PORT_AGING_EN_MASK) +#define DDRCTL_PCFG_R_RD_PORT_AGING_EN_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_R_RD_PORT_AGING_EN_MASK) >> DDRCTL_PCFG_R_RD_PORT_AGING_EN_SHIFT) + +/* + * RD_PORT_PRIORITY (R/W) + * + * Description: Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority will increase as the higher significant 5-bits of the counter starts to decrease. + * When the aging counter becomes 0, the corresponding port channel will have the highest priority level (timeout condition + * - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: The two LSBs of this register field are tied internally to 2'b00. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_PCFG_R_RD_PORT_PRIORITY_MASK (0x3FFU) +#define DDRCTL_PCFG_R_RD_PORT_PRIORITY_SHIFT (0U) +#define DDRCTL_PCFG_R_RD_PORT_PRIORITY_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_R_RD_PORT_PRIORITY_SHIFT) & DDRCTL_PCFG_R_RD_PORT_PRIORITY_MASK) +#define DDRCTL_PCFG_R_RD_PORT_PRIORITY_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_R_RD_PORT_PRIORITY_MASK) >> DDRCTL_PCFG_R_RD_PORT_PRIORITY_SHIFT) + +/* Bitfield definition for register of struct array PCFG: W */ +/* + * WR_PORT_PAGEMATCH_EN (R/W) + * + * Description: If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (i.e. same bank and same row). See also related PCCFG.pagematch_limit register. + * Value After Reset: 0x1 + * Exists: Always + */ +#define DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_MASK (0x4000U) +#define DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_SHIFT (14U) +#define DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_SHIFT) & DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_MASK) +#define DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_MASK) >> DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_SHIFT) + +/* + * WR_PORT_URGENT_EN (R/W) + * + * Description: If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_PCFG_W_WR_PORT_URGENT_EN_MASK (0x2000U) +#define DDRCTL_PCFG_W_WR_PORT_URGENT_EN_SHIFT (13U) +#define DDRCTL_PCFG_W_WR_PORT_URGENT_EN_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_W_WR_PORT_URGENT_EN_SHIFT) & DDRCTL_PCFG_W_WR_PORT_URGENT_EN_MASK) +#define DDRCTL_PCFG_W_WR_PORT_URGENT_EN_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_W_WR_PORT_URGENT_EN_MASK) >> DDRCTL_PCFG_W_WR_PORT_URGENT_EN_SHIFT) + +/* + * WR_PORT_AGING_EN (R/W) + * + * Description: If set to 1, enables aging function for the write channel of the port. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_PCFG_W_WR_PORT_AGING_EN_MASK (0x1000U) +#define DDRCTL_PCFG_W_WR_PORT_AGING_EN_SHIFT (12U) +#define DDRCTL_PCFG_W_WR_PORT_AGING_EN_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_W_WR_PORT_AGING_EN_SHIFT) & DDRCTL_PCFG_W_WR_PORT_AGING_EN_MASK) +#define DDRCTL_PCFG_W_WR_PORT_AGING_EN_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_W_WR_PORT_AGING_EN_MASK) >> DDRCTL_PCFG_W_WR_PORT_AGING_EN_SHIFT) + +/* + * WR_PORT_PRIORITY (R/W) + * + * Description: Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the + * write channel of a given port. Port's priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. Note: The two LSBs of this register field are tied internally to 2'b00. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_PCFG_W_WR_PORT_PRIORITY_MASK (0x3FFU) +#define DDRCTL_PCFG_W_WR_PORT_PRIORITY_SHIFT (0U) +#define DDRCTL_PCFG_W_WR_PORT_PRIORITY_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_W_WR_PORT_PRIORITY_SHIFT) & DDRCTL_PCFG_W_WR_PORT_PRIORITY_MASK) +#define DDRCTL_PCFG_W_WR_PORT_PRIORITY_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_W_WR_PORT_PRIORITY_MASK) >> DDRCTL_PCFG_W_WR_PORT_PRIORITY_SHIFT) + +/* Bitfield definition for register of struct array PCFG: C */ +/* + * AHB_ENDIANNESS (R/W) + * + * Description: If set to 0, enables support for little endian on the AHB port. If set to 1, enables support for big endian (BE- 32) on the AHB port. If set to 2, enables support for big endian (BE-A) on the AHB port. + * Value After Reset: 0x0 + * Exists: UMCTL2_A_AHB_n==1 + */ +#define DDRCTL_PCFG_C_AHB_ENDIANNESS_MASK (0x3U) +#define DDRCTL_PCFG_C_AHB_ENDIANNESS_SHIFT (0U) +#define DDRCTL_PCFG_C_AHB_ENDIANNESS_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_C_AHB_ENDIANNESS_SHIFT) & DDRCTL_PCFG_C_AHB_ENDIANNESS_MASK) +#define DDRCTL_PCFG_C_AHB_ENDIANNESS_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_C_AHB_ENDIANNESS_MASK) >> DDRCTL_PCFG_C_AHB_ENDIANNESS_SHIFT) + +/* Bitfield definition for register of struct array PCFG: MASKCH */ +/* + * ID_MASK (R/W) + * + * Description: Determines the mask used in the ID mapping function for virtual channel m. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_PCFG_ID_MASKCH_ID_MASK_MASK (0xFFFFFFFFUL) +#define DDRCTL_PCFG_ID_MASKCH_ID_MASK_SHIFT (0U) +#define DDRCTL_PCFG_ID_MASKCH_ID_MASK_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_ID_MASKCH_ID_MASK_SHIFT) & DDRCTL_PCFG_ID_MASKCH_ID_MASK_MASK) +#define DDRCTL_PCFG_ID_MASKCH_ID_MASK_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_ID_MASKCH_ID_MASK_MASK) >> DDRCTL_PCFG_ID_MASKCH_ID_MASK_SHIFT) + +/* Bitfield definition for register of struct array PCFG: VALUECH */ +/* + * ID_VALUE (R/W) + * + * Description: Determines the value used in the ID mapping function for virtual channel m. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_PCFG_ID_VALUECH_ID_VALUE_MASK (0xFFFFFFFFUL) +#define DDRCTL_PCFG_ID_VALUECH_ID_VALUE_SHIFT (0U) +#define DDRCTL_PCFG_ID_VALUECH_ID_VALUE_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_ID_VALUECH_ID_VALUE_SHIFT) & DDRCTL_PCFG_ID_VALUECH_ID_VALUE_MASK) +#define DDRCTL_PCFG_ID_VALUECH_ID_VALUE_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_ID_VALUECH_ID_VALUE_MASK) >> DDRCTL_PCFG_ID_VALUECH_ID_VALUE_SHIFT) + +/* Bitfield definition for register of struct array PCFG: CTRL */ +/* + * PORT_EN (R/W) + * + * Description: Enables port n. + * Value After Reset: "UMCTL2_PORT_EN_RESET_VALUE" + * Exists: Always + */ +#define DDRCTL_PCFG_CTRL_PORT_EN_MASK (0x1U) +#define DDRCTL_PCFG_CTRL_PORT_EN_SHIFT (0U) +#define DDRCTL_PCFG_CTRL_PORT_EN_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_CTRL_PORT_EN_SHIFT) & DDRCTL_PCFG_CTRL_PORT_EN_MASK) +#define DDRCTL_PCFG_CTRL_PORT_EN_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_CTRL_PORT_EN_MASK) >> DDRCTL_PCFG_CTRL_PORT_EN_SHIFT) + +/* Bitfield definition for register of struct array PCFG: QOS0 */ +/* + * RQOS_MAP_REGION1 (R/W) + * + * Description: This bitfield indicates the traffic class of region + * 1. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR) then VPR traffic is aliased to LPR traffic. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_MASK (0x300000UL) +#define DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_SHIFT (20U) +#define DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_SHIFT) & DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_MASK) +#define DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_MASK) >> DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_SHIFT) + +/* + * RQOS_MAP_REGION0 (R/W) + * + * Description: This bitfield indicates the traffic class of region + * 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR) then VPR traffic is aliased to LPR traffic. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_MASK (0x30000UL) +#define DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_SHIFT (16U) +#define DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_SHIFT) & DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_MASK) +#define DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_MASK) >> DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_SHIFT) + +/* + * RQOS_MAP_LEVEL1 (R/W) + * + * Description: Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13(for dual RAQ) or 0 to 14(for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinct values. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_MASK (0xFU) +#define DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_SHIFT (0U) +#define DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_SHIFT) & DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_MASK) +#define DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_MASK) >> DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_SHIFT) + +/* Bitfield definition for register of struct array PCFG: QOS1 */ +/* + * RQOS_MAP_TIMEOUTR (R/W) + * + * Description: Specifies the timeout value for transactions mapped to the red address queue. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_MASK (0x7FF0000UL) +#define DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_SHIFT (16U) +#define DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_SHIFT) & DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_MASK) +#define DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_MASK) >> DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_SHIFT) + +/* + * RQOS_MAP_TIMEOUTB (R/W) + * + * Description: Specifies the timeout value for transactions mapped to the blue address queue. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_MASK (0x7FFU) +#define DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_SHIFT (0U) +#define DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_SHIFT) & DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_MASK) +#define DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_MASK) >> DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_SHIFT) + +/* Bitfield definition for register of struct array PCFG: WQOS0 */ +/* + * WQOS_MAP_REGION1 (R/W) + * + * Description: This bitfield indicates the traffic class of region + * 1. Valid values are: + * 0: NPW + * 1: VPW + * When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW) then VPW traffic is aliased to NPW traffic. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_MASK (0x300000UL) +#define DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_SHIFT (20U) +#define DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_SHIFT) & DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_MASK) +#define DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_MASK) >> DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_SHIFT) + +/* + * WQOS_MAP_REGION0 (R/W) + * + * Description: This bitfield indicates the traffic class of region + * 0. Valid values are: + * 0: NPW + * 1: VPW + * When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region0 is set to 1 (VPW) then VPW traffic is aliased to NPW traffic. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_MASK (0x30000UL) +#define DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_SHIFT (16U) +#define DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_SHIFT) & DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_MASK) +#define DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_MASK) >> DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_SHIFT) + +/* + * WQOS_MAP_LEVEL (R/W) + * + * Description: Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which corresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value corresponds to higher port priority. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_MASK (0xFU) +#define DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_SHIFT (0U) +#define DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_SHIFT) & DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_MASK) +#define DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_MASK) >> DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_SHIFT) + +/* Bitfield definition for register of struct array PCFG: WQOS1 */ +/* + * WQOS_MAP_TIMEOUT (R/W) + * + * Description: Specifies the timeout value for write transactions. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_MASK (0x7FFU) +#define DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_SHIFT (0U) +#define DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_SHIFT) & DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_MASK) +#define DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_MASK) >> DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_SHIFT) + +/* Bitfield definition for register of struct array SAR: BASE */ +/* + * BASE_ADDR (R/W) + * + * Description: Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_SAR_BASE_BASE_ADDR_MASK (0xFFFFFFFFUL) +#define DDRCTL_SAR_BASE_BASE_ADDR_SHIFT (0U) +#define DDRCTL_SAR_BASE_BASE_ADDR_SET(x) (((uint32_t)(x) << DDRCTL_SAR_BASE_BASE_ADDR_SHIFT) & DDRCTL_SAR_BASE_BASE_ADDR_MASK) +#define DDRCTL_SAR_BASE_BASE_ADDR_GET(x) (((uint32_t)(x) & DDRCTL_SAR_BASE_BASE_ADDR_MASK) >> DDRCTL_SAR_BASE_BASE_ADDR_SHIFT) + +/* Bitfield definition for register of struct array SAR: SIZE */ +/* + * NBLOCKS (R/W) + * + * Description: Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block size as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. + * Value After Reset: 0x0 + * Exists: Always + */ +#define DDRCTL_SAR_SIZE_NBLOCKS_MASK (0xFFU) +#define DDRCTL_SAR_SIZE_NBLOCKS_SHIFT (0U) +#define DDRCTL_SAR_SIZE_NBLOCKS_SET(x) (((uint32_t)(x) << DDRCTL_SAR_SIZE_NBLOCKS_SHIFT) & DDRCTL_SAR_SIZE_NBLOCKS_MASK) +#define DDRCTL_SAR_SIZE_NBLOCKS_GET(x) (((uint32_t)(x) & DDRCTL_SAR_SIZE_NBLOCKS_MASK) >> DDRCTL_SAR_SIZE_NBLOCKS_SHIFT) + +/* Bitfield definition for register: SBRCTL */ +/* + * SCRUB_INTERVAL (R/W) + * + * Description: Scrub interval. (512 x scrub_interval) number of clock cycles between two scrub read commands. If set to 0, scrub commands are issued back-to-back. This mode of operation (scrub_interval=0) can typically be used for scrubbing the full range of memory at once before or after SW controlled low power operations. After completing the full range of scrub while scrub_interval=0, scrub_done register is set and sbr_done_intr interrupt signal is asserted. + * Value After Reset: 0xff + * Exists: UMCTL2_SBR_EN_1==1 + */ +#define DDRCTL_SBRCTL_SCRUB_INTERVAL_MASK (0x1FFF00UL) +#define DDRCTL_SBRCTL_SCRUB_INTERVAL_SHIFT (8U) +#define DDRCTL_SBRCTL_SCRUB_INTERVAL_SET(x) (((uint32_t)(x) << DDRCTL_SBRCTL_SCRUB_INTERVAL_SHIFT) & DDRCTL_SBRCTL_SCRUB_INTERVAL_MASK) +#define DDRCTL_SBRCTL_SCRUB_INTERVAL_GET(x) (((uint32_t)(x) & DDRCTL_SBRCTL_SCRUB_INTERVAL_MASK) >> DDRCTL_SBRCTL_SCRUB_INTERVAL_SHIFT) + +/* + * SCRUB_BURST (R/W) + * + * Description: Scrub burst count. Determines the number of back-to-back scrub read commands that can be issued together when the controller is in one of the HW controlled low power modes. During low power, the period of the scrub burst becomes \"scrub_burst*scrub_interval\" cycles. + * During normal operation mode of the controller (ie. not in power-down or self refresh), scrub_burst is ignored and only one scrub command is generated. Valid values are: 1: 1 read, 2: 4 reads, 3: 16 reads, 4: 64 reads, 5: 256 reads, + * 6: 1024 reads. + * Value After Reset: 0x1 + * Exists: UMCTL2_SBR_EN_1==1 + */ +#define DDRCTL_SBRCTL_SCRUB_BURST_MASK (0x70U) +#define DDRCTL_SBRCTL_SCRUB_BURST_SHIFT (4U) +#define DDRCTL_SBRCTL_SCRUB_BURST_SET(x) (((uint32_t)(x) << DDRCTL_SBRCTL_SCRUB_BURST_SHIFT) & DDRCTL_SBRCTL_SCRUB_BURST_MASK) +#define DDRCTL_SBRCTL_SCRUB_BURST_GET(x) (((uint32_t)(x) & DDRCTL_SBRCTL_SCRUB_BURST_MASK) >> DDRCTL_SBRCTL_SCRUB_BURST_SHIFT) + +/* + * SCRUB_MODE (R/W) + * + * Description: scrub_mode:0 ECC scrubber will perform reads scrub_mode:1 ECC scrubber will perform writes Value After Reset: 0x0 + * Exists: UMCTL2_SBR_EN_1==1 + */ +#define DDRCTL_SBRCTL_SCRUB_MODE_MASK (0x4U) +#define DDRCTL_SBRCTL_SCRUB_MODE_SHIFT (2U) +#define DDRCTL_SBRCTL_SCRUB_MODE_SET(x) (((uint32_t)(x) << DDRCTL_SBRCTL_SCRUB_MODE_SHIFT) & DDRCTL_SBRCTL_SCRUB_MODE_MASK) +#define DDRCTL_SBRCTL_SCRUB_MODE_GET(x) (((uint32_t)(x) & DDRCTL_SBRCTL_SCRUB_MODE_MASK) >> DDRCTL_SBRCTL_SCRUB_MODE_SHIFT) + +/* + * SCRUB_DURING_LOWPOWER (R/W) + * + * Description: Continue scrubbing during low power. If set to 1, burst of scrubs will be issued in HW controlled low power modes. There are two such modes: automatically initiated by idleness or initiated by HW low-power (LP) interface. If set to 0, the scrubber will not attempt to send commands while the DDRC is in HW controlled low power modes. In this case, the scrubber will remember the last address issued and will automatically continue from there when the DDRC exits the LP mode. + * Value After Reset: 0x0 + * Exists: UMCTL2_SBR_EN_1==1 + */ +#define DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_MASK (0x2U) +#define DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_SHIFT (1U) +#define DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_SET(x) (((uint32_t)(x) << DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_SHIFT) & DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_MASK) +#define DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_GET(x) (((uint32_t)(x) & DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_MASK) >> DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_SHIFT) + +/* + * SCRUB_EN (R/W) + * + * Description: Enable ECC scrubber. If set to 1, enables the scrubber to generate background read commands after the memories are initialized. If set to 0, disables the scrubber, resets the address generator to 0 and clears the scrubber status. This bitfield must be accessed separately from the other bitfields in this register. + * Value After Reset: 0x0 + * Exists: UMCTL2_SBR_EN_1==1 + */ +#define DDRCTL_SBRCTL_SCRUB_EN_MASK (0x1U) +#define DDRCTL_SBRCTL_SCRUB_EN_SHIFT (0U) +#define DDRCTL_SBRCTL_SCRUB_EN_SET(x) (((uint32_t)(x) << DDRCTL_SBRCTL_SCRUB_EN_SHIFT) & DDRCTL_SBRCTL_SCRUB_EN_MASK) +#define DDRCTL_SBRCTL_SCRUB_EN_GET(x) (((uint32_t)(x) & DDRCTL_SBRCTL_SCRUB_EN_MASK) >> DDRCTL_SBRCTL_SCRUB_EN_SHIFT) + +/* Bitfield definition for register: SBRSTAT */ +/* + * SCRUB_DONE (R) + * + * Description: Scrubber done. Controller sets this bit to 1, after full range of addresses are scrubbed once while scrub_interval is set to 0. Cleared if scrub_en is set to 0 (scrubber disabled) or scrub_interval is set to a non-zero value for normal scrub operation. The interrupt signal, sbr_done_intr, is equivalent to this status bitfield. + * Value After Reset: 0x0 + * Exists: UMCTL2_SBR_EN_1==1 + */ +#define DDRCTL_SBRSTAT_SCRUB_DONE_MASK (0x2U) +#define DDRCTL_SBRSTAT_SCRUB_DONE_SHIFT (1U) +#define DDRCTL_SBRSTAT_SCRUB_DONE_GET(x) (((uint32_t)(x) & DDRCTL_SBRSTAT_SCRUB_DONE_MASK) >> DDRCTL_SBRSTAT_SCRUB_DONE_SHIFT) + +/* + * SCRUB_BUSY (R) + * + * Description: Scrubber busy. Controller sets this bit to 1 when the scrubber logic has outstanding read commands being executed. Cleared when there are no active outstanding scrub reads in the system. + * Value After Reset: 0x0 + * Exists: UMCTL2_SBR_EN_1==1 + */ +#define DDRCTL_SBRSTAT_SCRUB_BUSY_MASK (0x1U) +#define DDRCTL_SBRSTAT_SCRUB_BUSY_SHIFT (0U) +#define DDRCTL_SBRSTAT_SCRUB_BUSY_GET(x) (((uint32_t)(x) & DDRCTL_SBRSTAT_SCRUB_BUSY_MASK) >> DDRCTL_SBRSTAT_SCRUB_BUSY_SHIFT) + +/* Bitfield definition for register: SBRWDATA0 */ +/* + * SCRUB_PATTERN0 (R/W) + * + * Description: ECC Scrubber write data pattern for data bus[31:0] + * Value After Reset: 0x0 + * Exists: UMCTL2_SBR_EN_1==1 + */ +#define DDRCTL_SBRWDATA0_SCRUB_PATTERN0_MASK (0xFFFFFFFFUL) +#define DDRCTL_SBRWDATA0_SCRUB_PATTERN0_SHIFT (0U) +#define DDRCTL_SBRWDATA0_SCRUB_PATTERN0_SET(x) (((uint32_t)(x) << DDRCTL_SBRWDATA0_SCRUB_PATTERN0_SHIFT) & DDRCTL_SBRWDATA0_SCRUB_PATTERN0_MASK) +#define DDRCTL_SBRWDATA0_SCRUB_PATTERN0_GET(x) (((uint32_t)(x) & DDRCTL_SBRWDATA0_SCRUB_PATTERN0_MASK) >> DDRCTL_SBRWDATA0_SCRUB_PATTERN0_SHIFT) + + + +/* ID register group index macro definition */ +#define DDRCTL_ID_0 (0UL) +#define DDRCTL_ID_1 (1UL) +#define DDRCTL_ID_2 (2UL) +#define DDRCTL_ID_3 (3UL) +#define DDRCTL_ID_4 (4UL) +#define DDRCTL_ID_5 (5UL) +#define DDRCTL_ID_6 (6UL) +#define DDRCTL_ID_7 (7UL) +#define DDRCTL_ID_8 (8UL) +#define DDRCTL_ID_9 (9UL) +#define DDRCTL_ID_10 (10UL) +#define DDRCTL_ID_11 (11UL) +#define DDRCTL_ID_12 (12UL) +#define DDRCTL_ID_13 (13UL) +#define DDRCTL_ID_14 (14UL) +#define DDRCTL_ID_15 (15UL) + +/* PCFG register group index macro definition */ +#define DDRCTL_PCFG_0 (0UL) +#define DDRCTL_PCFG_1 (1UL) +#define DDRCTL_PCFG_2 (2UL) +#define DDRCTL_PCFG_3 (3UL) +#define DDRCTL_PCFG_4 (4UL) +#define DDRCTL_PCFG_5 (5UL) +#define DDRCTL_PCFG_6 (6UL) +#define DDRCTL_PCFG_7 (7UL) +#define DDRCTL_PCFG_8 (8UL) +#define DDRCTL_PCFG_9 (9UL) +#define DDRCTL_PCFG_10 (10UL) +#define DDRCTL_PCFG_11 (11UL) +#define DDRCTL_PCFG_12 (12UL) +#define DDRCTL_PCFG_13 (13UL) +#define DDRCTL_PCFG_14 (14UL) +#define DDRCTL_PCFG_15 (15UL) + +/* SAR register group index macro definition */ +#define DDRCTL_SAR_0 (0UL) +#define DDRCTL_SAR_1 (1UL) +#define DDRCTL_SAR_2 (2UL) +#define DDRCTL_SAR_3 (3UL) + + +#endif /* HPM_DDRCTL_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ddrphy_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ddrphy_regs.h new file mode 100644 index 00000000000..7401f09af9e --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ddrphy_regs.h @@ -0,0 +1,5989 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_DDRPHY_H +#define HPM_DDRPHY_H + +typedef struct { + __R uint32_t RIDR; /* 0x0: Revision Identification Register */ + __RW uint32_t PIR; /* 0x4: PHY Initialization Register (PIR) */ + __RW uint32_t PGCR0; /* 0x8: PHY General Configuration Registers 0-1 (PGCR0- 1) */ + __RW uint32_t PGCR1; /* 0xC: PHY General Configuration Registers 0-1 (PGCR0- 1) */ + __R uint32_t PGSR0; /* 0x10: “PHY General Status Registers 0-1 (PGSR0-1)” on page 89 */ + __R uint32_t PGSR1; /* 0x14: “PHY General Status Registers 0-1 (PGSR0-1)” on page 89 */ + __RW uint32_t PLLCR; /* 0x18: “PLL Control Register (PLLCR)” on page 91 */ + __RW uint32_t PTR0; /* 0x1C: PHY Timing Registers 0-4 (PTR0-4) */ + __RW uint32_t PTR1; /* 0x20: PHY Timing Registers 0-4 (PTR0-4) */ + __RW uint32_t PTR2; /* 0x24: PHY Timing Registers 0-4 (PTR0-4) */ + __RW uint32_t PTR3; /* 0x28: PHY Timing Registers 0-4 (PTR0-4) */ + __RW uint32_t PTR4; /* 0x2C: PHY Timing Registers 0-4 (PTR0-4) */ + __RW uint32_t ACMDLR; /* 0x30: “AC Master Delay Line Register (ACMDLR)” on page 96 */ + __RW uint32_t ACBDLR; /* 0x34: “AC Bit Delay Line Register (ACBDLR)” on page 96 */ + __RW uint32_t ACIOCR; /* 0x38: “AC I/O Configuration Register (ACIOCR)” on page 97 */ + __RW uint32_t DXCCR; /* 0x3C: “DATX8 Common Configuration Register (DXCCR)” on page 99 */ + __RW uint32_t DSGCR; /* 0x40: “DDR System General Configuration Register (DSGCR)” on page 101 */ + __RW uint32_t DCR; /* 0x44: “DRAM Configuration Register (DCR)” on page 103 */ + __RW uint32_t DTPR0; /* 0x48: DRAM Timing Parameters Register 0-2 (DTPR0-2) */ + __RW uint32_t DTPR1; /* 0x4C: DRAM Timing Parameters Register 0-2 (DTPR0-2) */ + __RW uint32_t DTPR2; /* 0x50: DRAM Timing Parameters Register 0-2 (DTPR0-2) */ + union { + __RW uint32_t MR0; /* 0x54: “Mode Register 0 (MR0)” on page 108 */ + __RW uint32_t MR; /* 0x54: */ + }; + union { + __RW uint32_t MR1; /* 0x58: “Mode Register 1 (MR1)” on page 111 */ + __RW uint32_t EMR; /* 0x58: */ + }; + union { + __RW uint32_t MR2; /* 0x5C: “Mode Register 2/Extended Mode Register 2 (MR2/EMR2)” on page 114 */ + __RW uint32_t EMR2; /* 0x5C: */ + }; + union { + __RW uint32_t MR3; /* 0x60: “Mode Register 3 (MR3)” on page 116 */ + __RW uint32_t EMR3; /* 0x60: */ + }; + __RW uint32_t ODTCR; /* 0x64: “ODT Configuration Register (ODTCR)” on page 117 */ + __RW uint32_t DTCR; /* 0x68: “Data Training Configuration Register (DTCR)” on page 118 */ + __RW uint32_t DTAR0; /* 0x6C: Data Training Address Register 0-3 (DTAR0-3) */ + __RW uint32_t DTAR1; /* 0x70: Data Training Address Register 0-3 (DTAR0-3) */ + __RW uint32_t DTAR2; /* 0x74: Data Training Address Register 0-3 (DTAR0-3) */ + __RW uint32_t DTAR3; /* 0x78: Data Training Address Register 0-3 (DTAR0-3) */ + __RW uint32_t DTDR0; /* 0x7C: Data Training Eye Data Register 0-1 (DTEDR0-1) */ + __RW uint32_t DTDR1; /* 0x80: Data Training Eye Data Register 0-1 (DTEDR0-1) */ + __R uint32_t DTEDR0; /* 0x84: Data Training Eye Data Register 0-1 (DTEDR0-1) */ + __R uint32_t DTEDR1; /* 0x88: Data Training Eye Data Register 0-1 (DTEDR0-1) */ + __RW uint32_t PGCR2; /* 0x8C: “PHY General Configuration Register 2 (PGCR2)” on page 87 */ + __R uint8_t RESERVED0[32]; /* 0x90 - 0xAF: Reserved */ + __R uint32_t RDIMMGCR0; /* 0xB0: RDIMM General Configuration Register 0-1 (RDIMMGCR0-1) */ + __R uint32_t RDIMMGCR1; /* 0xB4: RDIMM General Configuration Register 0-1 (RDIMMGCR0-1) */ + __R uint32_t RDIMMCR0; /* 0xB8: RDIMM Control Register 0-1 (RDIMMCR0-1) */ + __R uint32_t RDIMMCR1; /* 0xBC: RDIMM Control Register 0-1 (RDIMMCR0-1) */ + __RW uint32_t DCUAR; /* 0xC0: “DCU Address Register (DCUAR)” on page 129 */ + __RW uint32_t DCUDR; /* 0xC4: “DCU Data Register (DCUDR)” on page 130 */ + __RW uint32_t DCURR; /* 0xC8: “DCU Run Register (DCURR)” on page 130 */ + __RW uint32_t DCULR; /* 0xCC: “DCU Loop Register (DCULR)” on page 131 */ + __RW uint32_t DCUGCR; /* 0xD0: “DCU General Configuration Register (DCUGCR)” on page 132 */ + __RW uint32_t DCUTPR; /* 0xD4: “DCU Timing Parameter Register (DCUTPR)” on page 132 */ + __R uint32_t DCUSR0; /* 0xD8: DCU Status Register 0-1 (DCUSR0-1) */ + __R uint32_t DCUSR1; /* 0xDC: DCU Status Register 0-1 (DCUSR0-1) */ + __R uint8_t RESERVED1[32]; /* 0xE0 - 0xFF: Reserved */ + __RW uint32_t BISTRR; /* 0x100: “BIST Run Register (BISTRR)” on page 133 */ + __RW uint32_t BISTWCR; /* 0x104: “BIST Word Count Register (BISTWCR)” on page 136 */ + __RW uint32_t BISTMSKR0; /* 0x108: BIST Mask Register 0-2 (BISTMSKR0-2) */ + __RW uint32_t BISTMSKR1; /* 0x10C: BIST Mask Register 0-2 (BISTMSKR0-2) */ + __RW uint32_t BISTMSKR2; /* 0x110: BIST Mask Register 0-2 (BISTMSKR0-2) */ + __RW uint32_t BISTLSR; /* 0x114: “BIST LFSR Seed Register (BISTLSR)” on page 137 */ + __RW uint32_t BISTAR0; /* 0x118: BIST Address Register 0-2 (BISTAR0-2) */ + __RW uint32_t BISTAR1; /* 0x11C: BIST Address Register 0-2 (BISTAR0-2) */ + __RW uint32_t BISTAR2; /* 0x120: BIST Address Register 0-2 (BISTAR0-2) */ + __RW uint32_t BISTUDPR; /* 0x124: “BIST User Data Pattern Register (BISTUDPR)” on page 138 */ + __R uint32_t BISTGSR; /* 0x128: “BIST General Status Register (BISTGSR)” on page 139 */ + __R uint32_t BISTWER; /* 0x12C: “BIST Word Error Register (BISTWER)” on page 139 */ + __R uint32_t BISTBER0; /* 0x130: BIST Bit Error Register 0-3 (BISTBER0-3) */ + __R uint32_t BISTBER1; /* 0x134: BIST Bit Error Register 0-3 (BISTBER0-3) */ + __R uint32_t BISTBER2; /* 0x138: BIST Bit Error Register 0-3 (BISTBER0-3) */ + __R uint32_t BISTBER3; /* 0x13C: BIST Bit Error Register 0-3 (BISTBER0-3) */ + __R uint32_t BISTWCSR; /* 0x140: “BIST Word Count Status Register (BISTWCSR)” on page 141 */ + __R uint32_t BISTFWR0; /* 0x144: BIST Fail Word Register 0-2 (BISTFWR0-2) */ + __R uint32_t BISTFWR1; /* 0x148: BIST Fail Word Register 0-2 (BISTFWR0-2) */ + __R uint32_t BISTFWR2; /* 0x14C: BIST Fail Word Register 0-2 (BISTFWR0-2) */ + __R uint8_t RESERVED2[36]; /* 0x150 - 0x173: Reserved */ + __RW uint32_t AACR; /* 0x174: “Anti-Aging Control Register (AACR)” on page 143 */ + __RW uint32_t GPR0; /* 0x178: General Purpose Register 0-1 (GPR0-1) */ + __RW uint32_t GPR1; /* 0x17C: General Purpose Register 0-1 (GPR0-1) */ + struct { + __RW uint32_t CR0; /* 0x180: Impedance Control Register 0-1 (ZQnCR0-1) */ + __RW uint32_t CR1; /* 0x184: Impedance Control Register 0-1 (ZQnCR0-1) */ + __R uint32_t SR0; /* 0x188: Impedance Status Register 0-1 (ZQnSR0-1) */ + __R uint32_t SR1; /* 0x18C: Impedance Status Register 0-1 (ZQnSR0-1) */ + } ZQ[4]; + struct { + __RW uint32_t GCR; /* 0x1C0: “DATX8 General Configuration Register (DXnGCR)” on page 148 */ + __R uint32_t GSR0; /* 0x1C4: DATX8 General Status Registers 0-2 (DXnGSR0-2) */ + __R uint32_t GSR1; /* 0x1C8: DATX8 General Status Registers 0-2 (DXnGSR0-2) */ + __RW uint32_t BDLR0; /* 0x1CC: DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) */ + __RW uint32_t BDLR1; /* 0x1D0: DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) */ + __RW uint32_t BDLR2; /* 0x1D4: DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) */ + __RW uint32_t BDLR3; /* 0x1D8: DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) */ + __RW uint32_t BDLR4; /* 0x1DC: DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) */ + __RW uint32_t LCDLR0; /* 0x1E0: DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) */ + __RW uint32_t LCDLR1; /* 0x1E4: DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) */ + __RW uint32_t LCDLR2; /* 0x1E8: DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) */ + __RW uint32_t MDLR; /* 0x1EC: “DATX8 Master Delay Line Register (DXnMDLR)” on page 157 */ + __RW uint32_t GTR; /* 0x1F0: “DATX8 General Timing Register (DXnGTR)” on page 159 */ + __RW uint32_t GSR2; /* 0x1F4: “DATX8 General Status Register 2 (DXnGSR2)” on page 152 */ + __R uint8_t RESERVED0[8]; /* 0x1F8 - 0x1FF: Reserved */ + } DX[9]; +} DDRPHY_Type; + + +/* Bitfield definition for register: RIDR */ +/* + * UDRID (R) + * + * User-Defined Revision ID: General purpose revision identification set by the user. + */ +#define DDRPHY_RIDR_UDRID_MASK (0xFF000000UL) +#define DDRPHY_RIDR_UDRID_SHIFT (24U) +#define DDRPHY_RIDR_UDRID_GET(x) (((uint32_t)(x) & DDRPHY_RIDR_UDRID_MASK) >> DDRPHY_RIDR_UDRID_SHIFT) + +/* + * PHYMJR (R) + * + * PHY Major Revision: Indicates major revision of the PHY such addition of the features that make the new version not compatible with previous versions. + */ +#define DDRPHY_RIDR_PHYMJR_MASK (0xF00000UL) +#define DDRPHY_RIDR_PHYMJR_SHIFT (20U) +#define DDRPHY_RIDR_PHYMJR_GET(x) (((uint32_t)(x) & DDRPHY_RIDR_PHYMJR_MASK) >> DDRPHY_RIDR_PHYMJR_SHIFT) + +/* + * PHYMDR (R) + * + * PHY Moderate Revision: Indicates moderate revision of the PHY such as addition of new features. Normally the new version is still compatible with previous versions. + */ +#define DDRPHY_RIDR_PHYMDR_MASK (0xF0000UL) +#define DDRPHY_RIDR_PHYMDR_SHIFT (16U) +#define DDRPHY_RIDR_PHYMDR_GET(x) (((uint32_t)(x) & DDRPHY_RIDR_PHYMDR_MASK) >> DDRPHY_RIDR_PHYMDR_SHIFT) + +/* + * PHYMNR (R) + * + * PHY Minor Revision: Indicates minor update of the PHY such as bug fixes. Normally no new features are included. + */ +#define DDRPHY_RIDR_PHYMNR_MASK (0xF000U) +#define DDRPHY_RIDR_PHYMNR_SHIFT (12U) +#define DDRPHY_RIDR_PHYMNR_GET(x) (((uint32_t)(x) & DDRPHY_RIDR_PHYMNR_MASK) >> DDRPHY_RIDR_PHYMNR_SHIFT) + +/* + * PUBMJR (R) + * + * PUB Major Revision: Indicates major revision of the PUB such addition of the features that make the new version not compatible with previous versions. + */ +#define DDRPHY_RIDR_PUBMJR_MASK (0xF00U) +#define DDRPHY_RIDR_PUBMJR_SHIFT (8U) +#define DDRPHY_RIDR_PUBMJR_GET(x) (((uint32_t)(x) & DDRPHY_RIDR_PUBMJR_MASK) >> DDRPHY_RIDR_PUBMJR_SHIFT) + +/* + * PUBMDR (R) + * + * PUB Moderate Revision: Indicates moderate revision of the PUB such as addition of new features. Normally the new version is still compatible with previous versions. + */ +#define DDRPHY_RIDR_PUBMDR_MASK (0xF0U) +#define DDRPHY_RIDR_PUBMDR_SHIFT (4U) +#define DDRPHY_RIDR_PUBMDR_GET(x) (((uint32_t)(x) & DDRPHY_RIDR_PUBMDR_MASK) >> DDRPHY_RIDR_PUBMDR_SHIFT) + +/* + * PUBMNR (R) + * + * PUB Minor Revision: Indicates minor update of the PUB such as bug fixes. Normally no new features are included. + */ +#define DDRPHY_RIDR_PUBMNR_MASK (0xFU) +#define DDRPHY_RIDR_PUBMNR_SHIFT (0U) +#define DDRPHY_RIDR_PUBMNR_GET(x) (((uint32_t)(x) & DDRPHY_RIDR_PUBMNR_MASK) >> DDRPHY_RIDR_PUBMNR_SHIFT) + +/* Bitfield definition for register: PIR */ +/* + * INITBYP (R/W) + * + * Initialization Bypass: Bypasses or stops, if set, all initialization routines currently running, including PHY initialization, DRAM initialization, and PHY training. + * Initialization may be triggered manually using INIT and the other relevant bits of the PIR register. This bit is self-clearing. + */ +#define DDRPHY_PIR_INITBYP_MASK (0x80000000UL) +#define DDRPHY_PIR_INITBYP_SHIFT (31U) +#define DDRPHY_PIR_INITBYP_SET(x) (((uint32_t)(x) << DDRPHY_PIR_INITBYP_SHIFT) & DDRPHY_PIR_INITBYP_MASK) +#define DDRPHY_PIR_INITBYP_GET(x) (((uint32_t)(x) & DDRPHY_PIR_INITBYP_MASK) >> DDRPHY_PIR_INITBYP_SHIFT) + +/* + * ZCALBYP (R/W) + * + * Impedance Calibration Bypass: Bypasses or stops, if set, impedance calibration of all ZQ control blocks that automatically triggers after reset. Impedance calibration may be triggered manually using INIT and ZCAL bits of the PIR register. This bit is self-clearing. + */ +#define DDRPHY_PIR_ZCALBYP_MASK (0x40000000UL) +#define DDRPHY_PIR_ZCALBYP_SHIFT (30U) +#define DDRPHY_PIR_ZCALBYP_SET(x) (((uint32_t)(x) << DDRPHY_PIR_ZCALBYP_SHIFT) & DDRPHY_PIR_ZCALBYP_MASK) +#define DDRPHY_PIR_ZCALBYP_GET(x) (((uint32_t)(x) & DDRPHY_PIR_ZCALBYP_MASK) >> DDRPHY_PIR_ZCALBYP_SHIFT) + +/* + * DCALBYP (R/W) + * + * Digital Delay Line (DDL) Calibration Bypass: Bypasses or stops, if set, DDL calibration that automatically triggers after reset. DDL calibration may be triggered manually using INIT and DCAL bits of the PIR register. This bit is self- clearing. + */ +#define DDRPHY_PIR_DCALBYP_MASK (0x20000000UL) +#define DDRPHY_PIR_DCALBYP_SHIFT (29U) +#define DDRPHY_PIR_DCALBYP_SET(x) (((uint32_t)(x) << DDRPHY_PIR_DCALBYP_SHIFT) & DDRPHY_PIR_DCALBYP_MASK) +#define DDRPHY_PIR_DCALBYP_GET(x) (((uint32_t)(x) & DDRPHY_PIR_DCALBYP_MASK) >> DDRPHY_PIR_DCALBYP_SHIFT) + +/* + * LOCKBYP (R/W) + * + * PLL Lock Bypass: Bypasses or stops, if set, the waiting of PLLs to lock. PLL lock wait is automatically triggered after reset. PLL lock wait may be triggered manually using INIT and PLLINIT bits of the PIR register. This bit is self-clearing. + */ +#define DDRPHY_PIR_LOCKBYP_MASK (0x10000000UL) +#define DDRPHY_PIR_LOCKBYP_SHIFT (28U) +#define DDRPHY_PIR_LOCKBYP_SET(x) (((uint32_t)(x) << DDRPHY_PIR_LOCKBYP_SHIFT) & DDRPHY_PIR_LOCKBYP_MASK) +#define DDRPHY_PIR_LOCKBYP_GET(x) (((uint32_t)(x) & DDRPHY_PIR_LOCKBYP_MASK) >> DDRPHY_PIR_LOCKBYP_SHIFT) + +/* + * CLRSR (R/W) + * + * Clear Status Registers: Writing 1 to this bit clears (reset to 0) select status bits in register PGSR0. + * This bit is primarily for debug purposes and is typically not needed during normal functional operation. It can be used when PGSR.IDONE=1, to manually clear a selection of the PGSR status bits, although starting a new initialization process (PIR[0].INIT = 1’b1) automatically clears the PGSR status bits associated with the initialization steps enabled. + * The following list describes which bits within the PGSR0 register are cleared when CLRSR is set to 1’b1 and which bits are not cleared: + * The following bits are not cleared by PIR[27] (CLRSR): + * PGSR0[31] (APLOCK) + * PGSR0[29:28] (PLDONE_CHN) + * PGSR0[23] (WLAERR) + * PGSR0[21] (WLERR) + * PGSR0[4] (DIDONE) + * PGSR0[2] (DCDONE) + * PGSR0[1] (PLDONE) + * PGSR0[0] (IDONE) + * The following bits are always zero: + * PGSR0[30] (reserved) + * PGSR0[19:12] (reserved) + * The following bits are cleared unconditionally by PIR[27] (CLRSR): + * PGSR0[27] (WEERR) + * PGSR0[26] (REERR) + * PGSR0[25] (WDERR) + * PGSR0[24] (RDERR) + * - PGSR0[22] (QSGERR) + * - PGSR0[20] (ZCERR) + * - PGSR0[11] (WEDONE) + * - PGSR0[10] (REDONE) + * - PGSR0[9] (WDDONE) + * - PGSR0[8] (RDDONE) + * - PGSR0[7] (WLADONE) + * - PGSR0[6] (QSGDONE) + * - PGSR0[5] (WLDONE) + * - PGSR0[3] (ZCDONE) + */ +#define DDRPHY_PIR_CLRSR_MASK (0x8000000UL) +#define DDRPHY_PIR_CLRSR_SHIFT (27U) +#define DDRPHY_PIR_CLRSR_SET(x) (((uint32_t)(x) << DDRPHY_PIR_CLRSR_SHIFT) & DDRPHY_PIR_CLRSR_MASK) +#define DDRPHY_PIR_CLRSR_GET(x) (((uint32_t)(x) & DDRPHY_PIR_CLRSR_MASK) >> DDRPHY_PIR_CLRSR_SHIFT) + +/* + * RDIMMINIT (R/W) + * + * RDIMM Initialization: Executes the RDIMM buffer chip initialization before executing DRAM initialization. The RDIMM buffer chip initialization is run after the DRAM is reset and CKE have been driven high by the DRAM initialization sequence. + */ +#define DDRPHY_PIR_RDIMMINIT_MASK (0x80000UL) +#define DDRPHY_PIR_RDIMMINIT_SHIFT (19U) +#define DDRPHY_PIR_RDIMMINIT_SET(x) (((uint32_t)(x) << DDRPHY_PIR_RDIMMINIT_SHIFT) & DDRPHY_PIR_RDIMMINIT_MASK) +#define DDRPHY_PIR_RDIMMINIT_GET(x) (((uint32_t)(x) & DDRPHY_PIR_RDIMMINIT_MASK) >> DDRPHY_PIR_RDIMMINIT_SHIFT) + +/* + * CTLDINIT (R/W) + * + * Controller DRAM Initialization: Indicates, if set, that DRAM initialization will be performed by the controller. Otherwise if not set it indicates that DRAM initialization will be performed using the built-in initialization sequence or using software through the configuration port. + */ +#define DDRPHY_PIR_CTLDINIT_MASK (0x40000UL) +#define DDRPHY_PIR_CTLDINIT_SHIFT (18U) +#define DDRPHY_PIR_CTLDINIT_SET(x) (((uint32_t)(x) << DDRPHY_PIR_CTLDINIT_SHIFT) & DDRPHY_PIR_CTLDINIT_MASK) +#define DDRPHY_PIR_CTLDINIT_GET(x) (((uint32_t)(x) & DDRPHY_PIR_CTLDINIT_MASK) >> DDRPHY_PIR_CTLDINIT_SHIFT) + +/* + * PLLBYP (R/W) + * + * PLL Bypass: A setting of 1 on this bit will put all PHY PLLs in bypass mode. + */ +#define DDRPHY_PIR_PLLBYP_MASK (0x20000UL) +#define DDRPHY_PIR_PLLBYP_SHIFT (17U) +#define DDRPHY_PIR_PLLBYP_SET(x) (((uint32_t)(x) << DDRPHY_PIR_PLLBYP_SHIFT) & DDRPHY_PIR_PLLBYP_MASK) +#define DDRPHY_PIR_PLLBYP_GET(x) (((uint32_t)(x) & DDRPHY_PIR_PLLBYP_MASK) >> DDRPHY_PIR_PLLBYP_SHIFT) + +/* + * ICPC (R/W) + * + * Initialization Complete Pin Configuration: Specifies how the DFI initialization complete output pin (dfi_init_complete) should be used to indicate the status of initialization. Valid value are: + * 0 = Asserted after PHY initialization (DLL locking and impedance calibration) is complete. + * 1 = Asserted after PHY initialization is complete and the triggered the PUB initialization (DRAM initialization, data training, or initialization trigger with no selected initialization) is complete. + */ +#define DDRPHY_PIR_ICPC_MASK (0x10000UL) +#define DDRPHY_PIR_ICPC_SHIFT (16U) +#define DDRPHY_PIR_ICPC_SET(x) (((uint32_t)(x) << DDRPHY_PIR_ICPC_SHIFT) & DDRPHY_PIR_ICPC_MASK) +#define DDRPHY_PIR_ICPC_GET(x) (((uint32_t)(x) & DDRPHY_PIR_ICPC_MASK) >> DDRPHY_PIR_ICPC_SHIFT) + +/* + * WREYE (R/W) + * + * Write Data Eye Training: Executes a PUB training routine to maximize the write data eye. + */ +#define DDRPHY_PIR_WREYE_MASK (0x8000U) +#define DDRPHY_PIR_WREYE_SHIFT (15U) +#define DDRPHY_PIR_WREYE_SET(x) (((uint32_t)(x) << DDRPHY_PIR_WREYE_SHIFT) & DDRPHY_PIR_WREYE_MASK) +#define DDRPHY_PIR_WREYE_GET(x) (((uint32_t)(x) & DDRPHY_PIR_WREYE_MASK) >> DDRPHY_PIR_WREYE_SHIFT) + +/* + * RDEYE (R/W) + * + * Read Data Eye Training: Executes a PUB training routine to maximize the read data eye. + */ +#define DDRPHY_PIR_RDEYE_MASK (0x4000U) +#define DDRPHY_PIR_RDEYE_SHIFT (14U) +#define DDRPHY_PIR_RDEYE_SET(x) (((uint32_t)(x) << DDRPHY_PIR_RDEYE_SHIFT) & DDRPHY_PIR_RDEYE_MASK) +#define DDRPHY_PIR_RDEYE_GET(x) (((uint32_t)(x) & DDRPHY_PIR_RDEYE_MASK) >> DDRPHY_PIR_RDEYE_SHIFT) + +/* + * WRDSKW (R/W) + * + * Write Data Bit Deskew: Executes a PUB training routine to deskew the DQ bits during write. + */ +#define DDRPHY_PIR_WRDSKW_MASK (0x2000U) +#define DDRPHY_PIR_WRDSKW_SHIFT (13U) +#define DDRPHY_PIR_WRDSKW_SET(x) (((uint32_t)(x) << DDRPHY_PIR_WRDSKW_SHIFT) & DDRPHY_PIR_WRDSKW_MASK) +#define DDRPHY_PIR_WRDSKW_GET(x) (((uint32_t)(x) & DDRPHY_PIR_WRDSKW_MASK) >> DDRPHY_PIR_WRDSKW_SHIFT) + +/* + * RDDSKW (R/W) + * + * Read Data Bit Deskew: Executes a PUB training routine to deskew the DQ bits during read. + */ +#define DDRPHY_PIR_RDDSKW_MASK (0x1000U) +#define DDRPHY_PIR_RDDSKW_SHIFT (12U) +#define DDRPHY_PIR_RDDSKW_SET(x) (((uint32_t)(x) << DDRPHY_PIR_RDDSKW_SHIFT) & DDRPHY_PIR_RDDSKW_MASK) +#define DDRPHY_PIR_RDDSKW_GET(x) (((uint32_t)(x) & DDRPHY_PIR_RDDSKW_MASK) >> DDRPHY_PIR_RDDSKW_SHIFT) + +/* + * WLADJ (R/W) + * + * Write Leveling Adjust (DDR3 Only): Executes a PUB training routine that re- adjusts the write latency used during write in case the write leveling routine changed the expected latency. + * Note: Ensure that the DCU command cache is cleared prior to running WLADJ. + */ +#define DDRPHY_PIR_WLADJ_MASK (0x800U) +#define DDRPHY_PIR_WLADJ_SHIFT (11U) +#define DDRPHY_PIR_WLADJ_SET(x) (((uint32_t)(x) << DDRPHY_PIR_WLADJ_SHIFT) & DDRPHY_PIR_WLADJ_MASK) +#define DDRPHY_PIR_WLADJ_GET(x) (((uint32_t)(x) & DDRPHY_PIR_WLADJ_MASK) >> DDRPHY_PIR_WLADJ_SHIFT) + +/* + * QSGATE (R/W) + * + * Read DQS Gate Training: Executes a PUB training routine to determine the optimum position of the read data DQS strobe for maximum system timing margins. + */ +#define DDRPHY_PIR_QSGATE_MASK (0x400U) +#define DDRPHY_PIR_QSGATE_SHIFT (10U) +#define DDRPHY_PIR_QSGATE_SET(x) (((uint32_t)(x) << DDRPHY_PIR_QSGATE_SHIFT) & DDRPHY_PIR_QSGATE_MASK) +#define DDRPHY_PIR_QSGATE_GET(x) (((uint32_t)(x) & DDRPHY_PIR_QSGATE_MASK) >> DDRPHY_PIR_QSGATE_SHIFT) + +/* + * WL (R/W) + * + * Write Leveling (DDR3 Only): Executes a PUB write leveling routine. + */ +#define DDRPHY_PIR_WL_MASK (0x200U) +#define DDRPHY_PIR_WL_SHIFT (9U) +#define DDRPHY_PIR_WL_SET(x) (((uint32_t)(x) << DDRPHY_PIR_WL_SHIFT) & DDRPHY_PIR_WL_MASK) +#define DDRPHY_PIR_WL_GET(x) (((uint32_t)(x) & DDRPHY_PIR_WL_MASK) >> DDRPHY_PIR_WL_SHIFT) + +/* + * DRAMINIT (R/W) + * + * DRAM Initialization: Executes the DRAM initialization sequence. + */ +#define DDRPHY_PIR_DRAMINIT_MASK (0x100U) +#define DDRPHY_PIR_DRAMINIT_SHIFT (8U) +#define DDRPHY_PIR_DRAMINIT_SET(x) (((uint32_t)(x) << DDRPHY_PIR_DRAMINIT_SHIFT) & DDRPHY_PIR_DRAMINIT_MASK) +#define DDRPHY_PIR_DRAMINIT_GET(x) (((uint32_t)(x) & DDRPHY_PIR_DRAMINIT_MASK) >> DDRPHY_PIR_DRAMINIT_SHIFT) + +/* + * DRAMRST (R/W) + * + * DRAM Reset (DDR3 Only): Issues a reset to the DRAM (by driving the DRAM reset pin low) and wait 200us. This can be triggered in isolation or with the full DRAM initialization (DRAMINIT). For the later case, the reset is issued and 200us is waited before starting the full initialization sequence. + */ +#define DDRPHY_PIR_DRAMRST_MASK (0x80U) +#define DDRPHY_PIR_DRAMRST_SHIFT (7U) +#define DDRPHY_PIR_DRAMRST_SET(x) (((uint32_t)(x) << DDRPHY_PIR_DRAMRST_SHIFT) & DDRPHY_PIR_DRAMRST_MASK) +#define DDRPHY_PIR_DRAMRST_GET(x) (((uint32_t)(x) & DDRPHY_PIR_DRAMRST_MASK) >> DDRPHY_PIR_DRAMRST_SHIFT) + +/* + * PHYRST (R/W) + * + * PHY Reset: Resets the AC and DATX8 modules by asserting the AC/DATX8 reset pin. + */ +#define DDRPHY_PIR_PHYRST_MASK (0x40U) +#define DDRPHY_PIR_PHYRST_SHIFT (6U) +#define DDRPHY_PIR_PHYRST_SET(x) (((uint32_t)(x) << DDRPHY_PIR_PHYRST_SHIFT) & DDRPHY_PIR_PHYRST_MASK) +#define DDRPHY_PIR_PHYRST_GET(x) (((uint32_t)(x) & DDRPHY_PIR_PHYRST_MASK) >> DDRPHY_PIR_PHYRST_SHIFT) + +/* + * DCAL (R/W) + * + * Digital Delay Line (DDL) Calibration: Performs PHY delay line calibration. + */ +#define DDRPHY_PIR_DCAL_MASK (0x20U) +#define DDRPHY_PIR_DCAL_SHIFT (5U) +#define DDRPHY_PIR_DCAL_SET(x) (((uint32_t)(x) << DDRPHY_PIR_DCAL_SHIFT) & DDRPHY_PIR_DCAL_MASK) +#define DDRPHY_PIR_DCAL_GET(x) (((uint32_t)(x) & DDRPHY_PIR_DCAL_MASK) >> DDRPHY_PIR_DCAL_SHIFT) + +/* + * PLLINIT (R/W) + * + * PLL Initialization: Executes the PLL initialization sequence which includes correct driving of PLL power-down, reset and gear shift pins, and then waiting for the PHY PLLs to lock. + */ +#define DDRPHY_PIR_PLLINIT_MASK (0x10U) +#define DDRPHY_PIR_PLLINIT_SHIFT (4U) +#define DDRPHY_PIR_PLLINIT_SET(x) (((uint32_t)(x) << DDRPHY_PIR_PLLINIT_SHIFT) & DDRPHY_PIR_PLLINIT_MASK) +#define DDRPHY_PIR_PLLINIT_GET(x) (((uint32_t)(x) & DDRPHY_PIR_PLLINIT_MASK) >> DDRPHY_PIR_PLLINIT_SHIFT) + +/* + * ZCAL (R/W) + * + * Impedance Calibration: Performs PHY impedance calibration. When set the impedance calibration will be performed in parallel with PHY initialization (PLL initialization + DDL calibration + PHY reset). + */ +#define DDRPHY_PIR_ZCAL_MASK (0x2U) +#define DDRPHY_PIR_ZCAL_SHIFT (1U) +#define DDRPHY_PIR_ZCAL_SET(x) (((uint32_t)(x) << DDRPHY_PIR_ZCAL_SHIFT) & DDRPHY_PIR_ZCAL_MASK) +#define DDRPHY_PIR_ZCAL_GET(x) (((uint32_t)(x) & DDRPHY_PIR_ZCAL_MASK) >> DDRPHY_PIR_ZCAL_SHIFT) + +/* + * INIT (R/W) + * + * Initialization Trigger: A write of '1' to this bit triggers the DDR system initialization, including PHY initialization, DRAM initialization, and PHY training. The exact initialization steps to be executed are specified in bits 1 to 15 of this register. A bit setting of 1 means the step will be executed as part of the initialization sequence, while a setting of ‘0’ means the step will be bypassed. The initialization trigger bit is self-clearing. + */ +#define DDRPHY_PIR_INIT_MASK (0x1U) +#define DDRPHY_PIR_INIT_SHIFT (0U) +#define DDRPHY_PIR_INIT_SET(x) (((uint32_t)(x) << DDRPHY_PIR_INIT_SHIFT) & DDRPHY_PIR_INIT_MASK) +#define DDRPHY_PIR_INIT_GET(x) (((uint32_t)(x) & DDRPHY_PIR_INIT_MASK) >> DDRPHY_PIR_INIT_SHIFT) + +/* Bitfield definition for register: PGCR0 */ +/* + * CKEN (R/W) + * + * CK Enable: Controls whether the CK going to the SDRAM is enabled (toggling) or disabled (static value) and whether the CK is inverted. Two bits for each of the up to three CK pairs. Valid values for the two bits are: + * 00 = CK disabled (Driven to constant 0) 01 = CK toggling with inverted polarity + * 10 = CK toggling with normal polarity (This should be the default setting) 11 = CK disabled (Driven to constant 1) + */ +#define DDRPHY_PGCR0_CKEN_MASK (0xFC000000UL) +#define DDRPHY_PGCR0_CKEN_SHIFT (26U) +#define DDRPHY_PGCR0_CKEN_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_CKEN_SHIFT) & DDRPHY_PGCR0_CKEN_MASK) +#define DDRPHY_PGCR0_CKEN_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_CKEN_MASK) >> DDRPHY_PGCR0_CKEN_SHIFT) + +/* + * PUBMODE (R/W) + * + * Enables, if set, the PUB to control the interface to the PHY and SDRAM. In this mode the DFI commands from the controller are ignored. The bit must be set to 0 after the system determines it is convenient to pass control of the DFI bus to the controller. When set to 0 the DFI interface has control of the PHY and SDRAM interface except when triggering pub operations such as BIST, DCU or data training. + */ +#define DDRPHY_PGCR0_PUBMODE_MASK (0x2000000UL) +#define DDRPHY_PGCR0_PUBMODE_SHIFT (25U) +#define DDRPHY_PGCR0_PUBMODE_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_PUBMODE_SHIFT) & DDRPHY_PGCR0_PUBMODE_MASK) +#define DDRPHY_PGCR0_PUBMODE_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_PUBMODE_MASK) >> DDRPHY_PGCR0_PUBMODE_SHIFT) + +/* + * DTOSEL (R/W) + * + * Digital Test Output Select: Selects the PHY digital test output that is driven onto PHY digital test output (phy_dto) pin: Valid values are: + * 00000 = DATX8 0 PLL digital test output 00001 = DATX8 1 PLL digital test output 00010 = DATX8 2 PLL digital test output 00011 = DATX8 3 PLL digital test output 00100 = DATX8 4 PLL digital test output 00101 = DATX8 5 PLL digital test output 00110 = DATX8 6 PLL digital test output 00111 = DATX8 7 PLL digital test output 01000 = DATX8 8 PLL digital test output 01001 = AC PLL digital test output 01010 – 01111 = Reserved + * 10000 = DATX8 0 delay line digital test output 10001 = DATX8 1 delay line digital test output 10010 = DATX8 2 delay line digital test output 10011 = DATX8 3 delay line digital test output 10100 = DATX8 4 delay line digital test output 10101 = DATX8 5 delay line digital test output 10110 = DATX8 6 delay line digital test output 10111 = DATX8 7 delay line digital test output 11000 = DATX8 8 delay line digital test output 11001 = AC delay line digital test output 11010 – 11111 = Reserved + */ +#define DDRPHY_PGCR0_DTOSEL_MASK (0x7C000UL) +#define DDRPHY_PGCR0_DTOSEL_SHIFT (14U) +#define DDRPHY_PGCR0_DTOSEL_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_DTOSEL_SHIFT) & DDRPHY_PGCR0_DTOSEL_MASK) +#define DDRPHY_PGCR0_DTOSEL_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_DTOSEL_MASK) >> DDRPHY_PGCR0_DTOSEL_SHIFT) + +/* + * OSCWDL (R/W) + * + * Oscillator Mode Write-Leveling Delay Line Select: Selects which of the two write leveling LCDLs is active. The delay select value of the inactive LCDL is set to zero while the delay select value of the active LCDL can be varied by the input write leveling delay select pin. Valid values are: + * 00 = No WL LCDL is active 01 = DDR WL LCDL is active 10 = SDR WL LCDL is active 11 = Both LCDLs are active + */ +#define DDRPHY_PGCR0_OSCWDL_MASK (0x3000U) +#define DDRPHY_PGCR0_OSCWDL_SHIFT (12U) +#define DDRPHY_PGCR0_OSCWDL_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_OSCWDL_SHIFT) & DDRPHY_PGCR0_OSCWDL_MASK) +#define DDRPHY_PGCR0_OSCWDL_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_OSCWDL_MASK) >> DDRPHY_PGCR0_OSCWDL_SHIFT) + +/* + * OSCDIV (R/W) + * + * Oscillator Mode Division: Specifies the factor by which the delay line oscillator mode output is divided down before it is output on the delay line digital test output pin dl_dto. Valid values are: + * 000 = Divide by 1 + * 001 = Divide by 256 + * 010 = Divide by 512 + * 011 = Divide by 1024 + * 100 = Divide by 2048 + * 101 = Divide by 4096 + * 110 = Divide by 8192 + * 111 = Divide by 65536 + */ +#define DDRPHY_PGCR0_OSCDIV_MASK (0xE00U) +#define DDRPHY_PGCR0_OSCDIV_SHIFT (9U) +#define DDRPHY_PGCR0_OSCDIV_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_OSCDIV_SHIFT) & DDRPHY_PGCR0_OSCDIV_MASK) +#define DDRPHY_PGCR0_OSCDIV_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_OSCDIV_MASK) >> DDRPHY_PGCR0_OSCDIV_SHIFT) + +/* + * OSCEN (R/W) + * + * Oscillator Enable: Enables, if set, the delay line oscillation. + */ +#define DDRPHY_PGCR0_OSCEN_MASK (0x100U) +#define DDRPHY_PGCR0_OSCEN_SHIFT (8U) +#define DDRPHY_PGCR0_OSCEN_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_OSCEN_SHIFT) & DDRPHY_PGCR0_OSCEN_MASK) +#define DDRPHY_PGCR0_OSCEN_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_OSCEN_MASK) >> DDRPHY_PGCR0_OSCEN_SHIFT) + +/* + * DLTST (R/W) + * + * Delay Line Test Start: A write of '1' to this bit will trigger delay line oscillator mode period measurement. This bit is not self clearing and needs to be reset to '0' before the measurement can be re-triggered. + */ +#define DDRPHY_PGCR0_DLTST_MASK (0x80U) +#define DDRPHY_PGCR0_DLTST_SHIFT (7U) +#define DDRPHY_PGCR0_DLTST_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_DLTST_SHIFT) & DDRPHY_PGCR0_DLTST_MASK) +#define DDRPHY_PGCR0_DLTST_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_DLTST_MASK) >> DDRPHY_PGCR0_DLTST_SHIFT) + +/* + * DLTMODE (R/W) + * + * Delay Line Test Mode: Selects, if set, the delay line oscillator test mode. Setting this bit also clears all delay line register values. For DL oscillator testing, first set this bit, then apply desired non-zero LCDL and BDL register programmings. + */ +#define DDRPHY_PGCR0_DLTMODE_MASK (0x40U) +#define DDRPHY_PGCR0_DLTMODE_SHIFT (6U) +#define DDRPHY_PGCR0_DLTMODE_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_DLTMODE_SHIFT) & DDRPHY_PGCR0_DLTMODE_MASK) +#define DDRPHY_PGCR0_DLTMODE_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_DLTMODE_MASK) >> DDRPHY_PGCR0_DLTMODE_SHIFT) + +/* + * RDBVT (R/W) + * + * Read Data BDL VT Compensation: Enables, if set, the VT drift compensation of the read data bit delay lines. + */ +#define DDRPHY_PGCR0_RDBVT_MASK (0x20U) +#define DDRPHY_PGCR0_RDBVT_SHIFT (5U) +#define DDRPHY_PGCR0_RDBVT_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_RDBVT_SHIFT) & DDRPHY_PGCR0_RDBVT_MASK) +#define DDRPHY_PGCR0_RDBVT_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_RDBVT_MASK) >> DDRPHY_PGCR0_RDBVT_SHIFT) + +/* + * WDBVT (R/W) + * + * Write Data BDL VT Compensation: Enables, if set, the VT drift compensation of the write data bit delay lines. + */ +#define DDRPHY_PGCR0_WDBVT_MASK (0x10U) +#define DDRPHY_PGCR0_WDBVT_SHIFT (4U) +#define DDRPHY_PGCR0_WDBVT_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_WDBVT_SHIFT) & DDRPHY_PGCR0_WDBVT_MASK) +#define DDRPHY_PGCR0_WDBVT_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_WDBVT_MASK) >> DDRPHY_PGCR0_WDBVT_SHIFT) + +/* + * RGLVT (R/W) + * + * Read DQS Gating LCDL Delay VT Compensation: Enables, if set, the VT drift compensation of the read DQS gating LCDL. + */ +#define DDRPHY_PGCR0_RGLVT_MASK (0x8U) +#define DDRPHY_PGCR0_RGLVT_SHIFT (3U) +#define DDRPHY_PGCR0_RGLVT_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_RGLVT_SHIFT) & DDRPHY_PGCR0_RGLVT_MASK) +#define DDRPHY_PGCR0_RGLVT_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_RGLVT_MASK) >> DDRPHY_PGCR0_RGLVT_SHIFT) + +/* + * RDLVT (R/W) + * + * Read DQS LCDL Delay VT Compensation: Enables, if set, the VT drift compensation of the read DQS LCDL. + */ +#define DDRPHY_PGCR0_RDLVT_MASK (0x4U) +#define DDRPHY_PGCR0_RDLVT_SHIFT (2U) +#define DDRPHY_PGCR0_RDLVT_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_RDLVT_SHIFT) & DDRPHY_PGCR0_RDLVT_MASK) +#define DDRPHY_PGCR0_RDLVT_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_RDLVT_MASK) >> DDRPHY_PGCR0_RDLVT_SHIFT) + +/* + * WDLVT (R/W) + * + * Write DQ LCDL Delay VT Compensation: Enables, if set, the VT drift compensation of the write DQ LCDL. + */ +#define DDRPHY_PGCR0_WDLVT_MASK (0x2U) +#define DDRPHY_PGCR0_WDLVT_SHIFT (1U) +#define DDRPHY_PGCR0_WDLVT_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_WDLVT_SHIFT) & DDRPHY_PGCR0_WDLVT_MASK) +#define DDRPHY_PGCR0_WDLVT_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_WDLVT_MASK) >> DDRPHY_PGCR0_WDLVT_SHIFT) + +/* + * WLLVT (R/W) + * + * Write Leveling LCDL Delay VT Compensation: Enables, if set, the VT drift compensation of the write leveling LCDL. + */ +#define DDRPHY_PGCR0_WLLVT_MASK (0x1U) +#define DDRPHY_PGCR0_WLLVT_SHIFT (0U) +#define DDRPHY_PGCR0_WLLVT_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_WLLVT_SHIFT) & DDRPHY_PGCR0_WLLVT_MASK) +#define DDRPHY_PGCR0_WLLVT_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_WLLVT_MASK) >> DDRPHY_PGCR0_WLLVT_SHIFT) + +/* Bitfield definition for register: PGCR1 */ +/* + * LBMODE (R/W) + * + * Loopback Mode: Indicates, if set, that the PHY/PUB is in loopback mode. + */ +#define DDRPHY_PGCR1_LBMODE_MASK (0x80000000UL) +#define DDRPHY_PGCR1_LBMODE_SHIFT (31U) +#define DDRPHY_PGCR1_LBMODE_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_LBMODE_SHIFT) & DDRPHY_PGCR1_LBMODE_MASK) +#define DDRPHY_PGCR1_LBMODE_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_LBMODE_MASK) >> DDRPHY_PGCR1_LBMODE_SHIFT) + +/* + * LBGDQS (R/W) + * + * Loopback DQS Gating: Selects the DQS gating mode that should be used when the PHY is in loopback mode, including BIST loopback mode. Valid values are: + * 00 = DQS gate is always on + * 01 = DQS gate training will be triggered on the PUB 10 = DQS gate is set manually using software + * 11 = Reserved + */ +#define DDRPHY_PGCR1_LBGDQS_MASK (0x60000000UL) +#define DDRPHY_PGCR1_LBGDQS_SHIFT (29U) +#define DDRPHY_PGCR1_LBGDQS_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_LBGDQS_SHIFT) & DDRPHY_PGCR1_LBGDQS_MASK) +#define DDRPHY_PGCR1_LBGDQS_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_LBGDQS_MASK) >> DDRPHY_PGCR1_LBGDQS_SHIFT) + +/* + * LBDQSS (R/W) + * + * Loopback DQS Shift: Selects how the read DQS is shifted during loopback to ensure that the read DQS is centered into the read data eye. Valid values are: + * 1b0 = PUB sets the read DQS LCDL to 0 (internally). DQS is already shifted 90 degrees by write path + * 1b1 = The read DQS shift is set manually through software + */ +#define DDRPHY_PGCR1_LBDQSS_MASK (0x10000000UL) +#define DDRPHY_PGCR1_LBDQSS_SHIFT (28U) +#define DDRPHY_PGCR1_LBDQSS_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_LBDQSS_SHIFT) & DDRPHY_PGCR1_LBDQSS_MASK) +#define DDRPHY_PGCR1_LBDQSS_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_LBDQSS_MASK) >> DDRPHY_PGCR1_LBDQSS_SHIFT) + +/* + * IOLB (R/W) + * + * I/O Loop-Back Select: Selects where inside the I/O the loop-back of signals happens. Valid values are: + * 0 = Loopback is after output buffer; output enable must be asserted 1 = Loopback is before output buffer; output enable is don’t care + */ +#define DDRPHY_PGCR1_IOLB_MASK (0x8000000UL) +#define DDRPHY_PGCR1_IOLB_SHIFT (27U) +#define DDRPHY_PGCR1_IOLB_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_IOLB_SHIFT) & DDRPHY_PGCR1_IOLB_MASK) +#define DDRPHY_PGCR1_IOLB_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_IOLB_MASK) >> DDRPHY_PGCR1_IOLB_SHIFT) + +/* + * INHVT (R/W) + * + * VT Calculation Inhibit: Inhibits calculation of the next VT compensated delay line values. A value of 1 will inhibit the VT calculation. This bit should be set to 1 during writes to the delay line registers. + */ +#define DDRPHY_PGCR1_INHVT_MASK (0x4000000UL) +#define DDRPHY_PGCR1_INHVT_SHIFT (26U) +#define DDRPHY_PGCR1_INHVT_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_INHVT_SHIFT) & DDRPHY_PGCR1_INHVT_MASK) +#define DDRPHY_PGCR1_INHVT_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_INHVT_MASK) >> DDRPHY_PGCR1_INHVT_SHIFT) + +/* + * DXHRST (R/W) + * + * DX PHY High-Speed Reset: a Write of '0' to this bit resets the DX macro without resetting the PUB RTL logic. This bit is not self-clearing and a '1' must be written to de-assert the reset. + */ +#define DDRPHY_PGCR1_DXHRST_MASK (0x2000000UL) +#define DDRPHY_PGCR1_DXHRST_SHIFT (25U) +#define DDRPHY_PGCR1_DXHRST_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_DXHRST_SHIFT) & DDRPHY_PGCR1_DXHRST_MASK) +#define DDRPHY_PGCR1_DXHRST_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_DXHRST_MASK) >> DDRPHY_PGCR1_DXHRST_SHIFT) + +/* + * ZCKSEL (R/W) + * + * Impedance Clock Divider Select: Selects the divide ratio for the clock used by the impedance control logic relative to the clock used by the memory controller and SDRAM. + * Valid values are: + * 00 = Divide by 2 + * 01 = Divide by 8 + * 10 = Divide by 32 + * 11 = Divide by 64 + * For more information, refer to “Impedance Calibration” on page 174. + */ +#define DDRPHY_PGCR1_ZCKSEL_MASK (0x1800000UL) +#define DDRPHY_PGCR1_ZCKSEL_SHIFT (23U) +#define DDRPHY_PGCR1_ZCKSEL_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_ZCKSEL_SHIFT) & DDRPHY_PGCR1_ZCKSEL_MASK) +#define DDRPHY_PGCR1_ZCKSEL_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_ZCKSEL_MASK) >> DDRPHY_PGCR1_ZCKSEL_SHIFT) + +/* + * DLDLMT (R/W) + * + * Delay Line VT Drift Limit: Specifies the minimum change in the delay line VT drift in one direction which should result in the assertion of the delay line VT drift status signal (vt_drift). The limit is specified in terms of delay select values. A value of 0 disables the assertion of delay line VT drift status signal. + */ +#define DDRPHY_PGCR1_DLDLMT_MASK (0x7F8000UL) +#define DDRPHY_PGCR1_DLDLMT_SHIFT (15U) +#define DDRPHY_PGCR1_DLDLMT_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_DLDLMT_SHIFT) & DDRPHY_PGCR1_DLDLMT_MASK) +#define DDRPHY_PGCR1_DLDLMT_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_DLDLMT_MASK) >> DDRPHY_PGCR1_DLDLMT_SHIFT) + +/* + * FDEPTH (R/W) + * + * Filter Depth: Specifies the number of measurements over which all AC and DATX8 initial period measurements, that happen after reset or when calibration is manually triggered, are averaged. Valid values are: + * 00 = 2 + * 01 = 4 + * 10 = 8 + * 11 = 16 + */ +#define DDRPHY_PGCR1_FDEPTH_MASK (0x6000U) +#define DDRPHY_PGCR1_FDEPTH_SHIFT (13U) +#define DDRPHY_PGCR1_FDEPTH_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_FDEPTH_SHIFT) & DDRPHY_PGCR1_FDEPTH_MASK) +#define DDRPHY_PGCR1_FDEPTH_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_FDEPTH_MASK) >> DDRPHY_PGCR1_FDEPTH_SHIFT) + +/* + * LPFDEPTH (R/W) + * + * Low-Pass Filter Depth: Specifies the number of measurements over which MDL period measurements are filtered. This determines the time constant of the low pass filter. Valid values are: + * 00 = 2 + * 01 = 4 + * 10 = 8 + * 11 = 16 + */ +#define DDRPHY_PGCR1_LPFDEPTH_MASK (0x1800U) +#define DDRPHY_PGCR1_LPFDEPTH_SHIFT (11U) +#define DDRPHY_PGCR1_LPFDEPTH_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_LPFDEPTH_SHIFT) & DDRPHY_PGCR1_LPFDEPTH_MASK) +#define DDRPHY_PGCR1_LPFDEPTH_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_LPFDEPTH_MASK) >> DDRPHY_PGCR1_LPFDEPTH_SHIFT) + +/* + * LPFEN (R/W) + * + * Low-Pass Filter Enable: Enables, if set, the low pass filtering of MDL period measurements. + */ +#define DDRPHY_PGCR1_LPFEN_MASK (0x400U) +#define DDRPHY_PGCR1_LPFEN_SHIFT (10U) +#define DDRPHY_PGCR1_LPFEN_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_LPFEN_SHIFT) & DDRPHY_PGCR1_LPFEN_MASK) +#define DDRPHY_PGCR1_LPFEN_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_LPFEN_MASK) >> DDRPHY_PGCR1_LPFEN_SHIFT) + +/* + * MDLEN (R/W) + * + * Master Delay Line Enable: Enables, if set, the AC master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or on when calibration is manually triggered. These additional measurements are accumulated and filtered as long as this bit remains high. + */ +#define DDRPHY_PGCR1_MDLEN_MASK (0x200U) +#define DDRPHY_PGCR1_MDLEN_SHIFT (9U) +#define DDRPHY_PGCR1_MDLEN_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_MDLEN_SHIFT) & DDRPHY_PGCR1_MDLEN_MASK) +#define DDRPHY_PGCR1_MDLEN_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_MDLEN_MASK) >> DDRPHY_PGCR1_MDLEN_SHIFT) + +/* + * IODDRM (R/W) + * + * I/O DDR Mode (D3F I/O Only): Selects the DDR mode for the I/Os. These bits connect to bits [2:1] of the IOM pin of the SSTL I/O. For more information, refer to the SSTL I/O chapter in the DWC DDR PHY Databook. + */ +#define DDRPHY_PGCR1_IODDRM_MASK (0x180U) +#define DDRPHY_PGCR1_IODDRM_SHIFT (7U) +#define DDRPHY_PGCR1_IODDRM_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_IODDRM_SHIFT) & DDRPHY_PGCR1_IODDRM_MASK) +#define DDRPHY_PGCR1_IODDRM_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_IODDRM_MASK) >> DDRPHY_PGCR1_IODDRM_SHIFT) + +/* + * WLSELT (R/W) + * + * Write Leveling Select Type: Selects the encoding type for the write leveling select signal depending on the desired setup/hold margins for the internal pipelines. Refer to the DDR PHY Databook for details of how the select type is used. Valid values are: + * 0 = Type 1: Setup margin of 90 degrees and hold margin of 90 degrees 1 = Type 2: Setup margin of 135 degrees and hold margin of 45 degrees + */ +#define DDRPHY_PGCR1_WLSELT_MASK (0x40U) +#define DDRPHY_PGCR1_WLSELT_SHIFT (6U) +#define DDRPHY_PGCR1_WLSELT_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_WLSELT_SHIFT) & DDRPHY_PGCR1_WLSELT_MASK) +#define DDRPHY_PGCR1_WLSELT_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_WLSELT_MASK) >> DDRPHY_PGCR1_WLSELT_SHIFT) + +/* + * ACHRST (R/W) + * + * AC PHY High-Speed Reset: a Write of '0' to this bit resets the AC macro without resetting the PUB RTL logic. This bit is not self-clearing and a '1' must be written to de-assert the reset. + */ +#define DDRPHY_PGCR1_ACHRST_MASK (0x20U) +#define DDRPHY_PGCR1_ACHRST_SHIFT (5U) +#define DDRPHY_PGCR1_ACHRST_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_ACHRST_SHIFT) & DDRPHY_PGCR1_ACHRST_MASK) +#define DDRPHY_PGCR1_ACHRST_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_ACHRST_MASK) >> DDRPHY_PGCR1_ACHRST_SHIFT) + +/* + * WSLOPT (R/W) + * + * Write System Latency Optimization: controls the insertion of a pipeline stage on the AC signals from the DFI interface to the PHY to cater for a negative write system latency (WSL) value (only -1 possible). + * 0x0 = A pipeline stage is inserted only if WL2 training results in a WSL of -1 for any rank + * 0x1 = Inserts a pipeline stage + */ +#define DDRPHY_PGCR1_WSLOPT_MASK (0x10U) +#define DDRPHY_PGCR1_WSLOPT_SHIFT (4U) +#define DDRPHY_PGCR1_WSLOPT_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_WSLOPT_SHIFT) & DDRPHY_PGCR1_WSLOPT_MASK) +#define DDRPHY_PGCR1_WSLOPT_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_WSLOPT_MASK) >> DDRPHY_PGCR1_WSLOPT_SHIFT) + +/* + * WLSTEP (R/W) + * + * Write Leveling Step: Specifies the number of delay step-size increments during each step of write leveling. Valid values are: + * 0 = computed to be 1/2 of the associated lane's DXnGSR0.WLPRD value 1 = 1 step size + */ +#define DDRPHY_PGCR1_WLSTEP_MASK (0x4U) +#define DDRPHY_PGCR1_WLSTEP_SHIFT (2U) +#define DDRPHY_PGCR1_WLSTEP_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_WLSTEP_SHIFT) & DDRPHY_PGCR1_WLSTEP_MASK) +#define DDRPHY_PGCR1_WLSTEP_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_WLSTEP_MASK) >> DDRPHY_PGCR1_WLSTEP_SHIFT) + +/* + * WLMODE (R/W) + * + * Write Leveling (Software) Mode: Indicates, if set, that the PUB is in software write leveling mode in which software executes single steps of DQS pulsing by writing '1' to PIR.WL. The write leveling DQ status from the DRAM is captured in DXnGSR0.WLDQ. + */ +#define DDRPHY_PGCR1_WLMODE_MASK (0x2U) +#define DDRPHY_PGCR1_WLMODE_SHIFT (1U) +#define DDRPHY_PGCR1_WLMODE_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_WLMODE_SHIFT) & DDRPHY_PGCR1_WLMODE_MASK) +#define DDRPHY_PGCR1_WLMODE_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_WLMODE_MASK) >> DDRPHY_PGCR1_WLMODE_SHIFT) + +/* + * PDDISDX (R/W) + * + * Power Down Disabled Byte: Indicates, if set, that the PLL and I/Os of a disabled byte should be powered down. + */ +#define DDRPHY_PGCR1_PDDISDX_MASK (0x1U) +#define DDRPHY_PGCR1_PDDISDX_SHIFT (0U) +#define DDRPHY_PGCR1_PDDISDX_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_PDDISDX_SHIFT) & DDRPHY_PGCR1_PDDISDX_MASK) +#define DDRPHY_PGCR1_PDDISDX_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_PDDISDX_MASK) >> DDRPHY_PGCR1_PDDISDX_SHIFT) + +/* Bitfield definition for register: PGSR0 */ +/* + * APLOCK (R) + * + * AC PLL Lock: Indicates, if set, that AC PLL has locked. This is a direct status of the AC PLL lock pin. + */ +#define DDRPHY_PGSR0_APLOCK_MASK (0x80000000UL) +#define DDRPHY_PGSR0_APLOCK_SHIFT (31U) +#define DDRPHY_PGSR0_APLOCK_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_APLOCK_MASK) >> DDRPHY_PGSR0_APLOCK_SHIFT) + +/* + * PLDONE_CHN (R) + * + * PLL Lock Done per Channel: Indicates PLL locking has completed for each underlying channel. Bit 28 represents channel 0 while bit 29 represents channel 1. + */ +#define DDRPHY_PGSR0_PLDONE_CHN_MASK (0x30000000UL) +#define DDRPHY_PGSR0_PLDONE_CHN_SHIFT (28U) +#define DDRPHY_PGSR0_PLDONE_CHN_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_PLDONE_CHN_MASK) >> DDRPHY_PGSR0_PLDONE_CHN_SHIFT) + +/* + * WEERR (R) + * + * Write Eye Training Error: Indicates, if set, that there is an error in write eye training. + */ +#define DDRPHY_PGSR0_WEERR_MASK (0x8000000UL) +#define DDRPHY_PGSR0_WEERR_SHIFT (27U) +#define DDRPHY_PGSR0_WEERR_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_WEERR_MASK) >> DDRPHY_PGSR0_WEERR_SHIFT) + +/* + * REERR (R) + * + * Read Data Eye Training Error: Indicates, if set, that there is an error in read eye training. + */ +#define DDRPHY_PGSR0_REERR_MASK (0x4000000UL) +#define DDRPHY_PGSR0_REERR_SHIFT (26U) +#define DDRPHY_PGSR0_REERR_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_REERR_MASK) >> DDRPHY_PGSR0_REERR_SHIFT) + +/* + * WDERR (R) + * + * Write Data Bit Deskew Error: Indicates, if set, that there is an error in write bit deskew. + */ +#define DDRPHY_PGSR0_WDERR_MASK (0x2000000UL) +#define DDRPHY_PGSR0_WDERR_SHIFT (25U) +#define DDRPHY_PGSR0_WDERR_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_WDERR_MASK) >> DDRPHY_PGSR0_WDERR_SHIFT) + +/* + * RDERR (R) + * + * Read Data Bit Deskew Error: Indicates, if set, that there is an error in read bit deskew. + */ +#define DDRPHY_PGSR0_RDERR_MASK (0x1000000UL) +#define DDRPHY_PGSR0_RDERR_SHIFT (24U) +#define DDRPHY_PGSR0_RDERR_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_RDERR_MASK) >> DDRPHY_PGSR0_RDERR_SHIFT) + +/* + * WLAERR (R) + * + * Write Data Leveling Adjustment Error: Indicates, if set, that there is an error in write leveling adjustment. + */ +#define DDRPHY_PGSR0_WLAERR_MASK (0x800000UL) +#define DDRPHY_PGSR0_WLAERR_SHIFT (23U) +#define DDRPHY_PGSR0_WLAERR_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_WLAERR_MASK) >> DDRPHY_PGSR0_WLAERR_SHIFT) + +/* + * QSGERR (R) + * + * Read DQS Gate Training Error: Indicates, if set, that there is an error in DQS gate training. + */ +#define DDRPHY_PGSR0_QSGERR_MASK (0x400000UL) +#define DDRPHY_PGSR0_QSGERR_SHIFT (22U) +#define DDRPHY_PGSR0_QSGERR_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_QSGERR_MASK) >> DDRPHY_PGSR0_QSGERR_SHIFT) + +/* + * WLERR (R) + * + * Write Leveling Error: Indicates, if set, that there is an error in write leveling. + */ +#define DDRPHY_PGSR0_WLERR_MASK (0x200000UL) +#define DDRPHY_PGSR0_WLERR_SHIFT (21U) +#define DDRPHY_PGSR0_WLERR_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_WLERR_MASK) >> DDRPHY_PGSR0_WLERR_SHIFT) + +/* + * ZCERR (R) + * + * Impedance Calibration Error: Indicates, if set, that there is an error in impedance calibration. + */ +#define DDRPHY_PGSR0_ZCERR_MASK (0x100000UL) +#define DDRPHY_PGSR0_ZCERR_SHIFT (20U) +#define DDRPHY_PGSR0_ZCERR_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_ZCERR_MASK) >> DDRPHY_PGSR0_ZCERR_SHIFT) + +/* + * WEDONE (R) + * + * Write Data Eye Training Done: Indicates, if set, that write eye training has completed. + */ +#define DDRPHY_PGSR0_WEDONE_MASK (0x800U) +#define DDRPHY_PGSR0_WEDONE_SHIFT (11U) +#define DDRPHY_PGSR0_WEDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_WEDONE_MASK) >> DDRPHY_PGSR0_WEDONE_SHIFT) + +/* + * REDONE (R) + * + * Read Data Eye Training Done: Indicates, if set, that read eye training has completed. + */ +#define DDRPHY_PGSR0_REDONE_MASK (0x400U) +#define DDRPHY_PGSR0_REDONE_SHIFT (10U) +#define DDRPHY_PGSR0_REDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_REDONE_MASK) >> DDRPHY_PGSR0_REDONE_SHIFT) + +/* + * WDDONE (R) + * + * Write Data Bit Deskew Done: Indicates, if set, that write bit deskew has completed. + */ +#define DDRPHY_PGSR0_WDDONE_MASK (0x200U) +#define DDRPHY_PGSR0_WDDONE_SHIFT (9U) +#define DDRPHY_PGSR0_WDDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_WDDONE_MASK) >> DDRPHY_PGSR0_WDDONE_SHIFT) + +/* + * RDDONE (R) + * + * Read Data Bit Deskew Done: Indicates, if set, that read bit deskew has completed. + */ +#define DDRPHY_PGSR0_RDDONE_MASK (0x100U) +#define DDRPHY_PGSR0_RDDONE_SHIFT (8U) +#define DDRPHY_PGSR0_RDDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_RDDONE_MASK) >> DDRPHY_PGSR0_RDDONE_SHIFT) + +/* + * WLADONE (R) + * + * Write Leveling Adjustment Done: Indicates, if set, that write leveling adjustment has completed. + */ +#define DDRPHY_PGSR0_WLADONE_MASK (0x80U) +#define DDRPHY_PGSR0_WLADONE_SHIFT (7U) +#define DDRPHY_PGSR0_WLADONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_WLADONE_MASK) >> DDRPHY_PGSR0_WLADONE_SHIFT) + +/* + * QSGDONE (R) + * + * Read DQS Gate Training Done: Indicates, if set, that DQS gate training has completed. + */ +#define DDRPHY_PGSR0_QSGDONE_MASK (0x40U) +#define DDRPHY_PGSR0_QSGDONE_SHIFT (6U) +#define DDRPHY_PGSR0_QSGDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_QSGDONE_MASK) >> DDRPHY_PGSR0_QSGDONE_SHIFT) + +/* + * WLDONE (R) + * + * Write Leveling Done: Indicates, if set, that write leveling has completed. + */ +#define DDRPHY_PGSR0_WLDONE_MASK (0x20U) +#define DDRPHY_PGSR0_WLDONE_SHIFT (5U) +#define DDRPHY_PGSR0_WLDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_WLDONE_MASK) >> DDRPHY_PGSR0_WLDONE_SHIFT) + +/* + * DIDONE (R) + * + * DRAM Initialization Done: Indicates, if set, that DRAM initialization has completed. + */ +#define DDRPHY_PGSR0_DIDONE_MASK (0x10U) +#define DDRPHY_PGSR0_DIDONE_SHIFT (4U) +#define DDRPHY_PGSR0_DIDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_DIDONE_MASK) >> DDRPHY_PGSR0_DIDONE_SHIFT) + +/* + * ZCDONE (R) + * + * Impedance Calibration Done: Indicates, if set, that impedance calibration has completed. + */ +#define DDRPHY_PGSR0_ZCDONE_MASK (0x8U) +#define DDRPHY_PGSR0_ZCDONE_SHIFT (3U) +#define DDRPHY_PGSR0_ZCDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_ZCDONE_MASK) >> DDRPHY_PGSR0_ZCDONE_SHIFT) + +/* + * DCDONE (R) + * + * Digital Delay Line (DDL) Calibration Done: Indicates, if set, that DDL calibration has completed. + */ +#define DDRPHY_PGSR0_DCDONE_MASK (0x4U) +#define DDRPHY_PGSR0_DCDONE_SHIFT (2U) +#define DDRPHY_PGSR0_DCDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_DCDONE_MASK) >> DDRPHY_PGSR0_DCDONE_SHIFT) + +/* + * PLDONE (R) + * + * PLL Lock Done: Indicates, if set, that PLL locking has completed. + */ +#define DDRPHY_PGSR0_PLDONE_MASK (0x2U) +#define DDRPHY_PGSR0_PLDONE_SHIFT (1U) +#define DDRPHY_PGSR0_PLDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_PLDONE_MASK) >> DDRPHY_PGSR0_PLDONE_SHIFT) + +/* + * IDONE (R) + * + * Initialization Done: Indicates, if set, that the DDR system initialization has completed. This bit is set after all the selected initialization routines in PIR register have completed. + */ +#define DDRPHY_PGSR0_IDONE_MASK (0x1U) +#define DDRPHY_PGSR0_IDONE_SHIFT (0U) +#define DDRPHY_PGSR0_IDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_IDONE_MASK) >> DDRPHY_PGSR0_IDONE_SHIFT) + +/* Bitfield definition for register: PGSR1 */ +/* + * PARERR (R) + * + * RDIMM Parity Error: Indicates, if set, that there was a parity error (i.e. err_out_n was sampled low) during one of the transactions to the RDIMM buffer chip. This bit remains asserted until cleared by the PIR.CLRSR. + */ +#define DDRPHY_PGSR1_PARERR_MASK (0x80000000UL) +#define DDRPHY_PGSR1_PARERR_SHIFT (31U) +#define DDRPHY_PGSR1_PARERR_GET(x) (((uint32_t)(x) & DDRPHY_PGSR1_PARERR_MASK) >> DDRPHY_PGSR1_PARERR_SHIFT) + +/* + * VTSTOP (R) + * + * VT Stop: Indicates, if set, that the VT calculation logic has stopped computing the next values for the VT compensated delay line values. After assertion of the PGCR.INHVT, the VTSTOP bit should be read to ensure all VT compensation logic has stopped computations before writing to the delay line registers. + */ +#define DDRPHY_PGSR1_VTSTOP_MASK (0x40000000UL) +#define DDRPHY_PGSR1_VTSTOP_SHIFT (30U) +#define DDRPHY_PGSR1_VTSTOP_GET(x) (((uint32_t)(x) & DDRPHY_PGSR1_VTSTOP_MASK) >> DDRPHY_PGSR1_VTSTOP_SHIFT) + +/* + * DLTCODE (R) + * + * Delay Line Test Code: Returns the code measured by the PHY control block that corresponds to the period of the AC delay line digital test output. + */ +#define DDRPHY_PGSR1_DLTCODE_MASK (0x1FFFFFEUL) +#define DDRPHY_PGSR1_DLTCODE_SHIFT (1U) +#define DDRPHY_PGSR1_DLTCODE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR1_DLTCODE_MASK) >> DDRPHY_PGSR1_DLTCODE_SHIFT) + +/* + * DLTDONE (R) + * + * Delay Line Test Done: Indicates, if set, that the PHY control block has finished doing period measurement of the AC delay line digital test output. + */ +#define DDRPHY_PGSR1_DLTDONE_MASK (0x1U) +#define DDRPHY_PGSR1_DLTDONE_SHIFT (0U) +#define DDRPHY_PGSR1_DLTDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR1_DLTDONE_MASK) >> DDRPHY_PGSR1_DLTDONE_SHIFT) + +/* Bitfield definition for register: PLLCR */ +/* + * BYP (R/W) + * + * PLL Bypass: Bypasses the PLL, if set, to 1. + */ +#define DDRPHY_PLLCR_BYP_MASK (0x80000000UL) +#define DDRPHY_PLLCR_BYP_SHIFT (31U) +#define DDRPHY_PLLCR_BYP_SET(x) (((uint32_t)(x) << DDRPHY_PLLCR_BYP_SHIFT) & DDRPHY_PLLCR_BYP_MASK) +#define DDRPHY_PLLCR_BYP_GET(x) (((uint32_t)(x) & DDRPHY_PLLCR_BYP_MASK) >> DDRPHY_PLLCR_BYP_SHIFT) + +/* + * PLLRST (R/W) + * + * PLL Rest: Resets the PLLs by driving the PLL reset pin. This bit is not self-clearing and a ‘0’ must be written to de-assert the reset. + */ +#define DDRPHY_PLLCR_PLLRST_MASK (0x40000000UL) +#define DDRPHY_PLLCR_PLLRST_SHIFT (30U) +#define DDRPHY_PLLCR_PLLRST_SET(x) (((uint32_t)(x) << DDRPHY_PLLCR_PLLRST_SHIFT) & DDRPHY_PLLCR_PLLRST_MASK) +#define DDRPHY_PLLCR_PLLRST_GET(x) (((uint32_t)(x) & DDRPHY_PLLCR_PLLRST_MASK) >> DDRPHY_PLLCR_PLLRST_SHIFT) + +/* + * PLLPD (R/W) + * + * PLL Power Down: Puts the PLLs in power down mode by driving the PLL power down pin. This bit is not self-clearing and a ‘0’ must be written to de-assert the power-down. + */ +#define DDRPHY_PLLCR_PLLPD_MASK (0x20000000UL) +#define DDRPHY_PLLCR_PLLPD_SHIFT (29U) +#define DDRPHY_PLLCR_PLLPD_SET(x) (((uint32_t)(x) << DDRPHY_PLLCR_PLLPD_SHIFT) & DDRPHY_PLLCR_PLLPD_MASK) +#define DDRPHY_PLLCR_PLLPD_GET(x) (((uint32_t)(x) & DDRPHY_PLLCR_PLLPD_MASK) >> DDRPHY_PLLCR_PLLPD_SHIFT) + +/* + * FRQSEL (R/W) + * + * PLL Frequency Select: Selects the operating range of the PLL. Valid values for PHYs that go up to 2133 Mbps are: + * 00 = PLL reference clock (ctl_clk/REF_CLK) ranges from 335MHz to 533MHz 01 = PLL reference clock (ctl_clk/REF_CLK) ranges from 225MHz to 385MHz 10 = Reserved + * 11 = PLL reference clock (ctl_clk/REF_CLK) ranges from 166MHz to 275MHz + * Valid values for PHYs that don’t go up to 2133 Mbps are: + * 00 = PLL reference clock (ctl_clk/REF_CLK) ranges from 250MHz to 400MHz 01 = PLL reference clock (ctl_clk/REF_CLK) ranges from 166MHz to 300MHz 10 = Reserved + * 11 = Reserved + */ +#define DDRPHY_PLLCR_FRQSEL_MASK (0xC0000UL) +#define DDRPHY_PLLCR_FRQSEL_SHIFT (18U) +#define DDRPHY_PLLCR_FRQSEL_SET(x) (((uint32_t)(x) << DDRPHY_PLLCR_FRQSEL_SHIFT) & DDRPHY_PLLCR_FRQSEL_MASK) +#define DDRPHY_PLLCR_FRQSEL_GET(x) (((uint32_t)(x) & DDRPHY_PLLCR_FRQSEL_MASK) >> DDRPHY_PLLCR_FRQSEL_SHIFT) + +/* + * QPMODE (R/W) + * + * PLL Quadrature Phase Mode: Enables, if set, the quadrature phase clock outputs. This mode is not used in this version of the PHY. + */ +#define DDRPHY_PLLCR_QPMODE_MASK (0x20000UL) +#define DDRPHY_PLLCR_QPMODE_SHIFT (17U) +#define DDRPHY_PLLCR_QPMODE_SET(x) (((uint32_t)(x) << DDRPHY_PLLCR_QPMODE_SHIFT) & DDRPHY_PLLCR_QPMODE_MASK) +#define DDRPHY_PLLCR_QPMODE_GET(x) (((uint32_t)(x) & DDRPHY_PLLCR_QPMODE_MASK) >> DDRPHY_PLLCR_QPMODE_SHIFT) + +/* + * CPPC (R/W) + * + * Charge Pump Proportional Current Control + */ +#define DDRPHY_PLLCR_CPPC_MASK (0x1E000UL) +#define DDRPHY_PLLCR_CPPC_SHIFT (13U) +#define DDRPHY_PLLCR_CPPC_SET(x) (((uint32_t)(x) << DDRPHY_PLLCR_CPPC_SHIFT) & DDRPHY_PLLCR_CPPC_MASK) +#define DDRPHY_PLLCR_CPPC_GET(x) (((uint32_t)(x) & DDRPHY_PLLCR_CPPC_MASK) >> DDRPHY_PLLCR_CPPC_SHIFT) + +/* + * CPIC (R/W) + * + * Charge Pump Integrating Current Control + */ +#define DDRPHY_PLLCR_CPIC_MASK (0x1800U) +#define DDRPHY_PLLCR_CPIC_SHIFT (11U) +#define DDRPHY_PLLCR_CPIC_SET(x) (((uint32_t)(x) << DDRPHY_PLLCR_CPIC_SHIFT) & DDRPHY_PLLCR_CPIC_MASK) +#define DDRPHY_PLLCR_CPIC_GET(x) (((uint32_t)(x) & DDRPHY_PLLCR_CPIC_MASK) >> DDRPHY_PLLCR_CPIC_SHIFT) + +/* + * GSHIFT (R/W) + * + * Gear Shift: Enables, if set, rapid locking mode. + */ +#define DDRPHY_PLLCR_GSHIFT_MASK (0x400U) +#define DDRPHY_PLLCR_GSHIFT_SHIFT (10U) +#define DDRPHY_PLLCR_GSHIFT_SET(x) (((uint32_t)(x) << DDRPHY_PLLCR_GSHIFT_SHIFT) & DDRPHY_PLLCR_GSHIFT_MASK) +#define DDRPHY_PLLCR_GSHIFT_GET(x) (((uint32_t)(x) & DDRPHY_PLLCR_GSHIFT_MASK) >> DDRPHY_PLLCR_GSHIFT_SHIFT) + +/* + * ATOEN (R/W) + * + * Analog Test Enable (ATOEN): Selects the analog test signal that is driven on the analog test output pin. Otherwise the analog test output is tri-stated. This allows analog test output pins from multiple PLLs to be connected together. Valid values are: + * 0000 = All PLL analog test signals are tri-stated 0001 = AC PLL analog test signal is driven out + * 0010 = DATX8 0 PLL analog test signal is driven out 0011 = DATX8 1 PLL analog test signal is driven out 0100 = DATX8 2 PLL analog test signal is driven out 0101 = DATX8 3 PLL analog test signal is driven out 0110 = DATX8 4 PLL analog test signal is driven out 0111 = DATX8 5 PLL analog test signal is driven out 1000 = DATX8 6 PLL analog test signal is driven out 1001 = DATX8 7 PLL analog test signal is driven out 1010 = DATX8 8 PLL analog test signal is driven out 1011 – 1111 = Reserved + */ +#define DDRPHY_PLLCR_ATOEN_MASK (0x3C0U) +#define DDRPHY_PLLCR_ATOEN_SHIFT (6U) +#define DDRPHY_PLLCR_ATOEN_SET(x) (((uint32_t)(x) << DDRPHY_PLLCR_ATOEN_SHIFT) & DDRPHY_PLLCR_ATOEN_MASK) +#define DDRPHY_PLLCR_ATOEN_GET(x) (((uint32_t)(x) & DDRPHY_PLLCR_ATOEN_MASK) >> DDRPHY_PLLCR_ATOEN_SHIFT) + +/* + * ATC (R/W) + * + * Analog Test Control: Selects various PLL analog test signals to be brought out via PLL analog test output pin (pll_ato). Valid values are: + * 0000 = Reserved + * 0001 = vdd_ckin + * 0010 = vrfbf + * 0011 = vdd_cko + * 0100 = vp_cp + * 0101 = vpfil(vp) + * 0110 = Reserved + * 0111 = gd + * 1000 = vcntrl_atb + * 1001 = vref_atb + * 1010 = vpsf_atb + * 1011 – 1111 = Reserved + */ +#define DDRPHY_PLLCR_ATC_MASK (0x3CU) +#define DDRPHY_PLLCR_ATC_SHIFT (2U) +#define DDRPHY_PLLCR_ATC_SET(x) (((uint32_t)(x) << DDRPHY_PLLCR_ATC_SHIFT) & DDRPHY_PLLCR_ATC_MASK) +#define DDRPHY_PLLCR_ATC_GET(x) (((uint32_t)(x) & DDRPHY_PLLCR_ATC_MASK) >> DDRPHY_PLLCR_ATC_SHIFT) + +/* + * DTC (R/W) + * + * Digital Test Control: Selects various PLL digital test signals and other test mode signals to be brought out via bit [1] of the PLL digital test output (pll_dto[1]). Valid values are: + * 00 = ‘0’ (Test output is disabled) 01 = PLL x1 clock (X1) + * 10 = PLL reference (input) clock (REF_CLK) 11 = PLL feedback clock (FB_X1) + */ +#define DDRPHY_PLLCR_DTC_MASK (0x3U) +#define DDRPHY_PLLCR_DTC_SHIFT (0U) +#define DDRPHY_PLLCR_DTC_SET(x) (((uint32_t)(x) << DDRPHY_PLLCR_DTC_SHIFT) & DDRPHY_PLLCR_DTC_MASK) +#define DDRPHY_PLLCR_DTC_GET(x) (((uint32_t)(x) & DDRPHY_PLLCR_DTC_MASK) >> DDRPHY_PLLCR_DTC_SHIFT) + +/* Bitfield definition for register: PTR0 */ +/* + * TPLLPD (R/W) + * + * PLL Power-Down Time: Number of configuration or APB clock cycles that the PLL must remain in power-down mode, i.e. number of clock cycles from when PLL power-down pin is asserted to when PLL power-down pin is de-asserted. This must correspond to a value that is equal to or more than 1us. Default value corresponds to 1us. + */ +#define DDRPHY_PTR0_TPLLPD_MASK (0xFFE00000UL) +#define DDRPHY_PTR0_TPLLPD_SHIFT (21U) +#define DDRPHY_PTR0_TPLLPD_SET(x) (((uint32_t)(x) << DDRPHY_PTR0_TPLLPD_SHIFT) & DDRPHY_PTR0_TPLLPD_MASK) +#define DDRPHY_PTR0_TPLLPD_GET(x) (((uint32_t)(x) & DDRPHY_PTR0_TPLLPD_MASK) >> DDRPHY_PTR0_TPLLPD_SHIFT) + +/* + * TPLLGS (R/W) + * + * PLL Gear Shift Time: Number of configuration or APB clock cycles from when the PLL reset pin is de-asserted to when the PLL gear shift pin is de-asserted. This must correspond to a value that is equal to or more than 4us. Default value corresponds to 4us. + */ +#define DDRPHY_PTR0_TPLLGS_MASK (0x1FFFC0UL) +#define DDRPHY_PTR0_TPLLGS_SHIFT (6U) +#define DDRPHY_PTR0_TPLLGS_SET(x) (((uint32_t)(x) << DDRPHY_PTR0_TPLLGS_SHIFT) & DDRPHY_PTR0_TPLLGS_MASK) +#define DDRPHY_PTR0_TPLLGS_GET(x) (((uint32_t)(x) & DDRPHY_PTR0_TPLLGS_MASK) >> DDRPHY_PTR0_TPLLGS_SHIFT) + +/* + * TPHYRST (R/W) + * + * PHY Reset Time: Number of configuration or APB clock cycles that the PHY reset must remain asserted after PHY calibration is done before the reset to the PHY is de-asserted. This is used to extend the reset to the PHY so that the reset is asserted for some clock cycles after the clocks are stable. Valid values are from 1 to 63 (the value must be non-zero). + */ +#define DDRPHY_PTR0_TPHYRST_MASK (0x3FU) +#define DDRPHY_PTR0_TPHYRST_SHIFT (0U) +#define DDRPHY_PTR0_TPHYRST_SET(x) (((uint32_t)(x) << DDRPHY_PTR0_TPHYRST_SHIFT) & DDRPHY_PTR0_TPHYRST_MASK) +#define DDRPHY_PTR0_TPHYRST_GET(x) (((uint32_t)(x) & DDRPHY_PTR0_TPHYRST_MASK) >> DDRPHY_PTR0_TPHYRST_SHIFT) + +/* Bitfield definition for register: PTR1 */ +/* + * TPLLLOCK (R/W) + * + * PLL Lock Time: Number of configuration or APB clock cycles for the PLL to stabilize and lock, i.e. number of clock cycles from when the PLL reset pin is de-asserted to when the PLL has lock and is ready for use. This must correspond to a value that is equal to or more than 100us. Default value corresponds to 100us. + */ +#define DDRPHY_PTR1_TPLLLOCK_MASK (0xFFFF0000UL) +#define DDRPHY_PTR1_TPLLLOCK_SHIFT (16U) +#define DDRPHY_PTR1_TPLLLOCK_SET(x) (((uint32_t)(x) << DDRPHY_PTR1_TPLLLOCK_SHIFT) & DDRPHY_PTR1_TPLLLOCK_MASK) +#define DDRPHY_PTR1_TPLLLOCK_GET(x) (((uint32_t)(x) & DDRPHY_PTR1_TPLLLOCK_MASK) >> DDRPHY_PTR1_TPLLLOCK_SHIFT) + +/* + * TPLLRST (R/W) + * + * PLL Reset Time: Number of configuration or APB clock cycles that the PLL must remain in reset mode, i.e. number of clock cycles from when PLL power-down pin is de-asserted and PLL reset pin is asserted to when PLL reset pin is de-asserted. + * The setting must correspond to a value that is equal to, or greater than, 3us. + */ +#define DDRPHY_PTR1_TPLLRST_MASK (0x1FFFU) +#define DDRPHY_PTR1_TPLLRST_SHIFT (0U) +#define DDRPHY_PTR1_TPLLRST_SET(x) (((uint32_t)(x) << DDRPHY_PTR1_TPLLRST_SHIFT) & DDRPHY_PTR1_TPLLRST_MASK) +#define DDRPHY_PTR1_TPLLRST_GET(x) (((uint32_t)(x) & DDRPHY_PTR1_TPLLRST_MASK) >> DDRPHY_PTR1_TPLLRST_SHIFT) + +/* Bitfield definition for register: PTR2 */ +/* + * TWLDLYS (R/W) + * + * Write Leveling Delay Settling Time: Number of controller clock cycles from when a new value of the write leveling delay is applies to the LCDL to when to DQS high is driven high. This allows the delay to settle. + */ +#define DDRPHY_PTR2_TWLDLYS_MASK (0xF8000UL) +#define DDRPHY_PTR2_TWLDLYS_SHIFT (15U) +#define DDRPHY_PTR2_TWLDLYS_SET(x) (((uint32_t)(x) << DDRPHY_PTR2_TWLDLYS_SHIFT) & DDRPHY_PTR2_TWLDLYS_MASK) +#define DDRPHY_PTR2_TWLDLYS_GET(x) (((uint32_t)(x) & DDRPHY_PTR2_TWLDLYS_MASK) >> DDRPHY_PTR2_TWLDLYS_SHIFT) + +/* + * TCALH (R/W) + * + * Calibration Hold Time: Number of controller clock cycles from when the clock was disabled (cal_clk_en deasserted) to when calibration is enable (cal_en asserted). + */ +#define DDRPHY_PTR2_TCALH_MASK (0x7C00U) +#define DDRPHY_PTR2_TCALH_SHIFT (10U) +#define DDRPHY_PTR2_TCALH_SET(x) (((uint32_t)(x) << DDRPHY_PTR2_TCALH_SHIFT) & DDRPHY_PTR2_TCALH_MASK) +#define DDRPHY_PTR2_TCALH_GET(x) (((uint32_t)(x) & DDRPHY_PTR2_TCALH_MASK) >> DDRPHY_PTR2_TCALH_SHIFT) + +/* + * TCALS (R/W) + * + * Calibration Setup Time: Number of controller clock cycles from when calibration is enabled (cal_en asserted) to when the calibration clock is asserted again (cal_clk_en asserted). + */ +#define DDRPHY_PTR2_TCALS_MASK (0x3E0U) +#define DDRPHY_PTR2_TCALS_SHIFT (5U) +#define DDRPHY_PTR2_TCALS_SET(x) (((uint32_t)(x) << DDRPHY_PTR2_TCALS_SHIFT) & DDRPHY_PTR2_TCALS_MASK) +#define DDRPHY_PTR2_TCALS_GET(x) (((uint32_t)(x) & DDRPHY_PTR2_TCALS_MASK) >> DDRPHY_PTR2_TCALS_SHIFT) + +/* + * TCALON (R/W) + * + * Calibration On Time: Number of clock cycles that the calibration clock is enabled (cal_clk_en asserted). + */ +#define DDRPHY_PTR2_TCALON_MASK (0x1FU) +#define DDRPHY_PTR2_TCALON_SHIFT (0U) +#define DDRPHY_PTR2_TCALON_SET(x) (((uint32_t)(x) << DDRPHY_PTR2_TCALON_SHIFT) & DDRPHY_PTR2_TCALON_MASK) +#define DDRPHY_PTR2_TCALON_GET(x) (((uint32_t)(x) & DDRPHY_PTR2_TCALON_MASK) >> DDRPHY_PTR2_TCALON_SHIFT) + +/* Bitfield definition for register: PTR3 */ +/* + * TDINIT1 (R/W) + * + * DRAM Initialization Time 1: DRAM initialization time in DRAM clock cycles corresponding to the following: + * DDR3 = CKE high time to first command (tRFC + 10 ns or 5 tCK, whichever is bigger) DDR2 = CKE high time to first command (400 ns) + * Default value corresponds to DDR3 tRFC of 360ns at 1066 MHz. + */ +#define DDRPHY_PTR3_TDINIT1_MASK (0x1FF00000UL) +#define DDRPHY_PTR3_TDINIT1_SHIFT (20U) +#define DDRPHY_PTR3_TDINIT1_SET(x) (((uint32_t)(x) << DDRPHY_PTR3_TDINIT1_SHIFT) & DDRPHY_PTR3_TDINIT1_MASK) +#define DDRPHY_PTR3_TDINIT1_GET(x) (((uint32_t)(x) & DDRPHY_PTR3_TDINIT1_MASK) >> DDRPHY_PTR3_TDINIT1_SHIFT) + +/* + * TDINIT0 (R/W) + * + * DRAM Initialization Time 0: DRAM initialization time in DRAM clock cycles corresponding to the following: + * DDR3 = CKE low time with power and clock stable (500 us) DDR2 = CKE low time with power and clock stable (200 us) Default value corresponds to DDR3 500 us at 1066 MHz. + * During Verilog simulations, it is recommended that this value is changed to a much smaller value in order to avoid long simulation times. However, this may cause a memory model error, due to a violation of the CKE setup sequence. This violation is expected if this value is not programmed to the required SDRAM CKE low time, but memory models should be able to tolerate this violation without malfunction of the model. + */ +#define DDRPHY_PTR3_TDINIT0_MASK (0xFFFFFUL) +#define DDRPHY_PTR3_TDINIT0_SHIFT (0U) +#define DDRPHY_PTR3_TDINIT0_SET(x) (((uint32_t)(x) << DDRPHY_PTR3_TDINIT0_SHIFT) & DDRPHY_PTR3_TDINIT0_MASK) +#define DDRPHY_PTR3_TDINIT0_GET(x) (((uint32_t)(x) & DDRPHY_PTR3_TDINIT0_MASK) >> DDRPHY_PTR3_TDINIT0_SHIFT) + +/* Bitfield definition for register: PTR4 */ +/* + * TDINIT3 (R/W) + * + * DRAM Initialization Time 3: DRAM initialization time in DRAM clock cycles corresponding to the following: + * DDR3 = Time from ZQ initialization command to first command (1 us) Default value corresponds to the DDR3 640ns at 1066 MHz. + */ +#define DDRPHY_PTR4_TDINIT3_MASK (0xFFC0000UL) +#define DDRPHY_PTR4_TDINIT3_SHIFT (18U) +#define DDRPHY_PTR4_TDINIT3_SET(x) (((uint32_t)(x) << DDRPHY_PTR4_TDINIT3_SHIFT) & DDRPHY_PTR4_TDINIT3_MASK) +#define DDRPHY_PTR4_TDINIT3_GET(x) (((uint32_t)(x) & DDRPHY_PTR4_TDINIT3_MASK) >> DDRPHY_PTR4_TDINIT3_SHIFT) + +/* + * TDINIT2 (R/W) + * + * DRAM Initialization Time 2: DRAM initialization time in DRAM clock cycles corresponding to the following: + * DDR3 = Reset low time (200 us on power-up or 100 ns after power-up) Default value corresponds to DDR3 200 us at 1066 MHz. + */ +#define DDRPHY_PTR4_TDINIT2_MASK (0x3FFFFUL) +#define DDRPHY_PTR4_TDINIT2_SHIFT (0U) +#define DDRPHY_PTR4_TDINIT2_SET(x) (((uint32_t)(x) << DDRPHY_PTR4_TDINIT2_SHIFT) & DDRPHY_PTR4_TDINIT2_MASK) +#define DDRPHY_PTR4_TDINIT2_GET(x) (((uint32_t)(x) & DDRPHY_PTR4_TDINIT2_MASK) >> DDRPHY_PTR4_TDINIT2_SHIFT) + +/* Bitfield definition for register: ACMDLR */ +/* + * MDLD (R/W) + * + * MDL Delay: Delay select for the LCDL for the Master Delay Line. + */ +#define DDRPHY_ACMDLR_MDLD_MASK (0xFF0000UL) +#define DDRPHY_ACMDLR_MDLD_SHIFT (16U) +#define DDRPHY_ACMDLR_MDLD_SET(x) (((uint32_t)(x) << DDRPHY_ACMDLR_MDLD_SHIFT) & DDRPHY_ACMDLR_MDLD_MASK) +#define DDRPHY_ACMDLR_MDLD_GET(x) (((uint32_t)(x) & DDRPHY_ACMDLR_MDLD_MASK) >> DDRPHY_ACMDLR_MDLD_SHIFT) + +/* + * TPRD (R/W) + * + * Target Period: Target period measured by the master delay line calibration for VT drift compensation. This is the current measured value of the period and is continuously updated if the MDL is enabled to do so. + */ +#define DDRPHY_ACMDLR_TPRD_MASK (0xFF00U) +#define DDRPHY_ACMDLR_TPRD_SHIFT (8U) +#define DDRPHY_ACMDLR_TPRD_SET(x) (((uint32_t)(x) << DDRPHY_ACMDLR_TPRD_SHIFT) & DDRPHY_ACMDLR_TPRD_MASK) +#define DDRPHY_ACMDLR_TPRD_GET(x) (((uint32_t)(x) & DDRPHY_ACMDLR_TPRD_MASK) >> DDRPHY_ACMDLR_TPRD_SHIFT) + +/* + * IPRD (R/W) + * + * Initial Period: Initial period measured by the master delay line calibration for VT drift compensation. This value is used as the denominator when calculating the ratios of updates during VT compensation. + */ +#define DDRPHY_ACMDLR_IPRD_MASK (0xFFU) +#define DDRPHY_ACMDLR_IPRD_SHIFT (0U) +#define DDRPHY_ACMDLR_IPRD_SET(x) (((uint32_t)(x) << DDRPHY_ACMDLR_IPRD_SHIFT) & DDRPHY_ACMDLR_IPRD_MASK) +#define DDRPHY_ACMDLR_IPRD_GET(x) (((uint32_t)(x) & DDRPHY_ACMDLR_IPRD_MASK) >> DDRPHY_ACMDLR_IPRD_SHIFT) + +/* Bitfield definition for register: ACBDLR */ +/* + * ACBD (R/W) + * + * Address/Command Bit Delay: Delay select for the BDLs on address and command signals. + */ +#define DDRPHY_ACBDLR_ACBD_MASK (0xFC0000UL) +#define DDRPHY_ACBDLR_ACBD_SHIFT (18U) +#define DDRPHY_ACBDLR_ACBD_SET(x) (((uint32_t)(x) << DDRPHY_ACBDLR_ACBD_SHIFT) & DDRPHY_ACBDLR_ACBD_MASK) +#define DDRPHY_ACBDLR_ACBD_GET(x) (((uint32_t)(x) & DDRPHY_ACBDLR_ACBD_MASK) >> DDRPHY_ACBDLR_ACBD_SHIFT) + +/* + * CK2BD (R/W) + * + * CK2 Bit Delay: Delay select for the BDL on CK2. + */ +#define DDRPHY_ACBDLR_CK2BD_MASK (0x3F000UL) +#define DDRPHY_ACBDLR_CK2BD_SHIFT (12U) +#define DDRPHY_ACBDLR_CK2BD_SET(x) (((uint32_t)(x) << DDRPHY_ACBDLR_CK2BD_SHIFT) & DDRPHY_ACBDLR_CK2BD_MASK) +#define DDRPHY_ACBDLR_CK2BD_GET(x) (((uint32_t)(x) & DDRPHY_ACBDLR_CK2BD_MASK) >> DDRPHY_ACBDLR_CK2BD_SHIFT) + +/* + * CK1BD (R/W) + * + * CK1 Bit Delay: Delay select for the BDL on CK1. + */ +#define DDRPHY_ACBDLR_CK1BD_MASK (0xFC0U) +#define DDRPHY_ACBDLR_CK1BD_SHIFT (6U) +#define DDRPHY_ACBDLR_CK1BD_SET(x) (((uint32_t)(x) << DDRPHY_ACBDLR_CK1BD_SHIFT) & DDRPHY_ACBDLR_CK1BD_MASK) +#define DDRPHY_ACBDLR_CK1BD_GET(x) (((uint32_t)(x) & DDRPHY_ACBDLR_CK1BD_MASK) >> DDRPHY_ACBDLR_CK1BD_SHIFT) + +/* + * CK0BD (R/W) + * + * CK0 Bit Delay: Delay select for the BDL on CK0. + */ +#define DDRPHY_ACBDLR_CK0BD_MASK (0x3FU) +#define DDRPHY_ACBDLR_CK0BD_SHIFT (0U) +#define DDRPHY_ACBDLR_CK0BD_SET(x) (((uint32_t)(x) << DDRPHY_ACBDLR_CK0BD_SHIFT) & DDRPHY_ACBDLR_CK0BD_MASK) +#define DDRPHY_ACBDLR_CK0BD_GET(x) (((uint32_t)(x) & DDRPHY_ACBDLR_CK0BD_MASK) >> DDRPHY_ACBDLR_CK0BD_SHIFT) + +/* Bitfield definition for register: ACIOCR */ +/* + * ACSR (R/W) + * + * Address/Command Slew Rate (D3F I/O Only): Selects slew rate of the I/O for all address and command pins. + */ +#define DDRPHY_ACIOCR_ACSR_MASK (0xC0000000UL) +#define DDRPHY_ACIOCR_ACSR_SHIFT (30U) +#define DDRPHY_ACIOCR_ACSR_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_ACSR_SHIFT) & DDRPHY_ACIOCR_ACSR_MASK) +#define DDRPHY_ACIOCR_ACSR_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_ACSR_MASK) >> DDRPHY_ACIOCR_ACSR_SHIFT) + +/* + * RSTIOM (R/W) + * + * SDRAM Reset I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for SDRAM Reset. + */ +#define DDRPHY_ACIOCR_RSTIOM_MASK (0x20000000UL) +#define DDRPHY_ACIOCR_RSTIOM_SHIFT (29U) +#define DDRPHY_ACIOCR_RSTIOM_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_RSTIOM_SHIFT) & DDRPHY_ACIOCR_RSTIOM_MASK) +#define DDRPHY_ACIOCR_RSTIOM_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_RSTIOM_MASK) >> DDRPHY_ACIOCR_RSTIOM_SHIFT) + +/* + * RSTPDR (R/W) + * + * SDRAM Reset Power Down Receiver: Powers down, when set, the input receiver on the I/O for SDRAM RST# pin. + */ +#define DDRPHY_ACIOCR_RSTPDR_MASK (0x10000000UL) +#define DDRPHY_ACIOCR_RSTPDR_SHIFT (28U) +#define DDRPHY_ACIOCR_RSTPDR_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_RSTPDR_SHIFT) & DDRPHY_ACIOCR_RSTPDR_MASK) +#define DDRPHY_ACIOCR_RSTPDR_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_RSTPDR_MASK) >> DDRPHY_ACIOCR_RSTPDR_SHIFT) + +/* + * RSTPDD1 (R/W) + * + * SDRAM Reset Power Down Driver: Powers down, when set, the output driver on the I/O for SDRAM RST# pin. + */ +#define DDRPHY_ACIOCR_RSTPDD1_MASK (0x8000000UL) +#define DDRPHY_ACIOCR_RSTPDD1_SHIFT (27U) +#define DDRPHY_ACIOCR_RSTPDD1_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_RSTPDD1_SHIFT) & DDRPHY_ACIOCR_RSTPDD1_MASK) +#define DDRPHY_ACIOCR_RSTPDD1_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_RSTPDD1_MASK) >> DDRPHY_ACIOCR_RSTPDD1_SHIFT) + +/* + * RSTODT (R/W) + * + * SDRAM Reset On-Die Termination: Enables, when set, the on-die termination on the I/O for SDRAM RST# pin. + */ +#define DDRPHY_ACIOCR_RSTODT_MASK (0x4000000UL) +#define DDRPHY_ACIOCR_RSTODT_SHIFT (26U) +#define DDRPHY_ACIOCR_RSTODT_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_RSTODT_SHIFT) & DDRPHY_ACIOCR_RSTODT_MASK) +#define DDRPHY_ACIOCR_RSTODT_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_RSTODT_MASK) >> DDRPHY_ACIOCR_RSTODT_SHIFT) + +/* + * RANKPDR (R/W) + * + * Rank Power Down Receiver: Powers down, when set, the input receiver on the I/O CKE[3:0], ODT[3:0], and CS#[3:0] pins. RANKPDR[0] controls the power down for CKE[0], ODT[0], and CS#[0], RANKPDR[1] controls the power down for CKE[1], ODT[1], and CS#[1], and so on. + */ +#define DDRPHY_ACIOCR_RANKPDR_MASK (0x3C00000UL) +#define DDRPHY_ACIOCR_RANKPDR_SHIFT (22U) +#define DDRPHY_ACIOCR_RANKPDR_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_RANKPDR_SHIFT) & DDRPHY_ACIOCR_RANKPDR_MASK) +#define DDRPHY_ACIOCR_RANKPDR_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_RANKPDR_MASK) >> DDRPHY_ACIOCR_RANKPDR_SHIFT) + +/* + * CSPDD1 (R/W) + * + * CS# Power Down Driver: Powers down, when set, the output driver on the I/O for CS#[3:0] pins. CSPDD[0] controls the power down for CS#[0], CSPDD[1] controls the power down for CS#[1], and so on. CKE and ODT driver power down is controlled by DSGCR register. + */ +#define DDRPHY_ACIOCR_CSPDD1_MASK (0x3C0000UL) +#define DDRPHY_ACIOCR_CSPDD1_SHIFT (18U) +#define DDRPHY_ACIOCR_CSPDD1_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_CSPDD1_SHIFT) & DDRPHY_ACIOCR_CSPDD1_MASK) +#define DDRPHY_ACIOCR_CSPDD1_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_CSPDD1_MASK) >> DDRPHY_ACIOCR_CSPDD1_SHIFT) + +/* + * RANKODT (R/W) + * + * Rank On-Die Termination: Enables, when set, the on-die termination on the I/O for CKE[3:0], ODT[3:0], and CS#[3:0] pins. RANKODT[0] controls the on-die termination for CKE[0], ODT[0], and CS#[0], RANKODT[1] controls the on-die termination for CKE[1], ODT[1], and CS#[1], and so on. + */ +#define DDRPHY_ACIOCR_RANKODT_MASK (0x3C000UL) +#define DDRPHY_ACIOCR_RANKODT_SHIFT (14U) +#define DDRPHY_ACIOCR_RANKODT_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_RANKODT_SHIFT) & DDRPHY_ACIOCR_RANKODT_MASK) +#define DDRPHY_ACIOCR_RANKODT_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_RANKODT_MASK) >> DDRPHY_ACIOCR_RANKODT_SHIFT) + +/* + * CKPDR (R/W) + * + * CK Power Down Receiver: Powers down, when set, the input receiver on the I/O for CK[0], CK[1], and CK[2] pins, respectively. + */ +#define DDRPHY_ACIOCR_CKPDR_MASK (0x3800U) +#define DDRPHY_ACIOCR_CKPDR_SHIFT (11U) +#define DDRPHY_ACIOCR_CKPDR_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_CKPDR_SHIFT) & DDRPHY_ACIOCR_CKPDR_MASK) +#define DDRPHY_ACIOCR_CKPDR_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_CKPDR_MASK) >> DDRPHY_ACIOCR_CKPDR_SHIFT) + +/* + * CKPDD1 (R/W) + * + * CK Power Down Driver: Powers down, when set, the output driver on the I/O for CK[0], CK[1], and CK[2] pins, respectively. + */ +#define DDRPHY_ACIOCR_CKPDD1_MASK (0x700U) +#define DDRPHY_ACIOCR_CKPDD1_SHIFT (8U) +#define DDRPHY_ACIOCR_CKPDD1_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_CKPDD1_SHIFT) & DDRPHY_ACIOCR_CKPDD1_MASK) +#define DDRPHY_ACIOCR_CKPDD1_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_CKPDD1_MASK) >> DDRPHY_ACIOCR_CKPDD1_SHIFT) + +/* + * CKODT (R/W) + * + * CK On-Die Termination: Enables, when set, the on-die termination on the I/O for CK[0], CK[1], and CK[2] pins, respectively. + */ +#define DDRPHY_ACIOCR_CKODT_MASK (0xE0U) +#define DDRPHY_ACIOCR_CKODT_SHIFT (5U) +#define DDRPHY_ACIOCR_CKODT_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_CKODT_SHIFT) & DDRPHY_ACIOCR_CKODT_MASK) +#define DDRPHY_ACIOCR_CKODT_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_CKODT_MASK) >> DDRPHY_ACIOCR_CKODT_SHIFT) + +/* + * ACPDR (R/W) + * + * AC Power Down Receiver: Powers down, when set, the input receiver on the I/O for RAS#, CAS#, WE#, BA[2:0], and A[15:0] pins. + */ +#define DDRPHY_ACIOCR_ACPDR_MASK (0x10U) +#define DDRPHY_ACIOCR_ACPDR_SHIFT (4U) +#define DDRPHY_ACIOCR_ACPDR_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_ACPDR_SHIFT) & DDRPHY_ACIOCR_ACPDR_MASK) +#define DDRPHY_ACIOCR_ACPDR_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_ACPDR_MASK) >> DDRPHY_ACIOCR_ACPDR_SHIFT) + +/* + * ACPDD1 (R/W) + * + * AC Power Down Driver: Powers down, when set, the output driver on the I/O for RAS#, CAS#, WE#, BA[2:0], and A[15:0] pins. + */ +#define DDRPHY_ACIOCR_ACPDD1_MASK (0x8U) +#define DDRPHY_ACIOCR_ACPDD1_SHIFT (3U) +#define DDRPHY_ACIOCR_ACPDD1_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_ACPDD1_SHIFT) & DDRPHY_ACIOCR_ACPDD1_MASK) +#define DDRPHY_ACIOCR_ACPDD1_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_ACPDD1_MASK) >> DDRPHY_ACIOCR_ACPDD1_SHIFT) + +/* + * ACODT (R/W) + * + * Address/Command On-Die Termination: Enables, when set, the on-die termination on the I/O for RAS#, CAS#, WE#, BA[2:0], and A[15:0] pins. + */ +#define DDRPHY_ACIOCR_ACODT_MASK (0x4U) +#define DDRPHY_ACIOCR_ACODT_SHIFT (2U) +#define DDRPHY_ACIOCR_ACODT_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_ACODT_SHIFT) & DDRPHY_ACIOCR_ACODT_MASK) +#define DDRPHY_ACIOCR_ACODT_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_ACODT_MASK) >> DDRPHY_ACIOCR_ACODT_SHIFT) + +/* + * ACOE (R/W) + * + * Address/Command Output Enable: Enables, when set, the output driver on the I/O for all address and command pins. + */ +#define DDRPHY_ACIOCR_ACOE_MASK (0x2U) +#define DDRPHY_ACIOCR_ACOE_SHIFT (1U) +#define DDRPHY_ACIOCR_ACOE_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_ACOE_SHIFT) & DDRPHY_ACIOCR_ACOE_MASK) +#define DDRPHY_ACIOCR_ACOE_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_ACOE_MASK) >> DDRPHY_ACIOCR_ACOE_SHIFT) + +/* + * ACIOM (R/W) + * + * Address/Command I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for all address and command pins. This bit connects to bit + * [0] of the IOM pin on the D3F I/Os, and for other I/O libraries, it connects to the IOM pin of the I/O. + */ +#define DDRPHY_ACIOCR_ACIOM_MASK (0x1U) +#define DDRPHY_ACIOCR_ACIOM_SHIFT (0U) +#define DDRPHY_ACIOCR_ACIOM_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_ACIOM_SHIFT) & DDRPHY_ACIOCR_ACIOM_MASK) +#define DDRPHY_ACIOCR_ACIOM_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_ACIOM_MASK) >> DDRPHY_ACIOCR_ACIOM_SHIFT) + +/* Bitfield definition for register: DXCCR */ +/* + * DDPDRCDO (R/W) + * + * Dynamic Data Power Down Receiver Count Down Offset: Offset applied in calculating window of time where receiver is powered up + */ +#define DDRPHY_DXCCR_DDPDRCDO_MASK (0xF0000000UL) +#define DDRPHY_DXCCR_DDPDRCDO_SHIFT (28U) +#define DDRPHY_DXCCR_DDPDRCDO_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_DDPDRCDO_SHIFT) & DDRPHY_DXCCR_DDPDRCDO_MASK) +#define DDRPHY_DXCCR_DDPDRCDO_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_DDPDRCDO_MASK) >> DDRPHY_DXCCR_DDPDRCDO_SHIFT) + +/* + * DDPDDCDO (R/W) + * + * Dynamic Data Power Down Driver Count Down Offset: Offset applied in calculating window of time where driver is powered up + */ +#define DDRPHY_DXCCR_DDPDDCDO_MASK (0xF000000UL) +#define DDRPHY_DXCCR_DDPDDCDO_SHIFT (24U) +#define DDRPHY_DXCCR_DDPDDCDO_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_DDPDDCDO_SHIFT) & DDRPHY_DXCCR_DDPDDCDO_MASK) +#define DDRPHY_DXCCR_DDPDDCDO_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_DDPDDCDO_MASK) >> DDRPHY_DXCCR_DDPDDCDO_SHIFT) + +/* + * DYNDXPDR (R/W) + * + * Data Power Down Receiver: Dynamically powers down, when set, the input receiver on I/O for the DQ pins of the active DATX8 macros. Applies only when DXPDR and DXnGCR.DXPDR are not set to 1. Receiver is powered-up on a DFI READ command and powered-down (trddata_en + fixed_read_latency + n) HDR cycles after the last DFI READ command. Note that n is defined by the register bit field DXCCR[31:28] (DDPDRCDO). + */ +#define DDRPHY_DXCCR_DYNDXPDR_MASK (0x800000UL) +#define DDRPHY_DXCCR_DYNDXPDR_SHIFT (23U) +#define DDRPHY_DXCCR_DYNDXPDR_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_DYNDXPDR_SHIFT) & DDRPHY_DXCCR_DYNDXPDR_MASK) +#define DDRPHY_DXCCR_DYNDXPDR_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_DYNDXPDR_MASK) >> DDRPHY_DXCCR_DYNDXPDR_SHIFT) + +/* + * DYNDXPDD1 (R/W) + * + * Dynamic Data Power Down Driver: Dynamically powers down, when set, the output driver on I/O for the DQ pins of the active DATX8 macros. Applies only when DXPDD and DXnGCR.DXPDD are not set to 1. Driver is powered-up on a DFI WRITE command and powered-down (twrlat + WL/2 + n) HDR cycles after the last DFI WRITE command. Note that n is defined by the register bit field DXCCR[27:24] (DDPDDCDO). + */ +#define DDRPHY_DXCCR_DYNDXPDD1_MASK (0x400000UL) +#define DDRPHY_DXCCR_DYNDXPDD1_SHIFT (22U) +#define DDRPHY_DXCCR_DYNDXPDD1_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_DYNDXPDD1_SHIFT) & DDRPHY_DXCCR_DYNDXPDD1_MASK) +#define DDRPHY_DXCCR_DYNDXPDD1_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_DYNDXPDD1_MASK) >> DDRPHY_DXCCR_DYNDXPDD1_SHIFT) + +/* + * UDQIOM (R/W) + * + * Unused DQ I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for unused DQ pins. + */ +#define DDRPHY_DXCCR_UDQIOM_MASK (0x200000UL) +#define DDRPHY_DXCCR_UDQIOM_SHIFT (21U) +#define DDRPHY_DXCCR_UDQIOM_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_UDQIOM_SHIFT) & DDRPHY_DXCCR_UDQIOM_MASK) +#define DDRPHY_DXCCR_UDQIOM_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_UDQIOM_MASK) >> DDRPHY_DXCCR_UDQIOM_SHIFT) + +/* + * UDQPDR (R/W) + * + * Unused DQ Power Down Receiver: Powers down, when set, the input receiver on the I/O for unused DQ pins. + */ +#define DDRPHY_DXCCR_UDQPDR_MASK (0x100000UL) +#define DDRPHY_DXCCR_UDQPDR_SHIFT (20U) +#define DDRPHY_DXCCR_UDQPDR_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_UDQPDR_SHIFT) & DDRPHY_DXCCR_UDQPDR_MASK) +#define DDRPHY_DXCCR_UDQPDR_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_UDQPDR_MASK) >> DDRPHY_DXCCR_UDQPDR_SHIFT) + +/* + * UDQPDD1 (R/W) + * + * Unused DQ Power Down Driver: Powers down, when set, the output driver on the I/O for unused DQ pins. + */ +#define DDRPHY_DXCCR_UDQPDD1_MASK (0x80000UL) +#define DDRPHY_DXCCR_UDQPDD1_SHIFT (19U) +#define DDRPHY_DXCCR_UDQPDD1_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_UDQPDD1_SHIFT) & DDRPHY_DXCCR_UDQPDD1_MASK) +#define DDRPHY_DXCCR_UDQPDD1_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_UDQPDD1_MASK) >> DDRPHY_DXCCR_UDQPDD1_SHIFT) + +/* + * UDQODT (R/W) + * + * Unused DQ On-Die Termination: Enables, when set, the on-die termination on the I/O for unused DQ pins. + */ +#define DDRPHY_DXCCR_UDQODT_MASK (0x40000UL) +#define DDRPHY_DXCCR_UDQODT_SHIFT (18U) +#define DDRPHY_DXCCR_UDQODT_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_UDQODT_SHIFT) & DDRPHY_DXCCR_UDQODT_MASK) +#define DDRPHY_DXCCR_UDQODT_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_UDQODT_MASK) >> DDRPHY_DXCCR_UDQODT_SHIFT) + +/* + * MSBUDQ (R/W) + * + * Most Significant Byte Unused DQs: Specifies the number of DQ bits that are not used in the most significant byte. The used (valid) bits for this byte are [8-MSBDQ- 1:0]. To disable the whole byte, use the DXnGCR.DXEN register. + */ +#define DDRPHY_DXCCR_MSBUDQ_MASK (0x38000UL) +#define DDRPHY_DXCCR_MSBUDQ_SHIFT (15U) +#define DDRPHY_DXCCR_MSBUDQ_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_MSBUDQ_SHIFT) & DDRPHY_DXCCR_MSBUDQ_MASK) +#define DDRPHY_DXCCR_MSBUDQ_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_MSBUDQ_MASK) >> DDRPHY_DXCCR_MSBUDQ_SHIFT) + +/* + * DXSR (R/W) + * + * Data Slew Rate (D3F I/O Only): Selects slew rate of the I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. + */ +#define DDRPHY_DXCCR_DXSR_MASK (0x6000U) +#define DDRPHY_DXCCR_DXSR_SHIFT (13U) +#define DDRPHY_DXCCR_DXSR_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_DXSR_SHIFT) & DDRPHY_DXCCR_DXSR_MASK) +#define DDRPHY_DXCCR_DXSR_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_DXSR_MASK) >> DDRPHY_DXCCR_DXSR_SHIFT) + +/* + * DQSNRES (R/W) + * + * DQS# Resistor: Selects the on-die pull-up/pull-down resistor for DQS# pins. Same encoding as DQSRES. + * Refer PHY databook for pull-down/pull-up resistor values (RA_SEL/RB_SEL) for DQS/DQS_b. + */ +#define DDRPHY_DXCCR_DQSNRES_MASK (0x1E00U) +#define DDRPHY_DXCCR_DQSNRES_SHIFT (9U) +#define DDRPHY_DXCCR_DQSNRES_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_DQSNRES_SHIFT) & DDRPHY_DXCCR_DQSNRES_MASK) +#define DDRPHY_DXCCR_DQSNRES_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_DQSNRES_MASK) >> DDRPHY_DXCCR_DQSNRES_SHIFT) + +/* + * DQSRES (R/W) + * + * DQS Resistor: Selects the on-die pull-down/pull-up resistor for DQS pins. DQSRES[3] selects pull-down (when set to 0) or pull-up (when set to 1). DQSRES[2:0] selects the resistor value. + * Refer PHY databook for pull-down/pull-up resistor values (RA_SEL/RB_SEL) for DQS/DQS_b. + */ +#define DDRPHY_DXCCR_DQSRES_MASK (0x1E0U) +#define DDRPHY_DXCCR_DQSRES_SHIFT (5U) +#define DDRPHY_DXCCR_DQSRES_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_DQSRES_SHIFT) & DDRPHY_DXCCR_DQSRES_MASK) +#define DDRPHY_DXCCR_DQSRES_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_DQSRES_MASK) >> DDRPHY_DXCCR_DQSRES_SHIFT) + +/* + * DXPDR (R/W) + * + * Data Power Down Receiver: Powers down, when set, the input receiver on I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. This bit is ORed with the PDR configuration bit of the individual DATX8. + */ +#define DDRPHY_DXCCR_DXPDR_MASK (0x10U) +#define DDRPHY_DXCCR_DXPDR_SHIFT (4U) +#define DDRPHY_DXCCR_DXPDR_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_DXPDR_SHIFT) & DDRPHY_DXCCR_DXPDR_MASK) +#define DDRPHY_DXCCR_DXPDR_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_DXPDR_MASK) >> DDRPHY_DXCCR_DXPDR_SHIFT) + +/* + * DXPDD1 (R/W) + * + * Data Power Down Driver: Powers down, when set, the output driver on I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. This bit is ORed with the PDD configuration bit of the individual DATX8. + */ +#define DDRPHY_DXCCR_DXPDD1_MASK (0x8U) +#define DDRPHY_DXCCR_DXPDD1_SHIFT (3U) +#define DDRPHY_DXCCR_DXPDD1_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_DXPDD1_SHIFT) & DDRPHY_DXCCR_DXPDD1_MASK) +#define DDRPHY_DXCCR_DXPDD1_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_DXPDD1_MASK) >> DDRPHY_DXCCR_DXPDD1_SHIFT) + +/* + * MDLEN (R/W) + * + * Master Delay Line Enable: Enables, if set, all DATX8 master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or on when calibration is manually triggered. These additional measurements are accumulated and filtered as long as this bit remains high. This bit is ANDed with the MDLEN bit in the individual DATX8. + */ +#define DDRPHY_DXCCR_MDLEN_MASK (0x4U) +#define DDRPHY_DXCCR_MDLEN_SHIFT (2U) +#define DDRPHY_DXCCR_MDLEN_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_MDLEN_SHIFT) & DDRPHY_DXCCR_MDLEN_MASK) +#define DDRPHY_DXCCR_MDLEN_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_MDLEN_MASK) >> DDRPHY_DXCCR_MDLEN_SHIFT) + +/* + * DXIOM (R/W) + * + * Data I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. This bit is ORed with the IOM configuration bit of the individual DATX8. + */ +#define DDRPHY_DXCCR_DXIOM_MASK (0x2U) +#define DDRPHY_DXCCR_DXIOM_SHIFT (1U) +#define DDRPHY_DXCCR_DXIOM_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_DXIOM_SHIFT) & DDRPHY_DXCCR_DXIOM_MASK) +#define DDRPHY_DXCCR_DXIOM_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_DXIOM_MASK) >> DDRPHY_DXCCR_DXIOM_SHIFT) + +/* + * DXODT (R/W) + * + * Data On-Die Termination: Enables, when set, the on-die termination on the I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. This bit is ORed with the ODT configuration bit of the individual DATX8 (“DATX8 General Configuration Register (DXnGCR)” on page 148) + */ +#define DDRPHY_DXCCR_DXODT_MASK (0x1U) +#define DDRPHY_DXCCR_DXODT_SHIFT (0U) +#define DDRPHY_DXCCR_DXODT_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_DXODT_SHIFT) & DDRPHY_DXCCR_DXODT_MASK) +#define DDRPHY_DXCCR_DXODT_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_DXODT_MASK) >> DDRPHY_DXCCR_DXODT_SHIFT) + +/* Bitfield definition for register: DSGCR */ +/* + * CKEOE (R/W) + * + * SDRAM CKE Output Enable: Enables, when set, the output driver on the I/O for SDRAM CKE pins. + */ +#define DDRPHY_DSGCR_CKEOE_MASK (0x80000000UL) +#define DDRPHY_DSGCR_CKEOE_SHIFT (31U) +#define DDRPHY_DSGCR_CKEOE_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_CKEOE_SHIFT) & DDRPHY_DSGCR_CKEOE_MASK) +#define DDRPHY_DSGCR_CKEOE_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_CKEOE_MASK) >> DDRPHY_DSGCR_CKEOE_SHIFT) + +/* + * RSTOE (R/W) + * + * SDRAM Reset Output Enable: Enables, when set, the output driver on the I/O for SDRAM RST# pin. + */ +#define DDRPHY_DSGCR_RSTOE_MASK (0x40000000UL) +#define DDRPHY_DSGCR_RSTOE_SHIFT (30U) +#define DDRPHY_DSGCR_RSTOE_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_RSTOE_SHIFT) & DDRPHY_DSGCR_RSTOE_MASK) +#define DDRPHY_DSGCR_RSTOE_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_RSTOE_MASK) >> DDRPHY_DSGCR_RSTOE_SHIFT) + +/* + * ODTOE (R/W) + * + * SDRAM ODT Output Enable: Enables, when set, the output driver on the I/O for SDRAM ODT pins. + */ +#define DDRPHY_DSGCR_ODTOE_MASK (0x20000000UL) +#define DDRPHY_DSGCR_ODTOE_SHIFT (29U) +#define DDRPHY_DSGCR_ODTOE_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_ODTOE_SHIFT) & DDRPHY_DSGCR_ODTOE_MASK) +#define DDRPHY_DSGCR_ODTOE_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_ODTOE_MASK) >> DDRPHY_DSGCR_ODTOE_SHIFT) + +/* + * CKOE (R/W) + * + * SDRAM CK Output Enable: Enables, when set, the output driver on the I/O for SDRAM CK/CK# pins. + */ +#define DDRPHY_DSGCR_CKOE_MASK (0x10000000UL) +#define DDRPHY_DSGCR_CKOE_SHIFT (28U) +#define DDRPHY_DSGCR_CKOE_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_CKOE_SHIFT) & DDRPHY_DSGCR_CKOE_MASK) +#define DDRPHY_DSGCR_CKOE_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_CKOE_MASK) >> DDRPHY_DSGCR_CKOE_SHIFT) + +/* + * ODTPDD1 (R/W) + * + * ODT Power Down Driver: Powers down, when set, the output driver on the I/O for ODT[3:0] pins. ODTPDD[0] controls the power down for ODT[0], ODTPDD[1] controls the power down for ODT[1], and so on. + */ +#define DDRPHY_DSGCR_ODTPDD1_MASK (0xF000000UL) +#define DDRPHY_DSGCR_ODTPDD1_SHIFT (24U) +#define DDRPHY_DSGCR_ODTPDD1_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_ODTPDD1_SHIFT) & DDRPHY_DSGCR_ODTPDD1_MASK) +#define DDRPHY_DSGCR_ODTPDD1_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_ODTPDD1_MASK) >> DDRPHY_DSGCR_ODTPDD1_SHIFT) + +/* + * CKEPDD1 (R/W) + * + * CKE Power Down Driver: Powers down, when set, the output driver on the I/O for CKE[3:0] pins. CKEPDD[0] controls the power down for CKE[0], CKEPDD[1] controls the power down for CKE[1], and so on. + */ +#define DDRPHY_DSGCR_CKEPDD1_MASK (0xF00000UL) +#define DDRPHY_DSGCR_CKEPDD1_SHIFT (20U) +#define DDRPHY_DSGCR_CKEPDD1_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_CKEPDD1_SHIFT) & DDRPHY_DSGCR_CKEPDD1_MASK) +#define DDRPHY_DSGCR_CKEPDD1_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_CKEPDD1_MASK) >> DDRPHY_DSGCR_CKEPDD1_SHIFT) + +/* + * SDRMODE (R/W) + * + * Single Data Rate Mode: Indicates, if set, that the external controller is configured to run in single data rate (SDR) mode. Otherwise if not set the controller is running in half data rate (HDR) mode. This bit not supported in the current version of the PUB. + */ +#define DDRPHY_DSGCR_SDRMODE_MASK (0x80000UL) +#define DDRPHY_DSGCR_SDRMODE_SHIFT (19U) +#define DDRPHY_DSGCR_SDRMODE_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_SDRMODE_SHIFT) & DDRPHY_DSGCR_SDRMODE_MASK) +#define DDRPHY_DSGCR_SDRMODE_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_SDRMODE_MASK) >> DDRPHY_DSGCR_SDRMODE_SHIFT) + +/* + * RRMODE (R/W) + * + * Rise-to-Rise Mode: Indicates, if set, that the PHY mission mode is configured to run in rise-to-rise mode. Otherwise if not set the PHY mission mode is running in rise-to- fall mode. + */ +#define DDRPHY_DSGCR_RRMODE_MASK (0x40000UL) +#define DDRPHY_DSGCR_RRMODE_SHIFT (18U) +#define DDRPHY_DSGCR_RRMODE_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_RRMODE_SHIFT) & DDRPHY_DSGCR_RRMODE_MASK) +#define DDRPHY_DSGCR_RRMODE_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_RRMODE_MASK) >> DDRPHY_DSGCR_RRMODE_SHIFT) + +/* + * ATOAE (R/W) + * + * ATO Analog Test Enable: Enables, if set, the analog test output (ATO) I/O. + */ +#define DDRPHY_DSGCR_ATOAE_MASK (0x20000UL) +#define DDRPHY_DSGCR_ATOAE_SHIFT (17U) +#define DDRPHY_DSGCR_ATOAE_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_ATOAE_SHIFT) & DDRPHY_DSGCR_ATOAE_MASK) +#define DDRPHY_DSGCR_ATOAE_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_ATOAE_MASK) >> DDRPHY_DSGCR_ATOAE_SHIFT) + +/* + * DTOOE (R/W) + * + * DTO Output Enable: Enables, when set, the output driver on the I/O for DTO pins. + */ +#define DDRPHY_DSGCR_DTOOE_MASK (0x10000UL) +#define DDRPHY_DSGCR_DTOOE_SHIFT (16U) +#define DDRPHY_DSGCR_DTOOE_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_DTOOE_SHIFT) & DDRPHY_DSGCR_DTOOE_MASK) +#define DDRPHY_DSGCR_DTOOE_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_DTOOE_MASK) >> DDRPHY_DSGCR_DTOOE_SHIFT) + +/* + * DTOIOM (R/W) + * + * DTO I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DTO pins. + */ +#define DDRPHY_DSGCR_DTOIOM_MASK (0x8000U) +#define DDRPHY_DSGCR_DTOIOM_SHIFT (15U) +#define DDRPHY_DSGCR_DTOIOM_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_DTOIOM_SHIFT) & DDRPHY_DSGCR_DTOIOM_MASK) +#define DDRPHY_DSGCR_DTOIOM_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_DTOIOM_MASK) >> DDRPHY_DSGCR_DTOIOM_SHIFT) + +/* + * DTOPDR (R/W) + * + * DTO Power Down Receiver: Powers down, when set, the input receiver on the I/O for DTO pins. + */ +#define DDRPHY_DSGCR_DTOPDR_MASK (0x4000U) +#define DDRPHY_DSGCR_DTOPDR_SHIFT (14U) +#define DDRPHY_DSGCR_DTOPDR_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_DTOPDR_SHIFT) & DDRPHY_DSGCR_DTOPDR_MASK) +#define DDRPHY_DSGCR_DTOPDR_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_DTOPDR_MASK) >> DDRPHY_DSGCR_DTOPDR_SHIFT) + +/* + * DTOPDD1 (R/W) + * + * DTO Power Down Driver: Powers down, when set, the output driver on the I/O for DTO pins. + */ +#define DDRPHY_DSGCR_DTOPDD1_MASK (0x2000U) +#define DDRPHY_DSGCR_DTOPDD1_SHIFT (13U) +#define DDRPHY_DSGCR_DTOPDD1_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_DTOPDD1_SHIFT) & DDRPHY_DSGCR_DTOPDD1_MASK) +#define DDRPHY_DSGCR_DTOPDD1_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_DTOPDD1_MASK) >> DDRPHY_DSGCR_DTOPDD1_SHIFT) + +/* + * DTOODT (R/W) + * + * DTO On-Die Termination: Enables, when set, the on-die termination on the I/O for DTO pins. + */ +#define DDRPHY_DSGCR_DTOODT_MASK (0x1000U) +#define DDRPHY_DSGCR_DTOODT_SHIFT (12U) +#define DDRPHY_DSGCR_DTOODT_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_DTOODT_SHIFT) & DDRPHY_DSGCR_DTOODT_MASK) +#define DDRPHY_DSGCR_DTOODT_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_DTOODT_MASK) >> DDRPHY_DSGCR_DTOODT_SHIFT) + +/* + * PUAD (R/W) + * + * PHY Update Acknowledge Delay: Specifies the number of clock cycles that the indication for the completion of PHY update from the PHY to the controller should be delayed. This essentially delays, by this many clock cycles, the de-assertion of dfi_ctrlup_ack and dfi_phyupd_req signals relative to the time when the delay lines or I/Os are updated. + */ +#define DDRPHY_DSGCR_PUAD_MASK (0xF00U) +#define DDRPHY_DSGCR_PUAD_SHIFT (8U) +#define DDRPHY_DSGCR_PUAD_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_PUAD_SHIFT) & DDRPHY_DSGCR_PUAD_MASK) +#define DDRPHY_DSGCR_PUAD_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_PUAD_MASK) >> DDRPHY_DSGCR_PUAD_SHIFT) + +/* + * BRRMODE (R/W) + * + * Bypass Rise-to-Rise Mode: Indicates, if set, that the PHY bypass mode is configured to run in rise-to-rise mode. Otherwise if not set the PHY bypass mode is running in rise-to-fall mode. + */ +#define DDRPHY_DSGCR_BRRMODE_MASK (0x80U) +#define DDRPHY_DSGCR_BRRMODE_SHIFT (7U) +#define DDRPHY_DSGCR_BRRMODE_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_BRRMODE_SHIFT) & DDRPHY_DSGCR_BRRMODE_MASK) +#define DDRPHY_DSGCR_BRRMODE_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_BRRMODE_MASK) >> DDRPHY_DSGCR_BRRMODE_SHIFT) + +/* + * DQSGX (R/W) + * + * DQS Gate Extension: Specifies, if set, that the DQS gating must be extended by two DRAM clock cycles and then re-centered, i.e. one clock cycle extension on either side. + */ +#define DDRPHY_DSGCR_DQSGX_MASK (0x40U) +#define DDRPHY_DSGCR_DQSGX_SHIFT (6U) +#define DDRPHY_DSGCR_DQSGX_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_DQSGX_SHIFT) & DDRPHY_DSGCR_DQSGX_MASK) +#define DDRPHY_DSGCR_DQSGX_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_DQSGX_MASK) >> DDRPHY_DSGCR_DQSGX_SHIFT) + +/* + * CUAEN (R/W) + * + * Controller Update Acknowledge Enable: Specifies, if set, that the PHY should issue controller update acknowledge when the DFI controller update request is asserted. By default the PHY does not acknowledge controller initiated update requests but simply does an update whenever there is a controller update request. This speeds up the update. + */ +#define DDRPHY_DSGCR_CUAEN_MASK (0x20U) +#define DDRPHY_DSGCR_CUAEN_SHIFT (5U) +#define DDRPHY_DSGCR_CUAEN_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_CUAEN_SHIFT) & DDRPHY_DSGCR_CUAEN_MASK) +#define DDRPHY_DSGCR_CUAEN_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_CUAEN_MASK) >> DDRPHY_DSGCR_CUAEN_SHIFT) + +/* + * LPPLLPD (R/W) + * + * Low Power PLL Power Down: Specifies, if set, that the PHY should respond to the DFI low power opportunity request and power down the PLL of the byte if the wakeup time request satisfies the PLL lock time. + */ +#define DDRPHY_DSGCR_LPPLLPD_MASK (0x10U) +#define DDRPHY_DSGCR_LPPLLPD_SHIFT (4U) +#define DDRPHY_DSGCR_LPPLLPD_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_LPPLLPD_SHIFT) & DDRPHY_DSGCR_LPPLLPD_MASK) +#define DDRPHY_DSGCR_LPPLLPD_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_LPPLLPD_MASK) >> DDRPHY_DSGCR_LPPLLPD_SHIFT) + +/* + * LPIOPD (R/W) + * + * Low Power I/O Power Down: Specifies, if set, that the PHY should respond to the DFI low power opportunity request and power down the I/Os of the byte. + */ +#define DDRPHY_DSGCR_LPIOPD_MASK (0x8U) +#define DDRPHY_DSGCR_LPIOPD_SHIFT (3U) +#define DDRPHY_DSGCR_LPIOPD_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_LPIOPD_SHIFT) & DDRPHY_DSGCR_LPIOPD_MASK) +#define DDRPHY_DSGCR_LPIOPD_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_LPIOPD_MASK) >> DDRPHY_DSGCR_LPIOPD_SHIFT) + +/* + * ZUEN (R/W) + * + * Impedance Update Enable: Specifies, if set, that in addition to DDL VT update, the PHY could also perform impedance calibration (update). + * Refer to the “Impedance Control Register 0-1 (ZQnCR0-1)” on page 145 bit fields DFICU0, DFICU1 and DFICCU bits to control if an impedance calibration is performed (update) with a DFI controller update request. + * Refer to the “Impedance Control Register 0-1 (ZQnCR0-1)” on page 145 bit fields DFIPU0 and DFIPU1 bits to control if an impedance calibration is performed (update) with a DFI PHY update request. + */ +#define DDRPHY_DSGCR_ZUEN_MASK (0x4U) +#define DDRPHY_DSGCR_ZUEN_SHIFT (2U) +#define DDRPHY_DSGCR_ZUEN_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_ZUEN_SHIFT) & DDRPHY_DSGCR_ZUEN_MASK) +#define DDRPHY_DSGCR_ZUEN_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_ZUEN_MASK) >> DDRPHY_DSGCR_ZUEN_SHIFT) + +/* + * BDISEN (R/W) + * + * Byte Disable Enable: Specifies, if set, that the PHY should respond to DFI byte disable request. Otherwise the byte disable from the DFI is ignored in which case bytes can only be disabled using the DXnGCR register. + */ +#define DDRPHY_DSGCR_BDISEN_MASK (0x2U) +#define DDRPHY_DSGCR_BDISEN_SHIFT (1U) +#define DDRPHY_DSGCR_BDISEN_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_BDISEN_SHIFT) & DDRPHY_DSGCR_BDISEN_MASK) +#define DDRPHY_DSGCR_BDISEN_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_BDISEN_MASK) >> DDRPHY_DSGCR_BDISEN_SHIFT) + +/* + * PUREN (R/W) + * + * PHY Update Request Enable: Specifies if set, that the PHY should issue PHY- initiated update request when there is DDL VT drift. + */ +#define DDRPHY_DSGCR_PUREN_MASK (0x1U) +#define DDRPHY_DSGCR_PUREN_SHIFT (0U) +#define DDRPHY_DSGCR_PUREN_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_PUREN_SHIFT) & DDRPHY_DSGCR_PUREN_MASK) +#define DDRPHY_DSGCR_PUREN_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_PUREN_MASK) >> DDRPHY_DSGCR_PUREN_SHIFT) + +/* Bitfield definition for register: DCR */ +/* + * UDIMM (R/W) + * + * Un-buffered DIMM Address Mirroring: Indicates, if set, that there is address mirroring on the second rank of an un-buffered DIMM (the rank connected to CS#[1]). In this case, the PUB re-scrambles the bank and address when sending mode register commands to the second rank. This only applies to PUB internal SDRAM transactions. Transactions generated by the controller must make its own adjustments when using an un-buffered DIMM. DCR[NOSRA] must be set if address mirroring is enabled. + */ +#define DDRPHY_DCR_UDIMM_MASK (0x20000000UL) +#define DDRPHY_DCR_UDIMM_SHIFT (29U) +#define DDRPHY_DCR_UDIMM_SET(x) (((uint32_t)(x) << DDRPHY_DCR_UDIMM_SHIFT) & DDRPHY_DCR_UDIMM_MASK) +#define DDRPHY_DCR_UDIMM_GET(x) (((uint32_t)(x) & DDRPHY_DCR_UDIMM_MASK) >> DDRPHY_DCR_UDIMM_SHIFT) + +/* + * DDR2T (R/W) + * + * DDR 2T Timing: Indicates, if set, that 2T timing should be used by PUB internally generated SDRAM transactions. + */ +#define DDRPHY_DCR_DDR2T_MASK (0x10000000UL) +#define DDRPHY_DCR_DDR2T_SHIFT (28U) +#define DDRPHY_DCR_DDR2T_SET(x) (((uint32_t)(x) << DDRPHY_DCR_DDR2T_SHIFT) & DDRPHY_DCR_DDR2T_MASK) +#define DDRPHY_DCR_DDR2T_GET(x) (((uint32_t)(x) & DDRPHY_DCR_DDR2T_MASK) >> DDRPHY_DCR_DDR2T_SHIFT) + +/* + * NOSRA (R/W) + * + * No Simultaneous Rank Access: Specifies, if set, that simultaneous rank access on the same clock cycle is not allowed. This means that multiple chip select signals should not be asserted at the same time. This may be required on some DIMM systems. + */ +#define DDRPHY_DCR_NOSRA_MASK (0x8000000UL) +#define DDRPHY_DCR_NOSRA_SHIFT (27U) +#define DDRPHY_DCR_NOSRA_SET(x) (((uint32_t)(x) << DDRPHY_DCR_NOSRA_SHIFT) & DDRPHY_DCR_NOSRA_MASK) +#define DDRPHY_DCR_NOSRA_GET(x) (((uint32_t)(x) & DDRPHY_DCR_NOSRA_MASK) >> DDRPHY_DCR_NOSRA_SHIFT) + +/* + * BYTEMASK (R/W) + * + * Byte Mask: Mask applied to all beats of read data on all bytes lanes during read DQS gate training. This allows training to be conducted based on selected bit(s) from the byte lanes. + * Valid values for each bit are: + * 0 = Disable compare for that bit 1 = Enable compare for that bit + * Note that this mask applies in DDR3 MPR operation mode as well and must be in keeping with the PDQ field setting. + */ +#define DDRPHY_DCR_BYTEMASK_MASK (0x3FC00UL) +#define DDRPHY_DCR_BYTEMASK_SHIFT (10U) +#define DDRPHY_DCR_BYTEMASK_SET(x) (((uint32_t)(x) << DDRPHY_DCR_BYTEMASK_SHIFT) & DDRPHY_DCR_BYTEMASK_MASK) +#define DDRPHY_DCR_BYTEMASK_GET(x) (((uint32_t)(x) & DDRPHY_DCR_BYTEMASK_MASK) >> DDRPHY_DCR_BYTEMASK_SHIFT) + +/* + * MPRDQ (R/W) + * + * Multi-Purpose Register (MPR) DQ (DDR3 Only): Specifies the value that is driven on non-primary DQ pins during MPR reads. Valid values are: + * 0 = Primary DQ drives out the data from MPR (0-1-0-1); non-primary DQs drive ‘0’ 1 = Primary DQ and non-primary DQs all drive the same data from MPR (0-1-0-1) + */ +#define DDRPHY_DCR_MPRDQ_MASK (0x80U) +#define DDRPHY_DCR_MPRDQ_SHIFT (7U) +#define DDRPHY_DCR_MPRDQ_SET(x) (((uint32_t)(x) << DDRPHY_DCR_MPRDQ_SHIFT) & DDRPHY_DCR_MPRDQ_MASK) +#define DDRPHY_DCR_MPRDQ_GET(x) (((uint32_t)(x) & DDRPHY_DCR_MPRDQ_MASK) >> DDRPHY_DCR_MPRDQ_SHIFT) + +/* + * PDQ (R/W) + * + * Primary DQ (DDR3 Only): Specifies the DQ pin in a byte that is designated as a primary pin for Multi-Purpose Register (MPR) reads. Valid values are 0 to 7 for DQ[0] to DQ[7], respectively. + */ +#define DDRPHY_DCR_PDQ_MASK (0x70U) +#define DDRPHY_DCR_PDQ_SHIFT (4U) +#define DDRPHY_DCR_PDQ_SET(x) (((uint32_t)(x) << DDRPHY_DCR_PDQ_SHIFT) & DDRPHY_DCR_PDQ_MASK) +#define DDRPHY_DCR_PDQ_GET(x) (((uint32_t)(x) & DDRPHY_DCR_PDQ_MASK) >> DDRPHY_DCR_PDQ_SHIFT) + +/* + * DDR8BNK (R/W) + * + * DDR 8-Bank: Indicates, if set, that the SDRAM used has 8 banks. tRPA = tRP+1 and tFAW are used for 8-bank DRAMs, otherwise tRPA = tRP and no tFAW is used. + * Note that a setting of 1 for DRAMs that have fewer than 8 banks results in correct functionality, but less tight DRAM command spacing for the parameters. + */ +#define DDRPHY_DCR_DDR8BNK_MASK (0x8U) +#define DDRPHY_DCR_DDR8BNK_SHIFT (3U) +#define DDRPHY_DCR_DDR8BNK_SET(x) (((uint32_t)(x) << DDRPHY_DCR_DDR8BNK_SHIFT) & DDRPHY_DCR_DDR8BNK_MASK) +#define DDRPHY_DCR_DDR8BNK_GET(x) (((uint32_t)(x) & DDRPHY_DCR_DDR8BNK_MASK) >> DDRPHY_DCR_DDR8BNK_SHIFT) + +/* + * DDRMD (R/W) + * + * DDR Mode: SDRAM DDR mode. Valid values are: 000 = Reserved + * 001 = Reserved + * 010 = DDR2 + * 011 = DDR3 + * 100 – 111 = Reserved + */ +#define DDRPHY_DCR_DDRMD_MASK (0x7U) +#define DDRPHY_DCR_DDRMD_SHIFT (0U) +#define DDRPHY_DCR_DDRMD_SET(x) (((uint32_t)(x) << DDRPHY_DCR_DDRMD_SHIFT) & DDRPHY_DCR_DDRMD_MASK) +#define DDRPHY_DCR_DDRMD_GET(x) (((uint32_t)(x) & DDRPHY_DCR_DDRMD_MASK) >> DDRPHY_DCR_DDRMD_SHIFT) + +/* Bitfield definition for register: DTPR0 */ +/* + * TRC (R/W) + * + * Activate to activate command delay (same bank). Valid values are 2 to 63. + */ +#define DDRPHY_DTPR0_TRC_MASK (0xFC000000UL) +#define DDRPHY_DTPR0_TRC_SHIFT (26U) +#define DDRPHY_DTPR0_TRC_SET(x) (((uint32_t)(x) << DDRPHY_DTPR0_TRC_SHIFT) & DDRPHY_DTPR0_TRC_MASK) +#define DDRPHY_DTPR0_TRC_GET(x) (((uint32_t)(x) & DDRPHY_DTPR0_TRC_MASK) >> DDRPHY_DTPR0_TRC_SHIFT) + +/* + * TRRD (R/W) + * + * Activate to activate command delay (different banks). Valid values are 1 to 15. + */ +#define DDRPHY_DTPR0_TRRD_MASK (0x3C00000UL) +#define DDRPHY_DTPR0_TRRD_SHIFT (22U) +#define DDRPHY_DTPR0_TRRD_SET(x) (((uint32_t)(x) << DDRPHY_DTPR0_TRRD_SHIFT) & DDRPHY_DTPR0_TRRD_MASK) +#define DDRPHY_DTPR0_TRRD_GET(x) (((uint32_t)(x) & DDRPHY_DTPR0_TRRD_MASK) >> DDRPHY_DTPR0_TRRD_SHIFT) + +/* + * TRAS (R/W) + * + * Activate to precharge command delay. Valid values are 2 to 63. + */ +#define DDRPHY_DTPR0_TRAS_MASK (0x3F0000UL) +#define DDRPHY_DTPR0_TRAS_SHIFT (16U) +#define DDRPHY_DTPR0_TRAS_SET(x) (((uint32_t)(x) << DDRPHY_DTPR0_TRAS_SHIFT) & DDRPHY_DTPR0_TRAS_MASK) +#define DDRPHY_DTPR0_TRAS_GET(x) (((uint32_t)(x) & DDRPHY_DTPR0_TRAS_MASK) >> DDRPHY_DTPR0_TRAS_SHIFT) + +/* + * TRCD (R/W) + * + * Activate to read or write delay. Minimum time from when an activate command is issued to when a read or write to the activated row can be issued. Valid values are 2 to 15. + */ +#define DDRPHY_DTPR0_TRCD_MASK (0xF000U) +#define DDRPHY_DTPR0_TRCD_SHIFT (12U) +#define DDRPHY_DTPR0_TRCD_SET(x) (((uint32_t)(x) << DDRPHY_DTPR0_TRCD_SHIFT) & DDRPHY_DTPR0_TRCD_MASK) +#define DDRPHY_DTPR0_TRCD_GET(x) (((uint32_t)(x) & DDRPHY_DTPR0_TRCD_MASK) >> DDRPHY_DTPR0_TRCD_SHIFT) + +/* + * TRP (R/W) + * + * Precharge command period: The minimum time between a precharge command and any other command. Note that the Controller automatically derives tRPA for 8- bank DDR2 devices by adding 1 to tRP. Valid values are 2 to 15. + */ +#define DDRPHY_DTPR0_TRP_MASK (0xF00U) +#define DDRPHY_DTPR0_TRP_SHIFT (8U) +#define DDRPHY_DTPR0_TRP_SET(x) (((uint32_t)(x) << DDRPHY_DTPR0_TRP_SHIFT) & DDRPHY_DTPR0_TRP_MASK) +#define DDRPHY_DTPR0_TRP_GET(x) (((uint32_t)(x) & DDRPHY_DTPR0_TRP_MASK) >> DDRPHY_DTPR0_TRP_SHIFT) + +/* + * TWTR (R/W) + * + * Internal write to read command delay. Valid values are 1 to 15. + */ +#define DDRPHY_DTPR0_TWTR_MASK (0xF0U) +#define DDRPHY_DTPR0_TWTR_SHIFT (4U) +#define DDRPHY_DTPR0_TWTR_SET(x) (((uint32_t)(x) << DDRPHY_DTPR0_TWTR_SHIFT) & DDRPHY_DTPR0_TWTR_MASK) +#define DDRPHY_DTPR0_TWTR_GET(x) (((uint32_t)(x) & DDRPHY_DTPR0_TWTR_MASK) >> DDRPHY_DTPR0_TWTR_SHIFT) + +/* + * TRTP (R/W) + * + * Internal read to precharge command delay. Valid values are 2 to 15. + */ +#define DDRPHY_DTPR0_TRTP_MASK (0xFU) +#define DDRPHY_DTPR0_TRTP_SHIFT (0U) +#define DDRPHY_DTPR0_TRTP_SET(x) (((uint32_t)(x) << DDRPHY_DTPR0_TRTP_SHIFT) & DDRPHY_DTPR0_TRTP_MASK) +#define DDRPHY_DTPR0_TRTP_GET(x) (((uint32_t)(x) & DDRPHY_DTPR0_TRTP_MASK) >> DDRPHY_DTPR0_TRTP_SHIFT) + +/* Bitfield definition for register: DTPR1 */ +/* + * TAOND_TAOFD (R/W) + * + * ODT turn-on/turn-off delays (DDR2 only). Valid values are: 00 = 2/2.5 + * 01 = 3/3.5 + * 10 = 4/4.5 + * 11 = 5/5.5 + * Most DDR2 devices utilize a fixed value of 2/2.5. For non-standard SDRAMs, the user must ensure that the operational Write Latency is always greater than or equal to the ODT turn-on delay. For example, a DDR2 SDRAM with CAS latency set to 3 and CAS additive latency set to 0 has a Write Latency of 2. Thus 2/2.5 can be used, but not 3/3.5 or higher. + */ +#define DDRPHY_DTPR1_TAOND_TAOFD_MASK (0xC0000000UL) +#define DDRPHY_DTPR1_TAOND_TAOFD_SHIFT (30U) +#define DDRPHY_DTPR1_TAOND_TAOFD_SET(x) (((uint32_t)(x) << DDRPHY_DTPR1_TAOND_TAOFD_SHIFT) & DDRPHY_DTPR1_TAOND_TAOFD_MASK) +#define DDRPHY_DTPR1_TAOND_TAOFD_GET(x) (((uint32_t)(x) & DDRPHY_DTPR1_TAOND_TAOFD_MASK) >> DDRPHY_DTPR1_TAOND_TAOFD_SHIFT) + +/* + * TWLO (R/W) + * + * Write leveling output delay: Number of clock cycles from when write leveling DQS is driven high by the control block to when the results from the SDRAM on DQ is sampled by the control block. This must include the SDRAM tWLO timing parameter plus the round trip delay from control block to SDRAM back to control block. + */ +#define DDRPHY_DTPR1_TWLO_MASK (0x3C000000UL) +#define DDRPHY_DTPR1_TWLO_SHIFT (26U) +#define DDRPHY_DTPR1_TWLO_SET(x) (((uint32_t)(x) << DDRPHY_DTPR1_TWLO_SHIFT) & DDRPHY_DTPR1_TWLO_MASK) +#define DDRPHY_DTPR1_TWLO_GET(x) (((uint32_t)(x) & DDRPHY_DTPR1_TWLO_MASK) >> DDRPHY_DTPR1_TWLO_SHIFT) + +/* + * TWLMRD (R/W) + * + * Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge. + */ +#define DDRPHY_DTPR1_TWLMRD_MASK (0x3F00000UL) +#define DDRPHY_DTPR1_TWLMRD_SHIFT (20U) +#define DDRPHY_DTPR1_TWLMRD_SET(x) (((uint32_t)(x) << DDRPHY_DTPR1_TWLMRD_SHIFT) & DDRPHY_DTPR1_TWLMRD_MASK) +#define DDRPHY_DTPR1_TWLMRD_GET(x) (((uint32_t)(x) & DDRPHY_DTPR1_TWLMRD_MASK) >> DDRPHY_DTPR1_TWLMRD_SHIFT) + +/* + * TRFC (R/W) + * + * Refresh-to-Refresh: Indicates the minimum time between two refresh commands or between a refresh and an active command. This is derived from the minimum refresh interval from the datasheet, tRFC(min), divided by the clock cycle time. The default number of clock cycles is for the largest JEDEC tRFC(min parameter value supported. + */ +#define DDRPHY_DTPR1_TRFC_MASK (0xFF800UL) +#define DDRPHY_DTPR1_TRFC_SHIFT (11U) +#define DDRPHY_DTPR1_TRFC_SET(x) (((uint32_t)(x) << DDRPHY_DTPR1_TRFC_SHIFT) & DDRPHY_DTPR1_TRFC_MASK) +#define DDRPHY_DTPR1_TRFC_GET(x) (((uint32_t)(x) & DDRPHY_DTPR1_TRFC_MASK) >> DDRPHY_DTPR1_TRFC_SHIFT) + +/* + * TFAW (R/W) + * + * 4-bank activate period. No more than 4-bank activate commands may be issued in a given tFAW period. Only applies to 8-bank devices. Valid values are 2 to 63. + */ +#define DDRPHY_DTPR1_TFAW_MASK (0x7E0U) +#define DDRPHY_DTPR1_TFAW_SHIFT (5U) +#define DDRPHY_DTPR1_TFAW_SET(x) (((uint32_t)(x) << DDRPHY_DTPR1_TFAW_SHIFT) & DDRPHY_DTPR1_TFAW_MASK) +#define DDRPHY_DTPR1_TFAW_GET(x) (((uint32_t)(x) & DDRPHY_DTPR1_TFAW_MASK) >> DDRPHY_DTPR1_TFAW_SHIFT) + +/* + * TMOD (R/W) + * + * Load mode update delay (DDR3 only). The minimum time between a load mode register command and a non-load mode register command. Valid values are: 000 = 12 + * 001 = 13 + * 010 = 14 + * 011 = 15 + * 100 = 16 + * 101 = 17 + * 110 – 111 = Reserved + */ +#define DDRPHY_DTPR1_TMOD_MASK (0x1CU) +#define DDRPHY_DTPR1_TMOD_SHIFT (2U) +#define DDRPHY_DTPR1_TMOD_SET(x) (((uint32_t)(x) << DDRPHY_DTPR1_TMOD_SHIFT) & DDRPHY_DTPR1_TMOD_MASK) +#define DDRPHY_DTPR1_TMOD_GET(x) (((uint32_t)(x) & DDRPHY_DTPR1_TMOD_MASK) >> DDRPHY_DTPR1_TMOD_SHIFT) + +/* + * TMRD (R/W) + * + * Load mode cycle time: The minimum time between a load mode register command and any other command. For DDR3 this is the minimum time between two load mode register commands. Valid values for DDR2 are 2 to 3. For DDR3, the value used for tMRD is 4 plus the value programmed in these bits, i.e. tMRD value for DDR3 ranges from 4 to 7. + */ +#define DDRPHY_DTPR1_TMRD_MASK (0x3U) +#define DDRPHY_DTPR1_TMRD_SHIFT (0U) +#define DDRPHY_DTPR1_TMRD_SET(x) (((uint32_t)(x) << DDRPHY_DTPR1_TMRD_SHIFT) & DDRPHY_DTPR1_TMRD_MASK) +#define DDRPHY_DTPR1_TMRD_GET(x) (((uint32_t)(x) & DDRPHY_DTPR1_TMRD_MASK) >> DDRPHY_DTPR1_TMRD_SHIFT) + +/* Bitfield definition for register: DTPR2 */ +/* + * TCCD (R/W) + * + * Read to read and write to write command delay. Valid values are: 0 = BL/2 for DDR2 and 4 for DDR3 + * 1 = BL/2 + 1 for DDR2 and 5 for DDR3 + */ +#define DDRPHY_DTPR2_TCCD_MASK (0x80000000UL) +#define DDRPHY_DTPR2_TCCD_SHIFT (31U) +#define DDRPHY_DTPR2_TCCD_SET(x) (((uint32_t)(x) << DDRPHY_DTPR2_TCCD_SHIFT) & DDRPHY_DTPR2_TCCD_MASK) +#define DDRPHY_DTPR2_TCCD_GET(x) (((uint32_t)(x) & DDRPHY_DTPR2_TCCD_MASK) >> DDRPHY_DTPR2_TCCD_SHIFT) + +/* + * TRTW (R/W) + * + * Read to Write command delay. Valid values are: + * 0 = standard bus turn around delay + * 1 = add 1 clock to standard bus turn around delay + * This parameter allows the user to increase the delay between issuing Write commands to the SDRAM when preceded by Read commands. This provides an option to increase bus turn-around margin for high frequency systems. + */ +#define DDRPHY_DTPR2_TRTW_MASK (0x40000000UL) +#define DDRPHY_DTPR2_TRTW_SHIFT (30U) +#define DDRPHY_DTPR2_TRTW_SET(x) (((uint32_t)(x) << DDRPHY_DTPR2_TRTW_SHIFT) & DDRPHY_DTPR2_TRTW_MASK) +#define DDRPHY_DTPR2_TRTW_GET(x) (((uint32_t)(x) & DDRPHY_DTPR2_TRTW_MASK) >> DDRPHY_DTPR2_TRTW_SHIFT) + +/* + * TRTODT (R/W) + * + * Read to ODT delay (DDR3 only). Specifies whether ODT can be enabled immediately after the read post-amble or one clock delay has to be added. Valid values are: + * 0 = ODT may be turned on immediately after read post-amble + * 1 = ODT may not be turned on until one clock after the read post-amble + * If tRTODT is set to 1, then the read-to-write latency is increased by 1 if ODT is enabled. + */ +#define DDRPHY_DTPR2_TRTODT_MASK (0x20000000UL) +#define DDRPHY_DTPR2_TRTODT_SHIFT (29U) +#define DDRPHY_DTPR2_TRTODT_SET(x) (((uint32_t)(x) << DDRPHY_DTPR2_TRTODT_SHIFT) & DDRPHY_DTPR2_TRTODT_MASK) +#define DDRPHY_DTPR2_TRTODT_GET(x) (((uint32_t)(x) & DDRPHY_DTPR2_TRTODT_MASK) >> DDRPHY_DTPR2_TRTODT_SHIFT) + +/* + * TDLLK (R/W) + * + * DLL locking time. Valid values are 2 to 1023. + */ +#define DDRPHY_DTPR2_TDLLK_MASK (0x1FF80000UL) +#define DDRPHY_DTPR2_TDLLK_SHIFT (19U) +#define DDRPHY_DTPR2_TDLLK_SET(x) (((uint32_t)(x) << DDRPHY_DTPR2_TDLLK_SHIFT) & DDRPHY_DTPR2_TDLLK_MASK) +#define DDRPHY_DTPR2_TDLLK_GET(x) (((uint32_t)(x) & DDRPHY_DTPR2_TDLLK_MASK) >> DDRPHY_DTPR2_TDLLK_SHIFT) + +/* + * TCKE (R/W) + * + * CKE minimum pulse width. Also specifies the minimum time that the SDRAM must remain in power down or self refresh mode. For DDR3 this parameter must be set to the value of tCKESR which is usually bigger than the value of tCKE. Valid values are 2 to 15. + */ +#define DDRPHY_DTPR2_TCKE_MASK (0x78000UL) +#define DDRPHY_DTPR2_TCKE_SHIFT (15U) +#define DDRPHY_DTPR2_TCKE_SET(x) (((uint32_t)(x) << DDRPHY_DTPR2_TCKE_SHIFT) & DDRPHY_DTPR2_TCKE_MASK) +#define DDRPHY_DTPR2_TCKE_GET(x) (((uint32_t)(x) & DDRPHY_DTPR2_TCKE_MASK) >> DDRPHY_DTPR2_TCKE_SHIFT) + +/* + * TXP (R/W) + * + * Power down exit delay. The minimum time between a power down exit command and any other command. This parameter must be set to the maximum of the various minimum power down exit delay parameters specified in the SDRAM datasheet, i.e. max(tXP, tXARD, tXARDS) for DDR2 and max(tXP, tXPDLL) for DDR3. Valid values are 2 to 31. + */ +#define DDRPHY_DTPR2_TXP_MASK (0x7C00U) +#define DDRPHY_DTPR2_TXP_SHIFT (10U) +#define DDRPHY_DTPR2_TXP_SET(x) (((uint32_t)(x) << DDRPHY_DTPR2_TXP_SHIFT) & DDRPHY_DTPR2_TXP_MASK) +#define DDRPHY_DTPR2_TXP_GET(x) (((uint32_t)(x) & DDRPHY_DTPR2_TXP_MASK) >> DDRPHY_DTPR2_TXP_SHIFT) + +/* + * TXS (R/W) + * + * Self refresh exit delay. The minimum time between a self refresh exit command and any other command. This parameter must be set to the maximum of the various minimum self refresh exit delay parameters specified in the SDRAM datasheet, i.e. max(tXSNR, tXSRD) for DDR2 and max(tXS, tXSDLL) for DDR3. Valid values are 2 to 1023. + */ +#define DDRPHY_DTPR2_TXS_MASK (0x3FFU) +#define DDRPHY_DTPR2_TXS_SHIFT (0U) +#define DDRPHY_DTPR2_TXS_SET(x) (((uint32_t)(x) << DDRPHY_DTPR2_TXS_SHIFT) & DDRPHY_DTPR2_TXS_MASK) +#define DDRPHY_DTPR2_TXS_GET(x) (((uint32_t)(x) & DDRPHY_DTPR2_TXS_MASK) >> DDRPHY_DTPR2_TXS_SHIFT) + +/* Bitfield definition for register: MR0 */ +/* + * PD (R/W) + * + * Power-Down Control: Controls the exit time for power-down modes. Refer to the SDRAM datasheet for details on power-down modes. Valid values are: + * 0 = Slow exit (DLL off) 1 = Fast exit (DLL on) + */ +#define DDRPHY_MR0_PD_MASK (0x1000U) +#define DDRPHY_MR0_PD_SHIFT (12U) +#define DDRPHY_MR0_PD_SET(x) (((uint32_t)(x) << DDRPHY_MR0_PD_SHIFT) & DDRPHY_MR0_PD_MASK) +#define DDRPHY_MR0_PD_GET(x) (((uint32_t)(x) & DDRPHY_MR0_PD_MASK) >> DDRPHY_MR0_PD_SHIFT) + +/* + * WR (R/W) + * + * Write Recovery: This is the value of the write recovery. It is calculated by dividing the datasheet write recovery time, tWR (ns) by the datasheet clock cycle time, tCK (ns) and rounding up a non-integer value to the next integer. Valid values are: + * 000 = 16 + * 001 = 5 + * 010 = 6 + * 011 = 7 + * 100 = 8 + * 101 = 10 + * 110 = 12 + * 111 = 14 + * All other settings are reserved and should not be used. + * NOTE: tWR (ns) is the time from the first SDRAM positive clock edge after the last data-in pair of a write command, to when a precharge of the same bank can be issued. + */ +#define DDRPHY_MR0_WR_MASK (0xE00U) +#define DDRPHY_MR0_WR_SHIFT (9U) +#define DDRPHY_MR0_WR_SET(x) (((uint32_t)(x) << DDRPHY_MR0_WR_SHIFT) & DDRPHY_MR0_WR_MASK) +#define DDRPHY_MR0_WR_GET(x) (((uint32_t)(x) & DDRPHY_MR0_WR_MASK) >> DDRPHY_MR0_WR_SHIFT) + +/* + * DR (R/W) + * + * DLL Reset: Writing a ‘1’ to this bit will reset the SDRAM DLL. This bit is self- clearing, i.e. it returns back to ‘0’ after the DLL reset has been issued. + */ +#define DDRPHY_MR0_DR_MASK (0x100U) +#define DDRPHY_MR0_DR_SHIFT (8U) +#define DDRPHY_MR0_DR_SET(x) (((uint32_t)(x) << DDRPHY_MR0_DR_SHIFT) & DDRPHY_MR0_DR_MASK) +#define DDRPHY_MR0_DR_GET(x) (((uint32_t)(x) & DDRPHY_MR0_DR_MASK) >> DDRPHY_MR0_DR_SHIFT) + +/* + * TM (R/W) + * + * Operating Mode: Selects either normal operating mode (0) or test mode (1). Test mode is reserved for the manufacturer and should not be used. + */ +#define DDRPHY_MR0_TM_MASK (0x80U) +#define DDRPHY_MR0_TM_SHIFT (7U) +#define DDRPHY_MR0_TM_SET(x) (((uint32_t)(x) << DDRPHY_MR0_TM_SHIFT) & DDRPHY_MR0_TM_MASK) +#define DDRPHY_MR0_TM_GET(x) (((uint32_t)(x) & DDRPHY_MR0_TM_MASK) >> DDRPHY_MR0_TM_SHIFT) + +/* + * CLH (R/W) + * + * CAS Latency: The delay between when the SDRAM registers a read command to when data is available. Valid values are: + * 0010 = 5 + * 0100 = 6 + * 0110 = 7 + * 1000 = 8 + * 1010 = 9 + * 1100 = 10 + * 1110 = 11 + * 0001 = 12 + * 0011 = 13 + * 0101 = 14 + * All other settings are reserved and should not be used. + */ +#define DDRPHY_MR0_CLH_MASK (0x70U) +#define DDRPHY_MR0_CLH_SHIFT (4U) +#define DDRPHY_MR0_CLH_SET(x) (((uint32_t)(x) << DDRPHY_MR0_CLH_SHIFT) & DDRPHY_MR0_CLH_MASK) +#define DDRPHY_MR0_CLH_GET(x) (((uint32_t)(x) & DDRPHY_MR0_CLH_MASK) >> DDRPHY_MR0_CLH_SHIFT) + +/* + * BT (R/W) + * + * Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). + */ +#define DDRPHY_MR0_BT_MASK (0x8U) +#define DDRPHY_MR0_BT_SHIFT (3U) +#define DDRPHY_MR0_BT_SET(x) (((uint32_t)(x) << DDRPHY_MR0_BT_SHIFT) & DDRPHY_MR0_BT_MASK) +#define DDRPHY_MR0_BT_GET(x) (((uint32_t)(x) & DDRPHY_MR0_BT_MASK) >> DDRPHY_MR0_BT_SHIFT) + +/* + * CLL (R/W) + * + * CAS Latency low bit + */ +#define DDRPHY_MR0_CLL_MASK (0x4U) +#define DDRPHY_MR0_CLL_SHIFT (2U) +#define DDRPHY_MR0_CLL_SET(x) (((uint32_t)(x) << DDRPHY_MR0_CLL_SHIFT) & DDRPHY_MR0_CLL_MASK) +#define DDRPHY_MR0_CLL_GET(x) (((uint32_t)(x) & DDRPHY_MR0_CLL_MASK) >> DDRPHY_MR0_CLL_SHIFT) + +/* + * BL (R/W) + * + * Burst Length: Determines the maximum number of column locations that can be accessed during a given read or write command. Valid values are: + * Valid values for DDR3 are: 00 = 8 (Fixed) + * 01 = 4 or 8 (On the fly) + * 10 = 4 (Fixed) + * 11 = Reserved + */ +#define DDRPHY_MR0_BL_MASK (0x3U) +#define DDRPHY_MR0_BL_SHIFT (0U) +#define DDRPHY_MR0_BL_SET(x) (((uint32_t)(x) << DDRPHY_MR0_BL_SHIFT) & DDRPHY_MR0_BL_MASK) +#define DDRPHY_MR0_BL_GET(x) (((uint32_t)(x) & DDRPHY_MR0_BL_MASK) >> DDRPHY_MR0_BL_SHIFT) + +/* Bitfield definition for register: MR */ +/* + * PD (R/W) + * + * Power-Down Control: Controls the exit time for power-down modes. Refer to the SDRAM datasheet for details on power-down modes. Valid values are: + * 0 = Fast exit 1 = Slow exit + */ +#define DDRPHY_MR_PD_MASK (0x1000U) +#define DDRPHY_MR_PD_SHIFT (12U) +#define DDRPHY_MR_PD_SET(x) (((uint32_t)(x) << DDRPHY_MR_PD_SHIFT) & DDRPHY_MR_PD_MASK) +#define DDRPHY_MR_PD_GET(x) (((uint32_t)(x) & DDRPHY_MR_PD_MASK) >> DDRPHY_MR_PD_SHIFT) + +/* + * WR (R/W) + * + * Write Recovery: This is the value of the write recovery. It is calculated by dividing the datasheet write recovery time, tWR (ns) by the datasheet clock cycle time, tCK (ns) and rounding up a non-integer value to the next integer. Valid values are: + * 001 = 2 + * 010 = 3 + * 011 = 4 + * 100 = 5 + * 101 = 6 + * All other settings are reserved and should not be used. + * NOTE: tWR (ns) is the time from the first SDRAM positive clock edge after the last data-in pair of a write command, to when a precharge of the same bank can be issued. + */ +#define DDRPHY_MR_WR_MASK (0xE00U) +#define DDRPHY_MR_WR_SHIFT (9U) +#define DDRPHY_MR_WR_SET(x) (((uint32_t)(x) << DDRPHY_MR_WR_SHIFT) & DDRPHY_MR_WR_MASK) +#define DDRPHY_MR_WR_GET(x) (((uint32_t)(x) & DDRPHY_MR_WR_MASK) >> DDRPHY_MR_WR_SHIFT) + +/* + * DR (R/W) + * + * DLL Reset: Writing a ‘1’ to this bit will reset the SDRAM DLL. This bit is self- clearing, i.e. it returns back to ‘0’ after the DLL reset has been issued. + */ +#define DDRPHY_MR_DR_MASK (0x100U) +#define DDRPHY_MR_DR_SHIFT (8U) +#define DDRPHY_MR_DR_SET(x) (((uint32_t)(x) << DDRPHY_MR_DR_SHIFT) & DDRPHY_MR_DR_MASK) +#define DDRPHY_MR_DR_GET(x) (((uint32_t)(x) & DDRPHY_MR_DR_MASK) >> DDRPHY_MR_DR_SHIFT) + +/* + * TM (R/W) + * + * Operating Mode: Selects either normal operating mode (0) or test mode (1). Test mode is reserved for the manufacturer and should not be used. + */ +#define DDRPHY_MR_TM_MASK (0x80U) +#define DDRPHY_MR_TM_SHIFT (7U) +#define DDRPHY_MR_TM_SET(x) (((uint32_t)(x) << DDRPHY_MR_TM_SHIFT) & DDRPHY_MR_TM_MASK) +#define DDRPHY_MR_TM_GET(x) (((uint32_t)(x) & DDRPHY_MR_TM_MASK) >> DDRPHY_MR_TM_SHIFT) + +/* + * CL (R/W) + * + * CAS Latency: The delay between when the SDRAM registers a read command to when data is available. Valid values are: + * 010 = 2 + * 011 = 3 + * 100 = 4 + * 101 = 5 + * 110 = 6 + * 111 = 7 + * All other settings are reserved and should not be used. + */ +#define DDRPHY_MR_CL_MASK (0x70U) +#define DDRPHY_MR_CL_SHIFT (4U) +#define DDRPHY_MR_CL_SET(x) (((uint32_t)(x) << DDRPHY_MR_CL_SHIFT) & DDRPHY_MR_CL_MASK) +#define DDRPHY_MR_CL_GET(x) (((uint32_t)(x) & DDRPHY_MR_CL_MASK) >> DDRPHY_MR_CL_SHIFT) + +/* + * BT (R/W) + * + * Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). + */ +#define DDRPHY_MR_BT_MASK (0x8U) +#define DDRPHY_MR_BT_SHIFT (3U) +#define DDRPHY_MR_BT_SET(x) (((uint32_t)(x) << DDRPHY_MR_BT_SHIFT) & DDRPHY_MR_BT_MASK) +#define DDRPHY_MR_BT_GET(x) (((uint32_t)(x) & DDRPHY_MR_BT_MASK) >> DDRPHY_MR_BT_SHIFT) + +/* + * BL (R/W) + * + * Burst Length: Determines the maximum number of column locations that can be accessed during a given read or write command. Valid values are: + * 010 = 4 + * 011 = 8 + * All other settings are reserved and should not be used. + */ +#define DDRPHY_MR_BL_MASK (0x7U) +#define DDRPHY_MR_BL_SHIFT (0U) +#define DDRPHY_MR_BL_SET(x) (((uint32_t)(x) << DDRPHY_MR_BL_SHIFT) & DDRPHY_MR_BL_MASK) +#define DDRPHY_MR_BL_GET(x) (((uint32_t)(x) & DDRPHY_MR_BL_MASK) >> DDRPHY_MR_BL_SHIFT) + +/* Bitfield definition for register: MR1 */ +/* + * QOFF (R/W) + * + * Output Enable/Disable: When ‘0’, all outputs function normal; when ‘1’ all SDRAM outputs are disabled removing output buffer current. This feature is intended to be used for IDD characterization of read current and should not be used in normal operation. + */ +#define DDRPHY_MR1_QOFF_MASK (0x1000U) +#define DDRPHY_MR1_QOFF_SHIFT (12U) +#define DDRPHY_MR1_QOFF_SET(x) (((uint32_t)(x) << DDRPHY_MR1_QOFF_SHIFT) & DDRPHY_MR1_QOFF_MASK) +#define DDRPHY_MR1_QOFF_GET(x) (((uint32_t)(x) & DDRPHY_MR1_QOFF_MASK) >> DDRPHY_MR1_QOFF_SHIFT) + +/* + * TDQS (R/W) + * + * Termination Data Strobe: When enabled (‘1’) TDQS provides additional termination resistance outputs that may be useful in some system configurations. Refer to the SDRAM datasheet for details. + */ +#define DDRPHY_MR1_TDQS_MASK (0x800U) +#define DDRPHY_MR1_TDQS_SHIFT (11U) +#define DDRPHY_MR1_TDQS_SET(x) (((uint32_t)(x) << DDRPHY_MR1_TDQS_SHIFT) & DDRPHY_MR1_TDQS_MASK) +#define DDRPHY_MR1_TDQS_GET(x) (((uint32_t)(x) & DDRPHY_MR1_TDQS_MASK) >> DDRPHY_MR1_TDQS_SHIFT) + +/* + * RTTH (R/W) + * + * On Die Termination high bit + */ +#define DDRPHY_MR1_RTTH_MASK (0x200U) +#define DDRPHY_MR1_RTTH_SHIFT (9U) +#define DDRPHY_MR1_RTTH_SET(x) (((uint32_t)(x) << DDRPHY_MR1_RTTH_SHIFT) & DDRPHY_MR1_RTTH_MASK) +#define DDRPHY_MR1_RTTH_GET(x) (((uint32_t)(x) & DDRPHY_MR1_RTTH_MASK) >> DDRPHY_MR1_RTTH_SHIFT) + +/* + * LEVEL (R/W) + * + * Write Leveling Enable: Enables write-leveling when set. + */ +#define DDRPHY_MR1_LEVEL_MASK (0x80U) +#define DDRPHY_MR1_LEVEL_SHIFT (7U) +#define DDRPHY_MR1_LEVEL_SET(x) (((uint32_t)(x) << DDRPHY_MR1_LEVEL_SHIFT) & DDRPHY_MR1_LEVEL_MASK) +#define DDRPHY_MR1_LEVEL_GET(x) (((uint32_t)(x) & DDRPHY_MR1_LEVEL_MASK) >> DDRPHY_MR1_LEVEL_SHIFT) + +/* + * RTTM (R/W) + * + * On Die Termination mid bit: + * Selects the effective resistance for SDRAM on die termination. Valid values are: + * 000 = ODT disabled 001 = RZQ/4 + * 010 = RZQ/2 + * 011 = RZQ/6 + * 100 = RZQ/12 + * 101 = RZQ/8 + * All other settings are reserved and should not be used. + * Bit on [9, 6,2] + */ +#define DDRPHY_MR1_RTTM_MASK (0x40U) +#define DDRPHY_MR1_RTTM_SHIFT (6U) +#define DDRPHY_MR1_RTTM_SET(x) (((uint32_t)(x) << DDRPHY_MR1_RTTM_SHIFT) & DDRPHY_MR1_RTTM_MASK) +#define DDRPHY_MR1_RTTM_GET(x) (((uint32_t)(x) & DDRPHY_MR1_RTTM_MASK) >> DDRPHY_MR1_RTTM_SHIFT) + +/* + * DICH (R/W) + * + * Output Driver Impedance Control high bit: + * Controls the output drive strength. Valid values are: + * 00 = RZQ/6 + * 01 = RZQ7 + * 10 = Reserved + * 11 = Reserved + */ +#define DDRPHY_MR1_DICH_MASK (0x20U) +#define DDRPHY_MR1_DICH_SHIFT (5U) +#define DDRPHY_MR1_DICH_SET(x) (((uint32_t)(x) << DDRPHY_MR1_DICH_SHIFT) & DDRPHY_MR1_DICH_MASK) +#define DDRPHY_MR1_DICH_GET(x) (((uint32_t)(x) & DDRPHY_MR1_DICH_MASK) >> DDRPHY_MR1_DICH_SHIFT) + +/* + * AL (R/W) + * + * Posted CAS Additive Latency: Setting additive latency that allows read and write commands to be issued to the SDRAM earlier than normal (refer to the SDRAM datasheet for details). Valid values are: + * 00 = 0 (AL disabled) + * 01 = CL - 1 + * 10 = CL - 2 + * 11 = Reserved + */ +#define DDRPHY_MR1_AL_MASK (0x18U) +#define DDRPHY_MR1_AL_SHIFT (3U) +#define DDRPHY_MR1_AL_SET(x) (((uint32_t)(x) << DDRPHY_MR1_AL_SHIFT) & DDRPHY_MR1_AL_MASK) +#define DDRPHY_MR1_AL_GET(x) (((uint32_t)(x) & DDRPHY_MR1_AL_MASK) >> DDRPHY_MR1_AL_SHIFT) + +/* + * RTTL (R/W) + * + * On Die Termination low bit + */ +#define DDRPHY_MR1_RTTL_MASK (0x4U) +#define DDRPHY_MR1_RTTL_SHIFT (2U) +#define DDRPHY_MR1_RTTL_SET(x) (((uint32_t)(x) << DDRPHY_MR1_RTTL_SHIFT) & DDRPHY_MR1_RTTL_MASK) +#define DDRPHY_MR1_RTTL_GET(x) (((uint32_t)(x) & DDRPHY_MR1_RTTL_MASK) >> DDRPHY_MR1_RTTL_SHIFT) + +/* + * DICL (R/W) + * + * Output Driver Impedance Control low bit + */ +#define DDRPHY_MR1_DICL_MASK (0x2U) +#define DDRPHY_MR1_DICL_SHIFT (1U) +#define DDRPHY_MR1_DICL_SET(x) (((uint32_t)(x) << DDRPHY_MR1_DICL_SHIFT) & DDRPHY_MR1_DICL_MASK) +#define DDRPHY_MR1_DICL_GET(x) (((uint32_t)(x) & DDRPHY_MR1_DICL_MASK) >> DDRPHY_MR1_DICL_SHIFT) + +/* + * DE (R/W) + * + * DLL Enable/Disable: Enable (0) or disable (1) the DLL. DLL must be enabled for normal operation. + * Note: SDRAM DLL off mode is not supported + */ +#define DDRPHY_MR1_DE_MASK (0x1U) +#define DDRPHY_MR1_DE_SHIFT (0U) +#define DDRPHY_MR1_DE_SET(x) (((uint32_t)(x) << DDRPHY_MR1_DE_SHIFT) & DDRPHY_MR1_DE_MASK) +#define DDRPHY_MR1_DE_GET(x) (((uint32_t)(x) & DDRPHY_MR1_DE_MASK) >> DDRPHY_MR1_DE_SHIFT) + +/* Bitfield definition for register: EMR */ +/* + * QOFF (R/W) + * + * Output Enable/Disable: When ‘0’, all outputs function normal; when ‘1’ all SDRAM outputs are disabled removing output buffer current. This feature is intended to be + * used for IDD characterization of read current and should not be used in normal operation. + */ +#define DDRPHY_EMR_QOFF_MASK (0x1000U) +#define DDRPHY_EMR_QOFF_SHIFT (12U) +#define DDRPHY_EMR_QOFF_SET(x) (((uint32_t)(x) << DDRPHY_EMR_QOFF_SHIFT) & DDRPHY_EMR_QOFF_MASK) +#define DDRPHY_EMR_QOFF_GET(x) (((uint32_t)(x) & DDRPHY_EMR_QOFF_MASK) >> DDRPHY_EMR_QOFF_SHIFT) + +/* + * RDQS (R/W) + * + * RDQS Enable/Disable: When enabled (‘1’), RDQS is identical in function and timing to data strobe DQS during a read, and ignored during a write. A ‘0’ disables the SDRAM from driving RDQS. The Controller does not allow the user to change this bit. + */ +#define DDRPHY_EMR_RDQS_MASK (0x800U) +#define DDRPHY_EMR_RDQS_SHIFT (11U) +#define DDRPHY_EMR_RDQS_SET(x) (((uint32_t)(x) << DDRPHY_EMR_RDQS_SHIFT) & DDRPHY_EMR_RDQS_MASK) +#define DDRPHY_EMR_RDQS_GET(x) (((uint32_t)(x) & DDRPHY_EMR_RDQS_MASK) >> DDRPHY_EMR_RDQS_SHIFT) + +/* + * DQS (R/W) + * + * DQS_b Enable/Disable: When ‘0’, DQS_b is the complement of the differential data strobe pair DQS/DQS_b. When ‘1’, DQS is used in a single-ended mode and the DQS_b pin is disabled. Also used to similarly enable/disable RDQS_b if RDQS is enabled. The Controller does not allow the user to change this bit. + */ +#define DDRPHY_EMR_DQS_MASK (0x400U) +#define DDRPHY_EMR_DQS_SHIFT (10U) +#define DDRPHY_EMR_DQS_SET(x) (((uint32_t)(x) << DDRPHY_EMR_DQS_SHIFT) & DDRPHY_EMR_DQS_MASK) +#define DDRPHY_EMR_DQS_GET(x) (((uint32_t)(x) & DDRPHY_EMR_DQS_MASK) >> DDRPHY_EMR_DQS_SHIFT) + +/* + * OCD (R/W) + * + * Off-Chip Driver (OCD) Impedance Calibration: Used to calibrate and match pull-up to pull- down impedance to 18  nominal (refer to the SDRAM datasheet for details). Valid values are: + * 000 = OCD calibration mode exit 001 = Drive (1) pull-up + * 010 = Drive (0) pull-down + * 100 = OCD enter adjust mode 111 = OCD calibration default + * All other settings are reserved and should not be used. Note that OCD is not supported by all vendors. Refer to the SDRAM datasheet for details on the recommended OCD settings. + */ +#define DDRPHY_EMR_OCD_MASK (0x380U) +#define DDRPHY_EMR_OCD_SHIFT (7U) +#define DDRPHY_EMR_OCD_SET(x) (((uint32_t)(x) << DDRPHY_EMR_OCD_SHIFT) & DDRPHY_EMR_OCD_MASK) +#define DDRPHY_EMR_OCD_GET(x) (((uint32_t)(x) & DDRPHY_EMR_OCD_MASK) >> DDRPHY_EMR_OCD_SHIFT) + +/* + * RTTH (R/W) + * + * On Die Termination high bit: + * Selects the effective resistance for SDRAM on die termination. Valid values are: + * 00 = ODT disabled 01 = 75 + * 10 = 150 + * 11 = 50 (some vendors) + */ +#define DDRPHY_EMR_RTTH_MASK (0x40U) +#define DDRPHY_EMR_RTTH_SHIFT (6U) +#define DDRPHY_EMR_RTTH_SET(x) (((uint32_t)(x) << DDRPHY_EMR_RTTH_SHIFT) & DDRPHY_EMR_RTTH_MASK) +#define DDRPHY_EMR_RTTH_GET(x) (((uint32_t)(x) & DDRPHY_EMR_RTTH_MASK) >> DDRPHY_EMR_RTTH_SHIFT) + +/* + * AL (R/W) + * + * Posted CAS Additive Latency: Setting additive latency that allows read and write commands to be issued to the SDRAM earlier than normal (refer to the SDRAM datasheet for details). Valid values are: + * 000 = 0 + * 001 = 1 + * 010 = 2 + * 011 = 3 + * 100 = 4 + * 101 = 5 + * All other settings are reserved and should not be used. The maximum allowed value of AL is tRCD-1. + */ +#define DDRPHY_EMR_AL_MASK (0x38U) +#define DDRPHY_EMR_AL_SHIFT (3U) +#define DDRPHY_EMR_AL_SET(x) (((uint32_t)(x) << DDRPHY_EMR_AL_SHIFT) & DDRPHY_EMR_AL_MASK) +#define DDRPHY_EMR_AL_GET(x) (((uint32_t)(x) & DDRPHY_EMR_AL_MASK) >> DDRPHY_EMR_AL_SHIFT) + +/* + * RTTL (R/W) + * + * On Die Termination low bit: + */ +#define DDRPHY_EMR_RTTL_MASK (0x4U) +#define DDRPHY_EMR_RTTL_SHIFT (2U) +#define DDRPHY_EMR_RTTL_SET(x) (((uint32_t)(x) << DDRPHY_EMR_RTTL_SHIFT) & DDRPHY_EMR_RTTL_MASK) +#define DDRPHY_EMR_RTTL_GET(x) (((uint32_t)(x) & DDRPHY_EMR_RTTL_MASK) >> DDRPHY_EMR_RTTL_SHIFT) + +/* + * DIC (R/W) + * + * Output Driver Impedance Control: Controls the output drive strength. Valid values are: + * 0 = Full strength + * 1 = Reduced strength + */ +#define DDRPHY_EMR_DIC_MASK (0x2U) +#define DDRPHY_EMR_DIC_SHIFT (1U) +#define DDRPHY_EMR_DIC_SET(x) (((uint32_t)(x) << DDRPHY_EMR_DIC_SHIFT) & DDRPHY_EMR_DIC_MASK) +#define DDRPHY_EMR_DIC_GET(x) (((uint32_t)(x) & DDRPHY_EMR_DIC_MASK) >> DDRPHY_EMR_DIC_SHIFT) + +/* + * DE (R/W) + * + * DLL Enable/Disable: Enable (0) or disable (1) the DLL. DLL must be enabled for normal operation. + */ +#define DDRPHY_EMR_DE_MASK (0x1U) +#define DDRPHY_EMR_DE_SHIFT (0U) +#define DDRPHY_EMR_DE_SET(x) (((uint32_t)(x) << DDRPHY_EMR_DE_SHIFT) & DDRPHY_EMR_DE_MASK) +#define DDRPHY_EMR_DE_GET(x) (((uint32_t)(x) & DDRPHY_EMR_DE_MASK) >> DDRPHY_EMR_DE_SHIFT) + +/* Bitfield definition for register: MR2 */ +/* + * RTTWR (R/W) + * + * Dynamic ODT: Selects RTT for dynamic ODT. Valid values are: 00 = Dynamic ODT off + * 01 = RZQ/4 + * 10 = RZQ/2 + * 11 = Reserved + */ +#define DDRPHY_MR2_RTTWR_MASK (0x600U) +#define DDRPHY_MR2_RTTWR_SHIFT (9U) +#define DDRPHY_MR2_RTTWR_SET(x) (((uint32_t)(x) << DDRPHY_MR2_RTTWR_SHIFT) & DDRPHY_MR2_RTTWR_MASK) +#define DDRPHY_MR2_RTTWR_GET(x) (((uint32_t)(x) & DDRPHY_MR2_RTTWR_MASK) >> DDRPHY_MR2_RTTWR_SHIFT) + +/* + * SRT (R/W) + * + * Self-Refresh Temperature Range: Selects either normal (‘0’) or extended (‘1’) operating temperature range during self-refresh. + */ +#define DDRPHY_MR2_SRT_MASK (0x80U) +#define DDRPHY_MR2_SRT_SHIFT (7U) +#define DDRPHY_MR2_SRT_SET(x) (((uint32_t)(x) << DDRPHY_MR2_SRT_SHIFT) & DDRPHY_MR2_SRT_MASK) +#define DDRPHY_MR2_SRT_GET(x) (((uint32_t)(x) & DDRPHY_MR2_SRT_MASK) >> DDRPHY_MR2_SRT_SHIFT) + +/* + * ASR (R/W) + * + * Auto Self-Refresh: When enabled (‘1’), SDRAM automatically provides self-refresh power management functions for all supported operating temperature values. + * Otherwise the SRT bit must be programmed to indicate the temperature range. + */ +#define DDRPHY_MR2_ASR_MASK (0x40U) +#define DDRPHY_MR2_ASR_SHIFT (6U) +#define DDRPHY_MR2_ASR_SET(x) (((uint32_t)(x) << DDRPHY_MR2_ASR_SHIFT) & DDRPHY_MR2_ASR_MASK) +#define DDRPHY_MR2_ASR_GET(x) (((uint32_t)(x) & DDRPHY_MR2_ASR_MASK) >> DDRPHY_MR2_ASR_SHIFT) + +/* + * CWL (R/W) + * + * CAS Write Latency: The delay between when the SDRAM registers a write command to when write data is available. Valid values are: + * 000 = 5 (tCK > 2.5ns) + * 001 = 6 (2.5ns > tCK > 1.875ns) + * 010 = 7 (1.875ns > tCK> 1.5ns) + * 011 = 8 (1.5ns > tCK > 1.25ns) + * 100 = 9 (1.25ns > tCK > 1.07ns) + * 101 = 10 (1.07ns > tCK > 0.935ns) + * 110 = 11 (0.935ns > tCK > 0.833ns) + * 111 = 12 (0.833ns > tCK > 0.75ns) + * All other settings are reserved and should not be used. + */ +#define DDRPHY_MR2_CWL_MASK (0x38U) +#define DDRPHY_MR2_CWL_SHIFT (3U) +#define DDRPHY_MR2_CWL_SET(x) (((uint32_t)(x) << DDRPHY_MR2_CWL_SHIFT) & DDRPHY_MR2_CWL_MASK) +#define DDRPHY_MR2_CWL_GET(x) (((uint32_t)(x) & DDRPHY_MR2_CWL_MASK) >> DDRPHY_MR2_CWL_SHIFT) + +/* + * PASR (R/W) + * + * Partial Array Self Refresh: Specifies that data located in areas of the array beyond the specified location will be lost if self refresh is entered. + * Valid settings for 4 banks are: + * 000 = Full Array + * 001 = Half Array (BA[1:0] = 00 & 01) + * 010 = Quarter Array (BA[1:0] = 00) 011 = Not defined + * 100 = 3/4 Array (BA[1:0] = 01, 10, & 11) + * 101 = Half Array (BA[1:0] = 10 & 11) + * 110 = Quarter Array (BA[1:0] = 11) 111 = Not defined + * Valid settings for 8 banks are: + * 000 = Full Array + * 001 = Half Array (BA[2:0] = 000, 001, 010 & 011) + * 010 = Quarter Array (BA[2:0] = 000, 001) 011 = 1/8 Array (BA[2:0] = 000) + * 100 = 3/4 Array (BA[2:0] = 010, 011, 100, 101, 110 & 111) + * 101 = Half Array (BA[2:0] = 100, 101, 110 & 111) + * 110 = Quarter Array (BA[2:0] = 110 & 111) + * 111 = 1/8 Array (BA[2:0] 111) + */ +#define DDRPHY_MR2_PASR_MASK (0x7U) +#define DDRPHY_MR2_PASR_SHIFT (0U) +#define DDRPHY_MR2_PASR_SET(x) (((uint32_t)(x) << DDRPHY_MR2_PASR_SHIFT) & DDRPHY_MR2_PASR_MASK) +#define DDRPHY_MR2_PASR_GET(x) (((uint32_t)(x) & DDRPHY_MR2_PASR_MASK) >> DDRPHY_MR2_PASR_SHIFT) + +/* Bitfield definition for register: EMR2 */ +/* + * SRF (R/W) + * + * Self Refresh Rate: Enables, if set, high temperature self refresh rate. + */ +#define DDRPHY_EMR2_SRF_MASK (0x80U) +#define DDRPHY_EMR2_SRF_SHIFT (7U) +#define DDRPHY_EMR2_SRF_SET(x) (((uint32_t)(x) << DDRPHY_EMR2_SRF_SHIFT) & DDRPHY_EMR2_SRF_MASK) +#define DDRPHY_EMR2_SRF_GET(x) (((uint32_t)(x) & DDRPHY_EMR2_SRF_MASK) >> DDRPHY_EMR2_SRF_SHIFT) + +/* + * DCC (R/W) + * + * Duty Cycle Corrector: Enables, if set, duty cycle correction within SDRAM. + */ +#define DDRPHY_EMR2_DCC_MASK (0x8U) +#define DDRPHY_EMR2_DCC_SHIFT (3U) +#define DDRPHY_EMR2_DCC_SET(x) (((uint32_t)(x) << DDRPHY_EMR2_DCC_SHIFT) & DDRPHY_EMR2_DCC_MASK) +#define DDRPHY_EMR2_DCC_GET(x) (((uint32_t)(x) & DDRPHY_EMR2_DCC_MASK) >> DDRPHY_EMR2_DCC_SHIFT) + +/* + * PASR (R/W) + * + * Partial Array Self Refresh: Specifies that data located in areas of the array beyond the specified location will be lost if self refresh is entered. + * Valid settings for 4 banks are: + * 000 = Full Array + * 001 = Half Array (BA[1:0] = 00 & 01) + * 010 = Quarter Array (BA[1:0] = 00) 011 = Not defined + * 100 = 3/4 Array (BA[1:0] = 01, 10, & 11) + * 101 = Half Array (BA[1:0] = 10 & 11) + * 110 = Quarter Array (BA[1:0] = 11) 111 = Not defined + * Valid settings for 8 banks are: + * 000 = Full Array + * 001 = Half Array (BA[2:0] = 000, 001, 010 & 011) + * 010 = Quarter Array (BA[2:0] = 000, 001) 011 = 1/8 Array (BA[2:0] = 000) + * 100 = 3/4 Array (BA[2:0] = 010, 011, 100, 101, 110 & 111) + * 101 = Half Array (BA[2:0] = 100, 101, 110 & 111) + * 110 = Quarter Array (BA[2:0] = 110 & 111) + * 111 = 1/8 Array (BA[2:0] 111) + */ +#define DDRPHY_EMR2_PASR_MASK (0x7U) +#define DDRPHY_EMR2_PASR_SHIFT (0U) +#define DDRPHY_EMR2_PASR_SET(x) (((uint32_t)(x) << DDRPHY_EMR2_PASR_SHIFT) & DDRPHY_EMR2_PASR_MASK) +#define DDRPHY_EMR2_PASR_GET(x) (((uint32_t)(x) & DDRPHY_EMR2_PASR_MASK) >> DDRPHY_EMR2_PASR_SHIFT) + +/* Bitfield definition for register: MR3 */ +/* + * MPR (R/W) + * + * Multi-Purpose Register Enable: Enables, if set, that read data should come from the Multi-Purpose Register. Otherwise read data come from the DRAM array. + */ +#define DDRPHY_MR3_MPR_MASK (0x4U) +#define DDRPHY_MR3_MPR_SHIFT (2U) +#define DDRPHY_MR3_MPR_SET(x) (((uint32_t)(x) << DDRPHY_MR3_MPR_SHIFT) & DDRPHY_MR3_MPR_MASK) +#define DDRPHY_MR3_MPR_GET(x) (((uint32_t)(x) & DDRPHY_MR3_MPR_MASK) >> DDRPHY_MR3_MPR_SHIFT) + +/* + * MPRLOC (R/W) + * + * Multi-Purpose Register (MPR) Location: Selects MPR data location: Valid value are: 00 = Predefined pattern for system calibration + * All other settings are reserved and should not be used. + */ +#define DDRPHY_MR3_MPRLOC_MASK (0x3U) +#define DDRPHY_MR3_MPRLOC_SHIFT (0U) +#define DDRPHY_MR3_MPRLOC_SET(x) (((uint32_t)(x) << DDRPHY_MR3_MPRLOC_SHIFT) & DDRPHY_MR3_MPRLOC_MASK) +#define DDRPHY_MR3_MPRLOC_GET(x) (((uint32_t)(x) & DDRPHY_MR3_MPRLOC_MASK) >> DDRPHY_MR3_MPRLOC_SHIFT) + +/* Bitfield definition for register: EMR3 */ +/* Bitfield definition for register: ODTCR */ +/* + * WRODT3 (R/W) + * + */ +#define DDRPHY_ODTCR_WRODT3_MASK (0xF0000000UL) +#define DDRPHY_ODTCR_WRODT3_SHIFT (28U) +#define DDRPHY_ODTCR_WRODT3_SET(x) (((uint32_t)(x) << DDRPHY_ODTCR_WRODT3_SHIFT) & DDRPHY_ODTCR_WRODT3_MASK) +#define DDRPHY_ODTCR_WRODT3_GET(x) (((uint32_t)(x) & DDRPHY_ODTCR_WRODT3_MASK) >> DDRPHY_ODTCR_WRODT3_SHIFT) + +/* + * WRODT2 (R/W) + * + */ +#define DDRPHY_ODTCR_WRODT2_MASK (0xF000000UL) +#define DDRPHY_ODTCR_WRODT2_SHIFT (24U) +#define DDRPHY_ODTCR_WRODT2_SET(x) (((uint32_t)(x) << DDRPHY_ODTCR_WRODT2_SHIFT) & DDRPHY_ODTCR_WRODT2_MASK) +#define DDRPHY_ODTCR_WRODT2_GET(x) (((uint32_t)(x) & DDRPHY_ODTCR_WRODT2_MASK) >> DDRPHY_ODTCR_WRODT2_SHIFT) + +/* + * WRODT1 (R/W) + * + */ +#define DDRPHY_ODTCR_WRODT1_MASK (0xF00000UL) +#define DDRPHY_ODTCR_WRODT1_SHIFT (20U) +#define DDRPHY_ODTCR_WRODT1_SET(x) (((uint32_t)(x) << DDRPHY_ODTCR_WRODT1_SHIFT) & DDRPHY_ODTCR_WRODT1_MASK) +#define DDRPHY_ODTCR_WRODT1_GET(x) (((uint32_t)(x) & DDRPHY_ODTCR_WRODT1_MASK) >> DDRPHY_ODTCR_WRODT1_SHIFT) + +/* + * WRODT0 (R/W) + * + * Write ODT: Specifies whether ODT should be enabled (‘1’) or disabled (‘0’) on each of the up to four ranks when a write command is sent to rank n. WRODT0, WRODT1, WRODT2, and WRODT3 specify ODT settings when a write is to rank 0, rank 1, rank 2, and rank 3, respectively. The four bits of each field each represent a rank, the LSB being rank 0 and the MSB being rank 3. Default is to enable ODT only on rank being written to. + */ +#define DDRPHY_ODTCR_WRODT0_MASK (0xF0000UL) +#define DDRPHY_ODTCR_WRODT0_SHIFT (16U) +#define DDRPHY_ODTCR_WRODT0_SET(x) (((uint32_t)(x) << DDRPHY_ODTCR_WRODT0_SHIFT) & DDRPHY_ODTCR_WRODT0_MASK) +#define DDRPHY_ODTCR_WRODT0_GET(x) (((uint32_t)(x) & DDRPHY_ODTCR_WRODT0_MASK) >> DDRPHY_ODTCR_WRODT0_SHIFT) + +/* + * RDODT3 (R/W) + * + */ +#define DDRPHY_ODTCR_RDODT3_MASK (0xF000U) +#define DDRPHY_ODTCR_RDODT3_SHIFT (12U) +#define DDRPHY_ODTCR_RDODT3_SET(x) (((uint32_t)(x) << DDRPHY_ODTCR_RDODT3_SHIFT) & DDRPHY_ODTCR_RDODT3_MASK) +#define DDRPHY_ODTCR_RDODT3_GET(x) (((uint32_t)(x) & DDRPHY_ODTCR_RDODT3_MASK) >> DDRPHY_ODTCR_RDODT3_SHIFT) + +/* + * RDODT2 (R/W) + * + */ +#define DDRPHY_ODTCR_RDODT2_MASK (0xF00U) +#define DDRPHY_ODTCR_RDODT2_SHIFT (8U) +#define DDRPHY_ODTCR_RDODT2_SET(x) (((uint32_t)(x) << DDRPHY_ODTCR_RDODT2_SHIFT) & DDRPHY_ODTCR_RDODT2_MASK) +#define DDRPHY_ODTCR_RDODT2_GET(x) (((uint32_t)(x) & DDRPHY_ODTCR_RDODT2_MASK) >> DDRPHY_ODTCR_RDODT2_SHIFT) + +/* + * RDODT1 (R/W) + * + */ +#define DDRPHY_ODTCR_RDODT1_MASK (0xF0U) +#define DDRPHY_ODTCR_RDODT1_SHIFT (4U) +#define DDRPHY_ODTCR_RDODT1_SET(x) (((uint32_t)(x) << DDRPHY_ODTCR_RDODT1_SHIFT) & DDRPHY_ODTCR_RDODT1_MASK) +#define DDRPHY_ODTCR_RDODT1_GET(x) (((uint32_t)(x) & DDRPHY_ODTCR_RDODT1_MASK) >> DDRPHY_ODTCR_RDODT1_SHIFT) + +/* + * RDODT0 (R/W) + * + * Read ODT: Specifies whether ODT should be enabled (‘1’) or disabled (‘0’) on each of the up to four ranks when a read command is sent to rank n. RDODT0, RDODT1, RDODT2, and RDODT3 specify ODT settings when a read is to rank 0, rank 1, rank 2, and rank 3, respectively. The four bits of each field each represent a rank, the LSB being rank 0 and the MSB being rank 3. Default is to disable ODT during reads. + */ +#define DDRPHY_ODTCR_RDODT0_MASK (0xFU) +#define DDRPHY_ODTCR_RDODT0_SHIFT (0U) +#define DDRPHY_ODTCR_RDODT0_SET(x) (((uint32_t)(x) << DDRPHY_ODTCR_RDODT0_SHIFT) & DDRPHY_ODTCR_RDODT0_MASK) +#define DDRPHY_ODTCR_RDODT0_GET(x) (((uint32_t)(x) & DDRPHY_ODTCR_RDODT0_MASK) >> DDRPHY_ODTCR_RDODT0_SHIFT) + +/* Bitfield definition for register: DTCR */ +/* + * RFSHDT (R/W) + * + * Refresh During Training: A non-zero value specifies that a burst of refreshes equal to the number specified in this field should be sent to the SDRAM after training each rank except the last rank. + */ +#define DDRPHY_DTCR_RFSHDT_MASK (0xF0000000UL) +#define DDRPHY_DTCR_RFSHDT_SHIFT (28U) +#define DDRPHY_DTCR_RFSHDT_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_RFSHDT_SHIFT) & DDRPHY_DTCR_RFSHDT_MASK) +#define DDRPHY_DTCR_RFSHDT_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_RFSHDT_MASK) >> DDRPHY_DTCR_RFSHDT_SHIFT) + +/* + * RANKEN (R/W) + * + * Rank Enable: Specifies the ranks that are enabled for data-training. Bit 0 controls rank 0, bit 1 controls rank 1, bit 2 controls rank 2, and bit 3 controls rank 3. Setting the bit to ‘1’ enables the rank, and setting it to ‘0’ disables the rank. + */ +#define DDRPHY_DTCR_RANKEN_MASK (0xF000000UL) +#define DDRPHY_DTCR_RANKEN_SHIFT (24U) +#define DDRPHY_DTCR_RANKEN_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_RANKEN_SHIFT) & DDRPHY_DTCR_RANKEN_MASK) +#define DDRPHY_DTCR_RANKEN_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_RANKEN_MASK) >> DDRPHY_DTCR_RANKEN_SHIFT) + +/* + * DTEXD (R/W) + * + * Data Training Extended Write DQS: Enables, if set, an extended write DQS whereby two additional pulses of DQS are added as post-amble to a burst of writes. + * Generally this should only be enabled when running read bit deskew with the intention of performing read eye deskew prior to running write leveling adjustment. + */ +#define DDRPHY_DTCR_DTEXD_MASK (0x400000UL) +#define DDRPHY_DTCR_DTEXD_SHIFT (22U) +#define DDRPHY_DTCR_DTEXD_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTEXD_SHIFT) & DDRPHY_DTCR_DTEXD_MASK) +#define DDRPHY_DTCR_DTEXD_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTEXD_MASK) >> DDRPHY_DTCR_DTEXD_SHIFT) + +/* + * DTDSTP (R/W) + * + * Data Training Debug Step: A write of 1 to this bit steps the data training algorithm through a single step. This bit is used to initiate one step of the data training algorithm in question. + * This bit is self-clearing. To trigger the next step, this bit must be written to again. Note: The training steps must be repeated in order to get new data in the “Data Training Eye Data Register 0-1 (DTEDR0-1)” on page 122. For example, to see the + * training results for a different lane, select that lane and repeat the training steps to + * populate DTEDR0 and DTEDR1 with the correct data. + */ +#define DDRPHY_DTCR_DTDSTP_MASK (0x200000UL) +#define DDRPHY_DTCR_DTDSTP_SHIFT (21U) +#define DDRPHY_DTCR_DTDSTP_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTDSTP_SHIFT) & DDRPHY_DTCR_DTDSTP_MASK) +#define DDRPHY_DTCR_DTDSTP_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTDSTP_MASK) >> DDRPHY_DTCR_DTDSTP_SHIFT) + +/* + * DTDEN (R/W) + * + * Data Training Debug Enable: Enables, if set, the data training single step debug mode. + */ +#define DDRPHY_DTCR_DTDEN_MASK (0x100000UL) +#define DDRPHY_DTCR_DTDEN_SHIFT (20U) +#define DDRPHY_DTCR_DTDEN_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTDEN_SHIFT) & DDRPHY_DTCR_DTDEN_MASK) +#define DDRPHY_DTCR_DTDEN_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTDEN_MASK) >> DDRPHY_DTCR_DTDEN_SHIFT) + +/* + * DTDBS (R/W) + * + * Data Training Debug Byte Select: Selects the byte during data training single step debug mode. + * Note: DTDEN is not used to enable this feature. + */ +#define DDRPHY_DTCR_DTDBS_MASK (0xF0000UL) +#define DDRPHY_DTCR_DTDBS_SHIFT (16U) +#define DDRPHY_DTCR_DTDBS_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTDBS_SHIFT) & DDRPHY_DTCR_DTDBS_MASK) +#define DDRPHY_DTCR_DTDBS_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTDBS_MASK) >> DDRPHY_DTCR_DTDBS_SHIFT) + +/* + * DTWDQMO (R/W) + * + * Data Training WDQ Margin Override: If set, the Training WDQ Margin value specified in DTCR[11:8] (DTWDQM) is used during data training. Otherwise the value is computed as ¼ of the ddr_clk period measurement found during calibration of the WDQ LCDL. + */ +#define DDRPHY_DTCR_DTWDQMO_MASK (0x4000U) +#define DDRPHY_DTCR_DTWDQMO_SHIFT (14U) +#define DDRPHY_DTCR_DTWDQMO_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTWDQMO_SHIFT) & DDRPHY_DTCR_DTWDQMO_MASK) +#define DDRPHY_DTCR_DTWDQMO_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTWDQMO_MASK) >> DDRPHY_DTCR_DTWDQMO_SHIFT) + +/* + * DTBDC (R/W) + * + * Data Training Bit Deskew Centering: Enables, if set, eye centering capability during write and read bit deskew training. + */ +#define DDRPHY_DTCR_DTBDC_MASK (0x2000U) +#define DDRPHY_DTCR_DTBDC_SHIFT (13U) +#define DDRPHY_DTCR_DTBDC_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTBDC_SHIFT) & DDRPHY_DTCR_DTBDC_MASK) +#define DDRPHY_DTCR_DTBDC_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTBDC_MASK) >> DDRPHY_DTCR_DTBDC_SHIFT) + +/* + * DTWBDDM (R/W) + * + * Data Training Write Bit Deskew Data Mask, if set, it enables write bit deskew of the data mask + */ +#define DDRPHY_DTCR_DTWBDDM_MASK (0x1000U) +#define DDRPHY_DTCR_DTWBDDM_SHIFT (12U) +#define DDRPHY_DTCR_DTWBDDM_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTWBDDM_SHIFT) & DDRPHY_DTCR_DTWBDDM_MASK) +#define DDRPHY_DTCR_DTWBDDM_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTWBDDM_MASK) >> DDRPHY_DTCR_DTWBDDM_SHIFT) + +/* + * DTWDQM (R/W) + * + * Training WDQ Margin: Defines how close to 0 or how close to 2*(wdq calibration_value) the WDQ LCDL can be moved during training. Basically defines how much timing margin. + */ +#define DDRPHY_DTCR_DTWDQM_MASK (0xF00U) +#define DDRPHY_DTCR_DTWDQM_SHIFT (8U) +#define DDRPHY_DTCR_DTWDQM_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTWDQM_SHIFT) & DDRPHY_DTCR_DTWDQM_MASK) +#define DDRPHY_DTCR_DTWDQM_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTWDQM_MASK) >> DDRPHY_DTCR_DTWDQM_SHIFT) + +/* + * DTCMPD (R/W) + * + * Read Data Training Compare Data: Specifies, if set, that DQS gate training should also check if the returning read data is correct. Otherwise data-training only checks if the correct number of DQS edges were returned. + */ +#define DDRPHY_DTCR_DTCMPD_MASK (0x80U) +#define DDRPHY_DTCR_DTCMPD_SHIFT (7U) +#define DDRPHY_DTCR_DTCMPD_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTCMPD_SHIFT) & DDRPHY_DTCR_DTCMPD_MASK) +#define DDRPHY_DTCR_DTCMPD_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTCMPD_MASK) >> DDRPHY_DTCR_DTCMPD_SHIFT) + +/* + * DTMPR (R/W) + * + * Read Data Training Using MPR (DDR3 Only): Specifies, if set, that DQS gate training should use the SDRAM Multi-Purpose Register (MPR) register. Otherwise data-training is performed by first writing to some locations in the SDRAM and then reading them back. + */ +#define DDRPHY_DTCR_DTMPR_MASK (0x40U) +#define DDRPHY_DTCR_DTMPR_SHIFT (6U) +#define DDRPHY_DTCR_DTMPR_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTMPR_SHIFT) & DDRPHY_DTCR_DTMPR_MASK) +#define DDRPHY_DTCR_DTMPR_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTMPR_MASK) >> DDRPHY_DTCR_DTMPR_SHIFT) + +/* + * DTRANK (R/W) + * + * Data Training Rank: Select the SDRAM rank to be used during Read DQS gate training, Read/Write Data Bit Deskew, Read/Write Eye Training. + */ +#define DDRPHY_DTCR_DTRANK_MASK (0x30U) +#define DDRPHY_DTCR_DTRANK_SHIFT (4U) +#define DDRPHY_DTCR_DTRANK_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTRANK_SHIFT) & DDRPHY_DTCR_DTRANK_MASK) +#define DDRPHY_DTCR_DTRANK_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTRANK_MASK) >> DDRPHY_DTCR_DTRANK_SHIFT) + +/* + * DTRPTN (R/W) + * + * Data Training Repeat Number: Repeat number used to confirm stability of DDR write or read. + * Note: The minimum value should be 0x4 and the maximum value should be 0x14. + */ +#define DDRPHY_DTCR_DTRPTN_MASK (0xFU) +#define DDRPHY_DTCR_DTRPTN_SHIFT (0U) +#define DDRPHY_DTCR_DTRPTN_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTRPTN_SHIFT) & DDRPHY_DTCR_DTRPTN_MASK) +#define DDRPHY_DTCR_DTRPTN_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTRPTN_MASK) >> DDRPHY_DTCR_DTRPTN_SHIFT) + +/* Bitfield definition for register: DTAR0 */ +/* + * DTBANK (R/W) + * + * Data Training Bank Address: Selects the SDRAM bank address to be used during data training. + */ +#define DDRPHY_DTAR0_DTBANK_MASK (0x70000000UL) +#define DDRPHY_DTAR0_DTBANK_SHIFT (28U) +#define DDRPHY_DTAR0_DTBANK_SET(x) (((uint32_t)(x) << DDRPHY_DTAR0_DTBANK_SHIFT) & DDRPHY_DTAR0_DTBANK_MASK) +#define DDRPHY_DTAR0_DTBANK_GET(x) (((uint32_t)(x) & DDRPHY_DTAR0_DTBANK_MASK) >> DDRPHY_DTAR0_DTBANK_SHIFT) + +/* + * DTROW (R/W) + * + * Data Training Row Address: Selects the SDRAM row address to be used during data training. + */ +#define DDRPHY_DTAR0_DTROW_MASK (0xFFFF000UL) +#define DDRPHY_DTAR0_DTROW_SHIFT (12U) +#define DDRPHY_DTAR0_DTROW_SET(x) (((uint32_t)(x) << DDRPHY_DTAR0_DTROW_SHIFT) & DDRPHY_DTAR0_DTROW_MASK) +#define DDRPHY_DTAR0_DTROW_GET(x) (((uint32_t)(x) & DDRPHY_DTAR0_DTROW_MASK) >> DDRPHY_DTAR0_DTROW_SHIFT) + +/* + * DTCOL (R/W) + * + * Data Training Column Address: Selects the SDRAM column address to be used during data training. The lower four bits of this address must always be “000”. + */ +#define DDRPHY_DTAR0_DTCOL_MASK (0xFFFU) +#define DDRPHY_DTAR0_DTCOL_SHIFT (0U) +#define DDRPHY_DTAR0_DTCOL_SET(x) (((uint32_t)(x) << DDRPHY_DTAR0_DTCOL_SHIFT) & DDRPHY_DTAR0_DTCOL_MASK) +#define DDRPHY_DTAR0_DTCOL_GET(x) (((uint32_t)(x) & DDRPHY_DTAR0_DTCOL_MASK) >> DDRPHY_DTAR0_DTCOL_SHIFT) + +/* Bitfield definition for register: DTAR1 */ +/* + * DTBANK (R/W) + * + * Data Training Bank Address: Selects the SDRAM bank address to be used during data training. + */ +#define DDRPHY_DTAR1_DTBANK_MASK (0x70000000UL) +#define DDRPHY_DTAR1_DTBANK_SHIFT (28U) +#define DDRPHY_DTAR1_DTBANK_SET(x) (((uint32_t)(x) << DDRPHY_DTAR1_DTBANK_SHIFT) & DDRPHY_DTAR1_DTBANK_MASK) +#define DDRPHY_DTAR1_DTBANK_GET(x) (((uint32_t)(x) & DDRPHY_DTAR1_DTBANK_MASK) >> DDRPHY_DTAR1_DTBANK_SHIFT) + +/* + * DTROW (R/W) + * + * Data Training Row Address: Selects the SDRAM row address to be used during data training. + */ +#define DDRPHY_DTAR1_DTROW_MASK (0xFFFF000UL) +#define DDRPHY_DTAR1_DTROW_SHIFT (12U) +#define DDRPHY_DTAR1_DTROW_SET(x) (((uint32_t)(x) << DDRPHY_DTAR1_DTROW_SHIFT) & DDRPHY_DTAR1_DTROW_MASK) +#define DDRPHY_DTAR1_DTROW_GET(x) (((uint32_t)(x) & DDRPHY_DTAR1_DTROW_MASK) >> DDRPHY_DTAR1_DTROW_SHIFT) + +/* + * DTCOL (R/W) + * + * Data Training Column Address: Selects the SDRAM column address to be used during data training. The lower four bits of this address must always be “000”. + */ +#define DDRPHY_DTAR1_DTCOL_MASK (0xFFFU) +#define DDRPHY_DTAR1_DTCOL_SHIFT (0U) +#define DDRPHY_DTAR1_DTCOL_SET(x) (((uint32_t)(x) << DDRPHY_DTAR1_DTCOL_SHIFT) & DDRPHY_DTAR1_DTCOL_MASK) +#define DDRPHY_DTAR1_DTCOL_GET(x) (((uint32_t)(x) & DDRPHY_DTAR1_DTCOL_MASK) >> DDRPHY_DTAR1_DTCOL_SHIFT) + +/* Bitfield definition for register: DTAR2 */ +/* + * DTBANK (R/W) + * + * Data Training Bank Address: Selects the SDRAM bank address to be used during data training. + */ +#define DDRPHY_DTAR2_DTBANK_MASK (0x70000000UL) +#define DDRPHY_DTAR2_DTBANK_SHIFT (28U) +#define DDRPHY_DTAR2_DTBANK_SET(x) (((uint32_t)(x) << DDRPHY_DTAR2_DTBANK_SHIFT) & DDRPHY_DTAR2_DTBANK_MASK) +#define DDRPHY_DTAR2_DTBANK_GET(x) (((uint32_t)(x) & DDRPHY_DTAR2_DTBANK_MASK) >> DDRPHY_DTAR2_DTBANK_SHIFT) + +/* + * DTROW (R/W) + * + * Data Training Row Address: Selects the SDRAM row address to be used during data training. + */ +#define DDRPHY_DTAR2_DTROW_MASK (0xFFFF000UL) +#define DDRPHY_DTAR2_DTROW_SHIFT (12U) +#define DDRPHY_DTAR2_DTROW_SET(x) (((uint32_t)(x) << DDRPHY_DTAR2_DTROW_SHIFT) & DDRPHY_DTAR2_DTROW_MASK) +#define DDRPHY_DTAR2_DTROW_GET(x) (((uint32_t)(x) & DDRPHY_DTAR2_DTROW_MASK) >> DDRPHY_DTAR2_DTROW_SHIFT) + +/* + * DTCOL (R/W) + * + * Data Training Column Address: Selects the SDRAM column address to be used during data training. The lower four bits of this address must always be “000”. + */ +#define DDRPHY_DTAR2_DTCOL_MASK (0xFFFU) +#define DDRPHY_DTAR2_DTCOL_SHIFT (0U) +#define DDRPHY_DTAR2_DTCOL_SET(x) (((uint32_t)(x) << DDRPHY_DTAR2_DTCOL_SHIFT) & DDRPHY_DTAR2_DTCOL_MASK) +#define DDRPHY_DTAR2_DTCOL_GET(x) (((uint32_t)(x) & DDRPHY_DTAR2_DTCOL_MASK) >> DDRPHY_DTAR2_DTCOL_SHIFT) + +/* Bitfield definition for register: DTAR3 */ +/* + * DTBANK (R/W) + * + * Data Training Bank Address: Selects the SDRAM bank address to be used during data training. + */ +#define DDRPHY_DTAR3_DTBANK_MASK (0x70000000UL) +#define DDRPHY_DTAR3_DTBANK_SHIFT (28U) +#define DDRPHY_DTAR3_DTBANK_SET(x) (((uint32_t)(x) << DDRPHY_DTAR3_DTBANK_SHIFT) & DDRPHY_DTAR3_DTBANK_MASK) +#define DDRPHY_DTAR3_DTBANK_GET(x) (((uint32_t)(x) & DDRPHY_DTAR3_DTBANK_MASK) >> DDRPHY_DTAR3_DTBANK_SHIFT) + +/* + * DTROW (R/W) + * + * Data Training Row Address: Selects the SDRAM row address to be used during data training. + */ +#define DDRPHY_DTAR3_DTROW_MASK (0xFFFF000UL) +#define DDRPHY_DTAR3_DTROW_SHIFT (12U) +#define DDRPHY_DTAR3_DTROW_SET(x) (((uint32_t)(x) << DDRPHY_DTAR3_DTROW_SHIFT) & DDRPHY_DTAR3_DTROW_MASK) +#define DDRPHY_DTAR3_DTROW_GET(x) (((uint32_t)(x) & DDRPHY_DTAR3_DTROW_MASK) >> DDRPHY_DTAR3_DTROW_SHIFT) + +/* + * DTCOL (R/W) + * + * Data Training Column Address: Selects the SDRAM column address to be used during data training. The lower four bits of this address must always be “000”. + */ +#define DDRPHY_DTAR3_DTCOL_MASK (0xFFFU) +#define DDRPHY_DTAR3_DTCOL_SHIFT (0U) +#define DDRPHY_DTAR3_DTCOL_SET(x) (((uint32_t)(x) << DDRPHY_DTAR3_DTCOL_SHIFT) & DDRPHY_DTAR3_DTCOL_MASK) +#define DDRPHY_DTAR3_DTCOL_GET(x) (((uint32_t)(x) & DDRPHY_DTAR3_DTCOL_MASK) >> DDRPHY_DTAR3_DTCOL_SHIFT) + +/* Bitfield definition for register: DTDR0 */ +/* + * DTBYTE3 (R/W) + * + */ +#define DDRPHY_DTDR0_DTBYTE3_MASK (0xFF000000UL) +#define DDRPHY_DTDR0_DTBYTE3_SHIFT (24U) +#define DDRPHY_DTDR0_DTBYTE3_SET(x) (((uint32_t)(x) << DDRPHY_DTDR0_DTBYTE3_SHIFT) & DDRPHY_DTDR0_DTBYTE3_MASK) +#define DDRPHY_DTDR0_DTBYTE3_GET(x) (((uint32_t)(x) & DDRPHY_DTDR0_DTBYTE3_MASK) >> DDRPHY_DTDR0_DTBYTE3_SHIFT) + +/* + * DTBYTE2 (R/W) + * + */ +#define DDRPHY_DTDR0_DTBYTE2_MASK (0xFF0000UL) +#define DDRPHY_DTDR0_DTBYTE2_SHIFT (16U) +#define DDRPHY_DTDR0_DTBYTE2_SET(x) (((uint32_t)(x) << DDRPHY_DTDR0_DTBYTE2_SHIFT) & DDRPHY_DTDR0_DTBYTE2_MASK) +#define DDRPHY_DTDR0_DTBYTE2_GET(x) (((uint32_t)(x) & DDRPHY_DTDR0_DTBYTE2_MASK) >> DDRPHY_DTDR0_DTBYTE2_SHIFT) + +/* + * DTBYTE1 (R/W) + * + */ +#define DDRPHY_DTDR0_DTBYTE1_MASK (0xFF00U) +#define DDRPHY_DTDR0_DTBYTE1_SHIFT (8U) +#define DDRPHY_DTDR0_DTBYTE1_SET(x) (((uint32_t)(x) << DDRPHY_DTDR0_DTBYTE1_SHIFT) & DDRPHY_DTDR0_DTBYTE1_MASK) +#define DDRPHY_DTDR0_DTBYTE1_GET(x) (((uint32_t)(x) & DDRPHY_DTDR0_DTBYTE1_MASK) >> DDRPHY_DTDR0_DTBYTE1_SHIFT) + +/* + * DTBYTE0 (R/W) + * + * Data Training Data: The first 4 bytes of data used during data training. This same data byte is used for each Byte Lane. Default sequence is a walking 1 while toggling data every data cycle. + */ +#define DDRPHY_DTDR0_DTBYTE0_MASK (0xFFU) +#define DDRPHY_DTDR0_DTBYTE0_SHIFT (0U) +#define DDRPHY_DTDR0_DTBYTE0_SET(x) (((uint32_t)(x) << DDRPHY_DTDR0_DTBYTE0_SHIFT) & DDRPHY_DTDR0_DTBYTE0_MASK) +#define DDRPHY_DTDR0_DTBYTE0_GET(x) (((uint32_t)(x) & DDRPHY_DTDR0_DTBYTE0_MASK) >> DDRPHY_DTDR0_DTBYTE0_SHIFT) + +/* Bitfield definition for register: DTDR1 */ +/* + * DTBYTE7 (R/W) + * + */ +#define DDRPHY_DTDR1_DTBYTE7_MASK (0xFF000000UL) +#define DDRPHY_DTDR1_DTBYTE7_SHIFT (24U) +#define DDRPHY_DTDR1_DTBYTE7_SET(x) (((uint32_t)(x) << DDRPHY_DTDR1_DTBYTE7_SHIFT) & DDRPHY_DTDR1_DTBYTE7_MASK) +#define DDRPHY_DTDR1_DTBYTE7_GET(x) (((uint32_t)(x) & DDRPHY_DTDR1_DTBYTE7_MASK) >> DDRPHY_DTDR1_DTBYTE7_SHIFT) + +/* + * DTBYTE6 (R/W) + * + */ +#define DDRPHY_DTDR1_DTBYTE6_MASK (0xFF0000UL) +#define DDRPHY_DTDR1_DTBYTE6_SHIFT (16U) +#define DDRPHY_DTDR1_DTBYTE6_SET(x) (((uint32_t)(x) << DDRPHY_DTDR1_DTBYTE6_SHIFT) & DDRPHY_DTDR1_DTBYTE6_MASK) +#define DDRPHY_DTDR1_DTBYTE6_GET(x) (((uint32_t)(x) & DDRPHY_DTDR1_DTBYTE6_MASK) >> DDRPHY_DTDR1_DTBYTE6_SHIFT) + +/* + * DTBYTE5 (R/W) + * + */ +#define DDRPHY_DTDR1_DTBYTE5_MASK (0xFF00U) +#define DDRPHY_DTDR1_DTBYTE5_SHIFT (8U) +#define DDRPHY_DTDR1_DTBYTE5_SET(x) (((uint32_t)(x) << DDRPHY_DTDR1_DTBYTE5_SHIFT) & DDRPHY_DTDR1_DTBYTE5_MASK) +#define DDRPHY_DTDR1_DTBYTE5_GET(x) (((uint32_t)(x) & DDRPHY_DTDR1_DTBYTE5_MASK) >> DDRPHY_DTDR1_DTBYTE5_SHIFT) + +/* + * DTBYTE4 (R/W) + * + * Data Training Data: The second 4 bytes of data used during data training. This same data byte is used for each Byte Lane. Default sequence is a walking 1 while toggling data every data cycle. + */ +#define DDRPHY_DTDR1_DTBYTE4_MASK (0xFFU) +#define DDRPHY_DTDR1_DTBYTE4_SHIFT (0U) +#define DDRPHY_DTDR1_DTBYTE4_SET(x) (((uint32_t)(x) << DDRPHY_DTDR1_DTBYTE4_SHIFT) & DDRPHY_DTDR1_DTBYTE4_MASK) +#define DDRPHY_DTDR1_DTBYTE4_GET(x) (((uint32_t)(x) & DDRPHY_DTDR1_DTBYTE4_MASK) >> DDRPHY_DTDR1_DTBYTE4_SHIFT) + +/* Bitfield definition for register: DTEDR0 */ +/* + * DTWBMX (R) + * + * Data Training Write BDL Shift Maximum. + */ +#define DDRPHY_DTEDR0_DTWBMX_MASK (0xFF000000UL) +#define DDRPHY_DTEDR0_DTWBMX_SHIFT (24U) +#define DDRPHY_DTEDR0_DTWBMX_GET(x) (((uint32_t)(x) & DDRPHY_DTEDR0_DTWBMX_MASK) >> DDRPHY_DTEDR0_DTWBMX_SHIFT) + +/* + * DTWBMN (R) + * + * Data Training Write BDL Shift Minimum. + */ +#define DDRPHY_DTEDR0_DTWBMN_MASK (0xFF0000UL) +#define DDRPHY_DTEDR0_DTWBMN_SHIFT (16U) +#define DDRPHY_DTEDR0_DTWBMN_GET(x) (((uint32_t)(x) & DDRPHY_DTEDR0_DTWBMN_MASK) >> DDRPHY_DTEDR0_DTWBMN_SHIFT) + +/* + * DTWLMX (R) + * + * Data Training WDQ LCDL Maximum. + */ +#define DDRPHY_DTEDR0_DTWLMX_MASK (0xFF00U) +#define DDRPHY_DTEDR0_DTWLMX_SHIFT (8U) +#define DDRPHY_DTEDR0_DTWLMX_GET(x) (((uint32_t)(x) & DDRPHY_DTEDR0_DTWLMX_MASK) >> DDRPHY_DTEDR0_DTWLMX_SHIFT) + +/* + * DTWLMN (R) + * + * Data Training WDQ LCDL Minimum. + */ +#define DDRPHY_DTEDR0_DTWLMN_MASK (0xFFU) +#define DDRPHY_DTEDR0_DTWLMN_SHIFT (0U) +#define DDRPHY_DTEDR0_DTWLMN_GET(x) (((uint32_t)(x) & DDRPHY_DTEDR0_DTWLMN_MASK) >> DDRPHY_DTEDR0_DTWLMN_SHIFT) + +/* Bitfield definition for register: DTEDR1 */ +/* + * DTRBMX (R) + * + * Data Training Read BDL Shift Maximum. + */ +#define DDRPHY_DTEDR1_DTRBMX_MASK (0xFF000000UL) +#define DDRPHY_DTEDR1_DTRBMX_SHIFT (24U) +#define DDRPHY_DTEDR1_DTRBMX_GET(x) (((uint32_t)(x) & DDRPHY_DTEDR1_DTRBMX_MASK) >> DDRPHY_DTEDR1_DTRBMX_SHIFT) + +/* + * DTRBMN (R) + * + * Data Training Read BDL Shift Minimum. + */ +#define DDRPHY_DTEDR1_DTRBMN_MASK (0xFF0000UL) +#define DDRPHY_DTEDR1_DTRBMN_SHIFT (16U) +#define DDRPHY_DTEDR1_DTRBMN_GET(x) (((uint32_t)(x) & DDRPHY_DTEDR1_DTRBMN_MASK) >> DDRPHY_DTEDR1_DTRBMN_SHIFT) + +/* + * DTRLMX (R) + * + * Data Training RDQS LCDL Maximum. + */ +#define DDRPHY_DTEDR1_DTRLMX_MASK (0xFF00U) +#define DDRPHY_DTEDR1_DTRLMX_SHIFT (8U) +#define DDRPHY_DTEDR1_DTRLMX_GET(x) (((uint32_t)(x) & DDRPHY_DTEDR1_DTRLMX_MASK) >> DDRPHY_DTEDR1_DTRLMX_SHIFT) + +/* + * DTRLMN (R) + * + * Data Training RDQS LCDL Minimum. + */ +#define DDRPHY_DTEDR1_DTRLMN_MASK (0xFFU) +#define DDRPHY_DTEDR1_DTRLMN_SHIFT (0U) +#define DDRPHY_DTEDR1_DTRLMN_GET(x) (((uint32_t)(x) & DDRPHY_DTEDR1_DTRLMN_MASK) >> DDRPHY_DTEDR1_DTRLMN_SHIFT) + +/* Bitfield definition for register: PGCR2 */ +/* + * DYNACPDD1 (R/W) + * + * Dynamic AC Power Down Driver: Powers down, when set, the output driver on I/O for ADDR and BA. This bit is ORed with bit ACIOCR[3] (ACPDD). + */ +#define DDRPHY_PGCR2_DYNACPDD1_MASK (0x80000000UL) +#define DDRPHY_PGCR2_DYNACPDD1_SHIFT (31U) +#define DDRPHY_PGCR2_DYNACPDD1_SET(x) (((uint32_t)(x) << DDRPHY_PGCR2_DYNACPDD1_SHIFT) & DDRPHY_PGCR2_DYNACPDD1_MASK) +#define DDRPHY_PGCR2_DYNACPDD1_GET(x) (((uint32_t)(x) & DDRPHY_PGCR2_DYNACPDD1_MASK) >> DDRPHY_PGCR2_DYNACPDD1_SHIFT) + +/* + * LPMSTRC0 (R/W) + * + * Low-Power Master Channel 0: set to 1 to have channel 0 act as master to drive channel 1 low-power functions simultaneously. Only valid in shared-AC mode. + */ +#define DDRPHY_PGCR2_LPMSTRC0_MASK (0x40000000UL) +#define DDRPHY_PGCR2_LPMSTRC0_SHIFT (30U) +#define DDRPHY_PGCR2_LPMSTRC0_SET(x) (((uint32_t)(x) << DDRPHY_PGCR2_LPMSTRC0_SHIFT) & DDRPHY_PGCR2_LPMSTRC0_MASK) +#define DDRPHY_PGCR2_LPMSTRC0_GET(x) (((uint32_t)(x) & DDRPHY_PGCR2_LPMSTRC0_MASK) >> DDRPHY_PGCR2_LPMSTRC0_SHIFT) + +/* + * ACPDDC (R/W) + * + * AC Power-Down with Dual Channels: Set to 1 to power-down address/command lane when both data channels are powered-down. Only valid in shared-AC mode. + */ +#define DDRPHY_PGCR2_ACPDDC_MASK (0x20000000UL) +#define DDRPHY_PGCR2_ACPDDC_SHIFT (29U) +#define DDRPHY_PGCR2_ACPDDC_SET(x) (((uint32_t)(x) << DDRPHY_PGCR2_ACPDDC_SHIFT) & DDRPHY_PGCR2_ACPDDC_MASK) +#define DDRPHY_PGCR2_ACPDDC_GET(x) (((uint32_t)(x) & DDRPHY_PGCR2_ACPDDC_MASK) >> DDRPHY_PGCR2_ACPDDC_SHIFT) + +/* + * SHRAC (R/W) + * + * Shared-AC mode: set to 1 to enable shared address/command mode with two independent data channels – available only if shared address/command mode support is compiled in. + */ +#define DDRPHY_PGCR2_SHRAC_MASK (0x10000000UL) +#define DDRPHY_PGCR2_SHRAC_SHIFT (28U) +#define DDRPHY_PGCR2_SHRAC_SET(x) (((uint32_t)(x) << DDRPHY_PGCR2_SHRAC_SHIFT) & DDRPHY_PGCR2_SHRAC_MASK) +#define DDRPHY_PGCR2_SHRAC_GET(x) (((uint32_t)(x) & DDRPHY_PGCR2_SHRAC_MASK) >> DDRPHY_PGCR2_SHRAC_SHIFT) + +/* + * DTPMXTMR (R/W) + * + * Data Training PUB Mode Timer Exit: Specifies the number of controller clocks to wait when entering and exiting pub mode data training. The default value ensures controller refreshes do not cause memory model errors when entering and exiting data training. The value should be increased if controller initiated SDRAM ZQ short or long operation may occur just before or just after the execution of data training. + */ +#define DDRPHY_PGCR2_DTPMXTMR_MASK (0xFF00000UL) +#define DDRPHY_PGCR2_DTPMXTMR_SHIFT (20U) +#define DDRPHY_PGCR2_DTPMXTMR_SET(x) (((uint32_t)(x) << DDRPHY_PGCR2_DTPMXTMR_SHIFT) & DDRPHY_PGCR2_DTPMXTMR_MASK) +#define DDRPHY_PGCR2_DTPMXTMR_GET(x) (((uint32_t)(x) & DDRPHY_PGCR2_DTPMXTMR_MASK) >> DDRPHY_PGCR2_DTPMXTMR_SHIFT) + +/* + * FXDLAT (R/W) + * + * Fixed Latency: Specified whether all reads should be returned to the controller with a fixed read latency. Enabling fixed read latency increases the read latency. Valid values are: + * 0 = Disable fixed read latency 1 = Enable fixed read latency + * Fixed read latency is calculated as (12 + (maximum DXnGTR.RxDGSL)/2) HDR clock cycles + */ +#define DDRPHY_PGCR2_FXDLAT_MASK (0x80000UL) +#define DDRPHY_PGCR2_FXDLAT_SHIFT (19U) +#define DDRPHY_PGCR2_FXDLAT_SET(x) (((uint32_t)(x) << DDRPHY_PGCR2_FXDLAT_SHIFT) & DDRPHY_PGCR2_FXDLAT_MASK) +#define DDRPHY_PGCR2_FXDLAT_GET(x) (((uint32_t)(x) & DDRPHY_PGCR2_FXDLAT_MASK) >> DDRPHY_PGCR2_FXDLAT_SHIFT) + +/* + * NOBUB (R/W) + * + * No Bubbles: Specified whether reads should be returned to the controller with no bubbles. Enabling no-bubble reads increases the read latency. Valid values are: 0 = Bubbles are allowed during reads + * 1 = Bubbles are not allowed during reads + */ +#define DDRPHY_PGCR2_NOBUB_MASK (0x40000UL) +#define DDRPHY_PGCR2_NOBUB_SHIFT (18U) +#define DDRPHY_PGCR2_NOBUB_SET(x) (((uint32_t)(x) << DDRPHY_PGCR2_NOBUB_SHIFT) & DDRPHY_PGCR2_NOBUB_MASK) +#define DDRPHY_PGCR2_NOBUB_GET(x) (((uint32_t)(x) & DDRPHY_PGCR2_NOBUB_MASK) >> DDRPHY_PGCR2_NOBUB_SHIFT) + +/* + * TREFPRD (R/W) + * + * Refresh Period: Indicates the period, after which the PUB has to issue a refresh command to the SDRAM. This is derived from the maximum refresh interval from the datasheet, tRFC(max) or REFI, divided by the clock cycle time. A further 400 clocks must be subtracted from the derived number to account for command flow and missed slots of refreshes in the internal PUB blocks. The default corresponds to DDR3 9*7.8us at 1066MHz when a burst of 9 refreshes are issued at every refresh interval. + */ +#define DDRPHY_PGCR2_TREFPRD_MASK (0x3FFFFUL) +#define DDRPHY_PGCR2_TREFPRD_SHIFT (0U) +#define DDRPHY_PGCR2_TREFPRD_SET(x) (((uint32_t)(x) << DDRPHY_PGCR2_TREFPRD_SHIFT) & DDRPHY_PGCR2_TREFPRD_MASK) +#define DDRPHY_PGCR2_TREFPRD_GET(x) (((uint32_t)(x) & DDRPHY_PGCR2_TREFPRD_MASK) >> DDRPHY_PGCR2_TREFPRD_SHIFT) + +/* Bitfield definition for register: RDIMMGCR0 */ +/* + * MIRROR (R) + * + * RDIMM Mirror: Selects between two different ballouts of the RDIMM buffer chip for front or back operation. This register bit controls the buffer chip MIRROR signal. + */ +#define DDRPHY_RDIMMGCR0_MIRROR_MASK (0x80000000UL) +#define DDRPHY_RDIMMGCR0_MIRROR_SHIFT (31U) +#define DDRPHY_RDIMMGCR0_MIRROR_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_MIRROR_MASK) >> DDRPHY_RDIMMGCR0_MIRROR_SHIFT) + +/* + * QCSEN (R) + * + * RDMIMM Quad CS Enable: Enables, if set, the Quad CS mode for the RDIMM registering buffer chip. This register bit controls the buffer chip QCSEN# signal. + */ +#define DDRPHY_RDIMMGCR0_QCSEN_MASK (0x40000000UL) +#define DDRPHY_RDIMMGCR0_QCSEN_SHIFT (30U) +#define DDRPHY_RDIMMGCR0_QCSEN_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_QCSEN_MASK) >> DDRPHY_RDIMMGCR0_QCSEN_SHIFT) + +/* + * MIRROROE (R) + * + * MIRROR Output Enable: Enables, when set, the output driver on the I/O for MIRROR pin. + */ +#define DDRPHY_RDIMMGCR0_MIRROROE_MASK (0x20000000UL) +#define DDRPHY_RDIMMGCR0_MIRROROE_SHIFT (29U) +#define DDRPHY_RDIMMGCR0_MIRROROE_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_MIRROROE_MASK) >> DDRPHY_RDIMMGCR0_MIRROROE_SHIFT) + +/* + * QCSENOE (R) + * + * QCSEN# Output Enable: Enables, when set, the output driver on the I/O for QCSEN# pin. + */ +#define DDRPHY_RDIMMGCR0_QCSENOE_MASK (0x10000000UL) +#define DDRPHY_RDIMMGCR0_QCSENOE_SHIFT (28U) +#define DDRPHY_RDIMMGCR0_QCSENOE_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_QCSENOE_MASK) >> DDRPHY_RDIMMGCR0_QCSENOE_SHIFT) + +/* + * RDIMMIOM (R) + * + * RDIMM Outputs I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for QCSEN# and MIRROR pins. + */ +#define DDRPHY_RDIMMGCR0_RDIMMIOM_MASK (0x8000000UL) +#define DDRPHY_RDIMMGCR0_RDIMMIOM_SHIFT (27U) +#define DDRPHY_RDIMMGCR0_RDIMMIOM_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_RDIMMIOM_MASK) >> DDRPHY_RDIMMGCR0_RDIMMIOM_SHIFT) + +/* + * RDIMMPDR (R) + * + * RDIMM Outputs Power Down Receiver: Powers down, when set, the input receiver on the I/O for QCSEN# and MIRROR pins. + */ +#define DDRPHY_RDIMMGCR0_RDIMMPDR_MASK (0x4000000UL) +#define DDRPHY_RDIMMGCR0_RDIMMPDR_SHIFT (26U) +#define DDRPHY_RDIMMGCR0_RDIMMPDR_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_RDIMMPDR_MASK) >> DDRPHY_RDIMMGCR0_RDIMMPDR_SHIFT) + +/* + * RDIMMPDD (R) + * + * RDIMM Outputs Power Down Driver: Powers down, when set, the output driver on the I/O for QCSEN# and MIRROR pins. + */ +#define DDRPHY_RDIMMGCR0_RDIMMPDD_MASK (0x2000000UL) +#define DDRPHY_RDIMMGCR0_RDIMMPDD_SHIFT (25U) +#define DDRPHY_RDIMMGCR0_RDIMMPDD_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_RDIMMPDD_MASK) >> DDRPHY_RDIMMGCR0_RDIMMPDD_SHIFT) + +/* + * RDIMMODT (R) + * + * RDIMM Outputs On-Die Termination: Enables, when set, the on-die termination on the I/O for QCSEN# and MIRROR pins. + */ +#define DDRPHY_RDIMMGCR0_RDIMMODT_MASK (0x1000000UL) +#define DDRPHY_RDIMMGCR0_RDIMMODT_SHIFT (24U) +#define DDRPHY_RDIMMGCR0_RDIMMODT_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_RDIMMODT_MASK) >> DDRPHY_RDIMMGCR0_RDIMMODT_SHIFT) + +/* + * ERROUTOE (R) + * + * ERROUT# Output Enable: Enables, when set, the output driver on the I/O for ERROUT# pin. + */ +#define DDRPHY_RDIMMGCR0_ERROUTOE_MASK (0x800000UL) +#define DDRPHY_RDIMMGCR0_ERROUTOE_SHIFT (23U) +#define DDRPHY_RDIMMGCR0_ERROUTOE_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_ERROUTOE_MASK) >> DDRPHY_RDIMMGCR0_ERROUTOE_SHIFT) + +/* + * ERROUTIOM (R) + * + * ERROUT# I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for ERROUT# pin. + */ +#define DDRPHY_RDIMMGCR0_ERROUTIOM_MASK (0x400000UL) +#define DDRPHY_RDIMMGCR0_ERROUTIOM_SHIFT (22U) +#define DDRPHY_RDIMMGCR0_ERROUTIOM_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_ERROUTIOM_MASK) >> DDRPHY_RDIMMGCR0_ERROUTIOM_SHIFT) + +/* + * ERROUTPDR (R) + * + * ERROUT# Power Down Receiver: Powers down, when set, the input receiver on the I/O for ERROUT# pin. + */ +#define DDRPHY_RDIMMGCR0_ERROUTPDR_MASK (0x200000UL) +#define DDRPHY_RDIMMGCR0_ERROUTPDR_SHIFT (21U) +#define DDRPHY_RDIMMGCR0_ERROUTPDR_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_ERROUTPDR_MASK) >> DDRPHY_RDIMMGCR0_ERROUTPDR_SHIFT) + +/* + * ERROUTPDD (R) + * + * ERROUT# Power Down Driver: Powers down, when set, the output driver on the I/O for ERROUT# pin. + */ +#define DDRPHY_RDIMMGCR0_ERROUTPDD_MASK (0x100000UL) +#define DDRPHY_RDIMMGCR0_ERROUTPDD_SHIFT (20U) +#define DDRPHY_RDIMMGCR0_ERROUTPDD_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_ERROUTPDD_MASK) >> DDRPHY_RDIMMGCR0_ERROUTPDD_SHIFT) + +/* + * ERROUTODT (R) + * + * ERROUT# On-Die Termination: Enables, when set, the on-die termination on the I/O for ERROUT# pin. + */ +#define DDRPHY_RDIMMGCR0_ERROUTODT_MASK (0x80000UL) +#define DDRPHY_RDIMMGCR0_ERROUTODT_SHIFT (19U) +#define DDRPHY_RDIMMGCR0_ERROUTODT_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_ERROUTODT_MASK) >> DDRPHY_RDIMMGCR0_ERROUTODT_SHIFT) + +/* + * PARINOE (R) + * + * PAR_IN Output Enable: Enables, when set, the output driver on the I/O for PAR_IN pin. + */ +#define DDRPHY_RDIMMGCR0_PARINOE_MASK (0x40000UL) +#define DDRPHY_RDIMMGCR0_PARINOE_SHIFT (18U) +#define DDRPHY_RDIMMGCR0_PARINOE_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_PARINOE_MASK) >> DDRPHY_RDIMMGCR0_PARINOE_SHIFT) + +/* + * PARINIOM (R) + * + * PAR_IN I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for PAR_IN pin. + */ +#define DDRPHY_RDIMMGCR0_PARINIOM_MASK (0x20000UL) +#define DDRPHY_RDIMMGCR0_PARINIOM_SHIFT (17U) +#define DDRPHY_RDIMMGCR0_PARINIOM_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_PARINIOM_MASK) >> DDRPHY_RDIMMGCR0_PARINIOM_SHIFT) + +/* + * PARINPDR (R) + * + * PAR_IN Power Down Receiver: Powers down, when set, the input receiver on the I/O for PAR_IN pin. + */ +#define DDRPHY_RDIMMGCR0_PARINPDR_MASK (0x10000UL) +#define DDRPHY_RDIMMGCR0_PARINPDR_SHIFT (16U) +#define DDRPHY_RDIMMGCR0_PARINPDR_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_PARINPDR_MASK) >> DDRPHY_RDIMMGCR0_PARINPDR_SHIFT) + +/* + * PARINPDD (R) + * + * PAR_IN Power Down Driver: Powers down, when set, the output driver on the I/O for PAR_IN pin. + */ +#define DDRPHY_RDIMMGCR0_PARINPDD_MASK (0x8000U) +#define DDRPHY_RDIMMGCR0_PARINPDD_SHIFT (15U) +#define DDRPHY_RDIMMGCR0_PARINPDD_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_PARINPDD_MASK) >> DDRPHY_RDIMMGCR0_PARINPDD_SHIFT) + +/* + * PARINODT (R) + * + * PAR_IN On-Die Termination: Enables, when set, the on-die termination on the I/O for PAR_IN pin. + */ +#define DDRPHY_RDIMMGCR0_PARINODT_MASK (0x4000U) +#define DDRPHY_RDIMMGCR0_PARINODT_SHIFT (14U) +#define DDRPHY_RDIMMGCR0_PARINODT_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_PARINODT_MASK) >> DDRPHY_RDIMMGCR0_PARINODT_SHIFT) + +/* + * SOPERR (R) + * + * Stop On Parity Error: Indicates, if set, that the PUB is to stop driving commands to the DRAM upon encountering a parity error. Transactions can resume only after status is cleared via PIR.CLRSR. + */ +#define DDRPHY_RDIMMGCR0_SOPERR_MASK (0x4U) +#define DDRPHY_RDIMMGCR0_SOPERR_SHIFT (2U) +#define DDRPHY_RDIMMGCR0_SOPERR_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_SOPERR_MASK) >> DDRPHY_RDIMMGCR0_SOPERR_SHIFT) + +/* + * ERRNOREG (R) + * + * Parity Error No Registering: Indicates, if set, that parity error signal from the RDIMM should be passed to the DFI controller without any synchronization or registering. Otherwise, the error signal is synchronized as shown in Figure 4-30 on page 262. + */ +#define DDRPHY_RDIMMGCR0_ERRNOREG_MASK (0x2U) +#define DDRPHY_RDIMMGCR0_ERRNOREG_SHIFT (1U) +#define DDRPHY_RDIMMGCR0_ERRNOREG_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_ERRNOREG_MASK) >> DDRPHY_RDIMMGCR0_ERRNOREG_SHIFT) + +/* + * RDIMM (R) + * + * Registered DIMM: Indicates, if set, that a registered DIMM is used. In this case, the PUB increases the SDRAM write and read latencies (WL/RL) by 1 and also enforces that accesses adhere to RDIMM buffer chip. This only applies to PUB internal SDRAM transactions. Transactions generated by the controller must make its own adjustments to WL/RL when using a registered DIMM. The DCR.NOSRA register bit must be set to ‘1’ if using the standard RDIMM buffer chip so that normal DRAM accesses do not assert multiple chip select bits at the same time. + */ +#define DDRPHY_RDIMMGCR0_RDIMM_MASK (0x1U) +#define DDRPHY_RDIMMGCR0_RDIMM_SHIFT (0U) +#define DDRPHY_RDIMMGCR0_RDIMM_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_RDIMM_MASK) >> DDRPHY_RDIMMGCR0_RDIMM_SHIFT) + +/* Bitfield definition for register: RDIMMGCR1 */ +/* + * CRINIT (R) + * + * Control Registers Initialization Enable: Indicates which RDIMM buffer chip control registers (RC0 to RC15) should be initialized (written) when the PUB is triggered to initialize the buffer chip. A setting of ‘1’ on CRINIT[n] bit means that CRn should be written during initialization. + */ +#define DDRPHY_RDIMMGCR1_CRINIT_MASK (0xFFFF0000UL) +#define DDRPHY_RDIMMGCR1_CRINIT_SHIFT (16U) +#define DDRPHY_RDIMMGCR1_CRINIT_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR1_CRINIT_MASK) >> DDRPHY_RDIMMGCR1_CRINIT_SHIFT) + +/* + * TBCMRD (R) + * + * Command word to command word programming delay: Number of DRAM clock cycles between two RDIMM buffer chip command programming accesses. The value used for tBCMRD is 8 plus the value programmed in these bits, i.e. tBCMRD value ranges from 8 to 15. This parameter corresponds to the buffer chip tMRD parameter. + */ +#define DDRPHY_RDIMMGCR1_TBCMRD_MASK (0x7000U) +#define DDRPHY_RDIMMGCR1_TBCMRD_SHIFT (12U) +#define DDRPHY_RDIMMGCR1_TBCMRD_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR1_TBCMRD_MASK) >> DDRPHY_RDIMMGCR1_TBCMRD_SHIFT) + +/* + * TBCSTAB (R) + * + * Stabilization time: Number of DRAM clock cycles for the RDIMM buffer chip to stabilize. This parameter corresponds to the buffer chip tSTAB parameter. Default value is in decimal format and corresponds to 6us at 533MHz. + */ +#define DDRPHY_RDIMMGCR1_TBCSTAB_MASK (0xFFFU) +#define DDRPHY_RDIMMGCR1_TBCSTAB_SHIFT (0U) +#define DDRPHY_RDIMMGCR1_TBCSTAB_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR1_TBCSTAB_MASK) >> DDRPHY_RDIMMGCR1_TBCSTAB_SHIFT) + +/* Bitfield definition for register: RDIMMCR0 */ +/* + * RC7 (R) + * + * Control Word 7: Reserved, free to use by vendor. + */ +#define DDRPHY_RDIMMCR0_RC7_MASK (0xF0000000UL) +#define DDRPHY_RDIMMCR0_RC7_SHIFT (28U) +#define DDRPHY_RDIMMCR0_RC7_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR0_RC7_MASK) >> DDRPHY_RDIMMCR0_RC7_SHIFT) + +/* + * RC6 (R) + * + * Control Word 6: Reserved, free to use by vendor. + */ +#define DDRPHY_RDIMMCR0_RC6_MASK (0xF000000UL) +#define DDRPHY_RDIMMCR0_RC6_SHIFT (24U) +#define DDRPHY_RDIMMCR0_RC6_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR0_RC6_MASK) >> DDRPHY_RDIMMCR0_RC6_SHIFT) + +/* + * RC5 (R) + * + * Control Word 5 (CK Driver Characteristics Control Word): RC5[1:0] is driver settings for clock Y1, Y1#, Y3, and Y3# outputs, and RC5[3:2] is driver settings for clock Y0, Y0#, Y2, and Y2# outputs. Bit definitions are: + * 00 = Light drive (4 or 5 DRAM loads) + * 01 = Moderate drive (8 or 10 DRAM loads) + * 10 = Strong drive (16 or 20 DRAM loads) + * 11 = Reserved + */ +#define DDRPHY_RDIMMCR0_RC5_MASK (0xF00000UL) +#define DDRPHY_RDIMMCR0_RC5_SHIFT (20U) +#define DDRPHY_RDIMMCR0_RC5_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR0_RC5_MASK) >> DDRPHY_RDIMMCR0_RC5_SHIFT) + +/* + * RC4 (R) + * + * Control Word 4 (Control Signals Driver Characteristics Control Word): RC4[1:0] is driver settings for control A outputs, and RC4[3:2] is driver settings for control B outputs. Bit definitions are: + * 00 = Light drive (4 or 5 DRAM loads) + * 01 = Moderate drive (8 or 10 DRAM loads) + * 10 = Reserved + * 11 = Reserved + */ +#define DDRPHY_RDIMMCR0_RC4_MASK (0xF0000UL) +#define DDRPHY_RDIMMCR0_RC4_SHIFT (16U) +#define DDRPHY_RDIMMCR0_RC4_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR0_RC4_MASK) >> DDRPHY_RDIMMCR0_RC4_SHIFT) + +/* + * RC3 (R) + * + * Control Word 3 (Command/Address Signals Driver Characteristics Control Word): RC3[1:0] is driver settings for command/address A outputs, and RC3[3:2] is driver settings for command/address B outputs. Bit definitions are: + * 00 = Light drive (4 or 5 DRAM loads) + * 01 = Moderate drive (8 or 10 DRAM loads) + * 10 = Strong drive (16 or 20 DRAM loads) + * 11 = Reserved + */ +#define DDRPHY_RDIMMCR0_RC3_MASK (0xF000U) +#define DDRPHY_RDIMMCR0_RC3_SHIFT (12U) +#define DDRPHY_RDIMMCR0_RC3_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR0_RC3_MASK) >> DDRPHY_RDIMMCR0_RC3_SHIFT) + +/* + * RC2 (R) + * + * Control Word 2 (Timing Control Word): Bit definitions are: + * RC2[0]: 0 = Standard (1/2 clock) pre-launch, 1 = Prelaunch controlled by RC12. RC2[1]: 0 = Reserved. + * RC2[2]: 0 = 100 Ohm input bus termination, 1 = 150 Ohm input bus termination. RC2[3]: 0 = Operation frequency band 1, 1 = Test mode frequency band 2. + */ +#define DDRPHY_RDIMMCR0_RC2_MASK (0xF00U) +#define DDRPHY_RDIMMCR0_RC2_SHIFT (8U) +#define DDRPHY_RDIMMCR0_RC2_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR0_RC2_MASK) >> DDRPHY_RDIMMCR0_RC2_SHIFT) + +/* + * RC1 (R) + * + * Control Word 1 (Clock Driver Enable Control Word): Bit definitions are: RC1[0]: 0 = Y0/Y0# clock enabled, 1 = Y0/Y0# clock disabled. + * RC1[1]: 0 = Y1/Y1# clock enabled, 1 = Y1/Y1# clock disabled. RC1[2]: 0 = Y2/Y2# clock enabled, 1 = Y2/Y2# clock disabled. RC1[3]: 0 = Y3/Y3# clock enabled, 1 = Y3/Y3# clock disabled. + */ +#define DDRPHY_RDIMMCR0_RC1_MASK (0xF0U) +#define DDRPHY_RDIMMCR0_RC1_SHIFT (4U) +#define DDRPHY_RDIMMCR0_RC1_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR0_RC1_MASK) >> DDRPHY_RDIMMCR0_RC1_SHIFT) + +/* + * RC0 (R) + * + * Control Word 0 (Global Features Control Word): Bit definitions are: RC0[0]: 0 = Output inversion enabled, 1 = Output inversion disabled. RC0[1]: 0 = Floating outputs disabled, 1 = Floating outputs enabled. RC0[2]: 0 = A outputs enabled, 1 = A outputs disabled. + * RC0[3]: 0 = B outputs enabled, 1 = B outputs disabled. + */ +#define DDRPHY_RDIMMCR0_RC0_MASK (0xFU) +#define DDRPHY_RDIMMCR0_RC0_SHIFT (0U) +#define DDRPHY_RDIMMCR0_RC0_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR0_RC0_MASK) >> DDRPHY_RDIMMCR0_RC0_SHIFT) + +/* Bitfield definition for register: RDIMMCR1 */ +/* + * RC15 (R) + * + * Control Word 15: Reserved for future use. + */ +#define DDRPHY_RDIMMCR1_RC15_MASK (0xF0000000UL) +#define DDRPHY_RDIMMCR1_RC15_SHIFT (28U) +#define DDRPHY_RDIMMCR1_RC15_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR1_RC15_MASK) >> DDRPHY_RDIMMCR1_RC15_SHIFT) + +/* + * RC14 (R) + * + * Control Word 14: Reserved for future use. + */ +#define DDRPHY_RDIMMCR1_RC14_MASK (0xF000000UL) +#define DDRPHY_RDIMMCR1_RC14_SHIFT (24U) +#define DDRPHY_RDIMMCR1_RC14_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR1_RC14_MASK) >> DDRPHY_RDIMMCR1_RC14_SHIFT) + +/* + * RC13 (R) + * + * Control Word 13: Reserved for future use. + */ +#define DDRPHY_RDIMMCR1_RC13_MASK (0xF00000UL) +#define DDRPHY_RDIMMCR1_RC13_SHIFT (20U) +#define DDRPHY_RDIMMCR1_RC13_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR1_RC13_MASK) >> DDRPHY_RDIMMCR1_RC13_SHIFT) + +/* + * RC12 (R) + * + * Control Word 12: Reserved for future use. + */ +#define DDRPHY_RDIMMCR1_RC12_MASK (0xF0000UL) +#define DDRPHY_RDIMMCR1_RC12_SHIFT (16U) +#define DDRPHY_RDIMMCR1_RC12_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR1_RC12_MASK) >> DDRPHY_RDIMMCR1_RC12_SHIFT) + +/* + * RC11 (R) + * + * Control Word 11 (Operating Voltage VDD Control Word): RC10[1:0] is VDD operating voltage setting as follows: 00 = DDR3 1.5V mode + * 01 = DDR3L 1.35V mode + * 10 = Reserved + * 11 = Reserved RC10[3:2]: Reserved. + */ +#define DDRPHY_RDIMMCR1_RC11_MASK (0xF000U) +#define DDRPHY_RDIMMCR1_RC11_SHIFT (12U) +#define DDRPHY_RDIMMCR1_RC11_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR1_RC11_MASK) >> DDRPHY_RDIMMCR1_RC11_SHIFT) + +/* + * RC10 (R) + * + * Control Word 10 (RDIMM Operating Speed Control Word): RC10[2:0] is RDIMM operating speed setting as follows: 000 = DDR3/DDR3L-800 + * 001 = DDR3/DDR3L-1066 + * 010 = DDR3/DDR3L-1333 + * 011 = DDR3/DDR3L-1600 + * 100 = Reserved + * 101 = Reserved + * 110 = Reserved + * 111 = Reserved RC10[3]: Don’t care. + */ +#define DDRPHY_RDIMMCR1_RC10_MASK (0xF00U) +#define DDRPHY_RDIMMCR1_RC10_SHIFT (8U) +#define DDRPHY_RDIMMCR1_RC10_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR1_RC10_MASK) >> DDRPHY_RDIMMCR1_RC10_SHIFT) + +/* + * RC9 (R) + * + * Control Word 9 (Power Saving Settings Control Word): Bit definitions are: RC9[0]: 0 = Floating outputs as defined in RC0, 1 = Weak drive enabled. RC9[1]: 0 = Reserved. + * RC9[2]: 0 = CKE power down with IBT ON, QxODT is a function of DxODT, 1 = CKE power down with IBT off, QxODT held LOW. RC9[2] is valid only when RC9[3] is 1. + * RC9[3]: 0 = CKE power down mode disabled, 1 = CKE power down mode enabled. + */ +#define DDRPHY_RDIMMCR1_RC9_MASK (0xF0U) +#define DDRPHY_RDIMMCR1_RC9_SHIFT (4U) +#define DDRPHY_RDIMMCR1_RC9_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR1_RC9_MASK) >> DDRPHY_RDIMMCR1_RC9_SHIFT) + +/* + * RC8 (R) + * + * Control Word 8 (Additional Input Bus Termination Setting Control Word): RC8[2:0] is Input Bus Termination (IBT) setting as follows: + * 000 = IBT as defined in RC2. 001 = Reserved + * 010 = 200 Ohm + * 011 = Reserved + * 100 = 300 Ohm + * 101 = Reserved + * 110 = Reserved + * 111 = Off + * RC8[3]: 0 = IBT off when MIRROR is HIGH, 1 = IBT on when MIRROR is high + */ +#define DDRPHY_RDIMMCR1_RC8_MASK (0xFU) +#define DDRPHY_RDIMMCR1_RC8_SHIFT (0U) +#define DDRPHY_RDIMMCR1_RC8_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR1_RC8_MASK) >> DDRPHY_RDIMMCR1_RC8_SHIFT) + +/* Bitfield definition for register: DCUAR */ +/* + * ATYPE (R/W) + * + * Access Type: Specifies the type of access to be performed using this address. Valid values are: + * 0 = Write access 1 = Read access + */ +#define DDRPHY_DCUAR_ATYPE_MASK (0x800U) +#define DDRPHY_DCUAR_ATYPE_SHIFT (11U) +#define DDRPHY_DCUAR_ATYPE_SET(x) (((uint32_t)(x) << DDRPHY_DCUAR_ATYPE_SHIFT) & DDRPHY_DCUAR_ATYPE_MASK) +#define DDRPHY_DCUAR_ATYPE_GET(x) (((uint32_t)(x) & DDRPHY_DCUAR_ATYPE_MASK) >> DDRPHY_DCUAR_ATYPE_SHIFT) + +/* + * INCA (R/W) + * + * Increment Address: Specifies, if set, that the cache address specified in WADDR and SADDR should be automatically incremented after each access of the cache. The increment happens in such a way that all the slices of a selected word are first accessed before going to the next word. + */ +#define DDRPHY_DCUAR_INCA_MASK (0x400U) +#define DDRPHY_DCUAR_INCA_SHIFT (10U) +#define DDRPHY_DCUAR_INCA_SET(x) (((uint32_t)(x) << DDRPHY_DCUAR_INCA_SHIFT) & DDRPHY_DCUAR_INCA_MASK) +#define DDRPHY_DCUAR_INCA_GET(x) (((uint32_t)(x) & DDRPHY_DCUAR_INCA_MASK) >> DDRPHY_DCUAR_INCA_SHIFT) + +/* + * CSEL (R/W) + * + * Cache Select: Selects the cache to be accessed. Valid values are: 00 = Command cache + * 01 = Expected data cache 10 = Read data cache + * 11 = Reserved + */ +#define DDRPHY_DCUAR_CSEL_MASK (0x300U) +#define DDRPHY_DCUAR_CSEL_SHIFT (8U) +#define DDRPHY_DCUAR_CSEL_SET(x) (((uint32_t)(x) << DDRPHY_DCUAR_CSEL_SHIFT) & DDRPHY_DCUAR_CSEL_MASK) +#define DDRPHY_DCUAR_CSEL_GET(x) (((uint32_t)(x) & DDRPHY_DCUAR_CSEL_MASK) >> DDRPHY_DCUAR_CSEL_SHIFT) + +/* + * CSADDR (R/W) + * + * Cache Slice Address: Address of the cache slice to be accessed. + */ +#define DDRPHY_DCUAR_CSADDR_MASK (0xF0U) +#define DDRPHY_DCUAR_CSADDR_SHIFT (4U) +#define DDRPHY_DCUAR_CSADDR_SET(x) (((uint32_t)(x) << DDRPHY_DCUAR_CSADDR_SHIFT) & DDRPHY_DCUAR_CSADDR_MASK) +#define DDRPHY_DCUAR_CSADDR_GET(x) (((uint32_t)(x) & DDRPHY_DCUAR_CSADDR_MASK) >> DDRPHY_DCUAR_CSADDR_SHIFT) + +/* + * CWADDR (R/W) + * + * Cache Word Address: Address of the cache word to be accessed. + */ +#define DDRPHY_DCUAR_CWADDR_MASK (0xFU) +#define DDRPHY_DCUAR_CWADDR_SHIFT (0U) +#define DDRPHY_DCUAR_CWADDR_SET(x) (((uint32_t)(x) << DDRPHY_DCUAR_CWADDR_SHIFT) & DDRPHY_DCUAR_CWADDR_MASK) +#define DDRPHY_DCUAR_CWADDR_GET(x) (((uint32_t)(x) & DDRPHY_DCUAR_CWADDR_MASK) >> DDRPHY_DCUAR_CWADDR_SHIFT) + +/* Bitfield definition for register: DCUDR */ +/* + * CDATA (R/W) + * + * Cache Data: Data to be written to or read from a cache. This data corresponds to the cache word slice specified by the DCU Address Register. + */ +#define DDRPHY_DCUDR_CDATA_MASK (0xFFFFFFFFUL) +#define DDRPHY_DCUDR_CDATA_SHIFT (0U) +#define DDRPHY_DCUDR_CDATA_SET(x) (((uint32_t)(x) << DDRPHY_DCUDR_CDATA_SHIFT) & DDRPHY_DCUDR_CDATA_MASK) +#define DDRPHY_DCUDR_CDATA_GET(x) (((uint32_t)(x) & DDRPHY_DCUDR_CDATA_MASK) >> DDRPHY_DCUDR_CDATA_SHIFT) + +/* Bitfield definition for register: DCURR */ +/* + * XCEN (R/W) + * + * Expected Compare Enable: Indicates, if set, that read data coming back from the SDRAM should be should be compared with the expected data. + */ +#define DDRPHY_DCURR_XCEN_MASK (0x800000UL) +#define DDRPHY_DCURR_XCEN_SHIFT (23U) +#define DDRPHY_DCURR_XCEN_SET(x) (((uint32_t)(x) << DDRPHY_DCURR_XCEN_SHIFT) & DDRPHY_DCURR_XCEN_MASK) +#define DDRPHY_DCURR_XCEN_GET(x) (((uint32_t)(x) & DDRPHY_DCURR_XCEN_MASK) >> DDRPHY_DCURR_XCEN_SHIFT) + +/* + * RCEN (R/W) + * + * Read Capture Enable: Indicates, if set, that read data coming back from the SDRAM should be captured into the read data cache. + */ +#define DDRPHY_DCURR_RCEN_MASK (0x400000UL) +#define DDRPHY_DCURR_RCEN_SHIFT (22U) +#define DDRPHY_DCURR_RCEN_SET(x) (((uint32_t)(x) << DDRPHY_DCURR_RCEN_SHIFT) & DDRPHY_DCURR_RCEN_MASK) +#define DDRPHY_DCURR_RCEN_GET(x) (((uint32_t)(x) & DDRPHY_DCURR_RCEN_MASK) >> DDRPHY_DCURR_RCEN_SHIFT) + +/* + * SCOF (R/W) + * + * Stop Capture On Full: Specifies, if set, that the capture of read data should stop when the capture cache is full. + */ +#define DDRPHY_DCURR_SCOF_MASK (0x200000UL) +#define DDRPHY_DCURR_SCOF_SHIFT (21U) +#define DDRPHY_DCURR_SCOF_SET(x) (((uint32_t)(x) << DDRPHY_DCURR_SCOF_SHIFT) & DDRPHY_DCURR_SCOF_MASK) +#define DDRPHY_DCURR_SCOF_GET(x) (((uint32_t)(x) & DDRPHY_DCURR_SCOF_MASK) >> DDRPHY_DCURR_SCOF_SHIFT) + +/* + * SONF (R/W) + * + * Stop On Nth Fail: Specifies, if set, that the execution of commands and the capture of read data should stop when there are N read data failures. The number of failures is specified by NFAIL. Otherwise commands execute until the end of the program or until manually stopped using a STOP command. + */ +#define DDRPHY_DCURR_SONF_MASK (0x100000UL) +#define DDRPHY_DCURR_SONF_SHIFT (20U) +#define DDRPHY_DCURR_SONF_SET(x) (((uint32_t)(x) << DDRPHY_DCURR_SONF_SHIFT) & DDRPHY_DCURR_SONF_MASK) +#define DDRPHY_DCURR_SONF_GET(x) (((uint32_t)(x) & DDRPHY_DCURR_SONF_MASK) >> DDRPHY_DCURR_SONF_SHIFT) + +/* + * NFAIL (R/W) + * + * Number of Failures: Specifies the number of failures after which the execution of commands and the capture of read data should stop if SONF bit of this register is set. Execution of commands and the capture of read data will stop after (NFAIL+1) failures if SONF is set. + * Valid values are from 0 to 254. + */ +#define DDRPHY_DCURR_NFAIL_MASK (0xFF000UL) +#define DDRPHY_DCURR_NFAIL_SHIFT (12U) +#define DDRPHY_DCURR_NFAIL_SET(x) (((uint32_t)(x) << DDRPHY_DCURR_NFAIL_SHIFT) & DDRPHY_DCURR_NFAIL_MASK) +#define DDRPHY_DCURR_NFAIL_GET(x) (((uint32_t)(x) & DDRPHY_DCURR_NFAIL_MASK) >> DDRPHY_DCURR_NFAIL_SHIFT) + +/* + * EADDR (R/W) + * + * End Address: Cache word address where the execution of command should end. + */ +#define DDRPHY_DCURR_EADDR_MASK (0xF00U) +#define DDRPHY_DCURR_EADDR_SHIFT (8U) +#define DDRPHY_DCURR_EADDR_SET(x) (((uint32_t)(x) << DDRPHY_DCURR_EADDR_SHIFT) & DDRPHY_DCURR_EADDR_MASK) +#define DDRPHY_DCURR_EADDR_GET(x) (((uint32_t)(x) & DDRPHY_DCURR_EADDR_MASK) >> DDRPHY_DCURR_EADDR_SHIFT) + +/* + * SADDR (R/W) + * + * Start Address: Cache word address where the execution of commands should begin. + */ +#define DDRPHY_DCURR_SADDR_MASK (0xF0U) +#define DDRPHY_DCURR_SADDR_SHIFT (4U) +#define DDRPHY_DCURR_SADDR_SET(x) (((uint32_t)(x) << DDRPHY_DCURR_SADDR_SHIFT) & DDRPHY_DCURR_SADDR_MASK) +#define DDRPHY_DCURR_SADDR_GET(x) (((uint32_t)(x) & DDRPHY_DCURR_SADDR_MASK) >> DDRPHY_DCURR_SADDR_SHIFT) + +/* + * DINST (R/W) + * + * DCU Instruction: Selects the DCU command to be executed: Valid values are: 0000 = NOP: No operation + * 0001 = Run: Triggers the execution of commands in the command cache. 0010 = Stop: Stops the execution of commands in the command cache. + * 0011 = Stop Loop: Stops the execution of an infinite loop in the command cache. 0100 = Reset: Resets all DCU run time registers. See “DCU Status” on page 255 for details. + * 0101 – 1111 Reserved + */ +#define DDRPHY_DCURR_DINST_MASK (0xFU) +#define DDRPHY_DCURR_DINST_SHIFT (0U) +#define DDRPHY_DCURR_DINST_SET(x) (((uint32_t)(x) << DDRPHY_DCURR_DINST_SHIFT) & DDRPHY_DCURR_DINST_MASK) +#define DDRPHY_DCURR_DINST_GET(x) (((uint32_t)(x) & DDRPHY_DCURR_DINST_MASK) >> DDRPHY_DCURR_DINST_SHIFT) + +/* Bitfield definition for register: DCULR */ +/* + * XLEADDR (R/W) + * + * Expected Data Loop End Address: The last expected data cache word address that contains valid expected data. Expected data should looped between 0 and this address. + * XLEADDR field uses only the following bits based on the cache depth: + * DCU expected data cache = 4, XLEADDR[1:0] + * DCU expected data cache = 8, XLEADDR[2:0] + * DCU expected data cache = 16, XLEADDR[3:0] + */ +#define DDRPHY_DCULR_XLEADDR_MASK (0xF0000000UL) +#define DDRPHY_DCULR_XLEADDR_SHIFT (28U) +#define DDRPHY_DCULR_XLEADDR_SET(x) (((uint32_t)(x) << DDRPHY_DCULR_XLEADDR_SHIFT) & DDRPHY_DCULR_XLEADDR_MASK) +#define DDRPHY_DCULR_XLEADDR_GET(x) (((uint32_t)(x) & DDRPHY_DCULR_XLEADDR_MASK) >> DDRPHY_DCULR_XLEADDR_SHIFT) + +/* + * IDA (R/W) + * + * Increment DRAM Address: Indicates, if set, that DRAM addresses should be incremented every time a DRAM read/write command inside the loop is executed. + */ +#define DDRPHY_DCULR_IDA_MASK (0x20000UL) +#define DDRPHY_DCULR_IDA_SHIFT (17U) +#define DDRPHY_DCULR_IDA_SET(x) (((uint32_t)(x) << DDRPHY_DCULR_IDA_SHIFT) & DDRPHY_DCULR_IDA_MASK) +#define DDRPHY_DCULR_IDA_GET(x) (((uint32_t)(x) & DDRPHY_DCULR_IDA_MASK) >> DDRPHY_DCULR_IDA_SHIFT) + +/* + * LINF (R/W) + * + * Loop Infinite: Indicates, if set, that the loop should be executed indefinitely until stopped by the STOP command. Otherwise the loop is execute LCNT times. + */ +#define DDRPHY_DCULR_LINF_MASK (0x10000UL) +#define DDRPHY_DCULR_LINF_SHIFT (16U) +#define DDRPHY_DCULR_LINF_SET(x) (((uint32_t)(x) << DDRPHY_DCULR_LINF_SHIFT) & DDRPHY_DCULR_LINF_MASK) +#define DDRPHY_DCULR_LINF_GET(x) (((uint32_t)(x) & DDRPHY_DCULR_LINF_MASK) >> DDRPHY_DCULR_LINF_SHIFT) + +/* + * LCNT (R/W) + * + * Loop Count: The number of times that the loop should be executed if LINF is not set. + */ +#define DDRPHY_DCULR_LCNT_MASK (0xFF00U) +#define DDRPHY_DCULR_LCNT_SHIFT (8U) +#define DDRPHY_DCULR_LCNT_SET(x) (((uint32_t)(x) << DDRPHY_DCULR_LCNT_SHIFT) & DDRPHY_DCULR_LCNT_MASK) +#define DDRPHY_DCULR_LCNT_GET(x) (((uint32_t)(x) & DDRPHY_DCULR_LCNT_MASK) >> DDRPHY_DCULR_LCNT_SHIFT) + +/* + * LEADDR (R/W) + * + * Loop End Address: Command cache word address where the loop should end. + */ +#define DDRPHY_DCULR_LEADDR_MASK (0xF0U) +#define DDRPHY_DCULR_LEADDR_SHIFT (4U) +#define DDRPHY_DCULR_LEADDR_SET(x) (((uint32_t)(x) << DDRPHY_DCULR_LEADDR_SHIFT) & DDRPHY_DCULR_LEADDR_MASK) +#define DDRPHY_DCULR_LEADDR_GET(x) (((uint32_t)(x) & DDRPHY_DCULR_LEADDR_MASK) >> DDRPHY_DCULR_LEADDR_SHIFT) + +/* + * LSADDR (R/W) + * + * Loop Start Address: Command cache word address where the loop should start. + */ +#define DDRPHY_DCULR_LSADDR_MASK (0xFU) +#define DDRPHY_DCULR_LSADDR_SHIFT (0U) +#define DDRPHY_DCULR_LSADDR_SET(x) (((uint32_t)(x) << DDRPHY_DCULR_LSADDR_SHIFT) & DDRPHY_DCULR_LSADDR_MASK) +#define DDRPHY_DCULR_LSADDR_GET(x) (((uint32_t)(x) & DDRPHY_DCULR_LSADDR_MASK) >> DDRPHY_DCULR_LSADDR_SHIFT) + +/* Bitfield definition for register: DCUGCR */ +/* + * RCSW (R/W) + * + * Read Capture Start Word: The capture and compare of read data should start after Nth word. For example setting this value to 12 will skip the first 12 read data. + */ +#define DDRPHY_DCUGCR_RCSW_MASK (0xFFFFU) +#define DDRPHY_DCUGCR_RCSW_SHIFT (0U) +#define DDRPHY_DCUGCR_RCSW_SET(x) (((uint32_t)(x) << DDRPHY_DCUGCR_RCSW_SHIFT) & DDRPHY_DCUGCR_RCSW_MASK) +#define DDRPHY_DCUGCR_RCSW_GET(x) (((uint32_t)(x) & DDRPHY_DCUGCR_RCSW_MASK) >> DDRPHY_DCUGCR_RCSW_SHIFT) + +/* Bitfield definition for register: DCUTPR */ +/* + * TDCUT3 (R/W) + * + * DCU Generic Timing Parameter 3 + */ +#define DDRPHY_DCUTPR_TDCUT3_MASK (0xFF000000UL) +#define DDRPHY_DCUTPR_TDCUT3_SHIFT (24U) +#define DDRPHY_DCUTPR_TDCUT3_SET(x) (((uint32_t)(x) << DDRPHY_DCUTPR_TDCUT3_SHIFT) & DDRPHY_DCUTPR_TDCUT3_MASK) +#define DDRPHY_DCUTPR_TDCUT3_GET(x) (((uint32_t)(x) & DDRPHY_DCUTPR_TDCUT3_MASK) >> DDRPHY_DCUTPR_TDCUT3_SHIFT) + +/* + * TDCUT2 (R/W) + * + * DCU Generic Timing Parameter 2 + */ +#define DDRPHY_DCUTPR_TDCUT2_MASK (0xFF0000UL) +#define DDRPHY_DCUTPR_TDCUT2_SHIFT (16U) +#define DDRPHY_DCUTPR_TDCUT2_SET(x) (((uint32_t)(x) << DDRPHY_DCUTPR_TDCUT2_SHIFT) & DDRPHY_DCUTPR_TDCUT2_MASK) +#define DDRPHY_DCUTPR_TDCUT2_GET(x) (((uint32_t)(x) & DDRPHY_DCUTPR_TDCUT2_MASK) >> DDRPHY_DCUTPR_TDCUT2_SHIFT) + +/* + * TDCUT1 (R/W) + * + * DCU Generic Timing Parameter 1 + */ +#define DDRPHY_DCUTPR_TDCUT1_MASK (0xFF00U) +#define DDRPHY_DCUTPR_TDCUT1_SHIFT (8U) +#define DDRPHY_DCUTPR_TDCUT1_SET(x) (((uint32_t)(x) << DDRPHY_DCUTPR_TDCUT1_SHIFT) & DDRPHY_DCUTPR_TDCUT1_MASK) +#define DDRPHY_DCUTPR_TDCUT1_GET(x) (((uint32_t)(x) & DDRPHY_DCUTPR_TDCUT1_MASK) >> DDRPHY_DCUTPR_TDCUT1_SHIFT) + +/* + * TDCUT0 (R/W) + * + * DCU Generic Timing Parameter 0 + */ +#define DDRPHY_DCUTPR_TDCUT0_MASK (0xFFU) +#define DDRPHY_DCUTPR_TDCUT0_SHIFT (0U) +#define DDRPHY_DCUTPR_TDCUT0_SET(x) (((uint32_t)(x) << DDRPHY_DCUTPR_TDCUT0_SHIFT) & DDRPHY_DCUTPR_TDCUT0_MASK) +#define DDRPHY_DCUTPR_TDCUT0_GET(x) (((uint32_t)(x) & DDRPHY_DCUTPR_TDCUT0_MASK) >> DDRPHY_DCUTPR_TDCUT0_SHIFT) + +/* Bitfield definition for register: DCUSR0 */ +/* + * CFULL (R) + * + * Capture Full: Indicates, if set, that the capture cache is full. + */ +#define DDRPHY_DCUSR0_CFULL_MASK (0x4U) +#define DDRPHY_DCUSR0_CFULL_SHIFT (2U) +#define DDRPHY_DCUSR0_CFULL_GET(x) (((uint32_t)(x) & DDRPHY_DCUSR0_CFULL_MASK) >> DDRPHY_DCUSR0_CFULL_SHIFT) + +/* + * CFAIL (R) + * + * Capture Fail: Indicates, if set, that at least one read data word has failed. + */ +#define DDRPHY_DCUSR0_CFAIL_MASK (0x2U) +#define DDRPHY_DCUSR0_CFAIL_SHIFT (1U) +#define DDRPHY_DCUSR0_CFAIL_GET(x) (((uint32_t)(x) & DDRPHY_DCUSR0_CFAIL_MASK) >> DDRPHY_DCUSR0_CFAIL_SHIFT) + +/* + * RDONE (R) + * + * Run Done: Indicates, if set, that the DCU has finished executing the commands in the command cache. This bit is also set to indicate that a STOP command has successfully been executed and command execution has stopped. + */ +#define DDRPHY_DCUSR0_RDONE_MASK (0x1U) +#define DDRPHY_DCUSR0_RDONE_SHIFT (0U) +#define DDRPHY_DCUSR0_RDONE_GET(x) (((uint32_t)(x) & DDRPHY_DCUSR0_RDONE_MASK) >> DDRPHY_DCUSR0_RDONE_SHIFT) + +/* Bitfield definition for register: DCUSR1 */ +/* + * LPCNT (R) + * + * Loop Count: Indicates the value of the loop count. This is useful when the program has stopped because of failures to assess how many reads were executed before first fail. + */ +#define DDRPHY_DCUSR1_LPCNT_MASK (0xFF000000UL) +#define DDRPHY_DCUSR1_LPCNT_SHIFT (24U) +#define DDRPHY_DCUSR1_LPCNT_GET(x) (((uint32_t)(x) & DDRPHY_DCUSR1_LPCNT_MASK) >> DDRPHY_DCUSR1_LPCNT_SHIFT) + +/* + * FLCNT (R) + * + * Fail Count: Number of read words that have failed. + */ +#define DDRPHY_DCUSR1_FLCNT_MASK (0xFF0000UL) +#define DDRPHY_DCUSR1_FLCNT_SHIFT (16U) +#define DDRPHY_DCUSR1_FLCNT_GET(x) (((uint32_t)(x) & DDRPHY_DCUSR1_FLCNT_MASK) >> DDRPHY_DCUSR1_FLCNT_SHIFT) + +/* + * RDCNT (R) + * + * Read Count: Number of read words returned from the SDRAM. + */ +#define DDRPHY_DCUSR1_RDCNT_MASK (0xFFFFU) +#define DDRPHY_DCUSR1_RDCNT_SHIFT (0U) +#define DDRPHY_DCUSR1_RDCNT_GET(x) (((uint32_t)(x) & DDRPHY_DCUSR1_RDCNT_MASK) >> DDRPHY_DCUSR1_RDCNT_SHIFT) + +/* Bitfield definition for register: BISTRR */ +/* + * BCCSEL (R/W) + * + * BIST Clock Cycle Select: Selects the clock numbers on which the AC loopback data is written into the FIFO. Data is written into the loopback FIFO once every four clock cycles. Valid values are: + * 00 = Clock cycle 0, 4, 8, 12, etc. + * 01 = Clock cycle 1, 5, 9, 13, etc. + * 10 = Clock cycle 2, 6, 10, 14, etc. + * 11 = Clock cycle 3, 7, 11, 15, etc. + */ +#define DDRPHY_BISTRR_BCCSEL_MASK (0x6000000UL) +#define DDRPHY_BISTRR_BCCSEL_SHIFT (25U) +#define DDRPHY_BISTRR_BCCSEL_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_BCCSEL_SHIFT) & DDRPHY_BISTRR_BCCSEL_MASK) +#define DDRPHY_BISTRR_BCCSEL_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_BCCSEL_MASK) >> DDRPHY_BISTRR_BCCSEL_SHIFT) + +/* + * BCKSEL (R/W) + * + * BIST CK Select: Selects the CK that should be used to register the AC loopback signals from the I/Os. Valid values are: + * 00 = CK[0] + * 01 = CK[1] + * 10 = CK[2] + * 11 = Reserved + */ +#define DDRPHY_BISTRR_BCKSEL_MASK (0x1800000UL) +#define DDRPHY_BISTRR_BCKSEL_SHIFT (23U) +#define DDRPHY_BISTRR_BCKSEL_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_BCKSEL_SHIFT) & DDRPHY_BISTRR_BCKSEL_MASK) +#define DDRPHY_BISTRR_BCKSEL_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_BCKSEL_MASK) >> DDRPHY_BISTRR_BCKSEL_SHIFT) + +/* + * BDXSEL (R/W) + * + * BIST DATX8 Select: Select the byte lane for comparison of loopback/read data. Valid values are 0 to 8. + */ +#define DDRPHY_BISTRR_BDXSEL_MASK (0x780000UL) +#define DDRPHY_BISTRR_BDXSEL_SHIFT (19U) +#define DDRPHY_BISTRR_BDXSEL_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_BDXSEL_SHIFT) & DDRPHY_BISTRR_BDXSEL_MASK) +#define DDRPHY_BISTRR_BDXSEL_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_BDXSEL_MASK) >> DDRPHY_BISTRR_BDXSEL_SHIFT) + +/* + * BDPAT (R/W) + * + * BIST Data Pattern: Selects the data pattern used during BIST. Valid values are: 00 = Walking 0 + * 01 = Walking 1 + * 10 = LFSR-based pseudo-random + * 11 = User programmable (Not valid for AC loopback). + */ +#define DDRPHY_BISTRR_BDPAT_MASK (0x60000UL) +#define DDRPHY_BISTRR_BDPAT_SHIFT (17U) +#define DDRPHY_BISTRR_BDPAT_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_BDPAT_SHIFT) & DDRPHY_BISTRR_BDPAT_MASK) +#define DDRPHY_BISTRR_BDPAT_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_BDPAT_MASK) >> DDRPHY_BISTRR_BDPAT_SHIFT) + +/* + * BDMEN (R/W) + * + * BIST Data Mask Enable: Enables, if set, that the data mask BIST should be included in the BIST run, i.e. data pattern generated and loopback data compared. This is valid only for loopback mode. + */ +#define DDRPHY_BISTRR_BDMEN_MASK (0x10000UL) +#define DDRPHY_BISTRR_BDMEN_SHIFT (16U) +#define DDRPHY_BISTRR_BDMEN_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_BDMEN_SHIFT) & DDRPHY_BISTRR_BDMEN_MASK) +#define DDRPHY_BISTRR_BDMEN_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_BDMEN_MASK) >> DDRPHY_BISTRR_BDMEN_SHIFT) + +/* + * BACEN (R/W) + * + * BIST AC Enable: Enables the running of BIST on the address/command lane PHY. This bit is exclusive with BDXEN, i.e. both cannot be set to ‘1’ at the same time. + */ +#define DDRPHY_BISTRR_BACEN_MASK (0x8000U) +#define DDRPHY_BISTRR_BACEN_SHIFT (15U) +#define DDRPHY_BISTRR_BACEN_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_BACEN_SHIFT) & DDRPHY_BISTRR_BACEN_MASK) +#define DDRPHY_BISTRR_BACEN_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_BACEN_MASK) >> DDRPHY_BISTRR_BACEN_SHIFT) + +/* + * BDXEN (R/W) + * + * BIST DATX8 Enable: Enables the running of BIST on the data byte lane PHYs. This bit is exclusive with BACEN, i.e. both cannot be set to ‘1’ at the same time. + */ +#define DDRPHY_BISTRR_BDXEN_MASK (0x4000U) +#define DDRPHY_BISTRR_BDXEN_SHIFT (14U) +#define DDRPHY_BISTRR_BDXEN_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_BDXEN_SHIFT) & DDRPHY_BISTRR_BDXEN_MASK) +#define DDRPHY_BISTRR_BDXEN_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_BDXEN_MASK) >> DDRPHY_BISTRR_BDXEN_SHIFT) + +/* + * BSONF (R/W) + * + * BIST Stop On Nth Fail: Specifies, if set, that the BIST should stop when an nth data word or address/command comparison error has been encountered. + */ +#define DDRPHY_BISTRR_BSONF_MASK (0x2000U) +#define DDRPHY_BISTRR_BSONF_SHIFT (13U) +#define DDRPHY_BISTRR_BSONF_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_BSONF_SHIFT) & DDRPHY_BISTRR_BSONF_MASK) +#define DDRPHY_BISTRR_BSONF_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_BSONF_MASK) >> DDRPHY_BISTRR_BSONF_SHIFT) + +/* + * NFAIL (R/W) + * + * Number of Failures: Specifies the number of failures after which the execution of commands and the capture of read data should stop if BSONF bit of this register is set. Execution of commands and the capture of read data will stop after (NFAIL+1) failures if BSONF is set. + */ +#define DDRPHY_BISTRR_NFAIL_MASK (0x1FE0U) +#define DDRPHY_BISTRR_NFAIL_SHIFT (5U) +#define DDRPHY_BISTRR_NFAIL_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_NFAIL_SHIFT) & DDRPHY_BISTRR_NFAIL_MASK) +#define DDRPHY_BISTRR_NFAIL_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_NFAIL_MASK) >> DDRPHY_BISTRR_NFAIL_SHIFT) + +/* + * BINF (R/W) + * + * BIST Infinite Run: Specifies, if set, that the BIST should be run indefinitely until when it is either stopped or a failure has been encountered. Otherwise BIST is run until number of BIST words specified in the BISTWCR register has been generated. + */ +#define DDRPHY_BISTRR_BINF_MASK (0x10U) +#define DDRPHY_BISTRR_BINF_SHIFT (4U) +#define DDRPHY_BISTRR_BINF_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_BINF_SHIFT) & DDRPHY_BISTRR_BINF_MASK) +#define DDRPHY_BISTRR_BINF_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_BINF_MASK) >> DDRPHY_BISTRR_BINF_SHIFT) + +/* + * BMODE (R/W) + * + * BIST Mode: Selects the mode in which BIST is run. Valid values are: + * 0 = Loopback mode: Address, commands and data loop back at the PHY I/Os. + * 1 = DRAM mode: Address, commands and data go to DRAM for normal memory accesses. + */ +#define DDRPHY_BISTRR_BMODE_MASK (0x8U) +#define DDRPHY_BISTRR_BMODE_SHIFT (3U) +#define DDRPHY_BISTRR_BMODE_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_BMODE_SHIFT) & DDRPHY_BISTRR_BMODE_MASK) +#define DDRPHY_BISTRR_BMODE_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_BMODE_MASK) >> DDRPHY_BISTRR_BMODE_SHIFT) + +/* + * BINST (R/W) + * + * BIST Instruction: Selects the BIST instruction to be executed: Valid values are: 000 = NOP: No operation + * 001 = Run: Triggers the running of the BIST. 010 = Stop: Stops the running of the BIST. + * 011 = Reset: Resets all BIST run-time registers, such as error counters. 100 – 111 Reserved + */ +#define DDRPHY_BISTRR_BINST_MASK (0x7U) +#define DDRPHY_BISTRR_BINST_SHIFT (0U) +#define DDRPHY_BISTRR_BINST_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_BINST_SHIFT) & DDRPHY_BISTRR_BINST_MASK) +#define DDRPHY_BISTRR_BINST_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_BINST_MASK) >> DDRPHY_BISTRR_BINST_SHIFT) + +/* Bitfield definition for register: BISTWCR */ +/* + * BWCNT (R/W) + * + * BIST Word Count: Indicates the number of words to generate during BIST. This must be a multiple of DRAM burst length (BL) divided by 2, e.g. for BL=8, valid values are 4, 8, 12, 16, and so on. + */ +#define DDRPHY_BISTWCR_BWCNT_MASK (0xFFFFU) +#define DDRPHY_BISTWCR_BWCNT_SHIFT (0U) +#define DDRPHY_BISTWCR_BWCNT_SET(x) (((uint32_t)(x) << DDRPHY_BISTWCR_BWCNT_SHIFT) & DDRPHY_BISTWCR_BWCNT_MASK) +#define DDRPHY_BISTWCR_BWCNT_GET(x) (((uint32_t)(x) & DDRPHY_BISTWCR_BWCNT_MASK) >> DDRPHY_BISTWCR_BWCNT_SHIFT) + +/* Bitfield definition for register: BISTMSKR0 */ +/* + * ODTMSK (R/W) + * + * Mask bit for each of the up to 4 ODT bits. + */ +#define DDRPHY_BISTMSKR0_ODTMSK_MASK (0xF0000000UL) +#define DDRPHY_BISTMSKR0_ODTMSK_SHIFT (28U) +#define DDRPHY_BISTMSKR0_ODTMSK_SET(x) (((uint32_t)(x) << DDRPHY_BISTMSKR0_ODTMSK_SHIFT) & DDRPHY_BISTMSKR0_ODTMSK_MASK) +#define DDRPHY_BISTMSKR0_ODTMSK_GET(x) (((uint32_t)(x) & DDRPHY_BISTMSKR0_ODTMSK_MASK) >> DDRPHY_BISTMSKR0_ODTMSK_SHIFT) + +/* + * CSMSK (R/W) + * + * Mask bit for each of the up to 4 CS# bits. + */ +#define DDRPHY_BISTMSKR0_CSMSK_MASK (0xF000000UL) +#define DDRPHY_BISTMSKR0_CSMSK_SHIFT (24U) +#define DDRPHY_BISTMSKR0_CSMSK_SET(x) (((uint32_t)(x) << DDRPHY_BISTMSKR0_CSMSK_SHIFT) & DDRPHY_BISTMSKR0_CSMSK_MASK) +#define DDRPHY_BISTMSKR0_CSMSK_GET(x) (((uint32_t)(x) & DDRPHY_BISTMSKR0_CSMSK_MASK) >> DDRPHY_BISTMSKR0_CSMSK_SHIFT) + +/* + * CKEMSK (R/W) + * + * Mask bit for each of the up to 4 CKE bits. + */ +#define DDRPHY_BISTMSKR0_CKEMSK_MASK (0xF00000UL) +#define DDRPHY_BISTMSKR0_CKEMSK_SHIFT (20U) +#define DDRPHY_BISTMSKR0_CKEMSK_SET(x) (((uint32_t)(x) << DDRPHY_BISTMSKR0_CKEMSK_SHIFT) & DDRPHY_BISTMSKR0_CKEMSK_MASK) +#define DDRPHY_BISTMSKR0_CKEMSK_GET(x) (((uint32_t)(x) & DDRPHY_BISTMSKR0_CKEMSK_MASK) >> DDRPHY_BISTMSKR0_CKEMSK_SHIFT) + +/* + * WEMSK (R/W) + * + * Mask bit for the WE#. + */ +#define DDRPHY_BISTMSKR0_WEMSK_MASK (0x80000UL) +#define DDRPHY_BISTMSKR0_WEMSK_SHIFT (19U) +#define DDRPHY_BISTMSKR0_WEMSK_SET(x) (((uint32_t)(x) << DDRPHY_BISTMSKR0_WEMSK_SHIFT) & DDRPHY_BISTMSKR0_WEMSK_MASK) +#define DDRPHY_BISTMSKR0_WEMSK_GET(x) (((uint32_t)(x) & DDRPHY_BISTMSKR0_WEMSK_MASK) >> DDRPHY_BISTMSKR0_WEMSK_SHIFT) + +/* + * BAMSK (R/W) + * + * Mask bit for each of the up to 3 bank address bits. + */ +#define DDRPHY_BISTMSKR0_BAMSK_MASK (0x70000UL) +#define DDRPHY_BISTMSKR0_BAMSK_SHIFT (16U) +#define DDRPHY_BISTMSKR0_BAMSK_SET(x) (((uint32_t)(x) << DDRPHY_BISTMSKR0_BAMSK_SHIFT) & DDRPHY_BISTMSKR0_BAMSK_MASK) +#define DDRPHY_BISTMSKR0_BAMSK_GET(x) (((uint32_t)(x) & DDRPHY_BISTMSKR0_BAMSK_MASK) >> DDRPHY_BISTMSKR0_BAMSK_SHIFT) + +/* + * AMSK (R/W) + * + * Mask bit for each of the up to 16 address bits. + */ +#define DDRPHY_BISTMSKR0_AMSK_MASK (0xFFFFU) +#define DDRPHY_BISTMSKR0_AMSK_SHIFT (0U) +#define DDRPHY_BISTMSKR0_AMSK_SET(x) (((uint32_t)(x) << DDRPHY_BISTMSKR0_AMSK_SHIFT) & DDRPHY_BISTMSKR0_AMSK_MASK) +#define DDRPHY_BISTMSKR0_AMSK_GET(x) (((uint32_t)(x) & DDRPHY_BISTMSKR0_AMSK_MASK) >> DDRPHY_BISTMSKR0_AMSK_SHIFT) + +/* Bitfield definition for register: BISTMSKR1 */ +/* + * DMMSK (R/W) + * + * Mask bit for the data mask (DM) bit. + */ +#define DDRPHY_BISTMSKR1_DMMSK_MASK (0xF0000000UL) +#define DDRPHY_BISTMSKR1_DMMSK_SHIFT (28U) +#define DDRPHY_BISTMSKR1_DMMSK_SET(x) (((uint32_t)(x) << DDRPHY_BISTMSKR1_DMMSK_SHIFT) & DDRPHY_BISTMSKR1_DMMSK_MASK) +#define DDRPHY_BISTMSKR1_DMMSK_GET(x) (((uint32_t)(x) & DDRPHY_BISTMSKR1_DMMSK_MASK) >> DDRPHY_BISTMSKR1_DMMSK_SHIFT) + +/* + * PARMSK (R/W) + * + * Mask bit for the PAR_IN. Only for DIMM parity support and only if the design is compiled for less than 3 ranks. + */ +#define DDRPHY_BISTMSKR1_PARMSK_MASK (0x8000000UL) +#define DDRPHY_BISTMSKR1_PARMSK_SHIFT (27U) +#define DDRPHY_BISTMSKR1_PARMSK_SET(x) (((uint32_t)(x) << DDRPHY_BISTMSKR1_PARMSK_SHIFT) & DDRPHY_BISTMSKR1_PARMSK_MASK) +#define DDRPHY_BISTMSKR1_PARMSK_GET(x) (((uint32_t)(x) & DDRPHY_BISTMSKR1_PARMSK_MASK) >> DDRPHY_BISTMSKR1_PARMSK_SHIFT) + +/* + * CASMSK (R/W) + * + * Mask bit for the CAS. + */ +#define DDRPHY_BISTMSKR1_CASMSK_MASK (0x2U) +#define DDRPHY_BISTMSKR1_CASMSK_SHIFT (1U) +#define DDRPHY_BISTMSKR1_CASMSK_SET(x) (((uint32_t)(x) << DDRPHY_BISTMSKR1_CASMSK_SHIFT) & DDRPHY_BISTMSKR1_CASMSK_MASK) +#define DDRPHY_BISTMSKR1_CASMSK_GET(x) (((uint32_t)(x) & DDRPHY_BISTMSKR1_CASMSK_MASK) >> DDRPHY_BISTMSKR1_CASMSK_SHIFT) + +/* + * RASMSK (R/W) + * + * Mask bit for the RAS. + */ +#define DDRPHY_BISTMSKR1_RASMSK_MASK (0x1U) +#define DDRPHY_BISTMSKR1_RASMSK_SHIFT (0U) +#define DDRPHY_BISTMSKR1_RASMSK_SET(x) (((uint32_t)(x) << DDRPHY_BISTMSKR1_RASMSK_SHIFT) & DDRPHY_BISTMSKR1_RASMSK_MASK) +#define DDRPHY_BISTMSKR1_RASMSK_GET(x) (((uint32_t)(x) & DDRPHY_BISTMSKR1_RASMSK_MASK) >> DDRPHY_BISTMSKR1_RASMSK_SHIFT) + +/* Bitfield definition for register: BISTMSKR2 */ +/* + * DQMSK (R/W) + * + * Mask bit for each of the 8 data (DQ) bits. + */ +#define DDRPHY_BISTMSKR2_DQMSK_MASK (0xFFFFFFFFUL) +#define DDRPHY_BISTMSKR2_DQMSK_SHIFT (0U) +#define DDRPHY_BISTMSKR2_DQMSK_SET(x) (((uint32_t)(x) << DDRPHY_BISTMSKR2_DQMSK_SHIFT) & DDRPHY_BISTMSKR2_DQMSK_MASK) +#define DDRPHY_BISTMSKR2_DQMSK_GET(x) (((uint32_t)(x) & DDRPHY_BISTMSKR2_DQMSK_MASK) >> DDRPHY_BISTMSKR2_DQMSK_SHIFT) + +/* Bitfield definition for register: BISTLSR */ +/* + * SEED (R/W) + * + * LFSR seed for pseudo-random BIST patterns. + */ +#define DDRPHY_BISTLSR_SEED_MASK (0xFFFFFFFFUL) +#define DDRPHY_BISTLSR_SEED_SHIFT (0U) +#define DDRPHY_BISTLSR_SEED_SET(x) (((uint32_t)(x) << DDRPHY_BISTLSR_SEED_SHIFT) & DDRPHY_BISTLSR_SEED_MASK) +#define DDRPHY_BISTLSR_SEED_GET(x) (((uint32_t)(x) & DDRPHY_BISTLSR_SEED_MASK) >> DDRPHY_BISTLSR_SEED_SHIFT) + +/* Bitfield definition for register: BISTAR0 */ +/* + * BBANK (R/W) + * + * BIST Bank Address: Selects the SDRAM bank address to be used during BIST. + */ +#define DDRPHY_BISTAR0_BBANK_MASK (0x70000000UL) +#define DDRPHY_BISTAR0_BBANK_SHIFT (28U) +#define DDRPHY_BISTAR0_BBANK_SET(x) (((uint32_t)(x) << DDRPHY_BISTAR0_BBANK_SHIFT) & DDRPHY_BISTAR0_BBANK_MASK) +#define DDRPHY_BISTAR0_BBANK_GET(x) (((uint32_t)(x) & DDRPHY_BISTAR0_BBANK_MASK) >> DDRPHY_BISTAR0_BBANK_SHIFT) + +/* + * BROW (R/W) + * + * BIST Row Address: Selects the SDRAM row address to be used during BIST. + */ +#define DDRPHY_BISTAR0_BROW_MASK (0xFFFF000UL) +#define DDRPHY_BISTAR0_BROW_SHIFT (12U) +#define DDRPHY_BISTAR0_BROW_SET(x) (((uint32_t)(x) << DDRPHY_BISTAR0_BROW_SHIFT) & DDRPHY_BISTAR0_BROW_MASK) +#define DDRPHY_BISTAR0_BROW_GET(x) (((uint32_t)(x) & DDRPHY_BISTAR0_BROW_MASK) >> DDRPHY_BISTAR0_BROW_SHIFT) + +/* + * BCOL (R/W) + * + * BIST Column Address: Selects the SDRAM column address to be used during BIST. The lower bits of this address must be “0000” for BL16, “000” for BL8, “00” for BL4 and “0” for BL2. + */ +#define DDRPHY_BISTAR0_BCOL_MASK (0xFFFU) +#define DDRPHY_BISTAR0_BCOL_SHIFT (0U) +#define DDRPHY_BISTAR0_BCOL_SET(x) (((uint32_t)(x) << DDRPHY_BISTAR0_BCOL_SHIFT) & DDRPHY_BISTAR0_BCOL_MASK) +#define DDRPHY_BISTAR0_BCOL_GET(x) (((uint32_t)(x) & DDRPHY_BISTAR0_BCOL_MASK) >> DDRPHY_BISTAR0_BCOL_SHIFT) + +/* Bitfield definition for register: BISTAR1 */ +/* + * BAINC (R/W) + * + * BIST Address Increment: Selects the value by which the SDRAM address is incremented for each write/read access. This value must be at the beginning of a burst boundary, i.e. the lower bits must be “0000” for BL16, “000” for BL8, “00” for BL4 and “0” for BL2. + */ +#define DDRPHY_BISTAR1_BAINC_MASK (0xFFF0U) +#define DDRPHY_BISTAR1_BAINC_SHIFT (4U) +#define DDRPHY_BISTAR1_BAINC_SET(x) (((uint32_t)(x) << DDRPHY_BISTAR1_BAINC_SHIFT) & DDRPHY_BISTAR1_BAINC_MASK) +#define DDRPHY_BISTAR1_BAINC_GET(x) (((uint32_t)(x) & DDRPHY_BISTAR1_BAINC_MASK) >> DDRPHY_BISTAR1_BAINC_SHIFT) + +/* + * BMRANK (R/W) + * + * BIST Maximum Rank: Specifies the maximum SDRAM rank to be used during BIST. The default value is set to maximum ranks minus 1. Example default shown here is for a 4-rank system + */ +#define DDRPHY_BISTAR1_BMRANK_MASK (0xCU) +#define DDRPHY_BISTAR1_BMRANK_SHIFT (2U) +#define DDRPHY_BISTAR1_BMRANK_SET(x) (((uint32_t)(x) << DDRPHY_BISTAR1_BMRANK_SHIFT) & DDRPHY_BISTAR1_BMRANK_MASK) +#define DDRPHY_BISTAR1_BMRANK_GET(x) (((uint32_t)(x) & DDRPHY_BISTAR1_BMRANK_MASK) >> DDRPHY_BISTAR1_BMRANK_SHIFT) + +/* + * BRANK (R/W) + * + * BIST Rank: Selects the SDRAM rank to be used during BIST. Valid values range from 0 to maximum ranks minus 1. + */ +#define DDRPHY_BISTAR1_BRANK_MASK (0x3U) +#define DDRPHY_BISTAR1_BRANK_SHIFT (0U) +#define DDRPHY_BISTAR1_BRANK_SET(x) (((uint32_t)(x) << DDRPHY_BISTAR1_BRANK_SHIFT) & DDRPHY_BISTAR1_BRANK_MASK) +#define DDRPHY_BISTAR1_BRANK_GET(x) (((uint32_t)(x) & DDRPHY_BISTAR1_BRANK_MASK) >> DDRPHY_BISTAR1_BRANK_SHIFT) + +/* Bitfield definition for register: BISTAR2 */ +/* + * BMBANK (R/W) + * + * BIST Maximum Bank Address: Specifies the maximum SDRAM bank address to be used during BIST before the address increments to the next rank. + */ +#define DDRPHY_BISTAR2_BMBANK_MASK (0x70000000UL) +#define DDRPHY_BISTAR2_BMBANK_SHIFT (28U) +#define DDRPHY_BISTAR2_BMBANK_SET(x) (((uint32_t)(x) << DDRPHY_BISTAR2_BMBANK_SHIFT) & DDRPHY_BISTAR2_BMBANK_MASK) +#define DDRPHY_BISTAR2_BMBANK_GET(x) (((uint32_t)(x) & DDRPHY_BISTAR2_BMBANK_MASK) >> DDRPHY_BISTAR2_BMBANK_SHIFT) + +/* + * BMROW (R/W) + * + * BIST Maximum Row Address: Specifies the maximum SDRAM row address to be used during BIST before the address increments to the next bank. + */ +#define DDRPHY_BISTAR2_BMROW_MASK (0xFFFF000UL) +#define DDRPHY_BISTAR2_BMROW_SHIFT (12U) +#define DDRPHY_BISTAR2_BMROW_SET(x) (((uint32_t)(x) << DDRPHY_BISTAR2_BMROW_SHIFT) & DDRPHY_BISTAR2_BMROW_MASK) +#define DDRPHY_BISTAR2_BMROW_GET(x) (((uint32_t)(x) & DDRPHY_BISTAR2_BMROW_MASK) >> DDRPHY_BISTAR2_BMROW_SHIFT) + +/* + * BMCOL (R/W) + * + * BIST Maximum Column Address: Specifies the maximum SDRAM column address to be used during BIST before the address increments to the next row. + */ +#define DDRPHY_BISTAR2_BMCOL_MASK (0xFFFU) +#define DDRPHY_BISTAR2_BMCOL_SHIFT (0U) +#define DDRPHY_BISTAR2_BMCOL_SET(x) (((uint32_t)(x) << DDRPHY_BISTAR2_BMCOL_SHIFT) & DDRPHY_BISTAR2_BMCOL_MASK) +#define DDRPHY_BISTAR2_BMCOL_GET(x) (((uint32_t)(x) & DDRPHY_BISTAR2_BMCOL_MASK) >> DDRPHY_BISTAR2_BMCOL_SHIFT) + +/* Bitfield definition for register: BISTUDPR */ +/* + * BUDP1 (R/W) + * + * BIST User Data Pattern 1: Data to be applied on odd DQ pins during BIST. + */ +#define DDRPHY_BISTUDPR_BUDP1_MASK (0xFFFF0000UL) +#define DDRPHY_BISTUDPR_BUDP1_SHIFT (16U) +#define DDRPHY_BISTUDPR_BUDP1_SET(x) (((uint32_t)(x) << DDRPHY_BISTUDPR_BUDP1_SHIFT) & DDRPHY_BISTUDPR_BUDP1_MASK) +#define DDRPHY_BISTUDPR_BUDP1_GET(x) (((uint32_t)(x) & DDRPHY_BISTUDPR_BUDP1_MASK) >> DDRPHY_BISTUDPR_BUDP1_SHIFT) + +/* + * BUDP0 (R/W) + * + * BIST User Data Pattern 0: Data to be applied on even DQ pins during BIST. + */ +#define DDRPHY_BISTUDPR_BUDP0_MASK (0xFFFFU) +#define DDRPHY_BISTUDPR_BUDP0_SHIFT (0U) +#define DDRPHY_BISTUDPR_BUDP0_SET(x) (((uint32_t)(x) << DDRPHY_BISTUDPR_BUDP0_SHIFT) & DDRPHY_BISTUDPR_BUDP0_MASK) +#define DDRPHY_BISTUDPR_BUDP0_GET(x) (((uint32_t)(x) & DDRPHY_BISTUDPR_BUDP0_MASK) >> DDRPHY_BISTUDPR_BUDP0_SHIFT) + +/* Bitfield definition for register: BISTGSR */ +/* + * CASBER (R) + * + * CAS Bit Error: Indicates the number of bit errors on CAS. + */ +#define DDRPHY_BISTGSR_CASBER_MASK (0xC0000000UL) +#define DDRPHY_BISTGSR_CASBER_SHIFT (30U) +#define DDRPHY_BISTGSR_CASBER_GET(x) (((uint32_t)(x) & DDRPHY_BISTGSR_CASBER_MASK) >> DDRPHY_BISTGSR_CASBER_SHIFT) + +/* + * RASBER (R) + * + * RAS Bit Error: Indicates the number of bit errors on RAS. + */ +#define DDRPHY_BISTGSR_RASBER_MASK (0x30000000UL) +#define DDRPHY_BISTGSR_RASBER_SHIFT (28U) +#define DDRPHY_BISTGSR_RASBER_GET(x) (((uint32_t)(x) & DDRPHY_BISTGSR_RASBER_MASK) >> DDRPHY_BISTGSR_RASBER_SHIFT) + +/* + * DMBER (R) + * + * DM Bit Error: Indicates the number of bit errors on data mask (DM) bit. DMBER[1:0] are for even DQS cycles first DM beat, and DMBER[3:2] are for even DQS cycles second DM beat. Similarly, DMBER[5:4] are for odd DQS cycles first DM beat, and DMBER[7:6] are for odd DQS cycles second DM beat. + */ +#define DDRPHY_BISTGSR_DMBER_MASK (0xFF00000UL) +#define DDRPHY_BISTGSR_DMBER_SHIFT (20U) +#define DDRPHY_BISTGSR_DMBER_GET(x) (((uint32_t)(x) & DDRPHY_BISTGSR_DMBER_MASK) >> DDRPHY_BISTGSR_DMBER_SHIFT) + +/* + * PARBER (R) + * + * PAR_IN Bit Error (DIMM Only): Indicates the number of bit errors on PAR_IN + */ +#define DDRPHY_BISTGSR_PARBER_MASK (0x30000UL) +#define DDRPHY_BISTGSR_PARBER_SHIFT (16U) +#define DDRPHY_BISTGSR_PARBER_GET(x) (((uint32_t)(x) & DDRPHY_BISTGSR_PARBER_MASK) >> DDRPHY_BISTGSR_PARBER_SHIFT) + +/* + * BDXERR (R) + * + * BIST Data Error: indicates, if set, that there is a data comparison error in the byte lane. + */ +#define DDRPHY_BISTGSR_BDXERR_MASK (0x4U) +#define DDRPHY_BISTGSR_BDXERR_SHIFT (2U) +#define DDRPHY_BISTGSR_BDXERR_GET(x) (((uint32_t)(x) & DDRPHY_BISTGSR_BDXERR_MASK) >> DDRPHY_BISTGSR_BDXERR_SHIFT) + +/* + * BACERR (R) + * + * BIST Address/Command Error: indicates, if set, that there is a data comparison error in the address/command lane. + */ +#define DDRPHY_BISTGSR_BACERR_MASK (0x2U) +#define DDRPHY_BISTGSR_BACERR_SHIFT (1U) +#define DDRPHY_BISTGSR_BACERR_GET(x) (((uint32_t)(x) & DDRPHY_BISTGSR_BACERR_MASK) >> DDRPHY_BISTGSR_BACERR_SHIFT) + +/* + * BDONE (R) + * + * BIST Done: Indicates, if set, that the BIST has finished executing. This bit is reset to zero when BIST is triggered. + */ +#define DDRPHY_BISTGSR_BDONE_MASK (0x1U) +#define DDRPHY_BISTGSR_BDONE_SHIFT (0U) +#define DDRPHY_BISTGSR_BDONE_GET(x) (((uint32_t)(x) & DDRPHY_BISTGSR_BDONE_MASK) >> DDRPHY_BISTGSR_BDONE_SHIFT) + +/* Bitfield definition for register: BISTWER */ +/* + * DXWER (R) + * + * Byte Word Error: Indicates the number of word errors on the byte lane. An error on any bit of the data bus including the data mask bit increments the error count. + */ +#define DDRPHY_BISTWER_DXWER_MASK (0xFFFF0000UL) +#define DDRPHY_BISTWER_DXWER_SHIFT (16U) +#define DDRPHY_BISTWER_DXWER_GET(x) (((uint32_t)(x) & DDRPHY_BISTWER_DXWER_MASK) >> DDRPHY_BISTWER_DXWER_SHIFT) + +/* + * ACWER (R) + * + * Address/Command Word Error: Indicates the number of word errors on the address/command lane. An error on any bit of the address/command bus increments the error count. + */ +#define DDRPHY_BISTWER_ACWER_MASK (0xFFFFU) +#define DDRPHY_BISTWER_ACWER_SHIFT (0U) +#define DDRPHY_BISTWER_ACWER_GET(x) (((uint32_t)(x) & DDRPHY_BISTWER_ACWER_MASK) >> DDRPHY_BISTWER_ACWER_SHIFT) + +/* Bitfield definition for register: BISTBER0 */ +/* + * ABER (R) + * + * Address Bit Error: Each group of two bits indicate the bit error count on each of the + */ +#define DDRPHY_BISTBER0_ABER_MASK (0xFFFFFFFFUL) +#define DDRPHY_BISTBER0_ABER_SHIFT (0U) +#define DDRPHY_BISTBER0_ABER_GET(x) (((uint32_t)(x) & DDRPHY_BISTBER0_ABER_MASK) >> DDRPHY_BISTBER0_ABER_SHIFT) + +/* Bitfield definition for register: BISTBER1 */ +/* + * ODTBER (R) + * + * ODT Bit Error: Each group of two bits indicates the bit error count on each of the up to 4 ODT bits. [1:0] is the error count for ODT[0], [3:2] for ODT[1], and so on. + */ +#define DDRPHY_BISTBER1_ODTBER_MASK (0xFF000000UL) +#define DDRPHY_BISTBER1_ODTBER_SHIFT (24U) +#define DDRPHY_BISTBER1_ODTBER_GET(x) (((uint32_t)(x) & DDRPHY_BISTBER1_ODTBER_MASK) >> DDRPHY_BISTBER1_ODTBER_SHIFT) + +/* + * CSBER (R) + * + * CS# Bit Error: Each group of two bits indicate the bit error count on each of the up to 4 CS# bits. [1:0] is the error count for CS#[0], [3:2] for CS#[1], and so on. + */ +#define DDRPHY_BISTBER1_CSBER_MASK (0xFF0000UL) +#define DDRPHY_BISTBER1_CSBER_SHIFT (16U) +#define DDRPHY_BISTBER1_CSBER_GET(x) (((uint32_t)(x) & DDRPHY_BISTBER1_CSBER_MASK) >> DDRPHY_BISTBER1_CSBER_SHIFT) + +/* + * CKEBER (R) + * + * CKE Bit Error: Each group of two bits indicate the bit error count on each of the up to 4 CKE bits. [1:0] is the error count for CKE[0], [3:2] for CKE[1], and so on. + */ +#define DDRPHY_BISTBER1_CKEBER_MASK (0xFF00U) +#define DDRPHY_BISTBER1_CKEBER_SHIFT (8U) +#define DDRPHY_BISTBER1_CKEBER_GET(x) (((uint32_t)(x) & DDRPHY_BISTBER1_CKEBER_MASK) >> DDRPHY_BISTBER1_CKEBER_SHIFT) + +/* + * WEBER (R) + * + * WE# Bit Error: Indicates the number of bit errors on WE#. + */ +#define DDRPHY_BISTBER1_WEBER_MASK (0xC0U) +#define DDRPHY_BISTBER1_WEBER_SHIFT (6U) +#define DDRPHY_BISTBER1_WEBER_GET(x) (((uint32_t)(x) & DDRPHY_BISTBER1_WEBER_MASK) >> DDRPHY_BISTBER1_WEBER_SHIFT) + +/* + * BABER (R) + * + * Bank Address Bit Error: Each group of two bits indicate the bit error count on each of the up to 3 bank address bits. [1:0] is the error count for BA[0], [3:2] for BA[1], and so on. + */ +#define DDRPHY_BISTBER1_BABER_MASK (0x3FU) +#define DDRPHY_BISTBER1_BABER_SHIFT (0U) +#define DDRPHY_BISTBER1_BABER_GET(x) (((uint32_t)(x) & DDRPHY_BISTBER1_BABER_MASK) >> DDRPHY_BISTBER1_BABER_SHIFT) + +/* Bitfield definition for register: BISTBER2 */ +/* + * DQBER0 (R) + * + * Data Bit Error: The error count for even DQS cycles. The first 16 bits indicate the error count for the first data beat (i.e. the data driven out on DQ[7:0] on the rising edge of DQS). The second 16 bits indicate the error on the second data beat (i.e. the error count of the data driven out on DQ[7:0] on the falling edge of DQS). For each of the 16-bit group, the first 2 bits are for DQ[0], the second for DQ[1], and so on. + */ +#define DDRPHY_BISTBER2_DQBER0_MASK (0xFFFFFFFFUL) +#define DDRPHY_BISTBER2_DQBER0_SHIFT (0U) +#define DDRPHY_BISTBER2_DQBER0_GET(x) (((uint32_t)(x) & DDRPHY_BISTBER2_DQBER0_MASK) >> DDRPHY_BISTBER2_DQBER0_SHIFT) + +/* Bitfield definition for register: BISTBER3 */ +/* + * DQBER1 (R) + * + * Data Bit Error: The error count for odd DQS cycles. The first 16 bits indicate the error count for the first data beat (i.e. the data driven out on DQ[7:0] on the rising edge of DQS). The second 16 bits indicate the error on the second data beat (i.e. the error count of the data driven out on DQ[7:0] on the falling edge of DQS). For each of the 16-bit group, the first 2 bits are for DQ[0], the second for DQ[1], and so on. + */ +#define DDRPHY_BISTBER3_DQBER1_MASK (0xFFFFFFFFUL) +#define DDRPHY_BISTBER3_DQBER1_SHIFT (0U) +#define DDRPHY_BISTBER3_DQBER1_GET(x) (((uint32_t)(x) & DDRPHY_BISTBER3_DQBER1_MASK) >> DDRPHY_BISTBER3_DQBER1_SHIFT) + +/* Bitfield definition for register: BISTWCSR */ +/* + * DXWCNT (R) + * + * Byte Word Count: Indicates the number of words received from the byte lane. + */ +#define DDRPHY_BISTWCSR_DXWCNT_MASK (0xFFFF0000UL) +#define DDRPHY_BISTWCSR_DXWCNT_SHIFT (16U) +#define DDRPHY_BISTWCSR_DXWCNT_GET(x) (((uint32_t)(x) & DDRPHY_BISTWCSR_DXWCNT_MASK) >> DDRPHY_BISTWCSR_DXWCNT_SHIFT) + +/* + * ACWCNT (R) + * + * Address/Command Word Count: Indicates the number of words received from the address/command lane. + */ +#define DDRPHY_BISTWCSR_ACWCNT_MASK (0xFFFFU) +#define DDRPHY_BISTWCSR_ACWCNT_SHIFT (0U) +#define DDRPHY_BISTWCSR_ACWCNT_GET(x) (((uint32_t)(x) & DDRPHY_BISTWCSR_ACWCNT_MASK) >> DDRPHY_BISTWCSR_ACWCNT_SHIFT) + +/* Bitfield definition for register: BISTFWR0 */ +/* + * ODTWEBS (R) + * + * Bit status during a word error for each of the up to 4 ODT bits. + */ +#define DDRPHY_BISTFWR0_ODTWEBS_MASK (0xF0000000UL) +#define DDRPHY_BISTFWR0_ODTWEBS_SHIFT (28U) +#define DDRPHY_BISTFWR0_ODTWEBS_GET(x) (((uint32_t)(x) & DDRPHY_BISTFWR0_ODTWEBS_MASK) >> DDRPHY_BISTFWR0_ODTWEBS_SHIFT) + +/* + * CSWEBS (R) + * + * Bit status during a word error for each of the up to 4 CS# bits. + */ +#define DDRPHY_BISTFWR0_CSWEBS_MASK (0xF000000UL) +#define DDRPHY_BISTFWR0_CSWEBS_SHIFT (24U) +#define DDRPHY_BISTFWR0_CSWEBS_GET(x) (((uint32_t)(x) & DDRPHY_BISTFWR0_CSWEBS_MASK) >> DDRPHY_BISTFWR0_CSWEBS_SHIFT) + +/* + * CKEWEBS (R) + * + * Bit status during a word error for each of the up to 4 CKE bits. + */ +#define DDRPHY_BISTFWR0_CKEWEBS_MASK (0xF00000UL) +#define DDRPHY_BISTFWR0_CKEWEBS_SHIFT (20U) +#define DDRPHY_BISTFWR0_CKEWEBS_GET(x) (((uint32_t)(x) & DDRPHY_BISTFWR0_CKEWEBS_MASK) >> DDRPHY_BISTFWR0_CKEWEBS_SHIFT) + +/* + * WEWEBS (R) + * + * Bit status during a word error for the WE#. + */ +#define DDRPHY_BISTFWR0_WEWEBS_MASK (0x80000UL) +#define DDRPHY_BISTFWR0_WEWEBS_SHIFT (19U) +#define DDRPHY_BISTFWR0_WEWEBS_GET(x) (((uint32_t)(x) & DDRPHY_BISTFWR0_WEWEBS_MASK) >> DDRPHY_BISTFWR0_WEWEBS_SHIFT) + +/* + * BAWEBS (R) + * + * Bit status during a word error for each of the up to 3 bank address bits. + */ +#define DDRPHY_BISTFWR0_BAWEBS_MASK (0x70000UL) +#define DDRPHY_BISTFWR0_BAWEBS_SHIFT (16U) +#define DDRPHY_BISTFWR0_BAWEBS_GET(x) (((uint32_t)(x) & DDRPHY_BISTFWR0_BAWEBS_MASK) >> DDRPHY_BISTFWR0_BAWEBS_SHIFT) + +/* + * AWEBS (R) + * + * Bit status during a word error for each of the up to 16 address bits. + */ +#define DDRPHY_BISTFWR0_AWEBS_MASK (0xFFFFU) +#define DDRPHY_BISTFWR0_AWEBS_SHIFT (0U) +#define DDRPHY_BISTFWR0_AWEBS_GET(x) (((uint32_t)(x) & DDRPHY_BISTFWR0_AWEBS_MASK) >> DDRPHY_BISTFWR0_AWEBS_SHIFT) + +/* Bitfield definition for register: BISTFWR1 */ +/* + * DMWEBS (R) + * + * Bit status during a word error for the data mask (DM) bit. DMWEBS [0] is for the first DM beat, DMWEBS [1] is for the second DM beat, and so on. + */ +#define DDRPHY_BISTFWR1_DMWEBS_MASK (0xF0000000UL) +#define DDRPHY_BISTFWR1_DMWEBS_SHIFT (28U) +#define DDRPHY_BISTFWR1_DMWEBS_GET(x) (((uint32_t)(x) & DDRPHY_BISTFWR1_DMWEBS_MASK) >> DDRPHY_BISTFWR1_DMWEBS_SHIFT) + +/* + * PARWEBS (R) + * + * Bit status during a word error for the PAR_IN. Only for DIMM parity support + */ +#define DDRPHY_BISTFWR1_PARWEBS_MASK (0x4000000UL) +#define DDRPHY_BISTFWR1_PARWEBS_SHIFT (26U) +#define DDRPHY_BISTFWR1_PARWEBS_GET(x) (((uint32_t)(x) & DDRPHY_BISTFWR1_PARWEBS_MASK) >> DDRPHY_BISTFWR1_PARWEBS_SHIFT) + +/* + * CASWEBS (R) + * + * Bit status during a word error for the CAS. + */ +#define DDRPHY_BISTFWR1_CASWEBS_MASK (0x2U) +#define DDRPHY_BISTFWR1_CASWEBS_SHIFT (1U) +#define DDRPHY_BISTFWR1_CASWEBS_GET(x) (((uint32_t)(x) & DDRPHY_BISTFWR1_CASWEBS_MASK) >> DDRPHY_BISTFWR1_CASWEBS_SHIFT) + +/* + * RASWEBS (R) + * + * Bit status during a word error for the RAS. + */ +#define DDRPHY_BISTFWR1_RASWEBS_MASK (0x1U) +#define DDRPHY_BISTFWR1_RASWEBS_SHIFT (0U) +#define DDRPHY_BISTFWR1_RASWEBS_GET(x) (((uint32_t)(x) & DDRPHY_BISTFWR1_RASWEBS_MASK) >> DDRPHY_BISTFWR1_RASWEBS_SHIFT) + +/* Bitfield definition for register: BISTFWR2 */ +/* + * DQWEBS (R) + * + * Bit status during a word error for each of the 8 data (DQ) bits. The first 8 bits indicate the status of the first data beat (i.e. the status of the data driven out on DQ[7:0] on the rising edge of DQS). The second 8 bits indicate the status of the second data beat (i.e. the status of the data driven out on DQ[7:0] on the falling edge of DQS), and so on. For each of the 8-bit group, the first bit is for DQ[0], the second bit is for DQ[1], and so on. + */ +#define DDRPHY_BISTFWR2_DQWEBS_MASK (0xFFFFFFFFUL) +#define DDRPHY_BISTFWR2_DQWEBS_SHIFT (0U) +#define DDRPHY_BISTFWR2_DQWEBS_GET(x) (((uint32_t)(x) & DDRPHY_BISTFWR2_DQWEBS_MASK) >> DDRPHY_BISTFWR2_DQWEBS_SHIFT) + +/* Bitfield definition for register: AACR */ +/* + * AAOENC (R/W) + * + * Anti-Aging PAD Output Enable Control: Enables, if set, anti-aging toggling on the pad output enable signal “ctl_oe_n” going into the DATX8s. This will increase power consumption for the anti-aging feature. + */ +#define DDRPHY_AACR_AAOENC_MASK (0x80000000UL) +#define DDRPHY_AACR_AAOENC_SHIFT (31U) +#define DDRPHY_AACR_AAOENC_SET(x) (((uint32_t)(x) << DDRPHY_AACR_AAOENC_SHIFT) & DDRPHY_AACR_AAOENC_MASK) +#define DDRPHY_AACR_AAOENC_GET(x) (((uint32_t)(x) & DDRPHY_AACR_AAOENC_MASK) >> DDRPHY_AACR_AAOENC_SHIFT) + +/* + * AAENC (R/W) + * + * Anti-Aging Enable Control: Enables, if set, the automatic toggling of the data going to the DATX8 when the data channel from the controller/PUB to DATX8 is idle for programmable number of clock cycles. + */ +#define DDRPHY_AACR_AAENC_MASK (0x40000000UL) +#define DDRPHY_AACR_AAENC_SHIFT (30U) +#define DDRPHY_AACR_AAENC_SET(x) (((uint32_t)(x) << DDRPHY_AACR_AAENC_SHIFT) & DDRPHY_AACR_AAENC_MASK) +#define DDRPHY_AACR_AAENC_GET(x) (((uint32_t)(x) & DDRPHY_AACR_AAENC_MASK) >> DDRPHY_AACR_AAENC_SHIFT) + +/* + * AATR (R/W) + * + * Anti-Aging Toggle Rate: Defines the number of controller clock (ctl_clk) cycles after which the PUB will toggle the data going to DATX8 if the data channel between the controller/PUB and DATX8 has been idle for this long. + * The default value correspond to a toggling count of 4096 ctl_clk cycles. For a ctl_clk running at 533MHz the toggle rate will be approximately 7.68us. + * The default value may also be overridden by the macro DWC_AACR_AATR_DFLT. + */ +#define DDRPHY_AACR_AATR_MASK (0x3FFFFFFFUL) +#define DDRPHY_AACR_AATR_SHIFT (0U) +#define DDRPHY_AACR_AATR_SET(x) (((uint32_t)(x) << DDRPHY_AACR_AATR_SHIFT) & DDRPHY_AACR_AATR_MASK) +#define DDRPHY_AACR_AATR_GET(x) (((uint32_t)(x) & DDRPHY_AACR_AATR_MASK) >> DDRPHY_AACR_AATR_SHIFT) + +/* Bitfield definition for register: GPR0 */ +/* + * GPR0 (R/W) + * + * General Purpose Register 0: General purpose register bits. + */ +#define DDRPHY_GPR0_GPR0_MASK (0xFFFFFFFFUL) +#define DDRPHY_GPR0_GPR0_SHIFT (0U) +#define DDRPHY_GPR0_GPR0_SET(x) (((uint32_t)(x) << DDRPHY_GPR0_GPR0_SHIFT) & DDRPHY_GPR0_GPR0_MASK) +#define DDRPHY_GPR0_GPR0_GET(x) (((uint32_t)(x) & DDRPHY_GPR0_GPR0_MASK) >> DDRPHY_GPR0_GPR0_SHIFT) + +/* Bitfield definition for register: GPR1 */ +/* + * GPR1 (R/W) + * + * General Purpose Register 1: General purpose register bits. + */ +#define DDRPHY_GPR1_GPR1_MASK (0xFFFFFFFFUL) +#define DDRPHY_GPR1_GPR1_SHIFT (0U) +#define DDRPHY_GPR1_GPR1_SET(x) (((uint32_t)(x) << DDRPHY_GPR1_GPR1_SHIFT) & DDRPHY_GPR1_GPR1_MASK) +#define DDRPHY_GPR1_GPR1_GET(x) (((uint32_t)(x) & DDRPHY_GPR1_GPR1_MASK) >> DDRPHY_GPR1_GPR1_SHIFT) + +/* Bitfield definition for register of struct array ZQ: CR0 */ +/* + * ZQPD (R/W) + * + * ZQ Power Down: Powers down, if set, the PZQ cell. + */ +#define DDRPHY_ZQ_CR0_ZQPD_MASK (0x80000000UL) +#define DDRPHY_ZQ_CR0_ZQPD_SHIFT (31U) +#define DDRPHY_ZQ_CR0_ZQPD_SET(x) (((uint32_t)(x) << DDRPHY_ZQ_CR0_ZQPD_SHIFT) & DDRPHY_ZQ_CR0_ZQPD_MASK) +#define DDRPHY_ZQ_CR0_ZQPD_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_CR0_ZQPD_MASK) >> DDRPHY_ZQ_CR0_ZQPD_SHIFT) + +/* + * ZCALEN (R/W) + * + * Impedance Calibration Enable: Enables, if set, the impedance calibration of this ZQ control block when impedance calibration is triggered using either the ZCAL bit of PIR register or the DFI update interface. + */ +#define DDRPHY_ZQ_CR0_ZCALEN_MASK (0x40000000UL) +#define DDRPHY_ZQ_CR0_ZCALEN_SHIFT (30U) +#define DDRPHY_ZQ_CR0_ZCALEN_SET(x) (((uint32_t)(x) << DDRPHY_ZQ_CR0_ZCALEN_SHIFT) & DDRPHY_ZQ_CR0_ZCALEN_MASK) +#define DDRPHY_ZQ_CR0_ZCALEN_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_CR0_ZCALEN_MASK) >> DDRPHY_ZQ_CR0_ZCALEN_SHIFT) + +/* + * ZCALBYP (R/W) + * + * Impedance Calibration Bypass: Bypasses, if set, impedance calibration of this ZQ control block when impedance calibration is already in progress. Impedance calibration can be disabled prior to trigger by using the ZCALEN bit. + */ +#define DDRPHY_ZQ_CR0_ZCALBYP_MASK (0x20000000UL) +#define DDRPHY_ZQ_CR0_ZCALBYP_SHIFT (29U) +#define DDRPHY_ZQ_CR0_ZCALBYP_SET(x) (((uint32_t)(x) << DDRPHY_ZQ_CR0_ZCALBYP_SHIFT) & DDRPHY_ZQ_CR0_ZCALBYP_MASK) +#define DDRPHY_ZQ_CR0_ZCALBYP_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_CR0_ZCALBYP_MASK) >> DDRPHY_ZQ_CR0_ZCALBYP_SHIFT) + +/* + * ZDEN (R/W) + * + * Impedance Over-ride Enable: When this bit is set, it allows users to directly drive the impedance control using the data programmed in the ZDATA field. Otherwise, the control is generated automatically by the impedance control logic. + */ +#define DDRPHY_ZQ_CR0_ZDEN_MASK (0x10000000UL) +#define DDRPHY_ZQ_CR0_ZDEN_SHIFT (28U) +#define DDRPHY_ZQ_CR0_ZDEN_SET(x) (((uint32_t)(x) << DDRPHY_ZQ_CR0_ZDEN_SHIFT) & DDRPHY_ZQ_CR0_ZDEN_MASK) +#define DDRPHY_ZQ_CR0_ZDEN_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_CR0_ZDEN_MASK) >> DDRPHY_ZQ_CR0_ZDEN_SHIFT) + +/* + * ZDATA (R/W) + * + * Impedance Over-Ride Data: Data used to directly drive the impedance control. + * ZDATA field mapping for D3F I/Os is as follows: + * ZDATA[27:21] is used to select the pull-up on-die termination impedance ZDATA[20:14] is used to select the pull-down on-die termination impedance ZDATA[13:7] is used to select the pull-up output impedance + * ZDATA[6:0] is used to select the pull-down output impedance + * ZDATA field mapping for D3A/B/R I/Os is as follows: ZDATA[27:20] is reserved and returns zeros on reads + * ZDATA[19:15] is used to select the pull-up on-die termination impedance ZDATA[14:10] is used to select the pull-down on-die termination impedance ZDATA[9:5] is used to select the pull-up output impedance + * ZDATA[4:0] is used to select the pull-down output impedance + * The default value is 0x000014A for I/O type D3C/R and 0x0001830 for I/O type D3F. + */ +#define DDRPHY_ZQ_CR0_ZDATA_MASK (0xFFFFFFFUL) +#define DDRPHY_ZQ_CR0_ZDATA_SHIFT (0U) +#define DDRPHY_ZQ_CR0_ZDATA_SET(x) (((uint32_t)(x) << DDRPHY_ZQ_CR0_ZDATA_SHIFT) & DDRPHY_ZQ_CR0_ZDATA_MASK) +#define DDRPHY_ZQ_CR0_ZDATA_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_CR0_ZDATA_MASK) >> DDRPHY_ZQ_CR0_ZDATA_SHIFT) + +/* Bitfield definition for register of struct array ZQ: CR1 */ +/* + * DFIPU1 (R/W) + * + * DFI Update Interface 1: Sets this impedance controller to be enabled for calibration when the DFI PHY update interface 1 (channel 1) requests an update. Only valid in shared-AC mode. + */ +#define DDRPHY_ZQ_CR1_DFIPU1_MASK (0x20000UL) +#define DDRPHY_ZQ_CR1_DFIPU1_SHIFT (17U) +#define DDRPHY_ZQ_CR1_DFIPU1_SET(x) (((uint32_t)(x) << DDRPHY_ZQ_CR1_DFIPU1_SHIFT) & DDRPHY_ZQ_CR1_DFIPU1_MASK) +#define DDRPHY_ZQ_CR1_DFIPU1_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_CR1_DFIPU1_MASK) >> DDRPHY_ZQ_CR1_DFIPU1_SHIFT) + +/* + * DFIPU0 (R/W) + * + * DFI Update Interface 0: Sets this impedance controller to be enabled for calibration when the DFI PHY update interface 0 (channel 0) requests an update. + */ +#define DDRPHY_ZQ_CR1_DFIPU0_MASK (0x10000UL) +#define DDRPHY_ZQ_CR1_DFIPU0_SHIFT (16U) +#define DDRPHY_ZQ_CR1_DFIPU0_SET(x) (((uint32_t)(x) << DDRPHY_ZQ_CR1_DFIPU0_SHIFT) & DDRPHY_ZQ_CR1_DFIPU0_MASK) +#define DDRPHY_ZQ_CR1_DFIPU0_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_CR1_DFIPU0_MASK) >> DDRPHY_ZQ_CR1_DFIPU0_SHIFT) + +/* + * DFICCU (R/W) + * + * DFI Concurrent Controller Update Interface: Sets this impedance controller to be enabled for calibration when both of the DFI controller update interfaces request an update on the same clock. This provides the ability to enable impedance calibration updates for the Address/Command lane. Only valid in shared-AC mode. + */ +#define DDRPHY_ZQ_CR1_DFICCU_MASK (0x4000U) +#define DDRPHY_ZQ_CR1_DFICCU_SHIFT (14U) +#define DDRPHY_ZQ_CR1_DFICCU_SET(x) (((uint32_t)(x) << DDRPHY_ZQ_CR1_DFICCU_SHIFT) & DDRPHY_ZQ_CR1_DFICCU_MASK) +#define DDRPHY_ZQ_CR1_DFICCU_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_CR1_DFICCU_MASK) >> DDRPHY_ZQ_CR1_DFICCU_SHIFT) + +/* + * DFICU1 (R/W) + * + * DFI Controller Update Interface 1: Sets this impedance controller to be enabled for calibration when the DFI controller update interface 1 (channel 1) requests an update. Only valid in shared-AC mode. + */ +#define DDRPHY_ZQ_CR1_DFICU1_MASK (0x2000U) +#define DDRPHY_ZQ_CR1_DFICU1_SHIFT (13U) +#define DDRPHY_ZQ_CR1_DFICU1_SET(x) (((uint32_t)(x) << DDRPHY_ZQ_CR1_DFICU1_SHIFT) & DDRPHY_ZQ_CR1_DFICU1_MASK) +#define DDRPHY_ZQ_CR1_DFICU1_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_CR1_DFICU1_MASK) >> DDRPHY_ZQ_CR1_DFICU1_SHIFT) + +/* + * DFICU0 (R/W) + * + * DFI Controller Update Interface 0: Sets this impedance controller to be enabled for calibration when the DFI controller update interface 0 (channel 0) requests an update. + */ +#define DDRPHY_ZQ_CR1_DFICU0_MASK (0x1000U) +#define DDRPHY_ZQ_CR1_DFICU0_SHIFT (12U) +#define DDRPHY_ZQ_CR1_DFICU0_SET(x) (((uint32_t)(x) << DDRPHY_ZQ_CR1_DFICU0_SHIFT) & DDRPHY_ZQ_CR1_DFICU0_MASK) +#define DDRPHY_ZQ_CR1_DFICU0_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_CR1_DFICU0_MASK) >> DDRPHY_ZQ_CR1_DFICU0_SHIFT) + +/* + * ZPROG (R/W) + * + * Impedance Divide Ratio: Selects the external resistor divide ratio to be used to set the output impedance and the on-die termination as follows: + * ZPROG[7:4] = On-die termination divide select ZPROG[3:0] = Output impedance divide select + */ +#define DDRPHY_ZQ_CR1_ZPROG_MASK (0xFFU) +#define DDRPHY_ZQ_CR1_ZPROG_SHIFT (0U) +#define DDRPHY_ZQ_CR1_ZPROG_SET(x) (((uint32_t)(x) << DDRPHY_ZQ_CR1_ZPROG_SHIFT) & DDRPHY_ZQ_CR1_ZPROG_MASK) +#define DDRPHY_ZQ_CR1_ZPROG_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_CR1_ZPROG_MASK) >> DDRPHY_ZQ_CR1_ZPROG_SHIFT) + +/* Bitfield definition for register of struct array ZQ: SR0 */ +/* + * ZDONE (R) + * + * Impedance Calibration Done: Indicates that impedance calibration has completed. + */ +#define DDRPHY_ZQ_SR0_ZDONE_MASK (0x80000000UL) +#define DDRPHY_ZQ_SR0_ZDONE_SHIFT (31U) +#define DDRPHY_ZQ_SR0_ZDONE_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_SR0_ZDONE_MASK) >> DDRPHY_ZQ_SR0_ZDONE_SHIFT) + +/* + * ZERR (R) + * + * Impedance Calibration Error: If set, indicates that there was an error during impedance calibration. + */ +#define DDRPHY_ZQ_SR0_ZERR_MASK (0x40000000UL) +#define DDRPHY_ZQ_SR0_ZERR_SHIFT (30U) +#define DDRPHY_ZQ_SR0_ZERR_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_SR0_ZERR_MASK) >> DDRPHY_ZQ_SR0_ZERR_SHIFT) + +/* + * ZCTRL (R) + * + * Impedance Control: Current value of impedance control. ZCTRL field mapping for D3F I/Os is as follows: + * ZCTRL[27:21] is used to select the pull-up on-die termination impedance ZCTRL[20:14] is used to select the pull-down on-die termination impedance ZCTRL[13:7] is used to select the pull-up output impedance + * ZCTRL[6:0] is used to select the pull-down output impedance + * ZCTRL field mapping for D3A/B/R I/Os is as follows: ZCTRL[27:20] is reserved and returns zeros on reads + * ZCTRL[19:15] is used to select the pull-up on-die termination impedance ZCTRL[14:10] is used to select the pull-down on-die termination impedance ZCTRL[9:5] is used to select the pull-up output impedance + * ZCTRL[4:0] is used to select the pull-down output impedance + * Note: The default value is 0x000014A for I/O type D3C/D3R and 0x0001839 for I/O type D3F. + */ +#define DDRPHY_ZQ_SR0_ZCTRL_MASK (0xFFFFFFFUL) +#define DDRPHY_ZQ_SR0_ZCTRL_SHIFT (0U) +#define DDRPHY_ZQ_SR0_ZCTRL_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_SR0_ZCTRL_MASK) >> DDRPHY_ZQ_SR0_ZCTRL_SHIFT) + +/* Bitfield definition for register of struct array ZQ: SR1 */ +/* + * OPU (R) + * + * On-die termination (ODT) pull-up calibration status. Similar status encodings as ZPD. + */ +#define DDRPHY_ZQ_SR1_OPU_MASK (0xC0U) +#define DDRPHY_ZQ_SR1_OPU_SHIFT (6U) +#define DDRPHY_ZQ_SR1_OPU_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_SR1_OPU_MASK) >> DDRPHY_ZQ_SR1_OPU_SHIFT) + +/* + * OPD (R) + * + * On-die termination (ODT) pull-down calibration status. Similar status encodings as ZPD. + */ +#define DDRPHY_ZQ_SR1_OPD_MASK (0x30U) +#define DDRPHY_ZQ_SR1_OPD_SHIFT (4U) +#define DDRPHY_ZQ_SR1_OPD_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_SR1_OPD_MASK) >> DDRPHY_ZQ_SR1_OPD_SHIFT) + +/* + * ZPU (R) + * + * Output impedance pull-up calibration status. Similar status encodings as ZPD. + */ +#define DDRPHY_ZQ_SR1_ZPU_MASK (0xCU) +#define DDRPHY_ZQ_SR1_ZPU_SHIFT (2U) +#define DDRPHY_ZQ_SR1_ZPU_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_SR1_ZPU_MASK) >> DDRPHY_ZQ_SR1_ZPU_SHIFT) + +/* + * ZPD (R) + * + * Output impedance pull-down calibration status. Valid status encodings are: 00 = Completed with no errors + * 01 = Overflow error 10 = Underflow error + * 11 = Calibration in progress + */ +#define DDRPHY_ZQ_SR1_ZPD_MASK (0x3U) +#define DDRPHY_ZQ_SR1_ZPD_SHIFT (0U) +#define DDRPHY_ZQ_SR1_ZPD_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_SR1_ZPD_MASK) >> DDRPHY_ZQ_SR1_ZPD_SHIFT) + +/* Bitfield definition for register of struct array DX: GCR */ +/* + * CALBYP (R/W) + * + * Calibration Bypass: Prevents, if set, period measurement calibration from automatically triggering after PHY initialization. + */ +#define DDRPHY_DX_GCR_CALBYP_MASK (0x80000000UL) +#define DDRPHY_DX_GCR_CALBYP_SHIFT (31U) +#define DDRPHY_DX_GCR_CALBYP_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_CALBYP_SHIFT) & DDRPHY_DX_GCR_CALBYP_MASK) +#define DDRPHY_DX_GCR_CALBYP_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_CALBYP_MASK) >> DDRPHY_DX_GCR_CALBYP_SHIFT) + +/* + * MDLEN (R/W) + * + * Master Delay Line Enable: Enables, if set, the DATX8 master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or when calibration is manually triggered. These additional measurements are accumulated and filtered as long as this bit remains high. This bit is ANDed with the common DATX8 MDL enable bit. + */ +#define DDRPHY_DX_GCR_MDLEN_MASK (0x40000000UL) +#define DDRPHY_DX_GCR_MDLEN_SHIFT (30U) +#define DDRPHY_DX_GCR_MDLEN_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_MDLEN_SHIFT) & DDRPHY_DX_GCR_MDLEN_MASK) +#define DDRPHY_DX_GCR_MDLEN_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_MDLEN_MASK) >> DDRPHY_DX_GCR_MDLEN_SHIFT) + +/* + * WLRKEN (R/W) + * + * Write Level Rank Enable: Specifies the ranks that should be write leveled for this byte. Write leveling responses from ranks that are not enabled for write leveling for a particular byte are ignored and write leveling is flagged as done for these ranks. + * WLRKEN[0] enables rank 0, [1] enables rank 1, [2] enables rank 2, and [3] enables + * rank 3. + */ +#define DDRPHY_DX_GCR_WLRKEN_MASK (0x3C000000UL) +#define DDRPHY_DX_GCR_WLRKEN_SHIFT (26U) +#define DDRPHY_DX_GCR_WLRKEN_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_WLRKEN_SHIFT) & DDRPHY_DX_GCR_WLRKEN_MASK) +#define DDRPHY_DX_GCR_WLRKEN_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_WLRKEN_MASK) >> DDRPHY_DX_GCR_WLRKEN_SHIFT) + +/* + * PLLBYP (R/W) + * + * PLL Bypass: Puts the byte PLL in bypass mode by driving the PLL bypass pin. This bit is not self-clearing and a '0' must be written to de-assert the bypass. This bit is ORed with the global BYP configuration bit (see Table 3-10 on page 91). + */ +#define DDRPHY_DX_GCR_PLLBYP_MASK (0x80000UL) +#define DDRPHY_DX_GCR_PLLBYP_SHIFT (19U) +#define DDRPHY_DX_GCR_PLLBYP_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_PLLBYP_SHIFT) & DDRPHY_DX_GCR_PLLBYP_MASK) +#define DDRPHY_DX_GCR_PLLBYP_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_PLLBYP_MASK) >> DDRPHY_DX_GCR_PLLBYP_SHIFT) + +/* + * GSHIFT (R/W) + * + * Gear Shift: Enables, if set, rapid locking mode on the byte PLL. This bit is ORed with the global GSHIFT configuration bit (see Table 3-10 on page 91). + */ +#define DDRPHY_DX_GCR_GSHIFT_MASK (0x40000UL) +#define DDRPHY_DX_GCR_GSHIFT_SHIFT (18U) +#define DDRPHY_DX_GCR_GSHIFT_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_GSHIFT_SHIFT) & DDRPHY_DX_GCR_GSHIFT_MASK) +#define DDRPHY_DX_GCR_GSHIFT_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_GSHIFT_MASK) >> DDRPHY_DX_GCR_GSHIFT_SHIFT) + +/* + * PLLPD (R/W) + * + * PLL Power Down: Puts the byte PLL in power down mode by driving the PLL power down pin. This bit is not self-clearing and a '0' must be written to de-assert the power-down. This bit is ORed with the global PLLPD configuration bit (see + * Table 3-10 on page 91). + */ +#define DDRPHY_DX_GCR_PLLPD_MASK (0x20000UL) +#define DDRPHY_DX_GCR_PLLPD_SHIFT (17U) +#define DDRPHY_DX_GCR_PLLPD_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_PLLPD_SHIFT) & DDRPHY_DX_GCR_PLLPD_MASK) +#define DDRPHY_DX_GCR_PLLPD_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_PLLPD_MASK) >> DDRPHY_DX_GCR_PLLPD_SHIFT) + +/* + * PLLRST (R/W) + * + * PLL Rest: Resets the byte PLL by driving the PLL reset pin. This bit is not self- clearing and a '0' must be written to de-assert the reset. This bit is ORed with the global PLLRST configuration bit (see Table 3-10 on page 91). + */ +#define DDRPHY_DX_GCR_PLLRST_MASK (0x10000UL) +#define DDRPHY_DX_GCR_PLLRST_SHIFT (16U) +#define DDRPHY_DX_GCR_PLLRST_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_PLLRST_SHIFT) & DDRPHY_DX_GCR_PLLRST_MASK) +#define DDRPHY_DX_GCR_PLLRST_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_PLLRST_MASK) >> DDRPHY_DX_GCR_PLLRST_SHIFT) + +/* + * DXOEO (R/W) + * + * Data Byte Output Enable Override: Specifies whether the output I/O output enable for the byte lane should be set to a fixed value. Valid values are: + * 00 = No override. Output enable is controlled by DFI transactions 01 = Ouput enable is asserted (I/O is forced to output mode). + * 10 = Output enable is de-asserted (I/O is forced to input mode) 11 = Reserved + */ +#define DDRPHY_DX_GCR_DXOEO_MASK (0xC000U) +#define DDRPHY_DX_GCR_DXOEO_SHIFT (14U) +#define DDRPHY_DX_GCR_DXOEO_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_DXOEO_SHIFT) & DDRPHY_DX_GCR_DXOEO_MASK) +#define DDRPHY_DX_GCR_DXOEO_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_DXOEO_MASK) >> DDRPHY_DX_GCR_DXOEO_SHIFT) + +/* + * RTTOAL (R/W) + * + * RTT On Additive Latency: Indicates when the ODT control of DQ/DQS SSTL I/Os is set to the value in DQODT/DQSODT during read cycles. Valid values are: + * 0 = ODT control is set to DQSODT/DQODT almost two cycles before read data preamble + * 1 = ODT control is set to DQSODT/DQODT almost one cycle before read data preamble + */ +#define DDRPHY_DX_GCR_RTTOAL_MASK (0x2000U) +#define DDRPHY_DX_GCR_RTTOAL_SHIFT (13U) +#define DDRPHY_DX_GCR_RTTOAL_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_RTTOAL_SHIFT) & DDRPHY_DX_GCR_RTTOAL_MASK) +#define DDRPHY_DX_GCR_RTTOAL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_RTTOAL_MASK) >> DDRPHY_DX_GCR_RTTOAL_SHIFT) + +/* + * RTTOH (R/W) + * + * RTT Output Hold: Indicates the number of clock cycles (from 0 to 3) after the read data postamble for which ODT control should remain set to DQSODT for DQS or DQODT for DQ/DM before disabling it (setting it to ‘0’) when using dynamic ODT control. ODT is disabled almost RTTOH clock cycles after the read postamble. + */ +#define DDRPHY_DX_GCR_RTTOH_MASK (0x1800U) +#define DDRPHY_DX_GCR_RTTOH_SHIFT (11U) +#define DDRPHY_DX_GCR_RTTOH_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_RTTOH_SHIFT) & DDRPHY_DX_GCR_RTTOH_MASK) +#define DDRPHY_DX_GCR_RTTOH_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_RTTOH_MASK) >> DDRPHY_DX_GCR_RTTOH_SHIFT) + +/* + * DQRTT (R/W) + * + * DQ Dynamic RTT Control: If set, the on die termination (ODT) control of the DQ/DM SSTL I/O is dynamically generated to enable the ODT during read operation and disabled otherwise. By setting this bit to '0' the dynamic ODT feature is disabled. To control ODT statically this bit must be set to '0' and DXnGCR0[2] (DQODT) is used to enable ODT (when set to '1') or disable ODT(when set to '0'). + */ +#define DDRPHY_DX_GCR_DQRTT_MASK (0x400U) +#define DDRPHY_DX_GCR_DQRTT_SHIFT (10U) +#define DDRPHY_DX_GCR_DQRTT_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_DQRTT_SHIFT) & DDRPHY_DX_GCR_DQRTT_MASK) +#define DDRPHY_DX_GCR_DQRTT_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_DQRTT_MASK) >> DDRPHY_DX_GCR_DQRTT_SHIFT) + +/* + * DQSRTT (R/W) + * + * DQS Dynamic RTT Control: If set, the on die termination (ODT) control of the DQS/DQS# SSTL I/O is dynamically generated to enable the ODT during read operation and disabled otherwise. By setting this bit to '0' the dynamic ODT feature is disabled. To control ODT statically this bit must be set to '0' and DXnGCR0[1] (DQSODT) is used to enable ODT (when set to '1') or disable ODT(when set to '0'). + */ +#define DDRPHY_DX_GCR_DQSRTT_MASK (0x200U) +#define DDRPHY_DX_GCR_DQSRTT_SHIFT (9U) +#define DDRPHY_DX_GCR_DQSRTT_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_DQSRTT_SHIFT) & DDRPHY_DX_GCR_DQSRTT_MASK) +#define DDRPHY_DX_GCR_DQSRTT_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_DQSRTT_MASK) >> DDRPHY_DX_GCR_DQSRTT_SHIFT) + +/* + * DSEN (R/W) + * + * Write DQS Enable: Controls whether the write DQS going to the SDRAM is enabled (toggling) or disabled (static value) and whether the DQS is inverted. DQS# is always the inversion of DQS. These values are valid only when DQS/DQS# output enable is on, otherwise the DQS/DQS# is tristated. Valid settings are: + * 00 = Reserved + * 01 = DQS toggling with normal polarity (This should be the default setting) 10 = Reserved + * 11 = Reserved + */ +#define DDRPHY_DX_GCR_DSEN_MASK (0x180U) +#define DDRPHY_DX_GCR_DSEN_SHIFT (7U) +#define DDRPHY_DX_GCR_DSEN_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_DSEN_SHIFT) & DDRPHY_DX_GCR_DSEN_MASK) +#define DDRPHY_DX_GCR_DSEN_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_DSEN_MASK) >> DDRPHY_DX_GCR_DSEN_SHIFT) + +/* + * DQSRPD (R/W) + * + * DQSR Power Down: Powers down, if set, the PDQSR cell. This bit is ORed with the common PDR configuration bit (see “DATX8 Common Configuration Register (DXCCR)” on page 99) + */ +#define DDRPHY_DX_GCR_DQSRPD_MASK (0x40U) +#define DDRPHY_DX_GCR_DQSRPD_SHIFT (6U) +#define DDRPHY_DX_GCR_DQSRPD_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_DQSRPD_SHIFT) & DDRPHY_DX_GCR_DQSRPD_MASK) +#define DDRPHY_DX_GCR_DQSRPD_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_DQSRPD_MASK) >> DDRPHY_DX_GCR_DQSRPD_SHIFT) + +/* + * DXPDR (R/W) + * + * Data Power Down Receiver: Powers down, when set, the input receiver on I/O for DQ, DM, and DQS/DQS# pins of the byte. This bit is ORed with the common PDR configuration bit (see “DATX8 Common Configuration Register (DXCCR)” on page 99). + */ +#define DDRPHY_DX_GCR_DXPDR_MASK (0x20U) +#define DDRPHY_DX_GCR_DXPDR_SHIFT (5U) +#define DDRPHY_DX_GCR_DXPDR_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_DXPDR_SHIFT) & DDRPHY_DX_GCR_DXPDR_MASK) +#define DDRPHY_DX_GCR_DXPDR_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_DXPDR_MASK) >> DDRPHY_DX_GCR_DXPDR_SHIFT) + +/* + * DXPDD1 (R/W) + * + * Data Power Down Driver: Powers down, when set, the output driver on I/O for DQ, DM, and DQS/DQS# pins of the byte. This bit is ORed with the common PDD configuration bit (see “DATX8 Common Configuration Register (DXCCR)” on page 99). + */ +#define DDRPHY_DX_GCR_DXPDD1_MASK (0x10U) +#define DDRPHY_DX_GCR_DXPDD1_SHIFT (4U) +#define DDRPHY_DX_GCR_DXPDD1_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_DXPDD1_SHIFT) & DDRPHY_DX_GCR_DXPDD1_MASK) +#define DDRPHY_DX_GCR_DXPDD1_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_DXPDD1_MASK) >> DDRPHY_DX_GCR_DXPDD1_SHIFT) + +/* + * DXIOM (R/W) + * + * Data I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DQ, DM, and DQS/DQS# pins of the byte. This bit is ORed with the IOM configuration bit of the individual DATX8(see “DATX8 Common Configuration Register (DXCCR)” on page 99). + */ +#define DDRPHY_DX_GCR_DXIOM_MASK (0x8U) +#define DDRPHY_DX_GCR_DXIOM_SHIFT (3U) +#define DDRPHY_DX_GCR_DXIOM_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_DXIOM_SHIFT) & DDRPHY_DX_GCR_DXIOM_MASK) +#define DDRPHY_DX_GCR_DXIOM_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_DXIOM_MASK) >> DDRPHY_DX_GCR_DXIOM_SHIFT) + +/* + * DQODT (R/W) + * + * Data On-Die Termination: Enables, when set, the on-die termination on the I/O for DQ and DM pins of the byte. This bit is ORed with the common DATX8 ODT configuration bit (see “DATX8 Common Configuration Register (DXCCR)” on page 99). + * Note: This bit is only valid when DXnGCR0[10] is '0'. + */ +#define DDRPHY_DX_GCR_DQODT_MASK (0x4U) +#define DDRPHY_DX_GCR_DQODT_SHIFT (2U) +#define DDRPHY_DX_GCR_DQODT_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_DQODT_SHIFT) & DDRPHY_DX_GCR_DQODT_MASK) +#define DDRPHY_DX_GCR_DQODT_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_DQODT_MASK) >> DDRPHY_DX_GCR_DQODT_SHIFT) + +/* + * DQSODT (R/W) + * + * DQS On-Die Termination: Enables, when set, the on-die termination on the I/O for DQS/DQS# pin of the byte. This bit is ORed with the common DATX8 ODT configuration bit (see “DATX8 Common Configuration Register (DXCCR)” on page 99). + * Note: This bit is only valid when DXnGCR0[9] is '0'. + */ +#define DDRPHY_DX_GCR_DQSODT_MASK (0x2U) +#define DDRPHY_DX_GCR_DQSODT_SHIFT (1U) +#define DDRPHY_DX_GCR_DQSODT_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_DQSODT_SHIFT) & DDRPHY_DX_GCR_DQSODT_MASK) +#define DDRPHY_DX_GCR_DQSODT_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_DQSODT_MASK) >> DDRPHY_DX_GCR_DQSODT_SHIFT) + +/* + * DXEN (R/W) + * + * Data Byte Enable: Enables, if set, the data byte. Setting this bit to '0' disables the byte, i.e. the byte is not used in PHY initialization or training and is ignored during SDRAM read/write operations. + */ +#define DDRPHY_DX_GCR_DXEN_MASK (0x1U) +#define DDRPHY_DX_GCR_DXEN_SHIFT (0U) +#define DDRPHY_DX_GCR_DXEN_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_DXEN_SHIFT) & DDRPHY_DX_GCR_DXEN_MASK) +#define DDRPHY_DX_GCR_DXEN_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_DXEN_MASK) >> DDRPHY_DX_GCR_DXEN_SHIFT) + +/* Bitfield definition for register of struct array DX: GSR0 */ +/* + * WLDQ (R) + * + * Write Leveling DQ Status: Captures the write leveling DQ status from the DRAM during software write leveling. + */ +#define DDRPHY_DX_GSR0_WLDQ_MASK (0x10000000UL) +#define DDRPHY_DX_GSR0_WLDQ_SHIFT (28U) +#define DDRPHY_DX_GSR0_WLDQ_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_WLDQ_MASK) >> DDRPHY_DX_GSR0_WLDQ_SHIFT) + +/* + * QSGERR (R) + * + * DQS Gate Training Error: Indicates, if set, that there is an error in DQS gate training. One bit for each of the up to 4 ranks. + */ +#define DDRPHY_DX_GSR0_QSGERR_MASK (0xF000000UL) +#define DDRPHY_DX_GSR0_QSGERR_SHIFT (24U) +#define DDRPHY_DX_GSR0_QSGERR_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_QSGERR_MASK) >> DDRPHY_DX_GSR0_QSGERR_SHIFT) + +/* + * GDQSPRD (R) + * + * Read DQS gating Period: Returns the DDR clock period measured by the read DQS gating LCDL during calibration. This value is PVT compensated. + */ +#define DDRPHY_DX_GSR0_GDQSPRD_MASK (0xFF0000UL) +#define DDRPHY_DX_GSR0_GDQSPRD_SHIFT (16U) +#define DDRPHY_DX_GSR0_GDQSPRD_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_GDQSPRD_MASK) >> DDRPHY_DX_GSR0_GDQSPRD_SHIFT) + +/* + * DPLOCK (R) + * + * DATX8 PLL Lock: Indicates, if set, that the DATX8 PLL has locked. This is a direct status of the DATX8 PLL lock pin. + */ +#define DDRPHY_DX_GSR0_DPLOCK_MASK (0x8000U) +#define DDRPHY_DX_GSR0_DPLOCK_SHIFT (15U) +#define DDRPHY_DX_GSR0_DPLOCK_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_DPLOCK_MASK) >> DDRPHY_DX_GSR0_DPLOCK_SHIFT) + +/* + * WLPRD (R) + * + * Write Leveling Period: Returns the DDR clock period measured by the write leveling LCDL during calibration. The measured period is used to generate the control of the write leveling pipeline which is a function of the write-leveling delay and the clock period. This value is PVT compensated. + */ +#define DDRPHY_DX_GSR0_WLPRD_MASK (0x7F80U) +#define DDRPHY_DX_GSR0_WLPRD_SHIFT (7U) +#define DDRPHY_DX_GSR0_WLPRD_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_WLPRD_MASK) >> DDRPHY_DX_GSR0_WLPRD_SHIFT) + +/* + * WLERR (R) + * + * Write Leveling Error: Indicates, if set, that there is a write leveling error in the DATX8. + */ +#define DDRPHY_DX_GSR0_WLERR_MASK (0x40U) +#define DDRPHY_DX_GSR0_WLERR_SHIFT (6U) +#define DDRPHY_DX_GSR0_WLERR_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_WLERR_MASK) >> DDRPHY_DX_GSR0_WLERR_SHIFT) + +/* + * WLDONE (R) + * + * Write Leveling Done: Indicates, if set, that the DATX8 has completed write leveling. + */ +#define DDRPHY_DX_GSR0_WLDONE_MASK (0x20U) +#define DDRPHY_DX_GSR0_WLDONE_SHIFT (5U) +#define DDRPHY_DX_GSR0_WLDONE_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_WLDONE_MASK) >> DDRPHY_DX_GSR0_WLDONE_SHIFT) + +/* + * WLCAL (R) + * + * Write Leveling Calibration: Indicates, if set, that the DATX8 has finished doing period measurement calibration for the write leveling slave delay line. + */ +#define DDRPHY_DX_GSR0_WLCAL_MASK (0x10U) +#define DDRPHY_DX_GSR0_WLCAL_SHIFT (4U) +#define DDRPHY_DX_GSR0_WLCAL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_WLCAL_MASK) >> DDRPHY_DX_GSR0_WLCAL_SHIFT) + +/* + * GDQSCAL (R) + * + * Read DQS gating Calibration: Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS gating LCDL. + */ +#define DDRPHY_DX_GSR0_GDQSCAL_MASK (0x8U) +#define DDRPHY_DX_GSR0_GDQSCAL_SHIFT (3U) +#define DDRPHY_DX_GSR0_GDQSCAL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_GDQSCAL_MASK) >> DDRPHY_DX_GSR0_GDQSCAL_SHIFT) + +/* + * RDQSNCAL (R) + * + * Read DQS# Calibration (Type B/B1 PHY Only): Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS# LCDL. + */ +#define DDRPHY_DX_GSR0_RDQSNCAL_MASK (0x4U) +#define DDRPHY_DX_GSR0_RDQSNCAL_SHIFT (2U) +#define DDRPHY_DX_GSR0_RDQSNCAL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_RDQSNCAL_MASK) >> DDRPHY_DX_GSR0_RDQSNCAL_SHIFT) + +/* + * RDQSCAL (R) + * + * Read DQS Calibration: Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS LCDL. + */ +#define DDRPHY_DX_GSR0_RDQSCAL_MASK (0x2U) +#define DDRPHY_DX_GSR0_RDQSCAL_SHIFT (1U) +#define DDRPHY_DX_GSR0_RDQSCAL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_RDQSCAL_MASK) >> DDRPHY_DX_GSR0_RDQSCAL_SHIFT) + +/* + * WDQCAL (R) + * + * Write DQ Calibration: Indicates, if set, that the DATX8 has finished doing period measurement calibration for the write DQ LCDL. + */ +#define DDRPHY_DX_GSR0_WDQCAL_MASK (0x1U) +#define DDRPHY_DX_GSR0_WDQCAL_SHIFT (0U) +#define DDRPHY_DX_GSR0_WDQCAL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_WDQCAL_MASK) >> DDRPHY_DX_GSR0_WDQCAL_SHIFT) + +/* Bitfield definition for register of struct array DX: GSR1 */ +/* + * DLTCODE (R) + * + * Delay Line Test Code: Returns the code measured by the PHY control block that corresponds to the period of the DATX8 delay line digital test output. + */ +#define DDRPHY_DX_GSR1_DLTCODE_MASK (0x1FFFFFEUL) +#define DDRPHY_DX_GSR1_DLTCODE_SHIFT (1U) +#define DDRPHY_DX_GSR1_DLTCODE_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR1_DLTCODE_MASK) >> DDRPHY_DX_GSR1_DLTCODE_SHIFT) + +/* + * DLTDONE (R) + * + * Delay Line Test Done: Indicates, if set, that the PHY control block has finished doing period measurement of the DATX8 delay line digital test output. + */ +#define DDRPHY_DX_GSR1_DLTDONE_MASK (0x1U) +#define DDRPHY_DX_GSR1_DLTDONE_SHIFT (0U) +#define DDRPHY_DX_GSR1_DLTDONE_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR1_DLTDONE_MASK) >> DDRPHY_DX_GSR1_DLTDONE_SHIFT) + +/* Bitfield definition for register of struct array DX: BDLR0 */ +/* + * DQ4WBD (R/W) + * + * DQ4 Write Bit Delay: Delay select for the BDL on DQ4 write path. + */ +#define DDRPHY_DX_BDLR0_DQ4WBD_MASK (0x3F000000UL) +#define DDRPHY_DX_BDLR0_DQ4WBD_SHIFT (24U) +#define DDRPHY_DX_BDLR0_DQ4WBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR0_DQ4WBD_SHIFT) & DDRPHY_DX_BDLR0_DQ4WBD_MASK) +#define DDRPHY_DX_BDLR0_DQ4WBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR0_DQ4WBD_MASK) >> DDRPHY_DX_BDLR0_DQ4WBD_SHIFT) + +/* + * DQ3WBD (R/W) + * + * DQ3 Write Bit Delay: Delay select for the BDL on DQ3 write path + */ +#define DDRPHY_DX_BDLR0_DQ3WBD_MASK (0xFC0000UL) +#define DDRPHY_DX_BDLR0_DQ3WBD_SHIFT (18U) +#define DDRPHY_DX_BDLR0_DQ3WBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR0_DQ3WBD_SHIFT) & DDRPHY_DX_BDLR0_DQ3WBD_MASK) +#define DDRPHY_DX_BDLR0_DQ3WBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR0_DQ3WBD_MASK) >> DDRPHY_DX_BDLR0_DQ3WBD_SHIFT) + +/* + * DQ2WBD (R/W) + * + * DQ2 Write Bit Delay: Delay select for the BDL on DQ2 write path. + */ +#define DDRPHY_DX_BDLR0_DQ2WBD_MASK (0x3F000UL) +#define DDRPHY_DX_BDLR0_DQ2WBD_SHIFT (12U) +#define DDRPHY_DX_BDLR0_DQ2WBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR0_DQ2WBD_SHIFT) & DDRPHY_DX_BDLR0_DQ2WBD_MASK) +#define DDRPHY_DX_BDLR0_DQ2WBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR0_DQ2WBD_MASK) >> DDRPHY_DX_BDLR0_DQ2WBD_SHIFT) + +/* + * DQ1WBD (R/W) + * + * DQ1 Write Bit Delay: Delay select for the BDL on DQ1 write path. + */ +#define DDRPHY_DX_BDLR0_DQ1WBD_MASK (0xFC0U) +#define DDRPHY_DX_BDLR0_DQ1WBD_SHIFT (6U) +#define DDRPHY_DX_BDLR0_DQ1WBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR0_DQ1WBD_SHIFT) & DDRPHY_DX_BDLR0_DQ1WBD_MASK) +#define DDRPHY_DX_BDLR0_DQ1WBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR0_DQ1WBD_MASK) >> DDRPHY_DX_BDLR0_DQ1WBD_SHIFT) + +/* + * DQ0WBD (R/W) + * + * DQ0 Write Bit Delay: Delay select for the BDL on DQ0 write path. + */ +#define DDRPHY_DX_BDLR0_DQ0WBD_MASK (0x3FU) +#define DDRPHY_DX_BDLR0_DQ0WBD_SHIFT (0U) +#define DDRPHY_DX_BDLR0_DQ0WBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR0_DQ0WBD_SHIFT) & DDRPHY_DX_BDLR0_DQ0WBD_MASK) +#define DDRPHY_DX_BDLR0_DQ0WBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR0_DQ0WBD_MASK) >> DDRPHY_DX_BDLR0_DQ0WBD_SHIFT) + +/* Bitfield definition for register of struct array DX: BDLR1 */ +/* + * DSWBD (R/W) + * + * DQS Write Bit Delay: Delay select for the BDL on DQS write path + */ +#define DDRPHY_DX_BDLR1_DSWBD_MASK (0x3F000000UL) +#define DDRPHY_DX_BDLR1_DSWBD_SHIFT (24U) +#define DDRPHY_DX_BDLR1_DSWBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR1_DSWBD_SHIFT) & DDRPHY_DX_BDLR1_DSWBD_MASK) +#define DDRPHY_DX_BDLR1_DSWBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR1_DSWBD_MASK) >> DDRPHY_DX_BDLR1_DSWBD_SHIFT) + +/* + * DMWBD (R/W) + * + * DM Write Bit Delay: Delay select for the BDL on DM write path. + */ +#define DDRPHY_DX_BDLR1_DMWBD_MASK (0xFC0000UL) +#define DDRPHY_DX_BDLR1_DMWBD_SHIFT (18U) +#define DDRPHY_DX_BDLR1_DMWBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR1_DMWBD_SHIFT) & DDRPHY_DX_BDLR1_DMWBD_MASK) +#define DDRPHY_DX_BDLR1_DMWBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR1_DMWBD_MASK) >> DDRPHY_DX_BDLR1_DMWBD_SHIFT) + +/* + * DQ7WBD (R/W) + * + * DQ7 Write Bit Delay: Delay select for the BDL on DQ7 write path. + */ +#define DDRPHY_DX_BDLR1_DQ7WBD_MASK (0x3F000UL) +#define DDRPHY_DX_BDLR1_DQ7WBD_SHIFT (12U) +#define DDRPHY_DX_BDLR1_DQ7WBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR1_DQ7WBD_SHIFT) & DDRPHY_DX_BDLR1_DQ7WBD_MASK) +#define DDRPHY_DX_BDLR1_DQ7WBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR1_DQ7WBD_MASK) >> DDRPHY_DX_BDLR1_DQ7WBD_SHIFT) + +/* + * DQ6WBD (R/W) + * + * DQ6 Write Bit Delay: Delay select for the BDL on DQ6 write path. + */ +#define DDRPHY_DX_BDLR1_DQ6WBD_MASK (0xFC0U) +#define DDRPHY_DX_BDLR1_DQ6WBD_SHIFT (6U) +#define DDRPHY_DX_BDLR1_DQ6WBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR1_DQ6WBD_SHIFT) & DDRPHY_DX_BDLR1_DQ6WBD_MASK) +#define DDRPHY_DX_BDLR1_DQ6WBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR1_DQ6WBD_MASK) >> DDRPHY_DX_BDLR1_DQ6WBD_SHIFT) + +/* + * DQ5WBD (R/W) + * + * DQ5 Write Bit Delay: Delay select for the BDL on DQ5 write path. + */ +#define DDRPHY_DX_BDLR1_DQ5WBD_MASK (0x3FU) +#define DDRPHY_DX_BDLR1_DQ5WBD_SHIFT (0U) +#define DDRPHY_DX_BDLR1_DQ5WBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR1_DQ5WBD_SHIFT) & DDRPHY_DX_BDLR1_DQ5WBD_MASK) +#define DDRPHY_DX_BDLR1_DQ5WBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR1_DQ5WBD_MASK) >> DDRPHY_DX_BDLR1_DQ5WBD_SHIFT) + +/* Bitfield definition for register of struct array DX: BDLR2 */ +/* + * DSNRBD (R/W) + * + * DQSN Read Bit Delay (Type B/B1 PHY Only): Delay select for the BDL on DQSN read path + */ +#define DDRPHY_DX_BDLR2_DSNRBD_MASK (0xFC0000UL) +#define DDRPHY_DX_BDLR2_DSNRBD_SHIFT (18U) +#define DDRPHY_DX_BDLR2_DSNRBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR2_DSNRBD_SHIFT) & DDRPHY_DX_BDLR2_DSNRBD_MASK) +#define DDRPHY_DX_BDLR2_DSNRBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR2_DSNRBD_MASK) >> DDRPHY_DX_BDLR2_DSNRBD_SHIFT) + +/* + * DSRBD (R/W) + * + * DQS Read Bit Delay: Delay select for the BDL on DQS read path + */ +#define DDRPHY_DX_BDLR2_DSRBD_MASK (0x3F000UL) +#define DDRPHY_DX_BDLR2_DSRBD_SHIFT (12U) +#define DDRPHY_DX_BDLR2_DSRBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR2_DSRBD_SHIFT) & DDRPHY_DX_BDLR2_DSRBD_MASK) +#define DDRPHY_DX_BDLR2_DSRBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR2_DSRBD_MASK) >> DDRPHY_DX_BDLR2_DSRBD_SHIFT) + +/* + * DQOEBD (R/W) + * + * DQ Output Enable Bit Delay: Delay select for the BDL on DQ/DM output enable path. + */ +#define DDRPHY_DX_BDLR2_DQOEBD_MASK (0xFC0U) +#define DDRPHY_DX_BDLR2_DQOEBD_SHIFT (6U) +#define DDRPHY_DX_BDLR2_DQOEBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR2_DQOEBD_SHIFT) & DDRPHY_DX_BDLR2_DQOEBD_MASK) +#define DDRPHY_DX_BDLR2_DQOEBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR2_DQOEBD_MASK) >> DDRPHY_DX_BDLR2_DQOEBD_SHIFT) + +/* + * DSOEBD (R/W) + * + * DQS Output Enable Bit Delay: Delay select for the BDL on DQS output enable path + */ +#define DDRPHY_DX_BDLR2_DSOEBD_MASK (0x3FU) +#define DDRPHY_DX_BDLR2_DSOEBD_SHIFT (0U) +#define DDRPHY_DX_BDLR2_DSOEBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR2_DSOEBD_SHIFT) & DDRPHY_DX_BDLR2_DSOEBD_MASK) +#define DDRPHY_DX_BDLR2_DSOEBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR2_DSOEBD_MASK) >> DDRPHY_DX_BDLR2_DSOEBD_SHIFT) + +/* Bitfield definition for register of struct array DX: BDLR3 */ +/* + * DQ4RBD (R/W) + * + * DQ4 Read Bit Delay: Delay select for the BDL on DQ4 read path. + */ +#define DDRPHY_DX_BDLR3_DQ4RBD_MASK (0x3F000000UL) +#define DDRPHY_DX_BDLR3_DQ4RBD_SHIFT (24U) +#define DDRPHY_DX_BDLR3_DQ4RBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR3_DQ4RBD_SHIFT) & DDRPHY_DX_BDLR3_DQ4RBD_MASK) +#define DDRPHY_DX_BDLR3_DQ4RBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR3_DQ4RBD_MASK) >> DDRPHY_DX_BDLR3_DQ4RBD_SHIFT) + +/* + * DQ3RBD (R/W) + * + * DQ3 Read Bit Delay: Delay select for the BDL on DQ3 read path + */ +#define DDRPHY_DX_BDLR3_DQ3RBD_MASK (0xFC0000UL) +#define DDRPHY_DX_BDLR3_DQ3RBD_SHIFT (18U) +#define DDRPHY_DX_BDLR3_DQ3RBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR3_DQ3RBD_SHIFT) & DDRPHY_DX_BDLR3_DQ3RBD_MASK) +#define DDRPHY_DX_BDLR3_DQ3RBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR3_DQ3RBD_MASK) >> DDRPHY_DX_BDLR3_DQ3RBD_SHIFT) + +/* + * DQ2RBD (R/W) + * + * DQ2 Read Bit Delay: Delay select for the BDL on DQ2 read path. + */ +#define DDRPHY_DX_BDLR3_DQ2RBD_MASK (0x3F000UL) +#define DDRPHY_DX_BDLR3_DQ2RBD_SHIFT (12U) +#define DDRPHY_DX_BDLR3_DQ2RBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR3_DQ2RBD_SHIFT) & DDRPHY_DX_BDLR3_DQ2RBD_MASK) +#define DDRPHY_DX_BDLR3_DQ2RBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR3_DQ2RBD_MASK) >> DDRPHY_DX_BDLR3_DQ2RBD_SHIFT) + +/* + * DQ1RBD (R/W) + * + * DQ1 Read Bit Delay: Delay select for the BDL on DQ1 read path. + */ +#define DDRPHY_DX_BDLR3_DQ1RBD_MASK (0xFC0U) +#define DDRPHY_DX_BDLR3_DQ1RBD_SHIFT (6U) +#define DDRPHY_DX_BDLR3_DQ1RBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR3_DQ1RBD_SHIFT) & DDRPHY_DX_BDLR3_DQ1RBD_MASK) +#define DDRPHY_DX_BDLR3_DQ1RBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR3_DQ1RBD_MASK) >> DDRPHY_DX_BDLR3_DQ1RBD_SHIFT) + +/* + * DQ0RBD (R/W) + * + * DQ0 Read Bit Delay: Delay select for the BDL on DQ0 read path. + */ +#define DDRPHY_DX_BDLR3_DQ0RBD_MASK (0x3FU) +#define DDRPHY_DX_BDLR3_DQ0RBD_SHIFT (0U) +#define DDRPHY_DX_BDLR3_DQ0RBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR3_DQ0RBD_SHIFT) & DDRPHY_DX_BDLR3_DQ0RBD_MASK) +#define DDRPHY_DX_BDLR3_DQ0RBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR3_DQ0RBD_MASK) >> DDRPHY_DX_BDLR3_DQ0RBD_SHIFT) + +/* Bitfield definition for register of struct array DX: BDLR4 */ +/* + * DMRBD (R/W) + * + * DM Read Bit Delay: Delay select for the BDL on DM read path. + */ +#define DDRPHY_DX_BDLR4_DMRBD_MASK (0xFC0000UL) +#define DDRPHY_DX_BDLR4_DMRBD_SHIFT (18U) +#define DDRPHY_DX_BDLR4_DMRBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR4_DMRBD_SHIFT) & DDRPHY_DX_BDLR4_DMRBD_MASK) +#define DDRPHY_DX_BDLR4_DMRBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR4_DMRBD_MASK) >> DDRPHY_DX_BDLR4_DMRBD_SHIFT) + +/* + * DQ7RBD (R/W) + * + * DQ7 Read Bit Delay: Delay select for the BDL on DQ7 read path. + */ +#define DDRPHY_DX_BDLR4_DQ7RBD_MASK (0x3F000UL) +#define DDRPHY_DX_BDLR4_DQ7RBD_SHIFT (12U) +#define DDRPHY_DX_BDLR4_DQ7RBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR4_DQ7RBD_SHIFT) & DDRPHY_DX_BDLR4_DQ7RBD_MASK) +#define DDRPHY_DX_BDLR4_DQ7RBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR4_DQ7RBD_MASK) >> DDRPHY_DX_BDLR4_DQ7RBD_SHIFT) + +/* + * DQ6RBD (R/W) + * + * DQ6 Read Bit Delay: Delay select for the BDL on DQ6 read path. + */ +#define DDRPHY_DX_BDLR4_DQ6RBD_MASK (0xFC0U) +#define DDRPHY_DX_BDLR4_DQ6RBD_SHIFT (6U) +#define DDRPHY_DX_BDLR4_DQ6RBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR4_DQ6RBD_SHIFT) & DDRPHY_DX_BDLR4_DQ6RBD_MASK) +#define DDRPHY_DX_BDLR4_DQ6RBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR4_DQ6RBD_MASK) >> DDRPHY_DX_BDLR4_DQ6RBD_SHIFT) + +/* + * DQ5RBD (R/W) + * + * DQ5 Read Bit Delay: Delay select for the BDL on DQ5 read path. + */ +#define DDRPHY_DX_BDLR4_DQ5RBD_MASK (0x3FU) +#define DDRPHY_DX_BDLR4_DQ5RBD_SHIFT (0U) +#define DDRPHY_DX_BDLR4_DQ5RBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR4_DQ5RBD_SHIFT) & DDRPHY_DX_BDLR4_DQ5RBD_MASK) +#define DDRPHY_DX_BDLR4_DQ5RBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR4_DQ5RBD_MASK) >> DDRPHY_DX_BDLR4_DQ5RBD_SHIFT) + +/* Bitfield definition for register of struct array DX: LCDLR0 */ +/* + * R3WLD (R/W) + * + * Rank 3 Write Leveling Delay: Rank 3 delay select for the write leveling (WL) LCDL + */ +#define DDRPHY_DX_LCDLR0_R3WLD_MASK (0xFF000000UL) +#define DDRPHY_DX_LCDLR0_R3WLD_SHIFT (24U) +#define DDRPHY_DX_LCDLR0_R3WLD_SET(x) (((uint32_t)(x) << DDRPHY_DX_LCDLR0_R3WLD_SHIFT) & DDRPHY_DX_LCDLR0_R3WLD_MASK) +#define DDRPHY_DX_LCDLR0_R3WLD_GET(x) (((uint32_t)(x) & DDRPHY_DX_LCDLR0_R3WLD_MASK) >> DDRPHY_DX_LCDLR0_R3WLD_SHIFT) + +/* + * R2WLD (R/W) + * + * Rank 2 Write Leveling Delay: Rank 2 delay select for the write leveling (WL) LCDL + */ +#define DDRPHY_DX_LCDLR0_R2WLD_MASK (0xFF0000UL) +#define DDRPHY_DX_LCDLR0_R2WLD_SHIFT (16U) +#define DDRPHY_DX_LCDLR0_R2WLD_SET(x) (((uint32_t)(x) << DDRPHY_DX_LCDLR0_R2WLD_SHIFT) & DDRPHY_DX_LCDLR0_R2WLD_MASK) +#define DDRPHY_DX_LCDLR0_R2WLD_GET(x) (((uint32_t)(x) & DDRPHY_DX_LCDLR0_R2WLD_MASK) >> DDRPHY_DX_LCDLR0_R2WLD_SHIFT) + +/* + * R1WLD (R/W) + * + * Rank 1 Write Leveling Delay: Rank 1 delay select for the write leveling (WL) LCDL + */ +#define DDRPHY_DX_LCDLR0_R1WLD_MASK (0xFF00U) +#define DDRPHY_DX_LCDLR0_R1WLD_SHIFT (8U) +#define DDRPHY_DX_LCDLR0_R1WLD_SET(x) (((uint32_t)(x) << DDRPHY_DX_LCDLR0_R1WLD_SHIFT) & DDRPHY_DX_LCDLR0_R1WLD_MASK) +#define DDRPHY_DX_LCDLR0_R1WLD_GET(x) (((uint32_t)(x) & DDRPHY_DX_LCDLR0_R1WLD_MASK) >> DDRPHY_DX_LCDLR0_R1WLD_SHIFT) + +/* + * R0WLD (R/W) + * + * Rank 0 Write Leveling Delay: Rank 0 delay select for the write leveling (WL) LCDL + */ +#define DDRPHY_DX_LCDLR0_R0WLD_MASK (0xFFU) +#define DDRPHY_DX_LCDLR0_R0WLD_SHIFT (0U) +#define DDRPHY_DX_LCDLR0_R0WLD_SET(x) (((uint32_t)(x) << DDRPHY_DX_LCDLR0_R0WLD_SHIFT) & DDRPHY_DX_LCDLR0_R0WLD_MASK) +#define DDRPHY_DX_LCDLR0_R0WLD_GET(x) (((uint32_t)(x) & DDRPHY_DX_LCDLR0_R0WLD_MASK) >> DDRPHY_DX_LCDLR0_R0WLD_SHIFT) + +/* Bitfield definition for register of struct array DX: LCDLR1 */ +/* + * RDQSND (R/W) + * + * Read DQSN Delay (Type B/B1 PHY Only): Delay select for the read DQSN (RDQS) LCDL + */ +#define DDRPHY_DX_LCDLR1_RDQSND_MASK (0xFF0000UL) +#define DDRPHY_DX_LCDLR1_RDQSND_SHIFT (16U) +#define DDRPHY_DX_LCDLR1_RDQSND_SET(x) (((uint32_t)(x) << DDRPHY_DX_LCDLR1_RDQSND_SHIFT) & DDRPHY_DX_LCDLR1_RDQSND_MASK) +#define DDRPHY_DX_LCDLR1_RDQSND_GET(x) (((uint32_t)(x) & DDRPHY_DX_LCDLR1_RDQSND_MASK) >> DDRPHY_DX_LCDLR1_RDQSND_SHIFT) + +/* + * RDQSD (R/W) + * + * Read DQS Delay: Delay select for the read DQS (RDQS) LCDL + */ +#define DDRPHY_DX_LCDLR1_RDQSD_MASK (0xFF00U) +#define DDRPHY_DX_LCDLR1_RDQSD_SHIFT (8U) +#define DDRPHY_DX_LCDLR1_RDQSD_SET(x) (((uint32_t)(x) << DDRPHY_DX_LCDLR1_RDQSD_SHIFT) & DDRPHY_DX_LCDLR1_RDQSD_MASK) +#define DDRPHY_DX_LCDLR1_RDQSD_GET(x) (((uint32_t)(x) & DDRPHY_DX_LCDLR1_RDQSD_MASK) >> DDRPHY_DX_LCDLR1_RDQSD_SHIFT) + +/* + * WDQD (R/W) + * + * Write Data Delay: Delay select for the write data (WDQ) LCDL + */ +#define DDRPHY_DX_LCDLR1_WDQD_MASK (0xFFU) +#define DDRPHY_DX_LCDLR1_WDQD_SHIFT (0U) +#define DDRPHY_DX_LCDLR1_WDQD_SET(x) (((uint32_t)(x) << DDRPHY_DX_LCDLR1_WDQD_SHIFT) & DDRPHY_DX_LCDLR1_WDQD_MASK) +#define DDRPHY_DX_LCDLR1_WDQD_GET(x) (((uint32_t)(x) & DDRPHY_DX_LCDLR1_WDQD_MASK) >> DDRPHY_DX_LCDLR1_WDQD_SHIFT) + +/* Bitfield definition for register of struct array DX: LCDLR2 */ +/* + * R3DQSGD (R/W) + * + * Rank 3 Read DQS Gating Delay: Rank 3 delay select for the read DQS gating (DQSG) LCDL + */ +#define DDRPHY_DX_LCDLR2_R3DQSGD_MASK (0xFF000000UL) +#define DDRPHY_DX_LCDLR2_R3DQSGD_SHIFT (24U) +#define DDRPHY_DX_LCDLR2_R3DQSGD_SET(x) (((uint32_t)(x) << DDRPHY_DX_LCDLR2_R3DQSGD_SHIFT) & DDRPHY_DX_LCDLR2_R3DQSGD_MASK) +#define DDRPHY_DX_LCDLR2_R3DQSGD_GET(x) (((uint32_t)(x) & DDRPHY_DX_LCDLR2_R3DQSGD_MASK) >> DDRPHY_DX_LCDLR2_R3DQSGD_SHIFT) + +/* + * R2DQSGD (R/W) + * + * Rank 2 Read DQS Gating Delay: Rank 2 delay select for the read DQS gating (DQSG) LCDL + */ +#define DDRPHY_DX_LCDLR2_R2DQSGD_MASK (0xFF0000UL) +#define DDRPHY_DX_LCDLR2_R2DQSGD_SHIFT (16U) +#define DDRPHY_DX_LCDLR2_R2DQSGD_SET(x) (((uint32_t)(x) << DDRPHY_DX_LCDLR2_R2DQSGD_SHIFT) & DDRPHY_DX_LCDLR2_R2DQSGD_MASK) +#define DDRPHY_DX_LCDLR2_R2DQSGD_GET(x) (((uint32_t)(x) & DDRPHY_DX_LCDLR2_R2DQSGD_MASK) >> DDRPHY_DX_LCDLR2_R2DQSGD_SHIFT) + +/* + * R1DQSGD (R/W) + * + * Rank 1 Read DQS Gating Delay: Rank 1 delay select for the read DQS gating (DQSG) LCDL + */ +#define DDRPHY_DX_LCDLR2_R1DQSGD_MASK (0xFF00U) +#define DDRPHY_DX_LCDLR2_R1DQSGD_SHIFT (8U) +#define DDRPHY_DX_LCDLR2_R1DQSGD_SET(x) (((uint32_t)(x) << DDRPHY_DX_LCDLR2_R1DQSGD_SHIFT) & DDRPHY_DX_LCDLR2_R1DQSGD_MASK) +#define DDRPHY_DX_LCDLR2_R1DQSGD_GET(x) (((uint32_t)(x) & DDRPHY_DX_LCDLR2_R1DQSGD_MASK) >> DDRPHY_DX_LCDLR2_R1DQSGD_SHIFT) + +/* + * R0DQSGD (R/W) + * + * Rank 0 Read DQS Gating Delay: Rank 0 delay select for the read DQS gating (DQSG) LCDL + */ +#define DDRPHY_DX_LCDLR2_R0DQSGD_MASK (0xFFU) +#define DDRPHY_DX_LCDLR2_R0DQSGD_SHIFT (0U) +#define DDRPHY_DX_LCDLR2_R0DQSGD_SET(x) (((uint32_t)(x) << DDRPHY_DX_LCDLR2_R0DQSGD_SHIFT) & DDRPHY_DX_LCDLR2_R0DQSGD_MASK) +#define DDRPHY_DX_LCDLR2_R0DQSGD_GET(x) (((uint32_t)(x) & DDRPHY_DX_LCDLR2_R0DQSGD_MASK) >> DDRPHY_DX_LCDLR2_R0DQSGD_SHIFT) + +/* Bitfield definition for register of struct array DX: MDLR */ +/* + * MDLD (R/W) + * + * MDL Delay: Delay select for the LCDL for the Master Delay Line. + */ +#define DDRPHY_DX_MDLR_MDLD_MASK (0xFF0000UL) +#define DDRPHY_DX_MDLR_MDLD_SHIFT (16U) +#define DDRPHY_DX_MDLR_MDLD_SET(x) (((uint32_t)(x) << DDRPHY_DX_MDLR_MDLD_SHIFT) & DDRPHY_DX_MDLR_MDLD_MASK) +#define DDRPHY_DX_MDLR_MDLD_GET(x) (((uint32_t)(x) & DDRPHY_DX_MDLR_MDLD_MASK) >> DDRPHY_DX_MDLR_MDLD_SHIFT) + +/* + * TPRD (R/W) + * + * Target Period: Target period measured by the master delay line calibration for VT drift compensation. This is the current measured value of the period and is continuously updated if the MDL is enabled to do so. + */ +#define DDRPHY_DX_MDLR_TPRD_MASK (0xFF00U) +#define DDRPHY_DX_MDLR_TPRD_SHIFT (8U) +#define DDRPHY_DX_MDLR_TPRD_SET(x) (((uint32_t)(x) << DDRPHY_DX_MDLR_TPRD_SHIFT) & DDRPHY_DX_MDLR_TPRD_MASK) +#define DDRPHY_DX_MDLR_TPRD_GET(x) (((uint32_t)(x) & DDRPHY_DX_MDLR_TPRD_MASK) >> DDRPHY_DX_MDLR_TPRD_SHIFT) + +/* + * IPRD (R/W) + * + * Initial Period: Initial period measured by the master delay line calibration for VT drift compensation. This value is used as the denominator when calculating the ratios of updates during VT compensation. + */ +#define DDRPHY_DX_MDLR_IPRD_MASK (0xFFU) +#define DDRPHY_DX_MDLR_IPRD_SHIFT (0U) +#define DDRPHY_DX_MDLR_IPRD_SET(x) (((uint32_t)(x) << DDRPHY_DX_MDLR_IPRD_SHIFT) & DDRPHY_DX_MDLR_IPRD_MASK) +#define DDRPHY_DX_MDLR_IPRD_GET(x) (((uint32_t)(x) & DDRPHY_DX_MDLR_IPRD_MASK) >> DDRPHY_DX_MDLR_IPRD_SHIFT) + +/* Bitfield definition for register of struct array DX: GTR */ +/* + * R3WLSL (R/W) + * + */ +#define DDRPHY_DX_GTR_R3WLSL_MASK (0xC0000UL) +#define DDRPHY_DX_GTR_R3WLSL_SHIFT (18U) +#define DDRPHY_DX_GTR_R3WLSL_SET(x) (((uint32_t)(x) << DDRPHY_DX_GTR_R3WLSL_SHIFT) & DDRPHY_DX_GTR_R3WLSL_MASK) +#define DDRPHY_DX_GTR_R3WLSL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GTR_R3WLSL_MASK) >> DDRPHY_DX_GTR_R3WLSL_SHIFT) + +/* + * R2WLSL (R/W) + * + */ +#define DDRPHY_DX_GTR_R2WLSL_MASK (0x30000UL) +#define DDRPHY_DX_GTR_R2WLSL_SHIFT (16U) +#define DDRPHY_DX_GTR_R2WLSL_SET(x) (((uint32_t)(x) << DDRPHY_DX_GTR_R2WLSL_SHIFT) & DDRPHY_DX_GTR_R2WLSL_MASK) +#define DDRPHY_DX_GTR_R2WLSL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GTR_R2WLSL_MASK) >> DDRPHY_DX_GTR_R2WLSL_SHIFT) + +/* + * R1WLSL (R/W) + * + */ +#define DDRPHY_DX_GTR_R1WLSL_MASK (0xC000U) +#define DDRPHY_DX_GTR_R1WLSL_SHIFT (14U) +#define DDRPHY_DX_GTR_R1WLSL_SET(x) (((uint32_t)(x) << DDRPHY_DX_GTR_R1WLSL_SHIFT) & DDRPHY_DX_GTR_R1WLSL_MASK) +#define DDRPHY_DX_GTR_R1WLSL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GTR_R1WLSL_MASK) >> DDRPHY_DX_GTR_R1WLSL_SHIFT) + +/* + * R0WLSL (R/W) + * + * Rank n Write Leveling System Latency: This is used to adjust the write latency after write leveling. Power-up default is 01 (i.e. no extra clock cycles required). The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register. Every two bits of this register control the latency of each of the (up to) four ranks. R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on. Valid values: + * 00 = Write latency = WL - 1 01 = Write latency = WL + * 10 = Write latency = WL + 1 11 = Reserved + */ +#define DDRPHY_DX_GTR_R0WLSL_MASK (0x3000U) +#define DDRPHY_DX_GTR_R0WLSL_SHIFT (12U) +#define DDRPHY_DX_GTR_R0WLSL_SET(x) (((uint32_t)(x) << DDRPHY_DX_GTR_R0WLSL_SHIFT) & DDRPHY_DX_GTR_R0WLSL_MASK) +#define DDRPHY_DX_GTR_R0WLSL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GTR_R0WLSL_MASK) >> DDRPHY_DX_GTR_R0WLSL_SHIFT) + +/* + * R3DGSL (R/W) + * + */ +#define DDRPHY_DX_GTR_R3DGSL_MASK (0xE00U) +#define DDRPHY_DX_GTR_R3DGSL_SHIFT (9U) +#define DDRPHY_DX_GTR_R3DGSL_SET(x) (((uint32_t)(x) << DDRPHY_DX_GTR_R3DGSL_SHIFT) & DDRPHY_DX_GTR_R3DGSL_MASK) +#define DDRPHY_DX_GTR_R3DGSL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GTR_R3DGSL_MASK) >> DDRPHY_DX_GTR_R3DGSL_SHIFT) + +/* + * R2DGSL (R/W) + * + */ +#define DDRPHY_DX_GTR_R2DGSL_MASK (0x1C0U) +#define DDRPHY_DX_GTR_R2DGSL_SHIFT (6U) +#define DDRPHY_DX_GTR_R2DGSL_SET(x) (((uint32_t)(x) << DDRPHY_DX_GTR_R2DGSL_SHIFT) & DDRPHY_DX_GTR_R2DGSL_MASK) +#define DDRPHY_DX_GTR_R2DGSL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GTR_R2DGSL_MASK) >> DDRPHY_DX_GTR_R2DGSL_SHIFT) + +/* + * R1DGSL (R/W) + * + */ +#define DDRPHY_DX_GTR_R1DGSL_MASK (0x38U) +#define DDRPHY_DX_GTR_R1DGSL_SHIFT (3U) +#define DDRPHY_DX_GTR_R1DGSL_SET(x) (((uint32_t)(x) << DDRPHY_DX_GTR_R1DGSL_SHIFT) & DDRPHY_DX_GTR_R1DGSL_MASK) +#define DDRPHY_DX_GTR_R1DGSL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GTR_R1DGSL_MASK) >> DDRPHY_DX_GTR_R1DGSL_SHIFT) + +/* + * R0DGSL (R/W) + * + * Rank n DQS Gating System Latency: This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles. + * This is used to compensate for board delays and other system delays. Power-up default is 000 (i.e. no extra clock cycles required). The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register. Every three bits of this register control the latency of each of the (up to) four ranks. R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on. Valid values are 0 to 7: + */ +#define DDRPHY_DX_GTR_R0DGSL_MASK (0x7U) +#define DDRPHY_DX_GTR_R0DGSL_SHIFT (0U) +#define DDRPHY_DX_GTR_R0DGSL_SET(x) (((uint32_t)(x) << DDRPHY_DX_GTR_R0DGSL_SHIFT) & DDRPHY_DX_GTR_R0DGSL_MASK) +#define DDRPHY_DX_GTR_R0DGSL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GTR_R0DGSL_MASK) >> DDRPHY_DX_GTR_R0DGSL_SHIFT) + +/* Bitfield definition for register of struct array DX: GSR2 */ +/* + * ESTAT (R/W) + * + * Error Status: If an error occurred for this lane as indicated by RDERR, WDERR, REERR or WEERR the error status code can provide additional information regard when the error occurred during the algorithm execution. + */ +#define DDRPHY_DX_GSR2_ESTAT_MASK (0xF00U) +#define DDRPHY_DX_GSR2_ESTAT_SHIFT (8U) +#define DDRPHY_DX_GSR2_ESTAT_SET(x) (((uint32_t)(x) << DDRPHY_DX_GSR2_ESTAT_SHIFT) & DDRPHY_DX_GSR2_ESTAT_MASK) +#define DDRPHY_DX_GSR2_ESTAT_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR2_ESTAT_MASK) >> DDRPHY_DX_GSR2_ESTAT_SHIFT) + +/* + * WEWN (R/W) + * + * Write Data Eye Training Warning: Indicates, if set, that the DATX8 has encountered a warning during execution of the write data eye training. + */ +#define DDRPHY_DX_GSR2_WEWN_MASK (0x80U) +#define DDRPHY_DX_GSR2_WEWN_SHIFT (7U) +#define DDRPHY_DX_GSR2_WEWN_SET(x) (((uint32_t)(x) << DDRPHY_DX_GSR2_WEWN_SHIFT) & DDRPHY_DX_GSR2_WEWN_MASK) +#define DDRPHY_DX_GSR2_WEWN_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR2_WEWN_MASK) >> DDRPHY_DX_GSR2_WEWN_SHIFT) + +/* + * WEERR (R/W) + * + * Write Data Eye Training Error: Indicates, if set, that the DATX8 has encountered an error during execution of the write data eye training. + */ +#define DDRPHY_DX_GSR2_WEERR_MASK (0x40U) +#define DDRPHY_DX_GSR2_WEERR_SHIFT (6U) +#define DDRPHY_DX_GSR2_WEERR_SET(x) (((uint32_t)(x) << DDRPHY_DX_GSR2_WEERR_SHIFT) & DDRPHY_DX_GSR2_WEERR_MASK) +#define DDRPHY_DX_GSR2_WEERR_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR2_WEERR_MASK) >> DDRPHY_DX_GSR2_WEERR_SHIFT) + +/* + * REWN (R/W) + * + * Read Data Eye Training Warning: Indicates, if set, that the DATX8 has encountered a warning during execution of the read data eye training. + */ +#define DDRPHY_DX_GSR2_REWN_MASK (0x20U) +#define DDRPHY_DX_GSR2_REWN_SHIFT (5U) +#define DDRPHY_DX_GSR2_REWN_SET(x) (((uint32_t)(x) << DDRPHY_DX_GSR2_REWN_SHIFT) & DDRPHY_DX_GSR2_REWN_MASK) +#define DDRPHY_DX_GSR2_REWN_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR2_REWN_MASK) >> DDRPHY_DX_GSR2_REWN_SHIFT) + +/* + * REERR (R/W) + * + * Read Data Eye Training Error: Indicates, if set, that the DATX8 has encountered an error during execution of the read data eye training. + */ +#define DDRPHY_DX_GSR2_REERR_MASK (0x10U) +#define DDRPHY_DX_GSR2_REERR_SHIFT (4U) +#define DDRPHY_DX_GSR2_REERR_SET(x) (((uint32_t)(x) << DDRPHY_DX_GSR2_REERR_SHIFT) & DDRPHY_DX_GSR2_REERR_MASK) +#define DDRPHY_DX_GSR2_REERR_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR2_REERR_MASK) >> DDRPHY_DX_GSR2_REERR_SHIFT) + +/* + * WDWN (R/W) + * + * Write Bit Deskew Warning: Indicates, if set, that the DATX8 has encountered a warning during execution of the write bit deskew training. + */ +#define DDRPHY_DX_GSR2_WDWN_MASK (0x8U) +#define DDRPHY_DX_GSR2_WDWN_SHIFT (3U) +#define DDRPHY_DX_GSR2_WDWN_SET(x) (((uint32_t)(x) << DDRPHY_DX_GSR2_WDWN_SHIFT) & DDRPHY_DX_GSR2_WDWN_MASK) +#define DDRPHY_DX_GSR2_WDWN_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR2_WDWN_MASK) >> DDRPHY_DX_GSR2_WDWN_SHIFT) + +/* + * WDERR (R/W) + * + * Write Bit Deskew Error: Indicates, if set, that the DATX8 has encountered an error during execution of the write bit deskew training. + */ +#define DDRPHY_DX_GSR2_WDERR_MASK (0x4U) +#define DDRPHY_DX_GSR2_WDERR_SHIFT (2U) +#define DDRPHY_DX_GSR2_WDERR_SET(x) (((uint32_t)(x) << DDRPHY_DX_GSR2_WDERR_SHIFT) & DDRPHY_DX_GSR2_WDERR_MASK) +#define DDRPHY_DX_GSR2_WDERR_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR2_WDERR_MASK) >> DDRPHY_DX_GSR2_WDERR_SHIFT) + +/* + * RDWN (R/W) + * + * Read Bit Deskew Warning: Indicates, if set, that the DATX8 has encountered a warning during execution of the read bit deskew training. + */ +#define DDRPHY_DX_GSR2_RDWN_MASK (0x2U) +#define DDRPHY_DX_GSR2_RDWN_SHIFT (1U) +#define DDRPHY_DX_GSR2_RDWN_SET(x) (((uint32_t)(x) << DDRPHY_DX_GSR2_RDWN_SHIFT) & DDRPHY_DX_GSR2_RDWN_MASK) +#define DDRPHY_DX_GSR2_RDWN_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR2_RDWN_MASK) >> DDRPHY_DX_GSR2_RDWN_SHIFT) + +/* + * RDERR (R/W) + * + * Read Bit Deskew Error: Indicates, if set, that the DATX8 has encountered an error during execution of the read bit deskew training. + */ +#define DDRPHY_DX_GSR2_RDERR_MASK (0x1U) +#define DDRPHY_DX_GSR2_RDERR_SHIFT (0U) +#define DDRPHY_DX_GSR2_RDERR_SET(x) (((uint32_t)(x) << DDRPHY_DX_GSR2_RDERR_SHIFT) & DDRPHY_DX_GSR2_RDERR_MASK) +#define DDRPHY_DX_GSR2_RDERR_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR2_RDERR_MASK) >> DDRPHY_DX_GSR2_RDERR_SHIFT) + + + +/* ZQ register group index macro definition */ +#define DDRPHY_ZQ_0 (0UL) +#define DDRPHY_ZQ_1 (1UL) +#define DDRPHY_ZQ_2 (2UL) +#define DDRPHY_ZQ_3 (3UL) + +/* DX register group index macro definition */ +#define DDRPHY_DX_0 (0UL) +#define DDRPHY_DX_1 (1UL) +#define DDRPHY_DX_2 (2UL) +#define DDRPHY_DX_3 (3UL) +#define DDRPHY_DX_4 (4UL) +#define DDRPHY_DX_5 (5UL) +#define DDRPHY_DX_6 (6UL) +#define DDRPHY_DX_7 (7UL) +#define DDRPHY_DX_8 (8UL) + + +#endif /* HPM_DDRPHY_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dmav2_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dmav2_regs.h new file mode 100644 index 00000000000..9fbe188a2e0 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dmav2_regs.h @@ -0,0 +1,596 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_DMAV2_H +#define HPM_DMAV2_H + +typedef struct { + __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */ + __R uint32_t IDMISC; /* 0x4: ID Misc */ + __R uint8_t RESERVED1[8]; /* 0x8 - 0xF: Reserved */ + __R uint32_t DMACFG; /* 0x10: DMAC Configuration Register */ + __W uint32_t DMACTRL; /* 0x14: DMAC Control Register */ + __W uint32_t CHABORT; /* 0x18: Channel Abort Register */ + __R uint8_t RESERVED2[8]; /* 0x1C - 0x23: Reserved */ + __RW uint32_t INTHALFSTS; /* 0x24: Harlf Complete Interrupt Status */ + __W uint32_t INTTCSTS; /* 0x28: Trans Complete Interrupt Status Register */ + __W uint32_t INTABORTSTS; /* 0x2C: Abort Interrupt Status Register */ + __W uint32_t INTERRSTS; /* 0x30: Error Interrupt Status Register */ + __R uint32_t CHEN; /* 0x34: Channel Enable Register */ + __R uint8_t RESERVED3[8]; /* 0x38 - 0x3F: Reserved */ + struct { + __RW uint32_t CTRL; /* 0x40: Channel Control Register */ + __RW uint32_t TRANSIZE; /* 0x44: Channel Transfer Size Register */ + __RW uint32_t SRCADDR; /* 0x48: Channel Source Address Low Part Register */ + __RW uint32_t CHANREQCTRL; /* 0x4C: Channel DMA Request Control Register */ + __RW uint32_t DSTADDR; /* 0x50: Channel Destination Address Low Part Register */ + __R uint8_t RESERVED0[4]; /* 0x54 - 0x57: Reserved */ + __RW uint32_t LLPOINTER; /* 0x58: Channel Linked List Pointer Low Part Register */ + __R uint8_t RESERVED1[4]; /* 0x5C - 0x5F: Reserved */ + } CHCTRL[32]; +} DMAV2_Type; + + +/* Bitfield definition for register: IDMISC */ +/* + * DMASTATE (RO) + * + * DMA state machine + * localparam ST_IDLE = 3'b000; + * localparam ST_READ = 3'b001; + * localparam ST_READ_ACK = 3'b010; + * localparam ST_WRITE = 3'b011; + * localparam ST_WRITE_ACK = 3'b100; + * localparam ST_LL = 3'b101; + * localparam ST_END = 3'b110; + * localparam ST_END_WAIT = 3'b111; + */ +#define DMAV2_IDMISC_DMASTATE_MASK (0xE000U) +#define DMAV2_IDMISC_DMASTATE_SHIFT (13U) +#define DMAV2_IDMISC_DMASTATE_GET(x) (((uint32_t)(x) & DMAV2_IDMISC_DMASTATE_MASK) >> DMAV2_IDMISC_DMASTATE_SHIFT) + +/* + * CURCHAN (RO) + * + * current channel in used + */ +#define DMAV2_IDMISC_CURCHAN_MASK (0x1F00U) +#define DMAV2_IDMISC_CURCHAN_SHIFT (8U) +#define DMAV2_IDMISC_CURCHAN_GET(x) (((uint32_t)(x) & DMAV2_IDMISC_CURCHAN_MASK) >> DMAV2_IDMISC_CURCHAN_SHIFT) + +/* Bitfield definition for register: DMACFG */ +/* + * CHAINXFR (RO) + * + * Chain transfer + * 0x0: Chain transfer is not configured + * 0x1: Chain transfer is configured + */ +#define DMAV2_DMACFG_CHAINXFR_MASK (0x80000000UL) +#define DMAV2_DMACFG_CHAINXFR_SHIFT (31U) +#define DMAV2_DMACFG_CHAINXFR_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_CHAINXFR_MASK) >> DMAV2_DMACFG_CHAINXFR_SHIFT) + +/* + * REQSYNC (RO) + * + * DMA request synchronization. The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, + * which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. + * 0x0: Request synchronization is not configured + * 0x1: Request synchronization is configured + */ +#define DMAV2_DMACFG_REQSYNC_MASK (0x40000000UL) +#define DMAV2_DMACFG_REQSYNC_SHIFT (30U) +#define DMAV2_DMACFG_REQSYNC_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_REQSYNC_MASK) >> DMAV2_DMACFG_REQSYNC_SHIFT) + +/* + * DATAWIDTH (RO) + * + * AXI bus data width + * 0x0: 32 bits + * 0x1: 64 bits + * 0x2: 128 bits + * 0x3: 256 bits + */ +#define DMAV2_DMACFG_DATAWIDTH_MASK (0x3000000UL) +#define DMAV2_DMACFG_DATAWIDTH_SHIFT (24U) +#define DMAV2_DMACFG_DATAWIDTH_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_DATAWIDTH_MASK) >> DMAV2_DMACFG_DATAWIDTH_SHIFT) + +/* + * ADDRWIDTH (RO) + * + * AXI bus address width + * 0x18: 24 bits + * 0x19: 25 bits + * ... + * 0x40: 64 bits + * Others: Invalid + */ +#define DMAV2_DMACFG_ADDRWIDTH_MASK (0xFE0000UL) +#define DMAV2_DMACFG_ADDRWIDTH_SHIFT (17U) +#define DMAV2_DMACFG_ADDRWIDTH_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_ADDRWIDTH_MASK) >> DMAV2_DMACFG_ADDRWIDTH_SHIFT) + +/* + * CORENUM (RO) + * + * DMA core number + * 0x0: 1 core + * 0x1: 2 cores + */ +#define DMAV2_DMACFG_CORENUM_MASK (0x10000UL) +#define DMAV2_DMACFG_CORENUM_SHIFT (16U) +#define DMAV2_DMACFG_CORENUM_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_CORENUM_MASK) >> DMAV2_DMACFG_CORENUM_SHIFT) + +/* + * BUSNUM (RO) + * + * AXI bus interface number + * 0x0: 1 AXI bus + * 0x1: 2 AXI busses + */ +#define DMAV2_DMACFG_BUSNUM_MASK (0x8000U) +#define DMAV2_DMACFG_BUSNUM_SHIFT (15U) +#define DMAV2_DMACFG_BUSNUM_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_BUSNUM_MASK) >> DMAV2_DMACFG_BUSNUM_SHIFT) + +/* + * REQNUM (RO) + * + * Request/acknowledge pair number + * 0x0: 0 pair + * 0x1: 1 pair + * 0x2: 2 pairs + * ... + * 0x10: 16 pairs + */ +#define DMAV2_DMACFG_REQNUM_MASK (0x7C00U) +#define DMAV2_DMACFG_REQNUM_SHIFT (10U) +#define DMAV2_DMACFG_REQNUM_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_REQNUM_MASK) >> DMAV2_DMACFG_REQNUM_SHIFT) + +/* + * FIFODEPTH (RO) + * + * FIFO depth + * 0x4: 4 entries + * 0x8: 8 entries + * 0x10: 16 entries + * 0x20: 32 entries + * Others: Invalid + */ +#define DMAV2_DMACFG_FIFODEPTH_MASK (0x3F0U) +#define DMAV2_DMACFG_FIFODEPTH_SHIFT (4U) +#define DMAV2_DMACFG_FIFODEPTH_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_FIFODEPTH_MASK) >> DMAV2_DMACFG_FIFODEPTH_SHIFT) + +/* + * CHANNELNUM (RO) + * + * Channel number + * 0x1: 1 channel + * 0x2: 2 channels + * ... + * 0x8: 8 channels + * Others: Invalid + */ +#define DMAV2_DMACFG_CHANNELNUM_MASK (0xFU) +#define DMAV2_DMACFG_CHANNELNUM_SHIFT (0U) +#define DMAV2_DMACFG_CHANNELNUM_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_CHANNELNUM_MASK) >> DMAV2_DMACFG_CHANNELNUM_SHIFT) + +/* Bitfield definition for register: DMACTRL */ +/* + * RESET (WO) + * + * Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. + * Note: The software reset may cause the in-completion of AXI transaction. + */ +#define DMAV2_DMACTRL_RESET_MASK (0x1U) +#define DMAV2_DMACTRL_RESET_SHIFT (0U) +#define DMAV2_DMACTRL_RESET_SET(x) (((uint32_t)(x) << DMAV2_DMACTRL_RESET_SHIFT) & DMAV2_DMACTRL_RESET_MASK) +#define DMAV2_DMACTRL_RESET_GET(x) (((uint32_t)(x) & DMAV2_DMACTRL_RESET_MASK) >> DMAV2_DMACTRL_RESET_SHIFT) + +/* Bitfield definition for register: CHABORT */ +/* + * CHABORT (WO) + * + * Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. + * Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) + */ +#define DMAV2_CHABORT_CHABORT_MASK (0xFFFFFFFFUL) +#define DMAV2_CHABORT_CHABORT_SHIFT (0U) +#define DMAV2_CHABORT_CHABORT_SET(x) (((uint32_t)(x) << DMAV2_CHABORT_CHABORT_SHIFT) & DMAV2_CHABORT_CHABORT_MASK) +#define DMAV2_CHABORT_CHABORT_GET(x) (((uint32_t)(x) & DMAV2_CHABORT_CHABORT_MASK) >> DMAV2_CHABORT_CHABORT_SHIFT) + +/* Bitfield definition for register: INTHALFSTS */ +/* + * STS (RW) + * + * half transfer done irq status + */ +#define DMAV2_INTHALFSTS_STS_MASK (0xFFFFFFFFUL) +#define DMAV2_INTHALFSTS_STS_SHIFT (0U) +#define DMAV2_INTHALFSTS_STS_SET(x) (((uint32_t)(x) << DMAV2_INTHALFSTS_STS_SHIFT) & DMAV2_INTHALFSTS_STS_MASK) +#define DMAV2_INTHALFSTS_STS_GET(x) (((uint32_t)(x) & DMAV2_INTHALFSTS_STS_MASK) >> DMAV2_INTHALFSTS_STS_SHIFT) + +/* Bitfield definition for register: INTTCSTS */ +/* + * STS (W1C) + * + * The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. + * 0x0: Channel n has no terminal count status + * 0x1: Channel n has terminal count status + */ +#define DMAV2_INTTCSTS_STS_MASK (0xFFFFFFFFUL) +#define DMAV2_INTTCSTS_STS_SHIFT (0U) +#define DMAV2_INTTCSTS_STS_SET(x) (((uint32_t)(x) << DMAV2_INTTCSTS_STS_SHIFT) & DMAV2_INTTCSTS_STS_MASK) +#define DMAV2_INTTCSTS_STS_GET(x) (((uint32_t)(x) & DMAV2_INTTCSTS_STS_MASK) >> DMAV2_INTTCSTS_STS_SHIFT) + +/* Bitfield definition for register: INTABORTSTS */ +/* + * STS (W1C) + * + * The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. + * 0x0: Channel n has no abort status + * 0x1: Channel n has abort status + */ +#define DMAV2_INTABORTSTS_STS_MASK (0xFFFFFFFFUL) +#define DMAV2_INTABORTSTS_STS_SHIFT (0U) +#define DMAV2_INTABORTSTS_STS_SET(x) (((uint32_t)(x) << DMAV2_INTABORTSTS_STS_SHIFT) & DMAV2_INTABORTSTS_STS_MASK) +#define DMAV2_INTABORTSTS_STS_GET(x) (((uint32_t)(x) & DMAV2_INTABORTSTS_STS_MASK) >> DMAV2_INTABORTSTS_STS_SHIFT) + +/* Bitfield definition for register: INTERRSTS */ +/* + * STS (W1C) + * + * The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: + * - Bus error + * - Unaligned address + * - Unaligned transfer width + * - Reserved configuration + * 0x0: Channel n has no error status + * 0x1: Channel n has error status + */ +#define DMAV2_INTERRSTS_STS_MASK (0xFFFFFFFFUL) +#define DMAV2_INTERRSTS_STS_SHIFT (0U) +#define DMAV2_INTERRSTS_STS_SET(x) (((uint32_t)(x) << DMAV2_INTERRSTS_STS_SHIFT) & DMAV2_INTERRSTS_STS_MASK) +#define DMAV2_INTERRSTS_STS_GET(x) (((uint32_t)(x) & DMAV2_INTERRSTS_STS_MASK) >> DMAV2_INTERRSTS_STS_SHIFT) + +/* Bitfield definition for register: CHEN */ +/* + * CHEN (RO) + * + * Alias of the Enable field of all ChnCtrl registers + */ +#define DMAV2_CHEN_CHEN_MASK (0xFFFFFFFFUL) +#define DMAV2_CHEN_CHEN_SHIFT (0U) +#define DMAV2_CHEN_CHEN_GET(x) (((uint32_t)(x) & DMAV2_CHEN_CHEN_MASK) >> DMAV2_CHEN_CHEN_SHIFT) + +/* Bitfield definition for register of struct array CHCTRL: CTRL */ +/* + * INFINITELOOP (RW) + * + * set to loop current config infinitely + */ +#define DMAV2_CHCTRL_CTRL_INFINITELOOP_MASK (0x80000000UL) +#define DMAV2_CHCTRL_CTRL_INFINITELOOP_SHIFT (31U) +#define DMAV2_CHCTRL_CTRL_INFINITELOOP_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INFINITELOOP_SHIFT) & DMAV2_CHCTRL_CTRL_INFINITELOOP_MASK) +#define DMAV2_CHCTRL_CTRL_INFINITELOOP_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INFINITELOOP_MASK) >> DMAV2_CHCTRL_CTRL_INFINITELOOP_SHIFT) + +/* + * HANDSHAKEOPT (RW) + * + * 0: one request to transfer one burst + * 1: one request to transfer all the data defined in ch_tts + */ +#define DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_MASK (0x40000000UL) +#define DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SHIFT (30U) +#define DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SHIFT) & DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_MASK) +#define DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_MASK) >> DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SHIFT) + +/* + * PRIORITY (RW) + * + * Channel priority level + * 0x0: Lower priority + * 0x1: Higher priority + */ +#define DMAV2_CHCTRL_CTRL_PRIORITY_MASK (0x20000000UL) +#define DMAV2_CHCTRL_CTRL_PRIORITY_SHIFT (29U) +#define DMAV2_CHCTRL_CTRL_PRIORITY_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_PRIORITY_SHIFT) & DMAV2_CHCTRL_CTRL_PRIORITY_MASK) +#define DMAV2_CHCTRL_CTRL_PRIORITY_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_PRIORITY_MASK) >> DMAV2_CHCTRL_CTRL_PRIORITY_SHIFT) + +/* + * BURSTOPT (RW) + * + * set to change burst_size definition + */ +#define DMAV2_CHCTRL_CTRL_BURSTOPT_MASK (0x10000000UL) +#define DMAV2_CHCTRL_CTRL_BURSTOPT_SHIFT (28U) +#define DMAV2_CHCTRL_CTRL_BURSTOPT_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_BURSTOPT_SHIFT) & DMAV2_CHCTRL_CTRL_BURSTOPT_MASK) +#define DMAV2_CHCTRL_CTRL_BURSTOPT_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_BURSTOPT_MASK) >> DMAV2_CHCTRL_CTRL_BURSTOPT_SHIFT) + +/* + * SRCBURSTSIZE (RW) + * + * Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. + * The burst transfer byte number is (SrcBurstSize * SrcWidth). + * 0x0: 1 transfer + * 0x1: 2 transfers + * 0x2: 4 transfers + * 0x3: 8 transfers + * 0x4: 16 transfers + * 0x5: 32 transfers + * 0x6: 64 transfers + * 0x7: 128 transfers + * 0x8: 256 transfers + * 0x9:512 transfers + * 0xa: 1024 transfers + * 0xb - 0xf: Reserved, setting this field with a reserved value triggers the error exception + */ +#define DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_MASK (0xF000000UL) +#define DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT (24U) +#define DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT) & DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_MASK) +#define DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_MASK) >> DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT) + +/* + * SRCWIDTH (RW) + * + * Source transfer width + * 0x0: Byte transfer + * 0x1: Half-word transfer + * 0x2: Word transfer + * 0x3: Double word transfer + * 0x4: Quad word transfer + * 0x5: Eight word transfer + * 0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception + */ +#define DMAV2_CHCTRL_CTRL_SRCWIDTH_MASK (0xE00000UL) +#define DMAV2_CHCTRL_CTRL_SRCWIDTH_SHIFT (21U) +#define DMAV2_CHCTRL_CTRL_SRCWIDTH_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_SRCWIDTH_SHIFT) & DMAV2_CHCTRL_CTRL_SRCWIDTH_MASK) +#define DMAV2_CHCTRL_CTRL_SRCWIDTH_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_SRCWIDTH_MASK) >> DMAV2_CHCTRL_CTRL_SRCWIDTH_SHIFT) + +/* + * DSTWIDTH (RW) + * + * Destination transfer width. + * Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. + * For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. + * See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. + * 0x0: Byte transfer + * 0x1: Half-word transfer + * 0x2: Word transfer + * 0x3: Double word transfer + * 0x4: Quad word transfer + * 0x5: Eight word transfer + * 0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception + */ +#define DMAV2_CHCTRL_CTRL_DSTWIDTH_MASK (0x1C0000UL) +#define DMAV2_CHCTRL_CTRL_DSTWIDTH_SHIFT (18U) +#define DMAV2_CHCTRL_CTRL_DSTWIDTH_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_DSTWIDTH_SHIFT) & DMAV2_CHCTRL_CTRL_DSTWIDTH_MASK) +#define DMAV2_CHCTRL_CTRL_DSTWIDTH_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_DSTWIDTH_MASK) >> DMAV2_CHCTRL_CTRL_DSTWIDTH_SHIFT) + +/* + * SRCMODE (RW) + * + * Source DMA handshake mode + * 0x0: Normal mode + * 0x1: Handshake mode + * Normal mode is enabled and started by software set Enable bit; + * Handshake mode is enabled by software set Enable bit, started by hardware dma request from DMAMUX block + */ +#define DMAV2_CHCTRL_CTRL_SRCMODE_MASK (0x20000UL) +#define DMAV2_CHCTRL_CTRL_SRCMODE_SHIFT (17U) +#define DMAV2_CHCTRL_CTRL_SRCMODE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_SRCMODE_SHIFT) & DMAV2_CHCTRL_CTRL_SRCMODE_MASK) +#define DMAV2_CHCTRL_CTRL_SRCMODE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_SRCMODE_MASK) >> DMAV2_CHCTRL_CTRL_SRCMODE_SHIFT) + +/* + * DSTMODE (RW) + * + * Destination DMA handshake mode + * 0x0: Normal mode + * 0x1: Handshake mode + * the difference bewteen Source/Destination handshake mode is: + * the dma block will response hardware request after read in Source handshake mode; + * the dma block will response hardware request after write in Destination handshake mode; + * NOTE: can't set SrcMode and DstMode at same time, otherwise result unknown. + */ +#define DMAV2_CHCTRL_CTRL_DSTMODE_MASK (0x10000UL) +#define DMAV2_CHCTRL_CTRL_DSTMODE_SHIFT (16U) +#define DMAV2_CHCTRL_CTRL_DSTMODE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_DSTMODE_SHIFT) & DMAV2_CHCTRL_CTRL_DSTMODE_MASK) +#define DMAV2_CHCTRL_CTRL_DSTMODE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_DSTMODE_MASK) >> DMAV2_CHCTRL_CTRL_DSTMODE_SHIFT) + +/* + * SRCADDRCTRL (RW) + * + * Source address control + * 0x0: Increment address + * 0x1: Decrement address + * 0x2: Fixed address + * 0x3: Reserved, setting the field with this value triggers the error exception + */ +#define DMAV2_CHCTRL_CTRL_SRCADDRCTRL_MASK (0xC000U) +#define DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SHIFT (14U) +#define DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SHIFT) & DMAV2_CHCTRL_CTRL_SRCADDRCTRL_MASK) +#define DMAV2_CHCTRL_CTRL_SRCADDRCTRL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_SRCADDRCTRL_MASK) >> DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SHIFT) + +/* + * DSTADDRCTRL (RW) + * + * Destination address control + * 0x0: Increment address + * 0x1: Decrement address + * 0x2: Fixed address + * 0x3: Reserved, setting the field with this value triggers the error exception + */ +#define DMAV2_CHCTRL_CTRL_DSTADDRCTRL_MASK (0x3000U) +#define DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SHIFT (12U) +#define DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SHIFT) & DMAV2_CHCTRL_CTRL_DSTADDRCTRL_MASK) +#define DMAV2_CHCTRL_CTRL_DSTADDRCTRL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_DSTADDRCTRL_MASK) >> DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SHIFT) + +/* + * INTHALFCNTMASK (RW) + * + * Channel half interrupt mask + * 0x0: Allow the half interrupt to be triggered + * 0x1: Disable the half interrupt + */ +#define DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_MASK (0x10U) +#define DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_SHIFT (4U) +#define DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_SHIFT) & DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_MASK) +#define DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_MASK) >> DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_SHIFT) + +/* + * INTABTMASK (RW) + * + * Channel abort interrupt mask + * 0x0: Allow the abort interrupt to be triggered + * 0x1: Disable the abort interrupt + */ +#define DMAV2_CHCTRL_CTRL_INTABTMASK_MASK (0x8U) +#define DMAV2_CHCTRL_CTRL_INTABTMASK_SHIFT (3U) +#define DMAV2_CHCTRL_CTRL_INTABTMASK_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INTABTMASK_SHIFT) & DMAV2_CHCTRL_CTRL_INTABTMASK_MASK) +#define DMAV2_CHCTRL_CTRL_INTABTMASK_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INTABTMASK_MASK) >> DMAV2_CHCTRL_CTRL_INTABTMASK_SHIFT) + +/* + * INTERRMASK (RW) + * + * Channel error interrupt mask + * 0x0: Allow the error interrupt to be triggered + * 0x1: Disable the error interrupt + */ +#define DMAV2_CHCTRL_CTRL_INTERRMASK_MASK (0x4U) +#define DMAV2_CHCTRL_CTRL_INTERRMASK_SHIFT (2U) +#define DMAV2_CHCTRL_CTRL_INTERRMASK_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INTERRMASK_SHIFT) & DMAV2_CHCTRL_CTRL_INTERRMASK_MASK) +#define DMAV2_CHCTRL_CTRL_INTERRMASK_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INTERRMASK_MASK) >> DMAV2_CHCTRL_CTRL_INTERRMASK_SHIFT) + +/* + * INTTCMASK (RW) + * + * Channel terminal count interrupt mask + * 0x0: Allow the terminal count interrupt to be triggered + * 0x1: Disable the terminal count interrupt + */ +#define DMAV2_CHCTRL_CTRL_INTTCMASK_MASK (0x2U) +#define DMAV2_CHCTRL_CTRL_INTTCMASK_SHIFT (1U) +#define DMAV2_CHCTRL_CTRL_INTTCMASK_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INTTCMASK_SHIFT) & DMAV2_CHCTRL_CTRL_INTTCMASK_MASK) +#define DMAV2_CHCTRL_CTRL_INTTCMASK_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INTTCMASK_MASK) >> DMAV2_CHCTRL_CTRL_INTTCMASK_SHIFT) + +/* + * ENABLE (RW) + * + * Channel enable bit + * 0x0: Disable + * 0x1: Enable + */ +#define DMAV2_CHCTRL_CTRL_ENABLE_MASK (0x1U) +#define DMAV2_CHCTRL_CTRL_ENABLE_SHIFT (0U) +#define DMAV2_CHCTRL_CTRL_ENABLE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_ENABLE_SHIFT) & DMAV2_CHCTRL_CTRL_ENABLE_MASK) +#define DMAV2_CHCTRL_CTRL_ENABLE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_ENABLE_MASK) >> DMAV2_CHCTRL_CTRL_ENABLE_SHIFT) + +/* Bitfield definition for register of struct array CHCTRL: TRANSIZE */ +/* + * TRANSIZE (RW) + * + * Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. + * If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + */ +#define DMAV2_CHCTRL_TRANSIZE_TRANSIZE_MASK (0xFFFFFFFUL) +#define DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SHIFT (0U) +#define DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SHIFT) & DMAV2_CHCTRL_TRANSIZE_TRANSIZE_MASK) +#define DMAV2_CHCTRL_TRANSIZE_TRANSIZE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_TRANSIZE_TRANSIZE_MASK) >> DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SHIFT) + +/* Bitfield definition for register of struct array CHCTRL: SRCADDR */ +/* + * SRCADDRL (RW) + * + * Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. + * This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + */ +#define DMAV2_CHCTRL_SRCADDR_SRCADDRL_MASK (0xFFFFFFFFUL) +#define DMAV2_CHCTRL_SRCADDR_SRCADDRL_SHIFT (0U) +#define DMAV2_CHCTRL_SRCADDR_SRCADDRL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_SRCADDR_SRCADDRL_SHIFT) & DMAV2_CHCTRL_SRCADDR_SRCADDRL_MASK) +#define DMAV2_CHCTRL_SRCADDR_SRCADDRL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_SRCADDR_SRCADDRL_MASK) >> DMAV2_CHCTRL_SRCADDR_SRCADDRL_SHIFT) + +/* Bitfield definition for register of struct array CHCTRL: CHANREQCTRL */ +/* + * SRCREQSEL (RW) + * + * Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + */ +#define DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_MASK (0x1F000000UL) +#define DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SHIFT (24U) +#define DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SHIFT) & DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_MASK) +#define DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_MASK) >> DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SHIFT) + +/* + * DSTREQSEL (RW) + * + * Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + */ +#define DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_MASK (0x1F0000UL) +#define DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SHIFT (16U) +#define DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SHIFT) & DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_MASK) +#define DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_MASK) >> DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SHIFT) + +/* Bitfield definition for register of struct array CHCTRL: DSTADDR */ +/* + * DSTADDRL (RW) + * + * Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. + * This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + */ +#define DMAV2_CHCTRL_DSTADDR_DSTADDRL_MASK (0xFFFFFFFFUL) +#define DMAV2_CHCTRL_DSTADDR_DSTADDRL_SHIFT (0U) +#define DMAV2_CHCTRL_DSTADDR_DSTADDRL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_DSTADDR_DSTADDRL_SHIFT) & DMAV2_CHCTRL_DSTADDR_DSTADDRL_MASK) +#define DMAV2_CHCTRL_DSTADDR_DSTADDRL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_DSTADDR_DSTADDRL_MASK) >> DMAV2_CHCTRL_DSTADDR_DSTADDRL_SHIFT) + +/* Bitfield definition for register of struct array CHCTRL: LLPOINTER */ +/* + * LLPOINTERL (RW) + * + * Low part of the pointer to the next descriptor. The pointer must be double word aligned. + */ +#define DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_MASK (0xFFFFFFF8UL) +#define DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT (3U) +#define DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT) & DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_MASK) +#define DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_MASK) >> DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT) + + + +/* CHCTRL register group index macro definition */ +#define DMAV2_CHCTRL_CH0 (0UL) +#define DMAV2_CHCTRL_CH1 (1UL) +#define DMAV2_CHCTRL_CH2 (2UL) +#define DMAV2_CHCTRL_CH3 (3UL) +#define DMAV2_CHCTRL_CH4 (4UL) +#define DMAV2_CHCTRL_CH5 (5UL) +#define DMAV2_CHCTRL_CH6 (6UL) +#define DMAV2_CHCTRL_CH7 (7UL) +#define DMAV2_CHCTRL_CH8 (8UL) +#define DMAV2_CHCTRL_CH9 (9UL) +#define DMAV2_CHCTRL_CH10 (10UL) +#define DMAV2_CHCTRL_CH11 (11UL) +#define DMAV2_CHCTRL_CH12 (12UL) +#define DMAV2_CHCTRL_CH13 (13UL) +#define DMAV2_CHCTRL_CH14 (14UL) +#define DMAV2_CHCTRL_CH15 (15UL) +#define DMAV2_CHCTRL_CH16 (16UL) +#define DMAV2_CHCTRL_CH17 (17UL) +#define DMAV2_CHCTRL_CH18 (18UL) +#define DMAV2_CHCTRL_CH19 (19UL) +#define DMAV2_CHCTRL_CH20 (20UL) +#define DMAV2_CHCTRL_CH21 (21UL) +#define DMAV2_CHCTRL_CH22 (22UL) +#define DMAV2_CHCTRL_CH23 (23UL) +#define DMAV2_CHCTRL_CH24 (24UL) +#define DMAV2_CHCTRL_CH25 (25UL) +#define DMAV2_CHCTRL_CH26 (26UL) +#define DMAV2_CHCTRL_CH27 (27UL) +#define DMAV2_CHCTRL_CH28 (28UL) +#define DMAV2_CHCTRL_CH29 (29UL) +#define DMAV2_CHCTRL_CH30 (30UL) +#define DMAV2_CHCTRL_CH31 (31UL) + + +#endif /* HPM_DMAV2_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_enet_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_enet_regs.h index 9deab135437..b9dec1a76e2 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_enet_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_enet_regs.h @@ -21,7 +21,7 @@ typedef struct { __R uint8_t RESERVED0[8]; /* 0x20 - 0x27: Reserved */ __RW uint32_t RWKFRMFILT; /* 0x28: Remote Wake-Up Frame Filter Register */ __RW uint32_t PMT_CSR; /* 0x2C: PMT Control and Status Register */ - __RW uint32_t LPI_CSR; /* 0x30: LPI Control and Status Regsiter */ + __RW uint32_t LPI_CSR; /* 0x30: LPI Control and Status Register */ __RW uint32_t LPI_TCR; /* 0x34: LPI Timers Control Register */ __R uint32_t INTR_STATUS; /* 0x38: Interrupt Status Register */ __RW uint32_t INTR_MASK; /* 0x3C: Interrupt Mask Register */ @@ -325,7 +325,7 @@ ICMP payload */ * DM (RW) * * Duplex Mode - * When this bit is set, the MAC operates in the full-duplex mode where it can transmit and receive simultaneously. This bit is RO with default value of 1'b1 in the full-duplex-only configuration. + * When this bit is set, the MAC operates in the full-duplex mode where it can transmit and receive simultaneously. */ #define ENET_MACCFG_DM_MASK (0x800U) #define ENET_MACCFG_DM_SHIFT (11U) diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ewdg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ewdg_regs.h new file mode 100644 index 00000000000..c62dfb0a4db --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ewdg_regs.h @@ -0,0 +1,465 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_EWDG_H +#define HPM_EWDG_H + +typedef struct { + __RW uint32_t CTRL0; /* 0x0: wdog ctrl register 0 +Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits */ + __RW uint32_t CTRL1; /* 0x4: wdog ctrl register 1 +Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits */ + __RW uint32_t OT_INT_VAL; /* 0x8: wdog timeout interrupt counter value */ + __RW uint32_t OT_RST_VAL; /* 0xC: wdog timeout reset counter value */ + __W uint32_t WDT_REFRESH_REG; /* 0x10: wdog refresh register */ + __RW uint32_t WDT_STATUS; /* 0x14: wdog status register */ + __RW uint32_t CFG_PROT; /* 0x18: ctrl register protection register */ + __RW uint32_t REF_PROT; /* 0x1C: refresh protection register */ + __RW uint32_t WDT_EN; /* 0x20: Wdog enable */ + __RW uint32_t REF_TIME; /* 0x24: Refresh period value */ +} EWDG_Type; + + +/* Bitfield definition for register: CTRL0 */ +/* + * CLK_SEL (RW) + * + * clock select + * 0：bus clock + * 1：ext clock + */ +#define EWDG_CTRL0_CLK_SEL_MASK (0x20000000UL) +#define EWDG_CTRL0_CLK_SEL_SHIFT (29U) +#define EWDG_CTRL0_CLK_SEL_SET(x) (((uint32_t)(x) << EWDG_CTRL0_CLK_SEL_SHIFT) & EWDG_CTRL0_CLK_SEL_MASK) +#define EWDG_CTRL0_CLK_SEL_GET(x) (((uint32_t)(x) & EWDG_CTRL0_CLK_SEL_MASK) >> EWDG_CTRL0_CLK_SEL_SHIFT) + +/* + * DIV_VALUE (RW) + * + * clock divider, the clock divider works as 2 ^ div_value for wdt counter + */ +#define EWDG_CTRL0_DIV_VALUE_MASK (0xE000000UL) +#define EWDG_CTRL0_DIV_VALUE_SHIFT (25U) +#define EWDG_CTRL0_DIV_VALUE_SET(x) (((uint32_t)(x) << EWDG_CTRL0_DIV_VALUE_SHIFT) & EWDG_CTRL0_DIV_VALUE_MASK) +#define EWDG_CTRL0_DIV_VALUE_GET(x) (((uint32_t)(x) & EWDG_CTRL0_DIV_VALUE_MASK) >> EWDG_CTRL0_DIV_VALUE_SHIFT) + +/* + * WIN_EN (RW) + * + * window mode enable + */ +#define EWDG_CTRL0_WIN_EN_MASK (0x1000000UL) +#define EWDG_CTRL0_WIN_EN_SHIFT (24U) +#define EWDG_CTRL0_WIN_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL0_WIN_EN_SHIFT) & EWDG_CTRL0_WIN_EN_MASK) +#define EWDG_CTRL0_WIN_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL0_WIN_EN_MASK) >> EWDG_CTRL0_WIN_EN_SHIFT) + +/* + * WIN_LOWER (RW) + * + * Once window mode is opened, the lower counter value to refresh wdt + * 00: 4/8 overtime value + * 01: 5/8 of overtime value + * 10: 6/8 of overtime value + * 11: 7/8 of overtime value + */ +#define EWDG_CTRL0_WIN_LOWER_MASK (0xC00000UL) +#define EWDG_CTRL0_WIN_LOWER_SHIFT (22U) +#define EWDG_CTRL0_WIN_LOWER_SET(x) (((uint32_t)(x) << EWDG_CTRL0_WIN_LOWER_SHIFT) & EWDG_CTRL0_WIN_LOWER_MASK) +#define EWDG_CTRL0_WIN_LOWER_GET(x) (((uint32_t)(x) & EWDG_CTRL0_WIN_LOWER_MASK) >> EWDG_CTRL0_WIN_LOWER_SHIFT) + +/* + * CFG_LOCK (RW) + * + * The register is locked and unlock is needed before re-config registers + * Once the lock mechanism takes effect, the CTRL0, CTRL1, timeout int register, timeout rst register, needs unlock before re-config them. + * The register update needs to be finished in the required period defined by UPD_OT_TIME register + */ +#define EWDG_CTRL0_CFG_LOCK_MASK (0x200000UL) +#define EWDG_CTRL0_CFG_LOCK_SHIFT (21U) +#define EWDG_CTRL0_CFG_LOCK_SET(x) (((uint32_t)(x) << EWDG_CTRL0_CFG_LOCK_SHIFT) & EWDG_CTRL0_CFG_LOCK_MASK) +#define EWDG_CTRL0_CFG_LOCK_GET(x) (((uint32_t)(x) & EWDG_CTRL0_CFG_LOCK_MASK) >> EWDG_CTRL0_CFG_LOCK_SHIFT) + +/* + * OT_SELF_CLEAR (RW) + * + * overtime reset can be self released after 32 function cycles + */ +#define EWDG_CTRL0_OT_SELF_CLEAR_MASK (0x20000UL) +#define EWDG_CTRL0_OT_SELF_CLEAR_SHIFT (17U) +#define EWDG_CTRL0_OT_SELF_CLEAR_SET(x) (((uint32_t)(x) << EWDG_CTRL0_OT_SELF_CLEAR_SHIFT) & EWDG_CTRL0_OT_SELF_CLEAR_MASK) +#define EWDG_CTRL0_OT_SELF_CLEAR_GET(x) (((uint32_t)(x) & EWDG_CTRL0_OT_SELF_CLEAR_MASK) >> EWDG_CTRL0_OT_SELF_CLEAR_SHIFT) + +/* + * REF_OT_REQ (RW) + * + * If refresh event has to be limited into a period after refresh unlocked. + * Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter + */ +#define EWDG_CTRL0_REF_OT_REQ_MASK (0x8000U) +#define EWDG_CTRL0_REF_OT_REQ_SHIFT (15U) +#define EWDG_CTRL0_REF_OT_REQ_SET(x) (((uint32_t)(x) << EWDG_CTRL0_REF_OT_REQ_SHIFT) & EWDG_CTRL0_REF_OT_REQ_MASK) +#define EWDG_CTRL0_REF_OT_REQ_GET(x) (((uint32_t)(x) & EWDG_CTRL0_REF_OT_REQ_MASK) >> EWDG_CTRL0_REF_OT_REQ_SHIFT) + +/* + * WIN_UPPER (RW) + * + * The upper threshold of window value + * The window period upper limit is: lower_limit + (overtime_rst_value / 16) * upper_reg_value + * If this register value is zero, then no upper level limitation + */ +#define EWDG_CTRL0_WIN_UPPER_MASK (0x7000U) +#define EWDG_CTRL0_WIN_UPPER_SHIFT (12U) +#define EWDG_CTRL0_WIN_UPPER_SET(x) (((uint32_t)(x) << EWDG_CTRL0_WIN_UPPER_SHIFT) & EWDG_CTRL0_WIN_UPPER_MASK) +#define EWDG_CTRL0_WIN_UPPER_GET(x) (((uint32_t)(x) & EWDG_CTRL0_WIN_UPPER_MASK) >> EWDG_CTRL0_WIN_UPPER_SHIFT) + +/* + * REF_LOCK (RW) + * + * WDT refresh has to be unlocked firstly once refresh lock is enable. + */ +#define EWDG_CTRL0_REF_LOCK_MASK (0x20U) +#define EWDG_CTRL0_REF_LOCK_SHIFT (5U) +#define EWDG_CTRL0_REF_LOCK_SET(x) (((uint32_t)(x) << EWDG_CTRL0_REF_LOCK_SHIFT) & EWDG_CTRL0_REF_LOCK_MASK) +#define EWDG_CTRL0_REF_LOCK_GET(x) (((uint32_t)(x) & EWDG_CTRL0_REF_LOCK_MASK) >> EWDG_CTRL0_REF_LOCK_SHIFT) + +/* + * REF_UNLOCK_MEC (RW) + * + * Unlock refresh mechanism + * 00: the required unlock password is the same with refresh_psd_register + * 01: the required unlock password is a ring shift left value of refresh_psd_register + * 10: the required unlock password is always 16'h55AA, no matter what refresh_psd_register is + * 11: the required unlock password is a LSFR result of refresh_psd_register, the characteristic polynomial is X^15 + 1 + */ +#define EWDG_CTRL0_REF_UNLOCK_MEC_MASK (0x18U) +#define EWDG_CTRL0_REF_UNLOCK_MEC_SHIFT (3U) +#define EWDG_CTRL0_REF_UNLOCK_MEC_SET(x) (((uint32_t)(x) << EWDG_CTRL0_REF_UNLOCK_MEC_SHIFT) & EWDG_CTRL0_REF_UNLOCK_MEC_MASK) +#define EWDG_CTRL0_REF_UNLOCK_MEC_GET(x) (((uint32_t)(x) & EWDG_CTRL0_REF_UNLOCK_MEC_MASK) >> EWDG_CTRL0_REF_UNLOCK_MEC_SHIFT) + +/* + * EN_DBG (RW) + * + * WTD enable or not in debug mode + */ +#define EWDG_CTRL0_EN_DBG_MASK (0x4U) +#define EWDG_CTRL0_EN_DBG_SHIFT (2U) +#define EWDG_CTRL0_EN_DBG_SET(x) (((uint32_t)(x) << EWDG_CTRL0_EN_DBG_SHIFT) & EWDG_CTRL0_EN_DBG_MASK) +#define EWDG_CTRL0_EN_DBG_GET(x) (((uint32_t)(x) & EWDG_CTRL0_EN_DBG_MASK) >> EWDG_CTRL0_EN_DBG_SHIFT) + +/* + * EN_LP (RW) + * + * WDT enable or not in low power mode + * 2'b00: wdt is halted once in low power mode + * 2'b01: wdt will work with 1/4 normal clock freq in low power mode + * 2'b10: wdt will work with 1/2 normal clock freq in low power mode + * 2'b11: wdt will work with normal clock freq in low power mode + */ +#define EWDG_CTRL0_EN_LP_MASK (0x3U) +#define EWDG_CTRL0_EN_LP_SHIFT (0U) +#define EWDG_CTRL0_EN_LP_SET(x) (((uint32_t)(x) << EWDG_CTRL0_EN_LP_SHIFT) & EWDG_CTRL0_EN_LP_MASK) +#define EWDG_CTRL0_EN_LP_GET(x) (((uint32_t)(x) & EWDG_CTRL0_EN_LP_MASK) >> EWDG_CTRL0_EN_LP_SHIFT) + +/* Bitfield definition for register: CTRL1 */ +/* + * REF_FAIL_RST_EN (RW) + * + * Refresh violation will trigger an reset. + * These event will be taken as a refresh violation: + * 1) Not refresh in the window once window mode is enabled + * 2) Not unlock refresh firstly if unlock is required + * 3) Not refresh in the required time after unlock, once refresh unlock overtime is enabled. + * 4) Not write the required word to refresh wdt. + */ +#define EWDG_CTRL1_REF_FAIL_RST_EN_MASK (0x800000UL) +#define EWDG_CTRL1_REF_FAIL_RST_EN_SHIFT (23U) +#define EWDG_CTRL1_REF_FAIL_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_REF_FAIL_RST_EN_SHIFT) & EWDG_CTRL1_REF_FAIL_RST_EN_MASK) +#define EWDG_CTRL1_REF_FAIL_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_REF_FAIL_RST_EN_MASK) >> EWDG_CTRL1_REF_FAIL_RST_EN_SHIFT) + +/* + * REF_FAIL_INT_EN (RW) + * + * Refresh violation will trigger an interrupt + */ +#define EWDG_CTRL1_REF_FAIL_INT_EN_MASK (0x400000UL) +#define EWDG_CTRL1_REF_FAIL_INT_EN_SHIFT (22U) +#define EWDG_CTRL1_REF_FAIL_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_REF_FAIL_INT_EN_SHIFT) & EWDG_CTRL1_REF_FAIL_INT_EN_MASK) +#define EWDG_CTRL1_REF_FAIL_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_REF_FAIL_INT_EN_MASK) >> EWDG_CTRL1_REF_FAIL_INT_EN_SHIFT) + +/* + * UNL_REF_FAIL_RST_EN (RW) + * + * Refresh unlock fail will trigger a reset + */ +#define EWDG_CTRL1_UNL_REF_FAIL_RST_EN_MASK (0x200000UL) +#define EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SHIFT (21U) +#define EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SHIFT) & EWDG_CTRL1_UNL_REF_FAIL_RST_EN_MASK) +#define EWDG_CTRL1_UNL_REF_FAIL_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_UNL_REF_FAIL_RST_EN_MASK) >> EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SHIFT) + +/* + * UNL_REF_FAIL_INT_EN (RW) + * + * Refresh unlock fail will trigger a interrupt + */ +#define EWDG_CTRL1_UNL_REF_FAIL_INT_EN_MASK (0x100000UL) +#define EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SHIFT (20U) +#define EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SHIFT) & EWDG_CTRL1_UNL_REF_FAIL_INT_EN_MASK) +#define EWDG_CTRL1_UNL_REF_FAIL_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_UNL_REF_FAIL_INT_EN_MASK) >> EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SHIFT) + +/* + * OT_RST_EN (RW) + * + * WDT overtime will generate a reset + */ +#define EWDG_CTRL1_OT_RST_EN_MASK (0x20000UL) +#define EWDG_CTRL1_OT_RST_EN_SHIFT (17U) +#define EWDG_CTRL1_OT_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_OT_RST_EN_SHIFT) & EWDG_CTRL1_OT_RST_EN_MASK) +#define EWDG_CTRL1_OT_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_OT_RST_EN_MASK) >> EWDG_CTRL1_OT_RST_EN_SHIFT) + +/* + * OT_INT_EN (RW) + * + * WDT can generate an interrupt warning before timeout + */ +#define EWDG_CTRL1_OT_INT_EN_MASK (0x10000UL) +#define EWDG_CTRL1_OT_INT_EN_SHIFT (16U) +#define EWDG_CTRL1_OT_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_OT_INT_EN_SHIFT) & EWDG_CTRL1_OT_INT_EN_MASK) +#define EWDG_CTRL1_OT_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_OT_INT_EN_MASK) >> EWDG_CTRL1_OT_INT_EN_SHIFT) + +/* + * CTL_VIO_RST_EN (RW) + * + * Ctrl update violation will trigger a reset + * The violation event is to try updating the locked register before unlock them + */ +#define EWDG_CTRL1_CTL_VIO_RST_EN_MASK (0x80U) +#define EWDG_CTRL1_CTL_VIO_RST_EN_SHIFT (7U) +#define EWDG_CTRL1_CTL_VIO_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_CTL_VIO_RST_EN_SHIFT) & EWDG_CTRL1_CTL_VIO_RST_EN_MASK) +#define EWDG_CTRL1_CTL_VIO_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_CTL_VIO_RST_EN_MASK) >> EWDG_CTRL1_CTL_VIO_RST_EN_SHIFT) + +/* + * CTL_VIO_INT_EN (RW) + * + * Ctrl update violation will trigger a interrupt + */ +#define EWDG_CTRL1_CTL_VIO_INT_EN_MASK (0x40U) +#define EWDG_CTRL1_CTL_VIO_INT_EN_SHIFT (6U) +#define EWDG_CTRL1_CTL_VIO_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_CTL_VIO_INT_EN_SHIFT) & EWDG_CTRL1_CTL_VIO_INT_EN_MASK) +#define EWDG_CTRL1_CTL_VIO_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_CTL_VIO_INT_EN_MASK) >> EWDG_CTRL1_CTL_VIO_INT_EN_SHIFT) + +/* + * UNL_CTL_FAIL_RST_EN (RW) + * + * Unlock register update failure will trigger a reset + */ +#define EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_MASK (0x20U) +#define EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SHIFT (5U) +#define EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SHIFT) & EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_MASK) +#define EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_MASK) >> EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SHIFT) + +/* + * UNL_CTL_FAIL_INT_EN (RW) + * + * Unlock register update failure will trigger a interrupt + */ +#define EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_MASK (0x10U) +#define EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SHIFT (4U) +#define EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SHIFT) & EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_MASK) +#define EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_MASK) >> EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SHIFT) + +/* + * PARITY_FAIL_RST_EN (RW) + * + * Parity error will trigger a reset + * A parity check is required once writing to ctrl0 and ctrl1 register. The result should be zero by modular two addition of all bits + */ +#define EWDG_CTRL1_PARITY_FAIL_RST_EN_MASK (0x8U) +#define EWDG_CTRL1_PARITY_FAIL_RST_EN_SHIFT (3U) +#define EWDG_CTRL1_PARITY_FAIL_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_PARITY_FAIL_RST_EN_SHIFT) & EWDG_CTRL1_PARITY_FAIL_RST_EN_MASK) +#define EWDG_CTRL1_PARITY_FAIL_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_PARITY_FAIL_RST_EN_MASK) >> EWDG_CTRL1_PARITY_FAIL_RST_EN_SHIFT) + +/* + * PARITY_FAIL_INT_EN (RW) + * + * Parity error will trigger a interrupt + */ +#define EWDG_CTRL1_PARITY_FAIL_INT_EN_MASK (0x4U) +#define EWDG_CTRL1_PARITY_FAIL_INT_EN_SHIFT (2U) +#define EWDG_CTRL1_PARITY_FAIL_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_PARITY_FAIL_INT_EN_SHIFT) & EWDG_CTRL1_PARITY_FAIL_INT_EN_MASK) +#define EWDG_CTRL1_PARITY_FAIL_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_PARITY_FAIL_INT_EN_MASK) >> EWDG_CTRL1_PARITY_FAIL_INT_EN_SHIFT) + +/* Bitfield definition for register: OT_INT_VAL */ +/* + * OT_INT_VAL (RW) + * + * WDT timeout interrupt value + */ +#define EWDG_OT_INT_VAL_OT_INT_VAL_MASK (0xFFFFU) +#define EWDG_OT_INT_VAL_OT_INT_VAL_SHIFT (0U) +#define EWDG_OT_INT_VAL_OT_INT_VAL_SET(x) (((uint32_t)(x) << EWDG_OT_INT_VAL_OT_INT_VAL_SHIFT) & EWDG_OT_INT_VAL_OT_INT_VAL_MASK) +#define EWDG_OT_INT_VAL_OT_INT_VAL_GET(x) (((uint32_t)(x) & EWDG_OT_INT_VAL_OT_INT_VAL_MASK) >> EWDG_OT_INT_VAL_OT_INT_VAL_SHIFT) + +/* Bitfield definition for register: OT_RST_VAL */ +/* + * OT_RST_VAL (RW) + * + * WDT timeout reset value + */ +#define EWDG_OT_RST_VAL_OT_RST_VAL_MASK (0xFFFFU) +#define EWDG_OT_RST_VAL_OT_RST_VAL_SHIFT (0U) +#define EWDG_OT_RST_VAL_OT_RST_VAL_SET(x) (((uint32_t)(x) << EWDG_OT_RST_VAL_OT_RST_VAL_SHIFT) & EWDG_OT_RST_VAL_OT_RST_VAL_MASK) +#define EWDG_OT_RST_VAL_OT_RST_VAL_GET(x) (((uint32_t)(x) & EWDG_OT_RST_VAL_OT_RST_VAL_MASK) >> EWDG_OT_RST_VAL_OT_RST_VAL_SHIFT) + +/* Bitfield definition for register: WDT_REFRESH_REG */ +/* + * WDT_REFRESH_REG (WO) + * + * Write this register by 32'h5A45_524F to refresh wdog + * Note: Reading this register can read back wdt real time counter value, while it is only used by debug purpose + */ +#define EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_MASK (0xFFFFFFFFUL) +#define EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SHIFT (0U) +#define EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SET(x) (((uint32_t)(x) << EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SHIFT) & EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_MASK) +#define EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_GET(x) (((uint32_t)(x) & EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_MASK) >> EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SHIFT) + +/* Bitfield definition for register: WDT_STATUS */ +/* + * PARITY_ERROR (RW) + * + * parity error + * Write one to clear the bit + */ +#define EWDG_WDT_STATUS_PARITY_ERROR_MASK (0x40U) +#define EWDG_WDT_STATUS_PARITY_ERROR_SHIFT (6U) +#define EWDG_WDT_STATUS_PARITY_ERROR_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_PARITY_ERROR_SHIFT) & EWDG_WDT_STATUS_PARITY_ERROR_MASK) +#define EWDG_WDT_STATUS_PARITY_ERROR_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_PARITY_ERROR_MASK) >> EWDG_WDT_STATUS_PARITY_ERROR_SHIFT) + +/* + * OT_RST (RO) + * + * Timeout happens, a reset will happen once enable bit set + * This bit can be cleared only by refreshing wdt or reset + */ +#define EWDG_WDT_STATUS_OT_RST_MASK (0x20U) +#define EWDG_WDT_STATUS_OT_RST_SHIFT (5U) +#define EWDG_WDT_STATUS_OT_RST_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_OT_RST_MASK) >> EWDG_WDT_STATUS_OT_RST_SHIFT) + +/* + * OT_INT (RO) + * + * Timeout happens, a interrupt will happen once enable bit set + * This bit can be cleared only by refreshing wdt or reset + */ +#define EWDG_WDT_STATUS_OT_INT_MASK (0x10U) +#define EWDG_WDT_STATUS_OT_INT_SHIFT (4U) +#define EWDG_WDT_STATUS_OT_INT_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_OT_INT_MASK) >> EWDG_WDT_STATUS_OT_INT_SHIFT) + +/* + * CTL_UNL_FAIL (RW) + * + * Unlock ctrl reg update protection fail + * Write one to clear the bit + */ +#define EWDG_WDT_STATUS_CTL_UNL_FAIL_MASK (0x8U) +#define EWDG_WDT_STATUS_CTL_UNL_FAIL_SHIFT (3U) +#define EWDG_WDT_STATUS_CTL_UNL_FAIL_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_CTL_UNL_FAIL_SHIFT) & EWDG_WDT_STATUS_CTL_UNL_FAIL_MASK) +#define EWDG_WDT_STATUS_CTL_UNL_FAIL_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_CTL_UNL_FAIL_MASK) >> EWDG_WDT_STATUS_CTL_UNL_FAIL_SHIFT) + +/* + * CTL_VIO (RW) + * + * Violate register update protection mechanism + * Write one to clear the bit + */ +#define EWDG_WDT_STATUS_CTL_VIO_MASK (0x4U) +#define EWDG_WDT_STATUS_CTL_VIO_SHIFT (2U) +#define EWDG_WDT_STATUS_CTL_VIO_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_CTL_VIO_SHIFT) & EWDG_WDT_STATUS_CTL_VIO_MASK) +#define EWDG_WDT_STATUS_CTL_VIO_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_CTL_VIO_MASK) >> EWDG_WDT_STATUS_CTL_VIO_SHIFT) + +/* + * REF_UNL_FAIL (RW) + * + * Refresh unlock fail + * Write one to clear the bit + */ +#define EWDG_WDT_STATUS_REF_UNL_FAIL_MASK (0x2U) +#define EWDG_WDT_STATUS_REF_UNL_FAIL_SHIFT (1U) +#define EWDG_WDT_STATUS_REF_UNL_FAIL_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_REF_UNL_FAIL_SHIFT) & EWDG_WDT_STATUS_REF_UNL_FAIL_MASK) +#define EWDG_WDT_STATUS_REF_UNL_FAIL_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_REF_UNL_FAIL_MASK) >> EWDG_WDT_STATUS_REF_UNL_FAIL_SHIFT) + +/* + * REF_VIO (RW) + * + * Refresh fail + * Write one to clear the bit + */ +#define EWDG_WDT_STATUS_REF_VIO_MASK (0x1U) +#define EWDG_WDT_STATUS_REF_VIO_SHIFT (0U) +#define EWDG_WDT_STATUS_REF_VIO_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_REF_VIO_SHIFT) & EWDG_WDT_STATUS_REF_VIO_MASK) +#define EWDG_WDT_STATUS_REF_VIO_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_REF_VIO_MASK) >> EWDG_WDT_STATUS_REF_VIO_SHIFT) + +/* Bitfield definition for register: CFG_PROT */ +/* + * UPD_OT_TIME (RW) + * + * The period in which register update has to be in after unlock + * The required period is less than： 128 * 2 ^ UPD_OT_TIME * bus_clock_cycle + */ +#define EWDG_CFG_PROT_UPD_OT_TIME_MASK (0xF0000UL) +#define EWDG_CFG_PROT_UPD_OT_TIME_SHIFT (16U) +#define EWDG_CFG_PROT_UPD_OT_TIME_SET(x) (((uint32_t)(x) << EWDG_CFG_PROT_UPD_OT_TIME_SHIFT) & EWDG_CFG_PROT_UPD_OT_TIME_MASK) +#define EWDG_CFG_PROT_UPD_OT_TIME_GET(x) (((uint32_t)(x) & EWDG_CFG_PROT_UPD_OT_TIME_MASK) >> EWDG_CFG_PROT_UPD_OT_TIME_SHIFT) + +/* + * UPD_PSD (RW) + * + * The password of unlocking register update + */ +#define EWDG_CFG_PROT_UPD_PSD_MASK (0xFFFFU) +#define EWDG_CFG_PROT_UPD_PSD_SHIFT (0U) +#define EWDG_CFG_PROT_UPD_PSD_SET(x) (((uint32_t)(x) << EWDG_CFG_PROT_UPD_PSD_SHIFT) & EWDG_CFG_PROT_UPD_PSD_MASK) +#define EWDG_CFG_PROT_UPD_PSD_GET(x) (((uint32_t)(x) & EWDG_CFG_PROT_UPD_PSD_MASK) >> EWDG_CFG_PROT_UPD_PSD_SHIFT) + +/* Bitfield definition for register: REF_PROT */ +/* + * REF_UNL_PSD (RW) + * + * The password to unlock refreshing + */ +#define EWDG_REF_PROT_REF_UNL_PSD_MASK (0xFFFFU) +#define EWDG_REF_PROT_REF_UNL_PSD_SHIFT (0U) +#define EWDG_REF_PROT_REF_UNL_PSD_SET(x) (((uint32_t)(x) << EWDG_REF_PROT_REF_UNL_PSD_SHIFT) & EWDG_REF_PROT_REF_UNL_PSD_MASK) +#define EWDG_REF_PROT_REF_UNL_PSD_GET(x) (((uint32_t)(x) & EWDG_REF_PROT_REF_UNL_PSD_MASK) >> EWDG_REF_PROT_REF_UNL_PSD_SHIFT) + +/* Bitfield definition for register: WDT_EN */ +/* + * WDOG_EN (RW) + * + * Wdog is enabled, the re-written of this register is impacted by enable lock function + */ +#define EWDG_WDT_EN_WDOG_EN_MASK (0x1U) +#define EWDG_WDT_EN_WDOG_EN_SHIFT (0U) +#define EWDG_WDT_EN_WDOG_EN_SET(x) (((uint32_t)(x) << EWDG_WDT_EN_WDOG_EN_SHIFT) & EWDG_WDT_EN_WDOG_EN_MASK) +#define EWDG_WDT_EN_WDOG_EN_GET(x) (((uint32_t)(x) & EWDG_WDT_EN_WDOG_EN_MASK) >> EWDG_WDT_EN_WDOG_EN_SHIFT) + +/* Bitfield definition for register: REF_TIME */ +/* + * REFRESH_PERIOD (RW) + * + * The refresh period after refresh unlocked + * Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter + */ +#define EWDG_REF_TIME_REFRESH_PERIOD_MASK (0xFFFFU) +#define EWDG_REF_TIME_REFRESH_PERIOD_SHIFT (0U) +#define EWDG_REF_TIME_REFRESH_PERIOD_SET(x) (((uint32_t)(x) << EWDG_REF_TIME_REFRESH_PERIOD_SHIFT) & EWDG_REF_TIME_REFRESH_PERIOD_MASK) +#define EWDG_REF_TIME_REFRESH_PERIOD_GET(x) (((uint32_t)(x) & EWDG_REF_TIME_REFRESH_PERIOD_MASK) >> EWDG_REF_TIME_REFRESH_PERIOD_SHIFT) + + + + +#endif /* HPM_EWDG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ffa_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ffa_regs.h index 29781c6641b..8d7eeeb96c8 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ffa_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ffa_regs.h @@ -11,7 +11,7 @@ typedef struct { __RW uint32_t CTRL; /* 0x0: */ - __R uint32_t STATUS; /* 0x4: */ + __RW uint32_t STATUS; /* 0x4: */ __RW uint32_t INT_EN; /* 0x8: */ __R uint8_t RESERVED0[20]; /* 0xC - 0x1F: Reserved */ __RW uint32_t OP_CTRL; /* 0x20: */ @@ -71,66 +71,73 @@ typedef struct { /* Bitfield definition for register: STATUS */ /* - * FIR_OV (RO) + * FIR_OV (W1C) * * FIR Overflow err */ #define FFA_STATUS_FIR_OV_MASK (0x80U) #define FFA_STATUS_FIR_OV_SHIFT (7U) +#define FFA_STATUS_FIR_OV_SET(x) (((uint32_t)(x) << FFA_STATUS_FIR_OV_SHIFT) & FFA_STATUS_FIR_OV_MASK) #define FFA_STATUS_FIR_OV_GET(x) (((uint32_t)(x) & FFA_STATUS_FIR_OV_MASK) >> FFA_STATUS_FIR_OV_SHIFT) /* - * FFT_OV (RO) + * FFT_OV (W1C) * * FFT Overflow Err */ #define FFA_STATUS_FFT_OV_MASK (0x40U) #define FFA_STATUS_FFT_OV_SHIFT (6U) +#define FFA_STATUS_FFT_OV_SET(x) (((uint32_t)(x) << FFA_STATUS_FFT_OV_SHIFT) & FFA_STATUS_FFT_OV_MASK) #define FFA_STATUS_FFT_OV_GET(x) (((uint32_t)(x) & FFA_STATUS_FFT_OV_MASK) >> FFA_STATUS_FFT_OV_SHIFT) /* - * WR_ERR (RO) + * WR_ERR (W1C) * * AXI Data Write Error */ #define FFA_STATUS_WR_ERR_MASK (0x20U) #define FFA_STATUS_WR_ERR_SHIFT (5U) +#define FFA_STATUS_WR_ERR_SET(x) (((uint32_t)(x) << FFA_STATUS_WR_ERR_SHIFT) & FFA_STATUS_WR_ERR_MASK) #define FFA_STATUS_WR_ERR_GET(x) (((uint32_t)(x) & FFA_STATUS_WR_ERR_MASK) >> FFA_STATUS_WR_ERR_SHIFT) /* - * RD_NXT_ERR (RO) + * RD_NXT_ERR (W1C) * * AXI Read Bus Error for NXT DATA */ #define FFA_STATUS_RD_NXT_ERR_MASK (0x10U) #define FFA_STATUS_RD_NXT_ERR_SHIFT (4U) +#define FFA_STATUS_RD_NXT_ERR_SET(x) (((uint32_t)(x) << FFA_STATUS_RD_NXT_ERR_SHIFT) & FFA_STATUS_RD_NXT_ERR_MASK) #define FFA_STATUS_RD_NXT_ERR_GET(x) (((uint32_t)(x) & FFA_STATUS_RD_NXT_ERR_MASK) >> FFA_STATUS_RD_NXT_ERR_SHIFT) /* - * RD_ERR (RO) + * RD_ERR (W1C) * * AXI Data Read Error */ #define FFA_STATUS_RD_ERR_MASK (0x8U) #define FFA_STATUS_RD_ERR_SHIFT (3U) +#define FFA_STATUS_RD_ERR_SET(x) (((uint32_t)(x) << FFA_STATUS_RD_ERR_SHIFT) & FFA_STATUS_RD_ERR_MASK) #define FFA_STATUS_RD_ERR_GET(x) (((uint32_t)(x) & FFA_STATUS_RD_ERR_MASK) >> FFA_STATUS_RD_ERR_SHIFT) /* - * NXT_CMD_RD_DONE (RO) + * NXT_CMD_RD_DONE (W1C) * * Indicate that next command sequence is already read into the module. */ #define FFA_STATUS_NXT_CMD_RD_DONE_MASK (0x2U) #define FFA_STATUS_NXT_CMD_RD_DONE_SHIFT (1U) +#define FFA_STATUS_NXT_CMD_RD_DONE_SET(x) (((uint32_t)(x) << FFA_STATUS_NXT_CMD_RD_DONE_SHIFT) & FFA_STATUS_NXT_CMD_RD_DONE_MASK) #define FFA_STATUS_NXT_CMD_RD_DONE_GET(x) (((uint32_t)(x) & FFA_STATUS_NXT_CMD_RD_DONE_MASK) >> FFA_STATUS_NXT_CMD_RD_DONE_SHIFT) /* - * OP_CMD_DONE (RO) + * OP_CMD_DONE (W1C) * * Indicate that operation cmd is done, and data are available in system memory. */ #define FFA_STATUS_OP_CMD_DONE_MASK (0x1U) #define FFA_STATUS_OP_CMD_DONE_SHIFT (0U) +#define FFA_STATUS_OP_CMD_DONE_SET(x) (((uint32_t)(x) << FFA_STATUS_OP_CMD_DONE_SHIFT) & FFA_STATUS_OP_CMD_DONE_MASK) #define FFA_STATUS_OP_CMD_DONE_GET(x) (((uint32_t)(x) & FFA_STATUS_OP_CMD_DONE_MASK) >> FFA_STATUS_OP_CMD_DONE_SHIFT) /* Bitfield definition for register: INT_EN */ @@ -557,4 +564,4 @@ typedef struct { -#endif /* HPM_FFA_H */ \ No newline at end of file +#endif /* HPM_FFA_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_gpio_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_gpio_regs.h index a6ac8a17567..8d47fbf6fb2 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_gpio_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_gpio_regs.h @@ -54,6 +54,12 @@ typedef struct { __RW uint32_t CLEAR; /* 0x708: GPIO interrupt asynchronous clear */ __RW uint32_t TOGGLE; /* 0x70C: GPIO interrupt asynchronous toggle */ } AS[16]; + struct { + __RW uint32_t VALUE; /* 0x800: GPIO dual edge interrupt enable value */ + __RW uint32_t SET; /* 0x804: GPIO dual edge interrupt enable set */ + __RW uint32_t CLEAR; /* 0x808: GPIO dual edge interrupt enable clear */ + __RW uint32_t TOGGLE; /* 0x80C: GPIO dual edge interrupt enable toggle */ + } PD[16]; } GPIO_Type; @@ -398,6 +404,58 @@ typedef struct { #define GPIO_AS_TOGGLE_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_TOGGLE_IRQ_ASYNC_SHIFT) & GPIO_AS_TOGGLE_IRQ_ASYNC_MASK) #define GPIO_AS_TOGGLE_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_TOGGLE_IRQ_ASYNC_MASK) >> GPIO_AS_TOGGLE_IRQ_ASYNC_SHIFT) +/* Bitfield definition for register of struct array PD: VALUE */ +/* + * IRQ_DUAL (RW) + * + * GPIO dual edge interrupt enable + * 0: single edge interrupt + * 1: dual edge interrupt enable + */ +#define GPIO_PD_VALUE_IRQ_DUAL_MASK (0x1U) +#define GPIO_PD_VALUE_IRQ_DUAL_SHIFT (0U) +#define GPIO_PD_VALUE_IRQ_DUAL_SET(x) (((uint32_t)(x) << GPIO_PD_VALUE_IRQ_DUAL_SHIFT) & GPIO_PD_VALUE_IRQ_DUAL_MASK) +#define GPIO_PD_VALUE_IRQ_DUAL_GET(x) (((uint32_t)(x) & GPIO_PD_VALUE_IRQ_DUAL_MASK) >> GPIO_PD_VALUE_IRQ_DUAL_SHIFT) + +/* Bitfield definition for register of struct array PD: SET */ +/* + * IRQ_DUAL (RW) + * + * GPIO dual edge interrupt enable set + * 0: keep original edge interrupt type + * 1: dual edge interrupt enable + */ +#define GPIO_PD_SET_IRQ_DUAL_MASK (0x1U) +#define GPIO_PD_SET_IRQ_DUAL_SHIFT (0U) +#define GPIO_PD_SET_IRQ_DUAL_SET(x) (((uint32_t)(x) << GPIO_PD_SET_IRQ_DUAL_SHIFT) & GPIO_PD_SET_IRQ_DUAL_MASK) +#define GPIO_PD_SET_IRQ_DUAL_GET(x) (((uint32_t)(x) & GPIO_PD_SET_IRQ_DUAL_MASK) >> GPIO_PD_SET_IRQ_DUAL_SHIFT) + +/* Bitfield definition for register of struct array PD: CLEAR */ +/* + * IRQ_DUAL (RW) + * + * GPIO dual edge interrupt enable clear + * 0: keep original edge interrupt type + * 1: single edge interrupt enable + */ +#define GPIO_PD_CLEAR_IRQ_DUAL_MASK (0x1U) +#define GPIO_PD_CLEAR_IRQ_DUAL_SHIFT (0U) +#define GPIO_PD_CLEAR_IRQ_DUAL_SET(x) (((uint32_t)(x) << GPIO_PD_CLEAR_IRQ_DUAL_SHIFT) & GPIO_PD_CLEAR_IRQ_DUAL_MASK) +#define GPIO_PD_CLEAR_IRQ_DUAL_GET(x) (((uint32_t)(x) & GPIO_PD_CLEAR_IRQ_DUAL_MASK) >> GPIO_PD_CLEAR_IRQ_DUAL_SHIFT) + +/* Bitfield definition for register of struct array PD: TOGGLE */ +/* + * IRQ_DUAL (RW) + * + * GPIO dual edge interrupt enable toggle + * 0: keep original edge interrupt type + * 1: change original edge interrupt type to another one. + */ +#define GPIO_PD_TOGGLE_IRQ_DUAL_MASK (0x1U) +#define GPIO_PD_TOGGLE_IRQ_DUAL_SHIFT (0U) +#define GPIO_PD_TOGGLE_IRQ_DUAL_SET(x) (((uint32_t)(x) << GPIO_PD_TOGGLE_IRQ_DUAL_SHIFT) & GPIO_PD_TOGGLE_IRQ_DUAL_MASK) +#define GPIO_PD_TOGGLE_IRQ_DUAL_GET(x) (((uint32_t)(x) & GPIO_PD_TOGGLE_IRQ_DUAL_MASK) >> GPIO_PD_TOGGLE_IRQ_DUAL_SHIFT) + /* DI register group index macro definition */ @@ -488,5 +546,16 @@ typedef struct { #define GPIO_AS_GPIOY (14UL) #define GPIO_AS_GPIOZ (15UL) +/* PD register group index macro definition */ +#define GPIO_PD_GPIOA (0UL) +#define GPIO_PD_GPIOB (1UL) +#define GPIO_PD_GPIOC (2UL) +#define GPIO_PD_GPIOD (3UL) +#define GPIO_PD_GPIOE (4UL) +#define GPIO_PD_GPIOF (5UL) +#define GPIO_PD_GPIOX (13UL) +#define GPIO_PD_GPIOY (14UL) +#define GPIO_PD_GPIOZ (15UL) + -#endif /* HPM_GPIO_H */ \ No newline at end of file +#endif /* HPM_GPIO_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_gpu_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_gpu_regs.h new file mode 100644 index 00000000000..9b4b1282ecc --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_gpu_regs.h @@ -0,0 +1,651 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_GPU_H +#define HPM_GPU_H + +typedef struct { + __RW uint32_t AQHICLOCKCONTROL; /* 0x0: clock control register */ + __R uint32_t AQHILDLE; /* 0x4: idle status register */ + __R uint8_t RESERVED0[8]; /* 0x8 - 0xF: Reserved */ + __R uint32_t AQINTRACKNOWLEDGE; /* 0x10: interrupt acknoledge register */ + __RW uint32_t AQINTRENBL; /* 0x14: interrupt enable register */ + __R uint8_t RESERVED1[12]; /* 0x18 - 0x23: Reserved */ + __R uint32_t GCCHIPREV; /* 0x24: chip revison register */ + __R uint32_t GCCHIPDATE; /* 0x28: chip date register */ + __R uint8_t RESERVED2[108]; /* 0x2C - 0x97: Reserved */ + __R uint32_t GCREGHICHIPPATCHREV; /* 0x98: chip patch revision register */ + __R uint8_t RESERVED3[12]; /* 0x9C - 0xA7: Reserved */ + __R uint32_t GCPRODUCTID; /* 0xA8: product identification register */ + __R uint8_t RESERVED4[84]; /* 0xAC - 0xFF: Reserved */ + __RW uint32_t GCMODULEPOWERCONTROLS; /* 0x100: module power control register */ + __RW uint32_t GCMODULEPOWERMODULECONTROL; /* 0x104: module power module control register */ + __R uint32_t GCMODULEPOWERMODULESTATUS; /* 0x108: module power module status register */ + __R uint8_t RESERVED5[756]; /* 0x10C - 0x3FF: Reserved */ + __RW uint32_t AQMEMORYFEPAGETABLE; /* 0x400: fetch engine page table base address register */ + __R uint8_t RESERVED6[16]; /* 0x404 - 0x413: Reserved */ + __RW uint32_t AQMEMORYDEBUG; /* 0x414: memory debug register */ + __R uint8_t RESERVED7[20]; /* 0x418 - 0x42B: Reserved */ + __RW uint32_t AQREGISTERTIMINGCONTROL; /* 0x42C: timing control register */ + __R uint8_t RESERVED8[208]; /* 0x430 - 0x4FF: Reserved */ + __RW uint32_t GCREGFETCHADDRESS; /* 0x500: fetch command buffer base address register */ + __RW uint32_t GCREGFETCHCONTROL; /* 0x504: fetch control register */ + __R uint32_t GCREGCURRENTFETCHADDRESS; /* 0x508: current fetch command address register */ +} GPU_Type; + + +/* Bitfield definition for register: AQHICLOCKCONTROL */ +/* + * ISOLATE_GPU (RW) + * + * isolate GPU bit, used for power on/off + */ +#define GPU_AQHICLOCKCONTROL_ISOLATE_GPU_MASK (0x80000UL) +#define GPU_AQHICLOCKCONTROL_ISOLATE_GPU_SHIFT (19U) +#define GPU_AQHICLOCKCONTROL_ISOLATE_GPU_SET(x) (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_ISOLATE_GPU_SHIFT) & GPU_AQHICLOCKCONTROL_ISOLATE_GPU_MASK) +#define GPU_AQHICLOCKCONTROL_ISOLATE_GPU_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_ISOLATE_GPU_MASK) >> GPU_AQHICLOCKCONTROL_ISOLATE_GPU_SHIFT) + +/* + * IDLE_VG (R) + * + * vg pipe is idle + */ +#define GPU_AQHICLOCKCONTROL_IDLE_VG_MASK (0x40000UL) +#define GPU_AQHICLOCKCONTROL_IDLE_VG_SHIFT (18U) +#define GPU_AQHICLOCKCONTROL_IDLE_VG_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_IDLE_VG_MASK) >> GPU_AQHICLOCKCONTROL_IDLE_VG_SHIFT) + +/* + * IDLE2_D (R) + * + * 2D pipe is idle or not present + */ +#define GPU_AQHICLOCKCONTROL_IDLE2_D_MASK (0x20000UL) +#define GPU_AQHICLOCKCONTROL_IDLE2_D_SHIFT (17U) +#define GPU_AQHICLOCKCONTROL_IDLE2_D_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_IDLE2_D_MASK) >> GPU_AQHICLOCKCONTROL_IDLE2_D_SHIFT) + +/* + * IDLE3_D (R) + * + * 3D pipe is idle or not present + */ +#define GPU_AQHICLOCKCONTROL_IDLE3_D_MASK (0x10000UL) +#define GPU_AQHICLOCKCONTROL_IDLE3_D_SHIFT (16U) +#define GPU_AQHICLOCKCONTROL_IDLE3_D_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_IDLE3_D_MASK) >> GPU_AQHICLOCKCONTROL_IDLE3_D_SHIFT) + +/* + * DISABLE_RAM_POWER_OPTIMIZATION (RW) + * + * disables ram power optimization + */ +#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_MASK (0x2000U) +#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_SHIFT (13U) +#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_SET(x) (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_SHIFT) & GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_MASK) +#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_MASK) >> GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_SHIFT) + +/* + * SOFT_RESET (RW) + * + * soft reset the IP + */ +#define GPU_AQHICLOCKCONTROL_SOFT_RESET_MASK (0x1000U) +#define GPU_AQHICLOCKCONTROL_SOFT_RESET_SHIFT (12U) +#define GPU_AQHICLOCKCONTROL_SOFT_RESET_SET(x) (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_SOFT_RESET_SHIFT) & GPU_AQHICLOCKCONTROL_SOFT_RESET_MASK) +#define GPU_AQHICLOCKCONTROL_SOFT_RESET_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_SOFT_RESET_MASK) >> GPU_AQHICLOCKCONTROL_SOFT_RESET_SHIFT) + +/* + * DISABLE_DEBUG_REGISTERS (RW) + * + * disable debug registers + */ +#define GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_MASK (0x800U) +#define GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_SHIFT (11U) +#define GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_SET(x) (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_SHIFT) & GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_MASK) +#define GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_MASK) >> GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_SHIFT) + +/* + * DISABLE_RAM_CLOCK_GATING (RW) + * + * disables clock gating for rams + */ +#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_MASK (0x400U) +#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_SHIFT (10U) +#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_SET(x) (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_SHIFT) & GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_MASK) +#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_MASK) >> GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_SHIFT) + +/* + * FSCALE_CMD_LOAD (RW) + * + * core clock frequency scale value enable + */ +#define GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_MASK (0x200U) +#define GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_SHIFT (9U) +#define GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_SET(x) (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_SHIFT) & GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_MASK) +#define GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_MASK) >> GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_SHIFT) + +/* + * FSCALE_VAL (RW) + * + * core clock frequency scale value + */ +#define GPU_AQHICLOCKCONTROL_FSCALE_VAL_MASK (0x1FCU) +#define GPU_AQHICLOCKCONTROL_FSCALE_VAL_SHIFT (2U) +#define GPU_AQHICLOCKCONTROL_FSCALE_VAL_SET(x) (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_FSCALE_VAL_SHIFT) & GPU_AQHICLOCKCONTROL_FSCALE_VAL_MASK) +#define GPU_AQHICLOCKCONTROL_FSCALE_VAL_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_FSCALE_VAL_MASK) >> GPU_AQHICLOCKCONTROL_FSCALE_VAL_SHIFT) + +/* + * CLK2D_DIS (RW) + * + * disable 2D/VG clock + */ +#define GPU_AQHICLOCKCONTROL_CLK2D_DIS_MASK (0x2U) +#define GPU_AQHICLOCKCONTROL_CLK2D_DIS_SHIFT (1U) +#define GPU_AQHICLOCKCONTROL_CLK2D_DIS_SET(x) (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_CLK2D_DIS_SHIFT) & GPU_AQHICLOCKCONTROL_CLK2D_DIS_MASK) +#define GPU_AQHICLOCKCONTROL_CLK2D_DIS_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_CLK2D_DIS_MASK) >> GPU_AQHICLOCKCONTROL_CLK2D_DIS_SHIFT) + +/* Bitfield definition for register: AQHILDLE */ +/* + * AXI_LP (R) + * + * axi is in low power mode + */ +#define GPU_AQHILDLE_AXI_LP_MASK (0x80000000UL) +#define GPU_AQHILDLE_AXI_LP_SHIFT (31U) +#define GPU_AQHILDLE_AXI_LP_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_AXI_LP_MASK) >> GPU_AQHILDLE_AXI_LP_SHIFT) + +/* + * IDLE_BLT (R) + * + * BLT is idle or not present + */ +#define GPU_AQHILDLE_IDLE_BLT_MASK (0x1000U) +#define GPU_AQHILDLE_IDLE_BLT_SHIFT (12U) +#define GPU_AQHILDLE_IDLE_BLT_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_BLT_MASK) >> GPU_AQHILDLE_IDLE_BLT_SHIFT) + +/* + * IDLE_TS (R) + * + * Tessellation Engine is idle + */ +#define GPU_AQHILDLE_IDLE_TS_MASK (0x800U) +#define GPU_AQHILDLE_IDLE_TS_SHIFT (11U) +#define GPU_AQHILDLE_IDLE_TS_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_TS_MASK) >> GPU_AQHILDLE_IDLE_TS_SHIFT) + +/* + * IDLE_FP (R) + * + * FP is idle or not present + */ +#define GPU_AQHILDLE_IDLE_FP_MASK (0x400U) +#define GPU_AQHILDLE_IDLE_FP_SHIFT (10U) +#define GPU_AQHILDLE_IDLE_FP_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_FP_MASK) >> GPU_AQHILDLE_IDLE_FP_SHIFT) + +/* + * IDLE_IM (R) + * + * Image Engine is idle + */ +#define GPU_AQHILDLE_IDLE_IM_MASK (0x200U) +#define GPU_AQHILDLE_IDLE_IM_SHIFT (9U) +#define GPU_AQHILDLE_IDLE_IM_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_IM_MASK) >> GPU_AQHILDLE_IDLE_IM_SHIFT) + +/* + * IDLE_VG (R) + * + * Vector Graphics Engine is idle + */ +#define GPU_AQHILDLE_IDLE_VG_MASK (0x100U) +#define GPU_AQHILDLE_IDLE_VG_SHIFT (8U) +#define GPU_AQHILDLE_IDLE_VG_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_VG_MASK) >> GPU_AQHILDLE_IDLE_VG_SHIFT) + +/* + * IDLE_TX (R) + * + * TX is idle or not present + */ +#define GPU_AQHILDLE_IDLE_TX_MASK (0x80U) +#define GPU_AQHILDLE_IDLE_TX_SHIFT (7U) +#define GPU_AQHILDLE_IDLE_TX_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_TX_MASK) >> GPU_AQHILDLE_IDLE_TX_SHIFT) + +/* + * IDLE_RA (R) + * + * RA is idle or not present + */ +#define GPU_AQHILDLE_IDLE_RA_MASK (0x40U) +#define GPU_AQHILDLE_IDLE_RA_SHIFT (6U) +#define GPU_AQHILDLE_IDLE_RA_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_RA_MASK) >> GPU_AQHILDLE_IDLE_RA_SHIFT) + +/* + * IDLE_SE (R) + * + * SE is idle or not present + */ +#define GPU_AQHILDLE_IDLE_SE_MASK (0x20U) +#define GPU_AQHILDLE_IDLE_SE_SHIFT (5U) +#define GPU_AQHILDLE_IDLE_SE_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_SE_MASK) >> GPU_AQHILDLE_IDLE_SE_SHIFT) + +/* + * IDLE_PA (R) + * + * PA is idle or not present + */ +#define GPU_AQHILDLE_IDLE_PA_MASK (0x10U) +#define GPU_AQHILDLE_IDLE_PA_SHIFT (4U) +#define GPU_AQHILDLE_IDLE_PA_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_PA_MASK) >> GPU_AQHILDLE_IDLE_PA_SHIFT) + +/* + * IDLE_SH (R) + * + * SH is idle or not present + */ +#define GPU_AQHILDLE_IDLE_SH_MASK (0x8U) +#define GPU_AQHILDLE_IDLE_SH_SHIFT (3U) +#define GPU_AQHILDLE_IDLE_SH_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_SH_MASK) >> GPU_AQHILDLE_IDLE_SH_SHIFT) + +/* + * IDLE_PE (R) + * + * Pixel engine is idle + */ +#define GPU_AQHILDLE_IDLE_PE_MASK (0x4U) +#define GPU_AQHILDLE_IDLE_PE_SHIFT (2U) +#define GPU_AQHILDLE_IDLE_PE_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_PE_MASK) >> GPU_AQHILDLE_IDLE_PE_SHIFT) + +/* + * IDLE_DE (R) + * + * DE is dile or not present + */ +#define GPU_AQHILDLE_IDLE_DE_MASK (0x2U) +#define GPU_AQHILDLE_IDLE_DE_SHIFT (1U) +#define GPU_AQHILDLE_IDLE_DE_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_DE_MASK) >> GPU_AQHILDLE_IDLE_DE_SHIFT) + +/* + * IDLE_FE (R) + * + * 0: fetch engine is busy 1:fetch engine is idle + */ +#define GPU_AQHILDLE_IDLE_FE_MASK (0x1U) +#define GPU_AQHILDLE_IDLE_FE_SHIFT (0U) +#define GPU_AQHILDLE_IDLE_FE_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_FE_MASK) >> GPU_AQHILDLE_IDLE_FE_SHIFT) + +/* Bitfield definition for register: AQINTRACKNOWLEDGE */ +/* + * INTR_VEC (R) + * + * for each interrupt event, 0=clear,1=interrupt active + */ +#define GPU_AQINTRACKNOWLEDGE_INTR_VEC_MASK (0xFFFFFFFFUL) +#define GPU_AQINTRACKNOWLEDGE_INTR_VEC_SHIFT (0U) +#define GPU_AQINTRACKNOWLEDGE_INTR_VEC_GET(x) (((uint32_t)(x) & GPU_AQINTRACKNOWLEDGE_INTR_VEC_MASK) >> GPU_AQINTRACKNOWLEDGE_INTR_VEC_SHIFT) + +/* Bitfield definition for register: AQINTRENBL */ +/* + * INTR_ENBL_VEC (RW) + * + * 0=disable interrupt; 1=enable interrupt + */ +#define GPU_AQINTRENBL_INTR_ENBL_VEC_MASK (0xFFFFFFFFUL) +#define GPU_AQINTRENBL_INTR_ENBL_VEC_SHIFT (0U) +#define GPU_AQINTRENBL_INTR_ENBL_VEC_SET(x) (((uint32_t)(x) << GPU_AQINTRENBL_INTR_ENBL_VEC_SHIFT) & GPU_AQINTRENBL_INTR_ENBL_VEC_MASK) +#define GPU_AQINTRENBL_INTR_ENBL_VEC_GET(x) (((uint32_t)(x) & GPU_AQINTRENBL_INTR_ENBL_VEC_MASK) >> GPU_AQINTRENBL_INTR_ENBL_VEC_SHIFT) + +/* Bitfield definition for register: GCCHIPREV */ +/* + * REV (R) + * + * revision + */ +#define GPU_GCCHIPREV_REV_MASK (0xFFFFFFFFUL) +#define GPU_GCCHIPREV_REV_SHIFT (0U) +#define GPU_GCCHIPREV_REV_GET(x) (((uint32_t)(x) & GPU_GCCHIPREV_REV_MASK) >> GPU_GCCHIPREV_REV_SHIFT) + +/* Bitfield definition for register: GCCHIPDATE */ +/* + * DATE (R) + * + * date + */ +#define GPU_GCCHIPDATE_DATE_MASK (0xFFFFFFFFUL) +#define GPU_GCCHIPDATE_DATE_SHIFT (0U) +#define GPU_GCCHIPDATE_DATE_GET(x) (((uint32_t)(x) & GPU_GCCHIPDATE_DATE_MASK) >> GPU_GCCHIPDATE_DATE_SHIFT) + +/* Bitfield definition for register: GCREGHICHIPPATCHREV */ +/* + * PATCH_REV (R) + * + * patch revision + */ +#define GPU_GCREGHICHIPPATCHREV_PATCH_REV_MASK (0xFFU) +#define GPU_GCREGHICHIPPATCHREV_PATCH_REV_SHIFT (0U) +#define GPU_GCREGHICHIPPATCHREV_PATCH_REV_GET(x) (((uint32_t)(x) & GPU_GCREGHICHIPPATCHREV_PATCH_REV_MASK) >> GPU_GCREGHICHIPPATCHREV_PATCH_REV_SHIFT) + +/* Bitfield definition for register: GCPRODUCTID */ +/* + * TYPE (R) + * + * product type is 3:VG + */ +#define GPU_GCPRODUCTID_TYPE_MASK (0xF000000UL) +#define GPU_GCPRODUCTID_TYPE_SHIFT (24U) +#define GPU_GCPRODUCTID_TYPE_GET(x) (((uint32_t)(x) & GPU_GCPRODUCTID_TYPE_MASK) >> GPU_GCPRODUCTID_TYPE_SHIFT) + +/* + * NUM (R) + * + * product number is 265 + */ +#define GPU_GCPRODUCTID_NUM_MASK (0xFFFFF0UL) +#define GPU_GCPRODUCTID_NUM_SHIFT (4U) +#define GPU_GCPRODUCTID_NUM_GET(x) (((uint32_t)(x) & GPU_GCPRODUCTID_NUM_MASK) >> GPU_GCPRODUCTID_NUM_SHIFT) + +/* + * GRADE_LEVEL (R) + * + * 0:None_no extra letter on the product name for this core 1:nano 5:nano ultra + */ +#define GPU_GCPRODUCTID_GRADE_LEVEL_MASK (0xFU) +#define GPU_GCPRODUCTID_GRADE_LEVEL_SHIFT (0U) +#define GPU_GCPRODUCTID_GRADE_LEVEL_GET(x) (((uint32_t)(x) & GPU_GCPRODUCTID_GRADE_LEVEL_MASK) >> GPU_GCPRODUCTID_GRADE_LEVEL_SHIFT) + +/* Bitfield definition for register: GCMODULEPOWERCONTROLS */ +/* + * TURN_OFF_COUNTER (RW) + * + * counter value for clock gating the module if the module is idle for this amout of clock cycles + */ +#define GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_MASK (0xFFFF0000UL) +#define GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_SHIFT (16U) +#define GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_SHIFT) & GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_MASK) +#define GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_MASK) >> GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_SHIFT) + +/* + * TURN_ON_COUNTER (RW) + * + * number of clock cycle gating the module if the modules is idle for this amout of clockk cycles + */ +#define GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_MASK (0xF0U) +#define GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_SHIFT (4U) +#define GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_SHIFT) & GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_MASK) +#define GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_MASK) >> GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_SHIFT) + +/* + * DISABLE_STARVE_MODULE_CLOCK_GATING (RW) + * + * disable module level clock gating for starve/idle condition + */ +#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_MASK (0x4U) +#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_SHIFT (2U) +#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_SHIFT) & GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_MASK) +#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_MASK) >> GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_SHIFT) + +/* + * DISABLE_STALL_MODULE_CLOCK_GATING (RW) + * + * disable module level clock gating for stall condition + */ +#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_MASK (0x2U) +#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_SHIFT (1U) +#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_SHIFT) & GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_MASK) +#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_MASK) >> GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_SHIFT) + +/* + * ENABLE_MODULE_CLOCK_GATING (RW) + * + * enable module level clock gating + */ +#define GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_MASK (0x1U) +#define GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_SHIFT (0U) +#define GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_SHIFT) & GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_MASK) +#define GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_MASK) >> GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_SHIFT) + +/* Bitfield definition for register: GCMODULEPOWERMODULECONTROL */ +/* + * DISABLE_MODULE_CLOCKGATING_FLEXA (RW) + * + * disables module level clock gating for flexa, not supported for all variants + */ +#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_MASK (0x1000U) +#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_SHIFT (12U) +#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_MASK) +#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_SHIFT) + +/* + * DISABLE_MODULE_CLOCK_GATING_TS (RW) + * + * disables module level clock gating for TS + */ +#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_MASK (0x800U) +#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_SHIFT (11U) +#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_MASK) +#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_SHIFT) + +/* + * DISABLE_MODULE_CLOCK_GATING_IM (RW) + * + * disables module level clock gating for IM + */ +#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_MASK (0x200U) +#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_SHIFT (9U) +#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_MASK) +#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_SHIFT) + +/* + * DISABLE_MODULE_CLOCK_GATING_VG (RW) + * + * disables module lelvel clock gating for VG + */ +#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_MASK (0x100U) +#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_SHIFT (8U) +#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_MASK) +#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_SHIFT) + +/* + * DISABLE_MODULE_CLOCK_GATING_PE (RW) + * + * disables module level clock gating for PE + */ +#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_MASK (0x4U) +#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_SHIFT (2U) +#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_MASK) +#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_SHIFT) + +/* + * DISABLE_MODULE_CLOCK_GATING_FE (RW) + * + * disables module level clock gating for FE + */ +#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_MASK (0x1U) +#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_SHIFT (0U) +#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_MASK) +#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_SHIFT) + +/* Bitfield definition for register: GCMODULEPOWERMODULESTATUS */ +/* + * MODULE_CLOCK_GATED_FLEXA (R) + * + * module level ckock gating is on for flexa + */ +#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FLEXA_MASK (0x1000U) +#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FLEXA_SHIFT (12U) +#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FLEXA_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FLEXA_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FLEXA_SHIFT) + +/* + * MODULE_CLOCK_GATED_TS (R) + * + * module level ckock gating is on for ts + */ +#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_TS_MASK (0x800U) +#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_TS_SHIFT (11U) +#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_TS_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_TS_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_TS_SHIFT) + +/* + * MODULE_CLOCK_GATED_IM (R) + * + * module level clock gating is on for IM + */ +#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_IM_MASK (0x200U) +#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_IM_SHIFT (9U) +#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_IM_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_IM_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_IM_SHIFT) + +/* + * MODULE_CLOCK_GATED_VG (R) + * + * module level clock gating is on for VG + */ +#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_VG_MASK (0x100U) +#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_VG_SHIFT (8U) +#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_VG_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_VG_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_VG_SHIFT) + +/* + * MODULE_CLOCK_GATED_PE (R) + * + * module level clock gating is on for PE + */ +#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_PE_MASK (0x4U) +#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_PE_SHIFT (2U) +#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_PE_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_PE_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_PE_SHIFT) + +/* + * MODULE_CLOCK_GATED_FE (R) + * + * module level clock gating is on for FE + */ +#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FE_MASK (0x1U) +#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FE_SHIFT (0U) +#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FE_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FE_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FE_SHIFT) + +/* Bitfield definition for register: AQMEMORYFEPAGETABLE */ +/* + * BASE_ADDRESS (RW) + * + * base address for the FE virtual address lookup table + */ +#define GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_MASK (0xFFFFF000UL) +#define GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_SHIFT (12U) +#define GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_SET(x) (((uint32_t)(x) << GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_SHIFT) & GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_MASK) +#define GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_GET(x) (((uint32_t)(x) & GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_MASK) >> GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_SHIFT) + +/* Bitfield definition for register: AQMEMORYDEBUG */ +/* + * ZCOMP_LIMIT (RW) + * + * not relevant for vector graphics IP + */ +#define GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_MASK (0x3F000000UL) +#define GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_SHIFT (24U) +#define GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_SET(x) (((uint32_t)(x) << GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_SHIFT) & GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_MASK) +#define GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_GET(x) (((uint32_t)(x) & GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_MASK) >> GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_SHIFT) + +/* + * MAX_OUTSTANDING_READS (RW) + * + * limits the total number of outstanding read requests + */ +#define GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_MASK (0xFFU) +#define GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_SHIFT (0U) +#define GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_SET(x) (((uint32_t)(x) << GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_SHIFT) & GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_MASK) +#define GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_GET(x) (((uint32_t)(x) & GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_MASK) >> GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_SHIFT) + +/* Bitfield definition for register: AQREGISTERTIMINGCONTROL */ +/* + * POWER_DOWN (RW) + * + * powerdown memory + */ +#define GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_MASK (0x100000UL) +#define GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_SHIFT (20U) +#define GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_SET(x) (((uint32_t)(x) << GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_SHIFT) & GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_MASK) +#define GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_GET(x) (((uint32_t)(x) & GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_MASK) >> GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_SHIFT) + +/* + * FAST_WTC (RW) + * + * WTC for fast rams + */ +#define GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_MASK (0xC0000UL) +#define GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_SHIFT (18U) +#define GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_SET(x) (((uint32_t)(x) << GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_SHIFT) & GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_MASK) +#define GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_GET(x) (((uint32_t)(x) & GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_MASK) >> GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_SHIFT) + +/* + * FAST_RTC (RW) + * + * RTC for fast rams + */ +#define GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_MASK (0x30000UL) +#define GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_SHIFT (16U) +#define GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_SET(x) (((uint32_t)(x) << GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_SHIFT) & GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_MASK) +#define GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_GET(x) (((uint32_t)(x) & GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_MASK) >> GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_SHIFT) + +/* + * FOR_RF2P (RW) + * + * for 2 port ram + */ +#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_MASK (0xFF00U) +#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_SHIFT (8U) +#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_SET(x) (((uint32_t)(x) << GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_SHIFT) & GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_MASK) +#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_GET(x) (((uint32_t)(x) & GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_MASK) >> GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_SHIFT) + +/* + * FOR_RF1P (RW) + * + * for 1 port ram + */ +#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_MASK (0xFFU) +#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_SHIFT (0U) +#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_SET(x) (((uint32_t)(x) << GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_SHIFT) & GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_MASK) +#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_GET(x) (((uint32_t)(x) & GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_MASK) >> GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_SHIFT) + +/* Bitfield definition for register: GCREGFETCHADDRESS */ +/* + * ADDRESS (RW) + * + * address of command buffer + */ +#define GPU_GCREGFETCHADDRESS_ADDRESS_MASK (0xFFFFFFFCUL) +#define GPU_GCREGFETCHADDRESS_ADDRESS_SHIFT (2U) +#define GPU_GCREGFETCHADDRESS_ADDRESS_SET(x) (((uint32_t)(x) << GPU_GCREGFETCHADDRESS_ADDRESS_SHIFT) & GPU_GCREGFETCHADDRESS_ADDRESS_MASK) +#define GPU_GCREGFETCHADDRESS_ADDRESS_GET(x) (((uint32_t)(x) & GPU_GCREGFETCHADDRESS_ADDRESS_MASK) >> GPU_GCREGFETCHADDRESS_ADDRESS_SHIFT) + +/* + * TYPE (RW) + * + * 0=system 2=vritual 1=local + */ +#define GPU_GCREGFETCHADDRESS_TYPE_MASK (0x3U) +#define GPU_GCREGFETCHADDRESS_TYPE_SHIFT (0U) +#define GPU_GCREGFETCHADDRESS_TYPE_SET(x) (((uint32_t)(x) << GPU_GCREGFETCHADDRESS_TYPE_SHIFT) & GPU_GCREGFETCHADDRESS_TYPE_MASK) +#define GPU_GCREGFETCHADDRESS_TYPE_GET(x) (((uint32_t)(x) & GPU_GCREGFETCHADDRESS_TYPE_MASK) >> GPU_GCREGFETCHADDRESS_TYPE_SHIFT) + +/* Bitfield definition for register: GCREGFETCHCONTROL */ +/* + * COUNT (RW) + * + * number of 64bit words to fetch + */ +#define GPU_GCREGFETCHCONTROL_COUNT_MASK (0x1FFFFFUL) +#define GPU_GCREGFETCHCONTROL_COUNT_SHIFT (0U) +#define GPU_GCREGFETCHCONTROL_COUNT_SET(x) (((uint32_t)(x) << GPU_GCREGFETCHCONTROL_COUNT_SHIFT) & GPU_GCREGFETCHCONTROL_COUNT_MASK) +#define GPU_GCREGFETCHCONTROL_COUNT_GET(x) (((uint32_t)(x) & GPU_GCREGFETCHCONTROL_COUNT_MASK) >> GPU_GCREGFETCHCONTROL_COUNT_SHIFT) + +/* Bitfield definition for register: GCREGCURRENTFETCHADDRESS */ +/* + * ADDRESS (R) + * + * address + */ +#define GPU_GCREGCURRENTFETCHADDRESS_ADDRESS_MASK (0xFFFFFFFFUL) +#define GPU_GCREGCURRENTFETCHADDRESS_ADDRESS_SHIFT (0U) +#define GPU_GCREGCURRENTFETCHADDRESS_ADDRESS_GET(x) (((uint32_t)(x) & GPU_GCREGCURRENTFETCHADDRESS_ADDRESS_MASK) >> GPU_GCREGCURRENTFETCHADDRESS_ADDRESS_SHIFT) + + + + +#endif /* HPM_GPU_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_gwc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_gwc_regs.h new file mode 100644 index 00000000000..b827b3e404a --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_gwc_regs.h @@ -0,0 +1,209 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_GWC_H +#define HPM_GWC_H + +typedef struct { + __RW uint32_t GLB_CTRL; /* 0x0: control reg */ + __RW uint32_t IRQ_MASK; /* 0x4: interrupt enable */ + __RW uint32_t IRQ_STS; /* 0x8: interrupt status */ + __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ + struct { + __RW uint32_t CFG0; /* 0x10: config reg 0 */ + __RW uint32_t CFG1; /* 0x14: config reg 1 */ + __RW uint32_t REFCRC; /* 0x18: reference CRC */ + __RW uint32_t CALCRC; /* 0x1C: calculated CRC */ + } CHANNEL[16]; +} GWC_Type; + + +/* Bitfield definition for register: GLB_CTRL */ +/* + * CLK_POL (RW) + * + * graphic clock polarity. + * set to invert input graphic clock + */ +#define GWC_GLB_CTRL_CLK_POL_MASK (0x80U) +#define GWC_GLB_CTRL_CLK_POL_SHIFT (7U) +#define GWC_GLB_CTRL_CLK_POL_SET(x) (((uint32_t)(x) << GWC_GLB_CTRL_CLK_POL_SHIFT) & GWC_GLB_CTRL_CLK_POL_MASK) +#define GWC_GLB_CTRL_CLK_POL_GET(x) (((uint32_t)(x) & GWC_GLB_CTRL_CLK_POL_MASK) >> GWC_GLB_CTRL_CLK_POL_SHIFT) + +/* + * GWC_EN (RW) + * + * graphic window check enable. + * set to enable the whole block + */ +#define GWC_GLB_CTRL_GWC_EN_MASK (0x1U) +#define GWC_GLB_CTRL_GWC_EN_SHIFT (0U) +#define GWC_GLB_CTRL_GWC_EN_SET(x) (((uint32_t)(x) << GWC_GLB_CTRL_GWC_EN_SHIFT) & GWC_GLB_CTRL_GWC_EN_MASK) +#define GWC_GLB_CTRL_GWC_EN_GET(x) (((uint32_t)(x) & GWC_GLB_CTRL_GWC_EN_MASK) >> GWC_GLB_CTRL_GWC_EN_SHIFT) + +/* Bitfield definition for register: IRQ_MASK */ +/* + * MASK_RREEZ (RW) + * + * freeze mask, set to disable changing ERR_MASK and FUNC_MASK. + * can only be cleared by system reset + */ +#define GWC_IRQ_MASK_MASK_RREEZ_MASK (0x8U) +#define GWC_IRQ_MASK_MASK_RREEZ_SHIFT (3U) +#define GWC_IRQ_MASK_MASK_RREEZ_SET(x) (((uint32_t)(x) << GWC_IRQ_MASK_MASK_RREEZ_SHIFT) & GWC_IRQ_MASK_MASK_RREEZ_MASK) +#define GWC_IRQ_MASK_MASK_RREEZ_GET(x) (((uint32_t)(x) & GWC_IRQ_MASK_MASK_RREEZ_MASK) >> GWC_IRQ_MASK_MASK_RREEZ_SHIFT) + +/* + * FUNC_MASK (RW) + * + * function interrupt mask + */ +#define GWC_IRQ_MASK_FUNC_MASK_MASK (0x2U) +#define GWC_IRQ_MASK_FUNC_MASK_SHIFT (1U) +#define GWC_IRQ_MASK_FUNC_MASK_SET(x) (((uint32_t)(x) << GWC_IRQ_MASK_FUNC_MASK_SHIFT) & GWC_IRQ_MASK_FUNC_MASK_MASK) +#define GWC_IRQ_MASK_FUNC_MASK_GET(x) (((uint32_t)(x) & GWC_IRQ_MASK_FUNC_MASK_MASK) >> GWC_IRQ_MASK_FUNC_MASK_SHIFT) + +/* + * ERR_MASK (RW) + * + * error interrupt mask + */ +#define GWC_IRQ_MASK_ERR_MASK_MASK (0x1U) +#define GWC_IRQ_MASK_ERR_MASK_SHIFT (0U) +#define GWC_IRQ_MASK_ERR_MASK_SET(x) (((uint32_t)(x) << GWC_IRQ_MASK_ERR_MASK_SHIFT) & GWC_IRQ_MASK_ERR_MASK_MASK) +#define GWC_IRQ_MASK_ERR_MASK_GET(x) (((uint32_t)(x) & GWC_IRQ_MASK_ERR_MASK_MASK) >> GWC_IRQ_MASK_ERR_MASK_SHIFT) + +/* Bitfield definition for register: IRQ_STS */ +/* + * FUNC_STS (W1C) + * + * function interrupt status. + * it's set when detect two VSYNC signals after the block is enabled(GWC_EN is set) + * software write 1 to clear. + */ +#define GWC_IRQ_STS_FUNC_STS_MASK (0x20000UL) +#define GWC_IRQ_STS_FUNC_STS_SHIFT (17U) +#define GWC_IRQ_STS_FUNC_STS_SET(x) (((uint32_t)(x) << GWC_IRQ_STS_FUNC_STS_SHIFT) & GWC_IRQ_STS_FUNC_STS_MASK) +#define GWC_IRQ_STS_FUNC_STS_GET(x) (((uint32_t)(x) & GWC_IRQ_STS_FUNC_STS_MASK) >> GWC_IRQ_STS_FUNC_STS_SHIFT) + +/* + * ERR_STS (RO) + * + * error status, it's OR of GWC_FAIL_STS[15:0] + */ +#define GWC_IRQ_STS_ERR_STS_MASK (0x10000UL) +#define GWC_IRQ_STS_ERR_STS_SHIFT (16U) +#define GWC_IRQ_STS_ERR_STS_GET(x) (((uint32_t)(x) & GWC_IRQ_STS_ERR_STS_MASK) >> GWC_IRQ_STS_ERR_STS_SHIFT) + +/* + * GWC_FAIL_STS (W1C) + * + * graphic window check fail interrupt status. + * will be set if the calculated CRC not equal reference CRC. + * one bit for each channel. + * software write 1 to clear. + */ +#define GWC_IRQ_STS_GWC_FAIL_STS_MASK (0xFFFFU) +#define GWC_IRQ_STS_GWC_FAIL_STS_SHIFT (0U) +#define GWC_IRQ_STS_GWC_FAIL_STS_SET(x) (((uint32_t)(x) << GWC_IRQ_STS_GWC_FAIL_STS_SHIFT) & GWC_IRQ_STS_GWC_FAIL_STS_MASK) +#define GWC_IRQ_STS_GWC_FAIL_STS_GET(x) (((uint32_t)(x) & GWC_IRQ_STS_GWC_FAIL_STS_MASK) >> GWC_IRQ_STS_GWC_FAIL_STS_SHIFT) + +/* Bitfield definition for register of struct array CHANNEL: CFG0 */ +/* + * ENABLE (RW) + * + * channel enable + */ +#define GWC_CHANNEL_CFG0_ENABLE_MASK (0x80000000UL) +#define GWC_CHANNEL_CFG0_ENABLE_SHIFT (31U) +#define GWC_CHANNEL_CFG0_ENABLE_SET(x) (((uint32_t)(x) << GWC_CHANNEL_CFG0_ENABLE_SHIFT) & GWC_CHANNEL_CFG0_ENABLE_MASK) +#define GWC_CHANNEL_CFG0_ENABLE_GET(x) (((uint32_t)(x) & GWC_CHANNEL_CFG0_ENABLE_MASK) >> GWC_CHANNEL_CFG0_ENABLE_SHIFT) + +/* + * FREEZE (RW) + * + * freeze config. set to freeze all other config registers for current channel. + * can only be cleared by system reset + */ +#define GWC_CHANNEL_CFG0_FREEZE_MASK (0x40000000UL) +#define GWC_CHANNEL_CFG0_FREEZE_SHIFT (30U) +#define GWC_CHANNEL_CFG0_FREEZE_SET(x) (((uint32_t)(x) << GWC_CHANNEL_CFG0_FREEZE_SHIFT) & GWC_CHANNEL_CFG0_FREEZE_MASK) +#define GWC_CHANNEL_CFG0_FREEZE_GET(x) (((uint32_t)(x) & GWC_CHANNEL_CFG0_FREEZE_MASK) >> GWC_CHANNEL_CFG0_FREEZE_SHIFT) + +/* + * START_ROW (RW) + * + * define the window start row number + */ +#define GWC_CHANNEL_CFG0_START_ROW_MASK (0xFFF0000UL) +#define GWC_CHANNEL_CFG0_START_ROW_SHIFT (16U) +#define GWC_CHANNEL_CFG0_START_ROW_SET(x) (((uint32_t)(x) << GWC_CHANNEL_CFG0_START_ROW_SHIFT) & GWC_CHANNEL_CFG0_START_ROW_MASK) +#define GWC_CHANNEL_CFG0_START_ROW_GET(x) (((uint32_t)(x) & GWC_CHANNEL_CFG0_START_ROW_MASK) >> GWC_CHANNEL_CFG0_START_ROW_SHIFT) + +/* + * START_COL (RW) + * + * define the window start column number + */ +#define GWC_CHANNEL_CFG0_START_COL_MASK (0x1FFFU) +#define GWC_CHANNEL_CFG0_START_COL_SHIFT (0U) +#define GWC_CHANNEL_CFG0_START_COL_SET(x) (((uint32_t)(x) << GWC_CHANNEL_CFG0_START_COL_SHIFT) & GWC_CHANNEL_CFG0_START_COL_MASK) +#define GWC_CHANNEL_CFG0_START_COL_GET(x) (((uint32_t)(x) & GWC_CHANNEL_CFG0_START_COL_MASK) >> GWC_CHANNEL_CFG0_START_COL_SHIFT) + +/* Bitfield definition for register of struct array CHANNEL: CFG1 */ +/* + * END_ROW (RW) + * + * define the window end row number + */ +#define GWC_CHANNEL_CFG1_END_ROW_MASK (0xFFF0000UL) +#define GWC_CHANNEL_CFG1_END_ROW_SHIFT (16U) +#define GWC_CHANNEL_CFG1_END_ROW_SET(x) (((uint32_t)(x) << GWC_CHANNEL_CFG1_END_ROW_SHIFT) & GWC_CHANNEL_CFG1_END_ROW_MASK) +#define GWC_CHANNEL_CFG1_END_ROW_GET(x) (((uint32_t)(x) & GWC_CHANNEL_CFG1_END_ROW_MASK) >> GWC_CHANNEL_CFG1_END_ROW_SHIFT) + +/* + * END_COL (RW) + * + * define the window end column number + */ +#define GWC_CHANNEL_CFG1_END_COL_MASK (0x1FFFU) +#define GWC_CHANNEL_CFG1_END_COL_SHIFT (0U) +#define GWC_CHANNEL_CFG1_END_COL_SET(x) (((uint32_t)(x) << GWC_CHANNEL_CFG1_END_COL_SHIFT) & GWC_CHANNEL_CFG1_END_COL_MASK) +#define GWC_CHANNEL_CFG1_END_COL_GET(x) (((uint32_t)(x) & GWC_CHANNEL_CFG1_END_COL_MASK) >> GWC_CHANNEL_CFG1_END_COL_SHIFT) + +/* Bitfield definition for register of struct array CHANNEL: REFCRC */ +/* + * REF_CRC (RW) + * + * reference CRC + * polynomial function: 0x104C11DB7 + */ +#define GWC_CHANNEL_REFCRC_REF_CRC_MASK (0xFFFFFFFFUL) +#define GWC_CHANNEL_REFCRC_REF_CRC_SHIFT (0U) +#define GWC_CHANNEL_REFCRC_REF_CRC_SET(x) (((uint32_t)(x) << GWC_CHANNEL_REFCRC_REF_CRC_SHIFT) & GWC_CHANNEL_REFCRC_REF_CRC_MASK) +#define GWC_CHANNEL_REFCRC_REF_CRC_GET(x) (((uint32_t)(x) & GWC_CHANNEL_REFCRC_REF_CRC_MASK) >> GWC_CHANNEL_REFCRC_REF_CRC_SHIFT) + +/* Bitfield definition for register of struct array CHANNEL: CALCRC */ +/* + * CAL_CRC (RW) + * + * calculated CRC for last frame + */ +#define GWC_CHANNEL_CALCRC_CAL_CRC_MASK (0xFFFFFFFFUL) +#define GWC_CHANNEL_CALCRC_CAL_CRC_SHIFT (0U) +#define GWC_CHANNEL_CALCRC_CAL_CRC_SET(x) (((uint32_t)(x) << GWC_CHANNEL_CALCRC_CAL_CRC_SHIFT) & GWC_CHANNEL_CALCRC_CAL_CRC_MASK) +#define GWC_CHANNEL_CALCRC_CAL_CRC_GET(x) (((uint32_t)(x) & GWC_CHANNEL_CALCRC_CAL_CRC_MASK) >> GWC_CHANNEL_CALCRC_CAL_CRC_SHIFT) + + + +/* CHANNEL register group index macro definition */ +#define GWC_CHANNEL_CH0 (0UL) +#define GWC_CHANNEL_CH15 (15UL) + + +#endif /* HPM_GWC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_i2s_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_i2s_regs.h index 51414306bc6..a1e7bd06e3d 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_i2s_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_i2s_regs.h @@ -588,4 +588,4 @@ typedef struct { #define I2S_TXDSLOT_DATA3 (3UL) -#endif /* HPM_I2S_H */ \ No newline at end of file +#endif /* HPM_I2S_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_lcb_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_lcb_regs.h new file mode 100644 index 00000000000..b9c7bfa196b --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_lcb_regs.h @@ -0,0 +1,325 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_LCB_H +#define HPM_LCB_H + +typedef struct { + __RW uint32_t CTRL; /* 0x0: control register */ + __R uint8_t RESERVED0[96]; /* 0x4 - 0x63: Reserved */ + __R uint32_t PHY_STAT; /* 0x64: LVDS RX PHY Status register */ + __RW uint32_t PHY_POW_CTRL[2]; /* 0x68 - 0x6C: LVDS0 PHY power control register */ + __RW uint32_t PHY_D_CTRL[4]; /* 0x70 - 0x7C: LVDS0 PHY Data Channel RX0 Setting */ + __RW uint32_t PHY_CK_CTRL[2]; /* 0x80 - 0x84: LVDS0 PHY CK Channel Setting */ + __RW uint32_t PHY_ADJ_CTRL[2]; /* 0x88 - 0x8C: LVDS0 PHY ADJ Setting */ + __RW uint32_t PHY_SU_CTRL[2]; /* 0x90 - 0x94: LVDS0 PHY SU CTRL */ +} LCB_Type; + + +/* Bitfield definition for register: CTRL */ +/* + * LVDS_RXCK_SEL (RW) + * + * just for LVDS Display mode and CAM LINK mode, clock selection: + * 1: LVDS1 RXCK + * 0: LVDS0 RXCK + */ +#define LCB_CTRL_LVDS_RXCK_SEL_MASK (0x100U) +#define LCB_CTRL_LVDS_RXCK_SEL_SHIFT (8U) +#define LCB_CTRL_LVDS_RXCK_SEL_SET(x) (((uint32_t)(x) << LCB_CTRL_LVDS_RXCK_SEL_SHIFT) & LCB_CTRL_LVDS_RXCK_SEL_MASK) +#define LCB_CTRL_LVDS_RXCK_SEL_GET(x) (((uint32_t)(x) & LCB_CTRL_LVDS_RXCK_SEL_MASK) >> LCB_CTRL_LVDS_RXCK_SEL_SHIFT) + +/* + * CAM_LINK_WIDTH (RW) + * + * just for CAM LINK mode, data width: + * 00: 24bit + * 01: 30bit + * 10: 36bit + * 11: reserved + */ +#define LCB_CTRL_CAM_LINK_WIDTH_MASK (0xC0U) +#define LCB_CTRL_CAM_LINK_WIDTH_SHIFT (6U) +#define LCB_CTRL_CAM_LINK_WIDTH_SET(x) (((uint32_t)(x) << LCB_CTRL_CAM_LINK_WIDTH_SHIFT) & LCB_CTRL_CAM_LINK_WIDTH_MASK) +#define LCB_CTRL_CAM_LINK_WIDTH_GET(x) (((uint32_t)(x) & LCB_CTRL_CAM_LINK_WIDTH_MASK) >> LCB_CTRL_CAM_LINK_WIDTH_SHIFT) + +/* + * BIT_MAPPING (RW) + * + * just for LVDS Display mode, data protocol: + * 1: JEIDA standard + * 0: SPWG standard + */ +#define LCB_CTRL_BIT_MAPPING_MASK (0x20U) +#define LCB_CTRL_BIT_MAPPING_SHIFT (5U) +#define LCB_CTRL_BIT_MAPPING_SET(x) (((uint32_t)(x) << LCB_CTRL_BIT_MAPPING_SHIFT) & LCB_CTRL_BIT_MAPPING_MASK) +#define LCB_CTRL_BIT_MAPPING_GET(x) (((uint32_t)(x) & LCB_CTRL_BIT_MAPPING_MASK) >> LCB_CTRL_BIT_MAPPING_SHIFT) + +/* + * DATA_WIDTH (RW) + * + * just for LVDS Display mode, data width: + * 1: 24bit + * 0: 18bit(3line) + */ +#define LCB_CTRL_DATA_WIDTH_MASK (0x10U) +#define LCB_CTRL_DATA_WIDTH_SHIFT (4U) +#define LCB_CTRL_DATA_WIDTH_SET(x) (((uint32_t)(x) << LCB_CTRL_DATA_WIDTH_SHIFT) & LCB_CTRL_DATA_WIDTH_MASK) +#define LCB_CTRL_DATA_WIDTH_GET(x) (((uint32_t)(x) & LCB_CTRL_DATA_WIDTH_MASK) >> LCB_CTRL_DATA_WIDTH_SHIFT) + +/* + * MODE (RW) + * + * mode selection： + * 00: lvds display(4 line), two LVDS RX PHY must be LVDS display mode + * 01: cam link(4 line), two LVDS RX PHY must be LVDS display mode + * 10: sync code(2 line), LVDS RX PHY must be LVDS cameral mode + * 11: sync code(1line), LVDS RX PHY must be LVDS cameral mode + */ +#define LCB_CTRL_MODE_MASK (0x3U) +#define LCB_CTRL_MODE_SHIFT (0U) +#define LCB_CTRL_MODE_SET(x) (((uint32_t)(x) << LCB_CTRL_MODE_SHIFT) & LCB_CTRL_MODE_MASK) +#define LCB_CTRL_MODE_GET(x) (((uint32_t)(x) & LCB_CTRL_MODE_MASK) >> LCB_CTRL_MODE_SHIFT) + +/* Bitfield definition for register: PHY_STAT */ +/* + * LVDS1_RX_PHY_DLL_LOCK (RO) + * + * LVDS1 RX PHY DLL Lock indication Signal, 1 means dll already locked + */ +#define LCB_PHY_STAT_LVDS1_RX_PHY_DLL_LOCK_MASK (0x2U) +#define LCB_PHY_STAT_LVDS1_RX_PHY_DLL_LOCK_SHIFT (1U) +#define LCB_PHY_STAT_LVDS1_RX_PHY_DLL_LOCK_GET(x) (((uint32_t)(x) & LCB_PHY_STAT_LVDS1_RX_PHY_DLL_LOCK_MASK) >> LCB_PHY_STAT_LVDS1_RX_PHY_DLL_LOCK_SHIFT) + +/* + * LVDS0_RX_PHY_DLL_LOCK (RO) + * + * LVDS0 RX PHY DLL Lock indication Signal, 1 means dll already locked + */ +#define LCB_PHY_STAT_LVDS0_RX_PHY_DLL_LOCK_MASK (0x1U) +#define LCB_PHY_STAT_LVDS0_RX_PHY_DLL_LOCK_SHIFT (0U) +#define LCB_PHY_STAT_LVDS0_RX_PHY_DLL_LOCK_GET(x) (((uint32_t)(x) & LCB_PHY_STAT_LVDS0_RX_PHY_DLL_LOCK_MASK) >> LCB_PHY_STAT_LVDS0_RX_PHY_DLL_LOCK_SHIFT) + +/* Bitfield definition for register array: PHY_POW_CTRL */ +/* + * IDDQ_EN (RW) + * + * Power down control signal of channel rxck/rx1/rx0 + * 0: Normal operation + * 1: Power down channel + */ +#define LCB_PHY_POW_CTRL_IDDQ_EN_MASK (0x8U) +#define LCB_PHY_POW_CTRL_IDDQ_EN_SHIFT (3U) +#define LCB_PHY_POW_CTRL_IDDQ_EN_SET(x) (((uint32_t)(x) << LCB_PHY_POW_CTRL_IDDQ_EN_SHIFT) & LCB_PHY_POW_CTRL_IDDQ_EN_MASK) +#define LCB_PHY_POW_CTRL_IDDQ_EN_GET(x) (((uint32_t)(x) & LCB_PHY_POW_CTRL_IDDQ_EN_MASK) >> LCB_PHY_POW_CTRL_IDDQ_EN_SHIFT) + +/* + * RXCK_PD (RW) + * + * Power down control signal of channel rxck + * 0: Normal operation + * 1: Power down channel + */ +#define LCB_PHY_POW_CTRL_RXCK_PD_MASK (0x4U) +#define LCB_PHY_POW_CTRL_RXCK_PD_SHIFT (2U) +#define LCB_PHY_POW_CTRL_RXCK_PD_SET(x) (((uint32_t)(x) << LCB_PHY_POW_CTRL_RXCK_PD_SHIFT) & LCB_PHY_POW_CTRL_RXCK_PD_MASK) +#define LCB_PHY_POW_CTRL_RXCK_PD_GET(x) (((uint32_t)(x) & LCB_PHY_POW_CTRL_RXCK_PD_MASK) >> LCB_PHY_POW_CTRL_RXCK_PD_SHIFT) + +/* + * RX1_PD (RW) + * + * Power down control signal of channel rx1 + * 0: Normal operation + * 1: Power down channel + */ +#define LCB_PHY_POW_CTRL_RX1_PD_MASK (0x2U) +#define LCB_PHY_POW_CTRL_RX1_PD_SHIFT (1U) +#define LCB_PHY_POW_CTRL_RX1_PD_SET(x) (((uint32_t)(x) << LCB_PHY_POW_CTRL_RX1_PD_SHIFT) & LCB_PHY_POW_CTRL_RX1_PD_MASK) +#define LCB_PHY_POW_CTRL_RX1_PD_GET(x) (((uint32_t)(x) & LCB_PHY_POW_CTRL_RX1_PD_MASK) >> LCB_PHY_POW_CTRL_RX1_PD_SHIFT) + +/* + * RX0_PD (RW) + * + * Power down control signal of channel rx0 + * 0: Normal operation + * 1: Power down channel + */ +#define LCB_PHY_POW_CTRL_RX0_PD_MASK (0x1U) +#define LCB_PHY_POW_CTRL_RX0_PD_SHIFT (0U) +#define LCB_PHY_POW_CTRL_RX0_PD_SET(x) (((uint32_t)(x) << LCB_PHY_POW_CTRL_RX0_PD_SHIFT) & LCB_PHY_POW_CTRL_RX0_PD_MASK) +#define LCB_PHY_POW_CTRL_RX0_PD_GET(x) (((uint32_t)(x) & LCB_PHY_POW_CTRL_RX0_PD_MASK) >> LCB_PHY_POW_CTRL_RX0_PD_SHIFT) + +/* Bitfield definition for register array: PHY_D_CTRL */ +/* + * RX_VCOM (RW) + * + * bit 1: Receiver hysteresis enable signal. 0: enable; 1: disable + * bit 0: Terminal impedance common mode selection control signal. 0: floating; 1: Ground + */ +#define LCB_PHY_D_CTRL_RX_VCOM_MASK (0x300000UL) +#define LCB_PHY_D_CTRL_RX_VCOM_SHIFT (20U) +#define LCB_PHY_D_CTRL_RX_VCOM_SET(x) (((uint32_t)(x) << LCB_PHY_D_CTRL_RX_VCOM_SHIFT) & LCB_PHY_D_CTRL_RX_VCOM_MASK) +#define LCB_PHY_D_CTRL_RX_VCOM_GET(x) (((uint32_t)(x) & LCB_PHY_D_CTRL_RX_VCOM_MASK) >> LCB_PHY_D_CTRL_RX_VCOM_SHIFT) + +/* + * RX_RTERM (RW) + * + * Terminal impedance regulation control signal + * 0000: hi-z; + * 0001: 150ohm; + * 1000:100ohm; + * 1111:75ohm + */ +#define LCB_PHY_D_CTRL_RX_RTERM_MASK (0xF0000UL) +#define LCB_PHY_D_CTRL_RX_RTERM_SHIFT (16U) +#define LCB_PHY_D_CTRL_RX_RTERM_SET(x) (((uint32_t)(x) << LCB_PHY_D_CTRL_RX_RTERM_SHIFT) & LCB_PHY_D_CTRL_RX_RTERM_MASK) +#define LCB_PHY_D_CTRL_RX_RTERM_GET(x) (((uint32_t)(x) & LCB_PHY_D_CTRL_RX_RTERM_MASK) >> LCB_PHY_D_CTRL_RX_RTERM_SHIFT) + +/* + * RX_CTL (RW) + * + * bit 0 : Lane N Data MSB first enable signal. 0: LSB ; 1: MSB + * bit 1 : Lane N Data Polarity signal. 0: Not inverting; 1: Inverting + * bit [4:2] : Phase difference between the output first bit data (rxN[6:0]) and the input clock (RCKP/N) in LVDS Display Mode. + * bit 5 : Reserved + * bit 6 : Output data sampling clock control signal + * 0: Sampling using the rising edge of the clock pck. + * 1: Sampling using the falling edge of the clock pck. + * bit 7 : Reserved + * bit 8 : Data Lane N Skew adjust enable in LVDS Camera Mode. + * bit [12:9] : Data Lane N Skew adjust; 0000: min; 0111: default; 1111: max. + * bit [15:13] : Reserved + */ +#define LCB_PHY_D_CTRL_RX_CTL_MASK (0xFFFFU) +#define LCB_PHY_D_CTRL_RX_CTL_SHIFT (0U) +#define LCB_PHY_D_CTRL_RX_CTL_SET(x) (((uint32_t)(x) << LCB_PHY_D_CTRL_RX_CTL_SHIFT) & LCB_PHY_D_CTRL_RX_CTL_MASK) +#define LCB_PHY_D_CTRL_RX_CTL_GET(x) (((uint32_t)(x) & LCB_PHY_D_CTRL_RX_CTL_MASK) >> LCB_PHY_D_CTRL_RX_CTL_SHIFT) + +/* Bitfield definition for register array: PHY_CK_CTRL */ +/* + * RX_VCOM (RW) + * + * bit 1: Receiver hysteresis enable signal. 0: enable; 1: disable + * bit 0: Terminal impedance common mode selection control signal. 0: floating; 1: Ground + */ +#define LCB_PHY_CK_CTRL_RX_VCOM_MASK (0x300000UL) +#define LCB_PHY_CK_CTRL_RX_VCOM_SHIFT (20U) +#define LCB_PHY_CK_CTRL_RX_VCOM_SET(x) (((uint32_t)(x) << LCB_PHY_CK_CTRL_RX_VCOM_SHIFT) & LCB_PHY_CK_CTRL_RX_VCOM_MASK) +#define LCB_PHY_CK_CTRL_RX_VCOM_GET(x) (((uint32_t)(x) & LCB_PHY_CK_CTRL_RX_VCOM_MASK) >> LCB_PHY_CK_CTRL_RX_VCOM_SHIFT) + +/* + * RX_RTERM (RW) + * + * Terminal impedance regulation control signal + * 0000: hi-z; + * 0001: 150ohm; + * 1000:100ohm; + * 1111:75ohm + */ +#define LCB_PHY_CK_CTRL_RX_RTERM_MASK (0xF0000UL) +#define LCB_PHY_CK_CTRL_RX_RTERM_SHIFT (16U) +#define LCB_PHY_CK_CTRL_RX_RTERM_SET(x) (((uint32_t)(x) << LCB_PHY_CK_CTRL_RX_RTERM_SHIFT) & LCB_PHY_CK_CTRL_RX_RTERM_MASK) +#define LCB_PHY_CK_CTRL_RX_RTERM_GET(x) (((uint32_t)(x) & LCB_PHY_CK_CTRL_RX_RTERM_MASK) >> LCB_PHY_CK_CTRL_RX_RTERM_SHIFT) + +/* + * RX_CTL (RW) + * + * bit 0 : DLL loop delay adjustment minimum control signal + * 0: used for RCKP/RCKN’s frequency is 40Mhz~70Mhz + * 1:used for RCKP/RCKN’s frequency is 70Mhz~110Mhz + * bit [2:1] : DLL loop delay adjustment current regulation control signal. 00: min; 11: max + * bit 3 : Reserved + * bit 4 : Clock Lane Skew adjust enable in LVDS Camera Mode. + * bit [7:5] : Bus width selection in LVDS Camera Mode + * 000: 4bit; 001:6bit; 010:7bit; 011:8bit; 100:9bit; 101:10bit; 110:11bit; 111:12bit. + * bit [10:8] : DDR Clock duty cycle adjust in LVDS Camera Mode. + * bit [15:11] : Reserved + */ +#define LCB_PHY_CK_CTRL_RX_CTL_MASK (0xFFFFU) +#define LCB_PHY_CK_CTRL_RX_CTL_SHIFT (0U) +#define LCB_PHY_CK_CTRL_RX_CTL_SET(x) (((uint32_t)(x) << LCB_PHY_CK_CTRL_RX_CTL_SHIFT) & LCB_PHY_CK_CTRL_RX_CTL_MASK) +#define LCB_PHY_CK_CTRL_RX_CTL_GET(x) (((uint32_t)(x) & LCB_PHY_CK_CTRL_RX_CTL_MASK) >> LCB_PHY_CK_CTRL_RX_CTL_SHIFT) + +/* Bitfield definition for register array: PHY_ADJ_CTRL */ +/* + * LVDS_RX0_DLINE_ADJ (RW) + * + * LVDS RX PHY RX0 line: + * bit [7:0] : Lane N skew adjustment control signal between data and clock + * 0000000: max; 1111111: min + * bit 8 : Reserved + */ +#define LCB_PHY_ADJ_CTRL_LVDS_RX0_DLINE_ADJ_MASK (0xFF000000UL) +#define LCB_PHY_ADJ_CTRL_LVDS_RX0_DLINE_ADJ_SHIFT (24U) +#define LCB_PHY_ADJ_CTRL_LVDS_RX0_DLINE_ADJ_SET(x) (((uint32_t)(x) << LCB_PHY_ADJ_CTRL_LVDS_RX0_DLINE_ADJ_SHIFT) & LCB_PHY_ADJ_CTRL_LVDS_RX0_DLINE_ADJ_MASK) +#define LCB_PHY_ADJ_CTRL_LVDS_RX0_DLINE_ADJ_GET(x) (((uint32_t)(x) & LCB_PHY_ADJ_CTRL_LVDS_RX0_DLINE_ADJ_MASK) >> LCB_PHY_ADJ_CTRL_LVDS_RX0_DLINE_ADJ_SHIFT) + +/* + * LVDS_RX1_DLINE_ADJ (RW) + * + * LVDS RX PHY RX1 line: + * bit [7:0] : Lane N skew adjustment control signal between data and clock + * 0000000: max; 1111111: min + * bit 8 : Reserved + */ +#define LCB_PHY_ADJ_CTRL_LVDS_RX1_DLINE_ADJ_MASK (0xFF0000UL) +#define LCB_PHY_ADJ_CTRL_LVDS_RX1_DLINE_ADJ_SHIFT (16U) +#define LCB_PHY_ADJ_CTRL_LVDS_RX1_DLINE_ADJ_SET(x) (((uint32_t)(x) << LCB_PHY_ADJ_CTRL_LVDS_RX1_DLINE_ADJ_SHIFT) & LCB_PHY_ADJ_CTRL_LVDS_RX1_DLINE_ADJ_MASK) +#define LCB_PHY_ADJ_CTRL_LVDS_RX1_DLINE_ADJ_GET(x) (((uint32_t)(x) & LCB_PHY_ADJ_CTRL_LVDS_RX1_DLINE_ADJ_MASK) >> LCB_PHY_ADJ_CTRL_LVDS_RX1_DLINE_ADJ_SHIFT) + +/* + * LVDS_DLL_TUNING_INT (RW) + * + * LVDS RX PHY RXCK line: + * DLL loop delay coarse adjustment initial signal + * 00000000: min ; 11111111: max + */ +#define LCB_PHY_ADJ_CTRL_LVDS_DLL_TUNING_INT_MASK (0x1FFU) +#define LCB_PHY_ADJ_CTRL_LVDS_DLL_TUNING_INT_SHIFT (0U) +#define LCB_PHY_ADJ_CTRL_LVDS_DLL_TUNING_INT_SET(x) (((uint32_t)(x) << LCB_PHY_ADJ_CTRL_LVDS_DLL_TUNING_INT_SHIFT) & LCB_PHY_ADJ_CTRL_LVDS_DLL_TUNING_INT_MASK) +#define LCB_PHY_ADJ_CTRL_LVDS_DLL_TUNING_INT_GET(x) (((uint32_t)(x) & LCB_PHY_ADJ_CTRL_LVDS_DLL_TUNING_INT_MASK) >> LCB_PHY_ADJ_CTRL_LVDS_DLL_TUNING_INT_SHIFT) + +/* Bitfield definition for register array: PHY_SU_CTRL */ +/* + * SU_CTRL (RW) + * + * bit [2:0] : Reference voltage/current adjustment control signal. 000: min; 111: max + * bit [3] : Internal bias circuit selection signal. 0: from Bandgap Mode; 1: from self-bias mode + * bit [7:4] : Reserved + */ +#define LCB_PHY_SU_CTRL_SU_CTRL_MASK (0xFFU) +#define LCB_PHY_SU_CTRL_SU_CTRL_SHIFT (0U) +#define LCB_PHY_SU_CTRL_SU_CTRL_SET(x) (((uint32_t)(x) << LCB_PHY_SU_CTRL_SU_CTRL_SHIFT) & LCB_PHY_SU_CTRL_SU_CTRL_MASK) +#define LCB_PHY_SU_CTRL_SU_CTRL_GET(x) (((uint32_t)(x) & LCB_PHY_SU_CTRL_SU_CTRL_MASK) >> LCB_PHY_SU_CTRL_SU_CTRL_SHIFT) + + + +/* PHY_POW_CTRL register group index macro definition */ +#define LCB_PHY_POW_CTRL_LVDS0 (0UL) +#define LCB_PHY_POW_CTRL_LVDS1 (1UL) + +/* PHY_D_CTRL register group index macro definition */ +#define LCB_PHY_D_CTRL_LVDS0_RX0 (0UL) +#define LCB_PHY_D_CTRL_LVDS0_RX1 (1UL) +#define LCB_PHY_D_CTRL_LVDS1_RX0 (2UL) +#define LCB_PHY_D_CTRL_LVDS1_RX1 (3UL) + +/* PHY_CK_CTRL register group index macro definition */ +#define LCB_PHY_CK_CTRL_LVDS0_RXCK (0UL) +#define LCB_PHY_CK_CTRL_LVDS1_RXCK (1UL) + +/* PHY_ADJ_CTRL register group index macro definition */ +#define LCB_PHY_ADJ_CTRL_LVDS0 (0UL) +#define LCB_PHY_ADJ_CTRL_LVDS1 (1UL) + +/* PHY_SU_CTRL register group index macro definition */ +#define LCB_PHY_SU_CTRL_LVDS0 (0UL) +#define LCB_PHY_SU_CTRL_LVDS1 (1UL) + + +#endif /* HPM_LCB_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_lcdc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_lcdc_regs.h index f1bc84ab104..23ae5e199a5 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_lcdc_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_lcdc_regs.h @@ -888,7 +888,7 @@ typedef struct { * 0001b - 2 bpp (pixel width must be multiples of 16), pixel sequence is from LSB to MSB in 32b word. * 0010b - 4 bpp (pixel width must be multiples of 8), pixel sequence is from LSB to MSB in 32b word. * 0011b - 8 bpp (pixel width must be multiples of 4), pixel sequence is from LSB to MSB in 32b word. - * 0100b - 16 bpp (RGB565), byte sequence as B,R + * 0100b - 16 bpp (RGB565), the low byte contains teh full R component. * 0111b - YCbCr422 (Only layer 0/1 can support this format), byte sequence determined by LAYCTRL[YUV_FORMAT] * 1001b - 32 bpp (ARGB8888), byte sequence as B,G,R,A * 1011b - Y8 (pixel width must be multiples of 4), byte sequence as Y1,Y2,Y3,Y4 diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_linv2_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_linv2_regs.h new file mode 100644 index 00000000000..d8f94b68b55 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_linv2_regs.h @@ -0,0 +1,466 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_LINV2_H +#define HPM_LINV2_H + +typedef struct { + union { + __RW uint32_t DATA[2]; /* 0x0 - 0x4: data byte */ + __RW uint8_t DATA_BYTE[8]; /* 0x0 - 0x7: */ + }; + __RW uint32_t DATA_LEN_ID; /* 0x8: data length and ID register */ + __RW uint32_t CONTROL_STATUS; /* 0xC: control and status register */ + __RW uint32_t TIMING_CONTROL; /* 0x10: timing control register */ + __RW uint32_t DMA_CONTROL; /* 0x14: dma control register */ +} LINV2_Type; + + +/* Bitfield definition for register: DATA0 */ +/* + * DATA (RW) + * + * data + */ +#define LINV2_DATA_DATA_MASK (0xFFFFFFFFUL) +#define LINV2_DATA_DATA_SHIFT (0U) +#define LINV2_DATA_DATA_SET(x) (((uint32_t)(x) << LINV2_DATA_DATA_SHIFT) & LINV2_DATA_DATA_MASK) +#define LINV2_DATA_DATA_GET(x) (((uint32_t)(x) & LINV2_DATA_DATA_MASK) >> LINV2_DATA_DATA_SHIFT) + +/* Bitfield definition for register: DATA_BYTE0 */ +/* + * DATA_BYTE (RW) + * + * data byte + */ +#define LINV2_DATA_BYTE_DATA_BYTE_MASK (0xFFU) +#define LINV2_DATA_BYTE_DATA_BYTE_SHIFT (0U) +#define LINV2_DATA_BYTE_DATA_BYTE_SET(x) (((uint8_t)(x) << LINV2_DATA_BYTE_DATA_BYTE_SHIFT) & LINV2_DATA_BYTE_DATA_BYTE_MASK) +#define LINV2_DATA_BYTE_DATA_BYTE_GET(x) (((uint8_t)(x) & LINV2_DATA_BYTE_DATA_BYTE_MASK) >> LINV2_DATA_BYTE_DATA_BYTE_SHIFT) + +/* Bitfield definition for register: DATA_LEN_ID */ +/* + * CHECKSUM (RO) + * + */ +#define LINV2_DATA_LEN_ID_CHECKSUM_MASK (0xFF0000UL) +#define LINV2_DATA_LEN_ID_CHECKSUM_SHIFT (16U) +#define LINV2_DATA_LEN_ID_CHECKSUM_GET(x) (((uint32_t)(x) & LINV2_DATA_LEN_ID_CHECKSUM_MASK) >> LINV2_DATA_LEN_ID_CHECKSUM_SHIFT) + +/* + * ID_PARITY (RO) + * + */ +#define LINV2_DATA_LEN_ID_ID_PARITY_MASK (0xC000U) +#define LINV2_DATA_LEN_ID_ID_PARITY_SHIFT (14U) +#define LINV2_DATA_LEN_ID_ID_PARITY_GET(x) (((uint32_t)(x) & LINV2_DATA_LEN_ID_ID_PARITY_MASK) >> LINV2_DATA_LEN_ID_ID_PARITY_SHIFT) + +/* + * ID (RW) + * + * ID register + */ +#define LINV2_DATA_LEN_ID_ID_MASK (0x3F00U) +#define LINV2_DATA_LEN_ID_ID_SHIFT (8U) +#define LINV2_DATA_LEN_ID_ID_SET(x) (((uint32_t)(x) << LINV2_DATA_LEN_ID_ID_SHIFT) & LINV2_DATA_LEN_ID_ID_MASK) +#define LINV2_DATA_LEN_ID_ID_GET(x) (((uint32_t)(x) & LINV2_DATA_LEN_ID_ID_MASK) >> LINV2_DATA_LEN_ID_ID_SHIFT) + +/* + * ENH_CHECK (RW) + * + * 1:enhance check mode 0:classical check mode + */ +#define LINV2_DATA_LEN_ID_ENH_CHECK_MASK (0x80U) +#define LINV2_DATA_LEN_ID_ENH_CHECK_SHIFT (7U) +#define LINV2_DATA_LEN_ID_ENH_CHECK_SET(x) (((uint32_t)(x) << LINV2_DATA_LEN_ID_ENH_CHECK_SHIFT) & LINV2_DATA_LEN_ID_ENH_CHECK_MASK) +#define LINV2_DATA_LEN_ID_ENH_CHECK_GET(x) (((uint32_t)(x) & LINV2_DATA_LEN_ID_ENH_CHECK_MASK) >> LINV2_DATA_LEN_ID_ENH_CHECK_SHIFT) + +/* + * DATA_LEN (RW) + * + * payload data length control register。The data length will decoded from ID[5:4] when all 1 is configured: 00-2 01-2 10-4 11-8 + */ +#define LINV2_DATA_LEN_ID_DATA_LEN_MASK (0xFU) +#define LINV2_DATA_LEN_ID_DATA_LEN_SHIFT (0U) +#define LINV2_DATA_LEN_ID_DATA_LEN_SET(x) (((uint32_t)(x) << LINV2_DATA_LEN_ID_DATA_LEN_SHIFT) & LINV2_DATA_LEN_ID_DATA_LEN_MASK) +#define LINV2_DATA_LEN_ID_DATA_LEN_GET(x) (((uint32_t)(x) & LINV2_DATA_LEN_ID_DATA_LEN_MASK) >> LINV2_DATA_LEN_ID_DATA_LEN_SHIFT) + +/* Bitfield definition for register: CONTROL_STATUS */ +/* + * BREAK_ERR_DIS (RW) + * + */ +#define LINV2_CONTROL_STATUS_BREAK_ERR_DIS_MASK (0x200000UL) +#define LINV2_CONTROL_STATUS_BREAK_ERR_DIS_SHIFT (21U) +#define LINV2_CONTROL_STATUS_BREAK_ERR_DIS_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_BREAK_ERR_DIS_SHIFT) & LINV2_CONTROL_STATUS_BREAK_ERR_DIS_MASK) +#define LINV2_CONTROL_STATUS_BREAK_ERR_DIS_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_BREAK_ERR_DIS_MASK) >> LINV2_CONTROL_STATUS_BREAK_ERR_DIS_SHIFT) + +/* + * BREAK_ERR (RO) + * + */ +#define LINV2_CONTROL_STATUS_BREAK_ERR_MASK (0x100000UL) +#define LINV2_CONTROL_STATUS_BREAK_ERR_SHIFT (20U) +#define LINV2_CONTROL_STATUS_BREAK_ERR_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_BREAK_ERR_MASK) >> LINV2_CONTROL_STATUS_BREAK_ERR_SHIFT) + +/* + * PARITY_ERROR (RO) + * + * slave only. identifier parity error + */ +#define LINV2_CONTROL_STATUS_PARITY_ERROR_MASK (0x80000UL) +#define LINV2_CONTROL_STATUS_PARITY_ERROR_SHIFT (19U) +#define LINV2_CONTROL_STATUS_PARITY_ERROR_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_PARITY_ERROR_MASK) >> LINV2_CONTROL_STATUS_PARITY_ERROR_SHIFT) + +/* + * TIME_OUT (RO) + * + * timeout error. The master detects a timeout error if it is expecting data from the bus but no slave does respond. The slave detects a timeout error if it is requesting a data acknowledge to the host controller. The slave detects a timeout if it has transmitted a wakeup signal and it detects no sync field within 150ms + */ +#define LINV2_CONTROL_STATUS_TIME_OUT_MASK (0x40000UL) +#define LINV2_CONTROL_STATUS_TIME_OUT_SHIFT (18U) +#define LINV2_CONTROL_STATUS_TIME_OUT_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_TIME_OUT_MASK) >> LINV2_CONTROL_STATUS_TIME_OUT_SHIFT) + +/* + * CHK_ERROR (RO) + * + * checksum error + */ +#define LINV2_CONTROL_STATUS_CHK_ERROR_MASK (0x20000UL) +#define LINV2_CONTROL_STATUS_CHK_ERROR_SHIFT (17U) +#define LINV2_CONTROL_STATUS_CHK_ERROR_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_CHK_ERROR_MASK) >> LINV2_CONTROL_STATUS_CHK_ERROR_SHIFT) + +/* + * BIT_ERROR (RO) + * + * bit error + */ +#define LINV2_CONTROL_STATUS_BIT_ERROR_MASK (0x10000UL) +#define LINV2_CONTROL_STATUS_BIT_ERROR_SHIFT (16U) +#define LINV2_CONTROL_STATUS_BIT_ERROR_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_BIT_ERROR_MASK) >> LINV2_CONTROL_STATUS_BIT_ERROR_SHIFT) + +/* + * LIN_ACTIVE (RO) + * + * The bit indicates whether the LIN bus is active or not + */ +#define LINV2_CONTROL_STATUS_LIN_ACTIVE_MASK (0x8000U) +#define LINV2_CONTROL_STATUS_LIN_ACTIVE_SHIFT (15U) +#define LINV2_CONTROL_STATUS_LIN_ACTIVE_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_LIN_ACTIVE_MASK) >> LINV2_CONTROL_STATUS_LIN_ACTIVE_SHIFT) + +/* + * BUS_IDLE_TIMEOUT (RO) + * + * slave only. This bit is set by LIN core if bit sleep is not set and no bus activity is detected for 4s + */ +#define LINV2_CONTROL_STATUS_BUS_IDLE_TIMEOUT_MASK (0x4000U) +#define LINV2_CONTROL_STATUS_BUS_IDLE_TIMEOUT_SHIFT (14U) +#define LINV2_CONTROL_STATUS_BUS_IDLE_TIMEOUT_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_BUS_IDLE_TIMEOUT_MASK) >> LINV2_CONTROL_STATUS_BUS_IDLE_TIMEOUT_SHIFT) + +/* + * ABORTED (RO) + * + * slave only. This bit is set by LIN core slave if a transmission is aborted after the bneginning of the data field due to a timeout or bit error. + */ +#define LINV2_CONTROL_STATUS_ABORTED_MASK (0x2000U) +#define LINV2_CONTROL_STATUS_ABORTED_SHIFT (13U) +#define LINV2_CONTROL_STATUS_ABORTED_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_ABORTED_MASK) >> LINV2_CONTROL_STATUS_ABORTED_SHIFT) + +/* + * DATA_REQ (RO) + * + * slave only. Sets after receiving the identifier and requests an interrupt to the host controller. + */ +#define LINV2_CONTROL_STATUS_DATA_REQ_MASK (0x1000U) +#define LINV2_CONTROL_STATUS_DATA_REQ_SHIFT (12U) +#define LINV2_CONTROL_STATUS_DATA_REQ_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_DATA_REQ_MASK) >> LINV2_CONTROL_STATUS_DATA_REQ_SHIFT) + +/* + * INT (RO) + * + * set when request an interrupt. Reset by reset_int + */ +#define LINV2_CONTROL_STATUS_INT_MASK (0x800U) +#define LINV2_CONTROL_STATUS_INT_SHIFT (11U) +#define LINV2_CONTROL_STATUS_INT_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_INT_MASK) >> LINV2_CONTROL_STATUS_INT_SHIFT) + +/* + * ERROR (RO) + * + * set when detecte an error, clear by reset_error + */ +#define LINV2_CONTROL_STATUS_ERROR_MASK (0x400U) +#define LINV2_CONTROL_STATUS_ERROR_SHIFT (10U) +#define LINV2_CONTROL_STATUS_ERROR_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_ERROR_MASK) >> LINV2_CONTROL_STATUS_ERROR_SHIFT) + +/* + * WAKEUP (RO) + * + * set when transmitting a wakeup signal or when received a wakeup signal. Clear when reset_error bit is 1 + */ +#define LINV2_CONTROL_STATUS_WAKEUP_MASK (0x200U) +#define LINV2_CONTROL_STATUS_WAKEUP_SHIFT (9U) +#define LINV2_CONTROL_STATUS_WAKEUP_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_WAKEUP_MASK) >> LINV2_CONTROL_STATUS_WAKEUP_SHIFT) + +/* + * COMPLETE (RO) + * + * set after a transmission has been successful finished and it will reset at the start of a transmission. + */ +#define LINV2_CONTROL_STATUS_COMPLETE_MASK (0x100U) +#define LINV2_CONTROL_STATUS_COMPLETE_SHIFT (8U) +#define LINV2_CONTROL_STATUS_COMPLETE_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_COMPLETE_MASK) >> LINV2_CONTROL_STATUS_COMPLETE_SHIFT) + +/* + * STOP (WO) + * + * slave only. Write 1 when the Host determin do not response to the data request according to a unkown ID + */ +#define LINV2_CONTROL_STATUS_STOP_MASK (0x80U) +#define LINV2_CONTROL_STATUS_STOP_SHIFT (7U) +#define LINV2_CONTROL_STATUS_STOP_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_STOP_SHIFT) & LINV2_CONTROL_STATUS_STOP_MASK) +#define LINV2_CONTROL_STATUS_STOP_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_STOP_MASK) >> LINV2_CONTROL_STATUS_STOP_SHIFT) + +/* + * SLEEP (RW) + * + * The bit is used by the LIN core to determine whether the LIN bus is in sleep mode or not. Set this bit after sending or receiving a Sleep Mode frame or if a bus idle timeout interrupt is requested or if after a wakeup request there is no response from the master and a timeout is signaled. The bit will be automatically reset by the LIN core. + */ +#define LINV2_CONTROL_STATUS_SLEEP_MASK (0x40U) +#define LINV2_CONTROL_STATUS_SLEEP_SHIFT (6U) +#define LINV2_CONTROL_STATUS_SLEEP_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_SLEEP_SHIFT) & LINV2_CONTROL_STATUS_SLEEP_MASK) +#define LINV2_CONTROL_STATUS_SLEEP_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_SLEEP_MASK) >> LINV2_CONTROL_STATUS_SLEEP_SHIFT) + +/* + * TRANSMIT (RW) + * + * 1: transmit operation 0: receive operation + */ +#define LINV2_CONTROL_STATUS_TRANSMIT_MASK (0x20U) +#define LINV2_CONTROL_STATUS_TRANSMIT_SHIFT (5U) +#define LINV2_CONTROL_STATUS_TRANSMIT_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_TRANSMIT_SHIFT) & LINV2_CONTROL_STATUS_TRANSMIT_MASK) +#define LINV2_CONTROL_STATUS_TRANSMIT_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_TRANSMIT_MASK) >> LINV2_CONTROL_STATUS_TRANSMIT_SHIFT) + +/* + * DATA_ACK (RW) + * + * slave only. Write 1 after handling a data request interrupt + */ +#define LINV2_CONTROL_STATUS_DATA_ACK_MASK (0x10U) +#define LINV2_CONTROL_STATUS_DATA_ACK_SHIFT (4U) +#define LINV2_CONTROL_STATUS_DATA_ACK_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_DATA_ACK_SHIFT) & LINV2_CONTROL_STATUS_DATA_ACK_MASK) +#define LINV2_CONTROL_STATUS_DATA_ACK_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_DATA_ACK_MASK) >> LINV2_CONTROL_STATUS_DATA_ACK_SHIFT) + +/* + * RESET_INT (WO) + * + * set 1 will clear the int register + */ +#define LINV2_CONTROL_STATUS_RESET_INT_MASK (0x8U) +#define LINV2_CONTROL_STATUS_RESET_INT_SHIFT (3U) +#define LINV2_CONTROL_STATUS_RESET_INT_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_RESET_INT_SHIFT) & LINV2_CONTROL_STATUS_RESET_INT_MASK) +#define LINV2_CONTROL_STATUS_RESET_INT_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_RESET_INT_MASK) >> LINV2_CONTROL_STATUS_RESET_INT_SHIFT) + +/* + * RESET_ERROR (WO) + * + * set 1 will clear the error register, and also the timeout/complete/wakeup register + */ +#define LINV2_CONTROL_STATUS_RESET_ERROR_MASK (0x4U) +#define LINV2_CONTROL_STATUS_RESET_ERROR_SHIFT (2U) +#define LINV2_CONTROL_STATUS_RESET_ERROR_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_RESET_ERROR_SHIFT) & LINV2_CONTROL_STATUS_RESET_ERROR_MASK) +#define LINV2_CONTROL_STATUS_RESET_ERROR_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_RESET_ERROR_MASK) >> LINV2_CONTROL_STATUS_RESET_ERROR_SHIFT) + +/* + * WAKEUP_REQ (RW) + * + * set 1 will make LIN bus exit sleep mode, the bit auto cleared after a wakeup signal has been complete + */ +#define LINV2_CONTROL_STATUS_WAKEUP_REQ_MASK (0x2U) +#define LINV2_CONTROL_STATUS_WAKEUP_REQ_SHIFT (1U) +#define LINV2_CONTROL_STATUS_WAKEUP_REQ_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_WAKEUP_REQ_SHIFT) & LINV2_CONTROL_STATUS_WAKEUP_REQ_MASK) +#define LINV2_CONTROL_STATUS_WAKEUP_REQ_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_WAKEUP_REQ_MASK) >> LINV2_CONTROL_STATUS_WAKEUP_REQ_SHIFT) + +/* + * START_REQ (RW) + * + * master only. Set 1 will start lin transmission, the bit will be auto cleared when an error occur or the trasmission complete + */ +#define LINV2_CONTROL_STATUS_START_REQ_MASK (0x1U) +#define LINV2_CONTROL_STATUS_START_REQ_SHIFT (0U) +#define LINV2_CONTROL_STATUS_START_REQ_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_START_REQ_SHIFT) & LINV2_CONTROL_STATUS_START_REQ_MASK) +#define LINV2_CONTROL_STATUS_START_REQ_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_START_REQ_MASK) >> LINV2_CONTROL_STATUS_START_REQ_SHIFT) + +/* Bitfield definition for register: TIMING_CONTROL */ +/* + * WAKE_LEN (RW) + * + */ +#define LINV2_TIMING_CONTROL_WAKE_LEN_MASK (0x38000000UL) +#define LINV2_TIMING_CONTROL_WAKE_LEN_SHIFT (27U) +#define LINV2_TIMING_CONTROL_WAKE_LEN_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_WAKE_LEN_SHIFT) & LINV2_TIMING_CONTROL_WAKE_LEN_MASK) +#define LINV2_TIMING_CONTROL_WAKE_LEN_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_WAKE_LEN_MASK) >> LINV2_TIMING_CONTROL_WAKE_LEN_SHIFT) + +/* + * BRK_LEN (RW) + * + */ +#define LINV2_TIMING_CONTROL_BRK_LEN_MASK (0x7000000UL) +#define LINV2_TIMING_CONTROL_BRK_LEN_SHIFT (24U) +#define LINV2_TIMING_CONTROL_BRK_LEN_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_BRK_LEN_SHIFT) & LINV2_TIMING_CONTROL_BRK_LEN_MASK) +#define LINV2_TIMING_CONTROL_BRK_LEN_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_BRK_LEN_MASK) >> LINV2_TIMING_CONTROL_BRK_LEN_SHIFT) + +/* + * LINBUSDISABLE (RW) + * + * 1：lin rx is disable + */ +#define LINV2_TIMING_CONTROL_LINBUSDISABLE_MASK (0x400000UL) +#define LINV2_TIMING_CONTROL_LINBUSDISABLE_SHIFT (22U) +#define LINV2_TIMING_CONTROL_LINBUSDISABLE_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_LINBUSDISABLE_SHIFT) & LINV2_TIMING_CONTROL_LINBUSDISABLE_MASK) +#define LINV2_TIMING_CONTROL_LINBUSDISABLE_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_LINBUSDISABLE_MASK) >> LINV2_TIMING_CONTROL_LINBUSDISABLE_SHIFT) + +/* + * LIN_INITIAL (RW) + * + * 1:initial lin controller + */ +#define LINV2_TIMING_CONTROL_LIN_INITIAL_MASK (0x200000UL) +#define LINV2_TIMING_CONTROL_LIN_INITIAL_SHIFT (21U) +#define LINV2_TIMING_CONTROL_LIN_INITIAL_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_LIN_INITIAL_SHIFT) & LINV2_TIMING_CONTROL_LIN_INITIAL_MASK) +#define LINV2_TIMING_CONTROL_LIN_INITIAL_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_LIN_INITIAL_MASK) >> LINV2_TIMING_CONTROL_LIN_INITIAL_SHIFT) + +/* + * MASTER_MODE (RW) + * + * 1：master mode + */ +#define LINV2_TIMING_CONTROL_MASTER_MODE_MASK (0x100000UL) +#define LINV2_TIMING_CONTROL_MASTER_MODE_SHIFT (20U) +#define LINV2_TIMING_CONTROL_MASTER_MODE_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_MASTER_MODE_SHIFT) & LINV2_TIMING_CONTROL_MASTER_MODE_MASK) +#define LINV2_TIMING_CONTROL_MASTER_MODE_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_MASTER_MODE_MASK) >> LINV2_TIMING_CONTROL_MASTER_MODE_SHIFT) + +/* + * BUS_INACTIVE_TIME (RW) + * + * slave only. LIN bus idle timeout register： 00-4s 01-6s 10-8s 11-10s + */ +#define LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_MASK (0xC0000UL) +#define LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_SHIFT (18U) +#define LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_SHIFT) & LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_MASK) +#define LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_MASK) >> LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_SHIFT) + +/* + * WUP_REPEAT_TIME (RW) + * + * slave only. wakeup repeat interval time 00-180ms 01-200ms 10-220ms 11-240ms + */ +#define LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_MASK (0x30000UL) +#define LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_SHIFT (16U) +#define LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_SHIFT) & LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_MASK) +#define LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_MASK) >> LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_SHIFT) + +/* + * PRESCL (RW) + * + * prescl register + */ +#define LINV2_TIMING_CONTROL_PRESCL_MASK (0xC000U) +#define LINV2_TIMING_CONTROL_PRESCL_SHIFT (14U) +#define LINV2_TIMING_CONTROL_PRESCL_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_PRESCL_SHIFT) & LINV2_TIMING_CONTROL_PRESCL_MASK) +#define LINV2_TIMING_CONTROL_PRESCL_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_PRESCL_MASK) >> LINV2_TIMING_CONTROL_PRESCL_SHIFT) + +/* + * BT_MUL (RW) + * + * bt_mul register + */ +#define LINV2_TIMING_CONTROL_BT_MUL_MASK (0x3E00U) +#define LINV2_TIMING_CONTROL_BT_MUL_SHIFT (9U) +#define LINV2_TIMING_CONTROL_BT_MUL_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_BT_MUL_SHIFT) & LINV2_TIMING_CONTROL_BT_MUL_MASK) +#define LINV2_TIMING_CONTROL_BT_MUL_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_BT_MUL_MASK) >> LINV2_TIMING_CONTROL_BT_MUL_SHIFT) + +/* + * BT_DIV (RW) + * + * bt_div register + */ +#define LINV2_TIMING_CONTROL_BT_DIV_MASK (0x1FFU) +#define LINV2_TIMING_CONTROL_BT_DIV_SHIFT (0U) +#define LINV2_TIMING_CONTROL_BT_DIV_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_BT_DIV_SHIFT) & LINV2_TIMING_CONTROL_BT_DIV_MASK) +#define LINV2_TIMING_CONTROL_BT_DIV_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_BT_DIV_MASK) >> LINV2_TIMING_CONTROL_BT_DIV_SHIFT) + +/* Bitfield definition for register: DMA_CONTROL */ +/* + * DMA_REQ_ENH_CHK (RW) + * + * payload data checksum type for dma operation + */ +#define LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_MASK (0x1000U) +#define LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_SHIFT (12U) +#define LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_SET(x) (((uint32_t)(x) << LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_SHIFT) & LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_MASK) +#define LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_GET(x) (((uint32_t)(x) & LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_MASK) >> LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_SHIFT) + +/* + * DMA_REQ_LEN (RW) + * + * paylaod length for dma request + */ +#define LINV2_DMA_CONTROL_DMA_REQ_LEN_MASK (0xF00U) +#define LINV2_DMA_CONTROL_DMA_REQ_LEN_SHIFT (8U) +#define LINV2_DMA_CONTROL_DMA_REQ_LEN_SET(x) (((uint32_t)(x) << LINV2_DMA_CONTROL_DMA_REQ_LEN_SHIFT) & LINV2_DMA_CONTROL_DMA_REQ_LEN_MASK) +#define LINV2_DMA_CONTROL_DMA_REQ_LEN_GET(x) (((uint32_t)(x) & LINV2_DMA_CONTROL_DMA_REQ_LEN_MASK) >> LINV2_DMA_CONTROL_DMA_REQ_LEN_SHIFT) + +/* + * DMA_REQ_ID_TYPE (RW) + * + * 1：transmite 0：receive + */ +#define LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_MASK (0x80U) +#define LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_SHIFT (7U) +#define LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_SET(x) (((uint32_t)(x) << LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_SHIFT) & LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_MASK) +#define LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_GET(x) (((uint32_t)(x) & LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_MASK) >> LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_SHIFT) + +/* + * DMA_REQ_ID (RW) + * + * dma_req_id register + */ +#define LINV2_DMA_CONTROL_DMA_REQ_ID_MASK (0x7EU) +#define LINV2_DMA_CONTROL_DMA_REQ_ID_SHIFT (1U) +#define LINV2_DMA_CONTROL_DMA_REQ_ID_SET(x) (((uint32_t)(x) << LINV2_DMA_CONTROL_DMA_REQ_ID_SHIFT) & LINV2_DMA_CONTROL_DMA_REQ_ID_MASK) +#define LINV2_DMA_CONTROL_DMA_REQ_ID_GET(x) (((uint32_t)(x) & LINV2_DMA_CONTROL_DMA_REQ_ID_MASK) >> LINV2_DMA_CONTROL_DMA_REQ_ID_SHIFT) + +/* + * DMA_REQ_ENABLE (RW) + * + * slave mode only. 1: enable dma request for data request ID equal dma_req_id + */ +#define LINV2_DMA_CONTROL_DMA_REQ_ENABLE_MASK (0x1U) +#define LINV2_DMA_CONTROL_DMA_REQ_ENABLE_SHIFT (0U) +#define LINV2_DMA_CONTROL_DMA_REQ_ENABLE_SET(x) (((uint32_t)(x) << LINV2_DMA_CONTROL_DMA_REQ_ENABLE_SHIFT) & LINV2_DMA_CONTROL_DMA_REQ_ENABLE_MASK) +#define LINV2_DMA_CONTROL_DMA_REQ_ENABLE_GET(x) (((uint32_t)(x) & LINV2_DMA_CONTROL_DMA_REQ_ENABLE_MASK) >> LINV2_DMA_CONTROL_DMA_REQ_ENABLE_SHIFT) + + + +/* DATA register group index macro definition */ +#define LINV2_DATA_DATA0 (0UL) +#define LINV2_DATA_DATA1 (1UL) + +/* DATA_BYTE register group index macro definition */ +#define LINV2_DATA_BYTE_DATA_BYTE0 (0UL) +#define LINV2_DATA_BYTE_DATA_BYTE1 (1UL) +#define LINV2_DATA_BYTE_DATA_BYTE2 (2UL) +#define LINV2_DATA_BYTE_DATA_BYTE3 (3UL) +#define LINV2_DATA_BYTE_DATA_BYTE4 (4UL) +#define LINV2_DATA_BYTE_DATA_BYTE5 (5UL) +#define LINV2_DATA_BYTE_DATA_BYTE6 (6UL) +#define LINV2_DATA_BYTE_DATA_BYTE7 (7UL) + + +#endif /* HPM_LINV2_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_lvb_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_lvb_regs.h new file mode 100644 index 00000000000..2e48cd4b0e6 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_lvb_regs.h @@ -0,0 +1,442 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_LVB_H +#define HPM_LVB_H + +typedef struct { + __RW uint32_t CTRL; /* 0x0: control register */ + __R uint8_t RESERVED0[12]; /* 0x4 - 0xF: Reserved */ + __R uint32_t PHY_STAT; /* 0x10: LVDS TX PHY Status register */ + __RW uint32_t PHY_POW_CTRL[2]; /* 0x14 - 0x18: LVDS0 PHY power control register */ + struct { + __RW uint32_t CTL0; /* 0x1C: TX PHY Setting */ + __RW uint32_t CTL1; /* 0x20: TX_PHY Setting */ + } TX_PHY[10]; +} LVB_Type; + + +/* Bitfield definition for register: CTRL */ +/* + * SPLIT_CH_REVERSE (RW) + * + * Just for split mode, reverse two channel data + */ +#define LVB_CTRL_SPLIT_CH_REVERSE_MASK (0x8000000UL) +#define LVB_CTRL_SPLIT_CH_REVERSE_SHIFT (27U) +#define LVB_CTRL_SPLIT_CH_REVERSE_SET(x) (((uint32_t)(x) << LVB_CTRL_SPLIT_CH_REVERSE_SHIFT) & LVB_CTRL_SPLIT_CH_REVERSE_MASK) +#define LVB_CTRL_SPLIT_CH_REVERSE_GET(x) (((uint32_t)(x) & LVB_CTRL_SPLIT_CH_REVERSE_MASK) >> LVB_CTRL_SPLIT_CH_REVERSE_SHIFT) + +/* + * SPLIT_CH_MODE (RW) + * + * Just for split mode + * 1: two channel pixel data are not aligned + * 0: two channel pixel data are aligned + */ +#define LVB_CTRL_SPLIT_CH_MODE_MASK (0x4000000UL) +#define LVB_CTRL_SPLIT_CH_MODE_SHIFT (26U) +#define LVB_CTRL_SPLIT_CH_MODE_SET(x) (((uint32_t)(x) << LVB_CTRL_SPLIT_CH_MODE_SHIFT) & LVB_CTRL_SPLIT_CH_MODE_MASK) +#define LVB_CTRL_SPLIT_CH_MODE_GET(x) (((uint32_t)(x) & LVB_CTRL_SPLIT_CH_MODE_MASK) >> LVB_CTRL_SPLIT_CH_MODE_SHIFT) + +/* + * SPLIT_HSWHBP_WIDTH (RW) + * + * Just for split mode, the sum of HSW and HBP width is even + * 1: yes + * 0: no + */ +#define LVB_CTRL_SPLIT_HSWHBP_WIDTH_MASK (0x2000000UL) +#define LVB_CTRL_SPLIT_HSWHBP_WIDTH_SHIFT (25U) +#define LVB_CTRL_SPLIT_HSWHBP_WIDTH_SET(x) (((uint32_t)(x) << LVB_CTRL_SPLIT_HSWHBP_WIDTH_SHIFT) & LVB_CTRL_SPLIT_HSWHBP_WIDTH_MASK) +#define LVB_CTRL_SPLIT_HSWHBP_WIDTH_GET(x) (((uint32_t)(x) & LVB_CTRL_SPLIT_HSWHBP_WIDTH_MASK) >> LVB_CTRL_SPLIT_HSWHBP_WIDTH_SHIFT) + +/* + * SPLIT_MODE_EN (RW) + * + * Split mode enable: + * 1: enable + * 0: disable + * Note: when using split mode, ch0/1 should be enabled, and should select same DI + */ +#define LVB_CTRL_SPLIT_MODE_EN_MASK (0x1000000UL) +#define LVB_CTRL_SPLIT_MODE_EN_SHIFT (24U) +#define LVB_CTRL_SPLIT_MODE_EN_SET(x) (((uint32_t)(x) << LVB_CTRL_SPLIT_MODE_EN_SHIFT) & LVB_CTRL_SPLIT_MODE_EN_MASK) +#define LVB_CTRL_SPLIT_MODE_EN_GET(x) (((uint32_t)(x) & LVB_CTRL_SPLIT_MODE_EN_MASK) >> LVB_CTRL_SPLIT_MODE_EN_SHIFT) + +/* + * DI1_VSYNC_POLARITY (RW) + * + * DI 1 vsync polarity: + * 1: active low + * 0: active high + */ +#define LVB_CTRL_DI1_VSYNC_POLARITY_MASK (0x20000UL) +#define LVB_CTRL_DI1_VSYNC_POLARITY_SHIFT (17U) +#define LVB_CTRL_DI1_VSYNC_POLARITY_SET(x) (((uint32_t)(x) << LVB_CTRL_DI1_VSYNC_POLARITY_SHIFT) & LVB_CTRL_DI1_VSYNC_POLARITY_MASK) +#define LVB_CTRL_DI1_VSYNC_POLARITY_GET(x) (((uint32_t)(x) & LVB_CTRL_DI1_VSYNC_POLARITY_MASK) >> LVB_CTRL_DI1_VSYNC_POLARITY_SHIFT) + +/* + * DI0_VSYNC_POLARITY (RW) + * + * DI 0 vsync polarity: + * 1: active low + * 0: active high + */ +#define LVB_CTRL_DI0_VSYNC_POLARITY_MASK (0x10000UL) +#define LVB_CTRL_DI0_VSYNC_POLARITY_SHIFT (16U) +#define LVB_CTRL_DI0_VSYNC_POLARITY_SET(x) (((uint32_t)(x) << LVB_CTRL_DI0_VSYNC_POLARITY_SHIFT) & LVB_CTRL_DI0_VSYNC_POLARITY_MASK) +#define LVB_CTRL_DI0_VSYNC_POLARITY_GET(x) (((uint32_t)(x) & LVB_CTRL_DI0_VSYNC_POLARITY_MASK) >> LVB_CTRL_DI0_VSYNC_POLARITY_SHIFT) + +/* + * LVDS_TXCLK_SHIFT (RW) + * + * Shift the LVDS TX PHY clock in relation to the data. + * 000: txck is 7'b1100011 + * 001: txck is 7‘b1110001 + * 010: txck is 7‘b1111000 + * 011: txck is 7‘b1000111 + * 100: txck is 7‘b0001111 + * 101: txck is 7‘b0011110 + * 110: txck is 7‘b0111100 + * 111: txck is 7‘b1100011 + */ +#define LVB_CTRL_LVDS_TXCLK_SHIFT_MASK (0x700U) +#define LVB_CTRL_LVDS_TXCLK_SHIFT_SHIFT (8U) +#define LVB_CTRL_LVDS_TXCLK_SHIFT_SET(x) (((uint32_t)(x) << LVB_CTRL_LVDS_TXCLK_SHIFT_SHIFT) & LVB_CTRL_LVDS_TXCLK_SHIFT_MASK) +#define LVB_CTRL_LVDS_TXCLK_SHIFT_GET(x) (((uint32_t)(x) & LVB_CTRL_LVDS_TXCLK_SHIFT_MASK) >> LVB_CTRL_LVDS_TXCLK_SHIFT_SHIFT) + +/* + * CH1_BIT_MAPPING (RW) + * + * Channel 1 data protocol: + * 1: JEIDA standard + * 0: SPWG standard + */ +#define LVB_CTRL_CH1_BIT_MAPPING_MASK (0x80U) +#define LVB_CTRL_CH1_BIT_MAPPING_SHIFT (7U) +#define LVB_CTRL_CH1_BIT_MAPPING_SET(x) (((uint32_t)(x) << LVB_CTRL_CH1_BIT_MAPPING_SHIFT) & LVB_CTRL_CH1_BIT_MAPPING_MASK) +#define LVB_CTRL_CH1_BIT_MAPPING_GET(x) (((uint32_t)(x) & LVB_CTRL_CH1_BIT_MAPPING_MASK) >> LVB_CTRL_CH1_BIT_MAPPING_SHIFT) + +/* + * CH0_BIT_MAPPING (RW) + * + * Channel 0 data protocol: + * 1: JEIDA standard + * 0: SPWG standard + */ +#define LVB_CTRL_CH0_BIT_MAPPING_MASK (0x20U) +#define LVB_CTRL_CH0_BIT_MAPPING_SHIFT (5U) +#define LVB_CTRL_CH0_BIT_MAPPING_SET(x) (((uint32_t)(x) << LVB_CTRL_CH0_BIT_MAPPING_SHIFT) & LVB_CTRL_CH0_BIT_MAPPING_MASK) +#define LVB_CTRL_CH0_BIT_MAPPING_GET(x) (((uint32_t)(x) & LVB_CTRL_CH0_BIT_MAPPING_MASK) >> LVB_CTRL_CH0_BIT_MAPPING_SHIFT) + +/* + * CH1_SEL (RW) + * + * Channel 1 select: + * 1: select DI 1 + * 0: select DI 0 + */ +#define LVB_CTRL_CH1_SEL_MASK (0x8U) +#define LVB_CTRL_CH1_SEL_SHIFT (3U) +#define LVB_CTRL_CH1_SEL_SET(x) (((uint32_t)(x) << LVB_CTRL_CH1_SEL_SHIFT) & LVB_CTRL_CH1_SEL_MASK) +#define LVB_CTRL_CH1_SEL_GET(x) (((uint32_t)(x) & LVB_CTRL_CH1_SEL_MASK) >> LVB_CTRL_CH1_SEL_SHIFT) + +/* + * CH1_EN (RW) + * + * Channel 1 enable: + * 1: enable + * 0: disable + */ +#define LVB_CTRL_CH1_EN_MASK (0x4U) +#define LVB_CTRL_CH1_EN_SHIFT (2U) +#define LVB_CTRL_CH1_EN_SET(x) (((uint32_t)(x) << LVB_CTRL_CH1_EN_SHIFT) & LVB_CTRL_CH1_EN_MASK) +#define LVB_CTRL_CH1_EN_GET(x) (((uint32_t)(x) & LVB_CTRL_CH1_EN_MASK) >> LVB_CTRL_CH1_EN_SHIFT) + +/* + * CH0_SEL (RW) + * + * Channel 0 select: + * 1: select DI 1 + * 0: select DI 0 + */ +#define LVB_CTRL_CH0_SEL_MASK (0x2U) +#define LVB_CTRL_CH0_SEL_SHIFT (1U) +#define LVB_CTRL_CH0_SEL_SET(x) (((uint32_t)(x) << LVB_CTRL_CH0_SEL_SHIFT) & LVB_CTRL_CH0_SEL_MASK) +#define LVB_CTRL_CH0_SEL_GET(x) (((uint32_t)(x) & LVB_CTRL_CH0_SEL_MASK) >> LVB_CTRL_CH0_SEL_SHIFT) + +/* + * CH0_EN (RW) + * + * Channel 0 enable: + * 1: enable + * 0: disable + */ +#define LVB_CTRL_CH0_EN_MASK (0x1U) +#define LVB_CTRL_CH0_EN_SHIFT (0U) +#define LVB_CTRL_CH0_EN_SET(x) (((uint32_t)(x) << LVB_CTRL_CH0_EN_SHIFT) & LVB_CTRL_CH0_EN_MASK) +#define LVB_CTRL_CH0_EN_GET(x) (((uint32_t)(x) & LVB_CTRL_CH0_EN_MASK) >> LVB_CTRL_CH0_EN_SHIFT) + +/* Bitfield definition for register: PHY_STAT */ +/* + * LVDS1_TX_PHY_PLL_LOCK (RO) + * + * LVDS1 TX PHY PLL Lock indication Signal, 1 means pll already locked + */ +#define LVB_PHY_STAT_LVDS1_TX_PHY_PLL_LOCK_MASK (0x2U) +#define LVB_PHY_STAT_LVDS1_TX_PHY_PLL_LOCK_SHIFT (1U) +#define LVB_PHY_STAT_LVDS1_TX_PHY_PLL_LOCK_GET(x) (((uint32_t)(x) & LVB_PHY_STAT_LVDS1_TX_PHY_PLL_LOCK_MASK) >> LVB_PHY_STAT_LVDS1_TX_PHY_PLL_LOCK_SHIFT) + +/* + * LVDS0_TX_PHY_PLL_LOCK (RO) + * + * LVDS0 TX PHY PLL Lock indication Signal, 1 means pll already locked + */ +#define LVB_PHY_STAT_LVDS0_TX_PHY_PLL_LOCK_MASK (0x1U) +#define LVB_PHY_STAT_LVDS0_TX_PHY_PLL_LOCK_SHIFT (0U) +#define LVB_PHY_STAT_LVDS0_TX_PHY_PLL_LOCK_GET(x) (((uint32_t)(x) & LVB_PHY_STAT_LVDS0_TX_PHY_PLL_LOCK_MASK) >> LVB_PHY_STAT_LVDS0_TX_PHY_PLL_LOCK_SHIFT) + +/* Bitfield definition for register array: PHY_POW_CTRL */ +/* + * PWON_PLL (RW) + * + * pll power on + */ +#define LVB_PHY_POW_CTRL_PWON_PLL_MASK (0x20U) +#define LVB_PHY_POW_CTRL_PWON_PLL_SHIFT (5U) +#define LVB_PHY_POW_CTRL_PWON_PLL_SET(x) (((uint32_t)(x) << LVB_PHY_POW_CTRL_PWON_PLL_SHIFT) & LVB_PHY_POW_CTRL_PWON_PLL_MASK) +#define LVB_PHY_POW_CTRL_PWON_PLL_GET(x) (((uint32_t)(x) & LVB_PHY_POW_CTRL_PWON_PLL_MASK) >> LVB_PHY_POW_CTRL_PWON_PLL_SHIFT) + +/* + * TXCK_PD (RW) + * + * Power down control signal of channel txck + * 0: Normal operation + * 1: Power down channel + */ +#define LVB_PHY_POW_CTRL_TXCK_PD_MASK (0x10U) +#define LVB_PHY_POW_CTRL_TXCK_PD_SHIFT (4U) +#define LVB_PHY_POW_CTRL_TXCK_PD_SET(x) (((uint32_t)(x) << LVB_PHY_POW_CTRL_TXCK_PD_SHIFT) & LVB_PHY_POW_CTRL_TXCK_PD_MASK) +#define LVB_PHY_POW_CTRL_TXCK_PD_GET(x) (((uint32_t)(x) & LVB_PHY_POW_CTRL_TXCK_PD_MASK) >> LVB_PHY_POW_CTRL_TXCK_PD_SHIFT) + +/* + * TX3_PD (RW) + * + * Power down control signal of channel tx3 + * 0: Normal operation + * 1: Power down channel + */ +#define LVB_PHY_POW_CTRL_TX3_PD_MASK (0x8U) +#define LVB_PHY_POW_CTRL_TX3_PD_SHIFT (3U) +#define LVB_PHY_POW_CTRL_TX3_PD_SET(x) (((uint32_t)(x) << LVB_PHY_POW_CTRL_TX3_PD_SHIFT) & LVB_PHY_POW_CTRL_TX3_PD_MASK) +#define LVB_PHY_POW_CTRL_TX3_PD_GET(x) (((uint32_t)(x) & LVB_PHY_POW_CTRL_TX3_PD_MASK) >> LVB_PHY_POW_CTRL_TX3_PD_SHIFT) + +/* + * TX2_PD (RW) + * + * Power down control signal of channel tx2 + * 0: Normal operation + * 1: Power down channel + */ +#define LVB_PHY_POW_CTRL_TX2_PD_MASK (0x4U) +#define LVB_PHY_POW_CTRL_TX2_PD_SHIFT (2U) +#define LVB_PHY_POW_CTRL_TX2_PD_SET(x) (((uint32_t)(x) << LVB_PHY_POW_CTRL_TX2_PD_SHIFT) & LVB_PHY_POW_CTRL_TX2_PD_MASK) +#define LVB_PHY_POW_CTRL_TX2_PD_GET(x) (((uint32_t)(x) & LVB_PHY_POW_CTRL_TX2_PD_MASK) >> LVB_PHY_POW_CTRL_TX2_PD_SHIFT) + +/* + * TX1_PD (RW) + * + * Power down control signal of channel tx1 + * 0: Normal operation + * 1: Power down channel + */ +#define LVB_PHY_POW_CTRL_TX1_PD_MASK (0x2U) +#define LVB_PHY_POW_CTRL_TX1_PD_SHIFT (1U) +#define LVB_PHY_POW_CTRL_TX1_PD_SET(x) (((uint32_t)(x) << LVB_PHY_POW_CTRL_TX1_PD_SHIFT) & LVB_PHY_POW_CTRL_TX1_PD_MASK) +#define LVB_PHY_POW_CTRL_TX1_PD_GET(x) (((uint32_t)(x) & LVB_PHY_POW_CTRL_TX1_PD_MASK) >> LVB_PHY_POW_CTRL_TX1_PD_SHIFT) + +/* + * TX0_PD (RW) + * + * Power down control signal of channel tx0 + * 0: Normal operation + * 1: Power down channel + */ +#define LVB_PHY_POW_CTRL_TX0_PD_MASK (0x1U) +#define LVB_PHY_POW_CTRL_TX0_PD_SHIFT (0U) +#define LVB_PHY_POW_CTRL_TX0_PD_SET(x) (((uint32_t)(x) << LVB_PHY_POW_CTRL_TX0_PD_SHIFT) & LVB_PHY_POW_CTRL_TX0_PD_MASK) +#define LVB_PHY_POW_CTRL_TX0_PD_GET(x) (((uint32_t)(x) & LVB_PHY_POW_CTRL_TX0_PD_MASK) >> LVB_PHY_POW_CTRL_TX0_PD_SHIFT) + +/* Bitfield definition for register of struct array TX_PHY: CTL0 */ +/* + * TX_IDLE (RW) + * + * Force the high-speed differential signal to common mode. + * This signal can be set during IP power up stage to prevent unexpected leakage current in TXP/TXN + * 0: Normal operation + * 1: Force TXPN /TXMN to common mode + */ +#define LVB_TX_PHY_CTL0_TX_IDLE_MASK (0x100000UL) +#define LVB_TX_PHY_CTL0_TX_IDLE_SHIFT (20U) +#define LVB_TX_PHY_CTL0_TX_IDLE_SET(x) (((uint32_t)(x) << LVB_TX_PHY_CTL0_TX_IDLE_SHIFT) & LVB_TX_PHY_CTL0_TX_IDLE_MASK) +#define LVB_TX_PHY_CTL0_TX_IDLE_GET(x) (((uint32_t)(x) & LVB_TX_PHY_CTL0_TX_IDLE_MASK) >> LVB_TX_PHY_CTL0_TX_IDLE_SHIFT) + +/* + * TX_RTERM_EN (RW) + * + * Inner Terminal Resistance enable + * 0: Disable rterm 2000ohm + * 1: Enable rterm 100ohm + */ +#define LVB_TX_PHY_CTL0_TX_RTERM_EN_MASK (0x80000UL) +#define LVB_TX_PHY_CTL0_TX_RTERM_EN_SHIFT (19U) +#define LVB_TX_PHY_CTL0_TX_RTERM_EN_SET(x) (((uint32_t)(x) << LVB_TX_PHY_CTL0_TX_RTERM_EN_SHIFT) & LVB_TX_PHY_CTL0_TX_RTERM_EN_MASK) +#define LVB_TX_PHY_CTL0_TX_RTERM_EN_GET(x) (((uint32_t)(x) & LVB_TX_PHY_CTL0_TX_RTERM_EN_MASK) >> LVB_TX_PHY_CTL0_TX_RTERM_EN_SHIFT) + +/* + * TX_BUS_WIDTH (RW) + * + * Parallel data bus width select： + * 000: 4-bit mode, txN_data[3:0] are valid, txN_data[11:4] can be arbitrary state. + * 001: 6-bit mode, txN_data[5:0] are valid, txN_data[11:6] can be arbitrary state. + * 010: 7-bit mode. txN_data[6:0] are valid, txN_data[11:7] can be arbitrary state. + * 011: 8-bit mode. txN_data[7:0] are valid, txN_data[11:8] can be arbitrary state. + * 100: 9-bit mode. txN_data[8:0] are valid, txN_data[11:9] can be arbitrary state. + * 101: 10-bit mode. txN_data[9:0] are valid, txN_data[11:10] can be arbitrary state. + * 110: 11-bit mode. txN_data[10:0] are valid, txN_data[11] can be arbitrary state. + * 111: 12-bit mode. txN_data[11:0] are valid + */ +#define LVB_TX_PHY_CTL0_TX_BUS_WIDTH_MASK (0x70000UL) +#define LVB_TX_PHY_CTL0_TX_BUS_WIDTH_SHIFT (16U) +#define LVB_TX_PHY_CTL0_TX_BUS_WIDTH_SET(x) (((uint32_t)(x) << LVB_TX_PHY_CTL0_TX_BUS_WIDTH_SHIFT) & LVB_TX_PHY_CTL0_TX_BUS_WIDTH_MASK) +#define LVB_TX_PHY_CTL0_TX_BUS_WIDTH_GET(x) (((uint32_t)(x) & LVB_TX_PHY_CTL0_TX_BUS_WIDTH_MASK) >> LVB_TX_PHY_CTL0_TX_BUS_WIDTH_SHIFT) + +/* + * TX_PHASE_SEL (RW) + * + * data/clock lane output phase adjustment: + * 0000: 0 + * 0001: data lane is 1/32, clock lane is 1/16 + * 0010: data lane is 2/32, clock lane is 2/16 + * 0011: data lane is 3/32, clock lane is 3/16 + * 0100: data lane is 4/32, clock lane is 4/16 + * 0101: data lane is 5/32, clock lane is 5/16 + * 0110: data lane is 6/32, clock lane is 6/16 + * 0111: data lane is 7/32, clock lane is 7/16 + * 1000: data lane is 8/32, clock lane is 8/16 + * 1001: data lane is 9/32, clock lane is 9/16 + * 1010: data lane is 10/32, clock lane is 10/16 + * 1011: data lane is 11/32, clock lane is 11/16 + * 1100: data lane is 12/32, clock lane is 12/16 + * 1101: data lane is 13/32, clock lane is 13/16 + * 1110: data lane is 14/32, clock lane is 14/16 + * 1111: data lane is 15/32, clock lane is 15/16 + */ +#define LVB_TX_PHY_CTL0_TX_PHASE_SEL_MASK (0xF000U) +#define LVB_TX_PHY_CTL0_TX_PHASE_SEL_SHIFT (12U) +#define LVB_TX_PHY_CTL0_TX_PHASE_SEL_SET(x) (((uint32_t)(x) << LVB_TX_PHY_CTL0_TX_PHASE_SEL_SHIFT) & LVB_TX_PHY_CTL0_TX_PHASE_SEL_MASK) +#define LVB_TX_PHY_CTL0_TX_PHASE_SEL_GET(x) (((uint32_t)(x) & LVB_TX_PHY_CTL0_TX_PHASE_SEL_MASK) >> LVB_TX_PHY_CTL0_TX_PHASE_SEL_SHIFT) + +/* + * TX_VCOM (RW) + * + * output Common Mode Voltage adjustment(Unit: V). + * 0000: 0.7 + * 0001: 0.8 + * 0010: 0.9 + * 0011: 1.0 + * 0100: 1.1 + * 0101: 1.2 + * 0110: 1.3 + * 0111: 1.4 + * 1000~1111: 1.5 + */ +#define LVB_TX_PHY_CTL0_TX_VCOM_MASK (0xF00U) +#define LVB_TX_PHY_CTL0_TX_VCOM_SHIFT (8U) +#define LVB_TX_PHY_CTL0_TX_VCOM_SET(x) (((uint32_t)(x) << LVB_TX_PHY_CTL0_TX_VCOM_SHIFT) & LVB_TX_PHY_CTL0_TX_VCOM_MASK) +#define LVB_TX_PHY_CTL0_TX_VCOM_GET(x) (((uint32_t)(x) & LVB_TX_PHY_CTL0_TX_VCOM_MASK) >> LVB_TX_PHY_CTL0_TX_VCOM_SHIFT) + +/* + * TX_AMP (RW) + * + * Output voltage Adjustment(Unit: mV). + * 0000 : 50 + * 0001: 100 + * 0010: 150 + * 0011: 200 + * 0100: 250 + * 0101: 300 + * 0110: 350 + * 0111: 400 + * 1000: 450 + * 1001: 500 + * 1010: 550 + * 1011~1111: 600 + */ +#define LVB_TX_PHY_CTL0_TX_AMP_MASK (0xF0U) +#define LVB_TX_PHY_CTL0_TX_AMP_SHIFT (4U) +#define LVB_TX_PHY_CTL0_TX_AMP_SET(x) (((uint32_t)(x) << LVB_TX_PHY_CTL0_TX_AMP_SHIFT) & LVB_TX_PHY_CTL0_TX_AMP_MASK) +#define LVB_TX_PHY_CTL0_TX_AMP_GET(x) (((uint32_t)(x) & LVB_TX_PHY_CTL0_TX_AMP_MASK) >> LVB_TX_PHY_CTL0_TX_AMP_SHIFT) + +/* + * TX_SR (RW) + * + * output slew-rate trimming + * 00: slowest slew-rate; + * 11: fastest slew-rate + */ +#define LVB_TX_PHY_CTL0_TX_SR_MASK (0xCU) +#define LVB_TX_PHY_CTL0_TX_SR_SHIFT (2U) +#define LVB_TX_PHY_CTL0_TX_SR_SET(x) (((uint32_t)(x) << LVB_TX_PHY_CTL0_TX_SR_SHIFT) & LVB_TX_PHY_CTL0_TX_SR_MASK) +#define LVB_TX_PHY_CTL0_TX_SR_GET(x) (((uint32_t)(x) & LVB_TX_PHY_CTL0_TX_SR_MASK) >> LVB_TX_PHY_CTL0_TX_SR_SHIFT) + +/* + * TX_DEEMP (RW) + * + * output de-emphasis level trimming(Unit: dB) + * 00: 0 + * 01: 2.5 + * 10: 6.0 + * 11: 6.0 + */ +#define LVB_TX_PHY_CTL0_TX_DEEMP_MASK (0x3U) +#define LVB_TX_PHY_CTL0_TX_DEEMP_SHIFT (0U) +#define LVB_TX_PHY_CTL0_TX_DEEMP_SET(x) (((uint32_t)(x) << LVB_TX_PHY_CTL0_TX_DEEMP_SHIFT) & LVB_TX_PHY_CTL0_TX_DEEMP_MASK) +#define LVB_TX_PHY_CTL0_TX_DEEMP_GET(x) (((uint32_t)(x) & LVB_TX_PHY_CTL0_TX_DEEMP_MASK) >> LVB_TX_PHY_CTL0_TX_DEEMP_SHIFT) + +/* Bitfield definition for register of struct array TX_PHY: CTL1 */ +/* + * TX_CTL (RW) + * + */ +#define LVB_TX_PHY_CTL1_TX_CTL_MASK (0xFFFFFUL) +#define LVB_TX_PHY_CTL1_TX_CTL_SHIFT (0U) +#define LVB_TX_PHY_CTL1_TX_CTL_SET(x) (((uint32_t)(x) << LVB_TX_PHY_CTL1_TX_CTL_SHIFT) & LVB_TX_PHY_CTL1_TX_CTL_MASK) +#define LVB_TX_PHY_CTL1_TX_CTL_GET(x) (((uint32_t)(x) & LVB_TX_PHY_CTL1_TX_CTL_MASK) >> LVB_TX_PHY_CTL1_TX_CTL_SHIFT) + + + +/* PHY_POW_CTRL register group index macro definition */ +#define LVB_PHY_POW_CTRL_LVDS0 (0UL) +#define LVB_PHY_POW_CTRL_LVDS1 (1UL) + +/* TX_PHY register group index macro definition */ +#define LVB_TX_PHY_LVDS0_TX0 (0UL) +#define LVB_TX_PHY_LVDS0_TX1 (1UL) +#define LVB_TX_PHY_LVDS0_TX2 (1UL) +#define LVB_TX_PHY_LVDS0_TX3 (3UL) +#define LVB_TX_PHY_LVDS0_TXCK (4UL) +#define LVB_TX_PHY_LVDS1_TX0 (5UL) +#define LVB_TX_PHY_LVDS1_TX1 (6UL) +#define LVB_TX_PHY_LVDS1_TX2 (7UL) +#define LVB_TX_PHY_LVDS1_TX3 (8UL) +#define LVB_TX_PHY_LVDS1_TXCK (9UL) + + +#endif /* HPM_LVB_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mcan_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mcan_regs.h index e2cfd0f8f70..b18f356a569 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mcan_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mcan_regs.h @@ -63,7 +63,7 @@ typedef struct { __R uint32_t TXEFS; /* 0xF4: tx event fifo status */ __RW uint32_t TXEFA; /* 0xF8: tx event fifo acknowledge */ __R uint8_t RESERVED7[260]; /* 0xFC - 0x1FF: Reserved */ - __R uint32_t TS_SEL[16]; /* 0x200 - 0x23C: timestamp 0-15 */ + __R uint32_t TS_SEL[16]; /* 0x200 - 0x23C: timestamp 0 */ __R uint32_t CREL; /* 0x240: core release register */ __RW uint32_t TSCFG; /* 0x244: timestamp configuration */ __R uint32_t TSS1; /* 0x248: timestamp status1 */ @@ -106,7 +106,8 @@ typedef struct { * DBRP (RW) * * Data Bit Rate Prescaler - * The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. When TDC = ‘1’, the range is limited to 0,1. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + * The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. + * When TDC = ‘1’, the range is limited to 0,1. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. */ #define MCAN_DBTP_DBRP_MASK (0x1F0000UL) #define MCAN_DBTP_DBRP_SHIFT (16U) @@ -531,7 +532,8 @@ typedef struct { * TSC (RC) * * Timestamp Counter - * The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx).When TSCC.TSS = “01”, the Timestamp Counter is incremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = “10”, TSC reflects the external Timestamp Counter value. A write access has no impact. + * The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx).When TSCC.TSS = “01”, the Timestamp Counter is incremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. + * A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = “10”, TSC reflects the external Timestamp Counter value. A write access has no impact. */ #define MCAN_TSCV_TSC_MASK (0xFFFFU) #define MCAN_TSCV_TSC_SHIFT (0U) @@ -553,7 +555,8 @@ typedef struct { * TOS (RW) * * Timeout Select - * When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. + * When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. + * When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. * 00= Continuous operation * 01= Timeout controlled by Tx Event FIFO * 10= Timeout controlled by Rx FIFO 0 @@ -581,7 +584,8 @@ typedef struct { * TOC (RC) * * Timeout Counter - * The Timeout Counter is decremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. + * The Timeout Counter is decremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. + * When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. * Note: Byte access: when TOCC.TOS = “00，writing one of the register bytes 3/2/1/0 will preset the Timeout Counter. */ #define MCAN_TOCV_TOC_MASK (0xFFFFU) @@ -593,7 +597,8 @@ typedef struct { * CEL (X) * * CAN Error Logging - * The counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. The counter is also incremented when the Bus_Off limit is reached. It is not incremented when only RP is set without changing REC. The increment of CEL follows after the increment of REC or TEC. + * The counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. + * The counter is also incremented when the Bus_Off limit is reached. It is not incremented when only RP is set without changing REC. The increment of CEL follows after the increment of REC or TEC. * The counter is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. * Note: Byte access: Reading byte 2 will reset CEL to zero, reading bytes 3/1/0 has no impact. */ @@ -638,7 +643,8 @@ typedef struct { * TDCV (R) * * Transmitter Delay Compensation Value - * Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. + * Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. + * The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. */ #define MCAN_PSR_TDCV_MASK (0x7F0000UL) #define MCAN_PSR_TDCV_SHIFT (16U) @@ -767,12 +773,16 @@ typedef struct { * 4= Bit1Error: During the transmission of a message (with the exception of the arbitration field), * the device wanted to send a recessive level (bit of logical value ‘1’), but the monitored bus * value was dominant. - * 5= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value‘0’), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at + * 5= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value‘0’), but the monitored bus value was recessive. + * During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at * dominant or continuously disturbed). * 6= CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. * 7= NoChange: Any read access to the Protocol Status Register re-initializes the LEC to ‘7’. When the LEC shows the value ‘7’, no CAN bus event was detected since the last CPU read access to the Protocol Status Register. * Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error. - * Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord,stopping all bus activities. Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences. + * Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord,stopping all bus activities. + * Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. + * At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, + * enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences. * Note: Byte access: Reading byte 0 will set LEC to “111”, reading bytes 3/2/1 has no impact. */ #define MCAN_PSR_LEC_MASK (0x7U) @@ -795,7 +805,8 @@ typedef struct { * TDCF (RW) * * Transmitter Delay Compensation Filter Window Length - * Defines the minimum value for the SSP position, dominant edges on m_can_rx that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq. + * Defines the minimum value for the SSP position, dominant edges on m_can_rx that would result in an earlier SSP position are ignored for transmitter delay measurement. + * The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq. */ #define MCAN_TDCR_TDCF_MASK (0x7FU) #define MCAN_TDCR_TDCF_SHIFT (0U) @@ -903,7 +914,8 @@ typedef struct { * BEU (RW) * * Bit Error Uncorrected - * Message RAM bit error detected, uncorrected. Controlled by input signal m_can_aeim_berr[1] generated by an optional external parity / ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets CCCR.INIT to ‘1’. This is done to avoid transmission of corrupted data. + * Message RAM bit error detected, uncorrected. Controlled by input signal m_can_aeim_berr[1] generated by an optional external parity / ECC logic attached to the Message RAM. + * An uncorrected Message RAM bit error sets CCCR.INIT to ‘1’. This is done to avoid transmission of corrupted data. * 0= No bit error detected when reading from Message RAM * 1= Bit error detected, uncorrected (e.g. parity logic) */ @@ -1910,7 +1922,8 @@ typedef struct { * EIDM (RW) * * Extended ID Mask - * For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active. + * For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. + * Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active. */ #define MCAN_XIDAM_EIDM_MASK (0x1FFFFFFFUL) #define MCAN_XIDAM_EIDM_SHIFT (0U) @@ -1968,7 +1981,8 @@ typedef struct { * ND1 (RW) * * New Data[31:0] - * The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them.A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. + * The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. + * The flags remain set until the Host clears them.A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. * 0= Rx Buffer not updated * 1= Rx Buffer updated from new message */ @@ -1982,7 +1996,8 @@ typedef struct { * ND2 (RW) * * New Data[63:32] - * The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. + * The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. + * The flags remain set until the Host clears them. A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. * 0= Rx Buffer not updated * 1= Rx Buffer updated from new message */ @@ -2103,7 +2118,8 @@ typedef struct { * F0AI (RW) * * Rx FIFO 0 Acknowledge Index - * After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. + * After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. + * This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. */ #define MCAN_RXF0A_F0AI_MASK (0x3FU) #define MCAN_RXF0A_F0AI_SHIFT (0U) @@ -2247,7 +2263,8 @@ typedef struct { * F1AI (RW) * * Rx FIFO 1 Acknowledge Index - * After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. + * After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. + * This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. */ #define MCAN_RXF1A_F1AI_MASK (0x3FU) #define MCAN_RXF1A_F1AI_SHIFT (0U) @@ -2303,7 +2320,8 @@ typedef struct { * 101= 32 byte data field * 110= 48 byte data field * 111= 64 byte data field - * Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame’s data field is ignored. + * Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, + * only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame’s data field is ignored. */ #define MCAN_RXESC_F0DS_MASK (0x7U) #define MCAN_RXESC_F0DS_SHIFT (0U) @@ -2436,7 +2454,8 @@ typedef struct { * TXBCR. * TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan (see Section 3.5, Tx Handling) is started to check for the pending Tx request with the * highest priority (Tx Buffer with lowest Message ID). - * A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. + * A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, + * this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. * After a cancellation has been requested, a finished cancellation is signalled via TXBCF * ? after successful transmission together with the corresponding TXBTO bit * ? when the transmission has not yet been started at the point of cancellation @@ -2473,7 +2492,8 @@ typedef struct { * CR (RW) * * Cancellation Request - * Each Tx Buffer has its own Cancellation Request bit. Writing a ‘1’ will set the corresponding Cancellation Request bit; writing a ‘0’ has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. + * Each Tx Buffer has its own Cancellation Request bit. Writing a ‘1’ will set the corresponding Cancellation Request bit; writing a ‘0’ has no impact. + * This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. * 0= No cancellation pending * 1= Cancellation pending */ @@ -2500,7 +2520,8 @@ typedef struct { * CF (R) * * Cancellation Finished - * Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. + * Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. + * In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. * 0= No transmit buffer cancellation * 1= Transmit buffer cancellation finished */ @@ -2881,8 +2902,9 @@ typedef struct { /* * TSU_TBIN_SEL (RW) * + * external timestamp select. each CAN block has 4 timestamp input, this register is used to select one of them as timestame if TSCFG.TBCS is set to 1 */ -#define MCAN_GLB_CTL_TSU_TBIN_SEL_MASK (0x7U) +#define MCAN_GLB_CTL_TSU_TBIN_SEL_MASK (0x3U) #define MCAN_GLB_CTL_TSU_TBIN_SEL_SHIFT (0U) #define MCAN_GLB_CTL_TSU_TBIN_SEL_SET(x) (((uint32_t)(x) << MCAN_GLB_CTL_TSU_TBIN_SEL_SHIFT) & MCAN_GLB_CTL_TSU_TBIN_SEL_MASK) #define MCAN_GLB_CTL_TSU_TBIN_SEL_GET(x) (((uint32_t)(x) & MCAN_GLB_CTL_TSU_TBIN_SEL_MASK) >> MCAN_GLB_CTL_TSU_TBIN_SEL_SHIFT) diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mipi_csi_phy_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mipi_csi_phy_regs.h new file mode 100644 index 00000000000..bd36a9af339 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mipi_csi_phy_regs.h @@ -0,0 +1,961 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_MIPI_CSI_PHY_H +#define HPM_MIPI_CSI_PHY_H + +typedef struct { + __RW uint32_t SOFT_RST; /* 0x0: soft reset control */ + __RW uint32_t PHY_RCAL; /* 0x4: dphy resistor calibration */ + __RW uint32_t ULP_RX_EN; /* 0x8: enable lprx and ulprx */ + __R uint32_t VOFFCAL_OUT; /* 0xC: hs-rx dc-offset auto-calibration results */ + __RW uint32_t CSI_CTL01; /* 0x10: dphy hardcore control */ + __RW uint32_t CSI_CTL23; /* 0x14: dphy hardcore control */ + __R uint8_t RESERVED0[4]; /* 0x18 - 0x1B: Reserved */ + __RW uint32_t CSI_VINIT; /* 0x1C: ulp lp-rx input threshold voltage trimming for data lane */ + __RW uint32_t CLANE_PARA; /* 0x20: clock lane parameter */ + __RW uint32_t T_HS_TERMEN; /* 0x24: t-termen of all datalane */ + __RW uint32_t T_HS_SETTLE; /* 0x28: t-settle of all data lanes */ + __R uint8_t RESERVED1[4]; /* 0x2C - 0x2F: Reserved */ + __RW uint32_t T_CLANE_INIT; /* 0x30: t-init of clock lane */ + __RW uint32_t T_LANE_INIT0; /* 0x34: t-init of data lane0 */ + __RW uint32_t T_LANE_INIT1; /* 0x38: t-init of data lane1 */ + __R uint8_t RESERVED2[8]; /* 0x3C - 0x43: Reserved */ + __RW uint32_t TLPX_CTRL; /* 0x44: the time of tlpx_ctrl of all lane */ + __RW uint32_t NE_SWAP; /* 0x48: lane swap and dp/dn swap select */ + __RW uint32_t MISC_INFO; /* 0x4C: misc info of dphyrx_pcs control */ + __R uint8_t RESERVED3[32]; /* 0x50 - 0x6F: Reserved */ + __RW uint32_t BIST_TEST0; /* 0x70: bist test control */ + __RW uint32_t BIST_TEST1; /* 0x74: bist test control */ + __RW uint32_t BIST_TEST2; /* 0x78: bist test control */ + __R uint32_t BIST_TEST3; /* 0x7C: bist test control */ + __R uint8_t RESERVED4[32]; /* 0x80 - 0x9F: Reserved */ + __RW uint32_t BURN_IN_TEST0; /* 0xA0: burn-in test control */ + __RW uint32_t BURN_IN_TEST1; /* 0xA4: burn-in test control */ + __R uint32_t BURN_IN_TEST2; /* 0xA8: bist test control */ + __R uint8_t RESERVED5[4]; /* 0xAC - 0xAF: Reserved */ + __R uint32_t BURN_IN_TEST4; /* 0xB0: bist test control */ + __R uint32_t BURN_IN_TEST5; /* 0xB4: burn-in test control */ + __R uint32_t BURN_IN_TEST6; /* 0xB8: burn-in test control */ + __R uint8_t RESERVED6[8]; /* 0xBC - 0xC3: Reserved */ + __R uint32_t BURN_IN_TEST9; /* 0xC4: burn-in test control */ + __R uint8_t RESERVED7[8]; /* 0xC8 - 0xCF: Reserved */ + __RW uint32_t DEBUG_INFO; /* 0xD0: debug data control */ + __RW uint32_t DEBUG_CFG_REG0; /* 0xD4: the hardcore interface control in debug mode */ + __RW uint32_t DEBUG_CFG_REG1; /* 0xD8: the hardcore interface control in debug mode */ + __R uint8_t RESERVED8[3126]; /* 0xDC - 0xD11: Reserved */ + __RW uint32_t DEBUG_CFG_REG2; /* 0xD12: the hardcore interface control in debug mode */ + __RW uint32_t DEBUG_CFG_REG3; /* 0xD16: the hardcore interface control in debug mode */ + __R uint8_t RESERVED9[6]; /* 0xD1A - 0xD1F: Reserved */ + __RW uint32_t DEBUG_CFG_REG4; /* 0xD20: the hardcore interface control in debug mode */ + __RW uint32_t DEBUG_CFG_REG5; /* 0xD24: the hardcore interface control in debug mode */ +} MIPI_CSI_PHY_Type; + + +/* Bitfield definition for register: SOFT_RST */ +/* + * HS_CLK_SOFT_RST (RW) + * + * the soft reset of clk_hs domain + */ +#define MIPI_CSI_PHY_SOFT_RST_HS_CLK_SOFT_RST_MASK (0x2U) +#define MIPI_CSI_PHY_SOFT_RST_HS_CLK_SOFT_RST_SHIFT (1U) +#define MIPI_CSI_PHY_SOFT_RST_HS_CLK_SOFT_RST_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_SOFT_RST_HS_CLK_SOFT_RST_SHIFT) & MIPI_CSI_PHY_SOFT_RST_HS_CLK_SOFT_RST_MASK) +#define MIPI_CSI_PHY_SOFT_RST_HS_CLK_SOFT_RST_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_SOFT_RST_HS_CLK_SOFT_RST_MASK) >> MIPI_CSI_PHY_SOFT_RST_HS_CLK_SOFT_RST_SHIFT) + +/* + * CFG_CLK_SOFT_RST (RW) + * + * the soft reset of clk_cfg domain + */ +#define MIPI_CSI_PHY_SOFT_RST_CFG_CLK_SOFT_RST_MASK (0x1U) +#define MIPI_CSI_PHY_SOFT_RST_CFG_CLK_SOFT_RST_SHIFT (0U) +#define MIPI_CSI_PHY_SOFT_RST_CFG_CLK_SOFT_RST_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_SOFT_RST_CFG_CLK_SOFT_RST_SHIFT) & MIPI_CSI_PHY_SOFT_RST_CFG_CLK_SOFT_RST_MASK) +#define MIPI_CSI_PHY_SOFT_RST_CFG_CLK_SOFT_RST_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_SOFT_RST_CFG_CLK_SOFT_RST_MASK) >> MIPI_CSI_PHY_SOFT_RST_CFG_CLK_SOFT_RST_SHIFT) + +/* Bitfield definition for register: PHY_RCAL */ +/* + * RCAL_DONE (RO) + * + * hs-rx terminal trimming done indicator signal + */ +#define MIPI_CSI_PHY_PHY_RCAL_RCAL_DONE_MASK (0x20000UL) +#define MIPI_CSI_PHY_PHY_RCAL_RCAL_DONE_SHIFT (17U) +#define MIPI_CSI_PHY_PHY_RCAL_RCAL_DONE_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_PHY_RCAL_RCAL_DONE_MASK) >> MIPI_CSI_PHY_PHY_RCAL_RCAL_DONE_SHIFT) + +/* + * RCAL_OUT (RO) + * + * hs-rx terminal trimming results + */ +#define MIPI_CSI_PHY_PHY_RCAL_RCAL_OUT_MASK (0x1E000UL) +#define MIPI_CSI_PHY_PHY_RCAL_RCAL_OUT_SHIFT (13U) +#define MIPI_CSI_PHY_PHY_RCAL_RCAL_OUT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_PHY_RCAL_RCAL_OUT_MASK) >> MIPI_CSI_PHY_PHY_RCAL_RCAL_OUT_SHIFT) + +/* + * RCAL_CTL (RW) + * + * rcal function control + */ +#define MIPI_CSI_PHY_PHY_RCAL_RCAL_CTL_MASK (0x1FE0U) +#define MIPI_CSI_PHY_PHY_RCAL_RCAL_CTL_SHIFT (5U) +#define MIPI_CSI_PHY_PHY_RCAL_RCAL_CTL_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_PHY_RCAL_RCAL_CTL_SHIFT) & MIPI_CSI_PHY_PHY_RCAL_RCAL_CTL_MASK) +#define MIPI_CSI_PHY_PHY_RCAL_RCAL_CTL_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_PHY_RCAL_RCAL_CTL_MASK) >> MIPI_CSI_PHY_PHY_RCAL_RCAL_CTL_SHIFT) + +/* + * RCAL_TRIM (RW) + * + * default value of HS-RX terminal configure + */ +#define MIPI_CSI_PHY_PHY_RCAL_RCAL_TRIM_MASK (0x1EU) +#define MIPI_CSI_PHY_PHY_RCAL_RCAL_TRIM_SHIFT (1U) +#define MIPI_CSI_PHY_PHY_RCAL_RCAL_TRIM_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_PHY_RCAL_RCAL_TRIM_SHIFT) & MIPI_CSI_PHY_PHY_RCAL_RCAL_TRIM_MASK) +#define MIPI_CSI_PHY_PHY_RCAL_RCAL_TRIM_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_PHY_RCAL_RCAL_TRIM_MASK) >> MIPI_CSI_PHY_PHY_RCAL_RCAL_TRIM_SHIFT) + +/* + * RCAL_EN (RW) + * + * enable hs-rx terminal trimming + */ +#define MIPI_CSI_PHY_PHY_RCAL_RCAL_EN_MASK (0x1U) +#define MIPI_CSI_PHY_PHY_RCAL_RCAL_EN_SHIFT (0U) +#define MIPI_CSI_PHY_PHY_RCAL_RCAL_EN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_PHY_RCAL_RCAL_EN_SHIFT) & MIPI_CSI_PHY_PHY_RCAL_RCAL_EN_MASK) +#define MIPI_CSI_PHY_PHY_RCAL_RCAL_EN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_PHY_RCAL_RCAL_EN_MASK) >> MIPI_CSI_PHY_PHY_RCAL_RCAL_EN_SHIFT) + +/* Bitfield definition for register: ULP_RX_EN */ +/* + * CSI_1_ULPRX_EN (RW) + * + * data lane1 ulp-rx receiver enable control + */ +#define MIPI_CSI_PHY_ULP_RX_EN_CSI_1_ULPRX_EN_MASK (0x80U) +#define MIPI_CSI_PHY_ULP_RX_EN_CSI_1_ULPRX_EN_SHIFT (7U) +#define MIPI_CSI_PHY_ULP_RX_EN_CSI_1_ULPRX_EN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_ULP_RX_EN_CSI_1_ULPRX_EN_SHIFT) & MIPI_CSI_PHY_ULP_RX_EN_CSI_1_ULPRX_EN_MASK) +#define MIPI_CSI_PHY_ULP_RX_EN_CSI_1_ULPRX_EN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_ULP_RX_EN_CSI_1_ULPRX_EN_MASK) >> MIPI_CSI_PHY_ULP_RX_EN_CSI_1_ULPRX_EN_SHIFT) + +/* + * CSI_0_ULPRX_EN (RW) + * + * data lane0 ulp-rx receiver enable control + */ +#define MIPI_CSI_PHY_ULP_RX_EN_CSI_0_ULPRX_EN_MASK (0x40U) +#define MIPI_CSI_PHY_ULP_RX_EN_CSI_0_ULPRX_EN_SHIFT (6U) +#define MIPI_CSI_PHY_ULP_RX_EN_CSI_0_ULPRX_EN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_ULP_RX_EN_CSI_0_ULPRX_EN_SHIFT) & MIPI_CSI_PHY_ULP_RX_EN_CSI_0_ULPRX_EN_MASK) +#define MIPI_CSI_PHY_ULP_RX_EN_CSI_0_ULPRX_EN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_ULP_RX_EN_CSI_0_ULPRX_EN_MASK) >> MIPI_CSI_PHY_ULP_RX_EN_CSI_0_ULPRX_EN_SHIFT) + +/* + * CSI_CLK_ULPRX_EN (RW) + * + * clock lane ulp-rx receiver enable control + */ +#define MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_ULPRX_EN_MASK (0x20U) +#define MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_ULPRX_EN_SHIFT (5U) +#define MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_ULPRX_EN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_ULPRX_EN_SHIFT) & MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_ULPRX_EN_MASK) +#define MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_ULPRX_EN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_ULPRX_EN_MASK) >> MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_ULPRX_EN_SHIFT) + +/* + * CSI_1_LPRX_EN (RW) + * + * data lane1 lp-rx receiver enable control + */ +#define MIPI_CSI_PHY_ULP_RX_EN_CSI_1_LPRX_EN_MASK (0x2U) +#define MIPI_CSI_PHY_ULP_RX_EN_CSI_1_LPRX_EN_SHIFT (1U) +#define MIPI_CSI_PHY_ULP_RX_EN_CSI_1_LPRX_EN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_ULP_RX_EN_CSI_1_LPRX_EN_SHIFT) & MIPI_CSI_PHY_ULP_RX_EN_CSI_1_LPRX_EN_MASK) +#define MIPI_CSI_PHY_ULP_RX_EN_CSI_1_LPRX_EN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_ULP_RX_EN_CSI_1_LPRX_EN_MASK) >> MIPI_CSI_PHY_ULP_RX_EN_CSI_1_LPRX_EN_SHIFT) + +/* + * CSI_CLK_LPRX_EN (RW) + * + * clock lane lp=rx receiver enable control + */ +#define MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_LPRX_EN_MASK (0x1U) +#define MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_LPRX_EN_SHIFT (0U) +#define MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_LPRX_EN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_LPRX_EN_SHIFT) & MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_LPRX_EN_MASK) +#define MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_LPRX_EN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_LPRX_EN_MASK) >> MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_LPRX_EN_SHIFT) + +/* Bitfield definition for register: VOFFCAL_OUT */ +/* + * CSI_CLK_VOFFCAL_DONE (RO) + * + * clock lane hs-rx dc-offset auto-calibration done + */ +#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_DONE_MASK (0x20000000UL) +#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_DONE_SHIFT (29U) +#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_DONE_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_DONE_MASK) >> MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_DONE_SHIFT) + +/* + * CSI_CLK_VOFFCAL_OUT (RO) + * + * clock lane hs-rx dc-offset auto-calibration results + */ +#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_OUT_MASK (0x1F000000UL) +#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_OUT_SHIFT (24U) +#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_OUT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_OUT_MASK) >> MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_OUT_SHIFT) + +/* + * CSI_0_VOFFCAL_DONE (RO) + * + * data lane0 hs-rx dc-offset auto-calibration done + */ +#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_0_VOFFCAL_DONE_MASK (0x800000UL) +#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_0_VOFFCAL_DONE_SHIFT (23U) +#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_0_VOFFCAL_DONE_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_VOFFCAL_OUT_CSI_0_VOFFCAL_DONE_MASK) >> MIPI_CSI_PHY_VOFFCAL_OUT_CSI_0_VOFFCAL_DONE_SHIFT) + +/* + * CSI_O_VOFFCAL_OUT (RO) + * + * data lane0 hs-rx dc-offset auto-calibration result + */ +#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_O_VOFFCAL_OUT_MASK (0x7C0000UL) +#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_O_VOFFCAL_OUT_SHIFT (18U) +#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_O_VOFFCAL_OUT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_VOFFCAL_OUT_CSI_O_VOFFCAL_OUT_MASK) >> MIPI_CSI_PHY_VOFFCAL_OUT_CSI_O_VOFFCAL_OUT_SHIFT) + +/* + * CSI_1_VOFFCAL_DONE (RO) + * + * data lane1 hs-rx dc-offset auto-calibration done + */ +#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_DONE_MASK (0x20000UL) +#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_DONE_SHIFT (17U) +#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_DONE_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_DONE_MASK) >> MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_DONE_SHIFT) + +/* + * CSI_1_VOFFCAL_OUT (RO) + * + * data lane1 hs-rx dc-offset auto-calibration result + */ +#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_OUT_MASK (0x1F000UL) +#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_OUT_SHIFT (12U) +#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_OUT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_OUT_MASK) >> MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_OUT_SHIFT) + +/* Bitfield definition for register: CSI_CTL01 */ +/* + * CSI_CTL1_7 (RW) + * + * clock lane hs-rx dc-offset auto-calibration enable + */ +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_7_MASK (0x20000000UL) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_7_SHIFT (29U) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_7_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_7_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_7_MASK) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_7_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_7_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_7_SHIFT) + +/* + * CSI_CTL1_6 (RW) + * + * clock lane hs-rx dc-offset trimming control + */ +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_6_MASK (0x1F000000UL) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_6_SHIFT (24U) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_6_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_6_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_6_MASK) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_6_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_6_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_6_SHIFT) + +/* + * CSI_CTL1_5 (RW) + * + * ulprx_vref_trim + */ +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_5_MASK (0x600000UL) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_5_SHIFT (21U) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_5_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_5_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_5_MASK) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_5_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_5_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_5_SHIFT) + +/* + * CSI_CTL1_4 (RW) + * + * bypass hs_rx_voffcal_en + */ +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_4_MASK (0x100000UL) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_4_SHIFT (20U) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_4_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_4_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_4_MASK) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_4_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_4_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_4_SHIFT) + +/* + * CSI_CTL1_3 (RW) + * + * hs_rx_voffcal_trim_polar + */ +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_3_MASK (0x80000UL) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_3_SHIFT (19U) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_3_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_3_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_3_MASK) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_3_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_3_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_3_SHIFT) + +/* + * CSI_CTL1_2 (RW) + * + * ulprx_lpen + */ +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_2_MASK (0x40000UL) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_2_SHIFT (18U) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_2_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_2_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_2_MASK) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_2_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_2_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_2_SHIFT) + +/* + * CSI_CTL1_1 (RW) + * + * force data lane-n and clock lane lp/ulprx to be normal operation + */ +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_1_MASK (0x20000UL) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_1_SHIFT (17U) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_1_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_1_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_1_MASK) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_1_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_1_SHIFT) + +/* + * CSI_CTL1_0 (RW) + * + * force data lane-n and clock lane hs-rx to be normal operation + */ +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_0_MASK (0x10000UL) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_0_SHIFT (16U) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_0_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_0_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_0_MASK) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_0_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_0_SHIFT) + +/* + * CSI_CTL0_7 (RW) + * + * clock lane hs-rx dc-offset auto-calibration enable + */ +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_7_MASK (0x2000U) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_7_SHIFT (13U) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_7_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_7_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_7_MASK) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_7_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_7_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_7_SHIFT) + +/* + * CSI_CTL0_6 (RW) + * + * clock lane hs-rx dc-offset trimming control + */ +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_6_MASK (0x1F00U) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_6_SHIFT (8U) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_6_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_6_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_6_MASK) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_6_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_6_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_6_SHIFT) + +/* + * CSI_CTL0_5 (RW) + * + * ulprx_vref_trim + */ +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_5_MASK (0x60U) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_5_SHIFT (5U) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_5_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_5_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_5_MASK) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_5_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_5_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_5_SHIFT) + +/* + * CSI_CTL0_4 (RW) + * + * bypass hs_rx_voffcal_en + */ +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_4_MASK (0x10U) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_4_SHIFT (4U) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_4_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_4_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_4_MASK) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_4_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_4_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_4_SHIFT) + +/* + * CSI_CTL0_3 (RW) + * + * hs_rx_voffcal_trim_polar + */ +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_3_MASK (0x8U) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_3_SHIFT (3U) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_3_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_3_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_3_MASK) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_3_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_3_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_3_SHIFT) + +/* + * CSI_CTL0_2 (RW) + * + * ulprx_lpen + */ +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_2_MASK (0x4U) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_2_SHIFT (2U) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_2_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_2_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_2_MASK) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_2_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_2_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_2_SHIFT) + +/* + * CSI_CTL0_1 (RW) + * + * force data lane-n and clock lane lp/ulprx to be normal operation + */ +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_1_MASK (0x2U) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_1_SHIFT (1U) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_1_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_1_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_1_MASK) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_1_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_1_SHIFT) + +/* + * CSI_CTL0_0 (RW) + * + * force data lane-n and clock lane hs-rx to be normal operation + */ +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_0_MASK (0x1U) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_0_SHIFT (0U) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_0_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_0_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_0_MASK) +#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_0_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_0_SHIFT) + +/* Bitfield definition for register: CSI_CTL23 */ +/* + * CSI_CTL3_3 (RW) + * + * data lane-1 skew trimming enable + */ +#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_3_MASK (0x10000000UL) +#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_3_SHIFT (28U) +#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_3_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_3_SHIFT) & MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_3_MASK) +#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_3_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_3_MASK) >> MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_3_SHIFT) + +/* + * CSI_CTL3_2 (RW) + * + * data lane-1 hs-rx skew adjust with binary code + */ +#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_2_MASK (0xF000000UL) +#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_2_SHIFT (24U) +#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_2_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_2_SHIFT) & MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_2_MASK) +#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_2_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_2_MASK) >> MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_2_SHIFT) + +/* + * CSI_CTL3_1 (RW) + * + * data lane-0 skew trimming enable + */ +#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_1_MASK (0x100000UL) +#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_1_SHIFT (20U) +#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_1_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_1_SHIFT) & MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_1_MASK) +#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_1_MASK) >> MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_1_SHIFT) + +/* + * CSI_CTL3_0 (RW) + * + * data lane-0 hs-rx skew adjust with binary code + */ +#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_0_MASK (0xF0000UL) +#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_0_SHIFT (16U) +#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_0_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_0_SHIFT) & MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_0_MASK) +#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_0_MASK) >> MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_0_SHIFT) + +/* Bitfield definition for register: CSI_VINIT */ +/* + * CSI_LPRX_VREF_TRIM (RW) + * + * pt ft indicator in csi clk data lane + */ +#define MIPI_CSI_PHY_CSI_VINIT_CSI_LPRX_VREF_TRIM_MASK (0xF00000UL) +#define MIPI_CSI_PHY_CSI_VINIT_CSI_LPRX_VREF_TRIM_SHIFT (20U) +#define MIPI_CSI_PHY_CSI_VINIT_CSI_LPRX_VREF_TRIM_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_VINIT_CSI_LPRX_VREF_TRIM_SHIFT) & MIPI_CSI_PHY_CSI_VINIT_CSI_LPRX_VREF_TRIM_MASK) +#define MIPI_CSI_PHY_CSI_VINIT_CSI_LPRX_VREF_TRIM_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_VINIT_CSI_LPRX_VREF_TRIM_MASK) >> MIPI_CSI_PHY_CSI_VINIT_CSI_LPRX_VREF_TRIM_SHIFT) + +/* + * CSI_CLK_LPRX_VINT (RO) + * + * pt ft indicator in csi clk lane + */ +#define MIPI_CSI_PHY_CSI_VINIT_CSI_CLK_LPRX_VINT_MASK (0xF0000UL) +#define MIPI_CSI_PHY_CSI_VINIT_CSI_CLK_LPRX_VINT_SHIFT (16U) +#define MIPI_CSI_PHY_CSI_VINIT_CSI_CLK_LPRX_VINT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_VINIT_CSI_CLK_LPRX_VINT_MASK) >> MIPI_CSI_PHY_CSI_VINIT_CSI_CLK_LPRX_VINT_SHIFT) + +/* + * CSI_1_LPRX_VINIT (RO) + * + * pt ft indicator in csi lane-1 + */ +#define MIPI_CSI_PHY_CSI_VINIT_CSI_1_LPRX_VINIT_MASK (0xF0U) +#define MIPI_CSI_PHY_CSI_VINIT_CSI_1_LPRX_VINIT_SHIFT (4U) +#define MIPI_CSI_PHY_CSI_VINIT_CSI_1_LPRX_VINIT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_VINIT_CSI_1_LPRX_VINIT_MASK) >> MIPI_CSI_PHY_CSI_VINIT_CSI_1_LPRX_VINIT_SHIFT) + +/* + * CSI_0_LPRX_VINIT (RO) + * + * pt ft indicator in csi lane-0 + */ +#define MIPI_CSI_PHY_CSI_VINIT_CSI_0_LPRX_VINIT_MASK (0xFU) +#define MIPI_CSI_PHY_CSI_VINIT_CSI_0_LPRX_VINIT_SHIFT (0U) +#define MIPI_CSI_PHY_CSI_VINIT_CSI_0_LPRX_VINIT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_VINIT_CSI_0_LPRX_VINIT_MASK) >> MIPI_CSI_PHY_CSI_VINIT_CSI_0_LPRX_VINIT_SHIFT) + +/* Bitfield definition for register: CLANE_PARA */ +/* + * T_CLK_TERMEN (RW) + * + * time for the clock lane receiver to enable the HS line termination + */ +#define MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_MASK (0xFF00U) +#define MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_SHIFT (8U) +#define MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_SHIFT) & MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_MASK) +#define MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_MASK) >> MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_SHIFT) + +/* + * T_CLK_SETTLE (RW) + * + * the value of tclk-settle of clklane + */ +#define MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_MASK (0xFFU) +#define MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_SHIFT (0U) +#define MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_SHIFT) & MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_MASK) +#define MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_MASK) >> MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_SHIFT) + +/* Bitfield definition for register: T_HS_TERMEN */ +/* + * T_D1_TERMEN (RW) + * + * the value of ths-termen of datalane1 + */ +#define MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_MASK (0xFF00U) +#define MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_SHIFT (8U) +#define MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_SHIFT) & MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_MASK) +#define MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_MASK) >> MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_SHIFT) + +/* + * T_D0_TERMEN (RW) + * + * the value of ths-termen of datalane0 + */ +#define MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_MASK (0xFFU) +#define MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_SHIFT (0U) +#define MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_SHIFT) & MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_MASK) +#define MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_MASK) >> MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_SHIFT) + +/* Bitfield definition for register: T_HS_SETTLE */ +/* + * T_D1_SETTLE (RW) + * + * the value of ths-settle of data lane1 + */ +#define MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_MASK (0xFF00U) +#define MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_SHIFT (8U) +#define MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_SHIFT) & MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_MASK) +#define MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_MASK) >> MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_SHIFT) + +/* + * T_D0_SETTLE (RW) + * + * the value of ths-settle of data lane0 + */ +#define MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_MASK (0xFFU) +#define MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_SHIFT (0U) +#define MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_SHIFT) & MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_MASK) +#define MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_MASK) >> MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_SHIFT) + +/* Bitfield definition for register: T_CLANE_INIT */ +/* + * T_CLK_INIT (RW) + * + * initialization time of lock lane + */ +#define MIPI_CSI_PHY_T_CLANE_INIT_T_CLK_INIT_MASK (0xFFFFFFUL) +#define MIPI_CSI_PHY_T_CLANE_INIT_T_CLK_INIT_SHIFT (0U) +#define MIPI_CSI_PHY_T_CLANE_INIT_T_CLK_INIT_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_T_CLANE_INIT_T_CLK_INIT_SHIFT) & MIPI_CSI_PHY_T_CLANE_INIT_T_CLK_INIT_MASK) +#define MIPI_CSI_PHY_T_CLANE_INIT_T_CLK_INIT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_T_CLANE_INIT_T_CLK_INIT_MASK) >> MIPI_CSI_PHY_T_CLANE_INIT_T_CLK_INIT_SHIFT) + +/* Bitfield definition for register: T_LANE_INIT0 */ +/* + * T_D0_INIT (RW) + * + * initialization time of data lane + */ +#define MIPI_CSI_PHY_T_LANE_INIT0_T_D0_INIT_MASK (0xFFFFFFUL) +#define MIPI_CSI_PHY_T_LANE_INIT0_T_D0_INIT_SHIFT (0U) +#define MIPI_CSI_PHY_T_LANE_INIT0_T_D0_INIT_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_T_LANE_INIT0_T_D0_INIT_SHIFT) & MIPI_CSI_PHY_T_LANE_INIT0_T_D0_INIT_MASK) +#define MIPI_CSI_PHY_T_LANE_INIT0_T_D0_INIT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_T_LANE_INIT0_T_D0_INIT_MASK) >> MIPI_CSI_PHY_T_LANE_INIT0_T_D0_INIT_SHIFT) + +/* Bitfield definition for register: T_LANE_INIT1 */ +/* + * T_D1_INIT (RW) + * + * initialization time of data lane + */ +#define MIPI_CSI_PHY_T_LANE_INIT1_T_D1_INIT_MASK (0xFFFFFFUL) +#define MIPI_CSI_PHY_T_LANE_INIT1_T_D1_INIT_SHIFT (0U) +#define MIPI_CSI_PHY_T_LANE_INIT1_T_D1_INIT_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_T_LANE_INIT1_T_D1_INIT_SHIFT) & MIPI_CSI_PHY_T_LANE_INIT1_T_D1_INIT_MASK) +#define MIPI_CSI_PHY_T_LANE_INIT1_T_D1_INIT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_T_LANE_INIT1_T_D1_INIT_MASK) >> MIPI_CSI_PHY_T_LANE_INIT1_T_D1_INIT_SHIFT) + +/* Bitfield definition for register: TLPX_CTRL */ +/* + * EN_TLPX_CHECK (RW) + * + * enable the tlpx width check + */ +#define MIPI_CSI_PHY_TLPX_CTRL_EN_TLPX_CHECK_MASK (0x100U) +#define MIPI_CSI_PHY_TLPX_CTRL_EN_TLPX_CHECK_SHIFT (8U) +#define MIPI_CSI_PHY_TLPX_CTRL_EN_TLPX_CHECK_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_TLPX_CTRL_EN_TLPX_CHECK_SHIFT) & MIPI_CSI_PHY_TLPX_CTRL_EN_TLPX_CHECK_MASK) +#define MIPI_CSI_PHY_TLPX_CTRL_EN_TLPX_CHECK_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_TLPX_CTRL_EN_TLPX_CHECK_MASK) >> MIPI_CSI_PHY_TLPX_CTRL_EN_TLPX_CHECK_SHIFT) + +/* + * TLPX (RW) + * + * the width of tlpx + */ +#define MIPI_CSI_PHY_TLPX_CTRL_TLPX_MASK (0xFFU) +#define MIPI_CSI_PHY_TLPX_CTRL_TLPX_SHIFT (0U) +#define MIPI_CSI_PHY_TLPX_CTRL_TLPX_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_TLPX_CTRL_TLPX_SHIFT) & MIPI_CSI_PHY_TLPX_CTRL_TLPX_MASK) +#define MIPI_CSI_PHY_TLPX_CTRL_TLPX_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_TLPX_CTRL_TLPX_MASK) >> MIPI_CSI_PHY_TLPX_CTRL_TLPX_SHIFT) + +/* Bitfield definition for register: NE_SWAP */ +/* + * DPDN_SWAP_LANE1 (RW) + * + * datalane1 dpdn swap + */ +#define MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LANE1_MASK (0x200U) +#define MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LANE1_SHIFT (9U) +#define MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LANE1_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LANE1_SHIFT) & MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LANE1_MASK) +#define MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LANE1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LANE1_MASK) >> MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LANE1_SHIFT) + +/* + * DPDN_SWAP_LAN0 (RW) + * + * datalane0 dpdn swap + */ +#define MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LAN0_MASK (0x100U) +#define MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LAN0_SHIFT (8U) +#define MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LAN0_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LAN0_SHIFT) & MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LAN0_MASK) +#define MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LAN0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LAN0_MASK) >> MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LAN0_SHIFT) + +/* + * LANE_SWAP_LAN1 (RW) + * + * data lane1 swap + */ +#define MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LAN1_MASK (0xCU) +#define MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LAN1_SHIFT (2U) +#define MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LAN1_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LAN1_SHIFT) & MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LAN1_MASK) +#define MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LAN1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LAN1_MASK) >> MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LAN1_SHIFT) + +/* + * LANE_SWAP_LANE0 (RW) + * + * data lane0 swap + */ +#define MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LANE0_MASK (0x3U) +#define MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LANE0_SHIFT (0U) +#define MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LANE0_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LANE0_SHIFT) & MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LANE0_MASK) +#define MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LANE0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LANE0_MASK) >> MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LANE0_SHIFT) + +/* Bitfield definition for register: MISC_INFO */ +/* + * ULPS_LP10_SEL (RW) + * + * the lp10 select signal in ulps_exit state + */ +#define MIPI_CSI_PHY_MISC_INFO_ULPS_LP10_SEL_MASK (0x2U) +#define MIPI_CSI_PHY_MISC_INFO_ULPS_LP10_SEL_SHIFT (1U) +#define MIPI_CSI_PHY_MISC_INFO_ULPS_LP10_SEL_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_MISC_INFO_ULPS_LP10_SEL_SHIFT) & MIPI_CSI_PHY_MISC_INFO_ULPS_LP10_SEL_MASK) +#define MIPI_CSI_PHY_MISC_INFO_ULPS_LP10_SEL_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_MISC_INFO_ULPS_LP10_SEL_MASK) >> MIPI_CSI_PHY_MISC_INFO_ULPS_LP10_SEL_SHIFT) + +/* + * LONG_SOTSYNC_EN (RW) + * + * at least six zero is checked before sot swquence "00011101" + */ +#define MIPI_CSI_PHY_MISC_INFO_LONG_SOTSYNC_EN_MASK (0x1U) +#define MIPI_CSI_PHY_MISC_INFO_LONG_SOTSYNC_EN_SHIFT (0U) +#define MIPI_CSI_PHY_MISC_INFO_LONG_SOTSYNC_EN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_MISC_INFO_LONG_SOTSYNC_EN_SHIFT) & MIPI_CSI_PHY_MISC_INFO_LONG_SOTSYNC_EN_MASK) +#define MIPI_CSI_PHY_MISC_INFO_LONG_SOTSYNC_EN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_MISC_INFO_LONG_SOTSYNC_EN_MASK) >> MIPI_CSI_PHY_MISC_INFO_LONG_SOTSYNC_EN_SHIFT) + +/* Bitfield definition for register: BIST_TEST0 */ +/* + * BIST_DONE_LAN1 (RO) + * + * bist_done of lane1 + */ +#define MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN1_MASK (0x80U) +#define MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN1_SHIFT (7U) +#define MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN1_MASK) >> MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN1_SHIFT) + +/* + * BIST_DONE_LAN0 (RO) + * + * bist_done of lane0 + */ +#define MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN0_MASK (0x40U) +#define MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN0_SHIFT (6U) +#define MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN0_MASK) >> MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN0_SHIFT) + +/* + * BIST_OK_LANE1 (RO) + * + * bist_ok of lane1 + */ +#define MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE1_MASK (0x8U) +#define MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE1_SHIFT (3U) +#define MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE1_MASK) >> MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE1_SHIFT) + +/* + * BIST_OK_LANE0 (RO) + * + * bist_ok of lane0 + */ +#define MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE0_MASK (0x4U) +#define MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE0_SHIFT (2U) +#define MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE0_MASK) >> MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE0_SHIFT) + +/* + * BIST_EN_SEL (RW) + * + * the source of bist_en sel + */ +#define MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SEL_MASK (0x2U) +#define MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SEL_SHIFT (1U) +#define MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SEL_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SEL_SHIFT) & MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SEL_MASK) +#define MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SEL_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SEL_MASK) >> MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SEL_SHIFT) + +/* + * BIST_EN_SOFT (RW) + * + * enable prbs bist test + */ +#define MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SOFT_MASK (0x1U) +#define MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SOFT_SHIFT (0U) +#define MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SOFT_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SOFT_SHIFT) & MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SOFT_MASK) +#define MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SOFT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SOFT_MASK) >> MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SOFT_SHIFT) + +/* Bitfield definition for register: BIST_TEST1 */ +/* + * PRBS_CHECK_NUM (RW) + * + * the byte num of prbs bist check num + */ +#define MIPI_CSI_PHY_BIST_TEST1_PRBS_CHECK_NUM_MASK (0xFFFFFFFFUL) +#define MIPI_CSI_PHY_BIST_TEST1_PRBS_CHECK_NUM_SHIFT (0U) +#define MIPI_CSI_PHY_BIST_TEST1_PRBS_CHECK_NUM_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_BIST_TEST1_PRBS_CHECK_NUM_SHIFT) & MIPI_CSI_PHY_BIST_TEST1_PRBS_CHECK_NUM_MASK) +#define MIPI_CSI_PHY_BIST_TEST1_PRBS_CHECK_NUM_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST1_PRBS_CHECK_NUM_MASK) >> MIPI_CSI_PHY_BIST_TEST1_PRBS_CHECK_NUM_SHIFT) + +/* Bitfield definition for register: BIST_TEST2 */ +/* + * PRBS_SEED (RW) + * + * the seed of prbs7 + */ +#define MIPI_CSI_PHY_BIST_TEST2_PRBS_SEED_MASK (0xFF0000UL) +#define MIPI_CSI_PHY_BIST_TEST2_PRBS_SEED_SHIFT (16U) +#define MIPI_CSI_PHY_BIST_TEST2_PRBS_SEED_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_BIST_TEST2_PRBS_SEED_SHIFT) & MIPI_CSI_PHY_BIST_TEST2_PRBS_SEED_MASK) +#define MIPI_CSI_PHY_BIST_TEST2_PRBS_SEED_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST2_PRBS_SEED_MASK) >> MIPI_CSI_PHY_BIST_TEST2_PRBS_SEED_SHIFT) + +/* + * PRBS_ERR_THRESHOLD (RW) + * + * the threshold of prbs bist error + */ +#define MIPI_CSI_PHY_BIST_TEST2_PRBS_ERR_THRESHOLD_MASK (0xFFFFU) +#define MIPI_CSI_PHY_BIST_TEST2_PRBS_ERR_THRESHOLD_SHIFT (0U) +#define MIPI_CSI_PHY_BIST_TEST2_PRBS_ERR_THRESHOLD_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_BIST_TEST2_PRBS_ERR_THRESHOLD_SHIFT) & MIPI_CSI_PHY_BIST_TEST2_PRBS_ERR_THRESHOLD_MASK) +#define MIPI_CSI_PHY_BIST_TEST2_PRBS_ERR_THRESHOLD_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST2_PRBS_ERR_THRESHOLD_MASK) >> MIPI_CSI_PHY_BIST_TEST2_PRBS_ERR_THRESHOLD_SHIFT) + +/* Bitfield definition for register: BIST_TEST3 */ +/* + * PRBS_ERR_NUM_LAN1 (RO) + * + * the byte num of mismatch data of data lane1 in bist mode + */ +#define MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN1_MASK (0xFFFF0000UL) +#define MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN1_SHIFT (16U) +#define MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN1_MASK) >> MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN1_SHIFT) + +/* + * PRBS_ERR_NUM_LAN0 (RO) + * + * the byte num of mismatch data of data lane0 in bist mode + */ +#define MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN0_MASK (0xFFFFU) +#define MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN0_SHIFT (0U) +#define MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN0_MASK) >> MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN0_SHIFT) + +/* Bitfield definition for register: BURN_IN_TEST0 */ +/* + * BURN_IN_OK_CLAN (RO) + * + * burn_in_ok of clock lane + */ +#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_CLAN_MASK (0x40U) +#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_CLAN_SHIFT (6U) +#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_CLAN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_CLAN_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_CLAN_SHIFT) + +/* + * BURN_IN_OK_LAN1 (RO) + * + * burn_in_ok of lane1 + */ +#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN1_MASK (0x8U) +#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN1_SHIFT (3U) +#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN1_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN1_SHIFT) + +/* + * BURN_IN_OK_LAN0 (RO) + * + * burn_in_ok of lane0 + */ +#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN0_MASK (0x4U) +#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN0_SHIFT (2U) +#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN0_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN0_SHIFT) + +/* + * BURN_IN_EN_SEL (RW) + * + * the source of prbs burn_in_en sel + */ +#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SEL_MASK (0x2U) +#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SEL_SHIFT (1U) +#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SEL_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SEL_SHIFT) & MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SEL_MASK) +#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SEL_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SEL_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SEL_SHIFT) + +/* + * BURN_IN_EN_SOFT (RW) + * + * enable prbs burn_in test + */ +#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SOFT_MASK (0x1U) +#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SOFT_SHIFT (0U) +#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SOFT_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SOFT_SHIFT) & MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SOFT_MASK) +#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SOFT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SOFT_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SOFT_SHIFT) + +/* Bitfield definition for register: BURN_IN_TEST1 */ +/* + * BURN_IN_SEED (RW) + * + * the seed of prbs7 for brun-in test + */ +#define MIPI_CSI_PHY_BURN_IN_TEST1_BURN_IN_SEED_MASK (0xFFU) +#define MIPI_CSI_PHY_BURN_IN_TEST1_BURN_IN_SEED_SHIFT (0U) +#define MIPI_CSI_PHY_BURN_IN_TEST1_BURN_IN_SEED_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_BURN_IN_TEST1_BURN_IN_SEED_SHIFT) & MIPI_CSI_PHY_BURN_IN_TEST1_BURN_IN_SEED_MASK) +#define MIPI_CSI_PHY_BURN_IN_TEST1_BURN_IN_SEED_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST1_BURN_IN_SEED_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST1_BURN_IN_SEED_SHIFT) + +/* Bitfield definition for register: BURN_IN_TEST2 */ +/* + * BURN_IN_ERR_NUM_LAN1 (RO) + * + * the bit num of mismatch data on data lan1 in burn-in mode + */ +#define MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN1_MASK (0xFFFF0000UL) +#define MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN1_SHIFT (16U) +#define MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN1_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN1_SHIFT) + +/* + * BURN_IN_ERR_NUM_LAN0 (RO) + * + * the bit num of mismatch data on data lan0 in burn-in mode + */ +#define MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN0_MASK (0xFFFFU) +#define MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN0_SHIFT (0U) +#define MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN0_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN0_SHIFT) + +/* Bitfield definition for register: BURN_IN_TEST4 */ +/* + * BURN_IN_ERR_NUM_CLAN (RO) + * + * the bit num of mismatch data on clock lane in burn-in mode + */ +#define MIPI_CSI_PHY_BURN_IN_TEST4_BURN_IN_ERR_NUM_CLAN_MASK (0xFFFFU) +#define MIPI_CSI_PHY_BURN_IN_TEST4_BURN_IN_ERR_NUM_CLAN_SHIFT (0U) +#define MIPI_CSI_PHY_BURN_IN_TEST4_BURN_IN_ERR_NUM_CLAN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST4_BURN_IN_ERR_NUM_CLAN_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST4_BURN_IN_ERR_NUM_CLAN_SHIFT) + +/* Bitfield definition for register: BURN_IN_TEST5 */ +/* + * BURN_IN_CHECK_NUM_LAN0 (RO) + * + * the checked bit num of lane0 + */ +#define MIPI_CSI_PHY_BURN_IN_TEST5_BURN_IN_CHECK_NUM_LAN0_MASK (0xFFFFFFFFUL) +#define MIPI_CSI_PHY_BURN_IN_TEST5_BURN_IN_CHECK_NUM_LAN0_SHIFT (0U) +#define MIPI_CSI_PHY_BURN_IN_TEST5_BURN_IN_CHECK_NUM_LAN0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST5_BURN_IN_CHECK_NUM_LAN0_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST5_BURN_IN_CHECK_NUM_LAN0_SHIFT) + +/* Bitfield definition for register: BURN_IN_TEST6 */ +/* + * BURN_IN_CHECKED_NUM_LAN1 (RO) + * + * the checked bit num of lane1 + */ +#define MIPI_CSI_PHY_BURN_IN_TEST6_BURN_IN_CHECKED_NUM_LAN1_MASK (0xFFFFFFFFUL) +#define MIPI_CSI_PHY_BURN_IN_TEST6_BURN_IN_CHECKED_NUM_LAN1_SHIFT (0U) +#define MIPI_CSI_PHY_BURN_IN_TEST6_BURN_IN_CHECKED_NUM_LAN1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST6_BURN_IN_CHECKED_NUM_LAN1_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST6_BURN_IN_CHECKED_NUM_LAN1_SHIFT) + +/* Bitfield definition for register: BURN_IN_TEST9 */ +/* + * BURN_IN_CHECK_NUM_CLAN (RO) + * + * the checked bit num of clock lane + */ +#define MIPI_CSI_PHY_BURN_IN_TEST9_BURN_IN_CHECK_NUM_CLAN_MASK (0xFFFFFFFFUL) +#define MIPI_CSI_PHY_BURN_IN_TEST9_BURN_IN_CHECK_NUM_CLAN_SHIFT (0U) +#define MIPI_CSI_PHY_BURN_IN_TEST9_BURN_IN_CHECK_NUM_CLAN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST9_BURN_IN_CHECK_NUM_CLAN_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST9_BURN_IN_CHECK_NUM_CLAN_SHIFT) + +/* Bitfield definition for register: DEBUG_INFO */ +/* + * DEBUG_MODE_SEL (RW) + * + * the debug bus sel + */ +#define MIPI_CSI_PHY_DEBUG_INFO_DEBUG_MODE_SEL_MASK (0x3F0000UL) +#define MIPI_CSI_PHY_DEBUG_INFO_DEBUG_MODE_SEL_SHIFT (16U) +#define MIPI_CSI_PHY_DEBUG_INFO_DEBUG_MODE_SEL_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_DEBUG_INFO_DEBUG_MODE_SEL_SHIFT) & MIPI_CSI_PHY_DEBUG_INFO_DEBUG_MODE_SEL_MASK) +#define MIPI_CSI_PHY_DEBUG_INFO_DEBUG_MODE_SEL_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_DEBUG_INFO_DEBUG_MODE_SEL_MASK) >> MIPI_CSI_PHY_DEBUG_INFO_DEBUG_MODE_SEL_SHIFT) + +/* Bitfield definition for register: DEBUG_CFG_REG0 */ +/* + * DEBUG_CFG_REG0 (RW) + * + * debug config register0 + */ +#define MIPI_CSI_PHY_DEBUG_CFG_REG0_DEBUG_CFG_REG0_MASK (0xFFFFFFFFUL) +#define MIPI_CSI_PHY_DEBUG_CFG_REG0_DEBUG_CFG_REG0_SHIFT (0U) +#define MIPI_CSI_PHY_DEBUG_CFG_REG0_DEBUG_CFG_REG0_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_DEBUG_CFG_REG0_DEBUG_CFG_REG0_SHIFT) & MIPI_CSI_PHY_DEBUG_CFG_REG0_DEBUG_CFG_REG0_MASK) +#define MIPI_CSI_PHY_DEBUG_CFG_REG0_DEBUG_CFG_REG0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_DEBUG_CFG_REG0_DEBUG_CFG_REG0_MASK) >> MIPI_CSI_PHY_DEBUG_CFG_REG0_DEBUG_CFG_REG0_SHIFT) + +/* Bitfield definition for register: DEBUG_CFG_REG1 */ +/* + * DEBUG_CFG_REG1 (RW) + * + * debug config register1 + */ +#define MIPI_CSI_PHY_DEBUG_CFG_REG1_DEBUG_CFG_REG1_MASK (0xFFFFFFFFUL) +#define MIPI_CSI_PHY_DEBUG_CFG_REG1_DEBUG_CFG_REG1_SHIFT (0U) +#define MIPI_CSI_PHY_DEBUG_CFG_REG1_DEBUG_CFG_REG1_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_DEBUG_CFG_REG1_DEBUG_CFG_REG1_SHIFT) & MIPI_CSI_PHY_DEBUG_CFG_REG1_DEBUG_CFG_REG1_MASK) +#define MIPI_CSI_PHY_DEBUG_CFG_REG1_DEBUG_CFG_REG1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_DEBUG_CFG_REG1_DEBUG_CFG_REG1_MASK) >> MIPI_CSI_PHY_DEBUG_CFG_REG1_DEBUG_CFG_REG1_SHIFT) + +/* Bitfield definition for register: DEBUG_CFG_REG2 */ +/* + * DEBUG_CFG_REG2 (RW) + * + * debug config register2 + */ +#define MIPI_CSI_PHY_DEBUG_CFG_REG2_DEBUG_CFG_REG2_MASK (0xFFFFFFFFUL) +#define MIPI_CSI_PHY_DEBUG_CFG_REG2_DEBUG_CFG_REG2_SHIFT (0U) +#define MIPI_CSI_PHY_DEBUG_CFG_REG2_DEBUG_CFG_REG2_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_DEBUG_CFG_REG2_DEBUG_CFG_REG2_SHIFT) & MIPI_CSI_PHY_DEBUG_CFG_REG2_DEBUG_CFG_REG2_MASK) +#define MIPI_CSI_PHY_DEBUG_CFG_REG2_DEBUG_CFG_REG2_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_DEBUG_CFG_REG2_DEBUG_CFG_REG2_MASK) >> MIPI_CSI_PHY_DEBUG_CFG_REG2_DEBUG_CFG_REG2_SHIFT) + +/* Bitfield definition for register: DEBUG_CFG_REG3 */ +/* + * DEBUG_CFG_REG3 (RW) + * + * debug config register3 + */ +#define MIPI_CSI_PHY_DEBUG_CFG_REG3_DEBUG_CFG_REG3_MASK (0xFFFFFFFFUL) +#define MIPI_CSI_PHY_DEBUG_CFG_REG3_DEBUG_CFG_REG3_SHIFT (0U) +#define MIPI_CSI_PHY_DEBUG_CFG_REG3_DEBUG_CFG_REG3_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_DEBUG_CFG_REG3_DEBUG_CFG_REG3_SHIFT) & MIPI_CSI_PHY_DEBUG_CFG_REG3_DEBUG_CFG_REG3_MASK) +#define MIPI_CSI_PHY_DEBUG_CFG_REG3_DEBUG_CFG_REG3_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_DEBUG_CFG_REG3_DEBUG_CFG_REG3_MASK) >> MIPI_CSI_PHY_DEBUG_CFG_REG3_DEBUG_CFG_REG3_SHIFT) + +/* Bitfield definition for register: DEBUG_CFG_REG4 */ +/* + * DEBUG_CFG_REG4 (RW) + * + * debug config register4 + */ +#define MIPI_CSI_PHY_DEBUG_CFG_REG4_DEBUG_CFG_REG4_MASK (0xFFFFFFFFUL) +#define MIPI_CSI_PHY_DEBUG_CFG_REG4_DEBUG_CFG_REG4_SHIFT (0U) +#define MIPI_CSI_PHY_DEBUG_CFG_REG4_DEBUG_CFG_REG4_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_DEBUG_CFG_REG4_DEBUG_CFG_REG4_SHIFT) & MIPI_CSI_PHY_DEBUG_CFG_REG4_DEBUG_CFG_REG4_MASK) +#define MIPI_CSI_PHY_DEBUG_CFG_REG4_DEBUG_CFG_REG4_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_DEBUG_CFG_REG4_DEBUG_CFG_REG4_MASK) >> MIPI_CSI_PHY_DEBUG_CFG_REG4_DEBUG_CFG_REG4_SHIFT) + +/* Bitfield definition for register: DEBUG_CFG_REG5 */ +/* + * DEBUG_CFG_REG5 (RW) + * + * debug config register5 + */ +#define MIPI_CSI_PHY_DEBUG_CFG_REG5_DEBUG_CFG_REG5_MASK (0xFFFFFFFFUL) +#define MIPI_CSI_PHY_DEBUG_CFG_REG5_DEBUG_CFG_REG5_SHIFT (0U) +#define MIPI_CSI_PHY_DEBUG_CFG_REG5_DEBUG_CFG_REG5_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_DEBUG_CFG_REG5_DEBUG_CFG_REG5_SHIFT) & MIPI_CSI_PHY_DEBUG_CFG_REG5_DEBUG_CFG_REG5_MASK) +#define MIPI_CSI_PHY_DEBUG_CFG_REG5_DEBUG_CFG_REG5_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_DEBUG_CFG_REG5_DEBUG_CFG_REG5_MASK) >> MIPI_CSI_PHY_DEBUG_CFG_REG5_DEBUG_CFG_REG5_SHIFT) + + + + +#endif /* HPM_MIPI_CSI_PHY_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mipi_csi_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mipi_csi_regs.h new file mode 100644 index 00000000000..6d4ceaada86 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mipi_csi_regs.h @@ -0,0 +1,3618 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_MIPI_CSI_H +#define HPM_MIPI_CSI_H + +typedef struct { + __R uint32_t VERSION; /* 0x0: version code */ + __RW uint32_t N_LANES; /* 0x4: the number of active lanes */ + __RW uint32_t CSI2_RESETN; /* 0x8: the internal logic of the controller goes into the reset state when active */ + __R uint32_t INT_ST_MAIN; /* 0xC: contains the stateus of individual interrupt sources */ + __RW uint32_t DATA_IDS_1; /* 0x10: programs data type fields for data ID monitors */ + __RW uint32_t DATA_IDS_2; /* 0x14: programs data type fields for data ID monitors */ + __R uint8_t RESERVED0[20]; /* 0x18 - 0x2B: Reserved */ + __R uint32_t INT_ST_AP_MAIN; /* 0x2C: contains the status of individual interrupt sources */ + __R uint8_t RESERVED1[16]; /* 0x30 - 0x3F: Reserved */ + __RW uint32_t PHY_SHUTDOWNZ; /* 0x40: controls the phy shutdown mode */ + __RW uint32_t DPHY_RSTZ; /* 0x44: controls the phy reset mode */ + __R uint32_t PHY_RX; /* 0x48: contains the status of rx-related signals from phy */ + __R uint32_t PHY_STOPSTATE; /* 0x4C: contains the stopstate signal status from phy */ + __R uint8_t RESERVED2[48]; /* 0x50 - 0x7F: Reserved */ + __RW uint32_t IPI_MODE; /* 0x80: selects how the ipi interface generates the video frame */ + __RW uint32_t IPI_VCID; /* 0x84: selects the vritual channel processed by ipi */ + __RW uint32_t IPI_DATA_TYPE; /* 0x88: selects the data type processed by ipi */ + __RW uint32_t IPI_MEM_FLASH; /* 0x8C: control the flush of ipi memory */ + __RW uint32_t IPI_HSA_TIME; /* 0x90: configures the video horizontal synchronism active time */ + __RW uint32_t IPI_HBP_TIME; /* 0x94: configures the video horizontal synchronism back porch time */ + __RW uint32_t IPI_HSD_TIME; /* 0x98: configures the vedeo Horizontal Sync Delay time */ + __RW uint32_t IPI_HLINE_TIME; /* 0x9C: configures the overall tiem for each video line */ + __RW uint32_t IPI_SOFTRSTN; /* 0xA0: congtrols the ipi logic reset state */ + __R uint8_t RESERVED3[8]; /* 0xA4 - 0xAB: Reserved */ + __RW uint32_t IPI_ADV_FEATURES; /* 0xAC: configures advanced features for ipi mode */ + __RW uint32_t IPI_VSA_LINES; /* 0xB0: configures the vertical synchronism active period */ + __RW uint32_t IPI_VBP_LINES; /* 0xB4: configures the verticall back porch period */ + __RW uint32_t IPI_VFP_LINES; /* 0xB8: configures the vertical front porch period */ + __RW uint32_t IPI_VACTIVE_LINES; /* 0xBC: configures the vertical resolution of video */ + __R uint8_t RESERVED4[8]; /* 0xC0 - 0xC7: Reserved */ + __RW uint32_t VC_EXTENSION; /* 0xC8: active extra bits for virtual channel */ + __R uint32_t PHY_CAL; /* 0xCC: contains the calibration signal status from synopsys d-phy */ + __R uint8_t RESERVED5[16]; /* 0xD0 - 0xDF: Reserved */ + __R uint32_t INT_ST_PHY_FATAL; /* 0xE0: groups the phy interruptions caused by phy packets discarded */ + __RW uint32_t INT_MSK_PHY_FATAL; /* 0xE4: interrupt mask for int_st_phy_fatal */ + __RW uint32_t INT_FORCE_PHY_FATAL; /* 0xE8: interrupt force register for test purposes */ + __R uint8_t RESERVED6[4]; /* 0xEC - 0xEF: Reserved */ + __R uint32_t INT_ST_PKT_FATAL; /* 0xF0: groups the fatal interruption related with packet construction */ + __RW uint32_t INT_MSK_PKT_FATAL; /* 0xF4: interrupt mask for int_st_pkt_fatal */ + __RW uint32_t INT_FORCE_PKT_FATAL; /* 0xF8: interrupt force register is used for test purpos */ + __R uint8_t RESERVED7[20]; /* 0xFC - 0x10F: Reserved */ + __R uint32_t INT_ST_PHY; /* 0x110: interruption caused by phy */ + __RW uint32_t INT_MSK_PHY; /* 0x114: interrupt mask for int_st_phy */ + __RW uint32_t INT_FORCE_PHY; /* 0x118: interrupt force register */ + __R uint8_t RESERVED8[36]; /* 0x11C - 0x13F: Reserved */ + __R uint32_t INT_ST_IPI_FATAL; /* 0x140: fatal interruption caused by ipi interface */ + __RW uint32_t INT_MSK_IPI_FATAL; /* 0x144: interrupt mask for int_st_ipi_fatal */ + __RW uint32_t INT_FORCE_IPI_FATAL; /* 0x148: interrupt force register */ + __R uint8_t RESERVED9[52]; /* 0x14C - 0x17F: Reserved */ + __R uint32_t INT_ST_AP_GENERIC; /* 0x180: groups and notifies which interruption bits caused the interruption */ + __RW uint32_t INT_MSK_AP_GENERIC; /* 0x184: interrupt mask for int_st_ap_generic */ + __RW uint32_t INT_FORCE_AP_GENERIC; /* 0x188: interrupt force register used for test purposes */ + __R uint8_t RESERVED10[4]; /* 0x18C - 0x18F: Reserved */ + __R uint32_t INT_ST_AP_IPI_FATAL; /* 0x190: groups and notifies which interruption bits */ + __R uint32_t INT_MSK_AP_IPI_FATAL; /* 0x194: interrupt mask for int_st_ap_ipi_fatal controls */ + __R uint32_t INT_FORCE_AP_IPI_FATAL; /* 0x198: interrupt force register */ + __R uint8_t RESERVED11[228]; /* 0x19C - 0x27F: Reserved */ + __R uint32_t INT_ST_BNDRY_FRAME_FATAL; /* 0x280: fatal interruption related with matching frame start with frame end for a specific virtual channel */ + __RW uint32_t INT_MSK_BNDRY_FRAME_FATAL; /* 0x284: interrupt mask for int_st_bndry_frame_fatal */ + __RW uint32_t INT_FORCE_BNDRY_FRAME_FATAL; /* 0x288: interrupt force register is used for test purposes */ + __R uint8_t RESERVED12[4]; /* 0x28C - 0x28F: Reserved */ + __R uint32_t INT_ST_SEQ_FRAME_FATAL; /* 0x290: fatal interruption related with matching frame start with frame end for a specific virtual channel */ + __RW uint32_t INT_MSK_SEQ_FRAME_FATAL; /* 0x294: interrupt mask for int_st_seq_frame_fatal */ + __RW uint32_t INT_FORCE_SEQ_FRAME_FATAL; /* 0x298: interrupt force register is used for test purposes */ + __R uint8_t RESERVED13[4]; /* 0x29C - 0x29F: Reserved */ + __R uint32_t INT_ST_CRC_FRAME_FATAL; /* 0x2A0: fatal interruption related with matching frame start with frame end for a specific virtual channel */ + __RW uint32_t INT_MSK_CRC_FRAME_FATAL; /* 0x2A4: interrupt mask for int_st_crc_frame_fatal */ + __RW uint32_t INT_FORCE_CRC_FRAME_FATAL; /* 0x2A8: interrupt force register is used for test purposes */ + __R uint8_t RESERVED14[4]; /* 0x2AC - 0x2AF: Reserved */ + __R uint32_t INT_ST_PLD_CRC_FRAME_FATAL; /* 0x2B0: fatal interruption related with matching frame start with frame end for a specific virtual channel */ + __RW uint32_t INT_MSK_PLD_CRC_FRAME_FATAL; /* 0x2B4: interrupt mask for int_st_crc_frame_fatal */ + __RW uint32_t INT_FORCE_PLD_CRC_FRAME_FATAL; /* 0x2B8: interrupt force register is used for test purposes */ +} MIPI_CSI_Type; + + +/* Bitfield definition for register: VERSION */ +/* + * VERSION (RO) + * + * version code + */ +#define MIPI_CSI_VERSION_VERSION_MASK (0xFFFFFFFFUL) +#define MIPI_CSI_VERSION_VERSION_SHIFT (0U) +#define MIPI_CSI_VERSION_VERSION_GET(x) (((uint32_t)(x) & MIPI_CSI_VERSION_VERSION_MASK) >> MIPI_CSI_VERSION_VERSION_SHIFT) + +/* Bitfield definition for register: N_LANES */ +/* + * N_LANES (RW) + * + * number of active data lanes + */ +#define MIPI_CSI_N_LANES_N_LANES_MASK (0x7U) +#define MIPI_CSI_N_LANES_N_LANES_SHIFT (0U) +#define MIPI_CSI_N_LANES_N_LANES_SET(x) (((uint32_t)(x) << MIPI_CSI_N_LANES_N_LANES_SHIFT) & MIPI_CSI_N_LANES_N_LANES_MASK) +#define MIPI_CSI_N_LANES_N_LANES_GET(x) (((uint32_t)(x) & MIPI_CSI_N_LANES_N_LANES_MASK) >> MIPI_CSI_N_LANES_N_LANES_SHIFT) + +/* Bitfield definition for register: CSI2_RESETN */ +/* + * CSI2_RESETN (RW) + * + * DWC_mipi_csi2_host reset output, active low + */ +#define MIPI_CSI_CSI2_RESETN_CSI2_RESETN_MASK (0x1U) +#define MIPI_CSI_CSI2_RESETN_CSI2_RESETN_SHIFT (0U) +#define MIPI_CSI_CSI2_RESETN_CSI2_RESETN_SET(x) (((uint32_t)(x) << MIPI_CSI_CSI2_RESETN_CSI2_RESETN_SHIFT) & MIPI_CSI_CSI2_RESETN_CSI2_RESETN_MASK) +#define MIPI_CSI_CSI2_RESETN_CSI2_RESETN_GET(x) (((uint32_t)(x) & MIPI_CSI_CSI2_RESETN_CSI2_RESETN_MASK) >> MIPI_CSI_CSI2_RESETN_CSI2_RESETN_SHIFT) + +/* Bitfield definition for register: INT_ST_MAIN */ +/* + * STATUS_INT_IPI4_FATAL (RC) + * + * status of int_st_ipi_fatal + */ +#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_IPI4_FATAL_MASK (0x40000UL) +#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_IPI4_FATAL_SHIFT (18U) +#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_IPI4_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_MAIN_STATUS_INT_IPI4_FATAL_MASK) >> MIPI_CSI_INT_ST_MAIN_STATUS_INT_IPI4_FATAL_SHIFT) + +/* + * STATUS_INT_LINE (RC) + * + * status of int_st_line + */ +#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_LINE_MASK (0x20000UL) +#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_LINE_SHIFT (17U) +#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_LINE_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_MAIN_STATUS_INT_LINE_MASK) >> MIPI_CSI_INT_ST_MAIN_STATUS_INT_LINE_SHIFT) + +/* + * STATUS_INT_PHY (RC) + * + * status of int_st_phy + */ +#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PHY_MASK (0x10000UL) +#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PHY_SHIFT (16U) +#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PHY_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_MAIN_STATUS_INT_PHY_MASK) >> MIPI_CSI_INT_ST_MAIN_STATUS_INT_PHY_SHIFT) + +/* + * STATUS_INT_ECC_CORRECTED (RC) + * + * status of status_int_ecc_corrected + */ +#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_ECC_CORRECTED_MASK (0x80U) +#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_ECC_CORRECTED_SHIFT (7U) +#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_ECC_CORRECTED_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_MAIN_STATUS_INT_ECC_CORRECTED_MASK) >> MIPI_CSI_INT_ST_MAIN_STATUS_INT_ECC_CORRECTED_SHIFT) + +/* + * STATUS_INT_DATA_ID (RC) + * + * status of status_int_data_id + */ +#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_DATA_ID_MASK (0x40U) +#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_DATA_ID_SHIFT (6U) +#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_DATA_ID_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_MAIN_STATUS_INT_DATA_ID_MASK) >> MIPI_CSI_INT_ST_MAIN_STATUS_INT_DATA_ID_SHIFT) + +/* + * STATUS_INT_PLD_CRC_FATAL (RC) + * + * status of status_int_pld_crc_fatal + */ +#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PLD_CRC_FATAL_MASK (0x20U) +#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PLD_CRC_FATAL_SHIFT (5U) +#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PLD_CRC_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_MAIN_STATUS_INT_PLD_CRC_FATAL_MASK) >> MIPI_CSI_INT_ST_MAIN_STATUS_INT_PLD_CRC_FATAL_SHIFT) + +/* + * STATUS_INT_CRC_FRAME_FATAL (RC) + * + * status of status_int_crc_frame_fatal + */ +#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_CRC_FRAME_FATAL_MASK (0x10U) +#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_CRC_FRAME_FATAL_SHIFT (4U) +#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_CRC_FRAME_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_MAIN_STATUS_INT_CRC_FRAME_FATAL_MASK) >> MIPI_CSI_INT_ST_MAIN_STATUS_INT_CRC_FRAME_FATAL_SHIFT) + +/* + * STATUS_INT_SEQ_FRAME_FATAL (RC) + * + * status of status_int_seq_frame_fatal + */ +#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_SEQ_FRAME_FATAL_MASK (0x8U) +#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_SEQ_FRAME_FATAL_SHIFT (3U) +#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_SEQ_FRAME_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_MAIN_STATUS_INT_SEQ_FRAME_FATAL_MASK) >> MIPI_CSI_INT_ST_MAIN_STATUS_INT_SEQ_FRAME_FATAL_SHIFT) + +/* + * STATUS_INT_BNDRY_FRAME_FATAL (RC) + * + * status of int_st_bndry_frame_fatal + */ +#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_BNDRY_FRAME_FATAL_MASK (0x4U) +#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_BNDRY_FRAME_FATAL_SHIFT (2U) +#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_BNDRY_FRAME_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_MAIN_STATUS_INT_BNDRY_FRAME_FATAL_MASK) >> MIPI_CSI_INT_ST_MAIN_STATUS_INT_BNDRY_FRAME_FATAL_SHIFT) + +/* + * STATUS_INT_PKT_FATAL (RC) + * + * status of int_st_pkt_fatal + */ +#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PKT_FATAL_MASK (0x2U) +#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PKT_FATAL_SHIFT (1U) +#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PKT_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_MAIN_STATUS_INT_PKT_FATAL_MASK) >> MIPI_CSI_INT_ST_MAIN_STATUS_INT_PKT_FATAL_SHIFT) + +/* + * STATUS_INT_PHY_FATAL (RC) + * + * status of int_st_phy_fatal + */ +#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PHY_FATAL_MASK (0x1U) +#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PHY_FATAL_SHIFT (0U) +#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PHY_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_MAIN_STATUS_INT_PHY_FATAL_MASK) >> MIPI_CSI_INT_ST_MAIN_STATUS_INT_PHY_FATAL_SHIFT) + +/* Bitfield definition for register: DATA_IDS_1 */ +/* + * DI3_DT (RW) + * + * data type for programmed data ID 3 + */ +#define MIPI_CSI_DATA_IDS_1_DI3_DT_MASK (0x3F000000UL) +#define MIPI_CSI_DATA_IDS_1_DI3_DT_SHIFT (24U) +#define MIPI_CSI_DATA_IDS_1_DI3_DT_SET(x) (((uint32_t)(x) << MIPI_CSI_DATA_IDS_1_DI3_DT_SHIFT) & MIPI_CSI_DATA_IDS_1_DI3_DT_MASK) +#define MIPI_CSI_DATA_IDS_1_DI3_DT_GET(x) (((uint32_t)(x) & MIPI_CSI_DATA_IDS_1_DI3_DT_MASK) >> MIPI_CSI_DATA_IDS_1_DI3_DT_SHIFT) + +/* + * DI2_DT (RW) + * + * data type for programmed data ID 2 + */ +#define MIPI_CSI_DATA_IDS_1_DI2_DT_MASK (0x3F0000UL) +#define MIPI_CSI_DATA_IDS_1_DI2_DT_SHIFT (16U) +#define MIPI_CSI_DATA_IDS_1_DI2_DT_SET(x) (((uint32_t)(x) << MIPI_CSI_DATA_IDS_1_DI2_DT_SHIFT) & MIPI_CSI_DATA_IDS_1_DI2_DT_MASK) +#define MIPI_CSI_DATA_IDS_1_DI2_DT_GET(x) (((uint32_t)(x) & MIPI_CSI_DATA_IDS_1_DI2_DT_MASK) >> MIPI_CSI_DATA_IDS_1_DI2_DT_SHIFT) + +/* + * DI1_DT (RW) + * + * data type for programmed data ID 1 + */ +#define MIPI_CSI_DATA_IDS_1_DI1_DT_MASK (0x3F00U) +#define MIPI_CSI_DATA_IDS_1_DI1_DT_SHIFT (8U) +#define MIPI_CSI_DATA_IDS_1_DI1_DT_SET(x) (((uint32_t)(x) << MIPI_CSI_DATA_IDS_1_DI1_DT_SHIFT) & MIPI_CSI_DATA_IDS_1_DI1_DT_MASK) +#define MIPI_CSI_DATA_IDS_1_DI1_DT_GET(x) (((uint32_t)(x) & MIPI_CSI_DATA_IDS_1_DI1_DT_MASK) >> MIPI_CSI_DATA_IDS_1_DI1_DT_SHIFT) + +/* + * DI0_DT (RW) + * + * data type for programmed data ID 0 + */ +#define MIPI_CSI_DATA_IDS_1_DI0_DT_MASK (0x3FU) +#define MIPI_CSI_DATA_IDS_1_DI0_DT_SHIFT (0U) +#define MIPI_CSI_DATA_IDS_1_DI0_DT_SET(x) (((uint32_t)(x) << MIPI_CSI_DATA_IDS_1_DI0_DT_SHIFT) & MIPI_CSI_DATA_IDS_1_DI0_DT_MASK) +#define MIPI_CSI_DATA_IDS_1_DI0_DT_GET(x) (((uint32_t)(x) & MIPI_CSI_DATA_IDS_1_DI0_DT_MASK) >> MIPI_CSI_DATA_IDS_1_DI0_DT_SHIFT) + +/* Bitfield definition for register: DATA_IDS_2 */ +/* + * DI7_DT (RW) + * + * data type for programmed data ID 7 + */ +#define MIPI_CSI_DATA_IDS_2_DI7_DT_MASK (0x3F000000UL) +#define MIPI_CSI_DATA_IDS_2_DI7_DT_SHIFT (24U) +#define MIPI_CSI_DATA_IDS_2_DI7_DT_SET(x) (((uint32_t)(x) << MIPI_CSI_DATA_IDS_2_DI7_DT_SHIFT) & MIPI_CSI_DATA_IDS_2_DI7_DT_MASK) +#define MIPI_CSI_DATA_IDS_2_DI7_DT_GET(x) (((uint32_t)(x) & MIPI_CSI_DATA_IDS_2_DI7_DT_MASK) >> MIPI_CSI_DATA_IDS_2_DI7_DT_SHIFT) + +/* + * DI6_DT (RW) + * + * data type for programmed data ID 6 + */ +#define MIPI_CSI_DATA_IDS_2_DI6_DT_MASK (0x3F0000UL) +#define MIPI_CSI_DATA_IDS_2_DI6_DT_SHIFT (16U) +#define MIPI_CSI_DATA_IDS_2_DI6_DT_SET(x) (((uint32_t)(x) << MIPI_CSI_DATA_IDS_2_DI6_DT_SHIFT) & MIPI_CSI_DATA_IDS_2_DI6_DT_MASK) +#define MIPI_CSI_DATA_IDS_2_DI6_DT_GET(x) (((uint32_t)(x) & MIPI_CSI_DATA_IDS_2_DI6_DT_MASK) >> MIPI_CSI_DATA_IDS_2_DI6_DT_SHIFT) + +/* + * DI5_DT (RW) + * + * data type for programmed data ID 5 + */ +#define MIPI_CSI_DATA_IDS_2_DI5_DT_MASK (0x3F00U) +#define MIPI_CSI_DATA_IDS_2_DI5_DT_SHIFT (8U) +#define MIPI_CSI_DATA_IDS_2_DI5_DT_SET(x) (((uint32_t)(x) << MIPI_CSI_DATA_IDS_2_DI5_DT_SHIFT) & MIPI_CSI_DATA_IDS_2_DI5_DT_MASK) +#define MIPI_CSI_DATA_IDS_2_DI5_DT_GET(x) (((uint32_t)(x) & MIPI_CSI_DATA_IDS_2_DI5_DT_MASK) >> MIPI_CSI_DATA_IDS_2_DI5_DT_SHIFT) + +/* + * DI4_DT (RW) + * + * data type for programmed data ID 4 + */ +#define MIPI_CSI_DATA_IDS_2_DI4_DT_MASK (0x3FU) +#define MIPI_CSI_DATA_IDS_2_DI4_DT_SHIFT (0U) +#define MIPI_CSI_DATA_IDS_2_DI4_DT_SET(x) (((uint32_t)(x) << MIPI_CSI_DATA_IDS_2_DI4_DT_SHIFT) & MIPI_CSI_DATA_IDS_2_DI4_DT_MASK) +#define MIPI_CSI_DATA_IDS_2_DI4_DT_GET(x) (((uint32_t)(x) & MIPI_CSI_DATA_IDS_2_DI4_DT_MASK) >> MIPI_CSI_DATA_IDS_2_DI4_DT_SHIFT) + +/* Bitfield definition for register: INT_ST_AP_MAIN */ +/* + * STATUS_INT_IPI_FATAL (RC) + * + * status of int_st_ipi_fatal + */ +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_IPI_FATAL_MASK (0x1000U) +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_IPI_FATAL_SHIFT (12U) +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_IPI_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_IPI_FATAL_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_IPI_FATAL_SHIFT) + +/* + * STATUS_INT_ST_AP_IPI_FATAL (RC) + * + * status of int_st_ap_ipi_fatal + */ +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ST_AP_IPI_FATAL_MASK (0x800U) +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ST_AP_IPI_FATAL_SHIFT (11U) +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ST_AP_IPI_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ST_AP_IPI_FATAL_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ST_AP_IPI_FATAL_SHIFT) + +/* + * STATUS_INT_LINE (RC) + * + * status of int_st_line + */ +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_LINE_MASK (0x400U) +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_LINE_SHIFT (10U) +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_LINE_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_LINE_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_LINE_SHIFT) + +/* + * STATUS_INT_ECC_CORRECTED (RC) + * + * status of status_int_ecc_corrected + */ +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ECC_CORRECTED_MASK (0x200U) +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ECC_CORRECTED_SHIFT (9U) +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ECC_CORRECTED_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ECC_CORRECTED_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ECC_CORRECTED_SHIFT) + +/* + * STATUS_INT_DATA_ID (RC) + * + * status of status_int_data_id + */ +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_DATA_ID_MASK (0x100U) +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_DATA_ID_SHIFT (8U) +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_DATA_ID_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_DATA_ID_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_DATA_ID_SHIFT) + +/* + * STATUS_INT_PLD_CRC_FATAL (RC) + * + * status of status_int_pld_crc_fatal + */ +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PLD_CRC_FATAL_MASK (0x80U) +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PLD_CRC_FATAL_SHIFT (7U) +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PLD_CRC_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PLD_CRC_FATAL_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PLD_CRC_FATAL_SHIFT) + +/* + * STATUS_INT_PHY (RC) + * + * status of int_st_phy + */ +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PHY_MASK (0x40U) +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PHY_SHIFT (6U) +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PHY_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PHY_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PHY_SHIFT) + +/* + * STATUS_INT_CRC_FRAME_FATAL (RC) + * + * status of status_int_crc_frame_fatal + */ +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_CRC_FRAME_FATAL_MASK (0x20U) +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_CRC_FRAME_FATAL_SHIFT (5U) +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_CRC_FRAME_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_CRC_FRAME_FATAL_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_CRC_FRAME_FATAL_SHIFT) + +/* + * STATUS_INT_SEQ_FRAME_FATAL (RC) + * + * status of status_int_seq_frame_fatal + */ +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_SEQ_FRAME_FATAL_MASK (0x10U) +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_SEQ_FRAME_FATAL_SHIFT (4U) +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_SEQ_FRAME_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_SEQ_FRAME_FATAL_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_SEQ_FRAME_FATAL_SHIFT) + +/* + * STATUS_INT_BNDRY_FRAME_FATAL (RC) + * + * status of int_st_bndry_frame_fatal + */ +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_BNDRY_FRAME_FATAL_MASK (0x8U) +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_BNDRY_FRAME_FATAL_SHIFT (3U) +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_BNDRY_FRAME_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_BNDRY_FRAME_FATAL_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_BNDRY_FRAME_FATAL_SHIFT) + +/* + * STATUS_INT_PKT_FATAL (RC) + * + * status of int_st_pkt_fatal + */ +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PKT_FATAL_MASK (0x4U) +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PKT_FATAL_SHIFT (2U) +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PKT_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PKT_FATAL_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PKT_FATAL_SHIFT) + +/* + * STATUS_INT_PHY_FATAL (RC) + * + * status of int_st_phy_fatal + */ +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PHY_FATAL_MASK (0x2U) +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PHY_FATAL_SHIFT (1U) +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PHY_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PHY_FATAL_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PHY_FATAL_SHIFT) + +/* + * STATUS_INT_ST_AP_GENERIC (RC) + * + * status of int_st_ap_generic + */ +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ST_AP_GENERIC_MASK (0x1U) +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ST_AP_GENERIC_SHIFT (0U) +#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ST_AP_GENERIC_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ST_AP_GENERIC_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ST_AP_GENERIC_SHIFT) + +/* Bitfield definition for register: PHY_SHUTDOWNZ */ +/* + * PHY_SHUTDOWNZ (RW) + * + * shutdown input,active low + */ +#define MIPI_CSI_PHY_SHUTDOWNZ_PHY_SHUTDOWNZ_MASK (0x1U) +#define MIPI_CSI_PHY_SHUTDOWNZ_PHY_SHUTDOWNZ_SHIFT (0U) +#define MIPI_CSI_PHY_SHUTDOWNZ_PHY_SHUTDOWNZ_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_SHUTDOWNZ_PHY_SHUTDOWNZ_SHIFT) & MIPI_CSI_PHY_SHUTDOWNZ_PHY_SHUTDOWNZ_MASK) +#define MIPI_CSI_PHY_SHUTDOWNZ_PHY_SHUTDOWNZ_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_SHUTDOWNZ_PHY_SHUTDOWNZ_MASK) >> MIPI_CSI_PHY_SHUTDOWNZ_PHY_SHUTDOWNZ_SHIFT) + +/* Bitfield definition for register: DPHY_RSTZ */ +/* + * DPHY_RSTZ (RW) + * + * phy reset output, active low + */ +#define MIPI_CSI_DPHY_RSTZ_DPHY_RSTZ_MASK (0x1U) +#define MIPI_CSI_DPHY_RSTZ_DPHY_RSTZ_SHIFT (0U) +#define MIPI_CSI_DPHY_RSTZ_DPHY_RSTZ_SET(x) (((uint32_t)(x) << MIPI_CSI_DPHY_RSTZ_DPHY_RSTZ_SHIFT) & MIPI_CSI_DPHY_RSTZ_DPHY_RSTZ_MASK) +#define MIPI_CSI_DPHY_RSTZ_DPHY_RSTZ_GET(x) (((uint32_t)(x) & MIPI_CSI_DPHY_RSTZ_DPHY_RSTZ_MASK) >> MIPI_CSI_DPHY_RSTZ_DPHY_RSTZ_SHIFT) + +/* Bitfield definition for register: PHY_RX */ +/* + * PHY_RXCLKACTIVEHS (RO) + * + * indicates the d-phy clock lane is actively receiving a ddr clock + */ +#define MIPI_CSI_PHY_RX_PHY_RXCLKACTIVEHS_MASK (0x20000UL) +#define MIPI_CSI_PHY_RX_PHY_RXCLKACTIVEHS_SHIFT (17U) +#define MIPI_CSI_PHY_RX_PHY_RXCLKACTIVEHS_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_RX_PHY_RXCLKACTIVEHS_MASK) >> MIPI_CSI_PHY_RX_PHY_RXCLKACTIVEHS_SHIFT) + +/* + * PHY_RXULPSCLKNOT (RO) + * + * active low. Indicates the d-phy clock lane module has entered the Ultra low power state + */ +#define MIPI_CSI_PHY_RX_PHY_RXULPSCLKNOT_MASK (0x10000UL) +#define MIPI_CSI_PHY_RX_PHY_RXULPSCLKNOT_SHIFT (16U) +#define MIPI_CSI_PHY_RX_PHY_RXULPSCLKNOT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_RX_PHY_RXULPSCLKNOT_MASK) >> MIPI_CSI_PHY_RX_PHY_RXULPSCLKNOT_SHIFT) + +/* + * PHY_RXULLPSESC_1 (RO) + * + * lane module 1 has entered the ultra low power mode + */ +#define MIPI_CSI_PHY_RX_PHY_RXULLPSESC_1_MASK (0x2U) +#define MIPI_CSI_PHY_RX_PHY_RXULLPSESC_1_SHIFT (1U) +#define MIPI_CSI_PHY_RX_PHY_RXULLPSESC_1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_RX_PHY_RXULLPSESC_1_MASK) >> MIPI_CSI_PHY_RX_PHY_RXULLPSESC_1_SHIFT) + +/* + * PHY_RXULPSESC_0 (RO) + * + * lane module 0 has entered the ultra low power mode + */ +#define MIPI_CSI_PHY_RX_PHY_RXULPSESC_0_MASK (0x1U) +#define MIPI_CSI_PHY_RX_PHY_RXULPSESC_0_SHIFT (0U) +#define MIPI_CSI_PHY_RX_PHY_RXULPSESC_0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_RX_PHY_RXULPSESC_0_MASK) >> MIPI_CSI_PHY_RX_PHY_RXULPSESC_0_SHIFT) + +/* Bitfield definition for register: PHY_STOPSTATE */ +/* + * PHY_STOPSTATECLK (RO) + * + * d-phy clock lane in stop state + */ +#define MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATECLK_MASK (0x10000UL) +#define MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATECLK_SHIFT (16U) +#define MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATECLK_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATECLK_MASK) >> MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATECLK_SHIFT) + +/* + * PHY_STOPSTATEDATA_1 (RO) + * + * data lane 1 in stop state + */ +#define MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATEDATA_1_MASK (0x2U) +#define MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATEDATA_1_SHIFT (1U) +#define MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATEDATA_1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATEDATA_1_MASK) >> MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATEDATA_1_SHIFT) + +/* + * PHY_STOPSTATEDATA_0 (RO) + * + * data lane 0 in stop state + */ +#define MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATEDATA_0_MASK (0x1U) +#define MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATEDATA_0_SHIFT (0U) +#define MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATEDATA_0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATEDATA_0_MASK) >> MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATEDATA_0_SHIFT) + +/* Bitfield definition for register: IPI_MODE */ +/* + * IPI_ENABLE (RW) + * + * enables the interface + */ +#define MIPI_CSI_IPI_MODE_IPI_ENABLE_MASK (0x1000000UL) +#define MIPI_CSI_IPI_MODE_IPI_ENABLE_SHIFT (24U) +#define MIPI_CSI_IPI_MODE_IPI_ENABLE_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_MODE_IPI_ENABLE_SHIFT) & MIPI_CSI_IPI_MODE_IPI_ENABLE_MASK) +#define MIPI_CSI_IPI_MODE_IPI_ENABLE_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_MODE_IPI_ENABLE_MASK) >> MIPI_CSI_IPI_MODE_IPI_ENABLE_SHIFT) + +/* + * IPI_CUT_THROUGH (RW) + * + * cut-through mode state active when high + */ +#define MIPI_CSI_IPI_MODE_IPI_CUT_THROUGH_MASK (0x10000UL) +#define MIPI_CSI_IPI_MODE_IPI_CUT_THROUGH_SHIFT (16U) +#define MIPI_CSI_IPI_MODE_IPI_CUT_THROUGH_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_MODE_IPI_CUT_THROUGH_SHIFT) & MIPI_CSI_IPI_MODE_IPI_CUT_THROUGH_MASK) +#define MIPI_CSI_IPI_MODE_IPI_CUT_THROUGH_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_MODE_IPI_CUT_THROUGH_MASK) >> MIPI_CSI_IPI_MODE_IPI_CUT_THROUGH_SHIFT) + +/* + * IPI_COLOR_COM (RW) + * + * if color mode components are deliverd as follows: 0x0 48bit intercase 0x1: 16bit interface + */ +#define MIPI_CSI_IPI_MODE_IPI_COLOR_COM_MASK (0x100U) +#define MIPI_CSI_IPI_MODE_IPI_COLOR_COM_SHIFT (8U) +#define MIPI_CSI_IPI_MODE_IPI_COLOR_COM_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_MODE_IPI_COLOR_COM_SHIFT) & MIPI_CSI_IPI_MODE_IPI_COLOR_COM_MASK) +#define MIPI_CSI_IPI_MODE_IPI_COLOR_COM_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_MODE_IPI_COLOR_COM_MASK) >> MIPI_CSI_IPI_MODE_IPI_COLOR_COM_SHIFT) + +/* + * IPI_MODE (RW) + * + * indicates the video mode transmission type 0x0: camera timing 0x1:controller timing + */ +#define MIPI_CSI_IPI_MODE_IPI_MODE_MASK (0x1U) +#define MIPI_CSI_IPI_MODE_IPI_MODE_SHIFT (0U) +#define MIPI_CSI_IPI_MODE_IPI_MODE_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_MODE_IPI_MODE_SHIFT) & MIPI_CSI_IPI_MODE_IPI_MODE_MASK) +#define MIPI_CSI_IPI_MODE_IPI_MODE_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_MODE_IPI_MODE_MASK) >> MIPI_CSI_IPI_MODE_IPI_MODE_SHIFT) + +/* Bitfield definition for register: IPI_VCID */ +/* + * IPI_VCX_0_1 (RW) + * + * virtual channel extension of data to be processed by pixel interface + */ +#define MIPI_CSI_IPI_VCID_IPI_VCX_0_1_MASK (0xCU) +#define MIPI_CSI_IPI_VCID_IPI_VCX_0_1_SHIFT (2U) +#define MIPI_CSI_IPI_VCID_IPI_VCX_0_1_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_VCID_IPI_VCX_0_1_SHIFT) & MIPI_CSI_IPI_VCID_IPI_VCX_0_1_MASK) +#define MIPI_CSI_IPI_VCID_IPI_VCX_0_1_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_VCID_IPI_VCX_0_1_MASK) >> MIPI_CSI_IPI_VCID_IPI_VCX_0_1_SHIFT) + +/* + * IP_VCID (RW) + * + * virtual channel of data to be processed by pixel interface + */ +#define MIPI_CSI_IPI_VCID_IP_VCID_MASK (0x3U) +#define MIPI_CSI_IPI_VCID_IP_VCID_SHIFT (0U) +#define MIPI_CSI_IPI_VCID_IP_VCID_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_VCID_IP_VCID_SHIFT) & MIPI_CSI_IPI_VCID_IP_VCID_MASK) +#define MIPI_CSI_IPI_VCID_IP_VCID_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_VCID_IP_VCID_MASK) >> MIPI_CSI_IPI_VCID_IP_VCID_SHIFT) + +/* Bitfield definition for register: IPI_DATA_TYPE */ +/* + * EMBENDED_DATA (RW) + * + * enable embedded data processing on ipi interface + */ +#define MIPI_CSI_IPI_DATA_TYPE_EMBENDED_DATA_MASK (0x100U) +#define MIPI_CSI_IPI_DATA_TYPE_EMBENDED_DATA_SHIFT (8U) +#define MIPI_CSI_IPI_DATA_TYPE_EMBENDED_DATA_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_DATA_TYPE_EMBENDED_DATA_SHIFT) & MIPI_CSI_IPI_DATA_TYPE_EMBENDED_DATA_MASK) +#define MIPI_CSI_IPI_DATA_TYPE_EMBENDED_DATA_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_DATA_TYPE_EMBENDED_DATA_MASK) >> MIPI_CSI_IPI_DATA_TYPE_EMBENDED_DATA_SHIFT) + +/* + * IPI_DATA_TYPE (RW) + * + * data type of data to be processed by pixel interface + */ +#define MIPI_CSI_IPI_DATA_TYPE_IPI_DATA_TYPE_MASK (0x3FU) +#define MIPI_CSI_IPI_DATA_TYPE_IPI_DATA_TYPE_SHIFT (0U) +#define MIPI_CSI_IPI_DATA_TYPE_IPI_DATA_TYPE_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_DATA_TYPE_IPI_DATA_TYPE_SHIFT) & MIPI_CSI_IPI_DATA_TYPE_IPI_DATA_TYPE_MASK) +#define MIPI_CSI_IPI_DATA_TYPE_IPI_DATA_TYPE_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_DATA_TYPE_IPI_DATA_TYPE_MASK) >> MIPI_CSI_IPI_DATA_TYPE_IPI_DATA_TYPE_SHIFT) + +/* Bitfield definition for register: IPI_MEM_FLASH */ +/* + * IPI_AUTO_FLUSH (RW) + * + * memory is automatically flashed at each vsync + */ +#define MIPI_CSI_IPI_MEM_FLASH_IPI_AUTO_FLUSH_MASK (0x100U) +#define MIPI_CSI_IPI_MEM_FLASH_IPI_AUTO_FLUSH_SHIFT (8U) +#define MIPI_CSI_IPI_MEM_FLASH_IPI_AUTO_FLUSH_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_MEM_FLASH_IPI_AUTO_FLUSH_SHIFT) & MIPI_CSI_IPI_MEM_FLASH_IPI_AUTO_FLUSH_MASK) +#define MIPI_CSI_IPI_MEM_FLASH_IPI_AUTO_FLUSH_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_MEM_FLASH_IPI_AUTO_FLUSH_MASK) >> MIPI_CSI_IPI_MEM_FLASH_IPI_AUTO_FLUSH_SHIFT) + +/* + * IPI_FLUSH (RW) + * + * flush ipi memory, this bit is auto clear + */ +#define MIPI_CSI_IPI_MEM_FLASH_IPI_FLUSH_MASK (0x1U) +#define MIPI_CSI_IPI_MEM_FLASH_IPI_FLUSH_SHIFT (0U) +#define MIPI_CSI_IPI_MEM_FLASH_IPI_FLUSH_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_MEM_FLASH_IPI_FLUSH_SHIFT) & MIPI_CSI_IPI_MEM_FLASH_IPI_FLUSH_MASK) +#define MIPI_CSI_IPI_MEM_FLASH_IPI_FLUSH_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_MEM_FLASH_IPI_FLUSH_MASK) >> MIPI_CSI_IPI_MEM_FLASH_IPI_FLUSH_SHIFT) + +/* Bitfield definition for register: IPI_HSA_TIME */ +/* + * IPI_HSA_TIME (RW) + * + * configures the Horizontal Synchronism Active period in pixclk cycles + */ +#define MIPI_CSI_IPI_HSA_TIME_IPI_HSA_TIME_MASK (0xFFFU) +#define MIPI_CSI_IPI_HSA_TIME_IPI_HSA_TIME_SHIFT (0U) +#define MIPI_CSI_IPI_HSA_TIME_IPI_HSA_TIME_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_HSA_TIME_IPI_HSA_TIME_SHIFT) & MIPI_CSI_IPI_HSA_TIME_IPI_HSA_TIME_MASK) +#define MIPI_CSI_IPI_HSA_TIME_IPI_HSA_TIME_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_HSA_TIME_IPI_HSA_TIME_MASK) >> MIPI_CSI_IPI_HSA_TIME_IPI_HSA_TIME_SHIFT) + +/* Bitfield definition for register: IPI_HBP_TIME */ +/* + * IPI_HBP_TIME (RW) + * + * configures the Horizontal Synchronism back porch period in pixclk cycles + */ +#define MIPI_CSI_IPI_HBP_TIME_IPI_HBP_TIME_MASK (0xFFFU) +#define MIPI_CSI_IPI_HBP_TIME_IPI_HBP_TIME_SHIFT (0U) +#define MIPI_CSI_IPI_HBP_TIME_IPI_HBP_TIME_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_HBP_TIME_IPI_HBP_TIME_SHIFT) & MIPI_CSI_IPI_HBP_TIME_IPI_HBP_TIME_MASK) +#define MIPI_CSI_IPI_HBP_TIME_IPI_HBP_TIME_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_HBP_TIME_IPI_HBP_TIME_MASK) >> MIPI_CSI_IPI_HBP_TIME_IPI_HBP_TIME_SHIFT) + +/* Bitfield definition for register: IPI_HSD_TIME */ +/* + * IPI_HSD_TIME (RW) + * + * configures the Horizontal Sync Porch delay period in pixclk cycles + */ +#define MIPI_CSI_IPI_HSD_TIME_IPI_HSD_TIME_MASK (0xFFFU) +#define MIPI_CSI_IPI_HSD_TIME_IPI_HSD_TIME_SHIFT (0U) +#define MIPI_CSI_IPI_HSD_TIME_IPI_HSD_TIME_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_HSD_TIME_IPI_HSD_TIME_SHIFT) & MIPI_CSI_IPI_HSD_TIME_IPI_HSD_TIME_MASK) +#define MIPI_CSI_IPI_HSD_TIME_IPI_HSD_TIME_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_HSD_TIME_IPI_HSD_TIME_MASK) >> MIPI_CSI_IPI_HSD_TIME_IPI_HSD_TIME_SHIFT) + +/* Bitfield definition for register: IPI_HLINE_TIME */ +/* + * IPI_HLIN_TIME (RW) + * + * configures the size of the line time counted in pixclk cycles + */ +#define MIPI_CSI_IPI_HLINE_TIME_IPI_HLIN_TIME_MASK (0x7FFFU) +#define MIPI_CSI_IPI_HLINE_TIME_IPI_HLIN_TIME_SHIFT (0U) +#define MIPI_CSI_IPI_HLINE_TIME_IPI_HLIN_TIME_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_HLINE_TIME_IPI_HLIN_TIME_SHIFT) & MIPI_CSI_IPI_HLINE_TIME_IPI_HLIN_TIME_MASK) +#define MIPI_CSI_IPI_HLINE_TIME_IPI_HLIN_TIME_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_HLINE_TIME_IPI_HLIN_TIME_MASK) >> MIPI_CSI_IPI_HLINE_TIME_IPI_HLIN_TIME_SHIFT) + +/* Bitfield definition for register: IPI_SOFTRSTN */ +/* + * IPI_SOFTRSTN (RW) + * + * resets ipi one, active low + */ +#define MIPI_CSI_IPI_SOFTRSTN_IPI_SOFTRSTN_MASK (0x1U) +#define MIPI_CSI_IPI_SOFTRSTN_IPI_SOFTRSTN_SHIFT (0U) +#define MIPI_CSI_IPI_SOFTRSTN_IPI_SOFTRSTN_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_SOFTRSTN_IPI_SOFTRSTN_SHIFT) & MIPI_CSI_IPI_SOFTRSTN_IPI_SOFTRSTN_MASK) +#define MIPI_CSI_IPI_SOFTRSTN_IPI_SOFTRSTN_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_SOFTRSTN_IPI_SOFTRSTN_MASK) >> MIPI_CSI_IPI_SOFTRSTN_IPI_SOFTRSTN_SHIFT) + +/* Bitfield definition for register: IPI_ADV_FEATURES */ +/* + * IPI_SYNC_EVENT_MODE (RW) + * + * for camera mode: 0x0- frame start do not trigger any sync event + */ +#define MIPI_CSI_IPI_ADV_FEATURES_IPI_SYNC_EVENT_MODE_MASK (0x1000000UL) +#define MIPI_CSI_IPI_ADV_FEATURES_IPI_SYNC_EVENT_MODE_SHIFT (24U) +#define MIPI_CSI_IPI_ADV_FEATURES_IPI_SYNC_EVENT_MODE_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_ADV_FEATURES_IPI_SYNC_EVENT_MODE_SHIFT) & MIPI_CSI_IPI_ADV_FEATURES_IPI_SYNC_EVENT_MODE_MASK) +#define MIPI_CSI_IPI_ADV_FEATURES_IPI_SYNC_EVENT_MODE_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_ADV_FEATURES_IPI_SYNC_EVENT_MODE_MASK) >> MIPI_CSI_IPI_ADV_FEATURES_IPI_SYNC_EVENT_MODE_SHIFT) + +/* + * EN_EMBEDDED (RW) + * + * allows the use of embendded packets for ipi synchronization events + */ +#define MIPI_CSI_IPI_ADV_FEATURES_EN_EMBEDDED_MASK (0x200000UL) +#define MIPI_CSI_IPI_ADV_FEATURES_EN_EMBEDDED_SHIFT (21U) +#define MIPI_CSI_IPI_ADV_FEATURES_EN_EMBEDDED_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_ADV_FEATURES_EN_EMBEDDED_SHIFT) & MIPI_CSI_IPI_ADV_FEATURES_EN_EMBEDDED_MASK) +#define MIPI_CSI_IPI_ADV_FEATURES_EN_EMBEDDED_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_ADV_FEATURES_EN_EMBEDDED_MASK) >> MIPI_CSI_IPI_ADV_FEATURES_EN_EMBEDDED_SHIFT) + +/* + * EN_BLANKING (RW) + * + * allows the use of blankong packets for IPI synchronization events + */ +#define MIPI_CSI_IPI_ADV_FEATURES_EN_BLANKING_MASK (0x100000UL) +#define MIPI_CSI_IPI_ADV_FEATURES_EN_BLANKING_SHIFT (20U) +#define MIPI_CSI_IPI_ADV_FEATURES_EN_BLANKING_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_ADV_FEATURES_EN_BLANKING_SHIFT) & MIPI_CSI_IPI_ADV_FEATURES_EN_BLANKING_MASK) +#define MIPI_CSI_IPI_ADV_FEATURES_EN_BLANKING_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_ADV_FEATURES_EN_BLANKING_MASK) >> MIPI_CSI_IPI_ADV_FEATURES_EN_BLANKING_SHIFT) + +/* + * EN_NULL (RW) + * + * allows the use of null packets for IPI synchronization events + */ +#define MIPI_CSI_IPI_ADV_FEATURES_EN_NULL_MASK (0x80000UL) +#define MIPI_CSI_IPI_ADV_FEATURES_EN_NULL_SHIFT (19U) +#define MIPI_CSI_IPI_ADV_FEATURES_EN_NULL_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_ADV_FEATURES_EN_NULL_SHIFT) & MIPI_CSI_IPI_ADV_FEATURES_EN_NULL_MASK) +#define MIPI_CSI_IPI_ADV_FEATURES_EN_NULL_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_ADV_FEATURES_EN_NULL_MASK) >> MIPI_CSI_IPI_ADV_FEATURES_EN_NULL_SHIFT) + +/* + * EN_LINE_START (RW) + * + * allows the use of line start packets for ipi synchronization events + */ +#define MIPI_CSI_IPI_ADV_FEATURES_EN_LINE_START_MASK (0x40000UL) +#define MIPI_CSI_IPI_ADV_FEATURES_EN_LINE_START_SHIFT (18U) +#define MIPI_CSI_IPI_ADV_FEATURES_EN_LINE_START_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_ADV_FEATURES_EN_LINE_START_SHIFT) & MIPI_CSI_IPI_ADV_FEATURES_EN_LINE_START_MASK) +#define MIPI_CSI_IPI_ADV_FEATURES_EN_LINE_START_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_ADV_FEATURES_EN_LINE_START_MASK) >> MIPI_CSI_IPI_ADV_FEATURES_EN_LINE_START_SHIFT) + +/* + * EN_VIDEO (RW) + * + * allows the use of video packets for ipi synchronization events + */ +#define MIPI_CSI_IPI_ADV_FEATURES_EN_VIDEO_MASK (0x20000UL) +#define MIPI_CSI_IPI_ADV_FEATURES_EN_VIDEO_SHIFT (17U) +#define MIPI_CSI_IPI_ADV_FEATURES_EN_VIDEO_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_ADV_FEATURES_EN_VIDEO_SHIFT) & MIPI_CSI_IPI_ADV_FEATURES_EN_VIDEO_MASK) +#define MIPI_CSI_IPI_ADV_FEATURES_EN_VIDEO_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_ADV_FEATURES_EN_VIDEO_MASK) >> MIPI_CSI_IPI_ADV_FEATURES_EN_VIDEO_SHIFT) + +/* + * LINE_EVENT_SELECTION (RW) + * + * for camero mode, allows manual selection of the packet fo line delimiter as follows: 0x0-controller seletc it automaticlly 0x1-select packets from list programmed in 17:21 + */ +#define MIPI_CSI_IPI_ADV_FEATURES_LINE_EVENT_SELECTION_MASK (0x10000UL) +#define MIPI_CSI_IPI_ADV_FEATURES_LINE_EVENT_SELECTION_SHIFT (16U) +#define MIPI_CSI_IPI_ADV_FEATURES_LINE_EVENT_SELECTION_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_ADV_FEATURES_LINE_EVENT_SELECTION_SHIFT) & MIPI_CSI_IPI_ADV_FEATURES_LINE_EVENT_SELECTION_MASK) +#define MIPI_CSI_IPI_ADV_FEATURES_LINE_EVENT_SELECTION_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_ADV_FEATURES_LINE_EVENT_SELECTION_MASK) >> MIPI_CSI_IPI_ADV_FEATURES_LINE_EVENT_SELECTION_SHIFT) + +/* + * IPI_DT (RW) + * + * datatype to overwrite + */ +#define MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_MASK (0x3F00U) +#define MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_SHIFT (8U) +#define MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_SHIFT) & MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_MASK) +#define MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_MASK) >> MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_SHIFT) + +/* + * IPI_DT_OVERWRITE (RW) + * + * ignore datatype of the header using the programmed datatype for decoding + */ +#define MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_OVERWRITE_MASK (0x1U) +#define MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_OVERWRITE_SHIFT (0U) +#define MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_OVERWRITE_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_OVERWRITE_SHIFT) & MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_OVERWRITE_MASK) +#define MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_OVERWRITE_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_OVERWRITE_MASK) >> MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_OVERWRITE_SHIFT) + +/* Bitfield definition for register: IPI_VSA_LINES */ +/* + * IPI_VSA_LINES (RW) + * + * configures the vertical synchronism active period measured in number of horizontal lines + */ +#define MIPI_CSI_IPI_VSA_LINES_IPI_VSA_LINES_MASK (0x3FFU) +#define MIPI_CSI_IPI_VSA_LINES_IPI_VSA_LINES_SHIFT (0U) +#define MIPI_CSI_IPI_VSA_LINES_IPI_VSA_LINES_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_VSA_LINES_IPI_VSA_LINES_SHIFT) & MIPI_CSI_IPI_VSA_LINES_IPI_VSA_LINES_MASK) +#define MIPI_CSI_IPI_VSA_LINES_IPI_VSA_LINES_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_VSA_LINES_IPI_VSA_LINES_MASK) >> MIPI_CSI_IPI_VSA_LINES_IPI_VSA_LINES_SHIFT) + +/* Bitfield definition for register: IPI_VBP_LINES */ +/* + * IPI_VBP_LINES (RW) + * + * configuress the vertical back porch period measured in number of horizontal lines + */ +#define MIPI_CSI_IPI_VBP_LINES_IPI_VBP_LINES_MASK (0x3FFU) +#define MIPI_CSI_IPI_VBP_LINES_IPI_VBP_LINES_SHIFT (0U) +#define MIPI_CSI_IPI_VBP_LINES_IPI_VBP_LINES_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_VBP_LINES_IPI_VBP_LINES_SHIFT) & MIPI_CSI_IPI_VBP_LINES_IPI_VBP_LINES_MASK) +#define MIPI_CSI_IPI_VBP_LINES_IPI_VBP_LINES_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_VBP_LINES_IPI_VBP_LINES_MASK) >> MIPI_CSI_IPI_VBP_LINES_IPI_VBP_LINES_SHIFT) + +/* Bitfield definition for register: IPI_VFP_LINES */ +/* + * IPI_VFP_LINES (RW) + * + * configures the vertical front porch period measured in number of horizontall lines + */ +#define MIPI_CSI_IPI_VFP_LINES_IPI_VFP_LINES_MASK (0x3FFU) +#define MIPI_CSI_IPI_VFP_LINES_IPI_VFP_LINES_SHIFT (0U) +#define MIPI_CSI_IPI_VFP_LINES_IPI_VFP_LINES_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_VFP_LINES_IPI_VFP_LINES_SHIFT) & MIPI_CSI_IPI_VFP_LINES_IPI_VFP_LINES_MASK) +#define MIPI_CSI_IPI_VFP_LINES_IPI_VFP_LINES_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_VFP_LINES_IPI_VFP_LINES_MASK) >> MIPI_CSI_IPI_VFP_LINES_IPI_VFP_LINES_SHIFT) + +/* Bitfield definition for register: IPI_VACTIVE_LINES */ +/* + * IPI_VACTIVE_LINES (RW) + * + * configures the vertical active period measured in bumber of horizontal lines + */ +#define MIPI_CSI_IPI_VACTIVE_LINES_IPI_VACTIVE_LINES_MASK (0x3FFFU) +#define MIPI_CSI_IPI_VACTIVE_LINES_IPI_VACTIVE_LINES_SHIFT (0U) +#define MIPI_CSI_IPI_VACTIVE_LINES_IPI_VACTIVE_LINES_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_VACTIVE_LINES_IPI_VACTIVE_LINES_SHIFT) & MIPI_CSI_IPI_VACTIVE_LINES_IPI_VACTIVE_LINES_MASK) +#define MIPI_CSI_IPI_VACTIVE_LINES_IPI_VACTIVE_LINES_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_VACTIVE_LINES_IPI_VACTIVE_LINES_MASK) >> MIPI_CSI_IPI_VACTIVE_LINES_IPI_VACTIVE_LINES_SHIFT) + +/* Bitfield definition for register: VC_EXTENSION */ +/* + * VCX (RW) + * + * indicates status of virtual channel extension: 0-virtual channel extension is enable 1-legacy mode + */ +#define MIPI_CSI_VC_EXTENSION_VCX_MASK (0x1U) +#define MIPI_CSI_VC_EXTENSION_VCX_SHIFT (0U) +#define MIPI_CSI_VC_EXTENSION_VCX_SET(x) (((uint32_t)(x) << MIPI_CSI_VC_EXTENSION_VCX_SHIFT) & MIPI_CSI_VC_EXTENSION_VCX_MASK) +#define MIPI_CSI_VC_EXTENSION_VCX_GET(x) (((uint32_t)(x) & MIPI_CSI_VC_EXTENSION_VCX_MASK) >> MIPI_CSI_VC_EXTENSION_VCX_SHIFT) + +/* Bitfield definition for register: PHY_CAL */ +/* + * RXSKEWCALHS (RC) + * + * a low-to-high transition on rxskewcalhs signal means the the phy has initiated the de-skew calibration + */ +#define MIPI_CSI_PHY_CAL_RXSKEWCALHS_MASK (0x1U) +#define MIPI_CSI_PHY_CAL_RXSKEWCALHS_SHIFT (0U) +#define MIPI_CSI_PHY_CAL_RXSKEWCALHS_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CAL_RXSKEWCALHS_MASK) >> MIPI_CSI_PHY_CAL_RXSKEWCALHS_SHIFT) + +/* Bitfield definition for register: INT_ST_PHY_FATAL */ +/* + * ERR_DESKEW (RC) + * + * reports whenever data is lost due to an existent skew between lanes greater than 2 rxwordclkhs + */ +#define MIPI_CSI_INT_ST_PHY_FATAL_ERR_DESKEW_MASK (0x100U) +#define MIPI_CSI_INT_ST_PHY_FATAL_ERR_DESKEW_SHIFT (8U) +#define MIPI_CSI_INT_ST_PHY_FATAL_ERR_DESKEW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PHY_FATAL_ERR_DESKEW_MASK) >> MIPI_CSI_INT_ST_PHY_FATAL_ERR_DESKEW_SHIFT) + +/* + * PHY_ERRSOTSYNCHS_1 (RC) + * + * start of transmission error on data lane1 + */ +#define MIPI_CSI_INT_ST_PHY_FATAL_PHY_ERRSOTSYNCHS_1_MASK (0x2U) +#define MIPI_CSI_INT_ST_PHY_FATAL_PHY_ERRSOTSYNCHS_1_SHIFT (1U) +#define MIPI_CSI_INT_ST_PHY_FATAL_PHY_ERRSOTSYNCHS_1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PHY_FATAL_PHY_ERRSOTSYNCHS_1_MASK) >> MIPI_CSI_INT_ST_PHY_FATAL_PHY_ERRSOTSYNCHS_1_SHIFT) + +/* + * PHY_ERRSOTSYNCHS_0 (RC) + * + * start of transmission error on data lane0 + */ +#define MIPI_CSI_INT_ST_PHY_FATAL_PHY_ERRSOTSYNCHS_0_MASK (0x1U) +#define MIPI_CSI_INT_ST_PHY_FATAL_PHY_ERRSOTSYNCHS_0_SHIFT (0U) +#define MIPI_CSI_INT_ST_PHY_FATAL_PHY_ERRSOTSYNCHS_0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PHY_FATAL_PHY_ERRSOTSYNCHS_0_MASK) >> MIPI_CSI_INT_ST_PHY_FATAL_PHY_ERRSOTSYNCHS_0_SHIFT) + +/* Bitfield definition for register: INT_MSK_PHY_FATAL */ +/* + * ERR_DESKEW (RW) + * + * mask for err_deskew + */ +#define MIPI_CSI_INT_MSK_PHY_FATAL_ERR_DESKEW_MASK (0x100U) +#define MIPI_CSI_INT_MSK_PHY_FATAL_ERR_DESKEW_SHIFT (8U) +#define MIPI_CSI_INT_MSK_PHY_FATAL_ERR_DESKEW_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PHY_FATAL_ERR_DESKEW_SHIFT) & MIPI_CSI_INT_MSK_PHY_FATAL_ERR_DESKEW_MASK) +#define MIPI_CSI_INT_MSK_PHY_FATAL_ERR_DESKEW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PHY_FATAL_ERR_DESKEW_MASK) >> MIPI_CSI_INT_MSK_PHY_FATAL_ERR_DESKEW_SHIFT) + +/* + * MASK_PHY_ERRSOTSYNCHS_1 (RW) + * + * mask for phy_errsotsynchs_1 + */ +#define MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_1_MASK (0x2U) +#define MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_1_SHIFT (1U) +#define MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_1_SHIFT) & MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_1_MASK) +#define MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_1_MASK) >> MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_1_SHIFT) + +/* + * MASK_PHY_ERRSOTSYNCHS_0 (RW) + * + * mask for phy_errsotsynchs_0 + */ +#define MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_0_MASK (0x1U) +#define MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_0_SHIFT (0U) +#define MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_0_SHIFT) & MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_0_MASK) +#define MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_0_MASK) >> MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_0_SHIFT) + +/* Bitfield definition for register: INT_FORCE_PHY_FATAL */ +/* + * ERR_DESKEW (RW) + * + * force err_deskew + */ +#define MIPI_CSI_INT_FORCE_PHY_FATAL_ERR_DESKEW_MASK (0x100U) +#define MIPI_CSI_INT_FORCE_PHY_FATAL_ERR_DESKEW_SHIFT (8U) +#define MIPI_CSI_INT_FORCE_PHY_FATAL_ERR_DESKEW_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PHY_FATAL_ERR_DESKEW_SHIFT) & MIPI_CSI_INT_FORCE_PHY_FATAL_ERR_DESKEW_MASK) +#define MIPI_CSI_INT_FORCE_PHY_FATAL_ERR_DESKEW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PHY_FATAL_ERR_DESKEW_MASK) >> MIPI_CSI_INT_FORCE_PHY_FATAL_ERR_DESKEW_SHIFT) + +/* + * FORCE_PHY_ERRSOTSYNCHS_1 (RW) + * + * force phy_errsotsynchs_1 + */ +#define MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_1_MASK (0x2U) +#define MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_1_SHIFT (1U) +#define MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_1_SHIFT) & MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_1_MASK) +#define MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_1_MASK) >> MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_1_SHIFT) + +/* + * FORCE_PHY_ERRSOTSYNCHS_0 (RW) + * + * force phy_errsotsynchs_0 + */ +#define MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_0_MASK (0x1U) +#define MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_0_SHIFT (0U) +#define MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_0_SHIFT) & MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_0_MASK) +#define MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_0_MASK) >> MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_0_SHIFT) + +/* Bitfield definition for register: INT_ST_PKT_FATAL */ +/* + * ERR_ECC_DOUBLE (RC) + * + * header ecc contains at least 2 errors + */ +#define MIPI_CSI_INT_ST_PKT_FATAL_ERR_ECC_DOUBLE_MASK (0x1U) +#define MIPI_CSI_INT_ST_PKT_FATAL_ERR_ECC_DOUBLE_SHIFT (0U) +#define MIPI_CSI_INT_ST_PKT_FATAL_ERR_ECC_DOUBLE_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PKT_FATAL_ERR_ECC_DOUBLE_MASK) >> MIPI_CSI_INT_ST_PKT_FATAL_ERR_ECC_DOUBLE_SHIFT) + +/* Bitfield definition for register: INT_MSK_PKT_FATAL */ +/* + * MASK_ERR_ECC_DOUBLE (RW) + * + * mask for err_ecc_double + */ +#define MIPI_CSI_INT_MSK_PKT_FATAL_MASK_ERR_ECC_DOUBLE_MASK (0x1U) +#define MIPI_CSI_INT_MSK_PKT_FATAL_MASK_ERR_ECC_DOUBLE_SHIFT (0U) +#define MIPI_CSI_INT_MSK_PKT_FATAL_MASK_ERR_ECC_DOUBLE_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PKT_FATAL_MASK_ERR_ECC_DOUBLE_SHIFT) & MIPI_CSI_INT_MSK_PKT_FATAL_MASK_ERR_ECC_DOUBLE_MASK) +#define MIPI_CSI_INT_MSK_PKT_FATAL_MASK_ERR_ECC_DOUBLE_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PKT_FATAL_MASK_ERR_ECC_DOUBLE_MASK) >> MIPI_CSI_INT_MSK_PKT_FATAL_MASK_ERR_ECC_DOUBLE_SHIFT) + +/* Bitfield definition for register: INT_FORCE_PKT_FATAL */ +/* + * FORCE_ERR_ECC_DOUBLE (RW) + * + * force err_ecc_double + */ +#define MIPI_CSI_INT_FORCE_PKT_FATAL_FORCE_ERR_ECC_DOUBLE_MASK (0x1U) +#define MIPI_CSI_INT_FORCE_PKT_FATAL_FORCE_ERR_ECC_DOUBLE_SHIFT (0U) +#define MIPI_CSI_INT_FORCE_PKT_FATAL_FORCE_ERR_ECC_DOUBLE_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PKT_FATAL_FORCE_ERR_ECC_DOUBLE_SHIFT) & MIPI_CSI_INT_FORCE_PKT_FATAL_FORCE_ERR_ECC_DOUBLE_MASK) +#define MIPI_CSI_INT_FORCE_PKT_FATAL_FORCE_ERR_ECC_DOUBLE_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PKT_FATAL_FORCE_ERR_ECC_DOUBLE_MASK) >> MIPI_CSI_INT_FORCE_PKT_FATAL_FORCE_ERR_ECC_DOUBLE_SHIFT) + +/* Bitfield definition for register: INT_ST_PHY */ +/* + * PHY_ERRESC_1 (RC) + * + * start of transmission error on data lane 1 + */ +#define MIPI_CSI_INT_ST_PHY_PHY_ERRESC_1_MASK (0x20000UL) +#define MIPI_CSI_INT_ST_PHY_PHY_ERRESC_1_SHIFT (17U) +#define MIPI_CSI_INT_ST_PHY_PHY_ERRESC_1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PHY_PHY_ERRESC_1_MASK) >> MIPI_CSI_INT_ST_PHY_PHY_ERRESC_1_SHIFT) + +/* + * PHY_ERRESC_0 (RC) + * + * start of transmission error on data lane 0 + */ +#define MIPI_CSI_INT_ST_PHY_PHY_ERRESC_0_MASK (0x10000UL) +#define MIPI_CSI_INT_ST_PHY_PHY_ERRESC_0_SHIFT (16U) +#define MIPI_CSI_INT_ST_PHY_PHY_ERRESC_0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PHY_PHY_ERRESC_0_MASK) >> MIPI_CSI_INT_ST_PHY_PHY_ERRESC_0_SHIFT) + +/* + * PHY_ERRSOTHS_1 (RC) + * + * start of transmission error on data lane 1 + */ +#define MIPI_CSI_INT_ST_PHY_PHY_ERRSOTHS_1_MASK (0x2U) +#define MIPI_CSI_INT_ST_PHY_PHY_ERRSOTHS_1_SHIFT (1U) +#define MIPI_CSI_INT_ST_PHY_PHY_ERRSOTHS_1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PHY_PHY_ERRSOTHS_1_MASK) >> MIPI_CSI_INT_ST_PHY_PHY_ERRSOTHS_1_SHIFT) + +/* + * PHY_ERRSOTHS_0 (RC) + * + * start of transmission error on data lane 0 + */ +#define MIPI_CSI_INT_ST_PHY_PHY_ERRSOTHS_0_MASK (0x1U) +#define MIPI_CSI_INT_ST_PHY_PHY_ERRSOTHS_0_SHIFT (0U) +#define MIPI_CSI_INT_ST_PHY_PHY_ERRSOTHS_0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PHY_PHY_ERRSOTHS_0_MASK) >> MIPI_CSI_INT_ST_PHY_PHY_ERRSOTHS_0_SHIFT) + +/* Bitfield definition for register: INT_MSK_PHY */ +/* + * MASK_PHY_ERRESC_1 (RW) + * + * mask for phy_erresc_1 + */ +#define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_1_MASK (0x20000UL) +#define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_1_SHIFT (17U) +#define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_1_SHIFT) & MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_1_MASK) +#define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_1_MASK) >> MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_1_SHIFT) + +/* + * MASK_PHY_ERRESC_0 (RW) + * + * mask for phy_erresc_0 + */ +#define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_0_MASK (0x10000UL) +#define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_0_SHIFT (16U) +#define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_0_SHIFT) & MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_0_MASK) +#define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_0_MASK) >> MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_0_SHIFT) + +/* + * MASK_PHY_ERRSOTHS_1 (RW) + * + * mask for phy_errsoths_1 + */ +#define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_1_MASK (0x2U) +#define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_1_SHIFT (1U) +#define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_1_SHIFT) & MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_1_MASK) +#define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_1_MASK) >> MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_1_SHIFT) + +/* + * MASK_PHY_ERRSOTHS_0 (RW) + * + * mask for phy_errsoths_0 + */ +#define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_0_MASK (0x1U) +#define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_0_SHIFT (0U) +#define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_0_SHIFT) & MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_0_MASK) +#define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_0_MASK) >> MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_0_SHIFT) + +/* Bitfield definition for register: INT_FORCE_PHY */ +/* + * FORCE_PHY_ERRESC_1 (RW) + * + * force phy_erresc_1 + */ +#define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_1_MASK (0x20000UL) +#define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_1_SHIFT (17U) +#define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_1_SHIFT) & MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_1_MASK) +#define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_1_MASK) >> MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_1_SHIFT) + +/* + * FORCE_PHY_ERRESC_0 (RW) + * + * force phy_erresc_0 + */ +#define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_0_MASK (0x10000UL) +#define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_0_SHIFT (16U) +#define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_0_SHIFT) & MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_0_MASK) +#define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_0_MASK) >> MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_0_SHIFT) + +/* + * FORCE_PHY_ERRSOTHS_1 (RW) + * + * force phy_errsoths_1 + */ +#define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_1_MASK (0x2U) +#define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_1_SHIFT (1U) +#define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_1_SHIFT) & MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_1_MASK) +#define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_1_MASK) >> MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_1_SHIFT) + +/* + * FORCE_PHY_ERRSOTHS_0 (RW) + * + * force phy_errsoths_0 + */ +#define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_0_MASK (0x1U) +#define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_0_SHIFT (0U) +#define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_0_SHIFT) & MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_0_MASK) +#define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_0_MASK) >> MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_0_SHIFT) + +/* Bitfield definition for register: INT_ST_IPI_FATAL */ +/* + * INT_EVENT_FIFO_OVERFLOW (RC) + * + * reporting internal fifo overflow + */ +#define MIPI_CSI_INT_ST_IPI_FATAL_INT_EVENT_FIFO_OVERFLOW_MASK (0x20U) +#define MIPI_CSI_INT_ST_IPI_FATAL_INT_EVENT_FIFO_OVERFLOW_SHIFT (5U) +#define MIPI_CSI_INT_ST_IPI_FATAL_INT_EVENT_FIFO_OVERFLOW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_IPI_FATAL_INT_EVENT_FIFO_OVERFLOW_MASK) >> MIPI_CSI_INT_ST_IPI_FATAL_INT_EVENT_FIFO_OVERFLOW_SHIFT) + +/* + * PIXEL_IF_HLINE_ERR (RC) + * + * horizontal line time error + */ +#define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_HLINE_ERR_MASK (0x10U) +#define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_HLINE_ERR_SHIFT (4U) +#define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_HLINE_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_HLINE_ERR_MASK) >> MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_HLINE_ERR_SHIFT) + +/* + * PIXEL_IF_FIFO_NEMPTY_FS (RC) + * + * the fifo of pixel interface is not empty at the starat of a new frame + */ +#define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_NEMPTY_FS_MASK (0x8U) +#define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_NEMPTY_FS_SHIFT (3U) +#define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_NEMPTY_FS_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_NEMPTY_FS_MASK) >> MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_NEMPTY_FS_SHIFT) + +/* + * PIXEL_IF_FRAME_SYNC_ERR (RC) + * + * whenever in controller mode, notifies if a new frame is received but previous has not been completed + */ +#define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FRAME_SYNC_ERR_MASK (0x4U) +#define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FRAME_SYNC_ERR_SHIFT (2U) +#define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FRAME_SYNC_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FRAME_SYNC_ERR_MASK) >> MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FRAME_SYNC_ERR_SHIFT) + +/* + * PIXEL_IF_FIFO_OVERFLOW (RC) + * + * the fifo of pixel interface has lost information because some data arrived and fifo is already full + */ +#define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_OVERFLOW_MASK (0x2U) +#define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_OVERFLOW_SHIFT (1U) +#define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_OVERFLOW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_OVERFLOW_MASK) >> MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_OVERFLOW_SHIFT) + +/* + * PIXEL_IF_FIFO_UNDERFLOW (RC) + * + * the fifo has become empty before the expected bumber of pixels could be extracted to the pixel intefcese + */ +#define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_UNDERFLOW_MASK (0x1U) +#define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_UNDERFLOW_SHIFT (0U) +#define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_UNDERFLOW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_UNDERFLOW_MASK) >> MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_UNDERFLOW_SHIFT) + +/* Bitfield definition for register: INT_MSK_IPI_FATAL */ +/* + * MSK_INT_EVENT_FIFO_OVERFLOW (RW) + * + * mask int_event_fifo_overflow + */ +#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_INT_EVENT_FIFO_OVERFLOW_MASK (0x20U) +#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_INT_EVENT_FIFO_OVERFLOW_SHIFT (5U) +#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_INT_EVENT_FIFO_OVERFLOW_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_IPI_FATAL_MSK_INT_EVENT_FIFO_OVERFLOW_SHIFT) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_INT_EVENT_FIFO_OVERFLOW_MASK) +#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_INT_EVENT_FIFO_OVERFLOW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_INT_EVENT_FIFO_OVERFLOW_MASK) >> MIPI_CSI_INT_MSK_IPI_FATAL_MSK_INT_EVENT_FIFO_OVERFLOW_SHIFT) + +/* + * MSK_PIXEL_IF_HLINE_ERR (RW) + * + * mask pixel_if_hline_err + */ +#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_HLINE_ERR_MASK (0x10U) +#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_HLINE_ERR_SHIFT (4U) +#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_HLINE_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_HLINE_ERR_SHIFT) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_HLINE_ERR_MASK) +#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_HLINE_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_HLINE_ERR_MASK) >> MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_HLINE_ERR_SHIFT) + +/* + * MSK_PIXEL_IF_FIFO_NEMPTY_FS (RW) + * + * mask pixel_if_fifo_nempty_fs + */ +#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_NEMPTY_FS_MASK (0x8U) +#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_NEMPTY_FS_SHIFT (3U) +#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_NEMPTY_FS_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_NEMPTY_FS_SHIFT) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_NEMPTY_FS_MASK) +#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_NEMPTY_FS_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_NEMPTY_FS_MASK) >> MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_NEMPTY_FS_SHIFT) + +/* + * MSK_FRAME_SYNC_ERR (RW) + * + * mask for pixel_if_frame_sync_err + */ +#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_FRAME_SYNC_ERR_MASK (0x4U) +#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_FRAME_SYNC_ERR_SHIFT (2U) +#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_FRAME_SYNC_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_IPI_FATAL_MSK_FRAME_SYNC_ERR_SHIFT) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_FRAME_SYNC_ERR_MASK) +#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_FRAME_SYNC_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_FRAME_SYNC_ERR_MASK) >> MIPI_CSI_INT_MSK_IPI_FATAL_MSK_FRAME_SYNC_ERR_SHIFT) + +/* + * MSK_PIXEL_IF_FIFO_OVERFLOW (RW) + * + * mask for pixel_if_fifo_overflow + */ +#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_OVERFLOW_MASK (0x2U) +#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_OVERFLOW_SHIFT (1U) +#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_OVERFLOW_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_OVERFLOW_SHIFT) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_OVERFLOW_MASK) +#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_OVERFLOW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_OVERFLOW_MASK) >> MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_OVERFLOW_SHIFT) + +/* + * MSK_PIXEL_IF_FIFO_UNDERFLOW (RW) + * + * mask for pixel_if_fifo_unterflow + */ +#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_UNDERFLOW_MASK (0x1U) +#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_UNDERFLOW_SHIFT (0U) +#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_UNDERFLOW_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_UNDERFLOW_SHIFT) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_UNDERFLOW_MASK) +#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_UNDERFLOW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_UNDERFLOW_MASK) >> MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_UNDERFLOW_SHIFT) + +/* Bitfield definition for register: INT_FORCE_IPI_FATAL */ +/* + * FORCE_INT_EVENT_FIFO_OVERFLOW (RW) + * + * force int_event_fifo_overflow + */ +#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_INT_EVENT_FIFO_OVERFLOW_MASK (0x20U) +#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_INT_EVENT_FIFO_OVERFLOW_SHIFT (5U) +#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_INT_EVENT_FIFO_OVERFLOW_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_INT_EVENT_FIFO_OVERFLOW_SHIFT) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_INT_EVENT_FIFO_OVERFLOW_MASK) +#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_INT_EVENT_FIFO_OVERFLOW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_INT_EVENT_FIFO_OVERFLOW_MASK) >> MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_INT_EVENT_FIFO_OVERFLOW_SHIFT) + +/* + * FORCE_PIXEL_IF_HLINE_ERR (RW) + * + * force pixel_if_hline_err + */ +#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_HLINE_ERR_MASK (0x10U) +#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_HLINE_ERR_SHIFT (4U) +#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_HLINE_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_HLINE_ERR_SHIFT) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_HLINE_ERR_MASK) +#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_HLINE_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_HLINE_ERR_MASK) >> MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_HLINE_ERR_SHIFT) + +/* + * FORCE_PIXEL_IF_FIFO_NEMPTY_FS (RW) + * + * force pixel_if_fifo_nempty_fs + */ +#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_NEMPTY_FS_MASK (0x8U) +#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_NEMPTY_FS_SHIFT (3U) +#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_NEMPTY_FS_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_NEMPTY_FS_SHIFT) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_NEMPTY_FS_MASK) +#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_NEMPTY_FS_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_NEMPTY_FS_MASK) >> MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_NEMPTY_FS_SHIFT) + +/* + * FORCE_FRAME_SYNC_ERR (RW) + * + * force for frame_sync_err + */ +#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_FRAME_SYNC_ERR_MASK (0x4U) +#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_FRAME_SYNC_ERR_SHIFT (2U) +#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_FRAME_SYNC_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_FRAME_SYNC_ERR_SHIFT) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_FRAME_SYNC_ERR_MASK) +#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_FRAME_SYNC_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_FRAME_SYNC_ERR_MASK) >> MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_FRAME_SYNC_ERR_SHIFT) + +/* + * FORCE_PIXEL_IF_FIFO_OVERFLOW (RW) + * + * force for pixel_if_fifo_overflow + */ +#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_OVERFLOW_MASK (0x2U) +#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_OVERFLOW_SHIFT (1U) +#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_OVERFLOW_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_OVERFLOW_SHIFT) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_OVERFLOW_MASK) +#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_OVERFLOW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_OVERFLOW_MASK) >> MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_OVERFLOW_SHIFT) + +/* + * FORCE_PIXEL_IF_FIFO_UNDERFLOW (RW) + * + * force for pixel_if_fifo_underflow + */ +#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_UNDERFLOW_MASK (0x1U) +#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_UNDERFLOW_SHIFT (0U) +#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_UNDERFLOW_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_UNDERFLOW_SHIFT) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_UNDERFLOW_MASK) +#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_UNDERFLOW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_UNDERFLOW_MASK) >> MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_UNDERFLOW_SHIFT) + +/* Bitfield definition for register: INT_ST_AP_GENERIC */ +/* + * SYNCHRONIZER_PIXCLK_AP_ERR (RC) + * + * ap error in synchronizer block for pixclk domain + */ +#define MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_PIXCLK_AP_ERR_MASK (0x10000UL) +#define MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_PIXCLK_AP_ERR_SHIFT (16U) +#define MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_PIXCLK_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_PIXCLK_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_PIXCLK_AP_ERR_SHIFT) + +/* + * SYNCHRONIZER_RXBYTECLKHS_AP_ERR (RC) + * + * ap error in synchronizer block for rxbyteclkhs domain + */ +#define MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_MASK (0x8000U) +#define MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_SHIFT (15U) +#define MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_SHIFT) + +/* + * SYNCHRONIZER_FPCLK_AP_ERR (RC) + * + * ap error in synchronizer block for fpclk domain + */ +#define MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_FPCLK_AP_ERR_MASK (0x4000U) +#define MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_FPCLK_AP_ERR_SHIFT (14U) +#define MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_FPCLK_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_FPCLK_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_FPCLK_AP_ERR_SHIFT) + +/* + * ERR_HANDLE_AP_ERR (RC) + * + * ap error in error handler block + */ +#define MIPI_CSI_INT_ST_AP_GENERIC_ERR_HANDLE_AP_ERR_MASK (0x2000U) +#define MIPI_CSI_INT_ST_AP_GENERIC_ERR_HANDLE_AP_ERR_SHIFT (13U) +#define MIPI_CSI_INT_ST_AP_GENERIC_ERR_HANDLE_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_ERR_HANDLE_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_ERR_HANDLE_AP_ERR_SHIFT) + +/* + * ERR_MSGR_AP_ERR (RC) + * + * ap error in err msgr block + */ +#define MIPI_CSI_INT_ST_AP_GENERIC_ERR_MSGR_AP_ERR_MASK (0x1000U) +#define MIPI_CSI_INT_ST_AP_GENERIC_ERR_MSGR_AP_ERR_SHIFT (12U) +#define MIPI_CSI_INT_ST_AP_GENERIC_ERR_MSGR_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_ERR_MSGR_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_ERR_MSGR_AP_ERR_SHIFT) + +/* + * PREP_OUTS_AP_ERR (RC) + * + * ap error in prepare outs block + */ +#define MIPI_CSI_INT_ST_AP_GENERIC_PREP_OUTS_AP_ERR_MASK (0xC00U) +#define MIPI_CSI_INT_ST_AP_GENERIC_PREP_OUTS_AP_ERR_SHIFT (10U) +#define MIPI_CSI_INT_ST_AP_GENERIC_PREP_OUTS_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_PREP_OUTS_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_PREP_OUTS_AP_ERR_SHIFT) + +/* + * PACKET_ANALYZER_AP_ERR (RC) + * + * ap error in packet analyzer block + */ +#define MIPI_CSI_INT_ST_AP_GENERIC_PACKET_ANALYZER_AP_ERR_MASK (0x300U) +#define MIPI_CSI_INT_ST_AP_GENERIC_PACKET_ANALYZER_AP_ERR_SHIFT (8U) +#define MIPI_CSI_INT_ST_AP_GENERIC_PACKET_ANALYZER_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_PACKET_ANALYZER_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_PACKET_ANALYZER_AP_ERR_SHIFT) + +/* + * PHY_ADAPTER_AP_ERR (RC) + * + * ap error in phy adapter block + */ +#define MIPI_CSI_INT_ST_AP_GENERIC_PHY_ADAPTER_AP_ERR_MASK (0x80U) +#define MIPI_CSI_INT_ST_AP_GENERIC_PHY_ADAPTER_AP_ERR_SHIFT (7U) +#define MIPI_CSI_INT_ST_AP_GENERIC_PHY_ADAPTER_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_PHY_ADAPTER_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_PHY_ADAPTER_AP_ERR_SHIFT) + +/* + * DESCRAMBLER_AP_ERR (RC) + * + * ap error in descrambler block + */ +#define MIPI_CSI_INT_ST_AP_GENERIC_DESCRAMBLER_AP_ERR_MASK (0x40U) +#define MIPI_CSI_INT_ST_AP_GENERIC_DESCRAMBLER_AP_ERR_SHIFT (6U) +#define MIPI_CSI_INT_ST_AP_GENERIC_DESCRAMBLER_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_DESCRAMBLER_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_DESCRAMBLER_AP_ERR_SHIFT) + +/* + * PIPELINE_DELAY_AP_ERR (RC) + * + * ap error in pipeline delay block + */ +#define MIPI_CSI_INT_ST_AP_GENERIC_PIPELINE_DELAY_AP_ERR_MASK (0x20U) +#define MIPI_CSI_INT_ST_AP_GENERIC_PIPELINE_DELAY_AP_ERR_SHIFT (5U) +#define MIPI_CSI_INT_ST_AP_GENERIC_PIPELINE_DELAY_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_PIPELINE_DELAY_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_PIPELINE_DELAY_AP_ERR_SHIFT) + +/* + * DE_SKEW_AP_ERR (RC) + * + * ap error in de-skew block + */ +#define MIPI_CSI_INT_ST_AP_GENERIC_DE_SKEW_AP_ERR_MASK (0x10U) +#define MIPI_CSI_INT_ST_AP_GENERIC_DE_SKEW_AP_ERR_SHIFT (4U) +#define MIPI_CSI_INT_ST_AP_GENERIC_DE_SKEW_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_DE_SKEW_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_DE_SKEW_AP_ERR_SHIFT) + +/* + * REG_BANK_AP_ERR (RC) + * + * ap error in register bank block + */ +#define MIPI_CSI_INT_ST_AP_GENERIC_REG_BANK_AP_ERR_MASK (0xCU) +#define MIPI_CSI_INT_ST_AP_GENERIC_REG_BANK_AP_ERR_SHIFT (2U) +#define MIPI_CSI_INT_ST_AP_GENERIC_REG_BANK_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_REG_BANK_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_REG_BANK_AP_ERR_SHIFT) + +/* + * APB_AP_ERR (RC) + * + * ap error in apb block + */ +#define MIPI_CSI_INT_ST_AP_GENERIC_APB_AP_ERR_MASK (0x3U) +#define MIPI_CSI_INT_ST_AP_GENERIC_APB_AP_ERR_SHIFT (0U) +#define MIPI_CSI_INT_ST_AP_GENERIC_APB_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_APB_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_APB_AP_ERR_SHIFT) + +/* Bitfield definition for register: INT_MSK_AP_GENERIC */ +/* + * MSK_SYNCHRONIZER_PIXCLK_AP_ERR (RW) + * + */ +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_PIXCLK_AP_ERR_MASK (0x10000UL) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_PIXCLK_AP_ERR_SHIFT (16U) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_PIXCLK_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_PIXCLK_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_PIXCLK_AP_ERR_MASK) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_PIXCLK_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_PIXCLK_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_PIXCLK_AP_ERR_SHIFT) + +/* + * MSK_SYNCHRONIZER_RXBYTECLKHS_AP_ERR (RW) + * + */ +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_MASK (0x8000U) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_SHIFT (15U) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_MASK) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_SHIFT) + +/* + * MSK_SYNCHRONIZER_FPCLK_AP_ERR (RW) + * + */ +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_FPCLK_AP_ERR_MASK (0x4000U) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_FPCLK_AP_ERR_SHIFT (14U) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_FPCLK_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_FPCLK_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_FPCLK_AP_ERR_MASK) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_FPCLK_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_FPCLK_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_FPCLK_AP_ERR_SHIFT) + +/* + * MSK_ERR_HANDLE_AP_ERR (RW) + * + */ +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_HANDLE_AP_ERR_MASK (0x2000U) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_HANDLE_AP_ERR_SHIFT (13U) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_HANDLE_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_HANDLE_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_HANDLE_AP_ERR_MASK) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_HANDLE_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_HANDLE_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_HANDLE_AP_ERR_SHIFT) + +/* + * MSK_ERR_MSGR_AP_ERR (RW) + * + */ +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_MSGR_AP_ERR_MASK (0x1000U) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_MSGR_AP_ERR_SHIFT (12U) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_MSGR_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_MSGR_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_MSGR_AP_ERR_MASK) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_MSGR_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_MSGR_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_MSGR_AP_ERR_SHIFT) + +/* + * MSK_PREP_OUTS_AP_ERR (RW) + * + */ +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PREP_OUTS_AP_ERR_MASK (0xC00U) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PREP_OUTS_AP_ERR_SHIFT (10U) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PREP_OUTS_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PREP_OUTS_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PREP_OUTS_AP_ERR_MASK) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PREP_OUTS_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PREP_OUTS_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PREP_OUTS_AP_ERR_SHIFT) + +/* + * MSK_PACKET_ANALYZER_AP_ERR (RW) + * + */ +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PACKET_ANALYZER_AP_ERR_MASK (0x300U) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PACKET_ANALYZER_AP_ERR_SHIFT (8U) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PACKET_ANALYZER_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PACKET_ANALYZER_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PACKET_ANALYZER_AP_ERR_MASK) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PACKET_ANALYZER_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PACKET_ANALYZER_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PACKET_ANALYZER_AP_ERR_SHIFT) + +/* + * MSK_PHY_ADAPTER_AP_ERR (RW) + * + */ +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PHY_ADAPTER_AP_ERR_MASK (0x80U) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PHY_ADAPTER_AP_ERR_SHIFT (7U) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PHY_ADAPTER_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PHY_ADAPTER_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PHY_ADAPTER_AP_ERR_MASK) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PHY_ADAPTER_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PHY_ADAPTER_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PHY_ADAPTER_AP_ERR_SHIFT) + +/* + * MSK_DESCRAMBLER_AP_ERR (RW) + * + */ +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DESCRAMBLER_AP_ERR_MASK (0x40U) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DESCRAMBLER_AP_ERR_SHIFT (6U) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DESCRAMBLER_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DESCRAMBLER_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DESCRAMBLER_AP_ERR_MASK) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DESCRAMBLER_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DESCRAMBLER_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DESCRAMBLER_AP_ERR_SHIFT) + +/* + * MSK_PIPELINE_DELAY_AP_ERR (RW) + * + */ +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PIPELINE_DELAY_AP_ERR_MASK (0x20U) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PIPELINE_DELAY_AP_ERR_SHIFT (5U) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PIPELINE_DELAY_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PIPELINE_DELAY_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PIPELINE_DELAY_AP_ERR_MASK) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PIPELINE_DELAY_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PIPELINE_DELAY_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PIPELINE_DELAY_AP_ERR_SHIFT) + +/* + * MSK_DE_SKEW_AP_ERR (RW) + * + */ +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DE_SKEW_AP_ERR_MASK (0x10U) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DE_SKEW_AP_ERR_SHIFT (4U) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DE_SKEW_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DE_SKEW_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DE_SKEW_AP_ERR_MASK) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DE_SKEW_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DE_SKEW_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DE_SKEW_AP_ERR_SHIFT) + +/* + * MSK_REG_BANK_AP_ERR (RW) + * + */ +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_REG_BANK_AP_ERR_MASK (0xCU) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_REG_BANK_AP_ERR_SHIFT (2U) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_REG_BANK_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_REG_BANK_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_REG_BANK_AP_ERR_MASK) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_REG_BANK_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_REG_BANK_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_REG_BANK_AP_ERR_SHIFT) + +/* + * MSK_APB_AP_ERR (RW) + * + */ +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_APB_AP_ERR_MASK (0x3U) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_APB_AP_ERR_SHIFT (0U) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_APB_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_APB_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_APB_AP_ERR_MASK) +#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_APB_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_APB_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_APB_AP_ERR_SHIFT) + +/* Bitfield definition for register: INT_FORCE_AP_GENERIC */ +/* + * FORCE_SYNCHRONIZER_PIXCLK_AP_ERR (RW) + * + */ +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_PIXCLK_AP_ERR_MASK (0x10000UL) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_PIXCLK_AP_ERR_SHIFT (16U) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_PIXCLK_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_PIXCLK_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_PIXCLK_AP_ERR_MASK) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_PIXCLK_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_PIXCLK_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_PIXCLK_AP_ERR_SHIFT) + +/* + * FORCE_SYNCHRONIZER_RXBYTECLKHS_AP_ERR (RW) + * + */ +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_MASK (0x8000U) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_SHIFT (15U) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_MASK) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_SHIFT) + +/* + * FORCE_SYNCHRONIZER_FPCLK_AP_ERR (RW) + * + */ +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_FPCLK_AP_ERR_MASK (0x4000U) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_FPCLK_AP_ERR_SHIFT (14U) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_FPCLK_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_FPCLK_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_FPCLK_AP_ERR_MASK) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_FPCLK_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_FPCLK_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_FPCLK_AP_ERR_SHIFT) + +/* + * FORCE_ERR_HANDLE_AP_ERR (RW) + * + */ +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_HANDLE_AP_ERR_MASK (0x2000U) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_HANDLE_AP_ERR_SHIFT (13U) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_HANDLE_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_HANDLE_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_HANDLE_AP_ERR_MASK) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_HANDLE_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_HANDLE_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_HANDLE_AP_ERR_SHIFT) + +/* + * FORCE_ERR_MSGR_AP_ERR (RW) + * + */ +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_MSGR_AP_ERR_MASK (0x1000U) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_MSGR_AP_ERR_SHIFT (12U) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_MSGR_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_MSGR_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_MSGR_AP_ERR_MASK) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_MSGR_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_MSGR_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_MSGR_AP_ERR_SHIFT) + +/* + * FORCE_PREP_OUTS_AP_ERR (RW) + * + */ +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PREP_OUTS_AP_ERR_MASK (0xC00U) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PREP_OUTS_AP_ERR_SHIFT (10U) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PREP_OUTS_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PREP_OUTS_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PREP_OUTS_AP_ERR_MASK) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PREP_OUTS_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PREP_OUTS_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PREP_OUTS_AP_ERR_SHIFT) + +/* + * FORCE_PACKET_ANALYZER_AP_ERR (RW) + * + */ +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PACKET_ANALYZER_AP_ERR_MASK (0x300U) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PACKET_ANALYZER_AP_ERR_SHIFT (8U) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PACKET_ANALYZER_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PACKET_ANALYZER_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PACKET_ANALYZER_AP_ERR_MASK) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PACKET_ANALYZER_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PACKET_ANALYZER_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PACKET_ANALYZER_AP_ERR_SHIFT) + +/* + * FORCE_PHY_ADAPTER_AP_ERR (RW) + * + */ +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PHY_ADAPTER_AP_ERR_MASK (0x80U) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PHY_ADAPTER_AP_ERR_SHIFT (7U) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PHY_ADAPTER_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PHY_ADAPTER_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PHY_ADAPTER_AP_ERR_MASK) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PHY_ADAPTER_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PHY_ADAPTER_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PHY_ADAPTER_AP_ERR_SHIFT) + +/* + * FORCE_DESCRAMBLER_AP_ERR (RW) + * + */ +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DESCRAMBLER_AP_ERR_MASK (0x40U) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DESCRAMBLER_AP_ERR_SHIFT (6U) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DESCRAMBLER_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DESCRAMBLER_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DESCRAMBLER_AP_ERR_MASK) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DESCRAMBLER_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DESCRAMBLER_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DESCRAMBLER_AP_ERR_SHIFT) + +/* + * FORCE_PIPELINE_DELAY_AP_ERR (RW) + * + */ +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PIPELINE_DELAY_AP_ERR_MASK (0x20U) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PIPELINE_DELAY_AP_ERR_SHIFT (5U) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PIPELINE_DELAY_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PIPELINE_DELAY_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PIPELINE_DELAY_AP_ERR_MASK) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PIPELINE_DELAY_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PIPELINE_DELAY_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PIPELINE_DELAY_AP_ERR_SHIFT) + +/* + * FORCE_DE_SKEW_AP_ERR (RW) + * + */ +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DE_SKEW_AP_ERR_MASK (0x10U) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DE_SKEW_AP_ERR_SHIFT (4U) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DE_SKEW_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DE_SKEW_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DE_SKEW_AP_ERR_MASK) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DE_SKEW_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DE_SKEW_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DE_SKEW_AP_ERR_SHIFT) + +/* + * FORCE_REG_BANK_AP_ERR (RW) + * + */ +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_REG_BANK_AP_ERR_MASK (0xCU) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_REG_BANK_AP_ERR_SHIFT (2U) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_REG_BANK_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_REG_BANK_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_REG_BANK_AP_ERR_MASK) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_REG_BANK_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_REG_BANK_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_REG_BANK_AP_ERR_SHIFT) + +/* + * FORCE_APB_AP_ERR (RW) + * + */ +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_APB_AP_ERR_MASK (0x3U) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_APB_AP_ERR_SHIFT (0U) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_APB_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_APB_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_APB_AP_ERR_MASK) +#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_APB_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_APB_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_APB_AP_ERR_SHIFT) + +/* Bitfield definition for register: INT_ST_AP_IPI_FATAL */ +/* + * REDUNDANCY_ERR (RC) + * + * ap redundancy error in ipi1 + */ +#define MIPI_CSI_INT_ST_AP_IPI_FATAL_REDUNDANCY_ERR_MASK (0x20U) +#define MIPI_CSI_INT_ST_AP_IPI_FATAL_REDUNDANCY_ERR_SHIFT (5U) +#define MIPI_CSI_INT_ST_AP_IPI_FATAL_REDUNDANCY_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_IPI_FATAL_REDUNDANCY_ERR_MASK) >> MIPI_CSI_INT_ST_AP_IPI_FATAL_REDUNDANCY_ERR_SHIFT) + +/* + * CRC_ERR (RC) + * + * ap crc error in ipi1 + */ +#define MIPI_CSI_INT_ST_AP_IPI_FATAL_CRC_ERR_MASK (0x10U) +#define MIPI_CSI_INT_ST_AP_IPI_FATAL_CRC_ERR_SHIFT (4U) +#define MIPI_CSI_INT_ST_AP_IPI_FATAL_CRC_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_IPI_FATAL_CRC_ERR_MASK) >> MIPI_CSI_INT_ST_AP_IPI_FATAL_CRC_ERR_SHIFT) + +/* + * ECC_MULTIPLE_ERR (RC) + * + * ap ecc multiple error in ipi1 + */ +#define MIPI_CSI_INT_ST_AP_IPI_FATAL_ECC_MULTIPLE_ERR_MASK (0x8U) +#define MIPI_CSI_INT_ST_AP_IPI_FATAL_ECC_MULTIPLE_ERR_SHIFT (3U) +#define MIPI_CSI_INT_ST_AP_IPI_FATAL_ECC_MULTIPLE_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_IPI_FATAL_ECC_MULTIPLE_ERR_MASK) >> MIPI_CSI_INT_ST_AP_IPI_FATAL_ECC_MULTIPLE_ERR_SHIFT) + +/* + * ECC_SINGLE_ERR (RC) + * + * ap ecc sigle error in ipi1 + */ +#define MIPI_CSI_INT_ST_AP_IPI_FATAL_ECC_SINGLE_ERR_MASK (0x4U) +#define MIPI_CSI_INT_ST_AP_IPI_FATAL_ECC_SINGLE_ERR_SHIFT (2U) +#define MIPI_CSI_INT_ST_AP_IPI_FATAL_ECC_SINGLE_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_IPI_FATAL_ECC_SINGLE_ERR_MASK) >> MIPI_CSI_INT_ST_AP_IPI_FATAL_ECC_SINGLE_ERR_SHIFT) + +/* + * PARITY_RX_ERR (RC) + * + * ap parity rx error in ipi1 + */ +#define MIPI_CSI_INT_ST_AP_IPI_FATAL_PARITY_RX_ERR_MASK (0x2U) +#define MIPI_CSI_INT_ST_AP_IPI_FATAL_PARITY_RX_ERR_SHIFT (1U) +#define MIPI_CSI_INT_ST_AP_IPI_FATAL_PARITY_RX_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_IPI_FATAL_PARITY_RX_ERR_MASK) >> MIPI_CSI_INT_ST_AP_IPI_FATAL_PARITY_RX_ERR_SHIFT) + +/* + * PARITY_TX_ERR (RC) + * + * ap parity tx error in ipi1 + */ +#define MIPI_CSI_INT_ST_AP_IPI_FATAL_PARITY_TX_ERR_MASK (0x1U) +#define MIPI_CSI_INT_ST_AP_IPI_FATAL_PARITY_TX_ERR_SHIFT (0U) +#define MIPI_CSI_INT_ST_AP_IPI_FATAL_PARITY_TX_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_IPI_FATAL_PARITY_TX_ERR_MASK) >> MIPI_CSI_INT_ST_AP_IPI_FATAL_PARITY_TX_ERR_SHIFT) + +/* Bitfield definition for register: INT_MSK_AP_IPI_FATAL */ +/* + * MASK_REDUNDANCY_ERR (RC) + * + */ +#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_REDUNDANCY_ERR_MASK (0x20U) +#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_REDUNDANCY_ERR_SHIFT (5U) +#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_REDUNDANCY_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_REDUNDANCY_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_REDUNDANCY_ERR_SHIFT) + +/* + * MASK_CRC_ERR (RC) + * + */ +#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_CRC_ERR_MASK (0x10U) +#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_CRC_ERR_SHIFT (4U) +#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_CRC_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_CRC_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_CRC_ERR_SHIFT) + +/* + * MASK_ECC_MULTIPLE_ERR (RC) + * + */ +#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_ECC_MULTIPLE_ERR_MASK (0x8U) +#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_ECC_MULTIPLE_ERR_SHIFT (3U) +#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_ECC_MULTIPLE_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_ECC_MULTIPLE_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_ECC_MULTIPLE_ERR_SHIFT) + +/* + * MASK_ECC_SINGLE_ERR (RC) + * + */ +#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_ECC_SINGLE_ERR_MASK (0x4U) +#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_ECC_SINGLE_ERR_SHIFT (2U) +#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_ECC_SINGLE_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_ECC_SINGLE_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_ECC_SINGLE_ERR_SHIFT) + +/* + * MASK_PARITY_RX_ERR (RC) + * + */ +#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_PARITY_RX_ERR_MASK (0x2U) +#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_PARITY_RX_ERR_SHIFT (1U) +#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_PARITY_RX_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_PARITY_RX_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_PARITY_RX_ERR_SHIFT) + +/* + * MASK_PARITY_TX_ERR (RC) + * + */ +#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_PARITY_TX_ERR_MASK (0x1U) +#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_PARITY_TX_ERR_SHIFT (0U) +#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_PARITY_TX_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_PARITY_TX_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_PARITY_TX_ERR_SHIFT) + +/* Bitfield definition for register: INT_FORCE_AP_IPI_FATAL */ +/* + * FORCE_REDUNDANCY_ERR (RC) + * + */ +#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_REDUNDANCY_ERR_MASK (0x20U) +#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_REDUNDANCY_ERR_SHIFT (5U) +#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_REDUNDANCY_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_REDUNDANCY_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_REDUNDANCY_ERR_SHIFT) + +/* + * FORCE_CRC_ERR (RC) + * + */ +#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_CRC_ERR_MASK (0x10U) +#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_CRC_ERR_SHIFT (4U) +#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_CRC_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_CRC_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_CRC_ERR_SHIFT) + +/* + * FORCE_ECC_MULTIPLE_ERR (RC) + * + */ +#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_ECC_MULTIPLE_ERR_MASK (0x8U) +#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_ECC_MULTIPLE_ERR_SHIFT (3U) +#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_ECC_MULTIPLE_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_ECC_MULTIPLE_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_ECC_MULTIPLE_ERR_SHIFT) + +/* + * FORCE_ECC_SINGLE_ERR (RC) + * + */ +#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_ECC_SINGLE_ERR_MASK (0x4U) +#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_ECC_SINGLE_ERR_SHIFT (2U) +#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_ECC_SINGLE_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_ECC_SINGLE_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_ECC_SINGLE_ERR_SHIFT) + +/* + * FORCE_PARITY_RX_ERR (RC) + * + */ +#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_PARITY_RX_ERR_MASK (0x2U) +#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_PARITY_RX_ERR_SHIFT (1U) +#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_PARITY_RX_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_PARITY_RX_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_PARITY_RX_ERR_SHIFT) + +/* + * FORCE_PARITY_TX_ERR (RC) + * + */ +#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_PARITY_TX_ERR_MASK (0x1U) +#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_PARITY_TX_ERR_SHIFT (0U) +#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_PARITY_TX_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_PARITY_TX_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_PARITY_TX_ERR_SHIFT) + +/* Bitfield definition for register: INT_ST_BNDRY_FRAME_FATAL */ +/* + * ERR_F_BNDRY_MATCH_VC15 (RC) + * + * error matching frame start with frame end for virtual channel 15 + */ +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC15_MASK (0x8000U) +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC15_SHIFT (15U) +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC15_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC15_SHIFT) + +/* + * ERR_F_BNDRY_MATCH_VC14 (RC) + * + * error matching frame start with frame end for virtual channel 14 + */ +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC14_MASK (0x4000U) +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC14_SHIFT (14U) +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC14_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC14_SHIFT) + +/* + * ERR_F_BNDRY_MATCH_VC13 (RC) + * + * error matching frame start with frame end for virtual channel 13 + */ +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC13_MASK (0x2000U) +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC13_SHIFT (13U) +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC13_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC13_SHIFT) + +/* + * ERR_F_BNDRY_MATCH_VC12 (RC) + * + * error matching frame start with frame end for virtual channel 12 + */ +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC12_MASK (0x1000U) +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC12_SHIFT (12U) +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC12_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC12_SHIFT) + +/* + * ERR_F_BNDRY_MATCH_VC11 (RC) + * + * error matching frame start with frame end for virtual channel 11 + */ +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC11_MASK (0x800U) +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC11_SHIFT (11U) +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC11_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC11_SHIFT) + +/* + * ERR_F_BNDRY_MATCH_VC10 (RC) + * + * error matching frame start with frame end for virtual channel 10 + */ +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC10_MASK (0x400U) +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC10_SHIFT (10U) +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC10_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC10_SHIFT) + +/* + * ERR_F_BNDRY_MATCH_VC9 (RC) + * + * error matching frame start with frame end for virtual channel 9 + */ +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC9_MASK (0x200U) +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC9_SHIFT (9U) +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC9_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC9_SHIFT) + +/* + * ERR_F_BNDRY_MATCH_VC8 (RC) + * + * error matching frame start with frame end for virtual channel 8 + */ +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC8_MASK (0x100U) +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC8_SHIFT (8U) +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC8_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC8_SHIFT) + +/* + * ERR_F_BNDRY_MATCH_VC7 (RC) + * + * error matching frame start with frame end for virtual channel 7 + */ +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC7_MASK (0x80U) +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC7_SHIFT (7U) +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC7_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC7_SHIFT) + +/* + * ERR_F_BNDRY_MATCH_VC6 (RC) + * + * error matching frame start with frame end for virtual channel 6 + */ +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC6_MASK (0x40U) +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC6_SHIFT (6U) +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC6_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC6_SHIFT) + +/* + * ERR_F_BNDRY_MATCH_VC5 (RC) + * + * error matching frame start with frame end for virtual channel 5 + */ +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC5_MASK (0x20U) +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC5_SHIFT (5U) +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC5_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC5_SHIFT) + +/* + * ERR_F_BNDRY_MATCH_VC4 (RC) + * + * error matching frame start with frame end for virtual channel 4 + */ +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC4_MASK (0x10U) +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC4_SHIFT (4U) +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC4_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC4_SHIFT) + +/* + * ERR_F_BNDRY_MATCH_VC3 (RC) + * + * error matching frame start with frame end for virtual channel 3 + */ +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC3_MASK (0x8U) +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC3_SHIFT (3U) +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC3_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC3_SHIFT) + +/* + * ERR_F_BNDRY_MATCH_VC2 (RC) + * + * error matching frame start with frame end for virtual channel 2 + */ +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC2_MASK (0x4U) +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC2_SHIFT (2U) +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC2_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC2_SHIFT) + +/* + * ERR_F_BNDRY_MATCH_VC1 (RC) + * + * error matching frame start with frame end for virtual channel 1 + */ +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC1_MASK (0x2U) +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC1_SHIFT (1U) +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC1_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC1_SHIFT) + +/* + * ERR_F_BNDRY_MATCH_VC0 (RC) + * + * error matching frame start with frame end for virtual channel 0 + */ +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC0_MASK (0x1U) +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC0_SHIFT (0U) +#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC0_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC0_SHIFT) + +/* Bitfield definition for register: INT_MSK_BNDRY_FRAME_FATAL */ +/* + * MSK_ERR_F_BNDRY_MATCH_VC15 (RW) + * + * error matching frame start with frame end for virtual channel 15 + */ +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC15_MASK (0x8000U) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC15_SHIFT (15U) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC15_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC15_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC15_MASK) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC15_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC15_SHIFT) + +/* + * MSK_ERR_F_BNDRY_MATCH_VC14 (RW) + * + * error matching frame start with frame end for virtual channel 14 + */ +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC14_MASK (0x4000U) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC14_SHIFT (14U) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC14_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC14_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC14_MASK) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC14_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC14_SHIFT) + +/* + * MSK_ERR_F_BNDRY_MATCH_VC13 (RW) + * + * error matching frame start with frame end for virtual channel 13 + */ +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC13_MASK (0x2000U) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC13_SHIFT (13U) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC13_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC13_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC13_MASK) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC13_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC13_SHIFT) + +/* + * MSK_ERR_F_BNDRY_MATCH_VC12 (RW) + * + * error matching frame start with frame end for virtual channel 12 + */ +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC12_MASK (0x1000U) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC12_SHIFT (12U) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC12_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC12_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC12_MASK) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC12_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC12_SHIFT) + +/* + * MSK_ERR_F_BNDRY_MATCH_VC11 (RW) + * + * error matching frame start with frame end for virtual channel 11 + */ +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC11_MASK (0x800U) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC11_SHIFT (11U) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC11_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC11_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC11_MASK) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC11_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC11_SHIFT) + +/* + * MSK_ERR_F_BNDRY_MATCH_VC10 (RW) + * + * error matching frame start with frame end for virtual channel 10 + */ +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC10_MASK (0x400U) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC10_SHIFT (10U) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC10_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC10_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC10_MASK) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC10_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC10_SHIFT) + +/* + * MSK_ERR_F_BNDRY_MATCH_VC9 (RW) + * + * error matching frame start with frame end for virtual channel 9 + */ +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC9_MASK (0x200U) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC9_SHIFT (9U) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC9_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC9_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC9_MASK) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC9_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC9_SHIFT) + +/* + * MSK_ERR_F_BNDRY_MATCH_VC8 (RW) + * + * error matching frame start with frame end for virtual channel 8 + */ +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC8_MASK (0x100U) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC8_SHIFT (8U) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC8_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC8_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC8_MASK) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC8_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC8_SHIFT) + +/* + * MSK_ERR_F_BNDRY_MATCH_VC7 (RW) + * + * error matching frame start with frame end for virtual channel 7 + */ +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC7_MASK (0x80U) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC7_SHIFT (7U) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC7_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC7_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC7_MASK) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC7_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC7_SHIFT) + +/* + * MSK_ERR_F_BNDRY_MATCH_VC6 (RW) + * + * error matching frame start with frame end for virtual channel 6 + */ +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC6_MASK (0x40U) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC6_SHIFT (6U) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC6_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC6_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC6_MASK) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC6_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC6_SHIFT) + +/* + * MSK_ERR_F_BNDRY_MATCH_VC5 (RW) + * + * error matching frame start with frame end for virtual channel 5 + */ +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC5_MASK (0x20U) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC5_SHIFT (5U) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC5_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC5_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC5_MASK) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC5_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC5_SHIFT) + +/* + * MSK_ERR_F_BNDRY_MATCH_VC4 (RW) + * + * error matching frame start with frame end for virtual channel 4 + */ +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC4_MASK (0x10U) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC4_SHIFT (4U) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC4_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC4_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC4_MASK) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC4_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC4_SHIFT) + +/* + * MSK_ERR_F_BNDRY_MATCH_VC3 (RW) + * + * error matching frame start with frame end for virtual channel 3 + */ +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC3_MASK (0x8U) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC3_SHIFT (3U) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC3_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC3_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC3_MASK) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC3_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC3_SHIFT) + +/* + * MSK_ERR_F_BNDRY_MATCH_VC2 (RW) + * + * error matching frame start with frame end for virtual channel 2 + */ +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC2_MASK (0x4U) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC2_SHIFT (2U) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC2_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC2_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC2_MASK) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC2_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC2_SHIFT) + +/* + * MSK_ERR_F_BNDRY_MATCH_VC1 (RW) + * + * error matching frame start with frame end for virtual channel 1 + */ +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC1_MASK (0x2U) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC1_SHIFT (1U) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC1_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC1_MASK) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC1_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC1_SHIFT) + +/* + * MSK_ERR_F_BNDRY_MATCH_VC0 (RW) + * + * error matching frame start with frame end for virtual channel 0 + */ +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC0_MASK (0x1U) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC0_SHIFT (0U) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC0_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC0_MASK) +#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC0_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC0_SHIFT) + +/* Bitfield definition for register: INT_FORCE_BNDRY_FRAME_FATAL */ +/* + * FORCE_ERR_F_BNDRY_MATCH_VC15 (RW) + * + * error matching frame start with frame end for virtual channel 15 + */ +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC15_MASK (0x8000U) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC15_SHIFT (15U) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC15_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC15_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC15_MASK) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC15_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC15_SHIFT) + +/* + * FORCE_ERR_F_BNDRY_MATCH_VC14 (RW) + * + * error matching frame start with frame end for virtual channel 14 + */ +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC14_MASK (0x4000U) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC14_SHIFT (14U) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC14_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC14_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC14_MASK) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC14_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC14_SHIFT) + +/* + * FORCE_ERR_F_BNDRY_MATCH_VC13 (RW) + * + * error matching frame start with frame end for virtual channel 13 + */ +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC13_MASK (0x2000U) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC13_SHIFT (13U) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC13_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC13_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC13_MASK) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC13_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC13_SHIFT) + +/* + * FORCE_ERR_F_BNDRY_MATCH_VC12 (RW) + * + * error matching frame start with frame end for virtual channel 12 + */ +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC12_MASK (0x1000U) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC12_SHIFT (12U) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC12_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC12_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC12_MASK) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC12_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC12_SHIFT) + +/* + * FORCE_ERR_F_BNDRY_MATCH_VC11 (RW) + * + * error matching frame start with frame end for virtual channel 11 + */ +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC11_MASK (0x800U) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC11_SHIFT (11U) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC11_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC11_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC11_MASK) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC11_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC11_SHIFT) + +/* + * FORCE_ERR_F_BNDRY_MATCH_VC10 (RW) + * + * error matching frame start with frame end for virtual channel 10 + */ +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC10_MASK (0x400U) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC10_SHIFT (10U) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC10_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC10_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC10_MASK) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC10_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC10_SHIFT) + +/* + * FORCE_ERR_F_BNDRY_MATCH_VC9 (RW) + * + * error matching frame start with frame end for virtual channel 9 + */ +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC9_MASK (0x200U) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC9_SHIFT (9U) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC9_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC9_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC9_MASK) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC9_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC9_SHIFT) + +/* + * FORCE_ERR_F_BNDRY_MATCH_VC8 (RW) + * + * error matching frame start with frame end for virtual channel 8 + */ +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC8_MASK (0x100U) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC8_SHIFT (8U) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC8_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC8_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC8_MASK) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC8_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC8_SHIFT) + +/* + * FORCE_ERR_F_BNDRY_MATCH_VC7 (RW) + * + * error matching frame start with frame end for virtual channel 7 + */ +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC7_MASK (0x80U) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC7_SHIFT (7U) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC7_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC7_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC7_MASK) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC7_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC7_SHIFT) + +/* + * FORCE_ERR_F_BNDRY_MATCH_VC6 (RW) + * + * error matching frame start with frame end for virtual channel 6 + */ +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC6_MASK (0x40U) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC6_SHIFT (6U) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC6_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC6_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC6_MASK) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC6_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC6_SHIFT) + +/* + * FORCE_ERR_F_BNDRY_MATCH_VC5 (RW) + * + * error matching frame start with frame end for virtual channel 5 + */ +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC5_MASK (0x20U) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC5_SHIFT (5U) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC5_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC5_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC5_MASK) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC5_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC5_SHIFT) + +/* + * FORCE_ERR_F_BNDRY_MATCH_VC4 (RW) + * + * error matching frame start with frame end for virtual channel 4 + */ +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC4_MASK (0x10U) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC4_SHIFT (4U) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC4_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC4_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC4_MASK) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC4_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC4_SHIFT) + +/* + * FORCE_ERR_F_BNDRY_MATCH_VC3 (RW) + * + * error matching frame start with frame end for virtual channel 3 + */ +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC3_MASK (0x8U) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC3_SHIFT (3U) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC3_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC3_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC3_MASK) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC3_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC3_SHIFT) + +/* + * FORCE_ERR_F_BNDRY_MATCH_VC2 (RW) + * + * error matching frame start with frame end for virtual channel 2 + */ +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC2_MASK (0x4U) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC2_SHIFT (2U) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC2_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC2_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC2_MASK) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC2_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC2_SHIFT) + +/* + * FORCE_ERR_F_BNDRY_MATCH_VC1 (RW) + * + * error matching frame start with frame end for virtual channel 1 + */ +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC1_MASK (0x2U) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC1_SHIFT (1U) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC1_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC1_MASK) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC1_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC1_SHIFT) + +/* + * FORCE_ERR_F_BNDRY_MATCH_VC0 (RW) + * + * error matching frame start with frame end for virtual channel 0 + */ +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC0_MASK (0x1U) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC0_SHIFT (0U) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC0_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC0_MASK) +#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC0_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC0_SHIFT) + +/* Bitfield definition for register: INT_ST_SEQ_FRAME_FATAL */ +/* + * ERR_F_SEQ_MATCH_VC15 (RC) + * + * error matching frame start with frame end for virtual channel 15 + */ +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC15_MASK (0x8000U) +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC15_SHIFT (15U) +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC15_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC15_SHIFT) + +/* + * ERR_F_SEQ_MATCH_VC14 (RC) + * + * error matching frame start with frame end for virtual channel 14 + */ +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC14_MASK (0x4000U) +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC14_SHIFT (14U) +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC14_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC14_SHIFT) + +/* + * ERR_F_SEQ_MATCH_VC13 (RC) + * + * error matching frame start with frame end for virtual channel 13 + */ +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC13_MASK (0x2000U) +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC13_SHIFT (13U) +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC13_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC13_SHIFT) + +/* + * ERR_F_SEQ_MATCH_VC12 (RC) + * + * error matching frame start with frame end for virtual channel 12 + */ +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC12_MASK (0x1000U) +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC12_SHIFT (12U) +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC12_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC12_SHIFT) + +/* + * ERR_F_SEQ_MATCH_VC11 (RC) + * + * error matching frame start with frame end for virtual channel 11 + */ +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC11_MASK (0x800U) +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC11_SHIFT (11U) +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC11_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC11_SHIFT) + +/* + * ERR_F_SEQ_MATCH_VC10 (RC) + * + * error matching frame start with frame end for virtual channel 10 + */ +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC10_MASK (0x400U) +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC10_SHIFT (10U) +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC10_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC10_SHIFT) + +/* + * ERR_F_SEQ_MATCH_VC9 (RC) + * + * error matching frame start with frame end for virtual channel 9 + */ +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC9_MASK (0x200U) +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC9_SHIFT (9U) +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC9_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC9_SHIFT) + +/* + * ERR_F_SEQ_MATCH_VC8 (RC) + * + * error matching frame start with frame end for virtual channel 8 + */ +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC8_MASK (0x100U) +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC8_SHIFT (8U) +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC8_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC8_SHIFT) + +/* + * ERR_F_SEQ_MATCH_VC7 (RC) + * + * error matching frame start with frame end for virtual channel 7 + */ +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC7_MASK (0x80U) +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC7_SHIFT (7U) +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC7_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC7_SHIFT) + +/* + * ERR_F_SEQ_MATCH_VC6 (RC) + * + * error matching frame start with frame end for virtual channel 6 + */ +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC6_MASK (0x40U) +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC6_SHIFT (6U) +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC6_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC6_SHIFT) + +/* + * ERR_F_SEQ_MATCH_VC5 (RC) + * + * error matching frame start with frame end for virtual channel 5 + */ +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC5_MASK (0x20U) +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC5_SHIFT (5U) +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC5_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC5_SHIFT) + +/* + * ERR_F_SEQ_MATCH_VC4 (RC) + * + * error matching frame start with frame end for virtual channel 4 + */ +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC4_MASK (0x10U) +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC4_SHIFT (4U) +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC4_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC4_SHIFT) + +/* + * ERR_F_SEQ_MATCH_VC3 (RC) + * + * error matching frame start with frame end for virtual channel 3 + */ +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC3_MASK (0x8U) +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC3_SHIFT (3U) +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC3_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC3_SHIFT) + +/* + * ERR_F_SEQ_MATCH_VC2 (RC) + * + * error matching frame start with frame end for virtual channel 2 + */ +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC2_MASK (0x4U) +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC2_SHIFT (2U) +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC2_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC2_SHIFT) + +/* + * ERR_F_SEQ_MATCH_VC1 (RC) + * + * error matching frame start with frame end for virtual channel 1 + */ +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC1_MASK (0x2U) +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC1_SHIFT (1U) +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC1_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC1_SHIFT) + +/* + * ERR_F_SEQ_MATCH_VC0 (RC) + * + * error matching frame start with frame end for virtual channel 0 + */ +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC0_MASK (0x1U) +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC0_SHIFT (0U) +#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC0_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC0_SHIFT) + +/* Bitfield definition for register: INT_MSK_SEQ_FRAME_FATAL */ +/* + * MSK_ERR_F_SEQ_MATCH_VC15 (RW) + * + * error matching frame start with frame end for virtual channel 15 + */ +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC15_MASK (0x8000U) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC15_SHIFT (15U) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC15_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC15_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC15_MASK) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC15_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC15_SHIFT) + +/* + * MSK_ERR_F_SEQ_MATCH_VC14 (RW) + * + * error matching frame start with frame end for virtual channel 14 + */ +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC14_MASK (0x4000U) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC14_SHIFT (14U) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC14_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC14_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC14_MASK) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC14_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC14_SHIFT) + +/* + * MSK_ERR_F_SEQ_MATCH_VC13 (RW) + * + * error matching frame start with frame end for virtual channel 13 + */ +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC13_MASK (0x2000U) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC13_SHIFT (13U) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC13_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC13_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC13_MASK) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC13_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC13_SHIFT) + +/* + * MSK_ERR_F_SEQ_MATCH_VC12 (RW) + * + * error matching frame start with frame end for virtual channel 12 + */ +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC12_MASK (0x1000U) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC12_SHIFT (12U) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC12_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC12_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC12_MASK) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC12_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC12_SHIFT) + +/* + * MSK_ERR_F_SEQ_MATCH_VC11 (RW) + * + * error matching frame start with frame end for virtual channel 11 + */ +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC11_MASK (0x800U) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC11_SHIFT (11U) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC11_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC11_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC11_MASK) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC11_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC11_SHIFT) + +/* + * MSK_ERR_F_SEQ_MATCH_VC10 (RW) + * + * error matching frame start with frame end for virtual channel 10 + */ +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC10_MASK (0x400U) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC10_SHIFT (10U) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC10_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC10_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC10_MASK) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC10_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC10_SHIFT) + +/* + * MSK_ERR_F_SEQ_MATCH_VC9 (RW) + * + * error matching frame start with frame end for virtual channel 9 + */ +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC9_MASK (0x200U) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC9_SHIFT (9U) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC9_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC9_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC9_MASK) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC9_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC9_SHIFT) + +/* + * MSK_ERR_F_SEQ_MATCH_VC8 (RW) + * + * error matching frame start with frame end for virtual channel 8 + */ +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC8_MASK (0x100U) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC8_SHIFT (8U) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC8_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC8_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC8_MASK) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC8_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC8_SHIFT) + +/* + * MSK_ERR_F_SEQ_MATCH_VC7 (RW) + * + * error matching frame start with frame end for virtual channel 7 + */ +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC7_MASK (0x80U) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC7_SHIFT (7U) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC7_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC7_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC7_MASK) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC7_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC7_SHIFT) + +/* + * MSK_ERR_F_SEQ_MATCH_VC6 (RW) + * + * error matching frame start with frame end for virtual channel 6 + */ +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC6_MASK (0x40U) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC6_SHIFT (6U) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC6_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC6_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC6_MASK) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC6_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC6_SHIFT) + +/* + * MSK_ERR_F_SEQ_MATCH_VC5 (RW) + * + * error matching frame start with frame end for virtual channel 5 + */ +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC5_MASK (0x20U) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC5_SHIFT (5U) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC5_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC5_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC5_MASK) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC5_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC5_SHIFT) + +/* + * MSK_ERR_F_SEQ_MATCH_VC4 (RW) + * + * error matching frame start with frame end for virtual channel 4 + */ +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC4_MASK (0x10U) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC4_SHIFT (4U) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC4_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC4_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC4_MASK) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC4_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC4_SHIFT) + +/* + * MSK_ERR_F_SEQ_MATCH_VC3 (RW) + * + * error matching frame start with frame end for virtual channel 3 + */ +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC3_MASK (0x8U) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC3_SHIFT (3U) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC3_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC3_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC3_MASK) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC3_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC3_SHIFT) + +/* + * MSK_ERR_F_SEQ_MATCH_VC2 (RW) + * + * error matching frame start with frame end for virtual channel 2 + */ +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC2_MASK (0x4U) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC2_SHIFT (2U) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC2_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC2_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC2_MASK) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC2_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC2_SHIFT) + +/* + * MSK_ERR_F_SEQ_MATCH_VC1 (RW) + * + * error matching frame start with frame end for virtual channel 1 + */ +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC1_MASK (0x2U) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC1_SHIFT (1U) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC1_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC1_MASK) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC1_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC1_SHIFT) + +/* + * MSK_ERR_F_SEQ_MATCH_VC0 (RW) + * + * error matching frame start with frame end for virtual channel 0 + */ +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC0_MASK (0x1U) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC0_SHIFT (0U) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC0_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC0_MASK) +#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC0_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC0_SHIFT) + +/* Bitfield definition for register: INT_FORCE_SEQ_FRAME_FATAL */ +/* + * FORCE_ERR_F_SEQ_MATCH_VC15 (RW) + * + * error matching frame start with frame end for virtual channel 15 + */ +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC15_MASK (0x8000U) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC15_SHIFT (15U) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC15_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC15_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC15_MASK) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC15_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC15_SHIFT) + +/* + * FORCE_ERR_F_SEQ_MATCH_VC14 (RW) + * + * error matching frame start with frame end for virtual channel 14 + */ +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC14_MASK (0x4000U) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC14_SHIFT (14U) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC14_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC14_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC14_MASK) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC14_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC14_SHIFT) + +/* + * FORCE_ERR_F_SEQ_MATCH_VC13 (RW) + * + * error matching frame start with frame end for virtual channel 13 + */ +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC13_MASK (0x2000U) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC13_SHIFT (13U) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC13_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC13_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC13_MASK) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC13_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC13_SHIFT) + +/* + * FORCE_ERR_F_SEQ_MATCH_VC12 (RW) + * + * error matching frame start with frame end for virtual channel 12 + */ +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC12_MASK (0x1000U) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC12_SHIFT (12U) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC12_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC12_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC12_MASK) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC12_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC12_SHIFT) + +/* + * FORCE_ERR_F_SEQ_MATCH_VC11 (RW) + * + * error matching frame start with frame end for virtual channel 11 + */ +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC11_MASK (0x800U) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC11_SHIFT (11U) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC11_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC11_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC11_MASK) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC11_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC11_SHIFT) + +/* + * FORCE_ERR_F_SEQ_MATCH_VC10 (RW) + * + * error matching frame start with frame end for virtual channel 10 + */ +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC10_MASK (0x400U) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC10_SHIFT (10U) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC10_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC10_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC10_MASK) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC10_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC10_SHIFT) + +/* + * FORCE_ERR_F_SEQ_MATCH_VC9 (RW) + * + * error matching frame start with frame end for virtual channel 9 + */ +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC9_MASK (0x200U) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC9_SHIFT (9U) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC9_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC9_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC9_MASK) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC9_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC9_SHIFT) + +/* + * FORCE_ERR_F_SEQ_MATCH_VC8 (RW) + * + * error matching frame start with frame end for virtual channel 8 + */ +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC8_MASK (0x100U) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC8_SHIFT (8U) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC8_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC8_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC8_MASK) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC8_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC8_SHIFT) + +/* + * FORCE_ERR_F_SEQ_MATCH_VC7 (RW) + * + * error matching frame start with frame end for virtual channel 7 + */ +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC7_MASK (0x80U) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC7_SHIFT (7U) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC7_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC7_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC7_MASK) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC7_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC7_SHIFT) + +/* + * FORCE_ERR_F_SEQ_MATCH_VC6 (RW) + * + * error matching frame start with frame end for virtual channel 6 + */ +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC6_MASK (0x40U) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC6_SHIFT (6U) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC6_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC6_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC6_MASK) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC6_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC6_SHIFT) + +/* + * FORCE_ERR_F_SEQ_MATCH_VC5 (RW) + * + * error matching frame start with frame end for virtual channel 5 + */ +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC5_MASK (0x20U) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC5_SHIFT (5U) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC5_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC5_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC5_MASK) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC5_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC5_SHIFT) + +/* + * FORCE_ERR_F_SEQ_MATCH_VC4 (RW) + * + * error matching frame start with frame end for virtual channel 4 + */ +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC4_MASK (0x10U) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC4_SHIFT (4U) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC4_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC4_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC4_MASK) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC4_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC4_SHIFT) + +/* + * FORCE_ERR_F_SEQ_MATCH_VC3 (RW) + * + * error matching frame start with frame end for virtual channel 3 + */ +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC3_MASK (0x8U) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC3_SHIFT (3U) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC3_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC3_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC3_MASK) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC3_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC3_SHIFT) + +/* + * FORCE_ERR_F_SEQ_MATCH_VC2 (RW) + * + * error matching frame start with frame end for virtual channel 2 + */ +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC2_MASK (0x4U) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC2_SHIFT (2U) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC2_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC2_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC2_MASK) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC2_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC2_SHIFT) + +/* + * FORCE_ERR_F_SEQ_MATCH_VC1 (RW) + * + * error matching frame start with frame end for virtual channel 1 + */ +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC1_MASK (0x2U) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC1_SHIFT (1U) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC1_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC1_MASK) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC1_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC1_SHIFT) + +/* + * FORCE_ERR_F_SEQ_MATCH_VC0 (RW) + * + * error matching frame start with frame end for virtual channel 0 + */ +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC0_MASK (0x1U) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC0_SHIFT (0U) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC0_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC0_MASK) +#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC0_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC0_SHIFT) + +/* Bitfield definition for register: INT_ST_CRC_FRAME_FATAL */ +/* + * ERR_F_CRC_MATCH_VC15 (RC) + * + * error matching frame start with frame end for virtual channel 15 + */ +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC15_MASK (0x8000U) +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC15_SHIFT (15U) +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC15_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC15_SHIFT) + +/* + * ERR_F_CRC_MATCH_VC14 (RC) + * + * error matching frame start with frame end for virtual channel 14 + */ +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC14_MASK (0x4000U) +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC14_SHIFT (14U) +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC14_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC14_SHIFT) + +/* + * ERR_F_CRC_MATCH_VC13 (RC) + * + * error matching frame start with frame end for virtual channel 13 + */ +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC13_MASK (0x2000U) +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC13_SHIFT (13U) +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC13_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC13_SHIFT) + +/* + * ERR_F_CRC_MATCH_VC12 (RC) + * + * error matching frame start with frame end for virtual channel 12 + */ +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC12_MASK (0x1000U) +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC12_SHIFT (12U) +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC12_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC12_SHIFT) + +/* + * ERR_F_CRC_MATCH_VC11 (RC) + * + * error matching frame start with frame end for virtual channel 11 + */ +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC11_MASK (0x800U) +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC11_SHIFT (11U) +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC11_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC11_SHIFT) + +/* + * ERR_F_CRC_MATCH_VC10 (RC) + * + * error matching frame start with frame end for virtual channel 10 + */ +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC10_MASK (0x400U) +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC10_SHIFT (10U) +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC10_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC10_SHIFT) + +/* + * ERR_F_CRC_MATCH_VC9 (RC) + * + * error matching frame start with frame end for virtual channel 9 + */ +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC9_MASK (0x200U) +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC9_SHIFT (9U) +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC9_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC9_SHIFT) + +/* + * ERR_F_CRC_MATCH_VC8 (RC) + * + * error matching frame start with frame end for virtual channel 8 + */ +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC8_MASK (0x100U) +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC8_SHIFT (8U) +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC8_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC8_SHIFT) + +/* + * ERR_F_CRC_MATCH_VC7 (RC) + * + * error matching frame start with frame end for virtual channel 7 + */ +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC7_MASK (0x80U) +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC7_SHIFT (7U) +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC7_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC7_SHIFT) + +/* + * ERR_F_CRC_MATCH_VC6 (RC) + * + * error matching frame start with frame end for virtual channel 6 + */ +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC6_MASK (0x40U) +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC6_SHIFT (6U) +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC6_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC6_SHIFT) + +/* + * ERR_F_CRC_MATCH_VC5 (RC) + * + * error matching frame start with frame end for virtual channel 5 + */ +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC5_MASK (0x20U) +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC5_SHIFT (5U) +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC5_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC5_SHIFT) + +/* + * ERR_F_CRC_MATCH_VC4 (RC) + * + * error matching frame start with frame end for virtual channel 4 + */ +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC4_MASK (0x10U) +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC4_SHIFT (4U) +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC4_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC4_SHIFT) + +/* + * ERR_F_CRC_MATCH_VC3 (RC) + * + * error matching frame start with frame end for virtual channel 3 + */ +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC3_MASK (0x8U) +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC3_SHIFT (3U) +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC3_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC3_SHIFT) + +/* + * ERR_F_CRC_MATCH_VC2 (RC) + * + * error matching frame start with frame end for virtual channel 2 + */ +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC2_MASK (0x4U) +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC2_SHIFT (2U) +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC2_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC2_SHIFT) + +/* + * ERR_F_CRC_MATCH_VC1 (RC) + * + * error matching frame start with frame end for virtual channel 1 + */ +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC1_MASK (0x2U) +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC1_SHIFT (1U) +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC1_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC1_SHIFT) + +/* + * ERR_F_CRC_MATCH_VC0 (RC) + * + * error matching frame start with frame end for virtual channel 0 + */ +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC0_MASK (0x1U) +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC0_SHIFT (0U) +#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC0_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC0_SHIFT) + +/* Bitfield definition for register: INT_MSK_CRC_FRAME_FATAL */ +/* + * MSK_ERR_F_CRC_MATCH_VC15 (RW) + * + * error matching frame start with frame end for virtual channel 15 + */ +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC15_MASK (0x8000U) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC15_SHIFT (15U) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC15_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC15_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC15_MASK) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC15_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC15_SHIFT) + +/* + * MSK_ERR_F_CRC_MATCH_VC14 (RW) + * + * error matching frame start with frame end for virtual channel 14 + */ +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC14_MASK (0x4000U) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC14_SHIFT (14U) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC14_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC14_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC14_MASK) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC14_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC14_SHIFT) + +/* + * MSK_ERR_F_CRC_MATCH_VC13 (RW) + * + * error matching frame start with frame end for virtual channel 13 + */ +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC13_MASK (0x2000U) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC13_SHIFT (13U) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC13_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC13_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC13_MASK) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC13_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC13_SHIFT) + +/* + * MSK_ERR_F_CRC_MATCH_VC12 (RW) + * + * error matching frame start with frame end for virtual channel 12 + */ +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC12_MASK (0x1000U) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC12_SHIFT (12U) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC12_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC12_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC12_MASK) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC12_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC12_SHIFT) + +/* + * MSK_ERR_F_CRC_MATCH_VC11 (RW) + * + * error matching frame start with frame end for virtual channel 11 + */ +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC11_MASK (0x800U) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC11_SHIFT (11U) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC11_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC11_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC11_MASK) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC11_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC11_SHIFT) + +/* + * MSK_ERR_F_CRC_MATCH_VC10 (RW) + * + * error matching frame start with frame end for virtual channel 10 + */ +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC10_MASK (0x400U) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC10_SHIFT (10U) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC10_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC10_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC10_MASK) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC10_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC10_SHIFT) + +/* + * MSK_ERR_F_CRC_MATCH_VC9 (RW) + * + * error matching frame start with frame end for virtual channel 9 + */ +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC9_MASK (0x200U) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC9_SHIFT (9U) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC9_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC9_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC9_MASK) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC9_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC9_SHIFT) + +/* + * MSK_ERR_F_CRC_MATCH_VC8 (RW) + * + * error matching frame start with frame end for virtual channel 8 + */ +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC8_MASK (0x100U) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC8_SHIFT (8U) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC8_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC8_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC8_MASK) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC8_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC8_SHIFT) + +/* + * MSK_ERR_F_CRC_MATCH_VC7 (RW) + * + * error matching frame start with frame end for virtual channel 7 + */ +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC7_MASK (0x80U) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC7_SHIFT (7U) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC7_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC7_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC7_MASK) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC7_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC7_SHIFT) + +/* + * MSK_ERR_F_CRC_MATCH_VC6 (RW) + * + * error matching frame start with frame end for virtual channel 6 + */ +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC6_MASK (0x40U) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC6_SHIFT (6U) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC6_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC6_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC6_MASK) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC6_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC6_SHIFT) + +/* + * MSK_ERR_F_CRC_MATCH_VC5 (RW) + * + * error matching frame start with frame end for virtual channel 5 + */ +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC5_MASK (0x20U) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC5_SHIFT (5U) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC5_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC5_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC5_MASK) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC5_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC5_SHIFT) + +/* + * MSK_ERR_F_CRC_MATCH_VC4 (RW) + * + * error matching frame start with frame end for virtual channel 4 + */ +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC4_MASK (0x10U) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC4_SHIFT (4U) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC4_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC4_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC4_MASK) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC4_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC4_SHIFT) + +/* + * MSK_ERR_F_CRC_MATCH_VC3 (RW) + * + * error matching frame start with frame end for virtual channel 3 + */ +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC3_MASK (0x8U) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC3_SHIFT (3U) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC3_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC3_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC3_MASK) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC3_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC3_SHIFT) + +/* + * MSK_ERR_F_CRC_MATCH_VC2 (RW) + * + * error matching frame start with frame end for virtual channel 2 + */ +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC2_MASK (0x4U) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC2_SHIFT (2U) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC2_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC2_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC2_MASK) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC2_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC2_SHIFT) + +/* + * MSK_ERR_F_CRC_MATCH_VC1 (RW) + * + * error matching frame start with frame end for virtual channel 1 + */ +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC1_MASK (0x2U) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC1_SHIFT (1U) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC1_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC1_MASK) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC1_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC1_SHIFT) + +/* + * MSK_ERR_F_CRC_MATCH_VC0 (RW) + * + * error matching frame start with frame end for virtual channel 0 + */ +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC0_MASK (0x1U) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC0_SHIFT (0U) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC0_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC0_MASK) +#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC0_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC0_SHIFT) + +/* Bitfield definition for register: INT_FORCE_CRC_FRAME_FATAL */ +/* + * FORCE_ERR_F_CRC_MATCH_VC15 (RW) + * + * error matching frame start with frame end for virtual channel 15 + */ +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC15_MASK (0x8000U) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC15_SHIFT (15U) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC15_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC15_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC15_MASK) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC15_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC15_SHIFT) + +/* + * FORCE_ERR_F_CRC_MATCH_VC14 (RW) + * + * error matching frame start with frame end for virtual channel 14 + */ +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC14_MASK (0x4000U) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC14_SHIFT (14U) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC14_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC14_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC14_MASK) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC14_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC14_SHIFT) + +/* + * FORCE_ERR_F_CRC_MATCH_VC13 (RW) + * + * error matching frame start with frame end for virtual channel 13 + */ +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC13_MASK (0x2000U) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC13_SHIFT (13U) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC13_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC13_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC13_MASK) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC13_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC13_SHIFT) + +/* + * FORCE_ERR_F_CRC_MATCH_VC12 (RW) + * + * error matching frame start with frame end for virtual channel 12 + */ +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC12_MASK (0x1000U) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC12_SHIFT (12U) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC12_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC12_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC12_MASK) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC12_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC12_SHIFT) + +/* + * FORCE_ERR_F_CRC_MATCH_VC11 (RW) + * + * error matching frame start with frame end for virtual channel 11 + */ +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC11_MASK (0x800U) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC11_SHIFT (11U) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC11_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC11_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC11_MASK) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC11_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC11_SHIFT) + +/* + * FORCE_ERR_F_CRC_MATCH_VC10 (RW) + * + * error matching frame start with frame end for virtual channel 10 + */ +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC10_MASK (0x400U) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC10_SHIFT (10U) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC10_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC10_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC10_MASK) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC10_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC10_SHIFT) + +/* + * FORCE_ERR_F_CRC_MATCH_VC9 (RW) + * + * error matching frame start with frame end for virtual channel 9 + */ +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC9_MASK (0x200U) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC9_SHIFT (9U) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC9_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC9_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC9_MASK) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC9_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC9_SHIFT) + +/* + * FORCE_ERR_F_CRC_MATCH_VC8 (RW) + * + * error matching frame start with frame end for virtual channel 8 + */ +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC8_MASK (0x100U) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC8_SHIFT (8U) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC8_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC8_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC8_MASK) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC8_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC8_SHIFT) + +/* + * FORCE_ERR_F_CRC_MATCH_VC7 (RW) + * + * error matching frame start with frame end for virtual channel 7 + */ +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC7_MASK (0x80U) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC7_SHIFT (7U) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC7_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC7_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC7_MASK) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC7_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC7_SHIFT) + +/* + * FORCE_ERR_F_CRC_MATCH_VC6 (RW) + * + * error matching frame start with frame end for virtual channel 6 + */ +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC6_MASK (0x40U) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC6_SHIFT (6U) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC6_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC6_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC6_MASK) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC6_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC6_SHIFT) + +/* + * FORCE_ERR_F_CRC_MATCH_VC5 (RW) + * + * error matching frame start with frame end for virtual channel 5 + */ +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC5_MASK (0x20U) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC5_SHIFT (5U) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC5_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC5_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC5_MASK) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC5_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC5_SHIFT) + +/* + * FORCE_ERR_F_CRC_MATCH_VC4 (RW) + * + * error matching frame start with frame end for virtual channel 4 + */ +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC4_MASK (0x10U) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC4_SHIFT (4U) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC4_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC4_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC4_MASK) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC4_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC4_SHIFT) + +/* + * FORCE_ERR_F_CRC_MATCH_VC3 (RW) + * + * error matching frame start with frame end for virtual channel 3 + */ +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC3_MASK (0x8U) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC3_SHIFT (3U) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC3_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC3_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC3_MASK) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC3_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC3_SHIFT) + +/* + * FORCE_ERR_F_CRC_MATCH_VC2 (RW) + * + * error matching frame start with frame end for virtual channel 2 + */ +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC2_MASK (0x4U) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC2_SHIFT (2U) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC2_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC2_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC2_MASK) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC2_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC2_SHIFT) + +/* + * FORCE_ERR_F_CRC_MATCH_VC1 (RW) + * + * error matching frame start with frame end for virtual channel 1 + */ +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC1_MASK (0x2U) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC1_SHIFT (1U) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC1_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC1_MASK) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC1_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC1_SHIFT) + +/* + * FORCE_ERR_F_CRC_MATCH_VC0 (RW) + * + * error matching frame start with frame end for virtual channel 0 + */ +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC0_MASK (0x1U) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC0_SHIFT (0U) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC0_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC0_MASK) +#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC0_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC0_SHIFT) + +/* Bitfield definition for register: INT_ST_PLD_CRC_FRAME_FATAL */ +/* + * ERR_CRC_MATCH_VC15 (RC) + * + * error matching frame start with frame end for virtual channel 15 + */ +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC15_MASK (0x8000U) +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC15_SHIFT (15U) +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC15_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC15_SHIFT) + +/* + * ERR_CRC_MATCH_VC14 (RC) + * + * error matching frame start with frame end for virtual channel 14 + */ +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC14_MASK (0x4000U) +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC14_SHIFT (14U) +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC14_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC14_SHIFT) + +/* + * ERR_CRC_MATCH_VC13 (RC) + * + * error matching frame start with frame end for virtual channel 13 + */ +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC13_MASK (0x2000U) +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC13_SHIFT (13U) +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC13_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC13_SHIFT) + +/* + * ERR_CRC_MATCH_VC12 (RC) + * + * error matching frame start with frame end for virtual channel 12 + */ +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC12_MASK (0x1000U) +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC12_SHIFT (12U) +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC12_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC12_SHIFT) + +/* + * ERR_CRC_MATCH_VC11 (RC) + * + * error matching frame start with frame end for virtual channel 11 + */ +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC11_MASK (0x800U) +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC11_SHIFT (11U) +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC11_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC11_SHIFT) + +/* + * ERR_CRC_MATCH_VC10 (RC) + * + * error matching frame start with frame end for virtual channel 10 + */ +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC10_MASK (0x400U) +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC10_SHIFT (10U) +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC10_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC10_SHIFT) + +/* + * ERR_CRC_MATCH_VC9 (RC) + * + * error matching frame start with frame end for virtual channel 9 + */ +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC9_MASK (0x200U) +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC9_SHIFT (9U) +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC9_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC9_SHIFT) + +/* + * ERR_CRC_MATCH_VC8 (RC) + * + * error matching frame start with frame end for virtual channel 8 + */ +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC8_MASK (0x100U) +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC8_SHIFT (8U) +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC8_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC8_SHIFT) + +/* + * ERR_CRC_MATCH_VC7 (RC) + * + * error matching frame start with frame end for virtual channel 7 + */ +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC7_MASK (0x80U) +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC7_SHIFT (7U) +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC7_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC7_SHIFT) + +/* + * ERR_CRC_MATCH_VC6 (RC) + * + * error matching frame start with frame end for virtual channel 6 + */ +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC6_MASK (0x40U) +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC6_SHIFT (6U) +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC6_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC6_SHIFT) + +/* + * ERR_CRC_MATCH_VC5 (RC) + * + * error matching frame start with frame end for virtual channel 5 + */ +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC5_MASK (0x20U) +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC5_SHIFT (5U) +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC5_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC5_SHIFT) + +/* + * ERR_CRC_MATCH_VC4 (RC) + * + * error matching frame start with frame end for virtual channel 4 + */ +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC4_MASK (0x10U) +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC4_SHIFT (4U) +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC4_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC4_SHIFT) + +/* + * ERR_CRC_MATCH_VC3 (RC) + * + * error matching frame start with frame end for virtual channel 3 + */ +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC3_MASK (0x8U) +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC3_SHIFT (3U) +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC3_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC3_SHIFT) + +/* + * ERR_CRC_MATCH_VC2 (RC) + * + * error matching frame start with frame end for virtual channel 2 + */ +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC2_MASK (0x4U) +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC2_SHIFT (2U) +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC2_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC2_SHIFT) + +/* + * ERR_CRC_MATCH_VC1 (RC) + * + * error matching frame start with frame end for virtual channel 1 + */ +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC1_MASK (0x2U) +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC1_SHIFT (1U) +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC1_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC1_SHIFT) + +/* + * ERR_CRC_MATCH_VC0 (RC) + * + * error matching frame start with frame end for virtual channel 0 + */ +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC0_MASK (0x1U) +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC0_SHIFT (0U) +#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC0_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC0_SHIFT) + +/* Bitfield definition for register: INT_MSK_PLD_CRC_FRAME_FATAL */ +/* + * MSK_ERR_CRC_MATCH_VC15 (RW) + * + * error matching frame start with frame end for virtual channel 15 + */ +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC15_MASK (0x8000U) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC15_SHIFT (15U) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC15_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC15_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC15_MASK) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC15_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC15_SHIFT) + +/* + * MSK_ERR_CRC_MATCH_VC14 (RW) + * + * error matching frame start with frame end for virtual channel 14 + */ +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC14_MASK (0x4000U) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC14_SHIFT (14U) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC14_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC14_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC14_MASK) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC14_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC14_SHIFT) + +/* + * MSK_ERR_CRC_MATCH_VC13 (RW) + * + * error matching frame start with frame end for virtual channel 13 + */ +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC13_MASK (0x2000U) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC13_SHIFT (13U) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC13_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC13_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC13_MASK) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC13_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC13_SHIFT) + +/* + * MSK_ERR_CRC_MATCH_VC12 (RW) + * + * error matching frame start with frame end for virtual channel 12 + */ +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC12_MASK (0x1000U) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC12_SHIFT (12U) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC12_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC12_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC12_MASK) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC12_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC12_SHIFT) + +/* + * MSK_ERR_CRC_MATCH_VC11 (RW) + * + * error matching frame start with frame end for virtual channel 11 + */ +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC11_MASK (0x800U) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC11_SHIFT (11U) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC11_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC11_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC11_MASK) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC11_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC11_SHIFT) + +/* + * MSK_ERR_CRC_MATCH_VC10 (RW) + * + * error matching frame start with frame end for virtual channel 10 + */ +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC10_MASK (0x400U) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC10_SHIFT (10U) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC10_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC10_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC10_MASK) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC10_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC10_SHIFT) + +/* + * MSK_ERR_CRC_MATCH_VC9 (RW) + * + * error matching frame start with frame end for virtual channel 9 + */ +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC9_MASK (0x200U) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC9_SHIFT (9U) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC9_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC9_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC9_MASK) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC9_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC9_SHIFT) + +/* + * MSK_ERR_CRC_MATCH_VC8 (RW) + * + * error matching frame start with frame end for virtual channel 8 + */ +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC8_MASK (0x100U) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC8_SHIFT (8U) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC8_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC8_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC8_MASK) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC8_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC8_SHIFT) + +/* + * MSK_ERR_CRC_MATCH_VC7 (RW) + * + * error matching frame start with frame end for virtual channel 7 + */ +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC7_MASK (0x80U) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC7_SHIFT (7U) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC7_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC7_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC7_MASK) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC7_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC7_SHIFT) + +/* + * MSK_ERR_CRC_MATCH_VC6 (RW) + * + * error matching frame start with frame end for virtual channel 6 + */ +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC6_MASK (0x40U) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC6_SHIFT (6U) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC6_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC6_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC6_MASK) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC6_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC6_SHIFT) + +/* + * MSK_ERR_CRC_MATCH_VC5 (RW) + * + * error matching frame start with frame end for virtual channel 5 + */ +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC5_MASK (0x20U) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC5_SHIFT (5U) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC5_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC5_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC5_MASK) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC5_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC5_SHIFT) + +/* + * MSK_ERR_CRC_MATCH_VC4 (RW) + * + * error matching frame start with frame end for virtual channel 4 + */ +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC4_MASK (0x10U) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC4_SHIFT (4U) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC4_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC4_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC4_MASK) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC4_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC4_SHIFT) + +/* + * MSK_ERR_CRC_MATCH_VC3 (RW) + * + * error matching frame start with frame end for virtual channel 3 + */ +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC3_MASK (0x8U) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC3_SHIFT (3U) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC3_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC3_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC3_MASK) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC3_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC3_SHIFT) + +/* + * MSK_ERR_CRC_MATCH_VC2 (RW) + * + * error matching frame start with frame end for virtual channel 2 + */ +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC2_MASK (0x4U) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC2_SHIFT (2U) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC2_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC2_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC2_MASK) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC2_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC2_SHIFT) + +/* + * MSK_ERR_CRC_MATCH_VC1 (RW) + * + * error matching frame start with frame end for virtual channel 1 + */ +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC1_MASK (0x2U) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC1_SHIFT (1U) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC1_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC1_MASK) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC1_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC1_SHIFT) + +/* + * MSK_ERR_CRC_MATCH_VC0 (RW) + * + * error matching frame start with frame end for virtual channel 0 + */ +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC0_MASK (0x1U) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC0_SHIFT (0U) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC0_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC0_MASK) +#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC0_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC0_SHIFT) + +/* Bitfield definition for register: INT_FORCE_PLD_CRC_FRAME_FATAL */ +/* + * FORCE_ERR_CRC_MATCH_VC15 (RW) + * + * error matching frame start with frame end for virtual channel 15 + */ +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC15_MASK (0x8000U) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC15_SHIFT (15U) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC15_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC15_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC15_MASK) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC15_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC15_SHIFT) + +/* + * FORCE_ERR_CRC_MATCH_VC14 (RW) + * + * error matching frame start with frame end for virtual channel 14 + */ +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC14_MASK (0x4000U) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC14_SHIFT (14U) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC14_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC14_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC14_MASK) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC14_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC14_SHIFT) + +/* + * FORCE_ERR_CRC_MATCH_VC13 (RW) + * + * error matching frame start with frame end for virtual channel 13 + */ +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC13_MASK (0x2000U) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC13_SHIFT (13U) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC13_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC13_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC13_MASK) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC13_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC13_SHIFT) + +/* + * FORCE_ERR_CRC_MATCH_VC12 (RW) + * + * error matching frame start with frame end for virtual channel 12 + */ +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC12_MASK (0x1000U) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC12_SHIFT (12U) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC12_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC12_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC12_MASK) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC12_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC12_SHIFT) + +/* + * FORCE_ERR_CRC_MATCH_VC11 (RW) + * + * error matching frame start with frame end for virtual channel 11 + */ +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC11_MASK (0x800U) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC11_SHIFT (11U) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC11_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC11_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC11_MASK) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC11_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC11_SHIFT) + +/* + * FORCE_ERR_CRC_MATCH_VC10 (RW) + * + * error matching frame start with frame end for virtual channel 10 + */ +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC10_MASK (0x400U) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC10_SHIFT (10U) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC10_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC10_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC10_MASK) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC10_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC10_SHIFT) + +/* + * FORCE_ERR_CRC_MATCH_VC9 (RW) + * + * error matching frame start with frame end for virtual channel 9 + */ +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC9_MASK (0x200U) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC9_SHIFT (9U) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC9_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC9_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC9_MASK) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC9_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC9_SHIFT) + +/* + * FORCE_ERR_CRC_MATCH_VC8 (RW) + * + * error matching frame start with frame end for virtual channel 8 + */ +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC8_MASK (0x100U) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC8_SHIFT (8U) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC8_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC8_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC8_MASK) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC8_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC8_SHIFT) + +/* + * FORCE_ERR_CRC_MATCH_VC7 (RW) + * + * error matching frame start with frame end for virtual channel 7 + */ +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC7_MASK (0x80U) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC7_SHIFT (7U) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC7_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC7_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC7_MASK) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC7_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC7_SHIFT) + +/* + * FORCE_ERR_CRC_MATCH_VC6 (RW) + * + * error matching frame start with frame end for virtual channel 6 + */ +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC6_MASK (0x40U) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC6_SHIFT (6U) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC6_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC6_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC6_MASK) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC6_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC6_SHIFT) + +/* + * FORCE_ERR_CRC_MATCH_VC5 (RW) + * + * error matching frame start with frame end for virtual channel 5 + */ +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC5_MASK (0x20U) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC5_SHIFT (5U) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC5_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC5_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC5_MASK) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC5_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC5_SHIFT) + +/* + * FORCE_ERR_CRC_MATCH_VC4 (RW) + * + * error matching frame start with frame end for virtual channel 4 + */ +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC4_MASK (0x10U) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC4_SHIFT (4U) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC4_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC4_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC4_MASK) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC4_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC4_SHIFT) + +/* + * FORCE_ERR_CRC_MATCH_VC3 (RW) + * + * error matching frame start with frame end for virtual channel 3 + */ +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC3_MASK (0x8U) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC3_SHIFT (3U) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC3_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC3_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC3_MASK) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC3_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC3_SHIFT) + +/* + * FORCE_ERR_CRC_MATCH_VC2 (RW) + * + * error matching frame start with frame end for virtual channel 2 + */ +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC2_MASK (0x4U) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC2_SHIFT (2U) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC2_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC2_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC2_MASK) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC2_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC2_SHIFT) + +/* + * FORCE_ERR_CRC_MATCH_VC1 (RW) + * + * error matching frame start with frame end for virtual channel 1 + */ +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC1_MASK (0x2U) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC1_SHIFT (1U) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC1_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC1_MASK) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC1_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC1_SHIFT) + +/* + * FORCE_ERR_CRC_MATCH_VC0 (RW) + * + * error matching frame start with frame end for virtual channel 0 + */ +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC0_MASK (0x1U) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC0_SHIFT (0U) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC0_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC0_MASK) +#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC0_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC0_SHIFT) + + + + +#endif /* HPM_MIPI_CSI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mipi_dsi_phy_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mipi_dsi_phy_regs.h new file mode 100644 index 00000000000..4b37ad046b2 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mipi_dsi_phy_regs.h @@ -0,0 +1,993 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_MIPI_DSI_PHY_H +#define HPM_MIPI_DSI_PHY_H + +typedef struct { + __RW uint32_t CLANE_PARA0; /* 0x0: timer counter about clock lane parameter */ + __RW uint32_t CLANE_PARA1; /* 0x4: timer counter about clock lane parameter */ + __RW uint32_t CLANE_PARA2; /* 0x8: timer counter about clock lane parameter */ + __RW uint32_t CLANE_PARA3; /* 0xC: timer counter about clock lane parameter */ + __RW uint32_t DLANE0_PARA0; /* 0x10: timer counter about datalane0 parameter */ + __RW uint32_t DLANE0_PARA1; /* 0x14: timer counter about datalane0 parameter */ + __RW uint32_t DLANE0_PARA2; /* 0x18: timer counter about datalane0 parameter */ + __RW uint32_t DLANE0_PARA3; /* 0x1C: timer counter about datalane0 parameter */ + __RW uint32_t DLANE0_PARA4; /* 0x20: timer counter about datalane0 parameter */ + __RW uint32_t DLANE1_PARA0; /* 0x24: timer counter about datalane1 parameter */ + __RW uint32_t DLANE1_PARA1; /* 0x28: timer counter about datalane1 parameter */ + __RW uint32_t DLANE1_PARA2; /* 0x2C: timer counter about datalane1 parameter */ + __RW uint32_t DLANE1_PARA3; /* 0x30: timer counter about datalane1 parameter */ + __RW uint32_t DLANE2_PARA0; /* 0x34: timer counter about datalane2 parameter */ + __RW uint32_t DLANE2_PARA1; /* 0x38: timer counter about datalane2 parameter */ + __RW uint32_t DLANE2_PARA2; /* 0x3C: timer counter about datalane2 parameter */ + __RW uint32_t DLANE2_PARA3; /* 0x40: timer counter about datalane2 parameter */ + __RW uint32_t DLANE3_PARA0; /* 0x44: timer counter about datalane3 parameter */ + __RW uint32_t DLANE3_PARA1; /* 0x48: timer counter about datalane3 parameter */ + __RW uint32_t DLANE3_PARA2; /* 0x4C: timer counter about datalane3 parameter */ + __RW uint32_t DLANE3_PARA3; /* 0x50: timer counter about datalane3 parameter */ + __RW uint32_t COMMON_PARA0; /* 0x54: timing parameter for all lanes */ + __RW uint32_t CTRL_PARA0; /* 0x58: dphy control parameter */ + __RW uint32_t PLL_CTRL_PARA0; /* 0x5C: dphy pll control parameter */ + __R uint8_t RESERVED0[4]; /* 0x60 - 0x63: Reserved */ + __RW uint32_t RCAL_CTRL; /* 0x64: dphy calibration control parameter */ + __RW uint32_t TRIM_PARA; /* 0x68: dphy trimming parameter */ + __RW uint32_t TEST_PARA0; /* 0x6C: dphy test control parameter */ + __RW uint32_t TEST_PARA1; /* 0x70: dphy bist test control parameter */ + __RW uint32_t MISC_PARA; /* 0x74: dphy control parameter */ + __RW uint32_t CLANE_PARA4; /* 0x78: dphy clock lane control parameter */ + __RW uint32_t INTERFACE_PARA; /* 0x7C: dphy clock lane control parameter */ + __RW uint32_t PCS_RESERVED_PIN_PARA; /* 0x80: reserved the pins for pcs */ + __R uint8_t RESERVED1[8]; /* 0x84 - 0x8B: Reserved */ + __RW uint32_t CLANE_DATA_PARA; /* 0x8C: parallel data about clock lane parameter */ + __RW uint32_t PMA_LANE_SEL_PARA; /* 0x90: pma about clock lane select parameter */ +} MIPI_DSI_PHY_Type; + + +/* Bitfield definition for register: CLANE_PARA0 */ +/* + * T_RST2ENLPTX_C (RW) + * + * the soft reset of clk_cfg domain + */ +#define MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_MASK (0xFFFFU) +#define MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_SHIFT (0U) +#define MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_MASK) +#define MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_SHIFT) + +/* Bitfield definition for register: CLANE_PARA1 */ +/* + * T_INITTIME_C (RW) + * + * the number of byteclk cycles that clklane drive LP-11 during initialization period + */ +#define MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_MASK (0xFFFFFFFFUL) +#define MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_SHIFT (0U) +#define MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_MASK) +#define MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_SHIFT) + +/* Bitfield definition for register: CLANE_PARA2 */ +/* + * T_CLKPREPARE_C (RW) + * + * the number of byteclk cycles that clock lane clkp/n lines are at the hs prepare state lp-00 during a hs clock transmission + */ +#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_MASK (0xFF0000UL) +#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_SHIFT (16U) +#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_MASK) +#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_SHIFT) + +/* + * T_CLKZERO_C (RW) + * + * the number of byteclk cycles that clock lane clkp/n lines are at the hs-zero state hs-0 during a hs clock transmission + */ +#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_MASK (0xFF00U) +#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_SHIFT (8U) +#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_MASK) +#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_SHIFT) + +/* + * T_CLKPRE_C (RW) + * + * the number of byteclk cycles that hs clock shall be driven prior to data lane beginning the transition from lp to hs mode + */ +#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_MASK (0xFFU) +#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_SHIFT (0U) +#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_MASK) +#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_SHIFT) + +/* Bitfield definition for register: CLANE_PARA3 */ +/* + * T_CLKPOST_C (RW) + * + * the number of byteclk cycles that the clock lane should keep sending the hs-clock after the last associated data lane has transitioned to LP mode. + */ +#define MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_MASK (0xFF0000UL) +#define MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_SHIFT (16U) +#define MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_MASK) +#define MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_SHIFT) + +/* + * T_CLKTRIAL_C (RW) + * + * the number of byteclk cycles that the clock lane clkp/n lines are at state hs-tail sate hs-0 during a hs clock transmission + */ +#define MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_MASK (0xFF00U) +#define MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_SHIFT (8U) +#define MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_MASK) +#define MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_SHIFT) + +/* + * T_HSEXIT_C (RW) + * + * the number of byteclk cycles that the clock lane clkp/n lines are at hs-exit state after a hs clock transmission + */ +#define MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_MASK (0xFFU) +#define MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_SHIFT (0U) +#define MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_MASK) +#define MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_SHIFT) + +/* Bitfield definition for register: DLANE0_PARA0 */ +/* + * T_RST2ENLPTX_D0 (RW) + * + * the number of byteclk cycles that datalane0 wait to enable lptx_en after reset release + */ +#define MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_MASK (0xFFFFU) +#define MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_SHIFT (0U) +#define MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_MASK) +#define MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_SHIFT) + +/* Bitfield definition for register: DLANE0_PARA1 */ +/* + * T_INITTIME_D0 (RW) + * + * the number of byteclk cycles that datalane0 drive lp-11 during initiaalization period + */ +#define MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_MASK (0xFFFFFFFFUL) +#define MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_SHIFT (0U) +#define MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_MASK) +#define MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_SHIFT) + +/* Bitfield definition for register: DLANE0_PARA2 */ +/* + * T_HSPREPARE_D0 (RW) + * + * the number of byteclk cycles that the datalane0 stay at hs prepare state lp-00 during a hs transmission + */ +#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_MASK (0xFF000000UL) +#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_SHIFT (24U) +#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_MASK) +#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_SHIFT) + +/* + * T_HSZERO_D0 (RW) + * + * the number of byteclk cycles that the datalane0 stay at hs-zero sate during a hs transmission + */ +#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_MASK (0xFF0000UL) +#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_SHIFT (16U) +#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_MASK) +#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_SHIFT) + +/* + * T_HSTRAIL_D0 (RW) + * + * the number of byteclk cycles that the datalane0 stay at hs-trail state during a hs clock trasmission + */ +#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_MASK (0xFF00U) +#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_SHIFT (8U) +#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_MASK) +#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_SHIFT) + +/* + * T_HSEXIT_D0 (RW) + * + * the number of byteclk cycles that the datalane0 stay at state hs-exit sate after a hs clock trasmission + */ +#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_MASK (0xFFU) +#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_SHIFT (0U) +#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_MASK) +#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_SHIFT) + +/* Bitfield definition for register: DLANE0_PARA3 */ +/* + * T_WAKEUP_D0 (RW) + * + * the number of byteclk cycles from exiting ultra low power sate to enabling the low-power driver + */ +#define MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_MASK (0xFFFFFFFFUL) +#define MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_SHIFT (0U) +#define MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_MASK) +#define MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_SHIFT) + +/* Bitfield definition for register: DLANE0_PARA4 */ +/* + * T_TAGO_D0 (RW) + * + * the number of byteclk cycles that the tx drives the bridge state during a turnaroud procedure + */ +#define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_MASK (0xFF0000UL) +#define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_SHIFT (16U) +#define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_MASK) +#define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_SHIFT) + +/* + * T_TASURE_D0 (RW) + * + * the number of byteclk cycles that the rx waits after a bridge state has been detected during a turnaround procedure + */ +#define MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_MASK (0xFF00U) +#define MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_SHIFT (8U) +#define MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_MASK) +#define MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_SHIFT) + +/* + * T_TAGET_D0 (RW) + * + * the number of byteclk cycles that the new transmitter drivers the bridge state after accepting control during bta + */ +#define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_MASK (0xFFU) +#define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_SHIFT (0U) +#define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_MASK) +#define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_SHIFT) + +/* Bitfield definition for register: DLANE1_PARA0 */ +/* + * T_RST2ENLPTX_D1 (RW) + * + * the number of byteclk cycles that datalane1 wait to enable lptx_en after reset release + */ +#define MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_MASK (0xFFFFU) +#define MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_SHIFT (0U) +#define MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_MASK) +#define MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_SHIFT) + +/* Bitfield definition for register: DLANE1_PARA1 */ +/* + * T_INITTIME_D1 (RW) + * + * the number of byteclk cycles that datalane1 drive lp-11 during initiaalization period + */ +#define MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_MASK (0xFFFFFFFFUL) +#define MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_SHIFT (0U) +#define MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_MASK) +#define MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_SHIFT) + +/* Bitfield definition for register: DLANE1_PARA2 */ +/* + * T_HSPREPARE_D1 (RW) + * + * the number of byteclk cycles that the datalane1 stay at hs prepare state lp-00 during a hs transmission + */ +#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_MASK (0xFF000000UL) +#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_SHIFT (24U) +#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_MASK) +#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_SHIFT) + +/* + * T_HSZERO_D1 (RW) + * + * the number of byteclk cycles that the datalane1 stay at hs-zero sate during a hs transmission + */ +#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_MASK (0xFF0000UL) +#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_SHIFT (16U) +#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_MASK) +#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_SHIFT) + +/* + * T_HSTRAIL_D1 (RW) + * + * the number of byteclk cycles that the datalane1 stay at hs-trail state during a hs clock trasmission + */ +#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_MASK (0xFF00U) +#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_SHIFT (8U) +#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_MASK) +#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_SHIFT) + +/* + * T_HSEXIT_D1 (RW) + * + * the number of byteclk cycles that the datalane1 stay at state hs-exit sate after a hs clock trasmission + */ +#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_MASK (0xFFU) +#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_SHIFT (0U) +#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_MASK) +#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_SHIFT) + +/* Bitfield definition for register: DLANE1_PARA3 */ +/* + * T_WAKEUP_D1 (RW) + * + * the number of byteclk cycles from exiting ultra low power sate to enabling the low-power driver + */ +#define MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_MASK (0xFFFFFFFFUL) +#define MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_SHIFT (0U) +#define MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_MASK) +#define MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_SHIFT) + +/* Bitfield definition for register: DLANE2_PARA0 */ +/* + * T_RST2ENLPTX_D2 (RW) + * + * the number of byteclk cycles that datalane2 wait to enable lptx_en after reset release + */ +#define MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_MASK (0xFFFFU) +#define MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_SHIFT (0U) +#define MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_MASK) +#define MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_SHIFT) + +/* Bitfield definition for register: DLANE2_PARA1 */ +/* + * T_INITTIME_D2 (RW) + * + * the number of byteclk cycles that datalane2 drive lp-11 during initiaalization period + */ +#define MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_MASK (0xFFFFFFFFUL) +#define MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_SHIFT (0U) +#define MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_MASK) +#define MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_SHIFT) + +/* Bitfield definition for register: DLANE2_PARA2 */ +/* + * T_HSPREPARE_D2 (RW) + * + * the number of byteclk cycles that the datalane2 stay at hs prepare state lp-00 during a hs transmission + */ +#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_MASK (0xFF000000UL) +#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_SHIFT (24U) +#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_MASK) +#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_SHIFT) + +/* + * T_HSZERO_D2 (RW) + * + * the number of byteclk cycles that the datalane2 stay at hs-zero sate during a hs transmission + */ +#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_MASK (0xFF0000UL) +#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_SHIFT (16U) +#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_MASK) +#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_SHIFT) + +/* + * T_HSTRAIL_D2 (RW) + * + * the number of byteclk cycles that the datalane2 stay at hs-trail state during a hs clock trasmission + */ +#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_MASK (0xFF00U) +#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_SHIFT (8U) +#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_MASK) +#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_SHIFT) + +/* + * T_HSEXIT_D2 (RW) + * + * the number of byteclk cycles that the datalane2 stay at state hs-exit sate after a hs clock trasmission + */ +#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_MASK (0xFFU) +#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_SHIFT (0U) +#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_MASK) +#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_SHIFT) + +/* Bitfield definition for register: DLANE2_PARA3 */ +/* + * T_WAKEUP_D2 (RW) + * + * the number of byteclk cycles from exiting ultra low power sate to enabling the low-power driver + */ +#define MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_MASK (0xFFFFFFFFUL) +#define MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_SHIFT (0U) +#define MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_MASK) +#define MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_SHIFT) + +/* Bitfield definition for register: DLANE3_PARA0 */ +/* + * T_RST2ENLPTX_D3 (RW) + * + * the number of byteclk cycles that datalane3 wait to enable lptx_en after reset release + */ +#define MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_MASK (0xFFFFU) +#define MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_SHIFT (0U) +#define MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_MASK) +#define MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_SHIFT) + +/* Bitfield definition for register: DLANE3_PARA1 */ +/* + * T_INITTIME_D3 (RW) + * + * the number of byteclk cycles that datalane3 drive lp-11 during initiaalization period + */ +#define MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_MASK (0xFFFFFFFFUL) +#define MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_SHIFT (0U) +#define MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_MASK) +#define MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_SHIFT) + +/* Bitfield definition for register: DLANE3_PARA2 */ +/* + * T_HSPREPARE_D3 (RW) + * + * the number of byteclk cycles that the datalane3 stay at hs prepare state lp-00 during a hs transmission + */ +#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_MASK (0xFF000000UL) +#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_SHIFT (24U) +#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_MASK) +#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_SHIFT) + +/* + * T_HSZERO_D3 (RW) + * + * the number of byteclk cycles that the datalane3 stay at hs-zero sate during a hs transmission + */ +#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_MASK (0xFF0000UL) +#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_SHIFT (16U) +#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_MASK) +#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_SHIFT) + +/* + * T_HSTRAIL_D3 (RW) + * + * the number of byteclk cycles that the datalane3 stay at hs-trail state during a hs clock trasmission + */ +#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_MASK (0xFF00U) +#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_SHIFT (8U) +#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_MASK) +#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_SHIFT) + +/* + * T_HSEXIT_D3 (RW) + * + * the number of byteclk cycles that the datalane3 stay at state hs-exit sate after a hs clock trasmission + */ +#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_MASK (0xFFU) +#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_SHIFT (0U) +#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_MASK) +#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_SHIFT) + +/* Bitfield definition for register: DLANE3_PARA3 */ +/* + * T_WAKEUP_D3 (RW) + * + * the number of byteclk cycles from exiting ultra low power sate to enabling the low-power driver + */ +#define MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_MASK (0xFFFFFFFFUL) +#define MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_SHIFT (0U) +#define MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_MASK) +#define MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_SHIFT) + +/* Bitfield definition for register: COMMON_PARA0 */ +/* + * T_LPX (RW) + * + * the number of byteclk cycles of transmitted length of any low-power state period + */ +#define MIPI_DSI_PHY_COMMON_PARA0_T_LPX_MASK (0xFFU) +#define MIPI_DSI_PHY_COMMON_PARA0_T_LPX_SHIFT (0U) +#define MIPI_DSI_PHY_COMMON_PARA0_T_LPX_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_COMMON_PARA0_T_LPX_SHIFT) & MIPI_DSI_PHY_COMMON_PARA0_T_LPX_MASK) +#define MIPI_DSI_PHY_COMMON_PARA0_T_LPX_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_COMMON_PARA0_T_LPX_MASK) >> MIPI_DSI_PHY_COMMON_PARA0_T_LPX_SHIFT) + +/* Bitfield definition for register: CTRL_PARA0 */ +/* + * VBG_RDY (RO) + * + * the indicator signal of reference generator is ready + */ +#define MIPI_DSI_PHY_CTRL_PARA0_VBG_RDY_MASK (0x80U) +#define MIPI_DSI_PHY_CTRL_PARA0_VBG_RDY_SHIFT (7U) +#define MIPI_DSI_PHY_CTRL_PARA0_VBG_RDY_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_VBG_RDY_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_VBG_RDY_SHIFT) + +/* + * EN_ULPRX_D0 (RW) + * + * ulp-rx enable for lane0 + */ +#define MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_MASK (0x40U) +#define MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_SHIFT (6U) +#define MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_MASK) +#define MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_SHIFT) + +/* + * EN_LPRX_D0 (RW) + * + * lp-rx enable for lane0 + */ +#define MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_MASK (0x20U) +#define MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_SHIFT (5U) +#define MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_MASK) +#define MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_SHIFT) + +/* + * EN_LPCD_D0 (RW) + * + * lp-cd enable for lane0 + */ +#define MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_MASK (0x10U) +#define MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_SHIFT (4U) +#define MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_MASK) +#define MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_SHIFT) + +/* + * PWON_SEL (RW) + * + * select the cource of PMA power on control signals + */ +#define MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_MASK (0x8U) +#define MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_SHIFT (3U) +#define MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_MASK) +#define MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_SHIFT) + +/* + * PWON_PLL (RW) + * + * power on pll high active + */ +#define MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_MASK (0x4U) +#define MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_SHIFT (2U) +#define MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_MASK) +#define MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_SHIFT) + +/* + * PWON_DSI (RW) + * + * power on all dsi lane + */ +#define MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_MASK (0x2U) +#define MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_SHIFT (1U) +#define MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_MASK) +#define MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_SHIFT) + +/* + * SU_IDDQ_EN (RW) + * + * power down all modules inside su includes ivref, r-calibration and pll, high effective + */ +#define MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_MASK (0x1U) +#define MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_SHIFT (0U) +#define MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_MASK) +#define MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_SHIFT) + +/* Bitfield definition for register: PLL_CTRL_PARA0 */ +/* + * PLL_LOCK (RO) + * + * pll lock indication + */ +#define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_LOCK_MASK (0x8000000UL) +#define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_LOCK_SHIFT (27U) +#define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_LOCK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_LOCK_MASK) >> MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_LOCK_SHIFT) + +/* + * RATE (RW) + * + * data reate control signal + */ +#define MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_MASK (0x7000000UL) +#define MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_SHIFT (24U) +#define MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_SHIFT) & MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_MASK) +#define MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_MASK) >> MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_SHIFT) + +/* + * REFCLK_DIV (RW) + * + * input refrence clock divider ratio control + */ +#define MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_MASK (0xF80000UL) +#define MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_SHIFT (19U) +#define MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_SHIFT) & MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_MASK) +#define MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_MASK) >> MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_SHIFT) + +/* + * PLL_DIV (RW) + * + * pll loop divider ratio control + */ +#define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_MASK (0x7FFF0UL) +#define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_SHIFT (4U) +#define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_SHIFT) & MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_MASK) +#define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_MASK) >> MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_SHIFT) + +/* + * DSI_PIXELCLK_DIV (RW) + * + * pixell clock divided from pll output + */ +#define MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_MASK (0xFU) +#define MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_SHIFT (0U) +#define MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_SHIFT) & MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_MASK) +#define MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_MASK) >> MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_SHIFT) + +/* Bitfield definition for register: RCAL_CTRL */ +/* + * RCAL_EN (RW) + * + * enable hs-tx output impedance trimming + */ +#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_MASK (0x2000U) +#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_SHIFT (13U) +#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_SHIFT) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_MASK) +#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_MASK) >> MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_SHIFT) + +/* + * RCAL_TRIM (RW) + * + * default value of hs-tx output resistance configure + */ +#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_MASK (0x1E00U) +#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_SHIFT (9U) +#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_SHIFT) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_MASK) +#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_MASK) >> MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_SHIFT) + +/* + * RCAL_CTRL (RW) + * + * resistor calibration control, reserved for test + */ +#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_MASK (0x1FEU) +#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_SHIFT (1U) +#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_SHIFT) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_MASK) +#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_MASK) >> MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_SHIFT) + +/* + * RCAL_DONE (RO) + * + * hs-tx output impedance trimming done indicator signal + */ +#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_DONE_MASK (0x1U) +#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_DONE_SHIFT (0U) +#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_DONE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_DONE_MASK) >> MIPI_DSI_PHY_RCAL_CTRL_RCAL_DONE_SHIFT) + +/* Bitfield definition for register: TRIM_PARA */ +/* + * HSTX_AMP_TRIM (RW) + * + * hs-tx output vod trimming for lane-0~4 + */ +#define MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_MASK (0x3800U) +#define MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_SHIFT (11U) +#define MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_SHIFT) & MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_MASK) +#define MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_MASK) >> MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_SHIFT) + +/* + * LPTX_SR_TRIM (RW) + * + * lp-tx output slew-rate trimming for lane0~4 + */ +#define MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_MASK (0x700U) +#define MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_SHIFT (8U) +#define MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_SHIFT) & MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_MASK) +#define MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_MASK) >> MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_SHIFT) + +/* + * LPRX_VREF_TRIM (RW) + * + * lp-rx input threshold voltage trimming for lane0 + */ +#define MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_MASK (0xF0U) +#define MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_SHIFT (4U) +#define MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_SHIFT) & MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_MASK) +#define MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_MASK) >> MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_SHIFT) + +/* + * LPCD_VREF_TRIM (RW) + * + * lp-cd input threshold voltage trimming for lane0 + */ +#define MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_MASK (0xFU) +#define MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_SHIFT (0U) +#define MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_SHIFT) & MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_MASK) +#define MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_MASK) >> MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_SHIFT) + +/* Bitfield definition for register: TEST_PARA0 */ +/* + * ERROR_NUM (RO) + * + * the byte num of mismatch data of lane in bist mode + */ +#define MIPI_DSI_PHY_TEST_PARA0_ERROR_NUM_MASK (0x7E0000UL) +#define MIPI_DSI_PHY_TEST_PARA0_ERROR_NUM_SHIFT (17U) +#define MIPI_DSI_PHY_TEST_PARA0_ERROR_NUM_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_ERROR_NUM_MASK) >> MIPI_DSI_PHY_TEST_PARA0_ERROR_NUM_SHIFT) + +/* + * BIST_N_DONE (RO) + * + * indicate prbs7 bist test is done + */ +#define MIPI_DSI_PHY_TEST_PARA0_BIST_N_DONE_MASK (0x1F000UL) +#define MIPI_DSI_PHY_TEST_PARA0_BIST_N_DONE_SHIFT (12U) +#define MIPI_DSI_PHY_TEST_PARA0_BIST_N_DONE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_BIST_N_DONE_MASK) >> MIPI_DSI_PHY_TEST_PARA0_BIST_N_DONE_SHIFT) + +/* + * BIST_N_OK (RO) + * + * indicate prbs7 bist test is ok + */ +#define MIPI_DSI_PHY_TEST_PARA0_BIST_N_OK_MASK (0xF80U) +#define MIPI_DSI_PHY_TEST_PARA0_BIST_N_OK_SHIFT (7U) +#define MIPI_DSI_PHY_TEST_PARA0_BIST_N_OK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_BIST_N_OK_MASK) >> MIPI_DSI_PHY_TEST_PARA0_BIST_N_OK_SHIFT) + +/* + * ATEST_EN (RW) + * + * analog test signal enable + */ +#define MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_MASK (0x40U) +#define MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_SHIFT (6U) +#define MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_SHIFT) & MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_MASK) +#define MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_MASK) >> MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_SHIFT) + +/* + * ATEST_SEL (RW) + * + * analog test signal select + */ +#define MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_MASK (0x30U) +#define MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_SHIFT (4U) +#define MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_SHIFT) & MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_MASK) +#define MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_MASK) >> MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_SHIFT) + +/* + * FSET_EN (RW) + * + * enable fast transmission between lp-tx and hs-tx + */ +#define MIPI_DSI_PHY_TEST_PARA0_FSET_EN_MASK (0x8U) +#define MIPI_DSI_PHY_TEST_PARA0_FSET_EN_SHIFT (3U) +#define MIPI_DSI_PHY_TEST_PARA0_FSET_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA0_FSET_EN_SHIFT) & MIPI_DSI_PHY_TEST_PARA0_FSET_EN_MASK) +#define MIPI_DSI_PHY_TEST_PARA0_FSET_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_FSET_EN_MASK) >> MIPI_DSI_PHY_TEST_PARA0_FSET_EN_SHIFT) + +/* + * FT_SEL (RW) + * + * pt/ft test mode select + */ +#define MIPI_DSI_PHY_TEST_PARA0_FT_SEL_MASK (0x7U) +#define MIPI_DSI_PHY_TEST_PARA0_FT_SEL_SHIFT (0U) +#define MIPI_DSI_PHY_TEST_PARA0_FT_SEL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA0_FT_SEL_SHIFT) & MIPI_DSI_PHY_TEST_PARA0_FT_SEL_MASK) +#define MIPI_DSI_PHY_TEST_PARA0_FT_SEL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_FT_SEL_MASK) >> MIPI_DSI_PHY_TEST_PARA0_FT_SEL_SHIFT) + +/* Bitfield definition for register: TEST_PARA1 */ +/* + * CHECK_NUM (RW) + * + * the byte num of prbs bist check num + */ +#define MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_MASK (0xFFFFFC00UL) +#define MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_SHIFT (10U) +#define MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_SHIFT) & MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_MASK) +#define MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_MASK) >> MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_SHIFT) + +/* + * ERR_THRESHOLD (RW) + * + * the threshold of prbs bit error + */ +#define MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_MASK (0x3C0U) +#define MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_SHIFT (6U) +#define MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_SHIFT) & MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_MASK) +#define MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_MASK) >> MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_SHIFT) + +/* + * BIST_BIT_ERROR (RW) + * + * enable insert error in bist test pattern + */ +#define MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_MASK (0x20U) +#define MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_SHIFT (5U) +#define MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_SHIFT) & MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_MASK) +#define MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_MASK) >> MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_SHIFT) + +/* + * BIST_EN (RW) + * + * bist enable + */ +#define MIPI_DSI_PHY_TEST_PARA1_BIST_EN_MASK (0x18U) +#define MIPI_DSI_PHY_TEST_PARA1_BIST_EN_SHIFT (3U) +#define MIPI_DSI_PHY_TEST_PARA1_BIST_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA1_BIST_EN_SHIFT) & MIPI_DSI_PHY_TEST_PARA1_BIST_EN_MASK) +#define MIPI_DSI_PHY_TEST_PARA1_BIST_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA1_BIST_EN_MASK) >> MIPI_DSI_PHY_TEST_PARA1_BIST_EN_SHIFT) + +/* + * BIST_SEL (RW) + * + * bist mode select + */ +#define MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_MASK (0x4U) +#define MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_SHIFT (2U) +#define MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_SHIFT) & MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_MASK) +#define MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_MASK) >> MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_SHIFT) + +/* + * PRBS_SEL (RW) + * + * prbs generator and checker pattern select signal + */ +#define MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_MASK (0x3U) +#define MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_SHIFT (0U) +#define MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_SHIFT) & MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_MASK) +#define MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_MASK) >> MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_SHIFT) + +/* Bitfield definition for register: MISC_PARA */ +/* + * DLL_SEL (RW) + * + * the phase select of clk_rxesc + */ +#define MIPI_DSI_PHY_MISC_PARA_DLL_SEL_MASK (0x780U) +#define MIPI_DSI_PHY_MISC_PARA_DLL_SEL_SHIFT (7U) +#define MIPI_DSI_PHY_MISC_PARA_DLL_SEL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_MISC_PARA_DLL_SEL_SHIFT) & MIPI_DSI_PHY_MISC_PARA_DLL_SEL_MASK) +#define MIPI_DSI_PHY_MISC_PARA_DLL_SEL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_MISC_PARA_DLL_SEL_MASK) >> MIPI_DSI_PHY_MISC_PARA_DLL_SEL_SHIFT) + +/* + * LANE_NUM (RW) + * + * the number of active data lanes + */ +#define MIPI_DSI_PHY_MISC_PARA_LANE_NUM_MASK (0x60U) +#define MIPI_DSI_PHY_MISC_PARA_LANE_NUM_SHIFT (5U) +#define MIPI_DSI_PHY_MISC_PARA_LANE_NUM_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_MISC_PARA_LANE_NUM_SHIFT) & MIPI_DSI_PHY_MISC_PARA_LANE_NUM_MASK) +#define MIPI_DSI_PHY_MISC_PARA_LANE_NUM_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_MISC_PARA_LANE_NUM_MASK) >> MIPI_DSI_PHY_MISC_PARA_LANE_NUM_SHIFT) + +/* + * PHYERR_MASK (RW) + * + * mask the phy error + */ +#define MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_MASK (0x1FU) +#define MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_SHIFT (0U) +#define MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_SHIFT) & MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_MASK) +#define MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_MASK) >> MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_SHIFT) + +/* Bitfield definition for register: CLANE_PARA4 */ +/* + * T_WAKEUP_C (RW) + * + * the number of byteclk cycles from exiting ultra low power state to enabling the low-power driver + */ +#define MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_MASK (0xFFFFFFFFUL) +#define MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_SHIFT (0U) +#define MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_MASK) +#define MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_SHIFT) + +/* Bitfield definition for register: INTERFACE_PARA */ +/* + * TXREADYESC_EXTEND_VLD (RW) + * + * the extend length of txreadyesc + */ +#define MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_MASK (0xFF00U) +#define MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_SHIFT (8U) +#define MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_SHIFT) & MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_MASK) +#define MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_MASK) >> MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_SHIFT) + +/* + * RXVALIDESC_EXTEND_VLD (RW) + * + * the extend length of rxvalidesc + */ +#define MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_MASK (0xFFU) +#define MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_SHIFT (0U) +#define MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_SHIFT) & MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_MASK) +#define MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_MASK) >> MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_SHIFT) + +/* Bitfield definition for register: PCS_RESERVED_PIN_PARA */ +/* + * CLK_TXHS_SEL_INNER (RW) + * + * select the clock source of clk_txhs in pcs + */ +#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_MASK (0x10U) +#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_SHIFT (4U) +#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_SHIFT) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_MASK) +#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_MASK) >> MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_SHIFT) + +/* + * INV_CLK_TXHS (RW) + * + * clk_txhs inverter signal + */ +#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_MASK (0x8U) +#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_SHIFT (3U) +#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_SHIFT) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_MASK) +#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_MASK) >> MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_SHIFT) + +/* + * INV_CLK_TXESC (RW) + * + * clk_txesc inverter signal + */ +#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_MASK (0x4U) +#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_SHIFT (2U) +#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_SHIFT) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_MASK) +#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_MASK) >> MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_SHIFT) + +/* + * INV_PCLK (RW) + * + * pclk inverter signal + */ +#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_MASK (0x2U) +#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_SHIFT (1U) +#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_SHIFT) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_MASK) +#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_MASK) >> MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_SHIFT) + +/* + * INV_DSI_RCLK (RW) + * + * pma clock dsi_rclk_i inverter signal + */ +#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_MASK (0x1U) +#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_SHIFT (0U) +#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_SHIFT) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_MASK) +#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_MASK) >> MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_SHIFT) + +/* Bitfield definition for register: CLANE_DATA_PARA */ +/* + * CLANE_DATA_SEL (RW) + * + * select the data about clock lane + */ +#define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_MASK (0x100U) +#define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_SHIFT (8U) +#define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_SHIFT) & MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_MASK) +#define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_MASK) >> MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_SHIFT) + +/* + * CLANE_DATA (RW) + * + * the parallel data about clock lane + */ +#define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_MASK (0xFFU) +#define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SHIFT (0U) +#define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SHIFT) & MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_MASK) +#define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_MASK) >> MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SHIFT) + +/* Bitfield definition for register: PMA_LANE_SEL_PARA */ +/* + * PMA_DLANE4_SEL (RW) + * + * select the channel 4 as the data lane + */ +#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_MASK (0x8U) +#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_SHIFT (3U) +#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_SHIFT) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_MASK) +#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_MASK) >> MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_SHIFT) + +/* + * PMA_DLANE3_SEL (RW) + * + * select the channel 3 as the data lane + */ +#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_MASK (0x4U) +#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_SHIFT (2U) +#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_SHIFT) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_MASK) +#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_MASK) >> MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_SHIFT) + +/* + * PMA_DLANE2_SEL (RW) + * + * select the channel 2 as the data lane + */ +#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_MASK (0x2U) +#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_SHIFT (1U) +#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_SHIFT) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_MASK) +#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_MASK) >> MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_SHIFT) + +/* + * PMA_DLANE1_SEL (RW) + * + * select the channel 1 as the data lane + */ +#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_MASK (0x1U) +#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_SHIFT (0U) +#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_SHIFT) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_MASK) +#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_MASK) >> MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_SHIFT) + + + + +#endif /* HPM_MIPI_DSI_PHY_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mipi_dsi_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mipi_dsi_regs.h new file mode 100644 index 00000000000..43122f9df42 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mipi_dsi_regs.h @@ -0,0 +1,2882 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_MIPI_DSI_H +#define HPM_MIPI_DSI_H + +typedef struct { + __R uint32_t VERSION; /* 0x0: version */ + __RW uint32_t PWR_UP; /* 0x4: power up */ + __RW uint32_t CLKMGR_CFG; /* 0x8: divide lanebyteclk for timeout */ + __RW uint32_t DPI_VCID; /* 0xC: virtual channel ID for DPI traffic */ + __RW uint32_t DPI_COLOR_CODING; /* 0x10: dpi color coding */ + __RW uint32_t DPI_CFG_POL; /* 0x14: the polarity of DPI signals */ + __RW uint32_t DPI_LP_CMD_TIM; /* 0x18: the timing for low-power commands sent while in video mode */ + __R uint8_t RESERVED0[16]; /* 0x1C - 0x2B: Reserved */ + __RW uint32_t PCKHDL_CFG; /* 0x2C: configures how EoTp, BTA, CRC and ECC to be used */ + __RW uint32_t GEN_VCID; /* 0x30: configures the virtual channel ID of read response to store and return to generic interface */ + __RW uint32_t MODE_CFG; /* 0x34: configures the mode of operation between video or command mode */ + __RW uint32_t VID_MODE_CFG; /* 0x38: several aspect of video mode operation */ + __RW uint32_t VID_PKT_SIZE; /* 0x3C: configures the video packet size */ + __RW uint32_t VID_NUM_CHUNKS; /* 0x40: configures the number of chunks to use */ + __RW uint32_t VID_NULL_SIZE; /* 0x44: configures the size of null packets */ + __RW uint32_t VID_HSA_TIME; /* 0x48: configures the video HAS time */ + __RW uint32_t VID_HBP_TIME; /* 0x4C: configure the video HBP time */ + __RW uint32_t VID_HLINE_TIME; /* 0x50: configures the overall time for each video line */ + __RW uint32_t VID_VSA_LINES; /* 0x54: configures the vsa period */ + __RW uint32_t VID_VBP_LINES; /* 0x58: configures the vbp period */ + __RW uint32_t VID_VFP_LINES; /* 0x5C: configures the vfp period */ + __RW uint32_t VID_VACTIVE_LINES; /* 0x60: configures the vertical resolution of video */ + __R uint8_t RESERVED1[4]; /* 0x64 - 0x67: Reserved */ + __RW uint32_t CMD_MODE_CFG; /* 0x68: This register configures several aspect of command mode operation, tearing effect, acknowledge for each packet and the speed mode to transmit each Data Type related to commands. */ + __RW uint32_t GEN_HDR; /* 0x6C: sets the header for new packets sent using the generic interface */ + __RW uint32_t GEN_PLD_DATA; /* 0x70: sets the payload for packets sent using the generic interface */ + __R uint32_t CMD_PKT_STATUS; /* 0x74: information about the status of FIFOs related to DBI and Generic interface */ + __RW uint32_t TO_CNT_CFG; /* 0x78: configures the trigger timeout errors */ + __RW uint32_t HS_RD_TO_CNT; /* 0x7C: configures the peripheral response timeout after high speed read operations */ + __RW uint32_t LP_RD_TO_CNT; /* 0x80: configures the peripheral response timeout after low-power read operation */ + __RW uint32_t HS_WR_TO_CNT; /* 0x84: configures the peripheral response timeout after high speed write operations */ + __RW uint32_t LP_WR_TO_CNT; /* 0x88: configures the peripheral response timeout after low power write operations */ + __RW uint32_t BTA_TO_CNT; /* 0x8C: configures the periphera response timeout after bus turnaround */ + __RW uint32_t SDF_3D; /* 0x90: sotres 3d control information for vss packets in video mode */ + __RW uint32_t LPCLK_CTRL; /* 0x94: configures the possibility for using non continous clock in the clock lane */ + __RW uint32_t PHY_TMR_LPCLK_CFG; /* 0x98: sets the time that dsi host assumes in calculations for the clock lane to switch between high-speed and low-power */ + __RW uint32_t PHY_TMR_CFG; /* 0x9C: sets the time that dsi host assumes in calculations for data lanes to switch between hs to lp */ + __RW uint32_t PHY_RSTZ; /* 0xA0: controls resets and the pll of d-phy */ + __RW uint32_t PHY_IF_CFG; /* 0xA4: configures the number of active lanes */ + __RW uint32_t PHY_ULPS_CTRL; /* 0xA8: configures entering and leaving ulps */ + __RW uint32_t PHY_TX_TRIGGERS; /* 0xAC: configures the pins that activate triggers in the d-phy */ + __R uint32_t PHY_STATUS; /* 0xB0: contains information about the status of the d-phy */ + __RW uint32_t PHY_TST_CTRL0; /* 0xB4: controls clock and clear pins of the d-phy vendor specific interface */ + __RW uint32_t PHY_TST_CTRL1; /* 0xB8: controls data and enable pins of the d-phy */ + __R uint32_t INT_ST0; /* 0xBC: controls the status of interrupt */ + __R uint32_t INT_ST1; /* 0xC0: the interrupt source related to timeout etc */ + __RW uint32_t INT_MSK0; /* 0xC4: configures masks for the sources of interrupt that affec int_st0 */ + __RW uint32_t INT_MSK1; /* 0xC8: configures masks for int_st1 */ + __RW uint32_t PHY_CAL; /* 0xCC: controls the skew calibration of D-phy */ + __R uint8_t RESERVED2[8]; /* 0xD0 - 0xD7: Reserved */ + __RW uint32_t INT_FORCE0; /* 0xD8: forces that affect the int_st0 register */ + __RW uint32_t INT_FORCE1; /* 0xDC: forces interrupts that affect the int_st1 register */ + __R uint8_t RESERVED3[20]; /* 0xE0 - 0xF3: Reserved */ + __RW uint32_t PHY_TMR_RD; /* 0xF4: configures times related to PHY to perform some operations in lane byte clock cycle */ + __RW uint32_t AUTO_ULPS_MIN_TIME; /* 0xF8: configures the minimum time required by phy between ulpsactivenot and ulpsexitreq for clock and data lane */ + __RW uint32_t PHY_MODE; /* 0xFC: select phy mode */ + __RW uint32_t VID_SHADOW_CTRL; /* 0x100: controls dpi shadow feature */ + __R uint8_t RESERVED4[8]; /* 0x104 - 0x10B: Reserved */ + __R uint32_t DPI_VCID_ACT; /* 0x10C: holds the value that controller is using for DPI_VCID */ + __R uint32_t DPI_COLOR_CODING_ACT; /* 0x110: holds the value that controller is using for DPI_COLOR_CODING */ + __R uint8_t RESERVED5[4]; /* 0x114 - 0x117: Reserved */ + __R uint32_t DPI_LP_CMD_TIM_ACT; /* 0x118: holds value that controller is using for dpi_lp_cmd_time */ + __R uint8_t RESERVED6[28]; /* 0x11C - 0x137: Reserved */ + __R uint32_t VID_MODE_CFG_ACT; /* 0x138: holds value that controller is using for vid_mode_cfg */ + __R uint32_t VID_PKT_SIZE_ACT; /* 0x13C: holds value that controller is using for vid_pkt_size */ + __R uint32_t VID_NUM_CHUNKS_ACT; /* 0x140: holds value that controller is using for vid_num_chunks */ + __R uint32_t VID_NULL_SIZE_ACT; /* 0x144: holds the value that controller is using for vid_null_size */ + __R uint32_t VID_HSA_TIME_ACT; /* 0x148: the value of vid_hsa_time */ + __R uint32_t VID_HBP_TIME_ACT; /* 0x14C: the value that controller is using for vid_hbp_time */ + __R uint32_t VID_HLINE_TIME_ACT; /* 0x150: the value for vid_hline_time */ + __R uint32_t VID_VSA_LINES_ACT; /* 0x154: value for vid_vsa_lines */ + __R uint32_t VID_VBP_LINES_ACT; /* 0x158: value for vid_vbp_lines */ + __R uint32_t VID_VFP_LINES_ACT; /* 0x15C: value for vid_vfp_lines */ + __R uint32_t VID_VACTIVE_LINES_ACT; /* 0x160: value for vid_vactive_lines */ + __R uint8_t RESERVED7[4]; /* 0x164 - 0x167: Reserved */ + __R uint32_t VID_PKT_STATUS; /* 0x168: status of fifo related to dpi */ + __R uint8_t RESERVED8[36]; /* 0x16C - 0x18F: Reserved */ + __R uint32_t SDF_3D_ACT; /* 0x190: value for sdf_3d */ +} MIPI_DSI_Type; + + +/* Bitfield definition for register: VERSION */ +/* + * VERSION (RO) + * + * version of DSI + */ +#define MIPI_DSI_VERSION_VERSION_MASK (0xFFFFFFFFUL) +#define MIPI_DSI_VERSION_VERSION_SHIFT (0U) +#define MIPI_DSI_VERSION_VERSION_GET(x) (((uint32_t)(x) & MIPI_DSI_VERSION_VERSION_MASK) >> MIPI_DSI_VERSION_VERSION_SHIFT) + +/* Bitfield definition for register: PWR_UP */ +/* + * SHUTDOWNZ (RW) + * + * 0x0: reset the core + * 0x1: power up the core + */ +#define MIPI_DSI_PWR_UP_SHUTDOWNZ_MASK (0x1U) +#define MIPI_DSI_PWR_UP_SHUTDOWNZ_SHIFT (0U) +#define MIPI_DSI_PWR_UP_SHUTDOWNZ_SET(x) (((uint32_t)(x) << MIPI_DSI_PWR_UP_SHUTDOWNZ_SHIFT) & MIPI_DSI_PWR_UP_SHUTDOWNZ_MASK) +#define MIPI_DSI_PWR_UP_SHUTDOWNZ_GET(x) (((uint32_t)(x) & MIPI_DSI_PWR_UP_SHUTDOWNZ_MASK) >> MIPI_DSI_PWR_UP_SHUTDOWNZ_SHIFT) + +/* Bitfield definition for register: CLKMGR_CFG */ +/* + * TO_CLK_DIVISION (RW) + * + * the timeout clock division factor for HS to LP and LP to HS transition error + */ +#define MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_MASK (0xFF00U) +#define MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_SHIFT (8U) +#define MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_SET(x) (((uint32_t)(x) << MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_SHIFT) & MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_MASK) +#define MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_GET(x) (((uint32_t)(x) & MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_MASK) >> MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_SHIFT) + +/* + * TX_ESC_CLK_DIVISION (RW) + * + * the division factor for the TX Escape clock source lanebyteclk + */ +#define MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_MASK (0xFFU) +#define MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_SHIFT (0U) +#define MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_SET(x) (((uint32_t)(x) << MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_SHIFT) & MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_MASK) +#define MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_GET(x) (((uint32_t)(x) & MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_MASK) >> MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_SHIFT) + +/* Bitfield definition for register: DPI_VCID */ +/* + * DPI_VCID (RW) + * + * the DPI virtual channel id to the video mode packets + */ +#define MIPI_DSI_DPI_VCID_DPI_VCID_MASK (0x3U) +#define MIPI_DSI_DPI_VCID_DPI_VCID_SHIFT (0U) +#define MIPI_DSI_DPI_VCID_DPI_VCID_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_VCID_DPI_VCID_SHIFT) & MIPI_DSI_DPI_VCID_DPI_VCID_MASK) +#define MIPI_DSI_DPI_VCID_DPI_VCID_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_VCID_DPI_VCID_MASK) >> MIPI_DSI_DPI_VCID_DPI_VCID_SHIFT) + +/* Bitfield definition for register: DPI_COLOR_CODING */ +/* + * LOOSELY18_EN (RW) + * + * when set to 1, this bit activates loosely packed variant to 18-bit configurations + */ +#define MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_MASK (0x100U) +#define MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_SHIFT (8U) +#define MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_SHIFT) & MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_MASK) +#define MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_MASK) >> MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_SHIFT) + +/* + * DPI_COLOR_CODING (RW) + * + * configures the DPI color for video mode + */ +#define MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_MASK (0xFU) +#define MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SHIFT (0U) +#define MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SHIFT) & MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_MASK) +#define MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_MASK) >> MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SHIFT) + +/* Bitfield definition for register: DPI_CFG_POL */ +/* + * COLORM_ACTIVE_LOW (RW) + * + * configures the color mode pin as active low + */ +#define MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_MASK (0x10U) +#define MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_SHIFT (4U) +#define MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_SHIFT) & MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_MASK) +#define MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_MASK) >> MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_SHIFT) + +/* + * SHUTD_ACTIVE_LOW (RW) + * + * configures the shutdown pin as active low + */ +#define MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_MASK (0x8U) +#define MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_SHIFT (3U) +#define MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_SHIFT) & MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_MASK) +#define MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_MASK) >> MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_SHIFT) + +/* + * HSYNC_ACTIVE_LOW (RW) + * + * configures the horizontal synchronism pin as active low + */ +#define MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_MASK (0x4U) +#define MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_SHIFT (2U) +#define MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_SHIFT) & MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_MASK) +#define MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_MASK) >> MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_SHIFT) + +/* + * VSYNC_ACTIVE_LOW (RW) + * + * configures the vertical synchronism pin as active low + */ +#define MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_MASK (0x2U) +#define MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_SHIFT (1U) +#define MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_SHIFT) & MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_MASK) +#define MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_MASK) >> MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_SHIFT) + +/* + * DATAEN_ACTIVE_LOW (RW) + * + * configures the data enable pin active low + */ +#define MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_MASK (0x1U) +#define MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_SHIFT (0U) +#define MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_SHIFT) & MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_MASK) +#define MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_MASK) >> MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_SHIFT) + +/* Bitfield definition for register: DPI_LP_CMD_TIM */ +/* + * OUTVACT_LPCMD_TIME (RW) + * + * transmission of commands in low-power mode, defines the size in bytes of the largest pachet that can fit in a line during the VSA VBP and VFP; + */ +#define MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_MASK (0xFF0000UL) +#define MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_SHIFT (16U) +#define MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_SHIFT) & MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_MASK) +#define MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_MASK) >> MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_SHIFT) + +/* + * INVACT_LPCMD_TIME (RW) + * + * transmission of commands in low-power mode, defines the size in bytes of the largest packet that can fit in a line during the VACT region. + */ +#define MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_MASK (0xFFU) +#define MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_SHIFT (0U) +#define MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_SHIFT) & MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_MASK) +#define MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_MASK) >> MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_SHIFT) + +/* Bitfield definition for register: PCKHDL_CFG */ +/* + * EOTP_TX_LP_EN (RW) + * + * enable the EoTp transmission in low-power + */ +#define MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_MASK (0x20U) +#define MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_SHIFT (5U) +#define MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_MASK) +#define MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_SHIFT) + +/* + * CRC_RX_EN (RW) + * + * enable the crc reception and error reporting + */ +#define MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_MASK (0x10U) +#define MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_SHIFT (4U) +#define MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_MASK) +#define MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_SHIFT) + +/* + * ECC_RX_EN (RW) + * + * enable the ecc reception error correction and reporting + */ +#define MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_MASK (0x8U) +#define MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_SHIFT (3U) +#define MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_MASK) +#define MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_SHIFT) + +/* + * BTA_EN (RW) + * + * enable the bus turn-around request + */ +#define MIPI_DSI_PCKHDL_CFG_BTA_EN_MASK (0x4U) +#define MIPI_DSI_PCKHDL_CFG_BTA_EN_SHIFT (2U) +#define MIPI_DSI_PCKHDL_CFG_BTA_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_BTA_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_BTA_EN_MASK) +#define MIPI_DSI_PCKHDL_CFG_BTA_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_BTA_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_BTA_EN_SHIFT) + +/* + * EOTP_RX_EN (RW) + * + * enable the EoTp reception + */ +#define MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_MASK (0x2U) +#define MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_SHIFT (1U) +#define MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_MASK) +#define MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_SHIFT) + +/* + * EOTP_TX_EN (RW) + * + * enable the EoTp transmission in high-speed + */ +#define MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_MASK (0x1U) +#define MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_SHIFT (0U) +#define MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_MASK) +#define MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_SHIFT) + +/* Bitfield definition for register: GEN_VCID */ +/* + * GEN_VCID_TX_AUTO (RW) + * + * indicates the generic interface virtual channel identification where generic packet is automatically generated and transmitted + */ +#define MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_MASK (0x30000UL) +#define MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_SHIFT (16U) +#define MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_SHIFT) & MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_MASK) +#define MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_MASK) >> MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_SHIFT) + +/* + * GEN_VCID_TEAR_AUTO (RW) + * + * indicates the virtual channel identification for tear effect by hardware + */ +#define MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_MASK (0x300U) +#define MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_SHIFT (8U) +#define MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_SHIFT) & MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_MASK) +#define MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_MASK) >> MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_SHIFT) + +/* + * GEN_VCID_RX (RW) + * + * indicates the generic interface read-back virtual channel identication + */ +#define MIPI_DSI_GEN_VCID_GEN_VCID_RX_MASK (0x3U) +#define MIPI_DSI_GEN_VCID_GEN_VCID_RX_SHIFT (0U) +#define MIPI_DSI_GEN_VCID_GEN_VCID_RX_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_VCID_GEN_VCID_RX_SHIFT) & MIPI_DSI_GEN_VCID_GEN_VCID_RX_MASK) +#define MIPI_DSI_GEN_VCID_GEN_VCID_RX_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_VCID_GEN_VCID_RX_MASK) >> MIPI_DSI_GEN_VCID_GEN_VCID_RX_SHIFT) + +/* Bitfield definition for register: MODE_CFG */ +/* + * CMD_VIDEO_MODE (RW) + * + * 0x0: video mode + * 0x1: command mode + */ +#define MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_MASK (0x1U) +#define MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_SHIFT (0U) +#define MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_SET(x) (((uint32_t)(x) << MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_SHIFT) & MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_MASK) +#define MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_GET(x) (((uint32_t)(x) & MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_MASK) >> MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_SHIFT) + +/* Bitfield definition for register: VID_MODE_CFG */ +/* + * VPG_ORIENTATION (RW) + * + * indicates the color bar orientation : + * 0x0: vertical mode + * 0x1: horizontal mode + */ +#define MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_MASK (0x1000000UL) +#define MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_SHIFT (24U) +#define MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_SHIFT) & MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_MASK) +#define MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_MASK) >> MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_SHIFT) + +/* + * VPG_MODE (RW) + * + * 0x0: colorbar + * 0x1: berpattern, vertical only + */ +#define MIPI_DSI_VID_MODE_CFG_VPG_MODE_MASK (0x100000UL) +#define MIPI_DSI_VID_MODE_CFG_VPG_MODE_SHIFT (20U) +#define MIPI_DSI_VID_MODE_CFG_VPG_MODE_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_VPG_MODE_SHIFT) & MIPI_DSI_VID_MODE_CFG_VPG_MODE_MASK) +#define MIPI_DSI_VID_MODE_CFG_VPG_MODE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_VPG_MODE_MASK) >> MIPI_DSI_VID_MODE_CFG_VPG_MODE_SHIFT) + +/* + * VPG_EN (RW) + * + * enable video mode pattern generator + */ +#define MIPI_DSI_VID_MODE_CFG_VPG_EN_MASK (0x10000UL) +#define MIPI_DSI_VID_MODE_CFG_VPG_EN_SHIFT (16U) +#define MIPI_DSI_VID_MODE_CFG_VPG_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_VPG_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_VPG_EN_MASK) +#define MIPI_DSI_VID_MODE_CFG_VPG_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_VPG_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_VPG_EN_SHIFT) + +/* + * LP_CMD_EN (RW) + * + * enable command transmission only in low-power mode + */ +#define MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_MASK (0x8000U) +#define MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_SHIFT (15U) +#define MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_MASK) +#define MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_SHIFT) + +/* + * FRAME_BTA_ACK_EN (RW) + * + * enable the request for an acknowledge response at the end of a frame + */ +#define MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_MASK (0x4000U) +#define MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_SHIFT (14U) +#define MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_MASK) +#define MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_SHIFT) + +/* + * LP_HFP_EN (RW) + * + * enable the return to low-power inside the HFP period when timing allows + */ +#define MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_MASK (0x2000U) +#define MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_SHIFT (13U) +#define MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_MASK) +#define MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_SHIFT) + +/* + * LP_HBP_EN (RW) + * + * enable the return to low-power inside the HBP period when timing allows + */ +#define MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_MASK (0x1000U) +#define MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_SHIFT (12U) +#define MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_MASK) +#define MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_SHIFT) + +/* + * LP_VACT_EN (RW) + * + * enable the return to low-power inside the VACT period when timing allows + */ +#define MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_MASK (0x800U) +#define MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_SHIFT (11U) +#define MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_MASK) +#define MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_SHIFT) + +/* + * LP_VFP_EN (RW) + * + * enable the return to low-power inside the VFP period when timing allows + */ +#define MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_MASK (0x400U) +#define MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_SHIFT (10U) +#define MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_MASK) +#define MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_SHIFT) + +/* + * LP_VBP_EN (RW) + * + * enable the return to low-power inside the VBP period when timing allows + */ +#define MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_MASK (0x200U) +#define MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_SHIFT (9U) +#define MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_MASK) +#define MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_SHIFT) + +/* + * LP_VSA_EN (RW) + * + * enable the return to low-power inside the VSA period when timing allows + */ +#define MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_MASK (0x100U) +#define MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_SHIFT (8U) +#define MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_MASK) +#define MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_SHIFT) + +/* + * VID_MODE_TYPE (RW) + * + * indicates the video mode transmission type + */ +#define MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_MASK (0x3U) +#define MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_SHIFT (0U) +#define MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_SHIFT) & MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_MASK) +#define MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_MASK) >> MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_SHIFT) + +/* Bitfield definition for register: VID_PKT_SIZE */ +/* + * VID_PKT_SIZE (RW) + * + * configures the number of pixels in a single video packet + */ +#define MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_MASK (0x3FFFU) +#define MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_SHIFT (0U) +#define MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_SHIFT) & MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_MASK) +#define MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_MASK) >> MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_SHIFT) + +/* Bitfield definition for register: VID_NUM_CHUNKS */ +/* + * VID_NUM_CHUNKS (RW) + * + * configures the number of chunks to be transmitted a line period + */ +#define MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_MASK (0x1FFFU) +#define MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_SHIFT (0U) +#define MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_SHIFT) & MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_MASK) +#define MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_MASK) >> MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_SHIFT) + +/* Bitfield definition for register: VID_NULL_SIZE */ +/* + * VID_NULL_SIZE (RW) + * + * configures the number of bytes inside a null packet + */ +#define MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_MASK (0x1FFFU) +#define MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_SHIFT (0U) +#define MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_SHIFT) & MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_MASK) +#define MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_MASK) >> MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_SHIFT) + +/* Bitfield definition for register: VID_HSA_TIME */ +/* + * VID_HSA_TIME (RW) + * + * configure the Horizontal synchronism active period in lane byte clock cycles + */ +#define MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_MASK (0xFFFU) +#define MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_SHIFT (0U) +#define MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_SHIFT) & MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_MASK) +#define MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_MASK) >> MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_SHIFT) + +/* Bitfield definition for register: VID_HBP_TIME */ +/* + * VID_HPB_TIME (RW) + * + * configures the Horizontal back porch period in lane byte clock cycles + */ +#define MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_MASK (0xFFFU) +#define MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_SHIFT (0U) +#define MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_SHIFT) & MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_MASK) +#define MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_MASK) >> MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_SHIFT) + +/* Bitfield definition for register: VID_HLINE_TIME */ +/* + * VID_HLINE_TIME (RW) + * + * configures the size of the total line time in lane byte clock cycles + */ +#define MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_MASK (0x7FFFU) +#define MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_SHIFT (0U) +#define MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_SHIFT) & MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_MASK) +#define MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_MASK) >> MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_SHIFT) + +/* Bitfield definition for register: VID_VSA_LINES */ +/* + * VSA_LINES (RW) + * + * configures the verical synchronism active period measured in number of horizontal lines + */ +#define MIPI_DSI_VID_VSA_LINES_VSA_LINES_MASK (0x3FFU) +#define MIPI_DSI_VID_VSA_LINES_VSA_LINES_SHIFT (0U) +#define MIPI_DSI_VID_VSA_LINES_VSA_LINES_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_VSA_LINES_VSA_LINES_SHIFT) & MIPI_DSI_VID_VSA_LINES_VSA_LINES_MASK) +#define MIPI_DSI_VID_VSA_LINES_VSA_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VSA_LINES_VSA_LINES_MASK) >> MIPI_DSI_VID_VSA_LINES_VSA_LINES_SHIFT) + +/* Bitfield definition for register: VID_VBP_LINES */ +/* + * VBP_LINES (RW) + * + * configures the vertical back porch period measured in number of horizontal lines + */ +#define MIPI_DSI_VID_VBP_LINES_VBP_LINES_MASK (0x3FFU) +#define MIPI_DSI_VID_VBP_LINES_VBP_LINES_SHIFT (0U) +#define MIPI_DSI_VID_VBP_LINES_VBP_LINES_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_VBP_LINES_VBP_LINES_SHIFT) & MIPI_DSI_VID_VBP_LINES_VBP_LINES_MASK) +#define MIPI_DSI_VID_VBP_LINES_VBP_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VBP_LINES_VBP_LINES_MASK) >> MIPI_DSI_VID_VBP_LINES_VBP_LINES_SHIFT) + +/* Bitfield definition for register: VID_VFP_LINES */ +/* + * VFP_LINIES (RW) + * + * configures the vertical front porch period measured in number of horizontal lines + */ +#define MIPI_DSI_VID_VFP_LINES_VFP_LINIES_MASK (0x3FFU) +#define MIPI_DSI_VID_VFP_LINES_VFP_LINIES_SHIFT (0U) +#define MIPI_DSI_VID_VFP_LINES_VFP_LINIES_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_VFP_LINES_VFP_LINIES_SHIFT) & MIPI_DSI_VID_VFP_LINES_VFP_LINIES_MASK) +#define MIPI_DSI_VID_VFP_LINES_VFP_LINIES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VFP_LINES_VFP_LINIES_MASK) >> MIPI_DSI_VID_VFP_LINES_VFP_LINIES_SHIFT) + +/* Bitfield definition for register: VID_VACTIVE_LINES */ +/* + * V_ACTIVE_LINES (RW) + * + * configures the vertical active period measured in number of horizontal lines + */ +#define MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_MASK (0x3FFFU) +#define MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_SHIFT (0U) +#define MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_SHIFT) & MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_MASK) +#define MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_MASK) >> MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_SHIFT) + +/* Bitfield definition for register: CMD_MODE_CFG */ +/* + * MAX_RD_PKT_SIZE (RW) + * + * This bit configures the maximum read packet size command transmission type: + * 0x0 (HIGHSPEED): Transition type is High Speed + * 0x1 (LOWPOWER): Transition type is Low Power + */ +#define MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_MASK (0x1000000UL) +#define MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_SHIFT (24U) +#define MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_SHIFT) & MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_MASK) +#define MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_MASK) >> MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_SHIFT) + +/* + * DCS_LW_TX (RW) + * + * This bit configures the DCS long write packet command transmission type: + * 0x0 (HIGHSPEED): Transition type is High Speed + * 0x1 (LOWPOWER): Transition type is Low Power + */ +#define MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_MASK (0x80000UL) +#define MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_SHIFT (19U) +#define MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_MASK) +#define MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_SHIFT) + +/* + * DCS_SR_0P_TX (RW) + * + * This bit configures the DCS short read packet with zero parameter command transmission type: + * 0x0 (HIGHSPEED): Transition type is High Speed + * 0x1 (LOWPOWER): Transition type is Low Power + */ +#define MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_MASK (0x40000UL) +#define MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_SHIFT (18U) +#define MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_MASK) +#define MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_SHIFT) + +/* + * DCS_SW_1P_TX (RW) + * + * This bit configures the DCS short write packet with one parameter command transmission type: + * 0x0 (HIGHSPEED): Transition type is High Speed + * 0x1 (LOWPOWER): Transition type is Low Power + */ +#define MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_MASK (0x20000UL) +#define MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_SHIFT (17U) +#define MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_MASK) +#define MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_SHIFT) + +/* + * DCS_SW_0P_TX (RW) + * + * This bit configures the DCS short write packet with zero parameter command transmission type: + * 0x0 (HIGHSPEED): Transition type is High Speed + * 0x1 (LOWPOWER): Transition type is Low Power + */ +#define MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_MASK (0x10000UL) +#define MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_SHIFT (16U) +#define MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_MASK) +#define MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_SHIFT) + +/* + * GEN_LW_TX (RW) + * + * This bit configures the Generic long write packet command transmission type: + * 0x0 (HIGHSPEED): Transition type is High Speed + * 0x1 (LOWPOWER): Transition type is Low Power + */ +#define MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_MASK (0x4000U) +#define MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_SHIFT (14U) +#define MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_MASK) +#define MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_SHIFT) + +/* + * GEN_SR_2P_TX (RW) + * + * This bit configures the Generic short read packet with two parameters command transmission type: + * 0x0 (HIGHSPEED): Transition type is High Speed + * 0x1 (LOWPOWER): Transition type is Low Power + */ +#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_MASK (0x2000U) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_SHIFT (13U) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_MASK) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_SHIFT) + +/* + * GEN_SR_1P_TX (RW) + * + * This bit configures the Generic short read packet with two parameters command transmission type: + * 0x0 (HIGHSPEED): Transition type is High Speed + * 0x1 (LOWPOWER): Transition type is Low Power + */ +#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_MASK (0x1000U) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_SHIFT (12U) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_MASK) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_SHIFT) + +/* + * GEN_SR_0P_TX (RW) + * + * This bit configures the Generic short read packet with two parameters command transmission type: + * 0x0 (HIGHSPEED): Transition type is High Speed + * 0x1 (LOWPOWER): Transition type is Low Power + */ +#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_MASK (0x800U) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_SHIFT (11U) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_MASK) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_SHIFT) + +/* + * GEN_SW_2P_TX (RW) + * + * This bit configures the Generic short read packet with two parameters command transmission type: + * 0x0 (HIGHSPEED): Transition type is High Speed + * 0x1 (LOWPOWER): Transition type is Low Power + */ +#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_MASK (0x400U) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_SHIFT (10U) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_MASK) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_SHIFT) + +/* + * GEN_SW_1P_TX (RW) + * + * This bit configures the Generic short read packet with two parameters command transmission type: + * 0x0 (HIGHSPEED): Transition type is High Speed + * 0x1 (LOWPOWER): Transition type is Low Power + */ +#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_MASK (0x200U) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_SHIFT (9U) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_MASK) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_SHIFT) + +/* + * GEN_SW_0P_TX (RW) + * + * This bit configures the Generic short read packet with two parameters command transmission type: + * 0x0 (HIGHSPEED): Transition type is High Speed + * 0x1 (LOWPOWER): Transition type is Low Power + */ +#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_MASK (0x100U) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_SHIFT (8U) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_MASK) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_SHIFT) + +/* + * ACK_RQST_EN (RW) + * + * When set to 1, this bit enables the acknowledge request after each packet transmission. + */ +#define MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_MASK (0x2U) +#define MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_SHIFT (1U) +#define MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_SHIFT) & MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_MASK) +#define MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_MASK) >> MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_SHIFT) + +/* + * TEAR_FX_EN (RW) + * + * When set to 1, this bit enables the tearing effect acknowledge request. + */ +#define MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_MASK (0x1U) +#define MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_SHIFT (0U) +#define MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_SHIFT) & MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_MASK) +#define MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_MASK) >> MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_SHIFT) + +/* Bitfield definition for register: GEN_HDR */ +/* + * GEN_WC_MSBYTE (RW) + * + * configures the most significant byte of the header packet's word count for long packets or data 1 for shout packets + */ +#define MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_MASK (0xFF0000UL) +#define MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_SHIFT (16U) +#define MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_SHIFT) & MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_MASK) +#define MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_MASK) >> MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_SHIFT) + +/* + * GEN_WC_LSBYTE (RW) + * + * configures the least significant byte of the header packet's word count for long packets or data0 for short packets + */ +#define MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_MASK (0xFF00U) +#define MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_SHIFT (8U) +#define MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_SHIFT) & MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_MASK) +#define MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_MASK) >> MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_SHIFT) + +/* + * GEN_VC (RW) + * + * configures the virtual channel ID of the header packet + */ +#define MIPI_DSI_GEN_HDR_GEN_VC_MASK (0xC0U) +#define MIPI_DSI_GEN_HDR_GEN_VC_SHIFT (6U) +#define MIPI_DSI_GEN_HDR_GEN_VC_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_HDR_GEN_VC_SHIFT) & MIPI_DSI_GEN_HDR_GEN_VC_MASK) +#define MIPI_DSI_GEN_HDR_GEN_VC_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_HDR_GEN_VC_MASK) >> MIPI_DSI_GEN_HDR_GEN_VC_SHIFT) + +/* + * GEN_DT (RW) + * + * configures the packet data type of the header packet + */ +#define MIPI_DSI_GEN_HDR_GEN_DT_MASK (0x3FU) +#define MIPI_DSI_GEN_HDR_GEN_DT_SHIFT (0U) +#define MIPI_DSI_GEN_HDR_GEN_DT_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_HDR_GEN_DT_SHIFT) & MIPI_DSI_GEN_HDR_GEN_DT_MASK) +#define MIPI_DSI_GEN_HDR_GEN_DT_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_HDR_GEN_DT_MASK) >> MIPI_DSI_GEN_HDR_GEN_DT_SHIFT) + +/* Bitfield definition for register: GEN_PLD_DATA */ +/* + * GEN_PLD_B4 (RW) + * + * indicates byte4 of the packet payload + */ +#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_MASK (0xFF000000UL) +#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_SHIFT (24U) +#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_SHIFT) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_MASK) +#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_MASK) >> MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_SHIFT) + +/* + * GEN_PLD_B3 (RW) + * + * indicates byte3 of the packet payload + */ +#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_MASK (0xFF0000UL) +#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_SHIFT (16U) +#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_SHIFT) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_MASK) +#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_MASK) >> MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_SHIFT) + +/* + * GEN_PLD_B2 (RW) + * + * indicates byte2 of the packet payload + */ +#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_MASK (0xFF00U) +#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_SHIFT (8U) +#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_SHIFT) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_MASK) +#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_MASK) >> MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_SHIFT) + +/* + * GEN_PLD_B1 (RW) + * + * indicates byte1 of the packet payload + */ +#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_MASK (0xFFU) +#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_SHIFT (0U) +#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_SHIFT) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_MASK) +#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_MASK) >> MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_SHIFT) + +/* Bitfield definition for register: CMD_PKT_STATUS */ +/* + * GEN_BUFF_PLD_FULL (R) + * + * the full status of the generic payload internal buffer + */ +#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_MASK (0x80000UL) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_SHIFT (19U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_SHIFT) + +/* + * GEN_BUFF_PLD_EMPTY (R) + * + * the empty status of the generic payload internal buffer + */ +#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_MASK (0x40000UL) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_SHIFT (18U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_SHIFT) + +/* + * GEN_BUFF_CMD_FULL (R) + * + * the full status of the generic command internal buffer + */ +#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_MASK (0x20000UL) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_SHIFT (17U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_SHIFT) + +/* + * GEN_BUFF_CMD_EMPTY (R) + * + * the empty status of the generic command internal buffer + */ +#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_MASK (0x10000UL) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_SHIFT (16U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_SHIFT) + +/* + * GEN_RD_CMD_BUSY (R) + * + * indicates a read command is issued and the entire response is not sotred in the FIFO + */ +#define MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_MASK (0x40U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_SHIFT (6U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_SHIFT) + +/* + * GEN_PLD_R_FULL (R) + * + * indicates the full status of the generic read payoad FIFO + */ +#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_MASK (0x20U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_SHIFT (5U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_SHIFT) + +/* + * GEN_PLD_R_EMPTY (R) + * + * indicates the empty status of the generic read payload FIFO + */ +#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_MASK (0x10U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_SHIFT (4U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_SHIFT) + +/* + * GEN_PLD_W_FULL (R) + * + * indicates the full status of the generic write payload FIFO + */ +#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_MASK (0x8U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_SHIFT (3U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_SHIFT) + +/* + * GEN_PLD_W_EMPTY (R) + * + * indicates the empty status of the generic write payload FIFO + */ +#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_MASK (0x4U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_SHIFT (2U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_SHIFT) + +/* + * GEN_CMD_FULL (R) + * + * indicates the full status of the generic command FIFO + */ +#define MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_MASK (0x2U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_SHIFT (1U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_SHIFT) + +/* + * GEN_CMD_EMPTY (R) + * + * indicates the empty status of the generic command FIFO + */ +#define MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_MASK (0x1U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_SHIFT (0U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_SHIFT) + +/* Bitfield definition for register: TO_CNT_CFG */ +/* + * HSTX_TO_CNT (RW) + * + * configures the timeout counter that triggers a high speed transmission timeout contention detection + */ +#define MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_MASK (0xFFFF0000UL) +#define MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_SHIFT (16U) +#define MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_SHIFT) & MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_MASK) +#define MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_MASK) >> MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_SHIFT) + +/* + * LPRX_TO_CNT (RW) + * + * configures the timeout counter that triggers a low power reception timeout contention detection + */ +#define MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_MASK (0xFFFFU) +#define MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_SHIFT (0U) +#define MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_SHIFT) & MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_MASK) +#define MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_MASK) >> MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_SHIFT) + +/* Bitfield definition for register: HS_RD_TO_CNT */ +/* + * HS_RD_TO_CNT (RW) + * + * sets a period for which DWC_mipi_dsi_host keeps the link still after sending a high speed read operation; + */ +#define MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_MASK (0xFFFFU) +#define MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_SHIFT (0U) +#define MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_SHIFT) & MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_MASK) +#define MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_MASK) >> MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_SHIFT) + +/* Bitfield definition for register: LP_RD_TO_CNT */ +/* + * LP_RD_TO_CNT (RW) + * + * sets a period for which dwc_mipi_dsi_host keeps the link still after sending a low power read operation + */ +#define MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_MASK (0xFFFFU) +#define MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_SHIFT (0U) +#define MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_SHIFT) & MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_MASK) +#define MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_MASK) >> MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_SHIFT) + +/* Bitfield definition for register: HS_WR_TO_CNT */ +/* + * HS_WR_TO_CNT (RW) + * + * sets the period for which dwc_mipi_dsi_host keeps the link still after sending a high speed wirte operation + */ +#define MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_MASK (0xFFFFU) +#define MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_SHIFT (0U) +#define MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_SHIFT) & MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_MASK) +#define MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_MASK) >> MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_SHIFT) + +/* Bitfield definition for register: LP_WR_TO_CNT */ +/* + * LP_WR_TO_CNT (RW) + * + * sets the period for which dsi host keeps the link still after sending a low power write operation + */ +#define MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_MASK (0xFFFFU) +#define MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_SHIFT (0U) +#define MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_SHIFT) & MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_MASK) +#define MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_MASK) >> MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_SHIFT) + +/* Bitfield definition for register: BTA_TO_CNT */ +/* + * BTA_TO_CNT (RW) + * + * sets the period for which dsi host keeps the link still after completing a bus turnaround. + */ +#define MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_MASK (0xFFFFU) +#define MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_SHIFT (0U) +#define MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_SHIFT) & MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_MASK) +#define MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_MASK) >> MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_SHIFT) + +/* Bitfield definition for register: SDF_3D */ +/* + * SEND_3D_CFG (RW) + * + * set the next vss packet to include 3d control payload in every vss packet + */ +#define MIPI_DSI_SDF_3D_SEND_3D_CFG_MASK (0x10000UL) +#define MIPI_DSI_SDF_3D_SEND_3D_CFG_SHIFT (16U) +#define MIPI_DSI_SDF_3D_SEND_3D_CFG_SET(x) (((uint32_t)(x) << MIPI_DSI_SDF_3D_SEND_3D_CFG_SHIFT) & MIPI_DSI_SDF_3D_SEND_3D_CFG_MASK) +#define MIPI_DSI_SDF_3D_SEND_3D_CFG_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_SEND_3D_CFG_MASK) >> MIPI_DSI_SDF_3D_SEND_3D_CFG_SHIFT) + +/* + * RIGHT_FIRST (RW) + * + * 0x0: left eye is sent first + * 0x1:right eye is sent first + */ +#define MIPI_DSI_SDF_3D_RIGHT_FIRST_MASK (0x20U) +#define MIPI_DSI_SDF_3D_RIGHT_FIRST_SHIFT (5U) +#define MIPI_DSI_SDF_3D_RIGHT_FIRST_SET(x) (((uint32_t)(x) << MIPI_DSI_SDF_3D_RIGHT_FIRST_SHIFT) & MIPI_DSI_SDF_3D_RIGHT_FIRST_MASK) +#define MIPI_DSI_SDF_3D_RIGHT_FIRST_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_RIGHT_FIRST_MASK) >> MIPI_DSI_SDF_3D_RIGHT_FIRST_SHIFT) + +/* + * SECOND_VSYNC (RW) + * + * defines whether there is a second VSYNC pulse + */ +#define MIPI_DSI_SDF_3D_SECOND_VSYNC_MASK (0x10U) +#define MIPI_DSI_SDF_3D_SECOND_VSYNC_SHIFT (4U) +#define MIPI_DSI_SDF_3D_SECOND_VSYNC_SET(x) (((uint32_t)(x) << MIPI_DSI_SDF_3D_SECOND_VSYNC_SHIFT) & MIPI_DSI_SDF_3D_SECOND_VSYNC_MASK) +#define MIPI_DSI_SDF_3D_SECOND_VSYNC_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_SECOND_VSYNC_MASK) >> MIPI_DSI_SDF_3D_SECOND_VSYNC_SHIFT) + +/* + * FORMAT_3D (RW) + * + * defines 3D image format + */ +#define MIPI_DSI_SDF_3D_FORMAT_3D_MASK (0xCU) +#define MIPI_DSI_SDF_3D_FORMAT_3D_SHIFT (2U) +#define MIPI_DSI_SDF_3D_FORMAT_3D_SET(x) (((uint32_t)(x) << MIPI_DSI_SDF_3D_FORMAT_3D_SHIFT) & MIPI_DSI_SDF_3D_FORMAT_3D_MASK) +#define MIPI_DSI_SDF_3D_FORMAT_3D_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_FORMAT_3D_MASK) >> MIPI_DSI_SDF_3D_FORMAT_3D_SHIFT) + +/* + * MODE_3D (RW) + * + * defines 3D mode on/off + */ +#define MIPI_DSI_SDF_3D_MODE_3D_MASK (0x3U) +#define MIPI_DSI_SDF_3D_MODE_3D_SHIFT (0U) +#define MIPI_DSI_SDF_3D_MODE_3D_SET(x) (((uint32_t)(x) << MIPI_DSI_SDF_3D_MODE_3D_SHIFT) & MIPI_DSI_SDF_3D_MODE_3D_MASK) +#define MIPI_DSI_SDF_3D_MODE_3D_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_MODE_3D_MASK) >> MIPI_DSI_SDF_3D_MODE_3D_SHIFT) + +/* Bitfield definition for register: LPCLK_CTRL */ +/* + * AUTO_CLKLANE_CTRL (RW) + * + * enables the automatic mechanism to stop providing clock in the clock lane + */ +#define MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_MASK (0x2U) +#define MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_SHIFT (1U) +#define MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_SET(x) (((uint32_t)(x) << MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_SHIFT) & MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_MASK) +#define MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_GET(x) (((uint32_t)(x) & MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_MASK) >> MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_SHIFT) + +/* + * PHY_TXREQUESTCLKHS (RW) + * + * controls the D-PHY PPI txrequestclkhs signal + */ +#define MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_MASK (0x1U) +#define MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_SHIFT (0U) +#define MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_SET(x) (((uint32_t)(x) << MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_SHIFT) & MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_MASK) +#define MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_GET(x) (((uint32_t)(x) & MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_MASK) >> MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_SHIFT) + +/* Bitfield definition for register: PHY_TMR_LPCLK_CFG */ +/* + * PHY_CLKHS2LP_TIME (RW) + * + * configures the maximum time that the d-phy clock lane takes to go from high-speed to low-power transmission + */ +#define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_MASK (0x3FF0000UL) +#define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_SHIFT (16U) +#define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_SHIFT) & MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_MASK) +#define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_MASK) >> MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_SHIFT) + +/* + * PHY_CLKLP2HS_TIME (RW) + * + * configures the maximum time that the d-phy clock lane takes to go from low-power to high-speed transmission + */ +#define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_MASK (0x3FFU) +#define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_SHIFT (0U) +#define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_SHIFT) & MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_MASK) +#define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_MASK) >> MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_SHIFT) + +/* Bitfield definition for register: PHY_TMR_CFG */ +/* + * PHY_HS2LP_TIME (RW) + * + * This field configures the maximum time that the D-PHY data + * lanes take to go from high-speed to low-power transmission + * measured in lane byte clock cycles + */ +#define MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_MASK (0x3FF0000UL) +#define MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_SHIFT (16U) +#define MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_SHIFT) & MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_MASK) +#define MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_MASK) >> MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_SHIFT) + +/* + * PHY_LP2HS_TIME (RW) + * + * This field configures the maximum time that the D-PHY data + * lanes take to go from low-power to high-speed transmission + * measured in lane byte clock cycles. + */ +#define MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_MASK (0x3FFU) +#define MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_SHIFT (0U) +#define MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_SHIFT) & MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_MASK) +#define MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_MASK) >> MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_SHIFT) + +/* Bitfield definition for register: PHY_RSTZ */ +/* + * PHY_FORCEPLL (RW) + * + * when the d-phy is in ulps, enable the d-phy pll + */ +#define MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_MASK (0x8U) +#define MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_SHIFT (3U) +#define MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_SHIFT) & MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_MASK) +#define MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_MASK) >> MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_SHIFT) + +/* + * PHY_ENABLECLK (RW) + * + * enable dphy clock lane + */ +#define MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_MASK (0x4U) +#define MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_SHIFT (2U) +#define MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_SHIFT) & MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_MASK) +#define MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_MASK) >> MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_SHIFT) + +/* + * PHY_RSTZ (RW) + * + * make the dphy in reset state when set to 0 + */ +#define MIPI_DSI_PHY_RSTZ_PHY_RSTZ_MASK (0x2U) +#define MIPI_DSI_PHY_RSTZ_PHY_RSTZ_SHIFT (1U) +#define MIPI_DSI_PHY_RSTZ_PHY_RSTZ_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_RSTZ_PHY_RSTZ_SHIFT) & MIPI_DSI_PHY_RSTZ_PHY_RSTZ_MASK) +#define MIPI_DSI_PHY_RSTZ_PHY_RSTZ_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_RSTZ_PHY_RSTZ_MASK) >> MIPI_DSI_PHY_RSTZ_PHY_RSTZ_SHIFT) + +/* + * PHY_SHUTDOWNZ (RW) + * + * places the dphy macro in power down mode when set to 0 + */ +#define MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_MASK (0x1U) +#define MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_SHIFT (0U) +#define MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_SHIFT) & MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_MASK) +#define MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_MASK) >> MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_SHIFT) + +/* Bitfield definition for register: PHY_IF_CFG */ +/* + * PHY_STOP_WAIT_TIME (RW) + * + * configures the minimum time phy needs to stay in stopstate before requesting an highspeed transmission + */ +#define MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_MASK (0xFF00U) +#define MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_SHIFT (8U) +#define MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_SHIFT) & MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_MASK) +#define MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_MASK) >> MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_SHIFT) + +/* + * N_LANES (RW) + * + * configures the number of active data lanes + */ +#define MIPI_DSI_PHY_IF_CFG_N_LANES_MASK (0x3U) +#define MIPI_DSI_PHY_IF_CFG_N_LANES_SHIFT (0U) +#define MIPI_DSI_PHY_IF_CFG_N_LANES_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_IF_CFG_N_LANES_SHIFT) & MIPI_DSI_PHY_IF_CFG_N_LANES_MASK) +#define MIPI_DSI_PHY_IF_CFG_N_LANES_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_IF_CFG_N_LANES_MASK) >> MIPI_DSI_PHY_IF_CFG_N_LANES_SHIFT) + +/* Bitfield definition for register: PHY_ULPS_CTRL */ +/* + * PHY_TXEXITULPSLAN (RW) + * + * ulps mode exit on all active data lanes + */ +#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_MASK (0x8U) +#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_SHIFT (3U) +#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_SHIFT) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_MASK) +#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_MASK) >> MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_SHIFT) + +/* + * PHY_TXREQULPSLAN (RW) + * + * ulps mode request on all active data lanes + */ +#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_MASK (0x4U) +#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_SHIFT (2U) +#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_SHIFT) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_MASK) +#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_MASK) >> MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_SHIFT) + +/* + * PHY_TXEXITULPSCLK (RW) + * + * ulps mode exit on clock lane + */ +#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_MASK (0x2U) +#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_SHIFT (1U) +#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_SHIFT) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_MASK) +#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_MASK) >> MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_SHIFT) + +/* + * PHY_TXREQULPSCLK (RW) + * + * ulps mode request on clock lane + */ +#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_MASK (0x1U) +#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_SHIFT (0U) +#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_SHIFT) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_MASK) +#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_MASK) >> MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_SHIFT) + +/* Bitfield definition for register: PHY_TX_TRIGGERS */ +/* + * PHY_TX_TRIGGERS (RW) + * + * controls the trigger transmissions + */ +#define MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_MASK (0xFU) +#define MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_SHIFT (0U) +#define MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_SHIFT) & MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_MASK) +#define MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_MASK) >> MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_SHIFT) + +/* Bitfield definition for register: PHY_STATUS */ +/* + * PHY_ULPSACTIVENOT3LANE (R) + * + * indicates the status of ulpsactivenot3lane d-phy signal + */ +#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_MASK (0x1000U) +#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_SHIFT (12U) +#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_SHIFT) + +/* + * PHY_STOPSTATE3LANE (R) + * + * This bit indicates the status of phystopstate3lane D-PHY + * signal. + */ +#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE3LANE_MASK (0x800U) +#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE3LANE_SHIFT (11U) +#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE3LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_STOPSTATE3LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_STOPSTATE3LANE_SHIFT) + +/* + * PHY_ULPSACTIVENOT2LANE (R) + * + * This bit indicates the status of ulpsactivenot2lane D-PHY + * signa + */ +#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_MASK (0x400U) +#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_SHIFT (10U) +#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_SHIFT) + +/* + * PHY_STOPSTATE2LANE (R) + * + * This bit indicates the status of phystopstate2lane D-PHY + * signal + */ +#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE2LANE_MASK (0x200U) +#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE2LANE_SHIFT (9U) +#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE2LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_STOPSTATE2LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_STOPSTATE2LANE_SHIFT) + +/* + * PHY_ULPSACTIVENOT1LANE (R) + * + * This bit indicates the status of ulpsactivenot1lane D-PHY + * signal + */ +#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_MASK (0x100U) +#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_SHIFT (8U) +#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_SHIFT) + +/* + * PHY_STOPSTATE1LANE (R) + * + * This bit indicates the status of phystopstate1lane D-PHY + * signal + */ +#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE1LANE_MASK (0x80U) +#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE1LANE_SHIFT (7U) +#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE1LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_STOPSTATE1LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_STOPSTATE1LANE_SHIFT) + +/* + * PHY_RXULPSESC0LANE (R) + * + * This bit indicates the status of rxulpsesc0lane D-PHY signa + */ +#define MIPI_DSI_PHY_STATUS_PHY_RXULPSESC0LANE_MASK (0x40U) +#define MIPI_DSI_PHY_STATUS_PHY_RXULPSESC0LANE_SHIFT (6U) +#define MIPI_DSI_PHY_STATUS_PHY_RXULPSESC0LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_RXULPSESC0LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_RXULPSESC0LANE_SHIFT) + +/* + * PHY_ULPSACTIVENOT0LANE (R) + * + * This bit indicates the status of ulpsactivenot0lane D-PHY + * signal + */ +#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_MASK (0x20U) +#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_SHIFT (5U) +#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_SHIFT) + +/* + * PHY_STOPSTATE0LANE (R) + * + * This bit indicates the status of phystopstate0lane D-PHY + * signal + */ +#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE0LANE_MASK (0x10U) +#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE0LANE_SHIFT (4U) +#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE0LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_STOPSTATE0LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_STOPSTATE0LANE_SHIFT) + +/* + * PHY_ULPSACTIVENOTCLK (R) + * + * This bit indicates the status of phyulpsactivenotclk D-PHY + * signal + */ +#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_MASK (0x8U) +#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_SHIFT (3U) +#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_MASK) >> MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_SHIFT) + +/* + * PHY_STOPSTATECLKLANE (R) + * + * This bit indicates the status of phystopstateclklane D-PHY + * signal + */ +#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATECLKLANE_MASK (0x4U) +#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATECLKLANE_SHIFT (2U) +#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATECLKLANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_STOPSTATECLKLANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_STOPSTATECLKLANE_SHIFT) + +/* + * PHY_DIRECTION (R) + * + * This bit indicates the status of phydirection D-PHY signal + */ +#define MIPI_DSI_PHY_STATUS_PHY_DIRECTION_MASK (0x2U) +#define MIPI_DSI_PHY_STATUS_PHY_DIRECTION_SHIFT (1U) +#define MIPI_DSI_PHY_STATUS_PHY_DIRECTION_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_DIRECTION_MASK) >> MIPI_DSI_PHY_STATUS_PHY_DIRECTION_SHIFT) + +/* + * PHY_LOCK (R) + * + * This bit indicates the status of phylock D-PHY signal + */ +#define MIPI_DSI_PHY_STATUS_PHY_LOCK_MASK (0x1U) +#define MIPI_DSI_PHY_STATUS_PHY_LOCK_SHIFT (0U) +#define MIPI_DSI_PHY_STATUS_PHY_LOCK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_LOCK_MASK) >> MIPI_DSI_PHY_STATUS_PHY_LOCK_SHIFT) + +/* Bitfield definition for register: PHY_TST_CTRL0 */ +/* + * PHY_TESTCLK (RW) + * + * reserve + */ +#define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_MASK (0x2U) +#define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_SHIFT (1U) +#define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_SHIFT) & MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_MASK) +#define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_MASK) >> MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_SHIFT) + +/* + * PHY_TESTCLR (RW) + * + * reserve + */ +#define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_MASK (0x1U) +#define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_SHIFT (0U) +#define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_SHIFT) & MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_MASK) +#define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_MASK) >> MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_SHIFT) + +/* Bitfield definition for register: PHY_TST_CTRL1 */ +/* + * PHY_TESTEN (RW) + * + * reserve + */ +#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_MASK (0x10000UL) +#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_SHIFT (16U) +#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_SHIFT) & MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_MASK) +#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_MASK) >> MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_SHIFT) + +/* + * PHY_TESTDOUT (R) + * + * reserve + */ +#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDOUT_MASK (0xFF00U) +#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDOUT_SHIFT (8U) +#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDOUT_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDOUT_MASK) >> MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDOUT_SHIFT) + +/* + * PHY_TESTDIN (RW) + * + * reserve + */ +#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_MASK (0xFFU) +#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_SHIFT (0U) +#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_SHIFT) & MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_MASK) +#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_MASK) >> MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_SHIFT) + +/* Bitfield definition for register: INT_ST0 */ +/* + * DPHY_ERRORS_4 (R) + * + * indicates LP1 contention error ErrContentionLP1 from lane0 + */ +#define MIPI_DSI_INT_ST0_DPHY_ERRORS_4_MASK (0x100000UL) +#define MIPI_DSI_INT_ST0_DPHY_ERRORS_4_SHIFT (20U) +#define MIPI_DSI_INT_ST0_DPHY_ERRORS_4_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_DPHY_ERRORS_4_MASK) >> MIPI_DSI_INT_ST0_DPHY_ERRORS_4_SHIFT) + +/* + * DPHY_ERRORS_3 (R) + * + * indicates LP0 contention error ErrContentionLP0 from lane0 + */ +#define MIPI_DSI_INT_ST0_DPHY_ERRORS_3_MASK (0x80000UL) +#define MIPI_DSI_INT_ST0_DPHY_ERRORS_3_SHIFT (19U) +#define MIPI_DSI_INT_ST0_DPHY_ERRORS_3_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_DPHY_ERRORS_3_MASK) >> MIPI_DSI_INT_ST0_DPHY_ERRORS_3_SHIFT) + +/* + * DPHY_ERRORS_2 (R) + * + * indicates control error ErrControl from lane0 + */ +#define MIPI_DSI_INT_ST0_DPHY_ERRORS_2_MASK (0x40000UL) +#define MIPI_DSI_INT_ST0_DPHY_ERRORS_2_SHIFT (18U) +#define MIPI_DSI_INT_ST0_DPHY_ERRORS_2_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_DPHY_ERRORS_2_MASK) >> MIPI_DSI_INT_ST0_DPHY_ERRORS_2_SHIFT) + +/* + * DPHY_ERRORS_1 (R) + * + * indicates ErrSyncEsc low-power data transmission synchronization error from lane 0 + */ +#define MIPI_DSI_INT_ST0_DPHY_ERRORS_1_MASK (0x20000UL) +#define MIPI_DSI_INT_ST0_DPHY_ERRORS_1_SHIFT (17U) +#define MIPI_DSI_INT_ST0_DPHY_ERRORS_1_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_DPHY_ERRORS_1_MASK) >> MIPI_DSI_INT_ST0_DPHY_ERRORS_1_SHIFT) + +/* + * DPHY_ERRORS_0 (R) + * + * indicates ErrEsc escape entry error from lane0 + */ +#define MIPI_DSI_INT_ST0_DPHY_ERRORS_0_MASK (0x10000UL) +#define MIPI_DSI_INT_ST0_DPHY_ERRORS_0_SHIFT (16U) +#define MIPI_DSI_INT_ST0_DPHY_ERRORS_0_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_DPHY_ERRORS_0_MASK) >> MIPI_DSI_INT_ST0_DPHY_ERRORS_0_SHIFT) + +/* + * ACK_WITH_ERR_15 (R) + * + * retrives the DSI protocal violation from the acknowledge error report + */ +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_15_MASK (0x8000U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_15_SHIFT (15U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_15_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_15_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_15_SHIFT) + +/* + * ACK_WITH_ERR_14 (R) + * + * retrives the reserved from the acknowledge error report + */ +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_14_MASK (0x4000U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_14_SHIFT (14U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_14_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_14_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_14_SHIFT) + +/* + * ACK_WITH_ERR_13 (R) + * + * retrives the invalid transmission length from the acknowledge error report + */ +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_13_MASK (0x2000U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_13_SHIFT (13U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_13_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_13_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_13_SHIFT) + +/* + * ACK_WITH_ERR_12 (R) + * + * retrieves the dsi vc id invalid from the acknowledge error report + */ +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_12_MASK (0x1000U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_12_SHIFT (12U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_12_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_12_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_12_SHIFT) + +/* + * ACK_WITH_ERR_11 (R) + * + * retrives the not recongnized dsi data type from the acknowledge error report + */ +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_11_MASK (0x800U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_11_SHIFT (11U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_11_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_11_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_11_SHIFT) + +/* + * ACK_WITH_ERR_10 (R) + * + * retrives the checksum error from the acknowledge error report + */ +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_10_MASK (0x400U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_10_SHIFT (10U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_10_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_10_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_10_SHIFT) + +/* + * ACK_WITH_ERR_9 (R) + * + * retrives the ECC error multi-bit from the acknowledge error report + */ +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_9_MASK (0x200U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_9_SHIFT (9U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_9_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_9_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_9_SHIFT) + +/* + * ACK_WITH_ERR8 (R) + * + * retrives the ecc error sigle-bit from the acknowledge error report + */ +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR8_MASK (0x100U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR8_SHIFT (8U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR8_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR8_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR8_SHIFT) + +/* + * ACK_WITH_ERR7 (R) + * + * retrieves the reserved from the acknowledge error report + */ +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR7_MASK (0x80U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR7_SHIFT (7U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR7_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR7_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR7_SHIFT) + +/* + * ACK_WITH_ERR6 (R) + * + * retrieves the false control error fro the acknowledge error report + */ +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR6_MASK (0x40U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR6_SHIFT (6U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR6_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR6_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR6_SHIFT) + +/* + * ACK_WITH_ERR5 (R) + * + * retrives the peripheral timeout error from the acknowledge error report + */ +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR5_MASK (0x20U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR5_SHIFT (5U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR5_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR5_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR5_SHIFT) + +/* + * ACK_WITH_ERR4 (R) + * + * retrives the LP transmit sync error from the acknowledge error report + */ +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR4_MASK (0x10U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR4_SHIFT (4U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR4_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR4_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR4_SHIFT) + +/* + * ACK_WITH_ERR3 (R) + * + * retrives the Escap mode entry command error from the acknowledge error report + */ +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR3_MASK (0x8U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR3_SHIFT (3U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR3_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR3_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR3_SHIFT) + +/* + * ACK_WITH_ERR2 (R) + * + * retrives the EoT sync error from the acknowledge error report + */ +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR2_MASK (0x4U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR2_SHIFT (2U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR2_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR2_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR2_SHIFT) + +/* + * ACK_WITH_ERR1 (R) + * + * retrives the SoT sync error from the acknowledge error report + */ +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR1_MASK (0x2U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR1_SHIFT (1U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR1_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR1_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR1_SHIFT) + +/* + * ACK_WITH_ERR0 (R) + * + * retrives the SoT serror from the acknowledge error report + */ +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR0_MASK (0x1U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR0_SHIFT (0U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR0_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR0_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR0_SHIFT) + +/* Bitfield definition for register: INT_ST1 */ +/* + * TEAR_REQUEST_ERR (R) + * + * indicates tear_request has occurred but tear effect is not active in dsi host and device + */ +#define MIPI_DSI_INT_ST1_TEAR_REQUEST_ERR_MASK (0x100000UL) +#define MIPI_DSI_INT_ST1_TEAR_REQUEST_ERR_SHIFT (20U) +#define MIPI_DSI_INT_ST1_TEAR_REQUEST_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_TEAR_REQUEST_ERR_MASK) >> MIPI_DSI_INT_ST1_TEAR_REQUEST_ERR_SHIFT) + +/* + * DPI_BUFF_PLD_UNDER (R) + * + * indicates an underflow when reading payload to build dsi packet for video mode + */ +#define MIPI_DSI_INT_ST1_DPI_BUFF_PLD_UNDER_MASK (0x80000UL) +#define MIPI_DSI_INT_ST1_DPI_BUFF_PLD_UNDER_SHIFT (19U) +#define MIPI_DSI_INT_ST1_DPI_BUFF_PLD_UNDER_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_DPI_BUFF_PLD_UNDER_MASK) >> MIPI_DSI_INT_ST1_DPI_BUFF_PLD_UNDER_SHIFT) + +/* + * GEN_PLD_RECEV_ERR (R) + * + * indicates that during a generic interface packet read back, the payload FIFO full + */ +#define MIPI_DSI_INT_ST1_GEN_PLD_RECEV_ERR_MASK (0x1000U) +#define MIPI_DSI_INT_ST1_GEN_PLD_RECEV_ERR_SHIFT (12U) +#define MIPI_DSI_INT_ST1_GEN_PLD_RECEV_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_GEN_PLD_RECEV_ERR_MASK) >> MIPI_DSI_INT_ST1_GEN_PLD_RECEV_ERR_SHIFT) + +/* + * GEN_PLD_RD_ERR (R) + * + * indicates that during a DCS read data, the payload FIFO becomes empty + */ +#define MIPI_DSI_INT_ST1_GEN_PLD_RD_ERR_MASK (0x800U) +#define MIPI_DSI_INT_ST1_GEN_PLD_RD_ERR_SHIFT (11U) +#define MIPI_DSI_INT_ST1_GEN_PLD_RD_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_GEN_PLD_RD_ERR_MASK) >> MIPI_DSI_INT_ST1_GEN_PLD_RD_ERR_SHIFT) + +/* + * GEN_PLD_SEND_ERR (R) + * + * indicates the payload FIFO become empty when packet build + */ +#define MIPI_DSI_INT_ST1_GEN_PLD_SEND_ERR_MASK (0x400U) +#define MIPI_DSI_INT_ST1_GEN_PLD_SEND_ERR_SHIFT (10U) +#define MIPI_DSI_INT_ST1_GEN_PLD_SEND_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_GEN_PLD_SEND_ERR_MASK) >> MIPI_DSI_INT_ST1_GEN_PLD_SEND_ERR_SHIFT) + +/* + * GEN_PLD_WR_ERR (R) + * + * indicates the system tried to write a payload and FIFO is full + */ +#define MIPI_DSI_INT_ST1_GEN_PLD_WR_ERR_MASK (0x200U) +#define MIPI_DSI_INT_ST1_GEN_PLD_WR_ERR_SHIFT (9U) +#define MIPI_DSI_INT_ST1_GEN_PLD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_GEN_PLD_WR_ERR_MASK) >> MIPI_DSI_INT_ST1_GEN_PLD_WR_ERR_SHIFT) + +/* + * GEN_CMD_WR_ERR (R) + * + * indicates the system tried to write a command and FIFO is full + */ +#define MIPI_DSI_INT_ST1_GEN_CMD_WR_ERR_MASK (0x100U) +#define MIPI_DSI_INT_ST1_GEN_CMD_WR_ERR_SHIFT (8U) +#define MIPI_DSI_INT_ST1_GEN_CMD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_GEN_CMD_WR_ERR_MASK) >> MIPI_DSI_INT_ST1_GEN_CMD_WR_ERR_SHIFT) + +/* + * DPI_BPLD_WR_ERR (R) + * + * indicates the payload FIFO is full during a DPI pixel line storage + */ +#define MIPI_DSI_INT_ST1_DPI_BPLD_WR_ERR_MASK (0x80U) +#define MIPI_DSI_INT_ST1_DPI_BPLD_WR_ERR_SHIFT (7U) +#define MIPI_DSI_INT_ST1_DPI_BPLD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_DPI_BPLD_WR_ERR_MASK) >> MIPI_DSI_INT_ST1_DPI_BPLD_WR_ERR_SHIFT) + +/* + * EOPT_ERR (R) + * + * indicates that the EoTp packet has not been received at the end of the incoming peripheral transmission + */ +#define MIPI_DSI_INT_ST1_EOPT_ERR_MASK (0x40U) +#define MIPI_DSI_INT_ST1_EOPT_ERR_SHIFT (6U) +#define MIPI_DSI_INT_ST1_EOPT_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_EOPT_ERR_MASK) >> MIPI_DSI_INT_ST1_EOPT_ERR_SHIFT) + +/* + * PKT_SIZE_ERR (R) + * + * indicates that the packet size error has been detected during the packet reception + */ +#define MIPI_DSI_INT_ST1_PKT_SIZE_ERR_MASK (0x20U) +#define MIPI_DSI_INT_ST1_PKT_SIZE_ERR_SHIFT (5U) +#define MIPI_DSI_INT_ST1_PKT_SIZE_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_PKT_SIZE_ERR_MASK) >> MIPI_DSI_INT_ST1_PKT_SIZE_ERR_SHIFT) + +/* + * CRC_ERR (R) + * + * indicates that the CRC error has been detected in the reveived packet payload + */ +#define MIPI_DSI_INT_ST1_CRC_ERR_MASK (0x10U) +#define MIPI_DSI_INT_ST1_CRC_ERR_SHIFT (4U) +#define MIPI_DSI_INT_ST1_CRC_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_CRC_ERR_MASK) >> MIPI_DSI_INT_ST1_CRC_ERR_SHIFT) + +/* + * ECC_MULTI_ERR (R) + * + * indicates that the ECC multiple error has been detected in a revieved packet + */ +#define MIPI_DSI_INT_ST1_ECC_MULTI_ERR_MASK (0x8U) +#define MIPI_DSI_INT_ST1_ECC_MULTI_ERR_SHIFT (3U) +#define MIPI_DSI_INT_ST1_ECC_MULTI_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_ECC_MULTI_ERR_MASK) >> MIPI_DSI_INT_ST1_ECC_MULTI_ERR_SHIFT) + +/* + * ECC_SIGLE_ERR (R) + * + * indicates that the ECC single error has been detected and corrected in a reveived packet + */ +#define MIPI_DSI_INT_ST1_ECC_SIGLE_ERR_MASK (0x4U) +#define MIPI_DSI_INT_ST1_ECC_SIGLE_ERR_SHIFT (2U) +#define MIPI_DSI_INT_ST1_ECC_SIGLE_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_ECC_SIGLE_ERR_MASK) >> MIPI_DSI_INT_ST1_ECC_SIGLE_ERR_SHIFT) + +/* + * TO_LP_TX (R) + * + * indicates that the low-power reception timeout counter reached the end and contention has been detected + */ +#define MIPI_DSI_INT_ST1_TO_LP_TX_MASK (0x2U) +#define MIPI_DSI_INT_ST1_TO_LP_TX_SHIFT (1U) +#define MIPI_DSI_INT_ST1_TO_LP_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_TO_LP_TX_MASK) >> MIPI_DSI_INT_ST1_TO_LP_TX_SHIFT) + +/* + * TO_HS_TX (R) + * + * indicates that the high-speed transmission timeout counter reached the end and contention has been detected + */ +#define MIPI_DSI_INT_ST1_TO_HS_TX_MASK (0x1U) +#define MIPI_DSI_INT_ST1_TO_HS_TX_SHIFT (0U) +#define MIPI_DSI_INT_ST1_TO_HS_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_TO_HS_TX_MASK) >> MIPI_DSI_INT_ST1_TO_HS_TX_SHIFT) + +/* Bitfield definition for register: INT_MSK0 */ +/* + * MASK_DPHY_ERRORS_4 (RW) + * + * disable LP1 contention error ErrContentionLP1 from lane0 + */ +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_MASK (0x100000UL) +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_SHIFT (20U) +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_SHIFT) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_MASK) +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_MASK) >> MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_SHIFT) + +/* + * MASK_DPHY_ERRORS_3 (RW) + * + * disable LP0 contention error ErrContentionLP0 from lane0 + */ +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_MASK (0x80000UL) +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_SHIFT (19U) +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_SHIFT) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_MASK) +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_MASK) >> MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_SHIFT) + +/* + * MASK_DPHY_ERRORS_2 (RW) + * + * disable control error ErrControl from lane0 + */ +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_MASK (0x40000UL) +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_SHIFT (18U) +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_SHIFT) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_MASK) +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_MASK) >> MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_SHIFT) + +/* + * MASK_DPHY_ERRORS_1 (RW) + * + * disable ErrSyncEsc low-power data transmission synchronization error from lane 0 + */ +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_MASK (0x20000UL) +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_SHIFT (17U) +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_SHIFT) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_MASK) +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_MASK) >> MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_SHIFT) + +/* + * MASK_DPHY_ERRORS_0 (RW) + * + * disable ErrEsc escape entry error from lane0 + */ +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_MASK (0x10000UL) +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_SHIFT (16U) +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_SHIFT) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_MASK) +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_MASK) >> MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_SHIFT) + +/* + * MASK_ACK_WITH_ERR_15 (RW) + * + * disable the DSI protocal violation from the acknowledge error report + */ +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_MASK (0x8000U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_SHIFT (15U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_MASK) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_SHIFT) + +/* + * MASK_ACK_WITH_ERR_14 (RW) + * + * disable the reserved from the acknowledge error report + */ +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_MASK (0x4000U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_SHIFT (14U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_MASK) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_SHIFT) + +/* + * MASK_ACK_WITH_ERR_13 (RW) + * + * disable the invalid transmission length from the acknowledge error report + */ +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_MASK (0x2000U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_SHIFT (13U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_MASK) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_SHIFT) + +/* + * MASK_ACK_WITH_ERR_12 (RW) + * + * disable the dsi vc id invalid from the acknowledge error report + */ +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_MASK (0x1000U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_SHIFT (12U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_MASK) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_SHIFT) + +/* + * MASK_ACK_WITH_ERR_11 (RW) + * + * disable the not recongnized dsi data type from the acknowledge error report + */ +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_MASK (0x800U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_SHIFT (11U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_MASK) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_SHIFT) + +/* + * MASK_ACK_WITH_ERR_10 (RW) + * + * disable the checksum error from the acknowledge error report + */ +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_MASK (0x400U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_SHIFT (10U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_MASK) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_SHIFT) + +/* + * MASK_ACK_WITH_ERR_9 (RW) + * + * disable the ECC error multi-bit from the acknowledge error report + */ +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_MASK (0x200U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_SHIFT (9U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_MASK) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_SHIFT) + +/* + * MASK_ACK_WITH_ERR8 (RW) + * + * disable the ecc error sigle-bit from the acknowledge error report + */ +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_MASK (0x100U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_SHIFT (8U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_MASK) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_SHIFT) + +/* + * MASK_ACK_WITH_ERR7 (RW) + * + * disable the reserved from the acknowledge error report + */ +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_MASK (0x80U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_SHIFT (7U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_MASK) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_SHIFT) + +/* + * MASK_ACK_WITH_ERR6 (RW) + * + * disable the false control error fro the acknowledge error report + */ +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_MASK (0x40U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_SHIFT (6U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_MASK) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_SHIFT) + +/* + * MASK_ACK_WITH_ERR5 (RW) + * + * disable the peripheral timeout error from the acknowledge error report + */ +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_MASK (0x20U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_SHIFT (5U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_MASK) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_SHIFT) + +/* + * MASK_ACK_WITH_ERR4 (RW) + * + * disable the LP transmit sync error from the acknowledge error report + */ +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_MASK (0x10U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_SHIFT (4U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_MASK) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_SHIFT) + +/* + * MASK_ACK_WITH_ERR3 (RW) + * + * disable the Escap mode entry command error from the acknowledge error report + */ +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_MASK (0x8U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_SHIFT (3U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_MASK) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_SHIFT) + +/* + * MASK_ACK_WITH_ERR2 (RW) + * + * disable the EoT sync error from the acknowledge error report + */ +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_MASK (0x4U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_SHIFT (2U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_MASK) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_SHIFT) + +/* + * MASK_ACK_WITH_ERR1 (RW) + * + * disable the SoT sync error from the acknowledge error report + */ +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_MASK (0x2U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_SHIFT (1U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_MASK) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_SHIFT) + +/* + * MASK_ACK_WITH_ERR0 (RW) + * + * disable the SoT serror from the acknowledge error report + */ +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_MASK (0x1U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_SHIFT (0U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_MASK) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_SHIFT) + +/* Bitfield definition for register: INT_MSK1 */ +/* + * MASK_TEAR_REQUEST_ERR (RW) + * + * disable tear_request has occurred but tear effect is not active in dsi host and device + */ +#define MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_MASK (0x100000UL) +#define MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_SHIFT (20U) +#define MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_MASK) +#define MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_SHIFT) + +/* + * MASK_DPI_BUFF_PLD_UNDER (RW) + * + * disable an underflow when reading payload to build dsi packet for video mode + */ +#define MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_MASK (0x80000UL) +#define MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_SHIFT (19U) +#define MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_SHIFT) & MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_MASK) +#define MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_MASK) >> MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_SHIFT) + +/* + * MASK_GEN_PLD_RECEV_ERR (RW) + * + * disable that during a generic interface packet read back, the payload FIFO full + */ +#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_MASK (0x1000U) +#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_SHIFT (12U) +#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_MASK) +#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_SHIFT) + +/* + * MASK_GEN_PLD_RD_ERR (RW) + * + * disable that during a DCS read data, the payload FIFO becomes empty + */ +#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_MASK (0x800U) +#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_SHIFT (11U) +#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_MASK) +#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_SHIFT) + +/* + * MASK_GEN_PLD_SEND_ERR (RW) + * + * disable the payload FIFO become empty when packet build + */ +#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_MASK (0x400U) +#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_SHIFT (10U) +#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_MASK) +#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_SHIFT) + +/* + * MASK_GEN_PLD_WR_ERR (RW) + * + * disable the system tried to write a payload and FIFO is full + */ +#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_MASK (0x200U) +#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_SHIFT (9U) +#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_MASK) +#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_SHIFT) + +/* + * MASK_GEN_CMD_WR_ERR (RW) + * + * disable the system tried to write a command and FIFO is full + */ +#define MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_MASK (0x100U) +#define MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_SHIFT (8U) +#define MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_MASK) +#define MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_SHIFT) + +/* + * MASK_DPI_BPLD_WR_ERR (RW) + * + * disable the payload FIFO is full during a DPI pixel line storage + */ +#define MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_MASK (0x80U) +#define MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_SHIFT (7U) +#define MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_MASK) +#define MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_SHIFT) + +/* + * MASK_EOPT_ERR (RW) + * + * disable that the EoTp packet has not been received at the end of the incoming peripheral transmission + */ +#define MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_MASK (0x40U) +#define MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_SHIFT (6U) +#define MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_MASK) +#define MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_SHIFT) + +/* + * MASK_PKT_SIZE_ERR (RW) + * + * disable that the packet size error has been detected during the packet reception + */ +#define MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_MASK (0x20U) +#define MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_SHIFT (5U) +#define MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_MASK) +#define MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_SHIFT) + +/* + * MASK_CRC_ERR (RW) + * + * disable that the CRC error has been detected in the reveived packet payload + */ +#define MIPI_DSI_INT_MSK1_MASK_CRC_ERR_MASK (0x10U) +#define MIPI_DSI_INT_MSK1_MASK_CRC_ERR_SHIFT (4U) +#define MIPI_DSI_INT_MSK1_MASK_CRC_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_CRC_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_CRC_ERR_MASK) +#define MIPI_DSI_INT_MSK1_MASK_CRC_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_CRC_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_CRC_ERR_SHIFT) + +/* + * MASK_ECC_MULTI_ERR (RW) + * + * disable that the ECC multiple error has been detected in a revieved packet + */ +#define MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_MASK (0x8U) +#define MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_SHIFT (3U) +#define MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_MASK) +#define MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_SHIFT) + +/* + * MASK_ECC_SIGLE_ERR (RW) + * + * disable that the ECC single error has been detected and corrected in a reveived packet + */ +#define MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_MASK (0x4U) +#define MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_SHIFT (2U) +#define MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_MASK) +#define MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_SHIFT) + +/* + * MASK_TO_LP_TX (RW) + * + * disable that the low-power reception timeout counter reached the end and contention has been detected + */ +#define MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_MASK (0x2U) +#define MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_SHIFT (1U) +#define MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_SHIFT) & MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_MASK) +#define MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_MASK) >> MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_SHIFT) + +/* + * MASK_TO_HS_TX (RW) + * + * disable that the high-speed transmission timeout counter reached the end and contention has been detected + */ +#define MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_MASK (0x1U) +#define MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_SHIFT (0U) +#define MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_SHIFT) & MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_MASK) +#define MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_MASK) >> MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_SHIFT) + +/* Bitfield definition for register: PHY_CAL */ +/* + * TXSKEWCALHS (RW) + * + * High-speed skew calibration is started when txskewcalhs is + * set high (assuming that PHY is in Stop state) + */ +#define MIPI_DSI_PHY_CAL_TXSKEWCALHS_MASK (0x1U) +#define MIPI_DSI_PHY_CAL_TXSKEWCALHS_SHIFT (0U) +#define MIPI_DSI_PHY_CAL_TXSKEWCALHS_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CAL_TXSKEWCALHS_SHIFT) & MIPI_DSI_PHY_CAL_TXSKEWCALHS_MASK) +#define MIPI_DSI_PHY_CAL_TXSKEWCALHS_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CAL_TXSKEWCALHS_MASK) >> MIPI_DSI_PHY_CAL_TXSKEWCALHS_SHIFT) + +/* Bitfield definition for register: INT_FORCE0 */ +/* + * FORCE_DPHY_ERRORS_4 (RW) + * + * force LP1 contention error ErrContentionLP1 from lane0 + */ +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_MASK (0x100000UL) +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_SHIFT (20U) +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_SHIFT) + +/* + * FORCE_DPHY_ERRORS_3 (RW) + * + * force LP0 contention error ErrContentionLP0 from lane0 + */ +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_MASK (0x80000UL) +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_SHIFT (19U) +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_SHIFT) + +/* + * FORCE_DPHY_ERRORS_2 (RW) + * + * force control error ErrControl from lane0 + */ +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_MASK (0x40000UL) +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_SHIFT (18U) +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_SHIFT) + +/* + * FORCE_DPHY_ERRORS_1 (RW) + * + * force ErrSyncEsc low-power data transmission synchronization error from lane 0 + */ +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_MASK (0x20000UL) +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_SHIFT (17U) +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_SHIFT) + +/* + * FORCE_DPHY_ERRORS_0 (RW) + * + * force ErrEsc escape entry error from lane0 + */ +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_MASK (0x10000UL) +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_SHIFT (16U) +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_SHIFT) + +/* + * FORCE_ACK_WITH_ERR_15 (RW) + * + * force the DSI protocal violation from the acknowledge error report + */ +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_MASK (0x8000U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_SHIFT (15U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_SHIFT) + +/* + * FORCE_ACK_WITH_ERR_14 (RW) + * + * force the reserved from the acknowledge error report + */ +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_MASK (0x4000U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_SHIFT (14U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_SHIFT) + +/* + * FORCE_ACK_WITH_ERR_13 (RW) + * + * force the invalid transmission length from the acknowledge error report + */ +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_MASK (0x2000U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_SHIFT (13U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_SHIFT) + +/* + * FORCE_ACK_WITH_ERR_12 (RW) + * + * force the dsi vc id invalid from the acknowledge error report + */ +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_MASK (0x1000U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_SHIFT (12U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_SHIFT) + +/* + * FORCE_ACK_WITH_ERR_11 (RW) + * + * force the not recongnized dsi data type from the acknowledge error report + */ +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_MASK (0x800U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_SHIFT (11U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_SHIFT) + +/* + * FORCE_ACK_WITH_ERR_10 (RW) + * + * force the checksum error from the acknowledge error report + */ +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_MASK (0x400U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_SHIFT (10U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_SHIFT) + +/* + * FORCE_ACK_WITH_ERR_9 (RW) + * + * force the ECC error multi-bit from the acknowledge error report + */ +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_MASK (0x200U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_SHIFT (9U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_SHIFT) + +/* + * FORCE_ACK_WITH_ERR8 (RW) + * + * force the ecc error sigle-bit from the acknowledge error report + */ +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_MASK (0x100U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_SHIFT (8U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_SHIFT) + +/* + * FORCE_ACK_WITH_ERR7 (RW) + * + * force the reserved from the acknowledge error report + */ +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_MASK (0x80U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_SHIFT (7U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_SHIFT) + +/* + * FORCE_ACK_WITH_ERR6 (RW) + * + * force the false control error fro the acknowledge error report + */ +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_MASK (0x40U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_SHIFT (6U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_SHIFT) + +/* + * FORCE_ACK_WITH_ERR5 (RW) + * + * force the peripheral timeout error from the acknowledge error report + */ +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_MASK (0x20U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_SHIFT (5U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_SHIFT) + +/* + * FORCE_ACK_WITH_ERR4 (RW) + * + * force the LP transmit sync error from the acknowledge error report + */ +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_MASK (0x10U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_SHIFT (4U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_SHIFT) + +/* + * FORCE_ACK_WITH_ERR3 (RW) + * + * force the Escap mode entry command error from the acknowledge error report + */ +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_MASK (0x8U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_SHIFT (3U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_SHIFT) + +/* + * FORCE_ACK_WITH_ERR2 (RW) + * + * force the EoT sync error from the acknowledge error report + */ +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_MASK (0x4U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_SHIFT (2U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_SHIFT) + +/* + * FORCE_ACK_WITH_ERR1 (RW) + * + * force the SoT sync error from the acknowledge error report + */ +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_MASK (0x2U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_SHIFT (1U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_SHIFT) + +/* + * FORCE_ACK_WITH_ERR0 (RW) + * + * force the SoT serror from the acknowledge error report + */ +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_MASK (0x1U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_SHIFT (0U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_SHIFT) + +/* Bitfield definition for register: INT_FORCE1 */ +/* + * FORCE_TEAR_REQUEST_ERR (RW) + * + * force tear_request has occurred but tear effect is not active in dsi host and device + */ +#define MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_MASK (0x100000UL) +#define MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_SHIFT (20U) +#define MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_MASK) +#define MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_SHIFT) + +/* + * FORCE_DPI_BUFF_PLD_UNDER (RW) + * + * force an underflow when reading payload to build dsi packet for video mode + */ +#define MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_MASK (0x80000UL) +#define MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_SHIFT (19U) +#define MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_MASK) +#define MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_SHIFT) + +/* + * FORCE_GEN_PLD_RECEV_ERR (RW) + * + * force that during a generic interface packet read back, the payload FIFO full + */ +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_MASK (0x1000U) +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_SHIFT (12U) +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_MASK) +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_SHIFT) + +/* + * FORCE_GEN_PLD_RD_ERR (RW) + * + * force that during a DCS read data, the payload FIFO becomes empty + */ +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_MASK (0x800U) +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_SHIFT (11U) +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_MASK) +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_SHIFT) + +/* + * FORCE_GEN_PLD_SEND_ERR (RW) + * + * force the payload FIFO become empty when packet build + */ +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_MASK (0x400U) +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_SHIFT (10U) +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_MASK) +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_SHIFT) + +/* + * FORCE_GEN_PLD_WR_ERR (RW) + * + * force the system tried to write a payload and FIFO is full + */ +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_MASK (0x200U) +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_SHIFT (9U) +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_MASK) +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_SHIFT) + +/* + * FORCE_GEN_CMD_WR_ERR (RW) + * + * force the system tried to write a command and FIFO is full + */ +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_MASK (0x100U) +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_SHIFT (8U) +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_MASK) +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_SHIFT) + +/* + * FORCE_DPI_BPLD_WR_ERR (RW) + * + * force the payload FIFO is full during a DPI pixel line storage + */ +#define MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_MASK (0x80U) +#define MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_SHIFT (7U) +#define MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_MASK) +#define MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_SHIFT) + +/* + * FORCE_EOPT_ERR (RW) + * + * force that the EoTp packet has not been received at the end of the incoming peripheral transmission + */ +#define MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_MASK (0x40U) +#define MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_SHIFT (6U) +#define MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_MASK) +#define MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_SHIFT) + +/* + * FORCE_PKT_SIZE_ERR (RW) + * + * force that the packet size error has been detected during the packet reception + */ +#define MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_MASK (0x20U) +#define MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_SHIFT (5U) +#define MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_MASK) +#define MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_SHIFT) + +/* + * FORCE_CRC_ERR (RW) + * + * force that the CRC error has been detected in the reveived packet payload + */ +#define MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_MASK (0x10U) +#define MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_SHIFT (4U) +#define MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_MASK) +#define MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_SHIFT) + +/* + * FORCE_ECC_MULTI_ERR (RW) + * + * force that the ECC multiple error has been detected in a revieved packet + */ +#define MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_MASK (0x8U) +#define MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_SHIFT (3U) +#define MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_MASK) +#define MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_SHIFT) + +/* + * FORCE_ECC_SIGLE_ERR (RW) + * + * force that the ECC single error has been detected and corrected in a reveived packet + */ +#define MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_MASK (0x4U) +#define MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_SHIFT (2U) +#define MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_MASK) +#define MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_SHIFT) + +/* + * FORCE_TO_LP_TX (RW) + * + * force that the low-power reception timeout counter reached the end and contention has been detected + */ +#define MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_MASK (0x2U) +#define MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_SHIFT (1U) +#define MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_MASK) +#define MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_SHIFT) + +/* + * FORCE_TO_HS_TX (RW) + * + * force that the high-speed transmission timeout counter reached the end and contention has been detected + */ +#define MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_MASK (0x1U) +#define MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_SHIFT (0U) +#define MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_MASK) +#define MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_SHIFT) + +/* Bitfield definition for register: PHY_TMR_RD */ +/* + * MAX_RD_TIME (RW) + * + * the maximum time required to perform a read command in lane byte clock cycles. + */ +#define MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_MASK (0x7FFFU) +#define MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_SHIFT (0U) +#define MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_SHIFT) & MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_MASK) +#define MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_MASK) >> MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_SHIFT) + +/* Bitfield definition for register: AUTO_ULPS_MIN_TIME */ +/* + * ULPS_MIN_TIME (RW) + * + * configures the minimum time required by phy between ulpsactivenot and ulpsexitreq for clock and data lane + */ +#define MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_MASK (0xFFFU) +#define MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_SHIFT (0U) +#define MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_SHIFT) & MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_MASK) +#define MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_MASK) >> MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_SHIFT) + +/* Bitfield definition for register: PHY_MODE */ +/* + * PHY_MODE (RW) + * + * sel DPHY or CPHY + */ +#define MIPI_DSI_PHY_MODE_PHY_MODE_MASK (0x1U) +#define MIPI_DSI_PHY_MODE_PHY_MODE_SHIFT (0U) +#define MIPI_DSI_PHY_MODE_PHY_MODE_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_MODE_PHY_MODE_SHIFT) & MIPI_DSI_PHY_MODE_PHY_MODE_MASK) +#define MIPI_DSI_PHY_MODE_PHY_MODE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_MODE_PHY_MODE_MASK) >> MIPI_DSI_PHY_MODE_PHY_MODE_SHIFT) + +/* Bitfield definition for register: VID_SHADOW_CTRL */ +/* + * VID_SHADOW_PIN_REQ (RW) + * + * when set to 1, the video request is done by external pin + */ +#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_MASK (0x10000UL) +#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_SHIFT (16U) +#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_SHIFT) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_MASK) +#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_MASK) >> MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_SHIFT) + +/* + * VID_SHADOW_REQ (RW) + * + * when set to 1, request that the dpi register from regbank are copied to the auxiliary registers + */ +#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_MASK (0x100U) +#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_SHIFT (8U) +#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_SHIFT) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_MASK) +#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_MASK) >> MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_SHIFT) + +/* + * VID_SHADOW_EN (RW) + * + * when set to 1, DPI receives the active configuration from the auxiliary register + */ +#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_MASK (0x1U) +#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_SHIFT (0U) +#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_SHIFT) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_MASK) +#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_MASK) >> MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_SHIFT) + +/* Bitfield definition for register: DPI_VCID_ACT */ +/* + * DPI_VCID (R) + * + * specifies the DPI virtual channel id that is indexed to the video mode packets + */ +#define MIPI_DSI_DPI_VCID_ACT_DPI_VCID_MASK (0x3U) +#define MIPI_DSI_DPI_VCID_ACT_DPI_VCID_SHIFT (0U) +#define MIPI_DSI_DPI_VCID_ACT_DPI_VCID_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_VCID_ACT_DPI_VCID_MASK) >> MIPI_DSI_DPI_VCID_ACT_DPI_VCID_SHIFT) + +/* Bitfield definition for register: DPI_COLOR_CODING_ACT */ +/* + * LOOSELY18_EN (R) + * + * avtivates loosely packed variant to 18-bit configuration + */ +#define MIPI_DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_MASK (0x100U) +#define MIPI_DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_SHIFT (8U) +#define MIPI_DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_MASK) >> MIPI_DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_SHIFT) + +/* + * DIP_COLOR_CODING (R) + * + * configures the DPI color for video mode + */ +#define MIPI_DSI_DPI_COLOR_CODING_ACT_DIP_COLOR_CODING_MASK (0xFU) +#define MIPI_DSI_DPI_COLOR_CODING_ACT_DIP_COLOR_CODING_SHIFT (0U) +#define MIPI_DSI_DPI_COLOR_CODING_ACT_DIP_COLOR_CODING_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_COLOR_CODING_ACT_DIP_COLOR_CODING_MASK) >> MIPI_DSI_DPI_COLOR_CODING_ACT_DIP_COLOR_CODING_SHIFT) + +/* Bitfield definition for register: DPI_LP_CMD_TIM_ACT */ +/* + * OUTVACT_LPCMD_TIME (R) + * + * transmission of commands in low-power mode, it specifies the size in bytes of the lagest packet that can fit in a line during the VSA VBP and VFP regions. + */ +#define MIPI_DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_MASK (0xFF0000UL) +#define MIPI_DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_SHIFT (16U) +#define MIPI_DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_MASK) >> MIPI_DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_SHIFT) + +/* + * INVACT_LPCMD_TIME (R) + * + * transmission of commands in low-power mode, it specifies the size in bytes of the lagest packet that can fit in a line during the vact regions. + */ +#define MIPI_DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_MASK (0xFFU) +#define MIPI_DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_SHIFT (0U) +#define MIPI_DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_MASK) >> MIPI_DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_SHIFT) + +/* Bitfield definition for register: VID_MODE_CFG_ACT */ +/* + * LP_CMD_EN (R) + * + * enable the command transmission only in low-power mode + */ +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_CMD_EN_MASK (0x200U) +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_CMD_EN_SHIFT (9U) +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_CMD_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_CMD_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_CMD_EN_SHIFT) + +/* + * FRAME_BTA_ACK_EN (R) + * + * enable the request for an acknowledge response at the end of a frame + */ +#define MIPI_DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_MASK (0x100U) +#define MIPI_DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_SHIFT (8U) +#define MIPI_DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_SHIFT) + +/* + * LP_HFP_EN (R) + * + * enable the returne to low-power inside the HFP period when timing allows + */ +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_HFP_EN_MASK (0x80U) +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_HFP_EN_SHIFT (7U) +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_HFP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_HFP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_HFP_EN_SHIFT) + +/* + * LP_HBP_EN (R) + * + * enable the returne to low-power inside the HBP period when timing allows + */ +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_HBP_EN_MASK (0x40U) +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_HBP_EN_SHIFT (6U) +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_HBP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_HBP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_HBP_EN_SHIFT) + +/* + * LP_VACT_EN (R) + * + * enable the returne to low-power inside the VACT period when timing allows + */ +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VACT_EN_MASK (0x20U) +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VACT_EN_SHIFT (5U) +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VACT_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_VACT_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_VACT_EN_SHIFT) + +/* + * LP_VFP_EN (R) + * + * enable the returne to low-power inside the VFP period when timing allows + */ +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VFP_EN_MASK (0x10U) +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VFP_EN_SHIFT (4U) +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VFP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_VFP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_VFP_EN_SHIFT) + +/* + * LP_VBP_EN (R) + * + * enable the returne to low-power inside the VBP period when timing allows + */ +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VBP_EN_MASK (0x8U) +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VBP_EN_SHIFT (3U) +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VBP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_VBP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_VBP_EN_SHIFT) + +/* + * LP_VSA_EN (R) + * + * enable the returne to low-power inside the VSA period when timing allows + */ +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VSA_EN_MASK (0x4U) +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VSA_EN_SHIFT (2U) +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VSA_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_VSA_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_VSA_EN_SHIFT) + +/* + * VID_MODE_TYPE (R) + * + * specifies the video mode transmission type + */ +#define MIPI_DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_MASK (0x3U) +#define MIPI_DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_SHIFT (0U) +#define MIPI_DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_SHIFT) + +/* Bitfield definition for register: VID_PKT_SIZE_ACT */ +/* + * VID_PKT_SIZE (R) + * + * the number of pixels in a single video packet + */ +#define MIPI_DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_MASK (0x3FFFU) +#define MIPI_DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_SHIFT (0U) +#define MIPI_DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_MASK) >> MIPI_DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_SHIFT) + +/* Bitfield definition for register: VID_NUM_CHUNKS_ACT */ +/* + * VID_NUM_CHUNKS (R) + * + * the number of chunks to be transmitted during a line period + */ +#define MIPI_DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_MASK (0x1FFFU) +#define MIPI_DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_SHIFT (0U) +#define MIPI_DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_MASK) >> MIPI_DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_SHIFT) + +/* Bitfield definition for register: VID_NULL_SIZE_ACT */ +/* + * VID_NULL_SIZE (R) + * + * the number of bytes in side a null packet + */ +#define MIPI_DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_MASK (0x1FFFU) +#define MIPI_DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_SHIFT (0U) +#define MIPI_DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_MASK) >> MIPI_DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_SHIFT) + +/* Bitfield definition for register: VID_HSA_TIME_ACT */ +/* + * VID_HSA_TIME (R) + * + * the horizontal synchronism active period in lane byte clock cycles + */ +#define MIPI_DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_MASK (0xFFFU) +#define MIPI_DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_SHIFT (0U) +#define MIPI_DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_MASK) >> MIPI_DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_SHIFT) + +/* Bitfield definition for register: VID_HBP_TIME_ACT */ +/* + * VID_HBP_TIME (R) + * + * the horizontal back porch period in lane byte clock cycles + */ +#define MIPI_DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_MASK (0xFFFU) +#define MIPI_DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_SHIFT (0U) +#define MIPI_DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_MASK) >> MIPI_DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_SHIFT) + +/* Bitfield definition for register: VID_HLINE_TIME_ACT */ +/* + * VID_HLINE_TIME (R) + * + * the size of total line: hsa+hbp+hact+hfp + */ +#define MIPI_DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_MASK (0x7FFFU) +#define MIPI_DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_SHIFT (0U) +#define MIPI_DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_MASK) >> MIPI_DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_SHIFT) + +/* Bitfield definition for register: VID_VSA_LINES_ACT */ +/* + * VSA_LINES (R) + * + * vertical synchronism active period + */ +#define MIPI_DSI_VID_VSA_LINES_ACT_VSA_LINES_MASK (0x3FFU) +#define MIPI_DSI_VID_VSA_LINES_ACT_VSA_LINES_SHIFT (0U) +#define MIPI_DSI_VID_VSA_LINES_ACT_VSA_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VSA_LINES_ACT_VSA_LINES_MASK) >> MIPI_DSI_VID_VSA_LINES_ACT_VSA_LINES_SHIFT) + +/* Bitfield definition for register: VID_VBP_LINES_ACT */ +/* + * VBP_LINES (R) + * + * vertical back porch period + */ +#define MIPI_DSI_VID_VBP_LINES_ACT_VBP_LINES_MASK (0x3FFU) +#define MIPI_DSI_VID_VBP_LINES_ACT_VBP_LINES_SHIFT (0U) +#define MIPI_DSI_VID_VBP_LINES_ACT_VBP_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VBP_LINES_ACT_VBP_LINES_MASK) >> MIPI_DSI_VID_VBP_LINES_ACT_VBP_LINES_SHIFT) + +/* Bitfield definition for register: VID_VFP_LINES_ACT */ +/* + * VFP_LINES (R) + * + * vertical porch period + */ +#define MIPI_DSI_VID_VFP_LINES_ACT_VFP_LINES_MASK (0x3FFU) +#define MIPI_DSI_VID_VFP_LINES_ACT_VFP_LINES_SHIFT (0U) +#define MIPI_DSI_VID_VFP_LINES_ACT_VFP_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VFP_LINES_ACT_VFP_LINES_MASK) >> MIPI_DSI_VID_VFP_LINES_ACT_VFP_LINES_SHIFT) + +/* Bitfield definition for register: VID_VACTIVE_LINES_ACT */ +/* + * V_ACTIVE_LINES (R) + * + * vertical active period + */ +#define MIPI_DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_MASK (0x3FFFU) +#define MIPI_DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_SHIFT (0U) +#define MIPI_DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_MASK) >> MIPI_DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_SHIFT) + +/* Bitfield definition for register: VID_PKT_STATUS */ +/* + * DPI_BUFF_PLD_FULL (R) + * + * This bit indicates the full status of the payload internal buffer + * for video Mode. This bit is set to 0 for command Mode + */ +#define MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_MASK (0x20000UL) +#define MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_SHIFT (17U) +#define MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_SHIFT) + +/* + * DPI_BUFF_PLD_EMPTY (R) + * + * This bit indicates the empty status of the payload internal + * buffer for video Mode. This bit is set to 0 for command Mod + */ +#define MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_MASK (0x10000UL) +#define MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_SHIFT (16U) +#define MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_SHIFT) + +/* + * DPI_PLD_W_FULL (R) + * + * This bit indicates the full status of write payload FIFO for + * video Mode. This bit is set to 0 for command Mode + */ +#define MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_FULL_MASK (0x8U) +#define MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_FULL_SHIFT (3U) +#define MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_FULL_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_FULL_SHIFT) + +/* + * DPI_PLD_W_EMPTY (R) + * + * This bit indicates the empty status of write payload FIFO for + * video Mode. This bit is set to 0 for command Mode + */ +#define MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_EMPTY_MASK (0x4U) +#define MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_EMPTY_SHIFT (2U) +#define MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_EMPTY_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_EMPTY_SHIFT) + +/* + * DPI_CMD_W_FULL (R) + * + * This bit indicates the full status of write command FIFO for + * video Mode. This bit is set to 0 for command Mode + */ +#define MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_FULL_MASK (0x2U) +#define MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_FULL_SHIFT (1U) +#define MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_FULL_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_FULL_SHIFT) + +/* + * DPI_CMD_W_EMPTY (R) + * + * This bit indicates the empty status of write command FIFO + * for video Mode. This bit is set to 0 for command Mode + */ +#define MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_EMPTY_MASK (0x1U) +#define MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_EMPTY_SHIFT (0U) +#define MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_EMPTY_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_EMPTY_SHIFT) + +/* Bitfield definition for register: SDF_3D_ACT */ +/* + * SEND_3D_CFG (R) + * + * When set, causes the next VSS packet to include 3D control + * payload in every VSS packet. + */ +#define MIPI_DSI_SDF_3D_ACT_SEND_3D_CFG_MASK (0x10000UL) +#define MIPI_DSI_SDF_3D_ACT_SEND_3D_CFG_SHIFT (16U) +#define MIPI_DSI_SDF_3D_ACT_SEND_3D_CFG_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_ACT_SEND_3D_CFG_MASK) >> MIPI_DSI_SDF_3D_ACT_SEND_3D_CFG_SHIFT) + +/* + * RIGHT_FIRST (R) + * + * This bit specifies the left/right order + */ +#define MIPI_DSI_SDF_3D_ACT_RIGHT_FIRST_MASK (0x20U) +#define MIPI_DSI_SDF_3D_ACT_RIGHT_FIRST_SHIFT (5U) +#define MIPI_DSI_SDF_3D_ACT_RIGHT_FIRST_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_ACT_RIGHT_FIRST_MASK) >> MIPI_DSI_SDF_3D_ACT_RIGHT_FIRST_SHIFT) + +/* + * SECOND_VSYNC (R) + * + * This field specifies whether there is a second VSYNC pulse + * between Left and Right Images, when 3D Image Format is + * Frame-based + */ +#define MIPI_DSI_SDF_3D_ACT_SECOND_VSYNC_MASK (0x10U) +#define MIPI_DSI_SDF_3D_ACT_SECOND_VSYNC_SHIFT (4U) +#define MIPI_DSI_SDF_3D_ACT_SECOND_VSYNC_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_ACT_SECOND_VSYNC_MASK) >> MIPI_DSI_SDF_3D_ACT_SECOND_VSYNC_SHIFT) + +/* + * FORMAT_3D (R) + * + * This field specifies 3D Image Format + */ +#define MIPI_DSI_SDF_3D_ACT_FORMAT_3D_MASK (0xCU) +#define MIPI_DSI_SDF_3D_ACT_FORMAT_3D_SHIFT (2U) +#define MIPI_DSI_SDF_3D_ACT_FORMAT_3D_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_ACT_FORMAT_3D_MASK) >> MIPI_DSI_SDF_3D_ACT_FORMAT_3D_SHIFT) + +/* + * MODE_3D (R) + * + * This field specifies 3D Mode On/Off and Display Orientation + */ +#define MIPI_DSI_SDF_3D_ACT_MODE_3D_MASK (0x3U) +#define MIPI_DSI_SDF_3D_ACT_MODE_3D_SHIFT (0U) +#define MIPI_DSI_SDF_3D_ACT_MODE_3D_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_ACT_MODE_3D_MASK) >> MIPI_DSI_SDF_3D_ACT_MODE_3D_SHIFT) + + + + +#endif /* HPM_MIPI_DSI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mmc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mmc_regs.h new file mode 100644 index 00000000000..06fc885ab17 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mmc_regs.h @@ -0,0 +1,1621 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_MMC_H +#define HPM_MMC_H + +typedef struct { + __RW uint32_t CR; /* 0x0: Control Register */ + __RW uint32_t STA; /* 0x4: Status Register */ + __RW uint32_t INT_EN; /* 0x8: Interrupt Enable Register */ + __RW uint32_t SYSCLK_FREQ; /* 0xC: System Clock Frequency Register */ + __RW uint32_t SYSCLK_PERIOD; /* 0x10: System Clock Period Register */ + __RW uint32_t OOSYNC_THETA_THR; /* 0x14: Position Out-Of-Sync Threshold Regster */ + __RW uint32_t DISCRETECFG0; /* 0x18: Discrete Mode Configuration 0 Register */ + __RW uint32_t DISCRETECFG1; /* 0x1C: Discrete Mode Configuration 1 Register */ + __RW uint32_t CONTCFG0; /* 0x20: Continuous Mode Configuration 0 Register */ + __RW uint32_t INI_POS_TIME; /* 0x24: The destined timestamp register for position initialization */ + __RW uint32_t INI_POS; /* 0x28: The destined position register for position initialization */ + __RW uint32_t INI_REV; /* 0x2C: The destined revolution register for position initialization */ + __RW uint32_t INI_SPEED; /* 0x30: The destined speed register for position initialization */ + __RW uint32_t INI_ACCEL; /* 0x34: The destined accelerator register for position initialization */ + __RW uint32_t INI_COEF_TIME; /* 0x38: The destined timestamp register for coefficients initialization */ + __RW uint32_t INI_PCOEF; /* 0x3C: The destined coefficient P register for coefficients initialization */ + __RW uint32_t INI_ICOEF; /* 0x40: The destined coefficient I register for coefficients initialization */ + __RW uint32_t INI_ACOEF; /* 0x44: The destined coefficient A register for coefficients initialization */ + __R uint32_t ESTM_TIM; /* 0x48: The timestamp register for internal estimation */ + __R uint32_t ESTM_POS; /* 0x4C: The position register for the internal estimation */ + __R uint32_t ESTM_REV; /* 0x50: The revolution register for the internal estimation */ + __R uint32_t ESTM_SPEED; /* 0x54: The speed register for the internal estimation */ + __R uint32_t ESTM_ACCEL; /* 0x58: The accelerator register for theinternal estimation */ + __R uint32_t CUR_PCOEF; /* 0x5C: The coefficient P register for the internal estimation */ + __R uint32_t CUR_ICOEF; /* 0x60: The coefficient I register for the internal estimation */ + __R uint32_t CUR_ACOEF; /* 0x64: The coefficient A register for the internal estimation */ + __RW uint32_t INI_DELTA_POS_TIME; /* 0x68: The destined timestamp register for delta position initialization */ + __RW uint32_t INI_DELTA_POS; /* 0x6C: The destined delta position register for delta position initialization */ + __RW uint32_t INI_DELTA_REV; /* 0x70: The destined delta revolution register for delta position initialization */ + __RW uint32_t INI_DELTA_SPEED; /* 0x74: The destined delta speed register for delta position initialization */ + __RW uint32_t INI_DELTA_ACCEL; /* 0x78: The destined delta accelerator register for delta position initialization */ + __R uint8_t RESERVED0[4]; /* 0x7C - 0x7F: Reserved */ + __RW uint32_t POS_TRG_CFG; /* 0x80: Tracking Configuration pos trigger cfg */ + __RW uint32_t POS_TRG_POS_THR; /* 0x84: Tracking Configuration position threshold */ + __RW uint32_t POS_TRG_REV_THR; /* 0x88: Tracking Configuration revolution threshold */ + __RW uint32_t SPEED_TRG_CFG; /* 0x8C: Tracking Configuration speed trigger cfg */ + __RW uint32_t SPEED_TRG_THR; /* 0x90: Tracking Configuration speed threshold */ + __R uint8_t RESERVED1[12]; /* 0x94 - 0x9F: Reserved */ + struct { + __RW uint32_t ERR_THR; /* 0xA0: Tracking Configuration coef trigger cfg */ + __RW uint32_t P; /* 0xA4: Tracking Configuration coef trigger cfg P */ + __RW uint32_t I; /* 0xA8: Tracking Configuration coef trigger cfg I */ + __RW uint32_t A; /* 0xAC: Tracking Configuration coef trigger cfg A */ + __RW uint32_t TIME; /* 0xB0: Tracking Configuration coef trigger cfg time */ + } COEF_TRG_CFG[3]; + __R uint8_t RESERVED2[36]; /* 0xDC - 0xFF: Reserved */ + struct { + __RW uint32_t BR_CTRL; /* 0x100: Prediction Control Register */ + __RW uint32_t BR_TIMEOFF; /* 0x104: Prediction Timing Offset Register */ + __RW uint32_t BR_TRG_PERIOD; /* 0x108: Prediction Triggering Period Offset Register */ + __RW uint32_t BR_TRG_F_TIME; /* 0x10C: Prediction Triggering First Offset Register */ + __RW uint32_t BR_ST; /* 0x110: Prediction Status Register */ + __R uint8_t RESERVED0[44]; /* 0x114 - 0x13F: Reserved */ + __RW uint32_t BR_TRG_POS_CFG; /* 0x140: Prediction Configuration postion trigger cfg */ + __RW uint32_t BR_TRG_POS_THR; /* 0x144: Prediction Configuration postion threshold */ + __RW uint32_t BR_TRG_REV_THR; /* 0x148: Prediction Configuration revolutiom threshold */ + __RW uint32_t BR_TRG_SPEED_CFG; /* 0x14C: Prediction Configuration speed trigger cfg */ + __RW uint32_t BR_TRG_SPEED_THR; /* 0x150: Prediction Configuration speed threshold */ + __R uint8_t RESERVED1[108]; /* 0x154 - 0x1BF: Reserved */ + __RW uint32_t BR_INI_POS_TIME; /* 0x1C0: Initialization timestamp for open-loop mode */ + __RW uint32_t BR_INI_POS; /* 0x1C4: Initialization position for open-loop mode */ + __RW uint32_t BR_INI_REV; /* 0x1C8: Initialization revolution for open-loop mode */ + __RW uint32_t BR_INI_SPEED; /* 0x1CC: Initialization speed for open-loop mode */ + __RW uint32_t BR_INI_ACCEL; /* 0x1D0: Initialization acceleration for open-loop mode */ + __RW uint32_t BR_INI_DELTA_POS_TIME; /* 0x1D4: Initialization timestamp for delta mode in prediction mode */ + __RW uint32_t BR_INI_DELTA_POS; /* 0x1D8: Initialization delta position for delta mode in prediction mode */ + __RW uint32_t BR_INI_DELTA_REV; /* 0x1DC: Initialization delta revolution for delta mode in prediction mode */ + __RW uint32_t BR_INI_DELTA_SPEED; /* 0x1E0: Initialization delta speed for delta mode in prediction mode */ + __RW uint32_t BR_INI_DELTA_ACCEL; /* 0x1E4: Initialization delta acceleration for delta mode in prediction mode */ + __R uint8_t RESERVED2[4]; /* 0x1E8 - 0x1EB: Reserved */ + __R uint32_t BR_CUR_POS_TIME; /* 0x1EC: Monitor of the output timestamp */ + __R uint32_t BR_CUR_POS; /* 0x1F0: Monitor of the output position */ + __R uint32_t BR_CUR_REV; /* 0x1F4: Monitor of the output revolution */ + __R uint32_t BR_CUR_SPEED; /* 0x1F8: Monitor of the output speed */ + __R uint32_t BR_CUR_ACCEL; /* 0x1FC: Monitor of the output acceleration */ + } BR[2]; + __R uint32_t BK0_TIMESTAMP; /* 0x300: Monitor of the just received input timestamp for tracing logic */ + __R uint32_t BK0_POSITION; /* 0x304: Monitor of the just received input position for tracing logic */ + __R uint32_t BK0_REVOLUTION; /* 0x308: Monitor of the just received input revolution for tracing logic */ + __R uint32_t BK0_SPEED; /* 0x30C: Monitor of the just received input speed for tracing logic */ + __R uint32_t BK0_ACCELERATOR; /* 0x310: Monitor of the just received input acceleration for tracing logic */ + __R uint8_t RESERVED3[12]; /* 0x314 - 0x31F: Reserved */ + __R uint32_t BK1_TIMESTAMP; /* 0x320: Monitor of the previous received input timestamp for tracing logic */ + __R uint32_t BK1_POSITION; /* 0x324: Monitor of the previous received input position for tracing logic */ + __R uint32_t BK1_REVOLUTION; /* 0x328: Monitor of the previous received input revolution for tracing logic */ + __R uint32_t BK1_SPEED; /* 0x32C: Monitor of the previous received input speed for tracing logic */ + __R uint32_t BK1_ACCELERATOR; /* 0x330: Monitor of the previous received input acceleration for tracing logic */ +} MMC_Type; + + +/* Bitfield definition for register: CR */ +/* + * SFTRST (RW) + * + * Software reset, high active. When write 1 ,all internal logical will be reset. + * 0b - No action + * 1b - All MMC internal registers are forced into their reset state. Interface registers are not affected. + */ +#define MMC_CR_SFTRST_MASK (0x80000000UL) +#define MMC_CR_SFTRST_SHIFT (31U) +#define MMC_CR_SFTRST_SET(x) (((uint32_t)(x) << MMC_CR_SFTRST_SHIFT) & MMC_CR_SFTRST_MASK) +#define MMC_CR_SFTRST_GET(x) (((uint32_t)(x) & MMC_CR_SFTRST_MASK) >> MMC_CR_SFTRST_SHIFT) + +/* + * INI_BR0_POS_REQ (RW) + * + * Auto clear. Only effective in open_loop mode. + */ +#define MMC_CR_INI_BR0_POS_REQ_MASK (0x20000000UL) +#define MMC_CR_INI_BR0_POS_REQ_SHIFT (29U) +#define MMC_CR_INI_BR0_POS_REQ_SET(x) (((uint32_t)(x) << MMC_CR_INI_BR0_POS_REQ_SHIFT) & MMC_CR_INI_BR0_POS_REQ_MASK) +#define MMC_CR_INI_BR0_POS_REQ_GET(x) (((uint32_t)(x) & MMC_CR_INI_BR0_POS_REQ_MASK) >> MMC_CR_INI_BR0_POS_REQ_SHIFT) + +/* + * INI_BR1_POS_REQ (RW) + * + * Auto clear. Only effective in open_loop mode. + */ +#define MMC_CR_INI_BR1_POS_REQ_MASK (0x10000000UL) +#define MMC_CR_INI_BR1_POS_REQ_SHIFT (28U) +#define MMC_CR_INI_BR1_POS_REQ_SET(x) (((uint32_t)(x) << MMC_CR_INI_BR1_POS_REQ_SHIFT) & MMC_CR_INI_BR1_POS_REQ_MASK) +#define MMC_CR_INI_BR1_POS_REQ_GET(x) (((uint32_t)(x) & MMC_CR_INI_BR1_POS_REQ_MASK) >> MMC_CR_INI_BR1_POS_REQ_SHIFT) + +/* + * FRCACCELZERO (RW) + * + * Zeroise the accelerator calculation. + */ +#define MMC_CR_FRCACCELZERO_MASK (0x8000000UL) +#define MMC_CR_FRCACCELZERO_SHIFT (27U) +#define MMC_CR_FRCACCELZERO_SET(x) (((uint32_t)(x) << MMC_CR_FRCACCELZERO_SHIFT) & MMC_CR_FRCACCELZERO_MASK) +#define MMC_CR_FRCACCELZERO_GET(x) (((uint32_t)(x) & MMC_CR_FRCACCELZERO_MASK) >> MMC_CR_FRCACCELZERO_SHIFT) + +/* + * MS_COEF_EN (RW) + * + * Multiple Coefficients Enable + */ +#define MMC_CR_MS_COEF_EN_MASK (0x4000000UL) +#define MMC_CR_MS_COEF_EN_SHIFT (26U) +#define MMC_CR_MS_COEF_EN_SET(x) (((uint32_t)(x) << MMC_CR_MS_COEF_EN_SHIFT) & MMC_CR_MS_COEF_EN_MASK) +#define MMC_CR_MS_COEF_EN_GET(x) (((uint32_t)(x) & MMC_CR_MS_COEF_EN_MASK) >> MMC_CR_MS_COEF_EN_SHIFT) + +/* + * INI_DELTA_POS_TRG_TYPE (RW) + * + * 0: Time Stamp in the configuration + * 1: Risedge of In Trg[0] + * 2: Risedge of In Trg[1] + * 3: Risedge of out trg[0] + * 4: Risedge of out trg[1] + * 5: triggered by self position trigger + * 6: triggered by self speed trigger + * Otherser: no function + */ +#define MMC_CR_INI_DELTA_POS_TRG_TYPE_MASK (0x3800000UL) +#define MMC_CR_INI_DELTA_POS_TRG_TYPE_SHIFT (23U) +#define MMC_CR_INI_DELTA_POS_TRG_TYPE_SET(x) (((uint32_t)(x) << MMC_CR_INI_DELTA_POS_TRG_TYPE_SHIFT) & MMC_CR_INI_DELTA_POS_TRG_TYPE_MASK) +#define MMC_CR_INI_DELTA_POS_TRG_TYPE_GET(x) (((uint32_t)(x) & MMC_CR_INI_DELTA_POS_TRG_TYPE_MASK) >> MMC_CR_INI_DELTA_POS_TRG_TYPE_SHIFT) + +/* + * INI_POS_TRG_TYPE (RW) + * + * 0: Time Stamp in the configuration + * 1: Risedge of In Trg[0] + * 2: Risedge of In Trg[1] + * 3: Risedge of out trg[0] + * 4: Risedge of out trg[1] + * 5: triggered by self position trigger + * 6: triggered by self speed trigger + * Otherser: no function + */ +#define MMC_CR_INI_POS_TRG_TYPE_MASK (0x700000UL) +#define MMC_CR_INI_POS_TRG_TYPE_SHIFT (20U) +#define MMC_CR_INI_POS_TRG_TYPE_SET(x) (((uint32_t)(x) << MMC_CR_INI_POS_TRG_TYPE_SHIFT) & MMC_CR_INI_POS_TRG_TYPE_MASK) +#define MMC_CR_INI_POS_TRG_TYPE_GET(x) (((uint32_t)(x) & MMC_CR_INI_POS_TRG_TYPE_MASK) >> MMC_CR_INI_POS_TRG_TYPE_SHIFT) + +/* + * INI_DELTA_POS_CMD_MSK (RW) + * + * 1: change + * 0: won't change + * bit 3: for delta accel + * bit 2: for delta speed + * bit 1: for delta revolution + * bit 0: for delta position + */ +#define MMC_CR_INI_DELTA_POS_CMD_MSK_MASK (0xF0000UL) +#define MMC_CR_INI_DELTA_POS_CMD_MSK_SHIFT (16U) +#define MMC_CR_INI_DELTA_POS_CMD_MSK_SET(x) (((uint32_t)(x) << MMC_CR_INI_DELTA_POS_CMD_MSK_SHIFT) & MMC_CR_INI_DELTA_POS_CMD_MSK_MASK) +#define MMC_CR_INI_DELTA_POS_CMD_MSK_GET(x) (((uint32_t)(x) & MMC_CR_INI_DELTA_POS_CMD_MSK_MASK) >> MMC_CR_INI_DELTA_POS_CMD_MSK_SHIFT) + +/* + * INI_DELTA_POS_REQ (RW) + * + * 1: Command to reload the delta pos. Auto clear + * 0: + */ +#define MMC_CR_INI_DELTA_POS_REQ_MASK (0x8000U) +#define MMC_CR_INI_DELTA_POS_REQ_SHIFT (15U) +#define MMC_CR_INI_DELTA_POS_REQ_SET(x) (((uint32_t)(x) << MMC_CR_INI_DELTA_POS_REQ_SHIFT) & MMC_CR_INI_DELTA_POS_REQ_MASK) +#define MMC_CR_INI_DELTA_POS_REQ_GET(x) (((uint32_t)(x) & MMC_CR_INI_DELTA_POS_REQ_MASK) >> MMC_CR_INI_DELTA_POS_REQ_SHIFT) + +/* + * OPEN_LOOP_MODE (RW) + * + * 1: in open loop mode + * 0: not in open loop mode + */ +#define MMC_CR_OPEN_LOOP_MODE_MASK (0x4000U) +#define MMC_CR_OPEN_LOOP_MODE_SHIFT (14U) +#define MMC_CR_OPEN_LOOP_MODE_SET(x) (((uint32_t)(x) << MMC_CR_OPEN_LOOP_MODE_SHIFT) & MMC_CR_OPEN_LOOP_MODE_MASK) +#define MMC_CR_OPEN_LOOP_MODE_GET(x) (((uint32_t)(x) & MMC_CR_OPEN_LOOP_MODE_MASK) >> MMC_CR_OPEN_LOOP_MODE_SHIFT) + +/* + * POS_TYPE (RW) + * + * 1: 32-bit for rev+pos, with each element occupying 16 bits + * 0: 32-bit for rev, and 32 bit for pos + * When CR[MANUAL_IO]==1, + * 1: means that the INI_POS is acting as INI_POS cmds + * 0: means that the INI_POS is simulating the input of iposition and itimestamp + */ +#define MMC_CR_POS_TYPE_MASK (0x2000U) +#define MMC_CR_POS_TYPE_SHIFT (13U) +#define MMC_CR_POS_TYPE_SET(x) (((uint32_t)(x) << MMC_CR_POS_TYPE_SHIFT) & MMC_CR_POS_TYPE_MASK) +#define MMC_CR_POS_TYPE_GET(x) (((uint32_t)(x) & MMC_CR_POS_TYPE_MASK) >> MMC_CR_POS_TYPE_SHIFT) + +/* + * INI_POS_CMD_MSK (RW) + * + * 1: change + * 0: won't change + * bit 3: for accel + * bit 2: for speed + * bit 1: for revolution + * bit 0: for position + */ +#define MMC_CR_INI_POS_CMD_MSK_MASK (0x1E00U) +#define MMC_CR_INI_POS_CMD_MSK_SHIFT (9U) +#define MMC_CR_INI_POS_CMD_MSK_SET(x) (((uint32_t)(x) << MMC_CR_INI_POS_CMD_MSK_SHIFT) & MMC_CR_INI_POS_CMD_MSK_MASK) +#define MMC_CR_INI_POS_CMD_MSK_GET(x) (((uint32_t)(x) & MMC_CR_INI_POS_CMD_MSK_MASK) >> MMC_CR_INI_POS_CMD_MSK_SHIFT) + +/* + * INI_POS_REQ (RW) + * + * 1: Command to reload the positions. Auto clear + * 0: + */ +#define MMC_CR_INI_POS_REQ_MASK (0x100U) +#define MMC_CR_INI_POS_REQ_SHIFT (8U) +#define MMC_CR_INI_POS_REQ_SET(x) (((uint32_t)(x) << MMC_CR_INI_POS_REQ_SHIFT) & MMC_CR_INI_POS_REQ_MASK) +#define MMC_CR_INI_POS_REQ_GET(x) (((uint32_t)(x) & MMC_CR_INI_POS_REQ_MASK) >> MMC_CR_INI_POS_REQ_SHIFT) + +/* + * INI_COEFS_CMD_MSK (RW) + * + * 1: change + * 0: won't change + * bit 2: for ACOEF + * bit 1: for ICOEF + * bit 0: for PCOEF + */ +#define MMC_CR_INI_COEFS_CMD_MSK_MASK (0xE0U) +#define MMC_CR_INI_COEFS_CMD_MSK_SHIFT (5U) +#define MMC_CR_INI_COEFS_CMD_MSK_SET(x) (((uint32_t)(x) << MMC_CR_INI_COEFS_CMD_MSK_SHIFT) & MMC_CR_INI_COEFS_CMD_MSK_MASK) +#define MMC_CR_INI_COEFS_CMD_MSK_GET(x) (((uint32_t)(x) & MMC_CR_INI_COEFS_CMD_MSK_MASK) >> MMC_CR_INI_COEFS_CMD_MSK_SHIFT) + +/* + * INI_COEFS_CMD (RW) + * + * 1: Command to reload the coefs. Auto clear + * 0: + */ +#define MMC_CR_INI_COEFS_CMD_MASK (0x10U) +#define MMC_CR_INI_COEFS_CMD_SHIFT (4U) +#define MMC_CR_INI_COEFS_CMD_SET(x) (((uint32_t)(x) << MMC_CR_INI_COEFS_CMD_SHIFT) & MMC_CR_INI_COEFS_CMD_MASK) +#define MMC_CR_INI_COEFS_CMD_GET(x) (((uint32_t)(x) & MMC_CR_INI_COEFS_CMD_MASK) >> MMC_CR_INI_COEFS_CMD_SHIFT) + +/* + * SHADOW_RD_REQ (RW) + * + * 1: Shadow Request for read of tracking parameters. Auto clear + * 0: + */ +#define MMC_CR_SHADOW_RD_REQ_MASK (0x8U) +#define MMC_CR_SHADOW_RD_REQ_SHIFT (3U) +#define MMC_CR_SHADOW_RD_REQ_SET(x) (((uint32_t)(x) << MMC_CR_SHADOW_RD_REQ_SHIFT) & MMC_CR_SHADOW_RD_REQ_MASK) +#define MMC_CR_SHADOW_RD_REQ_GET(x) (((uint32_t)(x) & MMC_CR_SHADOW_RD_REQ_MASK) >> MMC_CR_SHADOW_RD_REQ_SHIFT) + +/* + * ADJOP (RW) + * + * 1: use the input iposition whenever a new iposition comes, and force the predicted output stop at the boundaries. + * 0: Continuous tracking mode, without any boundary check + */ +#define MMC_CR_ADJOP_MASK (0x4U) +#define MMC_CR_ADJOP_SHIFT (2U) +#define MMC_CR_ADJOP_SET(x) (((uint32_t)(x) << MMC_CR_ADJOP_SHIFT) & MMC_CR_ADJOP_MASK) +#define MMC_CR_ADJOP_GET(x) (((uint32_t)(x) & MMC_CR_ADJOP_MASK) >> MMC_CR_ADJOP_SHIFT) + +/* + * DISCRETETRC (RW) + * + * 1: Discrete position input + * 0: Continuous position input + */ +#define MMC_CR_DISCRETETRC_MASK (0x2U) +#define MMC_CR_DISCRETETRC_SHIFT (1U) +#define MMC_CR_DISCRETETRC_SET(x) (((uint32_t)(x) << MMC_CR_DISCRETETRC_SHIFT) & MMC_CR_DISCRETETRC_MASK) +#define MMC_CR_DISCRETETRC_GET(x) (((uint32_t)(x) & MMC_CR_DISCRETETRC_MASK) >> MMC_CR_DISCRETETRC_SHIFT) + +/* + * MOD_EN (RW) + * + * Module Enable + */ +#define MMC_CR_MOD_EN_MASK (0x1U) +#define MMC_CR_MOD_EN_SHIFT (0U) +#define MMC_CR_MOD_EN_SET(x) (((uint32_t)(x) << MMC_CR_MOD_EN_SHIFT) & MMC_CR_MOD_EN_MASK) +#define MMC_CR_MOD_EN_GET(x) (((uint32_t)(x) & MMC_CR_MOD_EN_MASK) >> MMC_CR_MOD_EN_SHIFT) + +/* Bitfield definition for register: STA */ +/* + * ERR_ID (RO) + * + * Tracking ERR_ID + */ +#define MMC_STA_ERR_ID_MASK (0xF0000000UL) +#define MMC_STA_ERR_ID_SHIFT (28U) +#define MMC_STA_ERR_ID_GET(x) (((uint32_t)(x) & MMC_STA_ERR_ID_MASK) >> MMC_STA_ERR_ID_SHIFT) + +/* + * SPEED_TRG_VALID (W1C) + * + * W1C + */ +#define MMC_STA_SPEED_TRG_VALID_MASK (0x400U) +#define MMC_STA_SPEED_TRG_VALID_SHIFT (10U) +#define MMC_STA_SPEED_TRG_VALID_SET(x) (((uint32_t)(x) << MMC_STA_SPEED_TRG_VALID_SHIFT) & MMC_STA_SPEED_TRG_VALID_MASK) +#define MMC_STA_SPEED_TRG_VALID_GET(x) (((uint32_t)(x) & MMC_STA_SPEED_TRG_VALID_MASK) >> MMC_STA_SPEED_TRG_VALID_SHIFT) + +/* + * POS_TRG_VALID (W1C) + * + * W1C + */ +#define MMC_STA_POS_TRG_VALID_MASK (0x200U) +#define MMC_STA_POS_TRG_VALID_SHIFT (9U) +#define MMC_STA_POS_TRG_VALID_SET(x) (((uint32_t)(x) << MMC_STA_POS_TRG_VALID_SHIFT) & MMC_STA_POS_TRG_VALID_MASK) +#define MMC_STA_POS_TRG_VALID_GET(x) (((uint32_t)(x) & MMC_STA_POS_TRG_VALID_MASK) >> MMC_STA_POS_TRG_VALID_SHIFT) + +/* + * INI_DELTA_POS_REQ_CMD_DONE (W1C) + * + * W1C + */ +#define MMC_STA_INI_DELTA_POS_REQ_CMD_DONE_MASK (0x100U) +#define MMC_STA_INI_DELTA_POS_REQ_CMD_DONE_SHIFT (8U) +#define MMC_STA_INI_DELTA_POS_REQ_CMD_DONE_SET(x) (((uint32_t)(x) << MMC_STA_INI_DELTA_POS_REQ_CMD_DONE_SHIFT) & MMC_STA_INI_DELTA_POS_REQ_CMD_DONE_MASK) +#define MMC_STA_INI_DELTA_POS_REQ_CMD_DONE_GET(x) (((uint32_t)(x) & MMC_STA_INI_DELTA_POS_REQ_CMD_DONE_MASK) >> MMC_STA_INI_DELTA_POS_REQ_CMD_DONE_SHIFT) + +/* + * INI_BR0_POS_REQ_CMD_DONE (W1C) + * + * W1C + */ +#define MMC_STA_INI_BR0_POS_REQ_CMD_DONE_MASK (0x80U) +#define MMC_STA_INI_BR0_POS_REQ_CMD_DONE_SHIFT (7U) +#define MMC_STA_INI_BR0_POS_REQ_CMD_DONE_SET(x) (((uint32_t)(x) << MMC_STA_INI_BR0_POS_REQ_CMD_DONE_SHIFT) & MMC_STA_INI_BR0_POS_REQ_CMD_DONE_MASK) +#define MMC_STA_INI_BR0_POS_REQ_CMD_DONE_GET(x) (((uint32_t)(x) & MMC_STA_INI_BR0_POS_REQ_CMD_DONE_MASK) >> MMC_STA_INI_BR0_POS_REQ_CMD_DONE_SHIFT) + +/* + * INI_BR1_POS_REQ_CMD_DONE (W1C) + * + * W1C + */ +#define MMC_STA_INI_BR1_POS_REQ_CMD_DONE_MASK (0x40U) +#define MMC_STA_INI_BR1_POS_REQ_CMD_DONE_SHIFT (6U) +#define MMC_STA_INI_BR1_POS_REQ_CMD_DONE_SET(x) (((uint32_t)(x) << MMC_STA_INI_BR1_POS_REQ_CMD_DONE_SHIFT) & MMC_STA_INI_BR1_POS_REQ_CMD_DONE_MASK) +#define MMC_STA_INI_BR1_POS_REQ_CMD_DONE_GET(x) (((uint32_t)(x) & MMC_STA_INI_BR1_POS_REQ_CMD_DONE_MASK) >> MMC_STA_INI_BR1_POS_REQ_CMD_DONE_SHIFT) + +/* + * IDLE (RO) + * + * Tracking Module in Idle status + */ +#define MMC_STA_IDLE_MASK (0x20U) +#define MMC_STA_IDLE_SHIFT (5U) +#define MMC_STA_IDLE_GET(x) (((uint32_t)(x) & MMC_STA_IDLE_MASK) >> MMC_STA_IDLE_SHIFT) + +/* + * OOSYNC (W1C) + * + * Tracking module out-of sync. W1C + */ +#define MMC_STA_OOSYNC_MASK (0x10U) +#define MMC_STA_OOSYNC_SHIFT (4U) +#define MMC_STA_OOSYNC_SET(x) (((uint32_t)(x) << MMC_STA_OOSYNC_SHIFT) & MMC_STA_OOSYNC_MASK) +#define MMC_STA_OOSYNC_GET(x) (((uint32_t)(x) & MMC_STA_OOSYNC_MASK) >> MMC_STA_OOSYNC_SHIFT) + +/* + * INI_POS_REQ_CMD_DONE (W1C) + * + * W1C + */ +#define MMC_STA_INI_POS_REQ_CMD_DONE_MASK (0x4U) +#define MMC_STA_INI_POS_REQ_CMD_DONE_SHIFT (2U) +#define MMC_STA_INI_POS_REQ_CMD_DONE_SET(x) (((uint32_t)(x) << MMC_STA_INI_POS_REQ_CMD_DONE_SHIFT) & MMC_STA_INI_POS_REQ_CMD_DONE_MASK) +#define MMC_STA_INI_POS_REQ_CMD_DONE_GET(x) (((uint32_t)(x) & MMC_STA_INI_POS_REQ_CMD_DONE_MASK) >> MMC_STA_INI_POS_REQ_CMD_DONE_SHIFT) + +/* + * INI_COEFS_CMD_DONE (W1C) + * + * W1C + */ +#define MMC_STA_INI_COEFS_CMD_DONE_MASK (0x2U) +#define MMC_STA_INI_COEFS_CMD_DONE_SHIFT (1U) +#define MMC_STA_INI_COEFS_CMD_DONE_SET(x) (((uint32_t)(x) << MMC_STA_INI_COEFS_CMD_DONE_SHIFT) & MMC_STA_INI_COEFS_CMD_DONE_MASK) +#define MMC_STA_INI_COEFS_CMD_DONE_GET(x) (((uint32_t)(x) & MMC_STA_INI_COEFS_CMD_DONE_MASK) >> MMC_STA_INI_COEFS_CMD_DONE_SHIFT) + +/* + * SHADOW_RD_DONE (RO) + * + * Shadow ready for read. Auto cleared by setting CR[SHADOW_RD_REQ] as 1 + */ +#define MMC_STA_SHADOW_RD_DONE_MASK (0x1U) +#define MMC_STA_SHADOW_RD_DONE_SHIFT (0U) +#define MMC_STA_SHADOW_RD_DONE_GET(x) (((uint32_t)(x) & MMC_STA_SHADOW_RD_DONE_MASK) >> MMC_STA_SHADOW_RD_DONE_SHIFT) + +/* Bitfield definition for register: INT_EN */ +/* + * SPEED_TRG_VLD_IE (RW) + * + * Interrupt Enable for SPEED_TRG_VALID + */ +#define MMC_INT_EN_SPEED_TRG_VLD_IE_MASK (0x400U) +#define MMC_INT_EN_SPEED_TRG_VLD_IE_SHIFT (10U) +#define MMC_INT_EN_SPEED_TRG_VLD_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_SPEED_TRG_VLD_IE_SHIFT) & MMC_INT_EN_SPEED_TRG_VLD_IE_MASK) +#define MMC_INT_EN_SPEED_TRG_VLD_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_SPEED_TRG_VLD_IE_MASK) >> MMC_INT_EN_SPEED_TRG_VLD_IE_SHIFT) + +/* + * POS_TRG_VLD_IE (RW) + * + * Interrupt Enable for POS_TRG_VALID + */ +#define MMC_INT_EN_POS_TRG_VLD_IE_MASK (0x200U) +#define MMC_INT_EN_POS_TRG_VLD_IE_SHIFT (9U) +#define MMC_INT_EN_POS_TRG_VLD_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_POS_TRG_VLD_IE_SHIFT) & MMC_INT_EN_POS_TRG_VLD_IE_MASK) +#define MMC_INT_EN_POS_TRG_VLD_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_POS_TRG_VLD_IE_MASK) >> MMC_INT_EN_POS_TRG_VLD_IE_SHIFT) + +/* + * INI_DELTA_POS_REQ_CMD_DONE_IE (RW) + * + * Interrupt Enable for INI_DELTA_POS_REQ_CMD_DONE + */ +#define MMC_INT_EN_INI_DELTA_POS_REQ_CMD_DONE_IE_MASK (0x100U) +#define MMC_INT_EN_INI_DELTA_POS_REQ_CMD_DONE_IE_SHIFT (8U) +#define MMC_INT_EN_INI_DELTA_POS_REQ_CMD_DONE_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_INI_DELTA_POS_REQ_CMD_DONE_IE_SHIFT) & MMC_INT_EN_INI_DELTA_POS_REQ_CMD_DONE_IE_MASK) +#define MMC_INT_EN_INI_DELTA_POS_REQ_CMD_DONE_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_INI_DELTA_POS_REQ_CMD_DONE_IE_MASK) >> MMC_INT_EN_INI_DELTA_POS_REQ_CMD_DONE_IE_SHIFT) + +/* + * INI_BR0_POS_REQ_CMD_DONE_IE (RW) + * + * Interrupt Enable for INI_BR0_POS_REQ_CMD_DONE + */ +#define MMC_INT_EN_INI_BR0_POS_REQ_CMD_DONE_IE_MASK (0x80U) +#define MMC_INT_EN_INI_BR0_POS_REQ_CMD_DONE_IE_SHIFT (7U) +#define MMC_INT_EN_INI_BR0_POS_REQ_CMD_DONE_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_INI_BR0_POS_REQ_CMD_DONE_IE_SHIFT) & MMC_INT_EN_INI_BR0_POS_REQ_CMD_DONE_IE_MASK) +#define MMC_INT_EN_INI_BR0_POS_REQ_CMD_DONE_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_INI_BR0_POS_REQ_CMD_DONE_IE_MASK) >> MMC_INT_EN_INI_BR0_POS_REQ_CMD_DONE_IE_SHIFT) + +/* + * INI_BR1_POS_REQ_CMD_DONE_IE (RW) + * + * Interrupt Enable for INI_BR1_POS_REQ_CMD_DONE + */ +#define MMC_INT_EN_INI_BR1_POS_REQ_CMD_DONE_IE_MASK (0x40U) +#define MMC_INT_EN_INI_BR1_POS_REQ_CMD_DONE_IE_SHIFT (6U) +#define MMC_INT_EN_INI_BR1_POS_REQ_CMD_DONE_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_INI_BR1_POS_REQ_CMD_DONE_IE_SHIFT) & MMC_INT_EN_INI_BR1_POS_REQ_CMD_DONE_IE_MASK) +#define MMC_INT_EN_INI_BR1_POS_REQ_CMD_DONE_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_INI_BR1_POS_REQ_CMD_DONE_IE_MASK) >> MMC_INT_EN_INI_BR1_POS_REQ_CMD_DONE_IE_SHIFT) + +/* + * OOSYNC_IE (RW) + * + * Interrupt Enable for OOSYNC + */ +#define MMC_INT_EN_OOSYNC_IE_MASK (0x10U) +#define MMC_INT_EN_OOSYNC_IE_SHIFT (4U) +#define MMC_INT_EN_OOSYNC_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_OOSYNC_IE_SHIFT) & MMC_INT_EN_OOSYNC_IE_MASK) +#define MMC_INT_EN_OOSYNC_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_OOSYNC_IE_MASK) >> MMC_INT_EN_OOSYNC_IE_SHIFT) + +/* + * INI_POS_REQ_CMD_DONE_IE (RW) + * + * Interrupt Enable for INI_POS_REQ_CMD_DONE + */ +#define MMC_INT_EN_INI_POS_REQ_CMD_DONE_IE_MASK (0x4U) +#define MMC_INT_EN_INI_POS_REQ_CMD_DONE_IE_SHIFT (2U) +#define MMC_INT_EN_INI_POS_REQ_CMD_DONE_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_INI_POS_REQ_CMD_DONE_IE_SHIFT) & MMC_INT_EN_INI_POS_REQ_CMD_DONE_IE_MASK) +#define MMC_INT_EN_INI_POS_REQ_CMD_DONE_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_INI_POS_REQ_CMD_DONE_IE_MASK) >> MMC_INT_EN_INI_POS_REQ_CMD_DONE_IE_SHIFT) + +/* + * INI_COEFS_CMD_DONE_IE (RW) + * + * Interrupt Enable for INI_COEFS_CMD_DONE + */ +#define MMC_INT_EN_INI_COEFS_CMD_DONE_IE_MASK (0x2U) +#define MMC_INT_EN_INI_COEFS_CMD_DONE_IE_SHIFT (1U) +#define MMC_INT_EN_INI_COEFS_CMD_DONE_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_INI_COEFS_CMD_DONE_IE_SHIFT) & MMC_INT_EN_INI_COEFS_CMD_DONE_IE_MASK) +#define MMC_INT_EN_INI_COEFS_CMD_DONE_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_INI_COEFS_CMD_DONE_IE_MASK) >> MMC_INT_EN_INI_COEFS_CMD_DONE_IE_SHIFT) + +/* + * SHADOW_RD_DONE_IE (RW) + * + * Interrupt Enable for SHADOW_RD_DONE + */ +#define MMC_INT_EN_SHADOW_RD_DONE_IE_MASK (0x1U) +#define MMC_INT_EN_SHADOW_RD_DONE_IE_SHIFT (0U) +#define MMC_INT_EN_SHADOW_RD_DONE_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_SHADOW_RD_DONE_IE_SHIFT) & MMC_INT_EN_SHADOW_RD_DONE_IE_MASK) +#define MMC_INT_EN_SHADOW_RD_DONE_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_SHADOW_RD_DONE_IE_MASK) >> MMC_INT_EN_SHADOW_RD_DONE_IE_SHIFT) + +/* Bitfield definition for register: SYSCLK_FREQ */ +/* + * VAL (RW) + * + * system clock frequency, ufix<32, 0> + */ +#define MMC_SYSCLK_FREQ_VAL_MASK (0xFFFFFFFFUL) +#define MMC_SYSCLK_FREQ_VAL_SHIFT (0U) +#define MMC_SYSCLK_FREQ_VAL_SET(x) (((uint32_t)(x) << MMC_SYSCLK_FREQ_VAL_SHIFT) & MMC_SYSCLK_FREQ_VAL_MASK) +#define MMC_SYSCLK_FREQ_VAL_GET(x) (((uint32_t)(x) & MMC_SYSCLK_FREQ_VAL_MASK) >> MMC_SYSCLK_FREQ_VAL_SHIFT) + +/* Bitfield definition for register: SYSCLK_PERIOD */ +/* + * VAL (RW) + * + * round( the value of clock period * (2^24)*(2^20) ), ufix<32, 0> + */ +#define MMC_SYSCLK_PERIOD_VAL_MASK (0xFFFFFFFFUL) +#define MMC_SYSCLK_PERIOD_VAL_SHIFT (0U) +#define MMC_SYSCLK_PERIOD_VAL_SET(x) (((uint32_t)(x) << MMC_SYSCLK_PERIOD_VAL_SHIFT) & MMC_SYSCLK_PERIOD_VAL_MASK) +#define MMC_SYSCLK_PERIOD_VAL_GET(x) (((uint32_t)(x) & MMC_SYSCLK_PERIOD_VAL_MASK) >> MMC_SYSCLK_PERIOD_VAL_SHIFT) + +/* Bitfield definition for register: OOSYNC_THETA_THR */ +/* + * VAL (RW) + * + * the threshold of theta difference between actual and prediction for out-of-sync determination，ufix<32, 32> + */ +#define MMC_OOSYNC_THETA_THR_VAL_MASK (0xFFFFFFFFUL) +#define MMC_OOSYNC_THETA_THR_VAL_SHIFT (0U) +#define MMC_OOSYNC_THETA_THR_VAL_SET(x) (((uint32_t)(x) << MMC_OOSYNC_THETA_THR_VAL_SHIFT) & MMC_OOSYNC_THETA_THR_VAL_MASK) +#define MMC_OOSYNC_THETA_THR_VAL_GET(x) (((uint32_t)(x) & MMC_OOSYNC_THETA_THR_VAL_MASK) >> MMC_OOSYNC_THETA_THR_VAL_SHIFT) + +/* Bitfield definition for register: DISCRETECFG0 */ +/* + * POSMAX (RW) + * + * Max ID Of Lines. For example-1, for 512 lines, it is 511. ufix<32, 0> + */ +#define MMC_DISCRETECFG0_POSMAX_MASK (0xFFFFFUL) +#define MMC_DISCRETECFG0_POSMAX_SHIFT (0U) +#define MMC_DISCRETECFG0_POSMAX_SET(x) (((uint32_t)(x) << MMC_DISCRETECFG0_POSMAX_SHIFT) & MMC_DISCRETECFG0_POSMAX_MASK) +#define MMC_DISCRETECFG0_POSMAX_GET(x) (((uint32_t)(x) & MMC_DISCRETECFG0_POSMAX_MASK) >> MMC_DISCRETECFG0_POSMAX_SHIFT) + +/* Bitfield definition for register: DISCRETECFG1 */ +/* + * INV_POSMAX (RW) + * + * discrete mode: ufix<32, 0> of 1/(Number Of Lines) + * continuous mode: the max delta for tracking from the last received position, ufix<32, 32> + */ +#define MMC_DISCRETECFG1_INV_POSMAX_MASK (0xFFFFFFFFUL) +#define MMC_DISCRETECFG1_INV_POSMAX_SHIFT (0U) +#define MMC_DISCRETECFG1_INV_POSMAX_SET(x) (((uint32_t)(x) << MMC_DISCRETECFG1_INV_POSMAX_SHIFT) & MMC_DISCRETECFG1_INV_POSMAX_MASK) +#define MMC_DISCRETECFG1_INV_POSMAX_GET(x) (((uint32_t)(x) & MMC_DISCRETECFG1_INV_POSMAX_MASK) >> MMC_DISCRETECFG1_INV_POSMAX_SHIFT) + +/* Bitfield definition for register: CONTCFG0 */ +/* + * HALF_CIRC_THETA (RW) + * + * the theta for cal the clockwise or anticlockwise rotation between two adjacent inputs, ufix<32, 32> + */ +#define MMC_CONTCFG0_HALF_CIRC_THETA_MASK (0xFFFFFFFFUL) +#define MMC_CONTCFG0_HALF_CIRC_THETA_SHIFT (0U) +#define MMC_CONTCFG0_HALF_CIRC_THETA_SET(x) (((uint32_t)(x) << MMC_CONTCFG0_HALF_CIRC_THETA_SHIFT) & MMC_CONTCFG0_HALF_CIRC_THETA_MASK) +#define MMC_CONTCFG0_HALF_CIRC_THETA_GET(x) (((uint32_t)(x) & MMC_CONTCFG0_HALF_CIRC_THETA_MASK) >> MMC_CONTCFG0_HALF_CIRC_THETA_SHIFT) + +/* Bitfield definition for register: INI_POS_TIME */ +/* + * VAL (RW) + * + * indicate the time to change the values. + * 0: instant change + */ +#define MMC_INI_POS_TIME_VAL_MASK (0xFFFFFFFFUL) +#define MMC_INI_POS_TIME_VAL_SHIFT (0U) +#define MMC_INI_POS_TIME_VAL_SET(x) (((uint32_t)(x) << MMC_INI_POS_TIME_VAL_SHIFT) & MMC_INI_POS_TIME_VAL_MASK) +#define MMC_INI_POS_TIME_VAL_GET(x) (((uint32_t)(x) & MMC_INI_POS_TIME_VAL_MASK) >> MMC_INI_POS_TIME_VAL_SHIFT) + +/* Bitfield definition for register: INI_POS */ +/* + * VAL (RW) + * + * the value； + * continuous mode: ufix<32, 32> + */ +#define MMC_INI_POS_VAL_MASK (0xFFFFFFFFUL) +#define MMC_INI_POS_VAL_SHIFT (0U) +#define MMC_INI_POS_VAL_SET(x) (((uint32_t)(x) << MMC_INI_POS_VAL_SHIFT) & MMC_INI_POS_VAL_MASK) +#define MMC_INI_POS_VAL_GET(x) (((uint32_t)(x) & MMC_INI_POS_VAL_MASK) >> MMC_INI_POS_VAL_SHIFT) + +/* Bitfield definition for register: INI_REV */ +/* + * VAL (RW) + * + * the value； + * continuous mode: ufix<32, 0> + */ +#define MMC_INI_REV_VAL_MASK (0xFFFFFFFFUL) +#define MMC_INI_REV_VAL_SHIFT (0U) +#define MMC_INI_REV_VAL_SET(x) (((uint32_t)(x) << MMC_INI_REV_VAL_SHIFT) & MMC_INI_REV_VAL_MASK) +#define MMC_INI_REV_VAL_GET(x) (((uint32_t)(x) & MMC_INI_REV_VAL_MASK) >> MMC_INI_REV_VAL_SHIFT) + +/* Bitfield definition for register: INI_SPEED */ +/* + * VAL (RW) + * + * the value; + * continuous mode: fix<32, 19> + */ +#define MMC_INI_SPEED_VAL_MASK (0xFFFFFFFFUL) +#define MMC_INI_SPEED_VAL_SHIFT (0U) +#define MMC_INI_SPEED_VAL_SET(x) (((uint32_t)(x) << MMC_INI_SPEED_VAL_SHIFT) & MMC_INI_SPEED_VAL_MASK) +#define MMC_INI_SPEED_VAL_GET(x) (((uint32_t)(x) & MMC_INI_SPEED_VAL_MASK) >> MMC_INI_SPEED_VAL_SHIFT) + +/* Bitfield definition for register: INI_ACCEL */ +/* + * VAL (RW) + * + * the value + * continuous mode: fix<32, 19> + */ +#define MMC_INI_ACCEL_VAL_MASK (0xFFFFFFFFUL) +#define MMC_INI_ACCEL_VAL_SHIFT (0U) +#define MMC_INI_ACCEL_VAL_SET(x) (((uint32_t)(x) << MMC_INI_ACCEL_VAL_SHIFT) & MMC_INI_ACCEL_VAL_MASK) +#define MMC_INI_ACCEL_VAL_GET(x) (((uint32_t)(x) & MMC_INI_ACCEL_VAL_MASK) >> MMC_INI_ACCEL_VAL_SHIFT) + +/* Bitfield definition for register: INI_COEF_TIME */ +/* + * VAL (RW) + * + * indicate the time to change the values. + * 0: instant change + */ +#define MMC_INI_COEF_TIME_VAL_MASK (0xFFFFFFFFUL) +#define MMC_INI_COEF_TIME_VAL_SHIFT (0U) +#define MMC_INI_COEF_TIME_VAL_SET(x) (((uint32_t)(x) << MMC_INI_COEF_TIME_VAL_SHIFT) & MMC_INI_COEF_TIME_VAL_MASK) +#define MMC_INI_COEF_TIME_VAL_GET(x) (((uint32_t)(x) & MMC_INI_COEF_TIME_VAL_MASK) >> MMC_INI_COEF_TIME_VAL_SHIFT) + +/* Bitfield definition for register: INI_PCOEF */ +/* + * VAL (RW) + * + * the value, fix<32, 15> + */ +#define MMC_INI_PCOEF_VAL_MASK (0xFFFFFFFFUL) +#define MMC_INI_PCOEF_VAL_SHIFT (0U) +#define MMC_INI_PCOEF_VAL_SET(x) (((uint32_t)(x) << MMC_INI_PCOEF_VAL_SHIFT) & MMC_INI_PCOEF_VAL_MASK) +#define MMC_INI_PCOEF_VAL_GET(x) (((uint32_t)(x) & MMC_INI_PCOEF_VAL_MASK) >> MMC_INI_PCOEF_VAL_SHIFT) + +/* Bitfield definition for register: INI_ICOEF */ +/* + * VAL (RW) + * + * the value, fix<32, 21> + */ +#define MMC_INI_ICOEF_VAL_MASK (0xFFFFFFFFUL) +#define MMC_INI_ICOEF_VAL_SHIFT (0U) +#define MMC_INI_ICOEF_VAL_SET(x) (((uint32_t)(x) << MMC_INI_ICOEF_VAL_SHIFT) & MMC_INI_ICOEF_VAL_MASK) +#define MMC_INI_ICOEF_VAL_GET(x) (((uint32_t)(x) & MMC_INI_ICOEF_VAL_MASK) >> MMC_INI_ICOEF_VAL_SHIFT) + +/* Bitfield definition for register: INI_ACOEF */ +/* + * VAL (RW) + * + * the value, fix<32, 19> + */ +#define MMC_INI_ACOEF_VAL_MASK (0xFFFFFFFFUL) +#define MMC_INI_ACOEF_VAL_SHIFT (0U) +#define MMC_INI_ACOEF_VAL_SET(x) (((uint32_t)(x) << MMC_INI_ACOEF_VAL_SHIFT) & MMC_INI_ACOEF_VAL_MASK) +#define MMC_INI_ACOEF_VAL_GET(x) (((uint32_t)(x) & MMC_INI_ACOEF_VAL_MASK) >> MMC_INI_ACOEF_VAL_SHIFT) + +/* Bitfield definition for register: ESTM_TIM */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_ESTM_TIM_VAL_MASK (0xFFFFFFFFUL) +#define MMC_ESTM_TIM_VAL_SHIFT (0U) +#define MMC_ESTM_TIM_VAL_GET(x) (((uint32_t)(x) & MMC_ESTM_TIM_VAL_MASK) >> MMC_ESTM_TIM_VAL_SHIFT) + +/* Bitfield definition for register: ESTM_POS */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_ESTM_POS_VAL_MASK (0xFFFFFFFFUL) +#define MMC_ESTM_POS_VAL_SHIFT (0U) +#define MMC_ESTM_POS_VAL_GET(x) (((uint32_t)(x) & MMC_ESTM_POS_VAL_MASK) >> MMC_ESTM_POS_VAL_SHIFT) + +/* Bitfield definition for register: ESTM_REV */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_ESTM_REV_VAL_MASK (0xFFFFFFFFUL) +#define MMC_ESTM_REV_VAL_SHIFT (0U) +#define MMC_ESTM_REV_VAL_GET(x) (((uint32_t)(x) & MMC_ESTM_REV_VAL_MASK) >> MMC_ESTM_REV_VAL_SHIFT) + +/* Bitfield definition for register: ESTM_SPEED */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_ESTM_SPEED_VAL_MASK (0xFFFFFFFFUL) +#define MMC_ESTM_SPEED_VAL_SHIFT (0U) +#define MMC_ESTM_SPEED_VAL_GET(x) (((uint32_t)(x) & MMC_ESTM_SPEED_VAL_MASK) >> MMC_ESTM_SPEED_VAL_SHIFT) + +/* Bitfield definition for register: ESTM_ACCEL */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_ESTM_ACCEL_VAL_MASK (0xFFFFFFFFUL) +#define MMC_ESTM_ACCEL_VAL_SHIFT (0U) +#define MMC_ESTM_ACCEL_VAL_GET(x) (((uint32_t)(x) & MMC_ESTM_ACCEL_VAL_MASK) >> MMC_ESTM_ACCEL_VAL_SHIFT) + +/* Bitfield definition for register: CUR_PCOEF */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_CUR_PCOEF_VAL_MASK (0xFFFFFFFFUL) +#define MMC_CUR_PCOEF_VAL_SHIFT (0U) +#define MMC_CUR_PCOEF_VAL_GET(x) (((uint32_t)(x) & MMC_CUR_PCOEF_VAL_MASK) >> MMC_CUR_PCOEF_VAL_SHIFT) + +/* Bitfield definition for register: CUR_ICOEF */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_CUR_ICOEF_VAL_MASK (0xFFFFFFFFUL) +#define MMC_CUR_ICOEF_VAL_SHIFT (0U) +#define MMC_CUR_ICOEF_VAL_GET(x) (((uint32_t)(x) & MMC_CUR_ICOEF_VAL_MASK) >> MMC_CUR_ICOEF_VAL_SHIFT) + +/* Bitfield definition for register: CUR_ACOEF */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_CUR_ACOEF_VAL_MASK (0xFFFFFFFFUL) +#define MMC_CUR_ACOEF_VAL_SHIFT (0U) +#define MMC_CUR_ACOEF_VAL_GET(x) (((uint32_t)(x) & MMC_CUR_ACOEF_VAL_MASK) >> MMC_CUR_ACOEF_VAL_SHIFT) + +/* Bitfield definition for register: INI_DELTA_POS_TIME */ +/* + * VAL (RW) + * + * indicate the time to change the values. + * 0: instant change + */ +#define MMC_INI_DELTA_POS_TIME_VAL_MASK (0xFFFFFFFFUL) +#define MMC_INI_DELTA_POS_TIME_VAL_SHIFT (0U) +#define MMC_INI_DELTA_POS_TIME_VAL_SET(x) (((uint32_t)(x) << MMC_INI_DELTA_POS_TIME_VAL_SHIFT) & MMC_INI_DELTA_POS_TIME_VAL_MASK) +#define MMC_INI_DELTA_POS_TIME_VAL_GET(x) (((uint32_t)(x) & MMC_INI_DELTA_POS_TIME_VAL_MASK) >> MMC_INI_DELTA_POS_TIME_VAL_SHIFT) + +/* Bitfield definition for register: INI_DELTA_POS */ +/* + * VAL (RW) + * + * the value + * continuous mode: ufix <32, 32> + */ +#define MMC_INI_DELTA_POS_VAL_MASK (0xFFFFFFFFUL) +#define MMC_INI_DELTA_POS_VAL_SHIFT (0U) +#define MMC_INI_DELTA_POS_VAL_SET(x) (((uint32_t)(x) << MMC_INI_DELTA_POS_VAL_SHIFT) & MMC_INI_DELTA_POS_VAL_MASK) +#define MMC_INI_DELTA_POS_VAL_GET(x) (((uint32_t)(x) & MMC_INI_DELTA_POS_VAL_MASK) >> MMC_INI_DELTA_POS_VAL_SHIFT) + +/* Bitfield definition for register: INI_DELTA_REV */ +/* + * VAL (RW) + * + * the value + * continuous mode: fix<32, 0> + */ +#define MMC_INI_DELTA_REV_VAL_MASK (0xFFFFFFFFUL) +#define MMC_INI_DELTA_REV_VAL_SHIFT (0U) +#define MMC_INI_DELTA_REV_VAL_SET(x) (((uint32_t)(x) << MMC_INI_DELTA_REV_VAL_SHIFT) & MMC_INI_DELTA_REV_VAL_MASK) +#define MMC_INI_DELTA_REV_VAL_GET(x) (((uint32_t)(x) & MMC_INI_DELTA_REV_VAL_MASK) >> MMC_INI_DELTA_REV_VAL_SHIFT) + +/* Bitfield definition for register: INI_DELTA_SPEED */ +/* + * VAL (RW) + * + * the value； + * continuous mode: fix<32, 19> + */ +#define MMC_INI_DELTA_SPEED_VAL_MASK (0xFFFFFFFFUL) +#define MMC_INI_DELTA_SPEED_VAL_SHIFT (0U) +#define MMC_INI_DELTA_SPEED_VAL_SET(x) (((uint32_t)(x) << MMC_INI_DELTA_SPEED_VAL_SHIFT) & MMC_INI_DELTA_SPEED_VAL_MASK) +#define MMC_INI_DELTA_SPEED_VAL_GET(x) (((uint32_t)(x) & MMC_INI_DELTA_SPEED_VAL_MASK) >> MMC_INI_DELTA_SPEED_VAL_SHIFT) + +/* Bitfield definition for register: INI_DELTA_ACCEL */ +/* + * VAL (RW) + * + * the value + * continuous mode: fix<32, 19> + */ +#define MMC_INI_DELTA_ACCEL_VAL_MASK (0xFFFFFFFFUL) +#define MMC_INI_DELTA_ACCEL_VAL_SHIFT (0U) +#define MMC_INI_DELTA_ACCEL_VAL_SET(x) (((uint32_t)(x) << MMC_INI_DELTA_ACCEL_VAL_SHIFT) & MMC_INI_DELTA_ACCEL_VAL_MASK) +#define MMC_INI_DELTA_ACCEL_VAL_GET(x) (((uint32_t)(x) & MMC_INI_DELTA_ACCEL_VAL_MASK) >> MMC_INI_DELTA_ACCEL_VAL_SHIFT) + +/* Bitfield definition for register: POS_TRG_CFG */ +/* + * EDGE (RW) + * + * 0: (rising edge) pos inc greater than, 1: (falling edge) pos dec less than + */ +#define MMC_POS_TRG_CFG_EDGE_MASK (0x2U) +#define MMC_POS_TRG_CFG_EDGE_SHIFT (1U) +#define MMC_POS_TRG_CFG_EDGE_SET(x) (((uint32_t)(x) << MMC_POS_TRG_CFG_EDGE_SHIFT) & MMC_POS_TRG_CFG_EDGE_MASK) +#define MMC_POS_TRG_CFG_EDGE_GET(x) (((uint32_t)(x) & MMC_POS_TRG_CFG_EDGE_MASK) >> MMC_POS_TRG_CFG_EDGE_SHIFT) + +/* + * EN (RW) + * + * 1-trigger valid; 0-Trigger not valid" + */ +#define MMC_POS_TRG_CFG_EN_MASK (0x1U) +#define MMC_POS_TRG_CFG_EN_SHIFT (0U) +#define MMC_POS_TRG_CFG_EN_SET(x) (((uint32_t)(x) << MMC_POS_TRG_CFG_EN_SHIFT) & MMC_POS_TRG_CFG_EN_MASK) +#define MMC_POS_TRG_CFG_EN_GET(x) (((uint32_t)(x) & MMC_POS_TRG_CFG_EN_MASK) >> MMC_POS_TRG_CFG_EN_SHIFT) + +/* Bitfield definition for register: POS_TRG_POS_THR */ +/* + * VAL (RW) + * + * For pos out trigger (pos). + * ufix<32, 32> + */ +#define MMC_POS_TRG_POS_THR_VAL_MASK (0xFFFFFFFFUL) +#define MMC_POS_TRG_POS_THR_VAL_SHIFT (0U) +#define MMC_POS_TRG_POS_THR_VAL_SET(x) (((uint32_t)(x) << MMC_POS_TRG_POS_THR_VAL_SHIFT) & MMC_POS_TRG_POS_THR_VAL_MASK) +#define MMC_POS_TRG_POS_THR_VAL_GET(x) (((uint32_t)(x) & MMC_POS_TRG_POS_THR_VAL_MASK) >> MMC_POS_TRG_POS_THR_VAL_SHIFT) + +/* Bitfield definition for register: POS_TRG_REV_THR */ +/* + * VAL (RW) + * + * For pos out trigger (rev) + * fix<32, 0> + */ +#define MMC_POS_TRG_REV_THR_VAL_MASK (0xFFFFFFFFUL) +#define MMC_POS_TRG_REV_THR_VAL_SHIFT (0U) +#define MMC_POS_TRG_REV_THR_VAL_SET(x) (((uint32_t)(x) << MMC_POS_TRG_REV_THR_VAL_SHIFT) & MMC_POS_TRG_REV_THR_VAL_MASK) +#define MMC_POS_TRG_REV_THR_VAL_GET(x) (((uint32_t)(x) & MMC_POS_TRG_REV_THR_VAL_MASK) >> MMC_POS_TRG_REV_THR_VAL_SHIFT) + +/* Bitfield definition for register: SPEED_TRG_CFG */ +/* + * COMP_TYPE (RW) + * + * 1: Use abs value for comparion. 0: Use the speed with direction info (so not the abs value) + */ +#define MMC_SPEED_TRG_CFG_COMP_TYPE_MASK (0x4U) +#define MMC_SPEED_TRG_CFG_COMP_TYPE_SHIFT (2U) +#define MMC_SPEED_TRG_CFG_COMP_TYPE_SET(x) (((uint32_t)(x) << MMC_SPEED_TRG_CFG_COMP_TYPE_SHIFT) & MMC_SPEED_TRG_CFG_COMP_TYPE_MASK) +#define MMC_SPEED_TRG_CFG_COMP_TYPE_GET(x) (((uint32_t)(x) & MMC_SPEED_TRG_CFG_COMP_TYPE_MASK) >> MMC_SPEED_TRG_CFG_COMP_TYPE_SHIFT) + +/* + * EDGE (RW) + * + * 0: (rising edge) speed inc greater than, 1: (falling edge) speed dec less than + */ +#define MMC_SPEED_TRG_CFG_EDGE_MASK (0x2U) +#define MMC_SPEED_TRG_CFG_EDGE_SHIFT (1U) +#define MMC_SPEED_TRG_CFG_EDGE_SET(x) (((uint32_t)(x) << MMC_SPEED_TRG_CFG_EDGE_SHIFT) & MMC_SPEED_TRG_CFG_EDGE_MASK) +#define MMC_SPEED_TRG_CFG_EDGE_GET(x) (((uint32_t)(x) & MMC_SPEED_TRG_CFG_EDGE_MASK) >> MMC_SPEED_TRG_CFG_EDGE_SHIFT) + +/* + * EN (RW) + * + * 1-trigger valid; 0-Trigger not valid + * Normally it means either the max pos speed, or the min negative speed. + */ +#define MMC_SPEED_TRG_CFG_EN_MASK (0x1U) +#define MMC_SPEED_TRG_CFG_EN_SHIFT (0U) +#define MMC_SPEED_TRG_CFG_EN_SET(x) (((uint32_t)(x) << MMC_SPEED_TRG_CFG_EN_SHIFT) & MMC_SPEED_TRG_CFG_EN_MASK) +#define MMC_SPEED_TRG_CFG_EN_GET(x) (((uint32_t)(x) & MMC_SPEED_TRG_CFG_EN_MASK) >> MMC_SPEED_TRG_CFG_EN_SHIFT) + +/* Bitfield definition for register: SPEED_TRG_THR */ +/* + * VAL (RW) + * + * For speed trigger. + * continuous mode: fix<32, 19> + */ +#define MMC_SPEED_TRG_THR_VAL_MASK (0xFFFFFFFFUL) +#define MMC_SPEED_TRG_THR_VAL_SHIFT (0U) +#define MMC_SPEED_TRG_THR_VAL_SET(x) (((uint32_t)(x) << MMC_SPEED_TRG_THR_VAL_SHIFT) & MMC_SPEED_TRG_THR_VAL_MASK) +#define MMC_SPEED_TRG_THR_VAL_GET(x) (((uint32_t)(x) & MMC_SPEED_TRG_THR_VAL_MASK) >> MMC_SPEED_TRG_THR_VAL_SHIFT) + +/* Bitfield definition for register of struct array COEF_TRG_CFG: ERR_THR */ +/* + * VAL (RW) + * + * ErrThr0: Error Threshold 0, (abs(tracking error)>= will choose the coefs as below) + * Note: ErrThr0>ErrThr1>ErrThr2 + * ufix<31, 28> + */ +#define MMC_COEF_TRG_CFG_ERR_THR_VAL_MASK (0xFFFFFFFFUL) +#define MMC_COEF_TRG_CFG_ERR_THR_VAL_SHIFT (0U) +#define MMC_COEF_TRG_CFG_ERR_THR_VAL_SET(x) (((uint32_t)(x) << MMC_COEF_TRG_CFG_ERR_THR_VAL_SHIFT) & MMC_COEF_TRG_CFG_ERR_THR_VAL_MASK) +#define MMC_COEF_TRG_CFG_ERR_THR_VAL_GET(x) (((uint32_t)(x) & MMC_COEF_TRG_CFG_ERR_THR_VAL_MASK) >> MMC_COEF_TRG_CFG_ERR_THR_VAL_SHIFT) + +/* Bitfield definition for register of struct array COEF_TRG_CFG: P */ +/* + * VAL (RW) + * + * P0_Coef, fix<32, 15> + */ +#define MMC_COEF_TRG_CFG_P_VAL_MASK (0xFFFFFFFFUL) +#define MMC_COEF_TRG_CFG_P_VAL_SHIFT (0U) +#define MMC_COEF_TRG_CFG_P_VAL_SET(x) (((uint32_t)(x) << MMC_COEF_TRG_CFG_P_VAL_SHIFT) & MMC_COEF_TRG_CFG_P_VAL_MASK) +#define MMC_COEF_TRG_CFG_P_VAL_GET(x) (((uint32_t)(x) & MMC_COEF_TRG_CFG_P_VAL_MASK) >> MMC_COEF_TRG_CFG_P_VAL_SHIFT) + +/* Bitfield definition for register of struct array COEF_TRG_CFG: I */ +/* + * VAL (RW) + * + * I0_Coef, fix<32, 21> + */ +#define MMC_COEF_TRG_CFG_I_VAL_MASK (0xFFFFFFFFUL) +#define MMC_COEF_TRG_CFG_I_VAL_SHIFT (0U) +#define MMC_COEF_TRG_CFG_I_VAL_SET(x) (((uint32_t)(x) << MMC_COEF_TRG_CFG_I_VAL_SHIFT) & MMC_COEF_TRG_CFG_I_VAL_MASK) +#define MMC_COEF_TRG_CFG_I_VAL_GET(x) (((uint32_t)(x) & MMC_COEF_TRG_CFG_I_VAL_MASK) >> MMC_COEF_TRG_CFG_I_VAL_SHIFT) + +/* Bitfield definition for register of struct array COEF_TRG_CFG: A */ +/* + * VAL (RW) + * + * A0_Coef，fix<32, 19> + */ +#define MMC_COEF_TRG_CFG_A_VAL_MASK (0xFFFFFFFFUL) +#define MMC_COEF_TRG_CFG_A_VAL_SHIFT (0U) +#define MMC_COEF_TRG_CFG_A_VAL_SET(x) (((uint32_t)(x) << MMC_COEF_TRG_CFG_A_VAL_SHIFT) & MMC_COEF_TRG_CFG_A_VAL_MASK) +#define MMC_COEF_TRG_CFG_A_VAL_GET(x) (((uint32_t)(x) & MMC_COEF_TRG_CFG_A_VAL_MASK) >> MMC_COEF_TRG_CFG_A_VAL_SHIFT) + +/* Bitfield definition for register of struct array COEF_TRG_CFG: TIME */ +/* + * VAL (RW) + * + * CoefTime0: Time Stayed using this coefs (counted in input samples). Ideal value of tracing cycles should +1. ufix<32,0> + */ +#define MMC_COEF_TRG_CFG_TIME_VAL_MASK (0xFFFFFFFFUL) +#define MMC_COEF_TRG_CFG_TIME_VAL_SHIFT (0U) +#define MMC_COEF_TRG_CFG_TIME_VAL_SET(x) (((uint32_t)(x) << MMC_COEF_TRG_CFG_TIME_VAL_SHIFT) & MMC_COEF_TRG_CFG_TIME_VAL_MASK) +#define MMC_COEF_TRG_CFG_TIME_VAL_GET(x) (((uint32_t)(x) & MMC_COEF_TRG_CFG_TIME_VAL_MASK) >> MMC_COEF_TRG_CFG_TIME_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_CTRL */ +/* + * SPEED_TRG_VALID_IE (RW) + * + * Interrupt Enable for SPEED_TRG_VALID + */ +#define MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_MASK (0x40000000UL) +#define MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_SHIFT (30U) +#define MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_SHIFT) & MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_MASK) +#define MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_MASK) >> MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_SHIFT) + +/* + * POS_TRG_VALID_IE (RW) + * + * Interrupt Enable for POS_TRG_VALID + */ +#define MMC_BR_BR_CTRL_POS_TRG_VALID_IE_MASK (0x20000000UL) +#define MMC_BR_BR_CTRL_POS_TRG_VALID_IE_SHIFT (29U) +#define MMC_BR_BR_CTRL_POS_TRG_VALID_IE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_POS_TRG_VALID_IE_SHIFT) & MMC_BR_BR_CTRL_POS_TRG_VALID_IE_MASK) +#define MMC_BR_BR_CTRL_POS_TRG_VALID_IE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_POS_TRG_VALID_IE_MASK) >> MMC_BR_BR_CTRL_POS_TRG_VALID_IE_SHIFT) + +/* + * INI_POS_TRG_TYPE (RW) + * + * 0: Time Stamp in the configuration + * 1: Risedge of In Trg[0] + * 2: Risedge of In Trg[1] + * 3: Risedge of out trg[0] + * 4: Risedge of out trg[1] + * 5: Risedge of self pos trigger + * 6: Risedge of self speed trigger + * Others: no function + */ +#define MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_MASK (0x3800000UL) +#define MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_SHIFT (23U) +#define MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_SHIFT) & MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_MASK) +#define MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_MASK) >> MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_SHIFT) + +/* + * INI_POS_CMD_MSK (RW) + * + * 1: change + * 0: won't change + * bit 3: for accel + * bit 2: for speed + * bit 1: for revolution + * bit 0: for position + */ +#define MMC_BR_BR_CTRL_INI_POS_CMD_MSK_MASK (0x3C0000UL) +#define MMC_BR_BR_CTRL_INI_POS_CMD_MSK_SHIFT (18U) +#define MMC_BR_BR_CTRL_INI_POS_CMD_MSK_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_INI_POS_CMD_MSK_SHIFT) & MMC_BR_BR_CTRL_INI_POS_CMD_MSK_MASK) +#define MMC_BR_BR_CTRL_INI_POS_CMD_MSK_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_INI_POS_CMD_MSK_MASK) >> MMC_BR_BR_CTRL_INI_POS_CMD_MSK_SHIFT) + +/* + * INI_DELTA_POS_TRG_TYPE (RW) + * + * 0: Time Stamp in the configuration + * 1: Risedge of In Trg[0] + * 2: Risedge of In Trg[1] + * 3: Risedge of out trg[0] + * 4: Risedge of out trg[1] + * 5: Risedge of self pos trigger + * 6: Risedge of self speed trigger + * Others: no function + */ +#define MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_MASK (0x1C000UL) +#define MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_SHIFT (14U) +#define MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_SHIFT) & MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_MASK) +#define MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_MASK) >> MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_SHIFT) + +/* + * INI_DELTA_POS_DONE_IE (RW) + * + * Interrupt Enable for INI_DELTA_POS_DONE + */ +#define MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_MASK (0x2000U) +#define MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_SHIFT (13U) +#define MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_SHIFT) & MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_MASK) +#define MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_MASK) >> MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_SHIFT) + +/* + * INI_DELTA_POS_CMD_MSK (RW) + * + * 1: change + * 0: won't change + * bit 3: for delta accel + * bit 2: for delta speed + * bit 1: for delta revolution + * bit 0: for delta position + */ +#define MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_MASK (0x1E00U) +#define MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_SHIFT (9U) +#define MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_SHIFT) & MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_MASK) +#define MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_MASK) >> MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_SHIFT) + +/* + * INI_DELTA_POS_REQ (RW) + * + * 1: Command to reload the delta pos. Auto clear + * 0: + */ +#define MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_MASK (0x100U) +#define MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_SHIFT (8U) +#define MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_SHIFT) & MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_MASK) +#define MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_MASK) >> MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_SHIFT) + +/* + * OPEN_LOOP_MODE (RW) + * + * 1: in open loop mode + * 0: not in open loop mode + */ +#define MMC_BR_BR_CTRL_OPEN_LOOP_MODE_MASK (0x80U) +#define MMC_BR_BR_CTRL_OPEN_LOOP_MODE_SHIFT (7U) +#define MMC_BR_BR_CTRL_OPEN_LOOP_MODE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_OPEN_LOOP_MODE_SHIFT) & MMC_BR_BR_CTRL_OPEN_LOOP_MODE_MASK) +#define MMC_BR_BR_CTRL_OPEN_LOOP_MODE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_OPEN_LOOP_MODE_MASK) >> MMC_BR_BR_CTRL_OPEN_LOOP_MODE_SHIFT) + +/* + * PRED_MODE (RW) + * + * 1:continuously repeat pred, + * 0:cal the pred based on a definite time-stamp offset, + * 2:programed one-shot prediction mode + */ +#define MMC_BR_BR_CTRL_PRED_MODE_MASK (0x30U) +#define MMC_BR_BR_CTRL_PRED_MODE_SHIFT (4U) +#define MMC_BR_BR_CTRL_PRED_MODE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_PRED_MODE_SHIFT) & MMC_BR_BR_CTRL_PRED_MODE_MASK) +#define MMC_BR_BR_CTRL_PRED_MODE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_PRED_MODE_MASK) >> MMC_BR_BR_CTRL_PRED_MODE_SHIFT) + +/* + * NF_TRG_TYPE (RW) + * + * 1. Each non-first trigger by external trigger pin + * 0. Each non-first trigger by the timer + */ +#define MMC_BR_BR_CTRL_NF_TRG_TYPE_MASK (0x4U) +#define MMC_BR_BR_CTRL_NF_TRG_TYPE_SHIFT (2U) +#define MMC_BR_BR_CTRL_NF_TRG_TYPE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_NF_TRG_TYPE_SHIFT) & MMC_BR_BR_CTRL_NF_TRG_TYPE_MASK) +#define MMC_BR_BR_CTRL_NF_TRG_TYPE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_NF_TRG_TYPE_MASK) >> MMC_BR_BR_CTRL_NF_TRG_TYPE_SHIFT) + +/* + * F_TRG_TYPE (RW) + * + * 1. First trigger by external trigger pin + * 0. First trigger by the timer + * When in CR[MANUAL_IO]=1 mode, it is the prediction trigger + */ +#define MMC_BR_BR_CTRL_F_TRG_TYPE_MASK (0x2U) +#define MMC_BR_BR_CTRL_F_TRG_TYPE_SHIFT (1U) +#define MMC_BR_BR_CTRL_F_TRG_TYPE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_F_TRG_TYPE_SHIFT) & MMC_BR_BR_CTRL_F_TRG_TYPE_MASK) +#define MMC_BR_BR_CTRL_F_TRG_TYPE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_F_TRG_TYPE_MASK) >> MMC_BR_BR_CTRL_F_TRG_TYPE_SHIFT) + +/* + * BR_EN (RW) + * + * Branch Enable + */ +#define MMC_BR_BR_CTRL_BR_EN_MASK (0x1U) +#define MMC_BR_BR_CTRL_BR_EN_SHIFT (0U) +#define MMC_BR_BR_CTRL_BR_EN_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_BR_EN_SHIFT) & MMC_BR_BR_CTRL_BR_EN_MASK) +#define MMC_BR_BR_CTRL_BR_EN_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_BR_EN_MASK) >> MMC_BR_BR_CTRL_BR_EN_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_TIMEOFF */ +/* + * VAL (RW) + * + * ufix<32, 0> time offset incycles from the trigger time + */ +#define MMC_BR_BR_TIMEOFF_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_TIMEOFF_VAL_SHIFT (0U) +#define MMC_BR_BR_TIMEOFF_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_TIMEOFF_VAL_SHIFT) & MMC_BR_BR_TIMEOFF_VAL_MASK) +#define MMC_BR_BR_TIMEOFF_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_TIMEOFF_VAL_MASK) >> MMC_BR_BR_TIMEOFF_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_TRG_PERIOD */ +/* + * VAL (RW) + * + * uifx<32, 0>, time offset incycles between each trigger time + */ +#define MMC_BR_BR_TRG_PERIOD_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_TRG_PERIOD_VAL_SHIFT (0U) +#define MMC_BR_BR_TRG_PERIOD_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_PERIOD_VAL_SHIFT) & MMC_BR_BR_TRG_PERIOD_VAL_MASK) +#define MMC_BR_BR_TRG_PERIOD_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_PERIOD_VAL_MASK) >> MMC_BR_BR_TRG_PERIOD_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_TRG_F_TIME */ +/* + * VAL (RW) + * + * uifx<32, 0> the time for the first trigger + */ +#define MMC_BR_BR_TRG_F_TIME_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_TRG_F_TIME_VAL_SHIFT (0U) +#define MMC_BR_BR_TRG_F_TIME_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_F_TIME_VAL_SHIFT) & MMC_BR_BR_TRG_F_TIME_VAL_MASK) +#define MMC_BR_BR_TRG_F_TIME_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_F_TIME_VAL_MASK) >> MMC_BR_BR_TRG_F_TIME_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_ST */ +/* + * OPEN_LOOP_ST (RO) + * + * 1：in open loop mode + * 0：in closed loop mode + */ +#define MMC_BR_BR_ST_OPEN_LOOP_ST_MASK (0x400U) +#define MMC_BR_BR_ST_OPEN_LOOP_ST_SHIFT (10U) +#define MMC_BR_BR_ST_OPEN_LOOP_ST_GET(x) (((uint32_t)(x) & MMC_BR_BR_ST_OPEN_LOOP_ST_MASK) >> MMC_BR_BR_ST_OPEN_LOOP_ST_SHIFT) + +/* + * SPEED_TRG_VLD (W1C) + * + * 1：self speed trigger event found + * 0：self speed trigger event not found yet + */ +#define MMC_BR_BR_ST_SPEED_TRG_VLD_MASK (0x200U) +#define MMC_BR_BR_ST_SPEED_TRG_VLD_SHIFT (9U) +#define MMC_BR_BR_ST_SPEED_TRG_VLD_SET(x) (((uint32_t)(x) << MMC_BR_BR_ST_SPEED_TRG_VLD_SHIFT) & MMC_BR_BR_ST_SPEED_TRG_VLD_MASK) +#define MMC_BR_BR_ST_SPEED_TRG_VLD_GET(x) (((uint32_t)(x) & MMC_BR_BR_ST_SPEED_TRG_VLD_MASK) >> MMC_BR_BR_ST_SPEED_TRG_VLD_SHIFT) + +/* + * POS_TRG_VLD (W1C) + * + * 1：self position trigger event found + * 0：self position trigger event not found yet + */ +#define MMC_BR_BR_ST_POS_TRG_VLD_MASK (0x100U) +#define MMC_BR_BR_ST_POS_TRG_VLD_SHIFT (8U) +#define MMC_BR_BR_ST_POS_TRG_VLD_SET(x) (((uint32_t)(x) << MMC_BR_BR_ST_POS_TRG_VLD_SHIFT) & MMC_BR_BR_ST_POS_TRG_VLD_MASK) +#define MMC_BR_BR_ST_POS_TRG_VLD_GET(x) (((uint32_t)(x) & MMC_BR_BR_ST_POS_TRG_VLD_MASK) >> MMC_BR_BR_ST_POS_TRG_VLD_SHIFT) + +/* + * INI_DELTA_POS_DONE (W1C) + * + * 1: the initialization of delta position command is done + * 0: the initialization of delta position command is not done + */ +#define MMC_BR_BR_ST_INI_DELTA_POS_DONE_MASK (0x40U) +#define MMC_BR_BR_ST_INI_DELTA_POS_DONE_SHIFT (6U) +#define MMC_BR_BR_ST_INI_DELTA_POS_DONE_SET(x) (((uint32_t)(x) << MMC_BR_BR_ST_INI_DELTA_POS_DONE_SHIFT) & MMC_BR_BR_ST_INI_DELTA_POS_DONE_MASK) +#define MMC_BR_BR_ST_INI_DELTA_POS_DONE_GET(x) (((uint32_t)(x) & MMC_BR_BR_ST_INI_DELTA_POS_DONE_MASK) >> MMC_BR_BR_ST_INI_DELTA_POS_DONE_SHIFT) + +/* + * IDLE (RO) + * + * 1: The prediction module is idle. + * 0: The prediction module is not idle. + */ +#define MMC_BR_BR_ST_IDLE_MASK (0x20U) +#define MMC_BR_BR_ST_IDLE_SHIFT (5U) +#define MMC_BR_BR_ST_IDLE_GET(x) (((uint32_t)(x) & MMC_BR_BR_ST_IDLE_MASK) >> MMC_BR_BR_ST_IDLE_SHIFT) + +/* + * ERR_ID (RO) + * + * The module's error ID output + */ +#define MMC_BR_BR_ST_ERR_ID_MASK (0xFU) +#define MMC_BR_BR_ST_ERR_ID_SHIFT (0U) +#define MMC_BR_BR_ST_ERR_ID_GET(x) (((uint32_t)(x) & MMC_BR_BR_ST_ERR_ID_MASK) >> MMC_BR_BR_ST_ERR_ID_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_TRG_POS_CFG */ +/* + * EDGE (RW) + * + * bit1: 0: (rising edge) pos inc greater than, 1: (falling edge) pos dec less than + */ +#define MMC_BR_BR_TRG_POS_CFG_EDGE_MASK (0x2U) +#define MMC_BR_BR_TRG_POS_CFG_EDGE_SHIFT (1U) +#define MMC_BR_BR_TRG_POS_CFG_EDGE_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_POS_CFG_EDGE_SHIFT) & MMC_BR_BR_TRG_POS_CFG_EDGE_MASK) +#define MMC_BR_BR_TRG_POS_CFG_EDGE_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_POS_CFG_EDGE_MASK) >> MMC_BR_BR_TRG_POS_CFG_EDGE_SHIFT) + +/* + * EN (RW) + * + * 1-trigger valid; 0-Trigger not valid + */ +#define MMC_BR_BR_TRG_POS_CFG_EN_MASK (0x1U) +#define MMC_BR_BR_TRG_POS_CFG_EN_SHIFT (0U) +#define MMC_BR_BR_TRG_POS_CFG_EN_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_POS_CFG_EN_SHIFT) & MMC_BR_BR_TRG_POS_CFG_EN_MASK) +#define MMC_BR_BR_TRG_POS_CFG_EN_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_POS_CFG_EN_MASK) >> MMC_BR_BR_TRG_POS_CFG_EN_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_TRG_POS_THR */ +/* + * VAL (RW) + * + * For pos out trigger (pos). + * ufix<32, 32> + */ +#define MMC_BR_BR_TRG_POS_THR_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_TRG_POS_THR_VAL_SHIFT (0U) +#define MMC_BR_BR_TRG_POS_THR_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_POS_THR_VAL_SHIFT) & MMC_BR_BR_TRG_POS_THR_VAL_MASK) +#define MMC_BR_BR_TRG_POS_THR_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_POS_THR_VAL_MASK) >> MMC_BR_BR_TRG_POS_THR_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_TRG_REV_THR */ +/* + * VAL (RW) + * + * For pos out trigger (rev) + * ufix<32, 0> + */ +#define MMC_BR_BR_TRG_REV_THR_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_TRG_REV_THR_VAL_SHIFT (0U) +#define MMC_BR_BR_TRG_REV_THR_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_REV_THR_VAL_SHIFT) & MMC_BR_BR_TRG_REV_THR_VAL_MASK) +#define MMC_BR_BR_TRG_REV_THR_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_REV_THR_VAL_MASK) >> MMC_BR_BR_TRG_REV_THR_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_TRG_SPEED_CFG */ +/* + * COMP_TYPE (RW) + * + * Use abs value for comparion. 0: Use the speed with direction info (so not the abs value) + */ +#define MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_MASK (0x4U) +#define MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_SHIFT (2U) +#define MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_SHIFT) & MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_MASK) +#define MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_MASK) >> MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_SHIFT) + +/* + * EDGE_SEL (RW) + * + * 0: (rising edge) speed inc greater than, 1: (falling edge) speed dec less than + */ +#define MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_MASK (0x2U) +#define MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_SHIFT (1U) +#define MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_SHIFT) & MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_MASK) +#define MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_MASK) >> MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_SHIFT) + +/* + * EN (RW) + * + * 1-trigger valid; 0-Trigger not valid + * Normally it means either the max pos speed, or the min negative speed. + */ +#define MMC_BR_BR_TRG_SPEED_CFG_EN_MASK (0x1U) +#define MMC_BR_BR_TRG_SPEED_CFG_EN_SHIFT (0U) +#define MMC_BR_BR_TRG_SPEED_CFG_EN_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_SPEED_CFG_EN_SHIFT) & MMC_BR_BR_TRG_SPEED_CFG_EN_MASK) +#define MMC_BR_BR_TRG_SPEED_CFG_EN_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_SPEED_CFG_EN_MASK) >> MMC_BR_BR_TRG_SPEED_CFG_EN_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_TRG_SPEED_THR */ +/* + * VAL (RW) + * + * For speed trigger. + * continuous mode: fix<32, 19> + */ +#define MMC_BR_BR_TRG_SPEED_THR_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_TRG_SPEED_THR_VAL_SHIFT (0U) +#define MMC_BR_BR_TRG_SPEED_THR_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_SPEED_THR_VAL_SHIFT) & MMC_BR_BR_TRG_SPEED_THR_VAL_MASK) +#define MMC_BR_BR_TRG_SPEED_THR_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_SPEED_THR_VAL_MASK) >> MMC_BR_BR_TRG_SPEED_THR_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_INI_POS_TIME */ +/* + * VAL (RW) + * + * indicate the time to change the values. + * 0: instant change + */ +#define MMC_BR_BR_INI_POS_TIME_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_INI_POS_TIME_VAL_SHIFT (0U) +#define MMC_BR_BR_INI_POS_TIME_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_POS_TIME_VAL_SHIFT) & MMC_BR_BR_INI_POS_TIME_VAL_MASK) +#define MMC_BR_BR_INI_POS_TIME_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_POS_TIME_VAL_MASK) >> MMC_BR_BR_INI_POS_TIME_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_INI_POS */ +/* + * VAL (RW) + * + * the value + * ufix<32, 32> + */ +#define MMC_BR_BR_INI_POS_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_INI_POS_VAL_SHIFT (0U) +#define MMC_BR_BR_INI_POS_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_POS_VAL_SHIFT) & MMC_BR_BR_INI_POS_VAL_MASK) +#define MMC_BR_BR_INI_POS_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_POS_VAL_MASK) >> MMC_BR_BR_INI_POS_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_INI_REV */ +/* + * VAL (RW) + * + * the value + * ufix<32, 0> + */ +#define MMC_BR_BR_INI_REV_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_INI_REV_VAL_SHIFT (0U) +#define MMC_BR_BR_INI_REV_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_REV_VAL_SHIFT) & MMC_BR_BR_INI_REV_VAL_MASK) +#define MMC_BR_BR_INI_REV_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_REV_VAL_MASK) >> MMC_BR_BR_INI_REV_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_INI_SPEED */ +/* + * VAL (RW) + * + * the value + * fix<32, 19> + */ +#define MMC_BR_BR_INI_SPEED_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_INI_SPEED_VAL_SHIFT (0U) +#define MMC_BR_BR_INI_SPEED_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_SPEED_VAL_SHIFT) & MMC_BR_BR_INI_SPEED_VAL_MASK) +#define MMC_BR_BR_INI_SPEED_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_SPEED_VAL_MASK) >> MMC_BR_BR_INI_SPEED_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_INI_ACCEL */ +/* + * VAL (RW) + * + * the value + * continuous mode: fix<32, 19> + */ +#define MMC_BR_BR_INI_ACCEL_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_INI_ACCEL_VAL_SHIFT (0U) +#define MMC_BR_BR_INI_ACCEL_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_ACCEL_VAL_SHIFT) & MMC_BR_BR_INI_ACCEL_VAL_MASK) +#define MMC_BR_BR_INI_ACCEL_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_ACCEL_VAL_MASK) >> MMC_BR_BR_INI_ACCEL_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_INI_DELTA_POS_TIME */ +/* + * VAL (RW) + * + * indicate the time to change the values. + * 0: instant change + */ +#define MMC_BR_BR_INI_DELTA_POS_TIME_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_INI_DELTA_POS_TIME_VAL_SHIFT (0U) +#define MMC_BR_BR_INI_DELTA_POS_TIME_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_DELTA_POS_TIME_VAL_SHIFT) & MMC_BR_BR_INI_DELTA_POS_TIME_VAL_MASK) +#define MMC_BR_BR_INI_DELTA_POS_TIME_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_DELTA_POS_TIME_VAL_MASK) >> MMC_BR_BR_INI_DELTA_POS_TIME_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_INI_DELTA_POS */ +/* + * VAL (RW) + * + * the value + * continuous mode: ufix<32, 32> + */ +#define MMC_BR_BR_INI_DELTA_POS_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_INI_DELTA_POS_VAL_SHIFT (0U) +#define MMC_BR_BR_INI_DELTA_POS_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_DELTA_POS_VAL_SHIFT) & MMC_BR_BR_INI_DELTA_POS_VAL_MASK) +#define MMC_BR_BR_INI_DELTA_POS_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_DELTA_POS_VAL_MASK) >> MMC_BR_BR_INI_DELTA_POS_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_INI_DELTA_REV */ +/* + * VAL (RW) + * + * the value + * continuous mode: fix<32, 0> + */ +#define MMC_BR_BR_INI_DELTA_REV_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_INI_DELTA_REV_VAL_SHIFT (0U) +#define MMC_BR_BR_INI_DELTA_REV_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_DELTA_REV_VAL_SHIFT) & MMC_BR_BR_INI_DELTA_REV_VAL_MASK) +#define MMC_BR_BR_INI_DELTA_REV_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_DELTA_REV_VAL_MASK) >> MMC_BR_BR_INI_DELTA_REV_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_INI_DELTA_SPEED */ +/* + * VAL (RW) + * + * the value + * continuous mode: fix<32, 19> + */ +#define MMC_BR_BR_INI_DELTA_SPEED_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_INI_DELTA_SPEED_VAL_SHIFT (0U) +#define MMC_BR_BR_INI_DELTA_SPEED_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_DELTA_SPEED_VAL_SHIFT) & MMC_BR_BR_INI_DELTA_SPEED_VAL_MASK) +#define MMC_BR_BR_INI_DELTA_SPEED_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_DELTA_SPEED_VAL_MASK) >> MMC_BR_BR_INI_DELTA_SPEED_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_INI_DELTA_ACCEL */ +/* + * VAL (RW) + * + * the value + * continuous mode: fix<32, 19> + */ +#define MMC_BR_BR_INI_DELTA_ACCEL_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_INI_DELTA_ACCEL_VAL_SHIFT (0U) +#define MMC_BR_BR_INI_DELTA_ACCEL_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_DELTA_ACCEL_VAL_SHIFT) & MMC_BR_BR_INI_DELTA_ACCEL_VAL_MASK) +#define MMC_BR_BR_INI_DELTA_ACCEL_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_DELTA_ACCEL_VAL_MASK) >> MMC_BR_BR_INI_DELTA_ACCEL_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_CUR_POS_TIME */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_BR_BR_CUR_POS_TIME_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_CUR_POS_TIME_VAL_SHIFT (0U) +#define MMC_BR_BR_CUR_POS_TIME_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_CUR_POS_TIME_VAL_MASK) >> MMC_BR_BR_CUR_POS_TIME_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_CUR_POS */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_BR_BR_CUR_POS_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_CUR_POS_VAL_SHIFT (0U) +#define MMC_BR_BR_CUR_POS_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_CUR_POS_VAL_MASK) >> MMC_BR_BR_CUR_POS_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_CUR_REV */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_BR_BR_CUR_REV_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_CUR_REV_VAL_SHIFT (0U) +#define MMC_BR_BR_CUR_REV_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_CUR_REV_VAL_MASK) >> MMC_BR_BR_CUR_REV_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_CUR_SPEED */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_BR_BR_CUR_SPEED_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_CUR_SPEED_VAL_SHIFT (0U) +#define MMC_BR_BR_CUR_SPEED_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_CUR_SPEED_VAL_MASK) >> MMC_BR_BR_CUR_SPEED_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_CUR_ACCEL */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_BR_BR_CUR_ACCEL_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_CUR_ACCEL_VAL_SHIFT (0U) +#define MMC_BR_BR_CUR_ACCEL_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_CUR_ACCEL_VAL_MASK) >> MMC_BR_BR_CUR_ACCEL_VAL_SHIFT) + +/* Bitfield definition for register: BK0_TIMESTAMP */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_BK0_TIMESTAMP_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BK0_TIMESTAMP_VAL_SHIFT (0U) +#define MMC_BK0_TIMESTAMP_VAL_GET(x) (((uint32_t)(x) & MMC_BK0_TIMESTAMP_VAL_MASK) >> MMC_BK0_TIMESTAMP_VAL_SHIFT) + +/* Bitfield definition for register: BK0_POSITION */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_BK0_POSITION_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BK0_POSITION_VAL_SHIFT (0U) +#define MMC_BK0_POSITION_VAL_GET(x) (((uint32_t)(x) & MMC_BK0_POSITION_VAL_MASK) >> MMC_BK0_POSITION_VAL_SHIFT) + +/* Bitfield definition for register: BK0_REVOLUTION */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_BK0_REVOLUTION_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BK0_REVOLUTION_VAL_SHIFT (0U) +#define MMC_BK0_REVOLUTION_VAL_GET(x) (((uint32_t)(x) & MMC_BK0_REVOLUTION_VAL_MASK) >> MMC_BK0_REVOLUTION_VAL_SHIFT) + +/* Bitfield definition for register: BK0_SPEED */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_BK0_SPEED_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BK0_SPEED_VAL_SHIFT (0U) +#define MMC_BK0_SPEED_VAL_GET(x) (((uint32_t)(x) & MMC_BK0_SPEED_VAL_MASK) >> MMC_BK0_SPEED_VAL_SHIFT) + +/* Bitfield definition for register: BK0_ACCELERATOR */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_BK0_ACCELERATOR_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BK0_ACCELERATOR_VAL_SHIFT (0U) +#define MMC_BK0_ACCELERATOR_VAL_GET(x) (((uint32_t)(x) & MMC_BK0_ACCELERATOR_VAL_MASK) >> MMC_BK0_ACCELERATOR_VAL_SHIFT) + +/* Bitfield definition for register: BK1_TIMESTAMP */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_BK1_TIMESTAMP_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BK1_TIMESTAMP_VAL_SHIFT (0U) +#define MMC_BK1_TIMESTAMP_VAL_GET(x) (((uint32_t)(x) & MMC_BK1_TIMESTAMP_VAL_MASK) >> MMC_BK1_TIMESTAMP_VAL_SHIFT) + +/* Bitfield definition for register: BK1_POSITION */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_BK1_POSITION_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BK1_POSITION_VAL_SHIFT (0U) +#define MMC_BK1_POSITION_VAL_GET(x) (((uint32_t)(x) & MMC_BK1_POSITION_VAL_MASK) >> MMC_BK1_POSITION_VAL_SHIFT) + +/* Bitfield definition for register: BK1_REVOLUTION */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_BK1_REVOLUTION_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BK1_REVOLUTION_VAL_SHIFT (0U) +#define MMC_BK1_REVOLUTION_VAL_GET(x) (((uint32_t)(x) & MMC_BK1_REVOLUTION_VAL_MASK) >> MMC_BK1_REVOLUTION_VAL_SHIFT) + +/* Bitfield definition for register: BK1_SPEED */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_BK1_SPEED_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BK1_SPEED_VAL_SHIFT (0U) +#define MMC_BK1_SPEED_VAL_GET(x) (((uint32_t)(x) & MMC_BK1_SPEED_VAL_MASK) >> MMC_BK1_SPEED_VAL_SHIFT) + +/* Bitfield definition for register: BK1_ACCELERATOR */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_BK1_ACCELERATOR_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BK1_ACCELERATOR_VAL_SHIFT (0U) +#define MMC_BK1_ACCELERATOR_VAL_GET(x) (((uint32_t)(x) & MMC_BK1_ACCELERATOR_VAL_MASK) >> MMC_BK1_ACCELERATOR_VAL_SHIFT) + + + +/* COEF_TRG_CFG register group index macro definition */ +#define MMC_COEF_TRG_CFG_0 (0UL) +#define MMC_COEF_TRG_CFG_1 (1UL) +#define MMC_COEF_TRG_CFG_2 (2UL) + +/* BR register group index macro definition */ +#define MMC_BR_0 (0UL) +#define MMC_BR_1 (1UL) + + +#endif /* HPM_MMC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mon_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mon_regs.h index 694060dbcc3..dade4024abb 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mon_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mon_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -14,8 +14,7 @@ typedef struct { __RW uint32_t CONTROL; /* 0x0: Glitch and clock monitor control */ __RW uint32_t STATUS; /* 0x4: Glitch and clock monitor status */ } MONITOR[4]; - __RW uint32_t TEST_MODE; /* 0x20: */ - __R uint8_t RESERVED0[28]; /* 0x24 - 0x3F: Reserved */ + __R uint8_t RESERVED0[32]; /* 0x20 - 0x3F: Reserved */ __RW uint32_t IRQ_FLAG; /* 0x40: */ __RW uint32_t IRQ_ENABLE; /* 0x44: */ } MON_Type; @@ -59,28 +58,13 @@ typedef struct { #define MON_MONITOR_STATUS_FLAG_SET(x) (((uint32_t)(x) << MON_MONITOR_STATUS_FLAG_SHIFT) & MON_MONITOR_STATUS_FLAG_MASK) #define MON_MONITOR_STATUS_FLAG_GET(x) (((uint32_t)(x) & MON_MONITOR_STATUS_FLAG_MASK) >> MON_MONITOR_STATUS_FLAG_SHIFT) -/* Bitfield definition for register: TEST_MODE */ -/* - * DISABLE (RW) - * - * disable test mode entry, any non-zero value written to this register causes disable bit set - * 0: test mode enabled - * 1: test mode disabled - * Note: This register only available in BATT domain - */ -#define MON_TEST_MODE_DISABLE_MASK (0xFFFFFFFFUL) -#define MON_TEST_MODE_DISABLE_SHIFT (0U) -#define MON_TEST_MODE_DISABLE_SET(x) (((uint32_t)(x) << MON_TEST_MODE_DISABLE_SHIFT) & MON_TEST_MODE_DISABLE_MASK) -#define MON_TEST_MODE_DISABLE_GET(x) (((uint32_t)(x) & MON_TEST_MODE_DISABLE_MASK) >> MON_TEST_MODE_DISABLE_SHIFT) - /* Bitfield definition for register: IRQ_FLAG */ /* * FLAG (RW) * * interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag - * 0: no monitor interrupt + * 0: no monitor interrupt * 1: monitor interrupt happened - * Note: This register only available in PMIC domain */ #define MON_IRQ_FLAG_FLAG_MASK (0xFU) #define MON_IRQ_FLAG_FLAG_SHIFT (0U) @@ -94,7 +78,6 @@ typedef struct { * interrupt enable, each bit represents for one monitor * 0: monitor interrupt disabled * 1: monitor interrupt enabled - * Note: This register only available in PMIC domain */ #define MON_IRQ_ENABLE_ENABLE_MASK (0xFU) #define MON_IRQ_ENABLE_ENABLE_SHIFT (0U) diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mono_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mono_regs.h index 12b9a5c9fb0..1be0e78aa9a 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mono_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mono_regs.h @@ -15,39 +15,16 @@ typedef struct { } MONO_Type; -/* Bitfield definition for register: MONOL */ +/* Bitfield definition for register: MONO */ /* * COUNTER (RW) * - * low part of monotonica counter, write to this counter will cause counter increase by 1 + * 32 bits of monotonica counter, write to this counter will cause counter increase by 1 */ -#define MONO_MONOL_COUNTER_MASK (0xFFFFFFFFUL) -#define MONO_MONOL_COUNTER_SHIFT (0U) -#define MONO_MONOL_COUNTER_SET(x) (((uint32_t)(x) << MONO_MONOL_COUNTER_SHIFT) & MONO_MONOL_COUNTER_MASK) -#define MONO_MONOL_COUNTER_GET(x) (((uint32_t)(x) & MONO_MONOL_COUNTER_MASK) >> MONO_MONOL_COUNTER_SHIFT) - -/* Bitfield definition for register: MONOH */ -/* - * EPOCH (RW) - * - * Fuse value for high part of monotonica - */ -#define MONO_MONOH_EPOCH_MASK (0xFFFF0000UL) -#define MONO_MONOH_EPOCH_SHIFT (16U) -#define MONO_MONOH_EPOCH_SET(x) (((uint32_t)(x) << MONO_MONOH_EPOCH_SHIFT) & MONO_MONOH_EPOCH_MASK) -#define MONO_MONOH_EPOCH_GET(x) (((uint32_t)(x) & MONO_MONOH_EPOCH_MASK) >> MONO_MONOH_EPOCH_SHIFT) - -/* - * COUNTER (RW) - * - * high part of monotonica counter, write to this counter will cause counter increase by 1 if low part overflow - */ -#define MONO_MONOH_COUNTER_MASK (0xFFFFU) -#define MONO_MONOH_COUNTER_SHIFT (0U) -#define MONO_MONOH_COUNTER_SET(x) (((uint32_t)(x) << MONO_MONOH_COUNTER_SHIFT) & MONO_MONOH_COUNTER_MASK) -#define MONO_MONOH_COUNTER_GET(x) (((uint32_t)(x) & MONO_MONOH_COUNTER_MASK) >> MONO_MONOH_COUNTER_SHIFT) - - +#define MONO_COUNTER_MASK (0xFFFFFFFFUL) +#define MONO_COUNTER_SHIFT (0U) +#define MONO_COUNTER_SET(x) (((uint32_t)(x) << MONO_COUNTER_SHIFT) & MONO_COUNTER_MASK) +#define MONO_COUNTER_GET(x) (((uint32_t)(x) & MONO_COUNTER_MASK) >> MONO_COUNTER_SHIFT) #endif /* HPM_MONO_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_opamp_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_opamp_regs.h new file mode 100644 index 00000000000..cb3a9e4c291 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_opamp_regs.h @@ -0,0 +1,258 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_OPAMP_H +#define HPM_OPAMP_H + +typedef struct { + __RW uint32_t CTRL0; /* 0x0: control reg */ + __RW uint32_t STATUS; /* 0x4: status reg */ + __RW uint32_t CTRL1; /* 0x8: control reg1 */ + __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ + struct { + __RW uint32_t CFG0; /* 0x10: */ + __RW uint32_t CFG1; /* 0x14: */ + __RW uint32_t CFG2; /* 0x18: */ + } CFG[10]; +} OPAMP_Type; + + +/* Bitfield definition for register: CTRL0 */ +/* + * EN_LV (RW) + * + */ +#define OPAMP_CTRL0_EN_LV_MASK (0x4000000UL) +#define OPAMP_CTRL0_EN_LV_SHIFT (26U) +#define OPAMP_CTRL0_EN_LV_SET(x) (((uint32_t)(x) << OPAMP_CTRL0_EN_LV_SHIFT) & OPAMP_CTRL0_EN_LV_MASK) +#define OPAMP_CTRL0_EN_LV_GET(x) (((uint32_t)(x) & OPAMP_CTRL0_EN_LV_MASK) >> OPAMP_CTRL0_EN_LV_SHIFT) + +/* + * VIM_SEL (RW) + * + */ +#define OPAMP_CTRL0_VIM_SEL_MASK (0x70000UL) +#define OPAMP_CTRL0_VIM_SEL_SHIFT (16U) +#define OPAMP_CTRL0_VIM_SEL_SET(x) (((uint32_t)(x) << OPAMP_CTRL0_VIM_SEL_SHIFT) & OPAMP_CTRL0_VIM_SEL_MASK) +#define OPAMP_CTRL0_VIM_SEL_GET(x) (((uint32_t)(x) & OPAMP_CTRL0_VIM_SEL_MASK) >> OPAMP_CTRL0_VIM_SEL_SHIFT) + +/* + * MODE (RW) + * + */ +#define OPAMP_CTRL0_MODE_MASK (0xF800U) +#define OPAMP_CTRL0_MODE_SHIFT (11U) +#define OPAMP_CTRL0_MODE_SET(x) (((uint32_t)(x) << OPAMP_CTRL0_MODE_SHIFT) & OPAMP_CTRL0_MODE_MASK) +#define OPAMP_CTRL0_MODE_GET(x) (((uint32_t)(x) & OPAMP_CTRL0_MODE_MASK) >> OPAMP_CTRL0_MODE_SHIFT) + +/* + * GAIN_SEL (RW) + * + */ +#define OPAMP_CTRL0_GAIN_SEL_MASK (0x700U) +#define OPAMP_CTRL0_GAIN_SEL_SHIFT (8U) +#define OPAMP_CTRL0_GAIN_SEL_SET(x) (((uint32_t)(x) << OPAMP_CTRL0_GAIN_SEL_SHIFT) & OPAMP_CTRL0_GAIN_SEL_MASK) +#define OPAMP_CTRL0_GAIN_SEL_GET(x) (((uint32_t)(x) & OPAMP_CTRL0_GAIN_SEL_MASK) >> OPAMP_CTRL0_GAIN_SEL_SHIFT) + +/* + * DISABLE_PM_CAP (RW) + * + */ +#define OPAMP_CTRL0_DISABLE_PM_CAP_MASK (0x80U) +#define OPAMP_CTRL0_DISABLE_PM_CAP_SHIFT (7U) +#define OPAMP_CTRL0_DISABLE_PM_CAP_SET(x) (((uint32_t)(x) << OPAMP_CTRL0_DISABLE_PM_CAP_SHIFT) & OPAMP_CTRL0_DISABLE_PM_CAP_MASK) +#define OPAMP_CTRL0_DISABLE_PM_CAP_GET(x) (((uint32_t)(x) & OPAMP_CTRL0_DISABLE_PM_CAP_MASK) >> OPAMP_CTRL0_DISABLE_PM_CAP_SHIFT) + +/* + * MILLER_SEL (RW) + * + */ +#define OPAMP_CTRL0_MILLER_SEL_MASK (0x70U) +#define OPAMP_CTRL0_MILLER_SEL_SHIFT (4U) +#define OPAMP_CTRL0_MILLER_SEL_SET(x) (((uint32_t)(x) << OPAMP_CTRL0_MILLER_SEL_SHIFT) & OPAMP_CTRL0_MILLER_SEL_MASK) +#define OPAMP_CTRL0_MILLER_SEL_GET(x) (((uint32_t)(x) & OPAMP_CTRL0_MILLER_SEL_MASK) >> OPAMP_CTRL0_MILLER_SEL_SHIFT) + +/* + * VBYPASS (RW) + * + */ +#define OPAMP_CTRL0_VBYPASS_MASK (0x8U) +#define OPAMP_CTRL0_VBYPASS_SHIFT (3U) +#define OPAMP_CTRL0_VBYPASS_SET(x) (((uint32_t)(x) << OPAMP_CTRL0_VBYPASS_SHIFT) & OPAMP_CTRL0_VBYPASS_MASK) +#define OPAMP_CTRL0_VBYPASS_GET(x) (((uint32_t)(x) & OPAMP_CTRL0_VBYPASS_MASK) >> OPAMP_CTRL0_VBYPASS_SHIFT) + +/* + * VIP_SEL (RW) + * + */ +#define OPAMP_CTRL0_VIP_SEL_MASK (0x7U) +#define OPAMP_CTRL0_VIP_SEL_SHIFT (0U) +#define OPAMP_CTRL0_VIP_SEL_SET(x) (((uint32_t)(x) << OPAMP_CTRL0_VIP_SEL_SHIFT) & OPAMP_CTRL0_VIP_SEL_MASK) +#define OPAMP_CTRL0_VIP_SEL_GET(x) (((uint32_t)(x) & OPAMP_CTRL0_VIP_SEL_MASK) >> OPAMP_CTRL0_VIP_SEL_SHIFT) + +/* Bitfield definition for register: STATUS */ +/* + * TRIG_CONFLICT (RWC) + * + * if more than one hardware trigger is set, will put all trigger input here; + * write any value to clear + */ +#define OPAMP_STATUS_TRIG_CONFLICT_MASK (0xFF00000UL) +#define OPAMP_STATUS_TRIG_CONFLICT_SHIFT (20U) +#define OPAMP_STATUS_TRIG_CONFLICT_SET(x) (((uint32_t)(x) << OPAMP_STATUS_TRIG_CONFLICT_SHIFT) & OPAMP_STATUS_TRIG_CONFLICT_MASK) +#define OPAMP_STATUS_TRIG_CONFLICT_GET(x) (((uint32_t)(x) & OPAMP_STATUS_TRIG_CONFLICT_MASK) >> OPAMP_STATUS_TRIG_CONFLICT_SHIFT) + +/* + * PRESET_ACT (RO) + * + * 1 for preset active; one of cur_preset is selected for OPAMP; + * 0 for no preset, OPAMP use cfg0 parameters + */ +#define OPAMP_STATUS_PRESET_ACT_MASK (0x80000UL) +#define OPAMP_STATUS_PRESET_ACT_SHIFT (19U) +#define OPAMP_STATUS_PRESET_ACT_GET(x) (((uint32_t)(x) & OPAMP_STATUS_PRESET_ACT_MASK) >> OPAMP_STATUS_PRESET_ACT_SHIFT) + +/* + * CUR_PRESET (RO) + * + * current selected preset + */ +#define OPAMP_STATUS_CUR_PRESET_MASK (0x70000UL) +#define OPAMP_STATUS_CUR_PRESET_SHIFT (16U) +#define OPAMP_STATUS_CUR_PRESET_GET(x) (((uint32_t)(x) & OPAMP_STATUS_CUR_PRESET_MASK) >> OPAMP_STATUS_CUR_PRESET_SHIFT) + +/* Bitfield definition for register: CTRL1 */ +/* + * SW_PRESET (RW) + * + * set to use preset defined by sw_sel. + * NOTE: when set, the hardware trigger will not be used + */ +#define OPAMP_CTRL1_SW_PRESET_MASK (0x80000000UL) +#define OPAMP_CTRL1_SW_PRESET_SHIFT (31U) +#define OPAMP_CTRL1_SW_PRESET_SET(x) (((uint32_t)(x) << OPAMP_CTRL1_SW_PRESET_SHIFT) & OPAMP_CTRL1_SW_PRESET_MASK) +#define OPAMP_CTRL1_SW_PRESET_GET(x) (((uint32_t)(x) & OPAMP_CTRL1_SW_PRESET_MASK) >> OPAMP_CTRL1_SW_PRESET_SHIFT) + +/* + * SW_SEL (RW) + * + */ +#define OPAMP_CTRL1_SW_SEL_MASK (0x7U) +#define OPAMP_CTRL1_SW_SEL_SHIFT (0U) +#define OPAMP_CTRL1_SW_SEL_SET(x) (((uint32_t)(x) << OPAMP_CTRL1_SW_SEL_SHIFT) & OPAMP_CTRL1_SW_SEL_MASK) +#define OPAMP_CTRL1_SW_SEL_GET(x) (((uint32_t)(x) & OPAMP_CTRL1_SW_SEL_MASK) >> OPAMP_CTRL1_SW_SEL_SHIFT) + +/* Bitfield definition for register of struct array CFG: CFG0 */ +/* + * DISABLE_PM_CAP (RW) + * + */ +#define OPAMP_CFG_CFG0_DISABLE_PM_CAP_MASK (0x8000000UL) +#define OPAMP_CFG_CFG0_DISABLE_PM_CAP_SHIFT (27U) +#define OPAMP_CFG_CFG0_DISABLE_PM_CAP_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG0_DISABLE_PM_CAP_SHIFT) & OPAMP_CFG_CFG0_DISABLE_PM_CAP_MASK) +#define OPAMP_CFG_CFG0_DISABLE_PM_CAP_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG0_DISABLE_PM_CAP_MASK) >> OPAMP_CFG_CFG0_DISABLE_PM_CAP_SHIFT) + +/* + * MILLER_SEL (RW) + * + */ +#define OPAMP_CFG_CFG0_MILLER_SEL_MASK (0x7000000UL) +#define OPAMP_CFG_CFG0_MILLER_SEL_SHIFT (24U) +#define OPAMP_CFG_CFG0_MILLER_SEL_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG0_MILLER_SEL_SHIFT) & OPAMP_CFG_CFG0_MILLER_SEL_MASK) +#define OPAMP_CFG_CFG0_MILLER_SEL_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG0_MILLER_SEL_MASK) >> OPAMP_CFG_CFG0_MILLER_SEL_SHIFT) + +/* + * VIM_SEL (RW) + * + */ +#define OPAMP_CFG_CFG0_VIM_SEL_MASK (0x700U) +#define OPAMP_CFG_CFG0_VIM_SEL_SHIFT (8U) +#define OPAMP_CFG_CFG0_VIM_SEL_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG0_VIM_SEL_SHIFT) & OPAMP_CFG_CFG0_VIM_SEL_MASK) +#define OPAMP_CFG_CFG0_VIM_SEL_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG0_VIM_SEL_MASK) >> OPAMP_CFG_CFG0_VIM_SEL_SHIFT) + +/* + * VIP_SEL (RW) + * + */ +#define OPAMP_CFG_CFG0_VIP_SEL_MASK (0x7U) +#define OPAMP_CFG_CFG0_VIP_SEL_SHIFT (0U) +#define OPAMP_CFG_CFG0_VIP_SEL_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG0_VIP_SEL_SHIFT) & OPAMP_CFG_CFG0_VIP_SEL_MASK) +#define OPAMP_CFG_CFG0_VIP_SEL_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG0_VIP_SEL_MASK) >> OPAMP_CFG_CFG0_VIP_SEL_SHIFT) + +/* Bitfield definition for register of struct array CFG: CFG1 */ +/* + * HW_TRIG_EN (RW) + * + * set to enable hardware trigger from moto system. + * NOTE: when sw_preset is enabled, this bit will not take effert + */ +#define OPAMP_CFG_CFG1_HW_TRIG_EN_MASK (0x80000000UL) +#define OPAMP_CFG_CFG1_HW_TRIG_EN_SHIFT (31U) +#define OPAMP_CFG_CFG1_HW_TRIG_EN_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG1_HW_TRIG_EN_SHIFT) & OPAMP_CFG_CFG1_HW_TRIG_EN_MASK) +#define OPAMP_CFG_CFG1_HW_TRIG_EN_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG1_HW_TRIG_EN_MASK) >> OPAMP_CFG_CFG1_HW_TRIG_EN_SHIFT) + +/* + * EN_LV (RW) + * + */ +#define OPAMP_CFG_CFG1_EN_LV_MASK (0x40000000UL) +#define OPAMP_CFG_CFG1_EN_LV_SHIFT (30U) +#define OPAMP_CFG_CFG1_EN_LV_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG1_EN_LV_SHIFT) & OPAMP_CFG_CFG1_EN_LV_MASK) +#define OPAMP_CFG_CFG1_EN_LV_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG1_EN_LV_MASK) >> OPAMP_CFG_CFG1_EN_LV_SHIFT) + +/* + * VBYPASS_LV (RW) + * + */ +#define OPAMP_CFG_CFG1_VBYPASS_LV_MASK (0x20000000UL) +#define OPAMP_CFG_CFG1_VBYPASS_LV_SHIFT (29U) +#define OPAMP_CFG_CFG1_VBYPASS_LV_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG1_VBYPASS_LV_SHIFT) & OPAMP_CFG_CFG1_VBYPASS_LV_MASK) +#define OPAMP_CFG_CFG1_VBYPASS_LV_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG1_VBYPASS_LV_MASK) >> OPAMP_CFG_CFG1_VBYPASS_LV_SHIFT) + +/* + * MODE (RW) + * + */ +#define OPAMP_CFG_CFG1_MODE_MASK (0xF8U) +#define OPAMP_CFG_CFG1_MODE_SHIFT (3U) +#define OPAMP_CFG_CFG1_MODE_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG1_MODE_SHIFT) & OPAMP_CFG_CFG1_MODE_MASK) +#define OPAMP_CFG_CFG1_MODE_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG1_MODE_MASK) >> OPAMP_CFG_CFG1_MODE_SHIFT) + +/* + * GAIN_SEL (RW) + * + */ +#define OPAMP_CFG_CFG1_GAIN_SEL_MASK (0x7U) +#define OPAMP_CFG_CFG1_GAIN_SEL_SHIFT (0U) +#define OPAMP_CFG_CFG1_GAIN_SEL_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG1_GAIN_SEL_SHIFT) & OPAMP_CFG_CFG1_GAIN_SEL_MASK) +#define OPAMP_CFG_CFG1_GAIN_SEL_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG1_GAIN_SEL_MASK) >> OPAMP_CFG_CFG1_GAIN_SEL_SHIFT) + +/* Bitfield definition for register of struct array CFG: CFG2 */ +/* + * CHANNEL (RW) + * + */ +#define OPAMP_CFG_CFG2_CHANNEL_MASK (0x7000000UL) +#define OPAMP_CFG_CFG2_CHANNEL_SHIFT (24U) +#define OPAMP_CFG_CFG2_CHANNEL_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG2_CHANNEL_SHIFT) & OPAMP_CFG_CFG2_CHANNEL_MASK) +#define OPAMP_CFG_CFG2_CHANNEL_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG2_CHANNEL_MASK) >> OPAMP_CFG_CFG2_CHANNEL_SHIFT) + + + +/* CFG register group index macro definition */ +#define OPAMP_CFG_PRESET0 (0UL) +#define OPAMP_CFG_PRESET1 (1UL) +#define OPAMP_CFG_PRESET2 (2UL) +#define OPAMP_CFG_PRESET3 (4UL) +#define OPAMP_CFG_PRESET4 (5UL) +#define OPAMP_CFG_PRESET5 (6UL) +#define OPAMP_CFG_PRESET6 (8UL) +#define OPAMP_CFG_PRESET7 (9UL) + + +#endif /* HPM_OPAMP_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pdma_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pdma_regs.h index 32de012adc5..52f0695257b 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pdma_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pdma_regs.h @@ -194,12 +194,13 @@ typedef struct { #define PDMA_STAT_BLOCKX_GET(x) (((uint32_t)(x) & PDMA_STAT_BLOCKX_MASK) >> PDMA_STAT_BLOCKX_SHIFT) /* - * PDMA_DONE (RO) + * PDMA_DONE (W1C) * * PDMA one image done */ #define PDMA_STAT_PDMA_DONE_MASK (0x200U) #define PDMA_STAT_PDMA_DONE_SHIFT (9U) +#define PDMA_STAT_PDMA_DONE_SET(x) (((uint32_t)(x) << PDMA_STAT_PDMA_DONE_SHIFT) & PDMA_STAT_PDMA_DONE_MASK) #define PDMA_STAT_PDMA_DONE_GET(x) (((uint32_t)(x) & PDMA_STAT_PDMA_DONE_MASK) >> PDMA_STAT_PDMA_DONE_SHIFT) /* @@ -242,13 +243,12 @@ typedef struct { #define PDMA_STAT_AXI_0_READ_ERR_GET(x) (((uint32_t)(x) & PDMA_STAT_AXI_0_READ_ERR_MASK) >> PDMA_STAT_AXI_0_READ_ERR_SHIFT) /* - * IRQ (W1C) + * IRQ (RO) * * Asserted to indicate a IRQ event */ #define PDMA_STAT_IRQ_MASK (0x1U) #define PDMA_STAT_IRQ_SHIFT (0U) -#define PDMA_STAT_IRQ_SET(x) (((uint32_t)(x) << PDMA_STAT_IRQ_SHIFT) & PDMA_STAT_IRQ_MASK) #define PDMA_STAT_IRQ_GET(x) (((uint32_t)(x) & PDMA_STAT_IRQ_MASK) >> PDMA_STAT_IRQ_SHIFT) /* Bitfield definition for register: OUT_CTRL */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pixelmux_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pixelmux_regs.h new file mode 100644 index 00000000000..7bd8e8d2e2f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pixelmux_regs.h @@ -0,0 +1,1860 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PIXELMUX_H +#define HPM_PIXELMUX_H + +typedef struct { + __RW uint32_t PIXMUX; /* 0x0: pixel path mux register */ + __RW uint32_t DSI_SETTING[2]; /* 0x4 - 0x8: DSI0 config register */ + __RW uint32_t MISC; /* 0xC: common register */ + __RW uint32_t GPR_WR_D0; /* 0x10: gpr write-read register 0 */ + __RW uint32_t GPR_WR_D1; /* 0x14: gpr write-read register 1 */ + __RW uint32_t GPR_WR_D2; /* 0x18: gpr write-read register 2 */ + __RW uint32_t GPR_WR_D3; /* 0x1C: gpr write-read register 3 */ + __RW uint32_t GPR_WR_D4; /* 0x20: gpr write-read register 4 */ + __RW uint32_t GPR_WR_D5; /* 0x24: gpr write-read register 5 */ + __RW uint32_t GPR_WR_D6; /* 0x28: gpr write-read register 6 */ + __RW uint32_t GPR_WR_D7; /* 0x2C: gpr write-read register 7 */ + __RW uint32_t GPR_WR_D8; /* 0x30: gpr write-read register 8 */ + __RW uint32_t GPR_WR_D9; /* 0x34: gpr write-read register 9 */ + __R uint32_t GPR_RO_D0; /* 0x38: gpr read-only register 0 */ + __R uint32_t GPR_RO_D1; /* 0x3C: gpr read-only register 1 */ + __R uint32_t GPR_RO_D2; /* 0x40: gpr read-only register 2 */ + __R uint32_t GPR_RO_D3; /* 0x44: gpr read-only register 3 */ + __R uint32_t GPR_RO_D4; /* 0x48: gpr read-only register 4 */ + __R uint32_t GPR_RO_D5; /* 0x4C: gpr read-only register 5 */ + __R uint32_t GPR_RO_D6; /* 0x50: gpr read-only register 6 */ + __R uint32_t GPR_RO_D7; /* 0x54: gpr read-only register 7 */ + __R uint32_t GPR_RO_D8; /* 0x58: gpr read-only register 8 */ + __R uint32_t GPR_RO_D9; /* 0x5C: gpr read-only register 9 */ + __RW uint32_t GPR_WR1_CLR_D0; /* 0x60: gpr write1 set/no-write clr register */ +} PIXELMUX_Type; + + +/* Bitfield definition for register: PIXMUX */ +/* + * RGB_EN (RW) + * + * RGB pixel bus enable + */ +#define PIXELMUX_PIXMUX_RGB_EN_MASK (0x20000000UL) +#define PIXELMUX_PIXMUX_RGB_EN_SHIFT (29U) +#define PIXELMUX_PIXMUX_RGB_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_RGB_EN_SHIFT) & PIXELMUX_PIXMUX_RGB_EN_MASK) +#define PIXELMUX_PIXMUX_RGB_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_RGB_EN_MASK) >> PIXELMUX_PIXMUX_RGB_EN_SHIFT) + +/* + * RGB_SEL (RW) + * + * RGB pixel bus selection + * 1: LCDC1 + * 0: LCDC0 + */ +#define PIXELMUX_PIXMUX_RGB_SEL_MASK (0x10000000UL) +#define PIXELMUX_PIXMUX_RGB_SEL_SHIFT (28U) +#define PIXELMUX_PIXMUX_RGB_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_RGB_SEL_SHIFT) & PIXELMUX_PIXMUX_RGB_SEL_MASK) +#define PIXELMUX_PIXMUX_RGB_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_RGB_SEL_MASK) >> PIXELMUX_PIXMUX_RGB_SEL_SHIFT) + +/* + * GWC1_EN (RW) + * + * GWC1 pixel bus enable + */ +#define PIXELMUX_PIXMUX_GWC1_EN_MASK (0x8000000UL) +#define PIXELMUX_PIXMUX_GWC1_EN_SHIFT (27U) +#define PIXELMUX_PIXMUX_GWC1_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_GWC1_EN_SHIFT) & PIXELMUX_PIXMUX_GWC1_EN_MASK) +#define PIXELMUX_PIXMUX_GWC1_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_GWC1_EN_MASK) >> PIXELMUX_PIXMUX_GWC1_EN_SHIFT) + +/* + * GWC1_SEL (RW) + * + * GWC1 pixel bus selection + * 1: LCDC1 + * 0: LCDC0 + */ +#define PIXELMUX_PIXMUX_GWC1_SEL_MASK (0x4000000UL) +#define PIXELMUX_PIXMUX_GWC1_SEL_SHIFT (26U) +#define PIXELMUX_PIXMUX_GWC1_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_GWC1_SEL_SHIFT) & PIXELMUX_PIXMUX_GWC1_SEL_MASK) +#define PIXELMUX_PIXMUX_GWC1_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_GWC1_SEL_MASK) >> PIXELMUX_PIXMUX_GWC1_SEL_SHIFT) + +/* + * GWC0_EN (RW) + * + * GWC0 pixel bus enable + */ +#define PIXELMUX_PIXMUX_GWC0_EN_MASK (0x2000000UL) +#define PIXELMUX_PIXMUX_GWC0_EN_SHIFT (25U) +#define PIXELMUX_PIXMUX_GWC0_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_GWC0_EN_SHIFT) & PIXELMUX_PIXMUX_GWC0_EN_MASK) +#define PIXELMUX_PIXMUX_GWC0_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_GWC0_EN_MASK) >> PIXELMUX_PIXMUX_GWC0_EN_SHIFT) + +/* + * GWC0_SEL (RW) + * + * GWC0 pixel bus selection + * 1: LCDC1 + * 0: LCDC0 + */ +#define PIXELMUX_PIXMUX_GWC0_SEL_MASK (0x1000000UL) +#define PIXELMUX_PIXMUX_GWC0_SEL_SHIFT (24U) +#define PIXELMUX_PIXMUX_GWC0_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_GWC0_SEL_SHIFT) & PIXELMUX_PIXMUX_GWC0_SEL_MASK) +#define PIXELMUX_PIXMUX_GWC0_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_GWC0_SEL_MASK) >> PIXELMUX_PIXMUX_GWC0_SEL_SHIFT) + +/* + * LVB_DI1_EN (RW) + * + * LVB DI1 pixel bus enable + */ +#define PIXELMUX_PIXMUX_LVB_DI1_EN_MASK (0x800000UL) +#define PIXELMUX_PIXMUX_LVB_DI1_EN_SHIFT (23U) +#define PIXELMUX_PIXMUX_LVB_DI1_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_LVB_DI1_EN_SHIFT) & PIXELMUX_PIXMUX_LVB_DI1_EN_MASK) +#define PIXELMUX_PIXMUX_LVB_DI1_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_LVB_DI1_EN_MASK) >> PIXELMUX_PIXMUX_LVB_DI1_EN_SHIFT) + +/* + * LVB_DI1_SEL (RW) + * + * LVB DI1 pixel bus selection + * 1: LCDC1 + * 0: LCDC0 + */ +#define PIXELMUX_PIXMUX_LVB_DI1_SEL_MASK (0x400000UL) +#define PIXELMUX_PIXMUX_LVB_DI1_SEL_SHIFT (22U) +#define PIXELMUX_PIXMUX_LVB_DI1_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_LVB_DI1_SEL_SHIFT) & PIXELMUX_PIXMUX_LVB_DI1_SEL_MASK) +#define PIXELMUX_PIXMUX_LVB_DI1_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_LVB_DI1_SEL_MASK) >> PIXELMUX_PIXMUX_LVB_DI1_SEL_SHIFT) + +/* + * LVB_DI0_EN (RW) + * + * LVB DI0 pixel bus enable + */ +#define PIXELMUX_PIXMUX_LVB_DI0_EN_MASK (0x200000UL) +#define PIXELMUX_PIXMUX_LVB_DI0_EN_SHIFT (21U) +#define PIXELMUX_PIXMUX_LVB_DI0_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_LVB_DI0_EN_SHIFT) & PIXELMUX_PIXMUX_LVB_DI0_EN_MASK) +#define PIXELMUX_PIXMUX_LVB_DI0_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_LVB_DI0_EN_MASK) >> PIXELMUX_PIXMUX_LVB_DI0_EN_SHIFT) + +/* + * LVB_DI0_SEL (RW) + * + * LVB DI0 pixel bus selection + * 1: LCDC1 + * 0: LCDC0 + */ +#define PIXELMUX_PIXMUX_LVB_DI0_SEL_MASK (0x100000UL) +#define PIXELMUX_PIXMUX_LVB_DI0_SEL_SHIFT (20U) +#define PIXELMUX_PIXMUX_LVB_DI0_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_LVB_DI0_SEL_SHIFT) & PIXELMUX_PIXMUX_LVB_DI0_SEL_MASK) +#define PIXELMUX_PIXMUX_LVB_DI0_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_LVB_DI0_SEL_MASK) >> PIXELMUX_PIXMUX_LVB_DI0_SEL_SHIFT) + +/* + * DSI1_EN (RW) + * + * DSI0 pixel bus enable + */ +#define PIXELMUX_PIXMUX_DSI1_EN_MASK (0x80000UL) +#define PIXELMUX_PIXMUX_DSI1_EN_SHIFT (19U) +#define PIXELMUX_PIXMUX_DSI1_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_DSI1_EN_SHIFT) & PIXELMUX_PIXMUX_DSI1_EN_MASK) +#define PIXELMUX_PIXMUX_DSI1_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_DSI1_EN_MASK) >> PIXELMUX_PIXMUX_DSI1_EN_SHIFT) + +/* + * DSI1_SEL (RW) + * + * DSI0 pixel bus selection + * 1: LCDC1 + * 0: LCDC0 + */ +#define PIXELMUX_PIXMUX_DSI1_SEL_MASK (0x40000UL) +#define PIXELMUX_PIXMUX_DSI1_SEL_SHIFT (18U) +#define PIXELMUX_PIXMUX_DSI1_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_DSI1_SEL_SHIFT) & PIXELMUX_PIXMUX_DSI1_SEL_MASK) +#define PIXELMUX_PIXMUX_DSI1_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_DSI1_SEL_MASK) >> PIXELMUX_PIXMUX_DSI1_SEL_SHIFT) + +/* + * DSI0_EN (RW) + * + * DSI1 pixel bus enable + */ +#define PIXELMUX_PIXMUX_DSI0_EN_MASK (0x20000UL) +#define PIXELMUX_PIXMUX_DSI0_EN_SHIFT (17U) +#define PIXELMUX_PIXMUX_DSI0_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_DSI0_EN_SHIFT) & PIXELMUX_PIXMUX_DSI0_EN_MASK) +#define PIXELMUX_PIXMUX_DSI0_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_DSI0_EN_MASK) >> PIXELMUX_PIXMUX_DSI0_EN_SHIFT) + +/* + * DSI0_SEL (RW) + * + * DSI1 pixel bus selection + * 1: LCDC1 + * 0: LCDC0 + */ +#define PIXELMUX_PIXMUX_DSI0_SEL_MASK (0x10000UL) +#define PIXELMUX_PIXMUX_DSI0_SEL_SHIFT (16U) +#define PIXELMUX_PIXMUX_DSI0_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_DSI0_SEL_SHIFT) & PIXELMUX_PIXMUX_DSI0_SEL_MASK) +#define PIXELMUX_PIXMUX_DSI0_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_DSI0_SEL_MASK) >> PIXELMUX_PIXMUX_DSI0_SEL_SHIFT) + +/* + * CAM1_EN (RW) + * + * CAM1 pixel bus enable + */ +#define PIXELMUX_PIXMUX_CAM1_EN_MASK (0x80U) +#define PIXELMUX_PIXMUX_CAM1_EN_SHIFT (7U) +#define PIXELMUX_PIXMUX_CAM1_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_CAM1_EN_SHIFT) & PIXELMUX_PIXMUX_CAM1_EN_MASK) +#define PIXELMUX_PIXMUX_CAM1_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_CAM1_EN_MASK) >> PIXELMUX_PIXMUX_CAM1_EN_SHIFT) + +/* + * CAM1_SEL (RW) + * + * CAM1 pixel bus selection + * 111: Reserved + * 110: LCB1 + * 101: LCB0 + * 100: LCDC1 + * 011: LCDC0 + * 010: CSI1 + * 001: CSI0 + * 000: DVP + */ +#define PIXELMUX_PIXMUX_CAM1_SEL_MASK (0x70U) +#define PIXELMUX_PIXMUX_CAM1_SEL_SHIFT (4U) +#define PIXELMUX_PIXMUX_CAM1_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_CAM1_SEL_SHIFT) & PIXELMUX_PIXMUX_CAM1_SEL_MASK) +#define PIXELMUX_PIXMUX_CAM1_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_CAM1_SEL_MASK) >> PIXELMUX_PIXMUX_CAM1_SEL_SHIFT) + +/* + * CAM0_EN (RW) + * + * CAM0 pixel bus enable + */ +#define PIXELMUX_PIXMUX_CAM0_EN_MASK (0x8U) +#define PIXELMUX_PIXMUX_CAM0_EN_SHIFT (3U) +#define PIXELMUX_PIXMUX_CAM0_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_CAM0_EN_SHIFT) & PIXELMUX_PIXMUX_CAM0_EN_MASK) +#define PIXELMUX_PIXMUX_CAM0_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_CAM0_EN_MASK) >> PIXELMUX_PIXMUX_CAM0_EN_SHIFT) + +/* + * CAM0_SEL (RW) + * + * CAM0 pixel bus selection + * 111: Reserved + * 110: LCB1 + * 101: LCB0 + * 100: LCDC1 + * 011: LCDC0 + * 010: CSI1 + * 001: CSI0 + * 000: DVP + */ +#define PIXELMUX_PIXMUX_CAM0_SEL_MASK (0x7U) +#define PIXELMUX_PIXMUX_CAM0_SEL_SHIFT (0U) +#define PIXELMUX_PIXMUX_CAM0_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_CAM0_SEL_SHIFT) & PIXELMUX_PIXMUX_CAM0_SEL_MASK) +#define PIXELMUX_PIXMUX_CAM0_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_CAM0_SEL_MASK) >> PIXELMUX_PIXMUX_CAM0_SEL_SHIFT) + +/* Bitfield definition for register array: DSI_SETTING */ +/* + * DSI_DATA_ENABLE (RW) + * + * DSI pixel data type enable: + * Bit0: RGB565_CFG1 + * Bit1: RGB565_CFG2 + * Bit2: RGB565_CFG3 + * Bit3: RGB666_CFG1 + * Bit4: RGB666_CFG2 + * Bit5: RGB888 + * Bit6: RGB_10BIT + * Bit7: RGB_12BIT, no support + * Bit8: YUV422_12BIT, no support + * Bit9: YUV422_10BIT, no support + * Bit10: YUV422_8BIT, no support + * Bit11:YUV420_8BIT,no support + * others: Reserved + */ +#define PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_MASK (0xFFFF0000UL) +#define PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_SHIFT (16U) +#define PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_SET(x) (((uint32_t)(x) << PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_SHIFT) & PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_MASK) +#define PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_GET(x) (((uint32_t)(x) & PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_MASK) >> PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_SHIFT) + +/* + * DSI_DATA_TYPE (RW) + * + * DSI input pixel data type: + * ‘h0: RGB565_CFG1 + * ‘h1: RGB565_CFG2 + * ‘h2: RGB565_CFG3 + * ‘h3: RGB666_CFG1 + * ‘h4: RGB666_CFG2 + * ‘h5: RGB888 + * ‘h6: RGB_10BIT + * ‘h7: RGB_12BIT, no support + * ‘h8:YUV422_12BIT,no support + * ‘h9: YUV422_10BIT, no support + * ‘ha: YUV422_8BIT, no support + * ‘hb: YUV420_8BIT,no support + * ‘hc~’hf: Reserved + */ +#define PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_MASK (0xFU) +#define PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_SHIFT (0U) +#define PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_SET(x) (((uint32_t)(x) << PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_SHIFT) & PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_MASK) +#define PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_GET(x) (((uint32_t)(x) & PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_MASK) >> PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_SHIFT) + +/* Bitfield definition for register: MISC */ +/* + * LVB_DI1_CTL (RW) + * + * LVB DI1 optional general purpose control which is usually unused by display + */ +#define PIXELMUX_MISC_LVB_DI1_CTL_MASK (0x2U) +#define PIXELMUX_MISC_LVB_DI1_CTL_SHIFT (1U) +#define PIXELMUX_MISC_LVB_DI1_CTL_SET(x) (((uint32_t)(x) << PIXELMUX_MISC_LVB_DI1_CTL_SHIFT) & PIXELMUX_MISC_LVB_DI1_CTL_MASK) +#define PIXELMUX_MISC_LVB_DI1_CTL_GET(x) (((uint32_t)(x) & PIXELMUX_MISC_LVB_DI1_CTL_MASK) >> PIXELMUX_MISC_LVB_DI1_CTL_SHIFT) + +/* + * LVB_DI0_CTL (RW) + * + * LVB DI0 optional general purpose control which is usually unused by display + */ +#define PIXELMUX_MISC_LVB_DI0_CTL_MASK (0x1U) +#define PIXELMUX_MISC_LVB_DI0_CTL_SHIFT (0U) +#define PIXELMUX_MISC_LVB_DI0_CTL_SET(x) (((uint32_t)(x) << PIXELMUX_MISC_LVB_DI0_CTL_SHIFT) & PIXELMUX_MISC_LVB_DI0_CTL_MASK) +#define PIXELMUX_MISC_LVB_DI0_CTL_GET(x) (((uint32_t)(x) & PIXELMUX_MISC_LVB_DI0_CTL_MASK) >> PIXELMUX_MISC_LVB_DI0_CTL_SHIFT) + +/* Bitfield definition for register: GPR_WR_D0 */ +/* + * CSI1_CFG_AP_IF_CHECK_EN (RW) + * + * csi1 apb interface parity check enable + */ +#define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_MASK (0x7C00000UL) +#define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_SHIFT (22U) +#define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_MASK) +#define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_SHIFT) + +/* + * CSI1_CFG_AP_IF_INT_EN (RW) + * + * csi1 apb interface error interrupt enable + */ +#define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_MASK (0x200000UL) +#define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_SHIFT (21U) +#define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_MASK) +#define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_SHIFT) + +/* + * CSI1_CFG_APB_SLVERROR_EN (RW) + * + * csi1 apb interface error check enable + */ +#define PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_MASK (0x100000UL) +#define PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_SHIFT (20U) +#define PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_MASK) +#define PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_SHIFT) + +/* + * CSI0_CFG_AP_IF_CHECK_EN (RW) + * + * csi0 apb interface parity check enable + */ +#define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_MASK (0x7C000UL) +#define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_SHIFT (14U) +#define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_MASK) +#define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_SHIFT) + +/* + * CSI0_CFG_AP_IF_INT_EN (RW) + * + * csi0 apb interface error interrupt enable + */ +#define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_MASK (0x2000U) +#define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_SHIFT (13U) +#define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_MASK) +#define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_SHIFT) + +/* + * CSI0_CFG_APB_SLVERROR_EN (RW) + * + * csi0 apb interface error check enable + */ +#define PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_MASK (0x1000U) +#define PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_SHIFT (12U) +#define PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_MASK) +#define PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_SHIFT) + +/* + * DSI1_DPIUPDATECFG (RW) + * + * dsi1 dpi update configure + */ +#define PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_MASK (0x200U) +#define PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_SHIFT (9U) +#define PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_SHIFT) & PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_MASK) +#define PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_MASK) >> PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_SHIFT) + +/* + * DSI1_DPICOLORM (RW) + * + * dsi1 dpi cholor mode control + */ +#define PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_MASK (0x100U) +#define PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_SHIFT (8U) +#define PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_SHIFT) & PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_MASK) +#define PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_MASK) >> PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_SHIFT) + +/* + * DSI1_DPISHUTDN (RW) + * + * dsi1 dpi shuntdown control + */ +#define PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_MASK (0x80U) +#define PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_SHIFT (7U) +#define PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_SHIFT) & PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_MASK) +#define PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_MASK) >> PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_SHIFT) + +/* + * DSI0_DPIUPDATECFG (RW) + * + * dsi0 dpi update configure + */ +#define PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_MASK (0x40U) +#define PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_SHIFT (6U) +#define PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_SHIFT) & PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_MASK) +#define PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_MASK) >> PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_SHIFT) + +/* + * DSI0_DPICOLORM (RW) + * + * dsi0 dpi cholor mode control + */ +#define PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_MASK (0x20U) +#define PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_SHIFT (5U) +#define PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_SHIFT) & PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_MASK) +#define PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_MASK) >> PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_SHIFT) + +/* + * DSI0_DPISHUTDN (RW) + * + * dsi0 dpi shuntdown control + */ +#define PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_MASK (0x10U) +#define PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_SHIFT (4U) +#define PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_SHIFT) & PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_MASK) +#define PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_MASK) >> PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_SHIFT) + +/* + * CSI1_SOFT_RESET_N (RW) + * + * csi controller 1 reset, active low + */ +#define PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_MASK (0x8U) +#define PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_SHIFT (3U) +#define PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_MASK) +#define PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_MASK) >> PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_SHIFT) + +/* + * CSI0_SOFT_RESET_N (RW) + * + * csi controller 0 reset, active low + */ +#define PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_MASK (0x4U) +#define PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_SHIFT (2U) +#define PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_MASK) +#define PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_MASK) >> PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_SHIFT) + +/* + * DSI1_SOFT_RESET_N (RW) + * + * dsi controller 1 reset, active low + */ +#define PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_MASK (0x2U) +#define PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_SHIFT (1U) +#define PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_MASK) +#define PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_MASK) >> PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_SHIFT) + +/* + * DSI0_SOFT_RESET_N (RW) + * + * dsi controller 0 reset, active low + */ +#define PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_MASK (0x1U) +#define PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_SHIFT (0U) +#define PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_MASK) +#define PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_MASK) >> PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_SHIFT) + +/* Bitfield definition for register: GPR_WR_D1 */ +/* + * JPEG_CTRL (RW) + * + * bit0: select cam0; + * bit1: select cam1; + * bit2: select jpeg; + * bit3: select pdma + */ +#define PIXELMUX_GPR_WR_D1_JPEG_CTRL_MASK (0xF000000UL) +#define PIXELMUX_GPR_WR_D1_JPEG_CTRL_SHIFT (24U) +#define PIXELMUX_GPR_WR_D1_JPEG_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_JPEG_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_JPEG_CTRL_MASK) +#define PIXELMUX_GPR_WR_D1_JPEG_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_JPEG_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_JPEG_CTRL_SHIFT) + +/* + * PDMA_P1_CTRL (RW) + * + * bit0: select cam0; + * bit1: select cam1; + * bit2: select jpeg; + * bit3: select pdma + */ +#define PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_MASK (0xF00000UL) +#define PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_SHIFT (20U) +#define PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_MASK) +#define PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_SHIFT) + +/* + * PDMA_P0_CTRL (RW) + * + * bit0: select cam0; + * bit1: select cam1; + * bit2: select jpeg; + * bit3: select pdma + */ +#define PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_MASK (0xF0000UL) +#define PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_SHIFT (16U) +#define PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_MASK) +#define PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_SHIFT) + +/* + * LCDC1_P1_CTRL (RW) + * + * bit0: select cam0; + * bit1: select cam1; + * bit2: select jpeg; + * bit3: select pdma + */ +#define PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_MASK (0xF000U) +#define PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_SHIFT (12U) +#define PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_MASK) +#define PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_SHIFT) + +/* + * LCDC1_P0_CTRL (RW) + * + * bit0: select cam0; + * bit1: select cam1; + * bit2: select jpeg; + * bit3: select pdma + */ +#define PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_MASK (0xF00U) +#define PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_SHIFT (8U) +#define PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_MASK) +#define PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_SHIFT) + +/* + * LCDC0_P1_CTRL (RW) + * + * bit0: select cam0; + * bit1: select cam1; + * bit2: select jpeg; + * bit3: select pdma + */ +#define PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_MASK (0xF0U) +#define PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_SHIFT (4U) +#define PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_MASK) +#define PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_SHIFT) + +/* + * LCDC0_P0_CTRL (RW) + * + * bit0: select cam0; + * bit1: select cam1; + * bit2: select jpeg; + * bit3: select pdma + */ +#define PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_MASK (0xFU) +#define PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_SHIFT (0U) +#define PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_MASK) +#define PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_SHIFT) + +/* Bitfield definition for register: GPR_WR_D2 */ +/* + * TX_PHY0_PORT_PLL_RDY_SEL (RW) + * + * tx phy0 port_pll_rdy_sel + */ +#define PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_MASK (0x20000000UL) +#define PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_SHIFT (29U) +#define PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_MASK) +#define PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_SHIFT) + +/* + * TX_PHY0_RATE_LVDS (RW) + * + * tx phy0 rate_lvds + */ +#define PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_MASK (0x18000000UL) +#define PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_SHIFT (27U) +#define PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_MASK) +#define PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_SHIFT) + +/* + * TX_PHY0_PHY_MODE (RW) + * + * tx phy0 phy_mode + */ +#define PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_MASK (0x6000000UL) +#define PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_SHIFT (25U) +#define PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_MASK) +#define PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_SHIFT) + +/* + * TX_PHY0_REFCLK_DIV (RW) + * + * tx phy0 refclk_div + */ +#define PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_MASK (0xF00000UL) +#define PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_SHIFT (20U) +#define PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_MASK) +#define PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_SHIFT) + +/* + * TX_PHY0_IDDQ_EN (RW) + * + * tx phy0 iddq_en + */ +#define PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_MASK (0x80000UL) +#define PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_SHIFT (19U) +#define PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_MASK) +#define PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_SHIFT) + +/* + * TX_PHY0_RESET_N (RW) + * + * tx phy0 reset, active low + */ +#define PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_MASK (0x40000UL) +#define PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_SHIFT (18U) +#define PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_MASK) +#define PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_SHIFT) + +/* + * TX_PHY0_SHUTDOWNZ (RW) + * + * tx phy0 shutdownz, active low + */ +#define PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_MASK (0x20000UL) +#define PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_SHIFT (17U) +#define PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_MASK) +#define PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_SHIFT) + +/* + * TX_PHY0_BYPS_CKDET (RW) + * + * tx phy0 byps_ckdet + */ +#define PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_MASK (0x10000UL) +#define PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_SHIFT (16U) +#define PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_MASK) +#define PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_SHIFT) + +/* + * TX_PHY0_PLL_DIV (RW) + * + * tx phy0 pll_div + */ +#define PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_MASK (0x7FFFU) +#define PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_SHIFT (0U) +#define PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_MASK) +#define PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_SHIFT) + +/* Bitfield definition for register: GPR_WR_D3 */ +/* + * TX_PHY0_PLL_CTRL (RW) + * + * tx phy0 pll_ctrl + */ +#define PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_MASK (0xFFFFFFFFUL) +#define PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_SHIFT (0U) +#define PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_SHIFT) & PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_MASK) +#define PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_MASK) >> PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_SHIFT) + +/* Bitfield definition for register: GPR_WR_D4 */ +/* + * TX_PHY0_TXCK_BIST_EN (RW) + * + * tx phy0 txck_bist_en + */ +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_MASK (0x80000000UL) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_SHIFT (31U) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_MASK) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_SHIFT) + +/* + * TX_PHY0_TX3_BIST_EN (RW) + * + * tx phy0 tx3_bist_en + */ +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_MASK (0x40000000UL) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_SHIFT (30U) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_MASK) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_SHIFT) + +/* + * TX_PHY0_TX2_BIST_EN (RW) + * + * tx phy0 tx2_bist_en + */ +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_MASK (0x20000000UL) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_SHIFT (29U) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_MASK) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_SHIFT) + +/* + * TX_PHY0_TX1_BIST_EN (RW) + * + * tx phy0 tx1_bist_en + */ +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_MASK (0x10000000UL) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_SHIFT (28U) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_MASK) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_SHIFT) + +/* + * TX_PHY0_TX0_BIST_EN (RW) + * + * tx phy0 tx0_bist_en + */ +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_MASK (0x8000000UL) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_SHIFT (27U) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_MASK) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_SHIFT) + +/* + * TX_PHY0_TXCK_LPBK_EN (RW) + * + * tx_phy0 txck_lpbk_en + */ +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_MASK (0x4000000UL) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_SHIFT (26U) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_MASK) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_SHIFT) + +/* + * TX_PHY0_TX3_LPBK_EN (RW) + * + * tx_phy0 tx3_lpbk_en + */ +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_MASK (0x2000000UL) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_SHIFT (25U) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_MASK) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_SHIFT) + +/* + * TX_PHY0_TX2_LPBK_EN (RW) + * + * tx_phy0 tx2_lpbk_en + */ +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_MASK (0x1000000UL) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_SHIFT (24U) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_MASK) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_SHIFT) + +/* + * TX_PHY0_TX1_LPBK_EN (RW) + * + * tx_phy0 tx1_lpbk_en + */ +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_MASK (0x800000UL) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_SHIFT (23U) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_MASK) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_SHIFT) + +/* + * TX_PHY0_TX0_LPBK_EN (RW) + * + * tx_phy0 tx0_lpbk_en + */ +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_MASK (0x400000UL) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_SHIFT (22U) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_MASK) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_SHIFT) + +/* + * TX_PHY0_TXCK_PAT_SEL (RW) + * + * tx phy0 txck_pat_sel + */ +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_MASK (0x300000UL) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_SHIFT (20U) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_MASK) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_SHIFT) + +/* + * TX_PHY0_TX3_PAT_SEL (RW) + * + * tx phy0 tx3_pat_sel + */ +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_MASK (0xC0000UL) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_SHIFT (18U) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_MASK) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_SHIFT) + +/* + * TX_PHY0_TX2_PAT_SEL (RW) + * + * tx phy0 tx2_pat_sel + */ +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_MASK (0x30000UL) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_SHIFT (16U) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_MASK) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_SHIFT) + +/* + * TX_PHY0_TX1_PAT_SEL (RW) + * + * tx phy0 tx1_pat_sel + */ +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_MASK (0xC000U) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_SHIFT (14U) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_MASK) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_SHIFT) + +/* + * TX_PHY0_TX0_PAT_SEL (RW) + * + * tx phy0 tx0_pat_sel + */ +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_MASK (0x3000U) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_SHIFT (12U) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_MASK) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_SHIFT) + +/* + * TX_PHY0_DSI0_PRBS_DISABLE (RW) + * + * tx phy0 dsi0_prbs_disable + */ +#define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_MASK (0x800U) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_SHIFT (11U) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_MASK) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_SHIFT) + +/* + * TX_PHY0_DSI0_PRBS_START (RW) + * + * tx phy0 dsi0_prbs_start + */ +#define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_MASK (0x400U) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_SHIFT (10U) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_MASK) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_SHIFT) + +/* + * TX_PHY0_CKPHY_CTL (RW) + * + * tx phy0 ckphy_ctl + */ +#define PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_MASK (0x1FFU) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_SHIFT (0U) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_MASK) +#define PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_SHIFT) + +/* Bitfield definition for register: GPR_WR_D5 */ +/* + * TX_PHY1_PORT_PLL_RDY_SEL (RW) + * + * tx phy1 port_pll_rdy_sel + */ +#define PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_MASK (0x20000000UL) +#define PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_SHIFT (29U) +#define PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_MASK) +#define PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_SHIFT) + +/* + * TX_PHY1_RATE_LVDS (RW) + * + * tx phy1 rate_lvds + */ +#define PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_MASK (0x18000000UL) +#define PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_SHIFT (27U) +#define PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_MASK) +#define PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_SHIFT) + +/* + * TX_PHY1_PHY_MODE (RW) + * + * tx phy1 phy_mode + */ +#define PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_MASK (0x6000000UL) +#define PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_SHIFT (25U) +#define PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_MASK) +#define PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_SHIFT) + +/* + * TX_PHY1_REFCLK_DIV (RW) + * + * tx phy1 refclk_div + */ +#define PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_MASK (0xF00000UL) +#define PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_SHIFT (20U) +#define PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_MASK) +#define PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_SHIFT) + +/* + * TX_PHY1_IDDQ_EN (RW) + * + * tx phy1 iddq_en + */ +#define PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_MASK (0x80000UL) +#define PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_SHIFT (19U) +#define PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_MASK) +#define PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_SHIFT) + +/* + * TX_PHY1_RESET_N (RW) + * + * tx phy1 reset, active low + */ +#define PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_MASK (0x40000UL) +#define PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_SHIFT (18U) +#define PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_MASK) +#define PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_SHIFT) + +/* + * TX_PHY1_SHUTDOWNZ (RW) + * + * tx phy1 shutdownz, active low + */ +#define PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_MASK (0x20000UL) +#define PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_SHIFT (17U) +#define PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_MASK) +#define PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_SHIFT) + +/* + * TX_PHY1_BYPS_CKDET (RW) + * + * tx phy1 byps_ckdet + */ +#define PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_MASK (0x10000UL) +#define PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_SHIFT (16U) +#define PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_MASK) +#define PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_SHIFT) + +/* + * TX_PHY1_PLL_DIV (RW) + * + * tx phy1 pll_div + */ +#define PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_MASK (0x7FFFU) +#define PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_SHIFT (0U) +#define PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_MASK) +#define PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_SHIFT) + +/* Bitfield definition for register: GPR_WR_D6 */ +/* + * TX_PHY1_PLL_CTRL (RW) + * + * tx phy1 pll_ctrl + */ +#define PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_MASK (0xFFFFFFFFUL) +#define PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_SHIFT (0U) +#define PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_SHIFT) & PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_MASK) +#define PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_MASK) >> PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_SHIFT) + +/* Bitfield definition for register: GPR_WR_D7 */ +/* + * TX_PHY1_TXCK_BIST_EN (RW) + * + * tx phy1 txck_bist_en + */ +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_MASK (0x80000000UL) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_SHIFT (31U) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_MASK) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_SHIFT) + +/* + * TX_PHY1_TX3_BIST_EN (RW) + * + * tx phy1 tx3_bist_en + */ +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_MASK (0x40000000UL) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_SHIFT (30U) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_MASK) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_SHIFT) + +/* + * TX_PHY1_TX2_BIST_EN (RW) + * + * tx phy1 tx2_bist_en + */ +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_MASK (0x20000000UL) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_SHIFT (29U) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_MASK) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_SHIFT) + +/* + * TX_PHY1_TX1_BIST_EN (RW) + * + * tx phy1 tx1_bist_en + */ +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_MASK (0x10000000UL) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_SHIFT (28U) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_MASK) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_SHIFT) + +/* + * TX_PHY1_TX0_BIST_EN (RW) + * + * tx phy1 tx0_bist_en + */ +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_MASK (0x8000000UL) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_SHIFT (27U) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_MASK) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_SHIFT) + +/* + * TX_PHY1_TXCK_LPBK_EN (RW) + * + * tx_phy1 txck_lpbk_en + */ +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_MASK (0x4000000UL) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_SHIFT (26U) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_MASK) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_SHIFT) + +/* + * TX_PHY1_TX3_LPBK_EN (RW) + * + * tx_phy1 tx3_lpbk_en + */ +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_MASK (0x2000000UL) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_SHIFT (25U) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_MASK) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_SHIFT) + +/* + * TX_PHY1_TX2_LPBK_EN (RW) + * + * tx_phy1 tx2_lpbk_en + */ +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_MASK (0x1000000UL) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_SHIFT (24U) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_MASK) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_SHIFT) + +/* + * TX_PHY1_TX1_LPBK_EN (RW) + * + * tx_phy1 tx1_lpbk_en + */ +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_MASK (0x800000UL) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_SHIFT (23U) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_MASK) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_SHIFT) + +/* + * TX_PHY1_TX0_LPBK_EN (RW) + * + * tx_phy1 tx0_lpbk_en + */ +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_MASK (0x400000UL) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_SHIFT (22U) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_MASK) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_SHIFT) + +/* + * TX_PHY1_TXCK_PAT_SEL (RW) + * + * tx phy1 txck_pat_sel + */ +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_MASK (0x300000UL) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_SHIFT (20U) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_MASK) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_SHIFT) + +/* + * TX_PHY1_TX3_PAT_SEL (RW) + * + * tx phy1 tx3_pat_sel + */ +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_MASK (0xC0000UL) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_SHIFT (18U) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_MASK) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_SHIFT) + +/* + * TX_PHY1_TX2_PAT_SEL (RW) + * + * tx phy1 tx2_pat_sel + */ +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_MASK (0x30000UL) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_SHIFT (16U) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_MASK) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_SHIFT) + +/* + * TX_PHY1_TX1_PAT_SEL (RW) + * + * tx phy1 tx1_pat_sel + */ +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_MASK (0xC000U) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_SHIFT (14U) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_MASK) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_SHIFT) + +/* + * TX_PHY1_TX0_PAT_SEL (RW) + * + * tx phy1 tx0_pat_sel + */ +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_MASK (0x3000U) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_SHIFT (12U) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_MASK) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_SHIFT) + +/* + * TX_PHY1_DSI0_PRBS_DISABLE (RW) + * + * tx phy1 dsi0_prbs_disable + */ +#define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_MASK (0x800U) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_SHIFT (11U) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_MASK) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_SHIFT) + +/* + * TX_PHY1_DSI0_PRBS_START (RW) + * + * tx phy1 dsi0_prbs_start + */ +#define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_MASK (0x400U) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_SHIFT (10U) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_MASK) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_SHIFT) + +/* + * TX_PHY1_CKPHY_CTL (RW) + * + * tx phy1 ckphy_ctl + */ +#define PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_MASK (0x1FFU) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_SHIFT (0U) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_MASK) +#define PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_SHIFT) + +/* Bitfield definition for register: GPR_WR_D8 */ +/* + * RX_PHY0_BRUN_IN_MODE (RW) + * + * rx phy0 burn_in_mode + */ +#define PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_MASK (0x80000000UL) +#define PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_SHIFT (31U) +#define PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_MASK) +#define PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_SHIFT) + +/* + * RX_PHY0_BURN_IN_EN_PAD (RW) + * + * rx phy0 burn_in_en_pad + */ +#define PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_MASK (0x40000000UL) +#define PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_SHIFT (30U) +#define PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_MASK) +#define PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_SHIFT) + +/* + * RX_PHY0_LPBK_MODE (RW) + * + * rx phy0 lpbk_mode + */ +#define PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_MASK (0x30000000UL) +#define PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_SHIFT (28U) +#define PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_MASK) +#define PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_SHIFT) + +/* + * RX_PHY0_BIST_FREQ_TRIM (RW) + * + * rx phy0 bist_freq_trim + */ +#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_MASK (0xF000000UL) +#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_SHIFT (24U) +#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_MASK) +#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_SHIFT) + +/* + * RX_PHY0_RX0_BIST_EN (RW) + * + * rx phy0 rx0_bist_en rx1_bist_en + */ +#define PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_MASK (0x400000UL) +#define PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_SHIFT (22U) +#define PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_MASK) +#define PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_SHIFT) + +/* + * RX_PHY0_BIST_MODE (RW) + * + * rx phy0 bist_mode + */ +#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_MASK (0x200000UL) +#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_SHIFT (21U) +#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_MASK) +#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_SHIFT) + +/* + * RX_PHY0_BIST_EN_PAD (RW) + * + * rx phy0 bist_en_pad + */ +#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_MASK (0x100000UL) +#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_SHIFT (20U) +#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_MASK) +#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_SHIFT) + +/* + * RX_PHY0_BIST_EN (RW) + * + * rx phy0 bist_en + */ +#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_MASK (0x80000UL) +#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_SHIFT (19U) +#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_MASK) +#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_SHIFT) + +/* + * RX_PHY0_BIST_CKIN_SEL (RW) + * + * rx phy0 bist_ckin_sel + */ +#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_MASK (0x40000UL) +#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_SHIFT (18U) +#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_MASK) +#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_SHIFT) + +/* + * RX_PHY0_PHY_MODE (RW) + * + * rx phy0 phy_mode + */ +#define PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_MASK (0x3U) +#define PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_SHIFT (0U) +#define PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_MASK) +#define PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_SHIFT) + +/* Bitfield definition for register: GPR_WR_D9 */ +/* + * RX_PHY1_BRUN_IN_MODE (RW) + * + * rx phy1 burn_in_mode + */ +#define PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_MASK (0x80000000UL) +#define PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_SHIFT (31U) +#define PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_MASK) +#define PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_SHIFT) + +/* + * RX_PHY1_BURN_IN_EN_PAD (RW) + * + * rx phy1 burn_in_en_pad + */ +#define PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_MASK (0x40000000UL) +#define PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_SHIFT (30U) +#define PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_MASK) +#define PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_SHIFT) + +/* + * RX_PHY1_LPBK_MODE (RW) + * + * rx phy1 lpbk_mode + */ +#define PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_MASK (0x30000000UL) +#define PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_SHIFT (28U) +#define PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_MASK) +#define PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_SHIFT) + +/* + * RX_PHY1_BIST_FREQ_TRIM (RW) + * + * rx phy1 bist_freq_trim + */ +#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_MASK (0xF000000UL) +#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_SHIFT (24U) +#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_MASK) +#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_SHIFT) + +/* + * RX_PHY1_RX0_BIST_EN (RW) + * + * rx phy1 rx0_bist_en rx1_bist_en + */ +#define PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_MASK (0x400000UL) +#define PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_SHIFT (22U) +#define PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_MASK) +#define PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_SHIFT) + +/* + * RX_PHY1_BIST_MODE (RW) + * + * rx phy1 bist_mode + */ +#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_MASK (0x200000UL) +#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_SHIFT (21U) +#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_MASK) +#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_SHIFT) + +/* + * RX_PHY1_BIST_EN_PAD (RW) + * + * rx phy1 bist_en_pad + */ +#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_MASK (0x100000UL) +#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_SHIFT (20U) +#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_MASK) +#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_SHIFT) + +/* + * RX_PHY1_BIST_EN (RW) + * + * rx phy1 bist_en + */ +#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_MASK (0x80000UL) +#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_SHIFT (19U) +#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_MASK) +#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_SHIFT) + +/* + * RX_PHY1_BIST_CKIN_SEL (RW) + * + * rx phy1 bist_ckin_sel + */ +#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_MASK (0x40000UL) +#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_SHIFT (18U) +#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_MASK) +#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_SHIFT) + +/* + * RX_PHY1_PHY_MODE (RW) + * + * rx phy1 phy_mode + */ +#define PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_MASK (0x3U) +#define PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_SHIFT (0U) +#define PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_MASK) +#define PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_SHIFT) + +/* Bitfield definition for register: GPR_RO_D0 */ +/* + * TX_PHY1_CTL_O (RO) + * + * {2'b0, + * tx_phy1_tx3_ctl_o,tx_phy1_tx2_ctl_o, + * tx_phy1_tx1_ctl_o,tx_phy1_tx0_ctl_o, + * tx_phy1_txck_ctl_o,tx_phy1_pll_dtest_o} + */ +#define PIXELMUX_GPR_RO_D0_TX_PHY1_CTL_O_MASK (0xFF00U) +#define PIXELMUX_GPR_RO_D0_TX_PHY1_CTL_O_SHIFT (8U) +#define PIXELMUX_GPR_RO_D0_TX_PHY1_CTL_O_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D0_TX_PHY1_CTL_O_MASK) >> PIXELMUX_GPR_RO_D0_TX_PHY1_CTL_O_SHIFT) + +/* + * TX_PHY0_CTL_O (RO) + * + * {2'b0, + * tx_phy0_tx3_ctl_o,tx_phy0_tx2_ctl_o, + * tx_phy0_tx1_ctl_o,tx_phy0_tx0_ctl_o, + * tx_phy0_txck_ctl_o,tx_phy0_pll_dtest_o} + */ +#define PIXELMUX_GPR_RO_D0_TX_PHY0_CTL_O_MASK (0xFFU) +#define PIXELMUX_GPR_RO_D0_TX_PHY0_CTL_O_SHIFT (0U) +#define PIXELMUX_GPR_RO_D0_TX_PHY0_CTL_O_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D0_TX_PHY0_CTL_O_MASK) >> PIXELMUX_GPR_RO_D0_TX_PHY0_CTL_O_SHIFT) + +/* Bitfield definition for register: GPR_RO_D1 */ +/* + * IRQ_CSI0_AP (RO) + * + * interrupt of csi0 ap + */ +#define PIXELMUX_GPR_RO_D1_IRQ_CSI0_AP_MASK (0x20000UL) +#define PIXELMUX_GPR_RO_D1_IRQ_CSI0_AP_SHIFT (17U) +#define PIXELMUX_GPR_RO_D1_IRQ_CSI0_AP_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D1_IRQ_CSI0_AP_MASK) >> PIXELMUX_GPR_RO_D1_IRQ_CSI0_AP_SHIFT) + +/* + * CSI0_CFG_CSI_AP_DIAG_FAULTS (RO) + * + * csi0 ap diag faults + */ +#define PIXELMUX_GPR_RO_D1_CSI0_CFG_CSI_AP_DIAG_FAULTS_MASK (0x1FFE0UL) +#define PIXELMUX_GPR_RO_D1_CSI0_CFG_CSI_AP_DIAG_FAULTS_SHIFT (5U) +#define PIXELMUX_GPR_RO_D1_CSI0_CFG_CSI_AP_DIAG_FAULTS_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D1_CSI0_CFG_CSI_AP_DIAG_FAULTS_MASK) >> PIXELMUX_GPR_RO_D1_CSI0_CFG_CSI_AP_DIAG_FAULTS_SHIFT) + +/* + * CSI0_STA_AP_IF_INT_STA (RO) + * + * csi0 apb parity check interrupt satus + */ +#define PIXELMUX_GPR_RO_D1_CSI0_STA_AP_IF_INT_STA_MASK (0x1FU) +#define PIXELMUX_GPR_RO_D1_CSI0_STA_AP_IF_INT_STA_SHIFT (0U) +#define PIXELMUX_GPR_RO_D1_CSI0_STA_AP_IF_INT_STA_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D1_CSI0_STA_AP_IF_INT_STA_MASK) >> PIXELMUX_GPR_RO_D1_CSI0_STA_AP_IF_INT_STA_SHIFT) + +/* Bitfield definition for register: GPR_RO_D2 */ +/* + * IRQ_CSI1_AP (RO) + * + * interrupt of csi1 ap + */ +#define PIXELMUX_GPR_RO_D2_IRQ_CSI1_AP_MASK (0x20000UL) +#define PIXELMUX_GPR_RO_D2_IRQ_CSI1_AP_SHIFT (17U) +#define PIXELMUX_GPR_RO_D2_IRQ_CSI1_AP_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D2_IRQ_CSI1_AP_MASK) >> PIXELMUX_GPR_RO_D2_IRQ_CSI1_AP_SHIFT) + +/* + * CSI1_CFG_CSI_AP_DIAG_FAULTS (RO) + * + * csi1 ap diag faults + */ +#define PIXELMUX_GPR_RO_D2_CSI1_CFG_CSI_AP_DIAG_FAULTS_MASK (0x1FFE0UL) +#define PIXELMUX_GPR_RO_D2_CSI1_CFG_CSI_AP_DIAG_FAULTS_SHIFT (5U) +#define PIXELMUX_GPR_RO_D2_CSI1_CFG_CSI_AP_DIAG_FAULTS_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D2_CSI1_CFG_CSI_AP_DIAG_FAULTS_MASK) >> PIXELMUX_GPR_RO_D2_CSI1_CFG_CSI_AP_DIAG_FAULTS_SHIFT) + +/* + * CSI1_STA_AP_IF_INT_STA (RO) + * + * csi1 apb parity check interrupt satus + */ +#define PIXELMUX_GPR_RO_D2_CSI1_STA_AP_IF_INT_STA_MASK (0x1FU) +#define PIXELMUX_GPR_RO_D2_CSI1_STA_AP_IF_INT_STA_SHIFT (0U) +#define PIXELMUX_GPR_RO_D2_CSI1_STA_AP_IF_INT_STA_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D2_CSI1_STA_AP_IF_INT_STA_MASK) >> PIXELMUX_GPR_RO_D2_CSI1_STA_AP_IF_INT_STA_SHIFT) + +/* Bitfield definition for register: GPR_RO_D3 */ +/* + * RX_PHY0_RXCK_CTLO (RO) + * + * rx phy0 rxck_ctlo + */ +#define PIXELMUX_GPR_RO_D3_RX_PHY0_RXCK_CTLO_MASK (0xFF00U) +#define PIXELMUX_GPR_RO_D3_RX_PHY0_RXCK_CTLO_SHIFT (8U) +#define PIXELMUX_GPR_RO_D3_RX_PHY0_RXCK_CTLO_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D3_RX_PHY0_RXCK_CTLO_MASK) >> PIXELMUX_GPR_RO_D3_RX_PHY0_RXCK_CTLO_SHIFT) + +/* + * RX_PHY0_RX1_CTLO (RO) + * + * rx phy0 rx1_ctlo + */ +#define PIXELMUX_GPR_RO_D3_RX_PHY0_RX1_CTLO_MASK (0xF0U) +#define PIXELMUX_GPR_RO_D3_RX_PHY0_RX1_CTLO_SHIFT (4U) +#define PIXELMUX_GPR_RO_D3_RX_PHY0_RX1_CTLO_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D3_RX_PHY0_RX1_CTLO_MASK) >> PIXELMUX_GPR_RO_D3_RX_PHY0_RX1_CTLO_SHIFT) + +/* + * RX_PHY0_RX0_CTLO (RO) + * + * rx phy0 rx0_ctlo + */ +#define PIXELMUX_GPR_RO_D3_RX_PHY0_RX0_CTLO_MASK (0xFU) +#define PIXELMUX_GPR_RO_D3_RX_PHY0_RX0_CTLO_SHIFT (0U) +#define PIXELMUX_GPR_RO_D3_RX_PHY0_RX0_CTLO_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D3_RX_PHY0_RX0_CTLO_MASK) >> PIXELMUX_GPR_RO_D3_RX_PHY0_RX0_CTLO_SHIFT) + +/* Bitfield definition for register: GPR_RO_D4 */ +/* + * RX_PHY1_RXCK_CTLO (RO) + * + * rx phy1 rxck_ctlo + */ +#define PIXELMUX_GPR_RO_D4_RX_PHY1_RXCK_CTLO_MASK (0xFF00U) +#define PIXELMUX_GPR_RO_D4_RX_PHY1_RXCK_CTLO_SHIFT (8U) +#define PIXELMUX_GPR_RO_D4_RX_PHY1_RXCK_CTLO_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D4_RX_PHY1_RXCK_CTLO_MASK) >> PIXELMUX_GPR_RO_D4_RX_PHY1_RXCK_CTLO_SHIFT) + +/* + * RX_PHY1_RX1_CTLO (RO) + * + * rx phy1 rx1_ctlo + */ +#define PIXELMUX_GPR_RO_D4_RX_PHY1_RX1_CTLO_MASK (0xF0U) +#define PIXELMUX_GPR_RO_D4_RX_PHY1_RX1_CTLO_SHIFT (4U) +#define PIXELMUX_GPR_RO_D4_RX_PHY1_RX1_CTLO_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D4_RX_PHY1_RX1_CTLO_MASK) >> PIXELMUX_GPR_RO_D4_RX_PHY1_RX1_CTLO_SHIFT) + +/* + * RX_PHY1_RX0_CTLO (RO) + * + * rx phy1 rx0_ctlo + */ +#define PIXELMUX_GPR_RO_D4_RX_PHY1_RX0_CTLO_MASK (0xFU) +#define PIXELMUX_GPR_RO_D4_RX_PHY1_RX0_CTLO_SHIFT (0U) +#define PIXELMUX_GPR_RO_D4_RX_PHY1_RX0_CTLO_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D4_RX_PHY1_RX0_CTLO_MASK) >> PIXELMUX_GPR_RO_D4_RX_PHY1_RX0_CTLO_SHIFT) + +/* Bitfield definition for register: GPR_RO_D5 */ +/* + * DSI0_PRBS_STATE (RO) + * + * dsi0_prbs_state for debug only + */ +#define PIXELMUX_GPR_RO_D5_DSI0_PRBS_STATE_MASK (0xF000U) +#define PIXELMUX_GPR_RO_D5_DSI0_PRBS_STATE_SHIFT (12U) +#define PIXELMUX_GPR_RO_D5_DSI0_PRBS_STATE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_DSI0_PRBS_STATE_MASK) >> PIXELMUX_GPR_RO_D5_DSI0_PRBS_STATE_SHIFT) + +/* + * TX_PHY0_TXCK_BIST_DONE_PAD (RO) + * + * tx phy0 txck_done_pad + */ +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_PAD_MASK (0x800U) +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_PAD_SHIFT (11U) +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_PAD_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_PAD_SHIFT) + +/* + * TX_PHY0_TXCK_BIST_OK_PAD (RO) + * + * tx phy0 txck_ok_pad + */ +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OK_PAD_MASK (0x400U) +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OK_PAD_SHIFT (10U) +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OK_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OK_PAD_SHIFT) + +/* + * TX_PHY0_TXCK_BIST_DONE (RO) + * + * tx phy0 txck_bist_done + */ +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_MASK (0x200U) +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_SHIFT (9U) +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_SHIFT) + +/* + * TX_PHY0_TX3_BIST_DONE (RO) + * + * tx phy0 tx3_bist_done + */ +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_DONE_MASK (0x100U) +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_DONE_SHIFT (8U) +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_DONE_SHIFT) + +/* + * TX_PHY0_TX2_BIST_DONE (RO) + * + * tx phy0 tx2_bist_done + */ +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_DONE_MASK (0x80U) +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_DONE_SHIFT (7U) +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_DONE_SHIFT) + +/* + * TX_PHY0_TX1_BIST_DONE (RO) + * + * tx phy0 tx1_bist_done + */ +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_DONE_MASK (0x40U) +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_DONE_SHIFT (6U) +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_DONE_SHIFT) + +/* + * TX_PHY0_TX0_BIST_DONE (RO) + * + * tx phy0 tx0_bist_done + */ +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_DONE_MASK (0x20U) +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_DONE_SHIFT (5U) +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_DONE_SHIFT) + +/* + * TX_PHY0_TXCK_BIST_OUT (RO) + * + * tx phy0 txck_bist_out + */ +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OUT_MASK (0x10U) +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OUT_SHIFT (4U) +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OUT_SHIFT) + +/* + * TX_PHY0_TX3_BIST_OUT (RO) + * + * tx phy0 tx3_bist_out + */ +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_OUT_MASK (0x8U) +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_OUT_SHIFT (3U) +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_OUT_SHIFT) + +/* + * TX_PHY0_TX2_BIST_OUT (RO) + * + * tx phy0 tx2_bist_out + */ +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_OUT_MASK (0x4U) +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_OUT_SHIFT (2U) +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_OUT_SHIFT) + +/* + * TX_PHY0_TX1_BIST_OUT (RO) + * + * tx phy0 tx1_bist_out + */ +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_OUT_MASK (0x2U) +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_OUT_SHIFT (1U) +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_OUT_SHIFT) + +/* + * TX_PHY0_TX0_BIST_OUT (RO) + * + * tx phy0 tx0_bist_out + */ +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_OUT_MASK (0x1U) +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_OUT_SHIFT (0U) +#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_OUT_SHIFT) + +/* Bitfield definition for register: GPR_RO_D6 */ +/* + * DSI1_PRBS_STATE (RO) + * + * dsi1_prbs_state for debug only + */ +#define PIXELMUX_GPR_RO_D6_DSI1_PRBS_STATE_MASK (0xF000U) +#define PIXELMUX_GPR_RO_D6_DSI1_PRBS_STATE_SHIFT (12U) +#define PIXELMUX_GPR_RO_D6_DSI1_PRBS_STATE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_DSI1_PRBS_STATE_MASK) >> PIXELMUX_GPR_RO_D6_DSI1_PRBS_STATE_SHIFT) + +/* + * TX_PHY1_TXCK_BIST_DONE_PAD (RO) + * + * tx phy1 txck_done_pad + */ +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_PAD_MASK (0x800U) +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_PAD_SHIFT (11U) +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_PAD_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_PAD_SHIFT) + +/* + * TX_PHY1_TXCK_BIST_OK_PAD (RO) + * + * tx phy1 txck_ok_pad + */ +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OK_PAD_MASK (0x400U) +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OK_PAD_SHIFT (10U) +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OK_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OK_PAD_SHIFT) + +/* + * TX_PHY1_TXCK_BIST_DONE (RO) + * + * tx phy1 txck_bist_done + */ +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_MASK (0x200U) +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_SHIFT (9U) +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_SHIFT) + +/* + * TX_PHY1_TX3_BIST_DONE (RO) + * + * tx phy1 tx3_bist_done + */ +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_DONE_MASK (0x100U) +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_DONE_SHIFT (8U) +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_DONE_SHIFT) + +/* + * TX_PHY1_TX2_BIST_DONE (RO) + * + * tx phy1 tx2_bist_done + */ +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_DONE_MASK (0x80U) +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_DONE_SHIFT (7U) +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_DONE_SHIFT) + +/* + * TX_PHY1_TX1_BIST_DONE (RO) + * + * tx phy1 tx1_bist_done + */ +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_DONE_MASK (0x40U) +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_DONE_SHIFT (6U) +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_DONE_SHIFT) + +/* + * TX_PHY1_TX0_BIST_DONE (RO) + * + * tx phy1 tx0_bist_done + */ +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_DONE_MASK (0x20U) +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_DONE_SHIFT (5U) +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_DONE_SHIFT) + +/* + * TX_PHY1_TXCK_BIST_OUT (RO) + * + * tx phy1 txck_bist_out + */ +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OUT_MASK (0x10U) +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OUT_SHIFT (4U) +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OUT_SHIFT) + +/* + * TX_PHY1_TX3_BIST_OUT (RO) + * + * tx phy1 tx3_bist_out + */ +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_OUT_MASK (0x8U) +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_OUT_SHIFT (3U) +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_OUT_SHIFT) + +/* + * TX_PHY1_TX2_BIST_OUT (RO) + * + * tx phy1 tx2_bist_out + */ +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_OUT_MASK (0x4U) +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_OUT_SHIFT (2U) +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_OUT_SHIFT) + +/* + * TX_PHY1_TX1_BIST_OUT (RO) + * + * tx phy1 tx1_bist_out + */ +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_OUT_MASK (0x2U) +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_OUT_SHIFT (1U) +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_OUT_SHIFT) + +/* + * TX_PHY1_TX0_BIST_OUT (RO) + * + * tx phy1 tx0_bist_out + */ +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_OUT_MASK (0x1U) +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_OUT_SHIFT (0U) +#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_OUT_SHIFT) + +/* Bitfield definition for register: GPR_RO_D7 */ +/* + * RX_PHY0_BURN_IN_OK_PAD (RO) + * + * rx_phy0_burn_in_ok_pad + */ +#define PIXELMUX_GPR_RO_D7_RX_PHY0_BURN_IN_OK_PAD_MASK (0x40U) +#define PIXELMUX_GPR_RO_D7_RX_PHY0_BURN_IN_OK_PAD_SHIFT (6U) +#define PIXELMUX_GPR_RO_D7_RX_PHY0_BURN_IN_OK_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_BURN_IN_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_BURN_IN_OK_PAD_SHIFT) + +/* + * RX_PHY0_RX1_BIST_DONE (RO) + * + * rx phy0 rx1_bist_done + */ +#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_DONE_MASK (0x20U) +#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_DONE_SHIFT (5U) +#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_DONE_SHIFT) + +/* + * RX_PHY0_RX0_BIST_DONE (RO) + * + * rx phy0 rx0_bist_done + */ +#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_DONE_MASK (0x10U) +#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_DONE_SHIFT (4U) +#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_DONE_SHIFT) + +/* + * RX_PHY0_RX1_BIST_OUT (RO) + * + * rx phy0 rx1_bist_out + */ +#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_OUT_MASK (0x8U) +#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_OUT_SHIFT (3U) +#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_OUT_SHIFT) + +/* + * RX_PHY0_RX0_BIST_OUT (RO) + * + * rx phy0 rx0_bist_out + */ +#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_OUT_MASK (0x4U) +#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_OUT_SHIFT (2U) +#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_OUT_SHIFT) + +/* + * RX_PHY0_BIST_OK_PAD (RO) + * + * rx phy0 bist_ok_pad + */ +#define PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_OK_PAD_MASK (0x2U) +#define PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_OK_PAD_SHIFT (1U) +#define PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_OK_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_OK_PAD_SHIFT) + +/* + * RX_PHY0_BIST_DONE_PAD (RO) + * + * rx phy0 bist_done_pad + */ +#define PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_DONE_PAD_MASK (0x1U) +#define PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_DONE_PAD_SHIFT (0U) +#define PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_DONE_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_DONE_PAD_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_DONE_PAD_SHIFT) + +/* Bitfield definition for register: GPR_RO_D8 */ +/* + * RX_PHY1_BURN_IN_OK_PAD (RO) + * + * rx_phy1_burn_in_ok_pad + */ +#define PIXELMUX_GPR_RO_D8_RX_PHY1_BURN_IN_OK_PAD_MASK (0x40U) +#define PIXELMUX_GPR_RO_D8_RX_PHY1_BURN_IN_OK_PAD_SHIFT (6U) +#define PIXELMUX_GPR_RO_D8_RX_PHY1_BURN_IN_OK_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_BURN_IN_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_BURN_IN_OK_PAD_SHIFT) + +/* + * RX_PHY1_RX1_BIST_DONE (RO) + * + * rx phy1 rx1_bist_done + */ +#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_DONE_MASK (0x20U) +#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_DONE_SHIFT (5U) +#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_DONE_SHIFT) + +/* + * RX_PHY1_RX0_BIST_DONE (RO) + * + * rx phy1 rx0_bist_done + */ +#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_DONE_MASK (0x10U) +#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_DONE_SHIFT (4U) +#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_DONE_SHIFT) + +/* + * RX_PHY1_RX1_BIST_OUT (RO) + * + * rx phy1 rx1_bist_out + */ +#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_OUT_MASK (0x8U) +#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_OUT_SHIFT (3U) +#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_OUT_SHIFT) + +/* + * RX_PHY1_RX0_BIST_OUT (RO) + * + * rx phy1 rx0_bist_out + */ +#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_OUT_MASK (0x4U) +#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_OUT_SHIFT (2U) +#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_OUT_SHIFT) + +/* + * RX_PHY1_BIST_OK_PAD (RO) + * + * rx phy1 bist_ok_pad + */ +#define PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_OK_PAD_MASK (0x2U) +#define PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_OK_PAD_SHIFT (1U) +#define PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_OK_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_OK_PAD_SHIFT) + +/* + * RX_PHY1_BIST_DONE_PAD (RO) + * + * rx phy1 bist_done_pad + */ +#define PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_DONE_PAD_MASK (0x1U) +#define PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_DONE_PAD_SHIFT (0U) +#define PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_DONE_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_DONE_PAD_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_DONE_PAD_SHIFT) + +/* Bitfield definition for register: GPR_RO_D9 */ +/* Bitfield definition for register: GPR_WR1_CLR_D0 */ +/* + * GPR_WR1_CLR_DATA (RW) + * + * gpr register, write 1 /no-write set/clr matching bit + */ +#define PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_MASK (0xFFFFFFFFUL) +#define PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_SHIFT (0U) +#define PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_SHIFT) & PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_MASK) +#define PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_MASK) >> PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_SHIFT) + + + +/* DSI_SETTING register group index macro definition */ +#define PIXELMUX_DSI_SETTING_DSI0_CFG (0UL) +#define PIXELMUX_DSI_SETTING_DSI1_CFG (1UL) + + +#endif /* HPM_PIXELMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_plb_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_plb_regs.h new file mode 100644 index 00000000000..de378befa9e --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_plb_regs.h @@ -0,0 +1,165 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PLB_H +#define HPM_PLB_H + +typedef struct { + struct { + __RW uint32_t LOOKUP_TABLE[4]; /* 0x0 - 0xC: TYPE A CHN lookup_table 0 */ + __RW uint32_t SW_INJECT; /* 0x10: TYPE A CHN software inject */ + __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */ + } TYPE_A[4]; + __R uint8_t RESERVED0[896]; /* 0x80 - 0x3FF: Reserved */ + struct { + __RW uint32_t LUT[2]; /* 0x400 - 0x404: TYPE B CHN lookup table 0 */ + __RW uint32_t CMP[4]; /* 0x408 - 0x414: TYPE B CHN data unit cmp0 */ + __RW uint32_t MODE; /* 0x418: TYPE B CHN mode ctrl */ + __RW uint32_t SW_INJECT; /* 0x41C: TYPE B CHN software inject */ + } TYPE_B[4]; +} PLB_Type; + + +/* Bitfield definition for register of struct array TYPE_A: 0 */ +/* + * LOOKUP_TABLE (RW) + * + * using 4 bit trig_in as lookup index. software can program this register as trig_in's true table. + */ +#define PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_MASK (0xFFFFU) +#define PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_SHIFT (0U) +#define PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_SET(x) (((uint32_t)(x) << PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_SHIFT) & PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_MASK) +#define PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_GET(x) (((uint32_t)(x) & PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_MASK) >> PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_SHIFT) + +/* Bitfield definition for register of struct array TYPE_A: SW_INJECT */ +/* + * SW_INJECT (RW) + * + * software can inject value to TYPEA's output + */ +#define PLB_TYPE_A_SW_INJECT_SW_INJECT_MASK (0xFU) +#define PLB_TYPE_A_SW_INJECT_SW_INJECT_SHIFT (0U) +#define PLB_TYPE_A_SW_INJECT_SW_INJECT_SET(x) (((uint32_t)(x) << PLB_TYPE_A_SW_INJECT_SW_INJECT_SHIFT) & PLB_TYPE_A_SW_INJECT_SW_INJECT_MASK) +#define PLB_TYPE_A_SW_INJECT_SW_INJECT_GET(x) (((uint32_t)(x) & PLB_TYPE_A_SW_INJECT_SW_INJECT_MASK) >> PLB_TYPE_A_SW_INJECT_SW_INJECT_SHIFT) + +/* Bitfield definition for register of struct array TYPE_B: 0 */ +/* + * LOOKUP_TABLE (RW) + * + * lut0 and lut1 union as 64bit, consider each 4bit as one slice. then, total 16 slice. slice0 as bit3:0, slice1 as bit7:4...etc. using 4bit trig in as index of slice. the operate sel in data unit of type B channle is decided by which slice value choosed by trig_in + */ +#define PLB_TYPE_B_LUT_LOOKUP_TABLE_MASK (0xFFFFFFFFUL) +#define PLB_TYPE_B_LUT_LOOKUP_TABLE_SHIFT (0U) +#define PLB_TYPE_B_LUT_LOOKUP_TABLE_SET(x) (((uint32_t)(x) << PLB_TYPE_B_LUT_LOOKUP_TABLE_SHIFT) & PLB_TYPE_B_LUT_LOOKUP_TABLE_MASK) +#define PLB_TYPE_B_LUT_LOOKUP_TABLE_GET(x) (((uint32_t)(x) & PLB_TYPE_B_LUT_LOOKUP_TABLE_MASK) >> PLB_TYPE_B_LUT_LOOKUP_TABLE_SHIFT) + +/* Bitfield definition for register of struct array TYPE_B: 0 */ +/* + * CMP_VALUE (RW) + * + * cmp value, using as data unit operation + */ +#define PLB_TYPE_B_CMP_CMP_VALUE_MASK (0xFFFFFFFFUL) +#define PLB_TYPE_B_CMP_CMP_VALUE_SHIFT (0U) +#define PLB_TYPE_B_CMP_CMP_VALUE_SET(x) (((uint32_t)(x) << PLB_TYPE_B_CMP_CMP_VALUE_SHIFT) & PLB_TYPE_B_CMP_CMP_VALUE_MASK) +#define PLB_TYPE_B_CMP_CMP_VALUE_GET(x) (((uint32_t)(x) & PLB_TYPE_B_CMP_CMP_VALUE_MASK) >> PLB_TYPE_B_CMP_CMP_VALUE_SHIFT) + +/* Bitfield definition for register of struct array TYPE_B: MODE */ +/* + * OPT_SEL (RW) + * + * operation selection in data unit. + */ +#define PLB_TYPE_B_MODE_OPT_SEL_MASK (0x10000UL) +#define PLB_TYPE_B_MODE_OPT_SEL_SHIFT (16U) +#define PLB_TYPE_B_MODE_OPT_SEL_SET(x) (((uint32_t)(x) << PLB_TYPE_B_MODE_OPT_SEL_SHIFT) & PLB_TYPE_B_MODE_OPT_SEL_MASK) +#define PLB_TYPE_B_MODE_OPT_SEL_GET(x) (((uint32_t)(x) & PLB_TYPE_B_MODE_OPT_SEL_MASK) >> PLB_TYPE_B_MODE_OPT_SEL_SHIFT) + +/* + * OUT3_SEL (RW) + * + * trig out 3 output type in current channel + */ +#define PLB_TYPE_B_MODE_OUT3_SEL_MASK (0xF000U) +#define PLB_TYPE_B_MODE_OUT3_SEL_SHIFT (12U) +#define PLB_TYPE_B_MODE_OUT3_SEL_SET(x) (((uint32_t)(x) << PLB_TYPE_B_MODE_OUT3_SEL_SHIFT) & PLB_TYPE_B_MODE_OUT3_SEL_MASK) +#define PLB_TYPE_B_MODE_OUT3_SEL_GET(x) (((uint32_t)(x) & PLB_TYPE_B_MODE_OUT3_SEL_MASK) >> PLB_TYPE_B_MODE_OUT3_SEL_SHIFT) + +/* + * OUT2_SEL (RW) + * + * trig out 2 output type in current channel + */ +#define PLB_TYPE_B_MODE_OUT2_SEL_MASK (0xF00U) +#define PLB_TYPE_B_MODE_OUT2_SEL_SHIFT (8U) +#define PLB_TYPE_B_MODE_OUT2_SEL_SET(x) (((uint32_t)(x) << PLB_TYPE_B_MODE_OUT2_SEL_SHIFT) & PLB_TYPE_B_MODE_OUT2_SEL_MASK) +#define PLB_TYPE_B_MODE_OUT2_SEL_GET(x) (((uint32_t)(x) & PLB_TYPE_B_MODE_OUT2_SEL_MASK) >> PLB_TYPE_B_MODE_OUT2_SEL_SHIFT) + +/* + * OUT1_SEL (RW) + * + * trig out 1 output type in current channel + */ +#define PLB_TYPE_B_MODE_OUT1_SEL_MASK (0xF0U) +#define PLB_TYPE_B_MODE_OUT1_SEL_SHIFT (4U) +#define PLB_TYPE_B_MODE_OUT1_SEL_SET(x) (((uint32_t)(x) << PLB_TYPE_B_MODE_OUT1_SEL_SHIFT) & PLB_TYPE_B_MODE_OUT1_SEL_MASK) +#define PLB_TYPE_B_MODE_OUT1_SEL_GET(x) (((uint32_t)(x) & PLB_TYPE_B_MODE_OUT1_SEL_MASK) >> PLB_TYPE_B_MODE_OUT1_SEL_SHIFT) + +/* + * OUT0_SEL (RW) + * + * trig out 0 output type in current channel + */ +#define PLB_TYPE_B_MODE_OUT0_SEL_MASK (0xFU) +#define PLB_TYPE_B_MODE_OUT0_SEL_SHIFT (0U) +#define PLB_TYPE_B_MODE_OUT0_SEL_SET(x) (((uint32_t)(x) << PLB_TYPE_B_MODE_OUT0_SEL_SHIFT) & PLB_TYPE_B_MODE_OUT0_SEL_MASK) +#define PLB_TYPE_B_MODE_OUT0_SEL_GET(x) (((uint32_t)(x) & PLB_TYPE_B_MODE_OUT0_SEL_MASK) >> PLB_TYPE_B_MODE_OUT0_SEL_SHIFT) + +/* Bitfield definition for register of struct array TYPE_B: SW_INJECT */ +/* + * SOFTWARE_INJECT (RW) + * + * data unit value can be changed if program this register + */ +#define PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_MASK (0xFFFFFFFFUL) +#define PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_SHIFT (0U) +#define PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_SET(x) (((uint32_t)(x) << PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_SHIFT) & PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_MASK) +#define PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_GET(x) (((uint32_t)(x) & PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_MASK) >> PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_SHIFT) + + + +/* LOOKUP_TABLE register group index macro definition */ +#define PLB_TYPE_A_LOOKUP_TABLE_0 (0UL) +#define PLB_TYPE_A_LOOKUP_TABLE_1 (1UL) +#define PLB_TYPE_A_LOOKUP_TABLE_2 (2UL) +#define PLB_TYPE_A_LOOKUP_TABLE_3 (3UL) + +/* TYPE_A register group index macro definition */ +#define PLB_TYPE_A_0 (0UL) +#define PLB_TYPE_A_1 (1UL) +#define PLB_TYPE_A_2 (2UL) +#define PLB_TYPE_A_3 (3UL) + +/* LUT register group index macro definition */ +#define PLB_TYPE_B_LUT_0 (0UL) +#define PLB_TYPE_B_LUT_1 (1UL) + +/* CMP register group index macro definition */ +#define PLB_TYPE_B_CMP_0 (0UL) +#define PLB_TYPE_B_CMP_1 (1UL) +#define PLB_TYPE_B_CMP_2 (2UL) +#define PLB_TYPE_B_CMP_3 (3UL) + +/* TYPE_B register group index macro definition */ +#define PLB_TYPE_B_0 (0UL) +#define PLB_TYPE_B_1 (1UL) +#define PLB_TYPE_B_2 (2UL) +#define PLB_TYPE_B_3 (3UL) + + +#endif /* HPM_PLB_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pllctlv2_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pllctlv2_regs.h index 1345f6f9d41..3fbe9cee617 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pllctlv2_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pllctlv2_regs.h @@ -25,7 +25,7 @@ typedef struct { __R uint8_t RESERVED0[28]; /* 0xA4 - 0xBF: Reserved */ __RW uint32_t DIV[3]; /* 0xC0 - 0xC8: PLL0 divider output 0 configuration register */ __R uint8_t RESERVED1[52]; /* 0xCC - 0xFF: Reserved */ - } PLL[3]; + } PLL[7]; } PLLCTLV2_Type; @@ -301,6 +301,10 @@ typedef struct { #define PLLCTLV2_PLL_PLL0 (0UL) #define PLLCTLV2_PLL_PLL1 (1UL) #define PLLCTLV2_PLL_PLL2 (2UL) +#define PLLCTLV2_PLL_PLL3 (3UL) +#define PLLCTLV2_PLL_PLL4 (4UL) +#define PLLCTLV2_PLL_PLL5 (5UL) +#define PLLCTLV2_PLL_PLL6 (6UL) #endif /* HPM_PLLCTLV2_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ptpc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ptpc_regs.h index 48f5be63d66..60e687f3a12 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ptpc_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ptpc_regs.h @@ -29,6 +29,8 @@ typedef struct { __RW uint32_t TIME_SEL; /* 0x2000: */ __W uint32_t INT_STS; /* 0x2004: */ __RW uint32_t INT_EN; /* 0x2008: */ + __R uint8_t RESERVED0[4084]; /* 0x200C - 0x2FFF: Reserved */ + __RW uint32_t PTPC_CAN_TS_SEL; /* 0x3000: */ } PTPC_Type; @@ -109,8 +111,8 @@ typedef struct { /* * FINE_COARSE_SEL (RW) * - * 0: fine update, ns counter add ss_incr[7:0] each time addend counter overflow - * 1: coarse update, ns counter add ss_incr[7:0] each clk + * 0: coarse update, ns counter add ss_incr[7:0] each clk + * 1: fine update, ns counter add ss_incr[7:0] each time addend counter overflow */ #define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK (0x2U) #define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SHIFT (1U) @@ -399,6 +401,43 @@ typedef struct { #define PTPC_INT_EN_PPS_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_EN_PPS_INT_STS0_SHIFT) & PTPC_INT_EN_PPS_INT_STS0_MASK) #define PTPC_INT_EN_PPS_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_EN_PPS_INT_STS0_MASK) >> PTPC_INT_EN_PPS_INT_STS0_SHIFT) +/* Bitfield definition for register: PTPC_CAN_TS_SEL */ +/* + * TSU_TBIN3_SEL (RW) + * + */ +#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK (0xFC000000UL) +#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT (26U) +#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK) +#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT) + +/* + * TSU_TBIN2_SEL (RW) + * + */ +#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK (0x3F00000UL) +#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT (20U) +#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK) +#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT) + +/* + * TSU_TBIN1_SEL (RW) + * + */ +#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK (0xFC000UL) +#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT (14U) +#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK) +#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT) + +/* + * TSU_TBIN0_SEL (RW) + * + */ +#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK (0x3F00U) +#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT (8U) +#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK) +#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT) + /* PTPC register group index macro definition */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_qeiv2_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_qeiv2_regs.h new file mode 100644 index 00000000000..0de6ead4d18 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_qeiv2_regs.h @@ -0,0 +1,2000 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_QEIV2_H +#define HPM_QEIV2_H + +typedef struct { + __RW uint32_t CR; /* 0x0: Control register */ + __RW uint32_t PHCFG; /* 0x4: Phase configure register */ + __RW uint32_t WDGCFG; /* 0x8: Watchdog configure register */ + __RW uint32_t PHIDX; /* 0xC: Phase index register */ + __RW uint32_t TRGOEN; /* 0x10: Tigger output enable register */ + __RW uint32_t READEN; /* 0x14: Read event enable register */ + __RW uint32_t ZCMP; /* 0x18: Z comparator */ + __RW uint32_t PHCMP; /* 0x1C: Phase comparator */ + __RW uint32_t SPDCMP; /* 0x20: Speed comparator */ + __RW uint32_t DMAEN; /* 0x24: DMA request enable register */ + __RW uint32_t SR; /* 0x28: Status register */ + __RW uint32_t IRQEN; /* 0x2C: Interrupt request register */ + struct { + __RW uint32_t Z; /* 0x30: Z counter */ + __R uint32_t PH; /* 0x34: Phase counter */ + __RW uint32_t SPD; /* 0x38: Speed counter */ + __R uint32_t TMR; /* 0x3C: Timer counter */ + } COUNT[4]; + __R uint8_t RESERVED0[16]; /* 0x70 - 0x7F: Reserved */ + __RW uint32_t ZCMP2; /* 0x80: Z comparator */ + __RW uint32_t PHCMP2; /* 0x84: Phase comparator */ + __RW uint32_t SPDCMP2; /* 0x88: Speed comparator */ + __RW uint32_t MATCH_CFG; /* 0x8C: */ + __RW uint32_t FILT_CFG[6]; /* 0x90 - 0xA4: A signal filter config */ + __R uint8_t RESERVED1[88]; /* 0xA8 - 0xFF: Reserved */ + __RW uint32_t QEI_CFG; /* 0x100: qei config register */ + __R uint8_t RESERVED2[12]; /* 0x104 - 0x10F: Reserved */ + __RW uint32_t PULSE0_NUM; /* 0x110: pulse0_num */ + __RW uint32_t PULSE1_NUM; /* 0x114: pulse1_num */ + __R uint32_t CYCLE0_CNT; /* 0x118: cycle0_cnt */ + __R uint32_t CYCLE0PULSE_CNT; /* 0x11C: cycle0pulse_cnt */ + __R uint32_t CYCLE1_CNT; /* 0x120: cycle1_cnt */ + __R uint32_t CYCLE1PULSE_CNT; /* 0x124: cycle1pulse_cnt */ + __R uint32_t CYCLE0_SNAP0; /* 0x128: cycle0_snap0 */ + __R uint32_t CYCLE0_SNAP1; /* 0x12C: cycle0_snap1 */ + __R uint32_t CYCLE1_SNAP0; /* 0x130: cycle1_snap0 */ + __R uint32_t CYCLE1_SNAP1; /* 0x134: cycle1_snap1 */ + __R uint8_t RESERVED3[8]; /* 0x138 - 0x13F: Reserved */ + __RW uint32_t CYCLE0_NUM; /* 0x140: cycle0_num */ + __RW uint32_t CYCLE1_NUM; /* 0x144: cycle1_num */ + __R uint32_t PULSE0_CNT; /* 0x148: pulse0_cnt */ + __R uint32_t PULSE0CYCLE_CNT; /* 0x14C: pulse0cycle_cnt */ + __R uint32_t PULSE1_CNT; /* 0x150: pulse1_cnt */ + __R uint32_t PULSE1CYCLE_CNT; /* 0x154: pulse1cycle_cnt */ + __R uint32_t PULSE0_SNAP0; /* 0x158: pulse0_snap0 */ + __R uint32_t PULSE0CYCLE_SNAP0; /* 0x15C: pulse0cycle_snap0 */ + __R uint32_t PULSE0_SNAP1; /* 0x160: pulse0_snap1 */ + __R uint32_t PULSE0CYCLE_SNAP1; /* 0x164: pulse0cycle_snap1 */ + __R uint32_t PULSE1_SNAP0; /* 0x168: pulse1_snap0 */ + __R uint32_t PULSE1CYCLE_SNAP0; /* 0x16C: pulse1cycle_snap0 */ + __R uint32_t PULSE1_SNAP1; /* 0x170: pulse1_snap1 */ + __R uint32_t PULSE1CYCLE_SNAP1; /* 0x174: pulse1cycle_snap1 */ + __R uint8_t RESERVED4[136]; /* 0x178 - 0x1FF: Reserved */ + __RW uint32_t ADCX_CFG0; /* 0x200: adcx_cfg0 */ + __RW uint32_t ADCX_CFG1; /* 0x204: adcx_cfg1 */ + __RW uint32_t ADCX_CFG2; /* 0x208: adcx_cfg2 */ + __R uint8_t RESERVED5[4]; /* 0x20C - 0x20F: Reserved */ + __RW uint32_t ADCY_CFG0; /* 0x210: adcy_cfg0 */ + __RW uint32_t ADCY_CFG1; /* 0x214: adcy_cfg1 */ + __RW uint32_t ADCY_CFG2; /* 0x218: adcy_cfg2 */ + __R uint8_t RESERVED6[4]; /* 0x21C - 0x21F: Reserved */ + __RW uint32_t CAL_CFG; /* 0x220: cal_cfg */ + __R uint8_t RESERVED7[12]; /* 0x224 - 0x22F: Reserved */ + __RW uint32_t PHASE_PARAM; /* 0x230: phase_param */ + __RW uint32_t ANGLE_ADJ; /* 0x234: angle_adj */ + __RW uint32_t POS_THRESHOLD; /* 0x238: pos_threshold */ + __R uint8_t RESERVED8[4]; /* 0x23C - 0x23F: Reserved */ + __RW uint32_t UVW_POS[6]; /* 0x240 - 0x254: uvw_pos0 */ + __RW uint32_t UVW_POS_CFG[6]; /* 0x258 - 0x26C: */ + __R uint8_t RESERVED9[16]; /* 0x270 - 0x27F: Reserved */ + __RW uint32_t PHASE_CNT; /* 0x280: phase_cnt */ + __W uint32_t PHASE_UPDATE; /* 0x284: phase_update */ + __RW uint32_t POSITION; /* 0x288: position */ + __W uint32_t POSITION_UPDATE; /* 0x28C: position_update */ + __R uint32_t ANGLE; /* 0x290: */ + __RW uint32_t POS_TIMEOUT; /* 0x294: pos_timeout */ +} QEIV2_Type; + + +/* Bitfield definition for register: CR */ +/* + * READ (WO) + * + * 1- load phcnt, zcnt, spdcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 + */ +#define QEIV2_CR_READ_MASK (0x80000000UL) +#define QEIV2_CR_READ_SHIFT (31U) +#define QEIV2_CR_READ_SET(x) (((uint32_t)(x) << QEIV2_CR_READ_SHIFT) & QEIV2_CR_READ_MASK) +#define QEIV2_CR_READ_GET(x) (((uint32_t)(x) & QEIV2_CR_READ_MASK) >> QEIV2_CR_READ_SHIFT) + +/* + * ZCNTCFG (RW) + * + * 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 + * 0- zcnt will increment or decrement when Z input assert + */ +#define QEIV2_CR_ZCNTCFG_MASK (0x400000UL) +#define QEIV2_CR_ZCNTCFG_SHIFT (22U) +#define QEIV2_CR_ZCNTCFG_SET(x) (((uint32_t)(x) << QEIV2_CR_ZCNTCFG_SHIFT) & QEIV2_CR_ZCNTCFG_MASK) +#define QEIV2_CR_ZCNTCFG_GET(x) (((uint32_t)(x) & QEIV2_CR_ZCNTCFG_MASK) >> QEIV2_CR_ZCNTCFG_SHIFT) + +/* + * PHCALIZ (RW) + * + * 1- phcnt will set to phidx when Z input assert(for abz digital signsl) + */ +#define QEIV2_CR_PHCALIZ_MASK (0x200000UL) +#define QEIV2_CR_PHCALIZ_SHIFT (21U) +#define QEIV2_CR_PHCALIZ_SET(x) (((uint32_t)(x) << QEIV2_CR_PHCALIZ_SHIFT) & QEIV2_CR_PHCALIZ_MASK) +#define QEIV2_CR_PHCALIZ_GET(x) (((uint32_t)(x) & QEIV2_CR_PHCALIZ_MASK) >> QEIV2_CR_PHCALIZ_SHIFT) + +/* + * Z_ONLY_EN (RW) + * + * 1- phcnt will set to phidx when Z input assert(for xy analog signal and digital z, also need set phcaliz) + */ +#define QEIV2_CR_Z_ONLY_EN_MASK (0x100000UL) +#define QEIV2_CR_Z_ONLY_EN_SHIFT (20U) +#define QEIV2_CR_Z_ONLY_EN_SET(x) (((uint32_t)(x) << QEIV2_CR_Z_ONLY_EN_SHIFT) & QEIV2_CR_Z_ONLY_EN_MASK) +#define QEIV2_CR_Z_ONLY_EN_GET(x) (((uint32_t)(x) & QEIV2_CR_Z_ONLY_EN_MASK) >> QEIV2_CR_Z_ONLY_EN_SHIFT) + +/* + * H2FDIR0 (RW) + * + */ +#define QEIV2_CR_H2FDIR0_MASK (0x80000UL) +#define QEIV2_CR_H2FDIR0_SHIFT (19U) +#define QEIV2_CR_H2FDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_H2FDIR0_SHIFT) & QEIV2_CR_H2FDIR0_MASK) +#define QEIV2_CR_H2FDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_H2FDIR0_MASK) >> QEIV2_CR_H2FDIR0_SHIFT) + +/* + * H2FDIR1 (RW) + * + */ +#define QEIV2_CR_H2FDIR1_MASK (0x40000UL) +#define QEIV2_CR_H2FDIR1_SHIFT (18U) +#define QEIV2_CR_H2FDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_H2FDIR1_SHIFT) & QEIV2_CR_H2FDIR1_MASK) +#define QEIV2_CR_H2FDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_H2FDIR1_MASK) >> QEIV2_CR_H2FDIR1_SHIFT) + +/* + * H2RDIR0 (RW) + * + */ +#define QEIV2_CR_H2RDIR0_MASK (0x20000UL) +#define QEIV2_CR_H2RDIR0_SHIFT (17U) +#define QEIV2_CR_H2RDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_H2RDIR0_SHIFT) & QEIV2_CR_H2RDIR0_MASK) +#define QEIV2_CR_H2RDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_H2RDIR0_MASK) >> QEIV2_CR_H2RDIR0_SHIFT) + +/* + * H2RDIR1 (RW) + * + */ +#define QEIV2_CR_H2RDIR1_MASK (0x10000UL) +#define QEIV2_CR_H2RDIR1_SHIFT (16U) +#define QEIV2_CR_H2RDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_H2RDIR1_SHIFT) & QEIV2_CR_H2RDIR1_MASK) +#define QEIV2_CR_H2RDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_H2RDIR1_MASK) >> QEIV2_CR_H2RDIR1_SHIFT) + +/* + * PAUSEPOS (RW) + * + * 1- pause position output valid when PAUSE assert + */ +#define QEIV2_CR_PAUSEPOS_MASK (0x8000U) +#define QEIV2_CR_PAUSEPOS_SHIFT (15U) +#define QEIV2_CR_PAUSEPOS_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSEPOS_SHIFT) & QEIV2_CR_PAUSEPOS_MASK) +#define QEIV2_CR_PAUSEPOS_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSEPOS_MASK) >> QEIV2_CR_PAUSEPOS_SHIFT) + +/* + * PAUSESPD (RW) + * + * 1- pause spdcnt when PAUSE assert + */ +#define QEIV2_CR_PAUSESPD_MASK (0x4000U) +#define QEIV2_CR_PAUSESPD_SHIFT (14U) +#define QEIV2_CR_PAUSESPD_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSESPD_SHIFT) & QEIV2_CR_PAUSESPD_MASK) +#define QEIV2_CR_PAUSESPD_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSESPD_MASK) >> QEIV2_CR_PAUSESPD_SHIFT) + +/* + * PAUSEPH (RW) + * + * 1- pause phcnt when PAUSE assert + */ +#define QEIV2_CR_PAUSEPH_MASK (0x2000U) +#define QEIV2_CR_PAUSEPH_SHIFT (13U) +#define QEIV2_CR_PAUSEPH_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSEPH_SHIFT) & QEIV2_CR_PAUSEPH_MASK) +#define QEIV2_CR_PAUSEPH_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSEPH_MASK) >> QEIV2_CR_PAUSEPH_SHIFT) + +/* + * PAUSEZ (RW) + * + * 1- pause zcnt when PAUSE assert + */ +#define QEIV2_CR_PAUSEZ_MASK (0x1000U) +#define QEIV2_CR_PAUSEZ_SHIFT (12U) +#define QEIV2_CR_PAUSEZ_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSEZ_SHIFT) & QEIV2_CR_PAUSEZ_MASK) +#define QEIV2_CR_PAUSEZ_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSEZ_MASK) >> QEIV2_CR_PAUSEZ_SHIFT) + +/* + * HFDIR0 (RW) + * + * 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction) + */ +#define QEIV2_CR_HFDIR0_MASK (0x800U) +#define QEIV2_CR_HFDIR0_SHIFT (11U) +#define QEIV2_CR_HFDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_HFDIR0_SHIFT) & QEIV2_CR_HFDIR0_MASK) +#define QEIV2_CR_HFDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_HFDIR0_MASK) >> QEIV2_CR_HFDIR0_SHIFT) + +/* + * HFDIR1 (RW) + * + * 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction) + */ +#define QEIV2_CR_HFDIR1_MASK (0x400U) +#define QEIV2_CR_HFDIR1_SHIFT (10U) +#define QEIV2_CR_HFDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_HFDIR1_SHIFT) & QEIV2_CR_HFDIR1_MASK) +#define QEIV2_CR_HFDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_HFDIR1_MASK) >> QEIV2_CR_HFDIR1_SHIFT) + +/* + * HRDIR0 (RW) + * + * 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction) + */ +#define QEIV2_CR_HRDIR0_MASK (0x200U) +#define QEIV2_CR_HRDIR0_SHIFT (9U) +#define QEIV2_CR_HRDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_HRDIR0_SHIFT) & QEIV2_CR_HRDIR0_MASK) +#define QEIV2_CR_HRDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_HRDIR0_MASK) >> QEIV2_CR_HRDIR0_SHIFT) + +/* + * HRDIR1 (RW) + * + * 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction) + */ +#define QEIV2_CR_HRDIR1_MASK (0x100U) +#define QEIV2_CR_HRDIR1_SHIFT (8U) +#define QEIV2_CR_HRDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_HRDIR1_SHIFT) & QEIV2_CR_HRDIR1_MASK) +#define QEIV2_CR_HRDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_HRDIR1_MASK) >> QEIV2_CR_HRDIR1_SHIFT) + +/* + * FAULTPOS (RW) + * + */ +#define QEIV2_CR_FAULTPOS_MASK (0x40U) +#define QEIV2_CR_FAULTPOS_SHIFT (6U) +#define QEIV2_CR_FAULTPOS_SET(x) (((uint32_t)(x) << QEIV2_CR_FAULTPOS_SHIFT) & QEIV2_CR_FAULTPOS_MASK) +#define QEIV2_CR_FAULTPOS_GET(x) (((uint32_t)(x) & QEIV2_CR_FAULTPOS_MASK) >> QEIV2_CR_FAULTPOS_SHIFT) + +/* + * SNAPEN (RW) + * + * 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert + */ +#define QEIV2_CR_SNAPEN_MASK (0x20U) +#define QEIV2_CR_SNAPEN_SHIFT (5U) +#define QEIV2_CR_SNAPEN_SET(x) (((uint32_t)(x) << QEIV2_CR_SNAPEN_SHIFT) & QEIV2_CR_SNAPEN_MASK) +#define QEIV2_CR_SNAPEN_GET(x) (((uint32_t)(x) & QEIV2_CR_SNAPEN_MASK) >> QEIV2_CR_SNAPEN_SHIFT) + +/* + * RSTCNT (RW) + * + * 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx + */ +#define QEIV2_CR_RSTCNT_MASK (0x10U) +#define QEIV2_CR_RSTCNT_SHIFT (4U) +#define QEIV2_CR_RSTCNT_SET(x) (((uint32_t)(x) << QEIV2_CR_RSTCNT_SHIFT) & QEIV2_CR_RSTCNT_MASK) +#define QEIV2_CR_RSTCNT_GET(x) (((uint32_t)(x) & QEIV2_CR_RSTCNT_MASK) >> QEIV2_CR_RSTCNT_SHIFT) + +/* + * RD_SEL (RW) + * + * define the width/counter value(affect width_match, width_match2, width_cur, timer_cur, width_read, timer_read, width_snap0,width_snap1, timer_snap0, timer_snap1) + * 0 : same as hpm1000/500/500s; + * 1: use width for position; use timer for angle + */ +#define QEIV2_CR_RD_SEL_MASK (0x8U) +#define QEIV2_CR_RD_SEL_SHIFT (3U) +#define QEIV2_CR_RD_SEL_SET(x) (((uint32_t)(x) << QEIV2_CR_RD_SEL_SHIFT) & QEIV2_CR_RD_SEL_MASK) +#define QEIV2_CR_RD_SEL_GET(x) (((uint32_t)(x) & QEIV2_CR_RD_SEL_MASK) >> QEIV2_CR_RD_SEL_SHIFT) + +/* + * ENCTYP (RW) + * + * 000-abz; 001-pd; 010-ud; 011-UVW(hal) + * 100-single A; 101-single sin; 110: sin&cos + */ +#define QEIV2_CR_ENCTYP_MASK (0x7U) +#define QEIV2_CR_ENCTYP_SHIFT (0U) +#define QEIV2_CR_ENCTYP_SET(x) (((uint32_t)(x) << QEIV2_CR_ENCTYP_SHIFT) & QEIV2_CR_ENCTYP_MASK) +#define QEIV2_CR_ENCTYP_GET(x) (((uint32_t)(x) & QEIV2_CR_ENCTYP_MASK) >> QEIV2_CR_ENCTYP_SHIFT) + +/* Bitfield definition for register: PHCFG */ +/* + * PHMAX (RW) + * + * maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax + */ +#define QEIV2_PHCFG_PHMAX_MASK (0xFFFFFFFFUL) +#define QEIV2_PHCFG_PHMAX_SHIFT (0U) +#define QEIV2_PHCFG_PHMAX_SET(x) (((uint32_t)(x) << QEIV2_PHCFG_PHMAX_SHIFT) & QEIV2_PHCFG_PHMAX_MASK) +#define QEIV2_PHCFG_PHMAX_GET(x) (((uint32_t)(x) & QEIV2_PHCFG_PHMAX_MASK) >> QEIV2_PHCFG_PHMAX_SHIFT) + +/* Bitfield definition for register: WDGCFG */ +/* + * WDGEN (RW) + * + * 1- enable wdog counter + */ +#define QEIV2_WDGCFG_WDGEN_MASK (0x80000000UL) +#define QEIV2_WDGCFG_WDGEN_SHIFT (31U) +#define QEIV2_WDGCFG_WDGEN_SET(x) (((uint32_t)(x) << QEIV2_WDGCFG_WDGEN_SHIFT) & QEIV2_WDGCFG_WDGEN_MASK) +#define QEIV2_WDGCFG_WDGEN_GET(x) (((uint32_t)(x) & QEIV2_WDGCFG_WDGEN_MASK) >> QEIV2_WDGCFG_WDGEN_SHIFT) + +/* + * WDOG_CFG (RW) + * + * define as stop if phase_cnt change is less than it + * if 0, then each change of phase_cnt will clear wdog counter; + * if 2, then phase_cnt change larger than 2 will clear wdog counter + */ +#define QEIV2_WDGCFG_WDOG_CFG_MASK (0x70000000UL) +#define QEIV2_WDGCFG_WDOG_CFG_SHIFT (28U) +#define QEIV2_WDGCFG_WDOG_CFG_SET(x) (((uint32_t)(x) << QEIV2_WDGCFG_WDOG_CFG_SHIFT) & QEIV2_WDGCFG_WDOG_CFG_MASK) +#define QEIV2_WDGCFG_WDOG_CFG_GET(x) (((uint32_t)(x) & QEIV2_WDGCFG_WDOG_CFG_MASK) >> QEIV2_WDGCFG_WDOG_CFG_SHIFT) + +/* + * WDGTO (RW) + * + * watch dog timeout value + */ +#define QEIV2_WDGCFG_WDGTO_MASK (0xFFFFFFFUL) +#define QEIV2_WDGCFG_WDGTO_SHIFT (0U) +#define QEIV2_WDGCFG_WDGTO_SET(x) (((uint32_t)(x) << QEIV2_WDGCFG_WDGTO_SHIFT) & QEIV2_WDGCFG_WDGTO_MASK) +#define QEIV2_WDGCFG_WDGTO_GET(x) (((uint32_t)(x) & QEIV2_WDGCFG_WDGTO_MASK) >> QEIV2_WDGCFG_WDGTO_SHIFT) + +/* Bitfield definition for register: PHIDX */ +/* + * PHIDX (RW) + * + * phcnt reset value, phcnt will reset to phidx when phcaliz set to 1 + */ +#define QEIV2_PHIDX_PHIDX_MASK (0xFFFFFFFFUL) +#define QEIV2_PHIDX_PHIDX_SHIFT (0U) +#define QEIV2_PHIDX_PHIDX_SET(x) (((uint32_t)(x) << QEIV2_PHIDX_PHIDX_SHIFT) & QEIV2_PHIDX_PHIDX_MASK) +#define QEIV2_PHIDX_PHIDX_GET(x) (((uint32_t)(x) & QEIV2_PHIDX_PHIDX_MASK) >> QEIV2_PHIDX_PHIDX_SHIFT) + +/* Bitfield definition for register: TRGOEN */ +/* + * WDGFEN (RW) + * + * 1- enable trigger output when wdg flag set + */ +#define QEIV2_TRGOEN_WDGFEN_MASK (0x80000000UL) +#define QEIV2_TRGOEN_WDGFEN_SHIFT (31U) +#define QEIV2_TRGOEN_WDGFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_WDGFEN_SHIFT) & QEIV2_TRGOEN_WDGFEN_MASK) +#define QEIV2_TRGOEN_WDGFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_WDGFEN_MASK) >> QEIV2_TRGOEN_WDGFEN_SHIFT) + +/* + * HOMEFEN (RW) + * + * 1- enable trigger output when homef flag set + */ +#define QEIV2_TRGOEN_HOMEFEN_MASK (0x40000000UL) +#define QEIV2_TRGOEN_HOMEFEN_SHIFT (30U) +#define QEIV2_TRGOEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_HOMEFEN_SHIFT) & QEIV2_TRGOEN_HOMEFEN_MASK) +#define QEIV2_TRGOEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_HOMEFEN_MASK) >> QEIV2_TRGOEN_HOMEFEN_SHIFT) + +/* + * POSCMPFEN (RW) + * + * 1- enable trigger output when poscmpf flag set + */ +#define QEIV2_TRGOEN_POSCMPFEN_MASK (0x20000000UL) +#define QEIV2_TRGOEN_POSCMPFEN_SHIFT (29U) +#define QEIV2_TRGOEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_POSCMPFEN_SHIFT) & QEIV2_TRGOEN_POSCMPFEN_MASK) +#define QEIV2_TRGOEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_POSCMPFEN_MASK) >> QEIV2_TRGOEN_POSCMPFEN_SHIFT) + +/* + * ZPHFEN (RW) + * + * 1- enable trigger output when zphf flag set + */ +#define QEIV2_TRGOEN_ZPHFEN_MASK (0x10000000UL) +#define QEIV2_TRGOEN_ZPHFEN_SHIFT (28U) +#define QEIV2_TRGOEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_ZPHFEN_SHIFT) & QEIV2_TRGOEN_ZPHFEN_MASK) +#define QEIV2_TRGOEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_ZPHFEN_MASK) >> QEIV2_TRGOEN_ZPHFEN_SHIFT) + +/* + * ZMISSFEN (RW) + * + */ +#define QEIV2_TRGOEN_ZMISSFEN_MASK (0x8000000UL) +#define QEIV2_TRGOEN_ZMISSFEN_SHIFT (27U) +#define QEIV2_TRGOEN_ZMISSFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_ZMISSFEN_SHIFT) & QEIV2_TRGOEN_ZMISSFEN_MASK) +#define QEIV2_TRGOEN_ZMISSFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_ZMISSFEN_MASK) >> QEIV2_TRGOEN_ZMISSFEN_SHIFT) + +/* + * WIDTHTMFEN (RW) + * + */ +#define QEIV2_TRGOEN_WIDTHTMFEN_MASK (0x4000000UL) +#define QEIV2_TRGOEN_WIDTHTMFEN_SHIFT (26U) +#define QEIV2_TRGOEN_WIDTHTMFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_WIDTHTMFEN_SHIFT) & QEIV2_TRGOEN_WIDTHTMFEN_MASK) +#define QEIV2_TRGOEN_WIDTHTMFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_WIDTHTMFEN_MASK) >> QEIV2_TRGOEN_WIDTHTMFEN_SHIFT) + +/* + * POS2CMPFEN (RW) + * + */ +#define QEIV2_TRGOEN_POS2CMPFEN_MASK (0x2000000UL) +#define QEIV2_TRGOEN_POS2CMPFEN_SHIFT (25U) +#define QEIV2_TRGOEN_POS2CMPFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_POS2CMPFEN_SHIFT) & QEIV2_TRGOEN_POS2CMPFEN_MASK) +#define QEIV2_TRGOEN_POS2CMPFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_POS2CMPFEN_MASK) >> QEIV2_TRGOEN_POS2CMPFEN_SHIFT) + +/* + * DIRCHGFEN (RW) + * + */ +#define QEIV2_TRGOEN_DIRCHGFEN_MASK (0x1000000UL) +#define QEIV2_TRGOEN_DIRCHGFEN_SHIFT (24U) +#define QEIV2_TRGOEN_DIRCHGFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_DIRCHGFEN_SHIFT) & QEIV2_TRGOEN_DIRCHGFEN_MASK) +#define QEIV2_TRGOEN_DIRCHGFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_DIRCHGFEN_MASK) >> QEIV2_TRGOEN_DIRCHGFEN_SHIFT) + +/* + * CYCLE0FEN (RW) + * + */ +#define QEIV2_TRGOEN_CYCLE0FEN_MASK (0x800000UL) +#define QEIV2_TRGOEN_CYCLE0FEN_SHIFT (23U) +#define QEIV2_TRGOEN_CYCLE0FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_CYCLE0FEN_SHIFT) & QEIV2_TRGOEN_CYCLE0FEN_MASK) +#define QEIV2_TRGOEN_CYCLE0FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_CYCLE0FEN_MASK) >> QEIV2_TRGOEN_CYCLE0FEN_SHIFT) + +/* + * CYCLE1FEN (RW) + * + */ +#define QEIV2_TRGOEN_CYCLE1FEN_MASK (0x400000UL) +#define QEIV2_TRGOEN_CYCLE1FEN_SHIFT (22U) +#define QEIV2_TRGOEN_CYCLE1FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_CYCLE1FEN_SHIFT) & QEIV2_TRGOEN_CYCLE1FEN_MASK) +#define QEIV2_TRGOEN_CYCLE1FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_CYCLE1FEN_MASK) >> QEIV2_TRGOEN_CYCLE1FEN_SHIFT) + +/* + * PULSE0FEN (RW) + * + */ +#define QEIV2_TRGOEN_PULSE0FEN_MASK (0x200000UL) +#define QEIV2_TRGOEN_PULSE0FEN_SHIFT (21U) +#define QEIV2_TRGOEN_PULSE0FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_PULSE0FEN_SHIFT) & QEIV2_TRGOEN_PULSE0FEN_MASK) +#define QEIV2_TRGOEN_PULSE0FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_PULSE0FEN_MASK) >> QEIV2_TRGOEN_PULSE0FEN_SHIFT) + +/* + * PULSE1FEN (RW) + * + */ +#define QEIV2_TRGOEN_PULSE1FEN_MASK (0x100000UL) +#define QEIV2_TRGOEN_PULSE1FEN_SHIFT (20U) +#define QEIV2_TRGOEN_PULSE1FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_PULSE1FEN_SHIFT) & QEIV2_TRGOEN_PULSE1FEN_MASK) +#define QEIV2_TRGOEN_PULSE1FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_PULSE1FEN_MASK) >> QEIV2_TRGOEN_PULSE1FEN_SHIFT) + +/* + * HOME2FEN (RW) + * + */ +#define QEIV2_TRGOEN_HOME2FEN_MASK (0x80000UL) +#define QEIV2_TRGOEN_HOME2FEN_SHIFT (19U) +#define QEIV2_TRGOEN_HOME2FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_HOME2FEN_SHIFT) & QEIV2_TRGOEN_HOME2FEN_MASK) +#define QEIV2_TRGOEN_HOME2FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_HOME2FEN_MASK) >> QEIV2_TRGOEN_HOME2FEN_SHIFT) + +/* + * FAULTFEN (RW) + * + */ +#define QEIV2_TRGOEN_FAULTFEN_MASK (0x40000UL) +#define QEIV2_TRGOEN_FAULTFEN_SHIFT (18U) +#define QEIV2_TRGOEN_FAULTFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_FAULTFEN_SHIFT) & QEIV2_TRGOEN_FAULTFEN_MASK) +#define QEIV2_TRGOEN_FAULTFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_FAULTFEN_MASK) >> QEIV2_TRGOEN_FAULTFEN_SHIFT) + +/* Bitfield definition for register: READEN */ +/* + * WDGFEN (RW) + * + * 1- load counters to their read registers when wdg flag set + */ +#define QEIV2_READEN_WDGFEN_MASK (0x80000000UL) +#define QEIV2_READEN_WDGFEN_SHIFT (31U) +#define QEIV2_READEN_WDGFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_WDGFEN_SHIFT) & QEIV2_READEN_WDGFEN_MASK) +#define QEIV2_READEN_WDGFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_WDGFEN_MASK) >> QEIV2_READEN_WDGFEN_SHIFT) + +/* + * HOMEFEN (RW) + * + * 1- load counters to their read registers when homef flag set + */ +#define QEIV2_READEN_HOMEFEN_MASK (0x40000000UL) +#define QEIV2_READEN_HOMEFEN_SHIFT (30U) +#define QEIV2_READEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_HOMEFEN_SHIFT) & QEIV2_READEN_HOMEFEN_MASK) +#define QEIV2_READEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_HOMEFEN_MASK) >> QEIV2_READEN_HOMEFEN_SHIFT) + +/* + * POSCMPFEN (RW) + * + * 1- load counters to their read registers when poscmpf flag set + */ +#define QEIV2_READEN_POSCMPFEN_MASK (0x20000000UL) +#define QEIV2_READEN_POSCMPFEN_SHIFT (29U) +#define QEIV2_READEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_POSCMPFEN_SHIFT) & QEIV2_READEN_POSCMPFEN_MASK) +#define QEIV2_READEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_POSCMPFEN_MASK) >> QEIV2_READEN_POSCMPFEN_SHIFT) + +/* + * ZPHFEN (RW) + * + * 1- load counters to their read registers when zphf flag set + */ +#define QEIV2_READEN_ZPHFEN_MASK (0x10000000UL) +#define QEIV2_READEN_ZPHFEN_SHIFT (28U) +#define QEIV2_READEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_ZPHFEN_SHIFT) & QEIV2_READEN_ZPHFEN_MASK) +#define QEIV2_READEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_ZPHFEN_MASK) >> QEIV2_READEN_ZPHFEN_SHIFT) + +/* + * ZMISSFEN (RW) + * + */ +#define QEIV2_READEN_ZMISSFEN_MASK (0x8000000UL) +#define QEIV2_READEN_ZMISSFEN_SHIFT (27U) +#define QEIV2_READEN_ZMISSFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_ZMISSFEN_SHIFT) & QEIV2_READEN_ZMISSFEN_MASK) +#define QEIV2_READEN_ZMISSFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_ZMISSFEN_MASK) >> QEIV2_READEN_ZMISSFEN_SHIFT) + +/* + * WIDTHTMFEN (RW) + * + */ +#define QEIV2_READEN_WIDTHTMFEN_MASK (0x4000000UL) +#define QEIV2_READEN_WIDTHTMFEN_SHIFT (26U) +#define QEIV2_READEN_WIDTHTMFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_WIDTHTMFEN_SHIFT) & QEIV2_READEN_WIDTHTMFEN_MASK) +#define QEIV2_READEN_WIDTHTMFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_WIDTHTMFEN_MASK) >> QEIV2_READEN_WIDTHTMFEN_SHIFT) + +/* + * POS2CMPFEN (RW) + * + */ +#define QEIV2_READEN_POS2CMPFEN_MASK (0x2000000UL) +#define QEIV2_READEN_POS2CMPFEN_SHIFT (25U) +#define QEIV2_READEN_POS2CMPFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_POS2CMPFEN_SHIFT) & QEIV2_READEN_POS2CMPFEN_MASK) +#define QEIV2_READEN_POS2CMPFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_POS2CMPFEN_MASK) >> QEIV2_READEN_POS2CMPFEN_SHIFT) + +/* + * DIRCHGFEN (RW) + * + */ +#define QEIV2_READEN_DIRCHGFEN_MASK (0x1000000UL) +#define QEIV2_READEN_DIRCHGFEN_SHIFT (24U) +#define QEIV2_READEN_DIRCHGFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_DIRCHGFEN_SHIFT) & QEIV2_READEN_DIRCHGFEN_MASK) +#define QEIV2_READEN_DIRCHGFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_DIRCHGFEN_MASK) >> QEIV2_READEN_DIRCHGFEN_SHIFT) + +/* + * CYCLE0FEN (RW) + * + */ +#define QEIV2_READEN_CYCLE0FEN_MASK (0x800000UL) +#define QEIV2_READEN_CYCLE0FEN_SHIFT (23U) +#define QEIV2_READEN_CYCLE0FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_CYCLE0FEN_SHIFT) & QEIV2_READEN_CYCLE0FEN_MASK) +#define QEIV2_READEN_CYCLE0FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_CYCLE0FEN_MASK) >> QEIV2_READEN_CYCLE0FEN_SHIFT) + +/* + * CYCLE1FEN (RW) + * + */ +#define QEIV2_READEN_CYCLE1FEN_MASK (0x400000UL) +#define QEIV2_READEN_CYCLE1FEN_SHIFT (22U) +#define QEIV2_READEN_CYCLE1FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_CYCLE1FEN_SHIFT) & QEIV2_READEN_CYCLE1FEN_MASK) +#define QEIV2_READEN_CYCLE1FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_CYCLE1FEN_MASK) >> QEIV2_READEN_CYCLE1FEN_SHIFT) + +/* + * PULSE0FEN (RW) + * + */ +#define QEIV2_READEN_PULSE0FEN_MASK (0x200000UL) +#define QEIV2_READEN_PULSE0FEN_SHIFT (21U) +#define QEIV2_READEN_PULSE0FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_PULSE0FEN_SHIFT) & QEIV2_READEN_PULSE0FEN_MASK) +#define QEIV2_READEN_PULSE0FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_PULSE0FEN_MASK) >> QEIV2_READEN_PULSE0FEN_SHIFT) + +/* + * PULSE1FEN (RW) + * + */ +#define QEIV2_READEN_PULSE1FEN_MASK (0x100000UL) +#define QEIV2_READEN_PULSE1FEN_SHIFT (20U) +#define QEIV2_READEN_PULSE1FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_PULSE1FEN_SHIFT) & QEIV2_READEN_PULSE1FEN_MASK) +#define QEIV2_READEN_PULSE1FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_PULSE1FEN_MASK) >> QEIV2_READEN_PULSE1FEN_SHIFT) + +/* + * HOME2FEN (RW) + * + */ +#define QEIV2_READEN_HOME2FEN_MASK (0x80000UL) +#define QEIV2_READEN_HOME2FEN_SHIFT (19U) +#define QEIV2_READEN_HOME2FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_HOME2FEN_SHIFT) & QEIV2_READEN_HOME2FEN_MASK) +#define QEIV2_READEN_HOME2FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_HOME2FEN_MASK) >> QEIV2_READEN_HOME2FEN_SHIFT) + +/* + * FAULTFEN (RW) + * + */ +#define QEIV2_READEN_FAULTFEN_MASK (0x40000UL) +#define QEIV2_READEN_FAULTFEN_SHIFT (18U) +#define QEIV2_READEN_FAULTFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_FAULTFEN_SHIFT) & QEIV2_READEN_FAULTFEN_MASK) +#define QEIV2_READEN_FAULTFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_FAULTFEN_MASK) >> QEIV2_READEN_FAULTFEN_SHIFT) + +/* Bitfield definition for register: ZCMP */ +/* + * ZCMP (RW) + * + * zcnt postion compare value + */ +#define QEIV2_ZCMP_ZCMP_MASK (0xFFFFFFFFUL) +#define QEIV2_ZCMP_ZCMP_SHIFT (0U) +#define QEIV2_ZCMP_ZCMP_SET(x) (((uint32_t)(x) << QEIV2_ZCMP_ZCMP_SHIFT) & QEIV2_ZCMP_ZCMP_MASK) +#define QEIV2_ZCMP_ZCMP_GET(x) (((uint32_t)(x) & QEIV2_ZCMP_ZCMP_MASK) >> QEIV2_ZCMP_ZCMP_SHIFT) + +/* Bitfield definition for register: PHCMP */ +/* + * PHCMP (RW) + * + * phcnt position compare value + */ +#define QEIV2_PHCMP_PHCMP_MASK (0xFFFFFFFFUL) +#define QEIV2_PHCMP_PHCMP_SHIFT (0U) +#define QEIV2_PHCMP_PHCMP_SET(x) (((uint32_t)(x) << QEIV2_PHCMP_PHCMP_SHIFT) & QEIV2_PHCMP_PHCMP_MASK) +#define QEIV2_PHCMP_PHCMP_GET(x) (((uint32_t)(x) & QEIV2_PHCMP_PHCMP_MASK) >> QEIV2_PHCMP_PHCMP_SHIFT) + +/* Bitfield definition for register: SPDCMP */ +/* + * SPDCMP (RW) + * + * spdcnt position compare value + */ +#define QEIV2_SPDCMP_SPDCMP_MASK (0xFFFFFFFFUL) +#define QEIV2_SPDCMP_SPDCMP_SHIFT (0U) +#define QEIV2_SPDCMP_SPDCMP_SET(x) (((uint32_t)(x) << QEIV2_SPDCMP_SPDCMP_SHIFT) & QEIV2_SPDCMP_SPDCMP_MASK) +#define QEIV2_SPDCMP_SPDCMP_GET(x) (((uint32_t)(x) & QEIV2_SPDCMP_SPDCMP_MASK) >> QEIV2_SPDCMP_SPDCMP_SHIFT) + +/* Bitfield definition for register: DMAEN */ +/* + * WDGFEN (RW) + * + * 1- generate dma request when wdg flag set + */ +#define QEIV2_DMAEN_WDGFEN_MASK (0x80000000UL) +#define QEIV2_DMAEN_WDGFEN_SHIFT (31U) +#define QEIV2_DMAEN_WDGFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_WDGFEN_SHIFT) & QEIV2_DMAEN_WDGFEN_MASK) +#define QEIV2_DMAEN_WDGFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_WDGFEN_MASK) >> QEIV2_DMAEN_WDGFEN_SHIFT) + +/* + * HOMEFEN (RW) + * + * 1- generate dma request when homef flag set + */ +#define QEIV2_DMAEN_HOMEFEN_MASK (0x40000000UL) +#define QEIV2_DMAEN_HOMEFEN_SHIFT (30U) +#define QEIV2_DMAEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_HOMEFEN_SHIFT) & QEIV2_DMAEN_HOMEFEN_MASK) +#define QEIV2_DMAEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_HOMEFEN_MASK) >> QEIV2_DMAEN_HOMEFEN_SHIFT) + +/* + * POSCMPFEN (RW) + * + * 1- generate dma request when poscmpf flag set + */ +#define QEIV2_DMAEN_POSCMPFEN_MASK (0x20000000UL) +#define QEIV2_DMAEN_POSCMPFEN_SHIFT (29U) +#define QEIV2_DMAEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_POSCMPFEN_SHIFT) & QEIV2_DMAEN_POSCMPFEN_MASK) +#define QEIV2_DMAEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_POSCMPFEN_MASK) >> QEIV2_DMAEN_POSCMPFEN_SHIFT) + +/* + * ZPHFEN (RW) + * + * 1- generate dma request when zphf flag set + */ +#define QEIV2_DMAEN_ZPHFEN_MASK (0x10000000UL) +#define QEIV2_DMAEN_ZPHFEN_SHIFT (28U) +#define QEIV2_DMAEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_ZPHFEN_SHIFT) & QEIV2_DMAEN_ZPHFEN_MASK) +#define QEIV2_DMAEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_ZPHFEN_MASK) >> QEIV2_DMAEN_ZPHFEN_SHIFT) + +/* + * ZMISSFEN (RW) + * + */ +#define QEIV2_DMAEN_ZMISSFEN_MASK (0x8000000UL) +#define QEIV2_DMAEN_ZMISSFEN_SHIFT (27U) +#define QEIV2_DMAEN_ZMISSFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_ZMISSFEN_SHIFT) & QEIV2_DMAEN_ZMISSFEN_MASK) +#define QEIV2_DMAEN_ZMISSFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_ZMISSFEN_MASK) >> QEIV2_DMAEN_ZMISSFEN_SHIFT) + +/* + * WIDTHTMFEN (RW) + * + */ +#define QEIV2_DMAEN_WIDTHTMFEN_MASK (0x4000000UL) +#define QEIV2_DMAEN_WIDTHTMFEN_SHIFT (26U) +#define QEIV2_DMAEN_WIDTHTMFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_WIDTHTMFEN_SHIFT) & QEIV2_DMAEN_WIDTHTMFEN_MASK) +#define QEIV2_DMAEN_WIDTHTMFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_WIDTHTMFEN_MASK) >> QEIV2_DMAEN_WIDTHTMFEN_SHIFT) + +/* + * POS2CMPFEN (RW) + * + */ +#define QEIV2_DMAEN_POS2CMPFEN_MASK (0x2000000UL) +#define QEIV2_DMAEN_POS2CMPFEN_SHIFT (25U) +#define QEIV2_DMAEN_POS2CMPFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_POS2CMPFEN_SHIFT) & QEIV2_DMAEN_POS2CMPFEN_MASK) +#define QEIV2_DMAEN_POS2CMPFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_POS2CMPFEN_MASK) >> QEIV2_DMAEN_POS2CMPFEN_SHIFT) + +/* + * DIRCHGFEN (RW) + * + */ +#define QEIV2_DMAEN_DIRCHGFEN_MASK (0x1000000UL) +#define QEIV2_DMAEN_DIRCHGFEN_SHIFT (24U) +#define QEIV2_DMAEN_DIRCHGFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_DIRCHGFEN_SHIFT) & QEIV2_DMAEN_DIRCHGFEN_MASK) +#define QEIV2_DMAEN_DIRCHGFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_DIRCHGFEN_MASK) >> QEIV2_DMAEN_DIRCHGFEN_SHIFT) + +/* + * CYCLE0FEN (RW) + * + */ +#define QEIV2_DMAEN_CYCLE0FEN_MASK (0x800000UL) +#define QEIV2_DMAEN_CYCLE0FEN_SHIFT (23U) +#define QEIV2_DMAEN_CYCLE0FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_CYCLE0FEN_SHIFT) & QEIV2_DMAEN_CYCLE0FEN_MASK) +#define QEIV2_DMAEN_CYCLE0FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_CYCLE0FEN_MASK) >> QEIV2_DMAEN_CYCLE0FEN_SHIFT) + +/* + * CYCLE1FEN (RW) + * + */ +#define QEIV2_DMAEN_CYCLE1FEN_MASK (0x400000UL) +#define QEIV2_DMAEN_CYCLE1FEN_SHIFT (22U) +#define QEIV2_DMAEN_CYCLE1FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_CYCLE1FEN_SHIFT) & QEIV2_DMAEN_CYCLE1FEN_MASK) +#define QEIV2_DMAEN_CYCLE1FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_CYCLE1FEN_MASK) >> QEIV2_DMAEN_CYCLE1FEN_SHIFT) + +/* + * PULSE0FEN (RW) + * + */ +#define QEIV2_DMAEN_PULSE0FEN_MASK (0x200000UL) +#define QEIV2_DMAEN_PULSE0FEN_SHIFT (21U) +#define QEIV2_DMAEN_PULSE0FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_PULSE0FEN_SHIFT) & QEIV2_DMAEN_PULSE0FEN_MASK) +#define QEIV2_DMAEN_PULSE0FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_PULSE0FEN_MASK) >> QEIV2_DMAEN_PULSE0FEN_SHIFT) + +/* + * PULSE1FEN (RW) + * + */ +#define QEIV2_DMAEN_PULSE1FEN_MASK (0x100000UL) +#define QEIV2_DMAEN_PULSE1FEN_SHIFT (20U) +#define QEIV2_DMAEN_PULSE1FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_PULSE1FEN_SHIFT) & QEIV2_DMAEN_PULSE1FEN_MASK) +#define QEIV2_DMAEN_PULSE1FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_PULSE1FEN_MASK) >> QEIV2_DMAEN_PULSE1FEN_SHIFT) + +/* + * HOME2FEN (RW) + * + */ +#define QEIV2_DMAEN_HOME2FEN_MASK (0x80000UL) +#define QEIV2_DMAEN_HOME2FEN_SHIFT (19U) +#define QEIV2_DMAEN_HOME2FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_HOME2FEN_SHIFT) & QEIV2_DMAEN_HOME2FEN_MASK) +#define QEIV2_DMAEN_HOME2FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_HOME2FEN_MASK) >> QEIV2_DMAEN_HOME2FEN_SHIFT) + +/* + * FAULTFEN (RW) + * + */ +#define QEIV2_DMAEN_FAULTFEN_MASK (0x40000UL) +#define QEIV2_DMAEN_FAULTFEN_SHIFT (18U) +#define QEIV2_DMAEN_FAULTFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_FAULTFEN_SHIFT) & QEIV2_DMAEN_FAULTFEN_MASK) +#define QEIV2_DMAEN_FAULTFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_FAULTFEN_MASK) >> QEIV2_DMAEN_FAULTFEN_SHIFT) + +/* Bitfield definition for register: SR */ +/* + * WDGF (RW) + * + * watchdog flag + */ +#define QEIV2_SR_WDGF_MASK (0x80000000UL) +#define QEIV2_SR_WDGF_SHIFT (31U) +#define QEIV2_SR_WDGF_SET(x) (((uint32_t)(x) << QEIV2_SR_WDGF_SHIFT) & QEIV2_SR_WDGF_MASK) +#define QEIV2_SR_WDGF_GET(x) (((uint32_t)(x) & QEIV2_SR_WDGF_MASK) >> QEIV2_SR_WDGF_SHIFT) + +/* + * HOMEF (RW) + * + * home flag + */ +#define QEIV2_SR_HOMEF_MASK (0x40000000UL) +#define QEIV2_SR_HOMEF_SHIFT (30U) +#define QEIV2_SR_HOMEF_SET(x) (((uint32_t)(x) << QEIV2_SR_HOMEF_SHIFT) & QEIV2_SR_HOMEF_MASK) +#define QEIV2_SR_HOMEF_GET(x) (((uint32_t)(x) & QEIV2_SR_HOMEF_MASK) >> QEIV2_SR_HOMEF_SHIFT) + +/* + * POSCMPF (RW) + * + * postion compare match flag + */ +#define QEIV2_SR_POSCMPF_MASK (0x20000000UL) +#define QEIV2_SR_POSCMPF_SHIFT (29U) +#define QEIV2_SR_POSCMPF_SET(x) (((uint32_t)(x) << QEIV2_SR_POSCMPF_SHIFT) & QEIV2_SR_POSCMPF_MASK) +#define QEIV2_SR_POSCMPF_GET(x) (((uint32_t)(x) & QEIV2_SR_POSCMPF_MASK) >> QEIV2_SR_POSCMPF_SHIFT) + +/* + * ZPHF (RW) + * + * z input flag + */ +#define QEIV2_SR_ZPHF_MASK (0x10000000UL) +#define QEIV2_SR_ZPHF_SHIFT (28U) +#define QEIV2_SR_ZPHF_SET(x) (((uint32_t)(x) << QEIV2_SR_ZPHF_SHIFT) & QEIV2_SR_ZPHF_MASK) +#define QEIV2_SR_ZPHF_GET(x) (((uint32_t)(x) & QEIV2_SR_ZPHF_MASK) >> QEIV2_SR_ZPHF_SHIFT) + +/* + * ZMISSF (RW) + * + */ +#define QEIV2_SR_ZMISSF_MASK (0x8000000UL) +#define QEIV2_SR_ZMISSF_SHIFT (27U) +#define QEIV2_SR_ZMISSF_SET(x) (((uint32_t)(x) << QEIV2_SR_ZMISSF_SHIFT) & QEIV2_SR_ZMISSF_MASK) +#define QEIV2_SR_ZMISSF_GET(x) (((uint32_t)(x) & QEIV2_SR_ZMISSF_MASK) >> QEIV2_SR_ZMISSF_SHIFT) + +/* + * WIDTHTMF (RW) + * + */ +#define QEIV2_SR_WIDTHTMF_MASK (0x4000000UL) +#define QEIV2_SR_WIDTHTMF_SHIFT (26U) +#define QEIV2_SR_WIDTHTMF_SET(x) (((uint32_t)(x) << QEIV2_SR_WIDTHTMF_SHIFT) & QEIV2_SR_WIDTHTMF_MASK) +#define QEIV2_SR_WIDTHTMF_GET(x) (((uint32_t)(x) & QEIV2_SR_WIDTHTMF_MASK) >> QEIV2_SR_WIDTHTMF_SHIFT) + +/* + * POS2CMPF (RW) + * + */ +#define QEIV2_SR_POS2CMPF_MASK (0x2000000UL) +#define QEIV2_SR_POS2CMPF_SHIFT (25U) +#define QEIV2_SR_POS2CMPF_SET(x) (((uint32_t)(x) << QEIV2_SR_POS2CMPF_SHIFT) & QEIV2_SR_POS2CMPF_MASK) +#define QEIV2_SR_POS2CMPF_GET(x) (((uint32_t)(x) & QEIV2_SR_POS2CMPF_MASK) >> QEIV2_SR_POS2CMPF_SHIFT) + +/* + * DIRCHGF (RW) + * + */ +#define QEIV2_SR_DIRCHGF_MASK (0x1000000UL) +#define QEIV2_SR_DIRCHGF_SHIFT (24U) +#define QEIV2_SR_DIRCHGF_SET(x) (((uint32_t)(x) << QEIV2_SR_DIRCHGF_SHIFT) & QEIV2_SR_DIRCHGF_MASK) +#define QEIV2_SR_DIRCHGF_GET(x) (((uint32_t)(x) & QEIV2_SR_DIRCHGF_MASK) >> QEIV2_SR_DIRCHGF_SHIFT) + +/* + * CYCLE0F (RW) + * + */ +#define QEIV2_SR_CYCLE0F_MASK (0x800000UL) +#define QEIV2_SR_CYCLE0F_SHIFT (23U) +#define QEIV2_SR_CYCLE0F_SET(x) (((uint32_t)(x) << QEIV2_SR_CYCLE0F_SHIFT) & QEIV2_SR_CYCLE0F_MASK) +#define QEIV2_SR_CYCLE0F_GET(x) (((uint32_t)(x) & QEIV2_SR_CYCLE0F_MASK) >> QEIV2_SR_CYCLE0F_SHIFT) + +/* + * CYCLE1F (RW) + * + */ +#define QEIV2_SR_CYCLE1F_MASK (0x400000UL) +#define QEIV2_SR_CYCLE1F_SHIFT (22U) +#define QEIV2_SR_CYCLE1F_SET(x) (((uint32_t)(x) << QEIV2_SR_CYCLE1F_SHIFT) & QEIV2_SR_CYCLE1F_MASK) +#define QEIV2_SR_CYCLE1F_GET(x) (((uint32_t)(x) & QEIV2_SR_CYCLE1F_MASK) >> QEIV2_SR_CYCLE1F_SHIFT) + +/* + * PULSE0F (RW) + * + */ +#define QEIV2_SR_PULSE0F_MASK (0x200000UL) +#define QEIV2_SR_PULSE0F_SHIFT (21U) +#define QEIV2_SR_PULSE0F_SET(x) (((uint32_t)(x) << QEIV2_SR_PULSE0F_SHIFT) & QEIV2_SR_PULSE0F_MASK) +#define QEIV2_SR_PULSE0F_GET(x) (((uint32_t)(x) & QEIV2_SR_PULSE0F_MASK) >> QEIV2_SR_PULSE0F_SHIFT) + +/* + * PULSE1F (RW) + * + */ +#define QEIV2_SR_PULSE1F_MASK (0x100000UL) +#define QEIV2_SR_PULSE1F_SHIFT (20U) +#define QEIV2_SR_PULSE1F_SET(x) (((uint32_t)(x) << QEIV2_SR_PULSE1F_SHIFT) & QEIV2_SR_PULSE1F_MASK) +#define QEIV2_SR_PULSE1F_GET(x) (((uint32_t)(x) & QEIV2_SR_PULSE1F_MASK) >> QEIV2_SR_PULSE1F_SHIFT) + +/* + * HOME2F (RW) + * + */ +#define QEIV2_SR_HOME2F_MASK (0x80000UL) +#define QEIV2_SR_HOME2F_SHIFT (19U) +#define QEIV2_SR_HOME2F_SET(x) (((uint32_t)(x) << QEIV2_SR_HOME2F_SHIFT) & QEIV2_SR_HOME2F_MASK) +#define QEIV2_SR_HOME2F_GET(x) (((uint32_t)(x) & QEIV2_SR_HOME2F_MASK) >> QEIV2_SR_HOME2F_SHIFT) + +/* + * FAULTF (RW) + * + */ +#define QEIV2_SR_FAULTF_MASK (0x40000UL) +#define QEIV2_SR_FAULTF_SHIFT (18U) +#define QEIV2_SR_FAULTF_SET(x) (((uint32_t)(x) << QEIV2_SR_FAULTF_SHIFT) & QEIV2_SR_FAULTF_MASK) +#define QEIV2_SR_FAULTF_GET(x) (((uint32_t)(x) & QEIV2_SR_FAULTF_MASK) >> QEIV2_SR_FAULTF_SHIFT) + +/* Bitfield definition for register: IRQEN */ +/* + * WDGIE (RW) + * + * 1- generate interrupt when wdg flag set + */ +#define QEIV2_IRQEN_WDGIE_MASK (0x80000000UL) +#define QEIV2_IRQEN_WDGIE_SHIFT (31U) +#define QEIV2_IRQEN_WDGIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_WDGIE_SHIFT) & QEIV2_IRQEN_WDGIE_MASK) +#define QEIV2_IRQEN_WDGIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_WDGIE_MASK) >> QEIV2_IRQEN_WDGIE_SHIFT) + +/* + * HOMEIE (RW) + * + * 1- generate interrupt when homef flag set + */ +#define QEIV2_IRQEN_HOMEIE_MASK (0x40000000UL) +#define QEIV2_IRQEN_HOMEIE_SHIFT (30U) +#define QEIV2_IRQEN_HOMEIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_HOMEIE_SHIFT) & QEIV2_IRQEN_HOMEIE_MASK) +#define QEIV2_IRQEN_HOMEIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_HOMEIE_MASK) >> QEIV2_IRQEN_HOMEIE_SHIFT) + +/* + * POSCMPIE (RW) + * + * 1- generate interrupt when poscmpf flag set + */ +#define QEIV2_IRQEN_POSCMPIE_MASK (0x20000000UL) +#define QEIV2_IRQEN_POSCMPIE_SHIFT (29U) +#define QEIV2_IRQEN_POSCMPIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_POSCMPIE_SHIFT) & QEIV2_IRQEN_POSCMPIE_MASK) +#define QEIV2_IRQEN_POSCMPIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_POSCMPIE_MASK) >> QEIV2_IRQEN_POSCMPIE_SHIFT) + +/* + * ZPHIE (RW) + * + * 1- generate interrupt when zphf flag set + */ +#define QEIV2_IRQEN_ZPHIE_MASK (0x10000000UL) +#define QEIV2_IRQEN_ZPHIE_SHIFT (28U) +#define QEIV2_IRQEN_ZPHIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_ZPHIE_SHIFT) & QEIV2_IRQEN_ZPHIE_MASK) +#define QEIV2_IRQEN_ZPHIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_ZPHIE_MASK) >> QEIV2_IRQEN_ZPHIE_SHIFT) + +/* + * ZMISSE (RW) + * + */ +#define QEIV2_IRQEN_ZMISSE_MASK (0x8000000UL) +#define QEIV2_IRQEN_ZMISSE_SHIFT (27U) +#define QEIV2_IRQEN_ZMISSE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_ZMISSE_SHIFT) & QEIV2_IRQEN_ZMISSE_MASK) +#define QEIV2_IRQEN_ZMISSE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_ZMISSE_MASK) >> QEIV2_IRQEN_ZMISSE_SHIFT) + +/* + * WIDTHTME (RW) + * + */ +#define QEIV2_IRQEN_WIDTHTME_MASK (0x4000000UL) +#define QEIV2_IRQEN_WIDTHTME_SHIFT (26U) +#define QEIV2_IRQEN_WIDTHTME_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_WIDTHTME_SHIFT) & QEIV2_IRQEN_WIDTHTME_MASK) +#define QEIV2_IRQEN_WIDTHTME_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_WIDTHTME_MASK) >> QEIV2_IRQEN_WIDTHTME_SHIFT) + +/* + * POS2CMPE (RW) + * + */ +#define QEIV2_IRQEN_POS2CMPE_MASK (0x2000000UL) +#define QEIV2_IRQEN_POS2CMPE_SHIFT (25U) +#define QEIV2_IRQEN_POS2CMPE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_POS2CMPE_SHIFT) & QEIV2_IRQEN_POS2CMPE_MASK) +#define QEIV2_IRQEN_POS2CMPE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_POS2CMPE_MASK) >> QEIV2_IRQEN_POS2CMPE_SHIFT) + +/* + * DIRCHGE (RW) + * + */ +#define QEIV2_IRQEN_DIRCHGE_MASK (0x1000000UL) +#define QEIV2_IRQEN_DIRCHGE_SHIFT (24U) +#define QEIV2_IRQEN_DIRCHGE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_DIRCHGE_SHIFT) & QEIV2_IRQEN_DIRCHGE_MASK) +#define QEIV2_IRQEN_DIRCHGE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_DIRCHGE_MASK) >> QEIV2_IRQEN_DIRCHGE_SHIFT) + +/* + * CYCLE0E (RW) + * + */ +#define QEIV2_IRQEN_CYCLE0E_MASK (0x800000UL) +#define QEIV2_IRQEN_CYCLE0E_SHIFT (23U) +#define QEIV2_IRQEN_CYCLE0E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_CYCLE0E_SHIFT) & QEIV2_IRQEN_CYCLE0E_MASK) +#define QEIV2_IRQEN_CYCLE0E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_CYCLE0E_MASK) >> QEIV2_IRQEN_CYCLE0E_SHIFT) + +/* + * CYCLE1E (RW) + * + */ +#define QEIV2_IRQEN_CYCLE1E_MASK (0x400000UL) +#define QEIV2_IRQEN_CYCLE1E_SHIFT (22U) +#define QEIV2_IRQEN_CYCLE1E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_CYCLE1E_SHIFT) & QEIV2_IRQEN_CYCLE1E_MASK) +#define QEIV2_IRQEN_CYCLE1E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_CYCLE1E_MASK) >> QEIV2_IRQEN_CYCLE1E_SHIFT) + +/* + * PULSE0E (RW) + * + */ +#define QEIV2_IRQEN_PULSE0E_MASK (0x200000UL) +#define QEIV2_IRQEN_PULSE0E_SHIFT (21U) +#define QEIV2_IRQEN_PULSE0E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_PULSE0E_SHIFT) & QEIV2_IRQEN_PULSE0E_MASK) +#define QEIV2_IRQEN_PULSE0E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_PULSE0E_MASK) >> QEIV2_IRQEN_PULSE0E_SHIFT) + +/* + * PULSE1E (RW) + * + */ +#define QEIV2_IRQEN_PULSE1E_MASK (0x100000UL) +#define QEIV2_IRQEN_PULSE1E_SHIFT (20U) +#define QEIV2_IRQEN_PULSE1E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_PULSE1E_SHIFT) & QEIV2_IRQEN_PULSE1E_MASK) +#define QEIV2_IRQEN_PULSE1E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_PULSE1E_MASK) >> QEIV2_IRQEN_PULSE1E_SHIFT) + +/* + * HOME2E (RW) + * + */ +#define QEIV2_IRQEN_HOME2E_MASK (0x80000UL) +#define QEIV2_IRQEN_HOME2E_SHIFT (19U) +#define QEIV2_IRQEN_HOME2E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_HOME2E_SHIFT) & QEIV2_IRQEN_HOME2E_MASK) +#define QEIV2_IRQEN_HOME2E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_HOME2E_MASK) >> QEIV2_IRQEN_HOME2E_SHIFT) + +/* + * FAULTE (RW) + * + */ +#define QEIV2_IRQEN_FAULTE_MASK (0x40000UL) +#define QEIV2_IRQEN_FAULTE_SHIFT (18U) +#define QEIV2_IRQEN_FAULTE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_FAULTE_SHIFT) & QEIV2_IRQEN_FAULTE_MASK) +#define QEIV2_IRQEN_FAULTE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_FAULTE_MASK) >> QEIV2_IRQEN_FAULTE_SHIFT) + +/* Bitfield definition for register of struct array COUNT: Z */ +/* + * ZCNT (RW) + * + * zcnt value + */ +#define QEIV2_COUNT_Z_ZCNT_MASK (0xFFFFFFFFUL) +#define QEIV2_COUNT_Z_ZCNT_SHIFT (0U) +#define QEIV2_COUNT_Z_ZCNT_SET(x) (((uint32_t)(x) << QEIV2_COUNT_Z_ZCNT_SHIFT) & QEIV2_COUNT_Z_ZCNT_MASK) +#define QEIV2_COUNT_Z_ZCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_Z_ZCNT_MASK) >> QEIV2_COUNT_Z_ZCNT_SHIFT) + +/* Bitfield definition for register of struct array COUNT: PH */ +/* + * DIR (RO) + * + * 1- reverse rotation + * 0- forward rotation + */ +#define QEIV2_COUNT_PH_DIR_MASK (0x40000000UL) +#define QEIV2_COUNT_PH_DIR_SHIFT (30U) +#define QEIV2_COUNT_PH_DIR_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_DIR_MASK) >> QEIV2_COUNT_PH_DIR_SHIFT) + +/* + * ASTAT (RO) + * + * 1- a input is high + * 0- a input is low + */ +#define QEIV2_COUNT_PH_ASTAT_MASK (0x4000000UL) +#define QEIV2_COUNT_PH_ASTAT_SHIFT (26U) +#define QEIV2_COUNT_PH_ASTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_ASTAT_MASK) >> QEIV2_COUNT_PH_ASTAT_SHIFT) + +/* + * BSTAT (RO) + * + * 1- b input is high + * 0- b input is low + */ +#define QEIV2_COUNT_PH_BSTAT_MASK (0x2000000UL) +#define QEIV2_COUNT_PH_BSTAT_SHIFT (25U) +#define QEIV2_COUNT_PH_BSTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_BSTAT_MASK) >> QEIV2_COUNT_PH_BSTAT_SHIFT) + +/* + * PHCNT (RO) + * + * phcnt value + */ +#define QEIV2_COUNT_PH_PHCNT_MASK (0x1FFFFFUL) +#define QEIV2_COUNT_PH_PHCNT_SHIFT (0U) +#define QEIV2_COUNT_PH_PHCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_PHCNT_MASK) >> QEIV2_COUNT_PH_PHCNT_SHIFT) + +/* Bitfield definition for register of struct array COUNT: SPD */ +/* + * DIR (RO) + * + * 1- reverse rotation + * 0- forward rotation + */ +#define QEIV2_COUNT_SPD_DIR_MASK (0x80000000UL) +#define QEIV2_COUNT_SPD_DIR_SHIFT (31U) +#define QEIV2_COUNT_SPD_DIR_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_DIR_MASK) >> QEIV2_COUNT_SPD_DIR_SHIFT) + +/* + * ASTAT (RO) + * + * 1- a input is high + * 0- a input is low + */ +#define QEIV2_COUNT_SPD_ASTAT_MASK (0x40000000UL) +#define QEIV2_COUNT_SPD_ASTAT_SHIFT (30U) +#define QEIV2_COUNT_SPD_ASTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_ASTAT_MASK) >> QEIV2_COUNT_SPD_ASTAT_SHIFT) + +/* + * BSTAT (RW) + * + * 1- b input is high + * 0- b input is low + */ +#define QEIV2_COUNT_SPD_BSTAT_MASK (0x20000000UL) +#define QEIV2_COUNT_SPD_BSTAT_SHIFT (29U) +#define QEIV2_COUNT_SPD_BSTAT_SET(x) (((uint32_t)(x) << QEIV2_COUNT_SPD_BSTAT_SHIFT) & QEIV2_COUNT_SPD_BSTAT_MASK) +#define QEIV2_COUNT_SPD_BSTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_BSTAT_MASK) >> QEIV2_COUNT_SPD_BSTAT_SHIFT) + +/* + * SPDCNT (RO) + * + * spdcnt value + */ +#define QEIV2_COUNT_SPD_SPDCNT_MASK (0xFFFFFFFUL) +#define QEIV2_COUNT_SPD_SPDCNT_SHIFT (0U) +#define QEIV2_COUNT_SPD_SPDCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_SPDCNT_MASK) >> QEIV2_COUNT_SPD_SPDCNT_SHIFT) + +/* Bitfield definition for register of struct array COUNT: TMR */ +/* + * TMRCNT (RO) + * + * 32 bit free run timer + */ +#define QEIV2_COUNT_TMR_TMRCNT_MASK (0xFFFFFFFFUL) +#define QEIV2_COUNT_TMR_TMRCNT_SHIFT (0U) +#define QEIV2_COUNT_TMR_TMRCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_TMR_TMRCNT_MASK) >> QEIV2_COUNT_TMR_TMRCNT_SHIFT) + +/* Bitfield definition for register: ZCMP2 */ +/* + * ZCMP2 (RW) + * + */ +#define QEIV2_ZCMP2_ZCMP2_MASK (0xFFFFFFFFUL) +#define QEIV2_ZCMP2_ZCMP2_SHIFT (0U) +#define QEIV2_ZCMP2_ZCMP2_SET(x) (((uint32_t)(x) << QEIV2_ZCMP2_ZCMP2_SHIFT) & QEIV2_ZCMP2_ZCMP2_MASK) +#define QEIV2_ZCMP2_ZCMP2_GET(x) (((uint32_t)(x) & QEIV2_ZCMP2_ZCMP2_MASK) >> QEIV2_ZCMP2_ZCMP2_SHIFT) + +/* Bitfield definition for register: PHCMP2 */ +/* + * PHCMP2 (RW) + * + */ +#define QEIV2_PHCMP2_PHCMP2_MASK (0xFFFFFFFFUL) +#define QEIV2_PHCMP2_PHCMP2_SHIFT (0U) +#define QEIV2_PHCMP2_PHCMP2_SET(x) (((uint32_t)(x) << QEIV2_PHCMP2_PHCMP2_SHIFT) & QEIV2_PHCMP2_PHCMP2_MASK) +#define QEIV2_PHCMP2_PHCMP2_GET(x) (((uint32_t)(x) & QEIV2_PHCMP2_PHCMP2_MASK) >> QEIV2_PHCMP2_PHCMP2_SHIFT) + +/* Bitfield definition for register: SPDCMP2 */ +/* + * SPDCMP2 (RW) + * + */ +#define QEIV2_SPDCMP2_SPDCMP2_MASK (0xFFFFFFFFUL) +#define QEIV2_SPDCMP2_SPDCMP2_SHIFT (0U) +#define QEIV2_SPDCMP2_SPDCMP2_SET(x) (((uint32_t)(x) << QEIV2_SPDCMP2_SPDCMP2_SHIFT) & QEIV2_SPDCMP2_SPDCMP2_MASK) +#define QEIV2_SPDCMP2_SPDCMP2_GET(x) (((uint32_t)(x) & QEIV2_SPDCMP2_SPDCMP2_MASK) >> QEIV2_SPDCMP2_SPDCMP2_SHIFT) + +/* Bitfield definition for register: MATCH_CFG */ +/* + * ZCMPDIS (RW) + * + * 1- postion compare not include zcnt + */ +#define QEIV2_MATCH_CFG_ZCMPDIS_MASK (0x80000000UL) +#define QEIV2_MATCH_CFG_ZCMPDIS_SHIFT (31U) +#define QEIV2_MATCH_CFG_ZCMPDIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_ZCMPDIS_SHIFT) & QEIV2_MATCH_CFG_ZCMPDIS_MASK) +#define QEIV2_MATCH_CFG_ZCMPDIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_ZCMPDIS_MASK) >> QEIV2_MATCH_CFG_ZCMPDIS_SHIFT) + +/* + * DIRCMPDIS (RW) + * + * 1- postion compare not include rotation direction + */ +#define QEIV2_MATCH_CFG_DIRCMPDIS_MASK (0x40000000UL) +#define QEIV2_MATCH_CFG_DIRCMPDIS_SHIFT (30U) +#define QEIV2_MATCH_CFG_DIRCMPDIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMPDIS_SHIFT) & QEIV2_MATCH_CFG_DIRCMPDIS_MASK) +#define QEIV2_MATCH_CFG_DIRCMPDIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMPDIS_MASK) >> QEIV2_MATCH_CFG_DIRCMPDIS_SHIFT) + +/* + * DIRCMP (RW) + * + * 0- position compare need positive rotation + * 1- position compare need negative rotation + */ +#define QEIV2_MATCH_CFG_DIRCMP_MASK (0x20000000UL) +#define QEIV2_MATCH_CFG_DIRCMP_SHIFT (29U) +#define QEIV2_MATCH_CFG_DIRCMP_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMP_SHIFT) & QEIV2_MATCH_CFG_DIRCMP_MASK) +#define QEIV2_MATCH_CFG_DIRCMP_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMP_MASK) >> QEIV2_MATCH_CFG_DIRCMP_SHIFT) + +/* + * SPDCMPDIS (RW) + * + */ +#define QEIV2_MATCH_CFG_SPDCMPDIS_MASK (0x10000000UL) +#define QEIV2_MATCH_CFG_SPDCMPDIS_SHIFT (28U) +#define QEIV2_MATCH_CFG_SPDCMPDIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_SPDCMPDIS_SHIFT) & QEIV2_MATCH_CFG_SPDCMPDIS_MASK) +#define QEIV2_MATCH_CFG_SPDCMPDIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_SPDCMPDIS_MASK) >> QEIV2_MATCH_CFG_SPDCMPDIS_SHIFT) + +/* + * PHASE_MATCH_DIS (RW) + * + */ +#define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK (0x8000000UL) +#define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SHIFT (27U) +#define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SHIFT) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK) +#define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK) >> QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SHIFT) + +/* + * POS_MATCH_DIR (RW) + * + */ +#define QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK (0x4000000UL) +#define QEIV2_MATCH_CFG_POS_MATCH_DIR_SHIFT (26U) +#define QEIV2_MATCH_CFG_POS_MATCH_DIR_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH_DIR_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK) +#define QEIV2_MATCH_CFG_POS_MATCH_DIR_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK) >> QEIV2_MATCH_CFG_POS_MATCH_DIR_SHIFT) + +/* + * POS_MATCH_OPT (RW) + * + */ +#define QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK (0x2000000UL) +#define QEIV2_MATCH_CFG_POS_MATCH_OPT_SHIFT (25U) +#define QEIV2_MATCH_CFG_POS_MATCH_OPT_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH_OPT_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK) +#define QEIV2_MATCH_CFG_POS_MATCH_OPT_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK) >> QEIV2_MATCH_CFG_POS_MATCH_OPT_SHIFT) + +/* + * ZCMP2DIS (RW) + * + */ +#define QEIV2_MATCH_CFG_ZCMP2DIS_MASK (0x8000U) +#define QEIV2_MATCH_CFG_ZCMP2DIS_SHIFT (15U) +#define QEIV2_MATCH_CFG_ZCMP2DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_ZCMP2DIS_SHIFT) & QEIV2_MATCH_CFG_ZCMP2DIS_MASK) +#define QEIV2_MATCH_CFG_ZCMP2DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_ZCMP2DIS_MASK) >> QEIV2_MATCH_CFG_ZCMP2DIS_SHIFT) + +/* + * DIRCMP2DIS (RW) + * + */ +#define QEIV2_MATCH_CFG_DIRCMP2DIS_MASK (0x4000U) +#define QEIV2_MATCH_CFG_DIRCMP2DIS_SHIFT (14U) +#define QEIV2_MATCH_CFG_DIRCMP2DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMP2DIS_SHIFT) & QEIV2_MATCH_CFG_DIRCMP2DIS_MASK) +#define QEIV2_MATCH_CFG_DIRCMP2DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMP2DIS_MASK) >> QEIV2_MATCH_CFG_DIRCMP2DIS_SHIFT) + +/* + * DIRCMP2 (RW) + * + */ +#define QEIV2_MATCH_CFG_DIRCMP2_MASK (0x2000U) +#define QEIV2_MATCH_CFG_DIRCMP2_SHIFT (13U) +#define QEIV2_MATCH_CFG_DIRCMP2_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMP2_SHIFT) & QEIV2_MATCH_CFG_DIRCMP2_MASK) +#define QEIV2_MATCH_CFG_DIRCMP2_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMP2_MASK) >> QEIV2_MATCH_CFG_DIRCMP2_SHIFT) + +/* + * SPDCMP2DIS (RW) + * + */ +#define QEIV2_MATCH_CFG_SPDCMP2DIS_MASK (0x1000U) +#define QEIV2_MATCH_CFG_SPDCMP2DIS_SHIFT (12U) +#define QEIV2_MATCH_CFG_SPDCMP2DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_SPDCMP2DIS_SHIFT) & QEIV2_MATCH_CFG_SPDCMP2DIS_MASK) +#define QEIV2_MATCH_CFG_SPDCMP2DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_SPDCMP2DIS_MASK) >> QEIV2_MATCH_CFG_SPDCMP2DIS_SHIFT) + +/* + * PHASE_MATCH_DIS2 (RW) + * + */ +#define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK (0x800U) +#define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SHIFT (11U) +#define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SHIFT) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK) +#define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK) >> QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SHIFT) + +/* + * POS_MATCH2_DIR (RW) + * + */ +#define QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK (0x400U) +#define QEIV2_MATCH_CFG_POS_MATCH2_DIR_SHIFT (10U) +#define QEIV2_MATCH_CFG_POS_MATCH2_DIR_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH2_DIR_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK) +#define QEIV2_MATCH_CFG_POS_MATCH2_DIR_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK) >> QEIV2_MATCH_CFG_POS_MATCH2_DIR_SHIFT) + +/* + * POS_MATCH2_OPT (RW) + * + */ +#define QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK (0x200U) +#define QEIV2_MATCH_CFG_POS_MATCH2_OPT_SHIFT (9U) +#define QEIV2_MATCH_CFG_POS_MATCH2_OPT_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH2_OPT_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK) +#define QEIV2_MATCH_CFG_POS_MATCH2_OPT_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK) >> QEIV2_MATCH_CFG_POS_MATCH2_OPT_SHIFT) + +/* Bitfield definition for register array: FILT_CFG */ +/* + * OUTINV (RW) + * + * 1- Filter will invert the output + * 0- Filter will not invert the output + */ +#define QEIV2_FILT_CFG_OUTINV_MASK (0x10000UL) +#define QEIV2_FILT_CFG_OUTINV_SHIFT (16U) +#define QEIV2_FILT_CFG_OUTINV_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_OUTINV_SHIFT) & QEIV2_FILT_CFG_OUTINV_MASK) +#define QEIV2_FILT_CFG_OUTINV_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_OUTINV_MASK) >> QEIV2_FILT_CFG_OUTINV_SHIFT) + +/* + * MODE (RW) + * + * This bitfields defines the filter mode + * 000-bypass; + * 100-rapid change mode; + * 101-delay filter mode; + * 110-stable low mode; + * 111-stable high mode + */ +#define QEIV2_FILT_CFG_MODE_MASK (0xE000U) +#define QEIV2_FILT_CFG_MODE_SHIFT (13U) +#define QEIV2_FILT_CFG_MODE_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_MODE_SHIFT) & QEIV2_FILT_CFG_MODE_MASK) +#define QEIV2_FILT_CFG_MODE_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_MODE_MASK) >> QEIV2_FILT_CFG_MODE_SHIFT) + +/* + * SYNCEN (RW) + * + * set to enable sychronization input signal with TRGM clock + */ +#define QEIV2_FILT_CFG_SYNCEN_MASK (0x1000U) +#define QEIV2_FILT_CFG_SYNCEN_SHIFT (12U) +#define QEIV2_FILT_CFG_SYNCEN_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_SYNCEN_SHIFT) & QEIV2_FILT_CFG_SYNCEN_MASK) +#define QEIV2_FILT_CFG_SYNCEN_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_SYNCEN_MASK) >> QEIV2_FILT_CFG_SYNCEN_SHIFT) + +/* + * FILTLEN (RW) + * + * This bitfields defines the filter counter length. + */ +#define QEIV2_FILT_CFG_FILTLEN_MASK (0xFFFU) +#define QEIV2_FILT_CFG_FILTLEN_SHIFT (0U) +#define QEIV2_FILT_CFG_FILTLEN_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_FILTLEN_SHIFT) & QEIV2_FILT_CFG_FILTLEN_MASK) +#define QEIV2_FILT_CFG_FILTLEN_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_FILTLEN_MASK) >> QEIV2_FILT_CFG_FILTLEN_SHIFT) + +/* Bitfield definition for register: QEI_CFG */ +/* + * SPEED_DIR_CHG_EN (RW) + * + * clear counter if detect direction change + */ +#define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK (0x1000U) +#define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SHIFT (12U) +#define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SHIFT) & QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK) +#define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK) >> QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SHIFT) + +/* + * UVW_POS_OPT0 (RW) + * + * set to output next area position for QEO use; + * clr to output exact point position for MMC use + */ +#define QEIV2_QEI_CFG_UVW_POS_OPT0_MASK (0x20U) +#define QEIV2_QEI_CFG_UVW_POS_OPT0_SHIFT (5U) +#define QEIV2_QEI_CFG_UVW_POS_OPT0_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_UVW_POS_OPT0_SHIFT) & QEIV2_QEI_CFG_UVW_POS_OPT0_MASK) +#define QEIV2_QEI_CFG_UVW_POS_OPT0_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_UVW_POS_OPT0_MASK) >> QEIV2_QEI_CFG_UVW_POS_OPT0_SHIFT) + +/* + * NEGEDGE_EN (RW) + * + * bit4: negedge enable + * bit3: posedge enable + * bit2: W in hal enable + * bit1: signal b(or V in hal) enable + * bit0: signal a(or U in hal) enable + * such as: + * 01001: use posedge A + * 11010: use both edge of signal B + * 11111: use both edge of all HAL siganls + */ +#define QEIV2_QEI_CFG_NEGEDGE_EN_MASK (0x10U) +#define QEIV2_QEI_CFG_NEGEDGE_EN_SHIFT (4U) +#define QEIV2_QEI_CFG_NEGEDGE_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_NEGEDGE_EN_SHIFT) & QEIV2_QEI_CFG_NEGEDGE_EN_MASK) +#define QEIV2_QEI_CFG_NEGEDGE_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_NEGEDGE_EN_MASK) >> QEIV2_QEI_CFG_NEGEDGE_EN_SHIFT) + +/* + * POSIDGE_EN (RW) + * + */ +#define QEIV2_QEI_CFG_POSIDGE_EN_MASK (0x8U) +#define QEIV2_QEI_CFG_POSIDGE_EN_SHIFT (3U) +#define QEIV2_QEI_CFG_POSIDGE_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_POSIDGE_EN_SHIFT) & QEIV2_QEI_CFG_POSIDGE_EN_MASK) +#define QEIV2_QEI_CFG_POSIDGE_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_POSIDGE_EN_MASK) >> QEIV2_QEI_CFG_POSIDGE_EN_SHIFT) + +/* + * SIGZ_EN (RW) + * + */ +#define QEIV2_QEI_CFG_SIGZ_EN_MASK (0x4U) +#define QEIV2_QEI_CFG_SIGZ_EN_SHIFT (2U) +#define QEIV2_QEI_CFG_SIGZ_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SIGZ_EN_SHIFT) & QEIV2_QEI_CFG_SIGZ_EN_MASK) +#define QEIV2_QEI_CFG_SIGZ_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SIGZ_EN_MASK) >> QEIV2_QEI_CFG_SIGZ_EN_SHIFT) + +/* + * SIGB_EN (RW) + * + */ +#define QEIV2_QEI_CFG_SIGB_EN_MASK (0x2U) +#define QEIV2_QEI_CFG_SIGB_EN_SHIFT (1U) +#define QEIV2_QEI_CFG_SIGB_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SIGB_EN_SHIFT) & QEIV2_QEI_CFG_SIGB_EN_MASK) +#define QEIV2_QEI_CFG_SIGB_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SIGB_EN_MASK) >> QEIV2_QEI_CFG_SIGB_EN_SHIFT) + +/* + * SIGA_EN (RW) + * + */ +#define QEIV2_QEI_CFG_SIGA_EN_MASK (0x1U) +#define QEIV2_QEI_CFG_SIGA_EN_SHIFT (0U) +#define QEIV2_QEI_CFG_SIGA_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SIGA_EN_SHIFT) & QEIV2_QEI_CFG_SIGA_EN_MASK) +#define QEIV2_QEI_CFG_SIGA_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SIGA_EN_MASK) >> QEIV2_QEI_CFG_SIGA_EN_SHIFT) + +/* Bitfield definition for register: PULSE0_NUM */ +/* + * PULSE0_NUM (RW) + * + * for speed detection, will count the cycle number for configed pulse_num + */ +#define QEIV2_PULSE0_NUM_PULSE0_NUM_MASK (0xFFFFFFFFUL) +#define QEIV2_PULSE0_NUM_PULSE0_NUM_SHIFT (0U) +#define QEIV2_PULSE0_NUM_PULSE0_NUM_SET(x) (((uint32_t)(x) << QEIV2_PULSE0_NUM_PULSE0_NUM_SHIFT) & QEIV2_PULSE0_NUM_PULSE0_NUM_MASK) +#define QEIV2_PULSE0_NUM_PULSE0_NUM_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_NUM_PULSE0_NUM_MASK) >> QEIV2_PULSE0_NUM_PULSE0_NUM_SHIFT) + +/* Bitfield definition for register: PULSE1_NUM */ +/* + * PULSE1_NUM (RW) + * + */ +#define QEIV2_PULSE1_NUM_PULSE1_NUM_MASK (0xFFFFFFFFUL) +#define QEIV2_PULSE1_NUM_PULSE1_NUM_SHIFT (0U) +#define QEIV2_PULSE1_NUM_PULSE1_NUM_SET(x) (((uint32_t)(x) << QEIV2_PULSE1_NUM_PULSE1_NUM_SHIFT) & QEIV2_PULSE1_NUM_PULSE1_NUM_MASK) +#define QEIV2_PULSE1_NUM_PULSE1_NUM_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_NUM_PULSE1_NUM_MASK) >> QEIV2_PULSE1_NUM_PULSE1_NUM_SHIFT) + +/* Bitfield definition for register: CYCLE0_CNT */ +/* + * CYCLE0_CNT (RO) + * + */ +#define QEIV2_CYCLE0_CNT_CYCLE0_CNT_MASK (0xFFFFFFFFUL) +#define QEIV2_CYCLE0_CNT_CYCLE0_CNT_SHIFT (0U) +#define QEIV2_CYCLE0_CNT_CYCLE0_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_CNT_CYCLE0_CNT_MASK) >> QEIV2_CYCLE0_CNT_CYCLE0_CNT_SHIFT) + +/* Bitfield definition for register: CYCLE0PULSE_CNT */ +/* + * CYCLE0PULSE_CNT (RO) + * + */ +#define QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_MASK (0xFFFFFFFFUL) +#define QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_SHIFT (0U) +#define QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_MASK) >> QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_SHIFT) + +/* Bitfield definition for register: CYCLE1_CNT */ +/* + * CYCLE1_CNT (RO) + * + */ +#define QEIV2_CYCLE1_CNT_CYCLE1_CNT_MASK (0xFFFFFFFFUL) +#define QEIV2_CYCLE1_CNT_CYCLE1_CNT_SHIFT (0U) +#define QEIV2_CYCLE1_CNT_CYCLE1_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_CNT_CYCLE1_CNT_MASK) >> QEIV2_CYCLE1_CNT_CYCLE1_CNT_SHIFT) + +/* Bitfield definition for register: CYCLE1PULSE_CNT */ +/* + * CYCLE1PULSE_CNT (RO) + * + */ +#define QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_MASK (0xFFFFFFFFUL) +#define QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_SHIFT (0U) +#define QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_MASK) >> QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_SHIFT) + +/* Bitfield definition for register: CYCLE0_SNAP0 */ +/* + * CYCLE0_SNAP0 (RO) + * + */ +#define QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_MASK (0xFFFFFFFFUL) +#define QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_SHIFT (0U) +#define QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_MASK) >> QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_SHIFT) + +/* Bitfield definition for register: CYCLE0_SNAP1 */ +/* + * CYCLE0_SNAP1 (RO) + * + */ +#define QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_MASK (0xFFFFFFFFUL) +#define QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_SHIFT (0U) +#define QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_MASK) >> QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_SHIFT) + +/* Bitfield definition for register: CYCLE1_SNAP0 */ +/* + * CYCLE1_SNAP0 (RO) + * + */ +#define QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_MASK (0xFFFFFFFFUL) +#define QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_SHIFT (0U) +#define QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_MASK) >> QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_SHIFT) + +/* Bitfield definition for register: CYCLE1_SNAP1 */ +/* + * CYCLE1_SNAP1 (RO) + * + */ +#define QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_MASK (0xFFFFFFFFUL) +#define QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_SHIFT (0U) +#define QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_MASK) >> QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_SHIFT) + +/* Bitfield definition for register: CYCLE0_NUM */ +/* + * CYCLE0_NUM (RW) + * + */ +#define QEIV2_CYCLE0_NUM_CYCLE0_NUM_MASK (0xFFFFFFFFUL) +#define QEIV2_CYCLE0_NUM_CYCLE0_NUM_SHIFT (0U) +#define QEIV2_CYCLE0_NUM_CYCLE0_NUM_SET(x) (((uint32_t)(x) << QEIV2_CYCLE0_NUM_CYCLE0_NUM_SHIFT) & QEIV2_CYCLE0_NUM_CYCLE0_NUM_MASK) +#define QEIV2_CYCLE0_NUM_CYCLE0_NUM_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_NUM_CYCLE0_NUM_MASK) >> QEIV2_CYCLE0_NUM_CYCLE0_NUM_SHIFT) + +/* Bitfield definition for register: CYCLE1_NUM */ +/* + * CYCLE1_NUM (RW) + * + */ +#define QEIV2_CYCLE1_NUM_CYCLE1_NUM_MASK (0xFFFFFFFFUL) +#define QEIV2_CYCLE1_NUM_CYCLE1_NUM_SHIFT (0U) +#define QEIV2_CYCLE1_NUM_CYCLE1_NUM_SET(x) (((uint32_t)(x) << QEIV2_CYCLE1_NUM_CYCLE1_NUM_SHIFT) & QEIV2_CYCLE1_NUM_CYCLE1_NUM_MASK) +#define QEIV2_CYCLE1_NUM_CYCLE1_NUM_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_NUM_CYCLE1_NUM_MASK) >> QEIV2_CYCLE1_NUM_CYCLE1_NUM_SHIFT) + +/* Bitfield definition for register: PULSE0_CNT */ +/* + * PULSE0_CNT (RO) + * + */ +#define QEIV2_PULSE0_CNT_PULSE0_CNT_MASK (0xFFFFFFFFUL) +#define QEIV2_PULSE0_CNT_PULSE0_CNT_SHIFT (0U) +#define QEIV2_PULSE0_CNT_PULSE0_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_CNT_PULSE0_CNT_MASK) >> QEIV2_PULSE0_CNT_PULSE0_CNT_SHIFT) + +/* Bitfield definition for register: PULSE0CYCLE_CNT */ +/* + * PULSE0CYCLE_CNT (RO) + * + */ +#define QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_MASK (0xFFFFFFFFUL) +#define QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_SHIFT (0U) +#define QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_MASK) >> QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_SHIFT) + +/* Bitfield definition for register: PULSE1_CNT */ +/* + * PULSE1_CNT (RO) + * + */ +#define QEIV2_PULSE1_CNT_PULSE1_CNT_MASK (0xFFFFFFFFUL) +#define QEIV2_PULSE1_CNT_PULSE1_CNT_SHIFT (0U) +#define QEIV2_PULSE1_CNT_PULSE1_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_CNT_PULSE1_CNT_MASK) >> QEIV2_PULSE1_CNT_PULSE1_CNT_SHIFT) + +/* Bitfield definition for register: PULSE1CYCLE_CNT */ +/* + * PULSE1CYCLE_CNT (RO) + * + */ +#define QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_MASK (0xFFFFFFFFUL) +#define QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_SHIFT (0U) +#define QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_MASK) >> QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_SHIFT) + +/* Bitfield definition for register: PULSE0_SNAP0 */ +/* + * PULSE0_SNAP0 (RO) + * + */ +#define QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_MASK (0xFFFFFFFFUL) +#define QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_SHIFT (0U) +#define QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_MASK) >> QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_SHIFT) + +/* Bitfield definition for register: PULSE0CYCLE_SNAP0 */ +/* + * PULSE0CYCLE_SNAP0 (RO) + * + */ +#define QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_MASK (0xFFFFFFFFUL) +#define QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_SHIFT (0U) +#define QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_MASK) >> QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_SHIFT) + +/* Bitfield definition for register: PULSE0_SNAP1 */ +/* + * PULSE0_SNAP1 (RO) + * + */ +#define QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_MASK (0xFFFFFFFFUL) +#define QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_SHIFT (0U) +#define QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_MASK) >> QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_SHIFT) + +/* Bitfield definition for register: PULSE0CYCLE_SNAP1 */ +/* + * PULSE0CYCLE_SNAP1 (RO) + * + */ +#define QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_MASK (0xFFFFFFFFUL) +#define QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_SHIFT (0U) +#define QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_MASK) >> QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_SHIFT) + +/* Bitfield definition for register: PULSE1_SNAP0 */ +/* + * PULSE1_SNAP0 (RO) + * + */ +#define QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_MASK (0xFFFFFFFFUL) +#define QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_SHIFT (0U) +#define QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_MASK) >> QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_SHIFT) + +/* Bitfield definition for register: PULSE1CYCLE_SNAP0 */ +/* + * PULSE1CYCLE_SNAP0 (RO) + * + */ +#define QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_MASK (0xFFFFFFFFUL) +#define QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_SHIFT (0U) +#define QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_MASK) >> QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_SHIFT) + +/* Bitfield definition for register: PULSE1_SNAP1 */ +/* + * PULSE1_SNAP1 (RO) + * + */ +#define QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_MASK (0xFFFFFFFFUL) +#define QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_SHIFT (0U) +#define QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_MASK) >> QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_SHIFT) + +/* Bitfield definition for register: PULSE1CYCLE_SNAP1 */ +/* + * PULSE1CYCLE_SNAP1 (RO) + * + */ +#define QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_MASK (0xFFFFFFFFUL) +#define QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_SHIFT (0U) +#define QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_MASK) >> QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_SHIFT) + +/* Bitfield definition for register: ADCX_CFG0 */ +/* + * X_ADCSEL (RW) + * + */ +#define QEIV2_ADCX_CFG0_X_ADCSEL_MASK (0x100U) +#define QEIV2_ADCX_CFG0_X_ADCSEL_SHIFT (8U) +#define QEIV2_ADCX_CFG0_X_ADCSEL_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG0_X_ADCSEL_SHIFT) & QEIV2_ADCX_CFG0_X_ADCSEL_MASK) +#define QEIV2_ADCX_CFG0_X_ADCSEL_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG0_X_ADCSEL_MASK) >> QEIV2_ADCX_CFG0_X_ADCSEL_SHIFT) + +/* + * X_ADC_ENABLE (RW) + * + */ +#define QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK (0x80U) +#define QEIV2_ADCX_CFG0_X_ADC_ENABLE_SHIFT (7U) +#define QEIV2_ADCX_CFG0_X_ADC_ENABLE_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG0_X_ADC_ENABLE_SHIFT) & QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK) +#define QEIV2_ADCX_CFG0_X_ADC_ENABLE_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK) >> QEIV2_ADCX_CFG0_X_ADC_ENABLE_SHIFT) + +/* + * X_CHAN (RW) + * + */ +#define QEIV2_ADCX_CFG0_X_CHAN_MASK (0x1FU) +#define QEIV2_ADCX_CFG0_X_CHAN_SHIFT (0U) +#define QEIV2_ADCX_CFG0_X_CHAN_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG0_X_CHAN_SHIFT) & QEIV2_ADCX_CFG0_X_CHAN_MASK) +#define QEIV2_ADCX_CFG0_X_CHAN_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG0_X_CHAN_MASK) >> QEIV2_ADCX_CFG0_X_CHAN_SHIFT) + +/* Bitfield definition for register: ADCX_CFG1 */ +/* + * X_PARAM1 (RW) + * + */ +#define QEIV2_ADCX_CFG1_X_PARAM1_MASK (0xFFFF0000UL) +#define QEIV2_ADCX_CFG1_X_PARAM1_SHIFT (16U) +#define QEIV2_ADCX_CFG1_X_PARAM1_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG1_X_PARAM1_SHIFT) & QEIV2_ADCX_CFG1_X_PARAM1_MASK) +#define QEIV2_ADCX_CFG1_X_PARAM1_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG1_X_PARAM1_MASK) >> QEIV2_ADCX_CFG1_X_PARAM1_SHIFT) + +/* + * X_PARAM0 (RW) + * + */ +#define QEIV2_ADCX_CFG1_X_PARAM0_MASK (0xFFFFU) +#define QEIV2_ADCX_CFG1_X_PARAM0_SHIFT (0U) +#define QEIV2_ADCX_CFG1_X_PARAM0_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG1_X_PARAM0_SHIFT) & QEIV2_ADCX_CFG1_X_PARAM0_MASK) +#define QEIV2_ADCX_CFG1_X_PARAM0_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG1_X_PARAM0_MASK) >> QEIV2_ADCX_CFG1_X_PARAM0_SHIFT) + +/* Bitfield definition for register: ADCX_CFG2 */ +/* + * X_OFFSET (RW) + * + */ +#define QEIV2_ADCX_CFG2_X_OFFSET_MASK (0xFFFFFFFFUL) +#define QEIV2_ADCX_CFG2_X_OFFSET_SHIFT (0U) +#define QEIV2_ADCX_CFG2_X_OFFSET_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG2_X_OFFSET_SHIFT) & QEIV2_ADCX_CFG2_X_OFFSET_MASK) +#define QEIV2_ADCX_CFG2_X_OFFSET_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG2_X_OFFSET_MASK) >> QEIV2_ADCX_CFG2_X_OFFSET_SHIFT) + +/* Bitfield definition for register: ADCY_CFG0 */ +/* + * Y_ADCSEL (RW) + * + */ +#define QEIV2_ADCY_CFG0_Y_ADCSEL_MASK (0x100U) +#define QEIV2_ADCY_CFG0_Y_ADCSEL_SHIFT (8U) +#define QEIV2_ADCY_CFG0_Y_ADCSEL_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG0_Y_ADCSEL_SHIFT) & QEIV2_ADCY_CFG0_Y_ADCSEL_MASK) +#define QEIV2_ADCY_CFG0_Y_ADCSEL_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG0_Y_ADCSEL_MASK) >> QEIV2_ADCY_CFG0_Y_ADCSEL_SHIFT) + +/* + * Y_ADC_ENABLE (RW) + * + */ +#define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK (0x80U) +#define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SHIFT (7U) +#define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SHIFT) & QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK) +#define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK) >> QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SHIFT) + +/* + * Y_CHAN (RW) + * + */ +#define QEIV2_ADCY_CFG0_Y_CHAN_MASK (0x1FU) +#define QEIV2_ADCY_CFG0_Y_CHAN_SHIFT (0U) +#define QEIV2_ADCY_CFG0_Y_CHAN_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG0_Y_CHAN_SHIFT) & QEIV2_ADCY_CFG0_Y_CHAN_MASK) +#define QEIV2_ADCY_CFG0_Y_CHAN_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG0_Y_CHAN_MASK) >> QEIV2_ADCY_CFG0_Y_CHAN_SHIFT) + +/* Bitfield definition for register: ADCY_CFG1 */ +/* + * Y_PARAM1 (RW) + * + */ +#define QEIV2_ADCY_CFG1_Y_PARAM1_MASK (0xFFFF0000UL) +#define QEIV2_ADCY_CFG1_Y_PARAM1_SHIFT (16U) +#define QEIV2_ADCY_CFG1_Y_PARAM1_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG1_Y_PARAM1_SHIFT) & QEIV2_ADCY_CFG1_Y_PARAM1_MASK) +#define QEIV2_ADCY_CFG1_Y_PARAM1_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG1_Y_PARAM1_MASK) >> QEIV2_ADCY_CFG1_Y_PARAM1_SHIFT) + +/* + * Y_PARAM0 (RW) + * + */ +#define QEIV2_ADCY_CFG1_Y_PARAM0_MASK (0xFFFFU) +#define QEIV2_ADCY_CFG1_Y_PARAM0_SHIFT (0U) +#define QEIV2_ADCY_CFG1_Y_PARAM0_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG1_Y_PARAM0_SHIFT) & QEIV2_ADCY_CFG1_Y_PARAM0_MASK) +#define QEIV2_ADCY_CFG1_Y_PARAM0_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG1_Y_PARAM0_MASK) >> QEIV2_ADCY_CFG1_Y_PARAM0_SHIFT) + +/* Bitfield definition for register: ADCY_CFG2 */ +/* + * Y_OFFSET (RW) + * + */ +#define QEIV2_ADCY_CFG2_Y_OFFSET_MASK (0xFFFFFFFFUL) +#define QEIV2_ADCY_CFG2_Y_OFFSET_SHIFT (0U) +#define QEIV2_ADCY_CFG2_Y_OFFSET_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG2_Y_OFFSET_SHIFT) & QEIV2_ADCY_CFG2_Y_OFFSET_MASK) +#define QEIV2_ADCY_CFG2_Y_OFFSET_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG2_Y_OFFSET_MASK) >> QEIV2_ADCY_CFG2_Y_OFFSET_SHIFT) + +/* Bitfield definition for register: CAL_CFG */ +/* + * XY_DELAY (RW) + * + * valid x/y delay, larger than this delay will be treated as invalid data. + * Default 1.25us@200MHz; max 80ms; + */ +#define QEIV2_CAL_CFG_XY_DELAY_MASK (0xFFFFFFUL) +#define QEIV2_CAL_CFG_XY_DELAY_SHIFT (0U) +#define QEIV2_CAL_CFG_XY_DELAY_SET(x) (((uint32_t)(x) << QEIV2_CAL_CFG_XY_DELAY_SHIFT) & QEIV2_CAL_CFG_XY_DELAY_MASK) +#define QEIV2_CAL_CFG_XY_DELAY_GET(x) (((uint32_t)(x) & QEIV2_CAL_CFG_XY_DELAY_MASK) >> QEIV2_CAL_CFG_XY_DELAY_SHIFT) + +/* Bitfield definition for register: PHASE_PARAM */ +/* + * PHASE_PARAM (RW) + * + */ +#define QEIV2_PHASE_PARAM_PHASE_PARAM_MASK (0xFFFFFFFFUL) +#define QEIV2_PHASE_PARAM_PHASE_PARAM_SHIFT (0U) +#define QEIV2_PHASE_PARAM_PHASE_PARAM_SET(x) (((uint32_t)(x) << QEIV2_PHASE_PARAM_PHASE_PARAM_SHIFT) & QEIV2_PHASE_PARAM_PHASE_PARAM_MASK) +#define QEIV2_PHASE_PARAM_PHASE_PARAM_GET(x) (((uint32_t)(x) & QEIV2_PHASE_PARAM_PHASE_PARAM_MASK) >> QEIV2_PHASE_PARAM_PHASE_PARAM_SHIFT) + +/* Bitfield definition for register: ANGLE_ADJ */ +/* + * ANGLE_ADJ (RW) + * + */ +#define QEIV2_ANGLE_ADJ_ANGLE_ADJ_MASK (0xFFFFFFFFUL) +#define QEIV2_ANGLE_ADJ_ANGLE_ADJ_SHIFT (0U) +#define QEIV2_ANGLE_ADJ_ANGLE_ADJ_SET(x) (((uint32_t)(x) << QEIV2_ANGLE_ADJ_ANGLE_ADJ_SHIFT) & QEIV2_ANGLE_ADJ_ANGLE_ADJ_MASK) +#define QEIV2_ANGLE_ADJ_ANGLE_ADJ_GET(x) (((uint32_t)(x) & QEIV2_ANGLE_ADJ_ANGLE_ADJ_MASK) >> QEIV2_ANGLE_ADJ_ANGLE_ADJ_SHIFT) + +/* Bitfield definition for register: POS_THRESHOLD */ +/* + * POS_THRESHOLD (RW) + * + */ +#define QEIV2_POS_THRESHOLD_POS_THRESHOLD_MASK (0xFFFFFFFFUL) +#define QEIV2_POS_THRESHOLD_POS_THRESHOLD_SHIFT (0U) +#define QEIV2_POS_THRESHOLD_POS_THRESHOLD_SET(x) (((uint32_t)(x) << QEIV2_POS_THRESHOLD_POS_THRESHOLD_SHIFT) & QEIV2_POS_THRESHOLD_POS_THRESHOLD_MASK) +#define QEIV2_POS_THRESHOLD_POS_THRESHOLD_GET(x) (((uint32_t)(x) & QEIV2_POS_THRESHOLD_POS_THRESHOLD_MASK) >> QEIV2_POS_THRESHOLD_POS_THRESHOLD_SHIFT) + +/* Bitfield definition for register array: UVW_POS */ +/* + * UVW_POS0 (RW) + * + */ +#define QEIV2_UVW_POS_UVW_POS0_MASK (0xFFFFFFFFUL) +#define QEIV2_UVW_POS_UVW_POS0_SHIFT (0U) +#define QEIV2_UVW_POS_UVW_POS0_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_UVW_POS0_SHIFT) & QEIV2_UVW_POS_UVW_POS0_MASK) +#define QEIV2_UVW_POS_UVW_POS0_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_UVW_POS0_MASK) >> QEIV2_UVW_POS_UVW_POS0_SHIFT) + +/* Bitfield definition for register array: UVW_POS_CFG */ +/* + * POS_EN (RW) + * + */ +#define QEIV2_UVW_POS_CFG_POS_EN_MASK (0x40U) +#define QEIV2_UVW_POS_CFG_POS_EN_SHIFT (6U) +#define QEIV2_UVW_POS_CFG_POS_EN_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_POS_EN_SHIFT) & QEIV2_UVW_POS_CFG_POS_EN_MASK) +#define QEIV2_UVW_POS_CFG_POS_EN_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_POS_EN_MASK) >> QEIV2_UVW_POS_CFG_POS_EN_SHIFT) + +/* + * U_POS_SEL (RW) + * + */ +#define QEIV2_UVW_POS_CFG_U_POS_SEL_MASK (0x30U) +#define QEIV2_UVW_POS_CFG_U_POS_SEL_SHIFT (4U) +#define QEIV2_UVW_POS_CFG_U_POS_SEL_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_U_POS_SEL_SHIFT) & QEIV2_UVW_POS_CFG_U_POS_SEL_MASK) +#define QEIV2_UVW_POS_CFG_U_POS_SEL_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_U_POS_SEL_MASK) >> QEIV2_UVW_POS_CFG_U_POS_SEL_SHIFT) + +/* + * V_POS_SEL (RW) + * + */ +#define QEIV2_UVW_POS_CFG_V_POS_SEL_MASK (0xCU) +#define QEIV2_UVW_POS_CFG_V_POS_SEL_SHIFT (2U) +#define QEIV2_UVW_POS_CFG_V_POS_SEL_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_V_POS_SEL_SHIFT) & QEIV2_UVW_POS_CFG_V_POS_SEL_MASK) +#define QEIV2_UVW_POS_CFG_V_POS_SEL_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_V_POS_SEL_MASK) >> QEIV2_UVW_POS_CFG_V_POS_SEL_SHIFT) + +/* + * W_POS_SEL (RW) + * + */ +#define QEIV2_UVW_POS_CFG_W_POS_SEL_MASK (0x3U) +#define QEIV2_UVW_POS_CFG_W_POS_SEL_SHIFT (0U) +#define QEIV2_UVW_POS_CFG_W_POS_SEL_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_W_POS_SEL_SHIFT) & QEIV2_UVW_POS_CFG_W_POS_SEL_MASK) +#define QEIV2_UVW_POS_CFG_W_POS_SEL_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_W_POS_SEL_MASK) >> QEIV2_UVW_POS_CFG_W_POS_SEL_SHIFT) + +/* Bitfield definition for register: PHASE_CNT */ +/* + * PHASE_CNT (RW) + * + */ +#define QEIV2_PHASE_CNT_PHASE_CNT_MASK (0xFFFFFFFFUL) +#define QEIV2_PHASE_CNT_PHASE_CNT_SHIFT (0U) +#define QEIV2_PHASE_CNT_PHASE_CNT_SET(x) (((uint32_t)(x) << QEIV2_PHASE_CNT_PHASE_CNT_SHIFT) & QEIV2_PHASE_CNT_PHASE_CNT_MASK) +#define QEIV2_PHASE_CNT_PHASE_CNT_GET(x) (((uint32_t)(x) & QEIV2_PHASE_CNT_PHASE_CNT_MASK) >> QEIV2_PHASE_CNT_PHASE_CNT_SHIFT) + +/* Bitfield definition for register: PHASE_UPDATE */ +/* + * INC (WO) + * + * set to add value to phase_cnt + */ +#define QEIV2_PHASE_UPDATE_INC_MASK (0x80000000UL) +#define QEIV2_PHASE_UPDATE_INC_SHIFT (31U) +#define QEIV2_PHASE_UPDATE_INC_SET(x) (((uint32_t)(x) << QEIV2_PHASE_UPDATE_INC_SHIFT) & QEIV2_PHASE_UPDATE_INC_MASK) +#define QEIV2_PHASE_UPDATE_INC_GET(x) (((uint32_t)(x) & QEIV2_PHASE_UPDATE_INC_MASK) >> QEIV2_PHASE_UPDATE_INC_SHIFT) + +/* + * DEC (WO) + * + * set to minus value from phase_cnt(set inc and dec same time willl act inc) + */ +#define QEIV2_PHASE_UPDATE_DEC_MASK (0x40000000UL) +#define QEIV2_PHASE_UPDATE_DEC_SHIFT (30U) +#define QEIV2_PHASE_UPDATE_DEC_SET(x) (((uint32_t)(x) << QEIV2_PHASE_UPDATE_DEC_SHIFT) & QEIV2_PHASE_UPDATE_DEC_MASK) +#define QEIV2_PHASE_UPDATE_DEC_GET(x) (((uint32_t)(x) & QEIV2_PHASE_UPDATE_DEC_MASK) >> QEIV2_PHASE_UPDATE_DEC_SHIFT) + +/* + * VALUE (WO) + * + * value to be added or minus from phase_cnt. only valid when inc or dec is set in one 32bit write operation + */ +#define QEIV2_PHASE_UPDATE_VALUE_MASK (0x3FFFFFFFUL) +#define QEIV2_PHASE_UPDATE_VALUE_SHIFT (0U) +#define QEIV2_PHASE_UPDATE_VALUE_SET(x) (((uint32_t)(x) << QEIV2_PHASE_UPDATE_VALUE_SHIFT) & QEIV2_PHASE_UPDATE_VALUE_MASK) +#define QEIV2_PHASE_UPDATE_VALUE_GET(x) (((uint32_t)(x) & QEIV2_PHASE_UPDATE_VALUE_MASK) >> QEIV2_PHASE_UPDATE_VALUE_SHIFT) + +/* Bitfield definition for register: POSITION */ +/* + * POSITION (RW) + * + */ +#define QEIV2_POSITION_POSITION_MASK (0xFFFFFFFFUL) +#define QEIV2_POSITION_POSITION_SHIFT (0U) +#define QEIV2_POSITION_POSITION_SET(x) (((uint32_t)(x) << QEIV2_POSITION_POSITION_SHIFT) & QEIV2_POSITION_POSITION_MASK) +#define QEIV2_POSITION_POSITION_GET(x) (((uint32_t)(x) & QEIV2_POSITION_POSITION_MASK) >> QEIV2_POSITION_POSITION_SHIFT) + +/* Bitfield definition for register: POSITION_UPDATE */ +/* + * INC (WO) + * + * set to add value to position + */ +#define QEIV2_POSITION_UPDATE_INC_MASK (0x80000000UL) +#define QEIV2_POSITION_UPDATE_INC_SHIFT (31U) +#define QEIV2_POSITION_UPDATE_INC_SET(x) (((uint32_t)(x) << QEIV2_POSITION_UPDATE_INC_SHIFT) & QEIV2_POSITION_UPDATE_INC_MASK) +#define QEIV2_POSITION_UPDATE_INC_GET(x) (((uint32_t)(x) & QEIV2_POSITION_UPDATE_INC_MASK) >> QEIV2_POSITION_UPDATE_INC_SHIFT) + +/* + * DEC (WO) + * + * set to minus value from position(set inc and dec same time willl act inc) + */ +#define QEIV2_POSITION_UPDATE_DEC_MASK (0x40000000UL) +#define QEIV2_POSITION_UPDATE_DEC_SHIFT (30U) +#define QEIV2_POSITION_UPDATE_DEC_SET(x) (((uint32_t)(x) << QEIV2_POSITION_UPDATE_DEC_SHIFT) & QEIV2_POSITION_UPDATE_DEC_MASK) +#define QEIV2_POSITION_UPDATE_DEC_GET(x) (((uint32_t)(x) & QEIV2_POSITION_UPDATE_DEC_MASK) >> QEIV2_POSITION_UPDATE_DEC_SHIFT) + +/* + * VALUE (WO) + * + * value to be added or minus from position. only valid when inc or dec is set in one 32bit write operation + */ +#define QEIV2_POSITION_UPDATE_VALUE_MASK (0x3FFFFFFFUL) +#define QEIV2_POSITION_UPDATE_VALUE_SHIFT (0U) +#define QEIV2_POSITION_UPDATE_VALUE_SET(x) (((uint32_t)(x) << QEIV2_POSITION_UPDATE_VALUE_SHIFT) & QEIV2_POSITION_UPDATE_VALUE_MASK) +#define QEIV2_POSITION_UPDATE_VALUE_GET(x) (((uint32_t)(x) & QEIV2_POSITION_UPDATE_VALUE_MASK) >> QEIV2_POSITION_UPDATE_VALUE_SHIFT) + +/* Bitfield definition for register: ANGLE */ +/* + * ANGLE (RO) + * + */ +#define QEIV2_ANGLE_ANGLE_MASK (0xFFFFFFFFUL) +#define QEIV2_ANGLE_ANGLE_SHIFT (0U) +#define QEIV2_ANGLE_ANGLE_GET(x) (((uint32_t)(x) & QEIV2_ANGLE_ANGLE_MASK) >> QEIV2_ANGLE_ANGLE_SHIFT) + +/* Bitfield definition for register: POS_TIMEOUT */ +/* + * ENABLE (RW) + * + * enable position timeout feature, if timeout, send valid again + */ +#define QEIV2_POS_TIMEOUT_ENABLE_MASK (0x80000000UL) +#define QEIV2_POS_TIMEOUT_ENABLE_SHIFT (31U) +#define QEIV2_POS_TIMEOUT_ENABLE_SET(x) (((uint32_t)(x) << QEIV2_POS_TIMEOUT_ENABLE_SHIFT) & QEIV2_POS_TIMEOUT_ENABLE_MASK) +#define QEIV2_POS_TIMEOUT_ENABLE_GET(x) (((uint32_t)(x) & QEIV2_POS_TIMEOUT_ENABLE_MASK) >> QEIV2_POS_TIMEOUT_ENABLE_SHIFT) + +/* + * TIMEOUT (RW) + * + * postion timeout value + */ +#define QEIV2_POS_TIMEOUT_TIMEOUT_MASK (0x7FFFFFFFUL) +#define QEIV2_POS_TIMEOUT_TIMEOUT_SHIFT (0U) +#define QEIV2_POS_TIMEOUT_TIMEOUT_SET(x) (((uint32_t)(x) << QEIV2_POS_TIMEOUT_TIMEOUT_SHIFT) & QEIV2_POS_TIMEOUT_TIMEOUT_MASK) +#define QEIV2_POS_TIMEOUT_TIMEOUT_GET(x) (((uint32_t)(x) & QEIV2_POS_TIMEOUT_TIMEOUT_MASK) >> QEIV2_POS_TIMEOUT_TIMEOUT_SHIFT) + + + +/* COUNT register group index macro definition */ +#define QEIV2_COUNT_CURRENT (0UL) +#define QEIV2_COUNT_READ (1UL) +#define QEIV2_COUNT_SNAP0 (2UL) +#define QEIV2_COUNT_SNAP1 (3UL) + +/* FILT_CFG register group index macro definition */ +#define QEIV2_FILT_CFG_FILT_CFG_A (0UL) +#define QEIV2_FILT_CFG_FILT_CFG_B (1UL) +#define QEIV2_FILT_CFG_FILT_CFG_Z (2UL) +#define QEIV2_FILT_CFG_FILT_CFG_H (3UL) +#define QEIV2_FILT_CFG_FILT_CFG_H2 (4UL) +#define QEIV2_FILT_CFG_FILT_CFG_F (5UL) + +/* UVW_POS register group index macro definition */ +#define QEIV2_UVW_POS_UVW_POS0 (0UL) +#define QEIV2_UVW_POS_UVW_POS1 (1UL) +#define QEIV2_UVW_POS_UVW_POS2 (2UL) +#define QEIV2_UVW_POS_UVW_POS3 (3UL) +#define QEIV2_UVW_POS_UVW_POS4 (4UL) +#define QEIV2_UVW_POS_UVW_POS5 (5UL) + +/* UVW_POS_CFG register group index macro definition */ +#define QEIV2_UVW_POS_CFG_UVW_POS0_CFG (0UL) +#define QEIV2_UVW_POS_CFG_UVW_POS1_CFG (1UL) +#define QEIV2_UVW_POS_CFG_UVW_POS2_CFG (2UL) +#define QEIV2_UVW_POS_CFG_UVW_POS3_CFG (3UL) +#define QEIV2_UVW_POS_CFG_UVW_POS4_CFG (4UL) +#define QEIV2_UVW_POS_CFG_UVW_POS5_CFG (5UL) + + +#endif /* HPM_QEIV2_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_qeo_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_qeo_regs.h new file mode 100644 index 00000000000..e2034885765 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_qeo_regs.h @@ -0,0 +1,1065 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_QEO_H +#define HPM_QEO_H + +typedef struct { + struct { + __RW uint32_t MODE; /* 0x0: analog waves mode */ + __RW uint32_t RESOLUTION; /* 0x4: resolution of wave0/1/2 */ + __RW uint32_t PHASE_SHIFT[3]; /* 0x8 - 0x10: wave0 phase shifter */ + __RW uint32_t VD_VQ_INJECT[3]; /* 0x14 - 0x1C: wave0 vd vq inject value */ + __W uint32_t VD_VQ_LOAD; /* 0x20: load wave0/1/2 vd vq value */ + __RW uint32_t AMPLITUDE[3]; /* 0x24 - 0x2C: wave0 amplitude */ + __RW uint32_t MID_POINT[3]; /* 0x30 - 0x38: wave0 output middle point offset */ + struct { + __RW uint32_t MIN; /* 0x3C: wave0 low area limit value */ + __RW uint32_t MAX; /* 0x40: wave0 high area limit value */ + } LIMIT[3]; + __RW uint32_t DEADZONE_SHIFT[3]; /* 0x54 - 0x5C: deadzone_shifter_wave0 */ + } WAVE; + struct { + __RW uint32_t MODE; /* 0x60: wave_a/b/z output mode */ + __RW uint32_t RESOLUTION; /* 0x64: resolution of wave_a/b/z */ + __RW uint32_t PHASE_SHIFT[3]; /* 0x68 - 0x70: wave_a phase shifter */ + __RW uint32_t LINE_WIDTH; /* 0x74: Two-phase orthogonality wave 1/4 period */ + __RW uint32_t WDOG_WIDTH; /* 0x78: wdog width of qeo */ + __W uint32_t POSTION_SYNC; /* 0x7C: sync abz owned postion */ + } ABZ; + struct { + __RW uint32_t MODE; /* 0x80: pwm mode */ + __RW uint32_t RESOLUTION; /* 0x84: resolution of pwm */ + __RW uint32_t PHASE_SHIFT[4]; /* 0x88 - 0x94: pwm_a phase shifter */ + __RW uint32_t PHASE_TABLE[24]; /* 0x98 - 0xF4: pwm_phase_table 0 */ + } PWM; + __RW uint32_t POSTION_SOFTWARE; /* 0xF8: softwave inject postion */ + __RW uint32_t POSTION_SEL; /* 0xFC: select softwave inject postion */ + __R uint32_t STATUS; /* 0x100: qeo status */ + __R uint32_t DEBUG0; /* 0x104: qeo debug 0 */ + __R uint32_t DEBUG1; /* 0x108: qeo debug 1 */ + __R uint32_t DEBUG2; /* 0x10C: qeo debug 2 */ + __R uint32_t DEBUG3; /* 0x110: qeo debug 3 */ +} QEO_Type; + + +/* Bitfield definition for register of struct WAVE: MODE */ +/* + * WAVE2_ABOVE_MAX_LIMIT (RW) + * + * wave2 above max limit mode. + * 0: output 0xffff. + * 1: output 0x0. + * 2: output as level_max_limit2.level0_max_limit + */ +#define QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_MASK (0xC0000000UL) +#define QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SHIFT (30U) +#define QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SHIFT) + +/* + * WAVE2_HIGH_AREA1_LIMIT (RW) + * + * wave2 high area1 limit mode. + * 0: output 0xffff. + * 1: output as level_max_limit2.level0_max_limit + */ +#define QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_MASK (0x20000000UL) +#define QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SHIFT (29U) +#define QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SHIFT) + +/* + * WAVE2_HIGH_AREA0_LIMIT (RW) + * + * wave2 high area0 limit mode. + * 0: output 0xffff. + * 1: output as level_max_limit2.level0_max_limit + */ +#define QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_MASK (0x10000000UL) +#define QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SHIFT (28U) +#define QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SHIFT) + +/* + * WAVE2_LOW_AREA1_LIMIT (RW) + * + * wave2 low area1 limit mode. + * 0: output 0. + * 1: output as level_min_limit2.level1_min_limit + */ +#define QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_MASK (0x8000000UL) +#define QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SHIFT (27U) +#define QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SHIFT) + +/* + * WAVE2_LOW_AREA0_LIMIT (RW) + * + * wave2 low area0 limit mode. + * 0: output 0. + * 1: output as level_min_limit2.level1_min_limit + */ +#define QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_MASK (0x4000000UL) +#define QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SHIFT (26U) +#define QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SHIFT) + +/* + * WAVE2_BELOW_MIN_LIMIT (RW) + * + * wave2 below min limit mode. + * 0: output 0. + * 1: output 0xffff. + * 2: output as level_min_limit2.level1_min_limit + */ +#define QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_MASK (0x3000000UL) +#define QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SHIFT (24U) +#define QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SHIFT) + +/* + * WAVE1_ABOVE_MAX_LIMIT (RW) + * + * wave1 above max limit mode. + * 0: output 0xffff. + * 1: output 0x0. + * 2: output as level_max_limit1.level0_max_limit + */ +#define QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_MASK (0xC00000UL) +#define QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SHIFT (22U) +#define QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SHIFT) + +/* + * WAVE1_HIGH_AREA1_LIMIT (RW) + * + * wave1 high area1 limit mode. + * 0: output 0xffff. + * 1: output as level_max_limit1.level0_max_limit + */ +#define QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_MASK (0x200000UL) +#define QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SHIFT (21U) +#define QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SHIFT) + +/* + * WAVE1_HIGH_AREA0_LIMIT (RW) + * + * wave1 high area0 limit mode. + * 0: output 0xffff. + * 1: output as level_max_limit1.level0_max_limit + */ +#define QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_MASK (0x100000UL) +#define QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SHIFT (20U) +#define QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SHIFT) + +/* + * WAVE1_LOW_AREA1_LIMIT (RW) + * + * wave1 low area1 limit mode. + * 0: output 0. + * 1: output as level_min_limit1.level1_min_limit + */ +#define QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_MASK (0x80000UL) +#define QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SHIFT (19U) +#define QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SHIFT) + +/* + * WAVE1_LOW_AREA0_LIMIT (RW) + * + * wave1 low area0 limit mode. + * 0: output 0. + * 1: output as level_min_limit1.level1_min_limit + */ +#define QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_MASK (0x40000UL) +#define QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SHIFT (18U) +#define QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SHIFT) + +/* + * WAVE1_BELOW_MIN_LIMIT (RW) + * + * wave1 below min limit mode. + * 0: output 0. + * 1: output 0xffff. + * 2: output as level_min_limit1.level1_min_limit + */ +#define QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_MASK (0x30000UL) +#define QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SHIFT (16U) +#define QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SHIFT) + +/* + * WAVE0_ABOVE_MAX_LIMIT (RW) + * + * wave0 above max limit mode. + * 0: output 0xffff. + * 1: output 0x0. + * 2: output as level_max_limit0.level0_max_limit + */ +#define QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_MASK (0xC000U) +#define QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SHIFT (14U) +#define QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SHIFT) + +/* + * WAVE0_HIGH_AREA1_LIMIT (RW) + * + * wave0 high area1 limit mode. + * 0: output 0xffff. + * 1: output as level_max_limit0.level0_max_limit + */ +#define QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_MASK (0x2000U) +#define QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SHIFT (13U) +#define QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SHIFT) + +/* + * WAVE0_HIGH_AREA0_LIMIT (RW) + * + * wave0 high area0 limit mode. + * 0: output 0xffff. + * 1: output as level_max_limit0.level0_max_limit + */ +#define QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_MASK (0x1000U) +#define QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SHIFT (12U) +#define QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SHIFT) + +/* + * WAVE0_LOW_AREA1_LIMIT (RW) + * + * wave0 low area1 limit mode. + * 0: output 0. + * 1: output as level_min_limit0.level1_min_limit + */ +#define QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_MASK (0x800U) +#define QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SHIFT (11U) +#define QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SHIFT) + +/* + * WAVE0_LOW_AREA0_LIMIT (RW) + * + * wave0 low area0 limit mode. + * 0: output 0. + * 1: output as level_min_limit0.level1_min_limit + */ +#define QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_MASK (0x400U) +#define QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SHIFT (10U) +#define QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SHIFT) + +/* + * WAVE0_BELOW_MIN_LIMIT (RW) + * + * wave0 below min limit mode. + * 0: output 0. + * 1: output 0xffff. + * 2: output as level_min_limit0.level1_min_limit + */ +#define QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_MASK (0x300U) +#define QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SHIFT (8U) +#define QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SHIFT) + +/* + * SADDLE_TYPE (RW) + * + * saddle type seclect; + * 0:standard saddle. + * 1: triple-cos saddle. + */ +#define QEO_WAVE_MODE_SADDLE_TYPE_MASK (0x80U) +#define QEO_WAVE_MODE_SADDLE_TYPE_SHIFT (7U) +#define QEO_WAVE_MODE_SADDLE_TYPE_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_SADDLE_TYPE_SHIFT) & QEO_WAVE_MODE_SADDLE_TYPE_MASK) +#define QEO_WAVE_MODE_SADDLE_TYPE_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_SADDLE_TYPE_MASK) >> QEO_WAVE_MODE_SADDLE_TYPE_SHIFT) + +/* + * EN_WAVE2_VD_VQ_INJECT (RW) + * + * wave2 VdVq inject enable. + * 0: disable VdVq inject. + * 1: enable VdVq inject. + */ +#define QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_MASK (0x40U) +#define QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_SHIFT (6U) +#define QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_SHIFT) & QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_MASK) +#define QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_MASK) >> QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_SHIFT) + +/* + * EN_WAVE1_VD_VQ_INJECT (RW) + * + * wave1 VdVq inject enable. + * 0: disable VdVq inject. + * 1: enable VdVq inject. + */ +#define QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_MASK (0x20U) +#define QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_SHIFT (5U) +#define QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_SHIFT) & QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_MASK) +#define QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_MASK) >> QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_SHIFT) + +/* + * EN_WAVE0_VD_VQ_INJECT (RW) + * + * wave0 VdVq inject enable. + * 0: disable VdVq inject. + * 1: enable VdVq inject. + */ +#define QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_MASK (0x10U) +#define QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_SHIFT (4U) +#define QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_SHIFT) & QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_MASK) +#define QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_MASK) >> QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_SHIFT) + +/* + * WAVES_OUTPUT_TYPE (RW) + * + * wave0/1/2 output mode. + * 0: cosine wave. + * 1: saddle wave. + * 2. abs cosine wave. + * 3. saw wave + */ +#define QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK (0x3U) +#define QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_SHIFT (0U) +#define QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_SHIFT) & QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK) +#define QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK) >> QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_SHIFT) + +/* Bitfield definition for register of struct WAVE: RESOLUTION */ +/* + * LINES (RW) + * + * wave0/1/2 resolution + */ +#define QEO_WAVE_RESOLUTION_LINES_MASK (0xFFFFFFFFUL) +#define QEO_WAVE_RESOLUTION_LINES_SHIFT (0U) +#define QEO_WAVE_RESOLUTION_LINES_SET(x) (((uint32_t)(x) << QEO_WAVE_RESOLUTION_LINES_SHIFT) & QEO_WAVE_RESOLUTION_LINES_MASK) +#define QEO_WAVE_RESOLUTION_LINES_GET(x) (((uint32_t)(x) & QEO_WAVE_RESOLUTION_LINES_MASK) >> QEO_WAVE_RESOLUTION_LINES_SHIFT) + +/* Bitfield definition for register of struct WAVE: WAVE0 */ +/* + * VAL (RW) + * + * wave0 phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^16) period + */ +#define QEO_WAVE_PHASE_SHIFT_VAL_MASK (0xFFFFU) +#define QEO_WAVE_PHASE_SHIFT_VAL_SHIFT (0U) +#define QEO_WAVE_PHASE_SHIFT_VAL_SET(x) (((uint32_t)(x) << QEO_WAVE_PHASE_SHIFT_VAL_SHIFT) & QEO_WAVE_PHASE_SHIFT_VAL_MASK) +#define QEO_WAVE_PHASE_SHIFT_VAL_GET(x) (((uint32_t)(x) & QEO_WAVE_PHASE_SHIFT_VAL_MASK) >> QEO_WAVE_PHASE_SHIFT_VAL_SHIFT) + +/* Bitfield definition for register of struct WAVE: WAVE0 */ +/* + * VQ_VAL (RW) + * + * Vq inject value + */ +#define QEO_WAVE_VD_VQ_INJECT_VQ_VAL_MASK (0xFFFF0000UL) +#define QEO_WAVE_VD_VQ_INJECT_VQ_VAL_SHIFT (16U) +#define QEO_WAVE_VD_VQ_INJECT_VQ_VAL_SET(x) (((uint32_t)(x) << QEO_WAVE_VD_VQ_INJECT_VQ_VAL_SHIFT) & QEO_WAVE_VD_VQ_INJECT_VQ_VAL_MASK) +#define QEO_WAVE_VD_VQ_INJECT_VQ_VAL_GET(x) (((uint32_t)(x) & QEO_WAVE_VD_VQ_INJECT_VQ_VAL_MASK) >> QEO_WAVE_VD_VQ_INJECT_VQ_VAL_SHIFT) + +/* + * VD_VAL (RW) + * + * Vd inject value + */ +#define QEO_WAVE_VD_VQ_INJECT_VD_VAL_MASK (0xFFFFU) +#define QEO_WAVE_VD_VQ_INJECT_VD_VAL_SHIFT (0U) +#define QEO_WAVE_VD_VQ_INJECT_VD_VAL_SET(x) (((uint32_t)(x) << QEO_WAVE_VD_VQ_INJECT_VD_VAL_SHIFT) & QEO_WAVE_VD_VQ_INJECT_VD_VAL_MASK) +#define QEO_WAVE_VD_VQ_INJECT_VD_VAL_GET(x) (((uint32_t)(x) & QEO_WAVE_VD_VQ_INJECT_VD_VAL_MASK) >> QEO_WAVE_VD_VQ_INJECT_VD_VAL_SHIFT) + +/* Bitfield definition for register of struct WAVE: VD_VQ_LOAD */ +/* + * LOAD (WO) + * + * load wave0/1/2 vd vq value. always read 0 + * 0: vd vq keep previous value. + * 1: load wave0/1/2 vd vq value at sametime. + */ +#define QEO_WAVE_VD_VQ_LOAD_LOAD_MASK (0x1U) +#define QEO_WAVE_VD_VQ_LOAD_LOAD_SHIFT (0U) +#define QEO_WAVE_VD_VQ_LOAD_LOAD_SET(x) (((uint32_t)(x) << QEO_WAVE_VD_VQ_LOAD_LOAD_SHIFT) & QEO_WAVE_VD_VQ_LOAD_LOAD_MASK) +#define QEO_WAVE_VD_VQ_LOAD_LOAD_GET(x) (((uint32_t)(x) & QEO_WAVE_VD_VQ_LOAD_LOAD_MASK) >> QEO_WAVE_VD_VQ_LOAD_LOAD_SHIFT) + +/* Bitfield definition for register of struct WAVE: WAVE0 */ +/* + * EN_SCAL (RW) + * + * enable wave amplitude scaling. 0: disable; 1: enable + */ +#define QEO_WAVE_AMPLITUDE_EN_SCAL_MASK (0x10000UL) +#define QEO_WAVE_AMPLITUDE_EN_SCAL_SHIFT (16U) +#define QEO_WAVE_AMPLITUDE_EN_SCAL_SET(x) (((uint32_t)(x) << QEO_WAVE_AMPLITUDE_EN_SCAL_SHIFT) & QEO_WAVE_AMPLITUDE_EN_SCAL_MASK) +#define QEO_WAVE_AMPLITUDE_EN_SCAL_GET(x) (((uint32_t)(x) & QEO_WAVE_AMPLITUDE_EN_SCAL_MASK) >> QEO_WAVE_AMPLITUDE_EN_SCAL_SHIFT) + +/* + * AMP_VAL (RW) + * + * amplitude scaling value. bit15-12 are integer part value. bit11-0 are fraction value. + */ +#define QEO_WAVE_AMPLITUDE_AMP_VAL_MASK (0xFFFFU) +#define QEO_WAVE_AMPLITUDE_AMP_VAL_SHIFT (0U) +#define QEO_WAVE_AMPLITUDE_AMP_VAL_SET(x) (((uint32_t)(x) << QEO_WAVE_AMPLITUDE_AMP_VAL_SHIFT) & QEO_WAVE_AMPLITUDE_AMP_VAL_MASK) +#define QEO_WAVE_AMPLITUDE_AMP_VAL_GET(x) (((uint32_t)(x) & QEO_WAVE_AMPLITUDE_AMP_VAL_MASK) >> QEO_WAVE_AMPLITUDE_AMP_VAL_SHIFT) + +/* Bitfield definition for register of struct WAVE: WAVE0 */ +/* + * VAL (RW) + * + * wave0 output middle point, use this value as 32 bit signed value. bit 31 is signed bit. bit30-27 is integer part value. bit26-0 is fraction value. + */ +#define QEO_WAVE_MID_POINT_VAL_MASK (0xFFFFFFFFUL) +#define QEO_WAVE_MID_POINT_VAL_SHIFT (0U) +#define QEO_WAVE_MID_POINT_VAL_SET(x) (((uint32_t)(x) << QEO_WAVE_MID_POINT_VAL_SHIFT) & QEO_WAVE_MID_POINT_VAL_MASK) +#define QEO_WAVE_MID_POINT_VAL_GET(x) (((uint32_t)(x) & QEO_WAVE_MID_POINT_VAL_MASK) >> QEO_WAVE_MID_POINT_VAL_SHIFT) + +/* Bitfield definition for register of struct WAVE: MIN */ +/* + * LIMIT1 (RW) + * + * low area limit level1 + */ +#define QEO_WAVE_LIMIT_MIN_LIMIT1_MASK (0xFFFF0000UL) +#define QEO_WAVE_LIMIT_MIN_LIMIT1_SHIFT (16U) +#define QEO_WAVE_LIMIT_MIN_LIMIT1_SET(x) (((uint32_t)(x) << QEO_WAVE_LIMIT_MIN_LIMIT1_SHIFT) & QEO_WAVE_LIMIT_MIN_LIMIT1_MASK) +#define QEO_WAVE_LIMIT_MIN_LIMIT1_GET(x) (((uint32_t)(x) & QEO_WAVE_LIMIT_MIN_LIMIT1_MASK) >> QEO_WAVE_LIMIT_MIN_LIMIT1_SHIFT) + +/* + * LIMIT0 (RW) + * + * low area limit level0 + */ +#define QEO_WAVE_LIMIT_MIN_LIMIT0_MASK (0xFFFFU) +#define QEO_WAVE_LIMIT_MIN_LIMIT0_SHIFT (0U) +#define QEO_WAVE_LIMIT_MIN_LIMIT0_SET(x) (((uint32_t)(x) << QEO_WAVE_LIMIT_MIN_LIMIT0_SHIFT) & QEO_WAVE_LIMIT_MIN_LIMIT0_MASK) +#define QEO_WAVE_LIMIT_MIN_LIMIT0_GET(x) (((uint32_t)(x) & QEO_WAVE_LIMIT_MIN_LIMIT0_MASK) >> QEO_WAVE_LIMIT_MIN_LIMIT0_SHIFT) + +/* Bitfield definition for register of struct WAVE: MAX */ +/* + * LIMIT1 (RW) + * + * high area limit level1 + */ +#define QEO_WAVE_LIMIT_MAX_LIMIT1_MASK (0xFFFF0000UL) +#define QEO_WAVE_LIMIT_MAX_LIMIT1_SHIFT (16U) +#define QEO_WAVE_LIMIT_MAX_LIMIT1_SET(x) (((uint32_t)(x) << QEO_WAVE_LIMIT_MAX_LIMIT1_SHIFT) & QEO_WAVE_LIMIT_MAX_LIMIT1_MASK) +#define QEO_WAVE_LIMIT_MAX_LIMIT1_GET(x) (((uint32_t)(x) & QEO_WAVE_LIMIT_MAX_LIMIT1_MASK) >> QEO_WAVE_LIMIT_MAX_LIMIT1_SHIFT) + +/* + * LIMIT0 (RW) + * + * high area limit level0 + */ +#define QEO_WAVE_LIMIT_MAX_LIMIT0_MASK (0xFFFFU) +#define QEO_WAVE_LIMIT_MAX_LIMIT0_SHIFT (0U) +#define QEO_WAVE_LIMIT_MAX_LIMIT0_SET(x) (((uint32_t)(x) << QEO_WAVE_LIMIT_MAX_LIMIT0_SHIFT) & QEO_WAVE_LIMIT_MAX_LIMIT0_MASK) +#define QEO_WAVE_LIMIT_MAX_LIMIT0_GET(x) (((uint32_t)(x) & QEO_WAVE_LIMIT_MAX_LIMIT0_MASK) >> QEO_WAVE_LIMIT_MAX_LIMIT0_SHIFT) + +/* Bitfield definition for register of struct WAVE: WAVE0 */ +/* + * VAL (RW) + * + * wave0 deadzone shifter value + */ +#define QEO_WAVE_DEADZONE_SHIFT_VAL_MASK (0xFFFFU) +#define QEO_WAVE_DEADZONE_SHIFT_VAL_SHIFT (0U) +#define QEO_WAVE_DEADZONE_SHIFT_VAL_SET(x) (((uint32_t)(x) << QEO_WAVE_DEADZONE_SHIFT_VAL_SHIFT) & QEO_WAVE_DEADZONE_SHIFT_VAL_MASK) +#define QEO_WAVE_DEADZONE_SHIFT_VAL_GET(x) (((uint32_t)(x) & QEO_WAVE_DEADZONE_SHIFT_VAL_MASK) >> QEO_WAVE_DEADZONE_SHIFT_VAL_SHIFT) + +/* Bitfield definition for register of struct ABZ: MODE */ +/* + * REVERSE_EDGE_TYPE (RW) + * + * pulse reverse wave，reverse edge point: + * 0: between pulse's posedge and negedge, min period dedicated by the num line_width + * 1: edge change point flow pulse's negedge. + */ +#define QEO_ABZ_MODE_REVERSE_EDGE_TYPE_MASK (0x10000000UL) +#define QEO_ABZ_MODE_REVERSE_EDGE_TYPE_SHIFT (28U) +#define QEO_ABZ_MODE_REVERSE_EDGE_TYPE_SET(x) (((uint32_t)(x) << QEO_ABZ_MODE_REVERSE_EDGE_TYPE_SHIFT) & QEO_ABZ_MODE_REVERSE_EDGE_TYPE_MASK) +#define QEO_ABZ_MODE_REVERSE_EDGE_TYPE_GET(x) (((uint32_t)(x) & QEO_ABZ_MODE_REVERSE_EDGE_TYPE_MASK) >> QEO_ABZ_MODE_REVERSE_EDGE_TYPE_SHIFT) + +/* + * EN_WDOG (RW) + * + * enable abz wdog: + * 0: disable abz wdog. + * 1: enable abz wdog. + */ +#define QEO_ABZ_MODE_EN_WDOG_MASK (0x1000000UL) +#define QEO_ABZ_MODE_EN_WDOG_SHIFT (24U) +#define QEO_ABZ_MODE_EN_WDOG_SET(x) (((uint32_t)(x) << QEO_ABZ_MODE_EN_WDOG_SHIFT) & QEO_ABZ_MODE_EN_WDOG_MASK) +#define QEO_ABZ_MODE_EN_WDOG_GET(x) (((uint32_t)(x) & QEO_ABZ_MODE_EN_WDOG_MASK) >> QEO_ABZ_MODE_EN_WDOG_SHIFT) + +/* + * Z_POLARITY (RW) + * + * wave_z polarity. + * 0: normal output. + * 1: invert normal output + */ +#define QEO_ABZ_MODE_Z_POLARITY_MASK (0x100000UL) +#define QEO_ABZ_MODE_Z_POLARITY_SHIFT (20U) +#define QEO_ABZ_MODE_Z_POLARITY_SET(x) (((uint32_t)(x) << QEO_ABZ_MODE_Z_POLARITY_SHIFT) & QEO_ABZ_MODE_Z_POLARITY_MASK) +#define QEO_ABZ_MODE_Z_POLARITY_GET(x) (((uint32_t)(x) & QEO_ABZ_MODE_Z_POLARITY_MASK) >> QEO_ABZ_MODE_Z_POLARITY_SHIFT) + +/* + * B_POLARITY (RW) + * + * wave_b polarity. + * 0: normal output. + * 1: invert normal output + */ +#define QEO_ABZ_MODE_B_POLARITY_MASK (0x10000UL) +#define QEO_ABZ_MODE_B_POLARITY_SHIFT (16U) +#define QEO_ABZ_MODE_B_POLARITY_SET(x) (((uint32_t)(x) << QEO_ABZ_MODE_B_POLARITY_SHIFT) & QEO_ABZ_MODE_B_POLARITY_MASK) +#define QEO_ABZ_MODE_B_POLARITY_GET(x) (((uint32_t)(x) & QEO_ABZ_MODE_B_POLARITY_MASK) >> QEO_ABZ_MODE_B_POLARITY_SHIFT) + +/* + * A_POLARITY (RW) + * + * wave_a polarity. + * 0: normal output. + * 1: invert normal output + */ +#define QEO_ABZ_MODE_A_POLARITY_MASK (0x1000U) +#define QEO_ABZ_MODE_A_POLARITY_SHIFT (12U) +#define QEO_ABZ_MODE_A_POLARITY_SET(x) (((uint32_t)(x) << QEO_ABZ_MODE_A_POLARITY_SHIFT) & QEO_ABZ_MODE_A_POLARITY_MASK) +#define QEO_ABZ_MODE_A_POLARITY_GET(x) (((uint32_t)(x) & QEO_ABZ_MODE_A_POLARITY_MASK) >> QEO_ABZ_MODE_A_POLARITY_SHIFT) + +/* + * Z_TYPE (RW) + * + * wave_z type: + * 0: zero pulse and output high at both wave_a and wave_b are high. mantain about 25% period. + * 1: zero pulse output high about 75% period. start from 0 to 75% period. + * 2: zero pulse output high about 100% period. + * 3: wave_z output as tree-phase wave same as wave_a/wave_b + */ +#define QEO_ABZ_MODE_Z_TYPE_MASK (0x300U) +#define QEO_ABZ_MODE_Z_TYPE_SHIFT (8U) +#define QEO_ABZ_MODE_Z_TYPE_SET(x) (((uint32_t)(x) << QEO_ABZ_MODE_Z_TYPE_SHIFT) & QEO_ABZ_MODE_Z_TYPE_MASK) +#define QEO_ABZ_MODE_Z_TYPE_GET(x) (((uint32_t)(x) & QEO_ABZ_MODE_Z_TYPE_MASK) >> QEO_ABZ_MODE_Z_TYPE_SHIFT) + +/* + * B_TYPE (RW) + * + * wave_b type: + * 0: Two-phase orthogonality wave_b. + * 1: reverse wave of pulse/reverse type. + * 2: down wave of up/down type. + * 3: Three-phase orthogonality wave_b. + */ +#define QEO_ABZ_MODE_B_TYPE_MASK (0x30U) +#define QEO_ABZ_MODE_B_TYPE_SHIFT (4U) +#define QEO_ABZ_MODE_B_TYPE_SET(x) (((uint32_t)(x) << QEO_ABZ_MODE_B_TYPE_SHIFT) & QEO_ABZ_MODE_B_TYPE_MASK) +#define QEO_ABZ_MODE_B_TYPE_GET(x) (((uint32_t)(x) & QEO_ABZ_MODE_B_TYPE_MASK) >> QEO_ABZ_MODE_B_TYPE_SHIFT) + +/* + * A_TYPE (RW) + * + * wave_a type: + * 0: Two-phase orthogonality wave_a. + * 1: pulse wave of pulse/reverse type. + * 2: up wave of up/down type. + * 3: Three-phase orthogonality wave_a. + */ +#define QEO_ABZ_MODE_A_TYPE_MASK (0x3U) +#define QEO_ABZ_MODE_A_TYPE_SHIFT (0U) +#define QEO_ABZ_MODE_A_TYPE_SET(x) (((uint32_t)(x) << QEO_ABZ_MODE_A_TYPE_SHIFT) & QEO_ABZ_MODE_A_TYPE_MASK) +#define QEO_ABZ_MODE_A_TYPE_GET(x) (((uint32_t)(x) & QEO_ABZ_MODE_A_TYPE_MASK) >> QEO_ABZ_MODE_A_TYPE_SHIFT) + +/* Bitfield definition for register of struct ABZ: RESOLUTION */ +/* + * LINES (RW) + * + * wave_a/b/z resolution + */ +#define QEO_ABZ_RESOLUTION_LINES_MASK (0xFFFFFFFFUL) +#define QEO_ABZ_RESOLUTION_LINES_SHIFT (0U) +#define QEO_ABZ_RESOLUTION_LINES_SET(x) (((uint32_t)(x) << QEO_ABZ_RESOLUTION_LINES_SHIFT) & QEO_ABZ_RESOLUTION_LINES_MASK) +#define QEO_ABZ_RESOLUTION_LINES_GET(x) (((uint32_t)(x) & QEO_ABZ_RESOLUTION_LINES_MASK) >> QEO_ABZ_RESOLUTION_LINES_SHIFT) + +/* Bitfield definition for register of struct ABZ: A */ +/* + * VAL (RW) + * + * wave_a phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^16) period. + */ +#define QEO_ABZ_PHASE_SHIFT_VAL_MASK (0xFFFFU) +#define QEO_ABZ_PHASE_SHIFT_VAL_SHIFT (0U) +#define QEO_ABZ_PHASE_SHIFT_VAL_SET(x) (((uint32_t)(x) << QEO_ABZ_PHASE_SHIFT_VAL_SHIFT) & QEO_ABZ_PHASE_SHIFT_VAL_MASK) +#define QEO_ABZ_PHASE_SHIFT_VAL_GET(x) (((uint32_t)(x) & QEO_ABZ_PHASE_SHIFT_VAL_MASK) >> QEO_ABZ_PHASE_SHIFT_VAL_SHIFT) + +/* Bitfield definition for register of struct ABZ: LINE_WIDTH */ +/* + * LINE (RW) + * + * the num of system clk by 1/4 period when using as Two-phase orthogonality. + */ +#define QEO_ABZ_LINE_WIDTH_LINE_MASK (0xFFFFFFFFUL) +#define QEO_ABZ_LINE_WIDTH_LINE_SHIFT (0U) +#define QEO_ABZ_LINE_WIDTH_LINE_SET(x) (((uint32_t)(x) << QEO_ABZ_LINE_WIDTH_LINE_SHIFT) & QEO_ABZ_LINE_WIDTH_LINE_MASK) +#define QEO_ABZ_LINE_WIDTH_LINE_GET(x) (((uint32_t)(x) & QEO_ABZ_LINE_WIDTH_LINE_MASK) >> QEO_ABZ_LINE_WIDTH_LINE_SHIFT) + +/* Bitfield definition for register of struct ABZ: WDOG_WIDTH */ +/* + * WIDTH (RW) + * + * wave will step 1/4 line to reminder user QEO still in controlled if QEO has no any toggle after the num of wdog_width sys clk. + */ +#define QEO_ABZ_WDOG_WIDTH_WIDTH_MASK (0xFFFFFFFFUL) +#define QEO_ABZ_WDOG_WIDTH_WIDTH_SHIFT (0U) +#define QEO_ABZ_WDOG_WIDTH_WIDTH_SET(x) (((uint32_t)(x) << QEO_ABZ_WDOG_WIDTH_WIDTH_SHIFT) & QEO_ABZ_WDOG_WIDTH_WIDTH_MASK) +#define QEO_ABZ_WDOG_WIDTH_WIDTH_GET(x) (((uint32_t)(x) & QEO_ABZ_WDOG_WIDTH_WIDTH_MASK) >> QEO_ABZ_WDOG_WIDTH_WIDTH_SHIFT) + +/* Bitfield definition for register of struct ABZ: POSTION_SYNC */ +/* + * POSTION (WO) + * + * load next valid postion into abz owned postion. always read 0 + * 0: sync abz owned postion with next valid postion. + * 1: not sync. + */ +#define QEO_ABZ_POSTION_SYNC_POSTION_MASK (0x1U) +#define QEO_ABZ_POSTION_SYNC_POSTION_SHIFT (0U) +#define QEO_ABZ_POSTION_SYNC_POSTION_SET(x) (((uint32_t)(x) << QEO_ABZ_POSTION_SYNC_POSTION_SHIFT) & QEO_ABZ_POSTION_SYNC_POSTION_MASK) +#define QEO_ABZ_POSTION_SYNC_POSTION_GET(x) (((uint32_t)(x) & QEO_ABZ_POSTION_SYNC_POSTION_MASK) >> QEO_ABZ_POSTION_SYNC_POSTION_SHIFT) + +/* Bitfield definition for register of struct PWM: MODE */ +/* + * PWM7_SAFETY (RW) + * + * PWM safety mode phase table + */ +#define QEO_PWM_MODE_PWM7_SAFETY_MASK (0xC0000000UL) +#define QEO_PWM_MODE_PWM7_SAFETY_SHIFT (30U) +#define QEO_PWM_MODE_PWM7_SAFETY_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM7_SAFETY_SHIFT) & QEO_PWM_MODE_PWM7_SAFETY_MASK) +#define QEO_PWM_MODE_PWM7_SAFETY_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM7_SAFETY_MASK) >> QEO_PWM_MODE_PWM7_SAFETY_SHIFT) + +/* + * PWM6_SAFETY (RW) + * + * PWM safety mode phase table + */ +#define QEO_PWM_MODE_PWM6_SAFETY_MASK (0x30000000UL) +#define QEO_PWM_MODE_PWM6_SAFETY_SHIFT (28U) +#define QEO_PWM_MODE_PWM6_SAFETY_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM6_SAFETY_SHIFT) & QEO_PWM_MODE_PWM6_SAFETY_MASK) +#define QEO_PWM_MODE_PWM6_SAFETY_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM6_SAFETY_MASK) >> QEO_PWM_MODE_PWM6_SAFETY_SHIFT) + +/* + * PWM5_SAFETY (RW) + * + * PWM safety mode phase table + */ +#define QEO_PWM_MODE_PWM5_SAFETY_MASK (0xC000000UL) +#define QEO_PWM_MODE_PWM5_SAFETY_SHIFT (26U) +#define QEO_PWM_MODE_PWM5_SAFETY_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM5_SAFETY_SHIFT) & QEO_PWM_MODE_PWM5_SAFETY_MASK) +#define QEO_PWM_MODE_PWM5_SAFETY_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM5_SAFETY_MASK) >> QEO_PWM_MODE_PWM5_SAFETY_SHIFT) + +/* + * PWM4_SAFETY (RW) + * + * PWM safety mode phase table + */ +#define QEO_PWM_MODE_PWM4_SAFETY_MASK (0x3000000UL) +#define QEO_PWM_MODE_PWM4_SAFETY_SHIFT (24U) +#define QEO_PWM_MODE_PWM4_SAFETY_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM4_SAFETY_SHIFT) & QEO_PWM_MODE_PWM4_SAFETY_MASK) +#define QEO_PWM_MODE_PWM4_SAFETY_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM4_SAFETY_MASK) >> QEO_PWM_MODE_PWM4_SAFETY_SHIFT) + +/* + * PWM3_SAFETY (RW) + * + * PWM safety mode phase table + */ +#define QEO_PWM_MODE_PWM3_SAFETY_MASK (0xC00000UL) +#define QEO_PWM_MODE_PWM3_SAFETY_SHIFT (22U) +#define QEO_PWM_MODE_PWM3_SAFETY_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM3_SAFETY_SHIFT) & QEO_PWM_MODE_PWM3_SAFETY_MASK) +#define QEO_PWM_MODE_PWM3_SAFETY_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM3_SAFETY_MASK) >> QEO_PWM_MODE_PWM3_SAFETY_SHIFT) + +/* + * PWM2_SAFETY (RW) + * + * PWM safety mode phase table + */ +#define QEO_PWM_MODE_PWM2_SAFETY_MASK (0x300000UL) +#define QEO_PWM_MODE_PWM2_SAFETY_SHIFT (20U) +#define QEO_PWM_MODE_PWM2_SAFETY_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM2_SAFETY_SHIFT) & QEO_PWM_MODE_PWM2_SAFETY_MASK) +#define QEO_PWM_MODE_PWM2_SAFETY_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM2_SAFETY_MASK) >> QEO_PWM_MODE_PWM2_SAFETY_SHIFT) + +/* + * PWM1_SAFETY (RW) + * + * PWM safety mode phase table + */ +#define QEO_PWM_MODE_PWM1_SAFETY_MASK (0xC0000UL) +#define QEO_PWM_MODE_PWM1_SAFETY_SHIFT (18U) +#define QEO_PWM_MODE_PWM1_SAFETY_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM1_SAFETY_SHIFT) & QEO_PWM_MODE_PWM1_SAFETY_MASK) +#define QEO_PWM_MODE_PWM1_SAFETY_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM1_SAFETY_MASK) >> QEO_PWM_MODE_PWM1_SAFETY_SHIFT) + +/* + * PWM0_SAFETY (RW) + * + * PWM safety mode phase table + */ +#define QEO_PWM_MODE_PWM0_SAFETY_MASK (0x30000UL) +#define QEO_PWM_MODE_PWM0_SAFETY_SHIFT (16U) +#define QEO_PWM_MODE_PWM0_SAFETY_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM0_SAFETY_SHIFT) & QEO_PWM_MODE_PWM0_SAFETY_MASK) +#define QEO_PWM_MODE_PWM0_SAFETY_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM0_SAFETY_MASK) >> QEO_PWM_MODE_PWM0_SAFETY_SHIFT) + +/* + * PWM_ENTER_SAFETY_MODE (RW) + * + * PWM enter safety mode + * 0: not enter + * 1: enter + */ +#define QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK (0x200U) +#define QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_SHIFT (9U) +#define QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_SHIFT) & QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK) +#define QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK) >> QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_SHIFT) + +/* + * PWM_SAFETY_BYPASS (RW) + * + * PWM safety mode bypass + * 0: not bypass + * 1: bypass + */ +#define QEO_PWM_MODE_PWM_SAFETY_BYPASS_MASK (0x100U) +#define QEO_PWM_MODE_PWM_SAFETY_BYPASS_SHIFT (8U) +#define QEO_PWM_MODE_PWM_SAFETY_BYPASS_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM_SAFETY_BYPASS_SHIFT) & QEO_PWM_MODE_PWM_SAFETY_BYPASS_MASK) +#define QEO_PWM_MODE_PWM_SAFETY_BYPASS_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM_SAFETY_BYPASS_MASK) >> QEO_PWM_MODE_PWM_SAFETY_BYPASS_SHIFT) + +/* + * REVISE_UP_DN (RW) + * + * exchange PWM pairs’ output + * 0: not exchange. + * 1: exchange. + */ +#define QEO_PWM_MODE_REVISE_UP_DN_MASK (0x10U) +#define QEO_PWM_MODE_REVISE_UP_DN_SHIFT (4U) +#define QEO_PWM_MODE_REVISE_UP_DN_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_REVISE_UP_DN_SHIFT) & QEO_PWM_MODE_REVISE_UP_DN_MASK) +#define QEO_PWM_MODE_REVISE_UP_DN_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_REVISE_UP_DN_MASK) >> QEO_PWM_MODE_REVISE_UP_DN_SHIFT) + +/* + * PHASE_NUM (RW) + * + * pwm force phase number. + */ +#define QEO_PWM_MODE_PHASE_NUM_MASK (0xFU) +#define QEO_PWM_MODE_PHASE_NUM_SHIFT (0U) +#define QEO_PWM_MODE_PHASE_NUM_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PHASE_NUM_SHIFT) & QEO_PWM_MODE_PHASE_NUM_MASK) +#define QEO_PWM_MODE_PHASE_NUM_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PHASE_NUM_MASK) >> QEO_PWM_MODE_PHASE_NUM_SHIFT) + +/* Bitfield definition for register of struct PWM: RESOLUTION */ +/* + * LINES (RW) + * + * pwm resolution + */ +#define QEO_PWM_RESOLUTION_LINES_MASK (0xFFFFFFFFUL) +#define QEO_PWM_RESOLUTION_LINES_SHIFT (0U) +#define QEO_PWM_RESOLUTION_LINES_SET(x) (((uint32_t)(x) << QEO_PWM_RESOLUTION_LINES_SHIFT) & QEO_PWM_RESOLUTION_LINES_MASK) +#define QEO_PWM_RESOLUTION_LINES_GET(x) (((uint32_t)(x) & QEO_PWM_RESOLUTION_LINES_MASK) >> QEO_PWM_RESOLUTION_LINES_SHIFT) + +/* Bitfield definition for register of struct PWM: A */ +/* + * VAL (RW) + * + * pwm_a phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^16) period + */ +#define QEO_PWM_PHASE_SHIFT_VAL_MASK (0xFFFFU) +#define QEO_PWM_PHASE_SHIFT_VAL_SHIFT (0U) +#define QEO_PWM_PHASE_SHIFT_VAL_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_SHIFT_VAL_SHIFT) & QEO_PWM_PHASE_SHIFT_VAL_MASK) +#define QEO_PWM_PHASE_SHIFT_VAL_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_SHIFT_VAL_MASK) >> QEO_PWM_PHASE_SHIFT_VAL_SHIFT) + +/* Bitfield definition for register of struct PWM: POSEDGE0 */ +/* + * PWM7 (RW) + * + * pwm phase table value + */ +#define QEO_PWM_PHASE_TABLE_PWM7_MASK (0xC000U) +#define QEO_PWM_PHASE_TABLE_PWM7_SHIFT (14U) +#define QEO_PWM_PHASE_TABLE_PWM7_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM7_SHIFT) & QEO_PWM_PHASE_TABLE_PWM7_MASK) +#define QEO_PWM_PHASE_TABLE_PWM7_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM7_MASK) >> QEO_PWM_PHASE_TABLE_PWM7_SHIFT) + +/* + * PWM6 (RW) + * + * pwm phase table value + */ +#define QEO_PWM_PHASE_TABLE_PWM6_MASK (0x3000U) +#define QEO_PWM_PHASE_TABLE_PWM6_SHIFT (12U) +#define QEO_PWM_PHASE_TABLE_PWM6_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM6_SHIFT) & QEO_PWM_PHASE_TABLE_PWM6_MASK) +#define QEO_PWM_PHASE_TABLE_PWM6_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM6_MASK) >> QEO_PWM_PHASE_TABLE_PWM6_SHIFT) + +/* + * PWM5 (RW) + * + * pwm phase table value + */ +#define QEO_PWM_PHASE_TABLE_PWM5_MASK (0xC00U) +#define QEO_PWM_PHASE_TABLE_PWM5_SHIFT (10U) +#define QEO_PWM_PHASE_TABLE_PWM5_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM5_SHIFT) & QEO_PWM_PHASE_TABLE_PWM5_MASK) +#define QEO_PWM_PHASE_TABLE_PWM5_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM5_MASK) >> QEO_PWM_PHASE_TABLE_PWM5_SHIFT) + +/* + * PWM4 (RW) + * + * pwm phase table value + */ +#define QEO_PWM_PHASE_TABLE_PWM4_MASK (0x300U) +#define QEO_PWM_PHASE_TABLE_PWM4_SHIFT (8U) +#define QEO_PWM_PHASE_TABLE_PWM4_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM4_SHIFT) & QEO_PWM_PHASE_TABLE_PWM4_MASK) +#define QEO_PWM_PHASE_TABLE_PWM4_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM4_MASK) >> QEO_PWM_PHASE_TABLE_PWM4_SHIFT) + +/* + * PWM3 (RW) + * + * pwm phase table value + */ +#define QEO_PWM_PHASE_TABLE_PWM3_MASK (0xC0U) +#define QEO_PWM_PHASE_TABLE_PWM3_SHIFT (6U) +#define QEO_PWM_PHASE_TABLE_PWM3_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM3_SHIFT) & QEO_PWM_PHASE_TABLE_PWM3_MASK) +#define QEO_PWM_PHASE_TABLE_PWM3_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM3_MASK) >> QEO_PWM_PHASE_TABLE_PWM3_SHIFT) + +/* + * PWM2 (RW) + * + * pwm phase table value + */ +#define QEO_PWM_PHASE_TABLE_PWM2_MASK (0x30U) +#define QEO_PWM_PHASE_TABLE_PWM2_SHIFT (4U) +#define QEO_PWM_PHASE_TABLE_PWM2_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM2_SHIFT) & QEO_PWM_PHASE_TABLE_PWM2_MASK) +#define QEO_PWM_PHASE_TABLE_PWM2_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM2_MASK) >> QEO_PWM_PHASE_TABLE_PWM2_SHIFT) + +/* + * PWM1 (RW) + * + * pwm phase table value + */ +#define QEO_PWM_PHASE_TABLE_PWM1_MASK (0xCU) +#define QEO_PWM_PHASE_TABLE_PWM1_SHIFT (2U) +#define QEO_PWM_PHASE_TABLE_PWM1_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM1_SHIFT) & QEO_PWM_PHASE_TABLE_PWM1_MASK) +#define QEO_PWM_PHASE_TABLE_PWM1_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM1_MASK) >> QEO_PWM_PHASE_TABLE_PWM1_SHIFT) + +/* + * PWM0 (RW) + * + * pwm phase table value + */ +#define QEO_PWM_PHASE_TABLE_PWM0_MASK (0x3U) +#define QEO_PWM_PHASE_TABLE_PWM0_SHIFT (0U) +#define QEO_PWM_PHASE_TABLE_PWM0_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM0_SHIFT) & QEO_PWM_PHASE_TABLE_PWM0_MASK) +#define QEO_PWM_PHASE_TABLE_PWM0_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM0_MASK) >> QEO_PWM_PHASE_TABLE_PWM0_SHIFT) + +/* Bitfield definition for register: POSTION_SOFTWARE */ +/* + * POSTION_SOFTWAVE (RW) + * + * softwave inject postion + */ +#define QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_MASK (0xFFFFFFFFUL) +#define QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_SHIFT (0U) +#define QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_SET(x) (((uint32_t)(x) << QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_SHIFT) & QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_MASK) +#define QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_GET(x) (((uint32_t)(x) & QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_MASK) >> QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_SHIFT) + +/* Bitfield definition for register: POSTION_SEL */ +/* + * POSTION_SEL (RW) + * + * enable softwave inject postion. + * 0: disable. + * 1: enable. + */ +#define QEO_POSTION_SEL_POSTION_SEL_MASK (0x1U) +#define QEO_POSTION_SEL_POSTION_SEL_SHIFT (0U) +#define QEO_POSTION_SEL_POSTION_SEL_SET(x) (((uint32_t)(x) << QEO_POSTION_SEL_POSTION_SEL_SHIFT) & QEO_POSTION_SEL_POSTION_SEL_MASK) +#define QEO_POSTION_SEL_POSTION_SEL_GET(x) (((uint32_t)(x) & QEO_POSTION_SEL_POSTION_SEL_MASK) >> QEO_POSTION_SEL_POSTION_SEL_SHIFT) + +/* Bitfield definition for register: STATUS */ +/* + * PWM_FOURCE (RO) + * + * qeo_pwm_force observe + */ +#define QEO_STATUS_PWM_FOURCE_MASK (0xFFFF0000UL) +#define QEO_STATUS_PWM_FOURCE_SHIFT (16U) +#define QEO_STATUS_PWM_FOURCE_GET(x) (((uint32_t)(x) & QEO_STATUS_PWM_FOURCE_MASK) >> QEO_STATUS_PWM_FOURCE_SHIFT) + +/* + * PWM_SAFETY (RO) + * + * pwm_fault status + */ +#define QEO_STATUS_PWM_SAFETY_MASK (0x1U) +#define QEO_STATUS_PWM_SAFETY_SHIFT (0U) +#define QEO_STATUS_PWM_SAFETY_GET(x) (((uint32_t)(x) & QEO_STATUS_PWM_SAFETY_MASK) >> QEO_STATUS_PWM_SAFETY_SHIFT) + +/* Bitfield definition for register: DEBUG0 */ +/* + * WAVE1 (RO) + * + * wave1 observe + */ +#define QEO_DEBUG0_WAVE1_MASK (0xFFFF0000UL) +#define QEO_DEBUG0_WAVE1_SHIFT (16U) +#define QEO_DEBUG0_WAVE1_GET(x) (((uint32_t)(x) & QEO_DEBUG0_WAVE1_MASK) >> QEO_DEBUG0_WAVE1_SHIFT) + +/* + * WAVE0 (RO) + * + * wave0 observe + */ +#define QEO_DEBUG0_WAVE0_MASK (0xFFFFU) +#define QEO_DEBUG0_WAVE0_SHIFT (0U) +#define QEO_DEBUG0_WAVE0_GET(x) (((uint32_t)(x) & QEO_DEBUG0_WAVE0_MASK) >> QEO_DEBUG0_WAVE0_SHIFT) + +/* Bitfield definition for register: DEBUG1 */ +/* + * QEO_FINISH (RO) + * + * qeo finish observe + */ +#define QEO_DEBUG1_QEO_FINISH_MASK (0x10000000UL) +#define QEO_DEBUG1_QEO_FINISH_SHIFT (28U) +#define QEO_DEBUG1_QEO_FINISH_GET(x) (((uint32_t)(x) & QEO_DEBUG1_QEO_FINISH_MASK) >> QEO_DEBUG1_QEO_FINISH_SHIFT) + +/* + * WAVE_Z (RO) + * + * wave_z observe + */ +#define QEO_DEBUG1_WAVE_Z_MASK (0x1000000UL) +#define QEO_DEBUG1_WAVE_Z_SHIFT (24U) +#define QEO_DEBUG1_WAVE_Z_GET(x) (((uint32_t)(x) & QEO_DEBUG1_WAVE_Z_MASK) >> QEO_DEBUG1_WAVE_Z_SHIFT) + +/* + * WAVE_B (RO) + * + * wave_b observe + */ +#define QEO_DEBUG1_WAVE_B_MASK (0x100000UL) +#define QEO_DEBUG1_WAVE_B_SHIFT (20U) +#define QEO_DEBUG1_WAVE_B_GET(x) (((uint32_t)(x) & QEO_DEBUG1_WAVE_B_MASK) >> QEO_DEBUG1_WAVE_B_SHIFT) + +/* + * WAVE_A (RO) + * + * wave_a observe + */ +#define QEO_DEBUG1_WAVE_A_MASK (0x10000UL) +#define QEO_DEBUG1_WAVE_A_SHIFT (16U) +#define QEO_DEBUG1_WAVE_A_GET(x) (((uint32_t)(x) & QEO_DEBUG1_WAVE_A_MASK) >> QEO_DEBUG1_WAVE_A_SHIFT) + +/* + * WAVE2 (RO) + * + * wave2 observe + */ +#define QEO_DEBUG1_WAVE2_MASK (0xFFFFU) +#define QEO_DEBUG1_WAVE2_SHIFT (0U) +#define QEO_DEBUG1_WAVE2_GET(x) (((uint32_t)(x) & QEO_DEBUG1_WAVE2_MASK) >> QEO_DEBUG1_WAVE2_SHIFT) + +/* Bitfield definition for register: DEBUG2 */ +/* + * ABZ_OWN_POSTION (RO) + * + * abz_own_postion observe + */ +#define QEO_DEBUG2_ABZ_OWN_POSTION_MASK (0xFFFFFFFFUL) +#define QEO_DEBUG2_ABZ_OWN_POSTION_SHIFT (0U) +#define QEO_DEBUG2_ABZ_OWN_POSTION_GET(x) (((uint32_t)(x) & QEO_DEBUG2_ABZ_OWN_POSTION_MASK) >> QEO_DEBUG2_ABZ_OWN_POSTION_SHIFT) + +/* Bitfield definition for register: DEBUG3 */ +/* + * ABZ_OWN_POSTION (RO) + * + * abz_own_postion observe + */ +#define QEO_DEBUG3_ABZ_OWN_POSTION_MASK (0xFFFFFFFFUL) +#define QEO_DEBUG3_ABZ_OWN_POSTION_SHIFT (0U) +#define QEO_DEBUG3_ABZ_OWN_POSTION_GET(x) (((uint32_t)(x) & QEO_DEBUG3_ABZ_OWN_POSTION_MASK) >> QEO_DEBUG3_ABZ_OWN_POSTION_SHIFT) + + + +/* PHASE_SHIFT register group index macro definition */ +#define QEO_WAVE_PHASE_SHIFT_WAVE0 (0UL) +#define QEO_WAVE_PHASE_SHIFT_WAVE1 (1UL) +#define QEO_WAVE_PHASE_SHIFT_WAVE2 (2UL) + +/* VD_VQ_INJECT register group index macro definition */ +#define QEO_WAVE_VD_VQ_INJECT_WAVE0 (0UL) +#define QEO_WAVE_VD_VQ_INJECT_WAVE1 (1UL) +#define QEO_WAVE_VD_VQ_INJECT_WAVE2 (2UL) + +/* AMPLITUDE register group index macro definition */ +#define QEO_WAVE_AMPLITUDE_WAVE0 (0UL) +#define QEO_WAVE_AMPLITUDE_WAVE1 (1UL) +#define QEO_WAVE_AMPLITUDE_WAVE2 (2UL) + +/* MID_POINT register group index macro definition */ +#define QEO_WAVE_MID_POINT_WAVE0 (0UL) +#define QEO_WAVE_MID_POINT_WAVE1 (1UL) +#define QEO_WAVE_MID_POINT_WAVE2 (2UL) + +/* LIMIT register group index macro definition */ +#define QEO_LIMIT_WAVE0 (0UL) +#define QEO_LIMIT_WAVE1 (1UL) +#define QEO_LIMIT_WAVE2 (2UL) + +/* DEADZONE_SHIFT register group index macro definition */ +#define QEO_WAVE_DEADZONE_SHIFT_WAVE0 (0UL) +#define QEO_WAVE_DEADZONE_SHIFT_WAVE1 (1UL) +#define QEO_WAVE_DEADZONE_SHIFT_WAVE2 (2UL) + +/* PHASE_SHIFT register group index macro definition */ +#define QEO_ABZ_PHASE_SHIFT_A (0UL) +#define QEO_ABZ_PHASE_SHIFT_B (1UL) +#define QEO_ABZ_PHASE_SHIFT_Z (2UL) + +/* PHASE_SHIFT register group index macro definition */ +#define QEO_PWM_PHASE_SHIFT_A (0UL) +#define QEO_PWM_PHASE_SHIFT_B (1UL) +#define QEO_PWM_PHASE_SHIFT_C (2UL) +#define QEO_PWM_PHASE_SHIFT_D (3UL) + +/* PHASE_TABLE register group index macro definition */ +#define QEO_PWM_PHASE_TABLE_POSEDGE0 (0UL) +#define QEO_PWM_PHASE_TABLE_POSEDGE1 (1UL) +#define QEO_PWM_PHASE_TABLE_POSEDGE2 (2UL) +#define QEO_PWM_PHASE_TABLE_POSEDGE3 (3UL) +#define QEO_PWM_PHASE_TABLE_POSEDGE4 (4UL) +#define QEO_PWM_PHASE_TABLE_POSEDGE5 (5UL) +#define QEO_PWM_PHASE_TABLE_POSEDGE6 (6UL) +#define QEO_PWM_PHASE_TABLE_POSEDGE7 (7UL) +#define QEO_PWM_PHASE_TABLE_POSEDGE8 (8UL) +#define QEO_PWM_PHASE_TABLE_POSEDGE9 (9UL) +#define QEO_PWM_PHASE_TABLE_POSEDGE10 (10UL) +#define QEO_PWM_PHASE_TABLE_POSEDGE11 (11UL) +#define QEO_PWM_PHASE_TABLE_NEGEDGE0 (12UL) +#define QEO_PWM_PHASE_TABLE_NEGEDGE1 (13UL) +#define QEO_PWM_PHASE_TABLE_NEGEDGE2 (14UL) +#define QEO_PWM_PHASE_TABLE_NEGEDGE3 (15UL) +#define QEO_PWM_PHASE_TABLE_NEGEDGE4 (16UL) +#define QEO_PWM_PHASE_TABLE_NEGEDGE5 (17UL) +#define QEO_PWM_PHASE_TABLE_NEGEDGE6 (18UL) +#define QEO_PWM_PHASE_TABLE_NEGEDGE7 (19UL) +#define QEO_PWM_PHASE_TABLE_NEGEDGE8 (20UL) +#define QEO_PWM_PHASE_TABLE_NEGEDGE9 (21UL) +#define QEO_PWM_PHASE_TABLE_NEGEDGE10 (22UL) +#define QEO_PWM_PHASE_TABLE_NEGEDGE11 (23UL) + + +#endif /* HPM_QEO_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_rdc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_rdc_regs.h new file mode 100644 index 00000000000..95d83945b6b --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_rdc_regs.h @@ -0,0 +1,1331 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_RDC_H +#define HPM_RDC_H + +typedef struct { + __RW uint32_t RDC_CTL; /* 0x0: rdc control */ + __R uint32_t ACC_I; /* 0x4: accumulate result of i_channel */ + __R uint32_t ACC_Q; /* 0x8: accumulate result of q_channel */ + __RW uint32_t IN_CTL; /* 0xC: input channel selection */ + __RW uint32_t OUT_CTL; /* 0x10: output channel selection */ + __R uint8_t RESERVED0[32]; /* 0x14 - 0x33: Reserved */ + __RW uint32_t EXC_TIMMING; /* 0x34: excitation signal timming setting */ + __RW uint32_t EXC_SCALING; /* 0x38: amplitude scaling for excitation */ + __RW uint32_t EXC_OFFSET; /* 0x3C: amplitude offset setting */ + __RW uint32_t PWM_SCALING; /* 0x40: amplitude scaling for excitation */ + __RW uint32_t PWM_OFFSET; /* 0x44: amplitude offset setting */ + __RW uint32_t TRIG_OUT0_CFG; /* 0x48: Configuration for trigger out 0 in clock cycle */ + __RW uint32_t TRIG_OUT1_CFG; /* 0x4C: Configuration for trigger out 1 in clock cycle */ + __RW uint32_t PWM_DZ; /* 0x50: pwm dead zone control in clock cycle */ + __RW uint32_t SYNC_OUT_CTRL; /* 0x54: synchronize output signal control */ + __RW uint32_t EXC_SYNC_DLY; /* 0x58: trigger in delay timming in soc bus cycle */ + __R uint8_t RESERVED1[20]; /* 0x5C - 0x6F: Reserved */ + __RW uint32_t MAX_I; /* 0x70: max value of i_channel */ + __RW uint32_t MIN_I; /* 0x74: min value of i_channel */ + __RW uint32_t MAX_Q; /* 0x78: max value of q_channel */ + __RW uint32_t MIN_Q; /* 0x7C: min value of q_channel */ + __RW uint32_t THRS_I; /* 0x80: the offset setting for edge detection of the i_channel */ + __RW uint32_t THRS_Q; /* 0x84: the offset setting for edge detection of the q_channel */ + __RW uint32_t EDG_DET_CTL; /* 0x88: the control for edge detection */ + __RW uint32_t ACC_SCALING; /* 0x8C: scaling for accumulation result */ + __RW uint32_t EXC_PERIOD; /* 0x90: period of excitation */ + __R uint8_t RESERVED2[12]; /* 0x94 - 0x9F: Reserved */ + __RW uint32_t SYNC_DELAY_I; /* 0xA0: delay setting in clock cycle for synchronous signal */ + __R uint8_t RESERVED3[4]; /* 0xA4 - 0xA7: Reserved */ + __R uint32_t RISE_DELAY_I; /* 0xA8: delay in clock cycle between excitation synchrnous signal and rising edge of i_channel data */ + __R uint32_t FALL_DELAY_I; /* 0xAC: delay in clock cycle between excitation synchrnous signal and falling edge of i_channel data */ + __R uint32_t SAMPLE_RISE_I; /* 0xB0: sample value on rising edge of rectify signal */ + __R uint32_t SAMPLE_FALL_I; /* 0xB4: sample value on falling edge of rectify signal */ + __R uint32_t ACC_CNT_I; /* 0xB8: number of accumulation */ + __R uint32_t SIGN_CNT_I; /* 0xBC: sample counter of opposite sign with rectify signal */ + __RW uint32_t SYNC_DELAY_Q; /* 0xC0: delay setting in clock cycle for synchronous signal */ + __R uint8_t RESERVED4[4]; /* 0xC4 - 0xC7: Reserved */ + __R uint32_t RISE_DELAY_Q; /* 0xC8: delay in clock cycle between excitation synchrnous signal and rising edge of q_channel data */ + __R uint32_t FALL_DELAY_Q; /* 0xCC: delay in clock cycle between excitation synchrnous signal and falling edge of q_channel data */ + __R uint32_t SAMPLE_RISE_Q; /* 0xD0: sample value on rising edge of rectify signal */ + __R uint32_t SAMPLE_FALL_Q; /* 0xD4: sample value on falling edge of rectify signal */ + __R uint32_t ACC_CNT_Q; /* 0xD8: number of accumulation */ + __R uint32_t SIGN_CNT_Q; /* 0xDC: sample counter of opposite sign with rectify signal */ + __RW uint32_t AMP_MAX; /* 0xE0: the maximum of acc amplitude */ + __RW uint32_t AMP_MIN; /* 0xE4: the minimum of acc amplitude */ + __RW uint32_t INT_EN; /* 0xE8: the interrupt mask control */ + __W uint32_t ADC_INT_STATE; /* 0xEC: the interrupt state */ +} RDC_Type; + + +/* Bitfield definition for register: RDC_CTL */ +/* + * TS_SEL (RW) + * + * Time stamp selection for accumulation + * 0: end of accumulation + * 1: start of accumulation + * 2: center of accumulation + */ +#define RDC_RDC_CTL_TS_SEL_MASK (0x300000UL) +#define RDC_RDC_CTL_TS_SEL_SHIFT (20U) +#define RDC_RDC_CTL_TS_SEL_SET(x) (((uint32_t)(x) << RDC_RDC_CTL_TS_SEL_SHIFT) & RDC_RDC_CTL_TS_SEL_MASK) +#define RDC_RDC_CTL_TS_SEL_GET(x) (((uint32_t)(x) & RDC_RDC_CTL_TS_SEL_MASK) >> RDC_RDC_CTL_TS_SEL_SHIFT) + +/* + * ACC_LEN (RW) + * + * Accumulate time, support on the fly change + * 0：1 cycle + * 1：2 cycles + * … + * 255: 256 cycles + */ +#define RDC_RDC_CTL_ACC_LEN_MASK (0xFF000UL) +#define RDC_RDC_CTL_ACC_LEN_SHIFT (12U) +#define RDC_RDC_CTL_ACC_LEN_SET(x) (((uint32_t)(x) << RDC_RDC_CTL_ACC_LEN_SHIFT) & RDC_RDC_CTL_ACC_LEN_MASK) +#define RDC_RDC_CTL_ACC_LEN_GET(x) (((uint32_t)(x) & RDC_RDC_CTL_ACC_LEN_MASK) >> RDC_RDC_CTL_ACC_LEN_SHIFT) + +/* + * RECTIFY_SEL (RW) + * + * Select reference point of rectify signal + * 0: 0 phase of internal exciting signal + * 1: 90 phase of internal exciting signal + * 2: 180 phase of internal exciting signal + * 3: 270 phase of internal exciting signal + * 4: use value on external pin + * 5: use invert value on external pin + */ +#define RDC_RDC_CTL_RECTIFY_SEL_MASK (0x70U) +#define RDC_RDC_CTL_RECTIFY_SEL_SHIFT (4U) +#define RDC_RDC_CTL_RECTIFY_SEL_SET(x) (((uint32_t)(x) << RDC_RDC_CTL_RECTIFY_SEL_SHIFT) & RDC_RDC_CTL_RECTIFY_SEL_MASK) +#define RDC_RDC_CTL_RECTIFY_SEL_GET(x) (((uint32_t)(x) & RDC_RDC_CTL_RECTIFY_SEL_MASK) >> RDC_RDC_CTL_RECTIFY_SEL_SHIFT) + +/* + * ACC_EN (RW) + * + * Enable rdc accumulate + * 0: rdc disable + * 1: rdc enable + */ +#define RDC_RDC_CTL_ACC_EN_MASK (0x4U) +#define RDC_RDC_CTL_ACC_EN_SHIFT (2U) +#define RDC_RDC_CTL_ACC_EN_SET(x) (((uint32_t)(x) << RDC_RDC_CTL_ACC_EN_SHIFT) & RDC_RDC_CTL_ACC_EN_MASK) +#define RDC_RDC_CTL_ACC_EN_GET(x) (((uint32_t)(x) & RDC_RDC_CTL_ACC_EN_MASK) >> RDC_RDC_CTL_ACC_EN_SHIFT) + +/* + * EXC_START (RW1C) + * + * Write 1 start excite signal, always read 0 + * 0: no effect + * 1: start excite signal + */ +#define RDC_RDC_CTL_EXC_START_MASK (0x2U) +#define RDC_RDC_CTL_EXC_START_SHIFT (1U) +#define RDC_RDC_CTL_EXC_START_SET(x) (((uint32_t)(x) << RDC_RDC_CTL_EXC_START_SHIFT) & RDC_RDC_CTL_EXC_START_MASK) +#define RDC_RDC_CTL_EXC_START_GET(x) (((uint32_t)(x) & RDC_RDC_CTL_EXC_START_MASK) >> RDC_RDC_CTL_EXC_START_SHIFT) + +/* + * EXC_EN (RW) + * + * Enable rdc excite signal + * 0: rdc disable + * 1: rdc enable + */ +#define RDC_RDC_CTL_EXC_EN_MASK (0x1U) +#define RDC_RDC_CTL_EXC_EN_SHIFT (0U) +#define RDC_RDC_CTL_EXC_EN_SET(x) (((uint32_t)(x) << RDC_RDC_CTL_EXC_EN_SHIFT) & RDC_RDC_CTL_EXC_EN_MASK) +#define RDC_RDC_CTL_EXC_EN_GET(x) (((uint32_t)(x) & RDC_RDC_CTL_EXC_EN_MASK) >> RDC_RDC_CTL_EXC_EN_SHIFT) + +/* Bitfield definition for register: ACC_I */ +/* + * ACC (RO) + * + * accumulate result of i_channel, this is a signed number + */ +#define RDC_ACC_I_ACC_MASK (0xFFFFFFFFUL) +#define RDC_ACC_I_ACC_SHIFT (0U) +#define RDC_ACC_I_ACC_GET(x) (((uint32_t)(x) & RDC_ACC_I_ACC_MASK) >> RDC_ACC_I_ACC_SHIFT) + +/* Bitfield definition for register: ACC_Q */ +/* + * ACC (RO) + * + * accumulate result of q_channel, this is a signed number + */ +#define RDC_ACC_Q_ACC_MASK (0xFFFFFFFFUL) +#define RDC_ACC_Q_ACC_SHIFT (0U) +#define RDC_ACC_Q_ACC_GET(x) (((uint32_t)(x) & RDC_ACC_Q_ACC_MASK) >> RDC_ACC_Q_ACC_SHIFT) + +/* Bitfield definition for register: IN_CTL */ +/* + * PORT_Q_SEL (RW) + * + * Input port selection for q_channel, + * 0:sel port0 + * 1:sel port1 + */ +#define RDC_IN_CTL_PORT_Q_SEL_MASK (0x100000UL) +#define RDC_IN_CTL_PORT_Q_SEL_SHIFT (20U) +#define RDC_IN_CTL_PORT_Q_SEL_SET(x) (((uint32_t)(x) << RDC_IN_CTL_PORT_Q_SEL_SHIFT) & RDC_IN_CTL_PORT_Q_SEL_MASK) +#define RDC_IN_CTL_PORT_Q_SEL_GET(x) (((uint32_t)(x) & RDC_IN_CTL_PORT_Q_SEL_MASK) >> RDC_IN_CTL_PORT_Q_SEL_SHIFT) + +/* + * CH_Q_SEL (RW) + * + * Input channel selection for q_channel + * 0: channel 0 selected + * 1: channel 1 selected + * … + * 31: channel 31 selected + */ +#define RDC_IN_CTL_CH_Q_SEL_MASK (0x1F000UL) +#define RDC_IN_CTL_CH_Q_SEL_SHIFT (12U) +#define RDC_IN_CTL_CH_Q_SEL_SET(x) (((uint32_t)(x) << RDC_IN_CTL_CH_Q_SEL_SHIFT) & RDC_IN_CTL_CH_Q_SEL_MASK) +#define RDC_IN_CTL_CH_Q_SEL_GET(x) (((uint32_t)(x) & RDC_IN_CTL_CH_Q_SEL_MASK) >> RDC_IN_CTL_CH_Q_SEL_SHIFT) + +/* + * PORT_I_SEL (RW) + * + * Input port selection for i_channel, + * 0:sel port0 + * 1:sel port1 + */ +#define RDC_IN_CTL_PORT_I_SEL_MASK (0x100U) +#define RDC_IN_CTL_PORT_I_SEL_SHIFT (8U) +#define RDC_IN_CTL_PORT_I_SEL_SET(x) (((uint32_t)(x) << RDC_IN_CTL_PORT_I_SEL_SHIFT) & RDC_IN_CTL_PORT_I_SEL_MASK) +#define RDC_IN_CTL_PORT_I_SEL_GET(x) (((uint32_t)(x) & RDC_IN_CTL_PORT_I_SEL_MASK) >> RDC_IN_CTL_PORT_I_SEL_SHIFT) + +/* + * CH_I_SEL (RW) + * + * Input channel selection for i_channel + * 0: channel 0 selected + * 1: channel 1 selected + * … + * 31: channel 31 selected + */ +#define RDC_IN_CTL_CH_I_SEL_MASK (0x1FU) +#define RDC_IN_CTL_CH_I_SEL_SHIFT (0U) +#define RDC_IN_CTL_CH_I_SEL_SET(x) (((uint32_t)(x) << RDC_IN_CTL_CH_I_SEL_SHIFT) & RDC_IN_CTL_CH_I_SEL_MASK) +#define RDC_IN_CTL_CH_I_SEL_GET(x) (((uint32_t)(x) & RDC_IN_CTL_CH_I_SEL_MASK) >> RDC_IN_CTL_CH_I_SEL_SHIFT) + +/* Bitfield definition for register: OUT_CTL */ +/* + * CH_Q_SEL (RW) + * + * Output channel selection for q_channel + */ +#define RDC_OUT_CTL_CH_Q_SEL_MASK (0x1F00U) +#define RDC_OUT_CTL_CH_Q_SEL_SHIFT (8U) +#define RDC_OUT_CTL_CH_Q_SEL_SET(x) (((uint32_t)(x) << RDC_OUT_CTL_CH_Q_SEL_SHIFT) & RDC_OUT_CTL_CH_Q_SEL_MASK) +#define RDC_OUT_CTL_CH_Q_SEL_GET(x) (((uint32_t)(x) & RDC_OUT_CTL_CH_Q_SEL_MASK) >> RDC_OUT_CTL_CH_Q_SEL_SHIFT) + +/* + * CH_I_SEL (RW) + * + * Output channel selection for i_channel + */ +#define RDC_OUT_CTL_CH_I_SEL_MASK (0x1FU) +#define RDC_OUT_CTL_CH_I_SEL_SHIFT (0U) +#define RDC_OUT_CTL_CH_I_SEL_SET(x) (((uint32_t)(x) << RDC_OUT_CTL_CH_I_SEL_SHIFT) & RDC_OUT_CTL_CH_I_SEL_MASK) +#define RDC_OUT_CTL_CH_I_SEL_GET(x) (((uint32_t)(x) & RDC_OUT_CTL_CH_I_SEL_MASK) >> RDC_OUT_CTL_CH_I_SEL_SHIFT) + +/* Bitfield definition for register: EXC_TIMMING */ +/* + * SWAP (RW) + * + * Swap output of PWM and DAC + * 0: disable swap + * 1: swap output + */ +#define RDC_EXC_TIMMING_SWAP_MASK (0x1000000UL) +#define RDC_EXC_TIMMING_SWAP_SHIFT (24U) +#define RDC_EXC_TIMMING_SWAP_SET(x) (((uint32_t)(x) << RDC_EXC_TIMMING_SWAP_SHIFT) & RDC_EXC_TIMMING_SWAP_MASK) +#define RDC_EXC_TIMMING_SWAP_GET(x) (((uint32_t)(x) & RDC_EXC_TIMMING_SWAP_MASK) >> RDC_EXC_TIMMING_SWAP_SHIFT) + +/* + * PWM_PRD (RW) + * + * Pwm period in samples， + * 0：1 sample period + * 1: 2 sample period + * ... + * 15: 16 sample period + */ +#define RDC_EXC_TIMMING_PWM_PRD_MASK (0xF00000UL) +#define RDC_EXC_TIMMING_PWM_PRD_SHIFT (20U) +#define RDC_EXC_TIMMING_PWM_PRD_SET(x) (((uint32_t)(x) << RDC_EXC_TIMMING_PWM_PRD_SHIFT) & RDC_EXC_TIMMING_PWM_PRD_MASK) +#define RDC_EXC_TIMMING_PWM_PRD_GET(x) (((uint32_t)(x) & RDC_EXC_TIMMING_PWM_PRD_MASK) >> RDC_EXC_TIMMING_PWM_PRD_SHIFT) + +/* + * SMP_NUM (RW) + * + * Number of sample every excitation period + * 0: 4 point + * 1: 8 point + * … + * 8: 1024 point + */ +#define RDC_EXC_TIMMING_SMP_NUM_MASK (0xF0000UL) +#define RDC_EXC_TIMMING_SMP_NUM_SHIFT (16U) +#define RDC_EXC_TIMMING_SMP_NUM_SET(x) (((uint32_t)(x) << RDC_EXC_TIMMING_SMP_NUM_SHIFT) & RDC_EXC_TIMMING_SMP_NUM_MASK) +#define RDC_EXC_TIMMING_SMP_NUM_GET(x) (((uint32_t)(x) & RDC_EXC_TIMMING_SMP_NUM_MASK) >> RDC_EXC_TIMMING_SMP_NUM_SHIFT) + +/* + * SMP_RATE (RW) + * + * The period for excitation sample in clock cycle， + * 0: not allowed + * 1: 1 cycle + * 2: 2 cycles + * … + * 65535 : 65535 cycles + */ +#define RDC_EXC_TIMMING_SMP_RATE_MASK (0xFFFFU) +#define RDC_EXC_TIMMING_SMP_RATE_SHIFT (0U) +#define RDC_EXC_TIMMING_SMP_RATE_SET(x) (((uint32_t)(x) << RDC_EXC_TIMMING_SMP_RATE_SHIFT) & RDC_EXC_TIMMING_SMP_RATE_MASK) +#define RDC_EXC_TIMMING_SMP_RATE_GET(x) (((uint32_t)(x) & RDC_EXC_TIMMING_SMP_RATE_MASK) >> RDC_EXC_TIMMING_SMP_RATE_SHIFT) + +/* Bitfield definition for register: EXC_SCALING */ +/* + * AMP_EXP (RW) + * + * Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp + */ +#define RDC_EXC_SCALING_AMP_EXP_MASK (0xF0U) +#define RDC_EXC_SCALING_AMP_EXP_SHIFT (4U) +#define RDC_EXC_SCALING_AMP_EXP_SET(x) (((uint32_t)(x) << RDC_EXC_SCALING_AMP_EXP_SHIFT) & RDC_EXC_SCALING_AMP_EXP_MASK) +#define RDC_EXC_SCALING_AMP_EXP_GET(x) (((uint32_t)(x) & RDC_EXC_SCALING_AMP_EXP_MASK) >> RDC_EXC_SCALING_AMP_EXP_SHIFT) + +/* + * AMP_MAN (RW) + * + * Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp + */ +#define RDC_EXC_SCALING_AMP_MAN_MASK (0xFU) +#define RDC_EXC_SCALING_AMP_MAN_SHIFT (0U) +#define RDC_EXC_SCALING_AMP_MAN_SET(x) (((uint32_t)(x) << RDC_EXC_SCALING_AMP_MAN_SHIFT) & RDC_EXC_SCALING_AMP_MAN_MASK) +#define RDC_EXC_SCALING_AMP_MAN_GET(x) (((uint32_t)(x) & RDC_EXC_SCALING_AMP_MAN_MASK) >> RDC_EXC_SCALING_AMP_MAN_SHIFT) + +/* Bitfield definition for register: EXC_OFFSET */ +/* + * AMP_OFFSET (RW) + * + * Offset for excitation + */ +#define RDC_EXC_OFFSET_AMP_OFFSET_MASK (0xFFFFFFUL) +#define RDC_EXC_OFFSET_AMP_OFFSET_SHIFT (0U) +#define RDC_EXC_OFFSET_AMP_OFFSET_SET(x) (((uint32_t)(x) << RDC_EXC_OFFSET_AMP_OFFSET_SHIFT) & RDC_EXC_OFFSET_AMP_OFFSET_MASK) +#define RDC_EXC_OFFSET_AMP_OFFSET_GET(x) (((uint32_t)(x) & RDC_EXC_OFFSET_AMP_OFFSET_MASK) >> RDC_EXC_OFFSET_AMP_OFFSET_SHIFT) + +/* Bitfield definition for register: PWM_SCALING */ +/* + * N_POL (RW) + * + * Polarity of exc_n signal + * 0: high active + * 1: low active + */ +#define RDC_PWM_SCALING_N_POL_MASK (0x2000U) +#define RDC_PWM_SCALING_N_POL_SHIFT (13U) +#define RDC_PWM_SCALING_N_POL_SET(x) (((uint32_t)(x) << RDC_PWM_SCALING_N_POL_SHIFT) & RDC_PWM_SCALING_N_POL_MASK) +#define RDC_PWM_SCALING_N_POL_GET(x) (((uint32_t)(x) & RDC_PWM_SCALING_N_POL_MASK) >> RDC_PWM_SCALING_N_POL_SHIFT) + +/* + * P_POL (RW) + * + * Polarity of exc_p signal + * 0: high active + * 1: low active + */ +#define RDC_PWM_SCALING_P_POL_MASK (0x1000U) +#define RDC_PWM_SCALING_P_POL_SHIFT (12U) +#define RDC_PWM_SCALING_P_POL_SET(x) (((uint32_t)(x) << RDC_PWM_SCALING_P_POL_SHIFT) & RDC_PWM_SCALING_P_POL_MASK) +#define RDC_PWM_SCALING_P_POL_GET(x) (((uint32_t)(x) & RDC_PWM_SCALING_P_POL_MASK) >> RDC_PWM_SCALING_P_POL_SHIFT) + +/* + * DITHER (RW) + * + * Enable dither of pwm + * 0: disable + * 1: enable + */ +#define RDC_PWM_SCALING_DITHER_MASK (0x100U) +#define RDC_PWM_SCALING_DITHER_SHIFT (8U) +#define RDC_PWM_SCALING_DITHER_SET(x) (((uint32_t)(x) << RDC_PWM_SCALING_DITHER_SHIFT) & RDC_PWM_SCALING_DITHER_MASK) +#define RDC_PWM_SCALING_DITHER_GET(x) (((uint32_t)(x) & RDC_PWM_SCALING_DITHER_MASK) >> RDC_PWM_SCALING_DITHER_SHIFT) + +/* + * AMP_EXP (RW) + * + * Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp + */ +#define RDC_PWM_SCALING_AMP_EXP_MASK (0xF0U) +#define RDC_PWM_SCALING_AMP_EXP_SHIFT (4U) +#define RDC_PWM_SCALING_AMP_EXP_SET(x) (((uint32_t)(x) << RDC_PWM_SCALING_AMP_EXP_SHIFT) & RDC_PWM_SCALING_AMP_EXP_MASK) +#define RDC_PWM_SCALING_AMP_EXP_GET(x) (((uint32_t)(x) & RDC_PWM_SCALING_AMP_EXP_MASK) >> RDC_PWM_SCALING_AMP_EXP_SHIFT) + +/* + * AMP_MAN (RW) + * + * Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp + */ +#define RDC_PWM_SCALING_AMP_MAN_MASK (0xFU) +#define RDC_PWM_SCALING_AMP_MAN_SHIFT (0U) +#define RDC_PWM_SCALING_AMP_MAN_SET(x) (((uint32_t)(x) << RDC_PWM_SCALING_AMP_MAN_SHIFT) & RDC_PWM_SCALING_AMP_MAN_MASK) +#define RDC_PWM_SCALING_AMP_MAN_GET(x) (((uint32_t)(x) & RDC_PWM_SCALING_AMP_MAN_MASK) >> RDC_PWM_SCALING_AMP_MAN_SHIFT) + +/* Bitfield definition for register: PWM_OFFSET */ +/* + * AMP_OFFSET (RW) + * + * Offset for excitation + */ +#define RDC_PWM_OFFSET_AMP_OFFSET_MASK (0xFFFFFFUL) +#define RDC_PWM_OFFSET_AMP_OFFSET_SHIFT (0U) +#define RDC_PWM_OFFSET_AMP_OFFSET_SET(x) (((uint32_t)(x) << RDC_PWM_OFFSET_AMP_OFFSET_SHIFT) & RDC_PWM_OFFSET_AMP_OFFSET_MASK) +#define RDC_PWM_OFFSET_AMP_OFFSET_GET(x) (((uint32_t)(x) & RDC_PWM_OFFSET_AMP_OFFSET_MASK) >> RDC_PWM_OFFSET_AMP_OFFSET_SHIFT) + +/* Bitfield definition for register: TRIG_OUT0_CFG */ +/* + * ENABLE (RW) + * + * Enable trigger out0 + * 0: disable + * 1: enable + */ +#define RDC_TRIG_OUT0_CFG_ENABLE_MASK (0x100000UL) +#define RDC_TRIG_OUT0_CFG_ENABLE_SHIFT (20U) +#define RDC_TRIG_OUT0_CFG_ENABLE_SET(x) (((uint32_t)(x) << RDC_TRIG_OUT0_CFG_ENABLE_SHIFT) & RDC_TRIG_OUT0_CFG_ENABLE_MASK) +#define RDC_TRIG_OUT0_CFG_ENABLE_GET(x) (((uint32_t)(x) & RDC_TRIG_OUT0_CFG_ENABLE_MASK) >> RDC_TRIG_OUT0_CFG_ENABLE_SHIFT) + +/* + * LEAD_TIM (RW) + * + * Lead time for trigger out0 from center of low level , this is a signed value + * … + * 2: 2 cycle befor center of low level + * 1: 1 cycle before center of low level + * 0: center of low level + * -1: 1cycle after center of low level + * -2: 2cycle after center of low level + */ +#define RDC_TRIG_OUT0_CFG_LEAD_TIM_MASK (0xFFFFFUL) +#define RDC_TRIG_OUT0_CFG_LEAD_TIM_SHIFT (0U) +#define RDC_TRIG_OUT0_CFG_LEAD_TIM_SET(x) (((uint32_t)(x) << RDC_TRIG_OUT0_CFG_LEAD_TIM_SHIFT) & RDC_TRIG_OUT0_CFG_LEAD_TIM_MASK) +#define RDC_TRIG_OUT0_CFG_LEAD_TIM_GET(x) (((uint32_t)(x) & RDC_TRIG_OUT0_CFG_LEAD_TIM_MASK) >> RDC_TRIG_OUT0_CFG_LEAD_TIM_SHIFT) + +/* Bitfield definition for register: TRIG_OUT1_CFG */ +/* + * ENABLE (RW) + * + * Enable trigger out1 + * 0: disable + * 1: enable + */ +#define RDC_TRIG_OUT1_CFG_ENABLE_MASK (0x100000UL) +#define RDC_TRIG_OUT1_CFG_ENABLE_SHIFT (20U) +#define RDC_TRIG_OUT1_CFG_ENABLE_SET(x) (((uint32_t)(x) << RDC_TRIG_OUT1_CFG_ENABLE_SHIFT) & RDC_TRIG_OUT1_CFG_ENABLE_MASK) +#define RDC_TRIG_OUT1_CFG_ENABLE_GET(x) (((uint32_t)(x) & RDC_TRIG_OUT1_CFG_ENABLE_MASK) >> RDC_TRIG_OUT1_CFG_ENABLE_SHIFT) + +/* + * LEAD_TIM (RW) + * + * Lead time for trigger out0 from center of hight level , this is a signed value + * … + * 2: 2 cycle befor center of hight level + * 1: 1 cycle before center of hight level + * 0: center of hight level + * -1: 1cycle after center of hight level + * -2: 2cycle after center of hight level + */ +#define RDC_TRIG_OUT1_CFG_LEAD_TIM_MASK (0xFFFFFUL) +#define RDC_TRIG_OUT1_CFG_LEAD_TIM_SHIFT (0U) +#define RDC_TRIG_OUT1_CFG_LEAD_TIM_SET(x) (((uint32_t)(x) << RDC_TRIG_OUT1_CFG_LEAD_TIM_SHIFT) & RDC_TRIG_OUT1_CFG_LEAD_TIM_MASK) +#define RDC_TRIG_OUT1_CFG_LEAD_TIM_GET(x) (((uint32_t)(x) & RDC_TRIG_OUT1_CFG_LEAD_TIM_MASK) >> RDC_TRIG_OUT1_CFG_LEAD_TIM_SHIFT) + +/* Bitfield definition for register: PWM_DZ */ +/* + * DZ_N (RW) + * + * Exc_n dead zone in clock cycle before swap + * 0: no dead zone + * 1: 1 cycle dead zone + * 2: 2 cycle dead zone + * … + */ +#define RDC_PWM_DZ_DZ_N_MASK (0xFF00U) +#define RDC_PWM_DZ_DZ_N_SHIFT (8U) +#define RDC_PWM_DZ_DZ_N_SET(x) (((uint32_t)(x) << RDC_PWM_DZ_DZ_N_SHIFT) & RDC_PWM_DZ_DZ_N_MASK) +#define RDC_PWM_DZ_DZ_N_GET(x) (((uint32_t)(x) & RDC_PWM_DZ_DZ_N_MASK) >> RDC_PWM_DZ_DZ_N_SHIFT) + +/* + * DZ_P (RW) + * + * Exc_p dead zone in clock cycle before swap + * 0: no dead zone + * 1: 1 cycle dead zone + * 2: 2 cycle dead zone + * … + */ +#define RDC_PWM_DZ_DZ_P_MASK (0xFFU) +#define RDC_PWM_DZ_DZ_P_SHIFT (0U) +#define RDC_PWM_DZ_DZ_P_SET(x) (((uint32_t)(x) << RDC_PWM_DZ_DZ_P_SHIFT) & RDC_PWM_DZ_DZ_P_MASK) +#define RDC_PWM_DZ_DZ_P_GET(x) (((uint32_t)(x) & RDC_PWM_DZ_DZ_P_MASK) >> RDC_PWM_DZ_DZ_P_SHIFT) + +/* Bitfield definition for register: SYNC_OUT_CTRL */ +/* + * PWM_OUT_DLY (RO) + * + * Delay bettween the delyed trigger and the first pwm pulse in clock cycle + * 1: 1 cycle + * 2: 2 cycle + * … + */ +#define RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_MASK (0xFFFF0000UL) +#define RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_SHIFT (16U) +#define RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_GET(x) (((uint32_t)(x) & RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_MASK) >> RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_SHIFT) + +/* + * MIN2TRIG_EN (RW) + * + * Enable trigger out from the min point of exciting signal + * 1: enable + * 0: disable + */ +#define RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_MASK (0x20U) +#define RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_SHIFT (5U) +#define RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_SET(x) (((uint32_t)(x) << RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_SHIFT) & RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_MASK) +#define RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_GET(x) (((uint32_t)(x) & RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_MASK) >> RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_SHIFT) + +/* + * MAX2TRIG_EN (RW) + * + * Enable trigger out from the max point of exciting signal + * 1: enable + * 0: disable + */ +#define RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_MASK (0x10U) +#define RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_SHIFT (4U) +#define RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_SET(x) (((uint32_t)(x) << RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_SHIFT) & RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_MASK) +#define RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_GET(x) (((uint32_t)(x) & RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_MASK) >> RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_SHIFT) + +/* + * SYNC_OUT_SEL (RW) + * + * Select output synchornize signal + * 0: 0 phase of internal exciting signal + * 1: 90 phase of internal exciting signal + * 2: 180 phase of internal exciting signal + * 3: 270 phase of internal exciting signal + */ +#define RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_MASK (0x3U) +#define RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SHIFT (0U) +#define RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SET(x) (((uint32_t)(x) << RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SHIFT) & RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_MASK) +#define RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_GET(x) (((uint32_t)(x) & RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_MASK) >> RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SHIFT) + +/* Bitfield definition for register: EXC_SYNC_DLY */ +/* + * DISABLE (RW) + * + * Disable hardware trigger input + * 0: enable + * 1: disable + */ +#define RDC_EXC_SYNC_DLY_DISABLE_MASK (0x1000000UL) +#define RDC_EXC_SYNC_DLY_DISABLE_SHIFT (24U) +#define RDC_EXC_SYNC_DLY_DISABLE_SET(x) (((uint32_t)(x) << RDC_EXC_SYNC_DLY_DISABLE_SHIFT) & RDC_EXC_SYNC_DLY_DISABLE_MASK) +#define RDC_EXC_SYNC_DLY_DISABLE_GET(x) (((uint32_t)(x) & RDC_EXC_SYNC_DLY_DISABLE_MASK) >> RDC_EXC_SYNC_DLY_DISABLE_SHIFT) + +/* + * DELAY (RW) + * + * Trigger in delay timming in bus cycle from rising edge of trigger signal + * 0: 1 cycle + * 1: 2 cycle + * … + * 0xffffff: 2^24 cycle + */ +#define RDC_EXC_SYNC_DLY_DELAY_MASK (0xFFFFFFUL) +#define RDC_EXC_SYNC_DLY_DELAY_SHIFT (0U) +#define RDC_EXC_SYNC_DLY_DELAY_SET(x) (((uint32_t)(x) << RDC_EXC_SYNC_DLY_DELAY_SHIFT) & RDC_EXC_SYNC_DLY_DELAY_MASK) +#define RDC_EXC_SYNC_DLY_DELAY_GET(x) (((uint32_t)(x) & RDC_EXC_SYNC_DLY_DELAY_MASK) >> RDC_EXC_SYNC_DLY_DELAY_SHIFT) + +/* Bitfield definition for register: MAX_I */ +/* + * MAX (RWC) + * + * Max value of i_channel, write clear + */ +#define RDC_MAX_I_MAX_MASK (0xFFFFFF00UL) +#define RDC_MAX_I_MAX_SHIFT (8U) +#define RDC_MAX_I_MAX_SET(x) (((uint32_t)(x) << RDC_MAX_I_MAX_SHIFT) & RDC_MAX_I_MAX_MASK) +#define RDC_MAX_I_MAX_GET(x) (((uint32_t)(x) & RDC_MAX_I_MAX_MASK) >> RDC_MAX_I_MAX_SHIFT) + +/* + * VALID (RWC) + * + * Max value valid, write clear + * 0: max value is not valid + * 1: max value is valid + */ +#define RDC_MAX_I_VALID_MASK (0x1U) +#define RDC_MAX_I_VALID_SHIFT (0U) +#define RDC_MAX_I_VALID_SET(x) (((uint32_t)(x) << RDC_MAX_I_VALID_SHIFT) & RDC_MAX_I_VALID_MASK) +#define RDC_MAX_I_VALID_GET(x) (((uint32_t)(x) & RDC_MAX_I_VALID_MASK) >> RDC_MAX_I_VALID_SHIFT) + +/* Bitfield definition for register: MIN_I */ +/* + * MIN (RWC) + * + * Min value of i_channel, write clear + */ +#define RDC_MIN_I_MIN_MASK (0xFFFFFF00UL) +#define RDC_MIN_I_MIN_SHIFT (8U) +#define RDC_MIN_I_MIN_SET(x) (((uint32_t)(x) << RDC_MIN_I_MIN_SHIFT) & RDC_MIN_I_MIN_MASK) +#define RDC_MIN_I_MIN_GET(x) (((uint32_t)(x) & RDC_MIN_I_MIN_MASK) >> RDC_MIN_I_MIN_SHIFT) + +/* + * VALID (RWC) + * + * Min value valid, write clear + * 0: min value is not valid + * 1: min value is valid + */ +#define RDC_MIN_I_VALID_MASK (0x1U) +#define RDC_MIN_I_VALID_SHIFT (0U) +#define RDC_MIN_I_VALID_SET(x) (((uint32_t)(x) << RDC_MIN_I_VALID_SHIFT) & RDC_MIN_I_VALID_MASK) +#define RDC_MIN_I_VALID_GET(x) (((uint32_t)(x) & RDC_MIN_I_VALID_MASK) >> RDC_MIN_I_VALID_SHIFT) + +/* Bitfield definition for register: MAX_Q */ +/* + * MAX (RWC) + * + * Max value of q_channel, write clear + */ +#define RDC_MAX_Q_MAX_MASK (0xFFFFFF00UL) +#define RDC_MAX_Q_MAX_SHIFT (8U) +#define RDC_MAX_Q_MAX_SET(x) (((uint32_t)(x) << RDC_MAX_Q_MAX_SHIFT) & RDC_MAX_Q_MAX_MASK) +#define RDC_MAX_Q_MAX_GET(x) (((uint32_t)(x) & RDC_MAX_Q_MAX_MASK) >> RDC_MAX_Q_MAX_SHIFT) + +/* + * VALID (RWC) + * + * Max value valid, write clear + * 0: max value is not valid + * 1: max value is valid + */ +#define RDC_MAX_Q_VALID_MASK (0x1U) +#define RDC_MAX_Q_VALID_SHIFT (0U) +#define RDC_MAX_Q_VALID_SET(x) (((uint32_t)(x) << RDC_MAX_Q_VALID_SHIFT) & RDC_MAX_Q_VALID_MASK) +#define RDC_MAX_Q_VALID_GET(x) (((uint32_t)(x) & RDC_MAX_Q_VALID_MASK) >> RDC_MAX_Q_VALID_SHIFT) + +/* Bitfield definition for register: MIN_Q */ +/* + * MIN (RWC) + * + * Min value of q_channel, write clear + */ +#define RDC_MIN_Q_MIN_MASK (0xFFFFFF00UL) +#define RDC_MIN_Q_MIN_SHIFT (8U) +#define RDC_MIN_Q_MIN_SET(x) (((uint32_t)(x) << RDC_MIN_Q_MIN_SHIFT) & RDC_MIN_Q_MIN_MASK) +#define RDC_MIN_Q_MIN_GET(x) (((uint32_t)(x) & RDC_MIN_Q_MIN_MASK) >> RDC_MIN_Q_MIN_SHIFT) + +/* + * VALID (RWC) + * + * Min value valid, write clear + * 0: min value is not valid + * 1: min value is valid + */ +#define RDC_MIN_Q_VALID_MASK (0x1U) +#define RDC_MIN_Q_VALID_SHIFT (0U) +#define RDC_MIN_Q_VALID_SET(x) (((uint32_t)(x) << RDC_MIN_Q_VALID_SHIFT) & RDC_MIN_Q_VALID_MASK) +#define RDC_MIN_Q_VALID_GET(x) (((uint32_t)(x) & RDC_MIN_Q_VALID_MASK) >> RDC_MIN_Q_VALID_SHIFT) + +/* Bitfield definition for register: THRS_I */ +/* + * THRS (RW) + * + * The offset setting for edge detection of the i_channel, signed number + * … + * 2: the offset is 0x800000+2 + * 1: the offset is 0x800000+1 + * 0: the offset is 0x800000 + * -1: the offset is 0x800000-1 + * -2: the offset is 0x800000-2 + * … + */ +#define RDC_THRS_I_THRS_MASK (0xFFFFFF00UL) +#define RDC_THRS_I_THRS_SHIFT (8U) +#define RDC_THRS_I_THRS_SET(x) (((uint32_t)(x) << RDC_THRS_I_THRS_SHIFT) & RDC_THRS_I_THRS_MASK) +#define RDC_THRS_I_THRS_GET(x) (((uint32_t)(x) & RDC_THRS_I_THRS_MASK) >> RDC_THRS_I_THRS_SHIFT) + +/* Bitfield definition for register: THRS_Q */ +/* + * THRS (RW) + * + * The offset setting for edge detection of the q_channel, signed number + * … + * 2: the offset is 0x800000+2 + * 1: the offset is 0x800000+1 + * 0: the offset is 0x800000 + * -1: the offset is 0x800000-1 + * -2: the offset is 0x800000-2 + * … + */ +#define RDC_THRS_Q_THRS_MASK (0xFFFFFF00UL) +#define RDC_THRS_Q_THRS_SHIFT (8U) +#define RDC_THRS_Q_THRS_SET(x) (((uint32_t)(x) << RDC_THRS_Q_THRS_SHIFT) & RDC_THRS_Q_THRS_MASK) +#define RDC_THRS_Q_THRS_GET(x) (((uint32_t)(x) & RDC_THRS_Q_THRS_MASK) >> RDC_THRS_Q_THRS_SHIFT) + +/* Bitfield definition for register: EDG_DET_CTL */ +/* + * HOLD (RW) + * + * The minimum edge distance in sample + * 0:1 sample + * 1:2 sample + * 2:3 samples + * … + * 63:64 samples + */ +#define RDC_EDG_DET_CTL_HOLD_MASK (0x3F0U) +#define RDC_EDG_DET_CTL_HOLD_SHIFT (4U) +#define RDC_EDG_DET_CTL_HOLD_SET(x) (((uint32_t)(x) << RDC_EDG_DET_CTL_HOLD_SHIFT) & RDC_EDG_DET_CTL_HOLD_MASK) +#define RDC_EDG_DET_CTL_HOLD_GET(x) (((uint32_t)(x) & RDC_EDG_DET_CTL_HOLD_MASK) >> RDC_EDG_DET_CTL_HOLD_SHIFT) + +/* + * FILTER (RW) + * + * The continuous positive or negative number for edge detection + * 0: 1 + * 1: 2 + * … + * 7: 8 + */ +#define RDC_EDG_DET_CTL_FILTER_MASK (0x7U) +#define RDC_EDG_DET_CTL_FILTER_SHIFT (0U) +#define RDC_EDG_DET_CTL_FILTER_SET(x) (((uint32_t)(x) << RDC_EDG_DET_CTL_FILTER_SHIFT) & RDC_EDG_DET_CTL_FILTER_MASK) +#define RDC_EDG_DET_CTL_FILTER_GET(x) (((uint32_t)(x) & RDC_EDG_DET_CTL_FILTER_MASK) >> RDC_EDG_DET_CTL_FILTER_SHIFT) + +/* Bitfield definition for register: ACC_SCALING */ +/* + * TOXIC_LK (RW) + * + * Toxic accumulation data be removed control + * 1: enable + * 0: disable + */ +#define RDC_ACC_SCALING_TOXIC_LK_MASK (0x100U) +#define RDC_ACC_SCALING_TOXIC_LK_SHIFT (8U) +#define RDC_ACC_SCALING_TOXIC_LK_SET(x) (((uint32_t)(x) << RDC_ACC_SCALING_TOXIC_LK_SHIFT) & RDC_ACC_SCALING_TOXIC_LK_MASK) +#define RDC_ACC_SCALING_TOXIC_LK_GET(x) (((uint32_t)(x) & RDC_ACC_SCALING_TOXIC_LK_MASK) >> RDC_ACC_SCALING_TOXIC_LK_SHIFT) + +/* + * ACC_SHIFT (RW) + * + * Accumulation value shift control, this is a sign number. + * 0: {acc[39],acc[38:8]} + * 1: {acc[39],acc[37:7]} + * 2: {acc[39],acc[36:6]} + * … + * 7: {acc[39],acc[31:1]} + * 8: {acc[39],acc[30:0]} + * 9: acc/2^9 + * 10: acc/2^10 + * … + * 15:acc/2^15 + */ +#define RDC_ACC_SCALING_ACC_SHIFT_MASK (0xFU) +#define RDC_ACC_SCALING_ACC_SHIFT_SHIFT (0U) +#define RDC_ACC_SCALING_ACC_SHIFT_SET(x) (((uint32_t)(x) << RDC_ACC_SCALING_ACC_SHIFT_SHIFT) & RDC_ACC_SCALING_ACC_SHIFT_MASK) +#define RDC_ACC_SCALING_ACC_SHIFT_GET(x) (((uint32_t)(x) & RDC_ACC_SCALING_ACC_SHIFT_MASK) >> RDC_ACC_SCALING_ACC_SHIFT_SHIFT) + +/* Bitfield definition for register: EXC_PERIOD */ +/* + * EXC_PERIOD (RW) + * + * The num in clock cycle for period of excitation + * 0: invalid value + * 1:1 cycle + * 2:2 cycles + * … + */ +#define RDC_EXC_PERIOD_EXC_PERIOD_MASK (0xFFFFFFFFUL) +#define RDC_EXC_PERIOD_EXC_PERIOD_SHIFT (0U) +#define RDC_EXC_PERIOD_EXC_PERIOD_SET(x) (((uint32_t)(x) << RDC_EXC_PERIOD_EXC_PERIOD_SHIFT) & RDC_EXC_PERIOD_EXC_PERIOD_MASK) +#define RDC_EXC_PERIOD_EXC_PERIOD_GET(x) (((uint32_t)(x) & RDC_EXC_PERIOD_EXC_PERIOD_MASK) >> RDC_EXC_PERIOD_EXC_PERIOD_SHIFT) + +/* Bitfield definition for register: SYNC_DELAY_I */ +/* + * DELAY (RW) + * + * Delay in clock cycle for synchronous signal , the value shoud less than half of exc_period.exc_period. + * 0: invalid value + * 1: 1 cycles + * 2: 2 cycles + * ... + */ +#define RDC_SYNC_DELAY_I_DELAY_MASK (0xFFFFFFFFUL) +#define RDC_SYNC_DELAY_I_DELAY_SHIFT (0U) +#define RDC_SYNC_DELAY_I_DELAY_SET(x) (((uint32_t)(x) << RDC_SYNC_DELAY_I_DELAY_SHIFT) & RDC_SYNC_DELAY_I_DELAY_MASK) +#define RDC_SYNC_DELAY_I_DELAY_GET(x) (((uint32_t)(x) & RDC_SYNC_DELAY_I_DELAY_MASK) >> RDC_SYNC_DELAY_I_DELAY_SHIFT) + +/* Bitfield definition for register: RISE_DELAY_I */ +/* + * RISE_DELAY (RO) + * + * Delay value on rising edge of i_channel data + * 0: 1 cycle + * 1: 2 cycles + * … + */ +#define RDC_RISE_DELAY_I_RISE_DELAY_MASK (0xFFFFFFFFUL) +#define RDC_RISE_DELAY_I_RISE_DELAY_SHIFT (0U) +#define RDC_RISE_DELAY_I_RISE_DELAY_GET(x) (((uint32_t)(x) & RDC_RISE_DELAY_I_RISE_DELAY_MASK) >> RDC_RISE_DELAY_I_RISE_DELAY_SHIFT) + +/* Bitfield definition for register: FALL_DELAY_I */ +/* + * FALL_DELAY (RO) + * + * Delay value on falling edge of i_channel data + * 0: 1 cycle + * 1: 2 cycles + * … + */ +#define RDC_FALL_DELAY_I_FALL_DELAY_MASK (0xFFFFFFFFUL) +#define RDC_FALL_DELAY_I_FALL_DELAY_SHIFT (0U) +#define RDC_FALL_DELAY_I_FALL_DELAY_GET(x) (((uint32_t)(x) & RDC_FALL_DELAY_I_FALL_DELAY_MASK) >> RDC_FALL_DELAY_I_FALL_DELAY_SHIFT) + +/* Bitfield definition for register: SAMPLE_RISE_I */ +/* + * VALUE (RO) + * + * sample value on rising edge of rectify signal + */ +#define RDC_SAMPLE_RISE_I_VALUE_MASK (0xFFFFFF00UL) +#define RDC_SAMPLE_RISE_I_VALUE_SHIFT (8U) +#define RDC_SAMPLE_RISE_I_VALUE_GET(x) (((uint32_t)(x) & RDC_SAMPLE_RISE_I_VALUE_MASK) >> RDC_SAMPLE_RISE_I_VALUE_SHIFT) + +/* Bitfield definition for register: SAMPLE_FALL_I */ +/* + * VALUE (RO) + * + * sample value on falling edge of rectify signal + */ +#define RDC_SAMPLE_FALL_I_VALUE_MASK (0xFFFFFF00UL) +#define RDC_SAMPLE_FALL_I_VALUE_SHIFT (8U) +#define RDC_SAMPLE_FALL_I_VALUE_GET(x) (((uint32_t)(x) & RDC_SAMPLE_FALL_I_VALUE_MASK) >> RDC_SAMPLE_FALL_I_VALUE_SHIFT) + +/* Bitfield definition for register: ACC_CNT_I */ +/* + * CNT_NEG (RO) + * + * sample number during the negtive of rectify signal + * 1: 1 + * 2: 2 + * … + */ +#define RDC_ACC_CNT_I_CNT_NEG_MASK (0xFFFF0000UL) +#define RDC_ACC_CNT_I_CNT_NEG_SHIFT (16U) +#define RDC_ACC_CNT_I_CNT_NEG_GET(x) (((uint32_t)(x) & RDC_ACC_CNT_I_CNT_NEG_MASK) >> RDC_ACC_CNT_I_CNT_NEG_SHIFT) + +/* + * CNT_POS (RO) + * + * sample number during the positive of rectify signal + * 1: 1 + * 2: 2 + * … + */ +#define RDC_ACC_CNT_I_CNT_POS_MASK (0xFFFFU) +#define RDC_ACC_CNT_I_CNT_POS_SHIFT (0U) +#define RDC_ACC_CNT_I_CNT_POS_GET(x) (((uint32_t)(x) & RDC_ACC_CNT_I_CNT_POS_MASK) >> RDC_ACC_CNT_I_CNT_POS_SHIFT) + +/* Bitfield definition for register: SIGN_CNT_I */ +/* + * CNT_NEG (RO) + * + * Positive sample counter during negative rectify signal + */ +#define RDC_SIGN_CNT_I_CNT_NEG_MASK (0xFFFF0000UL) +#define RDC_SIGN_CNT_I_CNT_NEG_SHIFT (16U) +#define RDC_SIGN_CNT_I_CNT_NEG_GET(x) (((uint32_t)(x) & RDC_SIGN_CNT_I_CNT_NEG_MASK) >> RDC_SIGN_CNT_I_CNT_NEG_SHIFT) + +/* + * CNT_POS (RO) + * + * Negative sample counter during positive rectify signal + */ +#define RDC_SIGN_CNT_I_CNT_POS_MASK (0xFFFFU) +#define RDC_SIGN_CNT_I_CNT_POS_SHIFT (0U) +#define RDC_SIGN_CNT_I_CNT_POS_GET(x) (((uint32_t)(x) & RDC_SIGN_CNT_I_CNT_POS_MASK) >> RDC_SIGN_CNT_I_CNT_POS_SHIFT) + +/* Bitfield definition for register: SYNC_DELAY_Q */ +/* + * DELAY (RW) + * + * Delay in clock cycle for synchronous signal , the value shoud less than half of exc_period.exc_period. + * 0: invalid value + * 1: 1 cycles + * 2: 2 cycles + * ... + */ +#define RDC_SYNC_DELAY_Q_DELAY_MASK (0xFFFFFFFFUL) +#define RDC_SYNC_DELAY_Q_DELAY_SHIFT (0U) +#define RDC_SYNC_DELAY_Q_DELAY_SET(x) (((uint32_t)(x) << RDC_SYNC_DELAY_Q_DELAY_SHIFT) & RDC_SYNC_DELAY_Q_DELAY_MASK) +#define RDC_SYNC_DELAY_Q_DELAY_GET(x) (((uint32_t)(x) & RDC_SYNC_DELAY_Q_DELAY_MASK) >> RDC_SYNC_DELAY_Q_DELAY_SHIFT) + +/* Bitfield definition for register: RISE_DELAY_Q */ +/* + * RISE_DELAY (RO) + * + * Delay value on rising edge of q_channel data + * 0: 1 cycle + * 1: 2 cycles + * … + */ +#define RDC_RISE_DELAY_Q_RISE_DELAY_MASK (0xFFFFFFFFUL) +#define RDC_RISE_DELAY_Q_RISE_DELAY_SHIFT (0U) +#define RDC_RISE_DELAY_Q_RISE_DELAY_GET(x) (((uint32_t)(x) & RDC_RISE_DELAY_Q_RISE_DELAY_MASK) >> RDC_RISE_DELAY_Q_RISE_DELAY_SHIFT) + +/* Bitfield definition for register: FALL_DELAY_Q */ +/* + * FALL_DELAY (RO) + * + * Delay value on falling edge of q_channel data + * 0: 1 cycle + * 1: 2 cycles + * … + */ +#define RDC_FALL_DELAY_Q_FALL_DELAY_MASK (0xFFFFFFFFUL) +#define RDC_FALL_DELAY_Q_FALL_DELAY_SHIFT (0U) +#define RDC_FALL_DELAY_Q_FALL_DELAY_GET(x) (((uint32_t)(x) & RDC_FALL_DELAY_Q_FALL_DELAY_MASK) >> RDC_FALL_DELAY_Q_FALL_DELAY_SHIFT) + +/* Bitfield definition for register: SAMPLE_RISE_Q */ +/* + * VALUE (RO) + * + * sample value on rising edge of rectify signal + */ +#define RDC_SAMPLE_RISE_Q_VALUE_MASK (0xFFFFFF00UL) +#define RDC_SAMPLE_RISE_Q_VALUE_SHIFT (8U) +#define RDC_SAMPLE_RISE_Q_VALUE_GET(x) (((uint32_t)(x) & RDC_SAMPLE_RISE_Q_VALUE_MASK) >> RDC_SAMPLE_RISE_Q_VALUE_SHIFT) + +/* Bitfield definition for register: SAMPLE_FALL_Q */ +/* + * VALUE (RO) + * + * sample value on falling edge of rectify signal + */ +#define RDC_SAMPLE_FALL_Q_VALUE_MASK (0xFFFFFF00UL) +#define RDC_SAMPLE_FALL_Q_VALUE_SHIFT (8U) +#define RDC_SAMPLE_FALL_Q_VALUE_GET(x) (((uint32_t)(x) & RDC_SAMPLE_FALL_Q_VALUE_MASK) >> RDC_SAMPLE_FALL_Q_VALUE_SHIFT) + +/* Bitfield definition for register: ACC_CNT_Q */ +/* + * CNT_NEG (RO) + * + * sample number during the negtive of rectify signal + * 1: 1 + * 2: 2 + * … + */ +#define RDC_ACC_CNT_Q_CNT_NEG_MASK (0xFFFF0000UL) +#define RDC_ACC_CNT_Q_CNT_NEG_SHIFT (16U) +#define RDC_ACC_CNT_Q_CNT_NEG_GET(x) (((uint32_t)(x) & RDC_ACC_CNT_Q_CNT_NEG_MASK) >> RDC_ACC_CNT_Q_CNT_NEG_SHIFT) + +/* + * CNT_POS (RO) + * + * sample number during the positive of rectify signal + * 1: 1 + * 2: 2 + * … + */ +#define RDC_ACC_CNT_Q_CNT_POS_MASK (0xFFFFU) +#define RDC_ACC_CNT_Q_CNT_POS_SHIFT (0U) +#define RDC_ACC_CNT_Q_CNT_POS_GET(x) (((uint32_t)(x) & RDC_ACC_CNT_Q_CNT_POS_MASK) >> RDC_ACC_CNT_Q_CNT_POS_SHIFT) + +/* Bitfield definition for register: SIGN_CNT_Q */ +/* + * CNT_NEG (RO) + * + * Positive sample counter during negative rectify signal + */ +#define RDC_SIGN_CNT_Q_CNT_NEG_MASK (0xFFFF0000UL) +#define RDC_SIGN_CNT_Q_CNT_NEG_SHIFT (16U) +#define RDC_SIGN_CNT_Q_CNT_NEG_GET(x) (((uint32_t)(x) & RDC_SIGN_CNT_Q_CNT_NEG_MASK) >> RDC_SIGN_CNT_Q_CNT_NEG_SHIFT) + +/* + * CNT_POS (RO) + * + * Negative sample counter during positive rectify signal + */ +#define RDC_SIGN_CNT_Q_CNT_POS_MASK (0xFFFFU) +#define RDC_SIGN_CNT_Q_CNT_POS_SHIFT (0U) +#define RDC_SIGN_CNT_Q_CNT_POS_GET(x) (((uint32_t)(x) & RDC_SIGN_CNT_Q_CNT_POS_MASK) >> RDC_SIGN_CNT_Q_CNT_POS_SHIFT) + +/* Bitfield definition for register: AMP_MAX */ +/* + * MAX (RW) + * + * the maximum of acc amplitude + */ +#define RDC_AMP_MAX_MAX_MASK (0xFFFFFFFFUL) +#define RDC_AMP_MAX_MAX_SHIFT (0U) +#define RDC_AMP_MAX_MAX_SET(x) (((uint32_t)(x) << RDC_AMP_MAX_MAX_SHIFT) & RDC_AMP_MAX_MAX_MASK) +#define RDC_AMP_MAX_MAX_GET(x) (((uint32_t)(x) & RDC_AMP_MAX_MAX_MASK) >> RDC_AMP_MAX_MAX_SHIFT) + +/* Bitfield definition for register: AMP_MIN */ +/* + * MIN (RW) + * + * the minimum of acc amplitude + */ +#define RDC_AMP_MIN_MIN_MASK (0xFFFFFFFFUL) +#define RDC_AMP_MIN_MIN_SHIFT (0U) +#define RDC_AMP_MIN_MIN_SET(x) (((uint32_t)(x) << RDC_AMP_MIN_MIN_SHIFT) & RDC_AMP_MIN_MIN_MASK) +#define RDC_AMP_MIN_MIN_GET(x) (((uint32_t)(x) & RDC_AMP_MIN_MIN_MASK) >> RDC_AMP_MIN_MIN_SHIFT) + +/* Bitfield definition for register: INT_EN */ +/* + * INT_EN (RW) + * + * enable interrupt output + */ +#define RDC_INT_EN_INT_EN_MASK (0x80000000UL) +#define RDC_INT_EN_INT_EN_SHIFT (31U) +#define RDC_INT_EN_INT_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_INT_EN_SHIFT) & RDC_INT_EN_INT_EN_MASK) +#define RDC_INT_EN_INT_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_INT_EN_MASK) >> RDC_INT_EN_INT_EN_SHIFT) + +/* + * ACC_VLD_I_EN (RW) + * + * i_channel accumulate valid interrupt enable for i_channel + */ +#define RDC_INT_EN_ACC_VLD_I_EN_MASK (0x8000U) +#define RDC_INT_EN_ACC_VLD_I_EN_SHIFT (15U) +#define RDC_INT_EN_ACC_VLD_I_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_I_EN_SHIFT) & RDC_INT_EN_ACC_VLD_I_EN_MASK) +#define RDC_INT_EN_ACC_VLD_I_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_I_EN_MASK) >> RDC_INT_EN_ACC_VLD_I_EN_SHIFT) + +/* + * ACC_VLD_Q_EN (RW) + * + * q_channel accumulate valid interrupt enable for i_channel + */ +#define RDC_INT_EN_ACC_VLD_Q_EN_MASK (0x4000U) +#define RDC_INT_EN_ACC_VLD_Q_EN_SHIFT (14U) +#define RDC_INT_EN_ACC_VLD_Q_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_Q_EN_SHIFT) & RDC_INT_EN_ACC_VLD_Q_EN_MASK) +#define RDC_INT_EN_ACC_VLD_Q_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_Q_EN_MASK) >> RDC_INT_EN_ACC_VLD_Q_EN_SHIFT) + +/* + * RISING_DELAY_I_EN (RW) + * + * i_channel delayed rectify signal rising edge interrupt enable + */ +#define RDC_INT_EN_RISING_DELAY_I_EN_MASK (0x2000U) +#define RDC_INT_EN_RISING_DELAY_I_EN_SHIFT (13U) +#define RDC_INT_EN_RISING_DELAY_I_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_RISING_DELAY_I_EN_SHIFT) & RDC_INT_EN_RISING_DELAY_I_EN_MASK) +#define RDC_INT_EN_RISING_DELAY_I_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_RISING_DELAY_I_EN_MASK) >> RDC_INT_EN_RISING_DELAY_I_EN_SHIFT) + +/* + * FALLING_DELAY_I_EN (RW) + * + * i_channel delayed rectify signal falling edge interrupt enable + */ +#define RDC_INT_EN_FALLING_DELAY_I_EN_MASK (0x1000U) +#define RDC_INT_EN_FALLING_DELAY_I_EN_SHIFT (12U) +#define RDC_INT_EN_FALLING_DELAY_I_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_FALLING_DELAY_I_EN_SHIFT) & RDC_INT_EN_FALLING_DELAY_I_EN_MASK) +#define RDC_INT_EN_FALLING_DELAY_I_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_FALLING_DELAY_I_EN_MASK) >> RDC_INT_EN_FALLING_DELAY_I_EN_SHIFT) + +/* + * RISING_DELAY_Q_EN (RW) + * + * q_channel delayed rectify signal rising edge interrupt enable + */ +#define RDC_INT_EN_RISING_DELAY_Q_EN_MASK (0x800U) +#define RDC_INT_EN_RISING_DELAY_Q_EN_SHIFT (11U) +#define RDC_INT_EN_RISING_DELAY_Q_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_RISING_DELAY_Q_EN_SHIFT) & RDC_INT_EN_RISING_DELAY_Q_EN_MASK) +#define RDC_INT_EN_RISING_DELAY_Q_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_RISING_DELAY_Q_EN_MASK) >> RDC_INT_EN_RISING_DELAY_Q_EN_SHIFT) + +/* + * FALLING_DELAY_Q_EN (RW) + * + * q_channel delayed rectify signal falling edge interrupt enable + */ +#define RDC_INT_EN_FALLING_DELAY_Q_EN_MASK (0x400U) +#define RDC_INT_EN_FALLING_DELAY_Q_EN_SHIFT (10U) +#define RDC_INT_EN_FALLING_DELAY_Q_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_FALLING_DELAY_Q_EN_SHIFT) & RDC_INT_EN_FALLING_DELAY_Q_EN_MASK) +#define RDC_INT_EN_FALLING_DELAY_Q_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_FALLING_DELAY_Q_EN_MASK) >> RDC_INT_EN_FALLING_DELAY_Q_EN_SHIFT) + +/* + * SAMPLE_RISING_I_EN (RW) + * + * i_channel rising edge interrupt enable + */ +#define RDC_INT_EN_SAMPLE_RISING_I_EN_MASK (0x200U) +#define RDC_INT_EN_SAMPLE_RISING_I_EN_SHIFT (9U) +#define RDC_INT_EN_SAMPLE_RISING_I_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_SAMPLE_RISING_I_EN_SHIFT) & RDC_INT_EN_SAMPLE_RISING_I_EN_MASK) +#define RDC_INT_EN_SAMPLE_RISING_I_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_SAMPLE_RISING_I_EN_MASK) >> RDC_INT_EN_SAMPLE_RISING_I_EN_SHIFT) + +/* + * SAMPLE_FALLING_I_EN (RW) + * + * i_channel falling edge interrupt enable + */ +#define RDC_INT_EN_SAMPLE_FALLING_I_EN_MASK (0x100U) +#define RDC_INT_EN_SAMPLE_FALLING_I_EN_SHIFT (8U) +#define RDC_INT_EN_SAMPLE_FALLING_I_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_SAMPLE_FALLING_I_EN_SHIFT) & RDC_INT_EN_SAMPLE_FALLING_I_EN_MASK) +#define RDC_INT_EN_SAMPLE_FALLING_I_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_SAMPLE_FALLING_I_EN_MASK) >> RDC_INT_EN_SAMPLE_FALLING_I_EN_SHIFT) + +/* + * SAMPLE_RISING_Q_EN (RW) + * + * q_channel rising edge interrupt enable + */ +#define RDC_INT_EN_SAMPLE_RISING_Q_EN_MASK (0x80U) +#define RDC_INT_EN_SAMPLE_RISING_Q_EN_SHIFT (7U) +#define RDC_INT_EN_SAMPLE_RISING_Q_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_SAMPLE_RISING_Q_EN_SHIFT) & RDC_INT_EN_SAMPLE_RISING_Q_EN_MASK) +#define RDC_INT_EN_SAMPLE_RISING_Q_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_SAMPLE_RISING_Q_EN_MASK) >> RDC_INT_EN_SAMPLE_RISING_Q_EN_SHIFT) + +/* + * SAMPLE_FALLING_Q_EN (RW) + * + * q_channel falling edge interrupt enable + */ +#define RDC_INT_EN_SAMPLE_FALLING_Q_EN_MASK (0x40U) +#define RDC_INT_EN_SAMPLE_FALLING_Q_EN_SHIFT (6U) +#define RDC_INT_EN_SAMPLE_FALLING_Q_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_SAMPLE_FALLING_Q_EN_SHIFT) & RDC_INT_EN_SAMPLE_FALLING_Q_EN_MASK) +#define RDC_INT_EN_SAMPLE_FALLING_Q_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_SAMPLE_FALLING_Q_EN_MASK) >> RDC_INT_EN_SAMPLE_FALLING_Q_EN_SHIFT) + +/* + * ACC_VLD_I_OVH_EN (RW) + * + * i_channel accumulate overflow interrupt enable + */ +#define RDC_INT_EN_ACC_VLD_I_OVH_EN_MASK (0x20U) +#define RDC_INT_EN_ACC_VLD_I_OVH_EN_SHIFT (5U) +#define RDC_INT_EN_ACC_VLD_I_OVH_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_I_OVH_EN_SHIFT) & RDC_INT_EN_ACC_VLD_I_OVH_EN_MASK) +#define RDC_INT_EN_ACC_VLD_I_OVH_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_I_OVH_EN_MASK) >> RDC_INT_EN_ACC_VLD_I_OVH_EN_SHIFT) + +/* + * ACC_VLD_Q_OVH_EN (RW) + * + * q_channel accumulate overflow interrupt enable + */ +#define RDC_INT_EN_ACC_VLD_Q_OVH_EN_MASK (0x10U) +#define RDC_INT_EN_ACC_VLD_Q_OVH_EN_SHIFT (4U) +#define RDC_INT_EN_ACC_VLD_Q_OVH_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_Q_OVH_EN_SHIFT) & RDC_INT_EN_ACC_VLD_Q_OVH_EN_MASK) +#define RDC_INT_EN_ACC_VLD_Q_OVH_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_Q_OVH_EN_MASK) >> RDC_INT_EN_ACC_VLD_Q_OVH_EN_SHIFT) + +/* + * ACC_VLD_I_OVL_EN (RW) + * + * i_channel accumulate underflow interrupt enable + */ +#define RDC_INT_EN_ACC_VLD_I_OVL_EN_MASK (0x8U) +#define RDC_INT_EN_ACC_VLD_I_OVL_EN_SHIFT (3U) +#define RDC_INT_EN_ACC_VLD_I_OVL_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_I_OVL_EN_SHIFT) & RDC_INT_EN_ACC_VLD_I_OVL_EN_MASK) +#define RDC_INT_EN_ACC_VLD_I_OVL_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_I_OVL_EN_MASK) >> RDC_INT_EN_ACC_VLD_I_OVL_EN_SHIFT) + +/* + * ACC_VLD_Q_OVL_EN (RW) + * + * q_channel accumulate underflow interrupt enable + */ +#define RDC_INT_EN_ACC_VLD_Q_OVL_EN_MASK (0x4U) +#define RDC_INT_EN_ACC_VLD_Q_OVL_EN_SHIFT (2U) +#define RDC_INT_EN_ACC_VLD_Q_OVL_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_Q_OVL_EN_SHIFT) & RDC_INT_EN_ACC_VLD_Q_OVL_EN_MASK) +#define RDC_INT_EN_ACC_VLD_Q_OVL_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_Q_OVL_EN_MASK) >> RDC_INT_EN_ACC_VLD_Q_OVL_EN_SHIFT) + +/* + * ACC_AMP_OVH_EN (RW) + * + * accumulate ample overflow interrupt enable + */ +#define RDC_INT_EN_ACC_AMP_OVH_EN_MASK (0x2U) +#define RDC_INT_EN_ACC_AMP_OVH_EN_SHIFT (1U) +#define RDC_INT_EN_ACC_AMP_OVH_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_AMP_OVH_EN_SHIFT) & RDC_INT_EN_ACC_AMP_OVH_EN_MASK) +#define RDC_INT_EN_ACC_AMP_OVH_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_AMP_OVH_EN_MASK) >> RDC_INT_EN_ACC_AMP_OVH_EN_SHIFT) + +/* + * ACC_AMP_OVL_EN (RW) + * + * accumulate ample underflow interrupt enable + */ +#define RDC_INT_EN_ACC_AMP_OVL_EN_MASK (0x1U) +#define RDC_INT_EN_ACC_AMP_OVL_EN_SHIFT (0U) +#define RDC_INT_EN_ACC_AMP_OVL_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_AMP_OVL_EN_SHIFT) & RDC_INT_EN_ACC_AMP_OVL_EN_MASK) +#define RDC_INT_EN_ACC_AMP_OVL_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_AMP_OVL_EN_MASK) >> RDC_INT_EN_ACC_AMP_OVL_EN_SHIFT) + +/* Bitfield definition for register: ADC_INT_STATE */ +/* + * ACC_VLD_I_STA (W1C) + * + * i_channel accumulate valid interrupt status for i_channel + */ +#define RDC_ADC_INT_STATE_ACC_VLD_I_STA_MASK (0x8000U) +#define RDC_ADC_INT_STATE_ACC_VLD_I_STA_SHIFT (15U) +#define RDC_ADC_INT_STATE_ACC_VLD_I_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_I_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_I_STA_MASK) +#define RDC_ADC_INT_STATE_ACC_VLD_I_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_I_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_I_STA_SHIFT) + +/* + * ACC_VLD_Q_STA (W1C) + * + * q_channel accumulate valid interrupt status for i_channel + */ +#define RDC_ADC_INT_STATE_ACC_VLD_Q_STA_MASK (0x4000U) +#define RDC_ADC_INT_STATE_ACC_VLD_Q_STA_SHIFT (14U) +#define RDC_ADC_INT_STATE_ACC_VLD_Q_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_Q_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_Q_STA_MASK) +#define RDC_ADC_INT_STATE_ACC_VLD_Q_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_Q_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_Q_STA_SHIFT) + +/* + * RISING_DELAY_I_STA (W1C) + * + * i_channel delayed rectify signal rising edge interrupt status + */ +#define RDC_ADC_INT_STATE_RISING_DELAY_I_STA_MASK (0x2000U) +#define RDC_ADC_INT_STATE_RISING_DELAY_I_STA_SHIFT (13U) +#define RDC_ADC_INT_STATE_RISING_DELAY_I_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_RISING_DELAY_I_STA_SHIFT) & RDC_ADC_INT_STATE_RISING_DELAY_I_STA_MASK) +#define RDC_ADC_INT_STATE_RISING_DELAY_I_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_RISING_DELAY_I_STA_MASK) >> RDC_ADC_INT_STATE_RISING_DELAY_I_STA_SHIFT) + +/* + * FALLING_DELAY_I_STA (W1C) + * + * i_channel delayed rectify signal falling edge interrupt status + */ +#define RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_MASK (0x1000U) +#define RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_SHIFT (12U) +#define RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_SHIFT) & RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_MASK) +#define RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_MASK) >> RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_SHIFT) + +/* + * RISING_DELAY_Q_STA (W1C) + * + * q_channel delayed rectify signal rising edge interrupt status + */ +#define RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_MASK (0x800U) +#define RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_SHIFT (11U) +#define RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_SHIFT) & RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_MASK) +#define RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_MASK) >> RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_SHIFT) + +/* + * FALLING_DELAY_Q_STA (W1C) + * + * q_channel delayed rectify signal falling edge interrupt status + */ +#define RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_MASK (0x400U) +#define RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_SHIFT (10U) +#define RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_SHIFT) & RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_MASK) +#define RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_MASK) >> RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_SHIFT) + +/* + * SAMPLE_RISING_I_STA (W1C) + * + * i_channel rising edge interrupt status + */ +#define RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_MASK (0x200U) +#define RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_SHIFT (9U) +#define RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_SHIFT) & RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_MASK) +#define RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_MASK) >> RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_SHIFT) + +/* + * SAMPLE_FALLING_I_STA (W1C) + * + * i_channel falling edge interrupt status + */ +#define RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_MASK (0x100U) +#define RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_SHIFT (8U) +#define RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_SHIFT) & RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_MASK) +#define RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_MASK) >> RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_SHIFT) + +/* + * SAMPLE_RISING_Q_STA (W1C) + * + * q_channel rising edge interrupt status + */ +#define RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_MASK (0x80U) +#define RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_SHIFT (7U) +#define RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_SHIFT) & RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_MASK) +#define RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_MASK) >> RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_SHIFT) + +/* + * SAMPLE_FALLING_Q_STA (W1C) + * + * q_channel falling edge interrupt status + */ +#define RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_MASK (0x40U) +#define RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_SHIFT (6U) +#define RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_SHIFT) & RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_MASK) +#define RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_MASK) >> RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_SHIFT) + +/* + * ACC_VLD_I_OVH_STA (W1C) + * + * i_channel accumulate overflow interrupt status + */ +#define RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_MASK (0x20U) +#define RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_SHIFT (5U) +#define RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_MASK) +#define RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_SHIFT) + +/* + * ACC_VLD_Q_OVH_STA (W1C) + * + * q_channel accumulate overflow interrupt status + */ +#define RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_MASK (0x10U) +#define RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_SHIFT (4U) +#define RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_MASK) +#define RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_SHIFT) + +/* + * ACC_VLD_I_OVL_STA (W1C) + * + * i_channel accumulate underflow interrupt status + */ +#define RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_MASK (0x8U) +#define RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_SHIFT (3U) +#define RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_MASK) +#define RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_SHIFT) + +/* + * ACC_VLD_Q_OVL_STA (W1C) + * + * q_channel accumulate underflow interrupt status + */ +#define RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_MASK (0x4U) +#define RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_SHIFT (2U) +#define RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_MASK) +#define RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_SHIFT) + +/* + * ACC_AMP_OVH_STA (W1C) + * + * accumulate ample overflow interrupt status + */ +#define RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_MASK (0x2U) +#define RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_SHIFT (1U) +#define RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_MASK) +#define RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_MASK) >> RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_SHIFT) + +/* + * ACC_AMP_OVL_STA (W1C) + * + * accumulate ample underflow interrupt status + */ +#define RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_MASK (0x1U) +#define RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_SHIFT (0U) +#define RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_MASK) +#define RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_MASK) >> RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_SHIFT) + + + + +#endif /* HPM_RDC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sdadc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sdadc_regs.h new file mode 100644 index 00000000000..f855f124034 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sdadc_regs.h @@ -0,0 +1,238 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_SDADC_H +#define HPM_SDADC_H + +typedef struct { + __RW uint32_t CTRL; /* 0x0: SDADC control register */ + __RW uint32_t CLK_DIV; /* 0x4: clock divider */ + __RW uint32_t TTB; /* 0x8: Total Transfer Bits */ + __RW uint32_t START_OP; /* 0xC: Start_Of_Operation */ + __RW uint32_t MISC; /* 0x10: Misc Control */ + __R uint32_t ST; /* 0x14: Status Register */ +} SDADC_Type; + + +/* Bitfield definition for register: CTRL */ +/* + * SDM_CFG (RW) + * + * SDM analog part Configuration + */ +#define SDADC_CTRL_SDM_CFG_MASK (0xFF00000UL) +#define SDADC_CTRL_SDM_CFG_SHIFT (20U) +#define SDADC_CTRL_SDM_CFG_SET(x) (((uint32_t)(x) << SDADC_CTRL_SDM_CFG_SHIFT) & SDADC_CTRL_SDM_CFG_MASK) +#define SDADC_CTRL_SDM_CFG_GET(x) (((uint32_t)(x) & SDADC_CTRL_SDM_CFG_MASK) >> SDADC_CTRL_SDM_CFG_SHIFT) + +/* + * SDM_PGA_CE_SEL (RW) + * + * SDM_PGA_CE_SEL + */ +#define SDADC_CTRL_SDM_PGA_CE_SEL_MASK (0xC0000UL) +#define SDADC_CTRL_SDM_PGA_CE_SEL_SHIFT (18U) +#define SDADC_CTRL_SDM_PGA_CE_SEL_SET(x) (((uint32_t)(x) << SDADC_CTRL_SDM_PGA_CE_SEL_SHIFT) & SDADC_CTRL_SDM_PGA_CE_SEL_MASK) +#define SDADC_CTRL_SDM_PGA_CE_SEL_GET(x) (((uint32_t)(x) & SDADC_CTRL_SDM_PGA_CE_SEL_MASK) >> SDADC_CTRL_SDM_PGA_CE_SEL_SHIFT) + +/* + * SDM_PGA_CH_SEL (RW) + * + * SDM_PGA_CH_SEL + */ +#define SDADC_CTRL_SDM_PGA_CH_SEL_MASK (0x3C000UL) +#define SDADC_CTRL_SDM_PGA_CH_SEL_SHIFT (14U) +#define SDADC_CTRL_SDM_PGA_CH_SEL_SET(x) (((uint32_t)(x) << SDADC_CTRL_SDM_PGA_CH_SEL_SHIFT) & SDADC_CTRL_SDM_PGA_CH_SEL_MASK) +#define SDADC_CTRL_SDM_PGA_CH_SEL_GET(x) (((uint32_t)(x) & SDADC_CTRL_SDM_PGA_CH_SEL_MASK) >> SDADC_CTRL_SDM_PGA_CH_SEL_SHIFT) + +/* + * CFG_CDS_CMD (RW) + * + * config the common mode voltage of CDS CAP + */ +#define SDADC_CTRL_CFG_CDS_CMD_MASK (0x2000U) +#define SDADC_CTRL_CFG_CDS_CMD_SHIFT (13U) +#define SDADC_CTRL_CFG_CDS_CMD_SET(x) (((uint32_t)(x) << SDADC_CTRL_CFG_CDS_CMD_SHIFT) & SDADC_CTRL_CFG_CDS_CMD_MASK) +#define SDADC_CTRL_CFG_CDS_CMD_GET(x) (((uint32_t)(x) & SDADC_CTRL_CFG_CDS_CMD_MASK) >> SDADC_CTRL_CFG_CDS_CMD_SHIFT) + +/* + * LP_MODE_SDM (RW) + * + * lowpower mode of SDM + */ +#define SDADC_CTRL_LP_MODE_SDM_MASK (0xE00U) +#define SDADC_CTRL_LP_MODE_SDM_SHIFT (9U) +#define SDADC_CTRL_LP_MODE_SDM_SET(x) (((uint32_t)(x) << SDADC_CTRL_LP_MODE_SDM_SHIFT) & SDADC_CTRL_LP_MODE_SDM_MASK) +#define SDADC_CTRL_LP_MODE_SDM_GET(x) (((uint32_t)(x) & SDADC_CTRL_LP_MODE_SDM_MASK) >> SDADC_CTRL_LP_MODE_SDM_SHIFT) + +/* + * LP_MODE_PGA (RW) + * + * lowpower mode of PGA + */ +#define SDADC_CTRL_LP_MODE_PGA_MASK (0x1C0U) +#define SDADC_CTRL_LP_MODE_PGA_SHIFT (6U) +#define SDADC_CTRL_LP_MODE_PGA_SET(x) (((uint32_t)(x) << SDADC_CTRL_LP_MODE_PGA_SHIFT) & SDADC_CTRL_LP_MODE_PGA_MASK) +#define SDADC_CTRL_LP_MODE_PGA_GET(x) (((uint32_t)(x) & SDADC_CTRL_LP_MODE_PGA_MASK) >> SDADC_CTRL_LP_MODE_PGA_SHIFT) + +/* + * ANA_PWUP (RW) + * + * 1. Asserted to power up the analog part + * 0: Shut off the power for the analog part + */ +#define SDADC_CTRL_ANA_PWUP_MASK (0x20U) +#define SDADC_CTRL_ANA_PWUP_SHIFT (5U) +#define SDADC_CTRL_ANA_PWUP_SET(x) (((uint32_t)(x) << SDADC_CTRL_ANA_PWUP_SHIFT) & SDADC_CTRL_ANA_PWUP_MASK) +#define SDADC_CTRL_ANA_PWUP_GET(x) (((uint32_t)(x) & SDADC_CTRL_ANA_PWUP_MASK) >> SDADC_CTRL_ANA_PWUP_SHIFT) + +/* + * BYPASS_PGA (RW) + * + * 1: PGA is bypassed + * 0: PGA is enabled + */ +#define SDADC_CTRL_BYPASS_PGA_MASK (0x10U) +#define SDADC_CTRL_BYPASS_PGA_SHIFT (4U) +#define SDADC_CTRL_BYPASS_PGA_SET(x) (((uint32_t)(x) << SDADC_CTRL_BYPASS_PGA_SHIFT) & SDADC_CTRL_BYPASS_PGA_MASK) +#define SDADC_CTRL_BYPASS_PGA_GET(x) (((uint32_t)(x) & SDADC_CTRL_BYPASS_PGA_MASK) >> SDADC_CTRL_BYPASS_PGA_SHIFT) + +/* + * CONT_MODE (RW) + * + * 1: continuous mode of ADC conversion + * 0: burst mode of ADC conversion. + */ +#define SDADC_CTRL_CONT_MODE_MASK (0x8U) +#define SDADC_CTRL_CONT_MODE_SHIFT (3U) +#define SDADC_CTRL_CONT_MODE_SET(x) (((uint32_t)(x) << SDADC_CTRL_CONT_MODE_SHIFT) & SDADC_CTRL_CONT_MODE_MASK) +#define SDADC_CTRL_CONT_MODE_GET(x) (((uint32_t)(x) & SDADC_CTRL_CONT_MODE_MASK) >> SDADC_CTRL_CONT_MODE_SHIFT) + +/* + * RST_SDM (RW) + * + * 1: reset SDM. Should be de-asserted by software + * 0: no reset SDM + */ +#define SDADC_CTRL_RST_SDM_MASK (0x4U) +#define SDADC_CTRL_RST_SDM_SHIFT (2U) +#define SDADC_CTRL_RST_SDM_SET(x) (((uint32_t)(x) << SDADC_CTRL_RST_SDM_SHIFT) & SDADC_CTRL_RST_SDM_MASK) +#define SDADC_CTRL_RST_SDM_GET(x) (((uint32_t)(x) & SDADC_CTRL_RST_SDM_MASK) >> SDADC_CTRL_RST_SDM_SHIFT) + +/* + * RST_PGA (RW) + * + * 1: reset PGA. Should be de-asserted by software + * 0: no reset PGA + */ +#define SDADC_CTRL_RST_PGA_MASK (0x2U) +#define SDADC_CTRL_RST_PGA_SHIFT (1U) +#define SDADC_CTRL_RST_PGA_SET(x) (((uint32_t)(x) << SDADC_CTRL_RST_PGA_SHIFT) & SDADC_CTRL_RST_PGA_MASK) +#define SDADC_CTRL_RST_PGA_GET(x) (((uint32_t)(x) & SDADC_CTRL_RST_PGA_MASK) >> SDADC_CTRL_RST_PGA_SHIFT) + +/* + * EN (RW) + * + * Module enable, to enable clok divder. Etc + */ +#define SDADC_CTRL_EN_MASK (0x1U) +#define SDADC_CTRL_EN_SHIFT (0U) +#define SDADC_CTRL_EN_SET(x) (((uint32_t)(x) << SDADC_CTRL_EN_SHIFT) & SDADC_CTRL_EN_MASK) +#define SDADC_CTRL_EN_GET(x) (((uint32_t)(x) & SDADC_CTRL_EN_MASK) >> SDADC_CTRL_EN_SHIFT) + +/* Bitfield definition for register: CLK_DIV */ +/* + * FACTOR (RW) + * + * 0: disable clock output + * 1: bypass the clock divider + * 2: divide the clock by 2 + * … + * n: divide the clock by n + */ +#define SDADC_CLK_DIV_FACTOR_MASK (0xFFU) +#define SDADC_CLK_DIV_FACTOR_SHIFT (0U) +#define SDADC_CLK_DIV_FACTOR_SET(x) (((uint32_t)(x) << SDADC_CLK_DIV_FACTOR_SHIFT) & SDADC_CLK_DIV_FACTOR_MASK) +#define SDADC_CLK_DIV_FACTOR_GET(x) (((uint32_t)(x) & SDADC_CLK_DIV_FACTOR_MASK) >> SDADC_CLK_DIV_FACTOR_SHIFT) + +/* Bitfield definition for register: TTB */ +/* + * VAL (RW) + * + * the maximal number of output bits when ADC is in burst mode + */ +#define SDADC_TTB_VAL_MASK (0xFFFFFUL) +#define SDADC_TTB_VAL_SHIFT (0U) +#define SDADC_TTB_VAL_SET(x) (((uint32_t)(x) << SDADC_TTB_VAL_SHIFT) & SDADC_TTB_VAL_MASK) +#define SDADC_TTB_VAL_GET(x) (((uint32_t)(x) & SDADC_TTB_VAL_MASK) >> SDADC_TTB_VAL_SHIFT) + +/* Bitfield definition for register: START_OP */ +/* + * SDM_EN (RW) + * + * 1. Enable sigma-delta ADC. Auto clear in burst mode when TTB bits are received. In cont mode, must be cleared manually. + * 0: disable sigma-delta ADC + */ +#define SDADC_START_OP_SDM_EN_MASK (0x1U) +#define SDADC_START_OP_SDM_EN_SHIFT (0U) +#define SDADC_START_OP_SDM_EN_SET(x) (((uint32_t)(x) << SDADC_START_OP_SDM_EN_SHIFT) & SDADC_START_OP_SDM_EN_MASK) +#define SDADC_START_OP_SDM_EN_GET(x) (((uint32_t)(x) & SDADC_START_OP_SDM_EN_MASK) >> SDADC_START_OP_SDM_EN_SHIFT) + +/* Bitfield definition for register: MISC */ +/* + * BURST_DONE_IE (RW) + * + * Asserted to enable BURST_DONE event interrupt. Should not be asserted for continuous mode. + */ +#define SDADC_MISC_BURST_DONE_IE_MASK (0x2U) +#define SDADC_MISC_BURST_DONE_IE_SHIFT (1U) +#define SDADC_MISC_BURST_DONE_IE_SET(x) (((uint32_t)(x) << SDADC_MISC_BURST_DONE_IE_SHIFT) & SDADC_MISC_BURST_DONE_IE_MASK) +#define SDADC_MISC_BURST_DONE_IE_GET(x) (((uint32_t)(x) & SDADC_MISC_BURST_DONE_IE_MASK) >> SDADC_MISC_BURST_DONE_IE_SHIFT) + +/* + * PDM_CLK_SEL (RW) + * + * Asserted to use PDM clk input. Default to use MCLK which is directly from PLL. + */ +#define SDADC_MISC_PDM_CLK_SEL_MASK (0x1U) +#define SDADC_MISC_PDM_CLK_SEL_SHIFT (0U) +#define SDADC_MISC_PDM_CLK_SEL_SET(x) (((uint32_t)(x) << SDADC_MISC_PDM_CLK_SEL_SHIFT) & SDADC_MISC_PDM_CLK_SEL_MASK) +#define SDADC_MISC_PDM_CLK_SEL_GET(x) (((uint32_t)(x) & SDADC_MISC_PDM_CLK_SEL_MASK) >> SDADC_MISC_PDM_CLK_SEL_SHIFT) + +/* Bitfield definition for register: ST */ +/* + * ANA_RST (RO) + * + * Asserted when analog module is in reset mode. + */ +#define SDADC_ST_ANA_RST_MASK (0x4U) +#define SDADC_ST_ANA_RST_SHIFT (2U) +#define SDADC_ST_ANA_RST_GET(x) (((uint32_t)(x) & SDADC_ST_ANA_RST_MASK) >> SDADC_ST_ANA_RST_SHIFT) + +/* + * DIV_STABLE (RO) + * + * Asserted when CLK_DIV reaches stable status. Cleared automatically when CLK_DIV[FACTOR] is assigned a different value. + */ +#define SDADC_ST_DIV_STABLE_MASK (0x2U) +#define SDADC_ST_DIV_STABLE_SHIFT (1U) +#define SDADC_ST_DIV_STABLE_GET(x) (((uint32_t)(x) & SDADC_ST_DIV_STABLE_MASK) >> SDADC_ST_DIV_STABLE_SHIFT) + +/* + * BURST_DONE (RO) + * + * Asserted when burst transfer is done. Auto cleared after the ST register is read while this bit is asserted. + */ +#define SDADC_ST_BURST_DONE_MASK (0x1U) +#define SDADC_ST_BURST_DONE_SHIFT (0U) +#define SDADC_ST_BURST_DONE_GET(x) (((uint32_t)(x) & SDADC_ST_BURST_DONE_MASK) >> SDADC_ST_BURST_DONE_SHIFT) + + + + +#endif /* HPM_SDADC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sdmv2_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sdmv2_regs.h new file mode 100644 index 00000000000..d5ab6d236e7 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sdmv2_regs.h @@ -0,0 +1,692 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_SDMV2_H +#define HPM_SDMV2_H + +typedef struct { + __RW uint32_t CTRL; /* 0x0: SDM control register */ + __RW uint32_t INT_EN; /* 0x4: Interrupt enable register. */ + __R uint32_t STATUS; /* 0x8: Status Registers */ + __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ + struct { + __RW uint32_t SDFIFOCTRL; /* 0x10: Data FIFO Path Control Register */ + __RW uint32_t SDCTRLP; /* 0x14: Data Path Control Primary Register */ + __RW uint32_t SDCTRLE; /* 0x18: Data Path Control Extra Register */ + __RW uint32_t SDST; /* 0x1C: Data Path Status */ + __R uint32_t SDATA; /* 0x20: Data */ + __R uint32_t SDFIFO; /* 0x24: FIFO Data */ + __R uint32_t SCAMP; /* 0x28: instant Amplitude Results */ + __RW uint32_t SCHTL; /* 0x2C: Amplitude Threshold for High Limit */ + __RW uint32_t SCHTLZ; /* 0x30: Amplitude Threshold for zero crossing */ + __RW uint32_t SCLLT; /* 0x34: Amplitude Threshold for low limit */ + __RW uint32_t SCCTRL; /* 0x38: Amplitude Path Control */ + __RW uint32_t SCST; /* 0x3C: Amplitude Path Status */ + __R uint8_t RESERVED0[16]; /* 0x40 - 0x4F: Reserved */ + } CH[1]; +} SDMV2_Type; + + +/* Bitfield definition for register: CTRL */ +/* + * SFTRST (RW) + * + * software reset the module if asserted to be1’b1. + */ +#define SDMV2_CTRL_SFTRST_MASK (0x80000000UL) +#define SDMV2_CTRL_SFTRST_SHIFT (31U) +#define SDMV2_CTRL_SFTRST_SET(x) (((uint32_t)(x) << SDMV2_CTRL_SFTRST_SHIFT) & SDMV2_CTRL_SFTRST_MASK) +#define SDMV2_CTRL_SFTRST_GET(x) (((uint32_t)(x) & SDMV2_CTRL_SFTRST_MASK) >> SDMV2_CTRL_SFTRST_SHIFT) + +/* + * CHMD (RW) + * + * Channel Rcv mode + * Bits[2:0] for Ch0. + * Bits[5:3] for Ch1 + * Bits[8:6] for Ch2 + * Bits[11:9] for Ch3 + * 3'b000: Capture at posedge of MCLK + * 3'b001: Capture at both posedge and negedge of MCLK + * 3'b010: Manchestor Mode + * 3'b011: Capture at negedge of MCLK + * 3'b100: Capture at every other posedge of MCLK + * 3'b101: Capture at every other negedge of MCLK + * Others: Undefined + */ +#define SDMV2_CTRL_CHMD_MASK (0x3FFC000UL) +#define SDMV2_CTRL_CHMD_SHIFT (14U) +#define SDMV2_CTRL_CHMD_SET(x) (((uint32_t)(x) << SDMV2_CTRL_CHMD_SHIFT) & SDMV2_CTRL_CHMD_MASK) +#define SDMV2_CTRL_CHMD_GET(x) (((uint32_t)(x) & SDMV2_CTRL_CHMD_MASK) >> SDMV2_CTRL_CHMD_SHIFT) + +/* + * SYNC_MCLK (RW) + * + * Asserted to double sync the mclk input pin before its usage inside the module + */ +#define SDMV2_CTRL_SYNC_MCLK_MASK (0x3C00U) +#define SDMV2_CTRL_SYNC_MCLK_SHIFT (10U) +#define SDMV2_CTRL_SYNC_MCLK_SET(x) (((uint32_t)(x) << SDMV2_CTRL_SYNC_MCLK_SHIFT) & SDMV2_CTRL_SYNC_MCLK_MASK) +#define SDMV2_CTRL_SYNC_MCLK_GET(x) (((uint32_t)(x) & SDMV2_CTRL_SYNC_MCLK_MASK) >> SDMV2_CTRL_SYNC_MCLK_SHIFT) + +/* + * SYNC_MDAT (RW) + * + * Asserted to double sync the mdat input pin before its usage inside the module + */ +#define SDMV2_CTRL_SYNC_MDAT_MASK (0x3C0U) +#define SDMV2_CTRL_SYNC_MDAT_SHIFT (6U) +#define SDMV2_CTRL_SYNC_MDAT_SET(x) (((uint32_t)(x) << SDMV2_CTRL_SYNC_MDAT_SHIFT) & SDMV2_CTRL_SYNC_MDAT_MASK) +#define SDMV2_CTRL_SYNC_MDAT_GET(x) (((uint32_t)(x) & SDMV2_CTRL_SYNC_MDAT_MASK) >> SDMV2_CTRL_SYNC_MDAT_SHIFT) + +/* + * CH_EN (RW) + * + * Channel Enable + */ +#define SDMV2_CTRL_CH_EN_MASK (0x3CU) +#define SDMV2_CTRL_CH_EN_SHIFT (2U) +#define SDMV2_CTRL_CH_EN_SET(x) (((uint32_t)(x) << SDMV2_CTRL_CH_EN_SHIFT) & SDMV2_CTRL_CH_EN_MASK) +#define SDMV2_CTRL_CH_EN_GET(x) (((uint32_t)(x) & SDMV2_CTRL_CH_EN_MASK) >> SDMV2_CTRL_CH_EN_SHIFT) + +/* + * IE (RW) + * + * Interrupt Enable + */ +#define SDMV2_CTRL_IE_MASK (0x2U) +#define SDMV2_CTRL_IE_SHIFT (1U) +#define SDMV2_CTRL_IE_SET(x) (((uint32_t)(x) << SDMV2_CTRL_IE_SHIFT) & SDMV2_CTRL_IE_MASK) +#define SDMV2_CTRL_IE_GET(x) (((uint32_t)(x) & SDMV2_CTRL_IE_MASK) >> SDMV2_CTRL_IE_SHIFT) + +/* Bitfield definition for register: INT_EN */ +/* + * CH0DRY (RW) + * + * Ch0 Data Ready interrupt enable + */ +#define SDMV2_INT_EN_CH0DRY_MASK (0x10U) +#define SDMV2_INT_EN_CH0DRY_SHIFT (4U) +#define SDMV2_INT_EN_CH0DRY_SET(x) (((uint32_t)(x) << SDMV2_INT_EN_CH0DRY_SHIFT) & SDMV2_INT_EN_CH0DRY_MASK) +#define SDMV2_INT_EN_CH0DRY_GET(x) (((uint32_t)(x) & SDMV2_INT_EN_CH0DRY_MASK) >> SDMV2_INT_EN_CH0DRY_SHIFT) + +/* + * CH0ERR (RW) + * + * Ch0 Error interrupt enable + */ +#define SDMV2_INT_EN_CH0ERR_MASK (0x1U) +#define SDMV2_INT_EN_CH0ERR_SHIFT (0U) +#define SDMV2_INT_EN_CH0ERR_SET(x) (((uint32_t)(x) << SDMV2_INT_EN_CH0ERR_SHIFT) & SDMV2_INT_EN_CH0ERR_MASK) +#define SDMV2_INT_EN_CH0ERR_GET(x) (((uint32_t)(x) & SDMV2_INT_EN_CH0ERR_MASK) >> SDMV2_INT_EN_CH0ERR_SHIFT) + +/* Bitfield definition for register: STATUS */ +/* + * CH0DRY (RO) + * + * Ch0 Data Ready + */ +#define SDMV2_STATUS_CH0DRY_MASK (0x2U) +#define SDMV2_STATUS_CH0DRY_SHIFT (1U) +#define SDMV2_STATUS_CH0DRY_GET(x) (((uint32_t)(x) & SDMV2_STATUS_CH0DRY_MASK) >> SDMV2_STATUS_CH0DRY_SHIFT) + +/* + * CH0ERR (RO) + * + * Ch0 Error + */ +#define SDMV2_STATUS_CH0ERR_MASK (0x1U) +#define SDMV2_STATUS_CH0ERR_SHIFT (0U) +#define SDMV2_STATUS_CH0ERR_GET(x) (((uint32_t)(x) & SDMV2_STATUS_CH0ERR_MASK) >> SDMV2_STATUS_CH0ERR_SHIFT) + +/* Bitfield definition for register of struct array CH: SDFIFOCTRL */ +/* + * THRSH (RW) + * + * FIFO threshold (0,..,16) (fillings > threshold, then gen int) + */ +#define SDMV2_CH_SDFIFOCTRL_THRSH_MASK (0x1F0U) +#define SDMV2_CH_SDFIFOCTRL_THRSH_SHIFT (4U) +#define SDMV2_CH_SDFIFOCTRL_THRSH_SET(x) (((uint32_t)(x) << SDMV2_CH_SDFIFOCTRL_THRSH_SHIFT) & SDMV2_CH_SDFIFOCTRL_THRSH_MASK) +#define SDMV2_CH_SDFIFOCTRL_THRSH_GET(x) (((uint32_t)(x) & SDMV2_CH_SDFIFOCTRL_THRSH_MASK) >> SDMV2_CH_SDFIFOCTRL_THRSH_SHIFT) + +/* + * D_RDY_INT_EN (RW) + * + * FIFO data ready interrupt enable + */ +#define SDMV2_CH_SDFIFOCTRL_D_RDY_INT_EN_MASK (0x4U) +#define SDMV2_CH_SDFIFOCTRL_D_RDY_INT_EN_SHIFT (2U) +#define SDMV2_CH_SDFIFOCTRL_D_RDY_INT_EN_SET(x) (((uint32_t)(x) << SDMV2_CH_SDFIFOCTRL_D_RDY_INT_EN_SHIFT) & SDMV2_CH_SDFIFOCTRL_D_RDY_INT_EN_MASK) +#define SDMV2_CH_SDFIFOCTRL_D_RDY_INT_EN_GET(x) (((uint32_t)(x) & SDMV2_CH_SDFIFOCTRL_D_RDY_INT_EN_MASK) >> SDMV2_CH_SDFIFOCTRL_D_RDY_INT_EN_SHIFT) + +/* Bitfield definition for register of struct array CH: SDCTRLP */ +/* + * MANCH_THR (RW) + * + * Manchester Decoding threshold. 3/4 of PERIOD_MCLK[7:0] + */ +#define SDMV2_CH_SDCTRLP_MANCH_THR_MASK (0xFE000000UL) +#define SDMV2_CH_SDCTRLP_MANCH_THR_SHIFT (25U) +#define SDMV2_CH_SDCTRLP_MANCH_THR_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_MANCH_THR_SHIFT) & SDMV2_CH_SDCTRLP_MANCH_THR_MASK) +#define SDMV2_CH_SDCTRLP_MANCH_THR_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_MANCH_THR_MASK) >> SDMV2_CH_SDCTRLP_MANCH_THR_SHIFT) + +/* + * WDOG_THR (RW) + * + * Watch dog threshold for channel failure of CLK halting + */ +#define SDMV2_CH_SDCTRLP_WDOG_THR_MASK (0x1FE0000UL) +#define SDMV2_CH_SDCTRLP_WDOG_THR_SHIFT (17U) +#define SDMV2_CH_SDCTRLP_WDOG_THR_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_WDOG_THR_SHIFT) & SDMV2_CH_SDCTRLP_WDOG_THR_MASK) +#define SDMV2_CH_SDCTRLP_WDOG_THR_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_WDOG_THR_MASK) >> SDMV2_CH_SDCTRLP_WDOG_THR_SHIFT) + +/* + * AF_IE (RW) + * + * Acknowledge feedback interrupt enable + */ +#define SDMV2_CH_SDCTRLP_AF_IE_MASK (0x10000UL) +#define SDMV2_CH_SDCTRLP_AF_IE_SHIFT (16U) +#define SDMV2_CH_SDCTRLP_AF_IE_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_AF_IE_SHIFT) & SDMV2_CH_SDCTRLP_AF_IE_MASK) +#define SDMV2_CH_SDCTRLP_AF_IE_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_AF_IE_MASK) >> SDMV2_CH_SDCTRLP_AF_IE_SHIFT) + +/* + * DFFOVIE (RW) + * + * Ch Data FIFO overflow interrupt enable + */ +#define SDMV2_CH_SDCTRLP_DFFOVIE_MASK (0x8000U) +#define SDMV2_CH_SDCTRLP_DFFOVIE_SHIFT (15U) +#define SDMV2_CH_SDCTRLP_DFFOVIE_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_DFFOVIE_SHIFT) & SDMV2_CH_SDCTRLP_DFFOVIE_MASK) +#define SDMV2_CH_SDCTRLP_DFFOVIE_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_DFFOVIE_MASK) >> SDMV2_CH_SDCTRLP_DFFOVIE_SHIFT) + +/* + * DSATIE (RW) + * + * Ch CIC Data Saturation Interrupt Enable + */ +#define SDMV2_CH_SDCTRLP_DSATIE_MASK (0x4000U) +#define SDMV2_CH_SDCTRLP_DSATIE_SHIFT (14U) +#define SDMV2_CH_SDCTRLP_DSATIE_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_DSATIE_SHIFT) & SDMV2_CH_SDCTRLP_DSATIE_MASK) +#define SDMV2_CH_SDCTRLP_DSATIE_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_DSATIE_MASK) >> SDMV2_CH_SDCTRLP_DSATIE_SHIFT) + +/* + * DRIE (RW) + * + * Ch Data Ready Interrupt Enable + */ +#define SDMV2_CH_SDCTRLP_DRIE_MASK (0x2000U) +#define SDMV2_CH_SDCTRLP_DRIE_SHIFT (13U) +#define SDMV2_CH_SDCTRLP_DRIE_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_DRIE_SHIFT) & SDMV2_CH_SDCTRLP_DRIE_MASK) +#define SDMV2_CH_SDCTRLP_DRIE_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_DRIE_MASK) >> SDMV2_CH_SDCTRLP_DRIE_SHIFT) + +/* + * SYNCSEL (RW) + * + * Select the PWM SYNC Source + */ +#define SDMV2_CH_SDCTRLP_SYNCSEL_MASK (0x1F80U) +#define SDMV2_CH_SDCTRLP_SYNCSEL_SHIFT (7U) +#define SDMV2_CH_SDCTRLP_SYNCSEL_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_SYNCSEL_SHIFT) & SDMV2_CH_SDCTRLP_SYNCSEL_MASK) +#define SDMV2_CH_SDCTRLP_SYNCSEL_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_SYNCSEL_MASK) >> SDMV2_CH_SDCTRLP_SYNCSEL_SHIFT) + +/* + * FFSYNCCLREN (RW) + * + * Auto clear FIFO when a new SDSYNC event is found. Only valid when WTSYNCEN=1 + */ +#define SDMV2_CH_SDCTRLP_FFSYNCCLREN_MASK (0x40U) +#define SDMV2_CH_SDCTRLP_FFSYNCCLREN_SHIFT (6U) +#define SDMV2_CH_SDCTRLP_FFSYNCCLREN_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_FFSYNCCLREN_SHIFT) & SDMV2_CH_SDCTRLP_FFSYNCCLREN_MASK) +#define SDMV2_CH_SDCTRLP_FFSYNCCLREN_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_FFSYNCCLREN_MASK) >> SDMV2_CH_SDCTRLP_FFSYNCCLREN_SHIFT) + +/* + * WTSYNACLR (RW) + * + * 1: Asserted to Auto clear WTSYNFLG when the SDFFINT is gen + * 0: WTSYNFLG should be cleared manually by WTSYNMCLR + */ +#define SDMV2_CH_SDCTRLP_WTSYNACLR_MASK (0x20U) +#define SDMV2_CH_SDCTRLP_WTSYNACLR_SHIFT (5U) +#define SDMV2_CH_SDCTRLP_WTSYNACLR_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_WTSYNACLR_SHIFT) & SDMV2_CH_SDCTRLP_WTSYNACLR_MASK) +#define SDMV2_CH_SDCTRLP_WTSYNACLR_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_WTSYNACLR_MASK) >> SDMV2_CH_SDCTRLP_WTSYNACLR_SHIFT) + +/* + * WTSYNMCLR (RW) + * + * 1: Manually clear WTSYNFLG. Auto-clear. + */ +#define SDMV2_CH_SDCTRLP_WTSYNMCLR_MASK (0x10U) +#define SDMV2_CH_SDCTRLP_WTSYNMCLR_SHIFT (4U) +#define SDMV2_CH_SDCTRLP_WTSYNMCLR_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_WTSYNMCLR_SHIFT) & SDMV2_CH_SDCTRLP_WTSYNMCLR_MASK) +#define SDMV2_CH_SDCTRLP_WTSYNMCLR_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_WTSYNMCLR_MASK) >> SDMV2_CH_SDCTRLP_WTSYNMCLR_SHIFT) + +/* + * WTSYNCEN (RW) + * + * 1: Start to store data only after PWM SYNC event + * 0: Start to store data whenever enabled + */ +#define SDMV2_CH_SDCTRLP_WTSYNCEN_MASK (0x8U) +#define SDMV2_CH_SDCTRLP_WTSYNCEN_SHIFT (3U) +#define SDMV2_CH_SDCTRLP_WTSYNCEN_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_WTSYNCEN_SHIFT) & SDMV2_CH_SDCTRLP_WTSYNCEN_MASK) +#define SDMV2_CH_SDCTRLP_WTSYNCEN_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_WTSYNCEN_MASK) >> SDMV2_CH_SDCTRLP_WTSYNCEN_SHIFT) + +/* + * D32 (RW) + * + * 1:32 bit data + * 0:16 bit data + */ +#define SDMV2_CH_SDCTRLP_D32_MASK (0x4U) +#define SDMV2_CH_SDCTRLP_D32_SHIFT (2U) +#define SDMV2_CH_SDCTRLP_D32_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_D32_SHIFT) & SDMV2_CH_SDCTRLP_D32_MASK) +#define SDMV2_CH_SDCTRLP_D32_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_D32_MASK) >> SDMV2_CH_SDCTRLP_D32_SHIFT) + +/* + * DR_OPT (RW) + * + * 1: Use Data FIFO Ready as data ready when fifo fillings are greater than the threshold + * 0: Use Data Reg Ready as data ready + */ +#define SDMV2_CH_SDCTRLP_DR_OPT_MASK (0x2U) +#define SDMV2_CH_SDCTRLP_DR_OPT_SHIFT (1U) +#define SDMV2_CH_SDCTRLP_DR_OPT_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_DR_OPT_SHIFT) & SDMV2_CH_SDCTRLP_DR_OPT_MASK) +#define SDMV2_CH_SDCTRLP_DR_OPT_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_DR_OPT_MASK) >> SDMV2_CH_SDCTRLP_DR_OPT_SHIFT) + +/* + * EN (RW) + * + * Data Path Enable + */ +#define SDMV2_CH_SDCTRLP_EN_MASK (0x1U) +#define SDMV2_CH_SDCTRLP_EN_SHIFT (0U) +#define SDMV2_CH_SDCTRLP_EN_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_EN_SHIFT) & SDMV2_CH_SDCTRLP_EN_MASK) +#define SDMV2_CH_SDCTRLP_EN_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_EN_MASK) >> SDMV2_CH_SDCTRLP_EN_SHIFT) + +/* Bitfield definition for register of struct array CH: SDCTRLE */ +/* + * 2ND_CIC_SCL (RW) + * + * the shifter pace for the output of the 2ns stage CIC + * 0: shift right 0 + * … + * n: shift right n steps + * max 17, so needs 5 bits + */ +#define SDMV2_CH_SDCTRLE_2ND_CIC_SCL_MASK (0x3E00000UL) +#define SDMV2_CH_SDCTRLE_2ND_CIC_SCL_SHIFT (21U) +#define SDMV2_CH_SDCTRLE_2ND_CIC_SCL_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLE_2ND_CIC_SCL_SHIFT) & SDMV2_CH_SDCTRLE_2ND_CIC_SCL_MASK) +#define SDMV2_CH_SDCTRLE_2ND_CIC_SCL_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLE_2ND_CIC_SCL_MASK) >> SDMV2_CH_SDCTRLE_2ND_CIC_SCL_SHIFT) + +/* + * 2ND_SGD_ORDER (RW) + * + * 2nd CIC order + * 0: SYNC1 + * 1: SYNC2 + * 2: SYNC3 + * 3: FAST_SYNC + */ +#define SDMV2_CH_SDCTRLE_2ND_SGD_ORDER_MASK (0x180000UL) +#define SDMV2_CH_SDCTRLE_2ND_SGD_ORDER_SHIFT (19U) +#define SDMV2_CH_SDCTRLE_2ND_SGD_ORDER_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLE_2ND_SGD_ORDER_SHIFT) & SDMV2_CH_SDCTRLE_2ND_SGD_ORDER_MASK) +#define SDMV2_CH_SDCTRLE_2ND_SGD_ORDER_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLE_2ND_SGD_ORDER_MASK) >> SDMV2_CH_SDCTRLE_2ND_SGD_ORDER_SHIFT) + +/* + * SGD_ORDR (RW) + * + * CIC order + * 0: SYNC1 + * 1: SYNC2 + * 2: SYNC3 + * 3: FAST_SYNC + */ +#define SDMV2_CH_SDCTRLE_SGD_ORDR_MASK (0x60000UL) +#define SDMV2_CH_SDCTRLE_SGD_ORDR_SHIFT (17U) +#define SDMV2_CH_SDCTRLE_SGD_ORDR_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLE_SGD_ORDR_SHIFT) & SDMV2_CH_SDCTRLE_SGD_ORDR_MASK) +#define SDMV2_CH_SDCTRLE_SGD_ORDR_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLE_SGD_ORDR_MASK) >> SDMV2_CH_SDCTRLE_SGD_ORDR_SHIFT) + +/* + * PWMSYNC (RW) + * + * Asserted to double sync the PWM trigger signal + */ +#define SDMV2_CH_SDCTRLE_PWMSYNC_MASK (0x10000UL) +#define SDMV2_CH_SDCTRLE_PWMSYNC_SHIFT (16U) +#define SDMV2_CH_SDCTRLE_PWMSYNC_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLE_PWMSYNC_SHIFT) & SDMV2_CH_SDCTRLE_PWMSYNC_MASK) +#define SDMV2_CH_SDCTRLE_PWMSYNC_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLE_PWMSYNC_MASK) >> SDMV2_CH_SDCTRLE_PWMSYNC_SHIFT) + +/* + * USE_ALT (RW) + * + * Asserted to use alternative input. + * Alternative input has a restart_filt to reset the counter and start data transfer, and also it has an intermittent input clock to accompany the input data. + */ +#define SDMV2_CH_SDCTRLE_USE_ALT_MASK (0x8000U) +#define SDMV2_CH_SDCTRLE_USE_ALT_SHIFT (15U) +#define SDMV2_CH_SDCTRLE_USE_ALT_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLE_USE_ALT_SHIFT) & SDMV2_CH_SDCTRLE_USE_ALT_MASK) +#define SDMV2_CH_SDCTRLE_USE_ALT_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLE_USE_ALT_MASK) >> SDMV2_CH_SDCTRLE_USE_ALT_SHIFT) + +/* + * CIC_SCL (RW) + * + * CIC shift control + */ +#define SDMV2_CH_SDCTRLE_CIC_SCL_MASK (0x7800U) +#define SDMV2_CH_SDCTRLE_CIC_SCL_SHIFT (11U) +#define SDMV2_CH_SDCTRLE_CIC_SCL_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLE_CIC_SCL_SHIFT) & SDMV2_CH_SDCTRLE_CIC_SCL_MASK) +#define SDMV2_CH_SDCTRLE_CIC_SCL_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLE_CIC_SCL_MASK) >> SDMV2_CH_SDCTRLE_CIC_SCL_SHIFT) + +/* + * CIC_DEC_RATIO (RW) + * + * CIC decimation ratio. 0 means div-by-256 + */ +#define SDMV2_CH_SDCTRLE_CIC_DEC_RATIO_MASK (0x7F8U) +#define SDMV2_CH_SDCTRLE_CIC_DEC_RATIO_SHIFT (3U) +#define SDMV2_CH_SDCTRLE_CIC_DEC_RATIO_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLE_CIC_DEC_RATIO_SHIFT) & SDMV2_CH_SDCTRLE_CIC_DEC_RATIO_MASK) +#define SDMV2_CH_SDCTRLE_CIC_DEC_RATIO_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLE_CIC_DEC_RATIO_MASK) >> SDMV2_CH_SDCTRLE_CIC_DEC_RATIO_SHIFT) + +/* + * IGN_INI_SAMPLES (RW) + * + * NotZero: Don't store the first samples that are not accurate + * Zero: Store all samples + */ +#define SDMV2_CH_SDCTRLE_IGN_INI_SAMPLES_MASK (0x7U) +#define SDMV2_CH_SDCTRLE_IGN_INI_SAMPLES_SHIFT (0U) +#define SDMV2_CH_SDCTRLE_IGN_INI_SAMPLES_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLE_IGN_INI_SAMPLES_SHIFT) & SDMV2_CH_SDCTRLE_IGN_INI_SAMPLES_MASK) +#define SDMV2_CH_SDCTRLE_IGN_INI_SAMPLES_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLE_IGN_INI_SAMPLES_MASK) >> SDMV2_CH_SDCTRLE_IGN_INI_SAMPLES_SHIFT) + +/* Bitfield definition for register of struct array CH: SDST */ +/* + * PERIOD_MCLK (RO) + * + * maxim of mclk spacing in cycles, using edges of mclk signal. In manchester coding mode, it is just the period of MCLK. In other modes, it is almost the half period. + */ +#define SDMV2_CH_SDST_PERIOD_MCLK_MASK (0x7F800000UL) +#define SDMV2_CH_SDST_PERIOD_MCLK_SHIFT (23U) +#define SDMV2_CH_SDST_PERIOD_MCLK_GET(x) (((uint32_t)(x) & SDMV2_CH_SDST_PERIOD_MCLK_MASK) >> SDMV2_CH_SDST_PERIOD_MCLK_SHIFT) + +/* + * 2ND_DSAT_ERR (W1C) + * + * CIC out Data saturation err. Error flag. + */ +#define SDMV2_CH_SDST_2ND_DSAT_ERR_MASK (0x800U) +#define SDMV2_CH_SDST_2ND_DSAT_ERR_SHIFT (11U) +#define SDMV2_CH_SDST_2ND_DSAT_ERR_SET(x) (((uint32_t)(x) << SDMV2_CH_SDST_2ND_DSAT_ERR_SHIFT) & SDMV2_CH_SDST_2ND_DSAT_ERR_MASK) +#define SDMV2_CH_SDST_2ND_DSAT_ERR_GET(x) (((uint32_t)(x) & SDMV2_CH_SDST_2ND_DSAT_ERR_MASK) >> SDMV2_CH_SDST_2ND_DSAT_ERR_SHIFT) + +/* + * FIFO_DR (W1C) + * + * FIFO data ready + */ +#define SDMV2_CH_SDST_FIFO_DR_MASK (0x200U) +#define SDMV2_CH_SDST_FIFO_DR_SHIFT (9U) +#define SDMV2_CH_SDST_FIFO_DR_SET(x) (((uint32_t)(x) << SDMV2_CH_SDST_FIFO_DR_SHIFT) & SDMV2_CH_SDST_FIFO_DR_MASK) +#define SDMV2_CH_SDST_FIFO_DR_GET(x) (((uint32_t)(x) & SDMV2_CH_SDST_FIFO_DR_MASK) >> SDMV2_CH_SDST_FIFO_DR_SHIFT) + +/* + * AF (W1C) + * + * Achnowledge flag + */ +#define SDMV2_CH_SDST_AF_MASK (0x100U) +#define SDMV2_CH_SDST_AF_SHIFT (8U) +#define SDMV2_CH_SDST_AF_SET(x) (((uint32_t)(x) << SDMV2_CH_SDST_AF_SHIFT) & SDMV2_CH_SDST_AF_MASK) +#define SDMV2_CH_SDST_AF_GET(x) (((uint32_t)(x) & SDMV2_CH_SDST_AF_MASK) >> SDMV2_CH_SDST_AF_SHIFT) + +/* + * DOV_ERR (W1C) + * + * Data FIFO Overflow Error. Error flag. + */ +#define SDMV2_CH_SDST_DOV_ERR_MASK (0x80U) +#define SDMV2_CH_SDST_DOV_ERR_SHIFT (7U) +#define SDMV2_CH_SDST_DOV_ERR_SET(x) (((uint32_t)(x) << SDMV2_CH_SDST_DOV_ERR_SHIFT) & SDMV2_CH_SDST_DOV_ERR_MASK) +#define SDMV2_CH_SDST_DOV_ERR_GET(x) (((uint32_t)(x) & SDMV2_CH_SDST_DOV_ERR_MASK) >> SDMV2_CH_SDST_DOV_ERR_SHIFT) + +/* + * DSAT_ERR (W1C) + * + * CIC out Data saturation err. Error flag. + */ +#define SDMV2_CH_SDST_DSAT_ERR_MASK (0x40U) +#define SDMV2_CH_SDST_DSAT_ERR_SHIFT (6U) +#define SDMV2_CH_SDST_DSAT_ERR_SET(x) (((uint32_t)(x) << SDMV2_CH_SDST_DSAT_ERR_SHIFT) & SDMV2_CH_SDST_DSAT_ERR_MASK) +#define SDMV2_CH_SDST_DSAT_ERR_GET(x) (((uint32_t)(x) & SDMV2_CH_SDST_DSAT_ERR_MASK) >> SDMV2_CH_SDST_DSAT_ERR_SHIFT) + +/* + * WTSYNFLG (RO) + * + * Wait-for-sync event found + */ +#define SDMV2_CH_SDST_WTSYNFLG_MASK (0x20U) +#define SDMV2_CH_SDST_WTSYNFLG_SHIFT (5U) +#define SDMV2_CH_SDST_WTSYNFLG_GET(x) (((uint32_t)(x) & SDMV2_CH_SDST_WTSYNFLG_MASK) >> SDMV2_CH_SDST_WTSYNFLG_SHIFT) + +/* + * FILL (RO) + * + * Data FIFO Fillings + */ +#define SDMV2_CH_SDST_FILL_MASK (0x1FU) +#define SDMV2_CH_SDST_FILL_SHIFT (0U) +#define SDMV2_CH_SDST_FILL_GET(x) (((uint32_t)(x) & SDMV2_CH_SDST_FILL_MASK) >> SDMV2_CH_SDST_FILL_SHIFT) + +/* Bitfield definition for register of struct array CH: SDATA */ +/* + * VAL (RO) + * + * Data + */ +#define SDMV2_CH_SDATA_VAL_MASK (0xFFFFFFFFUL) +#define SDMV2_CH_SDATA_VAL_SHIFT (0U) +#define SDMV2_CH_SDATA_VAL_GET(x) (((uint32_t)(x) & SDMV2_CH_SDATA_VAL_MASK) >> SDMV2_CH_SDATA_VAL_SHIFT) + +/* Bitfield definition for register of struct array CH: SDFIFO */ +/* + * VAL (RO) + * + * FIFO Data + */ +#define SDMV2_CH_SDFIFO_VAL_MASK (0xFFFFFFFFUL) +#define SDMV2_CH_SDFIFO_VAL_SHIFT (0U) +#define SDMV2_CH_SDFIFO_VAL_GET(x) (((uint32_t)(x) & SDMV2_CH_SDFIFO_VAL_MASK) >> SDMV2_CH_SDFIFO_VAL_SHIFT) + +/* Bitfield definition for register of struct array CH: SCAMP */ +/* + * VAL (RO) + * + * instant Amplitude Results + */ +#define SDMV2_CH_SCAMP_VAL_MASK (0xFFFFU) +#define SDMV2_CH_SCAMP_VAL_SHIFT (0U) +#define SDMV2_CH_SCAMP_VAL_GET(x) (((uint32_t)(x) & SDMV2_CH_SCAMP_VAL_MASK) >> SDMV2_CH_SCAMP_VAL_SHIFT) + +/* Bitfield definition for register of struct array CH: SCHTL */ +/* + * VAL (RW) + * + * Amplitude Threshold for High Limit + */ +#define SDMV2_CH_SCHTL_VAL_MASK (0xFFFFU) +#define SDMV2_CH_SCHTL_VAL_SHIFT (0U) +#define SDMV2_CH_SCHTL_VAL_SET(x) (((uint32_t)(x) << SDMV2_CH_SCHTL_VAL_SHIFT) & SDMV2_CH_SCHTL_VAL_MASK) +#define SDMV2_CH_SCHTL_VAL_GET(x) (((uint32_t)(x) & SDMV2_CH_SCHTL_VAL_MASK) >> SDMV2_CH_SCHTL_VAL_SHIFT) + +/* Bitfield definition for register of struct array CH: SCHTLZ */ +/* + * VAL (RW) + * + * Amplitude Threshold for zero crossing + */ +#define SDMV2_CH_SCHTLZ_VAL_MASK (0xFFFFU) +#define SDMV2_CH_SCHTLZ_VAL_SHIFT (0U) +#define SDMV2_CH_SCHTLZ_VAL_SET(x) (((uint32_t)(x) << SDMV2_CH_SCHTLZ_VAL_SHIFT) & SDMV2_CH_SCHTLZ_VAL_MASK) +#define SDMV2_CH_SCHTLZ_VAL_GET(x) (((uint32_t)(x) & SDMV2_CH_SCHTLZ_VAL_MASK) >> SDMV2_CH_SCHTLZ_VAL_SHIFT) + +/* Bitfield definition for register of struct array CH: SCLLT */ +/* + * VAL (RW) + * + * Amplitude Threshold for low limit + */ +#define SDMV2_CH_SCLLT_VAL_MASK (0xFFFFU) +#define SDMV2_CH_SCLLT_VAL_SHIFT (0U) +#define SDMV2_CH_SCLLT_VAL_SET(x) (((uint32_t)(x) << SDMV2_CH_SCLLT_VAL_SHIFT) & SDMV2_CH_SCLLT_VAL_MASK) +#define SDMV2_CH_SCLLT_VAL_GET(x) (((uint32_t)(x) & SDMV2_CH_SCLLT_VAL_MASK) >> SDMV2_CH_SCLLT_VAL_SHIFT) + +/* Bitfield definition for register of struct array CH: SCCTRL */ +/* + * 2ND_SGD_ORDR (RW) + * + * CIC decimation ratio. 0 means div-by-256 + */ +#define SDMV2_CH_SCCTRL_2ND_SGD_ORDR_MASK (0xFF000000UL) +#define SDMV2_CH_SCCTRL_2ND_SGD_ORDR_SHIFT (24U) +#define SDMV2_CH_SCCTRL_2ND_SGD_ORDR_SET(x) (((uint32_t)(x) << SDMV2_CH_SCCTRL_2ND_SGD_ORDR_SHIFT) & SDMV2_CH_SCCTRL_2ND_SGD_ORDR_MASK) +#define SDMV2_CH_SCCTRL_2ND_SGD_ORDR_GET(x) (((uint32_t)(x) & SDMV2_CH_SCCTRL_2ND_SGD_ORDR_MASK) >> SDMV2_CH_SCCTRL_2ND_SGD_ORDR_SHIFT) + +/* + * HZ_EN (RW) + * + * Zero Crossing Enable + */ +#define SDMV2_CH_SCCTRL_HZ_EN_MASK (0x800000UL) +#define SDMV2_CH_SCCTRL_HZ_EN_SHIFT (23U) +#define SDMV2_CH_SCCTRL_HZ_EN_SET(x) (((uint32_t)(x) << SDMV2_CH_SCCTRL_HZ_EN_SHIFT) & SDMV2_CH_SCCTRL_HZ_EN_MASK) +#define SDMV2_CH_SCCTRL_HZ_EN_GET(x) (((uint32_t)(x) & SDMV2_CH_SCCTRL_HZ_EN_MASK) >> SDMV2_CH_SCCTRL_HZ_EN_SHIFT) + +/* + * MF_IE (RW) + * + * Module failure Interrupt enable + */ +#define SDMV2_CH_SCCTRL_MF_IE_MASK (0x400000UL) +#define SDMV2_CH_SCCTRL_MF_IE_SHIFT (22U) +#define SDMV2_CH_SCCTRL_MF_IE_SET(x) (((uint32_t)(x) << SDMV2_CH_SCCTRL_MF_IE_SHIFT) & SDMV2_CH_SCCTRL_MF_IE_MASK) +#define SDMV2_CH_SCCTRL_MF_IE_GET(x) (((uint32_t)(x) & SDMV2_CH_SCCTRL_MF_IE_MASK) >> SDMV2_CH_SCCTRL_MF_IE_SHIFT) + +/* + * HL_IE (RW) + * + * HLT Interrupt Enable + */ +#define SDMV2_CH_SCCTRL_HL_IE_MASK (0x200000UL) +#define SDMV2_CH_SCCTRL_HL_IE_SHIFT (21U) +#define SDMV2_CH_SCCTRL_HL_IE_SET(x) (((uint32_t)(x) << SDMV2_CH_SCCTRL_HL_IE_SHIFT) & SDMV2_CH_SCCTRL_HL_IE_MASK) +#define SDMV2_CH_SCCTRL_HL_IE_GET(x) (((uint32_t)(x) & SDMV2_CH_SCCTRL_HL_IE_MASK) >> SDMV2_CH_SCCTRL_HL_IE_SHIFT) + +/* + * LL_IE (RW) + * + * LLT interrupt Enable + */ +#define SDMV2_CH_SCCTRL_LL_IE_MASK (0x100000UL) +#define SDMV2_CH_SCCTRL_LL_IE_SHIFT (20U) +#define SDMV2_CH_SCCTRL_LL_IE_SET(x) (((uint32_t)(x) << SDMV2_CH_SCCTRL_LL_IE_SHIFT) & SDMV2_CH_SCCTRL_LL_IE_MASK) +#define SDMV2_CH_SCCTRL_LL_IE_GET(x) (((uint32_t)(x) & SDMV2_CH_SCCTRL_LL_IE_MASK) >> SDMV2_CH_SCCTRL_LL_IE_SHIFT) + +/* + * SGD_ORDR (RW) + * + * CIC order + * 0: SYNC1 + * 1: SYNC2 + * 2: SYNC3 + * 3: FAST_SYNC + */ +#define SDMV2_CH_SCCTRL_SGD_ORDR_MASK (0xC0000UL) +#define SDMV2_CH_SCCTRL_SGD_ORDR_SHIFT (18U) +#define SDMV2_CH_SCCTRL_SGD_ORDR_SET(x) (((uint32_t)(x) << SDMV2_CH_SCCTRL_SGD_ORDR_SHIFT) & SDMV2_CH_SCCTRL_SGD_ORDR_MASK) +#define SDMV2_CH_SCCTRL_SGD_ORDR_GET(x) (((uint32_t)(x) & SDMV2_CH_SCCTRL_SGD_ORDR_MASK) >> SDMV2_CH_SCCTRL_SGD_ORDR_SHIFT) + +/* + * CIC_DEC_RATIO (RW) + * + * CIC decimation ratio. 0 means div-by-32 + */ +#define SDMV2_CH_SCCTRL_CIC_DEC_RATIO_MASK (0x1F0U) +#define SDMV2_CH_SCCTRL_CIC_DEC_RATIO_SHIFT (4U) +#define SDMV2_CH_SCCTRL_CIC_DEC_RATIO_SET(x) (((uint32_t)(x) << SDMV2_CH_SCCTRL_CIC_DEC_RATIO_SHIFT) & SDMV2_CH_SCCTRL_CIC_DEC_RATIO_MASK) +#define SDMV2_CH_SCCTRL_CIC_DEC_RATIO_GET(x) (((uint32_t)(x) & SDMV2_CH_SCCTRL_CIC_DEC_RATIO_MASK) >> SDMV2_CH_SCCTRL_CIC_DEC_RATIO_SHIFT) + +/* + * IGN_INI_SAMPLES (RW) + * + * NotZero: Ignore the first samples that are not accurate + * Zero: Use all samples + */ +#define SDMV2_CH_SCCTRL_IGN_INI_SAMPLES_MASK (0xEU) +#define SDMV2_CH_SCCTRL_IGN_INI_SAMPLES_SHIFT (1U) +#define SDMV2_CH_SCCTRL_IGN_INI_SAMPLES_SET(x) (((uint32_t)(x) << SDMV2_CH_SCCTRL_IGN_INI_SAMPLES_SHIFT) & SDMV2_CH_SCCTRL_IGN_INI_SAMPLES_MASK) +#define SDMV2_CH_SCCTRL_IGN_INI_SAMPLES_GET(x) (((uint32_t)(x) & SDMV2_CH_SCCTRL_IGN_INI_SAMPLES_MASK) >> SDMV2_CH_SCCTRL_IGN_INI_SAMPLES_SHIFT) + +/* + * EN (RW) + * + * Amplitude Path Enable + */ +#define SDMV2_CH_SCCTRL_EN_MASK (0x1U) +#define SDMV2_CH_SCCTRL_EN_SHIFT (0U) +#define SDMV2_CH_SCCTRL_EN_SET(x) (((uint32_t)(x) << SDMV2_CH_SCCTRL_EN_SHIFT) & SDMV2_CH_SCCTRL_EN_MASK) +#define SDMV2_CH_SCCTRL_EN_GET(x) (((uint32_t)(x) & SDMV2_CH_SCCTRL_EN_MASK) >> SDMV2_CH_SCCTRL_EN_SHIFT) + +/* Bitfield definition for register of struct array CH: SCST */ +/* + * HZ (W1C) + * + * Amplitude rising above HZ event found. + */ +#define SDMV2_CH_SCST_HZ_MASK (0x8U) +#define SDMV2_CH_SCST_HZ_SHIFT (3U) +#define SDMV2_CH_SCST_HZ_SET(x) (((uint32_t)(x) << SDMV2_CH_SCST_HZ_SHIFT) & SDMV2_CH_SCST_HZ_MASK) +#define SDMV2_CH_SCST_HZ_GET(x) (((uint32_t)(x) & SDMV2_CH_SCST_HZ_MASK) >> SDMV2_CH_SCST_HZ_SHIFT) + +/* + * MF (W1C) + * + * power modulator Failure found. MCLK not found. Error flag. + */ +#define SDMV2_CH_SCST_MF_MASK (0x4U) +#define SDMV2_CH_SCST_MF_SHIFT (2U) +#define SDMV2_CH_SCST_MF_SET(x) (((uint32_t)(x) << SDMV2_CH_SCST_MF_SHIFT) & SDMV2_CH_SCST_MF_MASK) +#define SDMV2_CH_SCST_MF_GET(x) (((uint32_t)(x) & SDMV2_CH_SCST_MF_MASK) >> SDMV2_CH_SCST_MF_SHIFT) + +/* + * CMPH (W1C) + * + * HLT out of range. Error flag. + */ +#define SDMV2_CH_SCST_CMPH_MASK (0x2U) +#define SDMV2_CH_SCST_CMPH_SHIFT (1U) +#define SDMV2_CH_SCST_CMPH_SET(x) (((uint32_t)(x) << SDMV2_CH_SCST_CMPH_SHIFT) & SDMV2_CH_SCST_CMPH_MASK) +#define SDMV2_CH_SCST_CMPH_GET(x) (((uint32_t)(x) & SDMV2_CH_SCST_CMPH_MASK) >> SDMV2_CH_SCST_CMPH_SHIFT) + +/* + * CMPL (W1C) + * + * LLT out of range. Error flag. + */ +#define SDMV2_CH_SCST_CMPL_MASK (0x1U) +#define SDMV2_CH_SCST_CMPL_SHIFT (0U) +#define SDMV2_CH_SCST_CMPL_SET(x) (((uint32_t)(x) << SDMV2_CH_SCST_CMPL_SHIFT) & SDMV2_CH_SCST_CMPL_MASK) +#define SDMV2_CH_SCST_CMPL_GET(x) (((uint32_t)(x) & SDMV2_CH_SCST_CMPL_MASK) >> SDMV2_CH_SCST_CMPL_SHIFT) + + + +/* CH register group index macro definition */ +#define SDMV2_CH_0 (0UL) + + +#endif /* HPM_SDMV2_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sdxc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sdxc_regs.h index 1f3bbcadcd2..76f77c5037f 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sdxc_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sdxc_regs.h @@ -68,14 +68,12 @@ typedef struct { __R uint8_t RESERVED8[800]; /* 0x1E0 - 0x4FF: Reserved */ __R uint32_t MSHC_VER_ID; /* 0x500: */ __R uint32_t MSHC_VER_TYPE; /* 0x504: */ - __R uint8_t RESERVED9[8]; /* 0x508 - 0x50F: Reserved */ - __RW uint32_t MBIU_CTRL; /* 0x510: Y */ - __R uint8_t RESERVED10[24]; /* 0x514 - 0x52B: Reserved */ + __R uint8_t RESERVED9[36]; /* 0x508 - 0x52B: Reserved */ __RW uint32_t EMMC_BOOT_CTRL; /* 0x52C: */ - __R uint8_t RESERVED11[16]; /* 0x530 - 0x53F: Reserved */ + __R uint8_t RESERVED10[16]; /* 0x530 - 0x53F: Reserved */ __RW uint32_t AUTO_TUNING_CTRL; /* 0x540: */ __RW uint32_t AUTO_TUNING_STAT; /* 0x544: */ - __R uint8_t RESERVED12[10936]; /* 0x548 - 0x2FFF: Reserved */ + __R uint8_t RESERVED11[10936]; /* 0x548 - 0x2FFF: Reserved */ __RW uint32_t MISC_CTRL0; /* 0x3000: */ __RW uint32_t MISC_CTRL1; /* 0x3004: */ } SDXC_Type; @@ -445,7 +443,7 @@ typedef struct { * * Command Response * These bits reflect 39-8 bits of SD/eMMC Response Field. - * Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP67_R register. + * Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP[RESP67] register. */ #define SDXC_RESP_RESP01_MASK (0xFFFFFFFFUL) #define SDXC_RESP_RESP01_SHIFT (0U) @@ -826,7 +824,7 @@ typedef struct { * This bit enables VDD1 power of the card. * This setting is available on the sd_vdd1_on output of SDXC so that it can be used to control the VDD1 power supply of the card. * Before setting this bit, the SD Host Driver sets the SD Bus Voltage Select bit. If the Host Controller detects a No Card state, this bit is cleared. - * In SD mode, if this bit is cleared, the Host Controller stops the SD Clock by clearing the SD_CLK_IN bit in the CLK_CTRL_R register. + * In SD mode, if this bit is cleared, the Host Controller stops the SD Clock by clearing the SD_CLK_EN bit in the SYS_CTRL register. * Values: * 0x0 (OFF): Power off * 0x1 (ON): Power on @@ -1523,7 +1521,7 @@ typedef struct { * BOOT_ACK_ERR_STAT_EN (RW) * * Boot Acknowledgment Error (eMMC Mode only) - * Setting this bit to 1 enables setting of Boot Acknowledgment Error in Error Interrupt Status register (ERROR_INT_STAT_R). + * Setting this bit to 1 enables setting of Boot Acknowledgment Error in Error Interrupt Status register (INT_STAT). * Values: * 0x0 (FALSE): Masked * 0x1 (TRUE): Enabled @@ -3955,43 +3953,6 @@ typedef struct { #define SDXC_MSHC_VER_TYPE_VER_TYPE_SHIFT (0U) #define SDXC_MSHC_VER_TYPE_VER_TYPE_GET(x) (((uint32_t)(x) & SDXC_MSHC_VER_TYPE_VER_TYPE_MASK) >> SDXC_MSHC_VER_TYPE_VER_TYPE_SHIFT) -/* Bitfield definition for register: MBIU_CTRL */ -/* - * BURST_INCR16_EN (RW) - * - */ -#define SDXC_MBIU_CTRL_BURST_INCR16_EN_MASK (0x8U) -#define SDXC_MBIU_CTRL_BURST_INCR16_EN_SHIFT (3U) -#define SDXC_MBIU_CTRL_BURST_INCR16_EN_SET(x) (((uint32_t)(x) << SDXC_MBIU_CTRL_BURST_INCR16_EN_SHIFT) & SDXC_MBIU_CTRL_BURST_INCR16_EN_MASK) -#define SDXC_MBIU_CTRL_BURST_INCR16_EN_GET(x) (((uint32_t)(x) & SDXC_MBIU_CTRL_BURST_INCR16_EN_MASK) >> SDXC_MBIU_CTRL_BURST_INCR16_EN_SHIFT) - -/* - * BURST_INCR8_EN (RW) - * - */ -#define SDXC_MBIU_CTRL_BURST_INCR8_EN_MASK (0x4U) -#define SDXC_MBIU_CTRL_BURST_INCR8_EN_SHIFT (2U) -#define SDXC_MBIU_CTRL_BURST_INCR8_EN_SET(x) (((uint32_t)(x) << SDXC_MBIU_CTRL_BURST_INCR8_EN_SHIFT) & SDXC_MBIU_CTRL_BURST_INCR8_EN_MASK) -#define SDXC_MBIU_CTRL_BURST_INCR8_EN_GET(x) (((uint32_t)(x) & SDXC_MBIU_CTRL_BURST_INCR8_EN_MASK) >> SDXC_MBIU_CTRL_BURST_INCR8_EN_SHIFT) - -/* - * BUSRT_INCR4_EN (RW) - * - */ -#define SDXC_MBIU_CTRL_BUSRT_INCR4_EN_MASK (0x2U) -#define SDXC_MBIU_CTRL_BUSRT_INCR4_EN_SHIFT (1U) -#define SDXC_MBIU_CTRL_BUSRT_INCR4_EN_SET(x) (((uint32_t)(x) << SDXC_MBIU_CTRL_BUSRT_INCR4_EN_SHIFT) & SDXC_MBIU_CTRL_BUSRT_INCR4_EN_MASK) -#define SDXC_MBIU_CTRL_BUSRT_INCR4_EN_GET(x) (((uint32_t)(x) & SDXC_MBIU_CTRL_BUSRT_INCR4_EN_MASK) >> SDXC_MBIU_CTRL_BUSRT_INCR4_EN_SHIFT) - -/* - * UNDEFL_INCR_EN (RW) - * - */ -#define SDXC_MBIU_CTRL_UNDEFL_INCR_EN_MASK (0x1U) -#define SDXC_MBIU_CTRL_UNDEFL_INCR_EN_SHIFT (0U) -#define SDXC_MBIU_CTRL_UNDEFL_INCR_EN_SET(x) (((uint32_t)(x) << SDXC_MBIU_CTRL_UNDEFL_INCR_EN_SHIFT) & SDXC_MBIU_CTRL_UNDEFL_INCR_EN_MASK) -#define SDXC_MBIU_CTRL_UNDEFL_INCR_EN_GET(x) (((uint32_t)(x) & SDXC_MBIU_CTRL_UNDEFL_INCR_EN_MASK) >> SDXC_MBIU_CTRL_UNDEFL_INCR_EN_SHIFT) - /* Bitfield definition for register: EMMC_BOOT_CTRL */ /* * BOOT_TOUT_CNT (RW) @@ -4239,7 +4200,7 @@ typedef struct { * * This fields enables software-managed tuning flow. * Values: - * 0x1 (SW_TUNING_ENABLE): Software-managed tuning enabled. AT_STAT_R.CENTER_PH_CODE Field is now writable. + * 0x1 (SW_TUNING_ENABLE): Software-managed tuning enabled. AUTO_TUNING_STAT.CENTER_PH_CODE Field is now writable. * 0x0 (SW_TUNING_DISABLE): Software-managed tuning disabled */ #define SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_MASK (0x10U) @@ -4295,7 +4256,7 @@ typedef struct { * * Setting this bit enables Auto tuning engine. This bit is enabled by default when core is configured with mode3 retuning support. * Clear this bit to 0 when core is configured to have Mode3 re-tuning but SW wishes to disable mode3 retuning. - * This field should be programmed only when CLK_CTRL_R.SD_CLK_EN is 0. + * This field should be programmed only when SYS_CTRL.SD_CLK_EN is 0. * Values: * 0x1 (AT_ENABLE): AutoTuning is enabled * 0x0 (AT_DISABLE): AutoTuning is disabled @@ -4327,7 +4288,7 @@ typedef struct { /* * CENTER_PH_CODE (RW) * - * Centered Phase code. Reading this field returns the current value on tuning_cclk_sel output. Setting AT_CTRL_R.SW_TUNE_EN enables software to write to this field and its contents are reflected on tuning_cclk_sel + * Centered Phase code. Reading this field returns the current value on tuning_cclk_sel output. Setting AUTO_TUNING_CTRL.SW_TUNE_EN enables software to write to this field and its contents are reflected on tuning_cclk_sel */ #define SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_MASK (0xFFU) #define SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SHIFT (0U) diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sec_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sec_regs.h index 5a386bec927..ed6f54ebd4d 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sec_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sec_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -246,13 +246,13 @@ typedef struct { * LIFECYCLE (RO) * * lifecycle status, - * bit7: lifecycle_debate, - * bit6: lifecycle_scribe, - * bit5: lifecycle_no_ret, - * bit4: lifecycle_return, - * bit3: lifecycle_secure, - * bit2: lifecycle_nonsec, - * bit1: lifecycle_create, + * bit7: lifecycle_debate, + * bit6: lifecycle_scribe, + * bit5: lifecycle_no_ret, + * bit4: lifecycle_return, + * bit3: lifecycle_secure, + * bit2: lifecycle_nonsec, + * bit1: lifecycle_create, * bit0: lifecycle_unknow */ #define SEC_LIFECYCLE_LIFECYCLE_MASK (0xFFU) diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sei_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sei_regs.h new file mode 100644 index 00000000000..6057410125e --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sei_regs.h @@ -0,0 +1,3636 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_SEI_H +#define HPM_SEI_H + +typedef struct { + struct { + struct { + __RW uint32_t CTRL; /* 0x0: Engine control register */ + __RW uint32_t PTR_CFG; /* 0x4: Pointer configuration register */ + __RW uint32_t WDG_CFG; /* 0x8: Watch dog configuration register */ + __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ + __R uint32_t EXE_STA; /* 0x10: Execution status */ + __R uint32_t EXE_PTR; /* 0x14: Execution pointer */ + __R uint32_t EXE_INST; /* 0x18: Execution instruction */ + __R uint32_t WDG_STA; /* 0x1C: Watch dog status */ + } ENGINE; + struct { + __RW uint32_t CTRL; /* 0x20: Transceiver control register */ + __RW uint32_t TYPE_CFG; /* 0x24: Transceiver configuration register */ + __RW uint32_t BAUD_CFG; /* 0x28: Transceiver baud rate register */ + __RW uint32_t DATA_CFG; /* 0x2C: Transceiver data timing configuration */ + __RW uint32_t CLK_CFG; /* 0x30: Transceiver clock timing configuration */ + __R uint8_t RESERVED0[4]; /* 0x34 - 0x37: Reserved */ + __R uint32_t PIN; /* 0x38: Transceiver pin status */ + __R uint32_t STATE; /* 0x3C: FSM of asynchronous */ + } XCVR; + struct { + __RW uint32_t IN_CFG; /* 0x40: Trigger input configuration */ + __W uint32_t SW; /* 0x44: Software trigger */ + __RW uint32_t PRD_CFG; /* 0x48: Period trigger configuration */ + __RW uint32_t PRD; /* 0x4C: Trigger period */ + __RW uint32_t OUT_CFG; /* 0x50: Trigger output configuration */ + __R uint8_t RESERVED0[12]; /* 0x54 - 0x5F: Reserved */ + __R uint32_t PRD_STS; /* 0x60: Period trigger status */ + __R uint32_t PRD_CNT; /* 0x64: Period trigger counter */ + __R uint8_t RESERVED1[24]; /* 0x68 - 0x7F: Reserved */ + } TRG; + struct { + __RW uint32_t CMD[4]; /* 0x80 - 0x8C: Trigger command */ + __R uint8_t RESERVED0[16]; /* 0x90 - 0x9F: Reserved */ + __R uint32_t TIME[4]; /* 0xA0 - 0xAC: Trigger Time */ + __R uint8_t RESERVED1[16]; /* 0xB0 - 0xBF: Reserved */ + } TRG_TABLE; + struct { + __RW uint32_t MODE; /* 0xC0: command register mode */ + __RW uint32_t IDX; /* 0xC4: command register configuration */ + __RW uint32_t GOLD; /* 0xC8: Command gold value */ + __RW uint32_t CRCINIT; /* 0xCC: Command Initial value */ + __RW uint32_t CRCPOLY; /* 0xD0: Command CRC polymial */ + __R uint8_t RESERVED0[12]; /* 0xD4 - 0xDF: Reserved */ + __RW uint32_t CMD; /* 0xE0: command */ + __RW uint32_t SET; /* 0xE4: command bit set register */ + __RW uint32_t CLR; /* 0xE8: command bit clear register */ + __RW uint32_t INV; /* 0xEC: command bit invert register */ + __R uint32_t IN; /* 0xF0: Commad input */ + __R uint32_t OUT; /* 0xF4: Command output */ + __RW uint32_t STS; /* 0xF8: Command status */ + __R uint8_t RESERVED1[4]; /* 0xFC - 0xFF: Reserved */ + } CMD; + struct { + __RW uint32_t MIN; /* 0x100: command start value */ + __RW uint32_t MAX; /* 0x104: command end value */ + __RW uint32_t MSK; /* 0x108: command compare bit enable */ + __R uint8_t RESERVED0[4]; /* 0x10C - 0x10F: Reserved */ + __RW uint32_t PTA; /* 0x110: command pointer 0 - 3 */ + __RW uint32_t PTB; /* 0x114: command pointer 4 - 7 */ + __RW uint32_t PTC; /* 0x118: command pointer 8 - 11 */ + __RW uint32_t PTD; /* 0x11C: command pointer 12 - 15 */ + } CMD_TABLE[8]; + struct { + __RW uint32_t TRAN[4]; /* 0x200 - 0x20C: Latch state transition configuration */ + __RW uint32_t CFG; /* 0x210: Latch configuration */ + __R uint8_t RESERVED0[4]; /* 0x214 - 0x217: Reserved */ + __R uint32_t TIME; /* 0x218: Latch time */ + __R uint32_t STS; /* 0x21C: Latch status */ + } LATCH[4]; + struct { + __RW uint32_t SMP_EN; /* 0x280: Sample selection register */ + __RW uint32_t SMP_CFG; /* 0x284: Sample configuration */ + __RW uint32_t SMP_DAT; /* 0x288: Sample data */ + __R uint8_t RESERVED0[4]; /* 0x28C - 0x28F: Reserved */ + __RW uint32_t SMP_POS; /* 0x290: Sample override position */ + __RW uint32_t SMP_REV; /* 0x294: Sample override revolution */ + __RW uint32_t SMP_SPD; /* 0x298: Sample override speed */ + __RW uint32_t SMP_ACC; /* 0x29C: Sample override accelerate */ + __RW uint32_t UPD_EN; /* 0x2A0: Update configuration */ + __RW uint32_t UPD_CFG; /* 0x2A4: Update configuration */ + __RW uint32_t UPD_DAT; /* 0x2A8: Update data */ + __RW uint32_t UPD_TIME; /* 0x2AC: Update overide time */ + __RW uint32_t UPD_POS; /* 0x2B0: Update override position */ + __RW uint32_t UPD_REV; /* 0x2B4: Update override revolution */ + __RW uint32_t UPD_SPD; /* 0x2B8: Update override speed */ + __RW uint32_t UPD_ACC; /* 0x2BC: Update override accelerate */ + __R uint32_t SMP_VAL; /* 0x2C0: Sample valid */ + __R uint32_t SMP_STS; /* 0x2C4: Sample status */ + __R uint8_t RESERVED1[4]; /* 0x2C8 - 0x2CB: Reserved */ + __R uint32_t TIME_IN; /* 0x2CC: input time */ + __R uint32_t POS_IN; /* 0x2D0: Input position */ + __R uint32_t REV_IN; /* 0x2D4: Input revolution */ + __R uint32_t SPD_IN; /* 0x2D8: Input speed */ + __R uint32_t ACC_IN; /* 0x2DC: Input accelerate */ + __R uint8_t RESERVED2[4]; /* 0x2E0 - 0x2E3: Reserved */ + __R uint32_t UPD_STS; /* 0x2E4: Update status */ + __R uint8_t RESERVED3[24]; /* 0x2E8 - 0x2FF: Reserved */ + } POS; + struct { + __RW uint32_t INT_EN; /* 0x300: Interrupt Enable */ + __W uint32_t INT_FLAG; /* 0x304: Interrupt flag */ + __R uint32_t INT_STS; /* 0x308: Interrupt status */ + __R uint8_t RESERVED0[4]; /* 0x30C - 0x30F: Reserved */ + __RW uint32_t POINTER0; /* 0x310: Match pointer 0 */ + __RW uint32_t POINTER1; /* 0x314: Match pointer 1 */ + __RW uint32_t INSTR0; /* 0x318: Match instruction 0 */ + __RW uint32_t INSTR1; /* 0x31C: Match instruction 1 */ + } IRQ; + __R uint8_t RESERVED0[224]; /* 0x320 - 0x3FF: Reserved */ + } CTRL[13]; + __RW uint32_t INSTR[256]; /* 0x3400 - 0x37FC: Instructions */ + struct { + __RW uint32_t MODE; /* 0x3800: */ + __RW uint32_t IDX; /* 0x3804: Data register bit index */ + __RW uint32_t GOLD; /* 0x3808: Gold data for data check */ + __RW uint32_t CRCINIT; /* 0x380C: CRC calculation initial vector */ + __RW uint32_t CRCPOLY; /* 0x3810: CRC calculation polynomial */ + __R uint8_t RESERVED0[12]; /* 0x3814 - 0x381F: Reserved */ + __RW uint32_t DATA; /* 0x3820: Data value */ + __RW uint32_t SET; /* 0x3824: Data bit set */ + __RW uint32_t CLR; /* 0x3828: Data bit clear */ + __RW uint32_t INV; /* 0x382C: Data bit invert */ + __R uint32_t IN; /* 0x3830: Data input */ + __R uint32_t OUT; /* 0x3834: Data output */ + __RW uint32_t STS; /* 0x3838: Data status */ + __R uint8_t RESERVED1[4]; /* 0x383C - 0x383F: Reserved */ + } DAT[32]; +} SEI_Type; + + +/* Bitfield definition for register of struct array CTRL: CTRL */ +/* + * WATCH (RW) + * + * Enable watch dog + * 0: Watch dog disabled + * 1: Watch dog enabled + */ +#define SEI_CTRL_ENGINE_CTRL_WATCH_MASK (0x1000000UL) +#define SEI_CTRL_ENGINE_CTRL_WATCH_SHIFT (24U) +#define SEI_CTRL_ENGINE_CTRL_WATCH_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_WATCH_SHIFT) & SEI_CTRL_ENGINE_CTRL_WATCH_MASK) +#define SEI_CTRL_ENGINE_CTRL_WATCH_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_WATCH_MASK) >> SEI_CTRL_ENGINE_CTRL_WATCH_SHIFT) + +/* + * ARMING (RW) + * + * Wait for trigger before excuting + * 0: Execute on enable + * 1: Wait trigger before exection after enabled + */ +#define SEI_CTRL_ENGINE_CTRL_ARMING_MASK (0x10000UL) +#define SEI_CTRL_ENGINE_CTRL_ARMING_SHIFT (16U) +#define SEI_CTRL_ENGINE_CTRL_ARMING_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_ARMING_SHIFT) & SEI_CTRL_ENGINE_CTRL_ARMING_MASK) +#define SEI_CTRL_ENGINE_CTRL_ARMING_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_ARMING_MASK) >> SEI_CTRL_ENGINE_CTRL_ARMING_SHIFT) + +/* + * EXCEPT (RW) + * + * Explain timout as exception + * 0: when timeout, pointer move to next instruction + * 1: when timeout, pointer jump to timeout vector + */ +#define SEI_CTRL_ENGINE_CTRL_EXCEPT_MASK (0x100U) +#define SEI_CTRL_ENGINE_CTRL_EXCEPT_SHIFT (8U) +#define SEI_CTRL_ENGINE_CTRL_EXCEPT_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_EXCEPT_SHIFT) & SEI_CTRL_ENGINE_CTRL_EXCEPT_MASK) +#define SEI_CTRL_ENGINE_CTRL_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_EXCEPT_MASK) >> SEI_CTRL_ENGINE_CTRL_EXCEPT_SHIFT) + +/* + * REWIND (RW) + * + * Rewind execution pointer + * 0: run + * 1: clean status and rewind + */ +#define SEI_CTRL_ENGINE_CTRL_REWIND_MASK (0x10U) +#define SEI_CTRL_ENGINE_CTRL_REWIND_SHIFT (4U) +#define SEI_CTRL_ENGINE_CTRL_REWIND_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_REWIND_SHIFT) & SEI_CTRL_ENGINE_CTRL_REWIND_MASK) +#define SEI_CTRL_ENGINE_CTRL_REWIND_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_REWIND_MASK) >> SEI_CTRL_ENGINE_CTRL_REWIND_SHIFT) + +/* + * ENABLE (RW) + * + * Enable + * 0: disable + * 1: enable + */ +#define SEI_CTRL_ENGINE_CTRL_ENABLE_MASK (0x1U) +#define SEI_CTRL_ENGINE_CTRL_ENABLE_SHIFT (0U) +#define SEI_CTRL_ENGINE_CTRL_ENABLE_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_ENABLE_SHIFT) & SEI_CTRL_ENGINE_CTRL_ENABLE_MASK) +#define SEI_CTRL_ENGINE_CTRL_ENABLE_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_ENABLE_MASK) >> SEI_CTRL_ENGINE_CTRL_ENABLE_SHIFT) + +/* Bitfield definition for register of struct array CTRL: PTR_CFG */ +/* + * DAT_CDM (RW) + * + * Select DATA register to receive CDM bit in BiSSC slave mode + * 0: ignore + * 1: command + * 2: data register 2 + * 3: data register 3 + * ... + * 29:data register 29 + * 30: value 0 when send, ignore in receive + * 31: value1 when send, ignore in receive + */ +#define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_MASK (0x1F000000UL) +#define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SHIFT (24U) +#define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_MASK) +#define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SHIFT) + +/* + * DAT_BASE (RW) + * + * Bias for data register access, if calculated index bigger than 32, index will wrap around + * 0: real data index + * 1: access index is 1 greater than instruction address + * 2: access index is 2 greater than instruction address + * ... + * 31: access index is 31 greater than instruction address + */ +#define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK (0x1F0000UL) +#define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SHIFT (16U) +#define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK) +#define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SHIFT) + +/* + * POINTER_WDOG (RW) + * + * Pointer to the instruction that the program starts executing after the instruction timeout. The timeout is WDOG_TIME + */ +#define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK (0xFF00U) +#define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SHIFT (8U) +#define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK) +#define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SHIFT) + +/* + * POINTER_INIT (RW) + * + * Initial execute pointer + */ +#define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK (0xFFU) +#define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SHIFT (0U) +#define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK) +#define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SHIFT) + +/* Bitfield definition for register of struct array CTRL: WDG_CFG */ +/* + * WDOG_TIME (RW) + * + * Time out count for each instruction, counter in bit time. + */ +#define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_MASK (0xFFFFU) +#define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SHIFT (0U) +#define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SHIFT) & SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_MASK) +#define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_MASK) >> SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SHIFT) + +/* Bitfield definition for register of struct array CTRL: EXE_STA */ +/* + * TRIGERED (RO) + * + * Execution has been triggered + * 0: Execution not triggered + * 1: Execution triggered + */ +#define SEI_CTRL_ENGINE_EXE_STA_TRIGERED_MASK (0x100000UL) +#define SEI_CTRL_ENGINE_EXE_STA_TRIGERED_SHIFT (20U) +#define SEI_CTRL_ENGINE_EXE_STA_TRIGERED_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_TRIGERED_MASK) >> SEI_CTRL_ENGINE_EXE_STA_TRIGERED_SHIFT) + +/* + * ARMED (RO) + * + * Waiting for trigger for execution + * 0: Not in waiting status + * 1: In waiting status + */ +#define SEI_CTRL_ENGINE_EXE_STA_ARMED_MASK (0x10000UL) +#define SEI_CTRL_ENGINE_EXE_STA_ARMED_SHIFT (16U) +#define SEI_CTRL_ENGINE_EXE_STA_ARMED_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_ARMED_MASK) >> SEI_CTRL_ENGINE_EXE_STA_ARMED_SHIFT) + +/* + * EXPIRE (RO) + * + * Watchdog timer expired + * 0: Not expired + * 1: Expired + */ +#define SEI_CTRL_ENGINE_EXE_STA_EXPIRE_MASK (0x100U) +#define SEI_CTRL_ENGINE_EXE_STA_EXPIRE_SHIFT (8U) +#define SEI_CTRL_ENGINE_EXE_STA_EXPIRE_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_EXPIRE_MASK) >> SEI_CTRL_ENGINE_EXE_STA_EXPIRE_SHIFT) + +/* + * STALL (RO) + * + * Program finished + * 0: Program is executing + * 1: Program finished + */ +#define SEI_CTRL_ENGINE_EXE_STA_STALL_MASK (0x1U) +#define SEI_CTRL_ENGINE_EXE_STA_STALL_SHIFT (0U) +#define SEI_CTRL_ENGINE_EXE_STA_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_STALL_MASK) >> SEI_CTRL_ENGINE_EXE_STA_STALL_SHIFT) + +/* Bitfield definition for register of struct array CTRL: EXE_PTR */ +/* + * HALT_CNT (RO) + * + * Halt count in halt instrution + */ +#define SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_MASK (0x1F000000UL) +#define SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_SHIFT (24U) +#define SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_MASK) >> SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_SHIFT) + +/* + * BIT_CNT (RO) + * + * Bit count in send and receive instruction execution + */ +#define SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_MASK (0x1F0000UL) +#define SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_SHIFT (16U) +#define SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_MASK) >> SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_SHIFT) + +/* + * POINTER (RO) + * + * Current program pointer + */ +#define SEI_CTRL_ENGINE_EXE_PTR_POINTER_MASK (0xFFU) +#define SEI_CTRL_ENGINE_EXE_PTR_POINTER_SHIFT (0U) +#define SEI_CTRL_ENGINE_EXE_PTR_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_PTR_POINTER_MASK) >> SEI_CTRL_ENGINE_EXE_PTR_POINTER_SHIFT) + +/* Bitfield definition for register of struct array CTRL: EXE_INST */ +/* + * INST (RO) + * + * Current instruction + */ +#define SEI_CTRL_ENGINE_EXE_INST_INST_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_ENGINE_EXE_INST_INST_SHIFT (0U) +#define SEI_CTRL_ENGINE_EXE_INST_INST_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_INST_INST_MASK) >> SEI_CTRL_ENGINE_EXE_INST_INST_SHIFT) + +/* Bitfield definition for register of struct array CTRL: WDG_STA */ +/* + * WDOG_CNT (RO) + * + * Current watch dog counter value + */ +#define SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_MASK (0xFFFFU) +#define SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_SHIFT (0U) +#define SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_MASK) >> SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_SHIFT) + +/* Bitfield definition for register of struct array CTRL: CTRL */ +/* + * TRISMP (RW) + * + * Tipple sampe + * 0: sample 1 time for data transition + * 1: sample 3 times in receive and result in 2oo3 + */ +#define SEI_CTRL_XCVR_CTRL_TRISMP_MASK (0x1000U) +#define SEI_CTRL_XCVR_CTRL_TRISMP_SHIFT (12U) +#define SEI_CTRL_XCVR_CTRL_TRISMP_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_TRISMP_SHIFT) & SEI_CTRL_XCVR_CTRL_TRISMP_MASK) +#define SEI_CTRL_XCVR_CTRL_TRISMP_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_TRISMP_MASK) >> SEI_CTRL_XCVR_CTRL_TRISMP_SHIFT) + +/* + * PAR_CLR (WC) + * + * Clear parity error, this is a self clear bit + * 0: no effect + * 1: clear parity error + */ +#define SEI_CTRL_XCVR_CTRL_PAR_CLR_MASK (0x100U) +#define SEI_CTRL_XCVR_CTRL_PAR_CLR_SHIFT (8U) +#define SEI_CTRL_XCVR_CTRL_PAR_CLR_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_PAR_CLR_SHIFT) & SEI_CTRL_XCVR_CTRL_PAR_CLR_MASK) +#define SEI_CTRL_XCVR_CTRL_PAR_CLR_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_PAR_CLR_MASK) >> SEI_CTRL_XCVR_CTRL_PAR_CLR_SHIFT) + +/* + * RESTART (WC) + * + * Restart tranceiver, this is a self clear bit + * 0: no effect + * 1: reset tranceiver + */ +#define SEI_CTRL_XCVR_CTRL_RESTART_MASK (0x10U) +#define SEI_CTRL_XCVR_CTRL_RESTART_SHIFT (4U) +#define SEI_CTRL_XCVR_CTRL_RESTART_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_RESTART_SHIFT) & SEI_CTRL_XCVR_CTRL_RESTART_MASK) +#define SEI_CTRL_XCVR_CTRL_RESTART_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_RESTART_MASK) >> SEI_CTRL_XCVR_CTRL_RESTART_SHIFT) + +/* + * MODE (RW) + * + * Tranceiver mode + * 0: synchronous maaster + * 1: synchronous slave + * 2: asynchronous mode + * 3: asynchronous mode + */ +#define SEI_CTRL_XCVR_CTRL_MODE_MASK (0x3U) +#define SEI_CTRL_XCVR_CTRL_MODE_SHIFT (0U) +#define SEI_CTRL_XCVR_CTRL_MODE_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_MODE_SHIFT) & SEI_CTRL_XCVR_CTRL_MODE_MASK) +#define SEI_CTRL_XCVR_CTRL_MODE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_MODE_MASK) >> SEI_CTRL_XCVR_CTRL_MODE_SHIFT) + +/* Bitfield definition for register of struct array CTRL: TYPE_CFG */ +/* + * WAIT_LEN (RW) + * + * Number of extra stop bit for asynchronous mode + * 0: 1 bit + * 1: 2 bit + * ... + * 255: 256 bit + */ +#define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_MASK (0xFF000000UL) +#define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SHIFT (24U) +#define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_MASK) +#define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SHIFT) + +/* + * DATA_LEN (RW) + * + * Number of data bit for asynchronous mode + * 0: 1 bit + * 1: 2 bit + * ... + * 31: 32 bit + */ +#define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_MASK (0x1F0000UL) +#define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SHIFT (16U) +#define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_MASK) +#define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SHIFT) + +/* + * PAR_POL (RW) + * + * Polarity of parity for asynchronous mode + * 0: even + * 1: odd + */ +#define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_MASK (0x200U) +#define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SHIFT (9U) +#define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_MASK) +#define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SHIFT) + +/* + * PAR_EN (RW) + * + * enable parity check for asynchronous mode + * 0: disable + * 1: enable + */ +#define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_MASK (0x100U) +#define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SHIFT (8U) +#define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_MASK) +#define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SHIFT) + +/* + * DA_IDLEZ (RW) + * + * Idle state driver of data line + * 0: output + * 1: high-Z + */ +#define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_MASK (0x8U) +#define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SHIFT (3U) +#define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_MASK) +#define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SHIFT) + +/* + * CK_IDLEZ (RW) + * + * Idle state driver of clock line + * 0: output + * 1: high-Z + */ +#define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_MASK (0x4U) +#define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SHIFT (2U) +#define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_MASK) +#define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SHIFT) + +/* + * DA_IDLEV (RW) + * + * Idle state value of data line + * 0: data'0' + * 1: data'1' + */ +#define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_MASK (0x2U) +#define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SHIFT (1U) +#define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_MASK) +#define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SHIFT) + +/* + * CK_IDLEV (RW) + * + * Idle state value of clock line + * 0: data'0' + * 1: data'1' + */ +#define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_MASK (0x1U) +#define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SHIFT (0U) +#define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_MASK) +#define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SHIFT) + +/* Bitfield definition for register of struct array CTRL: BAUD_CFG */ +/* + * SYNC_POINT (RW) + * + * Baud synchronous time, minmum bit time + */ +#define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_MASK (0xFFFF0000UL) +#define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SHIFT (16U) +#define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SHIFT) & SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_MASK) +#define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_MASK) >> SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SHIFT) + +/* + * BAUD_DIV (RW) + * + * Baud rate, bit time in system clock cycle + */ +#define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_MASK (0xFFFFU) +#define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SHIFT (0U) +#define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SHIFT) & SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_MASK) +#define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_MASK) >> SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SHIFT) + +/* Bitfield definition for register of struct array CTRL: DATA_CFG */ +/* + * TXD_POINT (RW) + * + * data transmit point in system clcok cycle + */ +#define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK (0xFFFF0000UL) +#define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SHIFT (16U) +#define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SHIFT) & SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK) +#define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK) >> SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SHIFT) + +/* + * RXD_POINT (RW) + * + * data receive point in system clcok cycle + */ +#define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK (0xFFFFU) +#define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SHIFT (0U) +#define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SHIFT) & SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK) +#define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK) >> SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SHIFT) + +/* Bitfield definition for register of struct array CTRL: CLK_CFG */ +/* + * CK1_POINT (RW) + * + * clock point 1 in system clcok cycle + */ +#define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK (0xFFFF0000UL) +#define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SHIFT (16U) +#define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SHIFT) & SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK) +#define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK) >> SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SHIFT) + +/* + * CK0_POINT (RW) + * + * clock point 0 in system clcok cycle + */ +#define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK (0xFFFFU) +#define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SHIFT (0U) +#define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SHIFT) & SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK) +#define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK) >> SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SHIFT) + +/* Bitfield definition for register of struct array CTRL: PIN */ +/* + * OE_CK (RO) + * + * CK drive state + * 0: input + * 1: output + */ +#define SEI_CTRL_XCVR_PIN_OE_CK_MASK (0x4000000UL) +#define SEI_CTRL_XCVR_PIN_OE_CK_SHIFT (26U) +#define SEI_CTRL_XCVR_PIN_OE_CK_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_CK_MASK) >> SEI_CTRL_XCVR_PIN_OE_CK_SHIFT) + +/* + * DI_CK (RO) + * + * CK state + * 0: data 0 + * 1: data 1 + */ +#define SEI_CTRL_XCVR_PIN_DI_CK_MASK (0x2000000UL) +#define SEI_CTRL_XCVR_PIN_DI_CK_SHIFT (25U) +#define SEI_CTRL_XCVR_PIN_DI_CK_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_CK_MASK) >> SEI_CTRL_XCVR_PIN_DI_CK_SHIFT) + +/* + * DO_CK (RO) + * + * CK output + * 0: data 0 + * 1: data 1 + */ +#define SEI_CTRL_XCVR_PIN_DO_CK_MASK (0x1000000UL) +#define SEI_CTRL_XCVR_PIN_DO_CK_SHIFT (24U) +#define SEI_CTRL_XCVR_PIN_DO_CK_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_CK_MASK) >> SEI_CTRL_XCVR_PIN_DO_CK_SHIFT) + +/* + * OE_RX (RO) + * + * RX drive state + * 0: input + * 1: output + */ +#define SEI_CTRL_XCVR_PIN_OE_RX_MASK (0x40000UL) +#define SEI_CTRL_XCVR_PIN_OE_RX_SHIFT (18U) +#define SEI_CTRL_XCVR_PIN_OE_RX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_RX_MASK) >> SEI_CTRL_XCVR_PIN_OE_RX_SHIFT) + +/* + * DI_RX (RO) + * + * RX state + * 0: data 0 + * 1: data 1 + */ +#define SEI_CTRL_XCVR_PIN_DI_RX_MASK (0x20000UL) +#define SEI_CTRL_XCVR_PIN_DI_RX_SHIFT (17U) +#define SEI_CTRL_XCVR_PIN_DI_RX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_RX_MASK) >> SEI_CTRL_XCVR_PIN_DI_RX_SHIFT) + +/* + * DO_RX (RO) + * + * RX output + * 0: data 0 + * 1: data 1 + */ +#define SEI_CTRL_XCVR_PIN_DO_RX_MASK (0x10000UL) +#define SEI_CTRL_XCVR_PIN_DO_RX_SHIFT (16U) +#define SEI_CTRL_XCVR_PIN_DO_RX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_RX_MASK) >> SEI_CTRL_XCVR_PIN_DO_RX_SHIFT) + +/* + * OE_DE (RO) + * + * DE drive state + * 0: input + * 1: output + */ +#define SEI_CTRL_XCVR_PIN_OE_DE_MASK (0x400U) +#define SEI_CTRL_XCVR_PIN_OE_DE_SHIFT (10U) +#define SEI_CTRL_XCVR_PIN_OE_DE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_DE_MASK) >> SEI_CTRL_XCVR_PIN_OE_DE_SHIFT) + +/* + * DI_DE (RO) + * + * DE state + * 0: data 0 + * 1: data 1 + */ +#define SEI_CTRL_XCVR_PIN_DI_DE_MASK (0x200U) +#define SEI_CTRL_XCVR_PIN_DI_DE_SHIFT (9U) +#define SEI_CTRL_XCVR_PIN_DI_DE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_DE_MASK) >> SEI_CTRL_XCVR_PIN_DI_DE_SHIFT) + +/* + * DO_DE (RO) + * + * DE output + * 0: data 0 + * 1: data 1 + */ +#define SEI_CTRL_XCVR_PIN_DO_DE_MASK (0x100U) +#define SEI_CTRL_XCVR_PIN_DO_DE_SHIFT (8U) +#define SEI_CTRL_XCVR_PIN_DO_DE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_DE_MASK) >> SEI_CTRL_XCVR_PIN_DO_DE_SHIFT) + +/* + * OE_TX (RO) + * + * TX drive state + * 0: input + * 1: output + */ +#define SEI_CTRL_XCVR_PIN_OE_TX_MASK (0x4U) +#define SEI_CTRL_XCVR_PIN_OE_TX_SHIFT (2U) +#define SEI_CTRL_XCVR_PIN_OE_TX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_TX_MASK) >> SEI_CTRL_XCVR_PIN_OE_TX_SHIFT) + +/* + * DI_TX (RO) + * + * TX state + * 0: data 0 + * 1: data 1 + */ +#define SEI_CTRL_XCVR_PIN_DI_TX_MASK (0x2U) +#define SEI_CTRL_XCVR_PIN_DI_TX_SHIFT (1U) +#define SEI_CTRL_XCVR_PIN_DI_TX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_TX_MASK) >> SEI_CTRL_XCVR_PIN_DI_TX_SHIFT) + +/* + * DO_TX (RO) + * + * TX output + * 0: data 0 + * 1: data 1 + */ +#define SEI_CTRL_XCVR_PIN_DO_TX_MASK (0x1U) +#define SEI_CTRL_XCVR_PIN_DO_TX_SHIFT (0U) +#define SEI_CTRL_XCVR_PIN_DO_TX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_TX_MASK) >> SEI_CTRL_XCVR_PIN_DO_TX_SHIFT) + +/* Bitfield definition for register of struct array CTRL: STATE */ +/* + * RECV_STATE (RO) + * + * FSM of asynchronous receive + */ +#define SEI_CTRL_XCVR_STATE_RECV_STATE_MASK (0x7000000UL) +#define SEI_CTRL_XCVR_STATE_RECV_STATE_SHIFT (24U) +#define SEI_CTRL_XCVR_STATE_RECV_STATE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_STATE_RECV_STATE_MASK) >> SEI_CTRL_XCVR_STATE_RECV_STATE_SHIFT) + +/* + * SEND_STATE (RO) + * + * FSM of asynchronous transmit + */ +#define SEI_CTRL_XCVR_STATE_SEND_STATE_MASK (0x70000UL) +#define SEI_CTRL_XCVR_STATE_SEND_STATE_SHIFT (16U) +#define SEI_CTRL_XCVR_STATE_SEND_STATE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_STATE_SEND_STATE_MASK) >> SEI_CTRL_XCVR_STATE_SEND_STATE_SHIFT) + +/* Bitfield definition for register of struct array CTRL: IN_CFG */ +/* + * PRD_EN (RW) + * + * Enable period trigger (tigger 2) + * 0: periodical trigger disabled + * 1: periodical trigger enabled + */ +#define SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK (0x800000UL) +#define SEI_CTRL_TRG_IN_CFG_PRD_EN_SHIFT (23U) +#define SEI_CTRL_TRG_IN_CFG_PRD_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_PRD_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK) +#define SEI_CTRL_TRG_IN_CFG_PRD_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_PRD_EN_SHIFT) + +/* + * SYNC_SEL (RW) + * + * Synchronize sigal selection (tigger 2) + * 0: trigger in 0 + * 1: trigger in 1 + * ... + * 7: trigger in 7 + */ +#define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_MASK (0x70000UL) +#define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SHIFT (16U) +#define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_SYNC_SEL_MASK) +#define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_SYNC_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SHIFT) + +/* + * IN1_EN (RW) + * + * Enable trigger 1 + * 0: disable trigger 1 + * 1: enable trigger 1 + */ +#define SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK (0x8000U) +#define SEI_CTRL_TRG_IN_CFG_IN1_EN_SHIFT (15U) +#define SEI_CTRL_TRG_IN_CFG_IN1_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN1_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK) +#define SEI_CTRL_TRG_IN_CFG_IN1_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_IN1_EN_SHIFT) + +/* + * IN1_SEL (RW) + * + * Trigger 1 sigal selection + * 0: trigger in 0 + * 1: trigger in 1 + * ... + * 7: trigger in 7 + */ +#define SEI_CTRL_TRG_IN_CFG_IN1_SEL_MASK (0x700U) +#define SEI_CTRL_TRG_IN_CFG_IN1_SEL_SHIFT (8U) +#define SEI_CTRL_TRG_IN_CFG_IN1_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN1_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN1_SEL_MASK) +#define SEI_CTRL_TRG_IN_CFG_IN1_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN1_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_IN1_SEL_SHIFT) + +/* + * IN0_EN (RW) + * + * Enable trigger 0 + * 0: disable trigger 1 + * 1: enable trigger 1 + */ +#define SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK (0x80U) +#define SEI_CTRL_TRG_IN_CFG_IN0_EN_SHIFT (7U) +#define SEI_CTRL_TRG_IN_CFG_IN0_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN0_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK) +#define SEI_CTRL_TRG_IN_CFG_IN0_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_IN0_EN_SHIFT) + +/* + * IN0_SEL (RW) + * + * Trigger 0 sigal selection + * 0: trigger in 0 + * 1: trigger in 1 + * ... + * 7: trigger in 7 + */ +#define SEI_CTRL_TRG_IN_CFG_IN0_SEL_MASK (0x7U) +#define SEI_CTRL_TRG_IN_CFG_IN0_SEL_SHIFT (0U) +#define SEI_CTRL_TRG_IN_CFG_IN0_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN0_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN0_SEL_MASK) +#define SEI_CTRL_TRG_IN_CFG_IN0_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN0_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_IN0_SEL_SHIFT) + +/* Bitfield definition for register of struct array CTRL: SW */ +/* + * SOFT (WC) + * + * Software trigger (tigger 3). this bit is self-clear + * 0: trigger source disabled + * 1: trigger source enabled + */ +#define SEI_CTRL_TRG_SW_SOFT_MASK (0x1U) +#define SEI_CTRL_TRG_SW_SOFT_SHIFT (0U) +#define SEI_CTRL_TRG_SW_SOFT_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_SW_SOFT_SHIFT) & SEI_CTRL_TRG_SW_SOFT_MASK) +#define SEI_CTRL_TRG_SW_SOFT_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_SW_SOFT_MASK) >> SEI_CTRL_TRG_SW_SOFT_SHIFT) + +/* Bitfield definition for register of struct array CTRL: PRD_CFG */ +/* + * ARMING (RW) + * + * Wait for trigger synchronous before trigger + * 0: Trigger directly + * 1: Wait trigger source before period trigger + */ +#define SEI_CTRL_TRG_PRD_CFG_ARMING_MASK (0x10000UL) +#define SEI_CTRL_TRG_PRD_CFG_ARMING_SHIFT (16U) +#define SEI_CTRL_TRG_PRD_CFG_ARMING_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_PRD_CFG_ARMING_SHIFT) & SEI_CTRL_TRG_PRD_CFG_ARMING_MASK) +#define SEI_CTRL_TRG_PRD_CFG_ARMING_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_CFG_ARMING_MASK) >> SEI_CTRL_TRG_PRD_CFG_ARMING_SHIFT) + +/* + * SYNC (RW) + * + * Synchronous + * 0: Not synchronous + * 1: Synchronous every trigger source + */ +#define SEI_CTRL_TRG_PRD_CFG_SYNC_MASK (0x1U) +#define SEI_CTRL_TRG_PRD_CFG_SYNC_SHIFT (0U) +#define SEI_CTRL_TRG_PRD_CFG_SYNC_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_PRD_CFG_SYNC_SHIFT) & SEI_CTRL_TRG_PRD_CFG_SYNC_MASK) +#define SEI_CTRL_TRG_PRD_CFG_SYNC_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_CFG_SYNC_MASK) >> SEI_CTRL_TRG_PRD_CFG_SYNC_SHIFT) + +/* Bitfield definition for register of struct array CTRL: PRD */ +/* + * PERIOD (RW) + * + * Trigger period + */ +#define SEI_CTRL_TRG_PRD_PERIOD_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_TRG_PRD_PERIOD_SHIFT (0U) +#define SEI_CTRL_TRG_PRD_PERIOD_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_PRD_PERIOD_SHIFT) & SEI_CTRL_TRG_PRD_PERIOD_MASK) +#define SEI_CTRL_TRG_PRD_PERIOD_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_PERIOD_MASK) >> SEI_CTRL_TRG_PRD_PERIOD_SHIFT) + +/* Bitfield definition for register of struct array CTRL: OUT_CFG */ +/* + * OUT3_EN (RW) + * + * Enable trigger 3 + * 0: disable trigger 3 + * 1: enable trigger 3 + */ +#define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK (0x80000000UL) +#define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SHIFT (31U) +#define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK) +#define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SHIFT) + +/* + * OUT3_SEL (RW) + * + * Trigger 3 sigal selection + * 0: trigger out 0 + * 1: trigger out 1 + * ... + * 7: trigger out 7 + */ +#define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK (0x7000000UL) +#define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SHIFT (24U) +#define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK) +#define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SHIFT) + +/* + * OUT2_EN (RW) + * + * Enable trigger 2 + * 0: disable trigger 2 + * 1: enable trigger 2 + */ +#define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK (0x800000UL) +#define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SHIFT (23U) +#define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK) +#define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SHIFT) + +/* + * OUT2_SEL (RW) + * + * Trigger 2 sigal selection + * 0: trigger out 0 + * 1: trigger out 1 + * ... + * 7: trigger out 7 + */ +#define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK (0x70000UL) +#define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SHIFT (16U) +#define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK) +#define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SHIFT) + +/* + * OUT1_EN (RW) + * + * Enable trigger 1 + * 0: disable trigger 1 + * 1: enable trigger 1 + */ +#define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK (0x8000U) +#define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SHIFT (15U) +#define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK) +#define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SHIFT) + +/* + * OUT1_SEL (RW) + * + * Trigger 1 sigal selection + * 0: trigger out 0 + * 1: trigger out 1 + * ... + * 7: trigger out 7 + */ +#define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK (0x700U) +#define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SHIFT (8U) +#define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK) +#define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SHIFT) + +/* + * OUT0_EN (RW) + * + * Enable trigger 0 + * 0: disable trigger 1 + * 1: enable trigger 1 + */ +#define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK (0x80U) +#define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SHIFT (7U) +#define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK) +#define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SHIFT) + +/* + * OUT0_SEL (RW) + * + * Trigger 0 sigal selection + * 0: trigger out 0 + * 1: trigger out 1 + * ... + * 7: trigger out 7 + */ +#define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK (0x7U) +#define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SHIFT (0U) +#define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK) +#define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SHIFT) + +/* Bitfield definition for register of struct array CTRL: PRD_STS */ +/* + * TRIGERED (RO) + * + * Period has been triggered + * 0: Not triggered + * 1: Triggered + */ +#define SEI_CTRL_TRG_PRD_STS_TRIGERED_MASK (0x100000UL) +#define SEI_CTRL_TRG_PRD_STS_TRIGERED_SHIFT (20U) +#define SEI_CTRL_TRG_PRD_STS_TRIGERED_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_STS_TRIGERED_MASK) >> SEI_CTRL_TRG_PRD_STS_TRIGERED_SHIFT) + +/* + * ARMED (RO) + * + * Waiting for trigger + * 0: Not in waiting status + * 1: In waiting status + */ +#define SEI_CTRL_TRG_PRD_STS_ARMED_MASK (0x10000UL) +#define SEI_CTRL_TRG_PRD_STS_ARMED_SHIFT (16U) +#define SEI_CTRL_TRG_PRD_STS_ARMED_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_STS_ARMED_MASK) >> SEI_CTRL_TRG_PRD_STS_ARMED_SHIFT) + +/* Bitfield definition for register of struct array CTRL: PRD_CNT */ +/* + * PERIOD_CNT (RO) + * + * Trigger period counter + */ +#define SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_SHIFT (0U) +#define SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_MASK) >> SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_SHIFT) + +/* Bitfield definition for register of struct array CTRL: 0 */ +/* + * CMD_TRIGGER0 (RW) + * + * Trigger command + */ +#define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SHIFT (0U) +#define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SHIFT) & SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_MASK) +#define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_MASK) >> SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SHIFT) + +/* Bitfield definition for register of struct array CTRL: 0 */ +/* + * TRIGGER0_TIME (RO) + * + * Trigger time + */ +#define SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_SHIFT (0U) +#define SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_MASK) >> SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_SHIFT) + +/* Bitfield definition for register of struct array CTRL: MODE */ +/* + * WLEN (RW) + * + * word length + * 0: 1 bit + * 1: 2 bit + * ... + * 31: 32 bit + */ +#define SEI_CTRL_CMD_MODE_WLEN_MASK (0x1F0000UL) +#define SEI_CTRL_CMD_MODE_WLEN_SHIFT (16U) +#define SEI_CTRL_CMD_MODE_WLEN_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_WLEN_SHIFT) & SEI_CTRL_CMD_MODE_WLEN_MASK) +#define SEI_CTRL_CMD_MODE_WLEN_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_WLEN_MASK) >> SEI_CTRL_CMD_MODE_WLEN_SHIFT) + +/* + * WORDER (RW) + * + * word order + * 0: sample as bit order + * 1: different from bit order + */ +#define SEI_CTRL_CMD_MODE_WORDER_MASK (0x800U) +#define SEI_CTRL_CMD_MODE_WORDER_SHIFT (11U) +#define SEI_CTRL_CMD_MODE_WORDER_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_WORDER_SHIFT) & SEI_CTRL_CMD_MODE_WORDER_MASK) +#define SEI_CTRL_CMD_MODE_WORDER_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_WORDER_MASK) >> SEI_CTRL_CMD_MODE_WORDER_SHIFT) + +/* + * BORDER (RW) + * + * bit order + * 0: LSB first + * 1: MSB first + */ +#define SEI_CTRL_CMD_MODE_BORDER_MASK (0x400U) +#define SEI_CTRL_CMD_MODE_BORDER_SHIFT (10U) +#define SEI_CTRL_CMD_MODE_BORDER_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_BORDER_SHIFT) & SEI_CTRL_CMD_MODE_BORDER_MASK) +#define SEI_CTRL_CMD_MODE_BORDER_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_BORDER_MASK) >> SEI_CTRL_CMD_MODE_BORDER_SHIFT) + +/* + * SIGNED (RW) + * + * Signed + * 0: unsigned value + * 1: signed value + */ +#define SEI_CTRL_CMD_MODE_SIGNED_MASK (0x200U) +#define SEI_CTRL_CMD_MODE_SIGNED_SHIFT (9U) +#define SEI_CTRL_CMD_MODE_SIGNED_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_SIGNED_SHIFT) & SEI_CTRL_CMD_MODE_SIGNED_MASK) +#define SEI_CTRL_CMD_MODE_SIGNED_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_SIGNED_MASK) >> SEI_CTRL_CMD_MODE_SIGNED_SHIFT) + +/* + * REWIND (WC) + * + * Write 1 to rewind read/write pointer, this is a self clear bit + */ +#define SEI_CTRL_CMD_MODE_REWIND_MASK (0x100U) +#define SEI_CTRL_CMD_MODE_REWIND_SHIFT (8U) +#define SEI_CTRL_CMD_MODE_REWIND_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_REWIND_SHIFT) & SEI_CTRL_CMD_MODE_REWIND_MASK) +#define SEI_CTRL_CMD_MODE_REWIND_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_REWIND_MASK) >> SEI_CTRL_CMD_MODE_REWIND_SHIFT) + +/* + * MODE (RW) + * + * Data mode + * 0: data mode + * 1: check mode + * 2: CRC mode + */ +#define SEI_CTRL_CMD_MODE_MODE_MASK (0x3U) +#define SEI_CTRL_CMD_MODE_MODE_SHIFT (0U) +#define SEI_CTRL_CMD_MODE_MODE_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_MODE_SHIFT) & SEI_CTRL_CMD_MODE_MODE_MASK) +#define SEI_CTRL_CMD_MODE_MODE_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_MODE_MASK) >> SEI_CTRL_CMD_MODE_MODE_SHIFT) + +/* Bitfield definition for register of struct array CTRL: IDX */ +/* + * LAST_BIT (RW) + * + * Last bit index for tranceive + */ +#define SEI_CTRL_CMD_IDX_LAST_BIT_MASK (0x1F000000UL) +#define SEI_CTRL_CMD_IDX_LAST_BIT_SHIFT (24U) +#define SEI_CTRL_CMD_IDX_LAST_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_LAST_BIT_SHIFT) & SEI_CTRL_CMD_IDX_LAST_BIT_MASK) +#define SEI_CTRL_CMD_IDX_LAST_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_LAST_BIT_MASK) >> SEI_CTRL_CMD_IDX_LAST_BIT_SHIFT) + +/* + * FIRST_BIT (RW) + * + * First bit index for tranceive + */ +#define SEI_CTRL_CMD_IDX_FIRST_BIT_MASK (0x1F0000UL) +#define SEI_CTRL_CMD_IDX_FIRST_BIT_SHIFT (16U) +#define SEI_CTRL_CMD_IDX_FIRST_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_FIRST_BIT_SHIFT) & SEI_CTRL_CMD_IDX_FIRST_BIT_MASK) +#define SEI_CTRL_CMD_IDX_FIRST_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_FIRST_BIT_MASK) >> SEI_CTRL_CMD_IDX_FIRST_BIT_SHIFT) + +/* + * MAX_BIT (RW) + * + * Highest bit index + */ +#define SEI_CTRL_CMD_IDX_MAX_BIT_MASK (0x1F00U) +#define SEI_CTRL_CMD_IDX_MAX_BIT_SHIFT (8U) +#define SEI_CTRL_CMD_IDX_MAX_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_MAX_BIT_SHIFT) & SEI_CTRL_CMD_IDX_MAX_BIT_MASK) +#define SEI_CTRL_CMD_IDX_MAX_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_MAX_BIT_MASK) >> SEI_CTRL_CMD_IDX_MAX_BIT_SHIFT) + +/* + * MIN_BIT (RW) + * + * Lowest bit index + */ +#define SEI_CTRL_CMD_IDX_MIN_BIT_MASK (0x1FU) +#define SEI_CTRL_CMD_IDX_MIN_BIT_SHIFT (0U) +#define SEI_CTRL_CMD_IDX_MIN_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_MIN_BIT_SHIFT) & SEI_CTRL_CMD_IDX_MIN_BIT_MASK) +#define SEI_CTRL_CMD_IDX_MIN_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_MIN_BIT_MASK) >> SEI_CTRL_CMD_IDX_MIN_BIT_SHIFT) + +/* Bitfield definition for register of struct array CTRL: GOLD */ +/* + * GOLD_VALUE (RW) + * + * Gold value for check mode + */ +#define SEI_CTRL_CMD_GOLD_GOLD_VALUE_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_CMD_GOLD_GOLD_VALUE_SHIFT (0U) +#define SEI_CTRL_CMD_GOLD_GOLD_VALUE_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_GOLD_GOLD_VALUE_SHIFT) & SEI_CTRL_CMD_GOLD_GOLD_VALUE_MASK) +#define SEI_CTRL_CMD_GOLD_GOLD_VALUE_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_GOLD_GOLD_VALUE_MASK) >> SEI_CTRL_CMD_GOLD_GOLD_VALUE_SHIFT) + +/* Bitfield definition for register of struct array CTRL: CRCINIT */ +/* + * CRC_INIT (RW) + * + * CRC initial value + */ +#define SEI_CTRL_CMD_CRCINIT_CRC_INIT_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_CMD_CRCINIT_CRC_INIT_SHIFT (0U) +#define SEI_CTRL_CMD_CRCINIT_CRC_INIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_CRCINIT_CRC_INIT_SHIFT) & SEI_CTRL_CMD_CRCINIT_CRC_INIT_MASK) +#define SEI_CTRL_CMD_CRCINIT_CRC_INIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_CRCINIT_CRC_INIT_MASK) >> SEI_CTRL_CMD_CRCINIT_CRC_INIT_SHIFT) + +/* Bitfield definition for register of struct array CTRL: CRCPOLY */ +/* + * CRC_POLY (RW) + * + * CRC polymonial + */ +#define SEI_CTRL_CMD_CRCPOLY_CRC_POLY_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_CMD_CRCPOLY_CRC_POLY_SHIFT (0U) +#define SEI_CTRL_CMD_CRCPOLY_CRC_POLY_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_CRCPOLY_CRC_POLY_SHIFT) & SEI_CTRL_CMD_CRCPOLY_CRC_POLY_MASK) +#define SEI_CTRL_CMD_CRCPOLY_CRC_POLY_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_CRCPOLY_CRC_POLY_MASK) >> SEI_CTRL_CMD_CRCPOLY_CRC_POLY_SHIFT) + +/* Bitfield definition for register of struct array CTRL: CMD */ +/* + * DATA (RW) + * + * DATA + */ +#define SEI_CTRL_CMD_CMD_DATA_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_CMD_CMD_DATA_SHIFT (0U) +#define SEI_CTRL_CMD_CMD_DATA_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_CMD_DATA_SHIFT) & SEI_CTRL_CMD_CMD_DATA_MASK) +#define SEI_CTRL_CMD_CMD_DATA_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_CMD_DATA_MASK) >> SEI_CTRL_CMD_CMD_DATA_SHIFT) + +/* Bitfield definition for register of struct array CTRL: SET */ +/* + * DATA_SET (RW) + * + * DATA bit set + */ +#define SEI_CTRL_CMD_SET_DATA_SET_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_CMD_SET_DATA_SET_SHIFT (0U) +#define SEI_CTRL_CMD_SET_DATA_SET_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_SET_DATA_SET_SHIFT) & SEI_CTRL_CMD_SET_DATA_SET_MASK) +#define SEI_CTRL_CMD_SET_DATA_SET_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_SET_DATA_SET_MASK) >> SEI_CTRL_CMD_SET_DATA_SET_SHIFT) + +/* Bitfield definition for register of struct array CTRL: CLR */ +/* + * DATA_CLR (RW) + * + * DATA bit clear + */ +#define SEI_CTRL_CMD_CLR_DATA_CLR_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_CMD_CLR_DATA_CLR_SHIFT (0U) +#define SEI_CTRL_CMD_CLR_DATA_CLR_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_CLR_DATA_CLR_SHIFT) & SEI_CTRL_CMD_CLR_DATA_CLR_MASK) +#define SEI_CTRL_CMD_CLR_DATA_CLR_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_CLR_DATA_CLR_MASK) >> SEI_CTRL_CMD_CLR_DATA_CLR_SHIFT) + +/* Bitfield definition for register of struct array CTRL: INV */ +/* + * DATA_TGL (RW) + * + * DATA bit toggle + */ +#define SEI_CTRL_CMD_INV_DATA_TGL_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_CMD_INV_DATA_TGL_SHIFT (0U) +#define SEI_CTRL_CMD_INV_DATA_TGL_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_INV_DATA_TGL_SHIFT) & SEI_CTRL_CMD_INV_DATA_TGL_MASK) +#define SEI_CTRL_CMD_INV_DATA_TGL_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_INV_DATA_TGL_MASK) >> SEI_CTRL_CMD_INV_DATA_TGL_SHIFT) + +/* Bitfield definition for register of struct array CTRL: IN */ +/* + * DATA_IN (RO) + * + * Commad input + */ +#define SEI_CTRL_CMD_IN_DATA_IN_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_CMD_IN_DATA_IN_SHIFT (0U) +#define SEI_CTRL_CMD_IN_DATA_IN_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IN_DATA_IN_MASK) >> SEI_CTRL_CMD_IN_DATA_IN_SHIFT) + +/* Bitfield definition for register of struct array CTRL: OUT */ +/* + * DATA_OUT (RO) + * + * Command output + */ +#define SEI_CTRL_CMD_OUT_DATA_OUT_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_CMD_OUT_DATA_OUT_SHIFT (0U) +#define SEI_CTRL_CMD_OUT_DATA_OUT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_OUT_DATA_OUT_MASK) >> SEI_CTRL_CMD_OUT_DATA_OUT_SHIFT) + +/* Bitfield definition for register of struct array CTRL: STS */ +/* + * CRC_IDX (RO) + * + * CRC index + */ +#define SEI_CTRL_CMD_STS_CRC_IDX_MASK (0x1F000000UL) +#define SEI_CTRL_CMD_STS_CRC_IDX_SHIFT (24U) +#define SEI_CTRL_CMD_STS_CRC_IDX_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_STS_CRC_IDX_MASK) >> SEI_CTRL_CMD_STS_CRC_IDX_SHIFT) + +/* + * WORD_IDX (RO) + * + * Word index + */ +#define SEI_CTRL_CMD_STS_WORD_IDX_MASK (0x1F0000UL) +#define SEI_CTRL_CMD_STS_WORD_IDX_SHIFT (16U) +#define SEI_CTRL_CMD_STS_WORD_IDX_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_STS_WORD_IDX_MASK) >> SEI_CTRL_CMD_STS_WORD_IDX_SHIFT) + +/* + * WORD_CNT (RO) + * + * Word counter + */ +#define SEI_CTRL_CMD_STS_WORD_CNT_MASK (0x1F00U) +#define SEI_CTRL_CMD_STS_WORD_CNT_SHIFT (8U) +#define SEI_CTRL_CMD_STS_WORD_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_STS_WORD_CNT_MASK) >> SEI_CTRL_CMD_STS_WORD_CNT_SHIFT) + +/* + * BIT_IDX (RO) + * + * Bit index + */ +#define SEI_CTRL_CMD_STS_BIT_IDX_MASK (0x1FU) +#define SEI_CTRL_CMD_STS_BIT_IDX_SHIFT (0U) +#define SEI_CTRL_CMD_STS_BIT_IDX_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_STS_BIT_IDX_MASK) >> SEI_CTRL_CMD_STS_BIT_IDX_SHIFT) + +/* Bitfield definition for register of struct array CTRL: MIN */ +/* + * CMD_MIN (RW) + * + * minimum command value + */ +#define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SHIFT (0U) +#define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SHIFT) & SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_MASK) +#define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_MASK) >> SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SHIFT) + +/* Bitfield definition for register of struct array CTRL: MAX */ +/* + * CMD_MAX (RW) + * + * maximum command value + */ +#define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SHIFT (0U) +#define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SHIFT) & SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_MASK) +#define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_MASK) >> SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SHIFT) + +/* Bitfield definition for register of struct array CTRL: MSK */ +/* + * CMD_MASK (RW) + * + * compare mask + */ +#define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SHIFT (0U) +#define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SHIFT) & SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_MASK) +#define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_MASK) >> SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SHIFT) + +/* Bitfield definition for register of struct array CTRL: PTA */ +/* + * PTR3 (RW) + * + * pointer3 + */ +#define SEI_CTRL_CMD_TABLE_PTA_PTR3_MASK (0xFF000000UL) +#define SEI_CTRL_CMD_TABLE_PTA_PTR3_SHIFT (24U) +#define SEI_CTRL_CMD_TABLE_PTA_PTR3_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR3_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR3_MASK) +#define SEI_CTRL_CMD_TABLE_PTA_PTR3_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR3_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR3_SHIFT) + +/* + * PTR2 (RW) + * + * pointer2 + */ +#define SEI_CTRL_CMD_TABLE_PTA_PTR2_MASK (0xFF0000UL) +#define SEI_CTRL_CMD_TABLE_PTA_PTR2_SHIFT (16U) +#define SEI_CTRL_CMD_TABLE_PTA_PTR2_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR2_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR2_MASK) +#define SEI_CTRL_CMD_TABLE_PTA_PTR2_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR2_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR2_SHIFT) + +/* + * PTR1 (RW) + * + * pointer1 + */ +#define SEI_CTRL_CMD_TABLE_PTA_PTR1_MASK (0xFF00U) +#define SEI_CTRL_CMD_TABLE_PTA_PTR1_SHIFT (8U) +#define SEI_CTRL_CMD_TABLE_PTA_PTR1_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR1_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR1_MASK) +#define SEI_CTRL_CMD_TABLE_PTA_PTR1_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR1_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR1_SHIFT) + +/* + * PTR0 (RW) + * + * pointer0 + */ +#define SEI_CTRL_CMD_TABLE_PTA_PTR0_MASK (0xFFU) +#define SEI_CTRL_CMD_TABLE_PTA_PTR0_SHIFT (0U) +#define SEI_CTRL_CMD_TABLE_PTA_PTR0_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR0_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR0_MASK) +#define SEI_CTRL_CMD_TABLE_PTA_PTR0_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR0_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR0_SHIFT) + +/* Bitfield definition for register of struct array CTRL: PTB */ +/* + * PTR7 (RW) + * + * pointer7 + */ +#define SEI_CTRL_CMD_TABLE_PTB_PTR7_MASK (0xFF000000UL) +#define SEI_CTRL_CMD_TABLE_PTB_PTR7_SHIFT (24U) +#define SEI_CTRL_CMD_TABLE_PTB_PTR7_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR7_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR7_MASK) +#define SEI_CTRL_CMD_TABLE_PTB_PTR7_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR7_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR7_SHIFT) + +/* + * PTR6 (RW) + * + * pointer6 + */ +#define SEI_CTRL_CMD_TABLE_PTB_PTR6_MASK (0xFF0000UL) +#define SEI_CTRL_CMD_TABLE_PTB_PTR6_SHIFT (16U) +#define SEI_CTRL_CMD_TABLE_PTB_PTR6_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR6_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR6_MASK) +#define SEI_CTRL_CMD_TABLE_PTB_PTR6_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR6_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR6_SHIFT) + +/* + * PTR5 (RW) + * + * pointer5 + */ +#define SEI_CTRL_CMD_TABLE_PTB_PTR5_MASK (0xFF00U) +#define SEI_CTRL_CMD_TABLE_PTB_PTR5_SHIFT (8U) +#define SEI_CTRL_CMD_TABLE_PTB_PTR5_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR5_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR5_MASK) +#define SEI_CTRL_CMD_TABLE_PTB_PTR5_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR5_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR5_SHIFT) + +/* + * PTR4 (RW) + * + * pointer4 + */ +#define SEI_CTRL_CMD_TABLE_PTB_PTR4_MASK (0xFFU) +#define SEI_CTRL_CMD_TABLE_PTB_PTR4_SHIFT (0U) +#define SEI_CTRL_CMD_TABLE_PTB_PTR4_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR4_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR4_MASK) +#define SEI_CTRL_CMD_TABLE_PTB_PTR4_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR4_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR4_SHIFT) + +/* Bitfield definition for register of struct array CTRL: PTC */ +/* + * PTR11 (RW) + * + * pointer11 + */ +#define SEI_CTRL_CMD_TABLE_PTC_PTR11_MASK (0xFF000000UL) +#define SEI_CTRL_CMD_TABLE_PTC_PTR11_SHIFT (24U) +#define SEI_CTRL_CMD_TABLE_PTC_PTR11_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTC_PTR11_SHIFT) & SEI_CTRL_CMD_TABLE_PTC_PTR11_MASK) +#define SEI_CTRL_CMD_TABLE_PTC_PTR11_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTC_PTR11_MASK) >> SEI_CTRL_CMD_TABLE_PTC_PTR11_SHIFT) + +/* + * PTR10 (RW) + * + * pointer10 + */ +#define SEI_CTRL_CMD_TABLE_PTC_PTR10_MASK (0xFF0000UL) +#define SEI_CTRL_CMD_TABLE_PTC_PTR10_SHIFT (16U) +#define SEI_CTRL_CMD_TABLE_PTC_PTR10_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTC_PTR10_SHIFT) & SEI_CTRL_CMD_TABLE_PTC_PTR10_MASK) +#define SEI_CTRL_CMD_TABLE_PTC_PTR10_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTC_PTR10_MASK) >> SEI_CTRL_CMD_TABLE_PTC_PTR10_SHIFT) + +/* + * PTR9 (RW) + * + * pointer9 + */ +#define SEI_CTRL_CMD_TABLE_PTC_PTR9_MASK (0xFF00U) +#define SEI_CTRL_CMD_TABLE_PTC_PTR9_SHIFT (8U) +#define SEI_CTRL_CMD_TABLE_PTC_PTR9_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTC_PTR9_SHIFT) & SEI_CTRL_CMD_TABLE_PTC_PTR9_MASK) +#define SEI_CTRL_CMD_TABLE_PTC_PTR9_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTC_PTR9_MASK) >> SEI_CTRL_CMD_TABLE_PTC_PTR9_SHIFT) + +/* + * PTR8 (RW) + * + * pointer8 + */ +#define SEI_CTRL_CMD_TABLE_PTC_PTR8_MASK (0xFFU) +#define SEI_CTRL_CMD_TABLE_PTC_PTR8_SHIFT (0U) +#define SEI_CTRL_CMD_TABLE_PTC_PTR8_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTC_PTR8_SHIFT) & SEI_CTRL_CMD_TABLE_PTC_PTR8_MASK) +#define SEI_CTRL_CMD_TABLE_PTC_PTR8_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTC_PTR8_MASK) >> SEI_CTRL_CMD_TABLE_PTC_PTR8_SHIFT) + +/* Bitfield definition for register of struct array CTRL: PTD */ +/* + * PTR15 (RW) + * + * pointer15 + */ +#define SEI_CTRL_CMD_TABLE_PTD_PTR15_MASK (0xFF000000UL) +#define SEI_CTRL_CMD_TABLE_PTD_PTR15_SHIFT (24U) +#define SEI_CTRL_CMD_TABLE_PTD_PTR15_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTD_PTR15_SHIFT) & SEI_CTRL_CMD_TABLE_PTD_PTR15_MASK) +#define SEI_CTRL_CMD_TABLE_PTD_PTR15_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTD_PTR15_MASK) >> SEI_CTRL_CMD_TABLE_PTD_PTR15_SHIFT) + +/* + * PTR14 (RW) + * + * pointer14 + */ +#define SEI_CTRL_CMD_TABLE_PTD_PTR14_MASK (0xFF0000UL) +#define SEI_CTRL_CMD_TABLE_PTD_PTR14_SHIFT (16U) +#define SEI_CTRL_CMD_TABLE_PTD_PTR14_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTD_PTR14_SHIFT) & SEI_CTRL_CMD_TABLE_PTD_PTR14_MASK) +#define SEI_CTRL_CMD_TABLE_PTD_PTR14_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTD_PTR14_MASK) >> SEI_CTRL_CMD_TABLE_PTD_PTR14_SHIFT) + +/* + * PTR13 (RW) + * + * pointer13 + */ +#define SEI_CTRL_CMD_TABLE_PTD_PTR13_MASK (0xFF00U) +#define SEI_CTRL_CMD_TABLE_PTD_PTR13_SHIFT (8U) +#define SEI_CTRL_CMD_TABLE_PTD_PTR13_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTD_PTR13_SHIFT) & SEI_CTRL_CMD_TABLE_PTD_PTR13_MASK) +#define SEI_CTRL_CMD_TABLE_PTD_PTR13_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTD_PTR13_MASK) >> SEI_CTRL_CMD_TABLE_PTD_PTR13_SHIFT) + +/* + * PTR12 (RW) + * + * pointer12 + */ +#define SEI_CTRL_CMD_TABLE_PTD_PTR12_MASK (0xFFU) +#define SEI_CTRL_CMD_TABLE_PTD_PTR12_SHIFT (0U) +#define SEI_CTRL_CMD_TABLE_PTD_PTR12_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTD_PTR12_SHIFT) & SEI_CTRL_CMD_TABLE_PTD_PTR12_MASK) +#define SEI_CTRL_CMD_TABLE_PTD_PTR12_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTD_PTR12_MASK) >> SEI_CTRL_CMD_TABLE_PTD_PTR12_SHIFT) + +/* Bitfield definition for register of struct array CTRL: 0_1 */ +/* + * POINTER (RW) + * + * pointer + */ +#define SEI_CTRL_LATCH_TRAN_POINTER_MASK (0xFF000000UL) +#define SEI_CTRL_LATCH_TRAN_POINTER_SHIFT (24U) +#define SEI_CTRL_LATCH_TRAN_POINTER_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_POINTER_SHIFT) & SEI_CTRL_LATCH_TRAN_POINTER_MASK) +#define SEI_CTRL_LATCH_TRAN_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_POINTER_MASK) >> SEI_CTRL_LATCH_TRAN_POINTER_SHIFT) + +/* + * CFG_TM (RW) + * + * timeout + * 0: high + * 1: low + * 2: rise + * 3: fall + */ +#define SEI_CTRL_LATCH_TRAN_CFG_TM_MASK (0x30000UL) +#define SEI_CTRL_LATCH_TRAN_CFG_TM_SHIFT (16U) +#define SEI_CTRL_LATCH_TRAN_CFG_TM_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_TM_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_TM_MASK) +#define SEI_CTRL_LATCH_TRAN_CFG_TM_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_TM_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_TM_SHIFT) + +/* + * CFG_TXD (RW) + * + * data send + * 0: high + * 1: low + * 2: rise + * 3: fall + */ +#define SEI_CTRL_LATCH_TRAN_CFG_TXD_MASK (0x3000U) +#define SEI_CTRL_LATCH_TRAN_CFG_TXD_SHIFT (12U) +#define SEI_CTRL_LATCH_TRAN_CFG_TXD_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_TXD_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_TXD_MASK) +#define SEI_CTRL_LATCH_TRAN_CFG_TXD_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_TXD_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_TXD_SHIFT) + +/* + * CFG_CLK (RW) + * + * clock + * 0: high + * 1: low + * 2: rise + * 3: fall + */ +#define SEI_CTRL_LATCH_TRAN_CFG_CLK_MASK (0xC00U) +#define SEI_CTRL_LATCH_TRAN_CFG_CLK_SHIFT (10U) +#define SEI_CTRL_LATCH_TRAN_CFG_CLK_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_CLK_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_CLK_MASK) +#define SEI_CTRL_LATCH_TRAN_CFG_CLK_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_CLK_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_CLK_SHIFT) + +/* + * CFG_PTR (RW) + * + * pointer + * 0: match + * 1: not match + * 2:entry + * 3:leave + */ +#define SEI_CTRL_LATCH_TRAN_CFG_PTR_MASK (0x300U) +#define SEI_CTRL_LATCH_TRAN_CFG_PTR_SHIFT (8U) +#define SEI_CTRL_LATCH_TRAN_CFG_PTR_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_PTR_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_PTR_MASK) +#define SEI_CTRL_LATCH_TRAN_CFG_PTR_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_PTR_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_PTR_SHIFT) + +/* + * OV_TM (RW) + * + * override timeout check + */ +#define SEI_CTRL_LATCH_TRAN_OV_TM_MASK (0x10U) +#define SEI_CTRL_LATCH_TRAN_OV_TM_SHIFT (4U) +#define SEI_CTRL_LATCH_TRAN_OV_TM_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_TM_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_TM_MASK) +#define SEI_CTRL_LATCH_TRAN_OV_TM_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_TM_MASK) >> SEI_CTRL_LATCH_TRAN_OV_TM_SHIFT) + +/* + * OV_TXD (RW) + * + * override TX data check + */ +#define SEI_CTRL_LATCH_TRAN_OV_TXD_MASK (0x4U) +#define SEI_CTRL_LATCH_TRAN_OV_TXD_SHIFT (2U) +#define SEI_CTRL_LATCH_TRAN_OV_TXD_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_TXD_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_TXD_MASK) +#define SEI_CTRL_LATCH_TRAN_OV_TXD_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_TXD_MASK) >> SEI_CTRL_LATCH_TRAN_OV_TXD_SHIFT) + +/* + * OV_CLK (RW) + * + * override clock check + */ +#define SEI_CTRL_LATCH_TRAN_OV_CLK_MASK (0x2U) +#define SEI_CTRL_LATCH_TRAN_OV_CLK_SHIFT (1U) +#define SEI_CTRL_LATCH_TRAN_OV_CLK_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_CLK_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_CLK_MASK) +#define SEI_CTRL_LATCH_TRAN_OV_CLK_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_CLK_MASK) >> SEI_CTRL_LATCH_TRAN_OV_CLK_SHIFT) + +/* + * OV_PTR (RW) + * + * override pointer check + */ +#define SEI_CTRL_LATCH_TRAN_OV_PTR_MASK (0x1U) +#define SEI_CTRL_LATCH_TRAN_OV_PTR_SHIFT (0U) +#define SEI_CTRL_LATCH_TRAN_OV_PTR_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_PTR_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_PTR_MASK) +#define SEI_CTRL_LATCH_TRAN_OV_PTR_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_PTR_MASK) >> SEI_CTRL_LATCH_TRAN_OV_PTR_SHIFT) + +/* Bitfield definition for register of struct array CTRL: CFG */ +/* + * EN (RW) + * + * Enable latch + * 0: disable + * 1: enable + */ +#define SEI_CTRL_LATCH_CFG_EN_MASK (0x80000000UL) +#define SEI_CTRL_LATCH_CFG_EN_SHIFT (31U) +#define SEI_CTRL_LATCH_CFG_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_CFG_EN_SHIFT) & SEI_CTRL_LATCH_CFG_EN_MASK) +#define SEI_CTRL_LATCH_CFG_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_CFG_EN_MASK) >> SEI_CTRL_LATCH_CFG_EN_SHIFT) + +/* + * SELECT (RW) + * + * Output select + * 0: state0-state1 + * 1: state1-state2 + * 2: state2-state3 + * 3: state3-state0 + */ +#define SEI_CTRL_LATCH_CFG_SELECT_MASK (0x7000000UL) +#define SEI_CTRL_LATCH_CFG_SELECT_SHIFT (24U) +#define SEI_CTRL_LATCH_CFG_SELECT_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_CFG_SELECT_SHIFT) & SEI_CTRL_LATCH_CFG_SELECT_MASK) +#define SEI_CTRL_LATCH_CFG_SELECT_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_CFG_SELECT_MASK) >> SEI_CTRL_LATCH_CFG_SELECT_SHIFT) + +/* + * DELAY (RW) + * + * Delay in system clock cycle, for state transition + */ +#define SEI_CTRL_LATCH_CFG_DELAY_MASK (0xFFFFU) +#define SEI_CTRL_LATCH_CFG_DELAY_SHIFT (0U) +#define SEI_CTRL_LATCH_CFG_DELAY_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_CFG_DELAY_SHIFT) & SEI_CTRL_LATCH_CFG_DELAY_MASK) +#define SEI_CTRL_LATCH_CFG_DELAY_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_CFG_DELAY_MASK) >> SEI_CTRL_LATCH_CFG_DELAY_SHIFT) + +/* Bitfield definition for register of struct array CTRL: TIME */ +/* + * LAT_TIME (RO) + * + * Latch time + */ +#define SEI_CTRL_LATCH_TIME_LAT_TIME_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_LATCH_TIME_LAT_TIME_SHIFT (0U) +#define SEI_CTRL_LATCH_TIME_LAT_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TIME_LAT_TIME_MASK) >> SEI_CTRL_LATCH_TIME_LAT_TIME_SHIFT) + +/* Bitfield definition for register of struct array CTRL: STS */ +/* + * STATE (RO) + * + * State + */ +#define SEI_CTRL_LATCH_STS_STATE_MASK (0x7000000UL) +#define SEI_CTRL_LATCH_STS_STATE_SHIFT (24U) +#define SEI_CTRL_LATCH_STS_STATE_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_STS_STATE_MASK) >> SEI_CTRL_LATCH_STS_STATE_SHIFT) + +/* + * LAT_CNT (RO) + * + * Latch counter + */ +#define SEI_CTRL_LATCH_STS_LAT_CNT_MASK (0xFFFFU) +#define SEI_CTRL_LATCH_STS_LAT_CNT_SHIFT (0U) +#define SEI_CTRL_LATCH_STS_LAT_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_STS_LAT_CNT_MASK) >> SEI_CTRL_LATCH_STS_LAT_CNT_SHIFT) + +/* Bitfield definition for register of struct array CTRL: SMP_EN */ +/* + * ACC_EN (RW) + * + * Position include acceleration + */ +#define SEI_CTRL_POS_SMP_EN_ACC_EN_MASK (0x80000000UL) +#define SEI_CTRL_POS_SMP_EN_ACC_EN_SHIFT (31U) +#define SEI_CTRL_POS_SMP_EN_ACC_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_ACC_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_ACC_EN_MASK) +#define SEI_CTRL_POS_SMP_EN_ACC_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_ACC_EN_MASK) >> SEI_CTRL_POS_SMP_EN_ACC_EN_SHIFT) + +/* + * ACC_SEL (RW) + * + * Data register for acceleration transfer + */ +#define SEI_CTRL_POS_SMP_EN_ACC_SEL_MASK (0x1F000000UL) +#define SEI_CTRL_POS_SMP_EN_ACC_SEL_SHIFT (24U) +#define SEI_CTRL_POS_SMP_EN_ACC_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_ACC_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_ACC_SEL_MASK) +#define SEI_CTRL_POS_SMP_EN_ACC_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_ACC_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_ACC_SEL_SHIFT) + +/* + * SPD_EN (RW) + * + * Position include speed + */ +#define SEI_CTRL_POS_SMP_EN_SPD_EN_MASK (0x800000UL) +#define SEI_CTRL_POS_SMP_EN_SPD_EN_SHIFT (23U) +#define SEI_CTRL_POS_SMP_EN_SPD_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_SPD_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_SPD_EN_MASK) +#define SEI_CTRL_POS_SMP_EN_SPD_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_SPD_EN_MASK) >> SEI_CTRL_POS_SMP_EN_SPD_EN_SHIFT) + +/* + * SPD_SEL (RW) + * + * Data register for speed transfer + */ +#define SEI_CTRL_POS_SMP_EN_SPD_SEL_MASK (0x1F0000UL) +#define SEI_CTRL_POS_SMP_EN_SPD_SEL_SHIFT (16U) +#define SEI_CTRL_POS_SMP_EN_SPD_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_SPD_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_SPD_SEL_MASK) +#define SEI_CTRL_POS_SMP_EN_SPD_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_SPD_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_SPD_SEL_SHIFT) + +/* + * REV_EN (RW) + * + * Position include revolution + */ +#define SEI_CTRL_POS_SMP_EN_REV_EN_MASK (0x8000U) +#define SEI_CTRL_POS_SMP_EN_REV_EN_SHIFT (15U) +#define SEI_CTRL_POS_SMP_EN_REV_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_REV_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_REV_EN_MASK) +#define SEI_CTRL_POS_SMP_EN_REV_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_REV_EN_MASK) >> SEI_CTRL_POS_SMP_EN_REV_EN_SHIFT) + +/* + * REV_SEL (RW) + * + * Data register for revolution transfer + */ +#define SEI_CTRL_POS_SMP_EN_REV_SEL_MASK (0x1F00U) +#define SEI_CTRL_POS_SMP_EN_REV_SEL_SHIFT (8U) +#define SEI_CTRL_POS_SMP_EN_REV_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_REV_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_REV_SEL_MASK) +#define SEI_CTRL_POS_SMP_EN_REV_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_REV_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_REV_SEL_SHIFT) + +/* + * POS_EN (RW) + * + * Position include position + */ +#define SEI_CTRL_POS_SMP_EN_POS_EN_MASK (0x80U) +#define SEI_CTRL_POS_SMP_EN_POS_EN_SHIFT (7U) +#define SEI_CTRL_POS_SMP_EN_POS_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_POS_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_POS_EN_MASK) +#define SEI_CTRL_POS_SMP_EN_POS_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_POS_EN_MASK) >> SEI_CTRL_POS_SMP_EN_POS_EN_SHIFT) + +/* + * POS_SEL (RW) + * + * Data register for position transfer + */ +#define SEI_CTRL_POS_SMP_EN_POS_SEL_MASK (0x1FU) +#define SEI_CTRL_POS_SMP_EN_POS_SEL_SHIFT (0U) +#define SEI_CTRL_POS_SMP_EN_POS_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_POS_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_POS_SEL_MASK) +#define SEI_CTRL_POS_SMP_EN_POS_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_POS_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_POS_SEL_SHIFT) + +/* Bitfield definition for register of struct array CTRL: SMP_CFG */ +/* + * ONCE (RW) + * + * Sample one time + * 0: Sample during windows time + * 1: Close sample window after first sample + */ +#define SEI_CTRL_POS_SMP_CFG_ONCE_MASK (0x1000000UL) +#define SEI_CTRL_POS_SMP_CFG_ONCE_SHIFT (24U) +#define SEI_CTRL_POS_SMP_CFG_ONCE_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_CFG_ONCE_SHIFT) & SEI_CTRL_POS_SMP_CFG_ONCE_MASK) +#define SEI_CTRL_POS_SMP_CFG_ONCE_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_CFG_ONCE_MASK) >> SEI_CTRL_POS_SMP_CFG_ONCE_SHIFT) + +/* + * LAT_SEL (RW) + * + * Latch selection + * 0: latch 0 + * 1: latch 1 + * 2: latch 2 + * 3: latch 3 + */ +#define SEI_CTRL_POS_SMP_CFG_LAT_SEL_MASK (0x30000UL) +#define SEI_CTRL_POS_SMP_CFG_LAT_SEL_SHIFT (16U) +#define SEI_CTRL_POS_SMP_CFG_LAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_CFG_LAT_SEL_SHIFT) & SEI_CTRL_POS_SMP_CFG_LAT_SEL_MASK) +#define SEI_CTRL_POS_SMP_CFG_LAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_CFG_LAT_SEL_MASK) >> SEI_CTRL_POS_SMP_CFG_LAT_SEL_SHIFT) + +/* + * WINDOW (RW) + * + * Sample window, in clock cycle + */ +#define SEI_CTRL_POS_SMP_CFG_WINDOW_MASK (0xFFFFU) +#define SEI_CTRL_POS_SMP_CFG_WINDOW_SHIFT (0U) +#define SEI_CTRL_POS_SMP_CFG_WINDOW_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_CFG_WINDOW_SHIFT) & SEI_CTRL_POS_SMP_CFG_WINDOW_MASK) +#define SEI_CTRL_POS_SMP_CFG_WINDOW_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_CFG_WINDOW_MASK) >> SEI_CTRL_POS_SMP_CFG_WINDOW_SHIFT) + +/* Bitfield definition for register of struct array CTRL: SMP_DAT */ +/* + * DAT_SEL (RW) + * + * Data register sampled, each bit represent a data register + */ +#define SEI_CTRL_POS_SMP_DAT_DAT_SEL_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_POS_SMP_DAT_DAT_SEL_SHIFT (0U) +#define SEI_CTRL_POS_SMP_DAT_DAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_DAT_DAT_SEL_SHIFT) & SEI_CTRL_POS_SMP_DAT_DAT_SEL_MASK) +#define SEI_CTRL_POS_SMP_DAT_DAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_DAT_DAT_SEL_MASK) >> SEI_CTRL_POS_SMP_DAT_DAT_SEL_SHIFT) + +/* Bitfield definition for register of struct array CTRL: SMP_POS */ +/* + * POS (RW) + * + * Sample override position + */ +#define SEI_CTRL_POS_SMP_POS_POS_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_POS_SMP_POS_POS_SHIFT (0U) +#define SEI_CTRL_POS_SMP_POS_POS_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_POS_POS_SHIFT) & SEI_CTRL_POS_SMP_POS_POS_MASK) +#define SEI_CTRL_POS_SMP_POS_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_POS_POS_MASK) >> SEI_CTRL_POS_SMP_POS_POS_SHIFT) + +/* Bitfield definition for register of struct array CTRL: SMP_REV */ +/* + * REV (RW) + * + * Sample override revolution + */ +#define SEI_CTRL_POS_SMP_REV_REV_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_POS_SMP_REV_REV_SHIFT (0U) +#define SEI_CTRL_POS_SMP_REV_REV_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_REV_REV_SHIFT) & SEI_CTRL_POS_SMP_REV_REV_MASK) +#define SEI_CTRL_POS_SMP_REV_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_REV_REV_MASK) >> SEI_CTRL_POS_SMP_REV_REV_SHIFT) + +/* Bitfield definition for register of struct array CTRL: SMP_SPD */ +/* + * SPD (RW) + * + * Sample override speed + */ +#define SEI_CTRL_POS_SMP_SPD_SPD_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_POS_SMP_SPD_SPD_SHIFT (0U) +#define SEI_CTRL_POS_SMP_SPD_SPD_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_SPD_SPD_SHIFT) & SEI_CTRL_POS_SMP_SPD_SPD_MASK) +#define SEI_CTRL_POS_SMP_SPD_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_SPD_SPD_MASK) >> SEI_CTRL_POS_SMP_SPD_SPD_SHIFT) + +/* Bitfield definition for register of struct array CTRL: SMP_ACC */ +/* + * ACC (RW) + * + * Sample override accelerate + */ +#define SEI_CTRL_POS_SMP_ACC_ACC_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_POS_SMP_ACC_ACC_SHIFT (0U) +#define SEI_CTRL_POS_SMP_ACC_ACC_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_ACC_ACC_SHIFT) & SEI_CTRL_POS_SMP_ACC_ACC_MASK) +#define SEI_CTRL_POS_SMP_ACC_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_ACC_ACC_MASK) >> SEI_CTRL_POS_SMP_ACC_ACC_SHIFT) + +/* Bitfield definition for register of struct array CTRL: UPD_EN */ +/* + * ACC_EN (RW) + * + * Position include acceleration + */ +#define SEI_CTRL_POS_UPD_EN_ACC_EN_MASK (0x80000000UL) +#define SEI_CTRL_POS_UPD_EN_ACC_EN_SHIFT (31U) +#define SEI_CTRL_POS_UPD_EN_ACC_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_ACC_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_ACC_EN_MASK) +#define SEI_CTRL_POS_UPD_EN_ACC_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_ACC_EN_MASK) >> SEI_CTRL_POS_UPD_EN_ACC_EN_SHIFT) + +/* + * ACC_SEL (RW) + * + * Data register for acceleration transfer + */ +#define SEI_CTRL_POS_UPD_EN_ACC_SEL_MASK (0x1F000000UL) +#define SEI_CTRL_POS_UPD_EN_ACC_SEL_SHIFT (24U) +#define SEI_CTRL_POS_UPD_EN_ACC_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_ACC_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_ACC_SEL_MASK) +#define SEI_CTRL_POS_UPD_EN_ACC_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_ACC_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_ACC_SEL_SHIFT) + +/* + * SPD_EN (RW) + * + * Position include speed + */ +#define SEI_CTRL_POS_UPD_EN_SPD_EN_MASK (0x800000UL) +#define SEI_CTRL_POS_UPD_EN_SPD_EN_SHIFT (23U) +#define SEI_CTRL_POS_UPD_EN_SPD_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_SPD_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_SPD_EN_MASK) +#define SEI_CTRL_POS_UPD_EN_SPD_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_SPD_EN_MASK) >> SEI_CTRL_POS_UPD_EN_SPD_EN_SHIFT) + +/* + * SPD_SEL (RW) + * + * Data register for speed transfer + */ +#define SEI_CTRL_POS_UPD_EN_SPD_SEL_MASK (0x1F0000UL) +#define SEI_CTRL_POS_UPD_EN_SPD_SEL_SHIFT (16U) +#define SEI_CTRL_POS_UPD_EN_SPD_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_SPD_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_SPD_SEL_MASK) +#define SEI_CTRL_POS_UPD_EN_SPD_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_SPD_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_SPD_SEL_SHIFT) + +/* + * REV_EN (RW) + * + * Position include revolution + */ +#define SEI_CTRL_POS_UPD_EN_REV_EN_MASK (0x8000U) +#define SEI_CTRL_POS_UPD_EN_REV_EN_SHIFT (15U) +#define SEI_CTRL_POS_UPD_EN_REV_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_REV_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_REV_EN_MASK) +#define SEI_CTRL_POS_UPD_EN_REV_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_REV_EN_MASK) >> SEI_CTRL_POS_UPD_EN_REV_EN_SHIFT) + +/* + * REV_SEL (RW) + * + * Data register for revolution transfer + */ +#define SEI_CTRL_POS_UPD_EN_REV_SEL_MASK (0x1F00U) +#define SEI_CTRL_POS_UPD_EN_REV_SEL_SHIFT (8U) +#define SEI_CTRL_POS_UPD_EN_REV_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_REV_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_REV_SEL_MASK) +#define SEI_CTRL_POS_UPD_EN_REV_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_REV_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_REV_SEL_SHIFT) + +/* + * POS_EN (RW) + * + * Position include position + */ +#define SEI_CTRL_POS_UPD_EN_POS_EN_MASK (0x80U) +#define SEI_CTRL_POS_UPD_EN_POS_EN_SHIFT (7U) +#define SEI_CTRL_POS_UPD_EN_POS_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_POS_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_POS_EN_MASK) +#define SEI_CTRL_POS_UPD_EN_POS_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_POS_EN_MASK) >> SEI_CTRL_POS_UPD_EN_POS_EN_SHIFT) + +/* + * POS_SEL (RW) + * + * Data register for position transfer + */ +#define SEI_CTRL_POS_UPD_EN_POS_SEL_MASK (0x1FU) +#define SEI_CTRL_POS_UPD_EN_POS_SEL_SHIFT (0U) +#define SEI_CTRL_POS_UPD_EN_POS_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_POS_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_POS_SEL_MASK) +#define SEI_CTRL_POS_UPD_EN_POS_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_POS_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_POS_SEL_SHIFT) + +/* Bitfield definition for register of struct array CTRL: UPD_CFG */ +/* + * TIME_OVRD (RW) + * + * Use override time + * 0: use time sample from motor group + * 1: use override time + */ +#define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_MASK (0x80000000UL) +#define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SHIFT (31U) +#define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SHIFT) & SEI_CTRL_POS_UPD_CFG_TIME_OVRD_MASK) +#define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_CFG_TIME_OVRD_MASK) >> SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SHIFT) + +/* + * ONERR (RW) + * + * Sample one time + * 0: Sample during windows time + * 1: Close sample window after first sample + */ +#define SEI_CTRL_POS_UPD_CFG_ONERR_MASK (0x1000000UL) +#define SEI_CTRL_POS_UPD_CFG_ONERR_SHIFT (24U) +#define SEI_CTRL_POS_UPD_CFG_ONERR_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_CFG_ONERR_SHIFT) & SEI_CTRL_POS_UPD_CFG_ONERR_MASK) +#define SEI_CTRL_POS_UPD_CFG_ONERR_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_CFG_ONERR_MASK) >> SEI_CTRL_POS_UPD_CFG_ONERR_SHIFT) + +/* + * LAT_SEL (RW) + * + * Latch selection + * 0: latch 0 + * 1: latch 1 + * 2: latch 2 + * 3: latch 3 + */ +#define SEI_CTRL_POS_UPD_CFG_LAT_SEL_MASK (0x30000UL) +#define SEI_CTRL_POS_UPD_CFG_LAT_SEL_SHIFT (16U) +#define SEI_CTRL_POS_UPD_CFG_LAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_CFG_LAT_SEL_SHIFT) & SEI_CTRL_POS_UPD_CFG_LAT_SEL_MASK) +#define SEI_CTRL_POS_UPD_CFG_LAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_CFG_LAT_SEL_MASK) >> SEI_CTRL_POS_UPD_CFG_LAT_SEL_SHIFT) + +/* Bitfield definition for register of struct array CTRL: UPD_DAT */ +/* + * DAT_SEL (RW) + * + * Data register sampled, each bit represent a data register + */ +#define SEI_CTRL_POS_UPD_DAT_DAT_SEL_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_POS_UPD_DAT_DAT_SEL_SHIFT (0U) +#define SEI_CTRL_POS_UPD_DAT_DAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_DAT_DAT_SEL_SHIFT) & SEI_CTRL_POS_UPD_DAT_DAT_SEL_MASK) +#define SEI_CTRL_POS_UPD_DAT_DAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_DAT_DAT_SEL_MASK) >> SEI_CTRL_POS_UPD_DAT_DAT_SEL_SHIFT) + +/* Bitfield definition for register of struct array CTRL: UPD_TIME */ +/* + * TIME (RW) + * + * Update override time + */ +#define SEI_CTRL_POS_UPD_TIME_TIME_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_POS_UPD_TIME_TIME_SHIFT (0U) +#define SEI_CTRL_POS_UPD_TIME_TIME_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_TIME_TIME_SHIFT) & SEI_CTRL_POS_UPD_TIME_TIME_MASK) +#define SEI_CTRL_POS_UPD_TIME_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_TIME_TIME_MASK) >> SEI_CTRL_POS_UPD_TIME_TIME_SHIFT) + +/* Bitfield definition for register of struct array CTRL: UPD_POS */ +/* + * POS (RW) + * + * Update override position + */ +#define SEI_CTRL_POS_UPD_POS_POS_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_POS_UPD_POS_POS_SHIFT (0U) +#define SEI_CTRL_POS_UPD_POS_POS_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_POS_POS_SHIFT) & SEI_CTRL_POS_UPD_POS_POS_MASK) +#define SEI_CTRL_POS_UPD_POS_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_POS_POS_MASK) >> SEI_CTRL_POS_UPD_POS_POS_SHIFT) + +/* Bitfield definition for register of struct array CTRL: UPD_REV */ +/* + * REV (RW) + * + * Update override revolution + */ +#define SEI_CTRL_POS_UPD_REV_REV_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_POS_UPD_REV_REV_SHIFT (0U) +#define SEI_CTRL_POS_UPD_REV_REV_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_REV_REV_SHIFT) & SEI_CTRL_POS_UPD_REV_REV_MASK) +#define SEI_CTRL_POS_UPD_REV_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_REV_REV_MASK) >> SEI_CTRL_POS_UPD_REV_REV_SHIFT) + +/* Bitfield definition for register of struct array CTRL: UPD_SPD */ +/* + * SPD (RW) + * + * Update override speed + */ +#define SEI_CTRL_POS_UPD_SPD_SPD_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_POS_UPD_SPD_SPD_SHIFT (0U) +#define SEI_CTRL_POS_UPD_SPD_SPD_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_SPD_SPD_SHIFT) & SEI_CTRL_POS_UPD_SPD_SPD_MASK) +#define SEI_CTRL_POS_UPD_SPD_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_SPD_SPD_MASK) >> SEI_CTRL_POS_UPD_SPD_SPD_SHIFT) + +/* Bitfield definition for register of struct array CTRL: UPD_ACC */ +/* + * ACC (RW) + * + * Update override accelerate + */ +#define SEI_CTRL_POS_UPD_ACC_ACC_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_POS_UPD_ACC_ACC_SHIFT (0U) +#define SEI_CTRL_POS_UPD_ACC_ACC_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_ACC_ACC_SHIFT) & SEI_CTRL_POS_UPD_ACC_ACC_MASK) +#define SEI_CTRL_POS_UPD_ACC_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_ACC_ACC_MASK) >> SEI_CTRL_POS_UPD_ACC_ACC_SHIFT) + +/* Bitfield definition for register of struct array CTRL: SMP_VAL */ +/* + * ACC (RO) + * + * Position include acceleration + */ +#define SEI_CTRL_POS_SMP_VAL_ACC_MASK (0x80000000UL) +#define SEI_CTRL_POS_SMP_VAL_ACC_SHIFT (31U) +#define SEI_CTRL_POS_SMP_VAL_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_ACC_MASK) >> SEI_CTRL_POS_SMP_VAL_ACC_SHIFT) + +/* + * SPD (RO) + * + * Position include speed + */ +#define SEI_CTRL_POS_SMP_VAL_SPD_MASK (0x800000UL) +#define SEI_CTRL_POS_SMP_VAL_SPD_SHIFT (23U) +#define SEI_CTRL_POS_SMP_VAL_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_SPD_MASK) >> SEI_CTRL_POS_SMP_VAL_SPD_SHIFT) + +/* + * REV (RO) + * + * Position include revolution + */ +#define SEI_CTRL_POS_SMP_VAL_REV_MASK (0x8000U) +#define SEI_CTRL_POS_SMP_VAL_REV_SHIFT (15U) +#define SEI_CTRL_POS_SMP_VAL_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_REV_MASK) >> SEI_CTRL_POS_SMP_VAL_REV_SHIFT) + +/* + * POS (RO) + * + * Position include position + */ +#define SEI_CTRL_POS_SMP_VAL_POS_MASK (0x80U) +#define SEI_CTRL_POS_SMP_VAL_POS_SHIFT (7U) +#define SEI_CTRL_POS_SMP_VAL_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_POS_MASK) >> SEI_CTRL_POS_SMP_VAL_POS_SHIFT) + +/* Bitfield definition for register of struct array CTRL: SMP_STS */ +/* + * OCCUR (RO) + * + * Sample occured + * 0: Sample not happened + * 1: Sample occured + */ +#define SEI_CTRL_POS_SMP_STS_OCCUR_MASK (0x1000000UL) +#define SEI_CTRL_POS_SMP_STS_OCCUR_SHIFT (24U) +#define SEI_CTRL_POS_SMP_STS_OCCUR_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_STS_OCCUR_MASK) >> SEI_CTRL_POS_SMP_STS_OCCUR_SHIFT) + +/* + * WIN_CNT (RO) + * + * Sample window counter + */ +#define SEI_CTRL_POS_SMP_STS_WIN_CNT_MASK (0xFFFFU) +#define SEI_CTRL_POS_SMP_STS_WIN_CNT_SHIFT (0U) +#define SEI_CTRL_POS_SMP_STS_WIN_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_STS_WIN_CNT_MASK) >> SEI_CTRL_POS_SMP_STS_WIN_CNT_SHIFT) + +/* Bitfield definition for register of struct array CTRL: TIME_IN */ +/* + * TIME (RO) + * + * input time + */ +#define SEI_CTRL_POS_TIME_IN_TIME_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_POS_TIME_IN_TIME_SHIFT (0U) +#define SEI_CTRL_POS_TIME_IN_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_TIME_IN_TIME_MASK) >> SEI_CTRL_POS_TIME_IN_TIME_SHIFT) + +/* Bitfield definition for register of struct array CTRL: POS_IN */ +/* + * POS (RO) + * + * Input position + */ +#define SEI_CTRL_POS_POS_IN_POS_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_POS_POS_IN_POS_SHIFT (0U) +#define SEI_CTRL_POS_POS_IN_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_POS_IN_POS_MASK) >> SEI_CTRL_POS_POS_IN_POS_SHIFT) + +/* Bitfield definition for register of struct array CTRL: REV_IN */ +/* + * REV (RO) + * + * Input revolution + */ +#define SEI_CTRL_POS_REV_IN_REV_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_POS_REV_IN_REV_SHIFT (0U) +#define SEI_CTRL_POS_REV_IN_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_REV_IN_REV_MASK) >> SEI_CTRL_POS_REV_IN_REV_SHIFT) + +/* Bitfield definition for register of struct array CTRL: SPD_IN */ +/* + * SPD (RO) + * + * Input speed + */ +#define SEI_CTRL_POS_SPD_IN_SPD_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_POS_SPD_IN_SPD_SHIFT (0U) +#define SEI_CTRL_POS_SPD_IN_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SPD_IN_SPD_MASK) >> SEI_CTRL_POS_SPD_IN_SPD_SHIFT) + +/* Bitfield definition for register of struct array CTRL: ACC_IN */ +/* + * ACC (RO) + * + * Input accelerate + */ +#define SEI_CTRL_POS_ACC_IN_ACC_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_POS_ACC_IN_ACC_SHIFT (0U) +#define SEI_CTRL_POS_ACC_IN_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_ACC_IN_ACC_MASK) >> SEI_CTRL_POS_ACC_IN_ACC_SHIFT) + +/* Bitfield definition for register of struct array CTRL: UPD_STS */ +/* + * UPD_ERR (RO) + * + * Update error + * 0: data receive normally + * 1: data receive error + */ +#define SEI_CTRL_POS_UPD_STS_UPD_ERR_MASK (0x1000000UL) +#define SEI_CTRL_POS_UPD_STS_UPD_ERR_SHIFT (24U) +#define SEI_CTRL_POS_UPD_STS_UPD_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_STS_UPD_ERR_MASK) >> SEI_CTRL_POS_UPD_STS_UPD_ERR_SHIFT) + +/* Bitfield definition for register of struct array CTRL: INT_EN */ +/* + * TRG_ERR3 (RW) + * + * Trigger3 failed + */ +#define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_MASK (0x80000000UL) +#define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SHIFT (31U) +#define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR3_MASK) +#define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR3_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SHIFT) + +/* + * TRG_ERR2 (RW) + * + * Trigger2 failed + */ +#define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_MASK (0x40000000UL) +#define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SHIFT (30U) +#define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR2_MASK) +#define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR2_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SHIFT) + +/* + * TRG_ERR1 (RW) + * + * Trigger1 failed + */ +#define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_MASK (0x20000000UL) +#define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SHIFT (29U) +#define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR1_MASK) +#define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR1_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SHIFT) + +/* + * TRG_ERR0 (RW) + * + * Trigger0 failed + */ +#define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_MASK (0x10000000UL) +#define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SHIFT (28U) +#define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR0_MASK) +#define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR0_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SHIFT) + +/* + * TRIGER3 (RW) + * + * Trigger3 + */ +#define SEI_CTRL_IRQ_INT_EN_TRIGER3_MASK (0x8000000UL) +#define SEI_CTRL_IRQ_INT_EN_TRIGER3_SHIFT (27U) +#define SEI_CTRL_IRQ_INT_EN_TRIGER3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER3_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER3_MASK) +#define SEI_CTRL_IRQ_INT_EN_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER3_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER3_SHIFT) + +/* + * TRIGER2 (RW) + * + * Trigger2 + */ +#define SEI_CTRL_IRQ_INT_EN_TRIGER2_MASK (0x4000000UL) +#define SEI_CTRL_IRQ_INT_EN_TRIGER2_SHIFT (26U) +#define SEI_CTRL_IRQ_INT_EN_TRIGER2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER2_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER2_MASK) +#define SEI_CTRL_IRQ_INT_EN_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER2_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER2_SHIFT) + +/* + * TRIGER1 (RW) + * + * Trigger1 + */ +#define SEI_CTRL_IRQ_INT_EN_TRIGER1_MASK (0x2000000UL) +#define SEI_CTRL_IRQ_INT_EN_TRIGER1_SHIFT (25U) +#define SEI_CTRL_IRQ_INT_EN_TRIGER1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER1_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER1_MASK) +#define SEI_CTRL_IRQ_INT_EN_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER1_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER1_SHIFT) + +/* + * TRIGER0 (RW) + * + * Trigger0 + */ +#define SEI_CTRL_IRQ_INT_EN_TRIGER0_MASK (0x1000000UL) +#define SEI_CTRL_IRQ_INT_EN_TRIGER0_SHIFT (24U) +#define SEI_CTRL_IRQ_INT_EN_TRIGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER0_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER0_MASK) +#define SEI_CTRL_IRQ_INT_EN_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER0_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER0_SHIFT) + +/* + * SMP_ERR (RW) + * + * Sample error + */ +#define SEI_CTRL_IRQ_INT_EN_SMP_ERR_MASK (0x100000UL) +#define SEI_CTRL_IRQ_INT_EN_SMP_ERR_SHIFT (20U) +#define SEI_CTRL_IRQ_INT_EN_SMP_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_SMP_ERR_SHIFT) & SEI_CTRL_IRQ_INT_EN_SMP_ERR_MASK) +#define SEI_CTRL_IRQ_INT_EN_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_SMP_ERR_MASK) >> SEI_CTRL_IRQ_INT_EN_SMP_ERR_SHIFT) + +/* + * LATCH3 (RW) + * + * Latch3 + */ +#define SEI_CTRL_IRQ_INT_EN_LATCH3_MASK (0x80000UL) +#define SEI_CTRL_IRQ_INT_EN_LATCH3_SHIFT (19U) +#define SEI_CTRL_IRQ_INT_EN_LATCH3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH3_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH3_MASK) +#define SEI_CTRL_IRQ_INT_EN_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH3_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH3_SHIFT) + +/* + * LATCH2 (RW) + * + * Latch2 + */ +#define SEI_CTRL_IRQ_INT_EN_LATCH2_MASK (0x40000UL) +#define SEI_CTRL_IRQ_INT_EN_LATCH2_SHIFT (18U) +#define SEI_CTRL_IRQ_INT_EN_LATCH2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH2_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH2_MASK) +#define SEI_CTRL_IRQ_INT_EN_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH2_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH2_SHIFT) + +/* + * LATCH1 (RW) + * + * Latch1 + */ +#define SEI_CTRL_IRQ_INT_EN_LATCH1_MASK (0x20000UL) +#define SEI_CTRL_IRQ_INT_EN_LATCH1_SHIFT (17U) +#define SEI_CTRL_IRQ_INT_EN_LATCH1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH1_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH1_MASK) +#define SEI_CTRL_IRQ_INT_EN_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH1_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH1_SHIFT) + +/* + * LATCH0 (RW) + * + * Latch0 + */ +#define SEI_CTRL_IRQ_INT_EN_LATCH0_MASK (0x10000UL) +#define SEI_CTRL_IRQ_INT_EN_LATCH0_SHIFT (16U) +#define SEI_CTRL_IRQ_INT_EN_LATCH0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH0_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH0_MASK) +#define SEI_CTRL_IRQ_INT_EN_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH0_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH0_SHIFT) + +/* + * TIMEOUT (RW) + * + * Timeout + */ +#define SEI_CTRL_IRQ_INT_EN_TIMEOUT_MASK (0x2000U) +#define SEI_CTRL_IRQ_INT_EN_TIMEOUT_SHIFT (13U) +#define SEI_CTRL_IRQ_INT_EN_TIMEOUT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TIMEOUT_SHIFT) & SEI_CTRL_IRQ_INT_EN_TIMEOUT_MASK) +#define SEI_CTRL_IRQ_INT_EN_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TIMEOUT_MASK) >> SEI_CTRL_IRQ_INT_EN_TIMEOUT_SHIFT) + +/* + * TRX_ERR (RW) + * + * Transfer error + */ +#define SEI_CTRL_IRQ_INT_EN_TRX_ERR_MASK (0x1000U) +#define SEI_CTRL_IRQ_INT_EN_TRX_ERR_SHIFT (12U) +#define SEI_CTRL_IRQ_INT_EN_TRX_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRX_ERR_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRX_ERR_MASK) +#define SEI_CTRL_IRQ_INT_EN_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRX_ERR_MASK) >> SEI_CTRL_IRQ_INT_EN_TRX_ERR_SHIFT) + +/* + * INSTR1_END (RW) + * + * Instruction 1 end + */ +#define SEI_CTRL_IRQ_INT_EN_INSTR1_END_MASK (0x800U) +#define SEI_CTRL_IRQ_INT_EN_INSTR1_END_SHIFT (11U) +#define SEI_CTRL_IRQ_INT_EN_INSTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR1_END_MASK) +#define SEI_CTRL_IRQ_INT_EN_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR1_END_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR1_END_SHIFT) + +/* + * INSTR0_END (RW) + * + * Instruction 0 end + */ +#define SEI_CTRL_IRQ_INT_EN_INSTR0_END_MASK (0x400U) +#define SEI_CTRL_IRQ_INT_EN_INSTR0_END_SHIFT (10U) +#define SEI_CTRL_IRQ_INT_EN_INSTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR0_END_MASK) +#define SEI_CTRL_IRQ_INT_EN_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR0_END_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR0_END_SHIFT) + +/* + * PTR1_END (RW) + * + * Pointer 1 end + */ +#define SEI_CTRL_IRQ_INT_EN_PTR1_END_MASK (0x200U) +#define SEI_CTRL_IRQ_INT_EN_PTR1_END_SHIFT (9U) +#define SEI_CTRL_IRQ_INT_EN_PTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR1_END_MASK) +#define SEI_CTRL_IRQ_INT_EN_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR1_END_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR1_END_SHIFT) + +/* + * PTR0_END (RW) + * + * Pointer 0 end + */ +#define SEI_CTRL_IRQ_INT_EN_PTR0_END_MASK (0x100U) +#define SEI_CTRL_IRQ_INT_EN_PTR0_END_SHIFT (8U) +#define SEI_CTRL_IRQ_INT_EN_PTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR0_END_MASK) +#define SEI_CTRL_IRQ_INT_EN_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR0_END_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR0_END_SHIFT) + +/* + * INSTR1_ST (RW) + * + * Instruction 1 start + */ +#define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_MASK (0x80U) +#define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SHIFT (7U) +#define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR1_ST_MASK) +#define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SHIFT) + +/* + * INSTR0_ST (RW) + * + * Instruction 0 start + */ +#define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_MASK (0x40U) +#define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SHIFT (6U) +#define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR0_ST_MASK) +#define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SHIFT) + +/* + * PTR1_ST (RW) + * + * Pointer 1 start + */ +#define SEI_CTRL_IRQ_INT_EN_PTR1_ST_MASK (0x20U) +#define SEI_CTRL_IRQ_INT_EN_PTR1_ST_SHIFT (5U) +#define SEI_CTRL_IRQ_INT_EN_PTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR1_ST_MASK) +#define SEI_CTRL_IRQ_INT_EN_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR1_ST_SHIFT) + +/* + * PTR0_ST (RW) + * + * Pointer 0 start + */ +#define SEI_CTRL_IRQ_INT_EN_PTR0_ST_MASK (0x10U) +#define SEI_CTRL_IRQ_INT_EN_PTR0_ST_SHIFT (4U) +#define SEI_CTRL_IRQ_INT_EN_PTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR0_ST_MASK) +#define SEI_CTRL_IRQ_INT_EN_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR0_ST_SHIFT) + +/* + * WDOG (RW) + * + * Watch dog + */ +#define SEI_CTRL_IRQ_INT_EN_WDOG_MASK (0x4U) +#define SEI_CTRL_IRQ_INT_EN_WDOG_SHIFT (2U) +#define SEI_CTRL_IRQ_INT_EN_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_WDOG_SHIFT) & SEI_CTRL_IRQ_INT_EN_WDOG_MASK) +#define SEI_CTRL_IRQ_INT_EN_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_WDOG_MASK) >> SEI_CTRL_IRQ_INT_EN_WDOG_SHIFT) + +/* + * EXECPT (RW) + * + * Exception + */ +#define SEI_CTRL_IRQ_INT_EN_EXECPT_MASK (0x2U) +#define SEI_CTRL_IRQ_INT_EN_EXECPT_SHIFT (1U) +#define SEI_CTRL_IRQ_INT_EN_EXECPT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_EXECPT_SHIFT) & SEI_CTRL_IRQ_INT_EN_EXECPT_MASK) +#define SEI_CTRL_IRQ_INT_EN_EXECPT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_EXECPT_MASK) >> SEI_CTRL_IRQ_INT_EN_EXECPT_SHIFT) + +/* + * STALL (RW) + * + * Stall + */ +#define SEI_CTRL_IRQ_INT_EN_STALL_MASK (0x1U) +#define SEI_CTRL_IRQ_INT_EN_STALL_SHIFT (0U) +#define SEI_CTRL_IRQ_INT_EN_STALL_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_STALL_SHIFT) & SEI_CTRL_IRQ_INT_EN_STALL_MASK) +#define SEI_CTRL_IRQ_INT_EN_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_STALL_MASK) >> SEI_CTRL_IRQ_INT_EN_STALL_SHIFT) + +/* Bitfield definition for register of struct array CTRL: INT_FLAG */ +/* + * TRG_ERR3 (W1C) + * + * Trigger3 failed + */ +#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK (0x80000000UL) +#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SHIFT (31U) +#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SHIFT) + +/* + * TRG_ERR2 (W1C) + * + * Trigger2 failed + */ +#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK (0x40000000UL) +#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SHIFT (30U) +#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SHIFT) + +/* + * TRG_ERR1 (W1C) + * + * Trigger1 failed + */ +#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK (0x20000000UL) +#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SHIFT (29U) +#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SHIFT) + +/* + * TRG_ERR0 (W1C) + * + * Trigger0 failed + */ +#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK (0x10000000UL) +#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SHIFT (28U) +#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SHIFT) + +/* + * TRIGER3 (W1C) + * + * Trigger3 + */ +#define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK (0x8000000UL) +#define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SHIFT (27U) +#define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SHIFT) + +/* + * TRIGER2 (W1C) + * + * Trigger2 + */ +#define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK (0x4000000UL) +#define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SHIFT (26U) +#define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SHIFT) + +/* + * TRIGER1 (W1C) + * + * Trigger1 + */ +#define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK (0x2000000UL) +#define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SHIFT (25U) +#define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SHIFT) + +/* + * TRIGER0 (W1C) + * + * Trigger0 + */ +#define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK (0x1000000UL) +#define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SHIFT (24U) +#define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SHIFT) + +/* + * SMP_ERR (W1C) + * + * Sample error + */ +#define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK (0x100000UL) +#define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SHIFT (20U) +#define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK) >> SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SHIFT) + +/* + * LATCH3 (W1C) + * + * Latch3 + */ +#define SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK (0x80000UL) +#define SEI_CTRL_IRQ_INT_FLAG_LATCH3_SHIFT (19U) +#define SEI_CTRL_IRQ_INT_FLAG_LATCH3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH3_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH3_SHIFT) + +/* + * LATCH2 (W1C) + * + * Latch2 + */ +#define SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK (0x40000UL) +#define SEI_CTRL_IRQ_INT_FLAG_LATCH2_SHIFT (18U) +#define SEI_CTRL_IRQ_INT_FLAG_LATCH2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH2_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH2_SHIFT) + +/* + * LATCH1 (W1C) + * + * Latch1 + */ +#define SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK (0x20000UL) +#define SEI_CTRL_IRQ_INT_FLAG_LATCH1_SHIFT (17U) +#define SEI_CTRL_IRQ_INT_FLAG_LATCH1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH1_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH1_SHIFT) + +/* + * LATCH0 (W1C) + * + * Latch0 + */ +#define SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK (0x10000UL) +#define SEI_CTRL_IRQ_INT_FLAG_LATCH0_SHIFT (16U) +#define SEI_CTRL_IRQ_INT_FLAG_LATCH0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH0_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH0_SHIFT) + +/* + * TIMEOUT (W1C) + * + * Timeout + */ +#define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK (0x2000U) +#define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SHIFT (13U) +#define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SHIFT) + +/* + * TRX_ERR (W1C) + * + * Transfer error + */ +#define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK (0x1000U) +#define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SHIFT (12U) +#define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SHIFT) + +/* + * INSTR1_END (W1C) + * + * Instruction 1 end + */ +#define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK (0x800U) +#define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SHIFT (11U) +#define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SHIFT) + +/* + * INSTR0_END (W1C) + * + * Instruction 0 end + */ +#define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK (0x400U) +#define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SHIFT (10U) +#define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SHIFT) + +/* + * PTR1_END (W1C) + * + * Pointer 1 end + */ +#define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK (0x200U) +#define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SHIFT (9U) +#define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SHIFT) + +/* + * PTR0_END (W1C) + * + * Pointer 0 end + */ +#define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK (0x100U) +#define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SHIFT (8U) +#define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SHIFT) + +/* + * INSTR1_ST (W1C) + * + * Instruction 1 start + */ +#define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK (0x80U) +#define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SHIFT (7U) +#define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SHIFT) + +/* + * INSTR0_ST (W1C) + * + * Instruction 0 start + */ +#define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK (0x40U) +#define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SHIFT (6U) +#define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SHIFT) + +/* + * PTR1_ST (W1C) + * + * Pointer 1 start + */ +#define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK (0x20U) +#define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SHIFT (5U) +#define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SHIFT) + +/* + * PTR0_ST (W1C) + * + * Pointer 0 start + */ +#define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK (0x10U) +#define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SHIFT (4U) +#define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SHIFT) + +/* + * WDOG (W1C) + * + * Watch dog + */ +#define SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK (0x4U) +#define SEI_CTRL_IRQ_INT_FLAG_WDOG_SHIFT (2U) +#define SEI_CTRL_IRQ_INT_FLAG_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_WDOG_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK) >> SEI_CTRL_IRQ_INT_FLAG_WDOG_SHIFT) + +/* + * EXECPT (W1C) + * + * Exception + */ +#define SEI_CTRL_IRQ_INT_FLAG_EXECPT_MASK (0x2U) +#define SEI_CTRL_IRQ_INT_FLAG_EXECPT_SHIFT (1U) +#define SEI_CTRL_IRQ_INT_FLAG_EXECPT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_EXECPT_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_EXECPT_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_EXECPT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_EXECPT_MASK) >> SEI_CTRL_IRQ_INT_FLAG_EXECPT_SHIFT) + +/* + * STALL (W1C) + * + * Stall + */ +#define SEI_CTRL_IRQ_INT_FLAG_STALL_MASK (0x1U) +#define SEI_CTRL_IRQ_INT_FLAG_STALL_SHIFT (0U) +#define SEI_CTRL_IRQ_INT_FLAG_STALL_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_STALL_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_STALL_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_STALL_MASK) >> SEI_CTRL_IRQ_INT_FLAG_STALL_SHIFT) + +/* Bitfield definition for register of struct array CTRL: INT_STS */ +/* + * TRG_ERR3 (RO) + * + * Trigger3 failed + */ +#define SEI_CTRL_IRQ_INT_STS_TRG_ERR3_MASK (0x80000000UL) +#define SEI_CTRL_IRQ_INT_STS_TRG_ERR3_SHIFT (31U) +#define SEI_CTRL_IRQ_INT_STS_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR3_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR3_SHIFT) + +/* + * TRG_ERR2 (RO) + * + * Trigger2 failed + */ +#define SEI_CTRL_IRQ_INT_STS_TRG_ERR2_MASK (0x40000000UL) +#define SEI_CTRL_IRQ_INT_STS_TRG_ERR2_SHIFT (30U) +#define SEI_CTRL_IRQ_INT_STS_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR2_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR2_SHIFT) + +/* + * TRG_ERR1 (RO) + * + * Trigger1 failed + */ +#define SEI_CTRL_IRQ_INT_STS_TRG_ERR1_MASK (0x20000000UL) +#define SEI_CTRL_IRQ_INT_STS_TRG_ERR1_SHIFT (29U) +#define SEI_CTRL_IRQ_INT_STS_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR1_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR1_SHIFT) + +/* + * TRG_ERR0 (RO) + * + * Trigger0 failed + */ +#define SEI_CTRL_IRQ_INT_STS_TRG_ERR0_MASK (0x10000000UL) +#define SEI_CTRL_IRQ_INT_STS_TRG_ERR0_SHIFT (28U) +#define SEI_CTRL_IRQ_INT_STS_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR0_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR0_SHIFT) + +/* + * TRIGER3 (RO) + * + * Trigger3 + */ +#define SEI_CTRL_IRQ_INT_STS_TRIGER3_MASK (0x8000000UL) +#define SEI_CTRL_IRQ_INT_STS_TRIGER3_SHIFT (27U) +#define SEI_CTRL_IRQ_INT_STS_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER3_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER3_SHIFT) + +/* + * TRIGER2 (RO) + * + * Trigger2 + */ +#define SEI_CTRL_IRQ_INT_STS_TRIGER2_MASK (0x4000000UL) +#define SEI_CTRL_IRQ_INT_STS_TRIGER2_SHIFT (26U) +#define SEI_CTRL_IRQ_INT_STS_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER2_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER2_SHIFT) + +/* + * TRIGER1 (RO) + * + * Trigger1 + */ +#define SEI_CTRL_IRQ_INT_STS_TRIGER1_MASK (0x2000000UL) +#define SEI_CTRL_IRQ_INT_STS_TRIGER1_SHIFT (25U) +#define SEI_CTRL_IRQ_INT_STS_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER1_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER1_SHIFT) + +/* + * TRIGER0 (RO) + * + * Trigger0 + */ +#define SEI_CTRL_IRQ_INT_STS_TRIGER0_MASK (0x1000000UL) +#define SEI_CTRL_IRQ_INT_STS_TRIGER0_SHIFT (24U) +#define SEI_CTRL_IRQ_INT_STS_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER0_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER0_SHIFT) + +/* + * SMP_ERR (RO) + * + * Sample error + */ +#define SEI_CTRL_IRQ_INT_STS_SMP_ERR_MASK (0x100000UL) +#define SEI_CTRL_IRQ_INT_STS_SMP_ERR_SHIFT (20U) +#define SEI_CTRL_IRQ_INT_STS_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_SMP_ERR_MASK) >> SEI_CTRL_IRQ_INT_STS_SMP_ERR_SHIFT) + +/* + * LATCH3 (RO) + * + * Latch3 + */ +#define SEI_CTRL_IRQ_INT_STS_LATCH3_MASK (0x80000UL) +#define SEI_CTRL_IRQ_INT_STS_LATCH3_SHIFT (19U) +#define SEI_CTRL_IRQ_INT_STS_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH3_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH3_SHIFT) + +/* + * LATCH2 (RO) + * + * Latch2 + */ +#define SEI_CTRL_IRQ_INT_STS_LATCH2_MASK (0x40000UL) +#define SEI_CTRL_IRQ_INT_STS_LATCH2_SHIFT (18U) +#define SEI_CTRL_IRQ_INT_STS_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH2_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH2_SHIFT) + +/* + * LATCH1 (RO) + * + * Latch1 + */ +#define SEI_CTRL_IRQ_INT_STS_LATCH1_MASK (0x20000UL) +#define SEI_CTRL_IRQ_INT_STS_LATCH1_SHIFT (17U) +#define SEI_CTRL_IRQ_INT_STS_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH1_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH1_SHIFT) + +/* + * LATCH0 (RO) + * + * Latch0 + */ +#define SEI_CTRL_IRQ_INT_STS_LATCH0_MASK (0x10000UL) +#define SEI_CTRL_IRQ_INT_STS_LATCH0_SHIFT (16U) +#define SEI_CTRL_IRQ_INT_STS_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH0_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH0_SHIFT) + +/* + * TIMEOUT (RO) + * + * Timeout + */ +#define SEI_CTRL_IRQ_INT_STS_TIMEOUT_MASK (0x2000U) +#define SEI_CTRL_IRQ_INT_STS_TIMEOUT_SHIFT (13U) +#define SEI_CTRL_IRQ_INT_STS_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TIMEOUT_MASK) >> SEI_CTRL_IRQ_INT_STS_TIMEOUT_SHIFT) + +/* + * TRX_ERR (RO) + * + * Transfer error + */ +#define SEI_CTRL_IRQ_INT_STS_TRX_ERR_MASK (0x1000U) +#define SEI_CTRL_IRQ_INT_STS_TRX_ERR_SHIFT (12U) +#define SEI_CTRL_IRQ_INT_STS_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRX_ERR_MASK) >> SEI_CTRL_IRQ_INT_STS_TRX_ERR_SHIFT) + +/* + * INSTR1_END (RO) + * + * Instruction 1 end + */ +#define SEI_CTRL_IRQ_INT_STS_INSTR1_END_MASK (0x800U) +#define SEI_CTRL_IRQ_INT_STS_INSTR1_END_SHIFT (11U) +#define SEI_CTRL_IRQ_INT_STS_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR1_END_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR1_END_SHIFT) + +/* + * INSTR0_END (RO) + * + * Instruction 0 end + */ +#define SEI_CTRL_IRQ_INT_STS_INSTR0_END_MASK (0x400U) +#define SEI_CTRL_IRQ_INT_STS_INSTR0_END_SHIFT (10U) +#define SEI_CTRL_IRQ_INT_STS_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR0_END_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR0_END_SHIFT) + +/* + * PTR1_END (RO) + * + * Pointer 1 end + */ +#define SEI_CTRL_IRQ_INT_STS_PTR1_END_MASK (0x200U) +#define SEI_CTRL_IRQ_INT_STS_PTR1_END_SHIFT (9U) +#define SEI_CTRL_IRQ_INT_STS_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR1_END_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR1_END_SHIFT) + +/* + * PTR0_END (RO) + * + * Pointer 0 end + */ +#define SEI_CTRL_IRQ_INT_STS_PTR0_END_MASK (0x100U) +#define SEI_CTRL_IRQ_INT_STS_PTR0_END_SHIFT (8U) +#define SEI_CTRL_IRQ_INT_STS_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR0_END_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR0_END_SHIFT) + +/* + * INSTR1_ST (RO) + * + * Instruction 1 start + */ +#define SEI_CTRL_IRQ_INT_STS_INSTR1_ST_MASK (0x80U) +#define SEI_CTRL_IRQ_INT_STS_INSTR1_ST_SHIFT (7U) +#define SEI_CTRL_IRQ_INT_STS_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR1_ST_SHIFT) + +/* + * INSTR0_ST (RO) + * + * Instruction 0 start + */ +#define SEI_CTRL_IRQ_INT_STS_INSTR0_ST_MASK (0x40U) +#define SEI_CTRL_IRQ_INT_STS_INSTR0_ST_SHIFT (6U) +#define SEI_CTRL_IRQ_INT_STS_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR0_ST_SHIFT) + +/* + * PTR1_ST (RO) + * + * Pointer 1 start + */ +#define SEI_CTRL_IRQ_INT_STS_PTR1_ST_MASK (0x20U) +#define SEI_CTRL_IRQ_INT_STS_PTR1_ST_SHIFT (5U) +#define SEI_CTRL_IRQ_INT_STS_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR1_ST_SHIFT) + +/* + * PTR0_ST (RO) + * + * Pointer 0 start + */ +#define SEI_CTRL_IRQ_INT_STS_PTR0_ST_MASK (0x10U) +#define SEI_CTRL_IRQ_INT_STS_PTR0_ST_SHIFT (4U) +#define SEI_CTRL_IRQ_INT_STS_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR0_ST_SHIFT) + +/* + * WDOG (RO) + * + * Watch dog + */ +#define SEI_CTRL_IRQ_INT_STS_WDOG_MASK (0x4U) +#define SEI_CTRL_IRQ_INT_STS_WDOG_SHIFT (2U) +#define SEI_CTRL_IRQ_INT_STS_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_WDOG_MASK) >> SEI_CTRL_IRQ_INT_STS_WDOG_SHIFT) + +/* + * EXECPT (RO) + * + * Exception + */ +#define SEI_CTRL_IRQ_INT_STS_EXECPT_MASK (0x2U) +#define SEI_CTRL_IRQ_INT_STS_EXECPT_SHIFT (1U) +#define SEI_CTRL_IRQ_INT_STS_EXECPT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_EXECPT_MASK) >> SEI_CTRL_IRQ_INT_STS_EXECPT_SHIFT) + +/* + * STALL (RO) + * + * Stall + */ +#define SEI_CTRL_IRQ_INT_STS_STALL_MASK (0x1U) +#define SEI_CTRL_IRQ_INT_STS_STALL_SHIFT (0U) +#define SEI_CTRL_IRQ_INT_STS_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_STALL_MASK) >> SEI_CTRL_IRQ_INT_STS_STALL_SHIFT) + +/* Bitfield definition for register of struct array CTRL: POINTER0 */ +/* + * POINTER (RW) + * + * Match pointer 0 + */ +#define SEI_CTRL_IRQ_POINTER0_POINTER_MASK (0xFFU) +#define SEI_CTRL_IRQ_POINTER0_POINTER_SHIFT (0U) +#define SEI_CTRL_IRQ_POINTER0_POINTER_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_POINTER0_POINTER_SHIFT) & SEI_CTRL_IRQ_POINTER0_POINTER_MASK) +#define SEI_CTRL_IRQ_POINTER0_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_POINTER0_POINTER_MASK) >> SEI_CTRL_IRQ_POINTER0_POINTER_SHIFT) + +/* Bitfield definition for register of struct array CTRL: POINTER1 */ +/* + * POINTER (RW) + * + * Match pointer 1 + */ +#define SEI_CTRL_IRQ_POINTER1_POINTER_MASK (0xFFU) +#define SEI_CTRL_IRQ_POINTER1_POINTER_SHIFT (0U) +#define SEI_CTRL_IRQ_POINTER1_POINTER_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_POINTER1_POINTER_SHIFT) & SEI_CTRL_IRQ_POINTER1_POINTER_MASK) +#define SEI_CTRL_IRQ_POINTER1_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_POINTER1_POINTER_MASK) >> SEI_CTRL_IRQ_POINTER1_POINTER_SHIFT) + +/* Bitfield definition for register of struct array CTRL: INSTR0 */ +/* + * INSTR (RW) + * + * Match instruction 0 + */ +#define SEI_CTRL_IRQ_INSTR0_INSTR_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_IRQ_INSTR0_INSTR_SHIFT (0U) +#define SEI_CTRL_IRQ_INSTR0_INSTR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INSTR0_INSTR_SHIFT) & SEI_CTRL_IRQ_INSTR0_INSTR_MASK) +#define SEI_CTRL_IRQ_INSTR0_INSTR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INSTR0_INSTR_MASK) >> SEI_CTRL_IRQ_INSTR0_INSTR_SHIFT) + +/* Bitfield definition for register of struct array CTRL: INSTR1 */ +/* + * INSTR (RW) + * + * Match instruction 1 + */ +#define SEI_CTRL_IRQ_INSTR1_INSTR_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_IRQ_INSTR1_INSTR_SHIFT (0U) +#define SEI_CTRL_IRQ_INSTR1_INSTR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INSTR1_INSTR_SHIFT) & SEI_CTRL_IRQ_INSTR1_INSTR_MASK) +#define SEI_CTRL_IRQ_INSTR1_INSTR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INSTR1_INSTR_MASK) >> SEI_CTRL_IRQ_INSTR1_INSTR_SHIFT) + +/* Bitfield definition for register array: INSTR */ +/* + * OP (RW) + * + * operation + * 0: halt + * 1: jump + * 2: send with timeout check + * 3: send without timout check + * 4: wait with timeout check + * 5: wait without timout check + * 6: receive with timeout check + * 7: receive without timout check + */ +#define SEI_INSTR_OP_MASK (0x1C000000UL) +#define SEI_INSTR_OP_SHIFT (26U) +#define SEI_INSTR_OP_SET(x) (((uint32_t)(x) << SEI_INSTR_OP_SHIFT) & SEI_INSTR_OP_MASK) +#define SEI_INSTR_OP_GET(x) (((uint32_t)(x) & SEI_INSTR_OP_MASK) >> SEI_INSTR_OP_SHIFT) + +/* + * CK (RW) + * + * clock + * 0: low + * 1: rise-fall + * 2: fall-rise + * 3: high + */ +#define SEI_INSTR_CK_MASK (0x3000000UL) +#define SEI_INSTR_CK_SHIFT (24U) +#define SEI_INSTR_CK_SET(x) (((uint32_t)(x) << SEI_INSTR_CK_SHIFT) & SEI_INSTR_CK_MASK) +#define SEI_INSTR_CK_GET(x) (((uint32_t)(x) & SEI_INSTR_CK_MASK) >> SEI_INSTR_CK_SHIFT) + +/* + * CRC (RW) + * + * CRC register + * 0: don't calculate CRC + * 1: do not set this value + * 2: data register 2 + * 3: data register 3 + * ... + * 29: data register 29 + * 30: value 0 when send, wait 0 in receive + * 31: value1 when send, wait 1 in receive + */ +#define SEI_INSTR_CRC_MASK (0x1F0000UL) +#define SEI_INSTR_CRC_SHIFT (16U) +#define SEI_INSTR_CRC_SET(x) (((uint32_t)(x) << SEI_INSTR_CRC_SHIFT) & SEI_INSTR_CRC_MASK) +#define SEI_INSTR_CRC_GET(x) (((uint32_t)(x) & SEI_INSTR_CRC_MASK) >> SEI_INSTR_CRC_SHIFT) + +/* + * DAT (RW) + * + * DATA register + * 0: ignore data + * 1: command + * 2: data register 2 + * 3: data register 3 + * ... + * 29: data register 29 + * 30: value 0 when send, wait 0 in receive + * 31: value1 when send, wait 1 in receive + */ +#define SEI_INSTR_DAT_MASK (0x1F00U) +#define SEI_INSTR_DAT_SHIFT (8U) +#define SEI_INSTR_DAT_SET(x) (((uint32_t)(x) << SEI_INSTR_DAT_SHIFT) & SEI_INSTR_DAT_MASK) +#define SEI_INSTR_DAT_GET(x) (((uint32_t)(x) & SEI_INSTR_DAT_MASK) >> SEI_INSTR_DAT_SHIFT) + +/* + * OPR (RW) + * + * [1] When OP is 0, this area is the halt time in baudrate, 0 represents infinite time. + * [2] When OP is 1, this area is the the pointer to the command table. + * OPR[4]=1, OPR[3:0] value is CMD_TABLE instruct pointer; + * OPR[4]=0, OPR[3:0]=0 is INIT_POINTER; + * OPR[4]=0, OPR[3:0]=1 is WDG_POINTER. + * [3] When OP is 2-7, this area is the data length as fellow: + * 0: 1 bit + * 1: 2 bit + * ... + * 31: 32 bit + */ +#define SEI_INSTR_OPR_MASK (0x1FU) +#define SEI_INSTR_OPR_SHIFT (0U) +#define SEI_INSTR_OPR_SET(x) (((uint32_t)(x) << SEI_INSTR_OPR_SHIFT) & SEI_INSTR_OPR_MASK) +#define SEI_INSTR_OPR_GET(x) (((uint32_t)(x) & SEI_INSTR_OPR_MASK) >> SEI_INSTR_OPR_SHIFT) + +/* Bitfield definition for register of struct array DAT: MODE */ +/* + * CRC_LEN (RW) + * + * CRC length + * 0: 1 bit + * 1: 2 bit + * ... + * 31: 32 bit + */ +#define SEI_DAT_MODE_CRC_LEN_MASK (0x1F000000UL) +#define SEI_DAT_MODE_CRC_LEN_SHIFT (24U) +#define SEI_DAT_MODE_CRC_LEN_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_CRC_LEN_SHIFT) & SEI_DAT_MODE_CRC_LEN_MASK) +#define SEI_DAT_MODE_CRC_LEN_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_CRC_LEN_MASK) >> SEI_DAT_MODE_CRC_LEN_SHIFT) + +/* + * WLEN (RW) + * + * word length + * 0: 1 bit + * 1: 2 bit + * ... + * 31: 32 bit + */ +#define SEI_DAT_MODE_WLEN_MASK (0x1F0000UL) +#define SEI_DAT_MODE_WLEN_SHIFT (16U) +#define SEI_DAT_MODE_WLEN_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_WLEN_SHIFT) & SEI_DAT_MODE_WLEN_MASK) +#define SEI_DAT_MODE_WLEN_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_WLEN_MASK) >> SEI_DAT_MODE_WLEN_SHIFT) + +/* + * CRC_SHIFT (RW) + * + * CRC shift mode, this mode is used to perform repeat code check + * 0: CRC + * 1: shift mode + */ +#define SEI_DAT_MODE_CRC_SHIFT_MASK (0x2000U) +#define SEI_DAT_MODE_CRC_SHIFT_SHIFT (13U) +#define SEI_DAT_MODE_CRC_SHIFT_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_CRC_SHIFT_SHIFT) & SEI_DAT_MODE_CRC_SHIFT_MASK) +#define SEI_DAT_MODE_CRC_SHIFT_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_CRC_SHIFT_MASK) >> SEI_DAT_MODE_CRC_SHIFT_SHIFT) + +/* + * CRC_INV (RW) + * + * CRC invert + * 0: use CRC + * 1: use inverted CRC + */ +#define SEI_DAT_MODE_CRC_INV_MASK (0x1000U) +#define SEI_DAT_MODE_CRC_INV_SHIFT (12U) +#define SEI_DAT_MODE_CRC_INV_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_CRC_INV_SHIFT) & SEI_DAT_MODE_CRC_INV_MASK) +#define SEI_DAT_MODE_CRC_INV_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_CRC_INV_MASK) >> SEI_DAT_MODE_CRC_INV_SHIFT) + +/* + * WORDER (RW) + * + * word order + * 0: sample as bit order + * 1: different from bit order + */ +#define SEI_DAT_MODE_WORDER_MASK (0x800U) +#define SEI_DAT_MODE_WORDER_SHIFT (11U) +#define SEI_DAT_MODE_WORDER_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_WORDER_SHIFT) & SEI_DAT_MODE_WORDER_MASK) +#define SEI_DAT_MODE_WORDER_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_WORDER_MASK) >> SEI_DAT_MODE_WORDER_SHIFT) + +/* + * BORDER (RW) + * + * bit order + * 0: LSB first + * 1: MSB first + */ +#define SEI_DAT_MODE_BORDER_MASK (0x400U) +#define SEI_DAT_MODE_BORDER_SHIFT (10U) +#define SEI_DAT_MODE_BORDER_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_BORDER_SHIFT) & SEI_DAT_MODE_BORDER_MASK) +#define SEI_DAT_MODE_BORDER_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_BORDER_MASK) >> SEI_DAT_MODE_BORDER_SHIFT) + +/* + * SIGNED (RW) + * + * Signed + * 0: unsigned value + * 1: signed value + */ +#define SEI_DAT_MODE_SIGNED_MASK (0x200U) +#define SEI_DAT_MODE_SIGNED_SHIFT (9U) +#define SEI_DAT_MODE_SIGNED_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_SIGNED_SHIFT) & SEI_DAT_MODE_SIGNED_MASK) +#define SEI_DAT_MODE_SIGNED_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_SIGNED_MASK) >> SEI_DAT_MODE_SIGNED_SHIFT) + +/* + * REWIND (RW) + * + * Write 1 to rewind read/write pointer, this is a self clear bit + */ +#define SEI_DAT_MODE_REWIND_MASK (0x100U) +#define SEI_DAT_MODE_REWIND_SHIFT (8U) +#define SEI_DAT_MODE_REWIND_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_REWIND_SHIFT) & SEI_DAT_MODE_REWIND_MASK) +#define SEI_DAT_MODE_REWIND_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_REWIND_MASK) >> SEI_DAT_MODE_REWIND_SHIFT) + +/* + * MODE (RW) + * + * Data mode + * 0: data mode + * 1: check mode + * 2: CRC mode + */ +#define SEI_DAT_MODE_MODE_MASK (0x3U) +#define SEI_DAT_MODE_MODE_SHIFT (0U) +#define SEI_DAT_MODE_MODE_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_MODE_SHIFT) & SEI_DAT_MODE_MODE_MASK) +#define SEI_DAT_MODE_MODE_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_MODE_MASK) >> SEI_DAT_MODE_MODE_SHIFT) + +/* Bitfield definition for register of struct array DAT: IDX */ +/* + * LAST_BIT (RW) + * + * Last bit index for tranceive + */ +#define SEI_DAT_IDX_LAST_BIT_MASK (0x1F000000UL) +#define SEI_DAT_IDX_LAST_BIT_SHIFT (24U) +#define SEI_DAT_IDX_LAST_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_LAST_BIT_SHIFT) & SEI_DAT_IDX_LAST_BIT_MASK) +#define SEI_DAT_IDX_LAST_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_LAST_BIT_MASK) >> SEI_DAT_IDX_LAST_BIT_SHIFT) + +/* + * FIRST_BIT (RW) + * + * First bit index for tranceive + */ +#define SEI_DAT_IDX_FIRST_BIT_MASK (0x1F0000UL) +#define SEI_DAT_IDX_FIRST_BIT_SHIFT (16U) +#define SEI_DAT_IDX_FIRST_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_FIRST_BIT_SHIFT) & SEI_DAT_IDX_FIRST_BIT_MASK) +#define SEI_DAT_IDX_FIRST_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_FIRST_BIT_MASK) >> SEI_DAT_IDX_FIRST_BIT_SHIFT) + +/* + * MAX_BIT (RW) + * + * Highest bit index + */ +#define SEI_DAT_IDX_MAX_BIT_MASK (0x1F00U) +#define SEI_DAT_IDX_MAX_BIT_SHIFT (8U) +#define SEI_DAT_IDX_MAX_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_MAX_BIT_SHIFT) & SEI_DAT_IDX_MAX_BIT_MASK) +#define SEI_DAT_IDX_MAX_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_MAX_BIT_MASK) >> SEI_DAT_IDX_MAX_BIT_SHIFT) + +/* + * MIN_BIT (RW) + * + * Lowest bit index + */ +#define SEI_DAT_IDX_MIN_BIT_MASK (0x1FU) +#define SEI_DAT_IDX_MIN_BIT_SHIFT (0U) +#define SEI_DAT_IDX_MIN_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_MIN_BIT_SHIFT) & SEI_DAT_IDX_MIN_BIT_MASK) +#define SEI_DAT_IDX_MIN_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_MIN_BIT_MASK) >> SEI_DAT_IDX_MIN_BIT_SHIFT) + +/* Bitfield definition for register of struct array DAT: GOLD */ +/* + * GOLD_VALUE (RW) + * + * Gold value for check mode + */ +#define SEI_DAT_GOLD_GOLD_VALUE_MASK (0xFFFFFFFFUL) +#define SEI_DAT_GOLD_GOLD_VALUE_SHIFT (0U) +#define SEI_DAT_GOLD_GOLD_VALUE_SET(x) (((uint32_t)(x) << SEI_DAT_GOLD_GOLD_VALUE_SHIFT) & SEI_DAT_GOLD_GOLD_VALUE_MASK) +#define SEI_DAT_GOLD_GOLD_VALUE_GET(x) (((uint32_t)(x) & SEI_DAT_GOLD_GOLD_VALUE_MASK) >> SEI_DAT_GOLD_GOLD_VALUE_SHIFT) + +/* Bitfield definition for register of struct array DAT: CRCINIT */ +/* + * CRC_INIT (RW) + * + * CRC initial value + */ +#define SEI_DAT_CRCINIT_CRC_INIT_MASK (0xFFFFFFFFUL) +#define SEI_DAT_CRCINIT_CRC_INIT_SHIFT (0U) +#define SEI_DAT_CRCINIT_CRC_INIT_SET(x) (((uint32_t)(x) << SEI_DAT_CRCINIT_CRC_INIT_SHIFT) & SEI_DAT_CRCINIT_CRC_INIT_MASK) +#define SEI_DAT_CRCINIT_CRC_INIT_GET(x) (((uint32_t)(x) & SEI_DAT_CRCINIT_CRC_INIT_MASK) >> SEI_DAT_CRCINIT_CRC_INIT_SHIFT) + +/* Bitfield definition for register of struct array DAT: CRCPOLY */ +/* + * CRC_POLY (RW) + * + * CRC polymonial + */ +#define SEI_DAT_CRCPOLY_CRC_POLY_MASK (0xFFFFFFFFUL) +#define SEI_DAT_CRCPOLY_CRC_POLY_SHIFT (0U) +#define SEI_DAT_CRCPOLY_CRC_POLY_SET(x) (((uint32_t)(x) << SEI_DAT_CRCPOLY_CRC_POLY_SHIFT) & SEI_DAT_CRCPOLY_CRC_POLY_MASK) +#define SEI_DAT_CRCPOLY_CRC_POLY_GET(x) (((uint32_t)(x) & SEI_DAT_CRCPOLY_CRC_POLY_MASK) >> SEI_DAT_CRCPOLY_CRC_POLY_SHIFT) + +/* Bitfield definition for register of struct array DAT: DATA */ +/* + * DATA (RW) + * + * DATA + */ +#define SEI_DAT_DATA_DATA_MASK (0xFFFFFFFFUL) +#define SEI_DAT_DATA_DATA_SHIFT (0U) +#define SEI_DAT_DATA_DATA_SET(x) (((uint32_t)(x) << SEI_DAT_DATA_DATA_SHIFT) & SEI_DAT_DATA_DATA_MASK) +#define SEI_DAT_DATA_DATA_GET(x) (((uint32_t)(x) & SEI_DAT_DATA_DATA_MASK) >> SEI_DAT_DATA_DATA_SHIFT) + +/* Bitfield definition for register of struct array DAT: SET */ +/* + * DATA_SET (RW) + * + * DATA bit set + */ +#define SEI_DAT_SET_DATA_SET_MASK (0xFFFFFFFFUL) +#define SEI_DAT_SET_DATA_SET_SHIFT (0U) +#define SEI_DAT_SET_DATA_SET_SET(x) (((uint32_t)(x) << SEI_DAT_SET_DATA_SET_SHIFT) & SEI_DAT_SET_DATA_SET_MASK) +#define SEI_DAT_SET_DATA_SET_GET(x) (((uint32_t)(x) & SEI_DAT_SET_DATA_SET_MASK) >> SEI_DAT_SET_DATA_SET_SHIFT) + +/* Bitfield definition for register of struct array DAT: CLR */ +/* + * DATA_CLR (RW) + * + * DATA bit clear + */ +#define SEI_DAT_CLR_DATA_CLR_MASK (0xFFFFFFFFUL) +#define SEI_DAT_CLR_DATA_CLR_SHIFT (0U) +#define SEI_DAT_CLR_DATA_CLR_SET(x) (((uint32_t)(x) << SEI_DAT_CLR_DATA_CLR_SHIFT) & SEI_DAT_CLR_DATA_CLR_MASK) +#define SEI_DAT_CLR_DATA_CLR_GET(x) (((uint32_t)(x) & SEI_DAT_CLR_DATA_CLR_MASK) >> SEI_DAT_CLR_DATA_CLR_SHIFT) + +/* Bitfield definition for register of struct array DAT: INV */ +/* + * DATA_INV (RW) + * + * DATA bit toggle + */ +#define SEI_DAT_INV_DATA_INV_MASK (0xFFFFFFFFUL) +#define SEI_DAT_INV_DATA_INV_SHIFT (0U) +#define SEI_DAT_INV_DATA_INV_SET(x) (((uint32_t)(x) << SEI_DAT_INV_DATA_INV_SHIFT) & SEI_DAT_INV_DATA_INV_MASK) +#define SEI_DAT_INV_DATA_INV_GET(x) (((uint32_t)(x) & SEI_DAT_INV_DATA_INV_MASK) >> SEI_DAT_INV_DATA_INV_SHIFT) + +/* Bitfield definition for register of struct array DAT: IN */ +/* + * DATA_IN (RO) + * + * Data input + */ +#define SEI_DAT_IN_DATA_IN_MASK (0xFFFFFFFFUL) +#define SEI_DAT_IN_DATA_IN_SHIFT (0U) +#define SEI_DAT_IN_DATA_IN_GET(x) (((uint32_t)(x) & SEI_DAT_IN_DATA_IN_MASK) >> SEI_DAT_IN_DATA_IN_SHIFT) + +/* Bitfield definition for register of struct array DAT: OUT */ +/* + * DATA_OUT (RO) + * + * Data output + */ +#define SEI_DAT_OUT_DATA_OUT_MASK (0xFFFFFFFFUL) +#define SEI_DAT_OUT_DATA_OUT_SHIFT (0U) +#define SEI_DAT_OUT_DATA_OUT_GET(x) (((uint32_t)(x) & SEI_DAT_OUT_DATA_OUT_MASK) >> SEI_DAT_OUT_DATA_OUT_SHIFT) + +/* Bitfield definition for register of struct array DAT: STS */ +/* + * CRC_IDX (RO) + * + * CRC index + */ +#define SEI_DAT_STS_CRC_IDX_MASK (0x1F000000UL) +#define SEI_DAT_STS_CRC_IDX_SHIFT (24U) +#define SEI_DAT_STS_CRC_IDX_GET(x) (((uint32_t)(x) & SEI_DAT_STS_CRC_IDX_MASK) >> SEI_DAT_STS_CRC_IDX_SHIFT) + +/* + * WORD_IDX (RO) + * + * Word index + */ +#define SEI_DAT_STS_WORD_IDX_MASK (0x1F0000UL) +#define SEI_DAT_STS_WORD_IDX_SHIFT (16U) +#define SEI_DAT_STS_WORD_IDX_GET(x) (((uint32_t)(x) & SEI_DAT_STS_WORD_IDX_MASK) >> SEI_DAT_STS_WORD_IDX_SHIFT) + +/* + * WORD_CNT (RO) + * + * Word counter + */ +#define SEI_DAT_STS_WORD_CNT_MASK (0x1F00U) +#define SEI_DAT_STS_WORD_CNT_SHIFT (8U) +#define SEI_DAT_STS_WORD_CNT_GET(x) (((uint32_t)(x) & SEI_DAT_STS_WORD_CNT_MASK) >> SEI_DAT_STS_WORD_CNT_SHIFT) + +/* + * BIT_IDX (RO) + * + * Bit index + */ +#define SEI_DAT_STS_BIT_IDX_MASK (0x1FU) +#define SEI_DAT_STS_BIT_IDX_SHIFT (0U) +#define SEI_DAT_STS_BIT_IDX_GET(x) (((uint32_t)(x) & SEI_DAT_STS_BIT_IDX_MASK) >> SEI_DAT_STS_BIT_IDX_SHIFT) + + + +/* CMD register group index macro definition */ +#define SEI_CTRL_TRG_TABLE_CMD_0 (0UL) +#define SEI_CTRL_TRG_TABLE_CMD_1 (1UL) +#define SEI_CTRL_TRG_TABLE_CMD_2 (2UL) +#define SEI_CTRL_TRG_TABLE_CMD_3 (3UL) + +/* TIME register group index macro definition */ +#define SEI_CTRL_TRG_TABLE_TIME_0 (0UL) +#define SEI_CTRL_TRG_TABLE_TIME_1 (1UL) +#define SEI_CTRL_TRG_TABLE_TIME_2 (2UL) +#define SEI_CTRL_TRG_TABLE_TIME_3 (3UL) + +/* CMD_TABLE register group index macro definition */ +#define SEI_CMD_TABLE_0 (0UL) +#define SEI_CMD_TABLE_1 (1UL) +#define SEI_CMD_TABLE_2 (2UL) +#define SEI_CMD_TABLE_3 (3UL) +#define SEI_CMD_TABLE_4 (4UL) +#define SEI_CMD_TABLE_5 (5UL) +#define SEI_CMD_TABLE_6 (6UL) +#define SEI_CMD_TABLE_7 (7UL) + +/* TRAN register group index macro definition */ +#define SEI_CTRL_LATCH_TRAN_0_1 (0UL) +#define SEI_CTRL_LATCH_TRAN_1_2 (1UL) +#define SEI_CTRL_LATCH_TRAN_2_3 (2UL) +#define SEI_CTRL_LATCH_TRAN_3_0 (3UL) + +/* LATCH register group index macro definition */ +#define SEI_LATCH_0 (0UL) +#define SEI_LATCH_1 (1UL) +#define SEI_LATCH_2 (2UL) +#define SEI_LATCH_3 (3UL) + +/* CTRL register group index macro definition */ +#define SEI_CTRL_0 (0UL) +#define SEI_CTRL_1 (1UL) +#define SEI_CTRL_2 (2UL) +#define SEI_CTRL_3 (3UL) +#define SEI_CTRL_4 (4UL) +#define SEI_CTRL_5 (5UL) +#define SEI_CTRL_6 (6UL) +#define SEI_CTRL_7 (7UL) +#define SEI_CTRL_8 (8UL) +#define SEI_CTRL_9 (9UL) +#define SEI_CTRL_10 (10UL) +#define SEI_CTRL_11 (11UL) +#define SEI_CTRL_12 (12UL) + +/* INSTR register group index macro definition */ +#define SEI_INSTR_0 (0UL) +#define SEI_INSTR_1 (1UL) +#define SEI_INSTR_2 (2UL) +#define SEI_INSTR_3 (3UL) +#define SEI_INSTR_4 (4UL) +#define SEI_INSTR_5 (5UL) +#define SEI_INSTR_6 (6UL) +#define SEI_INSTR_7 (7UL) +#define SEI_INSTR_8 (8UL) +#define SEI_INSTR_9 (9UL) +#define SEI_INSTR_10 (10UL) +#define SEI_INSTR_11 (11UL) +#define SEI_INSTR_12 (12UL) +#define SEI_INSTR_13 (13UL) +#define SEI_INSTR_14 (14UL) +#define SEI_INSTR_15 (15UL) +#define SEI_INSTR_16 (16UL) +#define SEI_INSTR_17 (17UL) +#define SEI_INSTR_18 (18UL) +#define SEI_INSTR_19 (19UL) +#define SEI_INSTR_20 (20UL) +#define SEI_INSTR_21 (21UL) +#define SEI_INSTR_22 (22UL) +#define SEI_INSTR_23 (23UL) +#define SEI_INSTR_24 (24UL) +#define SEI_INSTR_25 (25UL) +#define SEI_INSTR_26 (26UL) +#define SEI_INSTR_27 (27UL) +#define SEI_INSTR_28 (28UL) +#define SEI_INSTR_29 (29UL) +#define SEI_INSTR_30 (30UL) +#define SEI_INSTR_31 (31UL) +#define SEI_INSTR_32 (32UL) +#define SEI_INSTR_33 (33UL) +#define SEI_INSTR_34 (34UL) +#define SEI_INSTR_35 (35UL) +#define SEI_INSTR_36 (36UL) +#define SEI_INSTR_37 (37UL) +#define SEI_INSTR_38 (38UL) +#define SEI_INSTR_39 (39UL) +#define SEI_INSTR_40 (40UL) +#define SEI_INSTR_41 (41UL) +#define SEI_INSTR_42 (42UL) +#define SEI_INSTR_43 (43UL) +#define SEI_INSTR_44 (44UL) +#define SEI_INSTR_45 (45UL) +#define SEI_INSTR_46 (46UL) +#define SEI_INSTR_47 (47UL) +#define SEI_INSTR_48 (48UL) +#define SEI_INSTR_49 (49UL) +#define SEI_INSTR_50 (50UL) +#define SEI_INSTR_51 (51UL) +#define SEI_INSTR_52 (52UL) +#define SEI_INSTR_53 (53UL) +#define SEI_INSTR_54 (54UL) +#define SEI_INSTR_55 (55UL) +#define SEI_INSTR_56 (56UL) +#define SEI_INSTR_57 (57UL) +#define SEI_INSTR_58 (58UL) +#define SEI_INSTR_59 (59UL) +#define SEI_INSTR_60 (60UL) +#define SEI_INSTR_61 (61UL) +#define SEI_INSTR_62 (62UL) +#define SEI_INSTR_63 (63UL) +#define SEI_INSTR_64 (64UL) +#define SEI_INSTR_65 (65UL) +#define SEI_INSTR_66 (66UL) +#define SEI_INSTR_67 (67UL) +#define SEI_INSTR_68 (68UL) +#define SEI_INSTR_69 (69UL) +#define SEI_INSTR_70 (70UL) +#define SEI_INSTR_71 (71UL) +#define SEI_INSTR_72 (72UL) +#define SEI_INSTR_73 (73UL) +#define SEI_INSTR_74 (74UL) +#define SEI_INSTR_75 (75UL) +#define SEI_INSTR_76 (76UL) +#define SEI_INSTR_77 (77UL) +#define SEI_INSTR_78 (78UL) +#define SEI_INSTR_79 (79UL) +#define SEI_INSTR_80 (80UL) +#define SEI_INSTR_81 (81UL) +#define SEI_INSTR_82 (82UL) +#define SEI_INSTR_83 (83UL) +#define SEI_INSTR_84 (84UL) +#define SEI_INSTR_85 (85UL) +#define SEI_INSTR_86 (86UL) +#define SEI_INSTR_87 (87UL) +#define SEI_INSTR_88 (88UL) +#define SEI_INSTR_89 (89UL) +#define SEI_INSTR_90 (90UL) +#define SEI_INSTR_91 (91UL) +#define SEI_INSTR_92 (92UL) +#define SEI_INSTR_93 (93UL) +#define SEI_INSTR_94 (94UL) +#define SEI_INSTR_95 (95UL) +#define SEI_INSTR_96 (96UL) +#define SEI_INSTR_97 (97UL) +#define SEI_INSTR_98 (98UL) +#define SEI_INSTR_99 (99UL) +#define SEI_INSTR_100 (100UL) +#define SEI_INSTR_101 (101UL) +#define SEI_INSTR_102 (102UL) +#define SEI_INSTR_103 (103UL) +#define SEI_INSTR_104 (104UL) +#define SEI_INSTR_105 (105UL) +#define SEI_INSTR_106 (106UL) +#define SEI_INSTR_107 (107UL) +#define SEI_INSTR_108 (108UL) +#define SEI_INSTR_109 (109UL) +#define SEI_INSTR_110 (110UL) +#define SEI_INSTR_111 (111UL) +#define SEI_INSTR_112 (112UL) +#define SEI_INSTR_113 (113UL) +#define SEI_INSTR_114 (114UL) +#define SEI_INSTR_115 (115UL) +#define SEI_INSTR_116 (116UL) +#define SEI_INSTR_117 (117UL) +#define SEI_INSTR_118 (118UL) +#define SEI_INSTR_119 (119UL) +#define SEI_INSTR_120 (120UL) +#define SEI_INSTR_121 (121UL) +#define SEI_INSTR_122 (122UL) +#define SEI_INSTR_123 (123UL) +#define SEI_INSTR_124 (124UL) +#define SEI_INSTR_125 (125UL) +#define SEI_INSTR_126 (126UL) +#define SEI_INSTR_127 (127UL) +#define SEI_INSTR_128 (128UL) +#define SEI_INSTR_129 (129UL) +#define SEI_INSTR_130 (130UL) +#define SEI_INSTR_131 (131UL) +#define SEI_INSTR_132 (132UL) +#define SEI_INSTR_133 (133UL) +#define SEI_INSTR_134 (134UL) +#define SEI_INSTR_135 (135UL) +#define SEI_INSTR_136 (136UL) +#define SEI_INSTR_137 (137UL) +#define SEI_INSTR_138 (138UL) +#define SEI_INSTR_139 (139UL) +#define SEI_INSTR_140 (140UL) +#define SEI_INSTR_141 (141UL) +#define SEI_INSTR_142 (142UL) +#define SEI_INSTR_143 (143UL) +#define SEI_INSTR_144 (144UL) +#define SEI_INSTR_145 (145UL) +#define SEI_INSTR_146 (146UL) +#define SEI_INSTR_147 (147UL) +#define SEI_INSTR_148 (148UL) +#define SEI_INSTR_149 (149UL) +#define SEI_INSTR_150 (150UL) +#define SEI_INSTR_151 (151UL) +#define SEI_INSTR_152 (152UL) +#define SEI_INSTR_153 (153UL) +#define SEI_INSTR_154 (154UL) +#define SEI_INSTR_155 (155UL) +#define SEI_INSTR_156 (156UL) +#define SEI_INSTR_157 (157UL) +#define SEI_INSTR_158 (158UL) +#define SEI_INSTR_159 (159UL) +#define SEI_INSTR_160 (160UL) +#define SEI_INSTR_161 (161UL) +#define SEI_INSTR_162 (162UL) +#define SEI_INSTR_163 (163UL) +#define SEI_INSTR_164 (164UL) +#define SEI_INSTR_165 (165UL) +#define SEI_INSTR_166 (166UL) +#define SEI_INSTR_167 (167UL) +#define SEI_INSTR_168 (168UL) +#define SEI_INSTR_169 (169UL) +#define SEI_INSTR_170 (170UL) +#define SEI_INSTR_171 (171UL) +#define SEI_INSTR_172 (172UL) +#define SEI_INSTR_173 (173UL) +#define SEI_INSTR_174 (174UL) +#define SEI_INSTR_175 (175UL) +#define SEI_INSTR_176 (176UL) +#define SEI_INSTR_177 (177UL) +#define SEI_INSTR_178 (178UL) +#define SEI_INSTR_179 (179UL) +#define SEI_INSTR_180 (180UL) +#define SEI_INSTR_181 (181UL) +#define SEI_INSTR_182 (182UL) +#define SEI_INSTR_183 (183UL) +#define SEI_INSTR_184 (184UL) +#define SEI_INSTR_185 (185UL) +#define SEI_INSTR_186 (186UL) +#define SEI_INSTR_187 (187UL) +#define SEI_INSTR_188 (188UL) +#define SEI_INSTR_189 (189UL) +#define SEI_INSTR_190 (190UL) +#define SEI_INSTR_191 (191UL) +#define SEI_INSTR_192 (192UL) +#define SEI_INSTR_193 (193UL) +#define SEI_INSTR_194 (194UL) +#define SEI_INSTR_195 (195UL) +#define SEI_INSTR_196 (196UL) +#define SEI_INSTR_197 (197UL) +#define SEI_INSTR_198 (198UL) +#define SEI_INSTR_199 (199UL) +#define SEI_INSTR_200 (200UL) +#define SEI_INSTR_201 (201UL) +#define SEI_INSTR_202 (202UL) +#define SEI_INSTR_203 (203UL) +#define SEI_INSTR_204 (204UL) +#define SEI_INSTR_205 (205UL) +#define SEI_INSTR_206 (206UL) +#define SEI_INSTR_207 (207UL) +#define SEI_INSTR_208 (208UL) +#define SEI_INSTR_209 (209UL) +#define SEI_INSTR_210 (210UL) +#define SEI_INSTR_211 (211UL) +#define SEI_INSTR_212 (212UL) +#define SEI_INSTR_213 (213UL) +#define SEI_INSTR_214 (214UL) +#define SEI_INSTR_215 (215UL) +#define SEI_INSTR_216 (216UL) +#define SEI_INSTR_217 (217UL) +#define SEI_INSTR_218 (218UL) +#define SEI_INSTR_219 (219UL) +#define SEI_INSTR_220 (220UL) +#define SEI_INSTR_221 (221UL) +#define SEI_INSTR_222 (222UL) +#define SEI_INSTR_223 (223UL) +#define SEI_INSTR_224 (224UL) +#define SEI_INSTR_225 (225UL) +#define SEI_INSTR_226 (226UL) +#define SEI_INSTR_227 (227UL) +#define SEI_INSTR_228 (228UL) +#define SEI_INSTR_229 (229UL) +#define SEI_INSTR_230 (230UL) +#define SEI_INSTR_231 (231UL) +#define SEI_INSTR_232 (232UL) +#define SEI_INSTR_233 (233UL) +#define SEI_INSTR_234 (234UL) +#define SEI_INSTR_235 (235UL) +#define SEI_INSTR_236 (236UL) +#define SEI_INSTR_237 (237UL) +#define SEI_INSTR_238 (238UL) +#define SEI_INSTR_239 (239UL) +#define SEI_INSTR_240 (240UL) +#define SEI_INSTR_241 (241UL) +#define SEI_INSTR_242 (242UL) +#define SEI_INSTR_243 (243UL) +#define SEI_INSTR_244 (244UL) +#define SEI_INSTR_245 (245UL) +#define SEI_INSTR_246 (246UL) +#define SEI_INSTR_247 (247UL) +#define SEI_INSTR_248 (248UL) +#define SEI_INSTR_249 (249UL) +#define SEI_INSTR_250 (250UL) +#define SEI_INSTR_251 (251UL) +#define SEI_INSTR_252 (252UL) +#define SEI_INSTR_253 (253UL) +#define SEI_INSTR_254 (254UL) +#define SEI_INSTR_255 (255UL) + +/* DAT register group index macro definition */ +#define SEI_DAT_0 (0UL) +#define SEI_DAT_1 (1UL) +#define SEI_DAT_2 (2UL) +#define SEI_DAT_3 (3UL) +#define SEI_DAT_4 (4UL) +#define SEI_DAT_5 (5UL) +#define SEI_DAT_6 (6UL) +#define SEI_DAT_7 (7UL) +#define SEI_DAT_8 (8UL) +#define SEI_DAT_9 (9UL) +#define SEI_DAT_10 (10UL) +#define SEI_DAT_11 (11UL) +#define SEI_DAT_12 (12UL) +#define SEI_DAT_13 (13UL) +#define SEI_DAT_14 (14UL) +#define SEI_DAT_15 (15UL) +#define SEI_DAT_16 (16UL) +#define SEI_DAT_17 (17UL) +#define SEI_DAT_18 (18UL) +#define SEI_DAT_19 (19UL) +#define SEI_DAT_20 (20UL) +#define SEI_DAT_21 (21UL) +#define SEI_DAT_22 (22UL) +#define SEI_DAT_23 (23UL) +#define SEI_DAT_24 (24UL) +#define SEI_DAT_25 (25UL) +#define SEI_DAT_26 (26UL) +#define SEI_DAT_27 (27UL) +#define SEI_DAT_28 (28UL) +#define SEI_DAT_29 (29UL) +#define SEI_DAT_30 (30UL) +#define SEI_DAT_31 (31UL) + + +#endif /* HPM_SEI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_smix_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_smix_regs.h new file mode 100644 index 00000000000..ce4e2d51e93 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_smix_regs.h @@ -0,0 +1,1018 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_SMIX_H +#define HPM_SMIX_H + +typedef struct { + __R uint32_t DMAC_ID; /* 0x0: DMAC_ID Register */ + __RW uint32_t DMAC_TC_ST; /* 0x4: Transfer Complete Status */ + __RW uint32_t DMAC_ABRT_ST; /* 0x8: Transfer Abort Status */ + __RW uint32_t DMAC_ERR_ST; /* 0xC: Transfer Error Status */ + __R uint8_t RESERVED0[16]; /* 0x10 - 0x1F: Reserved */ + __RW uint32_t DMAC_CTRL; /* 0x20: Control Register */ + __W uint32_t DMAC_ABRT_CMD; /* 0x24: Abort Command Register */ + __R uint8_t RESERVED1[12]; /* 0x28 - 0x33: Reserved */ + __RW uint32_t DMAC_CHEN; /* 0x34: Channel Enable Register */ + __R uint8_t RESERVED2[8]; /* 0x38 - 0x3F: Reserved */ + struct { + __RW uint32_t CTL; /* 0x40: Channel N Control Register */ + __RW uint32_t BURST_COUNT; /* 0x44: Channel N Source Total Beats Register */ + __RW uint32_t SRCADDR; /* 0x48: Channel N Source Register */ + __R uint8_t RESERVED0[4]; /* 0x4C - 0x4F: Reserved */ + __RW uint32_t DSTADDR; /* 0x50: Channel N Destination Register */ + __R uint8_t RESERVED1[4]; /* 0x54 - 0x57: Reserved */ + __RW uint32_t LLP; /* 0x58: Channel N Linked List Pointer Register */ + __R uint8_t RESERVED2[4]; /* 0x5C - 0x5F: Reserved */ + } DMA_CH[26]; + __R uint8_t RESERVED3[1152]; /* 0x380 - 0x7FF: Reserved */ + __RW uint32_t CALSAT_ST; /* 0x800: SMIX Cal Saturation Status Register */ + __RW uint32_t FDOT_DONE_ST; /* 0x804: SMIX Fade-Out Done Status Register */ + __R uint32_t DATA_ST; /* 0x808: SMIX Data Status Register */ + __R uint8_t RESERVED4[52]; /* 0x80C - 0x83F: Reserved */ + struct { + __RW uint32_t CTRL; /* 0x840: SMIX Dstination N Control Register */ + __RW uint32_t GAIN; /* 0x844: SMIX Dstination N Gain Register */ + __RW uint32_t BUFSIZE; /* 0x848: SMIX Dstination N Max Index Register */ + __RW uint32_t FADEIN; /* 0x84C: SMIX Dstination N Fade-In Configuration Register */ + __RW uint32_t FADEOUT; /* 0x850: SMIX Dstination N Fade-Out Configuration Register */ + __R uint32_t ST; /* 0x854: SMIX Dstination N Status Register */ + __R uint32_t DATA; /* 0x858: SMIX Dstination N Data Out Register */ + __R uint8_t RESERVED0[4]; /* 0x85C - 0x85F: Reserved */ + __RW uint32_t SOURCE_EN; /* 0x860: SMIX Dstination N Source Enable Register */ + __RW uint32_t SOURCE_ACT; /* 0x864: SMIX Dstination N Source Activation Register */ + __RW uint32_t SOURCE_DEACT; /* 0x868: SMIX Dstination N Source De-Activation Register */ + __RW uint32_t SOURCE_FADEIN_CTRL; /* 0x86C: SMIX Dstination N Source Fade-in Control Register */ + __R uint32_t DEACT_ST; /* 0x870: SMIX Dstination N Source Deactivation Status Register */ + __RW uint32_t SOURCE_MFADEOUT_CTRL; /* 0x874: SMIX Dstination N Source Manual Fade-out Control Register */ + __R uint8_t RESERVED1[8]; /* 0x878 - 0x87F: Reserved */ + } DST_CH[2]; + __R uint8_t RESERVED5[64]; /* 0x8C0 - 0x8FF: Reserved */ + struct { + __RW uint32_t CTRL; /* 0x900: SMIX Source N Control Register */ + __RW uint32_t GAIN; /* 0x904: SMIX Source N Gain Register */ + __RW uint32_t FADEIN; /* 0x908: SMIX Source N Fade-in Control Register */ + __RW uint32_t FADEOUT; /* 0x90C: SMIX Source N Fade-out Control Register */ + __RW uint32_t BUFSIZE; /* 0x910: SMIX Source N Buffer Size Register */ + __RW uint32_t ST; /* 0x914: SMIX Source N Status Register */ + __W uint32_t DATA; /* 0x918: SMIX Source N Data Input Register */ + __R uint8_t RESERVED0[4]; /* 0x91C - 0x91F: Reserved */ + } SOURCE_CH[14]; +} SMIX_Type; + + +/* Bitfield definition for register: DMAC_ID */ +/* + * REV (RO) + * + * Revision + */ +#define SMIX_DMAC_ID_REV_MASK (0x7FFFFUL) +#define SMIX_DMAC_ID_REV_SHIFT (0U) +#define SMIX_DMAC_ID_REV_GET(x) (((uint32_t)(x) & SMIX_DMAC_ID_REV_MASK) >> SMIX_DMAC_ID_REV_SHIFT) + +/* Bitfield definition for register: DMAC_TC_ST */ +/* + * CH (W1C) + * + * The terminal count status is set when a channel transfer finishes without abort or error events + */ +#define SMIX_DMAC_TC_ST_CH_MASK (0x3FFFFFFUL) +#define SMIX_DMAC_TC_ST_CH_SHIFT (0U) +#define SMIX_DMAC_TC_ST_CH_SET(x) (((uint32_t)(x) << SMIX_DMAC_TC_ST_CH_SHIFT) & SMIX_DMAC_TC_ST_CH_MASK) +#define SMIX_DMAC_TC_ST_CH_GET(x) (((uint32_t)(x) & SMIX_DMAC_TC_ST_CH_MASK) >> SMIX_DMAC_TC_ST_CH_SHIFT) + +/* Bitfield definition for register: DMAC_ABRT_ST */ +/* + * CH (W1C) + * + * The abort status is set when a channel transfer is aborted + */ +#define SMIX_DMAC_ABRT_ST_CH_MASK (0x3FFFFFFUL) +#define SMIX_DMAC_ABRT_ST_CH_SHIFT (0U) +#define SMIX_DMAC_ABRT_ST_CH_SET(x) (((uint32_t)(x) << SMIX_DMAC_ABRT_ST_CH_SHIFT) & SMIX_DMAC_ABRT_ST_CH_MASK) +#define SMIX_DMAC_ABRT_ST_CH_GET(x) (((uint32_t)(x) & SMIX_DMAC_ABRT_ST_CH_MASK) >> SMIX_DMAC_ABRT_ST_CH_SHIFT) + +/* Bitfield definition for register: DMAC_ERR_ST */ +/* + * CH (W1C) + * + * The error status is set when a channel transfer encounters the following error events: + * . Bus error + * . Unaligned address + * . Unaligned transfer width + * . Reserved configuration + */ +#define SMIX_DMAC_ERR_ST_CH_MASK (0x3FFFFFFUL) +#define SMIX_DMAC_ERR_ST_CH_SHIFT (0U) +#define SMIX_DMAC_ERR_ST_CH_SET(x) (((uint32_t)(x) << SMIX_DMAC_ERR_ST_CH_SHIFT) & SMIX_DMAC_ERR_ST_CH_MASK) +#define SMIX_DMAC_ERR_ST_CH_GET(x) (((uint32_t)(x) & SMIX_DMAC_ERR_ST_CH_MASK) >> SMIX_DMAC_ERR_ST_CH_SHIFT) + +/* Bitfield definition for register: DMAC_CTRL */ +/* + * SRST (RW) + * + * Software Reset + */ +#define SMIX_DMAC_CTRL_SRST_MASK (0x1U) +#define SMIX_DMAC_CTRL_SRST_SHIFT (0U) +#define SMIX_DMAC_CTRL_SRST_SET(x) (((uint32_t)(x) << SMIX_DMAC_CTRL_SRST_SHIFT) & SMIX_DMAC_CTRL_SRST_MASK) +#define SMIX_DMAC_CTRL_SRST_GET(x) (((uint32_t)(x) & SMIX_DMAC_CTRL_SRST_MASK) >> SMIX_DMAC_CTRL_SRST_SHIFT) + +/* Bitfield definition for register: DMAC_ABRT_CMD */ +/* + * CH (WO) + * + * Write 1 to force the corresponding channel into abort status + */ +#define SMIX_DMAC_ABRT_CMD_CH_MASK (0x3FFFFFFUL) +#define SMIX_DMAC_ABRT_CMD_CH_SHIFT (0U) +#define SMIX_DMAC_ABRT_CMD_CH_SET(x) (((uint32_t)(x) << SMIX_DMAC_ABRT_CMD_CH_SHIFT) & SMIX_DMAC_ABRT_CMD_CH_MASK) +#define SMIX_DMAC_ABRT_CMD_CH_GET(x) (((uint32_t)(x) & SMIX_DMAC_ABRT_CMD_CH_MASK) >> SMIX_DMAC_ABRT_CMD_CH_SHIFT) + +/* Bitfield definition for register: DMAC_CHEN */ +/* + * CH (RO) + * + * Write 1 to enable the corresponding channel + */ +#define SMIX_DMAC_CHEN_CH_MASK (0x3FFFFFFUL) +#define SMIX_DMAC_CHEN_CH_SHIFT (0U) +#define SMIX_DMAC_CHEN_CH_GET(x) (((uint32_t)(x) & SMIX_DMAC_CHEN_CH_MASK) >> SMIX_DMAC_CHEN_CH_SHIFT) + +/* Bitfield definition for register of struct array DMA_CH: CTL */ +/* + * SRCREQSEL (RW) + * + * Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + */ +#define SMIX_DMA_CH_CTL_SRCREQSEL_MASK (0x7C000000UL) +#define SMIX_DMA_CH_CTL_SRCREQSEL_SHIFT (26U) +#define SMIX_DMA_CH_CTL_SRCREQSEL_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_SRCREQSEL_SHIFT) & SMIX_DMA_CH_CTL_SRCREQSEL_MASK) +#define SMIX_DMA_CH_CTL_SRCREQSEL_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_SRCREQSEL_MASK) >> SMIX_DMA_CH_CTL_SRCREQSEL_SHIFT) + +/* + * DSTREQSEL (RW) + * + * Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + */ +#define SMIX_DMA_CH_CTL_DSTREQSEL_MASK (0x3E00000UL) +#define SMIX_DMA_CH_CTL_DSTREQSEL_SHIFT (21U) +#define SMIX_DMA_CH_CTL_DSTREQSEL_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_DSTREQSEL_SHIFT) & SMIX_DMA_CH_CTL_DSTREQSEL_MASK) +#define SMIX_DMA_CH_CTL_DSTREQSEL_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_DSTREQSEL_MASK) >> SMIX_DMA_CH_CTL_DSTREQSEL_SHIFT) + +/* + * PRIORITY (RW) + * + * 0x0: Lower priority + * 0x1: Higher priority + */ +#define SMIX_DMA_CH_CTL_PRIORITY_MASK (0x80000UL) +#define SMIX_DMA_CH_CTL_PRIORITY_SHIFT (19U) +#define SMIX_DMA_CH_CTL_PRIORITY_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_PRIORITY_SHIFT) & SMIX_DMA_CH_CTL_PRIORITY_MASK) +#define SMIX_DMA_CH_CTL_PRIORITY_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_PRIORITY_MASK) >> SMIX_DMA_CH_CTL_PRIORITY_SHIFT) + +/* + * SRCBURSTSIZE (RW) + * + * 0x0: 1 beat per transfer + * 0x1: 2 beats per transfer + * 0x2: 4 beats per transfer + * 0x3: 8 beats per transfer + * 0x4: 16 beats per transfer + * 0x5: 32 beats per transfer + * 0x6: 64 beats per transfer + * 0x7: 128 beats per transfer + */ +#define SMIX_DMA_CH_CTL_SRCBURSTSIZE_MASK (0x78000UL) +#define SMIX_DMA_CH_CTL_SRCBURSTSIZE_SHIFT (15U) +#define SMIX_DMA_CH_CTL_SRCBURSTSIZE_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_SRCBURSTSIZE_SHIFT) & SMIX_DMA_CH_CTL_SRCBURSTSIZE_MASK) +#define SMIX_DMA_CH_CTL_SRCBURSTSIZE_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_SRCBURSTSIZE_MASK) >> SMIX_DMA_CH_CTL_SRCBURSTSIZE_SHIFT) + +/* + * SRCWIDTH (RW) + * + * Source Transfer Beat Size: + * 0x0: Byte transfer + * 0x1: Half-word transfer + * 0x2: Word transfer + */ +#define SMIX_DMA_CH_CTL_SRCWIDTH_MASK (0x6000U) +#define SMIX_DMA_CH_CTL_SRCWIDTH_SHIFT (13U) +#define SMIX_DMA_CH_CTL_SRCWIDTH_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_SRCWIDTH_SHIFT) & SMIX_DMA_CH_CTL_SRCWIDTH_MASK) +#define SMIX_DMA_CH_CTL_SRCWIDTH_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_SRCWIDTH_MASK) >> SMIX_DMA_CH_CTL_SRCWIDTH_SHIFT) + +/* + * DSTWIDTH (RW) + * + * Destination Transfer Beat Size: + * 0x0: Byte transfer + * 0x1: Half-word transfer + * 0x2: Word transfer + */ +#define SMIX_DMA_CH_CTL_DSTWIDTH_MASK (0x1800U) +#define SMIX_DMA_CH_CTL_DSTWIDTH_SHIFT (11U) +#define SMIX_DMA_CH_CTL_DSTWIDTH_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_DSTWIDTH_SHIFT) & SMIX_DMA_CH_CTL_DSTWIDTH_MASK) +#define SMIX_DMA_CH_CTL_DSTWIDTH_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_DSTWIDTH_MASK) >> SMIX_DMA_CH_CTL_DSTWIDTH_SHIFT) + +/* + * SRCMODE (RW) + * + * DMA Source handshake mode + * 0x0: Normal mode + * 0x1: Handshake mode + */ +#define SMIX_DMA_CH_CTL_SRCMODE_MASK (0x400U) +#define SMIX_DMA_CH_CTL_SRCMODE_SHIFT (10U) +#define SMIX_DMA_CH_CTL_SRCMODE_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_SRCMODE_SHIFT) & SMIX_DMA_CH_CTL_SRCMODE_MASK) +#define SMIX_DMA_CH_CTL_SRCMODE_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_SRCMODE_MASK) >> SMIX_DMA_CH_CTL_SRCMODE_SHIFT) + +/* + * DSTMODE (RW) + * + * DMA Destination handshake mode + * 0x0: Normal mode + * 0x1: Handshake mode + */ +#define SMIX_DMA_CH_CTL_DSTMODE_MASK (0x200U) +#define SMIX_DMA_CH_CTL_DSTMODE_SHIFT (9U) +#define SMIX_DMA_CH_CTL_DSTMODE_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_DSTMODE_SHIFT) & SMIX_DMA_CH_CTL_DSTMODE_MASK) +#define SMIX_DMA_CH_CTL_DSTMODE_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_DSTMODE_MASK) >> SMIX_DMA_CH_CTL_DSTMODE_SHIFT) + +/* + * SRCADDRCTRL (RW) + * + * 0x0: Increment address + * 0x1: Decrement address + * 0x2: Fixed address + * 0x3: Reserved, setting the field with this value triggers an error exception + */ +#define SMIX_DMA_CH_CTL_SRCADDRCTRL_MASK (0x180U) +#define SMIX_DMA_CH_CTL_SRCADDRCTRL_SHIFT (7U) +#define SMIX_DMA_CH_CTL_SRCADDRCTRL_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_SRCADDRCTRL_SHIFT) & SMIX_DMA_CH_CTL_SRCADDRCTRL_MASK) +#define SMIX_DMA_CH_CTL_SRCADDRCTRL_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_SRCADDRCTRL_MASK) >> SMIX_DMA_CH_CTL_SRCADDRCTRL_SHIFT) + +/* + * DSTADDRCTRL (RW) + * + * 0x0: Increment address + * 0x1: Decrement address + * 0x2: Fixed address + * 0x3: Reserved, setting the field with this value triggers an error exception + */ +#define SMIX_DMA_CH_CTL_DSTADDRCTRL_MASK (0x60U) +#define SMIX_DMA_CH_CTL_DSTADDRCTRL_SHIFT (5U) +#define SMIX_DMA_CH_CTL_DSTADDRCTRL_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_DSTADDRCTRL_SHIFT) & SMIX_DMA_CH_CTL_DSTADDRCTRL_MASK) +#define SMIX_DMA_CH_CTL_DSTADDRCTRL_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_DSTADDRCTRL_MASK) >> SMIX_DMA_CH_CTL_DSTADDRCTRL_SHIFT) + +/* + * ABRT_INT_EN (RW) + * + * Abort interrupt enable + */ +#define SMIX_DMA_CH_CTL_ABRT_INT_EN_MASK (0x8U) +#define SMIX_DMA_CH_CTL_ABRT_INT_EN_SHIFT (3U) +#define SMIX_DMA_CH_CTL_ABRT_INT_EN_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_ABRT_INT_EN_SHIFT) & SMIX_DMA_CH_CTL_ABRT_INT_EN_MASK) +#define SMIX_DMA_CH_CTL_ABRT_INT_EN_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_ABRT_INT_EN_MASK) >> SMIX_DMA_CH_CTL_ABRT_INT_EN_SHIFT) + +/* + * ERR_INT_EN (RW) + * + * Err interrupt enable + */ +#define SMIX_DMA_CH_CTL_ERR_INT_EN_MASK (0x4U) +#define SMIX_DMA_CH_CTL_ERR_INT_EN_SHIFT (2U) +#define SMIX_DMA_CH_CTL_ERR_INT_EN_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_ERR_INT_EN_SHIFT) & SMIX_DMA_CH_CTL_ERR_INT_EN_MASK) +#define SMIX_DMA_CH_CTL_ERR_INT_EN_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_ERR_INT_EN_MASK) >> SMIX_DMA_CH_CTL_ERR_INT_EN_SHIFT) + +/* + * TC_INT_EN (RW) + * + * TC interrupt enable + */ +#define SMIX_DMA_CH_CTL_TC_INT_EN_MASK (0x2U) +#define SMIX_DMA_CH_CTL_TC_INT_EN_SHIFT (1U) +#define SMIX_DMA_CH_CTL_TC_INT_EN_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_TC_INT_EN_SHIFT) & SMIX_DMA_CH_CTL_TC_INT_EN_MASK) +#define SMIX_DMA_CH_CTL_TC_INT_EN_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_TC_INT_EN_MASK) >> SMIX_DMA_CH_CTL_TC_INT_EN_SHIFT) + +/* + * EN (RW) + * + * channel enable bit + */ +#define SMIX_DMA_CH_CTL_EN_MASK (0x1U) +#define SMIX_DMA_CH_CTL_EN_SHIFT (0U) +#define SMIX_DMA_CH_CTL_EN_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_EN_SHIFT) & SMIX_DMA_CH_CTL_EN_MASK) +#define SMIX_DMA_CH_CTL_EN_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_EN_MASK) >> SMIX_DMA_CH_CTL_EN_SHIFT) + +/* Bitfield definition for register of struct array DMA_CH: BURST_COUNT */ +/* + * NUM (RW) + * + * the total number of source beats + */ +#define SMIX_DMA_CH_BURST_COUNT_NUM_MASK (0xFFFFFFFFUL) +#define SMIX_DMA_CH_BURST_COUNT_NUM_SHIFT (0U) +#define SMIX_DMA_CH_BURST_COUNT_NUM_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_BURST_COUNT_NUM_SHIFT) & SMIX_DMA_CH_BURST_COUNT_NUM_MASK) +#define SMIX_DMA_CH_BURST_COUNT_NUM_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_BURST_COUNT_NUM_MASK) >> SMIX_DMA_CH_BURST_COUNT_NUM_SHIFT) + +/* Bitfield definition for register of struct array DMA_CH: SRCADDR */ +/* + * PTR (RW) + * + * source address + */ +#define SMIX_DMA_CH_SRCADDR_PTR_MASK (0xFFFFFFFFUL) +#define SMIX_DMA_CH_SRCADDR_PTR_SHIFT (0U) +#define SMIX_DMA_CH_SRCADDR_PTR_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_SRCADDR_PTR_SHIFT) & SMIX_DMA_CH_SRCADDR_PTR_MASK) +#define SMIX_DMA_CH_SRCADDR_PTR_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_SRCADDR_PTR_MASK) >> SMIX_DMA_CH_SRCADDR_PTR_SHIFT) + +/* Bitfield definition for register of struct array DMA_CH: DSTADDR */ +/* + * PTR (RW) + * + * destination address + */ +#define SMIX_DMA_CH_DSTADDR_PTR_MASK (0xFFFFFFFFUL) +#define SMIX_DMA_CH_DSTADDR_PTR_SHIFT (0U) +#define SMIX_DMA_CH_DSTADDR_PTR_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_DSTADDR_PTR_SHIFT) & SMIX_DMA_CH_DSTADDR_PTR_MASK) +#define SMIX_DMA_CH_DSTADDR_PTR_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_DSTADDR_PTR_MASK) >> SMIX_DMA_CH_DSTADDR_PTR_SHIFT) + +/* Bitfield definition for register of struct array DMA_CH: LLP */ +/* + * PTR (RW) + * + * the address pointer for the linked list descriptor + */ +#define SMIX_DMA_CH_LLP_PTR_MASK (0xFFFFFFFFUL) +#define SMIX_DMA_CH_LLP_PTR_SHIFT (0U) +#define SMIX_DMA_CH_LLP_PTR_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_LLP_PTR_SHIFT) & SMIX_DMA_CH_LLP_PTR_MASK) +#define SMIX_DMA_CH_LLP_PTR_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_LLP_PTR_MASK) >> SMIX_DMA_CH_LLP_PTR_SHIFT) + +/* Bitfield definition for register: CALSAT_ST */ +/* + * DST (W1C) + * + * DST CAL_SAT_ERR. W1C + */ +#define SMIX_CALSAT_ST_DST_MASK (0xC0000000UL) +#define SMIX_CALSAT_ST_DST_SHIFT (30U) +#define SMIX_CALSAT_ST_DST_SET(x) (((uint32_t)(x) << SMIX_CALSAT_ST_DST_SHIFT) & SMIX_CALSAT_ST_DST_MASK) +#define SMIX_CALSAT_ST_DST_GET(x) (((uint32_t)(x) & SMIX_CALSAT_ST_DST_MASK) >> SMIX_CALSAT_ST_DST_SHIFT) + +/* + * SRC (W1C) + * + * SRC CAL_SAT_ERR. W1C + */ +#define SMIX_CALSAT_ST_SRC_MASK (0x3FFFU) +#define SMIX_CALSAT_ST_SRC_SHIFT (0U) +#define SMIX_CALSAT_ST_SRC_SET(x) (((uint32_t)(x) << SMIX_CALSAT_ST_SRC_SHIFT) & SMIX_CALSAT_ST_SRC_MASK) +#define SMIX_CALSAT_ST_SRC_GET(x) (((uint32_t)(x) & SMIX_CALSAT_ST_SRC_MASK) >> SMIX_CALSAT_ST_SRC_SHIFT) + +/* Bitfield definition for register: FDOT_DONE_ST */ +/* + * DST (W1C) + * + * DST fadeout done. W1C + */ +#define SMIX_FDOT_DONE_ST_DST_MASK (0xC0000000UL) +#define SMIX_FDOT_DONE_ST_DST_SHIFT (30U) +#define SMIX_FDOT_DONE_ST_DST_SET(x) (((uint32_t)(x) << SMIX_FDOT_DONE_ST_DST_SHIFT) & SMIX_FDOT_DONE_ST_DST_MASK) +#define SMIX_FDOT_DONE_ST_DST_GET(x) (((uint32_t)(x) & SMIX_FDOT_DONE_ST_DST_MASK) >> SMIX_FDOT_DONE_ST_DST_SHIFT) + +/* + * SRC (W1C) + * + * SRC fadeout done. W1C + */ +#define SMIX_FDOT_DONE_ST_SRC_MASK (0x3FFFU) +#define SMIX_FDOT_DONE_ST_SRC_SHIFT (0U) +#define SMIX_FDOT_DONE_ST_SRC_SET(x) (((uint32_t)(x) << SMIX_FDOT_DONE_ST_SRC_SHIFT) & SMIX_FDOT_DONE_ST_SRC_MASK) +#define SMIX_FDOT_DONE_ST_SRC_GET(x) (((uint32_t)(x) & SMIX_FDOT_DONE_ST_SRC_MASK) >> SMIX_FDOT_DONE_ST_SRC_SHIFT) + +/* Bitfield definition for register: DATA_ST */ +/* + * DST_DA (RO) + * + * DST data available + */ +#define SMIX_DATA_ST_DST_DA_MASK (0xC0000000UL) +#define SMIX_DATA_ST_DST_DA_SHIFT (30U) +#define SMIX_DATA_ST_DST_DA_GET(x) (((uint32_t)(x) & SMIX_DATA_ST_DST_DA_MASK) >> SMIX_DATA_ST_DST_DA_SHIFT) + +/* + * DST_UNDL (RO) + * + * DST data underflow + */ +#define SMIX_DATA_ST_DST_UNDL_MASK (0x30000000UL) +#define SMIX_DATA_ST_DST_UNDL_SHIFT (28U) +#define SMIX_DATA_ST_DST_UNDL_GET(x) (((uint32_t)(x) & SMIX_DATA_ST_DST_UNDL_MASK) >> SMIX_DATA_ST_DST_UNDL_SHIFT) + +/* + * SRC_DN (RO) + * + * SRC data needed + */ +#define SMIX_DATA_ST_SRC_DN_MASK (0x3FFFU) +#define SMIX_DATA_ST_SRC_DN_SHIFT (0U) +#define SMIX_DATA_ST_SRC_DN_GET(x) (((uint32_t)(x) & SMIX_DATA_ST_SRC_DN_MASK) >> SMIX_DATA_ST_SRC_DN_SHIFT) + +/* Bitfield definition for register of struct array DST_CH: CTRL */ +/* + * DATA_UNFL_IE (RW) + * + * Data Underflow Error IntEn + */ +#define SMIX_DST_CH_CTRL_DATA_UNFL_IE_MASK (0x100000UL) +#define SMIX_DST_CH_CTRL_DATA_UNFL_IE_SHIFT (20U) +#define SMIX_DST_CH_CTRL_DATA_UNFL_IE_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_DATA_UNFL_IE_SHIFT) & SMIX_DST_CH_CTRL_DATA_UNFL_IE_MASK) +#define SMIX_DST_CH_CTRL_DATA_UNFL_IE_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_DATA_UNFL_IE_MASK) >> SMIX_DST_CH_CTRL_DATA_UNFL_IE_SHIFT) + +/* + * THRSH (RW) + * + * FIFO threshold for DMA or Int. >= will generate req. Must be greater or equal than 8. The read burst of DMA should make the fillings in the buffer be greater than 4. + */ +#define SMIX_DST_CH_CTRL_THRSH_MASK (0xFF000UL) +#define SMIX_DST_CH_CTRL_THRSH_SHIFT (12U) +#define SMIX_DST_CH_CTRL_THRSH_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_THRSH_SHIFT) & SMIX_DST_CH_CTRL_THRSH_MASK) +#define SMIX_DST_CH_CTRL_THRSH_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_THRSH_MASK) >> SMIX_DST_CH_CTRL_THRSH_SHIFT) + +/* + * CALSAT_INT_EN (RW) + * + * Cal Saturation IntEn + */ +#define SMIX_DST_CH_CTRL_CALSAT_INT_EN_MASK (0x800U) +#define SMIX_DST_CH_CTRL_CALSAT_INT_EN_SHIFT (11U) +#define SMIX_DST_CH_CTRL_CALSAT_INT_EN_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_CALSAT_INT_EN_SHIFT) & SMIX_DST_CH_CTRL_CALSAT_INT_EN_MASK) +#define SMIX_DST_CH_CTRL_CALSAT_INT_EN_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_CALSAT_INT_EN_MASK) >> SMIX_DST_CH_CTRL_CALSAT_INT_EN_SHIFT) + +/* + * DA_INT_EN (RW) + * + * Data Available IntEn + */ +#define SMIX_DST_CH_CTRL_DA_INT_EN_MASK (0x400U) +#define SMIX_DST_CH_CTRL_DA_INT_EN_SHIFT (10U) +#define SMIX_DST_CH_CTRL_DA_INT_EN_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_DA_INT_EN_SHIFT) & SMIX_DST_CH_CTRL_DA_INT_EN_MASK) +#define SMIX_DST_CH_CTRL_DA_INT_EN_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_DA_INT_EN_MASK) >> SMIX_DST_CH_CTRL_DA_INT_EN_SHIFT) + +/* + * ADEACTFADEOUT_EN (RW) + * + * AutoDeactAfterFadeOut_En: + * Asserted to enter de-activated mode after fade-out done + */ +#define SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_MASK (0x200U) +#define SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_SHIFT (9U) +#define SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_SHIFT) & SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_MASK) +#define SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_MASK) >> SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_SHIFT) + +/* + * FADEOUT_DONE_IE (RW) + * + * Fade-Out interrupt enable + */ +#define SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_MASK (0x100U) +#define SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_SHIFT (8U) +#define SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_SHIFT) & SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_MASK) +#define SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_MASK) >> SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_SHIFT) + +/* + * DST_DEACT (RW) + * + * de-activate the destination channel + */ +#define SMIX_DST_CH_CTRL_DST_DEACT_MASK (0x80U) +#define SMIX_DST_CH_CTRL_DST_DEACT_SHIFT (7U) +#define SMIX_DST_CH_CTRL_DST_DEACT_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_DST_DEACT_SHIFT) & SMIX_DST_CH_CTRL_DST_DEACT_MASK) +#define SMIX_DST_CH_CTRL_DST_DEACT_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_DST_DEACT_MASK) >> SMIX_DST_CH_CTRL_DST_DEACT_SHIFT) + +/* + * DST_ACT (RW) + * + * activate the destination channel + */ +#define SMIX_DST_CH_CTRL_DST_ACT_MASK (0x40U) +#define SMIX_DST_CH_CTRL_DST_ACT_SHIFT (6U) +#define SMIX_DST_CH_CTRL_DST_ACT_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_DST_ACT_SHIFT) & SMIX_DST_CH_CTRL_DST_ACT_MASK) +#define SMIX_DST_CH_CTRL_DST_ACT_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_DST_ACT_MASK) >> SMIX_DST_CH_CTRL_DST_ACT_SHIFT) + +/* + * DSTFADOUT_MEN (RW) + * + * Manual FadeOut_Ctrl for destionation. Auto clear. + */ +#define SMIX_DST_CH_CTRL_DSTFADOUT_MEN_MASK (0x20U) +#define SMIX_DST_CH_CTRL_DSTFADOUT_MEN_SHIFT (5U) +#define SMIX_DST_CH_CTRL_DSTFADOUT_MEN_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_DSTFADOUT_MEN_SHIFT) & SMIX_DST_CH_CTRL_DSTFADOUT_MEN_MASK) +#define SMIX_DST_CH_CTRL_DSTFADOUT_MEN_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_DSTFADOUT_MEN_MASK) >> SMIX_DST_CH_CTRL_DSTFADOUT_MEN_SHIFT) + +/* + * DSTFADOUT_AEN (RW) + * + * Automatically FadeOut_Ctrl for destionation. Only effective after DST_AFADEOUT is assigned a non-zero value + */ +#define SMIX_DST_CH_CTRL_DSTFADOUT_AEN_MASK (0x10U) +#define SMIX_DST_CH_CTRL_DSTFADOUT_AEN_SHIFT (4U) +#define SMIX_DST_CH_CTRL_DSTFADOUT_AEN_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_DSTFADOUT_AEN_SHIFT) & SMIX_DST_CH_CTRL_DSTFADOUT_AEN_MASK) +#define SMIX_DST_CH_CTRL_DSTFADOUT_AEN_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_DSTFADOUT_AEN_MASK) >> SMIX_DST_CH_CTRL_DSTFADOUT_AEN_SHIFT) + +/* + * DSTFADIN_EN (RW) + * + * FadeIn_Ctrl for destionation. Auto clear. + */ +#define SMIX_DST_CH_CTRL_DSTFADIN_EN_MASK (0x8U) +#define SMIX_DST_CH_CTRL_DSTFADIN_EN_SHIFT (3U) +#define SMIX_DST_CH_CTRL_DSTFADIN_EN_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_DSTFADIN_EN_SHIFT) & SMIX_DST_CH_CTRL_DSTFADIN_EN_MASK) +#define SMIX_DST_CH_CTRL_DSTFADIN_EN_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_DSTFADIN_EN_MASK) >> SMIX_DST_CH_CTRL_DSTFADIN_EN_SHIFT) + +/* + * DST_EN (RW) + * + * Dst enabled. When disabled, clear the FIFO pointers. + */ +#define SMIX_DST_CH_CTRL_DST_EN_MASK (0x4U) +#define SMIX_DST_CH_CTRL_DST_EN_SHIFT (2U) +#define SMIX_DST_CH_CTRL_DST_EN_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_DST_EN_SHIFT) & SMIX_DST_CH_CTRL_DST_EN_MASK) +#define SMIX_DST_CH_CTRL_DST_EN_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_DST_EN_MASK) >> SMIX_DST_CH_CTRL_DST_EN_SHIFT) + +/* + * SOFTRST (RW) + * + * Soft reset + */ +#define SMIX_DST_CH_CTRL_SOFTRST_MASK (0x2U) +#define SMIX_DST_CH_CTRL_SOFTRST_SHIFT (1U) +#define SMIX_DST_CH_CTRL_SOFTRST_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_SOFTRST_SHIFT) & SMIX_DST_CH_CTRL_SOFTRST_MASK) +#define SMIX_DST_CH_CTRL_SOFTRST_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_SOFTRST_MASK) >> SMIX_DST_CH_CTRL_SOFTRST_SHIFT) + +/* + * MIXER_EN (RW) + * + * mixer function enable. + */ +#define SMIX_DST_CH_CTRL_MIXER_EN_MASK (0x1U) +#define SMIX_DST_CH_CTRL_MIXER_EN_SHIFT (0U) +#define SMIX_DST_CH_CTRL_MIXER_EN_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_MIXER_EN_SHIFT) & SMIX_DST_CH_CTRL_MIXER_EN_MASK) +#define SMIX_DST_CH_CTRL_MIXER_EN_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_MIXER_EN_MASK) >> SMIX_DST_CH_CTRL_MIXER_EN_SHIFT) + +/* Bitfield definition for register of struct array DST_CH: GAIN */ +/* + * VAL (RW) + * + * Unsigned Int, with 12 fractional bits. . The top 3 bits are for shift. Same as SHFT_CTR[2:0] + */ +#define SMIX_DST_CH_GAIN_VAL_MASK (0x7FFFU) +#define SMIX_DST_CH_GAIN_VAL_SHIFT (0U) +#define SMIX_DST_CH_GAIN_VAL_SET(x) (((uint32_t)(x) << SMIX_DST_CH_GAIN_VAL_SHIFT) & SMIX_DST_CH_GAIN_VAL_MASK) +#define SMIX_DST_CH_GAIN_VAL_GET(x) (((uint32_t)(x) & SMIX_DST_CH_GAIN_VAL_MASK) >> SMIX_DST_CH_GAIN_VAL_SHIFT) + +/* Bitfield definition for register of struct array DST_CH: BUFSIZE */ +/* + * MAX_IDX (RW) + * + * The total length of the dst stream -1. If zero, means there is no end of the stream. + */ +#define SMIX_DST_CH_BUFSIZE_MAX_IDX_MASK (0xFFFFFFFFUL) +#define SMIX_DST_CH_BUFSIZE_MAX_IDX_SHIFT (0U) +#define SMIX_DST_CH_BUFSIZE_MAX_IDX_SET(x) (((uint32_t)(x) << SMIX_DST_CH_BUFSIZE_MAX_IDX_SHIFT) & SMIX_DST_CH_BUFSIZE_MAX_IDX_MASK) +#define SMIX_DST_CH_BUFSIZE_MAX_IDX_GET(x) (((uint32_t)(x) & SMIX_DST_CH_BUFSIZE_MAX_IDX_MASK) >> SMIX_DST_CH_BUFSIZE_MAX_IDX_SHIFT) + +/* Bitfield definition for register of struct array DST_CH: FADEIN */ +/* + * DELTA (RW) + * + * Fade-in delta for linear fading in from 0 to 1 (about at most 20s for 48kHz sampled sound) + * (Using only top 14 bits for mul) + */ +#define SMIX_DST_CH_FADEIN_DELTA_MASK (0xFFFFFUL) +#define SMIX_DST_CH_FADEIN_DELTA_SHIFT (0U) +#define SMIX_DST_CH_FADEIN_DELTA_SET(x) (((uint32_t)(x) << SMIX_DST_CH_FADEIN_DELTA_SHIFT) & SMIX_DST_CH_FADEIN_DELTA_MASK) +#define SMIX_DST_CH_FADEIN_DELTA_GET(x) (((uint32_t)(x) & SMIX_DST_CH_FADEIN_DELTA_MASK) >> SMIX_DST_CH_FADEIN_DELTA_SHIFT) + +/* Bitfield definition for register of struct array DST_CH: FADEOUT */ +/* + * DELTA (RW) + * + * Fade out in 2^DELTA samples. Now DELTA can be at most 14。 + */ +#define SMIX_DST_CH_FADEOUT_DELTA_MASK (0xFFFFFUL) +#define SMIX_DST_CH_FADEOUT_DELTA_SHIFT (0U) +#define SMIX_DST_CH_FADEOUT_DELTA_SET(x) (((uint32_t)(x) << SMIX_DST_CH_FADEOUT_DELTA_SHIFT) & SMIX_DST_CH_FADEOUT_DELTA_MASK) +#define SMIX_DST_CH_FADEOUT_DELTA_GET(x) (((uint32_t)(x) & SMIX_DST_CH_FADEOUT_DELTA_MASK) >> SMIX_DST_CH_FADEOUT_DELTA_SHIFT) + +/* Bitfield definition for register of struct array DST_CH: ST */ +/* + * FIFO_FILLINGS (RO) + * + * destination channel output FIFO fillings + */ +#define SMIX_DST_CH_ST_FIFO_FILLINGS_MASK (0x7FC0U) +#define SMIX_DST_CH_ST_FIFO_FILLINGS_SHIFT (6U) +#define SMIX_DST_CH_ST_FIFO_FILLINGS_GET(x) (((uint32_t)(x) & SMIX_DST_CH_ST_FIFO_FILLINGS_MASK) >> SMIX_DST_CH_ST_FIFO_FILLINGS_SHIFT) + +/* + * FDOUT_DONE (RO) + * + * Fade-Out Done. W1C + */ +#define SMIX_DST_CH_ST_FDOUT_DONE_MASK (0x20U) +#define SMIX_DST_CH_ST_FDOUT_DONE_SHIFT (5U) +#define SMIX_DST_CH_ST_FDOUT_DONE_GET(x) (((uint32_t)(x) & SMIX_DST_CH_ST_FDOUT_DONE_MASK) >> SMIX_DST_CH_ST_FDOUT_DONE_SHIFT) + +/* + * CALSAT (RO) + * + * Saturate Error Found. W1C + */ +#define SMIX_DST_CH_ST_CALSAT_MASK (0x10U) +#define SMIX_DST_CH_ST_CALSAT_SHIFT (4U) +#define SMIX_DST_CH_ST_CALSAT_GET(x) (((uint32_t)(x) & SMIX_DST_CH_ST_CALSAT_MASK) >> SMIX_DST_CH_ST_CALSAT_SHIFT) + +/* + * DA (RO) + * + * Data Available + */ +#define SMIX_DST_CH_ST_DA_MASK (0x8U) +#define SMIX_DST_CH_ST_DA_SHIFT (3U) +#define SMIX_DST_CH_ST_DA_GET(x) (((uint32_t)(x) & SMIX_DST_CH_ST_DA_MASK) >> SMIX_DST_CH_ST_DA_SHIFT) + +/* + * MODE (RO) + * + * The modes are: + * Mode 0: Disabled: after reset. Program the registers, and DSTn_CTRL [DST_EN] to enter Mode 1. + * Mode 1: Enabled and not-activated. wait for DSTn_CTRL [DSTFADIN_EN] or DSTn_CTRL [DST_ACT], jump to Mode 3 or Mode 4 based on whether Fade-in enabled. + * Mode 3: Enabled and activated and fade-in in progress: Can not be fade out. Will send data to DMA. Jump to Mode 4 after fadin op done. + * Mode 4: Enabled and activated and done fade-in, no fade-out yet: Can be fade out. Will send data to DMA. + * Mode 5: Enabled and activated and fade-out in progress: After faded out OP. Will send data to DMA. Will transfer to mode 6 or mode 7 depending on the DSTn_CTRL [ADeactFadeOut_En] cfg + * Mode 6: Enabled and activated and faded-out: faded out is done. Will send data to DMA. Will transfer to mode 7 if manual deactivated. + * Mode 7: Enabled and De-activated: If configured to enter this mode, after auto or manuallly fade-out, or after manual de-activated. Won't send data to DMA. Won't gen data avail signals. Intf register can be programmed. Will change to Mode 3 or Mode 4 after manual ACT or Fade-in CMD. Will transfer to Mode 0 if DSTn_CTRL [DST_EN] is assigned 0. To support a new stream or, to continue the old stream after a pause. + */ +#define SMIX_DST_CH_ST_MODE_MASK (0x7U) +#define SMIX_DST_CH_ST_MODE_SHIFT (0U) +#define SMIX_DST_CH_ST_MODE_GET(x) (((uint32_t)(x) & SMIX_DST_CH_ST_MODE_MASK) >> SMIX_DST_CH_ST_MODE_SHIFT) + +/* Bitfield definition for register of struct array DST_CH: DATA */ +/* + * VAL (RO) + * + * Output data buffer + */ +#define SMIX_DST_CH_DATA_VAL_MASK (0xFFFFFFFFUL) +#define SMIX_DST_CH_DATA_VAL_SHIFT (0U) +#define SMIX_DST_CH_DATA_VAL_GET(x) (((uint32_t)(x) & SMIX_DST_CH_DATA_VAL_MASK) >> SMIX_DST_CH_DATA_VAL_SHIFT) + +/* Bitfield definition for register of struct array DST_CH: SOURCE_EN */ +/* + * VAL (RW) + * + * After enabled, Data needed req will be asserted. DMA can feed in data. The channel will join in the sum operation of mixer operation. + */ +#define SMIX_DST_CH_SOURCE_EN_VAL_MASK (0xFFU) +#define SMIX_DST_CH_SOURCE_EN_VAL_SHIFT (0U) +#define SMIX_DST_CH_SOURCE_EN_VAL_SET(x) (((uint32_t)(x) << SMIX_DST_CH_SOURCE_EN_VAL_SHIFT) & SMIX_DST_CH_SOURCE_EN_VAL_MASK) +#define SMIX_DST_CH_SOURCE_EN_VAL_GET(x) (((uint32_t)(x) & SMIX_DST_CH_SOURCE_EN_VAL_MASK) >> SMIX_DST_CH_SOURCE_EN_VAL_SHIFT) + +/* Bitfield definition for register of struct array DST_CH: SOURCE_ACT */ +/* + * VAL (WO) + * + * Manually Activate the channel + */ +#define SMIX_DST_CH_SOURCE_ACT_VAL_MASK (0xFFU) +#define SMIX_DST_CH_SOURCE_ACT_VAL_SHIFT (0U) +#define SMIX_DST_CH_SOURCE_ACT_VAL_SET(x) (((uint32_t)(x) << SMIX_DST_CH_SOURCE_ACT_VAL_SHIFT) & SMIX_DST_CH_SOURCE_ACT_VAL_MASK) +#define SMIX_DST_CH_SOURCE_ACT_VAL_GET(x) (((uint32_t)(x) & SMIX_DST_CH_SOURCE_ACT_VAL_MASK) >> SMIX_DST_CH_SOURCE_ACT_VAL_SHIFT) + +/* Bitfield definition for register of struct array DST_CH: SOURCE_DEACT */ +/* + * VAL (WO) + * + * Manually DeActivate the channel + */ +#define SMIX_DST_CH_SOURCE_DEACT_VAL_MASK (0xFFU) +#define SMIX_DST_CH_SOURCE_DEACT_VAL_SHIFT (0U) +#define SMIX_DST_CH_SOURCE_DEACT_VAL_SET(x) (((uint32_t)(x) << SMIX_DST_CH_SOURCE_DEACT_VAL_SHIFT) & SMIX_DST_CH_SOURCE_DEACT_VAL_MASK) +#define SMIX_DST_CH_SOURCE_DEACT_VAL_GET(x) (((uint32_t)(x) & SMIX_DST_CH_SOURCE_DEACT_VAL_MASK) >> SMIX_DST_CH_SOURCE_DEACT_VAL_SHIFT) + +/* Bitfield definition for register of struct array DST_CH: SOURCE_FADEIN_CTRL */ +/* + * AOP (RW) + * + * Asserted to start fade-in operation. When the amplification factors are stable, auto clear. + */ +#define SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_MASK (0xFFU) +#define SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_SHIFT (0U) +#define SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_SET(x) (((uint32_t)(x) << SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_SHIFT) & SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_MASK) +#define SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_GET(x) (((uint32_t)(x) & SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_MASK) >> SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_SHIFT) + +/* Bitfield definition for register of struct array DST_CH: DEACT_ST */ +/* + * DST_DEACT (RO) + * + * Asserted when in de-active mode + */ +#define SMIX_DST_CH_DEACT_ST_DST_DEACT_MASK (0x80000000UL) +#define SMIX_DST_CH_DEACT_ST_DST_DEACT_SHIFT (31U) +#define SMIX_DST_CH_DEACT_ST_DST_DEACT_GET(x) (((uint32_t)(x) & SMIX_DST_CH_DEACT_ST_DST_DEACT_MASK) >> SMIX_DST_CH_DEACT_ST_DST_DEACT_SHIFT) + +/* + * SRC_DEACT_ST (RO) + * + * Asserted when in de-active mode + */ +#define SMIX_DST_CH_DEACT_ST_SRC_DEACT_ST_MASK (0xFFU) +#define SMIX_DST_CH_DEACT_ST_SRC_DEACT_ST_SHIFT (0U) +#define SMIX_DST_CH_DEACT_ST_SRC_DEACT_ST_GET(x) (((uint32_t)(x) & SMIX_DST_CH_DEACT_ST_SRC_DEACT_ST_MASK) >> SMIX_DST_CH_DEACT_ST_SRC_DEACT_ST_SHIFT) + +/* Bitfield definition for register of struct array DST_CH: SOURCE_MFADEOUT_CTRL */ +/* + * OP (RW) + * + * Asserted to start fade-out operation. When the amplification factors are stable, auto clear. + */ +#define SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_MASK (0xFFU) +#define SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_SHIFT (0U) +#define SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_SET(x) (((uint32_t)(x) << SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_SHIFT) & SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_MASK) +#define SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_GET(x) (((uint32_t)(x) & SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_MASK) >> SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_SHIFT) + +/* Bitfield definition for register of struct array SOURCE_CH: CTRL */ +/* + * FIFO_RESET (RW) + * + * Asserted to reset FIFO pointer. Cleared to exit reset state. + */ +#define SMIX_SOURCE_CH_CTRL_FIFO_RESET_MASK (0x200000UL) +#define SMIX_SOURCE_CH_CTRL_FIFO_RESET_SHIFT (21U) +#define SMIX_SOURCE_CH_CTRL_FIFO_RESET_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_FIFO_RESET_SHIFT) & SMIX_SOURCE_CH_CTRL_FIFO_RESET_MASK) +#define SMIX_SOURCE_CH_CTRL_FIFO_RESET_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_FIFO_RESET_MASK) >> SMIX_SOURCE_CH_CTRL_FIFO_RESET_SHIFT) + +/* + * THRSH (RW) + * + * FIFO threshold for DMA or Int. <= will generate req. Must be greater or equal than 8. This threshold is also used to trgger the internal FIR operation. To avoid the reading and writing to the same address in the memory block, the threshold should greater than 4. + */ +#define SMIX_SOURCE_CH_CTRL_THRSH_MASK (0x1FE000UL) +#define SMIX_SOURCE_CH_CTRL_THRSH_SHIFT (13U) +#define SMIX_SOURCE_CH_CTRL_THRSH_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_THRSH_SHIFT) & SMIX_SOURCE_CH_CTRL_THRSH_MASK) +#define SMIX_SOURCE_CH_CTRL_THRSH_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_THRSH_MASK) >> SMIX_SOURCE_CH_CTRL_THRSH_SHIFT) + +/* + * CALSAT_INT_EN (RW) + * + * Cal Saturation IntEn + */ +#define SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_MASK (0x1000U) +#define SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_SHIFT (12U) +#define SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_SHIFT) & SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_MASK) +#define SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_MASK) >> SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_SHIFT) + +/* + * DN_INT_EN (RW) + * + * Data Needed IntEn + */ +#define SMIX_SOURCE_CH_CTRL_DN_INT_EN_MASK (0x800U) +#define SMIX_SOURCE_CH_CTRL_DN_INT_EN_SHIFT (11U) +#define SMIX_SOURCE_CH_CTRL_DN_INT_EN_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_DN_INT_EN_SHIFT) & SMIX_SOURCE_CH_CTRL_DN_INT_EN_MASK) +#define SMIX_SOURCE_CH_CTRL_DN_INT_EN_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_DN_INT_EN_MASK) >> SMIX_SOURCE_CH_CTRL_DN_INT_EN_SHIFT) + +/* + * SHFT_CTRL (RW) + * + * Shift operation after FIR + * 0: no shift (when no upsampling or up-sampling-by-2 or up-sampling-by-3) + * 1: left-shift-by-1 (when up-sampling-by-4 or up-sampling-by-6) + * 2: left-shift-by-1 (when up-sampling-by-8 or up-sampling-by-12) + * 7: /2 (when rate /2) + * Other n: shift-left-by-n, but not suggested to be used. + */ +#define SMIX_SOURCE_CH_CTRL_SHFT_CTRL_MASK (0x700U) +#define SMIX_SOURCE_CH_CTRL_SHFT_CTRL_SHIFT (8U) +#define SMIX_SOURCE_CH_CTRL_SHFT_CTRL_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_SHFT_CTRL_SHIFT) & SMIX_SOURCE_CH_CTRL_SHFT_CTRL_MASK) +#define SMIX_SOURCE_CH_CTRL_SHFT_CTRL_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_SHFT_CTRL_MASK) >> SMIX_SOURCE_CH_CTRL_SHFT_CTRL_SHIFT) + +/* + * AUTODEACTAFTERFADEOUT_EN (RW) + * + * Asserted to enter de-activated mode after fade-out done + */ +#define SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_MASK (0x80U) +#define SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_SHIFT (7U) +#define SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_SHIFT) & SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_MASK) +#define SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_MASK) >> SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_SHIFT) + +/* + * FADEOUT_DONE_IE (RW) + * + * Fade-Out interrupt enable + */ +#define SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_MASK (0x40U) +#define SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_SHIFT (6U) +#define SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_SHIFT) & SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_MASK) +#define SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_MASK) >> SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_SHIFT) + +/* + * RATECONV (RW) + * + * 0: no rate conversion + * 1: up-conversion x2 + * 2: up-conversion x3 + * 3: up-conversion x4 + * 4: up-conversion x6 + * 5: up-conversion x8 + * 6: up-conversion x12 + * 7: down-conversion /2 + */ +#define SMIX_SOURCE_CH_CTRL_RATECONV_MASK (0x7U) +#define SMIX_SOURCE_CH_CTRL_RATECONV_SHIFT (0U) +#define SMIX_SOURCE_CH_CTRL_RATECONV_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_RATECONV_SHIFT) & SMIX_SOURCE_CH_CTRL_RATECONV_MASK) +#define SMIX_SOURCE_CH_CTRL_RATECONV_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_RATECONV_MASK) >> SMIX_SOURCE_CH_CTRL_RATECONV_SHIFT) + +/* Bitfield definition for register of struct array SOURCE_CH: GAIN */ +/* + * VAL (RW) + * + * Unsigned Int, with 12 fractional bits. The top 3 bits are for shift. Same as SHFT_CTR[2:0]. + */ +#define SMIX_SOURCE_CH_GAIN_VAL_MASK (0x7FFFU) +#define SMIX_SOURCE_CH_GAIN_VAL_SHIFT (0U) +#define SMIX_SOURCE_CH_GAIN_VAL_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_GAIN_VAL_SHIFT) & SMIX_SOURCE_CH_GAIN_VAL_MASK) +#define SMIX_SOURCE_CH_GAIN_VAL_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_GAIN_VAL_MASK) >> SMIX_SOURCE_CH_GAIN_VAL_SHIFT) + +/* Bitfield definition for register of struct array SOURCE_CH: FADEIN */ +/* + * DELTA (RW) + * + * Fade -in confg. + */ +#define SMIX_SOURCE_CH_FADEIN_DELTA_MASK (0xFFFFFUL) +#define SMIX_SOURCE_CH_FADEIN_DELTA_SHIFT (0U) +#define SMIX_SOURCE_CH_FADEIN_DELTA_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_FADEIN_DELTA_SHIFT) & SMIX_SOURCE_CH_FADEIN_DELTA_MASK) +#define SMIX_SOURCE_CH_FADEIN_DELTA_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_FADEIN_DELTA_MASK) >> SMIX_SOURCE_CH_FADEIN_DELTA_SHIFT) + +/* Bitfield definition for register of struct array SOURCE_CH: FADEOUT */ +/* + * DELTA (RW) + * + * Fade out in 2^DELTA samples. Now DELTA can be at most 14。 + */ +#define SMIX_SOURCE_CH_FADEOUT_DELTA_MASK (0xFFFFFUL) +#define SMIX_SOURCE_CH_FADEOUT_DELTA_SHIFT (0U) +#define SMIX_SOURCE_CH_FADEOUT_DELTA_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_FADEOUT_DELTA_SHIFT) & SMIX_SOURCE_CH_FADEOUT_DELTA_MASK) +#define SMIX_SOURCE_CH_FADEOUT_DELTA_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_FADEOUT_DELTA_MASK) >> SMIX_SOURCE_CH_FADEOUT_DELTA_SHIFT) + +/* Bitfield definition for register of struct array SOURCE_CH: BUFSIZE */ +/* + * MAXIDX (RW) + * + * unit as 16-bits per sample. Zero means no length limit. = Act Len-1. + * The actual length is the up_rate*(input_data_length-4). + * If the filter processing is down-sampling, the value of up_rate above is 1. + * If the filter processing is up-sampling, the value of up_rate above is the up-sampling rate. + */ +#define SMIX_SOURCE_CH_BUFSIZE_MAXIDX_MASK (0xFFFFFFFFUL) +#define SMIX_SOURCE_CH_BUFSIZE_MAXIDX_SHIFT (0U) +#define SMIX_SOURCE_CH_BUFSIZE_MAXIDX_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_BUFSIZE_MAXIDX_SHIFT) & SMIX_SOURCE_CH_BUFSIZE_MAXIDX_MASK) +#define SMIX_SOURCE_CH_BUFSIZE_MAXIDX_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_BUFSIZE_MAXIDX_MASK) >> SMIX_SOURCE_CH_BUFSIZE_MAXIDX_SHIFT) + +/* Bitfield definition for register of struct array SOURCE_CH: ST */ +/* + * FIFO_FILLINGS (RO) + * + * The fillings of input FIFO. + */ +#define SMIX_SOURCE_CH_ST_FIFO_FILLINGS_MASK (0x7FC00UL) +#define SMIX_SOURCE_CH_ST_FIFO_FILLINGS_SHIFT (10U) +#define SMIX_SOURCE_CH_ST_FIFO_FILLINGS_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_ST_FIFO_FILLINGS_MASK) >> SMIX_SOURCE_CH_ST_FIFO_FILLINGS_SHIFT) + +/* + * FDOUT_DONE (W1C) + * + * Fade-Out Done. W1C + */ +#define SMIX_SOURCE_CH_ST_FDOUT_DONE_MASK (0x200U) +#define SMIX_SOURCE_CH_ST_FDOUT_DONE_SHIFT (9U) +#define SMIX_SOURCE_CH_ST_FDOUT_DONE_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_ST_FDOUT_DONE_SHIFT) & SMIX_SOURCE_CH_ST_FDOUT_DONE_MASK) +#define SMIX_SOURCE_CH_ST_FDOUT_DONE_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_ST_FDOUT_DONE_MASK) >> SMIX_SOURCE_CH_ST_FDOUT_DONE_SHIFT) + +/* + * CALSAT (W1C) + * + * Calculation saturation status. W1C + */ +#define SMIX_SOURCE_CH_ST_CALSAT_MASK (0x100U) +#define SMIX_SOURCE_CH_ST_CALSAT_SHIFT (8U) +#define SMIX_SOURCE_CH_ST_CALSAT_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_ST_CALSAT_SHIFT) & SMIX_SOURCE_CH_ST_CALSAT_MASK) +#define SMIX_SOURCE_CH_ST_CALSAT_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_ST_CALSAT_MASK) >> SMIX_SOURCE_CH_ST_CALSAT_SHIFT) + +/* + * DN (RO) + * + * Data needed flag + */ +#define SMIX_SOURCE_CH_ST_DN_MASK (0x80U) +#define SMIX_SOURCE_CH_ST_DN_SHIFT (7U) +#define SMIX_SOURCE_CH_ST_DN_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_ST_DN_MASK) >> SMIX_SOURCE_CH_ST_DN_SHIFT) + +/* + * FIRPHASE (RO) + * + * the poly phase counter + */ +#define SMIX_SOURCE_CH_ST_FIRPHASE_MASK (0x78U) +#define SMIX_SOURCE_CH_ST_FIRPHASE_SHIFT (3U) +#define SMIX_SOURCE_CH_ST_FIRPHASE_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_ST_FIRPHASE_MASK) >> SMIX_SOURCE_CH_ST_FIRPHASE_SHIFT) + +/* + * MODE (RO) + * + * The modes are: + * Mode 0: Disabled: after reset. Program the registers, and DSTx_SRC_EN[n] to enter Mode 1. + * Mode 1: Enabled but not activated: After Enabled. Data needed signal can send out, can receive DMA data. Will enter Mode 2 after manual ACT or Fade-in CMD + * Mode 2: Enabled and activated and buffer feed-in in progress: Can not be fade out. Will consume data from DMA. If not enter due to Fade-in CMD, will enter Mode 4, else enter Mode 3. This mode is used to make the channel in MIX only after initial data are ready, thus will not stall mix operation due to the lackness of data of this channel omly. + * Mode 3: Enabled and activated and fade-in in progress: Can not be fade out. Will consume data from DMA. + * Mode 4: Enabled and activated and done fade-in, no fade-out yet: Can be fade out. Will consume data from DMA. + * Mode 5: Enabled and activated and fade-out in progress: After faded out done. Will consume data from DMA. Will transfer to mode 6 or mode 7 depending on the SRCn_CTRL[AutoDeactAfterFadeOut_En] cfg + * Mode 6: Enabled and activated and faded-out: faded out is done. Will consume data from DMA. Will transfer to mode 7 if manual deactivated. + * Mode 7: Enabled and De-activated: If configured to enter this mode, after auto or manuallly fade-out, or after manual de-activated. Won't consume data from DMA. Won't gen data needed signals. Intf register can be programmed. Will change to Mode 2 after manual ACT or Fade-in CMD. Will transfer to Mode 0 if DSTx_SRC_EN[n] is assigned 0. To support a new stream or, to continue the old stream after a pause. + */ +#define SMIX_SOURCE_CH_ST_MODE_MASK (0x7U) +#define SMIX_SOURCE_CH_ST_MODE_SHIFT (0U) +#define SMIX_SOURCE_CH_ST_MODE_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_ST_MODE_MASK) >> SMIX_SOURCE_CH_ST_MODE_SHIFT) + +/* Bitfield definition for register of struct array SOURCE_CH: DATA */ +/* + * VAL (WO) + * + * Data input register + */ +#define SMIX_SOURCE_CH_DATA_VAL_MASK (0xFFFFFFFFUL) +#define SMIX_SOURCE_CH_DATA_VAL_SHIFT (0U) +#define SMIX_SOURCE_CH_DATA_VAL_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_DATA_VAL_SHIFT) & SMIX_SOURCE_CH_DATA_VAL_MASK) +#define SMIX_SOURCE_CH_DATA_VAL_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_DATA_VAL_MASK) >> SMIX_SOURCE_CH_DATA_VAL_SHIFT) + + + +/* DMA_CH register group index macro definition */ +#define SMIX_DMA_CH_0 (0UL) +#define SMIX_DMA_CH_1 (1UL) +#define SMIX_DMA_CH_2 (2UL) +#define SMIX_DMA_CH_3 (3UL) +#define SMIX_DMA_CH_4 (4UL) +#define SMIX_DMA_CH_5 (5UL) +#define SMIX_DMA_CH_6 (6UL) +#define SMIX_DMA_CH_7 (7UL) +#define SMIX_DMA_CH_8 (8UL) +#define SMIX_DMA_CH_9 (9UL) +#define SMIX_DMA_CH_10 (10UL) +#define SMIX_DMA_CH_11 (11UL) +#define SMIX_DMA_CH_12 (12UL) +#define SMIX_DMA_CH_13 (13UL) +#define SMIX_DMA_CH_14 (14UL) +#define SMIX_DMA_CH_15 (15UL) +#define SMIX_DMA_CH_16 (16UL) +#define SMIX_DMA_CH_17 (17UL) +#define SMIX_DMA_CH_18 (18UL) +#define SMIX_DMA_CH_19 (19UL) +#define SMIX_DMA_CH_20 (20UL) +#define SMIX_DMA_CH_21 (21UL) +#define SMIX_DMA_CH_22 (22UL) +#define SMIX_DMA_CH_23 (23UL) +#define SMIX_DMA_CH_24 (24UL) +#define SMIX_DMA_CH_25 (25UL) + +/* DST_CH register group index macro definition */ +#define SMIX_DST_CH_0 (0UL) +#define SMIX_DST_CH_1 (1UL) + +/* SOURCE_CH register group index macro definition */ +#define SMIX_SOURCE_CH_0 (0UL) +#define SMIX_SOURCE_CH_1 (1UL) +#define SMIX_SOURCE_CH_2 (2UL) +#define SMIX_SOURCE_CH_3 (3UL) +#define SMIX_SOURCE_CH_4 (4UL) +#define SMIX_SOURCE_CH_5 (5UL) +#define SMIX_SOURCE_CH_6 (6UL) +#define SMIX_SOURCE_CH_7 (7UL) +#define SMIX_SOURCE_CH_8 (8UL) +#define SMIX_SOURCE_CH_9 (9UL) +#define SMIX_SOURCE_CH_10 (10UL) +#define SMIX_SOURCE_CH_11 (11UL) +#define SMIX_SOURCE_CH_12 (12UL) +#define SMIX_SOURCE_CH_13 (13UL) + + +#endif /* HPM_SMIX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_spi_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_spi_regs.h index 392c0b8a0bd..a37f79c1e4e 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_spi_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_spi_regs.h @@ -10,9 +10,13 @@ #define HPM_SPI_H typedef struct { - __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */ + __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */ + __RW uint32_t WR_TRANS_CNT; /* 0x4: Transfer count for write data */ + __RW uint32_t RD_TRANS_CNT; /* 0x8: Transfer count for read data */ + __R uint8_t RESERVED1[4]; /* 0xC - 0xF: Reserved */ __RW uint32_t TRANSFMT; /* 0x10: Transfer Format Register */ - __R uint8_t RESERVED1[12]; /* 0x14 - 0x1F: Reserved */ + __RW uint32_t DIRECTIO; /* 0x14: Direct IO Control Register */ + __R uint8_t RESERVED2[8]; /* 0x18 - 0x1F: Reserved */ __RW uint32_t TRANSCTRL; /* 0x20: Transfer Control Register */ __RW uint32_t CMD; /* 0x24: Command Register */ __RW uint32_t ADDR; /* 0x28: Address Register */ @@ -22,14 +26,46 @@ typedef struct { __RW uint32_t INTREN; /* 0x38: Interrupt Enable Register */ __W uint32_t INTRST; /* 0x3C: Interrupt Status Register */ __RW uint32_t TIMING; /* 0x40: Interface Timing Register */ - __R uint8_t RESERVED2[28]; /* 0x44 - 0x5F: Reserved */ + __R uint8_t RESERVED3[28]; /* 0x44 - 0x5F: Reserved */ __RW uint32_t SLVST; /* 0x60: Slave Status Register */ __R uint32_t SLVDATACNT; /* 0x64: Slave Data Count Register */ - __R uint8_t RESERVED3[20]; /* 0x68 - 0x7B: Reserved */ + __R uint32_t SLVDATAWCNT; /* 0x68: WCnt */ + __R uint32_t SLVDATARCNT; /* 0x6C: RCnt */ + __R uint8_t RESERVED4[12]; /* 0x70 - 0x7B: Reserved */ __R uint32_t CONFIG; /* 0x7C: Configuration Register */ } SPI_Type; +/* Bitfield definition for register: WR_TRANS_CNT */ +/* + * WRTRANCNT (RW) + * + * Transfer count for write data + * WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). + * WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. + * The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. + * For TransMode 0, WrTranCnt must be equal to RdTranCnt. + */ +#define SPI_WR_TRANS_CNT_WRTRANCNT_MASK (0xFFFFFFFFUL) +#define SPI_WR_TRANS_CNT_WRTRANCNT_SHIFT (0U) +#define SPI_WR_TRANS_CNT_WRTRANCNT_SET(x) (((uint32_t)(x) << SPI_WR_TRANS_CNT_WRTRANCNT_SHIFT) & SPI_WR_TRANS_CNT_WRTRANCNT_MASK) +#define SPI_WR_TRANS_CNT_WRTRANCNT_GET(x) (((uint32_t)(x) & SPI_WR_TRANS_CNT_WRTRANCNT_MASK) >> SPI_WR_TRANS_CNT_WRTRANCNT_SHIFT) + +/* Bitfield definition for register: RD_TRANS_CNT */ +/* + * RDTRANCNT (RW) + * + * Transfer count for read data + * RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). + * RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. + * The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. + * For TransMode 0, WrTranCnt must equal RdTranCnt. + */ +#define SPI_RD_TRANS_CNT_RDTRANCNT_MASK (0xFFFFFFFFUL) +#define SPI_RD_TRANS_CNT_RDTRANCNT_SHIFT (0U) +#define SPI_RD_TRANS_CNT_RDTRANCNT_SET(x) (((uint32_t)(x) << SPI_RD_TRANS_CNT_RDTRANCNT_SHIFT) & SPI_RD_TRANS_CNT_RDTRANCNT_MASK) +#define SPI_RD_TRANS_CNT_RDTRANCNT_GET(x) (((uint32_t)(x) & SPI_RD_TRANS_CNT_RDTRANCNT_MASK) >> SPI_RD_TRANS_CNT_RDTRANCNT_SHIFT) + /* Bitfield definition for register: TRANSFMT */ /* * ADDRLEN (RW) @@ -128,6 +164,193 @@ typedef struct { #define SPI_TRANSFMT_CPHA_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_CPHA_SHIFT) & SPI_TRANSFMT_CPHA_MASK) #define SPI_TRANSFMT_CPHA_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_CPHA_MASK) >> SPI_TRANSFMT_CPHA_SHIFT) +/* Bitfield definition for register: DIRECTIO */ +/* + * DIRECTIOEN (RW) + * + * Enable Direct IO + * 0x0: Disable + * 0x1: Enable + */ +#define SPI_DIRECTIO_DIRECTIOEN_MASK (0x1000000UL) +#define SPI_DIRECTIO_DIRECTIOEN_SHIFT (24U) +#define SPI_DIRECTIO_DIRECTIOEN_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_DIRECTIOEN_SHIFT) & SPI_DIRECTIO_DIRECTIOEN_MASK) +#define SPI_DIRECTIO_DIRECTIOEN_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_DIRECTIOEN_MASK) >> SPI_DIRECTIO_DIRECTIOEN_SHIFT) + +/* + * HOLD_OE (RW) + * + * Output enable for the SPI Flash hold signal + */ +#define SPI_DIRECTIO_HOLD_OE_MASK (0x200000UL) +#define SPI_DIRECTIO_HOLD_OE_SHIFT (21U) +#define SPI_DIRECTIO_HOLD_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_HOLD_OE_SHIFT) & SPI_DIRECTIO_HOLD_OE_MASK) +#define SPI_DIRECTIO_HOLD_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_HOLD_OE_MASK) >> SPI_DIRECTIO_HOLD_OE_SHIFT) + +/* + * WP_OE (RW) + * + * Output enable for the SPI Flash write protect signal + */ +#define SPI_DIRECTIO_WP_OE_MASK (0x100000UL) +#define SPI_DIRECTIO_WP_OE_SHIFT (20U) +#define SPI_DIRECTIO_WP_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_WP_OE_SHIFT) & SPI_DIRECTIO_WP_OE_MASK) +#define SPI_DIRECTIO_WP_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_WP_OE_MASK) >> SPI_DIRECTIO_WP_OE_SHIFT) + +/* + * MISO_OE (RW) + * + * Output enable fo the SPI MISO signal + */ +#define SPI_DIRECTIO_MISO_OE_MASK (0x80000UL) +#define SPI_DIRECTIO_MISO_OE_SHIFT (19U) +#define SPI_DIRECTIO_MISO_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_MISO_OE_SHIFT) & SPI_DIRECTIO_MISO_OE_MASK) +#define SPI_DIRECTIO_MISO_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MISO_OE_MASK) >> SPI_DIRECTIO_MISO_OE_SHIFT) + +/* + * MOSI_OE (RW) + * + * Output enable for the SPI MOSI signal + */ +#define SPI_DIRECTIO_MOSI_OE_MASK (0x40000UL) +#define SPI_DIRECTIO_MOSI_OE_SHIFT (18U) +#define SPI_DIRECTIO_MOSI_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_MOSI_OE_SHIFT) & SPI_DIRECTIO_MOSI_OE_MASK) +#define SPI_DIRECTIO_MOSI_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MOSI_OE_MASK) >> SPI_DIRECTIO_MOSI_OE_SHIFT) + +/* + * SCLK_OE (RW) + * + * Output enable for the SPI SCLK signal + */ +#define SPI_DIRECTIO_SCLK_OE_MASK (0x20000UL) +#define SPI_DIRECTIO_SCLK_OE_SHIFT (17U) +#define SPI_DIRECTIO_SCLK_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_SCLK_OE_SHIFT) & SPI_DIRECTIO_SCLK_OE_MASK) +#define SPI_DIRECTIO_SCLK_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_SCLK_OE_MASK) >> SPI_DIRECTIO_SCLK_OE_SHIFT) + +/* + * CS_OE (RW) + * + * Output enable for SPI CS (chip select) signal + */ +#define SPI_DIRECTIO_CS_OE_MASK (0x10000UL) +#define SPI_DIRECTIO_CS_OE_SHIFT (16U) +#define SPI_DIRECTIO_CS_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_CS_OE_SHIFT) & SPI_DIRECTIO_CS_OE_MASK) +#define SPI_DIRECTIO_CS_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_CS_OE_MASK) >> SPI_DIRECTIO_CS_OE_SHIFT) + +/* + * HOLD_O (RW) + * + * Output value for the SPI Flash hold signal + */ +#define SPI_DIRECTIO_HOLD_O_MASK (0x2000U) +#define SPI_DIRECTIO_HOLD_O_SHIFT (13U) +#define SPI_DIRECTIO_HOLD_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_HOLD_O_SHIFT) & SPI_DIRECTIO_HOLD_O_MASK) +#define SPI_DIRECTIO_HOLD_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_HOLD_O_MASK) >> SPI_DIRECTIO_HOLD_O_SHIFT) + +/* + * WP_O (RW) + * + * Output value for the SPI Flash write protect signal + */ +#define SPI_DIRECTIO_WP_O_MASK (0x1000U) +#define SPI_DIRECTIO_WP_O_SHIFT (12U) +#define SPI_DIRECTIO_WP_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_WP_O_SHIFT) & SPI_DIRECTIO_WP_O_MASK) +#define SPI_DIRECTIO_WP_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_WP_O_MASK) >> SPI_DIRECTIO_WP_O_SHIFT) + +/* + * MISO_O (RW) + * + * Output value for the SPI MISO signal + */ +#define SPI_DIRECTIO_MISO_O_MASK (0x800U) +#define SPI_DIRECTIO_MISO_O_SHIFT (11U) +#define SPI_DIRECTIO_MISO_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_MISO_O_SHIFT) & SPI_DIRECTIO_MISO_O_MASK) +#define SPI_DIRECTIO_MISO_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MISO_O_MASK) >> SPI_DIRECTIO_MISO_O_SHIFT) + +/* + * MOSI_O (RW) + * + * Output value for the SPI MOSI signal + */ +#define SPI_DIRECTIO_MOSI_O_MASK (0x400U) +#define SPI_DIRECTIO_MOSI_O_SHIFT (10U) +#define SPI_DIRECTIO_MOSI_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_MOSI_O_SHIFT) & SPI_DIRECTIO_MOSI_O_MASK) +#define SPI_DIRECTIO_MOSI_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MOSI_O_MASK) >> SPI_DIRECTIO_MOSI_O_SHIFT) + +/* + * SCLK_O (RW) + * + * Output value for the SPI SCLK signal + */ +#define SPI_DIRECTIO_SCLK_O_MASK (0x200U) +#define SPI_DIRECTIO_SCLK_O_SHIFT (9U) +#define SPI_DIRECTIO_SCLK_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_SCLK_O_SHIFT) & SPI_DIRECTIO_SCLK_O_MASK) +#define SPI_DIRECTIO_SCLK_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_SCLK_O_MASK) >> SPI_DIRECTIO_SCLK_O_SHIFT) + +/* + * CS_O (RW) + * + * Output value for the SPI CS (chip select) signal + */ +#define SPI_DIRECTIO_CS_O_MASK (0x100U) +#define SPI_DIRECTIO_CS_O_SHIFT (8U) +#define SPI_DIRECTIO_CS_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_CS_O_SHIFT) & SPI_DIRECTIO_CS_O_MASK) +#define SPI_DIRECTIO_CS_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_CS_O_MASK) >> SPI_DIRECTIO_CS_O_SHIFT) + +/* + * HOLD_I (RO) + * + * Status of the SPI Flash hold signal + */ +#define SPI_DIRECTIO_HOLD_I_MASK (0x20U) +#define SPI_DIRECTIO_HOLD_I_SHIFT (5U) +#define SPI_DIRECTIO_HOLD_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_HOLD_I_MASK) >> SPI_DIRECTIO_HOLD_I_SHIFT) + +/* + * WP_I (RO) + * + * Status of the SPI Flash write protect signal + */ +#define SPI_DIRECTIO_WP_I_MASK (0x10U) +#define SPI_DIRECTIO_WP_I_SHIFT (4U) +#define SPI_DIRECTIO_WP_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_WP_I_MASK) >> SPI_DIRECTIO_WP_I_SHIFT) + +/* + * MISO_I (RO) + * + * Status of the SPI MISO signal + */ +#define SPI_DIRECTIO_MISO_I_MASK (0x8U) +#define SPI_DIRECTIO_MISO_I_SHIFT (3U) +#define SPI_DIRECTIO_MISO_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MISO_I_MASK) >> SPI_DIRECTIO_MISO_I_SHIFT) + +/* + * MOSI_I (RO) + * + * Status of the SPI MOSI signal + */ +#define SPI_DIRECTIO_MOSI_I_MASK (0x4U) +#define SPI_DIRECTIO_MOSI_I_SHIFT (2U) +#define SPI_DIRECTIO_MOSI_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MOSI_I_MASK) >> SPI_DIRECTIO_MOSI_I_SHIFT) + +/* + * SCLK_I (RO) + * + * Status of the SPI SCLK signal + */ +#define SPI_DIRECTIO_SCLK_I_MASK (0x2U) +#define SPI_DIRECTIO_SCLK_I_SHIFT (1U) +#define SPI_DIRECTIO_SCLK_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_SCLK_I_MASK) >> SPI_DIRECTIO_SCLK_I_SHIFT) + +/* + * CS_I (RO) + * + * Status of the SPI CS (chip select) signal + */ +#define SPI_DIRECTIO_CS_I_MASK (0x1U) +#define SPI_DIRECTIO_CS_I_SHIFT (0U) +#define SPI_DIRECTIO_CS_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_CS_I_MASK) >> SPI_DIRECTIO_CS_I_SHIFT) + /* Bitfield definition for register: TRANSCTRL */ /* * SLVDATAONLY (RW) @@ -320,6 +543,15 @@ typedef struct { #define SPI_DATA_DATA_GET(x) (((uint32_t)(x) & SPI_DATA_DATA_MASK) >> SPI_DATA_DATA_SHIFT) /* Bitfield definition for register: CTRL */ +/* + * CS_EN (RW) + * + */ +#define SPI_CTRL_CS_EN_MASK (0xF000000UL) +#define SPI_CTRL_CS_EN_SHIFT (24U) +#define SPI_CTRL_CS_EN_SET(x) (((uint32_t)(x) << SPI_CTRL_CS_EN_SHIFT) & SPI_CTRL_CS_EN_MASK) +#define SPI_CTRL_CS_EN_GET(x) (((uint32_t)(x) & SPI_CTRL_CS_EN_MASK) >> SPI_CTRL_CS_EN_SHIFT) + /* * TXTHRES (RW) * @@ -718,6 +950,24 @@ typedef struct { #define SPI_SLVDATACNT_RCNT_SHIFT (0U) #define SPI_SLVDATACNT_RCNT_GET(x) (((uint32_t)(x) & SPI_SLVDATACNT_RCNT_MASK) >> SPI_SLVDATACNT_RCNT_SHIFT) +/* Bitfield definition for register: SLVDATAWCNT */ +/* + * VAL (RO) + * + */ +#define SPI_SLVDATAWCNT_VAL_MASK (0xFFFFFFFFUL) +#define SPI_SLVDATAWCNT_VAL_SHIFT (0U) +#define SPI_SLVDATAWCNT_VAL_GET(x) (((uint32_t)(x) & SPI_SLVDATAWCNT_VAL_MASK) >> SPI_SLVDATAWCNT_VAL_SHIFT) + +/* Bitfield definition for register: SLVDATARCNT */ +/* + * VAL (RO) + * + */ +#define SPI_SLVDATARCNT_VAL_MASK (0xFFFFFFFFUL) +#define SPI_SLVDATARCNT_VAL_SHIFT (0U) +#define SPI_SLVDATARCNT_VAL_GET(x) (((uint32_t)(x) & SPI_SLVDATARCNT_VAL_MASK) >> SPI_SLVDATARCNT_VAL_SHIFT) + /* Bitfield definition for register: CONFIG */ /* * SLAVE (RO) @@ -781,4 +1031,4 @@ typedef struct { -#endif /* HPM_SPI_H */ \ No newline at end of file +#endif /* HPM_SPI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_synt_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_synt_regs.h index 936d2bda0ad..698b3498cab 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_synt_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_synt_regs.h @@ -12,10 +12,10 @@ typedef struct { __RW uint32_t GCR; /* 0x0: Global control register */ __RW uint32_t RLD; /* 0x4: Counter reload register */ - __RW uint32_t SYNT_NEW; /* 0x8: sync timer new value register */ + __RW uint32_t TIMESTAMP_NEW; /* 0x8: timestamp new value register */ __R uint32_t CNT; /* 0xC: Counter */ - __R uint32_t SYNT_SAVE; /* 0x10: sync timer trig save value */ - __R uint32_t SYNT_READ; /* 0x14: sync timer read value */ + __R uint32_t TIMESTAMP_SAV; /* 0x10: timestamp trig save value */ + __R uint32_t TIMESTAMP_CUR; /* 0x14: timestamp read value */ __R uint8_t RESERVED0[8]; /* 0x18 - 0x1F: Reserved */ __RW uint32_t CMP[4]; /* 0x20 - 0x2C: Comparator */ } SYNT_Type; @@ -23,74 +23,74 @@ typedef struct { /* Bitfield definition for register: GCR */ /* - * SYNC_TIMER_INC (WO) + * TIMESTAMP_INC_NEW (WO) * - * set to increase the sync timer with new_value, auto clr + * set to increase the timesamp with new value, auto clr */ -#define SYNT_GCR_SYNC_TIMER_INC_MASK (0x80000000UL) -#define SYNT_GCR_SYNC_TIMER_INC_SHIFT (31U) -#define SYNT_GCR_SYNC_TIMER_INC_SET(x) (((uint32_t)(x) << SYNT_GCR_SYNC_TIMER_INC_SHIFT) & SYNT_GCR_SYNC_TIMER_INC_MASK) -#define SYNT_GCR_SYNC_TIMER_INC_GET(x) (((uint32_t)(x) & SYNT_GCR_SYNC_TIMER_INC_MASK) >> SYNT_GCR_SYNC_TIMER_INC_SHIFT) +#define SYNT_GCR_TIMESTAMP_INC_NEW_MASK (0x80000000UL) +#define SYNT_GCR_TIMESTAMP_INC_NEW_SHIFT (31U) +#define SYNT_GCR_TIMESTAMP_INC_NEW_SET(x) (((uint32_t)(x) << SYNT_GCR_TIMESTAMP_INC_NEW_SHIFT) & SYNT_GCR_TIMESTAMP_INC_NEW_MASK) +#define SYNT_GCR_TIMESTAMP_INC_NEW_GET(x) (((uint32_t)(x) & SYNT_GCR_TIMESTAMP_INC_NEW_MASK) >> SYNT_GCR_TIMESTAMP_INC_NEW_SHIFT) /* - * SYNC_TIMER_DEC (WO) + * TIMESTAMP_DEC_NEW (WO) * - * set to decrease the sync timer with new_value, auto clr + * set to decrease the timesamp with new value, auto clr */ -#define SYNT_GCR_SYNC_TIMER_DEC_MASK (0x40000000UL) -#define SYNT_GCR_SYNC_TIMER_DEC_SHIFT (30U) -#define SYNT_GCR_SYNC_TIMER_DEC_SET(x) (((uint32_t)(x) << SYNT_GCR_SYNC_TIMER_DEC_SHIFT) & SYNT_GCR_SYNC_TIMER_DEC_MASK) -#define SYNT_GCR_SYNC_TIMER_DEC_GET(x) (((uint32_t)(x) & SYNT_GCR_SYNC_TIMER_DEC_MASK) >> SYNT_GCR_SYNC_TIMER_DEC_SHIFT) +#define SYNT_GCR_TIMESTAMP_DEC_NEW_MASK (0x40000000UL) +#define SYNT_GCR_TIMESTAMP_DEC_NEW_SHIFT (30U) +#define SYNT_GCR_TIMESTAMP_DEC_NEW_SET(x) (((uint32_t)(x) << SYNT_GCR_TIMESTAMP_DEC_NEW_SHIFT) & SYNT_GCR_TIMESTAMP_DEC_NEW_MASK) +#define SYNT_GCR_TIMESTAMP_DEC_NEW_GET(x) (((uint32_t)(x) & SYNT_GCR_TIMESTAMP_DEC_NEW_MASK) >> SYNT_GCR_TIMESTAMP_DEC_NEW_SHIFT) /* - * SYNC_TIMER_NEW (WO) + * TIMESTAMP_SET_NEW (WO) * - * set the sync timer to new_value, auto clr + * set the timesamp to new value, auto clr */ -#define SYNT_GCR_SYNC_TIMER_NEW_MASK (0x20000000UL) -#define SYNT_GCR_SYNC_TIMER_NEW_SHIFT (29U) -#define SYNT_GCR_SYNC_TIMER_NEW_SET(x) (((uint32_t)(x) << SYNT_GCR_SYNC_TIMER_NEW_SHIFT) & SYNT_GCR_SYNC_TIMER_NEW_MASK) -#define SYNT_GCR_SYNC_TIMER_NEW_GET(x) (((uint32_t)(x) & SYNT_GCR_SYNC_TIMER_NEW_MASK) >> SYNT_GCR_SYNC_TIMER_NEW_SHIFT) +#define SYNT_GCR_TIMESTAMP_SET_NEW_MASK (0x20000000UL) +#define SYNT_GCR_TIMESTAMP_SET_NEW_SHIFT (29U) +#define SYNT_GCR_TIMESTAMP_SET_NEW_SET(x) (((uint32_t)(x) << SYNT_GCR_TIMESTAMP_SET_NEW_SHIFT) & SYNT_GCR_TIMESTAMP_SET_NEW_MASK) +#define SYNT_GCR_TIMESTAMP_SET_NEW_GET(x) (((uint32_t)(x) & SYNT_GCR_TIMESTAMP_SET_NEW_MASK) >> SYNT_GCR_TIMESTAMP_SET_NEW_SHIFT) /* - * SYNC_TIMER_RESET (WO) + * TIMESTAMP_RESET (WO) * - * reset sync timer to 0, auto clr + * reset timesamp to 0, auto clr */ -#define SYNT_GCR_SYNC_TIMER_RESET_MASK (0x10000000UL) -#define SYNT_GCR_SYNC_TIMER_RESET_SHIFT (28U) -#define SYNT_GCR_SYNC_TIMER_RESET_SET(x) (((uint32_t)(x) << SYNT_GCR_SYNC_TIMER_RESET_SHIFT) & SYNT_GCR_SYNC_TIMER_RESET_MASK) -#define SYNT_GCR_SYNC_TIMER_RESET_GET(x) (((uint32_t)(x) & SYNT_GCR_SYNC_TIMER_RESET_MASK) >> SYNT_GCR_SYNC_TIMER_RESET_SHIFT) +#define SYNT_GCR_TIMESTAMP_RESET_MASK (0x10000000UL) +#define SYNT_GCR_TIMESTAMP_RESET_SHIFT (28U) +#define SYNT_GCR_TIMESTAMP_RESET_SET(x) (((uint32_t)(x) << SYNT_GCR_TIMESTAMP_RESET_SHIFT) & SYNT_GCR_TIMESTAMP_RESET_MASK) +#define SYNT_GCR_TIMESTAMP_RESET_GET(x) (((uint32_t)(x) & SYNT_GCR_TIMESTAMP_RESET_MASK) >> SYNT_GCR_TIMESTAMP_RESET_SHIFT) /* - * SYNC_TIMER_STOPEN (RW) + * TIMESTAMP_DEBUG_EN (RW) * - * set to enable cpu_debug_mode to stop the sync timer + * set to enable cpu_debug_mode to stop the timesamp */ -#define SYNT_GCR_SYNC_TIMER_STOPEN_MASK (0x20U) -#define SYNT_GCR_SYNC_TIMER_STOPEN_SHIFT (5U) -#define SYNT_GCR_SYNC_TIMER_STOPEN_SET(x) (((uint32_t)(x) << SYNT_GCR_SYNC_TIMER_STOPEN_SHIFT) & SYNT_GCR_SYNC_TIMER_STOPEN_MASK) -#define SYNT_GCR_SYNC_TIMER_STOPEN_GET(x) (((uint32_t)(x) & SYNT_GCR_SYNC_TIMER_STOPEN_MASK) >> SYNT_GCR_SYNC_TIMER_STOPEN_SHIFT) +#define SYNT_GCR_TIMESTAMP_DEBUG_EN_MASK (0x20U) +#define SYNT_GCR_TIMESTAMP_DEBUG_EN_SHIFT (5U) +#define SYNT_GCR_TIMESTAMP_DEBUG_EN_SET(x) (((uint32_t)(x) << SYNT_GCR_TIMESTAMP_DEBUG_EN_SHIFT) & SYNT_GCR_TIMESTAMP_DEBUG_EN_MASK) +#define SYNT_GCR_TIMESTAMP_DEBUG_EN_GET(x) (((uint32_t)(x) & SYNT_GCR_TIMESTAMP_DEBUG_EN_MASK) >> SYNT_GCR_TIMESTAMP_DEBUG_EN_SHIFT) /* - * SYNC_TIMER_ENABLE (RW) + * TIMESTAMP_ENABLE (RW) * - * set to enable the sync timer, clr to stop + * set to enable the timesamp , clr to stop */ -#define SYNT_GCR_SYNC_TIMER_ENABLE_MASK (0x10U) -#define SYNT_GCR_SYNC_TIMER_ENABLE_SHIFT (4U) -#define SYNT_GCR_SYNC_TIMER_ENABLE_SET(x) (((uint32_t)(x) << SYNT_GCR_SYNC_TIMER_ENABLE_SHIFT) & SYNT_GCR_SYNC_TIMER_ENABLE_MASK) -#define SYNT_GCR_SYNC_TIMER_ENABLE_GET(x) (((uint32_t)(x) & SYNT_GCR_SYNC_TIMER_ENABLE_MASK) >> SYNT_GCR_SYNC_TIMER_ENABLE_SHIFT) +#define SYNT_GCR_TIMESTAMP_ENABLE_MASK (0x10U) +#define SYNT_GCR_TIMESTAMP_ENABLE_SHIFT (4U) +#define SYNT_GCR_TIMESTAMP_ENABLE_SET(x) (((uint32_t)(x) << SYNT_GCR_TIMESTAMP_ENABLE_SHIFT) & SYNT_GCR_TIMESTAMP_ENABLE_MASK) +#define SYNT_GCR_TIMESTAMP_ENABLE_GET(x) (((uint32_t)(x) & SYNT_GCR_TIMESTAMP_ENABLE_MASK) >> SYNT_GCR_TIMESTAMP_ENABLE_SHIFT) /* - * STOPEN (RW) + * COUNTER_DEBUG_EN (RW) * * set to enable cpu_debug_mode to stop the counter */ -#define SYNT_GCR_STOPEN_MASK (0x4U) -#define SYNT_GCR_STOPEN_SHIFT (2U) -#define SYNT_GCR_STOPEN_SET(x) (((uint32_t)(x) << SYNT_GCR_STOPEN_SHIFT) & SYNT_GCR_STOPEN_MASK) -#define SYNT_GCR_STOPEN_GET(x) (((uint32_t)(x) & SYNT_GCR_STOPEN_MASK) >> SYNT_GCR_STOPEN_SHIFT) +#define SYNT_GCR_COUNTER_DEBUG_EN_MASK (0x4U) +#define SYNT_GCR_COUNTER_DEBUG_EN_SHIFT (2U) +#define SYNT_GCR_COUNTER_DEBUG_EN_SET(x) (((uint32_t)(x) << SYNT_GCR_COUNTER_DEBUG_EN_SHIFT) & SYNT_GCR_COUNTER_DEBUG_EN_MASK) +#define SYNT_GCR_COUNTER_DEBUG_EN_GET(x) (((uint32_t)(x) & SYNT_GCR_COUNTER_DEBUG_EN_MASK) >> SYNT_GCR_COUNTER_DEBUG_EN_SHIFT) /* * CRST (RW) @@ -123,16 +123,16 @@ typedef struct { #define SYNT_RLD_RLD_SET(x) (((uint32_t)(x) << SYNT_RLD_RLD_SHIFT) & SYNT_RLD_RLD_MASK) #define SYNT_RLD_RLD_GET(x) (((uint32_t)(x) & SYNT_RLD_RLD_MASK) >> SYNT_RLD_RLD_SHIFT) -/* Bitfield definition for register: SYNT_NEW */ +/* Bitfield definition for register: TIMESTAMP_NEW */ /* - * NEW_VALUE (RW) + * VALUE (RW) * - * new value for sync timer, can be used as update/inc/dec + * new value for timesamp , can be used as set/inc/dec */ -#define SYNT_SYNT_NEW_NEW_VALUE_MASK (0xFFFFFFFFUL) -#define SYNT_SYNT_NEW_NEW_VALUE_SHIFT (0U) -#define SYNT_SYNT_NEW_NEW_VALUE_SET(x) (((uint32_t)(x) << SYNT_SYNT_NEW_NEW_VALUE_SHIFT) & SYNT_SYNT_NEW_NEW_VALUE_MASK) -#define SYNT_SYNT_NEW_NEW_VALUE_GET(x) (((uint32_t)(x) & SYNT_SYNT_NEW_NEW_VALUE_MASK) >> SYNT_SYNT_NEW_NEW_VALUE_SHIFT) +#define SYNT_TIMESTAMP_NEW_VALUE_MASK (0xFFFFFFFFUL) +#define SYNT_TIMESTAMP_NEW_VALUE_SHIFT (0U) +#define SYNT_TIMESTAMP_NEW_VALUE_SET(x) (((uint32_t)(x) << SYNT_TIMESTAMP_NEW_VALUE_SHIFT) & SYNT_TIMESTAMP_NEW_VALUE_MASK) +#define SYNT_TIMESTAMP_NEW_VALUE_GET(x) (((uint32_t)(x) & SYNT_TIMESTAMP_NEW_VALUE_MASK) >> SYNT_TIMESTAMP_NEW_VALUE_SHIFT) /* Bitfield definition for register: CNT */ /* @@ -144,25 +144,25 @@ typedef struct { #define SYNT_CNT_CNT_SHIFT (0U) #define SYNT_CNT_CNT_GET(x) (((uint32_t)(x) & SYNT_CNT_CNT_MASK) >> SYNT_CNT_CNT_SHIFT) -/* Bitfield definition for register: SYNT_SAVE */ +/* Bitfield definition for register: TIMESTAMP_SAV */ /* - * TIME_SAVE (RO) + * VALUE (RO) * - * use the trigger to save sync timer here + * use the trigger to save timesamp here */ -#define SYNT_SYNT_SAVE_TIME_SAVE_MASK (0xFFFFFFFFUL) -#define SYNT_SYNT_SAVE_TIME_SAVE_SHIFT (0U) -#define SYNT_SYNT_SAVE_TIME_SAVE_GET(x) (((uint32_t)(x) & SYNT_SYNT_SAVE_TIME_SAVE_MASK) >> SYNT_SYNT_SAVE_TIME_SAVE_SHIFT) +#define SYNT_TIMESTAMP_SAV_VALUE_MASK (0xFFFFFFFFUL) +#define SYNT_TIMESTAMP_SAV_VALUE_SHIFT (0U) +#define SYNT_TIMESTAMP_SAV_VALUE_GET(x) (((uint32_t)(x) & SYNT_TIMESTAMP_SAV_VALUE_MASK) >> SYNT_TIMESTAMP_SAV_VALUE_SHIFT) -/* Bitfield definition for register: SYNT_READ */ +/* Bitfield definition for register: TIMESTAMP_CUR */ /* - * SYNC_TIME (RO) + * VALUE (RO) * - * current sync timer value + * current timesamp value */ -#define SYNT_SYNT_READ_SYNC_TIME_MASK (0xFFFFFFFFUL) -#define SYNT_SYNT_READ_SYNC_TIME_SHIFT (0U) -#define SYNT_SYNT_READ_SYNC_TIME_GET(x) (((uint32_t)(x) & SYNT_SYNT_READ_SYNC_TIME_MASK) >> SYNT_SYNT_READ_SYNC_TIME_SHIFT) +#define SYNT_TIMESTAMP_CUR_VALUE_MASK (0xFFFFFFFFUL) +#define SYNT_TIMESTAMP_CUR_VALUE_SHIFT (0U) +#define SYNT_TIMESTAMP_CUR_VALUE_GET(x) (((uint32_t)(x) & SYNT_TIMESTAMP_CUR_VALUE_MASK) >> SYNT_TIMESTAMP_CUR_VALUE_SHIFT) /* Bitfield definition for register array: CMP */ /* diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_uart_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_uart_regs.h index aafd95775f3..d2966c87bc5 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_uart_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_uart_regs.h @@ -35,6 +35,7 @@ typedef struct { __RW uint32_t MCR; /* 0x30: Modem Control Register ( */ __R uint32_t LSR; /* 0x34: Line Status Register */ __R uint32_t MSR; /* 0x38: Modem Status Register */ + __RW uint32_t GPR; /* 0x3C: GPR Register */ } UART_Type; @@ -205,7 +206,7 @@ typedef struct { /* * RXIDLE_FLAG (W1C) * - * UART RX IDLE Flag, assert after rxd low and then rx idle timeout, write one clear + * UART RX IDLE Flag, assert after rxd high and then rx idle timeout, write one clear * 0 - UART RX is busy * 1 - UART RX is idle */ @@ -217,7 +218,7 @@ typedef struct { /* * TXIDLE_FLAG (W1C) * - * UART TX IDLE Flag, assert after txd low and then tx idle timeout, write one clear + * UART TX IDLE Flag, assert after txd high and then tx idle timeout, write one clear * 0 - UART TX is busy * 1 - UART TX is idle */ @@ -301,7 +302,7 @@ typedef struct { * Over-sample control * The value must be an even number; any odd value * writes to this field will be converted to an even value. - * OSC=0: The over-sample ratio is 32 + * OSC=0: reserved * OSC<=8: The over-sample ratio is 8 * 8 < OSC< 32: The over sample ratio is OSC */ @@ -1026,6 +1027,17 @@ typedef struct { #define UART_MSR_DCTS_SHIFT (0U) #define UART_MSR_DCTS_GET(x) (((uint32_t)(x) & UART_MSR_DCTS_MASK) >> UART_MSR_DCTS_SHIFT) +/* Bitfield definition for register: GPR */ +/* + * DATA (RW) + * + * An one-byte storage register + */ +#define UART_GPR_DATA_MASK (0xFFU) +#define UART_GPR_DATA_SHIFT (0U) +#define UART_GPR_DATA_SET(x) (((uint32_t)(x) << UART_GPR_DATA_SHIFT) & UART_GPR_DATA_MASK) +#define UART_GPR_DATA_GET(x) (((uint32_t)(x) & UART_GPR_DATA_MASK) >> UART_GPR_DATA_SHIFT) + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_usb_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_usb_regs.h index 8f18e72f3d9..47bcf4691c1 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_usb_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_usb_regs.h @@ -46,13 +46,12 @@ typedef struct { __RW uint32_t ENDPTFLUSH; /* 0x1B4: Endpoint Flush Register */ __R uint32_t ENDPTSTAT; /* 0x1B8: Endpoint Status Register */ __RW uint32_t ENDPTCOMPLETE; /* 0x1BC: Endpoint Complete Register */ - __RW uint32_t ENDPTCTRL[8]; /* 0x1C0 - 0x1DC: Endpoint Control0 Register... Endpoint Control7 Register */ - __R uint8_t RESERVED7[32]; /* 0x1E0 - 0x1FF: Reserved */ + __RW uint32_t ENDPTCTRL[16]; /* 0x1C0 - 0x1FC: Endpoint Control0 Register... Endpoint Control7 Register */ __RW uint32_t OTG_CTRL0; /* 0x200: */ - __R uint8_t RESERVED8[12]; /* 0x204 - 0x20F: Reserved */ + __R uint8_t RESERVED7[12]; /* 0x204 - 0x20F: Reserved */ __RW uint32_t PHY_CTRL0; /* 0x210: */ __RW uint32_t PHY_CTRL1; /* 0x214: */ - __R uint8_t RESERVED9[8]; /* 0x218 - 0x21F: Reserved */ + __R uint8_t RESERVED8[8]; /* 0x218 - 0x21F: Reserved */ __RW uint32_t TOP_STATUS; /* 0x220: */ __RW uint32_t PHY_STATUS; /* 0x224: */ } USB_Type; @@ -1022,7 +1021,7 @@ typedef struct { * device sends a NAK handshake on a received IN token for the corresponding endpoint. * Bit [N] - Endpoint #[N], N is 0-7 */ -#define USB_ENDPTNAK_EPTN_MASK (0xFF0000UL) +#define USB_ENDPTNAK_EPTN_MASK (0xFFFF0000UL) #define USB_ENDPTNAK_EPTN_SHIFT (16U) #define USB_ENDPTNAK_EPTN_SET(x) (((uint32_t)(x) << USB_ENDPTNAK_EPTN_SHIFT) & USB_ENDPTNAK_EPTN_MASK) #define USB_ENDPTNAK_EPTN_GET(x) (((uint32_t)(x) & USB_ENDPTNAK_EPTN_MASK) >> USB_ENDPTNAK_EPTN_SHIFT) @@ -1036,7 +1035,7 @@ typedef struct { * device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. * Bit [N] - Endpoint #[N], N is 0-7 */ -#define USB_ENDPTNAK_EPRN_MASK (0xFFU) +#define USB_ENDPTNAK_EPRN_MASK (0xFFFFU) #define USB_ENDPTNAK_EPRN_SHIFT (0U) #define USB_ENDPTNAK_EPRN_SET(x) (((uint32_t)(x) << USB_ENDPTNAK_EPRN_SHIFT) & USB_ENDPTNAK_EPRN_MASK) #define USB_ENDPTNAK_EPRN_GET(x) (((uint32_t)(x) & USB_ENDPTNAK_EPRN_MASK) >> USB_ENDPTNAK_EPRN_SHIFT) @@ -1051,7 +1050,7 @@ typedef struct { * corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. * Bit [N] - Endpoint #[N], N is 0-7 */ -#define USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000UL) +#define USB_ENDPTNAKEN_EPTNE_MASK (0xFFFF0000UL) #define USB_ENDPTNAKEN_EPTNE_SHIFT (16U) #define USB_ENDPTNAKEN_EPTNE_SET(x) (((uint32_t)(x) << USB_ENDPTNAKEN_EPTNE_SHIFT) & USB_ENDPTNAKEN_EPTNE_MASK) #define USB_ENDPTNAKEN_EPTNE_GET(x) (((uint32_t)(x) & USB_ENDPTNAKEN_EPTNE_MASK) >> USB_ENDPTNAKEN_EPTNE_SHIFT) @@ -1065,7 +1064,7 @@ typedef struct { * corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. * Bit [N] - Endpoint #[N], N is 0-7 */ -#define USB_ENDPTNAKEN_EPRNE_MASK (0xFFU) +#define USB_ENDPTNAKEN_EPRNE_MASK (0xFFFFU) #define USB_ENDPTNAKEN_EPRNE_SHIFT (0U) #define USB_ENDPTNAKEN_EPRNE_SET(x) (((uint32_t)(x) << USB_ENDPTNAKEN_EPRNE_SHIFT) & USB_ENDPTNAKEN_EPRNE_MASK) #define USB_ENDPTNAKEN_EPRNE_GET(x) (((uint32_t)(x) & USB_ENDPTNAKEN_EPRNE_MASK) >> USB_ENDPTNAKEN_EPRNE_SHIFT) @@ -1654,7 +1653,7 @@ typedef struct { * The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. * This register is only used in device mode. */ -#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFU) +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SET(x) (((uint32_t)(x) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_GET(x) (((uint32_t)(x) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) >> USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) @@ -1674,7 +1673,7 @@ typedef struct { * is retired, and the dQH is updated. * PETB[N] - Endpoint #N, N is in 0..7 */ -#define USB_ENDPTPRIME_PETB_MASK (0xFF0000UL) +#define USB_ENDPTPRIME_PETB_MASK (0xFFFF0000UL) #define USB_ENDPTPRIME_PETB_SHIFT (16U) #define USB_ENDPTPRIME_PETB_SET(x) (((uint32_t)(x) << USB_ENDPTPRIME_PETB_SHIFT) & USB_ENDPTPRIME_PETB_MASK) #define USB_ENDPTPRIME_PETB_GET(x) (((uint32_t)(x) & USB_ENDPTPRIME_PETB_MASK) >> USB_ENDPTPRIME_PETB_SHIFT) @@ -1691,7 +1690,7 @@ typedef struct { * is retired, and the dQH is updated. * PERB[N] - Endpoint #N, N is in 0..7 */ -#define USB_ENDPTPRIME_PERB_MASK (0xFFU) +#define USB_ENDPTPRIME_PERB_MASK (0xFFFFU) #define USB_ENDPTPRIME_PERB_SHIFT (0U) #define USB_ENDPTPRIME_PERB_SET(x) (((uint32_t)(x) << USB_ENDPTPRIME_PERB_SHIFT) & USB_ENDPTPRIME_PERB_MASK) #define USB_ENDPTPRIME_PERB_GET(x) (((uint32_t)(x) & USB_ENDPTPRIME_PERB_MASK) >> USB_ENDPTPRIME_PERB_SHIFT) @@ -1706,7 +1705,7 @@ typedef struct { * Hardware clears this register after the endpoint flush operation is successful. * FETB[N] - Endpoint #N, N is in 0..7 */ -#define USB_ENDPTFLUSH_FETB_MASK (0xFF0000UL) +#define USB_ENDPTFLUSH_FETB_MASK (0xFFFF0000UL) #define USB_ENDPTFLUSH_FETB_SHIFT (16U) #define USB_ENDPTFLUSH_FETB_SET(x) (((uint32_t)(x) << USB_ENDPTFLUSH_FETB_SHIFT) & USB_ENDPTFLUSH_FETB_MASK) #define USB_ENDPTFLUSH_FETB_GET(x) (((uint32_t)(x) & USB_ENDPTFLUSH_FETB_MASK) >> USB_ENDPTFLUSH_FETB_SHIFT) @@ -1720,7 +1719,7 @@ typedef struct { * Hardware clears this register after the endpoint flush operation is successful. * FERB[N] - Endpoint #N, N is in 0..7 */ -#define USB_ENDPTFLUSH_FERB_MASK (0xFFU) +#define USB_ENDPTFLUSH_FERB_MASK (0xFFFFU) #define USB_ENDPTFLUSH_FERB_SHIFT (0U) #define USB_ENDPTFLUSH_FERB_SET(x) (((uint32_t)(x) << USB_ENDPTFLUSH_FERB_SHIFT) & USB_ENDPTFLUSH_FERB_MASK) #define USB_ENDPTFLUSH_FERB_GET(x) (((uint32_t)(x) & USB_ENDPTFLUSH_FERB_MASK) >> USB_ENDPTFLUSH_FERB_SHIFT) @@ -1738,7 +1737,7 @@ typedef struct { * NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. * ETBR[N] - Endpoint #N, N is in 0..7 */ -#define USB_ENDPTSTAT_ETBR_MASK (0xFF0000UL) +#define USB_ENDPTSTAT_ETBR_MASK (0xFFFF0000UL) #define USB_ENDPTSTAT_ETBR_SHIFT (16U) #define USB_ENDPTSTAT_ETBR_GET(x) (((uint32_t)(x) & USB_ENDPTSTAT_ETBR_MASK) >> USB_ENDPTSTAT_ETBR_SHIFT) @@ -1756,7 +1755,7 @@ typedef struct { * when a dTD is retired, and the dQH is updated. * ERBR[N] - Endpoint #N, N is in 0..7 */ -#define USB_ENDPTSTAT_ERBR_MASK (0xFFU) +#define USB_ENDPTSTAT_ERBR_MASK (0xFFFFU) #define USB_ENDPTSTAT_ERBR_SHIFT (0U) #define USB_ENDPTSTAT_ERBR_GET(x) (((uint32_t)(x) & USB_ENDPTSTAT_ERBR_MASK) >> USB_ENDPTSTAT_ERBR_SHIFT) @@ -1769,7 +1768,7 @@ typedef struct { * If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. * ETCE[N] - Endpoint #N, N is in 0..7 */ -#define USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000UL) +#define USB_ENDPTCOMPLETE_ETCE_MASK (0xFFFF0000UL) #define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U) #define USB_ENDPTCOMPLETE_ETCE_SET(x) (((uint32_t)(x) << USB_ENDPTCOMPLETE_ETCE_SHIFT) & USB_ENDPTCOMPLETE_ETCE_MASK) #define USB_ENDPTCOMPLETE_ETCE_GET(x) (((uint32_t)(x) & USB_ENDPTCOMPLETE_ETCE_MASK) >> USB_ENDPTCOMPLETE_ETCE_SHIFT) @@ -1784,7 +1783,7 @@ typedef struct { * USBINT . Writing one clears the corresponding bit in this register. * ERCE[N] - Endpoint #N, N is in 0..7 */ -#define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU) +#define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFFFU) #define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U) #define USB_ENDPTCOMPLETE_ERCE_SET(x) (((uint32_t)(x) << USB_ENDPTCOMPLETE_ERCE_SHIFT) & USB_ENDPTCOMPLETE_ERCE_MASK) #define USB_ENDPTCOMPLETE_ERCE_GET(x) (((uint32_t)(x) & USB_ENDPTCOMPLETE_ERCE_MASK) >> USB_ENDPTCOMPLETE_ERCE_SHIFT) @@ -2192,6 +2191,14 @@ typedef struct { #define USB_ENDPTCTRL_ENDPTCTRL5 (5UL) #define USB_ENDPTCTRL_ENDPTCTRL6 (6UL) #define USB_ENDPTCTRL_ENDPTCTRL7 (7UL) +#define USB_ENDPTCTRL_ENDPTCTRL8 (8UL) +#define USB_ENDPTCTRL_ENDPTCTRL9 (9UL) +#define USB_ENDPTCTRL_ENDPTCTRL10 (10UL) +#define USB_ENDPTCTRL_ENDPTCTRL11 (11UL) +#define USB_ENDPTCTRL_ENDPTCTRL12 (12UL) +#define USB_ENDPTCTRL_ENDPTCTRL13 (13UL) +#define USB_ENDPTCTRL_ENDPTCTRL14 (14UL) +#define USB_ENDPTCTRL_ENDPTCTRL15 (15UL) #endif /* HPM_USB_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_crc32.c b/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_crc32.c new file mode 100644 index 00000000000..c1134d4d343 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_crc32.c @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_crc32.h" + + +uint32_t crc32(const uint8_t *buf, uint32_t len) +{ + uint8_t i; + uint32_t crc = 0xFFFFFFFF; + while (len--) { + crc ^= *buf++; + for (i = 0; i < 8; ++i) { + if (crc & 1) + crc = (crc >> 1) ^ 0xEDB88320; + else + crc = (crc >> 1); + } + } + + return ~crc; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_crc32.h b/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_crc32.h new file mode 100644 index 00000000000..82245e8c43d --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_crc32.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_CRC32_H +#define _HPM_CRC32_H + +#include +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +uint32_t crc32(const uint8_t *buf, uint32_t len); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_ffssi.c b/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_ffssi.c index 75ca411ff1f..513c5a85e61 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_ffssi.c +++ b/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_ffssi.c @@ -9,7 +9,7 @@ int __ffssi2(int x) { - int i = 0; + uint32_t i = 0; if (!x) { return 0; }